1 files changed, 5 insertions, 10 deletions

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index bee84c554932..b316dfb6f6c7 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -819,6 +819,7 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
         [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
         [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
         [tegra_clk_cec] = { .dt_id = TEGRA30_CLK_CEC, .present = true },
+        [tegra_clk_emc] = { .dt_id = TEGRA30_CLK_EMC, .present = true },
 };
 
 static const char *pll_e_parents[] = { "pll_ref", "pll_p" };
@@ -843,8 +844,7 @@ static void __init tegra30_pll_init(void)
 
         /* PLLM */
         clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
-                            CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
-                            &pll_m_params, NULL);
+                            CLK_SET_RATE_GATE, &pll_m_params, NULL);
         clks[TEGRA30_CLK_PLL_M] = clk;
 
         /* PLLM_OUT1 */
@@ -852,7 +852,7 @@ static void __init tegra30_pll_init(void)
                                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
                                 8, 8, 1, NULL);
         clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
-                                clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
+                                clk_base + PLLM_OUT, 1, 0,
                                 CLK_SET_RATE_PARENT, 0, NULL);
         clks[TEGRA30_CLK_PLL_M_OUT1] = clk;
 
@@ -990,7 +990,7 @@ static void __init tegra30_super_clk_init(void)
         /* SCLK */
         clk = tegra_clk_register_super_mux("sclk", sclk_parents,
                                   ARRAY_SIZE(sclk_parents),
-                                  CLK_SET_RATE_PARENT,
+                                  CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
                                   clk_base + SCLK_BURST_POLICY,
                                   0, 4, 0, 0, NULL);
         clks[TEGRA30_CLK_SCLK] = clk;
@@ -1060,9 +1060,6 @@ static void __init tegra30_periph_clk_init(void)
                                CLK_SET_RATE_NO_REPARENT,
                                clk_base + CLK_SOURCE_EMC,
                                30, 2, 0, &emc_lock);
-        clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
-                                    57, periph_clk_enb_refcnt);
-        clks[TEGRA30_CLK_EMC] = clk;
 
         clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
                                     &emc_lock);
@@ -1252,10 +1249,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
         { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
         { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
         { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
-        { TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1 },
-        { TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1 },
         { TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 },
-        { TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1 },
         { TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1 },
         { TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0 },
         { TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0 },
@@ -1272,6 +1266,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
         { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 },
         { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },
         { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 },
+        { TEGRA30_CLK_VDE, TEGRA30_CLK_CLK_MAX, 600000000, 0 },
         /* must be the last entry */
         { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
 };