1 files changed, 11 insertions, 13 deletions

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index cbd5a2e5c569..0ee56dd04cec 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -576,6 +576,7 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
         [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true },
         [tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true },
         [tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true },
+        [tegra_clk_emc] = { .dt_id = TEGRA20_CLK_EMC, .present = true },
 };
 
 static unsigned long tegra20_clk_measure_input_freq(void)
@@ -651,8 +652,7 @@ static void tegra20_pll_init(void)
 
         /* PLLM */
         clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,
-                            CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
-                            &pll_m_params, NULL);
+                            CLK_SET_RATE_GATE, &pll_m_params, NULL);
         clks[TEGRA20_CLK_PLL_M] = clk;
 
         /* PLLM_OUT1 */
@@ -660,7 +660,7 @@ static void tegra20_pll_init(void)
                                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
                                 8, 8, 1, NULL);
         clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
-                                clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
+                                clk_base + PLLM_OUT, 1, 0,
                                 CLK_SET_RATE_PARENT, 0, NULL);
         clks[TEGRA20_CLK_PLL_M_OUT1] = clk;
 
@@ -723,7 +723,8 @@ static void tegra20_super_clk_init(void)
 
         /* SCLK */
         clk = tegra_clk_register_super_mux("sclk", sclk_parents,
-                              ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT,
+                              ARRAY_SIZE(sclk_parents),
+                              CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
                               clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
         clks[TEGRA20_CLK_SCLK] = clk;
 
@@ -814,9 +815,6 @@ static void __init tegra20_periph_clk_init(void)
                                CLK_SET_RATE_NO_REPARENT,
                                clk_base + CLK_SOURCE_EMC,
                                30, 2, 0, &emc_lock);
-        clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
-                                    57, periph_clk_enb_refcnt);
-        clks[TEGRA20_CLK_EMC] = clk;
 
         clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
                                     &emc_lock);
@@ -1019,13 +1017,12 @@ static struct tegra_clk_init_table init_table[] __initdata = {
         { TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1 },
         { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 },
         { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 },
-        { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1 },
-        { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 216000000, 1 },
-        { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1 },
-        { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
-        { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1 },
+        { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 0 },
+        { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 240000000, 0 },
+        { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 240000000, 0 },
+        { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 240000000, 0 },
+        { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 0 },
         { TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 },
-        { TEGRA20_CLK_EMC, TEGRA20_CLK_CLK_MAX, 0, 1 },
         { TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
         { TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0 },
         { TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0 },
@@ -1051,6 +1048,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
         { TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0 },
         { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },
         { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },
+        { TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 300000000, 0 },
         /* must be the last entry */
         { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
 };