1 files changed, 4 insertions, 5 deletions

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index e81ea5b11577..50088e976611 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1089,8 +1089,7 @@ static void __init tegra124_pll_init(void __iomem *clk_base,
 
         /* PLLM */
         clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
-                             CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
-                             &pll_m_params, NULL);
+                             CLK_SET_RATE_GATE, &pll_m_params, NULL);
         clk_register_clkdev(clk, "pll_m", NULL);
         clks[TEGRA124_CLK_PLL_M] = clk;
 
@@ -1099,7 +1098,7 @@ static void __init tegra124_pll_init(void __iomem *clk_base,
                                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
                                 8, 8, 1, NULL);
         clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
-                                clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
+                                clk_base + PLLM_OUT, 1, 0,
                                 CLK_SET_RATE_PARENT, 0, NULL);
         clk_register_clkdev(clk, "pll_m_out1", NULL);
         clks[TEGRA124_CLK_PLL_M_OUT1] = clk;
@@ -1268,11 +1267,11 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
         { TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
         { TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
         { TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
-        { TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0 },
+        { TEGRA124_CLK_VDE, TEGRA124_CLK_CLK_MAX, 600000000, 0 },
         { TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1 },
         { TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0 },
         { TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0 },
-        { TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1 },
+        { TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 0 },
         { TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1 },
         { TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1 },
         { TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0 },