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Diffstat (limited to 'drivers/clk/renesas/r8a7795-cpg-mssr.c')
-rw-r--r--drivers/clk/renesas/r8a7795-cpg-mssr.c72
1 files changed, 35 insertions, 37 deletions
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index a85dd50e8911..119c02440726 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset 3 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
3 * 4 *
@@ -6,10 +7,6 @@
6 * Based on clk-rcar-gen3.c 7 * Based on clk-rcar-gen3.c
7 * 8 *
8 * Copyright (C) 2015 Renesas Electronics Corp. 9 * Copyright (C) 2015 Renesas Electronics Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 */ 10 */
14 11
15#include <linux/device.h> 12#include <linux/device.h>
@@ -73,6 +70,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
73 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), 70 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
74 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), 71 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
75 72
73 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
74
76 /* Core Clock Outputs */ 75 /* Core Clock Outputs */
77 DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), 76 DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
78 DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), 77 DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
@@ -111,8 +110,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
111 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014), 110 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
112 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250), 111 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
113 112
114 DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), 113 DEF_GEN3_OSC("osc", R8A7795_CLK_OSC, CLK_EXTAL, 8),
115 DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
116 114
117 DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), 115 DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
118}; 116};
@@ -283,25 +281,25 @@ static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
283 */ 281 */
284 282
285/* 283/*
286 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 284 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
287 * 14 13 19 17 (MHz) 285 * 14 13 19 17 (MHz)
288 *------------------------------------------------------------------- 286 *-------------------------------------------------------------------------
289 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 287 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
290 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 288 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
291 * 0 0 1 0 Prohibited setting 289 * 0 0 1 0 Prohibited setting
292 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 290 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
293 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 291 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
294 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 292 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
295 * 0 1 1 0 Prohibited setting 293 * 0 1 1 0 Prohibited setting
296 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 294 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
297 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 295 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
298 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 296 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
299 * 1 0 1 0 Prohibited setting 297 * 1 0 1 0 Prohibited setting
300 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 298 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
301 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 299 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
302 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 300 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
303 * 1 1 1 0 Prohibited setting 301 * 1 1 1 0 Prohibited setting
304 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 302 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
305 */ 303 */
306#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ 304#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
307 (((md) & BIT(13)) >> 11) | \ 305 (((md) & BIT(13)) >> 11) | \
@@ -309,23 +307,23 @@ static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
309 (((md) & BIT(17)) >> 17)) 307 (((md) & BIT(17)) >> 17))
310 308
311static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { 309static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
312 /* EXTAL div PLL1 mult/div PLL3 mult/div */ 310 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
313 { 1, 192, 1, 192, 1, }, 311 { 1, 192, 1, 192, 1, 16, },
314 { 1, 192, 1, 128, 1, }, 312 { 1, 192, 1, 128, 1, 16, },
315 { 0, /* Prohibited setting */ }, 313 { 0, /* Prohibited setting */ },
316 { 1, 192, 1, 192, 1, }, 314 { 1, 192, 1, 192, 1, 16, },
317 { 1, 160, 1, 160, 1, }, 315 { 1, 160, 1, 160, 1, 19, },
318 { 1, 160, 1, 106, 1, }, 316 { 1, 160, 1, 106, 1, 19, },
319 { 0, /* Prohibited setting */ }, 317 { 0, /* Prohibited setting */ },
320 { 1, 160, 1, 160, 1, }, 318 { 1, 160, 1, 160, 1, 19, },
321 { 1, 128, 1, 128, 1, }, 319 { 1, 128, 1, 128, 1, 24, },
322 { 1, 128, 1, 84, 1, }, 320 { 1, 128, 1, 84, 1, 24, },
323 { 0, /* Prohibited setting */ }, 321 { 0, /* Prohibited setting */ },
324 { 1, 128, 1, 128, 1, }, 322 { 1, 128, 1, 128, 1, 24, },
325 { 2, 192, 1, 192, 1, }, 323 { 2, 192, 1, 192, 1, 32, },
326 { 2, 192, 1, 128, 1, }, 324 { 2, 192, 1, 128, 1, 32, },
327 { 0, /* Prohibited setting */ }, 325 { 0, /* Prohibited setting */ },
328 { 2, 192, 1, 192, 1, }, 326 { 2, 192, 1, 192, 1, 32, },
329}; 327};
330 328
331static const struct soc_device_attribute r8a7795es1[] __initconst = { 329static const struct soc_device_attribute r8a7795es1[] __initconst = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-26 11:08:01 -0400