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path: root/drivers/clk/renesas/r8a774a1-cpg-mssr.c
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Diffstat (limited to 'drivers/clk/renesas/r8a774a1-cpg-mssr.c')
-rw-r--r--drivers/clk/renesas/r8a774a1-cpg-mssr.c323
1 files changed, 323 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
new file mode 100644
index 000000000000..b0da34217bdf
--- /dev/null
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -0,0 +1,323 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * r8a774a1 Clock Pulse Generator / Module Standby and Software Reset
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 *
7 * Based on r8a7796-cpg-mssr.c
8 *
9 * Copyright (C) 2016 Glider bvba
10 */
11
12#include <linux/device.h>
13#include <linux/init.h>
14#include <linux/kernel.h>
15#include <linux/soc/renesas/rcar-rst.h>
16
17#include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
18
19#include "renesas-cpg-mssr.h"
20#include "rcar-gen3-cpg.h"
21
22enum clk_ids {
23 /* Core Clock Outputs exported to DT */
24 LAST_DT_CORE_CLK = R8A774A1_CLK_OSC,
25
26 /* External Input Clocks */
27 CLK_EXTAL,
28 CLK_EXTALR,
29
30 /* Internal Core Clocks */
31 CLK_MAIN,
32 CLK_PLL0,
33 CLK_PLL1,
34 CLK_PLL2,
35 CLK_PLL3,
36 CLK_PLL4,
37 CLK_PLL1_DIV2,
38 CLK_PLL1_DIV4,
39 CLK_S0,
40 CLK_S1,
41 CLK_S2,
42 CLK_S3,
43 CLK_SDSRC,
44 CLK_RINT,
45
46 /* Module Clocks */
47 MOD_CLK_BASE
48};
49
50static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
51 /* External Clock Inputs */
52 DEF_INPUT("extal", CLK_EXTAL),
53 DEF_INPUT("extalr", CLK_EXTALR),
54
55 /* Internal Core Clocks */
56 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
57 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
58 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
59 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
60 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
61 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
62
63 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
64 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
65 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
66 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
67 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
68 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
69 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
70
71 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
72
73 /* Core Clock Outputs */
74 DEF_BASE("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
75 DEF_BASE("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
76 DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
77 DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
78 DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
79 DEF_FIXED("zx", R8A774A1_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
80 DEF_FIXED("s0d1", R8A774A1_CLK_S0D1, CLK_S0, 1, 1),
81 DEF_FIXED("s0d2", R8A774A1_CLK_S0D2, CLK_S0, 2, 1),
82 DEF_FIXED("s0d3", R8A774A1_CLK_S0D3, CLK_S0, 3, 1),
83 DEF_FIXED("s0d4", R8A774A1_CLK_S0D4, CLK_S0, 4, 1),
84 DEF_FIXED("s0d6", R8A774A1_CLK_S0D6, CLK_S0, 6, 1),
85 DEF_FIXED("s0d8", R8A774A1_CLK_S0D8, CLK_S0, 8, 1),
86 DEF_FIXED("s0d12", R8A774A1_CLK_S0D12, CLK_S0, 12, 1),
87 DEF_FIXED("s1d2", R8A774A1_CLK_S1D2, CLK_S1, 2, 1),
88 DEF_FIXED("s1d4", R8A774A1_CLK_S1D4, CLK_S1, 4, 1),
89 DEF_FIXED("s2d1", R8A774A1_CLK_S2D1, CLK_S2, 1, 1),
90 DEF_FIXED("s2d2", R8A774A1_CLK_S2D2, CLK_S2, 2, 1),
91 DEF_FIXED("s2d4", R8A774A1_CLK_S2D4, CLK_S2, 4, 1),
92 DEF_FIXED("s3d1", R8A774A1_CLK_S3D1, CLK_S3, 1, 1),
93 DEF_FIXED("s3d2", R8A774A1_CLK_S3D2, CLK_S3, 2, 1),
94 DEF_FIXED("s3d4", R8A774A1_CLK_S3D4, CLK_S3, 4, 1),
95
96 DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, CLK_SDSRC, 0x074),
97 DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078),
98 DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268),
99 DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c),
100
101 DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
102 DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1),
103
104 DEF_DIV6P1("csi0", R8A774A1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
105 DEF_DIV6P1("mso", R8A774A1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
106 DEF_DIV6P1("hdmi", R8A774A1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
107
108 DEF_GEN3_OSC("osc", R8A774A1_CLK_OSC, CLK_EXTAL, 8),
109
110 DEF_BASE("r", R8A774A1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
111};
112
113static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
114 DEF_MOD("fdp1-0", 119, R8A774A1_CLK_S0D1),
115 DEF_MOD("scif5", 202, R8A774A1_CLK_S3D4),
116 DEF_MOD("scif4", 203, R8A774A1_CLK_S3D4),
117 DEF_MOD("scif3", 204, R8A774A1_CLK_S3D4),
118 DEF_MOD("scif1", 206, R8A774A1_CLK_S3D4),
119 DEF_MOD("scif0", 207, R8A774A1_CLK_S3D4),
120 DEF_MOD("msiof3", 208, R8A774A1_CLK_MSO),
121 DEF_MOD("msiof2", 209, R8A774A1_CLK_MSO),
122 DEF_MOD("msiof1", 210, R8A774A1_CLK_MSO),
123 DEF_MOD("msiof0", 211, R8A774A1_CLK_MSO),
124 DEF_MOD("sys-dmac2", 217, R8A774A1_CLK_S0D3),
125 DEF_MOD("sys-dmac1", 218, R8A774A1_CLK_S0D3),
126 DEF_MOD("sys-dmac0", 219, R8A774A1_CLK_S0D3),
127 DEF_MOD("cmt3", 300, R8A774A1_CLK_R),
128 DEF_MOD("cmt2", 301, R8A774A1_CLK_R),
129 DEF_MOD("cmt1", 302, R8A774A1_CLK_R),
130 DEF_MOD("cmt0", 303, R8A774A1_CLK_R),
131 DEF_MOD("scif2", 310, R8A774A1_CLK_S3D4),
132 DEF_MOD("sdif3", 311, R8A774A1_CLK_SD3),
133 DEF_MOD("sdif2", 312, R8A774A1_CLK_SD2),
134 DEF_MOD("sdif1", 313, R8A774A1_CLK_SD1),
135 DEF_MOD("sdif0", 314, R8A774A1_CLK_SD0),
136 DEF_MOD("pcie1", 318, R8A774A1_CLK_S3D1),
137 DEF_MOD("pcie0", 319, R8A774A1_CLK_S3D1),
138 DEF_MOD("usb3-if0", 328, R8A774A1_CLK_S3D1),
139 DEF_MOD("usb-dmac0", 330, R8A774A1_CLK_S3D1),
140 DEF_MOD("usb-dmac1", 331, R8A774A1_CLK_S3D1),
141 DEF_MOD("rwdt", 402, R8A774A1_CLK_R),
142 DEF_MOD("intc-ex", 407, R8A774A1_CLK_CP),
143 DEF_MOD("intc-ap", 408, R8A774A1_CLK_S0D3),
144 DEF_MOD("audmac1", 501, R8A774A1_CLK_S0D3),
145 DEF_MOD("audmac0", 502, R8A774A1_CLK_S0D3),
146 DEF_MOD("hscif4", 516, R8A774A1_CLK_S3D1),
147 DEF_MOD("hscif3", 517, R8A774A1_CLK_S3D1),
148 DEF_MOD("hscif2", 518, R8A774A1_CLK_S3D1),
149 DEF_MOD("hscif1", 519, R8A774A1_CLK_S3D1),
150 DEF_MOD("hscif0", 520, R8A774A1_CLK_S3D1),
151 DEF_MOD("thermal", 522, R8A774A1_CLK_CP),
152 DEF_MOD("pwm", 523, R8A774A1_CLK_S0D12),
153 DEF_MOD("fcpvd2", 601, R8A774A1_CLK_S0D2),
154 DEF_MOD("fcpvd1", 602, R8A774A1_CLK_S0D2),
155 DEF_MOD("fcpvd0", 603, R8A774A1_CLK_S0D2),
156 DEF_MOD("fcpvb0", 607, R8A774A1_CLK_S0D1),
157 DEF_MOD("fcpvi0", 611, R8A774A1_CLK_S0D1),
158 DEF_MOD("fcpf0", 615, R8A774A1_CLK_S0D1),
159 DEF_MOD("fcpci0", 617, R8A774A1_CLK_S0D2),
160 DEF_MOD("fcpcs", 619, R8A774A1_CLK_S0D2),
161 DEF_MOD("vspd2", 621, R8A774A1_CLK_S0D2),
162 DEF_MOD("vspd1", 622, R8A774A1_CLK_S0D2),
163 DEF_MOD("vspd0", 623, R8A774A1_CLK_S0D2),
164 DEF_MOD("vspb", 626, R8A774A1_CLK_S0D1),
165 DEF_MOD("vspi0", 631, R8A774A1_CLK_S0D1),
166 DEF_MOD("ehci1", 702, R8A774A1_CLK_S3D4),
167 DEF_MOD("ehci0", 703, R8A774A1_CLK_S3D4),
168 DEF_MOD("hsusb", 704, R8A774A1_CLK_S3D4),
169 DEF_MOD("csi20", 714, R8A774A1_CLK_CSI0),
170 DEF_MOD("csi40", 716, R8A774A1_CLK_CSI0),
171 DEF_MOD("du2", 722, R8A774A1_CLK_S2D1),
172 DEF_MOD("du1", 723, R8A774A1_CLK_S2D1),
173 DEF_MOD("du0", 724, R8A774A1_CLK_S2D1),
174 DEF_MOD("lvds", 727, R8A774A1_CLK_S2D1),
175 DEF_MOD("hdmi0", 729, R8A774A1_CLK_HDMI),
176 DEF_MOD("vin7", 804, R8A774A1_CLK_S0D2),
177 DEF_MOD("vin6", 805, R8A774A1_CLK_S0D2),
178 DEF_MOD("vin5", 806, R8A774A1_CLK_S0D2),
179 DEF_MOD("vin4", 807, R8A774A1_CLK_S0D2),
180 DEF_MOD("vin3", 808, R8A774A1_CLK_S0D2),
181 DEF_MOD("vin2", 809, R8A774A1_CLK_S0D2),
182 DEF_MOD("vin1", 810, R8A774A1_CLK_S0D2),
183 DEF_MOD("vin0", 811, R8A774A1_CLK_S0D2),
184 DEF_MOD("etheravb", 812, R8A774A1_CLK_S0D6),
185 DEF_MOD("gpio7", 905, R8A774A1_CLK_S3D4),
186 DEF_MOD("gpio6", 906, R8A774A1_CLK_S3D4),
187 DEF_MOD("gpio5", 907, R8A774A1_CLK_S3D4),
188 DEF_MOD("gpio4", 908, R8A774A1_CLK_S3D4),
189 DEF_MOD("gpio3", 909, R8A774A1_CLK_S3D4),
190 DEF_MOD("gpio2", 910, R8A774A1_CLK_S3D4),
191 DEF_MOD("gpio1", 911, R8A774A1_CLK_S3D4),
192 DEF_MOD("gpio0", 912, R8A774A1_CLK_S3D4),
193 DEF_MOD("can-if1", 915, R8A774A1_CLK_S3D4),
194 DEF_MOD("can-if0", 916, R8A774A1_CLK_S3D4),
195 DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6),
196 DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6),
197 DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP),
198 DEF_MOD("i2c4", 927, R8A774A1_CLK_S0D6),
199 DEF_MOD("i2c3", 928, R8A774A1_CLK_S0D6),
200 DEF_MOD("i2c2", 929, R8A774A1_CLK_S3D2),
201 DEF_MOD("i2c1", 930, R8A774A1_CLK_S3D2),
202 DEF_MOD("i2c0", 931, R8A774A1_CLK_S3D2),
203 DEF_MOD("ssi-all", 1005, R8A774A1_CLK_S3D4),
204 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
205 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
206 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
207 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
208 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
209 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
210 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
211 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
212 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
213 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
214 DEF_MOD("scu-all", 1017, R8A774A1_CLK_S3D4),
215 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
216 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
217 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
218 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
219 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
220 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
221 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
222 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
223 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
224 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
225 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
226 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
227 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
228 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
229};
230
231static const unsigned int r8a774a1_crit_mod_clks[] __initconst = {
232 MOD_CLK_ID(408), /* INTC-AP (GIC) */
233};
234
235/*
236 * CPG Clock Data
237 */
238
239/*
240 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
241 * 14 13 19 17 (MHz)
242 *-------------------------------------------------------------------------
243 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
244 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
245 * 0 0 1 0 Prohibited setting
246 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
247 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
248 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
249 * 0 1 1 0 Prohibited setting
250 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
251 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
252 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
253 * 1 0 1 0 Prohibited setting
254 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
255 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
256 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
257 * 1 1 1 0 Prohibited setting
258 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
259 */
260#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
261 (((md) & BIT(13)) >> 11) | \
262 (((md) & BIT(19)) >> 18) | \
263 (((md) & BIT(17)) >> 17))
264
265static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
266 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
267 { 1, 192, 1, 192, 1, 16, },
268 { 1, 192, 1, 128, 1, 16, },
269 { 0, /* Prohibited setting */ },
270 { 1, 192, 1, 192, 1, 16, },
271 { 1, 160, 1, 160, 1, 19, },
272 { 1, 160, 1, 106, 1, 19, },
273 { 0, /* Prohibited setting */ },
274 { 1, 160, 1, 160, 1, 19, },
275 { 1, 128, 1, 128, 1, 24, },
276 { 1, 128, 1, 84, 1, 24, },
277 { 0, /* Prohibited setting */ },
278 { 1, 128, 1, 128, 1, 24, },
279 { 2, 192, 1, 192, 1, 32, },
280 { 2, 192, 1, 128, 1, 32, },
281 { 0, /* Prohibited setting */ },
282 { 2, 192, 1, 192, 1, 32, },
283};
284
285static int __init r8a774a1_cpg_mssr_init(struct device *dev)
286{
287 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
288 u32 cpg_mode;
289 int error;
290
291 error = rcar_rst_read_mode_pins(&cpg_mode);
292 if (error)
293 return error;
294
295 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
296 if (!cpg_pll_config->extal_div) {
297 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
298 return -EINVAL;
299 }
300
301 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
302}
303
304const struct cpg_mssr_info r8a774a1_cpg_mssr_info __initconst = {
305 /* Core Clocks */
306 .core_clks = r8a774a1_core_clks,
307 .num_core_clks = ARRAY_SIZE(r8a774a1_core_clks),
308 .last_dt_core_clk = LAST_DT_CORE_CLK,
309 .num_total_core_clks = MOD_CLK_BASE,
310
311 /* Module Clocks */
312 .mod_clks = r8a774a1_mod_clks,
313 .num_mod_clks = ARRAY_SIZE(r8a774a1_mod_clks),
314 .num_hw_mod_clks = 12 * 32,
315
316 /* Critical Module Clocks */
317 .crit_mod_clks = r8a774a1_crit_mod_clks,
318 .num_crit_mod_clks = ARRAY_SIZE(r8a774a1_crit_mod_clks),
319
320 /* Callbacks */
321 .init = r8a774a1_cpg_mssr_init,
322 .cpg_clk_register = rcar_gen3_cpg_clk_register,
323};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-26 10:29:46 -0400