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-rw-r--r--drivers/clk/qcom/gcc-qcs404.c2744
1 files changed, 2744 insertions, 0 deletions
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
new file mode 100644
index 000000000000..e4ca6a45f313
--- /dev/null
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -0,0 +1,2744 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/kernel.h>
7#include <linux/platform_device.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/clk-provider.h>
11#include <linux/regmap.h>
12#include <linux/reset-controller.h>
13
14#include <dt-bindings/clock/qcom,gcc-qcs404.h>
15
16#include "clk-alpha-pll.h"
17#include "clk-branch.h"
18#include "clk-pll.h"
19#include "clk-rcg.h"
20#include "clk-regmap.h"
21#include "common.h"
22#include "reset.h"
23
24enum {
25 P_CORE_BI_PLL_TEST_SE,
26 P_DSI0_PHY_PLL_OUT_BYTECLK,
27 P_DSI0_PHY_PLL_OUT_DSICLK,
28 P_GPLL0_OUT_AUX,
29 P_GPLL0_OUT_MAIN,
30 P_GPLL1_OUT_MAIN,
31 P_GPLL3_OUT_MAIN,
32 P_GPLL4_OUT_AUX,
33 P_GPLL4_OUT_MAIN,
34 P_GPLL6_OUT_AUX,
35 P_HDMI_PHY_PLL_CLK,
36 P_PCIE_0_PIPE_CLK,
37 P_SLEEP_CLK,
38 P_XO,
39};
40
41static const struct parent_map gcc_parent_map_0[] = {
42 { P_XO, 0 },
43 { P_GPLL0_OUT_MAIN, 1 },
44 { P_CORE_BI_PLL_TEST_SE, 7 },
45};
46
47static const char * const gcc_parent_names_0[] = {
48 "cxo",
49 "gpll0_out_main",
50 "core_bi_pll_test_se",
51};
52
53static const char * const gcc_parent_names_ao_0[] = {
54 "cxo",
55 "gpll0_ao_out_main",
56 "core_bi_pll_test_se",
57};
58
59static const struct parent_map gcc_parent_map_1[] = {
60 { P_XO, 0 },
61 { P_CORE_BI_PLL_TEST_SE, 7 },
62};
63
64static const char * const gcc_parent_names_1[] = {
65 "cxo",
66 "core_bi_pll_test_se",
67};
68
69static const struct parent_map gcc_parent_map_2[] = {
70 { P_XO, 0 },
71 { P_GPLL0_OUT_MAIN, 1 },
72 { P_GPLL6_OUT_AUX, 2 },
73 { P_SLEEP_CLK, 6 },
74};
75
76static const char * const gcc_parent_names_2[] = {
77 "cxo",
78 "gpll0_out_main",
79 "gpll6_out_aux",
80 "sleep_clk",
81};
82
83static const struct parent_map gcc_parent_map_3[] = {
84 { P_XO, 0 },
85 { P_GPLL0_OUT_MAIN, 1 },
86 { P_GPLL6_OUT_AUX, 2 },
87 { P_CORE_BI_PLL_TEST_SE, 7 },
88};
89
90static const char * const gcc_parent_names_3[] = {
91 "cxo",
92 "gpll0_out_main",
93 "gpll6_out_aux",
94 "core_bi_pll_test_se",
95};
96
97static const struct parent_map gcc_parent_map_4[] = {
98 { P_XO, 0 },
99 { P_GPLL1_OUT_MAIN, 1 },
100 { P_CORE_BI_PLL_TEST_SE, 7 },
101};
102
103static const char * const gcc_parent_names_4[] = {
104 "cxo",
105 "gpll1_out_main",
106 "core_bi_pll_test_se",
107};
108
109static const struct parent_map gcc_parent_map_5[] = {
110 { P_XO, 0 },
111 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
112 { P_GPLL0_OUT_AUX, 2 },
113 { P_CORE_BI_PLL_TEST_SE, 7 },
114};
115
116static const char * const gcc_parent_names_5[] = {
117 "cxo",
118 "dsi0pll_byteclk_src",
119 "gpll0_out_aux",
120 "core_bi_pll_test_se",
121};
122
123static const struct parent_map gcc_parent_map_6[] = {
124 { P_XO, 0 },
125 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
126 { P_GPLL0_OUT_AUX, 3 },
127 { P_CORE_BI_PLL_TEST_SE, 7 },
128};
129
130static const char * const gcc_parent_names_6[] = {
131 "cxo",
132 "dsi0_phy_pll_out_byteclk",
133 "gpll0_out_aux",
134 "core_bi_pll_test_se",
135};
136
137static const struct parent_map gcc_parent_map_7[] = {
138 { P_XO, 0 },
139 { P_GPLL0_OUT_MAIN, 1 },
140 { P_GPLL3_OUT_MAIN, 2 },
141 { P_GPLL6_OUT_AUX, 3 },
142 { P_GPLL4_OUT_AUX, 4 },
143 { P_CORE_BI_PLL_TEST_SE, 7 },
144};
145
146static const char * const gcc_parent_names_7[] = {
147 "cxo",
148 "gpll0_out_main",
149 "gpll3_out_main",
150 "gpll6_out_aux",
151 "gpll4_out_aux",
152 "core_bi_pll_test_se",
153};
154
155static const struct parent_map gcc_parent_map_8[] = {
156 { P_XO, 0 },
157 { P_HDMI_PHY_PLL_CLK, 1 },
158 { P_CORE_BI_PLL_TEST_SE, 7 },
159};
160
161static const char * const gcc_parent_names_8[] = {
162 "cxo",
163 "hdmi_phy_pll_clk",
164 "core_bi_pll_test_se",
165};
166
167static const struct parent_map gcc_parent_map_9[] = {
168 { P_XO, 0 },
169 { P_GPLL0_OUT_MAIN, 1 },
170 { P_DSI0_PHY_PLL_OUT_DSICLK, 2 },
171 { P_GPLL6_OUT_AUX, 3 },
172 { P_CORE_BI_PLL_TEST_SE, 7 },
173};
174
175static const char * const gcc_parent_names_9[] = {
176 "cxo",
177 "gpll0_out_main",
178 "dsi0_phy_pll_out_dsiclk",
179 "gpll6_out_aux",
180 "core_bi_pll_test_se",
181};
182
183static const struct parent_map gcc_parent_map_10[] = {
184 { P_XO, 0 },
185 { P_SLEEP_CLK, 1 },
186 { P_CORE_BI_PLL_TEST_SE, 7 },
187};
188
189static const char * const gcc_parent_names_10[] = {
190 "cxo",
191 "sleep_clk",
192 "core_bi_pll_test_se",
193};
194
195static const struct parent_map gcc_parent_map_11[] = {
196 { P_XO, 0 },
197 { P_PCIE_0_PIPE_CLK, 1 },
198 { P_CORE_BI_PLL_TEST_SE, 7 },
199};
200
201static const char * const gcc_parent_names_11[] = {
202 "cxo",
203 "pcie_0_pipe_clk",
204 "core_bi_pll_test_se",
205};
206
207static const struct parent_map gcc_parent_map_12[] = {
208 { P_XO, 0 },
209 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
210 { P_GPLL0_OUT_AUX, 2 },
211 { P_CORE_BI_PLL_TEST_SE, 7 },
212};
213
214static const char * const gcc_parent_names_12[] = {
215 "cxo",
216 "dsi0pll_pclk_src",
217 "gpll0_out_aux",
218 "core_bi_pll_test_se",
219};
220
221static const struct parent_map gcc_parent_map_13[] = {
222 { P_XO, 0 },
223 { P_GPLL0_OUT_MAIN, 1 },
224 { P_GPLL4_OUT_MAIN, 2 },
225 { P_GPLL6_OUT_AUX, 3 },
226 { P_CORE_BI_PLL_TEST_SE, 7 },
227};
228
229static const char * const gcc_parent_names_13[] = {
230 "cxo",
231 "gpll0_out_main",
232 "gpll4_out_main",
233 "gpll6_out_aux",
234 "core_bi_pll_test_se",
235};
236
237static const struct parent_map gcc_parent_map_14[] = {
238 { P_XO, 0 },
239 { P_GPLL0_OUT_MAIN, 1 },
240 { P_GPLL4_OUT_AUX, 2 },
241 { P_CORE_BI_PLL_TEST_SE, 7 },
242};
243
244static const char * const gcc_parent_names_14[] = {
245 "cxo",
246 "gpll0_out_main",
247 "gpll4_out_aux",
248 "core_bi_pll_test_se",
249};
250
251static const struct parent_map gcc_parent_map_15[] = {
252 { P_XO, 0 },
253 { P_GPLL0_OUT_AUX, 2 },
254 { P_CORE_BI_PLL_TEST_SE, 7 },
255};
256
257static const char * const gcc_parent_names_15[] = {
258 "cxo",
259 "gpll0_out_aux",
260 "core_bi_pll_test_se",
261};
262
263static struct clk_fixed_factor cxo = {
264 .mult = 1,
265 .div = 1,
266 .hw.init = &(struct clk_init_data){
267 .name = "cxo",
268 .parent_names = (const char *[]){ "xo_board" },
269 .num_parents = 1,
270 .ops = &clk_fixed_factor_ops,
271 },
272};
273
274static struct clk_alpha_pll gpll0_sleep_clk_src = {
275 .offset = 0x21000,
276 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
277 .clkr = {
278 .enable_reg = 0x45008,
279 .enable_mask = BIT(23),
280 .enable_is_inverted = true,
281 .hw.init = &(struct clk_init_data){
282 .name = "gpll0_sleep_clk_src",
283 .parent_names = (const char *[]){ "cxo" },
284 .num_parents = 1,
285 .ops = &clk_alpha_pll_ops,
286 },
287 },
288};
289
290static struct clk_alpha_pll gpll0_out_main = {
291 .offset = 0x21000,
292 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
293 .flags = SUPPORTS_FSM_MODE,
294 .clkr = {
295 .enable_reg = 0x45000,
296 .enable_mask = BIT(0),
297 .hw.init = &(struct clk_init_data){
298 .name = "gpll0_out_main",
299 .parent_names = (const char *[])
300 { "gpll0_sleep_clk_src" },
301 .num_parents = 1,
302 .ops = &clk_alpha_pll_ops,
303 },
304 },
305};
306
307static struct clk_alpha_pll gpll0_ao_out_main = {
308 .offset = 0x21000,
309 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
310 .flags = SUPPORTS_FSM_MODE,
311 .clkr = {
312 .enable_reg = 0x45000,
313 .enable_mask = BIT(0),
314 .hw.init = &(struct clk_init_data){
315 .name = "gpll0_ao_out_main",
316 .parent_names = (const char *[]){ "cxo" },
317 .num_parents = 1,
318 .flags = CLK_IS_CRITICAL,
319 .ops = &clk_alpha_pll_ops,
320 },
321 },
322};
323
324static struct clk_alpha_pll gpll1_out_main = {
325 .offset = 0x20000,
326 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
327 .clkr = {
328 .enable_reg = 0x45000,
329 .enable_mask = BIT(1),
330 .hw.init = &(struct clk_init_data){
331 .name = "gpll1_out_main",
332 .parent_names = (const char *[]){ "cxo" },
333 .num_parents = 1,
334 .ops = &clk_alpha_pll_ops,
335 },
336 },
337};
338
339/* 930MHz configuration */
340static const struct alpha_pll_config gpll3_config = {
341 .l = 48,
342 .alpha = 0x0,
343 .alpha_en_mask = BIT(24),
344 .post_div_mask = 0xf << 8,
345 .post_div_val = 0x1 << 8,
346 .vco_mask = 0x3 << 20,
347 .main_output_mask = 0x1,
348 .config_ctl_val = 0x4001055b,
349};
350
351static const struct pll_vco gpll3_vco[] = {
352 { 700000000, 1400000000, 0 },
353};
354
355static struct clk_alpha_pll gpll3_out_main = {
356 .offset = 0x22000,
357 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
358 .vco_table = gpll3_vco,
359 .num_vco = ARRAY_SIZE(gpll3_vco),
360 .clkr = {
361 .hw.init = &(struct clk_init_data){
362 .name = "gpll3_out_main",
363 .parent_names = (const char *[]){ "cxo" },
364 .num_parents = 1,
365 .ops = &clk_alpha_pll_ops,
366 },
367 },
368};
369
370static struct clk_alpha_pll gpll4_out_main = {
371 .offset = 0x24000,
372 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
373 .clkr = {
374 .enable_reg = 0x45000,
375 .enable_mask = BIT(5),
376 .hw.init = &(struct clk_init_data){
377 .name = "gpll4_out_main",
378 .parent_names = (const char *[]){ "cxo" },
379 .num_parents = 1,
380 .ops = &clk_alpha_pll_ops,
381 },
382 },
383};
384
385static struct clk_pll gpll6 = {
386 .l_reg = 0x37004,
387 .m_reg = 0x37008,
388 .n_reg = 0x3700C,
389 .config_reg = 0x37014,
390 .mode_reg = 0x37000,
391 .status_reg = 0x3701C,
392 .status_bit = 17,
393 .clkr.hw.init = &(struct clk_init_data){
394 .name = "gpll6",
395 .parent_names = (const char *[]){ "cxo" },
396 .num_parents = 1,
397 .ops = &clk_pll_ops,
398 },
399};
400
401static struct clk_regmap gpll6_out_aux = {
402 .enable_reg = 0x45000,
403 .enable_mask = BIT(7),
404 .hw.init = &(struct clk_init_data){
405 .name = "gpll6_out_aux",
406 .parent_names = (const char *[]){ "gpll6" },
407 .num_parents = 1,
408 .ops = &clk_pll_vote_ops,
409 },
410};
411
412static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
413 F(19200000, P_XO, 1, 0, 0),
414 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
415 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
416 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
417 { }
418};
419
420static struct clk_rcg2 apss_ahb_clk_src = {
421 .cmd_rcgr = 0x46000,
422 .mnd_width = 0,
423 .hid_width = 5,
424 .parent_map = gcc_parent_map_0,
425 .freq_tbl = ftbl_apss_ahb_clk_src,
426 .clkr.hw.init = &(struct clk_init_data){
427 .name = "apss_ahb_clk_src",
428 .parent_names = gcc_parent_names_ao_0,
429 .num_parents = 3,
430 .flags = CLK_IS_CRITICAL,
431 .ops = &clk_rcg2_ops,
432 },
433};
434
435static const struct freq_tbl ftbl_blsp1_qup0_i2c_apps_clk_src[] = {
436 F(19200000, P_XO, 1, 0, 0),
437 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
438 { }
439};
440
441static struct clk_rcg2 blsp1_qup0_i2c_apps_clk_src = {
442 .cmd_rcgr = 0x602c,
443 .mnd_width = 0,
444 .hid_width = 5,
445 .parent_map = gcc_parent_map_0,
446 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
447 .clkr.hw.init = &(struct clk_init_data){
448 .name = "blsp1_qup0_i2c_apps_clk_src",
449 .parent_names = gcc_parent_names_0,
450 .num_parents = 3,
451 .ops = &clk_rcg2_ops,
452 },
453};
454
455static const struct freq_tbl ftbl_blsp1_qup0_spi_apps_clk_src[] = {
456 F(960000, P_XO, 10, 1, 2),
457 F(4800000, P_XO, 4, 0, 0),
458 F(9600000, P_XO, 2, 0, 0),
459 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
460 F(19200000, P_XO, 1, 0, 0),
461 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
462 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
463 { }
464};
465
466static struct clk_rcg2 blsp1_qup0_spi_apps_clk_src = {
467 .cmd_rcgr = 0x6034,
468 .mnd_width = 8,
469 .hid_width = 5,
470 .parent_map = gcc_parent_map_0,
471 .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
472 .clkr.hw.init = &(struct clk_init_data){
473 .name = "blsp1_qup0_spi_apps_clk_src",
474 .parent_names = gcc_parent_names_0,
475 .num_parents = 3,
476 .ops = &clk_rcg2_ops,
477 },
478};
479
480static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
481 .cmd_rcgr = 0x200c,
482 .mnd_width = 0,
483 .hid_width = 5,
484 .parent_map = gcc_parent_map_0,
485 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
486 .clkr.hw.init = &(struct clk_init_data){
487 .name = "blsp1_qup1_i2c_apps_clk_src",
488 .parent_names = gcc_parent_names_0,
489 .num_parents = 3,
490 .ops = &clk_rcg2_ops,
491 },
492};
493
494static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
495 F(960000, P_XO, 10, 1, 2),
496 F(4800000, P_XO, 4, 0, 0),
497 F(9600000, P_XO, 2, 0, 0),
498 F(10480000, P_GPLL0_OUT_MAIN, 1, 3, 229),
499 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
500 F(19200000, P_XO, 1, 0, 0),
501 F(20961000, P_GPLL0_OUT_MAIN, 1, 6, 229),
502 { }
503};
504
505static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
506 .cmd_rcgr = 0x2024,
507 .mnd_width = 8,
508 .hid_width = 5,
509 .parent_map = gcc_parent_map_0,
510 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
511 .clkr.hw.init = &(struct clk_init_data){
512 .name = "blsp1_qup1_spi_apps_clk_src",
513 .parent_names = gcc_parent_names_0,
514 .num_parents = 3,
515 .ops = &clk_rcg2_ops,
516 },
517};
518
519static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
520 .cmd_rcgr = 0x3000,
521 .mnd_width = 0,
522 .hid_width = 5,
523 .parent_map = gcc_parent_map_0,
524 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
525 .clkr.hw.init = &(struct clk_init_data){
526 .name = "blsp1_qup2_i2c_apps_clk_src",
527 .parent_names = gcc_parent_names_0,
528 .num_parents = 3,
529 .ops = &clk_rcg2_ops,
530 },
531};
532
533static const struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
534 F(960000, P_XO, 10, 1, 2),
535 F(4800000, P_XO, 4, 0, 0),
536 F(9600000, P_XO, 2, 0, 0),
537 F(15000000, P_GPLL0_OUT_MAIN, 1, 3, 160),
538 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
539 F(19200000, P_XO, 1, 0, 0),
540 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
541 F(30000000, P_GPLL0_OUT_MAIN, 1, 3, 80),
542 { }
543};
544
545static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
546 .cmd_rcgr = 0x3014,
547 .mnd_width = 8,
548 .hid_width = 5,
549 .parent_map = gcc_parent_map_0,
550 .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
551 .clkr.hw.init = &(struct clk_init_data){
552 .name = "blsp1_qup2_spi_apps_clk_src",
553 .parent_names = gcc_parent_names_0,
554 .num_parents = 3,
555 .ops = &clk_rcg2_ops,
556 },
557};
558
559static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
560 .cmd_rcgr = 0x4000,
561 .mnd_width = 0,
562 .hid_width = 5,
563 .parent_map = gcc_parent_map_0,
564 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
565 .clkr.hw.init = &(struct clk_init_data){
566 .name = "blsp1_qup3_i2c_apps_clk_src",
567 .parent_names = gcc_parent_names_0,
568 .num_parents = 3,
569 .ops = &clk_rcg2_ops,
570 },
571};
572
573static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
574 .cmd_rcgr = 0x4024,
575 .mnd_width = 8,
576 .hid_width = 5,
577 .parent_map = gcc_parent_map_0,
578 .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
579 .clkr.hw.init = &(struct clk_init_data){
580 .name = "blsp1_qup3_spi_apps_clk_src",
581 .parent_names = gcc_parent_names_0,
582 .num_parents = 3,
583 .ops = &clk_rcg2_ops,
584 },
585};
586
587static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
588 .cmd_rcgr = 0x5000,
589 .mnd_width = 0,
590 .hid_width = 5,
591 .parent_map = gcc_parent_map_0,
592 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
593 .clkr.hw.init = &(struct clk_init_data){
594 .name = "blsp1_qup4_i2c_apps_clk_src",
595 .parent_names = gcc_parent_names_0,
596 .num_parents = 3,
597 .ops = &clk_rcg2_ops,
598 },
599};
600
601static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
602 .cmd_rcgr = 0x5024,
603 .mnd_width = 8,
604 .hid_width = 5,
605 .parent_map = gcc_parent_map_0,
606 .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
607 .clkr.hw.init = &(struct clk_init_data){
608 .name = "blsp1_qup4_spi_apps_clk_src",
609 .parent_names = gcc_parent_names_0,
610 .num_parents = 3,
611 .ops = &clk_rcg2_ops,
612 },
613};
614
615static const struct freq_tbl ftbl_blsp1_uart0_apps_clk_src[] = {
616 F(3686400, P_GPLL0_OUT_MAIN, 1, 72, 15625),
617 F(7372800, P_GPLL0_OUT_MAIN, 1, 144, 15625),
618 F(14745600, P_GPLL0_OUT_MAIN, 1, 288, 15625),
619 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
620 F(19200000, P_XO, 1, 0, 0),
621 F(24000000, P_GPLL0_OUT_MAIN, 1, 3, 100),
622 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
623 F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
624 F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
625 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),
626 F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
627 F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
628 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
629 F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),
630 F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
631 F(64000000, P_GPLL0_OUT_MAIN, 1, 2, 25),
632 { }
633};
634
635static struct clk_rcg2 blsp1_uart0_apps_clk_src = {
636 .cmd_rcgr = 0x600c,
637 .mnd_width = 16,
638 .hid_width = 5,
639 .parent_map = gcc_parent_map_0,
640 .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
641 .clkr.hw.init = &(struct clk_init_data){
642 .name = "blsp1_uart0_apps_clk_src",
643 .parent_names = gcc_parent_names_0,
644 .num_parents = 3,
645 .ops = &clk_rcg2_ops,
646 },
647};
648
649static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
650 .cmd_rcgr = 0x2044,
651 .mnd_width = 16,
652 .hid_width = 5,
653 .parent_map = gcc_parent_map_0,
654 .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
655 .clkr.hw.init = &(struct clk_init_data){
656 .name = "blsp1_uart1_apps_clk_src",
657 .parent_names = gcc_parent_names_0,
658 .num_parents = 3,
659 .ops = &clk_rcg2_ops,
660 },
661};
662
663static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
664 .cmd_rcgr = 0x3034,
665 .mnd_width = 16,
666 .hid_width = 5,
667 .parent_map = gcc_parent_map_0,
668 .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
669 .clkr.hw.init = &(struct clk_init_data){
670 .name = "blsp1_uart2_apps_clk_src",
671 .parent_names = gcc_parent_names_0,
672 .num_parents = 3,
673 .ops = &clk_rcg2_ops,
674 },
675};
676
677static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
678 .cmd_rcgr = 0x4014,
679 .mnd_width = 16,
680 .hid_width = 5,
681 .parent_map = gcc_parent_map_0,
682 .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
683 .clkr.hw.init = &(struct clk_init_data){
684 .name = "blsp1_uart3_apps_clk_src",
685 .parent_names = gcc_parent_names_0,
686 .num_parents = 3,
687 .ops = &clk_rcg2_ops,
688 },
689};
690
691static struct clk_rcg2 blsp2_qup0_i2c_apps_clk_src = {
692 .cmd_rcgr = 0xc00c,
693 .mnd_width = 0,
694 .hid_width = 5,
695 .parent_map = gcc_parent_map_0,
696 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
697 .clkr.hw.init = &(struct clk_init_data){
698 .name = "blsp2_qup0_i2c_apps_clk_src",
699 .parent_names = gcc_parent_names_0,
700 .num_parents = 3,
701 .ops = &clk_rcg2_ops,
702 },
703};
704
705static struct clk_rcg2 blsp2_qup0_spi_apps_clk_src = {
706 .cmd_rcgr = 0xc024,
707 .mnd_width = 8,
708 .hid_width = 5,
709 .parent_map = gcc_parent_map_0,
710 .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
711 .clkr.hw.init = &(struct clk_init_data){
712 .name = "blsp2_qup0_spi_apps_clk_src",
713 .parent_names = gcc_parent_names_0,
714 .num_parents = 3,
715 .ops = &clk_rcg2_ops,
716 },
717};
718
719static struct clk_rcg2 blsp2_uart0_apps_clk_src = {
720 .cmd_rcgr = 0xc044,
721 .mnd_width = 16,
722 .hid_width = 5,
723 .parent_map = gcc_parent_map_0,
724 .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
725 .clkr.hw.init = &(struct clk_init_data){
726 .name = "blsp2_uart0_apps_clk_src",
727 .parent_names = gcc_parent_names_0,
728 .num_parents = 3,
729 .ops = &clk_rcg2_ops,
730 },
731};
732
733static struct clk_rcg2 byte0_clk_src = {
734 .cmd_rcgr = 0x4d044,
735 .mnd_width = 0,
736 .hid_width = 5,
737 .parent_map = gcc_parent_map_5,
738 .clkr.hw.init = &(struct clk_init_data){
739 .name = "byte0_clk_src",
740 .parent_names = gcc_parent_names_5,
741 .num_parents = 4,
742 .flags = CLK_SET_RATE_PARENT,
743 .ops = &clk_byte2_ops,
744 },
745};
746
747static const struct freq_tbl ftbl_emac_clk_src[] = {
748 F(5000000, P_GPLL1_OUT_MAIN, 2, 1, 50),
749 F(50000000, P_GPLL1_OUT_MAIN, 10, 0, 0),
750 F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
751 F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
752 { }
753};
754
755static struct clk_rcg2 emac_clk_src = {
756 .cmd_rcgr = 0x4e01c,
757 .mnd_width = 8,
758 .hid_width = 5,
759 .parent_map = gcc_parent_map_4,
760 .freq_tbl = ftbl_emac_clk_src,
761 .clkr.hw.init = &(struct clk_init_data){
762 .name = "emac_clk_src",
763 .parent_names = gcc_parent_names_4,
764 .num_parents = 3,
765 .ops = &clk_rcg2_ops,
766 },
767};
768
769static const struct freq_tbl ftbl_emac_ptp_clk_src[] = {
770 F(50000000, P_GPLL1_OUT_MAIN, 10, 0, 0),
771 F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
772 F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
773 { }
774};
775
776static struct clk_rcg2 emac_ptp_clk_src = {
777 .cmd_rcgr = 0x4e014,
778 .mnd_width = 0,
779 .hid_width = 5,
780 .parent_map = gcc_parent_map_4,
781 .freq_tbl = ftbl_emac_ptp_clk_src,
782 .clkr.hw.init = &(struct clk_init_data){
783 .name = "emac_ptp_clk_src",
784 .parent_names = gcc_parent_names_4,
785 .num_parents = 3,
786 .ops = &clk_rcg2_ops,
787 },
788};
789
790static const struct freq_tbl ftbl_esc0_clk_src[] = {
791 F(19200000, P_XO, 1, 0, 0),
792 { }
793};
794
795static struct clk_rcg2 esc0_clk_src = {
796 .cmd_rcgr = 0x4d05c,
797 .mnd_width = 0,
798 .hid_width = 5,
799 .parent_map = gcc_parent_map_6,
800 .freq_tbl = ftbl_esc0_clk_src,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "esc0_clk_src",
803 .parent_names = gcc_parent_names_6,
804 .num_parents = 4,
805 .ops = &clk_rcg2_ops,
806 },
807};
808
809static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
810 F(19200000, P_XO, 1, 0, 0),
811 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
812 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
813 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
814 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
815 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
816 F(228571429, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
817 F(240000000, P_GPLL6_OUT_AUX, 4.5, 0, 0),
818 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
819 F(270000000, P_GPLL6_OUT_AUX, 4, 0, 0),
820 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
821 F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
822 F(484800000, P_GPLL3_OUT_MAIN, 1, 0, 0),
823 F(523200000, P_GPLL3_OUT_MAIN, 1, 0, 0),
824 F(550000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
825 F(598000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
826 { }
827};
828
829static struct clk_rcg2 gfx3d_clk_src = {
830 .cmd_rcgr = 0x59000,
831 .mnd_width = 0,
832 .hid_width = 5,
833 .parent_map = gcc_parent_map_7,
834 .freq_tbl = ftbl_gfx3d_clk_src,
835 .clkr.hw.init = &(struct clk_init_data){
836 .name = "gfx3d_clk_src",
837 .parent_names = gcc_parent_names_7,
838 .num_parents = 6,
839 .ops = &clk_rcg2_ops,
840 },
841};
842
843static const struct freq_tbl ftbl_gp1_clk_src[] = {
844 F(19200000, P_XO, 1, 0, 0),
845 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
846 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
847 { }
848};
849
850static struct clk_rcg2 gp1_clk_src = {
851 .cmd_rcgr = 0x8004,
852 .mnd_width = 8,
853 .hid_width = 5,
854 .parent_map = gcc_parent_map_2,
855 .freq_tbl = ftbl_gp1_clk_src,
856 .clkr.hw.init = &(struct clk_init_data){
857 .name = "gp1_clk_src",
858 .parent_names = gcc_parent_names_2,
859 .num_parents = 4,
860 .ops = &clk_rcg2_ops,
861 },
862};
863
864static struct clk_rcg2 gp2_clk_src = {
865 .cmd_rcgr = 0x9004,
866 .mnd_width = 8,
867 .hid_width = 5,
868 .parent_map = gcc_parent_map_2,
869 .freq_tbl = ftbl_gp1_clk_src,
870 .clkr.hw.init = &(struct clk_init_data){
871 .name = "gp2_clk_src",
872 .parent_names = gcc_parent_names_2,
873 .num_parents = 4,
874 .ops = &clk_rcg2_ops,
875 },
876};
877
878static struct clk_rcg2 gp3_clk_src = {
879 .cmd_rcgr = 0xa004,
880 .mnd_width = 8,
881 .hid_width = 5,
882 .parent_map = gcc_parent_map_2,
883 .freq_tbl = ftbl_gp1_clk_src,
884 .clkr.hw.init = &(struct clk_init_data){
885 .name = "gp3_clk_src",
886 .parent_names = gcc_parent_names_2,
887 .num_parents = 4,
888 .ops = &clk_rcg2_ops,
889 },
890};
891
892static struct clk_rcg2 hdmi_app_clk_src = {
893 .cmd_rcgr = 0x4d0e4,
894 .mnd_width = 0,
895 .hid_width = 5,
896 .parent_map = gcc_parent_map_1,
897 .freq_tbl = ftbl_esc0_clk_src,
898 .clkr.hw.init = &(struct clk_init_data){
899 .name = "hdmi_app_clk_src",
900 .parent_names = gcc_parent_names_1,
901 .num_parents = 2,
902 .ops = &clk_rcg2_ops,
903 },
904};
905
906static struct clk_rcg2 hdmi_pclk_clk_src = {
907 .cmd_rcgr = 0x4d0dc,
908 .mnd_width = 0,
909 .hid_width = 5,
910 .parent_map = gcc_parent_map_8,
911 .freq_tbl = ftbl_esc0_clk_src,
912 .clkr.hw.init = &(struct clk_init_data){
913 .name = "hdmi_pclk_clk_src",
914 .parent_names = gcc_parent_names_8,
915 .num_parents = 3,
916 .ops = &clk_rcg2_ops,
917 },
918};
919
920static const struct freq_tbl ftbl_mdp_clk_src[] = {
921 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
922 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
923 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
924 F(145454545, P_GPLL0_OUT_MAIN, 5.5, 0, 0),
925 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
926 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
927 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
928 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
929 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
930 { }
931};
932
933static struct clk_rcg2 mdp_clk_src = {
934 .cmd_rcgr = 0x4d014,
935 .mnd_width = 0,
936 .hid_width = 5,
937 .parent_map = gcc_parent_map_9,
938 .freq_tbl = ftbl_mdp_clk_src,
939 .clkr.hw.init = &(struct clk_init_data){
940 .name = "mdp_clk_src",
941 .parent_names = gcc_parent_names_9,
942 .num_parents = 5,
943 .ops = &clk_rcg2_ops,
944 },
945};
946
947static const struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
948 F(1200000, P_XO, 16, 0, 0),
949 { }
950};
951
952static struct clk_rcg2 pcie_0_aux_clk_src = {
953 .cmd_rcgr = 0x3e024,
954 .mnd_width = 16,
955 .hid_width = 5,
956 .parent_map = gcc_parent_map_10,
957 .freq_tbl = ftbl_pcie_0_aux_clk_src,
958 .clkr.hw.init = &(struct clk_init_data){
959 .name = "pcie_0_aux_clk_src",
960 .parent_names = gcc_parent_names_10,
961 .num_parents = 3,
962 .ops = &clk_rcg2_ops,
963 },
964};
965
966static const struct freq_tbl ftbl_pcie_0_pipe_clk_src[] = {
967 F(19200000, P_XO, 1, 0, 0),
968 F(125000000, P_PCIE_0_PIPE_CLK, 2, 0, 0),
969 F(250000000, P_PCIE_0_PIPE_CLK, 1, 0, 0),
970 { }
971};
972
973static struct clk_rcg2 pcie_0_pipe_clk_src = {
974 .cmd_rcgr = 0x3e01c,
975 .mnd_width = 0,
976 .hid_width = 5,
977 .parent_map = gcc_parent_map_11,
978 .freq_tbl = ftbl_pcie_0_pipe_clk_src,
979 .clkr.hw.init = &(struct clk_init_data){
980 .name = "pcie_0_pipe_clk_src",
981 .parent_names = gcc_parent_names_11,
982 .num_parents = 3,
983 .ops = &clk_rcg2_ops,
984 },
985};
986
987static struct clk_rcg2 pclk0_clk_src = {
988 .cmd_rcgr = 0x4d000,
989 .mnd_width = 8,
990 .hid_width = 5,
991 .parent_map = gcc_parent_map_12,
992 .clkr.hw.init = &(struct clk_init_data){
993 .name = "pclk0_clk_src",
994 .parent_names = gcc_parent_names_12,
995 .num_parents = 4,
996 .flags = CLK_SET_RATE_PARENT,
997 .ops = &clk_pixel_ops,
998 },
999};
1000
1001static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1002 F(19200000, P_XO, 1, 0, 0),
1003 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
1004 { }
1005};
1006
1007static struct clk_rcg2 pdm2_clk_src = {
1008 .cmd_rcgr = 0x44010,
1009 .mnd_width = 0,
1010 .hid_width = 5,
1011 .parent_map = gcc_parent_map_0,
1012 .freq_tbl = ftbl_pdm2_clk_src,
1013 .clkr.hw.init = &(struct clk_init_data){
1014 .name = "pdm2_clk_src",
1015 .parent_names = gcc_parent_names_0,
1016 .num_parents = 3,
1017 .ops = &clk_rcg2_ops,
1018 },
1019};
1020
1021static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
1022 F(144000, P_XO, 16, 3, 25),
1023 F(400000, P_XO, 12, 1, 4),
1024 F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
1025 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
1026 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1027 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1028 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1029 F(192000000, P_GPLL4_OUT_MAIN, 6, 0, 0),
1030 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1031 F(384000000, P_GPLL4_OUT_MAIN, 3, 0, 0),
1032 { }
1033};
1034
1035static struct clk_rcg2 sdcc1_apps_clk_src = {
1036 .cmd_rcgr = 0x42004,
1037 .mnd_width = 8,
1038 .hid_width = 5,
1039 .parent_map = gcc_parent_map_13,
1040 .freq_tbl = ftbl_sdcc1_apps_clk_src,
1041 .clkr.hw.init = &(struct clk_init_data){
1042 .name = "sdcc1_apps_clk_src",
1043 .parent_names = gcc_parent_names_13,
1044 .num_parents = 5,
1045 .ops = &clk_rcg2_ops,
1046 },
1047};
1048
1049static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
1050 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1051 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1052 { }
1053};
1054
1055static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1056 .cmd_rcgr = 0x5d000,
1057 .mnd_width = 8,
1058 .hid_width = 5,
1059 .parent_map = gcc_parent_map_3,
1060 .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
1061 .clkr.hw.init = &(struct clk_init_data){
1062 .name = "sdcc1_ice_core_clk_src",
1063 .parent_names = gcc_parent_names_3,
1064 .num_parents = 4,
1065 .ops = &clk_rcg2_ops,
1066 },
1067};
1068
1069static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
1070 F(144000, P_XO, 16, 3, 25),
1071 F(400000, P_XO, 12, 1, 4),
1072 F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
1073 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
1074 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1075 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1076 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1077 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1078 { }
1079};
1080
1081static struct clk_rcg2 sdcc2_apps_clk_src = {
1082 .cmd_rcgr = 0x43004,
1083 .mnd_width = 8,
1084 .hid_width = 5,
1085 .parent_map = gcc_parent_map_14,
1086 .freq_tbl = ftbl_sdcc2_apps_clk_src,
1087 .clkr.hw.init = &(struct clk_init_data){
1088 .name = "sdcc2_apps_clk_src",
1089 .parent_names = gcc_parent_names_14,
1090 .num_parents = 4,
1091 .ops = &clk_rcg2_ops,
1092 },
1093};
1094
1095static struct clk_rcg2 usb20_mock_utmi_clk_src = {
1096 .cmd_rcgr = 0x41048,
1097 .mnd_width = 0,
1098 .hid_width = 5,
1099 .parent_map = gcc_parent_map_1,
1100 .freq_tbl = ftbl_esc0_clk_src,
1101 .clkr.hw.init = &(struct clk_init_data){
1102 .name = "usb20_mock_utmi_clk_src",
1103 .parent_names = gcc_parent_names_1,
1104 .num_parents = 2,
1105 .ops = &clk_rcg2_ops,
1106 },
1107};
1108
1109static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
1110 F(19200000, P_XO, 1, 0, 0),
1111 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1112 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1113 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1114 { }
1115};
1116
1117static struct clk_rcg2 usb30_master_clk_src = {
1118 .cmd_rcgr = 0x39028,
1119 .mnd_width = 8,
1120 .hid_width = 5,
1121 .parent_map = gcc_parent_map_0,
1122 .freq_tbl = ftbl_usb30_master_clk_src,
1123 .clkr.hw.init = &(struct clk_init_data){
1124 .name = "usb30_master_clk_src",
1125 .parent_names = gcc_parent_names_0,
1126 .num_parents = 3,
1127 .ops = &clk_rcg2_ops,
1128 },
1129};
1130
1131static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1132 .cmd_rcgr = 0x3901c,
1133 .mnd_width = 0,
1134 .hid_width = 5,
1135 .parent_map = gcc_parent_map_1,
1136 .freq_tbl = ftbl_esc0_clk_src,
1137 .clkr.hw.init = &(struct clk_init_data){
1138 .name = "usb30_mock_utmi_clk_src",
1139 .parent_names = gcc_parent_names_1,
1140 .num_parents = 2,
1141 .ops = &clk_rcg2_ops,
1142 },
1143};
1144
1145static struct clk_rcg2 usb3_phy_aux_clk_src = {
1146 .cmd_rcgr = 0x3903c,
1147 .mnd_width = 0,
1148 .hid_width = 5,
1149 .parent_map = gcc_parent_map_1,
1150 .freq_tbl = ftbl_pcie_0_aux_clk_src,
1151 .clkr.hw.init = &(struct clk_init_data){
1152 .name = "usb3_phy_aux_clk_src",
1153 .parent_names = gcc_parent_names_1,
1154 .num_parents = 2,
1155 .ops = &clk_rcg2_ops,
1156 },
1157};
1158
1159static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1160 F(19200000, P_XO, 1, 0, 0),
1161 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1162 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1163 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1164 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1165 { }
1166};
1167
1168static struct clk_rcg2 usb_hs_system_clk_src = {
1169 .cmd_rcgr = 0x41010,
1170 .mnd_width = 0,
1171 .hid_width = 5,
1172 .parent_map = gcc_parent_map_3,
1173 .freq_tbl = ftbl_usb_hs_system_clk_src,
1174 .clkr.hw.init = &(struct clk_init_data){
1175 .name = "usb_hs_system_clk_src",
1176 .parent_names = gcc_parent_names_3,
1177 .num_parents = 4,
1178 .ops = &clk_rcg2_ops,
1179 },
1180};
1181
1182static struct clk_rcg2 vsync_clk_src = {
1183 .cmd_rcgr = 0x4d02c,
1184 .mnd_width = 0,
1185 .hid_width = 5,
1186 .parent_map = gcc_parent_map_15,
1187 .freq_tbl = ftbl_esc0_clk_src,
1188 .clkr.hw.init = &(struct clk_init_data){
1189 .name = "vsync_clk_src",
1190 .parent_names = gcc_parent_names_15,
1191 .num_parents = 3,
1192 .ops = &clk_rcg2_ops,
1193 },
1194};
1195
1196static struct clk_branch gcc_apss_ahb_clk = {
1197 .halt_reg = 0x4601c,
1198 .halt_check = BRANCH_HALT_VOTED,
1199 .clkr = {
1200 .enable_reg = 0x45004,
1201 .enable_mask = BIT(14),
1202 .hw.init = &(struct clk_init_data){
1203 .name = "gcc_apss_ahb_clk",
1204 .parent_names = (const char *[]){
1205 "apss_ahb_clk_src",
1206 },
1207 .num_parents = 1,
1208 .flags = CLK_SET_RATE_PARENT,
1209 .ops = &clk_branch2_ops,
1210 },
1211 },
1212};
1213
1214static struct clk_branch gcc_apss_tcu_clk = {
1215 .halt_reg = 0x5b004,
1216 .halt_check = BRANCH_VOTED,
1217 .clkr = {
1218 .enable_reg = 0x4500c,
1219 .enable_mask = BIT(1),
1220 .hw.init = &(struct clk_init_data){
1221 .name = "gcc_apss_tcu_clk",
1222 .ops = &clk_branch2_ops,
1223 },
1224 },
1225};
1226
1227static struct clk_branch gcc_bimc_gfx_clk = {
1228 .halt_reg = 0x59034,
1229 .halt_check = BRANCH_HALT,
1230 .clkr = {
1231 .enable_reg = 0x59034,
1232 .enable_mask = BIT(0),
1233 .hw.init = &(struct clk_init_data){
1234 .name = "gcc_bimc_gfx_clk",
1235 .ops = &clk_branch2_ops,
1236 .parent_names = (const char *[]){
1237 "gcc_apss_tcu_clk",
1238 },
1239
1240 },
1241 },
1242};
1243
1244static struct clk_branch gcc_bimc_gpu_clk = {
1245 .halt_reg = 0x59030,
1246 .halt_check = BRANCH_HALT,
1247 .clkr = {
1248 .enable_reg = 0x59030,
1249 .enable_mask = BIT(0),
1250 .hw.init = &(struct clk_init_data){
1251 .name = "gcc_bimc_gpu_clk",
1252 .ops = &clk_branch2_ops,
1253 },
1254 },
1255};
1256
1257static struct clk_branch gcc_bimc_mdss_clk = {
1258 .halt_reg = 0x31038,
1259 .halt_check = BRANCH_HALT,
1260 .clkr = {
1261 .enable_reg = 0x31038,
1262 .enable_mask = BIT(0),
1263 .hw.init = &(struct clk_init_data){
1264 .name = "gcc_bimc_mdss_clk",
1265 .ops = &clk_branch2_ops,
1266 },
1267 },
1268};
1269
1270static struct clk_branch gcc_blsp1_ahb_clk = {
1271 .halt_reg = 0x1008,
1272 .halt_check = BRANCH_HALT_VOTED,
1273 .clkr = {
1274 .enable_reg = 0x45004,
1275 .enable_mask = BIT(10),
1276 .hw.init = &(struct clk_init_data){
1277 .name = "gcc_blsp1_ahb_clk",
1278 .ops = &clk_branch2_ops,
1279 },
1280 },
1281};
1282
1283static struct clk_branch gcc_dcc_clk = {
1284 .halt_reg = 0x77004,
1285 .halt_check = BRANCH_HALT,
1286 .clkr = {
1287 .enable_reg = 0x77004,
1288 .enable_mask = BIT(0),
1289 .hw.init = &(struct clk_init_data){
1290 .name = "gcc_dcc_clk",
1291 .ops = &clk_branch2_ops,
1292 },
1293 },
1294};
1295
1296static struct clk_branch gcc_dcc_xo_clk = {
1297 .halt_reg = 0x77008,
1298 .halt_check = BRANCH_HALT,
1299 .clkr = {
1300 .enable_reg = 0x77008,
1301 .enable_mask = BIT(0),
1302 .hw.init = &(struct clk_init_data){
1303 .name = "gcc_dcc_xo_clk",
1304 .ops = &clk_branch2_ops,
1305 },
1306 },
1307};
1308
1309static struct clk_branch gcc_blsp1_qup0_i2c_apps_clk = {
1310 .halt_reg = 0x6028,
1311 .halt_check = BRANCH_HALT,
1312 .clkr = {
1313 .enable_reg = 0x6028,
1314 .enable_mask = BIT(0),
1315 .hw.init = &(struct clk_init_data){
1316 .name = "gcc_blsp1_qup0_i2c_apps_clk",
1317 .parent_names = (const char *[]){
1318 "blsp1_qup0_i2c_apps_clk_src",
1319 },
1320 .num_parents = 1,
1321 .flags = CLK_SET_RATE_PARENT,
1322 .ops = &clk_branch2_ops,
1323 },
1324 },
1325};
1326
1327static struct clk_branch gcc_blsp1_qup0_spi_apps_clk = {
1328 .halt_reg = 0x6024,
1329 .halt_check = BRANCH_HALT,
1330 .clkr = {
1331 .enable_reg = 0x6024,
1332 .enable_mask = BIT(0),
1333 .hw.init = &(struct clk_init_data){
1334 .name = "gcc_blsp1_qup0_spi_apps_clk",
1335 .parent_names = (const char *[]){
1336 "blsp1_qup0_spi_apps_clk_src",
1337 },
1338 .num_parents = 1,
1339 .flags = CLK_SET_RATE_PARENT,
1340 .ops = &clk_branch2_ops,
1341 },
1342 },
1343};
1344
1345static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1346 .halt_reg = 0x2008,
1347 .halt_check = BRANCH_HALT,
1348 .clkr = {
1349 .enable_reg = 0x2008,
1350 .enable_mask = BIT(0),
1351 .hw.init = &(struct clk_init_data){
1352 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1353 .parent_names = (const char *[]){
1354 "blsp1_qup1_i2c_apps_clk_src",
1355 },
1356 .num_parents = 1,
1357 .flags = CLK_SET_RATE_PARENT,
1358 .ops = &clk_branch2_ops,
1359 },
1360 },
1361};
1362
1363static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1364 .halt_reg = 0x2004,
1365 .halt_check = BRANCH_HALT,
1366 .clkr = {
1367 .enable_reg = 0x2004,
1368 .enable_mask = BIT(0),
1369 .hw.init = &(struct clk_init_data){
1370 .name = "gcc_blsp1_qup1_spi_apps_clk",
1371 .parent_names = (const char *[]){
1372 "blsp1_qup1_spi_apps_clk_src",
1373 },
1374 .num_parents = 1,
1375 .flags = CLK_SET_RATE_PARENT,
1376 .ops = &clk_branch2_ops,
1377 },
1378 },
1379};
1380
1381static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1382 .halt_reg = 0x3010,
1383 .halt_check = BRANCH_HALT,
1384 .clkr = {
1385 .enable_reg = 0x3010,
1386 .enable_mask = BIT(0),
1387 .hw.init = &(struct clk_init_data){
1388 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1389 .parent_names = (const char *[]){
1390 "blsp1_qup2_i2c_apps_clk_src",
1391 },
1392 .num_parents = 1,
1393 .flags = CLK_SET_RATE_PARENT,
1394 .ops = &clk_branch2_ops,
1395 },
1396 },
1397};
1398
1399static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1400 .halt_reg = 0x300c,
1401 .halt_check = BRANCH_HALT,
1402 .clkr = {
1403 .enable_reg = 0x300c,
1404 .enable_mask = BIT(0),
1405 .hw.init = &(struct clk_init_data){
1406 .name = "gcc_blsp1_qup2_spi_apps_clk",
1407 .parent_names = (const char *[]){
1408 "blsp1_qup2_spi_apps_clk_src",
1409 },
1410 .num_parents = 1,
1411 .flags = CLK_SET_RATE_PARENT,
1412 .ops = &clk_branch2_ops,
1413 },
1414 },
1415};
1416
1417static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1418 .halt_reg = 0x4020,
1419 .halt_check = BRANCH_HALT,
1420 .clkr = {
1421 .enable_reg = 0x4020,
1422 .enable_mask = BIT(0),
1423 .hw.init = &(struct clk_init_data){
1424 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1425 .parent_names = (const char *[]){
1426 "blsp1_qup3_i2c_apps_clk_src",
1427 },
1428 .num_parents = 1,
1429 .flags = CLK_SET_RATE_PARENT,
1430 .ops = &clk_branch2_ops,
1431 },
1432 },
1433};
1434
1435static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1436 .halt_reg = 0x401c,
1437 .halt_check = BRANCH_HALT,
1438 .clkr = {
1439 .enable_reg = 0x401c,
1440 .enable_mask = BIT(0),
1441 .hw.init = &(struct clk_init_data){
1442 .name = "gcc_blsp1_qup3_spi_apps_clk",
1443 .parent_names = (const char *[]){
1444 "blsp1_qup3_spi_apps_clk_src",
1445 },
1446 .num_parents = 1,
1447 .flags = CLK_SET_RATE_PARENT,
1448 .ops = &clk_branch2_ops,
1449 },
1450 },
1451};
1452
1453static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1454 .halt_reg = 0x5020,
1455 .halt_check = BRANCH_HALT,
1456 .clkr = {
1457 .enable_reg = 0x5020,
1458 .enable_mask = BIT(0),
1459 .hw.init = &(struct clk_init_data){
1460 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1461 .parent_names = (const char *[]){
1462 "blsp1_qup4_i2c_apps_clk_src",
1463 },
1464 .num_parents = 1,
1465 .flags = CLK_SET_RATE_PARENT,
1466 .ops = &clk_branch2_ops,
1467 },
1468 },
1469};
1470
1471static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1472 .halt_reg = 0x501c,
1473 .halt_check = BRANCH_HALT,
1474 .clkr = {
1475 .enable_reg = 0x501c,
1476 .enable_mask = BIT(0),
1477 .hw.init = &(struct clk_init_data){
1478 .name = "gcc_blsp1_qup4_spi_apps_clk",
1479 .parent_names = (const char *[]){
1480 "blsp1_qup4_spi_apps_clk_src",
1481 },
1482 .num_parents = 1,
1483 .flags = CLK_SET_RATE_PARENT,
1484 .ops = &clk_branch2_ops,
1485 },
1486 },
1487};
1488
1489static struct clk_branch gcc_blsp1_uart0_apps_clk = {
1490 .halt_reg = 0x6004,
1491 .halt_check = BRANCH_HALT,
1492 .clkr = {
1493 .enable_reg = 0x6004,
1494 .enable_mask = BIT(0),
1495 .hw.init = &(struct clk_init_data){
1496 .name = "gcc_blsp1_uart0_apps_clk",
1497 .parent_names = (const char *[]){
1498 "blsp1_uart0_apps_clk_src",
1499 },
1500 .num_parents = 1,
1501 .flags = CLK_SET_RATE_PARENT,
1502 .ops = &clk_branch2_ops,
1503 },
1504 },
1505};
1506
1507static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1508 .halt_reg = 0x203c,
1509 .halt_check = BRANCH_HALT,
1510 .clkr = {
1511 .enable_reg = 0x203c,
1512 .enable_mask = BIT(0),
1513 .hw.init = &(struct clk_init_data){
1514 .name = "gcc_blsp1_uart1_apps_clk",
1515 .parent_names = (const char *[]){
1516 "blsp1_uart1_apps_clk_src",
1517 },
1518 .num_parents = 1,
1519 .flags = CLK_SET_RATE_PARENT,
1520 .ops = &clk_branch2_ops,
1521 },
1522 },
1523};
1524
1525static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1526 .halt_reg = 0x302c,
1527 .halt_check = BRANCH_HALT,
1528 .clkr = {
1529 .enable_reg = 0x302c,
1530 .enable_mask = BIT(0),
1531 .hw.init = &(struct clk_init_data){
1532 .name = "gcc_blsp1_uart2_apps_clk",
1533 .parent_names = (const char *[]){
1534 "blsp1_uart2_apps_clk_src",
1535 },
1536 .num_parents = 1,
1537 .flags = CLK_SET_RATE_PARENT,
1538 .ops = &clk_branch2_ops,
1539 },
1540 },
1541};
1542
1543static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1544 .halt_reg = 0x400c,
1545 .halt_check = BRANCH_HALT,
1546 .clkr = {
1547 .enable_reg = 0x400c,
1548 .enable_mask = BIT(0),
1549 .hw.init = &(struct clk_init_data){
1550 .name = "gcc_blsp1_uart3_apps_clk",
1551 .parent_names = (const char *[]){
1552 "blsp1_uart3_apps_clk_src",
1553 },
1554 .num_parents = 1,
1555 .flags = CLK_SET_RATE_PARENT,
1556 .ops = &clk_branch2_ops,
1557 },
1558 },
1559};
1560
1561static struct clk_branch gcc_blsp2_ahb_clk = {
1562 .halt_reg = 0xb008,
1563 .halt_check = BRANCH_HALT_VOTED,
1564 .clkr = {
1565 .enable_reg = 0x45004,
1566 .enable_mask = BIT(20),
1567 .hw.init = &(struct clk_init_data){
1568 .name = "gcc_blsp2_ahb_clk",
1569 .ops = &clk_branch2_ops,
1570 },
1571 },
1572};
1573
1574static struct clk_branch gcc_blsp2_qup0_i2c_apps_clk = {
1575 .halt_reg = 0xc008,
1576 .halt_check = BRANCH_HALT,
1577 .clkr = {
1578 .enable_reg = 0xc008,
1579 .enable_mask = BIT(0),
1580 .hw.init = &(struct clk_init_data){
1581 .name = "gcc_blsp2_qup0_i2c_apps_clk",
1582 .parent_names = (const char *[]){
1583 "blsp2_qup0_i2c_apps_clk_src",
1584 },
1585 .num_parents = 1,
1586 .flags = CLK_SET_RATE_PARENT,
1587 .ops = &clk_branch2_ops,
1588 },
1589 },
1590};
1591
1592static struct clk_branch gcc_blsp2_qup0_spi_apps_clk = {
1593 .halt_reg = 0xc004,
1594 .halt_check = BRANCH_HALT,
1595 .clkr = {
1596 .enable_reg = 0xc004,
1597 .enable_mask = BIT(0),
1598 .hw.init = &(struct clk_init_data){
1599 .name = "gcc_blsp2_qup0_spi_apps_clk",
1600 .parent_names = (const char *[]){
1601 "blsp2_qup0_spi_apps_clk_src",
1602 },
1603 .num_parents = 1,
1604 .flags = CLK_SET_RATE_PARENT,
1605 .ops = &clk_branch2_ops,
1606 },
1607 },
1608};
1609
1610static struct clk_branch gcc_blsp2_uart0_apps_clk = {
1611 .halt_reg = 0xc03c,
1612 .halt_check = BRANCH_HALT,
1613 .clkr = {
1614 .enable_reg = 0xc03c,
1615 .enable_mask = BIT(0),
1616 .hw.init = &(struct clk_init_data){
1617 .name = "gcc_blsp2_uart0_apps_clk",
1618 .parent_names = (const char *[]){
1619 "blsp2_uart0_apps_clk_src",
1620 },
1621 .num_parents = 1,
1622 .flags = CLK_SET_RATE_PARENT,
1623 .ops = &clk_branch2_ops,
1624 },
1625 },
1626};
1627
1628static struct clk_branch gcc_boot_rom_ahb_clk = {
1629 .halt_reg = 0x1300c,
1630 .halt_check = BRANCH_HALT_VOTED,
1631 .clkr = {
1632 .enable_reg = 0x45004,
1633 .enable_mask = BIT(7),
1634 .hw.init = &(struct clk_init_data){
1635 .name = "gcc_boot_rom_ahb_clk",
1636 .ops = &clk_branch2_ops,
1637 },
1638 },
1639};
1640
1641static struct clk_branch gcc_crypto_ahb_clk = {
1642 .halt_reg = 0x16024,
1643 .halt_check = BRANCH_VOTED,
1644 .clkr = {
1645 .enable_reg = 0x45004,
1646 .enable_mask = BIT(0),
1647 .hw.init = &(struct clk_init_data){
1648 .name = "gcc_crypto_ahb_clk",
1649 .ops = &clk_branch2_ops,
1650 },
1651 },
1652};
1653
1654static struct clk_branch gcc_crypto_axi_clk = {
1655 .halt_reg = 0x16020,
1656 .halt_check = BRANCH_VOTED,
1657 .clkr = {
1658 .enable_reg = 0x45004,
1659 .enable_mask = BIT(1),
1660 .hw.init = &(struct clk_init_data){
1661 .name = "gcc_crypto_axi_clk",
1662 .ops = &clk_branch2_ops,
1663 },
1664 },
1665};
1666
1667static struct clk_branch gcc_crypto_clk = {
1668 .halt_reg = 0x1601c,
1669 .halt_check = BRANCH_VOTED,
1670 .clkr = {
1671 .enable_reg = 0x45004,
1672 .enable_mask = BIT(2),
1673 .hw.init = &(struct clk_init_data){
1674 .name = "gcc_crypto_clk",
1675 .ops = &clk_branch2_ops,
1676 },
1677 },
1678};
1679
1680static struct clk_branch gcc_eth_axi_clk = {
1681 .halt_reg = 0x4e010,
1682 .halt_check = BRANCH_HALT,
1683 .clkr = {
1684 .enable_reg = 0x4e010,
1685 .enable_mask = BIT(0),
1686 .hw.init = &(struct clk_init_data){
1687 .name = "gcc_eth_axi_clk",
1688 .ops = &clk_branch2_ops,
1689 },
1690 },
1691};
1692
1693static struct clk_branch gcc_eth_ptp_clk = {
1694 .halt_reg = 0x4e004,
1695 .halt_check = BRANCH_HALT,
1696 .clkr = {
1697 .enable_reg = 0x4e004,
1698 .enable_mask = BIT(0),
1699 .hw.init = &(struct clk_init_data){
1700 .name = "gcc_eth_ptp_clk",
1701 .parent_names = (const char *[]){
1702 "emac_ptp_clk_src",
1703 },
1704 .num_parents = 1,
1705 .flags = CLK_SET_RATE_PARENT,
1706 .ops = &clk_branch2_ops,
1707 },
1708 },
1709};
1710
1711static struct clk_branch gcc_eth_rgmii_clk = {
1712 .halt_reg = 0x4e008,
1713 .halt_check = BRANCH_HALT,
1714 .clkr = {
1715 .enable_reg = 0x4e008,
1716 .enable_mask = BIT(0),
1717 .hw.init = &(struct clk_init_data){
1718 .name = "gcc_eth_rgmii_clk",
1719 .parent_names = (const char *[]){
1720 "emac_clk_src",
1721 },
1722 .num_parents = 1,
1723 .flags = CLK_SET_RATE_PARENT,
1724 .ops = &clk_branch2_ops,
1725 },
1726 },
1727};
1728
1729static struct clk_branch gcc_eth_slave_ahb_clk = {
1730 .halt_reg = 0x4e00c,
1731 .halt_check = BRANCH_HALT,
1732 .clkr = {
1733 .enable_reg = 0x4e00c,
1734 .enable_mask = BIT(0),
1735 .hw.init = &(struct clk_init_data){
1736 .name = "gcc_eth_slave_ahb_clk",
1737 .ops = &clk_branch2_ops,
1738 },
1739 },
1740};
1741
1742static struct clk_branch gcc_geni_ir_s_clk = {
1743 .halt_reg = 0xf008,
1744 .halt_check = BRANCH_HALT,
1745 .clkr = {
1746 .enable_reg = 0xf008,
1747 .enable_mask = BIT(0),
1748 .hw.init = &(struct clk_init_data){
1749 .name = "gcc_geni_ir_s_clk",
1750 .ops = &clk_branch2_ops,
1751 },
1752 },
1753};
1754
1755static struct clk_branch gcc_geni_ir_h_clk = {
1756 .halt_reg = 0xf004,
1757 .halt_check = BRANCH_HALT,
1758 .clkr = {
1759 .enable_reg = 0xf004,
1760 .enable_mask = BIT(0),
1761 .hw.init = &(struct clk_init_data){
1762 .name = "gcc_geni_ir_h_clk",
1763 .ops = &clk_branch2_ops,
1764 },
1765 },
1766};
1767
1768static struct clk_branch gcc_gfx_tcu_clk = {
1769 .halt_reg = 0x12020,
1770 .halt_check = BRANCH_VOTED,
1771 .clkr = {
1772 .enable_reg = 0x4500C,
1773 .enable_mask = BIT(2),
1774 .hw.init = &(struct clk_init_data){
1775 .name = "gcc_gfx_tcu_clk",
1776 .ops = &clk_branch2_ops,
1777 },
1778 },
1779};
1780
1781static struct clk_branch gcc_gfx_tbu_clk = {
1782 .halt_reg = 0x12010,
1783 .halt_check = BRANCH_VOTED,
1784 .clkr = {
1785 .enable_reg = 0x4500C,
1786 .enable_mask = BIT(3),
1787 .hw.init = &(struct clk_init_data){
1788 .name = "gcc_gfx_tbu_clk",
1789 .ops = &clk_branch2_ops,
1790 },
1791 },
1792};
1793
1794static struct clk_branch gcc_gp1_clk = {
1795 .halt_reg = 0x8000,
1796 .halt_check = BRANCH_HALT,
1797 .clkr = {
1798 .enable_reg = 0x8000,
1799 .enable_mask = BIT(0),
1800 .hw.init = &(struct clk_init_data){
1801 .name = "gcc_gp1_clk",
1802 .parent_names = (const char *[]){
1803 "gp1_clk_src",
1804 },
1805 .num_parents = 1,
1806 .flags = CLK_SET_RATE_PARENT,
1807 .ops = &clk_branch2_ops,
1808 },
1809 },
1810};
1811
1812static struct clk_branch gcc_gp2_clk = {
1813 .halt_reg = 0x9000,
1814 .halt_check = BRANCH_HALT,
1815 .clkr = {
1816 .enable_reg = 0x9000,
1817 .enable_mask = BIT(0),
1818 .hw.init = &(struct clk_init_data){
1819 .name = "gcc_gp2_clk",
1820 .parent_names = (const char *[]){
1821 "gp2_clk_src",
1822 },
1823 .num_parents = 1,
1824 .flags = CLK_SET_RATE_PARENT,
1825 .ops = &clk_branch2_ops,
1826 },
1827 },
1828};
1829
1830static struct clk_branch gcc_gp3_clk = {
1831 .halt_reg = 0xa000,
1832 .halt_check = BRANCH_HALT,
1833 .clkr = {
1834 .enable_reg = 0xa000,
1835 .enable_mask = BIT(0),
1836 .hw.init = &(struct clk_init_data){
1837 .name = "gcc_gp3_clk",
1838 .parent_names = (const char *[]){
1839 "gp3_clk_src",
1840 },
1841 .num_parents = 1,
1842 .flags = CLK_SET_RATE_PARENT,
1843 .ops = &clk_branch2_ops,
1844 },
1845 },
1846};
1847
1848static struct clk_branch gcc_gtcu_ahb_clk = {
1849 .halt_reg = 0x12044,
1850 .halt_check = BRANCH_VOTED,
1851 .clkr = {
1852 .enable_reg = 0x4500c,
1853 .enable_mask = BIT(13),
1854 .hw.init = &(struct clk_init_data){
1855 .name = "gcc_gtcu_ahb_clk",
1856 .ops = &clk_branch2_ops,
1857 },
1858 },
1859};
1860
1861static struct clk_branch gcc_mdp_tbu_clk = {
1862 .halt_reg = 0x1201c,
1863 .halt_check = BRANCH_VOTED,
1864 .clkr = {
1865 .enable_reg = 0x4500c,
1866 .enable_mask = BIT(4),
1867 .hw.init = &(struct clk_init_data){
1868 .name = "gcc_mdp_tbu_clk",
1869 .ops = &clk_branch2_ops,
1870 },
1871 },
1872};
1873
1874static struct clk_branch gcc_mdss_ahb_clk = {
1875 .halt_reg = 0x4d07c,
1876 .halt_check = BRANCH_HALT,
1877 .clkr = {
1878 .enable_reg = 0x4d07c,
1879 .enable_mask = BIT(0),
1880 .hw.init = &(struct clk_init_data){
1881 .name = "gcc_mdss_ahb_clk",
1882 .ops = &clk_branch2_ops,
1883 },
1884 },
1885};
1886
1887static struct clk_branch gcc_mdss_axi_clk = {
1888 .halt_reg = 0x4d080,
1889 .halt_check = BRANCH_HALT,
1890 .clkr = {
1891 .enable_reg = 0x4d080,
1892 .enable_mask = BIT(0),
1893 .hw.init = &(struct clk_init_data){
1894 .name = "gcc_mdss_axi_clk",
1895 .ops = &clk_branch2_ops,
1896 },
1897 },
1898};
1899
1900static struct clk_branch gcc_mdss_byte0_clk = {
1901 .halt_reg = 0x4d094,
1902 .halt_check = BRANCH_HALT,
1903 .clkr = {
1904 .enable_reg = 0x4d094,
1905 .enable_mask = BIT(0),
1906 .hw.init = &(struct clk_init_data){
1907 .name = "gcc_mdss_byte0_clk",
1908 .parent_names = (const char *[]){
1909 "byte0_clk_src",
1910 },
1911 .num_parents = 1,
1912 .flags = CLK_SET_RATE_PARENT,
1913 .ops = &clk_branch2_ops,
1914 },
1915 },
1916};
1917
1918static struct clk_branch gcc_mdss_esc0_clk = {
1919 .halt_reg = 0x4d098,
1920 .halt_check = BRANCH_HALT,
1921 .clkr = {
1922 .enable_reg = 0x4d098,
1923 .enable_mask = BIT(0),
1924 .hw.init = &(struct clk_init_data){
1925 .name = "gcc_mdss_esc0_clk",
1926 .parent_names = (const char *[]){
1927 "esc0_clk_src",
1928 },
1929 .num_parents = 1,
1930 .flags = CLK_SET_RATE_PARENT,
1931 .ops = &clk_branch2_ops,
1932 },
1933 },
1934};
1935
1936static struct clk_branch gcc_mdss_hdmi_app_clk = {
1937 .halt_reg = 0x4d0d8,
1938 .halt_check = BRANCH_HALT,
1939 .clkr = {
1940 .enable_reg = 0x4d0d8,
1941 .enable_mask = BIT(0),
1942 .hw.init = &(struct clk_init_data){
1943 .name = "gcc_mdss_hdmi_app_clk",
1944 .parent_names = (const char *[]){
1945 "hdmi_app_clk_src",
1946 },
1947 .num_parents = 1,
1948 .flags = CLK_SET_RATE_PARENT,
1949 .ops = &clk_branch2_ops,
1950 },
1951 },
1952};
1953
1954static struct clk_branch gcc_mdss_hdmi_pclk_clk = {
1955 .halt_reg = 0x4d0d4,
1956 .halt_check = BRANCH_HALT,
1957 .clkr = {
1958 .enable_reg = 0x4d0d4,
1959 .enable_mask = BIT(0),
1960 .hw.init = &(struct clk_init_data){
1961 .name = "gcc_mdss_hdmi_pclk_clk",
1962 .parent_names = (const char *[]){
1963 "hdmi_pclk_clk_src",
1964 },
1965 .num_parents = 1,
1966 .flags = CLK_SET_RATE_PARENT,
1967 .ops = &clk_branch2_ops,
1968 },
1969 },
1970};
1971
1972static struct clk_branch gcc_mdss_mdp_clk = {
1973 .halt_reg = 0x4d088,
1974 .halt_check = BRANCH_HALT,
1975 .clkr = {
1976 .enable_reg = 0x4d088,
1977 .enable_mask = BIT(0),
1978 .hw.init = &(struct clk_init_data){
1979 .name = "gcc_mdss_mdp_clk",
1980 .parent_names = (const char *[]){
1981 "mdp_clk_src",
1982 },
1983 .num_parents = 1,
1984 .flags = CLK_SET_RATE_PARENT,
1985 .ops = &clk_branch2_ops,
1986 },
1987 },
1988};
1989
1990static struct clk_branch gcc_mdss_pclk0_clk = {
1991 .halt_reg = 0x4d084,
1992 .halt_check = BRANCH_HALT,
1993 .clkr = {
1994 .enable_reg = 0x4d084,
1995 .enable_mask = BIT(0),
1996 .hw.init = &(struct clk_init_data){
1997 .name = "gcc_mdss_pclk0_clk",
1998 .parent_names = (const char *[]){
1999 "pclk0_clk_src",
2000 },
2001 .num_parents = 1,
2002 .flags = CLK_SET_RATE_PARENT,
2003 .ops = &clk_branch2_ops,
2004 },
2005 },
2006};
2007
2008static struct clk_branch gcc_mdss_vsync_clk = {
2009 .halt_reg = 0x4d090,
2010 .halt_check = BRANCH_HALT,
2011 .clkr = {
2012 .enable_reg = 0x4d090,
2013 .enable_mask = BIT(0),
2014 .hw.init = &(struct clk_init_data){
2015 .name = "gcc_mdss_vsync_clk",
2016 .parent_names = (const char *[]){
2017 "vsync_clk_src",
2018 },
2019 .num_parents = 1,
2020 .flags = CLK_SET_RATE_PARENT,
2021 .ops = &clk_branch2_ops,
2022 },
2023 },
2024};
2025
2026static struct clk_branch gcc_oxili_ahb_clk = {
2027 .halt_reg = 0x59028,
2028 .halt_check = BRANCH_HALT,
2029 .clkr = {
2030 .enable_reg = 0x59028,
2031 .enable_mask = BIT(0),
2032 .hw.init = &(struct clk_init_data){
2033 .name = "gcc_oxili_ahb_clk",
2034 .ops = &clk_branch2_ops,
2035 },
2036 },
2037};
2038
2039static struct clk_branch gcc_oxili_gfx3d_clk = {
2040 .halt_reg = 0x59020,
2041 .halt_check = BRANCH_HALT,
2042 .clkr = {
2043 .enable_reg = 0x59020,
2044 .enable_mask = BIT(0),
2045 .hw.init = &(struct clk_init_data){
2046 .name = "gcc_oxili_gfx3d_clk",
2047 .parent_names = (const char *[]){
2048 "gfx3d_clk_src",
2049 },
2050 .num_parents = 1,
2051 .flags = CLK_SET_RATE_PARENT,
2052 .ops = &clk_branch2_ops,
2053 },
2054 },
2055};
2056
2057static struct clk_branch gcc_pcie_0_aux_clk = {
2058 .halt_reg = 0x3e014,
2059 .halt_check = BRANCH_HALT_VOTED,
2060 .clkr = {
2061 .enable_reg = 0x45004,
2062 .enable_mask = BIT(27),
2063 .hw.init = &(struct clk_init_data){
2064 .name = "gcc_pcie_0_aux_clk",
2065 .parent_names = (const char *[]){
2066 "pcie_0_aux_clk_src",
2067 },
2068 .num_parents = 1,
2069 .flags = CLK_SET_RATE_PARENT,
2070 .ops = &clk_branch2_ops,
2071 },
2072 },
2073};
2074
2075static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2076 .halt_reg = 0x3e008,
2077 .halt_check = BRANCH_HALT_VOTED,
2078 .clkr = {
2079 .enable_reg = 0x45004,
2080 .enable_mask = BIT(11),
2081 .hw.init = &(struct clk_init_data){
2082 .name = "gcc_pcie_0_cfg_ahb_clk",
2083 .ops = &clk_branch2_ops,
2084 },
2085 },
2086};
2087
2088static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2089 .halt_reg = 0x3e018,
2090 .halt_check = BRANCH_HALT_VOTED,
2091 .clkr = {
2092 .enable_reg = 0x45004,
2093 .enable_mask = BIT(18),
2094 .hw.init = &(struct clk_init_data){
2095 .name = "gcc_pcie_0_mstr_axi_clk",
2096 .ops = &clk_branch2_ops,
2097 },
2098 },
2099};
2100
2101static struct clk_branch gcc_pcie_0_pipe_clk = {
2102 .halt_reg = 0x3e00c,
2103 .halt_check = BRANCH_HALT_VOTED,
2104 .clkr = {
2105 .enable_reg = 0x45004,
2106 .enable_mask = BIT(28),
2107 .hw.init = &(struct clk_init_data){
2108 .name = "gcc_pcie_0_pipe_clk",
2109 .parent_names = (const char *[]){
2110 "pcie_0_pipe_clk_src",
2111 },
2112 .num_parents = 1,
2113 .flags = CLK_SET_RATE_PARENT,
2114 .ops = &clk_branch2_ops,
2115 },
2116 },
2117};
2118
2119static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2120 .halt_reg = 0x3e010,
2121 .halt_check = BRANCH_HALT_VOTED,
2122 .clkr = {
2123 .enable_reg = 0x45004,
2124 .enable_mask = BIT(22),
2125 .hw.init = &(struct clk_init_data){
2126 .name = "gcc_pcie_0_slv_axi_clk",
2127 .ops = &clk_branch2_ops,
2128 },
2129 },
2130};
2131
2132static struct clk_branch gcc_pcnoc_usb2_clk = {
2133 .halt_reg = 0x27008,
2134 .halt_check = BRANCH_HALT,
2135 .clkr = {
2136 .enable_reg = 0x27008,
2137 .enable_mask = BIT(0),
2138 .hw.init = &(struct clk_init_data){
2139 .name = "gcc_pcnoc_usb2_clk",
2140 .flags = CLK_IS_CRITICAL,
2141 .ops = &clk_branch2_ops,
2142 },
2143 },
2144};
2145
2146static struct clk_branch gcc_pcnoc_usb3_clk = {
2147 .halt_reg = 0x2700c,
2148 .halt_check = BRANCH_HALT,
2149 .clkr = {
2150 .enable_reg = 0x2700c,
2151 .enable_mask = BIT(0),
2152 .hw.init = &(struct clk_init_data){
2153 .name = "gcc_pcnoc_usb3_clk",
2154 .flags = CLK_IS_CRITICAL,
2155 .ops = &clk_branch2_ops,
2156 },
2157 },
2158};
2159
2160static struct clk_branch gcc_pdm2_clk = {
2161 .halt_reg = 0x4400c,
2162 .halt_check = BRANCH_HALT,
2163 .clkr = {
2164 .enable_reg = 0x4400c,
2165 .enable_mask = BIT(0),
2166 .hw.init = &(struct clk_init_data){
2167 .name = "gcc_pdm2_clk",
2168 .parent_names = (const char *[]){
2169 "pdm2_clk_src",
2170 },
2171 .num_parents = 1,
2172 .flags = CLK_SET_RATE_PARENT,
2173 .ops = &clk_branch2_ops,
2174 },
2175 },
2176};
2177
2178static struct clk_branch gcc_pdm_ahb_clk = {
2179 .halt_reg = 0x44004,
2180 .halt_check = BRANCH_HALT,
2181 .clkr = {
2182 .enable_reg = 0x44004,
2183 .enable_mask = BIT(0),
2184 .hw.init = &(struct clk_init_data){
2185 .name = "gcc_pdm_ahb_clk",
2186 .ops = &clk_branch2_ops,
2187 },
2188 },
2189};
2190
2191static struct clk_branch gcc_prng_ahb_clk = {
2192 .halt_reg = 0x13004,
2193 .halt_check = BRANCH_HALT_VOTED,
2194 .clkr = {
2195 .enable_reg = 0x45004,
2196 .enable_mask = BIT(8),
2197 .hw.init = &(struct clk_init_data){
2198 .name = "gcc_prng_ahb_clk",
2199 .ops = &clk_branch2_ops,
2200 },
2201 },
2202};
2203
2204/* PWM clks do not have XO as parent as src clk is a balance root */
2205static struct clk_branch gcc_pwm0_xo512_clk = {
2206 .halt_reg = 0x44018,
2207 .halt_check = BRANCH_HALT,
2208 .clkr = {
2209 .enable_reg = 0x44018,
2210 .enable_mask = BIT(0),
2211 .hw.init = &(struct clk_init_data){
2212 .name = "gcc_pwm0_xo512_clk",
2213 .ops = &clk_branch2_ops,
2214 },
2215 },
2216};
2217
2218static struct clk_branch gcc_pwm1_xo512_clk = {
2219 .halt_reg = 0x49004,
2220 .halt_check = BRANCH_HALT,
2221 .clkr = {
2222 .enable_reg = 0x49004,
2223 .enable_mask = BIT(0),
2224 .hw.init = &(struct clk_init_data){
2225 .name = "gcc_pwm1_xo512_clk",
2226 .ops = &clk_branch2_ops,
2227 },
2228 },
2229};
2230
2231static struct clk_branch gcc_pwm2_xo512_clk = {
2232 .halt_reg = 0x4a004,
2233 .halt_check = BRANCH_HALT,
2234 .clkr = {
2235 .enable_reg = 0x4a004,
2236 .enable_mask = BIT(0),
2237 .hw.init = &(struct clk_init_data){
2238 .name = "gcc_pwm2_xo512_clk",
2239 .ops = &clk_branch2_ops,
2240 },
2241 },
2242};
2243
2244static struct clk_branch gcc_qdss_dap_clk = {
2245 .halt_reg = 0x29084,
2246 .halt_check = BRANCH_VOTED,
2247 .clkr = {
2248 .enable_reg = 0x45004,
2249 .enable_mask = BIT(21),
2250 .hw.init = &(struct clk_init_data){
2251 .name = "gcc_qdss_dap_clk",
2252 .ops = &clk_branch2_ops,
2253 },
2254 },
2255};
2256
2257static struct clk_branch gcc_sdcc1_ahb_clk = {
2258 .halt_reg = 0x4201c,
2259 .halt_check = BRANCH_HALT,
2260 .clkr = {
2261 .enable_reg = 0x4201c,
2262 .enable_mask = BIT(0),
2263 .hw.init = &(struct clk_init_data){
2264 .name = "gcc_sdcc1_ahb_clk",
2265 .ops = &clk_branch2_ops,
2266 },
2267 },
2268};
2269
2270static struct clk_branch gcc_sdcc1_apps_clk = {
2271 .halt_reg = 0x42018,
2272 .halt_check = BRANCH_HALT,
2273 .clkr = {
2274 .enable_reg = 0x42018,
2275 .enable_mask = BIT(0),
2276 .hw.init = &(struct clk_init_data){
2277 .name = "gcc_sdcc1_apps_clk",
2278 .parent_names = (const char *[]){
2279 "sdcc1_apps_clk_src",
2280 },
2281 .num_parents = 1,
2282 .flags = CLK_SET_RATE_PARENT,
2283 .ops = &clk_branch2_ops,
2284 },
2285 },
2286};
2287
2288static struct clk_branch gcc_sdcc1_ice_core_clk = {
2289 .halt_reg = 0x5d014,
2290 .halt_check = BRANCH_HALT,
2291 .clkr = {
2292 .enable_reg = 0x5d014,
2293 .enable_mask = BIT(0),
2294 .hw.init = &(struct clk_init_data){
2295 .name = "gcc_sdcc1_ice_core_clk",
2296 .parent_names = (const char *[]){
2297 "sdcc1_ice_core_clk_src",
2298 },
2299 .num_parents = 1,
2300 .flags = CLK_SET_RATE_PARENT,
2301 .ops = &clk_branch2_ops,
2302 },
2303 },
2304};
2305
2306static struct clk_branch gcc_sdcc2_ahb_clk = {
2307 .halt_reg = 0x4301c,
2308 .halt_check = BRANCH_HALT,
2309 .clkr = {
2310 .enable_reg = 0x4301c,
2311 .enable_mask = BIT(0),
2312 .hw.init = &(struct clk_init_data){
2313 .name = "gcc_sdcc2_ahb_clk",
2314 .ops = &clk_branch2_ops,
2315 },
2316 },
2317};
2318
2319static struct clk_branch gcc_sdcc2_apps_clk = {
2320 .halt_reg = 0x43018,
2321 .halt_check = BRANCH_HALT,
2322 .clkr = {
2323 .enable_reg = 0x43018,
2324 .enable_mask = BIT(0),
2325 .hw.init = &(struct clk_init_data){
2326 .name = "gcc_sdcc2_apps_clk",
2327 .parent_names = (const char *[]){
2328 "sdcc2_apps_clk_src",
2329 },
2330 .num_parents = 1,
2331 .flags = CLK_SET_RATE_PARENT,
2332 .ops = &clk_branch2_ops,
2333 },
2334 },
2335};
2336
2337static struct clk_branch gcc_smmu_cfg_clk = {
2338 .halt_reg = 0x12038,
2339 .halt_check = BRANCH_VOTED,
2340 .clkr = {
2341 .enable_reg = 0x3600C,
2342 .enable_mask = BIT(12),
2343 .hw.init = &(struct clk_init_data){
2344 .name = "gcc_smmu_cfg_clk",
2345 .ops = &clk_branch2_ops,
2346 },
2347 },
2348};
2349
2350static struct clk_branch gcc_sys_noc_usb3_clk = {
2351 .halt_reg = 0x26014,
2352 .halt_check = BRANCH_HALT,
2353 .clkr = {
2354 .enable_reg = 0x26014,
2355 .enable_mask = BIT(0),
2356 .hw.init = &(struct clk_init_data){
2357 .name = "gcc_sys_noc_usb3_clk",
2358 .parent_names = (const char *[]){
2359 "usb30_master_clk_src",
2360 },
2361 .num_parents = 1,
2362 .ops = &clk_branch2_ops,
2363 },
2364 },
2365};
2366
2367static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
2368 .halt_reg = 0x4100C,
2369 .halt_check = BRANCH_HALT,
2370 .clkr = {
2371 .enable_reg = 0x4100C,
2372 .enable_mask = BIT(0),
2373 .hw.init = &(struct clk_init_data){
2374 .name = "gcc_usb_hs_inactivity_timers_clk",
2375 .ops = &clk_branch2_ops,
2376 },
2377 },
2378};
2379
2380static struct clk_branch gcc_usb20_mock_utmi_clk = {
2381 .halt_reg = 0x41044,
2382 .halt_check = BRANCH_HALT,
2383 .clkr = {
2384 .enable_reg = 0x41044,
2385 .enable_mask = BIT(0),
2386 .hw.init = &(struct clk_init_data){
2387 .name = "gcc_usb20_mock_utmi_clk",
2388 .parent_names = (const char *[]){
2389 "usb20_mock_utmi_clk_src",
2390 },
2391 .num_parents = 1,
2392 .flags = CLK_SET_RATE_PARENT,
2393 .ops = &clk_branch2_ops,
2394 },
2395 },
2396};
2397
2398static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2399 .halt_reg = 0x4102c,
2400 .halt_check = BRANCH_HALT,
2401 .clkr = {
2402 .enable_reg = 0x4102c,
2403 .enable_mask = BIT(0),
2404 .hw.init = &(struct clk_init_data){
2405 .name = "gcc_usb2a_phy_sleep_clk",
2406 .ops = &clk_branch2_ops,
2407 },
2408 },
2409};
2410
2411static struct clk_branch gcc_usb30_master_clk = {
2412 .halt_reg = 0x3900c,
2413 .halt_check = BRANCH_HALT,
2414 .clkr = {
2415 .enable_reg = 0x3900c,
2416 .enable_mask = BIT(0),
2417 .hw.init = &(struct clk_init_data){
2418 .name = "gcc_usb30_master_clk",
2419 .parent_names = (const char *[]){
2420 "usb30_master_clk_src",
2421 },
2422 .num_parents = 1,
2423 .flags = CLK_SET_RATE_PARENT,
2424 .ops = &clk_branch2_ops,
2425 },
2426 },
2427};
2428
2429static struct clk_branch gcc_usb30_mock_utmi_clk = {
2430 .halt_reg = 0x39014,
2431 .halt_check = BRANCH_HALT,
2432 .clkr = {
2433 .enable_reg = 0x39014,
2434 .enable_mask = BIT(0),
2435 .hw.init = &(struct clk_init_data){
2436 .name = "gcc_usb30_mock_utmi_clk",
2437 .parent_names = (const char *[]){
2438 "usb30_mock_utmi_clk_src",
2439 },
2440 .num_parents = 1,
2441 .flags = CLK_SET_RATE_PARENT,
2442 .ops = &clk_branch2_ops,
2443 },
2444 },
2445};
2446
2447static struct clk_branch gcc_usb30_sleep_clk = {
2448 .halt_reg = 0x39010,
2449 .halt_check = BRANCH_HALT,
2450 .clkr = {
2451 .enable_reg = 0x39010,
2452 .enable_mask = BIT(0),
2453 .hw.init = &(struct clk_init_data){
2454 .name = "gcc_usb30_sleep_clk",
2455 .ops = &clk_branch2_ops,
2456 },
2457 },
2458};
2459
2460static struct clk_branch gcc_usb3_phy_aux_clk = {
2461 .halt_reg = 0x39044,
2462 .halt_check = BRANCH_HALT,
2463 .clkr = {
2464 .enable_reg = 0x39044,
2465 .enable_mask = BIT(0),
2466 .hw.init = &(struct clk_init_data){
2467 .name = "gcc_usb3_phy_aux_clk",
2468 .parent_names = (const char *[]){
2469 "usb3_phy_aux_clk_src",
2470 },
2471 .num_parents = 1,
2472 .flags = CLK_SET_RATE_PARENT,
2473 .ops = &clk_branch2_ops,
2474 },
2475 },
2476};
2477
2478static struct clk_branch gcc_usb3_phy_pipe_clk = {
2479 .halt_check = BRANCH_HALT_SKIP,
2480 .clkr = {
2481 .enable_reg = 0x39018,
2482 .enable_mask = BIT(0),
2483 .hw.init = &(struct clk_init_data){
2484 .name = "gcc_usb3_phy_pipe_clk",
2485 .ops = &clk_branch2_ops,
2486 },
2487 },
2488};
2489
2490static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {
2491 .halt_reg = 0x41030,
2492 .halt_check = BRANCH_HALT,
2493 .clkr = {
2494 .enable_reg = 0x41030,
2495 .enable_mask = BIT(0),
2496 .hw.init = &(struct clk_init_data){
2497 .name = "gcc_usb_hs_phy_cfg_ahb_clk",
2498 .ops = &clk_branch2_ops,
2499 },
2500 },
2501};
2502
2503static struct clk_branch gcc_usb_hs_system_clk = {
2504 .halt_reg = 0x41004,
2505 .halt_check = BRANCH_HALT,
2506 .clkr = {
2507 .enable_reg = 0x41004,
2508 .enable_mask = BIT(0),
2509 .hw.init = &(struct clk_init_data){
2510 .name = "gcc_usb_hs_system_clk",
2511 .parent_names = (const char *[]){
2512 "usb_hs_system_clk_src",
2513 },
2514 .num_parents = 1,
2515 .flags = CLK_SET_RATE_PARENT,
2516 .ops = &clk_branch2_ops,
2517 },
2518 },
2519};
2520
2521static struct clk_hw *gcc_qcs404_hws[] = {
2522 &cxo.hw,
2523};
2524
2525static struct clk_regmap *gcc_qcs404_clocks[] = {
2526 [GCC_APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
2527 [GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC] = &blsp1_qup0_i2c_apps_clk_src.clkr,
2528 [GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC] = &blsp1_qup0_spi_apps_clk_src.clkr,
2529 [GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2530 [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2531 [GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2532 [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2533 [GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2534 [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2535 [GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2536 [GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2537 [GCC_BLSP1_UART0_APPS_CLK_SRC] = &blsp1_uart0_apps_clk_src.clkr,
2538 [GCC_BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2539 [GCC_BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2540 [GCC_BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2541 [GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC] = &blsp2_qup0_i2c_apps_clk_src.clkr,
2542 [GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC] = &blsp2_qup0_spi_apps_clk_src.clkr,
2543 [GCC_BLSP2_UART0_APPS_CLK_SRC] = &blsp2_uart0_apps_clk_src.clkr,
2544 [GCC_BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2545 [GCC_EMAC_CLK_SRC] = &emac_clk_src.clkr,
2546 [GCC_EMAC_PTP_CLK_SRC] = &emac_ptp_clk_src.clkr,
2547 [GCC_ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2548 [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
2549 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
2550 [GCC_BIMC_MDSS_CLK] = &gcc_bimc_mdss_clk.clkr,
2551 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2552 [GCC_BLSP1_QUP0_I2C_APPS_CLK] = &gcc_blsp1_qup0_i2c_apps_clk.clkr,
2553 [GCC_BLSP1_QUP0_SPI_APPS_CLK] = &gcc_blsp1_qup0_spi_apps_clk.clkr,
2554 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2555 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2556 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2557 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2558 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2559 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2560 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2561 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2562 [GCC_BLSP1_UART0_APPS_CLK] = &gcc_blsp1_uart0_apps_clk.clkr,
2563 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2564 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2565 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2566 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2567 [GCC_BLSP2_QUP0_I2C_APPS_CLK] = &gcc_blsp2_qup0_i2c_apps_clk.clkr,
2568 [GCC_BLSP2_QUP0_SPI_APPS_CLK] = &gcc_blsp2_qup0_spi_apps_clk.clkr,
2569 [GCC_BLSP2_UART0_APPS_CLK] = &gcc_blsp2_uart0_apps_clk.clkr,
2570 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2571 [GCC_ETH_AXI_CLK] = &gcc_eth_axi_clk.clkr,
2572 [GCC_ETH_PTP_CLK] = &gcc_eth_ptp_clk.clkr,
2573 [GCC_ETH_RGMII_CLK] = &gcc_eth_rgmii_clk.clkr,
2574 [GCC_ETH_SLAVE_AHB_CLK] = &gcc_eth_slave_ahb_clk.clkr,
2575 [GCC_GENI_IR_S_CLK] = &gcc_geni_ir_s_clk.clkr,
2576 [GCC_GENI_IR_H_CLK] = &gcc_geni_ir_h_clk.clkr,
2577 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2578 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2579 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2580 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
2581 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
2582 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
2583 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
2584 [GCC_MDSS_HDMI_APP_CLK] = &gcc_mdss_hdmi_app_clk.clkr,
2585 [GCC_MDSS_HDMI_PCLK_CLK] = &gcc_mdss_hdmi_pclk_clk.clkr,
2586 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
2587 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
2588 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
2589 [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
2590 [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
2591 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2592 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2593 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2594 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2595 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2596 [GCC_PCNOC_USB2_CLK] = &gcc_pcnoc_usb2_clk.clkr,
2597 [GCC_PCNOC_USB3_CLK] = &gcc_pcnoc_usb3_clk.clkr,
2598 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2599 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2600 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2601 [GCC_PWM0_XO512_CLK] = &gcc_pwm0_xo512_clk.clkr,
2602 [GCC_PWM1_XO512_CLK] = &gcc_pwm1_xo512_clk.clkr,
2603 [GCC_PWM2_XO512_CLK] = &gcc_pwm2_xo512_clk.clkr,
2604 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2605 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2606 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2607 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2608 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2609 [GCC_SYS_NOC_USB3_CLK] = &gcc_sys_noc_usb3_clk.clkr,
2610 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
2611 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2612 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2613 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2614 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2615 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2616 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2617 [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
2618 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2619 [GCC_GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2620 [GCC_GP1_CLK_SRC] = &gp1_clk_src.clkr,
2621 [GCC_GP2_CLK_SRC] = &gp2_clk_src.clkr,
2622 [GCC_GP3_CLK_SRC] = &gp3_clk_src.clkr,
2623 [GCC_GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
2624 [GCC_GPLL0_AO_OUT_MAIN] = &gpll0_ao_out_main.clkr,
2625 [GCC_GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
2626 [GCC_GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
2627 [GCC_GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
2628 [GCC_GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
2629 [GCC_GPLL6] = &gpll6.clkr,
2630 [GCC_GPLL6_OUT_AUX] = &gpll6_out_aux,
2631 [GCC_HDMI_APP_CLK_SRC] = &hdmi_app_clk_src.clkr,
2632 [GCC_HDMI_PCLK_CLK_SRC] = &hdmi_pclk_clk_src.clkr,
2633 [GCC_MDP_CLK_SRC] = &mdp_clk_src.clkr,
2634 [GCC_PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2635 [GCC_PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2636 [GCC_PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2637 [GCC_PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2638 [GCC_SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2639 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
2640 [GCC_SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2641 [GCC_USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
2642 [GCC_USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2643 [GCC_USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2644 [GCC_USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2645 [GCC_USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2646 [GCC_VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2647 [GCC_USB_HS_INACTIVITY_TIMERS_CLK] =
2648 &gcc_usb_hs_inactivity_timers_clk.clkr,
2649 [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
2650 [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
2651 [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
2652 [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
2653 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
2654 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
2655 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
2656 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
2657 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
2658 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
2659 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
2660 [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
2661 [GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr,
2662};
2663
2664static const struct qcom_reset_map gcc_qcs404_resets[] = {
2665 [GCC_GENI_IR_BCR] = { 0x0F000 },
2666 [GCC_USB_HS_BCR] = { 0x41000 },
2667 [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
2668 [GCC_QUSB2_PHY_BCR] = { 0x4103c },
2669 [GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },
2670 [GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },
2671 [GCC_USB3_PHY_BCR] = { 0x39004 },
2672 [GCC_USB_30_BCR] = { 0x39000 },
2673 [GCC_USB3PHY_PHY_BCR] = { 0x39008 },
2674 [GCC_PCIE_0_BCR] = { 0x3e000 },
2675 [GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
2676 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
2677 [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
2678 [GCC_EMAC_BCR] = { 0x4e000 },
2679};
2680
2681static const struct regmap_config gcc_qcs404_regmap_config = {
2682 .reg_bits = 32,
2683 .reg_stride = 4,
2684 .val_bits = 32,
2685 .max_register = 0x7f000,
2686 .fast_io = true,
2687};
2688
2689static const struct qcom_cc_desc gcc_qcs404_desc = {
2690 .config = &gcc_qcs404_regmap_config,
2691 .clks = gcc_qcs404_clocks,
2692 .num_clks = ARRAY_SIZE(gcc_qcs404_clocks),
2693 .resets = gcc_qcs404_resets,
2694 .num_resets = ARRAY_SIZE(gcc_qcs404_resets),
2695};
2696
2697static const struct of_device_id gcc_qcs404_match_table[] = {
2698 { .compatible = "qcom,gcc-qcs404" },
2699 { }
2700};
2701MODULE_DEVICE_TABLE(of, gcc_qcs404_match_table);
2702
2703static int gcc_qcs404_probe(struct platform_device *pdev)
2704{
2705 struct regmap *regmap;
2706 int ret, i;
2707
2708 regmap = qcom_cc_map(pdev, &gcc_qcs404_desc);
2709 if (IS_ERR(regmap))
2710 return PTR_ERR(regmap);
2711
2712 clk_alpha_pll_configure(&gpll3_out_main, regmap, &gpll3_config);
2713
2714 for (i = 0; i < ARRAY_SIZE(gcc_qcs404_hws); i++) {
2715 ret = devm_clk_hw_register(&pdev->dev, gcc_qcs404_hws[i]);
2716 if (ret)
2717 return ret;
2718 }
2719
2720 return qcom_cc_really_probe(pdev, &gcc_qcs404_desc, regmap);
2721}
2722
2723static struct platform_driver gcc_qcs404_driver = {
2724 .probe = gcc_qcs404_probe,
2725 .driver = {
2726 .name = "gcc-qcs404",
2727 .of_match_table = gcc_qcs404_match_table,
2728 },
2729};
2730
2731static int __init gcc_qcs404_init(void)
2732{
2733 return platform_driver_register(&gcc_qcs404_driver);
2734}
2735subsys_initcall(gcc_qcs404_init);
2736
2737static void __exit gcc_qcs404_exit(void)
2738{
2739 platform_driver_unregister(&gcc_qcs404_driver);
2740}
2741module_exit(gcc_qcs404_exit);
2742
2743MODULE_DESCRIPTION("Qualcomm GCC QCS404 Driver");
2744MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-25 17:20:01 -0400