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path: root/drivers/clk/qcom/clk-regmap-divider.c
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Diffstat (limited to 'drivers/clk/qcom/clk-regmap-divider.c')
-rw-r--r--drivers/clk/qcom/clk-regmap-divider.c20
1 files changed, 6 insertions, 14 deletions
diff --git a/drivers/clk/qcom/clk-regmap-divider.c b/drivers/clk/qcom/clk-regmap-divider.c
index 4e9b8c2c8980..1ee75a5e93f4 100644
--- a/drivers/clk/qcom/clk-regmap-divider.c
+++ b/drivers/clk/qcom/clk-regmap-divider.c
@@ -28,22 +28,14 @@ static long div_round_ro_rate(struct clk_hw *hw, unsigned long rate,
28{ 28{
29 struct clk_regmap_div *divider = to_clk_regmap_div(hw); 29 struct clk_regmap_div *divider = to_clk_regmap_div(hw);
30 struct clk_regmap *clkr = &divider->clkr; 30 struct clk_regmap *clkr = &divider->clkr;
31 u32 div; 31 u32 val;
32 struct clk_hw *hw_parent = clk_hw_get_parent(hw);
33
34 regmap_read(clkr->regmap, divider->reg, &div);
35 div >>= divider->shift;
36 div &= BIT(divider->width) - 1;
37 div += 1;
38
39 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
40 if (!hw_parent)
41 return -EINVAL;
42 32
43 *prate = clk_hw_round_rate(hw_parent, rate * div); 33 regmap_read(clkr->regmap, divider->reg, &val);
44 } 34 val >>= divider->shift;
35 val &= BIT(divider->width) - 1;
45 36
46 return DIV_ROUND_UP_ULL((u64)*prate, div); 37 return divider_ro_round_rate(hw, rate, prate, NULL, divider->width,
38 CLK_DIVIDER_ROUND_CLOSEST, val);
47} 39}
48 40
49static long div_round_rate(struct clk_hw *hw, unsigned long rate, 41static long div_round_rate(struct clk_hw *hw, unsigned long rate,