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path: root/drivers/clk/meson/gxbb.c
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-rw-r--r--drivers/clk/meson/gxbb.c1591
1 files changed, 878 insertions, 713 deletions
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index af24455af5b4..b1e4d9557610 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -19,108 +19,19 @@
19 19
20#include <linux/clk.h> 20#include <linux/clk.h>
21#include <linux/clk-provider.h> 21#include <linux/clk-provider.h>
22#include <linux/init.h>
22#include <linux/of_address.h> 23#include <linux/of_address.h>
23#include <linux/of_device.h> 24#include <linux/of_device.h>
25#include <linux/mfd/syscon.h>
24#include <linux/platform_device.h> 26#include <linux/platform_device.h>
25#include <linux/init.h> 27#include <linux/regmap.h>
26 28
27#include "clkc.h" 29#include "clkc.h"
28#include "gxbb.h" 30#include "gxbb.h"
31#include "clk-regmap.h"
29 32
30static DEFINE_SPINLOCK(meson_clk_lock); 33static DEFINE_SPINLOCK(meson_clk_lock);
31 34
32static const struct pll_rate_table sys_pll_rate_table[] = {
33 PLL_RATE(24000000, 56, 1, 2),
34 PLL_RATE(48000000, 64, 1, 2),
35 PLL_RATE(72000000, 72, 1, 2),
36 PLL_RATE(96000000, 64, 1, 2),
37 PLL_RATE(120000000, 80, 1, 2),
38 PLL_RATE(144000000, 96, 1, 2),
39 PLL_RATE(168000000, 56, 1, 1),
40 PLL_RATE(192000000, 64, 1, 1),
41 PLL_RATE(216000000, 72, 1, 1),
42 PLL_RATE(240000000, 80, 1, 1),
43 PLL_RATE(264000000, 88, 1, 1),
44 PLL_RATE(288000000, 96, 1, 1),
45 PLL_RATE(312000000, 52, 1, 2),
46 PLL_RATE(336000000, 56, 1, 2),
47 PLL_RATE(360000000, 60, 1, 2),
48 PLL_RATE(384000000, 64, 1, 2),
49 PLL_RATE(408000000, 68, 1, 2),
50 PLL_RATE(432000000, 72, 1, 2),
51 PLL_RATE(456000000, 76, 1, 2),
52 PLL_RATE(480000000, 80, 1, 2),
53 PLL_RATE(504000000, 84, 1, 2),
54 PLL_RATE(528000000, 88, 1, 2),
55 PLL_RATE(552000000, 92, 1, 2),
56 PLL_RATE(576000000, 96, 1, 2),
57 PLL_RATE(600000000, 50, 1, 1),
58 PLL_RATE(624000000, 52, 1, 1),
59 PLL_RATE(648000000, 54, 1, 1),
60 PLL_RATE(672000000, 56, 1, 1),
61 PLL_RATE(696000000, 58, 1, 1),
62 PLL_RATE(720000000, 60, 1, 1),
63 PLL_RATE(744000000, 62, 1, 1),
64 PLL_RATE(768000000, 64, 1, 1),
65 PLL_RATE(792000000, 66, 1, 1),
66 PLL_RATE(816000000, 68, 1, 1),
67 PLL_RATE(840000000, 70, 1, 1),
68 PLL_RATE(864000000, 72, 1, 1),
69 PLL_RATE(888000000, 74, 1, 1),
70 PLL_RATE(912000000, 76, 1, 1),
71 PLL_RATE(936000000, 78, 1, 1),
72 PLL_RATE(960000000, 80, 1, 1),
73 PLL_RATE(984000000, 82, 1, 1),
74 PLL_RATE(1008000000, 84, 1, 1),
75 PLL_RATE(1032000000, 86, 1, 1),
76 PLL_RATE(1056000000, 88, 1, 1),
77 PLL_RATE(1080000000, 90, 1, 1),
78 PLL_RATE(1104000000, 92, 1, 1),
79 PLL_RATE(1128000000, 94, 1, 1),
80 PLL_RATE(1152000000, 96, 1, 1),
81 PLL_RATE(1176000000, 98, 1, 1),
82 PLL_RATE(1200000000, 50, 1, 0),
83 PLL_RATE(1224000000, 51, 1, 0),
84 PLL_RATE(1248000000, 52, 1, 0),
85 PLL_RATE(1272000000, 53, 1, 0),
86 PLL_RATE(1296000000, 54, 1, 0),
87 PLL_RATE(1320000000, 55, 1, 0),
88 PLL_RATE(1344000000, 56, 1, 0),
89 PLL_RATE(1368000000, 57, 1, 0),
90 PLL_RATE(1392000000, 58, 1, 0),
91 PLL_RATE(1416000000, 59, 1, 0),
92 PLL_RATE(1440000000, 60, 1, 0),
93 PLL_RATE(1464000000, 61, 1, 0),
94 PLL_RATE(1488000000, 62, 1, 0),
95 PLL_RATE(1512000000, 63, 1, 0),
96 PLL_RATE(1536000000, 64, 1, 0),
97 PLL_RATE(1560000000, 65, 1, 0),
98 PLL_RATE(1584000000, 66, 1, 0),
99 PLL_RATE(1608000000, 67, 1, 0),
100 PLL_RATE(1632000000, 68, 1, 0),
101 PLL_RATE(1656000000, 68, 1, 0),
102 PLL_RATE(1680000000, 68, 1, 0),
103 PLL_RATE(1704000000, 68, 1, 0),
104 PLL_RATE(1728000000, 69, 1, 0),
105 PLL_RATE(1752000000, 69, 1, 0),
106 PLL_RATE(1776000000, 69, 1, 0),
107 PLL_RATE(1800000000, 69, 1, 0),
108 PLL_RATE(1824000000, 70, 1, 0),
109 PLL_RATE(1848000000, 70, 1, 0),
110 PLL_RATE(1872000000, 70, 1, 0),
111 PLL_RATE(1896000000, 70, 1, 0),
112 PLL_RATE(1920000000, 71, 1, 0),
113 PLL_RATE(1944000000, 71, 1, 0),
114 PLL_RATE(1968000000, 71, 1, 0),
115 PLL_RATE(1992000000, 71, 1, 0),
116 PLL_RATE(2016000000, 72, 1, 0),
117 PLL_RATE(2040000000, 72, 1, 0),
118 PLL_RATE(2064000000, 72, 1, 0),
119 PLL_RATE(2088000000, 72, 1, 0),
120 PLL_RATE(2112000000, 73, 1, 0),
121 { /* sentinel */ },
122};
123
124static const struct pll_rate_table gxbb_gp0_pll_rate_table[] = { 35static const struct pll_rate_table gxbb_gp0_pll_rate_table[] = {
125 PLL_RATE(96000000, 32, 1, 3), 36 PLL_RATE(96000000, 32, 1, 3),
126 PLL_RATE(99000000, 33, 1, 3), 37 PLL_RATE(99000000, 33, 1, 3),
@@ -278,23 +189,39 @@ static const struct pll_rate_table gxl_gp0_pll_rate_table[] = {
278 { /* sentinel */ }, 189 { /* sentinel */ },
279}; 190};
280 191
281static struct meson_clk_pll gxbb_fixed_pll = { 192static struct clk_regmap gxbb_fixed_pll = {
282 .m = { 193 .data = &(struct meson_clk_pll_data){
283 .reg_off = HHI_MPLL_CNTL, 194 .m = {
284 .shift = 0, 195 .reg_off = HHI_MPLL_CNTL,
285 .width = 9, 196 .shift = 0,
197 .width = 9,
198 },
199 .n = {
200 .reg_off = HHI_MPLL_CNTL,
201 .shift = 9,
202 .width = 5,
203 },
204 .od = {
205 .reg_off = HHI_MPLL_CNTL,
206 .shift = 16,
207 .width = 2,
208 },
209 .frac = {
210 .reg_off = HHI_MPLL_CNTL2,
211 .shift = 0,
212 .width = 12,
213 },
214 .l = {
215 .reg_off = HHI_MPLL_CNTL,
216 .shift = 31,
217 .width = 1,
218 },
219 .rst = {
220 .reg_off = HHI_MPLL_CNTL,
221 .shift = 29,
222 .width = 1,
223 },
286 }, 224 },
287 .n = {
288 .reg_off = HHI_MPLL_CNTL,
289 .shift = 9,
290 .width = 5,
291 },
292 .od = {
293 .reg_off = HHI_MPLL_CNTL,
294 .shift = 16,
295 .width = 2,
296 },
297 .lock = &meson_clk_lock,
298 .hw.init = &(struct clk_init_data){ 225 .hw.init = &(struct clk_init_data){
299 .name = "fixed_pll", 226 .name = "fixed_pll",
300 .ops = &meson_clk_pll_ro_ops, 227 .ops = &meson_clk_pll_ro_ops,
@@ -304,33 +231,118 @@ static struct meson_clk_pll gxbb_fixed_pll = {
304 }, 231 },
305}; 232};
306 233
307static struct meson_clk_pll gxbb_hdmi_pll = { 234static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
308 .m = { 235 .mult = 2,
309 .reg_off = HHI_HDMI_PLL_CNTL, 236 .div = 1,
310 .shift = 0, 237 .hw.init = &(struct clk_init_data){
311 .width = 9, 238 .name = "hdmi_pll_pre_mult",
312 }, 239 .ops = &clk_fixed_factor_ops,
313 .n = { 240 .parent_names = (const char *[]){ "xtal" },
314 .reg_off = HHI_HDMI_PLL_CNTL, 241 .num_parents = 1,
315 .shift = 9,
316 .width = 5,
317 }, 242 },
318 .frac = { 243};
319 .reg_off = HHI_HDMI_PLL_CNTL2, 244
320 .shift = 0, 245static struct clk_regmap gxbb_hdmi_pll = {
321 .width = 12, 246 .data = &(struct meson_clk_pll_data){
247 .m = {
248 .reg_off = HHI_HDMI_PLL_CNTL,
249 .shift = 0,
250 .width = 9,
251 },
252 .n = {
253 .reg_off = HHI_HDMI_PLL_CNTL,
254 .shift = 9,
255 .width = 5,
256 },
257 .frac = {
258 .reg_off = HHI_HDMI_PLL_CNTL2,
259 .shift = 0,
260 .width = 12,
261 },
262 .od = {
263 .reg_off = HHI_HDMI_PLL_CNTL2,
264 .shift = 16,
265 .width = 2,
266 },
267 .od2 = {
268 .reg_off = HHI_HDMI_PLL_CNTL2,
269 .shift = 22,
270 .width = 2,
271 },
272 .od3 = {
273 .reg_off = HHI_HDMI_PLL_CNTL2,
274 .shift = 18,
275 .width = 2,
276 },
277 .l = {
278 .reg_off = HHI_HDMI_PLL_CNTL,
279 .shift = 31,
280 .width = 1,
281 },
282 .rst = {
283 .reg_off = HHI_HDMI_PLL_CNTL,
284 .shift = 28,
285 .width = 1,
286 },
322 }, 287 },
323 .od = { 288 .hw.init = &(struct clk_init_data){
324 .reg_off = HHI_HDMI_PLL_CNTL2, 289 .name = "hdmi_pll",
325 .shift = 16, 290 .ops = &meson_clk_pll_ro_ops,
326 .width = 2, 291 .parent_names = (const char *[]){ "hdmi_pll_pre_mult" },
292 .num_parents = 1,
293 .flags = CLK_GET_RATE_NOCACHE,
327 }, 294 },
328 .od2 = { 295};
329 .reg_off = HHI_HDMI_PLL_CNTL2, 296
330 .shift = 22, 297static struct clk_regmap gxl_hdmi_pll = {
331 .width = 2, 298 .data = &(struct meson_clk_pll_data){
299 .m = {
300 .reg_off = HHI_HDMI_PLL_CNTL,
301 .shift = 0,
302 .width = 9,
303 },
304 .n = {
305 .reg_off = HHI_HDMI_PLL_CNTL,
306 .shift = 9,
307 .width = 5,
308 },
309 .frac = {
310 /*
311 * On gxl, there is a register shift due to
312 * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
313 * so we compute the register offset based on the PLL
314 * base to get it right
315 */
316 .reg_off = HHI_HDMI_PLL_CNTL + 4,
317 .shift = 0,
318 .width = 12,
319 },
320 .od = {
321 .reg_off = HHI_HDMI_PLL_CNTL + 8,
322 .shift = 21,
323 .width = 2,
324 },
325 .od2 = {
326 .reg_off = HHI_HDMI_PLL_CNTL + 8,
327 .shift = 23,
328 .width = 2,
329 },
330 .od3 = {
331 .reg_off = HHI_HDMI_PLL_CNTL + 8,
332 .shift = 19,
333 .width = 2,
334 },
335 .l = {
336 .reg_off = HHI_HDMI_PLL_CNTL,
337 .shift = 31,
338 .width = 1,
339 },
340 .rst = {
341 .reg_off = HHI_HDMI_PLL_CNTL,
342 .shift = 29,
343 .width = 1,
344 },
332 }, 345 },
333 .lock = &meson_clk_lock,
334 .hw.init = &(struct clk_init_data){ 346 .hw.init = &(struct clk_init_data){
335 .name = "hdmi_pll", 347 .name = "hdmi_pll",
336 .ops = &meson_clk_pll_ro_ops, 348 .ops = &meson_clk_pll_ro_ops,
@@ -340,25 +352,34 @@ static struct meson_clk_pll gxbb_hdmi_pll = {
340 }, 352 },
341}; 353};
342 354
343static struct meson_clk_pll gxbb_sys_pll = { 355static struct clk_regmap gxbb_sys_pll = {
344 .m = { 356 .data = &(struct meson_clk_pll_data){
345 .reg_off = HHI_SYS_PLL_CNTL, 357 .m = {
346 .shift = 0, 358 .reg_off = HHI_SYS_PLL_CNTL,
347 .width = 9, 359 .shift = 0,
348 }, 360 .width = 9,
349 .n = { 361 },
350 .reg_off = HHI_SYS_PLL_CNTL, 362 .n = {
351 .shift = 9, 363 .reg_off = HHI_SYS_PLL_CNTL,
352 .width = 5, 364 .shift = 9,
365 .width = 5,
366 },
367 .od = {
368 .reg_off = HHI_SYS_PLL_CNTL,
369 .shift = 10,
370 .width = 2,
371 },
372 .l = {
373 .reg_off = HHI_SYS_PLL_CNTL,
374 .shift = 31,
375 .width = 1,
376 },
377 .rst = {
378 .reg_off = HHI_SYS_PLL_CNTL,
379 .shift = 29,
380 .width = 1,
381 },
353 }, 382 },
354 .od = {
355 .reg_off = HHI_SYS_PLL_CNTL,
356 .shift = 10,
357 .width = 2,
358 },
359 .rate_table = sys_pll_rate_table,
360 .rate_count = ARRAY_SIZE(sys_pll_rate_table),
361 .lock = &meson_clk_lock,
362 .hw.init = &(struct clk_init_data){ 383 .hw.init = &(struct clk_init_data){
363 .name = "sys_pll", 384 .name = "sys_pll",
364 .ops = &meson_clk_pll_ro_ops, 385 .ops = &meson_clk_pll_ro_ops,
@@ -368,38 +389,44 @@ static struct meson_clk_pll gxbb_sys_pll = {
368 }, 389 },
369}; 390};
370 391
371struct pll_params_table gxbb_gp0_params_table[] = { 392static const struct reg_sequence gxbb_gp0_init_regs[] = {
372 PLL_PARAM(HHI_GP0_PLL_CNTL, 0x6a000228), 393 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 },
373 PLL_PARAM(HHI_GP0_PLL_CNTL2, 0x69c80000), 394 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 },
374 PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a5590c4), 395 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d },
375 PLL_PARAM(HHI_GP0_PLL_CNTL4, 0x0000500d), 396 { .reg = HHI_GP0_PLL_CNTL, .def = 0x4a000228 },
376}; 397};
377 398
378static struct meson_clk_pll gxbb_gp0_pll = { 399static struct clk_regmap gxbb_gp0_pll = {
379 .m = { 400 .data = &(struct meson_clk_pll_data){
380 .reg_off = HHI_GP0_PLL_CNTL, 401 .m = {
381 .shift = 0, 402 .reg_off = HHI_GP0_PLL_CNTL,
382 .width = 9, 403 .shift = 0,
383 }, 404 .width = 9,
384 .n = { 405 },
385 .reg_off = HHI_GP0_PLL_CNTL, 406 .n = {
386 .shift = 9, 407 .reg_off = HHI_GP0_PLL_CNTL,
387 .width = 5, 408 .shift = 9,
388 }, 409 .width = 5,
389 .od = { 410 },
390 .reg_off = HHI_GP0_PLL_CNTL, 411 .od = {
391 .shift = 16, 412 .reg_off = HHI_GP0_PLL_CNTL,
392 .width = 2, 413 .shift = 16,
393 }, 414 .width = 2,
394 .params = { 415 },
395 .params_table = gxbb_gp0_params_table, 416 .l = {
396 .params_count = ARRAY_SIZE(gxbb_gp0_params_table), 417 .reg_off = HHI_GP0_PLL_CNTL,
397 .no_init_reset = true, 418 .shift = 31,
398 .clear_reset_for_lock = true, 419 .width = 1,
420 },
421 .rst = {
422 .reg_off = HHI_GP0_PLL_CNTL,
423 .shift = 29,
424 .width = 1,
425 },
426 .table = gxbb_gp0_pll_rate_table,
427 .init_regs = gxbb_gp0_init_regs,
428 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
399 }, 429 },
400 .rate_table = gxbb_gp0_pll_rate_table,
401 .rate_count = ARRAY_SIZE(gxbb_gp0_pll_rate_table),
402 .lock = &meson_clk_lock,
403 .hw.init = &(struct clk_init_data){ 430 .hw.init = &(struct clk_init_data){
404 .name = "gp0_pll", 431 .name = "gp0_pll",
405 .ops = &meson_clk_pll_ops, 432 .ops = &meson_clk_pll_ops,
@@ -409,40 +436,51 @@ static struct meson_clk_pll gxbb_gp0_pll = {
409 }, 436 },
410}; 437};
411 438
412struct pll_params_table gxl_gp0_params_table[] = { 439static const struct reg_sequence gxl_gp0_init_regs[] = {
413 PLL_PARAM(HHI_GP0_PLL_CNTL, 0x40010250), 440 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
414 PLL_PARAM(HHI_GP0_PLL_CNTL1, 0xc084a000), 441 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
415 PLL_PARAM(HHI_GP0_PLL_CNTL2, 0xb75020be), 442 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
416 PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a59a288), 443 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
417 PLL_PARAM(HHI_GP0_PLL_CNTL4, 0xc000004d), 444 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
418 PLL_PARAM(HHI_GP0_PLL_CNTL5, 0x00078000), 445 { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 },
419}; 446};
420 447
421static struct meson_clk_pll gxl_gp0_pll = { 448static struct clk_regmap gxl_gp0_pll = {
422 .m = { 449 .data = &(struct meson_clk_pll_data){
423 .reg_off = HHI_GP0_PLL_CNTL, 450 .m = {
424 .shift = 0, 451 .reg_off = HHI_GP0_PLL_CNTL,
425 .width = 9, 452 .shift = 0,
426 }, 453 .width = 9,
427 .n = { 454 },
428 .reg_off = HHI_GP0_PLL_CNTL, 455 .n = {
429 .shift = 9, 456 .reg_off = HHI_GP0_PLL_CNTL,
430 .width = 5, 457 .shift = 9,
431 }, 458 .width = 5,
432 .od = { 459 },
433 .reg_off = HHI_GP0_PLL_CNTL, 460 .od = {
434 .shift = 16, 461 .reg_off = HHI_GP0_PLL_CNTL,
435 .width = 2, 462 .shift = 16,
463 .width = 2,
464 },
465 .frac = {
466 .reg_off = HHI_GP0_PLL_CNTL1,
467 .shift = 0,
468 .width = 10,
469 },
470 .l = {
471 .reg_off = HHI_GP0_PLL_CNTL,
472 .shift = 31,
473 .width = 1,
474 },
475 .rst = {
476 .reg_off = HHI_GP0_PLL_CNTL,
477 .shift = 29,
478 .width = 1,
479 },
480 .table = gxl_gp0_pll_rate_table,
481 .init_regs = gxl_gp0_init_regs,
482 .init_count = ARRAY_SIZE(gxl_gp0_init_regs),
436 }, 483 },
437 .params = {
438 .params_table = gxl_gp0_params_table,
439 .params_count = ARRAY_SIZE(gxl_gp0_params_table),
440 .no_init_reset = true,
441 .reset_lock_loop = true,
442 },
443 .rate_table = gxl_gp0_pll_rate_table,
444 .rate_count = ARRAY_SIZE(gxl_gp0_pll_rate_table),
445 .lock = &meson_clk_lock,
446 .hw.init = &(struct clk_init_data){ 484 .hw.init = &(struct clk_init_data){
447 .name = "gp0_pll", 485 .name = "gp0_pll",
448 .ops = &meson_clk_pll_ops, 486 .ops = &meson_clk_pll_ops,
@@ -452,161 +490,267 @@ static struct meson_clk_pll gxl_gp0_pll = {
452 }, 490 },
453}; 491};
454 492
455static struct clk_fixed_factor gxbb_fclk_div2 = { 493static struct clk_fixed_factor gxbb_fclk_div2_div = {
456 .mult = 1, 494 .mult = 1,
457 .div = 2, 495 .div = 2,
458 .hw.init = &(struct clk_init_data){ 496 .hw.init = &(struct clk_init_data){
459 .name = "fclk_div2", 497 .name = "fclk_div2_div",
460 .ops = &clk_fixed_factor_ops, 498 .ops = &clk_fixed_factor_ops,
461 .parent_names = (const char *[]){ "fixed_pll" }, 499 .parent_names = (const char *[]){ "fixed_pll" },
462 .num_parents = 1, 500 .num_parents = 1,
463 }, 501 },
464}; 502};
465 503
466static struct clk_fixed_factor gxbb_fclk_div3 = { 504static struct clk_regmap gxbb_fclk_div2 = {
505 .data = &(struct clk_regmap_gate_data){
506 .offset = HHI_MPLL_CNTL6,
507 .bit_idx = 27,
508 },
509 .hw.init = &(struct clk_init_data){
510 .name = "fclk_div2",
511 .ops = &clk_regmap_gate_ops,
512 .parent_names = (const char *[]){ "fclk_div2_div" },
513 .num_parents = 1,
514 },
515};
516
517static struct clk_fixed_factor gxbb_fclk_div3_div = {
467 .mult = 1, 518 .mult = 1,
468 .div = 3, 519 .div = 3,
469 .hw.init = &(struct clk_init_data){ 520 .hw.init = &(struct clk_init_data){
470 .name = "fclk_div3", 521 .name = "fclk_div3_div",
471 .ops = &clk_fixed_factor_ops, 522 .ops = &clk_fixed_factor_ops,
472 .parent_names = (const char *[]){ "fixed_pll" }, 523 .parent_names = (const char *[]){ "fixed_pll" },
473 .num_parents = 1, 524 .num_parents = 1,
474 }, 525 },
475}; 526};
476 527
477static struct clk_fixed_factor gxbb_fclk_div4 = { 528static struct clk_regmap gxbb_fclk_div3 = {
529 .data = &(struct clk_regmap_gate_data){
530 .offset = HHI_MPLL_CNTL6,
531 .bit_idx = 28,
532 },
533 .hw.init = &(struct clk_init_data){
534 .name = "fclk_div3",
535 .ops = &clk_regmap_gate_ops,
536 .parent_names = (const char *[]){ "fclk_div3_div" },
537 .num_parents = 1,
538 },
539};
540
541static struct clk_fixed_factor gxbb_fclk_div4_div = {
478 .mult = 1, 542 .mult = 1,
479 .div = 4, 543 .div = 4,
480 .hw.init = &(struct clk_init_data){ 544 .hw.init = &(struct clk_init_data){
481 .name = "fclk_div4", 545 .name = "fclk_div4_div",
482 .ops = &clk_fixed_factor_ops, 546 .ops = &clk_fixed_factor_ops,
483 .parent_names = (const char *[]){ "fixed_pll" }, 547 .parent_names = (const char *[]){ "fixed_pll" },
484 .num_parents = 1, 548 .num_parents = 1,
485 }, 549 },
486}; 550};
487 551
488static struct clk_fixed_factor gxbb_fclk_div5 = { 552static struct clk_regmap gxbb_fclk_div4 = {
553 .data = &(struct clk_regmap_gate_data){
554 .offset = HHI_MPLL_CNTL6,
555 .bit_idx = 29,
556 },
557 .hw.init = &(struct clk_init_data){
558 .name = "fclk_div4",
559 .ops = &clk_regmap_gate_ops,
560 .parent_names = (const char *[]){ "fclk_div4_div" },
561 .num_parents = 1,
562 },
563};
564
565static struct clk_fixed_factor gxbb_fclk_div5_div = {
489 .mult = 1, 566 .mult = 1,
490 .div = 5, 567 .div = 5,
491 .hw.init = &(struct clk_init_data){ 568 .hw.init = &(struct clk_init_data){
492 .name = "fclk_div5", 569 .name = "fclk_div5_div",
493 .ops = &clk_fixed_factor_ops, 570 .ops = &clk_fixed_factor_ops,
494 .parent_names = (const char *[]){ "fixed_pll" }, 571 .parent_names = (const char *[]){ "fixed_pll" },
495 .num_parents = 1, 572 .num_parents = 1,
496 }, 573 },
497}; 574};
498 575
499static struct clk_fixed_factor gxbb_fclk_div7 = { 576static struct clk_regmap gxbb_fclk_div5 = {
577 .data = &(struct clk_regmap_gate_data){
578 .offset = HHI_MPLL_CNTL6,
579 .bit_idx = 30,
580 },
581 .hw.init = &(struct clk_init_data){
582 .name = "fclk_div5",
583 .ops = &clk_regmap_gate_ops,
584 .parent_names = (const char *[]){ "fclk_div5_div" },
585 .num_parents = 1,
586 },
587};
588
589static struct clk_fixed_factor gxbb_fclk_div7_div = {
500 .mult = 1, 590 .mult = 1,
501 .div = 7, 591 .div = 7,
502 .hw.init = &(struct clk_init_data){ 592 .hw.init = &(struct clk_init_data){
503 .name = "fclk_div7", 593 .name = "fclk_div7_div",
504 .ops = &clk_fixed_factor_ops, 594 .ops = &clk_fixed_factor_ops,
505 .parent_names = (const char *[]){ "fixed_pll" }, 595 .parent_names = (const char *[]){ "fixed_pll" },
506 .num_parents = 1, 596 .num_parents = 1,
507 }, 597 },
508}; 598};
509 599
510static struct meson_clk_mpll gxbb_mpll0 = { 600static struct clk_regmap gxbb_fclk_div7 = {
511 .sdm = { 601 .data = &(struct clk_regmap_gate_data){
512 .reg_off = HHI_MPLL_CNTL7, 602 .offset = HHI_MPLL_CNTL6,
513 .shift = 0, 603 .bit_idx = 31,
514 .width = 14,
515 }, 604 },
516 .sdm_en = { 605 .hw.init = &(struct clk_init_data){
517 .reg_off = HHI_MPLL_CNTL7, 606 .name = "fclk_div7",
518 .shift = 15, 607 .ops = &clk_regmap_gate_ops,
519 .width = 1, 608 .parent_names = (const char *[]){ "fclk_div7_div" },
609 .num_parents = 1,
520 }, 610 },
521 .n2 = { 611};
522 .reg_off = HHI_MPLL_CNTL7, 612
523 .shift = 16, 613static struct clk_regmap gxbb_mpll_prediv = {
524 .width = 9, 614 .data = &(struct clk_regmap_div_data){
615 .offset = HHI_MPLL_CNTL5,
616 .shift = 12,
617 .width = 1,
525 }, 618 },
526 .en = { 619 .hw.init = &(struct clk_init_data){
527 .reg_off = HHI_MPLL_CNTL7, 620 .name = "mpll_prediv",
528 .shift = 14, 621 .ops = &clk_regmap_divider_ro_ops,
529 .width = 1, 622 .parent_names = (const char *[]){ "fixed_pll" },
623 .num_parents = 1,
530 }, 624 },
531 .ssen = { 625};
532 .reg_off = HHI_MPLL_CNTL, 626
533 .shift = 25, 627static struct clk_regmap gxbb_mpll0_div = {
534 .width = 1, 628 .data = &(struct meson_clk_mpll_data){
629 .sdm = {
630 .reg_off = HHI_MPLL_CNTL7,
631 .shift = 0,
632 .width = 14,
633 },
634 .sdm_en = {
635 .reg_off = HHI_MPLL_CNTL7,
636 .shift = 15,
637 .width = 1,
638 },
639 .n2 = {
640 .reg_off = HHI_MPLL_CNTL7,
641 .shift = 16,
642 .width = 9,
643 },
644 .ssen = {
645 .reg_off = HHI_MPLL_CNTL,
646 .shift = 25,
647 .width = 1,
648 },
649 .lock = &meson_clk_lock,
535 }, 650 },
536 .lock = &meson_clk_lock,
537 .hw.init = &(struct clk_init_data){ 651 .hw.init = &(struct clk_init_data){
538 .name = "mpll0", 652 .name = "mpll0_div",
539 .ops = &meson_clk_mpll_ops, 653 .ops = &meson_clk_mpll_ops,
540 .parent_names = (const char *[]){ "fixed_pll" }, 654 .parent_names = (const char *[]){ "mpll_prediv" },
541 .num_parents = 1, 655 .num_parents = 1,
542 }, 656 },
543}; 657};
544 658
545static struct meson_clk_mpll gxbb_mpll1 = { 659static struct clk_regmap gxbb_mpll0 = {
546 .sdm = { 660 .data = &(struct clk_regmap_gate_data){
547 .reg_off = HHI_MPLL_CNTL8, 661 .offset = HHI_MPLL_CNTL7,
548 .shift = 0, 662 .bit_idx = 14,
549 .width = 14,
550 },
551 .sdm_en = {
552 .reg_off = HHI_MPLL_CNTL8,
553 .shift = 15,
554 .width = 1,
555 }, 663 },
556 .n2 = { 664 .hw.init = &(struct clk_init_data){
557 .reg_off = HHI_MPLL_CNTL8, 665 .name = "mpll0",
558 .shift = 16, 666 .ops = &clk_regmap_gate_ops,
559 .width = 9, 667 .parent_names = (const char *[]){ "mpll0_div" },
668 .num_parents = 1,
669 .flags = CLK_SET_RATE_PARENT,
560 }, 670 },
561 .en = { 671};
562 .reg_off = HHI_MPLL_CNTL8, 672
563 .shift = 14, 673static struct clk_regmap gxbb_mpll1_div = {
564 .width = 1, 674 .data = &(struct meson_clk_mpll_data){
675 .sdm = {
676 .reg_off = HHI_MPLL_CNTL8,
677 .shift = 0,
678 .width = 14,
679 },
680 .sdm_en = {
681 .reg_off = HHI_MPLL_CNTL8,
682 .shift = 15,
683 .width = 1,
684 },
685 .n2 = {
686 .reg_off = HHI_MPLL_CNTL8,
687 .shift = 16,
688 .width = 9,
689 },
690 .lock = &meson_clk_lock,
565 }, 691 },
566 .lock = &meson_clk_lock,
567 .hw.init = &(struct clk_init_data){ 692 .hw.init = &(struct clk_init_data){
568 .name = "mpll1", 693 .name = "mpll1_div",
569 .ops = &meson_clk_mpll_ops, 694 .ops = &meson_clk_mpll_ops,
570 .parent_names = (const char *[]){ "fixed_pll" }, 695 .parent_names = (const char *[]){ "mpll_prediv" },
571 .num_parents = 1, 696 .num_parents = 1,
572 }, 697 },
573}; 698};
574 699
575static struct meson_clk_mpll gxbb_mpll2 = { 700static struct clk_regmap gxbb_mpll1 = {
576 .sdm = { 701 .data = &(struct clk_regmap_gate_data){
577 .reg_off = HHI_MPLL_CNTL9, 702 .offset = HHI_MPLL_CNTL8,
578 .shift = 0, 703 .bit_idx = 14,
579 .width = 14,
580 },
581 .sdm_en = {
582 .reg_off = HHI_MPLL_CNTL9,
583 .shift = 15,
584 .width = 1,
585 }, 704 },
586 .n2 = { 705 .hw.init = &(struct clk_init_data){
587 .reg_off = HHI_MPLL_CNTL9, 706 .name = "mpll1",
588 .shift = 16, 707 .ops = &clk_regmap_gate_ops,
589 .width = 9, 708 .parent_names = (const char *[]){ "mpll1_div" },
709 .num_parents = 1,
710 .flags = CLK_SET_RATE_PARENT,
590 }, 711 },
591 .en = { 712};
592 .reg_off = HHI_MPLL_CNTL9, 713
593 .shift = 14, 714static struct clk_regmap gxbb_mpll2_div = {
594 .width = 1, 715 .data = &(struct meson_clk_mpll_data){
716 .sdm = {
717 .reg_off = HHI_MPLL_CNTL9,
718 .shift = 0,
719 .width = 14,
720 },
721 .sdm_en = {
722 .reg_off = HHI_MPLL_CNTL9,
723 .shift = 15,
724 .width = 1,
725 },
726 .n2 = {
727 .reg_off = HHI_MPLL_CNTL9,
728 .shift = 16,
729 .width = 9,
730 },
731 .lock = &meson_clk_lock,
595 }, 732 },
596 .lock = &meson_clk_lock,
597 .hw.init = &(struct clk_init_data){ 733 .hw.init = &(struct clk_init_data){
598 .name = "mpll2", 734 .name = "mpll2_div",
599 .ops = &meson_clk_mpll_ops, 735 .ops = &meson_clk_mpll_ops,
600 .parent_names = (const char *[]){ "fixed_pll" }, 736 .parent_names = (const char *[]){ "mpll_prediv" },
601 .num_parents = 1, 737 .num_parents = 1,
602 }, 738 },
603}; 739};
604 740
605/* 741static struct clk_regmap gxbb_mpll2 = {
606 * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers 742 .data = &(struct clk_regmap_gate_data){
607 * and should be modeled with their respective PLLs via the forthcoming 743 .offset = HHI_MPLL_CNTL9,
608 * coordinated clock rates feature 744 .bit_idx = 14,
609 */ 745 },
746 .hw.init = &(struct clk_init_data){
747 .name = "mpll2",
748 .ops = &clk_regmap_gate_ops,
749 .parent_names = (const char *[]){ "mpll2_div" },
750 .num_parents = 1,
751 .flags = CLK_SET_RATE_PARENT,
752 },
753};
610 754
611static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 755static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
612static const char * const clk81_parent_names[] = { 756static const char * const clk81_parent_names[] = {
@@ -614,16 +758,16 @@ static const char * const clk81_parent_names[] = {
614 "fclk_div3", "fclk_div5" 758 "fclk_div3", "fclk_div5"
615}; 759};
616 760
617static struct clk_mux gxbb_mpeg_clk_sel = { 761static struct clk_regmap gxbb_mpeg_clk_sel = {
618 .reg = (void *)HHI_MPEG_CLK_CNTL, 762 .data = &(struct clk_regmap_mux_data){
619 .mask = 0x7, 763 .offset = HHI_MPEG_CLK_CNTL,
620 .shift = 12, 764 .mask = 0x7,
621 .flags = CLK_MUX_READ_ONLY, 765 .shift = 12,
622 .table = mux_table_clk81, 766 .table = mux_table_clk81,
623 .lock = &meson_clk_lock, 767 },
624 .hw.init = &(struct clk_init_data){ 768 .hw.init = &(struct clk_init_data){
625 .name = "mpeg_clk_sel", 769 .name = "mpeg_clk_sel",
626 .ops = &clk_mux_ro_ops, 770 .ops = &clk_regmap_mux_ro_ops,
627 /* 771 /*
628 * bits 14:12 selects from 8 possible parents: 772 * bits 14:12 selects from 8 possible parents:
629 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 773 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
@@ -631,72 +775,75 @@ static struct clk_mux gxbb_mpeg_clk_sel = {
631 */ 775 */
632 .parent_names = clk81_parent_names, 776 .parent_names = clk81_parent_names,
633 .num_parents = ARRAY_SIZE(clk81_parent_names), 777 .num_parents = ARRAY_SIZE(clk81_parent_names),
634 .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
635 }, 778 },
636}; 779};
637 780
638static struct clk_divider gxbb_mpeg_clk_div = { 781static struct clk_regmap gxbb_mpeg_clk_div = {
639 .reg = (void *)HHI_MPEG_CLK_CNTL, 782 .data = &(struct clk_regmap_div_data){
640 .shift = 0, 783 .offset = HHI_MPEG_CLK_CNTL,
641 .width = 7, 784 .shift = 0,
642 .lock = &meson_clk_lock, 785 .width = 7,
786 },
643 .hw.init = &(struct clk_init_data){ 787 .hw.init = &(struct clk_init_data){
644 .name = "mpeg_clk_div", 788 .name = "mpeg_clk_div",
645 .ops = &clk_divider_ops, 789 .ops = &clk_regmap_divider_ro_ops,
646 .parent_names = (const char *[]){ "mpeg_clk_sel" }, 790 .parent_names = (const char *[]){ "mpeg_clk_sel" },
647 .num_parents = 1, 791 .num_parents = 1,
648 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
649 }, 792 },
650}; 793};
651 794
652/* the mother of dragons^W gates */ 795/* the mother of dragons gates */
653static struct clk_gate gxbb_clk81 = { 796static struct clk_regmap gxbb_clk81 = {
654 .reg = (void *)HHI_MPEG_CLK_CNTL, 797 .data = &(struct clk_regmap_gate_data){
655 .bit_idx = 7, 798 .offset = HHI_MPEG_CLK_CNTL,
656 .lock = &meson_clk_lock, 799 .bit_idx = 7,
800 },
657 .hw.init = &(struct clk_init_data){ 801 .hw.init = &(struct clk_init_data){
658 .name = "clk81", 802 .name = "clk81",
659 .ops = &clk_gate_ops, 803 .ops = &clk_regmap_gate_ops,
660 .parent_names = (const char *[]){ "mpeg_clk_div" }, 804 .parent_names = (const char *[]){ "mpeg_clk_div" },
661 .num_parents = 1, 805 .num_parents = 1,
662 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), 806 .flags = CLK_IS_CRITICAL,
663 }, 807 },
664}; 808};
665 809
666static struct clk_mux gxbb_sar_adc_clk_sel = { 810static struct clk_regmap gxbb_sar_adc_clk_sel = {
667 .reg = (void *)HHI_SAR_CLK_CNTL, 811 .data = &(struct clk_regmap_mux_data){
668 .mask = 0x3, 812 .offset = HHI_SAR_CLK_CNTL,
669 .shift = 9, 813 .mask = 0x3,
670 .lock = &meson_clk_lock, 814 .shift = 9,
815 },
671 .hw.init = &(struct clk_init_data){ 816 .hw.init = &(struct clk_init_data){
672 .name = "sar_adc_clk_sel", 817 .name = "sar_adc_clk_sel",
673 .ops = &clk_mux_ops, 818 .ops = &clk_regmap_mux_ops,
674 /* NOTE: The datasheet doesn't list the parents for bit 10 */ 819 /* NOTE: The datasheet doesn't list the parents for bit 10 */
675 .parent_names = (const char *[]){ "xtal", "clk81", }, 820 .parent_names = (const char *[]){ "xtal", "clk81", },
676 .num_parents = 2, 821 .num_parents = 2,
677 }, 822 },
678}; 823};
679 824
680static struct clk_divider gxbb_sar_adc_clk_div = { 825static struct clk_regmap gxbb_sar_adc_clk_div = {
681 .reg = (void *)HHI_SAR_CLK_CNTL, 826 .data = &(struct clk_regmap_div_data){
682 .shift = 0, 827 .offset = HHI_SAR_CLK_CNTL,
683 .width = 8, 828 .shift = 0,
684 .lock = &meson_clk_lock, 829 .width = 8,
830 },
685 .hw.init = &(struct clk_init_data){ 831 .hw.init = &(struct clk_init_data){
686 .name = "sar_adc_clk_div", 832 .name = "sar_adc_clk_div",
687 .ops = &clk_divider_ops, 833 .ops = &clk_regmap_divider_ops,
688 .parent_names = (const char *[]){ "sar_adc_clk_sel" }, 834 .parent_names = (const char *[]){ "sar_adc_clk_sel" },
689 .num_parents = 1, 835 .num_parents = 1,
690 }, 836 },
691}; 837};
692 838
693static struct clk_gate gxbb_sar_adc_clk = { 839static struct clk_regmap gxbb_sar_adc_clk = {
694 .reg = (void *)HHI_SAR_CLK_CNTL, 840 .data = &(struct clk_regmap_gate_data){
695 .bit_idx = 8, 841 .offset = HHI_SAR_CLK_CNTL,
696 .lock = &meson_clk_lock, 842 .bit_idx = 8,
843 },
697 .hw.init = &(struct clk_init_data){ 844 .hw.init = &(struct clk_init_data){
698 .name = "sar_adc_clk", 845 .name = "sar_adc_clk",
699 .ops = &clk_gate_ops, 846 .ops = &clk_regmap_gate_ops,
700 .parent_names = (const char *[]){ "sar_adc_clk_div" }, 847 .parent_names = (const char *[]){ "sar_adc_clk_div" },
701 .num_parents = 1, 848 .num_parents = 1,
702 .flags = CLK_SET_RATE_PARENT, 849 .flags = CLK_SET_RATE_PARENT,
@@ -708,21 +855,20 @@ static struct clk_gate gxbb_sar_adc_clk = {
708 * muxed by a glitch-free switch. 855 * muxed by a glitch-free switch.
709 */ 856 */
710 857
711static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7};
712static const char * const gxbb_mali_0_1_parent_names[] = { 858static const char * const gxbb_mali_0_1_parent_names[] = {
713 "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7", 859 "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
714 "fclk_div4", "fclk_div3", "fclk_div5" 860 "fclk_div4", "fclk_div3", "fclk_div5"
715}; 861};
716 862
717static struct clk_mux gxbb_mali_0_sel = { 863static struct clk_regmap gxbb_mali_0_sel = {
718 .reg = (void *)HHI_MALI_CLK_CNTL, 864 .data = &(struct clk_regmap_mux_data){
719 .mask = 0x7, 865 .offset = HHI_MALI_CLK_CNTL,
720 .shift = 9, 866 .mask = 0x7,
721 .table = mux_table_mali_0_1, 867 .shift = 9,
722 .lock = &meson_clk_lock, 868 },
723 .hw.init = &(struct clk_init_data){ 869 .hw.init = &(struct clk_init_data){
724 .name = "mali_0_sel", 870 .name = "mali_0_sel",
725 .ops = &clk_mux_ops, 871 .ops = &clk_regmap_mux_ops,
726 /* 872 /*
727 * bits 10:9 selects from 8 possible parents: 873 * bits 10:9 selects from 8 possible parents:
728 * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 874 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
@@ -734,42 +880,44 @@ static struct clk_mux gxbb_mali_0_sel = {
734 }, 880 },
735}; 881};
736 882
737static struct clk_divider gxbb_mali_0_div = { 883static struct clk_regmap gxbb_mali_0_div = {
738 .reg = (void *)HHI_MALI_CLK_CNTL, 884 .data = &(struct clk_regmap_div_data){
739 .shift = 0, 885 .offset = HHI_MALI_CLK_CNTL,
740 .width = 7, 886 .shift = 0,
741 .lock = &meson_clk_lock, 887 .width = 7,
888 },
742 .hw.init = &(struct clk_init_data){ 889 .hw.init = &(struct clk_init_data){
743 .name = "mali_0_div", 890 .name = "mali_0_div",
744 .ops = &clk_divider_ops, 891 .ops = &clk_regmap_divider_ops,
745 .parent_names = (const char *[]){ "mali_0_sel" }, 892 .parent_names = (const char *[]){ "mali_0_sel" },
746 .num_parents = 1, 893 .num_parents = 1,
747 .flags = CLK_SET_RATE_NO_REPARENT, 894 .flags = CLK_SET_RATE_NO_REPARENT,
748 }, 895 },
749}; 896};
750 897
751static struct clk_gate gxbb_mali_0 = { 898static struct clk_regmap gxbb_mali_0 = {
752 .reg = (void *)HHI_MALI_CLK_CNTL, 899 .data = &(struct clk_regmap_gate_data){
753 .bit_idx = 8, 900 .offset = HHI_MALI_CLK_CNTL,
754 .lock = &meson_clk_lock, 901 .bit_idx = 8,
902 },
755 .hw.init = &(struct clk_init_data){ 903 .hw.init = &(struct clk_init_data){
756 .name = "mali_0", 904 .name = "mali_0",
757 .ops = &clk_gate_ops, 905 .ops = &clk_regmap_gate_ops,
758 .parent_names = (const char *[]){ "mali_0_div" }, 906 .parent_names = (const char *[]){ "mali_0_div" },
759 .num_parents = 1, 907 .num_parents = 1,
760 .flags = CLK_SET_RATE_PARENT, 908 .flags = CLK_SET_RATE_PARENT,
761 }, 909 },
762}; 910};
763 911
764static struct clk_mux gxbb_mali_1_sel = { 912static struct clk_regmap gxbb_mali_1_sel = {
765 .reg = (void *)HHI_MALI_CLK_CNTL, 913 .data = &(struct clk_regmap_mux_data){
766 .mask = 0x7, 914 .offset = HHI_MALI_CLK_CNTL,
767 .shift = 25, 915 .mask = 0x7,
768 .table = mux_table_mali_0_1, 916 .shift = 25,
769 .lock = &meson_clk_lock, 917 },
770 .hw.init = &(struct clk_init_data){ 918 .hw.init = &(struct clk_init_data){
771 .name = "mali_1_sel", 919 .name = "mali_1_sel",
772 .ops = &clk_mux_ops, 920 .ops = &clk_regmap_mux_ops,
773 /* 921 /*
774 * bits 10:9 selects from 8 possible parents: 922 * bits 10:9 selects from 8 possible parents:
775 * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 923 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
@@ -781,77 +929,79 @@ static struct clk_mux gxbb_mali_1_sel = {
781 }, 929 },
782}; 930};
783 931
784static struct clk_divider gxbb_mali_1_div = { 932static struct clk_regmap gxbb_mali_1_div = {
785 .reg = (void *)HHI_MALI_CLK_CNTL, 933 .data = &(struct clk_regmap_div_data){
786 .shift = 16, 934 .offset = HHI_MALI_CLK_CNTL,
787 .width = 7, 935 .shift = 16,
788 .lock = &meson_clk_lock, 936 .width = 7,
937 },
789 .hw.init = &(struct clk_init_data){ 938 .hw.init = &(struct clk_init_data){
790 .name = "mali_1_div", 939 .name = "mali_1_div",
791 .ops = &clk_divider_ops, 940 .ops = &clk_regmap_divider_ops,
792 .parent_names = (const char *[]){ "mali_1_sel" }, 941 .parent_names = (const char *[]){ "mali_1_sel" },
793 .num_parents = 1, 942 .num_parents = 1,
794 .flags = CLK_SET_RATE_NO_REPARENT, 943 .flags = CLK_SET_RATE_NO_REPARENT,
795 }, 944 },
796}; 945};
797 946
798static struct clk_gate gxbb_mali_1 = { 947static struct clk_regmap gxbb_mali_1 = {
799 .reg = (void *)HHI_MALI_CLK_CNTL, 948 .data = &(struct clk_regmap_gate_data){
800 .bit_idx = 24, 949 .offset = HHI_MALI_CLK_CNTL,
801 .lock = &meson_clk_lock, 950 .bit_idx = 24,
951 },
802 .hw.init = &(struct clk_init_data){ 952 .hw.init = &(struct clk_init_data){
803 .name = "mali_1", 953 .name = "mali_1",
804 .ops = &clk_gate_ops, 954 .ops = &clk_regmap_gate_ops,
805 .parent_names = (const char *[]){ "mali_1_div" }, 955 .parent_names = (const char *[]){ "mali_1_div" },
806 .num_parents = 1, 956 .num_parents = 1,
807 .flags = CLK_SET_RATE_PARENT, 957 .flags = CLK_SET_RATE_PARENT,
808 }, 958 },
809}; 959};
810 960
811static u32 mux_table_mali[] = {0, 1};
812static const char * const gxbb_mali_parent_names[] = { 961static const char * const gxbb_mali_parent_names[] = {
813 "mali_0", "mali_1" 962 "mali_0", "mali_1"
814}; 963};
815 964
816static struct clk_mux gxbb_mali = { 965static struct clk_regmap gxbb_mali = {
817 .reg = (void *)HHI_MALI_CLK_CNTL, 966 .data = &(struct clk_regmap_mux_data){
818 .mask = 1, 967 .offset = HHI_MALI_CLK_CNTL,
819 .shift = 31, 968 .mask = 1,
820 .table = mux_table_mali, 969 .shift = 31,
821 .lock = &meson_clk_lock, 970 },
822 .hw.init = &(struct clk_init_data){ 971 .hw.init = &(struct clk_init_data){
823 .name = "mali", 972 .name = "mali",
824 .ops = &clk_mux_ops, 973 .ops = &clk_regmap_mux_ops,
825 .parent_names = gxbb_mali_parent_names, 974 .parent_names = gxbb_mali_parent_names,
826 .num_parents = 2, 975 .num_parents = 2,
827 .flags = CLK_SET_RATE_NO_REPARENT, 976 .flags = CLK_SET_RATE_NO_REPARENT,
828 }, 977 },
829}; 978};
830 979
831static struct clk_mux gxbb_cts_amclk_sel = { 980static struct clk_regmap gxbb_cts_amclk_sel = {
832 .reg = (void *) HHI_AUD_CLK_CNTL, 981 .data = &(struct clk_regmap_mux_data){
833 .mask = 0x3, 982 .offset = HHI_AUD_CLK_CNTL,
834 .shift = 9, 983 .mask = 0x3,
835 /* Default parent unknown (register reset value: 0) */ 984 .shift = 9,
836 .table = (u32[]){ 1, 2, 3 }, 985 .table = (u32[]){ 1, 2, 3 },
837 .lock = &meson_clk_lock, 986 },
838 .hw.init = &(struct clk_init_data){ 987 .hw.init = &(struct clk_init_data){
839 .name = "cts_amclk_sel", 988 .name = "cts_amclk_sel",
840 .ops = &clk_mux_ops, 989 .ops = &clk_regmap_mux_ops,
841 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, 990 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
842 .num_parents = 3, 991 .num_parents = 3,
843 .flags = CLK_SET_RATE_PARENT, 992 .flags = CLK_SET_RATE_PARENT,
844 }, 993 },
845}; 994};
846 995
847static struct meson_clk_audio_divider gxbb_cts_amclk_div = { 996static struct clk_regmap gxbb_cts_amclk_div = {
848 .div = { 997 .data = &(struct meson_clk_audio_div_data){
849 .reg_off = HHI_AUD_CLK_CNTL, 998 .div = {
850 .shift = 0, 999 .reg_off = HHI_AUD_CLK_CNTL,
851 .width = 8, 1000 .shift = 0,
1001 .width = 8,
1002 },
1003 .flags = CLK_DIVIDER_ROUND_CLOSEST,
852 }, 1004 },
853 .flags = CLK_DIVIDER_ROUND_CLOSEST,
854 .lock = &meson_clk_lock,
855 .hw.init = &(struct clk_init_data){ 1005 .hw.init = &(struct clk_init_data){
856 .name = "cts_amclk_div", 1006 .name = "cts_amclk_div",
857 .ops = &meson_clk_audio_divider_ops, 1007 .ops = &meson_clk_audio_divider_ops,
@@ -861,71 +1011,75 @@ static struct meson_clk_audio_divider gxbb_cts_amclk_div = {
861 }, 1011 },
862}; 1012};
863 1013
864static struct clk_gate gxbb_cts_amclk = { 1014static struct clk_regmap gxbb_cts_amclk = {
865 .reg = (void *) HHI_AUD_CLK_CNTL, 1015 .data = &(struct clk_regmap_gate_data){
866 .bit_idx = 8, 1016 .offset = HHI_AUD_CLK_CNTL,
867 .lock = &meson_clk_lock, 1017 .bit_idx = 8,
1018 },
868 .hw.init = &(struct clk_init_data){ 1019 .hw.init = &(struct clk_init_data){
869 .name = "cts_amclk", 1020 .name = "cts_amclk",
870 .ops = &clk_gate_ops, 1021 .ops = &clk_regmap_gate_ops,
871 .parent_names = (const char *[]){ "cts_amclk_div" }, 1022 .parent_names = (const char *[]){ "cts_amclk_div" },
872 .num_parents = 1, 1023 .num_parents = 1,
873 .flags = CLK_SET_RATE_PARENT, 1024 .flags = CLK_SET_RATE_PARENT,
874 }, 1025 },
875}; 1026};
876 1027
877static struct clk_mux gxbb_cts_mclk_i958_sel = { 1028static struct clk_regmap gxbb_cts_mclk_i958_sel = {
878 .reg = (void *)HHI_AUD_CLK_CNTL2, 1029 .data = &(struct clk_regmap_mux_data){
879 .mask = 0x3, 1030 .offset = HHI_AUD_CLK_CNTL2,
880 .shift = 25, 1031 .mask = 0x3,
881 /* Default parent unknown (register reset value: 0) */ 1032 .shift = 25,
882 .table = (u32[]){ 1, 2, 3 }, 1033 .table = (u32[]){ 1, 2, 3 },
883 .lock = &meson_clk_lock, 1034 },
884 .hw.init = &(struct clk_init_data) { 1035 .hw.init = &(struct clk_init_data) {
885 .name = "cts_mclk_i958_sel", 1036 .name = "cts_mclk_i958_sel",
886 .ops = &clk_mux_ops, 1037 .ops = &clk_regmap_mux_ops,
887 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, 1038 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
888 .num_parents = 3, 1039 .num_parents = 3,
889 .flags = CLK_SET_RATE_PARENT, 1040 .flags = CLK_SET_RATE_PARENT,
890 }, 1041 },
891}; 1042};
892 1043
893static struct clk_divider gxbb_cts_mclk_i958_div = { 1044static struct clk_regmap gxbb_cts_mclk_i958_div = {
894 .reg = (void *)HHI_AUD_CLK_CNTL2, 1045 .data = &(struct clk_regmap_div_data){
895 .shift = 16, 1046 .offset = HHI_AUD_CLK_CNTL2,
896 .width = 8, 1047 .shift = 16,
897 .lock = &meson_clk_lock, 1048 .width = 8,
898 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1049 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1050 },
899 .hw.init = &(struct clk_init_data) { 1051 .hw.init = &(struct clk_init_data) {
900 .name = "cts_mclk_i958_div", 1052 .name = "cts_mclk_i958_div",
901 .ops = &clk_divider_ops, 1053 .ops = &clk_regmap_divider_ops,
902 .parent_names = (const char *[]){ "cts_mclk_i958_sel" }, 1054 .parent_names = (const char *[]){ "cts_mclk_i958_sel" },
903 .num_parents = 1, 1055 .num_parents = 1,
904 .flags = CLK_SET_RATE_PARENT, 1056 .flags = CLK_SET_RATE_PARENT,
905 }, 1057 },
906}; 1058};
907 1059
908static struct clk_gate gxbb_cts_mclk_i958 = { 1060static struct clk_regmap gxbb_cts_mclk_i958 = {
909 .reg = (void *)HHI_AUD_CLK_CNTL2, 1061 .data = &(struct clk_regmap_gate_data){
910 .bit_idx = 24, 1062 .offset = HHI_AUD_CLK_CNTL2,
911 .lock = &meson_clk_lock, 1063 .bit_idx = 24,
1064 },
912 .hw.init = &(struct clk_init_data){ 1065 .hw.init = &(struct clk_init_data){
913 .name = "cts_mclk_i958", 1066 .name = "cts_mclk_i958",
914 .ops = &clk_gate_ops, 1067 .ops = &clk_regmap_gate_ops,
915 .parent_names = (const char *[]){ "cts_mclk_i958_div" }, 1068 .parent_names = (const char *[]){ "cts_mclk_i958_div" },
916 .num_parents = 1, 1069 .num_parents = 1,
917 .flags = CLK_SET_RATE_PARENT, 1070 .flags = CLK_SET_RATE_PARENT,
918 }, 1071 },
919}; 1072};
920 1073
921static struct clk_mux gxbb_cts_i958 = { 1074static struct clk_regmap gxbb_cts_i958 = {
922 .reg = (void *)HHI_AUD_CLK_CNTL2, 1075 .data = &(struct clk_regmap_mux_data){
923 .mask = 0x1, 1076 .offset = HHI_AUD_CLK_CNTL2,
924 .shift = 27, 1077 .mask = 0x1,
925 .lock = &meson_clk_lock, 1078 .shift = 27,
926 .hw.init = &(struct clk_init_data){ 1079 },
1080 .hw.init = &(struct clk_init_data){
927 .name = "cts_i958", 1081 .name = "cts_i958",
928 .ops = &clk_mux_ops, 1082 .ops = &clk_regmap_mux_ops,
929 .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" }, 1083 .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" },
930 .num_parents = 2, 1084 .num_parents = 2,
931 /* 1085 /*
@@ -936,27 +1090,29 @@ static struct clk_mux gxbb_cts_i958 = {
936 }, 1090 },
937}; 1091};
938 1092
939static struct clk_divider gxbb_32k_clk_div = { 1093static struct clk_regmap gxbb_32k_clk_div = {
940 .reg = (void *)HHI_32K_CLK_CNTL, 1094 .data = &(struct clk_regmap_div_data){
941 .shift = 0, 1095 .offset = HHI_32K_CLK_CNTL,
942 .width = 14, 1096 .shift = 0,
943 .lock = &meson_clk_lock, 1097 .width = 14,
1098 },
944 .hw.init = &(struct clk_init_data){ 1099 .hw.init = &(struct clk_init_data){
945 .name = "32k_clk_div", 1100 .name = "32k_clk_div",
946 .ops = &clk_divider_ops, 1101 .ops = &clk_regmap_divider_ops,
947 .parent_names = (const char *[]){ "32k_clk_sel" }, 1102 .parent_names = (const char *[]){ "32k_clk_sel" },
948 .num_parents = 1, 1103 .num_parents = 1,
949 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, 1104 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
950 }, 1105 },
951}; 1106};
952 1107
953static struct clk_gate gxbb_32k_clk = { 1108static struct clk_regmap gxbb_32k_clk = {
954 .reg = (void *)HHI_32K_CLK_CNTL, 1109 .data = &(struct clk_regmap_gate_data){
955 .bit_idx = 15, 1110 .offset = HHI_32K_CLK_CNTL,
956 .lock = &meson_clk_lock, 1111 .bit_idx = 15,
1112 },
957 .hw.init = &(struct clk_init_data){ 1113 .hw.init = &(struct clk_init_data){
958 .name = "32k_clk", 1114 .name = "32k_clk",
959 .ops = &clk_gate_ops, 1115 .ops = &clk_regmap_gate_ops,
960 .parent_names = (const char *[]){ "32k_clk_div" }, 1116 .parent_names = (const char *[]){ "32k_clk_div" },
961 .num_parents = 1, 1117 .num_parents = 1,
962 .flags = CLK_SET_RATE_PARENT, 1118 .flags = CLK_SET_RATE_PARENT,
@@ -967,14 +1123,15 @@ static const char * const gxbb_32k_clk_parent_names[] = {
967 "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5" 1123 "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
968}; 1124};
969 1125
970static struct clk_mux gxbb_32k_clk_sel = { 1126static struct clk_regmap gxbb_32k_clk_sel = {
971 .reg = (void *)HHI_32K_CLK_CNTL, 1127 .data = &(struct clk_regmap_mux_data){
972 .mask = 0x3, 1128 .offset = HHI_32K_CLK_CNTL,
973 .shift = 16, 1129 .mask = 0x3,
974 .lock = &meson_clk_lock, 1130 .shift = 16,
975 .hw.init = &(struct clk_init_data){ 1131 },
1132 .hw.init = &(struct clk_init_data){
976 .name = "32k_clk_sel", 1133 .name = "32k_clk_sel",
977 .ops = &clk_mux_ops, 1134 .ops = &clk_regmap_mux_ops,
978 .parent_names = gxbb_32k_clk_parent_names, 1135 .parent_names = gxbb_32k_clk_parent_names,
979 .num_parents = 4, 1136 .num_parents = 4,
980 .flags = CLK_SET_RATE_PARENT, 1137 .flags = CLK_SET_RATE_PARENT,
@@ -993,42 +1150,45 @@ static const char * const gxbb_sd_emmc_clk0_parent_names[] = {
993}; 1150};
994 1151
995/* SDIO clock */ 1152/* SDIO clock */
996static struct clk_mux gxbb_sd_emmc_a_clk0_sel = { 1153static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
997 .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 1154 .data = &(struct clk_regmap_mux_data){
998 .mask = 0x7, 1155 .offset = HHI_SD_EMMC_CLK_CNTL,
999 .shift = 9, 1156 .mask = 0x7,
1000 .lock = &meson_clk_lock, 1157 .shift = 9,
1158 },
1001 .hw.init = &(struct clk_init_data) { 1159 .hw.init = &(struct clk_init_data) {
1002 .name = "sd_emmc_a_clk0_sel", 1160 .name = "sd_emmc_a_clk0_sel",
1003 .ops = &clk_mux_ops, 1161 .ops = &clk_regmap_mux_ops,
1004 .parent_names = gxbb_sd_emmc_clk0_parent_names, 1162 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1005 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1163 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1006 .flags = CLK_SET_RATE_PARENT, 1164 .flags = CLK_SET_RATE_PARENT,
1007 }, 1165 },
1008}; 1166};
1009 1167
1010static struct clk_divider gxbb_sd_emmc_a_clk0_div = { 1168static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
1011 .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 1169 .data = &(struct clk_regmap_div_data){
1012 .shift = 0, 1170 .offset = HHI_SD_EMMC_CLK_CNTL,
1013 .width = 7, 1171 .shift = 0,
1014 .lock = &meson_clk_lock, 1172 .width = 7,
1015 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1173 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1174 },
1016 .hw.init = &(struct clk_init_data) { 1175 .hw.init = &(struct clk_init_data) {
1017 .name = "sd_emmc_a_clk0_div", 1176 .name = "sd_emmc_a_clk0_div",
1018 .ops = &clk_divider_ops, 1177 .ops = &clk_regmap_divider_ops,
1019 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" }, 1178 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
1020 .num_parents = 1, 1179 .num_parents = 1,
1021 .flags = CLK_SET_RATE_PARENT, 1180 .flags = CLK_SET_RATE_PARENT,
1022 }, 1181 },
1023}; 1182};
1024 1183
1025static struct clk_gate gxbb_sd_emmc_a_clk0 = { 1184static struct clk_regmap gxbb_sd_emmc_a_clk0 = {
1026 .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 1185 .data = &(struct clk_regmap_gate_data){
1027 .bit_idx = 7, 1186 .offset = HHI_SD_EMMC_CLK_CNTL,
1028 .lock = &meson_clk_lock, 1187 .bit_idx = 7,
1188 },
1029 .hw.init = &(struct clk_init_data){ 1189 .hw.init = &(struct clk_init_data){
1030 .name = "sd_emmc_a_clk0", 1190 .name = "sd_emmc_a_clk0",
1031 .ops = &clk_gate_ops, 1191 .ops = &clk_regmap_gate_ops,
1032 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" }, 1192 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
1033 .num_parents = 1, 1193 .num_parents = 1,
1034 .flags = CLK_SET_RATE_PARENT, 1194 .flags = CLK_SET_RATE_PARENT,
@@ -1036,42 +1196,45 @@ static struct clk_gate gxbb_sd_emmc_a_clk0 = {
1036}; 1196};
1037 1197
1038/* SDcard clock */ 1198/* SDcard clock */
1039static struct clk_mux gxbb_sd_emmc_b_clk0_sel = { 1199static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
1040 .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 1200 .data = &(struct clk_regmap_mux_data){
1041 .mask = 0x7, 1201 .offset = HHI_SD_EMMC_CLK_CNTL,
1042 .shift = 25, 1202 .mask = 0x7,
1043 .lock = &meson_clk_lock, 1203 .shift = 25,
1204 },
1044 .hw.init = &(struct clk_init_data) { 1205 .hw.init = &(struct clk_init_data) {
1045 .name = "sd_emmc_b_clk0_sel", 1206 .name = "sd_emmc_b_clk0_sel",
1046 .ops = &clk_mux_ops, 1207 .ops = &clk_regmap_mux_ops,
1047 .parent_names = gxbb_sd_emmc_clk0_parent_names, 1208 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1048 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1209 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1049 .flags = CLK_SET_RATE_PARENT, 1210 .flags = CLK_SET_RATE_PARENT,
1050 }, 1211 },
1051}; 1212};
1052 1213
1053static struct clk_divider gxbb_sd_emmc_b_clk0_div = { 1214static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
1054 .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 1215 .data = &(struct clk_regmap_div_data){
1055 .shift = 16, 1216 .offset = HHI_SD_EMMC_CLK_CNTL,
1056 .width = 7, 1217 .shift = 16,
1057 .lock = &meson_clk_lock, 1218 .width = 7,
1058 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1219 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1220 },
1059 .hw.init = &(struct clk_init_data) { 1221 .hw.init = &(struct clk_init_data) {
1060 .name = "sd_emmc_b_clk0_div", 1222 .name = "sd_emmc_b_clk0_div",
1061 .ops = &clk_divider_ops, 1223 .ops = &clk_regmap_divider_ops,
1062 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, 1224 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
1063 .num_parents = 1, 1225 .num_parents = 1,
1064 .flags = CLK_SET_RATE_PARENT, 1226 .flags = CLK_SET_RATE_PARENT,
1065 }, 1227 },
1066}; 1228};
1067 1229
1068static struct clk_gate gxbb_sd_emmc_b_clk0 = { 1230static struct clk_regmap gxbb_sd_emmc_b_clk0 = {
1069 .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 1231 .data = &(struct clk_regmap_gate_data){
1070 .bit_idx = 23, 1232 .offset = HHI_SD_EMMC_CLK_CNTL,
1071 .lock = &meson_clk_lock, 1233 .bit_idx = 23,
1234 },
1072 .hw.init = &(struct clk_init_data){ 1235 .hw.init = &(struct clk_init_data){
1073 .name = "sd_emmc_b_clk0", 1236 .name = "sd_emmc_b_clk0",
1074 .ops = &clk_gate_ops, 1237 .ops = &clk_regmap_gate_ops,
1075 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" }, 1238 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
1076 .num_parents = 1, 1239 .num_parents = 1,
1077 .flags = CLK_SET_RATE_PARENT, 1240 .flags = CLK_SET_RATE_PARENT,
@@ -1079,42 +1242,45 @@ static struct clk_gate gxbb_sd_emmc_b_clk0 = {
1079}; 1242};
1080 1243
1081/* EMMC/NAND clock */ 1244/* EMMC/NAND clock */
1082static struct clk_mux gxbb_sd_emmc_c_clk0_sel = { 1245static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
1083 .reg = (void *)HHI_NAND_CLK_CNTL, 1246 .data = &(struct clk_regmap_mux_data){
1084 .mask = 0x7, 1247 .offset = HHI_NAND_CLK_CNTL,
1085 .shift = 9, 1248 .mask = 0x7,
1086 .lock = &meson_clk_lock, 1249 .shift = 9,
1250 },
1087 .hw.init = &(struct clk_init_data) { 1251 .hw.init = &(struct clk_init_data) {
1088 .name = "sd_emmc_c_clk0_sel", 1252 .name = "sd_emmc_c_clk0_sel",
1089 .ops = &clk_mux_ops, 1253 .ops = &clk_regmap_mux_ops,
1090 .parent_names = gxbb_sd_emmc_clk0_parent_names, 1254 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1091 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1255 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1092 .flags = CLK_SET_RATE_PARENT, 1256 .flags = CLK_SET_RATE_PARENT,
1093 }, 1257 },
1094}; 1258};
1095 1259
1096static struct clk_divider gxbb_sd_emmc_c_clk0_div = { 1260static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
1097 .reg = (void *)HHI_NAND_CLK_CNTL, 1261 .data = &(struct clk_regmap_div_data){
1098 .shift = 0, 1262 .offset = HHI_NAND_CLK_CNTL,
1099 .width = 7, 1263 .shift = 0,
1100 .lock = &meson_clk_lock, 1264 .width = 7,
1101 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1265 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1266 },
1102 .hw.init = &(struct clk_init_data) { 1267 .hw.init = &(struct clk_init_data) {
1103 .name = "sd_emmc_c_clk0_div", 1268 .name = "sd_emmc_c_clk0_div",
1104 .ops = &clk_divider_ops, 1269 .ops = &clk_regmap_divider_ops,
1105 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, 1270 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
1106 .num_parents = 1, 1271 .num_parents = 1,
1107 .flags = CLK_SET_RATE_PARENT, 1272 .flags = CLK_SET_RATE_PARENT,
1108 }, 1273 },
1109}; 1274};
1110 1275
1111static struct clk_gate gxbb_sd_emmc_c_clk0 = { 1276static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
1112 .reg = (void *)HHI_NAND_CLK_CNTL, 1277 .data = &(struct clk_regmap_gate_data){
1113 .bit_idx = 7, 1278 .offset = HHI_NAND_CLK_CNTL,
1114 .lock = &meson_clk_lock, 1279 .bit_idx = 7,
1280 },
1115 .hw.init = &(struct clk_init_data){ 1281 .hw.init = &(struct clk_init_data){
1116 .name = "sd_emmc_c_clk0", 1282 .name = "sd_emmc_c_clk0",
1117 .ops = &clk_gate_ops, 1283 .ops = &clk_regmap_gate_ops,
1118 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" }, 1284 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
1119 .num_parents = 1, 1285 .num_parents = 1,
1120 .flags = CLK_SET_RATE_PARENT, 1286 .flags = CLK_SET_RATE_PARENT,
@@ -1123,20 +1289,19 @@ static struct clk_gate gxbb_sd_emmc_c_clk0 = {
1123 1289
1124/* VPU Clock */ 1290/* VPU Clock */
1125 1291
1126static u32 mux_table_vpu[] = {0, 1, 2, 3};
1127static const char * const gxbb_vpu_parent_names[] = { 1292static const char * const gxbb_vpu_parent_names[] = {
1128 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" 1293 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1129}; 1294};
1130 1295
1131static struct clk_mux gxbb_vpu_0_sel = { 1296static struct clk_regmap gxbb_vpu_0_sel = {
1132 .reg = (void *)HHI_VPU_CLK_CNTL, 1297 .data = &(struct clk_regmap_mux_data){
1133 .mask = 0x3, 1298 .offset = HHI_VPU_CLK_CNTL,
1134 .shift = 9, 1299 .mask = 0x3,
1135 .lock = &meson_clk_lock, 1300 .shift = 9,
1136 .table = mux_table_vpu, 1301 },
1137 .hw.init = &(struct clk_init_data){ 1302 .hw.init = &(struct clk_init_data){
1138 .name = "vpu_0_sel", 1303 .name = "vpu_0_sel",
1139 .ops = &clk_mux_ops, 1304 .ops = &clk_regmap_mux_ops,
1140 /* 1305 /*
1141 * bits 9:10 selects from 4 possible parents: 1306 * bits 9:10 selects from 4 possible parents:
1142 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1307 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
@@ -1147,42 +1312,44 @@ static struct clk_mux gxbb_vpu_0_sel = {
1147 }, 1312 },
1148}; 1313};
1149 1314
1150static struct clk_divider gxbb_vpu_0_div = { 1315static struct clk_regmap gxbb_vpu_0_div = {
1151 .reg = (void *)HHI_VPU_CLK_CNTL, 1316 .data = &(struct clk_regmap_div_data){
1152 .shift = 0, 1317 .offset = HHI_VPU_CLK_CNTL,
1153 .width = 7, 1318 .shift = 0,
1154 .lock = &meson_clk_lock, 1319 .width = 7,
1320 },
1155 .hw.init = &(struct clk_init_data){ 1321 .hw.init = &(struct clk_init_data){
1156 .name = "vpu_0_div", 1322 .name = "vpu_0_div",
1157 .ops = &clk_divider_ops, 1323 .ops = &clk_regmap_divider_ops,
1158 .parent_names = (const char *[]){ "vpu_0_sel" }, 1324 .parent_names = (const char *[]){ "vpu_0_sel" },
1159 .num_parents = 1, 1325 .num_parents = 1,
1160 .flags = CLK_SET_RATE_PARENT, 1326 .flags = CLK_SET_RATE_PARENT,
1161 }, 1327 },
1162}; 1328};
1163 1329
1164static struct clk_gate gxbb_vpu_0 = { 1330static struct clk_regmap gxbb_vpu_0 = {
1165 .reg = (void *)HHI_VPU_CLK_CNTL, 1331 .data = &(struct clk_regmap_gate_data){
1166 .bit_idx = 8, 1332 .offset = HHI_VPU_CLK_CNTL,
1167 .lock = &meson_clk_lock, 1333 .bit_idx = 8,
1334 },
1168 .hw.init = &(struct clk_init_data) { 1335 .hw.init = &(struct clk_init_data) {
1169 .name = "vpu_0", 1336 .name = "vpu_0",
1170 .ops = &clk_gate_ops, 1337 .ops = &clk_regmap_gate_ops,
1171 .parent_names = (const char *[]){ "vpu_0_div" }, 1338 .parent_names = (const char *[]){ "vpu_0_div" },
1172 .num_parents = 1, 1339 .num_parents = 1,
1173 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1340 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1174 }, 1341 },
1175}; 1342};
1176 1343
1177static struct clk_mux gxbb_vpu_1_sel = { 1344static struct clk_regmap gxbb_vpu_1_sel = {
1178 .reg = (void *)HHI_VPU_CLK_CNTL, 1345 .data = &(struct clk_regmap_mux_data){
1179 .mask = 0x3, 1346 .offset = HHI_VPU_CLK_CNTL,
1180 .shift = 25, 1347 .mask = 0x3,
1181 .lock = &meson_clk_lock, 1348 .shift = 25,
1182 .table = mux_table_vpu, 1349 },
1183 .hw.init = &(struct clk_init_data){ 1350 .hw.init = &(struct clk_init_data){
1184 .name = "vpu_1_sel", 1351 .name = "vpu_1_sel",
1185 .ops = &clk_mux_ops, 1352 .ops = &clk_regmap_mux_ops,
1186 /* 1353 /*
1187 * bits 25:26 selects from 4 possible parents: 1354 * bits 25:26 selects from 4 possible parents:
1188 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1355 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
@@ -1193,41 +1360,44 @@ static struct clk_mux gxbb_vpu_1_sel = {
1193 }, 1360 },
1194}; 1361};
1195 1362
1196static struct clk_divider gxbb_vpu_1_div = { 1363static struct clk_regmap gxbb_vpu_1_div = {
1197 .reg = (void *)HHI_VPU_CLK_CNTL, 1364 .data = &(struct clk_regmap_div_data){
1198 .shift = 16, 1365 .offset = HHI_VPU_CLK_CNTL,
1199 .width = 7, 1366 .shift = 16,
1200 .lock = &meson_clk_lock, 1367 .width = 7,
1368 },
1201 .hw.init = &(struct clk_init_data){ 1369 .hw.init = &(struct clk_init_data){
1202 .name = "vpu_1_div", 1370 .name = "vpu_1_div",
1203 .ops = &clk_divider_ops, 1371 .ops = &clk_regmap_divider_ops,
1204 .parent_names = (const char *[]){ "vpu_1_sel" }, 1372 .parent_names = (const char *[]){ "vpu_1_sel" },
1205 .num_parents = 1, 1373 .num_parents = 1,
1206 .flags = CLK_SET_RATE_PARENT, 1374 .flags = CLK_SET_RATE_PARENT,
1207 }, 1375 },
1208}; 1376};
1209 1377
1210static struct clk_gate gxbb_vpu_1 = { 1378static struct clk_regmap gxbb_vpu_1 = {
1211 .reg = (void *)HHI_VPU_CLK_CNTL, 1379 .data = &(struct clk_regmap_gate_data){
1212 .bit_idx = 24, 1380 .offset = HHI_VPU_CLK_CNTL,
1213 .lock = &meson_clk_lock, 1381 .bit_idx = 24,
1382 },
1214 .hw.init = &(struct clk_init_data) { 1383 .hw.init = &(struct clk_init_data) {
1215 .name = "vpu_1", 1384 .name = "vpu_1",
1216 .ops = &clk_gate_ops, 1385 .ops = &clk_regmap_gate_ops,
1217 .parent_names = (const char *[]){ "vpu_1_div" }, 1386 .parent_names = (const char *[]){ "vpu_1_div" },
1218 .num_parents = 1, 1387 .num_parents = 1,
1219 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1388 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1220 }, 1389 },
1221}; 1390};
1222 1391
1223static struct clk_mux gxbb_vpu = { 1392static struct clk_regmap gxbb_vpu = {
1224 .reg = (void *)HHI_VPU_CLK_CNTL, 1393 .data = &(struct clk_regmap_mux_data){
1225 .mask = 1, 1394 .offset = HHI_VPU_CLK_CNTL,
1226 .shift = 31, 1395 .mask = 1,
1227 .lock = &meson_clk_lock, 1396 .shift = 31,
1397 },
1228 .hw.init = &(struct clk_init_data){ 1398 .hw.init = &(struct clk_init_data){
1229 .name = "vpu", 1399 .name = "vpu",
1230 .ops = &clk_mux_ops, 1400 .ops = &clk_regmap_mux_ops,
1231 /* 1401 /*
1232 * bit 31 selects from 2 possible parents: 1402 * bit 31 selects from 2 possible parents:
1233 * vpu_0 or vpu_1 1403 * vpu_0 or vpu_1
@@ -1240,20 +1410,19 @@ static struct clk_mux gxbb_vpu = {
1240 1410
1241/* VAPB Clock */ 1411/* VAPB Clock */
1242 1412
1243static u32 mux_table_vapb[] = {0, 1, 2, 3};
1244static const char * const gxbb_vapb_parent_names[] = { 1413static const char * const gxbb_vapb_parent_names[] = {
1245 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" 1414 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1246}; 1415};
1247 1416
1248static struct clk_mux gxbb_vapb_0_sel = { 1417static struct clk_regmap gxbb_vapb_0_sel = {
1249 .reg = (void *)HHI_VAPBCLK_CNTL, 1418 .data = &(struct clk_regmap_mux_data){
1250 .mask = 0x3, 1419 .offset = HHI_VAPBCLK_CNTL,
1251 .shift = 9, 1420 .mask = 0x3,
1252 .lock = &meson_clk_lock, 1421 .shift = 9,
1253 .table = mux_table_vapb, 1422 },
1254 .hw.init = &(struct clk_init_data){ 1423 .hw.init = &(struct clk_init_data){
1255 .name = "vapb_0_sel", 1424 .name = "vapb_0_sel",
1256 .ops = &clk_mux_ops, 1425 .ops = &clk_regmap_mux_ops,
1257 /* 1426 /*
1258 * bits 9:10 selects from 4 possible parents: 1427 * bits 9:10 selects from 4 possible parents:
1259 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1428 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
@@ -1264,42 +1433,44 @@ static struct clk_mux gxbb_vapb_0_sel = {
1264 }, 1433 },
1265}; 1434};
1266 1435
1267static struct clk_divider gxbb_vapb_0_div = { 1436static struct clk_regmap gxbb_vapb_0_div = {
1268 .reg = (void *)HHI_VAPBCLK_CNTL, 1437 .data = &(struct clk_regmap_div_data){
1269 .shift = 0, 1438 .offset = HHI_VAPBCLK_CNTL,
1270 .width = 7, 1439 .shift = 0,
1271 .lock = &meson_clk_lock, 1440 .width = 7,
1441 },
1272 .hw.init = &(struct clk_init_data){ 1442 .hw.init = &(struct clk_init_data){
1273 .name = "vapb_0_div", 1443 .name = "vapb_0_div",
1274 .ops = &clk_divider_ops, 1444 .ops = &clk_regmap_divider_ops,
1275 .parent_names = (const char *[]){ "vapb_0_sel" }, 1445 .parent_names = (const char *[]){ "vapb_0_sel" },
1276 .num_parents = 1, 1446 .num_parents = 1,
1277 .flags = CLK_SET_RATE_PARENT, 1447 .flags = CLK_SET_RATE_PARENT,
1278 }, 1448 },
1279}; 1449};
1280 1450
1281static struct clk_gate gxbb_vapb_0 = { 1451static struct clk_regmap gxbb_vapb_0 = {
1282 .reg = (void *)HHI_VAPBCLK_CNTL, 1452 .data = &(struct clk_regmap_gate_data){
1283 .bit_idx = 8, 1453 .offset = HHI_VAPBCLK_CNTL,
1284 .lock = &meson_clk_lock, 1454 .bit_idx = 8,
1455 },
1285 .hw.init = &(struct clk_init_data) { 1456 .hw.init = &(struct clk_init_data) {
1286 .name = "vapb_0", 1457 .name = "vapb_0",
1287 .ops = &clk_gate_ops, 1458 .ops = &clk_regmap_gate_ops,
1288 .parent_names = (const char *[]){ "vapb_0_div" }, 1459 .parent_names = (const char *[]){ "vapb_0_div" },
1289 .num_parents = 1, 1460 .num_parents = 1,
1290 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1461 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1291 }, 1462 },
1292}; 1463};
1293 1464
1294static struct clk_mux gxbb_vapb_1_sel = { 1465static struct clk_regmap gxbb_vapb_1_sel = {
1295 .reg = (void *)HHI_VAPBCLK_CNTL, 1466 .data = &(struct clk_regmap_mux_data){
1296 .mask = 0x3, 1467 .offset = HHI_VAPBCLK_CNTL,
1297 .shift = 25, 1468 .mask = 0x3,
1298 .lock = &meson_clk_lock, 1469 .shift = 25,
1299 .table = mux_table_vapb, 1470 },
1300 .hw.init = &(struct clk_init_data){ 1471 .hw.init = &(struct clk_init_data){
1301 .name = "vapb_1_sel", 1472 .name = "vapb_1_sel",
1302 .ops = &clk_mux_ops, 1473 .ops = &clk_regmap_mux_ops,
1303 /* 1474 /*
1304 * bits 25:26 selects from 4 possible parents: 1475 * bits 25:26 selects from 4 possible parents:
1305 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1476 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
@@ -1310,41 +1481,44 @@ static struct clk_mux gxbb_vapb_1_sel = {
1310 }, 1481 },
1311}; 1482};
1312 1483
1313static struct clk_divider gxbb_vapb_1_div = { 1484static struct clk_regmap gxbb_vapb_1_div = {
1314 .reg = (void *)HHI_VAPBCLK_CNTL, 1485 .data = &(struct clk_regmap_div_data){
1315 .shift = 16, 1486 .offset = HHI_VAPBCLK_CNTL,
1316 .width = 7, 1487 .shift = 16,
1317 .lock = &meson_clk_lock, 1488 .width = 7,
1489 },
1318 .hw.init = &(struct clk_init_data){ 1490 .hw.init = &(struct clk_init_data){
1319 .name = "vapb_1_div", 1491 .name = "vapb_1_div",
1320 .ops = &clk_divider_ops, 1492 .ops = &clk_regmap_divider_ops,
1321 .parent_names = (const char *[]){ "vapb_1_sel" }, 1493 .parent_names = (const char *[]){ "vapb_1_sel" },
1322 .num_parents = 1, 1494 .num_parents = 1,
1323 .flags = CLK_SET_RATE_PARENT, 1495 .flags = CLK_SET_RATE_PARENT,
1324 }, 1496 },
1325}; 1497};
1326 1498
1327static struct clk_gate gxbb_vapb_1 = { 1499static struct clk_regmap gxbb_vapb_1 = {
1328 .reg = (void *)HHI_VAPBCLK_CNTL, 1500 .data = &(struct clk_regmap_gate_data){
1329 .bit_idx = 24, 1501 .offset = HHI_VAPBCLK_CNTL,
1330 .lock = &meson_clk_lock, 1502 .bit_idx = 24,
1503 },
1331 .hw.init = &(struct clk_init_data) { 1504 .hw.init = &(struct clk_init_data) {
1332 .name = "vapb_1", 1505 .name = "vapb_1",
1333 .ops = &clk_gate_ops, 1506 .ops = &clk_regmap_gate_ops,
1334 .parent_names = (const char *[]){ "vapb_1_div" }, 1507 .parent_names = (const char *[]){ "vapb_1_div" },
1335 .num_parents = 1, 1508 .num_parents = 1,
1336 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1509 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1337 }, 1510 },
1338}; 1511};
1339 1512
1340static struct clk_mux gxbb_vapb_sel = { 1513static struct clk_regmap gxbb_vapb_sel = {
1341 .reg = (void *)HHI_VAPBCLK_CNTL, 1514 .data = &(struct clk_regmap_mux_data){
1342 .mask = 1, 1515 .offset = HHI_VAPBCLK_CNTL,
1343 .shift = 31, 1516 .mask = 1,
1344 .lock = &meson_clk_lock, 1517 .shift = 31,
1518 },
1345 .hw.init = &(struct clk_init_data){ 1519 .hw.init = &(struct clk_init_data){
1346 .name = "vapb_sel", 1520 .name = "vapb_sel",
1347 .ops = &clk_mux_ops, 1521 .ops = &clk_regmap_mux_ops,
1348 /* 1522 /*
1349 * bit 31 selects from 2 possible parents: 1523 * bit 31 selects from 2 possible parents:
1350 * vapb_0 or vapb_1 1524 * vapb_0 or vapb_1
@@ -1355,13 +1529,14 @@ static struct clk_mux gxbb_vapb_sel = {
1355 }, 1529 },
1356}; 1530};
1357 1531
1358static struct clk_gate gxbb_vapb = { 1532static struct clk_regmap gxbb_vapb = {
1359 .reg = (void *)HHI_VAPBCLK_CNTL, 1533 .data = &(struct clk_regmap_gate_data){
1360 .bit_idx = 30, 1534 .offset = HHI_VAPBCLK_CNTL,
1361 .lock = &meson_clk_lock, 1535 .bit_idx = 30,
1536 },
1362 .hw.init = &(struct clk_init_data) { 1537 .hw.init = &(struct clk_init_data) {
1363 .name = "vapb", 1538 .name = "vapb",
1364 .ops = &clk_gate_ops, 1539 .ops = &clk_regmap_gate_ops,
1365 .parent_names = (const char *[]){ "vapb_sel" }, 1540 .parent_names = (const char *[]){ "vapb_sel" },
1366 .num_parents = 1, 1541 .num_parents = 1,
1367 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1542 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
@@ -1601,6 +1776,16 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
1601 [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 1776 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
1602 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 1777 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
1603 [CLKID_VAPB] = &gxbb_vapb.hw, 1778 [CLKID_VAPB] = &gxbb_vapb.hw,
1779 [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw,
1780 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
1781 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
1782 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
1783 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
1784 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
1785 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
1786 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
1787 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
1788 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
1604 [NR_CLKS] = NULL, 1789 [NR_CLKS] = NULL,
1605 }, 1790 },
1606 .num = NR_CLKS, 1791 .num = NR_CLKS,
@@ -1609,7 +1794,7 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
1609static struct clk_hw_onecell_data gxl_hw_onecell_data = { 1794static struct clk_hw_onecell_data gxl_hw_onecell_data = {
1610 .hws = { 1795 .hws = {
1611 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 1796 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
1612 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 1797 [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw,
1613 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 1798 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
1614 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 1799 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
1615 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 1800 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
@@ -1748,34 +1933,31 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
1748 [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 1933 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
1749 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 1934 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
1750 [CLKID_VAPB] = &gxbb_vapb.hw, 1935 [CLKID_VAPB] = &gxbb_vapb.hw,
1936 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
1937 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
1938 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
1939 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
1940 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
1941 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
1942 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
1943 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
1944 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
1751 [NR_CLKS] = NULL, 1945 [NR_CLKS] = NULL,
1752 }, 1946 },
1753 .num = NR_CLKS, 1947 .num = NR_CLKS,
1754}; 1948};
1755 1949
1756/* Convenience tables to populate base addresses in .probe */ 1950static struct clk_regmap *const gxbb_clk_regmaps[] = {
1757
1758static struct meson_clk_pll *const gxbb_clk_plls[] = {
1759 &gxbb_fixed_pll,
1760 &gxbb_hdmi_pll,
1761 &gxbb_sys_pll,
1762 &gxbb_gp0_pll, 1951 &gxbb_gp0_pll,
1763};
1764
1765static struct meson_clk_pll *const gxl_clk_plls[] = {
1766 &gxbb_fixed_pll,
1767 &gxbb_hdmi_pll, 1952 &gxbb_hdmi_pll,
1768 &gxbb_sys_pll,
1769 &gxl_gp0_pll,
1770}; 1953};
1771 1954
1772static struct meson_clk_mpll *const gxbb_clk_mplls[] = { 1955static struct clk_regmap *const gxl_clk_regmaps[] = {
1773 &gxbb_mpll0, 1956 &gxl_gp0_pll,
1774 &gxbb_mpll1, 1957 &gxl_hdmi_pll,
1775 &gxbb_mpll2,
1776}; 1958};
1777 1959
1778static struct clk_gate *const gxbb_clk_gates[] = { 1960static struct clk_regmap *const gx_clk_regmaps[] = {
1779 &gxbb_clk81, 1961 &gxbb_clk81,
1780 &gxbb_ddr, 1962 &gxbb_ddr,
1781 &gxbb_dos, 1963 &gxbb_dos,
@@ -1872,9 +2054,19 @@ static struct clk_gate *const gxbb_clk_gates[] = {
1872 &gxbb_vapb_0, 2054 &gxbb_vapb_0,
1873 &gxbb_vapb_1, 2055 &gxbb_vapb_1,
1874 &gxbb_vapb, 2056 &gxbb_vapb,
1875}; 2057 &gxbb_mpeg_clk_div,
1876 2058 &gxbb_sar_adc_clk_div,
1877static struct clk_mux *const gxbb_clk_muxes[] = { 2059 &gxbb_mali_0_div,
2060 &gxbb_mali_1_div,
2061 &gxbb_cts_mclk_i958_div,
2062 &gxbb_32k_clk_div,
2063 &gxbb_sd_emmc_a_clk0_div,
2064 &gxbb_sd_emmc_b_clk0_div,
2065 &gxbb_sd_emmc_c_clk0_div,
2066 &gxbb_vpu_0_div,
2067 &gxbb_vpu_1_div,
2068 &gxbb_vapb_0_div,
2069 &gxbb_vapb_1_div,
1878 &gxbb_mpeg_clk_sel, 2070 &gxbb_mpeg_clk_sel,
1879 &gxbb_sar_adc_clk_sel, 2071 &gxbb_sar_adc_clk_sel,
1880 &gxbb_mali_0_sel, 2072 &gxbb_mali_0_sel,
@@ -1893,73 +2085,38 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
1893 &gxbb_vapb_0_sel, 2085 &gxbb_vapb_0_sel,
1894 &gxbb_vapb_1_sel, 2086 &gxbb_vapb_1_sel,
1895 &gxbb_vapb_sel, 2087 &gxbb_vapb_sel,
1896}; 2088 &gxbb_mpll0,
1897 2089 &gxbb_mpll1,
1898static struct clk_divider *const gxbb_clk_dividers[] = { 2090 &gxbb_mpll2,
1899 &gxbb_mpeg_clk_div, 2091 &gxbb_mpll0_div,
1900 &gxbb_sar_adc_clk_div, 2092 &gxbb_mpll1_div,
1901 &gxbb_mali_0_div, 2093 &gxbb_mpll2_div,
1902 &gxbb_mali_1_div,
1903 &gxbb_cts_mclk_i958_div,
1904 &gxbb_32k_clk_div,
1905 &gxbb_sd_emmc_a_clk0_div,
1906 &gxbb_sd_emmc_b_clk0_div,
1907 &gxbb_sd_emmc_c_clk0_div,
1908 &gxbb_vpu_0_div,
1909 &gxbb_vpu_1_div,
1910 &gxbb_vapb_0_div,
1911 &gxbb_vapb_1_div,
1912};
1913
1914static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
1915 &gxbb_cts_amclk_div, 2094 &gxbb_cts_amclk_div,
2095 &gxbb_fixed_pll,
2096 &gxbb_sys_pll,
2097 &gxbb_mpll_prediv,
2098 &gxbb_fclk_div2,
2099 &gxbb_fclk_div3,
2100 &gxbb_fclk_div4,
2101 &gxbb_fclk_div5,
2102 &gxbb_fclk_div7,
1916}; 2103};
1917 2104
1918struct clkc_data { 2105struct clkc_data {
1919 struct clk_gate *const *clk_gates; 2106 struct clk_regmap *const *regmap_clks;
1920 unsigned int clk_gates_count; 2107 unsigned int regmap_clks_count;
1921 struct meson_clk_mpll *const *clk_mplls;
1922 unsigned int clk_mplls_count;
1923 struct meson_clk_pll *const *clk_plls;
1924 unsigned int clk_plls_count;
1925 struct clk_mux *const *clk_muxes;
1926 unsigned int clk_muxes_count;
1927 struct clk_divider *const *clk_dividers;
1928 unsigned int clk_dividers_count;
1929 struct meson_clk_audio_divider *const *clk_audio_dividers;
1930 unsigned int clk_audio_dividers_count;
1931 struct clk_hw_onecell_data *hw_onecell_data; 2108 struct clk_hw_onecell_data *hw_onecell_data;
1932}; 2109};
1933 2110
1934static const struct clkc_data gxbb_clkc_data = { 2111static const struct clkc_data gxbb_clkc_data = {
1935 .clk_gates = gxbb_clk_gates, 2112 .regmap_clks = gxbb_clk_regmaps,
1936 .clk_gates_count = ARRAY_SIZE(gxbb_clk_gates), 2113 .regmap_clks_count = ARRAY_SIZE(gxbb_clk_regmaps),
1937 .clk_mplls = gxbb_clk_mplls,
1938 .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls),
1939 .clk_plls = gxbb_clk_plls,
1940 .clk_plls_count = ARRAY_SIZE(gxbb_clk_plls),
1941 .clk_muxes = gxbb_clk_muxes,
1942 .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes),
1943 .clk_dividers = gxbb_clk_dividers,
1944 .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
1945 .clk_audio_dividers = gxbb_audio_dividers,
1946 .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
1947 .hw_onecell_data = &gxbb_hw_onecell_data, 2114 .hw_onecell_data = &gxbb_hw_onecell_data,
1948}; 2115};
1949 2116
1950static const struct clkc_data gxl_clkc_data = { 2117static const struct clkc_data gxl_clkc_data = {
1951 .clk_gates = gxbb_clk_gates, 2118 .regmap_clks = gxl_clk_regmaps,
1952 .clk_gates_count = ARRAY_SIZE(gxbb_clk_gates), 2119 .regmap_clks_count = ARRAY_SIZE(gxl_clk_regmaps),
1953 .clk_mplls = gxbb_clk_mplls,
1954 .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls),
1955 .clk_plls = gxl_clk_plls,
1956 .clk_plls_count = ARRAY_SIZE(gxl_clk_plls),
1957 .clk_muxes = gxbb_clk_muxes,
1958 .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes),
1959 .clk_dividers = gxbb_clk_dividers,
1960 .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
1961 .clk_audio_dividers = gxbb_audio_dividers,
1962 .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
1963 .hw_onecell_data = &gxl_hw_onecell_data, 2120 .hw_onecell_data = &gxl_hw_onecell_data,
1964}; 2121};
1965 2122
@@ -1969,71 +2126,79 @@ static const struct of_device_id clkc_match_table[] = {
1969 {}, 2126 {},
1970}; 2127};
1971 2128
2129static const struct regmap_config clkc_regmap_config = {
2130 .reg_bits = 32,
2131 .val_bits = 32,
2132 .reg_stride = 4,
2133};
2134
1972static int gxbb_clkc_probe(struct platform_device *pdev) 2135static int gxbb_clkc_probe(struct platform_device *pdev)
1973{ 2136{
1974 const struct clkc_data *clkc_data; 2137 const struct clkc_data *clkc_data;
2138 struct resource *res;
1975 void __iomem *clk_base; 2139 void __iomem *clk_base;
1976 int ret, clkid, i; 2140 struct regmap *map;
2141 int ret, i;
1977 struct device *dev = &pdev->dev; 2142 struct device *dev = &pdev->dev;
1978 2143
1979 clkc_data = of_device_get_match_data(&pdev->dev); 2144 clkc_data = of_device_get_match_data(dev);
1980 if (!clkc_data) 2145 if (!clkc_data)
1981 return -EINVAL; 2146 return -EINVAL;
1982 2147
1983 /* Generic clocks and PLLs */ 2148 /* Get the hhi system controller node if available */
1984 clk_base = of_iomap(dev->of_node, 0); 2149 map = syscon_node_to_regmap(of_get_parent(dev->of_node));
1985 if (!clk_base) { 2150 if (IS_ERR(map)) {
1986 pr_err("%s: Unable to map clk base\n", __func__); 2151 dev_err(dev,
1987 return -ENXIO; 2152 "failed to get HHI regmap - Trying obsolete regs\n");
1988 }
1989
1990 /* Populate base address for PLLs */
1991 for (i = 0; i < clkc_data->clk_plls_count; i++)
1992 clkc_data->clk_plls[i]->base = clk_base;
1993
1994 /* Populate base address for MPLLs */
1995 for (i = 0; i < clkc_data->clk_mplls_count; i++)
1996 clkc_data->clk_mplls[i]->base = clk_base;
1997 2153
1998 /* Populate base address for gates */ 2154 /*
1999 for (i = 0; i < clkc_data->clk_gates_count; i++) 2155 * FIXME: HHI registers should be accessed through
2000 clkc_data->clk_gates[i]->reg = clk_base + 2156 * the appropriate system controller. This is required because
2001 (u64)clkc_data->clk_gates[i]->reg; 2157 * there is more than just clocks in this register space
2002 2158 *
2003 /* Populate base address for muxes */ 2159 * This fallback method is only provided temporarily until
2004 for (i = 0; i < clkc_data->clk_muxes_count; i++) 2160 * all the platform DTs are properly using the syscon node
2005 clkc_data->clk_muxes[i]->reg = clk_base + 2161 */
2006 (u64)clkc_data->clk_muxes[i]->reg; 2162 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2163 if (!res)
2164 return -EINVAL;
2165
2166 clk_base = devm_ioremap(dev, res->start, resource_size(res));
2167 if (!clk_base) {
2168 dev_err(dev, "Unable to map clk base\n");
2169 return -ENXIO;
2170 }
2171
2172 map = devm_regmap_init_mmio(dev, clk_base,
2173 &clkc_regmap_config);
2174 if (IS_ERR(map))
2175 return PTR_ERR(map);
2176 }
2007 2177
2008 /* Populate base address for dividers */ 2178 /* Populate regmap for the common regmap backed clocks */
2009 for (i = 0; i < clkc_data->clk_dividers_count; i++) 2179 for (i = 0; i < ARRAY_SIZE(gx_clk_regmaps); i++)
2010 clkc_data->clk_dividers[i]->reg = clk_base + 2180 gx_clk_regmaps[i]->map = map;
2011 (u64)clkc_data->clk_dividers[i]->reg;
2012 2181
2013 /* Populate base address for the audio dividers */ 2182 /* Populate regmap for soc specific clocks */
2014 for (i = 0; i < clkc_data->clk_audio_dividers_count; i++) 2183 for (i = 0; i < clkc_data->regmap_clks_count; i++)
2015 clkc_data->clk_audio_dividers[i]->base = clk_base; 2184 clkc_data->regmap_clks[i]->map = map;
2016 2185
2017 /* 2186 /* Register all clks */
2018 * register all clks 2187 for (i = 0; i < clkc_data->hw_onecell_data->num; i++) {
2019 */
2020 for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) {
2021 /* array might be sparse */ 2188 /* array might be sparse */
2022 if (!clkc_data->hw_onecell_data->hws[clkid]) 2189 if (!clkc_data->hw_onecell_data->hws[i])
2023 continue; 2190 continue;
2024 2191
2025 ret = devm_clk_hw_register(dev, 2192 ret = devm_clk_hw_register(dev,
2026 clkc_data->hw_onecell_data->hws[clkid]); 2193 clkc_data->hw_onecell_data->hws[i]);
2027 if (ret) 2194 if (ret) {
2028 goto iounmap; 2195 dev_err(dev, "Clock registration failed\n");
2196 return ret;
2197 }
2029 } 2198 }
2030 2199
2031 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, 2200 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
2032 clkc_data->hw_onecell_data); 2201 clkc_data->hw_onecell_data);
2033
2034iounmap:
2035 iounmap(clk_base);
2036 return ret;
2037} 2202}
2038 2203
2039static struct platform_driver gxbb_driver = { 2204static struct platform_driver gxbb_driver = {
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