diff options
Diffstat (limited to 'drivers/clk/meson/gxbb-aoclk.c')
-rw-r--r-- | drivers/clk/meson/gxbb-aoclk.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c index 6c161e0a8e59..9ec23ae9a219 100644 --- a/drivers/clk/meson/gxbb-aoclk.c +++ b/drivers/clk/meson/gxbb-aoclk.c | |||
@@ -62,10 +62,9 @@ | |||
62 | #include <linux/delay.h> | 62 | #include <linux/delay.h> |
63 | #include <dt-bindings/clock/gxbb-aoclkc.h> | 63 | #include <dt-bindings/clock/gxbb-aoclkc.h> |
64 | #include <dt-bindings/reset/gxbb-aoclkc.h> | 64 | #include <dt-bindings/reset/gxbb-aoclkc.h> |
65 | #include "clk-regmap.h" | ||
65 | #include "gxbb-aoclk.h" | 66 | #include "gxbb-aoclk.h" |
66 | 67 | ||
67 | static DEFINE_SPINLOCK(gxbb_aoclk_lock); | ||
68 | |||
69 | struct gxbb_aoclk_reset_controller { | 68 | struct gxbb_aoclk_reset_controller { |
70 | struct reset_controller_dev reset; | 69 | struct reset_controller_dev reset; |
71 | unsigned int *data; | 70 | unsigned int *data; |
@@ -87,12 +86,14 @@ static const struct reset_control_ops gxbb_aoclk_reset_ops = { | |||
87 | }; | 86 | }; |
88 | 87 | ||
89 | #define GXBB_AO_GATE(_name, _bit) \ | 88 | #define GXBB_AO_GATE(_name, _bit) \ |
90 | static struct aoclk_gate_regmap _name##_ao = { \ | 89 | static struct clk_regmap _name##_ao = { \ |
91 | .bit_idx = (_bit), \ | 90 | .data = &(struct clk_regmap_gate_data) { \ |
92 | .lock = &gxbb_aoclk_lock, \ | 91 | .offset = AO_RTI_GEN_CNTL_REG0, \ |
92 | .bit_idx = (_bit), \ | ||
93 | }, \ | ||
93 | .hw.init = &(struct clk_init_data) { \ | 94 | .hw.init = &(struct clk_init_data) { \ |
94 | .name = #_name "_ao", \ | 95 | .name = #_name "_ao", \ |
95 | .ops = &meson_aoclk_gate_regmap_ops, \ | 96 | .ops = &clk_regmap_gate_ops, \ |
96 | .parent_names = (const char *[]){ "clk81" }, \ | 97 | .parent_names = (const char *[]){ "clk81" }, \ |
97 | .num_parents = 1, \ | 98 | .num_parents = 1, \ |
98 | .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ | 99 | .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ |
@@ -107,7 +108,6 @@ GXBB_AO_GATE(uart2, 5); | |||
107 | GXBB_AO_GATE(ir_blaster, 6); | 108 | GXBB_AO_GATE(ir_blaster, 6); |
108 | 109 | ||
109 | static struct aoclk_cec_32k cec_32k_ao = { | 110 | static struct aoclk_cec_32k cec_32k_ao = { |
110 | .lock = &gxbb_aoclk_lock, | ||
111 | .hw.init = &(struct clk_init_data) { | 111 | .hw.init = &(struct clk_init_data) { |
112 | .name = "cec_32k_ao", | 112 | .name = "cec_32k_ao", |
113 | .ops = &meson_aoclk_cec_32k_ops, | 113 | .ops = &meson_aoclk_cec_32k_ops, |
@@ -126,7 +126,7 @@ static unsigned int gxbb_aoclk_reset[] = { | |||
126 | [RESET_AO_IR_BLASTER] = 23, | 126 | [RESET_AO_IR_BLASTER] = 23, |
127 | }; | 127 | }; |
128 | 128 | ||
129 | static struct aoclk_gate_regmap *gxbb_aoclk_gate[] = { | 129 | static struct clk_regmap *gxbb_aoclk_gate[] = { |
130 | [CLKID_AO_REMOTE] = &remote_ao, | 130 | [CLKID_AO_REMOTE] = &remote_ao, |
131 | [CLKID_AO_I2C_MASTER] = &i2c_master_ao, | 131 | [CLKID_AO_I2C_MASTER] = &i2c_master_ao, |
132 | [CLKID_AO_I2C_SLAVE] = &i2c_slave_ao, | 132 | [CLKID_AO_I2C_SLAVE] = &i2c_slave_ao, |
@@ -177,10 +177,10 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev) | |||
177 | * Populate regmap and register all clks | 177 | * Populate regmap and register all clks |
178 | */ | 178 | */ |
179 | for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) { | 179 | for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) { |
180 | gxbb_aoclk_gate[clkid]->regmap = regmap; | 180 | gxbb_aoclk_gate[clkid]->map = regmap; |
181 | 181 | ||
182 | ret = devm_clk_hw_register(dev, | 182 | ret = devm_clk_hw_register(dev, |
183 | gxbb_aoclk_onecell_data.hws[clkid]); | 183 | gxbb_aoclk_onecell_data.hws[clkid]); |
184 | if (ret) | 184 | if (ret) |
185 | return ret; | 185 | return ret; |
186 | } | 186 | } |