1 files changed, 20 insertions, 17 deletions

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 6a31f7f434ce..a0ae8dc16909 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -121,7 +121,7 @@ static const char * const cpu_src[] = {
 };
 
 static const char * const axi_src[] = {
-        "ck_hsi", "ck_hse", "pll2_p", "pll3_p"
+        "ck_hsi", "ck_hse", "pll2_p"
 };
 
 static const char * const per_src[] = {
@@ -225,19 +225,19 @@ static const char * const usart6_src[] = {
 };
 
 static const char * const fdcan_src[] = {
-        "ck_hse", "pll3_q", "pll4_q"
+        "ck_hse", "pll3_q", "pll4_q", "pll4_r"
 };
 
 static const char * const sai_src[] = {
-        "pll4_q", "pll3_q", "i2s_ckin", "ck_per"
+        "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
 };
 
 static const char * const sai2_src[] = {
-        "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb"
+        "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb", "pll3_r"
 };
 
 static const char * const adc12_src[] = {
-        "pll4_q", "ck_per"
+        "pll4_r", "ck_per", "pll3_q"
 };
 
 static const char * const dsi_src[] = {
@@ -269,7 +269,7 @@ static const struct clk_div_table axi_div_table[] = {
 static const struct clk_div_table mcu_div_table[] = {
         { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
         { 4, 16 }, { 5, 32 }, { 6, 64 }, { 7, 128 },
-        { 8, 512 }, { 9, 512 }, { 10, 512}, { 11, 512 },
+        { 8, 256 }, { 9, 512 }, { 10, 512}, { 11, 512 },
         { 12, 512 }, { 13, 512 }, { 14, 512}, { 15, 512 },
         { 0 },
 };
@@ -1286,10 +1286,11 @@ _clk_stm32_register_composite(struct device *dev,
         MGATE_MP1(_id, _name, _parent, _flags, _mgate)
 
 #define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\
-             COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE | _flags,\
-                  _MGATE_MP1(_mgate),\
-                  _MMUX(_mmux),\
-                  _NO_DIV)
+             COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\
+                       CLK_SET_RATE_NO_REPARENT | _flags,\
+                       _MGATE_MP1(_mgate),\
+                       _MMUX(_mmux),\
+                       _NO_DIV)
 
 enum {
         G_SAI1,
@@ -1655,12 +1656,14 @@ static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
 
 static const struct clock_config stm32mp1_clock_cfg[] = {
         /* Oscillator divider */
-        DIV(NO_ID, "clk-hsi-div", "clk-hsi", 0, RCC_HSICFGR, 0, 2,
-            CLK_DIVIDER_READ_ONLY),
+        DIV(NO_ID, "clk-hsi-div", "clk-hsi", CLK_DIVIDER_POWER_OF_TWO,
+            RCC_HSICFGR, 0, 2, CLK_DIVIDER_READ_ONLY),
 
         /*  External / Internal Oscillators */
         GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
-        GATE_MP1(CK_CSI, "ck_csi", "clk-csi", 0, RCC_OCENSETR, 4, 0),
+        /* ck_csi is used by IO compensation and should be critical */
+        GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
+                 RCC_OCENSETR, 4, 0),
         GATE_MP1(CK_HSI, "ck_hsi", "clk-hsi-div", 0, RCC_OCENSETR, 0, 0),
         GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
         GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
@@ -1952,14 +1955,14 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
         MGATE_MP1(GPU_K, "gpu_k", "pll2_q", 0, G_GPU),
         MGATE_MP1(DAC12_K, "dac12_k", "ck_lsi", 0, G_DAC12),
 
-        COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE,
+        COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE |
+                  CLK_SET_RATE_NO_REPARENT,
                   _NO_GATE,
                   _MMUX(M_ETHCK),
-                  _DIV(RCC_ETHCKSELR, 4, 4, CLK_DIVIDER_ALLOW_ZERO, NULL)),
+                  _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
 
         /* RTC clock */
-        DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 7,
-            CLK_DIVIDER_ALLOW_ZERO),
+        DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 6, 0),
 
         COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
                    CLK_SET_RATE_PARENT,