1 files changed, 12 insertions, 2 deletions

diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index da44f8dc1d29..294850bdc195 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -282,6 +282,7 @@ static const struct stm32f4_gate_data stm32f746_gates[] __initconst = {
 
         { STM32F4_RCC_APB2ENR,  0,      "tim1",         "apb2_mul" },
         { STM32F4_RCC_APB2ENR,  1,      "tim8",         "apb2_mul" },
+        { STM32F4_RCC_APB2ENR,  7,      "sdmmc2",       "sdmux"    },
         { STM32F4_RCC_APB2ENR,  8,      "adc1",         "apb2_div" },
         { STM32F4_RCC_APB2ENR,  9,      "adc2",         "apb2_div" },
         { STM32F4_RCC_APB2ENR, 10,      "adc3",         "apb2_div" },
@@ -315,7 +316,7 @@ static const u64 stm32f46xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
 
 static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
                                                       0x0000000000000003ull,
-                                                      0x04f77f033e01c9ffull };
+                                                      0x04f77f833e01c9ffull };
 
 static const u64 *stm32f4_gate_map;
 
@@ -521,7 +522,7 @@ static const struct stm32f4_pll_data stm32f429_pll[MAX_PLL_DIV] = {
 };
 
 static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
-        { PLL,     50, { "pll",      "pll-q",    NULL       } },
+        { PLL,     50, { "pll",      "pll-q",    "pll-r"    } },
         { PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
         { PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
 };
@@ -1047,6 +1048,8 @@ static const char *rtc_parents[4] = {
         "no-clock", "lse", "lsi", "hse-rtc"
 };
 
+static const char *dsi_parent[2] = { NULL, "pll-r" };
+
 static const char *lcd_parent[1] = { "pllsai-r-div" };
 
 static const char *i2s_parents[2] = { "plli2s-r", NULL };
@@ -1156,6 +1159,12 @@ static const struct stm32_aux_clk stm32f469_aux_clk[] = {
                 NO_GATE, 0,
                 0
         },
+        {
+                CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),
+                STM32F4_RCC_DCKCFGR, 29, 1,
+                STM32F4_RCC_APB2ENR, 27,
+                CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
+        },
 };
 
 static const struct stm32_aux_clk stm32f746_aux_clk[] = {
@@ -1450,6 +1459,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
         stm32f4_gate_map = data->gates_map;
 
         hse_clk = of_clk_get_parent_name(np, 0);
+        dsi_parent[0] = hse_clk;
 
         i2s_in_clk = of_clk_get_parent_name(np, 1);