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Diffstat (limited to 'arch/x86/platform/intel-mid/intel-mid.c')
-rw-r--r--arch/x86/platform/intel-mid/intel-mid.c8
1 files changed, 3 insertions, 5 deletions
diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c
index 1bbc21e2e4ae..90bb997ed0a2 100644
--- a/arch/x86/platform/intel-mid/intel-mid.c
+++ b/arch/x86/platform/intel-mid/intel-mid.c
@@ -138,7 +138,7 @@ static void intel_mid_arch_setup(void)
138 intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip](); 138 intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip]();
139 else { 139 else {
140 intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL](); 140 intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL]();
141 pr_info("ARCH: Unknown SoC, assuming PENWELL!\n"); 141 pr_info("ARCH: Unknown SoC, assuming Penwell!\n");
142 } 142 }
143 143
144out: 144out:
@@ -214,12 +214,10 @@ static inline int __init setup_x86_intel_mid_timer(char *arg)
214 else if (strcmp("lapic_and_apbt", arg) == 0) 214 else if (strcmp("lapic_and_apbt", arg) == 0)
215 intel_mid_timer_options = INTEL_MID_TIMER_LAPIC_APBT; 215 intel_mid_timer_options = INTEL_MID_TIMER_LAPIC_APBT;
216 else { 216 else {
217 pr_warn("X86 INTEL_MID timer option %s not recognised" 217 pr_warn("X86 INTEL_MID timer option %s not recognised use x86_intel_mid_timer=apbt_only or lapic_and_apbt\n",
218 " use x86_intel_mid_timer=apbt_only or lapic_and_apbt\n", 218 arg);
219 arg);
220 return -EINVAL; 219 return -EINVAL;
221 } 220 }
222 return 0; 221 return 0;
223} 222}
224__setup("x86_intel_mid_timer=", setup_x86_intel_mid_timer); 223__setup("x86_intel_mid_timer=", setup_x86_intel_mid_timer);
225