1 files changed, 65 insertions, 5 deletions

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index ef29ad001991..d63f4b5706e4 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -47,6 +47,8 @@
 #include <asm/pat.h>
 #include <asm/microcode.h>
 #include <asm/microcode_intel.h>
+#include <asm/intel-family.h>
+#include <asm/cpu_device_id.h>
 
 #ifdef CONFIG_X86_LOCAL_APIC
 #include <asm/uv/uv.h>
@@ -748,6 +750,26 @@ static void apply_forced_caps(struct cpuinfo_x86 *c)
         }
 }
 
+static void init_speculation_control(struct cpuinfo_x86 *c)
+{
+        /*
+         * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
+         * and they also have a different bit for STIBP support. Also,
+         * a hypervisor might have set the individual AMD bits even on
+         * Intel CPUs, for finer-grained selection of what's available.
+         *
+         * We use the AMD bits in 0x8000_0008 EBX as the generic hardware
+         * features, which are visible in /proc/cpuinfo and used by the
+         * kernel. So set those accordingly from the Intel bits.
+         */
+        if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
+                set_cpu_cap(c, X86_FEATURE_IBRS);
+                set_cpu_cap(c, X86_FEATURE_IBPB);
+        }
+        if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
+                set_cpu_cap(c, X86_FEATURE_STIBP);
+}
+
 void get_cpu_cap(struct cpuinfo_x86 *c)
 {
         u32 eax, ebx, ecx, edx;
@@ -769,6 +791,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
                 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
                 c->x86_capability[CPUID_7_0_EBX] = ebx;
                 c->x86_capability[CPUID_7_ECX] = ecx;
+                c->x86_capability[CPUID_7_EDX] = edx;
         }
 
         /* Extended state features: level 0x0000000d */
@@ -841,6 +864,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
                 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
 
         init_scattered_cpuid_features(c);
+        init_speculation_control(c);
 
         /*
          * Clear/Set all flags overridden by options, after probe.
@@ -876,6 +900,41 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
 #endif
 }
 
+static const __initconst struct x86_cpu_id cpu_no_speculation[] = {
+        { X86_VENDOR_INTEL,     6, INTEL_FAM6_ATOM_CEDARVIEW,   X86_FEATURE_ANY },
+        { X86_VENDOR_INTEL,     6, INTEL_FAM6_ATOM_CLOVERVIEW,  X86_FEATURE_ANY },
+        { X86_VENDOR_INTEL,     6, INTEL_FAM6_ATOM_LINCROFT,    X86_FEATURE_ANY },
+        { X86_VENDOR_INTEL,     6, INTEL_FAM6_ATOM_PENWELL,     X86_FEATURE_ANY },
+        { X86_VENDOR_INTEL,     6, INTEL_FAM6_ATOM_PINEVIEW,    X86_FEATURE_ANY },
+        { X86_VENDOR_CENTAUR,   5 },
+        { X86_VENDOR_INTEL,     5 },
+        { X86_VENDOR_NSC,       5 },
+        { X86_VENDOR_ANY,       4 },
+        {}
+};
+
+static const __initconst struct x86_cpu_id cpu_no_meltdown[] = {
+        { X86_VENDOR_AMD },
+        {}
+};
+
+static bool __init cpu_vulnerable_to_meltdown(struct cpuinfo_x86 *c)
+{
+        u64 ia32_cap = 0;
+
+        if (x86_match_cpu(cpu_no_meltdown))
+                return false;
+
+        if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES))
+                rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
+
+        /* Rogue Data Cache Load? No! */
+        if (ia32_cap & ARCH_CAP_RDCL_NO)
+                return false;
+
+        return true;
+}
+
 /*
  * Do minimum CPU detection early.
  * Fields really needed: vendor, cpuid_level, family, model, mask,
@@ -923,11 +982,12 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
 
         setup_force_cpu_cap(X86_FEATURE_ALWAYS);
 
-        if (c->x86_vendor != X86_VENDOR_AMD)
-                setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
-
-        setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
-        setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
+        if (!x86_match_cpu(cpu_no_speculation)) {
+                if (cpu_vulnerable_to_meltdown(c))
+                        setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
+                setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
+                setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
+        }
 
         fpu__init_system(c);