diff options
Diffstat (limited to 'arch/sparc/mm/ultra.S')
| -rw-r--r-- | arch/sparc/mm/ultra.S | 119 |
1 files changed, 95 insertions, 24 deletions
diff --git a/arch/sparc/mm/ultra.S b/arch/sparc/mm/ultra.S index f8e13d421fcb..432aa0cb1b38 100644 --- a/arch/sparc/mm/ultra.S +++ b/arch/sparc/mm/ultra.S | |||
| @@ -53,6 +53,33 @@ __flush_tlb_mm: /* 18 insns */ | |||
| 53 | nop | 53 | nop |
| 54 | 54 | ||
| 55 | .align 32 | 55 | .align 32 |
| 56 | .globl __flush_tlb_page | ||
| 57 | __flush_tlb_page: /* 22 insns */ | ||
| 58 | /* %o0 = context, %o1 = vaddr */ | ||
| 59 | rdpr %pstate, %g7 | ||
| 60 | andn %g7, PSTATE_IE, %g2 | ||
| 61 | wrpr %g2, %pstate | ||
| 62 | mov SECONDARY_CONTEXT, %o4 | ||
| 63 | ldxa [%o4] ASI_DMMU, %g2 | ||
| 64 | stxa %o0, [%o4] ASI_DMMU | ||
| 65 | andcc %o1, 1, %g0 | ||
| 66 | andn %o1, 1, %o3 | ||
| 67 | be,pn %icc, 1f | ||
| 68 | or %o3, 0x10, %o3 | ||
| 69 | stxa %g0, [%o3] ASI_IMMU_DEMAP | ||
| 70 | 1: stxa %g0, [%o3] ASI_DMMU_DEMAP | ||
| 71 | membar #Sync | ||
| 72 | stxa %g2, [%o4] ASI_DMMU | ||
| 73 | sethi %hi(KERNBASE), %o4 | ||
| 74 | flush %o4 | ||
| 75 | retl | ||
| 76 | wrpr %g7, 0x0, %pstate | ||
| 77 | nop | ||
| 78 | nop | ||
| 79 | nop | ||
| 80 | nop | ||
| 81 | |||
| 82 | .align 32 | ||
| 56 | .globl __flush_tlb_pending | 83 | .globl __flush_tlb_pending |
| 57 | __flush_tlb_pending: /* 26 insns */ | 84 | __flush_tlb_pending: /* 26 insns */ |
| 58 | /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */ | 85 | /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */ |
| @@ -203,6 +230,31 @@ __cheetah_flush_tlb_mm: /* 19 insns */ | |||
| 203 | retl | 230 | retl |
| 204 | wrpr %g7, 0x0, %pstate | 231 | wrpr %g7, 0x0, %pstate |
| 205 | 232 | ||
| 233 | __cheetah_flush_tlb_page: /* 22 insns */ | ||
| 234 | /* %o0 = context, %o1 = vaddr */ | ||
| 235 | rdpr %pstate, %g7 | ||
| 236 | andn %g7, PSTATE_IE, %g2 | ||
| 237 | wrpr %g2, 0x0, %pstate | ||
| 238 | wrpr %g0, 1, %tl | ||
| 239 | mov PRIMARY_CONTEXT, %o4 | ||
| 240 | ldxa [%o4] ASI_DMMU, %g2 | ||
| 241 | srlx %g2, CTX_PGSZ1_NUC_SHIFT, %o3 | ||
| 242 | sllx %o3, CTX_PGSZ1_NUC_SHIFT, %o3 | ||
| 243 | or %o0, %o3, %o0 /* Preserve nucleus page size fields */ | ||
| 244 | stxa %o0, [%o4] ASI_DMMU | ||
| 245 | andcc %o1, 1, %g0 | ||
| 246 | be,pn %icc, 1f | ||
| 247 | andn %o1, 1, %o3 | ||
| 248 | stxa %g0, [%o3] ASI_IMMU_DEMAP | ||
| 249 | 1: stxa %g0, [%o3] ASI_DMMU_DEMAP | ||
| 250 | membar #Sync | ||
| 251 | stxa %g2, [%o4] ASI_DMMU | ||
| 252 | sethi %hi(KERNBASE), %o4 | ||
| 253 | flush %o4 | ||
| 254 | wrpr %g0, 0, %tl | ||
| 255 | retl | ||
| 256 | wrpr %g7, 0x0, %pstate | ||
| 257 | |||
| 206 | __cheetah_flush_tlb_pending: /* 27 insns */ | 258 | __cheetah_flush_tlb_pending: /* 27 insns */ |
| 207 | /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */ | 259 | /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */ |
| 208 | rdpr %pstate, %g7 | 260 | rdpr %pstate, %g7 |
| @@ -269,6 +321,20 @@ __hypervisor_flush_tlb_mm: /* 10 insns */ | |||
| 269 | retl | 321 | retl |
| 270 | nop | 322 | nop |
| 271 | 323 | ||
| 324 | __hypervisor_flush_tlb_page: /* 11 insns */ | ||
| 325 | /* %o0 = context, %o1 = vaddr */ | ||
| 326 | mov %o0, %g2 | ||
| 327 | mov %o1, %o0 /* ARG0: vaddr + IMMU-bit */ | ||
| 328 | mov %g2, %o1 /* ARG1: mmu context */ | ||
| 329 | mov HV_MMU_ALL, %o2 /* ARG2: flags */ | ||
| 330 | srlx %o0, PAGE_SHIFT, %o0 | ||
| 331 | sllx %o0, PAGE_SHIFT, %o0 | ||
| 332 | ta HV_MMU_UNMAP_ADDR_TRAP | ||
| 333 | brnz,pn %o0, __hypervisor_tlb_tl0_error | ||
| 334 | mov HV_MMU_UNMAP_ADDR_TRAP, %o1 | ||
| 335 | retl | ||
| 336 | nop | ||
| 337 | |||
| 272 | __hypervisor_flush_tlb_pending: /* 16 insns */ | 338 | __hypervisor_flush_tlb_pending: /* 16 insns */ |
| 273 | /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */ | 339 | /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */ |
| 274 | sllx %o1, 3, %g1 | 340 | sllx %o1, 3, %g1 |
| @@ -339,6 +405,13 @@ cheetah_patch_cachetlbops: | |||
| 339 | call tlb_patch_one | 405 | call tlb_patch_one |
| 340 | mov 19, %o2 | 406 | mov 19, %o2 |
| 341 | 407 | ||
| 408 | sethi %hi(__flush_tlb_page), %o0 | ||
| 409 | or %o0, %lo(__flush_tlb_page), %o0 | ||
| 410 | sethi %hi(__cheetah_flush_tlb_page), %o1 | ||
| 411 | or %o1, %lo(__cheetah_flush_tlb_page), %o1 | ||
| 412 | call tlb_patch_one | ||
| 413 | mov 22, %o2 | ||
| 414 | |||
| 342 | sethi %hi(__flush_tlb_pending), %o0 | 415 | sethi %hi(__flush_tlb_pending), %o0 |
| 343 | or %o0, %lo(__flush_tlb_pending), %o0 | 416 | or %o0, %lo(__flush_tlb_pending), %o0 |
| 344 | sethi %hi(__cheetah_flush_tlb_pending), %o1 | 417 | sethi %hi(__cheetah_flush_tlb_pending), %o1 |
| @@ -397,10 +470,9 @@ xcall_flush_tlb_mm: /* 21 insns */ | |||
| 397 | nop | 470 | nop |
| 398 | nop | 471 | nop |
| 399 | 472 | ||
| 400 | .globl xcall_flush_tlb_pending | 473 | .globl xcall_flush_tlb_page |
| 401 | xcall_flush_tlb_pending: /* 21 insns */ | 474 | xcall_flush_tlb_page: /* 17 insns */ |
| 402 | /* %g5=context, %g1=nr, %g7=vaddrs[] */ | 475 | /* %g5=context, %g1=vaddr */ |
| 403 | sllx %g1, 3, %g1 | ||
| 404 | mov PRIMARY_CONTEXT, %g4 | 476 | mov PRIMARY_CONTEXT, %g4 |
| 405 | ldxa [%g4] ASI_DMMU, %g2 | 477 | ldxa [%g4] ASI_DMMU, %g2 |
| 406 | srlx %g2, CTX_PGSZ1_NUC_SHIFT, %g4 | 478 | srlx %g2, CTX_PGSZ1_NUC_SHIFT, %g4 |
| @@ -408,20 +480,16 @@ xcall_flush_tlb_pending: /* 21 insns */ | |||
| 408 | or %g5, %g4, %g5 | 480 | or %g5, %g4, %g5 |
| 409 | mov PRIMARY_CONTEXT, %g4 | 481 | mov PRIMARY_CONTEXT, %g4 |
| 410 | stxa %g5, [%g4] ASI_DMMU | 482 | stxa %g5, [%g4] ASI_DMMU |
| 411 | 1: sub %g1, (1 << 3), %g1 | 483 | andcc %g1, 0x1, %g0 |
| 412 | ldx [%g7 + %g1], %g5 | ||
| 413 | andcc %g5, 0x1, %g0 | ||
| 414 | be,pn %icc, 2f | 484 | be,pn %icc, 2f |
| 415 | 485 | andn %g1, 0x1, %g5 | |
| 416 | andn %g5, 0x1, %g5 | ||
| 417 | stxa %g0, [%g5] ASI_IMMU_DEMAP | 486 | stxa %g0, [%g5] ASI_IMMU_DEMAP |
| 418 | 2: stxa %g0, [%g5] ASI_DMMU_DEMAP | 487 | 2: stxa %g0, [%g5] ASI_DMMU_DEMAP |
| 419 | membar #Sync | 488 | membar #Sync |
| 420 | brnz,pt %g1, 1b | ||
| 421 | nop | ||
| 422 | stxa %g2, [%g4] ASI_DMMU | 489 | stxa %g2, [%g4] ASI_DMMU |
| 423 | retry | 490 | retry |
| 424 | nop | 491 | nop |
| 492 | nop | ||
| 425 | 493 | ||
| 426 | .globl xcall_flush_tlb_kernel_range | 494 | .globl xcall_flush_tlb_kernel_range |
| 427 | xcall_flush_tlb_kernel_range: /* 25 insns */ | 495 | xcall_flush_tlb_kernel_range: /* 25 insns */ |
| @@ -656,15 +724,13 @@ __hypervisor_xcall_flush_tlb_mm: /* 21 insns */ | |||
| 656 | membar #Sync | 724 | membar #Sync |
| 657 | retry | 725 | retry |
| 658 | 726 | ||
| 659 | .globl __hypervisor_xcall_flush_tlb_pending | 727 | .globl __hypervisor_xcall_flush_tlb_page |
| 660 | __hypervisor_xcall_flush_tlb_pending: /* 21 insns */ | 728 | __hypervisor_xcall_flush_tlb_page: /* 17 insns */ |
| 661 | /* %g5=ctx, %g1=nr, %g7=vaddrs[], %g2,%g3,%g4,g6=scratch */ | 729 | /* %g5=ctx, %g1=vaddr */ |
| 662 | sllx %g1, 3, %g1 | ||
| 663 | mov %o0, %g2 | 730 | mov %o0, %g2 |
| 664 | mov %o1, %g3 | 731 | mov %o1, %g3 |
| 665 | mov %o2, %g4 | 732 | mov %o2, %g4 |
| 666 | 1: sub %g1, (1 << 3), %g1 | 733 | mov %g1, %o0 /* ARG0: virtual address */ |
| 667 | ldx [%g7 + %g1], %o0 /* ARG0: virtual address */ | ||
| 668 | mov %g5, %o1 /* ARG1: mmu context */ | 734 | mov %g5, %o1 /* ARG1: mmu context */ |
| 669 | mov HV_MMU_ALL, %o2 /* ARG2: flags */ | 735 | mov HV_MMU_ALL, %o2 /* ARG2: flags */ |
| 670 | srlx %o0, PAGE_SHIFT, %o0 | 736 | srlx %o0, PAGE_SHIFT, %o0 |
| @@ -673,8 +739,6 @@ __hypervisor_xcall_flush_tlb_pending: /* 21 insns */ | |||
| 673 | mov HV_MMU_UNMAP_ADDR_TRAP, %g6 | 739 | mov HV_MMU_UNMAP_ADDR_TRAP, %g6 |
| 674 | brnz,a,pn %o0, __hypervisor_tlb_xcall_error | 740 | brnz,a,pn %o0, __hypervisor_tlb_xcall_error |
| 675 | mov %o0, %g5 | 741 | mov %o0, %g5 |
| 676 | brnz,pt %g1, 1b | ||
| 677 | nop | ||
| 678 | mov %g2, %o0 | 742 | mov %g2, %o0 |
| 679 | mov %g3, %o1 | 743 | mov %g3, %o1 |
| 680 | mov %g4, %o2 | 744 | mov %g4, %o2 |
| @@ -757,6 +821,13 @@ hypervisor_patch_cachetlbops: | |||
| 757 | call tlb_patch_one | 821 | call tlb_patch_one |
| 758 | mov 10, %o2 | 822 | mov 10, %o2 |
| 759 | 823 | ||
| 824 | sethi %hi(__flush_tlb_page), %o0 | ||
| 825 | or %o0, %lo(__flush_tlb_page), %o0 | ||
| 826 | sethi %hi(__hypervisor_flush_tlb_page), %o1 | ||
| 827 | or %o1, %lo(__hypervisor_flush_tlb_page), %o1 | ||
| 828 | call tlb_patch_one | ||
| 829 | mov 11, %o2 | ||
| 830 | |||
| 760 | sethi %hi(__flush_tlb_pending), %o0 | 831 | sethi %hi(__flush_tlb_pending), %o0 |
| 761 | or %o0, %lo(__flush_tlb_pending), %o0 | 832 | or %o0, %lo(__flush_tlb_pending), %o0 |
| 762 | sethi %hi(__hypervisor_flush_tlb_pending), %o1 | 833 | sethi %hi(__hypervisor_flush_tlb_pending), %o1 |
| @@ -788,12 +859,12 @@ hypervisor_patch_cachetlbops: | |||
| 788 | call tlb_patch_one | 859 | call tlb_patch_one |
| 789 | mov 21, %o2 | 860 | mov 21, %o2 |
| 790 | 861 | ||
| 791 | sethi %hi(xcall_flush_tlb_pending), %o0 | 862 | sethi %hi(xcall_flush_tlb_page), %o0 |
| 792 | or %o0, %lo(xcall_flush_tlb_pending), %o0 | 863 | or %o0, %lo(xcall_flush_tlb_page), %o0 |
| 793 | sethi %hi(__hypervisor_xcall_flush_tlb_pending), %o1 | 864 | sethi %hi(__hypervisor_xcall_flush_tlb_page), %o1 |
| 794 | or %o1, %lo(__hypervisor_xcall_flush_tlb_pending), %o1 | 865 | or %o1, %lo(__hypervisor_xcall_flush_tlb_page), %o1 |
| 795 | call tlb_patch_one | 866 | call tlb_patch_one |
| 796 | mov 21, %o2 | 867 | mov 17, %o2 |
| 797 | 868 | ||
| 798 | sethi %hi(xcall_flush_tlb_kernel_range), %o0 | 869 | sethi %hi(xcall_flush_tlb_kernel_range), %o0 |
| 799 | or %o0, %lo(xcall_flush_tlb_kernel_range), %o0 | 870 | or %o0, %lo(xcall_flush_tlb_kernel_range), %o0 |
