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-rw-r--r--arch/powerpc/mm/tlb_nohash_low.S15
1 files changed, 4 insertions, 11 deletions
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index fab919fd1384..626ad081639f 100644
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -191,12 +191,6 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
191#ifdef CONFIG_PPC_47x 191#ifdef CONFIG_PPC_47x
192 192
193/* 193/*
194 * 47x variant of icbt
195 */
196# define ICBT(CT,RA,RB) \
197 .long 0x7c00002c | ((CT) << 21) | ((RA) << 16) | ((RB) << 11)
198
199/*
200 * _tlbivax_bcast is only on 47x. We don't bother doing a runtime 194 * _tlbivax_bcast is only on 47x. We don't bother doing a runtime
201 * check though, it will blow up soon enough if we mistakenly try 195 * check though, it will blow up soon enough if we mistakenly try
202 * to use it on a 440. 196 * to use it on a 440.
@@ -208,8 +202,7 @@ _GLOBAL(_tlbivax_bcast)
208 wrteei 0 202 wrteei 0
209 mtspr SPRN_MMUCR,r5 203 mtspr SPRN_MMUCR,r5
210 isync 204 isync
211/* tlbivax 0,r3 - use .long to avoid binutils deps */ 205 PPC_TLBIVAX(0, R3)
212 .long 0x7c000624 | (r3 << 11)
213 isync 206 isync
214 eieio 207 eieio
215 tlbsync 208 tlbsync
@@ -227,11 +220,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_476_DD2)
227 bl 2f 220 bl 2f
2282: mflr r6 2212: mflr r6
229 li r7,32 222 li r7,32
230 ICBT(0,r6,r7) /* touch next cache line */ 223 PPC_ICBT(0,R6,R7) /* touch next cache line */
231 add r6,r6,r7 224 add r6,r6,r7
232 ICBT(0,r6,r7) /* touch next cache line */ 225 PPC_ICBT(0,R6,R7) /* touch next cache line */
233 add r6,r6,r7 226 add r6,r6,r7
234 ICBT(0,r6,r7) /* touch next cache line */ 227 PPC_ICBT(0,R6,R7) /* touch next cache line */
235 sync 228 sync
236 nop 229 nop
237 nop 230 nop