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-rw-r--r--arch/powerpc/include/asm/code-patching.h11
-rw-r--r--arch/powerpc/include/asm/mmu.h10
-rw-r--r--arch/powerpc/include/asm/opal.h29
-rw-r--r--arch/powerpc/include/asm/perf_event_server.h3
-rw-r--r--arch/powerpc/include/asm/swab.h43
5 files changed, 13 insertions, 83 deletions
diff --git a/arch/powerpc/include/asm/code-patching.h b/arch/powerpc/include/asm/code-patching.h
index 37991e154ef8..840a5509b3f1 100644
--- a/arch/powerpc/include/asm/code-patching.h
+++ b/arch/powerpc/include/asm/code-patching.h
@@ -88,4 +88,15 @@ static inline unsigned long ppc_function_entry(void *func)
88#endif 88#endif
89} 89}
90 90
91static inline unsigned long ppc_global_function_entry(void *func)
92{
93#if defined(CONFIG_PPC64) && defined(_CALL_ELF) && _CALL_ELF == 2
94 /* PPC64 ABIv2 the global entry point is at the address */
95 return (unsigned long)func;
96#else
97 /* All other cases there is no change vs ppc_function_entry() */
98 return ppc_function_entry(func);
99#endif
100}
101
91#endif /* _ASM_POWERPC_CODE_PATCHING_H */ 102#endif /* _ASM_POWERPC_CODE_PATCHING_H */
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index f8d1d6dcf7db..e61f24ed4e65 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -19,8 +19,7 @@
19#define MMU_FTR_TYPE_40x ASM_CONST(0x00000004) 19#define MMU_FTR_TYPE_40x ASM_CONST(0x00000004)
20#define MMU_FTR_TYPE_44x ASM_CONST(0x00000008) 20#define MMU_FTR_TYPE_44x ASM_CONST(0x00000008)
21#define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010) 21#define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
22#define MMU_FTR_TYPE_3E ASM_CONST(0x00000020) 22#define MMU_FTR_TYPE_47x ASM_CONST(0x00000020)
23#define MMU_FTR_TYPE_47x ASM_CONST(0x00000040)
24 23
25/* 24/*
26 * This is individual features 25 * This is individual features
@@ -106,13 +105,6 @@
106 MMU_FTR_CI_LARGE_PAGE 105 MMU_FTR_CI_LARGE_PAGE
107#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ 106#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
108 MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B 107 MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
109#define MMU_FTRS_A2 MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX | \
110 MMU_FTR_USE_TLBIVAX_BCAST | \
111 MMU_FTR_LOCK_BCAST_INVAL | \
112 MMU_FTR_USE_TLBRSRV | \
113 MMU_FTR_USE_PAIRED_MAS | \
114 MMU_FTR_TLBIEL | \
115 MMU_FTR_16M_PAGE
116#ifndef __ASSEMBLY__ 108#ifndef __ASSEMBLY__
117#include <asm/cputable.h> 109#include <asm/cputable.h>
118 110
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 460018889ba9..0da1dbd42e02 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -12,27 +12,7 @@
12#ifndef __OPAL_H 12#ifndef __OPAL_H
13#define __OPAL_H 13#define __OPAL_H
14 14
15/****** Takeover interface ********/
16
17/* PAPR H-Call used to querty the HAL existence and/or instanciate
18 * it from within pHyp (tech preview only).
19 *
20 * This is exclusively used in prom_init.c
21 */
22
23#ifndef __ASSEMBLY__ 15#ifndef __ASSEMBLY__
24
25struct opal_takeover_args {
26 u64 k_image; /* r4 */
27 u64 k_size; /* r5 */
28 u64 k_entry; /* r6 */
29 u64 k_entry2; /* r7 */
30 u64 hal_addr; /* r8 */
31 u64 rd_image; /* r9 */
32 u64 rd_size; /* r10 */
33 u64 rd_loc; /* r11 */
34};
35
36/* 16/*
37 * SG entry 17 * SG entry
38 * 18 *
@@ -55,15 +35,6 @@ struct opal_sg_list {
55/* We calculate number of sg entries based on PAGE_SIZE */ 35/* We calculate number of sg entries based on PAGE_SIZE */
56#define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry)) 36#define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
57 37
58extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
59
60extern long opal_do_takeover(struct opal_takeover_args *args);
61
62struct rtas_args;
63extern int opal_enter_rtas(struct rtas_args *args,
64 unsigned long data,
65 unsigned long entry);
66
67#endif /* __ASSEMBLY__ */ 38#endif /* __ASSEMBLY__ */
68 39
69/****** OPAL APIs ******/ 40/****** OPAL APIs ******/
diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h
index 9ed737146dbb..b3e936027b26 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -61,8 +61,7 @@ struct power_pmu {
61#define PPMU_SIAR_VALID 0x00000010 /* Processor has SIAR Valid bit */ 61#define PPMU_SIAR_VALID 0x00000010 /* Processor has SIAR Valid bit */
62#define PPMU_HAS_SSLOT 0x00000020 /* Has sampled slot in MMCRA */ 62#define PPMU_HAS_SSLOT 0x00000020 /* Has sampled slot in MMCRA */
63#define PPMU_HAS_SIER 0x00000040 /* Has SIER */ 63#define PPMU_HAS_SIER 0x00000040 /* Has SIER */
64#define PPMU_BHRB 0x00000080 /* has BHRB feature enabled */ 64#define PPMU_ARCH_207S 0x00000080 /* PMC is architecture v2.07S */
65#define PPMU_EBB 0x00000100 /* supports event based branch */
66 65
67/* 66/*
68 * Values for flags to get_alternatives() 67 * Values for flags to get_alternatives()
diff --git a/arch/powerpc/include/asm/swab.h b/arch/powerpc/include/asm/swab.h
index b9bd1ca944d0..96f59de61855 100644
--- a/arch/powerpc/include/asm/swab.h
+++ b/arch/powerpc/include/asm/swab.h
@@ -9,10 +9,6 @@
9 9
10#include <uapi/asm/swab.h> 10#include <uapi/asm/swab.h>
11 11
12#ifdef __GNUC__
13#ifndef __powerpc64__
14#endif /* __powerpc64__ */
15
16static __inline__ __u16 ld_le16(const volatile __u16 *addr) 12static __inline__ __u16 ld_le16(const volatile __u16 *addr)
17{ 13{
18 __u16 val; 14 __u16 val;
@@ -20,19 +16,12 @@ static __inline__ __u16 ld_le16(const volatile __u16 *addr)
20 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr)); 16 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
21 return val; 17 return val;
22} 18}
23#define __arch_swab16p ld_le16
24 19
25static __inline__ void st_le16(volatile __u16 *addr, const __u16 val) 20static __inline__ void st_le16(volatile __u16 *addr, const __u16 val)
26{ 21{
27 __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); 22 __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
28} 23}
29 24
30static inline void __arch_swab16s(__u16 *addr)
31{
32 st_le16(addr, *addr);
33}
34#define __arch_swab16s __arch_swab16s
35
36static __inline__ __u32 ld_le32(const volatile __u32 *addr) 25static __inline__ __u32 ld_le32(const volatile __u32 *addr)
37{ 26{
38 __u32 val; 27 __u32 val;
@@ -40,42 +29,10 @@ static __inline__ __u32 ld_le32(const volatile __u32 *addr)
40 __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr)); 29 __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
41 return val; 30 return val;
42} 31}
43#define __arch_swab32p ld_le32
44 32
45static __inline__ void st_le32(volatile __u32 *addr, const __u32 val) 33static __inline__ void st_le32(volatile __u32 *addr, const __u32 val)
46{ 34{
47 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); 35 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
48} 36}
49 37
50static inline void __arch_swab32s(__u32 *addr)
51{
52 st_le32(addr, *addr);
53}
54#define __arch_swab32s __arch_swab32s
55
56static inline __attribute_const__ __u16 __arch_swab16(__u16 value)
57{
58 __u16 result;
59
60 __asm__("rlwimi %0,%1,8,16,23"
61 : "=r" (result)
62 : "r" (value), "0" (value >> 8));
63 return result;
64}
65#define __arch_swab16 __arch_swab16
66
67static inline __attribute_const__ __u32 __arch_swab32(__u32 value)
68{
69 __u32 result;
70
71 __asm__("rlwimi %0,%1,24,16,23\n\t"
72 "rlwimi %0,%1,8,8,15\n\t"
73 "rlwimi %0,%1,24,0,7"
74 : "=r" (result)
75 : "r" (value), "0" (value >> 24));
76 return result;
77}
78#define __arch_swab32 __arch_swab32
79
80#endif /* __GNUC__ */
81#endif /* _ASM_POWERPC_SWAB_H */ 38#endif /* _ASM_POWERPC_SWAB_H */