8 files changed, 16 insertions, 151 deletions

diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 576397c69920..fcd4060f6421 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -92,6 +92,7 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 #include <asm/scatterlist.h>
 #include <linux/string.h>
 #include <asm/io.h>
+#include <asm-generic/pci-bridge.h>
 
 struct pci_dev;
 
@@ -112,12 +113,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 }
 #endif
 
-extern void pcibios_resource_to_bus(struct pci_dev *dev,
-        struct pci_bus_region *region, struct resource *res);
-
-extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                                    struct pci_bus_region *region);
-
 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
 
 static inline int pci_proc_domain(struct pci_bus *bus)
@@ -145,8 +140,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 #define arch_setup_msi_irqs arch_setup_msi_irqs
 #endif
 
-extern int pci_probe_only;
-
 extern char * (*pcibios_plat_setup)(char *str);
 
 #endif /* _ASM_PCI_H */
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index acacd1407c63..9553b14002dd 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -51,67 +51,6 @@ static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
          qube_raq_galileo_early_fixup);
 
-static void __devinit cobalt_legacy_ide_resource_fixup(struct pci_dev *dev,
-                                                       struct resource *res)
-{
-        struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
-        unsigned long offset = hose->io_offset;
-        struct resource orig = *res;
-
-        if (!(res->flags & IORESOURCE_IO) ||
-            !(res->flags & IORESOURCE_PCI_FIXED))
-                return;
-
-        res->start -= offset;
-        res->end -= offset;
-        dev_printk(KERN_DEBUG, &dev->dev, "converted legacy %pR to bus %pR\n",
-                   &orig, res);
-}
-
-static void __devinit cobalt_legacy_ide_fixup(struct pci_dev *dev)
-{
-        u32 class;
-        u8 progif;
-
-        /*
-         * If the IDE controller is in legacy mode, pci_setup_device() fills in
-         * the resources with the legacy addresses that normally appear on the
-         * PCI bus, just as if we had read them from a BAR.
-         *
-         * However, with the GT-64111, those legacy addresses, e.g., 0x1f0,
-         * will never appear on the PCI bus because it converts memory accesses
-         * in the PCI I/O region (which is never at address zero) into I/O port
-         * accesses with no address translation.
-         *
-         * For example, if GT_DEF_PCI0_IO_BASE is 0x10000000, a load or store
-         * to physical address 0x100001f0 will become a PCI access to I/O port
-         * 0x100001f0.  There's no way to generate an access to I/O port 0x1f0,
-         * but the VT82C586 IDE controller does respond at 0x100001f0 because
-         * it only decodes the low 24 bits of the address.
-         *
-         * When this quirk runs, the pci_dev resources should contain bus
-         * addresses, not Linux I/O port numbers, so convert legacy addresses
-         * like 0x1f0 to bus addresses like 0x100001f0.  Later, we'll convert
-         * them back with pcibios_fixup_bus() or pcibios_bus_to_resource().
-         */
-        class = dev->class >> 8;
-        if (class != PCI_CLASS_STORAGE_IDE)
-                return;
-
-        pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
-        if ((progif & 1) == 0) {
-                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[0]);
-                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[1]);
-        }
-        if ((progif & 4) == 0) {
-                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[2]);
-                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[3]);
-        }
-}
-
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
-          cobalt_legacy_ide_fixup);
-
 static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
 {
         unsigned short cfgword;
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
index af8c31996965..37b52dc3d27e 100644
--- a/arch/mips/pci/pci-bcm1480.c
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -204,7 +204,7 @@ static int __init bcm1480_pcibios_init(void)
         uint64_t reg;
 
         /* CFE will assign PCI resources */
-        pci_probe_only = 1;
+        pci_set_flags(PCI_PROBE_ONLY);
 
         /* Avoid ISA compat ranges.  */
         PCIBIOS_MIN_IO = 0x00008000UL;
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index 193e9494f98e..0fbe4c0c170a 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -50,7 +50,7 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
         bridge_t *bridge;
         int slot;
 
-        pci_probe_only = 1;
+        pci_set_flags(PCI_PROBE_ONLY);
 
         printk("a bridge\n");
 
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index be1e1afe12c3..030c77e7926e 100644
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -270,7 +270,8 @@ static int __devinit ltq_pci_probe(struct platform_device *pdev)
 {
         struct ltq_pci_data *ltq_pci_data =
                 (struct ltq_pci_data *) pdev->dev.platform_data;
-        pci_probe_only = 0;
+
+        pci_clear_flags(PCI_PROBE_ONLY);
         ltq_pci_irq_map = ltq_pci_data->irq;
         ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE);
         ltq_pci_mapped_cfg =
diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c
index 1711e8e101bc..dd97f3a83baa 100644
--- a/arch/mips/pci/pci-sb1250.c
+++ b/arch/mips/pci/pci-sb1250.c
@@ -213,7 +213,7 @@ static int __init sb1250_pcibios_init(void)
         uint64_t reg;
 
         /* CFE will assign PCI resources */
-        pci_probe_only = 1;
+        pci_set_flags(PCI_PROBE_ONLY);
 
         /* Avoid ISA compat ranges.  */
         PCIBIOS_MIN_IO = 0x00008000UL;
diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c
index 3d701a962ef4..1644805a6730 100644
--- a/arch/mips/pci/pci-xlr.c
+++ b/arch/mips/pci/pci-xlr.c
@@ -292,7 +292,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
 static int __init pcibios_init(void)
 {
         /* PSB assigns PCI resources */
-        pci_probe_only = 1;
+        pci_set_flags(PCI_PROBE_ONLY);
         pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20);
 
         /* Extend IO port for memory mapped io */
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 15521505ebe8..0514866fa925 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -20,16 +20,9 @@
 #include <asm/cpu-info.h>
 
 /*
- * Indicate whether we respect the PCI setup left by the firmware.
- *
- * Make this long-lived  so that we know when shutting down
- * whether we probed only or not.
+ * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
+ * assignments.
  */
-int pci_probe_only;
-
-#define PCI_ASSIGN_ALL_BUSSES   1
-
-unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
 
 /*
  * The PCI controller list.
@@ -92,11 +85,12 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose)
         if (!hose->iommu)
                 PCI_DMA_BUS_IS_PHYS = 1;
 
-        if (hose->get_busno && pci_probe_only)
+        if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
                 next_busno = (*hose->get_busno)();
 
-        pci_add_resource(&resources, hose->mem_resource);
-        pci_add_resource(&resources, hose->io_resource);
+        pci_add_resource_offset(&resources,
+                                hose->mem_resource, hose->mem_offset);
+        pci_add_resource_offset(&resources, hose->io_resource, hose->io_offset);
         bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
                                 &resources);
         if (!bus)
@@ -115,7 +109,7 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose)
                         need_domain_info = 1;
                 }
 
-                if (!pci_probe_only) {
+                if (!pci_has_flag(PCI_PROBE_ONLY)) {
                         pci_bus_size_bridges(bus);
                         pci_bus_assign_resources(bus);
                         pci_enable_bridges(bus);
@@ -241,7 +235,7 @@ static int pcibios_enable_resources(struct pci_dev *dev, int mask)
 
 unsigned int pcibios_assign_all_busses(void)
 {
-        return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
+        return 1;
 }
 
 int pcibios_enable_device(struct pci_dev *dev, int mask)
@@ -254,42 +248,13 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
         return pcibios_plat_dev_init(dev);
 }
 
-static void pcibios_fixup_device_resources(struct pci_dev *dev,
-        struct pci_bus *bus)
-{
-        /* Update device resources.  */
-        struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
-        unsigned long offset = 0;
-        int i;
-
-        for (i = 0; i < PCI_NUM_RESOURCES; i++) {
-                if (!dev->resource[i].start)
-                        continue;
-                if (dev->resource[i].flags & IORESOURCE_IO)
-                        offset = hose->io_offset;
-                else if (dev->resource[i].flags & IORESOURCE_MEM)
-                        offset = hose->mem_offset;
-
-                dev->resource[i].start += offset;
-                dev->resource[i].end += offset;
-        }
-}
-
 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
 {
-        /* Propagate hose info into the subordinate devices.  */
-
         struct pci_dev *dev = bus->self;
 
-        if (pci_probe_only && dev &&
+        if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
             (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
                 pci_read_bridge_bases(bus);
-                pcibios_fixup_device_resources(dev, bus);
-        }
-
-        list_for_each_entry(dev, &bus->devices, bus_list) {
-                if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
-                        pcibios_fixup_device_resources(dev, bus);
         }
 }
 
@@ -299,40 +264,7 @@ pcibios_update_irq(struct pci_dev *dev, int irq)
         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 }
 
-void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                         struct resource *res)
-{
-        struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
-        unsigned long offset = 0;
-
-        if (res->flags & IORESOURCE_IO)
-                offset = hose->io_offset;
-        else if (res->flags & IORESOURCE_MEM)
-                offset = hose->mem_offset;
-
-        region->start = res->start - offset;
-        region->end = res->end - offset;
-}
-
-void __devinit
-pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                        struct pci_bus_region *region)
-{
-        struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
-        unsigned long offset = 0;
-
-        if (res->flags & IORESOURCE_IO)
-                offset = hose->io_offset;
-        else if (res->flags & IORESOURCE_MEM)
-                offset = hose->mem_offset;
-
-        res->start = region->start + offset;
-        res->end = region->end + offset;
-}
-
 #ifdef CONFIG_HOTPLUG
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-EXPORT_SYMBOL(pcibios_bus_to_resource);
 EXPORT_SYMBOL(PCIBIOS_MIN_IO);
 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
 #endif