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-rw-r--r--arch/mips/include/asm/mach-powertv/asic.h120
-rw-r--r--arch/mips/include/asm/mach-powertv/asic_reg_map.h90
-rw-r--r--arch/mips/include/asm/mach-powertv/asic_regs.h125
-rw-r--r--arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h60
-rw-r--r--arch/mips/include/asm/mach-powertv/dma-coherence.h107
-rw-r--r--arch/mips/include/asm/mach-powertv/interrupts.h253
-rw-r--r--arch/mips/include/asm/mach-powertv/ioremap.h167
-rw-r--r--arch/mips/include/asm/mach-powertv/irq.h25
-rw-r--r--arch/mips/include/asm/mach-powertv/powertv-clock.h29
-rw-r--r--arch/mips/include/asm/mach-powertv/war.h27
10 files changed, 0 insertions, 1003 deletions
diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h
deleted file mode 100644
index b341108d12f1..000000000000
--- a/arch/mips/include/asm/mach-powertv/asic.h
+++ /dev/null
@@ -1,120 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_ASIC_H
20#define _ASM_MACH_POWERTV_ASIC_H
21
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24#include <asm/mach-powertv/asic_regs.h>
25
26#define DVR_CAPABLE (1<<0)
27#define PCIE_CAPABLE (1<<1)
28#define FFS_CAPABLE (1<<2)
29#define DISPLAY_CAPABLE (1<<3)
30
31/* Platform Family types
32 * For compitability, the new value must be added in the end */
33enum family_type {
34 FAMILY_8500,
35 FAMILY_8500RNG,
36 FAMILY_4500,
37 FAMILY_1500,
38 FAMILY_8600,
39 FAMILY_4600,
40 FAMILY_4600VZA,
41 FAMILY_8600VZB,
42 FAMILY_1500VZE,
43 FAMILY_1500VZF,
44 FAMILY_8700,
45 FAMILIES
46};
47
48/* Register maps for each ASIC */
49extern const struct register_map calliope_register_map;
50extern const struct register_map cronus_register_map;
51extern const struct register_map gaia_register_map;
52extern const struct register_map zeus_register_map;
53
54extern struct resource dvr_cronus_resources[];
55extern struct resource dvr_gaia_resources[];
56extern struct resource dvr_zeus_resources[];
57extern struct resource non_dvr_calliope_resources[];
58extern struct resource non_dvr_cronus_resources[];
59extern struct resource non_dvr_cronuslite_resources[];
60extern struct resource non_dvr_gaia_resources[];
61extern struct resource non_dvr_vz_calliope_resources[];
62extern struct resource non_dvr_vze_calliope_resources[];
63extern struct resource non_dvr_vzf_calliope_resources[];
64extern struct resource non_dvr_zeus_resources[];
65
66extern void powertv_platform_init(void);
67extern void platform_alloc_bootmem(void);
68extern enum asic_type platform_get_asic(void);
69extern enum family_type platform_get_family(void);
70extern int platform_supports_dvr(void);
71extern int platform_supports_ffs(void);
72extern int platform_supports_pcie(void);
73extern int platform_supports_display(void);
74extern void configure_platform(void);
75
76/* Platform Resources */
77#define ASIC_RESOURCE_GET_EXISTS 1
78extern struct resource *asic_resource_get(const char *name);
79extern void platform_release_memory(void *baddr, int size);
80
81/* USB configuration */
82struct usb_hcd; /* Forward reference */
83extern void platform_configure_usb_ehci(void);
84extern void platform_unconfigure_usb_ehci(void);
85extern void platform_configure_usb_ohci(void);
86extern void platform_unconfigure_usb_ohci(void);
87
88/* Resource for ASIC registers */
89extern struct resource asic_resource;
90extern int platform_usb_devices_init(struct platform_device **echi_dev,
91 struct platform_device **ohci_dev);
92
93/* Reboot Cause */
94extern void set_reboot_cause(char code, unsigned int data, unsigned int data2);
95extern void set_locked_reboot_cause(char code, unsigned int data,
96 unsigned int data2);
97
98enum sys_reboot_type {
99 sys_unknown_reboot = 0x00, /* Unknown reboot cause */
100 sys_davic_change = 0x01, /* Reboot due to change in DAVIC
101 * mode */
102 sys_user_reboot = 0x02, /* Reboot initiated by user */
103 sys_system_reboot = 0x03, /* Reboot initiated by OS */
104 sys_trap_reboot = 0x04, /* Reboot due to a CPU trap */
105 sys_silent_reboot = 0x05, /* Silent reboot */
106 sys_boot_ldr_reboot = 0x06, /* Bootloader reboot */
107 sys_power_up_reboot = 0x07, /* Power on bootup. Older
108 * drivers may report as
109 * userReboot. */
110 sys_code_change = 0x08, /* Reboot to take code change.
111 * Older drivers may report as
112 * userReboot. */
113 sys_hardware_reset = 0x09, /* HW watchdog or front-panel
114 * reset button reset. Older
115 * drivers may report as
116 * userReboot. */
117 sys_watchdogInterrupt = 0x0A /* Pre-watchdog interrupt */
118};
119
120#endif /* _ASM_MACH_POWERTV_ASIC_H */
diff --git a/arch/mips/include/asm/mach-powertv/asic_reg_map.h b/arch/mips/include/asm/mach-powertv/asic_reg_map.h
deleted file mode 100644
index 20348e817b09..000000000000
--- a/arch/mips/include/asm/mach-powertv/asic_reg_map.h
+++ /dev/null
@@ -1,90 +0,0 @@
1/*
2 * asic_reg_map.h
3 *
4 * A macro-enclosed list of the elements for the register_map structure for
5 * use in defining and manipulating the structure.
6 *
7 * Copyright (C) 2009 Cisco Systems, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24REGISTER_MAP_ELEMENT(eic_slow0_strt_add)
25REGISTER_MAP_ELEMENT(eic_cfg_bits)
26REGISTER_MAP_ELEMENT(eic_ready_status)
27REGISTER_MAP_ELEMENT(chipver3)
28REGISTER_MAP_ELEMENT(chipver2)
29REGISTER_MAP_ELEMENT(chipver1)
30REGISTER_MAP_ELEMENT(chipver0)
31REGISTER_MAP_ELEMENT(uart1_intstat)
32REGISTER_MAP_ELEMENT(uart1_inten)
33REGISTER_MAP_ELEMENT(uart1_config1)
34REGISTER_MAP_ELEMENT(uart1_config2)
35REGISTER_MAP_ELEMENT(uart1_divisorhi)
36REGISTER_MAP_ELEMENT(uart1_divisorlo)
37REGISTER_MAP_ELEMENT(uart1_data)
38REGISTER_MAP_ELEMENT(uart1_status)
39REGISTER_MAP_ELEMENT(int_stat_3)
40REGISTER_MAP_ELEMENT(int_stat_2)
41REGISTER_MAP_ELEMENT(int_stat_1)
42REGISTER_MAP_ELEMENT(int_stat_0)
43REGISTER_MAP_ELEMENT(int_config)
44REGISTER_MAP_ELEMENT(int_int_scan)
45REGISTER_MAP_ELEMENT(ien_int_3)
46REGISTER_MAP_ELEMENT(ien_int_2)
47REGISTER_MAP_ELEMENT(ien_int_1)
48REGISTER_MAP_ELEMENT(ien_int_0)
49REGISTER_MAP_ELEMENT(int_level_3_3)
50REGISTER_MAP_ELEMENT(int_level_3_2)
51REGISTER_MAP_ELEMENT(int_level_3_1)
52REGISTER_MAP_ELEMENT(int_level_3_0)
53REGISTER_MAP_ELEMENT(int_level_2_3)
54REGISTER_MAP_ELEMENT(int_level_2_2)
55REGISTER_MAP_ELEMENT(int_level_2_1)
56REGISTER_MAP_ELEMENT(int_level_2_0)
57REGISTER_MAP_ELEMENT(int_level_1_3)
58REGISTER_MAP_ELEMENT(int_level_1_2)
59REGISTER_MAP_ELEMENT(int_level_1_1)
60REGISTER_MAP_ELEMENT(int_level_1_0)
61REGISTER_MAP_ELEMENT(int_level_0_3)
62REGISTER_MAP_ELEMENT(int_level_0_2)
63REGISTER_MAP_ELEMENT(int_level_0_1)
64REGISTER_MAP_ELEMENT(int_level_0_0)
65REGISTER_MAP_ELEMENT(int_docsis_en)
66REGISTER_MAP_ELEMENT(mips_pll_setup)
67REGISTER_MAP_ELEMENT(fs432x4b4_usb_ctl)
68REGISTER_MAP_ELEMENT(test_bus)
69REGISTER_MAP_ELEMENT(crt_spare)
70REGISTER_MAP_ELEMENT(usb2_ohci_int_mask)
71REGISTER_MAP_ELEMENT(usb2_strap)
72REGISTER_MAP_ELEMENT(ehci_hcapbase)
73REGISTER_MAP_ELEMENT(ohci_hc_revision)
74REGISTER_MAP_ELEMENT(bcm1_bs_lmi_steer)
75REGISTER_MAP_ELEMENT(usb2_control)
76REGISTER_MAP_ELEMENT(usb2_stbus_obc)
77REGISTER_MAP_ELEMENT(usb2_stbus_mess_size)
78REGISTER_MAP_ELEMENT(usb2_stbus_chunk_size)
79REGISTER_MAP_ELEMENT(pcie_regs)
80REGISTER_MAP_ELEMENT(tim_ch)
81REGISTER_MAP_ELEMENT(tim_cl)
82REGISTER_MAP_ELEMENT(gpio_dout)
83REGISTER_MAP_ELEMENT(gpio_din)
84REGISTER_MAP_ELEMENT(gpio_dir)
85REGISTER_MAP_ELEMENT(watchdog)
86REGISTER_MAP_ELEMENT(front_panel)
87REGISTER_MAP_ELEMENT(misc_clk_ctl1)
88REGISTER_MAP_ELEMENT(misc_clk_ctl2)
89REGISTER_MAP_ELEMENT(crt_ext_ctl)
90REGISTER_MAP_ELEMENT(register_maps)
diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h
deleted file mode 100644
index 06712abb3e55..000000000000
--- a/arch/mips/include/asm/mach-powertv/asic_regs.h
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef __ASM_MACH_POWERTV_ASIC_H_
20#define __ASM_MACH_POWERTV_ASIC_H_
21#include <linux/io.h>
22
23/* ASIC types */
24enum asic_type {
25 ASIC_UNKNOWN,
26 ASIC_ZEUS,
27 ASIC_CALLIOPE,
28 ASIC_CRONUS,
29 ASIC_CRONUSLITE,
30 ASIC_GAIA,
31 ASICS /* Number of supported ASICs */
32};
33
34/* hardcoded values read from Chip Version registers */
35#define CRONUS_10 0x0B4C1C20
36#define CRONUS_11 0x0B4C1C21
37#define CRONUSLITE_10 0x0B4C1C40
38
39#define NAND_FLASH_BASE 0x03000000
40#define CALLIOPE_IO_BASE 0x08000000
41#define GAIA_IO_BASE 0x09000000
42#define CRONUS_IO_BASE 0x09000000
43#define ZEUS_IO_BASE 0x09000000
44
45#define ASIC_IO_SIZE 0x01000000
46
47/* Definitions for backward compatibility */
48#define UART1_INTSTAT uart1_intstat
49#define UART1_INTEN uart1_inten
50#define UART1_CONFIG1 uart1_config1
51#define UART1_CONFIG2 uart1_config2
52#define UART1_DIVISORHI uart1_divisorhi
53#define UART1_DIVISORLO uart1_divisorlo
54#define UART1_DATA uart1_data
55#define UART1_STATUS uart1_status
56
57/* ASIC register enumeration */
58union register_map_entry {
59 unsigned long phys;
60 u32 *virt;
61};
62
63#define REGISTER_MAP_ELEMENT(x) union register_map_entry x;
64struct register_map {
65#include <asm/mach-powertv/asic_reg_map.h>
66};
67#undef REGISTER_MAP_ELEMENT
68
69/**
70 * register_map_offset_phys - add an offset to the physical address
71 * @map: Pointer to the &struct register_map
72 * @offset: Value to add
73 *
74 * Only adds the base to non-zero physical addresses
75 */
76static inline void register_map_offset_phys(struct register_map *map,
77 unsigned long offset)
78{
79#define REGISTER_MAP_ELEMENT(x) do { \
80 if (map->x.phys != 0) \
81 map->x.phys += offset; \
82 } while (false);
83
84#include <asm/mach-powertv/asic_reg_map.h>
85#undef REGISTER_MAP_ELEMENT
86}
87
88/**
89 * register_map_virtualize - Convert &register_map to virtual addresses
90 * @map: Pointer to &register_map to virtualize
91 */
92static inline void register_map_virtualize(struct register_map *map)
93{
94#define REGISTER_MAP_ELEMENT(x) do { \
95 map->x.virt = (!map->x.phys) ? NULL : \
96 UNCAC_ADDR(phys_to_virt(map->x.phys)); \
97 } while (false);
98
99#include <asm/mach-powertv/asic_reg_map.h>
100#undef REGISTER_MAP_ELEMENT
101}
102
103extern struct register_map _asic_register_map;
104extern unsigned long asic_phy_base;
105
106/*
107 * Macros to interface to registers through their ioremapped address
108 * asic_reg_phys_addr Returns the physical address of the given register
109 * asic_reg_addr Returns the iomapped virtual address of the given
110 * register.
111 */
112#define asic_reg_addr(x) (_asic_register_map.x.virt)
113#define asic_reg_phys_addr(x) (virt_to_phys((void *) CAC_ADDR( \
114 (unsigned long) asic_reg_addr(x))))
115
116/*
117 * The asic_reg macro is gone. It should be replaced by either asic_read or
118 * asic_write, as appropriate.
119 */
120
121#define asic_read(x) readl(asic_reg_addr(x))
122#define asic_write(v, x) writel(v, asic_reg_addr(x))
123
124extern void asic_irq_init(void);
125#endif
diff --git a/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h b/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h
deleted file mode 100644
index 58c76ec32a19..000000000000
--- a/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * Copyright (C) 2010 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_
20#define _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_
21#define cpu_has_tlb 1
22#define cpu_has_4kex 1
23#define cpu_has_3k_cache 0
24#define cpu_has_4k_cache 1
25#define cpu_has_tx39_cache 0
26#define cpu_has_fpu 0
27#define cpu_has_counter 1
28#define cpu_has_watch 1
29#define cpu_has_divec 1
30#define cpu_has_vce 0
31#define cpu_has_cache_cdex_p 0
32#define cpu_has_cache_cdex_s 0
33#define cpu_has_mcheck 1
34#define cpu_has_ejtag 1
35#define cpu_has_llsc 1
36#define cpu_has_mips16 0
37#define cpu_has_mdmx 0
38#define cpu_has_mips3d 0
39#define cpu_has_smartmips 0
40#define cpu_has_vtag_icache 0
41#define cpu_has_dc_aliases 0
42#define cpu_has_ic_fills_f_dc 0
43#define cpu_has_mips32r1 0
44#define cpu_has_mips32r2 1
45#define cpu_has_mips64r1 0
46#define cpu_has_mips64r2 0
47#define cpu_has_dsp 0
48#define cpu_has_dsp2 0
49#define cpu_has_mipsmt 0
50#define cpu_has_userlocal 0
51#define cpu_has_nofpuex 0
52#define cpu_has_64bits 0
53#define cpu_has_64bit_zero_reg 0
54#define cpu_has_vint 1
55#define cpu_has_veic 1
56#define cpu_has_inclusive_pcaches 0
57
58#define cpu_dcache_line_size() 32
59#define cpu_icache_line_size() 32
60#endif
diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h
deleted file mode 100644
index 5d4c3fe04722..000000000000
--- a/arch/mips/include/asm/mach-powertv/dma-coherence.h
+++ /dev/null
@@ -1,107 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Version from mach-generic modified to support PowerTV port
7 * Portions Copyright (C) 2009 Cisco Systems, Inc.
8 * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
9 *
10 */
11
12#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H
13#define __ASM_MACH_POWERTV_DMA_COHERENCE_H
14
15#include <linux/sched.h>
16#include <linux/device.h>
17#include <asm/mach-powertv/asic.h>
18
19static inline bool is_kseg2(void *addr)
20{
21 return (unsigned long)addr >= KSEG2;
22}
23
24static inline unsigned long virt_to_phys_from_pte(void *addr)
25{
26 pgd_t *pgd;
27 pud_t *pud;
28 pmd_t *pmd;
29 pte_t *ptep, pte;
30
31 unsigned long virt_addr = (unsigned long)addr;
32 unsigned long phys_addr = 0UL;
33
34 /* get the page global directory. */
35 pgd = pgd_offset_k(virt_addr);
36
37 if (!pgd_none(*pgd)) {
38 /* get the page upper directory */
39 pud = pud_offset(pgd, virt_addr);
40 if (!pud_none(*pud)) {
41 /* get the page middle directory */
42 pmd = pmd_offset(pud, virt_addr);
43 if (!pmd_none(*pmd)) {
44 /* get a pointer to the page table entry */
45 ptep = pte_offset(pmd, virt_addr);
46 pte = *ptep;
47 /* check for a valid page */
48 if (pte_present(pte)) {
49 /* get the physical address the page is
50 * referring to */
51 phys_addr = (unsigned long)
52 page_to_phys(pte_page(pte));
53 /* add the offset within the page */
54 phys_addr |= (virt_addr & ~PAGE_MASK);
55 }
56 }
57 }
58 }
59
60 return phys_addr;
61}
62
63static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
64 size_t size)
65{
66 if (is_kseg2(addr))
67 return phys_to_dma(virt_to_phys_from_pte(addr));
68 else
69 return phys_to_dma(virt_to_phys(addr));
70}
71
72static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
73 struct page *page)
74{
75 return phys_to_dma(page_to_phys(page));
76}
77
78static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
79 dma_addr_t dma_addr)
80{
81 return dma_to_phys(dma_addr);
82}
83
84static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
85 size_t size, enum dma_data_direction direction)
86{
87}
88
89static inline int plat_dma_supported(struct device *dev, u64 mask)
90{
91 /*
92 * we fall back to GFP_DMA when the mask isn't all 1s,
93 * so we can't guarantee allocations that must be
94 * within a tighter range than GFP_DMA..
95 */
96 if (mask < DMA_BIT_MASK(24))
97 return 0;
98
99 return 1;
100}
101
102static inline int plat_device_is_coherent(struct device *dev)
103{
104 return 0;
105}
106
107#endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h
deleted file mode 100644
index 6c463be62156..000000000000
--- a/arch/mips/include/asm/mach-powertv/interrupts.h
+++ /dev/null
@@ -1,253 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_
20#define _ASM_MACH_POWERTV_INTERRUPTS_H_
21
22/*
23 * Defines for all of the interrupt lines
24 */
25
26/* Definitions for backward compatibility */
27#define kIrq_Uart1 irq_uart1
28
29#define ibase 0
30
31/*------------- Register: int_stat_3 */
32/* 126 unused (bit 31) */
33#define irq_asc2video (ibase+126) /* ASC 2 Video Interrupt */
34#define irq_asc1video (ibase+125) /* ASC 1 Video Interrupt */
35#define irq_comms_block_wd (ibase+124) /* ASC 1 Video Interrupt */
36#define irq_fdma_mailbox (ibase+123) /* FDMA Mailbox Output */
37#define irq_fdma_gp (ibase+122) /* FDMA GP Output */
38#define irq_mips_pic (ibase+121) /* MIPS Performance Counter
39 * Interrupt */
40#define irq_mips_timer (ibase+120) /* MIPS Timer Interrupt */
41#define irq_memory_protect (ibase+119) /* Memory Protection Interrupt
42 * -- Ored by glue logic inside
43 * SPARC ILC (see
44 * INT_MEM_PROT_STAT, below,
45 * for individual interrupts)
46 */
47/* 118 unused (bit 22) */
48#define irq_sbag (ibase+117) /* SBAG Interrupt -- Ored by
49 * glue logic inside SPARC ILC
50 * (see INT_SBAG_STAT, below,
51 * for individual interrupts) */
52#define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */
53#define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */
54/* 114 unused (bit 18) */
55#define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt --
56 * Ored by glue logic inside
57 * SPARC ILC (see
58 * INT_MAILBOX_STAT, below, for
59 * individual interrupts) */
60#define irq_fuse_stat1 (ibase+112) /* Fuse Status 1 */
61#define irq_fuse_stat2 (ibase+111) /* Fuse Status 2 */
62#define irq_fuse_stat3 (ibase+110) /* Blitter Interrupt / Fuse
63 * Status 3 */
64#define irq_blitter (ibase+110) /* Blitter Interrupt / Fuse
65 * Status 3 */
66#define irq_avc1_pp0 (ibase+109) /* AVC Decoder #1 PP0
67 * Interrupt */
68#define irq_avc1_pp1 (ibase+108) /* AVC Decoder #1 PP1
69 * Interrupt */
70#define irq_avc1_mbe (ibase+107) /* AVC Decoder #1 MBE
71 * Interrupt */
72#define irq_avc2_pp0 (ibase+106) /* AVC Decoder #2 PP0
73 * Interrupt */
74#define irq_avc2_pp1 (ibase+105) /* AVC Decoder #2 PP1
75 * Interrupt */
76#define irq_avc2_mbe (ibase+104) /* AVC Decoder #2 MBE
77 * Interrupt */
78#define irq_zbug_spi (ibase+103) /* Zbug SPI Slave Interrupt */
79#define irq_qam_mod2 (ibase+102) /* QAM Modulator 2 DMA
80 * Interrupt */
81#define irq_ir_rx (ibase+101) /* IR RX 2 Interrupt */
82#define irq_aud_dsp2 (ibase+100) /* Audio DSP #2 Interrupt */
83#define irq_aud_dsp1 (ibase+99) /* Audio DSP #1 Interrupt */
84#define irq_docsis (ibase+98) /* DOCSIS Debug Interrupt */
85#define irq_sd_dvp1 (ibase+97) /* SD DVP #1 Interrupt */
86#define irq_sd_dvp2 (ibase+96) /* SD DVP #2 Interrupt */
87/*------------- Register: int_stat_2 */
88#define irq_hd_dvp (ibase+95) /* HD DVP Interrupt */
89#define kIrq_Prewatchdog (ibase+94) /* watchdog Pre-Interrupt */
90#define irq_timer2 (ibase+93) /* Programmable Timer
91 * Interrupt 2 */
92#define irq_1394 (ibase+92) /* 1394 Firewire Interrupt */
93#define irq_usbohci (ibase+91) /* USB 2.0 OHCI Interrupt */
94#define irq_usbehci (ibase+90) /* USB 2.0 EHCI Interrupt */
95#define irq_pciexp (ibase+89) /* PCI Express 0 Interrupt */
96#define irq_pciexp0 (ibase+89) /* PCI Express 0 Interrupt */
97#define irq_afe1 (ibase+88) /* AFE 1 Interrupt */
98#define irq_sata (ibase+87) /* SATA 1 Interrupt */
99#define irq_sata1 (ibase+87) /* SATA 1 Interrupt */
100#define irq_dtcp (ibase+86) /* DTCP Interrupt */
101#define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */
102/* 84 unused (bit 20) */
103/* 83 unused (bit 19) */
104/* 82 unused (bit 18) */
105#define irq_sata2 (ibase+81) /* SATA2 Interrupt */
106#define irq_uart2 (ibase+80) /* UART2 Interrupt */
107#define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1
108 * Host module) */
109#define irq_pod (ibase+78) /* POD Interrupt */
110#define irq_slave_usb (ibase+77) /* Slave USB */
111#define irq_denc1 (ibase+76) /* DENC #1 VTG Interrupt */
112#define irq_vbi_vtg (ibase+75) /* VBI VTG Interrupt */
113#define irq_afe2 (ibase+74) /* AFE 2 Interrupt */
114#define irq_denc2 (ibase+73) /* DENC #2 VTG Interrupt */
115#define irq_asc2 (ibase+72) /* ASC #2 Interrupt */
116#define irq_asc1 (ibase+71) /* ASC #1 Interrupt */
117#define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */
118#define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */
119#define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */
120/* 67 unused (bit 03) */
121/* 66 unused (bit 02) */
122/* 65 unused (bit 01) */
123/* 64 unused (bit 00) */
124/*------------- Register: int_stat_1 */
125/* 63 unused (bit 31) */
126/* 62 unused (bit 30) */
127/* 61 unused (bit 29) */
128/* 60 unused (bit 28) */
129/* 59 unused (bit 27) */
130/* 58 unused (bit 26) */
131/* 57 unused (bit 25) */
132/* 56 unused (bit 24) */
133#define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory
134 * Interrupt */
135#define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit
136 * Interrupt */
137#define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit
138 * Interrupt */
139#define irq_buf_dma_transmit_error (ibase+52) /* BufDMA Transmit Error
140 * Interrupt */
141#define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive
142 * Interrupt */
143#define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive
144 * Interrupt */
145#define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error
146 * Interrupt */
147#define irq_qamdma_transmit_play (ibase+48) /* QAMDMA Transmit/Play
148 * Interrupt */
149#define irq_qamdma_transmit_error (ibase+47) /* QAMDMA Transmit Error
150 * Interrupt */
151#define irq_qamdma_recv2high (ibase+46) /* QAMDMA Receive 2 High
152 * (Chans 63-32) */
153#define irq_qamdma_recv2low (ibase+45) /* QAMDMA Receive 2 Low
154 * (Chans 31-0) */
155#define irq_qamdma_recv1high (ibase+44) /* QAMDMA Receive 1 High
156 * (Chans 63-32) */
157#define irq_qamdma_recv1low (ibase+43) /* QAMDMA Receive 1 Low
158 * (Chans 31-0) */
159#define irq_qamdma_recv_error (ibase+42) /* QAMDMA Receive Error
160 * Interrupt */
161#define irq_mpegsplice (ibase+41) /* MPEG Splice Interrupt */
162#define irq_deinterlace_rdy (ibase+40) /* Deinterlacer Frame Ready
163 * Interrupt */
164#define irq_ext_in0 (ibase+39) /* External Interrupt irq_in0 */
165#define irq_gpio3 (ibase+38) /* GP I/O IRQ 3 - From GP I/O
166 * Module */
167#define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O
168 * Module (ABE_intN) */
169#define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or
170 * Discontinuity 1 */
171#define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or
172 * Discontinuity 2 */
173#define irq_parse_peierr (ibase+34) /* PID Parser Error Detect
174 * (PEI) */
175#define irq_parse_cont_err (ibase+33) /* PID Parser continuity error
176 * detect */
177#define irq_ds1framer (ibase+32) /* DS1 Framer Interrupt */
178/*------------- Register: int_stat_0 */
179#define irq_gpio1 (ibase+31) /* GP I/O IRQ 1 - From GP I/O
180 * Module */
181#define irq_gpio0 (ibase+30) /* GP I/O IRQ 0 - From GP I/O
182 * Module */
183#define irq_qpsk_out_aloha (ibase+29) /* QPSK Output Slotted Aloha
184 * (chan 3) Transmission
185 * Completed OK */
186#define irq_qpsk_out_tdma (ibase+28) /* QPSK Output TDMA (chan 2)
187 * Transmission Completed OK */
188#define irq_qpsk_out_reserve (ibase+27) /* QPSK Output Reservation
189 * (chan 1) Transmission
190 * Completed OK */
191#define irq_qpsk_out_aloha_err (ibase+26) /* QPSK Output Slotted Aloha
192 * (chan 3)Transmission
193 * completed with Errors. */
194#define irq_qpsk_out_tdma_err (ibase+25) /* QPSK Output TDMA (chan 2)
195 * Transmission completed with
196 * Errors. */
197#define irq_qpsk_out_rsrv_err (ibase+24) /* QPSK Output Reservation
198 * (chan 1) Transmission
199 * completed with Errors */
200#define irq_aloha_fail (ibase+23) /* Unsuccessful Resend of Aloha
201 * for N times. Aloha retry
202 * timeout for channel 3. */
203#define irq_timer1 (ibase+22) /* Programmable Timer
204 * Interrupt */
205#define irq_keyboard (ibase+21) /* Keyboard Module Interrupt */
206#define irq_i2c (ibase+20) /* I2C Module Interrupt */
207#define irq_spi (ibase+19) /* SPI Module Interrupt */
208#define irq_irblaster (ibase+18) /* IR Blaster Interrupt */
209#define irq_splice_detect (ibase+17) /* PID Key Change Interrupt or
210 * Splice Detect Interrupt */
211#define irq_se_micro (ibase+16) /* Secure Micro I/F Module
212 * Interrupt */
213#define irq_uart1 (ibase+15) /* UART Interrupt */
214#define irq_irrecv (ibase+14) /* IR Receiver Interrupt */
215#define irq_host_int1 (ibase+13) /* Host-to-Host Interrupt 1 */
216#define irq_host_int0 (ibase+12) /* Host-to-Host Interrupt 0 */
217#define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */
218#define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error
219 * Interrupt */
220/* 9 unused (bit 09) */
221/* 8 unused (bit 08) */
222#define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error
223 * Interrupt */
224#define irq_psilength_err (ibase+6) /* QAM PSI Length Error
225 * Interrupt */
226#define irq_esfforward (ibase+5) /* ESF Interrupt Mark From
227 * Forward Path Reference -
228 * every 3ms when forward Mbits
229 * and forward slot control
230 * bytes are updated. */
231#define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from
232 * Reverse Path Reference -
233 * delayed from forward mark by
234 * the ranging delay plus a
235 * fixed amount. When reverse
236 * Mbits and reverse slot
237 * control bytes are updated.
238 * Occurs every 3ms for 3.0M and
239 * 1.554 M upstream rates and
240 * every 6 ms for 256K upstream
241 * rate. */
242#define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on
243 * Channel 1. */
244#define irq_reservation (ibase+2) /* Partial (or Incremental)
245 * Reservation Message Completed
246 * or Slotted aloha verify for
247 * channel 1. */
248#define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify
249 * Interrupt or Reservation
250 * increment completed for
251 * channel 3. */
252#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */
253#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */
diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h
deleted file mode 100644
index c86ef094ec37..000000000000
--- a/arch/mips/include/asm/mach-powertv/ioremap.h
+++ /dev/null
@@ -1,167 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version
5 * 2 of the License, or (at your option) any later version.
6 *
7 * Portions Copyright (C) Cisco Systems, Inc.
8 */
9#ifndef __ASM_MACH_POWERTV_IOREMAP_H
10#define __ASM_MACH_POWERTV_IOREMAP_H
11
12#include <linux/types.h>
13#include <linux/log2.h>
14#include <linux/compiler.h>
15
16#include <asm/pgtable-bits.h>
17#include <asm/addrspace.h>
18
19/* We're going to mess with bits, so get sizes */
20#define IOR_BPC 8 /* Bits per char */
21#define IOR_PHYS_BITS (IOR_BPC * sizeof(phys_addr_t))
22#define IOR_DMA_BITS (IOR_BPC * sizeof(dma_addr_t))
23
24/*
25 * Define the granularity of physical/DMA mapping in terms of the number
26 * of bits that defines the offset within a grain. These will be the
27 * least significant bits of the address. The rest of a physical or DMA
28 * address will be used to index into an appropriate table to find the
29 * offset to add to the address to yield the corresponding DMA or physical
30 * address, respectively.
31 */
32#define IOR_LSBITS 22 /* Bits in a grain */
33
34/*
35 * Compute the number of most significant address bits after removing those
36 * used for the offset within a grain and then compute the number of table
37 * entries for the conversion.
38 */
39#define IOR_PHYS_MSBITS (IOR_PHYS_BITS - IOR_LSBITS)
40#define IOR_NUM_PHYS_TO_DMA ((phys_addr_t) 1 << IOR_PHYS_MSBITS)
41
42#define IOR_DMA_MSBITS (IOR_DMA_BITS - IOR_LSBITS)
43#define IOR_NUM_DMA_TO_PHYS ((dma_addr_t) 1 << IOR_DMA_MSBITS)
44
45/*
46 * Define data structures used as elements in the arrays for the conversion
47 * between physical and DMA addresses. We do some slightly fancy math to
48 * compute the width of the offset element of the conversion tables so
49 * that we can have the smallest conversion tables. Next, round up the
50 * sizes to the next higher power of two, i.e. the offset element will have
51 * 8, 16, 32, 64, etc. bits. This eliminates the need to mask off any
52 * bits. Finally, we compute a shift value that puts the most significant
53 * bits of the offset into the most significant bits of the offset element.
54 * This makes it more efficient on processors without barrel shifters and
55 * easier to see the values if the conversion table is dumped in binary.
56 */
57#define _IOR_OFFSET_WIDTH(n) (1 << order_base_2(n))
58#define IOR_OFFSET_WIDTH(n) \
59 (_IOR_OFFSET_WIDTH(n) < 8 ? 8 : _IOR_OFFSET_WIDTH(n))
60
61#define IOR_PHYS_OFFSET_BITS IOR_OFFSET_WIDTH(IOR_PHYS_MSBITS)
62#define IOR_PHYS_SHIFT (IOR_PHYS_BITS - IOR_PHYS_OFFSET_BITS)
63
64#define IOR_DMA_OFFSET_BITS IOR_OFFSET_WIDTH(IOR_DMA_MSBITS)
65#define IOR_DMA_SHIFT (IOR_DMA_BITS - IOR_DMA_OFFSET_BITS)
66
67struct ior_phys_to_dma {
68 dma_addr_t offset:IOR_DMA_OFFSET_BITS __packed
69 __aligned((IOR_DMA_OFFSET_BITS / IOR_BPC));
70};
71
72struct ior_dma_to_phys {
73 dma_addr_t offset:IOR_PHYS_OFFSET_BITS __packed
74 __aligned((IOR_PHYS_OFFSET_BITS / IOR_BPC));
75};
76
77extern struct ior_phys_to_dma _ior_phys_to_dma[IOR_NUM_PHYS_TO_DMA];
78extern struct ior_dma_to_phys _ior_dma_to_phys[IOR_NUM_DMA_TO_PHYS];
79
80static inline dma_addr_t _phys_to_dma_offset_raw(phys_addr_t phys)
81{
82 return (dma_addr_t)_ior_phys_to_dma[phys >> IOR_LSBITS].offset;
83}
84
85static inline dma_addr_t _dma_to_phys_offset_raw(dma_addr_t dma)
86{
87 return (dma_addr_t)_ior_dma_to_phys[dma >> IOR_LSBITS].offset;
88}
89
90/* These are not portable and should not be used in drivers. Drivers should
91 * be using ioremap() and friends to map physical addresses to virtual
92 * addresses and dma_map*() and friends to map virtual addresses into DMA
93 * addresses and back.
94 */
95static inline dma_addr_t phys_to_dma(phys_addr_t phys)
96{
97 return phys + (_phys_to_dma_offset_raw(phys) << IOR_PHYS_SHIFT);
98}
99
100static inline phys_addr_t dma_to_phys(dma_addr_t dma)
101{
102 return dma + (_dma_to_phys_offset_raw(dma) << IOR_DMA_SHIFT);
103}
104
105extern void ioremap_add_map(dma_addr_t phys, phys_addr_t alias,
106 dma_addr_t size);
107
108/*
109 * Allow physical addresses to be fixed up to help peripherals located
110 * outside the low 32-bit range -- generic pass-through version.
111 */
112static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
113{
114 return phys_addr;
115}
116
117/*
118 * Handle the special case of addresses the area aliased into the first
119 * 512 MiB of the processor's physical address space. These turn into either
120 * kseg0 or kseg1 addresses, depending on flags.
121 */
122static inline void __iomem *plat_ioremap(phys_t start, unsigned long size,
123 unsigned long flags)
124{
125 phys_addr_t start_offset;
126 void __iomem *result = NULL;
127
128 /* Start by checking to see whether this is an aliased address */
129 start_offset = _dma_to_phys_offset_raw(start);
130
131 /*
132 * If:
133 * o the memory is aliased into the first 512 MiB, and
134 * o the start and end are in the same RAM bank, and
135 * o we don't have a zero size or wrap around, and
136 * o we are supposed to create an uncached mapping,
137 * handle this is a kseg0 or kseg1 address
138 */
139 if (start_offset != 0) {
140 phys_addr_t last;
141 dma_addr_t dma_to_phys_offset;
142
143 last = start + size - 1;
144 dma_to_phys_offset =
145 _dma_to_phys_offset_raw(last) << IOR_DMA_SHIFT;
146
147 if (dma_to_phys_offset == start_offset &&
148 size != 0 && start <= last) {
149 phys_t adjusted_start;
150 adjusted_start = start + start_offset;
151 if (flags == _CACHE_UNCACHED)
152 result = (void __iomem *) (unsigned long)
153 CKSEG1ADDR(adjusted_start);
154 else
155 result = (void __iomem *) (unsigned long)
156 CKSEG0ADDR(adjusted_start);
157 }
158 }
159
160 return result;
161}
162
163static inline int plat_iounmap(const volatile void __iomem *addr)
164{
165 return 0;
166}
167#endif /* __ASM_MACH_POWERTV_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-powertv/irq.h b/arch/mips/include/asm/mach-powertv/irq.h
deleted file mode 100644
index 4bd5d0c61a91..000000000000
--- a/arch/mips/include/asm/mach-powertv/irq.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_IRQ_H
20#define _ASM_MACH_POWERTV_IRQ_H
21#include <asm/mach-powertv/interrupts.h>
22
23#define MIPS_CPU_IRQ_BASE ibase
24#define NR_IRQS 127
25#endif
diff --git a/arch/mips/include/asm/mach-powertv/powertv-clock.h b/arch/mips/include/asm/mach-powertv/powertv-clock.h
deleted file mode 100644
index 6f3e9a0fcf8c..000000000000
--- a/arch/mips/include/asm/mach-powertv/powertv-clock.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18/*
19 * Local definitions for the powertv PCI code
20 */
21
22#ifndef _POWERTV_PCI_POWERTV_PCI_H_
23#define _POWERTV_PCI_POWERTV_PCI_H_
24extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
25extern int asic_pcie_init(void);
26extern int asic_pcie_init(void);
27
28extern int log_level;
29#endif
diff --git a/arch/mips/include/asm/mach-powertv/war.h b/arch/mips/include/asm/mach-powertv/war.h
deleted file mode 100644
index c5651c8e58d1..000000000000
--- a/arch/mips/include/asm/mach-powertv/war.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * This version for the PowerTV platform copied from the Malta version.
7 *
8 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
9 * Portions copyright (C) 2009 Cisco Systems, Inc.
10 */
11#ifndef __ASM_MACH_POWERTV_WAR_H
12#define __ASM_MACH_POWERTV_WAR_H
13
14#define R4600_V1_INDEX_ICACHEOP_WAR 0
15#define R4600_V1_HIT_CACHEOP_WAR 0
16#define R4600_V2_HIT_CACHEOP_WAR 0
17#define R5432_CP0_INTERRUPT_WAR 0
18#define BCM1250_M3_WAR 0
19#define SIBYTE_1956_WAR 0
20#define MIPS4K_ICACHE_REFILL_WAR 1
21#define MIPS_CACHE_SYNC_WAR 1
22#define TX49XX_ICACHE_INDEX_INV_WAR 0
23#define ICACHE_REFILLS_WORKAROUND_WAR 1
24#define R10000_LLSC_WAR 0
25#define MIPS34K_MISSED_ITLB_WAR 0
26
27#endif /* __ASM_MACH_POWERTV_WAR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-06 15:42:33 -0500