7 files changed, 31 insertions, 154 deletions

diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 75a6df7fd265..227705d9d5ae 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -10,6 +10,10 @@ config CAVIUM_CN63XXP1
           non-CN63XXP1 hardware, so it is recommended to select "n"
           unless it is known the workarounds are needed.
 
+endif # CPU_CAVIUM_OCTEON
+
+if CAVIUM_OCTEON_SOC
+
 config CAVIUM_OCTEON_2ND_KERNEL
         bool "Build the kernel to be used as a 2nd kernel on the same chip"
         default "n"
@@ -19,17 +23,6 @@ config CAVIUM_OCTEON_2ND_KERNEL
           with this option to be run at the same time as one built without this
           option.
 
-config CAVIUM_OCTEON_HW_FIX_UNALIGNED
-        bool "Enable hardware fixups of unaligned loads and stores"
-        default "y"
-        help
-          Configure the Octeon hardware to automatically fix unaligned loads
-          and stores. Normally unaligned accesses are fixed using a kernel
-          exception handler. This option enables the hardware automatic fixups,
-          which requires only an extra 3 cycles. Disable this option if you
-          are running code that relies on address exceptions on unaligned
-          accesses.
-
 config CAVIUM_OCTEON_CVMSEG_SIZE
         int "Number of L1 cache lines reserved for CVMSEG memory"
         range 0 54
@@ -103,4 +96,4 @@ config OCTEON_ILM
           To compile this driver as a module, choose M here.  The module
           will be called octeon-ilm
 
-endif # CPU_CAVIUM_OCTEON
+endif # CAVIUM_OCTEON_SOC
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index e3fd50cc709c..4e952043c922 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -12,7 +12,7 @@
 CFLAGS_octeon-platform.o = -I$(src)/../../../scripts/dtc/libfdt
 CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt
 
-obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
+obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o
 obj-y += dma-octeon.o
 obj-y += octeon-memcpy.o
 obj-y += executive/
diff --git a/arch/mips/cavium-octeon/Platform b/arch/mips/cavium-octeon/Platform
index 1e43ccf1a792..8a301cb12d68 100644
--- a/arch/mips/cavium-octeon/Platform
+++ b/arch/mips/cavium-octeon/Platform
@@ -1,11 +1,11 @@
 #
 # Cavium Octeon
 #
-platform-$(CONFIG_CPU_CAVIUM_OCTEON)    += cavium-octeon/
-cflags-$(CONFIG_CPU_CAVIUM_OCTEON)      +=                              \
+platform-$(CONFIG_CAVIUM_OCTEON_SOC)    += cavium-octeon/
+cflags-$(CONFIG_CAVIUM_OCTEON_SOC)      +=                              \
                 -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
 ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
-load-$(CONFIG_CPU_CAVIUM_OCTEON)        += 0xffffffff84100000
+load-$(CONFIG_CAVIUM_OCTEON_SOC)        += 0xffffffff84100000
 else
-load-$(CONFIG_CPU_CAVIUM_OCTEON)        += 0xffffffff81100000
+load-$(CONFIG_CAVIUM_OCTEON_SOC)        += 0xffffffff81100000
 endif
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
index 7c6497781895..0a1283ce47f5 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
@@ -181,6 +181,11 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
                         return ipd_port - 16 + 4;
                 else
                         return -1;
+        case CVMX_BOARD_TYPE_UBNT_E100:
+                if (ipd_port >= 0 && ipd_port <= 2)
+                        return 7 - ipd_port;
+                else
+                        return -1;
         }
 
         /* Some unknown board. Somebody forgot to update this function... */
@@ -706,6 +711,14 @@ int __cvmx_helper_board_hardware_enable(int interface)
                                 }
                         }
                 }
+        } else if (cvmx_sysinfo_get()->board_type ==
+                        CVMX_BOARD_TYPE_UBNT_E100) {
+                cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 0);
+                cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 0x10);
+                cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0);
+                cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0x10);
+                cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(2, interface), 0);
+                cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(2, interface), 0x10);
         }
         return 0;
 }
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index 389512e2abd6..7b746e7bf7a1 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -490,8 +490,15 @@ int __init octeon_prune_device_tree(void)
 
                 if (alias_prop) {
                         uart = fdt_path_offset(initial_boot_params, alias_prop);
-                        if (uart_mask & (1 << i))
+                        if (uart_mask & (1 << i)) {
+                                __be32 f;
+
+                                f = cpu_to_be32(octeon_get_io_clock_rate());
+                                fdt_setprop_inplace(initial_boot_params,
+                                                    uart, "clock-frequency",
+                                                    &f, sizeof(f));
                                 continue;
+                        }
                         pr_debug("Deleting uart%d\n", i);
                         fdt_nop_node(initial_boot_params, uart);
                         fdt_nop_property(initial_boot_params, aliases,
diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c
deleted file mode 100644
index f393f65f3923..000000000000
--- a/arch/mips/cavium-octeon/serial.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004-2007 Cavium Networks
- */
-#include <linux/console.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial.h>
-#include <linux/serial_8250.h>
-#include <linux/serial_reg.h>
-#include <linux/tty.h>
-#include <linux/irq.h>
-
-#include <asm/time.h>
-
-#include <asm/octeon/octeon.h>
-
-#define DEBUG_UART 1
-
-unsigned int octeon_serial_in(struct uart_port *up, int offset)
-{
-        int rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
-        if (offset == UART_IIR && (rv & 0xf) == 7) {
-                /* Busy interrupt, read the USR (39) and try again. */
-                cvmx_read_csr((uint64_t)(up->membase + (39 << 3)));
-                rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
-        }
-        return rv;
-}
-
-void octeon_serial_out(struct uart_port *up, int offset, int value)
-{
-        /*
-         * If bits 6 or 7 of the OCTEON UART's LCR are set, it quits
-         * working.
-         */
-        if (offset == UART_LCR)
-                value &= 0x9f;
-        cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value);
-}
-
-static int octeon_serial_probe(struct platform_device *pdev)
-{
-        int irq, res;
-        struct resource *res_mem;
-        struct uart_8250_port up;
-
-        /* All adaptors have an irq.  */
-        irq = platform_get_irq(pdev, 0);
-        if (irq < 0)
-                return irq;
-
-        memset(&up, 0, sizeof(up));
-
-        up.port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
-        up.port.type = PORT_OCTEON;
-        up.port.iotype = UPIO_MEM;
-        up.port.regshift = 3;
-        up.port.dev = &pdev->dev;
-
-        if (octeon_is_simulation())
-                /* Make simulator output fast*/
-                up.port.uartclk = 115200 * 16;
-        else
-                up.port.uartclk = octeon_get_io_clock_rate();
-
-        up.port.serial_in = octeon_serial_in;
-        up.port.serial_out = octeon_serial_out;
-        up.port.irq = irq;
-
-        res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (res_mem == NULL) {
-                dev_err(&pdev->dev, "found no memory resource\n");
-                return -ENXIO;
-        }
-        up.port.mapbase = res_mem->start;
-        up.port.membase = ioremap(res_mem->start, resource_size(res_mem));
-
-        res = serial8250_register_8250_port(&up);
-
-        return res >= 0 ? 0 : res;
-}
-
-static struct of_device_id octeon_serial_match[] = {
-        {
-                .compatible = "cavium,octeon-3860-uart",
-        },
-        {},
-};
-MODULE_DEVICE_TABLE(of, octeon_serial_match);
-
-static struct platform_driver octeon_serial_driver = {
-        .probe          = octeon_serial_probe,
-        .driver         = {
-                .owner  = THIS_MODULE,
-                .name   = "octeon_serial",
-                .of_match_table = octeon_serial_match,
-        },
-};
-
-static int __init octeon_serial_init(void)
-{
-        return platform_driver_register(&octeon_serial_driver);
-}
-late_initcall(octeon_serial_init);
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 2a75ff249e71..48b08eb9d9e4 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -41,12 +41,6 @@
 #include <asm/octeon/pci-octeon.h>
 #include <asm/octeon/cvmx-mio-defs.h>
 
-#ifdef CONFIG_CAVIUM_DECODE_RSL
-extern void cvmx_interrupt_rsl_decode(void);
-extern int __cvmx_interrupt_ecc_report_single_bit_errors;
-extern void cvmx_interrupt_rsl_enable(void);
-#endif
-
 extern struct plat_smp_ops octeon_smp_ops;
 
 #ifdef CONFIG_PCI
@@ -464,18 +458,6 @@ static void octeon_halt(void)
 }
 
 /**
- * Handle all the error condition interrupts that might occur.
- *
- */
-#ifdef CONFIG_CAVIUM_DECODE_RSL
-static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id)
-{
-        cvmx_interrupt_rsl_decode();
-        return IRQ_HANDLED;
-}
-#endif
-
-/**
  * Return a string representing the system type
  *
  * Returns
@@ -1065,15 +1047,6 @@ void prom_free_prom_memory(void)
                         panic("Core-14449 WAR not in place (%04x).\n"
                               "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn);
         }
-#ifdef CONFIG_CAVIUM_DECODE_RSL
-        cvmx_interrupt_rsl_enable();
-
-        /* Add an interrupt handler for general failures. */
-        if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED,
-                        "RML/RSL", octeon_rlm_interrupt)) {
-                panic("Unable to request_irq(OCTEON_IRQ_RML)");
-        }
-#endif
 }
 
 int octeon_prune_device_tree(void);