diff options
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/am437x-sk-evm.dts | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/am57xx-beagle-x15.dts | 11 | ||||
| -rw-r--r-- | arch/arm/boot/dts/dra7.dtsi | 10 | ||||
| -rw-r--r-- | arch/arm/boot/dts/omap3-n900.dts | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/omap3.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/omap5.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/configs/omap2plus_defconfig | 2 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/prm-regbits-34xx.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/prm-regbits-44xx.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/timer.c | 13 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/vc.c | 12 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/vc.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/vc3xxx_data.c | 1 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/vc44xx_data.c | 1 |
14 files changed, 42 insertions, 24 deletions
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 8ae29c955c11..c17097d2c167 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts | |||
| @@ -49,7 +49,7 @@ | |||
| 49 | pinctrl-0 = <&matrix_keypad_pins>; | 49 | pinctrl-0 = <&matrix_keypad_pins>; |
| 50 | 50 | ||
| 51 | debounce-delay-ms = <5>; | 51 | debounce-delay-ms = <5>; |
| 52 | col-scan-delay-us = <1500>; | 52 | col-scan-delay-us = <5>; |
| 53 | 53 | ||
| 54 | row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */ | 54 | row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */ |
| 55 | &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */ | 55 | &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */ |
| @@ -473,7 +473,7 @@ | |||
| 473 | interrupt-parent = <&gpio0>; | 473 | interrupt-parent = <&gpio0>; |
| 474 | interrupts = <31 0>; | 474 | interrupts = <31 0>; |
| 475 | 475 | ||
| 476 | wake-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; | 476 | reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; |
| 477 | 477 | ||
| 478 | touchscreen-size-x = <480>; | 478 | touchscreen-size-x = <480>; |
| 479 | touchscreen-size-y = <272>; | 479 | touchscreen-size-y = <272>; |
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts index 15f198e4864d..7128fad991ac 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15.dts +++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | aliases { | 18 | aliases { |
| 19 | rtc0 = &mcp_rtc; | 19 | rtc0 = &mcp_rtc; |
| 20 | rtc1 = &tps659038_rtc; | 20 | rtc1 = &tps659038_rtc; |
| 21 | rtc2 = &rtc; | ||
| 21 | }; | 22 | }; |
| 22 | 23 | ||
| 23 | memory { | 24 | memory { |
| @@ -83,7 +84,7 @@ | |||
| 83 | gpio_fan: gpio_fan { | 84 | gpio_fan: gpio_fan { |
| 84 | /* Based on 5v 500mA AFB02505HHB */ | 85 | /* Based on 5v 500mA AFB02505HHB */ |
| 85 | compatible = "gpio-fan"; | 86 | compatible = "gpio-fan"; |
| 86 | gpios = <&tps659038_gpio 1 GPIO_ACTIVE_HIGH>; | 87 | gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; |
| 87 | gpio-fan,speed-map = <0 0>, | 88 | gpio-fan,speed-map = <0 0>, |
| 88 | <13000 1>; | 89 | <13000 1>; |
| 89 | #cooling-cells = <2>; | 90 | #cooling-cells = <2>; |
| @@ -130,8 +131,8 @@ | |||
| 130 | 131 | ||
| 131 | uart3_pins_default: uart3_pins_default { | 132 | uart3_pins_default: uart3_pins_default { |
| 132 | pinctrl-single,pins = < | 133 | pinctrl-single,pins = < |
| 133 | 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd.rxd */ | 134 | 0x3f8 (PIN_INPUT_SLEW | MUX_MODE2) /* uart2_ctsn.uart3_rxd */ |
| 134 | 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd.txd */ | 135 | 0x3fc (PIN_INPUT_SLEW | MUX_MODE1) /* uart2_rtsn.uart3_txd */ |
| 135 | >; | 136 | >; |
| 136 | }; | 137 | }; |
| 137 | 138 | ||
| @@ -455,7 +456,7 @@ | |||
| 455 | mcp_rtc: rtc@6f { | 456 | mcp_rtc: rtc@6f { |
| 456 | compatible = "microchip,mcp7941x"; | 457 | compatible = "microchip,mcp7941x"; |
| 457 | reg = <0x6f>; | 458 | reg = <0x6f>; |
| 458 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_LOW>; /* IRQ_SYS_1N */ | 459 | interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; /* IRQ_SYS_1N */ |
| 459 | 460 | ||
| 460 | pinctrl-names = "default"; | 461 | pinctrl-names = "default"; |
| 461 | pinctrl-0 = <&mcp79410_pins_default>; | 462 | pinctrl-0 = <&mcp79410_pins_default>; |
| @@ -478,7 +479,7 @@ | |||
| 478 | &uart3 { | 479 | &uart3 { |
| 479 | status = "okay"; | 480 | status = "okay"; |
| 480 | interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, | 481 | interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, |
| 481 | <&dra7_pmx_core 0x248>; | 482 | <&dra7_pmx_core 0x3f8>; |
| 482 | 483 | ||
| 483 | pinctrl-names = "default"; | 484 | pinctrl-names = "default"; |
| 484 | pinctrl-0 = <&uart3_pins_default>; | 485 | pinctrl-0 = <&uart3_pins_default>; |
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 5332b57b4950..f03a091cd076 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi | |||
| @@ -911,7 +911,7 @@ | |||
| 911 | ti,clock-cycles = <16>; | 911 | ti,clock-cycles = <16>; |
| 912 | 912 | ||
| 913 | reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, | 913 | reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, |
| 914 | <0x4ae06014 0x4>, <0x4a003b20 0x8>, | 914 | <0x4ae06014 0x4>, <0x4a003b20 0xc>, |
| 915 | <0x4ae0c158 0x4>; | 915 | <0x4ae0c158 0x4>; |
| 916 | reg-names = "setup-address", "control-address", | 916 | reg-names = "setup-address", "control-address", |
| 917 | "int-address", "efuse-address", | 917 | "int-address", "efuse-address", |
| @@ -944,7 +944,7 @@ | |||
| 944 | ti,clock-cycles = <16>; | 944 | ti,clock-cycles = <16>; |
| 945 | 945 | ||
| 946 | reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, | 946 | reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, |
| 947 | <0x4ae06010 0x4>, <0x4a0025cc 0x8>, | 947 | <0x4ae06010 0x4>, <0x4a0025cc 0xc>, |
| 948 | <0x4a002470 0x4>; | 948 | <0x4a002470 0x4>; |
| 949 | reg-names = "setup-address", "control-address", | 949 | reg-names = "setup-address", "control-address", |
| 950 | "int-address", "efuse-address", | 950 | "int-address", "efuse-address", |
| @@ -977,7 +977,7 @@ | |||
| 977 | ti,clock-cycles = <16>; | 977 | ti,clock-cycles = <16>; |
| 978 | 978 | ||
| 979 | reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, | 979 | reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, |
| 980 | <0x4ae06010 0x4>, <0x4a0025e0 0x8>, | 980 | <0x4ae06010 0x4>, <0x4a0025e0 0xc>, |
| 981 | <0x4a00246c 0x4>; | 981 | <0x4a00246c 0x4>; |
| 982 | reg-names = "setup-address", "control-address", | 982 | reg-names = "setup-address", "control-address", |
| 983 | "int-address", "efuse-address", | 983 | "int-address", "efuse-address", |
| @@ -1010,7 +1010,7 @@ | |||
| 1010 | ti,clock-cycles = <16>; | 1010 | ti,clock-cycles = <16>; |
| 1011 | 1011 | ||
| 1012 | reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, | 1012 | reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, |
| 1013 | <0x4ae06010 0x4>, <0x4a003b08 0x8>, | 1013 | <0x4ae06010 0x4>, <0x4a003b08 0xc>, |
| 1014 | <0x4ae0c154 0x4>; | 1014 | <0x4ae0c154 0x4>; |
| 1015 | reg-names = "setup-address", "control-address", | 1015 | reg-names = "setup-address", "control-address", |
| 1016 | "int-address", "efuse-address", | 1016 | "int-address", "efuse-address", |
| @@ -1203,7 +1203,7 @@ | |||
| 1203 | status = "disabled"; | 1203 | status = "disabled"; |
| 1204 | }; | 1204 | }; |
| 1205 | 1205 | ||
| 1206 | rtc@48838000 { | 1206 | rtc: rtc@48838000 { |
| 1207 | compatible = "ti,am3352-rtc"; | 1207 | compatible = "ti,am3352-rtc"; |
| 1208 | reg = <0x48838000 0x100>; | 1208 | reg = <0x48838000 0x100>; |
| 1209 | interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, | 1209 | interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, |
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index a29315833ecd..5c16145920ea 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts | |||
| @@ -498,6 +498,8 @@ | |||
| 498 | DRVDD-supply = <&vmmc2>; | 498 | DRVDD-supply = <&vmmc2>; |
| 499 | IOVDD-supply = <&vio>; | 499 | IOVDD-supply = <&vio>; |
| 500 | DVDD-supply = <&vio>; | 500 | DVDD-supply = <&vio>; |
| 501 | |||
| 502 | ai3x-micbias-vg = <1>; | ||
| 501 | }; | 503 | }; |
| 502 | 504 | ||
| 503 | tlv320aic3x_aux: tlv320aic3x@19 { | 505 | tlv320aic3x_aux: tlv320aic3x@19 { |
| @@ -509,6 +511,8 @@ | |||
| 509 | DRVDD-supply = <&vmmc2>; | 511 | DRVDD-supply = <&vmmc2>; |
| 510 | IOVDD-supply = <&vio>; | 512 | IOVDD-supply = <&vio>; |
| 511 | DVDD-supply = <&vio>; | 513 | DVDD-supply = <&vio>; |
| 514 | |||
| 515 | ai3x-micbias-vg = <2>; | ||
| 512 | }; | 516 | }; |
| 513 | 517 | ||
| 514 | tsl2563: tsl2563@29 { | 518 | tsl2563: tsl2563@29 { |
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index d18a90f5eca3..69a40cfc1f29 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi | |||
| @@ -456,6 +456,7 @@ | |||
| 456 | }; | 456 | }; |
| 457 | 457 | ||
| 458 | mmu_isp: mmu@480bd400 { | 458 | mmu_isp: mmu@480bd400 { |
| 459 | #iommu-cells = <0>; | ||
| 459 | compatible = "ti,omap2-iommu"; | 460 | compatible = "ti,omap2-iommu"; |
| 460 | reg = <0x480bd400 0x80>; | 461 | reg = <0x480bd400 0x80>; |
| 461 | interrupts = <24>; | 462 | interrupts = <24>; |
| @@ -464,6 +465,7 @@ | |||
| 464 | }; | 465 | }; |
| 465 | 466 | ||
| 466 | mmu_iva: mmu@5d000000 { | 467 | mmu_iva: mmu@5d000000 { |
| 468 | #iommu-cells = <0>; | ||
| 467 | compatible = "ti,omap2-iommu"; | 469 | compatible = "ti,omap2-iommu"; |
| 468 | reg = <0x5d000000 0x80>; | 470 | reg = <0x5d000000 0x80>; |
| 469 | interrupts = <28>; | 471 | interrupts = <28>; |
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index efe5f737f39b..7d24ae0306b5 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi | |||
| @@ -128,7 +128,7 @@ | |||
| 128 | * hierarchy. | 128 | * hierarchy. |
| 129 | */ | 129 | */ |
| 130 | ocp { | 130 | ocp { |
| 131 | compatible = "ti,omap4-l3-noc", "simple-bus"; | 131 | compatible = "ti,omap5-l3-noc", "simple-bus"; |
| 132 | #address-cells = <1>; | 132 | #address-cells = <1>; |
| 133 | #size-cells = <1>; | 133 | #size-cells = <1>; |
| 134 | ranges; | 134 | ranges; |
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 9ff7b54b2a83..3743ca221d40 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig | |||
| @@ -393,7 +393,7 @@ CONFIG_TI_EDMA=y | |||
| 393 | CONFIG_DMA_OMAP=y | 393 | CONFIG_DMA_OMAP=y |
| 394 | # CONFIG_IOMMU_SUPPORT is not set | 394 | # CONFIG_IOMMU_SUPPORT is not set |
| 395 | CONFIG_EXTCON=m | 395 | CONFIG_EXTCON=m |
| 396 | CONFIG_EXTCON_GPIO=m | 396 | CONFIG_EXTCON_USB_GPIO=m |
| 397 | CONFIG_EXTCON_PALMAS=m | 397 | CONFIG_EXTCON_PALMAS=m |
| 398 | CONFIG_TI_EMIF=m | 398 | CONFIG_TI_EMIF=m |
| 399 | CONFIG_PWM=y | 399 | CONFIG_PWM=y |
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index cbefbd7cfdb5..661d753df584 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h | |||
| @@ -112,6 +112,7 @@ | |||
| 112 | #define OMAP3430_VC_CMD_ONLP_SHIFT 16 | 112 | #define OMAP3430_VC_CMD_ONLP_SHIFT 16 |
| 113 | #define OMAP3430_VC_CMD_RET_SHIFT 8 | 113 | #define OMAP3430_VC_CMD_RET_SHIFT 8 |
| 114 | #define OMAP3430_VC_CMD_OFF_SHIFT 0 | 114 | #define OMAP3430_VC_CMD_OFF_SHIFT 0 |
| 115 | #define OMAP3430_SREN_MASK (1 << 4) | ||
| 115 | #define OMAP3430_HSEN_MASK (1 << 3) | 116 | #define OMAP3430_HSEN_MASK (1 << 3) |
| 116 | #define OMAP3430_MCODE_MASK (0x7 << 0) | 117 | #define OMAP3430_MCODE_MASK (0x7 << 0) |
| 117 | #define OMAP3430_VALID_MASK (1 << 24) | 118 | #define OMAP3430_VALID_MASK (1 << 24) |
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h index b1c7a33e00e7..e794828dee55 100644 --- a/arch/arm/mach-omap2/prm-regbits-44xx.h +++ b/arch/arm/mach-omap2/prm-regbits-44xx.h | |||
| @@ -35,6 +35,7 @@ | |||
| 35 | #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 | 35 | #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 |
| 36 | #define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) | 36 | #define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) |
| 37 | #define OMAP4430_HSMCODE_MASK (0x7 << 0) | 37 | #define OMAP4430_HSMCODE_MASK (0x7 << 0) |
| 38 | #define OMAP4430_SRMODEEN_MASK (1 << 4) | ||
| 38 | #define OMAP4430_HSMODEEN_MASK (1 << 3) | 39 | #define OMAP4430_HSMODEEN_MASK (1 << 3) |
| 39 | #define OMAP4430_HSSCLL_SHIFT 24 | 40 | #define OMAP4430_HSSCLL_SHIFT 24 |
| 40 | #define OMAP4430_ICEPICK_RST_SHIFT 9 | 41 | #define OMAP4430_ICEPICK_RST_SHIFT 9 |
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index cef67af9e9b8..cac46d852da1 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c | |||
| @@ -298,14 +298,11 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, | |||
| 298 | if (IS_ERR(src)) | 298 | if (IS_ERR(src)) |
| 299 | return PTR_ERR(src); | 299 | return PTR_ERR(src); |
| 300 | 300 | ||
| 301 | if (clk_get_parent(timer->fclk) != src) { | 301 | r = clk_set_parent(timer->fclk, src); |
| 302 | r = clk_set_parent(timer->fclk, src); | 302 | if (r < 0) { |
| 303 | if (r < 0) { | 303 | pr_warn("%s: %s cannot set source\n", __func__, oh->name); |
| 304 | pr_warn("%s: %s cannot set source\n", __func__, | 304 | clk_put(src); |
| 305 | oh->name); | 305 | return r; |
| 306 | clk_put(src); | ||
| 307 | return r; | ||
| 308 | } | ||
| 309 | } | 306 | } |
| 310 | 307 | ||
| 311 | clk_put(src); | 308 | clk_put(src); |
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index be9ef834fa81..076fd20d7e5a 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c | |||
| @@ -316,7 +316,8 @@ static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm) | |||
| 316 | * idle. And we can also scale voltages to zero for off-idle. | 316 | * idle. And we can also scale voltages to zero for off-idle. |
| 317 | * Note that no actual voltage scaling during off-idle will | 317 | * Note that no actual voltage scaling during off-idle will |
| 318 | * happen unless the board specific twl4030 PMIC scripts are | 318 | * happen unless the board specific twl4030 PMIC scripts are |
| 319 | * loaded. | 319 | * loaded. See also omap_vc_i2c_init for comments regarding |
| 320 | * erratum i531. | ||
| 320 | */ | 321 | */ |
| 321 | val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET); | 322 | val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET); |
| 322 | if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) { | 323 | if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) { |
| @@ -704,9 +705,16 @@ static void __init omap_vc_i2c_init(struct voltagedomain *voltdm) | |||
| 704 | return; | 705 | return; |
| 705 | } | 706 | } |
| 706 | 707 | ||
| 708 | /* | ||
| 709 | * Note that for omap3 OMAP3430_SREN_MASK clears SREN to work around | ||
| 710 | * erratum i531 "Extra Power Consumed When Repeated Start Operation | ||
| 711 | * Mode Is Enabled on I2C Interface Dedicated for Smart Reflex (I2C4)". | ||
| 712 | * Otherwise I2C4 eventually leads into about 23mW extra power being | ||
| 713 | * consumed even during off idle using VMODE. | ||
| 714 | */ | ||
| 707 | i2c_high_speed = voltdm->pmic->i2c_high_speed; | 715 | i2c_high_speed = voltdm->pmic->i2c_high_speed; |
| 708 | if (i2c_high_speed) | 716 | if (i2c_high_speed) |
| 709 | voltdm->rmw(vc->common->i2c_cfg_hsen_mask, | 717 | voltdm->rmw(vc->common->i2c_cfg_clear_mask, |
| 710 | vc->common->i2c_cfg_hsen_mask, | 718 | vc->common->i2c_cfg_hsen_mask, |
| 711 | vc->common->i2c_cfg_reg); | 719 | vc->common->i2c_cfg_reg); |
| 712 | 720 | ||
diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h index cdbdd78e755e..89b83b7ff3ec 100644 --- a/arch/arm/mach-omap2/vc.h +++ b/arch/arm/mach-omap2/vc.h | |||
| @@ -34,6 +34,7 @@ struct voltagedomain; | |||
| 34 | * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register | 34 | * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register |
| 35 | * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register | 35 | * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register |
| 36 | * @i2c_cfg_reg: I2C configuration register offset | 36 | * @i2c_cfg_reg: I2C configuration register offset |
| 37 | * @i2c_cfg_clear_mask: high-speed mode bit clear mask in I2C config register | ||
| 37 | * @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register | 38 | * @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register |
| 38 | * @i2c_mcode_mask: MCODE field mask for I2C config register | 39 | * @i2c_mcode_mask: MCODE field mask for I2C config register |
| 39 | * | 40 | * |
| @@ -52,6 +53,7 @@ struct omap_vc_common { | |||
| 52 | u8 cmd_ret_shift; | 53 | u8 cmd_ret_shift; |
| 53 | u8 cmd_off_shift; | 54 | u8 cmd_off_shift; |
| 54 | u8 i2c_cfg_reg; | 55 | u8 i2c_cfg_reg; |
| 56 | u8 i2c_cfg_clear_mask; | ||
| 55 | u8 i2c_cfg_hsen_mask; | 57 | u8 i2c_cfg_hsen_mask; |
| 56 | u8 i2c_mcode_mask; | 58 | u8 i2c_mcode_mask; |
| 57 | }; | 59 | }; |
diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c index 75bc4aa22b3a..71d74c9172c1 100644 --- a/arch/arm/mach-omap2/vc3xxx_data.c +++ b/arch/arm/mach-omap2/vc3xxx_data.c | |||
| @@ -40,6 +40,7 @@ static struct omap_vc_common omap3_vc_common = { | |||
| 40 | .cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT, | 40 | .cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT, |
| 41 | .cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT, | 41 | .cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT, |
| 42 | .cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT, | 42 | .cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT, |
| 43 | .i2c_cfg_clear_mask = OMAP3430_SREN_MASK | OMAP3430_HSEN_MASK, | ||
| 43 | .i2c_cfg_hsen_mask = OMAP3430_HSEN_MASK, | 44 | .i2c_cfg_hsen_mask = OMAP3430_HSEN_MASK, |
| 44 | .i2c_cfg_reg = OMAP3_PRM_VC_I2C_CFG_OFFSET, | 45 | .i2c_cfg_reg = OMAP3_PRM_VC_I2C_CFG_OFFSET, |
| 45 | .i2c_mcode_mask = OMAP3430_MCODE_MASK, | 46 | .i2c_mcode_mask = OMAP3430_MCODE_MASK, |
diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c index 085e5d6a04fd..2abd5fa8a697 100644 --- a/arch/arm/mach-omap2/vc44xx_data.c +++ b/arch/arm/mach-omap2/vc44xx_data.c | |||
| @@ -42,6 +42,7 @@ static const struct omap_vc_common omap4_vc_common = { | |||
| 42 | .cmd_ret_shift = OMAP4430_RET_SHIFT, | 42 | .cmd_ret_shift = OMAP4430_RET_SHIFT, |
| 43 | .cmd_off_shift = OMAP4430_OFF_SHIFT, | 43 | .cmd_off_shift = OMAP4430_OFF_SHIFT, |
| 44 | .i2c_cfg_reg = OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET, | 44 | .i2c_cfg_reg = OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET, |
| 45 | .i2c_cfg_clear_mask = OMAP4430_SRMODEEN_MASK | OMAP4430_HSMODEEN_MASK, | ||
| 45 | .i2c_cfg_hsen_mask = OMAP4430_HSMODEEN_MASK, | 46 | .i2c_cfg_hsen_mask = OMAP4430_HSMODEEN_MASK, |
| 46 | .i2c_mcode_mask = OMAP4430_HSMCODE_MASK, | 47 | .i2c_mcode_mask = OMAP4430_HSMCODE_MASK, |
| 47 | }; | 48 | }; |
