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-rw-r--r--arch/arm/Kconfig3
-rw-r--r--arch/arm/include/asm/mach/pci.h6
-rw-r--r--arch/arm/include/asm/pci.h7
-rw-r--r--arch/arm/kernel/bios32.c3
-rw-r--r--arch/arm/mach-cns3xxx/pcie.c40
5 files changed, 20 insertions, 39 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 97d07ed60a0b..dcb2e0c55be4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1279,6 +1279,9 @@ config PCI_DOMAINS
1279 bool 1279 bool
1280 depends on PCI 1280 depends on PCI
1281 1281
1282config PCI_DOMAINS_GENERIC
1283 def_bool PCI_DOMAINS
1284
1282config PCI_NANOENGINE 1285config PCI_NANOENGINE
1283 bool "BSE nanoEngine PCI support" 1286 bool "BSE nanoEngine PCI support"
1284 depends on SA1100_NANOENGINE 1287 depends on SA1100_NANOENGINE
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 8292b5f81e23..28b9bb35949e 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -19,9 +19,6 @@ struct pci_bus;
19struct device; 19struct device;
20 20
21struct hw_pci { 21struct hw_pci {
22#ifdef CONFIG_PCI_DOMAINS
23 int domain;
24#endif
25#ifdef CONFIG_PCI_MSI 22#ifdef CONFIG_PCI_MSI
26 struct msi_controller *msi_ctrl; 23 struct msi_controller *msi_ctrl;
27#endif 24#endif
@@ -45,9 +42,6 @@ struct hw_pci {
45 * Per-controller structure 42 * Per-controller structure
46 */ 43 */
47struct pci_sys_data { 44struct pci_sys_data {
48#ifdef CONFIG_PCI_DOMAINS
49 int domain;
50#endif
51#ifdef CONFIG_PCI_MSI 45#ifdef CONFIG_PCI_MSI
52 struct msi_controller *msi_ctrl; 46 struct msi_controller *msi_ctrl;
53#endif 47#endif
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
index 7e95d8535e24..585dc33a7a24 100644
--- a/arch/arm/include/asm/pci.h
+++ b/arch/arm/include/asm/pci.h
@@ -18,13 +18,6 @@ static inline int pcibios_assign_all_busses(void)
18} 18}
19 19
20#ifdef CONFIG_PCI_DOMAINS 20#ifdef CONFIG_PCI_DOMAINS
21static inline int pci_domain_nr(struct pci_bus *bus)
22{
23 struct pci_sys_data *root = bus->sysdata;
24
25 return root->domain;
26}
27
28static inline int pci_proc_domain(struct pci_bus *bus) 21static inline int pci_proc_domain(struct pci_bus *bus)
29{ 22{
30 return pci_domain_nr(bus); 23 return pci_domain_nr(bus);
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index a4effd6d8f2f..ddd75c58b1e8 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -463,9 +463,6 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
463 if (!sys) 463 if (!sys)
464 panic("PCI: unable to allocate sys data!"); 464 panic("PCI: unable to allocate sys data!");
465 465
466#ifdef CONFIG_PCI_DOMAINS
467 sys->domain = hw->domain;
468#endif
469#ifdef CONFIG_PCI_MSI 466#ifdef CONFIG_PCI_MSI
470 sys->msi_ctrl = hw->msi_ctrl; 467 sys->msi_ctrl = hw->msi_ctrl;
471#endif 468#endif
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index 45d6bd09e6ef..f6bf9f623d70 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -30,18 +30,15 @@ struct cns3xxx_pcie {
30 unsigned int irqs[2]; 30 unsigned int irqs[2];
31 struct resource res_io; 31 struct resource res_io;
32 struct resource res_mem; 32 struct resource res_mem;
33 struct hw_pci hw_pci; 33 int port;
34
35 bool linked; 34 bool linked;
36}; 35};
37 36
38static struct cns3xxx_pcie cns3xxx_pcie[]; /* forward decl. */
39
40static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata) 37static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
41{ 38{
42 struct pci_sys_data *root = sysdata; 39 struct pci_sys_data *root = sysdata;
43 40
44 return &cns3xxx_pcie[root->domain]; 41 return root->private_data;
45} 42}
46 43
47static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev) 44static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev)
@@ -192,13 +189,7 @@ static struct cns3xxx_pcie cns3xxx_pcie[] = {
192 .flags = IORESOURCE_MEM, 189 .flags = IORESOURCE_MEM,
193 }, 190 },
194 .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, }, 191 .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
195 .hw_pci = { 192 .port = 0,
196 .domain = 0,
197 .nr_controllers = 1,
198 .ops = &cns3xxx_pcie_ops,
199 .setup = cns3xxx_pci_setup,
200 .map_irq = cns3xxx_pcie_map_irq,
201 },
202 }, 193 },
203 [1] = { 194 [1] = {
204 .host_regs = (void __iomem *)CNS3XXX_PCIE1_HOST_BASE_VIRT, 195 .host_regs = (void __iomem *)CNS3XXX_PCIE1_HOST_BASE_VIRT,
@@ -217,19 +208,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[] = {
217 .flags = IORESOURCE_MEM, 208 .flags = IORESOURCE_MEM,
218 }, 209 },
219 .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, }, 210 .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
220 .hw_pci = { 211 .port = 1,
221 .domain = 1,
222 .nr_controllers = 1,
223 .ops = &cns3xxx_pcie_ops,
224 .setup = cns3xxx_pci_setup,
225 .map_irq = cns3xxx_pcie_map_irq,
226 },
227 }, 212 },
228}; 213};
229 214
230static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci) 215static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
231{ 216{
232 int port = cnspci->hw_pci.domain; 217 int port = cnspci->port;
233 u32 reg; 218 u32 reg;
234 unsigned long time; 219 unsigned long time;
235 220
@@ -260,9 +245,9 @@ static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
260 245
261static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci) 246static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
262{ 247{
263 int port = cnspci->hw_pci.domain; 248 int port = cnspci->port;
264 struct pci_sys_data sd = { 249 struct pci_sys_data sd = {
265 .domain = port, 250 .private_data = cnspci,
266 }; 251 };
267 struct pci_bus bus = { 252 struct pci_bus bus = {
268 .number = 0, 253 .number = 0,
@@ -323,6 +308,14 @@ static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
323void __init cns3xxx_pcie_init_late(void) 308void __init cns3xxx_pcie_init_late(void)
324{ 309{
325 int i; 310 int i;
311 void *private_data;
312 struct hw_pci hw_pci = {
313 .nr_controllers = 1,
314 .ops = &cns3xxx_pcie_ops,
315 .setup = cns3xxx_pci_setup,
316 .map_irq = cns3xxx_pcie_map_irq,
317 .private_data = &private_data,
318 };
326 319
327 pcibios_min_io = 0; 320 pcibios_min_io = 0;
328 pcibios_min_mem = 0; 321 pcibios_min_mem = 0;
@@ -335,7 +328,8 @@ void __init cns3xxx_pcie_init_late(void)
335 cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i)); 328 cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
336 cns3xxx_pcie_check_link(&cns3xxx_pcie[i]); 329 cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
337 cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]); 330 cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
338 pci_common_init(&cns3xxx_pcie[i].hw_pci); 331 private_data = &cns3xxx_pcie[i];
332 pci_common_init(&hw_pci);
339 } 333 }
340 334
341 pci_assign_unassigned_resources(); 335 pci_assign_unassigned_resources();