617 files changed, 11445 insertions, 5657 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 664e918e2624..054ead960f98 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2,6 +2,7 @@
 config ARM
         bool
         default y
+        select ARCH_32BIT_OFF_T
         select ARCH_CLOCKSOURCE_DATA
         select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC
         select ARCH_HAS_DEBUG_VIRTUAL if MMU
@@ -12,9 +13,11 @@ config ARM
         select ARCH_HAS_MEMBARRIER_SYNC_CORE
         select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
         select ARCH_HAS_PHYS_TO_DMA
+        select ARCH_HAS_SETUP_DMA_OPS
         select ARCH_HAS_SET_MEMORY
         select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
         select ARCH_HAS_STRICT_MODULE_RWX if MMU
+        select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
         select ARCH_HAVE_CUSTOM_GPIO_H
         select ARCH_HAS_GCOV_PROFILE_ALL
@@ -30,6 +33,7 @@ config ARM
         select CLONE_BACKWARDS
         select CPU_PM if SUSPEND || CPU_IDLE
         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
+        select DMA_DECLARE_COHERENT
         select DMA_REMAP if MMU
         select EDAC_SUPPORT
         select EDAC_ATOMIC_SCRUB
@@ -72,7 +76,6 @@ config ARM
         select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL
         select HAVE_FUNCTION_TRACER if !XIP_KERNEL
         select HAVE_GCC_PLUGINS
-        select HAVE_GENERIC_DMA_COHERENT
         select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
         select HAVE_IDE if PCI || ISA || PCMCIA
         select HAVE_IRQ_TIME_ACCOUNTING
@@ -101,7 +104,6 @@ config ARM
         select MODULES_USE_ELF_REL
         select NEED_DMA_MAP_STATE
         select OF_EARLY_FLATTREE if OF
-        select OF_RESERVED_MEM if OF
         select OLD_SIGACTION
         select OLD_SIGSUSPEND3
         select PCI_SYSCALL if PCI
@@ -589,11 +591,13 @@ config ARCH_DAVINCI
         select GENERIC_ALLOCATOR
         select GENERIC_CLOCKEVENTS
         select GENERIC_IRQ_CHIP
+        select GENERIC_IRQ_MULTI_HANDLER
         select GPIOLIB
         select HAVE_IDE
         select PM_GENERIC_DOMAINS if PM
         select PM_GENERIC_DOMAINS_OF if PM && OF
         select RESET_CONTROLLER
+        select SPARSE_IRQ
         select USE_OF
         select ZONE_DMA
         help
@@ -750,6 +754,8 @@ source "arch/arm/mach-mediatek/Kconfig"
 
 source "arch/arm/mach-meson/Kconfig"
 
+source "arch/arm/mach-milbeaut/Kconfig"
+
 source "arch/arm/mach-mmp/Kconfig"
 
 source "arch/arm/mach-moxart/Kconfig"
@@ -1304,7 +1310,7 @@ config SCHED_SMT
 config HAVE_ARM_SCU
         bool
         help
-          This option enables support for the ARM system coherency unit
+          This option enables support for the ARM snoop control unit
 
 config HAVE_ARM_ARCH_TIMER
         bool "Architected timer support"
@@ -1316,7 +1322,6 @@ config HAVE_ARM_ARCH_TIMER
 
 config HAVE_ARM_TWD
         bool
-        select TIMER_OF if OF
         help
           This options enables support for the ARM timer and watchdog unit
 
@@ -1400,6 +1405,7 @@ config NR_CPUS
 config HOTPLUG_CPU
         bool "Support for hot-pluggable CPUs"
         depends on SMP
+        select GENERIC_IRQ_MIGRATION
         help
           Say Y here to experiment with turning CPUs off and on.  CPUs
           can be controlled through /sys/devices/system/cpu.
diff --git a/arch/arm/Kconfig-nommu b/arch/arm/Kconfig-nommu
index 1168a03c8525..36c80d3dd93f 100644
--- a/arch/arm/Kconfig-nommu
+++ b/arch/arm/Kconfig-nommu
@@ -20,10 +20,12 @@ config DRAM_SIZE
 
 config FLASH_MEM_BASE
         hex 'FLASH Base Address' if SET_MEM_PARAM
+        depends on CPU_ARM740T || CPU_ARM946E || CPU_ARM940T
         default 0x00400000
 
 config FLASH_SIZE
         hex 'FLASH Size' if SET_MEM_PARAM
+        depends on CPU_ARM740T || CPU_ARM946E || CPU_ARM940T
         default 0x00400000
 
 config PROCESSOR_ID
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 9db3c584b2cb..807a7d06c2a0 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -10,7 +10,7 @@
 #
 # Copyright (C) 1995-2001 by Russell King
 
-LDFLAGS_vmlinux :=-p --no-undefined -X --pic-veneer
+LDFLAGS_vmlinux := --no-undefined -X --pic-veneer
 ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
 LDFLAGS_vmlinux += --be8
 KBUILD_LDFLAGS_MODULE   += --be8
@@ -190,6 +190,7 @@ machine-$(CONFIG_ARCH_MV78XX0)		+= mv78xx0
 machine-$(CONFIG_ARCH_MVEBU)            += mvebu
 machine-$(CONFIG_ARCH_MXC)              += imx
 machine-$(CONFIG_ARCH_MEDIATEK)         += mediatek
+machine-$(CONFIG_ARCH_MILBEAUT)         += milbeaut
 machine-$(CONFIG_ARCH_MXS)              += mxs
 machine-$(CONFIG_ARCH_NETX)             += netx
 machine-$(CONFIG_ARCH_NOMADIK)          += nomadik
diff --git a/arch/arm/boot/bootp/Makefile b/arch/arm/boot/bootp/Makefile
index 83e1a076a5d6..981a8d03f064 100644
--- a/arch/arm/boot/bootp/Makefile
+++ b/arch/arm/boot/bootp/Makefile
@@ -8,7 +8,7 @@
 
 GCOV_PROFILE    := n
 
-LDFLAGS_bootp   :=-p --no-undefined -X \
+LDFLAGS_bootp   := --no-undefined -X \
                  --defsym initrd_phys=$(INITRD_PHYS) \
                  --defsym params_phys=$(PARAMS_PHYS) -T
 AFLAGS_initrd.o :=-DINITRD=\"$(INITRD)\"
diff --git a/arch/arm/boot/bootp/init.S b/arch/arm/boot/bootp/init.S
index 78b508075161..142927e5f485 100644
--- a/arch/arm/boot/bootp/init.S
+++ b/arch/arm/boot/bootp/init.S
@@ -44,7 +44,7 @@ _start:		add	lr, pc, #-0x8		@ lr = current load addr
  */
                 movne   r10, #0                 @ terminator
                 movne   r4, #2                  @ Size of this entry (2 words)
-                stmneia r9, {r4, r5, r10}       @ Size, ATAG_CORE, terminator
+                stmiane r9, {r4, r5, r10}       @ Size, ATAG_CORE, terminator
 
 /*
  * find the end of the tag list, and then add an INITRD tag on the end.
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 6114ae6ea466..9219389bbe61 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -132,8 +132,6 @@ endif
 ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
 LDFLAGS_vmlinux += --be8
 endif
-# ?
-LDFLAGS_vmlinux += -p
 # Report unresolved symbol references
 LDFLAGS_vmlinux += --no-undefined
 # Delete all temporary local symbols
diff --git a/arch/arm/boot/compressed/ll_char_wr.S b/arch/arm/boot/compressed/ll_char_wr.S
index 8517c8606b4a..b1dcdb9f4030 100644
--- a/arch/arm/boot/compressed/ll_char_wr.S
+++ b/arch/arm/boot/compressed/ll_char_wr.S
@@ -75,7 +75,7 @@ Lrow4bpplp:
         tst     r1, #7                          @ avoid using r7 directly after
         str     r7, [r0, -r5]!
         subne   r1, r1, #1
-        ldrneb  r7, [r6, r1]
+        ldrbne  r7, [r6, r1]
         bne     Lrow4bpplp
         ldmfd   sp!, {r4 - r7, pc}
 
@@ -103,7 +103,7 @@ Lrow8bpplp:
         sub     r0, r0, r5                      @ avoid ip
         stmia   r0, {r4, ip}
         subne   r1, r1, #1
-        ldrneb  r7, [r6, r1]
+        ldrbne  r7, [r6, r1]
         bne     Lrow8bpplp
         ldmfd   sp!, {r4 - r7, pc}
 
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index bd40148a15b2..f4f5aeaf3298 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -79,6 +79,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \
         bcm2835-rpi-a-plus.dtb \
         bcm2835-rpi-cm1-io1.dtb \
         bcm2836-rpi-2-b.dtb \
+        bcm2837-rpi-3-a-plus.dtb \
         bcm2837-rpi-3-b.dtb \
         bcm2837-rpi-3-b-plus.dtb \
         bcm2837-rpi-cm3-io3.dtb \
@@ -115,6 +116,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
         bcm47094-luxul-xwr-3100.dtb \
         bcm47094-luxul-xwr-3150-v1.dtb \
         bcm47094-netgear-r8500.dtb \
+        bcm47094-phicomm-k3.dtb \
         bcm94708.dtb \
         bcm94709.dtb \
         bcm953012er.dtb \
@@ -313,7 +315,8 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \
 dtb-$(CONFIG_ARCH_LPC18XX) += \
         lpc4337-ciaa.dtb \
         lpc4350-hitex-eval.dtb \
-        lpc4357-ea4357-devkit.dtb
+        lpc4357-ea4357-devkit.dtb \
+        lpc4357-myd-lpc4357.dtb
 dtb-$(CONFIG_ARCH_LPC32XX) += \
         lpc3250-ea3250.dtb \
         lpc3250-phy3250.dtb
@@ -445,6 +448,9 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
         imx6dl-wandboard.dtb \
         imx6dl-wandboard-revb1.dtb \
         imx6dl-wandboard-revd1.dtb \
+        imx6dl-yapp4-draco.dtb \
+        imx6dl-yapp4-hydra.dtb \
+        imx6dl-yapp4-ursa.dtb \
         imx6q-apalis-eval.dtb \
         imx6q-apalis-ixora.dtb \
         imx6q-apalis-ixora-v1.1.dtb \
@@ -561,6 +567,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
         imx6ul-opos6uldev.dtb \
         imx6ul-pico-hobbit.dtb \
         imx6ul-pico-pi.dtb \
+        imx6ul-phytec-phyboard-segin-full.dtb \
         imx6ul-tx6ul-0010.dtb \
         imx6ul-tx6ul-0011.dtb \
         imx6ul-tx6ul-mainboard.dtb \
@@ -599,6 +606,7 @@ dtb-$(CONFIG_SOC_VF610) += \
         vf610-zii-dev-rev-b.dtb \
         vf610-zii-dev-rev-c.dtb \
         vf610-zii-scu4-aib.dtb \
+        vf610-zii-ssmb-dtu.dtb \
         vf610-zii-ssmb-spu3.dtb
 dtb-$(CONFIG_ARCH_MXS) += \
         imx23-evk.dtb \
@@ -700,6 +708,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
         omap3-thunder.dtb \
         omap3-zoom3.dtb
 dtb-$(CONFIG_SOC_TI81XX) += \
+        am3874-iceboard.dtb \
         dm8148-evm.dtb \
         dm8148-t410.dtb \
         dm8168-evm.dtb \
@@ -719,6 +728,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \
         am335x-cm-t335.dtb \
         am335x-evm.dtb \
         am335x-evmsk.dtb \
+        am335x-guardian.dtb \
         am335x-icev2.dtb \
         am335x-lxm.dtb \
         am335x-moxa-uc-2101.dtb \
@@ -843,6 +853,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
         r7s72100-genmai.dtb \
         r7s72100-gr-peach.dtb \
         r7s72100-rskrza1.dtb \
+        r7s9210-rza2mevb.dtb \
         r8a73a4-ape6evm.dtb \
         r8a7740-armadillo800eva.dtb \
         r8a7743-iwg20d-q7.dtb \
@@ -868,6 +879,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
         r9a06g032-rzn1d400-db.dtb \
         sh73a0-kzm9g.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+        rv1108-elgin-r1.dtb \
         rv1108-evb.dtb \
         rk3036-evb.dtb \
         rk3036-kylin.dtb \
@@ -919,6 +931,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
         socfpga_arria10_socdk_nand.dtb \
         socfpga_arria10_socdk_qspi.dtb \
         socfpga_arria10_socdk_sdmmc.dtb \
+        socfpga_cyclone5_chameleon96.dtb \
         socfpga_cyclone5_mcvevk.dtb \
         socfpga_cyclone5_socdk.dtb \
         socfpga_cyclone5_de0_nano_soc.dtb \
@@ -1233,6 +1246,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
         mt7623n-bananapi-bpi-r2.dtb \
         mt8127-moose.dtb \
         mt8135-evbp1.dtb
+dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb
 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
 dtb-$(CONFIG_ARCH_ASPEED) += \
         aspeed-ast2500-evb.dtb \
diff --git a/arch/arm/boot/dts/alphascale-asm9260.dtsi b/arch/arm/boot/dts/alphascale-asm9260.dtsi
index 907fc7bfc418..2ce6038536fd 100644
--- a/arch/arm/boot/dts/alphascale-asm9260.dtsi
+++ b/arch/arm/boot/dts/alphascale-asm9260.dtsi
@@ -4,10 +4,11 @@
  * Licensed under the X11 license or the GPL v2 (or later)
  */
 
-#include "skeleton.dtsi"
 #include <dt-bindings/clock/alphascale,asm9260.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         interrupt-parent = <&icoll>;
 
         memory {
diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi
index 731df7a8c4e6..d3036ea823d1 100644
--- a/arch/arm/boot/dts/alpine.dtsi
+++ b/arch/arm/boot/dts/alpine.dtsi
@@ -25,12 +25,18 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton64.dtsi"
 
 / {
+        #address-cells = <2>;
+        #size-cells = <2>;
         /* SOC compatibility */
         compatible = "al,alpine";
 
+        memory {
+                device_type = "memory";
+                reg = <0 0 0 0>;
+        };
+
         /* CPU Configuration */
         cpus {
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts
index 75de1e723303..50dcf1290ac6 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir2110.dts
@@ -72,7 +72,3 @@
         dual_emac_res_vlan = <2>;
         phy-handle = <&phy1>;
 };
-
-&phy_sel {
-        rmii-clock-ext = <1>;
-};
diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/am335x-baltos-ir3220.dts
index 1b215c425c57..f3f1abd26470 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir3220.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir3220.dts
@@ -114,7 +114,3 @@
         dual_emac_res_vlan = <2>;
         phy-handle = <&phy1>;
 };
-
-&phy_sel {
-        rmii-clock-ext = <1>;
-};
diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts
index 832ead864dc5..42f473f0ed77 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts
@@ -133,10 +133,6 @@
         phy-handle = <&phy1>;
 };
 
-&phy_sel {
-        rmii-clock-ext = <1>;
-};
-
 &dcan1 {
         pinctrl-names = "default";
         pinctrl-0 = <&dcan1_pins>;
diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts
index 9c2a947aacf5..bffa5dce54ec 100644
--- a/arch/arm/boot/dts/am335x-chiliboard.dts
+++ b/arch/arm/boot/dts/am335x-chiliboard.dts
@@ -14,6 +14,10 @@
         compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom",
                      "ti,am33xx";
 
+        chosen {
+                stdout-path = &uart0;
+        };
+
         leds {
                 compatible = "gpio-leds";
                 pinctrl-names = "default";
@@ -151,10 +155,6 @@
         phy-mode = "rmii";
 };
 
-&phy_sel {
-        rmii-clock-ext;
-};
-
 /* USB */
 &usb {
         status = "okay";
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index b67f5fee1469..dce5be5df97b 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -729,7 +729,7 @@
 
 &cpsw_emac0 {
         phy-handle = <&ethphy0>;
-        phy-mode = "rgmii-txid";
+        phy-mode = "rgmii-id";
 };
 
 &tscadc {
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 172c0224e7f6..b128998097ce 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -651,13 +651,13 @@
 
 &cpsw_emac0 {
         phy-handle = <&ethphy0>;
-        phy-mode = "rgmii-txid";
+        phy-mode = "rgmii-id";
         dual_emac_res_vlan = <1>;
 };
 
 &cpsw_emac1 {
         phy-handle = <&ethphy1>;
-        phy-mode = "rgmii-txid";
+        phy-mode = "rgmii-id";
         dual_emac_res_vlan = <2>;
 };
 
diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts
new file mode 100644
index 000000000000..c9611ea4b884
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-guardian.dts
@@ -0,0 +1,511 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Robert Bosch Power Tools GmbH
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+        model = "Bosch AM335x Guardian";
+        compatible = "bosch,am335x-guardian", "ti,am33xx";
+
+        chosen {
+                stdout-path = &uart0;
+                tick-timer = &timer2;
+        };
+
+        cpus {
+                cpu@0 {
+                        cpu0-supply = <&dcdc2_reg>;
+                };
+        };
+
+        memory@80000000 {
+                device_type = "memory";
+                reg = <0x80000000 0x10000000>; /* 256 MB */
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&gpio_keys_pins>;
+
+                button21 {
+                        label = "guardian-power-button";
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio2 21 0>;
+                        wakeup-source;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&leds_pins>;
+
+                led1 {
+                        label = "green:heartbeat";
+                        gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                        default-state = "off";
+                };
+
+                led2 {
+                        label = "green:mmc0";
+                        gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "mmc0";
+                        default-state = "off";
+                };
+        };
+
+        panel {
+                compatible = "ti,tilcdc,panel";
+                pinctrl-names = "default", "sleep";
+                pinctrl-0 = <&lcd_pins_default &lcd_disen_pins>;
+                pinctrl-1 = <&lcd_pins_sleep>;
+
+                display-timings {
+                        320x240 {
+                                hactive         = <320>;
+                                vactive         = <240>;
+                                hback-porch     = <68>;
+                                hfront-porch    = <20>;
+                                hsync-len       = <1>;
+                                vback-porch     = <18>;
+                                vfront-porch    = <4>;
+                                vsync-len       = <1>;
+                                clock-frequency = <9000000>;
+                                hsync-active    = <0>;
+                                vsync-active    = <0>;
+                        };
+                };
+                panel-info {
+                        ac-bias           = <255>;
+                        ac-bias-intrpt    = <0>;
+                        dma-burst-sz      = <16>;
+                        bpp               = <24>;
+                        bus-width         = <16>;
+                        fdd               = <0x80>;
+                        sync-edge         = <0>;
+                        sync-ctrl         = <1>;
+                        raster-order      = <0>;
+                        fifo-th           = <0>;
+                };
+
+        };
+
+        pwm7: dmtimer-pwm {
+                compatible = "ti,omap-dmtimer-pwm";
+                ti,timers = <&timer7>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&dmtimer7_pins>;
+        };
+
+        vmmcsd_fixed: regulator-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "vmmcsd_fixed";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+};
+
+&cppi41dma  {
+        status = "okay";
+};
+
+&elm {
+        status = "okay";
+};
+
+&gpmc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&nandflash_pins>;
+        ranges = <0 0 0x08000000 0x1000000>;  /* CS0: 16MB for NAND */
+        status = "okay";
+
+        nand@0,0 {
+                compatible = "ti,omap2-nand";
+                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+                interrupt-parent = <&gpmc>;
+                interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+                             <1 IRQ_TYPE_NONE>; /* termcount */
+                rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
+                ti,nand-ecc-opt = "bch16";
+                ti,elm-id = <&elm>;
+                nand-bus-width = <8>;
+                gpmc,device-width = <1>;
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <44>;
+                gpmc,cs-wr-off-ns = <44>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <34>;
+                gpmc,adv-wr-off-ns = <44>;
+                gpmc,we-on-ns = <0>;
+                gpmc,we-off-ns = <40>;
+                gpmc,oe-on-ns = <0>;
+                gpmc,oe-off-ns = <54>;
+                gpmc,access-ns = <64>;
+                gpmc,rd-cycle-ns = <82>;
+                gpmc,wr-cycle-ns = <82>;
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-delay-ns = <0>;
+                gpmc,clk-activation-ns = <0>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+
+                /*
+                 * MTD partition table
+                 *
+                 * All SPL-* partitions are sized to minimal length which can
+                 * be independently programmable. For NAND flash this is equal
+                 * to size of erase-block.
+                 */
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                partition@0 {
+                        label = "SPL";
+                        reg = <0x0 0x40000>;
+                };
+
+                partition@1 {
+                        label = "SPL.backup1";
+                        reg = <0x40000  0x40000>;
+                };
+
+                partition@2 {
+                        label = "SPL.backup2";
+                        reg = <0x80000  0x40000>;
+                };
+
+                partition@3 {
+                        label = "SPL.backup3";
+                        reg = <0xc0000  0x40000>;
+                };
+
+                partition@4 {
+                        label = "u-boot";
+                        reg = <0x100000 0x100000>;
+                };
+
+                partition@5 {
+                        label = "u-boot.backup1";
+                        reg = <0x200000 0x100000>;
+                };
+
+                partition@6 {
+                        label = "u-boot-env";
+                        reg = <0x300000 0x40000>;
+                };
+
+                partition@7 {
+                        label = "u-boot-env.backup1";
+                        reg = <0x340000 0x40000>;
+                };
+
+                partition@8 {
+                        label = "UBI";
+                        reg = <0x380000 0x1fc80000>;
+                };
+        };
+};
+
+&i2c0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_pins>;
+        clock-frequency = <400000>;
+        status = "okay";
+
+        tps: tps@24 {
+                reg = <0x24>;
+        };
+};
+
+&lcdc {
+        blue-and-red-wiring = "crossed";
+        status = "okay";
+};
+
+&mmc1 {
+        bus-width = <0x4>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+        vmmc-supply = <&vmmcsd_fixed>;
+        status = "okay";
+};
+
+&rtc {
+        clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
+        clock-names = "ext-clk", "int-clk";
+        system-power-controller;
+};
+
+&spi0 {
+        ti,pindir-d0-out-d1-in;
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi0_pins>;
+        status = "okay";
+};
+
+#include "tps65217.dtsi"
+
+&tps {
+        ti,pmic-shutdown-controller;
+        interrupt-parent = <&intc>;
+        interrupts = <7>; /* NMI */
+
+        backlight {
+                isel = <1>;  /* 1 - ISET1, 2 ISET2 */
+                fdim = <100>; /* TPS65217_BL_FDIM_100HZ */
+                default-brightness = <100>;
+        };
+
+        regulators {
+                dcdc1_reg: regulator@0 {
+                        regulator-name = "vdds_dpr";
+                        regulator-always-on;
+                };
+
+                dcdc2_reg: regulator@1 {
+                        regulator-name = "vdd_mpu";
+                        regulator-min-microvolt = <925000>;
+                        regulator-max-microvolt = <1351500>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                dcdc3_reg: regulator@2 {
+                        regulator-name = "vdd_core";
+                        regulator-min-microvolt = <925000>;
+                        regulator-max-microvolt = <1150000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                ldo1_reg: regulator@3 {
+                        regulator-name = "vio,vrtc,vdds";
+                        regulator-always-on;
+                };
+
+                ldo2_reg: regulator@4 {
+                        regulator-name = "vdd_3v3aux";
+                        regulator-always-on;
+                };
+
+                ldo3_reg: regulator@5 {
+                        regulator-name = "vdd_1v8";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-always-on;
+                };
+
+                ldo4_reg: regulator@6 {
+                        regulator-name = "vdd_3v3a";
+                        regulator-always-on;
+                };
+        };
+};
+
+&tscadc {
+        status = "okay";
+
+        adc {
+                ti,adc-channels = <0 1 2 3 4 5 6>;
+        };
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins>;
+        status = "okay";
+};
+
+&usb {
+        status = "okay";
+};
+
+&usb_ctrl_mod {
+        status = "okay";
+};
+
+&usb0 {
+        dr_mode = "peripheral";
+        status = "okay";
+};
+
+&usb0_phy {
+        status = "okay";
+};
+
+&usb1 {
+        dr_mode = "host";
+        status = "okay";
+};
+
+&usb1_phy {
+        status = "okay";
+};
+
+&am33xx_pinmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&clkout2_pin &gpio_pins>;
+
+        clkout2_pin: pinmux_clkout2_pin {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)
+                >;
+        };
+
+        dmtimer7_pins: pinmux_dmtimer7_pins {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5)
+                >;
+        };
+
+        gpio_keys_pins: pinmux_gpio_keys_pins {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7)
+                >;
+        };
+
+        gpio_pins: pinmux_gpio_pins {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7)
+                        AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7)
+                >;
+        };
+
+        i2c0_pins: pinmux_i2c0_pins {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)
+                        AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)
+                >;
+        };
+
+        lcd_disen_pins: pinmux_lcd_disen_pins {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7)
+                >;
+        };
+
+        lcd_pins_default: pinmux_lcd_pins_default {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+                        AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+                        AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+                        AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+                        AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+                        AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+                        AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+                        AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
+                        AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+                        AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+                        AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+                        AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+                        AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+                        AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+                        AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+                        AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+                        AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+                        AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+                        AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+                        AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+                        AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+                        AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+                        AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+                        AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+                        AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+                        AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+                        AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+                        AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
+                >;
+        };
+
+        lcd_pins_sleep: pinmux_lcd_pins_sleep {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+                        AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+                        AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+                        AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+                        AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+                        AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+                        AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+                        AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+                        AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+                        AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+                        AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+                        AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+                        AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+                        AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+                        AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+                        AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
+                        AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
+                        AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
+                        AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
+                        AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
+                >;
+        };
+
+        leds_pins: pinmux_leds_pins {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7)
+                        AM33XX_IOPAD(0x86c, PIN_OUTPUT | MUX_MODE7)
+                >;
+        };
+
+        mmc1_pins: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)
+                        AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)
+                        AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)
+                        AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)
+                        AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)
+                        AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)
+                        AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7)
+                >;
+        };
+
+        spi0_pins: pinmux_spi0_pins {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+                        AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                        AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)
+                        AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0)
+                >;
+        };
+
+        uart0_pins: pinmux_uart0_pins {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)
+                        AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+                >;
+        };
+
+        nandflash_pins: pinmux_nandflash_pins {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0)
+                        AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0)
+                        AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0)
+                        AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0)
+                        AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0)
+                        AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0)
+                        AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0)
+                        AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0)
+                        AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0)
+                        AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0)
+                        AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)
+                        AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)
+                        AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)
+                        AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)
+                        AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts
index f2005ecca74f..9ac775c71072 100644
--- a/arch/arm/boot/dts/am335x-icev2.dts
+++ b/arch/arm/boot/dts/am335x-icev2.dts
@@ -484,10 +484,6 @@
         dual_emac;
 };
 
-&phy_sel {
-        rmii-clock-ext;
-};
-
 &davinci_mdio {
         pinctrl-names = "default", "sleep";
         pinctrl-0 = <&davinci_mdio_default>;
diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi
index 55b4c94cfafb..cbd22f25de95 100644
--- a/arch/arm/boot/dts/am335x-igep0033.dtsi
+++ b/arch/arm/boot/dts/am335x-igep0033.dtsi
@@ -123,10 +123,6 @@
         phy-mode = "rmii";
 };
 
-&phy_sel {
-        rmii-clock-ext;
-};
-
 &elm {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts
index 481edcfaf121..d0e8e720a4d6 100644
--- a/arch/arm/boot/dts/am335x-lxm.dts
+++ b/arch/arm/boot/dts/am335x-lxm.dts
@@ -328,10 +328,6 @@
         dual_emac_res_vlan = <3>;
 };
 
-&phy_sel {
-        rmii-clock-ext;
-};
-
 &mac {
         pinctrl-names = "default", "sleep";
         pinctrl-0 = <&cpsw_default>;
diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
index 14f781953475..cb5913a69837 100644
--- a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
+++ b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
@@ -159,11 +159,6 @@
         status = "okay";
 };
 
-&phy_sel {
-        reg= <0x44e10650 0xf5>;
-        rmii-clock-ext;
-};
-
 &sham {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts
index 5a58efc0c874..e562ce40f290 100644
--- a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts
+++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts
@@ -446,11 +446,6 @@
         dual_emac_res_vlan = <2>;
 };
 
-&phy_sel {
-        reg= <0x44e10650 0xf5>;
-        rmii-clock-ext;
-};
-
 &sham {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi
index 428a25e952b0..015adb626b03 100644
--- a/arch/arm/boot/dts/am335x-phycore-som.dtsi
+++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi
@@ -100,10 +100,6 @@
         status = "okay";
 };
 
-&phy_sel {
-        rmii-clock-ext;
-};
-
 /* I2C Busses */
 &am33xx_pinmux {
         i2c0_pins: pinmux_i2c0 {
diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts
index d0fd68873689..bfbe27a80006 100644
--- a/arch/arm/boot/dts/am335x-shc.dts
+++ b/arch/arm/boot/dts/am335x-shc.dts
@@ -1,11 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * support for the bosch am335x based shc c3 board
  *
  * Copyright, C) 2015 Heiko Schocher <hs@denx.de>
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 /dts-v1/;
 
@@ -215,7 +213,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&mmc1_pins>;
         bus-width = <0x4>;
-        cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+        cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
         cd-inverted;
         max-frequency = <26000000>;
         vmmc-supply = <&vmmcsd_fixed>;
diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi
index 7b818d9d2eab..f459ec316a22 100644
--- a/arch/arm/boot/dts/am33xx-l4.dtsi
+++ b/arch/arm/boot/dts/am33xx-l4.dtsi
@@ -279,17 +279,9 @@
                                 #pinctrl-cells = <1>;
                                 ranges = <0 0 0x2000>;
 
-                                phy_sel: cpsw-phy-sel@650 {
-                                        compatible = "ti,am3352-cpsw-phy-sel";
-                                        reg= <0x650 0x4>;
-                                        reg-names = "gmii-sel";
-                                };
-
                                 am33xx_pinmux: pinmux@800 {
                                         compatible = "pinctrl-single";
                                         reg = <0x800 0x238>;
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
                                         #pinctrl-cells = <1>;
                                         pinctrl-single,register-width = <32>;
                                         pinctrl-single,function-mask = <0x7f>;
@@ -302,6 +294,12 @@
                                         #size-cells = <1>;
                                         ranges = <0 0 0x800>;
 
+                                        phy_gmii_sel: phy-gmii-sel {
+                                                compatible = "ti,am3352-phy-gmii-sel";
+                                                reg = <0x650 0x4>;
+                                                #phy-cells = <2>;
+                                        };
+
                                         scm_clocks: clocks {
                                                 #address-cells = <1>;
                                                 #size-cells = <0>;
@@ -717,7 +715,6 @@
                                 interrupts = <40 41 42 43>;
                                 ranges = <0 0 0x8000>;
                                 syscon = <&scm_conf>;
-                                cpsw-phy-sel = <&phy_sel>;
                                 status = "disabled";
 
                                 davinci_mdio: mdio@1000 {
@@ -733,11 +730,13 @@
                                 cpsw_emac0: slave@200 {
                                         /* Filled in by U-Boot */
                                         mac-address = [ 00 00 00 00 00 00 ];
+                                        phys = <&phy_gmii_sel 1 1>;
                                 };
 
                                 cpsw_emac1: slave@300 {
                                         /* Filled in by U-Boot */
                                         mac-address = [ 00 00 00 00 00 00 ];
+                                        phys = <&phy_gmii_sel 2 1>;
                                 };
                         };
                 };
diff --git a/arch/arm/boot/dts/am3874-iceboard.dts b/arch/arm/boot/dts/am3874-iceboard.dts
new file mode 100644
index 000000000000..883fb85135d4
--- /dev/null
+++ b/arch/arm/boot/dts/am3874-iceboard.dts
@@ -0,0 +1,496 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device tree for Winterland IceBoard
+ *
+ * http://mcgillcosmology.com
+ * http://threespeedlogic.com
+ *
+ * This is an ARM + FPGA instrumentation board used at telescopes in
+ * Antarctica (the South Pole Telescope), Chile (POLARBEAR), and at the DRAO
+ * observatory in British Columbia (CHIME).
+ *
+ * Copyright (c) 2019 Three-Speed Logic, Inc. <gsmecher@threespeedlogic.com>
+ */
+
+/dts-v1/;
+
+#include "dm814x.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+        model = "Winterland IceBoard";
+        compatible = "ti,dm8148", "ti,dm814";
+
+        chosen {
+                stdout-path = "serial1:115200n8";
+                bootargs = "earlycon";
+        };
+
+        memory@80000000 {
+                device_type = "memory";
+                reg = <0x80000000 0x40000000>;  /* 1 GB */
+        };
+
+        vmmcsd_fixed: fixedregulator0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vmmcsd_fixed";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+};
+
+/* The MAC provides internal delay for the transmit path ONLY, which is enabled
+ * provided no -id/-txid/-rxid suffix is provided to "phy-mode".
+ *
+ * The receive path is delayed at the PHY. The recommended register settings
+ * are 0xf0 for the control bits, and 0x7777 for the data bits. However, the
+ * conversion code in the kernel lies: the PHY's registers are 120 ps per tap,
+ * and the kernel assumes 200 ps per tap. So we have fudged the numbers here to
+ * obtain the correct register settings.
+ */
+&mac { dual_emac = <1>; };
+&cpsw_emac0 {
+        phy-handle = <&ethphy0>;
+        phy-mode = "rgmii";
+        dual_emac_res_vlan = <1>;
+};
+&cpsw_emac1 {
+        phy-handle = <&ethphy1>;
+        phy-mode = "rgmii";
+        dual_emac_res_vlan = <2>;
+};
+
+&davinci_mdio {
+        ethphy0: ethernet-phy@0 {
+                reg = <0x2>;
+
+                rxc-skew-ps = <3000>;
+                rxdv-skew-ps = <0>;
+
+                rxd3-skew-ps = <0>;
+                rxd2-skew-ps = <0>;
+                rxd1-skew-ps = <0>;
+                rxd0-skew-ps = <0>;
+
+                phy-reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+        };
+
+        ethphy1: ethernet-phy@1 {
+                reg = <0x1>;
+
+                rxc-skew-ps = <3000>;
+                rxdv-skew-ps = <0>;
+
+                rxd3-skew-ps = <0>;
+                rxd2-skew-ps = <0>;
+                rxd1-skew-ps = <0>;
+                rxd0-skew-ps = <0>;
+
+                phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+        };
+};
+
+&mmc1 { status = "disabled"; };
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins>;
+        vmmc-supply = <&vmmcsd_fixed>;
+        bus-width = <4>;
+};
+&mmc3 { status = "disabled"; };
+
+&i2c1 {
+        /* Most I2C activity happens through this port, with the sole exception
+         * of the backplane. Since there are multiply assigned addresses, the
+         * "i2c-mux-idle-disconnect" is important.
+         */
+
+        pca9548@70 {
+                compatible = "nxp,pca9548";
+                reg = <0x70>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                i2c@0 {
+                        /* FMC A */
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0>;
+                        i2c-mux-idle-disconnect;
+                };
+
+                i2c@1 {
+                        /* FMC B */
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <1>;
+                        i2c-mux-idle-disconnect;
+                };
+
+                i2c@2 {
+                        /* QSFP A */
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <2>;
+                        i2c-mux-idle-disconnect;
+                };
+
+                i2c@3 {
+                        /* QSFP B */
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <3>;
+                        i2c-mux-idle-disconnect;
+                };
+
+                i2c@4 {
+                        /* SFP */
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <4>;
+                        i2c-mux-idle-disconnect;
+                };
+
+                i2c@5 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <5>;
+                        i2c-mux-idle-disconnect;
+
+                        ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; };
+                        ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; };
+                        ina230@42 { compatible = "ti,ina230"; reg = <0x42>; shunt-resistor = <5000>; };
+
+                        ina230@44 { compatible = "ti,ina230"; reg = <0x44>; shunt-resistor = <5000>; };
+                        ina230@45 { compatible = "ti,ina230"; reg = <0x45>; shunt-resistor = <5000>; };
+                        ina230@46 { compatible = "ti,ina230"; reg = <0x46>; shunt-resistor = <5000>; };
+
+                        ina230@47 { compatible = "ti,ina230"; reg = <0x47>; shunt-resistor = <5500>; };
+                        ina230@48 { compatible = "ti,ina230"; reg = <0x48>; shunt-resistor = <2360>; };
+                        ina230@49 { compatible = "ti,ina230"; reg = <0x49>; shunt-resistor = <2360>; };
+                        ina230@43 { compatible = "ti,ina230"; reg = <0x43>; shunt-resistor = <2360>; };
+                        ina230@4b { compatible = "ti,ina230"; reg = <0x4b>; shunt-resistor = <5500>; };
+                        ina230@4c { compatible = "ti,ina230"; reg = <0x4c>; shunt-resistor = <2360>; };
+                        ina230@4d { compatible = "ti,ina230"; reg = <0x4d>; shunt-resistor = <770>; };
+                        ina230@4e { compatible = "ti,ina230"; reg = <0x4e>; shunt-resistor = <770>; };
+                        ina230@4f { compatible = "ti,ina230"; reg = <0x4f>; shunt-resistor = <770>; };
+                };
+
+                i2c@6 {
+                        /* Backplane */
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <6>;
+                        i2c-mux-idle-disconnect;
+                };
+
+                i2c@7 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <7>;
+                        i2c-mux-idle-disconnect;
+
+                        u41: pca9575@20 {
+                                compatible = "nxp,pca9575";
+                                reg = <0x20>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+
+                                gpio-line-names =
+                                        "FMCA_EN_12V0", "FMCA_EN_3V3", "FMCA_EN_VADJ", "FMCA_PG_M2C",
+                                        "FMCA_PG_C2M", "FMCA_PRSNT_M2C_L", "FMCA_CLK_DIR", "SFP_LOS",
+                                        "FMCB_EN_12V0", "FMCB_EN_3V3", "FMCB_EN_VADJ", "FMCB_PG_M2C",
+                                        "FMCB_PG_C2M", "FMCB_PRSNT_M2C_L", "FMCB_CLK_DIR", "SFP_ModPrsL";
+                                reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+                        };
+
+                        u42: pca9575@21 {
+                                compatible = "nxp,pca9575";
+                                reg = <0x21>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                gpio-line-names =
+                                        "QSFPA_ModPrsL", "QSFPA_IntL", "QSFPA_ResetL", "QSFPA_ModSelL",
+                                        "QSFPA_LPMode", "QSFPB_ModPrsL", "QSFPB_IntL", "QSFPB_ResetL",
+                                        "SFP_TxFault", "SFP_TxDisable", "SFP_RS0", "SFP_RS1",
+                                        "QSFPB_ModSelL", "QSFPB_LPMode", "SEL_SFP", "ARM_MR";
+                                reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+                        };
+
+                        u48: pca9575@22 {
+                                compatible = "nxp,pca9575";
+                                reg=<0x22>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+
+                                sw-gpios = <&u48 0 0>, <&u48 1 0>, <&u48 2 0>, <&u48 3 0>,
+                                        <&u48 4 0>, <&u48 5 0>, <&u48 6 0>, <&u48 7 0>;
+                                led-gpios = <&u48 7 0>, <&u48 6 0>, <&u48 5 0>, <&u48 4 0>,
+                                        <&u48 3 0>, <&u48 2 0>, <&u48 1 0>, <&u48 0 0>;
+
+                                gpio-line-names =
+                                        "GP_SW1", "GP_SW2", "GP_SW3", "GP_SW4",
+                                        "GP_SW5", "GP_SW6", "GP_SW7", "GP_SW8",
+                                        "GP_LED8", "GP_LED7", "GP_LED6", "GP_LED5",
+                                        "GP_LED4", "GP_LED3", "GP_LED2", "GP_LED1";
+                                reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+                        };
+
+                        u59: pca9575@23 {
+                                compatible = "nxp,pca9575";
+                                reg=<0x23>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                gpio-line-names =
+                                        "GP_LED9", "GP_LED10", "GP_LED11", "GP_LED12",
+                                        "GTX1V8PowerFault", "PHYAPowerFault", "PHYBPowerFault", "ArmPowerFault",
+                                        "BP_SLOW_GPIO0", "BP_SLOW_GPIO1", "BP_SLOW_GPIO2", "BP_SLOW_GPIO3",
+                                        "BP_SLOW_GPIO4", "BP_SLOW_GPIO5", "__unused_u59_p16", "__unused_u59_p17";
+                                reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+                        };
+
+                        tmp100@48 { compatible = "ti,tmp100"; reg = <0x48>; };
+                        tmp100@4a { compatible = "ti,tmp100"; reg = <0x4a>; };
+                        tmp100@4b { compatible = "ti,tmp100"; reg = <0x4b>; };
+                        tmp100@4c { compatible = "ti,tmp100"; reg = <0x4c>; };
+
+                        /* EEPROM bank and serial number are treated as separate devices */
+                        at24c01@57 { compatible = "atmel,24c01"; reg = <0x57>; };
+                        at24cs01@5f { compatible = "atmel,24cs01"; reg = <0x5f>; };
+                };
+        };
+};
+
+&i2c2 {
+        pca9548@71 {
+                compatible = "nxp,pca9548";
+                reg = <0x71>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                i2c@6 {
+                        /* Backplane */
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <6>;
+                        multi-master;
+
+                        /* All backplanes should have this -- it's how we know they're there. */
+                        at24c08@54 { compatible="atmel,24c08"; reg=<0x54>; };
+                        at24cs08@5c { compatible="atmel,24cs08"; reg=<0x5c>; };
+
+                        /* 16 slot backplane */
+                        tmp421@4d { compatible="ti,tmp421"; reg=<0x4d>; };
+                        tmp421@4e { compatible="ti,tmp421"; reg=<0x4e>; };
+                        ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <2360>; };
+                        amc6821@18 { compatible = "ti,amc6821"; reg = <0x18>; };
+
+                        /* Single slot backplane */
+                };
+        };
+};
+
+&pincntl {
+        mmc2_pins: pinmux_mmc2_pins {
+                pinctrl-single,pins = <
+                        DM814X_IOPAD(0x0800, PIN_INPUT | 0x1)   /* SD1_CLK */
+                        DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1)    /* SD1_CMD */
+                        DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1)    /* SD1_DAT[0] */
+                        DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1)    /* SD1_DAT[1] */
+                        DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1)    /* SD1_DAT[2] */
+                        DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1)    /* SD1_DAT[3] */
+                        DM814X_IOPAD(0x0924, PIN_INPUT_PULLUP | 0x40)   /* SD1_POW */
+                        DM814X_IOPAD(0x0928, PIN_INPUT | 0x40)  /* SD1_SDWP */
+                        DM814X_IOPAD(0x093C, PIN_INPUT | 0x2)   /* SD1_SDCD */
+                        >;
+        };
+
+        usb0_pins: pinmux_usb0_pins {
+                pinctrl-single,pins = <
+                        DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1)  /* USB0_DRVVBUS */
+                        >;
+        };
+
+        usb1_pins: pinmux_usb1_pins {
+                pinctrl-single,pins = <
+                        DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */
+                        >;
+        };
+
+        gpio1_pins: pinmux_gpio1_pins {
+                pinctrl-single,pins = <
+                        DM814X_IOPAD(0x081c, PIN_OUTPUT | 0x80) /* PROGRAM_B */
+                        DM814X_IOPAD(0x0820, PIN_INPUT | 0x80)  /* INIT_B */
+                        DM814X_IOPAD(0x0824, PIN_INPUT | 0x80)  /* DONE */
+
+                        DM814X_IOPAD(0x0838, PIN_INPUT_PULLUP | 0x80) /* FMCA_TMS */
+                        DM814X_IOPAD(0x083c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TCK */
+                        DM814X_IOPAD(0x0898, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDO */
+                        DM814X_IOPAD(0x089c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDI */
+                        DM814X_IOPAD(0x08ac, PIN_INPUT_PULLUP | 0x80) /* FMCA_TRST */
+
+                        DM814X_IOPAD(0x08b0, PIN_INPUT_PULLUP | 0x80) /* FMCB_TMS */
+                        DM814X_IOPAD(0x0a88, PIN_INPUT_PULLUP | 0x80) /* FMCB_TCK */
+                        DM814X_IOPAD(0x0a8c, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDO */
+                        DM814X_IOPAD(0x08bc, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDI */
+                        DM814X_IOPAD(0x0a94, PIN_INPUT_PULLUP | 0x80) /* FMCB_TRST */
+
+                        DM814X_IOPAD(0x08d4, PIN_INPUT_PULLUP | 0x80) /* FPGA_TMS */
+                        DM814X_IOPAD(0x0aa8, PIN_INPUT_PULLUP | 0x80) /* FPGA_TCK */
+                        DM814X_IOPAD(0x0adc, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDO */
+                        DM814X_IOPAD(0x0ab0, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDI */
+                        >;
+        };
+
+        gpio2_pins: pinmux_gpio2_pins {
+                pinctrl-single,pins = <
+                        DM814X_IOPAD(0x090c, PIN_INPUT_PULLUP | 0x80) /* PHY A IRQ */
+                        DM814X_IOPAD(0x0910, PIN_INPUT_PULLUP | 0x80) /* PHY A RESET */
+                        DM814X_IOPAD(0x08f4, PIN_INPUT_PULLUP | 0x80) /* PHY B IRQ */
+                        DM814X_IOPAD(0x08f8, PIN_INPUT_PULLUP | 0x80) /* PHY B RESET */
+
+                        //DM814X_IOPAD(0x0a14, PIN_INPUT_PULLUP | 0x80) /* ARM IRQ */
+                        //DM814X_IOPAD(0x0900, PIN_INPUT | 0x80) /* GPIO IRQ */
+                        DM814X_IOPAD(0x0a2c, PIN_INPUT_PULLUP | 0x80) /* GPIO RESET */
+                >;
+        };
+
+        gpio4_pins: pinmux_gpio4_pins {
+                pinctrl-single,pins = <
+                        /* The PLL doesn't react well to the SPI controller reset, so
+                         * we force the CS lines to pull up as GPIOs until we're ready.
+                         * See https://e2e.ti.com/support/processors/f/791/t/276011?Linux-support-for-AM3874-DM8148-in-Arago-linux-omap3
+                         */
+                        DM814X_IOPAD(0x0b3c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO0 */
+                        DM814X_IOPAD(0x0b40, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO1 */
+                        DM814X_IOPAD(0x0b44, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO2 */
+                        DM814X_IOPAD(0x0b48, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO3 */
+                        DM814X_IOPAD(0x0b4c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO4 */
+                        DM814X_IOPAD(0x0b50, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO5 */
+                >;
+        };
+
+        spi2_pins: pinmux_spi2_pins {
+                pinctrl-single,pins = <
+                        DM814X_IOPAD(0x0950, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS1 as GPIO */
+                        DM814X_IOPAD(0x0818, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS2 as GPIO */
+                >;
+        };
+
+        spi4_pins: pinmux_spi4_pins {
+                pinctrl-single,pins = <
+                        DM814X_IOPAD(0x0a7c, 0x20)
+                        DM814X_IOPAD(0x0b74, 0x20)
+                        DM814X_IOPAD(0x0b78, PIN_OUTPUT | 0x20)
+                        DM814X_IOPAD(0x0b7c, PIN_OUTPUT_PULLDOWN | 0x20)
+                        DM814X_IOPAD(0x0b80, PIN_INPUT | 0x20)
+                >;
+        };
+};
+
+&gpio1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&gpio1_pins>;
+        gpio-line-names =
+                "", "PROGRAM_B", "INIT_B", "DONE",                      /* 0-3 */
+                "", "", "", "",                                         /* 4-7 */
+                "FMCA_TMS", "FMCA_TCK", "FMCA_TDO", "FMCA_TDI",         /* 8-11 */
+                "", "", "", "FMCA_TRST",                                /* 12-15 */
+                "FMCB_TMS", "FMCB_TCK", "FMCB_TDO", "FMCB_TDI",         /* 16-19 */
+                "FMCB_TRST", "", "", "",                                /* 20-23 */
+                "FPGA_TMS", "FPGA_TCK", "FPGA_TDO", "FPGA_TDI",         /* 24-27 */
+                "", "", "", "";                                         /* 28-31 */
+};
+
+&gpio2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&gpio2_pins>;
+        gpio-line-names =
+                "PHYA_IRQ_N", "PHYA_RESET_N", "", "",                   /* 0-3 */
+                "", "", "", "PHYB_IRQ_N",                               /* 4-7 */
+                "PHYB_RESET_N", "ARM_IRQ", "GPIO_IRQ", "";              /* 8-11 */
+};
+
+&gpio3 {
+        pinctrl-names = "default";
+        /*pinctrl-0 = <&gpio3_pins>;*/
+        gpio-line-names =
+                "", "", "ARMClkSel0", "",                               /* 0-3 */
+                "EnFPGARef", "", "", "ARMClkSel1";                      /* 4-7 */
+};
+
+&gpio4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&gpio4_pins>;
+        gpio-line-names =
+                "BP_ARM_GPIO0", "BP_ARM_GPIO1", "BP_ARM_GPIO2", "BP_ARM_GPIO3",
+                "BP_ARM_GPIO4", "BP_ARM_GPIO5";
+};
+
+&usb0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb0_pins>;
+        dr_mode = "host";
+};
+
+&usb1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb1_pins>;
+        dr_mode = "host";
+};
+
+&mcspi1 {
+        s25fl256@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "jedec,spi-nor";
+                reg = <0>;
+                spi-max-frequency = <40000000>;
+
+                fsbl@0 {
+                        /* 256 kB */
+                        label = "U-Boot-min";
+                        reg = <0 0x40000>;
+                };
+                ssbl@1 {
+                        /* 512 kB */
+                        label = "U-Boot";
+                        reg = <0x40000 0x80000>;
+                };
+                bootenv@2 {
+                        /* 256 kB */
+                        label = "U-Boot Env";
+                        reg = <0xc0000 0x40000>;
+                };
+                kernel@3 {
+                        /* 4 MB */
+                        label = "Kernel";
+                        reg = <0x100000 0x400000>;
+                };
+                ipmi@4 {
+                        label = "IPMI FRU";
+                        reg = <0x500000 0x40000>;
+                };
+                fs@5 {
+                        label = "File System";
+                        reg = <0x540000 0x1ac0000>;
+                };
+        };
+};
+
+&mcspi3 {
+        /* DMA event numbers stolen from MCASP */
+        dmas = <&edma_xbar 8 0 16 &edma_xbar 9 0 17
+                &edma_xbar 10 0 18 &edma_xbar 11 0 19>;
+        dma-names = "tx0", "rx0", "tx1", "rx1";
+};
+
+&mcspi4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi4_pins>;
+
+        /* DMA event numbers stolen from MCASP, MCBSP */
+        dmas = <&edma_xbar 12 0 20 &edma_xbar 13 0 21>;
+        dma-names = "tx0", "rx0";
+};
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index f4a20cade808..4c6ee37ea573 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -71,7 +71,7 @@
                 pinctrl-0 = <&matrix_keypad_default>;
                 pinctrl-1 = <&matrix_keypad_sleep>;
 
-                linux,wakeup;
+                wakeup-source;
 
                 row-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH /* Bank0, pin3 */
                                 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi
index ca0896f80248..85c6f4ff1824 100644
--- a/arch/arm/boot/dts/am437x-l4.dtsi
+++ b/arch/arm/boot/dts/am437x-l4.dtsi
@@ -280,12 +280,6 @@
                                 #size-cells = <1>;
                                 ranges = <0 0 0x4000>;
 
-                                phy_sel: cpsw-phy-sel@650 {
-                                        compatible = "ti,am43xx-cpsw-phy-sel";
-                                        reg= <0x650 0x4>;
-                                        reg-names = "gmii-sel";
-                                };
-
                                 am43xx_pinmux: pinmux@800 {
                                         compatible = "ti,am437-padconf",
                                                      "pinctrl-single";
@@ -300,11 +294,17 @@
                                 };
 
                                 scm_conf: scm_conf@0 {
-                                        compatible = "syscon";
+                                        compatible = "syscon", "simple-bus";
                                         reg = <0x0 0x800>;
                                         #address-cells = <1>;
                                         #size-cells = <1>;
 
+                                        phy_gmii_sel: phy-gmii-sel {
+                                                compatible = "ti,am43xx-phy-gmii-sel";
+                                                reg = <0x650 0x4>;
+                                                #phy-cells = <2>;
+                                        };
+
                                         scm_clocks: clocks {
                                                 #address-cells = <1>;
                                                 #size-cells = <0>;
@@ -555,7 +555,6 @@
                                 cpts_clock_shift = <29>;
                                 ranges = <0 0 0x8000>;
                                 syscon = <&scm_conf>;
-                                cpsw-phy-sel = <&phy_sel>;
 
                                 davinci_mdio: mdio@1000 {
                                         compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio";
@@ -572,11 +571,13 @@
                                 cpsw_emac0: slave@200 {
                                         /* Filled in by U-Boot */
                                         mac-address = [ 00 00 00 00 00 00 ];
+                                        phys = <&phy_gmii_sel 1 0>;
                                 };
 
                                 cpsw_emac1: slave@300 {
                                         /* Filled in by U-Boot */
                                         mac-address = [ 00 00 00 00 00 00 ];
+                                        phys = <&phy_gmii_sel 2 0>;
                                 };
                         };
                 };
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 4ea753b3ee43..9dfd80e3b76e 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -584,10 +584,7 @@
 &cpsw_emac0 {
         phy-handle = <&ethphy0>;
         phy-mode = "rmii";
-};
-
-&phy_sel {
-        rmii-clock-ext;
+        phys = <&phy_gmii_sel 1 1>;
 };
 
 &i2c0 {
diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm-realview-eb.dtsi
index 0e4c7c4c8c09..610506723ea5 100644
--- a/arch/arm/boot/dts/arm-realview-eb.dtsi
+++ b/arch/arm/boot/dts/arm-realview-eb.dtsi
@@ -22,9 +22,10 @@
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
-#include "skeleton.dtsi"
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "arm,realview-eb";
 
         chosen { };
@@ -38,6 +39,7 @@
         };
 
         memory {
+                device_type = "memory";
                 /* 128 MiB memory @ 0x0 */
                 reg = <0x00000000 0x08000000>;
         };
diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts
index 83e0fbc4a1a1..cbbb8878daa3 100644
--- a/arch/arm/boot/dts/arm-realview-pb1176.dts
+++ b/arch/arm/boot/dts/arm-realview-pb1176.dts
@@ -23,9 +23,10 @@
 /dts-v1/;
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
-#include "skeleton.dtsi"
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "ARM RealView PB1176";
         compatible = "arm,realview-pb1176";
 
@@ -40,6 +41,7 @@
         };
 
         memory {
+                device_type = "memory";
                 /* 128 MiB memory @ 0x0 */
                 reg = <0x00000000 0x08000000>;
         };
diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts
index 2f6aa24a0b67..2015619ca22c 100644
--- a/arch/arm/boot/dts/arm-realview-pb11mp.dts
+++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts
@@ -23,9 +23,10 @@
 /dts-v1/;
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
-#include "skeleton.dtsi"
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "ARM RealView PB11MPcore";
         compatible = "arm,realview-pb11mp";
 
@@ -39,6 +40,7 @@
         };
 
         memory {
+                device_type = "memory";
                 /*
                  * The PB11MPCore has 512 MiB memory @ 0x70000000
                  * and the first 256 are also remapped @ 0x00000000
diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi
index 916a97734f84..a81e9c282432 100644
--- a/arch/arm/boot/dts/arm-realview-pbx.dtsi
+++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi
@@ -22,9 +22,10 @@
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
-#include "skeleton.dtsi"
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "arm,realview-pbx";
 
         chosen { };
@@ -39,6 +40,7 @@
         };
 
         memory {
+                device_type = "memory";
                 /* 128 MiB memory @ 0x0 */
                 reg = <0x00000000 0x08000000>;
         };
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 2bfb3108b5b2..c910d157a686 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -114,48 +114,6 @@
                         };
                 };
         };
-
-        dsa {
-                status = "disabled";
-
-                compatible = "marvell,dsa";
-                #address-cells = <2>;
-                #size-cells = <0>;
-
-                dsa,ethernet = <&eth1>;
-                dsa,mii-bus = <&mdio>;
-
-                switch@0 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        reg = <0x10 0>; /* MDIO address 16, switch 0 in tree */
-
-                        port@0 {
-                                reg = <0>;
-                                label = "lan0";
-                        };
-
-                        port@1 {
-                               reg = <1>;
-                               label = "lan1";
-                        };
-
-                        port@2 {
-                               reg = <2>;
-                               label = "lan2";
-                        };
-
-                        port@3 {
-                               reg = <3>;
-                               label = "lan3";
-                        };
-
-                        port@5 {
-                              reg = <5>;
-                              label = "cpu";
-                        };
-                };
-         };
 };
 
 &pciec {
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
index 89a354b43978..20f8d4667753 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -30,64 +30,6 @@
                 };
         };
 
-        dsa@0 {
-                status = "disabled";
-
-                compatible = "marvell,dsa";
-                dsa,ethernet = <&eth1>;
-                dsa,mii-bus = <&mdio>;
-                pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
-                pinctrl-names = "default";
-                #address-cells = <2>;
-                #size-cells = <0>;
-
-                switch@0 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        reg = <4 0>;
-
-                        port@0 {
-                                reg = <0>;
-                                label = "lan5";
-                        };
-
-                        port@1 {
-                                reg = <1>;
-                                label = "lan4";
-                        };
-
-                        port@2 {
-                                reg = <2>;
-                                label = "lan3";
-                        };
-
-                        port@3 {
-                                reg = <3>;
-                                label = "lan2";
-                        };
-
-                        port@4 {
-                                reg = <4>;
-                                label = "lan1";
-                        };
-
-                        port@5 {
-                                reg = <5>;
-                                label = "cpu";
-                        };
-
-                        port@6 {
-                                /* 88E1512 external phy */
-                                reg = <6>;
-                                label = "lan6";
-                                fixed-link {
-                                        speed = <1000>;
-                                        full-duplex;
-                                };
-                        };
-                };
-        };
-
         gpio-keys {
                 compatible = "gpio-keys";
                 pinctrl-0 = <&rear_button_pins>;
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi
index 1b0d0680c8b6..0d81600ca247 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dtsi
+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi
@@ -93,6 +93,7 @@
         bm,pool-long = <2>;
         bm,pool-short = <1>;
         buffer-manager = <&bm>;
+        phys = <&comphy1 1>;
         phy-mode = "sgmii";
         status = "okay";
 };
@@ -103,6 +104,7 @@
         bm,pool-short = <1>;
         buffer-manager = <&bm>;
         managed = "in-band-status";
+        phys = <&comphy5 2>;
         phy-mode = "sgmii";
         sfp = <&sfp>;
         status = "okay";
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 929459c42760..96c18703e471 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -9,13 +9,15 @@
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  */
 
-#include "skeleton.dtsi"
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
         model = "Marvell Armada 38x family SoC";
         compatible = "marvell,armada380";
 
@@ -335,6 +337,43 @@
                                 #clock-cells = <1>;
                         };
 
+                        comphy: phy@18300 {
+                                compatible = "marvell,armada-380-comphy";
+                                reg = <0x18300 0x100>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                comphy0: phy@0 {
+                                        reg = <0>;
+                                        #phy-cells = <1>;
+                                };
+
+                                comphy1: phy@1 {
+                                        reg = <1>;
+                                        #phy-cells = <1>;
+                                };
+
+                                comphy2: phy@2 {
+                                        reg = <2>;
+                                        #phy-cells = <1>;
+                                };
+
+                                comphy3: phy@3 {
+                                        reg = <3>;
+                                        #phy-cells = <1>;
+                                };
+
+                                comphy4: phy@4 {
+                                        reg = <4>;
+                                        #phy-cells = <1>;
+                                };
+
+                                comphy5: phy@5 {
+                                        reg = <5>;
+                                        #phy-cells = <1>;
+                                };
+                        };
+
                         coreclk: mvebu-sar@18600 {
                                 compatible = "marvell,armada-380-core-clock";
                                 reg = <0x18600 0x04>;
diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi
index f0c949831efb..b1b86934c688 100644
--- a/arch/arm/boot/dts/armada-39x.dtsi
+++ b/arch/arm/boot/dts/armada-39x.dtsi
@@ -7,13 +7,14 @@
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  */
 
-#include "skeleton.dtsi"
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Marvell Armada 39x family SoC";
         compatible = "marvell,armada390";
 
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index f3ac7483afed..5d04dc68cf57 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -144,30 +144,32 @@
                                 status = "okay";
                         };
 
-                        nand@d0000 {
+                        nand-controller@d0000 {
                                 status = "okay";
-                                label = "pxa3xx_nand-0";
-                                num-cs = <1>;
-                                marvell,nand-keep-config;
-                                nand-on-flash-bbt;
-
-                                partitions {
-                                        compatible = "fixed-partitions";
-                                        #address-cells = <1>;
-                                        #size-cells = <1>;
-
-                                        partition@0 {
-                                                label = "U-Boot";
-                                                reg = <0 0x800000>;
-                                        };
-                                        partition@800000 {
-                                                label = "Linux";
-                                                reg = <0x800000 0x800000>;
-                                        };
-                                        partition@1000000 {
-                                                label = "Filesystem";
-                                                reg = <0x1000000 0x3f000000>;
 
+                                nand@0 {
+                                        reg = <0>;
+                                        label = "pxa3xx_nand-0";
+                                        nand-rb = <0>;
+                                        nand-on-flash-bbt;
+
+                                        partitions {
+                                                compatible = "fixed-partitions";
+                                                #address-cells = <1>;
+                                                #size-cells = <1>;
+
+                                                partition@0 {
+                                                        label = "U-Boot";
+                                                        reg = <0 0x800000>;
+                                                };
+                                                partition@800000 {
+                                                        label = "Linux";
+                                                        reg = <0x800000 0x800000>;
+                                                };
+                                                partition@1000000 {
+                                                        label = "Filesystem";
+                                                        reg = <0x1000000 0x3f000000>;
+                                                };
                                         };
                                 };
                         };
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 1139e9469a83..b4cca507cf13 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -160,12 +160,15 @@
                                 status = "okay";
                         };
 
-                        nand@d0000 {
+                        nand-controller@d0000 {
                                 status = "okay";
-                                label = "pxa3xx_nand-0";
-                                num-cs = <1>;
-                                marvell,nand-keep-config;
-                                nand-on-flash-bbt;
+
+                                nand@0 {
+                                        reg = <0>;
+                                        label = "pxa3xx_nand-0";
+                                        nand-rb = <0>;
+                                        nand-on-flash-bbt;
+                                };
                         };
                 };
 
diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
index bbbb38888bb8..87dcb502f72d 100644
--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
+++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
@@ -81,49 +81,52 @@
 
                         };
 
-                        nand@d0000 {
+                        nand-controller@d0000 {
                                 status = "okay";
-                                label = "pxa3xx_nand-0";
-                                num-cs = <1>;
-                                marvell,nand-keep-config;
-                                nand-on-flash-bbt;
-
-                                partitions {
-                                        compatible = "fixed-partitions";
-                                        #address-cells = <1>;
-                                        #size-cells = <1>;
-
-                                        partition@0 {
-                                                label = "u-boot";
-                                                reg = <0x00000000 0x000e0000>;
-                                                read-only;
-                                        };
-
-                                        partition@e0000 {
-                                                label = "u-boot-env";
-                                                reg = <0x000e0000 0x00020000>;
-                                                read-only;
-                                        };
-
-                                        partition@100000 {
-                                                label = "u-boot-env2";
-                                                reg = <0x00100000 0x00020000>;
-                                                read-only;
-                                        };
-
-                                        partition@120000 {
-                                                label = "zImage";
-                                                reg = <0x00120000 0x00400000>;
-                                        };
-
-                                        partition@520000 {
-                                                label = "initrd";
-                                                reg = <0x00520000 0x00400000>;
-                                        };
 
-                                        partition@e00000 {
-                                                label = "boot";
-                                                reg = <0x00e00000 0x3f200000>;
+                                nand@0 {
+                                        reg = <0>;
+                                        label = "pxa3xx_nand-0";
+                                        nand-rb = <0>;
+                                        nand-on-flash-bbt;
+
+                                        partitions {
+                                                compatible = "fixed-partitions";
+                                                #address-cells = <1>;
+                                                #size-cells = <1>;
+
+                                                partition@0 {
+                                                        label = "u-boot";
+                                                        reg = <0x00000000 0x000e0000>;
+                                                        read-only;
+                                                };
+
+                                                partition@e0000 {
+                                                        label = "u-boot-env";
+                                                        reg = <0x000e0000 0x00020000>;
+                                                        read-only;
+                                                };
+
+                                                partition@100000 {
+                                                        label = "u-boot-env2";
+                                                        reg = <0x00100000 0x00020000>;
+                                                        read-only;
+                                                };
+
+                                                partition@120000 {
+                                                        label = "zImage";
+                                                        reg = <0x00120000 0x00400000>;
+                                                };
+
+                                                partition@520000 {
+                                                        label = "initrd";
+                                                        reg = <0x00520000 0x00400000>;
+                                                };
+
+                                                partition@e00000 {
+                                                        label = "boot";
+                                                        reg = <0x00e00000 0x3f200000>;
+                                                };
                                         };
                                 };
                         };
diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
index 7a2606c3b62e..8480a16919a0 100644
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -210,53 +210,6 @@
                 compatible = "pwm-fan";
                 pwms = <&gpio0 24 4000>;
         };
-
-        dsa {
-                status = "disabled";
-
-                compatible = "marvell,dsa";
-                #address-cells = <2>;
-                #size-cells = <0>;
-
-                dsa,ethernet = <&eth0>;
-                dsa,mii-bus = <&mdio>;
-
-                switch@0 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        reg = <0x0 0>;  /* MDIO address 0, switch 0 in tree */
-
-                        port@0 {
-                                reg = <0>;
-                                label = "lan4";
-                        };
-
-                        port@1 {
-                                reg = <1>;
-                                label = "lan3";
-                        };
-
-                        port@2 {
-                                reg = <2>;
-                                label = "lan2";
-                        };
-
-                        port@3 {
-                                reg = <3>;
-                                label = "lan1";
-                        };
-
-                        port@4 {
-                                reg = <4>;
-                                label = "internet";
-                        };
-
-                        port@5 {
-                                reg = <5>;
-                                label = "cpu";
-                        };
-                };
-        };
 };
 
 &pciec {
diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
index 3e4115c2cd75..037157e6c5ee 100644
--- a/arch/arm/boot/dts/artpec6.dtsi
+++ b/arch/arm/boot/dts/artpec6.dtsi
@@ -43,9 +43,10 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/dma/nbpfaxi.h>
 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
-#include "skeleton.dtsi"
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "axis,artpec6";
         interrupt-parent = <&intc>;
 
diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts
index bdfd8c9f3a7c..521afbea2c5b 100644
--- a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts
@@ -173,6 +173,16 @@
                         };
                 };
         };
+
+        dps650ab@58 {
+                compatible = "delta,dps650ab";
+                reg = <0x58>;
+        };
+
+        dps650ab@59 {
+                compatible = "delta,dps650ab";
+                reg = <0x59>;
+        };
 };
 
 &i2c9 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
index f8e7b71af7e6..4c2dcac738e8 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
@@ -21,6 +21,17 @@
         memory@80000000 {
                 reg = <0x80000000 0x20000000>;
         };
+
+        iio-hwmon {
+                compatible = "iio-hwmon";
+                io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+                                        <&adc 4>, <&adc 5>, <&adc 6>;
+        };
+
+        iio-hwmon-battery {
+                compatible = "iio-hwmon";
+                io-channels = <&adc 7>;
+        };
 };
 
 &fmc {
@@ -43,6 +54,16 @@
         };
 };
 
+&lpc_snoop {
+        status = "okay";
+        snoop-ports = <0x80>;
+};
+
+&lpc_ctrl {
+        // Enable lpc clock
+        status = "okay";
+};
+
 &uart1 {
         // Host Console
         status = "okay";
@@ -51,11 +72,33 @@
                      &pinctrl_rxd1_default>;
 };
 
+&uart2 {
+        // SoL Host Console
+        status = "okay";
+};
+
+&uart3 {
+        // SoL BMC Console
+        status = "okay";
+};
+
 &uart5 {
         // BMC Console
         status = "okay";
 };
 
+&kcs2 {
+        // BMC KCS channel 2
+        status = "okay";
+        kcs_addr = <0xca8>;
+};
+
+&kcs3 {
+        // BMC KCS channel 3
+        status = "okay";
+        kcs_addr = <0xca2>;
+};
+
 &mac0 {
         status = "okay";
 
@@ -64,6 +107,10 @@
         use-ncsi;
 };
 
+&adc {
+        status = "okay";
+};
+
 &i2c0 {
         status = "okay";
         //Airmax Conn B, CPU0 PIROM, CPU1 PIROM
@@ -122,6 +169,10 @@
 
 &i2c8 {
         status = "okay";
+        tmp421@1f {
+                compatible = "ti,tmp421";
+                reg = <0x1f>;
+        };
         //Mezz Sensor SMBus
 };
 
@@ -140,7 +191,7 @@
         };
 
         fan@1 {
-                reg = <0x00>;
-                aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+                reg = <0x01>;
+                aspeed,fan-tach-ch = /bits/ 8 <0x02>;
         };
 };
diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts
new file mode 100644
index 000000000000..2337ee23f5c4
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Inspur Corporation
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+        model = "ON5263M5 BMC";
+        compatible = "inspur,on5263m5-bmc", "aspeed,ast2500";
+
+        chosen {
+                stdout-path = &uart5;
+                bootargs = "earlyprintk";
+        };
+
+        memory {
+                reg = <0x80000000 0x20000000>;
+        };
+
+        reserved-memory {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                vga_memory: framebuffer@9f000000 {
+                        no-map;
+                        reg = <0x9f000000 0x01000000>;
+                };
+        };
+
+        leds {
+            compatible = "gpio-leds";
+            bmc_alive {
+                label = "bmc_alive";
+                gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>;
+                linux,default-trigger = "timer";
+            };
+        };
+
+        iio-hwmon {
+                compatible = "iio-hwmon";
+                io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+                        <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>;
+        };
+
+};
+
+&fmc {
+        status = "okay";
+        flash@0 {
+                status = "okay";
+                m25p,fast-read;
+                label = "bmc";
+#include "openbmc-flash-layout.dtsi"
+        };
+};
+
+&spi1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_spi1_default>;
+
+        flash@0 {
+                status = "okay";
+                m25p,fast-read;
+                label = "pnor";
+        };
+};
+
+&uart5 {
+        status = "okay";
+};
+
+&mac0 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_rmii1_default>;
+        use-ncsi;
+};
+
+&mac1 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+};
+
+&i2c6 {
+        status = "okay";
+
+        tmp421@4e {
+                compatible = "ti,tmp421";
+                reg = <0x4e>;
+        };
+
+        tmp112@48 {
+                compatible = "ti,tmp112";
+                reg = <0x48>;
+        };
+
+        eeprom@54 {
+                compatible = "atmel,24c64";
+                reg = <0x54>;
+                pagesize = <32>;
+        };
+};
+
+&i2c7 {
+        status = "okay";
+
+        adm1278@11 {
+                  compatible = "adi,adm1278";
+                  reg = <0x11>;
+        };
+};
+
+&gfx {
+        status = "okay";
+};
+
+&pinctrl {
+        aspeed,external-nodes = <&gfx &lhc>;
+};
+
+&pwm_tacho {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
+
+        fan@0 {
+                reg = <0x00>;
+                aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>;
+        };
+
+        fan@1 {
+                reg = <0x01>;
+                aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>;
+        };
+};
+
+&adc {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index 9aa1d4467453..b854ac0bae9a 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -169,6 +169,11 @@
 
 &i2c3 {
         status = "okay";
+
+        occ-hwmon@50 {
+                compatible = "ibm,p8-occ-hwmon";
+                reg = <0x50>;
+        };
 };
 
 &i2c4 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
index 385c0f4b69ee..0d7c6339da46 100644
--- a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
@@ -116,6 +116,10 @@
         status = "okay";
 };
 
+&lpc_ctrl {
+        status = "okay";
+};
+
 &lpc_snoop {
         status = "okay";
         snoop-ports = <0x80>;
@@ -134,6 +138,10 @@
         pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
 };
 
+&uart1 {
+        status = "okay";
+};
+
 &uart5 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 69f6b9d2e7e7..9549f867aa1e 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -197,6 +197,7 @@
                                 gpio-ranges = <&pinctrl 0 0 220>;
                                 clocks = <&syscon ASPEED_CLK_APB>;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         timer: timer@1e782000 {
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d107459fc0f8..85ed9dbec196 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -47,6 +47,13 @@
                 reg = <0x80000000 0>;
         };
 
+        edac: sdram@1e6e0000 {
+                compatible = "aspeed,ast2500-sdram-edac";
+                reg = <0x1e6e0000 0x174>;
+                interrupts = <0>;
+                status = "disabled";
+        };
+
         ahb {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -250,6 +257,7 @@
                                 gpio-ranges = <&pinctrl 0 0 220>;
                                 clocks = <&syscon ASPEED_CLK_APB>;
                                 interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         timer: timer@1e782000 {
@@ -330,8 +338,32 @@
                                 ranges = <0x0 0x1e789000 0x1000>;
 
                                 lpc_bmc: lpc-bmc@0 {
-                                        compatible = "aspeed,ast2500-lpc-bmc";
+                                        compatible = "aspeed,ast2500-lpc-bmc", "simple-mfd", "syscon";
                                         reg = <0x0 0x80>;
+                                        reg-io-width = <4>;
+
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        ranges = <0x0 0x0 0x80>;
+
+                                        kcs1: kcs1@0 {
+                                                compatible = "aspeed,ast2500-kcs-bmc";
+                                                interrupts = <8>;
+                                                kcs_chan = <1>;
+                                                status = "disabled";
+                                        };
+                                        kcs2: kcs2@0 {
+                                                compatible = "aspeed,ast2500-kcs-bmc";
+                                                interrupts = <8>;
+                                                kcs_chan = <2>;
+                                                status = "disabled";
+                                        };
+                                        kcs3: kcs3@0 {
+                                                compatible = "aspeed,ast2500-kcs-bmc";
+                                                interrupts = <8>;
+                                                kcs_chan = <3>;
+                                                status = "disabled";
+                                        };
                                 };
 
                                 lpc_host: lpc-host@80 {
@@ -343,6 +375,13 @@
                                         #size-cells = <1>;
                                         ranges = <0x0 0x80 0x1e0>;
 
+                                        kcs4: kcs4@0 {
+                                                compatible = "aspeed,ast2500-kcs-bmc";
+                                                interrupts = <8>;
+                                                kcs_chan = <4>;
+                                                status = "disabled";
+                                        };
+
                                         lpc_ctrl: lpc-ctrl@0 {
                                                 compatible = "aspeed,ast2500-lpc-ctrl";
                                                 reg = <0x0 0x80>;
diff --git a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
index 0f6d335125e2..f245944bd5d7 100644
--- a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
+++ b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
@@ -22,7 +22,7 @@
                 wakeup {
                         label = "Wakeup";
                         linux,code = <10>;
-                        gpio-key,wakeup;
+                        wakeup-source;
                         gpios = <&pioB 27 GPIO_ACTIVE_LOW>;
                 };
         };
diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
index cf0087b4c9e1..33a159c0163f 100644
--- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
+++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
@@ -62,6 +62,20 @@
 
         ahb {
                 apb {
+                        qspi1: spi@f0024000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_qspi1_default>;
+
+                                flash@0 {
+                                        compatible = "jedec,spi-nor";
+                                        reg = <0>;
+                                        spi-max-frequency = <80000000>;
+                                        spi-tx-bus-width = <4>;
+                                        spi-rx-bus-width = <4>;
+                                        m25p,fast-read;
+                                };
+                        };
+
                         macb0: ethernet@f8008000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_macb0_default>;
@@ -78,6 +92,22 @@
 
                         pinctrl@fc038000 {
 
+                                pinctrl_qspi1_default: qspi1_default {
+                                        sck_cs {
+                                                pinmux = <PIN_PB5__QSPI1_SCK>,
+                                                         <PIN_PB6__QSPI1_CS>;
+                                                bias-disable;
+                                        };
+
+                                        data {
+                                                pinmux = <PIN_PB7__QSPI1_IO0>,
+                                                         <PIN_PB8__QSPI1_IO1>,
+                                                         <PIN_PB9__QSPI1_IO2>,
+                                                         <PIN_PB10__QSPI1_IO3>;
+                                                bias-pull-up;
+                                        };
+                                };
+
                                 pinctrl_macb0_default: macb0_default {
                                         pinmux = <PIN_PD9__GTXCK>,
                                                  <PIN_PD10__GTXEN>,
diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
index 4a258867ddf1..a48180555ef5 100644
--- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
@@ -109,6 +109,10 @@
                                 status = "okay";
                         };
 
+                        qspi1: spi@f0024000 {
+                                status = "okay";
+                        };
+
                         spi0: spi@f8000000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_spi0_default>;
diff --git a/arch/arm/boot/dts/at91-wb45n.dts b/arch/arm/boot/dts/at91-wb45n.dts
index 5b9512a6c89c..54d130c92185 100644
--- a/arch/arm/boot/dts/at91-wb45n.dts
+++ b/arch/arm/boot/dts/at91-wb45n.dts
@@ -22,7 +22,7 @@
                         label = "IRQBTN";
                         linux,code = <99>;
                         gpios = <&pioB 18 GPIO_ACTIVE_LOW>;
-                        gpio-key,wakeup = <1>;
+                        wakeup-source;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/at91-wb50n.dts b/arch/arm/boot/dts/at91-wb50n.dts
index 8cecc7051a86..a5e45bb95c04 100644
--- a/arch/arm/boot/dts/at91-wb50n.dts
+++ b/arch/arm/boot/dts/at91-wb50n.dts
@@ -23,7 +23,7 @@
                         label = "BTNESC";
                         linux,code = <1>; /* ESC button */
                         gpios = <&pioA 10 GPIO_ACTIVE_LOW>;
-                        gpio-key,wakeup = <1>;
+                        wakeup-source;
                 };
 
                 irqbtn@31 {
@@ -31,7 +31,7 @@
                         label = "IRQBTN";
                         linux,code = <99>; /* SysReq button */
                         gpios = <&pioE 31 GPIO_ACTIVE_LOW>;
-                        gpio-key,wakeup = <1>;
+                        wakeup-source;
                 };
         };
 
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 2ad69a7fbc00..5a882a053816 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -10,13 +10,14 @@
  * Licensed under GPLv2 or later.
  */
 
-#include "skeleton.dtsi"
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/clock/at91.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Atmel AT91RM9200 family SoC";
         compatible = "atmel,at91rm9200";
         interrupt-parent = <&aic>;
@@ -49,6 +50,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x20000000 0x04000000>;
         };
 
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 7cd9c3bc4dfb..3b58b94b53c9 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -8,13 +8,14 @@
  * Licensed under GPLv2 or later.
  */
 
-#include "skeleton.dtsi"
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/clock/at91.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Atmel AT91SAM9260 family SoC";
         compatible = "atmel,at91sam9260";
         interrupt-parent = <&aic>;
@@ -46,6 +47,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x20000000 0x04000000>;
         };
 
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index 01d700b63b45..a907a1fdd24c 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -6,13 +6,14 @@
  * Licensed under GPLv2 only.
  */
 
-#include "skeleton.dtsi"
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/clock/at91.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Atmel AT91SAM9261 family SoC";
         compatible = "atmel,at91sam9261";
         interrupt-parent = <&aic>;
@@ -43,6 +44,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x20000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index c5766da4e54e..3fb63d81f18e 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -6,13 +6,14 @@
  * Licensed under GPLv2 only.
  */
 
-#include "skeleton.dtsi"
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/clock/at91.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Atmel AT91SAM9263 family SoC";
         compatible = "atmel,at91sam9263";
         interrupt-parent = <&aic>;
@@ -45,6 +46,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x20000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index d16db1fa7e15..f36819607131 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -9,7 +9,6 @@
  * Licensed under GPLv2 or later.
  */
 
-#include "skeleton.dtsi"
 #include <dt-bindings/dma/at91.h>
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -17,6 +16,8 @@
 #include <dt-bindings/clock/at91.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Atmel AT91SAM9G45 family SoC";
         compatible = "atmel,at91sam9g45";
         interrupt-parent = <&aic>;
@@ -51,6 +52,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x70000000 0x10000000>;
         };
 
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 37cb81f457b5..f71d65e6e510 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -7,7 +7,6 @@
  * Licensed under GPLv2 or later.
  */
 
-#include "skeleton.dtsi"
 #include <dt-bindings/dma/at91.h>
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -15,6 +14,8 @@
 #include <dt-bindings/clock/at91.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Atmel AT91SAM9N12 SoC";
         compatible = "atmel,at91sam9n12";
         interrupt-parent = <&aic>;
@@ -47,6 +48,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x20000000 0x10000000>;
         };
 
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index 3862ff2f26e0..6b5777f3c20b 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -7,7 +7,6 @@
  * Licensed under GPLv2 or later.
  */
 
-#include "skeleton.dtsi"
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/clock/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -15,6 +14,8 @@
 #include <dt-bindings/pwm/pwm.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Atmel AT91SAM9RL family SoC";
         compatible = "atmel,at91sam9rl", "atmel,at91sam9";
         interrupt-parent = <&aic>;
@@ -48,6 +49,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x20000000 0x04000000>;
         };
 
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 07443a387a8f..79c4956d3902 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -9,7 +9,6 @@
  * Licensed under GPLv2 or later.
  */
 
-#include "skeleton.dtsi"
 #include <dt-bindings/dma/at91.h>
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -17,6 +16,8 @@
 #include <dt-bindings/clock/at91.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Atmel AT91SAM9x5 family SoC";
         compatible = "atmel,at91sam9x5";
         interrupt-parent = <&aic>;
@@ -49,6 +50,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x20000000 0x10000000>;
         };
 
diff --git a/arch/arm/boot/dts/atlas6-evb.dts b/arch/arm/boot/dts/atlas6-evb.dts
index ab042ca8dea1..40882419309d 100644
--- a/arch/arm/boot/dts/atlas6-evb.dts
+++ b/arch/arm/boot/dts/atlas6-evb.dts
@@ -15,6 +15,7 @@
         compatible = "sirf,atlas6-cb", "sirf,atlas6";
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index 29598667420b..5587b98032a3 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -6,7 +6,6 @@
  * Licensed under GPLv2 or later.
  */
 
-/include/ "skeleton.dtsi"
 / {
         compatible = "sirf,atlas6";
         #address-cells = <1>;
diff --git a/arch/arm/boot/dts/atlas7.dtsi b/arch/arm/boot/dts/atlas7.dtsi
index 83449b33de6b..f3de9af35b4d 100644
--- a/arch/arm/boot/dts/atlas7.dtsi
+++ b/arch/arm/boot/dts/atlas7.dtsi
@@ -6,7 +6,6 @@
  * Licensed under GPLv2 or later.
  */
 
-/include/ "skeleton.dtsi"
 / {
         compatible = "sirf,atlas7";
         #address-cells = <1>;
diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi
index 47799f59faa5..2a93d3ee3b66 100644
--- a/arch/arm/boot/dts/axm55xx.dtsi
+++ b/arch/arm/boot/dts/axm55xx.dtsi
@@ -12,9 +12,9 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/lsi,axm5516-clks.h>
 
-#include "skeleton64.dtsi"
-
 / {
+        #address-cells = <2>;
+        #size-cells = <2>;
         interrupt-parent = <&gic>;
 
         aliases {
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 253df7170a4e..5f7b46503a51 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -34,9 +34,9 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/clock/bcm-cygnus.h>
 
-#include "skeleton.dtsi"
-
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "brcm,cygnus";
         model = "Broadcom Cygnus SoC";
         interrupt-parent = <&gic>;
@@ -45,6 +45,11 @@
                 ethernet0 = &eth0;
         };
 
+        memory {
+                device_type = "memory";
+                reg = <0 0>;
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 0d2538b46139..6925b30c2253 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -34,9 +34,9 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/clock/bcm-nsp.h>
 
-#include "skeleton.dtsi"
-
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "brcm,nsp";
         model = "Broadcom Northstar Plus SoC";
         interrupt-parent = <&gic>;
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index db7cded1b7ad..b99c2e579622 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -16,9 +16,9 @@
 
 #include "dt-bindings/clock/bcm281xx.h"
 
-#include "skeleton.dtsi"
-
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "BCM11351 SoC";
         compatible = "brcm,bcm11351";
         interrupt-parent = <&gic>;
diff --git a/arch/arm/boot/dts/bcm21664-garnet.dts b/arch/arm/boot/dts/bcm21664-garnet.dts
index e87cb26ddf84..8b045cfab64b 100644
--- a/arch/arm/boot/dts/bcm21664-garnet.dts
+++ b/arch/arm/boot/dts/bcm21664-garnet.dts
@@ -22,6 +22,7 @@
         compatible = "brcm,bcm21664-garnet", "brcm,bcm21664";
 
         memory {
+                device_type = "memory";
                 reg = <0x80000000 0x40000000>; /* 1 GB */
         };
 
diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi
index 266f2611dc22..758daa334148 100644
--- a/arch/arm/boot/dts/bcm21664.dtsi
+++ b/arch/arm/boot/dts/bcm21664.dtsi
@@ -16,9 +16,9 @@
 
 #include "dt-bindings/clock/bcm21664.h"
 
-#include "skeleton.dtsi"
-
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "BCM21664 SoC";
         compatible = "brcm,bcm21664";
         interrupt-parent = <&gic>;
diff --git a/arch/arm/boot/dts/bcm23550-sparrow.dts b/arch/arm/boot/dts/bcm23550-sparrow.dts
index 4d525ccb48c8..1c66b15f3013 100644
--- a/arch/arm/boot/dts/bcm23550-sparrow.dts
+++ b/arch/arm/boot/dts/bcm23550-sparrow.dts
@@ -46,6 +46,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x80000000 0x20000000>; /* 512 MB */
         };
 };
diff --git a/arch/arm/boot/dts/bcm23550.dtsi b/arch/arm/boot/dts/bcm23550.dtsi
index a7a643f38385..701198f5f498 100644
--- a/arch/arm/boot/dts/bcm23550.dtsi
+++ b/arch/arm/boot/dts/bcm23550.dtsi
@@ -36,9 +36,9 @@
 /* BCM23550 and BCM21664 have almost identical clocks */
 #include "dt-bindings/clock/bcm21664.h"
 
-#include "skeleton.dtsi"
-
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "BCM23550 SoC";
         compatible = "brcm,bcm23550";
         interrupt-parent = <&gic>;
diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts
index 9ce91dd60cb6..fbfca83bd28f 100644
--- a/arch/arm/boot/dts/bcm28155-ap.dts
+++ b/arch/arm/boot/dts/bcm28155-ap.dts
@@ -22,6 +22,7 @@
         compatible = "brcm,bcm28155-ap", "brcm,bcm11351";
 
         memory {
+                device_type = "memory";
                 reg = <0x80000000 0x40000000>; /* 1 GB */
         };
 
diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
index 2cd9c5e4f892..db8a6017f220 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
@@ -31,8 +31,8 @@
          * "FOO" = GPIO line named "FOO" on the schematic
          * "FOO_N" = GPIO line named "FOO" on schematic, active low
          */
-        gpio-line-names = "SDA0",
-                          "SCL0",
+        gpio-line-names = "ID_SDA",
+                          "ID_SCL",
                           "SDA1",
                           "SCL1",
                           "GPIO_GCLK",
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
index cfbdaacbaeba..1e40d672b055 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
@@ -33,8 +33,8 @@
          * "FOO" = GPIO line named "FOO" on the schematic
          * "FOO_N" = GPIO line named "FOO" on schematic, active low
          */
-        gpio-line-names = "SDA0",
-                          "SCL0",
+        gpio-line-names = "ID_SDA",
+                          "ID_SCL",
                           "SDA1",
                           "SCL1",
                           "GPIO_GCLK",
diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
index 644d907bafbb..ba0167df6c5f 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
@@ -25,8 +25,6 @@
 
         wifi_pwrseq: wifi-pwrseq {
                 compatible = "mmc-pwrseq-simple";
-                pinctrl-names = "default";
-                pinctrl-0 = <&wl_on>;
                 reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
         };
 };
@@ -40,8 +38,8 @@
          * "FOO" = GPIO line named "FOO" on the schematic
          * "FOO_N" = GPIO line named "FOO" on schematic, active low
          */
-        gpio-line-names = "GPIO0",
-                          "GPIO1",
+        gpio-line-names = "ID_SDA",
+                          "ID_SCL",
                           "SDA1",
                           "SCL1",
                           "GPIO_GCLK",
@@ -98,11 +96,6 @@
                           "SD_DATA3_R";
 
         pinctrl-0 = <&gpioout &alt0>;
-
-        wl_on: wl-on {
-                brcm,pins = <41>;
-                brcm,function = <BCM2835_FSEL_GPIO_OUT>;
-        };
 };
 
 &hdmi {
diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
index 00323ba8f7de..3b35a8a4a55f 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
@@ -28,8 +28,8 @@
          * "FOO" = GPIO line named "FOO" on the schematic
          * "FOO_N" = GPIO line named "FOO" on schematic, active low
          */
-        gpio-line-names = "SDA0",
-                          "SCL0",
+        gpio-line-names = "ID_SDA",
+                          "ID_SCL",
                           "SDA1",
                           "SCL1",
                           "GPIO_GCLK",
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index 29f970f864dc..715d50c64529 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -1,7 +1,7 @@
 #include <dt-bindings/power/raspberrypi-power.h>
 
 / {
-        memory {
+        memory@0 {
                 device_type = "memory";
                 reg = <0 0x10000000>;
         };
@@ -19,8 +19,6 @@
         soc {
                 firmware: firmware {
                         compatible = "raspberrypi,bcm2835-firmware", "simple-bus";
-                        #address-cells = <0>;
-                        #size-cells = <0>;
                         mboxes = <&mailbox>;
                 };
 
@@ -87,10 +85,6 @@
         power-domains = <&power RPI_POWER_DOMAIN_USB>;
 };
 
-&v3d {
-        power-domains = <&power RPI_POWER_DOMAIN_V3D>;
-};
-
 &hdmi {
         power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
         status = "okay";
diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
index ac4408b34b58..7b4e651bafdd 100644
--- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
+++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
@@ -9,7 +9,7 @@
         compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
         model = "Raspberry Pi 2 Model B";
 
-        memory {
+        memory@0 {
                 reg = <0 0x40000000>;
         };
 
@@ -28,6 +28,72 @@
 };
 
 &gpio {
+        /*
+         * Taken from rpi_SCH_2b_1p2_reduced.pdf and
+         * the official GPU firmware DT blob.
+         *
+         * Legend:
+         * "NC" = not connected (no rail from the SoC)
+         * "FOO" = GPIO line named "FOO" on the schematic
+         * "FOO_N" = GPIO line named "FOO" on schematic, active low
+         */
+        gpio-line-names = "ID_SDA",
+                          "ID_SCL",
+                          "SDA1",
+                          "SCL1",
+                          "GPIO_GCLK",
+                          "GPIO5",
+                          "GPIO6",
+                          "SPI_CE1_N",
+                          "SPI_CE0_N",
+                          "SPI_MISO",
+                          "SPI_MOSI",
+                          "SPI_SCLK",
+                          "GPIO12",
+                          "GPIO13",
+                          /* Serial port */
+                          "TXD0",
+                          "RXD0",
+                          "GPIO16",
+                          "GPIO17",
+                          "GPIO18",
+                          "GPIO19",
+                          "GPIO20",
+                          "GPIO21",
+                          "GPIO22",
+                          "GPIO23",
+                          "GPIO24",
+                          "GPIO25",
+                          "GPIO26",
+                          "GPIO27",
+                          "SDA0",
+                          "SCL0",
+                          "", /* GPIO30 */
+                          "LAN_RUN",
+                          "CAM_GPIO1",
+                          "", /* GPIO33 */
+                          "", /* GPIO34 */
+                          "PWR_LOW_N",
+                          "", /* GPIO36 */
+                          "", /* GPIO37 */
+                          "USB_LIMIT",
+                          "", /* GPIO39 */
+                          "PWM0_OUT",
+                          "CAM_GPIO0",
+                          "SMPS_SCL",
+                          "SMPS_SDA",
+                          "ETHCLK",
+                          "PWM1_OUT",
+                          "HDMI_HPD_N",
+                          "STATUS_LED",
+                          /* Used by SD Card */
+                          "SD_CLK_R",
+                          "SD_CMD_R",
+                          "SD_DATA0_R",
+                          "SD_DATA1_R",
+                          "SD_DATA2_R",
+                          "SD_DATA3_R";
+
         pinctrl-0 = <&gpioout &alt0 &i2s_alt0>;
 
         /* I2S interface */
diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
new file mode 100644
index 000000000000..7f4437a8eedb
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "bcm2837.dtsi"
+#include "bcm2836-rpi.dtsi"
+#include "bcm283x-rpi-usb-host.dtsi"
+
+/ {
+        compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837";
+        model = "Raspberry Pi 3 Model A+";
+
+        chosen {
+                /* 8250 auxiliary UART instead of pl011 */
+                stdout-path = "serial1:115200n8";
+        };
+
+        memory@0 {
+                reg = <0 0x20000000>;
+        };
+
+        leds {
+                act {
+                        gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
+                };
+
+                pwr {
+                        label = "PWR";
+                        gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
+
+&firmware {
+        expgpio: gpio {
+                compatible = "raspberrypi,firmware-gpio";
+                gpio-controller;
+                #gpio-cells = <2>;
+                gpio-line-names = "",
+                                  "BT_WL_ON",
+                                  "STATUS_LED_R",
+                                  "",
+                                  "",
+                                  "CAM_GPIO0",
+                                  "CAM_GPIO1",
+                                  "";
+                status = "okay";
+        };
+};
+
+&gpio {
+        /*
+         * This is mostly based on the official GPU firmware DT blob.
+         *
+         * Legend:
+         * "NC" = not connected (no rail from the SoC)
+         * "FOO" = GPIO line named "FOO" on the schematic
+         * "FOO_N" = GPIO line named "FOO" on schematic, active low
+         */
+        gpio-line-names = "ID_SDA",
+                          "ID_SCL",
+                          "SDA1",
+                          "SCL1",
+                          "GPIO_GCLK",
+                          "GPIO5",
+                          "GPIO6",
+                          "SPI_CE1_N",
+                          "SPI_CE0_N",
+                          "SPI_MISO",
+                          "SPI_MOSI",
+                          "SPI_SCLK",
+                          "GPIO12",
+                          "GPIO13",
+                          /* Serial port */
+                          "TXD1",
+                          "RXD1",
+                          "GPIO16",
+                          "GPIO17",
+                          "GPIO18",
+                          "GPIO19",
+                          "GPIO20",
+                          "GPIO21",
+                          "GPIO22",
+                          "GPIO23",
+                          "GPIO24",
+                          "GPIO25",
+                          "GPIO26",
+                          "GPIO27",
+                          "HDMI_HPD_N",
+                          "STATUS_LED_G",
+                          /* Used by BT module */
+                          "CTS0",
+                          "RTS0",
+                          "TXD0",
+                          "RXD0",
+                          /* Used by Wifi */
+                          "SD1_CLK",
+                          "SD1_CMD",
+                          "SD1_DATA0",
+                          "SD1_DATA1",
+                          "SD1_DATA2",
+                          "SD1_DATA3",
+                          "PWM0_OUT",
+                          "PWM1_OUT",
+                          "", /* GPIO42 */
+                          "WIFI_CLK",
+                          "SDA0",
+                          "SCL0",
+                          "SMPS_SCL",
+                          "SMPS_SDA",
+                          /* Used by SD Card */
+                          "SD_CLK_R",
+                          "SD_CMD_R",
+                          "SD_DATA0_R",
+                          "SD_DATA1_R",
+                          "SD_DATA2_R",
+                          "SD_DATA3_R";
+};
+
+&hdmi {
+        hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
+};
+
+&pwm {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>;
+        status = "okay";
+};
+
+/*
+ * SDHCI is used to control the SDIO for wireless
+ *
+ * WL_REG_ON and BT_REG_ON of the CYW43455 Wifi/BT module are driven
+ * by a single GPIO. We can't give GPIO control to one of the drivers,
+ * otherwise the other part would get unexpectedly disturbed.
+ */
+&sdhci {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&emmc_gpio34>;
+        status = "okay";
+        bus-width = <4>;
+        non-removable;
+
+        brcmf: wifi@1 {
+                reg = <1>;
+                compatible = "brcm,bcm4329-fmac";
+        };
+};
+
+/* SDHOST is used to drive the SD card */
+&sdhost {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sdhost_gpio48>;
+        status = "okay";
+        bus-width = <4>;
+};
+
+/* uart0 communicates with the BT module */
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>;
+        status = "okay";
+
+        bluetooth {
+                compatible = "brcm,bcm43438-bt";
+                max-speed = <2000000>;
+        };
+};
+
+/* uart1 is mapped to the pin header */
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart1_gpio14>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
index 42bb09044cc7..c6fa34c24100 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
@@ -14,7 +14,7 @@
                 stdout-path = "serial1:115200n8";
         };
 
-        memory {
+        memory@0 {
                 reg = <0 0x40000000>;
         };
 
@@ -42,7 +42,7 @@
                 #gpio-cells = <2>;
                 gpio-line-names = "BT_ON",
                                   "WL_ON",
-                                  "STATUS_LED",
+                                  "STATUS_LED_R",
                                   "LAN_RUN",
                                   "",
                                   "CAM_GPIO0",
@@ -52,6 +52,76 @@
         };
 };
 
+&gpio {
+        /*
+         * Taken from rpi_SCH_3bplus_1p0_reduced.pdf and
+         * the official GPU firmware DT blob.
+         *
+         * Legend:
+         * "NC" = not connected (no rail from the SoC)
+         * "FOO" = GPIO line named "FOO" on the schematic
+         * "FOO_N" = GPIO line named "FOO" on schematic, active low
+         */
+        gpio-line-names = "ID_SDA",
+                          "ID_SCL",
+                          "SDA1",
+                          "SCL1",
+                          "GPIO_GCLK",
+                          "GPIO5",
+                          "GPIO6",
+                          "SPI_CE1_N",
+                          "SPI_CE0_N",
+                          "SPI_MISO",
+                          "SPI_MOSI",
+                          "SPI_SCLK",
+                          "GPIO12",
+                          "GPIO13",
+                          /* Serial port */
+                          "TXD1",
+                          "RXD1",
+                          "GPIO16",
+                          "GPIO17",
+                          "GPIO18",
+                          "GPIO19",
+                          "GPIO20",
+                          "GPIO21",
+                          "GPIO22",
+                          "GPIO23",
+                          "GPIO24",
+                          "GPIO25",
+                          "GPIO26",
+                          "GPIO27",
+                          "HDMI_HPD_N",
+                          "STATUS_LED_G",
+                          /* Used by BT module */
+                          "CTS0",
+                          "RTS0",
+                          "TXD0",
+                          "RXD0",
+                          /* Used by Wifi */
+                          "SD1_CLK",
+                          "SD1_CMD",
+                          "SD1_DATA0",
+                          "SD1_DATA1",
+                          "SD1_DATA2",
+                          "SD1_DATA3",
+                          "PWM0_OUT",
+                          "PWM1_OUT",
+                          "ETHCLK",
+                          "WIFI_CLK",
+                          "SDA0",
+                          "SCL0",
+                          "SMPS_SCL",
+                          "SMPS_SDA",
+                          /* Used by SD Card */
+                          "SD_CLK_R",
+                          "SD_CMD_R",
+                          "SD_DATA0_R",
+                          "SD_DATA1_R",
+                          "SD_DATA2_R",
+                          "SD_DATA3_R";
+};
+
 &hdmi {
         hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
 };
diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
index 0c155dd4f396..ce71f578c51a 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
@@ -14,7 +14,7 @@
                 stdout-path = "serial1:115200n8";
         };
 
-        memory {
+        memory@0 {
                 reg = <0 0x40000000>;
         };
 
@@ -39,7 +39,7 @@
                                   "WL_ON",
                                   "STATUS_LED",
                                   "LAN_RUN",
-                                  "HPD_N",
+                                  "HDMI_HPD_N",
                                   "CAM_GPIO0",
                                   "CAM_GPIO1",
                                   "PWR_LOW_N";
@@ -47,6 +47,76 @@
         };
 };
 
+&gpio {
+        /*
+         * Taken from rpi_SCH_3b_1p2_reduced.pdf and
+         * the official GPU firmware DT blob.
+         *
+         * Legend:
+         * "NC" = not connected (no rail from the SoC)
+         * "FOO" = GPIO line named "FOO" on the schematic
+         * "FOO_N" = GPIO line named "FOO" on schematic, active low
+         */
+        gpio-line-names = "ID_SDA",
+                          "ID_SCL",
+                          "SDA1",
+                          "SCL1",
+                          "GPIO_GCLK",
+                          "GPIO5",
+                          "GPIO6",
+                          "SPI_CE1_N",
+                          "SPI_CE0_N",
+                          "SPI_MISO",
+                          "SPI_MOSI",
+                          "SPI_SCLK",
+                          "GPIO12",
+                          "GPIO13",
+                          /* Serial port */
+                          "TXD1",
+                          "RXD1",
+                          "GPIO16",
+                          "GPIO17",
+                          "GPIO18",
+                          "GPIO19",
+                          "GPIO20",
+                          "GPIO21",
+                          "GPIO22",
+                          "GPIO23",
+                          "GPIO24",
+                          "GPIO25",
+                          "GPIO26",
+                          "GPIO27",
+                          "", /* GPIO 28 */
+                          "LAN_RUN_BOOT",
+                          /* Used by BT module */
+                          "CTS0",
+                          "RTS0",
+                          "TXD0",
+                          "RXD0",
+                          /* Used by Wifi */
+                          "SD1_CLK",
+                          "SD1_CMD",
+                          "SD1_DATA0",
+                          "SD1_DATA1",
+                          "SD1_DATA2",
+                          "SD1_DATA3",
+                          "PWM0_OUT",
+                          "PWM1_OUT",
+                          "ETHCLK",
+                          "WIFI_CLK",
+                          "SDA0",
+                          "SCL0",
+                          "SMPS_SCL",
+                          "SMPS_SDA",
+                          /* Used by SD Card */
+                          "SD_CLK_R",
+                          "SD_CMD_R",
+                          "SD_DATA0_R",
+                          "SD_DATA1_R",
+                          "SD_DATA2_R",
+                          "SD_DATA3_R";
+};
+
 &pwm {
         pinctrl-names = "default";
         pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>;
diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
index 4a89a1885a3d..81399b2c5af9 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
+++ b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
@@ -4,7 +4,7 @@
 #include "bcm2836-rpi.dtsi"
 
 / {
-        memory {
+        memory@0 {
                 reg = <0 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index 31b29646b14c..9777644c6c2b 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -3,6 +3,7 @@
 #include <dt-bindings/clock/bcm2835-aux.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/soc/bcm2835-pm.h>
 
 /* firmware-provided startup stubs live here, where the secondary CPUs are
  * spinning.
@@ -120,9 +121,18 @@
                         #interrupt-cells = <2>;
                 };
 
-                watchdog@7e100000 {
-                        compatible = "brcm,bcm2835-pm-wdt";
-                        reg = <0x7e100000 0x28>;
+                pm: watchdog@7e100000 {
+                        compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
+                        #power-domain-cells = <1>;
+                        #reset-cells = <1>;
+                        reg = <0x7e100000 0x114>,
+                              <0x7e00a000 0x24>;
+                        clocks = <&clocks BCM2835_CLOCK_V3D>,
+                                 <&clocks BCM2835_CLOCK_PERI_IMAGE>,
+                                 <&clocks BCM2835_CLOCK_H264>,
+                                 <&clocks BCM2835_CLOCK_ISP>;
+                        clock-names = "v3d", "peri_image", "h264", "isp";
+                        system-power-controller;
                 };
 
                 clocks: cprman@7e101000 {
@@ -629,6 +639,7 @@
                         compatible = "brcm,bcm2835-v3d";
                         reg = <0x7ec00000 0x1000>;
                         interrupts = <1 10>;
+                        power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
                 };
 
                 vc4: gpu {
diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
index 76a2bab3bc6f..fe842f2f1ca7 100644
--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
+++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
@@ -20,6 +20,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x08000000
                        0x88000000 0x08000000>;
         };
diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
index 69e3570e03dd..6fcbb0509ba0 100644
--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
@@ -20,6 +20,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x08000000
                        0x88000000 0x08000000>;
         };
diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
index 0f6f0fe13bfb..b3e8cc90b13f 100644
--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
@@ -20,6 +20,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x08000000
                        0x88000000 0x08000000>;
         };
diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
index f77089744996..fdeaa895512f 100644
--- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
+++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
@@ -16,6 +16,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
index 4d427863756f..0d510cb15ec3 100644
--- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
+++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
@@ -17,6 +17,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
index 189cc3dcd6ef..962e89edba11 100644
--- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
+++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
@@ -16,6 +16,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
index 03c1ab188576..658a56ff8a5c 100644
--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
@@ -20,6 +20,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x08000000
                        0x88000000 0x08000000>;
         };
diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
index 36efe410dcd7..5fd47eec4407 100644
--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
@@ -17,6 +17,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x08000000
                        0x88000000 0x08000000>;
         };
diff --git a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
index 3e5e9972cd97..6604be6ff0a0 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
@@ -17,6 +17,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x08000000
                        0x88000000 0x18000000>;
         };
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts
index 7fd85475893d..567ebbd5a0e9 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts
@@ -16,6 +16,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
index 7acbecd42950..ac2d136ed334 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
@@ -17,6 +17,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x08000000
                        0x88000000 0x18000000>;
         };
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
index f4558d9d2769..74371e821b1a 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
@@ -17,6 +17,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x08000000
                        0x88000000 0x08000000>;
         };
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
index bdad7267255a..b44af63ee310 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
@@ -17,6 +17,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x08000000
                        0x88000000 0x18000000>;
         };
diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
index 30719380b6c0..eebc0d43e220 100644
--- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
+++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
@@ -17,6 +17,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x08000000
                        0x88000000 0x18000000>;
         };
diff --git a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts
new file mode 100644
index 000000000000..ec09c0426d16
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2017 Hamster Tian <haotia@gmail.com>
+ * Copyright (C) 2019 Hao Dong <halbertdong@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm47094.dtsi"
+#include "bcm5301x-nand-cs0-bch4.dtsi"
+
+/ {
+        compatible = "phicomm,k3", "brcm,bcm47094", "brcm,bcm4708";
+        model = "Phicomm K3";
+
+        memory {
+                reg = <0x00000000 0x08000000
+                       0x88000000 0x18000000>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                restart {
+                        label = "Reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&usb3_phy {
+        status = "okay";
+};
+
+&nandcs {
+        partitions {
+                compatible = "fixed-partitions";
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                partition@0 {
+                        label = "boot";
+                        reg = <0x0000000 0x0080000>;
+                        read-only;
+                };
+
+                partition@80000 {
+                        label = "nvram";
+                        reg = <0x0080000 0x0100000>;
+                };
+
+                partition@180000{
+                        label = "phicomm";
+                        reg = <0x0180000 0x0280000>;
+                        read-only;
+                };
+
+                partition@400000 {
+                        label = "firmware";
+                        reg = <0x0400000 0x7C00000>;
+                        compatible = "brcm,trx";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts
index 74c83b0ca54e..eb59508578e4 100644
--- a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts
+++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
  * Copyright 2017 Luxul Inc.
- *
- * Licensed under the ISC license.
  */
 
 /dts-v1/;
@@ -17,6 +16,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts
index 214df18f3a75..4c71f5e95e00 100644
--- a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts
+++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
  * Copyright 2017 Luxul Inc.
- *
- * Licensed under the ISC license.
  */
 
 /dts-v1/;
@@ -17,6 +16,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
index e15e2a1e9d8c..5ad53ea52d0a 100644
--- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
+++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
@@ -16,6 +16,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index fd7af943fb0b..ac5266ee8d4c 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -13,9 +13,10 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         interrupt-parent = <&gic>;
 
         chipcommonA {
diff --git a/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts b/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts
index 431cda514230..2e7fda9b998c 100644
--- a/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts
+++ b/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts
@@ -20,6 +20,7 @@
         };
 
         memory@0 {
+                device_type = "memory";
                 reg = <0x00000000 0x08000000>,
                       <0x68000000 0x08000000>;
         };
diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi
index 5054fa9eb0d0..b29695bd4855 100644
--- a/arch/arm/boot/dts/bcm53573.dtsi
+++ b/arch/arm/boot/dts/bcm53573.dtsi
@@ -7,9 +7,10 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         interrupt-parent = <&gic>;
 
         aliases {
diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi
index f59764008b9c..e6a41e1b27fd 100644
--- a/arch/arm/boot/dts/bcm63138.dtsi
+++ b/arch/arm/boot/dts/bcm63138.dtsi
@@ -6,9 +6,9 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
-#include "skeleton.dtsi"
-
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "brcm,bcm63138";
         model = "Broadcom BCM63138 DSL SoC";
         interrupt-parent = <&gic>;
diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi
index c859aa6f358c..504a63236a5e 100644
--- a/arch/arm/boot/dts/bcm7445.dtsi
+++ b/arch/arm/boot/dts/bcm7445.dtsi
@@ -1,8 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
-#include "skeleton.dtsi"
-
 / {
         #address-cells = <2>;
         #size-cells = <2>;
diff --git a/arch/arm/boot/dts/bcm947189acdbmr.dts b/arch/arm/boot/dts/bcm947189acdbmr.dts
index ef263412fea5..4991700ae6b0 100644
--- a/arch/arm/boot/dts/bcm947189acdbmr.dts
+++ b/arch/arm/boot/dts/bcm947189acdbmr.dts
@@ -18,6 +18,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/bcm953012er.dts
index 17f63c7a0437..250a1d6f2d05 100644
--- a/arch/arm/boot/dts/bcm953012er.dts
+++ b/arch/arm/boot/dts/bcm953012er.dts
@@ -40,6 +40,7 @@
         compatible = "brcm,bcm953012er", "brcm,brcm53012", "brcm,bcm4708";
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x8000000>;
         };
 
diff --git a/arch/arm/boot/dts/bcm953012hr.dts b/arch/arm/boot/dts/bcm953012hr.dts
index 11b0f5ed99e6..9140be7ec053 100644
--- a/arch/arm/boot/dts/bcm953012hr.dts
+++ b/arch/arm/boot/dts/bcm953012hr.dts
@@ -46,6 +46,7 @@
         };
 
         memory@80000000 {
+                device_type = "memory";
                 reg = <0x80000000 0x10000000>;
         };
 };
diff --git a/arch/arm/boot/dts/bcm953012k.dts b/arch/arm/boot/dts/bcm953012k.dts
index e798055d6989..52c4c6c9d3f1 100644
--- a/arch/arm/boot/dts/bcm953012k.dts
+++ b/arch/arm/boot/dts/bcm953012k.dts
@@ -44,6 +44,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x80000000 0x10000000>;
         };
 };
diff --git a/arch/arm/boot/dts/cx92755.dtsi b/arch/arm/boot/dts/cx92755.dtsi
index a5a23c376418..d2e8f36f8c60 100644
--- a/arch/arm/boot/dts/cx92755.dtsi
+++ b/arch/arm/boot/dts/cx92755.dtsi
@@ -44,9 +44,9 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include "skeleton.dtsi"
-
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "cnxt,cx92755";
 
         interrupt-parent = <&intc>;
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index a3c9b346721d..f04bc3e15332 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -94,6 +94,28 @@
                 regulator-boot-on;
         };
 
+        baseboard_3v3: fixedregulator-3v3 {
+                /* TPS73701DCQ */
+                compatible = "regulator-fixed";
+                regulator-name = "baseboard_3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                vin-supply = <&vbat>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
+        baseboard_1v8: fixedregulator-1v8 {
+                /* TPS73701DCQ */
+                compatible = "regulator-fixed";
+                regulator-name = "baseboard_1v8";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                vin-supply = <&vbat>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
         backlight_lcd: backlight-regulator {
                 compatible = "regulator-fixed";
                 regulator-name = "lcd_backlight_pwr";
@@ -105,7 +127,7 @@
 
         sound {
                 compatible = "simple-audio-card";
-                simple-audio-card,name = "DA850/OMAP-L138 EVM";
+                simple-audio-card,name = "DA850-OMAPL138 EVM";
                 simple-audio-card,widgets =
                         "Line", "Line In",
                         "Line", "Line Out";
@@ -210,10 +232,9 @@
 
                 /* Regulators */
                 IOVDD-supply = <&vdcdc2_reg>;
-                /* Derived from VBAT: Baseboard 3.3V / 1.8V */
-                AVDD-supply = <&vbat>;
-                DRVDD-supply = <&vbat>;
-                DVDD-supply = <&vbat>;
+                AVDD-supply = <&baseboard_3v3>;
+                DRVDD-supply = <&baseboard_3v3>;
+                DVDD-supply = <&baseboard_1v8>;
         };
         tca6416: gpio@20 {
                 compatible = "ti,tca6416";
diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts
index 0177e3ed20fe..26f453dc8370 100644
--- a/arch/arm/boot/dts/da850-lcdk.dts
+++ b/arch/arm/boot/dts/da850-lcdk.dts
@@ -39,17 +39,51 @@
                 };
         };
 
+        vcc_5vd: fixedregulator-vcc_5vd {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc_5vd";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+        };
+
+        vcc_3v3d: fixedregulator-vcc_3v3d {
+                /* TPS650250 - VDCDC1 */
+                compatible = "regulator-fixed";
+                regulator-name = "vcc_3v3d";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                vin-supply = <&vcc_5vd>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
+        vcc_1v8d: fixedregulator-vcc_1v8d {
+                /* TPS650250 - VDCDC2 */
+                compatible = "regulator-fixed";
+                regulator-name = "vcc_1v8d";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                vin-supply = <&vcc_5vd>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
         sound {
                 compatible = "simple-audio-card";
-                simple-audio-card,name = "DA850/OMAP-L138 LCDK";
+                simple-audio-card,name = "DA850-OMAPL138 LCDK";
                 simple-audio-card,widgets =
                         "Line", "Line In",
-                        "Line", "Line Out";
+                        "Line", "Line Out",
+                        "Microphone", "Mic Jack";
                 simple-audio-card,routing =
                         "LINE1L", "Line In",
                         "LINE1R", "Line In",
                         "Line Out", "LLOUT",
-                        "Line Out", "RLOUT";
+                        "Line Out", "RLOUT",
+                        "MIC3L", "Mic Jack",
+                        "MIC3R", "Mic Jack",
+                        "Mic Jack", "Mic Bias";
                 simple-audio-card,format = "dsp_b";
                 simple-audio-card,bitclock-master = <&link0_codec>;
                 simple-audio-card,frame-master = <&link0_codec>;
@@ -220,7 +254,15 @@
                 #sound-dai-cells = <0>;
                 compatible = "ti,tlv320aic3106";
                 reg = <0x18>;
+                adc-settle-ms = <40>;
+                ai3x-micbias-vg = <1>;          /* 2.0V */
                 status = "okay";
+
+                /* Regulators */
+                IOVDD-supply = <&vcc_3v3d>;
+                AVDD-supply = <&vcc_3v3d>;
+                DRVDD-supply = <&vcc_3v3d>;
+                DVDD-supply = <&vcc_1v8d>;
         };
 };
 
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 47aa53ba6b92..559659b399d0 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -476,7 +476,7 @@
                 clocksource: timer@20000 {
                         compatible = "ti,da830-timer";
                         reg = <0x20000 0x1000>;
-                        interrupts = <12>, <13>;
+                        interrupts = <21>, <22>;
                         interrupt-names = "tint12", "tint34";
                         clocks = <&pll0_auxclk>;
                 };
diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi
index 601c57afd4fe..95de9f214c14 100644
--- a/arch/arm/boot/dts/dm814x.dtsi
+++ b/arch/arm/boot/dts/dm814x.dtsi
@@ -222,6 +222,30 @@
                                 #interrupt-cells = <2>;
                         };
 
+                        gpio3: gpio@1ac000 {
+                                compatible = "ti,omap4-gpio";
+                                ti,hwmods = "gpio3";
+                                ti,gpio-always-on;
+                                reg = <0x1ac000 0x2000>;
+                                interrupts = <32>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        gpio4: gpio@1ae000 {
+                                compatible = "ti,omap4-gpio";
+                                ti,hwmods = "gpio4";
+                                ti,gpio-always-on;
+                                reg = <0x1ae000 0x2000>;
+                                interrupts = <62>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
                         i2c2: i2c@2a000 {
                                 compatible = "ti,omap4-i2c";
                                 #address-cells = <1>;
@@ -240,10 +264,48 @@
                                 ti,spi-num-cs = <4>;
                                 ti,hwmods = "mcspi1";
                                 dmas = <&edma 16 0 &edma 17 0
-                                        &edma 18 0 &edma 19 0>;
+                                        &edma 18 0 &edma 19 0
+                                        &edma 20 0 &edma 21 0
+                                        &edma 22 0 &edma 23 0>;
+
+                                dma-names = "tx0", "rx0", "tx1", "rx1",
+                                        "tx2", "rx2", "tx3", "rx3";
+                        };
+
+                        mcspi2: spi@1a0000 {
+                                compatible = "ti,omap4-mcspi";
+                                reg = <0x1a0000 0x1000>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <125>;
+                                ti,spi-num-cs = <4>;
+                                ti,hwmods = "mcspi2";
+                                dmas = <&edma 42 0 &edma 43 0
+                                        &edma 44 0 &edma 45 0>;
                                 dma-names = "tx0", "rx0", "tx1", "rx1";
                         };
 
+                        /* Board must configure dmas with edma_xbar for EDMA */
+                        mcspi3: spi@1a2000 {
+                                compatible = "ti,omap4-mcspi";
+                                reg = <0x1a2000 0x1000>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <126>;
+                                ti,spi-num-cs = <4>;
+                                ti,hwmods = "mcspi3";
+                        };
+
+                        mcspi4: spi@1a4000 {
+                                compatible = "ti,omap4-mcspi";
+                                reg = <0x1a4000 0x1000>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                interrupts = <127>;
+                                ti,spi-num-cs = <4>;
+                                ti,hwmods = "mcspi4";
+                        };
+
                         timer1: timer@2e000 {
                                 compatible = "ti,dm814-timer";
                                 reg = <0x2e000 0x2000>;
@@ -343,6 +405,12 @@
                                         #size-cells = <1>;
                                         ranges = <0 0 0x800>;
 
+                                        phy_gmii_sel: phy-gmii-sel {
+                                                compatible = "ti,dm814-phy-gmii-sel";
+                                                reg = <0x650 0x4>;
+                                                #phy-cells = <1>;
+                                        };
+
                                         scm_clocks: clocks {
                                                 #address-cells = <1>;
                                                 #size-cells = <0>;
@@ -549,17 +617,14 @@
                         cpsw_emac0: slave@4a100200 {
                                 /* Filled in by U-Boot */
                                 mac-address = [ 00 00 00 00 00 00 ];
+                                phys = <&phy_gmii_sel 1>;
+
                         };
 
                         cpsw_emac1: slave@4a100300 {
                                 /* Filled in by U-Boot */
                                 mac-address = [ 00 00 00 00 00 00 ];
-                        };
-
-                        phy_sel: cpsw-phy-sel@48140650 {
-                                compatible = "ti,am3352-cpsw-phy-sel";
-                                reg= <0x48140650 0x4>;
-                                reg-names = "gmii-sel";
+                                phys = <&phy_gmii_sel 2>;
                         };
                 };
 
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 250ad0535e8c..2e8a3977219f 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -1,12 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0
-/include/ "skeleton.dtsi"
-
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "marvell,dove";
         model = "Marvell Armada 88AP510 SoC";
         interrupt-parent = <&intc>;
diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi
index bb45cb7fc3b6..414f1cd68733 100644
--- a/arch/arm/boot/dts/dra7-l4.dtsi
+++ b/arch/arm/boot/dts/dra7-l4.dtsi
@@ -77,18 +77,18 @@
                                                 };
                                         };
 
+                                        phy_gmii_sel: phy-gmii-sel {
+                                                compatible = "ti,dra7xx-phy-gmii-sel";
+                                                reg = <0x554 0x4>;
+                                                #phy-cells = <1>;
+                                        };
+
                                         scm_conf_clocks: clocks {
                                                 #address-cells = <1>;
                                                 #size-cells = <0>;
                                         };
                                 };
 
-                                phy_sel: cpsw-phy-sel@554 {
-                                        compatible = "ti,dra7xx-cpsw-phy-sel";
-                                        reg= <0x554 0x4>;
-                                        reg-names = "gmii-sel";
-                                };
-
                                 dra7_pmx_core: pinmux@1400 {
                                         compatible = "ti,dra7-padconf",
                                                      "pinctrl-single";
@@ -3099,7 +3099,6 @@
                                              <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
                                 ranges = <0 0 0x4000>;
                                 syscon = <&scm_conf>;
-                                cpsw-phy-sel = <&phy_sel>;
                                 status = "disabled";
 
                                 davinci_mdio: mdio@1000 {
@@ -3114,11 +3113,13 @@
                                 cpsw_emac0: slave@200 {
                                         /* Filled in by U-Boot */
                                         mac-address = [ 00 00 00 00 00 00 ];
+                                        phys = <&phy_gmii_sel 1>;
                                 };
 
                                 cpsw_emac1: slave@300 {
                                         /* Filled in by U-Boot */
                                         mac-address = [ 00 00 00 00 00 00 ];
+                                        phys = <&phy_gmii_sel 2>;
                                 };
                         };
                 };
diff --git a/arch/arm/boot/dts/ep7209.dtsi b/arch/arm/boot/dts/ep7209.dtsi
index aaf1261d2ee4..0e74222a5eae 100644
--- a/arch/arm/boot/dts/ep7209.dtsi
+++ b/arch/arm/boot/dts/ep7209.dtsi
@@ -6,11 +6,11 @@
 
 /dts-v1/;
 
-#include "skeleton.dtsi"
-
 #include <dt-bindings/clock/clps711x-clock.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Cirrus Logic EP7209";
         compatible = "cirrus,ep7209";
 
diff --git a/arch/arm/boot/dts/ep7211-edb7211.dts b/arch/arm/boot/dts/ep7211-edb7211.dts
index bc9d5b697452..3475c7777cbc 100644
--- a/arch/arm/boot/dts/ep7211-edb7211.dts
+++ b/arch/arm/boot/dts/ep7211-edb7211.dts
@@ -12,6 +12,7 @@
         compatible = "cirrus,edb7211", "cirrus,ep7211", "cirrus,ep7209";
 
         memory {
+                device_type = "memory";
                 reg = <0xc0000000 0x02000000>;
         };
 
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 608d17454179..5892a9f7622f 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -168,6 +168,9 @@
                         interrupt-controller;
                         #interrupt-cells = <3>;
                         interrupt-parent = <&gic>;
+                        clock-names = "clkout8";
+                        clocks = <&cmu CLK_FIN_PLL>;
+                        #clock-cells = <1>;
                 };
 
                 mipi_phy: video-phy {
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 3a9eb1e91c45..08d3a0a7b4eb 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -49,7 +49,7 @@
         };
 
         emmc_pwrseq: pwrseq {
-                pinctrl-0 = <&sd1_cd>;
+                pinctrl-0 = <&emmc_rstn>;
                 pinctrl-names = "default";
                 compatible = "mmc-pwrseq-emmc";
                 reset-gpios = <&gpk1 2 GPIO_ACTIVE_LOW>;
@@ -165,12 +165,6 @@
         cpu0-supply = <&buck2_reg>;
 };
 
-/* RSTN signal for eMMC */
-&sd1_cd {
-        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-};
-
 &pinctrl_1 {
         gpio_power_key: power_key {
                 samsung,pins = "gpx1-3";
@@ -188,6 +182,11 @@
                 samsung,pins = "gpx3-7";
                 samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
         };
+
+        emmc_rstn: emmc-rstn {
+                samsung,pins = "gpk1-2";
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+        };
 };
 
 &ehci {
@@ -390,7 +389,6 @@
                                 regulator-name = "LDO20_1.8V";
                                 regulator-min-microvolt = <1800000>;
                                 regulator-max-microvolt = <1800000>;
-                                regulator-boot-on;
                         };
 
                         ldo21_reg: LDO21 {
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 348556fcdd9d..a2251581f6b6 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -53,7 +53,7 @@
                 regulator-name = "p3v3_en";
                 regulator-min-microvolt = <3300000>;
                 regulator-max-microvolt = <3300000>;
-                gpio = <&gpa1 1 GPIO_ACTIVE_LOW>;
+                gpio = <&gpa1 1 GPIO_ACTIVE_HIGH>;
                 enable-active-high;
                 regulator-always-on;
         };
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 2ca9319f48f2..dc6fa6fe83f1 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -23,7 +23,7 @@
         };
 
         chosen {
-                bootargs = "console=ttySAC2,115200";
+                stdout-path = "serial2:115200n8";
         };
 
         gpio_keys {
@@ -100,7 +100,7 @@
                         regulator-name = "VDD_33ON_2.8V";
                         regulator-min-microvolt = <2800000>;
                         regulator-max-microvolt = <2800000>;
-                        gpio = <&gpx1 1 GPIO_ACTIVE_LOW>;
+                        gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
 
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index bf09eab90f8a..25d95de15c9b 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -36,6 +36,11 @@
         };
 };
 
+&adc {
+        vdd-supply = <&ldo4_reg>;
+        status = "okay";
+};
+
 &bus_wcore {
         devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
                         <&nocp_mem1_0>, <&nocp_mem1_1>;
@@ -468,7 +473,7 @@
                         buck8_reg: BUCK8 {
                                 regulator-name = "vdd_1.8v_ldo";
                                 regulator-min-microvolt = <800000>;
-                                regulator-max-microvolt = <1500000>;
+                                regulator-max-microvolt = <2000000>;
                                 regulator-always-on;
                                 regulator-boot-on;
                         };
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
index e84544b220b9..51a843bd65ed 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
@@ -24,7 +24,9 @@
                         "Headphone Jack", "MICBIAS",
                         "IN1", "Headphone Jack",
                         "Speakers", "SPKL",
-                        "Speakers", "SPKR";
+                        "Speakers", "SPKR",
+                        "I2S Playback", "Mixer DAI TX",
+                        "HiFi Playback", "Mixer DAI TX";
 
                 assigned-clocks = <&clock CLK_MOUT_EPLL>,
                                 <&clock CLK_MOUT_MAU_EPLL>,
@@ -51,7 +53,7 @@
                                 <196608000>;
 
                 cpu {
-                        sound-dai = <&i2s0 0>;
+                        sound-dai = <&i2s0 0>, <&i2s0 1>;
                 };
                 codec {
                         sound-dai = <&hdmi>, <&max98090>;
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index b299e541cac0..5f195ad7e467 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -362,11 +362,6 @@
         };
 };
 
-&adc {
-        vdd-supply = <&ldo4_reg>;
-        status = "okay";
-};
-
 &hdmi {
         status = "okay";
         ddc = <&i2c_2>;
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
index 0db935f2b836..c19b5a51ca44 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
@@ -18,6 +18,14 @@
         compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5";
 };
 
+&arm_a7_pmu {
+        status = "disabled";
+};
+
+&arm_a15_pmu {
+        status = "disabled";
+};
+
 &pwm {
         /*
          * PWM 0 -- fan
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
index 122174ea9e0a..892d389d6d09 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
@@ -33,6 +33,8 @@
                 compatible = "samsung,odroid-xu3-audio";
                 model = "Odroid-XU4";
 
+                samsung,audio-routing = "I2S Playback", "Mixer DAI TX";
+
                 assigned-clocks = <&clock CLK_MOUT_EPLL>,
                                 <&clock CLK_MOUT_MAU_EPLL>,
                                 <&clock CLK_MOUT_USER_MAU_EPLL>,
@@ -58,7 +60,7 @@
                                 <196608000>;
 
                 cpu {
-                        sound-dai = <&i2s0 0>;
+                        sound-dai = <&i2s0 0>, <&i2s0 1>;
                 };
 
                 codec {
diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
index cc0c3cf89eaa..592111c8d6fd 100644
--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts
+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
@@ -443,7 +443,7 @@
                 };
 
                 display-controller@6a000000 {
-                        status = "disabled";
+                        status = "okay";
 
                         port@0 {
                                 reg = <0>;
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 26ff5d419bfc..3652f5556b29 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -40,7 +40,7 @@
                 spi2 = &cspi3;
         };
 
-        aitc: aitc-interrupt-controller@e0000000 {
+        aitc: aitc-interrupt-controller@10040000 {
                 compatible = "fsl,imx27-aitc", "fsl,avic";
                 interrupt-controller;
                 #interrupt-cells = <1>;
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index d3e3622979c5..de48b5808ef6 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -11,6 +11,7 @@
 
 /dts-v1/;
 #include "imx28.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         model = "Crystalfontz CFA-10036 Board";
@@ -96,7 +97,7 @@
                                         pinctrl-names = "default";
                                         pinctrl-0 = <&ssd1306_cfa10036>;
                                         reg = <0x3c>;
-                                        reset-gpios = <&gpio2 7 0>;
+                                        reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
                                         solomon,height = <32>;
                                         solomon,width = <128>;
                                         solomon,page-offset = <0>;
diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts
index 2967a748d859..a2eea58510dc 100644
--- a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts
+++ b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts
@@ -21,12 +21,28 @@
         };
 };
 
+&esdhc1 {
+        status = "okay";
+};
+
 &owire {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_owire>;
         status = "okay";
 };
 
+&pmic {
+        fsl,mc13xxx-uses-rtc;
+
+        regulators {
+                vcoincell_reg: vcoincell {
+                        regulator-min-microvolt = <3000000>;
+                        regulator-max-microvolt = <3000000>;
+                        regulator-always-on;
+                };
+        };
+};
+
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1>;
diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
index 82d8df097ef1..d90ba5fe4f1b 100644
--- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
+++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
@@ -37,7 +37,6 @@
                 reg = <0>;
                 interrupt-parent = <&gpio1>;
                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
-                fsl,mc13xxx-uses-rtc;
 
                 regulators {
                         sw1_reg: sw1 {
@@ -142,16 +141,17 @@
                         pwgt2spi_reg: pwgt2spi {
                                 regulator-always-on;
                         };
-
-                        vcoincell_reg: vcoincell {
-                                regulator-min-microvolt = <3000000>;
-                                regulator-max-microvolt = <3000000>;
-                                regulator-always-on;
-                        };
                 };
         };
 };
 
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1>;
+        max-frequency = <50000000>;
+        bus-width = <1>;
+};
+
 &esdhc2 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_esdhc2>;
@@ -174,9 +174,12 @@
 };
 
 &i2c2 {
-        pinctrl-names = "default";
+        pinctrl-names = "default", "gpio";
         pinctrl-0 = <&pinctrl_i2c2>;
+        pinctrl-1 = <&pinctrl_i2c2_gpio>;
         clock-frequency = <400000>;
+        scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+        sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
         status = "okay";
 
         mma7455l@1d {
@@ -241,6 +244,14 @@
                         >;
                 };
 
+                pinctrl_esdhc1: esdhc1grp {
+                        fsl,pins = <
+                                MX51_PAD_SD1_CLK__SD1_CLK               0x400021d5
+                                MX51_PAD_SD1_CMD__SD1_CMD               0x400020d5
+                                MX51_PAD_SD1_DATA0__SD1_DATA0           0x400020d5
+                        >;
+                };
+
                 pinctrl_esdhc2: esdhc2grp {
                         fsl,pins = <
                                 MX51_PAD_SD2_CMD__SD2_CMD               0x400020d5
@@ -282,6 +293,13 @@
                         >;
                 };
 
+                pinctrl_i2c2_gpio: i2c2gpiogrp {
+                        fsl,pins = <
+                                MX51_PAD_GPIO1_2__GPIO1_2               0x400001ed
+                                MX51_PAD_GPIO1_3__GPIO1_3               0x400001ed
+                        >;
+                };
+
                 pinctrl_nfc: nfcgrp {
                         fsl,pins = <
                                 MX51_PAD_NANDF_D0__NANDF_D0             0x80000000
diff --git a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi
new file mode 100644
index 000000000000..fb01fa6e4224
--- /dev/null
+++ b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi
@@ -0,0 +1,555 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2019 Logic PD, Inc.
+
+/ {
+        keyboard {
+                compatible = "gpio-keys";
+
+                btn0 {
+                        gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>;
+                        label = "btn0";
+                        linux,code = <KEY_WAKEUP>;
+                        debounce-interval = <10>;
+                        wakeup-source;
+                };
+
+                btn1 {
+                        gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>;
+                        label = "btn1";
+                        linux,code = <KEY_WAKEUP>;
+                        debounce-interval = <10>;
+                        wakeup-source;
+                };
+
+                btn2 {
+                        gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>;
+                        label = "btn2";
+                        linux,code = <KEY_WAKEUP>;
+                        debounce-interval = <10>;
+                        wakeup-source;
+                };
+
+                btn3 {
+                        gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>;
+                        label = "btn3";
+                        linux,code = <KEY_WAKEUP>;
+                        debounce-interval = <10>;
+                        wakeup-source;
+                };
+
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                gen-led0 {
+                        label = "led0";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_led0>;
+                        gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "cpu0";
+                };
+
+                gen-led1 {
+                        label = "led1";
+                        gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>;
+                };
+
+                gen-led2 {
+                        label = "led2";
+                        gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+
+                gen-led3 {
+                        label = "led3";
+                        gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+        };
+
+        reg_usb_otg_vbus: regulator-otg-vbus {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_reg_usb_otg>;
+                compatible = "regulator-fixed";
+                regulator-name = "usb_otg_vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        reg_usb_h1_vbus: regulator-usb-h1-vbus {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
+                compatible = "regulator-fixed";
+                regulator-name = "usb_h1_vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        reg_3v3: regulator-3v3 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_reg_3v3>;
+                compatible = "regulator-fixed";
+                regulator-name = "reg_3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                regulator-always-on;
+        };
+
+        reg_enet: regulator-ethernet {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_reg_enet>;
+                compatible = "regulator-fixed";
+                regulator-name = "ethernet-supply";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
+                startup-delay-us = <70000>;
+                enable-active-high;
+                vin-supply = <&sw4_reg>;
+        };
+
+        reg_audio: regulator-audio {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_reg_audio>;
+                compatible = "regulator-fixed";
+                regulator-name = "3v3_aud";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                vin-supply = <&reg_3v3>;
+        };
+
+        reg_hdmi: regulator-hdmi {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_reg_hdmi>;
+                compatible = "regulator-fixed";
+                regulator-name = "hdmi-supply";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                vin-supply = <&reg_3v3>;
+        };
+
+        reg_uart3: regulator-uart3 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_reg_uart3>;
+                compatible = "regulator-fixed";
+                regulator-name = "uart3-supply";
+                gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                regulator-always-on;
+                vin-supply = <&reg_3v3>;
+        };
+
+        reg_1v8: regulator-1v8 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_reg_1v8>;
+                compatible = "regulator-fixed";
+                regulator-name = "1v8-supply";
+                gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                regulator-always-on;
+                vin-supply = <&reg_3v3>;
+        };
+
+        reg_pcie: regulator-pcie {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_reg_pcie>;
+                regulator-name = "mpcie_3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        reg_mipi: regulator-mipi {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_reg_mipi>;
+                regulator-name = "mipi_pwr_en";
+                regulator-min-microvolt = <2800000>;
+                regulator-max-microvolt = <2800000>;
+                gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        sound {
+                compatible = "fsl,imx-audio-wm8962";
+                model = "wm8962-audio";
+                ssi-controller = <&ssi2>;
+                audio-codec = <&wm8962>;
+                audio-routing =
+                        "Headphone Jack", "HPOUTL",
+                        "Headphone Jack", "HPOUTR",
+                        "Ext Spk", "SPKOUTL",
+                        "Ext Spk", "SPKOUTR",
+                        "AMIC", "MICBIAS",
+                        "IN3R", "AMIC";
+                mux-int-port = <2>;
+                mux-ext-port = <4>;
+        };
+};
+
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>;
+        status = "okay";
+};
+
+&ecspi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1>;
+        status = "disabled";
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rgmii";
+        phy-reset-duration = <10>;
+        phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
+        phy-supply = <&reg_enet>;
+        interrupt-parent = <&gpio1>;
+        interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+        status = "okay";
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        clock-frequency = <400000>;
+        status = "okay";
+
+        wm8962: audio-codec@1a {
+                compatible = "wlf,wm8962";
+                reg = <0x1a>;
+                clocks = <&clks IMX6QDL_CLK_CKO>;
+                clock-names = "xclk";
+                DCVDD-supply = <&reg_audio>;
+                DBVDD-supply = <&reg_audio>;
+                AVDD-supply = <&reg_audio>;
+                CPVDD-supply = <&reg_audio>;
+                MICVDD-supply = <&reg_audio>;
+                PLLVDD-supply = <&reg_audio>;
+                SPKVDD1-supply = <&reg_audio>;
+                SPKVDD2-supply = <&reg_audio>;
+                gpio-cfg = <
+                        0x0000 /* 0:Default */
+                        0x0000 /* 1:Default */
+                        0x0013 /* 2:FN_DMICCLK */
+                        0x0000 /* 3:Default */
+                        0x8014 /* 4:FN_DMICCDAT */
+                        0x0000 /* 5:Default */
+                >;
+        };
+};
+
+&i2c3 {
+        ov5640: camera@10 {
+                compatible = "ovti,ov5640";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_ov5640>;
+                reg = <0x10>;
+                clocks = <&clks IMX6QDL_CLK_CKO>;
+                clock-names = "xclk";
+                DOVDD-supply = <&reg_mipi>;
+                AVDD-supply = <&reg_mipi>;
+                DVDD-supply = <&reg_mipi>;
+                reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
+                powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
+
+                port {
+                        ov5640_to_mipi_csi2: endpoint {
+                                remote-endpoint = <&mipi_csi2_in>;
+                                clock-lanes = <0>;
+                                data-lanes = <1 2>;
+                        };
+                };
+        };
+
+        pcf8575: gpio@20 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pcf8574>;
+                compatible = "nxp,pcf8575";
+                reg = <0x20>;
+                interrupt-parent = <&gpio6>;
+                interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                lines-initial-states = <0x0710>;
+                wakeup-source;
+        };
+};
+
+&ipu1_csi1_from_mipi_vc1 {
+        clock-lanes = <0>;
+        data-lanes = <1 2>;
+};
+
+&mipi_csi {
+        status = "okay";
+
+        port@0 {
+                reg = <0>;
+
+                mipi_csi2_in: endpoint {
+                        remote-endpoint = <&ov5640_to_mipi_csi2>;
+                        clock-lanes = <0>;
+                        data-lanes = <1 2>;
+                };
+        };
+};
+
+&pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pcie>;
+        reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
+        vpcie-supply = <&reg_pcie>;
+        status = "okay";
+};
+
+&pwm3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm3>;
+};
+
+&ssi2 {
+        status = "okay";
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3>;
+        status = "okay";
+};
+
+&usbh1 {
+        vbus-supply = <&reg_usb_h1_vbus>;
+        status = "okay";
+};
+
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        dr_mode = "otg";
+        status = "okay";
+};
+
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2>;
+        pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+        pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+        vmmc-supply = <&reg_3v3>;
+        no-1-8-v;
+        keep-power-in-suspend;
+        cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+        status = "okay";
+};
+
+&iomuxc {
+        pinctrl_audmux: audmuxgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
+                        MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x110b0
+                        MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
+                        MX6QDL_PAD_DISP0_DAT23__AUD4_RXD  0x130b0
+                >;
+        };
+
+        pinctrl_ecspi1: ecspi1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK        0x100b1
+                        MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI        0x100b1
+                        MX6QDL_PAD_KEY_COL1__ECSPI1_MISO        0x100b1
+                        MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0         0x100b1
+                >;
+        };
+
+        pinctrl_enet: enetgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b8b0
+                        MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                        MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
+                        MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
+                        MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
+                        MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
+                        MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
+                        MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
+                        MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
+                        MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+                        MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
+                        MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x13030
+                        MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x13030
+                        MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
+                        MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
+                        MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x13030
+                        MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x1b0b0 /* ENET_INT */
+                        MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24       0x1b0b0 /* ETHR_nRST */
+                >;
+        };
+
+        pinctrl_i2c1: i2c1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D21__I2C1_SCL    0x4001b8b1
+                        MX6QDL_PAD_EIM_D28__I2C1_SDA    0x4001b8b1
+                >;
+        };
+
+        pinctrl_led0: led0grp {
+            fsl,pins = <
+                MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0
+            >;
+        };
+
+        pinctrl_ov5640: ov5640grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D26__GPIO3_IO26  0x1b0b1
+                        MX6QDL_PAD_EIM_D27__GPIO3_IO27  0x1b0b1
+                >;
+        };
+
+        pinctrl_pcf8574: pcf8575grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
+                >;
+        };
+
+        pinctrl_pcie: pciegrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
+                        MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+                >;
+        };
+
+        pinctrl_pwm3: pwm3grp {
+            fsl,pins = <
+                MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
+            >;
+        };
+
+        pinctrl_reg_1v8: reg1v8grp {
+            fsl,pins = <
+                MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x1b0b0
+            >;
+        };
+
+        pinctrl_reg_3v3: reg3v3grp {
+            fsl,pins = <
+                MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b0
+            >;
+        };
+
+        pinctrl_reg_audio: reg-audiogrp {
+                fsl,pins = <
+                        MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
+                >;
+        };
+
+        pinctrl_reg_enet: reg-enetgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D31__GPIO3_IO31  0x1b0b0
+                >;
+        };
+
+        pinctrl_reg_hdmi: reg-hdmigrp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D20__GPIO3_IO20  0x1b0b0
+                >;
+        };
+
+        pinctrl_reg_mipi: reg-mipigrp {
+                fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>;
+        };
+
+        pinctrl_reg_pcie: reg-pciegrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_2__GPIO1_IO02   0x1b0b0
+                        >;
+        };
+
+        pinctrl_reg_uart3: reguart3grp {
+            fsl,pins = <
+                MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x1b0b0
+            >;
+        };
+
+        pinctrl_reg_usb_h1_vbus: usbh1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b0b0
+                >;
+        };
+
+        pinctrl_reg_usb_otg: reg-usb-otggrp {
+                fsl,pins = <
+                        MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
+                >;
+        };
+
+        pinctrl_uart3: uart3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D23__UART3_CTS_B         0x1b0b1
+                        MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
+                        MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
+                        MX6QDL_PAD_EIM_EB3__UART3_RTS_B         0x1b0b1
+                >;
+        };
+
+        pinctrl_usbotg: usbotggrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_1__USB_OTG_ID   0xd17059
+                >;
+        };
+
+        pinctrl_usdhc2: usdhc2grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0 /* CD */
+                        MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17069
+                        MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10069
+                        MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17069
+                        MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17069
+                        MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17069
+                        MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17069
+                >;
+        };
+
+        pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0 /* CD */
+                        MX6QDL_PAD_SD2_CMD__SD2_CMD             0x170b9
+                        MX6QDL_PAD_SD2_CLK__SD2_CLK             0x100b9
+                        MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x170b9
+                        MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x170b9
+                        MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x170b9
+                        MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x170b9
+                >;
+        };
+
+        pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0 /* CD */
+                        MX6QDL_PAD_SD2_CMD__SD2_CMD             0x170f9
+                        MX6QDL_PAD_SD2_CLK__SD2_CLK             0x100f9
+                        MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x170f9
+                        MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x170f9
+                        MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x170f9
+                        MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x170f9
+                >;
+        };
+
+};
diff --git a/arch/arm/boot/dts/imx6-logicpd-som.dtsi b/arch/arm/boot/dts/imx6-logicpd-som.dtsi
new file mode 100644
index 000000000000..7ceae3573248
--- /dev/null
+++ b/arch/arm/boot/dts/imx6-logicpd-som.dtsi
@@ -0,0 +1,365 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2019 Logic PD, Inc.
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+        chosen {
+                stdout-path = &uart1;
+        };
+
+        memory@10000000 {
+                device_type = "memory";
+                reg = <0x10000000 0x80000000>;
+        };
+
+        reg_wl18xx_vmmc: regulator-wl18xx {
+                compatible = "regulator-fixed";
+                regulator-name = "vwl1837";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio7 0 GPIO_ACTIVE_HIGH>;
+                startup-delay-us = <70000>;
+                enable-active-high;
+        };
+};
+
+&clks {
+        assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+                          <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+        assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+                                 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand>;
+        nand-on-flash-bbt;
+        status = "okay";
+};
+
+&i2c3 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        status = "okay";
+
+        pfuze100: pmic@8 {
+                compatible = "fsl,pfuze100";
+                reg = <0x08>;
+
+                regulators {
+                        sw1a_reg: sw1ab {
+                                regulator-min-microvolt = <725000>;
+                                regulator-max-microvolt = <1450000>;
+                                regulator-name = "vddcore";
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+
+                        sw1c_reg: sw1c {
+                                regulator-min-microvolt = <725000>;
+                                regulator-max-microvolt = <1450000>;
+                                regulator-name = "vddsoc";
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+
+                        sw2_reg: sw2 {
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "gen_3v3";
+                                regulator-boot-on;
+                        };
+
+                        sw3a_reg: sw3a {
+                                regulator-min-microvolt = <1350000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-name = "sw3a_vddr";
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        sw3b_reg: sw3b {
+                                regulator-min-microvolt = <1350000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-name = "sw3b_vddr";
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        sw4_reg: sw4 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "gen_rgmii";
+                        };
+
+                        swbst_reg: swbst {
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5150000>;
+                                regulator-name = "gen_5v0";
+                        };
+
+                        snvs_reg: vsnvs {
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-name = "gen_vsns";
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        vref_reg: vrefddr {
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        vgen1_reg: vgen1 {
+                                regulator-min-microvolt = <1500000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-name = "gen_1v5";
+                        };
+
+                        vgen2_reg: vgen2 {
+                                regulator-name = "vgen2";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+
+                        vgen3_reg: vgen3 {
+                                regulator-name = "gen_vadj_0";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+
+                        vgen4_reg: vgen4 {
+                                regulator-name = "gen_1v8";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        vgen5_reg: vgen5 {
+                                regulator-name = "gen_vadj_1";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+
+                        vgen6_reg: vgen6 {
+                                regulator-name = "gen_2v5";
+                                regulator-min-microvolt = <2500000>;
+                                regulator-max-microvolt = <2500000>;
+                                regulator-always-on;
+                        };
+
+                        coin_reg: coin {
+                                regulator-min-microvolt = <2500000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+
+        temperature-sensor@49 {
+                compatible = "ti,tmp102";
+                reg = <0x49>;
+                interrupt-parent = <&gpio6>;
+                interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+                #thermal-sensor-cells = <1>;
+        };
+
+        temperature-sensor@4a {
+                compatible = "ti,tmp102";
+                reg = <0x4a>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_tempsense>;
+                interrupt-parent = <&gpio6>;
+                interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+                #thermal-sensor-cells = <1>;
+        };
+
+        eeprom@51 {
+                compatible = "atmel,24c64";
+                pagesize = <32>;
+                read-only;      /* Manufacturing EEPROM programmed at factory */
+                reg = <0x51>;
+        };
+
+        eeprom@52 {
+                compatible = "atmel,24c64";
+                pagesize = <32>;
+                reg = <0x52>;
+        };
+};
+
+/* Reroute power feeding the CPU to come from the external PMIC */
+&reg_arm
+{
+        vin-supply = <&sw1a_reg>;
+};
+
+&reg_soc
+{
+        vin-supply = <&sw1c_reg>;
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+
+        pinctrl_gpmi_nand: gpmi-nandgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_NANDF_CLE__NAND_CLE          0x0b0b1
+                        MX6QDL_PAD_NANDF_ALE__NAND_ALE          0x0b0b1
+                        MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0x0b0b1
+                        MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0x0b000
+                        MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0x0b0b1
+                        MX6QDL_PAD_SD4_CMD__NAND_RE_B           0x0b0b1
+                        MX6QDL_PAD_SD4_CLK__NAND_WE_B           0x0b0b1
+                        MX6QDL_PAD_NANDF_D0__NAND_DATA00        0x0b0b1
+                        MX6QDL_PAD_NANDF_D1__NAND_DATA01        0x0b0b1
+                        MX6QDL_PAD_NANDF_D2__NAND_DATA02        0x0b0b1
+                        MX6QDL_PAD_NANDF_D3__NAND_DATA03        0x0b0b1
+                        MX6QDL_PAD_NANDF_D4__NAND_DATA04        0x0b0b1
+                        MX6QDL_PAD_NANDF_D5__NAND_DATA05        0x0b0b1
+                        MX6QDL_PAD_NANDF_D6__NAND_DATA06        0x0b0b1
+                        MX6QDL_PAD_NANDF_D7__NAND_DATA07        0x0b0b1
+                >;
+        };
+
+        pinctrl_hog: hoggrp {
+                fsl,pins = <    /* Enable ARM Debugger */
+                        MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL     0x1b0b0
+                        MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO      0x1b0b0
+                        MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00      0x1b0b0
+                        MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK  0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01       0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02       0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03       0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04       0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05       0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06       0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07      0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08      0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09      0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10      0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11      0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12      0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13      0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14      0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15      0x1b0b0
+                        MX6QDL_PAD_GPIO_0__CCM_CLKO1        0x130b0
+                >;
+        };
+
+        pinctrl_i2c3: i2c3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D17__I2C3_SCL            0x4001b8b1
+                        MX6QDL_PAD_EIM_D18__I2C3_SDA            0x4001b8b1
+                >;
+        };
+
+        pinctrl_tempsense: tempsensegrp {
+                fsl,pins = <
+                        MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
+                >;
+        };
+
+        pinctrl_uart1: uart1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
+                        MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
+                >;
+        };
+
+        pinctrl_uart2: uart2grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD3_RST__GPIO7_IO08          0x13059 /* BT_EN */
+                        MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
+                        MX6QDL_PAD_SD4_DAT5__UART2_RTS_B        0x1b0b1
+                        MX6QDL_PAD_SD4_DAT6__UART2_CTS_B        0x1b0b1
+                        MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
+                >;
+        };
+
+        pinctrl_usdhc1: usdhc1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD1_CMD__SD1_CMD     0x170B9
+                        MX6QDL_PAD_SD1_CLK__SD1_CLK     0x100B9
+                        MX6QDL_PAD_SD1_DAT0__SD1_DATA0  0x170B9
+                        MX6QDL_PAD_SD1_DAT1__SD1_DATA1  0x170B9
+                        MX6QDL_PAD_SD1_DAT2__SD1_DATA2  0x170B9
+                        MX6QDL_PAD_SD1_DAT3__SD1_DATA3  0x170B9
+                >;
+        };
+
+        pinctrl_usdhc3: usdhc3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17049
+                        MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10049
+                        MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17049
+                        MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17049
+                        MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17049
+                        MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17049
+                        MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x130b0 /* WL_IRQ */
+                        MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* WLAN_EN */
+                >;
+        };
+};
+
+&snvs_poweroff {
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        uart-has-rtscts;
+        status = "okay";
+
+        bluetooth {
+                compatible = "ti,wl1837-st";
+                enable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+        };
+};
+
+&usdhc1 {
+        pinctrl-names = "default", "state_100mhz", "state_200mhz";
+        pinctrl-0 = <&pinctrl_usdhc1>;
+        non-removable;
+        keep-power-in-suspend;
+        wakeup-source;
+        vmmc-supply = <&sw2_reg>;
+        status = "okay";
+};
+
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        non-removable;
+        cap-power-off-card;
+        keep-power-in-suspend;
+        wakeup-source;
+        vmmc-supply = <&reg_wl18xx_vmmc>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        status = "okay";
+
+        wlcore: wlcore@2 {
+                  compatible = "ti,wl1837";
+                  reg = <2>;
+                  interrupt-parent = <&gpio7>;
+                  interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+                  tcxo-clock-frequency = <26000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
index d5f7a1703aae..9a5d6c94cca4 100644
--- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
@@ -228,10 +228,11 @@
 &weim {
         status = "okay";
 
-        /* weim memory map: 32MB on CS0, 32MB on CS1, 32MB on CS2 */
+        /* weim memory map: 32MB on CS0, CS1, CS2 and CS3 */
         ranges = <0 0 0x08000000 0x02000000
                   1 0 0x0a000000 0x02000000
-                  2 0 0x0c000000 0x02000000>;
+                  2 0 0x0c000000 0x02000000
+                  3 0 0x0e000000 0x02000000>;
 
         /* SRAM on Colibri nEXT_CS0 */
         sram@0,0 {
diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi
new file mode 100644
index 000000000000..b715ab0fa1ff
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi
@@ -0,0 +1,595 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2015-2018 Y Soft Corporation, a.s.
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>;
+                brightness-levels = <0 32 64 128 255>;
+                default-brightness-level = <32>;
+                num-interpolated-steps = <8>;
+                power-supply = <&sw2_reg>;
+                status = "disabled";
+        };
+
+        lcd_display: display {
+                compatible = "fsl,imx-parallel-display";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                interface-pix-fmt = "rgb24";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_ipu1>;
+                status = "disabled";
+
+                port@0 {
+                        reg = <0>;
+
+                        lcd_display_in: endpoint {
+                                remote-endpoint = <&ipu1_di0_disp0>;
+                        };
+                };
+
+                port@1 {
+                        reg = <1>;
+
+                        lcd_display_out: endpoint {
+                                remote-endpoint = <&lcd_panel_in>;
+                        };
+                };
+        };
+
+        panel: panel {
+                compatible = "dataimage,scf0700c48ggu18";
+                power-supply = <&sw2_reg>;
+                status = "disabled";
+
+                port {
+                        lcd_panel_in: endpoint {
+                                remote-endpoint = <&lcd_display_out>;
+                        };
+                };
+        };
+
+        reg_pcie: regulator-pcie {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pcie_reg>;
+                regulator-name = "MPCIE_3V3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                status = "disabled";
+        };
+
+        reg_usb_h1_vbus: regulator-usb-h1-vbus {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_usbh1_vbus>;
+                regulator-name = "usb_h1_vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                status = "disabled";
+        };
+
+        reg_usb_otg_vbus: regulator-usb-otg-vbus {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_usbotg_vbus>;
+                regulator-name = "usb_otg_vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                status = "okay";
+        };
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rgmii-id";
+        phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+        phy-reset-duration = <20>;
+        phy-supply = <&sw2_reg>;
+        phy-handle = <&ethphy0>;
+        status = "okay";
+
+        mdio {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                phy_port2: phy@1 {
+                        reg = <1>;
+                };
+
+                phy_port3: phy@2 {
+                        reg = <2>;
+                };
+
+                switch@0 {
+                        compatible = "qca,qca8334";
+                        reg = <0>;
+
+                        switch_ports: ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                ethphy0: port@0 {
+                                        reg = <0>;
+                                        label = "cpu";
+                                        phy-mode = "rgmii";
+                                        ethernet = <&fec>;
+
+                                        fixed-link {
+                                                speed = <1000>;
+                                                full-duplex;
+                                        };
+                                };
+
+                                port@2 {
+                                        reg = <2>;
+                                        label = "eth2";
+                                        phy-handle = <&phy_port2>;
+                                };
+
+                                port@3 {
+                                        reg = <3>;
+                                        label = "eth1";
+                                        phy-handle = <&phy_port3>;
+                                };
+                        };
+                };
+        };
+};
+
+&hdmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hdmi_cec>;
+        ddc-i2c-bus = <&i2c2>;
+        status = "disabled";
+};
+
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+
+        pmic@8 {
+                compatible = "fsl,pfuze200";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pmic>;
+                reg = <0x8>;
+
+                regulators {
+                        sw1a_reg: sw1ab {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+
+                        sw2_reg: sw2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        sw3a_reg: sw3a {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        sw3b_reg: sw3b {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        swbst_reg: swbst {
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5150000>;
+                        };
+
+                        vgen1_reg: vgen1 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+
+                        vgen2_reg: vgen2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+
+                        vgen3_reg: vgen3 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+
+                        vgen4_reg: vgen4 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+
+                        vgen5_reg: vgen5 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+
+                        vgen6_reg: vgen6 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+
+                        vref_reg: vrefddr {
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        vsnvs_reg: vsnvs {
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                };
+        };
+
+        leds: led-controller@30 {
+                compatible = "ti,lp5562";
+                reg = <0x30>;
+                clock-mode = /bits/ 8 <1>;
+                status = "disabled";
+
+                chan0 {
+                        chan-name = "R";
+                        led-cur = /bits/ 8 <0x20>;
+                        max-cur = /bits/ 8 <0x60>;
+                };
+
+                chan1 {
+                        chan-name = "G";
+                        led-cur = /bits/ 8 <0x20>;
+                        max-cur = /bits/ 8 <0x60>;
+                };
+
+                chan2 {
+                        chan-name = "B";
+                        led-cur = /bits/ 8 <0x20>;
+                        max-cur = /bits/ 8 <0x60>;
+                };
+
+                chan3 {
+                        chan-name = "W";
+                        led-cur = /bits/ 8 <0x0>;
+                        max-cur = /bits/ 8 <0x0>;
+                };
+        };
+
+        eeprom@57 {
+                compatible = "atmel,24c128";
+                reg = <0x57>;
+                pagesize = <64>;
+                status = "okay";
+        };
+
+        touchscreen: touchscreen@5c {
+                compatible = "pixcir,pixcir_tangoc";
+                reg = <0x5c>;
+                pinctrl-0 = <&pinctrl_touch>;
+                interrupt-parent = <&gpio4>;
+                interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+                attb-gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>;
+                reset-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+                touchscreen-size-x = <800>;
+                touchscreen-size-y = <480>;
+                status = "disabled";
+        };
+};
+
+&i2c3 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        status = "disabled";
+
+        oled: oled@3d {
+                compatible = "solomon,ssd1305fb-i2c";
+                reg = <0x3d>;
+                solomon,height = <64>;
+                solomon,width = <128>;
+                solomon,page-offset = <0>;
+                solomon,prechargep2 = <15>;
+                reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>;
+                vbat-supply = <&sw2_reg>;
+                status = "disabled";
+        };
+
+        gpio_oled: gpio@41 {
+                compatible = "nxp,pca9536";
+                gpio-controller;
+                #gpio-cells = <2>;
+                reg = <0x41>;
+                vcc-supply = <&sw2_reg>;
+                status = "disabled";
+        };
+};
+
+&iomuxc {
+        pinctrl_enet: enetgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b020
+                        MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b020
+                        MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b020
+                        MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b020
+                        MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b020
+                        MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b020
+                        MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b020
+                        MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b020
+                        MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b020
+                        MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b020
+                        MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b020
+                        MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b020
+                        MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b020
+                        MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b020
+                        MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b010
+                        MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x1b010
+                        MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x1b098
+                >;
+        };
+
+        pinctrl_hdmi_cec: hdmicecgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE    0x1b898
+                >;
+        };
+
+        pinctrl_i2c2: i2c2grp {
+                fsl,pins = <
+                        MX6QDL_PAD_KEY_COL3__I2C2_SCL   0x4001b899
+                        MX6QDL_PAD_KEY_ROW3__I2C2_SDA   0x4001b899
+                >;
+        };
+
+        pinctrl_i2c3: i2c3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_3__I2C3_SCL     0x4001b899
+                        MX6QDL_PAD_GPIO_6__I2C3_SDA     0x4001b899
+                >;
+        };
+
+        pinctrl_ipu1: ipu1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK      0x10
+                        MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02             0x10
+                        MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03             0x10
+                        MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00        0x10
+                        MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01        0x10
+                        MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02        0x10
+                        MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03        0x10
+                        MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04        0x10
+                        MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05        0x10
+                        MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06        0x10
+                        MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07        0x10
+                        MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08        0x10
+                        MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09        0x10
+                        MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10       0x10
+                        MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11       0x10
+                        MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12       0x10
+                        MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13       0x10
+                        MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14       0x10
+                        MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15       0x10
+                        MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16       0x10
+                        MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17       0x10
+                        MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18       0x10
+                        MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19       0x10
+                        MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20       0x10
+                        MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21       0x10
+                        MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22       0x10
+                        MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23       0x10
+                >;
+        };
+
+        pinctrl_pcie: pciegrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b098
+                        MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b098
+                        MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20     0x1b098
+                >;
+        };
+
+        pinctrl_pcie_reg: pciereggrp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x1b098
+                >;
+        };
+
+        pinctrl_pmic: pmicgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_18__GPIO7_IO13  0x1b098
+                >;
+        };
+
+        pinctrl_pwm1: pwm1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_9__PWM1_OUT     0x8
+                >;
+        };
+
+        pinctrl_touch: touchgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_19__GPIO4_IO05  0x1b098
+                        MX6QDL_PAD_GPIO_2__GPIO1_IO02   0x1b098
+                >;
+        };
+
+        pinctrl_uart1: uart1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0a8
+                        MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0a8
+                >;
+        };
+
+        pinctrl_usbh1: usbh1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D30__USB_H1_OC   0x1b098
+                >;
+        };
+
+        pinctrl_usbh1_vbus: usbh1-vbus {
+                fsl,pins = <
+                        MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x98
+                >;
+        };
+
+        pinctrl_usbotg: usbotggrp {
+                fsl,pins = <
+                        MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x1b098
+                        MX6QDL_PAD_EIM_D21__USB_OTG_OC          0x1b098
+                >;
+        };
+
+        pinctrl_usbotg_vbus: usbotg-vbus {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x98
+                >;
+        };
+
+        pinctrl_usdhc3: usdhc3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_A16__GPIO2_IO22  0x1b018
+                        MX6QDL_PAD_SD3_RST__GPIO7_IO08  0x1b018
+                        MX6QDL_PAD_SD3_CMD__SD3_CMD     0x17059
+                        MX6QDL_PAD_SD3_CLK__SD3_CLK     0x10059
+                        MX6QDL_PAD_SD3_DAT0__SD3_DATA0  0x17059
+                        MX6QDL_PAD_SD3_DAT1__SD3_DATA1  0x17059
+                        MX6QDL_PAD_SD3_DAT2__SD3_DATA2  0x17059
+                        MX6QDL_PAD_SD3_DAT3__SD3_DATA3  0x17059
+                >;
+        };
+
+        pinctrl_usdhc4: usdhc4grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD4_CMD__SD4_CMD     0x1f069
+                        MX6QDL_PAD_SD4_CLK__SD4_CLK     0x10069
+                        MX6QDL_PAD_SD4_DAT0__SD4_DATA0  0x17069
+                        MX6QDL_PAD_SD4_DAT1__SD4_DATA1  0x17069
+                        MX6QDL_PAD_SD4_DAT2__SD4_DATA2  0x17069
+                        MX6QDL_PAD_SD4_DAT3__SD4_DATA3  0x17069
+                        MX6QDL_PAD_SD4_DAT4__SD4_DATA4  0x17069
+                        MX6QDL_PAD_SD4_DAT5__SD4_DATA5  0x17069
+                        MX6QDL_PAD_SD4_DAT6__SD4_DATA6  0x17069
+                        MX6QDL_PAD_SD4_DAT7__SD4_DATA7  0x17069
+                >;
+        };
+
+        pinctrl_wdog: wdoggrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_1__WDOG2_B      0x1b0b0
+                >;
+        };
+};
+
+&ipu1_di0_disp0 {
+        remote-endpoint = <&lcd_display_in>;
+};
+
+&pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pcie>;
+        reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
+        vpcie-supply = <&reg_pcie>;
+        status = "disabled";
+};
+
+&pwm1 {
+        #pwm-cells = <3>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm1>;
+        status = "disabled";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+
+&usbh1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbh1>;
+        vbus-supply = <&reg_usb_h1_vbus>;
+        status = "disabled";
+};
+
+&usbotg {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        vbus-supply = <&reg_usb_otg_vbus>;
+        srp-disable;
+        hnp-disable;
+        adp-disable;
+        status = "okay";
+};
+
+&usbphy1 {
+        fsl,tx-d-cal = <106>;
+        status = "okay";
+};
+
+&usbphy2 {
+        fsl,tx-d-cal = <109>;
+        status = "disabled";
+};
+
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        bus-width = <4>;
+        cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
+        wp-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+        no-1-8-v;
+        keep-power-in-suspend;
+        wakeup-source;
+        vmmc-supply = <&sw2_reg>;
+        status = "disabled";
+};
+
+&usdhc4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4>;
+        bus-width = <8>;
+        non-removable;
+        no-1-8-v;
+        keep-power-in-suspend;
+        vmmc-supply = <&sw2_reg>;
+        status = "okay";
+};
+
+&wdog1 {
+        status = "disabled";
+};
+
+&wdog2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_wdog>;
+        fsl,ext-reset-output;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl-yapp4-draco.dts b/arch/arm/boot/dts/imx6dl-yapp4-draco.dts
new file mode 100644
index 000000000000..a38c407fd837
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-yapp4-draco.dts
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2015-2018 Y Soft Corporation, a.s.
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6dl-yapp4-common.dtsi"
+
+/ {
+        model = "Y Soft IOTA Draco i.MX6Solo board";
+        compatible = "ysoft,imx6dl-yapp4-draco", "fsl,imx6dl";
+
+        memory@10000000 {
+                device_type = "memory";
+                reg = <0x10000000 0x20000000>;
+        };
+};
+
+&backlight {
+        status = "okay";
+};
+
+&lcd_display {
+        status = "okay";
+};
+
+&leds {
+        status = "okay";
+};
+
+&panel {
+        status = "okay";
+};
+
+&pwm1 {
+        status = "okay";
+};
+
+&reg_usb_h1_vbus {
+        status = "okay";
+};
+
+&touchscreen {
+        status = "okay";
+};
+
+&usbh1 {
+        status = "okay";
+};
+
+&usbphy2 {
+        status = "okay";
+};
+
+&usdhc3 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts b/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts
new file mode 100644
index 000000000000..f97927064750
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2015-2018 Y Soft Corporation, a.s.
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6dl-yapp4-common.dtsi"
+
+/ {
+        model = "Y Soft IOTA Hydra i.MX6DualLite board";
+        compatible = "ysoft,imx6dl-yapp4-hydra", "fsl,imx6dl";
+
+        memory@10000000 {
+                device_type = "memory";
+                reg = <0x10000000 0x80000000>;
+        };
+};
+
+&gpio_oled {
+        status = "okay";
+};
+
+&hdmi {
+        status = "okay";
+};
+
+&i2c3 {
+        status = "okay";
+};
+
+&leds {
+        status = "okay";
+};
+
+&oled {
+        status = "okay";
+};
+
+&pcie {
+        status = "okay";
+};
+
+&reg_pcie {
+        status = "okay";
+};
+
+&usdhc3 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts b/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts
new file mode 100644
index 000000000000..0d594e4bd559
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2015-2018 Y Soft Corporation, a.s.
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6dl-yapp4-common.dtsi"
+
+/ {
+        model = "Y Soft IOTA Ursa i.MX6Solo board";
+        compatible = "ysoft,imx6dl-yapp4-ursa", "fsl,imx6dl";
+
+        memory@10000000 {
+                device_type = "memory";
+                reg = <0x10000000 0x20000000>;
+        };
+};
+
+&backlight {
+        status = "okay";
+};
+
+&lcd_display {
+        status = "okay";
+};
+
+&panel {
+        status = "okay";
+};
+
+&pwm1 {
+        status = "okay";
+};
+
+&reg_usb_h1_vbus {
+        status = "okay";
+};
+
+&switch_ports {
+        /delete-node/ port@2;
+};
+
+&touchscreen {
+        status = "okay";
+};
+
+&usbh1 {
+        status = "okay";
+};
+
+&usbphy2 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-logicpd.dts b/arch/arm/boot/dts/imx6q-logicpd.dts
new file mode 100644
index 000000000000..45eb0b7f75f8
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-logicpd.dts
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2019 Logic PD, Inc.
+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6-logicpd-som.dtsi"
+#include "imx6-logicpd-baseboard.dtsi"
+
+/ {
+        model = "Logic PD i.MX6QD SOM-M3";
+        compatible = "fsl,imx6q";
+
+        backlight: backlight-lvds {
+                compatible = "pwm-backlight";
+                pwms = <&pwm3 0 20000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+                power-supply = <&reg_lcd>;
+        };
+
+        panel-lvds0 {
+                compatible = "okaya,rs800480t-7x0gp";
+
+                port {
+                        panel_in_lvds0: endpoint {
+                                remote-endpoint = <&lvds0_out>;
+                        };
+                };
+        };
+
+        reg_lcd: regulator-lcd {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_lcd_reg>;
+                compatible = "regulator-fixed";
+                regulator-name = "lcd_panel_pwr";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                regulator-always-on;
+                vin-supply = <&reg_3v3>;
+                startup-delay-us = <500000>;
+        };
+
+        reg_lcd_reset: regulator-lcd-reset {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_lcd_reset>;
+                compatible = "regulator-fixed";
+                regulator-name = "nLCD_RESET";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                regulator-always-on;
+                vin-supply = <&reg_lcd>;
+        };
+};
+
+&clks {
+        assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+                          <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+                          <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
+                          <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
+        assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+                                 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+                                 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+                                 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
+};
+
+&hdmi {
+        ddc-i2c-bus = <&i2c3>;
+        status = "okay";
+};
+
+&ldb {
+        status = "okay";
+
+        lvds-channel@0 {
+                fsl,data-mapping = "spwg";
+                fsl,data-width = <24>;
+                status = "okay";
+
+                port@4 {
+                        reg = <4>;
+                        lvds0_out: endpoint {
+                                remote-endpoint = <&panel_in_lvds0>;
+                        };
+                };
+        };
+
+};
+
+&pwm3 {
+        status = "okay";
+};
+
+&reg_hdmi {
+        regulator-always-on;    /* Without this, the level shifter on HDMI doesn't turn on */
+};
+
+&iomuxc {
+        pinctrl_lcd_reg: lcdreg {
+                fsl,pins = <
+                        MX6QDL_PAD_DI0_PIN15__GPIO4_IO17        0x100b0 /* R_LCD_PANEL_PWR */
+                >;
+        };
+
+        pinctrl_lcd_reset: lcdreset {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_A25__GPIO5_IO02  0x100b0 /* LCD_nRESET */
+                >;
+        };
+
+        pinctrl_touchscreen: touchscreengrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_6__GPIO1_IO06   0x1b0b0 /* TOUCH_nPINTDAV */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6q-pistachio.dts b/arch/arm/boot/dts/imx6q-pistachio.dts
index 5edf858c8b86..a31b17eaf51c 100644
--- a/arch/arm/boot/dts/imx6q-pistachio.dts
+++ b/arch/arm/boot/dts/imx6q-pistachio.dts
@@ -103,7 +103,7 @@
                 power {
                         label = "Power Button";
                         gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
-                        gpio-key,wakeup;
+                        wakeup-source;
                         linux,code = <KEY_POWER>;
                 };
         };
diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts
index 279b15e9ae2e..2ce8399a10ba 100644
--- a/arch/arm/boot/dts/imx6q-tbs2910.dts
+++ b/arch/arm/boot/dts/imx6q-tbs2910.dts
@@ -1,49 +1,6 @@
-/*
- * Copyright 2014 Soeren Moch <smoch@web.de>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of
- *     the License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- *     You should have received a copy of the GNU General Public
- *     License along with this file; if not, write to the Free
- *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- *     MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2014 Soeren Moch <smoch@web.de>
 
 /dts-v1/;
 
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index 8380f1b26826..7c4ad541c3f5 100644
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -332,11 +332,17 @@
                 id = <0>;
                 blocks = <0x5>;
                 irq-trigger = <0x1>;
+                /* 3.25 MHz ADC clock speed */
+                st,adc-freq = <1>;
+                /* 12-bit ADC */
+                st,mod-12b = <1>;
+                /* internal ADC reference */
+                st,ref-sel = <0>;
+                /* ADC converstion time: 80 clocks */
+                st,sample-time = <4>;
 
                 stmpe_touchscreen {
                         compatible = "st,stmpe-ts";
-                        /* 3.25 MHz ADC clock speed */
-                        st,adc-freq = <1>;
                         /* 8 sample average control */
                         st,ave-ctrl = <3>;
                         /* 7 length fractional part in z */
@@ -346,17 +352,17 @@
                          * current limit value
                          */
                         st,i-drive = <1>;
-                        /* 12-bit ADC */
-                        st,mod-12b = <1>;
-                        /* internal ADC reference */
-                        st,ref-sel = <0>;
-                        /* ADC converstion time: 80 clocks */
-                        st,sample-time = <4>;
                         /* 1 ms panel driver settling time */
                         st,settling = <3>;
                         /* 5 ms touch detect interrupt delay */
                         st,touch-det-delay = <5>;
                 };
+
+                stmpe_adc {
+                        compatible = "st,stmpe-adc";
+                        /* forbid to use ADC channels 3-0 (touch) */
+                        st,norequest-mask = <0x0F>;
+                };
         };
 };
 
@@ -369,8 +375,8 @@
         pinctrl-names = "default", "recovery";
         pinctrl-0 = <&pinctrl_i2c3>;
         pinctrl-1 = <&pinctrl_i2c3_recovery>;
-        scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
-        sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
+        scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+        sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
         status = "disabled";
 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
index 87e15e7cb32b..1beac22266ed 100644
--- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
@@ -262,11 +262,17 @@
                 id = <0>;
                 blocks = <0x5>;
                 irq-trigger = <0x1>;
+                /* 3.25 MHz ADC clock speed */
+                st,adc-freq = <1>;
+                /* 12-bit ADC */
+                st,mod-12b = <1>;
+                /* internal ADC reference */
+                st,ref-sel = <0>;
+                /* ADC converstion time: 80 clocks */
+                st,sample-time = <4>;
 
                 stmpe_touchscreen {
                         compatible = "st,stmpe-ts";
-                        /* 3.25 MHz ADC clock speed */
-                        st,adc-freq = <1>;
                         /* 8 sample average control */
                         st,ave-ctrl = <3>;
                         /* 7 length fractional part in z */
@@ -276,17 +282,17 @@
                          * current limit value
                          */
                         st,i-drive = <1>;
-                        /* 12-bit ADC */
-                        st,mod-12b = <1>;
-                        /* internal ADC reference */
-                        st,ref-sel = <0>;
-                        /* ADC converstion time: 80 clocks */
-                        st,sample-time = <4>;
                         /* 1 ms panel driver settling time */
                         st,settling = <3>;
                         /* 5 ms touch detect interrupt delay */
                         st,touch-det-delay = <5>;
                 };
+
+                stmpe_adc {
+                        compatible = "st,stmpe-adc";
+                        /* forbid to use ADC channels 3-0 (touch) */
+                        st,norequest-mask = <0x0F>;
+                };
         };
 };
 
@@ -298,8 +304,8 @@
         pinctrl-names = "default", "recovery";
         pinctrl-0 = <&pinctrl_i2c3>;
         pinctrl-1 = <&pinctrl_i2c3_recovery>;
-        scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
-        sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+        scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+        sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
         status = "disabled";
 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 1b50b01e9bac..433bf09a1954 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -89,10 +89,23 @@
 &fec {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet>;
+        phy-handle = <&ethphy>;
         phy-mode = "rgmii";
         phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
         phy-supply = <&vdd_eth_io_reg>;
         status = "disabled";
+
+        fec_mdio: mdio {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ethphy: ethernet-phy@0 {
+                        compatible = "ethernet-phy-ieee802.3-c22";
+                        reg = <0>;
+                        txc-skew-ps = <1680>;
+                        rxc-skew-ps = <1860>;
+                };
+        };
 };
 
 &gpmi {
@@ -117,6 +130,7 @@
                 reg = <0x58>;
                 interrupt-parent = <&gpio2>;
                 interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */
+                interrupt-controller;
 
                 regulators {
                         vddcore_reg: bcore1 {
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 8930aec6464c..a0705066ccba 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -64,7 +64,6 @@
                 regulator-max-microvolt = <3300000>;
                 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
                 enable-active-high;
-                regulator-always-on;
         };
 
         gpio-keys {
@@ -250,6 +249,8 @@
                 pinctrl-0 = <&pinctrl_i2c1_mma8451_int>;
                 interrupt-parent = <&gpio1>;
                 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+                vdd-supply = <&reg_sensors>;
+                vddio-supply = <&reg_sensors>;
         };
 
         ov5642: camera@3c {
@@ -440,6 +441,8 @@
                 pinctrl-0 = <&pinctrl_i2c3_mag3110_int>;
                 interrupt-parent = <&gpio3>;
                 interrupts = <16 IRQ_TYPE_EDGE_RISING>;
+                vdd-supply = <&reg_sensors>;
+                vddio-supply = <&reg_sensors>;
         };
 
         light-sensor@44 {
@@ -449,6 +452,7 @@
                 pinctrl-0 = <&pinctrl_i2c3_isl29023_int>;
                 interrupt-parent = <&gpio3>;
                 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+                vcc-supply = <&reg_sensors>;
         };
 };
 
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index e7524e73efb4..4b4813f176cd 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -338,7 +338,7 @@
                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
                                 reg = <0x02080000 0x4000>;
                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX6SL_CLK_PWM1>,
+                                clocks = <&clks IMX6SL_CLK_PERCLK>,
                                          <&clks IMX6SL_CLK_PWM1>;
                                 clock-names = "ipg", "per";
                         };
@@ -348,7 +348,7 @@
                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
                                 reg = <0x02084000 0x4000>;
                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX6SL_CLK_PWM2>,
+                                clocks = <&clks IMX6SL_CLK_PERCLK>,
                                          <&clks IMX6SL_CLK_PWM2>;
                                 clock-names = "ipg", "per";
                         };
@@ -358,7 +358,7 @@
                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
                                 reg = <0x02088000 0x4000>;
                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX6SL_CLK_PWM3>,
+                                clocks = <&clks IMX6SL_CLK_PERCLK>,
                                          <&clks IMX6SL_CLK_PWM3>;
                                 clock-names = "ipg", "per";
                         };
@@ -368,7 +368,7 @@
                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
                                 reg = <0x0208c000 0x4000>;
                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX6SL_CLK_PWM4>,
+                                clocks = <&clks IMX6SL_CLK_PERCLK>,
                                          <&clks IMX6SL_CLK_PWM4>;
                                 clock-names = "ipg", "per";
                         };
diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts
index d8163705363e..4a31a415f88e 100644
--- a/arch/arm/boot/dts/imx6sll-evk.dts
+++ b/arch/arm/boot/dts/imx6sll-evk.dts
@@ -309,7 +309,7 @@
         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
         cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
         keep-power-in-suspend;
-        enable-sdio-wakeup;
+        wakeup-source;
         vmmc-supply = <&reg_sd3_vmmc>;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 272ff6133ec1..5b16e65f7696 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -467,7 +467,7 @@
                         };
 
                         gpt: gpt@2098000 {
-                                compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
+                                compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
                                 reg = <0x02098000 0x4000>;
                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
@@ -785,6 +785,18 @@
                                                 clocks = <&clks IMX6SX_CLK_GPU>;
                                         };
 
+                                        pd_disp: power-domain@2 {
+                                                reg = <2>;
+                                                #power-domain-cells = <0>;
+                                                clocks = <&clks IMX6SX_CLK_PXP_AXI>,
+                                                         <&clks IMX6SX_CLK_DISPLAY_AXI>,
+                                                         <&clks IMX6SX_CLK_LCDIF1_PIX>,
+                                                         <&clks IMX6SX_CLK_LCDIF_APB>,
+                                                         <&clks IMX6SX_CLK_LCDIF2_PIX>,
+                                                         <&clks IMX6SX_CLK_CSI>,
+                                                         <&clks IMX6SX_CLK_VADC>;
+                                        };
+
                                         pd_pci: power-domain@3 {
                                                 reg = <3>;
                                                 #power-domain-cells = <0>;
@@ -1205,6 +1217,7 @@
                                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
                                         clocks = <&clks IMX6SX_CLK_PXP_AXI>;
                                         clock-names = "axi";
+                                        power-domains = <&pd_disp>;
                                         status = "disabled";
                                 };
 
@@ -1226,6 +1239,7 @@
                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
                                         clock-names = "pix", "axi", "disp_axi";
+                                        power-domains = <&pd_disp>;
                                         status = "disabled";
                                 };
 
@@ -1237,6 +1251,7 @@
                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
                                         clock-names = "pix", "axi", "disp_axi";
+                                        power-domains = <&pd_disp>;
                                         status = "disabled";
                                 };
 
@@ -1246,6 +1261,7 @@
                                         clocks = <&clks IMX6SX_CLK_VADC>,
                                                  <&clks IMX6SX_CLK_CSI>;
                                         clock-names = "vadc", "csi";
+                                        power-domains = <&pd_disp>;
                                         status = "disabled";
                                 };
                         };
@@ -1370,7 +1386,8 @@
                                  <&clks IMX6SX_CLK_PCIE_REF_125M>,
                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
                         clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
-                        power-domains = <&pd_pci>;
+                        power-domains = <&pd_disp>, <&pd_pci>;
+                        power-domain-names = "pcie", "pcie_phy";
                         status = "disabled";
                 };
         };
diff --git a/arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi b/arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi
new file mode 100644
index 000000000000..fc2997449b49
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "imx6ul.dtsi"
+
+/ {
+        model = "Phytec phyCORE i.MX6 UltraLite";
+        compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
+
+        chosen {
+                stdout-path = &uart1;
+        };
+
+        /*
+         * Set the minimum memory size here and
+         * let the bootloader set the real size.
+         */
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x8000000>;
+        };
+
+        gpio_leds_som: leds {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpioleds_som>;
+                compatible = "gpio-leds";
+
+                led_green {
+                        label = "phycore:green";
+                        gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
+
+&fec1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet1>;
+        phy-mode = "rmii";
+        phy-handle = <&ethphy0>;
+        status = "okay";
+
+        mdio: mdio {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ethphy0: ethernet-phy@1 {
+                        reg = <1>;
+                        interrupt-parent = <&gpio1>;
+                        interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+                        micrel,led-mode = <1>;
+                        clocks = <&clks IMX6UL_CLK_ENET_REF>;
+                        clock-names = "rmii-ref";
+                };
+        };
+};
+
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand>;
+        nand-on-flash-bbt;
+        status = "okay";
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 =<&pinctrl_i2c1>;
+        clock-frequency = <100000>;
+        status = "okay";
+
+        eeprom@52 {
+                compatible = "catalyst,24c32", "atmel,24c32";
+                reg = <0x52>;
+        };
+};
+
+&snvs_poweroff {
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+
+&iomuxc {
+        pinctrl_enet1: enet1grp {
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x1b0b0
+                        MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
+                        MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
+                        MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
+                        MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+                        MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+                        MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
+                        MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+                        MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+                        MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
+                        MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x17059
+                >;
+        };
+
+        pinctrl_gpioleds_som: gpioledssomgrp {
+                fsl,pins = <MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04  0x0b0b0>;
+        };
+
+        pinctrl_gpmi_nand: gpminandgrp {
+                fsl,pins = <
+                        MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
+                        MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
+                        MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
+                        MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
+                        MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
+                        MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
+                        MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
+                        MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
+                        MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
+                        MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
+                        MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
+                        MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
+                        MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
+                        MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
+                        MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
+                >;
+        };
+
+        pinctrl_i2c1: i2cgrp {
+                fsl,pins = <
+                        MX6UL_PAD_UART4_TX_DATA__I2C1_SCL       0x4001b8b0
+                        MX6UL_PAD_UART4_RX_DATA__I2C1_SDA       0x4001b8b0
+                >;
+        };
+
+        pinctrl_uart1: uart1grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x1b0b1
+                        MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x1b0b1
+                >;
+        };
+
+};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-peb-eval-01.dtsi b/arch/arm/boot/dts/imx6ul-phytec-peb-eval-01.dtsi
new file mode 100644
index 000000000000..e2f38f39a6ad
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-phytec-peb-eval-01.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 PHYTEC Messtechnik
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+#include <dt-bindings/input/input.h>
+
+/ {
+        gpio_keys: gpio-keys {
+                compatible = "gpio-key";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_keys>;
+                status = "disabled";
+
+                power {
+                        label = "Power Button";
+                        gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        wakeup-source;
+                };
+        };
+
+        user_leds: leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_user_leds>;
+                status = "disabled";
+
+                led_yellow {
+                        gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+
+                led_red {
+                        gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+        };
+};
+
+&iomuxc {
+        pinctrl_gpio_keys: gpio_keysgrp {
+                fsl,pins = <
+                        MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x79
+                >;
+        };
+
+        pinctrl_user_leds: user_ledsgrp {
+                fsl,pins = <
+                        MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x79
+                        MX6UL_PAD_GPIO1_IO01__GPIO1_IO01        0x79
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts b/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts
new file mode 100644
index 000000000000..b6a1407a9d44
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6ul-phytec-pcl063.dtsi"
+#include "imx6ul-phytec-phyboard-segin.dtsi"
+#include "imx6ul-phytec-peb-eval-01.dtsi"
+
+/ {
+        model = "Phytec phyBOARD-Segin i.MX6 UltraLite Full Featured";
+        compatible = "phytec,imx6ul-pbacd10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
+};
+
+&adc1 {
+        status = "okay";
+};
+
+&can1 {
+        status = "okay";
+};
+
+&tlv320 {
+        status = "okay";
+};
+
+&ecspi3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi3>;
+        cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+
+&fec2 {
+        status = "okay";
+};
+
+&i2c_rtc {
+        status = "okay";
+};
+
+&reg_can1_en {
+        status = "okay";
+};
+
+&reg_sound_1v8 {
+        status = "okay";
+};
+
+&reg_sound_3v3 {
+        status = "okay";
+};
+
+&sai2 {
+        status = "okay";
+};
+
+&sound {
+        status = "okay";
+};
+
+&uart5 {
+        status = "okay";
+};
+
+&usbotg1 {
+        status = "okay";
+};
+
+&usbotg2 {
+        status = "okay";
+};
+
+&usdhc1 {
+        status = "okay";
+};
+
+&iomuxc {
+        pinctrl_ecspi3: ecspi3grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO      0x10b0
+                        MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI      0x10b0
+                        MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK    0x10b0
+                        MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20     0x10b0
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi
new file mode 100644
index 000000000000..7bf439a77d2c
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi
@@ -0,0 +1,329 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+/ {
+        model = "Phytec phyBOARD-Segin i.MX6 UltraLite";
+        compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
+
+        aliases {
+                rtc0 = &i2c_rtc;
+                rtc1 = &snvs_rtc;
+        };
+
+        reg_sound_1v8: regulator-1v8 {
+                compatible = "regulator-fixed";
+                regulator-name = "i2s-audio-1v8";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                status = "disabled";
+        };
+
+        reg_sound_3v3: regulator-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "i2s-audio-3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                status = "disabled";
+        };
+
+        reg_can1_en: regulator-can1 {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&princtrl_flexcan1_en>;
+                regulator-name = "Can";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                status = "disabled";
+        };
+
+        reg_adc1_vref_3v3: regulator-vref-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "vref-3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        sound: sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007";
+                simple-audio-card,format = "i2s";
+                simple-audio-card,bitclock-master = <&dailink_master>;
+                simple-audio-card,frame-master = <&dailink_master>;
+                simple-audio-card,widgets =
+                        "Line", "Line In",
+                        "Line", "Line Out",
+                        "Speaker", "Speaker";
+                simple-audio-card,routing =
+                        "Line Out", "LLOUT",
+                        "Line Out", "RLOUT",
+                        "Speaker", "SPOP",
+                        "Speaker", "SPOM",
+                        "LINE1L", "Line In",
+                        "LINE1R", "Line In";
+                status = "disabled";
+
+                simple-audio-card,cpu {
+                        sound-dai = <&sai2>;
+                };
+
+                dailink_master: simple-audio-card,codec {
+                        sound-dai = <&tlv320>;
+                        clocks = <&clks IMX6UL_CLK_SAI2>;
+                };
+        };
+
+};
+
+&adc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_adc1>;
+        vref-supply = <&reg_adc1_vref_3v3>;
+        /*
+         * driver can not separate a specific channel so we request 4 channels
+         * here - we need only the fourth channel
+         */
+        num-channels = <4>;
+        status = "disabled";
+};
+
+&can1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_flexcan1>;
+        xceiver-supply = <&reg_can1_en>;
+        status = "disabled";
+};
+
+&clks {
+        assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+        assigned-clock-rates = <786432000>;
+};
+
+&fec2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet2>;
+        phy-mode = "rmii";
+        phy-handle = <&ethphy1>;
+        status = "disabled";
+};
+
+&i2c1 {
+        tlv320: codec@18 {
+                compatible = "ti,tlv320aic3007";
+                #sound-dai-cells = <0>;
+                reg = <0x18>;
+                AVDD-supply = <&reg_sound_3v3>;
+                IOVDD-supply = <&reg_sound_3v3>;
+                DRVDD-supply = <&reg_sound_3v3>;
+                DVDD-supply = <&reg_sound_1v8>;
+                status = "disabled";
+        };
+
+        stmpe: touchscreen@44 {
+                compatible = "st,stmpe811";
+                reg = <0x44>;
+                interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+                interrupt-parent = <&gpio5>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_stmpe>;
+                status = "disabled";
+
+                touchscreen {
+                        compatible = "st,stmpe-ts";
+                        st,sample-time = <4>;
+                        st,mod-12b = <1>;
+                        st,ref-sel = <0>;
+                        st,adc-freq = <1>;
+                        st,ave-ctrl = <1>;
+                        st,touch-det-delay = <2>;
+                        st,settling = <2>;
+                        st,fraction-z = <7>;
+                        st,i-drive = <1>;
+                        touchscreen-inverted-x = <1>;
+                        touchscreen-inverted-y = <1>;
+                };
+        };
+
+        i2c_rtc: rtc@68 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_rtc_int>;
+                compatible = "microcrystal,rv4162";
+                reg = <0x68>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+                status = "disabled";
+        };
+};
+
+&mdio {
+        ethphy1: ethernet-phy@2 {
+                reg = <2>;
+                micrel,led-mode = <1>;
+                clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+                clock-names = "rmii-ref";
+        };
+};
+
+&pwm3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm3>;
+        status = "disabled";
+};
+
+&sai2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_sai2>;
+        assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
+                        <&clks IMX6UL_CLK_SAI2>;
+        assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+        assigned-clock-rates = <0>, <19200000>;
+        fsl,sai-mclk-direction-output;
+        status = "disabled";
+};
+
+&uart5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart5>;
+        uart-has-rtscts;
+        status = "disabled";
+};
+
+&usbotg1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usb_otg1_id>;
+        dr_mode = "otg";
+        status = "disabled";
+};
+
+&usbotg2 {
+        dr_mode = "host";
+        disable-over-current;
+        status = "disabled";
+};
+
+&usdhc1 {
+        pinctrl-names = "default", "state_100mhz", "state_200mhz";
+        pinctrl-0 = <&pinctrl_usdhc1>;
+        pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+        pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+        cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+        no-1-8-v;
+        keep-power-in-suspend;
+        wakeup-source;
+        status = "disabled";
+};
+
+&iomuxc {
+        pinctrl_adc1: adc1grp {
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0xb0
+                >;
+        };
+
+        pinctrl_enet2: enet2grp {
+                fsl,pins = <
+                        MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
+                        MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
+                        MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+                        MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+                        MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
+                        MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+                        MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+                        MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
+                >;
+        };
+
+        pinctrl_flexcan1: flexcan1 {
+                fsl,pins = <
+                        MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x0b0b0
+                        MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x0b0b0
+                >;
+        };
+
+        princtrl_flexcan1_en: flexcan1engrp {
+                fsl,pins = <
+                        MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02      0x17059
+                >;
+        };
+
+        pinctrl_pwm3: pwm3grp {
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO04__PWM3_OUT  0x0b0b0
+                >;
+        };
+
+        pinctrl_rtc_int: rtcintgrp {
+                fsl,pins = <
+                        MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01      0x17059
+                >;
+        };
+
+        pinctrl_sai2: sai2grp {
+                fsl,pins = <
+                        MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x17088
+                        MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x17088
+                        MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x11088
+                        MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x11088
+                        MX6UL_PAD_JTAG_TMS__SAI2_MCLK           0x17088
+                >;
+        };
+
+        pinctrl_stmpe: stmpegrp {
+                fsl,pins = <
+                        MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x17059
+                >;
+        };
+
+        pinctrl_uart5: uart5grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX   0x1b0b1
+                        MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX   0x1b0b1
+                        MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x1b0b1
+                        MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x1b0b1
+                >;
+        };
+
+        pinctrl_usb_otg1_id: usbotg1idgrp {
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
+                >;
+        };
+
+        pinctrl_usdhc1: usdhc1grp {
+                fsl,pins = <
+                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
+                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10059
+                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
+                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
+                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
+                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
+                        MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059
+                >;
+        };
+
+        pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+                fsl,pins = <
+                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x170b9
+                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x100b9
+                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x170b9
+                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x170b9
+                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x170b9
+                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x170b9
+                >;
+        };
+
+        pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+                fsl,pins = <
+                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x170f9
+                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x100f9
+                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x170f9
+                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x170f9
+                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x170f9
+                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x170f9
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index 6c63a7384611..9ad1da159768 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -94,16 +94,16 @@
         pinctrl-names = "default", "gpio";
         pinctrl-0 = <&pinctrl_i2c1>;
         pinctrl-1 = <&pinctrl_i2c1_gpio>;
-        sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
-        scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+        sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+        scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 };
 
 &i2c2 {
         pinctrl-names = "default", "gpio";
         pinctrl-0 = <&pinctrl_i2c2>;
         pinctrl-1 = <&pinctrl_i2c2_gpio>;
-        sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
-        scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+        sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+        scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
         status = "okay";
 
         ad7879@2c {
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index f3668fe69eac..22e4a307fa59 100644
--- a/arch/arm/boot/dts/imx6ull.dtsi
+++ b/arch/arm/boot/dts/imx6ull.dtsi
@@ -30,6 +30,18 @@
         >;
 };
 
+&ocotp {
+        compatible = "fsl,imx6ull-ocotp", "syscon";
+};
+
+&usdhc1 {
+        compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
+};
+
+&usdhc2 {
+        compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
+};
+
 / {
         soc {
                 aips3: aips-bus@2200000 {
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index 6b298e388f4b..6eb98e7c568d 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -96,6 +96,14 @@
         };
 };
 
+&aips2 {
+        pcie_phy: pcie-phy@306d0000 {
+                  compatible = "fsl,imx7d-pcie-phy";
+                  reg = <0x306d0000 0x10000>;
+                  status = "disabled";
+        };
+};
+
 &aips3 {
         usbotg2: usb@30b20000 {
                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
@@ -173,6 +181,7 @@
                          <&src IMX7_RESET_PCIE_CTRL_APPS_EN>,
                          <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>;
                 reset-names = "pciephy", "apps", "turnoff";
+                fsl,imx7d-pcie-phy = <&pcie_phy>;
                 status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index 931b2754b099..fca6e50f37c8 100644
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -199,9 +199,13 @@
                         assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
                 };
 
-                smc1: smc1@40410000 {
+                smc1: clock-controller@40410000 {
                         compatible = "fsl,imx7ulp-smc1";
                         reg = <0x40410000 0x1000>;
+                        #clock-cells = <1>;
+                        clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
+                                 <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
+                        clock-names = "divcore", "hsrun_divcore";
                 };
 
                 pcc3: clock-controller@40b30000 {
@@ -343,4 +347,17 @@
                         gpio-ranges = <&iomuxc1 0 96 32>;
                 };
         };
+
+        m4aips1: bus@41080000 {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x41080000 0x80000>;
+                ranges;
+
+                sim: sim@410a3000 {
+                        compatible = "fsl,imx7ulp-sim", "syscon";
+                        reg = <0x410a3000 0x1000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi
index 4d58638d104b..1612a869a4f7 100644
--- a/arch/arm/boot/dts/integrator.dtsi
+++ b/arch/arm/boot/dts/integrator.dtsi
@@ -3,9 +3,15 @@
  * SoC core Device Tree for the ARM Integrator platforms
  */
 
-/include/ "skeleton.dtsi"
-
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x0>;
+        };
+
         core-module@10000000 {
                 compatible = "arm,core-module-integrator", "syscon", "simple-mfd";
                 reg = <0x10000000 0x200>;
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index a185ab8759fa..01fa229e1bd0 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -192,6 +192,43 @@
                 interrupts = <27>;
         };
 
+        bridge {
+                compatible = "ti,ths8134a", "ti,ths8134";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+
+                                vga_bridge_in: endpoint {
+                                        remote-endpoint = <&clcd_pads_vga_dac>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+
+                                vga_bridge_out: endpoint {
+                                        remote-endpoint = <&vga_con_in>;
+                                };
+                        };
+                };
+        };
+
+        vga {
+                compatible = "vga-connector";
+
+                port {
+                        vga_con_in: endpoint {
+                                remote-endpoint = <&vga_bridge_out>;
+                        };
+                };
+        };
+
         fpga {
                 /*
                  * These PrimeCells are at the same location and using
@@ -254,39 +291,27 @@
                         interrupts = <22>;
                         clocks = <&auxosc>, <&pclk>;
                         clock-names = "clcdclk", "apb_pclk";
+                        /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
+                        max-memory-bandwidth = <40000000>;
 
-                        port {
-                                /*
-                                 * The VGA connected is implemented with a
-                                 * THS8134A triple DAC that can be run in 24bit
-                                 * or 16bit RGB mode.
-                                 */
-                                clcd_pads: endpoint {
-                                        remote-endpoint = <&clcd_panel>;
-                                        arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
-                                };
-                        };
-
-                        panel {
-                                compatible = "panel-dpi";
-
-                                port {
-                                        clcd_panel: endpoint {
-                                                remote-endpoint = <&clcd_pads>;
-                                        };
-                                };
-
-                                /* Standard 640x480 VGA timings */
-                                panel-timing {
-                                        clock-frequency = <25175000>;
-                                        hactive = <640>;
-                                        hback-porch = <48>;
-                                        hfront-porch = <16>;
-                                        hsync-len = <96>;
-                                        vactive = <480>;
-                                        vback-porch = <33>;
-                                        vfront-porch = <10>;
-                                        vsync-len = <2>;
+                        /*
+                         * This port is routed through a PLD (Programmable
+                         * Logic Device) that routes the output from the CLCD
+                         * (after transformations) to the VGA DAC and also an
+                         * external panel connector. The PLD is essential for
+                         * supporting RGB565/BGR565.
+                         *
+                         * The signals from the port thus reaches two endpoints.
+                         * The PLD is managed through a few special bits in the
+                         * FPGA "sysreg".
+                         *
+                         * This arrangement can be clearly seen in
+                         * ARM DUI 0225D, page 3-41, figure 3-19.
+                         */
+                        port@0 {
+                                clcd_pads_vga_dac: endpoint {
+                                        remote-endpoint = <&vga_bridge_in>;
+                                        arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
                                 };
                         };
                 };
diff --git a/arch/arm/boot/dts/kirkwood-dir665.dts b/arch/arm/boot/dts/kirkwood-dir665.dts
index 31ceacd841de..b3ad3f607d31 100644
--- a/arch/arm/boot/dts/kirkwood-dir665.dts
+++ b/arch/arm/boot/dts/kirkwood-dir665.dts
@@ -190,53 +190,6 @@
                         gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
                 };
         };
-
-        dsa {
-                status = "disabled";
-
-                compatible = "marvell,dsa";
-                #address-cells = <2>;
-                #size-cells = <0>;
-
-                dsa,ethernet = <&eth0port>;
-                dsa,mii-bus = <&mdio>;
-
-                switch@0 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        reg = <0 0>;    /* MDIO address 0, switch 0 in tree */
-
-                        port@0 {
-                                reg = <0>;
-                                label = "lan4";
-                        };
-
-                        port@1 {
-                               reg = <1>;
-                               label = "lan3";
-                        };
-
-                        port@2 {
-                               reg = <2>;
-                               label = "lan2";
-                        };
-
-                        port@3 {
-                               reg = <3>;
-                               label = "lan1";
-                        };
-
-                        port@4 {
-                                reg = <4>;
-                                label = "wan";
-                        };
-
-                        port@6 {
-                               reg = <6>;
-                               label = "cpu";
-                        };
-                };
-        };
 };
 
 &mdio {
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index cbaf06f2f78e..eb917462b219 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -36,8 +36,8 @@
                 compatible = "gpio-fan";
                 pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>;
                 pinctrl-names = "default";
-                gpios = <&gpio1 14 GPIO_ACTIVE_LOW
-                         &gpio1 13 GPIO_ACTIVE_LOW>;
+                gpios = <&gpio1 14 GPIO_ACTIVE_HIGH
+                         &gpio1 13 GPIO_ACTIVE_HIGH>;
                 gpio-fan,speed-map = <0    0
                                       3000 1
                                       6000 2>;
diff --git a/arch/arm/boot/dts/kirkwood-linksys-viper.dts b/arch/arm/boot/dts/kirkwood-linksys-viper.dts
index a7d659b7145a..2f9660f3b457 100644
--- a/arch/arm/boot/dts/kirkwood-linksys-viper.dts
+++ b/arch/arm/boot/dts/kirkwood-linksys-viper.dts
@@ -66,53 +66,6 @@
                         gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
                 };
         };
-
-        dsa {
-                status = "disabled";
-
-                compatible = "marvell,dsa";
-                #address-cells = <2>;
-                #size-cells = <0>;
-
-                dsa,ethernet = <&eth0port>;
-                dsa,mii-bus = <&mdio>;
-
-                switch@16,0 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        reg = <16 0>;   /* MDIO address 16, switch 0 in tree */
-
-                        port@0 {
-                                reg = <0>;
-                                label = "ethernet1";
-                        };
-
-                        port@1 {
-                                reg = <1>;
-                                label = "ethernet2";
-                        };
-
-                        port@2 {
-                                reg = <2>;
-                                label = "ethernet3";
-                        };
-
-                        port@3 {
-                                reg = <3>;
-                                label = "ethernet4";
-                        };
-
-                        port@4 {
-                                reg = <4>;
-                                label = "internet";
-                        };
-
-                        port@5 {
-                                reg = <5>;
-                                label = "cpu";
-                        };
-                };
-        };
 };
 
 &pinctrl {
diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
index 86d532916d56..2e1a75348908 100644
--- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
+++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
@@ -107,53 +107,6 @@
                         gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
                 };
         };
-
-        dsa {
-                status = "disabled";
-
-                compatible = "marvell,dsa";
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                dsa,ethernet = <&eth0port>;
-                dsa,mii-bus = <&mdio>;
-
-                switch@0 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        reg = <0 0>;    /* MDIO address 0, switch 0 in tree */
-
-                        port@0 {
-                                reg = <0>;
-                                label = "lan1";
-                        };
-
-                        port@1 {
-                                reg = <1>;
-                                label = "lan2";
-                        };
-
-                        port@2 {
-                                reg = <2>;
-                                label = "lan3";
-                        };
-
-                        port@3 {
-                                reg = <3>;
-                                label = "lan4";
-                        };
-
-                        port@4 {
-                                reg = <4>;
-                                label = "wan";
-                        };
-
-                        port@5 {
-                                reg = <5>;
-                                label = "cpu";
-                        };
-                };
-        };
 };
 
 &mdio {
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts
index a9fee2c2bcaf..9d88301daf0e 100644
--- a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts
@@ -16,15 +16,6 @@
         model = "Marvell RD88f6281 Reference design, with Z0 SoC";
         compatible = "marvell,rd88f6281-z0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
 
-        dsa {
-                switch@0 {
-                        reg = <0 0>;    /* MDIO address 0, switch 0 in tree */
-                        port@4 {
-                                reg = <4>;
-                                label = "wan";
-                        };
-                };
-        };
 };
 
 &eth1 {
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
index 0f22f0e6f56b..f1f8eee132e8 100644
--- a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
@@ -48,47 +48,6 @@
                         cd-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
                         /* No WP GPIO */
                 };
-        };
-
-        dsa {
-                status = "disabled";
-
-                compatible = "marvell,dsa";
-                #address-cells = <2>;
-                #size-cells = <0>;
-
-                dsa,ethernet = <&eth0port>;
-                dsa,mii-bus = <&mdio>;
-
-                switch@0 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        port@0 {
-                                reg = <0>;
-                                label = "lan1";
-                        };
-
-                        port@1 {
-                                reg = <1>;
-                                label = "lan2";
-                        };
-
-                        port@2 {
-                                reg = <2>;
-                                label = "lan3";
-                        };
-
-                        port@3 {
-                                reg = <3>;
-                                label = "lan4";
-                        };
-
-                        port@5 {
-                                reg = <5>;
-                                label = "cpu";
-                        };
-                };
        };
 };
 
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 81c7eda2c442..2161e23bd98e 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -1,11 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0
-/include/ "skeleton.dtsi"
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
 
 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "marvell,kirkwood";
         interrupt-parent = <&intc>;
 
diff --git a/arch/arm/boot/dts/lpc3250-ea3250.dts b/arch/arm/boot/dts/lpc3250-ea3250.dts
index 58ea0a4e7afa..f46a11827ef6 100644
--- a/arch/arm/boot/dts/lpc3250-ea3250.dts
+++ b/arch/arm/boot/dts/lpc3250-ea3250.dts
@@ -17,64 +17,70 @@
 / {
         model = "Embedded Artists LPC3250 board based on NXP LPC3250";
         compatible = "ea,ea3250", "nxp,lpc3250";
-        #address-cells = <1>;
-        #size-cells = <1>;
 
-        memory {
+        memory@80000000 {
                 device_type = "memory";
                 reg = <0x80000000 0x4000000>;
         };
 
-        gpio_keys {
+        gpio-keys {
                 compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
                 autorepeat;
-                button@21 {
+
+                button {
                         label = "Interrupt Key";
                         linux,code = <103>;
                         gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
                 };
+
                 key1 {
                         label = "KEY1";
                         linux,code = <1>;
                         gpios = <&pca9532 0 0>;
                 };
+
                 key2 {
                         label = "KEY2";
                         linux,code = <2>;
                         gpios = <&pca9532 1 0>;
                 };
+
                 key3 {
                         label = "KEY3";
                         linux,code = <3>;
                         gpios = <&pca9532 2 0>;
                 };
+
                 key4 {
                         label = "KEY4";
                         linux,code = <4>;
                         gpios = <&pca9532 3 0>;
                 };
+
                 joy0 {
                         label = "Joystick Key 0";
                         linux,code = <10>;
                         gpios = <&gpio 2 0 0>; /* P2.0 */
                 };
+
                 joy1 {
                         label = "Joystick Key 1";
                         linux,code = <11>;
                         gpios = <&gpio 2 1 0>; /* P2.1 */
                 };
+
                 joy2 {
                         label = "Joystick Key 2";
                         linux,code = <12>;
                         gpios = <&gpio 2 2 0>; /* P2.2 */
                 };
+
                 joy3 {
                         label = "Joystick Key 3";
                         linux,code = <13>;
                         gpios = <&gpio 2 3 0>; /* P2.3 */
                 };
+
                 joy4 {
                         label = "Joystick Key 4";
                         linux,code = <14>;
diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts
index 1e1c2f517a82..ebd19258e22b 100644
--- a/arch/arm/boot/dts/lpc3250-phy3250.dts
+++ b/arch/arm/boot/dts/lpc3250-phy3250.dts
@@ -1,6 +1,7 @@
 /*
  * PHYTEC phyCORE-LPC3250 board
  *
+ * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
  * Copyright 2012 Roland Stigge <stigge@antcom.de>
  *
  * The code contained herein is licensed under the GNU General Public
@@ -17,45 +18,12 @@
 / {
         model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
         compatible = "phytec,phy3250", "nxp,lpc3250";
-        #address-cells = <1>;
-        #size-cells = <1>;
 
-        memory {
+        memory@80000000 {
                 device_type = "memory";
                 reg = <0x80000000 0x4000000>;
         };
 
-        regulators {
-                backlight_reg: regulator@0 {
-                        compatible = "regulator-fixed";
-                        regulator-name = "backlight_reg";
-                        regulator-min-microvolt = <1800000>;
-                        regulator-max-microvolt = <1800000>;
-                        gpio = <&gpio 5 4 0>;
-                        enable-active-high;
-                        regulator-boot-on;
-                };
-
-                lcd_reg: regulator@1 {
-                        compatible = "regulator-fixed";
-                        regulator-name = "lcd_reg";
-                        regulator-min-microvolt = <1800000>;
-                        regulator-max-microvolt = <1800000>;
-                        gpio = <&gpio 5 0 0>;
-                        enable-active-high;
-                        regulator-boot-on;
-                };
-
-                sd_reg: regulator@2 {
-                        compatible = "regulator-fixed";
-                        regulator-name = "sd_reg";
-                        regulator-min-microvolt = <1800000>;
-                        regulator-max-microvolt = <1800000>;
-                        gpio = <&gpio 5 5 0>;
-                        enable-active-high;
-                };
-        };
-
         leds {
                 compatible = "gpio-leds";
 
@@ -69,10 +37,59 @@
                         linux,default-trigger = "heartbeat";
                 };
         };
+
+        panel: panel {
+                compatible = "sharp,lq035q7db03";
+                power-supply = <&reg_lcd>;
+
+                port {
+                        panel_input: endpoint {
+                                remote-endpoint = <&cldc_output>;
+                        };
+                };
+        };
+
+        reg_backlight: regulator-backlight {
+                compatible = "regulator-fixed";
+                regulator-name = "backlight";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                gpio = <&gpio 5 4 0>;
+                enable-active-high;
+                regulator-boot-on;
+        };
+
+        reg_lcd: regulator-lcd {
+                compatible = "regulator-fixed";
+                regulator-name = "lcd";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                gpio = <&gpio 5 0 0>;
+                enable-active-high;
+                regulator-boot-on;
+        };
+
+        reg_sd: regulator-sd {
+                compatible = "regulator-fixed";
+                regulator-name = "sd";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio 5 5 0>;
+                enable-active-high;
+                regulator-boot-on;
+        };
 };
 
 &clcd {
+        max-memory-bandwidth = <18710000>;
         status = "okay";
+
+        port {
+                cldc_output: endpoint {
+                        remote-endpoint = <&panel_input>;
+                        arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
+                };
+        };
 };
 
 &i2c1 {
@@ -130,7 +147,7 @@
         cd-gpios = <&gpio 3 1 0>;
         cd-inverted;
         bus-width = <4>;
-        vmmc-supply = <&sd_reg>;
+        vmmc-supply = <&reg_sd>;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index b7303a4e4236..20b38f4ade37 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -11,12 +11,12 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include "skeleton.dtsi"
-
 #include <dt-bindings/clock/lpc32xx-clock.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "nxp,lpc3220";
         interrupt-parent = <&mic>;
 
@@ -139,11 +139,11 @@
                 };
 
                 clcd: clcd@31040000 {
-                        compatible = "arm,pl110", "arm,primecell";
+                        compatible = "arm,pl111", "arm,primecell";
                         reg = <0x31040000 0x1000>;
                         interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clk LPC32XX_CLK_LCD>;
-                        clock-names = "apb_pclk";
+                        clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>;
+                        clock-names = "clcdclk", "apb_pclk";
                         status = "disabled";
                 };
 
@@ -230,7 +230,7 @@
                                 status = "disabled";
                         };
 
-                        i2s1: i2s@2009C000 {
+                        i2s1: i2s@2009c000 {
                                 compatible = "nxp,lpc3220-i2s";
                                 reg = <0x2009C000 0x1000>;
                         };
@@ -273,7 +273,7 @@
                                 status = "disabled";
                         };
 
-                        i2c1: i2c@400A0000 {
+                        i2c1: i2c@400a0000 {
                                 compatible = "nxp,pnx-i2c";
                                 reg = <0x400A0000 0x100>;
                                 interrupt-parent = <&sic1>;
@@ -284,7 +284,7 @@
                                 clocks = <&clk LPC32XX_CLK_I2C1>;
                         };
 
-                        i2c2: i2c@400A8000 {
+                        i2c2: i2c@400a8000 {
                                 compatible = "nxp,pnx-i2c";
                                 reg = <0x400A8000 0x100>;
                                 interrupt-parent = <&sic1>;
@@ -295,7 +295,7 @@
                                 clocks = <&clk LPC32XX_CLK_I2C2>;
                         };
 
-                        mpwm: mpwm@400E8000 {
+                        mpwm: mpwm@400e8000 {
                                 compatible = "nxp,lpc3220-motor-pwm";
                                 reg = <0x400E8000 0x78>;
                                 status = "disabled";
@@ -394,7 +394,7 @@
                                 #gpio-cells = <3>; /* bank, pin, flags */
                         };
 
-                        timer4: timer@4002C000 {
+                        timer4: timer@4002c000 {
                                 compatible = "nxp,lpc3220-timer";
                                 reg = <0x4002C000 0x1000>;
                                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
@@ -412,7 +412,7 @@
                                 status = "disabled";
                         };
 
-                        watchdog: watchdog@4003C000 {
+                        watchdog: watchdog@4003c000 {
                                 compatible = "nxp,pnx4008-wdt";
                                 reg = <0x4003C000 0x1000>;
                                 clocks = <&clk LPC32XX_CLK_WDOG>;
@@ -451,7 +451,7 @@
                                 status = "disabled";
                         };
 
-                        timer1: timer@4004C000 {
+                        timer1: timer@4004c000 {
                                 compatible = "nxp,lpc3220-timer";
                                 reg = <0x4004C000 0x1000>;
                                 interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
@@ -462,7 +462,9 @@
                         key: key@40050000 {
                                 compatible = "nxp,lpc3220-key";
                                 reg = <0x40050000 0x1000>;
-                                interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clk LPC32XX_CLK_KEY>;
+                                interrupt-parent = <&sic1>;
+                                interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
                                 status = "disabled";
                         };
 
@@ -475,7 +477,7 @@
                                 status = "disabled";
                         };
 
-                        pwm1: pwm@4005C000 {
+                        pwm1: pwm@4005c000 {
                                 compatible = "nxp,lpc3220-pwm";
                                 reg = <0x4005C000 0x4>;
                                 clocks = <&clk LPC32XX_CLK_PWM1>;
@@ -484,7 +486,7 @@
                                 status = "disabled";
                         };
 
-                        pwm2: pwm@4005C004 {
+                        pwm2: pwm@4005c004 {
                                 compatible = "nxp,lpc3220-pwm";
                                 reg = <0x4005C004 0x4>;
                                 clocks = <&clk LPC32XX_CLK_PWM2>;
diff --git a/arch/arm/boot/dts/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/lpc4350-hitex-eval.dts
index 8b973f537d3a..93d0c2e99e7c 100644
--- a/arch/arm/boot/dts/lpc4350-hitex-eval.dts
+++ b/arch/arm/boot/dts/lpc4350-hitex-eval.dts
@@ -40,8 +40,6 @@
 
         pca_buttons {
                 compatible = "gpio-keys-polled";
-                #address-cells = <1>;
-                #size-cells = <0>;
                 poll-interval = <100>;
                 autorepeat;
 
diff --git a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts
index 02b23fa29d75..224f80a4a31d 100644
--- a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts
+++ b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts
@@ -57,8 +57,6 @@
                 compatible = "gpio-keys-polled";
                 pinctrl-names = "default";
                 pinctrl-0 = <&gpio_joystick_pins>;
-                #address-cells = <1>;
-                #size-cells = <0>;
                 poll-interval = <100>;
                 autorepeat;
 
diff --git a/arch/arm/boot/dts/lpc4357-myd-lpc4357.dts b/arch/arm/boot/dts/lpc4357-myd-lpc4357.dts
new file mode 100644
index 000000000000..1f84654df50c
--- /dev/null
+++ b/arch/arm/boot/dts/lpc4357-myd-lpc4357.dts
@@ -0,0 +1,619 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel
+ *
+ * Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
+ */
+
+/dts-v1/;
+
+#include "lpc18xx.dtsi"
+#include "lpc4357.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "MYIR Tech LPC4357 Development Board";
+        compatible = "myir,myd-lpc4357", "nxp,lpc4357";
+
+        chosen {
+                stdout-path = "serial3:115200n8";
+        };
+
+        memory@28000000 {
+                device_type = "memory";
+                reg = <0x28000000 0x2000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins>;
+
+                led1 {
+                        gpios = <&gpio LPC_GPIO(6,15) GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+
+                led2 {
+                        gpios = <&gpio LPC_GPIO(6,16) GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+
+                led3 {
+                        gpios = <&gpio LPC_GPIO(6,17) GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+
+                led4 {
+                        gpios = <&gpio LPC_GPIO(6,10) GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+
+                led5 {
+                        gpios = <&gpio LPC_GPIO(7,14) GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+
+                led6 {
+                        gpios = <&gpio LPC_GPIO(6,14) GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+        };
+
+        panel: panel {
+                compatible = "innolux,at070tn92";
+
+                port {
+                        panel_input: endpoint {
+                                remote-endpoint = <&lcdc_output>;
+                        };
+                };
+        };
+
+        vcc: vcc_fixed {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc-supply";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        vmmc: vmmc_fixed {
+                compatible = "regulator-fixed";
+                regulator-name = "vmmc-supply";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+};
+
+&pinctrl {
+        can0_pins: can0-pins {
+                can_rd_cfg {
+                        pins = "p3_1";
+                        function = "can0";
+                        input-enable;
+                };
+
+                can_td_cfg {
+                        pins = "p3_2";
+                        function = "can0";
+                };
+        };
+
+        can1_pins: can1-pins {
+                can_rd_cfg {
+                        pins = "pe_1";
+                        function = "can1";
+                        input-enable;
+                };
+
+                can_td_cfg {
+                        pins = "pe_0";
+                        function = "can1";
+                };
+        };
+
+        emc_pins: emc-pins {
+                emc_addr0_22_cfg {
+                        pins = "p2_9",  "p2_10", "p2_11", "p2_12",
+                               "p2_13", "p1_0",  "p1_1",  "p1_2",
+                               "p2_8",  "p2_7",  "p2_6",  "p2_2",
+                               "p2_1",  "p2_0",  "p6_8",  "p6_7",
+                               "pd_16", "pd_15", "pe_0",  "pe_1",
+                               "pe_2",  "pe_3",  "pe_4";
+                        function = "emc";
+                        slew-rate = <1>;
+                        bias-disable;
+                };
+
+                emc_data0_15_cfg {
+                        pins = "p1_7",  "p1_8",  "p1_9",  "p1_10",
+                               "p1_11", "p1_12", "p1_13", "p1_14",
+                               "p5_4",  "p5_5",  "p5_6",  "p5_7",
+                               "p5_0",  "p5_1",  "p5_2",  "p5_3";
+                        function = "emc";
+                        input-enable;
+                        input-schmitt-disable;
+                        slew-rate = <1>;
+                        bias-disable;
+                };
+
+                emc_we_oe_cfg {
+                        pins = "p1_6", "p1_3";
+                        function = "emc";
+                        slew-rate = <1>;
+                        bias-disable;
+                };
+
+                emc_cs0_cfg {
+                        pins = "p1_5";
+                        function = "emc";
+                        slew-rate = <1>;
+                        bias-disable;
+                };
+
+                emc_sdram_dqm0_1_cfg {
+                        pins = "p6_12", "p6_10";
+                        function = "emc";
+                        slew-rate = <1>;
+                        bias-disable;
+                };
+
+                emc_sdram_ras_cas_cfg {
+                        pins = "p6_5", "p6_4";
+                        function = "emc";
+                        slew-rate = <1>;
+                        bias-disable;
+                };
+
+                emc_sdram_dycs0_cfg {
+                        pins = "p6_9";
+                        function = "emc";
+                        slew-rate = <1>;
+                        bias-disable;
+                };
+
+                emc_sdram_cke_cfg {
+                        pins = "p6_11";
+                        function = "emc";
+                        slew-rate = <1>;
+                        bias-disable;
+                };
+
+                emc_sdram_clock_cfg {
+                        pins = "clk0";
+                        function = "emc";
+                        input-enable;
+                        input-schmitt-disable;
+                        slew-rate = <1>;
+                        bias-disable;
+                };
+        };
+
+        enet_rmii_pins: enet-rmii-pins {
+                enet_rmii_rxd_cfg {
+                        pins = "p1_15", "p0_0";
+                        function = "enet";
+                        input-enable;
+                        input-schmitt-disable;
+                        slew-rate = <1>;
+                        bias-disable;
+                };
+
+                enet_rmii_txd_cfg {
+                        pins = "p1_18", "p1_20";
+                        function = "enet";
+                        slew-rate = <1>;
+                        bias-disable;
+                };
+
+                enet_rmii_rx_dv_cfg {
+                        pins = "p1_16";
+                        function = "enet";
+                        input-enable;
+                        input-schmitt-disable;
+                        bias-disable;
+                };
+
+                enet_mdio_cfg {
+                        pins = "p1_17";
+                        function = "enet";
+                        input-enable;
+                        input-schmitt-disable;
+                        bias-disable;
+                };
+
+                enet_mdc_cfg {
+                        pins = "pc_1";
+                        function = "enet";
+                        slew-rate = <1>;
+                        bias-disable;
+                };
+
+                enet_rmii_tx_en_cfg {
+                        pins = "p0_1";
+                        function = "enet";
+                        bias-disable;
+                };
+
+                enet_ref_clk_cfg {
+                        pins = "p1_19";
+                        function = "enet";
+                        slew-rate = <1>;
+                        input-enable;
+                        input-schmitt-disable;
+                        bias-disable;
+                };
+        };
+
+        i2c0_pins: i2c0-pins {
+                i2c0_pins_cfg {
+                        pins = "i2c0_scl", "i2c0_sda";
+                        function = "i2c0";
+                        input-enable;
+                };
+        };
+
+        i2c1_pins: i2c1-pins {
+                i2c1_pins_cfg {
+                        pins = "pe_15", "pe_13";
+                        function = "i2c1";
+                        input-enable;
+                };
+        };
+
+        lcd_pins: lcd-pins {
+                lcd_vd0_23_cfg {
+                        pins = "p4_1", "p4_4", "p4_3",  "p4_2",
+                               "p8_7", "p8_6", "p8_5",  "p8_4",
+                               "p7_5", "p4_8", "p4_10", "p4_9",
+                               "p8_3", "pb_6", "pb_5",  "pb_4",
+                               "p7_4", "p7_3", "p7_2",  "p7_1",
+                               "pb_3", "pb_2", "pb_1",  "pb_0";
+                        function = "lcd";
+                };
+
+                lcd_vsync_en_dclk_lp_pwr_cfg {
+                        pins = "p4_5", "p4_6", "p4_7", "p7_6", "p7_7";
+                        function = "lcd";
+                };
+        };
+
+        led_pins: led-pins {
+                led_1_6_cfg {
+                        pins = "pd_1", "pd_2", "pd_3", "pc_11", "pe_14", "pd_0";
+                        function = "gpio";
+                        bias-pull-down;
+                };
+        };
+
+        sdmmc_pins: sdmmc-pins {
+                sdmmc_clk_cfg {
+                        pins = "pc_0";
+                        function = "sdmmc";
+                        slew-rate = <1>;
+                        bias-pull-down;
+                };
+
+                sdmmc_cmd_dat0_3_cfg {
+                        pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10";
+                        function = "sdmmc";
+                        input-enable;
+                        input-schmitt-disable;
+                        slew-rate = <1>;
+                        bias-disable;
+                };
+
+                sdmmc_cd_cfg {
+                        pins = "pc_8";
+                        function = "sdmmc";
+                        input-enable;
+                        bias-pull-down;
+                };
+        };
+
+        spifi_pins: spifi-pins {
+                spifi_sck_cfg {
+                        pins = "p3_3";
+                        function = "spifi";
+                        input-enable;
+                        input-schmitt-disable;
+                        slew-rate = <1>;
+                        bias-disable;
+                };
+
+                spifi_mosi_miso_sio2_sio3_cfg {
+                        pins = "p3_7", "p3_6", "p3_5", "p3_4";
+                        function = "spifi";
+                        input-enable;
+                        input-schmitt-disable;
+                        slew-rate = <1>;
+                        bias-disable;
+                };
+
+                spifi_cs_cfg {
+                        pins = "p3_8";
+                        function = "spifi";
+                        bias-disable;
+                };
+        };
+
+        ssp1_pins: ssp1-pins {
+                ssp1_sck_cfg {
+                        pins = "pf_4";
+                        function = "ssp1";
+                        slew-rate = <1>;
+                        bias-pull-down;
+                };
+
+                ssp1_miso_cfg {
+                        pins = "pf_6";
+                        function = "ssp1";
+                        input-enable;
+                        input-schmitt-disable;
+                        slew-rate = <1>;
+                        bias-pull-down;
+                };
+
+                ssp1_mosi_cfg {
+                        pins = "pf_7";
+                        function = "ssp1";
+                        slew-rate = <1>;
+                        bias-pull-down;
+                };
+
+                ssp1_ssel_cfg {
+                        pins = "pf_5";
+                        function = "gpio";
+                        bias-disable;
+                };
+        };
+
+        uart0_pins: uart0-pins {
+                uart0_rxd_cfg {
+                        pins = "pf_11";
+                        function = "uart0";
+                        input-enable;
+                        input-schmitt-disable;
+                        bias-disable;
+                };
+
+                uart0_clk_dir_txd_cfg {
+                        pins = "pf_8", "pf_9", "pf_10";
+                        function = "uart0";
+                        bias-pull-down;
+                };
+        };
+
+        uart1_pins: uart1-pins {
+                uart1_rxd_cfg {
+                        pins = "pc_14";
+                        function = "uart1";
+                        bias-disable;
+                        input-enable;
+                        input-schmitt-disable;
+                };
+
+                uart1_dtr_txd_cfg {
+                        pins = "pc_12", "pc_13";
+                        function = "uart1";
+                        bias-pull-down;
+                };
+        };
+
+        uart2_pins: uart2-pins {
+                uart2_rxd_cfg {
+                        pins = "pa_2";
+                        function = "uart2";
+                        bias-disable;
+                        input-enable;
+                        input-schmitt-disable;
+                };
+
+                uart2_txd_cfg {
+                        pins = "pa_1";
+                        function = "uart2";
+                        bias-pull-down;
+                };
+        };
+
+        uart3_pins: uart3-pins {
+                uart3_rx_cfg {
+                        pins = "p2_4";
+                        function = "uart3";
+                        bias-disable;
+                        input-enable;
+                        input-schmitt-disable;
+                };
+
+                uart3_tx_cfg {
+                        pins = "p2_3";
+                        function = "uart3";
+                        bias-pull-down;
+                };
+        };
+
+        usb0_pins: usb0-pins {
+                usb0_pwr_enable_cfg {
+                        pins = "p6_3";
+                        function = "usb0";
+                };
+
+                usb0_pwr_fault_cfg {
+                        pins = "p8_0";
+                        function = "usb0";
+                        bias-disable;
+                        input-enable;
+                };
+        };
+};
+
+&adc1 {
+        status = "okay";
+        vref-supply = <&vcc>;
+};
+
+&can0 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&can0_pins>;
+};
+
+/* Pin conflict with EMC, muxed by JP5 and JP6 */
+&can1 {
+        status = "disabled";
+        pinctrl-names = "default";
+        pinctrl-0 = <&can1_pins>;
+};
+
+&emc {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&emc_pins>;
+
+        cs0 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges;
+
+                mpmc,cs = <0>;
+                mpmc,memory-width = <16>;
+                mpmc,byte-lane-low;
+                mpmc,write-enable-delay = <0>;
+                mpmc,output-enable-delay = <0>;
+                mpmc,read-access-delay = <70>;
+                mpmc,page-mode-read-delay = <70>;
+
+                /* SST/Microchip SST39VF1601 */
+                flash@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0 0 0x400000>;
+                        bank-width = <2>;
+                };
+        };
+};
+
+&enet_tx_clk {
+        clock-frequency = <50000000>;
+};
+
+&i2c0 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_pins>;
+        clock-frequency = <400000>;
+};
+
+&i2c1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
+        clock-frequency = <400000>;
+
+        sensor@49 {
+                compatible = "lm75";
+                reg = <0x49>;
+        };
+
+        eeprom@50 {
+                compatible = "atmel,24c512";
+                reg = <0x50>;
+        };
+};
+
+&lcdc {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&lcd_pins>;
+
+        max-memory-bandwidth = <92240000>;
+
+        port {
+                lcdc_output: endpoint {
+                        remote-endpoint = <&panel_input>;
+                        arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
+                };
+        };
+};
+
+&mac {
+        status = "okay";
+        phy-mode = "rmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&enet_rmii_pins>;
+        phy-handle = <&phy1>;
+
+        mdio0 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "snps,dwmac-mdio";
+
+                phy1: ethernet-phy@1 {
+                        reg = <1>;
+                };
+        };
+};
+
+&mmcsd {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&sdmmc_pins>;
+        bus-width = <4>;
+        vmmc-supply = <&vmmc>;
+};
+
+/* Pin conflict with SSP0, the latter is routed to J17 pin header */
+&spifi {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&spifi_pins>;
+
+        /* Atmel AT25DF321A */
+        flash {
+                compatible = "jedec,spi-nor";
+                spi-max-frequency = <51000000>;
+                spi-cpol;
+                spi-cpha;
+        };
+};
+
+&ssp1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&ssp1_pins>;
+        num-cs = <1>;
+        cs-gpios = <&gpio LPC_GPIO(7,19) GPIO_ACTIVE_LOW>;
+};
+
+/* Routed to J17 pin header */
+&uart0 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins>;
+};
+
+/* RS485 */
+&uart1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart1_pins>;
+};
+
+/* Routed to J17 pin header */
+&uart2 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart2_pins>;
+};
+
+&uart3 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
+
+&usb0 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb0_pins>;
+};
diff --git a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
index 6a83f30029ea..ba1ddd93b8f8 100644
--- a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
+++ b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
@@ -18,6 +18,7 @@
 
 / {
         model = "Moxa UC-8410A";
+        compatible = "fsl,ls1021a-moxa-uc-8410a", "fsl,ls1021a";
 
         aliases {
                 enet0_rgmii_phy = &rgmii_phy0;
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 923a25760516..ca60730dda40 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -51,6 +51,7 @@
 
 / {
         model = "LS1021A QDS Board";
+        compatible = "fsl,ls1021a-qds", "fsl,ls1021a";
 
         aliases {
                 enet0_rgmii_phy = &rgmii_phy1;
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index 8b48c3c7cd21..97e1fb7ea932 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -51,6 +51,7 @@
 
 / {
         model = "LS1021A TWR Board";
+        compatible = "fsl,ls1021a-twr", "fsl,ls1021a";
 
         aliases {
                 enet2_rgmii_phy = &rgmii_phy1;
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index ed0941292172..b4f2723ecd86 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -45,11 +45,12 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include "skeleton64.dtsi"
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/thermal/thermal.h>
 
 / {
+        #address-cells = <2>;
+        #size-cells = <2>;
         compatible = "fsl,ls1021a";
         interrupt-parent = <&gic>;
 
@@ -88,6 +89,11 @@
                 };
         };
 
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x0>;
+        };
+
         sysclk: sysclk {
                 compatible = "fixed-clock";
                 #clock-cells = <0>;
@@ -125,6 +131,13 @@
                 interrupt-parent = <&gic>;
                 ranges;
 
+                ddr: memory-controller@1080000 {
+                        compatible = "fsl,qoriq-memory-controller";
+                        reg = <0x0 0x1080000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+                        big-endian;
+                };
+
                 gic: interrupt-controller@1400000 {
                         compatible = "arm,gic-400", "arm,cortex-a7-gic";
                         #interrupt-cells = <3>;
@@ -706,6 +719,7 @@
                         fsl,tmr-fiper1  = <999999995>;
                         fsl,tmr-fiper2  = <99990>;
                         fsl,max-adj     = <499999999>;
+                        fsl,extts-fifo;
                 };
 
                 enet0: ethernet@2d10000 {
@@ -811,6 +825,7 @@
                         dr_mode = "host";
                         snps,quirk-frame-length-adjustment = <0x20>;
                         snps,dis_rxdet_inp3_quirk;
+                        snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
                 };
 
                 pcie@3400000 {
@@ -824,6 +839,7 @@
                         #size-cells = <2>;
                         device_type = "pci";
                         num-lanes = <4>;
+                        num-viewport = <6>;
                         bus-range = <0x0 0xff>;
                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
@@ -848,6 +864,7 @@
                         #size-cells = <2>;
                         device_type = "pci";
                         num-lanes = <4>;
+                        num-viewport = <6>;
                         bus-range = <0x0 0xff>;
                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index e4645f612712..6f54a8897574 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -47,9 +47,10 @@
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
-/include/ "skeleton.dtsi"
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         interrupt-parent = <&gic>;
 
         L2: l2-cache-controller@c4200000 {
@@ -72,6 +73,13 @@
                         #size-cells = <1>;
                         ranges = <0x0 0xc1100000 0x200000>;
 
+                        hhi: system-controller@4000 {
+                                compatible = "amlogic,meson-hhi-sysctrl",
+                                             "simple-mfd",
+                                             "syscon";
+                                reg = <0x4000 0x400>;
+                        };
+
                         assist: assist@7c00 {
                                 compatible = "amlogic,meson-mx-assist", "syscon";
                                 reg = <0x7c00 0x200>;
@@ -274,7 +282,7 @@
                         compatible = "amlogic,meson6-dwmac", "snps,dwmac";
                         reg = <0xc9410000 0x10000
                                0xc1108108 0x4>;
-                        interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
+                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "macirq";
                         status = "disabled";
                 };
diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts
index fc48cff71ddf..997e69c5963e 100644
--- a/arch/arm/boot/dts/meson6-atv1200.dts
+++ b/arch/arm/boot/dts/meson6-atv1200.dts
@@ -61,6 +61,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x40000000 0x80000000>;
         };
 };
diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
index ca978ab952cd..65585255910a 100644
--- a/arch/arm/boot/dts/meson6.dtsi
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -70,6 +70,14 @@
                 };
         };
 
+        apb2: bus@d0000000 {
+                compatible = "simple-bus";
+                reg = <0xd0000000 0x40000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x0 0xd0000000 0x40000>;
+        };
+
         xtal: xtal-clk {
                 compatible = "fixed-clock";
                 clock-frequency = <24000000>;
diff --git a/arch/arm/boot/dts/meson8-minix-neo-x8.dts b/arch/arm/boot/dts/meson8-minix-neo-x8.dts
index 55fb090a40ef..8686abd5de7f 100644
--- a/arch/arm/boot/dts/meson8-minix-neo-x8.dts
+++ b/arch/arm/boot/dts/meson8-minix-neo-x8.dts
@@ -57,6 +57,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x40000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index e5cd325d7ea8..a9781243453e 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -166,6 +166,32 @@
                 };
         };
 
+        gpu_opp_table: gpu-opp-table {
+                compatible = "operating-points-v2";
+
+                opp-182150000 {
+                        opp-hz = /bits/ 64 <182150000>;
+                        opp-microvolt = <1150000>;
+                };
+                opp-318750000 {
+                        opp-hz = /bits/ 64 <318750000>;
+                        opp-microvolt = <1150000>;
+                };
+                opp-425000000 {
+                        opp-hz = /bits/ 64 <425000000>;
+                        opp-microvolt = <1150000>;
+                };
+                opp-510000000 {
+                        opp-hz = /bits/ 64 <510000000>;
+                        opp-microvolt = <1150000>;
+                };
+                opp-637500000 {
+                        opp-hz = /bits/ 64 <637500000>;
+                        opp-microvolt = <1150000>;
+                        turbo-mode;
+                };
+        };
+
         pmu {
                 compatible = "arm,cortex-a9-pmu";
                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
@@ -201,6 +227,46 @@
                         no-map;
                 };
         };
+
+        apb: bus@d0000000 {
+                compatible = "simple-bus";
+                reg = <0xd0000000 0x200000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x0 0xd0000000 0x200000>;
+
+                mali: gpu@c0000 {
+                        compatible = "amlogic,meson8-mali", "arm,mali-450";
+                        reg = <0xc0000 0x40000>;
+                        interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "gp", "gpmmu", "pp", "pmu",
+                                          "pp0", "ppmmu0", "pp1", "ppmmu1",
+                                          "pp2", "ppmmu2", "pp4", "ppmmu4",
+                                          "pp5", "ppmmu5", "pp6", "ppmmu6";
+                        resets = <&reset RESET_MALI>;
+                        clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
+                        clock-names = "bus", "core";
+                        operating-points-v2 = <&gpu_opp_table>;
+                        switch-delay = <0xffff>;
+                };
+        };
 }; /* end of / */
 
 &aobus {
@@ -261,13 +327,6 @@
 };
 
 &cbus {
-        clkc: clock-controller@4000 {
-                #clock-cells = <1>;
-                #reset-cells = <1>;
-                compatible = "amlogic,meson8-clkc";
-                reg = <0x8000 0x4>, <0x4000 0x400>;
-        };
-
         reset: reset-controller@4404 {
                 compatible = "amlogic,meson8b-reset";
                 reg = <0x4404 0x9c>;
@@ -390,6 +449,11 @@
         compatible = "amlogic,meson8-efuse";
         clocks = <&clkc CLKID_EFUSE>;
         clock-names = "core";
+
+        temperature_calib: calib@1f4 {
+                /* only the upper two bytes are relevant */
+                reg = <0x1f4 0x4>;
+        };
 };
 
 &ethmac {
@@ -402,6 +466,14 @@
         status = "okay";
 };
 
+&hhi {
+        clkc: clock-controller {
+                compatible = "amlogic,meson8-clkc";
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+        };
+};
+
 &hwrng {
         compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
         clocks = <&clkc CLKID_RNG0>;
@@ -469,6 +541,9 @@
         clocks = <&clkc CLKID_XTAL>,
                 <&clkc CLKID_SAR_ADC>;
         clock-names = "clkin", "core";
+        amlogic,hhi-sysctrl = <&hhi>;
+        nvmem-cells = <&temperature_calib>;
+        nvmem-cell-names = "temperature_calib";
 };
 
 &sdio {
diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts
index 0872f6e3abf5..3ca9638fad09 100644
--- a/arch/arm/boot/dts/meson8b-ec100.dts
+++ b/arch/arm/boot/dts/meson8b-ec100.dts
@@ -23,6 +23,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x40000000 0x40000000>;
         };
 
@@ -64,6 +65,11 @@
                 timeout-ms = <20000>;
         };
 
+        iio-hwmon {
+                compatible = "iio-hwmon";
+                io-channels = <&saradc 8>;
+        };
+
         leds {
                 compatible = "gpio-leds";
 
@@ -83,6 +89,9 @@
         };
 
         usb_vbus: regulator-usb-vbus {
+                /*
+                 * Silergy SY6288CCAC-GP 2A Power Distribution Switch.
+                 */
                 compatible = "regulator-fixed";
 
                 regulator-name = "USB_VBUS";
@@ -90,11 +99,20 @@
                 regulator-min-microvolt = <5000000>;
                 regulator-max-microvolt = <5000000>;
 
+                vin-supply = <&vcc_5v>;
+
+                /*
+                 * signal name from the schematics: USB_PWR_EN
+                 */
                 gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
                 enable-active-high;
         };
 
         vcc_5v: regulator-vcc5v {
+                /*
+                 * supplied by the main power input which called PWR_5V_STB
+                 * in the schematics
+                 */
                 compatible = "regulator-fixed";
 
                 regulator-name = "VCC5V";
@@ -102,6 +120,9 @@
                 regulator-min-microvolt = <5000000>;
                 regulator-max-microvolt = <5000000>;
 
+                /*
+                 * signal name from the schematics: 3V3_5V_EN
+                 */
                 gpio = <&gpio GPIODV_29 GPIO_ACTIVE_LOW>;
 
                 regulator-boot-on;
@@ -109,12 +130,18 @@
         };
 
         vcck: regulator-vcck {
+                /*
+                 * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz
+                 * Synchronous Step Down Regulator.
+                 */
                 compatible = "pwm-regulator";
 
                 regulator-name = "VCCK";
                 regulator-min-microvolt = <860000>;
                 regulator-max-microvolt = <1140000>;
 
+                vin-supply = <&vcc_5v>;
+
                 pwms = <&pwm_cd 0 1148 0>;
                 pwm-dutycycle-range = <100 0>;
 
@@ -123,19 +150,66 @@
         };
 
         vcc_1v8: regulator-vcc1v8 {
+                /*
+                 * ABLIC S-1339D18-M5001-GP
+                 */
                 compatible = "regulator-fixed";
 
                 regulator-name = "VCC1V8";
                 regulator-min-microvolt = <1800000>;
                 regulator-max-microvolt = <1800000>;
+
+                vin-supply = <&vcc_3v3>;
         };
 
         vcc_3v3: regulator-vcc3v3 {
+                /*
+                 * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz
+                 * Synchronous Step Down Regulator. Also called
+                 * VDDIO_AO3.3V in the schematics.
+                 */
                 compatible = "regulator-fixed";
 
                 regulator-name = "VCC3V3";
                 regulator-min-microvolt = <3300000>;
                 regulator-max-microvolt = <3300000>;
+
+                vin-supply = <&vcc_5v>;
+        };
+
+        vcc_ddr3: regulator-vcc-ddr3 {
+                /*
+                 * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz
+                 * Synchronous Step Down Regulator. Also called
+                 * DDR3_1.5V in the schematics.
+                 */
+                compatible = "regulator-fixed";
+
+                regulator-name = "VCC_DDR3_1V5";
+                regulator-min-microvolt = <1500000>;
+                regulator-max-microvolt = <1500000>;
+
+                vin-supply = <&vcc_5v>;
+
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        vcc_rtc: regulator-vcc-rtc {
+                /*
+                 * Global Mixed-mode Technology Inc. G918T12U-GP
+                 */
+                compatible = "regulator-fixed";
+
+                regulator-name = "VCC_RTC";
+                regulator-min-microvolt = <900000>;
+                regulator-max-microvolt = <900000>;
+
+                /*
+                 * When the board is powered then the input is VCC3V3,
+                 * otherwise power is taken from the coin cell battery.
+                 */
+                vin-supply = <&vcc_3v3>;
         };
 };
 
@@ -164,6 +238,10 @@
                 eth_phy0: ethernet-phy@0 {
                         /* IC Plus IP101A/G (0x02430c54) */
                         reg = <0>;
+                        icplus,select-interrupt;
+                        interrupt-parent = <&gpio_intc>;
+                        /* GPIOH_3 */
+                        interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
                 };
         };
 };
@@ -205,13 +283,62 @@
                 cap-sd-highspeed;
                 disable-wp;
 
-                cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
-                cd-inverted;
+                cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
 
                 vmmc-supply = <&vcc_3v3>;
         };
 };
 
+&gpio_ao {
+        gpio-line-names = "Linux_TX", "Linux_RX",
+                          "SLP_S5_N", "USB2_OC_FLAG#",
+                          "HUB_RST", "USB_PWR_EN",
+                          "I2S_IN", "SLP_S1_N",
+                          "TCK", "TMS", "TDI", "TDO",
+                          "HDMI_CEC", "5640_IRQ",
+                          "MUTE", "S805_TEST#";
+};
+
+&gpio {
+        gpio-line-names = /* Bank GPIOX */
+                          "WIFI_SD_D0", "WIFI_SD_D1", "WIFI_SD_D2",
+                          "WIFI_SD_D3", "BTPCM_DOUT", "BTPCM_DIN",
+                          "BTPCM_SYNC", "BTPCM_CLK", "WIFI_SD_CLK",
+                          "WIFI_SD_CMD", "WIFI_32K", "WIFI_PWREN",
+                          "UART_B_TX", "UART_B_RX", "UART_B_CTS_N",
+                          "UART_B_RTS_N", "BT_EN", "WIFI_WAKE_HOST",
+                          /* Bank GPIOY */
+                          "", "", "", "", "", "", "", "", "", "",
+                          "", "",
+                          /* Bank GPIODV */
+                          "VCCK_PWM_C", "I2C_SDA_A", "I2C_SCL_A",
+                          "I2C_SDA_B", "I2C_SCL_B", "VDDEE_PWM_D",
+                          "VDDEE_PWM 3V3_5V_EN",
+                          /* Bank GPIOH */
+                          "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL",
+                          "RMII_IRQ", "RMII_RST#", "RMII_TXD1",
+                          "RMII_TXD0", "AV_select_1", "AV_select_2",
+                          "MCU_Control_S",
+                          /* Bank CARD */
+                          "SD_D1_B", "SD_D0_B", "SD_CLK_8726MX",
+                          "SD_CMD_8726MX", "SD_D3_B", "SD_D2_B",
+                          "CARD_EN_DET (CARD_DET)",
+                          /* Bank BOOT */
+                          "NAND_D0 (EMMC)", "NAND_D1 (EMMC)",
+                          "NAND_D2 (EMMC)", "NAND_D3 (EMMC)",
+                          "NAND_D4 (EMMC)", "NAND_D5 (EMMC)",
+                          "NAND_D6 (EMMC)", "NAND_D7 (EMMC)",
+                          "NAND_CS1 (EMMC)", "NAND_CS2 iNAND_RS1 (EMMC)",
+                          "NAND_nR/B iNAND_CMD (EMMC)", "NAND_ALE (EMMC)",
+                          "NAND_CLE (EMMC)", "nRE_S1 NAND_nRE (EMMC)",
+                          "nWE_S1 NAND_nWE (EMMC)",  "", "", "SPI_CS",
+                          /* Bank DIF */
+                          "RMII_RXD1", "RMII_RXD0", "RMII_CRS_DV",
+                          "RMII_50M_IN", "GPIODIF_4", "GPIODIF_5",
+                          "RMII_TXEN", "CPUETH_25MOUT", "RMII_MDC",
+                          "RMII_MDIO";
+};
+
 &pwm_cd {
         status = "okay";
         pinctrl-0 = <&pwm_c1_pins>;
diff --git a/arch/arm/boot/dts/meson8b-mxq.dts b/arch/arm/boot/dts/meson8b-mxq.dts
index 5c9b76af8d42..08ddd7fb0bf8 100644
--- a/arch/arm/boot/dts/meson8b-mxq.dts
+++ b/arch/arm/boot/dts/meson8b-mxq.dts
@@ -60,6 +60,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x40000000 0x40000000>;
         };
 };
diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts
index 58669abda259..3b0e0f8fbc23 100644
--- a/arch/arm/boot/dts/meson8b-odroidc1.dts
+++ b/arch/arm/boot/dts/meson8b-odroidc1.dts
@@ -62,6 +62,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x40000000 0x40000000>;
         };
 
@@ -118,6 +119,11 @@
                           1800000 1>;
         };
 
+        iio-hwmon {
+                compatible = "iio-hwmon";
+                io-channels = <&saradc 8>;
+        };
+
         vcc_1v8: regulator-vcc-1v8 {
                 /*
                  * RICHTEK RT9179 configured for a fixed output voltage of
@@ -221,7 +227,6 @@
                 /* Realtek RTL8211F (0x001cc916) */
                 eth_phy: ethernet-phy@0 {
                         reg = <0>;
-                        eee-broken-1000t;
                         interrupt-parent = <&gpio_intc>;
                         /* GPIOH_3 */
                         interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
@@ -273,8 +278,7 @@
                 cap-sd-highspeed;
                 disable-wp;
 
-                cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
-                cd-inverted;
+                cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
 
                 vmmc-supply = <&tflash_vdd>;
                 vqmmc-supply = <&tf_io>;
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 22d775460767..fe84a8c3ce81 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -158,6 +158,32 @@
                 };
         };
 
+        gpu_opp_table: gpu-opp-table {
+                compatible = "operating-points-v2";
+
+                opp-255000000 {
+                        opp-hz = /bits/ 64 <255000000>;
+                        opp-microvolt = <1150000>;
+                };
+                opp-364300000 {
+                        opp-hz = /bits/ 64 <364300000>;
+                        opp-microvolt = <1150000>;
+                };
+                opp-425000000 {
+                        opp-hz = /bits/ 64 <425000000>;
+                        opp-microvolt = <1150000>;
+                };
+                opp-510000000 {
+                        opp-hz = /bits/ 64 <510000000>;
+                        opp-microvolt = <1150000>;
+                };
+                opp-637500000 {
+                        opp-hz = /bits/ 64 <637500000>;
+                        opp-microvolt = <1150000>;
+                        turbo-mode;
+                };
+        };
+
         pmu {
                 compatible = "arm,cortex-a5-pmu";
                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
@@ -178,6 +204,34 @@
                         no-map;
                 };
         };
+
+        apb: bus@d0000000 {
+                compatible = "simple-bus";
+                reg = <0xd0000000 0x200000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x0 0xd0000000 0x200000>;
+
+                mali: gpu@c0000 {
+                        compatible = "amlogic,meson8b-mali", "arm,mali-450";
+                        reg = <0xc0000 0x40000>;
+                        interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "gp", "gpmmu", "pp", "pmu",
+                                          "pp0", "ppmmu0", "pp1", "ppmmu1";
+                        resets = <&reset RESET_MALI>;
+                        clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
+                        clock-names = "bus", "core";
+                        operating-points-v2 = <&gpu_opp_table>;
+                        switch-delay = <0xffff>;
+                };
+        };
 }; /* end of / */
 
 &aobus {
@@ -222,13 +276,6 @@
 };
 
 &cbus {
-        clkc: clock-controller@4000 {
-                #clock-cells = <1>;
-                #reset-cells = <1>;
-                compatible = "amlogic,meson8b-clkc";
-                reg = <0x8000 0x4>, <0x4000 0x400>;
-        };
-
         reset: reset-controller@4404 {
                 compatible = "amlogic,meson8b-reset";
                 reg = <0x4404 0x9c>;
@@ -270,9 +317,7 @@
                                 groups = "eth_tx_clk",
                                          "eth_tx_en",
                                          "eth_txd1_0",
-                                         "eth_txd1_1",
                                          "eth_txd0_0",
-                                         "eth_txd0_1",
                                          "eth_rx_clk",
                                          "eth_rx_dv",
                                          "eth_rxd1",
@@ -281,7 +326,9 @@
                                          "eth_mdc",
                                          "eth_ref_clk",
                                          "eth_txd2",
-                                         "eth_txd3";
+                                         "eth_txd3",
+                                         "eth_rxd3",
+                                         "eth_rxd2";
                                 function = "ethernet";
                                 bias-disable;
                         };
@@ -360,6 +407,11 @@
         compatible = "amlogic,meson8b-efuse";
         clocks = <&clkc CLKID_EFUSE>;
         clock-names = "core";
+
+        temperature_calib: calib@1f4 {
+                /* only the upper two bytes are relevant */
+                reg = <0x1f4 0x4>;
+        };
 };
 
 &ethmac {
@@ -383,6 +435,14 @@
         status = "okay";
 };
 
+&hhi {
+        clkc: clock-controller {
+                compatible = "amlogic,meson8-clkc";
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+        };
+};
+
 &hwrng {
         compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
         clocks = <&clkc CLKID_RNG0>;
@@ -450,6 +510,9 @@
         clocks = <&clkc CLKID_XTAL>,
                 <&clkc CLKID_SAR_ADC>;
         clock-names = "clkin", "core";
+        amlogic,hhi-sysctrl = <&hhi>;
+        nvmem-cells = <&temperature_calib>;
+        nvmem-cell-names = "temperature_calib";
 };
 
 &sdio {
diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
index f5853610b20b..29d830ae4bf4 100644
--- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
+++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
@@ -28,6 +28,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x40000000 0x80000000>;
         };
 
@@ -44,6 +45,11 @@
                 };
         };
 
+        iio-hwmon {
+                compatible = "iio-hwmon";
+                io-channels = <&saradc 8>;
+        };
+
         vcc_3v3: regulator-vcc3v3 {
                 compatible = "regulator-fixed";
                 regulator-name = "VCC3V3";
@@ -206,8 +212,7 @@
                 cap-sd-highspeed;
                 disable-wp;
 
-                cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
-                cd-inverted;
+                cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
 
                 vmmc-supply = <&vcc_3v3>;
         };
diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi
index d1a28c2adac5..bb87b251e16d 100644
--- a/arch/arm/boot/dts/meson8m2.dtsi
+++ b/arch/arm/boot/dts/meson8m2.dtsi
@@ -50,6 +50,10 @@
         };
 };
 
+&saradc {
+        compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc";
+};
+
 &wdt {
         compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt";
 };
diff --git a/arch/arm/boot/dts/milbeaut-m10v-evb.dts b/arch/arm/boot/dts/milbeaut-m10v-evb.dts
new file mode 100644
index 000000000000..614f60c6b0a2
--- /dev/null
+++ b/arch/arm/boot/dts/milbeaut-m10v-evb.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Socionext Milbeaut M10V Evaluation Board */
+/dts-v1/;
+#include "milbeaut-m10v.dtsi"
+
+/ {
+        model = "Socionext M10V EVB";
+        compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a";
+
+        aliases {
+                serial0 = &uart1;
+        };
+
+        chosen {
+                bootargs = "rootwait earlycon";
+                stdout-path = "serial0:115200n8";
+        };
+
+        clocks {
+                uclk40xi: uclk40xi {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <40000000>;
+                };
+        };
+
+        memory@40000000 {
+                device_type = "memory";
+                reg = <0x40000000  0x80000000>;
+        };
+
+};
diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/milbeaut-m10v.dtsi
new file mode 100644
index 000000000000..aa7c6caeb750
--- /dev/null
+++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+        compatible = "socionext,sc2000a";
+        interrupt-parent = <&gic>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                enable-method = "socionext,milbeaut-m10v-smp";
+                cpu@f00 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0xf00>;
+                };
+                cpu@f01 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0xf01>;
+                };
+                cpu@f02 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0xf02>;
+                };
+                cpu@f03 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0xf03>;
+                };
+        };
+
+        timer { /* The Generic Timer */
+                compatible = "arm,armv7-timer";
+                interrupts = <GIC_PPI 13
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                        <GIC_PPI 14
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                        <GIC_PPI 11
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                        <GIC_PPI 10
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+                clock-frequency = <40000000>;
+                always-on;
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                interrupt-parent = <&gic>;
+
+                gic: interrupt-controller@1d000000 {
+                        compatible = "arm,cortex-a7-gic";
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        reg = <0x1d001000 0x1000>,
+                              <0x1d002000 0x1000>; /* CPU I/f base and size */
+                };
+
+                timer@1e000050 { /* 32-bit Reload Timers */
+                        compatible = "socionext,milbeaut-timer";
+                        reg = <0x1e000050 0x20>;
+                        interrupts = <0 91 4>;
+                };
+
+                uart1: serial@1e700010 { /* PE4, PE5 */
+                        /* Enable this as ttyUSI0 */
+                        compatible = "socionext,milbeaut-usio-uart";
+                        reg = <0x1e700010 0x10>;
+                        interrupts = <0 141 0x4>, <0 149 0x4>;
+                        interrupt-names = "rx", "tx";
+                };
+
+        };
+
+        sram@0 {
+                compatible = "mmio-sram";
+                reg = <0x0 0x10000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0x0 0x10000>;
+                smp-sram@f100 {
+                        compatible = "socionext,milbeaut-smp-sram";
+                        reg = <0xf100 0x20>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/mmp2-brownstone.dts
index 350208c5e1ed..3da038ba5733 100644
--- a/arch/arm/boot/dts/mmp2-brownstone.dts
+++ b/arch/arm/boot/dts/mmp2-brownstone.dts
@@ -19,6 +19,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
index ee03e0846740..f02fb97f515c 100644
--- a/arch/arm/boot/dts/mmp2.dtsi
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -7,10 +7,12 @@
  *  publishhed by the Free Software Foundation.
  */
 
-#include "skeleton.dtsi"
 #include <dt-bindings/clock/marvell,mmp2.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
         aliases {
                 serial0 = &uart1;
                 serial1 = &uart2;
diff --git a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi
index ddc7a7bb33c0..f57acf8f66b9 100644
--- a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi
+++ b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi
@@ -105,7 +105,7 @@
                         interrupts-extended = <
                                 &cpcap 15 0 &cpcap 14 0 &cpcap 28 0 &cpcap 19 0
                                 &cpcap 18 0 &cpcap 17 0 &cpcap 16 0 &cpcap 49 0
-                                &cpcap 48 1
+                                &cpcap 48 0
                         >;
                         interrupt-names =
                                 "id_ground", "id_float", "se0conn", "vbusvld",
diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxart.dtsi
index da7b3237bfe9..cbf17656bcc7 100644
--- a/arch/arm/boot/dts/moxart.dtsi
+++ b/arch/arm/boot/dts/moxart.dtsi
@@ -5,10 +5,11 @@
  * Licensed under GPLv2 or later.
  */
 
-/include/ "skeleton.dtsi"
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "moxa,moxart";
         model = "MOXART";
         interrupt-parent = <&intc>;
diff --git a/arch/arm/boot/dts/mps2.dtsi b/arch/arm/boot/dts/mps2.dtsi
index 23467390558d..96fb5a5cf4d3 100644
--- a/arch/arm/boot/dts/mps2.dtsi
+++ b/arch/arm/boot/dts/mps2.dtsi
@@ -171,7 +171,7 @@
                         uart0: serial@4000 {
                                 compatible = "arm,mps2-uart";
                                 reg = <0x4000 0x1000>;
-                                interrupts = <0 1 12>;
+                                interrupts = <0>, <1>, <12>;
                                 clocks = <&sysclk>;
                                 status = "disabled";
                         };
@@ -179,7 +179,7 @@
                         uart1: serial@5000 {
                                 compatible = "arm,mps2-uart";
                                 reg = <0x5000 0x1000>;
-                                interrupts = <2 3 12>;
+                                interrupts = <2>, <3>, <12>;
                                 clocks = <&sysclk>;
                                 status = "disabled";
                         };
@@ -187,7 +187,7 @@
                         uart2: serial@6000 {
                                 compatible = "arm,mps2-uart";
                                 reg = <0x6000 0x1000>;
-                                interrupts = <4 5 12>;
+                                interrupts = <4>, <5>, <12>;
                                 clocks = <&sysclk>;
                                 status = "disabled";
                         };
diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
index be0edb3dae6c..88f8fd22302a 100644
--- a/arch/arm/boot/dts/mt2701-evb.dts
+++ b/arch/arm/boot/dts/mt2701-evb.dts
@@ -13,6 +13,7 @@
         compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
 
         memory {
+                device_type = "memory";
                 reg = <0 0x80000000 0 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 180377e56ef4..51e1305c6471 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -12,10 +12,11 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/memory/mt2701-larb-port.h>
 #include <dt-bindings/reset/mt2701-resets.h>
-#include "skeleton64.dtsi"
 #include "mt2701-pinfunc.h"
 
 / {
+        #address-cells = <2>;
+        #size-cells = <2>;
         compatible = "mediatek,mt2701";
         interrupt-parent = <&cirq>;
 
diff --git a/arch/arm/boot/dts/mt6580-evbp1.dts b/arch/arm/boot/dts/mt6580-evbp1.dts
index ca137897ed60..755a0774a8ee 100644
--- a/arch/arm/boot/dts/mt6580-evbp1.dts
+++ b/arch/arm/boot/dts/mt6580-evbp1.dts
@@ -22,6 +22,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x80000000 0x20000000>;
         };
 };
diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi
index 2bdc5ed12fca..9e17698c0609 100644
--- a/arch/arm/boot/dts/mt6580.dtsi
+++ b/arch/arm/boot/dts/mt6580.dtsi
@@ -7,7 +7,6 @@
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
 
 / {
         compatible = "mediatek,mt6580";
diff --git a/arch/arm/boot/dts/mt6589-aquaris5.dts b/arch/arm/boot/dts/mt6589-aquaris5.dts
index 7bbaa1279a26..1e7079a3b449 100644
--- a/arch/arm/boot/dts/mt6589-aquaris5.dts
+++ b/arch/arm/boot/dts/mt6589-aquaris5.dts
@@ -18,6 +18,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x80000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi
index 28df8495686a..f3ccb70c0779 100644
--- a/arch/arm/boot/dts/mt6589.dtsi
+++ b/arch/arm/boot/dts/mt6589.dtsi
@@ -7,9 +7,10 @@
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "mediatek,mt6589";
         interrupt-parent = <&sysirq>;
 
diff --git a/arch/arm/boot/dts/mt6592-evb.dts b/arch/arm/boot/dts/mt6592-evb.dts
index 02849f6548e3..5e00c1cca2d1 100644
--- a/arch/arm/boot/dts/mt6592-evb.dts
+++ b/arch/arm/boot/dts/mt6592-evb.dts
@@ -13,7 +13,7 @@
         compatible = "mediatek,mt6592-evb", "mediatek,mt6592";
 
         memory {
+                device_type = "memory";
                 reg = <0x80000000 0x40000000>;
         };
 };
-
diff --git a/arch/arm/boot/dts/mt6592.dtsi b/arch/arm/boot/dts/mt6592.dtsi
index 8696ac891d60..3716f8db951c 100644
--- a/arch/arm/boot/dts/mt6592.dtsi
+++ b/arch/arm/boot/dts/mt6592.dtsi
@@ -7,9 +7,10 @@
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "mediatek,mt6592";
         interrupt-parent = <&sysirq>;
 
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index 98f115966391..a79f0b6c3429 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -187,17 +187,26 @@
                         cooling-maps {
                                 map0 {
                                         trip = <&cpu_passive>;
-                                        cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                        cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                         <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                         <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                         <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                 };
 
                                 map1 {
                                         trip = <&cpu_active>;
-                                        cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                        cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                         <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                         <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                         <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                 };
 
                                 map2 {
                                         trip = <&cpu_hot>;
-                                        cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                        cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                         <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                         <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                         <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                 };
                         };
                 };
diff --git a/arch/arm/boot/dts/mt8127-moose.dts b/arch/arm/boot/dts/mt8127-moose.dts
index 308829b2da86..560687af87dc 100644
--- a/arch/arm/boot/dts/mt8127-moose.dts
+++ b/arch/arm/boot/dts/mt8127-moose.dts
@@ -13,6 +13,7 @@
         compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
 
         memory {
+                device_type = "memory";
                 reg = <0 0x80000000 0 0x40000000>;
         };
 };
diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
index 3adfc6f7859c..aced173c2a52 100644
--- a/arch/arm/boot/dts/mt8127.dtsi
+++ b/arch/arm/boot/dts/mt8127.dtsi
@@ -7,9 +7,10 @@
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton64.dtsi"
 
 / {
+        #address-cells = <2>;
+        #size-cells = <2>;
         compatible = "mediatek,mt8127";
         interrupt-parent = <&sysirq>;
 
diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts b/arch/arm/boot/dts/mt8135-evbp1.dts
index 0ace7a40a60d..f6147fe62f41 100644
--- a/arch/arm/boot/dts/mt8135-evbp1.dts
+++ b/arch/arm/boot/dts/mt8135-evbp1.dts
@@ -13,6 +13,7 @@
         compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135";
 
         memory {
+                device_type = "memory";
                 reg = <0 0x80000000 0 0x40000000>;
         };
 };
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 688069dc1533..0e4e835026db 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -9,10 +9,11 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/mt8135-resets.h>
-#include "skeleton64.dtsi"
 #include "mt8135-pinfunc.h"
 
 / {
+        #address-cells = <2>;
+        #size-cells = <2>;
         compatible = "mediatek,mt8135";
         interrupt-parent = <&sysirq>;
 
diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi
index 1a5ae4cd107f..5a3c1f9d1832 100644
--- a/arch/arm/boot/dts/nspire.dtsi
+++ b/arch/arm/boot/dts/nspire.dtsi
@@ -9,9 +9,9 @@
  *
  */
 
-/include/ "skeleton.dtsi"
-
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         interrupt-parent = <&intc>;
 
         cpus {
diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi
index 4c1227d1e79b..17c89df6ce6b 100644
--- a/arch/arm/boot/dts/omap3-evm-common.dtsi
+++ b/arch/arm/boot/dts/omap3-evm-common.dtsi
@@ -122,6 +122,7 @@
 };
 
 &mmc2 {
+        interrupts-extended = <&intc 86 &omap3_pmx_core 0x12e>;
         vmmc-supply = <&wl12xx_vmmc>;
         non-removable;
         bus-width = <4>;
@@ -132,8 +133,10 @@
         wlcore: wlcore@2 {
                 compatible = "ti,wl1271";
                 reg = <2>;
-                interrupt-parent = <&gpio5>;
-                interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 149 */
+                /* gpio_149 with uart1_rts pad as wakeirq */
+                interrupts-extended = <&gpio5 21 IRQ_TYPE_EDGE_RISING>,
+                                      <&omap3_pmx_core 0x14e>;
+                interrupt-names = "irq", "wakeup";
                 ref-clock-frequency = <38400000>;
         };
 };
diff --git a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi
index ce7f42f9448c..b4109f48ec18 100644
--- a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi
+++ b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi
@@ -86,6 +86,10 @@
                         OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
                         OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
                         OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
+                        OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1)       /* sdmmc2_dat4.sdmmc2_dir_dat0 */
+                        OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1)       /* sdmmc2_dat5.sdmmc2_dir_dat1 */
+                        OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1)       /* sdmmc2_dat6.sdmmc2_dir_cmd */
+                        OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1)        /* sdmmc2_dat7.sdmmc2_clkin */
                 >;
         };
 
@@ -127,9 +131,13 @@
                 >;
         };
 
+        /*
+         * Note that gpio_150 pulled high with internal pull to prevent wlcore
+         * reset on return from off mode in idle.
+         */
         wl12xx_gpio: pinmux_wl12xx_gpio {
                 pinctrl-single,pins = <
-                        OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4)               /* uart1_cts.gpio_150 */
+                        OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE7)         /* uart1_cts.gpio_150 */
                         OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4)                /* uart1_rts.gpio_149 */
                 >;
         };
diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi
index e53d32691308..04f2b53d4d3d 100644
--- a/arch/arm/boot/dts/omap3-gta04.dtsi
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -32,6 +32,14 @@
                 display1 = &tv0;
         };
 
+        ldo_3v3: fixedregulator {
+                compatible = "regulator-fixed";
+                regulator-name = "ldo_3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
         /* fixed 26MHz oscillator */
         hfclk_26m: oscillator {
                 #clock-cells = <0>;
@@ -116,6 +124,7 @@
                         spi-cpol;
                         spi-cpha;
 
+                        backlight= <&backlight>;
                         label = "lcd";
                         port {
                                 lcd_in: endpoint {
@@ -125,7 +134,7 @@
                 };
         };
 
-        backlight {
+        backlight: backlight {
                 compatible = "pwm-backlight";
                 pwms = <&pwm11 0 12000000 0>;
                 pwm-names = "backlight";
@@ -224,6 +233,15 @@
         };
 };
 
+&omap3_pmx_wkup {
+        gpio1_pins: pinmux_gpio1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */
+                        OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_clkout.gpio_10 */
+                >;
+        };
+};
+
 &omap3_pmx_core {
         pinctrl-names = "default";
         pinctrl-0 = <
@@ -312,6 +330,12 @@
                 >;
        };
 
+        gps_pins: pinmux_gps_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* gpio145 */
+                >;
+        };
+
         hdq_pins: hdq_pins {
                 pinctrl-single,pins = <
                         OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.hdq */
@@ -636,6 +660,11 @@
         status = "disabled";
 };
 
+&gpio1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&gpio1_pins>;
+};
+
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart1_pins>;
@@ -644,6 +673,14 @@
 &uart2 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart2_pins>;
+        gnss: gnss {
+                compatible = "wi2wi,w2sg0004";
+                pinctrl-names = "default";
+                pinctrl-0 = <&gps_pins>;
+                sirf,onoff-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+                lna-supply = <&vsim>;
+                vcc-supply = <&ldo_3v3>;
+        };
 };
 
 &uart3 {
@@ -714,11 +751,7 @@
 
         vdda-supply = <&vdac>;
 
-        #address-cells = <1>;
-        #size-cells = <0>;
-
         port {
-                reg = <0>;
                 venc_out: endpoint {
                         remote-endpoint = <&opa_in>;
                         ti,channels = <1>;
diff --git a/arch/arm/boot/dts/omap3-gta04a5.dts b/arch/arm/boot/dts/omap3-gta04a5.dts
index bd232b1b24cb..223b47ac596e 100644
--- a/arch/arm/boot/dts/omap3-gta04a5.dts
+++ b/arch/arm/boot/dts/omap3-gta04a5.dts
@@ -82,7 +82,7 @@
 
 /*
  * for WL183x module see
- * http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt
+ * Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt
  */
 
 &wifi_pwrseq {
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 182a53991c90..826920e6b878 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -814,7 +814,7 @@
         /* For debugging, it is often good idea to remove this GPIO.
            It means you can remove back cover (to reboot by removing
            battery) and still use the MMC card. */
-        cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */
+        cd-gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* 160 */
 };
 
 /* most boards use vaux3, only some old versions use vmmc2 instead */
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi
index 0d9b85317529..e142e6c70a59 100644
--- a/arch/arm/boot/dts/omap3-n950-n9.dtsi
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -370,6 +370,19 @@
                 compatible = "ti,omap2-onenand";
                 reg = <0 0 0x20000>;    /* CS0, offset 0, IO size 128K */
 
+                /*
+                 * These timings are based on CONFIG_OMAP_GPMC_DEBUG=y reported
+                 * bootloader set values when booted with v4.19 using both N950
+                 * and N9 devices (OneNAND Manufacturer: Samsung):
+                 *
+                 *   gpmc cs0 before gpmc_cs_program_settings:
+                 *   cs0 GPMC_CS_CONFIG1: 0xfd001202
+                 *   cs0 GPMC_CS_CONFIG2: 0x00181800
+                 *   cs0 GPMC_CS_CONFIG3: 0x00030300
+                 *   cs0 GPMC_CS_CONFIG4: 0x18001804
+                 *   cs0 GPMC_CS_CONFIG5: 0x03171d1d
+                 *   cs0 GPMC_CS_CONFIG6: 0x97080000
+                 */
                 gpmc,sync-read;
                 gpmc,sync-write;
                 gpmc,burst-length = <16>;
@@ -379,26 +392,27 @@
                 gpmc,device-width = <2>;
                 gpmc,mux-add-data = <2>;
                 gpmc,cs-on-ns = <0>;
-                gpmc,cs-rd-off-ns = <87>;
-                gpmc,cs-wr-off-ns = <87>;
+                gpmc,cs-rd-off-ns = <122>;
+                gpmc,cs-wr-off-ns = <122>;
                 gpmc,adv-on-ns = <0>;
-                gpmc,adv-rd-off-ns = <10>;
-                gpmc,adv-wr-off-ns = <10>;
-                gpmc,oe-on-ns = <15>;
-                gpmc,oe-off-ns = <87>;
+                gpmc,adv-rd-off-ns = <15>;
+                gpmc,adv-wr-off-ns = <15>;
+                gpmc,oe-on-ns = <20>;
+                gpmc,oe-off-ns = <122>;
                 gpmc,we-on-ns = <0>;
-                gpmc,we-off-ns = <87>;
-                gpmc,rd-cycle-ns = <112>;
-                gpmc,wr-cycle-ns = <112>;
-                gpmc,access-ns = <81>;
+                gpmc,we-off-ns = <122>;
+                gpmc,rd-cycle-ns = <148>;
+                gpmc,wr-cycle-ns = <148>;
+                gpmc,access-ns = <117>;
                 gpmc,page-burst-access-ns = <15>;
                 gpmc,bus-turnaround-ns = <0>;
                 gpmc,cycle2cycle-delay-ns = <0>;
                 gpmc,wait-monitoring-ns = <0>;
-                gpmc,clk-activation-ns = <5>;
-                gpmc,wr-data-mux-bus-ns = <30>;
-                gpmc,wr-access-ns = <81>;
-                gpmc,sync-clk-ps = <15000>;
+                gpmc,clk-activation-ns = <10>;
+                gpmc,wr-data-mux-bus-ns = <40>;
+                gpmc,wr-access-ns = <117>;
+
+                gpmc,sync-clk-ps = <15000>; /* TBC; Where this value came? */
 
                 /*
                  * MTD partition table corresponding to Nokia's MeeGo 1.2
diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts
index 04758a2a87f0..e21ec929f096 100644
--- a/arch/arm/boot/dts/omap4-droid4-xt894.dts
+++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts
@@ -359,20 +359,24 @@
 
 &mmc3 {
         vmmc-supply = <&wl12xx_vmmc>;
+        /* uart2_tx.sdmmc3_dat1 pad as wakeirq */
         interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
                                &omap4_pmx_core 0xde>;
-
+        interrupt-names = "irq", "wakeup";
         non-removable;
         bus-width = <4>;
         cap-power-off-card;
+        keep-power-in-suspend;
 
         #address-cells = <1>;
         #size-cells = <0>;
         wlcore: wlcore@2 {
                 compatible = "ti,wl1285", "ti,wl1283";
                 reg = <2>;
-                interrupt-parent = <&gpio4>;
-                interrupts = <4 IRQ_TYPE_EDGE_RISING>; /* gpio100 */
+                /* gpio_100 with gpmc_wait2 pad as wakeirq */
+                interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>,
+                                      <&omap4_pmx_core 0x4e>;
+                interrupt-names = "irq", "wakeup";
                 ref-clock-frequency = <26000000>;
                 tcxo-clock-frequency = <26000000>;
         };
@@ -644,6 +648,17 @@
         };
 };
 
+/* Configure pwm clock source for timers 8 & 9 */
+&timer8 {
+        assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
+        assigned-clock-parents = <&sys_clkin_ck>;
+};
+
+&timer9 {
+        assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;
+        assigned-clock-parents = <&sys_clkin_ck>;
+};
+
 /*
  * As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for
  * uart1 wakeirq.
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 27895c1604b9..926f018823a4 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -485,8 +485,10 @@
         wlcore: wlcore@2 {
                 compatible = "ti,wl1271";
                 reg = <2>;
-                interrupt-parent = <&gpio2>;
-                interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 53 */
+                /* gpio_53 with gpmc_ncs3 pad as wakeup */
+                interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_RISING>,
+                                      <&omap4_pmx_core 0x3a>;
+                interrupt-names = "irq", "wakeup";
                 ref-clock-frequency = <38400000>;
         };
 };
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 9dc7ec7655cb..c88817bdcc56 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -26,6 +26,9 @@
         };
 
         vdd_eth: fixedregulator-vdd-eth {
+                pinctrl-names = "default";
+                pinctrl-0 = <&enet_enable_gpio>;
+
                 compatible = "regulator-fixed";
                 regulator-name = "VDD_ETH";
                 regulator-min-microvolt = <3300000>;
@@ -352,6 +355,29 @@
                         OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc5_dat3.sdmmc5_dat3 */
                 >;
         };
+
+        /* gpio_48 for ENET_ENABLE */
+        enet_enable_gpio: pinmux_enet_enable_gpio {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLDOWN | MUX_MODE3)     /* gpmc_a24.gpio_48 */
+                >;
+        };
+
+        ks8851_pins: pinmux_ks8851_pins {
+                pinctrl-single,pins = <
+                        /* ENET_INT */
+                        OMAP4_IOPAD(0x054, PIN_INPUT_PULLUP | MUX_MODE3)        /* gpmc_ad10.gpio_34 */
+                        /*
+                         * Misterious pin which makes the ethernet working
+                         * The legacy board file requested this pin on boot
+                         * (ETH_KS8851_QUART) and set it to high, similarly to
+                         * the ENET_ENABLE pin.
+                         * We could use gpio-hog to keep it high, but let's use
+                         * it as a reset GPIO for ks8851.
+                         */
+                        OMAP4_IOPAD(0x13a, PIN_OUTPUT_PULLUP | MUX_MODE3)       /* mcspi1_cs1.gpio_138 */
+                >;
+        };
 };
 
 &i2c1 {
@@ -452,12 +478,16 @@
         pinctrl-0 = <&mcspi1_pins>;
 
         eth@0 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&ks8851_pins>;
+
                 compatible = "ks8851";
                 spi-max-frequency = <24000000>;
                 reg = <0>;
                 interrupt-parent = <&gpio2>;
                 interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34 */
                 vdd-supply = <&vdd_eth>;
+                reset-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
         };
 };
 
diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi
index bc853ebeda22..61a06f6add3c 100644
--- a/arch/arm/boot/dts/omap5-board-common.dtsi
+++ b/arch/arm/boot/dts/omap5-board-common.dtsi
@@ -317,7 +317,8 @@
 
         palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins {
                 pinctrl-single,pins = <
-                        OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1 */
+                        /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */
+                        OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0)
                 >;
         };
 
@@ -385,7 +386,8 @@
 
         palmas: palmas@48 {
                 compatible = "ti,palmas";
-                interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
+                /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
                 reg = <0x48>;
                 interrupt-controller;
                 #interrupt-cells = <2>;
@@ -651,7 +653,8 @@
                 pinctrl-names = "default";
                 pinctrl-0 = <&twl6040_pins>;
 
-                interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */
+                /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
+                interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_LOW>;
 
                 /* audpwron gpio defined in the board specific dts */
 
diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts
index 5e21fb430a65..e78d3718f145 100644
--- a/arch/arm/boot/dts/omap5-cm-t54.dts
+++ b/arch/arm/boot/dts/omap5-cm-t54.dts
@@ -181,6 +181,13 @@
                         OMAP5_IOPAD(0x0042, PIN_INPUT_PULLDOWN | MUX_MODE6)  /* llib_wakereqin.gpio1_wk15 */
                 >;
         };
+
+        palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins {
+                pinctrl-single,pins = <
+                        /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */
+                        OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0)
+                >;
+        };
 };
 
 &omap5_pmx_core {
@@ -414,8 +421,11 @@
 
         palmas: palmas@48 {
                 compatible = "ti,palmas";
-                interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
                 reg = <0x48>;
+                pinctrl-0 = <&palmas_sys_nirq_pins>;
+                pinctrl-names = "default";
+                /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
                 interrupt-controller;
                 #interrupt-cells = <2>;
                 ti,system-power-controller;
diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi
index 9c7e309d9c2c..0960348002ad 100644
--- a/arch/arm/boot/dts/omap5-l4.dtsi
+++ b/arch/arm/boot/dts/omap5-l4.dtsi
@@ -1046,8 +1046,6 @@
                                         <SYSC_IDLE_SMART>,
                                         <SYSC_IDLE_SMART_WKUP>;
                         ti,syss-mask = <1>;
-                        ti,no-reset-on-init;
-                        ti,no-idle-on-init;
                         /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
                         clocks = <&l4per_clkctrl OMAP5_UART3_CLKCTRL 0>;
                         clock-names = "fck";
diff --git a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
index 8c2449da6f00..422958d13d42 100644
--- a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
@@ -19,6 +19,7 @@
         compatible = "lacie,d2-network", "marvell,orion5x-88f5182", "marvell,orion5x";
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x4000000>; /* 64 MB */
         };
 
diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
index b545d0f228a5..0043e0040153 100644
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -25,6 +25,7 @@
         compatible = "lacie,ethernet-disk-mini-v2", "marvell,orion5x-88f5182", "marvell,orion5x";
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x4000000>; /* 64 MB */
         };
 
diff --git a/arch/arm/boot/dts/orion5x-lswsgl.dts b/arch/arm/boot/dts/orion5x-lswsgl.dts
index 0d97ded66257..2fbc17d6dfa4 100644
--- a/arch/arm/boot/dts/orion5x-lswsgl.dts
+++ b/arch/arm/boot/dts/orion5x-lswsgl.dts
@@ -55,6 +55,7 @@
         compatible = "buffalo,lswsgl", "marvell,orion5x-88f5182", "marvell,orion5x";
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x8000000>; /* 128 MB */
         };
 
diff --git a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts
index 0324cb54939d..0ca6208a267d 100644
--- a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts
+++ b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts
@@ -19,6 +19,7 @@
         compatible = "maxtor,shared-storage-2", "marvell,orion5x-88f5182", "marvell,orion5x";
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x4000000>; /* 64 MB */
         };
 
diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
index 9f6ae4e1de06..ea081afa469d 100644
--- a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
+++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts
@@ -21,6 +21,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x2000000>; /* 32 MB */
         };
 
diff --git a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
index d1817af53e0b..487324f7c54e 100644
--- a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
+++ b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
@@ -16,6 +16,7 @@
         compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x";
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x4000000>; /* 64 MB */
         };
 
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index fbccfbbab223..61e631b3fd8b 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -6,11 +6,11 @@
  * warranty of any kind, whether express or implied.
  */
 
-#include "skeleton.dtsi"
-
 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Marvell Orion5x SoC";
         compatible = "marvell,orion5x";
         interrupt-parent = <&intc>;
diff --git a/arch/arm/boot/dts/ox810se.dtsi b/arch/arm/boot/dts/ox810se.dtsi
index c2b48a1838eb..3a26650de4eb 100644
--- a/arch/arm/boot/dts/ox810se.dtsi
+++ b/arch/arm/boot/dts/ox810se.dtsi
@@ -6,11 +6,12 @@
  * Licensed under GPLv2 or later
  */
 
-/include/ "skeleton.dtsi"
 #include <dt-bindings/clock/oxsemi,ox810se.h>
 #include <dt-bindings/reset/oxsemi,ox810se.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "oxsemi,ox810se";
 
         cpus {
@@ -25,6 +26,7 @@
         };
 
         memory {
+                device_type = "memory";
                 /* Max 256MB @ 0x48000000 */
                 reg = <0x48000000 0x10000000>;
         };
diff --git a/arch/arm/boot/dts/ox820.dtsi b/arch/arm/boot/dts/ox820.dtsi
index 085bbd33eadc..f3239586f38d 100644
--- a/arch/arm/boot/dts/ox820.dtsi
+++ b/arch/arm/boot/dts/ox820.dtsi
@@ -6,12 +6,13 @@
  * Licensed under GPLv2 or later
  */
 
-/include/ "skeleton.dtsi"
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/oxsemi,ox820.h>
 #include <dt-bindings/reset/oxsemi,ox820.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "oxsemi,ox820";
 
         cpus {
@@ -35,6 +36,7 @@
         };
 
         memory {
+                device_type = "memory";
                 /* Max 512MB @ 0x60000000 */
                 reg = <0x60000000 0x20000000>;
         };
diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
index a1266cf8776c..291a28f34762 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
@@ -10,7 +10,6 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
-/include/ "skeleton.dtsi"
 / {
         model = "Picochip picoXcell PC3X2";
         compatible = "picochip,pc3x2";
diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
index d78cd207eca1..bf9a39ea76b0 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
@@ -10,7 +10,6 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
-/include/ "skeleton.dtsi"
 / {
         model = "Picochip picoXcell PC3X3";
         compatible = "picochip,pc3x3";
diff --git a/arch/arm/boot/dts/prima2-evb.dts b/arch/arm/boot/dts/prima2-evb.dts
index 57286b4e7b87..55594b3bbc99 100644
--- a/arch/arm/boot/dts/prima2-evb.dts
+++ b/arch/arm/boot/dts/prima2-evb.dts
@@ -15,6 +15,7 @@
         compatible = "sirf,prima2", "sirf,prima2-cb";
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 1ca1a9aa953f..54d4f8850e22 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -6,7 +6,6 @@
  * Licensed under GPLv2 or later.
  */
 
-/include/ "skeleton.dtsi"
 / {
         compatible = "sirf,prima2";
         #address-cells = <1>;
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
index b899e25cbb1b..7137f3550183 100644
--- a/arch/arm/boot/dts/pxa168.dtsi
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -7,10 +7,12 @@
  *  publishhed by the Free Software Foundation.
  */
 
-#include "skeleton.dtsi"
 #include <dt-bindings/clock/marvell,pxa168.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
         aliases {
                 serial0 = &uart1;
                 serial1 = &uart2;
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
index e83879d97aea..bd6bf6d9300f 100644
--- a/arch/arm/boot/dts/pxa2xx.dtsi
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -6,7 +6,6 @@
  * Licensed under GPLv2 or later.
  */
 
-#include "skeleton.dtsi"
 #include "dt-bindings/clock/pxa-clock.h"
 
 #define PMGROUP(pin) #pin
@@ -29,6 +28,8 @@
         }
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Marvell PXA2xx family SoC";
         compatible = "marvell,pxa2xx";
         interrupt-parent = <&pxairq>;
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
index 0868f6729be1..c88553a8ee29 100644
--- a/arch/arm/boot/dts/pxa910.dtsi
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -7,10 +7,12 @@
  *  publishhed by the Free Software Foundation.
  */
 
-#include "skeleton.dtsi"
 #include <dt-bindings/clock/marvell,pxa910.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
         aliases {
                 serial0 = &uart1;
                 serial1 = &uart2;
diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
index 497bb065eb9d..4e6c50d45cb2 100644
--- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
@@ -93,9 +93,8 @@
                 vdd-supply = <&pm8058_l14>; // 2.85V
                 aset-gpios = <&pm8058_gpio 35 GPIO_ACTIVE_LOW>;
                 capella,aset-resistance-ohms = <100000>;
-                /* GPIO34 has interrupt 225 on the PM8058 */
                 /* Trig on both edges - getting close or far away */
-                interrupts-extended = <&pm8058 225 IRQ_TYPE_EDGE_BOTH>;
+                interrupts-extended = <&pm8058_gpio 34 IRQ_TYPE_EDGE_BOTH>;
                 /* MPP05 analog input to the XOADC */
                 io-channels = <&xoadc 0x00 0x05>;
                 io-channel-names = "aout";
@@ -515,9 +514,8 @@
                                 ak8975@c {
                                         compatible = "asahi-kasei,ak8975";
                                         reg = <0x0c>;
-                                        /* FIXME: GPIO33 has interrupt 224 on the PM8058 */
-                                        interrupt-parent = <&pm8058>;
-                                        interrupts = <224 IRQ_TYPE_EDGE_RISING>;
+                                        interrupt-parent = <&pm8058_gpio>;
+                                        interrupts = <33 IRQ_TYPE_EDGE_RISING>;
                                         pinctrl-names = "default";
                                         pinctrl-0 = <&dragon_ak8975_gpios>;
                                         vid-supply = <&pm8058_lvs0>; // 1.8V
@@ -526,9 +524,8 @@
                                 bmp085@77 {
                                         compatible = "bosch,bmp085";
                                         reg = <0x77>;
-                                        /* FIXME: GPIO16 has interrupt 207 on the PM8058 */
-                                        interrupt-parent = <&pm8058>;
-                                        interrupts = <207 IRQ_TYPE_EDGE_RISING>;
+                                        interrupt-parent = <&pm8058_gpio>;
+                                        interrupts = <16 IRQ_TYPE_EDGE_RISING>;
                                         reset-gpios = <&tlmm 86 GPIO_ACTIVE_LOW>;
                                         pinctrl-names = "default";
                                         pinctrl-0 = <&dragon_bmp085_gpios>;
@@ -539,12 +536,11 @@
                                         compatible = "invensense,mpu3050";
                                         reg = <0x68>;
                                         /*
-                                         * GPIO17 has interrupt 208 on the
-                                         * PM8058, it is pulled high by a 10k
+                                         * GPIO17 is pulled high by a 10k
                                          * resistor to VLOGIC so needs to be
                                          * active low/falling edge.
                                          */
-                                        interrupts-extended = <&pm8058 208 IRQ_TYPE_EDGE_FALLING>;
+                                        interrupts-extended = <&pm8058_gpio 17 IRQ_TYPE_EDGE_FALLING>;
                                         pinctrl-names = "default";
                                         pinctrl-0 = <&dragon_mpu3050_gpios>;
                                         vlogic-supply = <&pm8058_lvs0>; // 1.8V
@@ -589,11 +585,10 @@
                                 compatible = "smsc,lan9221", "smsc,lan9115";
                                 reg = <2 0x0 0x100>;
                                 /*
-                                 * GPIO7 has interrupt 198 on the PM8058
                                  * The second interrupt is the PME interrupt
                                  * for network wakeup, connected to the TLMM.
                                  */
-                                interrupts-extended = <&pm8058 198 IRQ_TYPE_EDGE_FALLING>,
+                                interrupts-extended = <&pm8058_gpio 7 IRQ_TYPE_EDGE_FALLING>,
                                                     <&tlmm 29 IRQ_TYPE_EDGE_RISING>;
                                 reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
                                 vdd33a-supply = <&dragon_veth>;
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 48c3cf427610..bd6907db615b 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -1,7 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /dts-v1/;
 
-#include "skeleton.dtsi"
 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
@@ -10,6 +9,8 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Qualcomm APQ8064";
         compatible = "qcom,apq8064";
         interrupt-parent = <&intc>;
@@ -94,6 +95,11 @@
                 };
         };
 
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x0>;
+        };
+
         thermal-zones {
                 cpu-thermal0 {
                         polling-delay-passive = <250>;
@@ -705,50 +711,8 @@
                                         compatible = "qcom,pm8921-gpio",
                                                      "qcom,ssbi-gpio";
                                         reg = <0x150>;
-                                        interrupts = <192 IRQ_TYPE_NONE>,
-                                                     <193 IRQ_TYPE_NONE>,
-                                                     <194 IRQ_TYPE_NONE>,
-                                                     <195 IRQ_TYPE_NONE>,
-                                                     <196 IRQ_TYPE_NONE>,
-                                                     <197 IRQ_TYPE_NONE>,
-                                                     <198 IRQ_TYPE_NONE>,
-                                                     <199 IRQ_TYPE_NONE>,
-                                                     <200 IRQ_TYPE_NONE>,
-                                                     <201 IRQ_TYPE_NONE>,
-                                                     <202 IRQ_TYPE_NONE>,
-                                                     <203 IRQ_TYPE_NONE>,
-                                                     <204 IRQ_TYPE_NONE>,
-                                                     <205 IRQ_TYPE_NONE>,
-                                                     <206 IRQ_TYPE_NONE>,
-                                                     <207 IRQ_TYPE_NONE>,
-                                                     <208 IRQ_TYPE_NONE>,
-                                                     <209 IRQ_TYPE_NONE>,
-                                                     <210 IRQ_TYPE_NONE>,
-                                                     <211 IRQ_TYPE_NONE>,
-                                                     <212 IRQ_TYPE_NONE>,
-                                                     <213 IRQ_TYPE_NONE>,
-                                                     <214 IRQ_TYPE_NONE>,
-                                                     <215 IRQ_TYPE_NONE>,
-                                                     <216 IRQ_TYPE_NONE>,
-                                                     <217 IRQ_TYPE_NONE>,
-                                                     <218 IRQ_TYPE_NONE>,
-                                                     <219 IRQ_TYPE_NONE>,
-                                                     <220 IRQ_TYPE_NONE>,
-                                                     <221 IRQ_TYPE_NONE>,
-                                                     <222 IRQ_TYPE_NONE>,
-                                                     <223 IRQ_TYPE_NONE>,
-                                                     <224 IRQ_TYPE_NONE>,
-                                                     <225 IRQ_TYPE_NONE>,
-                                                     <226 IRQ_TYPE_NONE>,
-                                                     <227 IRQ_TYPE_NONE>,
-                                                     <228 IRQ_TYPE_NONE>,
-                                                     <229 IRQ_TYPE_NONE>,
-                                                     <230 IRQ_TYPE_NONE>,
-                                                     <231 IRQ_TYPE_NONE>,
-                                                     <232 IRQ_TYPE_NONE>,
-                                                     <233 IRQ_TYPE_NONE>,
-                                                     <234 IRQ_TYPE_NONE>,
-                                                     <235 IRQ_TYPE_NONE>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
                                         gpio-controller;
                                         #gpio-cells = <2>;
 
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 899f28533ed7..0a0fb147ebb9 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -1,12 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0
 /dts-v1/;
 
-#include "skeleton.dtsi"
-
 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Qualcomm APQ 8084";
         compatible = "qcom,apq8084";
         interrupt-parent = <&intc>;
@@ -87,6 +87,11 @@
                 };
         };
 
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x0>;
+        };
+
         firmware {
                 scm {
                         compatible = "qcom,scm";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 2d56008d8d6b..9e75f97770ce 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -13,12 +13,14 @@
 
 /dts-v1/;
 
-#include "skeleton.dtsi"
 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
         model = "Qualcomm Technologies, Inc. IPQ4019";
         compatible = "qcom,ipq4019";
         interrupt-parent = <&intc>;
@@ -133,6 +135,11 @@
                 };
         };
 
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x0>;
+        };
+
         pmu {
                 compatible = "arm,cortex-a7-pmu";
                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
@@ -396,7 +403,7 @@
                         ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
                                   0x82000000 0 0x40300000 0x40300000 0 0x400000>;
 
-                        interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
+                        interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "msi";
                         #interrupt-cells = <1>;
                         interrupt-map-mask = <0 0 0 0x7>;
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index f793cd1ad6d0..16c0da97932c 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -1,7 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /dts-v1/;
 
-#include "skeleton.dtsi"
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
@@ -11,6 +10,8 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Qualcomm IPQ8064";
         compatible = "qcom,ipq8064";
         interrupt-parent = <&intc>;
@@ -45,6 +46,11 @@
                 };
         };
 
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x0>;
+        };
+
         cpu-pmu {
                 compatible = "qcom,krait-pmu";
                 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi
index 7869898e392d..26b034bd19d2 100644
--- a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi
+++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi
@@ -50,6 +50,7 @@
         compatible = "swir,wp8548", "qcom,mdm9615";
 
         memory {
+                device_type = "memory";
                 reg = <0x48000000 0x7F00000>;
         };
 };
diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi
index c852b69229c9..02afc6a42005 100644
--- a/arch/arm/boot/dts/qcom-mdm9615.dtsi
+++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi
@@ -45,8 +45,6 @@
 
 /dts-v1/;
 
-/include/ "skeleton.dtsi"
-
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
@@ -54,6 +52,8 @@
 #include <dt-bindings/soc/qcom,gsbi.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Qualcomm MDM9615";
         compatible = "qcom,mdm9615";
         interrupt-parent = <&intc>;
@@ -323,13 +323,8 @@
 
                                 pmicgpio: gpio@150 {
                                         compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio";
-                                        interrupt-parent = <&pmicintc>;
-                                        interrupts = <24 IRQ_TYPE_NONE>,
-                                                     <25 IRQ_TYPE_NONE>,
-                                                     <26 IRQ_TYPE_NONE>,
-                                                     <27 IRQ_TYPE_NONE>,
-                                                     <28 IRQ_TYPE_NONE>,
-                                                     <29 IRQ_TYPE_NONE>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
                                         gpio-controller;
                                         #gpio-cells = <2>;
                                 };
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 70698941f64c..65a994f0e09b 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -1,14 +1,14 @@
 // SPDX-License-Identifier: GPL-2.0
 /dts-v1/;
 
-/include/ "skeleton.dtsi"
-
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
 #include <dt-bindings/soc/qcom,gsbi.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Qualcomm MSM8660";
         compatible = "qcom,msm8660";
         interrupt-parent = <&intc>;
@@ -39,6 +39,11 @@
                 };
         };
 
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x0>;
+        };
+
         cpu-pmu {
                 compatible = "qcom,scorpion-mp-pmu";
                 interrupts = <1 9 0x304>;
@@ -133,6 +138,7 @@
                         #address-cells = <1>;
                         #size-cells = <1>;
                         ranges;
+                        status = "disabled";
 
                         syscon-tcsr = <&tcsr>;
 
@@ -140,7 +146,7 @@
                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                 reg = <0x16540000 0x1000>,
                                       <0x16500000 0x1000>;
-                                interrupts = <GIC_SPI 156 IRQ_TYPE_NONE>;
+                                interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
                                 clock-names = "core", "iface";
                                 status = "disabled";
@@ -149,7 +155,7 @@
                         gsbi6_i2c: i2c@16580000 {
                                 compatible = "qcom,i2c-qup-v1.1.1";
                                 reg = <0x16580000 0x1000>;
-                                interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
+                                interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
                                 clock-names = "core", "iface";
                                 #address-cells = <1>;
@@ -167,6 +173,7 @@
                         #address-cells = <1>;
                         #size-cells = <1>;
                         ranges;
+                        status = "disabled";
 
                         syscon-tcsr = <&tcsr>;
 
@@ -174,7 +181,7 @@
                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                 reg = <0x16640000 0x1000>,
                                       <0x16600000 0x1000>;
-                                interrupts = <GIC_SPI 158 IRQ_TYPE_NONE>;
+                                interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
                                 clock-names = "core", "iface";
                                 status = "disabled";
@@ -183,7 +190,7 @@
                         gsbi7_i2c: i2c@16680000 {
                                 compatible = "qcom,i2c-qup-v1.1.1";
                                 reg = <0x16680000 0x1000>;
-                                interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
+                                interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
                                 clock-names = "core", "iface";
                                 #address-cells = <1>;
@@ -207,7 +214,7 @@
                         gsbi8_i2c: i2c@19880000 {
                                 compatible = "qcom,i2c-qup-v1.1.1";
                                 reg = <0x19880000 0x1000>;
-                                interrupts = <GIC_SPI 161 IRQ_TYPE_NONE>;
+                                interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
                                 clock-names = "core", "iface";
                                 #address-cells = <1>;
@@ -232,7 +239,7 @@
                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                 reg = <0x19c40000 0x1000>,
                                       <0x19c00000 0x1000>;
-                                interrupts = <0 195 IRQ_TYPE_NONE>;
+                                interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
                                 clock-names = "core", "iface";
                                 status = "disabled";
@@ -241,7 +248,7 @@
                         gsbi12_i2c: i2c@19c80000 {
                                 compatible = "qcom,i2c-qup-v1.1.1";
                                 reg = <0x19c80000 0x1000>;
-                                interrupts = <0 196 IRQ_TYPE_NONE>;
+                                interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
                                 clock-names = "core", "iface";
                                 #address-cells = <1>;
@@ -285,51 +292,8 @@
                                         compatible = "qcom,pm8058-gpio",
                                                      "qcom,ssbi-gpio";
                                         reg = <0x150>;
-                                        interrupt-parent = <&pm8058>;
-                                        interrupts = <192 IRQ_TYPE_NONE>,
-                                                     <193 IRQ_TYPE_NONE>,
-                                                     <194 IRQ_TYPE_NONE>,
-                                                     <195 IRQ_TYPE_NONE>,
-                                                     <196 IRQ_TYPE_NONE>,
-                                                     <197 IRQ_TYPE_NONE>,
-                                                     <198 IRQ_TYPE_NONE>,
-                                                     <199 IRQ_TYPE_NONE>,
-                                                     <200 IRQ_TYPE_NONE>,
-                                                     <201 IRQ_TYPE_NONE>,
-                                                     <202 IRQ_TYPE_NONE>,
-                                                     <203 IRQ_TYPE_NONE>,
-                                                     <204 IRQ_TYPE_NONE>,
-                                                     <205 IRQ_TYPE_NONE>,
-                                                     <206 IRQ_TYPE_NONE>,
-                                                     <207 IRQ_TYPE_NONE>,
-                                                     <208 IRQ_TYPE_NONE>,
-                                                     <209 IRQ_TYPE_NONE>,
-                                                     <210 IRQ_TYPE_NONE>,
-                                                     <211 IRQ_TYPE_NONE>,
-                                                     <212 IRQ_TYPE_NONE>,
-                                                     <213 IRQ_TYPE_NONE>,
-                                                     <214 IRQ_TYPE_NONE>,
-                                                     <215 IRQ_TYPE_NONE>,
-                                                     <216 IRQ_TYPE_NONE>,
-                                                     <217 IRQ_TYPE_NONE>,
-                                                     <218 IRQ_TYPE_NONE>,
-                                                     <219 IRQ_TYPE_NONE>,
-                                                     <220 IRQ_TYPE_NONE>,
-                                                     <221 IRQ_TYPE_NONE>,
-                                                     <222 IRQ_TYPE_NONE>,
-                                                     <223 IRQ_TYPE_NONE>,
-                                                     <224 IRQ_TYPE_NONE>,
-                                                     <225 IRQ_TYPE_NONE>,
-                                                     <226 IRQ_TYPE_NONE>,
-                                                     <227 IRQ_TYPE_NONE>,
-                                                     <228 IRQ_TYPE_NONE>,
-                                                     <229 IRQ_TYPE_NONE>,
-                                                     <230 IRQ_TYPE_NONE>,
-                                                     <231 IRQ_TYPE_NONE>,
-                                                     <232 IRQ_TYPE_NONE>,
-                                                     <233 IRQ_TYPE_NONE>,
-                                                     <234 IRQ_TYPE_NONE>,
-                                                     <235 IRQ_TYPE_NONE>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
                                         gpio-controller;
                                         #gpio-cells = <2>;
 
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi
index 1733d8f40ab1..f2aeaccdc1ad 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -1,14 +1,14 @@
 // SPDX-License-Identifier: GPL-2.0
 /dts-v1/;
 
-/include/ "skeleton.dtsi"
-
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
 #include <dt-bindings/mfd/qcom-rpm.h>
 #include <dt-bindings/soc/qcom,gsbi.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Qualcomm MSM8960";
         compatible = "qcom,msm8960";
         interrupt-parent = <&intc>;
@@ -44,6 +44,11 @@
                 };
         };
 
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x0>;
+        };
+
         cpu-pmu {
                 compatible = "qcom,krait-pmu";
                 interrupts = <1 10 0x304>;
diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
index 51444c53fc72..b3b04736a159 100644
--- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
@@ -220,6 +220,20 @@
                         };
                 };
         };
+
+        vreg_wlan: wlan-regulator {
+                compatible = "regulator-fixed";
+
+                regulator-name = "wl-reg";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+
+                gpio = <&msmgpio 26 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&wlan_regulator_pin>;
+        };
 };
 
 &soc {
@@ -242,6 +256,30 @@
                         };
                 };
 
+                sdhc2_pin_a: sdhc2-pin-active {
+                        clk {
+                                pins = "sdc2_clk";
+                                drive-strength = <6>;
+                                bias-disable;
+                        };
+
+                        cmd-data {
+                                pins = "sdc2_cmd", "sdc2_data";
+                                drive-strength = <6>;
+                                bias-pull-up;
+                        };
+                };
+
+                i2c1_pins: i2c1 {
+                        mux {
+                                pins = "gpio2", "gpio3";
+                                function = "blsp_i2c1";
+
+                                drive-strength = <2>;
+                                bias-disable;
+                        };
+                };
+
                 i2c3_pins: i2c3 {
                         mux {
                                 pins = "gpio10", "gpio11";
@@ -283,6 +321,32 @@
                 pinctrl-0 = <&sdhc1_pin_a>;
         };
 
+        sdhci@f98a4900 {
+                status = "ok";
+
+                max-frequency = <100000000>;
+                bus-width = <4>;
+                non-removable;
+                vmmc-supply = <&vreg_wlan>;
+                vqmmc-supply = <&pm8941_s3>;
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&sdhc2_pin_a>;
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                bcrmf@1 {
+                        compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac";
+                        reg = <1>;
+
+                        brcm,drive-strength = <10>;
+
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&wlan_sleep_clk_pin>;
+                };
+        };
+
         gpio-keys {
                 compatible = "gpio-keys";
                 input-name = "gpio-keys";
@@ -342,6 +406,24 @@
                 };
         };
 
+        i2c@f9923000 {
+                status = "ok";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c1_pins>;
+                clock-frequency = <100000>;
+                qcom,src-freq = <50000000>;
+
+                charger: bq24192@6b {
+                        compatible = "ti,bq24192";
+                        reg = <0x6b>;
+                        interrupts-extended = <&spmi_bus 0 0xd5 0 IRQ_TYPE_EDGE_FALLING>;
+
+                        omit-battery-class;
+
+                        usb_otg_vbus: usb-otg-vbus { };
+                };
+        };
+
         i2c@f9925000 {
                 status = "ok";
                 pinctrl-names = "default";
@@ -359,6 +441,31 @@
                         amstaos,proximity-diodes = <0>;
                 };
         };
+
+        usb@f9a55000 {
+                status = "ok";
+
+                phys = <&usb_hs1_phy>;
+                phy-select = <&tcsr 0xb000 0>;
+
+                extcon = <&charger>, <&usb_id>;
+                vbus-supply = <&usb_otg_vbus>;
+
+                hnp-disable;
+                srp-disable;
+                adp-disable;
+
+                ulpi {
+                        phy@a {
+                                status = "ok";
+
+                                v1p8-supply = <&pm8941_l6>;
+                                v3p3-supply = <&pm8941_l24>;
+
+                                qcom,init-seq = /bits/ 8 <0x1 0x64>;
+                        };
+                };
+        };
 };
 
 &spmi_bus {
@@ -371,6 +478,29 @@
                                 bias-pull-up;
                                 power-source = <PM8941_GPIO_S3>;
                         };
+
+                        wlan_sleep_clk_pin: wl-sleep-clk {
+                                pins = "gpio16";
+                                function = "func2";
+
+                                output-high;
+                                power-source = <PM8941_GPIO_S3>;
+                        };
+
+                        wlan_regulator_pin: wl-reg-active {
+                                pins = "gpio17";
+                                function = "normal";
+
+                                bias-disable;
+                                power-source = <PM8941_GPIO_S3>;
+                        };
+
+                        otg {
+                                gpio-hog;
+                                gpios = <35 GPIO_ACTIVE_HIGH>;
+                                output-high;
+                                line-name = "otg-gpio";
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index ca266a5f021d..45b5c8ef0374 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -6,9 +6,10 @@
 #include <dt-bindings/clock/qcom,rpmcc.h>
 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
 #include <dt-bindings/gpio/gpio.h>
-#include "skeleton.dtsi"
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Qualcomm MSM8974";
         compatible = "qcom,msm8974";
         interrupt-parent = <&intc>;
@@ -130,6 +131,11 @@
                 };
         };
 
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x0>;
+        };
+
         thermal-zones {
                 cpu-thermal0 {
                         polling-delay-passive = <250>;
@@ -706,6 +712,17 @@
                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
                 };
 
+                i2c@f9923000 {
+                        status = "disabled";
+                        compatible = "qcom,i2c-qup-v2.1.1";
+                        reg = <0xf9923000 0x1000>;
+                        interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+                        clock-names = "core", "iface";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
                 i2c@f9924000 {
                         status = "disabled";
                         compatible = "qcom,i2c-qup-v2.1.1";
diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi
index 2515c5c217ac..f198480c8ef4 100644
--- a/arch/arm/boot/dts/qcom-pm8941.dtsi
+++ b/arch/arm/boot/dts/qcom-pm8941.dtsi
@@ -63,43 +63,10 @@
                         compatible = "qcom,pm8941-gpio", "qcom,spmi-gpio";
                         reg = <0xc000>;
                         gpio-controller;
+                        gpio-ranges = <&pm8941_gpios 0 0 36>;
                         #gpio-cells = <2>;
-                        interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
-                                     <0 0xc1 0 IRQ_TYPE_NONE>,
-                                     <0 0xc2 0 IRQ_TYPE_NONE>,
-                                     <0 0xc3 0 IRQ_TYPE_NONE>,
-                                     <0 0xc4 0 IRQ_TYPE_NONE>,
-                                     <0 0xc5 0 IRQ_TYPE_NONE>,
-                                     <0 0xc6 0 IRQ_TYPE_NONE>,
-                                     <0 0xc7 0 IRQ_TYPE_NONE>,
-                                     <0 0xc8 0 IRQ_TYPE_NONE>,
-                                     <0 0xc9 0 IRQ_TYPE_NONE>,
-                                     <0 0xca 0 IRQ_TYPE_NONE>,
-                                     <0 0xcb 0 IRQ_TYPE_NONE>,
-                                     <0 0xcc 0 IRQ_TYPE_NONE>,
-                                     <0 0xcd 0 IRQ_TYPE_NONE>,
-                                     <0 0xce 0 IRQ_TYPE_NONE>,
-                                     <0 0xcf 0 IRQ_TYPE_NONE>,
-                                     <0 0xd0 0 IRQ_TYPE_NONE>,
-                                     <0 0xd1 0 IRQ_TYPE_NONE>,
-                                     <0 0xd2 0 IRQ_TYPE_NONE>,
-                                     <0 0xd3 0 IRQ_TYPE_NONE>,
-                                     <0 0xd4 0 IRQ_TYPE_NONE>,
-                                     <0 0xd5 0 IRQ_TYPE_NONE>,
-                                     <0 0xd6 0 IRQ_TYPE_NONE>,
-                                     <0 0xd7 0 IRQ_TYPE_NONE>,
-                                     <0 0xd8 0 IRQ_TYPE_NONE>,
-                                     <0 0xd9 0 IRQ_TYPE_NONE>,
-                                     <0 0xda 0 IRQ_TYPE_NONE>,
-                                     <0 0xdb 0 IRQ_TYPE_NONE>,
-                                     <0 0xdc 0 IRQ_TYPE_NONE>,
-                                     <0 0xdd 0 IRQ_TYPE_NONE>,
-                                     <0 0xde 0 IRQ_TYPE_NONE>,
-                                     <0 0xdf 0 IRQ_TYPE_NONE>,
-                                     <0 0xe0 0 IRQ_TYPE_NONE>,
-                                     <0 0xe1 0 IRQ_TYPE_NONE>,
-                                     <0 0xe2 0 IRQ_TYPE_NONE>,
-                                     <0 0xe3 0 IRQ_TYPE_NONE>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
 
                         boost_bypass_n_pin: boost-bypass {
                                 pins = "gpio21";
diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom-pma8084.dtsi
index aac7e73b6872..8f5ea7add20f 100644
--- a/arch/arm/boot/dts/qcom-pma8084.dtsi
+++ b/arch/arm/boot/dts/qcom-pma8084.dtsi
@@ -32,28 +32,8 @@
                         reg = <0xc000>;
                         gpio-controller;
                         #gpio-cells = <2>;
-                        interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
-                                     <0 0xc1 0 IRQ_TYPE_NONE>,
-                                     <0 0xc2 0 IRQ_TYPE_NONE>,
-                                     <0 0xc3 0 IRQ_TYPE_NONE>,
-                                     <0 0xc4 0 IRQ_TYPE_NONE>,
-                                     <0 0xc5 0 IRQ_TYPE_NONE>,
-                                     <0 0xc6 0 IRQ_TYPE_NONE>,
-                                     <0 0xc7 0 IRQ_TYPE_NONE>,
-                                     <0 0xc8 0 IRQ_TYPE_NONE>,
-                                     <0 0xc9 0 IRQ_TYPE_NONE>,
-                                     <0 0xca 0 IRQ_TYPE_NONE>,
-                                     <0 0xcb 0 IRQ_TYPE_NONE>,
-                                     <0 0xcc 0 IRQ_TYPE_NONE>,
-                                     <0 0xcd 0 IRQ_TYPE_NONE>,
-                                     <0 0xce 0 IRQ_TYPE_NONE>,
-                                     <0 0xcf 0 IRQ_TYPE_NONE>,
-                                     <0 0xd0 0 IRQ_TYPE_NONE>,
-                                     <0 0xd1 0 IRQ_TYPE_NONE>,
-                                     <0 0xd2 0 IRQ_TYPE_NONE>,
-                                     <0 0xd3 0 IRQ_TYPE_NONE>,
-                                     <0 0xd4 0 IRQ_TYPE_NONE>,
-                                     <0 0xd5 0 IRQ_TYPE_NONE>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
                 };
 
                 pma8084_mpps: mpps@a000 {
diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
new file mode 100644
index 000000000000..991e09de1219
--- /dev/null
+++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the RZA2MEVB board
+ *
+ * Copyright (C) 2018 Renesas Electronics
+ *
+ */
+
+/dts-v1/;
+#include "r7s9210.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/r7s9210-pinctrl.h>
+
+/ {
+        model = "RZA2MEVB";
+        compatible = "renesas,rza2mevb", "renesas,r7s9210";
+
+        aliases {
+                serial0 = &scif4;
+        };
+
+        chosen {
+                bootargs = "ignore_loglevel";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@40000000 {
+                device_type = "memory";
+                reg = <0x40000000 0x00800000>;   /* HyperRAM */
+        };
+
+        lbsc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                red {
+                        gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>;
+                };
+                green {
+                        gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+
+/* EXTAL */
+&extal_clk {
+        clock-frequency = <24000000>;   /* 24MHz */
+};
+
+/* RTC_X1 */
+&rtc_x1_clk {
+        clock-frequency = <32768>;
+};
+
+&pinctrl {
+        /* Serial Console */
+        scif4_pins: serial4 {
+                pinmux = <RZA2_PINMUX(PORT9, 0, 4)>,    /* TxD4 */
+                         <RZA2_PINMUX(PORT9, 1, 4)>;    /* RxD4 */
+        };
+};
+
+/* High resolution System tick timers */
+&ostm0 {
+        status = "okay";
+};
+
+&ostm1 {
+        status = "okay";
+};
+
+/* Serial Console */
+&scif4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&scif4_pins>;
+
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi
new file mode 100644
index 000000000000..22baa96f5974
--- /dev/null
+++ b/arch/arm/boot/dts/r7s9210.dtsi
@@ -0,0 +1,218 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the R7S9210 SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corporation
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r7s9210-cpg-mssr.h>
+
+/ {
+        compatible = "renesas,r7s9210";
+        interrupt-parent = <&gic>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        /* External clocks */
+        extal_clk: extal {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                /* Value must be set by board */
+                clock-frequency = <0>;
+        };
+
+        rtc_x1_clk: rtc_x1 {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                /* If clk present, value (32678) must be set by board */
+                clock-frequency = <0>;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                        clock-frequency = <528000000>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        soc {
+                compatible = "simple-bus";
+                interrupt-parent = <&gic>;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                L2: cache-controller@1f003000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0x1f003000 0x1000>;
+                        interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+                        arm,early-bresp-disable;
+                        arm,full-line-zero-disable;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+
+                scif0: serial@e8007000 {
+                        compatible = "renesas,scif-r7s9210";
+                        reg = <0xe8007000 0x18>;
+                        interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "eri", "rxi", "txi",
+                                          "bri", "dri", "tei";
+                        clocks = <&cpg CPG_MOD 47>;
+                        clock-names = "fck";
+                        power-domains = <&cpg>;
+                        status = "disabled";
+                };
+
+                scif1: serial@e8007800 {
+                        compatible = "renesas,scif-r7s9210";
+                        reg = <0xe8007800 0x18>;
+                        interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "eri", "rxi", "txi",
+                                          "bri", "dri", "tei";
+                        clocks = <&cpg CPG_MOD 46>;
+                        clock-names = "fck";
+                        power-domains = <&cpg>;
+                        status = "disabled";
+                };
+
+                scif2: serial@e8008000 {
+                        compatible = "renesas,scif-r7s9210";
+                        reg = <0xe8008000 0x18>;
+                        interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "eri", "rxi", "txi",
+                                          "bri", "dri", "tei";
+                        clocks = <&cpg CPG_MOD 45>;
+                        clock-names = "fck";
+                        power-domains = <&cpg>;
+                        status = "disabled";
+                };
+
+                scif3: serial@e8008800 {
+                        compatible = "renesas,scif-r7s9210";
+                        reg = <0xe8008800 0x18>;
+                        interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "eri", "rxi", "txi",
+                                          "bri", "dri", "tei";
+                        clocks = <&cpg CPG_MOD 44>;
+                        clock-names = "fck";
+                        power-domains = <&cpg>;
+                        status = "disabled";
+                };
+
+                scif4: serial@e8009000 {
+                        compatible = "renesas,scif-r7s9210";
+                        reg = <0xe8009000 0x18>;
+                        interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "eri", "rxi", "txi",
+                                          "bri", "dri", "tei";
+                        clocks = <&cpg CPG_MOD 43>;
+                        clock-names = "fck";
+                        power-domains = <&cpg>;
+                        status = "disabled";
+                };
+
+                ostm0: timer@e803b000 {
+                        compatible = "renesas,r7s9210-ostm", "renesas,ostm";
+                        reg = <0xe803b000 0x30>;
+                        interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
+                        clocks = <&cpg CPG_MOD 36>;
+                        clock-names = "ostm0";
+                        power-domains = <&cpg>;
+                        status = "disabled";
+                };
+
+                ostm1: timer@e803c000 {
+                        compatible = "renesas,r7s9210-ostm", "renesas,ostm";
+                        reg = <0xe803c000 0x30>;
+                        interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
+                        clocks = <&cpg CPG_MOD 35>;
+                        clock-names = "ostm1";
+                        power-domains = <&cpg>;
+                        status = "disabled";
+                };
+
+                ostm2: timer@e803d000 {
+                        compatible = "renesas,r7s9210-ostm", "renesas,ostm";
+                        reg = <0xe803d000 0x30>;
+                        interrupts = <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>;
+                        clocks = <&cpg CPG_MOD 34>;
+                        clock-names = "ostm2";
+                        power-domains = <&cpg>;
+                        status = "disabled";
+                };
+
+                gic: interrupt-controller@e8221000 {
+                        compatible = "arm,gic-400";
+                        #interrupt-cells = <3>;
+                        #address-cells = <0>;
+                        interrupt-controller;
+                        reg = <0xe8221000 0x1000>,
+                              <0xe8222000 0x1000>;
+                };
+
+                cpg: clock-controller@fcfe0010 {
+                        compatible = "renesas,r7s9210-cpg-mssr";
+                        reg = <0xfcfe0010 0x455>;
+                        clocks = <&extal_clk>;
+                        clock-names = "extal";
+                        #clock-cells = <2>;
+                        #power-domain-cells = <0>;
+                };
+
+                wdt: watchdog@fcfe7000 {
+                        compatible = "renesas,r7s9210-wdt", "renesas,rza-wdt";
+                        reg = <0xfcfe7000 0x26>;
+                        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_CORE R7S9210_CLK_P0>;
+                };
+
+                bsid: chipid@fcfe8004 {
+                        compatible = "renesas,bsid";
+                        reg = <0xfcfe8004 4>;
+                };
+
+                pinctrl: pin-controller@fcffe000 {
+                        compatible = "renesas,r7s9210-pinctrl";
+                        reg = <0xfcffe000 0x1000>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-ranges = <&pinctrl 0 0 176>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 3cc33f7ff7fe..de981d629bdd 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -15,25 +15,6 @@
         #address-cells = <2>;
         #size-cells = <2>;
 
-        aliases {
-                i2c0 = &i2c0;
-                i2c1 = &i2c1;
-                i2c2 = &i2c2;
-                i2c3 = &i2c3;
-                i2c4 = &i2c4;
-                i2c5 = &i2c5;
-                i2c6 = &iic0;
-                i2c7 = &iic1;
-                i2c8 = &iic3;
-                spi0 = &qspi;
-                spi1 = &msiof0;
-                spi2 = &msiof1;
-                spi3 = &msiof2;
-                vin0 = &vin0;
-                vin1 = &vin1;
-                vin2 = &vin2;
-        };
-
         /*
          * The external audio clocks are configured as 0 Hz fixed frequency
          * clocks by default.
@@ -154,6 +135,16 @@
                 #size-cells = <2>;
                 ranges;
 
+                rwdt: watchdog@e6020000 {
+                        compatible = "renesas,r8a7743-wdt",
+                                     "renesas,rcar-gen2-wdt";
+                        reg = <0 0xe6020000 0 0x0c>;
+                        clocks = <&cpg CPG_MOD 402>;
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 402>;
+                        status = "disabled";
+                };
+
                 gpio0: gpio@e6050000 {
                         compatible = "renesas,gpio-r8a7743",
                                      "renesas,rcar-gen2-gpio";
@@ -310,16 +301,6 @@
                         reg = <0 0xe6160000 0 0x100>;
                 };
 
-                rwdt: watchdog@e6020000 {
-                        compatible = "renesas,r8a7743-wdt",
-                                     "renesas,rcar-gen2-wdt";
-                        reg = <0 0xe6020000 0 0x0c>;
-                        clocks = <&cpg CPG_MOD 402>;
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 402>;
-                        status = "disabled";
-                };
-
                 sysc: system-controller@e6180000 {
                         compatible = "renesas,r8a7743-sysc";
                         reg = <0 0xe6180000 0 0x200>;
@@ -564,9 +545,7 @@
                         /* doesn't need pinmux */
                         #address-cells = <1>;
                         #size-cells = <0>;
-                        compatible = "renesas,iic-r8a7743",
-                                     "renesas,rcar-gen2-iic",
-                                     "renesas,rmobile-iic";
+                        compatible = "renesas,iic-r8a7743";
                         reg = <0 0xe60b0000 0 0x425>;
                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 926>;
@@ -1681,15 +1660,12 @@
 
                 du: display@feb00000 {
                         compatible = "renesas,du-r8a7743";
-                        reg = <0 0xfeb00000 0 0x40000>,
-                              <0 0xfeb90000 0 0x1c>;
-                        reg-names = "du", "lvds.0";
+                        reg = <0 0xfeb00000 0 0x40000>;
                         interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 724>,
-                                 <&cpg CPG_MOD 723>,
-                                 <&cpg CPG_MOD 726>;
-                        clock-names = "du.0", "du.1", "lvds.0";
+                                 <&cpg CPG_MOD 723>;
+                        clock-names = "du.0", "du.1";
                         status = "disabled";
 
                         ports {
@@ -1704,6 +1680,33 @@
                                 port@1 {
                                         reg = <1>;
                                         du_out_lvds0: endpoint {
+                                                remote-endpoint = <&lvds0_in>;
+                                        };
+                                };
+                        };
+                };
+
+                lvds0: lvds@feb90000 {
+                        compatible = "renesas,r8a7743-lvds";
+                        reg = <0 0xfeb90000 0 0x1c>;
+                        clocks = <&cpg CPG_MOD 726>;
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 726>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        lvds0_in: endpoint {
+                                                remote-endpoint = <&du_out_lvds0>;
+                                        };
+                                };
+                                port@1 {
+                                        reg = <1>;
+                                        lvds0_out: endpoint {
                                         };
                                 };
                         };
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 04148d608fc4..fa74a262107b 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -998,6 +998,54 @@
                         status = "disabled";
                 };
 
+                msiof0: spi@e6e20000 {
+                        compatible = "renesas,msiof-r8a7744",
+                                     "renesas,rcar-gen2-msiof";
+                        reg = <0 0xe6e20000 0 0x0064>;
+                        interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 000>;
+                        dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+                               <&dmac1 0x51>, <&dmac1 0x52>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        resets = <&cpg 000>;
+                        status = "disabled";
+                };
+
+                msiof1: spi@e6e10000 {
+                        compatible = "renesas,msiof-r8a7744",
+                                     "renesas,rcar-gen2-msiof";
+                        reg = <0 0xe6e10000 0 0x0064>;
+                        interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 208>;
+                        dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+                               <&dmac1 0x55>, <&dmac1 0x56>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        resets = <&cpg 208>;
+                        status = "disabled";
+                };
+
+                msiof2: spi@e6e00000 {
+                        compatible = "renesas,msiof-r8a7744",
+                                     "renesas,rcar-gen2-msiof";
+                        reg = <0 0xe6e00000 0 0x0064>;
+                        interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 205>;
+                        dmas = <&dmac0 0x41>, <&dmac0 0x42>,
+                               <&dmac1 0x41>, <&dmac1 0x42>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        resets = <&cpg 205>;
+                        status = "disabled";
+                };
+
                 pwm0: pwm@e6e30000 {
                         compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
                         reg = <0 0xe6e30000 0 0x8>;
@@ -1068,54 +1116,6 @@
                         status = "disabled";
                 };
 
-                msiof0: spi@e6e20000 {
-                        compatible = "renesas,msiof-r8a7744",
-                                     "renesas,rcar-gen2-msiof";
-                        reg = <0 0xe6e20000 0 0x0064>;
-                        interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 000>;
-                        dmas = <&dmac0 0x51>, <&dmac0 0x52>,
-                               <&dmac1 0x51>, <&dmac1 0x52>;
-                        dma-names = "tx", "rx", "tx", "rx";
-                        power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        resets = <&cpg 000>;
-                        status = "disabled";
-                };
-
-                msiof1: spi@e6e10000 {
-                        compatible = "renesas,msiof-r8a7744",
-                                     "renesas,rcar-gen2-msiof";
-                        reg = <0 0xe6e10000 0 0x0064>;
-                        interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 208>;
-                        dmas = <&dmac0 0x55>, <&dmac0 0x56>,
-                               <&dmac1 0x55>, <&dmac1 0x56>;
-                        dma-names = "tx", "rx", "tx", "rx";
-                        power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        resets = <&cpg 208>;
-                        status = "disabled";
-                };
-
-                msiof2: spi@e6e00000 {
-                        compatible = "renesas,msiof-r8a7744",
-                                     "renesas,rcar-gen2-msiof";
-                        reg = <0 0xe6e00000 0 0x0064>;
-                        interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 205>;
-                        dmas = <&dmac0 0x41>, <&dmac0 0x42>,
-                               <&dmac1 0x41>, <&dmac1 0x42>;
-                        dma-names = "tx", "rx", "tx", "rx";
-                        power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        resets = <&cpg 205>;
-                        status = "disabled";
-                };
-
                 can0: can@e6e80000 {
                         compatible = "renesas,can-r8a7744",
                                      "renesas,rcar-gen2-can";
@@ -1589,33 +1589,6 @@
                         resets = <&cpg 408>;
                 };
 
-                vsp@fe928000 {
-                        compatible = "renesas,vsp1";
-                        reg = <0 0xfe928000 0 0x8000>;
-                        interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 131>;
-                        power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
-                        resets = <&cpg 131>;
-                };
-
-                vsp@fe930000 {
-                        compatible = "renesas,vsp1";
-                        reg = <0 0xfe930000 0 0x8000>;
-                        interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 128>;
-                        power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
-                        resets = <&cpg 128>;
-                };
-
-                vsp@fe938000 {
-                        compatible = "renesas,vsp1";
-                        reg = <0 0xfe938000 0 0x8000>;
-                        interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 127>;
-                        power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
-                        resets = <&cpg 127>;
-                };
-
                 pciec: pcie@fe000000 {
                         compatible = "renesas,pcie-r8a7744",
                                      "renesas,pcie-rcar-gen2";
@@ -1644,9 +1617,42 @@
                         status = "disabled";
                 };
 
+                vsp@fe928000 {
+                        compatible = "renesas,vsp1";
+                        reg = <0 0xfe928000 0 0x8000>;
+                        interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 131>;
+                        power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+                        resets = <&cpg 131>;
+                };
+
+                vsp@fe930000 {
+                        compatible = "renesas,vsp1";
+                        reg = <0 0xfe930000 0 0x8000>;
+                        interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 128>;
+                        power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+                        resets = <&cpg 128>;
+                };
+
+                vsp@fe938000 {
+                        compatible = "renesas,vsp1";
+                        reg = <0 0xfe938000 0 0x8000>;
+                        interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 127>;
+                        power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+                        resets = <&cpg 127>;
+                };
+
                 du: display@feb00000 {
-                        reg = <0 0xfeb00000 0 0x40000>,
-                              <0 0xfeb90000 0 0x1c>;
+                        compatible = "renesas,du-r8a7744";
+                        reg = <0 0xfeb00000 0 0x40000>;
+                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 724>,
+                                 <&cpg CPG_MOD 723>;
+                        clock-names = "du.0", "du.1";
+                        status = "disabled";
 
                         ports {
                                 #address-cells = <1>;
@@ -1660,10 +1666,36 @@
                                 port@1 {
                                         reg = <1>;
                                         du_out_lvds0: endpoint {
+                                                remote-endpoint = <&lvds0_in>;
+                                        };
+                                };
+                        };
+                };
+
+                lvds0: lvds@feb90000 {
+                        compatible = "renesas,r8a7744-lvds";
+                        reg = <0 0xfeb90000 0 0x1c>;
+                        clocks = <&cpg CPG_MOD 726>;
+                        power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+                        resets = <&cpg 726>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        lvds0_in: endpoint {
+                                                remote-endpoint = <&du_out_lvds0>;
+                                        };
+                                };
+                                port@1 {
+                                        reg = <1>;
+                                        lvds0_out: endpoint {
                                         };
                                 };
                         };
-                        /* placeholder */
                 };
 
                 prr: chipid@ff000044 {
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index 40b7f98d6013..77d18242ef59 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -84,12 +84,30 @@
         clock-frequency = <20000000>;
 };
 
+&i2c3 {
+        pinctrl-0 = <&i2c3_pins>;
+        pinctrl-names = "default";
+
+        status = "okay";
+        clock-frequency = <400000>;
+
+        rtc@51 {
+                compatible = "nxp,pcf85263";
+                reg = <0x51>;
+        };
+};
+
 &pfc {
         avb_pins: avb {
                 groups = "avb_mdio", "avb_gmii_tx_rx";
                 function = "avb";
         };
 
+        i2c3_pins: i2c3 {
+                groups = "i2c3_c";
+                function = "i2c3";
+        };
+
         mmc_pins_uhs: mmc_uhs {
                 groups = "mmc_data8", "mmc_ctrl";
                 function = "mmc";
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 05db0ccad7a6..10d996d2941f 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -367,6 +367,30 @@
                 status = "disabled";
         };
 
+        hscif0: serial@ffe48000 {
+                compatible = "renesas,hscif-r8a7778",
+                             "renesas,rcar-gen1-hscif", "renesas,hscif";
+                reg = <0xffe48000 96>;
+                interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>,
+                         <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
+                clock-names = "fck", "brg_int", "scif_clk";
+                power-domains = <&cpg_clocks>;
+                status = "disabled";
+        };
+
+        hscif1: serial@ffe49000 {
+                compatible = "renesas,hscif-r8a7778",
+                             "renesas,rcar-gen1-hscif", "renesas,hscif";
+                reg = <0xffe49000 96>;
+                interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>,
+                         <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
+                clock-names = "fck", "brg_int", "scif_clk";
+                power-domains = <&cpg_clocks>;
+                status = "disabled";
+        };
+
         mmcif: mmc@ffe4e000 {
                 compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif";
                 reg = <0xffe4e000 0x100>;
@@ -535,6 +559,8 @@
                                  <&cpg_clocks R8A7778_CLK_P>,
                                  <&cpg_clocks R8A7778_CLK_P>,
                                  <&cpg_clocks R8A7778_CLK_P>,
+                                 <&cpg_clocks R8A7778_CLK_S>,
+                                 <&cpg_clocks R8A7778_CLK_S>,
                                  <&cpg_clocks R8A7778_CLK_P>,
                                  <&cpg_clocks R8A7778_CLK_P>,
                                  <&cpg_clocks R8A7778_CLK_P>,
@@ -551,6 +577,7 @@
                                 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
                                 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
                                 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
+                                R8A7778_CLK_HSCIF0 R8A7778_CLK_HSCIF1
                                 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
                                 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
                                 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
@@ -560,6 +587,7 @@
                         clock-output-names =
                                 "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
                                 "scif1", "scif2", "scif3", "scif4", "scif5",
+                                "hscif0", "hscif1",
                                 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
                                 "ssi2", "ssi3", "sru", "hspi";
                 };
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 3bc133d9489c..3ff259207527 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -287,6 +287,32 @@
                 status = "disabled";
         };
 
+        hscif0: serial@ffe48000 {
+                compatible = "renesas,hscif-r8a7779",
+                             "renesas,rcar-gen1-hscif", "renesas,hscif";
+                reg = <0xffe48000 96>;
+                interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7779_CLK_HSCIF0>,
+                         <&cpg_clocks R8A7779_CLK_S>,
+                         <&scif_clk>;
+                clock-names = "fck", "brg_int", "scif_clk";
+                power-domains = <&cpg_clocks>;
+                status = "disabled";
+        };
+
+        hscif1: serial@ffe49000 {
+                compatible = "renesas,hscif-r8a7779",
+                             "renesas,rcar-gen1-hscif", "renesas,hscif";
+                reg = <0xffe49000 96>;
+                interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7779_CLK_HSCIF1>,
+                         <&cpg_clocks R8A7779_CLK_S>,
+                         <&scif_clk>;
+                clock-names = "fck", "brg_int", "scif_clk";
+                power-domains = <&cpg_clocks>;
+                status = "disabled";
+        };
+
         pfc: pin-controller@fffc0000 {
                 compatible = "renesas,pfc-r8a7779";
                 reg = <0xfffc0000 0x23c>;
diff --git a/arch/arm/boot/dts/r8a7790-stout.dts b/arch/arm/boot/dts/r8a7790-stout.dts
index 629da4cee1b9..7a7d3b84d1a6 100644
--- a/arch/arm/boot/dts/r8a7790-stout.dts
+++ b/arch/arm/boot/dts/r8a7790-stout.dts
@@ -94,9 +94,8 @@
         status = "okay";
 
         clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
-                 <&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
                  <&osc1_clk>;
-        clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1", "dclkin.0";
+        clock-names = "du.0", "du.1", "du.2", "dclkin.0";
 
         ports {
                 port@0 {
@@ -104,11 +103,21 @@
                                 remote-endpoint = <&adv7511_in>;
                         };
                 };
+        };
+};
+
+&lvds0 {
+        ports {
                 port@1 {
                         lvds_connector0: endpoint {
                         };
                 };
-                port@2 {
+        };
+};
+
+&lvds1 {
+        ports {
+                port@1 {
                         lvds_connector1: endpoint {
                         };
                 };
diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts
index 0fd19f9723df..0173eb11ec28 100644
--- a/arch/arm/boot/dts/rk3036-kylin.dts
+++ b/arch/arm/boot/dts/rk3036-kylin.dts
@@ -310,7 +310,6 @@
 };
 
 &i2s {
-        #sound-dai-cells = <0>;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index d560fc4051c5..59c90863b0e7 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -289,6 +289,7 @@
                 dma-names = "tx", "rx";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2s_bus>;
+                #sound-dai-cells = <0>;
                 status = "disabled";
         };
 
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index 1c925f20dba0..0a56a2f1bc4d 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -171,7 +171,6 @@
         pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
 
         bus-width = <4>;
-        disable-wp;
 };
 
 &pwm3 {
diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts
index b6a8a82d219e..9d2216d71f70 100644
--- a/arch/arm/boot/dts/rk3066a-mk808.dts
+++ b/arch/arm/boot/dts/rk3066a-mk808.dts
@@ -101,7 +101,6 @@
 
 &mmc1 {
         bus-width = <4>;
-        disable-wp;
         non-removable;
         pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts
index cd126b927ba8..949fa800582d 100644
--- a/arch/arm/boot/dts/rk3066a-rayeager.dts
+++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
@@ -147,7 +147,6 @@
 &emmc {
         bus-width = <8>;
         cap-mmc-highspeed;
-        disable-wp;
         non-removable;
         pinctrl-names = "default";
         pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>;
@@ -309,7 +308,6 @@
 
 &mmc1 {
         bus-width = <4>;
-        disable-wp;
         non-removable;
         pinctrl-names = "default";
         pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>;
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 30dc8af0bdcb..653127a377fa 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -44,6 +44,11 @@
                 };
         };
 
+        display-subsystem {
+                compatible = "rockchip,display-subsystem";
+                ports = <&vop0_out>, <&vop1_out>;
+        };
+
         sram: sram@10080000 {
                 compatible = "mmio-sram";
                 reg = <0x10080000 0x10000>;
@@ -57,6 +62,48 @@
                 };
         };
 
+        vop0: vop@1010c000 {
+                compatible = "rockchip,rk3066-vop";
+                reg = <0x1010c000 0x19c>;
+                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru ACLK_LCDC0>,
+                         <&cru DCLK_LCDC0>,
+                         <&cru HCLK_LCDC0>;
+                clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+                power-domains = <&power RK3066_PD_VIO>;
+                resets = <&cru SRST_LCDC0_AXI>,
+                         <&cru SRST_LCDC0_AHB>,
+                         <&cru SRST_LCDC0_DCLK>;
+                reset-names = "axi", "ahb", "dclk";
+                status = "disabled";
+
+                vop0_out: port {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+        };
+
+        vop1: vop@1010e000 {
+                compatible = "rockchip,rk3066-vop";
+                reg = <0x1010e000 0x19c>;
+                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru ACLK_LCDC1>,
+                         <&cru DCLK_LCDC1>,
+                         <&cru HCLK_LCDC1>;
+                clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+                power-domains = <&power RK3066_PD_VIO>;
+                resets = <&cru SRST_LCDC1_AXI>,
+                         <&cru SRST_LCDC1_AHB>,
+                         <&cru SRST_LCDC1_DCLK>;
+                reset-names = "axi", "ahb", "dclk";
+                status = "disabled";
+
+                vop1_out: port {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+        };
+
         i2s0: i2s@10118000 {
                 compatible = "rockchip,rk3066-i2s";
                 reg = <0x10118000 0x2000>;
@@ -669,6 +716,7 @@
                                  <&cru SCLK_CIF0>,
                                  <&cru ACLK_CIF0>,
                                  <&cru HCLK_CIF0>,
+                                 <&cru HCLK_HDMI>,
                                  <&cru ACLK_IPP>,
                                  <&cru HCLK_IPP>,
                                  <&cru ACLK_RGA>,
diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts
index a7477a09fbe8..c8b62bbd6a4a 100644
--- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts
+++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts
@@ -227,7 +227,6 @@
 &emmc {
         bus-width = <8>;
         cap-mmc-highspeed;
-        disable-wp;
         non-removable;
         pinctrl-names = "default";
         pinctrl-0 = <&emmc_clk &emmc_cmd>;
@@ -408,6 +407,21 @@
 &i2c2 {
         clock-frequency = <400000>;
         status = "okay";
+
+        ft5606: touchscreen@3e {
+                compatible = "edt,edt-ft5506";
+                reg = <0x3e>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <RK_PB7 IRQ_TYPE_EDGE_FALLING>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&tp_int &tp_rst>;
+                reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
+                touchscreen-inverted-y;
+                /* hw ts resolution does not match display */
+                touchscreen-size-y = <1024>;
+                touchscreen-size-x = <768>;
+                touchscreen-swapped-x-y;
+        };
 };
 
 &i2c3 {
@@ -446,7 +460,6 @@
 &mmc1 {
         bus-width = <4>;
         cap-sd-highspeed;
-        cap-mmc-highspeed;
         keep-power-in-suspend;
         mmc-pwrseq = <&sdio_pwrseq>;
         non-removable;
@@ -526,7 +539,7 @@
                 };
 
                 cif1_pdn: cif1-pdn {
-                        rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+                        rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
                 };
 
                 cif_avdd_en: cif-avdd-en {
diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts
index 9ae65c767c90..c0eaa9c5490b 100644
--- a/arch/arm/boot/dts/rk3188-px3-evb.dts
+++ b/arch/arm/boot/dts/rk3188-px3-evb.dts
@@ -62,7 +62,6 @@
 &emmc {
         bus-width = <8>;
         cap-mmc-highspeed;
-        disable-wp;
         non-removable;
         pinctrl-names = "default";
         pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_rst>;
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 4acb501dd3f8..3ed49898f4b2 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -719,7 +719,6 @@
                         pm_qos = <&qos_lcdc0>,
                                  <&qos_lcdc1>,
                                  <&qos_cif0>,
-                                 <&qos_cif1>,
                                  <&qos_ipp>,
                                  <&qos_rga>;
                 };
diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts
index 4df7accc3ad7..350497a3ca86 100644
--- a/arch/arm/boot/dts/rk3229-evb.dts
+++ b/arch/arm/boot/dts/rk3229-evb.dts
@@ -137,7 +137,6 @@
 
 &emmc {
         cap-mmc-highspeed;
-        disable-wp;
         non-removable;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/rk3288-fennec.dts b/arch/arm/boot/dts/rk3288-fennec.dts
index b1b56dfdfdba..29af26e6d442 100644
--- a/arch/arm/boot/dts/rk3288-fennec.dts
+++ b/arch/arm/boot/dts/rk3288-fennec.dts
@@ -37,7 +37,6 @@
 &emmc {
         bus-width = <8>;
         cap-mmc-highspeed;
-        disable-wp;
         non-removable;
         pinctrl-names = "default";
         pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts
index 58ea8bed040a..3a646c5f4fcf 100644
--- a/arch/arm/boot/dts/rk3288-firefly-reload.dts
+++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts
@@ -254,7 +254,6 @@
         bus-width = <4>;
         cap-sd-highspeed;
         cap-sdio-irq;
-        disable-wp;
         mmc-pwrseq = <&sdio_pwrseq>;
         non-removable;
         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index 504ab1177aa7..fb7365b604bb 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -87,7 +87,6 @@
 &emmc {
         bus-width = <8>;
         cap-mmc-highspeed;
-        disable-wp;
         non-removable;
         pinctrl-names = "default";
         pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts
index 596435e03132..6a51940398b5 100644
--- a/arch/arm/boot/dts/rk3288-popmetal.dts
+++ b/arch/arm/boot/dts/rk3288-popmetal.dts
@@ -109,7 +109,6 @@
 &emmc {
         bus-width = <8>;
         cap-mmc-highspeed;
-        disable-wp;
         mmc-ddr-1_8v;
         mmc-hs200-1_8v;
         non-removable;
diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts
index 6a30cadad88a..5b7e1c9e92e1 100644
--- a/arch/arm/boot/dts/rk3288-rock2-square.dts
+++ b/arch/arm/boot/dts/rk3288-rock2-square.dts
@@ -133,7 +133,6 @@
         bus-width = <4>;
         cap-sd-highspeed;
         cap-sdio-irq;
-        disable-wp;
         mmc-pwrseq = <&sdio_pwrseq>;
         non-removable;
         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/rk3288-tinker-s.dts b/arch/arm/boot/dts/rk3288-tinker-s.dts
index 37093922b482..d97da89bcd51 100644
--- a/arch/arm/boot/dts/rk3288-tinker-s.dts
+++ b/arch/arm/boot/dts/rk3288-tinker-s.dts
@@ -15,7 +15,6 @@
 &emmc {
         bus-width = <8>;
         cap-mmc-highspeed;
-        disable-wp;
         non-removable;
         pinctrl-names = "default";
         pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index d8bf939a3aff..0bc2409f6903 100644
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -10,6 +10,10 @@
 #include "rk3288.dtsi"
 
 / {
+        chosen {
+                stdout-path = "serial2:115200n8";
+        };
+
         /*
          * The default coreboot on veyron devices ignores memory@0 nodes
          * and would instead create another memory node.
diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts
index 4856a9fc0aea..40b232eb5011 100644
--- a/arch/arm/boot/dts/rk3288-vyasa.dts
+++ b/arch/arm/boot/dts/rk3288-vyasa.dts
@@ -121,7 +121,6 @@
 &emmc {
         bus-width = <8>;
         cap-mmc-highspeed;
-        disable-wp;
         non-removable;
         pinctrl-names = "default";
         pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
diff --git a/arch/arm/boot/dts/rv1108-elgin-r1.dts b/arch/arm/boot/dts/rv1108-elgin-r1.dts
new file mode 100644
index 000000000000..1c4507b66fdd
--- /dev/null
+++ b/arch/arm/boot/dts/rv1108-elgin-r1.dts
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Copyright (C) 2018 O.S. Systems Software LTDA.
+ */
+
+/dts-v1/;
+
+#include "rv1108.dtsi"
+
+/ {
+        model = "Elgin RV1108 R1 board";
+        compatible = "elgin,rv1108-r1", "rockchip,rv1108";
+
+        memory@60000000 {
+                device_type = "memory";
+                reg = <0x60000000 0x08000000>;
+        };
+
+        chosen {
+                stdout-path = "serial2:1500000n8";
+        };
+
+        vcc_sys: vsys-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "vsys";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+        };
+};
+
+&cpu0 {
+        cpu-supply = <&vdd_core>;
+};
+
+&emmc {
+        bus-width = <8>;
+        cap-mmc-highspeed;
+        disable-wp;
+        no-sd;
+        no-sdio;
+        non-removable;
+        mmc-ddr-1_8v;
+        mmc-hs200-1_8v;
+        pinctrl-names = "default";
+        pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+        status = "okay";
+};
+
+&gmac {
+        clock_in_out = "output";
+        pinctrl-names = "default";
+        pinctrl-0 = <&rmii_pins>;
+        snps,reset-gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>;
+        snps,reset-active-low;
+        status = "okay";
+};
+
+&i2c0 {
+        clock-frequency = <400000>;
+        i2c-scl-rising-time-ns = <275>;
+        i2c-scl-falling-time-ns = <16>;
+        status = "okay";
+
+        rk805: pmic@18 {
+                compatible = "rockchip,rk805";
+                reg = <0x18>;
+                interrupt-parent = <&gpio0>;
+                interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>;
+                rockchip,system-power-controller;
+
+                vcc1-supply = <&vcc_sys>;
+                vcc2-supply = <&vcc_sys>;
+                vcc3-supply = <&vcc_sys>;
+                vcc4-supply = <&vcc_sys>;
+                vcc5-supply = <&vdd_buck2>;
+                vcc6-supply = <&vdd_buck2>;
+
+                regulators {
+                        vdd_core: DCDC_REG1 {
+                                regulator-name= "vdd_core";
+                                regulator-min-microvolt = <700000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <900000>;
+                                };
+                        };
+
+                        vdd_buck2: DCDC_REG2 {
+                                regulator-name= "vdd_buck2";
+                                regulator-min-microvolt = <2200000>;
+                                regulator-max-microvolt = <2200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vcc_ddr: DCDC_REG3 {
+                                regulator-name= "vcc_ddr";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        vcc_io: DCDC_REG4 {
+                                regulator-name= "vcc_io";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3300000>;
+                                };
+                        };
+
+                        vdd_10: LDO_REG1 {
+                                regulator-name= "vdd_10";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vcc_18: LDO_REG2 {
+                                regulator-name= "vcc_18";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vdd10_pmu: LDO_REG3 {
+                                regulator-name= "vdd10_pmu";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1000000>;
+                                };
+                        };
+                };
+        };
+};
+
+&spi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spim1_clk &spim1_cs0 &spim1_tx &spim1_rx>;
+        status = "okay";
+
+        dh2228fv: dac@0 {
+                compatible = "rohm,dh2228fv";
+                reg = <0>;
+                spi-max-frequency = <24000000>;
+                spi-cpha;
+                spi-cpol;
+        };
+};
+
+&u2phy {
+        status = "okay";
+
+        u2phy_host: host-port {
+                status = "okay";
+        };
+
+        u2phy_otg: otg-port {
+                status = "okay";
+        };
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_xfer>;
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&usb_host_ehci {
+        status = "okay";
+};
+
+&usb_host_ohci {
+        status = "okay";
+};
+
+&usb_otg {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index 203d83e3bbf5..30f3d0470ad9 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -97,8 +97,8 @@
                                 regulator-always-on;
                                 regulator-boot-on;
                                 regulator-state-mem {
-                                        regulator-state-enabled;
-                                        regulator-state-uv = <900000>;
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <900000>;
                                 };
                         };
 
@@ -107,7 +107,7 @@
                                 regulator-min-microvolt = <700000>;
                                 regulator-max-microvolt = <2000000>;
                                 regulator-state-mem {
-                                        regulator-state-disabled;
+                                        regulator-off-in-suspend;
                                 };
                         };
 
@@ -116,7 +116,7 @@
                                 regulator-always-on;
                                 regulator-boot-on;
                                 regulator-state-mem {
-                                        regulator-state-enabled;
+                                        regulator-on-in-suspend;
                                 };
                         };
 
@@ -127,8 +127,8 @@
                                 regulator-always-on;
                                 regulator-boot-on;
                                 regulator-state-mem {
-                                        regulator-state-enabled;
-                                        regulator-state-uv = <3300000>;
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3300000>;
                                 };
                         };
 
@@ -139,7 +139,7 @@
                                 regulator-always-on;
                                 regulator-boot-on;
                                 regulator-state-mem {
-                                        regulator-state-disabled;
+                                        regulator-off-in-suspend;
                                 };
                         };
 
@@ -150,7 +150,7 @@
                                 regulator-always-on;
                                 regulator-boot-on;
                                 regulator-state-mem {
-                                        regulator-state-disabled;
+                                        regulator-off-in-suspend;
                                 };
                         };
 
@@ -161,8 +161,8 @@
                                 regulator-always-on;
                                 regulator-boot-on;
                                 regulator-state-mem {
-                                        regulator-state-enabled;
-                                        regulator-state-uv = <1000000>;
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1000000>;
                                 };
                         };
                 };
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index d31370ff28f4..f47ac86d2852 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -207,6 +207,7 @@
                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
                 clock-names = "spiclk", "apb_pclk";
                 dmas = <&pdma 8>, <&pdma 9>;
+                dma-names = "tx", "rx";
                 #dma-cells = <2>;
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -833,6 +834,42 @@
                         };
                 };
 
+                spim0 {
+                        spim0_clk: spim0-clk {
+                                rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_up>;
+                        };
+
+                        spim0_cs0: spim0-cs0 {
+                                rockchip,pins = <1 RK_PD1 RK_FUNC_2 &pcfg_pull_up>;
+                        };
+
+                        spim0_tx: spim0-tx {
+                                rockchip,pins = <1 RK_PD3 RK_FUNC_2 &pcfg_pull_up>;
+                        };
+
+                        spim0_rx: spim0-rx {
+                                rockchip,pins = <1 RK_PD2 RK_FUNC_2 &pcfg_pull_up>;
+                        };
+                };
+
+                spim1 {
+                        spim1_clk: spim1-clk {
+                                rockchip,pins = <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+
+                        spim1_cs0: spim1-cs0 {
+                                rockchip,pins = <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+
+                        spim1_rx: spim1-rx {
+                                rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+
+                        spim1_tx: spim1-tx {
+                                rockchip,pins = <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
+                        };
+                };
+
                 tsadc {
                         otp_out: otp-out {
                                 rockchip,pins = <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts
index 5164386aff3a..cb371bf72f64 100644
--- a/arch/arm/boot/dts/s3c2416-smdk2416.dts
+++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts
@@ -19,9 +19,12 @@
 
         clocks {
                 compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
 
-                xti: xti {
+                xti: xti@0 {
                         compatible = "fixed-clock";
+                        reg = <0>;
                         clock-frequency = <12000000>;
                         clock-output-names = "xti";
                         #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi
index 575094ea7024..8ff70b856334 100644
--- a/arch/arm/boot/dts/s5pv210-aries.dtsi
+++ b/arch/arm/boot/dts/s5pv210-aries.dtsi
@@ -23,6 +23,31 @@
                         0x50000000 0x08000000>;
         };
 
+        reserved-memory {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                mfc_left: region@43000000 {
+                        compatible = "shared-dma-pool";
+                        no-map;
+                        reg = <0x43000000 0x2000000>;
+                };
+
+                mfc_right: region@51000000 {
+                        compatible = "shared-dma-pool";
+                        no-map;
+                        reg = <0x51000000 0x2000000>;
+                };
+        };
+
+        vibrator_pwr: regulator-fixed-0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vibrator-en";
+                enable-active-high;
+                gpio = <&gpj1 1 GPIO_ACTIVE_HIGH>;
+        };
+
         wifi_pwrseq: wifi-pwrseq {
                 compatible = "mmc-pwrseq-simple";
                 reset-gpios = <&gpg1 2 GPIO_ACTIVE_LOW>;
@@ -296,6 +321,22 @@
                         reg = <0x36>;
                 };
         };
+
+        vibrator: pwm-vibrator {
+                compatible = "pwm-vibrator";
+                pwms = <&pwm 1 44642 0>;
+                pwm-names = "enable";
+                vcc-supply = <&vibrator_pwr>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwm1_out>;
+        };
+
+        poweroff: syscon-poweroff {
+                compatible = "syscon-poweroff";
+                regmap = <&pmu_syscon>;
+                offset = <0x681c>; /* PS_HOLD_CONTROL */
+                value = <0x5200>;
+        };
 };
 
 &fimd {
@@ -329,6 +370,27 @@
         status = "okay";
 };
 
+&i2c2 {
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <400000>;
+        samsung,i2c-slave-addr = <0x10>;
+        status = "okay";
+
+        touchscreen@4a {
+                compatible = "atmel,maxtouch";
+                reg = <0x4a>;
+                interrupt-parent = <&gpj0>;
+                interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&ts_irq>;
+                reset-gpios = <&gpj1 3 GPIO_ACTIVE_HIGH>;
+        };
+};
+
+&mfc {
+        memory-region = <&mfc_left>, <&mfc_right>;
+};
+
 &pinctrl0 {
         wlan_bt_en: wlan-bt-en {
                 samsung,pins = "gpb-5";
@@ -350,6 +412,13 @@
                 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
         };
 
+        bt_host_wake: bt-host-wake {
+                samsung,pins = "gph2-5";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+                samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
         tf_detect: tf-detect {
                 samsung,pins = "gph3-4";
                 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
@@ -362,6 +431,17 @@
                 samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
                 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
         };
+
+        ts_irq: ts-irq {
+                samsung,pins = "gpj0-5";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+                samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+};
+
+&pwm {
+        samsung,pwm-outputs = <1>;
 };
 
 &sdhci1 {
@@ -399,6 +479,16 @@
 
 &uart0 {
         status = "okay";
+
+        bluetooth {
+                compatible = "brcm,bcm43438-bt";
+                max-speed = <115200>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart0_data &uart0_fctl &bt_host_wake>;
+                shutdown-gpios = <&gpb 3 GPIO_ACTIVE_HIGH>;
+                device-wakeup-gpios = <&gpg3 4 GPIO_ACTIVE_HIGH>;
+                host-wakeup-gpios = <&gph2 5 GPIO_ACTIVE_HIGH>;
+        };
 };
 
 &uart1 {
diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/s5pv210-fascinate4g.dts
index ccf761b1babf..07a8d9bbe5b8 100644
--- a/arch/arm/boot/dts/s5pv210-fascinate4g.dts
+++ b/arch/arm/boot/dts/s5pv210-fascinate4g.dts
@@ -11,13 +11,6 @@
 
         chosen {
                 stdout-path = &uart2;
-                /*
-                 * It's hard to change those parameters in stock bootloader,
-                 * since it requires special hardware/cable.
-                 * Let's hardocde bootargs for now, till u-boot port is finished,
-                 * with which it should be easier.
-                 */
-                bootargs = "root=/dev/mmcblk1p1 rw rootwait ignore_loglevel earlyprintk";
         };
 
         gpio-keys {
diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/s5pv210-galaxys.dts
index 842276749717..cf161bbfbacf 100644
--- a/arch/arm/boot/dts/s5pv210-galaxys.dts
+++ b/arch/arm/boot/dts/s5pv210-galaxys.dts
@@ -11,13 +11,6 @@
 
         chosen {
                 stdout-path = &uart2;
-                /*
-                 * It's hard to change those parameters in stock bootloader,
-                 * since it requires special hardware/cable.
-                 * Let's hardocde bootargs for now, till u-boot port is finished,
-                 * with which it should be easier.
-                 */
-                bootargs = "root=/dev/mmcblk2p1 rw rootwait ignore_loglevel earlyprintk";
         };
 
         nand_pwrseq: nand-pwrseq {
diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi
index 12eac8930eac..a44d5eb56bed 100644
--- a/arch/arm/boot/dts/s5pv210.dtsi
+++ b/arch/arm/boot/dts/s5pv210.dtsi
@@ -25,6 +25,8 @@
 
         aliases {
                 csis0 = &csis0;
+                dmc0 = &dmc0;
+                dmc1 = &dmc1;
                 fimc0 = &fimc0;
                 fimc1 = &fimc1;
                 fimc2 = &fimc2;
@@ -78,7 +80,7 @@
                         };
                 };
 
-                onenand: onenand@b0000000 {
+                onenand: onenand@b0600000 {
                         compatible = "samsung,s5pv210-onenand";
                         reg = <0xb0600000 0x2000>,
                                 <0xb0000000 0x20000>,
@@ -511,7 +513,7 @@
                 };
 
                 fimd: fimd@f8000000 {
-                        compatible = "samsung,exynos4210-fimd";
+                        compatible = "samsung,s5pv210-fimd";
                         interrupt-parent = <&vic2>;
                         reg = <0xf8000000 0x20000>;
                         interrupt-names = "fifo", "vsync", "lcd_sys";
@@ -521,6 +523,16 @@
                         status = "disabled";
                 };
 
+                dmc0: dmc@f0000000 {
+                        compatible = "samsung,s5pv210-dmc";
+                        reg = <0xf0000000 0x1000>;
+                };
+
+                dmc1: dmc@f1400000 {
+                        compatible = "samsung,s5pv210-dmc";
+                        reg = <0xf1400000 0x1000>;
+                };
+
                 g2d: g2d@fa000000 {
                         compatible = "samsung,s5pv210-g2d";
                         reg = <0xfa000000 0x1000>;
@@ -542,6 +554,15 @@
                         #dma-requests = <1>;
                 };
 
+                rotator: rotator@fa300000 {
+                        compatible = "samsung,s5pv210-rotator";
+                        reg = <0xfa300000 0x1000>;
+                        interrupt-parent = <&vic2>;
+                        interrupts = <4>;
+                        clocks = <&clocks CLK_ROTATOR>;
+                        clock-names = "rotator";
+                };
+
                 i2c1: i2c@fab00000 {
                         compatible = "samsung,s3c2440-i2c";
                         reg = <0xfab00000 0x1000>;
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index dc2280d9127f..d159ee42ef29 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -43,13 +43,14 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include "skeleton.dtsi"
 #include <dt-bindings/dma/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/clock/at91.h>
 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Atmel SAMA5D2 family SoC";
         compatible = "atmel,sama5d2";
         interrupt-parent = <&aic>;
@@ -113,6 +114,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x20000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 1408fa4a62e4..02198772eb81 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -8,7 +8,6 @@
  * Licensed under GPLv2 or later.
  */
 
-#include "skeleton.dtsi"
 #include <dt-bindings/dma/at91.h>
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -16,6 +15,8 @@
 #include <dt-bindings/clock/at91.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Atmel SAMA5D3 family SoC";
         compatible = "atmel,sama5d3", "atmel,sama5";
         interrupt-parent = <&aic>;
@@ -56,6 +57,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x20000000 0x8000000>;
         };
 
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 2604fd07dd53..6c1e41f94549 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -43,7 +43,6 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include "skeleton.dtsi"
 #include <dt-bindings/clock/at91.h>
 #include <dt-bindings/dma/at91.h>
 #include <dt-bindings/pinctrl/at91.h>
@@ -51,6 +50,8 @@
 #include <dt-bindings/gpio/gpio.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         model = "Atmel SAMA5D4 family SoC";
         compatible = "atmel,sama5d4";
         interrupt-parent = <&aic>;
@@ -90,6 +91,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x20000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/skeleton.dtsi b/arch/arm/boot/dts/skeleton.dtsi
deleted file mode 100644
index 34eda68d9ea2..000000000000
--- a/arch/arm/boot/dts/skeleton.dtsi
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * This file is deprecated, and will be removed once existing users have been
- * updated. New dts{,i} files should *not* include skeleton.dtsi, and should
- * instead explicitly provide the below nodes only as required.
- *
- * Skeleton device tree; the bare minimum needed to boot; just include and
- * add a compatible value.  The bootloader will typically populate the memory
- * node.
- */
-
-/ {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        chosen { };
-        aliases { };
-        memory { device_type = "memory"; reg = <0 0>; };
-};
diff --git a/arch/arm/boot/dts/skeleton64.dtsi b/arch/arm/boot/dts/skeleton64.dtsi
deleted file mode 100644
index 54e637752b9d..000000000000
--- a/arch/arm/boot/dts/skeleton64.dtsi
+++ /dev/null
@@ -1,14 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Skeleton device tree in the 64 bits version; the bare minimum
- * needed to boot; just include and add a compatible value.  The
- * bootloader will typically populate the memory node.
- */
-
-/ {
-        #address-cells = <2>;
-        #size-cells = <2>;
-        chosen { };
-        aliases { };
-        memory { device_type = "memory"; reg = <0 0 0 0>; };
-};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index dcb8fba3d709..ec1966480f2f 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -84,6 +84,7 @@
                                 #dma-requests = <32>;
                                 clocks = <&l4_main_clk>;
                                 clock-names = "apb_pclk";
+                                resets = <&rst DMA_RESET>;
                         };
                 };
 
@@ -100,6 +101,7 @@
                         reg = <0xffc00000 0x1000>;
                         interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
                         clocks = <&can0_clk>;
+                        resets = <&rst CAN0_RESET>;
                         status = "disabled";
                 };
 
@@ -108,6 +110,7 @@
                         reg = <0xffc01000 0x1000>;
                         interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
                         clocks = <&can1_clk>;
+                        resets = <&rst CAN1_RESET>;
                         status = "disabled";
                 };
 
@@ -585,6 +588,7 @@
                         compatible = "snps,dw-apb-gpio";
                         reg = <0xff708000 0x1000>;
                         clocks = <&l4_mp_clk>;
+                        resets = <&rst GPIO0_RESET>;
                         status = "disabled";
 
                         porta: gpio-controller@0 {
@@ -605,6 +609,7 @@
                         compatible = "snps,dw-apb-gpio";
                         reg = <0xff709000 0x1000>;
                         clocks = <&l4_mp_clk>;
+                        resets = <&rst GPIO1_RESET>;
                         status = "disabled";
 
                         portb: gpio-controller@0 {
@@ -625,6 +630,7 @@
                         compatible = "snps,dw-apb-gpio";
                         reg = <0xff70a000 0x1000>;
                         clocks = <&l4_mp_clk>;
+                        resets = <&rst GPIO2_RESET>;
                         status = "disabled";
 
                         portc: gpio-controller@0 {
@@ -735,6 +741,7 @@
                         #size-cells = <0>;
                         clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
                         clock-names = "biu", "ciu";
+                        resets = <&rst SDMMC_RESET>;
                         status = "disabled";
                 };
 
@@ -748,6 +755,7 @@
                         interrupts = <0x0 0x90 0x4>;
                         clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
                         clock-names = "nand", "nand_x", "ecc";
+                        resets = <&rst NAND_RESET>;
                         status = "disabled";
                 };
 
@@ -767,6 +775,7 @@
                         cdns,fifo-width = <4>;
                         cdns,trigger-address = <0x00000000>;
                         clocks = <&qspi_clk>;
+                        resets = <&rst QSPI_RESET>;
                         status = "disabled";
                 };
 
@@ -785,6 +794,7 @@
                 sdr: sdr@ffc25000 {
                         compatible = "altr,sdr-ctl", "syscon";
                         reg = <0xffc25000 0x1000>;
+                        resets = <&rst SDR_RESET>;
                 };
 
                 sdramedac {
@@ -801,6 +811,7 @@
                         interrupts = <0 154 4>;
                         num-cs = <4>;
                         clocks = <&spi_m_clk>;
+                        resets = <&rst SPIM0_RESET>;
                         status = "disabled";
                 };
 
@@ -812,6 +823,7 @@
                         interrupts = <0 155 4>;
                         num-cs = <4>;
                         clocks = <&spi_m_clk>;
+                        resets = <&rst SPIM1_RESET>;
                         status = "disabled";
                 };
 
@@ -878,6 +890,7 @@
                         dmas = <&pdma 28>,
                                <&pdma 29>;
                         dma-names = "tx", "rx";
+                        resets = <&rst UART0_RESET>;
                 };
 
                 uart1: serial1@ffc03000 {
@@ -890,6 +903,7 @@
                         dmas = <&pdma 30>,
                                <&pdma 31>;
                         dma-names = "tx", "rx";
+                        resets = <&rst UART1_RESET>;
                 };
 
                 usbphy0: usbphy {
@@ -929,6 +943,7 @@
                         reg = <0xffd02000 0x1000>;
                         interrupts = <0 171 4>;
                         clocks = <&osc1>;
+                        resets = <&rst L4WD0_RESET>;
                         status = "disabled";
                 };
 
@@ -937,6 +952,7 @@
                         reg = <0xffd03000 0x1000>;
                         interrupts = <0 172 4>;
                         clocks = <&osc1>;
+                        resets = <&rst L4WD1_RESET>;
                         status = "disabled";
                 };
         };
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index e41fa23481c3..ae24599d5829 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -470,6 +470,7 @@
                         tx-fifo-depth = <4096>;
                         rx-fifo-depth = <16384>;
                         clocks = <&l4_mp_clk>;
+                        resets = <&rst EMAC2_RESET>;
                         clock-names = "stmmaceth";
                         snps,axi-config = <&socfpga_axi_setup>;
                         status = "disabled";
@@ -480,6 +481,7 @@
                         #size-cells = <0>;
                         compatible = "snps,dw-apb-gpio";
                         reg = <0xffc02900 0x100>;
+                        resets = <&rst GPIO0_RESET>;
                         status = "disabled";
 
                         porta: gpio-controller@0 {
@@ -499,6 +501,7 @@
                         #size-cells = <0>;
                         compatible = "snps,dw-apb-gpio";
                         reg = <0xffc02a00 0x100>;
+                        resets = <&rst GPIO1_RESET>;
                         status = "disabled";
 
                         portb: gpio-controller@0 {
@@ -518,6 +521,7 @@
                         #size-cells = <0>;
                         compatible = "snps,dw-apb-gpio";
                         reg = <0xffc02b00 0x100>;
+                        resets = <&rst GPIO2_RESET>;
                         status = "disabled";
 
                         portc: gpio-controller@0 {
@@ -548,6 +552,7 @@
                         reg = <0xffc02200 0x100>;
                         interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&l4_sp_clk>;
+                        resets = <&rst I2C0_RESET>;
                         status = "disabled";
                 };
 
@@ -558,6 +563,7 @@
                         reg = <0xffc02300 0x100>;
                         interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&l4_sp_clk>;
+                        resets = <&rst I2C1_RESET>;
                         status = "disabled";
                 };
 
@@ -568,6 +574,7 @@
                         reg = <0xffc02400 0x100>;
                         interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&l4_sp_clk>;
+                        resets = <&rst I2C2_RESET>;
                         status = "disabled";
                 };
 
@@ -578,6 +585,7 @@
                         reg = <0xffc02500 0x100>;
                         interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&l4_sp_clk>;
+                        resets = <&rst I2C3_RESET>;
                         status = "disabled";
                 };
 
@@ -588,6 +596,7 @@
                         reg = <0xffc02600 0x100>;
                         interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&l4_sp_clk>;
+                        resets = <&rst I2C4_RESET>;
                         status = "disabled";
                 };
 
@@ -600,6 +609,7 @@
                         num-cs = <4>;
                         /*32bit_access;*/
                         clocks = <&spi_m_clk>;
+                        resets = <&rst SPIM0_RESET>;
                         status = "disabled";
                 };
 
@@ -614,6 +624,7 @@
                         tx-dma-channel = <&pdma 16>;
                         rx-dma-channel = <&pdma 17>;
                         clocks = <&spi_m_clk>;
+                        resets = <&rst SPIM1_RESET>;
                         status = "disabled";
                 };
 
@@ -642,6 +653,7 @@
                         fifo-depth = <0x400>;
                         clocks = <&l4_mp_clk>, <&sdmmc_clk>;
                         clock-names = "biu", "ciu";
+                        resets = <&rst SDMMC_RESET>;
                         status = "disabled";
                 };
 
@@ -655,6 +667,7 @@
                         interrupts = <0 99 4>;
                         clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
                         clock-names = "nand", "nand_x", "ecc";
+                        resets = <&rst NAND_RESET>;
                         status = "disabled";
                 };
 
@@ -739,6 +752,7 @@
                         cdns,fifo-width = <4>;
                         cdns,trigger-address = <0x00000000>;
                         clocks = <&qspi_clk>;
+                        resets = <&rst QSPI_RESET>;
                         status = "disabled";
                 };
 
@@ -815,6 +829,7 @@
                         reg-shift = <2>;
                         reg-io-width = <4>;
                         clocks = <&l4_sp_clk>;
+                        resets = <&rst UART0_RESET>;
                         status = "disabled";
                 };
 
@@ -825,6 +840,7 @@
                         reg-shift = <2>;
                         reg-io-width = <4>;
                         clocks = <&l4_sp_clk>;
+                        resets = <&rst UART1_RESET>;
                         status = "disabled";
                 };
 
@@ -865,6 +881,7 @@
                         reg = <0xffd00200 0x100>;
                         interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&l4_sys_free_clk>;
+                        resets = <&rst L4WD0_RESET>;
                         status = "disabled";
                 };
 
@@ -873,6 +890,7 @@
                         reg = <0xffd00300 0x100>;
                         interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&l4_sys_free_clk>;
+                        resets = <&rst L4WD1_RESET>;
                         status = "disabled";
                 };
         };
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts b/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts
new file mode 100644
index 000000000000..f6561766d83f
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Device Tree file for the Chameleon96
+ *
+ * Copyright (c) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+        model = "Novetech Chameleon96";
+        compatible = "novtech,chameleon96", "altr,socfpga-cyclone5", "altr,socfpga";
+
+        chosen {
+                bootargs = "earlyprintk";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                name = "memory";
+                device_type = "memory";
+                reg = <0x0 0x20000000>; /* 512MB */
+        };
+
+        regulator_3_3v: 3-3-v-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                user_led1 {
+                        label = "green:user1";
+                        gpios = <&porta 14 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "heartbeat";
+                };
+
+                user_led2 {
+                        label = "green:user2";
+                        gpios = <&porta 22 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "mmc0";
+                };
+
+                user_led3 {
+                        label = "green:user3";
+                        gpios = <&porta 25 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "none";
+                };
+
+                user_led4 {
+                        label = "green:user4";
+                        gpios = <&portb 3 GPIO_ACTIVE_LOW>;
+                        panic-indicator;
+                        linux,default-trigger = "none";
+                };
+        };
+};
+
+&gpio0 {
+        status = "okay";
+};
+
+&gpio1 {
+        status = "okay";
+};
+
+&i2c0 {
+        /* On Low speed expansion */
+        label = "LS-I2C0";
+        status = "okay";
+};
+
+&i2c1 {
+        /* On Low speed expansion */
+        label = "LS-I2C1";
+        status = "okay";
+};
+
+&i2c2 {
+        status = "okay";
+};
+
+&i2c3 {
+        /* On High speed expansion */
+        label = "HS-I2C2";
+        status = "okay";
+};
+
+&mmc0 {
+        vmmc-supply = <&regulator_3_3v>;
+        vqmmc-supply = <&regulator_3_3v>;
+        status = "okay";
+};
+
+&spi0 {
+        /* On High speed expansion */
+        label = "HS-SPI1";
+        status = "okay";
+};
+
+&spi1 {
+        /* On Low speed expansion */
+        label = "LS-SPI0";
+        status = "okay";
+};
+
+&uart0 {
+        /* On Low speed expansion */
+        label = "LS-UART1";
+        status = "okay";
+};
+
+&uart1 {
+        /* On Low speed expansion */
+        label = "LS-UART0";
+        status = "okay";
+};
+
+&usbphy0 {
+        status = "okay";
+};
+
+&usb1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 086b4b333249..390df643a174 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -11,9 +11,9 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/include/ "skeleton.dtsi"
-
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         interrupt-parent = <&gic>;
 
         cpus {
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index 118135d75899..c47380763cae 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -11,9 +11,9 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/include/ "skeleton.dtsi"
-
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         interrupt-parent = <&vic>;
 
         cpus {
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index 00166eb9be86..0a634fb07452 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -9,9 +9,9 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/include/ "skeleton.dtsi"
-
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "st,spear600";
 
         cpus {
diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts
index 12afdc7467e7..04066f9cb8a3 100644
--- a/arch/arm/boot/dts/ste-nomadik-nhk15.dts
+++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts
@@ -1,7 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree for the ST-Ericsson Nomadik S8815 board
- * Produced by Calao Systems
+ * Device Tree for the ST Microelectronics Nomadik NHK8815 board
  */
 
 /dts-v1/;
@@ -182,43 +181,12 @@
                         pinctrl-names = "default";
                         pinctrl-0 = <&clcd_24bit_mux>;
                         port {
-                                nomadik_clcd_pads: endpoint {
+                                nomadik_clcd: endpoint {
                                         remote-endpoint = <&nomadik_clcd_panel>;
                                         arm,pl11x,tft-r0g0b0-pads = <16 8 0>;
                                 };
                         };
 
-                        /*
-                         * WVGA connector 21
-                         * WVGA (800x480): 4.3" TPG110 TDO43MTEA2 24-bit RGB
-                         * with TPO touch screen.
-                         */
-                        panel {
-                                compatible = "tpo,tpg110", "panel-dpi";
-                                grestb-gpios = <&stmpe_gpio44 5 GPIO_ACTIVE_LOW>;
-                                scen-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
-                                scl-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
-                                sda-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
-                                backlight = <&bl>;
-
-                                port {
-                                        nomadik_clcd_panel: endpoint {
-                                                remote-endpoint = <&nomadik_clcd_pads>;
-                                        };
-                                };
-
-                                panel-timing {
-                                        clock-frequency = <33200000>;
-                                        hactive = <800>;
-                                        hback-porch = <216>;
-                                        hfront-porch = <40>;
-                                        hsync-len = <1>;
-                                        vactive = <480>;
-                                        vback-porch = <35>;
-                                        vfront-porch = <10>;
-                                        vsync-len = <1>;
-                                };
-                        };
                 };
 
                 /* Activate RX/TX and CTS/RTS on UART 0 */
@@ -233,6 +201,55 @@
                 };
         };
 
+        spi {
+                compatible = "spi-gpio";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                /*
+                 * As we're dealing with 3wire SPI, we only define SCK
+                 * and MOSI (in the spec MOSI is called "SDA").
+                 */
+                gpio-sck = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+                gpio-mosi = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+                /*
+                 * It's not actually active high, but the frameworks assume
+                 * the polarity of the passed-in GPIO is "normal" (active
+                 * high) then actively drives the line low to select the
+                 * chip.
+                 */
+                cs-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+                num-chipselects = <1>;
+
+                /*
+                 * WVGA connector 21
+                 * WVGA (800x480): 4.3" TPG110 TDO43MTEA2 24-bit RGB
+                 * with TPO touch screen.
+                  */
+                panel: display@0 {
+                        /*
+                         * The TPO display driver is connected to a
+                         * 5.7" OSD OSD057VA01CT TFT display.
+                         */
+                        compatible = "tpo,tpg110";
+                        reg = <0>;
+                        spi-3wire;
+                        /* 320 ns min period ~= 3 MHz */
+                        spi-max-frequency = <3000000>;
+                        /* Width and height from the OSD data sheet */
+                        width-mm = <116>;
+                        height-mm = <87>;
+                        grestb-gpios = <&stmpe_gpio44 5 GPIO_ACTIVE_LOW>;
+                        backlight = <&bl>;
+
+                        port {
+                                nomadik_clcd_panel: endpoint {
+                                        remote-endpoint = <&nomadik_clcd>;
+                                };
+                        };
+                };
+        };
+
         bl: backlight {
                 compatible = "pwm-backlight";
                 pwms = <&stmpe0_pwm 0 500000>;
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index fca76a696d9d..f78b4eabd68c 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -4,13 +4,13 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
-#include "skeleton.dtsi"
 
 / {
         #address-cells = <1>;
         #size-cells = <1>;
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x04000000>,
                     <0x08000000 0x04000000>;
         };
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 1bd1aba3322f..f4e7660fead7 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -4,7 +4,6 @@
  */
 
 /dts-v1/;
-/include/ "skeleton.dtsi"
 
 / {
         model = "ST-Ericsson U300";
@@ -22,6 +21,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x48000000 0x03c00000>;
         };
 
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index ed7d7f46465e..73ea84df7bf4 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -61,6 +61,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x2000000>;
         };
 
diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts
index 8c081eaf20fe..d90b0d1e18c7 100644
--- a/arch/arm/boot/dts/stm32746g-eval.dts
+++ b/arch/arm/boot/dts/stm32746g-eval.dts
@@ -55,6 +55,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0xc0000000 0x2000000>;
         };
 
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts
index 5ceb2cf3777f..e19d0fe7dbda 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -60,6 +60,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x90000000 0x800000>;
         };
 
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 8d6f028ae285..588b6ef94e93 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -45,12 +45,14 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include "skeleton.dtsi"
 #include "armv7-m.dtsi"
 #include <dt-bindings/clock/stm32fx-clock.h>
 #include <dt-bindings/mfd/stm32f4-rcc.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
         clocks {
                 clk_hse: clk-hse {
                         #clock-cells = <0>;
@@ -314,6 +316,26 @@
                         status = "disabled";
                 };
 
+                spi2: spi@40003800 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "st,stm32f4-spi";
+                        reg = <0x40003800 0x400>;
+                        interrupts = <36>;
+                        clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
+                        status = "disabled";
+                };
+
+                spi3: spi@40003c00 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "st,stm32f4-spi";
+                        reg = <0x40003c00 0x400>;
+                        interrupts = <51>;
+                        clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
+                        status = "disabled";
+                };
+
                 usart2: serial@40004400 {
                         compatible = "st,stm32-uart";
                         reg = <0x40004400 0x400>;
@@ -523,6 +545,26 @@
                         status = "disabled";
                 };
 
+                spi1: spi@40013000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "st,stm32f4-spi";
+                        reg = <0x40013000 0x400>;
+                        interrupts = <35>;
+                        clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
+                        status = "disabled";
+                };
+
+                spi4: spi@40013400 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "st,stm32f4-spi";
+                        reg = <0x40013400 0x400>;
+                        interrupts = <84>;
+                        clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
+                        status = "disabled";
+                };
+
                 syscfg: system-config@40013800 {
                         compatible = "syscon";
                         reg = <0x40013800 0x400>;
@@ -587,6 +629,26 @@
                         };
                 };
 
+                spi5: spi@40015000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "st,stm32f4-spi";
+                        reg = <0x40015000 0x400>;
+                        interrupts = <85>;
+                        clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
+                        status = "disabled";
+                };
+
+                spi6: spi@40015400 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "st,stm32f4-spi";
+                        reg = <0x40015400 0x400>;
+                        interrupts = <86>;
+                        clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
+                        status = "disabled";
+                };
+
                 pwrcfg: power-config@40007000 {
                         compatible = "syscon";
                         reg = <0x40007000 0x400>;
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index 7937b43d7788..a3ff04940aec 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -61,6 +61,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x1000000>;
         };
 
diff --git a/arch/arm/boot/dts/stm32f746-disco.dts b/arch/arm/boot/dts/stm32f746-disco.dts
index e3a7bd338d61..0ba9c5b08ab9 100644
--- a/arch/arm/boot/dts/stm32f746-disco.dts
+++ b/arch/arm/boot/dts/stm32f746-disco.dts
@@ -56,6 +56,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0xC0000000 0x800000>;
         };
 
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index f48d06a80d1d..a25b7000a3a1 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -40,12 +40,14 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include "skeleton.dtsi"
 #include "armv7-m.dtsi"
 #include <dt-bindings/clock/stm32fx-clock.h>
 #include <dt-bindings/mfd/stm32f7-rcc.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
         clocks {
                 clk_hse: clk-hse {
                         #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts
index 483d896e2bc1..3c7216844a9b 100644
--- a/arch/arm/boot/dts/stm32f769-disco.dts
+++ b/arch/arm/boot/dts/stm32f769-disco.dts
@@ -56,6 +56,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0xC0000000 0x1000000>;
         };
 
diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
index 24be8e63dec8..980b2769caf9 100644
--- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
@@ -173,6 +173,21 @@
                                 };
                         };
 
+                        ethernet_rmii: rmii@0 {
+                                pins {
+                                        pinmux = <STM32_PINMUX('G', 11, AF11)>,
+                                                 <STM32_PINMUX('G', 13, AF11)>,
+                                                 <STM32_PINMUX('G', 12, AF11)>,
+                                                 <STM32_PINMUX('C', 4, AF11)>,
+                                                 <STM32_PINMUX('C', 5, AF11)>,
+                                                 <STM32_PINMUX('A', 7, AF11)>,
+                                                 <STM32_PINMUX('C', 1, AF11)>,
+                                                 <STM32_PINMUX('A', 2, AF11)>,
+                                                 <STM32_PINMUX('A', 1, AF11)>;
+                                        slew-rate = <2>;
+                                };
+                        };
+
                         usart1_pins: usart1@0 {
                                 pins1 {
                                         pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index cbdd69ca9e7a..5cac79ebebb1 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -40,13 +40,15 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include "skeleton.dtsi"
 #include "armv7-m.dtsi"
 #include <dt-bindings/clock/stm32h7-clks.h>
 #include <dt-bindings/mfd/stm32h7-rcc.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
         clocks {
                 clk_hse: clk-hse {
                         #clock-cells = <0>;
@@ -511,6 +513,19 @@
                                 status = "disabled";
                         };
                 };
+
+                mac: ethernet@40028000 {
+                        compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
+                        reg = <0x40028000 0x8000>;
+                        reg-names = "stmmaceth";
+                        interrupts = <61>;
+                        interrupt-names = "macirq";
+                        clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
+                        clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>;
+                        st,syscon = <&syscfg 0x4>;
+                        snps,pbl = <8>;
+                        status = "disabled";
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/stm32h743i-disco.dts
index 45e088c55741..dd06c8f3d09a 100644
--- a/arch/arm/boot/dts/stm32h743i-disco.dts
+++ b/arch/arm/boot/dts/stm32h743i-disco.dts
@@ -54,6 +54,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0xd0000000 0x2000000>;
         };
 
@@ -66,6 +67,23 @@
         clock-frequency = <25000000>;
 };
 
+&mac {
+        status = "disabled";
+        pinctrl-0       = <&ethernet_rmii>;
+        pinctrl-names   = "default";
+        phy-mode        = "rmii";
+        phy-handle      = <&phy0>;
+
+        mdio0 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "snps,dwmac-mdio";
+                phy0: ethernet-phy@0 {
+                        reg = <0>;
+                };
+        };
+};
+
 &usart2 {
         pinctrl-0 = <&usart2_pins>;
         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts
index 3f8e0c4a998d..ebc3f0933f5c 100644
--- a/arch/arm/boot/dts/stm32h743i-eval.dts
+++ b/arch/arm/boot/dts/stm32h743i-eval.dts
@@ -54,6 +54,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0xd0000000 0x2000000>;
         };
 
@@ -104,6 +105,23 @@
         status = "okay";
 };
 
+&mac {
+        status = "disabled";
+        pinctrl-0       = <&ethernet_rmii>;
+        pinctrl-names   = "default";
+        phy-mode        = "rmii";
+        phy-handle      = <&phy0>;
+
+        mdio0 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "snps,dwmac-mdio";
+                phy0: ethernet-phy@0 {
+                        reg = <0>;
+                };
+        };
+};
+
 &usart1 {
         pinctrl-0 = <&usart1_pins>;
         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
index c4851271e810..9ec4694e93a7 100644
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -246,6 +246,13 @@
                                 };
                         };
 
+                        m_can1_sleep_pins_a: m_can1-sleep@0 {
+                                pins {
+                                        pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
+                                                 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
+                                };
+                        };
+
                         pwm2_pins_a: pwm2-0 {
                                 pins {
                                         pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts
index f77bea49c079..d66edb0c66cd 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -17,6 +17,7 @@
         };
 
         memory@c0000000 {
+                device_type = "memory";
                 reg = <0xC0000000 0x40000000>;
         };
 
@@ -49,6 +50,10 @@
         };
 };
 
+&dts {
+        status = "okay";
+};
+
 &i2c4 {
         pinctrl-names = "default";
         pinctrl-0 = <&i2c4_pins_a>;
@@ -72,6 +77,9 @@
 
 &timers6 {
         status = "okay";
+        /* spare dmas for other usage */
+        /delete-property/dmas;
+        /delete-property/dma-names;
         timer@5 {
                 status = "okay";
         };
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
index 063ee8ac5dcb..b6aca40b9b90 100644
--- a/arch/arm/boot/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
@@ -124,8 +124,9 @@
 };
 
 &m_can1 {
-        pinctrl-names = "default";
+        pinctrl-names = "default", "sleep";
         pinctrl-0 = <&m_can1_pins_a>;
+        pinctrl-1 = <&m_can1_sleep_pins_a>;
         status = "okay";
 };
 
@@ -161,6 +162,9 @@
 };
 
 &timers2 {
+        /* spare dmas for other usage (un-delete to enable pwm capture) */
+        /delete-property/dmas;
+        /delete-property/dma-names;
         status = "disabled";
         pwm {
                 pinctrl-0 = <&pwm2_pins_a>;
@@ -173,6 +177,8 @@
 };
 
 &timers8 {
+        /delete-property/dmas;
+        /delete-property/dma-names;
         status = "disabled";
         pwm {
                 pinctrl-0 = <&pwm8_pins_a>;
@@ -185,6 +191,8 @@
 };
 
 &timers12 {
+        /delete-property/dmas;
+        /delete-property/dma-names;
         status = "disabled";
         pwm {
                 pinctrl-0 = <&pwm12_pins_a>;
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
index 8bf1c17f8cef..f8bbfff5950b 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -84,6 +84,31 @@
                 };
         };
 
+        thermal-zones {
+                cpu_thermal: cpu-thermal {
+                        polling-delay-passive = <0>;
+                        polling-delay = <0>;
+                        thermal-sensors = <&dts>;
+
+                        trips {
+                                cpu_alert1: cpu-alert1 {
+                                        temperature = <85000>;
+                                        hysteresis = <0>;
+                                        type = "passive";
+                                };
+
+                                cpu-crit {
+                                        temperature = <120000>;
+                                        hysteresis = <0>;
+                                        type = "critical";
+                                };
+                        };
+
+                        cooling-maps {
+                        };
+                };
+        };
+
         soc {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -98,6 +123,12 @@
                         reg = <0x40000000 0x400>;
                         clocks = <&rcc TIM2_K>;
                         clock-names = "int";
+                        dmas = <&dmamux1 18 0x400 0x1>,
+                               <&dmamux1 19 0x400 0x1>,
+                               <&dmamux1 20 0x400 0x1>,
+                               <&dmamux1 21 0x400 0x1>,
+                               <&dmamux1 22 0x400 0x1>;
+                        dma-names = "ch1", "ch2", "ch3", "ch4", "up";
                         status = "disabled";
 
                         pwm {
@@ -119,6 +150,13 @@
                         reg = <0x40001000 0x400>;
                         clocks = <&rcc TIM3_K>;
                         clock-names = "int";
+                        dmas = <&dmamux1 23 0x400 0x1>,
+                               <&dmamux1 24 0x400 0x1>,
+                               <&dmamux1 25 0x400 0x1>,
+                               <&dmamux1 26 0x400 0x1>,
+                               <&dmamux1 27 0x400 0x1>,
+                               <&dmamux1 28 0x400 0x1>;
+                        dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
                         status = "disabled";
 
                         pwm {
@@ -140,6 +178,11 @@
                         reg = <0x40002000 0x400>;
                         clocks = <&rcc TIM4_K>;
                         clock-names = "int";
+                        dmas = <&dmamux1 29 0x400 0x1>,
+                               <&dmamux1 30 0x400 0x1>,
+                               <&dmamux1 31 0x400 0x1>,
+                               <&dmamux1 32 0x400 0x1>;
+                        dma-names = "ch1", "ch2", "ch3", "ch4";
                         status = "disabled";
 
                         pwm {
@@ -161,6 +204,13 @@
                         reg = <0x40003000 0x400>;
                         clocks = <&rcc TIM5_K>;
                         clock-names = "int";
+                        dmas = <&dmamux1 55 0x400 0x1>,
+                               <&dmamux1 56 0x400 0x1>,
+                               <&dmamux1 57 0x400 0x1>,
+                               <&dmamux1 58 0x400 0x1>,
+                               <&dmamux1 59 0x400 0x1>,
+                               <&dmamux1 60 0x400 0x1>;
+                        dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
                         status = "disabled";
 
                         pwm {
@@ -182,6 +232,8 @@
                         reg = <0x40004000 0x400>;
                         clocks = <&rcc TIM6_K>;
                         clock-names = "int";
+                        dmas = <&dmamux1 69 0x400 0x1>;
+                        dma-names = "up";
                         status = "disabled";
 
                         timer@5 {
@@ -198,6 +250,8 @@
                         reg = <0x40005000 0x400>;
                         clocks = <&rcc TIM7_K>;
                         clock-names = "int";
+                        dmas = <&dmamux1 70 0x400 0x1>;
+                        dma-names = "up";
                         status = "disabled";
 
                         timer@6 {
@@ -465,6 +519,15 @@
                         reg = <0x44000000 0x400>;
                         clocks = <&rcc TIM1_K>;
                         clock-names = "int";
+                        dmas = <&dmamux1 11 0x400 0x1>,
+                               <&dmamux1 12 0x400 0x1>,
+                               <&dmamux1 13 0x400 0x1>,
+                               <&dmamux1 14 0x400 0x1>,
+                               <&dmamux1 15 0x400 0x1>,
+                               <&dmamux1 16 0x400 0x1>,
+                               <&dmamux1 17 0x400 0x1>;
+                        dma-names = "ch1", "ch2", "ch3", "ch4",
+                                    "up", "trig", "com";
                         status = "disabled";
 
                         pwm {
@@ -486,6 +549,15 @@
                         reg = <0x44001000 0x400>;
                         clocks = <&rcc TIM8_K>;
                         clock-names = "int";
+                        dmas = <&dmamux1 47 0x400 0x1>,
+                               <&dmamux1 48 0x400 0x1>,
+                               <&dmamux1 49 0x400 0x1>,
+                               <&dmamux1 50 0x400 0x1>,
+                               <&dmamux1 51 0x400 0x1>,
+                               <&dmamux1 52 0x400 0x1>,
+                               <&dmamux1 53 0x400 0x1>;
+                        dma-names = "ch1", "ch2", "ch3", "ch4",
+                                    "up", "trig", "com";
                         status = "disabled";
 
                         pwm {
@@ -543,6 +615,11 @@
                         reg = <0x44006000 0x400>;
                         clocks = <&rcc TIM15_K>;
                         clock-names = "int";
+                        dmas = <&dmamux1 105 0x400 0x1>,
+                               <&dmamux1 106 0x400 0x1>,
+                               <&dmamux1 107 0x400 0x1>,
+                               <&dmamux1 108 0x400 0x1>;
+                        dma-names = "ch1", "up", "trig", "com";
                         status = "disabled";
 
                         pwm {
@@ -564,6 +641,9 @@
                         reg = <0x44007000 0x400>;
                         clocks = <&rcc TIM16_K>;
                         clock-names = "int";
+                        dmas = <&dmamux1 109 0x400 0x1>,
+                               <&dmamux1 110 0x400 0x1>;
+                        dma-names = "ch1", "up";
                         status = "disabled";
 
                         pwm {
@@ -584,6 +664,9 @@
                         reg = <0x44008000 0x400>;
                         clocks = <&rcc TIM17_K>;
                         clock-names = "int";
+                        dmas = <&dmamux1 111 0x400 0x1>,
+                               <&dmamux1 112 0x400 0x1>;
+                        dma-names = "ch1", "up";
                         status = "disabled";
 
                         pwm {
@@ -684,14 +767,14 @@
 
                 m_can1: can@4400e000 {
                         compatible = "bosch,m_can";
-                        reg = <0x4400e000 0x400>, <0x44011000 0x2800>;
+                        reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
                         reg-names = "m_can", "message_ram";
                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "int0", "int1";
                         clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
                         clock-names = "hclk", "cclk";
-                        bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
+                        bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
                         status = "disabled";
                 };
 
@@ -908,6 +991,16 @@
                         status = "disabled";
                 };
 
+                dts: thermal@50028000 {
+                        compatible = "st,stm32-thermal";
+                        reg = <0x50028000 0x100>;
+                        interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&rcc TMPSENS>;
+                        clock-names = "pclk";
+                        #thermal-sensor-cells = <0>;
+                        status = "disabled";
+                };
+
                 cryp1: cryp@54001000 {
                         compatible = "st,stm32mp1-cryp";
                         reg = <0x54001000 0x400>;
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 5d46bb0139fa..73c3ac42095f 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -184,6 +184,26 @@
                 status = "disabled";
         };
 
+        pmu {
+                compatible = "arm,cortex-a8-pmu";
+                interrupts = <3>;
+        };
+
+        reserved-memory {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
+                default-pool {
+                        compatible = "shared-dma-pool";
+                        size = <0x6000000>;
+                        alloc-ranges = <0x4a000000 0x6000000>;
+                        reusable;
+                        linux,cma-default;
+                };
+        };
+
         soc {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -224,6 +244,19 @@
                                         status = "disabled";
                                 };
                         };
+
+                        sram_c: sram@1d00000 {
+                                compatible = "mmio-sram";
+                                reg = <0x01d00000 0xd0000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x01d00000 0xd0000>;
+
+                                ve_sram: sram-section@0 {
+                                        compatible = "allwinner,sun4i-a10-sram-c1";
+                                        reg = <0x000000 0x80000>;
+                                };
+                        };
                 };
 
                 dma: dma-controller@1c02000 {
@@ -394,6 +427,17 @@
                         };
                 };
 
+                video-codec@1c0e000 {
+                        compatible = "allwinner,sun4i-a10-video-engine";
+                        reg = <0x01c0e000 0x1000>;
+                        clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
+                                 <&ccu CLK_DRAM_VE>;
+                        clock-names = "ahb", "mod", "ram";
+                        resets = <&ccu RST_VE>;
+                        interrupts = <53>;
+                        allwinner,sram = <&ve_sram 1>;
+                };
+
                 mmc0: mmc@1c0f000 {
                         compatible = "allwinner,sun4i-a10-mmc";
                         reg = <0x01c0f000 0x1000>;
diff --git a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts
index a89f29fa3e40..7257f39b31ce 100644
--- a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts
+++ b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts
@@ -49,14 +49,15 @@
         compatible = "allwinner,q8-a13", "allwinner,sun5i-a13";
 
         panel: panel {
-                compatible = "urt,umsh-8596md-t", "simple-panel";
+                compatible = "bananapi,s070wv20-ct16", "simple-panel";
+                power-supply = <&reg_vcc3v3>;
+                enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */
+                backlight = <&backlight>;
                 #address-cells = <1>;
                 #size-cells = <0>;
 
                 port@0 {
                         reg = <0>;
-                        /* TODO: lcd panel uses axp gpio0 as enable pin */
-                        backlight = <&backlight>;
                         #address-cells = <1>;
                         #size-cells = <0>;
 
diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
index 6202aabedbfe..5b1f0e198eb6 100644
--- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
@@ -54,7 +54,7 @@
                 pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
                 brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
                 default-brightness-level = <8>;
-                /* TODO: backlight uses axp gpio1 as enable pin */
+                enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; /* AXP GPIO1 */
         };
 
         chosen {
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 353d90f99b40..13304b8c5139 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -216,6 +216,7 @@
                         #clock-cells = <0>;
                         compatible = "fixed-clock";
                         clock-frequency = <24000000>;
+                        clock-output-names = "osc24M";
                 };
 
                 osc32k: clk-32k {
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
index 556b1b591c5d..81bc85d398c1 100644
--- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
@@ -191,6 +191,11 @@
 };
 
 &pio {
+        vcc-pa-supply = <&reg_vcc3v3>;
+        vcc-pc-supply = <&reg_vcc3v3>;
+        vcc-pe-supply = <&reg_vcc3v3>;
+        vcc-pf-supply = <&reg_vcc3v3>;
+        vcc-pg-supply = <&reg_vcc3v3>;
         gpio-line-names =
                 /* PA */
                 "ERXD3", "ERXD2", "ERXD1", "ERXD0", "ETXD3",
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index a9c123de5d2c..43fe215e83ea 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -68,6 +68,12 @@
                 };
         };
 
+        de: display-engine {
+                /* compatible gets set in SoC specific dtsi file */
+                allwinner,pipelines = <&fe0>;
+                status = "disabled";
+        };
+
         timer {
                 compatible = "arm,armv7-timer";
                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -155,6 +161,55 @@
                         #dma-cells = <1>;
                 };
 
+                nfc: nand@1c03000 {
+                        compatible = "allwinner,sun4i-a10-nand";
+                        reg = <0x01c03000 0x1000>;
+                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
+                        clock-names = "ahb", "mod";
+                        resets = <&ccu RST_BUS_NAND>;
+                        reset-names = "ahb";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                tcon0: lcd-controller@1c0c000 {
+                        /* compatible gets set in SoC specific dtsi file */
+                        reg = <0x01c0c000 0x1000>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_LCD>,
+                                 <&ccu CLK_LCD_CH0>;
+                        clock-names = "ahb",
+                                      "tcon-ch0";
+                        clock-output-names = "tcon-pixel-clock";
+                        resets = <&ccu RST_BUS_LCD>;
+                        reset-names = "lcd";
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                tcon0_in: port@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0>;
+
+                                        tcon0_in_drc0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&drc0_out_tcon0>;
+                                        };
+                                };
+
+                                tcon0_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+                                };
+                        };
+                };
+
                 mmc0: mmc@1c0f000 {
                         compatible = "allwinner,sun7i-a20-mmc";
                         reg = <0x01c0f000 0x1000>;
@@ -214,21 +269,6 @@
                         #size-cells = <0>;
                 };
 
-                nfc: nand@1c03000 {
-                        compatible = "allwinner,sun4i-a10-nand";
-                        reg = <0x01c03000 0x1000>;
-                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
-                        clock-names = "ahb", "mod";
-                        resets = <&ccu RST_BUS_NAND>;
-                        reset-names = "ahb";
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>;
-                        status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                };
-
                 usb_otg: usb@1c19000 {
                         /* compatible gets set in SoC specific dtsi file */
                         reg = <0x01c19000 0x0400>;
@@ -572,6 +612,111 @@
                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
                 };
 
+                fe0: display-frontend@1e00000 {
+                        /* compatible gets set in SoC specific dtsi file */
+                        reg = <0x01e00000 0x20000>;
+                        interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
+                                 <&ccu CLK_DRAM_DE_FE>;
+                        clock-names = "ahb", "mod",
+                                      "ram";
+                        resets = <&ccu RST_BUS_DE_FE>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                fe0_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        fe0_out_be0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&be0_in_fe0>;
+                                        };
+                                };
+                        };
+                };
+
+                be0: display-backend@1e60000 {
+                        /* compatible gets set in SoC specific dtsi file */
+                        reg = <0x01e60000 0x10000>;
+                        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
+                                 <&ccu CLK_DRAM_DE_BE>;
+                        clock-names = "ahb", "mod",
+                                      "ram";
+                        resets = <&ccu RST_BUS_DE_BE>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                be0_in: port@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0>;
+
+                                        be0_in_fe0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&fe0_out_be0>;
+                                        };
+                                };
+
+                                be0_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        be0_out_drc0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&drc0_in_be0>;
+                                        };
+                                };
+                        };
+                };
+
+                drc0: drc@1e70000 {
+                        /* compatible gets set in SoC specific dtsi file */
+                        reg = <0x01e70000 0x10000>;
+                        interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
+                                 <&ccu CLK_DRAM_DRC>;
+                        clock-names = "ahb", "mod", "ram";
+                        resets = <&ccu RST_BUS_DRC>;
+
+                        assigned-clocks = <&ccu CLK_DRC>;
+                        assigned-clock-rates = <300000000>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                drc0_in: port@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0>;
+
+                                        drc0_in_be0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&be0_out_drc0>;
+                                        };
+                                };
+
+                                drc0_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        drc0_out_tcon0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&tcon0_in_drc0>;
+                                        };
+                                };
+                        };
+                };
+
                 rtc: rtc@1f00000 {
                         compatible = "allwinner,sun8i-a23-rtc";
                         reg = <0x01f00000 0x400>;
diff --git a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts
index b6958e8f2f01..d4dab7c28398 100644
--- a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts
+++ b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts
@@ -61,3 +61,7 @@
                 "Headset Mic", "HBIAS";
         status = "okay";
 };
+
+&panel {
+        compatible = "bananapi,s070wv20-ct16", "simple-panel";
+};
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index d00055e9eef5..a5e884a8b2ae 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -62,10 +62,26 @@
         };
 };
 
+&be0 {
+        compatible = "allwinner,sun8i-a23-display-backend";
+};
+
 &ccu {
         compatible = "allwinner,sun8i-a23-ccu";
 };
 
+&de {
+        compatible = "allwinner,sun8i-a23-display-engine";
+};
+
+&drc0 {
+        compatible = "allwinner,sun8i-a23-drc";
+};
+
+&fe0 {
+        compatible = "allwinner,sun8i-a23-display-frontend";
+};
+
 &pio {
         compatible = "allwinner,sun8i-a23-pinctrl";
         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
@@ -73,6 +89,10 @@
                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 };
 
+&tcon0 {
+        compatible = "allwinner,sun8i-a23-tcon";
+};
+
 &usb_otg {
         compatible = "allwinner,sun6i-a31-musb";
 };
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index 626152c30f50..1111a6498102 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -159,12 +159,6 @@
                 };
         };
 
-        de: display-engine {
-                compatible = "allwinner,sun8i-a33-display-engine";
-                allwinner,pipelines = <&fe0>;
-                status = "disabled";
-        };
-
         iio-hwmon {
                 compatible = "iio-hwmon";
                 io-channels = <&ths>;
@@ -209,47 +203,6 @@
         };
 
         soc {
-                tcon0: lcd-controller@1c0c000 {
-                        compatible = "allwinner,sun8i-a33-tcon";
-                        reg = <0x01c0c000 0x1000>;
-                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ccu CLK_BUS_LCD>,
-                                 <&ccu CLK_LCD_CH0>;
-                        clock-names = "ahb",
-                                      "tcon-ch0";
-                        clock-output-names = "tcon-pixel-clock";
-                        resets = <&ccu RST_BUS_LCD>;
-                        reset-names = "lcd";
-                        status = "disabled";
-
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                tcon0_in: port@0 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <0>;
-
-                                        tcon0_in_drc0: endpoint@0 {
-                                                reg = <0>;
-                                                remote-endpoint = <&drc0_out_tcon0>;
-                                        };
-                                };
-
-                                tcon0_out: port@1 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <1>;
-
-                                        tcon0_out_dsi: endpoint@1 {
-                                                reg = <1>;
-                                                remote-endpoint = <&dsi_in_tcon0>;
-                                        };
-                                };
-                        };
-                };
-
                 video-codec@1c0e000 {
                         compatible = "allwinner,sun8i-a33-video-engine";
                         reg = <0x01c0e000 0x1000>;
@@ -339,115 +292,6 @@
                         status = "disabled";
                         #phy-cells = <0>;
                 };
-
-                fe0: display-frontend@1e00000 {
-                        compatible = "allwinner,sun8i-a33-display-frontend";
-                        reg = <0x01e00000 0x20000>;
-                        interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
-                                 <&ccu CLK_DRAM_DE_FE>;
-                        clock-names = "ahb", "mod",
-                                      "ram";
-                        resets = <&ccu RST_BUS_DE_FE>;
-
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                fe0_out: port@1 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <1>;
-
-                                        fe0_out_be0: endpoint@0 {
-                                                reg = <0>;
-                                                remote-endpoint = <&be0_in_fe0>;
-                                        };
-                                };
-                        };
-                };
-
-                be0: display-backend@1e60000 {
-                        compatible = "allwinner,sun8i-a33-display-backend";
-                        reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
-                        reg-names = "be", "sat";
-                        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
-                                 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
-                        clock-names = "ahb", "mod",
-                                      "ram", "sat";
-                        resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
-                        reset-names = "be", "sat";
-                        assigned-clocks = <&ccu CLK_DE_BE>;
-                        assigned-clock-rates = <300000000>;
-
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                be0_in: port@0 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <0>;
-
-                                        be0_in_fe0: endpoint@0 {
-                                                reg = <0>;
-                                                remote-endpoint = <&fe0_out_be0>;
-                                        };
-                                };
-
-                                be0_out: port@1 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <1>;
-
-                                        be0_out_drc0: endpoint@0 {
-                                                reg = <0>;
-                                                remote-endpoint = <&drc0_in_be0>;
-                                        };
-                                };
-                        };
-                };
-
-                drc0: drc@1e70000 {
-                        compatible = "allwinner,sun8i-a33-drc";
-                        reg = <0x01e70000 0x10000>;
-                        interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
-                                 <&ccu CLK_DRAM_DRC>;
-                        clock-names = "ahb", "mod", "ram";
-                        resets = <&ccu RST_BUS_DRC>;
-
-                        assigned-clocks = <&ccu CLK_DRC>;
-                        assigned-clock-rates = <300000000>;
-
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                drc0_in: port@0 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <0>;
-
-                                        drc0_in_be0: endpoint@0 {
-                                                reg = <0>;
-                                                remote-endpoint = <&be0_out_drc0>;
-                                        };
-                                };
-
-                                drc0_out: port@1 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <1>;
-
-                                        drc0_out_tcon0: endpoint@0 {
-                                                reg = <0>;
-                                                remote-endpoint = <&tcon0_in_drc0>;
-                                        };
-                                };
-                        };
-                };
         };
 
         thermal-zones {
@@ -524,10 +368,37 @@
         };
 };
 
+&be0 {
+        compatible = "allwinner,sun8i-a33-display-backend";
+        /* A33 has an extra "SAT" module packed inside the display backend */
+        reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
+        reg-names = "be", "sat";
+        clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
+                 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
+        clock-names = "ahb", "mod",
+                      "ram", "sat";
+        resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
+        reset-names = "be", "sat";
+        assigned-clocks = <&ccu CLK_DE_BE>;
+        assigned-clock-rates = <300000000>;
+};
+
 &ccu {
         compatible = "allwinner,sun8i-a33-ccu";
 };
 
+&de {
+        compatible = "allwinner,sun8i-a33-display-engine";
+};
+
+&drc0 {
+        compatible = "allwinner,sun8i-a33-drc";
+};
+
+&fe0 {
+        compatible = "allwinner,sun8i-a33-display-frontend";
+};
+
 &mali {
         operating-points-v2 = <&mali_opp_table>;
 };
@@ -544,6 +415,17 @@
 
 };
 
+&tcon0 {
+        compatible = "allwinner,sun8i-a33-tcon";
+};
+
+&tcon0_out {
+        tcon0_out_dsi: endpoint@1 {
+                reg = <1>;
+                remote-endpoint = <&dsi_in_tcon0>;
+        };
+};
+
 &usb_otg {
         compatible = "allwinner,sun8i-a33-musb";
 };
diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
index 1c012a4def16..9c006fc18821 100644
--- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -154,6 +154,10 @@
 
 #include "axp81x.dtsi"
 
+&ac_power_supply {
+        status = "okay";
+};
+
 &reg_aldo1 {
         regulator-always-on;
         regulator-min-microvolt = <1800000>;
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 7d30d3e530fb..838be7b3715f 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -237,6 +237,14 @@
 
 #include "axp81x.dtsi"
 
+&ac_power_supply {
+        status = "okay";
+};
+
+&battery_power_supply {
+        status = "okay";
+};
+
 &reg_aldo1 {
         regulator-always-on;
         regulator-min-microvolt = <1800000>;
diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
index a5a9f5a0603e..fcbec3d7ccd7 100644
--- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
@@ -247,6 +247,14 @@
 
 #include "axp81x.dtsi"
 
+&ac_power_supply {
+        status = "okay";
+};
+
+&battery_power_supply {
+        status = "okay";
+};
+
 &reg_aldo1 {
         regulator-always-on;
         regulator-min-microvolt = <1800000>;
diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
index 5d23667dc2d2..25540b7694d5 100644
--- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
@@ -53,7 +53,7 @@
 
         aliases {
                 serial0 = &uart0;
-                /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+                ethernet0 = &emac;
                 ethernet1 = &sdiowifi;
         };
 
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
index 65cba1050802..4ec94d72f021 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
@@ -67,6 +67,21 @@
                 pinctrl-names = "default";
                 reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
         };
+
+        connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+};
+
+&de {
+        status = "okay";
 };
 
 &ehci1 {
@@ -94,6 +109,16 @@
         };
 };
 
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &ir {
         pinctrl-names = "default";
         pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi b/arch/arm/boot/dts/sun8i-q8-common.dtsi
index 719ad769b837..53104f4ccacc 100644
--- a/arch/arm/boot/dts/sun8i-q8-common.dtsi
+++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi
@@ -49,6 +49,26 @@
                 ethernet0 = &sdio_wifi;
         };
 
+        panel: panel {
+                /* Tablet dts should provide panel compatible */
+                backlight = <&backlight>;
+                enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+                power-supply = <&reg_dc1sw>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                        reg = <0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        panel_input: endpoint@0 {
+                                reg = <0>;
+                                remote-endpoint = <&tcon0_out_lcd>;
+                        };
+                };
+        };
+
         wifi_pwrseq: wifi_pwrseq {
                 compatible = "mmc-pwrseq-simple";
                 /*
@@ -64,6 +84,10 @@
         };
 };
 
+&de {
+        status = "okay";
+};
+
 &ehci0 {
         status  = "okay";
 };
@@ -90,6 +114,19 @@
         };
 };
 
+&tcon0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&lcd_rgb666_pins>;
+        status = "okay";
+};
+
+&tcon0_out {
+        tcon0_out_lcd: endpoint@0 {
+                reg = <0>;
+                remote-endpoint = <&panel_input>;
+        };
+};
+
 &usbphy {
         usb1_vbus-supply = <&reg_dldo1>;
 };
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index 438b7b44dab3..c488aaacbd68 100644
--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -102,6 +102,8 @@
         wifi_pwrseq: wifi_pwrseq {
                 compatible = "mmc-pwrseq-simple";
                 reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
+                clocks = <&ccu CLK_OUTA>;
+                clock-names = "ext_clock";
         };
 };
 
@@ -196,6 +198,11 @@
         status = "okay";
 };
 
+&pio {
+        pinctrl-names = "default";
+        pinctrl-0 = <&clk_out_a_pin>;
+};
+
 &reg_aldo2 {
         regulator-always-on;
         regulator-min-microvolt = <2500000>;
@@ -250,12 +257,27 @@
         regulator-name = "vcc-wifi-io";
 };
 
+/*
+ * Our WiFi chip needs both DLDO2 and DLDO3 to be powered at the same
+ * time, with the two being in sync, to be able to meet maximum power
+ * consumption during transmits. Since this is not really supported
+ * right now, just use the two as always on, and we will fix it later.
+ */
+
 &reg_dldo2 {
+        regulator-always-on;
         regulator-min-microvolt = <3300000>;
         regulator-max-microvolt = <3300000>;
         regulator-name = "vcc-wifi";
 };
 
+&reg_dldo3 {
+        regulator-always-on;
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-wifi-2";
+};
+
 &reg_dldo4 {
         regulator-min-microvolt = <2500000>;
         regulator-max-microvolt = <2500000>;
@@ -278,6 +300,25 @@
         status = "okay";
 };
 
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>;
+        uart-has-rtscts;
+        status = "okay";
+
+        bluetooth {
+                compatible = "brcm,bcm43438-bt";
+                clocks = <&ccu CLK_OUTA>;
+                clock-names = "lpo";
+                vbat-supply = <&reg_dldo2>;
+                vddio-supply = <&reg_dldo1>;
+                device-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
+                /* TODO host wake line connected to PMIC GPIO pins */
+                shutdown-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */
+                max-speed = <1500000>;
+        };
+};
+
 &usbphy {
         usb1_vbus-supply = <&reg_vcc5v0>;
         usb2_vbus-supply = <&reg_vcc5v0>;
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 89762dbefe42..06b685869f52 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -342,6 +342,11 @@
                         #interrupt-cells = <3>;
                         #gpio-cells = <3>;
 
+                        clk_out_a_pin: clk-out-a-pin {
+                                pins = "PI12";
+                                function = "clk_out_a";
+                        };
+
                         gmac_rgmii_pins: gmac-rgmii-pins {
                                 pins = "PA0", "PA1", "PA2", "PA3",
                                        "PA4", "PA5", "PA6", "PA7",
@@ -389,6 +394,16 @@
                                 pins = "PB22", "PB23";
                                 function = "uart0";
                         };
+
+                        uart3_pg_pins: uart3-pg-pins {
+                                pins = "PG6", "PG7";
+                                function = "uart3";
+                        };
+
+                        uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
+                                pins = "PG8", "PG9";
+                                function = "uart3";
+                        };
                 };
 
                 wdt: watchdog@1c20c90 {
diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
index 85da85faf869..28c034928d67 100644
--- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
+++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
@@ -133,6 +133,19 @@
         status = "okay";
 };
 
+&gmac {
+        pinctrl-names = "default";
+        pinctrl-0 = <&gmac_rgmii_pins>;
+        phy = <&phy1>;
+        phy-mode = "rgmii";
+        phy-supply = <&reg_cldo1>;
+        status = "okay";
+
+        phy1: ethernet-phy@1 {
+                reg = <1>;
+        };
+};
+
 &i2c3 {
         pinctrl-names = "default";
         pinctrl-0 = <&i2c3_pins>;
@@ -183,10 +196,26 @@
         clocks = <&ac100_rtc 0>;
 };
 
+&pio {
+        vcc-pa-supply = <&reg_ldo_io1>;
+        vcc-pb-supply = <&reg_aldo2>;
+        vcc-pc-supply = <&reg_dcdc1>;
+        vcc-pd-supply = <&reg_dc1sw>;
+        vcc-pe-supply = <&reg_eldo2>;
+        vcc-pf-supply = <&reg_dcdc1>;
+        vcc-pg-supply = <&reg_ldo_io0>;
+        vcc-ph-supply = <&reg_dcdc1>;
+};
+
 &r_ir {
         status = "okay";
 };
 
+&r_pio {
+        vcc-pl-supply = <&reg_dldo2>;
+        vcc-pm-supply = <&reg_eldo3>;
+};
+
 &r_rsb {
         status = "okay";
 
@@ -217,6 +246,10 @@
                                 /* unused */
                         };
 
+                        reg_dc1sw: dc1sw {
+                                regulator-name = "vcc-pd";
+                        };
+
                         reg_dc5ldo: dc5ldo {
                                 regulator-always-on;
                                 regulator-min-microvolt = <800000>;
@@ -271,7 +304,6 @@
                         };
 
                         reg_dldo2: dldo2 {
-                                regulator-always-on;
                                 regulator-min-microvolt = <3000000>;
                                 regulator-max-microvolt = <3000000>;
                                 regulator-name = "vcc-pl";
@@ -290,14 +322,12 @@
                         };
 
                         reg_eldo3: eldo3 {
-                                regulator-always-on;
                                 regulator-min-microvolt = <3000000>;
                                 regulator-max-microvolt = <3000000>;
                                 regulator-name = "vcc-pm-codec-io1";
                         };
 
                         reg_ldo_io0: ldo_io0 {
-                                regulator-always-on;
                                 regulator-min-microvolt = <3000000>;
                                 regulator-max-microvolt = <3000000>;
                                 regulator-name = "vcc-pg";
@@ -385,6 +415,14 @@
                                  */
                                 regulator-min-microvolt = <3300000>;
                                 regulator-max-microvolt = <3300000>;
+                                /*
+                                 * The PHY requires 20ms after all voltages
+                                 * are applied until core logic is ready and
+                                 * 30ms after the reset pin is de-asserted.
+                                 * Set a 100ms delay to account for PMIC
+                                 * ramp time and board traces.
+                                 */
+                                regulator-enable-ramp-delay = <100000>;
                                 regulator-name = "vcc-gmac-phy";
                         };
 
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index 58a199b0e494..864715ec3cb0 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -120,6 +120,19 @@
         status = "okay";
 };
 
+&gmac {
+        pinctrl-names = "default";
+        pinctrl-0 = <&gmac_rgmii_pins>;
+        phy = <&phy1>;
+        phy-mode = "rgmii";
+        phy-supply = <&reg_cldo1>;
+        status = "okay";
+
+        phy1: ethernet-phy@1 {
+                reg = <1>;
+        };
+};
+
 &mmc0 {
         pinctrl-names = "default";
         pinctrl-0 = <&mmc0_pins>;
@@ -172,10 +185,26 @@
         clocks = <&ac100_rtc 0>;
 };
 
+&pio {
+        vcc-pa-supply = <&reg_ldo_io1>;
+        vcc-pb-supply = <&reg_aldo2>;
+        vcc-pc-supply = <&reg_dcdc1>;
+        vcc-pd-supply = <&reg_dcdc1>;
+        vcc-pe-supply = <&reg_eldo2>;
+        vcc-pf-supply = <&reg_dcdc1>;
+        vcc-pg-supply = <&reg_ldo_io0>;
+        vcc-ph-supply = <&reg_dcdc1>;
+};
+
 &r_ir {
         status = "okay";
 };
 
+&r_pio {
+        vcc-pl-supply = <&reg_dldo2>;
+        vcc-pm-supply = <&reg_eldo3>;
+};
+
 &r_rsb {
         status = "okay";
 
@@ -213,6 +242,10 @@
                                 regulator-name = "vdd-cpus-09-usbh";
                         };
 
+                        dc1sw {
+                                /* unused */
+                        };
+
                         reg_dcdc1: dcdc1 {
                                 regulator-always-on;
                                 regulator-min-microvolt = <3000000>;
@@ -260,7 +293,6 @@
                         };
 
                         reg_dldo2: dldo2 {
-                                regulator-always-on;
                                 regulator-min-microvolt = <3000000>;
                                 regulator-max-microvolt = <3000000>;
                                 regulator-name = "vcc-pl";
@@ -279,14 +311,12 @@
                         };
 
                         reg_eldo3: eldo3 {
-                                regulator-always-on;
                                 regulator-min-microvolt = <3000000>;
                                 regulator-max-microvolt = <3000000>;
                                 regulator-name = "vcc-pm-codec-io1";
                         };
 
                         reg_ldo_io0: ldo_io0 {
-                                regulator-always-on;
                                 regulator-min-microvolt = <3000000>;
                                 regulator-max-microvolt = <3000000>;
                                 regulator-name = "vcc-pg";
@@ -374,6 +404,14 @@
                                  */
                                 regulator-min-microvolt = <3300000>;
                                 regulator-max-microvolt = <3300000>;
+                                /*
+                                 * The PHY requires 20ms after all voltages
+                                 * are applied until core logic is ready and
+                                 * 30ms after the reset pin is de-asserted.
+                                 * Set a 100ms delay to account for PMIC
+                                 * ramp time and board traces.
+                                 */
+                                regulator-enable-ramp-delay = <100000>;
                                 regulator-name = "vcc-gmac-phy";
                         };
 
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index d9532fb1ef65..6fb292e0b662 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -56,6 +56,10 @@
         #size-cells = <2>;
         interrupt-parent = <&gic>;
 
+        aliases {
+                ethernet0 = &gmac;
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -183,6 +187,37 @@
                         clock-output-names = "osc32k";
                 };
 
+                /*
+                 * The following two are dummy clocks, placeholders
+                 * used in the gmac_tx clock. The gmac driver will
+                 * choose one parent depending on the PHY interface
+                 * mode, using clk_set_rate auto-reparenting.
+                 *
+                 * The actual TX clock rate is not controlled by the
+                 * gmac_tx clock.
+                 */
+                mii_phy_tx_clk: mii_phy_tx_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <25000000>;
+                        clock-output-names = "mii_phy_tx";
+                };
+
+                gmac_int_tx_clk: gmac_int_tx_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <125000000>;
+                        clock-output-names = "gmac_int_tx";
+                };
+
+                gmac_tx_clk: clk@800030 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun7i-a20-gmac-clk";
+                        reg = <0x00800030 0x4>;
+                        clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
+                        clock-output-names = "gmac_tx";
+                };
+
                 cpus_clk: clk@8001410 {
                         compatible = "allwinner,sun9i-a80-cpus-clk";
                         reg = <0x08001410 0x4>;
@@ -283,6 +318,23 @@
                         };
                 };
 
+                gmac: ethernet@830000 {
+                        compatible = "allwinner,sun7i-a20-gmac";
+                        reg = <0x00830000 0x1054>;
+                        interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "macirq";
+                        clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>;
+                        clock-names = "stmmaceth", "allwinner_gmac_tx";
+                        resets = <&ccu RST_BUS_GMAC>;
+                        reset-names = "stmmaceth";
+                        snps,pbl = <2>;
+                        snps,fixed-burst;
+                        snps,force_sf_dma_mode;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
                 ehci0: usb@a00000 {
                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
                         reg = <0x00a00000 0x100>;
@@ -948,6 +1000,19 @@
                         #size-cells = <0>;
                         #gpio-cells = <3>;
 
+                        gmac_rgmii_pins: gmac-rgmii-pins {
+                                allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+                                                 "PA4", "PA5", "PA7", "PA8",
+                                                 "PA9", "PA10", "PA12", "PA13",
+                                                 "PA15", "PA16", "PA17";
+                                allwinner,function = "gmac";
+                                /*
+                                 * data lines in RGMII mode use DDR mode
+                                 * and need a higher signal drive strength
+                                 */
+                                drive-strength = <40>;
+                        };
+
                         i2c3_pins: i2c3-pins {
                                 pins = "PG10", "PG11";
                                 function = "i2c3";
diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
index b3283aeb5b7d..3bed375b9c03 100644
--- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
+++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
@@ -103,6 +103,8 @@
                 compatible = "mmc-pwrseq-simple";
                 pinctrl-names = "default";
                 reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+                clocks = <&rtc 1>;
+                clock-names = "ext_clock";
         };
 };
 
@@ -215,7 +217,19 @@
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
-        status = "okay";
+        uart-has-rtscts;
+        status = "okay";
+
+        bluetooth {
+                compatible = "brcm,bcm43438-bt";
+                clocks = <&rtc 1>;
+                clock-names = "lpo";
+                vbat-supply = <&reg_vcc3v3>;
+                vddio-supply = <&reg_vcc3v3>;
+                device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
+                host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
+                shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+        };
 };
 
 &usb_otg {
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index a4c757c0b741..d74a6cbbfdf4 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -740,8 +740,7 @@
                 };
 
                 csi: camera@1cb0000 {
-                        compatible = "allwinner,sun8i-h3-csi",
-                                     "allwinner,sun6i-a31-csi";
+                        compatible = "allwinner,sun8i-h3-csi";
                         reg = <0x01cb0000 0x1000>;
                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&ccu CLK_BUS_CSI>,
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 1788556b4977..97a5c3504bbe 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -1087,7 +1087,7 @@
                 status = "okay";
                 spi-max-frequency = <25000000>;
                 spi-flash@0 {
-                        compatible = "winbond,w25q32dw";
+                        compatible = "winbond,w25q32dw", "jedec,spi-nor";
                         reg = <0>;
                         spi-max-frequency = <20000000>;
                 };
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index 9151b3ebb839..33bbb1c5285d 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -1656,7 +1656,7 @@
                 status = "okay";
                 spi-max-frequency = <25000000>;
                 spi-flash@0 {
-                        compatible = "winbond,w25q32dw";
+                        compatible = "winbond,w25q32dw", "jedec,spi-nor";
                         reg = <0>;
                         spi-max-frequency = <20000000>;
                 };
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index d5f11d6d987e..a1acd872bcf2 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -13,10 +13,25 @@
                 stdout-path = "serial0:115200n8";
         };
 
-        memory@80000000 {
+        /*
+         * Note that recent version of the device tree compiler (starting with
+         * version 1.4.2) warn about this node containing a reg property, but
+         * missing a unit-address. However, the bootloader on these Chromebook
+         * devices relies on the full name of this node to be exactly /memory.
+         * Adding the unit-address causes the bootloader to create a /memory
+         * node and write the memory bank configuration to that node, which in
+         * turn leads the kernel to believe that the device has 2 GiB of
+         * memory instead of the amount detected by the bootloader.
+         *
+         * The name of this node is effectively ABI and must not be changed.
+         */
+        memory {
+                device_type = "memory";
                 reg = <0x0 0x80000000 0x0 0x80000000>;
         };
 
+        /delete-node/ memory@80000000;
+
         host1x@50000000 {
                 hdmi@54280000 {
                         status = "okay";
@@ -355,7 +370,7 @@
                 spi-max-frequency = <25000000>;
 
                 flash@0 {
-                        compatible = "winbond,w25q32dw";
+                        compatible = "winbond,w25q32dw", "jedec,spi-nor";
                         spi-max-frequency = <25000000>;
                         reg = <0>;
                 };
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 82d139648ef1..4882b61fb680 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -879,7 +879,7 @@
                 status = "okay";
                 spi-max-frequency = <25000000>;
                 spi-flash@0 {
-                        compatible = "winbond,w25q32dw";
+                        compatible = "winbond,w25q32dw", "jedec,spi-nor";
                         reg = <0>;
                         spi-max-frequency = <20000000>;
                 };
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 9eb26dc15f6b..3e5ac096d85e 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -287,7 +287,7 @@
                 status = "okay";
                 spi-max-frequency = <48000000>;
                 spi-flash@0 {
-                        compatible = "winbond,w25q80bl";
+                        compatible = "winbond,w25q80bl", "jedec,spi-nor";
                         reg = <0>;
                         spi-max-frequency = <48000000>;
                 };
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index dcad6d6128cf..8c942e60703e 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -616,17 +616,14 @@
         };
 
         mc: memory-controller@7000f000 {
-                compatible = "nvidia,tegra20-mc";
-                reg = <0x7000f000 0x024
-                       0x7000f03c 0x3c4>;
+                compatible = "nvidia,tegra20-mc-gart";
+                reg = <0x7000f000 0x400         /* controller registers */
+                       0x58000000 0x02000000>;  /* GART aperture */
+                clocks = <&tegra_car TEGRA20_CLK_MC>;
+                clock-names = "mc";
                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
                 #reset-cells = <1>;
-        };
-
-        iommu@7000f024 {
-                compatible = "nvidia,tegra20-gart";
-                reg = <0x7000f024 0x00000018    /* controller registers */
-                       0x58000000 0x02000000>;  /* GART aperture */
+                #iommu-cells = <0>;
         };
 
         memory-controller@7000f400 {
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index b0d40ac8ac6e..a3b0f3555cd2 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -1886,7 +1886,7 @@
                 status = "okay";
                 spi-max-frequency = <25000000>;
                 spi-flash@1 {
-                        compatible = "winbond,w25q32";
+                        compatible = "winbond,w25q32", "jedec,spi-nor";
                         reg = <1>;
                         spi-max-frequency = <20000000>;
                 };
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index fb9222b479d2..7ce61edd52f5 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -360,7 +360,7 @@
                 status = "okay";
                 spi-max-frequency = <25000000>;
                 spi-flash@1 {
-                        compatible = "winbond,w25q32";
+                        compatible = "winbond,w25q32", "jedec,spi-nor";
                         reg = <1>;
                         spi-max-frequency = <20000000>;
                 };
diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts
index 6f4f60ba5429..269e6bf99ccb 100644
--- a/arch/arm/boot/dts/versatile-ab.dts
+++ b/arch/arm/boot/dts/versatile-ab.dts
@@ -1,6 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0
 /dts-v1/;
-/include/ "skeleton.dtsi"
 
 / {
         model = "ARM Versatile AB";
@@ -21,6 +20,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x0 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index a9569d15de41..d3963e9eaf48 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -133,7 +133,7 @@
                                 mmci@50000 {
                                         compatible = "arm,pl180", "arm,primecell";
                                         reg = <0x050000 0x1000>;
-                                        interrupts = <9 10>;
+                                        interrupts = <9>, <10>;
                                         cd-gpios = <&v2m_mmc_gpios 0 0>;
                                         wp-gpios = <&v2m_mmc_gpios 1 0>;
                                         max-frequency = <12000000>;
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index fd42e1194179..798c97aff7fa 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -133,7 +133,7 @@
                                 mmci@5000 {
                                         compatible = "arm,pl180", "arm,primecell";
                                         reg = <0x05000 0x1000>;
-                                        interrupts = <9 10>;
+                                        interrupts = <9>, <10>;
                                         cd-gpios = <&v2m_mmc_gpios 0 0>;
                                         wp-gpios = <&v2m_mmc_gpios 1 0>;
                                         max-frequency = <12000000>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index a2ccacd07f4f..00cd9f5bef2e 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -42,6 +42,7 @@
                         cci-control-port = <&cci_control1>;
                         cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
                         capacity-dmips-mhz = <1024>;
+                        dynamic-power-coefficient = <990>;
                 };
 
                 cpu1: cpu@1 {
@@ -51,6 +52,7 @@
                         cci-control-port = <&cci_control1>;
                         cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
                         capacity-dmips-mhz = <1024>;
+                        dynamic-power-coefficient = <990>;
                 };
 
                 cpu2: cpu@2 {
@@ -60,6 +62,7 @@
                         cci-control-port = <&cci_control2>;
                         cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
                         capacity-dmips-mhz = <516>;
+                        dynamic-power-coefficient = <133>;
                 };
 
                 cpu3: cpu@3 {
@@ -69,6 +72,7 @@
                         cci-control-port = <&cci_control2>;
                         cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
                         capacity-dmips-mhz = <516>;
+                        dynamic-power-coefficient = <133>;
                 };
 
                 cpu4: cpu@4 {
@@ -78,6 +82,7 @@
                         cci-control-port = <&cci_control2>;
                         cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
                         capacity-dmips-mhz = <516>;
+                        dynamic-power-coefficient = <133>;
                 };
 
                 idle-states {
diff --git a/arch/arm/boot/dts/vf610-bk4.dts b/arch/arm/boot/dts/vf610-bk4.dts
index 689c8930dce3..3fa0cbe456db 100644
--- a/arch/arm/boot/dts/vf610-bk4.dts
+++ b/arch/arm/boot/dts/vf610-bk4.dts
@@ -60,6 +60,29 @@
                 regulator-min-microvolt = <3300000>;
                 regulator-max-microvolt = <3300000>;
         };
+
+        spi-gpio {
+                compatible = "spi-gpio";
+                pinctrl-0 = <&pinctrl_gpio_spi>;
+                pinctrl-names = "default";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                /* PTD12 ->RPIO[91] */
+                sck-gpios  = <&gpio2 27 GPIO_ACTIVE_LOW>;
+                /* PTD10 ->RPIO[89] */
+                miso-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
+                num-chipselects = <0>;
+
+                gpio@0 {
+                        compatible = "pisosr-gpio";
+                        reg = <0>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        /* PTB18 -> RGPIO[40] */
+                        load-gpios  = <&gpio1 8 GPIO_ACTIVE_LOW>;
+                        spi-max-frequency = <100000>;
+                };
+        };
 };
 
 &adc0 {
@@ -110,11 +133,11 @@
         bus-num = <3>;
         status = "okay";
         spi-slave;
+        #address-cells = <0>;
 
-        slave@0 {
+        slave {
                 compatible = "lwn,bk4";
                 spi-max-frequency = <30000000>;
-                reg = <0>;
         };
 };
 
@@ -431,6 +454,14 @@
                 >;
         };
 
+        pinctrl_gpio_spi: pinctrl-gpio-spi {
+                fsl,pins = <
+                        VF610_PAD_PTB18__GPIO_40        0x1183
+                        VF610_PAD_PTD10__GPIO_89        0x1183
+                        VF610_PAD_PTD12__GPIO_91        0x1183
+                >;
+        };
+
         pinctrl_i2c2: i2c2grp {
                 fsl,pins = <
                         VF610_PAD_PTA22__I2C2_SCL               0x34df
diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts
index 7cdcc5fe8282..445c7dc306b2 100644
--- a/arch/arm/boot/dts/vf610-zii-cfu1.dts
+++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts
@@ -207,7 +207,7 @@
 };
 
 &i2c0 {
-        clock-frequency = <100000>;
+        clock-frequency = <400000>;
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_i2c0>;
         status = "okay";
diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts
new file mode 100644
index 000000000000..2b10672fadbd
--- /dev/null
+++ b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/*
+ * Device tree file for ZII's SSMB DTU board
+ *
+ * SSMB - SPU3 Switch Management Board
+ * DTU - Digital Tapping Unit
+ *
+ * Copyright (C) 2015-2019 Zodiac Inflight Innovations
+ *
+ * Based on an original 'vf610-twr.dts' which is Copyright 2015,
+ * Freescale Semiconductor, Inc.
+ */
+
+/dts-v1/;
+#include "vf610.dtsi"
+
+/ {
+        model = "ZII VF610 SSMB DTU Board";
+        compatible = "zii,vf610dtu", "zii,vf610dev", "fsl,vf610";
+
+        chosen {
+                stdout-path = &uart0;
+        };
+
+        memory@80000000 {
+                device_type = "memory";
+                reg = <0x80000000 0x20000000>;
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+                pinctrl-0 = <&pinctrl_leds_debug>;
+                pinctrl-names = "default";
+
+                led-debug {
+                        label = "zii:green:debug1";
+                        gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                        max-brightness = <1>;
+                };
+        };
+
+        reg_vcc_3v3_mcu: regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc_3v3_mcu";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+};
+
+&adc0 {
+        vref-supply = <&reg_vcc_3v3_mcu>;
+        status = "okay";
+};
+
+&adc1 {
+        vref-supply = <&reg_vcc_3v3_mcu>;
+        status = "okay";
+};
+
+&edma0 {
+        status = "okay";
+};
+
+&edma1 {
+        status = "okay";
+};
+
+&esdhc0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc0>;
+        bus-width = <8>;
+        non-removable;
+        no-1-8-v;
+        keep-power-in-suspend;
+        status = "okay";
+};
+
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1>;
+        bus-width = <4>;
+        status = "okay";
+};
+
+&fec1 {
+        phy-mode = "rmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec1>;
+        status = "okay";
+
+        fixed-link {
+                speed = <100>;
+                full-duplex;
+        };
+
+        mdio1: mdio {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "okay";
+
+                switch0: switch0@0 {
+                        compatible = "marvell,mv88e6190";
+                        pinctrl-0 = <&pinctrl_gpio_switch0>;
+                        pinctrl-names = "default";
+                        reg = <0>;
+                        eeprom-length = <65536>;
+                        reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
+                        interrupt-parent = <&gpio3>;
+                        interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        label = "cpu";
+                                        ethernet = <&fec1>;
+
+                                        fixed-link {
+                                                speed = <100>;
+                                                full-duplex;
+                                        };
+                                };
+
+                                port@1 {
+                                        reg = <1>;
+                                        label = "eth_cu_100_3";
+                                };
+
+                                port@5 {
+                                        reg = <5>;
+                                        label = "eth_cu_1000_4";
+                                };
+
+                                port@6 {
+                                        reg = <6>;
+                                        label = "eth_cu_1000_5";
+                                };
+
+                                port@8 {
+                                        reg = <8>;
+                                        label = "eth_cu_1000_1";
+                                };
+
+                                port@9 {
+                                        reg = <9>;
+                                        label = "eth_cu_1000_2";
+                                        phy-handle = <&phy9>;
+                                        phy-mode = "sgmii";
+                                        managed = "in-band-status";
+                                };
+                        };
+
+                        mdio1 {
+                                compatible = "marvell,mv88e6xxx-mdio-external";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                phy9: phy9@0 {
+                                        compatible = "ethernet-phy-ieee802.3-c45";
+                                        pinctrl-0 = <&pinctrl_gpio_phy9>;
+                                        pinctrl-names = "default";
+                                        interrupt-parent = <&gpio2>;
+                                        interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
+                                        reg = <0>;
+                                };
+                        };
+                };
+        };
+};
+
+&i2c0 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c0>;
+        status = "okay";
+
+        gpio6: gpio-expander@22 {
+                compatible = "nxp,pca9554";
+                reg = <0x22>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        /* On SSMB */
+        temperature-sensor@48 {
+                compatible = "national,lm75";
+                reg = <0x48>;
+        };
+
+        /* On DSB */
+        temperature-sensor@4d {
+                compatible = "national,lm75";
+                reg = <0x4d>;
+        };
+
+        eeprom@50 {
+                compatible = "atmel,24c04";
+                reg = <0x50>;
+                label = "nameplate";
+        };
+
+        eeprom@52 {
+                compatible = "atmel,24c04";
+                reg = <0x52>;
+        };
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart0>;
+        status = "okay";
+};
+
+&iomuxc {
+        pinctrl_dspi1: dspi1grp {
+                fsl,pins = <
+                        VF610_PAD_PTD5__DSPI1_CS0               0x1182
+                        VF610_PAD_PTD4__DSPI1_CS1               0x1182
+                        VF610_PAD_PTC6__DSPI1_SIN               0x1181
+                        VF610_PAD_PTC7__DSPI1_SOUT              0x1182
+                        VF610_PAD_PTC8__DSPI1_SCK               0x1182
+                >;
+        };
+
+        pinctrl_esdhc0: esdhc0grp {
+                fsl,pins = <
+                        VF610_PAD_PTC0__ESDHC0_CLK              0x31ef
+                        VF610_PAD_PTC1__ESDHC0_CMD              0x31ef
+                        VF610_PAD_PTC2__ESDHC0_DAT0             0x31ef
+                        VF610_PAD_PTC3__ESDHC0_DAT1             0x31ef
+                        VF610_PAD_PTC4__ESDHC0_DAT2             0x31ef
+                        VF610_PAD_PTC5__ESDHC0_DAT3             0x31ef
+                        VF610_PAD_PTD23__ESDHC0_DAT4            0x31ef
+                        VF610_PAD_PTD22__ESDHC0_DAT5            0x31ef
+                        VF610_PAD_PTD21__ESDHC0_DAT6            0x31ef
+                        VF610_PAD_PTD20__ESDHC0_DAT7            0x31ef
+                >;
+        };
+
+        pinctrl_esdhc1: esdhc1grp {
+                fsl,pins = <
+                        VF610_PAD_PTA24__ESDHC1_CLK             0x31ef
+                        VF610_PAD_PTA25__ESDHC1_CMD             0x31ef
+                        VF610_PAD_PTA26__ESDHC1_DAT0            0x31ef
+                        VF610_PAD_PTA27__ESDHC1_DAT1            0x31ef
+                        VF610_PAD_PTA28__ESDHC1_DATA2           0x31ef
+                        VF610_PAD_PTA29__ESDHC1_DAT3            0x31ef
+                >;
+        };
+
+        pinctrl_fec1: fec1grp {
+                fsl,pins = <
+                        VF610_PAD_PTA6__RMII_CLKIN              0x30d1
+                        VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
+                        VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
+                        VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
+                        VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
+                        VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
+                        VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
+                        VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
+                        VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
+                        VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
+                >;
+        };
+
+        pinctrl_gpio_phy9: pinctrl-gpio-phy9 {
+                fsl,pins = <
+                        VF610_PAD_PTB24__GPIO_94                0x219d
+                >;
+        };
+
+        pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
+                fsl,pins = <
+                        VF610_PAD_PTE2__GPIO_107                0x31c2
+                        VF610_PAD_PTB28__GPIO_98                0x219d
+                >;
+        };
+
+        pinctrl_i2c0: i2c0grp {
+                fsl,pins = <
+                        VF610_PAD_PTB14__I2C0_SCL               0x37ff
+                        VF610_PAD_PTB15__I2C0_SDA               0x37ff
+                >;
+        };
+
+        pinctrl_i2c1: i2c1grp {
+                fsl,pins = <
+                        VF610_PAD_PTB16__I2C1_SCL               0x37ff
+                        VF610_PAD_PTB17__I2C1_SDA               0x37ff
+                >;
+        };
+
+        pinctrl_leds_debug: pinctrl-leds-debug {
+                fsl,pins = <
+                        VF610_PAD_PTD3__GPIO_82                 0x31c2
+                >;
+        };
+
+        pinctrl_uart0: uart0grp {
+                fsl,pins = <
+                        VF610_PAD_PTB10__UART0_TX               0x21a2
+                        VF610_PAD_PTB11__UART0_RX               0x21a1
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts
index 757af56e8ee7..0d9fe5ac83a3 100644
--- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts
+++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts
@@ -99,6 +99,8 @@
         non-removable;
         no-1-8-v;
         keep-power-in-suspend;
+        no-sdio;
+        no-sd;
         status = "okay";
 };
 
@@ -106,6 +108,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_esdhc1>;
         bus-width = <4>;
+        no-sdio;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
index 1929ad390d88..8b5af039b072 100644
--- a/arch/arm/boot/dts/vt8500.dtsi
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -6,9 +6,9 @@
  * Licensed under GPLv2 or later
  */
 
-/include/ "skeleton.dtsi"
-
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "via,vt8500";
 
         cpus {
@@ -21,6 +21,11 @@
                 };
         };
 
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x0>;
+        };
+
         aliases {
                 serial0 = &uart0;
                 serial1 = &uart1;
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
index e9ef539e13d3..cca6747304c4 100644
--- a/arch/arm/boot/dts/wm8505.dtsi
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -6,9 +6,9 @@
  * Licensed under GPLv2 or later
  */
 
-/include/ "skeleton.dtsi"
-
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "wm,wm8505";
 
         cpus {
@@ -21,6 +21,11 @@
                 };
         };
 
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x0>;
+        };
+
         aliases {
                 serial0 = &uart0;
                 serial1 = &uart1;
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
index e12213d16693..00d01769a68f 100644
--- a/arch/arm/boot/dts/wm8650.dtsi
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -6,9 +6,9 @@
  * Licensed under GPLv2 or later
  */
 
-/include/ "skeleton.dtsi"
-
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "wm,wm8650";
 
         cpus {
@@ -21,6 +21,11 @@
                 };
         };
 
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x0>;
+        };
+
         aliases {
                 serial0 = &uart0;
                 serial1 = &uart1;
diff --git a/arch/arm/boot/dts/wm8750.dtsi b/arch/arm/boot/dts/wm8750.dtsi
index 46d076d7302b..54d8f7d9bb33 100644
--- a/arch/arm/boot/dts/wm8750.dtsi
+++ b/arch/arm/boot/dts/wm8750.dtsi
@@ -6,9 +6,9 @@
  * Licensed under GPLv2 or later
  */
 
-/include/ "skeleton.dtsi"
-
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "wm,wm8750";
 
         cpus {
@@ -21,6 +21,11 @@
                 };
         };
 
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x0>;
+        };
+
         aliases {
                 serial0 = &uart0;
                 serial1 = &uart1;
diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi
index 8fbccfbe75f3..c572d777077f 100644
--- a/arch/arm/boot/dts/wm8850.dtsi
+++ b/arch/arm/boot/dts/wm8850.dtsi
@@ -6,9 +6,9 @@
  * Licensed under GPLv2 or later
  */
 
-/include/ "skeleton.dtsi"
-
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
         compatible = "wm,wm8850";
 
         cpus {
@@ -22,6 +22,11 @@
                 };
         };
 
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x0>;
+        };
+
         aliases {
                 serial0 = &uart0;
                 serial1 = &uart1;
diff --git a/arch/arm/boot/dts/zx296702-ad1.dts b/arch/arm/boot/dts/zx296702-ad1.dts
index eedd3fcbc002..bd9400840023 100644
--- a/arch/arm/boot/dts/zx296702-ad1.dts
+++ b/arch/arm/boot/dts/zx296702-ad1.dts
@@ -14,6 +14,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x50000000 0x20000000>;
         };
 };
diff --git a/arch/arm/boot/dts/zx296702.dtsi b/arch/arm/boot/dts/zx296702.dtsi
index 240e7a23d81f..afd98de029be 100644
--- a/arch/arm/boot/dts/zx296702.dtsi
+++ b/arch/arm/boot/dts/zx296702.dtsi
@@ -1,10 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0
 
-#include "skeleton.dtsi"
 #include <dt-bindings/clock/zx296702-clock.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/zynq-zturn.dts b/arch/arm/boot/dts/zynq-zturn.dts
index b38704657960..5ec616ebca08 100644
--- a/arch/arm/boot/dts/zynq-zturn.dts
+++ b/arch/arm/boot/dts/zynq-zturn.dts
@@ -54,7 +54,7 @@
                         label = "K1";
                         gpios = <&gpio0 0x32 0x1>;
                         linux,code = <0x66>;
-                        gpio-key,wakeup;
+                        wakeup-source;
                         autorepeat;
                 };
         };
diff --git a/arch/arm/common/mcpm_entry.c b/arch/arm/common/mcpm_entry.c
index ad574d20415c..1b1b82b37ce0 100644
--- a/arch/arm/common/mcpm_entry.c
+++ b/arch/arm/common/mcpm_entry.c
@@ -381,7 +381,7 @@ static int __init nocache_trampoline(unsigned long _arg)
         unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
         phys_reset_t phys_reset;
 
-        mcpm_set_entry_vector(cpu, cluster, cpu_resume);
+        mcpm_set_entry_vector(cpu, cluster, cpu_resume_no_hyp);
         setup_mm_for_reboot();
 
         __mcpm_cpu_going_down(cpu, cluster);
diff --git a/arch/arm/configs/axm55xx_defconfig b/arch/arm/configs/axm55xx_defconfig
index 8e17e7ed1f02..53864316bee1 100644
--- a/arch/arm/configs/axm55xx_defconfig
+++ b/arch/arm/configs/axm55xx_defconfig
@@ -155,10 +155,6 @@ CONFIG_PMBUS=y
 CONFIG_SENSORS_LTC2978=y
 CONFIG_WATCHDOG=y
 CONFIG_ARM_SP805_WATCHDOG=y
-CONFIG_FB=y
-CONFIG_FB_ARMCLCD=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_MONO is not set
 # CONFIG_LOGO_LINUX_VGA16 is not set
 CONFIG_HID_A4TECH=y
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index bb6a35fb1dd7..dcf7610cfe55 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -91,6 +91,8 @@ CONFIG_THERMAL=y
 CONFIG_BCM2835_THERMAL=y
 CONFIG_WATCHDOG=y
 CONFIG_BCM2835_WDT=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_DRM=y
 CONFIG_DRM_VC4=y
 CONFIG_FB_SIMPLE=y
@@ -129,6 +131,7 @@ CONFIG_DMADEVICES=y
 CONFIG_DMA_BCM2835=y
 CONFIG_STAGING=y
 CONFIG_SND_BCM2835=m
+CONFIG_VIDEO_BCM2835=m
 CONFIG_MAILBOX=y
 CONFIG_BCM2835_MBOX=y
 # CONFIG_IOMMU_SUPPORT is not set
@@ -158,7 +161,6 @@ CONFIG_PRINTK_TIME=y
 CONFIG_BOOT_PRINTK_DELAY=y
 CONFIG_DYNAMIC_DEBUG=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_UNUSED_SYMBOLS=y
 CONFIG_DEBUG_MEMORY_INIT=y
diff --git a/arch/arm/configs/cns3420vb_defconfig b/arch/arm/configs/cns3420vb_defconfig
index c6dcd6e4f4e6..419b73564f29 100644
--- a/arch/arm/configs/cns3420vb_defconfig
+++ b/arch/arm/configs/cns3420vb_defconfig
@@ -60,7 +60,6 @@ CONFIG_EXT2_FS_XATTR=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_FSCACHE=y
 CONFIG_TMPFS=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/configs/efm32_defconfig b/arch/arm/configs/efm32_defconfig
index 860d27138e6f..ee42158f41ec 100644
--- a/arch/arm/configs/efm32_defconfig
+++ b/arch/arm/configs/efm32_defconfig
@@ -94,7 +94,6 @@ CONFIG_ROMFS_BACKED_BY_MTD=y
 # CONFIG_NETWORK_FILESYSTEMS is not set
 CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_SCHED_DEBUG is not set
diff --git a/arch/arm/configs/eseries_pxa_defconfig b/arch/arm/configs/eseries_pxa_defconfig
index cd27d651463c..eabb784cf7da 100644
--- a/arch/arm/configs/eseries_pxa_defconfig
+++ b/arch/arm/configs/eseries_pxa_defconfig
@@ -103,7 +103,6 @@ CONFIG_NFS_V3=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_CRYPTO_CBC=m
 CONFIG_CRYPTO_PCBC=m
diff --git a/arch/arm/configs/gemini_defconfig b/arch/arm/configs/gemini_defconfig
index 553777ac2814..ef9aae89907d 100644
--- a/arch/arm/configs/gemini_defconfig
+++ b/arch/arm/configs/gemini_defconfig
@@ -87,6 +87,5 @@ CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_ROMFS_FS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_DEBUG_FS=y
diff --git a/arch/arm/configs/integrator_defconfig b/arch/arm/configs/integrator_defconfig
index 69cb8f1efcea..747550c7af2f 100644
--- a/arch/arm/configs/integrator_defconfig
+++ b/arch/arm/configs/integrator_defconfig
@@ -27,6 +27,7 @@ CONFIG_CPU_FREQ_GOV_POWERSAVE=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
 CONFIG_CPU_FREQ_GOV_ONDEMAND=y
 CONFIG_CPUFREQ_DT=y
+CONFIG_CMA=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -53,13 +54,17 @@ CONFIG_E100=y
 CONFIG_SMC91X=y
 # CONFIG_KEYBOARD_ATKBD is not set
 # CONFIG_SERIO_SERPORT is not set
-CONFIG_FB=y
+CONFIG_DRM=y
+CONFIG_DRM_DUMB_VGA_DAC=y
+CONFIG_DRM_PL111=y
 CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_ARMCLCD=y
 CONFIG_FB_MATROX=y
 CONFIG_FB_MATROX_MILLENIUM=y
 CONFIG_FB_MATROX_MYSTIQUE=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
 # CONFIG_VGA_CONSOLE is not set
+CONFIG_LOGO=y
 CONFIG_MMC=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_NEW_LEDS=y
diff --git a/arch/arm/configs/lpc18xx_defconfig b/arch/arm/configs/lpc18xx_defconfig
index 23df2518203d..e3d5e15d66d1 100644
--- a/arch/arm/configs/lpc18xx_defconfig
+++ b/arch/arm/configs/lpc18xx_defconfig
@@ -1,5 +1,6 @@
 CONFIG_CROSS_COMPILE="arm-linux-gnueabihf-"
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
 CONFIG_BLK_DEV_INITRD=y
 # CONFIG_RD_BZIP2 is not set
 # CONFIG_RD_LZMA is not set
@@ -17,22 +18,20 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_EMBEDDED=y
 # CONFIG_VM_EVENT_COUNTERS is not set
 # CONFIG_SLUB_DEBUG is not set
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
 # CONFIG_MMU is not set
-CONFIG_ARM_SINGLE_ARMV7M=y
 CONFIG_ARCH_LPC18XX=y
 CONFIG_SET_MEM_PARAM=y
 CONFIG_DRAM_BASE=0x28000000
 CONFIG_DRAM_SIZE=0x02000000
 CONFIG_FLASH_MEM_BASE=0x1b000000
 CONFIG_FLASH_SIZE=0x00080000
-CONFIG_PREEMPT=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
 CONFIG_BINFMT_SHARED_FLAT=y
@@ -69,7 +68,6 @@ CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
 # CONFIG_NET_VENDOR_ARC is not set
-# CONFIG_NET_CADENCE is not set
 # CONFIG_NET_VENDOR_BROADCOM is not set
 # CONFIG_NET_VENDOR_CIRRUS is not set
 # CONFIG_NET_VENDOR_FARADAY is not set
@@ -90,7 +88,6 @@ CONFIG_STMMAC_ETH=y
 CONFIG_SMSC_PHY=y
 # CONFIG_USB_NET_DRIVERS is not set
 # CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_GPIO=y
@@ -101,13 +98,11 @@ CONFIG_KEYBOARD_GPIO_POLLED=y
 # CONFIG_UNIX98_PTYS is not set
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_NONSTANDARD=y
-# CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_8250=y
 # CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
 CONFIG_I2C_LPC2K=y
 CONFIG_SPI=y
 CONFIG_SPI_PL022=y
@@ -121,8 +116,10 @@ CONFIG_WATCHDOG=y
 CONFIG_LPC18XX_WATCHDOG=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_FB=y
-CONFIG_FB_ARMCLCD=y
+CONFIG_DRM=y
+CONFIG_DRM_PL111=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
@@ -144,15 +141,14 @@ CONFIG_AMBA_PL08X=y
 CONFIG_LPC18XX_DMAMUX=y
 CONFIG_MEMORY=y
 CONFIG_ARM_PL172_MPMC=y
-CONFIG_PWM=y
-CONFIG_PWM_LPC18XX_SCT=y
 CONFIG_IIO=y
 CONFIG_MMA7455_I2C=y
 CONFIG_LPC18XX_ADC=y
 CONFIG_LPC18XX_DAC=y
 CONFIG_IIO_SYSFS_TRIGGER=y
+CONFIG_PWM=y
+CONFIG_PWM_LPC18XX_SCT=y
 CONFIG_PHY_LPC18XX_USB_OTG=y
-CONFIG_NVMEM=y
 CONFIG_NVMEM_LPC18XX_EEPROM=y
 CONFIG_EXT2_FS=y
 # CONFIG_FILE_LOCKING is not set
@@ -160,9 +156,10 @@ CONFIG_EXT2_FS=y
 # CONFIG_INOTIFY_USER is not set
 CONFIG_JFFS2_FS=y
 # CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC7=y
 CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_DEBUG_FS=y
 CONFIG_MAGIC_SYSRQ=y
@@ -170,5 +167,3 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index 0b54b4024e51..e752fb704df0 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=16
@@ -11,13 +12,7 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
-CONFIG_JUMP_LABEL=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_LPC32XX=y
-CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
@@ -26,6 +21,11 @@ CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_CMDLINE="console=ttyS0,115200n81 root=/dev/ram0"
 CONFIG_CPU_IDLE=y
 CONFIG_VFP=y
+CONFIG_JUMP_LABEL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -56,6 +56,7 @@ CONFIG_BLK_DEV_CRYPTOLOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=1
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_SRAM=y
 CONFIG_EEPROM_AT24=y
 CONFIG_EEPROM_AT25=y
 CONFIG_SCSI=y
@@ -75,9 +76,6 @@ CONFIG_LPC_ENET=y
 # CONFIG_NET_VENDOR_STMICRO is not set
 CONFIG_SMSC_PHY=y
 # CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_GPIO=y
@@ -92,48 +90,39 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SERIAL_HS_LPC32XX=y
+CONFIG_SERIAL_HS_LPC32XX_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_PNX=y
 CONFIG_SPI=y
 CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_EM=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_PL061=y
-CONFIG_GPIO_ADP5588=y
-CONFIG_GPIO_ADNP=y
-CONFIG_GPIO_MAX7300=y
-CONFIG_GPIO_MAX732X=y
 CONFIG_GPIO_PCA953X=y
 CONFIG_GPIO_PCF857X=y
-CONFIG_GPIO_74X164=y
-CONFIG_GPIO_MAX7301=y
-CONFIG_GPIO_MC33880=y
-CONFIG_PINCTRL_MCP23S08=y
-CONFIG_PINCTRL_SX150X=y
 CONFIG_SENSORS_DS620=y
 CONFIG_SENSORS_MAX6639=y
 CONFIG_WATCHDOG=y
 CONFIG_PNX4008_WATCHDOG=y
-CONFIG_FB=y
-CONFIG_FB_ARMCLCD=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_DRM=y
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_DRM_PL111=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_MONO is not set
 # CONFIG_LOGO_LINUX_VGA16 is not set
 CONFIG_SOUND=y
 CONFIG_SND=y
-CONFIG_SND_SEQUENCER=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_SEQUENCER_OSS=y
 # CONFIG_SND_SUPPORT_OLD_API is not set
 # CONFIG_SND_VERBOSE_PROCFS is not set
 CONFIG_SND_DEBUG=y
 CONFIG_SND_DEBUG_VERBOSE=y
+CONFIG_SND_SEQUENCER=y
 # CONFIG_SND_DRIVERS is not set
 # CONFIG_SND_ARM is not set
 # CONFIG_SND_SPI is not set
@@ -146,7 +135,6 @@ CONFIG_USB_LPC32XX=y
 CONFIG_USB_MASS_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ARMMMCI=y
 CONFIG_MMC_SPI=y
 CONFIG_NEW_LEDS=y
@@ -169,10 +157,10 @@ CONFIG_RTC_DRV_LPC32XX=y
 CONFIG_DMADEVICES=y
 CONFIG_AMBA_PL08X=y
 CONFIG_STAGING=y
-CONFIG_LPC32XX_ADC=y
 CONFIG_MEMORY=y
 CONFIG_ARM_PL172_MPMC=y
 CONFIG_IIO=y
+CONFIG_LPC32XX_ADC=y
 CONFIG_MAX517=y
 CONFIG_PWM=y
 CONFIG_PWM_LPC32XX=y
@@ -186,18 +174,27 @@ CONFIG_JFFS2_FS_WBUF_VERIFY=y
 CONFIG_UBIFS_FS=y
 CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_UTF8=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_HW is not set
+CONFIG_CRC_CCITT=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
 CONFIG_DEBUG_INFO=y
+CONFIG_GDB_SCRIPTS=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_PANIC_ON_OOPS=y
+CONFIG_PANIC_TIMEOUT=5
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
 # CONFIG_FTRACE is not set
-# CONFIG_ARM_UNWIND is not set
 CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
-CONFIG_CRYPTO_ANSI_CPRNG=y
-# CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/milbeaut_m10v_defconfig b/arch/arm/configs/milbeaut_m10v_defconfig
new file mode 100644
index 000000000000..7c07f9893a0f
--- /dev/null
+++ b/arch/arm/configs/milbeaut_m10v_defconfig
@@ -0,0 +1,119 @@
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_CGROUPS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+CONFIG_ARCH_MILBEAUT=y
+CONFIG_ARCH_MILBEAUT_M10V=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_VDSO is not set
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_ARM_ERRATA_430973=y
+CONFIG_ARM_ERRATA_720789=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_754327=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_ARM_ERRATA_775420=y
+CONFIG_ARM_ERRATA_798181=y
+CONFIG_SMP=y
+# CONFIG_SMP_ON_UP is not set
+# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_NR_CPUS=16
+CONFIG_THUMB2_KERNEL=y
+# CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11 is not set
+# CONFIG_ARM_PATCH_IDIV is not set
+CONFIG_HIGHMEM=y
+CONFIG_FORCE_MAX_ZONEORDER=12
+CONFIG_SECCOMP=y
+CONFIG_KEXEC=y
+CONFIG_EFI=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_USERSPACE=m
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_QORIQ_CPUFREQ=y
+CONFIG_CPU_IDLE=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_KERNEL_MODE_NEON=y
+CONFIG_EFI_VARS=m
+CONFIG_EFI_CAPSULE_LOADER=m
+CONFIG_ARM_CRYPTO=y
+CONFIG_CRYPTO_SHA1_ARM_NEON=m
+CONFIG_CRYPTO_SHA1_ARM_CE=m
+CONFIG_CRYPTO_SHA2_ARM_CE=m
+CONFIG_CRYPTO_SHA512_ARM=m
+CONFIG_CRYPTO_AES_ARM=m
+CONFIG_CRYPTO_AES_ARM_BS=m
+CONFIG_CRYPTO_AES_ARM_CE=m
+CONFIG_CRYPTO_GHASH_ARM_CE=m
+CONFIG_CRYPTO_CRC32_ARM_CE=m
+CONFIG_CRYPTO_CHACHA20_NEON=m
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_CMDLINE_PARTITION=y
+CONFIG_CMA=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=64
+CONFIG_OF_OVERLAY=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_SRAM=y
+CONFIG_INPUT_FF_MEMLESS=m
+CONFIG_INPUT_MATRIXKMAP=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_SERIO_LIBPS2=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_DEV_BUS=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+# CONFIG_HWMON is not set
+CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
+# CONFIG_HID is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_SYNC_FILE=y
+# CONFIG_VIRTIO_MENU is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_SOC_BRCMSTB=y
+CONFIG_MEMORY=y
+# CONFIG_ARM_PMU is not set
+CONFIG_EXT4_FS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_CONFIGFS_FS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_KEYS=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
+CONFIG_CRYPTO_SEQIV=m
+# CONFIG_CRYPTO_ECHAINIV is not set
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_HW is not set
+CONFIG_CRC_CCITT=m
+CONFIG_CRC_ITU_T=m
+CONFIG_PRINTK_TIME=y
+CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig
index 88ea02e7ba19..d95a8059d30b 100644
--- a/arch/arm/configs/mini2440_defconfig
+++ b/arch/arm/configs/mini2440_defconfig
@@ -298,7 +298,6 @@ CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
 CONFIG_DEBUG_INFO=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_FS=y
diff --git a/arch/arm/configs/moxart_defconfig b/arch/arm/configs/moxart_defconfig
index 2da0d9ee2107..078228a19339 100644
--- a/arch/arm/configs/moxart_defconfig
+++ b/arch/arm/configs/moxart_defconfig
@@ -125,7 +125,6 @@ CONFIG_CONFIGFS_FS=y
 CONFIG_JFFS2_FS=y
 CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_DEBUG_PAGEALLOC=y
 CONFIG_DEBUG_OBJECTS=y
diff --git a/arch/arm/configs/mps2_defconfig b/arch/arm/configs/mps2_defconfig
index 0bcdec7cc169..1d923dbb9928 100644
--- a/arch/arm/configs/mps2_defconfig
+++ b/arch/arm/configs/mps2_defconfig
@@ -100,7 +100,6 @@ CONFIG_ROOT_NFS=y
 CONFIG_NLS=y
 CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_SCHED_DEBUG is not set
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 5bee34a7ff2e..c75051b9392c 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -54,6 +54,8 @@ CONFIG_SOC_VF610=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_ARCH_MEDIATEK=y
 CONFIG_ARCH_MESON=y
+CONFIG_ARCH_MILBEAUT=y
+CONFIG_ARCH_MILBEAUT_M10V=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_375=y
@@ -76,6 +78,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_ARCH_RENESAS=y
 CONFIG_ARCH_EMEV2=y
 CONFIG_ARCH_R7S72100=y
+CONFIG_ARCH_R7S9210=y
 CONFIG_ARCH_R8A73A4=y
 CONFIG_ARCH_R8A7740=y
 CONFIG_ARCH_R8A7743=y
@@ -404,6 +407,7 @@ CONFIG_SPI_XILINX=y
 CONFIG_SPI_SPIDEV=y
 CONFIG_SPMI=y
 CONFIG_PINCTRL_AS3722=y
+CONFIG_PINCTRL_RZA2=y
 CONFIG_PINCTRL_PALMAS=y
 CONFIG_PINCTRL_APQ8064=y
 CONFIG_PINCTRL_APQ8084=y
@@ -631,6 +635,7 @@ CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
 CONFIG_DRM_DUMB_VGA_DAC=m
 CONFIG_DRM_NXP_PTN3460=m
 CONFIG_DRM_PARADE_PS8622=m
+CONFIG_DRM_SII902X=m
 CONFIG_DRM_SII9234=m
 CONFIG_DRM_TOSHIBA_TC358764=m
 CONFIG_DRM_I2C_ADV7511=m
@@ -641,7 +646,7 @@ CONFIG_DRM_STM_DSI=m
 CONFIG_DRM_VC4=m
 CONFIG_DRM_ETNAVIV=m
 CONFIG_DRM_MXSFB=m
-CONFIG_FB_ARMCLCD=y
+CONFIG_DRM_PL111=m
 CONFIG_FB_EFI=y
 CONFIG_FB_WM8505=y
 CONFIG_FB_SH_MOBILE_LCDC=y
@@ -826,6 +831,7 @@ CONFIG_RTC_DRV_MAX8997=m
 CONFIG_RTC_DRV_MAX77686=y
 CONFIG_RTC_DRV_RK808=m
 CONFIG_RTC_DRV_RS5C372=m
+CONFIG_RTC_DRV_PCF85363=m
 CONFIG_RTC_DRV_BQ32K=m
 CONFIG_RTC_DRV_TWL4030=y
 CONFIG_RTC_DRV_PALMAS=y
@@ -1028,3 +1034,5 @@ CONFIG_CRYPTO_AES_ARM_CE=m
 CONFIG_CRYPTO_GHASH_ARM_CE=m
 CONFIG_CRYPTO_CRC32_ARM_CE=m
 CONFIG_CRYPTO_CHACHA20_NEON=m
+CONFIG_GCC_PLUGINS=y
+CONFIG_GCC_PLUGIN_STRUCTLEAK=y
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index 0ac44acd5bc4..5f4c6aaa07f6 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ_IDLE=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -10,16 +11,16 @@ CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 CONFIG_KALLSYMS_ALL=y
 CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
 # CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_NOMADIK=y
 CONFIG_MACH_NOMADIK_8815NHK=y
-CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_CMA=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -49,12 +50,12 @@ CONFIG_MTD=y
 CONFIG_MTD_TESTS=m
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND_ECC_SMC=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_FSMC=y
 CONFIG_MTD_ONENAND=y
 CONFIG_MTD_ONENAND_VERIFY_WRITE=y
 CONFIG_MTD_ONENAND_GENERIC=y
+CONFIG_MTD_NAND_ECC_SMC=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=y
 CONFIG_BLK_DEV_RAM=y
@@ -75,7 +76,6 @@ CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
 CONFIG_PPP_ASYNC=m
 CONFIG_PPP_SYNC_TTY=m
-# CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_GPIO=y
@@ -88,13 +88,22 @@ CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
-CONFIG_DEBUG_GPIO=y
+CONFIG_SPI=y
+CONFIG_SPI_GPIO=y
 CONFIG_GPIO_STMPE=y
 # CONFIG_HWMON is not set
 CONFIG_MFD_STMPE=y
+CONFIG_MFD_STW481X=y
 CONFIG_REGULATOR=y
+CONFIG_DRM=y
+CONFIG_DRM_PANEL_TPO_TPG110=y
+CONFIG_DRM_PL111=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
 CONFIG_MMC=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ARMMMCI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
@@ -105,6 +114,11 @@ CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_DMADEVICES=y
 CONFIG_AMBA_PL08X=y
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_ST_ACCEL_3AXIS=y
+CONFIG_PWM=y
+CONFIG_PWM_STMPE=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 CONFIG_FUSE_FS=y
@@ -121,13 +135,12 @@ CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_DES=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/configs/nuc910_defconfig b/arch/arm/configs/nuc910_defconfig
index a72653645f9d..c0d152c02fba 100644
--- a/arch/arm/configs/nuc910_defconfig
+++ b/arch/arm/configs/nuc910_defconfig
@@ -47,7 +47,6 @@ CONFIG_ROMFS_FS=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/nuc950_defconfig b/arch/arm/configs/nuc950_defconfig
index 614a0a28d0b4..8dde1186c2ef 100644
--- a/arch/arm/configs/nuc950_defconfig
+++ b/arch/arm/configs/nuc950_defconfig
@@ -64,6 +64,5 @@ CONFIG_ROMFS_FS=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_DEBUG_FS=y
diff --git a/arch/arm/configs/nuc960_defconfig b/arch/arm/configs/nuc960_defconfig
index b84bbd216153..6bb784f8eb5b 100644
--- a/arch/arm/configs/nuc960_defconfig
+++ b/arch/arm/configs/nuc960_defconfig
@@ -53,7 +53,6 @@ CONFIG_ROMFS_FS=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 9c6f436d1b12..3f03ec6d2644 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -25,16 +25,6 @@ CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 CONFIG_SLAB=y
 CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-CONFIG_KPROBES=y
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_MULTI_V6=y
 CONFIG_POWER_AVS_OMAP=y
 CONFIG_POWER_AVS_OMAP_CLASS3=y
@@ -48,15 +38,8 @@ CONFIG_SOC_AM43XX=y
 CONFIG_SOC_DRA7XX=y
 CONFIG_ARM_THUMBEE=y
 CONFIG_ARM_ERRATA_411920=y
-CONFIG_PCI=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_DRA7XX_EP=y
-CONFIG_PCI_ENDPOINT=y
-CONFIG_PCI_ENDPOINT_CONFIGFS=y
-CONFIG_PCI_EPF_TEST=m
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
-CONFIG_CMA=y
 CONFIG_SECCOMP=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
@@ -74,8 +57,27 @@ CONFIG_CPUFREQ_DT=m
 CONFIG_ARM_TI_CPUFREQ=y
 CONFIG_CPU_IDLE=y
 CONFIG_KERNEL_MODE_NEON=y
-CONFIG_BINFMT_MISC=y
 CONFIG_PM_DEBUG=y
+CONFIG_ARM_CRYPTO=y
+CONFIG_CRYPTO_SHA1_ARM_NEON=m
+CONFIG_CRYPTO_SHA256_ARM=m
+CONFIG_CRYPTO_SHA512_ARM=m
+CONFIG_CRYPTO_AES_ARM=m
+CONFIG_CRYPTO_AES_ARM_BS=m
+CONFIG_CRYPTO_GHASH_ARM_CE=m
+CONFIG_CRYPTO_CHACHA20_NEON=m
+CONFIG_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_BINFMT_MISC=y
+CONFIG_CMA=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -118,6 +120,12 @@ CONFIG_AF_RXRPC=m
 CONFIG_RXKAD=y
 CONFIG_CFG80211=m
 CONFIG_MAC80211=m
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_DRA7XX_EP=y
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PCI_ENDPOINT_CONFIGFS=y
+CONFIG_PCI_EPF_TEST=m
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_DMA_CMA=y
@@ -132,13 +140,13 @@ CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_M25P80=m
+CONFIG_MTD_ONENAND=y
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+CONFIG_MTD_ONENAND_OMAP2=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ECC_BCH=y
 CONFIG_MTD_NAND_OMAP2=y
 CONFIG_MTD_NAND_OMAP_BCH=y
-CONFIG_MTD_ONENAND=y
-CONFIG_MTD_ONENAND_VERIFY_WRITE=y
-CONFIG_MTD_ONENAND_OMAP2=y
 CONFIG_MTD_SPI_NOR=m
 CONFIG_MTD_UBI=y
 CONFIG_BLK_DEV_LOOP=y
@@ -155,7 +163,6 @@ CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_AHCI_DM816=m
 CONFIG_NETDEVICES=y
 # CONFIG_NET_VENDOR_ARC is not set
-# CONFIG_NET_CADENCE is not set
 # CONFIG_NET_VENDOR_BROADCOM is not set
 # CONFIG_NET_VENDOR_CIRRUS is not set
 CONFIG_DM9000=y
@@ -283,11 +290,9 @@ CONFIG_HWMON=m
 CONFIG_SENSORS_GPIO_FAN=m
 CONFIG_SENSORS_LM75=m
 CONFIG_SENSORS_TMP102=m
-CONFIG_THERMAL=m
 CONFIG_THERMAL_GOV_FAIR_SHARE=y
 CONFIG_THERMAL_GOV_USER_SPACE=y
 CONFIG_CPU_THERMAL=y
-CONFIG_TI_SOC_THERMAL=m
 CONFIG_TI_THERMAL=y
 CONFIG_OMAP4_THERMAL=y
 CONFIG_OMAP5_THERMAL=y
@@ -381,13 +386,12 @@ CONFIG_SND_VERBOSE_PRINTK=y
 CONFIG_SND_DEBUG=y
 CONFIG_SND_USB_AUDIO=m
 CONFIG_SND_SOC=m
-CONFIG_SND_SOC_TLV320AIC3X=m
 CONFIG_SND_SOC_DAVINCI_MCASP=m
 CONFIG_SND_SOC_NOKIA_RX51=m
-CONFIG_SND_SOC_OMAP_HDMI=m
-CONFIG_SND_SOC_OMAP_ABE_TWL6040=m
 CONFIG_SND_SOC_OMAP3_PANDORA=m
 CONFIG_SND_SOC_OMAP3_TWL4030=m
+CONFIG_SND_SOC_OMAP_ABE_TWL6040=m
+CONFIG_SND_SOC_OMAP_HDMI=m
 CONFIG_SND_SOC_CPCAP=m
 CONFIG_SND_SOC_TLV320AIC23_I2C=m
 CONFIG_SND_SIMPLE_CARD=m
@@ -475,8 +479,6 @@ CONFIG_RTC_DRV_PALMAS=m
 CONFIG_RTC_DRV_OMAP=m
 CONFIG_RTC_DRV_CPCAP=m
 CONFIG_DMADEVICES=y
-CONFIG_DMA_OMAP=y
-CONFIG_TI_EDMA=y
 CONFIG_OMAP_IOMMU=y
 CONFIG_REMOTEPROC=m
 CONFIG_OMAP_REMOTEPROC=m
@@ -531,24 +533,8 @@ CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_INFO_SPLIT=y
-CONFIG_DEBUG_INFO_DWARF4=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_SCHEDSTATS=y
-CONFIG_PROVE_LOCKING=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_SECURITY=y
 CONFIG_CRYPTO_MICHAEL_MIC=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_CRYPTO_SHA1_ARM_NEON=m
-CONFIG_CRYPTO_SHA256_ARM=m
-CONFIG_CRYPTO_SHA512_ARM=m
-CONFIG_CRYPTO_AES_ARM=m
-CONFIG_CRYPTO_AES_ARM_BS=m
-CONFIG_CRYPTO_GHASH_ARM_CE=m
-CONFIG_CRYPTO_CHACHA20_NEON=m
 CONFIG_CRC_CCITT=y
 CONFIG_CRC_T10DIF=y
 CONFIG_CRC_ITU_T=y
@@ -557,3 +543,10 @@ CONFIG_LIBCRC32C=y
 CONFIG_FONTS=y
 CONFIG_FONT_8x8=y
 CONFIG_FONT_8x16=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_SPLIT=y
+CONFIG_DEBUG_INFO_DWARF4=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_SCHEDSTATS=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
diff --git a/arch/arm/configs/pxa_defconfig b/arch/arm/configs/pxa_defconfig
index 6bb506edb1f5..d4654755b09c 100644
--- a/arch/arm/configs/pxa_defconfig
+++ b/arch/arm/configs/pxa_defconfig
@@ -66,9 +66,6 @@ CONFIG_MACH_MIOA701=y
 CONFIG_PXA_EZX=y
 CONFIG_MACH_MP900C=y
 CONFIG_ARCH_PXA_PALM=y
-CONFIG_MACH_RAUMFELD_RC=y
-CONFIG_MACH_RAUMFELD_CONNECTOR=y
-CONFIG_MACH_RAUMFELD_SPEAKER=y
 CONFIG_PXA_SHARPSL=y
 CONFIG_MACH_POODLE=y
 CONFIG_MACH_CORGI=y
@@ -482,7 +479,6 @@ CONFIG_SND_PCM_OSS=m
 CONFIG_SND_DYNAMIC_MINORS=y
 CONFIG_SND_VERBOSE_PRINTK=y
 CONFIG_SND_DEBUG=y
-CONFIG_SND_PXA2XX_AC97=m
 CONFIG_SND_USB_AUDIO=m
 CONFIG_SND_SOC=m
 CONFIG_SND_ATMEL_SOC=m
@@ -498,7 +494,6 @@ CONFIG_SND_PXA2XX_SOC_E800=m
 CONFIG_SND_PXA2XX_SOC_EM_X270=m
 CONFIG_SND_PXA2XX_SOC_PALM27X=y
 CONFIG_SND_SOC_ZYLONITE=m
-CONFIG_SND_SOC_RAUMFELD=m
 CONFIG_SND_PXA2XX_SOC_HX4700=m
 CONFIG_SND_PXA2XX_SOC_MAGICIAN=m
 CONFIG_SND_PXA2XX_SOC_MIOA701=m
diff --git a/arch/arm/configs/raumfeld_defconfig b/arch/arm/configs/raumfeld_defconfig
deleted file mode 100644
index 2dd56e9a484e..000000000000
--- a/arch/arm/configs/raumfeld_defconfig
+++ /dev/null
@@ -1,197 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
-CONFIG_MACH_RAUMFELD_RC=y
-CONFIG_MACH_RAUMFELD_CONNECTOR=y
-CONFIG_MACH_RAUMFELD_SPEAKER=y
-CONFIG_NO_HZ=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_CMDLINE="console=ttyS0,115200 rw"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_IDLE=y
-CONFIG_PM=y
-CONFIG_APM_EMULATION=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_SYN_COOKIES=y
-CONFIG_IPV6=y
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_NFTL=y
-CONFIG_NFTL_RW=y
-CONFIG_MTD_BLOCK2MTD=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_MARVELL=y
-CONFIG_MTD_UBI=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_ISL29003=y
-CONFIG_IIO=y
-CONFIG_AD5446=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMSC911X=y
-CONFIG_LIBERTAS=y
-CONFIG_LIBERTAS_SDIO=m
-CONFIG_USB_USBNET=y
-# CONFIG_USB_NET_AX8817X is not set
-# CONFIG_USB_NET_NET1080 is not set
-CONFIG_USB_NET_MCS7830=y
-# CONFIG_USB_NET_CDC_SUBSET is not set
-# CONFIG_USB_NET_ZAURUS is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_EETI=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_GPIO_ROTARY_ENCODER=y
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_PXA=y
-CONFIG_SPI=y
-CONFIG_SPI_DEBUG=y
-CONFIG_SPI_GPIO=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_DEBUG_GPIO=y
-CONFIG_W1_MASTER_GPIO=m
-CONFIG_POWER_SUPPLY=y
-CONFIG_PDA_POWER=y
-CONFIG_BATTERY_DS2760=m
-CONFIG_SENSORS_LIS3_SPI=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_DEBUG=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_MAX8660=y
-CONFIG_FB=y
-CONFIG_FB_PXA=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_BACKLIGHT_PWM=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_PXA2XX_SOC=y
-CONFIG_SND_SOC_RAUMFELD=y
-CONFIG_HID_DRAGONRISE=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-CONFIG_HID_SMARTJOYPLUS=y
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-CONFIG_HID_ZEROPLUS=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_STORAGE_FREECOM=y
-CONFIG_USB_STORAGE_ISD200=y
-CONFIG_USB_STORAGE_USBAT=y
-CONFIG_USB_STORAGE_SDDR09=y
-CONFIG_USB_STORAGE_SDDR55=y
-CONFIG_MMC=y
-CONFIG_MMC_PXA=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_LT3593=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_PXA=y
-CONFIG_DMADEVICES=y
-CONFIG_UIO=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XIP=y
-CONFIG_EXT3_FS=y
-CONFIG_FSCACHE=y
-CONFIG_FSCACHE_STATS=y
-CONFIG_CACHEFILES=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_UBIFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFS_FSCACHE=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_737=y
-CONFIG_NLS_CODEPAGE_775=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_CODEPAGE_852=y
-CONFIG_NLS_CODEPAGE_855=y
-CONFIG_NLS_CODEPAGE_857=y
-CONFIG_NLS_CODEPAGE_860=y
-CONFIG_NLS_CODEPAGE_861=y
-CONFIG_NLS_CODEPAGE_862=y
-CONFIG_NLS_CODEPAGE_863=y
-CONFIG_NLS_CODEPAGE_864=y
-CONFIG_NLS_CODEPAGE_865=y
-CONFIG_NLS_CODEPAGE_866=y
-CONFIG_NLS_CODEPAGE_869=y
-CONFIG_NLS_CODEPAGE_936=y
-CONFIG_NLS_CODEPAGE_950=y
-CONFIG_NLS_CODEPAGE_932=y
-CONFIG_NLS_CODEPAGE_949=y
-CONFIG_NLS_CODEPAGE_874=y
-CONFIG_NLS_ISO8859_8=y
-CONFIG_NLS_CODEPAGE_1250=y
-CONFIG_NLS_CODEPAGE_1251=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=y
-CONFIG_NLS_ISO8859_3=y
-CONFIG_NLS_ISO8859_4=y
-CONFIG_NLS_ISO8859_5=y
-CONFIG_NLS_ISO8859_6=y
-CONFIG_NLS_ISO8859_7=y
-CONFIG_NLS_ISO8859_9=y
-CONFIG_NLS_ISO8859_13=y
-CONFIG_NLS_ISO8859_14=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_KOI8_R=y
-CONFIG_NLS_KOI8_U=y
-CONFIG_NLS_UTF8=y
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
diff --git a/arch/arm/configs/s5pv210_defconfig b/arch/arm/configs/s5pv210_defconfig
index a077597369f1..fd4f28aabda6 100644
--- a/arch/arm/configs/s5pv210_defconfig
+++ b/arch/arm/configs/s5pv210_defconfig
@@ -1,24 +1,30 @@
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
 CONFIG_CGROUPS=y
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_KALLSYMS_ALL=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_SOLARIS_X86_PARTITION=y
 CONFIG_ARCH_S5PV210=y
 CONFIG_VMSPLIT_2G=y
-CONFIG_PREEMPT=y
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_USERSPACE=m
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
 CONFIG_VFP=y
 CONFIG_NEON=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_SOLARIS_X86_PARTITION=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -27,6 +33,11 @@ CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 CONFIG_IP_PNP_RARP=y
+CONFIG_BT=m
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_BCM=y
 CONFIG_CFG80211=m
 CONFIG_MAC80211=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
@@ -44,21 +55,35 @@ CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=m
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_PWM_VIBRA=m
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_SAMSUNG=y
 CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
 CONFIG_HW_RANDOM=y
 CONFIG_I2C_GPIO=y
+CONFIG_I2C_S3C2410=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
 CONFIG_POWER_SUPPLY=y
 CONFIG_BATTERY_MAX17040=y
 # CONFIG_HWMON is not set
 CONFIG_MFD_MAX8998=y
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_MAX8998=y
+CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m
+CONFIG_VIDEO_SAMSUNG_S5P_MFC=m
 CONFIG_DRM=y
 CONFIG_DRM_EXYNOS=y
 CONFIG_DRM_EXYNOS_FIMD=y
 CONFIG_DRM_EXYNOS_DPI=y
+CONFIG_DRM_EXYNOS_ROTATOR=y
 CONFIG_USB=y
 CONFIG_USB_OTG=y
 CONFIG_USB_EHCI_HCD=y
@@ -72,6 +97,9 @@ CONFIG_MMC_SDHCI_S3C=y
 CONFIG_MMC_SDHCI_S3C_DMA=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_MAX8998=m
+CONFIG_DMADEVICES=y
+CONFIG_PWM=y
+CONFIG_PWM_SAMSUNG=y
 CONFIG_PHY_SAMSUNG_USB2=m
 CONFIG_PHY_S5PV210_USB2=y
 CONFIG_EXT2_FS=y
@@ -87,6 +115,7 @@ CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_UTF8=y
+CONFIG_CRC_CCITT=y
 CONFIG_DEBUG_INFO=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_KERNEL=y
@@ -96,7 +125,3 @@ CONFIG_DEBUG_SPINLOCK=y
 CONFIG_DEBUG_MUTEXES=y
 CONFIG_DEBUG_ATOMIC_SLEEP=y
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_S3C_UART1=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index 9e5a5ade6cab..9b0efac101ab 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -8,29 +8,8 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 CONFIG_ARCH_RENESAS=y
-CONFIG_ARCH_EMEV2=y
-CONFIG_ARCH_R7S72100=y
-CONFIG_ARCH_R8A73A4=y
-CONFIG_ARCH_R8A7740=y
-CONFIG_ARCH_R8A7743=y
-CONFIG_ARCH_R8A7744=y
-CONFIG_ARCH_R8A7745=y
-CONFIG_ARCH_R8A77470=y
-CONFIG_ARCH_R8A7778=y
-CONFIG_ARCH_R8A7779=y
-CONFIG_ARCH_R8A7790=y
-CONFIG_ARCH_R8A7791=y
-CONFIG_ARCH_R8A7792=y
-CONFIG_ARCH_R8A7793=y
-CONFIG_ARCH_R8A7794=y
-CONFIG_ARCH_R9A06G032=y
-CONFIG_ARCH_SH73A0=y
 CONFIG_PL310_ERRATA_588369=y
 CONFIG_ARM_ERRATA_754322=y
-CONFIG_PCI=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_RCAR_GEN2=y
-CONFIG_PCIE_RCAR=y
 CONFIG_SMP=y
 CONFIG_SCHED_MC=y
 CONFIG_NR_CPUS=8
@@ -58,6 +37,10 @@ CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_CAN=y
 CONFIG_CAN_RCAR=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_RCAR_GEN2=y
+CONFIG_PCIE_RCAR=y
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_DMA_CMA=y
@@ -91,7 +74,6 @@ CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_8250_EM=y
 CONFIG_SERIAL_SH_SCI=y
 CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MUX=y
 CONFIG_I2C_DEMUX_PINCTRL=y
 CONFIG_I2C_EMEV2=y
 CONFIG_I2C_GPIO=y
@@ -104,6 +86,7 @@ CONFIG_SPI_RSPI=y
 CONFIG_SPI_SH_MSIOF=y
 CONFIG_SPI_SH_HSPI=y
 CONFIG_PINCTRL_RZA1=y
+CONFIG_PINCTRL_RZA2=y
 CONFIG_GPIO_EM=y
 CONFIG_GPIO_RCAR=y
 CONFIG_GPIO_PCF857X=y
@@ -177,17 +160,35 @@ CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_RS5C372=y
+CONFIG_RTC_DRV_PCF85363=y
 CONFIG_RTC_DRV_BQ32K=y
 CONFIG_RTC_DRV_S35390A=y
 CONFIG_RTC_DRV_RX8581=y
 CONFIG_RTC_DRV_DA9063=y
 CONFIG_DMADEVICES=y
-CONFIG_SH_DMAE=y
 CONFIG_RCAR_DMAC=y
 CONFIG_RENESAS_USB_DMAC=y
 CONFIG_STAGING=y
 CONFIG_STAGING_BOARD=y
 # CONFIG_IOMMU_SUPPORT is not set
+CONFIG_ARCH_EMEV2=y
+CONFIG_ARCH_R7S72100=y
+CONFIG_ARCH_R7S9210=y
+CONFIG_ARCH_R8A73A4=y
+CONFIG_ARCH_R8A7740=y
+CONFIG_ARCH_R8A7743=y
+CONFIG_ARCH_R8A7744=y
+CONFIG_ARCH_R8A7745=y
+CONFIG_ARCH_R8A77470=y
+CONFIG_ARCH_R8A7778=y
+CONFIG_ARCH_R8A7779=y
+CONFIG_ARCH_R8A7790=y
+CONFIG_ARCH_R8A7791=y
+CONFIG_ARCH_R8A7792=y
+CONFIG_ARCH_R8A7793=y
+CONFIG_ARCH_R8A7794=y
+CONFIG_ARCH_R9A06G032=y
+CONFIG_ARCH_SH73A0=y
 CONFIG_IIO=y
 CONFIG_AK8975=y
 CONFIG_PWM=y
@@ -211,4 +212,3 @@ CONFIG_NLS_ISO8859_1=y
 CONFIG_PRINTK_TIME=y
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
-# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index 371fca4e1ab7..08d1b3e11d68 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -9,27 +9,20 @@ CONFIG_NAMESPACES=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EMBEDDED=y
 CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ARM_THUMBEE=y
-CONFIG_PCI=y
-CONFIG_PCI_MSI=y
-CONFIG_PCIE_ALTERA=y
-CONFIG_PCIE_ALTERA_MSI=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
-CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_VFP=y
 CONFIG_NEON=y
+CONFIG_OPROFILE=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -48,6 +41,10 @@ CONFIG_CAN=y
 CONFIG_CAN_C_CAN=y
 CONFIG_CAN_C_CAN_PLATFORM=y
 CONFIG_CAN_DEBUG_DEVICES=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIE_ALTERA=y
+CONFIG_PCIE_ALTERA_MSI=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -60,7 +57,7 @@ CONFIG_MTD_SPI_NOR=y
 # CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
 CONFIG_SPI_CADENCE_QUADSPI=y
 CONFIG_OF_OVERLAY=y
-CONFIG_OF_CONFIGFS=y
+CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=2
 CONFIG_BLK_DEV_RAM_SIZE=8192
@@ -131,12 +128,12 @@ CONFIG_DMADEVICES=y
 CONFIG_PL330_DMA=y
 CONFIG_DMATEST=m
 CONFIG_FPGA=y
-CONFIG_FPGA_REGION=y
 CONFIG_FPGA_MGR_SOCFPGA=y
 CONFIG_FPGA_MGR_SOCFPGA_A10=y
 CONFIG_FPGA_BRIDGE=y
 CONFIG_SOCFPGA_FPGA_BRIDGE=y
 CONFIG_ALTERA_FREEZE_BRIDGE=y
+CONFIG_FPGA_REGION=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
index 2c5e8df33191..f1b52fb3461b 100644
--- a/arch/arm/configs/spear3xx_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -52,8 +52,10 @@ CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_ARM_SP805_WATCHDOG=y
-CONFIG_FB=y
-CONFIG_FB_ARMCLCD=y
+CONFIG_DRM=y
+CONFIG_DRM_PL111=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index ba805b757a8d..0258ba891376 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -80,7 +80,6 @@ CONFIG_EXT3_FS=y
 CONFIG_NLS=y
 CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_SCHED_DEBUG is not set
diff --git a/arch/arm/crypto/aes-ce-core.S b/arch/arm/crypto/aes-ce-core.S
index ba8e6a32fdc9..bc53bcaa772e 100644
--- a/arch/arm/crypto/aes-ce-core.S
+++ b/arch/arm/crypto/aes-ce-core.S
@@ -317,25 +317,27 @@ ENTRY(ce_aes_ctr_encrypt)
 .Lctrloop:
         vmov            q0, q6
         bl              aes_encrypt
-        subs            r4, r4, #1
-        bmi             .Lctrtailblock          @ blocks < 0 means tail block
-        vld1.8          {q3}, [r1]!
-        veor            q3, q0, q3
-        vst1.8          {q3}, [r0]!
 
         adds            r6, r6, #1              @ increment BE ctr
         rev             ip, r6
         vmov            s27, ip
         bcs             .Lctrcarry
-        teq             r4, #0
+
+.Lctrcarrydone:
+        subs            r4, r4, #1
+        bmi             .Lctrtailblock          @ blocks < 0 means tail block
+        vld1.8          {q3}, [r1]!
+        veor            q3, q0, q3
+        vst1.8          {q3}, [r0]!
         bne             .Lctrloop
+
 .Lctrout:
-        vst1.8          {q6}, [r5]
+        vst1.8          {q6}, [r5]              @ return next CTR value
         pop             {r4-r6, pc}
 
 .Lctrtailblock:
-        vst1.8          {q0}, [r0, :64]         @ return just the key stream
-        pop             {r4-r6, pc}
+        vst1.8          {q0}, [r0, :64]         @ return the key stream
+        b               .Lctrout
 
 .Lctrcarry:
         .irp            sreg, s26, s25, s24
@@ -344,11 +346,9 @@ ENTRY(ce_aes_ctr_encrypt)
         adds            ip, ip, #1
         rev             ip, ip
         vmov            \sreg, ip
-        bcc             0f
+        bcc             .Lctrcarrydone
         .endr
-0:      teq             r4, #0
-        beq             .Lctrout
-        b               .Lctrloop
+        b               .Lctrcarrydone
 ENDPROC(ce_aes_ctr_encrypt)
 
         /*
diff --git a/arch/arm/crypto/crct10dif-ce-core.S b/arch/arm/crypto/crct10dif-ce-core.S
index ce45ba0c0687..86be258a803f 100644
--- a/arch/arm/crypto/crct10dif-ce-core.S
+++ b/arch/arm/crypto/crct10dif-ce-core.S
@@ -2,12 +2,14 @@
 // Accelerated CRC-T10DIF using ARM NEON and Crypto Extensions instructions
 //
 // Copyright (C) 2016 Linaro Ltd <ard.biesheuvel@linaro.org>
+// Copyright (C) 2019 Google LLC <ebiggers@google.com>
 //
 // This program is free software; you can redistribute it and/or modify
 // it under the terms of the GNU General Public License version 2 as
 // published by the Free Software Foundation.
 //
 
+// Derived from the x86 version:
 //
 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
 //
@@ -54,19 +56,11 @@
 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 //
-//       Function API:
-//       UINT16 crc_t10dif_pcl(
-//               UINT16 init_crc, //initial CRC value, 16 bits
-//               const unsigned char *buf, //buffer pointer to calculate CRC on
-//               UINT64 len //buffer length in bytes (64-bit data)
-//       );
-//
 //       Reference paper titled "Fast CRC Computation for Generic
 //      Polynomials Using PCLMULQDQ Instruction"
 //       URL: http://www.intel.com/content/dam/www/public/us/en/documents
 //  /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
 //
-//
 
 #include <linux/linkage.h>
 #include <asm/assembler.h>
@@ -78,13 +72,14 @@
 #endif
 
         .text
+        .arch           armv7-a
         .fpu            crypto-neon-fp-armv8
 
-        arg1_low32      .req    r0
-        arg2            .req    r1
-        arg3            .req    r2
+        init_crc        .req    r0
+        buf             .req    r1
+        len             .req    r2
 
-        qzr             .req    q13
+        fold_consts_ptr .req    ip
 
         q0l             .req    d0
         q0h             .req    d1
@@ -102,82 +97,35 @@
         q6h             .req    d13
         q7l             .req    d14
         q7h             .req    d15
-
-ENTRY(crc_t10dif_pmull)
-        vmov.i8         qzr, #0                 // init zero register
-
-        // adjust the 16-bit initial_crc value, scale it to 32 bits
-        lsl             arg1_low32, arg1_low32, #16
-
-        // check if smaller than 256
-        cmp             arg3, #256
-
-        // for sizes less than 128, we can't fold 64B at a time...
-        blt             _less_than_128
-
-        // load the initial crc value
-        // crc value does not need to be byte-reflected, but it needs
-        // to be moved to the high part of the register.
-        // because data will be byte-reflected and will align with
-        // initial crc at correct place.
-        vmov            s0, arg1_low32          // initial crc
-        vext.8          q10, qzr, q0, #4
-
-        // receive the initial 64B data, xor the initial crc value
-        vld1.64         {q0-q1}, [arg2, :128]!
-        vld1.64         {q2-q3}, [arg2, :128]!
-        vld1.64         {q4-q5}, [arg2, :128]!
-        vld1.64         {q6-q7}, [arg2, :128]!
-CPU_LE( vrev64.8        q0, q0                  )
-CPU_LE( vrev64.8        q1, q1                  )
-CPU_LE( vrev64.8        q2, q2                  )
-CPU_LE( vrev64.8        q3, q3                  )
-CPU_LE( vrev64.8        q4, q4                  )
-CPU_LE( vrev64.8        q5, q5                  )
-CPU_LE( vrev64.8        q6, q6                  )
-CPU_LE( vrev64.8        q7, q7                  )
-
-        vswp            d0, d1
-        vswp            d2, d3
-        vswp            d4, d5
-        vswp            d6, d7
-        vswp            d8, d9
-        vswp            d10, d11
-        vswp            d12, d13
-        vswp            d14, d15
-
-        // XOR the initial_crc value
-        veor.8          q0, q0, q10
-
-        adr             ip, rk3
-        vld1.64         {q10}, [ip, :128]       // xmm10 has rk3 and rk4
-
-        //
-        // we subtract 256 instead of 128 to save one instruction from the loop
-        //
-        sub             arg3, arg3, #256
-
-        // at this section of the code, there is 64*x+y (0<=y<64) bytes of
-        // buffer. The _fold_64_B_loop will fold 64B at a time
-        // until we have 64+y Bytes of buffer
-
-
-        // fold 64B at a time. This section of the code folds 4 vector
-        // registers in parallel
-_fold_64_B_loop:
-
-        .macro          fold64, reg1, reg2
-        vld1.64         {q11-q12}, [arg2, :128]!
-
-        vmull.p64       q8, \reg1\()h, d21
-        vmull.p64       \reg1, \reg1\()l, d20
-        vmull.p64       q9, \reg2\()h, d21
-        vmull.p64       \reg2, \reg2\()l, d20
-
-CPU_LE( vrev64.8        q11, q11                )
-CPU_LE( vrev64.8        q12, q12                )
-        vswp            d22, d23
-        vswp            d24, d25
+        q8l             .req    d16
+        q8h             .req    d17
+        q9l             .req    d18
+        q9h             .req    d19
+        q10l            .req    d20
+        q10h            .req    d21
+        q11l            .req    d22
+        q11h            .req    d23
+        q12l            .req    d24
+        q12h            .req    d25
+
+        FOLD_CONSTS     .req    q10
+        FOLD_CONST_L    .req    q10l
+        FOLD_CONST_H    .req    q10h
+
+        // Fold reg1, reg2 into the next 32 data bytes, storing the result back
+        // into reg1, reg2.
+        .macro          fold_32_bytes, reg1, reg2
+        vld1.64         {q11-q12}, [buf]!
+
+        vmull.p64       q8, \reg1\()h, FOLD_CONST_H
+        vmull.p64       \reg1, \reg1\()l, FOLD_CONST_L
+        vmull.p64       q9, \reg2\()h, FOLD_CONST_H
+        vmull.p64       \reg2, \reg2\()l, FOLD_CONST_L
+
+CPU_LE( vrev64.8        q11, q11        )
+CPU_LE( vrev64.8        q12, q12        )
+        vswp            q11l, q11h
+        vswp            q12l, q12h
 
         veor.8          \reg1, \reg1, q8
         veor.8          \reg2, \reg2, q9
@@ -185,242 +133,248 @@ CPU_LE(	vrev64.8	q12, q12		)
         veor.8          \reg2, \reg2, q12
         .endm
 
-        fold64          q0, q1
-        fold64          q2, q3
-        fold64          q4, q5
-        fold64          q6, q7
-
-        subs            arg3, arg3, #128
-
-        // check if there is another 64B in the buffer to be able to fold
-        bge             _fold_64_B_loop
-
-        // at this point, the buffer pointer is pointing at the last y Bytes
-        // of the buffer the 64B of folded data is in 4 of the vector
-        // registers: v0, v1, v2, v3
-
-        // fold the 8 vector registers to 1 vector register with different
-        // constants
-
-        adr             ip, rk9
-        vld1.64         {q10}, [ip, :128]!
-
-        .macro          fold16, reg, rk
-        vmull.p64       q8, \reg\()l, d20
-        vmull.p64       \reg, \reg\()h, d21
-        .ifnb           \rk
-        vld1.64         {q10}, [ip, :128]!
+        // Fold src_reg into dst_reg, optionally loading the next fold constants
+        .macro          fold_16_bytes, src_reg, dst_reg, load_next_consts
+        vmull.p64       q8, \src_reg\()l, FOLD_CONST_L
+        vmull.p64       \src_reg, \src_reg\()h, FOLD_CONST_H
+        .ifnb           \load_next_consts
+        vld1.64         {FOLD_CONSTS}, [fold_consts_ptr, :128]!
         .endif
-        veor.8          q7, q7, q8
-        veor.8          q7, q7, \reg
+        veor.8          \dst_reg, \dst_reg, q8
+        veor.8          \dst_reg, \dst_reg, \src_reg
         .endm
 
-        fold16          q0, rk11
-        fold16          q1, rk13
-        fold16          q2, rk15
-        fold16          q3, rk17
-        fold16          q4, rk19
-        fold16          q5, rk1
-        fold16          q6
-
-        // instead of 64, we add 48 to the loop counter to save 1 instruction
-        // from the loop instead of a cmp instruction, we use the negative
-        // flag with the jl instruction
-        adds            arg3, arg3, #(128-16)
-        blt             _final_reduction_for_128
-
-        // now we have 16+y bytes left to reduce. 16 Bytes is in register v7
-        // and the rest is in memory. We can fold 16 bytes at a time if y>=16
-        // continue folding 16B at a time
-
-_16B_reduction_loop:
-        vmull.p64       q8, d14, d20
-        vmull.p64       q7, d15, d21
-        veor.8          q7, q7, q8
+        .macro          __adrl, out, sym
+        movw            \out, #:lower16:\sym
+        movt            \out, #:upper16:\sym
+        .endm
 
-        vld1.64         {q0}, [arg2, :128]!
-CPU_LE( vrev64.8        q0, q0          )
-        vswp            d0, d1
-        veor.8          q7, q7, q0
-        subs            arg3, arg3, #16
-
-        // instead of a cmp instruction, we utilize the flags with the
-        // jge instruction equivalent of: cmp arg3, 16-16
-        // check if there is any more 16B in the buffer to be able to fold
-        bge             _16B_reduction_loop
-
-        // now we have 16+z bytes left to reduce, where 0<= z < 16.
-        // first, we reduce the data in the xmm7 register
-
-_final_reduction_for_128:
-        // check if any more data to fold. If not, compute the CRC of
-        // the final 128 bits
-        adds            arg3, arg3, #16
-        beq             _128_done
-
-        // here we are getting data that is less than 16 bytes.
-        // since we know that there was data before the pointer, we can
-        // offset the input pointer before the actual point, to receive
-        // exactly 16 bytes. after that the registers need to be adjusted.
-_get_last_two_regs:
-        add             arg2, arg2, arg3
-        sub             arg2, arg2, #16
-        vld1.64         {q1}, [arg2]
-CPU_LE( vrev64.8        q1, q1                  )
-        vswp            d2, d3
-
-        // get rid of the extra data that was loaded before
-        // load the shift constant
-        adr             ip, tbl_shf_table + 16
-        sub             ip, ip, arg3
-        vld1.8          {q0}, [ip]
-
-        // shift v2 to the left by arg3 bytes
-        vtbl.8          d4, {d14-d15}, d0
-        vtbl.8          d5, {d14-d15}, d1
-
-        // shift v7 to the right by 16-arg3 bytes
-        vmov.i8         q9, #0x80
-        veor.8          q0, q0, q9
-        vtbl.8          d18, {d14-d15}, d0
-        vtbl.8          d19, {d14-d15}, d1
-
-        // blend
-        vshr.s8         q0, q0, #7              // convert to 8-bit mask
-        vbsl.8          q0, q2, q1
-
-        // fold 16 Bytes
-        vmull.p64       q8, d18, d20
-        vmull.p64       q7, d19, d21
+//
+// u16 crc_t10dif_pmull(u16 init_crc, const u8 *buf, size_t len);
+//
+// Assumes len >= 16.
+//
+ENTRY(crc_t10dif_pmull)
+
+        // For sizes less than 256 bytes, we can't fold 128 bytes at a time.
+        cmp             len, #256
+        blt             .Lless_than_256_bytes
+
+        __adrl          fold_consts_ptr, .Lfold_across_128_bytes_consts
+
+        // Load the first 128 data bytes.  Byte swapping is necessary to make
+        // the bit order match the polynomial coefficient order.
+        vld1.64         {q0-q1}, [buf]!
+        vld1.64         {q2-q3}, [buf]!
+        vld1.64         {q4-q5}, [buf]!
+        vld1.64         {q6-q7}, [buf]!
+CPU_LE( vrev64.8        q0, q0  )
+CPU_LE( vrev64.8        q1, q1  )
+CPU_LE( vrev64.8        q2, q2  )
+CPU_LE( vrev64.8        q3, q3  )
+CPU_LE( vrev64.8        q4, q4  )
+CPU_LE( vrev64.8        q5, q5  )
+CPU_LE( vrev64.8        q6, q6  )
+CPU_LE( vrev64.8        q7, q7  )
+        vswp            q0l, q0h
+        vswp            q1l, q1h
+        vswp            q2l, q2h
+        vswp            q3l, q3h
+        vswp            q4l, q4h
+        vswp            q5l, q5h
+        vswp            q6l, q6h
+        vswp            q7l, q7h
+
+        // XOR the first 16 data *bits* with the initial CRC value.
+        vmov.i8         q8h, #0
+        vmov.u16        q8h[3], init_crc
+        veor            q0h, q0h, q8h
+
+        // Load the constants for folding across 128 bytes.
+        vld1.64         {FOLD_CONSTS}, [fold_consts_ptr, :128]!
+
+        // Subtract 128 for the 128 data bytes just consumed.  Subtract another
+        // 128 to simplify the termination condition of the following loop.
+        sub             len, len, #256
+
+        // While >= 128 data bytes remain (not counting q0-q7), fold the 128
+        // bytes q0-q7 into them, storing the result back into q0-q7.
+.Lfold_128_bytes_loop:
+        fold_32_bytes   q0, q1
+        fold_32_bytes   q2, q3
+        fold_32_bytes   q4, q5
+        fold_32_bytes   q6, q7
+        subs            len, len, #128
+        bge             .Lfold_128_bytes_loop
+
+        // Now fold the 112 bytes in q0-q6 into the 16 bytes in q7.
+
+        // Fold across 64 bytes.
+        vld1.64         {FOLD_CONSTS}, [fold_consts_ptr, :128]!
+        fold_16_bytes   q0, q4
+        fold_16_bytes   q1, q5
+        fold_16_bytes   q2, q6
+        fold_16_bytes   q3, q7, 1
+        // Fold across 32 bytes.
+        fold_16_bytes   q4, q6
+        fold_16_bytes   q5, q7, 1
+        // Fold across 16 bytes.
+        fold_16_bytes   q6, q7
+
+        // Add 128 to get the correct number of data bytes remaining in 0...127
+        // (not counting q7), following the previous extra subtraction by 128.
+        // Then subtract 16 to simplify the termination condition of the
+        // following loop.
+        adds            len, len, #(128-16)
+
+        // While >= 16 data bytes remain (not counting q7), fold the 16 bytes q7
+        // into them, storing the result back into q7.
+        blt             .Lfold_16_bytes_loop_done
+.Lfold_16_bytes_loop:
+        vmull.p64       q8, q7l, FOLD_CONST_L
+        vmull.p64       q7, q7h, FOLD_CONST_H
         veor.8          q7, q7, q8
+        vld1.64         {q0}, [buf]!
+CPU_LE( vrev64.8        q0, q0  )
+        vswp            q0l, q0h
         veor.8          q7, q7, q0
-
-_128_done:
-        // compute crc of a 128-bit value
-        vldr            d20, rk5
-        vldr            d21, rk6                // rk5 and rk6 in xmm10
-
-        // 64b fold
-        vext.8          q0, qzr, q7, #8
-        vmull.p64       q7, d15, d20
+        subs            len, len, #16
+        bge             .Lfold_16_bytes_loop
+
+.Lfold_16_bytes_loop_done:
+        // Add 16 to get the correct number of data bytes remaining in 0...15
+        // (not counting q7), following the previous extra subtraction by 16.
+        adds            len, len, #16
+        beq             .Lreduce_final_16_bytes
+
+.Lhandle_partial_segment:
+        // Reduce the last '16 + len' bytes where 1 <= len <= 15 and the first
+        // 16 bytes are in q7 and the rest are the remaining data in 'buf'.  To
+        // do this without needing a fold constant for each possible 'len',
+        // redivide the bytes into a first chunk of 'len' bytes and a second
+        // chunk of 16 bytes, then fold the first chunk into the second.
+
+        // q0 = last 16 original data bytes
+        add             buf, buf, len
+        sub             buf, buf, #16
+        vld1.64         {q0}, [buf]
+CPU_LE( vrev64.8        q0, q0  )
+        vswp            q0l, q0h
+
+        // q1 = high order part of second chunk: q7 left-shifted by 'len' bytes.
+        __adrl          r3, .Lbyteshift_table + 16
+        sub             r3, r3, len
+        vld1.8          {q2}, [r3]
+        vtbl.8          q1l, {q7l-q7h}, q2l
+        vtbl.8          q1h, {q7l-q7h}, q2h
+
+        // q3 = first chunk: q7 right-shifted by '16-len' bytes.
+        vmov.i8         q3, #0x80
+        veor.8          q2, q2, q3
+        vtbl.8          q3l, {q7l-q7h}, q2l
+        vtbl.8          q3h, {q7l-q7h}, q2h
+
+        // Convert to 8-bit masks: 'len' 0x00 bytes, then '16-len' 0xff bytes.
+        vshr.s8         q2, q2, #7
+
+        // q2 = second chunk: 'len' bytes from q0 (low-order bytes),
+        // then '16-len' bytes from q1 (high-order bytes).
+        vbsl.8          q2, q1, q0
+
+        // Fold the first chunk into the second chunk, storing the result in q7.
+        vmull.p64       q0, q3l, FOLD_CONST_L
+        vmull.p64       q7, q3h, FOLD_CONST_H
         veor.8          q7, q7, q0
+        veor.8          q7, q7, q2
+
+.Lreduce_final_16_bytes:
+        // Reduce the 128-bit value M(x), stored in q7, to the final 16-bit CRC.
+
+        // Load 'x^48 * (x^48 mod G(x))' and 'x^48 * (x^80 mod G(x))'.
+        vld1.64         {FOLD_CONSTS}, [fold_consts_ptr, :128]!
+
+        // Fold the high 64 bits into the low 64 bits, while also multiplying by
+        // x^64.  This produces a 128-bit value congruent to x^64 * M(x) and
+        // whose low 48 bits are 0.
+        vmull.p64       q0, q7h, FOLD_CONST_H   // high bits * x^48 * (x^80 mod G(x))
+        veor.8          q0h, q0h, q7l           // + low bits * x^64
+
+        // Fold the high 32 bits into the low 96 bits.  This produces a 96-bit
+        // value congruent to x^64 * M(x) and whose low 48 bits are 0.
+        vmov.i8         q1, #0
+        vmov            s4, s3                  // extract high 32 bits
+        vmov            s3, s5                  // zero high 32 bits
+        vmull.p64       q1, q1l, FOLD_CONST_L   // high 32 bits * x^48 * (x^48 mod G(x))
+        veor.8          q0, q0, q1              // + low bits
+
+        // Load G(x) and floor(x^48 / G(x)).
+        vld1.64         {FOLD_CONSTS}, [fold_consts_ptr, :128]
+
+        // Use Barrett reduction to compute the final CRC value.
+        vmull.p64       q1, q0h, FOLD_CONST_H   // high 32 bits * floor(x^48 / G(x))
+        vshr.u64        q1l, q1l, #32           // /= x^32
+        vmull.p64       q1, q1l, FOLD_CONST_L   // *= G(x)
+        vshr.u64        q0l, q0l, #48
+        veor.8          q0l, q0l, q1l           // + low 16 nonzero bits
+        // Final CRC value (x^16 * M(x)) mod G(x) is in low 16 bits of q0.
+
+        vmov.u16        r0, q0l[0]
+        bx              lr
 
-        // 32b fold
-        vext.8          q0, q7, qzr, #12
-        vmov            s31, s3
-        vmull.p64       q0, d0, d21
-        veor.8          q7, q0, q7
-
-        // barrett reduction
-_barrett:
-        vldr            d20, rk7
-        vldr            d21, rk8
-
-        vmull.p64       q0, d15, d20
-        vext.8          q0, qzr, q0, #12
-        vmull.p64       q0, d1, d21
-        vext.8          q0, qzr, q0, #12
-        veor.8          q7, q7, q0
-        vmov            r0, s29
+.Lless_than_256_bytes:
+        // Checksumming a buffer of length 16...255 bytes
 
-_cleanup:
-        // scale the result back to 16 bits
-        lsr             r0, r0, #16
-        bx              lr
+        __adrl          fold_consts_ptr, .Lfold_across_16_bytes_consts
 
-_less_than_128:
-        teq             arg3, #0
-        beq             _cleanup
+        // Load the first 16 data bytes.
+        vld1.64         {q7}, [buf]!
+CPU_LE( vrev64.8        q7, q7  )
+        vswp            q7l, q7h
 
-        vmov.i8         q0, #0
-        vmov            s3, arg1_low32          // get the initial crc value
+        // XOR the first 16 data *bits* with the initial CRC value.
+        vmov.i8         q0h, #0
+        vmov.u16        q0h[3], init_crc
+        veor.8          q7h, q7h, q0h
 
-        vld1.64         {q7}, [arg2, :128]!
-CPU_LE( vrev64.8        q7, q7          )
-        vswp            d14, d15
-        veor.8          q7, q7, q0
+        // Load the fold-across-16-bytes constants.
+        vld1.64         {FOLD_CONSTS}, [fold_consts_ptr, :128]!
 
-        cmp             arg3, #16
-        beq             _128_done               // exactly 16 left
-        blt             _less_than_16_left
-
-        // now if there is, load the constants
-        vldr            d20, rk1
-        vldr            d21, rk2                // rk1 and rk2 in xmm10
-
-        // check if there is enough buffer to be able to fold 16B at a time
-        subs            arg3, arg3, #32
-        addlt           arg3, arg3, #16
-        blt             _get_last_two_regs
-        b               _16B_reduction_loop
-
-_less_than_16_left:
-        // shl r9, 4
-        adr             ip, tbl_shf_table + 16
-        sub             ip, ip, arg3
-        vld1.8          {q0}, [ip]
-        vmov.i8         q9, #0x80
-        veor.8          q0, q0, q9
-        vtbl.8          d18, {d14-d15}, d0
-        vtbl.8          d15, {d14-d15}, d1
-        vmov            d14, d18
-        b               _128_done
+        cmp             len, #16
+        beq             .Lreduce_final_16_bytes         // len == 16
+        subs            len, len, #32
+        addlt           len, len, #16
+        blt             .Lhandle_partial_segment        // 17 <= len <= 31
+        b               .Lfold_16_bytes_loop            // 32 <= len <= 255
 ENDPROC(crc_t10dif_pmull)
 
-// precomputed constants
-// these constants are precomputed from the poly:
-// 0x8bb70000 (0x8bb7 scaled to 32 bits)
+        .section        ".rodata", "a"
         .align          4
-// Q = 0x18BB70000
-// rk1 = 2^(32*3) mod Q << 32
-// rk2 = 2^(32*5) mod Q << 32
-// rk3 = 2^(32*15) mod Q << 32
-// rk4 = 2^(32*17) mod Q << 32
-// rk5 = 2^(32*3) mod Q << 32
-// rk6 = 2^(32*2) mod Q << 32
-// rk7 = floor(2^64/Q)
-// rk8 = Q
-
-rk3:    .quad           0x9d9d000000000000
-rk4:    .quad           0x7cf5000000000000
-rk5:    .quad           0x2d56000000000000
-rk6:    .quad           0x1368000000000000
-rk7:    .quad           0x00000001f65a57f8
-rk8:    .quad           0x000000018bb70000
-rk9:    .quad           0xceae000000000000
-rk10:   .quad           0xbfd6000000000000
-rk11:   .quad           0x1e16000000000000
-rk12:   .quad           0x713c000000000000
-rk13:   .quad           0xf7f9000000000000
-rk14:   .quad           0x80a6000000000000
-rk15:   .quad           0x044c000000000000
-rk16:   .quad           0xe658000000000000
-rk17:   .quad           0xad18000000000000
-rk18:   .quad           0xa497000000000000
-rk19:   .quad           0x6ee3000000000000
-rk20:   .quad           0xe7b5000000000000
-rk1:    .quad           0x2d56000000000000
-rk2:    .quad           0x06df000000000000
-
-tbl_shf_table:
-// use these values for shift constants for the tbl/tbx instruction
-// different alignments result in values as shown:
-//      DDQ 0x008f8e8d8c8b8a898887868584838281 # shl 15 (16-1) / shr1
-//      DDQ 0x01008f8e8d8c8b8a8988878685848382 # shl 14 (16-3) / shr2
-//      DDQ 0x0201008f8e8d8c8b8a89888786858483 # shl 13 (16-4) / shr3
-//      DDQ 0x030201008f8e8d8c8b8a898887868584 # shl 12 (16-4) / shr4
-//      DDQ 0x04030201008f8e8d8c8b8a8988878685 # shl 11 (16-5) / shr5
-//      DDQ 0x0504030201008f8e8d8c8b8a89888786 # shl 10 (16-6) / shr6
-//      DDQ 0x060504030201008f8e8d8c8b8a898887 # shl 9  (16-7) / shr7
-//      DDQ 0x07060504030201008f8e8d8c8b8a8988 # shl 8  (16-8) / shr8
-//      DDQ 0x0807060504030201008f8e8d8c8b8a89 # shl 7  (16-9) / shr9
-//      DDQ 0x090807060504030201008f8e8d8c8b8a # shl 6  (16-10) / shr10
-//      DDQ 0x0a090807060504030201008f8e8d8c8b # shl 5  (16-11) / shr11
-//      DDQ 0x0b0a090807060504030201008f8e8d8c # shl 4  (16-12) / shr12
-//      DDQ 0x0c0b0a090807060504030201008f8e8d # shl 3  (16-13) / shr13
-//      DDQ 0x0d0c0b0a090807060504030201008f8e # shl 2  (16-14) / shr14
-//      DDQ 0x0e0d0c0b0a090807060504030201008f # shl 1  (16-15) / shr15
 
+// Fold constants precomputed from the polynomial 0x18bb7
+// G(x) = x^16 + x^15 + x^11 + x^9 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + x^0
+.Lfold_across_128_bytes_consts:
+        .quad           0x0000000000006123      // x^(8*128)    mod G(x)
+        .quad           0x0000000000002295      // x^(8*128+64) mod G(x)
+// .Lfold_across_64_bytes_consts:
+        .quad           0x0000000000001069      // x^(4*128)    mod G(x)
+        .quad           0x000000000000dd31      // x^(4*128+64) mod G(x)
+// .Lfold_across_32_bytes_consts:
+        .quad           0x000000000000857d      // x^(2*128)    mod G(x)
+        .quad           0x0000000000007acc      // x^(2*128+64) mod G(x)
+.Lfold_across_16_bytes_consts:
+        .quad           0x000000000000a010      // x^(1*128)    mod G(x)
+        .quad           0x0000000000001faa      // x^(1*128+64) mod G(x)
+// .Lfinal_fold_consts:
+        .quad           0x1368000000000000      // x^48 * (x^48 mod G(x))
+        .quad           0x2d56000000000000      // x^48 * (x^80 mod G(x))
+// .Lbarrett_reduction_consts:
+        .quad           0x0000000000018bb7      // G(x)
+        .quad           0x00000001f65a57f8      // floor(x^48 / G(x))
+
+// For 1 <= len <= 15, the 16-byte vector beginning at &byteshift_table[16 -
+// len] is the index vector to shift left by 'len' bytes, and is also {0x80,
+// ..., 0x80} XOR the index vector to shift right by '16 - len' bytes.
+.Lbyteshift_table:
         .byte            0x0, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87
         .byte           0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f
         .byte            0x0,  0x1,  0x2,  0x3,  0x4,  0x5,  0x6,  0x7
diff --git a/arch/arm/crypto/crct10dif-ce-glue.c b/arch/arm/crypto/crct10dif-ce-glue.c
index d428355cf38d..3d6b800b8396 100644
--- a/arch/arm/crypto/crct10dif-ce-glue.c
+++ b/arch/arm/crypto/crct10dif-ce-glue.c
@@ -21,7 +21,7 @@
 
 #define CRC_T10DIF_PMULL_CHUNK_SIZE     16U
 
-asmlinkage u16 crc_t10dif_pmull(u16 init_crc, const u8 buf[], u32 len);
+asmlinkage u16 crc_t10dif_pmull(u16 init_crc, const u8 *buf, size_t len);
 
 static int crct10dif_init(struct shash_desc *desc)
 {
@@ -35,26 +35,15 @@ static int crct10dif_update(struct shash_desc *desc, const u8 *data,
                             unsigned int length)
 {
         u16 *crc = shash_desc_ctx(desc);
-        unsigned int l;
 
-        if (!may_use_simd()) {
-                *crc = crc_t10dif_generic(*crc, data, length);
+        if (length >= CRC_T10DIF_PMULL_CHUNK_SIZE && may_use_simd()) {
+                kernel_neon_begin();
+                *crc = crc_t10dif_pmull(*crc, data, length);
+                kernel_neon_end();
         } else {
-                if (unlikely((u32)data % CRC_T10DIF_PMULL_CHUNK_SIZE)) {
-                        l = min_t(u32, length, CRC_T10DIF_PMULL_CHUNK_SIZE -
-                                  ((u32)data % CRC_T10DIF_PMULL_CHUNK_SIZE));
-
-                        *crc = crc_t10dif_generic(*crc, data, l);
-
-                        length -= l;
-                        data += l;
-                }
-                if (length > 0) {
-                        kernel_neon_begin();
-                        *crc = crc_t10dif_pmull(*crc, data, length);
-                        kernel_neon_end();
-                }
+                *crc = crc_t10dif_generic(*crc, data, length);
         }
+
         return 0;
 }
 
diff --git a/arch/arm/crypto/sha256-armv4.pl b/arch/arm/crypto/sha256-armv4.pl
index b9ec44060ed3..a03cf4dfb781 100644
--- a/arch/arm/crypto/sha256-armv4.pl
+++ b/arch/arm/crypto/sha256-armv4.pl
@@ -212,10 +212,11 @@ K256:
 .global sha256_block_data_order
 .type   sha256_block_data_order,%function
 sha256_block_data_order:
+.Lsha256_block_data_order:
 #if __ARM_ARCH__<7
         sub     r3,pc,#8                @ sha256_block_data_order
 #else
-        adr     r3,sha256_block_data_order
+        adr     r3,.Lsha256_block_data_order
 #endif
 #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
         ldr     r12,.LOPENSSL_armcap
diff --git a/arch/arm/crypto/sha256-core.S_shipped b/arch/arm/crypto/sha256-core.S_shipped
index 3b58300d611c..054aae0edfce 100644
--- a/arch/arm/crypto/sha256-core.S_shipped
+++ b/arch/arm/crypto/sha256-core.S_shipped
@@ -93,10 +93,11 @@ K256:
 .global sha256_block_data_order
 .type   sha256_block_data_order,%function
 sha256_block_data_order:
+.Lsha256_block_data_order:
 #if __ARM_ARCH__<7
         sub     r3,pc,#8                @ sha256_block_data_order
 #else
-        adr     r3,sha256_block_data_order
+        adr     r3,.Lsha256_block_data_order
 #endif
 #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
         ldr     r12,.LOPENSSL_armcap
diff --git a/arch/arm/crypto/sha512-armv4.pl b/arch/arm/crypto/sha512-armv4.pl
index fb5d15048c0b..788c17b56ecc 100644
--- a/arch/arm/crypto/sha512-armv4.pl
+++ b/arch/arm/crypto/sha512-armv4.pl
@@ -274,10 +274,11 @@ WORD64(0x5fcb6fab,0x3ad6faec, 0x6c44198c,0x4a475817)
 .global sha512_block_data_order
 .type   sha512_block_data_order,%function
 sha512_block_data_order:
+.Lsha512_block_data_order:
 #if __ARM_ARCH__<7
         sub     r3,pc,#8                @ sha512_block_data_order
 #else
-        adr     r3,sha512_block_data_order
+        adr     r3,.Lsha512_block_data_order
 #endif
 #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
         ldr     r12,.LOPENSSL_armcap
diff --git a/arch/arm/crypto/sha512-core.S_shipped b/arch/arm/crypto/sha512-core.S_shipped
index b1c334a49cda..710ea309769e 100644
--- a/arch/arm/crypto/sha512-core.S_shipped
+++ b/arch/arm/crypto/sha512-core.S_shipped
@@ -141,10 +141,11 @@ WORD64(0x5fcb6fab,0x3ad6faec, 0x6c44198c,0x4a475817)
 .global sha512_block_data_order
 .type   sha512_block_data_order,%function
 sha512_block_data_order:
+.Lsha512_block_data_order:
 #if __ARM_ARCH__<7
         sub     r3,pc,#8                @ sha512_block_data_order
 #else
-        adr     r3,sha512_block_data_order
+        adr     r3,.Lsha512_block_data_order
 #endif
 #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
         ldr     r12,.LOPENSSL_armcap
diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h
index 0bd530702118..d15b8c99f1b3 100644
--- a/arch/arm/include/asm/arch_gicv3.h
+++ b/arch/arm/include/asm/arch_gicv3.h
@@ -34,6 +34,7 @@
 #define ICC_SRE                         __ACCESS_CP15(c12, 0, c12, 5)
 #define ICC_IGRPEN1                     __ACCESS_CP15(c12, 0, c12, 7)
 #define ICC_BPR1                        __ACCESS_CP15(c12, 0, c12, 3)
+#define ICC_RPR                         __ACCESS_CP15(c12, 0, c11, 3)
 
 #define __ICC_AP0Rx(x)                  __ACCESS_CP15(c12, 0, c8, 4 | x)
 #define ICC_AP0R0                       __ICC_AP0Rx(0)
@@ -54,7 +55,7 @@
 #define ICH_VTR                         __ACCESS_CP15(c12, 4, c11, 1)
 #define ICH_MISR                        __ACCESS_CP15(c12, 4, c11, 2)
 #define ICH_EISR                        __ACCESS_CP15(c12, 4, c11, 3)
-#define ICH_ELSR                        __ACCESS_CP15(c12, 4, c11, 5)
+#define ICH_ELRSR                       __ACCESS_CP15(c12, 4, c11, 5)
 #define ICH_VMCR                        __ACCESS_CP15(c12, 4, c11, 7)
 
 #define __LR0(x)                        __ACCESS_CP15(c12, 4, c12, x)
@@ -151,7 +152,7 @@ CPUIF_MAP(ICH_HCR, ICH_HCR_EL2)
 CPUIF_MAP(ICH_VTR, ICH_VTR_EL2)
 CPUIF_MAP(ICH_MISR, ICH_MISR_EL2)
 CPUIF_MAP(ICH_EISR, ICH_EISR_EL2)
-CPUIF_MAP(ICH_ELSR, ICH_ELSR_EL2)
+CPUIF_MAP(ICH_ELRSR, ICH_ELRSR_EL2)
 CPUIF_MAP(ICH_VMCR, ICH_VMCR_EL2)
 CPUIF_MAP(ICH_AP0R3, ICH_AP0R3_EL2)
 CPUIF_MAP(ICH_AP0R2, ICH_AP0R2_EL2)
@@ -245,6 +246,21 @@ static inline void gic_write_bpr1(u32 val)
         write_sysreg(val, ICC_BPR1);
 }
 
+static inline u32 gic_read_pmr(void)
+{
+        return read_sysreg(ICC_PMR);
+}
+
+static inline void gic_write_pmr(u32 val)
+{
+        write_sysreg(val, ICC_PMR);
+}
+
+static inline u32 gic_read_rpr(void)
+{
+        return read_sysreg(ICC_RPR);
+}
+
 /*
  * Even in 32bit systems that use LPAE, there is no guarantee that the I/O
  * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't
@@ -347,5 +363,22 @@ static inline void gits_write_vpendbaser(u64 val, void * __iomem addr)
 
 #define gits_read_vpendbaser(c)         __gic_readq_nonatomic(c)
 
+static inline bool gic_prio_masking_enabled(void)
+{
+        return false;
+}
+
+static inline void gic_pmr_mask_irqs(void)
+{
+        /* Should not get called. */
+        WARN_ON_ONCE(true);
+}
+
+static inline void gic_arch_enable_irqs(void)
+{
+        /* Should not get called. */
+        WARN_ON_ONCE(true);
+}
+
 #endif /* !__ASSEMBLY__ */
 #endif /* !__ASM_ARCH_GICV3_H */
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 28a48e0d4cca..b59921a560da 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -376,9 +376,9 @@ THUMB(	orr	\reg , \reg , #PSR_T_BIT	)
         .macro  usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
 9999:
         .if     \inc == 1
-        \instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
+        \instr\()b\t\cond\().w \reg, [\ptr, #\off]
         .elseif \inc == 4
-        \instr\cond\()\t\().w \reg, [\ptr, #\off]
+        \instr\t\cond\().w \reg, [\ptr, #\off]
         .else
         .error  "Unsupported inc macro argument"
         .endif
@@ -417,9 +417,9 @@ THUMB(	orr	\reg , \reg , #PSR_T_BIT	)
         .rept   \rept
 9999:
         .if     \inc == 1
-        \instr\cond\()b\()\t \reg, [\ptr], #\inc
+        \instr\()b\t\cond \reg, [\ptr], #\inc
         .elseif \inc == 4
-        \instr\cond\()\t \reg, [\ptr], #\inc
+        \instr\t\cond \reg, [\ptr], #\inc
         .else
         .error  "Unsupported inc macro argument"
         .endif
@@ -460,7 +460,7 @@ THUMB(	orr	\reg , \reg , #PSR_T_BIT	)
         .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
 #ifndef CONFIG_CPU_USE_DOMAINS
         adds    \tmp, \addr, #\size - 1
-        sbcccs  \tmp, \tmp, \limit
+        sbcscc  \tmp, \tmp, \limit
         bcs     \bad
 #ifdef CONFIG_CPU_SPECTRE
         movcs   \addr, #0
@@ -474,7 +474,7 @@ THUMB(	orr	\reg , \reg , #PSR_T_BIT	)
         sub     \tmp, \limit, #1
         subs    \tmp, \tmp, \addr       @ tmp = limit - 1 - addr
         addhs   \tmp, \tmp, #1          @ if (tmp >= 0) {
-        subhss  \tmp, \tmp, \size       @ tmp = limit - (addr + size) }
+        subshs  \tmp, \tmp, \size       @ tmp = limit - (addr + size) }
         movlo   \addr, #0               @ if (tmp < 0) addr = NULL
         csdb
 #endif
diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h
index 69772e742a0a..83ae97c049d9 100644
--- a/arch/arm/include/asm/barrier.h
+++ b/arch/arm/include/asm/barrier.h
@@ -11,6 +11,8 @@
 #define sev()   __asm__ __volatile__ ("sev" : : : "memory")
 #define wfe()   __asm__ __volatile__ ("wfe" : : : "memory")
 #define wfi()   __asm__ __volatile__ ("wfi" : : : "memory")
+#else
+#define wfe()   do { } while (0)
 #endif
 
 #if __LINUX_ARM_ARCH__ >= 7
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 31d3b96f0f4b..03ba90ffc0f8 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -96,15 +96,6 @@ static inline unsigned long dma_max_pfn(struct device *dev)
 }
 #define dma_max_pfn(dev) dma_max_pfn(dev)
 
-#define arch_setup_dma_ops arch_setup_dma_ops
-extern void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
-                               const struct iommu_ops *iommu, bool coherent);
-
-#ifdef CONFIG_MMU
-#define arch_teardown_dma_ops arch_teardown_dma_ops
-extern void arch_teardown_dma_ops(struct device *dev);
-#endif
-
 /* do not use this function in a driver */
 static inline bool is_device_dma_coherent(struct device *dev)
 {
diff --git a/arch/arm/include/asm/hardware/entry-macro-iomd.S b/arch/arm/include/asm/hardware/entry-macro-iomd.S
index 8c215acd9b57..f7692731e514 100644
--- a/arch/arm/include/asm/hardware/entry-macro-iomd.S
+++ b/arch/arm/include/asm/hardware/entry-macro-iomd.S
@@ -16,25 +16,25 @@
                 ldr     \tmp, =irq_prio_h
                 teq     \irqstat, #0
 #ifdef IOMD_BASE
-                ldreqb  \irqstat, [\base, #IOMD_DMAREQ] @ get dma
+                ldrbeq  \irqstat, [\base, #IOMD_DMAREQ] @ get dma
                 addeq   \tmp, \tmp, #256                @ irq_prio_h table size
                 teqeq   \irqstat, #0
                 bne     2406f
 #endif
-                ldreqb  \irqstat, [\base, #IOMD_IRQREQA]        @ get low priority
+                ldrbeq  \irqstat, [\base, #IOMD_IRQREQA]        @ get low priority
                 addeq   \tmp, \tmp, #256                @ irq_prio_d table size
                 teqeq   \irqstat, #0
 #ifdef IOMD_IRQREQC
-                ldreqb  \irqstat, [\base, #IOMD_IRQREQC]
+                ldrbeq  \irqstat, [\base, #IOMD_IRQREQC]
                 addeq   \tmp, \tmp, #256                @ irq_prio_l table size
                 teqeq   \irqstat, #0
 #endif
 #ifdef IOMD_IRQREQD
-                ldreqb  \irqstat, [\base, #IOMD_IRQREQD]
+                ldrbeq  \irqstat, [\base, #IOMD_IRQREQD]
                 addeq   \tmp, \tmp, #256                @ irq_prio_lc table size
                 teqeq   \irqstat, #0
 #endif
-2406:           ldrneb  \irqnr, [\tmp, \irqstat]        @ get IRQ number
+2406:           ldrbne  \irqnr, [\tmp, \irqstat]        @ get IRQ number
                 .endm
 
 /*
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index c883fcbe93b6..46d41140df27 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -25,7 +25,6 @@
 #ifndef __ASSEMBLY__
 struct irqaction;
 struct pt_regs;
-extern void migrate_irqs(void);
 
 extern void asm_do_IRQ(unsigned int, struct pt_regs *);
 void handle_IRQ(unsigned int, struct pt_regs *);
diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h
index 77121b713bef..8927cae7c966 100644
--- a/arch/arm/include/asm/kvm_emulate.h
+++ b/arch/arm/include/asm/kvm_emulate.h
@@ -265,6 +265,14 @@ static inline bool kvm_vcpu_dabt_isextabt(struct kvm_vcpu *vcpu)
         }
 }
 
+static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
+{
+        if (kvm_vcpu_trap_is_iabt(vcpu))
+                return false;
+
+        return kvm_vcpu_dabt_iswrite(vcpu);
+}
+
 static inline u32 kvm_vcpu_hvc_get_imm(struct kvm_vcpu *vcpu)
 {
         return kvm_vcpu_get_hsr(vcpu) & HSR_HVC_IMM_MASK;
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index ca56537b61bc..770d73257ad9 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -26,6 +26,7 @@
 #include <asm/kvm_asm.h>
 #include <asm/kvm_mmio.h>
 #include <asm/fpstate.h>
+#include <asm/smp_plat.h>
 #include <kvm/arm_arch_timer.h>
 
 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
@@ -48,6 +49,7 @@
 #define KVM_REQ_SLEEP \
         KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
 #define KVM_REQ_IRQ_PENDING     KVM_ARCH_REQ(1)
+#define KVM_REQ_VCPU_RESET      KVM_ARCH_REQ(2)
 
 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
 
@@ -56,10 +58,13 @@ int __attribute_const__ kvm_target_cpu(void);
 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
 void kvm_reset_coprocs(struct kvm_vcpu *vcpu);
 
-struct kvm_arch {
-        /* VTTBR value associated with below pgd and vmid */
-        u64    vttbr;
+struct kvm_vmid {
+        /* The VMID generation used for the virt. memory system */
+        u64    vmid_gen;
+        u32    vmid;
+};
 
+struct kvm_arch {
         /* The last vcpu id that ran on each physical CPU */
         int __percpu *last_vcpu_ran;
 
@@ -69,11 +74,11 @@ struct kvm_arch {
          */
 
         /* The VMID generation used for the virt. memory system */
-        u64    vmid_gen;
-        u32    vmid;
+        struct kvm_vmid vmid;
 
         /* Stage-2 page table */
         pgd_t *pgd;
+        phys_addr_t pgd_phys;
 
         /* Interrupt controller */
         struct vgic_dist        vgic;
@@ -147,6 +152,20 @@ struct kvm_cpu_context {
 
 typedef struct kvm_cpu_context kvm_cpu_context_t;
 
+static inline void kvm_init_host_cpu_context(kvm_cpu_context_t *cpu_ctxt,
+                                             int cpu)
+{
+        /* The host's MPIDR is immutable, so let's set it up at boot time */
+        cpu_ctxt->cp15[c0_MPIDR] = cpu_logical_map(cpu);
+}
+
+struct vcpu_reset_state {
+        unsigned long   pc;
+        unsigned long   r0;
+        bool            be;
+        bool            reset;
+};
+
 struct kvm_vcpu_arch {
         struct kvm_cpu_context ctxt;
 
@@ -186,6 +205,8 @@ struct kvm_vcpu_arch {
         /* Cache some mmu pages needed inside spinlock regions */
         struct kvm_mmu_memory_cache mmu_page_cache;
 
+        struct vcpu_reset_state reset_state;
+
         /* Detect first run of a vcpu */
         bool has_run_once;
 };
@@ -214,7 +235,35 @@ unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
-unsigned long kvm_call_hyp(void *hypfn, ...);
+
+unsigned long __kvm_call_hyp(void *hypfn, ...);
+
+/*
+ * The has_vhe() part doesn't get emitted, but is used for type-checking.
+ */
+#define kvm_call_hyp(f, ...)                                            \
+        do {                                                            \
+                if (has_vhe()) {                                        \
+                        f(__VA_ARGS__);                                 \
+                } else {                                                \
+                        __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__); \
+                }                                                       \
+        } while(0)
+
+#define kvm_call_hyp_ret(f, ...)                                        \
+        ({                                                              \
+                typeof(f(__VA_ARGS__)) ret;                             \
+                                                                        \
+                if (has_vhe()) {                                        \
+                        ret = f(__VA_ARGS__);                           \
+                } else {                                                \
+                        ret = __kvm_call_hyp(kvm_ksym_ref(f),           \
+                                             ##__VA_ARGS__);            \
+                }                                                       \
+                                                                        \
+                ret;                                                    \
+        })
+
 void force_vm_exit(const cpumask_t *mask);
 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
                               struct kvm_vcpu_events *events);
@@ -265,7 +314,7 @@ static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
          * compliant with the PCS!).
          */
 
-        kvm_call_hyp((void*)hyp_stack_ptr, vector_ptr, pgd_ptr);
+        __kvm_call_hyp((void*)hyp_stack_ptr, vector_ptr, pgd_ptr);
 }
 
 static inline void __cpu_init_stage2(void)
diff --git a/arch/arm/include/asm/kvm_hyp.h b/arch/arm/include/asm/kvm_hyp.h
index e93a0cac9add..87bcd18df8d5 100644
--- a/arch/arm/include/asm/kvm_hyp.h
+++ b/arch/arm/include/asm/kvm_hyp.h
@@ -40,6 +40,7 @@
 #define TTBR1           __ACCESS_CP15_64(1, c2)
 #define VTTBR           __ACCESS_CP15_64(6, c2)
 #define PAR             __ACCESS_CP15_64(0, c7)
+#define CNTP_CVAL       __ACCESS_CP15_64(2, c14)
 #define CNTV_CVAL       __ACCESS_CP15_64(3, c14)
 #define CNTVOFF         __ACCESS_CP15_64(4, c14)
 
@@ -85,6 +86,7 @@
 #define TID_PRIV        __ACCESS_CP15(c13, 0, c0, 4)
 #define HTPIDR          __ACCESS_CP15(c13, 4, c0, 2)
 #define CNTKCTL         __ACCESS_CP15(c14, 0, c1, 0)
+#define CNTP_CTL        __ACCESS_CP15(c14, 0, c2, 1)
 #define CNTV_CTL        __ACCESS_CP15(c14, 0, c3, 1)
 #define CNTHCTL         __ACCESS_CP15(c14, 4, c1, 0)
 
@@ -94,6 +96,8 @@
 #define read_sysreg_el0(r)              read_sysreg(r##_el0)
 #define write_sysreg_el0(v, r)          write_sysreg(v, r##_el0)
 
+#define cntp_ctl_el0                    CNTP_CTL
+#define cntp_cval_el0                   CNTP_CVAL
 #define cntv_ctl_el0                    CNTV_CTL
 #define cntv_cval_el0                   CNTV_CVAL
 #define cntvoff_el2                     CNTVOFF
diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
index 3a875fc1b63c..2de96a180166 100644
--- a/arch/arm/include/asm/kvm_mmu.h
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -421,9 +421,14 @@ static inline int hyp_map_aux_data(void)
 
 static inline void kvm_set_ipa_limit(void) {}
 
-static inline bool kvm_cpu_has_cnp(void)
+static __always_inline u64 kvm_get_vttbr(struct kvm *kvm)
 {
-        return false;
+        struct kvm_vmid *vmid = &kvm->arch.vmid;
+        u64 vmid_field, baddr;
+
+        baddr = kvm->arch.pgd_phys;
+        vmid_field = (u64)vmid->vmid << VTTBR_VMID_SHIFT;
+        return kvm_phys_to_vttbr(baddr) | vmid_field;
 }
 
 #endif  /* !__ASSEMBLY__ */
diff --git a/arch/arm/include/asm/kvm_ras.h b/arch/arm/include/asm/kvm_ras.h
new file mode 100644
index 000000000000..e9577292dfe4
--- /dev/null
+++ b/arch/arm/include/asm/kvm_ras.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (C) 2018 - Arm Ltd */
+
+#ifndef __ARM_KVM_RAS_H__
+#define __ARM_KVM_RAS_H__
+
+#include <linux/types.h>
+
+static inline int kvm_handle_guest_sea(phys_addr_t addr, unsigned int esr)
+{
+        return -1;
+}
+
+#endif /* __ARM_KVM_RAS_H__ */
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index a757401129f9..48ce1b19069b 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -125,6 +125,9 @@ extern pgprot_t		pgprot_s2_device;
 #define pgprot_stronglyordered(prot) \
         __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
 
+#define pgprot_device(prot) \
+        __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_SHARED | L_PTE_SHARED | L_PTE_DIRTY | L_PTE_XN)
+
 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 #define pgprot_dmacoherent(prot) \
         __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 120f4c9bbfde..57fe73ea0f72 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -89,7 +89,11 @@ extern void release_thread(struct task_struct *);
 unsigned long get_wchan(struct task_struct *p);
 
 #if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327)
-#define cpu_relax()                     smp_mb()
+#define cpu_relax()                                             \
+        do {                                                    \
+                smp_mb();                                       \
+                __asm__ __volatile__("nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;");      \
+        } while (0)
 #else
 #define cpu_relax()                     barrier()
 #endif
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 709a55989cb0..451ae684aaf4 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -67,7 +67,6 @@ struct secondary_data {
         void *stack;
 };
 extern struct secondary_data secondary_data;
-extern volatile int pen_release;
 extern void secondary_startup(void);
 extern void secondary_startup_arm(void);
 
diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h
index 312784ee9936..c729d2113a24 100644
--- a/arch/arm/include/asm/smp_twd.h
+++ b/arch/arm/include/asm/smp_twd.h
@@ -19,20 +19,4 @@
 #define TWD_TIMER_CONTROL_PERIODIC      (1 << 1)
 #define TWD_TIMER_CONTROL_IT_ENABLE     (1 << 2)
 
-#include <linux/ioport.h>
-
-struct twd_local_timer {
-        struct resource res[2];
-};
-
-#define DEFINE_TWD_LOCAL_TIMER(name,base,irq)   \
-struct twd_local_timer name __initdata = {      \
-        .res    = {                             \
-                DEFINE_RES_MEM(base, 0x10),     \
-                DEFINE_RES_IRQ(irq),            \
-        },                                      \
-};
-
-int twd_local_timer_register(struct twd_local_timer *);
-
 #endif
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index 099c78fcf62d..8f009e788ad4 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -210,11 +210,12 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
 
         prefetchw(&rw->lock);
         __asm__ __volatile__(
+"       .syntax unified\n"
 "1:     ldrex   %0, [%2]\n"
 "       adds    %0, %0, #1\n"
 "       strexpl %1, %0, [%2]\n"
         WFE("mi")
-"       rsbpls  %0, %1, #0\n"
+"       rsbspl  %0, %1, #0\n"
 "       bmi     1b"
         : "=&r" (tmp), "=&r" (tmp2)
         : "r" (&rw->lock)
diff --git a/arch/arm/include/asm/stage2_pgtable.h b/arch/arm/include/asm/stage2_pgtable.h
index c4b1d4fb1797..de2089501b8b 100644
--- a/arch/arm/include/asm/stage2_pgtable.h
+++ b/arch/arm/include/asm/stage2_pgtable.h
@@ -76,4 +76,9 @@ static inline bool kvm_stage2_has_pud(struct kvm *kvm)
 #define S2_PMD_MASK                             PMD_MASK
 #define S2_PMD_SIZE                             PMD_SIZE
 
+static inline bool kvm_stage2_has_pmd(struct kvm *kvm)
+{
+        return true;
+}
+
 #endif  /* __ARM_S2_PGTABLE_H_ */
diff --git a/arch/arm/include/asm/suspend.h b/arch/arm/include/asm/suspend.h
index 452bbdcbcc83..506314265c6f 100644
--- a/arch/arm/include/asm/suspend.h
+++ b/arch/arm/include/asm/suspend.h
@@ -10,6 +10,7 @@ struct sleep_save_sp {
 };
 
 extern void cpu_resume(void);
+extern void cpu_resume_no_hyp(void);
 extern void cpu_resume_arm(void);
 extern int cpu_suspend(unsigned long, int (*)(unsigned long));
 
diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h
index 8e76db83c498..66f6a3ae68d2 100644
--- a/arch/arm/include/asm/system_misc.h
+++ b/arch/arm/include/asm/system_misc.h
@@ -38,11 +38,6 @@ static inline void harden_branch_predictor(void)
 
 extern unsigned int user_debug;
 
-static inline int handle_guest_sea(phys_addr_t addr, unsigned int esr)
-{
-        return -1;
-}
-
 #endif /* !__ASSEMBLY__ */
 
 #endif /* __ASM_ARM_SYSTEM_MISC_H */
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 42aa4a22803c..dff49845eb87 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -59,7 +59,6 @@ extern int __put_user_bad(void);
  * Note that this is actually 0x1,0000,0000
  */
 #define KERNEL_DS       0x00000000
-#define get_ds()        (KERNEL_DS)
 
 #ifdef CONFIG_MMU
 
@@ -86,7 +85,8 @@ static inline void set_fs(mm_segment_t fs)
 #define __range_ok(addr, size) ({ \
         unsigned long flag, roksum; \
         __chk_user_ptr(addr);   \
-        __asm__("adds %1, %2, %3; sbcccs %1, %1, %0; movcc %0, #0" \
+        __asm__(".syntax unified\n" \
+                "adds %1, %2, %3; sbcscc %1, %1, %0; movcc %0, #0" \
                 : "=&r" (flag), "=&r" (roksum) \
                 : "r" (addr), "Ir" (size), "0" (current_thread_info()->addr_limit) \
                 : "cc"); \
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 88ef2ce1f69a..7a39e77984ef 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -26,10 +26,10 @@
 #define __ARCH_WANT_SYS_SIGPROCMASK
 #define __ARCH_WANT_SYS_OLD_MMAP
 #define __ARCH_WANT_SYS_OLD_SELECT
-#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_UTIME32
 
 #if !defined(CONFIG_AEABI) || defined(CONFIG_OABI_COMPAT)
-#define __ARCH_WANT_SYS_TIME
+#define __ARCH_WANT_SYS_TIME32
 #define __ARCH_WANT_SYS_IPC
 #define __ARCH_WANT_SYS_OLDUMOUNT
 #define __ARCH_WANT_SYS_ALARM
@@ -45,7 +45,6 @@
  * Unimplemented (or alternatively implemented) syscalls
  */
 #define __IGNORE_fadvise64_64
-#define __IGNORE_migrate_pages
 
 #ifdef __ARM_EABI__
 /*
diff --git a/arch/arm/include/asm/v7m.h b/arch/arm/include/asm/v7m.h
index 187ccf6496ad..2cb00d15831b 100644
--- a/arch/arm/include/asm/v7m.h
+++ b/arch/arm/include/asm/v7m.h
@@ -49,7 +49,7 @@
  * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
  */
 #define EXC_RET_STACK_MASK                      0x00000004
-#define EXC_RET_THREADMODE_PROCESSSTACK         0xfffffffd
+#define EXC_RET_THREADMODE_PROCESSSTACK         (3 << 2)
 
 /* Cache related definitions */
 
diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h
index ef5dfedacd8d..628c336e8e3b 100644
--- a/arch/arm/include/asm/vfpmacros.h
+++ b/arch/arm/include/asm/vfpmacros.h
@@ -29,13 +29,13 @@
         ldr     \tmp, =elf_hwcap                    @ may not have MVFR regs
         ldr     \tmp, [\tmp, #0]
         tst     \tmp, #HWCAP_VFPD32
-        ldcnel  p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
+        ldclne  p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
         addeq   \base, \base, #32*4                 @ step over unused register space
 #else
         VFPFMRX \tmp, MVFR0                         @ Media and VFP Feature Register 0
         and     \tmp, \tmp, #MVFR0_A_SIMD_MASK      @ A_SIMD field
         cmp     \tmp, #2                            @ 32 x 64bit registers?
-        ldceql  p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
+        ldcleq  p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
         addne   \base, \base, #32*4                 @ step over unused register space
 #endif
 #endif
@@ -53,13 +53,13 @@
         ldr     \tmp, =elf_hwcap                    @ may not have MVFR regs
         ldr     \tmp, [\tmp, #0]
         tst     \tmp, #HWCAP_VFPD32
-        stcnel  p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
+        stclne  p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
         addeq   \base, \base, #32*4                 @ step over unused register space
 #else
         VFPFMRX \tmp, MVFR0                         @ Media and VFP Feature Register 0
         and     \tmp, \tmp, #MVFR0_A_SIMD_MASK      @ A_SIMD field
         cmp     \tmp, #2                            @ 32 x 64bit registers?
-        stceql  p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
+        stcleq  p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
         addne   \base, \base, #32*4                 @ step over unused register space
 #endif
 #endif
diff --git a/arch/arm/include/asm/xen/page-coherent.h b/arch/arm/include/asm/xen/page-coherent.h
index b3ef061d8b74..2c403e7c782d 100644
--- a/arch/arm/include/asm/xen/page-coherent.h
+++ b/arch/arm/include/asm/xen/page-coherent.h
@@ -1 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_ARM_XEN_PAGE_COHERENT_H
+#define _ASM_ARM_XEN_PAGE_COHERENT_H
+
+#include <linux/dma-mapping.h>
+#include <asm/page.h>
 #include <xen/arm/page-coherent.h>
+
+static inline const struct dma_map_ops *xen_get_dma_ops(struct device *dev)
+{
+        if (dev && dev->archdata.dev_dma_ops)
+                return dev->archdata.dev_dma_ops;
+        return get_arch_dma_ops(NULL);
+}
+
+static inline void *xen_alloc_coherent_pages(struct device *hwdev, size_t size,
+                dma_addr_t *dma_handle, gfp_t flags, unsigned long attrs)
+{
+        return xen_get_dma_ops(hwdev)->alloc(hwdev, size, dma_handle, flags, attrs);
+}
+
+static inline void xen_free_coherent_pages(struct device *hwdev, size_t size,
+                void *cpu_addr, dma_addr_t dma_handle, unsigned long attrs)
+{
+        xen_get_dma_ops(hwdev)->free(hwdev, size, cpu_addr, dma_handle, attrs);
+}
+
+static inline void xen_dma_map_page(struct device *hwdev, struct page *page,
+             dma_addr_t dev_addr, unsigned long offset, size_t size,
+             enum dma_data_direction dir, unsigned long attrs)
+{
+        unsigned long page_pfn = page_to_xen_pfn(page);
+        unsigned long dev_pfn = XEN_PFN_DOWN(dev_addr);
+        unsigned long compound_pages =
+                (1<<compound_order(page)) * XEN_PFN_PER_PAGE;
+        bool local = (page_pfn <= dev_pfn) &&
+                (dev_pfn - page_pfn < compound_pages);
+
+        /*
+         * Dom0 is mapped 1:1, while the Linux page can span across
+         * multiple Xen pages, it's not possible for it to contain a
+         * mix of local and foreign Xen pages. So if the first xen_pfn
+         * == mfn the page is local otherwise it's a foreign page
+         * grant-mapped in dom0. If the page is local we can safely
+         * call the native dma_ops function, otherwise we call the xen
+         * specific function.
+         */
+        if (local)
+                xen_get_dma_ops(hwdev)->map_page(hwdev, page, offset, size, dir, attrs);
+        else
+                __xen_dma_map_page(hwdev, page, dev_addr, offset, size, dir, attrs);
+}
+
+static inline void xen_dma_unmap_page(struct device *hwdev, dma_addr_t handle,
+                size_t size, enum dma_data_direction dir, unsigned long attrs)
+{
+        unsigned long pfn = PFN_DOWN(handle);
+        /*
+         * Dom0 is mapped 1:1, while the Linux page can be spanned accross
+         * multiple Xen page, it's not possible to have a mix of local and
+         * foreign Xen page. Dom0 is mapped 1:1, so calling pfn_valid on a
+         * foreign mfn will always return false. If the page is local we can
+         * safely call the native dma_ops function, otherwise we call the xen
+         * specific function.
+         */
+        if (pfn_valid(pfn)) {
+                if (xen_get_dma_ops(hwdev)->unmap_page)
+                        xen_get_dma_ops(hwdev)->unmap_page(hwdev, handle, size, dir, attrs);
+        } else
+                __xen_dma_unmap_page(hwdev, handle, size, dir, attrs);
+}
+
+static inline void xen_dma_sync_single_for_cpu(struct device *hwdev,
+                dma_addr_t handle, size_t size, enum dma_data_direction dir)
+{
+        unsigned long pfn = PFN_DOWN(handle);
+        if (pfn_valid(pfn)) {
+                if (xen_get_dma_ops(hwdev)->sync_single_for_cpu)
+                        xen_get_dma_ops(hwdev)->sync_single_for_cpu(hwdev, handle, size, dir);
+        } else
+                __xen_dma_sync_single_for_cpu(hwdev, handle, size, dir);
+}
+
+static inline void xen_dma_sync_single_for_device(struct device *hwdev,
+                dma_addr_t handle, size_t size, enum dma_data_direction dir)
+{
+        unsigned long pfn = PFN_DOWN(handle);
+        if (pfn_valid(pfn)) {
+                if (xen_get_dma_ops(hwdev)->sync_single_for_device)
+                        xen_get_dma_ops(hwdev)->sync_single_for_device(hwdev, handle, size, dir);
+        } else
+                __xen_dma_sync_single_for_device(hwdev, handle, size, dir);
+}
+
+#endif /* _ASM_ARM_XEN_PAGE_COHERENT_H */
diff --git a/arch/arm/include/debug/tegra.S b/arch/arm/include/debug/tegra.S
index 3bc80599c022..4a5a645c76e2 100644
--- a/arch/arm/include/debug/tegra.S
+++ b/arch/arm/include/debug/tegra.S
@@ -173,7 +173,7 @@
 
                 .macro  senduart, rd, rx
                 cmp     \rx, #0
-                strneb  \rd, [\rx, #UART_TX << UART_SHIFT]
+                strbne  \rd, [\rx, #UART_TX << UART_SHIFT]
 1001:
                 .endm
 
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index b795dc2408c0..b9f94e03d916 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -86,7 +86,7 @@ hexbuf_rel:	.long	hexbuf_addr - .
 ENTRY(printascii)
                 addruart_current r3, r1, r2
 1:              teq     r0, #0
-                ldrneb  r1, [r0], #1
+                ldrbne  r1, [r0], #1
                 teqne   r1, #0
                 reteq   lr
 2:              teq     r1, #'\n'
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index e85a3af9ddeb..ce4aea57130a 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -636,7 +636,7 @@ call_fpe:
         @ Test if we need to give access to iWMMXt coprocessors
         ldr     r5, [r10, #TI_FLAGS]
         rsbs    r7, r8, #(1 << 8)               @ CP 0 or 1 only
-        movcss  r7, r5, lsr #(TIF_USING_IWMMXT + 1)
+        movscs  r7, r5, lsr #(TIF_USING_IWMMXT + 1)
         bcs     iwmmxt_task_enable
 #endif
  ARM(   add     pc, pc, r8, lsr #6      )
@@ -872,7 +872,7 @@ __kuser_cmpxchg64:				@ 0xffff0f60
         smp_dmb arm
 1:      ldrexd  r0, r1, [r2]                    @ load current val
         eors    r3, r0, r4                      @ compare with oldval (1)
-        eoreqs  r3, r1, r5                      @ compare with oldval (2)
+        eorseq  r3, r1, r5                      @ compare with oldval (2)
         strexdeq r3, r6, r7, [r2]               @ store newval if eq
         teqeq   r3, #1                          @ success?
         beq     1b                              @ if no then retry
@@ -896,8 +896,8 @@ __kuser_cmpxchg64:				@ 0xffff0f60
         ldmia   r1, {r6, lr}                    @ load new val
 1:      ldmia   r2, {r0, r1}                    @ load current val
         eors    r3, r0, r4                      @ compare with oldval (1)
-        eoreqs  r3, r1, r5                      @ compare with oldval (2)
-2:      stmeqia r2, {r6, lr}                    @ store newval if eq
+        eorseq  r3, r1, r5                      @ compare with oldval (2)
+2:      stmiaeq r2, {r6, lr}                    @ store newval if eq
         rsbs    r0, r3, #0                      @ set return val and C flag
         ldmfd   sp!, {r4, r5, r6, pc}
 
@@ -911,7 +911,7 @@ kuser_cmpxchg64_fixup:
         mov     r7, #0xffff0fff
         sub     r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
         subs    r8, r4, r7
-        rsbcss  r8, r8, #(2b - 1b)
+        rsbscs  r8, r8, #(2b - 1b)
         strcs   r7, [sp, #S_PC]
 #if __LINUX_ARM_ARCH__ < 6
         bcc     kuser_cmpxchg32_fixup
@@ -969,7 +969,7 @@ kuser_cmpxchg32_fixup:
         mov     r7, #0xffff0fff
         sub     r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
         subs    r8, r4, r7
-        rsbcss  r8, r8, #(2b - 1b)
+        rsbscs  r8, r8, #(2b - 1b)
         strcs   r7, [sp, #S_PC]
         ret     lr
         .previous
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 0465d65d23de..f7649adef505 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -373,7 +373,7 @@ sys_syscall:
                 movhs   scno, #0
                 csdb
 #endif
-                stmloia sp, {r5, r6}            @ shuffle args
+                stmialo sp, {r5, r6}            @ shuffle args
                 movlo   r0, r1
                 movlo   r1, r2
                 movlo   r2, r3
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 773424843d6e..32051ec5b33f 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -127,7 +127,8 @@
          */
         .macro  v7m_exception_slow_exit ret_r0
         cpsid   i
-        ldr     lr, =EXC_RET_THREADMODE_PROCESSSTACK
+        ldr     lr, =exc_ret
+        ldr     lr, [lr]
 
         @ read original r12, sp, lr, pc and xPSR
         add     r12, sp, #S_IP
@@ -387,8 +388,8 @@
         badr    lr, \ret                        @ return address
         .if     \reload
         add     r1, sp, #S_R0 + S_OFF           @ pointer to regs
-        ldmccia r1, {r0 - r6}                   @ reload r0-r6
-        stmccia sp, {r4, r5}                    @ update stack arguments
+        ldmiacc r1, {r0 - r6}                   @ reload r0-r6
+        stmiacc sp, {r4, r5}                    @ update stack arguments
         .endif
         ldrcc   pc, [\table, \tmp, lsl #2]      @ call sys_* routine
 #else
@@ -396,8 +397,8 @@
         badr    lr, \ret                        @ return address
         .if     \reload
         add     r1, sp, #S_R0 + S_OFF           @ pointer to regs
-        ldmccia r1, {r0 - r6}                   @ reload r0-r6
-        stmccia sp, {r4, r5}                    @ update stack arguments
+        ldmiacc r1, {r0 - r6}                   @ reload r0-r6
+        stmiacc sp, {r4, r5}                    @ update stack arguments
         .endif
         ldrcc   pc, [\table, \nr, lsl #2]       @ call sys_* routine
 #endif
diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S
index abcf47848525..19d2dcd6530d 100644
--- a/arch/arm/kernel/entry-v7m.S
+++ b/arch/arm/kernel/entry-v7m.S
@@ -146,3 +146,7 @@ ENTRY(vector_table)
         .rept   CONFIG_CPU_V7M_NUM_IRQ
         .long   __irq_entry             @ External Interrupts
         .endr
+        .align  2
+        .globl  exc_ret
+exc_ret:
+        .space  4
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index ec29de250076..c08d2d890f7b 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -439,8 +439,8 @@ M_CLASS(str	r6, [r12, #PMSAv8_RLAR_A(3)])
         str     r5, [r12, #PMSAv8_RBAR_A(0)]
         str     r6, [r12, #PMSAv8_RLAR_A(0)]
 #else
-        mcr     p15, 0, r5, c6, c10, 1                  @ PRBAR4
-        mcr     p15, 0, r6, c6, c10, 2                  @ PRLAR4
+        mcr     p15, 0, r5, c6, c10, 0                  @ PRBAR4
+        mcr     p15, 0, r6, c6, c10, 1                  @ PRLAR4
 #endif
 #endif
         ret     lr
diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
index 60146e32619a..82a942894fc0 100644
--- a/arch/arm/kernel/hyp-stub.S
+++ b/arch/arm/kernel/hyp-stub.S
@@ -180,8 +180,8 @@ ARM_BE8(orr	r7, r7, #(1 << 25))     @ HSCTLR.EE
         @ Check whether GICv3 system registers are available
         mrc     p15, 0, r7, c0, c1, 1   @ ID_PFR1
         ubfx    r7, r7, #28, #4
-        cmp     r7, #1
-        bne     2f
+        teq     r7, #0
+        beq     2f
 
         @ Enable system register accesses
         mrc     p15, 4, r7, c12, c9, 5  @ ICC_HSRE
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 9908dacf9229..844861368cd5 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -31,7 +31,6 @@
 #include <linux/smp.h>
 #include <linux/init.h>
 #include <linux/seq_file.h>
-#include <linux/ratelimit.h>
 #include <linux/errno.h>
 #include <linux/list.h>
 #include <linux/kallsyms.h>
@@ -109,64 +108,3 @@ int __init arch_probe_nr_irqs(void)
         return nr_irqs;
 }
 #endif
-
-#ifdef CONFIG_HOTPLUG_CPU
-static bool migrate_one_irq(struct irq_desc *desc)
-{
-        struct irq_data *d = irq_desc_get_irq_data(desc);
-        const struct cpumask *affinity = irq_data_get_affinity_mask(d);
-        struct irq_chip *c;
-        bool ret = false;
-
-        /*
-         * If this is a per-CPU interrupt, or the affinity does not
-         * include this CPU, then we have nothing to do.
-         */
-        if (irqd_is_per_cpu(d) || !cpumask_test_cpu(smp_processor_id(), affinity))
-                return false;
-
-        if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
-                affinity = cpu_online_mask;
-                ret = true;
-        }
-
-        c = irq_data_get_irq_chip(d);
-        if (!c->irq_set_affinity)
-                pr_debug("IRQ%u: unable to set affinity\n", d->irq);
-        else if (c->irq_set_affinity(d, affinity, false) == IRQ_SET_MASK_OK && ret)
-                cpumask_copy(irq_data_get_affinity_mask(d), affinity);
-
-        return ret;
-}
-
-/*
- * The current CPU has been marked offline.  Migrate IRQs off this CPU.
- * If the affinity settings do not allow other CPUs, force them onto any
- * available CPU.
- *
- * Note: we must iterate over all IRQs, whether they have an attached
- * action structure or not, as we need to get chained interrupts too.
- */
-void migrate_irqs(void)
-{
-        unsigned int i;
-        struct irq_desc *desc;
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        for_each_irq_desc(i, desc) {
-                bool affinity_broken;
-
-                raw_spin_lock(&desc->lock);
-                affinity_broken = migrate_one_irq(desc);
-                raw_spin_unlock(&desc->lock);
-
-                if (affinity_broken)
-                        pr_warn_ratelimited("IRQ%u no longer affine to CPU%u\n",
-                                i, smp_processor_id());
-        }
-
-        local_irq_restore(flags);
-}
-#endif /* CONFIG_HOTPLUG_CPU */
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index dd2eb5f76b9f..76300f3813e8 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -91,8 +91,11 @@ void machine_crash_nonpanic_core(void *unused)
 
         set_cpu_online(smp_processor_id(), false);
         atomic_dec(&waiting_for_crash_ipi);
-        while (1)
+
+        while (1) {
                 cpu_relax();
+                wfe();
+        }
 }
 
 void crash_smp_send_stop(void)
diff --git a/arch/arm/kernel/patch.c b/arch/arm/kernel/patch.c
index a50dc00d79a2..d0a05a3bdb96 100644
--- a/arch/arm/kernel/patch.c
+++ b/arch/arm/kernel/patch.c
@@ -16,7 +16,7 @@ struct patch {
         unsigned int insn;
 };
 
-static DEFINE_SPINLOCK(patch_lock);
+static DEFINE_RAW_SPINLOCK(patch_lock);
 
 static void __kprobes *patch_map(void *addr, int fixmap, unsigned long *flags)
         __acquires(&patch_lock)
@@ -33,7 +33,7 @@ static void __kprobes *patch_map(void *addr, int fixmap, unsigned long *flags)
                 return addr;
 
         if (flags)
-                spin_lock_irqsave(&patch_lock, *flags);
+                raw_spin_lock_irqsave(&patch_lock, *flags);
         else
                 __acquire(&patch_lock);
 
@@ -48,7 +48,7 @@ static void __kprobes patch_unmap(int fixmap, unsigned long *flags)
         clear_fixmap(fixmap);
 
         if (flags)
-                spin_unlock_irqrestore(&patch_lock, *flags);
+                raw_spin_unlock_irqrestore(&patch_lock, *flags);
         else
                 __release(&patch_lock);
 }
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 16601d1442d1..72cc0862a30e 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -150,7 +150,7 @@ void __show_regs(struct pt_regs *regs)
                 if ((domain & domain_mask(DOMAIN_USER)) ==
                     domain_val(DOMAIN_USER, DOMAIN_NOACCESS))
                         segment = "none";
-                else if (fs == get_ds())
+                else if (fs == KERNEL_DS)
                         segment = "kernel";
                 else
                         segment = "user";
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 375b13f7e780..5d78b6ac0429 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -867,6 +867,9 @@ static void __init request_standard_resources(const struct machine_desc *mdesc)
                 boot_alias_start = phys_to_idmap(start);
                 if (arm_has_idmap_alias() && boot_alias_start != IDMAP_INVALID_ADDR) {
                         res = memblock_alloc(sizeof(*res), SMP_CACHE_BYTES);
+                        if (!res)
+                                panic("%s: Failed to allocate %zu bytes\n",
+                                      __func__, sizeof(*res));
                         res->name = "System RAM (boot alias)";
                         res->start = boot_alias_start;
                         res->end = phys_to_idmap(end);
@@ -875,6 +878,9 @@ static void __init request_standard_resources(const struct machine_desc *mdesc)
                 }
 
                 res = memblock_alloc(sizeof(*res), SMP_CACHE_BYTES);
+                if (!res)
+                        panic("%s: Failed to allocate %zu bytes\n", __func__,
+                              sizeof(*res));
                 res->name  = "System RAM";
                 res->start = start;
                 res->end = end;
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index a8257fc9cf2a..5dc8b80bb693 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -120,6 +120,14 @@ ENDPROC(cpu_resume_after_mmu)
         .text
         .align
 
+#ifdef CONFIG_MCPM
+        .arm
+THUMB(  .thumb                  )
+ENTRY(cpu_resume_no_hyp)
+ARM_BE8(setend be)                      @ ensure we are in BE mode
+        b       no_hyp
+#endif
+
 #ifdef CONFIG_MMU
         .arm
 ENTRY(cpu_resume_arm)
@@ -135,6 +143,7 @@ ARM_BE8(setend be)			@ ensure we are in BE mode
         bl      __hyp_stub_install_secondary
 #endif
         safe_svcmode_maskall r1
+no_hyp:
         mov     r1, #0
         ALT_SMP(mrc p15, 0, r0, c0, c0, 5)
         ALT_UP_B(1f)
@@ -164,6 +173,9 @@ ENDPROC(cpu_resume)
 #ifdef CONFIG_MMU
 ENDPROC(cpu_resume_arm)
 #endif
+#ifdef CONFIG_MCPM
+ENDPROC(cpu_resume_no_hyp)
+#endif
 
         .align 2
 _sleep_save_sp:
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 3bf82232b1be..facd4240ca02 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -62,12 +62,6 @@
  */
 struct secondary_data secondary_data;
 
-/*
- * control for which core is the next to come out of the secondary
- * boot "holding pen"
- */
-volatile int pen_release = -1;
-
 enum ipi_msg_type {
         IPI_WAKEUP,
         IPI_TIMER,
@@ -254,7 +248,7 @@ int __cpu_disable(void)
         /*
          * OK - migrate IRQs away from this CPU
          */
-        migrate_irqs();
+        irq_migrate_all_off_this_cpu();
 
         /*
          * Flush user cache and TLB mappings, and then remove this CPU
@@ -604,8 +598,10 @@ static void ipi_cpu_stop(unsigned int cpu)
         local_fiq_disable();
         local_irq_disable();
 
-        while (1)
+        while (1) {
                 cpu_relax();
+                wfe();
+        }
 }
 
 static DEFINE_PER_CPU(struct completion *, cpu_completion);
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index b30eafeef096..3cdc399b9fc3 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -100,8 +100,6 @@ static void twd_timer_stop(void)
         disable_percpu_irq(clk->irq);
 }
 
-#ifdef CONFIG_COMMON_CLK
-
 /*
  * Updates clockevent frequency when the cpu frequency changes.
  * Called on the cpu that is changing frequency with interrupts disabled.
@@ -143,54 +141,6 @@ static int twd_clk_init(void)
 }
 core_initcall(twd_clk_init);
 
-#elif defined (CONFIG_CPU_FREQ)
-
-#include <linux/cpufreq.h>
-
-/*
- * Updates clockevent frequency when the cpu frequency changes.
- * Called on the cpu that is changing frequency with interrupts disabled.
- */
-static void twd_update_frequency(void *data)
-{
-        twd_timer_rate = clk_get_rate(twd_clk);
-
-        clockevents_update_freq(raw_cpu_ptr(twd_evt), twd_timer_rate);
-}
-
-static int twd_cpufreq_transition(struct notifier_block *nb,
-        unsigned long state, void *data)
-{
-        struct cpufreq_freqs *freqs = data;
-
-        /*
-         * The twd clock events must be reprogrammed to account for the new
-         * frequency.  The timer is local to a cpu, so cross-call to the
-         * changing cpu.
-         */
-        if (state == CPUFREQ_POSTCHANGE)
-                smp_call_function_single(freqs->cpu, twd_update_frequency,
-                        NULL, 1);
-
-        return NOTIFY_OK;
-}
-
-static struct notifier_block twd_cpufreq_nb = {
-        .notifier_call = twd_cpufreq_transition,
-};
-
-static int twd_cpufreq_init(void)
-{
-        if (twd_evt && raw_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
-                return cpufreq_register_notifier(&twd_cpufreq_nb,
-                        CPUFREQ_TRANSITION_NOTIFIER);
-
-        return 0;
-}
-core_initcall(twd_cpufreq_init);
-
-#endif
-
 static void twd_calibrate_rate(void)
 {
         unsigned long count;
@@ -366,21 +316,6 @@ out_free:
         return err;
 }
 
-int __init twd_local_timer_register(struct twd_local_timer *tlt)
-{
-        if (twd_base || twd_evt)
-                return -EBUSY;
-
-        twd_ppi = tlt->res[1].start;
-
-        twd_base = ioremap(tlt->res[0].start, resource_size(&tlt->res[0]));
-        if (!twd_base)
-                return -ENOMEM;
-
-        return twd_local_timer_common_register(NULL);
-}
-
-#ifdef CONFIG_OF
 static int __init twd_local_timer_of_register(struct device_node *np)
 {
         int err;
@@ -406,4 +341,3 @@ out:
 TIMER_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register);
 TIMER_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register);
 TIMER_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register);
-#endif
diff --git a/arch/arm/kernel/sys_oabi-compat.c b/arch/arm/kernel/sys_oabi-compat.c
index 92ab36f38795..acd054a42ba2 100644
--- a/arch/arm/kernel/sys_oabi-compat.c
+++ b/arch/arm/kernel/sys_oabi-compat.c
@@ -317,10 +317,10 @@ struct oabi_sembuf {
 asmlinkage long sys_oabi_semtimedop(int semid,
                                     struct oabi_sembuf __user *tsops,
                                     unsigned nsops,
-                                    const struct timespec __user *timeout)
+                                    const struct old_timespec32 __user *timeout)
 {
         struct sembuf *sops;
-        struct timespec local_timeout;
+        struct old_timespec32 local_timeout;
         long err;
         int i;
 
@@ -350,7 +350,7 @@ asmlinkage long sys_oabi_semtimedop(int semid,
         } else {
                 mm_segment_t fs = get_fs();
                 set_fs(KERNEL_DS);
-                err = sys_semtimedop(semid, sops, nsops, timeout);
+                err = sys_semtimedop_time32(semid, sops, nsops, timeout);
                 set_fs(fs);
         }
         kfree(sops);
@@ -375,7 +375,7 @@ asmlinkage int sys_oabi_ipc(uint call, int first, int second, int third,
                 return  sys_oabi_semtimedop(first,
                                             (struct oabi_sembuf __user *)ptr,
                                             second,
-                                            (const struct timespec __user *)fifth);
+                                            (const struct old_timespec32 __user *)fifth);
         default:
                 return sys_ipc(call, first, second, third, ptr, fifth);
         }
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
index 0bee233fef9a..314cfb232a63 100644
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -93,7 +93,7 @@ extern const struct unwind_idx __start_unwind_idx[];
 static const struct unwind_idx *__origin_unwind_idx;
 extern const struct unwind_idx __stop_unwind_idx[];
 
-static DEFINE_SPINLOCK(unwind_lock);
+static DEFINE_RAW_SPINLOCK(unwind_lock);
 static LIST_HEAD(unwind_tables);
 
 /* Convert a prel31 symbol to an absolute address */
@@ -201,7 +201,7 @@ static const struct unwind_idx *unwind_find_idx(unsigned long addr)
                 /* module unwind tables */
                 struct unwind_table *table;
 
-                spin_lock_irqsave(&unwind_lock, flags);
+                raw_spin_lock_irqsave(&unwind_lock, flags);
                 list_for_each_entry(table, &unwind_tables, list) {
                         if (addr >= table->begin_addr &&
                             addr < table->end_addr) {
@@ -213,7 +213,7 @@ static const struct unwind_idx *unwind_find_idx(unsigned long addr)
                                 break;
                         }
                 }
-                spin_unlock_irqrestore(&unwind_lock, flags);
+                raw_spin_unlock_irqrestore(&unwind_lock, flags);
         }
 
         pr_debug("%s: idx = %p\n", __func__, idx);
@@ -529,9 +529,9 @@ struct unwind_table *unwind_table_add(unsigned long start, unsigned long size,
         tab->begin_addr = text_addr;
         tab->end_addr = text_addr + text_size;
 
-        spin_lock_irqsave(&unwind_lock, flags);
+        raw_spin_lock_irqsave(&unwind_lock, flags);
         list_add_tail(&tab->list, &unwind_tables);
-        spin_unlock_irqrestore(&unwind_lock, flags);
+        raw_spin_unlock_irqrestore(&unwind_lock, flags);
 
         return tab;
 }
@@ -543,9 +543,9 @@ void unwind_table_del(struct unwind_table *tab)
         if (!tab)
                 return;
 
-        spin_lock_irqsave(&unwind_lock, flags);
+        raw_spin_lock_irqsave(&unwind_lock, flags);
         list_del(&tab->list);
-        spin_unlock_irqrestore(&unwind_lock, flags);
+        raw_spin_unlock_irqrestore(&unwind_lock, flags);
 
         kfree(tab);
 }
diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
index 48de846f2246..531e59f5be9c 100644
--- a/arch/arm/kvm/Makefile
+++ b/arch/arm/kvm/Makefile
@@ -8,9 +8,8 @@ ifeq ($(plus_virt),+virt)
         plus_virt_def := -DREQUIRES_VIRT=1
 endif
 
-ccflags-y += -Iarch/arm/kvm -Ivirt/kvm/arm/vgic
-CFLAGS_arm.o := -I. $(plus_virt_def)
-CFLAGS_mmu.o := -I.
+ccflags-y += -I $(srctree)/$(src) -I $(srctree)/virt/kvm/arm/vgic
+CFLAGS_arm.o := $(plus_virt_def)
 
 AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt)
 AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
index 222c1635bc7a..14915c78bd99 100644
--- a/arch/arm/kvm/coproc.c
+++ b/arch/arm/kvm/coproc.c
@@ -293,15 +293,16 @@ static bool access_cntp_tval(struct kvm_vcpu *vcpu,
                              const struct coproc_params *p,
                              const struct coproc_reg *r)
 {
-        u64 now = kvm_phys_timer_read();
-        u64 val;
+        u32 val;
 
         if (p->is_write) {
                 val = *vcpu_reg(vcpu, p->Rt1);
-                kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL, val + now);
+                kvm_arm_timer_write_sysreg(vcpu,
+                                           TIMER_PTIMER, TIMER_REG_TVAL, val);
         } else {
-                val = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL);
-                *vcpu_reg(vcpu, p->Rt1) = val - now;
+                val = kvm_arm_timer_read_sysreg(vcpu,
+                                                TIMER_PTIMER, TIMER_REG_TVAL);
+                *vcpu_reg(vcpu, p->Rt1) = val;
         }
 
         return true;
@@ -315,9 +316,11 @@ static bool access_cntp_ctl(struct kvm_vcpu *vcpu,
 
         if (p->is_write) {
                 val = *vcpu_reg(vcpu, p->Rt1);
-                kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CTL, val);
+                kvm_arm_timer_write_sysreg(vcpu,
+                                           TIMER_PTIMER, TIMER_REG_CTL, val);
         } else {
-                val = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CTL);
+                val = kvm_arm_timer_read_sysreg(vcpu,
+                                                TIMER_PTIMER, TIMER_REG_CTL);
                 *vcpu_reg(vcpu, p->Rt1) = val;
         }
 
@@ -333,9 +336,11 @@ static bool access_cntp_cval(struct kvm_vcpu *vcpu,
         if (p->is_write) {
                 val = (u64)*vcpu_reg(vcpu, p->Rt2) << 32;
                 val |= *vcpu_reg(vcpu, p->Rt1);
-                kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL, val);
+                kvm_arm_timer_write_sysreg(vcpu,
+                                           TIMER_PTIMER, TIMER_REG_CVAL, val);
         } else {
-                val = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL);
+                val = kvm_arm_timer_read_sysreg(vcpu,
+                                                TIMER_PTIMER, TIMER_REG_CVAL);
                 *vcpu_reg(vcpu, p->Rt1) = val;
                 *vcpu_reg(vcpu, p->Rt2) = val >> 32;
         }
@@ -1450,6 +1455,6 @@ void kvm_reset_coprocs(struct kvm_vcpu *vcpu)
         reset_coproc_regs(vcpu, table, num);
 
         for (num = 1; num < NR_CP15_REGS; num++)
-                if (vcpu_cp15(vcpu, num) == 0x42424242)
-                        panic("Didn't reset vcpu_cp15(vcpu, %zi)", num);
+                WARN(vcpu_cp15(vcpu, num) == 0x42424242,
+                     "Didn't reset vcpu_cp15(vcpu, %zi)", num);
 }
diff --git a/arch/arm/kvm/hyp/cp15-sr.c b/arch/arm/kvm/hyp/cp15-sr.c
index c4782812714c..8bf895ec6e04 100644
--- a/arch/arm/kvm/hyp/cp15-sr.c
+++ b/arch/arm/kvm/hyp/cp15-sr.c
@@ -27,7 +27,6 @@ static u64 *cp15_64(struct kvm_cpu_context *ctxt, int idx)
 
 void __hyp_text __sysreg_save_state(struct kvm_cpu_context *ctxt)
 {
-        ctxt->cp15[c0_MPIDR]            = read_sysreg(VMPIDR);
         ctxt->cp15[c0_CSSELR]           = read_sysreg(CSSELR);
         ctxt->cp15[c1_SCTLR]            = read_sysreg(SCTLR);
         ctxt->cp15[c1_CPACR]            = read_sysreg(CPACR);
diff --git a/arch/arm/kvm/hyp/hyp-entry.S b/arch/arm/kvm/hyp/hyp-entry.S
index aa3f9a9837ac..6ed3cf23fe89 100644
--- a/arch/arm/kvm/hyp/hyp-entry.S
+++ b/arch/arm/kvm/hyp/hyp-entry.S
@@ -176,7 +176,7 @@ THUMB(	orr	lr, lr, #PSR_T_BIT	)
         msr     spsr_cxsf, lr
         ldr     lr, =panic
         msr     ELR_hyp, lr
-        ldr     lr, =kvm_call_hyp
+        ldr     lr, =__kvm_call_hyp
         clrex
         eret
 ENDPROC(__hyp_do_panic)
diff --git a/arch/arm/kvm/hyp/switch.c b/arch/arm/kvm/hyp/switch.c
index acf1c37fa49c..3b058a5d7c5f 100644
--- a/arch/arm/kvm/hyp/switch.c
+++ b/arch/arm/kvm/hyp/switch.c
@@ -77,7 +77,7 @@ static void __hyp_text __deactivate_traps(struct kvm_vcpu *vcpu)
 static void __hyp_text __activate_vm(struct kvm_vcpu *vcpu)
 {
         struct kvm *kvm = kern_hyp_va(vcpu->kvm);
-        write_sysreg(kvm->arch.vttbr, VTTBR);
+        write_sysreg(kvm_get_vttbr(kvm), VTTBR);
         write_sysreg(vcpu->arch.midr, VPIDR);
 }
 
diff --git a/arch/arm/kvm/hyp/tlb.c b/arch/arm/kvm/hyp/tlb.c
index c0edd450e104..8e4afba73635 100644
--- a/arch/arm/kvm/hyp/tlb.c
+++ b/arch/arm/kvm/hyp/tlb.c
@@ -41,7 +41,7 @@ void __hyp_text __kvm_tlb_flush_vmid(struct kvm *kvm)
 
         /* Switch to requested VMID */
         kvm = kern_hyp_va(kvm);
-        write_sysreg(kvm->arch.vttbr, VTTBR);
+        write_sysreg(kvm_get_vttbr(kvm), VTTBR);
         isb();
 
         write_sysreg(0, TLBIALLIS);
@@ -61,7 +61,7 @@ void __hyp_text __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu)
         struct kvm *kvm = kern_hyp_va(kern_hyp_va(vcpu)->kvm);
 
         /* Switch to requested VMID */
-        write_sysreg(kvm->arch.vttbr, VTTBR);
+        write_sysreg(kvm_get_vttbr(kvm), VTTBR);
         isb();
 
         write_sysreg(0, TLBIALL);
diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
index 80a1d6cd261c..a08e6419ebe9 100644
--- a/arch/arm/kvm/interrupts.S
+++ b/arch/arm/kvm/interrupts.S
@@ -42,7 +42,7 @@
  *   r12:     caller save
  *   rest:    callee save
  */
-ENTRY(kvm_call_hyp)
+ENTRY(__kvm_call_hyp)
         hvc     #0
         bx      lr
-ENDPROC(kvm_call_hyp)
+ENDPROC(__kvm_call_hyp)
diff --git a/arch/arm/kvm/reset.c b/arch/arm/kvm/reset.c
index 5ed0c3ee33d6..e53327912adc 100644
--- a/arch/arm/kvm/reset.c
+++ b/arch/arm/kvm/reset.c
@@ -26,6 +26,7 @@
 #include <asm/cputype.h>
 #include <asm/kvm_arm.h>
 #include <asm/kvm_coproc.h>
+#include <asm/kvm_emulate.h>
 
 #include <kvm/arm_arch_timer.h>
 
@@ -69,6 +70,29 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
         /* Reset CP15 registers */
         kvm_reset_coprocs(vcpu);
 
+        /*
+         * Additional reset state handling that PSCI may have imposed on us.
+         * Must be done after all the sys_reg reset.
+         */
+        if (READ_ONCE(vcpu->arch.reset_state.reset)) {
+                unsigned long target_pc = vcpu->arch.reset_state.pc;
+
+                /* Gracefully handle Thumb2 entry point */
+                if (target_pc & 1) {
+                        target_pc &= ~1UL;
+                        vcpu_set_thumb(vcpu);
+                }
+
+                /* Propagate caller endianness */
+                if (vcpu->arch.reset_state.be)
+                        kvm_vcpu_set_be(vcpu);
+
+                *vcpu_pc(vcpu) = target_pc;
+                vcpu_set_reg(vcpu, 0, vcpu->arch.reset_state.r0);
+
+                vcpu->arch.reset_state.reset = false;
+        }
+
         /* Reset arch_timer context */
         return kvm_timer_vcpu_reset(vcpu);
 }
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index ad25fd1872c7..0bff0176db2c 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -39,7 +39,7 @@ $(obj)/csumpartialcopy.o:	$(obj)/csumpartialcopygeneric.S
 $(obj)/csumpartialcopyuser.o:   $(obj)/csumpartialcopygeneric.S
 
 ifeq ($(CONFIG_KERNEL_MODE_NEON),y)
-  NEON_FLAGS                    := -mfloat-abi=softfp -mfpu=neon
+  NEON_FLAGS                    := -march=armv7-a -mfloat-abi=softfp -mfpu=neon
   CFLAGS_xor-neon.o             += $(NEON_FLAGS)
   obj-$(CONFIG_XOR_BLOCKS)      += xor-neon.o
 endif
diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h
index 93cddab73072..95bd35991288 100644
--- a/arch/arm/lib/bitops.h
+++ b/arch/arm/lib/bitops.h
@@ -7,7 +7,7 @@
 ENTRY(  \name           )
 UNWIND( .fnstart        )
         ands    ip, r1, #3
-        strneb  r1, [ip]                @ assert word-aligned
+        strbne  r1, [ip]                @ assert word-aligned
         mov     r2, #1
         and     r3, r0, #31             @ Get bit offset
         mov     r0, r0, lsr #5
@@ -32,7 +32,7 @@ ENDPROC(\name		)
 ENTRY(  \name           )
 UNWIND( .fnstart        )
         ands    ip, r1, #3
-        strneb  r1, [ip]                @ assert word-aligned
+        strbne  r1, [ip]                @ assert word-aligned
         mov     r2, #1
         and     r3, r0, #31             @ Get bit offset
         mov     r0, r0, lsr #5
@@ -62,7 +62,7 @@ ENDPROC(\name		)
 ENTRY(  \name           )
 UNWIND( .fnstart        )
         ands    ip, r1, #3
-        strneb  r1, [ip]                @ assert word-aligned
+        strbne  r1, [ip]                @ assert word-aligned
         and     r2, r0, #31
         mov     r0, r0, lsr #5
         mov     r3, #1
@@ -89,7 +89,7 @@ ENDPROC(\name		)
 ENTRY(  \name           )
 UNWIND( .fnstart        )
         ands    ip, r1, #3
-        strneb  r1, [ip]                @ assert word-aligned
+        strbne  r1, [ip]                @ assert word-aligned
         and     r3, r0, #31
         mov     r0, r0, lsr #5
         save_and_disable_irqs ip
diff --git a/arch/arm/lib/clear_user.S b/arch/arm/lib/clear_user.S
index e936352ccb00..55946e3fa2ba 100644
--- a/arch/arm/lib/clear_user.S
+++ b/arch/arm/lib/clear_user.S
@@ -44,7 +44,7 @@ UNWIND(.save {r1, lr})
                 strusr  r2, r0, 1, ne, rept=2
                 tst     r1, #1                  @ x1 x0 x1 x0 x1 x0 x1
                 it      ne                      @ explicit IT needed for the label
-USER(           strnebt r2, [r0])
+USER(           strbtne r2, [r0])
                 mov     r0, #0
                 ldmfd   sp!, {r1, pc}
 UNWIND(.fnend)
diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S
index 0d4c189c7f4f..6a3419e2c6d8 100644
--- a/arch/arm/lib/copy_from_user.S
+++ b/arch/arm/lib/copy_from_user.S
@@ -91,7 +91,7 @@
         .endm
 
         .macro str1b ptr reg cond=al abort
-        str\cond\()b \reg, [\ptr], #1
+        strb\cond \reg, [\ptr], #1
         .endm
 
         .macro enter reg1 reg2
diff --git a/arch/arm/lib/copy_page.S b/arch/arm/lib/copy_page.S
index 6ee2f6706f86..b84ce1792043 100644
--- a/arch/arm/lib/copy_page.S
+++ b/arch/arm/lib/copy_page.S
@@ -39,9 +39,9 @@ ENTRY(copy_page)
         .endr
                 subs    r2, r2, #1                      @       1
                 stmia   r0!, {r3, r4, ip, lr}           @       4
-                ldmgtia r1!, {r3, r4, ip, lr}           @       4
+                ldmiagt r1!, {r3, r4, ip, lr}           @       4
                 bgt     1b                              @       1
-        PLD(    ldmeqia r1!, {r3, r4, ip, lr}   )
+        PLD(    ldmiaeq r1!, {r3, r4, ip, lr}   )
         PLD(    beq     2b                      )
                 ldmfd   sp!, {r4, pc}                   @       3
 ENDPROC(copy_page)
diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
index 652e4d98cd47..a11f2c25e03a 100644
--- a/arch/arm/lib/copy_template.S
+++ b/arch/arm/lib/copy_template.S
@@ -99,7 +99,7 @@
 
         CALGN(  ands    ip, r0, #31             )
         CALGN(  rsb     r3, ip, #32             )
-        CALGN(  sbcnes  r4, r3, r2              )  @ C is always set here
+        CALGN(  sbcsne  r4, r3, r2              )  @ C is always set here
         CALGN(  bcs     2f                      )
         CALGN(  adr     r4, 6f                  )
         CALGN(  subs    r2, r2, r3              )  @ C gets set
@@ -204,7 +204,7 @@
 
         CALGN(  ands    ip, r0, #31             )
         CALGN(  rsb     ip, ip, #32             )
-        CALGN(  sbcnes  r4, ip, r2              )  @ C is always set here
+        CALGN(  sbcsne  r4, ip, r2              )  @ C is always set here
         CALGN(  subcc   r2, r2, ip              )
         CALGN(  bcc     15f                     )
 
@@ -241,7 +241,7 @@
                 orr     r9, r9, ip, lspush #\push
                 mov     ip, ip, lspull #\pull
                 orr     ip, ip, lr, lspush #\push
-                str8w   r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f
+                str8w   r0, r3, r4, r5, r6, r7, r8, r9, ip, abort=19f
                 bge     12b
         PLD(    cmn     r2, #96                 )
         PLD(    bge     13b                     )
diff --git a/arch/arm/lib/copy_to_user.S b/arch/arm/lib/copy_to_user.S
index 97a6ff4b7e3c..c7d08096e354 100644
--- a/arch/arm/lib/copy_to_user.S
+++ b/arch/arm/lib/copy_to_user.S
@@ -49,7 +49,7 @@
         .endm
 
         .macro ldr1b ptr reg cond=al abort
-        ldr\cond\()b \reg, [\ptr], #1
+        ldrb\cond \reg, [\ptr], #1
         .endm
 
 #ifdef CONFIG_CPU_USE_DOMAINS
diff --git a/arch/arm/lib/csumpartial.S b/arch/arm/lib/csumpartial.S
index 984e0f29d548..bd84e2db353b 100644
--- a/arch/arm/lib/csumpartial.S
+++ b/arch/arm/lib/csumpartial.S
@@ -40,9 +40,9 @@ td3	.req	lr
                 /* we must have at least one byte. */
                 tst     buf, #1                 @ odd address?
                 movne   sum, sum, ror #8
-                ldrneb  td0, [buf], #1
+                ldrbne  td0, [buf], #1
                 subne   len, len, #1
-                adcnes  sum, sum, td0, put_byte_1
+                adcsne  sum, sum, td0, put_byte_1
 
 .Lless4:                tst     len, #6
                 beq     .Lless8_byte
@@ -68,8 +68,8 @@ td3	.req	lr
                 bne     .Lless8_wordlp
 
 .Lless8_byte:   tst     len, #1                 @ odd number of bytes
-                ldrneb  td0, [buf], #1          @ include last byte
-                adcnes  sum, sum, td0, put_byte_0       @ update checksum
+                ldrbne  td0, [buf], #1          @ include last byte
+                adcsne  sum, sum, td0, put_byte_0       @ update checksum
 
 .Ldone:         adc     r0, sum, #0             @ collect up the last carry
                 ldr     td0, [sp], #4
@@ -78,17 +78,17 @@ td3	.req	lr
                 ldr     pc, [sp], #4            @ return
 
 .Lnot_aligned:  tst     buf, #1                 @ odd address
-                ldrneb  td0, [buf], #1          @ make even
+                ldrbne  td0, [buf], #1          @ make even
                 subne   len, len, #1
-                adcnes  sum, sum, td0, put_byte_1       @ update checksum
+                adcsne  sum, sum, td0, put_byte_1       @ update checksum
 
                 tst     buf, #2                 @ 32-bit aligned?
 #if __LINUX_ARM_ARCH__ >= 4
-                ldrneh  td0, [buf], #2          @ make 32-bit aligned
+                ldrhne  td0, [buf], #2          @ make 32-bit aligned
                 subne   len, len, #2
 #else
-                ldrneb  td0, [buf], #1
-                ldrneb  ip, [buf], #1
+                ldrbne  td0, [buf], #1
+                ldrbne  ip, [buf], #1
                 subne   len, len, #2
 #ifndef __ARMEB__
                 orrne   td0, td0, ip, lsl #8
@@ -96,7 +96,7 @@ td3	.req	lr
                 orrne   td0, ip, td0, lsl #8
 #endif
 #endif
-                adcnes  sum, sum, td0           @ update checksum
+                adcsne  sum, sum, td0           @ update checksum
                 ret     lr
 
 ENTRY(csum_partial)
diff --git a/arch/arm/lib/csumpartialcopygeneric.S b/arch/arm/lib/csumpartialcopygeneric.S
index 10b45909610c..08e17758cbea 100644
--- a/arch/arm/lib/csumpartialcopygeneric.S
+++ b/arch/arm/lib/csumpartialcopygeneric.S
@@ -148,9 +148,9 @@ FN_ENTRY
                 strb    r5, [dst], #1
                 mov     r5, r4, get_byte_2
 .Lexit:         tst     len, #1
-                strneb  r5, [dst], #1
+                strbne  r5, [dst], #1
                 andne   r5, r5, #255
-                adcnes  sum, sum, r5, put_byte_0
+                adcsne  sum, sum, r5, put_byte_0
 
                 /*
                  * If the dst pointer was not 16-bit aligned, we
diff --git a/arch/arm/lib/csumpartialcopyuser.S b/arch/arm/lib/csumpartialcopyuser.S
index b83fdc06286a..f4716d98e0b4 100644
--- a/arch/arm/lib/csumpartialcopyuser.S
+++ b/arch/arm/lib/csumpartialcopyuser.S
@@ -95,7 +95,7 @@
                 add     r2, r2, r1
                 mov     r0, #0                  @ zero the buffer
 9002:           teq     r2, r1
-                strneb  r0, [r1], #1
+                strbne  r0, [r1], #1
                 bne     9002b
                 load_regs
                 .popsection
diff --git a/arch/arm/lib/div64.S b/arch/arm/lib/div64.S
index a9eafe4981eb..4d80f690c48b 100644
--- a/arch/arm/lib/div64.S
+++ b/arch/arm/lib/div64.S
@@ -88,8 +88,8 @@ UNWIND(.fnstart)
         @ Break out early if dividend reaches 0.
 2:      cmp     xh, yl
         orrcs   yh, yh, ip
-        subcss  xh, xh, yl
-        movnes  ip, ip, lsr #1
+        subscs  xh, xh, yl
+        movsne  ip, ip, lsr #1
         mov     yl, yl, lsr #1
         bne     2b
 
diff --git a/arch/arm/lib/floppydma.S b/arch/arm/lib/floppydma.S
index 617150b1baef..de68d3b343e3 100644
--- a/arch/arm/lib/floppydma.S
+++ b/arch/arm/lib/floppydma.S
@@ -14,8 +14,8 @@
                 .global floppy_fiqin_end
 ENTRY(floppy_fiqin_start)
                 subs    r9, r9, #1
-                ldrgtb  r12, [r11, #-4]
-                ldrleb  r12, [r11], #0
+                ldrbgt  r12, [r11, #-4]
+                ldrble  r12, [r11], #0
                 strb    r12, [r10], #1
                 subs    pc, lr, #4
 floppy_fiqin_end:
@@ -23,10 +23,10 @@ floppy_fiqin_end:
                 .global floppy_fiqout_end
 ENTRY(floppy_fiqout_start)
                 subs    r9, r9, #1
-                ldrgeb  r12, [r10], #1
+                ldrbge  r12, [r10], #1
                 movlt   r12, #0
-                strleb  r12, [r11], #0
-                subles  pc, lr, #4
+                strble  r12, [r11], #0
+                subsle  pc, lr, #4
                 strb    r12, [r11, #-4]
                 subs    pc, lr, #4
 floppy_fiqout_end:
diff --git a/arch/arm/lib/io-readsb.S b/arch/arm/lib/io-readsb.S
index c31b2f3153f1..91038a0a77b5 100644
--- a/arch/arm/lib/io-readsb.S
+++ b/arch/arm/lib/io-readsb.S
@@ -16,10 +16,10 @@
                 cmp     ip, #2
                 ldrb    r3, [r0]
                 strb    r3, [r1], #1
-                ldrgeb  r3, [r0]
-                strgeb  r3, [r1], #1
-                ldrgtb  r3, [r0]
-                strgtb  r3, [r1], #1
+                ldrbge  r3, [r0]
+                strbge  r3, [r1], #1
+                ldrbgt  r3, [r0]
+                strbgt  r3, [r1], #1
                 subs    r2, r2, ip
                 bne     .Linsb_aligned
 
@@ -72,7 +72,7 @@ ENTRY(__raw_readsb)
                 bpl     .Linsb_16_lp
 
                 tst     r2, #15
-                ldmeqfd sp!, {r4 - r6, pc}
+                ldmfdeq sp!, {r4 - r6, pc}
 
 .Linsb_no_16:   tst     r2, #8
                 beq     .Linsb_no_8
@@ -109,15 +109,15 @@ ENTRY(__raw_readsb)
                 str     r3, [r1], #4
 
 .Linsb_no_4:    ands    r2, r2, #3
-                ldmeqfd sp!, {r4 - r6, pc}
+                ldmfdeq sp!, {r4 - r6, pc}
 
                 cmp     r2, #2
                 ldrb    r3, [r0]
                 strb    r3, [r1], #1
-                ldrgeb  r3, [r0]
-                strgeb  r3, [r1], #1
-                ldrgtb  r3, [r0]
-                strgtb  r3, [r1]
+                ldrbge  r3, [r0]
+                strbge  r3, [r1], #1
+                ldrbgt  r3, [r0]
+                strbgt  r3, [r1]
 
                 ldmfd   sp!, {r4 - r6, pc}
 ENDPROC(__raw_readsb)
diff --git a/arch/arm/lib/io-readsl.S b/arch/arm/lib/io-readsl.S
index 2ed86fa5465f..f2e2064318d2 100644
--- a/arch/arm/lib/io-readsl.S
+++ b/arch/arm/lib/io-readsl.S
@@ -30,7 +30,7 @@ ENTRY(__raw_readsl)
 2:              movs    r2, r2, lsl #31
                 ldrcs   r3, [r0, #0]
                 ldrcs   ip, [r0, #0]
-                stmcsia r1!, {r3, ip}
+                stmiacs r1!, {r3, ip}
                 ldrne   r3, [r0, #0]
                 strne   r3, [r1, #0]
                 ret     lr
diff --git a/arch/arm/lib/io-readsw-armv3.S b/arch/arm/lib/io-readsw-armv3.S
index 413da9914529..8b25b69c516e 100644
--- a/arch/arm/lib/io-readsw-armv3.S
+++ b/arch/arm/lib/io-readsw-armv3.S
@@ -68,7 +68,7 @@ ENTRY(__raw_readsw)
                 bpl     .Linsw_8_lp
 
                 tst     r2, #7
-                ldmeqfd sp!, {r4, r5, r6, pc}
+                ldmfdeq sp!, {r4, r5, r6, pc}
 
 .Lno_insw_8:    tst     r2, #4
                 beq     .Lno_insw_4
@@ -97,9 +97,9 @@ ENTRY(__raw_readsw)
 
 .Lno_insw_2:    tst     r2, #1
                 ldrne   r3, [r0]
-                strneb  r3, [r1], #1
+                strbne  r3, [r1], #1
                 movne   r3, r3, lsr #8
-                strneb  r3, [r1]
+                strbne  r3, [r1]
 
                 ldmfd   sp!, {r4, r5, r6, pc}
 
diff --git a/arch/arm/lib/io-readsw-armv4.S b/arch/arm/lib/io-readsw-armv4.S
index d9a45e9692ae..5efdd66f5dcd 100644
--- a/arch/arm/lib/io-readsw-armv4.S
+++ b/arch/arm/lib/io-readsw-armv4.S
@@ -76,8 +76,8 @@ ENTRY(__raw_readsw)
                 pack    r3, r3, ip
                 str     r3, [r1], #4
 
-.Lno_insw_2:    ldrneh  r3, [r0]
-                strneh  r3, [r1]
+.Lno_insw_2:    ldrhne  r3, [r0]
+                strhne  r3, [r1]
 
                 ldmfd   sp!, {r4, r5, pc}
 
@@ -94,7 +94,7 @@ ENTRY(__raw_readsw)
 #endif
 
 .Linsw_noalign: stmfd   sp!, {r4, lr}
-                ldrccb  ip, [r1, #-1]!
+                ldrbcc  ip, [r1, #-1]!
                 bcc     1f
 
                 ldrh    ip, [r0]
@@ -121,11 +121,11 @@ ENTRY(__raw_readsw)
 
 3:              tst     r2, #1
                 strb    ip, [r1], #1
-                ldrneh  ip, [r0]
+                ldrhne  ip, [r0]
    _BE_ONLY_(   movne   ip, ip, ror #8          )
-                strneb  ip, [r1], #1
+                strbne  ip, [r1], #1
    _LE_ONLY_(   movne   ip, ip, lsr #8          )
    _BE_ONLY_(   movne   ip, ip, lsr #24         )
-                strneb  ip, [r1]
+                strbne  ip, [r1]
                 ldmfd   sp!, {r4, pc}
 ENDPROC(__raw_readsw)
diff --git a/arch/arm/lib/io-writesb.S b/arch/arm/lib/io-writesb.S
index a46bbc9b168b..7d2881a2381e 100644
--- a/arch/arm/lib/io-writesb.S
+++ b/arch/arm/lib/io-writesb.S
@@ -36,10 +36,10 @@
                 cmp     ip, #2
                 ldrb    r3, [r1], #1
                 strb    r3, [r0]
-                ldrgeb  r3, [r1], #1
-                strgeb  r3, [r0]
-                ldrgtb  r3, [r1], #1
-                strgtb  r3, [r0]
+                ldrbge  r3, [r1], #1
+                strbge  r3, [r0]
+                ldrbgt  r3, [r1], #1
+                strbgt  r3, [r0]
                 subs    r2, r2, ip
                 bne     .Loutsb_aligned
 
@@ -64,7 +64,7 @@ ENTRY(__raw_writesb)
                 bpl     .Loutsb_16_lp
 
                 tst     r2, #15
-                ldmeqfd sp!, {r4, r5, pc}
+                ldmfdeq sp!, {r4, r5, pc}
 
 .Loutsb_no_16:  tst     r2, #8
                 beq     .Loutsb_no_8
@@ -80,15 +80,15 @@ ENTRY(__raw_writesb)
                 outword r3
 
 .Loutsb_no_4:   ands    r2, r2, #3
-                ldmeqfd sp!, {r4, r5, pc}
+                ldmfdeq sp!, {r4, r5, pc}
 
                 cmp     r2, #2
                 ldrb    r3, [r1], #1
                 strb    r3, [r0]
-                ldrgeb  r3, [r1], #1
-                strgeb  r3, [r0]
-                ldrgtb  r3, [r1]
-                strgtb  r3, [r0]
+                ldrbge  r3, [r1], #1
+                strbge  r3, [r0]
+                ldrbgt  r3, [r1]
+                strbgt  r3, [r0]
 
                 ldmfd   sp!, {r4, r5, pc}
 ENDPROC(__raw_writesb)
diff --git a/arch/arm/lib/io-writesl.S b/arch/arm/lib/io-writesl.S
index 4ea2435988c1..7596ac0c90b0 100644
--- a/arch/arm/lib/io-writesl.S
+++ b/arch/arm/lib/io-writesl.S
@@ -28,7 +28,7 @@ ENTRY(__raw_writesl)
                 bpl     1b
                 ldmfd   sp!, {r4, lr}
 2:              movs    r2, r2, lsl #31
-                ldmcsia r1!, {r3, ip}
+                ldmiacs r1!, {r3, ip}
                 strcs   r3, [r0, #0]
                 ldrne   r3, [r1, #0]
                 strcs   ip, [r0, #0]
diff --git a/arch/arm/lib/io-writesw-armv3.S b/arch/arm/lib/io-writesw-armv3.S
index 121789eb6802..cb94b9b49405 100644
--- a/arch/arm/lib/io-writesw-armv3.S
+++ b/arch/arm/lib/io-writesw-armv3.S
@@ -79,7 +79,7 @@ ENTRY(__raw_writesw)
                 bpl     .Loutsw_8_lp
 
                 tst     r2, #7
-                ldmeqfd sp!, {r4, r5, r6, pc}
+                ldmfdeq sp!, {r4, r5, r6, pc}
 
 .Lno_outsw_8:   tst     r2, #4
                 beq     .Lno_outsw_4
diff --git a/arch/arm/lib/io-writesw-armv4.S b/arch/arm/lib/io-writesw-armv4.S
index 269f90c51ad2..e6645b2f249e 100644
--- a/arch/arm/lib/io-writesw-armv4.S
+++ b/arch/arm/lib/io-writesw-armv4.S
@@ -61,8 +61,8 @@ ENTRY(__raw_writesw)
                 ldr     r3, [r1], #4
                 outword r3
 
-.Lno_outsw_2:   ldrneh  r3, [r1]
-                strneh  r3, [r0]
+.Lno_outsw_2:   ldrhne  r3, [r1]
+                strhne  r3, [r0]
 
                 ldmfd   sp!, {r4, r5, pc}
 
@@ -95,6 +95,6 @@ ENTRY(__raw_writesw)
 
                 tst     r2, #1
 3:              movne   ip, r3, lsr #8
-                strneh  ip, [r0]
+                strhne  ip, [r0]
                 ret     lr
 ENDPROC(__raw_writesw)
diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S
index 9397b2e532af..c23f9d9e2970 100644
--- a/arch/arm/lib/lib1funcs.S
+++ b/arch/arm/lib/lib1funcs.S
@@ -96,7 +96,7 @@ Boston, MA 02111-1307, USA.  */
         subhs   \dividend, \dividend, \divisor, lsr #3
         orrhs   \result,   \result,   \curbit,  lsr #3
         cmp     \dividend, #0                   @ Early termination?
-        movnes  \curbit,   \curbit,  lsr #4     @ No, any more bits to do?
+        movsne  \curbit,   \curbit,  lsr #4     @ No, any more bits to do?
         movne   \divisor,  \divisor, lsr #4
         bne     1b
 
@@ -182,7 +182,7 @@ Boston, MA 02111-1307, USA.  */
         subhs   \dividend, \dividend, \divisor, lsr #3
         cmp     \dividend, #1
         mov     \divisor, \divisor, lsr #4
-        subges  \order, \order, #4
+        subsge  \order, \order, #4
         bge     1b
 
         tst     \order, #3
diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
index 64111bd4440b..4a6997bb4404 100644
--- a/arch/arm/lib/memcpy.S
+++ b/arch/arm/lib/memcpy.S
@@ -30,7 +30,7 @@
         .endm
 
         .macro ldr1b ptr reg cond=al abort
-        ldr\cond\()b \reg, [\ptr], #1
+        ldrb\cond \reg, [\ptr], #1
         .endm
 
         .macro str1w ptr reg abort
@@ -42,7 +42,7 @@
         .endm
 
         .macro str1b ptr reg cond=al abort
-        str\cond\()b \reg, [\ptr], #1
+        strb\cond \reg, [\ptr], #1
         .endm
 
         .macro enter reg1 reg2
diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S
index 69a9d47fc5ab..d70304cb2cd0 100644
--- a/arch/arm/lib/memmove.S
+++ b/arch/arm/lib/memmove.S
@@ -59,7 +59,7 @@ ENTRY(memmove)
                 blt     5f
 
         CALGN(  ands    ip, r0, #31             )
-        CALGN(  sbcnes  r4, ip, r2              )  @ C is always set here
+        CALGN(  sbcsne  r4, ip, r2              )  @ C is always set here
         CALGN(  bcs     2f                      )
         CALGN(  adr     r4, 6f                  )
         CALGN(  subs    r2, r2, ip              )  @ C is set here
@@ -114,20 +114,20 @@ ENTRY(memmove)
         UNWIND( .save   {r0, r4, lr}            ) @ still in first stmfd block
 
 8:              movs    r2, r2, lsl #31
-                ldrneb  r3, [r1, #-1]!
-                ldrcsb  r4, [r1, #-1]!
-                ldrcsb  ip, [r1, #-1]
-                strneb  r3, [r0, #-1]!
-                strcsb  r4, [r0, #-1]!
-                strcsb  ip, [r0, #-1]
+                ldrbne  r3, [r1, #-1]!
+                ldrbcs  r4, [r1, #-1]!
+                ldrbcs  ip, [r1, #-1]
+                strbne  r3, [r0, #-1]!
+                strbcs  r4, [r0, #-1]!
+                strbcs  ip, [r0, #-1]
                 ldmfd   sp!, {r0, r4, pc}
 
 9:              cmp     ip, #2
-                ldrgtb  r3, [r1, #-1]!
-                ldrgeb  r4, [r1, #-1]!
+                ldrbgt  r3, [r1, #-1]!
+                ldrbge  r4, [r1, #-1]!
                 ldrb    lr, [r1, #-1]!
-                strgtb  r3, [r0, #-1]!
-                strgeb  r4, [r0, #-1]!
+                strbgt  r3, [r0, #-1]!
+                strbge  r4, [r0, #-1]!
                 subs    r2, r2, ip
                 strb    lr, [r0, #-1]!
                 blt     8b
@@ -150,7 +150,7 @@ ENTRY(memmove)
                 blt     14f
 
         CALGN(  ands    ip, r0, #31             )
-        CALGN(  sbcnes  r4, ip, r2              )  @ C is always set here
+        CALGN(  sbcsne  r4, ip, r2              )  @ C is always set here
         CALGN(  subcc   r2, r2, ip              )
         CALGN(  bcc     15f                     )
 
diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S
index ed6d35d9cdb5..5593a45e0a8c 100644
--- a/arch/arm/lib/memset.S
+++ b/arch/arm/lib/memset.S
@@ -44,20 +44,20 @@ UNWIND( .save {r8, lr}      )
         mov     lr, r3
 
 2:      subs    r2, r2, #64
-        stmgeia ip!, {r1, r3, r8, lr}   @ 64 bytes at a time.
-        stmgeia ip!, {r1, r3, r8, lr}
-        stmgeia ip!, {r1, r3, r8, lr}
-        stmgeia ip!, {r1, r3, r8, lr}
+        stmiage ip!, {r1, r3, r8, lr}   @ 64 bytes at a time.
+        stmiage ip!, {r1, r3, r8, lr}
+        stmiage ip!, {r1, r3, r8, lr}
+        stmiage ip!, {r1, r3, r8, lr}
         bgt     2b
-        ldmeqfd sp!, {r8, pc}           @ Now <64 bytes to go.
+        ldmfdeq sp!, {r8, pc}           @ Now <64 bytes to go.
 /*
  * No need to correct the count; we're only testing bits from now on
  */
         tst     r2, #32
-        stmneia ip!, {r1, r3, r8, lr}
-        stmneia ip!, {r1, r3, r8, lr}
+        stmiane ip!, {r1, r3, r8, lr}
+        stmiane ip!, {r1, r3, r8, lr}
         tst     r2, #16
-        stmneia ip!, {r1, r3, r8, lr}
+        stmiane ip!, {r1, r3, r8, lr}
         ldmfd   sp!, {r8, lr}
 UNWIND( .fnend              )
 
@@ -87,22 +87,22 @@ UNWIND( .save {r4-r8, lr}      )
         rsb     r8, r8, #32
         sub     r2, r2, r8
         movs    r8, r8, lsl #(32 - 4)
-        stmcsia ip!, {r4, r5, r6, r7}
-        stmmiia ip!, {r4, r5}
+        stmiacs ip!, {r4, r5, r6, r7}
+        stmiami ip!, {r4, r5}
         tst     r8, #(1 << 30)
         mov     r8, r1
         strne   r1, [ip], #4
 
 3:      subs    r2, r2, #64
-        stmgeia ip!, {r1, r3-r8, lr}
-        stmgeia ip!, {r1, r3-r8, lr}
+        stmiage ip!, {r1, r3-r8, lr}
+        stmiage ip!, {r1, r3-r8, lr}
         bgt     3b
-        ldmeqfd sp!, {r4-r8, pc}
+        ldmfdeq sp!, {r4-r8, pc}
 
         tst     r2, #32
-        stmneia ip!, {r1, r3-r8, lr}
+        stmiane ip!, {r1, r3-r8, lr}
         tst     r2, #16
-        stmneia ip!, {r4-r7}
+        stmiane ip!, {r4-r7}
         ldmfd   sp!, {r4-r8, lr}
 UNWIND( .fnend                 )
 
@@ -110,7 +110,7 @@ UNWIND( .fnend                 )
 
 UNWIND( .fnstart            )
 4:      tst     r2, #8
-        stmneia ip!, {r1, r3}
+        stmiane ip!, {r1, r3}
         tst     r2, #4
         strne   r1, [ip], #4
 /*
@@ -118,17 +118,17 @@ UNWIND( .fnstart            )
  * may have an unaligned pointer as well.
  */
 5:      tst     r2, #2
-        strneb  r1, [ip], #1
-        strneb  r1, [ip], #1
+        strbne  r1, [ip], #1
+        strbne  r1, [ip], #1
         tst     r2, #1
-        strneb  r1, [ip], #1
+        strbne  r1, [ip], #1
         ret     lr
 
 6:      subs    r2, r2, #4              @ 1 do we have enough
         blt     5b                      @ 1 bytes to align with?
         cmp     r3, #2                  @ 1
-        strltb  r1, [ip], #1            @ 1
-        strleb  r1, [ip], #1            @ 1
+        strblt  r1, [ip], #1            @ 1
+        strble  r1, [ip], #1            @ 1
         strb    r1, [ip], #1            @ 1
         add     r2, r2, r3              @ 1 (r2 = r2 - (4 - r3))
         b       1b
diff --git a/arch/arm/lib/xor-neon.c b/arch/arm/lib/xor-neon.c
index 2c40aeab3eaa..c691b901092f 100644
--- a/arch/arm/lib/xor-neon.c
+++ b/arch/arm/lib/xor-neon.c
@@ -14,7 +14,7 @@
 MODULE_LICENSE("GPL");
 
 #ifndef __ARM_NEON__
-#error You should compile this file with '-mfloat-abi=softfp -mfpu=neon'
+#error You should compile this file with '-march=armv7-a -mfloat-abi=softfp -mfpu=neon'
 #endif
 
 /*
diff --git a/arch/arm/mach-actions/platsmp.c b/arch/arm/mach-actions/platsmp.c
index 3efaa10efc43..4fd479c948e6 100644
--- a/arch/arm/mach-actions/platsmp.c
+++ b/arch/arm/mach-actions/platsmp.c
@@ -39,10 +39,6 @@ static void __iomem *sps_base_addr;
 static void __iomem *timer_base_addr;
 static int ncores;
 
-static DEFINE_SPINLOCK(boot_lock);
-
-void owl_secondary_startup(void);
-
 static int s500_wakeup_secondary(unsigned int cpu)
 {
         int ret;
@@ -84,7 +80,6 @@ static int s500_wakeup_secondary(unsigned int cpu)
 
 static int s500_smp_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        unsigned long timeout;
         int ret;
 
         ret = s500_wakeup_secondary(cpu);
@@ -93,21 +88,11 @@ static int s500_smp_boot_secondary(unsigned int cpu, struct task_struct *idle)
 
         udelay(10);
 
-        spin_lock(&boot_lock);
-
         smp_send_reschedule(cpu);
 
-        timeout = jiffies + (1 * HZ);
-        while (time_before(jiffies, timeout)) {
-                if (pen_release == -1)
-                        break;
-        }
-
         writel(0, timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);
         writel(0, timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);
 
-        spin_unlock(&boot_lock);
-
         return 0;
 }
 
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index a067adf9f1ee..4ef1e55f4a0b 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -167,6 +167,7 @@ config ARCH_BCM2835
         select BCM2835_TIMER
         select PINCTRL
         select PINCTRL_BCM2835
+        select MFD_CORE
         help
           This enables support for the Broadcom BCM2835 and BCM2836 SoCs.
           This SoC is used in the Raspberry Pi and Roku 2 devices.
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index 318394ed5c7a..95a11d5b3587 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -83,7 +83,7 @@ static void __iomem *cns3xxx_pci_map_bus(struct pci_bus *bus,
         } else /* remote PCI bus */
                 base = cnspci->cfg1_regs + ((busno & 0xf) << 20);
 
-        return base + (where & 0xffc) + (devfn << 12);
+        return base + where + (devfn << 12);
 }
 
 static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
@@ -93,7 +93,7 @@ static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
         u32 mask = (0x1ull << (size * 8)) - 1;
         int shift = (where % 4) * 8;
 
-        ret = pci_generic_config_read32(bus, devfn, where, size, val);
+        ret = pci_generic_config_read(bus, devfn, where, size, val);
 
         if (ret == PCIBIOS_SUCCESSFUL && !bus->number && !devfn &&
             (where & 0xffc) == PCI_CLASS_REVISION)
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index da8a039d65f9..5a59cebc7d0a 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -1,13 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 if ARCH_DAVINCI
 
-config AINTC
-        bool
-
-config CP_INTC
-        bool
-        select IRQ_DOMAIN
-
 config ARCH_DAVINCI_DMx
         bool
 
@@ -17,17 +10,17 @@ comment "DaVinci Core Type"
 
 config ARCH_DAVINCI_DM644x
         bool "DaVinci 644x based system"
-        select AINTC
+        select DAVINCI_AINTC
         select ARCH_DAVINCI_DMx
 
 config ARCH_DAVINCI_DM355
         bool "DaVinci 355 based system"
-        select AINTC
+        select DAVINCI_AINTC
         select ARCH_DAVINCI_DMx
 
 config ARCH_DAVINCI_DM646x
         bool "DaVinci 646x based system"
-        select AINTC
+        select DAVINCI_AINTC
         select ARCH_DAVINCI_DMx
 
 config ARCH_DAVINCI_DA830
@@ -36,20 +29,20 @@ config ARCH_DAVINCI_DA830
         select ARCH_DAVINCI_DA8XX
         # needed on silicon revs 1.0, 1.1:
         select CPU_DCACHE_WRITETHROUGH if !CPU_DCACHE_DISABLE
-        select CP_INTC
+        select DAVINCI_CP_INTC
 
 config ARCH_DAVINCI_DA850
         bool "DA850/OMAP-L138/AM18x based system"
         depends on !ARCH_DAVINCI_DMx || (AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT)
         select ARCH_DAVINCI_DA8XX
-        select CP_INTC
+        select DAVINCI_CP_INTC
 
 config ARCH_DAVINCI_DA8XX
         bool
 
 config ARCH_DAVINCI_DM365
         bool "DaVinci 365 based system"
-        select AINTC
+        select DAVINCI_AINTC
         select ARCH_DAVINCI_DMx
 
 comment "DaVinci Board Type"
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 93d271b4d84b..f76a8482784f 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -18,9 +18,6 @@ obj-$(CONFIG_ARCH_DAVINCI_DM365)	+= dm365.o devices.o
 obj-$(CONFIG_ARCH_DAVINCI_DA830)        += da830.o devices-da8xx.o usb-da8xx.o
 obj-$(CONFIG_ARCH_DAVINCI_DA850)        += da850.o devices-da8xx.o usb-da8xx.o
 
-obj-$(CONFIG_AINTC)                     += irq.o
-obj-$(CONFIG_CP_INTC)                   += cp_intc.o
-
 # Board specific
 obj-$(CONFIG_MACH_DA8XX_DT)             += da8xx-dt.o pdata-quirks.o
 obj-$(CONFIG_MACH_DAVINCI_EVM)          += board-dm644x-evm.o
diff --git a/arch/arm/mach-davinci/asp.h b/arch/arm/mach-davinci/asp.h
index 495aa6907cbc..d0ecd1d0f084 100644
--- a/arch/arm/mach-davinci/asp.h
+++ b/arch/arm/mach-davinci/asp.h
@@ -49,9 +49,9 @@
 #define DAVINCI_DA830_DMA_MCASP2_AXEVT  5
 
 /* Interrupts */
-#define DAVINCI_ASP0_RX_INT     IRQ_MBRINT
-#define DAVINCI_ASP0_TX_INT     IRQ_MBXINT
-#define DAVINCI_ASP1_RX_INT     IRQ_MBRINT
-#define DAVINCI_ASP1_TX_INT     IRQ_MBXINT
+#define DAVINCI_ASP0_RX_INT     DAVINCI_INTC_IRQ(IRQ_MBRINT)
+#define DAVINCI_ASP0_TX_INT     DAVINCI_INTC_IRQ(IRQ_MBXINT)
+#define DAVINCI_ASP1_RX_INT     DAVINCI_INTC_IRQ(IRQ_MBRINT)
+#define DAVINCI_ASP1_TX_INT     DAVINCI_INTC_IRQ(IRQ_MBXINT)
 
 #endif /* __ASM_ARCH_DAVINCI_ASP_H */
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index e52ec1619b70..ff097ecfa451 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -18,7 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
 #include <linux/platform_data/pcf857x.h>
-#include <linux/platform_data/at24.h>
+#include <linux/property.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/spi/spi.h>
@@ -36,10 +36,11 @@
 #include <asm/mach/arch.h>
 
 #include <mach/common.h>
-#include "cp_intc.h"
 #include <mach/mux.h>
 #include <mach/da8xx.h>
 
+#include "irqs.h"
+
 #define DA830_EVM_PHY_ID                ""
 /*
  * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4].
@@ -52,62 +53,19 @@ static const short da830_evm_usb11_pins[] = {
         -1
 };
 
-static da8xx_ocic_handler_t da830_evm_usb_ocic_handler;
-
-static int da830_evm_usb_set_power(unsigned port, int on)
-{
-        gpio_set_value(ON_BD_USB_DRV, on);
-        return 0;
-}
-
-static int da830_evm_usb_get_power(unsigned port)
-{
-        return gpio_get_value(ON_BD_USB_DRV);
-}
-
-static int da830_evm_usb_get_oci(unsigned port)
-{
-        return !gpio_get_value(ON_BD_USB_OVC);
-}
-
-static irqreturn_t da830_evm_usb_ocic_irq(int, void *);
-
-static int da830_evm_usb_ocic_notify(da8xx_ocic_handler_t handler)
-{
-        int irq         = gpio_to_irq(ON_BD_USB_OVC);
-        int error       = 0;
-
-        if (handler != NULL) {
-                da830_evm_usb_ocic_handler = handler;
-
-                error = request_irq(irq, da830_evm_usb_ocic_irq,
-                                    IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
-                                    "OHCI over-current indicator", NULL);
-                if (error)
-                        pr_err("%s: could not request IRQ to watch over-current indicator changes\n",
-                               __func__);
-        } else
-                free_irq(irq, NULL);
-
-        return error;
-}
+static struct gpiod_lookup_table da830_evm_usb_gpio_lookup = {
+        .dev_id         = "ohci-da8xx",
+        .table = {
+                GPIO_LOOKUP("davinci_gpio", ON_BD_USB_DRV, "vbus", 0),
+                GPIO_LOOKUP("davinci_gpio", ON_BD_USB_OVC, "oc", 0),
+        },
+};
 
 static struct da8xx_ohci_root_hub da830_evm_usb11_pdata = {
-        .set_power      = da830_evm_usb_set_power,
-        .get_power      = da830_evm_usb_get_power,
-        .get_oci        = da830_evm_usb_get_oci,
-        .ocic_notify    = da830_evm_usb_ocic_notify,
-
         /* TPS2065 switch @ 5V */
         .potpgt         = (3 + 1) / 2,  /* 3 ms max */
 };
 
-static irqreturn_t da830_evm_usb_ocic_irq(int irq, void *dev_id)
-{
-        da830_evm_usb_ocic_handler(&da830_evm_usb11_pdata, 1);
-        return IRQ_HANDLED;
-}
-
 static __init void da830_evm_usb_init(void)
 {
         int ret;
@@ -142,21 +100,7 @@ static __init void da830_evm_usb_init(void)
                 return;
         }
 
-        ret = gpio_request(ON_BD_USB_DRV, "ON_BD_USB_DRV");
-        if (ret) {
-                pr_err("%s: failed to request GPIO for USB 1.1 port power control: %d\n",
-                       __func__, ret);
-                return;
-        }
-        gpio_direction_output(ON_BD_USB_DRV, 0);
-
-        ret = gpio_request(ON_BD_USB_OVC, "ON_BD_USB_OVC");
-        if (ret) {
-                pr_err("%s: failed to request GPIO for USB 1.1 port over-current indicator: %d\n",
-                       __func__, ret);
-                return;
-        }
-        gpio_direction_input(ON_BD_USB_OVC);
+        gpiod_add_lookup_table(&da830_evm_usb_gpio_lookup);
 
         ret = da8xx_register_usb11(&da830_evm_usb11_pdata);
         if (ret)
@@ -208,9 +152,9 @@ static struct gpiod_lookup_table mmc_gpios_table = {
         .dev_id = "da830-mmc.0",
         .table = {
                 /* gpio chip 1 contains gpio range 32-63 */
-                GPIO_LOOKUP("davinci_gpio.0", DA830_MMCSD_CD_PIN, "cd",
+                GPIO_LOOKUP("davinci_gpio", DA830_MMCSD_CD_PIN, "cd",
                             GPIO_ACTIVE_LOW),
-                GPIO_LOOKUP("davinci_gpio.0", DA830_MMCSD_WP_PIN, "wp",
+                GPIO_LOOKUP("davinci_gpio", DA830_MMCSD_WP_PIN, "wp",
                             GPIO_ACTIVE_LOW),
         },
 };
@@ -457,12 +401,9 @@ static struct nvmem_cell_lookup da830_evm_nvmem_cell_lookup = {
         .con_id         = "mac-address",
 };
 
-static struct at24_platform_data da830_evm_i2c_eeprom_info = {
-        .byte_len       = SZ_256K / 8,
-        .page_size      = 64,
-        .flags          = AT24_FLAG_ADDR16,
-        .setup          = davinci_get_mac_addr,
-        .context        = (void *)0x7f00,
+static const struct property_entry da830_evm_i2c_eeprom_properties[] = {
+        PROPERTY_ENTRY_U32("pagesize", 64),
+        { }
 };
 
 static int __init da830_evm_ui_expander_setup(struct i2c_client *client,
@@ -496,7 +437,7 @@ static struct pcf857x_platform_data __initdata da830_evm_ui_expander_info = {
 static struct i2c_board_info __initdata da830_evm_i2c_devices[] = {
         {
                 I2C_BOARD_INFO("24c256", 0x50),
-                .platform_data  = &da830_evm_i2c_eeprom_info,
+                .properties = da830_evm_i2c_eeprom_properties,
         },
         {
                 I2C_BOARD_INFO("tlv320aic3x", 0x18),
@@ -693,7 +634,7 @@ static void __init da830_evm_map_io(void)
 MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM")
         .atag_offset    = 0x100,
         .map_io         = da830_evm_map_io,
-        .init_irq       = cp_intc_init,
+        .init_irq       = da830_init_irq,
         .init_time      = da830_init_time,
         .init_machine   = da830_evm_init,
         .init_late      = davinci_init_late,
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 6a29baf0a289..1fdc9283a8c5 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -43,9 +43,10 @@
 #include <linux/spi/flash.h>
 
 #include <mach/common.h>
-#include "cp_intc.h"
 #include <mach/da8xx.h>
 #include <mach/mux.h>
+
+#include "irqs.h"
 #include "sram.h"
 
 #include <asm/mach-types.h>
@@ -150,32 +151,6 @@ static struct spi_board_info da850evm_spi_info[] = {
         },
 };
 
-#ifdef CONFIG_MTD
-static void da850_evm_m25p80_notify_add(struct mtd_info *mtd)
-{
-        char *mac_addr = davinci_soc_info.emac_pdata->mac_addr;
-        size_t retlen;
-
-        if (!strcmp(mtd->name, "MAC-Address")) {
-                mtd_read(mtd, 0, ETH_ALEN, &retlen, mac_addr);
-                if (retlen == ETH_ALEN)
-                        pr_info("Read MAC addr from SPI Flash: %pM\n",
-                                mac_addr);
-        }
-}
-
-static struct mtd_notifier da850evm_spi_notifier = {
-        .add    = da850_evm_m25p80_notify_add,
-};
-
-static void da850_evm_setup_mac_addr(void)
-{
-        register_mtd_user(&da850evm_spi_notifier);
-}
-#else
-static void da850_evm_setup_mac_addr(void) { }
-#endif
-
 static struct mtd_partition da850_evm_norflash_partition[] = {
         {
                 .name           = "bootloaders + env",
@@ -805,9 +780,9 @@ static struct gpiod_lookup_table mmc_gpios_table = {
         .dev_id = "da830-mmc.0",
         .table = {
                 /* gpio chip 2 contains gpio range 64-95 */
-                GPIO_LOOKUP("davinci_gpio.0", DA850_MMCSD_CD_PIN, "cd",
+                GPIO_LOOKUP("davinci_gpio", DA850_MMCSD_CD_PIN, "cd",
                             GPIO_ACTIVE_LOW),
-                GPIO_LOOKUP("davinci_gpio.0", DA850_MMCSD_WP_PIN, "wp",
+                GPIO_LOOKUP("davinci_gpio", DA850_MMCSD_WP_PIN, "wp",
                             GPIO_ACTIVE_HIGH),
         },
 };
@@ -1064,6 +1039,17 @@ static const short da850_evm_rmii_pins[] = {
         -1
 };
 
+static struct gpiod_hog da850_evm_emac_gpio_hogs[] = {
+        {
+                .chip_label     = "davinci_gpio",
+                .chip_hwnum     = DA850_MII_MDIO_CLKEN_PIN,
+                .line_name      = "mdio_clk_en",
+                .lflags         = 0,
+                /* dflags set in da850_evm_config_emac() */
+        },
+        { }
+};
+
 static int __init da850_evm_config_emac(void)
 {
         void __iomem *cfg_chip3_base;
@@ -1102,14 +1088,9 @@ static int __init da850_evm_config_emac(void)
         if (ret)
                 pr_warn("%s:GPIO(2,6) mux setup failed\n", __func__);
 
-        ret = gpio_request(DA850_MII_MDIO_CLKEN_PIN, "mdio_clk_en");
-        if (ret) {
-                pr_warn("Cannot open GPIO %d\n", DA850_MII_MDIO_CLKEN_PIN);
-                return ret;
-        }
-
-        /* Enable/Disable MII MDIO clock */
-        gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_en);
+        da850_evm_emac_gpio_hogs[0].dflags = rmii_en ? GPIOD_OUT_HIGH
+                                                     : GPIOD_OUT_LOW;
+        gpiod_add_hogs(da850_evm_emac_gpio_hogs);
 
         soc_info->emac_pdata->phy_id = DA850_EVM_PHY_ID;
 
@@ -1494,8 +1475,6 @@ static __init void da850_evm_init(void)
         if (ret)
                 pr_warn("%s: SATA registration failed: %d\n", __func__, ret);
 
-        da850_evm_setup_mac_addr();
-
         ret = da8xx_register_rproc();
         if (ret)
                 pr_warn("%s: dsp/rproc registration failed: %d\n",
@@ -1521,7 +1500,7 @@ static void __init da850_evm_map_io(void)
 MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
         .atag_offset    = 0x100,
         .map_io         = da850_evm_map_io,
-        .init_irq       = cp_intc_init,
+        .init_irq       = da850_init_irq,
         .init_time      = da850_init_time,
         .init_machine   = da850_evm_init,
         .init_late      = davinci_init_late,
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index f53a461a606f..64d81fc86f14 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -117,9 +117,9 @@ static struct platform_device davinci_nand_device = {
 static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
         .dev_id = "i2c_davinci.1",
         .table = {
-                GPIO_LOOKUP("davinci_gpio.0", DM355_I2C_SDA_PIN, "sda",
+                GPIO_LOOKUP("davinci_gpio", DM355_I2C_SDA_PIN, "sda",
                             GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
-                GPIO_LOOKUP("davinci_gpio.0", DM355_I2C_SCL_PIN, "scl",
+                GPIO_LOOKUP("davinci_gpio", DM355_I2C_SCL_PIN, "scl",
                             GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
         },
 };
@@ -438,7 +438,7 @@ static __init void dm355_evm_init(void)
 MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
         .atag_offset  = 0x100,
         .map_io       = dm355_evm_map_io,
-        .init_irq     = davinci_irq_init,
+        .init_irq     = dm355_init_irq,
         .init_time      = dm355_init_time,
         .init_machine = dm355_evm_init,
         .init_late      = davinci_init_late,
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 0fdf1d03eb11..b9e9950dd300 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -273,7 +273,7 @@ static __init void dm355_leopard_init(void)
 MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
         .atag_offset  = 0x100,
         .map_io       = dm355_leopard_map_io,
-        .init_irq     = davinci_irq_init,
+        .init_irq     = dm355_init_irq,
         .init_time      = dm355_init_time,
         .init_machine = dm355_leopard_init,
         .init_late      = davinci_init_late,
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index e3b0b701e395..150a36f333df 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -18,7 +18,7 @@
 #include <linux/i2c.h>
 #include <linux/io.h>
 #include <linux/clk.h>
-#include <linux/platform_data/at24.h>
+#include <linux/property.h>
 #include <linux/leds.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -225,18 +225,15 @@ static struct nvmem_cell_lookup davinci_nvmem_cell_lookup = {
         .con_id         = "mac-address",
 };
 
-static struct at24_platform_data eeprom_info = {
-        .byte_len       = (256*1024) / 8,
-        .page_size      = 64,
-        .flags          = AT24_FLAG_ADDR16,
-        .setup          = davinci_get_mac_addr,
-        .context        = (void *)0x7f00,
+static const struct property_entry eeprom_properties[] = {
+        PROPERTY_ENTRY_U32("pagesize", 64),
+        { }
 };
 
 static struct i2c_board_info i2c_info[] = {
         {
                 I2C_BOARD_INFO("24c256", 0x50),
-                .platform_data  = &eeprom_info,
+                .properties = eeprom_properties,
         },
         {
                 I2C_BOARD_INFO("tlv320aic3x", 0x18),
@@ -834,7 +831,7 @@ static __init void dm365_evm_init(void)
 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
         .atag_offset    = 0x100,
         .map_io         = dm365_evm_map_io,
-        .init_irq       = davinci_irq_init,
+        .init_irq       = dm365_init_irq,
         .init_time      = dm365_init_time,
         .init_machine   = dm365_evm_init,
         .init_late      = davinci_init_late,
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index e1428115067f..de15f782816e 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -16,8 +16,8 @@
 #include <linux/gpio/machine.h>
 #include <linux/i2c.h>
 #include <linux/platform_data/pcf857x.h>
-#include <linux/platform_data/at24.h>
 #include <linux/platform_data/gpio-davinci.h>
+#include <linux/property.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/rawnand.h>
 #include <linux/mtd/partitions.h>
@@ -36,9 +36,10 @@
 #include <asm/mach/arch.h>
 
 #include <mach/common.h>
-#include <linux/platform_data/i2c-davinci.h>
-#include <mach/serial.h>
 #include <mach/mux.h>
+#include <mach/serial.h>
+
+#include <linux/platform_data/i2c-davinci.h>
 #include <linux/platform_data/mtd-davinci.h>
 #include <linux/platform_data/mmc-davinci.h>
 #include <linux/platform_data/usb-davinci.h>
@@ -46,6 +47,7 @@
 #include <linux/platform_data/ti-aemif.h>
 
 #include "davinci.h"
+#include "irqs.h"
 
 #define DM644X_EVM_PHY_ID               "davinci_mdio-0:01"
 #define LXT971_PHY_ID   (0x001378e2)
@@ -532,12 +534,9 @@ static struct nvmem_cell_lookup dm644evm_nvmem_cell_lookup = {
         .con_id         = "mac-address",
 };
 
-static struct at24_platform_data eeprom_info = {
-        .byte_len       = (256*1024) / 8,
-        .page_size      = 64,
-        .flags          = AT24_FLAG_ADDR16,
-        .setup          = davinci_get_mac_addr,
-        .context        = (void *)0x7f00,
+static const struct property_entry eeprom_properties[] = {
+        PROPERTY_ENTRY_U32("pagesize", 64),
+        { }
 };
 
 /*
@@ -647,7 +646,7 @@ static struct i2c_board_info __initdata i2c_info[] =  {
         },
         {
                 I2C_BOARD_INFO("24c256", 0x50),
-                .platform_data  = &eeprom_info,
+                .properties = eeprom_properties,
         },
         {
                 I2C_BOARD_INFO("tlv320aic33", 0x1b),
@@ -660,9 +659,9 @@ static struct i2c_board_info __initdata i2c_info[] =  {
 static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
         .dev_id = "i2c_davinci.1",
         .table = {
-                GPIO_LOOKUP("davinci_gpio.0", DM644X_I2C_SDA_PIN, "sda",
+                GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SDA_PIN, "sda",
                             GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
-                GPIO_LOOKUP("davinci_gpio.0", DM644X_I2C_SCL_PIN, "scl",
+                GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SCL_PIN, "scl",
                             GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
         },
 };
@@ -889,7 +888,7 @@ MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
         /* Maintainer: MontaVista Software <source@mvista.com> */
         .atag_offset  = 0x100,
         .map_io       = davinci_evm_map_io,
-        .init_irq     = davinci_irq_init,
+        .init_irq     = dm644x_init_irq,
         .init_time      = dm644x_init_time,
         .init_machine = davinci_evm_init,
         .init_late      = davinci_init_late,
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 8d5be6dd2019..4600b617f9b4 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -22,7 +22,7 @@
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
-#include <linux/platform_data/at24.h>
+#include <linux/property.h>
 #include <linux/platform_data/pcf857x.h>
 #include <linux/platform_data/ti-aemif.h>
 
@@ -44,10 +44,10 @@
 #include <asm/mach/arch.h>
 
 #include <mach/common.h>
-#include <mach/irqs.h>
 #include <mach/serial.h>
 
 #include "davinci.h"
+#include "irqs.h"
 
 #define NAND_BLOCK_SIZE         SZ_128K
 
@@ -364,12 +364,9 @@ static struct nvmem_cell_lookup dm646x_evm_nvmem_cell_lookup = {
         .con_id         = "mac-address",
 };
 
-static struct at24_platform_data eeprom_info = {
-        .byte_len       = (256*1024) / 8,
-        .page_size      = 64,
-        .flags          = AT24_FLAG_ADDR16,
-        .setup          = davinci_get_mac_addr,
-        .context        = (void *)0x7f00,
+static const struct property_entry eeprom_properties[] = {
+        PROPERTY_ENTRY_U32("pagesize", 64),
+        { }
 };
 #endif
 
@@ -440,7 +437,7 @@ static void evm_init_cpld(void)
 static struct i2c_board_info __initdata i2c_info[] =  {
         {
                 I2C_BOARD_INFO("24c256", 0x50),
-                .platform_data  = &eeprom_info,
+                .properties  = eeprom_properties,
         },
         {
                 I2C_BOARD_INFO("pcf8574a", 0x38),
@@ -863,7 +860,7 @@ static __init void evm_init(void)
 MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
         .atag_offset  = 0x100,
         .map_io       = davinci_map_io,
-        .init_irq     = davinci_irq_init,
+        .init_irq     = dm646x_init_irq,
         .init_time      = dm646x_evm_init_time,
         .init_machine = evm_init,
         .init_late      = davinci_init_late,
@@ -873,7 +870,7 @@ MACHINE_END
 MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
         .atag_offset  = 0x100,
         .map_io       = davinci_map_io,
-        .init_irq     = davinci_irq_init,
+        .init_irq     = dm646x_init_irq,
         .init_time      = dm6467t_evm_init_time,
         .init_machine = evm_init,
         .init_late      = davinci_init_late,
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index 8df16e81b69e..dfce421c0579 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -14,11 +14,13 @@
 #include <linux/init.h>
 #include <linux/console.h>
 #include <linux/platform_device.h>
+#include <linux/property.h>
 #include <linux/mtd/partitions.h>
+#include <linux/notifier.h>
+#include <linux/nvmem-consumer.h>
 #include <linux/nvmem-provider.h>
 #include <linux/regulator/machine.h>
 #include <linux/i2c.h>
-#include <linux/platform_data/at24.h>
 #include <linux/etherdevice.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
@@ -27,7 +29,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/common.h>
-#include "cp_intc.h"
 #include <mach/da8xx.h>
 #include <linux/platform_data/mtd-davinci.h>
 #include <linux/platform_data/mtd-davinci-aemif.h>
@@ -117,11 +118,15 @@ static void mityomapl138_cpufreq_init(const char *partnum)
 static void mityomapl138_cpufreq_init(const char *partnum) { }
 #endif
 
-static void read_factory_config(struct nvmem_device *nvmem, void *context)
+static int read_factory_config(struct notifier_block *nb,
+                               unsigned long event, void *data)
 {
         int ret;
         const char *partnum = NULL;
-        struct davinci_soc_info *soc_info = &davinci_soc_info;
+        struct nvmem_device *nvmem = data;
+
+        if (strcmp(nvmem_dev_name(nvmem), "1-00500") != 0)
+                return NOTIFY_DONE;
 
         if (!IS_BUILTIN(CONFIG_NVMEM)) {
                 pr_warn("Factory Config not available without CONFIG_NVMEM\n");
@@ -147,21 +152,20 @@ static void read_factory_config(struct nvmem_device *nvmem, void *context)
                 goto bad_config;
         }
 
-        pr_info("Found MAC = %pM\n", factory_config.mac);
-        if (is_valid_ether_addr(factory_config.mac))
-                memcpy(soc_info->emac_pdata->mac_addr,
-                        factory_config.mac, ETH_ALEN);
-        else
-                pr_warn("Invalid MAC found in factory config block\n");
-
         partnum = factory_config.partnum;
         pr_info("Part Number = %s\n", partnum);
 
 bad_config:
         /* default maximum speed is valid for all platforms */
         mityomapl138_cpufreq_init(partnum);
+
+        return NOTIFY_STOP;
 }
 
+static struct notifier_block mityomapl138_nvmem_notifier = {
+        .notifier_call = read_factory_config,
+};
+
 /*
  * We don't define a cell for factory config as it will be accessed from the
  * board file using the nvmem notifier chain.
@@ -187,12 +191,10 @@ static struct nvmem_cell_lookup mityomapl138_nvmem_cell_lookup = {
         .con_id         = "mac-address",
 };
 
-static struct at24_platform_data mityomapl138_fd_chip = {
-        .byte_len       = 256,
-        .page_size      = 8,
-        .flags          = AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
-        .setup          = read_factory_config,
-        .context        = NULL,
+static const struct property_entry mityomapl138_fd_chip_properties[] = {
+        PROPERTY_ENTRY_U32("pagesize", 8),
+        PROPERTY_ENTRY_BOOL("read-only"),
+        { }
 };
 
 static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
@@ -321,7 +323,7 @@ static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
         },
         {
                 I2C_BOARD_INFO("24c02", 0x50),
-                .platform_data = &mityomapl138_fd_chip,
+                .properties = mityomapl138_fd_chip_properties,
         },
 };
 
@@ -569,6 +571,7 @@ static void __init mityomapl138_init(void)
 
         davinci_serial_init(da8xx_serial_device);
 
+        nvmem_register_notifier(&mityomapl138_nvmem_notifier);
         nvmem_add_cell_table(&mityomapl138_nvmem_cell_table);
         nvmem_add_cell_lookups(&mityomapl138_nvmem_cell_lookup, 1);
 
@@ -624,7 +627,7 @@ static void __init mityomapl138_map_io(void)
 MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
         .atag_offset    = 0x100,
         .map_io         = mityomapl138_map_io,
-        .init_irq       = cp_intc_init,
+        .init_irq       = da850_init_irq,
         .init_time      = da850_init_time,
         .init_machine   = mityomapl138_init,
         .init_late      = davinci_init_late,
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index efdaa27241c5..ce99f782811a 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -231,7 +231,7 @@ MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
         /* Maintainer: Neuros Technologies <neuros@groups.google.com> */
         .atag_offset    = 0x100,
         .map_io          = davinci_ntosd2_map_io,
-        .init_irq       = davinci_irq_init,
+        .init_irq       = dm644x_init_irq,
         .init_time      = dm644x_init_time,
         .init_machine = davinci_ntosd2_init,
         .init_late      = davinci_init_late,
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index 8e8d51f4a276..0896af2bed24 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -27,7 +27,6 @@
 #include <asm/mach/arch.h>
 
 #include <mach/common.h>
-#include "cp_intc.h"
 #include <mach/da8xx.h>
 #include <mach/mux.h>
 
@@ -134,9 +133,9 @@ static const short hawk_mmcsd0_pins[] = {
 static struct gpiod_lookup_table mmc_gpios_table = {
         .dev_id = "da830-mmc.0",
         .table = {
-                GPIO_LOOKUP("davinci_gpio.0", DA850_HAWK_MMCSD_CD_PIN, "cd",
+                GPIO_LOOKUP("davinci_gpio", DA850_HAWK_MMCSD_CD_PIN, "cd",
                             GPIO_ACTIVE_LOW),
-                GPIO_LOOKUP("davinci_gpio.0", DA850_HAWK_MMCSD_WP_PIN, "wp",
+                GPIO_LOOKUP("davinci_gpio", DA850_HAWK_MMCSD_WP_PIN, "wp",
                             GPIO_ACTIVE_LOW),
         },
 };
@@ -294,66 +293,24 @@ static int omapl138_hawk_register_aemif(void)
         return platform_device_register(&omapl138_hawk_aemif_device);
 }
 
-static irqreturn_t omapl138_hawk_usb_ocic_irq(int irq, void *dev_id);
-static da8xx_ocic_handler_t hawk_usb_ocic_handler;
-
 static const short da850_hawk_usb11_pins[] = {
         DA850_GPIO2_4, DA850_GPIO6_13,
         -1
 };
 
-static int hawk_usb_set_power(unsigned port, int on)
-{
-        gpio_set_value(DA850_USB1_VBUS_PIN, on);
-        return 0;
-}
-
-static int hawk_usb_get_power(unsigned port)
-{
-        return gpio_get_value(DA850_USB1_VBUS_PIN);
-}
-
-static int hawk_usb_get_oci(unsigned port)
-{
-        return !gpio_get_value(DA850_USB1_OC_PIN);
-}
-
-static int hawk_usb_ocic_notify(da8xx_ocic_handler_t handler)
-{
-        int irq         = gpio_to_irq(DA850_USB1_OC_PIN);
-        int error       = 0;
-
-        if (handler != NULL) {
-                hawk_usb_ocic_handler = handler;
-
-                error = request_irq(irq, omapl138_hawk_usb_ocic_irq,
-                                        IRQF_TRIGGER_RISING |
-                                        IRQF_TRIGGER_FALLING,
-                                        "OHCI over-current indicator", NULL);
-                if (error)
-                        pr_err("%s: could not request IRQ to watch "
-                                "over-current indicator changes\n", __func__);
-        } else {
-                free_irq(irq, NULL);
-        }
-        return error;
-}
+static struct gpiod_lookup_table hawk_usb_gpio_lookup = {
+        .dev_id         = "ohci-da8xx",
+        .table = {
+                GPIO_LOOKUP("davinci_gpio", DA850_USB1_VBUS_PIN, "vbus", 0),
+                GPIO_LOOKUP("davinci_gpio", DA850_USB1_OC_PIN, "oc", 0),
+        },
+};
 
 static struct da8xx_ohci_root_hub omapl138_hawk_usb11_pdata = {
-        .set_power      = hawk_usb_set_power,
-        .get_power      = hawk_usb_get_power,
-        .get_oci        = hawk_usb_get_oci,
-        .ocic_notify    = hawk_usb_ocic_notify,
         /* TPS2087 switch @ 5V */
         .potpgt         = (3 + 1) / 2,  /* 3 ms max */
 };
 
-static irqreturn_t omapl138_hawk_usb_ocic_irq(int irq, void *dev_id)
-{
-        hawk_usb_ocic_handler(&omapl138_hawk_usb11_pdata, 1);
-        return IRQ_HANDLED;
-}
-
 static __init void omapl138_hawk_usb_init(void)
 {
         int ret;
@@ -374,34 +331,13 @@ static __init void omapl138_hawk_usb_init(void)
                 pr_warn("%s: USB PHY registration failed: %d\n",
                         __func__, ret);
 
-        ret = gpio_request_one(DA850_USB1_VBUS_PIN,
-                        GPIOF_DIR_OUT, "USB1 VBUS");
-        if (ret < 0) {
-                pr_err("%s: failed to request GPIO for USB 1.1 port "
-                        "power control: %d\n", __func__, ret);
-                return;
-        }
-
-        ret = gpio_request_one(DA850_USB1_OC_PIN,
-                        GPIOF_DIR_IN, "USB1 OC");
-        if (ret < 0) {
-                pr_err("%s: failed to request GPIO for USB 1.1 port "
-                        "over-current indicator: %d\n", __func__, ret);
-                goto usb11_setup_oc_fail;
-        }
+        gpiod_add_lookup_table(&hawk_usb_gpio_lookup);
 
         ret = da8xx_register_usb11(&omapl138_hawk_usb11_pdata);
-        if (ret) {
+        if (ret)
                 pr_warn("%s: USB 1.1 registration failed: %d\n", __func__, ret);
-                goto usb11_setup_fail;
-        }
 
         return;
-
-usb11_setup_fail:
-        gpio_free(DA850_USB1_OC_PIN);
-usb11_setup_oc_fail:
-        gpio_free(DA850_USB1_VBUS_PIN);
 }
 
 static __init void omapl138_hawk_init(void)
@@ -462,7 +398,7 @@ static void __init omapl138_hawk_map_io(void)
 MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard")
         .atag_offset    = 0x100,
         .map_io         = omapl138_hawk_map_io,
-        .init_irq       = cp_intc_init,
+        .init_irq       = da850_init_irq,
         .init_time      = da850_init_time,
         .init_machine   = omapl138_hawk_init,
         .init_late      = davinci_init_late,
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 792bb84d5011..bcdefde2f401 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -26,7 +26,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
-#include <linux/platform_data/at24.h>
+#include <linux/property.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/rawnand.h>
 #include <linux/mtd/partitions.h>
@@ -92,16 +92,15 @@ static struct platform_device davinci_sffsdr_nandflash_device = {
         .resource       = davinci_sffsdr_nandflash_resource,
 };
 
-static struct at24_platform_data eeprom_info = {
-        .byte_len       = (64*1024) / 8,
-        .page_size      = 32,
-        .flags          = AT24_FLAG_ADDR16,
+static const struct property_entry eeprom_properties[] = {
+        PROPERTY_ENTRY_U32("pagesize", 32),
+        { }
 };
 
 static struct i2c_board_info __initdata i2c_info[] =  {
         {
-                I2C_BOARD_INFO("24lc64", 0x50),
-                .platform_data  = &eeprom_info,
+                I2C_BOARD_INFO("24c64", 0x50),
+                .properties = eeprom_properties,
         },
         /* Other I2C devices:
          * MSP430,  addr 0x23 (not used)
@@ -153,7 +152,7 @@ static __init void davinci_sffsdr_init(void)
 MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
         .atag_offset  = 0x100,
         .map_io       = davinci_sffsdr_map_io,
-        .init_irq     = davinci_irq_init,
+        .init_irq     = dm644x_init_irq,
         .init_time      = dm644x_init_time,
         .init_machine = davinci_sffsdr_init,
         .init_late      = davinci_init_late,
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index e1d0f0d841ff..ae61d19f9b3a 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -23,24 +23,6 @@
 struct davinci_soc_info davinci_soc_info;
 EXPORT_SYMBOL(davinci_soc_info);
 
-void __iomem *davinci_intc_base;
-int davinci_intc_type;
-
-void davinci_get_mac_addr(struct nvmem_device *nvmem, void *context)
-{
-        char *mac_addr = davinci_soc_info.emac_pdata->mac_addr;
-        off_t offset = (off_t)context;
-
-        if (!IS_BUILTIN(CONFIG_NVMEM)) {
-                pr_warn("Cannot read MAC addr from EEPROM without CONFIG_NVMEM\n");
-                return;
-        }
-
-        /* Read MAC addr from EEPROM */
-        if (nvmem_device_read(nvmem, offset, ETH_ALEN, mac_addr) == ETH_ALEN)
-                pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr);
-}
-
 static int __init davinci_init_id(struct davinci_soc_info *soc_info)
 {
         int                     i;
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
deleted file mode 100644
index 94085d21018e..000000000000
--- a/arch/arm/mach-davinci/cp_intc.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * TI Common Platform Interrupt Controller (cp_intc) driver
- *
- * Author: Steve Chen <schen@mvista.com>
- * Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/irqchip.h>
-#include <linux/irqdomain.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-
-#include <mach/common.h>
-#include "cp_intc.h"
-
-static inline unsigned int cp_intc_read(unsigned offset)
-{
-        return __raw_readl(davinci_intc_base + offset);
-}
-
-static inline void cp_intc_write(unsigned long value, unsigned offset)
-{
-        __raw_writel(value, davinci_intc_base + offset);
-}
-
-static void cp_intc_ack_irq(struct irq_data *d)
-{
-        cp_intc_write(d->hwirq, CP_INTC_SYS_STAT_IDX_CLR);
-}
-
-/* Disable interrupt */
-static void cp_intc_mask_irq(struct irq_data *d)
-{
-        /* XXX don't know why we need to disable nIRQ here... */
-        cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR);
-        cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_CLR);
-        cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
-}
-
-/* Enable interrupt */
-static void cp_intc_unmask_irq(struct irq_data *d)
-{
-        cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_SET);
-}
-
-static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type)
-{
-        unsigned reg            = BIT_WORD(d->hwirq);
-        unsigned mask           = BIT_MASK(d->hwirq);
-        unsigned polarity       = cp_intc_read(CP_INTC_SYS_POLARITY(reg));
-        unsigned type           = cp_intc_read(CP_INTC_SYS_TYPE(reg));
-
-        switch (flow_type) {
-        case IRQ_TYPE_EDGE_RISING:
-                polarity |= mask;
-                type |= mask;
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                polarity &= ~mask;
-                type |= mask;
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                polarity |= mask;
-                type &= ~mask;
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                polarity &= ~mask;
-                type &= ~mask;
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        cp_intc_write(polarity, CP_INTC_SYS_POLARITY(reg));
-        cp_intc_write(type, CP_INTC_SYS_TYPE(reg));
-
-        return 0;
-}
-
-static struct irq_chip cp_intc_irq_chip = {
-        .name           = "cp_intc",
-        .irq_ack        = cp_intc_ack_irq,
-        .irq_mask       = cp_intc_mask_irq,
-        .irq_unmask     = cp_intc_unmask_irq,
-        .irq_set_type   = cp_intc_set_irq_type,
-        .flags          = IRQCHIP_SKIP_SET_WAKE,
-};
-
-static struct irq_domain *cp_intc_domain;
-
-static int cp_intc_host_map(struct irq_domain *h, unsigned int virq,
-                          irq_hw_number_t hw)
-{
-        pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
-
-        irq_set_chip(virq, &cp_intc_irq_chip);
-        irq_set_probe(virq);
-        irq_set_handler(virq, handle_edge_irq);
-        return 0;
-}
-
-static const struct irq_domain_ops cp_intc_host_ops = {
-        .map = cp_intc_host_map,
-        .xlate = irq_domain_xlate_onetwocell,
-};
-
-int __init cp_intc_of_init(struct device_node *node, struct device_node *parent)
-{
-        u32 num_irq             = davinci_soc_info.intc_irq_num;
-        u8 *irq_prio            = davinci_soc_info.intc_irq_prios;
-        u32 *host_map           = davinci_soc_info.intc_host_map;
-        unsigned num_reg        = BITS_TO_LONGS(num_irq);
-        int i, irq_base;
-
-        davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC;
-        if (node) {
-                davinci_intc_base = of_iomap(node, 0);
-                if (of_property_read_u32(node, "ti,intc-size", &num_irq))
-                        pr_warn("unable to get intc-size, default to %d\n",
-                                num_irq);
-        } else {
-                davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
-        }
-        if (WARN_ON(!davinci_intc_base))
-                return -EINVAL;
-
-        cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
-
-        /* Disable all host interrupts */
-        cp_intc_write(0, CP_INTC_HOST_ENABLE(0));
-
-        /* Disable system interrupts */
-        for (i = 0; i < num_reg; i++)
-                cp_intc_write(~0, CP_INTC_SYS_ENABLE_CLR(i));
-
-        /* Set to normal mode, no nesting, no priority hold */
-        cp_intc_write(0, CP_INTC_CTRL);
-        cp_intc_write(0, CP_INTC_HOST_CTRL);
-
-        /* Clear system interrupt status */
-        for (i = 0; i < num_reg; i++)
-                cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i));
-
-        /* Enable nIRQ (what about nFIQ?) */
-        cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
-
-        /*
-         * Priority is determined by host channel: lower channel number has
-         * higher priority i.e. channel 0 has highest priority and channel 31
-         * had the lowest priority.
-         */
-        num_reg = (num_irq + 3) >> 2;   /* 4 channels per register */
-        if (irq_prio) {
-                unsigned j, k;
-                u32 val;
-
-                for (k = i = 0; i < num_reg; i++) {
-                        for (val = j = 0; j < 4; j++, k++) {
-                                val >>= 8;
-                                if (k < num_irq)
-                                        val |= irq_prio[k] << 24;
-                        }
-
-                        cp_intc_write(val, CP_INTC_CHAN_MAP(i));
-                }
-        } else  {
-                /*
-                 * Default everything to channel 15 if priority not specified.
-                 * Note that channel 0-1 are mapped to nFIQ and channels 2-31
-                 * are mapped to nIRQ.
-                 */
-                for (i = 0; i < num_reg; i++)
-                        cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i));
-        }
-
-        if (host_map)
-                for (i = 0; host_map[i] != -1; i++)
-                        cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i));
-
-        irq_base = irq_alloc_descs(-1, 0, num_irq, 0);
-        if (irq_base < 0) {
-                pr_warn("Couldn't allocate IRQ numbers\n");
-                irq_base = 0;
-        }
-
-        /* create a legacy host */
-        cp_intc_domain = irq_domain_add_legacy(node, num_irq,
-                                        irq_base, 0, &cp_intc_host_ops, NULL);
-
-        if (!cp_intc_domain) {
-                pr_err("cp_intc: failed to allocate irq host!\n");
-                return -EINVAL;
-        }
-
-        /* Enable global interrupt */
-        cp_intc_write(1, CP_INTC_GLOBAL_ENABLE);
-
-        return 0;
-}
-
-void __init cp_intc_init(void)
-{
-        cp_intc_of_init(NULL, NULL);
-}
-
-IRQCHIP_DECLARE(cp_intc, "ti,cp-intc", cp_intc_of_init);
diff --git a/arch/arm/mach-davinci/cp_intc.h b/arch/arm/mach-davinci/cp_intc.h
deleted file mode 100644
index 827bbe9baed4..000000000000
--- a/arch/arm/mach-davinci/cp_intc.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * TI Common Platform Interrupt Controller (cp_intc) definitions
- *
- * Author: Steve Chen <schen@mvista.com>
- * Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-#ifndef __ASM_HARDWARE_CP_INTC_H
-#define __ASM_HARDWARE_CP_INTC_H
-
-#define CP_INTC_REV                     0x00
-#define CP_INTC_CTRL                    0x04
-#define CP_INTC_HOST_CTRL               0x0C
-#define CP_INTC_GLOBAL_ENABLE           0x10
-#define CP_INTC_GLOBAL_NESTING_LEVEL    0x1C
-#define CP_INTC_SYS_STAT_IDX_SET        0x20
-#define CP_INTC_SYS_STAT_IDX_CLR        0x24
-#define CP_INTC_SYS_ENABLE_IDX_SET      0x28
-#define CP_INTC_SYS_ENABLE_IDX_CLR      0x2C
-#define CP_INTC_GLOBAL_WAKEUP_ENABLE    0x30
-#define CP_INTC_HOST_ENABLE_IDX_SET     0x34
-#define CP_INTC_HOST_ENABLE_IDX_CLR     0x38
-#define CP_INTC_PACING_PRESCALE         0x40
-#define CP_INTC_VECTOR_BASE             0x50
-#define CP_INTC_VECTOR_SIZE             0x54
-#define CP_INTC_VECTOR_NULL             0x58
-#define CP_INTC_PRIO_IDX                0x80
-#define CP_INTC_PRIO_VECTOR             0x84
-#define CP_INTC_SECURE_ENABLE           0x90
-#define CP_INTC_SECURE_PRIO_IDX         0x94
-#define CP_INTC_PACING_PARAM(n)         (0x0100 + (n << 4))
-#define CP_INTC_PACING_DEC(n)           (0x0104 + (n << 4))
-#define CP_INTC_PACING_MAP(n)           (0x0108 + (n << 4))
-#define CP_INTC_SYS_RAW_STAT(n)         (0x0200 + (n << 2))
-#define CP_INTC_SYS_STAT_CLR(n)         (0x0280 + (n << 2))
-#define CP_INTC_SYS_ENABLE_SET(n)       (0x0300 + (n << 2))
-#define CP_INTC_SYS_ENABLE_CLR(n)       (0x0380 + (n << 2))
-#define CP_INTC_CHAN_MAP(n)             (0x0400 + (n << 2))
-#define CP_INTC_HOST_MAP(n)             (0x0800 + (n << 2))
-#define CP_INTC_HOST_PRIO_IDX(n)        (0x0900 + (n << 2))
-#define CP_INTC_SYS_POLARITY(n)         (0x0D00 + (n << 2))
-#define CP_INTC_SYS_TYPE(n)             (0x0D80 + (n << 2))
-#define CP_INTC_WAKEUP_ENABLE(n)        (0x0E00 + (n << 2))
-#define CP_INTC_DEBUG_SELECT(n)         (0x0F00 + (n << 2))
-#define CP_INTC_SYS_SECURE_ENABLE(n)    (0x1000 + (n << 2))
-#define CP_INTC_HOST_NESTING_LEVEL(n)   (0x1100 + (n << 2))
-#define CP_INTC_HOST_ENABLE(n)          (0x1500 + (n << 2))
-#define CP_INTC_HOST_PRIO_VECTOR(n)     (0x1600 + (n << 2))
-#define CP_INTC_VECTOR_ADDR(n)          (0x2000 + (n << 2))
-
-void cp_intc_init(void);
-int cp_intc_of_init(struct device_node *, struct device_node *);
-
-#endif  /* __ASM_HARDWARE_CP_INTC_H */
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 2cc9fe4c3a91..63511f638ce4 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -12,6 +12,7 @@
 #include <linux/clk/davinci.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
+#include <linux/irqchip/irq-davinci-cp-intc.h>
 #include <linux/platform_data/gpio-davinci.h>
 
 #include <asm/mach/map.h>
@@ -19,9 +20,9 @@
 #include <mach/common.h>
 #include <mach/cputype.h>
 #include <mach/da8xx.h>
-#include <mach/irqs.h>
 #include <mach/time.h>
 
+#include "irqs.h"
 #include "mux.h"
 
 /* Offsets of the 8 compare registers on the da830 */
@@ -623,101 +624,6 @@ const short da830_eqep1_pins[] __initconst = {
         -1
 };
 
-/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
-static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = {
-        [IRQ_DA8XX_COMMTX]              = 7,
-        [IRQ_DA8XX_COMMRX]              = 7,
-        [IRQ_DA8XX_NINT]                = 7,
-        [IRQ_DA8XX_EVTOUT0]             = 7,
-        [IRQ_DA8XX_EVTOUT1]             = 7,
-        [IRQ_DA8XX_EVTOUT2]             = 7,
-        [IRQ_DA8XX_EVTOUT3]             = 7,
-        [IRQ_DA8XX_EVTOUT4]             = 7,
-        [IRQ_DA8XX_EVTOUT5]             = 7,
-        [IRQ_DA8XX_EVTOUT6]             = 7,
-        [IRQ_DA8XX_EVTOUT7]             = 7,
-        [IRQ_DA8XX_CCINT0]              = 7,
-        [IRQ_DA8XX_CCERRINT]            = 7,
-        [IRQ_DA8XX_TCERRINT0]           = 7,
-        [IRQ_DA8XX_AEMIFINT]            = 7,
-        [IRQ_DA8XX_I2CINT0]             = 7,
-        [IRQ_DA8XX_MMCSDINT0]           = 7,
-        [IRQ_DA8XX_MMCSDINT1]           = 7,
-        [IRQ_DA8XX_ALLINT0]             = 7,
-        [IRQ_DA8XX_RTC]                 = 7,
-        [IRQ_DA8XX_SPINT0]              = 7,
-        [IRQ_DA8XX_TINT12_0]            = 7,
-        [IRQ_DA8XX_TINT34_0]            = 7,
-        [IRQ_DA8XX_TINT12_1]            = 7,
-        [IRQ_DA8XX_TINT34_1]            = 7,
-        [IRQ_DA8XX_UARTINT0]            = 7,
-        [IRQ_DA8XX_KEYMGRINT]           = 7,
-        [IRQ_DA830_MPUERR]              = 7,
-        [IRQ_DA8XX_CHIPINT0]            = 7,
-        [IRQ_DA8XX_CHIPINT1]            = 7,
-        [IRQ_DA8XX_CHIPINT2]            = 7,
-        [IRQ_DA8XX_CHIPINT3]            = 7,
-        [IRQ_DA8XX_TCERRINT1]           = 7,
-        [IRQ_DA8XX_C0_RX_THRESH_PULSE]  = 7,
-        [IRQ_DA8XX_C0_RX_PULSE]         = 7,
-        [IRQ_DA8XX_C0_TX_PULSE]         = 7,
-        [IRQ_DA8XX_C0_MISC_PULSE]       = 7,
-        [IRQ_DA8XX_C1_RX_THRESH_PULSE]  = 7,
-        [IRQ_DA8XX_C1_RX_PULSE]         = 7,
-        [IRQ_DA8XX_C1_TX_PULSE]         = 7,
-        [IRQ_DA8XX_C1_MISC_PULSE]       = 7,
-        [IRQ_DA8XX_MEMERR]              = 7,
-        [IRQ_DA8XX_GPIO0]               = 7,
-        [IRQ_DA8XX_GPIO1]               = 7,
-        [IRQ_DA8XX_GPIO2]               = 7,
-        [IRQ_DA8XX_GPIO3]               = 7,
-        [IRQ_DA8XX_GPIO4]               = 7,
-        [IRQ_DA8XX_GPIO5]               = 7,
-        [IRQ_DA8XX_GPIO6]               = 7,
-        [IRQ_DA8XX_GPIO7]               = 7,
-        [IRQ_DA8XX_GPIO8]               = 7,
-        [IRQ_DA8XX_I2CINT1]             = 7,
-        [IRQ_DA8XX_LCDINT]              = 7,
-        [IRQ_DA8XX_UARTINT1]            = 7,
-        [IRQ_DA8XX_MCASPINT]            = 7,
-        [IRQ_DA8XX_ALLINT1]             = 7,
-        [IRQ_DA8XX_SPINT1]              = 7,
-        [IRQ_DA8XX_UHPI_INT1]           = 7,
-        [IRQ_DA8XX_USB_INT]             = 7,
-        [IRQ_DA8XX_IRQN]                = 7,
-        [IRQ_DA8XX_RWAKEUP]             = 7,
-        [IRQ_DA8XX_UARTINT2]            = 7,
-        [IRQ_DA8XX_DFTSSINT]            = 7,
-        [IRQ_DA8XX_EHRPWM0]             = 7,
-        [IRQ_DA8XX_EHRPWM0TZ]           = 7,
-        [IRQ_DA8XX_EHRPWM1]             = 7,
-        [IRQ_DA8XX_EHRPWM1TZ]           = 7,
-        [IRQ_DA830_EHRPWM2]             = 7,
-        [IRQ_DA830_EHRPWM2TZ]           = 7,
-        [IRQ_DA8XX_ECAP0]               = 7,
-        [IRQ_DA8XX_ECAP1]               = 7,
-        [IRQ_DA8XX_ECAP2]               = 7,
-        [IRQ_DA830_EQEP0]               = 7,
-        [IRQ_DA830_EQEP1]               = 7,
-        [IRQ_DA830_T12CMPINT0_0]        = 7,
-        [IRQ_DA830_T12CMPINT1_0]        = 7,
-        [IRQ_DA830_T12CMPINT2_0]        = 7,
-        [IRQ_DA830_T12CMPINT3_0]        = 7,
-        [IRQ_DA830_T12CMPINT4_0]        = 7,
-        [IRQ_DA830_T12CMPINT5_0]        = 7,
-        [IRQ_DA830_T12CMPINT6_0]        = 7,
-        [IRQ_DA830_T12CMPINT7_0]        = 7,
-        [IRQ_DA830_T12CMPINT0_1]        = 7,
-        [IRQ_DA830_T12CMPINT1_1]        = 7,
-        [IRQ_DA830_T12CMPINT2_1]        = 7,
-        [IRQ_DA830_T12CMPINT3_1]        = 7,
-        [IRQ_DA830_T12CMPINT4_1]        = 7,
-        [IRQ_DA830_T12CMPINT5_1]        = 7,
-        [IRQ_DA830_T12CMPINT6_1]        = 7,
-        [IRQ_DA830_T12CMPINT7_1]        = 7,
-        [IRQ_DA8XX_ARMCLKSTOPREQ]       = 7,
-};
-
 static struct map_desc da830_io_desc[] = {
         {
                 .virtual        = IO_VIRT,
@@ -772,17 +678,17 @@ int __init da830_register_gpio(void)
 static struct davinci_timer_instance da830_timer_instance[2] = {
         {
                 .base           = DA8XX_TIMER64P0_BASE,
-                .bottom_irq     = IRQ_DA8XX_TINT12_0,
-                .top_irq        = IRQ_DA8XX_TINT34_0,
+                .bottom_irq     = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0),
+                .top_irq        = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0),
                 .cmp_off        = DA830_CMP12_0,
-                .cmp_irq        = IRQ_DA830_T12CMPINT0_0,
+                .cmp_irq        = DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_0),
         },
         {
                 .base           = DA8XX_TIMER64P1_BASE,
-                .bottom_irq     = IRQ_DA8XX_TINT12_1,
-                .top_irq        = IRQ_DA8XX_TINT34_1,
+                .bottom_irq     = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_1),
+                .top_irq        = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_1),
                 .cmp_off        = DA830_CMP12_0,
-                .cmp_irq        = IRQ_DA830_T12CMPINT0_1,
+                .cmp_irq        = DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_1),
         },
 };
 
@@ -806,10 +712,6 @@ static const struct davinci_soc_info davinci_soc_info_da830 = {
         .pinmux_base            = DA8XX_SYSCFG0_BASE + 0x120,
         .pinmux_pins            = da830_pins,
         .pinmux_pins_num        = ARRAY_SIZE(da830_pins),
-        .intc_base              = DA8XX_CP_INTC_BASE,
-        .intc_type              = DAVINCI_INTC_TYPE_CP_INTC,
-        .intc_irq_prios         = da830_default_priorities,
-        .intc_irq_num           = DA830_N_CP_INTC_IRQ,
         .timer_info             = &da830_timer_info,
         .emac_pdata             = &da8xx_emac_pdata,
 };
@@ -822,6 +724,20 @@ void __init da830_init(void)
         WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module");
 }
 
+static const struct davinci_cp_intc_config da830_cp_intc_config = {
+        .reg = {
+                .start          = DA8XX_CP_INTC_BASE,
+                .end            = DA8XX_CP_INTC_BASE + SZ_8K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        .num_irqs               = DA830_N_CP_INTC_IRQ,
+};
+
+void __init da830_init_irq(void)
+{
+        davinci_cp_intc_init(&da830_cp_intc_config);
+}
+
 void __init da830_init_time(void)
 {
         void __iomem *pll;
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index e7b78df2bfef..67ab71ba3ad3 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -18,9 +18,11 @@
 #include <linux/cpufreq.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
+#include <linux/irqchip/irq-davinci-cp-intc.h>
 #include <linux/mfd/da8xx-cfgchip.h>
 #include <linux/platform_data/clk-da8xx-cfgchip.h>
 #include <linux/platform_data/clk-davinci-pll.h>
+#include <linux/platform_data/davinci-cpufreq.h>
 #include <linux/platform_data/gpio-davinci.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
@@ -29,13 +31,12 @@
 #include <asm/mach/map.h>
 
 #include <mach/common.h>
-#include <mach/cpufreq.h>
 #include <mach/cputype.h>
 #include <mach/da8xx.h>
-#include <mach/irqs.h>
 #include <mach/pm.h>
 #include <mach/time.h>
 
+#include "irqs.h"
 #include "mux.h"
 
 #define DA850_PLL1_BASE         0x01e1a000
@@ -298,111 +299,6 @@ const short da850_vpif_display_pins[] __initconst = {
         -1
 };
 
-/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
-static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
-        [IRQ_DA8XX_COMMTX]              = 7,
-        [IRQ_DA8XX_COMMRX]              = 7,
-        [IRQ_DA8XX_NINT]                = 7,
-        [IRQ_DA8XX_EVTOUT0]             = 7,
-        [IRQ_DA8XX_EVTOUT1]             = 7,
-        [IRQ_DA8XX_EVTOUT2]             = 7,
-        [IRQ_DA8XX_EVTOUT3]             = 7,
-        [IRQ_DA8XX_EVTOUT4]             = 7,
-        [IRQ_DA8XX_EVTOUT5]             = 7,
-        [IRQ_DA8XX_EVTOUT6]             = 7,
-        [IRQ_DA8XX_EVTOUT7]             = 7,
-        [IRQ_DA8XX_CCINT0]              = 7,
-        [IRQ_DA8XX_CCERRINT]            = 7,
-        [IRQ_DA8XX_TCERRINT0]           = 7,
-        [IRQ_DA8XX_AEMIFINT]            = 7,
-        [IRQ_DA8XX_I2CINT0]             = 7,
-        [IRQ_DA8XX_MMCSDINT0]           = 7,
-        [IRQ_DA8XX_MMCSDINT1]           = 7,
-        [IRQ_DA8XX_ALLINT0]             = 7,
-        [IRQ_DA8XX_RTC]                 = 7,
-        [IRQ_DA8XX_SPINT0]              = 7,
-        [IRQ_DA8XX_TINT12_0]            = 7,
-        [IRQ_DA8XX_TINT34_0]            = 7,
-        [IRQ_DA8XX_TINT12_1]            = 7,
-        [IRQ_DA8XX_TINT34_1]            = 7,
-        [IRQ_DA8XX_UARTINT0]            = 7,
-        [IRQ_DA8XX_KEYMGRINT]           = 7,
-        [IRQ_DA850_MPUADDRERR0]         = 7,
-        [IRQ_DA8XX_CHIPINT0]            = 7,
-        [IRQ_DA8XX_CHIPINT1]            = 7,
-        [IRQ_DA8XX_CHIPINT2]            = 7,
-        [IRQ_DA8XX_CHIPINT3]            = 7,
-        [IRQ_DA8XX_TCERRINT1]           = 7,
-        [IRQ_DA8XX_C0_RX_THRESH_PULSE]  = 7,
-        [IRQ_DA8XX_C0_RX_PULSE]         = 7,
-        [IRQ_DA8XX_C0_TX_PULSE]         = 7,
-        [IRQ_DA8XX_C0_MISC_PULSE]       = 7,
-        [IRQ_DA8XX_C1_RX_THRESH_PULSE]  = 7,
-        [IRQ_DA8XX_C1_RX_PULSE]         = 7,
-        [IRQ_DA8XX_C1_TX_PULSE]         = 7,
-        [IRQ_DA8XX_C1_MISC_PULSE]       = 7,
-        [IRQ_DA8XX_MEMERR]              = 7,
-        [IRQ_DA8XX_GPIO0]               = 7,
-        [IRQ_DA8XX_GPIO1]               = 7,
-        [IRQ_DA8XX_GPIO2]               = 7,
-        [IRQ_DA8XX_GPIO3]               = 7,
-        [IRQ_DA8XX_GPIO4]               = 7,
-        [IRQ_DA8XX_GPIO5]               = 7,
-        [IRQ_DA8XX_GPIO6]               = 7,
-        [IRQ_DA8XX_GPIO7]               = 7,
-        [IRQ_DA8XX_GPIO8]               = 7,
-        [IRQ_DA8XX_I2CINT1]             = 7,
-        [IRQ_DA8XX_LCDINT]              = 7,
-        [IRQ_DA8XX_UARTINT1]            = 7,
-        [IRQ_DA8XX_MCASPINT]            = 7,
-        [IRQ_DA8XX_ALLINT1]             = 7,
-        [IRQ_DA8XX_SPINT1]              = 7,
-        [IRQ_DA8XX_UHPI_INT1]           = 7,
-        [IRQ_DA8XX_USB_INT]             = 7,
-        [IRQ_DA8XX_IRQN]                = 7,
-        [IRQ_DA8XX_RWAKEUP]             = 7,
-        [IRQ_DA8XX_UARTINT2]            = 7,
-        [IRQ_DA8XX_DFTSSINT]            = 7,
-        [IRQ_DA8XX_EHRPWM0]             = 7,
-        [IRQ_DA8XX_EHRPWM0TZ]           = 7,
-        [IRQ_DA8XX_EHRPWM1]             = 7,
-        [IRQ_DA8XX_EHRPWM1TZ]           = 7,
-        [IRQ_DA850_SATAINT]             = 7,
-        [IRQ_DA850_TINTALL_2]           = 7,
-        [IRQ_DA8XX_ECAP0]               = 7,
-        [IRQ_DA8XX_ECAP1]               = 7,
-        [IRQ_DA8XX_ECAP2]               = 7,
-        [IRQ_DA850_MMCSDINT0_1]         = 7,
-        [IRQ_DA850_MMCSDINT1_1]         = 7,
-        [IRQ_DA850_T12CMPINT0_2]        = 7,
-        [IRQ_DA850_T12CMPINT1_2]        = 7,
-        [IRQ_DA850_T12CMPINT2_2]        = 7,
-        [IRQ_DA850_T12CMPINT3_2]        = 7,
-        [IRQ_DA850_T12CMPINT4_2]        = 7,
-        [IRQ_DA850_T12CMPINT5_2]        = 7,
-        [IRQ_DA850_T12CMPINT6_2]        = 7,
-        [IRQ_DA850_T12CMPINT7_2]        = 7,
-        [IRQ_DA850_T12CMPINT0_3]        = 7,
-        [IRQ_DA850_T12CMPINT1_3]        = 7,
-        [IRQ_DA850_T12CMPINT2_3]        = 7,
-        [IRQ_DA850_T12CMPINT3_3]        = 7,
-        [IRQ_DA850_T12CMPINT4_3]        = 7,
-        [IRQ_DA850_T12CMPINT5_3]        = 7,
-        [IRQ_DA850_T12CMPINT6_3]        = 7,
-        [IRQ_DA850_T12CMPINT7_3]        = 7,
-        [IRQ_DA850_RPIINT]              = 7,
-        [IRQ_DA850_VPIFINT]             = 7,
-        [IRQ_DA850_CCINT1]              = 7,
-        [IRQ_DA850_CCERRINT1]           = 7,
-        [IRQ_DA850_TCERRINT2]           = 7,
-        [IRQ_DA850_TINTALL_3]           = 7,
-        [IRQ_DA850_MCBSP0RINT]          = 7,
-        [IRQ_DA850_MCBSP0XINT]          = 7,
-        [IRQ_DA850_MCBSP1RINT]          = 7,
-        [IRQ_DA850_MCBSP1XINT]          = 7,
-        [IRQ_DA8XX_ARMCLKSTOPREQ]       = 7,
-};
-
 static struct map_desc da850_io_desc[] = {
         {
                 .virtual        = IO_VIRT,
@@ -439,23 +335,23 @@ static struct davinci_id da850_ids[] = {
 static struct davinci_timer_instance da850_timer_instance[4] = {
         {
                 .base           = DA8XX_TIMER64P0_BASE,
-                .bottom_irq     = IRQ_DA8XX_TINT12_0,
-                .top_irq        = IRQ_DA8XX_TINT34_0,
+                .bottom_irq     = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0),
+                .top_irq        = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0),
         },
         {
                 .base           = DA8XX_TIMER64P1_BASE,
-                .bottom_irq     = IRQ_DA8XX_TINT12_1,
-                .top_irq        = IRQ_DA8XX_TINT34_1,
+                .bottom_irq     = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_1),
+                .top_irq        = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_1),
         },
         {
                 .base           = DA850_TIMER64P2_BASE,
-                .bottom_irq     = IRQ_DA850_TINT12_2,
-                .top_irq        = IRQ_DA850_TINT34_2,
+                .bottom_irq     = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_2),
+                .top_irq        = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_2),
         },
         {
                 .base           = DA850_TIMER64P3_BASE,
-                .bottom_irq     = IRQ_DA850_TINT12_3,
-                .top_irq        = IRQ_DA850_TINT34_3,
+                .bottom_irq     = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_3),
+                .top_irq        = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_3),
         },
 };
 
@@ -658,8 +554,8 @@ static struct platform_device da850_vpif_dev = {
 
 static struct resource da850_vpif_display_resource[] = {
         {
-                .start = IRQ_DA850_VPIFINT,
-                .end   = IRQ_DA850_VPIFINT,
+                .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
+                .end   = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
                 .flags = IORESOURCE_IRQ,
         },
 };
@@ -677,13 +573,13 @@ static struct platform_device da850_vpif_display_dev = {
 
 static struct resource da850_vpif_capture_resource[] = {
         {
-                .start = IRQ_DA850_VPIFINT,
-                .end   = IRQ_DA850_VPIFINT,
+                .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
+                .end   = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
                 .flags = IORESOURCE_IRQ,
         },
         {
-                .start = IRQ_DA850_VPIFINT,
-                .end   = IRQ_DA850_VPIFINT,
+                .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
+                .end   = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
                 .flags = IORESOURCE_IRQ,
         },
 };
@@ -738,10 +634,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = {
         .pinmux_base            = DA8XX_SYSCFG0_BASE + 0x120,
         .pinmux_pins            = da850_pins,
         .pinmux_pins_num        = ARRAY_SIZE(da850_pins),
-        .intc_base              = DA8XX_CP_INTC_BASE,
-        .intc_type              = DAVINCI_INTC_TYPE_CP_INTC,
-        .intc_irq_prios         = da850_default_priorities,
-        .intc_irq_num           = DA850_N_CP_INTC_IRQ,
         .timer_info             = &da850_timer_info,
         .emac_pdata             = &da8xx_emac_pdata,
         .sram_dma               = DA8XX_SHARED_RAM_BASE,
@@ -760,6 +652,20 @@ void __init da850_init(void)
         WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module");
 }
 
+static const struct davinci_cp_intc_config da850_cp_intc_config = {
+        .reg = {
+                .start          = DA8XX_CP_INTC_BASE,
+                .end            = DA8XX_CP_INTC_BASE + SZ_8K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        .num_irqs               = DA850_N_CP_INTC_IRQ,
+};
+
+void __init da850_init_irq(void)
+{
+        davinci_cp_intc_init(&da850_cp_intc_config);
+}
+
 void __init da850_init_time(void)
 {
         void __iomem *pll0;
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index db4c95ef4d5c..56c1835c42e5 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -88,6 +88,7 @@ int davinci_init_wdt(void);
 /* DM355 function declarations */
 void dm355_init(void);
 void dm355_init_time(void);
+void dm355_init_irq(void);
 void dm355_register_clocks(void);
 void dm355_init_spi0(unsigned chipselect_mask,
                 const struct spi_board_info *info, unsigned len);
@@ -97,6 +98,7 @@ int dm355_gpio_register(void);
 
 /* DM365 function declarations */
 void dm365_init(void);
+void dm365_init_irq(void);
 void dm365_init_time(void);
 void dm365_register_clocks(void);
 void dm365_init_asp(void);
@@ -110,6 +112,7 @@ int dm365_gpio_register(void);
 
 /* DM644x function declarations */
 void dm644x_init(void);
+void dm644x_init_irq(void);
 void dm644x_init_devices(void);
 void dm644x_init_time(void);
 void dm644x_register_clocks(void);
@@ -119,6 +122,7 @@ int dm644x_gpio_register(void);
 
 /* DM646x function declarations */
 void dm646x_init(void);
+void dm646x_init_irq(void);
 void dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate);
 void dm646x_register_clocks(void);
 void dm646x_init_mcasp0(struct snd_platform_data *pdata);
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index cf78da5ab054..b8dc674e06bc 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -28,6 +28,7 @@
 
 #include "asp.h"
 #include "cpuidle.h"
+#include "irqs.h"
 #include "sram.h"
 
 #define DA8XX_TPCC_BASE                 0x01c00000
@@ -64,7 +65,7 @@ void __iomem *da8xx_syscfg1_base;
 static struct plat_serial8250_port da8xx_serial0_pdata[] = {
         {
                 .mapbase        = DA8XX_UART0_BASE,
-                .irq            = IRQ_DA8XX_UARTINT0,
+                .irq            = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT0),
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
                                         UPF_IOREMAP,
                 .iotype         = UPIO_MEM,
@@ -77,7 +78,7 @@ static struct plat_serial8250_port da8xx_serial0_pdata[] = {
 static struct plat_serial8250_port da8xx_serial1_pdata[] = {
         {
                 .mapbase        = DA8XX_UART1_BASE,
-                .irq            = IRQ_DA8XX_UARTINT1,
+                .irq            = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT1),
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
                                         UPF_IOREMAP,
                 .iotype         = UPIO_MEM,
@@ -90,7 +91,7 @@ static struct plat_serial8250_port da8xx_serial1_pdata[] = {
 static struct plat_serial8250_port da8xx_serial2_pdata[] = {
         {
                 .mapbase        = DA8XX_UART2_BASE,
-                .irq            = IRQ_DA8XX_UARTINT2,
+                .irq            = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT2),
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
                                         UPF_IOREMAP,
                 .iotype         = UPIO_MEM,
@@ -171,12 +172,12 @@ static struct resource da8xx_edma0_resources[] = {
         },
         {
                 .name   = "edma3_ccint",
-                .start  = IRQ_DA8XX_CCINT0,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCINT0),
                 .flags  = IORESOURCE_IRQ,
         },
         {
                 .name   = "edma3_ccerrint",
-                .start  = IRQ_DA8XX_CCERRINT,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCERRINT),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -196,12 +197,12 @@ static struct resource da850_edma1_resources[] = {
         },
         {
                 .name   = "edma3_ccint",
-                .start  = IRQ_DA850_CCINT1,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA850_CCINT1),
                 .flags  = IORESOURCE_IRQ,
         },
         {
                 .name   = "edma3_ccerrint",
-                .start  = IRQ_DA850_CCERRINT1,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA850_CCERRINT1),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -306,8 +307,8 @@ static struct resource da8xx_i2c_resources0[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = IRQ_DA8XX_I2CINT0,
-                .end    = IRQ_DA8XX_I2CINT0,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -326,8 +327,8 @@ static struct resource da8xx_i2c_resources1[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = IRQ_DA8XX_I2CINT1,
-                .end    = IRQ_DA8XX_I2CINT1,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -382,23 +383,23 @@ static struct resource da8xx_emac_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = IRQ_DA8XX_C0_RX_THRESH_PULSE,
-                .end    = IRQ_DA8XX_C0_RX_THRESH_PULSE,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DA8XX_C0_RX_PULSE,
-                .end    = IRQ_DA8XX_C0_RX_PULSE,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DA8XX_C0_TX_PULSE,
-                .end    = IRQ_DA8XX_C0_TX_PULSE,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DA8XX_C0_MISC_PULSE,
-                .end    = IRQ_DA8XX_C0_MISC_PULSE,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -470,7 +471,7 @@ static struct resource da830_mcasp1_resources[] = {
         },
         {
                 .name   = "common",
-                .start  = IRQ_DA8XX_MCASPINT,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -505,7 +506,7 @@ static struct resource da830_mcasp2_resources[] = {
         },
         {
                 .name   = "common",
-                .start  = IRQ_DA8XX_MCASPINT,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -540,7 +541,7 @@ static struct resource da850_mcasp_resources[] = {
         },
         {
                 .name   = "common",
-                .start  = IRQ_DA8XX_MCASPINT,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -588,43 +589,43 @@ static struct resource da8xx_pruss_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = IRQ_DA8XX_EVTOUT0,
-                .end    = IRQ_DA8XX_EVTOUT0,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DA8XX_EVTOUT1,
-                .end    = IRQ_DA8XX_EVTOUT1,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DA8XX_EVTOUT2,
-                .end    = IRQ_DA8XX_EVTOUT2,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DA8XX_EVTOUT3,
-                .end    = IRQ_DA8XX_EVTOUT3,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DA8XX_EVTOUT4,
-                .end    = IRQ_DA8XX_EVTOUT4,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DA8XX_EVTOUT5,
-                .end    = IRQ_DA8XX_EVTOUT5,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DA8XX_EVTOUT6,
-                .end    = IRQ_DA8XX_EVTOUT6,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DA8XX_EVTOUT7,
-                .end    = IRQ_DA8XX_EVTOUT7,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -674,8 +675,8 @@ static struct resource da8xx_lcdc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = { /* interrupt */
-                .start  = IRQ_DA8XX_LCDINT,
-                .end    = IRQ_DA8XX_LCDINT,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -700,48 +701,48 @@ static struct resource da8xx_gpio_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         { /* interrupt */
-                .start  = IRQ_DA8XX_GPIO0,
-                .end    = IRQ_DA8XX_GPIO0,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DA8XX_GPIO1,
-                .end    = IRQ_DA8XX_GPIO1,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DA8XX_GPIO2,
-                .end    = IRQ_DA8XX_GPIO2,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DA8XX_GPIO3,
-                .end    = IRQ_DA8XX_GPIO3,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DA8XX_GPIO4,
-                .end    = IRQ_DA8XX_GPIO4,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DA8XX_GPIO5,
-                .end    = IRQ_DA8XX_GPIO5,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DA8XX_GPIO6,
-                .end    = IRQ_DA8XX_GPIO6,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DA8XX_GPIO7,
-                .end    = IRQ_DA8XX_GPIO7,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DA8XX_GPIO8,
-                .end    = IRQ_DA8XX_GPIO8,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -766,8 +767,8 @@ static struct resource da8xx_mmcsd0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {               /* interrupt */
-                .start  = IRQ_DA8XX_MMCSDINT0,
-                .end    = IRQ_DA8XX_MMCSDINT0,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -793,8 +794,8 @@ static struct resource da850_mmcsd1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {               /* interrupt */
-                .start  = IRQ_DA850_MMCSDINT0_1,
-                .end    = IRQ_DA850_MMCSDINT0_1,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -845,8 +846,8 @@ static struct resource da8xx_rproc_resources[] = {
                 .flags          = IORESOURCE_MEM,
         },
         { /* dsp irq */
-                .start          = IRQ_DA8XX_CHIPINT0,
-                .end            = IRQ_DA8XX_CHIPINT0,
+                .start          = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
+                .end            = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
                 .flags          = IORESOURCE_IRQ,
         },
 };
@@ -936,13 +937,13 @@ static struct resource da8xx_rtc_resources[] = {
                 .flags          = IORESOURCE_MEM,
         },
         { /* timer irq */
-                .start          = IRQ_DA8XX_RTC,
-                .end            = IRQ_DA8XX_RTC,
+                .start          = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
+                .end            = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
                 .flags          = IORESOURCE_IRQ,
         },
         { /* alarm irq */
-                .start          = IRQ_DA8XX_RTC,
-                .end            = IRQ_DA8XX_RTC,
+                .start          = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
+                .end            = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
                 .flags          = IORESOURCE_IRQ,
         },
 };
@@ -1009,8 +1010,8 @@ static struct resource da8xx_spi0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = IRQ_DA8XX_SPINT0,
-                .end    = IRQ_DA8XX_SPINT0,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1022,8 +1023,8 @@ static struct resource da8xx_spi1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = IRQ_DA8XX_SPINT1,
-                .end    = IRQ_DA8XX_SPINT1,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1103,7 +1104,7 @@ static struct resource da850_sata_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = IRQ_DA850_SATAINT,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA850_SATAINT),
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index e8dbbb7479ab..40bd8029e457 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -11,21 +11,20 @@
 
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/platform_data/i2c-davinci.h>
+#include <linux/platform_data/mmc-davinci.h>
+#include <linux/platform_data/edma.h>
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
 #include <linux/reboot.h>
 
 #include <mach/hardware.h>
-#include <linux/platform_data/i2c-davinci.h>
-#include <mach/irqs.h>
 #include <mach/cputype.h>
 #include <mach/mux.h>
-#include <linux/platform_data/mmc-davinci.h>
 #include <mach/time.h>
-#include <linux/platform_data/edma.h>
-
 
 #include "davinci.h"
+#include "irqs.h"
 
 #define DAVINCI_I2C_BASE             0x01C21000
 #define DAVINCI_ATA_BASE             0x01C66000
@@ -56,7 +55,7 @@ static struct resource i2c_resources[] = {
                 .flags          = IORESOURCE_MEM,
         },
         {
-                .start          = IRQ_I2C,
+                .start          = DAVINCI_INTC_IRQ(IRQ_I2C),
                 .flags          = IORESOURCE_IRQ,
         },
 };
@@ -84,8 +83,8 @@ static struct resource ide_resources[] = {
                 .flags          = IORESOURCE_MEM,
         },
         {
-                .start          = IRQ_IDE,
-                .end            = IRQ_IDE,
+                .start          = DAVINCI_INTC_IRQ(IRQ_IDE),
+                .end            = DAVINCI_INTC_IRQ(IRQ_IDE),
                 .flags          = IORESOURCE_IRQ,
         },
 };
@@ -133,11 +132,11 @@ static struct resource mmcsd0_resources[] = {
         },
         /* IRQs:  MMC/SD, then SDIO */
         {
-                .start = IRQ_MMCINT,
+                .start = DAVINCI_INTC_IRQ(IRQ_MMCINT),
                 .flags = IORESOURCE_IRQ,
         }, {
                 /* different on dm355 */
-                .start = IRQ_SDIOINT,
+                .start = DAVINCI_INTC_IRQ(IRQ_SDIOINT),
                 .flags = IORESOURCE_IRQ,
         },
 };
@@ -163,10 +162,10 @@ static struct resource mmcsd1_resources[] = {
         },
         /* IRQs:  MMC/SD, then SDIO */
         {
-                .start = IRQ_DM355_MMCINT1,
+                .start = DAVINCI_INTC_IRQ(IRQ_DM355_MMCINT1),
                 .flags = IORESOURCE_IRQ,
         }, {
-                .start = IRQ_DM355_SDIOINT1,
+                .start = DAVINCI_INTC_IRQ(IRQ_DM355_SDIOINT1),
                 .flags = IORESOURCE_IRQ,
         },
 };
@@ -219,7 +218,8 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
                         mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
                         mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
                                                         SZ_4K - 1;
-                        mmcsd1_resources[2].start = IRQ_DM365_SDIOINT1;
+                        mmcsd1_resources[2].start = DAVINCI_INTC_IRQ(
+                                                        IRQ_DM365_SDIOINT1);
                         davinci_mmcsd1_device.name = "da830-mmc";
                 } else
                         break;
@@ -230,7 +230,8 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
                 if (cpu_is_davinci_dm355()) {
                         mmcsd0_resources[0].start = DM355_MMCSD0_BASE;
                         mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1;
-                        mmcsd0_resources[2].start = IRQ_DM355_SDIOINT0;
+                        mmcsd0_resources[2].start = DAVINCI_INTC_IRQ(
+                                                        IRQ_DM355_SDIOINT0);
 
                         /* expose all 6 MMC0 signals:  CLK, CMD, DATA[0..3] */
                         davinci_cfg_reg(DM355_MMCSD0);
@@ -241,7 +242,8 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
                         mmcsd0_resources[0].start = DM365_MMCSD0_BASE;
                         mmcsd0_resources[0].end = DM365_MMCSD0_BASE +
                                                         SZ_4K - 1;
-                        mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0;
+                        mmcsd0_resources[2].start = DAVINCI_INTC_IRQ(
+                                                        IRQ_DM365_SDIOINT0);
                         davinci_mmcsd0_device.name = "da830-mmc";
                 } else if (cpu_is_davinci_dm644x()) {
                         /* REVISIT: should this be in board-init code? */
@@ -313,13 +315,13 @@ int davinci_gpio_register(struct resource *res, int size, void *pdata)
 struct davinci_timer_instance davinci_timer_instance[2] = {
         {
                 .base           = DAVINCI_TIMER0_BASE,
-                .bottom_irq     = IRQ_TINT0_TINT12,
-                .top_irq        = IRQ_TINT0_TINT34,
+                .bottom_irq     = DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12),
+                .top_irq        = DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34),
         },
         {
                 .base           = DAVINCI_TIMER1_BASE,
-                .bottom_irq     = IRQ_TINT1_TINT12,
-                .top_irq        = IRQ_TINT1_TINT34,
+                .bottom_irq     = DAVINCI_INTC_IRQ(IRQ_TINT1_TINT12),
+                .top_irq        = DAVINCI_INTC_IRQ(IRQ_TINT1_TINT34),
         },
 };
 
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 4c6e0bef4509..4a482445b9a2 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -15,6 +15,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/dmaengine.h>
 #include <linux/init.h>
+#include <linux/irqchip/irq-davinci-aintc.h>
 #include <linux/platform_data/edma.h>
 #include <linux/platform_data/gpio-davinci.h>
 #include <linux/platform_data/spi-davinci.h>
@@ -26,13 +27,13 @@
 
 #include <mach/common.h>
 #include <mach/cputype.h>
-#include <mach/irqs.h>
 #include <mach/mux.h>
 #include <mach/serial.h>
 #include <mach/time.h>
 
 #include "asp.h"
 #include "davinci.h"
+#include "irqs.h"
 #include "mux.h"
 
 #define DM355_UART2_BASE        (IO_PHYS + 0x206000)
@@ -53,7 +54,7 @@ static struct resource dm355_spi0_resources[] = {
                 .flags = IORESOURCE_MEM,
         },
         {
-                .start = IRQ_DM355_SPINT0_0,
+                .start = DAVINCI_INTC_IRQ(IRQ_DM355_SPINT0_0),
                 .flags = IORESOURCE_IRQ,
         },
 };
@@ -273,12 +274,12 @@ static struct resource edma_resources[] = {
         },
         {
                 .name   = "edma3_ccint",
-                .start  = IRQ_CCINT0,
+                .start  = DAVINCI_INTC_IRQ(IRQ_CCINT0),
                 .flags  = IORESOURCE_IRQ,
         },
         {
                 .name   = "edma3_ccerrint",
-                .start  = IRQ_CCERRINT,
+                .start  = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
                 .flags  = IORESOURCE_IRQ,
         },
         /* not using (or muxing) TC*_ERR */
@@ -358,13 +359,13 @@ static struct platform_device dm355_vpss_device = {
 
 static struct resource vpfe_resources[] = {
         {
-                .start          = IRQ_VDINT0,
-                .end            = IRQ_VDINT0,
+                .start          = DAVINCI_INTC_IRQ(IRQ_VDINT0),
+                .end            = DAVINCI_INTC_IRQ(IRQ_VDINT0),
                 .flags          = IORESOURCE_IRQ,
         },
         {
-                .start          = IRQ_VDINT1,
-                .end            = IRQ_VDINT1,
+                .start          = DAVINCI_INTC_IRQ(IRQ_VDINT1),
+                .end            = DAVINCI_INTC_IRQ(IRQ_VDINT1),
                 .flags          = IORESOURCE_IRQ,
         },
 };
@@ -422,8 +423,8 @@ static struct platform_device dm355_osd_dev = {
 
 static struct resource dm355_venc_resources[] = {
         {
-                .start  = IRQ_VENCINT,
-                .end    = IRQ_VENCINT,
+                .start  = DAVINCI_INTC_IRQ(IRQ_VENCINT),
+                .end    = DAVINCI_INTC_IRQ(IRQ_VENCINT),
                 .flags  = IORESOURCE_IRQ,
         },
         /* venc registers io space */
@@ -442,8 +443,8 @@ static struct resource dm355_venc_resources[] = {
 
 static struct resource dm355_v4l2_disp_resources[] = {
         {
-                .start  = IRQ_VENCINT,
-                .end    = IRQ_VENCINT,
+                .start  = DAVINCI_INTC_IRQ(IRQ_VENCINT),
+                .end    = DAVINCI_INTC_IRQ(IRQ_VENCINT),
                 .flags  = IORESOURCE_IRQ,
         },
         /* venc registers io space */
@@ -547,38 +548,38 @@ static struct resource dm355_gpio_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {       /* interrupt */
-                .start  = IRQ_DM355_GPIOBNK0,
-                .end    = IRQ_DM355_GPIOBNK0,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM355_GPIOBNK1,
-                .end    = IRQ_DM355_GPIOBNK1,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM355_GPIOBNK2,
-                .end    = IRQ_DM355_GPIOBNK2,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM355_GPIOBNK3,
-                .end    = IRQ_DM355_GPIOBNK3,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM355_GPIOBNK4,
-                .end    = IRQ_DM355_GPIOBNK4,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM355_GPIOBNK5,
-                .end    = IRQ_DM355_GPIOBNK5,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM355_GPIOBNK6,
-                .end    = IRQ_DM355_GPIOBNK6,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -632,7 +633,7 @@ static struct davinci_timer_info dm355_timer_info = {
 static struct plat_serial8250_port dm355_serial0_platform_data[] = {
         {
                 .mapbase        = DAVINCI_UART0_BASE,
-                .irq            = IRQ_UARTINT0,
+                .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
                                   UPF_IOREMAP,
                 .iotype         = UPIO_MEM,
@@ -645,7 +646,7 @@ static struct plat_serial8250_port dm355_serial0_platform_data[] = {
 static struct plat_serial8250_port dm355_serial1_platform_data[] = {
         {
                 .mapbase        = DAVINCI_UART1_BASE,
-                .irq            = IRQ_UARTINT1,
+                .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
                                   UPF_IOREMAP,
                 .iotype         = UPIO_MEM,
@@ -658,7 +659,7 @@ static struct plat_serial8250_port dm355_serial1_platform_data[] = {
 static struct plat_serial8250_port dm355_serial2_platform_data[] = {
         {
                 .mapbase        = DM355_UART2_BASE,
-                .irq            = IRQ_DM355_UARTINT2,
+                .irq            = DAVINCI_INTC_IRQ(IRQ_DM355_UARTINT2),
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
                                   UPF_IOREMAP,
                 .iotype         = UPIO_MEM,
@@ -704,10 +705,6 @@ static const struct davinci_soc_info davinci_soc_info_dm355 = {
         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
         .pinmux_pins            = dm355_pins,
         .pinmux_pins_num        = ARRAY_SIZE(dm355_pins),
-        .intc_base              = DAVINCI_ARM_INTC_BASE,
-        .intc_type              = DAVINCI_INTC_TYPE_AINTC,
-        .intc_irq_prios         = dm355_default_priorities,
-        .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
         .timer_info             = &dm355_timer_info,
         .sram_dma               = 0x00010000,
         .sram_len               = SZ_32K,
@@ -793,6 +790,21 @@ int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
         return 0;
 }
 
+static const struct davinci_aintc_config dm355_aintc_config = {
+        .reg = {
+                .start          = DAVINCI_ARM_INTC_BASE,
+                .end            = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        .num_irqs               = 64,
+        .prios                  = dm355_default_priorities,
+};
+
+void __init dm355_init_irq(void)
+{
+        davinci_aintc_init(&dm355_aintc_config);
+}
+
 static int __init dm355_init_devices(void)
 {
         struct platform_device *edma_pdev;
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 01fb2b0c82de..8e0a77315add 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -19,6 +19,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/dmaengine.h>
 #include <linux/init.h>
+#include <linux/irqchip/irq-davinci-aintc.h>
 #include <linux/platform_data/edma.h>
 #include <linux/platform_data/gpio-davinci.h>
 #include <linux/platform_data/keyscan-davinci.h>
@@ -31,13 +32,13 @@
 
 #include <mach/common.h>
 #include <mach/cputype.h>
-#include <mach/irqs.h>
 #include <mach/mux.h>
 #include <mach/serial.h>
 #include <mach/time.h>
 
 #include "asp.h"
 #include "davinci.h"
+#include "irqs.h"
 #include "mux.h"
 
 #define DM365_REF_FREQ          24000000        /* 24 MHz on the DM365 EVM */
@@ -224,7 +225,7 @@ static struct resource dm365_spi0_resources[] = {
                 .flags = IORESOURCE_MEM,
         },
         {
-                .start = IRQ_DM365_SPIINT0_0,
+                .start = DAVINCI_INTC_IRQ(IRQ_DM365_SPIINT0_0),
                 .flags = IORESOURCE_IRQ,
         },
 };
@@ -266,43 +267,43 @@ static struct resource dm365_gpio_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {       /* interrupt */
-                .start  = IRQ_DM365_GPIO0,
-                .end    = IRQ_DM365_GPIO0,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM365_GPIO1,
-                .end    = IRQ_DM365_GPIO1,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM365_GPIO2,
-                .end    = IRQ_DM365_GPIO2,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM365_GPIO3,
-                .end    = IRQ_DM365_GPIO3,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM365_GPIO4,
-                .end    = IRQ_DM365_GPIO4,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM365_GPIO5,
-                .end    = IRQ_DM365_GPIO5,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM365_GPIO6,
-                .end    = IRQ_DM365_GPIO6,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM365_GPIO7,
-                .end    = IRQ_DM365_GPIO7,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -336,23 +337,23 @@ static struct resource dm365_emac_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = IRQ_DM365_EMAC_RXTHRESH,
-                .end    = IRQ_DM365_EMAC_RXTHRESH,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM365_EMAC_RXPULSE,
-                .end    = IRQ_DM365_EMAC_RXPULSE,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM365_EMAC_TXPULSE,
-                .end    = IRQ_DM365_EMAC_TXPULSE,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM365_EMAC_MISCPULSE,
-                .end    = IRQ_DM365_EMAC_MISCPULSE,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -518,12 +519,12 @@ static struct resource edma_resources[] = {
         },
         {
                 .name   = "edma3_ccint",
-                .start  = IRQ_CCINT0,
+                .start  = DAVINCI_INTC_IRQ(IRQ_CCINT0),
                 .flags  = IORESOURCE_IRQ,
         },
         {
                 .name   = "edma3_ccerrint",
-                .start  = IRQ_CCERRINT,
+                .start  = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
                 .flags  = IORESOURCE_IRQ,
         },
         /* not using TC*_ERR */
@@ -597,7 +598,7 @@ static struct resource dm365_rtc_resources[] = {
                 .flags = IORESOURCE_MEM,
         },
         {
-                .start = IRQ_DM365_RTCINT,
+                .start = DAVINCI_INTC_IRQ(IRQ_DM365_RTCINT),
                 .flags = IORESOURCE_IRQ,
         },
 };
@@ -627,8 +628,8 @@ static struct resource dm365_ks_resources[] = {
         },
         {
                 /* interrupt */
-                .start = IRQ_DM365_KEYINT,
-                .end = IRQ_DM365_KEYINT,
+                .start = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
+                .end = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
                 .flags = IORESOURCE_IRQ,
         },
 };
@@ -669,7 +670,7 @@ static struct davinci_timer_info dm365_timer_info = {
 static struct plat_serial8250_port dm365_serial0_platform_data[] = {
         {
                 .mapbase        = DAVINCI_UART0_BASE,
-                .irq            = IRQ_UARTINT0,
+                .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
                                   UPF_IOREMAP,
                 .iotype         = UPIO_MEM,
@@ -682,7 +683,7 @@ static struct plat_serial8250_port dm365_serial0_platform_data[] = {
 static struct plat_serial8250_port dm365_serial1_platform_data[] = {
         {
                 .mapbase        = DM365_UART1_BASE,
-                .irq            = IRQ_UARTINT1,
+                .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
                                   UPF_IOREMAP,
                 .iotype         = UPIO_MEM,
@@ -721,10 +722,6 @@ static const struct davinci_soc_info davinci_soc_info_dm365 = {
         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
         .pinmux_pins            = dm365_pins,
         .pinmux_pins_num        = ARRAY_SIZE(dm365_pins),
-        .intc_base              = DAVINCI_ARM_INTC_BASE,
-        .intc_type              = DAVINCI_INTC_TYPE_AINTC,
-        .intc_irq_prios         = dm365_default_priorities,
-        .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
         .timer_info             = &dm365_timer_info,
         .emac_pdata             = &dm365_emac_pdata,
         .sram_dma               = 0x00010000,
@@ -822,13 +819,13 @@ static struct platform_device dm365_vpss_device = {
 
 static struct resource vpfe_resources[] = {
         {
-                .start          = IRQ_VDINT0,
-                .end            = IRQ_VDINT0,
+                .start          = DAVINCI_INTC_IRQ(IRQ_VDINT0),
+                .end            = DAVINCI_INTC_IRQ(IRQ_VDINT0),
                 .flags          = IORESOURCE_IRQ,
         },
         {
-                .start          = IRQ_VDINT1,
-                .end            = IRQ_VDINT1,
+                .start          = DAVINCI_INTC_IRQ(IRQ_VDINT1),
+                .end            = DAVINCI_INTC_IRQ(IRQ_VDINT1),
                 .flags          = IORESOURCE_IRQ,
         },
 };
@@ -909,8 +906,8 @@ static struct platform_device dm365_osd_dev = {
 
 static struct resource dm365_venc_resources[] = {
         {
-                .start = IRQ_VENCINT,
-                .end   = IRQ_VENCINT,
+                .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
+                .end   = DAVINCI_INTC_IRQ(IRQ_VENCINT),
                 .flags = IORESOURCE_IRQ,
         },
         /* venc registers io space */
@@ -929,8 +926,8 @@ static struct resource dm365_venc_resources[] = {
 
 static struct resource dm365_v4l2_disp_resources[] = {
         {
-                .start = IRQ_VENCINT,
-                .end   = IRQ_VENCINT,
+                .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
+                .end   = DAVINCI_INTC_IRQ(IRQ_VENCINT),
                 .flags = IORESOURCE_IRQ,
         },
         /* venc registers io space */
@@ -1052,6 +1049,21 @@ int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
         return 0;
 }
 
+static const struct davinci_aintc_config dm365_aintc_config = {
+        .reg = {
+                .start          = DAVINCI_ARM_INTC_BASE,
+                .end            = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        .num_irqs               = 64,
+        .prios                  = dm365_default_priorities,
+};
+
+void __init dm365_init_irq(void)
+{
+        davinci_aintc_init(&dm365_aintc_config);
+}
+
 static int __init dm365_init_devices(void)
 {
         struct platform_device *edma_pdev;
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 38f92b7d413e..cecc7ceb8d34 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -14,6 +14,7 @@
 #include <linux/clkdev.h>
 #include <linux/dmaengine.h>
 #include <linux/init.h>
+#include <linux/irqchip/irq-davinci-aintc.h>
 #include <linux/platform_data/edma.h>
 #include <linux/platform_data/gpio-davinci.h>
 #include <linux/platform_device.h>
@@ -23,13 +24,13 @@
 
 #include <mach/common.h>
 #include <mach/cputype.h>
-#include <mach/irqs.h>
 #include <mach/mux.h>
 #include <mach/serial.h>
 #include <mach/time.h>
 
 #include "asp.h"
 #include "davinci.h"
+#include "irqs.h"
 #include "mux.h"
 
 /*
@@ -59,8 +60,8 @@ static struct resource dm644x_emac_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start = IRQ_EMACINT,
-                .end   = IRQ_EMACINT,
+                .start = DAVINCI_INTC_IRQ(IRQ_EMACINT),
+                .end   = DAVINCI_INTC_IRQ(IRQ_EMACINT),
                 .flags = IORESOURCE_IRQ,
         },
 };
@@ -260,12 +261,12 @@ static struct resource edma_resources[] = {
         },
         {
                 .name   = "edma3_ccint",
-                .start  = IRQ_CCINT0,
+                .start  = DAVINCI_INTC_IRQ(IRQ_CCINT0),
                 .flags  = IORESOURCE_IRQ,
         },
         {
                 .name   = "edma3_ccerrint",
-                .start  = IRQ_CCERRINT,
+                .start  = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
                 .flags  = IORESOURCE_IRQ,
         },
         /* not using TC*_ERR */
@@ -330,13 +331,13 @@ static struct platform_device dm644x_vpss_device = {
 
 static struct resource dm644x_vpfe_resources[] = {
         {
-                .start          = IRQ_VDINT0,
-                .end            = IRQ_VDINT0,
+                .start          = DAVINCI_INTC_IRQ(IRQ_VDINT0),
+                .end            = DAVINCI_INTC_IRQ(IRQ_VDINT0),
                 .flags          = IORESOURCE_IRQ,
         },
         {
-                .start          = IRQ_VDINT1,
-                .end            = IRQ_VDINT1,
+                .start          = DAVINCI_INTC_IRQ(IRQ_VDINT1),
+                .end            = DAVINCI_INTC_IRQ(IRQ_VDINT1),
                 .flags          = IORESOURCE_IRQ,
         },
 };
@@ -442,8 +443,8 @@ static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
 
 static struct resource dm644x_v4l2_disp_resources[] = {
         {
-                .start  = IRQ_VENCINT,
-                .end    = IRQ_VENCINT,
+                .start  = DAVINCI_INTC_IRQ(IRQ_VENCINT),
+                .end    = DAVINCI_INTC_IRQ(IRQ_VENCINT),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -491,28 +492,28 @@ static struct resource dm644_gpio_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {       /* interrupt */
-                .start  = IRQ_GPIOBNK0,
-                .end    = IRQ_GPIOBNK0,
+                .start  = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
+                .end    = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_GPIOBNK1,
-                .end    = IRQ_GPIOBNK1,
+                .start  = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
+                .end    = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_GPIOBNK2,
-                .end    = IRQ_GPIOBNK2,
+                .start  = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
+                .end    = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_GPIOBNK3,
-                .end    = IRQ_GPIOBNK3,
+                .start  = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
+                .end    = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_GPIOBNK4,
-                .end    = IRQ_GPIOBNK4,
+                .start  = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
+                .end    = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -573,7 +574,7 @@ static struct davinci_timer_info dm644x_timer_info = {
 static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
         {
                 .mapbase        = DAVINCI_UART0_BASE,
-                .irq            = IRQ_UARTINT0,
+                .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
                                   UPF_IOREMAP,
                 .iotype         = UPIO_MEM,
@@ -586,7 +587,7 @@ static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
 static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
         {
                 .mapbase        = DAVINCI_UART1_BASE,
-                .irq            = IRQ_UARTINT1,
+                .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
                                   UPF_IOREMAP,
                 .iotype         = UPIO_MEM,
@@ -599,7 +600,7 @@ static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
 static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
         {
                 .mapbase        = DAVINCI_UART2_BASE,
-                .irq            = IRQ_UARTINT2,
+                .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT2),
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
                                   UPF_IOREMAP,
                 .iotype         = UPIO_MEM,
@@ -645,10 +646,6 @@ static const struct davinci_soc_info davinci_soc_info_dm644x = {
         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
         .pinmux_pins            = dm644x_pins,
         .pinmux_pins_num        = ARRAY_SIZE(dm644x_pins),
-        .intc_base              = DAVINCI_ARM_INTC_BASE,
-        .intc_type              = DAVINCI_INTC_TYPE_AINTC,
-        .intc_irq_prios         = dm644x_default_priorities,
-        .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
         .timer_info             = &dm644x_timer_info,
         .emac_pdata             = &dm644x_emac_pdata,
         .sram_dma               = 0x00008000,
@@ -729,6 +726,21 @@ int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
         return 0;
 }
 
+static const struct davinci_aintc_config dm644x_aintc_config = {
+        .reg = {
+                .start          = DAVINCI_ARM_INTC_BASE,
+                .end            = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        .num_irqs               = 64,
+        .prios                  = dm644x_default_priorities,
+};
+
+void __init dm644x_init_irq(void)
+{
+        davinci_aintc_init(&dm644x_aintc_config);
+}
+
 void __init dm644x_init_devices(void)
 {
         struct platform_device *edma_pdev;
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 7dc54b2a610f..f33392f77a03 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -15,6 +15,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/dmaengine.h>
 #include <linux/init.h>
+#include <linux/irqchip/irq-davinci-aintc.h>
 #include <linux/platform_data/edma.h>
 #include <linux/platform_data/gpio-davinci.h>
 #include <linux/platform_device.h>
@@ -24,13 +25,13 @@
 
 #include <mach/common.h>
 #include <mach/cputype.h>
-#include <mach/irqs.h>
 #include <mach/mux.h>
 #include <mach/serial.h>
 #include <mach/time.h>
 
 #include "asp.h"
 #include "davinci.h"
+#include "irqs.h"
 #include "mux.h"
 
 #define DAVINCI_VPIF_BASE       (0x01C12000)
@@ -62,23 +63,23 @@ static struct resource dm646x_emac_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = IRQ_DM646X_EMACRXTHINT,
-                .end    = IRQ_DM646X_EMACRXTHINT,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM646X_EMACRXINT,
-                .end    = IRQ_DM646X_EMACRXINT,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM646X_EMACTXINT,
-                .end    = IRQ_DM646X_EMACTXINT,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM646X_EMACMISCINT,
-                .end    = IRQ_DM646X_EMACMISCINT,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -273,12 +274,12 @@ static struct resource edma_resources[] = {
         },
         {
                 .name   = "edma3_ccint",
-                .start  = IRQ_CCINT0,
+                .start  = DAVINCI_INTC_IRQ(IRQ_CCINT0),
                 .flags  = IORESOURCE_IRQ,
         },
         {
                 .name   = "edma3_ccerrint",
-                .start  = IRQ_CCERRINT,
+                .start  = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
                 .flags  = IORESOURCE_IRQ,
         },
         /* not using TC*_ERR */
@@ -315,12 +316,12 @@ static struct resource dm646x_mcasp0_resources[] = {
         },
         {
                 .name   = "tx",
-                .start  = IRQ_DM646X_MCASP0TXINT,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0TXINT),
                 .flags  = IORESOURCE_IRQ,
         },
         {
                 .name   = "rx",
-                .start  = IRQ_DM646X_MCASP0RXINT,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0RXINT),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -341,7 +342,7 @@ static struct resource dm646x_mcasp1_resources[] = {
         },
         {
                 .name   = "tx",
-                .start  = IRQ_DM646X_MCASP1TXINT,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP1TXINT),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -388,13 +389,13 @@ static struct platform_device vpif_dev = {
 
 static struct resource vpif_display_resource[] = {
         {
-                .start = IRQ_DM646X_VP_VERTINT2,
-                .end   = IRQ_DM646X_VP_VERTINT2,
+                .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
+                .end   = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
                 .flags = IORESOURCE_IRQ,
         },
         {
-                .start = IRQ_DM646X_VP_VERTINT3,
-                .end   = IRQ_DM646X_VP_VERTINT3,
+                .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
+                .end   = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
                 .flags = IORESOURCE_IRQ,
         },
 };
@@ -412,13 +413,13 @@ static struct platform_device vpif_display_dev = {
 
 static struct resource vpif_capture_resource[] = {
         {
-                .start = IRQ_DM646X_VP_VERTINT0,
-                .end   = IRQ_DM646X_VP_VERTINT0,
+                .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
+                .end   = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
                 .flags = IORESOURCE_IRQ,
         },
         {
-                .start = IRQ_DM646X_VP_VERTINT1,
-                .end   = IRQ_DM646X_VP_VERTINT1,
+                .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
+                .end   = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
                 .flags = IORESOURCE_IRQ,
         },
 };
@@ -441,18 +442,18 @@ static struct resource dm646x_gpio_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {       /* interrupt */
-                .start  = IRQ_DM646X_GPIOBNK0,
-                .end    = IRQ_DM646X_GPIOBNK0,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM646X_GPIOBNK1,
-                .end    = IRQ_DM646X_GPIOBNK1,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
                 .flags  = IORESOURCE_IRQ,
         },
         {
-                .start  = IRQ_DM646X_GPIOBNK2,
-                .end    = IRQ_DM646X_GPIOBNK2,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -513,7 +514,7 @@ static struct davinci_timer_info dm646x_timer_info = {
 static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
         {
                 .mapbase        = DAVINCI_UART0_BASE,
-                .irq            = IRQ_UARTINT0,
+                .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
                                   UPF_IOREMAP,
                 .iotype         = UPIO_MEM32,
@@ -526,7 +527,7 @@ static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
 static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
         {
                 .mapbase        = DAVINCI_UART1_BASE,
-                .irq            = IRQ_UARTINT1,
+                .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
                                   UPF_IOREMAP,
                 .iotype         = UPIO_MEM32,
@@ -539,7 +540,7 @@ static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
 static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
         {
                 .mapbase        = DAVINCI_UART2_BASE,
-                .irq            = IRQ_DM646X_UARTINT2,
+                .irq            = DAVINCI_INTC_IRQ(IRQ_DM646X_UARTINT2),
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
                                   UPF_IOREMAP,
                 .iotype         = UPIO_MEM32,
@@ -585,10 +586,6 @@ static const struct davinci_soc_info davinci_soc_info_dm646x = {
         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
         .pinmux_pins            = dm646x_pins,
         .pinmux_pins_num        = ARRAY_SIZE(dm646x_pins),
-        .intc_base              = DAVINCI_ARM_INTC_BASE,
-        .intc_type              = DAVINCI_INTC_TYPE_AINTC,
-        .intc_irq_prios         = dm646x_default_priorities,
-        .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
         .timer_info             = &dm646x_timer_info,
         .emac_pdata             = &dm646x_emac_pdata,
         .sram_dma               = 0x10010000,
@@ -690,6 +687,21 @@ void __init dm646x_register_clocks(void)
         platform_device_register(&dm646x_pll2_device);
 }
 
+static const struct davinci_aintc_config dm646x_aintc_config = {
+        .reg = {
+                .start          = DAVINCI_ARM_INTC_BASE,
+                .end            = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        .num_irqs               = 64,
+        .prios                  = dm646x_default_priorities,
+};
+
+void __init dm646x_init_irq(void)
+{
+        davinci_aintc_init(&dm646x_aintc_config);
+}
+
 static int __init dm646x_init_devices(void)
 {
         int ret = 0;
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index b577e13a9c23..9526e5da0d33 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -17,11 +17,12 @@
 #include <linux/types.h>
 #include <linux/reboot.h>
 
-void davinci_timer_init(struct clk *clk);
+#include <asm/irq.h>
+
+#define DAVINCI_INTC_START              NR_IRQS
+#define DAVINCI_INTC_IRQ(_irqnum)       (DAVINCI_INTC_START + (_irqnum))
 
-extern void davinci_irq_init(void);
-extern void __iomem *davinci_intc_base;
-extern int davinci_intc_type;
+void davinci_timer_init(struct clk *clk);
 
 struct davinci_timer_instance {
         u32             base;
@@ -57,11 +58,6 @@ struct davinci_soc_info {
         u32                             pinmux_base;
         const struct mux_config         *pinmux_pins;
         unsigned long                   pinmux_pins_num;
-        u32                             intc_base;
-        int                             intc_type;
-        u8                              *intc_irq_prios;
-        unsigned long                   intc_irq_num;
-        u32                             *intc_host_map;
         struct davinci_timer_info       *timer_info;
         int                             gpio_type;
         u32                             gpio_base;
diff --git a/arch/arm/mach-davinci/include/mach/cpufreq.h b/arch/arm/mach-davinci/include/mach/cpufreq.h
deleted file mode 100644
index 3c089cfb6cd6..000000000000
--- a/arch/arm/mach-davinci/include/mach/cpufreq.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * TI DaVinci CPUFreq platform support.
- *
- * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef _MACH_DAVINCI_CPUFREQ_H
-#define _MACH_DAVINCI_CPUFREQ_H
-
-#include <linux/cpufreq.h>
-
-struct davinci_cpufreq_config {
-        struct cpufreq_frequency_table *freq_table;
-        int (*set_voltage) (unsigned int index);
-        int (*init) (void);
-};
-
-#endif
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index ab4a57f433f4..1618b30661a9 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -88,10 +88,12 @@ extern unsigned int da850_max_speed;
 #define DA8XX_ARM_RAM_BASE      0xffff0000
 
 void da830_init(void);
+void da830_init_irq(void);
 void da830_init_time(void);
 void da830_register_clocks(void);
 
 void da850_init(void);
+void da850_init_irq(void);
 void da850_init_time(void);
 void da850_register_clocks(void);
 
diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S
deleted file mode 100644
index cf5f573eb5fd..000000000000
--- a/arch/arm/mach-davinci/include/mach/entry-macro.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Low-level IRQ helper macros for TI DaVinci-based platforms
- *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <mach/irqs.h>
-
-                .macro  get_irqnr_preamble, base, tmp
-                ldr \base, =davinci_intc_base
-                ldr \base, [\base]
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-#if defined(CONFIG_AINTC) && defined(CONFIG_CP_INTC)
-                ldr \tmp, =davinci_intc_type
-                ldr \tmp, [\tmp]
-                cmp \tmp, #DAVINCI_INTC_TYPE_CP_INTC
-                beq 1001f
-#endif
-#if defined(CONFIG_AINTC)
-                ldr \tmp, [\base, #0x14]
-                movs \tmp, \tmp, lsr #2
-                sub \irqnr, \tmp, #1
-                b 1002f
-#endif
-#if defined(CONFIG_CP_INTC)
-1001:           ldr \irqnr, [\base, #0x80] /* get irq number */
-                mov \tmp, \irqnr, lsr #31
-                and \irqnr, \irqnr, #0xff  /* irq is in bits 0-9 */
-                and \tmp, \tmp, #0x1
-                cmp \tmp, #0x1
-#endif
-1002:
-                .endm
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
deleted file mode 100644
index 952dc126c390..000000000000
--- a/arch/arm/mach-davinci/irq.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Interrupt handler for DaVinci boards.
- *
- * Copyright (C) 2006 Texas Instruments.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/cputype.h>
-#include <mach/common.h>
-#include <asm/mach/irq.h>
-
-#define FIQ_REG0_OFFSET         0x0000
-#define FIQ_REG1_OFFSET         0x0004
-#define IRQ_REG0_OFFSET         0x0008
-#define IRQ_REG1_OFFSET         0x000C
-#define IRQ_ENT_REG0_OFFSET     0x0018
-#define IRQ_ENT_REG1_OFFSET     0x001C
-#define IRQ_INCTL_REG_OFFSET    0x0020
-#define IRQ_EABASE_REG_OFFSET   0x0024
-#define IRQ_INTPRI0_REG_OFFSET  0x0030
-#define IRQ_INTPRI7_REG_OFFSET  0x004C
-
-static inline void davinci_irq_writel(unsigned long value, int offset)
-{
-        __raw_writel(value, davinci_intc_base + offset);
-}
-
-static __init void
-davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
-{
-        struct irq_chip_generic *gc;
-        struct irq_chip_type *ct;
-
-        gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);
-        if (!gc) {
-                pr_err("%s: irq_alloc_generic_chip for IRQ %u failed\n",
-                       __func__, irq_start);
-                return;
-        }
-
-        ct = gc->chip_types;
-        ct->chip.irq_ack = irq_gc_ack_set_bit;
-        ct->chip.irq_mask = irq_gc_mask_clr_bit;
-        ct->chip.irq_unmask = irq_gc_mask_set_bit;
-
-        ct->regs.ack = IRQ_REG0_OFFSET;
-        ct->regs.mask = IRQ_ENT_REG0_OFFSET;
-        irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
-                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
-}
-
-/* ARM Interrupt Controller Initialization */
-void __init davinci_irq_init(void)
-{
-        unsigned i, j;
-        const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
-
-        davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
-        davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_4K);
-        if (WARN_ON(!davinci_intc_base))
-                return;
-
-        /* Clear all interrupt requests */
-        davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
-        davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
-        davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
-        davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
-
-        /* Disable all interrupts */
-        davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET);
-        davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET);
-
-        /* Interrupts disabled immediately, IRQ entry reflects all */
-        davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET);
-
-        /* we don't use the hardware vector table, just its entry addresses */
-        davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET);
-
-        /* Clear all interrupt requests */
-        davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
-        davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
-        davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
-        davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
-
-        for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
-                u32             pri;
-
-                for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
-                        pri |= (*davinci_def_priorities & 0x07) << j;
-                davinci_irq_writel(pri, i);
-        }
-
-        for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; i += 32, j += 0x04)
-                davinci_alloc_gc(davinci_intc_base + j, i, 32);
-
-        irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq);
-}
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/irqs.h
index edb2ca62321a..8f9fc7a56ce8 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/irqs.h
@@ -30,9 +30,6 @@
 /* Base address */
 #define DAVINCI_ARM_INTC_BASE 0x01C48000
 
-#define DAVINCI_INTC_TYPE_AINTC         0
-#define DAVINCI_INTC_TYPE_CP_INTC       1
-
 /* Interrupt lines */
 #define IRQ_VDINT0       0
 #define IRQ_VDINT1       1
@@ -404,6 +401,5 @@
 /* da850 currently has the most gpio pins (144) */
 #define DAVINCI_N_GPIO                  144
 /* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
-#define NR_IRQS                         (DA850_N_CP_INTC_IRQ + DAVINCI_N_GPIO)
 
 #endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-davinci/usb-da8xx.c b/arch/arm/mach-davinci/usb-da8xx.c
index c17ce66a3d95..25f21ee86f1a 100644
--- a/arch/arm/mach-davinci/usb-da8xx.c
+++ b/arch/arm/mach-davinci/usb-da8xx.c
@@ -18,7 +18,8 @@
 #include <mach/common.h>
 #include <mach/cputype.h>
 #include <mach/da8xx.h>
-#include <mach/irqs.h>
+
+#include "irqs.h"
 
 #define DA8XX_USB0_BASE         0x01e00000
 #define DA8XX_USB1_BASE         0x01e25000
@@ -70,7 +71,7 @@ static struct resource da8xx_usb20_resources[] = {
                 .flags          = IORESOURCE_MEM,
         },
         {
-                .start          = IRQ_DA8XX_USB_INT,
+                .start          = DAVINCI_INTC_IRQ(IRQ_DA8XX_USB_INT),
                 .flags          = IORESOURCE_IRQ,
                 .name           = "mc",
         },
@@ -105,8 +106,8 @@ static struct resource da8xx_usb11_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = IRQ_DA8XX_IRQN,
-                .end    = IRQ_DA8XX_IRQN,
+                .start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_IRQN),
+                .end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_IRQN),
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
index 31ed7aa47227..dd8db61cdd1c 100644
--- a/arch/arm/mach-davinci/usb.c
+++ b/arch/arm/mach-davinci/usb.c
@@ -2,16 +2,16 @@
 /*
  * USB
  */
+#include <linux/dma-mapping.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-
+#include <linux/platform_data/usb-davinci.h>
 #include <linux/usb/musb.h>
 
 #include <mach/common.h>
-#include <mach/irqs.h>
 #include <mach/cputype.h>
-#include <linux/platform_data/usb-davinci.h>
+
+#include "irqs.h"
 
 #define DAVINCI_USB_OTG_BASE    0x01c64000
 
@@ -38,7 +38,7 @@ static struct resource usb_resources[] = {
                 .flags          = IORESOURCE_MEM,
         },
         {
-                .start          = IRQ_USBINT,
+                .start          = DAVINCI_INTC_IRQ(IRQ_USBINT),
                 .flags          = IORESOURCE_IRQ,
                 .name           = "mc"
         },
@@ -70,8 +70,9 @@ void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms)
 
         if (cpu_is_davinci_dm646x()) {
                 /* Override the defaults as DM6467 uses different IRQs. */
-                usb_dev.resource[1].start = IRQ_DM646X_USBINT;
-                usb_dev.resource[2].start = IRQ_DM646X_USBDMAINT;
+                usb_dev.resource[1].start = DAVINCI_INTC_IRQ(IRQ_DM646X_USBINT);
+                usb_dev.resource[2].start = DAVINCI_INTC_IRQ(
+                                                        IRQ_DM646X_USBDMAINT);
         } else  /* other devices don't have dedicated CPPI IRQ */
                 usb_dev.num_resources = 2;
 
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index c6a533699b00..85b74ac943f0 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -26,7 +26,6 @@
 #include <mach/gpio-ep93xx.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
-#include <mach/gpio-ep93xx.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S
index 005695c9bf40..0ac2cb9a7355 100644
--- a/arch/arm/mach-exynos/headsmp.S
+++ b/arch/arm/mach-exynos/headsmp.S
@@ -36,4 +36,4 @@ ENDPROC(exynos4_secondary_startup)
 
         .align 2
 1:      .long   .
-        .long   pen_release
+        .long   exynos_pen_release
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index c39ffd2e2fe6..abcac6164233 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -28,6 +28,9 @@
 
 extern void exynos4_secondary_startup(void);
 
+/* XXX exynos_pen_release is cargo culted code - DO NOT COPY XXX */
+volatile int exynos_pen_release = -1;
+
 #ifdef CONFIG_HOTPLUG_CPU
 static inline void cpu_leave_lowpower(u32 core_id)
 {
@@ -57,7 +60,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 
                 wfi();
 
-                if (pen_release == core_id) {
+                if (exynos_pen_release == core_id) {
                         /*
                          * OK, proper wakeup, we're done
                          */
@@ -228,15 +231,17 @@ void exynos_core_restart(u32 core_id)
 }
 
 /*
- * Write pen_release in a way that is guaranteed to be visible to all
- * observers, irrespective of whether they're taking part in coherency
+ * XXX CARGO CULTED CODE - DO NOT COPY XXX
+ *
+ * Write exynos_pen_release in a way that is guaranteed to be visible to
+ * all observers, irrespective of whether they're taking part in coherency
  * or not.  This is necessary for the hotplug code to work reliably.
  */
-static void write_pen_release(int val)
+static void exynos_write_pen_release(int val)
 {
-        pen_release = val;
+        exynos_pen_release = val;
         smp_wmb();
-        sync_cache_w(&pen_release);
+        sync_cache_w(&exynos_pen_release);
 }
 
 static DEFINE_SPINLOCK(boot_lock);
@@ -247,7 +252,7 @@ static void exynos_secondary_init(unsigned int cpu)
          * let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
-        write_pen_release(-1);
+        exynos_write_pen_release(-1);
 
         /*
          * Synchronise with the boot thread.
@@ -322,12 +327,12 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
         /*
          * The secondary processor is waiting to be released from
          * the holding pen - release it, then wait for it to flag
-         * that it has been released by resetting pen_release.
+         * that it has been released by resetting exynos_pen_release.
          *
-         * Note that "pen_release" is the hardware CPU core ID, whereas
+         * Note that "exynos_pen_release" is the hardware CPU core ID, whereas
          * "cpu" is Linux's internal ID.
          */
-        write_pen_release(core_id);
+        exynos_write_pen_release(core_id);
 
         if (!exynos_cpu_power_state(core_id)) {
                 exynos_cpu_power_up(core_id);
@@ -336,9 +341,9 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
                 /* wait max 10 ms until cpu1 is on */
                 while (exynos_cpu_power_state(core_id)
                        != S5P_CORE_LOCAL_PWR_EN) {
-                        if (timeout-- == 0)
+                        if (timeout == 0)
                                 break;
-
+                        timeout--;
                         mdelay(1);
                 }
 
@@ -376,13 +381,13 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
                 else
                         arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 
-                if (pen_release == -1)
+                if (exynos_pen_release == -1)
                         break;
 
                 udelay(10);
         }
 
-        if (pen_release != -1)
+        if (exynos_pen_release != -1)
                 ret = -ETIMEDOUT;
 
         /*
@@ -392,7 +397,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
 fail:
         spin_unlock(&boot_lock);
 
-        return pen_release != -1 ? ret : 0;
+        return exynos_pen_release != -1 ? ret : 0;
 }
 
 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 8af2f7e91d13..35ff620537e6 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -29,9 +29,10 @@ obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o
 obj-$(CONFIG_SOC_IMX6SLL) += cpuidle-imx6sx.o
 obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o
 obj-$(CONFIG_SOC_IMX6UL) += cpuidle-imx6sx.o
+obj-$(CONFIG_SOC_IMX7ULP) += cpuidle-imx7ulp.o
 endif
 
-ifdef CONFIG_SND_IMX_SOC
+ifdef CONFIG_SND_SOC_IMX_PCM_FIQ
 obj-y += ssi-fiq.o
 obj-y += ssi-fiq-ksym.o
 endif
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index bc915e5b4d56..c51764a85fd7 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -72,6 +72,15 @@ enum mxc_cpu_pwr_mode {
         STOP_POWER_OFF,         /* STOP + SRPG */
 };
 
+enum ulp_cpu_pwr_mode {
+        ULP_PM_HSRUN,    /* High speed run mode */
+        ULP_PM_RUN,      /* Run mode */
+        ULP_PM_WAIT,     /* Wait mode */
+        ULP_PM_STOP,     /* Stop mode */
+        ULP_PM_VLPS,     /* Very low power stop mode */
+        ULP_PM_VLLS,     /* very low leakage stop mode */
+};
+
 void imx_enable_cpu(int cpu, bool enable);
 void imx_set_cpu_jump(int cpu, void *jump_addr);
 u32 imx_get_cpu_arg(int cpu);
@@ -98,6 +107,7 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
 void imx6_set_int_mem_clk_lpm(bool enable);
 void imx6sl_set_wait_clk(bool enter);
 int imx_mmdc_get_ddr_type(void);
+int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode);
 
 void imx_cpu_die(unsigned int cpu);
 int imx_cpu_kill(unsigned int cpu);
diff --git a/arch/arm/mach-imx/cpuidle-imx7ulp.c b/arch/arm/mach-imx/cpuidle-imx7ulp.c
new file mode 100644
index 000000000000..ca86c967d19e
--- /dev/null
+++ b/arch/arm/mach-imx/cpuidle-imx7ulp.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *   Anson Huang <Anson.Huang@nxp.com>
+ */
+
+#include <linux/cpuidle.h>
+#include <linux/module.h>
+#include <asm/cpuidle.h>
+
+#include "common.h"
+#include "cpuidle.h"
+
+static int imx7ulp_enter_wait(struct cpuidle_device *dev,
+                            struct cpuidle_driver *drv, int index)
+{
+        if (index == 1)
+                imx7ulp_set_lpm(ULP_PM_WAIT);
+        else
+                imx7ulp_set_lpm(ULP_PM_STOP);
+
+        cpu_do_idle();
+
+        imx7ulp_set_lpm(ULP_PM_RUN);
+
+        return index;
+}
+
+static struct cpuidle_driver imx7ulp_cpuidle_driver = {
+        .name = "imx7ulp_cpuidle",
+        .owner = THIS_MODULE,
+        .states = {
+                /* WFI */
+                ARM_CPUIDLE_WFI_STATE,
+                /* WAIT */
+                {
+                        .exit_latency = 50,
+                        .target_residency = 75,
+                        .enter = imx7ulp_enter_wait,
+                        .name = "WAIT",
+                        .desc = "PSTOP2",
+                },
+                /* STOP */
+                {
+                        .exit_latency = 100,
+                        .target_residency = 150,
+                        .enter = imx7ulp_enter_wait,
+                        .name = "STOP",
+                        .desc = "PSTOP1",
+                },
+        },
+        .state_count = 3,
+        .safe_state_index = 0,
+};
+
+int __init imx7ulp_cpuidle_init(void)
+{
+        return cpuidle_register(&imx7ulp_cpuidle_driver, NULL);
+}
diff --git a/arch/arm/mach-imx/cpuidle.h b/arch/arm/mach-imx/cpuidle.h
index f9140128ba05..7694c8f810a4 100644
--- a/arch/arm/mach-imx/cpuidle.h
+++ b/arch/arm/mach-imx/cpuidle.h
@@ -15,6 +15,7 @@ extern int imx5_cpuidle_init(void);
 extern int imx6q_cpuidle_init(void);
 extern int imx6sl_cpuidle_init(void);
 extern int imx6sx_cpuidle_init(void);
+extern int imx7ulp_cpuidle_init(void);
 #else
 static inline int imx5_cpuidle_init(void)
 {
@@ -32,4 +33,8 @@ static inline int imx6sx_cpuidle_init(void)
 {
         return 0;
 }
+static inline int imx7ulp_cpuidle_init(void)
+{
+        return 0;
+}
 #endif
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 5169dfba9718..07d4fcfe5c2e 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -258,8 +258,7 @@ static void __init visstrim_analog_camera_init(void)
                 return;
 
         dma_declare_coherent_memory(&pdev->dev, mx2_camera_base,
-                                    mx2_camera_base, MX2_CAMERA_BUF_SIZE,
-                                    DMA_MEMORY_EXCLUSIVE);
+                                    mx2_camera_base, MX2_CAMERA_BUF_SIZE);
 }
 
 static void __init visstrim_reserve(void)
@@ -445,8 +444,7 @@ static void __init visstrim_coda_init(void)
         dma_declare_coherent_memory(&pdev->dev,
                                     mx2_camera_base + MX2_CAMERA_BUF_SIZE,
                                     mx2_camera_base + MX2_CAMERA_BUF_SIZE,
-                                    MX2_CAMERA_BUF_SIZE,
-                                    DMA_MEMORY_EXCLUSIVE);
+                                    MX2_CAMERA_BUF_SIZE);
 }
 
 /* DMA deinterlace */
@@ -465,8 +463,7 @@ static void __init visstrim_deinterlace_init(void)
         dma_declare_coherent_memory(&pdev->dev,
                                     mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE,
                                     mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE,
-                                    MX2_CAMERA_BUF_SIZE,
-                                    DMA_MEMORY_EXCLUSIVE);
+                                    MX2_CAMERA_BUF_SIZE);
 }
 
 /* Emma-PrP for format conversion */
@@ -485,8 +482,7 @@ static void __init visstrim_emmaprp_init(void)
          */
         ret = dma_declare_coherent_memory(&pdev->dev,
                                 mx2_camera_base, mx2_camera_base,
-                                MX2_CAMERA_BUF_SIZE,
-                                DMA_MEMORY_EXCLUSIVE);
+                                MX2_CAMERA_BUF_SIZE);
         if (ret)
                 pr_err("Failed to declare memory for emmaprp\n");
 }
diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c
index 33937ebf66b5..11ac71aaf965 100644
--- a/arch/arm/mach-imx/mach-imx7ulp.c
+++ b/arch/arm/mach-imx/mach-imx7ulp.c
@@ -6,17 +6,57 @@
  */
 
 #include <linux/irqchip.h>
+#include <linux/mfd/syscon.h>
 #include <linux/of_platform.h>
+#include <linux/regmap.h>
 #include <asm/mach/arch.h>
 
 #include "common.h"
+#include "cpuidle.h"
 #include "hardware.h"
 
+#define SIM_JTAG_ID_REG         0x8c
+
+static void __init imx7ulp_set_revision(void)
+{
+        struct regmap *sim;
+        u32 revision;
+
+        sim = syscon_regmap_lookup_by_compatible("fsl,imx7ulp-sim");
+        if (IS_ERR(sim)) {
+                pr_warn("failed to find fsl,imx7ulp-sim regmap!\n");
+                return;
+        }
+
+        if (regmap_read(sim, SIM_JTAG_ID_REG, &revision)) {
+                pr_warn("failed to read sim regmap!\n");
+                return;
+        }
+
+        /*
+         * bit[31:28] of JTAG_ID register defines revision as below from B0:
+         * 0001        B0
+         * 0010        B1
+         */
+        switch (revision >> 28) {
+        case 1:
+                imx_set_soc_revision(IMX_CHIP_REVISION_2_0);
+                break;
+        case 2:
+                imx_set_soc_revision(IMX_CHIP_REVISION_2_1);
+                break;
+        default:
+                imx_set_soc_revision(IMX_CHIP_REVISION_1_0);
+                break;
+        }
+}
+
 static void __init imx7ulp_init_machine(void)
 {
         imx7ulp_pm_init();
 
         mxc_set_cpu_type(MXC_CPU_IMX7ULP);
+        imx7ulp_set_revision();
         of_platform_default_populate(NULL, NULL, imx_soc_device_init());
 }
 
@@ -25,7 +65,13 @@ static const char *const imx7ulp_dt_compat[] __initconst = {
         NULL,
 };
 
+static void __init imx7ulp_init_late(void)
+{
+        imx7ulp_cpuidle_init();
+}
+
 DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)")
         .init_machine   = imx7ulp_init_machine,
         .dt_compat      = imx7ulp_dt_compat,
+        .init_late      = imx7ulp_init_late,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 2e1e540f2e5a..d278fb672d40 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -205,7 +205,6 @@ static struct regulator_init_data mx21ads_lcd_regulator_init_data = {
 static struct fixed_voltage_config mx21ads_lcd_regulator_pdata = {
         .supply_name    = "LCD",
         .microvolts     = 3300000,
-        .enable_high    = 1,
         .init_data      = &mx21ads_lcd_regulator_init_data,
 };
 
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index f5e04047ed13..6dd7f57c332f 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -237,7 +237,7 @@ static struct fixed_voltage_config mx27ads_lcd_regulator_pdata = {
 static struct gpiod_lookup_table mx27ads_lcd_regulator_gpiod_table = {
         .dev_id = "reg-fixed-voltage.0", /* Let's hope ID 0 is what we get */
         .table = {
-                GPIO_LOOKUP("LCD", 0, NULL, GPIO_ACTIVE_HIGH),
+                GPIO_LOOKUP("LCD", 0, NULL, GPIO_ACTIVE_LOW),
                 { },
         },
 };
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index 643a3d749703..fe50f4cf00a7 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -475,8 +475,7 @@ static int __init mx31moboard_init_cam(void)
 
         ret = dma_declare_coherent_memory(&pdev->dev,
                                           mx3_camera_base, mx3_camera_base,
-                                          MX3_CAMERA_BUF_SIZE,
-                                          DMA_MEMORY_EXCLUSIVE);
+                                          MX3_CAMERA_BUF_SIZE);
         if (ret)
                 goto err;
 
diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c
index e49e06834516..fce4b426c379 100644
--- a/arch/arm/mach-imx/mmdc.c
+++ b/arch/arm/mach-imx/mmdc.c
@@ -294,13 +294,7 @@ static int mmdc_pmu_event_init(struct perf_event *event)
                 return -EOPNOTSUPP;
         }
 
-        if (event->attr.exclude_user            ||
-                        event->attr.exclude_kernel      ||
-                        event->attr.exclude_hv          ||
-                        event->attr.exclude_idle        ||
-                        event->attr.exclude_host        ||
-                        event->attr.exclude_guest       ||
-                        event->attr.sample_period)
+        if (event->attr.sample_period)
                 return -EINVAL;
 
         if (cfg < 0 || cfg >= MMDC_NUM_COUNTERS)
@@ -456,6 +450,7 @@ static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc,
                         .start          = mmdc_pmu_event_start,
                         .stop           = mmdc_pmu_event_stop,
                         .read           = mmdc_pmu_event_update,
+                        .capabilities   = PERF_PMU_CAP_NO_EXCLUDE,
                 },
                 .mmdc_base = mmdc_base,
                 .dev = dev,
diff --git a/arch/arm/mach-imx/pm-imx7ulp.c b/arch/arm/mach-imx/pm-imx7ulp.c
index cf6a380c2b8d..7b2f7387e662 100644
--- a/arch/arm/mach-imx/pm-imx7ulp.c
+++ b/arch/arm/mach-imx/pm-imx7ulp.c
@@ -9,21 +9,60 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 
+#include "common.h"
+
 #define SMC_PMCTRL              0x10
 #define BP_PMCTRL_PSTOPO        16
 #define PSTOPO_PSTOP3           0x3
+#define PSTOPO_PSTOP2           0x2
+#define PSTOPO_PSTOP1           0x1
+#define BP_PMCTRL_RUNM          8
+#define RUNM_RUN                0
+#define BP_PMCTRL_STOPM         0
+#define STOPM_STOP              0
+
+#define BM_PMCTRL_PSTOPO        (3 << BP_PMCTRL_PSTOPO)
+#define BM_PMCTRL_RUNM          (3 << BP_PMCTRL_RUNM)
+#define BM_PMCTRL_STOPM         (7 << BP_PMCTRL_STOPM)
+
+static void __iomem *smc1_base;
+
+int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode)
+{
+        u32 val = readl_relaxed(smc1_base + SMC_PMCTRL);
+
+        /* clear all */
+        val &= ~(BM_PMCTRL_RUNM | BM_PMCTRL_STOPM | BM_PMCTRL_PSTOPO);
+
+        switch (mode) {
+        case ULP_PM_RUN:
+                /* system/bus clock enabled */
+                val |= PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO;
+                break;
+        case ULP_PM_WAIT:
+                /* system clock disabled, bus clock enabled */
+                val |= PSTOPO_PSTOP2 << BP_PMCTRL_PSTOPO;
+                break;
+        case ULP_PM_STOP:
+                /* system/bus clock disabled */
+                val |= PSTOPO_PSTOP1 << BP_PMCTRL_PSTOPO;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        writel_relaxed(val, smc1_base + SMC_PMCTRL);
+
+        return 0;
+}
 
 void __init imx7ulp_pm_init(void)
 {
         struct device_node *np;
-        void __iomem *smc1_base;
 
         np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1");
         smc1_base = of_iomap(np, 0);
         WARN_ON(!smc1_base);
 
-        /* Partial Stop mode 3 with system/bus clock enabled */
-        writel_relaxed(PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO,
-                       smc1_base + SMC_PMCTRL);
-        iounmap(smc1_base);
+        imx7ulp_set_lpm(ULP_PM_RUN);
 }
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index a109f6482413..8dfad012dfae 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -390,10 +390,14 @@ static int __ref impd1_probe(struct lm_device *dev)
                         char *mmciname;
 
                         lookup = devm_kzalloc(&dev->dev,
-                                              sizeof(*lookup) + 3 * sizeof(struct gpiod_lookup),
+                                              struct_size(lookup, table, 3),
                                               GFP_KERNEL);
                         chipname = devm_kstrdup(&dev->dev, devname, GFP_KERNEL);
-                        mmciname = kasprintf(GFP_KERNEL, "lm%x:00700", dev->id);
+                        mmciname = devm_kasprintf(&dev->dev, GFP_KERNEL,
+                                                  "lm%x:00700", dev->id);
+                        if (!lookup || !chipname || !mmciname)
+                                return -ENOMEM;
+
                         lookup->dev_id = mmciname;
                         /*
                          * Offsets on GPIO block 1:
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index 3b73813c6b04..23e8c93515d4 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -75,8 +75,7 @@ void __init n2100_map_io(void)
 /*
  * N2100 PCI.
  */
-static int __init
-n2100_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+static int n2100_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
         int irq;
 
diff --git a/arch/arm/mach-ks8695/include/mach/entry-macro.S b/arch/arm/mach-ks8695/include/mach/entry-macro.S
index 8315b34f32ff..7ff812cb010b 100644
--- a/arch/arm/mach-ks8695/include/mach/entry-macro.S
+++ b/arch/arm/mach-ks8695/include/mach/entry-macro.S
@@ -42,6 +42,6 @@
                 moveq   \irqstat, \irqstat, lsr #2
                 addeq   \irqnr, \irqnr, #2
                 tst     \irqstat, #0x01
-                addeqs  \irqnr, \irqnr, #1
+                addseq  \irqnr, \irqnr, #1
 1001:
         .endm
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index e48cc06c2aec..b3be60a8e467 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -45,73 +45,6 @@
 #include <mach/board.h>
 #include "common.h"
 
-/*
- * AMBA LCD controller
- */
-static struct clcd_panel conn_lcd_panel = {
-        .mode           = {
-                .name           = "QVGA portrait",
-                .refresh        = 60,
-                .xres           = 240,
-                .yres           = 320,
-                .pixclock       = 191828,
-                .left_margin    = 22,
-                .right_margin   = 11,
-                .upper_margin   = 2,
-                .lower_margin   = 1,
-                .hsync_len      = 5,
-                .vsync_len      = 2,
-                .sync           = 0,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-        .width          = -1,
-        .height         = -1,
-        .tim2           = (TIM2_IVS | TIM2_IHS),
-        .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
-                                CNTL_LCDBPP16_565),
-        .bpp            = 16,
-};
-#define PANEL_SIZE (3 * SZ_64K)
-
-static int lpc32xx_clcd_setup(struct clcd_fb *fb)
-{
-        dma_addr_t dma;
-
-        fb->fb.screen_base = dma_alloc_wc(&fb->dev->dev, PANEL_SIZE, &dma,
-                                          GFP_KERNEL);
-        if (!fb->fb.screen_base) {
-                printk(KERN_ERR "CLCD: unable to map framebuffer\n");
-                return -ENOMEM;
-        }
-
-        fb->fb.fix.smem_start = dma;
-        fb->fb.fix.smem_len = PANEL_SIZE;
-        fb->panel = &conn_lcd_panel;
-
-        return 0;
-}
-
-static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
-{
-        return dma_mmap_wc(&fb->dev->dev, vma, fb->fb.screen_base,
-                           fb->fb.fix.smem_start, fb->fb.fix.smem_len);
-}
-
-static void lpc32xx_clcd_remove(struct clcd_fb *fb)
-{
-        dma_free_wc(&fb->dev->dev, fb->fb.fix.smem_len, fb->fb.screen_base,
-                    fb->fb.fix.smem_start);
-}
-
-static struct clcd_board lpc32xx_clcd_data = {
-        .name           = "Phytec LCD",
-        .check          = clcdfb_check,
-        .decode         = clcdfb_decode,
-        .setup          = lpc32xx_clcd_setup,
-        .mmap           = lpc32xx_clcd_mmap,
-        .remove         = lpc32xx_clcd_remove,
-};
-
 static struct pl08x_channel_data pl08x_slave_channels[] = {
         {
                 .bus_id = "nand-slc",
@@ -148,11 +81,6 @@ static struct pl08x_platform_data pl08x_pd = {
         .mem_buses = PL08X_AHB1,
 };
 
-static struct mmci_platform_data lpc32xx_mmci_data = {
-        .ocr_mask       = MMC_VDD_30_31 | MMC_VDD_31_32 |
-                          MMC_VDD_32_33 | MMC_VDD_33_34,
-};
-
 static struct lpc32xx_slc_platform_data lpc32xx_slc_data = {
         .dma_filter = pl08x_filter_id,
 };
@@ -164,10 +92,7 @@ static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = {
 static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
         OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", NULL),
         OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", NULL),
-        OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
         OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
-        OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd",
-                       &lpc32xx_mmci_data),
         OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash",
                        &lpc32xx_slc_data),
         OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
@@ -177,15 +102,6 @@ static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
 
 static void __init lpc3250_machine_init(void)
 {
-        u32 tmp;
-
-        /* Setup LCD muxing to RGB565 */
-        tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
-                ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
-                LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
-        tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
-        __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
-
         lpc32xx_serial_init();
 
         /* Test clock needed for UDA1380 initial init */
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
index 62471570d586..32bca351a73b 100644
--- a/arch/arm/mach-lpc32xx/pm.c
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -86,17 +86,10 @@ static int lpc32xx_pm_enter(suspend_state_t state)
         void *iram_swap_area;
 
         /* Allocate some space for temporary IRAM storage */
-        iram_swap_area = kmalloc(lpc32xx_sys_suspend_sz, GFP_KERNEL);
-        if (!iram_swap_area) {
-                printk(KERN_ERR
-                       "PM Suspend: cannot allocate memory to save portion "
-                        "of SRAM\n");
+        iram_swap_area = kmemdup((void *)TEMP_IRAM_AREA,
+                                 lpc32xx_sys_suspend_sz, GFP_KERNEL);
+        if (!iram_swap_area)
                 return -ENOMEM;
-        }
-
-        /* Backup a small area of IRAM used for the suspend code */
-        memcpy(iram_swap_area, (void *) TEMP_IRAM_AREA,
-                lpc32xx_sys_suspend_sz);
 
         /*
          * Copy code to suspend system into IRAM. The suspend code
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 91cc461f7b04..11ed264f0731 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -26,6 +26,10 @@ config MACH_MT7623
         bool "MediaTek MT7623 SoCs support"
         default ARCH_MEDIATEK
 
+config MACH_MT7629
+        bool "MediaTek MT7629 SoCs support"
+        default ARCH_MEDIATEK
+
 config MACH_MT8127
         bool "MediaTek MT8127 SoCs support"
         default ARCH_MEDIATEK
diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
index 6910b4e0d913..b6a81ba1ce32 100644
--- a/arch/arm/mach-mediatek/mediatek.c
+++ b/arch/arm/mach-mediatek/mediatek.c
@@ -30,7 +30,6 @@ static void __init mediatek_timer_init(void)
 
         if (of_machine_is_compatible("mediatek,mt6589") ||
             of_machine_is_compatible("mediatek,mt7623") ||
-            of_machine_is_compatible("mediatek,mt7623a") ||
             of_machine_is_compatible("mediatek,mt8135") ||
             of_machine_is_compatible("mediatek,mt8127")) {
                 /* turn on GPT6 which ungates arch timer clocks */
@@ -50,7 +49,7 @@ static const char * const mediatek_board_dt_compat[] = {
         "mediatek,mt6589",
         "mediatek,mt6592",
         "mediatek,mt7623",
-        "mediatek,mt7623a",
+        "mediatek,mt7629",
         "mediatek,mt8127",
         "mediatek,mt8135",
         NULL,
diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c
index 6882ff07aaa6..c9d7c0458452 100644
--- a/arch/arm/mach-mediatek/platsmp.c
+++ b/arch/arm/mach-mediatek/platsmp.c
@@ -60,7 +60,7 @@ static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = {
 static const struct of_device_id mtk_smp_boot_infos[] __initconst = {
         { .compatible   = "mediatek,mt6589", .data = &mtk_mt6589_boot },
         { .compatible   = "mediatek,mt7623", .data = &mtk_mt7623_boot },
-        { .compatible   = "mediatek,mt7623a", .data = &mtk_mt7623_boot },
+        { .compatible   = "mediatek,mt7629", .data = &mtk_mt7623_boot },
         {},
 };
 
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index b16831697183..15e9cb75738e 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -9,7 +9,6 @@ menuconfig ARCH_MESON
         select PINCTRL
         select PINCTRL_MESON
         select COMMON_CLK
-        select COMMON_CLK_AMLOGIC
         select HAVE_ARM_SCU if SMP
         select HAVE_ARM_TWD if SMP
 
diff --git a/arch/arm/mach-milbeaut/Kconfig b/arch/arm/mach-milbeaut/Kconfig
new file mode 100644
index 000000000000..6a576fd8521e
--- /dev/null
+++ b/arch/arm/mach-milbeaut/Kconfig
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0
+menuconfig ARCH_MILBEAUT
+        bool "Socionext Milbeaut SoCs"
+        depends on ARCH_MULTI_V7
+        select ARM_GIC
+        help
+          This enables support for Socionext Milbeaut SoCs
+
+if ARCH_MILBEAUT
+
+config ARCH_MILBEAUT_M10V
+        bool "Milbeaut SC2000/M10V platform"
+        select ARM_ARCH_TIMER
+        select MILBEAUT_TIMER
+        select PINCTRL
+        select PINCTRL_MILBEAUT
+        help
+          Support for Socionext's MILBEAUT M10V based systems
+
+endif
diff --git a/arch/arm/mach-milbeaut/Makefile b/arch/arm/mach-milbeaut/Makefile
new file mode 100644
index 000000000000..ce5ea062047a
--- /dev/null
+++ b/arch/arm/mach-milbeaut/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-milbeaut/platsmp.c b/arch/arm/mach-milbeaut/platsmp.c
new file mode 100644
index 000000000000..591543c81399
--- /dev/null
+++ b/arch/arm/mach-milbeaut/platsmp.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright:   (C) 2018 Socionext Inc.
+ * Copyright:   (C) 2015 Linaro Ltd.
+ */
+
+#include <linux/cpu_pm.h>
+#include <linux/irqchip/arm-gic.h>
+#include <linux/of_address.h>
+#include <linux/suspend.h>
+
+#include <asm/cacheflush.h>
+#include <asm/cp15.h>
+#include <asm/idmap.h>
+#include <asm/smp_plat.h>
+#include <asm/suspend.h>
+
+#define M10V_MAX_CPU    4
+#define KERNEL_UNBOOT_FLAG      0x12345678
+
+static void __iomem *m10v_smp_base;
+
+static int m10v_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
+{
+        unsigned int mpidr, cpu, cluster;
+
+        if (!m10v_smp_base)
+                return -ENXIO;
+
+        mpidr = cpu_logical_map(l_cpu);
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+        if (cpu >= M10V_MAX_CPU)
+                return -EINVAL;
+
+        pr_info("%s: cpu %u l_cpu %u cluster %u\n",
+                        __func__, cpu, l_cpu, cluster);
+
+        writel(__pa_symbol(secondary_startup), m10v_smp_base + cpu * 4);
+        arch_send_wakeup_ipi_mask(cpumask_of(l_cpu));
+
+        return 0;
+}
+
+static void m10v_smp_init(unsigned int max_cpus)
+{
+        unsigned int mpidr, cpu, cluster;
+        struct device_node *np;
+
+        np = of_find_compatible_node(NULL, NULL, "socionext,milbeaut-smp-sram");
+        if (!np)
+                return;
+
+        m10v_smp_base = of_iomap(np, 0);
+        if (!m10v_smp_base)
+                return;
+
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+        pr_info("MCPM boot on cpu_%u cluster_%u\n", cpu, cluster);
+
+        for (cpu = 0; cpu < M10V_MAX_CPU; cpu++)
+                writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4);
+}
+
+static void m10v_cpu_die(unsigned int l_cpu)
+{
+        gic_cpu_if_down(0);
+        v7_exit_coherency_flush(louis);
+        wfi();
+}
+
+static int m10v_cpu_kill(unsigned int l_cpu)
+{
+        unsigned int mpidr, cpu;
+
+        mpidr = cpu_logical_map(l_cpu);
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+
+        writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4);
+
+        return 1;
+}
+
+static struct smp_operations m10v_smp_ops __initdata = {
+        .smp_prepare_cpus       = m10v_smp_init,
+        .smp_boot_secondary     = m10v_boot_secondary,
+        .cpu_die                = m10v_cpu_die,
+        .cpu_kill               = m10v_cpu_kill,
+};
+CPU_METHOD_OF_DECLARE(m10v_smp, "socionext,milbeaut-m10v-smp", &m10v_smp_ops);
+
+static int m10v_pm_valid(suspend_state_t state)
+{
+        return (state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM);
+}
+
+typedef void (*phys_reset_t)(unsigned long);
+static phys_reset_t phys_reset;
+
+static int m10v_die(unsigned long arg)
+{
+        setup_mm_for_reboot();
+        asm("wfi");
+        /* Boot just like a secondary */
+        phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
+        phys_reset(virt_to_phys(cpu_resume));
+
+        return 0;
+}
+
+static int m10v_pm_enter(suspend_state_t state)
+{
+        switch (state) {
+        case PM_SUSPEND_STANDBY:
+                asm("wfi");
+                break;
+        case PM_SUSPEND_MEM:
+                cpu_pm_enter();
+                cpu_suspend(0, m10v_die);
+                cpu_pm_exit();
+                break;
+        }
+        return 0;
+}
+
+static const struct platform_suspend_ops m10v_pm_ops = {
+        .valid          = m10v_pm_valid,
+        .enter          = m10v_pm_enter,
+};
+
+struct clk *m10v_clclk_register(struct device *cpu_dev);
+
+static int __init m10v_pm_init(void)
+{
+        if (of_machine_is_compatible("socionext,milbeaut-evb"))
+                suspend_set_ops(&m10v_pm_ops);
+
+        return 0;
+}
+late_initcall(m10v_pm_init);
diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c
index a04e249c654b..d2560fb1e835 100644
--- a/arch/arm/mach-mmp/brownstone.c
+++ b/arch/arm/mach-mmp/brownstone.c
@@ -149,7 +149,6 @@ static struct regulator_init_data brownstone_v_5vp_data = {
 static struct fixed_voltage_config brownstone_v_5vp = {
         .supply_name            = "v_5vp",
         .microvolts             = 5000000,
-        .enable_high            = 1,
         .enabled_at_boot        = 1,
         .init_data              = &brownstone_v_5vp_data,
 };
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index c4c0a8ea11e4..be30c3c061b4 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -267,7 +267,6 @@ static struct fixed_voltage_config modem_nreset_config = {
         .supply_name            = "modem_nreset",
         .microvolts             = 3300000,
         .startup_delay          = 25000,
-        .enable_high            = 1,
         .enabled_at_boot        = 1,
         .init_data              = &modem_nreset_data,
 };
@@ -533,7 +532,6 @@ static struct regulator_init_data keybrd_pwr_initdata = {
 static struct fixed_voltage_config keybrd_pwr_config = {
         .supply_name            = "keybrd_pwr",
         .microvolts             = 5000000,
-        .enable_high            = 1,
         .init_data              = &keybrd_pwr_initdata,
 };
 
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index eb41db78cd47..10848f573d37 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -10,6 +10,7 @@
 #include <linux/clkdev.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
+#include <linux/gpio/machine.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/mutex.h>
@@ -25,7 +26,6 @@
 #include <linux/platform_data/keypad-omap.h>
 #include <linux/platform_data/lcd-mipid.h>
 #include <linux/platform_data/gpio-omap.h>
-#include <linux/platform_data/i2c-cbus-gpio.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -217,18 +217,19 @@ static inline void nokia770_mmc_init(void)
 #endif
 
 #if IS_ENABLED(CONFIG_I2C_CBUS_GPIO)
-static struct i2c_cbus_platform_data nokia770_cbus_data = {
-        .clk_gpio = OMAP_MPUIO(9),
-        .dat_gpio = OMAP_MPUIO(10),
-        .sel_gpio = OMAP_MPUIO(11),
+static struct gpiod_lookup_table nokia770_cbus_gpio_table = {
+        .dev_id = "i2c-cbus-gpio.2",
+        .table = {
+                GPIO_LOOKUP_IDX("mpuio", 9, NULL, 0, 0), /* clk */
+                GPIO_LOOKUP_IDX("mpuio", 10, NULL, 1, 0), /* dat */
+                GPIO_LOOKUP_IDX("mpuio", 11, NULL, 2, 0), /* sel */
+                { },
+        },
 };
 
 static struct platform_device nokia770_cbus_device = {
         .name   = "i2c-cbus-gpio",
         .id     = 2,
-        .dev    = {
-                .platform_data = &nokia770_cbus_data,
-        },
 };
 
 static struct i2c_board_info nokia770_i2c_board_info_2[] __initdata = {
@@ -257,6 +258,7 @@ static void __init nokia770_cbus_init(void)
         nokia770_i2c_board_info_2[1].irq = gpio_to_irq(tahvo_irq_gpio);
         i2c_register_board_info(2, nokia770_i2c_board_info_2,
                                 ARRAY_SIZE(nokia770_i2c_board_info_2));
+        gpiod_add_lookup_table(&nokia770_cbus_gpio_table);
         platform_device_register(&nokia770_cbus_device);
 }
 #else /* CONFIG_I2C_CBUS_GPIO */
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index a8b291f00109..dae514c8276a 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -152,6 +152,10 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
         mpuss_can_lose_context = (cx->mpu_state == PWRDM_POWER_RET) &&
                                  (cx->mpu_logic_state == PWRDM_POWER_OFF);
 
+        /* Enter broadcast mode for periodic timers */
+        tick_broadcast_enable();
+
+        /* Enter broadcast mode for one-shot timers */
         tick_broadcast_enter();
 
         /*
@@ -218,15 +222,6 @@ fail:
         return index;
 }
 
-/*
- * For each cpu, setup the broadcast timer because local timers
- * stops for the states above C1.
- */
-static void omap_setup_broadcast_timer(void *arg)
-{
-        tick_broadcast_enable();
-}
-
 static struct cpuidle_driver omap4_idle_driver = {
         .name                           = "omap4_idle",
         .owner                          = THIS_MODULE,
@@ -319,8 +314,5 @@ int __init omap4_idle_init(void)
         if (!cpu_clkdm[0] || !cpu_clkdm[1])
                 return -ENODEV;
 
-        /* Configure the broadcast timer on each cpu */
-        on_each_cpu(omap_setup_broadcast_timer, NULL, 1);
-
         return cpuidle_register(idle_driver, cpu_online_mask);
 }
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index f86b72d1d59e..1444b4b4bd9f 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -83,6 +83,7 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
         u32 enable_mask, enable_shift;
         u32 pipd_mask, pipd_shift;
         u32 reg;
+        int ret;
 
         if (dsi_id == 0) {
                 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
@@ -98,7 +99,11 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
                 return -ENODEV;
         }
 
-        regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, &reg);
+        ret = regmap_read(omap4_dsi_mux_syscon,
+                                          OMAP4_DSIPHY_SYSCON_OFFSET,
+                                          &reg);
+        if (ret)
+                return ret;
 
         reg &= ~enable_mask;
         reg &= ~pipd_mask;
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index fc5fb776a710..17558be4bf0a 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -50,6 +50,9 @@
 #define OMAP4_NR_BANKS          4
 #define OMAP4_NR_IRQS           128
 
+#define SYS_NIRQ1_EXT_SYS_IRQ_1 7
+#define SYS_NIRQ2_EXT_SYS_IRQ_2 119
+
 static void __iomem *wakeupgen_base;
 static void __iomem *sar_base;
 static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
@@ -153,6 +156,37 @@ static void wakeupgen_unmask(struct irq_data *d)
         irq_chip_unmask_parent(d);
 }
 
+/*
+ * The sys_nirq pins bypass peripheral modules and are wired directly
+ * to MPUSS wakeupgen. They get automatically inverted for GIC.
+ */
+static int wakeupgen_irq_set_type(struct irq_data *d, unsigned int type)
+{
+        bool inverted = false;
+
+        switch (type) {
+        case IRQ_TYPE_LEVEL_LOW:
+                type &= ~IRQ_TYPE_LEVEL_MASK;
+                type |= IRQ_TYPE_LEVEL_HIGH;
+                inverted = true;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                type &= ~IRQ_TYPE_EDGE_BOTH;
+                type |= IRQ_TYPE_EDGE_RISING;
+                inverted = true;
+                break;
+        default:
+                break;
+        }
+
+        if (inverted && d->hwirq != SYS_NIRQ1_EXT_SYS_IRQ_1 &&
+            d->hwirq != SYS_NIRQ2_EXT_SYS_IRQ_2)
+                pr_warn("wakeupgen: irq%li polarity inverted in dts\n",
+                        d->hwirq);
+
+        return irq_chip_set_type_parent(d, type);
+}
+
 #ifdef CONFIG_HOTPLUG_CPU
 static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
 
@@ -446,7 +480,7 @@ static struct irq_chip wakeupgen_chip = {
         .irq_mask               = wakeupgen_mask,
         .irq_unmask             = wakeupgen_unmask,
         .irq_retrigger          = irq_chip_retrigger_hierarchy,
-        .irq_set_type           = irq_chip_set_type_parent,
+        .irq_set_type           = wakeupgen_irq_set_type,
         .flags                  = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
 #ifdef CONFIG_SMP
         .irq_set_affinity       = irq_chip_set_affinity_parent,
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index b5531dd3ae9c..3a04c73ac03c 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1002,8 +1002,10 @@ static int _enable_clocks(struct omap_hwmod *oh)
                 clk_enable(oh->_clk);
 
         list_for_each_entry(os, &oh->slave_ports, node) {
-                if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
+                if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) {
+                        omap2_clk_deny_idle(os->_clk);
                         clk_enable(os->_clk);
+                }
         }
 
         /* The opt clocks are controlled by the device driver. */
@@ -1055,8 +1057,10 @@ static int _disable_clocks(struct omap_hwmod *oh)
                 clk_disable(oh->_clk);
 
         list_for_each_entry(os, &oh->slave_ports, node) {
-                if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
+                if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) {
                         clk_disable(os->_clk);
+                        omap2_clk_allow_idle(os->_clk);
+                }
         }
 
         if (oh->flags & HWMOD_OPT_CLKS_NEEDED)
@@ -2436,9 +2440,13 @@ static void _setup_iclk_autoidle(struct omap_hwmod *oh)
                         continue;
 
                 if (os->flags & OCPIF_SWSUP_IDLE) {
-                        /* XXX omap_iclk_deny_idle(c); */
+                        /*
+                         * we might have multiple users of one iclk with
+                         * different requirements, disable autoidle when
+                         * the module is enabled, e.g. dss iclk
+                         */
                 } else {
-                        /* XXX omap_iclk_allow_idle(c); */
+                        /* we are enabling autoidle afterwards anyways */
                         clk_enable(os->_clk);
                 }
         }
diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
index 8e44e2728620..debcd88ab971 100644
--- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
@@ -432,6 +432,13 @@ static struct omap_hwmod dm81xx_i2c2_hwmod = {
         .class          = &i2c_class,
 };
 
+static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = {
+        .master         = &dm81xx_l4_ls_hwmod,
+        .slave          = &dm81xx_i2c2_hwmod,
+        .clk            = "sysclk6_ck",
+        .user           = OCP_USER_MPU,
+};
+
 static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
         .rev_offs       = 0x0000,
         .sysc_offs      = 0x0010,
@@ -443,13 +450,6 @@ static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
         .sysc_fields    = &omap_hwmod_sysc_type1,
 };
 
-static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = {
-        .master         = &dm81xx_l4_ls_hwmod,
-        .slave          = &dm81xx_i2c2_hwmod,
-        .clk            = "sysclk6_ck",
-        .user           = OCP_USER_MPU,
-};
-
 static struct omap_hwmod_class dm81xx_elm_hwmod_class = {
         .name = "elm",
         .sysc = &dm81xx_elm_sysc,
@@ -539,6 +539,58 @@ static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
         .user           = OCP_USER_MPU,
 };
 
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+        { .role = "dbclk", .clk = "sysclk18_ck" },
+};
+
+static struct omap_hwmod dm81xx_gpio3_hwmod = {
+        .name           = "gpio3",
+        .clkdm_name     = "alwon_l3s_clkdm",
+        .class          = &dm81xx_gpio_hwmod_class,
+        .main_clk       = "sysclk6_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
+                        .modulemode = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = gpio3_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
+};
+
+static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio3 = {
+        .master         = &dm81xx_l4_ls_hwmod,
+        .slave          = &dm81xx_gpio3_hwmod,
+        .clk            = "sysclk6_ck",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+        { .role = "dbclk", .clk = "sysclk18_ck" },
+};
+
+static struct omap_hwmod dm81xx_gpio4_hwmod = {
+        .name           = "gpio4",
+        .clkdm_name     = "alwon_l3s_clkdm",
+        .class          = &dm81xx_gpio_hwmod_class,
+        .main_clk       = "sysclk6_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
+                        .modulemode = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = gpio4_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
+};
+
+static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio4 = {
+        .master         = &dm81xx_l4_ls_hwmod,
+        .slave          = &dm81xx_gpio4_hwmod,
+        .clk            = "sysclk6_ck",
+        .user           = OCP_USER_MPU,
+};
+
 static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = {
         .rev_offs       = 0x0,
         .sysc_offs      = 0x10,
@@ -1133,6 +1185,45 @@ static struct omap_hwmod dm81xx_mcspi1_hwmod = {
         .class          = &dm816x_mcspi_class,
 };
 
+static struct omap_hwmod dm81xx_mcspi2_hwmod = {
+        .name           = "mcspi2",
+        .clkdm_name     = "alwon_l3s_clkdm",
+        .main_clk       = "sysclk10_ck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
+                        .modulemode = MODULEMODE_SWCTRL,
+                },
+        },
+        .class          = &dm816x_mcspi_class,
+};
+
+static struct omap_hwmod dm81xx_mcspi3_hwmod = {
+        .name           = "mcspi3",
+        .clkdm_name     = "alwon_l3s_clkdm",
+        .main_clk       = "sysclk10_ck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
+                        .modulemode = MODULEMODE_SWCTRL,
+                },
+        },
+        .class          = &dm816x_mcspi_class,
+};
+
+static struct omap_hwmod dm81xx_mcspi4_hwmod = {
+        .name           = "mcspi4",
+        .clkdm_name     = "alwon_l3s_clkdm",
+        .main_clk       = "sysclk10_ck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
+                        .modulemode = MODULEMODE_SWCTRL,
+                },
+        },
+        .class          = &dm816x_mcspi_class,
+};
+
 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
         .master         = &dm81xx_l4_ls_hwmod,
         .slave          = &dm81xx_mcspi1_hwmod,
@@ -1140,6 +1231,27 @@ static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
         .user           = OCP_USER_MPU,
 };
 
+static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi2 = {
+        .master         = &dm81xx_l4_ls_hwmod,
+        .slave          = &dm81xx_mcspi2_hwmod,
+        .clk            = "sysclk6_ck",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi3 = {
+        .master         = &dm81xx_l4_ls_hwmod,
+        .slave          = &dm81xx_mcspi3_hwmod,
+        .clk            = "sysclk6_ck",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi4 = {
+        .master         = &dm81xx_l4_ls_hwmod,
+        .slave          = &dm81xx_mcspi4_hwmod,
+        .clk            = "sysclk6_ck",
+        .user           = OCP_USER_MPU,
+};
+
 static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = {
         .rev_offs       = 0x000,
         .sysc_offs      = 0x010,
@@ -1378,8 +1490,13 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
         &dm81xx_l4_ls__i2c2,
         &dm81xx_l4_ls__gpio1,
         &dm81xx_l4_ls__gpio2,
+        &dm81xx_l4_ls__gpio3,
+        &dm81xx_l4_ls__gpio4,
         &dm81xx_l4_ls__elm,
         &dm81xx_l4_ls__mcspi1,
+        &dm81xx_l4_ls__mcspi2,
+        &dm81xx_l4_ls__mcspi3,
+        &dm81xx_l4_ls__mcspi4,
         &dm814x_l4_ls__mmc1,
         &dm814x_l4_ls__mmc2,
         &ti81xx_l4_ls__rtc,
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 8a5b6ed4ec36..a2ecc5e69abb 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -330,7 +330,6 @@ static struct fixed_voltage_config pandora_vwlan = {
         .supply_name            = "vwlan",
         .microvolts             = 1800000, /* 1.8V */
         .startup_delay          = 50000, /* 50ms */
-        .enable_high            = 1,
         .init_data              = &pandora_vmmc3,
 };
 
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 058a37e6d11c..fd6e0671f957 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -523,8 +523,10 @@ void omap_prm_reset_system(void)
 
         prm_ll_data->reset_system();
 
-        while (1)
+        while (1) {
                 cpu_relax();
+                wfe();
+        }
 }
 
 /**
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 83a7ec4c16d0..c67f92bfa30e 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -20,7 +20,7 @@
 #include <linux/delay.h>
 #include <linux/clk-provider.h>
 #include <linux/cpu.h>
-#include <net/dsa.h>
+#include <linux/platform_data/dsa.h>
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <asm/system_misc.h>
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index a3c1336d30c9..c65ab7db36ad 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -16,7 +16,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/ethtool.h>
-#include <net/dsa.h>
+#include <linux/platform_data/dsa.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index 252efe29bd1a..76b8138d9d79 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -17,7 +17,7 @@
 #include <linux/mv643xx_eth.h>
 #include <linux/ethtool.h>
 #include <linux/i2c.h>
-#include <net/dsa.h>
+#include <linux/platform_data/dsa.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index f4f1dbe1d91d..5f388a1ed1e4 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -18,7 +18,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/ethtool.h>
-#include <net/dsa.h>
+#include <linux/platform_data/dsa.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index d162d4c7f85d..83589a28a491 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -15,7 +15,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/ethtool.h>
-#include <net/dsa.h>
+#include <linux/platform_data/dsa.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index 9250bb2e429c..cea08d4a2597 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -18,7 +18,7 @@
 #include <linux/leds.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
-#include <net/dsa.h>
+#include <linux/platform_data/dsa.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-oxnas/Makefile b/arch/arm/mach-oxnas/Makefile
index b625906a9970..61a34e1c0f22 100644
--- a/arch/arm/mach-oxnas/Makefile
+++ b/arch/arm/mach-oxnas/Makefile
@@ -1,2 +1 @@
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
-obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
diff --git a/arch/arm/mach-oxnas/hotplug.c b/arch/arm/mach-oxnas/hotplug.c
deleted file mode 100644
index 854f29b8cba6..000000000000
--- a/arch/arm/mach-oxnas/hotplug.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-
-#include <asm/cp15.h>
-#include <asm/smp_plat.h>
-
-static inline void cpu_enter_lowpower(void)
-{
-        unsigned int v;
-
-        asm volatile(
-        "       mcr     p15, 0, %1, c7, c5, 0\n"
-        "       mcr     p15, 0, %1, c7, c10, 4\n"
-        /*
-         * Turn off coherency
-         */
-        "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       bic     %0, %0, #0x20\n"
-        "       mcr     p15, 0, %0, c1, c0, 1\n"
-        "       mrc     p15, 0, %0, c1, c0, 0\n"
-        "       bic     %0, %0, %2\n"
-        "       mcr     p15, 0, %0, c1, c0, 0\n"
-          : "=&r" (v)
-          : "r" (0), "Ir" (CR_C)
-          : "cc");
-}
-
-static inline void cpu_leave_lowpower(void)
-{
-        unsigned int v;
-
-        asm volatile(   "mrc    p15, 0, %0, c1, c0, 0\n"
-        "       orr     %0, %0, %1\n"
-        "       mcr     p15, 0, %0, c1, c0, 0\n"
-        "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       orr     %0, %0, #0x20\n"
-        "       mcr     p15, 0, %0, c1, c0, 1\n"
-          : "=&r" (v)
-          : "Ir" (CR_C)
-          : "cc");
-}
-
-static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
-{
-        /*
-         * there is no power-control hardware on this platform, so all
-         * we can do is put the core into WFI; this is safe as the calling
-         * code will have already disabled interrupts
-         */
-        for (;;) {
-                /*
-                 * here's the WFI
-                 */
-                asm(".word      0xe320f003\n"
-                    :
-                    :
-                    : "memory", "cc");
-
-                if (pen_release == cpu_logical_map(cpu)) {
-                        /*
-                         * OK, proper wakeup, we're done
-                         */
-                        break;
-                }
-
-                /*
-                 * Getting here, means that we have come out of WFI without
-                 * having been woken up - this shouldn't happen
-                 *
-                 * Just note it happening - when we're woken, we can report
-                 * its occurrence.
-                 */
-                (*spurious)++;
-        }
-}
-
-/*
- * platform-specific code to shutdown a CPU
- *
- * Called with IRQs disabled
- */
-void ox820_cpu_die(unsigned int cpu)
-{
-        int spurious = 0;
-
-        /*
-         * we're ready for shutdown now, so do it
-         */
-        cpu_enter_lowpower();
-        platform_do_lowpower(cpu, &spurious);
-
-        /*
-         * bring this CPU back into the world of cache
-         * coherency, and then restore interrupts
-         */
-        cpu_leave_lowpower();
-
-        if (spurious)
-                pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
-}
diff --git a/arch/arm/mach-oxnas/platsmp.c b/arch/arm/mach-oxnas/platsmp.c
index 442cc8a2f7dc..735141c0e3a3 100644
--- a/arch/arm/mach-oxnas/platsmp.c
+++ b/arch/arm/mach-oxnas/platsmp.c
@@ -19,7 +19,6 @@
 #include <asm/smp_scu.h>
 
 extern void ox820_secondary_startup(void);
-extern void ox820_cpu_die(unsigned int cpu);
 
 static void __iomem *cpu_ctrl;
 static void __iomem *gic_cpu_ctrl;
@@ -94,9 +93,6 @@ unmap_scu:
 static const struct smp_operations ox820_smp_ops __initconst = {
         .smp_prepare_cpus       = ox820_smp_prepare_cpus,
         .smp_boot_secondary     = ox820_boot_secondary,
-#ifdef CONFIG_HOTPLUG_CPU
-        .cpu_die                = ox820_cpu_die,
-#endif
 };
 
 CPU_METHOD_OF_DECLARE(ox820_smp, "oxsemi,ox820-smp", &ox820_smp_ops);
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index 6d77b622d168..457eb7b18160 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -15,6 +15,8 @@
 #include <asm/mach/time.h>
 #include <asm/exception.h>
 
+extern volatile int prima2_pen_release;
+
 extern const struct smp_operations sirfsoc_smp_ops;
 extern void sirfsoc_secondary_startup(void);
 extern void sirfsoc_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-prima2/headsmp.S b/arch/arm/mach-prima2/headsmp.S
index 209d9fc5c16c..6cf4fc60347b 100644
--- a/arch/arm/mach-prima2/headsmp.S
+++ b/arch/arm/mach-prima2/headsmp.S
@@ -34,4 +34,4 @@ ENDPROC(sirfsoc_secondary_startup)
 
         .align
 1:      .long   .
-        .long   pen_release
+        .long   prima2_pen_release
diff --git a/arch/arm/mach-prima2/hotplug.c b/arch/arm/mach-prima2/hotplug.c
index a728c78b996f..b6cf1527e330 100644
--- a/arch/arm/mach-prima2/hotplug.c
+++ b/arch/arm/mach-prima2/hotplug.c
@@ -11,6 +11,7 @@
 #include <linux/smp.h>
 
 #include <asm/smp_plat.h>
+#include "common.h"
 
 static inline void platform_do_lowpower(unsigned int cpu)
 {
@@ -18,7 +19,7 @@ static inline void platform_do_lowpower(unsigned int cpu)
         for (;;) {
                 __asm__ __volatile__("dsb\n\t" "wfi\n\t"
                         : : : "memory");
-                if (pen_release == cpu_logical_map(cpu)) {
+                if (prima2_pen_release == cpu_logical_map(cpu)) {
                         /*
                          * OK, proper wakeup, we're done
                          */
diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c
index 75ef5d4be554..d1f8b5168083 100644
--- a/arch/arm/mach-prima2/platsmp.c
+++ b/arch/arm/mach-prima2/platsmp.c
@@ -24,13 +24,16 @@ static void __iomem *clk_base;
 
 static DEFINE_SPINLOCK(boot_lock);
 
+/* XXX prima2_pen_release is cargo culted code - DO NOT COPY XXX */
+volatile int prima2_pen_release = -1;
+
 static void sirfsoc_secondary_init(unsigned int cpu)
 {
         /*
          * let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
-        pen_release = -1;
+        prima2_pen_release = -1;
         smp_wmb();
 
         /*
@@ -80,13 +83,13 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
         /*
          * The secondary processor is waiting to be released from
          * the holding pen - release it, then wait for it to flag
-         * that it has been released by resetting pen_release.
+         * that it has been released by resetting prima2_pen_release.
          *
-         * Note that "pen_release" is the hardware CPU ID, whereas
+         * Note that "prima2_pen_release" is the hardware CPU ID, whereas
          * "cpu" is Linux's internal ID.
          */
-        pen_release = cpu_logical_map(cpu);
-        sync_cache_w(&pen_release);
+        prima2_pen_release = cpu_logical_map(cpu);
+        sync_cache_w(&prima2_pen_release);
 
         /*
          * Send the secondary CPU SEV, thereby causing the boot monitor to read
@@ -97,7 +100,7 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
         timeout = jiffies + (1 * HZ);
         while (time_before(jiffies, timeout)) {
                 smp_rmb();
-                if (pen_release == -1)
+                if (prima2_pen_release == -1)
                         break;
 
                 udelay(10);
@@ -109,7 +112,7 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
          */
         spin_unlock(&boot_lock);
 
-        return pen_release != -1 ? -ENOSYS : 0;
+        return prima2_pen_release != -1 ? -ENOSYS : 0;
 }
 
 const struct smp_operations sirfsoc_smp_ops __initconst = {
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index dc8e4f4b7ade..8839c72fdee3 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -454,24 +454,6 @@ config MACH_TREO680
           Say Y here if you intend to run this kernel on Palm Treo 680
           smartphone.
 
-config MACH_RAUMFELD_RC
-        bool "Raumfeld Controller"
-        select CPU_PXA300
-        select POWER_SUPPLY
-        select PXA3xx
-
-config MACH_RAUMFELD_CONNECTOR
-        bool "Raumfeld Connector"
-        select CPU_PXA300
-        select POWER_SUPPLY
-        select PXA3xx
-
-config MACH_RAUMFELD_SPEAKER
-        bool "Raumfeld Speaker"
-        select CPU_PXA300
-        select POWER_SUPPLY
-        select PXA3xx
-
 config PXA_SHARPSL
         bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models"
         select SHARP_PARAM
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 0a8e9611052f..f70728930c4f 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -86,9 +86,6 @@ obj-$(CONFIG_MACH_POODLE)	+= poodle.o
 obj-$(CONFIG_MACH_TOSA)         += tosa.o
 obj-$(CONFIG_MACH_ICONTROL)     += icontrol.o mxm8x10.o
 obj-$(CONFIG_ARCH_PXA_ESERIES)  += eseries.o
-obj-$(CONFIG_MACH_RAUMFELD_RC)          += raumfeld.o
-obj-$(CONFIG_MACH_RAUMFELD_CONNECTOR)   += raumfeld.o
-obj-$(CONFIG_MACH_RAUMFELD_SPEAKER)     += raumfeld.o
 obj-$(CONFIG_MACH_ZIPIT2)       += z2.o
 
 obj-$(CONFIG_PXA_SYSTEMS_CPLDS) += pxa_cplds_irqs.o
diff --git a/arch/arm/mach-pxa/cm-x255.c b/arch/arm/mach-pxa/cm-x255.c
index fa8e7dd4d898..4401dfcd7e68 100644
--- a/arch/arm/mach-pxa/cm-x255.c
+++ b/arch/arm/mach-pxa/cm-x255.c
@@ -98,7 +98,7 @@ static unsigned long cmx255_pin_config[] = {
 };
 
 #if defined(CONFIG_SPI_PXA2XX)
-static struct pxa2xx_spi_master pxa_ssp_master_info = {
+static struct pxa2xx_spi_controller pxa_ssp_master_info = {
         .num_chipselect = 1,
 };
 
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
index f7081a50dc67..279eeca7add0 100644
--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -313,7 +313,7 @@ static inline void cmx270_init_mmc(void) {}
 #endif
 
 #if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
-static struct pxa2xx_spi_master cm_x270_spi_info = {
+static struct pxa2xx_spi_controller cm_x270_spi_info = {
         .num_chipselect = 1,
         .enable_dma     = 1,
 };
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index c9732cace5e3..7ecf559bd71c 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -530,7 +530,7 @@ static struct pxa2xx_udc_mach_info udc_info __initdata = {
 };
 
 #if IS_ENABLED(CONFIG_SPI_PXA2XX)
-static struct pxa2xx_spi_master corgi_spi_info = {
+static struct pxa2xx_spi_controller corgi_spi_info = {
         .num_chipselect = 3,
 };
 
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index a24783a03827..524d6093e0c7 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -1065,7 +1065,7 @@ struct platform_device pxa93x_device_gpio = {
 
 /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
-void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
+void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_controller *info)
 {
         struct platform_device *pd;
 
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 32c1edeb3f14..fa3adb073a0f 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -689,7 +689,7 @@ static inline void em_x270_init_lcd(void) {}
 #endif
 
 #if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
-static struct pxa2xx_spi_master em_x270_spi_info = {
+static struct pxa2xx_spi_controller em_x270_spi_info = {
         .num_chipselect = 1,
 };
 
@@ -703,7 +703,7 @@ static struct tdo24m_platform_data em_x270_tdo24m_pdata = {
         .model = TDO35S,
 };
 
-static struct pxa2xx_spi_master em_x270_spi_2_info = {
+static struct pxa2xx_spi_controller em_x270_spi_2_info = {
         .num_chipselect = 1,
         .enable_dma     = 1,
 };
@@ -976,7 +976,6 @@ static struct fixed_voltage_config camera_dummy_config = {
         .supply_name            = "camera_vdd",
         .input_supply           = "vcc cam",
         .microvolts             = 2800000,
-        .enable_high            = 0,
         .init_data              = &camera_dummy_initdata,
 };
 
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index 565965e9acc7..5e110e70ce5a 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -714,7 +714,6 @@ static struct regulator_init_data camera_regulator_initdata = {
 static struct fixed_voltage_config camera_regulator_config = {
         .supply_name            = "camera_vdd",
         .microvolts             = 2800000,
-        .enable_high            = 0,
         .init_data              = &camera_regulator_initdata,
 };
 
@@ -730,7 +729,7 @@ static struct gpiod_lookup_table camera_supply_gpiod_table = {
         .dev_id = "reg-fixed-voltage.1",
         .table = {
                 GPIO_LOOKUP("gpio-pxa", GPIO50_nCAM_EN,
-                            NULL, GPIO_ACTIVE_HIGH),
+                            NULL, GPIO_ACTIVE_LOW),
                 { },
         },
 };
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index b79b757fdd41..1d6b1d2fb6a9 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -19,6 +19,7 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/fb.h>
+#include <linux/gpio/machine.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
@@ -629,7 +630,7 @@ static struct spi_board_info tsc2046_board_info[] __initdata = {
         },
 };
 
-static struct pxa2xx_spi_master pxa_ssp2_master_info = {
+static struct pxa2xx_spi_controller pxa_ssp2_master_info = {
         .num_chipselect = 1,
         .enable_dma     = 1,
 };
@@ -702,9 +703,7 @@ static struct regulator_init_data bq24022_init_data = {
         .consumer_supplies      = bq24022_consumers,
 };
 
-static struct gpio bq24022_gpios[] = {
-        { GPIO96_HX4700_BQ24022_ISET2, GPIOF_OUT_INIT_LOW, "bq24022_iset2" },
-};
+static enum gpiod_flags bq24022_gpiod_gflags[] = { GPIOD_OUT_LOW };
 
 static struct gpio_regulator_state bq24022_states[] = {
         { .value = 100000, .gpios = (0 << 0) },
@@ -714,12 +713,10 @@ static struct gpio_regulator_state bq24022_states[] = {
 static struct gpio_regulator_config bq24022_info = {
         .supply_name = "bq24022",
 
-        .enable_gpio = GPIO72_HX4700_BQ24022_nCHARGE_EN,
-        .enable_high = 0,
         .enabled_at_boot = 0,
 
-        .gpios = bq24022_gpios,
-        .nr_gpios = ARRAY_SIZE(bq24022_gpios),
+        .gflags = bq24022_gpiod_gflags,
+        .ngpios = ARRAY_SIZE(bq24022_gpiod_gflags),
 
         .states = bq24022_states,
         .nr_states = ARRAY_SIZE(bq24022_states),
@@ -736,6 +733,17 @@ static struct platform_device bq24022 = {
         },
 };
 
+static struct gpiod_lookup_table bq24022_gpiod_table = {
+        .dev_id = "gpio-regulator",
+        .table = {
+                GPIO_LOOKUP("gpio-pxa", GPIO96_HX4700_BQ24022_ISET2,
+                            NULL, GPIO_ACTIVE_HIGH),
+                GPIO_LOOKUP("gpio-pxa", GPIO72_HX4700_BQ24022_nCHARGE_EN,
+                            "enable", GPIO_ACTIVE_LOW),
+                { },
+        },
+};
+
 /*
  * StrataFlash
  */
@@ -878,6 +886,7 @@ static void __init hx4700_init(void)
         pxa_set_btuart_info(NULL);
         pxa_set_stuart_info(NULL);
 
+        gpiod_add_lookup_table(&bq24022_gpiod_table);
         platform_add_devices(devices, ARRAY_SIZE(devices));
         pwm_add_table(hx4700_pwm_lookup, ARRAY_SIZE(hx4700_pwm_lookup));
 
diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c
index cbaf4f6edcda..7e30452e3840 100644
--- a/arch/arm/mach-pxa/icontrol.c
+++ b/arch/arm/mach-pxa/icontrol.c
@@ -115,12 +115,12 @@ static struct spi_board_info mcp251x_board_info[] = {
         }
 };
 
-static struct pxa2xx_spi_master pxa_ssp3_spi_master_info = {
+static struct pxa2xx_spi_controller pxa_ssp3_spi_master_info = {
         .num_chipselect = 2,
         .enable_dma     = 1
 };
 
-static struct pxa2xx_spi_master pxa_ssp4_spi_master_info = {
+static struct pxa2xx_spi_controller pxa_ssp4_spi_master_info = {
         .num_chipselect = 2,
         .enable_dma     = 1
 };
diff --git a/arch/arm/mach-pxa/include/mach/pxa25x-udc.h b/arch/arm/mach-pxa/include/mach/pxa25x-udc.h
deleted file mode 100644
index e69de29bb2d1..000000000000
--- a/arch/arm/mach-pxa/include/mach/pxa25x-udc.h
+++ /dev/null
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 39db4898dc4a..464b8bd2bcb9 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -191,7 +191,7 @@ static inline void littleton_init_lcd(void) {};
 #endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */
 
 #if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
-static struct pxa2xx_spi_master littleton_spi_info = {
+static struct pxa2xx_spi_controller littleton_spi_info = {
         .num_chipselect         = 1,
 };
 
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index a1391e113ef4..c1bd0d544981 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -197,7 +197,7 @@ static struct platform_device sa1111_device = {
  * (to J5) and poking board registers (as done below).  Else it's only useful
  * for the temperature sensors.
  */
-static struct pxa2xx_spi_master pxa_ssp_master_info = {
+static struct pxa2xx_spi_controller pxa_ssp_master_info = {
         .num_chipselect = 1,
 };
 
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 08b079653c3f..75abc21083eb 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -645,9 +645,8 @@ static struct regulator_init_data bq24022_init_data = {
         .consumer_supplies      = bq24022_consumers,
 };
 
-static struct gpio bq24022_gpios[] = {
-        { EGPIO_MAGICIAN_BQ24022_ISET2, GPIOF_OUT_INIT_LOW, "bq24022_iset2" },
-};
+
+static enum gpiod_flags bq24022_gpiod_gflags[] = { GPIOD_OUT_LOW };
 
 static struct gpio_regulator_state bq24022_states[] = {
         { .value = 100000, .gpios = (0 << 0) },
@@ -657,12 +656,10 @@ static struct gpio_regulator_state bq24022_states[] = {
 static struct gpio_regulator_config bq24022_info = {
         .supply_name            = "bq24022",
 
-        .enable_gpio            = GPIO30_MAGICIAN_BQ24022_nCHARGE_EN,
-        .enable_high            = 0,
         .enabled_at_boot        = 1,
 
-        .gpios                  = bq24022_gpios,
-        .nr_gpios               = ARRAY_SIZE(bq24022_gpios),
+        .gflags = bq24022_gpiod_gflags,
+        .ngpios = ARRAY_SIZE(bq24022_gpiod_gflags),
 
         .states                 = bq24022_states,
         .nr_states              = ARRAY_SIZE(bq24022_states),
@@ -679,6 +676,17 @@ static struct platform_device bq24022 = {
         },
 };
 
+static struct gpiod_lookup_table bq24022_gpiod_table = {
+        .dev_id = "gpio-regulator",
+        .table = {
+                GPIO_LOOKUP("gpio-pxa", EGPIO_MAGICIAN_BQ24022_ISET2,
+                            NULL, GPIO_ACTIVE_HIGH),
+                GPIO_LOOKUP("gpio-pxa", GPIO30_MAGICIAN_BQ24022_nCHARGE_EN,
+                            "enable", GPIO_ACTIVE_LOW),
+                { },
+        },
+};
+
 /*
  * fixed regulator for ads7846
  */
@@ -932,7 +940,7 @@ struct pxa2xx_spi_chip tsc2046_chip_info = {
         .gpio_cs        = GPIO14_MAGICIAN_TSC2046_CS,
 };
 
-static struct pxa2xx_spi_master magician_spi_info = {
+static struct pxa2xx_spi_controller magician_spi_info = {
         .num_chipselect = 1,
         .enable_dma     = 1,
 };
@@ -1027,6 +1035,7 @@ static void __init magician_init(void)
         regulator_register_always_on(0, "power", pwm_backlight_supply,
                 ARRAY_SIZE(pwm_backlight_supply), 5000000);
 
+        gpiod_add_lookup_table(&bq24022_gpiod_table);
         platform_add_devices(ARRAY_AND_SIZE(devices));
 }
 
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index ccca9f7575c3..e2e613449660 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -132,7 +132,7 @@ static struct platform_device smc91x_device = {
 /*
  * SPI host and devices
  */
-static struct pxa2xx_spi_master pxa_ssp_master_info = {
+static struct pxa2xx_spi_controller pxa_ssp_master_info = {
         .num_chipselect = 1,
 };
 
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index c2a43d4cfd3e..9450a523cd0b 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -196,7 +196,7 @@ struct platform_device poodle_locomo_device = {
 EXPORT_SYMBOL(poodle_locomo_device);
 
 #if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
-static struct pxa2xx_spi_master poodle_spi_info = {
+static struct pxa2xx_spi_controller poodle_spi_info = {
         .num_chipselect = 1,
 };
 
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
deleted file mode 100644
index e1db072756f2..000000000000
--- a/arch/arm/mach-pxa/raumfeld.c
+++ /dev/null
@@ -1,1187 +0,0 @@
-/*
- * arch/arm/mach-pxa/raumfeld.c
- *
- * Support for the following Raumfeld devices:
- *
- *      * Controller
- *      * Connector
- *      * Speaker S/M
- *
- * See http://www.raumfeld.com for details.
- *
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/property.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/smsc911x.h>
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-#include <linux/leds.h>
-#include <linux/w1-gpio.h>
-#include <linux/sched.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/spi_gpio.h>
-#include <linux/lis3lv02d.h>
-#include <linux/pda_power.h>
-#include <linux/power_supply.h>
-#include <linux/regulator/max8660.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/consumer.h>
-#include <linux/delay.h>
-
-#include <asm/system_info.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "pxa300.h"
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/mtd-nand-pxa3xx.h>
-
-#include "generic.h"
-#include "devices.h"
-
-/* common GPIO  definitions */
-
-/* inputs */
-#define GPIO_ON_OFF             (14)
-#define GPIO_VOLENC_A           (19)
-#define GPIO_VOLENC_B           (20)
-#define GPIO_CHARGE_DONE        (23)
-#define GPIO_CHARGE_IND         (27)
-#define GPIO_TOUCH_IRQ          (32)
-#define GPIO_ETH_IRQ            (40)
-#define GPIO_SPI_MISO           (98)
-#define GPIO_ACCEL_IRQ          (104)
-#define GPIO_RESCUE_BOOT        (115)
-#define GPIO_DOCK_DETECT        (116)
-#define GPIO_KEY1               (117)
-#define GPIO_KEY2               (118)
-#define GPIO_KEY3               (119)
-#define GPIO_CHARGE_USB_OK      (112)
-#define GPIO_CHARGE_DC_OK       (101)
-#define GPIO_CHARGE_USB_SUSP    (102)
-
-/* outputs */
-#define GPIO_SHUTDOWN_SUPPLY    (16)
-#define GPIO_SHUTDOWN_BATT      (18)
-#define GPIO_CHRG_PEN2          (31)
-#define GPIO_TFT_VA_EN          (33)
-#define GPIO_SPDIF_CS           (34)
-#define GPIO_LED2               (35)
-#define GPIO_LED1               (36)
-#define GPIO_SPDIF_RESET        (38)
-#define GPIO_SPI_CLK            (95)
-#define GPIO_MCLK_DAC_CS        (96)
-#define GPIO_SPI_MOSI           (97)
-#define GPIO_W1_PULLUP_ENABLE   (105)
-#define GPIO_DISPLAY_ENABLE     (106)
-#define GPIO_MCLK_RESET         (111)
-#define GPIO_W2W_RESET          (113)
-#define GPIO_W2W_PDN            (114)
-#define GPIO_CODEC_RESET        (120)
-#define GPIO_AUDIO_VA_ENABLE    (124)
-#define GPIO_ACCEL_CS           (125)
-#define GPIO_ONE_WIRE           (126)
-
-/*
- * GPIO configurations
- */
-static mfp_cfg_t raumfeld_controller_pin_config[] __initdata = {
-        /* UART1 */
-        GPIO77_UART1_RXD,
-        GPIO78_UART1_TXD,
-        GPIO79_UART1_CTS,
-        GPIO81_UART1_DSR,
-        GPIO83_UART1_DTR,
-        GPIO84_UART1_RTS,
-
-        /* UART3 */
-        GPIO110_UART3_RXD,
-
-        /* USB Host */
-        GPIO0_2_USBH_PEN,
-        GPIO1_2_USBH_PWR,
-
-        /* I2C */
-        GPIO21_I2C_SCL | MFP_LPM_FLOAT | MFP_PULL_FLOAT,
-        GPIO22_I2C_SDA | MFP_LPM_FLOAT | MFP_PULL_FLOAT,
-
-        /* SPI */
-        GPIO34_GPIO,    /* SPDIF_CS */
-        GPIO96_GPIO,    /* MCLK_CS */
-        GPIO125_GPIO,   /* ACCEL_CS */
-
-        /* MMC */
-        GPIO3_MMC1_DAT0,
-        GPIO4_MMC1_DAT1,
-        GPIO5_MMC1_DAT2,
-        GPIO6_MMC1_DAT3,
-        GPIO7_MMC1_CLK,
-        GPIO8_MMC1_CMD,
-
-        /* One-wire */
-        GPIO126_GPIO | MFP_LPM_FLOAT,
-        GPIO105_GPIO | MFP_PULL_LOW | MFP_LPM_PULL_LOW,
-
-        /* CHRG_USB_OK */
-        GPIO101_GPIO | MFP_PULL_HIGH,
-        /* CHRG_USB_OK */
-        GPIO112_GPIO | MFP_PULL_HIGH,
-        /* CHRG_USB_SUSP */
-        GPIO102_GPIO,
-        /* DISPLAY_ENABLE */
-        GPIO106_GPIO,
-        /* DOCK_DETECT */
-        GPIO116_GPIO | MFP_LPM_FLOAT | MFP_PULL_FLOAT,
-
-        /* LCD */
-        GPIO54_LCD_LDD_0,
-        GPIO55_LCD_LDD_1,
-        GPIO56_LCD_LDD_2,
-        GPIO57_LCD_LDD_3,
-        GPIO58_LCD_LDD_4,
-        GPIO59_LCD_LDD_5,
-        GPIO60_LCD_LDD_6,
-        GPIO61_LCD_LDD_7,
-        GPIO62_LCD_LDD_8,
-        GPIO63_LCD_LDD_9,
-        GPIO64_LCD_LDD_10,
-        GPIO65_LCD_LDD_11,
-        GPIO66_LCD_LDD_12,
-        GPIO67_LCD_LDD_13,
-        GPIO68_LCD_LDD_14,
-        GPIO69_LCD_LDD_15,
-        GPIO70_LCD_LDD_16,
-        GPIO71_LCD_LDD_17,
-        GPIO72_LCD_FCLK,
-        GPIO73_LCD_LCLK,
-        GPIO74_LCD_PCLK,
-        GPIO75_LCD_BIAS,
-};
-
-static mfp_cfg_t raumfeld_connector_pin_config[] __initdata = {
-        /* UART1 */
-        GPIO77_UART1_RXD,
-        GPIO78_UART1_TXD,
-        GPIO79_UART1_CTS,
-        GPIO81_UART1_DSR,
-        GPIO83_UART1_DTR,
-        GPIO84_UART1_RTS,
-
-        /* UART3 */
-        GPIO110_UART3_RXD,
-
-        /* USB Host */
-        GPIO0_2_USBH_PEN,
-        GPIO1_2_USBH_PWR,
-
-        /* I2C */
-        GPIO21_I2C_SCL | MFP_LPM_FLOAT | MFP_PULL_FLOAT,
-        GPIO22_I2C_SDA | MFP_LPM_FLOAT | MFP_PULL_FLOAT,
-
-        /* SPI */
-        GPIO34_GPIO,    /* SPDIF_CS */
-        GPIO96_GPIO,    /* MCLK_CS */
-        GPIO125_GPIO,   /* ACCEL_CS */
-
-        /* MMC */
-        GPIO3_MMC1_DAT0,
-        GPIO4_MMC1_DAT1,
-        GPIO5_MMC1_DAT2,
-        GPIO6_MMC1_DAT3,
-        GPIO7_MMC1_CLK,
-        GPIO8_MMC1_CMD,
-
-        /* Ethernet */
-        GPIO1_nCS2,                     /* CS */
-        GPIO40_GPIO | MFP_PULL_HIGH,    /* IRQ */
-
-        /* SSP for I2S */
-        GPIO85_SSP1_SCLK,
-        GPIO89_SSP1_EXTCLK,
-        GPIO86_SSP1_FRM,
-        GPIO87_SSP1_TXD,
-        GPIO88_SSP1_RXD,
-        GPIO90_SSP1_SYSCLK,
-
-        /* SSP2 for S/PDIF */
-        GPIO25_SSP2_SCLK,
-        GPIO26_SSP2_FRM,
-        GPIO27_SSP2_TXD,
-        GPIO29_SSP2_EXTCLK,
-
-        /* LEDs */
-        GPIO35_GPIO | MFP_LPM_PULL_LOW,
-        GPIO36_GPIO | MFP_LPM_DRIVE_HIGH,
-};
-
-static mfp_cfg_t raumfeld_speaker_pin_config[] __initdata = {
-        /* UART1 */
-        GPIO77_UART1_RXD,
-        GPIO78_UART1_TXD,
-        GPIO79_UART1_CTS,
-        GPIO81_UART1_DSR,
-        GPIO83_UART1_DTR,
-        GPIO84_UART1_RTS,
-
-        /* UART3 */
-        GPIO110_UART3_RXD,
-
-        /* USB Host */
-        GPIO0_2_USBH_PEN,
-        GPIO1_2_USBH_PWR,
-
-        /* I2C */
-        GPIO21_I2C_SCL | MFP_LPM_FLOAT | MFP_PULL_FLOAT,
-        GPIO22_I2C_SDA | MFP_LPM_FLOAT | MFP_PULL_FLOAT,
-
-        /* SPI */
-        GPIO34_GPIO,    /* SPDIF_CS */
-        GPIO96_GPIO,    /* MCLK_CS */
-        GPIO125_GPIO,   /* ACCEL_CS */
-
-        /* MMC */
-        GPIO3_MMC1_DAT0,
-        GPIO4_MMC1_DAT1,
-        GPIO5_MMC1_DAT2,
-        GPIO6_MMC1_DAT3,
-        GPIO7_MMC1_CLK,
-        GPIO8_MMC1_CMD,
-
-        /* Ethernet */
-        GPIO1_nCS2,                     /* CS */
-        GPIO40_GPIO | MFP_PULL_HIGH,    /* IRQ */
-
-        /* SSP for I2S */
-        GPIO85_SSP1_SCLK,
-        GPIO89_SSP1_EXTCLK,
-        GPIO86_SSP1_FRM,
-        GPIO87_SSP1_TXD,
-        GPIO88_SSP1_RXD,
-        GPIO90_SSP1_SYSCLK,
-
-        /* LEDs */
-        GPIO35_GPIO | MFP_LPM_PULL_LOW,
-        GPIO36_GPIO | MFP_LPM_DRIVE_HIGH,
-};
-
-/*
- * SMSC LAN9220 Ethernet
- */
-
-static struct resource smc91x_resources[] = {
-        {
-                .start  = PXA3xx_CS2_PHYS,
-                .end    = PXA3xx_CS2_PHYS + 0xfffff,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = PXA_GPIO_TO_IRQ(GPIO_ETH_IRQ),
-                .end    = PXA_GPIO_TO_IRQ(GPIO_ETH_IRQ),
-                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
-        }
-};
-
-static struct smsc911x_platform_config raumfeld_smsc911x_config = {
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
-        .flags          = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
-};
-
-static struct platform_device smc91x_device = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(smc91x_resources),
-        .resource       = smc91x_resources,
-        .dev            = {
-                .platform_data = &raumfeld_smsc911x_config,
-        }
-};
-
-/**
- * NAND
- */
-
-static struct mtd_partition raumfeld_nand_partitions[] = {
-        {
-                .name           = "Bootloader",
-                .offset         = 0,
-                .size           = 0xa0000,
-                .mask_flags     = MTD_WRITEABLE, /* force read-only */
-        },
-        {
-                .name           = "BootloaderEnvironment",
-                .offset         = 0xa0000,
-                .size           = 0x20000,
-        },
-        {
-                .name           = "BootloaderSplashScreen",
-                .offset         = 0xc0000,
-                .size           = 0x60000,
-        },
-        {
-                .name           = "UBI",
-                .offset         = 0x120000,
-                .size           = MTDPART_SIZ_FULL,
-        },
-};
-
-static struct pxa3xx_nand_platform_data raumfeld_nand_info = {
-        .keep_config    = 1,
-        .parts          = raumfeld_nand_partitions,
-        .nr_parts       = ARRAY_SIZE(raumfeld_nand_partitions),
-};
-
-/**
- * USB (OHCI) support
- */
-
-static struct pxaohci_platform_data raumfeld_ohci_info = {
-        .port_mode      = PMM_GLOBAL_MODE,
-        .flags          = ENABLE_PORT1,
-};
-
-/**
- * Rotary encoder input device
- */
-
-static struct gpiod_lookup_table raumfeld_rotary_gpios_table = {
-        .dev_id = "rotary-encoder.0",
-        .table = {
-                GPIO_LOOKUP_IDX("gpio-0",
-                                GPIO_VOLENC_A, NULL, 0, GPIO_ACTIVE_LOW),
-                GPIO_LOOKUP_IDX("gpio-0",
-                                GPIO_VOLENC_B, NULL, 1, GPIO_ACTIVE_HIGH),
-                { },
-        },
-};
-
-static const struct property_entry raumfeld_rotary_properties[] __initconst = {
-        PROPERTY_ENTRY_U32("rotary-encoder,steps-per-period", 24),
-        PROPERTY_ENTRY_U32("linux,axis",                      REL_X),
-        PROPERTY_ENTRY_U32("rotary-encoder,relative_axis",    1),
-        { },
-};
-
-static struct platform_device rotary_encoder_device = {
-        .name           = "rotary-encoder",
-        .id             = 0,
-};
-
-/**
- * GPIO buttons
- */
-
-static struct gpio_keys_button gpio_keys_button[] = {
-        {
-                .code                   = KEY_F1,
-                .type                   = EV_KEY,
-                .gpio                   = GPIO_KEY1,
-                .active_low             = 1,
-                .wakeup                 = 0,
-                .debounce_interval      = 5, /* ms */
-                .desc                   = "Button 1",
-        },
-        {
-                .code                   = KEY_F2,
-                .type                   = EV_KEY,
-                .gpio                   = GPIO_KEY2,
-                .active_low             = 1,
-                .wakeup                 = 0,
-                .debounce_interval      = 5, /* ms */
-                .desc                   = "Button 2",
-        },
-        {
-                .code                   = KEY_F3,
-                .type                   = EV_KEY,
-                .gpio                   = GPIO_KEY3,
-                .active_low             = 1,
-                .wakeup                 = 0,
-                .debounce_interval      = 5, /* ms */
-                .desc                   = "Button 3",
-        },
-        {
-                .code                   = KEY_F4,
-                .type                   = EV_KEY,
-                .gpio                   = GPIO_RESCUE_BOOT,
-                .active_low             = 0,
-                .wakeup                 = 0,
-                .debounce_interval      = 5, /* ms */
-                .desc                   = "rescue boot button",
-        },
-        {
-                .code                   = KEY_F5,
-                .type                   = EV_KEY,
-                .gpio                   = GPIO_DOCK_DETECT,
-                .active_low             = 1,
-                .wakeup                 = 0,
-                .debounce_interval      = 5, /* ms */
-                .desc                   = "dock detect",
-        },
-        {
-                .code                   = KEY_F6,
-                .type                   = EV_KEY,
-                .gpio                   = GPIO_ON_OFF,
-                .active_low             = 0,
-                .wakeup                 = 0,
-                .debounce_interval      = 5, /* ms */
-                .desc                   = "on_off button",
-        },
-};
-
-static struct gpio_keys_platform_data gpio_keys_platform_data = {
-        .buttons        = gpio_keys_button,
-        .nbuttons       = ARRAY_SIZE(gpio_keys_button),
-        .rep            = 0,
-};
-
-static struct platform_device raumfeld_gpio_keys_device = {
-        .name   = "gpio-keys",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &gpio_keys_platform_data,
-        }
-};
-
-/**
- * GPIO LEDs
- */
-
-static struct gpio_led raumfeld_leds[] = {
-        {
-                .name           = "raumfeld:1",
-                .gpio           = GPIO_LED1,
-                .active_low     = 1,
-                .default_state  = LEDS_GPIO_DEFSTATE_ON,
-        },
-        {
-                .name           = "raumfeld:2",
-                .gpio           = GPIO_LED2,
-                .active_low     = 0,
-                .default_state  = LEDS_GPIO_DEFSTATE_OFF,
-        }
-};
-
-static struct gpio_led_platform_data raumfeld_led_platform_data = {
-        .leds           = raumfeld_leds,
-        .num_leds       = ARRAY_SIZE(raumfeld_leds),
-};
-
-static struct platform_device raumfeld_led_device = {
-        .name   = "leds-gpio",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &raumfeld_led_platform_data,
-        },
-};
-
-/**
- * One-wire (W1 bus) support
- */
-
-static void w1_enable_external_pullup(int enable)
-{
-        gpio_set_value(GPIO_W1_PULLUP_ENABLE, enable);
-        msleep(100);
-}
-
-static struct gpiod_lookup_table raumfeld_w1_gpiod_table = {
-        .dev_id = "w1-gpio",
-        .table = {
-                GPIO_LOOKUP_IDX("gpio-pxa", GPIO_ONE_WIRE, NULL, 0,
-                                GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
-        },
-};
-
-static struct w1_gpio_platform_data w1_gpio_platform_data = {
-        .enable_external_pullup = w1_enable_external_pullup,
-};
-
-static struct platform_device raumfeld_w1_gpio_device = {
-        .name   = "w1-gpio",
-        .dev    = {
-                .platform_data = &w1_gpio_platform_data
-        }
-};
-
-static void __init raumfeld_w1_init(void)
-{
-        int ret = gpio_request(GPIO_W1_PULLUP_ENABLE,
-                                "W1 external pullup enable");
-
-        if (ret < 0)
-                pr_warn("Unable to request GPIO_W1_PULLUP_ENABLE\n");
-        else
-                gpio_direction_output(GPIO_W1_PULLUP_ENABLE, 0);
-
-        gpiod_add_lookup_table(&raumfeld_w1_gpiod_table);
-        platform_device_register(&raumfeld_w1_gpio_device);
-}
-
-/**
- * Framebuffer device
- */
-
-static struct pwm_lookup raumfeld_pwm_lookup[] = {
-        PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight", NULL, 10000,
-                   PWM_POLARITY_NORMAL),
-};
-
-/* PWM controlled backlight */
-static struct platform_pwm_backlight_data raumfeld_pwm_backlight_data = {
-        .max_brightness = 100,
-        .dft_brightness = 100,
-        .enable_gpio    = -1,
-};
-
-static struct platform_device raumfeld_pwm_backlight_device = {
-        .name   = "pwm-backlight",
-        .dev    = {
-                .parent         = &pxa27x_device_pwm0.dev,
-                .platform_data  = &raumfeld_pwm_backlight_data,
-        }
-};
-
-/* LT3593 controlled backlight */
-static struct gpio_led raumfeld_lt3593_led = {
-        .name           = "backlight",
-        .gpio           = mfp_to_gpio(MFP_PIN_GPIO17),
-        .default_state  = LEDS_GPIO_DEFSTATE_ON,
-};
-
-static struct gpio_led_platform_data raumfeld_lt3593_platform_data = {
-        .leds           = &raumfeld_lt3593_led,
-        .num_leds       = 1,
-};
-
-static struct platform_device raumfeld_lt3593_device = {
-        .name   = "leds-lt3593",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &raumfeld_lt3593_platform_data,
-        },
-};
-
-static struct pxafb_mode_info sharp_lq043t3dx02_mode = {
-        .pixclock       = 111000,
-        .xres           = 480,
-        .yres           = 272,
-        .bpp            = 16,
-        .hsync_len      = 41,
-        .left_margin    = 2,
-        .right_margin   = 1,
-        .vsync_len      = 10,
-        .upper_margin   = 3,
-        .lower_margin   = 1,
-        .sync           = 0,
-};
-
-static struct pxafb_mach_info raumfeld_sharp_lcd_info = {
-        .modes          = &sharp_lq043t3dx02_mode,
-        .num_modes      = 1,
-        .video_mem_size = 0x400000,
-        .lcd_conn       = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
-#ifdef CONFIG_PXA3XX_GCU
-        .acceleration_enabled = 1,
-#endif
-};
-
-static void __init raumfeld_lcd_init(void)
-{
-        int ret;
-
-        ret = gpio_request(GPIO_TFT_VA_EN, "display VA enable");
-        if (ret < 0)
-                pr_warn("Unable to request GPIO_TFT_VA_EN\n");
-        else
-                gpio_direction_output(GPIO_TFT_VA_EN, 1);
-
-        msleep(100);
-
-        ret = gpio_request(GPIO_DISPLAY_ENABLE, "display enable");
-        if (ret < 0)
-                pr_warn("Unable to request GPIO_DISPLAY_ENABLE\n");
-        else
-                gpio_direction_output(GPIO_DISPLAY_ENABLE, 1);
-
-        /* Hardware revision 2 has the backlight regulator controlled
-         * by an LT3593, earlier and later devices use PWM for that. */
-        if ((system_rev & 0xff) == 2) {
-                platform_device_register(&raumfeld_lt3593_device);
-        } else {
-                mfp_cfg_t raumfeld_pwm_pin_config = GPIO17_PWM0_OUT;
-                pxa3xx_mfp_config(&raumfeld_pwm_pin_config, 1);
-                pwm_add_table(raumfeld_pwm_lookup,
-                              ARRAY_SIZE(raumfeld_pwm_lookup));
-                platform_device_register(&raumfeld_pwm_backlight_device);
-        }
-
-        pxa_set_fb_info(NULL, &raumfeld_sharp_lcd_info);
-        platform_device_register(&pxa3xx_device_gcu);
-}
-
-/**
- * SPI devices
- */
-
-static struct spi_gpio_platform_data raumfeld_spi_platform_data = {
-        .num_chipselect = 3,
-};
-
-static struct platform_device raumfeld_spi_device = {
-        .name   = "spi_gpio",
-        .id     = 0,
-        .dev    = {
-                .platform_data  = &raumfeld_spi_platform_data,
-        }
-};
-
-static struct gpiod_lookup_table raumfeld_spi_gpiod_table = {
-        .dev_id         = "spi_gpio",
-        .table          = {
-                GPIO_LOOKUP("gpio-0", GPIO_SPI_CLK,
-                            "sck", GPIO_ACTIVE_HIGH),
-                GPIO_LOOKUP("gpio-0", GPIO_SPI_MOSI,
-                            "mosi", GPIO_ACTIVE_HIGH),
-                GPIO_LOOKUP("gpio-0", GPIO_SPI_MISO,
-                            "miso", GPIO_ACTIVE_HIGH),
-                GPIO_LOOKUP_IDX("gpio-0", GPIO_SPDIF_CS,
-                                "cs", 0, GPIO_ACTIVE_HIGH),
-                GPIO_LOOKUP_IDX("gpio-0", GPIO_ACCEL_CS,
-                                "cs", 1, GPIO_ACTIVE_HIGH),
-                GPIO_LOOKUP_IDX("gpio-0", GPIO_MCLK_DAC_CS,
-                                "cs", 2, GPIO_ACTIVE_HIGH),
-                { },
-        },
-};
-
-static struct lis3lv02d_platform_data lis3_pdata = {
-        .click_flags    = LIS3_CLICK_SINGLE_X |
-                          LIS3_CLICK_SINGLE_Y |
-                          LIS3_CLICK_SINGLE_Z,
-        .irq_cfg        = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK,
-        .wakeup_flags   = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI |
-                          LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI |
-                          LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI,
-        .wakeup_thresh  = 10,
-        .click_thresh_x = 10,
-        .click_thresh_y = 10,
-        .click_thresh_z = 10,
-};
-
-#define SPI_AK4104      \
-{                       \
-        .modalias       = "ak4104-codec",       \
-        .max_speed_hz   = 10000,                \
-        .bus_num        = 0,                    \
-        .chip_select    = 0,                    \
-}
-
-#define SPI_LIS3        \
-{                       \
-        .modalias       = "lis3lv02d_spi",      \
-        .max_speed_hz   = 1000000,              \
-        .bus_num        = 0,                    \
-        .chip_select    = 1,                    \
-        .platform_data  = &lis3_pdata,          \
-        .irq            = PXA_GPIO_TO_IRQ(GPIO_ACCEL_IRQ),      \
-}
-
-#define SPI_DAC7512     \
-{       \
-        .modalias       = "dac7512",            \
-        .max_speed_hz   = 1000000,              \
-        .bus_num        = 0,                    \
-        .chip_select    = 2,                    \
-}
-
-static struct spi_board_info connector_spi_devices[] __initdata = {
-        SPI_AK4104,
-        SPI_DAC7512,
-};
-
-static struct spi_board_info speaker_spi_devices[] __initdata = {
-        SPI_DAC7512,
-};
-
-static struct spi_board_info controller_spi_devices[] __initdata = {
-        SPI_LIS3,
-};
-
-/**
- * MMC for Marvell Libertas 8688 via SDIO
- */
-
-static int raumfeld_mci_init(struct device *dev, irq_handler_t isr, void *data)
-{
-        gpio_set_value(GPIO_W2W_RESET, 1);
-        gpio_set_value(GPIO_W2W_PDN, 1);
-
-        return 0;
-}
-
-static void raumfeld_mci_exit(struct device *dev, void *data)
-{
-        gpio_set_value(GPIO_W2W_RESET, 0);
-        gpio_set_value(GPIO_W2W_PDN, 0);
-}
-
-static struct pxamci_platform_data raumfeld_mci_platform_data = {
-        .init                   = raumfeld_mci_init,
-        .exit                   = raumfeld_mci_exit,
-        .detect_delay_ms        = 200,
-};
-
-/*
- * External power / charge logic
- */
-
-static int power_supply_init(struct device *dev)
-{
-        return 0;
-}
-
-static void power_supply_exit(struct device *dev)
-{
-}
-
-static int raumfeld_is_ac_online(void)
-{
-        return !gpio_get_value(GPIO_CHARGE_DC_OK);
-}
-
-static int raumfeld_is_usb_online(void)
-{
-        return 0;
-}
-
-static char *raumfeld_power_supplicants[] = { "ds2760-battery.0" };
-
-static void raumfeld_power_signal_charged(void)
-{
-        struct power_supply *psy =
-                power_supply_get_by_name(raumfeld_power_supplicants[0]);
-
-        if (psy) {
-                power_supply_set_battery_charged(psy);
-                power_supply_put(psy);
-        }
-}
-
-static int raumfeld_power_resume(void)
-{
-        /* check if GPIO_CHARGE_DONE went low while we were sleeping */
-        if (!gpio_get_value(GPIO_CHARGE_DONE))
-                raumfeld_power_signal_charged();
-
-        return 0;
-}
-
-static struct pda_power_pdata power_supply_info = {
-        .init                   = power_supply_init,
-        .is_ac_online           = raumfeld_is_ac_online,
-        .is_usb_online          = raumfeld_is_usb_online,
-        .exit                   = power_supply_exit,
-        .supplied_to            = raumfeld_power_supplicants,
-        .num_supplicants        = ARRAY_SIZE(raumfeld_power_supplicants),
-        .resume                 = raumfeld_power_resume,
-};
-
-static struct resource power_supply_resources[] = {
-        {
-                .name  = "ac",
-                .flags = IORESOURCE_IRQ |
-                         IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE,
-                .start = GPIO_CHARGE_DC_OK,
-                .end   = GPIO_CHARGE_DC_OK,
-        },
-};
-
-static irqreturn_t charge_done_irq(int irq, void *dev_id)
-{
-        raumfeld_power_signal_charged();
-        return IRQ_HANDLED;
-}
-
-static struct platform_device raumfeld_power_supply = {
-        .name = "pda-power",
-        .id   = -1,
-        .dev  = {
-                .platform_data = &power_supply_info,
-        },
-        .resource      = power_supply_resources,
-        .num_resources = ARRAY_SIZE(power_supply_resources),
-};
-
-static void __init raumfeld_power_init(void)
-{
-        int ret;
-
-        /* Set PEN2 high to enable maximum charge current */
-        ret = gpio_request(GPIO_CHRG_PEN2, "CHRG_PEN2");
-        if (ret < 0)
-                pr_warn("Unable to request GPIO_CHRG_PEN2\n");
-        else
-                gpio_direction_output(GPIO_CHRG_PEN2, 1);
-
-        ret = gpio_request(GPIO_CHARGE_DC_OK, "CABLE_DC_OK");
-        if (ret < 0)
-                pr_warn("Unable to request GPIO_CHARGE_DC_OK\n");
-
-        ret = gpio_request(GPIO_CHARGE_USB_SUSP, "CHARGE_USB_SUSP");
-        if (ret < 0)
-                pr_warn("Unable to request GPIO_CHARGE_USB_SUSP\n");
-        else
-                gpio_direction_output(GPIO_CHARGE_USB_SUSP, 0);
-
-        power_supply_resources[0].start = gpio_to_irq(GPIO_CHARGE_DC_OK);
-        power_supply_resources[0].end = gpio_to_irq(GPIO_CHARGE_DC_OK);
-
-        ret = request_irq(gpio_to_irq(GPIO_CHARGE_DONE),
-                        &charge_done_irq, IORESOURCE_IRQ_LOWEDGE,
-                        "charge_done", NULL);
-
-        if (ret < 0)
-                printk(KERN_ERR "%s: unable to register irq %d\n", __func__,
-                        GPIO_CHARGE_DONE);
-        else
-                platform_device_register(&raumfeld_power_supply);
-}
-
-/* Fixed regulator for AUDIO_VA, 0-0048 maps to the cs4270 codec device */
-
-static struct regulator_consumer_supply audio_va_consumer_supply =
-        REGULATOR_SUPPLY("va", "0-0048");
-
-static struct regulator_init_data audio_va_initdata = {
-        .consumer_supplies = &audio_va_consumer_supply,
-        .num_consumer_supplies = 1,
-        .constraints = {
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-};
-
-static struct fixed_voltage_config audio_va_config = {
-        .supply_name            = "audio_va",
-        .microvolts             = 5000000,
-        .enable_high            = 1,
-        .enabled_at_boot        = 0,
-        .init_data              = &audio_va_initdata,
-};
-
-static struct platform_device audio_va_device = {
-        .name   = "reg-fixed-voltage",
-        .id     = 0,
-        .dev    = {
-                .platform_data = &audio_va_config,
-        },
-};
-
-static struct gpiod_lookup_table audio_va_gpiod_table = {
-        .dev_id = "reg-fixed-voltage.0",
-        .table = {
-                GPIO_LOOKUP("gpio-pxa", GPIO_AUDIO_VA_ENABLE,
-                            NULL, GPIO_ACTIVE_HIGH),
-                { },
-        },
-};
-
-/* Dummy supplies for Codec's VD/VLC */
-
-static struct regulator_consumer_supply audio_dummy_supplies[] = {
-        REGULATOR_SUPPLY("vd", "0-0048"),
-        REGULATOR_SUPPLY("vlc", "0-0048"),
-};
-
-static struct regulator_init_data audio_dummy_initdata = {
-        .consumer_supplies = audio_dummy_supplies,
-        .num_consumer_supplies = ARRAY_SIZE(audio_dummy_supplies),
-        .constraints = {
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-};
-
-static struct fixed_voltage_config audio_dummy_config = {
-        .supply_name            = "audio_vd",
-        .microvolts             = 3300000,
-        .init_data              = &audio_dummy_initdata,
-};
-
-static struct platform_device audio_supply_dummy_device = {
-        .name   = "reg-fixed-voltage",
-        .id     = 1,
-        .dev    = {
-                .platform_data = &audio_dummy_config,
-        },
-};
-
-static struct platform_device *audio_regulator_devices[] = {
-        &audio_va_device,
-        &audio_supply_dummy_device,
-};
-
-/**
- * Regulator support via MAX8660
- */
-
-static struct regulator_consumer_supply vcc_mmc_supply =
-        REGULATOR_SUPPLY("vmmc", "pxa2xx-mci.0");
-
-static struct regulator_init_data vcc_mmc_init_data = {
-        .constraints = {
-                .min_uV                 = 3300000,
-                .max_uV                 = 3300000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL,
-                .valid_ops_mask         = REGULATOR_CHANGE_STATUS |
-                                          REGULATOR_CHANGE_VOLTAGE |
-                                          REGULATOR_CHANGE_MODE,
-        },
-        .consumer_supplies = &vcc_mmc_supply,
-        .num_consumer_supplies = 1,
-};
-
-static struct max8660_subdev_data max8660_v6_subdev_data = {
-        .id             = MAX8660_V6,
-        .name           = "vmmc",
-        .platform_data  = &vcc_mmc_init_data,
-};
-
-static struct max8660_platform_data max8660_pdata = {
-        .subdevs = &max8660_v6_subdev_data,
-        .num_subdevs = 1,
-};
-
-/**
- * I2C devices
- */
-
-static struct i2c_board_info raumfeld_pwri2c_board_info = {
-        .type           = "max8660",
-        .addr           = 0x34,
-        .platform_data  = &max8660_pdata,
-};
-
-static struct i2c_board_info raumfeld_connector_i2c_board_info __initdata = {
-        .type   = "cs4270",
-        .addr   = 0x48,
-};
-
-static struct gpiod_lookup_table raumfeld_controller_gpios_table = {
-        .dev_id = "0-000a",
-        .table = {
-                GPIO_LOOKUP("gpio-pxa",
-                            GPIO_TOUCH_IRQ, "attn", GPIO_ACTIVE_HIGH),
-                { },
-        },
-};
-
-static const struct resource raumfeld_controller_resources[] __initconst = {
-        {
-                .start  = PXA_GPIO_TO_IRQ(GPIO_TOUCH_IRQ),
-                .end    = PXA_GPIO_TO_IRQ(GPIO_TOUCH_IRQ),
-                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
-        },
-};
-
-static struct i2c_board_info raumfeld_controller_i2c_board_info __initdata = {
-        .type   = "eeti_ts",
-        .addr   = 0x0a,
-        .resources = raumfeld_controller_resources,
-        .num_resources = ARRAY_SIZE(raumfeld_controller_resources),
-};
-
-static struct platform_device *raumfeld_common_devices[] = {
-        &raumfeld_gpio_keys_device,
-        &raumfeld_led_device,
-        &raumfeld_spi_device,
-};
-
-static void __init raumfeld_audio_init(void)
-{
-        int ret;
-
-        ret = gpio_request(GPIO_CODEC_RESET, "cs4270 reset");
-        if (ret < 0)
-                pr_warn("unable to request GPIO_CODEC_RESET\n");
-        else
-                gpio_direction_output(GPIO_CODEC_RESET, 1);
-
-        ret = gpio_request(GPIO_SPDIF_RESET, "ak4104 s/pdif reset");
-        if (ret < 0)
-                pr_warn("unable to request GPIO_SPDIF_RESET\n");
-        else
-                gpio_direction_output(GPIO_SPDIF_RESET, 1);
-
-        ret = gpio_request(GPIO_MCLK_RESET, "MCLK reset");
-        if (ret < 0)
-                pr_warn("unable to request GPIO_MCLK_RESET\n");
-        else
-                gpio_direction_output(GPIO_MCLK_RESET, 1);
-
-        gpiod_add_lookup_table(&audio_va_gpiod_table);
-        platform_add_devices(ARRAY_AND_SIZE(audio_regulator_devices));
-}
-
-static void __init raumfeld_common_init(void)
-{
-        int ret;
-
-        /* The on/off button polarity has changed after revision 1 */
-        if ((system_rev & 0xff) > 1) {
-                int i;
-
-                for (i = 0; i < ARRAY_SIZE(gpio_keys_button); i++)
-                        if (!strcmp(gpio_keys_button[i].desc, "on_off button"))
-                                gpio_keys_button[i].active_low = 1;
-        }
-
-        enable_irq_wake(IRQ_WAKEUP0);
-
-        pxa3xx_set_nand_info(&raumfeld_nand_info);
-        pxa3xx_set_i2c_power_info(NULL);
-        pxa_set_ohci_info(&raumfeld_ohci_info);
-        pxa_set_mci_info(&raumfeld_mci_platform_data);
-        pxa_set_i2c_info(NULL);
-        pxa_set_ffuart_info(NULL);
-
-        ret = gpio_request(GPIO_W2W_RESET, "Wi2Wi reset");
-        if (ret < 0)
-                pr_warn("Unable to request GPIO_W2W_RESET\n");
-        else
-                gpio_direction_output(GPIO_W2W_RESET, 0);
-
-        ret = gpio_request(GPIO_W2W_PDN, "Wi2Wi powerup");
-        if (ret < 0)
-                pr_warn("Unable to request GPIO_W2W_PDN\n");
-        else
-                gpio_direction_output(GPIO_W2W_PDN, 0);
-
-        /* this can be used to switch off the device */
-        ret = gpio_request(GPIO_SHUTDOWN_SUPPLY, "supply shutdown");
-        if (ret < 0)
-                pr_warn("Unable to request GPIO_SHUTDOWN_SUPPLY\n");
-        else
-                gpio_direction_output(GPIO_SHUTDOWN_SUPPLY, 0);
-
-        gpiod_add_lookup_table(&raumfeld_spi_gpiod_table);
-        platform_add_devices(ARRAY_AND_SIZE(raumfeld_common_devices));
-        i2c_register_board_info(1, &raumfeld_pwri2c_board_info, 1);
-}
-
-static void __init __maybe_unused raumfeld_controller_init(void)
-{
-        int ret;
-
-        pxa3xx_mfp_config(ARRAY_AND_SIZE(raumfeld_controller_pin_config));
-
-        gpiod_add_lookup_table(&raumfeld_rotary_gpios_table);
-        device_add_properties(&rotary_encoder_device.dev,
-                              raumfeld_rotary_properties);
-        platform_device_register(&rotary_encoder_device);
-
-        spi_register_board_info(ARRAY_AND_SIZE(controller_spi_devices));
-
-        gpiod_add_lookup_table(&raumfeld_controller_gpios_table);
-        i2c_register_board_info(0, &raumfeld_controller_i2c_board_info, 1);
-
-        ret = gpio_request(GPIO_SHUTDOWN_BATT, "battery shutdown");
-        if (ret < 0)
-                pr_warn("Unable to request GPIO_SHUTDOWN_BATT\n");
-        else
-                gpio_direction_output(GPIO_SHUTDOWN_BATT, 0);
-
-        raumfeld_common_init();
-        raumfeld_power_init();
-        raumfeld_lcd_init();
-        raumfeld_w1_init();
-}
-
-static void __init __maybe_unused raumfeld_connector_init(void)
-{
-        pxa3xx_mfp_config(ARRAY_AND_SIZE(raumfeld_connector_pin_config));
-        spi_register_board_info(ARRAY_AND_SIZE(connector_spi_devices));
-        i2c_register_board_info(0, &raumfeld_connector_i2c_board_info, 1);
-
-        platform_device_register(&smc91x_device);
-
-        raumfeld_audio_init();
-        raumfeld_common_init();
-}
-
-static void __init __maybe_unused raumfeld_speaker_init(void)
-{
-        pxa3xx_mfp_config(ARRAY_AND_SIZE(raumfeld_speaker_pin_config));
-        spi_register_board_info(ARRAY_AND_SIZE(speaker_spi_devices));
-        i2c_register_board_info(0, &raumfeld_connector_i2c_board_info, 1);
-
-        platform_device_register(&smc91x_device);
-
-        gpiod_add_lookup_table(&raumfeld_rotary_gpios_table);
-        device_add_properties(&rotary_encoder_device.dev,
-                              raumfeld_rotary_properties);
-        platform_device_register(&rotary_encoder_device);
-
-        raumfeld_audio_init();
-        raumfeld_common_init();
-}
-
-/* physical memory regions */
-#define RAUMFELD_SDRAM_BASE     0xa0000000      /* SDRAM region */
-
-#ifdef CONFIG_MACH_RAUMFELD_RC
-MACHINE_START(RAUMFELD_RC, "Raumfeld Controller")
-        .atag_offset    = 0x100,
-        .init_machine   = raumfeld_controller_init,
-        .map_io         = pxa3xx_map_io,
-        .nr_irqs        = PXA_NR_IRQS,
-        .init_irq       = pxa3xx_init_irq,
-        .handle_irq     = pxa3xx_handle_irq,
-        .init_time      = pxa_timer_init,
-        .restart        = pxa_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_RAUMFELD_CONNECTOR
-MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector")
-        .atag_offset    = 0x100,
-        .init_machine   = raumfeld_connector_init,
-        .map_io         = pxa3xx_map_io,
-        .nr_irqs        = PXA_NR_IRQS,
-        .init_irq       = pxa3xx_init_irq,
-        .handle_irq     = pxa3xx_handle_irq,
-        .init_time      = pxa_timer_init,
-        .restart        = pxa_restart,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_RAUMFELD_SPEAKER
-MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker")
-        .atag_offset    = 0x100,
-        .init_machine   = raumfeld_speaker_init,
-        .map_io         = pxa3xx_map_io,
-        .nr_irqs        = PXA_NR_IRQS,
-        .init_irq       = pxa3xx_init_irq,
-        .handle_irq     = pxa3xx_handle_irq,
-        .init_time      = pxa_timer_init,
-        .restart        = pxa_restart,
-MACHINE_END
-#endif
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 306818e2cf54..8dac824a85df 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -572,7 +572,7 @@ static struct spi_board_info spitz_spi_devices[] = {
         },
 };
 
-static struct pxa2xx_spi_master spitz_spi_info = {
+static struct pxa2xx_spi_controller spitz_spi_info = {
         .num_chipselect = 3,
 };
 
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index e0d6c872270a..c28d19b126a7 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -337,15 +337,15 @@ static struct platform_device stargate2_flash_device = {
         .num_resources = 1,
 };
 
-static struct pxa2xx_spi_master pxa_ssp_master_0_info = {
+static struct pxa2xx_spi_controller pxa_ssp_master_0_info = {
         .num_chipselect = 1,
 };
 
-static struct pxa2xx_spi_master pxa_ssp_master_1_info = {
+static struct pxa2xx_spi_controller pxa_ssp_master_1_info = {
         .num_chipselect = 1,
 };
 
-static struct pxa2xx_spi_master pxa_ssp_master_2_info = {
+static struct pxa2xx_spi_controller pxa_ssp_master_2_info = {
         .num_chipselect = 1,
 };
 
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index e8a93c088c35..7439798d58e4 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -813,7 +813,7 @@ static struct platform_device tosa_bt_device = {
         .dev.platform_data = &tosa_bt_data,
 };
 
-static struct pxa2xx_spi_master pxa_ssp_master_info = {
+static struct pxa2xx_spi_controller pxa_ssp_master_info = {
         .num_chipselect = 1,
 };
 
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index e2353e75bb28..ad082e11e2a4 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -607,12 +607,12 @@ static struct spi_board_info spi_board_info[] __initdata = {
 },
 };
 
-static struct pxa2xx_spi_master pxa_ssp1_master_info = {
+static struct pxa2xx_spi_controller pxa_ssp1_master_info = {
         .num_chipselect = 1,
         .enable_dma     = 1,
 };
 
-static struct pxa2xx_spi_master pxa_ssp2_master_info = {
+static struct pxa2xx_spi_controller pxa_ssp2_master_info = {
         .num_chipselect = 1,
 };
 
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index c411f79d4cb5..3fd1119c14d5 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -391,7 +391,7 @@ static struct platform_device zeus_sram_device = {
 };
 
 /* SPI interface on SSP3 */
-static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = {
+static struct pxa2xx_spi_controller pxa2xx_spi_ssp3_master_info = {
         .num_chipselect = 1,
         .enable_dma     = 1,
 };
@@ -426,7 +426,7 @@ static struct gpiod_lookup_table can_regulator_gpiod_table = {
         .dev_id = "reg-fixed-voltage.0",
         .table = {
                 GPIO_LOOKUP("gpio-pxa", ZEUS_CAN_SHDN_GPIO,
-                            NULL, GPIO_ACTIVE_HIGH),
+                            NULL, GPIO_ACTIVE_LOW),
                 { },
         },
 };
@@ -547,7 +547,6 @@ static struct regulator_init_data zeus_ohci_regulator_data = {
 static struct fixed_voltage_config zeus_ohci_regulator_config = {
         .supply_name            = "vbus2",
         .microvolts             = 5000000, /* 5.0V */
-        .enable_high            = 1,
         .startup_delay          = 0,
         .init_data              = &zeus_ohci_regulator_data,
 };
diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c
index 5494c9e0c909..99a6a5e809e0 100644
--- a/arch/arm/mach-qcom/platsmp.c
+++ b/arch/arm/mach-qcom/platsmp.c
@@ -46,8 +46,6 @@
 
 extern void secondary_startup_arm(void);
 
-static DEFINE_SPINLOCK(boot_lock);
-
 #ifdef CONFIG_HOTPLUG_CPU
 static void qcom_cpu_die(unsigned int cpu)
 {
@@ -55,15 +53,6 @@ static void qcom_cpu_die(unsigned int cpu)
 }
 #endif
 
-static void qcom_secondary_init(unsigned int cpu)
-{
-        /*
-         * Synchronise with the boot thread.
-         */
-        spin_lock(&boot_lock);
-        spin_unlock(&boot_lock);
-}
-
 static int scss_release_secondary(unsigned int cpu)
 {
         struct device_node *node;
@@ -281,24 +270,12 @@ static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
         }
 
         /*
-         * set synchronisation state between this boot processor
-         * and the secondary one
-         */
-        spin_lock(&boot_lock);
-
-        /*
          * Send the secondary CPU a soft interrupt, thereby causing
          * the boot monitor to read the system wide flags register,
          * and branch to the address found there.
          */
         arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 
-        /*
-         * now the secondary core is starting up let it run its
-         * calibrations, then wait for it to finish
-         */
-        spin_unlock(&boot_lock);
-
         return ret;
 }
 
@@ -334,7 +311,6 @@ static void __init qcom_smp_prepare_cpus(unsigned int max_cpus)
 
 static const struct smp_operations smp_msm8660_ops __initconst = {
         .smp_prepare_cpus       = qcom_smp_prepare_cpus,
-        .smp_secondary_init     = qcom_secondary_init,
         .smp_boot_secondary     = msm8660_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_die                = qcom_cpu_die,
@@ -344,7 +320,6 @@ CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops);
 
 static const struct smp_operations qcom_smp_kpssv1_ops __initconst = {
         .smp_prepare_cpus       = qcom_smp_prepare_cpus,
-        .smp_secondary_init     = qcom_secondary_init,
         .smp_boot_secondary     = kpssv1_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_die                = qcom_cpu_die,
@@ -354,7 +329,6 @@ CPU_METHOD_OF_DECLARE(qcom_smp_kpssv1, "qcom,kpss-acc-v1", &qcom_smp_kpssv1_ops)
 
 static const struct smp_operations qcom_smp_kpssv2_ops __initconst = {
         .smp_prepare_cpus       = qcom_smp_prepare_cpus,
-        .smp_secondary_init     = qcom_secondary_init,
         .smp_boot_secondary     = kpssv2_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_die                = qcom_cpu_die,
diff --git a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
index 058ce73137e8..5d819b6ea428 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
@@ -65,16 +65,16 @@ static int osiris_dvs_notify(struct notifier_block *nb,
 
         switch (val) {
         case CPUFREQ_PRECHANGE:
-                if (old_dvs & !new_dvs ||
-                    cur_dvs & !new_dvs) {
+                if ((old_dvs && !new_dvs) ||
+                    (cur_dvs && !new_dvs)) {
                         pr_debug("%s: exiting dvs\n", __func__);
                         cur_dvs = false;
                         gpio_set_value(OSIRIS_GPIO_DVS, 1);
                 }
                 break;
         case CPUFREQ_POSTCHANGE:
-                if (!old_dvs & new_dvs ||
-                    !cur_dvs & new_dvs) {
+                if ((!old_dvs && new_dvs) ||
+                    (!cur_dvs && new_dvs)) {
                         pr_debug("entering dvs\n");
                         cur_dvs = true;
                         gpio_set_value(OSIRIS_GPIO_DVS, 0);
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index dfa42496ec27..d09c3f236186 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -469,7 +469,6 @@ static struct regulator_consumer_supply assabet_cf_vcc_consumers[] = {
 static struct fixed_voltage_config assabet_cf_vcc_pdata __initdata = {
         .supply_name = "cf-power",
         .microvolts = 3300000,
-        .enable_high = 1,
 };
 
 static struct gpiod_lookup_table assabet_cf_vcc_gpio_table = {
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index 406487e76a5c..c7fb9a73e4c5 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -18,7 +18,6 @@
 #include <linux/mtd/partitions.h>
 #include <linux/io.h>
 #include <linux/gpio/driver.h>
-#include <linux/gpio/machine.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
diff --git a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
index 8e50daa99151..dc526ef2e9b3 100644
--- a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
@@ -40,6 +40,7 @@
 struct regulator_quirk {
         struct list_head                list;
         const struct of_device_id       *id;
+        struct device_node              *np;
         struct of_phandle_args          irq_args;
         struct i2c_msg                  i2c_msg;
         bool                            shared; /* IRQ line is shared */
@@ -101,6 +102,9 @@ static int regulator_quirk_notify(struct notifier_block *nb,
                 if (!pos->shared)
                         continue;
 
+                if (pos->np->parent != client->dev.parent->of_node)
+                        continue;
+
                 dev_info(&client->dev, "clearing %s@0x%02x interrupts\n",
                          pos->id->compatible, pos->i2c_msg.addr);
 
@@ -165,6 +169,7 @@ static int __init rcar_gen2_regulator_quirk(void)
                 memcpy(&quirk->i2c_msg, id->data, sizeof(quirk->i2c_msg));
 
                 quirk->id = id;
+                quirk->np = np;
                 quirk->i2c_msg.addr = addr;
 
                 ret = of_irq_parse_one(np, 0, argsa);
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 5fb6f79059a8..816da0eb6616 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -19,6 +19,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/reboot.h>
+#include <linux/reset/socfpga.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
@@ -64,6 +65,7 @@ static void __init socfpga_init_irq(void)
 
         if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
                 socfpga_init_ocram_ecc();
+        socfpga_reset_init();
 }
 
 static void __init socfpga_arria10_init_irq(void)
@@ -74,6 +76,7 @@ static void __init socfpga_arria10_init_irq(void)
                 socfpga_init_arria10_l2_ecc();
         if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
                 socfpga_init_arria10_ocram_ecc();
+        socfpga_reset_init();
 }
 
 static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
diff --git a/arch/arm/mach-spear/generic.h b/arch/arm/mach-spear/generic.h
index 909b97c0b237..25b4c5e66e39 100644
--- a/arch/arm/mach-spear/generic.h
+++ b/arch/arm/mach-spear/generic.h
@@ -20,6 +20,8 @@
 
 #include <asm/mach/time.h>
 
+extern volatile int spear_pen_release;
+
 extern void spear13xx_timer_init(void);
 extern void spear3xx_timer_init(void);
 extern struct pl022_ssp_controller pl022_plat_data;
diff --git a/arch/arm/mach-spear/headsmp.S b/arch/arm/mach-spear/headsmp.S
index c52192dc3d9f..6e250b6c0aa2 100644
--- a/arch/arm/mach-spear/headsmp.S
+++ b/arch/arm/mach-spear/headsmp.S
@@ -43,5 +43,5 @@ pen:	ldr	r7, [r6]
 
         .align
 1:      .long   .
-        .long   pen_release
+        .long   spear_pen_release
 ENDPROC(spear13xx_secondary_startup)
diff --git a/arch/arm/mach-spear/hotplug.c b/arch/arm/mach-spear/hotplug.c
index 12edd1cf8a12..0dd84f609627 100644
--- a/arch/arm/mach-spear/hotplug.c
+++ b/arch/arm/mach-spear/hotplug.c
@@ -16,6 +16,8 @@
 #include <asm/cp15.h>
 #include <asm/smp_plat.h>
 
+#include "generic.h"
+
 static inline void cpu_enter_lowpower(void)
 {
         unsigned int v;
@@ -57,7 +59,7 @@ static inline void spear13xx_do_lowpower(unsigned int cpu, int *spurious)
         for (;;) {
                 wfi();
 
-                if (pen_release == cpu) {
+                if (spear_pen_release == cpu) {
                         /*
                          * OK, proper wakeup, we're done
                          */
diff --git a/arch/arm/mach-spear/platsmp.c b/arch/arm/mach-spear/platsmp.c
index 39038a03836a..b1ff4bb86f6d 100644
--- a/arch/arm/mach-spear/platsmp.c
+++ b/arch/arm/mach-spear/platsmp.c
@@ -20,16 +20,21 @@
 #include <mach/spear.h>
 #include "generic.h"
 
+/* XXX spear_pen_release is cargo culted code - DO NOT COPY XXX */
+volatile int spear_pen_release = -1;
+
 /*
- * Write pen_release in a way that is guaranteed to be visible to all
- * observers, irrespective of whether they're taking part in coherency
+ * XXX CARGO CULTED CODE - DO NOT COPY XXX
+ *
+ * Write spear_pen_release in a way that is guaranteed to be visible to
+ * all observers, irrespective of whether they're taking part in coherency
  * or not.  This is necessary for the hotplug code to work reliably.
  */
-static void write_pen_release(int val)
+static void spear_write_pen_release(int val)
 {
-        pen_release = val;
+        spear_pen_release = val;
         smp_wmb();
-        sync_cache_w(&pen_release);
+        sync_cache_w(&spear_pen_release);
 }
 
 static DEFINE_SPINLOCK(boot_lock);
@@ -42,7 +47,7 @@ static void spear13xx_secondary_init(unsigned int cpu)
          * let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
-        write_pen_release(-1);
+        spear_write_pen_release(-1);
 
         /*
          * Synchronise with the boot thread.
@@ -64,17 +69,17 @@ static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
         /*
          * The secondary processor is waiting to be released from
          * the holding pen - release it, then wait for it to flag
-         * that it has been released by resetting pen_release.
+         * that it has been released by resetting spear_pen_release.
          *
-         * Note that "pen_release" is the hardware CPU ID, whereas
+         * Note that "spear_pen_release" is the hardware CPU ID, whereas
          * "cpu" is Linux's internal ID.
          */
-        write_pen_release(cpu);
+        spear_write_pen_release(cpu);
 
         timeout = jiffies + (1 * HZ);
         while (time_before(jiffies, timeout)) {
                 smp_rmb();
-                if (pen_release == -1)
+                if (spear_pen_release == -1)
                         break;
 
                 udelay(10);
@@ -86,7 +91,7 @@ static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
          */
         spin_unlock(&boot_lock);
 
-        return pen_release != -1 ? -ENOSYS : 0;
+        return spear_pen_release != -1 ? -ENOSYS : 0;
 }
 
 /*
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 8a7f301839c2..933b6930f024 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -14,6 +14,7 @@
 #include <linux/clocksource.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/reset/sunxi.h>
 
 #include <asm/mach/arch.h>
 #include <asm/secure_cntvoff.h>
@@ -37,7 +38,6 @@ static const char * const sun6i_board_dt_compat[] = {
         NULL,
 };
 
-extern void __init sun6i_reset_init(void);
 static void __init sun6i_timer_init(void)
 {
         of_clk_init(NULL);
diff --git a/arch/arm/mach-tango/pm.c b/arch/arm/mach-tango/pm.c
index 028e50c6383f..a32c3b631484 100644
--- a/arch/arm/mach-tango/pm.c
+++ b/arch/arm/mach-tango/pm.c
@@ -3,6 +3,7 @@
 #include <linux/suspend.h>
 #include <asm/suspend.h>
 #include "smc.h"
+#include "pm.h"
 
 static int tango_pm_powerdown(unsigned long arg)
 {
@@ -24,10 +25,7 @@ static const struct platform_suspend_ops tango_pm_ops = {
         .valid = suspend_valid_only_mem,
 };
 
-static int __init tango_pm_init(void)
+void __init tango_pm_init(void)
 {
         suspend_set_ops(&tango_pm_ops);
-        return 0;
 }
-
-late_initcall(tango_pm_init);
diff --git a/arch/arm/mach-tango/pm.h b/arch/arm/mach-tango/pm.h
new file mode 100644
index 000000000000..35ea705a0ee2
--- /dev/null
+++ b/arch/arm/mach-tango/pm.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifdef CONFIG_SUSPEND
+void __init tango_pm_init(void);
+#else
+#define tango_pm_init NULL
+#endif
diff --git a/arch/arm/mach-tango/setup.c b/arch/arm/mach-tango/setup.c
index 677dd7b5efd9..824f90737b04 100644
--- a/arch/arm/mach-tango/setup.c
+++ b/arch/arm/mach-tango/setup.c
@@ -2,6 +2,7 @@
 #include <asm/mach/arch.h>
 #include <asm/hardware/cache-l2x0.h>
 #include "smc.h"
+#include "pm.h"
 
 static void tango_l2c_write(unsigned long val, unsigned int reg)
 {
@@ -15,4 +16,5 @@ DT_MACHINE_START(TANGO_DT, "Sigma Tango DT")
         .dt_compat      = tango_dt_compat,
         .l2c_aux_mask   = ~0,
         .l2c_write_sec  = tango_l2c_write,
+        .init_late      = tango_pm_init,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index 9e5b2f869fc8..9bc291e76887 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -79,15 +79,24 @@
 #define TEGRA_PMC_BASE                  0x7000E400
 #define TEGRA_PMC_SIZE                  SZ_256
 
+#define TEGRA_MC_BASE                   0x7000F000
+#define TEGRA_MC_SIZE                   SZ_1K
+
 #define TEGRA_EMC_BASE                  0x7000F400
 #define TEGRA_EMC_SIZE                  SZ_1K
 
+#define TEGRA114_MC_BASE                0x70019000
+#define TEGRA114_MC_SIZE                SZ_4K
+
 #define TEGRA_EMC0_BASE                 0x7001A000
 #define TEGRA_EMC0_SIZE                 SZ_2K
 
 #define TEGRA_EMC1_BASE                 0x7001A800
 #define TEGRA_EMC1_SIZE                 SZ_2K
 
+#define TEGRA124_MC_BASE                0x70019000
+#define TEGRA124_MC_SIZE                SZ_4K
+
 #define TEGRA124_EMC_BASE               0x7001B000
 #define TEGRA124_EMC_SIZE               SZ_2K
 
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 805f306fa6f7..e22ccf87eded 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -172,7 +172,7 @@ after_errata:
         mov32   r5, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET
         mov     r0, #CPU_NOT_RESETTABLE
         cmp     r10, #0
-        strneb  r0, [r5, #__tegra20_cpu1_resettable_status_offset]
+        strbne  r0, [r5, #__tegra20_cpu1_resettable_status_offset]
 1:
 #endif
 
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index 5c8e638ee51a..dedeebfccc55 100644
--- a/arch/arm/mach-tegra/sleep-tegra20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -32,7 +32,6 @@
 
 #define EMC_CFG                         0xc
 #define EMC_ADR_CFG                     0x10
-#define EMC_REFRESH                     0x70
 #define EMC_NOP                         0xdc
 #define EMC_SELF_REF                    0xe0
 #define EMC_REQ_CTRL                    0x2b0
@@ -397,7 +396,6 @@ padload_done:
         mov     r1, #1
         str     r1, [r0, #EMC_NOP]
         str     r1, [r0, #EMC_NOP]
-        str     r1, [r0, #EMC_REFRESH]
 
         emc_device_mask r1, r0
 
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index dd4a67dabd91..d0b4c486ddbf 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -29,7 +29,6 @@
 #define EMC_CFG                         0xc
 #define EMC_ADR_CFG                     0x10
 #define EMC_TIMING_CONTROL              0x28
-#define EMC_REFRESH                     0x70
 #define EMC_NOP                         0xdc
 #define EMC_SELF_REF                    0xe0
 #define EMC_MRW                         0xe8
@@ -45,6 +44,8 @@
 #define EMC_XM2VTTGENPADCTRL            0x310
 #define EMC_XM2VTTGENPADCTRL2           0x314
 
+#define MC_EMEM_ARB_CFG                 0x90
+
 #define PMC_CTRL                        0x0
 #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
 
@@ -419,6 +420,22 @@ _pll_m_c_x_done:
         movweq  r0, #:lower16:TEGRA124_EMC_BASE
         movteq  r0, #:upper16:TEGRA124_EMC_BASE
 
+        cmp     r10, #TEGRA30
+        moveq   r2, #0x20
+        movweq  r4, #:lower16:TEGRA_MC_BASE
+        movteq  r4, #:upper16:TEGRA_MC_BASE
+        cmp     r10, #TEGRA114
+        moveq   r2, #0x34
+        movweq  r4, #:lower16:TEGRA114_MC_BASE
+        movteq  r4, #:upper16:TEGRA114_MC_BASE
+        cmp     r10, #TEGRA124
+        moveq   r2, #0x20
+        movweq  r4, #:lower16:TEGRA124_MC_BASE
+        movteq  r4, #:upper16:TEGRA124_MC_BASE
+
+        ldr     r1, [r5, r2]            @ restore MC_EMEM_ARB_CFG
+        str     r1, [r4, #MC_EMEM_ARB_CFG]
+
 exit_self_refresh:
         ldr     r1, [r5, #0xC]          @ restore EMC_XM2VTTGENPADCTRL
         str     r1, [r0, #EMC_XM2VTTGENPADCTRL]
@@ -459,7 +476,6 @@ emc_wait_auto_cal_onetime:
         cmp     r10, #TEGRA30
         streq   r1, [r0, #EMC_NOP]
         streq   r1, [r0, #EMC_NOP]
-        streq   r1, [r0, #EMC_REFRESH]
 
         emc_device_mask r1, r0
 
@@ -521,6 +537,8 @@ zcal_done:
         ldr     r1, [r5, #0x0]          @ restore EMC_CFG
         str     r1, [r0, #EMC_CFG]
 
+        emc_timing_update r1, r0
+
         /* Tegra114 had dual EMC channel, now config the other one */
         cmp     r10, #TEGRA114
         bne     __no_dual_emc_chanl
@@ -546,6 +564,7 @@ tegra30_sdram_pad_address:
         .word   TEGRA_PMC_BASE + PMC_IO_DPD_STATUS                      @0x14
         .word   TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT     @0x18
         .word   TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST             @0x1c
+        .word   TEGRA_MC_BASE + MC_EMEM_ARB_CFG                         @0x20
 tegra30_sdram_pad_address_end:
 
 tegra114_sdram_pad_address:
@@ -562,6 +581,7 @@ tegra114_sdram_pad_address:
         .word   TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL                 @0x28
         .word   TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL                  @0x2c
         .word   TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2                 @0x30
+        .word   TEGRA114_MC_BASE + MC_EMEM_ARB_CFG                      @0x34
 tegra114_sdram_pad_adress_end:
 
 tegra124_sdram_pad_address:
@@ -573,6 +593,7 @@ tegra124_sdram_pad_address:
         .word   TEGRA_PMC_BASE + PMC_IO_DPD_STATUS                      @0x14
         .word   TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT     @0x18
         .word   TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST             @0x1c
+        .word   TEGRA124_MC_BASE + MC_EMEM_ARB_CFG                      @0x20
 tegra124_sdram_pad_address_end:
 
 tegra30_sdram_pad_size:
diff --git a/arch/arm/mm/cache-l2x0-pmu.c b/arch/arm/mm/cache-l2x0-pmu.c
index afe5b4c7b164..99bcd074916a 100644
--- a/arch/arm/mm/cache-l2x0-pmu.c
+++ b/arch/arm/mm/cache-l2x0-pmu.c
@@ -314,14 +314,6 @@ static int l2x0_pmu_event_init(struct perf_event *event)
             event->attach_state & PERF_ATTACH_TASK)
                 return -EINVAL;
 
-        if (event->attr.exclude_user   ||
-            event->attr.exclude_kernel ||
-            event->attr.exclude_hv     ||
-            event->attr.exclude_idle   ||
-            event->attr.exclude_host   ||
-            event->attr.exclude_guest)
-                return -EINVAL;
-
         if (event->cpu < 0)
                 return -EINVAL;
 
@@ -544,6 +536,7 @@ static __init int l2x0_pmu_init(void)
                 .del = l2x0_pmu_event_del,
                 .event_init = l2x0_pmu_event_init,
                 .attr_groups = l2x0_pmu_attr_groups,
+                .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
         };
 
         l2x0_pmu_reset();
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 24659952c278..be68d62566c7 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -215,8 +215,8 @@ v6_dma_inv_range:
 #endif
         tst     r1, #D_CACHE_LINE_SIZE - 1
 #ifdef CONFIG_DMA_CACHE_RWFO
-        ldrneb  r2, [r1, #-1]                   @ read for ownership
-        strneb  r2, [r1, #-1]                   @ write for ownership
+        ldrbne  r2, [r1, #-1]                   @ read for ownership
+        strbne  r2, [r1, #-1]                   @ write for ownership
 #endif
         bic     r1, r1, #D_CACHE_LINE_SIZE - 1
 #ifdef HARVARD_CACHE
@@ -284,8 +284,8 @@ ENTRY(v6_dma_flush_range)
         add     r0, r0, #D_CACHE_LINE_SIZE
         cmp     r0, r1
 #ifdef CONFIG_DMA_CACHE_RWFO
-        ldrlob  r2, [r0]                        @ read for ownership
-        strlob  r2, [r0]                        @ write for ownership
+        ldrblo  r2, [r0]                        @ read for ownership
+        strblo  r2, [r0]                        @ write for ownership
 #endif
         blo     1b
         mov     r0, #0
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index b03202cddddb..f74cdce6d4da 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -45,6 +45,7 @@ static void mc_copy_user_page(void *from, void *to)
         int tmp;
 
         asm volatile ("\
+        .syntax unified\n\
         ldmia   %0!, {r2, r3, ip, lr}           @ 4\n\
 1:      mcr     p15, 0, %1, c7, c6, 1           @ 1   invalidate D line\n\
         stmia   %1!, {r2, r3, ip, lr}           @ 4\n\
@@ -56,7 +57,7 @@ static void mc_copy_user_page(void *from, void *to)
         ldmia   %0!, {r2, r3, ip, lr}           @ 4\n\
         subs    %2, %2, #1                      @ 1\n\
         stmia   %1!, {r2, r3, ip, lr}           @ 4\n\
-        ldmneia %0!, {r2, r3, ip, lr}           @ 4\n\
+        ldmiane %0!, {r2, r3, ip, lr}           @ 4\n\
         bne     1b                              @ "
         : "+&r" (from), "+&r" (to), "=&r" (tmp)
         : "2" (PAGE_SIZE / 64)
diff --git a/arch/arm/mm/copypage-v4wb.c b/arch/arm/mm/copypage-v4wb.c
index cd3e165afeed..6d336740aae4 100644
--- a/arch/arm/mm/copypage-v4wb.c
+++ b/arch/arm/mm/copypage-v4wb.c
@@ -27,6 +27,7 @@ static void v4wb_copy_user_page(void *kto, const void *kfrom)
         int tmp;
 
         asm volatile ("\
+        .syntax unified\n\
         ldmia   %1!, {r3, r4, ip, lr}           @ 4\n\
 1:      mcr     p15, 0, %0, c7, c6, 1           @ 1   invalidate D line\n\
         stmia   %0!, {r3, r4, ip, lr}           @ 4\n\
@@ -38,7 +39,7 @@ static void v4wb_copy_user_page(void *kto, const void *kfrom)
         ldmia   %1!, {r3, r4, ip, lr}           @ 4\n\
         subs    %2, %2, #1                      @ 1\n\
         stmia   %0!, {r3, r4, ip, lr}           @ 4\n\
-        ldmneia %1!, {r3, r4, ip, lr}           @ 4\n\
+        ldmiane %1!, {r3, r4, ip, lr}           @ 4\n\
         bne     1b                              @ 1\n\
         mcr     p15, 0, %1, c7, c10, 4          @ 1   drain WB"
         : "+&r" (kto), "+&r" (kfrom), "=&r" (tmp)
diff --git a/arch/arm/mm/copypage-v4wt.c b/arch/arm/mm/copypage-v4wt.c
index 8614572e1296..3851bb396442 100644
--- a/arch/arm/mm/copypage-v4wt.c
+++ b/arch/arm/mm/copypage-v4wt.c
@@ -25,6 +25,7 @@ static void v4wt_copy_user_page(void *kto, const void *kfrom)
         int tmp;
 
         asm volatile ("\
+        .syntax unified\n\
         ldmia   %1!, {r3, r4, ip, lr}           @ 4\n\
 1:      stmia   %0!, {r3, r4, ip, lr}           @ 4\n\
         ldmia   %1!, {r3, r4, ip, lr}           @ 4+1\n\
@@ -34,7 +35,7 @@ static void v4wt_copy_user_page(void *kto, const void *kfrom)
         ldmia   %1!, {r3, r4, ip, lr}           @ 4\n\
         subs    %2, %2, #1                      @ 1\n\
         stmia   %0!, {r3, r4, ip, lr}           @ 4\n\
-        ldmneia %1!, {r3, r4, ip, lr}           @ 4\n\
+        ldmiane %1!, {r3, r4, ip, lr}           @ 4\n\
         bne     1b                              @ 1\n\
         mcr     p15, 0, %2, c7, c7, 0           @ flush ID cache"
         : "+&r" (kto), "+&r" (kfrom), "=&r" (tmp)
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index f1e2922e447c..43f46aa7ef33 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -188,6 +188,7 @@ const struct dma_map_ops arm_dma_ops = {
         .unmap_page             = arm_dma_unmap_page,
         .map_sg                 = arm_dma_map_sg,
         .unmap_sg               = arm_dma_unmap_sg,
+        .map_resource           = dma_direct_map_resource,
         .sync_single_for_cpu    = arm_dma_sync_single_for_cpu,
         .sync_single_for_device = arm_dma_sync_single_for_device,
         .sync_sg_for_cpu        = arm_dma_sync_sg_for_cpu,
@@ -211,6 +212,7 @@ const struct dma_map_ops arm_coherent_dma_ops = {
         .get_sgtable            = arm_dma_get_sgtable,
         .map_page               = arm_coherent_dma_map_page,
         .map_sg                 = arm_dma_map_sg,
+        .map_resource           = dma_direct_map_resource,
         .dma_supported          = arm_dma_supported,
 };
 EXPORT_SYMBOL(arm_coherent_dma_ops);
@@ -2277,7 +2279,7 @@ EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
  * @dev: valid struct device pointer
  *
  * Detaches the provided device from a previously attached map.
- * This voids the dma operations (dma_map_ops pointer)
+ * This overwrites the dma_ops pointer with appropriate non-IOMMU ops.
  */
 void arm_iommu_detach_device(struct device *dev)
 {
@@ -2390,4 +2392,6 @@ void arch_teardown_dma_ops(struct device *dev)
                 return;
 
         arm_teardown_iommu_dma_ops(dev);
+        /* Let arch_setup_dma_ops() start again from scratch upon re-probe */
+        set_dma_ops(dev, NULL);
 }
diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c
index 1d1edd064199..a033f6134a64 100644
--- a/arch/arm/mm/idmap.c
+++ b/arch/arm/mm/idmap.c
@@ -6,6 +6,7 @@
 
 #include <asm/cputype.h>
 #include <asm/idmap.h>
+#include <asm/hwcap.h>
 #include <asm/pgalloc.h>
 #include <asm/pgtable.h>
 #include <asm/sections.h>
@@ -110,7 +111,8 @@ static int __init init_static_idmap(void)
                              __idmap_text_end, 0);
 
         /* Flush L1 for the hardware to see this page table content */
-        flush_cache_louis();
+        if (!(elf_hwcap & HWCAP_LPAE))
+                flush_cache_louis();
 
         return 0;
 }
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 478ea8b7db87..c2daabbe0af0 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -205,7 +205,11 @@ phys_addr_t __init arm_memblock_steal(phys_addr_t size, phys_addr_t align)
 
         BUG_ON(!arm_memblock_steal_permitted);
 
-        phys = memblock_alloc_base(size, align, MEMBLOCK_ALLOC_ANYWHERE);
+        phys = memblock_phys_alloc(size, align);
+        if (!phys)
+                panic("Failed to steal %pa bytes at %pS\n",
+                      &size, (void *)_RET_IP_);
+
         memblock_free(phys, size);
         memblock_remove(phys, size);
 
@@ -278,15 +282,12 @@ void __init arm_memblock_init(const struct machine_desc *mdesc)
 
 void __init bootmem_init(void)
 {
-        unsigned long min, max_low, max_high;
-
         memblock_allow_resize();
-        max_low = max_high = 0;
 
-        find_limits(&min, &max_low, &max_high);
+        find_limits(&min_low_pfn, &max_low_pfn, &max_pfn);
 
-        early_memtest((phys_addr_t)min << PAGE_SHIFT,
-                      (phys_addr_t)max_low << PAGE_SHIFT);
+        early_memtest((phys_addr_t)min_low_pfn << PAGE_SHIFT,
+                      (phys_addr_t)max_low_pfn << PAGE_SHIFT);
 
         /*
          * Sparsemem tries to allocate bootmem in memory_present(),
@@ -304,16 +305,7 @@ void __init bootmem_init(void)
          * the sparse mem_map arrays initialized by sparse_init()
          * for memmap_init_zone(), otherwise all PFNs are invalid.
          */
-        zone_sizes_init(min, max_low, max_high);
-
-        /*
-         * This doesn't seem to be used by the Linux memory manager any
-         * more, but is used by ll_rw_block.  If we can get rid of it, we
-         * also get rid of some of the stuff above as well.
-         */
-        min_low_pfn = min;
-        max_low_pfn = max_low;
-        max_pfn = max_high;
+        zone_sizes_init(min_low_pfn, max_low_pfn, max_pfn);
 }
 
 /*
@@ -494,55 +486,6 @@ void __init mem_init(void)
 
         mem_init_print_info(NULL);
 
-#define MLK(b, t) b, t, ((t) - (b)) >> 10
-#define MLM(b, t) b, t, ((t) - (b)) >> 20
-#define MLK_ROUNDUP(b, t) b, t, DIV_ROUND_UP(((t) - (b)), SZ_1K)
-
-        pr_notice("Virtual kernel memory layout:\n"
-                        "    vector  : 0x%08lx - 0x%08lx   (%4ld kB)\n"
-#ifdef CONFIG_HAVE_TCM
-                        "    DTCM    : 0x%08lx - 0x%08lx   (%4ld kB)\n"
-                        "    ITCM    : 0x%08lx - 0x%08lx   (%4ld kB)\n"
-#endif
-                        "    fixmap  : 0x%08lx - 0x%08lx   (%4ld kB)\n"
-                        "    vmalloc : 0x%08lx - 0x%08lx   (%4ld MB)\n"
-                        "    lowmem  : 0x%08lx - 0x%08lx   (%4ld MB)\n"
-#ifdef CONFIG_HIGHMEM
-                        "    pkmap   : 0x%08lx - 0x%08lx   (%4ld MB)\n"
-#endif
-#ifdef CONFIG_MODULES
-                        "    modules : 0x%08lx - 0x%08lx   (%4ld MB)\n"
-#endif
-                        "      .text : 0x%p" " - 0x%p" "   (%4td kB)\n"
-                        "      .init : 0x%p" " - 0x%p" "   (%4td kB)\n"
-                        "      .data : 0x%p" " - 0x%p" "   (%4td kB)\n"
-                        "       .bss : 0x%p" " - 0x%p" "   (%4td kB)\n",
-
-                        MLK(VECTORS_BASE, VECTORS_BASE + PAGE_SIZE),
-#ifdef CONFIG_HAVE_TCM
-                        MLK(DTCM_OFFSET, (unsigned long) dtcm_end),
-                        MLK(ITCM_OFFSET, (unsigned long) itcm_end),
-#endif
-                        MLK(FIXADDR_START, FIXADDR_END),
-                        MLM(VMALLOC_START, VMALLOC_END),
-                        MLM(PAGE_OFFSET, (unsigned long)high_memory),
-#ifdef CONFIG_HIGHMEM
-                        MLM(PKMAP_BASE, (PKMAP_BASE) + (LAST_PKMAP) *
-                                (PAGE_SIZE)),
-#endif
-#ifdef CONFIG_MODULES
-                        MLM(MODULES_VADDR, MODULES_END),
-#endif
-
-                        MLK_ROUNDUP(_text, _etext),
-                        MLK_ROUNDUP(__init_begin, __init_end),
-                        MLK_ROUNDUP(_sdata, _edata),
-                        MLK_ROUNDUP(__bss_start, __bss_stop));
-
-#undef MLK
-#undef MLM
-#undef MLK_ROUNDUP
-
         /*
          * Check boundaries twice: Some fundamental inconsistencies can
          * be detected at build time already.
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index f5cc1ccfea3d..f3ce34113f89 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -719,16 +719,15 @@ EXPORT_SYMBOL(phys_mem_access_prot);
 
 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 
-static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
-{
-        void *ptr = __va(memblock_phys_alloc(sz, align));
-        memset(ptr, 0, sz);
-        return ptr;
-}
-
 static void __init *early_alloc(unsigned long sz)
 {
-        return early_alloc_aligned(sz, sz);
+        void *ptr = memblock_alloc(sz, sz);
+
+        if (!ptr)
+                panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
+                      __func__, sz, sz);
+
+        return ptr;
 }
 
 static void *__init late_alloc(unsigned long sz)
@@ -1000,7 +999,10 @@ void __init iotable_init(struct map_desc *io_desc, int nr)
         if (!nr)
                 return;
 
-        svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
+        svm = memblock_alloc(sizeof(*svm) * nr, __alignof__(*svm));
+        if (!svm)
+                panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
+                      __func__, sizeof(*svm) * nr, __alignof__(*svm));
 
         for (md = io_desc; nr; md++, nr--) {
                 create_mapping(md);
@@ -1022,7 +1024,10 @@ void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
         struct vm_struct *vm;
         struct static_vm *svm;
 
-        svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
+        svm = memblock_alloc(sizeof(*svm), __alignof__(*svm));
+        if (!svm)
+                panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
+                      __func__, sizeof(*svm), __alignof__(*svm));
 
         vm = &svm->vm;
         vm->addr = (void *)addr;
diff --git a/arch/arm/mm/pmsa-v8.c b/arch/arm/mm/pmsa-v8.c
index 617a83def88a..0d7d5fb59247 100644
--- a/arch/arm/mm/pmsa-v8.c
+++ b/arch/arm/mm/pmsa-v8.c
@@ -165,7 +165,7 @@ static int __init pmsav8_setup_ram(unsigned int number, phys_addr_t start,phys_a
                 return -EINVAL;
 
         bar = start;
-        lar = (end - 1) & ~(PMSAv8_MINALIGN - 1);;
+        lar = (end - 1) & ~(PMSAv8_MINALIGN - 1);
 
         bar |= PMSAv8_AP_PL1RW_PL0RW | PMSAv8_RGN_SHARED;
         lar |= PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN;
@@ -181,7 +181,7 @@ static int __init pmsav8_setup_io(unsigned int number, phys_addr_t start,phys_ad
                 return -EINVAL;
 
         bar = start;
-        lar = (end - 1) & ~(PMSAv8_MINALIGN - 1);;
+        lar = (end - 1) & ~(PMSAv8_MINALIGN - 1);
 
         bar |= PMSAv8_AP_PL1RW_PL0RW | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN;
         lar |= PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN;
diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
index 47a5acc64433..acd5a66dfc23 100644
--- a/arch/arm/mm/proc-v7m.S
+++ b/arch/arm/mm/proc-v7m.S
@@ -139,6 +139,9 @@ __v7m_setup_cont:
         cpsie   i
         svc     #0
 1:      cpsid   i
+        ldr     r0, =exc_ret
+        orr     lr, lr, #EXC_RET_THREADMODE_PROCESSSTACK
+        str     lr, [r0]
         ldmia   sp, {r0-r3, r12}
         str     r5, [r12, #11 * 4]      @ restore the original SVC vector entry
         mov     lr, r6                  @ restore LR
@@ -149,10 +152,10 @@ __v7m_setup_cont:
 
         @ Configure caches (if implemented)
         teq     r8, #0
-        stmneia sp, {r0-r6, lr}         @ v7m_invalidate_l1 touches r0-r6
+        stmiane sp, {r0-r6, lr}         @ v7m_invalidate_l1 touches r0-r6
         blne    v7m_invalidate_l1
         teq     r8, #0                  @ re-evalutae condition
-        ldmneia sp, {r0-r6, lr}
+        ldmiane sp, {r0-r6, lr}
 
         @ Configure the System Control Register to ensure 8-byte stack alignment
         @ Note the STKALIGN bit is either RW or RAO.
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index 25b3ee85066e..c8bfbbfdfcc3 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -1083,12 +1083,17 @@ static inline void emit_ldx_r(const s8 dst[], const s8 src,
 
 /* Arithmatic Operation */
 static inline void emit_ar_r(const u8 rd, const u8 rt, const u8 rm,
-                             const u8 rn, struct jit_ctx *ctx, u8 op) {
+                             const u8 rn, struct jit_ctx *ctx, u8 op,
+                             bool is_jmp64) {
         switch (op) {
         case BPF_JSET:
-                emit(ARM_AND_R(ARM_IP, rt, rn), ctx);
-                emit(ARM_AND_R(ARM_LR, rd, rm), ctx);
-                emit(ARM_ORRS_R(ARM_IP, ARM_LR, ARM_IP), ctx);
+                if (is_jmp64) {
+                        emit(ARM_AND_R(ARM_IP, rt, rn), ctx);
+                        emit(ARM_AND_R(ARM_LR, rd, rm), ctx);
+                        emit(ARM_ORRS_R(ARM_IP, ARM_LR, ARM_IP), ctx);
+                } else {
+                        emit(ARM_ANDS_R(ARM_IP, rt, rn), ctx);
+                }
                 break;
         case BPF_JEQ:
         case BPF_JNE:
@@ -1096,18 +1101,25 @@ static inline void emit_ar_r(const u8 rd, const u8 rt, const u8 rm,
         case BPF_JGE:
         case BPF_JLE:
         case BPF_JLT:
-                emit(ARM_CMP_R(rd, rm), ctx);
-                _emit(ARM_COND_EQ, ARM_CMP_R(rt, rn), ctx);
+                if (is_jmp64) {
+                        emit(ARM_CMP_R(rd, rm), ctx);
+                        /* Only compare low halve if high halve are equal. */
+                        _emit(ARM_COND_EQ, ARM_CMP_R(rt, rn), ctx);
+                } else {
+                        emit(ARM_CMP_R(rt, rn), ctx);
+                }
                 break;
         case BPF_JSLE:
         case BPF_JSGT:
                 emit(ARM_CMP_R(rn, rt), ctx);
-                emit(ARM_SBCS_R(ARM_IP, rm, rd), ctx);
+                if (is_jmp64)
+                        emit(ARM_SBCS_R(ARM_IP, rm, rd), ctx);
                 break;
         case BPF_JSLT:
         case BPF_JSGE:
                 emit(ARM_CMP_R(rt, rn), ctx);
-                emit(ARM_SBCS_R(ARM_IP, rd, rm), ctx);
+                if (is_jmp64)
+                        emit(ARM_SBCS_R(ARM_IP, rd, rm), ctx);
                 break;
         }
 }
@@ -1615,6 +1627,17 @@ exit:
         case BPF_JMP | BPF_JLT | BPF_X:
         case BPF_JMP | BPF_JSLT | BPF_X:
         case BPF_JMP | BPF_JSLE | BPF_X:
+        case BPF_JMP32 | BPF_JEQ | BPF_X:
+        case BPF_JMP32 | BPF_JGT | BPF_X:
+        case BPF_JMP32 | BPF_JGE | BPF_X:
+        case BPF_JMP32 | BPF_JNE | BPF_X:
+        case BPF_JMP32 | BPF_JSGT | BPF_X:
+        case BPF_JMP32 | BPF_JSGE | BPF_X:
+        case BPF_JMP32 | BPF_JSET | BPF_X:
+        case BPF_JMP32 | BPF_JLE | BPF_X:
+        case BPF_JMP32 | BPF_JLT | BPF_X:
+        case BPF_JMP32 | BPF_JSLT | BPF_X:
+        case BPF_JMP32 | BPF_JSLE | BPF_X:
                 /* Setup source registers */
                 rm = arm_bpf_get_reg32(src_hi, tmp2[0], ctx);
                 rn = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
@@ -1641,6 +1664,17 @@ exit:
         case BPF_JMP | BPF_JLE | BPF_K:
         case BPF_JMP | BPF_JSLT | BPF_K:
         case BPF_JMP | BPF_JSLE | BPF_K:
+        case BPF_JMP32 | BPF_JEQ | BPF_K:
+        case BPF_JMP32 | BPF_JGT | BPF_K:
+        case BPF_JMP32 | BPF_JGE | BPF_K:
+        case BPF_JMP32 | BPF_JNE | BPF_K:
+        case BPF_JMP32 | BPF_JSGT | BPF_K:
+        case BPF_JMP32 | BPF_JSGE | BPF_K:
+        case BPF_JMP32 | BPF_JSET | BPF_K:
+        case BPF_JMP32 | BPF_JLT | BPF_K:
+        case BPF_JMP32 | BPF_JLE | BPF_K:
+        case BPF_JMP32 | BPF_JSLT | BPF_K:
+        case BPF_JMP32 | BPF_JSLE | BPF_K:
                 if (off == 0)
                         break;
                 rm = tmp2[0];
@@ -1652,7 +1686,8 @@ go_jmp:
                 rd = arm_bpf_get_reg64(dst, tmp, ctx);
 
                 /* Check for the condition */
-                emit_ar_r(rd[0], rd[1], rm, rn, ctx, BPF_OP(code));
+                emit_ar_r(rd[0], rd[1], rm, rn, ctx, BPF_OP(code),
+                          BPF_CLASS(code) == BPF_JMP);
 
                 /* Setup JUMP instruction */
                 jmp_offset = bpf2a32_offset(i+off, i, ctx);
diff --git a/arch/arm/net/bpf_jit_32.h b/arch/arm/net/bpf_jit_32.h
index f4e58bcdaa43..13a05f759552 100644
--- a/arch/arm/net/bpf_jit_32.h
+++ b/arch/arm/net/bpf_jit_32.h
@@ -62,6 +62,7 @@
 #define ARM_INST_ADDS_I         0x02900000
 
 #define ARM_INST_AND_R          0x00000000
+#define ARM_INST_ANDS_R         0x00100000
 #define ARM_INST_AND_I          0x02000000
 
 #define ARM_INST_BIC_R          0x01c00000
@@ -172,6 +173,7 @@
 #define ARM_ADC_I(rd, rn, imm)  _AL3_I(ARM_INST_ADC, rd, rn, imm)
 
 #define ARM_AND_R(rd, rn, rm)   _AL3_R(ARM_INST_AND, rd, rn, rm)
+#define ARM_ANDS_R(rd, rn, rm)  _AL3_R(ARM_INST_ANDS, rd, rn, rm)
 #define ARM_AND_I(rd, rn, imm)  _AL3_I(ARM_INST_AND, rd, rn, imm)
 
 #define ARM_BIC_R(rd, rn, rm)   _AL3_R(ARM_INST_BIC, rd, rn, rm)
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index a2399fd66e97..a6c81ce00f52 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -18,7 +18,7 @@
 #include <linux/clkdev.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/mv643xx_i2c.h>
-#include <net/dsa.h>
+#include <linux/platform_data/dsa.h>
 #include <linux/platform_data/dma-mv_xor.h>
 #include <linux/platform_data/usb-ehci-orion.h>
 #include <plat/common.h>
diff --git a/arch/arm/plat-pxa/ssp.c b/arch/arm/plat-pxa/ssp.c
index ed36dcab80f1..f51919974183 100644
--- a/arch/arm/plat-pxa/ssp.c
+++ b/arch/arm/plat-pxa/ssp.c
@@ -190,8 +190,6 @@ static int pxa_ssp_remove(struct platform_device *pdev)
         if (ssp == NULL)
                 return -ENODEV;
 
-        iounmap(ssp->mmio_base);
-
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         release_mem_region(res->start, resource_size(res));
 
@@ -201,7 +199,6 @@ static int pxa_ssp_remove(struct platform_device *pdev)
         list_del(&ssp->node);
         mutex_unlock(&ssp_lock);
 
-        kfree(ssp);
         return 0;
 }
 
diff --git a/arch/arm/probes/kprobes/opt-arm.c b/arch/arm/probes/kprobes/opt-arm.c
index 2c118a6ab358..0dc23fc227ed 100644
--- a/arch/arm/probes/kprobes/opt-arm.c
+++ b/arch/arm/probes/kprobes/opt-arm.c
@@ -247,7 +247,7 @@ int arch_prepare_optimized_kprobe(struct optimized_kprobe *op, struct kprobe *or
         }
 
         /* Copy arch-dep-instance from template. */
-        memcpy(code, (unsigned char *)optprobe_template_entry,
+        memcpy(code, (unsigned long *)&optprobe_template_entry,
                         TMPL_END_IDX * sizeof(kprobe_opcode_t));
 
         /* Adjust buffer according to instruction. */
diff --git a/arch/arm/tools/syscall.tbl b/arch/arm/tools/syscall.tbl
index 8edf93b4490f..9016f4081bb9 100644
--- a/arch/arm/tools/syscall.tbl
+++ b/arch/arm/tools/syscall.tbl
@@ -24,7 +24,7 @@
 10      common  unlink                  sys_unlink
 11      common  execve                  sys_execve
 12      common  chdir                   sys_chdir
-13      oabi    time                    sys_time
+13      oabi    time                    sys_time32
 14      common  mknod                   sys_mknod
 15      common  chmod                   sys_chmod
 16      common  lchown                  sys_lchown16
@@ -36,12 +36,12 @@
 22      oabi    umount                  sys_oldumount
 23      common  setuid                  sys_setuid16
 24      common  getuid                  sys_getuid16
-25      oabi    stime                   sys_stime
+25      oabi    stime                   sys_stime32
 26      common  ptrace                  sys_ptrace
 27      oabi    alarm                   sys_alarm
 # 28 was sys_fstat
 29      common  pause                   sys_pause
-30      oabi    utime                   sys_utime
+30      oabi    utime                   sys_utime32
 # 31 was sys_stty
 # 32 was sys_gtty
 33      common  access                  sys_access
@@ -137,7 +137,7 @@
 121     common  setdomainname           sys_setdomainname
 122     common  uname                   sys_newuname
 # 123 was sys_modify_ldt
-124     common  adjtimex                sys_adjtimex
+124     common  adjtimex                sys_adjtimex_time32
 125     common  mprotect                sys_mprotect
 126     common  sigprocmask             sys_sigprocmask
 # 127 was sys_create_module
@@ -174,8 +174,8 @@
 158     common  sched_yield             sys_sched_yield
 159     common  sched_get_priority_max  sys_sched_get_priority_max
 160     common  sched_get_priority_min  sys_sched_get_priority_min
-161     common  sched_rr_get_interval   sys_sched_rr_get_interval
-162     common  nanosleep               sys_nanosleep
+161     common  sched_rr_get_interval   sys_sched_rr_get_interval_time32
+162     common  nanosleep               sys_nanosleep_time32
 163     common  mremap                  sys_mremap
 164     common  setresuid               sys_setresuid16
 165     common  getresuid               sys_getresuid16
@@ -190,7 +190,7 @@
 174     common  rt_sigaction            sys_rt_sigaction
 175     common  rt_sigprocmask          sys_rt_sigprocmask
 176     common  rt_sigpending           sys_rt_sigpending
-177     common  rt_sigtimedwait         sys_rt_sigtimedwait
+177     common  rt_sigtimedwait         sys_rt_sigtimedwait_time32
 178     common  rt_sigqueueinfo         sys_rt_sigqueueinfo
 179     common  rt_sigsuspend           sys_rt_sigsuspend
 180     common  pread64                 sys_pread64             sys_oabi_pread64
@@ -254,12 +254,12 @@
 237     common  fremovexattr            sys_fremovexattr
 238     common  tkill                   sys_tkill
 239     common  sendfile64              sys_sendfile64
-240     common  futex                   sys_futex
+240     common  futex                   sys_futex_time32
 241     common  sched_setaffinity       sys_sched_setaffinity
 242     common  sched_getaffinity       sys_sched_getaffinity
 243     common  io_setup                sys_io_setup
 244     common  io_destroy              sys_io_destroy
-245     common  io_getevents            sys_io_getevents
+245     common  io_getevents            sys_io_getevents_time32
 246     common  io_submit               sys_io_submit
 247     common  io_cancel               sys_io_cancel
 248     common  exit_group              sys_exit_group
@@ -272,26 +272,26 @@
 # 255 for get_thread_area
 256     common  set_tid_address         sys_set_tid_address
 257     common  timer_create            sys_timer_create
-258     common  timer_settime           sys_timer_settime
-259     common  timer_gettime           sys_timer_gettime
+258     common  timer_settime           sys_timer_settime32
+259     common  timer_gettime           sys_timer_gettime32
 260     common  timer_getoverrun        sys_timer_getoverrun
 261     common  timer_delete            sys_timer_delete
-262     common  clock_settime           sys_clock_settime
-263     common  clock_gettime           sys_clock_gettime
-264     common  clock_getres            sys_clock_getres
-265     common  clock_nanosleep         sys_clock_nanosleep
+262     common  clock_settime           sys_clock_settime32
+263     common  clock_gettime           sys_clock_gettime32
+264     common  clock_getres            sys_clock_getres_time32
+265     common  clock_nanosleep         sys_clock_nanosleep_time32
 266     common  statfs64                sys_statfs64_wrapper
 267     common  fstatfs64               sys_fstatfs64_wrapper
 268     common  tgkill                  sys_tgkill
-269     common  utimes                  sys_utimes
+269     common  utimes                  sys_utimes_time32
 270     common  arm_fadvise64_64        sys_arm_fadvise64_64
 271     common  pciconfig_iobase        sys_pciconfig_iobase
 272     common  pciconfig_read          sys_pciconfig_read
 273     common  pciconfig_write         sys_pciconfig_write
 274     common  mq_open                 sys_mq_open
 275     common  mq_unlink               sys_mq_unlink
-276     common  mq_timedsend            sys_mq_timedsend
-277     common  mq_timedreceive         sys_mq_timedreceive
+276     common  mq_timedsend            sys_mq_timedsend_time32
+277     common  mq_timedreceive         sys_mq_timedreceive_time32
 278     common  mq_notify               sys_mq_notify
 279     common  mq_getsetattr           sys_mq_getsetattr
 280     common  waitid                  sys_waitid
@@ -314,19 +314,19 @@
 297     common  recvmsg                 sys_recvmsg
 298     common  semop                   sys_semop               sys_oabi_semop
 299     common  semget                  sys_semget
-300     common  semctl                  sys_semctl
+300     common  semctl                  sys_old_semctl
 301     common  msgsnd                  sys_msgsnd
 302     common  msgrcv                  sys_msgrcv
 303     common  msgget                  sys_msgget
-304     common  msgctl                  sys_msgctl
+304     common  msgctl                  sys_old_msgctl
 305     common  shmat                   sys_shmat
 306     common  shmdt                   sys_shmdt
 307     common  shmget                  sys_shmget
-308     common  shmctl                  sys_shmctl
+308     common  shmctl                  sys_old_shmctl
 309     common  add_key                 sys_add_key
 310     common  request_key             sys_request_key
 311     common  keyctl                  sys_keyctl
-312     common  semtimedop              sys_semtimedop          sys_oabi_semtimedop
+312     common  semtimedop              sys_semtimedop_time32   sys_oabi_semtimedop
 313     common  vserver
 314     common  ioprio_set              sys_ioprio_set
 315     common  ioprio_get              sys_ioprio_get
@@ -340,7 +340,7 @@
 323     common  mkdirat                 sys_mkdirat
 324     common  mknodat                 sys_mknodat
 325     common  fchownat                sys_fchownat
-326     common  futimesat               sys_futimesat
+326     common  futimesat               sys_futimesat_time32
 327     common  fstatat64               sys_fstatat64           sys_oabi_fstatat64
 328     common  unlinkat                sys_unlinkat
 329     common  renameat                sys_renameat
@@ -349,8 +349,8 @@
 332     common  readlinkat              sys_readlinkat
 333     common  fchmodat                sys_fchmodat
 334     common  faccessat               sys_faccessat
-335     common  pselect6                sys_pselect6
-336     common  ppoll                   sys_ppoll
+335     common  pselect6                sys_pselect6_time32
+336     common  ppoll                   sys_ppoll_time32
 337     common  unshare                 sys_unshare
 338     common  set_robust_list         sys_set_robust_list
 339     common  get_robust_list         sys_get_robust_list
@@ -362,13 +362,13 @@
 345     common  getcpu                  sys_getcpu
 346     common  epoll_pwait             sys_epoll_pwait
 347     common  kexec_load              sys_kexec_load
-348     common  utimensat               sys_utimensat
+348     common  utimensat               sys_utimensat_time32
 349     common  signalfd                sys_signalfd
 350     common  timerfd_create          sys_timerfd_create
 351     common  eventfd                 sys_eventfd
 352     common  fallocate               sys_fallocate
-353     common  timerfd_settime         sys_timerfd_settime
-354     common  timerfd_gettime         sys_timerfd_gettime
+353     common  timerfd_settime         sys_timerfd_settime32
+354     common  timerfd_gettime         sys_timerfd_gettime32
 355     common  signalfd4               sys_signalfd4
 356     common  eventfd2                sys_eventfd2
 357     common  epoll_create1           sys_epoll_create1
@@ -379,14 +379,14 @@
 362     common  pwritev                 sys_pwritev
 363     common  rt_tgsigqueueinfo       sys_rt_tgsigqueueinfo
 364     common  perf_event_open         sys_perf_event_open
-365     common  recvmmsg                sys_recvmmsg
+365     common  recvmmsg                sys_recvmmsg_time32
 366     common  accept4                 sys_accept4
 367     common  fanotify_init           sys_fanotify_init
 368     common  fanotify_mark           sys_fanotify_mark
 369     common  prlimit64               sys_prlimit64
 370     common  name_to_handle_at       sys_name_to_handle_at
 371     common  open_by_handle_at       sys_open_by_handle_at
-372     common  clock_adjtime           sys_clock_adjtime
+372     common  clock_adjtime           sys_clock_adjtime32
 373     common  syncfs                  sys_syncfs
 374     common  sendmmsg                sys_sendmmsg
 375     common  setns                   sys_setns
@@ -413,4 +413,27 @@
 396     common  pkey_free               sys_pkey_free
 397     common  statx                   sys_statx
 398     common  rseq                    sys_rseq
-399     common  io_pgetevents           sys_io_pgetevents
+399     common  io_pgetevents           sys_io_pgetevents_time32
+400     common  migrate_pages           sys_migrate_pages
+401     common  kexec_file_load         sys_kexec_file_load
+# 402 is unused
+403     common  clock_gettime64                 sys_clock_gettime
+404     common  clock_settime64                 sys_clock_settime
+405     common  clock_adjtime64                 sys_clock_adjtime
+406     common  clock_getres_time64             sys_clock_getres
+407     common  clock_nanosleep_time64          sys_clock_nanosleep
+408     common  timer_gettime64                 sys_timer_gettime
+409     common  timer_settime64                 sys_timer_settime
+410     common  timerfd_gettime64               sys_timerfd_gettime
+411     common  timerfd_settime64               sys_timerfd_settime
+412     common  utimensat_time64                sys_utimensat
+413     common  pselect6_time64                 sys_pselect6
+414     common  ppoll_time64                    sys_ppoll
+416     common  io_pgetevents_time64            sys_io_pgetevents
+417     common  recvmmsg_time64                 sys_recvmmsg
+418     common  mq_timedsend_time64             sys_mq_timedsend
+419     common  mq_timedreceive_time64          sys_mq_timedreceive
+420     common  semtimedop_time64               sys_semtimedop
+421     common  rt_sigtimedwait_time64          sys_rt_sigtimedwait
+422     common  futex_time64                    sys_futex
+423     common  sched_rr_get_interval_time64    sys_sched_rr_get_interval
diff --git a/arch/arm/xen/hypercall.S b/arch/arm/xen/hypercall.S
index b0b80c0f09f3..b11bba542fac 100644
--- a/arch/arm/xen/hypercall.S
+++ b/arch/arm/xen/hypercall.S
@@ -113,8 +113,7 @@ ENTRY(privcmd_call)
 
         /*
          * Disable userspace access from kernel. This is fine to do it
-         * unconditionally as no set_fs(KERNEL_DS)/set_fs(get_ds()) is
-         * called before.
+         * unconditionally as no set_fs(KERNEL_DS) is called before.
          */
         uaccess_disable r4
 
diff --git a/arch/arm/xen/mm.c b/arch/arm/xen/mm.c
index cb44aa290e73..e1d44b903dfc 100644
--- a/arch/arm/xen/mm.c
+++ b/arch/arm/xen/mm.c
@@ -7,7 +7,6 @@
 #include <linux/of_address.h>
 #include <linux/slab.h>
 #include <linux/types.h>
-#include <linux/dma-mapping.h>
 #include <linux/vmalloc.h>
 #include <linux/swiotlb.h>