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-rw-r--r--arch/arm64/Makefile2
-rw-r--r--arch/arm64/boot/dts/Makefile1
-rw-r--r--arch/arm64/boot/dts/al/Makefile5
-rw-r--r--arch/arm64/boot/dts/al/alpine-v2-evp.dts53
-rw-r--r--arch/arm64/boot/dts/al/alpine-v2.dtsi236
-rw-r--r--arch/arm64/boot/dts/amd/Makefile4
-rw-r--r--arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts87
-rw-r--r--arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts91
-rw-r--r--arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi104
-rw-r--r--arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi117
-rw-r--r--arch/arm64/boot/dts/amd/husky.dts83
-rw-r--r--arch/arm64/boot/dts/apm/apm-merlin.dts3
-rw-r--r--arch/arm64/boot/dts/apm/apm-mustang.dts3
-rw-r--r--arch/arm64/boot/dts/apm/apm-shadowcat.dtsi27
-rw-r--r--arch/arm64/boot/dts/apm/apm-storm.dtsi22
-rw-r--r--arch/arm64/boot/dts/arm/juno-base.dtsi1
-rw-r--r--arch/arm64/boot/dts/broadcom/ns2-svk.dts12
-rw-r--r--arch/arm64/boot/dts/broadcom/ns2.dtsi140
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi3
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi2
-rw-r--r--arch/arm64/boot/dts/hisilicon/hip05-d02.dts18
-rw-r--r--arch/arm64/boot/dts/hisilicon/hip05.dtsi92
-rw-r--r--arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi19
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8173-evb.dts3
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8173.dtsi16
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra132-norrin.dts2
-rw-r--r--arch/arm64/boot/dts/qcom/Makefile1
-rw-r--r--arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi2
-rw-r--r--arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi14
-rw-r--r--arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi170
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-pins.dtsi238
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916.dtsi48
-rw-r--r--arch/arm64/boot/dts/qcom/msm8996-mtp.dts21
-rw-r--r--arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi30
-rw-r--r--arch/arm64/boot/dts/qcom/msm8996.dtsi269
-rw-r--r--arch/arm64/boot/dts/qcom/pm8004.dtsi19
-rw-r--r--arch/arm64/boot/dts/qcom/pm8916.dtsi10
-rw-r--r--arch/arm64/boot/dts/qcom/pm8994.dtsi62
-rw-r--r--arch/arm64/boot/dts/qcom/pmi8994.dtsi19
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts139
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795.dtsi531
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi2
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3368-r88.dts2
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3368.dtsi10
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi88
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts1
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp.dtsi61
-rw-r--r--arch/arm64/configs/defconfig42
-rw-r--r--arch/arm64/include/asm/futex.h2
-rw-r--r--arch/arm64/include/asm/page.h1
-rw-r--r--arch/arm64/include/asm/pgtable.h21
-rw-r--r--arch/arm64/kernel/head.S5
-rw-r--r--arch/arm64/kernel/image.h40
-rw-r--r--arch/arm64/mm/dump.c2
-rw-r--r--arch/arm64/mm/kasan_init.c9
-rw-r--r--arch/arm64/mm/pageattr.c24
-rw-r--r--arch/arm64/mm/proc-macros.S12
-rw-r--r--arch/arm64/mm/proc.S4
58 files changed, 2793 insertions, 252 deletions
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index cd822d8454c0..307237cfe728 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -27,6 +27,8 @@ $(warning LSE atomics not supported by binutils)
27endif 27endif
28 28
29KBUILD_CFLAGS += -mgeneral-regs-only $(lseinstr) 29KBUILD_CFLAGS += -mgeneral-regs-only $(lseinstr)
30KBUILD_CFLAGS += -fno-asynchronous-unwind-tables
31KBUILD_CFLAGS += $(call cc-option, -mpc-relative-literal-loads)
30KBUILD_AFLAGS += $(lseinstr) 32KBUILD_AFLAGS += $(lseinstr)
31 33
32ifeq ($(CONFIG_CPU_BIG_ENDIAN), y) 34ifeq ($(CONFIG_CPU_BIG_ENDIAN), y)
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index f832b8a7453a..fd80617a9c6f 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,4 @@
1dts-dirs += al
1dts-dirs += altera 2dts-dirs += altera
2dts-dirs += amd 3dts-dirs += amd
3dts-dirs += apm 4dts-dirs += apm
diff --git a/arch/arm64/boot/dts/al/Makefile b/arch/arm64/boot/dts/al/Makefile
new file mode 100644
index 000000000000..8a6cde4f9b23
--- /dev/null
+++ b/arch/arm64/boot/dts/al/Makefile
@@ -0,0 +1,5 @@
1dtb-$(CONFIG_ARCH_ALPINE) += alpine-v2-evp.dtb
2
3always := $(dtb-y)
4subdir-y := $(dts-dirs)
5clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/al/alpine-v2-evp.dts b/arch/arm64/boot/dts/al/alpine-v2-evp.dts
new file mode 100644
index 000000000000..a079d7b3063e
--- /dev/null
+++ b/arch/arm64/boot/dts/al/alpine-v2-evp.dts
@@ -0,0 +1,53 @@
1/*
2 * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
3 *
4 * Antoine Tenart <antoine.tenart@free-electrons.com>
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include "alpine-v2.dtsi"
36
37/ {
38 model = "Annapurna Labs Alpine v2 EVP";
39 compatible = "al,alpine-v2-evp", "al,alpine-v2";
40
41 aliases {
42 serial0 = &uart0;
43 serial1 = &uart1;
44 serial2 = &uart2;
45 serial3 = &uart3;
46 };
47
48 chosen {
49 stdout-path = "serial0:115200n8";
50 };
51};
52
53&uart0 { status = "okay"; };
diff --git a/arch/arm64/boot/dts/al/alpine-v2.dtsi b/arch/arm64/boot/dts/al/alpine-v2.dtsi
new file mode 100644
index 000000000000..5b7bef684256
--- /dev/null
+++ b/arch/arm64/boot/dts/al/alpine-v2.dtsi
@@ -0,0 +1,236 @@
1/*
2 * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
3 *
4 * Antoine Tenart <antoine.tenart@free-electrons.com>
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35/dts-v1/;
36
37#include <dt-bindings/interrupt-controller/arm-gic.h>
38
39/ {
40 model = "Annapurna Labs Alpine v2";
41 compatible = "al,alpine-v2";
42 #address-cells = <2>;
43 #size-cells = <2>;
44
45 cpus {
46 #address-cells = <2>;
47 #size-cells = <0>;
48
49 cpu@0 {
50 compatible = "arm,cortex-a57", "arm,armv8";
51 device_type = "cpu";
52 reg = <0x0 0x0>;
53 enable-method = "psci";
54 };
55
56 cpu@1 {
57 compatible = "arm,cortex-a57", "arm,armv8";
58 device_type = "cpu";
59 reg = <0x0 0x1>;
60 enable-method = "psci";
61 };
62
63 cpu@2 {
64 compatible = "arm,cortex-a57", "arm,armv8";
65 device_type = "cpu";
66 reg = <0x0 0x2>;
67 enable-method = "psci";
68 };
69
70 cpu@3 {
71 compatible = "arm,cortex-a57", "arm,armv8";
72 device_type = "cpu";
73 reg = <0x0 0x3>;
74 enable-method = "psci";
75 };
76 };
77
78 psci {
79 compatible = "arm,psci-0.2", "arm,psci";
80 method = "smc";
81 cpu_suspend = <0x84000001>;
82 cpu_off = <0x84000002>;
83 cpu_on = <0x84000003>;
84 };
85
86 sbclk: sbclk {
87 compatible = "fixed-clock";
88 #clock-cells = <0>;
89 clock-frequency = <1000000>;
90 };
91
92 soc {
93 compatible = "simple-bus";
94 #address-cells = <2>;
95 #size-cells = <2>;
96
97 interrupt-parent = <&gic>;
98 ranges;
99
100 timer {
101 compatible = "arm,armv8-timer";
102 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
103 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
104 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
105 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
106 };
107
108 pmu {
109 compatible = "arm,armv8-pmuv3";
110 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
112 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
113 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
114 };
115
116 gic: gic@f0100000 {
117 compatible = "arm,gic-v3";
118 reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */
119 <0x0 0xf0280000 0x0 0x200000>, /* GICR */
120 <0x0 0xf0100000 0x0 0x2000>, /* GICC */
121 <0x0 0xf0110000 0x0 0x2000>, /* GICV */
122 <0x0 0xf0120000 0x0 0x2000>; /* GICH */
123 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
124 interrupt-controller;
125 #interrupt-cells = <3>;
126 };
127
128 pci@fbc00000 {
129 compatible = "pci-host-ecam-generic";
130 device_type = "pci";
131 #size-cells = <2>;
132 #address-cells = <3>;
133 #interrupt-cells = <1>;
134 reg = <0x0 0xfbc00000 0x0 0x100000>;
135 interrupt-map-mask = <0xf800 0 0 7>;
136 /* add legacy interrupts for SATA only */
137 interrupt-map = <0x4000 0 0 1 &gic 0 53 4>,
138 <0x4800 0 0 1 &gic 0 54 4>;
139 /* 32 bit non prefetchable memory space */
140 ranges = <0x2000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
141 bus-range = <0x00 0x00>;
142 msi-parent = <&msix>;
143 };
144
145 msix: msix@fbe00000 {
146 compatible = "al,alpine-msix";
147 reg = <0x0 0xfbe00000 0x0 0x100000>;
148 interrupt-controller;
149 msi-controller;
150 al,msi-base-spi = <160>;
151 al,msi-num-spis = <160>;
152 };
153
154 io-fabric {
155 compatible = "simple-bus";
156 #address-cells = <1>;
157 #size-cells = <1>;
158 ranges = <0x0 0x0 0xfc000000 0x2000000>;
159
160 uart0: serial@1883000 {
161 compatible = "ns16550a";
162 device_type = "serial";
163 reg = <0x1883000 0x1000>;
164 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
165 clock-frequency = <500000000>;
166 reg-shift = <2>;
167 reg-io-width = <4>;
168 status = "disabled";
169 };
170
171 uart1: serial@1884000 {
172 compatible = "ns16550a";
173 device_type = "serial";
174 reg = <0x1884000 0x1000>;
175 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
176 clock-frequency = <500000000>;
177 reg-shift = <2>;
178 reg-io-width = <4>;
179 status = "disabled";
180 };
181
182 uart2: serial@1885000 {
183 compatible = "ns16550a";
184 device_type = "serial";
185 reg = <0x1885000 0x1000>;
186 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
187 clock-frequency = <500000000>;
188 reg-shift = <2>;
189 reg-io-width = <4>;
190 status = "disabled";
191 };
192
193 uart3: serial@1886000 {
194 compatible = "ns16550a";
195 device_type = "serial";
196 reg = <0x1886000 0x1000>;
197 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
198 clock-frequency = <500000000>;
199 reg-shift = <2>;
200 reg-io-width = <4>;
201 status = "disabled";
202 };
203
204 timer0: timer@1890000 {
205 compatible = "arm,sp804", "arm,primecell";
206 reg = <0x1890000 0x1000>;
207 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&sbclk>;
209 };
210
211 timer1: timer@1891000 {
212 compatible = "arm,sp804", "arm,primecell";
213 reg = <0x1891000 0x1000>;
214 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&sbclk>;
216 status = "disabled";
217 };
218
219 timer2: timer@1892000 {
220 compatible = "arm,sp804", "arm,primecell";
221 reg = <0x1892000 0x1000>;
222 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&sbclk>;
224 status = "disabled";
225 };
226
227 timer3: timer@1893000 {
228 compatible = "arm,sp804", "arm,primecell";
229 reg = <0x1893000 0x1000>;
230 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&sbclk>;
232 status = "disabled";
233 };
234 };
235 };
236};
diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile
index cfdf701e05df..ba84770f789f 100644
--- a/arch/arm64/boot/dts/amd/Makefile
+++ b/arch/arm64/boot/dts/amd/Makefile
@@ -1,4 +1,6 @@
1dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive.dtb 1dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive.dtb \
2 amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb \
3 husky.dtb
2 4
3always := $(dtb-y) 5always := $(dtb-y)
4subdir-y := $(dts-dirs) 6subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts
new file mode 100644
index 000000000000..8e3074a4947d
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts
@@ -0,0 +1,87 @@
1/*
2 * DTS file for AMD Seattle Overdrive Development Board
3 * Note: For Seattle Rev.B0
4 *
5 * Copyright (C) 2015 Advanced Micro Devices, Inc.
6 */
7
8/dts-v1/;
9
10/include/ "amd-seattle-soc.dtsi"
11
12/ {
13 model = "AMD Seattle (Rev.B0) Development Board (Overdrive)";
14 compatible = "amd,seattle-overdrive", "amd,seattle";
15
16 chosen {
17 stdout-path = &serial0;
18 };
19
20 psci {
21 compatible = "arm,psci-0.2";
22 method = "smc";
23 };
24};
25
26&ccp0 {
27 status = "ok";
28 amd,zlib-support = <1>;
29};
30
31/**
32 * NOTE: In Rev.B, gpio0 is reserved.
33 */
34&gpio1 {
35 status = "ok";
36};
37
38&gpio2 {
39 status = "ok";
40};
41
42&gpio3 {
43 status = "ok";
44};
45
46&gpio4 {
47 status = "ok";
48};
49
50&i2c0 {
51 status = "ok";
52};
53
54&i2c1 {
55 status = "ok";
56};
57
58&pcie0 {
59 status = "ok";
60};
61
62&spi0 {
63 status = "ok";
64};
65
66&spi1 {
67 status = "ok";
68 sdcard0: sdcard@0 {
69 compatible = "mmc-spi-slot";
70 reg = <0>;
71 spi-max-frequency = <20000000>;
72 voltage-ranges = <3200 3400>;
73 pl022,hierarchy = <0>;
74 pl022,interface = <0>;
75 pl022,com-mode = <0x0>;
76 pl022,rx-level-trig = <0>;
77 pl022,tx-level-trig = <0>;
78 };
79};
80
81&ipmi_kcs {
82 status = "ok";
83};
84
85&smb0 {
86 /include/ "amd-seattle-xgbe-b.dtsi"
87};
diff --git a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts
new file mode 100644
index 000000000000..ed5e043f37aa
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts
@@ -0,0 +1,91 @@
1/*
2 * DTS file for AMD Seattle Overdrive Development Board
3 * Note: For Seattle Rev.B1
4 *
5 * Copyright (C) 2015 Advanced Micro Devices, Inc.
6 */
7
8/dts-v1/;
9
10/include/ "amd-seattle-soc.dtsi"
11
12/ {
13 model = "AMD Seattle (Rev.B1) Development Board (Overdrive)";
14 compatible = "amd,seattle-overdrive", "amd,seattle";
15
16 chosen {
17 stdout-path = &serial0;
18 };
19
20 psci {
21 compatible = "arm,psci-0.2";
22 method = "smc";
23 };
24};
25
26&ccp0 {
27 status = "ok";
28 amd,zlib-support = <1>;
29};
30
31/**
32 * NOTE: In Rev.B, gpio0 is reserved.
33 */
34&gpio1 {
35 status = "ok";
36};
37
38&gpio2 {
39 status = "ok";
40};
41
42&gpio3 {
43 status = "ok";
44};
45
46&gpio4 {
47 status = "ok";
48};
49
50&i2c0 {
51 status = "ok";
52};
53
54&i2c1 {
55 status = "ok";
56};
57
58&pcie0 {
59 status = "ok";
60};
61
62&sata1 {
63 status = "ok";
64};
65
66&spi0 {
67 status = "ok";
68};
69
70&spi1 {
71 status = "ok";
72 sdcard0: sdcard@0 {
73 compatible = "mmc-spi-slot";
74 reg = <0>;
75 spi-max-frequency = <20000000>;
76 voltage-ranges = <3200 3400>;
77 pl022,hierarchy = <0>;
78 pl022,interface = <0>;
79 pl022,com-mode = <0x0>;
80 pl022,rx-level-trig = <0>;
81 pl022,tx-level-trig = <0>;
82 };
83};
84
85&ipmi_kcs {
86 status = "ok";
87};
88
89&smb0 {
90 /include/ "amd-seattle-xgbe-b.dtsi"
91};
diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
index 2874d92881fd..bd3adeac374f 100644
--- a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
+++ b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
@@ -18,8 +18,8 @@
18 #size-cells = <2>; 18 #size-cells = <2>;
19 reg = <0x0 0xe1110000 0 0x1000>, 19 reg = <0x0 0xe1110000 0 0x1000>,
20 <0x0 0xe112f000 0 0x2000>, 20 <0x0 0xe112f000 0 0x2000>,
21 <0x0 0xe1140000 0 0x10000>, 21 <0x0 0xe1140000 0 0x2000>,
22 <0x0 0xe1160000 0 0x10000>; 22 <0x0 0xe1160000 0 0x2000>;
23 interrupts = <1 9 0xf04>; 23 interrupts = <1 9 0xf04>;
24 ranges = <0 0 0 0xe1100000 0 0x100000>; 24 ranges = <0 0 0 0xe1100000 0 0x100000>;
25 v2m0: v2m@e0080000 { 25 v2m0: v2m@e0080000 {
@@ -55,25 +55,47 @@
55 #size-cells = <2>; 55 #size-cells = <2>;
56 ranges; 56 ranges;
57 57
58 /* DDR range is 40-bit addressing */ 58 /*
59 dma-ranges = <0x80 0x0 0x80 0x0 0x7f 0xffffffff>; 59 * dma-ranges is 40-bit address space containing:
60 * - GICv2m MSI register is at 0xe0080000
61 * - DRAM range [0x8000000000 to 0xffffffffff]
62 */
63 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
60 64
61 /include/ "amd-seattle-clks.dtsi" 65 /include/ "amd-seattle-clks.dtsi"
62 66
63 sata0: sata@e0300000 { 67 sata0: sata@e0300000 {
64 compatible = "snps,dwc-ahci"; 68 compatible = "snps,dwc-ahci";
65 reg = <0 0xe0300000 0 0x800>; 69 reg = <0 0xe0300000 0 0xf0000>;
66 interrupts = <0 355 4>; 70 interrupts = <0 355 4>;
67 clocks = <&sataclk_333mhz>; 71 clocks = <&sataclk_333mhz>;
68 dma-coherent; 72 dma-coherent;
69 }; 73 };
70 74
75 /* This is for Rev B only */
76 sata1: sata@e0d00000 {
77 status = "disabled";
78 compatible = "snps,dwc-ahci";
79 reg = <0 0xe0d00000 0 0xf0000>;
80 interrupts = <0 354 4>;
81 clocks = <&sataclk_333mhz>;
82 dma-coherent;
83 };
84
71 i2c0: i2c@e1000000 { 85 i2c0: i2c@e1000000 {
72 status = "disabled"; 86 status = "disabled";
73 compatible = "snps,designware-i2c"; 87 compatible = "snps,designware-i2c";
74 reg = <0 0xe1000000 0 0x1000>; 88 reg = <0 0xe1000000 0 0x1000>;
75 interrupts = <0 357 4>; 89 interrupts = <0 357 4>;
76 clocks = <&uartspiclk_100mhz>; 90 clocks = <&miscclk_250mhz>;
91 };
92
93 i2c1: i2c@e0050000 {
94 status = "disabled";
95 compatible = "snps,designware-i2c";
96 reg = <0 0xe0050000 0 0x1000>;
97 interrupts = <0 340 4>;
98 clocks = <&miscclk_250mhz>;
77 }; 99 };
78 100
79 serial0: serial@e1010000 { 101 serial0: serial@e1010000 {
@@ -87,7 +109,6 @@
87 spi0: ssp@e1020000 { 109 spi0: ssp@e1020000 {
88 status = "disabled"; 110 status = "disabled";
89 compatible = "arm,pl022", "arm,primecell"; 111 compatible = "arm,pl022", "arm,primecell";
90 #gpio-cells = <2>;
91 reg = <0 0xe1020000 0 0x1000>; 112 reg = <0 0xe1020000 0 0x1000>;
92 spi-controller; 113 spi-controller;
93 interrupts = <0 330 4>; 114 interrupts = <0 330 4>;
@@ -98,7 +119,6 @@
98 spi1: ssp@e1030000 { 119 spi1: ssp@e1030000 {
99 status = "disabled"; 120 status = "disabled";
100 compatible = "arm,pl022", "arm,primecell"; 121 compatible = "arm,pl022", "arm,primecell";
101 #gpio-cells = <2>;
102 reg = <0 0xe1030000 0 0x1000>; 122 reg = <0 0xe1030000 0 0x1000>;
103 spi-controller; 123 spi-controller;
104 interrupts = <0 329 4>; 124 interrupts = <0 329 4>;
@@ -109,7 +129,7 @@
109 #size-cells = <0>; 129 #size-cells = <0>;
110 }; 130 };
111 131
112 gpio0: gpio@e1040000 { 132 gpio0: gpio@e1040000 { /* Not available to OS for B0 */
113 status = "disabled"; 133 status = "disabled";
114 compatible = "arm,pl061", "arm,primecell"; 134 compatible = "arm,pl061", "arm,primecell";
115 #gpio-cells = <2>; 135 #gpio-cells = <2>;
@@ -118,18 +138,59 @@
118 interrupts = <0 359 4>; 138 interrupts = <0 359 4>;
119 interrupt-controller; 139 interrupt-controller;
120 #interrupt-cells = <2>; 140 #interrupt-cells = <2>;
121 clocks = <&uartspiclk_100mhz>; 141 clocks = <&miscclk_250mhz>;
122 clock-names = "apb_pclk"; 142 clock-names = "apb_pclk";
123 }; 143 };
124 144
125 gpio1: gpio@e1050000 { 145 gpio1: gpio@e1050000 { /* [0:7] */
126 status = "disabled"; 146 status = "disabled";
127 compatible = "arm,pl061", "arm,primecell"; 147 compatible = "arm,pl061", "arm,primecell";
128 #gpio-cells = <2>; 148 #gpio-cells = <2>;
129 reg = <0 0xe1050000 0 0x1000>; 149 reg = <0 0xe1050000 0 0x1000>;
130 gpio-controller; 150 gpio-controller;
151 interrupt-controller;
152 #interrupt-cells = <2>;
131 interrupts = <0 358 4>; 153 interrupts = <0 358 4>;
132 clocks = <&uartspiclk_100mhz>; 154 clocks = <&miscclk_250mhz>;
155 clock-names = "apb_pclk";
156 };
157
158 gpio2: gpio@e0020000 { /* [8:15] */
159 status = "disabled";
160 compatible = "arm,pl061", "arm,primecell";
161 #gpio-cells = <2>;
162 reg = <0 0xe0020000 0 0x1000>;
163 gpio-controller;
164 interrupt-controller;
165 #interrupt-cells = <2>;
166 interrupts = <0 366 4>;
167 clocks = <&miscclk_250mhz>;
168 clock-names = "apb_pclk";
169 };
170
171 gpio3: gpio@e0030000 { /* [16:23] */
172 status = "disabled";
173 compatible = "arm,pl061", "arm,primecell";
174 #gpio-cells = <2>;
175 reg = <0 0xe0030000 0 0x1000>;
176 gpio-controller;
177 interrupt-controller;
178 #interrupt-cells = <2>;
179 interrupts = <0 365 4>;
180 clocks = <&miscclk_250mhz>;
181 clock-names = "apb_pclk";
182 };
183
184 gpio4: gpio@e0080000 { /* [24] */
185 status = "disabled";
186 compatible = "arm,pl061", "arm,primecell";
187 #gpio-cells = <2>;
188 reg = <0 0xe0080000 0 0x1000>;
189 gpio-controller;
190 interrupt-controller;
191 #interrupt-cells = <2>;
192 interrupts = <0 361 4>;
193 clocks = <&miscclk_250mhz>;
133 clock-names = "apb_pclk"; 194 clock-names = "apb_pclk";
134 }; 195 };
135 196
@@ -159,7 +220,7 @@
159 <0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>; 220 <0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>;
160 221
161 dma-coherent; 222 dma-coherent;
162 dma-ranges = <0x43000000 0x80 0x0 0x80 0x0 0x7f 0xffffffff>; 223 dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
163 ranges = 224 ranges =
164 /* I/O Memory (size=64K) */ 225 /* I/O Memory (size=64K) */
165 <0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>, 226 <0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>,
@@ -168,5 +229,22 @@
168 /* 64-bit MMIO (size= 124G) */ 229 /* 64-bit MMIO (size= 124G) */
169 <0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>; 230 <0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
170 }; 231 };
232
233 /* Perf CCN504 PMU */
234 ccn: ccn@e8000000 {
235 compatible = "arm,ccn-504";
236 reg = <0x0 0xe8000000 0 0x1000000>;
237 interrupts = <0 380 4>;
238 };
239
240 ipmi_kcs: kcs@e0010000 {
241 status = "disabled";
242 compatible = "ipmi-kcs";
243 device_type = "ipmi";
244 reg = <0x0 0xe0010000 0 0x8>;
245 interrupts = <0 389 4>;
246 reg-size = <1>;
247 reg-spacing = <4>;
248 };
171 }; 249 };
172}; 250};
diff --git a/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi
new file mode 100644
index 000000000000..8e8631952497
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi
@@ -0,0 +1,117 @@
1/*
2 * DTS file for AMD Seattle XGBE (RevB)
3 *
4 * Copyright (C) 2015 Advanced Micro Devices, Inc.
5 */
6
7 xgmacclk0_dma_250mhz: clk250mhz_0 {
8 compatible = "fixed-clock";
9 #clock-cells = <0>;
10 clock-frequency = <250000000>;
11 clock-output-names = "xgmacclk0_dma_250mhz";
12 };
13
14 xgmacclk0_ptp_250mhz: clk250mhz_1 {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <250000000>;
18 clock-output-names = "xgmacclk0_ptp_250mhz";
19 };
20
21 xgmacclk1_dma_250mhz: clk250mhz_2 {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <250000000>;
25 clock-output-names = "xgmacclk1_dma_250mhz";
26 };
27
28 xgmacclk1_ptp_250mhz: clk250mhz_3 {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <250000000>;
32 clock-output-names = "xgmacclk1_ptp_250mhz";
33 };
34
35 xgmac0: xgmac@e0700000 {
36 compatible = "amd,xgbe-seattle-v1a";
37 reg = <0 0xe0700000 0 0x80000>,
38 <0 0xe0780000 0 0x80000>,
39 <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
40 <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
41 <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
42 interrupts = <0 325 4>,
43 <0 346 1>, <0 347 1>, <0 348 1>, <0 349 1>,
44 <0 323 4>;
45 amd,per-channel-interrupt;
46 amd,speed-set = <0>;
47 amd,serdes-blwc = <1>, <1>, <0>;
48 amd,serdes-cdr-rate = <2>, <2>, <7>;
49 amd,serdes-pq-skew = <10>, <10>, <18>;
50 amd,serdes-tx-amp = <0>, <0>, <0>;
51 amd,serdes-dfe-tap-config = <3>, <3>, <3>;
52 amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
53 mac-address = [ 02 A1 A2 A3 A4 A5 ];
54 clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>;
55 clock-names = "dma_clk", "ptp_clk";
56 phy-mode = "xgmii";
57 #stream-id-cells = <16>;
58 dma-coherent;
59 };
60
61 xgmac1: xgmac@e0900000 {
62 compatible = "amd,xgbe-seattle-v1a";
63 reg = <0 0xe0900000 0 0x80000>,
64 <0 0xe0980000 0 0x80000>,
65 <0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */
66 <0 0xe1250080 0 0x00060>, /* SERDES IR 1/2 */
67 <0 0xe12500fc 0 0x00004>; /* SERDES IR 2/2 */
68 interrupts = <0 324 4>,
69 <0 341 1>, <0 342 1>, <0 343 1>, <0 344 1>,
70 <0 322 4>;
71 amd,per-channel-interrupt;
72 amd,speed-set = <0>;
73 amd,serdes-blwc = <1>, <1>, <0>;
74 amd,serdes-cdr-rate = <2>, <2>, <7>;
75 amd,serdes-pq-skew = <10>, <10>, <18>;
76 amd,serdes-tx-amp = <0>, <0>, <0>;
77 amd,serdes-dfe-tap-config = <3>, <3>, <3>;
78 amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
79 mac-address = [ 02 B1 B2 B3 B4 B5 ];
80 clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>;
81 clock-names = "dma_clk", "ptp_clk";
82 phy-mode = "xgmii";
83 #stream-id-cells = <16>;
84 dma-coherent;
85 };
86
87 xgmac0_smmu: smmu@e0600000 {
88 compatible = "arm,mmu-401";
89 reg = <0 0xe0600000 0 0x10000>;
90 #global-interrupts = <1>;
91 interrupts = /* Uses combined intr for both
92 * global and context
93 */
94 <0 336 4>,
95 <0 336 4>;
96
97 mmu-masters = <&xgmac0
98 0 1 2 3 4 5 6 7
99 16 17 18 19 20 21 22 23
100 >;
101 };
102
103 xgmac1_smmu: smmu@e0800000 {
104 compatible = "arm,mmu-401";
105 reg = <0 0xe0800000 0 0x10000>;
106 #global-interrupts = <1>;
107 interrupts = /* Uses combined intr for both
108 * global and context
109 */
110 <0 335 4>,
111 <0 335 4>;
112
113 mmu-masters = <&xgmac1
114 0 1 2 3 4 5 6 7
115 16 17 18 19 20 21 22 23
116 >;
117 };
diff --git a/arch/arm64/boot/dts/amd/husky.dts b/arch/arm64/boot/dts/amd/husky.dts
new file mode 100644
index 000000000000..1381d4b2bf1b
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/husky.dts
@@ -0,0 +1,83 @@
1/*
2 * DTS file for AMD/Linaro 96Boards Enterprise Edition Server (Husky) Board
3 * Note: Based-on AMD Seattle Rev.B0
4 *
5 * Copyright (C) 2015 Advanced Micro Devices, Inc.
6 */
7
8/dts-v1/;
9
10/include/ "amd-seattle-soc.dtsi"
11
12/ {
13 model = "Linaro 96Boards Enterprise Edition Server (Husky) Board";
14 compatible = "amd,seattle-overdrive", "amd,seattle";
15
16 chosen {
17 stdout-path = &serial0;
18 };
19
20 psci {
21 compatible = "arm,psci-0.2";
22 method = "smc";
23 };
24};
25
26&ccp0 {
27 status = "ok";
28 amd,zlib-support = <1>;
29};
30
31/**
32 * NOTE: In Rev.B, gpio0 is reserved.
33 */
34&gpio1 {
35 status = "ok";
36};
37
38&gpio2 {
39 status = "ok";
40};
41
42&gpio3 {
43 status = "ok";
44};
45
46&gpio4 {
47 status = "ok";
48};
49
50&i2c0 {
51 status = "ok";
52};
53
54&i2c1 {
55 status = "ok";
56};
57
58&pcie0 {
59 status = "ok";
60};
61
62&spi0 {
63 status = "ok";
64};
65
66&spi1 {
67 status = "ok";
68 sdcard0: sdcard@0 {
69 compatible = "mmc-spi-slot";
70 reg = <0>;
71 spi-max-frequency = <20000000>;
72 voltage-ranges = <3200 3400>;
73 pl022,hierarchy = <0>;
74 pl022,interface = <0>;
75 pl022,com-mode = <0x0>;
76 pl022,rx-level-trig = <0>;
77 pl022,tx-level-trig = <0>;
78 };
79};
80
81&smb0 {
82 /include/ "amd-seattle-xgbe-b.dtsi"
83};
diff --git a/arch/arm64/boot/dts/apm/apm-merlin.dts b/arch/arm64/boot/dts/apm/apm-merlin.dts
index e5ba8d5d0cae..387c6a8d0da9 100644
--- a/arch/arm64/boot/dts/apm/apm-merlin.dts
+++ b/arch/arm64/boot/dts/apm/apm-merlin.dts
@@ -30,7 +30,8 @@
30 label = "POWER"; 30 label = "POWER";
31 linux,code = <116>; 31 linux,code = <116>;
32 linux,input-type = <0x1>; 32 linux,input-type = <0x1>;
33 interrupts = <0x0 0x28 0x1>; 33 interrupt-parent = <&sbgpio>;
34 interrupts = <0x0 0x1>;
34 }; 35 };
35 }; 36 };
36 37
diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts b/arch/arm64/boot/dts/apm/apm-mustang.dts
index 178aef2cdd09..44db32ec5e9c 100644
--- a/arch/arm64/boot/dts/apm/apm-mustang.dts
+++ b/arch/arm64/boot/dts/apm/apm-mustang.dts
@@ -30,7 +30,8 @@
30 label = "POWER"; 30 label = "POWER";
31 linux,code = <116>; 31 linux,code = <116>;
32 linux,input-type = <0x1>; 32 linux,input-type = <0x1>;
33 interrupts = <0x0 0x2d 0x1>; 33 interrupt-parent = <&sbgpio>;
34 interrupts = <0x5 0x1>;
34 }; 35 };
35 }; 36 };
36 37
diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
index 5d87a3dc44b8..04d83a163e85 100644
--- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
@@ -224,7 +224,7 @@
224 }; 224 };
225 225
226 socpll: socpll@17000120 { 226 socpll: socpll@17000120 {
227 compatible = "apm,xgene-socpll-clock"; 227 compatible = "apm,xgene-socpll-v2-clock";
228 #clock-cells = <1>; 228 #clock-cells = <1>;
229 clocks = <&refclk 0>; 229 clocks = <&refclk 0>;
230 reg = <0x0 0x17000120 0x0 0x1000>; 230 reg = <0x0 0x17000120 0x0 0x1000>;
@@ -453,6 +453,25 @@
453 }; 453 };
454 }; 454 };
455 455
456 mailbox: mailbox@10540000 {
457 compatible = "apm,xgene-slimpro-mbox";
458 reg = <0x0 0x10540000 0x0 0x8000>;
459 #mbox-cells = <1>;
460 interrupts = <0x0 0x0 0x4
461 0x0 0x1 0x4
462 0x0 0x2 0x4
463 0x0 0x3 0x4
464 0x0 0x4 0x4
465 0x0 0x5 0x4
466 0x0 0x6 0x4
467 0x0 0x7 0x4>;
468 };
469
470 i2cslimpro {
471 compatible = "apm,xgene-slimpro-i2c";
472 mboxes = <&mailbox 0>;
473 };
474
456 serial0: serial@10600000 { 475 serial0: serial@10600000 {
457 device_type = "serial"; 476 device_type = "serial";
458 compatible = "ns16550"; 477 compatible = "ns16550";
@@ -598,6 +617,12 @@
598 <0x0 0x2d 0x1>, 617 <0x0 0x2d 0x1>,
599 <0x0 0x2e 0x1>, 618 <0x0 0x2e 0x1>,
600 <0x0 0x2f 0x1>; 619 <0x0 0x2f 0x1>;
620 interrupt-parent = <&gic>;
621 #interrupt-cells = <2>;
622 interrupt-controller;
623 apm,nr-gpios = <22>;
624 apm,nr-irqs = <8>;
625 apm,irq-start = <8>;
601 }; 626 };
602 627
603 sgenet0: ethernet@1f610000 { 628 sgenet0: ethernet@1f610000 {
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index fe30f7671ea3..5ceb3e4fc44f 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -691,6 +691,25 @@
691 msi-parent = <&msi>; 691 msi-parent = <&msi>;
692 }; 692 };
693 693
694 mailbox: mailbox@10540000 {
695 compatible = "apm,xgene-slimpro-mbox";
696 reg = <0x0 0x10540000 0x0 0xa000>;
697 #mbox-cells = <1>;
698 interrupts = <0x0 0x0 0x4>,
699 <0x0 0x1 0x4>,
700 <0x0 0x2 0x4>,
701 <0x0 0x3 0x4>,
702 <0x0 0x4 0x4>,
703 <0x0 0x5 0x4>,
704 <0x0 0x6 0x4>,
705 <0x0 0x7 0x4>;
706 };
707
708 i2cslimpro {
709 compatible = "apm,xgene-slimpro-i2c";
710 mboxes = <&mailbox 0>;
711 };
712
694 serial0: serial@1c020000 { 713 serial0: serial@1c020000 {
695 status = "disabled"; 714 status = "disabled";
696 device_type = "serial"; 715 device_type = "serial";
@@ -883,6 +902,9 @@
883 <0x0 0x2b 0x1>, 902 <0x0 0x2b 0x1>,
884 <0x0 0x2c 0x1>, 903 <0x0 0x2c 0x1>,
885 <0x0 0x2d 0x1>; 904 <0x0 0x2d 0x1>;
905 interrupt-parent = <&gic>;
906 #interrupt-cells = <2>;
907 interrupt-controller;
886 }; 908 };
887 909
888 rtc: rtc@10510000 { 910 rtc: rtc@10510000 {
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index dd5158eb5872..e5b59ca9debb 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -115,6 +115,7 @@
115 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
116 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
index 6bb3d4d9efa9..ce0ab84e0f2d 100644
--- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts
+++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
@@ -52,6 +52,14 @@
52 }; 52 };
53}; 53};
54 54
55&pcie0 {
56 status = "ok";
57};
58
59&pcie4 {
60 status = "ok";
61};
62
55&i2c0 { 63&i2c0 {
56 status = "ok"; 64 status = "ok";
57}; 65};
@@ -64,6 +72,10 @@
64 status = "ok"; 72 status = "ok";
65}; 73};
66 74
75&sdio0 {
76 status = "ok";
77};
78
67&nand { 79&nand {
68 nandcs@0 { 80 nandcs@0 {
69 compatible = "brcm,nandcs"; 81 compatible = "brcm,nandcs";
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index a510d3a8e647..6f81c9d7fb06 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -137,6 +137,80 @@
137 }; 137 };
138 }; 138 };
139 139
140 pcie0: pcie@20020000 {
141 compatible = "brcm,iproc-pcie";
142 reg = <0 0x20020000 0 0x1000>;
143
144 #interrupt-cells = <1>;
145 interrupt-map-mask = <0 0 0 0>;
146 interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>;
147
148 linux,pci-domain = <0>;
149
150 bus-range = <0x00 0xff>;
151
152 #address-cells = <3>;
153 #size-cells = <2>;
154 device_type = "pci";
155 ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
156
157 brcm,pcie-ob;
158 brcm,pcie-ob-oarr-size;
159 brcm,pcie-ob-axi-offset = <0x00000000>;
160 brcm,pcie-ob-window-size = <256>;
161
162 status = "disabled";
163
164 msi-parent = <&msi0>;
165 msi0: msi@20020000 {
166 compatible = "brcm,iproc-msi";
167 msi-controller;
168 interrupt-parent = <&gic>;
169 interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>,
170 <GIC_SPI 278 IRQ_TYPE_NONE>,
171 <GIC_SPI 279 IRQ_TYPE_NONE>,
172 <GIC_SPI 280 IRQ_TYPE_NONE>;
173 brcm,num-eq-region = <1>;
174 brcm,num-msi-msg-region = <1>;
175 };
176 };
177
178 pcie4: pcie@50020000 {
179 compatible = "brcm,iproc-pcie";
180 reg = <0 0x50020000 0 0x1000>;
181
182 #interrupt-cells = <1>;
183 interrupt-map-mask = <0 0 0 0>;
184 interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>;
185
186 linux,pci-domain = <4>;
187
188 bus-range = <0x00 0xff>;
189
190 #address-cells = <3>;
191 #size-cells = <2>;
192 device_type = "pci";
193 ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
194
195 brcm,pcie-ob;
196 brcm,pcie-ob-oarr-size;
197 brcm,pcie-ob-axi-offset = <0x30000000>;
198 brcm,pcie-ob-window-size = <256>;
199
200 status = "disabled";
201
202 msi-parent = <&msi4>;
203 msi4: msi@50020000 {
204 compatible = "brcm,iproc-msi";
205 msi-controller;
206 interrupt-parent = <&gic>;
207 interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>,
208 <GIC_SPI 302 IRQ_TYPE_NONE>,
209 <GIC_SPI 303 IRQ_TYPE_NONE>,
210 <GIC_SPI 304 IRQ_TYPE_NONE>;
211 };
212 };
213
140 soc: soc { 214 soc: soc {
141 compatible = "simple-bus"; 215 compatible = "simple-bus";
142 #address-cells = <1>; 216 #address-cells = <1>;
@@ -256,6 +330,46 @@
256 <0x65260000 0x1000>; 330 <0x65260000 0x1000>;
257 }; 331 };
258 332
333 timer0: timer@66030000 {
334 compatible = "arm,sp804", "arm,primecell";
335 reg = <0x66030000 0x1000>;
336 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&iprocslow>,
338 <&iprocslow>,
339 <&iprocslow>;
340 clock-names = "timer1", "timer2", "apb_pclk";
341 };
342
343 timer1: timer@66040000 {
344 compatible = "arm,sp804", "arm,primecell";
345 reg = <0x66040000 0x1000>;
346 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&iprocslow>,
348 <&iprocslow>,
349 <&iprocslow>;
350 clock-names = "timer1", "timer2", "apb_pclk";
351 };
352
353 timer2: timer@66050000 {
354 compatible = "arm,sp804", "arm,primecell";
355 reg = <0x66050000 0x1000>;
356 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&iprocslow>,
358 <&iprocslow>,
359 <&iprocslow>;
360 clock-names = "timer1", "timer2", "apb_pclk";
361 };
362
363 timer3: timer@66060000 {
364 compatible = "arm,sp804", "arm,primecell";
365 reg = <0x66060000 0x1000>;
366 interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&iprocslow>,
368 <&iprocslow>,
369 <&iprocslow>;
370 clock-names = "timer1", "timer2", "apb_pclk";
371 };
372
259 i2c0: i2c@66080000 { 373 i2c0: i2c@66080000 {
260 compatible = "brcm,iproc-i2c"; 374 compatible = "brcm,iproc-i2c";
261 reg = <0x66080000 0x100>; 375 reg = <0x66080000 0x100>;
@@ -266,6 +380,14 @@
266 status = "disabled"; 380 status = "disabled";
267 }; 381 };
268 382
383 wdt0: watchdog@66090000 {
384 compatible = "arm,sp805", "arm,primecell";
385 reg = <0x66090000 0x1000>;
386 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&iprocslow>, <&iprocslow>;
388 clock-names = "wdogclk", "apb_pclk";
389 };
390
269 i2c1: i2c@660b0000 { 391 i2c1: i2c@660b0000 {
270 compatible = "brcm,iproc-i2c"; 392 compatible = "brcm,iproc-i2c";
271 reg = <0x660b0000 0x100>; 393 reg = <0x660b0000 0x100>;
@@ -291,6 +413,24 @@
291 reg = <0x66220000 0x28>; 413 reg = <0x66220000 0x28>;
292 }; 414 };
293 415
416 sdio0: sdhci@66420000 {
417 compatible = "brcm,sdhci-iproc-cygnus";
418 reg = <0x66420000 0x100>;
419 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
420 bus-width = <8>;
421 clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
422 status = "disabled";
423 };
424
425 sdio1: sdhci@66430000 {
426 compatible = "brcm,sdhci-iproc-cygnus";
427 reg = <0x66430000 0x100>;
428 interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
429 bus-width = <8>;
430 clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
431 status = "disabled";
432 };
433
294 nand: nand@66460000 { 434 nand: nand@66460000 {
295 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; 435 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
296 reg = <0x66460000 0x600>, 436 reg = <0x66460000 0x600>,
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 42a61549afd4..be72bf5b58b5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -407,6 +407,7 @@
407 reg = <0x0 0x2f00000 0x0 0x10000>; 407 reg = <0x0 0x2f00000 0x0 0x10000>;
408 interrupts = <0 60 0x4>; 408 interrupts = <0 60 0x4>;
409 dr_mode = "host"; 409 dr_mode = "host";
410 snps,quirk-frame-length-adjustment = <0x20>;
410 }; 411 };
411 412
412 usb1: usb3@3000000 { 413 usb1: usb3@3000000 {
@@ -414,6 +415,7 @@
414 reg = <0x0 0x3000000 0x0 0x10000>; 415 reg = <0x0 0x3000000 0x0 0x10000>;
415 interrupts = <0 61 0x4>; 416 interrupts = <0 61 0x4>;
416 dr_mode = "host"; 417 dr_mode = "host";
418 snps,quirk-frame-length-adjustment = <0x20>;
417 }; 419 };
418 420
419 usb2: usb3@3100000 { 421 usb2: usb3@3100000 {
@@ -421,6 +423,7 @@
421 reg = <0x0 0x3100000 0x0 0x10000>; 423 reg = <0x0 0x3100000 0x0 0x10000>;
422 interrupts = <0 63 0x4>; 424 interrupts = <0 63 0x4>;
423 dr_mode = "host"; 425 dr_mode = "host";
426 snps,quirk-frame-length-adjustment = <0x20>;
424 }; 427 };
425 428
426 sata: sata@3200000 { 429 sata: sata@3200000 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 2b23d0360683..909a1e3e673b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -569,6 +569,7 @@
569 reg = <0x0 0x3100000 0x0 0x10000>; 569 reg = <0x0 0x3100000 0x0 0x10000>;
570 interrupts = <0 80 0x4>; /* Level high type */ 570 interrupts = <0 80 0x4>; /* Level high type */
571 dr_mode = "host"; 571 dr_mode = "host";
572 snps,quirk-frame-length-adjustment = <0x20>;
572 }; 573 };
573 574
574 usb1: usb3@3110000 { 575 usb1: usb3@3110000 {
@@ -577,6 +578,7 @@
577 reg = <0x0 0x3110000 0x0 0x10000>; 578 reg = <0x0 0x3110000 0x0 0x10000>;
578 interrupts = <0 81 0x4>; /* Level high type */ 579 interrupts = <0 81 0x4>; /* Level high type */
579 dr_mode = "host"; 580 dr_mode = "host";
581 snps,quirk-frame-length-adjustment = <0x20>;
580 }; 582 };
581 583
582 ccn@4000000 { 584 ccn@4000000 {
diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
index ae34e250456f..e9436c0d81f7 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
+++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts
@@ -11,6 +11,7 @@
11 11
12/dts-v1/; 12/dts-v1/;
13 13
14#include <dt-bindings/gpio/gpio.h>
14#include "hip05.dtsi" 15#include "hip05.dtsi"
15 16
16/ { 17/ {
@@ -29,8 +30,25 @@
29 chosen { 30 chosen {
30 stdout-path = "serial0:115200n8"; 31 stdout-path = "serial0:115200n8";
31 }; 32 };
33
34 gpio_keys {
35 compatible = "gpio-keys";
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 pwrbutton {
40 label = "Power Button";
41 gpios = <&porta 8 GPIO_ACTIVE_LOW>;
42 linux,code = <116>;
43 debounce-interval = <0>;
44 };
45 };
32}; 46};
33 47
34&uart0 { 48&uart0 {
35 status = "ok"; 49 status = "ok";
36}; 50};
51
52&peri_gpio0 {
53 status = "ok";
54};
diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index c1ea999c7be1..6319ff3b03ea 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -90,6 +90,7 @@
90 compatible = "arm,cortex-a57", "arm,armv8"; 90 compatible = "arm,cortex-a57", "arm,armv8";
91 reg = <0x20000>; 91 reg = <0x20000>;
92 enable-method = "psci"; 92 enable-method = "psci";
93 next-level-cache = <&cluster0_l2>;
93 }; 94 };
94 95
95 cpu1: cpu@20001 { 96 cpu1: cpu@20001 {
@@ -97,6 +98,7 @@
97 compatible = "arm,cortex-a57", "arm,armv8"; 98 compatible = "arm,cortex-a57", "arm,armv8";
98 reg = <0x20001>; 99 reg = <0x20001>;
99 enable-method = "psci"; 100 enable-method = "psci";
101 next-level-cache = <&cluster0_l2>;
100 }; 102 };
101 103
102 cpu2: cpu@20002 { 104 cpu2: cpu@20002 {
@@ -104,6 +106,7 @@
104 compatible = "arm,cortex-a57", "arm,armv8"; 106 compatible = "arm,cortex-a57", "arm,armv8";
105 reg = <0x20002>; 107 reg = <0x20002>;
106 enable-method = "psci"; 108 enable-method = "psci";
109 next-level-cache = <&cluster0_l2>;
107 }; 110 };
108 111
109 cpu3: cpu@20003 { 112 cpu3: cpu@20003 {
@@ -111,6 +114,7 @@
111 compatible = "arm,cortex-a57", "arm,armv8"; 114 compatible = "arm,cortex-a57", "arm,armv8";
112 reg = <0x20003>; 115 reg = <0x20003>;
113 enable-method = "psci"; 116 enable-method = "psci";
117 next-level-cache = <&cluster0_l2>;
114 }; 118 };
115 119
116 cpu4: cpu@20100 { 120 cpu4: cpu@20100 {
@@ -118,6 +122,7 @@
118 compatible = "arm,cortex-a57", "arm,armv8"; 122 compatible = "arm,cortex-a57", "arm,armv8";
119 reg = <0x20100>; 123 reg = <0x20100>;
120 enable-method = "psci"; 124 enable-method = "psci";
125 next-level-cache = <&cluster1_l2>;
121 }; 126 };
122 127
123 cpu5: cpu@20101 { 128 cpu5: cpu@20101 {
@@ -125,6 +130,7 @@
125 compatible = "arm,cortex-a57", "arm,armv8"; 130 compatible = "arm,cortex-a57", "arm,armv8";
126 reg = <0x20101>; 131 reg = <0x20101>;
127 enable-method = "psci"; 132 enable-method = "psci";
133 next-level-cache = <&cluster1_l2>;
128 }; 134 };
129 135
130 cpu6: cpu@20102 { 136 cpu6: cpu@20102 {
@@ -132,6 +138,7 @@
132 compatible = "arm,cortex-a57", "arm,armv8"; 138 compatible = "arm,cortex-a57", "arm,armv8";
133 reg = <0x20102>; 139 reg = <0x20102>;
134 enable-method = "psci"; 140 enable-method = "psci";
141 next-level-cache = <&cluster1_l2>;
135 }; 142 };
136 143
137 cpu7: cpu@20103 { 144 cpu7: cpu@20103 {
@@ -139,6 +146,7 @@
139 compatible = "arm,cortex-a57", "arm,armv8"; 146 compatible = "arm,cortex-a57", "arm,armv8";
140 reg = <0x20103>; 147 reg = <0x20103>;
141 enable-method = "psci"; 148 enable-method = "psci";
149 next-level-cache = <&cluster1_l2>;
142 }; 150 };
143 151
144 cpu8: cpu@20200 { 152 cpu8: cpu@20200 {
@@ -146,6 +154,7 @@
146 compatible = "arm,cortex-a57", "arm,armv8"; 154 compatible = "arm,cortex-a57", "arm,armv8";
147 reg = <0x20200>; 155 reg = <0x20200>;
148 enable-method = "psci"; 156 enable-method = "psci";
157 next-level-cache = <&cluster2_l2>;
149 }; 158 };
150 159
151 cpu9: cpu@20201 { 160 cpu9: cpu@20201 {
@@ -153,6 +162,7 @@
153 compatible = "arm,cortex-a57", "arm,armv8"; 162 compatible = "arm,cortex-a57", "arm,armv8";
154 reg = <0x20201>; 163 reg = <0x20201>;
155 enable-method = "psci"; 164 enable-method = "psci";
165 next-level-cache = <&cluster2_l2>;
156 }; 166 };
157 167
158 cpu10: cpu@20202 { 168 cpu10: cpu@20202 {
@@ -160,6 +170,7 @@
160 compatible = "arm,cortex-a57", "arm,armv8"; 170 compatible = "arm,cortex-a57", "arm,armv8";
161 reg = <0x20202>; 171 reg = <0x20202>;
162 enable-method = "psci"; 172 enable-method = "psci";
173 next-level-cache = <&cluster2_l2>;
163 }; 174 };
164 175
165 cpu11: cpu@20203 { 176 cpu11: cpu@20203 {
@@ -167,6 +178,7 @@
167 compatible = "arm,cortex-a57", "arm,armv8"; 178 compatible = "arm,cortex-a57", "arm,armv8";
168 reg = <0x20203>; 179 reg = <0x20203>;
169 enable-method = "psci"; 180 enable-method = "psci";
181 next-level-cache = <&cluster2_l2>;
170 }; 182 };
171 183
172 cpu12: cpu@20300 { 184 cpu12: cpu@20300 {
@@ -174,6 +186,7 @@
174 compatible = "arm,cortex-a57", "arm,armv8"; 186 compatible = "arm,cortex-a57", "arm,armv8";
175 reg = <0x20300>; 187 reg = <0x20300>;
176 enable-method = "psci"; 188 enable-method = "psci";
189 next-level-cache = <&cluster3_l2>;
177 }; 190 };
178 191
179 cpu13: cpu@20301 { 192 cpu13: cpu@20301 {
@@ -181,6 +194,7 @@
181 compatible = "arm,cortex-a57", "arm,armv8"; 194 compatible = "arm,cortex-a57", "arm,armv8";
182 reg = <0x20301>; 195 reg = <0x20301>;
183 enable-method = "psci"; 196 enable-method = "psci";
197 next-level-cache = <&cluster3_l2>;
184 }; 198 };
185 199
186 cpu14: cpu@20302 { 200 cpu14: cpu@20302 {
@@ -188,6 +202,7 @@
188 compatible = "arm,cortex-a57", "arm,armv8"; 202 compatible = "arm,cortex-a57", "arm,armv8";
189 reg = <0x20302>; 203 reg = <0x20302>;
190 enable-method = "psci"; 204 enable-method = "psci";
205 next-level-cache = <&cluster3_l2>;
191 }; 206 };
192 207
193 cpu15: cpu@20303 { 208 cpu15: cpu@20303 {
@@ -195,6 +210,23 @@
195 compatible = "arm,cortex-a57", "arm,armv8"; 210 compatible = "arm,cortex-a57", "arm,armv8";
196 reg = <0x20303>; 211 reg = <0x20303>;
197 enable-method = "psci"; 212 enable-method = "psci";
213 next-level-cache = <&cluster3_l2>;
214 };
215
216 cluster0_l2: l2-cache0 {
217 compatible = "cache";
218 };
219
220 cluster1_l2: l2-cache1 {
221 compatible = "cache";
222 };
223
224 cluster2_l2: l2-cache2 {
225 compatible = "cache";
226 };
227
228 cluster3_l2: l2-cache3 {
229 compatible = "cache";
198 }; 230 };
199 }; 231 };
200 232
@@ -214,11 +246,29 @@
214 <0x0 0xfe020000 0 0x10000>; /* GICV */ 246 <0x0 0xfe020000 0 0x10000>; /* GICV */
215 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 247 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
216 248
217 its_totems: interrupt-controller@8c000000 { 249 its_peri: interrupt-controller@8c000000 {
218 compatible = "arm,gic-v3-its"; 250 compatible = "arm,gic-v3-its";
219 msi-controller; 251 msi-controller;
220 reg = <0x0 0x8c000000 0x0 0x40000>; 252 reg = <0x0 0x8c000000 0x0 0x40000>;
221 }; 253 };
254
255 its_m3: interrupt-controller@a3000000 {
256 compatible = "arm,gic-v3-its";
257 msi-controller;
258 reg = <0x0 0xa3000000 0x0 0x40000>;
259 };
260
261 its_pcie: interrupt-controller@b7000000 {
262 compatible = "arm,gic-v3-its";
263 msi-controller;
264 reg = <0x0 0xb7000000 0x0 0x40000>;
265 };
266
267 its_dsa: interrupt-controller@c6000000 {
268 compatible = "arm,gic-v3-its";
269 msi-controller;
270 reg = <0x0 0xc6000000 0x0 0x40000>;
271 };
222 }; 272 };
223 273
224 timer { 274 timer {
@@ -230,7 +280,7 @@
230 }; 280 };
231 281
232 pmu { 282 pmu {
233 compatible = "arm,armv8-pmuv3"; 283 compatible = "arm,cortex-a57-pmu";
234 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 284 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
235 }; 285 };
236 286
@@ -272,5 +322,43 @@
272 reg-io-width = <4>; 322 reg-io-width = <4>;
273 status = "disabled"; 323 status = "disabled";
274 }; 324 };
325
326 peri_gpio0: gpio@802e0000 {
327 #address-cells = <1>;
328 #size-cells = <0>;
329 compatible = "snps,dw-apb-gpio";
330 reg = <0x0 0x802e0000 0x0 0x10000>;
331 status = "disabled";
332
333 porta: gpio-controller@0 {
334 compatible = "snps,dw-apb-gpio-port";
335 gpio-controller;
336 #gpio-cells = <2>;
337 snps,nr-gpios = <32>;
338 reg = <0>;
339 interrupt-controller;
340 #interrupt-cells = <2>;
341 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
342 };
343 };
344
345 peri_gpio1: gpio@802f0000 {
346 #address-cells = <1>;
347 #size-cells = <0>;
348 compatible = "snps,dw-apb-gpio";
349 reg = <0x0 0x802f0000 0x0 0x10000>;
350 status = "disabled";
351
352 portb: gpio-controller@0 {
353 compatible = "snps,dw-apb-gpio-port";
354 gpio-controller;
355 #gpio-cells = <2>;
356 snps,nr-gpios = <32>;
357 reg = <0>;
358 interrupt-controller;
359 #interrupt-cells = <2>;
360 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;
361 };
362 };
275 }; 363 };
276}; 364};
diff --git a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
index da7b6e613257..933cba359918 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
@@ -23,9 +23,8 @@ soc0: soc@000000000 {
23 }; 23 };
24 }; 24 };
25 25
26 dsa: dsa@c7000000 { 26 dsaf0: dsa@c7000000 {
27 compatible = "hisilicon,hns-dsaf-v1"; 27 compatible = "hisilicon,hns-dsaf-v1";
28 dsa_name = "dsaf0";
29 mode = "6port-16rss"; 28 mode = "6port-16rss";
30 interrupt-parent = <&mbigen_dsa>; 29 interrupt-parent = <&mbigen_dsa>;
31 30
@@ -127,7 +126,7 @@ soc0: soc@000000000 {
127 126
128 eth0: ethernet@0{ 127 eth0: ethernet@0{
129 compatible = "hisilicon,hns-nic-v1"; 128 compatible = "hisilicon,hns-nic-v1";
130 ae-name = "dsaf0"; 129 ae-handle = <&dsaf0>;
131 port-id = <0>; 130 port-id = <0>;
132 local-mac-address = [00 00 00 01 00 58]; 131 local-mac-address = [00 00 00 01 00 58];
133 status = "disabled"; 132 status = "disabled";
@@ -135,14 +134,14 @@ soc0: soc@000000000 {
135 }; 134 };
136 eth1: ethernet@1{ 135 eth1: ethernet@1{
137 compatible = "hisilicon,hns-nic-v1"; 136 compatible = "hisilicon,hns-nic-v1";
138 ae-name = "dsaf0"; 137 ae-handle = <&dsaf0>;
139 port-id = <1>; 138 port-id = <1>;
140 status = "disabled"; 139 status = "disabled";
141 dma-coherent; 140 dma-coherent;
142 }; 141 };
143 eth2: ethernet@2{ 142 eth2: ethernet@2{
144 compatible = "hisilicon,hns-nic-v1"; 143 compatible = "hisilicon,hns-nic-v1";
145 ae-name = "dsaf0"; 144 ae-handle = <&dsaf0>;
146 port-id = <2>; 145 port-id = <2>;
147 local-mac-address = [00 00 00 01 00 5a]; 146 local-mac-address = [00 00 00 01 00 5a];
148 status = "disabled"; 147 status = "disabled";
@@ -150,7 +149,7 @@ soc0: soc@000000000 {
150 }; 149 };
151 eth3: ethernet@3{ 150 eth3: ethernet@3{
152 compatible = "hisilicon,hns-nic-v1"; 151 compatible = "hisilicon,hns-nic-v1";
153 ae-name = "dsaf0"; 152 ae-handle = <&dsaf0>;
154 port-id = <3>; 153 port-id = <3>;
155 local-mac-address = [00 00 00 01 00 5b]; 154 local-mac-address = [00 00 00 01 00 5b];
156 status = "disabled"; 155 status = "disabled";
@@ -158,7 +157,7 @@ soc0: soc@000000000 {
158 }; 157 };
159 eth4: ethernet@4{ 158 eth4: ethernet@4{
160 compatible = "hisilicon,hns-nic-v1"; 159 compatible = "hisilicon,hns-nic-v1";
161 ae-name = "dsaf0"; 160 ae-handle = <&dsaf0>;
162 port-id = <4>; 161 port-id = <4>;
163 local-mac-address = [00 00 00 01 00 5c]; 162 local-mac-address = [00 00 00 01 00 5c];
164 status = "disabled"; 163 status = "disabled";
@@ -166,7 +165,7 @@ soc0: soc@000000000 {
166 }; 165 };
167 eth5: ethernet@5{ 166 eth5: ethernet@5{
168 compatible = "hisilicon,hns-nic-v1"; 167 compatible = "hisilicon,hns-nic-v1";
169 ae-name = "dsaf0"; 168 ae-handle = <&dsaf0>;
170 port-id = <5>; 169 port-id = <5>;
171 local-mac-address = [00 00 00 01 00 5d]; 170 local-mac-address = [00 00 00 01 00 5d];
172 status = "disabled"; 171 status = "disabled";
@@ -174,7 +173,7 @@ soc0: soc@000000000 {
174 }; 173 };
175 eth6: ethernet@6{ 174 eth6: ethernet@6{
176 compatible = "hisilicon,hns-nic-v1"; 175 compatible = "hisilicon,hns-nic-v1";
177 ae-name = "dsaf0"; 176 ae-handle = <&dsaf0>;
178 port-id = <6>; 177 port-id = <6>;
179 local-mac-address = [00 00 00 01 00 5e]; 178 local-mac-address = [00 00 00 01 00 5e];
180 status = "disabled"; 179 status = "disabled";
@@ -182,7 +181,7 @@ soc0: soc@000000000 {
182 }; 181 };
183 eth7: ethernet@7{ 182 eth7: ethernet@7{
184 compatible = "hisilicon,hns-nic-v1"; 183 compatible = "hisilicon,hns-nic-v1";
185 ae-name = "dsaf0"; 184 ae-handle = <&dsaf0>;
186 port-id = <7>; 185 port-id = <7>;
187 local-mac-address = [00 00 00 01 00 5f]; 186 local-mac-address = [00 00 00 01 00 5f];
188 status = "disabled"; 187 status = "disabled";
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index e427f04a9f45..7453a47b3047 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -214,6 +214,9 @@
214}; 214};
215 215
216&pwrap { 216&pwrap {
217 /* Only MT8173 E1 needs USB power domain */
218 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
219
217 pmic: mt6397 { 220 pmic: mt6397 {
218 compatible = "mediatek,mt6397"; 221 compatible = "mediatek,mt6397";
219 interrupt-parent = <&pio>; 222 interrupt-parent = <&pio>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index ec135eae31f5..f4bd3c9182ad 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -277,6 +277,11 @@
277 reg = <0 0x10200620 0 0x20>; 277 reg = <0 0x10200620 0 0x20>;
278 }; 278 };
279 279
280 efuse: efuse@10206000 {
281 compatible = "mediatek,mt8173-efuse";
282 reg = <0 0x10206000 0 0x1000>;
283 };
284
280 apmixedsys: clock-controller@10209000 { 285 apmixedsys: clock-controller@10209000 {
281 compatible = "mediatek,mt8173-apmixedsys"; 286 compatible = "mediatek,mt8173-apmixedsys";
282 reg = <0 0x10209000 0 0x1000>; 287 reg = <0 0x10209000 0 0x1000>;
@@ -397,6 +402,17 @@
397 status = "disabled"; 402 status = "disabled";
398 }; 403 };
399 404
405 nor_flash: spi@1100d000 {
406 compatible = "mediatek,mt8173-nor";
407 reg = <0 0x1100d000 0 0xe0>;
408 clocks = <&pericfg CLK_PERI_SPI>,
409 <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
410 clock-names = "spi", "sf";
411 #address-cells = <1>;
412 #size-cells = <0>;
413 status = "disabled";
414 };
415
400 i2c3: i2c@11010000 { 416 i2c3: i2c@11010000 {
401 compatible = "mediatek,mt8173-i2c"; 417 compatible = "mediatek,mt8173-i2c";
402 reg = <0 0x11010000 0 0x70>, 418 reg = <0 0x11010000 0 0x70>,
diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
index 7dfe1c085966..62f33fc84e3e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
@@ -12,6 +12,8 @@
12 rtc1 = "/rtc@0,7000e000"; 12 rtc1 = "/rtc@0,7000e000";
13 }; 13 };
14 14
15 chosen { };
16
15 memory { 17 memory {
16 device_type = "memory"; 18 device_type = "memory";
17 reg = <0x0 0x80000000 0x0 0x80000000>; 19 reg = <0x0 0x80000000 0x0 0x80000000>;
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 8e94af64ee94..fa1f661ccccf 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -1,4 +1,5 @@
1dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb msm8916-mtp.dtb 1dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb msm8916-mtp.dtb
2dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
2 3
3always := $(dtb-y) 4always := $(dtb-y)
4subdir-y := $(dts-dirs) 5subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
index e03c11d9d834..f881437d53c5 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
@@ -33,7 +33,7 @@
33 pm8916_mpps_leds: pm8916_mpps_leds { 33 pm8916_mpps_leds: pm8916_mpps_leds {
34 pinconf { 34 pinconf {
35 pins = "mpp2", "mpp3"; 35 pins = "mpp2", "mpp3";
36 function = PMIC_GPIO_FUNC_NORMAL; 36 function = "digital";
37 output-low; 37 output-low;
38 }; 38 };
39 }; 39 };
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
index cbeee0bcdf52..ee828a8a8236 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
@@ -10,4 +10,18 @@
10 output-low; 10 output-low;
11 }; 11 };
12 }; 12 };
13
14 usb_id_default: usb-id-default {
15 pinmux {
16 function = "gpio";
17 pins = "gpio121";
18 };
19
20 pinconf {
21 pins = "gpio121";
22 drive-strength = <8>;
23 input-enable;
24 bias-pull-up;
25 };
26 };
13}; 27};
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index db17c5d5689c..205ef89b8ca0 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -24,6 +24,8 @@
24 i2c0 = &blsp_i2c2; 24 i2c0 = &blsp_i2c2;
25 i2c1 = &blsp_i2c6; 25 i2c1 = &blsp_i2c6;
26 i2c3 = &blsp_i2c4; 26 i2c3 = &blsp_i2c4;
27 spi0 = &blsp_spi5;
28 spi1 = &blsp_spi3;
27 }; 29 };
28 30
29 chosen { 31 chosen {
@@ -127,9 +129,173 @@
127 default-state = "off"; 129 default-state = "off";
128 }; 130 };
129 }; 131 };
132
133 sdhci@07824000 {
134 vmmc-supply = <&pm8916_l8>;
135 vqmmc-supply = <&pm8916_l5>;
136
137 pinctrl-names = "default", "sleep";
138 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
139 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
140 status = "okay";
141 };
142
143 usb@78d9000 {
144 extcon = <&usb_id>, <&usb_id>;
145 status = "okay";
146 };
147
148 ehci@78d9000 {
149 status = "okay";
150 };
151
152 phy@78d9000 {
153 v1p8-supply = <&pm8916_l7>;
154 v3p3-supply = <&pm8916_l13>;
155 vddcx-supply = <&pm8916_s1>;
156 extcon = <&usb_id>, <&usb_id>;
157 dr_mode = "otg";
158 status = "okay";
159 switch-gpio = <&pm8916_gpios 4 GPIO_ACTIVE_HIGH>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&usb_sw_sel_pm>;
162 };
163
164 lpass@07708000 {
165 status = "okay";
166 };
167 };
168
169 usb2513 {
170 compatible = "smsc,usb3503";
171 reset-gpios = <&pm8916_gpios 3 GPIO_ACTIVE_LOW>;
172 initial-mode = <1>;
173 };
174
175 usb_id: usb-id {
176 compatible = "linux,extcon-usb-gpio";
177 id-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&usb_id_default>;
130 }; 180 };
131}; 181};
132 182
133&sdhc_1 { 183&smd_rpm_regulators {
134 status = "okay"; 184 vdd_l1_l2_l3-supply = <&pm8916_s3>;
185 vdd_l5-supply = <&pm8916_s3>;
186 vdd_l4_l5_l6-supply = <&pm8916_s4>;
187 vdd_l7-supply = <&pm8916_s4>;
188
189 s1 {
190 regulator-min-microvolt = <375000>;
191 regulator-max-microvolt = <1562000>;
192 };
193
194 s3 {
195 regulator-min-microvolt = <375000>;
196 regulator-max-microvolt = <1562000>;
197 };
198
199 s4 {
200 regulator-min-microvolt = <1800000>;
201 regulator-max-microvolt = <1800000>;
202
203 regulator-always-on;
204 regulator-boot-on;
205 };
206
207 l1 {
208 regulator-min-microvolt = <375000>;
209 regulator-max-microvolt = <1525000>;
210 };
211
212 l2 {
213 regulator-min-microvolt = <375000>;
214 regulator-max-microvolt = <1525000>;
215 };
216
217 l3 {
218 regulator-min-microvolt = <375000>;
219 regulator-max-microvolt = <1525000>;
220 };
221
222 l4 {
223 regulator-min-microvolt = <1750000>;
224 regulator-max-microvolt = <3337000>;
225 };
226
227 l5 {
228 regulator-min-microvolt = <1750000>;
229 regulator-max-microvolt = <3337000>;
230 };
231
232 l6 {
233 regulator-min-microvolt = <1750000>;
234 regulator-max-microvolt = <3337000>;
235 };
236
237 l7 {
238 regulator-min-microvolt = <1750000>;
239 regulator-max-microvolt = <3337000>;
240 };
241
242 l8 {
243 regulator-min-microvolt = <1750000>;
244 regulator-max-microvolt = <3337000>;
245 };
246
247 l9 {
248 regulator-min-microvolt = <1750000>;
249 regulator-max-microvolt = <3337000>;
250 };
251
252 l10 {
253 regulator-min-microvolt = <1750000>;
254 regulator-max-microvolt = <3337000>;
255 };
256
257 l11 {
258 regulator-min-microvolt = <1750000>;
259 regulator-max-microvolt = <3337000>;
260 };
261
262 l12 {
263 regulator-min-microvolt = <1750000>;
264 regulator-max-microvolt = <3337000>;
265 };
266
267 l13 {
268 regulator-min-microvolt = <1750000>;
269 regulator-max-microvolt = <3337000>;
270 };
271
272 l14 {
273 regulator-min-microvolt = <1750000>;
274 regulator-max-microvolt = <3337000>;
275 };
276
277 /**
278 * 1.8v required on LS expansion
279 * for mezzanine boards
280 */
281 l15 {
282 regulator-min-microvolt = <1750000>;
283 regulator-max-microvolt = <3337000>;
284 regulator-always-on;
285 };
286
287 l16 {
288 regulator-min-microvolt = <1750000>;
289 regulator-max-microvolt = <3337000>;
290 };
291
292 l17 {
293 regulator-min-microvolt = <1750000>;
294 regulator-max-microvolt = <3337000>;
295 };
296
297 l18 {
298 regulator-min-microvolt = <1750000>;
299 regulator-max-microvolt = <3337000>;
300 };
135}; 301};
diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
index 955c6f174d4c..10c83e11c272 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -82,7 +82,7 @@
82 }; 82 };
83 pinconf_cs { 83 pinconf_cs {
84 pins = "gpio2"; 84 pins = "gpio2";
85 drive-strength = <2>; 85 drive-strength = <16>;
86 bias-disable; 86 bias-disable;
87 output-high; 87 output-high;
88 }; 88 };
@@ -110,13 +110,13 @@
110 pins = "gpio6"; 110 pins = "gpio6";
111 }; 111 };
112 pinconf { 112 pinconf {
113 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 113 pins = "gpio4", "gpio5", "gpio7";
114 drive-strength = <12>; 114 drive-strength = <12>;
115 bias-disable; 115 bias-disable;
116 }; 116 };
117 pinconf_cs { 117 pinconf_cs {
118 pins = "gpio6"; 118 pins = "gpio6";
119 drive-strength = <2>; 119 drive-strength = <16>;
120 bias-disable; 120 bias-disable;
121 output-high; 121 output-high;
122 }; 122 };
@@ -144,13 +144,13 @@
144 pins = "gpio10"; 144 pins = "gpio10";
145 }; 145 };
146 pinconf { 146 pinconf {
147 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 147 pins = "gpio8", "gpio9", "gpio11";
148 drive-strength = <12>; 148 drive-strength = <12>;
149 bias-disable; 149 bias-disable;
150 }; 150 };
151 pinconf_cs { 151 pinconf_cs {
152 pins = "gpio10"; 152 pins = "gpio10";
153 drive-strength = <2>; 153 drive-strength = <16>;
154 bias-disable; 154 bias-disable;
155 output-high; 155 output-high;
156 }; 156 };
@@ -178,13 +178,13 @@
178 pins = "gpio14"; 178 pins = "gpio14";
179 }; 179 };
180 pinconf { 180 pinconf {
181 pins = "gpio12", "gpio13", "gpio14", "gpio15"; 181 pins = "gpio12", "gpio13", "gpio15";
182 drive-strength = <12>; 182 drive-strength = <12>;
183 bias-disable; 183 bias-disable;
184 }; 184 };
185 pinconf_cs { 185 pinconf_cs {
186 pins = "gpio14"; 186 pins = "gpio14";
187 drive-strength = <2>; 187 drive-strength = <16>;
188 bias-disable; 188 bias-disable;
189 output-high; 189 output-high;
190 }; 190 };
@@ -212,13 +212,13 @@
212 pins = "gpio18"; 212 pins = "gpio18";
213 }; 213 };
214 pinconf { 214 pinconf {
215 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 215 pins = "gpio16", "gpio17", "gpio19";
216 drive-strength = <12>; 216 drive-strength = <12>;
217 bias-disable; 217 bias-disable;
218 }; 218 };
219 pinconf_cs { 219 pinconf_cs {
220 pins = "gpio18"; 220 pins = "gpio18";
221 drive-strength = <2>; 221 drive-strength = <16>;
222 bias-disable; 222 bias-disable;
223 output-high; 223 output-high;
224 }; 224 };
@@ -246,13 +246,13 @@
246 pins = "gpio22"; 246 pins = "gpio22";
247 }; 247 };
248 pinconf { 248 pinconf {
249 pins = "gpio20", "gpio21", "gpio22", "gpio23"; 249 pins = "gpio20", "gpio21", "gpio23";
250 drive-strength = <12>; 250 drive-strength = <12>;
251 bias-disable; 251 bias-disable;
252 }; 252 };
253 pinconf_cs { 253 pinconf_cs {
254 pins = "gpio22"; 254 pins = "gpio22";
255 drive-strength = <2>; 255 drive-strength = <16>;
256 bias-disable; 256 bias-disable;
257 output-high; 257 output-high;
258 }; 258 };
@@ -504,4 +504,220 @@
504 }; 504 };
505 }; 505 };
506 }; 506 };
507
508 ext-codec-lines {
509 ext_codec_lines_act: lines_on {
510 pinmux {
511 function = "gpio";
512 pins = "gpio67";
513 };
514 pinconf {
515 pins = "gpio67";
516 drive-strength = <8>;
517 bias-disable;
518 output-high;
519 };
520 };
521 ext_codec_lines_sus: lines_off {
522 pinmux {
523 function = "gpio";
524 pins = "gpio67";
525 };
526 pinconf {
527 pins = "gpio67";
528 drive-strength = <2>;
529 bias-disable;
530 };
531 };
532 };
533
534 cdc-pdm-lines {
535 cdc_pdm_lines_act: pdm_lines_on {
536 pinmux {
537 function = "cdc_pdm0";
538 pins = "gpio63", "gpio64", "gpio65", "gpio66",
539 "gpio67", "gpio68";
540 };
541 pinconf {
542 pins = "gpio63", "gpio64", "gpio65", "gpio66",
543 "gpio67", "gpio68";
544 drive-strength = <8>;
545 bias-pull-none;
546 };
547 };
548 cdc_pdm_lines_sus: pdm_lines_off {
549 pinmux {
550 function = "cdc_pdm0";
551 pins = "gpio63", "gpio64", "gpio65", "gpio66",
552 "gpio67", "gpio68";
553 };
554 pinconf {
555 pins = "gpio63", "gpio64", "gpio65", "gpio66",
556 "gpio67", "gpio68";
557 drive-strength = <2>;
558 bias-disable;
559 };
560 };
561 };
562
563 ext-pri-tlmm-lines {
564 ext_pri_tlmm_lines_act: ext_pa_on {
565 pinmux {
566 function = "pri_mi2s";
567 pins = "gpio113", "gpio114", "gpio115",
568 "gpio116";
569 };
570 pinconf {
571 pins = "gpio113", "gpio114", "gpio115",
572 "gpio116";
573 drive-strength = <8>;
574 bias-pull-none;
575 };
576 };
577
578 ext_pri_tlmm_lines_sus: ext_pa_off {
579 pinmux {
580 function = "pri_mi2s";
581 pins = "gpio113", "gpio114", "gpio115",
582 "gpio116";
583 };
584 pinconf {
585 pins = "gpio113", "gpio114", "gpio115",
586 "gpio116";
587 drive-strength = <2>;
588 bias-disable;
589 };
590 };
591 };
592
593 ext-pri-ws-line {
594 ext_pri_ws_act: ext_pa_on {
595 pinmux {
596 function = "pri_mi2s_ws";
597 pins = "gpio110";
598 };
599 pinconf {
600 pins = "gpio110";
601 drive-strength = <8>;
602 bias-pull-none;
603 };
604 };
605
606 ext_pri_ws_sus: ext_pa_off {
607 pinmux {
608 function = "pri_mi2s_ws";
609 pins = "gpio110";
610 };
611 pinconf {
612 pins = "gpio110";
613 drive-strength = <2>;
614 bias-disable;
615 };
616 };
617 };
618
619 ext-mclk-tlmm-lines {
620 ext_mclk_tlmm_lines_act: mclk_lines_on {
621 pinmux {
622 function = "pri_mi2s";
623 pins = "gpio116";
624 };
625 pinconf {
626 pins = "gpio116";
627 drive-strength = <8>;
628 bias-pull-none;
629 };
630 };
631 ext_mclk_tlmm_lines_sus: mclk_lines_off {
632 pinmux {
633 function = "pri_mi2s";
634 pins = "gpio116";
635 };
636 pinconf {
637 pins = "gpio116";
638 drive-strength = <2>;
639 bias-disable;
640 };
641 };
642 };
643
644 /* secondary Mi2S */
645 ext-sec-tlmm-lines {
646 ext_sec_tlmm_lines_act: tlmm_lines_on {
647 pinmux {
648 function = "sec_mi2s";
649 pins = "gpio112", "gpio117", "gpio118",
650 "gpio119";
651 };
652 pinconf {
653 pins = "gpio112", "gpio117", "gpio118",
654 "gpio119";
655 drive-strength = <8>;
656 bias-pull-none;
657 };
658 };
659 ext_sec_tlmm_lines_sus: tlmm_lines_off {
660 pinmux {
661 function = "sec_mi2s";
662 pins = "gpio112", "gpio117", "gpio118",
663 "gpio119";
664 };
665 pinconf {
666 pins = "gpio112", "gpio117", "gpio118",
667 "gpio119";
668 drive-strength = <2>;
669 bias-disable;
670 };
671 };
672 };
673
674 cdc-dmic-lines {
675 cdc_dmic_lines_act: dmic_lines_on {
676 pinmux_dmic0_clk {
677 function = "dmic0_clk";
678 pins = "gpio0";
679 };
680 pinmux_dmic0_data {
681 function = "dmic0_data";
682 pins = "gpio1";
683 };
684 pinconf {
685 pins = "gpio0", "gpio1";
686 drive-strength = <8>;
687 };
688 };
689 cdc_dmic_lines_sus: dmic_lines_off {
690 pinconf {
691 pins = "gpio0", "gpio1";
692 drive-strength = <2>;
693 bias-disable;
694 };
695 };
696 };
697
698 cross-conn-det {
699 cross_conn_det_act: lines_on {
700 pinmux {
701 function = "gpio";
702 pins = "gpio120";
703 };
704 pinconf {
705 pins = "gpio120";
706 drive-strength = <8>;
707 output-low;
708 bias-pull-down;
709 };
710 };
711 cross_conn_det_sus: lines_off {
712 pinmux {
713 function = "gpio";
714 pins = "gpio120";
715 };
716 pinconf {
717 pins = "gpio120";
718 drive-strength = <2>;
719 bias-disable;
720 };
721 };
722 };
507}; 723};
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 915321479998..96812007850e 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -61,24 +61,33 @@
61 device_type = "cpu"; 61 device_type = "cpu";
62 compatible = "arm,cortex-a53", "arm,armv8"; 62 compatible = "arm,cortex-a53", "arm,armv8";
63 reg = <0x0>; 63 reg = <0x0>;
64 next-level-cache = <&L2_0>;
64 }; 65 };
65 66
66 CPU1: cpu@1 { 67 CPU1: cpu@1 {
67 device_type = "cpu"; 68 device_type = "cpu";
68 compatible = "arm,cortex-a53", "arm,armv8"; 69 compatible = "arm,cortex-a53", "arm,armv8";
69 reg = <0x1>; 70 reg = <0x1>;
71 next-level-cache = <&L2_0>;
70 }; 72 };
71 73
72 CPU2: cpu@2 { 74 CPU2: cpu@2 {
73 device_type = "cpu"; 75 device_type = "cpu";
74 compatible = "arm,cortex-a53", "arm,armv8"; 76 compatible = "arm,cortex-a53", "arm,armv8";
75 reg = <0x2>; 77 reg = <0x2>;
78 next-level-cache = <&L2_0>;
76 }; 79 };
77 80
78 CPU3: cpu@3 { 81 CPU3: cpu@3 {
79 device_type = "cpu"; 82 device_type = "cpu";
80 compatible = "arm,cortex-a53", "arm,armv8"; 83 compatible = "arm,cortex-a53", "arm,armv8";
81 reg = <0x3>; 84 reg = <0x3>;
85 next-level-cache = <&L2_0>;
86 };
87
88 L2_0: l2-cache {
89 compatible = "cache";
90 cache-level = <2>;
82 }; 91 };
83 }; 92 };
84 93
@@ -134,7 +143,7 @@
134 #interrupt-cells = <2>; 143 #interrupt-cells = <2>;
135 }; 144 };
136 145
137 gcc: qcom,gcc@1800000 { 146 gcc: clock-controller@1800000 {
138 compatible = "qcom,gcc-msm8916"; 147 compatible = "qcom,gcc-msm8916";
139 #clock-cells = <1>; 148 #clock-cells = <1>;
140 #reset-cells = <1>; 149 #reset-cells = <1>;
@@ -343,6 +352,32 @@
343 status = "disabled"; 352 status = "disabled";
344 }; 353 };
345 354
355 lpass: lpass@07708000 {
356 status = "disabled";
357 compatible = "qcom,lpass-cpu-apq8016";
358 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
359 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
360 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
361 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
362 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
363 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
364 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
365
366 clock-names = "ahbix-clk",
367 "pcnoc-mport-clk",
368 "pcnoc-sway-clk",
369 "mi2s-bit-clk0",
370 "mi2s-bit-clk1",
371 "mi2s-bit-clk2",
372 "mi2s-bit-clk3";
373 #sound-dai-cells = <1>;
374
375 interrupts = <0 160 0>;
376 interrupt-names = "lpass-irq-lpaif";
377 reg = <0x07708000 0x10000>;
378 reg-names = "lpass-lpaif";
379 };
380
346 sdhc_1: sdhci@07824000 { 381 sdhc_1: sdhci@07824000 {
347 compatible = "qcom,sdhci-msm-v4"; 382 compatible = "qcom,sdhci-msm-v4";
348 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 383 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
@@ -395,10 +430,11 @@
395 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>, 430 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
396 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 431 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
397 432
398 qcom,vdd-levels = <1 5 7>; 433 qcom,vdd-levels = <500000 1000000 1320000>;
399 qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>; 434 qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
400 dr_mode = "peripheral"; 435 dr_mode = "peripheral";
401 qcom,otg-control = <2>; // PMIC 436 qcom,otg-control = <2>; // PMIC
437 qcom,manual-pullup;
402 438
403 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 439 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
404 <&gcc GCC_USB_HS_SYSTEM_CLK>, 440 <&gcc GCC_USB_HS_SYSTEM_CLK>,
@@ -515,11 +551,15 @@
515 compatible = "qcom,rpm-msm8916"; 551 compatible = "qcom,rpm-msm8916";
516 qcom,smd-channels = "rpm_requests"; 552 qcom,smd-channels = "rpm_requests";
517 553
518 pm8916-regulators { 554 rpmcc: qcom,rpmcc {
555 compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
556 #clock-cells = <1>;
557 };
558
559 smd_rpm_regulators: pm8916-regulators {
519 compatible = "qcom,rpm-pm8916-regulators"; 560 compatible = "qcom,rpm-pm8916-regulators";
520 561
521 pm8916_s1: s1 {}; 562 pm8916_s1: s1 {};
522 pm8916_s2: s2 {};
523 pm8916_s3: s3 {}; 563 pm8916_s3: s3 {};
524 pm8916_s4: s4 {}; 564 pm8916_s4: s4 {};
525 565
diff --git a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts
new file mode 100644
index 000000000000..619af44a595d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts
@@ -0,0 +1,21 @@
1/*
2 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15
16#include "msm8996-mtp.dtsi"
17
18/ {
19 model = "Qualcomm Technologies, Inc. MSM 8996 MTP";
20 compatible = "qcom,msm8996-mtp";
21};
diff --git a/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi
new file mode 100644
index 000000000000..9bab5c011c07
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi
@@ -0,0 +1,30 @@
1/*
2 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include "msm8996.dtsi"
15
16/ {
17 aliases {
18 serial0 = &blsp2_uart1;
19 };
20
21 chosen {
22 stdout-path = "serial0";
23 };
24
25 soc {
26 serial@75b0000 {
27 status = "okay";
28 };
29 };
30};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
new file mode 100644
index 000000000000..0506fb808c56
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -0,0 +1,269 @@
1/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/clock/qcom,gcc-msm8996.h>
15#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
16
17/ {
18 model = "Qualcomm Technologies, Inc. MSM8996";
19
20 interrupt-parent = <&intc>;
21
22 #address-cells = <2>;
23 #size-cells = <2>;
24
25 chosen { };
26
27 memory {
28 device_type = "memory";
29 /* We expect the bootloader to fill in the reg */
30 reg = <0 0 0 0>;
31 };
32
33 cpus {
34 #address-cells = <2>;
35 #size-cells = <0>;
36
37 CPU0: cpu@0 {
38 device_type = "cpu";
39 compatible = "qcom,kryo";
40 reg = <0x0 0x0>;
41 enable-method = "psci";
42 next-level-cache = <&L2_0>;
43 L2_0: l2-cache {
44 compatible = "cache";
45 cache-level = <2>;
46 };
47 };
48
49 CPU1: cpu@1 {
50 device_type = "cpu";
51 compatible = "qcom,kryo";
52 reg = <0x0 0x1>;
53 enable-method = "psci";
54 next-level-cache = <&L2_0>;
55 };
56
57 CPU2: cpu@100 {
58 device_type = "cpu";
59 compatible = "qcom,kryo";
60 reg = <0x0 0x100>;
61 enable-method = "psci";
62 next-level-cache = <&L2_1>;
63 L2_1: l2-cache {
64 compatible = "cache";
65 cache-level = <2>;
66 };
67 };
68
69 CPU3: cpu@101 {
70 device_type = "cpu";
71 compatible = "qcom,kryo";
72 reg = <0x0 0x101>;
73 enable-method = "psci";
74 next-level-cache = <&L2_1>;
75 };
76
77 cpu-map {
78 cluster0 {
79 core0 {
80 cpu = <&CPU0>;
81 };
82
83 core1 {
84 cpu = <&CPU1>;
85 };
86 };
87
88 cluster1 {
89 core0 {
90 cpu = <&CPU2>;
91 };
92
93 core1 {
94 cpu = <&CPU3>;
95 };
96 };
97 };
98 };
99
100 timer {
101 compatible = "arm,armv8-timer";
102 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
103 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
104 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
105 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
106 };
107
108 clocks {
109 xo_board {
110 compatible = "fixed-clock";
111 #clock-cells = <0>;
112 clock-frequency = <19200000>;
113 clock-output-names = "xo_board";
114 };
115
116 sleep_clk {
117 compatible = "fixed-clock";
118 #clock-cells = <0>;
119 clock-frequency = <32764>;
120 clock-output-names = "sleep_clk";
121 };
122 };
123
124 psci {
125 compatible = "arm,psci-1.0";
126 method = "smc";
127 };
128
129 soc: soc {
130 #address-cells = <1>;
131 #size-cells = <1>;
132 ranges = <0 0 0 0xffffffff>;
133 compatible = "simple-bus";
134
135 intc: interrupt-controller@9bc0000 {
136 compatible = "arm,gic-v3";
137 #interrupt-cells = <3>;
138 interrupt-controller;
139 #redistributor-regions = <1>;
140 redistributor-stride = <0x0 0x40000>;
141 reg = <0x09bc0000 0x10000>,
142 <0x09c00000 0x100000>;
143 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
144 };
145
146 gcc: clock-controller@300000 {
147 compatible = "qcom,gcc-msm8996";
148 #clock-cells = <1>;
149 #reset-cells = <1>;
150 #power-domain-cells = <1>;
151 reg = <0x300000 0x90000>;
152 };
153
154 blsp2_uart1: serial@75b0000 {
155 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
156 reg = <0x75b0000 0x1000>;
157 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
159 <&gcc GCC_BLSP2_AHB_CLK>;
160 clock-names = "core", "iface";
161 status = "disabled";
162 };
163
164 pinctrl@1010000 {
165 compatible = "qcom,msm8996-pinctrl";
166 reg = <0x01010000 0x300000>;
167 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
168 gpio-controller;
169 #gpio-cells = <2>;
170 interrupt-controller;
171 #interrupt-cells = <2>;
172 };
173
174 timer@09840000 {
175 #address-cells = <1>;
176 #size-cells = <1>;
177 ranges;
178 compatible = "arm,armv7-timer-mem";
179 reg = <0x09840000 0x1000>;
180 clock-frequency = <19200000>;
181
182 frame@9850000 {
183 frame-number = <0>;
184 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
186 reg = <0x09850000 0x1000>,
187 <0x09860000 0x1000>;
188 };
189
190 frame@9870000 {
191 frame-number = <1>;
192 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
193 reg = <0x09870000 0x1000>;
194 status = "disabled";
195 };
196
197 frame@9880000 {
198 frame-number = <2>;
199 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
200 reg = <0x09880000 0x1000>;
201 status = "disabled";
202 };
203
204 frame@9890000 {
205 frame-number = <3>;
206 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
207 reg = <0x09890000 0x1000>;
208 status = "disabled";
209 };
210
211 frame@98a0000 {
212 frame-number = <4>;
213 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
214 reg = <0x098a0000 0x1000>;
215 status = "disabled";
216 };
217
218 frame@98b0000 {
219 frame-number = <5>;
220 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
221 reg = <0x098b0000 0x1000>;
222 status = "disabled";
223 };
224
225 frame@98c0000 {
226 frame-number = <6>;
227 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
228 reg = <0x098c0000 0x1000>;
229 status = "disabled";
230 };
231 };
232
233 spmi_bus: qcom,spmi@400f000 {
234 compatible = "qcom,spmi-pmic-arb";
235 reg = <0x400f000 0x1000>,
236 <0x4400000 0x800000>,
237 <0x4c00000 0x800000>,
238 <0x5800000 0x200000>,
239 <0x400a000 0x002100>;
240 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
241 interrupt-names = "periph_irq";
242 interrupts = <GIC_SPI 326 IRQ_TYPE_NONE>;
243 qcom,ee = <0>;
244 qcom,channel = <0>;
245 #address-cells = <2>;
246 #size-cells = <0>;
247 interrupt-controller;
248 #interrupt-cells = <4>;
249 };
250
251 mmcc: clock-controller@8c0000 {
252 compatible = "qcom,mmcc-msm8996";
253 #clock-cells = <1>;
254 #reset-cells = <1>;
255 #power-domain-cells = <1>;
256 reg = <0x8c0000 0x40000>;
257 assigned-clocks = <&mmcc MMPLL9_PLL>,
258 <&mmcc MMPLL1_PLL>,
259 <&mmcc MMPLL3_PLL>,
260 <&mmcc MMPLL4_PLL>,
261 <&mmcc MMPLL5_PLL>;
262 assigned-clock-rates = <624000000>,
263 <810000000>,
264 <980000000>,
265 <960000000>,
266 <825000000>;
267 };
268 };
269};
diff --git a/arch/arm64/boot/dts/qcom/pm8004.dtsi b/arch/arm64/boot/dts/qcom/pm8004.dtsi
new file mode 100644
index 000000000000..ef2207afa86b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm8004.dtsi
@@ -0,0 +1,19 @@
1#include <dt-bindings/interrupt-controller/irq.h>
2#include <dt-bindings/spmi/spmi.h>
3
4&spmi_bus {
5
6 pmic@4 {
7 compatible = "qcom,pm8004", "qcom,spmi-pmic";
8 reg = <0x4 SPMI_USID>;
9 #address-cells = <1>;
10 #size-cells = <0>;
11 };
12
13 pmic@5 {
14 compatible = "qcom,pm8004", "qcom,spmi-pmic";
15 reg = <0x5 SPMI_USID>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 };
19};
diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi
index 37432451ee4c..f71679b15d54 100644
--- a/arch/arm64/boot/dts/qcom/pm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi
@@ -12,7 +12,7 @@
12 12
13 rtc@6000 { 13 rtc@6000 {
14 compatible = "qcom,pm8941-rtc"; 14 compatible = "qcom,pm8941-rtc";
15 reg = <0x6000 0x6100>; 15 reg = <0x6000>;
16 reg-names = "rtc", "alarm"; 16 reg-names = "rtc", "alarm";
17 interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; 17 interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
18 }; 18 };
@@ -27,7 +27,7 @@
27 27
28 pm8916_gpios: gpios@c000 { 28 pm8916_gpios: gpios@c000 {
29 compatible = "qcom,pm8916-gpio"; 29 compatible = "qcom,pm8916-gpio";
30 reg = <0xc000 0x400>; 30 reg = <0xc000>;
31 gpio-controller; 31 gpio-controller;
32 #gpio-cells = <2>; 32 #gpio-cells = <2>;
33 interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, 33 interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
@@ -38,7 +38,7 @@
38 38
39 pm8916_mpps: mpps@a000 { 39 pm8916_mpps: mpps@a000 {
40 compatible = "qcom,pm8916-mpp"; 40 compatible = "qcom,pm8916-mpp";
41 reg = <0xa000 0x400>; 41 reg = <0xa000>;
42 gpio-controller; 42 gpio-controller;
43 #gpio-cells = <2>; 43 #gpio-cells = <2>;
44 interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, 44 interrupts = <0 0xa0 0 IRQ_TYPE_NONE>,
@@ -49,7 +49,7 @@
49 49
50 pm8916_temp: temp-alarm@2400 { 50 pm8916_temp: temp-alarm@2400 {
51 compatible = "qcom,spmi-temp-alarm"; 51 compatible = "qcom,spmi-temp-alarm";
52 reg = <0x2400 0x100>; 52 reg = <0x2400>;
53 interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; 53 interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
54 io-channels = <&pm8916_vadc VADC_DIE_TEMP>; 54 io-channels = <&pm8916_vadc VADC_DIE_TEMP>;
55 io-channel-names = "thermal"; 55 io-channel-names = "thermal";
@@ -58,7 +58,7 @@
58 58
59 pm8916_vadc: vadc@3100 { 59 pm8916_vadc: vadc@3100 {
60 compatible = "qcom,spmi-vadc"; 60 compatible = "qcom,spmi-vadc";
61 reg = <0x3100 0x100>; 61 reg = <0x3100>;
62 interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; 62 interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
63 #address-cells = <1>; 63 #address-cells = <1>;
64 #size-cells = <0>; 64 #size-cells = <0>;
diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi
new file mode 100644
index 000000000000..1222d2e904f6
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi
@@ -0,0 +1,62 @@
1#include <dt-bindings/interrupt-controller/irq.h>
2#include <dt-bindings/spmi/spmi.h>
3
4&spmi_bus {
5
6 pmic@0 {
7 compatible = "qcom,pm8994", "qcom,spmi-pmic";
8 reg = <0x0 SPMI_USID>;
9 #address-cells = <1>;
10 #size-cells = <0>;
11
12 pm8994_gpios: gpios@c000 {
13 compatible = "qcom,pm8994-gpio";
14 reg = <0xc000>;
15 gpio-controller;
16 #gpio-cells = <2>;
17 interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
18 <0 0xc1 0 IRQ_TYPE_NONE>,
19 <0 0xc2 0 IRQ_TYPE_NONE>,
20 <0 0xc3 0 IRQ_TYPE_NONE>,
21 <0 0xc4 0 IRQ_TYPE_NONE>,
22 <0 0xc5 0 IRQ_TYPE_NONE>,
23 <0 0xc6 0 IRQ_TYPE_NONE>,
24 <0 0xc7 0 IRQ_TYPE_NONE>,
25 <0 0xc8 0 IRQ_TYPE_NONE>,
26 <0 0xc9 0 IRQ_TYPE_NONE>,
27 <0 0xca 0 IRQ_TYPE_NONE>,
28 <0 0xcb 0 IRQ_TYPE_NONE>,
29 <0 0xcc 0 IRQ_TYPE_NONE>,
30 <0 0xcd 0 IRQ_TYPE_NONE>,
31 <0 0xce 0 IRQ_TYPE_NONE>,
32 <0 0xd0 0 IRQ_TYPE_NONE>,
33 <0 0xd1 0 IRQ_TYPE_NONE>,
34 <0 0xd2 0 IRQ_TYPE_NONE>,
35 <0 0xd3 0 IRQ_TYPE_NONE>,
36 <0 0xd4 0 IRQ_TYPE_NONE>,
37 <0 0xd5 0 IRQ_TYPE_NONE>;
38 };
39
40 pm8994_mpps: mpps@a000 {
41 compatible = "qcom,pm8994-mpp";
42 reg = <0xa000>;
43 gpio-controller;
44 #gpio-cells = <2>;
45 interrupts = <0 0xa0 0 IRQ_TYPE_NONE>,
46 <0 0xa1 0 IRQ_TYPE_NONE>,
47 <0 0xa2 0 IRQ_TYPE_NONE>,
48 <0 0xa3 0 IRQ_TYPE_NONE>,
49 <0 0xa4 0 IRQ_TYPE_NONE>,
50 <0 0xa5 0 IRQ_TYPE_NONE>,
51 <0 0xa6 0 IRQ_TYPE_NONE>,
52 <0 0xa7 0 IRQ_TYPE_NONE>;
53 };
54 };
55
56 pmic@1 {
57 compatible = "qcom,pm8994", "qcom,spmi-pmic";
58 reg = <0x1 SPMI_USID>;
59 #address-cells = <1>;
60 #size-cells = <0>;
61 };
62};
diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi
new file mode 100644
index 000000000000..d3879a4e8076
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi
@@ -0,0 +1,19 @@
1#include <dt-bindings/interrupt-controller/irq.h>
2#include <dt-bindings/spmi/spmi.h>
3
4&spmi_bus {
5
6 pmic@2 {
7 compatible = "qcom,pmi8994", "qcom,spmi-pmic";
8 reg = <0x2 SPMI_USID>;
9 #address-cells = <1>;
10 #size-cells = <0>;
11 };
12
13 pmic@3 {
14 compatible = "qcom,pmi8994", "qcom,spmi-pmic";
15 reg = <0x3 SPMI_USID>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 };
19};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index 265d12ff6022..b992b1a3d956 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -33,6 +33,7 @@
33 33
34/dts-v1/; 34/dts-v1/;
35#include "r8a7795.dtsi" 35#include "r8a7795.dtsi"
36#include <dt-bindings/gpio/gpio.h>
36 37
37/ { 38/ {
38 model = "Renesas Salvator-X board based on r8a7795"; 39 model = "Renesas Salvator-X board based on r8a7795";
@@ -61,6 +62,54 @@
61 clock-frequency = <24576000>; 62 clock-frequency = <24576000>;
62 }; 63 };
63 64
65 vcc_sdhi0: regulator@1 {
66 compatible = "regulator-fixed";
67
68 regulator-name = "SDHI0 Vcc";
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
71
72 gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
73 enable-active-high;
74 };
75
76 vccq_sdhi0: regulator@2 {
77 compatible = "regulator-gpio";
78
79 regulator-name = "SDHI0 VccQ";
80 regulator-min-microvolt = <1800000>;
81 regulator-max-microvolt = <3300000>;
82
83 gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
84 gpios-states = <1>;
85 states = <3300000 1
86 1800000 0>;
87 };
88
89 vcc_sdhi3: regulator@3 {
90 compatible = "regulator-fixed";
91
92 regulator-name = "SDHI3 Vcc";
93 regulator-min-microvolt = <3300000>;
94 regulator-max-microvolt = <3300000>;
95
96 gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
97 enable-active-high;
98 };
99
100 vccq_sdhi3: regulator@4 {
101 compatible = "regulator-gpio";
102
103 regulator-name = "SDHI3 VccQ";
104 regulator-min-microvolt = <1800000>;
105 regulator-max-microvolt = <3300000>;
106
107 gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
108 gpios-states = <1>;
109 states = <3300000 1
110 1800000 0>;
111 };
112
64 audio_clkout: audio_clkout { 113 audio_clkout: audio_clkout {
65 /* 114 /*
66 * This is same as <&rcar_sound 0> 115 * This is same as <&rcar_sound 0>
@@ -93,6 +142,9 @@
93}; 142};
94 143
95&pfc { 144&pfc {
145 pinctrl-0 = <&scif_clk_pins>;
146 pinctrl-names = "default";
147
96 scif1_pins: scif1 { 148 scif1_pins: scif1 {
97 renesas,groups = "scif1_data_a", "scif1_ctrl"; 149 renesas,groups = "scif1_data_a", "scif1_ctrl";
98 renesas,function = "scif1"; 150 renesas,function = "scif1";
@@ -101,6 +153,10 @@
101 renesas,groups = "scif2_data_a"; 153 renesas,groups = "scif2_data_a";
102 renesas,function = "scif2"; 154 renesas,function = "scif2";
103 }; 155 };
156 scif_clk_pins: scif_clk {
157 renesas,groups = "scif_clk_a";
158 renesas,function = "scif_clk";
159 };
104 160
105 i2c2_pins: i2c2 { 161 i2c2_pins: i2c2 {
106 renesas,groups = "i2c2_a"; 162 renesas,groups = "i2c2_a";
@@ -112,6 +168,16 @@
112 renesas,function = "avb"; 168 renesas,function = "avb";
113 }; 169 };
114 170
171 sdhi0_pins: sd0 {
172 renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
173 renesas,function = "sdhi0";
174 };
175
176 sdhi3_pins: sd3 {
177 renesas,groups = "sdhi3_data4", "sdhi3_ctrl";
178 renesas,function = "sdhi3";
179 };
180
115 sound_pins: sound { 181 sound_pins: sound {
116 renesas,groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; 182 renesas,groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
117 renesas,function = "ssi"; 183 renesas,function = "ssi";
@@ -122,6 +188,16 @@
122 "audio_clkout_a", "audio_clkout3_a"; 188 "audio_clkout_a", "audio_clkout3_a";
123 renesas,function = "audio_clk"; 189 renesas,function = "audio_clk";
124 }; 190 };
191
192 usb1_pins: usb1 {
193 renesas,groups = "usb1";
194 renesas,function = "usb1";
195 };
196
197 usb2_pins: usb2 {
198 renesas,groups = "usb2";
199 renesas,function = "usb2";
200 };
125}; 201};
126 202
127&scif1 { 203&scif1 {
@@ -138,6 +214,11 @@
138 status = "okay"; 214 status = "okay";
139}; 215};
140 216
217&scif_clk {
218 clock-frequency = <14745600>;
219 status = "okay";
220};
221
141&i2c2 { 222&i2c2 {
142 pinctrl-0 = <&i2c2_pins>; 223 pinctrl-0 = <&i2c2_pins>;
143 pinctrl-names = "default"; 224 pinctrl-names = "default";
@@ -216,6 +297,30 @@
216 status = "okay"; 297 status = "okay";
217}; 298};
218 299
300&sdhi0 {
301 pinctrl-0 = <&sdhi0_pins>;
302 pinctrl-names = "default";
303
304 vmmc-supply = <&vcc_sdhi0>;
305 vqmmc-supply = <&vccq_sdhi0>;
306 cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
307 wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
308 bus-width = <4>;
309 status = "okay";
310};
311
312&sdhi3 {
313 pinctrl-0 = <&sdhi3_pins>;
314 pinctrl-names = "default";
315
316 vmmc-supply = <&vcc_sdhi3>;
317 vqmmc-supply = <&vccq_sdhi3>;
318 cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
319 wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
320 bus-width = <4>;
321 status = "okay";
322};
323
219&ssi1 { 324&ssi1 {
220 shared-pin; 325 shared-pin;
221}; 326};
@@ -249,3 +354,37 @@
249 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 354 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
250 }; 355 };
251}; 356};
357
358&xhci0 {
359 status = "okay";
360};
361
362&usb2_phy1 {
363 pinctrl-0 = <&usb1_pins>;
364 pinctrl-names = "default";
365
366 status = "okay";
367};
368
369&usb2_phy2 {
370 pinctrl-0 = <&usb2_pins>;
371 pinctrl-names = "default";
372
373 status = "okay";
374};
375
376&ehci1 {
377 status = "okay";
378};
379
380&ehci2 {
381 status = "okay";
382};
383
384&ohci1 {
385 status = "okay";
386};
387
388&ohci2 {
389 status = "okay";
390};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index bb353cde1253..a7315ebe3883 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -39,6 +39,7 @@
39 compatible = "arm,cortex-a57", "arm,armv8"; 39 compatible = "arm,cortex-a57", "arm,armv8";
40 reg = <0x0>; 40 reg = <0x0>;
41 device_type = "cpu"; 41 device_type = "cpu";
42 next-level-cache = <&L2_CA57>;
42 enable-method = "psci"; 43 enable-method = "psci";
43 }; 44 };
44 45
@@ -46,22 +47,37 @@
46 compatible = "arm,cortex-a57","arm,armv8"; 47 compatible = "arm,cortex-a57","arm,armv8";
47 reg = <0x1>; 48 reg = <0x1>;
48 device_type = "cpu"; 49 device_type = "cpu";
50 next-level-cache = <&L2_CA57>;
49 enable-method = "psci"; 51 enable-method = "psci";
50 }; 52 };
51 a57_2: cpu@2 { 53 a57_2: cpu@2 {
52 compatible = "arm,cortex-a57","arm,armv8"; 54 compatible = "arm,cortex-a57","arm,armv8";
53 reg = <0x2>; 55 reg = <0x2>;
54 device_type = "cpu"; 56 device_type = "cpu";
57 next-level-cache = <&L2_CA57>;
55 enable-method = "psci"; 58 enable-method = "psci";
56 }; 59 };
57 a57_3: cpu@3 { 60 a57_3: cpu@3 {
58 compatible = "arm,cortex-a57","arm,armv8"; 61 compatible = "arm,cortex-a57","arm,armv8";
59 reg = <0x3>; 62 reg = <0x3>;
60 device_type = "cpu"; 63 device_type = "cpu";
64 next-level-cache = <&L2_CA57>;
61 enable-method = "psci"; 65 enable-method = "psci";
62 }; 66 };
63 }; 67 };
64 68
69 L2_CA57: cache-controller@0 {
70 compatible = "cache";
71 cache-unified;
72 cache-level = <2>;
73 };
74
75 L2_CA53: cache-controller@1 {
76 compatible = "cache";
77 cache-unified;
78 cache-level = <2>;
79 };
80
65 extal_clk: extal { 81 extal_clk: extal {
66 compatible = "fixed-clock"; 82 compatible = "fixed-clock";
67 #clock-cells = <0>; 83 #clock-cells = <0>;
@@ -99,6 +115,14 @@
99 clock-frequency = <0>; 115 clock-frequency = <0>;
100 }; 116 };
101 117
118 /* External SCIF clock - to be overridden by boards that provide it */
119 scif_clk: scif {
120 compatible = "fixed-clock";
121 #clock-cells = <0>;
122 clock-frequency = <0>;
123 status = "disabled";
124 };
125
102 soc { 126 soc {
103 compatible = "simple-bus"; 127 compatible = "simple-bus";
104 interrupt-parent = <&gic>; 128 interrupt-parent = <&gic>;
@@ -113,7 +137,9 @@
113 #address-cells = <0>; 137 #address-cells = <0>;
114 interrupt-controller; 138 interrupt-controller;
115 reg = <0x0 0xf1010000 0 0x1000>, 139 reg = <0x0 0xf1010000 0 0x1000>,
116 <0x0 0xf1020000 0 0x2000>; 140 <0x0 0xf1020000 0 0x2000>,
141 <0x0 0xf1040000 0 0x20000>,
142 <0x0 0xf1060000 0 0x2000>;
117 interrupts = <GIC_PPI 9 143 interrupts = <GIC_PPI 9
118 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 144 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
119 }; 145 };
@@ -230,8 +256,8 @@
230 power-domains = <&cpg>; 256 power-domains = <&cpg>;
231 }; 257 };
232 258
233 pmu { 259 pmu_a57 {
234 compatible = "arm,armv8-pmuv3"; 260 compatible = "arm,cortex-a57-pmu";
235 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 261 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
@@ -266,23 +292,23 @@
266 audma0: dma-controller@ec700000 { 292 audma0: dma-controller@ec700000 {
267 compatible = "renesas,rcar-dmac"; 293 compatible = "renesas,rcar-dmac";
268 reg = <0 0xec700000 0 0x10000>; 294 reg = <0 0xec700000 0 0x10000>;
269 interrupts = <0 350 IRQ_TYPE_LEVEL_HIGH 295 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
270 0 320 IRQ_TYPE_LEVEL_HIGH 296 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
271 0 321 IRQ_TYPE_LEVEL_HIGH 297 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
272 0 322 IRQ_TYPE_LEVEL_HIGH 298 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
273 0 323 IRQ_TYPE_LEVEL_HIGH 299 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
274 0 324 IRQ_TYPE_LEVEL_HIGH 300 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
275 0 325 IRQ_TYPE_LEVEL_HIGH 301 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
276 0 326 IRQ_TYPE_LEVEL_HIGH 302 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
277 0 327 IRQ_TYPE_LEVEL_HIGH 303 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
278 0 328 IRQ_TYPE_LEVEL_HIGH 304 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
279 0 329 IRQ_TYPE_LEVEL_HIGH 305 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
280 0 330 IRQ_TYPE_LEVEL_HIGH 306 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
281 0 331 IRQ_TYPE_LEVEL_HIGH 307 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
282 0 332 IRQ_TYPE_LEVEL_HIGH 308 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
283 0 333 IRQ_TYPE_LEVEL_HIGH 309 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
284 0 334 IRQ_TYPE_LEVEL_HIGH 310 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
285 0 335 IRQ_TYPE_LEVEL_HIGH>; 311 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
286 interrupt-names = "error", 312 interrupt-names = "error",
287 "ch0", "ch1", "ch2", "ch3", 313 "ch0", "ch1", "ch2", "ch3",
288 "ch4", "ch5", "ch6", "ch7", 314 "ch4", "ch5", "ch6", "ch7",
@@ -298,23 +324,23 @@
298 audma1: dma-controller@ec720000 { 324 audma1: dma-controller@ec720000 {
299 compatible = "renesas,rcar-dmac"; 325 compatible = "renesas,rcar-dmac";
300 reg = <0 0xec720000 0 0x10000>; 326 reg = <0 0xec720000 0 0x10000>;
301 interrupts = <0 351 IRQ_TYPE_LEVEL_HIGH 327 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
302 0 336 IRQ_TYPE_LEVEL_HIGH 328 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
303 0 337 IRQ_TYPE_LEVEL_HIGH 329 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
304 0 338 IRQ_TYPE_LEVEL_HIGH 330 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
305 0 339 IRQ_TYPE_LEVEL_HIGH 331 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
306 0 340 IRQ_TYPE_LEVEL_HIGH 332 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
307 0 341 IRQ_TYPE_LEVEL_HIGH 333 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
308 0 342 IRQ_TYPE_LEVEL_HIGH 334 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
309 0 343 IRQ_TYPE_LEVEL_HIGH 335 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
310 0 344 IRQ_TYPE_LEVEL_HIGH 336 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
311 0 345 IRQ_TYPE_LEVEL_HIGH 337 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
312 0 346 IRQ_TYPE_LEVEL_HIGH 338 GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
313 0 347 IRQ_TYPE_LEVEL_HIGH 339 GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
314 0 348 IRQ_TYPE_LEVEL_HIGH 340 GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
315 0 349 IRQ_TYPE_LEVEL_HIGH 341 GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
316 0 382 IRQ_TYPE_LEVEL_HIGH 342 GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
317 0 383 IRQ_TYPE_LEVEL_HIGH>; 343 GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
318 interrupt-names = "error", 344 interrupt-names = "error",
319 "ch0", "ch1", "ch2", "ch3", 345 "ch0", "ch1", "ch2", "ch3",
320 "ch4", "ch5", "ch6", "ch7", 346 "ch4", "ch5", "ch6", "ch7",
@@ -332,20 +358,123 @@
332 reg = <0 0xe6060000 0 0x50c>; 358 reg = <0 0xe6060000 0 0x50c>;
333 }; 359 };
334 360
361 intc_ex: interrupt-controller@e61c0000 {
362 compatible = "renesas,intc-ex-r8a7795", "renesas,irqc";
363 #interrupt-cells = <2>;
364 interrupt-controller;
365 reg = <0 0xe61c0000 0 0x200>;
366 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
367 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
368 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
369 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
370 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
371 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&cpg CPG_MOD 407>;
373 power-domains = <&cpg>;
374 };
375
335 dmac0: dma-controller@e6700000 { 376 dmac0: dma-controller@e6700000 {
336 /* Empty node for now */ 377 compatible = "renesas,dmac-r8a7795",
378 "renesas,rcar-dmac";
379 reg = <0 0xe6700000 0 0x10000>;
380 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
381 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
382 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
383 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
384 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
385 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
386 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
387 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
388 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
389 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
390 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
391 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
392 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
393 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
394 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
395 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
396 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
397 interrupt-names = "error",
398 "ch0", "ch1", "ch2", "ch3",
399 "ch4", "ch5", "ch6", "ch7",
400 "ch8", "ch9", "ch10", "ch11",
401 "ch12", "ch13", "ch14", "ch15";
402 clocks = <&cpg CPG_MOD 219>;
403 clock-names = "fck";
404 power-domains = <&cpg>;
405 #dma-cells = <1>;
406 dma-channels = <16>;
337 }; 407 };
338 408
339 dmac1: dma-controller@e7300000 { 409 dmac1: dma-controller@e7300000 {
340 /* Empty node for now */ 410 compatible = "renesas,dmac-r8a7795",
411 "renesas,rcar-dmac";
412 reg = <0 0xe7300000 0 0x10000>;
413 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
414 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
415 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
416 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
417 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
418 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
419 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
420 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
421 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
422 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
423 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
424 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
425 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
426 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
427 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
428 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
429 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
430 interrupt-names = "error",
431 "ch0", "ch1", "ch2", "ch3",
432 "ch4", "ch5", "ch6", "ch7",
433 "ch8", "ch9", "ch10", "ch11",
434 "ch12", "ch13", "ch14", "ch15";
435 clocks = <&cpg CPG_MOD 218>;
436 clock-names = "fck";
437 power-domains = <&cpg>;
438 #dma-cells = <1>;
439 dma-channels = <16>;
341 }; 440 };
342 441
343 dmac2: dma-controller@e7310000 { 442 dmac2: dma-controller@e7310000 {
344 /* Empty node for now */ 443 compatible = "renesas,dmac-r8a7795",
444 "renesas,rcar-dmac";
445 reg = <0 0xe7310000 0 0x10000>;
446 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
447 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
448 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
449 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
450 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
451 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
452 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
453 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
454 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
455 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
456 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
457 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
458 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
459 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
460 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
461 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
462 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
463 interrupt-names = "error",
464 "ch0", "ch1", "ch2", "ch3",
465 "ch4", "ch5", "ch6", "ch7",
466 "ch8", "ch9", "ch10", "ch11",
467 "ch12", "ch13", "ch14", "ch15";
468 clocks = <&cpg CPG_MOD 217>;
469 clock-names = "fck";
470 power-domains = <&cpg>;
471 #dma-cells = <1>;
472 dma-channels = <16>;
345 }; 473 };
346 474
347 avb: ethernet@e6800000 { 475 avb: ethernet@e6800000 {
348 compatible = "renesas,etheravb-r8a7795"; 476 compatible = "renesas,etheravb-r8a7795",
477 "renesas,etheravb-rcar-gen3";
349 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 478 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
350 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 479 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
@@ -387,11 +516,15 @@
387 }; 516 };
388 517
389 hscif0: serial@e6540000 { 518 hscif0: serial@e6540000 {
390 compatible = "renesas,hscif-r8a7795", "renesas,hscif"; 519 compatible = "renesas,hscif-r8a7795",
520 "renesas,rcar-gen3-hscif",
521 "renesas,hscif";
391 reg = <0 0xe6540000 0 96>; 522 reg = <0 0xe6540000 0 96>;
392 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 523 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&cpg CPG_MOD 520>; 524 clocks = <&cpg CPG_MOD 520>,
394 clock-names = "sci_ick"; 525 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
526 <&scif_clk>;
527 clock-names = "fck", "brg_int", "scif_clk";
395 dmas = <&dmac1 0x31>, <&dmac1 0x30>; 528 dmas = <&dmac1 0x31>, <&dmac1 0x30>;
396 dma-names = "tx", "rx"; 529 dma-names = "tx", "rx";
397 power-domains = <&cpg>; 530 power-domains = <&cpg>;
@@ -399,11 +532,15 @@
399 }; 532 };
400 533
401 hscif1: serial@e6550000 { 534 hscif1: serial@e6550000 {
402 compatible = "renesas,hscif-r8a7795", "renesas,hscif"; 535 compatible = "renesas,hscif-r8a7795",
536 "renesas,rcar-gen3-hscif",
537 "renesas,hscif";
403 reg = <0 0xe6550000 0 96>; 538 reg = <0 0xe6550000 0 96>;
404 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 539 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&cpg CPG_MOD 519>; 540 clocks = <&cpg CPG_MOD 519>,
406 clock-names = "sci_ick"; 541 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
542 <&scif_clk>;
543 clock-names = "fck", "brg_int", "scif_clk";
407 dmas = <&dmac1 0x33>, <&dmac1 0x32>; 544 dmas = <&dmac1 0x33>, <&dmac1 0x32>;
408 dma-names = "tx", "rx"; 545 dma-names = "tx", "rx";
409 power-domains = <&cpg>; 546 power-domains = <&cpg>;
@@ -411,11 +548,15 @@
411 }; 548 };
412 549
413 hscif2: serial@e6560000 { 550 hscif2: serial@e6560000 {
414 compatible = "renesas,hscif-r8a7795", "renesas,hscif"; 551 compatible = "renesas,hscif-r8a7795",
552 "renesas,rcar-gen3-hscif",
553 "renesas,hscif";
415 reg = <0 0xe6560000 0 96>; 554 reg = <0 0xe6560000 0 96>;
416 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 555 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&cpg CPG_MOD 518>; 556 clocks = <&cpg CPG_MOD 518>,
418 clock-names = "sci_ick"; 557 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
558 <&scif_clk>;
559 clock-names = "fck", "brg_int", "scif_clk";
419 dmas = <&dmac1 0x35>, <&dmac1 0x34>; 560 dmas = <&dmac1 0x35>, <&dmac1 0x34>;
420 dma-names = "tx", "rx"; 561 dma-names = "tx", "rx";
421 power-domains = <&cpg>; 562 power-domains = <&cpg>;
@@ -423,11 +564,15 @@
423 }; 564 };
424 565
425 hscif3: serial@e66a0000 { 566 hscif3: serial@e66a0000 {
426 compatible = "renesas,hscif-r8a7795", "renesas,hscif"; 567 compatible = "renesas,hscif-r8a7795",
568 "renesas,rcar-gen3-hscif",
569 "renesas,hscif";
427 reg = <0 0xe66a0000 0 96>; 570 reg = <0 0xe66a0000 0 96>;
428 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 571 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&cpg CPG_MOD 517>; 572 clocks = <&cpg CPG_MOD 517>,
430 clock-names = "sci_ick"; 573 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
574 <&scif_clk>;
575 clock-names = "fck", "brg_int", "scif_clk";
431 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 576 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
432 dma-names = "tx", "rx"; 577 dma-names = "tx", "rx";
433 power-domains = <&cpg>; 578 power-domains = <&cpg>;
@@ -435,11 +580,15 @@
435 }; 580 };
436 581
437 hscif4: serial@e66b0000 { 582 hscif4: serial@e66b0000 {
438 compatible = "renesas,hscif-r8a7795", "renesas,hscif"; 583 compatible = "renesas,hscif-r8a7795",
584 "renesas,rcar-gen3-hscif",
585 "renesas,hscif";
439 reg = <0 0xe66b0000 0 96>; 586 reg = <0 0xe66b0000 0 96>;
440 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 587 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&cpg CPG_MOD 516>; 588 clocks = <&cpg CPG_MOD 516>,
442 clock-names = "sci_ick"; 589 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
590 <&scif_clk>;
591 clock-names = "fck", "brg_int", "scif_clk";
443 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 592 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
444 dma-names = "tx", "rx"; 593 dma-names = "tx", "rx";
445 power-domains = <&cpg>; 594 power-domains = <&cpg>;
@@ -447,11 +596,14 @@
447 }; 596 };
448 597
449 scif0: serial@e6e60000 { 598 scif0: serial@e6e60000 {
450 compatible = "renesas,scif-r8a7795", "renesas,scif"; 599 compatible = "renesas,scif-r8a7795",
600 "renesas,rcar-gen3-scif", "renesas,scif";
451 reg = <0 0xe6e60000 0 64>; 601 reg = <0 0xe6e60000 0 64>;
452 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 602 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&cpg CPG_MOD 207>; 603 clocks = <&cpg CPG_MOD 207>,
454 clock-names = "sci_ick"; 604 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
605 <&scif_clk>;
606 clock-names = "fck", "brg_int", "scif_clk";
455 dmas = <&dmac1 0x51>, <&dmac1 0x50>; 607 dmas = <&dmac1 0x51>, <&dmac1 0x50>;
456 dma-names = "tx", "rx"; 608 dma-names = "tx", "rx";
457 power-domains = <&cpg>; 609 power-domains = <&cpg>;
@@ -459,11 +611,14 @@
459 }; 611 };
460 612
461 scif1: serial@e6e68000 { 613 scif1: serial@e6e68000 {
462 compatible = "renesas,scif-r8a7795", "renesas,scif"; 614 compatible = "renesas,scif-r8a7795",
615 "renesas,rcar-gen3-scif", "renesas,scif";
463 reg = <0 0xe6e68000 0 64>; 616 reg = <0 0xe6e68000 0 64>;
464 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 617 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&cpg CPG_MOD 206>; 618 clocks = <&cpg CPG_MOD 206>,
466 clock-names = "sci_ick"; 619 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
620 <&scif_clk>;
621 clock-names = "fck", "brg_int", "scif_clk";
467 dmas = <&dmac1 0x53>, <&dmac1 0x52>; 622 dmas = <&dmac1 0x53>, <&dmac1 0x52>;
468 dma-names = "tx", "rx"; 623 dma-names = "tx", "rx";
469 power-domains = <&cpg>; 624 power-domains = <&cpg>;
@@ -471,11 +626,14 @@
471 }; 626 };
472 627
473 scif2: serial@e6e88000 { 628 scif2: serial@e6e88000 {
474 compatible = "renesas,scif-r8a7795", "renesas,scif"; 629 compatible = "renesas,scif-r8a7795",
630 "renesas,rcar-gen3-scif", "renesas,scif";
475 reg = <0 0xe6e88000 0 64>; 631 reg = <0 0xe6e88000 0 64>;
476 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 632 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&cpg CPG_MOD 310>; 633 clocks = <&cpg CPG_MOD 310>,
478 clock-names = "sci_ick"; 634 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
635 <&scif_clk>;
636 clock-names = "fck", "brg_int", "scif_clk";
479 dmas = <&dmac1 0x13>, <&dmac1 0x12>; 637 dmas = <&dmac1 0x13>, <&dmac1 0x12>;
480 dma-names = "tx", "rx"; 638 dma-names = "tx", "rx";
481 power-domains = <&cpg>; 639 power-domains = <&cpg>;
@@ -483,11 +641,14 @@
483 }; 641 };
484 642
485 scif3: serial@e6c50000 { 643 scif3: serial@e6c50000 {
486 compatible = "renesas,scif-r8a7795", "renesas,scif"; 644 compatible = "renesas,scif-r8a7795",
645 "renesas,rcar-gen3-scif", "renesas,scif";
487 reg = <0 0xe6c50000 0 64>; 646 reg = <0 0xe6c50000 0 64>;
488 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 647 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&cpg CPG_MOD 204>; 648 clocks = <&cpg CPG_MOD 204>,
490 clock-names = "sci_ick"; 649 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
650 <&scif_clk>;
651 clock-names = "fck", "brg_int", "scif_clk";
491 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 652 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
492 dma-names = "tx", "rx"; 653 dma-names = "tx", "rx";
493 power-domains = <&cpg>; 654 power-domains = <&cpg>;
@@ -495,11 +656,14 @@
495 }; 656 };
496 657
497 scif4: serial@e6c40000 { 658 scif4: serial@e6c40000 {
498 compatible = "renesas,scif-r8a7795", "renesas,scif"; 659 compatible = "renesas,scif-r8a7795",
660 "renesas,rcar-gen3-scif", "renesas,scif";
499 reg = <0 0xe6c40000 0 64>; 661 reg = <0 0xe6c40000 0 64>;
500 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 662 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&cpg CPG_MOD 203>; 663 clocks = <&cpg CPG_MOD 203>,
502 clock-names = "sci_ick"; 664 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
665 <&scif_clk>;
666 clock-names = "fck", "brg_int", "scif_clk";
503 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 667 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
504 dma-names = "tx", "rx"; 668 dma-names = "tx", "rx";
505 power-domains = <&cpg>; 669 power-domains = <&cpg>;
@@ -507,11 +671,14 @@
507 }; 671 };
508 672
509 scif5: serial@e6f30000 { 673 scif5: serial@e6f30000 {
510 compatible = "renesas,scif-r8a7795", "renesas,scif"; 674 compatible = "renesas,scif-r8a7795",
675 "renesas,rcar-gen3-scif", "renesas,scif";
511 reg = <0 0xe6f30000 0 64>; 676 reg = <0 0xe6f30000 0 64>;
512 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 677 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&cpg CPG_MOD 202>; 678 clocks = <&cpg CPG_MOD 202>,
514 clock-names = "sci_ick"; 679 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
680 <&scif_clk>;
681 clock-names = "fck", "brg_int", "scif_clk";
515 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>; 682 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>;
516 dma-names = "tx", "rx"; 683 dma-names = "tx", "rx";
517 power-domains = <&cpg>; 684 power-domains = <&cpg>;
@@ -663,52 +830,52 @@
663 830
664 rcar_sound,src { 831 rcar_sound,src {
665 src0: src@0 { 832 src0: src@0 {
666 interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; 833 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
667 dmas = <&audma0 0x85>, <&audma1 0x9a>; 834 dmas = <&audma0 0x85>, <&audma1 0x9a>;
668 dma-names = "rx", "tx"; 835 dma-names = "rx", "tx";
669 }; 836 };
670 src1: src@1 { 837 src1: src@1 {
671 interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; 838 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
672 dmas = <&audma0 0x87>, <&audma1 0x9c>; 839 dmas = <&audma0 0x87>, <&audma1 0x9c>;
673 dma-names = "rx", "tx"; 840 dma-names = "rx", "tx";
674 }; 841 };
675 src2: src@2 { 842 src2: src@2 {
676 interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; 843 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
677 dmas = <&audma0 0x89>, <&audma1 0x9e>; 844 dmas = <&audma0 0x89>, <&audma1 0x9e>;
678 dma-names = "rx", "tx"; 845 dma-names = "rx", "tx";
679 }; 846 };
680 src3: src@3 { 847 src3: src@3 {
681 interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; 848 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
682 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 849 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
683 dma-names = "rx", "tx"; 850 dma-names = "rx", "tx";
684 }; 851 };
685 src4: src@4 { 852 src4: src@4 {
686 interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; 853 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
687 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 854 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
688 dma-names = "rx", "tx"; 855 dma-names = "rx", "tx";
689 }; 856 };
690 src5: src@5 { 857 src5: src@5 {
691 interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; 858 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
692 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 859 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
693 dma-names = "rx", "tx"; 860 dma-names = "rx", "tx";
694 }; 861 };
695 src6: src@6 { 862 src6: src@6 {
696 interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; 863 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
697 dmas = <&audma0 0x91>, <&audma1 0xb4>; 864 dmas = <&audma0 0x91>, <&audma1 0xb4>;
698 dma-names = "rx", "tx"; 865 dma-names = "rx", "tx";
699 }; 866 };
700 src7: src@7 { 867 src7: src@7 {
701 interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; 868 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
702 dmas = <&audma0 0x93>, <&audma1 0xb6>; 869 dmas = <&audma0 0x93>, <&audma1 0xb6>;
703 dma-names = "rx", "tx"; 870 dma-names = "rx", "tx";
704 }; 871 };
705 src8: src@8 { 872 src8: src@8 {
706 interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; 873 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
707 dmas = <&audma0 0x95>, <&audma1 0xb8>; 874 dmas = <&audma0 0x95>, <&audma1 0xb8>;
708 dma-names = "rx", "tx"; 875 dma-names = "rx", "tx";
709 }; 876 };
710 src9: src@9 { 877 src9: src@9 {
711 interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; 878 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
712 dmas = <&audma0 0x97>, <&audma1 0xba>; 879 dmas = <&audma0 0x97>, <&audma1 0xba>;
713 dma-names = "rx", "tx"; 880 dma-names = "rx", "tx";
714 }; 881 };
@@ -716,52 +883,52 @@
716 883
717 rcar_sound,ssi { 884 rcar_sound,ssi {
718 ssi0: ssi@0 { 885 ssi0: ssi@0 {
719 interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; 886 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
720 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; 887 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
721 dma-names = "rx", "tx", "rxu", "txu"; 888 dma-names = "rx", "tx", "rxu", "txu";
722 }; 889 };
723 ssi1: ssi@1 { 890 ssi1: ssi@1 {
724 interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; 891 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
725 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; 892 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
726 dma-names = "rx", "tx", "rxu", "txu"; 893 dma-names = "rx", "tx", "rxu", "txu";
727 }; 894 };
728 ssi2: ssi@2 { 895 ssi2: ssi@2 {
729 interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; 896 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
730 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; 897 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
731 dma-names = "rx", "tx", "rxu", "txu"; 898 dma-names = "rx", "tx", "rxu", "txu";
732 }; 899 };
733 ssi3: ssi@3 { 900 ssi3: ssi@3 {
734 interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; 901 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
735 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; 902 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
736 dma-names = "rx", "tx", "rxu", "txu"; 903 dma-names = "rx", "tx", "rxu", "txu";
737 }; 904 };
738 ssi4: ssi@4 { 905 ssi4: ssi@4 {
739 interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; 906 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
740 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; 907 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
741 dma-names = "rx", "tx", "rxu", "txu"; 908 dma-names = "rx", "tx", "rxu", "txu";
742 }; 909 };
743 ssi5: ssi@5 { 910 ssi5: ssi@5 {
744 interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; 911 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
745 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; 912 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
746 dma-names = "rx", "tx", "rxu", "txu"; 913 dma-names = "rx", "tx", "rxu", "txu";
747 }; 914 };
748 ssi6: ssi@6 { 915 ssi6: ssi@6 {
749 interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; 916 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
750 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; 917 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
751 dma-names = "rx", "tx", "rxu", "txu"; 918 dma-names = "rx", "tx", "rxu", "txu";
752 }; 919 };
753 ssi7: ssi@7 { 920 ssi7: ssi@7 {
754 interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; 921 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
755 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; 922 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
756 dma-names = "rx", "tx", "rxu", "txu"; 923 dma-names = "rx", "tx", "rxu", "txu";
757 }; 924 };
758 ssi8: ssi@8 { 925 ssi8: ssi@8 {
759 interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; 926 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
760 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; 927 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
761 dma-names = "rx", "tx", "rxu", "txu"; 928 dma-names = "rx", "tx", "rxu", "txu";
762 }; 929 };
763 ssi9: ssi@9 { 930 ssi9: ssi@9 {
764 interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; 931 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
765 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; 932 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
766 dma-names = "rx", "tx", "rxu", "txu"; 933 dma-names = "rx", "tx", "rxu", "txu";
767 }; 934 };
@@ -775,5 +942,181 @@
775 clocks = <&cpg CPG_MOD 815>; 942 clocks = <&cpg CPG_MOD 815>;
776 status = "disabled"; 943 status = "disabled";
777 }; 944 };
945
946 xhci0: usb@ee000000 {
947 compatible = "renesas,xhci-r8a7795";
948 reg = <0 0xee000000 0 0xc00>;
949 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&cpg CPG_MOD 328>;
951 power-domains = <&cpg>;
952 status = "disabled";
953 };
954
955 xhci1: usb@ee0400000 {
956 compatible = "renesas,xhci-r8a7795";
957 reg = <0 0xee040000 0 0xc00>;
958 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
959 clocks = <&cpg CPG_MOD 327>;
960 power-domains = <&cpg>;
961 status = "disabled";
962 };
963
964 usb_dmac0: dma-controller@e65a0000 {
965 compatible = "renesas,r8a7795-usb-dmac",
966 "renesas,usb-dmac";
967 reg = <0 0xe65a0000 0 0x100>;
968 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
969 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
970 interrupt-names = "ch0", "ch1";
971 clocks = <&cpg CPG_MOD 330>;
972 power-domains = <&cpg>;
973 #dma-cells = <1>;
974 dma-channels = <2>;
975 };
976
977 usb_dmac1: dma-controller@e65b0000 {
978 compatible = "renesas,r8a7795-usb-dmac",
979 "renesas,usb-dmac";
980 reg = <0 0xe65b0000 0 0x100>;
981 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
982 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
983 interrupt-names = "ch0", "ch1";
984 clocks = <&cpg CPG_MOD 331>;
985 power-domains = <&cpg>;
986 #dma-cells = <1>;
987 dma-channels = <2>;
988 };
989
990 sdhi0: sd@ee100000 {
991 compatible = "renesas,sdhi-r8a7795";
992 reg = <0 0xee100000 0 0x2000>;
993 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&cpg CPG_MOD 314>;
995 power-domains = <&cpg>;
996 status = "disabled";
997 };
998
999 sdhi1: sd@ee120000 {
1000 compatible = "renesas,sdhi-r8a7795";
1001 reg = <0 0xee120000 0 0x2000>;
1002 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1003 clocks = <&cpg CPG_MOD 313>;
1004 power-domains = <&cpg>;
1005 status = "disabled";
1006 };
1007
1008 sdhi2: sd@ee140000 {
1009 compatible = "renesas,sdhi-r8a7795";
1010 reg = <0 0xee140000 0 0x2000>;
1011 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1012 clocks = <&cpg CPG_MOD 312>;
1013 power-domains = <&cpg>;
1014 cap-mmc-highspeed;
1015 status = "disabled";
1016 };
1017
1018 sdhi3: sd@ee160000 {
1019 compatible = "renesas,sdhi-r8a7795";
1020 reg = <0 0xee160000 0 0x2000>;
1021 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1022 clocks = <&cpg CPG_MOD 311>;
1023 power-domains = <&cpg>;
1024 cap-mmc-highspeed;
1025 status = "disabled";
1026 };
1027
1028 usb2_phy0: usb-phy@ee080200 {
1029 compatible = "renesas,usb2-phy-r8a7795";
1030 reg = <0 0xee080200 0 0x700>;
1031 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1032 clocks = <&cpg CPG_MOD 703>;
1033 power-domains = <&cpg>;
1034 #phy-cells = <0>;
1035 status = "disabled";
1036 };
1037
1038 usb2_phy1: usb-phy@ee0a0200 {
1039 compatible = "renesas,usb2-phy-r8a7795";
1040 reg = <0 0xee0a0200 0 0x700>;
1041 clocks = <&cpg CPG_MOD 702>;
1042 power-domains = <&cpg>;
1043 #phy-cells = <0>;
1044 status = "disabled";
1045 };
1046
1047 usb2_phy2: usb-phy@ee0c0200 {
1048 compatible = "renesas,usb2-phy-r8a7795";
1049 reg = <0 0xee0c0200 0 0x700>;
1050 clocks = <&cpg CPG_MOD 701>;
1051 power-domains = <&cpg>;
1052 #phy-cells = <0>;
1053 status = "disabled";
1054 };
1055
1056 ehci0: usb@ee080100 {
1057 compatible = "generic-ehci";
1058 reg = <0 0xee080100 0 0x100>;
1059 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1060 clocks = <&cpg CPG_MOD 703>;
1061 phys = <&usb2_phy0>;
1062 phy-names = "usb";
1063 power-domains = <&cpg>;
1064 status = "disabled";
1065 };
1066
1067 ehci1: usb@ee0a0100 {
1068 compatible = "generic-ehci";
1069 reg = <0 0xee0a0100 0 0x100>;
1070 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1071 clocks = <&cpg CPG_MOD 702>;
1072 phys = <&usb2_phy1>;
1073 phy-names = "usb";
1074 power-domains = <&cpg>;
1075 status = "disabled";
1076 };
1077
1078 ehci2: usb@ee0c0100 {
1079 compatible = "generic-ehci";
1080 reg = <0 0xee0c0100 0 0x100>;
1081 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1082 clocks = <&cpg CPG_MOD 701>;
1083 phys = <&usb2_phy2>;
1084 phy-names = "usb";
1085 power-domains = <&cpg>;
1086 status = "disabled";
1087 };
1088
1089 ohci0: usb@ee080000 {
1090 compatible = "generic-ohci";
1091 reg = <0 0xee080000 0 0x100>;
1092 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1093 clocks = <&cpg CPG_MOD 703>;
1094 phys = <&usb2_phy0>;
1095 phy-names = "usb";
1096 power-domains = <&cpg>;
1097 status = "disabled";
1098 };
1099
1100 ohci1: usb@ee0a0000 {
1101 compatible = "generic-ohci";
1102 reg = <0 0xee0a0000 0 0x100>;
1103 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1104 clocks = <&cpg CPG_MOD 702>;
1105 phys = <&usb2_phy1>;
1106 phy-names = "usb";
1107 power-domains = <&cpg>;
1108 status = "disabled";
1109 };
1110
1111 ohci2: usb@ee0c0000 {
1112 compatible = "generic-ohci";
1113 reg = <0 0xee0c0000 0 0x100>;
1114 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1115 clocks = <&cpg CPG_MOD 701>;
1116 phys = <&usb2_phy2>;
1117 phy-names = "usb";
1118 power-domains = <&cpg>;
1119 status = "disabled";
1120 };
778 }; 1121 };
779}; 1122};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
index 8c219ccf67a3..6e27b22704df 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
@@ -111,7 +111,7 @@
111 pinctrl-0 = <&pwr_key>; 111 pinctrl-0 = <&pwr_key>;
112 112
113 button@0 { 113 button@0 {
114 gpio-key,wakeup = <1>; 114 wakeup-source;
115 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; 115 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
116 label = "GPIO Power"; 116 label = "GPIO Power";
117 linux,code = <116>; 117 linux,code = <116>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
index 104cbee762bb..1f2b642e794a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
@@ -71,7 +71,7 @@
71 pinctrl-0 = <&pwr_key>; 71 pinctrl-0 = <&pwr_key>;
72 72
73 button@0 { 73 button@0 {
74 gpio-key,wakeup = <1>; 74 wakeup-source;
75 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; 75 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
76 label = "GPIO Power"; 76 label = "GPIO Power";
77 linux,code = <116>; 77 linux,code = <116>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 122777b1441e..49d119103e31 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -231,8 +231,9 @@
231 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 231 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
232 reg = <0x0 0xff0c0000 0x0 0x4000>; 232 reg = <0x0 0xff0c0000 0x0 0x4000>;
233 clock-freq-min-max = <400000 150000000>; 233 clock-freq-min-max = <400000 150000000>;
234 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 234 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
235 clock-names = "biu", "ciu"; 235 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
236 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
236 fifo-depth = <0x100>; 237 fifo-depth = <0x100>;
237 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 238 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
238 status = "disabled"; 239 status = "disabled";
@@ -254,8 +255,9 @@
254 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 255 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
255 reg = <0x0 0xff0f0000 0x0 0x4000>; 256 reg = <0x0 0xff0f0000 0x0 0x4000>;
256 clock-freq-min-max = <400000 150000000>; 257 clock-freq-min-max = <400000 150000000>;
257 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 258 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
258 clock-names = "biu", "ciu"; 259 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
260 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
259 fifo-depth = <0x100>; 261 fifo-depth = <0x100>;
260 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 262 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
261 status = "disabled"; 263 status = "disabled";
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi
new file mode 100644
index 000000000000..cdc6a437dcc7
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi
@@ -0,0 +1,88 @@
1/*
2 * clock specification for Xilinx ZynqMP ep108 development board
3 *
4 * (C) Copyright 2015, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 */
13
14&amba {
15 misc_clk: misc_clk {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <25000000>;
19 };
20
21 i2c_clk: i2c_clk {
22 compatible = "fixed-clock";
23 #clock-cells = <0x0>;
24 clock-frequency = <111111111>;
25 };
26
27 sata_clk: sata_clk {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <75000000>;
31 };
32};
33
34&can0 {
35 clocks = <&misc_clk &misc_clk>;
36};
37
38&gem0 {
39 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
40};
41
42&gpio {
43 clocks = <&misc_clk>;
44};
45
46&i2c0 {
47 clocks = <&i2c_clk>;
48};
49
50&i2c1 {
51 clocks = <&i2c_clk>;
52};
53
54&sata {
55 clocks = <&sata_clk>;
56};
57
58&sdhci0 {
59 clocks = <&misc_clk>, <&misc_clk>;
60};
61
62&sdhci1 {
63 clocks = <&misc_clk>, <&misc_clk>;
64};
65
66&spi0 {
67 clocks = <&misc_clk &misc_clk>;
68};
69
70&spi1 {
71 clocks = <&misc_clk &misc_clk>;
72};
73
74&uart0 {
75 clocks = <&misc_clk &misc_clk>;
76};
77
78&usb0 {
79 clocks = <&misc_clk>, <&misc_clk>;
80};
81
82&usb1 {
83 clocks = <&misc_clk>, <&misc_clk>;
84};
85
86&watchdog0 {
87 clocks= <&misc_clk>;
88};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
index ce5d848251fa..acb0527fdc4a 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
@@ -14,6 +14,7 @@
14/dts-v1/; 14/dts-v1/;
15 15
16/include/ "zynqmp.dtsi" 16/include/ "zynqmp.dtsi"
17/include/ "zynqmp-ep108-clk.dtsi"
17 18
18/ { 19/ {
19 model = "ZynqMP EP108"; 20 model = "ZynqMP EP108";
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 200fb588d0f5..e595f22e7e4b 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -90,7 +90,7 @@
90 }; 90 };
91 }; 91 };
92 92
93 amba { 93 amba: amba {
94 compatible = "simple-bus"; 94 compatible = "simple-bus";
95 #address-cells = <2>; 95 #address-cells = <2>;
96 #size-cells = <1>; 96 #size-cells = <1>;
@@ -99,7 +99,6 @@
99 can0: can@ff060000 { 99 can0: can@ff060000 {
100 compatible = "xlnx,zynq-can-1.0"; 100 compatible = "xlnx,zynq-can-1.0";
101 status = "disabled"; 101 status = "disabled";
102 clocks = <&misc_clk &misc_clk>;
103 clock-names = "can_clk", "pclk"; 102 clock-names = "can_clk", "pclk";
104 reg = <0x0 0xff060000 0x1000>; 103 reg = <0x0 0xff060000 0x1000>;
105 interrupts = <0 23 4>; 104 interrupts = <0 23 4>;
@@ -111,7 +110,6 @@
111 can1: can@ff070000 { 110 can1: can@ff070000 {
112 compatible = "xlnx,zynq-can-1.0"; 111 compatible = "xlnx,zynq-can-1.0";
113 status = "disabled"; 112 status = "disabled";
114 clocks = <&misc_clk &misc_clk>;
115 clock-names = "can_clk", "pclk"; 113 clock-names = "can_clk", "pclk";
116 reg = <0x0 0xff070000 0x1000>; 114 reg = <0x0 0xff070000 0x1000>;
117 interrupts = <0 24 4>; 115 interrupts = <0 24 4>;
@@ -120,24 +118,6 @@
120 rx-fifo-depth = <0x40>; 118 rx-fifo-depth = <0x40>;
121 }; 119 };
122 120
123 misc_clk: misc_clk {
124 compatible = "fixed-clock";
125 #clock-cells = <0>;
126 clock-frequency = <25000000>;
127 };
128
129 gpio: gpio@ff0a0000 {
130 compatible = "xlnx,zynqmp-gpio-1.0";
131 status = "disabled";
132 #gpio-cells = <0x2>;
133 clocks = <&misc_clk>;
134 interrupt-parent = <&gic>;
135 interrupts = <0 16 4>;
136 interrupt-controller;
137 #interrupt-cells = <2>;
138 reg = <0x0 0xff0a0000 0x1000>;
139 };
140
141 gem0: ethernet@ff0b0000 { 121 gem0: ethernet@ff0b0000 {
142 compatible = "cdns,gem"; 122 compatible = "cdns,gem";
143 status = "disabled"; 123 status = "disabled";
@@ -145,7 +125,6 @@
145 interrupts = <0 57 4>, <0 57 4>; 125 interrupts = <0 57 4>, <0 57 4>;
146 reg = <0x0 0xff0b0000 0x1000>; 126 reg = <0x0 0xff0b0000 0x1000>;
147 clock-names = "pclk", "hclk", "tx_clk"; 127 clock-names = "pclk", "hclk", "tx_clk";
148 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
149 #address-cells = <1>; 128 #address-cells = <1>;
150 #size-cells = <0>; 129 #size-cells = <0>;
151 }; 130 };
@@ -157,7 +136,6 @@
157 interrupts = <0 59 4>, <0 59 4>; 136 interrupts = <0 59 4>, <0 59 4>;
158 reg = <0x0 0xff0c0000 0x1000>; 137 reg = <0x0 0xff0c0000 0x1000>;
159 clock-names = "pclk", "hclk", "tx_clk"; 138 clock-names = "pclk", "hclk", "tx_clk";
160 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
161 #address-cells = <1>; 139 #address-cells = <1>;
162 #size-cells = <0>; 140 #size-cells = <0>;
163 }; 141 };
@@ -169,7 +147,6 @@
169 interrupts = <0 61 4>, <0 61 4>; 147 interrupts = <0 61 4>, <0 61 4>;
170 reg = <0x0 0xff0d0000 0x1000>; 148 reg = <0x0 0xff0d0000 0x1000>;
171 clock-names = "pclk", "hclk", "tx_clk"; 149 clock-names = "pclk", "hclk", "tx_clk";
172 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
173 #address-cells = <1>; 150 #address-cells = <1>;
174 #size-cells = <0>; 151 #size-cells = <0>;
175 }; 152 };
@@ -181,15 +158,19 @@
181 interrupts = <0 63 4>, <0 63 4>; 158 interrupts = <0 63 4>, <0 63 4>;
182 reg = <0x0 0xff0e0000 0x1000>; 159 reg = <0x0 0xff0e0000 0x1000>;
183 clock-names = "pclk", "hclk", "tx_clk"; 160 clock-names = "pclk", "hclk", "tx_clk";
184 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
185 #address-cells = <1>; 161 #address-cells = <1>;
186 #size-cells = <0>; 162 #size-cells = <0>;
187 }; 163 };
188 164
189 i2c_clk: i2c_clk { 165 gpio: gpio@ff0a0000 {
190 compatible = "fixed-clock"; 166 compatible = "xlnx,zynqmp-gpio-1.0";
191 #clock-cells = <0x0>; 167 status = "disabled";
192 clock-frequency = <111111111>; 168 #gpio-cells = <0x2>;
169 interrupt-parent = <&gic>;
170 interrupts = <0 16 4>;
171 interrupt-controller;
172 #interrupt-cells = <2>;
173 reg = <0x0 0xff0a0000 0x1000>;
193 }; 174 };
194 175
195 i2c0: i2c@ff020000 { 176 i2c0: i2c@ff020000 {
@@ -198,7 +179,6 @@
198 interrupt-parent = <&gic>; 179 interrupt-parent = <&gic>;
199 interrupts = <0 17 4>; 180 interrupts = <0 17 4>;
200 reg = <0x0 0xff020000 0x1000>; 181 reg = <0x0 0xff020000 0x1000>;
201 clocks = <&i2c_clk>;
202 #address-cells = <1>; 182 #address-cells = <1>;
203 #size-cells = <0>; 183 #size-cells = <0>;
204 }; 184 };
@@ -209,24 +189,16 @@
209 interrupt-parent = <&gic>; 189 interrupt-parent = <&gic>;
210 interrupts = <0 18 4>; 190 interrupts = <0 18 4>;
211 reg = <0x0 0xff030000 0x1000>; 191 reg = <0x0 0xff030000 0x1000>;
212 clocks = <&i2c_clk>;
213 #address-cells = <1>; 192 #address-cells = <1>;
214 #size-cells = <0>; 193 #size-cells = <0>;
215 }; 194 };
216 195
217 sata_clk: sata_clk {
218 compatible = "fixed-clock";
219 #clock-cells = <0>;
220 clock-frequency = <75000000>;
221 };
222
223 sata: ahci@fd0c0000 { 196 sata: ahci@fd0c0000 {
224 compatible = "ceva,ahci-1v84"; 197 compatible = "ceva,ahci-1v84";
225 status = "disabled"; 198 status = "disabled";
226 reg = <0x0 0xfd0c0000 0x2000>; 199 reg = <0x0 0xfd0c0000 0x2000>;
227 interrupt-parent = <&gic>; 200 interrupt-parent = <&gic>;
228 interrupts = <0 133 4>; 201 interrupts = <0 133 4>;
229 clocks = <&sata_clk>;
230 }; 202 };
231 203
232 sdhci0: sdhci@ff160000 { 204 sdhci0: sdhci@ff160000 {
@@ -236,7 +208,6 @@
236 interrupts = <0 48 4>; 208 interrupts = <0 48 4>;
237 reg = <0x0 0xff160000 0x1000>; 209 reg = <0x0 0xff160000 0x1000>;
238 clock-names = "clk_xin", "clk_ahb"; 210 clock-names = "clk_xin", "clk_ahb";
239 clocks = <&misc_clk>, <&misc_clk>;
240 }; 211 };
241 212
242 sdhci1: sdhci@ff170000 { 213 sdhci1: sdhci@ff170000 {
@@ -246,7 +217,6 @@
246 interrupts = <0 49 4>; 217 interrupts = <0 49 4>;
247 reg = <0x0 0xff170000 0x1000>; 218 reg = <0x0 0xff170000 0x1000>;
248 clock-names = "clk_xin", "clk_ahb"; 219 clock-names = "clk_xin", "clk_ahb";
249 clocks = <&misc_clk>, <&misc_clk>;
250 }; 220 };
251 221
252 smmu: smmu@fd800000 { 222 smmu: smmu@fd800000 {
@@ -268,7 +238,6 @@
268 interrupts = <0 19 4>; 238 interrupts = <0 19 4>;
269 reg = <0x0 0xff040000 0x1000>; 239 reg = <0x0 0xff040000 0x1000>;
270 clock-names = "ref_clk", "pclk"; 240 clock-names = "ref_clk", "pclk";
271 clocks = <&misc_clk &misc_clk>;
272 #address-cells = <1>; 241 #address-cells = <1>;
273 #size-cells = <0>; 242 #size-cells = <0>;
274 }; 243 };
@@ -280,7 +249,6 @@
280 interrupts = <0 20 4>; 249 interrupts = <0 20 4>;
281 reg = <0x0 0xff050000 0x1000>; 250 reg = <0x0 0xff050000 0x1000>;
282 clock-names = "ref_clk", "pclk"; 251 clock-names = "ref_clk", "pclk";
283 clocks = <&misc_clk &misc_clk>;
284 #address-cells = <1>; 252 #address-cells = <1>;
285 #size-cells = <0>; 253 #size-cells = <0>;
286 }; 254 };
@@ -291,7 +259,6 @@
291 interrupt-parent = <&gic>; 259 interrupt-parent = <&gic>;
292 interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 260 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
293 reg = <0x0 0xff110000 0x1000>; 261 reg = <0x0 0xff110000 0x1000>;
294 clocks = <&misc_clk>;
295 timer-width = <32>; 262 timer-width = <32>;
296 }; 263 };
297 264
@@ -301,7 +268,6 @@
301 interrupt-parent = <&gic>; 268 interrupt-parent = <&gic>;
302 interrupts = <0 39 4>, <0 40 4>, <0 41 4>; 269 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
303 reg = <0x0 0xff120000 0x1000>; 270 reg = <0x0 0xff120000 0x1000>;
304 clocks = <&misc_clk>;
305 timer-width = <32>; 271 timer-width = <32>;
306 }; 272 };
307 273
@@ -311,7 +277,6 @@
311 interrupt-parent = <&gic>; 277 interrupt-parent = <&gic>;
312 interrupts = <0 42 4>, <0 43 4>, <0 44 4>; 278 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
313 reg = <0x0 0xff130000 0x1000>; 279 reg = <0x0 0xff130000 0x1000>;
314 clocks = <&misc_clk>;
315 timer-width = <32>; 280 timer-width = <32>;
316 }; 281 };
317 282
@@ -321,7 +286,6 @@
321 interrupt-parent = <&gic>; 286 interrupt-parent = <&gic>;
322 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 287 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
323 reg = <0x0 0xff140000 0x1000>; 288 reg = <0x0 0xff140000 0x1000>;
324 clocks = <&misc_clk>;
325 timer-width = <32>; 289 timer-width = <32>;
326 }; 290 };
327 291
@@ -332,7 +296,6 @@
332 interrupts = <0 21 4>; 296 interrupts = <0 21 4>;
333 reg = <0x0 0xff000000 0x1000>; 297 reg = <0x0 0xff000000 0x1000>;
334 clock-names = "uart_clk", "pclk"; 298 clock-names = "uart_clk", "pclk";
335 clocks = <&misc_clk &misc_clk>;
336 }; 299 };
337 300
338 uart1: serial@ff010000 { 301 uart1: serial@ff010000 {
@@ -342,7 +305,6 @@
342 interrupts = <0 22 4>; 305 interrupts = <0 22 4>;
343 reg = <0x0 0xff010000 0x1000>; 306 reg = <0x0 0xff010000 0x1000>;
344 clock-names = "uart_clk", "pclk"; 307 clock-names = "uart_clk", "pclk";
345 clocks = <&misc_clk &misc_clk>;
346 }; 308 };
347 309
348 usb0: usb@fe200000 { 310 usb0: usb@fe200000 {
@@ -352,7 +314,6 @@
352 interrupts = <0 65 4>; 314 interrupts = <0 65 4>;
353 reg = <0x0 0xfe200000 0x40000>; 315 reg = <0x0 0xfe200000 0x40000>;
354 clock-names = "clk_xin", "clk_ahb"; 316 clock-names = "clk_xin", "clk_ahb";
355 clocks = <&misc_clk>, <&misc_clk>;
356 }; 317 };
357 318
358 usb1: usb@fe300000 { 319 usb1: usb@fe300000 {
@@ -362,13 +323,11 @@
362 interrupts = <0 70 4>; 323 interrupts = <0 70 4>;
363 reg = <0x0 0xfe300000 0x40000>; 324 reg = <0x0 0xfe300000 0x40000>;
364 clock-names = "clk_xin", "clk_ahb"; 325 clock-names = "clk_xin", "clk_ahb";
365 clocks = <&misc_clk>, <&misc_clk>;
366 }; 326 };
367 327
368 watchdog0: watchdog@fd4d0000 { 328 watchdog0: watchdog@fd4d0000 {
369 compatible = "cdns,wdt-r1p2"; 329 compatible = "cdns,wdt-r1p2";
370 status = "disabled"; 330 status = "disabled";
371 clocks= <&misc_clk>;
372 interrupt-parent = <&gic>; 331 interrupt-parent = <&gic>;
373 interrupts = <0 52 1>; 332 interrupts = <0 52 1>;
374 reg = <0x0 0xfd4d0000 0x1000>; 333 reg = <0x0 0xfd4d0000 0x1000>;
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 18ca9fb9e65f..86581f793e39 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -16,7 +16,6 @@ CONFIG_IKCONFIG_PROC=y
16CONFIG_LOG_BUF_SHIFT=14 16CONFIG_LOG_BUF_SHIFT=14
17CONFIG_MEMCG=y 17CONFIG_MEMCG=y
18CONFIG_MEMCG_SWAP=y 18CONFIG_MEMCG_SWAP=y
19CONFIG_MEMCG_KMEM=y
20CONFIG_CGROUP_HUGETLB=y 19CONFIG_CGROUP_HUGETLB=y
21# CONFIG_UTS_NS is not set 20# CONFIG_UTS_NS is not set
22# CONFIG_IPC_NS is not set 21# CONFIG_IPC_NS is not set
@@ -37,15 +36,13 @@ CONFIG_ARCH_EXYNOS7=y
37CONFIG_ARCH_LAYERSCAPE=y 36CONFIG_ARCH_LAYERSCAPE=y
38CONFIG_ARCH_HISI=y 37CONFIG_ARCH_HISI=y
39CONFIG_ARCH_MEDIATEK=y 38CONFIG_ARCH_MEDIATEK=y
39CONFIG_ARCH_QCOM=y
40CONFIG_ARCH_ROCKCHIP=y 40CONFIG_ARCH_ROCKCHIP=y
41CONFIG_ARCH_SEATTLE=y 41CONFIG_ARCH_SEATTLE=y
42CONFIG_ARCH_RENESAS=y 42CONFIG_ARCH_RENESAS=y
43CONFIG_ARCH_R8A7795=y 43CONFIG_ARCH_R8A7795=y
44CONFIG_ARCH_STRATIX10=y 44CONFIG_ARCH_STRATIX10=y
45CONFIG_ARCH_TEGRA=y 45CONFIG_ARCH_TEGRA=y
46CONFIG_ARCH_TEGRA_132_SOC=y
47CONFIG_ARCH_TEGRA_210_SOC=y
48CONFIG_ARCH_QCOM=y
49CONFIG_ARCH_SPRD=y 46CONFIG_ARCH_SPRD=y
50CONFIG_ARCH_THUNDER=y 47CONFIG_ARCH_THUNDER=y
51CONFIG_ARCH_UNIPHIER=y 48CONFIG_ARCH_UNIPHIER=y
@@ -54,14 +51,19 @@ CONFIG_ARCH_XGENE=y
54CONFIG_ARCH_ZYNQMP=y 51CONFIG_ARCH_ZYNQMP=y
55CONFIG_PCI=y 52CONFIG_PCI=y
56CONFIG_PCI_MSI=y 53CONFIG_PCI_MSI=y
54CONFIG_PCI_IOV=y
55CONFIG_PCI_RCAR_GEN2_PCIE=y
57CONFIG_PCI_HOST_GENERIC=y 56CONFIG_PCI_HOST_GENERIC=y
58CONFIG_PCI_XGENE=y 57CONFIG_PCI_XGENE=y
59CONFIG_SMP=y 58CONFIG_PCI_LAYERSCAPE=y
59CONFIG_PCI_HISI=y
60CONFIG_PCIE_QCOM=y
60CONFIG_SCHED_MC=y 61CONFIG_SCHED_MC=y
61CONFIG_PREEMPT=y 62CONFIG_PREEMPT=y
62CONFIG_KSM=y 63CONFIG_KSM=y
63CONFIG_TRANSPARENT_HUGEPAGE=y 64CONFIG_TRANSPARENT_HUGEPAGE=y
64CONFIG_CMA=y 65CONFIG_CMA=y
66CONFIG_XEN=y
65CONFIG_CMDLINE="console=ttyAMA0" 67CONFIG_CMDLINE="console=ttyAMA0"
66# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set 68# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
67CONFIG_COMPAT=y 69CONFIG_COMPAT=y
@@ -100,7 +102,11 @@ CONFIG_PATA_OF_PLATFORM=y
100CONFIG_NETDEVICES=y 102CONFIG_NETDEVICES=y
101CONFIG_TUN=y 103CONFIG_TUN=y
102CONFIG_VIRTIO_NET=y 104CONFIG_VIRTIO_NET=y
105CONFIG_AMD_XGBE=y
103CONFIG_NET_XGENE=y 106CONFIG_NET_XGENE=y
107CONFIG_E1000E=y
108CONFIG_IGB=y
109CONFIG_IGBVF=y
104CONFIG_SKY2=y 110CONFIG_SKY2=y
105CONFIG_RAVB=y 111CONFIG_RAVB=y
106CONFIG_SMC91X=y 112CONFIG_SMC91X=y
@@ -117,25 +123,23 @@ CONFIG_SERIAL_8250_CONSOLE=y
117CONFIG_SERIAL_8250_DW=y 123CONFIG_SERIAL_8250_DW=y
118CONFIG_SERIAL_8250_MT6577=y 124CONFIG_SERIAL_8250_MT6577=y
119CONFIG_SERIAL_8250_UNIPHIER=y 125CONFIG_SERIAL_8250_UNIPHIER=y
126CONFIG_SERIAL_OF_PLATFORM=y
120CONFIG_SERIAL_AMBA_PL011=y 127CONFIG_SERIAL_AMBA_PL011=y
121CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 128CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
122CONFIG_SERIAL_SAMSUNG=y 129CONFIG_SERIAL_SAMSUNG=y
123CONFIG_SERIAL_SAMSUNG_UARTS_4=y
124CONFIG_SERIAL_SAMSUNG_UARTS=4
125CONFIG_SERIAL_SAMSUNG_CONSOLE=y 130CONFIG_SERIAL_SAMSUNG_CONSOLE=y
131CONFIG_SERIAL_TEGRA=y
126CONFIG_SERIAL_SH_SCI=y 132CONFIG_SERIAL_SH_SCI=y
127CONFIG_SERIAL_SH_SCI_NR_UARTS=11 133CONFIG_SERIAL_SH_SCI_NR_UARTS=11
128CONFIG_SERIAL_SH_SCI_CONSOLE=y 134CONFIG_SERIAL_SH_SCI_CONSOLE=y
129CONFIG_SERIAL_TEGRA=y
130CONFIG_SERIAL_MSM=y 135CONFIG_SERIAL_MSM=y
131CONFIG_SERIAL_MSM_CONSOLE=y 136CONFIG_SERIAL_MSM_CONSOLE=y
132CONFIG_SERIAL_OF_PLATFORM=y
133CONFIG_SERIAL_XILINX_PS_UART=y 137CONFIG_SERIAL_XILINX_PS_UART=y
134CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y 138CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
135CONFIG_VIRTIO_CONSOLE=y 139CONFIG_VIRTIO_CONSOLE=y
136# CONFIG_HW_RANDOM is not set 140# CONFIG_HW_RANDOM is not set
137CONFIG_I2C=y
138CONFIG_I2C_QUP=y 141CONFIG_I2C_QUP=y
142CONFIG_I2C_UNIPHIER_F=y
139CONFIG_I2C_RCAR=y 143CONFIG_I2C_RCAR=y
140CONFIG_SPI=y 144CONFIG_SPI=y
141CONFIG_SPI_PL022=y 145CONFIG_SPI_PL022=y
@@ -176,8 +180,6 @@ CONFIG_MMC_SDHCI_PLTFM=y
176CONFIG_MMC_SDHCI_TEGRA=y 180CONFIG_MMC_SDHCI_TEGRA=y
177CONFIG_MMC_SPI=y 181CONFIG_MMC_SPI=y
178CONFIG_MMC_DW=y 182CONFIG_MMC_DW=y
179CONFIG_MMC_DW_IDMAC=y
180CONFIG_MMC_DW_PLTFM=y
181CONFIG_MMC_DW_EXYNOS=y 183CONFIG_MMC_DW_EXYNOS=y
182CONFIG_NEW_LEDS=y 184CONFIG_NEW_LEDS=y
183CONFIG_LEDS_CLASS=y 185CONFIG_LEDS_CLASS=y
@@ -187,28 +189,33 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
187CONFIG_LEDS_TRIGGER_CPU=y 189CONFIG_LEDS_TRIGGER_CPU=y
188CONFIG_RTC_CLASS=y 190CONFIG_RTC_CLASS=y
189CONFIG_RTC_DRV_EFI=y 191CONFIG_RTC_DRV_EFI=y
192CONFIG_RTC_DRV_PL031=y
190CONFIG_RTC_DRV_XGENE=y 193CONFIG_RTC_DRV_XGENE=y
191CONFIG_DMADEVICES=y 194CONFIG_DMADEVICES=y
192CONFIG_RCAR_DMAC=y
193CONFIG_QCOM_BAM_DMA=y 195CONFIG_QCOM_BAM_DMA=y
194CONFIG_TEGRA20_APB_DMA=y 196CONFIG_TEGRA20_APB_DMA=y
197CONFIG_RCAR_DMAC=y
198CONFIG_VFIO=y
199CONFIG_VFIO_PCI=y
195CONFIG_VIRTIO_PCI=y 200CONFIG_VIRTIO_PCI=y
196CONFIG_VIRTIO_BALLOON=y 201CONFIG_VIRTIO_BALLOON=y
197CONFIG_VIRTIO_MMIO=y 202CONFIG_VIRTIO_MMIO=y
203CONFIG_XEN_GNTDEV=y
204CONFIG_XEN_GRANT_DEV_ALLOC=y
198CONFIG_COMMON_CLK_CS2000_CP=y 205CONFIG_COMMON_CLK_CS2000_CP=y
199CONFIG_COMMON_CLK_QCOM=y 206CONFIG_COMMON_CLK_QCOM=y
200CONFIG_MSM_GCC_8916=y 207CONFIG_MSM_GCC_8916=y
201CONFIG_HWSPINLOCK_QCOM=y 208CONFIG_HWSPINLOCK_QCOM=y
202# CONFIG_IOMMU_SUPPORT is not set 209CONFIG_ARM_SMMU=y
203CONFIG_QCOM_SMEM=y 210CONFIG_QCOM_SMEM=y
204CONFIG_QCOM_SMD=y 211CONFIG_QCOM_SMD=y
205CONFIG_QCOM_SMD_RPM=y 212CONFIG_QCOM_SMD_RPM=y
213CONFIG_ARCH_TEGRA_132_SOC=y
214CONFIG_ARCH_TEGRA_210_SOC=y
215CONFIG_HISILICON_IRQ_MBIGEN=y
206CONFIG_PHY_XGENE=y 216CONFIG_PHY_XGENE=y
207CONFIG_EXT2_FS=y 217CONFIG_EXT2_FS=y
208CONFIG_EXT3_FS=y 218CONFIG_EXT3_FS=y
209# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
210# CONFIG_EXT3_FS_XATTR is not set
211CONFIG_EXT4_FS=y
212CONFIG_FANOTIFY=y 219CONFIG_FANOTIFY=y
213CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y 220CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
214CONFIG_QUOTA=y 221CONFIG_QUOTA=y
@@ -239,6 +246,7 @@ CONFIG_LOCKUP_DETECTOR=y
239# CONFIG_FTRACE is not set 246# CONFIG_FTRACE is not set
240CONFIG_MEMTEST=y 247CONFIG_MEMTEST=y
241CONFIG_SECURITY=y 248CONFIG_SECURITY=y
249CONFIG_CRYPTO_ECHAINIV=y
242CONFIG_CRYPTO_ANSI_CPRNG=y 250CONFIG_CRYPTO_ANSI_CPRNG=y
243CONFIG_ARM64_CRYPTO=y 251CONFIG_ARM64_CRYPTO=y
244CONFIG_CRYPTO_SHA1_ARM64_CE=y 252CONFIG_CRYPTO_SHA1_ARM64_CE=y
diff --git a/arch/arm64/include/asm/futex.h b/arch/arm64/include/asm/futex.h
index 007a69fc4f40..5f3ab8c1db55 100644
--- a/arch/arm64/include/asm/futex.h
+++ b/arch/arm64/include/asm/futex.h
@@ -121,6 +121,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
121 return -EFAULT; 121 return -EFAULT;
122 122
123 asm volatile("// futex_atomic_cmpxchg_inatomic\n" 123 asm volatile("// futex_atomic_cmpxchg_inatomic\n"
124ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, CONFIG_ARM64_PAN)
124" prfm pstl1strm, %2\n" 125" prfm pstl1strm, %2\n"
125"1: ldxr %w1, %2\n" 126"1: ldxr %w1, %2\n"
126" sub %w3, %w1, %w4\n" 127" sub %w3, %w1, %w4\n"
@@ -137,6 +138,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
137" .align 3\n" 138" .align 3\n"
138" .quad 1b, 4b, 2b, 4b\n" 139" .quad 1b, 4b, 2b, 4b\n"
139" .popsection\n" 140" .popsection\n"
141ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, CONFIG_ARM64_PAN)
140 : "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp) 142 : "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp)
141 : "r" (oldval), "r" (newval), "Ir" (-EFAULT) 143 : "r" (oldval), "r" (newval), "Ir" (-EFAULT)
142 : "memory"); 144 : "memory");
diff --git a/arch/arm64/include/asm/page.h b/arch/arm64/include/asm/page.h
index 9b2f5a9d019d..ae615b9d9a55 100644
--- a/arch/arm64/include/asm/page.h
+++ b/arch/arm64/include/asm/page.h
@@ -39,6 +39,7 @@
39 39
40#ifndef __ASSEMBLY__ 40#ifndef __ASSEMBLY__
41 41
42#include <linux/personality.h> /* for READ_IMPLIES_EXEC */
42#include <asm/pgtable-types.h> 43#include <asm/pgtable-types.h>
43 44
44extern void __cpu_clear_user_page(void *p, unsigned long user); 45extern void __cpu_clear_user_page(void *p, unsigned long user);
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 2d545d7aa80b..bf464de33f52 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -67,11 +67,11 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
67#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) 67#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
68#define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) 68#define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
69 69
70#define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRnE)) 70#define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
71#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE)) 71#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
72#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_NC)) 72#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
73#define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_WT)) 73#define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
74#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL)) 74#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
75 75
76#define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE)) 76#define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
77#define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL)) 77#define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
@@ -81,7 +81,7 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
81 81
82#define PAGE_KERNEL __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE) 82#define PAGE_KERNEL __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE)
83#define PAGE_KERNEL_RO __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_RDONLY) 83#define PAGE_KERNEL_RO __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_RDONLY)
84#define PAGE_KERNEL_ROX __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_RDONLY) 84#define PAGE_KERNEL_ROX __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_RDONLY)
85#define PAGE_KERNEL_EXEC __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE) 85#define PAGE_KERNEL_EXEC __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE)
86#define PAGE_KERNEL_EXEC_CONT __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_CONT) 86#define PAGE_KERNEL_EXEC_CONT __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_CONT)
87 87
@@ -153,6 +153,7 @@ extern struct page *empty_zero_page;
153#define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 153#define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
154#define pte_exec(pte) (!(pte_val(pte) & PTE_UXN)) 154#define pte_exec(pte) (!(pte_val(pte) & PTE_UXN))
155#define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 155#define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT))
156#define pte_user(pte) (!!(pte_val(pte) & PTE_USER))
156 157
157#ifdef CONFIG_ARM64_HW_AFDBM 158#ifdef CONFIG_ARM64_HW_AFDBM
158#define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 159#define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
@@ -163,8 +164,6 @@ extern struct page *empty_zero_page;
163#define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 164#define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
164 165
165#define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 166#define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
166#define pte_valid_user(pte) \
167 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
168#define pte_valid_not_user(pte) \ 167#define pte_valid_not_user(pte) \
169 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID) 168 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID)
170#define pte_valid_young(pte) \ 169#define pte_valid_young(pte) \
@@ -278,13 +277,13 @@ extern void __sync_icache_dcache(pte_t pteval, unsigned long addr);
278static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 277static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
279 pte_t *ptep, pte_t pte) 278 pte_t *ptep, pte_t pte)
280{ 279{
281 if (pte_valid_user(pte)) { 280 if (pte_valid(pte)) {
282 if (!pte_special(pte) && pte_exec(pte))
283 __sync_icache_dcache(pte, addr);
284 if (pte_sw_dirty(pte) && pte_write(pte)) 281 if (pte_sw_dirty(pte) && pte_write(pte))
285 pte_val(pte) &= ~PTE_RDONLY; 282 pte_val(pte) &= ~PTE_RDONLY;
286 else 283 else
287 pte_val(pte) |= PTE_RDONLY; 284 pte_val(pte) |= PTE_RDONLY;
285 if (pte_user(pte) && pte_exec(pte) && !pte_special(pte))
286 __sync_icache_dcache(pte, addr);
288 } 287 }
289 288
290 /* 289 /*
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index ffe9c2b6431b..917d98108b3f 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -514,9 +514,14 @@ CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
514#endif 514#endif
515 515
516 /* EL2 debug */ 516 /* EL2 debug */
517 mrs x0, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
518 sbfx x0, x0, #8, #4
519 cmp x0, #1
520 b.lt 4f // Skip if no PMU present
517 mrs x0, pmcr_el0 // Disable debug access traps 521 mrs x0, pmcr_el0 // Disable debug access traps
518 ubfx x0, x0, #11, #5 // to EL2 and allow access to 522 ubfx x0, x0, #11, #5 // to EL2 and allow access to
519 msr mdcr_el2, x0 // all PMU counters from EL1 523 msr mdcr_el2, x0 // all PMU counters from EL1
5244:
520 525
521 /* Stage-2 translation */ 526 /* Stage-2 translation */
522 msr vttbr_el2, xzr 527 msr vttbr_el2, xzr
diff --git a/arch/arm64/kernel/image.h b/arch/arm64/kernel/image.h
index bc2abb8b1599..999633bd7294 100644
--- a/arch/arm64/kernel/image.h
+++ b/arch/arm64/kernel/image.h
@@ -65,6 +65,16 @@
65#ifdef CONFIG_EFI 65#ifdef CONFIG_EFI
66 66
67/* 67/*
68 * Prevent the symbol aliases below from being emitted into the kallsyms
69 * table, by forcing them to be absolute symbols (which are conveniently
70 * ignored by scripts/kallsyms) rather than section relative symbols.
71 * The distinction is only relevant for partial linking, and only for symbols
72 * that are defined within a section declaration (which is not the case for
73 * the definitions below) so the resulting values will be identical.
74 */
75#define KALLSYMS_HIDE(sym) ABSOLUTE(sym)
76
77/*
68 * The EFI stub has its own symbol namespace prefixed by __efistub_, to 78 * The EFI stub has its own symbol namespace prefixed by __efistub_, to
69 * isolate it from the kernel proper. The following symbols are legally 79 * isolate it from the kernel proper. The following symbols are legally
70 * accessed by the stub, so provide some aliases to make them accessible. 80 * accessed by the stub, so provide some aliases to make them accessible.
@@ -73,25 +83,25 @@
73 * linked at. The routines below are all implemented in assembler in a 83 * linked at. The routines below are all implemented in assembler in a
74 * position independent manner 84 * position independent manner
75 */ 85 */
76__efistub_memcmp = __pi_memcmp; 86__efistub_memcmp = KALLSYMS_HIDE(__pi_memcmp);
77__efistub_memchr = __pi_memchr; 87__efistub_memchr = KALLSYMS_HIDE(__pi_memchr);
78__efistub_memcpy = __pi_memcpy; 88__efistub_memcpy = KALLSYMS_HIDE(__pi_memcpy);
79__efistub_memmove = __pi_memmove; 89__efistub_memmove = KALLSYMS_HIDE(__pi_memmove);
80__efistub_memset = __pi_memset; 90__efistub_memset = KALLSYMS_HIDE(__pi_memset);
81__efistub_strlen = __pi_strlen; 91__efistub_strlen = KALLSYMS_HIDE(__pi_strlen);
82__efistub_strcmp = __pi_strcmp; 92__efistub_strcmp = KALLSYMS_HIDE(__pi_strcmp);
83__efistub_strncmp = __pi_strncmp; 93__efistub_strncmp = KALLSYMS_HIDE(__pi_strncmp);
84__efistub___flush_dcache_area = __pi___flush_dcache_area; 94__efistub___flush_dcache_area = KALLSYMS_HIDE(__pi___flush_dcache_area);
85 95
86#ifdef CONFIG_KASAN 96#ifdef CONFIG_KASAN
87__efistub___memcpy = __pi_memcpy; 97__efistub___memcpy = KALLSYMS_HIDE(__pi_memcpy);
88__efistub___memmove = __pi_memmove; 98__efistub___memmove = KALLSYMS_HIDE(__pi_memmove);
89__efistub___memset = __pi_memset; 99__efistub___memset = KALLSYMS_HIDE(__pi_memset);
90#endif 100#endif
91 101
92__efistub__text = _text; 102__efistub__text = KALLSYMS_HIDE(_text);
93__efistub__end = _end; 103__efistub__end = KALLSYMS_HIDE(_end);
94__efistub__edata = _edata; 104__efistub__edata = KALLSYMS_HIDE(_edata);
95 105
96#endif 106#endif
97 107
diff --git a/arch/arm64/mm/dump.c b/arch/arm64/mm/dump.c
index 5a22a119a74c..0adbebbc2803 100644
--- a/arch/arm64/mm/dump.c
+++ b/arch/arm64/mm/dump.c
@@ -46,7 +46,7 @@ enum address_markers_idx {
46 PCI_START_NR, 46 PCI_START_NR,
47 PCI_END_NR, 47 PCI_END_NR,
48 MODULES_START_NR, 48 MODULES_START_NR,
49 MODUELS_END_NR, 49 MODULES_END_NR,
50 KERNEL_SPACE_NR, 50 KERNEL_SPACE_NR,
51}; 51};
52 52
diff --git a/arch/arm64/mm/kasan_init.c b/arch/arm64/mm/kasan_init.c
index cf038c7d9fa9..cab7a5be40aa 100644
--- a/arch/arm64/mm/kasan_init.c
+++ b/arch/arm64/mm/kasan_init.c
@@ -120,6 +120,7 @@ static void __init cpu_set_ttbr1(unsigned long ttbr1)
120void __init kasan_init(void) 120void __init kasan_init(void)
121{ 121{
122 struct memblock_region *reg; 122 struct memblock_region *reg;
123 int i;
123 124
124 /* 125 /*
125 * We are going to perform proper setup of shadow memory. 126 * We are going to perform proper setup of shadow memory.
@@ -155,6 +156,14 @@ void __init kasan_init(void)
155 pfn_to_nid(virt_to_pfn(start))); 156 pfn_to_nid(virt_to_pfn(start)));
156 } 157 }
157 158
159 /*
160 * KAsan may reuse the contents of kasan_zero_pte directly, so we
161 * should make sure that it maps the zero page read-only.
162 */
163 for (i = 0; i < PTRS_PER_PTE; i++)
164 set_pte(&kasan_zero_pte[i],
165 pfn_pte(virt_to_pfn(kasan_zero_page), PAGE_KERNEL_RO));
166
158 memset(kasan_zero_page, 0, PAGE_SIZE); 167 memset(kasan_zero_page, 0, PAGE_SIZE);
159 cpu_set_ttbr1(__pa(swapper_pg_dir)); 168 cpu_set_ttbr1(__pa(swapper_pg_dir));
160 flush_tlb_all(); 169 flush_tlb_all();
diff --git a/arch/arm64/mm/pageattr.c b/arch/arm64/mm/pageattr.c
index 3571c7309c5e..0795c3a36d8f 100644
--- a/arch/arm64/mm/pageattr.c
+++ b/arch/arm64/mm/pageattr.c
@@ -14,6 +14,7 @@
14#include <linux/mm.h> 14#include <linux/mm.h>
15#include <linux/module.h> 15#include <linux/module.h>
16#include <linux/sched.h> 16#include <linux/sched.h>
17#include <linux/vmalloc.h>
17 18
18#include <asm/pgtable.h> 19#include <asm/pgtable.h>
19#include <asm/tlbflush.h> 20#include <asm/tlbflush.h>
@@ -44,6 +45,7 @@ static int change_memory_common(unsigned long addr, int numpages,
44 unsigned long end = start + size; 45 unsigned long end = start + size;
45 int ret; 46 int ret;
46 struct page_change_data data; 47 struct page_change_data data;
48 struct vm_struct *area;
47 49
48 if (!PAGE_ALIGNED(addr)) { 50 if (!PAGE_ALIGNED(addr)) {
49 start &= PAGE_MASK; 51 start &= PAGE_MASK;
@@ -51,11 +53,27 @@ static int change_memory_common(unsigned long addr, int numpages,
51 WARN_ON_ONCE(1); 53 WARN_ON_ONCE(1);
52 } 54 }
53 55
54 if (start < MODULES_VADDR || start >= MODULES_END) 56 /*
57 * Kernel VA mappings are always live, and splitting live section
58 * mappings into page mappings may cause TLB conflicts. This means
59 * we have to ensure that changing the permission bits of the range
60 * we are operating on does not result in such splitting.
61 *
62 * Let's restrict ourselves to mappings created by vmalloc (or vmap).
63 * Those are guaranteed to consist entirely of page mappings, and
64 * splitting is never needed.
65 *
66 * So check whether the [addr, addr + size) interval is entirely
67 * covered by precisely one VM area that has the VM_ALLOC flag set.
68 */
69 area = find_vm_area((void *)addr);
70 if (!area ||
71 end > (unsigned long)area->addr + area->size ||
72 !(area->flags & VM_ALLOC))
55 return -EINVAL; 73 return -EINVAL;
56 74
57 if (end < MODULES_VADDR || end >= MODULES_END) 75 if (!numpages)
58 return -EINVAL; 76 return 0;
59 77
60 data.set_mask = set_mask; 78 data.set_mask = set_mask;
61 data.clear_mask = clear_mask; 79 data.clear_mask = clear_mask;
diff --git a/arch/arm64/mm/proc-macros.S b/arch/arm64/mm/proc-macros.S
index 146bd99a7532..e6a30e1268a8 100644
--- a/arch/arm64/mm/proc-macros.S
+++ b/arch/arm64/mm/proc-macros.S
@@ -84,3 +84,15 @@
84 b.lo 9998b 84 b.lo 9998b
85 dsb \domain 85 dsb \domain
86 .endm 86 .endm
87
88/*
89 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
90 */
91 .macro reset_pmuserenr_el0, tmpreg
92 mrs \tmpreg, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
93 sbfx \tmpreg, \tmpreg, #8, #4
94 cmp \tmpreg, #1 // Skip if no PMU present
95 b.lt 9000f
96 msr pmuserenr_el0, xzr // Disable PMU access from EL0
979000:
98 .endm
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index a3d867e723b4..c164d2cb35c0 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -117,7 +117,7 @@ ENTRY(cpu_do_resume)
117 */ 117 */
118 ubfx x11, x11, #1, #1 118 ubfx x11, x11, #1, #1
119 msr oslar_el1, x11 119 msr oslar_el1, x11
120 msr pmuserenr_el0, xzr // Disable PMU access from EL0 120 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
121 mov x0, x12 121 mov x0, x12
122 dsb nsh // Make sure local tlb invalidation completed 122 dsb nsh // Make sure local tlb invalidation completed
123 isb 123 isb
@@ -154,7 +154,7 @@ ENTRY(__cpu_setup)
154 msr cpacr_el1, x0 // Enable FP/ASIMD 154 msr cpacr_el1, x0 // Enable FP/ASIMD
155 mov x0, #1 << 12 // Reset mdscr_el1 and disable 155 mov x0, #1 << 12 // Reset mdscr_el1 and disable
156 msr mdscr_el1, x0 // access to the DCC from EL0 156 msr mdscr_el1, x0 // access to the DCC from EL0
157 msr pmuserenr_el0, xzr // Disable PMU access from EL0 157 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
158 /* 158 /*
159 * Memory region attributes for LPAE: 159 * Memory region attributes for LPAE:
160 * 160 *
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 21:55:07 -0500