1 files changed, 49 insertions, 4 deletions

diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index d5025c69ca81..28bfe6132eb6 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -87,6 +87,15 @@
         .endm
 
 /*
+ * NOP sequence
+ */
+        .macro  nops, num
+        .rept   \num
+        nop
+        .endr
+        .endm
+
+/*
  * Emit an entry into the exception table
  */
         .macro          _asm_extable, from, to
@@ -216,11 +225,26 @@ lr	.req	x30		// link register
         .macro  mmid, rd, rn
         ldr     \rd, [\rn, #MM_CONTEXT_ID]
         .endm
+/*
+ * read_ctr - read CTR_EL0. If the system has mismatched
+ * cache line sizes, provide the system wide safe value
+ * from arm64_ftr_reg_ctrel0.sys_val
+ */
+        .macro  read_ctr, reg
+alternative_if_not ARM64_MISMATCHED_CACHE_LINE_SIZE
+        mrs     \reg, ctr_el0                   // read CTR
+        nop
+alternative_else
+        ldr_l   \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL
+alternative_endif
+        .endm
+
 
 /*
- * dcache_line_size - get the minimum D-cache line size from the CTR register.
+ * raw_dcache_line_size - get the minimum D-cache line size on this CPU
+ * from the CTR register.
  */
-        .macro  dcache_line_size, reg, tmp
+        .macro  raw_dcache_line_size, reg, tmp
         mrs     \tmp, ctr_el0                   // read CTR
         ubfm    \tmp, \tmp, #16, #19            // cache line size encoding
         mov     \reg, #4                        // bytes per word
@@ -228,9 +252,20 @@ lr	.req	x30		// link register
         .endm
 
 /*
- * icache_line_size - get the minimum I-cache line size from the CTR register.
+ * dcache_line_size - get the safe D-cache line size across all CPUs
  */
-        .macro  icache_line_size, reg, tmp
+        .macro  dcache_line_size, reg, tmp
+        read_ctr        \tmp
+        ubfm            \tmp, \tmp, #16, #19    // cache line size encoding
+        mov             \reg, #4                // bytes per word
+        lsl             \reg, \reg, \tmp        // actual cache line size
+        .endm
+
+/*
+ * raw_icache_line_size - get the minimum I-cache line size on this CPU
+ * from the CTR register.
+ */
+        .macro  raw_icache_line_size, reg, tmp
         mrs     \tmp, ctr_el0                   // read CTR
         and     \tmp, \tmp, #0xf                // cache line size encoding
         mov     \reg, #4                        // bytes per word
@@ -238,6 +273,16 @@ lr	.req	x30		// link register
         .endm
 
 /*
+ * icache_line_size - get the safe I-cache line size across all CPUs
+ */
+        .macro  icache_line_size, reg, tmp
+        read_ctr        \tmp
+        and             \tmp, \tmp, #0xf        // cache line size encoding
+        mov             \reg, #4                // bytes per word
+        lsl             \reg, \reg, \tmp        // actual cache line size
+        .endm
+
+/*
  * tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map
  */
         .macro  tcr_set_idmap_t0sz, valreg, tmpreg