diff options
Diffstat (limited to 'arch/arm/mach-s5pv310/include/mach/regs-clock.h')
| -rw-r--r-- | arch/arm/mach-s5pv310/include/mach/regs-clock.h | 59 |
1 files changed, 30 insertions, 29 deletions
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h index 59e3a7e94d80..4013553cd9be 100644 --- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h | |||
| @@ -15,48 +15,49 @@ | |||
| 15 | 15 | ||
| 16 | #include <mach/map.h> | 16 | #include <mach/map.h> |
| 17 | 17 | ||
| 18 | #define S5P_CLKREG(x) (S3C_VA_SYS + (x)) | 18 | #define S5P_CLKREG(x) (S5P_VA_CMU + (x)) |
| 19 | 19 | ||
| 20 | #define S5P_INFORM0 S5P_CLKREG(0x800) | 20 | #define S5P_INFORM0 S5P_CLKREG(0x800) |
| 21 | 21 | ||
| 22 | #define S5P_EPLL_CON0 S5P_CLKREG(0x1C110) | 22 | #define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) |
| 23 | #define S5P_EPLL_CON1 S5P_CLKREG(0x1C114) | 23 | #define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) |
| 24 | #define S5P_VPLL_CON0 S5P_CLKREG(0x1C120) | 24 | #define S5P_VPLL_CON0 S5P_CLKREG(0x0C120) |
| 25 | #define S5P_VPLL_CON1 S5P_CLKREG(0x1C124) | 25 | #define S5P_VPLL_CON1 S5P_CLKREG(0x0C124) |
| 26 | 26 | ||
| 27 | #define S5P_CLKSRC_TOP0 S5P_CLKREG(0x1C210) | 27 | #define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) |
| 28 | #define S5P_CLKSRC_TOP1 S5P_CLKREG(0x1C214) | 28 | #define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) |
| 29 | 29 | ||
| 30 | #define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x1C250) | 30 | #define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250) |
| 31 | 31 | ||
| 32 | #define S5P_CLKDIV_TOP S5P_CLKREG(0x1C510) | 32 | #define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510) |
| 33 | 33 | ||
| 34 | #define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x1C550) | 34 | #define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550) |
| 35 | #define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x1C554) | 35 | #define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554) |
| 36 | #define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x1C558) | 36 | #define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558) |
| 37 | #define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x1C55C) | 37 | #define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C) |
| 38 | #define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x1C560) | 38 | #define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) |
| 39 | #define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x1C564) | 39 | #define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) |
| 40 | 40 | ||
| 41 | #define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x1C950) | 41 | #define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) |
| 42 | 42 | ||
| 43 | #define S5P_CLKSRC_CORE S5P_CLKREG(0x20200) | 43 | #define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) |
| 44 | 44 | ||
| 45 | #define S5P_CLKDIV_CORE0 S5P_CLKREG(0x20500) | 45 | #define S5P_CLKSRC_CORE S5P_CLKREG(0x10200) |
| 46 | #define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500) | ||
| 46 | 47 | ||
| 47 | #define S5P_APLL_LOCK S5P_CLKREG(0x24000) | 48 | #define S5P_APLL_LOCK S5P_CLKREG(0x14000) |
| 48 | #define S5P_MPLL_LOCK S5P_CLKREG(0x24004) | 49 | #define S5P_MPLL_LOCK S5P_CLKREG(0x14004) |
| 49 | #define S5P_APLL_CON0 S5P_CLKREG(0x24100) | 50 | #define S5P_APLL_CON0 S5P_CLKREG(0x14100) |
| 50 | #define S5P_APLL_CON1 S5P_CLKREG(0x24104) | 51 | #define S5P_APLL_CON1 S5P_CLKREG(0x14104) |
| 51 | #define S5P_MPLL_CON0 S5P_CLKREG(0x24108) | 52 | #define S5P_MPLL_CON0 S5P_CLKREG(0x14108) |
| 52 | #define S5P_MPLL_CON1 S5P_CLKREG(0x2410C) | 53 | #define S5P_MPLL_CON1 S5P_CLKREG(0x1410C) |
| 53 | 54 | ||
| 54 | #define S5P_CLKSRC_CPU S5P_CLKREG(0x24200) | 55 | #define S5P_CLKSRC_CPU S5P_CLKREG(0x14200) |
| 55 | #define S5P_CLKMUX_STATCPU S5P_CLKREG(0x24400) | 56 | #define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400) |
| 56 | 57 | ||
| 57 | #define S5P_CLKDIV_CPU S5P_CLKREG(0x24500) | 58 | #define S5P_CLKDIV_CPU S5P_CLKREG(0x14500) |
| 58 | #define S5P_CLKDIV_STATCPU S5P_CLKREG(0x24600) | 59 | #define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600) |
| 59 | 60 | ||
| 60 | #define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x24800) | 61 | #define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) |
| 61 | 62 | ||
| 62 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ | 63 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ |