2 files changed, 47 insertions, 47 deletions
diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
index eb187e0e059b..5f03484584d4 100644
--- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
+++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
@@ -11,18 +11,18 @@
 #include <mach/mv78xx0.h>
-#define CPU_CONTROL             (BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
 #define L2_WRITETHROUGH         0x00020000
-#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE | 0x0108)
+#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
 #define SOFT_RESET_OUT_EN       0x00000004
-#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
+#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
 #define SOFT_RESET              0x00000001
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
-#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_ERR_OFF       0x0000
 #define IRQ_CAUSE_LOW_OFF       0x0004
 #define IRQ_CAUSE_HIGH_OFF      0x0008
@@ -30,7 +30,7 @@
 #define IRQ_MASK_LOW_OFF        0x0010
 #define IRQ_MASK_HIGH_OFF       0x0014
-#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0300)
+#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE + 0x0300)
-#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE | 0x0300)
+#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
 #endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index e807c4c52a0b..a86e79ecfeaf 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -65,47 +65,47 @@
 /*
 * Register Map
 */
-#define DDR_VIRT_BASE           (MV78XX0_REGS_VIRT_BASE | 0x00000)
+#define DDR_VIRT_BASE           (MV78XX0_REGS_VIRT_BASE + 0x00000)
-#define  DDR_WINDOW_CPU0_BASE   (DDR_VIRT_BASE | 0x1500)
+#define  DDR_WINDOW_CPU0_BASE   (DDR_VIRT_BASE + 0x1500)
-#define  DDR_WINDOW_CPU1_BASE   (DDR_VIRT_BASE | 0x1570)
+#define  DDR_WINDOW_CPU1_BASE   (DDR_VIRT_BASE + 0x1570)
-#define DEV_BUS_PHYS_BASE       (MV78XX0_REGS_PHYS_BASE | 0x10000)
+#define DEV_BUS_PHYS_BASE       (MV78XX0_REGS_PHYS_BASE + 0x10000)
-#define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x10000)
+#define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE + 0x10000)
-#define  SAMPLE_AT_RESET_LOW    (DEV_BUS_VIRT_BASE | 0x0030)
+#define  SAMPLE_AT_RESET_LOW    (DEV_BUS_VIRT_BASE + 0x0030)
-#define  SAMPLE_AT_RESET_HIGH   (DEV_BUS_VIRT_BASE | 0x0034)
+#define  SAMPLE_AT_RESET_HIGH   (DEV_BUS_VIRT_BASE + 0x0034)
-#define  GPIO_VIRT_BASE         (DEV_BUS_VIRT_BASE | 0x0100)
+#define  GPIO_VIRT_BASE         (DEV_BUS_VIRT_BASE + 0x0100)
-#define  I2C_0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x1000)
+#define  I2C_0_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x1000)
-#define  I2C_1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x1100)
+#define  I2C_1_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x1100)
-#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2000)
-#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2000)
-#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2100)
-#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2100)
-#define  UART2_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2200)
+#define  UART2_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2200)
-#define  UART2_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2200)
+#define  UART2_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2200)
-#define  UART3_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2300)
+#define  UART3_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2300)
-#define  UART3_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2300)
+#define  UART3_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2300)
-#define GE10_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x30000)
+#define GE10_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x30000)
-#define GE11_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x34000)
+#define GE11_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x34000)
-#define PCIE00_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x40000)
+#define PCIE00_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x40000)
-#define PCIE01_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x44000)
+#define PCIE01_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x44000)
-#define PCIE02_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x48000)
+#define PCIE02_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x48000)
-#define PCIE03_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x4c000)
+#define PCIE03_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x4c000)
-#define USB0_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x50000)
+#define USB0_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x50000)
-#define USB1_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x51000)
+#define USB1_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x51000)
-#define USB2_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x52000)
+#define USB2_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x52000)
-#define GE00_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x70000)
+#define GE00_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x70000)
-#define GE01_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x74000)
+#define GE01_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x74000)
-#define PCIE10_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x80000)
+#define PCIE10_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x80000)
-#define PCIE11_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x84000)
+#define PCIE11_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x84000)
-#define PCIE12_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x88000)
+#define PCIE12_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x88000)
-#define PCIE13_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x8c000)
+#define PCIE13_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x8c000)
-#define SATA_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0xa0000)
+#define SATA_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0xa0000)
 /*
 * Supported devices and revisions.

diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h index eb187e0e059b..5f03484584d4 100644 --- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h +++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
@@ -11,18 +11,18 @@
11		11
12	#include <mach/mv78xx0.h>	12	#include <mach/mv78xx0.h>
13		13
14	#define CPU_CONTROL (BRIDGE_VIRT_BASE \| 0x0104)	14	#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
15	#define L2_WRITETHROUGH 0x00020000	15	#define L2_WRITETHROUGH 0x00020000
16		16
17	#define RSTOUTn_MASK (BRIDGE_VIRT_BASE \| 0x0108)	17	#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
18	#define SOFT_RESET_OUT_EN 0x00000004	18	#define SOFT_RESET_OUT_EN 0x00000004
19		19
20	#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE \| 0x010c)	20	#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
21	#define SOFT_RESET 0x00000001	21	#define SOFT_RESET 0x00000001
22		22
23	#define BRIDGE_INT_TIMER1_CLR (~0x0004)	23	#define BRIDGE_INT_TIMER1_CLR (~0x0004)
24		24
25	#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE \| 0x0200)	25	#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
26	#define IRQ_CAUSE_ERR_OFF 0x0000	26	#define IRQ_CAUSE_ERR_OFF 0x0000
27	#define IRQ_CAUSE_LOW_OFF 0x0004	27	#define IRQ_CAUSE_LOW_OFF 0x0004
28	#define IRQ_CAUSE_HIGH_OFF 0x0008	28	#define IRQ_CAUSE_HIGH_OFF 0x0008
@@ -30,7 +30,7 @@
30	#define IRQ_MASK_LOW_OFF 0x0010	30	#define IRQ_MASK_LOW_OFF 0x0010
31	#define IRQ_MASK_HIGH_OFF 0x0014	31	#define IRQ_MASK_HIGH_OFF 0x0014
32		32
33	#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE \| 0x0300)	33	#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
34	#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE \| 0x0300)	34	#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
35		35
36	#endif	36	#endif


diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index e807c4c52a0b..a86e79ecfeaf 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -65,47 +65,47 @@
65	/*	65	/*
66	* Register Map	66	* Register Map
67	*/	67	*/
68	#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE \| 0x00000)	68	#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000)
69	#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE \| 0x1500)	69	#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE + 0x1500)
70	#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE \| 0x1570)	70	#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE + 0x1570)
71		71
72	#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE \| 0x10000)	72	#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000)
73	#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE \| 0x10000)	73	#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000)
74	#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE \| 0x0030)	74	#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030)
75	#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE \| 0x0034)	75	#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034)
76	#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE \| 0x0100)	76	#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100)
77	#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE \| 0x1000)	77	#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000)
78	#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE \| 0x1100)	78	#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100)
79	#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE \| 0x2000)	79	#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000)
80	#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE \| 0x2000)	80	#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000)
81	#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE \| 0x2100)	81	#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100)
82	#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE \| 0x2100)	82	#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100)
83	#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE \| 0x2200)	83	#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200)
84	#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE \| 0x2200)	84	#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200)
85	#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE \| 0x2300)	85	#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300)
86	#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE \| 0x2300)	86	#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300)
87		87
88	#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE \| 0x30000)	88	#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000)
89	#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE \| 0x34000)	89	#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000)
90		90
91	#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE \| 0x40000)	91	#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000)
92	#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE \| 0x44000)	92	#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000)
93	#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE \| 0x48000)	93	#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000)
94	#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE \| 0x4c000)	94	#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000)
95		95
96	#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE \| 0x50000)	96	#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000)
97	#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE \| 0x51000)	97	#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000)
98	#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE \| 0x52000)	98	#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000)
99		99
100	#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE \| 0x70000)	100	#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000)
101	#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE \| 0x74000)	101	#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000)
102		102
103	#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE \| 0x80000)	103	#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000)
104	#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE \| 0x84000)	104	#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000)
105	#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE \| 0x88000)	105	#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000)
106	#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE \| 0x8c000)	106	#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000)
107		107
108	#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE \| 0xa0000)	108	#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000)
109		109
110	/*	110	/*
111	* Supported devices and revisions.	111	* Supported devices and revisions.