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-rw-r--r--arch/arm/boot/dts/Makefile3
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi5
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts1
-rw-r--r--arch/arm/boot/dts/mmp2-brownstone.dts2
-rw-r--r--arch/arm/boot/dts/mmp2.dtsi29
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts2
-rw-r--r--arch/arm/boot/dts/pxa168-aspenite.dts2
-rw-r--r--arch/arm/boot/dts/pxa168.dtsi27
-rw-r--r--arch/arm/boot/dts/pxa910-dkb.dts2
-rw-r--r--arch/arm/boot/dts/pxa910.dtsi28
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi12
-rw-r--r--arch/arm/boot/dts/socfpga_arria5.dtsi2
-rw-r--r--arch/arm/boot/dts/socfpga_arria5_socdk.dts12
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_socdk.dts15
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_sockit.dts12
-rw-r--r--arch/arm/boot/dts/vf610-cosmic.dts19
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi24
-rw-r--r--arch/arm/boot/dts/zynq-parallella.dts4
18 files changed, 177 insertions, 24 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 38c89cafa1ab..5b31c3f6d8e5 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -164,6 +164,9 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
164dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb 164dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
165dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb 165dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
166dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb 166dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb
167dtb-$(CONFIG_ARCH_MMP) += pxa168-aspenite.dtb \
168 pxa910-dkb.dtb \
169 mmp2-brownstone.dtb
167dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb 170dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
168dtb-$(CONFIG_ARCH_MXC) += \ 171dtb-$(CONFIG_ARCH_MXC) += \
169 imx1-ads.dtb \ 172 imx1-ads.dtb \
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index d68b3c4862bc..51416c7d0625 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -122,9 +122,10 @@
122 interrupts-extended = <&pmc AT91_PMC_LOCKB>; 122 interrupts-extended = <&pmc AT91_PMC_LOCKB>;
123 clocks = <&main>; 123 clocks = <&main>;
124 reg = <1>; 124 reg = <1>;
125 atmel,clk-input-range = <1000000 5000000>; 125 atmel,clk-input-range = <1000000 32000000>;
126 #atmel,pll-clk-output-range-cells = <4>; 126 #atmel,pll-clk-output-range-cells = <4>;
127 atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; 127 atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
128 <190000000 240000000 2 1>;
128 }; 129 };
129 130
130 mck: masterck { 131 mck: masterck {
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 09664fcf5afb..0e13b4b10a92 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -193,7 +193,6 @@
193 i2c0: i2c@80058000 { 193 i2c0: i2c@80058000 {
194 pinctrl-names = "default"; 194 pinctrl-names = "default";
195 pinctrl-0 = <&i2c0_pins_a>; 195 pinctrl-0 = <&i2c0_pins_a>;
196 clock-frequency = <400000>;
197 status = "okay"; 196 status = "okay";
198 197
199 sgtl5000: codec@0a { 198 sgtl5000: codec@0a {
diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/mmp2-brownstone.dts
index 7f70a39459f6..350208c5e1ed 100644
--- a/arch/arm/boot/dts/mmp2-brownstone.dts
+++ b/arch/arm/boot/dts/mmp2-brownstone.dts
@@ -8,7 +8,7 @@
8 */ 8 */
9 9
10/dts-v1/; 10/dts-v1/;
11/include/ "mmp2.dtsi" 11#include "mmp2.dtsi"
12 12
13/ { 13/ {
14 model = "Marvell MMP2 Brownstone Development Board"; 14 model = "Marvell MMP2 Brownstone Development Board";
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
index 4e8b08c628c7..766bbb8495b6 100644
--- a/arch/arm/boot/dts/mmp2.dtsi
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -7,7 +7,8 @@
7 * publishhed by the Free Software Foundation. 7 * publishhed by the Free Software Foundation.
8 */ 8 */
9 9
10/include/ "skeleton.dtsi" 10#include "skeleton.dtsi"
11#include <dt-bindings/clock/marvell,mmp2.h>
11 12
12/ { 13/ {
13 aliases { 14 aliases {
@@ -135,6 +136,8 @@
135 compatible = "mrvl,mmp-uart"; 136 compatible = "mrvl,mmp-uart";
136 reg = <0xd4030000 0x1000>; 137 reg = <0xd4030000 0x1000>;
137 interrupts = <27>; 138 interrupts = <27>;
139 clocks = <&soc_clocks MMP2_CLK_UART0>;
140 resets = <&soc_clocks MMP2_CLK_UART0>;
138 status = "disabled"; 141 status = "disabled";
139 }; 142 };
140 143
@@ -142,6 +145,8 @@
142 compatible = "mrvl,mmp-uart"; 145 compatible = "mrvl,mmp-uart";
143 reg = <0xd4017000 0x1000>; 146 reg = <0xd4017000 0x1000>;
144 interrupts = <28>; 147 interrupts = <28>;
148 clocks = <&soc_clocks MMP2_CLK_UART1>;
149 resets = <&soc_clocks MMP2_CLK_UART1>;
145 status = "disabled"; 150 status = "disabled";
146 }; 151 };
147 152
@@ -149,6 +154,8 @@
149 compatible = "mrvl,mmp-uart"; 154 compatible = "mrvl,mmp-uart";
150 reg = <0xd4018000 0x1000>; 155 reg = <0xd4018000 0x1000>;
151 interrupts = <24>; 156 interrupts = <24>;
157 clocks = <&soc_clocks MMP2_CLK_UART2>;
158 resets = <&soc_clocks MMP2_CLK_UART2>;
152 status = "disabled"; 159 status = "disabled";
153 }; 160 };
154 161
@@ -156,6 +163,8 @@
156 compatible = "mrvl,mmp-uart"; 163 compatible = "mrvl,mmp-uart";
157 reg = <0xd4016000 0x1000>; 164 reg = <0xd4016000 0x1000>;
158 interrupts = <46>; 165 interrupts = <46>;
166 clocks = <&soc_clocks MMP2_CLK_UART3>;
167 resets = <&soc_clocks MMP2_CLK_UART3>;
159 status = "disabled"; 168 status = "disabled";
160 }; 169 };
161 170
@@ -168,6 +177,8 @@
168 #gpio-cells = <2>; 177 #gpio-cells = <2>;
169 interrupts = <49>; 178 interrupts = <49>;
170 interrupt-names = "gpio_mux"; 179 interrupt-names = "gpio_mux";
180 clocks = <&soc_clocks MMP2_CLK_GPIO>;
181 resets = <&soc_clocks MMP2_CLK_GPIO>;
171 interrupt-controller; 182 interrupt-controller;
172 #interrupt-cells = <1>; 183 #interrupt-cells = <1>;
173 ranges; 184 ranges;
@@ -201,6 +212,8 @@
201 compatible = "mrvl,mmp-twsi"; 212 compatible = "mrvl,mmp-twsi";
202 reg = <0xd4011000 0x1000>; 213 reg = <0xd4011000 0x1000>;
203 interrupts = <7>; 214 interrupts = <7>;
215 clocks = <&soc_clocks MMP2_CLK_TWSI0>;
216 resets = <&soc_clocks MMP2_CLK_TWSI0>;
204 #address-cells = <1>; 217 #address-cells = <1>;
205 #size-cells = <0>; 218 #size-cells = <0>;
206 mrvl,i2c-fast-mode; 219 mrvl,i2c-fast-mode;
@@ -211,6 +224,8 @@
211 compatible = "mrvl,mmp-twsi"; 224 compatible = "mrvl,mmp-twsi";
212 reg = <0xd4025000 0x1000>; 225 reg = <0xd4025000 0x1000>;
213 interrupts = <58>; 226 interrupts = <58>;
227 clocks = <&soc_clocks MMP2_CLK_TWSI1>;
228 resets = <&soc_clocks MMP2_CLK_TWSI1>;
214 status = "disabled"; 229 status = "disabled";
215 }; 230 };
216 231
@@ -220,8 +235,20 @@
220 interrupts = <1 0>; 235 interrupts = <1 0>;
221 interrupt-names = "rtc 1Hz", "rtc alarm"; 236 interrupt-names = "rtc 1Hz", "rtc alarm";
222 interrupt-parent = <&intcmux5>; 237 interrupt-parent = <&intcmux5>;
238 clocks = <&soc_clocks MMP2_CLK_RTC>;
239 resets = <&soc_clocks MMP2_CLK_RTC>;
223 status = "disabled"; 240 status = "disabled";
224 }; 241 };
225 }; 242 };
243
244 soc_clocks: clocks{
245 compatible = "marvell,mmp2-clock";
246 reg = <0xd4050000 0x1000>,
247 <0xd4282800 0x400>,
248 <0xd4015000 0x1000>;
249 reg-names = "mpmu", "apmu", "apbc";
250 #clock-cells = <1>;
251 #reset-cells = <1>;
252 };
226 }; 253 };
227}; 254};
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 739fcf29c643..bc82a12d4c2c 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -668,6 +668,8 @@
668 bank-width = <2>; 668 bank-width = <2>;
669 pinctrl-names = "default"; 669 pinctrl-names = "default";
670 pinctrl-0 = <&ethernet_pins>; 670 pinctrl-0 = <&ethernet_pins>;
671 power-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* gpio86 */
672 reset-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio164 */
671 gpmc,device-width = <2>; 673 gpmc,device-width = <2>;
672 gpmc,sync-clk-ps = <0>; 674 gpmc,sync-clk-ps = <0>;
673 gpmc,cs-on-ns = <0>; 675 gpmc,cs-on-ns = <0>;
diff --git a/arch/arm/boot/dts/pxa168-aspenite.dts b/arch/arm/boot/dts/pxa168-aspenite.dts
index e762facb3fa4..0a988b3fb248 100644
--- a/arch/arm/boot/dts/pxa168-aspenite.dts
+++ b/arch/arm/boot/dts/pxa168-aspenite.dts
@@ -8,7 +8,7 @@
8 */ 8 */
9 9
10/dts-v1/; 10/dts-v1/;
11/include/ "pxa168.dtsi" 11#include "pxa168.dtsi"
12 12
13/ { 13/ {
14 model = "Marvell PXA168 Aspenite Development Board"; 14 model = "Marvell PXA168 Aspenite Development Board";
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
index 975dad21ac38..b899e25cbb1b 100644
--- a/arch/arm/boot/dts/pxa168.dtsi
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -7,7 +7,8 @@
7 * publishhed by the Free Software Foundation. 7 * publishhed by the Free Software Foundation.
8 */ 8 */
9 9
10/include/ "skeleton.dtsi" 10#include "skeleton.dtsi"
11#include <dt-bindings/clock/marvell,pxa168.h>
11 12
12/ { 13/ {
13 aliases { 14 aliases {
@@ -59,6 +60,8 @@
59 compatible = "mrvl,mmp-uart"; 60 compatible = "mrvl,mmp-uart";
60 reg = <0xd4017000 0x1000>; 61 reg = <0xd4017000 0x1000>;
61 interrupts = <27>; 62 interrupts = <27>;
63 clocks = <&soc_clocks PXA168_CLK_UART0>;
64 resets = <&soc_clocks PXA168_CLK_UART0>;
62 status = "disabled"; 65 status = "disabled";
63 }; 66 };
64 67
@@ -66,6 +69,8 @@
66 compatible = "mrvl,mmp-uart"; 69 compatible = "mrvl,mmp-uart";
67 reg = <0xd4018000 0x1000>; 70 reg = <0xd4018000 0x1000>;
68 interrupts = <28>; 71 interrupts = <28>;
72 clocks = <&soc_clocks PXA168_CLK_UART1>;
73 resets = <&soc_clocks PXA168_CLK_UART1>;
69 status = "disabled"; 74 status = "disabled";
70 }; 75 };
71 76
@@ -73,6 +78,8 @@
73 compatible = "mrvl,mmp-uart"; 78 compatible = "mrvl,mmp-uart";
74 reg = <0xd4026000 0x1000>; 79 reg = <0xd4026000 0x1000>;
75 interrupts = <29>; 80 interrupts = <29>;
81 clocks = <&soc_clocks PXA168_CLK_UART2>;
82 resets = <&soc_clocks PXA168_CLK_UART2>;
76 status = "disabled"; 83 status = "disabled";
77 }; 84 };
78 85
@@ -84,6 +91,8 @@
84 gpio-controller; 91 gpio-controller;
85 #gpio-cells = <2>; 92 #gpio-cells = <2>;
86 interrupts = <49>; 93 interrupts = <49>;
94 clocks = <&soc_clocks PXA168_CLK_GPIO>;
95 resets = <&soc_clocks PXA168_CLK_GPIO>;
87 interrupt-names = "gpio_mux"; 96 interrupt-names = "gpio_mux";
88 interrupt-controller; 97 interrupt-controller;
89 #interrupt-cells = <1>; 98 #interrupt-cells = <1>;
@@ -110,6 +119,8 @@
110 compatible = "mrvl,mmp-twsi"; 119 compatible = "mrvl,mmp-twsi";
111 reg = <0xd4011000 0x1000>; 120 reg = <0xd4011000 0x1000>;
112 interrupts = <7>; 121 interrupts = <7>;
122 clocks = <&soc_clocks PXA168_CLK_TWSI0>;
123 resets = <&soc_clocks PXA168_CLK_TWSI0>;
113 mrvl,i2c-fast-mode; 124 mrvl,i2c-fast-mode;
114 status = "disabled"; 125 status = "disabled";
115 }; 126 };
@@ -118,6 +129,8 @@
118 compatible = "mrvl,mmp-twsi"; 129 compatible = "mrvl,mmp-twsi";
119 reg = <0xd4025000 0x1000>; 130 reg = <0xd4025000 0x1000>;
120 interrupts = <58>; 131 interrupts = <58>;
132 clocks = <&soc_clocks PXA168_CLK_TWSI1>;
133 resets = <&soc_clocks PXA168_CLK_TWSI1>;
121 status = "disabled"; 134 status = "disabled";
122 }; 135 };
123 136
@@ -126,8 +139,20 @@
126 reg = <0xd4010000 0x1000>; 139 reg = <0xd4010000 0x1000>;
127 interrupts = <5 6>; 140 interrupts = <5 6>;
128 interrupt-names = "rtc 1Hz", "rtc alarm"; 141 interrupt-names = "rtc 1Hz", "rtc alarm";
142 clocks = <&soc_clocks PXA168_CLK_RTC>;
143 resets = <&soc_clocks PXA168_CLK_RTC>;
129 status = "disabled"; 144 status = "disabled";
130 }; 145 };
131 }; 146 };
147
148 soc_clocks: clocks{
149 compatible = "marvell,pxa168-clock";
150 reg = <0xd4050000 0x1000>,
151 <0xd4282800 0x400>,
152 <0xd4015000 0x1000>;
153 reg-names = "mpmu", "apmu", "apbc";
154 #clock-cells = <1>;
155 #reset-cells = <1>;
156 };
132 }; 157 };
133}; 158};
diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts
index 595492aa5053..c82f2810ec73 100644
--- a/arch/arm/boot/dts/pxa910-dkb.dts
+++ b/arch/arm/boot/dts/pxa910-dkb.dts
@@ -8,7 +8,7 @@
8 */ 8 */
9 9
10/dts-v1/; 10/dts-v1/;
11/include/ "pxa910.dtsi" 11#include "pxa910.dtsi"
12 12
13/ { 13/ {
14 model = "Marvell PXA910 DKB Development Board"; 14 model = "Marvell PXA910 DKB Development Board";
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
index 0247c622f580..0868f6729be1 100644
--- a/arch/arm/boot/dts/pxa910.dtsi
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -7,7 +7,8 @@
7 * publishhed by the Free Software Foundation. 7 * publishhed by the Free Software Foundation.
8 */ 8 */
9 9
10/include/ "skeleton.dtsi" 10#include "skeleton.dtsi"
11#include <dt-bindings/clock/marvell,pxa910.h>
11 12
12/ { 13/ {
13 aliases { 14 aliases {
@@ -71,6 +72,8 @@
71 compatible = "mrvl,mmp-uart"; 72 compatible = "mrvl,mmp-uart";
72 reg = <0xd4017000 0x1000>; 73 reg = <0xd4017000 0x1000>;
73 interrupts = <27>; 74 interrupts = <27>;
75 clocks = <&soc_clocks PXA910_CLK_UART0>;
76 resets = <&soc_clocks PXA910_CLK_UART0>;
74 status = "disabled"; 77 status = "disabled";
75 }; 78 };
76 79
@@ -78,6 +81,8 @@
78 compatible = "mrvl,mmp-uart"; 81 compatible = "mrvl,mmp-uart";
79 reg = <0xd4018000 0x1000>; 82 reg = <0xd4018000 0x1000>;
80 interrupts = <28>; 83 interrupts = <28>;
84 clocks = <&soc_clocks PXA910_CLK_UART1>;
85 resets = <&soc_clocks PXA910_CLK_UART1>;
81 status = "disabled"; 86 status = "disabled";
82 }; 87 };
83 88
@@ -85,6 +90,8 @@
85 compatible = "mrvl,mmp-uart"; 90 compatible = "mrvl,mmp-uart";
86 reg = <0xd4036000 0x1000>; 91 reg = <0xd4036000 0x1000>;
87 interrupts = <59>; 92 interrupts = <59>;
93 clocks = <&soc_clocks PXA910_CLK_UART2>;
94 resets = <&soc_clocks PXA910_CLK_UART2>;
88 status = "disabled"; 95 status = "disabled";
89 }; 96 };
90 97
@@ -97,6 +104,8 @@
97 #gpio-cells = <2>; 104 #gpio-cells = <2>;
98 interrupts = <49>; 105 interrupts = <49>;
99 interrupt-names = "gpio_mux"; 106 interrupt-names = "gpio_mux";
107 clocks = <&soc_clocks PXA910_CLK_GPIO>;
108 resets = <&soc_clocks PXA910_CLK_GPIO>;
100 interrupt-controller; 109 interrupt-controller;
101 #interrupt-cells = <1>; 110 #interrupt-cells = <1>;
102 ranges; 111 ranges;
@@ -124,6 +133,8 @@
124 #size-cells = <0>; 133 #size-cells = <0>;
125 reg = <0xd4011000 0x1000>; 134 reg = <0xd4011000 0x1000>;
126 interrupts = <7>; 135 interrupts = <7>;
136 clocks = <&soc_clocks PXA910_CLK_TWSI0>;
137 resets = <&soc_clocks PXA910_CLK_TWSI0>;
127 mrvl,i2c-fast-mode; 138 mrvl,i2c-fast-mode;
128 status = "disabled"; 139 status = "disabled";
129 }; 140 };
@@ -134,6 +145,8 @@
134 #size-cells = <0>; 145 #size-cells = <0>;
135 reg = <0xd4037000 0x1000>; 146 reg = <0xd4037000 0x1000>;
136 interrupts = <54>; 147 interrupts = <54>;
148 clocks = <&soc_clocks PXA910_CLK_TWSI1>;
149 resets = <&soc_clocks PXA910_CLK_TWSI1>;
137 status = "disabled"; 150 status = "disabled";
138 }; 151 };
139 152
@@ -142,8 +155,21 @@
142 reg = <0xd4010000 0x1000>; 155 reg = <0xd4010000 0x1000>;
143 interrupts = <5 6>; 156 interrupts = <5 6>;
144 interrupt-names = "rtc 1Hz", "rtc alarm"; 157 interrupt-names = "rtc 1Hz", "rtc alarm";
158 clocks = <&soc_clocks PXA910_CLK_RTC>;
159 resets = <&soc_clocks PXA910_CLK_RTC>;
145 status = "disabled"; 160 status = "disabled";
146 }; 161 };
147 }; 162 };
163
164 soc_clocks: clocks{
165 compatible = "marvell,pxa910-clock";
166 reg = <0xd4050000 0x1000>,
167 <0xd4282800 0x400>,
168 <0xd4015000 0x1000>,
169 <0xd403b000 0x1000>;
170 reg-names = "mpmu", "apmu", "apbc", "apbcp";
171 #clock-cells = <1>;
172 #reset-cells = <1>;
173 };
148 }; 174 };
149}; 175};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 45fce2cf6fed..4472fd92685c 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -547,7 +547,7 @@
547 status = "disabled"; 547 status = "disabled";
548 }; 548 };
549 549
550 gpio@ff708000 { 550 gpio0: gpio@ff708000 {
551 #address-cells = <1>; 551 #address-cells = <1>;
552 #size-cells = <0>; 552 #size-cells = <0>;
553 compatible = "snps,dw-apb-gpio"; 553 compatible = "snps,dw-apb-gpio";
@@ -555,7 +555,7 @@
555 clocks = <&per_base_clk>; 555 clocks = <&per_base_clk>;
556 status = "disabled"; 556 status = "disabled";
557 557
558 gpio0: gpio-controller@0 { 558 porta: gpio-controller@0 {
559 compatible = "snps,dw-apb-gpio-port"; 559 compatible = "snps,dw-apb-gpio-port";
560 gpio-controller; 560 gpio-controller;
561 #gpio-cells = <2>; 561 #gpio-cells = <2>;
@@ -567,7 +567,7 @@
567 }; 567 };
568 }; 568 };
569 569
570 gpio@ff709000 { 570 gpio1: gpio@ff709000 {
571 #address-cells = <1>; 571 #address-cells = <1>;
572 #size-cells = <0>; 572 #size-cells = <0>;
573 compatible = "snps,dw-apb-gpio"; 573 compatible = "snps,dw-apb-gpio";
@@ -575,7 +575,7 @@
575 clocks = <&per_base_clk>; 575 clocks = <&per_base_clk>;
576 status = "disabled"; 576 status = "disabled";
577 577
578 gpio1: gpio-controller@0 { 578 portb: gpio-controller@0 {
579 compatible = "snps,dw-apb-gpio-port"; 579 compatible = "snps,dw-apb-gpio-port";
580 gpio-controller; 580 gpio-controller;
581 #gpio-cells = <2>; 581 #gpio-cells = <2>;
@@ -587,7 +587,7 @@
587 }; 587 };
588 }; 588 };
589 589
590 gpio@ff70a000 { 590 gpio2: gpio@ff70a000 {
591 #address-cells = <1>; 591 #address-cells = <1>;
592 #size-cells = <0>; 592 #size-cells = <0>;
593 compatible = "snps,dw-apb-gpio"; 593 compatible = "snps,dw-apb-gpio";
@@ -595,7 +595,7 @@
595 clocks = <&per_base_clk>; 595 clocks = <&per_base_clk>;
596 status = "disabled"; 596 status = "disabled";
597 597
598 gpio2: gpio-controller@0 { 598 portc: gpio-controller@0 {
599 compatible = "snps,dw-apb-gpio-port"; 599 compatible = "snps,dw-apb-gpio-port";
600 gpio-controller; 600 gpio-controller;
601 #gpio-cells = <2>; 601 #gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 03e8268ae219..1907cc600452 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -29,7 +29,7 @@
29 }; 29 };
30 }; 30 };
31 31
32 dwmmc0@ff704000 { 32 mmc0: dwmmc0@ff704000 {
33 num-slots = <1>; 33 num-slots = <1>;
34 broken-cd; 34 broken-cd;
35 bus-width = <4>; 35 bus-width = <4>;
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index 27d551c384d0..ccaf41742fc3 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -37,6 +37,13 @@
37 */ 37 */
38 ethernet0 = &gmac1; 38 ethernet0 = &gmac1;
39 }; 39 };
40
41 regulator_3_3v: 3-3-v-regulator {
42 compatible = "regulator-fixed";
43 regulator-name = "3.3V";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 };
40}; 47};
41 48
42&gmac1 { 49&gmac1 {
@@ -68,6 +75,11 @@
68 }; 75 };
69}; 76};
70 77
78&mmc0 {
79 vmmc-supply = <&regulator_3_3v>;
80 vqmmc-supply = <&regulator_3_3v>;
81};
82
71&usb1 { 83&usb1 {
72 status = "okay"; 84 status = "okay";
73}; 85};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index d7296a5f750c..258865da8f6a 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -37,6 +37,13 @@
37 */ 37 */
38 ethernet0 = &gmac1; 38 ethernet0 = &gmac1;
39 }; 39 };
40
41 regulator_3_3v: 3-3-v-regulator {
42 compatible = "regulator-fixed";
43 regulator-name = "3.3V";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 };
40}; 47};
41 48
42&gmac1 { 49&gmac1 {
@@ -53,6 +60,10 @@
53 rxc-skew-ps = <2000>; 60 rxc-skew-ps = <2000>;
54}; 61};
55 62
63&gpio1 {
64 status = "okay";
65};
66
56&i2c0 { 67&i2c0 {
57 status = "okay"; 68 status = "okay";
58 69
@@ -69,7 +80,9 @@
69}; 80};
70 81
71&mmc0 { 82&mmc0 {
72 cd-gpios = <&gpio1 18 0>; 83 cd-gpios = <&portb 18 0>;
84 vmmc-supply = <&regulator_3_3v>;
85 vqmmc-supply = <&regulator_3_3v>;
73}; 86};
74 87
75&usb1 { 88&usb1 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
index d26f155f5fd9..16ea6f5f2ab8 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
@@ -37,6 +37,13 @@
37 */ 37 */
38 ethernet0 = &gmac1; 38 ethernet0 = &gmac1;
39 }; 39 };
40
41 regulator_3_3v: vcc3p3-regulator {
42 compatible = "regulator-fixed";
43 regulator-name = "VCC3P3";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 };
40}; 47};
41 48
42&gmac1 { 49&gmac1 {
@@ -53,6 +60,11 @@
53 rxc-skew-ps = <2000>; 60 rxc-skew-ps = <2000>;
54}; 61};
55 62
63&mmc0 {
64 vmmc-supply = <&regulator_3_3v>;
65 vqmmc-supply = <&regulator_3_3v>;
66};
67
56&usb1 { 68&usb1 {
57 status = "okay"; 69 status = "okay";
58}; 70};
diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts
index 3fd1b74e1216..de1b453c2932 100644
--- a/arch/arm/boot/dts/vf610-cosmic.dts
+++ b/arch/arm/boot/dts/vf610-cosmic.dts
@@ -33,6 +33,13 @@
33 33
34}; 34};
35 35
36&esdhc1 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_esdhc1>;
39 bus-width = <4>;
40 status = "okay";
41};
42
36&fec1 { 43&fec1 {
37 phy-mode = "rmii"; 44 phy-mode = "rmii";
38 pinctrl-names = "default"; 45 pinctrl-names = "default";
@@ -42,6 +49,18 @@
42 49
43&iomuxc { 50&iomuxc {
44 vf610-cosmic { 51 vf610-cosmic {
52 pinctrl_esdhc1: esdhc1grp {
53 fsl,pins = <
54 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
55 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
56 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
57 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
58 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
59 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
60 VF610_PAD_PTB28__GPIO_98 0x219d
61 >;
62 };
63
45 pinctrl_fec1: fec1grp { 64 pinctrl_fec1: fec1grp {
46 fsl,pins = < 65 fsl,pins = <
47 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 66 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 24036c440440..ce2ef5bec4f2 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -30,7 +30,6 @@
30 /* kHz uV */ 30 /* kHz uV */
31 666667 1000000 31 666667 1000000
32 333334 1000000 32 333334 1000000
33 222223 1000000
34 >; 33 >;
35 }; 34 };
36 35
@@ -65,7 +64,7 @@
65 interrupt-parent = <&intc>; 64 interrupt-parent = <&intc>;
66 ranges; 65 ranges;
67 66
68 adc@f8007100 { 67 adc: adc@f8007100 {
69 compatible = "xlnx,zynq-xadc-1.00.a"; 68 compatible = "xlnx,zynq-xadc-1.00.a";
70 reg = <0xf8007100 0x20>; 69 reg = <0xf8007100 0x20>;
71 interrupts = <0 7 4>; 70 interrupts = <0 7 4>;
@@ -137,7 +136,7 @@
137 <0xF8F00100 0x100>; 136 <0xF8F00100 0x100>;
138 }; 137 };
139 138
140 L2: cache-controller { 139 L2: cache-controller@f8f02000 {
141 compatible = "arm,pl310-cache"; 140 compatible = "arm,pl310-cache";
142 reg = <0xF8F02000 0x1000>; 141 reg = <0xF8F02000 0x1000>;
143 arm,data-latency = <3 2 2>; 142 arm,data-latency = <3 2 2>;
@@ -146,10 +145,10 @@
146 cache-level = <2>; 145 cache-level = <2>;
147 }; 146 };
148 147
149 memory-controller@f8006000 { 148 mc: memory-controller@f8006000 {
150 compatible = "xlnx,zynq-ddrc-a05"; 149 compatible = "xlnx,zynq-ddrc-a05";
151 reg = <0xf8006000 0x1000>; 150 reg = <0xf8006000 0x1000>;
152 } ; 151 };
153 152
154 uart0: serial@e0000000 { 153 uart0: serial@e0000000 {
155 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 154 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
@@ -195,7 +194,7 @@
195 194
196 gem0: ethernet@e000b000 { 195 gem0: ethernet@e000b000 {
197 compatible = "cdns,gem"; 196 compatible = "cdns,gem";
198 reg = <0xe000b000 0x4000>; 197 reg = <0xe000b000 0x1000>;
199 status = "disabled"; 198 status = "disabled";
200 interrupts = <0 22 4>; 199 interrupts = <0 22 4>;
201 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 200 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
@@ -206,7 +205,7 @@
206 205
207 gem1: ethernet@e000c000 { 206 gem1: ethernet@e000c000 {
208 compatible = "cdns,gem"; 207 compatible = "cdns,gem";
209 reg = <0xe000c000 0x4000>; 208 reg = <0xe000c000 0x1000>;
210 status = "disabled"; 209 status = "disabled";
211 interrupts = <0 45 4>; 210 interrupts = <0 45 4>;
212 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; 211 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
@@ -315,5 +314,16 @@
315 reg = <0xf8f00600 0x20>; 314 reg = <0xf8f00600 0x20>;
316 clocks = <&clkc 4>; 315 clocks = <&clkc 4>;
317 }; 316 };
317
318 watchdog0: watchdog@f8005000 {
319 clocks = <&clkc 45>;
320 compatible = "xlnx,zynq-wdt-r1p2";
321 device_type = "watchdog";
322 interrupt-parent = <&intc>;
323 interrupts = <0 9 1>;
324 reg = <0xf8005000 0x1000>;
325 reset = <0>;
326 timeout-sec = <10>;
327 };
318 }; 328 };
319}; 329};
diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index e1f51ca127fe..0429bbd89fba 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -34,6 +34,10 @@
34 }; 34 };
35}; 35};
36 36
37&clkc {
38 fclk-enable = <0xf>;
39};
40
37&gem0 { 41&gem0 {
38 status = "okay"; 42 status = "okay";
39 phy-mode = "rgmii-id"; 43 phy-mode = "rgmii-id";
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 23:44:09 -0500