22 files changed, 463 insertions, 175 deletions

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 376366a7db81..d750b302d5ab 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -191,7 +191,6 @@ config NR_CPUS
 
 config ARC_SMP_HALT_ON_RESET
         bool "Enable Halt-on-reset boot mode"
-        default y if ARC_UBOOT_SUPPORT
         help
           In SMP configuration cores can be configured as Halt-on-reset
           or they could all start at same time. For Halt-on-reset, non
@@ -407,6 +406,14 @@ config ARC_HAS_ACCL_REGS
           (also referred to as r58:r59). These can also be used by gcc as GPR so
           kernel needs to save/restore per process
 
+config ARC_IRQ_NO_AUTOSAVE
+        bool "Disable hardware autosave regfile on interrupts"
+        default n
+        help
+          On HS cores, taken interrupt auto saves the regfile on stack.
+          This is programmable and can be optionally disabled in which case
+          software INTERRUPT_PROLOGUE/EPILGUE do the needed work
+
 endif   # ISA_ARCV2
 
 endmenu   # "ARC CPU Configuration"
@@ -515,17 +522,6 @@ config ARC_DBG_TLB_PARANOIA
 
 endif
 
-config ARC_UBOOT_SUPPORT
-        bool "Support uboot arg Handling"
-        help
-          ARC Linux by default checks for uboot provided args as pointers to
-          external cmdline or DTB. This however breaks in absence of uboot,
-          when booting from Metaware debugger directly, as the registers are
-          not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
-          registers look like uboot args to kernel which then chokes.
-          So only enable the uboot arg checking/processing if users are sure
-          of uboot being in play.
-
 config ARC_BUILTIN_DTB_NAME
         string "Built in DTB"
         help
diff --git a/arch/arc/configs/nps_defconfig b/arch/arc/configs/nps_defconfig
index 6e84060e7c90..621f59407d76 100644
--- a/arch/arc/configs/nps_defconfig
+++ b/arch/arc/configs/nps_defconfig
@@ -31,7 +31,6 @@ CONFIG_ARC_CACHE_LINE_SHIFT=5
 # CONFIG_ARC_HAS_LLSC is not set
 CONFIG_ARC_KVADDR_SIZE=402
 CONFIG_ARC_EMUL_UNALIGNED=y
-CONFIG_ARC_UBOOT_SUPPORT=y
 CONFIG_PREEMPT=y
 CONFIG_NET=y
 CONFIG_UNIX=y
diff --git a/arch/arc/configs/vdk_hs38_defconfig b/arch/arc/configs/vdk_hs38_defconfig
index 1e59a2e9c602..e447ace6fa1c 100644
--- a/arch/arc/configs/vdk_hs38_defconfig
+++ b/arch/arc/configs/vdk_hs38_defconfig
@@ -13,7 +13,6 @@ CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARC_PLAT_AXS10X=y
 CONFIG_AXS103=y
 CONFIG_ISA_ARCV2=y
-CONFIG_ARC_UBOOT_SUPPORT=y
 CONFIG_ARC_BUILTIN_DTB_NAME="vdk_hs38"
 CONFIG_PREEMPT=y
 CONFIG_NET=y
diff --git a/arch/arc/configs/vdk_hs38_smp_defconfig b/arch/arc/configs/vdk_hs38_smp_defconfig
index b5c3f6c54b03..c82cdb10aaf4 100644
--- a/arch/arc/configs/vdk_hs38_smp_defconfig
+++ b/arch/arc/configs/vdk_hs38_smp_defconfig
@@ -15,8 +15,6 @@ CONFIG_AXS103=y
 CONFIG_ISA_ARCV2=y
 CONFIG_SMP=y
 # CONFIG_ARC_TIMERS_64BIT is not set
-# CONFIG_ARC_SMP_HALT_ON_RESET is not set
-CONFIG_ARC_UBOOT_SUPPORT=y
 CONFIG_ARC_BUILTIN_DTB_NAME="vdk_hs38_smp"
 CONFIG_PREEMPT=y
 CONFIG_NET=y
diff --git a/arch/arc/include/asm/Kbuild b/arch/arc/include/asm/Kbuild
index feed50ce89fa..caa270261521 100644
--- a/arch/arc/include/asm/Kbuild
+++ b/arch/arc/include/asm/Kbuild
@@ -3,23 +3,19 @@ generic-y += bugs.h
 generic-y += compat.h
 generic-y += device.h
 generic-y += div64.h
-generic-y += dma-mapping.h
 generic-y += emergency-restart.h
 generic-y += extable.h
-generic-y += fb.h
 generic-y += ftrace.h
 generic-y += hardirq.h
 generic-y += hw_irq.h
 generic-y += irq_regs.h
 generic-y += irq_work.h
-generic-y += kmap_types.h
 generic-y += local.h
 generic-y += local64.h
 generic-y += mcs_spinlock.h
 generic-y += mm-arch-hooks.h
 generic-y += msi.h
 generic-y += parport.h
-generic-y += pci.h
 generic-y += percpu.h
 generic-y += preempt.h
 generic-y += topology.h
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 49bfbd879caa..a27eafdc8260 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -151,6 +151,14 @@ struct bcr_isa_arcv2 {
 #endif
 };
 
+struct bcr_uarch_build_arcv2 {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+        unsigned int pad:8, prod:8, maj:8, min:8;
+#else
+        unsigned int min:8, maj:8, prod:8, pad:8;
+#endif
+};
+
 struct bcr_mpy {
 #ifdef CONFIG_CPU_BIG_ENDIAN
         unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
@@ -216,6 +224,14 @@ struct bcr_fp_arcv2 {
 #endif
 };
 
+struct bcr_actionpoint {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+        unsigned int pad:21, min:1, num:2, ver:8;
+#else
+        unsigned int ver:8, num:2, min:1, pad:21;
+#endif
+};
+
 #include <soc/arc/timers.h>
 
 struct bcr_bpu_arcompact {
@@ -283,7 +299,7 @@ struct cpuinfo_arc_cache {
 };
 
 struct cpuinfo_arc_bpu {
-        unsigned int ver, full, num_cache, num_pred;
+        unsigned int ver, full, num_cache, num_pred, ret_stk;
 };
 
 struct cpuinfo_arc_ccm {
@@ -302,7 +318,7 @@ struct cpuinfo_arc {
         struct {
                 unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
                              fpu_sp:1, fpu_dp:1, dual:1, dual_enb:1, pad2:4,
-                             debug:1, ap:1, smart:1, rtt:1, pad3:4,
+                             ap_num:4, ap_full:1, smart:1, rtt:1, pad3:1,
                              timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
         } extn;
         struct bcr_mpy extn_mpy;
diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h
index ee9246184033..202b74c339f0 100644
--- a/arch/arc/include/asm/bitops.h
+++ b/arch/arc/include/asm/bitops.h
@@ -340,7 +340,7 @@ static inline __attribute__ ((const)) int __fls(unsigned long x)
 /*
  * __ffs: Similar to ffs, but zero based (0-31)
  */
-static inline __attribute__ ((const)) int __ffs(unsigned long word)
+static inline __attribute__ ((const)) unsigned long __ffs(unsigned long word)
 {
         if (!word)
                 return word;
@@ -400,9 +400,9 @@ static inline __attribute__ ((const)) int ffs(unsigned long x)
 /*
  * __ffs: Similar to ffs, but zero based (0-31)
  */
-static inline __attribute__ ((const)) int __ffs(unsigned long x)
+static inline __attribute__ ((const)) unsigned long __ffs(unsigned long x)
 {
-        int n;
+        unsigned long n;
 
         asm volatile(
         "       ffs.f   %0, %1          \n"  /* 0:31; 31(Z) if src 0 */
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index f393b663413e..2ad77fb43639 100644
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -52,6 +52,17 @@
 #define cache_line_size()       SMP_CACHE_BYTES
 #define ARCH_DMA_MINALIGN       SMP_CACHE_BYTES
 
+/*
+ * Make sure slab-allocated buffers are 64-bit aligned when atomic64_t uses
+ * ARCv2 64-bit atomics (LLOCKD/SCONDD). This guarantess runtime 64-bit
+ * alignment for any atomic64_t embedded in buffer.
+ * Default ARCH_SLAB_MINALIGN is __alignof__(long long) which has a relaxed
+ * value of 4 (and not 8) in ARC ABI.
+ */
+#if defined(CONFIG_ARC_HAS_LL64) && defined(CONFIG_ARC_HAS_LLSC)
+#define ARCH_SLAB_MINALIGN      8
+#endif
+
 extern void arc_cache_init(void);
 extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
 extern void read_decode_cache_bcr(void);
diff --git a/arch/arc/include/asm/entry-arcv2.h b/arch/arc/include/asm/entry-arcv2.h
index 309f4e6721b3..225e7df2d8ed 100644
--- a/arch/arc/include/asm/entry-arcv2.h
+++ b/arch/arc/include/asm/entry-arcv2.h
@@ -17,6 +17,33 @@
         ;
         ; Now manually save: r12, sp, fp, gp, r25
 
+#ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE
+.ifnc \called_from, exception
+        st.as   r9, [sp, -10]   ; save r9 in it's final stack slot
+        sub     sp, sp, 12      ; skip JLI, LDI, EI
+
+        PUSH    lp_count
+        PUSHAX  lp_start
+        PUSHAX  lp_end
+        PUSH    blink
+
+        PUSH    r11
+        PUSH    r10
+
+        sub     sp, sp, 4       ; skip r9
+
+        PUSH    r8
+        PUSH    r7
+        PUSH    r6
+        PUSH    r5
+        PUSH    r4
+        PUSH    r3
+        PUSH    r2
+        PUSH    r1
+        PUSH    r0
+.endif
+#endif
+
 #ifdef CONFIG_ARC_HAS_ACCL_REGS
         PUSH    r59
         PUSH    r58
@@ -86,6 +113,33 @@
         POP     r59
 #endif
 
+#ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE
+.ifnc \called_from, exception
+        POP     r0
+        POP     r1
+        POP     r2
+        POP     r3
+        POP     r4
+        POP     r5
+        POP     r6
+        POP     r7
+        POP     r8
+        POP     r9
+        POP     r10
+        POP     r11
+
+        POP     blink
+        POPAX   lp_end
+        POPAX   lp_start
+
+        POP     r9
+        mov     lp_count, r9
+
+        add     sp, sp, 12      ; skip JLI, LDI, EI
+        ld.as   r9, [sp, -10]   ; reload r9 which got clobbered
+.endif
+#endif
+
 .endm
 
 /*------------------------------------------------------------------------*/
diff --git a/arch/arc/include/asm/perf_event.h b/arch/arc/include/asm/perf_event.h
index 9185541035cc..6958545390f0 100644
--- a/arch/arc/include/asm/perf_event.h
+++ b/arch/arc/include/asm/perf_event.h
@@ -103,7 +103,8 @@ static const char * const arc_pmu_ev_hw_map[] = {
 
         /* counts condition */
         [PERF_COUNT_HW_INSTRUCTIONS] = "iall",
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmp", /* Excludes ZOL jumps */
+        /* All jump instructions that are taken */
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmptak",
         [PERF_COUNT_ARC_BPOK]         = "bpok",   /* NP-NT, PT-T, PNT-NT */
 #ifdef CONFIG_ISA_ARCV2
         [PERF_COUNT_HW_BRANCH_MISSES] = "bpmp",
diff --git a/arch/arc/include/asm/uaccess.h b/arch/arc/include/asm/uaccess.h
index c9173c02081c..eabc3efa6c6d 100644
--- a/arch/arc/include/asm/uaccess.h
+++ b/arch/arc/include/asm/uaccess.h
@@ -207,7 +207,7 @@ raw_copy_from_user(void *to, const void __user *from, unsigned long n)
                 */
                   "=&r" (tmp), "+r" (to), "+r" (from)
                 :
-                : "lp_count", "lp_start", "lp_end", "memory");
+                : "lp_count", "memory");
 
                 return n;
         }
@@ -433,7 +433,7 @@ raw_copy_to_user(void __user *to, const void *from, unsigned long n)
                  */
                   "=&r" (tmp), "+r" (to), "+r" (from)
                 :
-                : "lp_count", "lp_start", "lp_end", "memory");
+                : "lp_count", "memory");
 
                 return n;
         }
@@ -653,7 +653,7 @@ static inline unsigned long __arc_clear_user(void __user *to, unsigned long n)
         "       .previous                       \n"
         : "+r"(d_char), "+r"(res)
         : "i"(0)
-        : "lp_count", "lp_start", "lp_end", "memory");
+        : "lp_count", "memory");
 
         return res;
 }
@@ -686,7 +686,7 @@ __arc_strncpy_from_user(char *dst, const char __user *src, long count)
         "       .previous                       \n"
         : "+r"(res), "+r"(dst), "+r"(src), "=r"(val)
         : "g"(-EFAULT), "r"(count)
-        : "lp_count", "lp_start", "lp_end", "memory");
+        : "lp_count", "memory");
 
         return res;
 }
diff --git a/arch/arc/kernel/entry-arcv2.S b/arch/arc/kernel/entry-arcv2.S
index cc558a25b8fa..562089d62d9d 100644
--- a/arch/arc/kernel/entry-arcv2.S
+++ b/arch/arc/kernel/entry-arcv2.S
@@ -209,7 +209,9 @@ restore_regs:
 ;####### Return from Intr #######
 
 debug_marker_l1:
-        bbit1.nt r0, STATUS_DE_BIT, .Lintr_ret_to_delay_slot
+        ; bbit1.nt r0, STATUS_DE_BIT, .Lintr_ret_to_delay_slot
+        btst    r0, STATUS_DE_BIT               ; Z flag set if bit clear
+        bnz     .Lintr_ret_to_delay_slot        ; branch if STATUS_DE_BIT set
 
 .Lisr_ret_fast_path:
         ; Handle special case #1: (Entry via Exception, Return via IRQ)
diff --git a/arch/arc/kernel/head.S b/arch/arc/kernel/head.S
index 8b90d25a15cc..30e090625916 100644
--- a/arch/arc/kernel/head.S
+++ b/arch/arc/kernel/head.S
@@ -17,6 +17,7 @@
 #include <asm/entry.h>
 #include <asm/arcregs.h>
 #include <asm/cache.h>
+#include <asm/irqflags.h>
 
 .macro CPU_EARLY_SETUP
 
@@ -47,6 +48,15 @@
         sr      r5, [ARC_REG_DC_CTRL]
 
 1:
+
+#ifdef CONFIG_ISA_ARCV2
+        ; Unaligned access is disabled at reset, so re-enable early as
+        ; gcc 7.3.1 (ARC GNU 2018.03) onwards generates unaligned access
+        ; by default
+        lr      r5, [status32]
+        bset    r5, r5, STATUS_AD_BIT
+        kflag   r5
+#endif
 .endm
 
         .section .init.text, "ax",@progbits
@@ -90,15 +100,13 @@ ENTRY(stext)
         st.ab   0, [r5, 4]
 1:
 
-#ifdef CONFIG_ARC_UBOOT_SUPPORT
         ; Uboot - kernel ABI
         ;    r0 = [0] No uboot interaction, [1] cmdline in r2, [2] DTB in r2
-        ;    r1 = magic number (board identity, unused as of now
+        ;    r1 = magic number (always zero as of now)
         ;    r2 = pointer to uboot provided cmdline or external DTB in mem
-        ; These are handled later in setup_arch()
+        ; These are handled later in handle_uboot_args()
         st      r0, [@uboot_tag]
         st      r2, [@uboot_arg]
-#endif
 
         ; setup "current" tsk and optionally cache it in dedicated r25
         mov     r9, @init_task
diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
index 067ea362fb3e..cf18b3e5a934 100644
--- a/arch/arc/kernel/intc-arcv2.c
+++ b/arch/arc/kernel/intc-arcv2.c
@@ -49,11 +49,13 @@ void arc_init_IRQ(void)
 
         *(unsigned int *)&ictrl = 0;
 
+#ifndef CONFIG_ARC_IRQ_NO_AUTOSAVE
         ictrl.save_nr_gpr_pairs = 6;    /* r0 to r11 (r12 saved manually) */
         ictrl.save_blink = 1;
         ictrl.save_lp_regs = 1;         /* LP_COUNT, LP_START, LP_END */
         ictrl.save_u_to_u = 0;          /* user ctxt saved on kernel stack */
         ictrl.save_idx_regs = 1;        /* JLI, LDI, EI */
+#endif
 
         WRITE_AUX(AUX_IRQ_CTRL, ictrl);
 
diff --git a/arch/arc/kernel/perf_event.c b/arch/arc/kernel/perf_event.c
index 8aec462d90fb..861a8aea51f9 100644
--- a/arch/arc/kernel/perf_event.c
+++ b/arch/arc/kernel/perf_event.c
@@ -1,15 +1,10 @@
-/*
- * Linux performance counter support for ARC700 series
- *
- * Copyright (C) 2013-2015 Synopsys, Inc. (www.synopsys.com)
- *
- * This code is inspired by the perf support of various other architectures.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Linux performance counter support for ARC CPUs.
+// This code is inspired by the perf support of various other architectures.
+//
+// Copyright (C) 2013-2018 Synopsys, Inc. (www.synopsys.com)
+
 #include <linux/errno.h>
 #include <linux/interrupt.h>
 #include <linux/module.h>
@@ -19,12 +14,31 @@
 #include <asm/arcregs.h>
 #include <asm/stacktrace.h>
 
+/* HW holds 8 symbols + one for null terminator */
+#define ARCPMU_EVENT_NAME_LEN   9
+
+enum arc_pmu_attr_groups {
+        ARCPMU_ATTR_GR_EVENTS,
+        ARCPMU_ATTR_GR_FORMATS,
+        ARCPMU_NR_ATTR_GR
+};
+
+struct arc_pmu_raw_event_entry {
+        char name[ARCPMU_EVENT_NAME_LEN];
+};
+
 struct arc_pmu {
         struct pmu      pmu;
         unsigned int    irq;
         int             n_counters;
+        int             n_events;
         u64             max_period;
         int             ev_hw_idx[PERF_COUNT_ARC_HW_MAX];
+
+        struct arc_pmu_raw_event_entry  *raw_entry;
+        struct attribute                **attrs;
+        struct perf_pmu_events_attr     *attr;
+        const struct attribute_group    *attr_groups[ARCPMU_NR_ATTR_GR + 1];
 };
 
 struct arc_pmu_cpu {
@@ -49,6 +63,7 @@ static int callchain_trace(unsigned int addr, void *data)
 {
         struct arc_callchain_trace *ctrl = data;
         struct perf_callchain_entry_ctx *entry = ctrl->perf_stuff;
+
         perf_callchain_store(entry, addr);
 
         if (ctrl->depth++ < 3)
@@ -57,8 +72,8 @@ static int callchain_trace(unsigned int addr, void *data)
         return -1;
 }
 
-void
-perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
+void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry,
+                           struct pt_regs *regs)
 {
         struct arc_callchain_trace ctrl = {
                 .depth = 0,
@@ -68,8 +83,8 @@ perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *re
         arc_unwind_core(NULL, regs, callchain_trace, &ctrl);
 }
 
-void
-perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
+void perf_callchain_user(struct perf_callchain_entry_ctx *entry,
+                         struct pt_regs *regs)
 {
         /*
          * User stack can't be unwound trivially with kernel dwarf unwinder
@@ -82,10 +97,10 @@ static struct arc_pmu *arc_pmu;
 static DEFINE_PER_CPU(struct arc_pmu_cpu, arc_pmu_cpu);
 
 /* read counter #idx; note that counter# != event# on ARC! */
-static uint64_t arc_pmu_read_counter(int idx)
+static u64 arc_pmu_read_counter(int idx)
 {
-        uint32_t tmp;
-        uint64_t result;
+        u32 tmp;
+        u64 result;
 
         /*
          * ARC supports making 'snapshots' of the counters, so we don't
@@ -94,7 +109,7 @@ static uint64_t arc_pmu_read_counter(int idx)
         write_aux_reg(ARC_REG_PCT_INDEX, idx);
         tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
         write_aux_reg(ARC_REG_PCT_CONTROL, tmp | ARC_REG_PCT_CONTROL_SN);
-        result = (uint64_t) (read_aux_reg(ARC_REG_PCT_SNAPH)) << 32;
+        result = (u64) (read_aux_reg(ARC_REG_PCT_SNAPH)) << 32;
         result |= read_aux_reg(ARC_REG_PCT_SNAPL);
 
         return result;
@@ -103,9 +118,9 @@ static uint64_t arc_pmu_read_counter(int idx)
 static void arc_perf_event_update(struct perf_event *event,
                                   struct hw_perf_event *hwc, int idx)
 {
-        uint64_t prev_raw_count = local64_read(&hwc->prev_count);
-        uint64_t new_raw_count = arc_pmu_read_counter(idx);
-        int64_t delta = new_raw_count - prev_raw_count;
+        u64 prev_raw_count = local64_read(&hwc->prev_count);
+        u64 new_raw_count = arc_pmu_read_counter(idx);
+        s64 delta = new_raw_count - prev_raw_count;
 
         /*
          * We aren't afraid of hwc->prev_count changing beneath our feet
@@ -155,7 +170,7 @@ static int arc_pmu_event_init(struct perf_event *event)
         int ret;
 
         if (!is_sampling_event(event)) {
-                hwc->sample_period  = arc_pmu->max_period;
+                hwc->sample_period = arc_pmu->max_period;
                 hwc->last_period = hwc->sample_period;
                 local64_set(&hwc->period_left, hwc->sample_period);
         }
@@ -192,6 +207,18 @@ static int arc_pmu_event_init(struct perf_event *event)
                 pr_debug("init cache event with h/w %08x \'%s\'\n",
                          (int)hwc->config, arc_pmu_ev_hw_map[ret]);
                 return 0;
+
+        case PERF_TYPE_RAW:
+                if (event->attr.config >= arc_pmu->n_events)
+                        return -ENOENT;
+
+                hwc->config |= event->attr.config;
+                pr_debug("init raw event with idx %lld \'%s\'\n",
+                         event->attr.config,
+                         arc_pmu->raw_entry[event->attr.config].name);
+
+                return 0;
+
         default:
                 return -ENOENT;
         }
@@ -200,7 +227,7 @@ static int arc_pmu_event_init(struct perf_event *event)
 /* starts all counters */
 static void arc_pmu_enable(struct pmu *pmu)
 {
-        uint32_t tmp;
+        u32 tmp;
         tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
         write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x1);
 }
@@ -208,7 +235,7 @@ static void arc_pmu_enable(struct pmu *pmu)
 /* stops all counters */
 static void arc_pmu_disable(struct pmu *pmu)
 {
-        uint32_t tmp;
+        u32 tmp;
         tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
         write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x0);
 }
@@ -228,7 +255,7 @@ static int arc_pmu_event_set_period(struct perf_event *event)
                 local64_set(&hwc->period_left, left);
                 hwc->last_period = period;
                 overflow = 1;
-        } else  if (unlikely(left <= 0)) {
+        } else if (unlikely(left <= 0)) {
                 /* left underflowed by less than period. */
                 left += period;
                 local64_set(&hwc->period_left, left);
@@ -246,8 +273,8 @@ static int arc_pmu_event_set_period(struct perf_event *event)
         write_aux_reg(ARC_REG_PCT_INDEX, idx);
 
         /* Write value */
-        write_aux_reg(ARC_REG_PCT_COUNTL, (u32)value);
-        write_aux_reg(ARC_REG_PCT_COUNTH, (value >> 32));
+        write_aux_reg(ARC_REG_PCT_COUNTL, lower_32_bits(value));
+        write_aux_reg(ARC_REG_PCT_COUNTH, upper_32_bits(value));
 
         perf_event_update_userpage(event);
 
@@ -277,7 +304,7 @@ static void arc_pmu_start(struct perf_event *event, int flags)
         /* Enable interrupt for this counter */
         if (is_sampling_event(event))
                 write_aux_reg(ARC_REG_PCT_INT_CTRL,
-                              read_aux_reg(ARC_REG_PCT_INT_CTRL) | (1 << idx));
+                              read_aux_reg(ARC_REG_PCT_INT_CTRL) | BIT(idx));
 
         /* enable ARC pmu here */
         write_aux_reg(ARC_REG_PCT_INDEX, idx);          /* counter # */
@@ -295,9 +322,9 @@ static void arc_pmu_stop(struct perf_event *event, int flags)
                  * Reset interrupt flag by writing of 1. This is required
                  * to make sure pending interrupt was not left.
                  */
-                write_aux_reg(ARC_REG_PCT_INT_ACT, 1 << idx);
+                write_aux_reg(ARC_REG_PCT_INT_ACT, BIT(idx));
                 write_aux_reg(ARC_REG_PCT_INT_CTRL,
-                              read_aux_reg(ARC_REG_PCT_INT_CTRL) & ~(1 << idx));
+                              read_aux_reg(ARC_REG_PCT_INT_CTRL) & ~BIT(idx));
         }
 
         if (!(event->hw.state & PERF_HES_STOPPED)) {
@@ -349,9 +376,10 @@ static int arc_pmu_add(struct perf_event *event, int flags)
 
         if (is_sampling_event(event)) {
                 /* Mimic full counter overflow as other arches do */
-                write_aux_reg(ARC_REG_PCT_INT_CNTL, (u32)arc_pmu->max_period);
+                write_aux_reg(ARC_REG_PCT_INT_CNTL,
+                              lower_32_bits(arc_pmu->max_period));
                 write_aux_reg(ARC_REG_PCT_INT_CNTH,
-                              (arc_pmu->max_period >> 32));
+                              upper_32_bits(arc_pmu->max_period));
         }
 
         write_aux_reg(ARC_REG_PCT_CONFIG, 0);
@@ -392,7 +420,7 @@ static irqreturn_t arc_pmu_intr(int irq, void *dev)
                 idx = __ffs(active_ints);
 
                 /* Reset interrupt flag by writing of 1 */
-                write_aux_reg(ARC_REG_PCT_INT_ACT, 1 << idx);
+                write_aux_reg(ARC_REG_PCT_INT_ACT, BIT(idx));
 
                 /*
                  * On reset of "interrupt active" bit corresponding
@@ -400,7 +428,7 @@ static irqreturn_t arc_pmu_intr(int irq, void *dev)
                  * Now we need to re-enable interrupt for the counter.
                  */
                 write_aux_reg(ARC_REG_PCT_INT_CTRL,
-                        read_aux_reg(ARC_REG_PCT_INT_CTRL) | (1 << idx));
+                        read_aux_reg(ARC_REG_PCT_INT_CTRL) | BIT(idx));
 
                 event = pmu_cpu->act_counter[idx];
                 hwc = &event->hw;
@@ -414,7 +442,7 @@ static irqreturn_t arc_pmu_intr(int irq, void *dev)
                                 arc_pmu_stop(event, 0);
                 }
 
-                active_ints &= ~(1U << idx);
+                active_ints &= ~BIT(idx);
         } while (active_ints);
 
 done:
@@ -441,19 +469,108 @@ static void arc_cpu_pmu_irq_init(void *data)
         write_aux_reg(ARC_REG_PCT_INT_ACT, 0xffffffff);
 }
 
+/* Event field occupies the bottom 15 bits of our config field */
+PMU_FORMAT_ATTR(event, "config:0-14");
+static struct attribute *arc_pmu_format_attrs[] = {
+        &format_attr_event.attr,
+        NULL,
+};
+
+static struct attribute_group arc_pmu_format_attr_gr = {
+        .name = "format",
+        .attrs = arc_pmu_format_attrs,
+};
+
+static ssize_t arc_pmu_events_sysfs_show(struct device *dev,
+                                         struct device_attribute *attr,
+                                         char *page)
+{
+        struct perf_pmu_events_attr *pmu_attr;
+
+        pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
+        return sprintf(page, "event=0x%04llx\n", pmu_attr->id);
+}
+
+/*
+ * We don't add attrs here as we don't have pre-defined list of perf events.
+ * We will generate and add attrs dynamically in probe() after we read HW
+ * configuration.
+ */
+static struct attribute_group arc_pmu_events_attr_gr = {
+        .name = "events",
+};
+
+static void arc_pmu_add_raw_event_attr(int j, char *str)
+{
+        memmove(arc_pmu->raw_entry[j].name, str, ARCPMU_EVENT_NAME_LEN - 1);
+        arc_pmu->attr[j].attr.attr.name = arc_pmu->raw_entry[j].name;
+        arc_pmu->attr[j].attr.attr.mode = VERIFY_OCTAL_PERMISSIONS(0444);
+        arc_pmu->attr[j].attr.show = arc_pmu_events_sysfs_show;
+        arc_pmu->attr[j].id = j;
+        arc_pmu->attrs[j] = &(arc_pmu->attr[j].attr.attr);
+}
+
+static int arc_pmu_raw_alloc(struct device *dev)
+{
+        arc_pmu->attr = devm_kmalloc_array(dev, arc_pmu->n_events + 1,
+                sizeof(*arc_pmu->attr), GFP_KERNEL | __GFP_ZERO);
+        if (!arc_pmu->attr)
+                return -ENOMEM;
+
+        arc_pmu->attrs = devm_kmalloc_array(dev, arc_pmu->n_events + 1,
+                sizeof(*arc_pmu->attrs), GFP_KERNEL | __GFP_ZERO);
+        if (!arc_pmu->attrs)
+                return -ENOMEM;
+
+        arc_pmu->raw_entry = devm_kmalloc_array(dev, arc_pmu->n_events,
+                sizeof(*arc_pmu->raw_entry), GFP_KERNEL | __GFP_ZERO);
+        if (!arc_pmu->raw_entry)
+                return -ENOMEM;
+
+        return 0;
+}
+
+static inline bool event_in_hw_event_map(int i, char *name)
+{
+        if (!arc_pmu_ev_hw_map[i])
+                return false;
+
+        if (!strlen(arc_pmu_ev_hw_map[i]))
+                return false;
+
+        if (strcmp(arc_pmu_ev_hw_map[i], name))
+                return false;
+
+        return true;
+}
+
+static void arc_pmu_map_hw_event(int j, char *str)
+{
+        int i;
+
+        /* See if HW condition has been mapped to a perf event_id */
+        for (i = 0; i < ARRAY_SIZE(arc_pmu_ev_hw_map); i++) {
+                if (event_in_hw_event_map(i, str)) {
+                        pr_debug("mapping perf event %2d to h/w event \'%8s\' (idx %d)\n",
+                                 i, str, j);
+                        arc_pmu->ev_hw_idx[i] = j;
+                }
+        }
+}
+
 static int arc_pmu_device_probe(struct platform_device *pdev)
 {
         struct arc_reg_pct_build pct_bcr;
         struct arc_reg_cc_build cc_bcr;
-        int i, j, has_interrupts;
+        int i, has_interrupts;
         int counter_size;       /* in bits */
 
         union cc_name {
                 struct {
-                        uint32_t word0, word1;
+                        u32 word0, word1;
                         char sentinel;
                 } indiv;
-                char str[9];
+                char str[ARCPMU_EVENT_NAME_LEN];
         } cc_name;
 
 
@@ -463,15 +580,22 @@ static int arc_pmu_device_probe(struct platform_device *pdev)
                 return -ENODEV;
         }
         BUILD_BUG_ON(ARC_PERF_MAX_COUNTERS > 32);
-        BUG_ON(pct_bcr.c > ARC_PERF_MAX_COUNTERS);
+        if (WARN_ON(pct_bcr.c > ARC_PERF_MAX_COUNTERS))
+                return -EINVAL;
 
         READ_BCR(ARC_REG_CC_BUILD, cc_bcr);
-        BUG_ON(!cc_bcr.v); /* Counters exist but No countable conditions ? */
+        if (WARN(!cc_bcr.v, "Counters exist but No countable conditions?"))
+                return -EINVAL;
 
         arc_pmu = devm_kzalloc(&pdev->dev, sizeof(struct arc_pmu), GFP_KERNEL);
         if (!arc_pmu)
                 return -ENOMEM;
 
+        arc_pmu->n_events = cc_bcr.c;
+
+        if (arc_pmu_raw_alloc(&pdev->dev))
+                return -ENOMEM;
+
         has_interrupts = is_isa_arcv2() ? pct_bcr.i : 0;
 
         arc_pmu->n_counters = pct_bcr.c;
@@ -481,30 +605,26 @@ static int arc_pmu_device_probe(struct platform_device *pdev)
 
         pr_info("ARC perf\t: %d counters (%d bits), %d conditions%s\n",
                 arc_pmu->n_counters, counter_size, cc_bcr.c,
-                has_interrupts ? ", [overflow IRQ support]":"");
+                has_interrupts ? ", [overflow IRQ support]" : "");
 
-        cc_name.str[8] = 0;
+        cc_name.str[ARCPMU_EVENT_NAME_LEN - 1] = 0;
         for (i = 0; i < PERF_COUNT_ARC_HW_MAX; i++)
                 arc_pmu->ev_hw_idx[i] = -1;
 
         /* loop thru all available h/w condition indexes */
-        for (j = 0; j < cc_bcr.c; j++) {
-                write_aux_reg(ARC_REG_CC_INDEX, j);
+        for (i = 0; i < cc_bcr.c; i++) {
+                write_aux_reg(ARC_REG_CC_INDEX, i);
                 cc_name.indiv.word0 = read_aux_reg(ARC_REG_CC_NAME0);
                 cc_name.indiv.word1 = read_aux_reg(ARC_REG_CC_NAME1);
 
-                /* See if it has been mapped to a perf event_id */
-                for (i = 0; i < ARRAY_SIZE(arc_pmu_ev_hw_map); i++) {
-                        if (arc_pmu_ev_hw_map[i] &&
-                            !strcmp(arc_pmu_ev_hw_map[i], cc_name.str) &&
-                            strlen(arc_pmu_ev_hw_map[i])) {
-                                pr_debug("mapping perf event %2d to h/w event \'%8s\' (idx %d)\n",
-                                         i, cc_name.str, j);
-                                arc_pmu->ev_hw_idx[i] = j;
-                        }
-                }
+                arc_pmu_map_hw_event(i, cc_name.str);
+                arc_pmu_add_raw_event_attr(i, cc_name.str);
         }
 
+        arc_pmu_events_attr_gr.attrs = arc_pmu->attrs;
+        arc_pmu->attr_groups[ARCPMU_ATTR_GR_EVENTS] = &arc_pmu_events_attr_gr;
+        arc_pmu->attr_groups[ARCPMU_ATTR_GR_FORMATS] = &arc_pmu_format_attr_gr;
+
         arc_pmu->pmu = (struct pmu) {
                 .pmu_enable     = arc_pmu_enable,
                 .pmu_disable    = arc_pmu_disable,
@@ -514,6 +634,7 @@ static int arc_pmu_device_probe(struct platform_device *pdev)
                 .start          = arc_pmu_start,
                 .stop           = arc_pmu_stop,
                 .read           = arc_pmu_read,
+                .attr_groups    = arc_pmu->attr_groups,
         };
 
         if (has_interrupts) {
@@ -535,17 +656,19 @@ static int arc_pmu_device_probe(struct platform_device *pdev)
         } else
                 arc_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
 
-        return perf_pmu_register(&arc_pmu->pmu, pdev->name, PERF_TYPE_RAW);
+        /*
+         * perf parser doesn't really like '-' symbol in events name, so let's
+         * use '_' in arc pct name as it goes to kernel PMU event prefix.
+         */
+        return perf_pmu_register(&arc_pmu->pmu, "arc_pct", PERF_TYPE_RAW);
 }
 
-#ifdef CONFIG_OF
 static const struct of_device_id arc_pmu_match[] = {
         { .compatible = "snps,arc700-pct" },
         { .compatible = "snps,archs-pct" },
         {},
 };
 MODULE_DEVICE_TABLE(of, arc_pmu_match);
-#endif
 
 static struct platform_driver arc_pmu_driver = {
         .driver = {
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 2e018b8c2e19..7b2340996cf8 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -123,6 +123,7 @@ static void read_arc_build_cfg_regs(void)
         struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
         const struct id_to_str *tbl;
         struct bcr_isa_arcv2 isa;
+        struct bcr_actionpoint ap;
 
         FIX_PTR(cpu);
 
@@ -195,20 +196,40 @@ static void read_arc_build_cfg_regs(void)
                 cpu->bpu.full = bpu.ft;
                 cpu->bpu.num_cache = 256 << bpu.bce;
                 cpu->bpu.num_pred = 2048 << bpu.pte;
+                cpu->bpu.ret_stk = 4 << bpu.rse;
 
                 if (cpu->core.family >= 0x54) {
-                        unsigned int exec_ctrl;
 
-                        READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
-                        cpu->extn.dual_enb = !(exec_ctrl & 1);
+                        struct bcr_uarch_build_arcv2 uarch;
 
-                        /* dual issue always present for this core */
-                        cpu->extn.dual = 1;
+                        /*
+                         * The first 0x54 core (uarch maj:min 0:1 or 0:2) was
+                         * dual issue only (HS4x). But next uarch rev (1:0)
+                         * allows it be configured for single issue (HS3x)
+                         * Ensure we fiddle with dual issue only on HS4x
+                         */
+                        READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch);
+
+                        if (uarch.prod == 4) {
+                                unsigned int exec_ctrl;
+
+                                /* dual issue hardware always present */
+                                cpu->extn.dual = 1;
+
+                                READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
+
+                                /* dual issue hardware enabled ? */
+                                cpu->extn.dual_enb = !(exec_ctrl & 1);
+
+                        }
                 }
         }
 
-        READ_BCR(ARC_REG_AP_BCR, bcr);
-        cpu->extn.ap = bcr.ver ? 1 : 0;
+        READ_BCR(ARC_REG_AP_BCR, ap);
+        if (ap.ver) {
+                cpu->extn.ap_num = 2 << ap.num;
+                cpu->extn.ap_full = !ap.min;
+        }
 
         READ_BCR(ARC_REG_SMART_BCR, bcr);
         cpu->extn.smart = bcr.ver ? 1 : 0;
@@ -216,8 +237,6 @@ static void read_arc_build_cfg_regs(void)
         READ_BCR(ARC_REG_RTT_BCR, bcr);
         cpu->extn.rtt = bcr.ver ? 1 : 0;
 
-        cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt;
-
         READ_BCR(ARC_REG_ISA_CFG_BCR, isa);
 
         /* some hacks for lack of feature BCR info in old ARC700 cores */
@@ -299,10 +318,10 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
 
         if (cpu->bpu.ver)
                 n += scnprintf(buf + n, len - n,
-                              "BPU\t\t: %s%s match, cache:%d, Predict Table:%d",
+                              "BPU\t\t: %s%s match, cache:%d, Predict Table:%d Return stk: %d",
                               IS_AVAIL1(cpu->bpu.full, "full"),
                               IS_AVAIL1(!cpu->bpu.full, "partial"),
-                              cpu->bpu.num_cache, cpu->bpu.num_pred);
+                              cpu->bpu.num_cache, cpu->bpu.num_pred, cpu->bpu.ret_stk);
 
         if (is_isa_arcv2()) {
                 struct bcr_lpb lpb;
@@ -336,11 +355,17 @@ static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
                                IS_AVAIL1(cpu->extn.fpu_sp, "SP "),
                                IS_AVAIL1(cpu->extn.fpu_dp, "DP "));
 
-        if (cpu->extn.debug)
-                n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s%s\n",
-                               IS_AVAIL1(cpu->extn.ap, "ActionPoint "),
+        if (cpu->extn.ap_num | cpu->extn.smart | cpu->extn.rtt) {
+                n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s",
                                IS_AVAIL1(cpu->extn.smart, "smaRT "),
                                IS_AVAIL1(cpu->extn.rtt, "RTT "));
+                if (cpu->extn.ap_num) {
+                        n += scnprintf(buf + n, len - n, "ActionPoint %d/%s",
+                                       cpu->extn.ap_num,
+                                       cpu->extn.ap_full ? "full":"min");
+                }
+                n += scnprintf(buf + n, len - n, "\n");
+        }
 
         if (cpu->dccm.sz || cpu->iccm.sz)
                 n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n",
@@ -453,43 +478,78 @@ void setup_processor(void)
         arc_chk_core_config();
 }
 
-static inline int is_kernel(unsigned long addr)
+static inline bool uboot_arg_invalid(unsigned long addr)
 {
-        if (addr >= (unsigned long)_stext && addr <= (unsigned long)_end)
-                return 1;
-        return 0;
+        /*
+         * Check that it is a untranslated address (although MMU is not enabled
+         * yet, it being a high address ensures this is not by fluke)
+         */
+        if (addr < PAGE_OFFSET)
+                return true;
+
+        /* Check that address doesn't clobber resident kernel image */
+        return addr >= (unsigned long)_stext && addr <= (unsigned long)_end;
 }
 
-void __init setup_arch(char **cmdline_p)
+#define IGNORE_ARGS             "Ignore U-boot args: "
+
+/* uboot_tag values for U-boot - kernel ABI revision 0; see head.S */
+#define UBOOT_TAG_NONE          0
+#define UBOOT_TAG_CMDLINE       1
+#define UBOOT_TAG_DTB           2
+
+void __init handle_uboot_args(void)
 {
-#ifdef CONFIG_ARC_UBOOT_SUPPORT
-        /* make sure that uboot passed pointer to cmdline/dtb is valid */
-        if (uboot_tag && is_kernel((unsigned long)uboot_arg))
-                panic("Invalid uboot arg\n");
-
-        /* See if u-boot passed an external Device Tree blob */
-        machine_desc = setup_machine_fdt(uboot_arg);    /* uboot_tag == 2 */
-        if (!machine_desc)
-#endif
-        {
-                /* No, so try the embedded one */
+        bool use_embedded_dtb = true;
+        bool append_cmdline = false;
+
+        /* check that we know this tag */
+        if (uboot_tag != UBOOT_TAG_NONE &&
+            uboot_tag != UBOOT_TAG_CMDLINE &&
+            uboot_tag != UBOOT_TAG_DTB) {
+                pr_warn(IGNORE_ARGS "invalid uboot tag: '%08x'\n", uboot_tag);
+                goto ignore_uboot_args;
+        }
+
+        if (uboot_tag != UBOOT_TAG_NONE &&
+            uboot_arg_invalid((unsigned long)uboot_arg)) {
+                pr_warn(IGNORE_ARGS "invalid uboot arg: '%px'\n", uboot_arg);
+                goto ignore_uboot_args;
+        }
+
+        /* see if U-boot passed an external Device Tree blob */
+        if (uboot_tag == UBOOT_TAG_DTB) {
+                machine_desc = setup_machine_fdt((void *)uboot_arg);
+
+                /* external Device Tree blob is invalid - use embedded one */
+                use_embedded_dtb = !machine_desc;
+        }
+
+        if (uboot_tag == UBOOT_TAG_CMDLINE)
+                append_cmdline = true;
+
+ignore_uboot_args:
+
+        if (use_embedded_dtb) {
                 machine_desc = setup_machine_fdt(__dtb_start);
                 if (!machine_desc)
                         panic("Embedded DT invalid\n");
+        }
 
-                /*
-                 * If we are here, it is established that @uboot_arg didn't
-                 * point to DT blob. Instead if u-boot says it is cmdline,
-                 * append to embedded DT cmdline.
-                 * setup_machine_fdt() would have populated @boot_command_line
-                 */
-                if (uboot_tag == 1) {
-                        /* Ensure a whitespace between the 2 cmdlines */
-                        strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
-                        strlcat(boot_command_line, uboot_arg,
-                                COMMAND_LINE_SIZE);
-                }
+        /*
+         * NOTE: @boot_command_line is populated by setup_machine_fdt() so this
+         * append processing can only happen after.
+         */
+        if (append_cmdline) {
+                /* Ensure a whitespace between the 2 cmdlines */
+                strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
+                strlcat(boot_command_line, uboot_arg, COMMAND_LINE_SIZE);
         }
+}
+
+void __init setup_arch(char **cmdline_p)
+{
+        handle_uboot_args();
 
         /* Save unparsed command line copy for /proc/cmdline */
         *cmdline_p = boot_command_line;
diff --git a/arch/arc/kernel/troubleshoot.c b/arch/arc/kernel/troubleshoot.c
index e8d9fb452346..215f515442e0 100644
--- a/arch/arc/kernel/troubleshoot.c
+++ b/arch/arc/kernel/troubleshoot.c
@@ -18,6 +18,8 @@
 #include <asm/arcregs.h>
 #include <asm/irqflags.h>
 
+#define ARC_PATH_MAX    256
+
 /*
  * Common routine to print scratch regs (r0-r12) or callee regs (r13-r25)
  *   -Prints 3 regs per line and a CR.
@@ -58,11 +60,12 @@ static void show_callee_regs(struct callee_regs *cregs)
         print_reg_file(&(cregs->r13), 13);
 }
 
-static void print_task_path_n_nm(struct task_struct *tsk, char *buf)
+static void print_task_path_n_nm(struct task_struct *tsk)
 {
         char *path_nm = NULL;
         struct mm_struct *mm;
         struct file *exe_file;
+        char buf[ARC_PATH_MAX];
 
         mm = get_task_mm(tsk);
         if (!mm)
@@ -72,7 +75,7 @@ static void print_task_path_n_nm(struct task_struct *tsk, char *buf)
         mmput(mm);
 
         if (exe_file) {
-                path_nm = file_path(exe_file, buf, 255);
+                path_nm = file_path(exe_file, buf, ARC_PATH_MAX-1);
                 fput(exe_file);
         }
 
@@ -80,10 +83,9 @@ done:
         pr_info("Path: %s\n", !IS_ERR(path_nm) ? path_nm : "?");
 }
 
-static void show_faulting_vma(unsigned long address, char *buf)
+static void show_faulting_vma(unsigned long address)
 {
         struct vm_area_struct *vma;
-        char *nm = buf;
         struct mm_struct *active_mm = current->active_mm;
 
         /* can't use print_vma_addr() yet as it doesn't check for
@@ -96,8 +98,11 @@ static void show_faulting_vma(unsigned long address, char *buf)
          * if the container VMA is not found
          */
         if (vma && (vma->vm_start <= address)) {
+                char buf[ARC_PATH_MAX];
+                char *nm = "?";
+
                 if (vma->vm_file) {
-                        nm = file_path(vma->vm_file, buf, PAGE_SIZE - 1);
+                        nm = file_path(vma->vm_file, buf, ARC_PATH_MAX-1);
                         if (IS_ERR(nm))
                                 nm = "?";
                 }
@@ -173,13 +178,14 @@ void show_regs(struct pt_regs *regs)
 {
         struct task_struct *tsk = current;
         struct callee_regs *cregs;
-        char *buf;
 
-        buf = (char *)__get_free_page(GFP_KERNEL);
-        if (!buf)
-                return;
+        /*
+         * generic code calls us with preemption disabled, but some calls
+         * here could sleep, so re-enable to avoid lockdep splat
+         */
+        preempt_enable();
 
-        print_task_path_n_nm(tsk, buf);
+        print_task_path_n_nm(tsk);
         show_regs_print_info(KERN_INFO);
 
         show_ecr_verbose(regs);
@@ -189,7 +195,7 @@ void show_regs(struct pt_regs *regs)
                 (void *)regs->blink, (void *)regs->ret);
 
         if (user_mode(regs))
-                show_faulting_vma(regs->ret, buf); /* faulting code, not data */
+                show_faulting_vma(regs->ret); /* faulting code, not data */
 
         pr_info("[STAT32]: 0x%08lx", regs->status32);
 
@@ -222,7 +228,7 @@ void show_regs(struct pt_regs *regs)
         if (cregs)
                 show_callee_regs(cregs);
 
-        free_page((unsigned long)buf);
+        preempt_disable();
 }
 
 void show_kernel_fault_diag(const char *str, struct pt_regs *regs,
diff --git a/arch/arc/lib/memcpy-archs.S b/arch/arc/lib/memcpy-archs.S
index d61044dd8b58..ea14b0bf3116 100644
--- a/arch/arc/lib/memcpy-archs.S
+++ b/arch/arc/lib/memcpy-archs.S
@@ -25,15 +25,11 @@
 #endif
 
 #ifdef CONFIG_ARC_HAS_LL64
-# define PREFETCH_READ(RX)      prefetch    [RX, 56]
-# define PREFETCH_WRITE(RX)     prefetchw   [RX, 64]
 # define LOADX(DST,RX)          ldd.ab  DST, [RX, 8]
 # define STOREX(SRC,RX)         std.ab  SRC, [RX, 8]
 # define ZOLSHFT                5
 # define ZOLAND                 0x1F
 #else
-# define PREFETCH_READ(RX)      prefetch    [RX, 28]
-# define PREFETCH_WRITE(RX)     prefetchw   [RX, 32]
 # define LOADX(DST,RX)          ld.ab   DST, [RX, 4]
 # define STOREX(SRC,RX)         st.ab   SRC, [RX, 4]
 # define ZOLSHFT                4
@@ -41,8 +37,6 @@
 #endif
 
 ENTRY_CFI(memcpy)
-        prefetch [r1]           ; Prefetch the read location
-        prefetchw [r0]          ; Prefetch the write location
         mov.f   0, r2
 ;;; if size is zero
         jz.d    [blink]
@@ -72,8 +66,6 @@ ENTRY_CFI(memcpy)
         lpnz    @.Lcopy32_64bytes
         ;; LOOP START
         LOADX (r6, r1)
-        PREFETCH_READ (r1)
-        PREFETCH_WRITE (r3)
         LOADX (r8, r1)
         LOADX (r10, r1)
         LOADX (r4, r1)
@@ -117,9 +109,7 @@ ENTRY_CFI(memcpy)
         lpnz    @.Lcopy8bytes_1
         ;; LOOP START
         ld.ab   r6, [r1, 4]
-        prefetch [r1, 28]       ;Prefetch the next read location
         ld.ab   r8, [r1,4]
-        prefetchw [r3, 32]      ;Prefetch the next write location
 
         SHIFT_1 (r7, r6, 24)
         or      r7, r7, r5
@@ -162,9 +152,7 @@ ENTRY_CFI(memcpy)
         lpnz    @.Lcopy8bytes_2
         ;; LOOP START
         ld.ab   r6, [r1, 4]
-        prefetch [r1, 28]       ;Prefetch the next read location
         ld.ab   r8, [r1,4]
-        prefetchw [r3, 32]      ;Prefetch the next write location
 
         SHIFT_1 (r7, r6, 16)
         or      r7, r7, r5
@@ -204,9 +192,7 @@ ENTRY_CFI(memcpy)
         lpnz    @.Lcopy8bytes_3
         ;; LOOP START
         ld.ab   r6, [r1, 4]
-        prefetch [r1, 28]       ;Prefetch the next read location
         ld.ab   r8, [r1,4]
-        prefetchw [r3, 32]      ;Prefetch the next write location
 
         SHIFT_1 (r7, r6, 8)
         or      r7, r7, r5
diff --git a/arch/arc/lib/memset-archs.S b/arch/arc/lib/memset-archs.S
index 62ad4bcb841a..f230bb7092fd 100644
--- a/arch/arc/lib/memset-archs.S
+++ b/arch/arc/lib/memset-archs.S
@@ -7,11 +7,39 @@
  */
 
 #include <linux/linkage.h>
+#include <asm/cache.h>
 
-#undef PREALLOC_NOT_AVAIL
+/*
+ * The memset implementation below is optimized to use prefetchw and prealloc
+ * instruction in case of CPU with 64B L1 data cache line (L1_CACHE_SHIFT == 6)
+ * If you want to implement optimized memset for other possible L1 data cache
+ * line lengths (32B and 128B) you should rewrite code carefully checking
+ * we don't call any prefetchw/prealloc instruction for L1 cache lines which
+ * don't belongs to memset area.
+ */
+
+#if L1_CACHE_SHIFT == 6
+
+.macro PREALLOC_INSTR   reg, off
+        prealloc        [\reg, \off]
+.endm
+
+.macro PREFETCHW_INSTR  reg, off
+        prefetchw       [\reg, \off]
+.endm
+
+#else
+
+.macro PREALLOC_INSTR
+.endm
+
+.macro PREFETCHW_INSTR
+.endm
+
+#endif
 
 ENTRY_CFI(memset)
-        prefetchw [r0]          ; Prefetch the write location
+        PREFETCHW_INSTR r0, 0   ; Prefetch the first write location
         mov.f   0, r2
 ;;; if size is zero
         jz.d    [blink]
@@ -48,11 +76,8 @@ ENTRY_CFI(memset)
 
         lpnz    @.Lset64bytes
         ;; LOOP START
-#ifdef PREALLOC_NOT_AVAIL
-        prefetchw [r3, 64]      ;Prefetch the next write location
-#else
-        prealloc  [r3, 64]
-#endif
+        PREALLOC_INSTR  r3, 64  ; alloc next line w/o fetching
+
 #ifdef CONFIG_ARC_HAS_LL64
         std.ab  r4, [r3, 8]
         std.ab  r4, [r3, 8]
@@ -85,7 +110,6 @@ ENTRY_CFI(memset)
         lsr.f   lp_count, r2, 5 ;Last remaining  max 124 bytes
         lpnz    .Lset32bytes
         ;; LOOP START
-        prefetchw   [r3, 32]    ;Prefetch the next write location
 #ifdef CONFIG_ARC_HAS_LL64
         std.ab  r4, [r3, 8]
         std.ab  r4, [r3, 8]
diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c
index a1d723197084..8df1638259f3 100644
--- a/arch/arc/mm/fault.c
+++ b/arch/arc/mm/fault.c
@@ -141,12 +141,17 @@ good_area:
          */
         fault = handle_mm_fault(vma, address, flags);
 
-        /* If Pagefault was interrupted by SIGKILL, exit page fault "early" */
         if (fatal_signal_pending(current)) {
-                if ((fault & VM_FAULT_ERROR) && !(fault & VM_FAULT_RETRY))
-                        up_read(&mm->mmap_sem);
-                if (user_mode(regs))
+
+                /*
+                 * if fault retry, mmap_sem already relinquished by core mm
+                 * so OK to return to user mode (with signal handled first)
+                 */
+                if (fault & VM_FAULT_RETRY) {
+                        if (!user_mode(regs))
+                                goto no_context;
                         return;
+                }
         }
 
         perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c
index 43bf4c3a1290..e1ab2d7f1d64 100644
--- a/arch/arc/mm/init.c
+++ b/arch/arc/mm/init.c
@@ -119,7 +119,8 @@ void __init setup_arch_memory(void)
          */
 
         memblock_add_node(low_mem_start, low_mem_sz, 0);
-        memblock_reserve(low_mem_start, __pa(_end) - low_mem_start);
+        memblock_reserve(CONFIG_LINUX_LINK_BASE,
+                         __pa(_end) - CONFIG_LINUX_LINK_BASE);
 
 #ifdef CONFIG_BLK_DEV_INITRD
         if (phys_initrd_size) {
diff --git a/arch/arc/plat-hsdk/Kconfig b/arch/arc/plat-hsdk/Kconfig
index f25c085b9874..23e00216e5a5 100644
--- a/arch/arc/plat-hsdk/Kconfig
+++ b/arch/arc/plat-hsdk/Kconfig
@@ -9,6 +9,7 @@ menuconfig ARC_SOC_HSDK
         bool "ARC HS Development Kit SOC"
         depends on ISA_ARCV2
         select ARC_HAS_ACCL_REGS
+        select ARC_IRQ_NO_AUTOSAVE
         select CLK_HSDK
         select RESET_HSDK
         select HAVE_PCI