1 files changed, 21 insertions, 15 deletions

diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 25c631942500..f2701c13a66b 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -65,7 +65,7 @@ char *arc_cache_mumbojumbo(int c, char *buf, int len)
 
         n += scnprintf(buf + n, len - n, "Peripherals\t: %#lx%s%s\n",
                        perip_base,
-                       IS_AVAIL3(ioc_exists, ioc_enable, ", IO-Coherency "));
+                       IS_AVAIL3(ioc_exists, ioc_enable, ", IO-Coherency (per-device) "));
 
         return buf;
 }
@@ -897,15 +897,6 @@ static void __dma_cache_wback_slc(phys_addr_t start, unsigned long sz)
 }
 
 /*
- * DMA ops for systems with IOC
- * IOC hardware snoops all DMA traffic keeping the caches consistent with
- * memory - eliding need for any explicit cache maintenance of DMA buffers
- */
-static void __dma_cache_wback_inv_ioc(phys_addr_t start, unsigned long sz) {}
-static void __dma_cache_inv_ioc(phys_addr_t start, unsigned long sz) {}
-static void __dma_cache_wback_ioc(phys_addr_t start, unsigned long sz) {}
-
-/*
  * Exported DMA API
  */
 void dma_cache_wback_inv(phys_addr_t start, unsigned long sz)
@@ -1153,6 +1144,19 @@ noinline void __init arc_ioc_setup(void)
 {
         unsigned int ioc_base, mem_sz;
 
+        /*
+         * As for today we don't support both IOC and ZONE_HIGHMEM enabled
+         * simultaneously. This happens because as of today IOC aperture covers
+         * only ZONE_NORMAL (low mem) and any dma transactions outside this
+         * region won't be HW coherent.
+         * If we want to use both IOC and ZONE_HIGHMEM we can use
+         * bounce_buffer to handle dma transactions to HIGHMEM.
+         * Also it is possible to modify dma_direct cache ops or increase IOC
+         * aperture size if we are planning to use HIGHMEM without PAE.
+         */
+        if (IS_ENABLED(CONFIG_HIGHMEM))
+                panic("IOC and HIGHMEM can't be used simultaneously");
+
         /* Flush + invalidate + disable L1 dcache */
         __dc_disable();
 
@@ -1264,11 +1268,7 @@ void __init arc_cache_init_master(void)
         if (is_isa_arcv2() && ioc_enable)
                 arc_ioc_setup();
 
-        if (is_isa_arcv2() && ioc_enable) {
-                __dma_cache_wback_inv = __dma_cache_wback_inv_ioc;
-                __dma_cache_inv = __dma_cache_inv_ioc;
-                __dma_cache_wback = __dma_cache_wback_ioc;
-        } else if (is_isa_arcv2() && l2_line_sz && slc_enable) {
+        if (is_isa_arcv2() && l2_line_sz && slc_enable) {
                 __dma_cache_wback_inv = __dma_cache_wback_inv_slc;
                 __dma_cache_inv = __dma_cache_inv_slc;
                 __dma_cache_wback = __dma_cache_wback_slc;
@@ -1277,6 +1277,12 @@ void __init arc_cache_init_master(void)
                 __dma_cache_inv = __dma_cache_inv_l1;
                 __dma_cache_wback = __dma_cache_wback_l1;
         }
+        /*
+         * In case of IOC (say IOC+SLC case), pointers above could still be set
+         * but end up not being relevant as the first function in chain is not
+         * called at all for @dma_direct_ops
+         *     arch_sync_dma_for_cpu() -> dma_cache_*() -> __dma_cache_*()
+         */
 }
 
 void __ref arc_cache_init(void)