47 files changed, 1131 insertions, 43 deletions

diff --git a/Documentation/ABI/testing/configfs-usb-gadget-tcm b/Documentation/ABI/testing/configfs-usb-gadget-tcm
new file mode 100644
index 000000000000..a29ed2dd6173
--- /dev/null
+++ b/Documentation/ABI/testing/configfs-usb-gadget-tcm
@@ -0,0 +1,6 @@
+What:           /config/usb-gadget/gadget/functions/tcm.name
+Date:           Dec 2015
+KernelVersion:  4.5
+Description:
+                There are no attributes because all the configuration
+                is performed in the "target" subsystem of configfs.
diff --git a/Documentation/arm/pxa/mfp.txt b/Documentation/arm/pxa/mfp.txt
index a179e5bc02c9..0b7cab978c02 100644
--- a/Documentation/arm/pxa/mfp.txt
+++ b/Documentation/arm/pxa/mfp.txt
@@ -49,7 +49,7 @@ to this new MFP mechanism, here are several key points:
      internal controllers like PWM, SSP and UART, with 128 internal signals
      which can be routed to external through one or more MFPs (e.g. GPIO<0>
      can be routed through either MFP_PIN_GPIO0 as well as MFP_PIN_GPIO0_2,
-     see arch/arm/mach-pxa/mach/include/mfp-pxa300.h)
+     see arch/arm/mach-pxa/mfp-pxa300.h)
 
   2. Alternate function configuration is removed from this GPIO controller,
      the remaining functions are pure GPIO-specific, i.e.
@@ -76,11 +76,11 @@ For board code writers, here are some guidelines:
 
 1. include ONE of the following header files in your <board>.c:
 
-   - #include <mach/mfp-pxa25x.h>
-   - #include <mach/mfp-pxa27x.h>
-   - #include <mach/mfp-pxa300.h>
-   - #include <mach/mfp-pxa320.h>
-   - #include <mach/mfp-pxa930.h>
+   - #include "mfp-pxa25x.h"
+   - #include "mfp-pxa27x.h"
+   - #include "mfp-pxa300.h"
+   - #include "mfp-pxa320.h"
+   - #include "mfp-pxa930.h"
 
    NOTE: only one file in your <board>.c, depending on the processors used,
    because pin configuration definitions may conflict in these file (i.e.
@@ -203,20 +203,20 @@ make them effective there-after.
     1. Unified pin definitions - enum constants for all configurable pins
     2. processor-neutral bit definitions for a possible MFP configuration
 
-  - arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h
+  - arch/arm/mach-pxa/mfp-pxa3xx.h
 
   for PXA3xx specific MFPR register bit definitions and PXA3xx common pin
   configurations
 
-  - arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
+  - arch/arm/mach-pxa/mfp-pxa2xx.h
 
   for PXA2xx specific definitions and PXA25x/PXA27x common pin configurations
 
-  - arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
-    arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
-    arch/arm/mach-pxa/include/mach/mfp-pxa300.h
-    arch/arm/mach-pxa/include/mach/mfp-pxa320.h
-    arch/arm/mach-pxa/include/mach/mfp-pxa930.h
+  - arch/arm/mach-pxa/mfp-pxa25x.h
+    arch/arm/mach-pxa/mfp-pxa27x.h
+    arch/arm/mach-pxa/mfp-pxa300.h
+    arch/arm/mach-pxa/mfp-pxa320.h
+    arch/arm/mach-pxa/mfp-pxa930.h
 
   for processor specific definitions
 
diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
index c78576bb7729..11d3056dc2bd 100644
--- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
@@ -26,6 +26,10 @@ Raspberry Pi Model B+
 Required root node properties:
 compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
 
+Raspberry Pi 2 Model B
+Required root node properties:
+compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
+
 Raspberry Pi Compute Module
 Required root node properties:
 compatible = "raspberrypi,compute-module", "brcm,bcm2835";
diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt
index 6b0f49f6f499..8608a776caa7 100644
--- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt
@@ -5,4 +5,11 @@ Boards with the BCM4708 SoC shall have the following properties:
 
 Required root node property:
 
+bcm4708
 compatible = "brcm,bcm4708";
+
+bcm4709
+compatible = "brcm,bcm4709";
+
+bcm53012
+compatible = "brcm,bcm53012";
diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
new file mode 100644
index 000000000000..677ef9d9f445
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
@@ -0,0 +1,39 @@
+Broadcom Northstar Plus SoC CPU Enable Method
+---------------------------------------------
+This binding defines the enable method used for starting secondary
+CPU in the following Broadcom SoCs:
+  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
+
+The enable method is specified by defining the following required
+properties in the corresponding secondary "cpu" device tree node:
+  - enable-method = "brcm,bcm-nsp-smp";
+  - secondary-boot-reg = <...>;
+
+The secondary-boot-reg property is a u32 value that specifies the
+physical address of the register which should hold the common
+entry point for a secondary CPU. This entry is cpu node specific
+and should be added per cpu. E.g., in case of NSP (BCM58625) which
+is a dual core CPU SoC, this entry should be added to cpu1 node.
+
+
+Example:
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <0>;
+                };
+
+                cpu1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        enable-method = "brcm,bcm-nsp-smp";
+                        secondary-boot-reg = <0xffff042c>;
+                        reg = <1>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/arm/compulab-boards.txt b/Documentation/devicetree/bindings/arm/compulab-boards.txt
new file mode 100644
index 000000000000..42a10285af9c
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/compulab-boards.txt
@@ -0,0 +1,25 @@
+CompuLab SB-SOM is a multi-module baseboard capable of carrying:
+ - CM-T43
+ - CM-T54
+ - CM-QS600
+ - CL-SOM-AM57x
+ - CL-SOM-iMX7
+modules with minor modifications to the SB-SOM assembly.
+
+Required root node properties:
+    - compatible = should be "compulab,sb-som"
+
+Compulab CL-SOM-iMX7 is a miniature System-on-Module (SoM) based on
+Freescale i.MX7 ARM Cortex-A7 System-on-Chip.
+
+Required root node properties:
+    - compatible = "compulab,cl-som-imx7", "fsl,imx7d";
+
+Compulab SBC-iMX7 is a single board computer based on the
+Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with
+the CL-SOM-iMX7 System-on-Module providing most of the functions,
+and SB-SOM-iMX7 carrier board providing additional peripheral
+functions and connectors.
+
+Required root node properties:
+    - compatible = "compulab,sbc-imx7", "compulab,cl-som-imx7", "fsl,imx7d";
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index c352c11bd641..ae9be074d09f 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -191,6 +191,8 @@ nodes to be present and contain the properties described below.
                             "allwinner,sun6i-a31"
                             "allwinner,sun8i-a23"
                             "arm,psci"
+                            "arm,realview-smp"
+                            "brcm,bcm-nsp-smp"
                             "brcm,brahma-b15"
                             "marvell,armada-375-smp"
                             "marvell,armada-380-smp"
@@ -201,6 +203,7 @@ nodes to be present and contain the properties described below.
                             "qcom,gcc-msm8660"
                             "qcom,kpss-acc-v1"
                             "qcom,kpss-acc-v2"
+                            "rockchip,rk3036-smp"
                             "rockchip,rk3066-smp"
                             "ste,dbx500-smp"
 
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 34c88b0c7ab4..752a685d926f 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -131,6 +131,10 @@ Example:
 Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
 ----------------------------------------------------------------
 
+LS1043A ARMv8 based RDB Board
+Required root node properties:
+    - compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
+
 LS2080A ARMv8 based Simulator model
 Required root node properties:
     - compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
diff --git a/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt b/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt
index 5171ad8f48ff..ab0c9cdf388e 100644
--- a/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt
+++ b/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt
@@ -24,6 +24,8 @@ board. Currently known boards are:
 "buffalo,lswxl"
 "buffalo,lsxhl"
 "buffalo,lsxl"
+"cloudengines,pogo02"
+"cloudengines,pogoplugv4"
 "dlink,dns-320"
 "dlink,dns-320-a1"
 "dlink,dns-325"
diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
index 618a91994a18..54f43bc2df44 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -6,6 +6,7 @@ following property:
 Required root node property:
 
 compatible: Must contain one of
+   "mediatek,mt2701"
    "mediatek,mt6580"
    "mediatek,mt6589"
    "mediatek,mt6592"
@@ -17,6 +18,9 @@ compatible: Must contain one of
 
 Supported boards:
 
+- Evaluation board for MT2701:
+    Required root node properties:
+      - compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
 - Evaluation board for MT6580:
     Required root node properties:
       - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
index f6cd3e4192ff..aaf8d1460c4d 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
@@ -18,7 +18,7 @@ The available clocks are defined in dt-bindings/clock/mt*-clk.h.
 Also it uses the common reset controller binding from
 Documentation/devicetree/bindings/reset/reset.txt.
 The available reset outputs are defined in
-dt-bindings/reset-controller/mt*-resets.h
+dt-bindings/reset/mt*-resets.h
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
index f25b85499a6f..2f6ff86df49f 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
@@ -18,7 +18,7 @@ The available clocks are defined in dt-bindings/clock/mt*-clk.h.
 Also it uses the common reset controller binding from
 Documentation/devicetree/bindings/reset/reset.txt.
 The available reset outputs are defined in
-dt-bindings/reset-controller/mt*-resets.h
+dt-bindings/reset/mt*-resets.h
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index 9f4e5136e568..a2bd593881ca 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -138,9 +138,21 @@ Boards:
 - AM335X phyBOARD-WEGA: Single Board Computer dev kit
   compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"
 
+- AM335X CM-T335 : System On Module, built around the Sitara AM3352/4
+  compatible = "compulab,cm-t335", "ti,am33xx"
+
+- AM335X SBC-T335 : single board computer, built around the Sitara AM3352/4
+  compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx"
+
 - OMAP5 EVM : Evaluation Module
   compatible = "ti,omap5-evm", "ti,omap5"
 
+- AM437x CM-T43
+  compatible = "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"
+
+- AM437x SBC-T43
+  compatible = "compulab,am437x-sbc-t43", "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"
+
 - AM43x EPOS EVM
   compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"
 
@@ -150,6 +162,12 @@ Boards:
 - AM437x SK EVM: AM437x StarterKit Evaluation Module
   compatible = "ti,am437x-sk-evm", "ti,am4372", "ti,am43"
 
+- AM57XX CL-SOM-AM57x
+  compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
+
+- AM57XX SBC-AM57x
+  compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
+
 - DRA742 EVM:  Software Development Board for DRA742
   compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
 
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
index 8e985dd2f181..078c14fcdaaa 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
@@ -1,6 +1,10 @@
 Rockchip platforms device tree bindings
 ---------------------------------------
 
+- Kylin RK3036 board:
+    Required root node properties:
+      - compatible = "rockchip,kylin-rk3036", "rockchip,rk3036";
+
 - MarsBoard RK3066 board:
     Required root node properties:
       - compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a";
@@ -35,6 +39,11 @@ Rockchip platforms device tree bindings
     Required root node properties:
       - compatible = "netxeon,r89", "rockchip,rk3288";
 
+- Google Brain (dev-board):
+    Required root node properties:
+      - compatible = "google,veyron-brain-rev0", "google,veyron-brain",
+                     "google,veyron", "rockchip,rk3288";
+
 - Google Jaq (Haier Chromebook 11 and more):
     Required root node properties:
       - compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
@@ -49,6 +58,15 @@ Rockchip platforms device tree bindings
                      "google,veyron-jerry-rev3", "google,veyron-jerry",
                      "google,veyron", "rockchip,rk3288";
 
+- Google Mickey (Asus Chromebit CS10):
+    Required root node properties:
+      - compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7",
+                     "google,veyron-mickey-rev6", "google,veyron-mickey-rev5",
+                     "google,veyron-mickey-rev4", "google,veyron-mickey-rev3",
+                     "google,veyron-mickey-rev2", "google,veyron-mickey-rev1",
+                     "google,veyron-mickey-rev0", "google,veyron-mickey",
+                     "google,veyron", "rockchip,rk3288";
+
 - Google Minnie (Asus Chromebook Flip C100P):
     Required root node properties:
       - compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
@@ -69,6 +87,14 @@ Rockchip platforms device tree bindings
                      "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
                      "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
 
+- Rockchip RK3368 evb:
+    Required root node properties:
+      - compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368";
+
 - Rockchip R88 board:
     Required root node properties:
       - compatible = "rockchip,r88", "rockchip,rk3368";
+
+- Rockchip RK3228 Evaluation board:
+    Required root node properties:
+      - compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
index f46ca9a316a2..ccaaec6014bd 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
@@ -47,6 +47,9 @@ Required properties:
 
 - samsung,syscon-phandle Contains the PMU system controller node
                         (To access the ADC_PHY register on Exynos5250/5420/5800/3250)
+Optional properties:
+- has-touchscreen:      If present, indicates that a touchscreen is
+                        connected an usable.
 
 Note: child nodes can be added for auto probing from device tree.
 
diff --git a/Documentation/devicetree/bindings/arm/scu.txt b/Documentation/devicetree/bindings/arm/scu.txt
index c447680519bb..08a587875996 100644
--- a/Documentation/devicetree/bindings/arm/scu.txt
+++ b/Documentation/devicetree/bindings/arm/scu.txt
@@ -10,10 +10,13 @@ References:
   Revision r2p0
 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
   Revision r0p1
+- ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
+  Manial Revision r2p0
 
 - compatible : Should be:
         "arm,cortex-a9-scu"
         "arm,cortex-a5-scu"
+        "arm,arm11mp-scu"
 
 - reg : Specify the base address and the size of the SCU register window.
 
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 40bb9007cd0d..9cf67e48f222 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -27,6 +27,8 @@ SoCs:
     compatible = "renesas,r8a7793"
   - R-Car E2 (R8A77940)
     compatible = "renesas,r8a7794"
+  - R-Car H3 (R8A77950)
+    compatible = "renesas,r8a7795"
 
 
 Boards:
@@ -57,5 +59,7 @@ Boards:
     compatible = "renesas,marzen", "renesas,r8a7779"
   - Porter (M2-LCDP)
     compatible = "renesas,porter", "renesas,r8a7791"
+  - Salvator-X (RTP0RC7795SIPB0010S)
+    compatible = "renesas,salvator-x", "renesas,r8a7795";
   - SILK (RTP0RC7794LCB00011S)
     compatible = "renesas,silk", "renesas,r8a7794"
diff --git a/Documentation/devicetree/bindings/arm/technologic.txt b/Documentation/devicetree/bindings/arm/technologic.txt
new file mode 100644
index 000000000000..842298894cf0
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/technologic.txt
@@ -0,0 +1,6 @@
+Technologic Systems Platforms Device Tree Bindings
+--------------------------------------------------
+
+TS-4800 board
+Required root node properties:
+        - compatible = "technologic,imx51-ts4800", "fsl,imx51";
diff --git a/Documentation/devicetree/bindings/bus/uniphier-system-bus.txt b/Documentation/devicetree/bindings/bus/uniphier-system-bus.txt
new file mode 100644
index 000000000000..68ef80afff16
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/uniphier-system-bus.txt
@@ -0,0 +1,66 @@
+UniPhier System Bus
+
+The UniPhier System Bus is an external bus that connects on-board devices to
+the UniPhier SoC.  It is a simple (semi-)parallel bus with address, data, and
+some control signals.  It supports up to 8 banks (chip selects).
+
+Before any access to the bus, the bus controller must be configured; the bus
+controller registers provide the control for the translation from the offset
+within each bank to the CPU-viewed address.  The needed setup includes the base
+address, the size of each bank.  Optionally, some timing parameters can be
+optimized for faster bus access.
+
+Required properties:
+- compatible: should be "socionext,uniphier-system-bus".
+- reg: offset and length of the register set for the bus controller device.
+- #address-cells: should be 2.  The first cell is the bank number (chip select).
+  The second cell is the address offset within the bank.
+- #size-cells: should be 1.
+- ranges: should provide a proper address translation from the System Bus to
+  the parent bus.
+
+Note:
+The address region(s) that can be assigned for the System Bus is implementation
+defined.  Some SoCs can use 0x00000000-0x0fffffff and 0x40000000-0x4fffffff,
+while other SoCs can only use 0x40000000-0x4fffffff.  There might be additional
+limitations depending on SoCs and the boot mode.  The address translation is
+arbitrary as long as the banks are assigned in the supported address space with
+the required alignment and they do not overlap one another.
+For example, it is possible to map:
+  bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
+It is also possible to map:
+  bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
+There is no reason to stick to a particular translation mapping, but the
+"ranges" property should provide a "reasonable" default that is known to work.
+The software should initialize the bus controller according to it.
+
+Example:
+
+        system-bus {
+                compatible = "socionext,uniphier-system-bus";
+                reg = <0x58c00000 0x400>;
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges = <1 0x00000000 0x42000000 0x02000000
+                          5 0x00000000 0x46000000 0x01000000>;
+
+                ethernet@1,01f00000 {
+                        compatible = "smsc,lan9115";
+                        reg = <1 0x01f00000 0x1000>;
+                        interrupts = <0 48 4>
+                        phy-mode = "mii";
+                };
+
+                uart@5,00200000 {
+                        compatible = "ns16550a";
+                        reg = <5 0x00200000 0x20>;
+                        interrupts = <0 49 4>
+                        clock-frequency = <12288000>;
+                };
+        };
+
+In this example,
+ - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
+   mapped to 0x43f00000 of the parent bus.
+ - the UART device is connected at the offset 0x00200000 of CS5 and
+   mapped to 0x46200000 of the parent bus.
diff --git a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt b/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt
new file mode 100644
index 000000000000..8b7177cecb36
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt
@@ -0,0 +1,40 @@
+ARM System Controller ICST clocks
+
+The ICS525 and ICS307 oscillators are produced by Integrated Devices
+Technology (IDT). ARM integrated these oscillators deeply into their
+reference designs by adding special control registers that manage such
+oscillators to their system controllers.
+
+The ARM system controller contains logic to serialize and initialize
+an ICST clock request after a write to the 32 bit register at an offset
+into the system controller. Furthermore, to even be able to alter one of
+these frequencies, the system controller must first be unlocked by
+writing a special token to another offset in the system controller.
+
+The ICST oscillator must be provided inside a system controller node.
+
+Required properties:
+- lock-offset: the offset address into the system controller where the
+  unlocking register is located
+- vco-offset: the offset address into the system controller where the
+  ICST control register is located (even 32 bit address)
+- compatible: must be one of "arm,syscon-icst525" or "arm,syscon-icst307"
+- #clock-cells: must be <0>
+- clocks: parent clock, since the ICST needs a parent clock to derive its
+  frequency from, this attribute is compulsory.
+
+Example:
+
+syscon: syscon@10000000 {
+        compatible = "syscon";
+        reg = <0x10000000 0x1000>;
+
+        oscclk0: osc0@0c {
+                compatible = "arm,syscon-icst307";
+                #clock-cells = <0>;
+                lock-offset = <0x20>;
+                vco-offset = <0x0c>;
+                clocks = <&xtal24mhz>;
+        };
+        (...)
+};
diff --git a/Documentation/devicetree/bindings/clock/dove-divider-clock.txt b/Documentation/devicetree/bindings/clock/dove-divider-clock.txt
new file mode 100644
index 000000000000..e3eb0f657c5e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/dove-divider-clock.txt
@@ -0,0 +1,28 @@
+PLL divider based Dove clocks
+
+Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
+high speed clocks for a number of peripherals.  These dividers are part of
+the PMU, and thus this node should be a child of the PMU node.
+
+The following clocks are provided:
+
+ID      Clock
+-------------
+0       AXI bus clock
+1       GPU clock
+2       VMeta clock
+3       LCD clock
+
+Required properties:
+- compatible : shall be "marvell,dove-divider-clock"
+- reg : shall be the register address of the Core PLL and Clock Divider
+   Control 0 register.  This will cover that register, as well as the
+   Core PLL and Clock Divider Control 1 register.  Thus, it will have
+   a size of 8.
+- #clock-cells : from common clock binding; shall be set to 1
+
+divider_clk: core-clock@0064 {
+        compatible = "marvell,dove-divider-clock";
+        reg = <0x0064 0x8>;
+        #clock-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt b/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt
index 36c2b528245c..399e0da22348 100644
--- a/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt
@@ -2,7 +2,7 @@
 
 Required Properties:
 
-  - compatible: Must be "renesas,sh73a0-h8300-div-clock"
+  - compatible: Must be "renesas,h8300-div-clock"
 
   - clocks: Reference to the parent clocks ("extal1" and "extal2")
 
diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_hdmi.txt b/Documentation/devicetree/bindings/display/exynos/exynos_hdmi.txt
index 1fd8cf9cbfac..d474f59be6d6 100644
--- a/Documentation/devicetree/bindings/display/exynos/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/display/exynos/exynos_hdmi.txt
@@ -2,10 +2,9 @@ Device-Tree bindings for drm hdmi driver
 
 Required properties:
 - compatible: value should be one among the following:
-        1) "samsung,exynos5-hdmi" <DEPRECATED>
-        2) "samsung,exynos4210-hdmi"
-        3) "samsung,exynos4212-hdmi"
-        4) "samsung,exynos5420-hdmi"
+        1) "samsung,exynos4210-hdmi"
+        2) "samsung,exynos4212-hdmi"
+        3) "samsung,exynos5420-hdmi"
 - reg: physical base address of the hdmi and length of memory mapped
         region.
 - interrupts: interrupt number to the cpu.
diff --git a/Documentation/devicetree/bindings/display/panel/startek,startek-kd050c.txt b/Documentation/devicetree/bindings/display/panel/startek,startek-kd050c.txt
new file mode 100644
index 000000000000..70cd8d18d841
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/startek,startek-kd050c.txt
@@ -0,0 +1,4 @@
+Startek Electronic Technology Co. KD050C 5.0" WVGA TFT LCD panel
+
+Required properties:
+- compatible: should be "startek,startek-kd050c"
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index afef6a85ac51..b8e1674c7837 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -14,6 +14,7 @@ Required properties:
         "mediatek,mt6582-sysirq"
         "mediatek,mt6580-sysirq"
         "mediatek,mt6577-sysirq"
+        "mediatek,mt2701-sysirq"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Use the same format as specified by GIC in
   Documentation/devicetree/bindings/arm/gic.txt
diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
index 45c2a8094a9f..01b88f4e0d5b 100644
--- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
@@ -1,7 +1,10 @@
 * Broadcom iProc PCIe controller with the platform bus interface
 
 Required properties:
-- compatible: Must be "brcm,iproc-pcie"
+- compatible: Must be "brcm,iproc-pcie" for PAXB, or "brcm,iproc-pcie-paxc"
+  for PAXC.  PAXB-based root complex is used for external endpoint devices.
+  PAXC-based root complex is connected to emulated endpoint devices
+  internal to the ASIC
 - reg: base address and length of the PCIe controller I/O register space
 - #interrupt-cells: set to <1>
 - interrupt-map-mask and interrupt-map, standard PCI properties to define the
@@ -32,6 +35,28 @@ Optional:
 - brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to
 increase the outbound window size
 
+MSI support (optional):
+
+For older platforms without MSI integrated in the GIC, iProc PCIe core provides
+an event queue based MSI support.  The iProc MSI uses host memories to store
+MSI posted writes in the event queues
+
+- msi-parent: Link to the device node of the MSI controller.  On newer iProc
+platforms, the MSI controller may be gicv2m or gicv3-its.  On older iProc
+platforms without MSI support in its interrupt controller, one may use the
+event queue based MSI support integrated within the iProc PCIe core.
+
+When the iProc event queue based MSI is used, one needs to define the
+following properties in the MSI device node:
+- compatible: Must be "brcm,iproc-msi"
+- msi-controller: claims itself as an MSI controller
+- interrupt-parent: Link to its parent interrupt device
+- interrupts: List of interrupt IDs from its parent interrupt device
+
+Optional properties:
+- brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that
+require the interrupt enable registers to be set explicitly to enable MSI
+
 Example:
         pcie0: pcie@18012000 {
                 compatible = "brcm,iproc-pcie";
@@ -58,6 +83,19 @@ Example:
                 brcm,pcie-ob-oarr-size;
                 brcm,pcie-ob-axi-offset = <0x00000000>;
                 brcm,pcie-ob-window-size = <256>;
+
+                msi-parent = <&msi0>;
+
+                /* iProc event queue based MSI */
+                msi0: msi@18012000 {
+                        compatible = "brcm,iproc-msi";
+                        msi-controller;
+                        interrupt-parent = <&gic>;
+                        interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
+                                     <GIC_SPI 97 IRQ_TYPE_NONE>,
+                                     <GIC_SPI 98 IRQ_TYPE_NONE>,
+                                     <GIC_SPI 99 IRQ_TYPE_NONE>,
+                };
         };
 
         pcie1: pcie@18013000 {
diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
index 17c6ed9c6059..b721beacfe4d 100644
--- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
@@ -1,4 +1,4 @@
-HiSilicon PCIe host bridge DT description
+HiSilicon Hip05 and Hip06 PCIe host bridge DT description
 
 HiSilicon PCIe host controller is based on Designware PCI core.
 It shares common functions with PCIe Designware core driver and inherits
@@ -7,8 +7,8 @@ Documentation/devicetree/bindings/pci/designware-pci.txt.
 
 Additional properties are described here:
 
-Required properties:
-- compatible: Should contain "hisilicon,hip05-pcie".
+Required properties
+- compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
 - reg: Should contain rc_dbi, config registers location and length.
 - reg-names: Must include the following entries:
   "rc_dbi": controller configuration registers;
@@ -20,7 +20,7 @@ Optional properties:
 - status: Either "ok" or "disabled".
 - dma-coherent: Present if DMA operations are coherent.
 
-Example:
+Hip05 Example (note that Hip06 is the same except compatible):
         pcie@0xb0080000 {
                 compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
                 reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>;
diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
index 7fab84b33531..4e8b90e43dd8 100644
--- a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
+++ b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
@@ -8,7 +8,14 @@ OHCI and EHCI controllers.
 Required properties:
 - compatible: "renesas,pci-r8a7790" for the R8A7790 SoC;
               "renesas,pci-r8a7791" for the R8A7791 SoC;
-              "renesas,pci-r8a7794" for the R8A7794 SoC.
+              "renesas,pci-r8a7794" for the R8A7794 SoC;
+              "renesas,pci-rcar-gen2" for a generic R-Car Gen2 compatible device
+
+
+              When compatible with the generic version, nodes must list the
+              SoC-specific version corresponding to the platform first
+              followed by the generic version.
+
 - reg:  A list of physical regions to access the device: the first is
         the operational registers for the OHCI/EHCI controllers and the
         second is for the bridge configuration and control registers.
@@ -24,10 +31,15 @@ Required properties:
 - interrupt-map-mask: standard property that helps to define the interrupt
   mapping.
 
+Optional properties:
+- dma-ranges: a single range for the inbound memory region. If not supplied,
+  defaults to 1GiB at 0x40000000. Note there are hardware restrictions on the
+  allowed combinations of address and size.
+
 Example SoC configuration:
 
         pci0: pci@ee090000  {
-                compatible = "renesas,pci-r8a7790";
+                compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
                 reg = <0x0 0xee090000 0x0 0xc00>,
                       <0x0 0xee080000 0x0 0x1100>;
@@ -38,6 +50,7 @@ Example SoC configuration:
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
+                dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
                 interrupt-map-mask = <0xff00 0 0 0x7>;
                 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
                                  0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
new file mode 100644
index 000000000000..4059a6f89bc1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -0,0 +1,233 @@
+* Qualcomm PCI express root complex
+
+- compatible:
+        Usage: required
+        Value type: <stringlist>
+        Definition: Value should contain
+                        - "qcom,pcie-ipq8064" for ipq8064
+                        - "qcom,pcie-apq8064" for apq8064
+                        - "qcom,pcie-apq8084" for apq8084
+
+- reg:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: Register ranges as listed in the reg-names property
+
+- reg-names:
+        Usage: required
+        Value type: <stringlist>
+        Definition: Must include the following entries
+                        - "parf"   Qualcomm specific registers
+                        - "dbi"    Designware PCIe registers
+                        - "elbi"   External local bus interface registers
+                        - "config" PCIe configuration space
+
+- device_type:
+        Usage: required
+        Value type: <string>
+        Definition: Should be "pci". As specified in designware-pcie.txt
+
+- #address-cells:
+        Usage: required
+        Value type: <u32>
+        Definition: Should be 3. As specified in designware-pcie.txt
+
+- #size-cells:
+        Usage: required
+        Value type: <u32>
+        Definition: Should be 2. As specified in designware-pcie.txt
+
+- ranges:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: As specified in designware-pcie.txt
+
+- interrupts:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: MSI interrupt
+
+- interrupt-names:
+        Usage: required
+        Value type: <stringlist>
+        Definition: Should contain "msi"
+
+- #interrupt-cells:
+        Usage: required
+        Value type: <u32>
+        Definition: Should be 1. As specified in designware-pcie.txt
+
+- interrupt-map-mask:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: As specified in designware-pcie.txt
+
+- interrupt-map:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: As specified in designware-pcie.txt
+
+- clocks:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: List of phandle and clock specifier pairs as listed
+                    in clock-names property
+
+- clock-names:
+        Usage: required
+        Value type: <stringlist>
+        Definition: Should contain the following entries
+                        - "iface"       Configuration AHB clock
+
+- clock-names:
+        Usage: required for ipq/apq8064
+        Value type: <stringlist>
+        Definition: Should contain the following entries
+                        - "core"        Clocks the pcie hw block
+                        - "phy"         Clocks the pcie PHY block
+- clock-names:
+        Usage: required for apq8084
+        Value type: <stringlist>
+        Definition: Should contain the following entries
+                        - "aux"         Auxiliary (AUX) clock
+                        - "bus_master"  Master AXI clock
+                        - "bus_slave"   Slave AXI clock
+- resets:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: List of phandle and reset specifier pairs as listed
+                    in reset-names property
+
+- reset-names:
+        Usage: required for ipq/apq8064
+        Value type: <stringlist>
+        Definition: Should contain the following entries
+                        - "axi"  AXI reset
+                        - "ahb"  AHB reset
+                        - "por"  POR reset
+                        - "pci"  PCI reset
+                        - "phy"  PHY reset
+
+- reset-names:
+        Usage: required for apq8084
+        Value type: <stringlist>
+        Definition: Should contain the following entries
+                        - "core" Core reset
+
+- power-domains:
+        Usage: required for apq8084
+        Value type: <prop-encoded-array>
+        Definition: A phandle and power domain specifier pair to the
+                    power domain which is responsible for collapsing
+                    and restoring power to the peripheral
+
+- vdda-supply:
+        Usage: required
+        Value type: <phandle>
+        Definition: A phandle to the core analog power supply
+
+- vdda_phy-supply:
+        Usage: required for ipq/apq8064
+        Value type: <phandle>
+        Definition: A phandle to the analog power supply for PHY
+
+- vdda_refclk-supply:
+        Usage: required for ipq/apq8064
+        Value type: <phandle>
+        Definition: A phandle to the analog power supply for IC which generates
+                    reference clock
+
+- phys:
+        Usage: required for apq8084
+        Value type: <phandle>
+        Definition: List of phandle(s) as listed in phy-names property
+
+- phy-names:
+        Usage: required for apq8084
+        Value type: <stringlist>
+        Definition: Should contain "pciephy"
+
+- <name>-gpios:
+        Usage: optional
+        Value type: <prop-encoded-array>
+        Definition: List of phandle and gpio specifier pairs. Should contain
+                        - "perst-gpios" PCIe endpoint reset signal line
+                        - "wake-gpios"  PCIe endpoint wake signal line
+
+* Example for ipq/apq8064
+        pcie@1b500000 {
+                compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";
+                reg = <0x1b500000 0x1000
+                       0x1b502000 0x80
+                       0x1b600000 0x100
+                       0x0ff00000 0x100000>;
+                reg-names = "dbi", "elbi", "parf", "config";
+                device_type = "pci";
+                linux,pci-domain = <0>;
+                bus-range = <0x00 0xff>;
+                num-lanes = <1>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
+                          0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
+                interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
+                interrupt-names = "msi";
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 0x7>;
+                interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+                                <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+                                <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+                                <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+                clocks = <&gcc PCIE_A_CLK>,
+                         <&gcc PCIE_H_CLK>,
+                         <&gcc PCIE_PHY_CLK>;
+                clock-names = "core", "iface", "phy";
+                resets = <&gcc PCIE_ACLK_RESET>,
+                         <&gcc PCIE_HCLK_RESET>,
+                         <&gcc PCIE_POR_RESET>,
+                         <&gcc PCIE_PCI_RESET>,
+                         <&gcc PCIE_PHY_RESET>;
+                reset-names = "axi", "ahb", "por", "pci", "phy";
+                pinctrl-0 = <&pcie_pins_default>;
+                pinctrl-names = "default";
+        };
+
+* Example for apq8084
+        pcie0@fc520000 {
+                compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
+                reg = <0xfc520000 0x2000>,
+                      <0xff000000 0x1000>,
+                      <0xff001000 0x1000>,
+                      <0xff002000 0x2000>;
+                reg-names = "parf", "dbi", "elbi", "config";
+                device_type = "pci";
+                linux,pci-domain = <0>;
+                bus-range = <0x00 0xff>;
+                num-lanes = <1>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                ranges = <0x81000000 0 0          0xff200000 0 0x00100000   /* I/O */
+                          0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */
+                interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;
+                interrupt-names = "msi";
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 0x7>;
+                interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+                                <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+                                <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+                                <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+                clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+                         <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+                         <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+                         <&gcc GCC_PCIE_0_AUX_CLK>;
+                clock-names = "iface", "master_bus", "slave_bus", "aux";
+                resets = <&gcc GCC_PCIE_0_BCR>;
+                reset-names = "core";
+                power-domains = <&gcc PCIE0_GDSC>;
+                vdda-supply = <&pma8084_l3>;
+                phys = <&pciephy0>;
+                phy-names = "pciephy";
+                perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
+                pinctrl-0 = <&pcie0_pins_default>;
+                pinctrl-names = "default";
+        };
diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt
index 29d3b989d3b0..558fe528ae19 100644
--- a/Documentation/devicetree/bindings/pci/rcar-pci.txt
+++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt
@@ -1,8 +1,16 @@
 * Renesas RCar PCIe interface
 
 Required properties:
-- compatible: should contain one of the following
-        "renesas,pcie-r8a7779", "renesas,pcie-r8a7790", "renesas,pcie-r8a7791"
+compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
+            "renesas,pcie-r8a7790" for the R8A7790 SoC;
+            "renesas,pcie-r8a7791" for the R8A7791 SoC;
+            "renesas,pcie-r8a7795" for the R8A7795 SoC;
+            "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 compatible device.
+
+            When compatible with the generic version, nodes must list the
+            SoC-specific version corresponding to the platform first
+            followed by the generic version.
+
 - reg: base address and length of the pcie controller registers.
 - #address-cells: set to <3>
 - #size-cells: set to <2>
@@ -25,7 +33,7 @@ Example:
 SoC specific DT Entry:
 
         pcie: pcie@fe000000 {
-                compatible = "renesas,pcie-r8a7791";
+                compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
                 reg = <0 0xfe000000 0 0x80000>;
                 #address-cells = <3>;
                 #size-cells = <2>;
diff --git a/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt b/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt
index cfe1db3bb6e9..74b5bc5dd19a 100644
--- a/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt
@@ -6,7 +6,12 @@ Required properties:
 
 Examples:
 
-pwm@0x4005C000 {
+pwm@4005c000 {
         compatible = "nxp,lpc3220-pwm";
-        reg = <0x4005C000 0x8>;
+        reg = <0x4005c000 0x4>;
+};
+
+pwm@4005c004 {
+        compatible = "nxp,lpc3220-pwm";
+        reg = <0x4005c004 0x4>;
 };
diff --git a/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt b/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt
new file mode 100644
index 000000000000..5befb538db95
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt
@@ -0,0 +1,18 @@
+* OMAP PWM for dual-mode timers
+
+Required properties:
+- compatible: Shall contain "ti,omap-dmtimer-pwm".
+- ti,timers: phandle to PWM capable OMAP timer. See arm/omap/timer.txt for info
+  about these timers.
+- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
+  the cells format.
+
+Optional properties:
+- ti,prescaler: Should be a value between 0 and 7, see the timers datasheet
+
+Example:
+        pwm9: dmtimer-pwm@9 {
+                compatible = "ti,omap-dmtimer-pwm";
+                ti,timers = <&timer9>;
+                #pwm-cells = <3>;
+        };
diff --git a/Documentation/devicetree/bindings/regulator/tps65217.txt b/Documentation/devicetree/bindings/regulator/tps65217.txt
index 4f05d208c95c..d18109657da6 100644
--- a/Documentation/devicetree/bindings/regulator/tps65217.txt
+++ b/Documentation/devicetree/bindings/regulator/tps65217.txt
@@ -26,7 +26,11 @@ Example:
                 ti,pmic-shutdown-controller;
 
                 regulators {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
                         dcdc1_reg: dcdc1 {
+                                reg = <0>;
                                 regulator-min-microvolt = <900000>;
                                 regulator-max-microvolt = <1800000>;
                                 regulator-boot-on;
@@ -34,6 +38,7 @@ Example:
                         };
 
                         dcdc2_reg: dcdc2 {
+                                reg = <1>;
                                 regulator-min-microvolt = <900000>;
                                 regulator-max-microvolt = <3300000>;
                                 regulator-boot-on;
@@ -41,6 +46,7 @@ Example:
                         };
 
                         dcdc3_reg: dcc3 {
+                                reg = <2>;
                                 regulator-min-microvolt = <900000>;
                                 regulator-max-microvolt = <1500000>;
                                 regulator-boot-on;
@@ -48,6 +54,7 @@ Example:
                         };
 
                         ldo1_reg: ldo1 {
+                                reg = <3>;
                                 regulator-min-microvolt = <1000000>;
                                 regulator-max-microvolt = <3300000>;
                                 regulator-boot-on;
@@ -55,6 +62,7 @@ Example:
                         };
 
                         ldo2_reg: ldo2 {
+                                reg = <4>;
                                 regulator-min-microvolt = <900000>;
                                 regulator-max-microvolt = <3300000>;
                                 regulator-boot-on;
@@ -62,6 +70,7 @@ Example:
                         };
 
                         ldo3_reg: ldo3 {
+                                reg = <5>;
                                 regulator-min-microvolt = <1800000>;
                                 regulator-max-microvolt = <3300000>;
                                 regulator-boot-on;
@@ -69,6 +78,7 @@ Example:
                         };
 
                         ldo4_reg: ldo4 {
+                                reg = <6>;
                                 regulator-min-microvolt = <1800000>;
                                 regulator-max-microvolt = <3300000>;
                                 regulator-boot-on;
diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
new file mode 100644
index 000000000000..e0b185a944ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
@@ -0,0 +1,34 @@
+Hisilicon System Reset Controller
+======================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+The reset controller registers are part of the system-ctl block on
+hi6220 SoC.
+
+Required properties:
+- compatible: may be "hisilicon,hi6220-sysctrl"
+- reg: should be register base and length as documented in the
+  datasheet
+- #reset-cells: 1, see below
+
+Example:
+sys_ctrl: sys_ctrl@f7030000 {
+        compatible = "hisilicon,hi6220-sysctrl", "syscon";
+        reg = <0x0 0xf7030000 0x0 0x2000>;
+        #clock-cells = <1>;
+        #reset-cells = <1>;
+};
+
+Specifying reset lines connected to IP modules
+==============================================
+example:
+
+        uart1: serial@..... {
+                ...
+                resets = <&sys_ctrl PERIPH_RSTEN3_UART1>;
+                ...
+        };
+
+The index could be found in <dt-bindings/reset/hisi,hi6220-resets.h>.
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 2d47add34765..a833a016f656 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -2,15 +2,15 @@
 
 Required properties:
 - compatible should contain:
-  * "mediatek,mt8135-uart" for MT8135 compatible UARTS
+  * "mediatek,mt2701-uart" for MT2701 compatible UARTS
+  * "mediatek,mt6580-uart" for MT6580 compatible UARTS
+  * "mediatek,mt6582-uart" for MT6582 compatible UARTS
+  * "mediatek,mt6589-uart" for MT6589 compatible UARTS
+  * "mediatek,mt6795-uart" for MT6795 compatible UARTS
   * "mediatek,mt8127-uart" for MT8127 compatible UARTS
+  * "mediatek,mt8135-uart" for MT8135 compatible UARTS
   * "mediatek,mt8173-uart" for MT8173 compatible UARTS
-  * "mediatek,mt6795-uart" for MT6795 compatible UARTS
-  * "mediatek,mt6589-uart" for MT6589 compatible UARTS
-  * "mediatek,mt6582-uart" for MT6582 compatible UARTS
-  * "mediatek,mt6580-uart" for MT6580 compatible UARTS
-  * "mediatek,mt6577-uart" for all compatible UARTS (MT8173, MT6795,
-        MT6589, MT6582, MT6580, MT6577)
+  * "mediatek,mt6577-uart" for MT6577 and all of the above
 
 - reg: The base address of the UART register bank.
 
diff --git a/Documentation/devicetree/bindings/soc/bcm/raspberrypi,bcm2835-power.txt b/Documentation/devicetree/bindings/soc/bcm/raspberrypi,bcm2835-power.txt
new file mode 100644
index 000000000000..30942cf7992b
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/bcm/raspberrypi,bcm2835-power.txt
@@ -0,0 +1,47 @@
+Raspberry Pi power domain driver
+
+Required properties:
+
+- compatible:           Should be "raspberrypi,bcm2835-power".
+- firmware:             Reference to the RPi firmware device node.
+- #power-domain-cells:  Should be <1>, we providing multiple power domains.
+
+The valid defines for power domain are:
+
+ RPI_POWER_DOMAIN_I2C0
+ RPI_POWER_DOMAIN_I2C1
+ RPI_POWER_DOMAIN_I2C2
+ RPI_POWER_DOMAIN_VIDEO_SCALER
+ RPI_POWER_DOMAIN_VPU1
+ RPI_POWER_DOMAIN_HDMI
+ RPI_POWER_DOMAIN_USB
+ RPI_POWER_DOMAIN_VEC
+ RPI_POWER_DOMAIN_JPEG
+ RPI_POWER_DOMAIN_H264
+ RPI_POWER_DOMAIN_V3D
+ RPI_POWER_DOMAIN_ISP
+ RPI_POWER_DOMAIN_UNICAM0
+ RPI_POWER_DOMAIN_UNICAM1
+ RPI_POWER_DOMAIN_CCP2RX
+ RPI_POWER_DOMAIN_CSI2
+ RPI_POWER_DOMAIN_CPI
+ RPI_POWER_DOMAIN_DSI0
+ RPI_POWER_DOMAIN_DSI1
+ RPI_POWER_DOMAIN_TRANSPOSER
+ RPI_POWER_DOMAIN_CCP2TX
+ RPI_POWER_DOMAIN_CDP
+ RPI_POWER_DOMAIN_ARM
+
+Example:
+
+power: power {
+        compatible = "raspberrypi,bcm2835-power";
+        firmware = <&firmware>;
+        #power-domain-cells = <1>;
+};
+
+Example for using power domain:
+
+&usb {
+       power-domains = <&power RPI_POWER_DOMAIN_USB>;
+};
diff --git a/Documentation/devicetree/bindings/soc/dove/pmu.txt b/Documentation/devicetree/bindings/soc/dove/pmu.txt
new file mode 100644
index 000000000000..edd40b796b74
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/dove/pmu.txt
@@ -0,0 +1,56 @@
+Device Tree bindings for Marvell PMU
+
+Required properties:
+ - compatible: value should be "marvell,dove-pmu".
+    May also include "simple-bus" if there are child devices, in which
+    case the ranges node is required.
+ - reg: two base addresses and sizes of the PM controller and PMU.
+ - interrupts: single interrupt number for the PMU interrupt
+ - interrupt-controller: must be specified as the PMU itself is an
+    interrupt controller.
+ - #interrupt-cells: must be 1.
+ - #reset-cells: must be 1.
+ - domains: sub-node containing domain descriptions
+
+Optional properties:
+ - ranges: defines the address mapping for child devices, as per the
+   standard property of this name.  Required when compatible includes
+   "simple-bus".
+
+Power domain descriptions are listed as child nodes of the "domains"
+sub-node.  Each domain has the following properties:
+
+Required properties:
+ - #power-domain-cells: must be 0.
+
+Optional properties:
+ - marvell,pmu_pwr_mask: specifies the mask value for PMU power register
+ - marvell,pmu_iso_mask: specifies the mask value for PMU isolation register
+ - resets: points to the reset manager (PMU node) and reset index.
+
+Example:
+
+        pmu: power-management@d0000 {
+                compatible = "marvell,dove-pmu";
+                reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
+                interrupts = <33>;
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                #reset-cells = <1>;
+
+                domains {
+                        vpu_domain: vpu-domain {
+                                #power-domain-cells = <0>;
+                                marvell,pmu_pwr_mask = <0x00000008>;
+                                marvell,pmu_iso_mask = <0x00000001>;
+                                resets = <&pmu 16>;
+                        };
+
+                        gpu_domain: gpu-domain {
+                                #power-domain-cells = <0>;
+                                marvell,pmu_pwr_mask = <0x00000004>;
+                                marvell,pmu_iso_mask = <0x00000002>;
+                                resets = <&pmu 18>;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index a6c8afc8385a..e8f15e34027f 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -21,6 +21,18 @@ Required properties:
                       These are the clocks which hardware needs to be enabled
                       before enabling certain power domains.
 
+Optional properties:
+- vdec-supply: Power supply for the vdec power domain
+- venc-supply: Power supply for the venc power domain
+- isp-supply: Power supply for the isp power domain
+- mm-supply: Power supply for the mm power domain
+- venc_lt-supply: Power supply for the venc_lt power domain
+- audio-supply: Power supply for the audio power domain
+- usb-supply: Power supply for the usb power domain
+- mfg_async-supply: Power supply for the mfg_async power domain
+- mfg_2d-supply: Power supply for the mfg_2d power domain
+- mfg-supply: Power supply for the mfg power domain
+
 Example:
 
         scpsys: scpsys@10006000 {
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt
new file mode 100644
index 000000000000..5cc82b8353d8
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt
@@ -0,0 +1,104 @@
+Qualcomm Shared Memory Point 2 Point binding
+
+The Shared Memory Point to Point (SMP2P) protocol facilitates communication of
+a single 32-bit value between two processors.  Each value has a single writer
+(the local side) and a single reader (the remote side).  Values are uniquely
+identified in the system by the directed edge (local processor ID to remote
+processor ID) and a string identifier.
+
+- compatible:
+        Usage: required
+        Value type: <string>
+        Definition: must be one of:
+                    "qcom,smp2p"
+
+- interrupts:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: one entry specifying the smp2p notification interrupt
+
+- qcom,ipc:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: three entries specifying the outgoing ipc bit used for
+                    signaling the remote end of the smp2p edge:
+                    - phandle to a syscon node representing the apcs registers
+                    - u32 representing offset to the register within the syscon
+                    - u32 representing the ipc bit within the register
+
+- qcom,smem:
+        Usage: required
+        Value type: <u32 array>
+        Definition: two identifiers of the inbound and outbound smem items used
+                    for this edge
+
+- qcom,local-pid:
+        Usage: required
+        Value type: <u32>
+        Definition: specifies the identfier of the local endpoint of this edge
+
+- qcom,remote-pid:
+        Usage: required
+        Value type: <u32>
+        Definition: specifies the identfier of the remote endpoint of this edge
+
+= SUBNODES
+Each SMP2P pair contain a set of inbound and outbound entries, these are
+described in subnodes of the smp2p device node. The node names are not
+important.
+
+- qcom,entry-name:
+        Usage: required
+        Value type: <string>
+        Definition: specifies the name of this entry, for inbound entries this
+                    will be used to match against the remotely allocated entry
+                    and for outbound entries this name is used for allocating
+                    entries
+
+- interrupt-controller:
+        Usage: required for incoming entries
+        Value type: <empty>
+        Definition: marks the entry as inbound; the node should be specified
+                    as a two cell interrupt-controller as defined in
+                    "../interrupt-controller/interrupts.txt"
+                    If not specified this node will denote the outgoing entry
+
+- #interrupt-cells:
+        Usage: required for incoming entries
+        Value type: <u32>
+        Definition: must be 2 - denoting the bit in the entry and IRQ flags
+
+- #qcom,state-cells:
+        Usage: required for outgoing entries
+        Value type: <u32>
+        Definition: must be 1 - denoting the bit in the entry
+
+= EXAMPLE
+The following example shows the SMP2P setup with the wireless processor,
+defined from the 8974 apps processor's point-of-view. It encompasses one
+inbound and one outbound entry:
+
+wcnss-smp2p {
+        compatible = "qcom,smp2p";
+        qcom,smem = <431>, <451>;
+
+        interrupts = <0 143 1>;
+
+        qcom,ipc = <&apcs 8 18>;
+
+        qcom,local-pid = <0>;
+        qcom,remote-pid = <4>;
+
+        wcnss_smp2p_out: master-kernel {
+                qcom,entry-name = "master-kernel";
+
+                #qcom,state-cells = <1>;
+        };
+
+        wcnss_smp2p_in: slave-kernel {
+                qcom,entry-name = "slave-kernel";
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt
new file mode 100644
index 000000000000..a6634c70850d
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt
@@ -0,0 +1,104 @@
+Qualcomm Shared Memory State Machine
+
+The Shared Memory State Machine facilitates broadcasting of single bit state
+information between the processors in a Qualcomm SoC. Each processor is
+assigned 32 bits of state that can be modified. A processor can through a
+matrix of bitmaps signal subscription of notifications upon changes to a
+certain bit owned by a certain remote processor.
+
+- compatible:
+        Usage: required
+        Value type: <string>
+        Definition: must be one of:
+                    "qcom,smsm"
+
+- qcom,ipc-N:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: three entries specifying the outgoing ipc bit used for
+                    signaling the N:th remote processor
+                    - phandle to a syscon node representing the apcs registers
+                    - u32 representing offset to the register within the syscon
+                    - u32 representing the ipc bit within the register
+
+- qcom,local-host:
+        Usage: optional
+        Value type: <u32>
+        Definition: identifier of the local processor in the list of hosts, or
+                    in other words specifier of the column in the subscription
+                    matrix representing the local processor
+                    defaults to host 0
+
+- #address-cells:
+        Usage: required
+        Value type: <u32>
+        Definition: must be 1
+
+- #size-cells:
+        Usage: required
+        Value type: <u32>
+        Definition: must be 0
+
+= SUBNODES
+Each processor's state bits are described by a subnode of the smsm device node.
+Nodes can either be flagged as an interrupt-controller to denote a remote
+processor's state bits or the local processors bits.  The node names are not
+important.
+
+- reg:
+        Usage: required
+        Value type: <u32>
+        Definition: specifies the offset, in words, of the first bit for this
+                    entry
+
+- #qcom,state-cells:
+        Usage: required for local entry
+        Value type: <u32>
+        Definition: must be 1 - denotes bit number
+
+- interrupt-controller:
+        Usage: required for remote entries
+        Value type: <empty>
+        Definition: marks the entry as a interrupt-controller and the state bits
+                    to belong to a remote processor
+
+- #interrupt-cells:
+        Usage: required for remote entries
+        Value type: <u32>
+        Definition: must be 2 - denotes bit number and IRQ flags
+
+- interrupts:
+        Usage: required for remote entries
+        Value type: <prop-encoded-array>
+        Definition: one entry specifying remote IRQ used by the remote processor
+                    to signal changes of its state bits
+
+
+= EXAMPLE
+The following example shows the SMEM setup for controlling properties of the
+wireless processor, defined from the 8974 apps processor's point-of-view. It
+encompasses one outbound entry and the outgoing interrupt for the wireless
+processor.
+
+smsm {
+        compatible = "qcom,smsm";
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        qcom,ipc-3 = <&apcs 8 19>;
+
+        apps_smsm: apps@0 {
+                reg = <0>;
+
+                #qcom,state-cells = <1>;
+        };
+
+        wcnss_smsm: wcnss@7 {
+                reg = <7>;
+                interrupts = <0 144 1>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/soc/ti/wkup_m3_ipc.txt b/Documentation/devicetree/bindings/soc/ti/wkup_m3_ipc.txt
new file mode 100644
index 000000000000..401550487ed6
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/ti/wkup_m3_ipc.txt
@@ -0,0 +1,57 @@
+Wakeup M3 IPC Driver
+=====================
+
+The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
+(commonly referred to as Wakeup M3 or CM3) to help with various low power tasks
+that cannot be controlled from the MPU, like suspend/resume and certain deep
+C-states for CPU Idle. Once the wkup_m3_ipc driver uses the wkup_m3_rproc driver
+to boot the wkup_m3, it handles communication with the CM3 using IPC registers
+present in the SoC's control module and a mailbox. The wkup_m3_ipc exposes an
+API to allow the SoC PM code to execute specific PM tasks.
+
+Wkup M3 Device Node:
+====================
+A wkup_m3_ipc device node is used to represent the IPC registers within an
+SoC.
+
+Required properties:
+--------------------
+- compatible:           Should be,
+                                "ti,am3352-wkup-m3-ipc" for AM33xx SoCs
+                                "ti,am4372-wkup-m3-ipc" for AM43xx SoCs
+- reg:                  Contains the IPC register address space to communicate
+                        with the Wakeup M3 processor
+- interrupts:           Contains the interrupt information for the wkup_m3
+                        interrupt that signals the MPU.
+- ti,rproc:             phandle to the wkup_m3 rproc node so the IPC driver
+                        can boot it.
+- mboxes:               phandles used by IPC framework to get correct mbox
+                        channel for communication. Must point to appropriate
+                        mbox_wkupm3 child node.
+
+Example:
+--------
+/* AM33xx */
+        l4_wkup: l4_wkup@44c00000 {
+                ...
+
+                scm: scm@210000 {
+                        compatible = "ti,am3-scm", "simple-bus";
+                        reg = <0x210000 0x2000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x210000 0x2000>;
+
+                        ...
+
+                        wkup_m3_ipc: wkup_m3_ipc@1324 {
+                                compatible = "ti,am3352-wkup-m3-ipc";
+                                reg = <0x1324 0x24>;
+                                interrupts = <78>;
+                                ti,rproc = <&wkup_m3>;
+                                mboxes = <&mailbox &mbox_wkupm3>;
+                        };
+
+                        ...
+                };
+        };
diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt b/Documentation/devicetree/bindings/spi/ti_qspi.txt
index 601a360531a5..cc8304aa64ac 100644
--- a/Documentation/devicetree/bindings/spi/ti_qspi.txt
+++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
@@ -15,14 +15,32 @@ Recommended properties:
 - spi-max-frequency: Definition as per
                      Documentation/devicetree/bindings/spi/spi-bus.txt
 
+Optional properties:
+- syscon-chipselects: Handle to system control region contains QSPI
+                      chipselect register and offset of that register.
+
 Example:
 
+For am4372:
 qspi: qspi@4b300000 {
-        compatible = "ti,dra7xxx-qspi";
-        reg = <0x47900000 0x100>, <0x30000000 0x3ffffff>;
+        compatible = "ti,am4372-qspi";
+        reg = <0x47900000 0x100>, <0x30000000 0x4000000>;
         reg-names = "qspi_base", "qspi_mmap";
         #address-cells = <1>;
         #size-cells = <0>;
         spi-max-frequency = <25000000>;
         ti,hwmods = "qspi";
 };
+
+For dra7xx:
+qspi: qspi@4b300000 {
+        compatible = "ti,dra7xxx-qspi";
+        reg = <0x4b300000 0x100>,
+              <0x5c000000 0x4000000>,
+        reg-names = "qspi_base", "qspi_mmap";
+        syscon-chipselects = <&scm_conf 0x558>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        spi-max-frequency = <48000000>;
+        ti,hwmods = "qspi";
+};
diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
index 64083bc5633c..8ff54eb464dc 100644
--- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
+++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
@@ -3,6 +3,7 @@ Mediatek MT6577, MT6572 and MT6589 Timers
 
 Required properties:
 - compatible should contain:
+        * "mediatek,mt2701-timer" for MT2701 compatible timers
         * "mediatek,mt6580-timer" for MT6580 compatible timers
         * "mediatek,mt6589-timer" for MT6589 compatible timers
         * "mediatek,mt8127-timer" for MT8127 compatible timers
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 084439d35747..72e2c5a2b327 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -124,6 +124,7 @@ jedec	JEDEC Solid State Technology Association
 karo    Ka-Ro electronics GmbH
 keymile Keymile GmbH
 kinetic Kinetic Technologies
+kosagi  Sutajio Ko-Usagi PTE Ltd.
 kyo     Kyocera Corporation
 lacie   LaCie
 lantiq  Lantiq Semiconductor
@@ -222,11 +223,13 @@ sony	Sony Corporation
 spansion        Spansion Inc.
 sprd    Spreadtrum Communications Inc.
 st      STMicroelectronics
+startek Startek
 ste     ST-Ericsson
 stericsson      ST-Ericsson
 synology        Synology, Inc.
 tbs     TBS Technologies
 tcl     Toby Churchill Ltd.
+technologic     Technologic Systems
 thine   THine Electronics, Inc.
 ti      Texas Instruments
 tlm     Trusted Logic Mobility
diff --git a/Documentation/devicetree/bindings/watchdog/meson6-wdt.txt b/Documentation/devicetree/bindings/watchdog/meson-wdt.txt
index 9200fc2d508c..ae70185d96e6 100644
--- a/Documentation/devicetree/bindings/watchdog/meson6-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/meson-wdt.txt
@@ -2,7 +2,7 @@ Meson SoCs Watchdog timer
 
 Required properties:
 
-- compatible : should be "amlogic,meson6-wdt"
+- compatible : should be "amlogic,meson6-wdt" or "amlogic,meson8b-wdt"
 - reg : Specifies base physical address and size of the registers.
 
 Example:
diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index af9eb5b8a253..6a00939a059a 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -2,7 +2,11 @@ Mediatek SoCs Watchdog timer
 
 Required properties:
 
-- compatible : should be "mediatek,mt6589-wdt"
+- compatible should contain:
+        * "mediatek,mt2701-wdt" for MT2701 compatible watchdog timers
+        * "mediatek,mt6589-wdt" for all compatible watchdog timers (MT2701,
+                MT6589)
+
 - reg : Specifies base physical address and size of the registers.
 
 Example:
diff --git a/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt b/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
new file mode 100644
index 000000000000..edc4f0ea54a3
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
@@ -0,0 +1,31 @@
+* ARM SP805 Watchdog Timer (WDT) Controller
+
+SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that
+can be used to identify the peripheral type, vendor, and revision.
+This value can be used for driver matching.
+
+As SP805 WDT is a primecell IP, it follows the base bindings specified in
+'arm/primecell.txt'
+
+Required properties:
+- compatible : Should be "arm,sp805-wdt", "arm,primecell"
+- reg : Base address and size of the watchdog timer registers.
+- clocks : From common clock binding.
+           First clock is PCLK and the second is WDOGCLK.
+           WDOGCLK can be equal to or be a sub-multiple of the PCLK frequency.
+- clock-names : From common clock binding.
+                Shall be "apb_pclk" for first clock and "wdog_clk" for the
+                second one.
+
+Optional properties:
+- interrupts : Should specify WDT interrupt number.
+
+Examples:
+
+                cluster1_core0_watchdog: wdt@c000000 {
+                        compatible = "arm,sp805-wdt", "arm,primecell";
+                        reg = <0x0 0xc000000 0x0 0x1000>;
+                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                        clock-names = "apb_pclk", "wdog_clk";
+                };
+