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diff --git a/Documentation/devicetree/bindings/display/msm/edp.txt b/Documentation/devicetree/bindings/display/msm/edp.txt
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+Qualcomm Technologies Inc. adreno/snapdragon eDP output
+
+Required properties:
+- compatible:
+  * "qcom,mdss-edp"
+- reg: Physical base address and length of the registers of controller and PLL
+- reg-names: The names of register regions. The following regions are required:
+  * "edp"
+  * "pll_base"
+- interrupts: The interrupt signal from the eDP block.
+- power-domains: Should be <&mmcc MDSS_GDSC>.
+- clocks: device clocks
+  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
+- clock-names: the following clocks are required:
+  * "core_clk"
+  * "iface_clk"
+  * "mdp_core_clk"
+  * "pixel_clk"
+  * "link_clk"
+- #clock-cells: The value should be 1.
+- vdda-supply: phandle to vdda regulator device node
+- lvl-vdd-supply: phandle to regulator device node which is used to supply power
+  to HPD receiving chip
+- panel-en-gpios: GPIO pin to supply power to panel.
+- panel-hpd-gpios: GPIO pin used for eDP hpd.
+
+
+Optional properties:
+- interrupt-parent: phandle to the MDP block if the interrupt signal is routed
+  through MDP block
+
+Example:
+        mdss_edp: qcom,mdss_edp@fd923400 {
+                        compatible = "qcom,mdss-edp";
+                        reg-names =
+                                "edp",
+                                "pll_base";
+                        reg =   <0xfd923400 0x700>,
+                                <0xfd923a00 0xd4>;
+                        interrupt-parent = <&mdss_mdp>;
+                        interrupts = <12 0>;
+                        power-domains = <&mmcc MDSS_GDSC>;
+                        clock-names =
+                                "core_clk",
+                                "pixel_clk",
+                                "iface_clk",
+                                "link_clk",
+                                "mdp_core_clk";
+                        clocks =
+                                <&mmcc MDSS_EDPAUX_CLK>,
+                                <&mmcc MDSS_EDPPIXEL_CLK>,
+                                <&mmcc MDSS_AHB_CLK>,
+                                <&mmcc MDSS_EDPLINK_CLK>,
+                                <&mmcc MDSS_MDP_CLK>;
+                        #clock-cells = <1>;
+                        vdda-supply = <&pma8084_l12>;
+                        lvl-vdd-supply = <&lvl_vreg>;
+                        panel-en-gpios = <&tlmm 137 0>;
+                        panel-hpd-gpios = <&tlmm 103 0>;
+        };