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-rw-r--r--arch/xtensa/Kconfig17
-rw-r--r--arch/xtensa/Makefile2
-rw-r--r--arch/xtensa/boot/dts/kc705.dts2
-rw-r--r--arch/xtensa/boot/dts/xtfpga.dtsi8
-rw-r--r--arch/xtensa/include/asm/hw_breakpoint.h58
-rw-r--r--arch/xtensa/include/asm/io.h16
-rw-r--r--arch/xtensa/include/asm/irqflags.h1
-rw-r--r--arch/xtensa/include/asm/processor.h21
-rw-r--r--arch/xtensa/include/asm/regs.h3
-rw-r--r--arch/xtensa/include/asm/thread_info.h1
-rw-r--r--arch/xtensa/include/asm/timex.h9
-rw-r--r--arch/xtensa/include/asm/traps.h17
-rw-r--r--arch/xtensa/include/uapi/asm/ptrace.h2
-rw-r--r--arch/xtensa/kernel/Makefile2
-rw-r--r--arch/xtensa/kernel/asm-offsets.c12
-rw-r--r--arch/xtensa/kernel/entry.S90
-rw-r--r--arch/xtensa/kernel/head.S7
-rw-r--r--arch/xtensa/kernel/hw_breakpoint.c317
-rw-r--r--arch/xtensa/kernel/process.c5
-rw-r--r--arch/xtensa/kernel/ptrace.c164
-rw-r--r--arch/xtensa/kernel/traps.c69
-rw-r--r--arch/xtensa/kernel/vectors.S4
-rw-r--r--arch/xtensa/mm/Makefile2
-rw-r--r--arch/xtensa/mm/cache.c8
-rw-r--r--arch/xtensa/mm/ioremap.c68
-rw-r--r--arch/xtensa/platforms/iss/console.c10
-rw-r--r--arch/xtensa/platforms/xtfpga/setup.c3
-rw-r--r--arch/xtensa/variants/test_kc705_hifi/include/variant/core.h531
-rw-r--r--arch/xtensa/variants/test_kc705_hifi/include/variant/tie-asm.h328
-rw-r--r--arch/xtensa/variants/test_kc705_hifi/include/variant/tie.h189
-rw-r--r--arch/xtensa/variants/test_mmuhifi_c3/include/variant/core.h383
-rw-r--r--arch/xtensa/variants/test_mmuhifi_c3/include/variant/tie-asm.h182
-rw-r--r--arch/xtensa/variants/test_mmuhifi_c3/include/variant/tie.h140
33 files changed, 2593 insertions, 78 deletions
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 7e9464b0fc00..e832d3e9835e 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -17,6 +17,7 @@ config XTENSA
17 select HAVE_DMA_API_DEBUG 17 select HAVE_DMA_API_DEBUG
18 select HAVE_FUNCTION_TRACER 18 select HAVE_FUNCTION_TRACER
19 select HAVE_FUTEX_CMPXCHG if !MMU 19 select HAVE_FUTEX_CMPXCHG if !MMU
20 select HAVE_HW_BREAKPOINT if PERF_EVENTS
20 select HAVE_IRQ_TIME_ACCOUNTING 21 select HAVE_IRQ_TIME_ACCOUNTING
21 select HAVE_OPROFILE 22 select HAVE_OPROFILE
22 select HAVE_PERF_EVENTS 23 select HAVE_PERF_EVENTS
@@ -138,6 +139,22 @@ config XTENSA_VARIANT_HAVE_PERF_EVENTS
138 139
139 If unsure, say N. 140 If unsure, say N.
140 141
142config XTENSA_FAKE_NMI
143 bool "Treat PMM IRQ as NMI"
144 depends on XTENSA_VARIANT_HAVE_PERF_EVENTS
145 default n
146 help
147 If PMM IRQ is the only IRQ at EXCM level it is safe to
148 treat it as NMI, which improves accuracy of profiling.
149
150 If there are other interrupts at or above PMM IRQ priority level
151 but not above the EXCM level, PMM IRQ still may be treated as NMI,
152 but only if these IRQs are not used. There will be a build warning
153 saying that this is not safe, and a bugcheck if one of these IRQs
154 actually fire.
155
156 If unsure, say N.
157
141config XTENSA_UNALIGNED_USER 158config XTENSA_UNALIGNED_USER
142 bool "Unaligned memory access in use space" 159 bool "Unaligned memory access in use space"
143 help 160 help
diff --git a/arch/xtensa/Makefile b/arch/xtensa/Makefile
index 709b5748a2d7..e54189427b31 100644
--- a/arch/xtensa/Makefile
+++ b/arch/xtensa/Makefile
@@ -53,9 +53,11 @@ endif
53 53
54ifeq ($(shell echo __XTENSA_EB__ | $(CC) -E - | grep -v "\#"),1) 54ifeq ($(shell echo __XTENSA_EB__ | $(CC) -E - | grep -v "\#"),1)
55CHECKFLAGS += -D__XTENSA_EB__ 55CHECKFLAGS += -D__XTENSA_EB__
56KBUILD_CPPFLAGS += -DCONFIG_CPU_BIG_ENDIAN
56endif 57endif
57ifeq ($(shell echo __XTENSA_EL__ | $(CC) -E - | grep -v "\#"),1) 58ifeq ($(shell echo __XTENSA_EL__ | $(CC) -E - | grep -v "\#"),1)
58CHECKFLAGS += -D__XTENSA_EL__ 59CHECKFLAGS += -D__XTENSA_EL__
60KBUILD_CPPFLAGS += -DCONFIG_CPU_LITTLE_ENDIAN
59endif 61endif
60 62
61vardirs := $(patsubst %,arch/xtensa/variants/%/,$(variant-y)) 63vardirs := $(patsubst %,arch/xtensa/variants/%/,$(variant-y))
diff --git a/arch/xtensa/boot/dts/kc705.dts b/arch/xtensa/boot/dts/kc705.dts
index c4d17a34ab86..b1f4ee8c9a22 100644
--- a/arch/xtensa/boot/dts/kc705.dts
+++ b/arch/xtensa/boot/dts/kc705.dts
@@ -5,7 +5,7 @@
5/ { 5/ {
6 compatible = "cdns,xtensa-kc705"; 6 compatible = "cdns,xtensa-kc705";
7 chosen { 7 chosen {
8 bootargs = "earlycon=uart8250,mmio32,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug memmap=0x38000000"; 8 bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug memmap=0x38000000";
9 }; 9 };
10 memory@0 { 10 memory@0 {
11 device_type = "memory"; 11 device_type = "memory";
diff --git a/arch/xtensa/boot/dts/xtfpga.dtsi b/arch/xtensa/boot/dts/xtfpga.dtsi
index cd0b9e34adc8..cd45f9c2c448 100644
--- a/arch/xtensa/boot/dts/xtfpga.dtsi
+++ b/arch/xtensa/boot/dts/xtfpga.dtsi
@@ -5,7 +5,7 @@
5 interrupt-parent = <&pic>; 5 interrupt-parent = <&pic>;
6 6
7 chosen { 7 chosen {
8 bootargs = "earlycon=uart8250,mmio32,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug"; 8 bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
9 }; 9 };
10 10
11 memory@0 { 11 memory@0 {
@@ -60,6 +60,8 @@
60 no-loopback-test; 60 no-loopback-test;
61 reg = <0x0d050020 0x20>; 61 reg = <0x0d050020 0x20>;
62 reg-shift = <2>; 62 reg-shift = <2>;
63 reg-io-width = <4>;
64 native-endian;
63 interrupts = <0 1>; /* external irq 0 */ 65 interrupts = <0 1>; /* external irq 0 */
64 clocks = <&osc>; 66 clocks = <&osc>;
65 }; 67 };
@@ -67,6 +69,7 @@
67 enet0: ethoc@0d030000 { 69 enet0: ethoc@0d030000 {
68 compatible = "opencores,ethoc"; 70 compatible = "opencores,ethoc";
69 reg = <0x0d030000 0x4000 0x0d800000 0x4000>; 71 reg = <0x0d030000 0x4000 0x0d800000 0x4000>;
72 native-endian;
70 interrupts = <1 1>; /* external irq 1 */ 73 interrupts = <1 1>; /* external irq 1 */
71 local-mac-address = [00 50 c2 13 6f 00]; 74 local-mac-address = [00 50 c2 13 6f 00];
72 clocks = <&osc>; 75 clocks = <&osc>;
@@ -86,7 +89,8 @@
86 #size-cells = <0>; 89 #size-cells = <0>;
87 reg = <0x0d090000 0x20>; 90 reg = <0x0d090000 0x20>;
88 reg-shift = <2>; 91 reg-shift = <2>;
89 reg-io-width = <1>; 92 reg-io-width = <4>;
93 native-endian;
90 interrupts = <4 1>; 94 interrupts = <4 1>;
91 clocks = <&osc>; 95 clocks = <&osc>;
92 96
diff --git a/arch/xtensa/include/asm/hw_breakpoint.h b/arch/xtensa/include/asm/hw_breakpoint.h
new file mode 100644
index 000000000000..dbe3053b284a
--- /dev/null
+++ b/arch/xtensa/include/asm/hw_breakpoint.h
@@ -0,0 +1,58 @@
1/*
2 * Xtensa hardware breakpoints/watchpoints handling functions
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2016 Cadence Design Systems Inc.
9 */
10
11#ifndef __ASM_XTENSA_HW_BREAKPOINT_H
12#define __ASM_XTENSA_HW_BREAKPOINT_H
13
14#ifdef CONFIG_HAVE_HW_BREAKPOINT
15
16#include <linux/kdebug.h>
17#include <linux/types.h>
18#include <uapi/linux/hw_breakpoint.h>
19
20/* Breakpoint */
21#define XTENSA_BREAKPOINT_EXECUTE 0
22
23/* Watchpoints */
24#define XTENSA_BREAKPOINT_LOAD 1
25#define XTENSA_BREAKPOINT_STORE 2
26
27struct arch_hw_breakpoint {
28 unsigned long address;
29 u16 len;
30 u16 type;
31};
32
33struct perf_event;
34struct pt_regs;
35struct task_struct;
36
37int hw_breakpoint_slots(int type);
38int arch_check_bp_in_kernelspace(struct perf_event *bp);
39int arch_validate_hwbkpt_settings(struct perf_event *bp);
40int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
41 unsigned long val, void *data);
42
43int arch_install_hw_breakpoint(struct perf_event *bp);
44void arch_uninstall_hw_breakpoint(struct perf_event *bp);
45void hw_breakpoint_pmu_read(struct perf_event *bp);
46int check_hw_breakpoint(struct pt_regs *regs);
47void clear_ptrace_hw_breakpoint(struct task_struct *tsk);
48
49#else
50
51struct task_struct;
52
53static inline void clear_ptrace_hw_breakpoint(struct task_struct *tsk)
54{
55}
56
57#endif /* CONFIG_HAVE_HW_BREAKPOINT */
58#endif /* __ASM_XTENSA_HW_BREAKPOINT_H */
diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h
index 74fed0b4e2c2..c38e5a732d86 100644
--- a/arch/xtensa/include/asm/io.h
+++ b/arch/xtensa/include/asm/io.h
@@ -25,9 +25,12 @@
25 25
26#ifdef CONFIG_MMU 26#ifdef CONFIG_MMU
27 27
28void __iomem *xtensa_ioremap_nocache(unsigned long addr, unsigned long size);
29void __iomem *xtensa_ioremap_cache(unsigned long addr, unsigned long size);
30void xtensa_iounmap(volatile void __iomem *addr);
31
28/* 32/*
29 * Return the virtual address for the specified bus memory. 33 * Return the virtual address for the specified bus memory.
30 * Note that we currently don't support any address outside the KIO segment.
31 */ 34 */
32static inline void __iomem *ioremap_nocache(unsigned long offset, 35static inline void __iomem *ioremap_nocache(unsigned long offset,
33 unsigned long size) 36 unsigned long size)
@@ -36,7 +39,7 @@ static inline void __iomem *ioremap_nocache(unsigned long offset,
36 && offset - XCHAL_KIO_PADDR < XCHAL_KIO_SIZE) 39 && offset - XCHAL_KIO_PADDR < XCHAL_KIO_SIZE)
37 return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_BYPASS_VADDR); 40 return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_BYPASS_VADDR);
38 else 41 else
39 BUG(); 42 return xtensa_ioremap_nocache(offset, size);
40} 43}
41 44
42static inline void __iomem *ioremap_cache(unsigned long offset, 45static inline void __iomem *ioremap_cache(unsigned long offset,
@@ -46,7 +49,7 @@ static inline void __iomem *ioremap_cache(unsigned long offset,
46 && offset - XCHAL_KIO_PADDR < XCHAL_KIO_SIZE) 49 && offset - XCHAL_KIO_PADDR < XCHAL_KIO_SIZE)
47 return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_CACHED_VADDR); 50 return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_CACHED_VADDR);
48 else 51 else
49 BUG(); 52 return xtensa_ioremap_cache(offset, size);
50} 53}
51#define ioremap_cache ioremap_cache 54#define ioremap_cache ioremap_cache
52 55
@@ -60,6 +63,13 @@ static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
60 63
61static inline void iounmap(volatile void __iomem *addr) 64static inline void iounmap(volatile void __iomem *addr)
62{ 65{
66 unsigned long va = (unsigned long) addr;
67
68 if (!(va >= XCHAL_KIO_CACHED_VADDR &&
69 va - XCHAL_KIO_CACHED_VADDR < XCHAL_KIO_SIZE) &&
70 !(va >= XCHAL_KIO_BYPASS_VADDR &&
71 va - XCHAL_KIO_BYPASS_VADDR < XCHAL_KIO_SIZE))
72 xtensa_iounmap(addr);
63} 73}
64 74
65#define virt_to_bus virt_to_phys 75#define virt_to_bus virt_to_phys
diff --git a/arch/xtensa/include/asm/irqflags.h b/arch/xtensa/include/asm/irqflags.h
index 8e090c709046..407606e576f8 100644
--- a/arch/xtensa/include/asm/irqflags.h
+++ b/arch/xtensa/include/asm/irqflags.h
@@ -13,6 +13,7 @@
13#define _XTENSA_IRQFLAGS_H 13#define _XTENSA_IRQFLAGS_H
14 14
15#include <linux/types.h> 15#include <linux/types.h>
16#include <asm/processor.h>
16 17
17static inline unsigned long arch_local_save_flags(void) 18static inline unsigned long arch_local_save_flags(void)
18{ 19{
diff --git a/arch/xtensa/include/asm/processor.h b/arch/xtensa/include/asm/processor.h
index 83e2e4bc01ba..d2e40d39c615 100644
--- a/arch/xtensa/include/asm/processor.h
+++ b/arch/xtensa/include/asm/processor.h
@@ -78,22 +78,20 @@
78#define XTENSA_INTLEVEL_MASK(level) _XTENSA_INTLEVEL_MASK(level) 78#define XTENSA_INTLEVEL_MASK(level) _XTENSA_INTLEVEL_MASK(level)
79#define _XTENSA_INTLEVEL_MASK(level) (XCHAL_INTLEVEL##level##_MASK) 79#define _XTENSA_INTLEVEL_MASK(level) (XCHAL_INTLEVEL##level##_MASK)
80 80
81#define IS_POW2(v) (((v) & ((v) - 1)) == 0) 81#define XTENSA_INTLEVEL_ANDBELOW_MASK(l) _XTENSA_INTLEVEL_ANDBELOW_MASK(l)
82#define _XTENSA_INTLEVEL_ANDBELOW_MASK(l) (XCHAL_INTLEVEL##l##_ANDBELOW_MASK)
82 83
83#define PROFILING_INTLEVEL XTENSA_INT_LEVEL(XCHAL_PROFILING_INTERRUPT) 84#define PROFILING_INTLEVEL XTENSA_INT_LEVEL(XCHAL_PROFILING_INTERRUPT)
84 85
85/* LOCKLEVEL defines the interrupt level that masks all 86/* LOCKLEVEL defines the interrupt level that masks all
86 * general-purpose interrupts. 87 * general-purpose interrupts.
87 */ 88 */
88#if defined(CONFIG_XTENSA_VARIANT_HAVE_PERF_EVENTS) && \ 89#if defined(CONFIG_XTENSA_FAKE_NMI) && defined(XCHAL_PROFILING_INTERRUPT)
89 defined(XCHAL_PROFILING_INTERRUPT) && \ 90#define LOCKLEVEL (PROFILING_INTLEVEL - 1)
90 PROFILING_INTLEVEL == XCHAL_EXCM_LEVEL && \
91 XCHAL_EXCM_LEVEL > 1 && \
92 IS_POW2(XTENSA_INTLEVEL_MASK(PROFILING_INTLEVEL))
93#define LOCKLEVEL (XCHAL_EXCM_LEVEL - 1)
94#else 91#else
95#define LOCKLEVEL XCHAL_EXCM_LEVEL 92#define LOCKLEVEL XCHAL_EXCM_LEVEL
96#endif 93#endif
94
97#define TOPLEVEL XCHAL_EXCM_LEVEL 95#define TOPLEVEL XCHAL_EXCM_LEVEL
98#define XTENSA_FAKE_NMI (LOCKLEVEL < TOPLEVEL) 96#define XTENSA_FAKE_NMI (LOCKLEVEL < TOPLEVEL)
99 97
@@ -132,11 +130,10 @@ struct thread_struct {
132 unsigned long bad_vaddr; /* last user fault */ 130 unsigned long bad_vaddr; /* last user fault */
133 unsigned long bad_uaddr; /* last kernel fault accessing user space */ 131 unsigned long bad_uaddr; /* last kernel fault accessing user space */
134 unsigned long error_code; 132 unsigned long error_code;
135 133#ifdef CONFIG_HAVE_HW_BREAKPOINT
136 unsigned long ibreak[XCHAL_NUM_IBREAK]; 134 struct perf_event *ptrace_bp[XCHAL_NUM_IBREAK];
137 unsigned long dbreaka[XCHAL_NUM_DBREAK]; 135 struct perf_event *ptrace_wp[XCHAL_NUM_DBREAK];
138 unsigned long dbreakc[XCHAL_NUM_DBREAK]; 136#endif
139
140 /* Make structure 16 bytes aligned. */ 137 /* Make structure 16 bytes aligned. */
141 int align[0] __attribute__ ((aligned(16))); 138 int align[0] __attribute__ ((aligned(16)));
142}; 139};
diff --git a/arch/xtensa/include/asm/regs.h b/arch/xtensa/include/asm/regs.h
index 4ba9f516b0e2..881a1134a4b4 100644
--- a/arch/xtensa/include/asm/regs.h
+++ b/arch/xtensa/include/asm/regs.h
@@ -28,6 +28,7 @@
28/* Special registers. */ 28/* Special registers. */
29 29
30#define SREG_MR 32 30#define SREG_MR 32
31#define SREG_IBREAKENABLE 96
31#define SREG_IBREAKA 128 32#define SREG_IBREAKA 128
32#define SREG_DBREAKA 144 33#define SREG_DBREAKA 144
33#define SREG_DBREAKC 160 34#define SREG_DBREAKC 160
@@ -103,6 +104,8 @@
103 104
104/* DEBUGCAUSE register fields. */ 105/* DEBUGCAUSE register fields. */
105 106
107#define DEBUGCAUSE_DBNUM_MASK 0xf00
108#define DEBUGCAUSE_DBNUM_SHIFT 8 /* First bit of DBNUM field */
106#define DEBUGCAUSE_DEBUGINT_BIT 5 /* External debug interrupt */ 109#define DEBUGCAUSE_DEBUGINT_BIT 5 /* External debug interrupt */
107#define DEBUGCAUSE_BREAKN_BIT 4 /* BREAK.N instruction */ 110#define DEBUGCAUSE_BREAKN_BIT 4 /* BREAK.N instruction */
108#define DEBUGCAUSE_BREAK_BIT 3 /* BREAK instruction */ 111#define DEBUGCAUSE_BREAK_BIT 3 /* BREAK instruction */
diff --git a/arch/xtensa/include/asm/thread_info.h b/arch/xtensa/include/asm/thread_info.h
index 9ad12c617184..7be2400f745a 100644
--- a/arch/xtensa/include/asm/thread_info.h
+++ b/arch/xtensa/include/asm/thread_info.h
@@ -111,6 +111,7 @@ static inline struct thread_info *current_thread_info(void)
111#define TIF_MEMDIE 5 /* is terminating due to OOM killer */ 111#define TIF_MEMDIE 5 /* is terminating due to OOM killer */
112#define TIF_RESTORE_SIGMASK 6 /* restore signal mask in do_signal() */ 112#define TIF_RESTORE_SIGMASK 6 /* restore signal mask in do_signal() */
113#define TIF_NOTIFY_RESUME 7 /* callback before returning to user */ 113#define TIF_NOTIFY_RESUME 7 /* callback before returning to user */
114#define TIF_DB_DISABLED 8 /* debug trap disabled for syscall */
114 115
115#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) 116#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
116#define _TIF_SIGPENDING (1<<TIF_SIGPENDING) 117#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
diff --git a/arch/xtensa/include/asm/timex.h b/arch/xtensa/include/asm/timex.h
index ca929e6a38b5..f9b389d4e973 100644
--- a/arch/xtensa/include/asm/timex.h
+++ b/arch/xtensa/include/asm/timex.h
@@ -12,19 +12,16 @@
12#include <asm/processor.h> 12#include <asm/processor.h>
13#include <linux/stringify.h> 13#include <linux/stringify.h>
14 14
15#define _INTLEVEL(x) XCHAL_INT ## x ## _LEVEL
16#define INTLEVEL(x) _INTLEVEL(x)
17
18#if XCHAL_NUM_TIMERS > 0 && \ 15#if XCHAL_NUM_TIMERS > 0 && \
19 INTLEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL 16 XTENSA_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
20# define LINUX_TIMER 0 17# define LINUX_TIMER 0
21# define LINUX_TIMER_INT XCHAL_TIMER0_INTERRUPT 18# define LINUX_TIMER_INT XCHAL_TIMER0_INTERRUPT
22#elif XCHAL_NUM_TIMERS > 1 && \ 19#elif XCHAL_NUM_TIMERS > 1 && \
23 INTLEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL 20 XTENSA_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
24# define LINUX_TIMER 1 21# define LINUX_TIMER 1
25# define LINUX_TIMER_INT XCHAL_TIMER1_INTERRUPT 22# define LINUX_TIMER_INT XCHAL_TIMER1_INTERRUPT
26#elif XCHAL_NUM_TIMERS > 2 && \ 23#elif XCHAL_NUM_TIMERS > 2 && \
27 INTLEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL 24 XTENSA_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
28# define LINUX_TIMER 2 25# define LINUX_TIMER 2
29# define LINUX_TIMER_INT XCHAL_TIMER2_INTERRUPT 26# define LINUX_TIMER_INT XCHAL_TIMER2_INTERRUPT
30#else 27#else
diff --git a/arch/xtensa/include/asm/traps.h b/arch/xtensa/include/asm/traps.h
index 28f33a8b7f5f..2e69aa4b843f 100644
--- a/arch/xtensa/include/asm/traps.h
+++ b/arch/xtensa/include/asm/traps.h
@@ -65,4 +65,21 @@ static inline void spill_registers(void)
65#endif 65#endif
66} 66}
67 67
68struct debug_table {
69 /* Pointer to debug exception handler */
70 void (*debug_exception)(void);
71 /* Temporary register save area */
72 unsigned long debug_save[1];
73#ifdef CONFIG_HAVE_HW_BREAKPOINT
74 /* Save area for DBREAKC registers */
75 unsigned long dbreakc_save[XCHAL_NUM_DBREAK];
76 /* Saved ICOUNT register */
77 unsigned long icount_save;
78 /* Saved ICOUNTLEVEL register */
79 unsigned long icount_level_save;
80#endif
81};
82
83void debug_exception(void);
84
68#endif /* _XTENSA_TRAPS_H */ 85#endif /* _XTENSA_TRAPS_H */
diff --git a/arch/xtensa/include/uapi/asm/ptrace.h b/arch/xtensa/include/uapi/asm/ptrace.h
index ee17aa842fdf..6ccbd9e38e35 100644
--- a/arch/xtensa/include/uapi/asm/ptrace.h
+++ b/arch/xtensa/include/uapi/asm/ptrace.h
@@ -72,6 +72,8 @@
72#define PTRACE_SETREGS 13 72#define PTRACE_SETREGS 13
73#define PTRACE_GETXTREGS 18 73#define PTRACE_GETXTREGS 18
74#define PTRACE_SETXTREGS 19 74#define PTRACE_SETXTREGS 19
75#define PTRACE_GETHBPREGS 20
76#define PTRACE_SETHBPREGS 21
75 77
76 78
77#endif /* _UAPI_XTENSA_PTRACE_H */ 79#endif /* _UAPI_XTENSA_PTRACE_H */
diff --git a/arch/xtensa/kernel/Makefile b/arch/xtensa/kernel/Makefile
index 4db730290d2d..c31f5d5afc7d 100644
--- a/arch/xtensa/kernel/Makefile
+++ b/arch/xtensa/kernel/Makefile
@@ -8,12 +8,12 @@ obj-y := align.o coprocessor.o entry.o irq.o pci-dma.o platform.o process.o \
8 ptrace.o setup.o signal.o stacktrace.o syscall.o time.o traps.o \ 8 ptrace.o setup.o signal.o stacktrace.o syscall.o time.o traps.o \
9 vectors.o 9 vectors.o
10 10
11obj-$(CONFIG_KGDB) += xtensa-stub.o
12obj-$(CONFIG_PCI) += pci.o 11obj-$(CONFIG_PCI) += pci.o
13obj-$(CONFIG_MODULES) += xtensa_ksyms.o module.o 12obj-$(CONFIG_MODULES) += xtensa_ksyms.o module.o
14obj-$(CONFIG_FUNCTION_TRACER) += mcount.o 13obj-$(CONFIG_FUNCTION_TRACER) += mcount.o
15obj-$(CONFIG_SMP) += smp.o mxhead.o 14obj-$(CONFIG_SMP) += smp.o mxhead.o
16obj-$(CONFIG_XTENSA_VARIANT_HAVE_PERF_EVENTS) += perf_event.o 15obj-$(CONFIG_XTENSA_VARIANT_HAVE_PERF_EVENTS) += perf_event.o
16obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
17 17
18AFLAGS_head.o += -mtext-section-literals 18AFLAGS_head.o += -mtext-section-literals
19AFLAGS_mxhead.o += -mtext-section-literals 19AFLAGS_mxhead.o += -mtext-section-literals
diff --git a/arch/xtensa/kernel/asm-offsets.c b/arch/xtensa/kernel/asm-offsets.c
index b123ace3b67c..8e10e357ee32 100644
--- a/arch/xtensa/kernel/asm-offsets.c
+++ b/arch/xtensa/kernel/asm-offsets.c
@@ -23,6 +23,7 @@
23#include <linux/kbuild.h> 23#include <linux/kbuild.h>
24 24
25#include <asm/ptrace.h> 25#include <asm/ptrace.h>
26#include <asm/traps.h>
26#include <asm/uaccess.h> 27#include <asm/uaccess.h>
27 28
28int main(void) 29int main(void)
@@ -117,5 +118,16 @@ int main(void)
117 DEFINE(_CLONE_UNTRACED, CLONE_UNTRACED); 118 DEFINE(_CLONE_UNTRACED, CLONE_UNTRACED);
118 DEFINE(PG_ARCH_1, PG_arch_1); 119 DEFINE(PG_ARCH_1, PG_arch_1);
119 120
121 /* struct debug_table */
122 DEFINE(DT_DEBUG_EXCEPTION,
123 offsetof(struct debug_table, debug_exception));
124 DEFINE(DT_DEBUG_SAVE, offsetof(struct debug_table, debug_save));
125#ifdef CONFIG_HAVE_HW_BREAKPOINT
126 DEFINE(DT_DBREAKC_SAVE, offsetof(struct debug_table, dbreakc_save));
127 DEFINE(DT_ICOUNT_SAVE, offsetof(struct debug_table, icount_save));
128 DEFINE(DT_ICOUNT_LEVEL_SAVE,
129 offsetof(struct debug_table, icount_level_save));
130#endif
131
120 return 0; 132 return 0;
121} 133}
diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S
index db5c1765b413..fe8f7e7efb9d 100644
--- a/arch/xtensa/kernel/entry.S
+++ b/arch/xtensa/kernel/entry.S
@@ -543,6 +543,12 @@ common_exception_return:
543#endif 543#endif
544 544
5455: 5455:
546#ifdef CONFIG_HAVE_HW_BREAKPOINT
547 _bbci.l a4, TIF_DB_DISABLED, 7f
548 movi a4, restore_dbreak
549 callx4 a4
5507:
551#endif
546#ifdef CONFIG_DEBUG_TLB_SANITY 552#ifdef CONFIG_DEBUG_TLB_SANITY
547 l32i a4, a1, PT_DEPC 553 l32i a4, a1, PT_DEPC
548 bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 4f 554 bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 4f
@@ -789,39 +795,99 @@ ENTRY(debug_exception)
789 795
790 movi a2, 1 << PS_EXCM_BIT 796 movi a2, 1 << PS_EXCM_BIT
791 or a2, a0, a2 797 or a2, a0, a2
792 movi a0, debug_exception # restore a3, debug jump vector
793 wsr a2, ps 798 wsr a2, ps
794 xsr a0, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
795 799
796 /* Switch to kernel/user stack, restore jump vector, and save a0 */ 800 /* Switch to kernel/user stack, restore jump vector, and save a0 */
797 801
798 bbsi.l a2, PS_UM_BIT, 2f # jump if user mode 802 bbsi.l a2, PS_UM_BIT, 2f # jump if user mode
799 803
800 addi a2, a1, -16-PT_SIZE # assume kernel stack 804 addi a2, a1, -16-PT_SIZE # assume kernel stack
8053:
806 l32i a0, a3, DT_DEBUG_SAVE
807 s32i a1, a2, PT_AREG1
801 s32i a0, a2, PT_AREG0 808 s32i a0, a2, PT_AREG0
802 movi a0, 0 809 movi a0, 0
803 s32i a1, a2, PT_AREG1
804 s32i a0, a2, PT_DEPC # mark it as a regular exception 810 s32i a0, a2, PT_DEPC # mark it as a regular exception
811 xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
805 xsr a0, depc 812 xsr a0, depc
806 s32i a3, a2, PT_AREG3 813 s32i a3, a2, PT_AREG3
807 s32i a0, a2, PT_AREG2 814 s32i a0, a2, PT_AREG2
808 mov a1, a2 815 mov a1, a2
816
817 /* Debug exception is handled as an exception, so interrupts will
818 * likely be enabled in the common exception handler. Disable
819 * preemption if we have HW breakpoints to preserve DEBUGCAUSE.DBNUM
820 * meaning.
821 */
822#if defined(CONFIG_PREEMPT_COUNT) && defined(CONFIG_HAVE_HW_BREAKPOINT)
823 GET_THREAD_INFO(a2, a1)
824 l32i a3, a2, TI_PRE_COUNT
825 addi a3, a3, 1
826 s32i a3, a2, TI_PRE_COUNT
827#endif
828
829 rsr a2, ps
830 bbsi.l a2, PS_UM_BIT, _user_exception
809 j _kernel_exception 831 j _kernel_exception
810 832
8112: rsr a2, excsave1 8332: rsr a2, excsave1
812 l32i a2, a2, EXC_TABLE_KSTK # load kernel stack pointer 834 l32i a2, a2, EXC_TABLE_KSTK # load kernel stack pointer
813 s32i a0, a2, PT_AREG0 835 j 3b
836
837#ifdef CONFIG_HAVE_HW_BREAKPOINT
838 /* Debug exception while in exception mode. This may happen when
839 * window overflow/underflow handler or fast exception handler hits
840 * data breakpoint, in which case save and disable all data
841 * breakpoints, single-step faulting instruction and restore data
842 * breakpoints.
843 */
8441:
845 bbci.l a0, PS_UM_BIT, 1b # jump if kernel mode
846
847 rsr a0, debugcause
848 bbsi.l a0, DEBUGCAUSE_DBREAK_BIT, .Ldebug_save_dbreak
849
850 .set _index, 0
851 .rept XCHAL_NUM_DBREAK
852 l32i a0, a3, DT_DBREAKC_SAVE + _index * 4
853 wsr a0, SREG_DBREAKC + _index
854 .set _index, _index + 1
855 .endr
856
857 l32i a0, a3, DT_ICOUNT_LEVEL_SAVE
858 wsr a0, icountlevel
859
860 l32i a0, a3, DT_ICOUNT_SAVE
861 xsr a0, icount
862
863 l32i a0, a3, DT_DEBUG_SAVE
864 xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
865 rfi XCHAL_DEBUGLEVEL
866
867.Ldebug_save_dbreak:
868 .set _index, 0
869 .rept XCHAL_NUM_DBREAK
814 movi a0, 0 870 movi a0, 0
815 s32i a1, a2, PT_AREG1 871 xsr a0, SREG_DBREAKC + _index
816 s32i a0, a2, PT_DEPC 872 s32i a0, a3, DT_DBREAKC_SAVE + _index * 4
817 xsr a0, depc 873 .set _index, _index + 1
818 s32i a3, a2, PT_AREG3 874 .endr
819 s32i a0, a2, PT_AREG2
820 mov a1, a2
821 j _user_exception
822 875
823 /* Debug exception while in exception mode. */ 876 movi a0, XCHAL_EXCM_LEVEL + 1
877 xsr a0, icountlevel
878 s32i a0, a3, DT_ICOUNT_LEVEL_SAVE
879
880 movi a0, 0xfffffffe
881 xsr a0, icount
882 s32i a0, a3, DT_ICOUNT_SAVE
883
884 l32i a0, a3, DT_DEBUG_SAVE
885 xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
886 rfi XCHAL_DEBUGLEVEL
887#else
888 /* Debug exception while in exception mode. Should not happen. */
8241: j 1b // FIXME!! 8891: j 1b // FIXME!!
890#endif
825 891
826ENDPROC(debug_exception) 892ENDPROC(debug_exception)
827 893
diff --git a/arch/xtensa/kernel/head.S b/arch/xtensa/kernel/head.S
index 9ed55649ac8e..bc4f4bf05099 100644
--- a/arch/xtensa/kernel/head.S
+++ b/arch/xtensa/kernel/head.S
@@ -128,7 +128,7 @@ ENTRY(_startup)
128 wsr a0, icountlevel 128 wsr a0, icountlevel
129 129
130 .set _index, 0 130 .set _index, 0
131 .rept XCHAL_NUM_DBREAK - 1 131 .rept XCHAL_NUM_DBREAK
132 wsr a0, SREG_DBREAKC + _index 132 wsr a0, SREG_DBREAKC + _index
133 .set _index, _index + 1 133 .set _index, _index + 1
134 .endr 134 .endr
@@ -197,11 +197,6 @@ ENTRY(_startup)
197 wsr a2, ps # (enable reg-windows; progmode stack) 197 wsr a2, ps # (enable reg-windows; progmode stack)
198 rsync 198 rsync
199 199
200 /* Set up EXCSAVE[DEBUGLEVEL] to point to the Debug Exception Handler.*/
201
202 movi a2, debug_exception
203 wsr a2, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
204
205#ifdef CONFIG_SMP 200#ifdef CONFIG_SMP
206 /* 201 /*
207 * Notice that we assume with SMP that cores have PRID 202 * Notice that we assume with SMP that cores have PRID
diff --git a/arch/xtensa/kernel/hw_breakpoint.c b/arch/xtensa/kernel/hw_breakpoint.c
new file mode 100644
index 000000000000..b35656ab7dbd
--- /dev/null
+++ b/arch/xtensa/kernel/hw_breakpoint.c
@@ -0,0 +1,317 @@
1/*
2 * Xtensa hardware breakpoints/watchpoints handling functions
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2016 Cadence Design Systems Inc.
9 */
10
11#include <linux/hw_breakpoint.h>
12#include <linux/log2.h>
13#include <linux/percpu.h>
14#include <linux/perf_event.h>
15#include <variant/core.h>
16
17/* Breakpoint currently in use for each IBREAKA. */
18static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[XCHAL_NUM_IBREAK]);
19
20/* Watchpoint currently in use for each DBREAKA. */
21static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[XCHAL_NUM_DBREAK]);
22
23int hw_breakpoint_slots(int type)
24{
25 switch (type) {
26 case TYPE_INST:
27 return XCHAL_NUM_IBREAK;
28 case TYPE_DATA:
29 return XCHAL_NUM_DBREAK;
30 default:
31 pr_warn("unknown slot type: %d\n", type);
32 return 0;
33 }
34}
35
36int arch_check_bp_in_kernelspace(struct perf_event *bp)
37{
38 unsigned int len;
39 unsigned long va;
40 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
41
42 va = info->address;
43 len = bp->attr.bp_len;
44
45 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
46}
47
48/*
49 * Construct an arch_hw_breakpoint from a perf_event.
50 */
51static int arch_build_bp_info(struct perf_event *bp)
52{
53 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
54
55 /* Type */
56 switch (bp->attr.bp_type) {
57 case HW_BREAKPOINT_X:
58 info->type = XTENSA_BREAKPOINT_EXECUTE;
59 break;
60 case HW_BREAKPOINT_R:
61 info->type = XTENSA_BREAKPOINT_LOAD;
62 break;
63 case HW_BREAKPOINT_W:
64 info->type = XTENSA_BREAKPOINT_STORE;
65 break;
66 case HW_BREAKPOINT_RW:
67 info->type = XTENSA_BREAKPOINT_LOAD | XTENSA_BREAKPOINT_STORE;
68 break;
69 default:
70 return -EINVAL;
71 }
72
73 /* Len */
74 info->len = bp->attr.bp_len;
75 if (info->len < 1 || info->len > 64 || !is_power_of_2(info->len))
76 return -EINVAL;
77
78 /* Address */
79 info->address = bp->attr.bp_addr;
80 if (info->address & (info->len - 1))
81 return -EINVAL;
82
83 return 0;
84}
85
86int arch_validate_hwbkpt_settings(struct perf_event *bp)
87{
88 int ret;
89
90 /* Build the arch_hw_breakpoint. */
91 ret = arch_build_bp_info(bp);
92 return ret;
93}
94
95int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
96 unsigned long val, void *data)
97{
98 return NOTIFY_DONE;
99}
100
101static void xtensa_wsr(unsigned long v, u8 sr)
102{
103 /* We don't have indexed wsr and creating instruction dynamically
104 * doesn't seem worth it given how small XCHAL_NUM_IBREAK and
105 * XCHAL_NUM_DBREAK are. Thus the switch. In case build breaks here
106 * the switch below needs to be extended.
107 */
108 BUILD_BUG_ON(XCHAL_NUM_IBREAK > 2);
109 BUILD_BUG_ON(XCHAL_NUM_DBREAK > 2);
110
111 switch (sr) {
112#if XCHAL_NUM_IBREAK > 0
113 case SREG_IBREAKA + 0:
114 WSR(v, SREG_IBREAKA + 0);
115 break;
116#endif
117#if XCHAL_NUM_IBREAK > 1
118 case SREG_IBREAKA + 1:
119 WSR(v, SREG_IBREAKA + 1);
120 break;
121#endif
122
123#if XCHAL_NUM_DBREAK > 0
124 case SREG_DBREAKA + 0:
125 WSR(v, SREG_DBREAKA + 0);
126 break;
127 case SREG_DBREAKC + 0:
128 WSR(v, SREG_DBREAKC + 0);
129 break;
130#endif
131#if XCHAL_NUM_DBREAK > 1
132 case SREG_DBREAKA + 1:
133 WSR(v, SREG_DBREAKA + 1);
134 break;
135
136 case SREG_DBREAKC + 1:
137 WSR(v, SREG_DBREAKC + 1);
138 break;
139#endif
140 }
141}
142
143static int alloc_slot(struct perf_event **slot, size_t n,
144 struct perf_event *bp)
145{
146 size_t i;
147
148 for (i = 0; i < n; ++i) {
149 if (!slot[i]) {
150 slot[i] = bp;
151 return i;
152 }
153 }
154 return -EBUSY;
155}
156
157static void set_ibreak_regs(int reg, struct perf_event *bp)
158{
159 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
160 unsigned long ibreakenable;
161
162 xtensa_wsr(info->address, SREG_IBREAKA + reg);
163 RSR(ibreakenable, SREG_IBREAKENABLE);
164 WSR(ibreakenable | (1 << reg), SREG_IBREAKENABLE);
165}
166
167static void set_dbreak_regs(int reg, struct perf_event *bp)
168{
169 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
170 unsigned long dbreakc = DBREAKC_MASK_MASK & -info->len;
171
172 if (info->type & XTENSA_BREAKPOINT_LOAD)
173 dbreakc |= DBREAKC_LOAD_MASK;
174 if (info->type & XTENSA_BREAKPOINT_STORE)
175 dbreakc |= DBREAKC_STOR_MASK;
176
177 xtensa_wsr(info->address, SREG_DBREAKA + reg);
178 xtensa_wsr(dbreakc, SREG_DBREAKC + reg);
179}
180
181int arch_install_hw_breakpoint(struct perf_event *bp)
182{
183 int i;
184
185 if (counter_arch_bp(bp)->type == XTENSA_BREAKPOINT_EXECUTE) {
186 /* Breakpoint */
187 i = alloc_slot(this_cpu_ptr(bp_on_reg), XCHAL_NUM_IBREAK, bp);
188 if (i < 0)
189 return i;
190 set_ibreak_regs(i, bp);
191
192 } else {
193 /* Watchpoint */
194 i = alloc_slot(this_cpu_ptr(wp_on_reg), XCHAL_NUM_DBREAK, bp);
195 if (i < 0)
196 return i;
197 set_dbreak_regs(i, bp);
198 }
199 return 0;
200}
201
202static int free_slot(struct perf_event **slot, size_t n,
203 struct perf_event *bp)
204{
205 size_t i;
206
207 for (i = 0; i < n; ++i) {
208 if (slot[i] == bp) {
209 slot[i] = NULL;
210 return i;
211 }
212 }
213 return -EBUSY;
214}
215
216void arch_uninstall_hw_breakpoint(struct perf_event *bp)
217{
218 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
219 int i;
220
221 if (info->type == XTENSA_BREAKPOINT_EXECUTE) {
222 unsigned long ibreakenable;
223
224 /* Breakpoint */
225 i = free_slot(this_cpu_ptr(bp_on_reg), XCHAL_NUM_IBREAK, bp);
226 if (i >= 0) {
227 RSR(ibreakenable, SREG_IBREAKENABLE);
228 WSR(ibreakenable & ~(1 << i), SREG_IBREAKENABLE);
229 }
230 } else {
231 /* Watchpoint */
232 i = free_slot(this_cpu_ptr(wp_on_reg), XCHAL_NUM_DBREAK, bp);
233 if (i >= 0)
234 xtensa_wsr(0, SREG_DBREAKC + i);
235 }
236}
237
238void hw_breakpoint_pmu_read(struct perf_event *bp)
239{
240}
241
242void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
243{
244 int i;
245 struct thread_struct *t = &tsk->thread;
246
247 for (i = 0; i < XCHAL_NUM_IBREAK; ++i) {
248 if (t->ptrace_bp[i]) {
249 unregister_hw_breakpoint(t->ptrace_bp[i]);
250 t->ptrace_bp[i] = NULL;
251 }
252 }
253 for (i = 0; i < XCHAL_NUM_DBREAK; ++i) {
254 if (t->ptrace_wp[i]) {
255 unregister_hw_breakpoint(t->ptrace_wp[i]);
256 t->ptrace_wp[i] = NULL;
257 }
258 }
259}
260
261/*
262 * Set ptrace breakpoint pointers to zero for this task.
263 * This is required in order to prevent child processes from unregistering
264 * breakpoints held by their parent.
265 */
266void clear_ptrace_hw_breakpoint(struct task_struct *tsk)
267{
268 memset(tsk->thread.ptrace_bp, 0, sizeof(tsk->thread.ptrace_bp));
269 memset(tsk->thread.ptrace_wp, 0, sizeof(tsk->thread.ptrace_wp));
270}
271
272void restore_dbreak(void)
273{
274 int i;
275
276 for (i = 0; i < XCHAL_NUM_DBREAK; ++i) {
277 struct perf_event *bp = this_cpu_ptr(wp_on_reg)[i];
278
279 if (bp)
280 set_dbreak_regs(i, bp);
281 }
282 clear_thread_flag(TIF_DB_DISABLED);
283}
284
285int check_hw_breakpoint(struct pt_regs *regs)
286{
287 if (regs->debugcause & BIT(DEBUGCAUSE_IBREAK_BIT)) {
288 int i;
289 struct perf_event **bp = this_cpu_ptr(bp_on_reg);
290
291 for (i = 0; i < XCHAL_NUM_IBREAK; ++i) {
292 if (bp[i] && !bp[i]->attr.disabled &&
293 regs->pc == bp[i]->attr.bp_addr)
294 perf_bp_event(bp[i], regs);
295 }
296 return 0;
297 } else if (regs->debugcause & BIT(DEBUGCAUSE_DBREAK_BIT)) {
298 struct perf_event **bp = this_cpu_ptr(wp_on_reg);
299 int dbnum = (regs->debugcause & DEBUGCAUSE_DBNUM_MASK) >>
300 DEBUGCAUSE_DBNUM_SHIFT;
301
302 if (dbnum < XCHAL_NUM_DBREAK && bp[dbnum]) {
303 if (user_mode(regs)) {
304 perf_bp_event(bp[dbnum], regs);
305 } else {
306 set_thread_flag(TIF_DB_DISABLED);
307 xtensa_wsr(0, SREG_DBREAKC + dbnum);
308 }
309 } else {
310 WARN_ONCE(1,
311 "Wrong/unconfigured DBNUM reported in DEBUGCAUSE: %d\n",
312 dbnum);
313 }
314 return 0;
315 }
316 return -ENOENT;
317}
diff --git a/arch/xtensa/kernel/process.c b/arch/xtensa/kernel/process.c
index 1c85323f01d7..5bbfed81c97b 100644
--- a/arch/xtensa/kernel/process.c
+++ b/arch/xtensa/kernel/process.c
@@ -24,6 +24,7 @@
24#include <linux/unistd.h> 24#include <linux/unistd.h>
25#include <linux/ptrace.h> 25#include <linux/ptrace.h>
26#include <linux/elf.h> 26#include <linux/elf.h>
27#include <linux/hw_breakpoint.h>
27#include <linux/init.h> 28#include <linux/init.h>
28#include <linux/prctl.h> 29#include <linux/prctl.h>
29#include <linux/init_task.h> 30#include <linux/init_task.h>
@@ -43,6 +44,7 @@
43#include <linux/atomic.h> 44#include <linux/atomic.h>
44#include <asm/asm-offsets.h> 45#include <asm/asm-offsets.h>
45#include <asm/regs.h> 46#include <asm/regs.h>
47#include <asm/hw_breakpoint.h>
46 48
47extern void ret_from_fork(void); 49extern void ret_from_fork(void);
48extern void ret_from_kernel_thread(void); 50extern void ret_from_kernel_thread(void);
@@ -131,6 +133,7 @@ void flush_thread(void)
131 coprocessor_flush_all(ti); 133 coprocessor_flush_all(ti);
132 coprocessor_release_all(ti); 134 coprocessor_release_all(ti);
133#endif 135#endif
136 flush_ptrace_hw_breakpoint(current);
134} 137}
135 138
136/* 139/*
@@ -273,6 +276,8 @@ int copy_thread(unsigned long clone_flags, unsigned long usp_thread_fn,
273 ti->cpenable = 0; 276 ti->cpenable = 0;
274#endif 277#endif
275 278
279 clear_ptrace_hw_breakpoint(p);
280
276 return 0; 281 return 0;
277} 282}
278 283
diff --git a/arch/xtensa/kernel/ptrace.c b/arch/xtensa/kernel/ptrace.c
index 4d54b481123b..a651f3a628ee 100644
--- a/arch/xtensa/kernel/ptrace.c
+++ b/arch/xtensa/kernel/ptrace.c
@@ -13,21 +13,23 @@
13 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca> 13 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
14 */ 14 */
15 15
16#include <linux/errno.h>
17#include <linux/hw_breakpoint.h>
16#include <linux/kernel.h> 18#include <linux/kernel.h>
17#include <linux/sched.h>
18#include <linux/mm.h> 19#include <linux/mm.h>
19#include <linux/errno.h> 20#include <linux/perf_event.h>
20#include <linux/ptrace.h> 21#include <linux/ptrace.h>
21#include <linux/smp.h> 22#include <linux/sched.h>
22#include <linux/security.h> 23#include <linux/security.h>
23#include <linux/signal.h> 24#include <linux/signal.h>
25#include <linux/smp.h>
24 26
25#include <asm/pgtable.h> 27#include <asm/coprocessor.h>
28#include <asm/elf.h>
26#include <asm/page.h> 29#include <asm/page.h>
27#include <asm/uaccess.h> 30#include <asm/pgtable.h>
28#include <asm/ptrace.h> 31#include <asm/ptrace.h>
29#include <asm/elf.h> 32#include <asm/uaccess.h>
30#include <asm/coprocessor.h>
31 33
32 34
33void user_enable_single_step(struct task_struct *child) 35void user_enable_single_step(struct task_struct *child)
@@ -267,6 +269,146 @@ int ptrace_pokeusr(struct task_struct *child, long regno, long val)
267 return 0; 269 return 0;
268} 270}
269 271
272#ifdef CONFIG_HAVE_HW_BREAKPOINT
273static void ptrace_hbptriggered(struct perf_event *bp,
274 struct perf_sample_data *data,
275 struct pt_regs *regs)
276{
277 int i;
278 siginfo_t info;
279 struct arch_hw_breakpoint *bkpt = counter_arch_bp(bp);
280
281 if (bp->attr.bp_type & HW_BREAKPOINT_X) {
282 for (i = 0; i < XCHAL_NUM_IBREAK; ++i)
283 if (current->thread.ptrace_bp[i] == bp)
284 break;
285 i <<= 1;
286 } else {
287 for (i = 0; i < XCHAL_NUM_DBREAK; ++i)
288 if (current->thread.ptrace_wp[i] == bp)
289 break;
290 i = (i << 1) | 1;
291 }
292
293 info.si_signo = SIGTRAP;
294 info.si_errno = i;
295 info.si_code = TRAP_HWBKPT;
296 info.si_addr = (void __user *)bkpt->address;
297
298 force_sig_info(SIGTRAP, &info, current);
299}
300
301static struct perf_event *ptrace_hbp_create(struct task_struct *tsk, int type)
302{
303 struct perf_event_attr attr;
304
305 ptrace_breakpoint_init(&attr);
306
307 /* Initialise fields to sane defaults. */
308 attr.bp_addr = 0;
309 attr.bp_len = 1;
310 attr.bp_type = type;
311 attr.disabled = 1;
312
313 return register_user_hw_breakpoint(&attr, ptrace_hbptriggered, NULL,
314 tsk);
315}
316
317/*
318 * Address bit 0 choose instruction (0) or data (1) break register, bits
319 * 31..1 are the register number.
320 * Both PTRACE_GETHBPREGS and PTRACE_SETHBPREGS transfer two 32-bit words:
321 * address (0) and control (1).
322 * Instruction breakpoint contorl word is 0 to clear breakpoint, 1 to set.
323 * Data breakpoint control word bit 31 is 'trigger on store', bit 30 is
324 * 'trigger on load, bits 29..0 are length. Length 0 is used to clear a
325 * breakpoint. To set a breakpoint length must be a power of 2 in the range
326 * 1..64 and the address must be length-aligned.
327 */
328
329static long ptrace_gethbpregs(struct task_struct *child, long addr,
330 long __user *datap)
331{
332 struct perf_event *bp;
333 u32 user_data[2] = {0};
334 bool dbreak = addr & 1;
335 unsigned idx = addr >> 1;
336
337 if ((!dbreak && idx >= XCHAL_NUM_IBREAK) ||
338 (dbreak && idx >= XCHAL_NUM_DBREAK))
339 return -EINVAL;
340
341 if (dbreak)
342 bp = child->thread.ptrace_wp[idx];
343 else
344 bp = child->thread.ptrace_bp[idx];
345
346 if (bp) {
347 user_data[0] = bp->attr.bp_addr;
348 user_data[1] = bp->attr.disabled ? 0 : bp->attr.bp_len;
349 if (dbreak) {
350 if (bp->attr.bp_type & HW_BREAKPOINT_R)
351 user_data[1] |= DBREAKC_LOAD_MASK;
352 if (bp->attr.bp_type & HW_BREAKPOINT_W)
353 user_data[1] |= DBREAKC_STOR_MASK;
354 }
355 }
356
357 if (copy_to_user(datap, user_data, sizeof(user_data)))
358 return -EFAULT;
359
360 return 0;
361}
362
363static long ptrace_sethbpregs(struct task_struct *child, long addr,
364 long __user *datap)
365{
366 struct perf_event *bp;
367 struct perf_event_attr attr;
368 u32 user_data[2];
369 bool dbreak = addr & 1;
370 unsigned idx = addr >> 1;
371 int bp_type = 0;
372
373 if ((!dbreak && idx >= XCHAL_NUM_IBREAK) ||
374 (dbreak && idx >= XCHAL_NUM_DBREAK))
375 return -EINVAL;
376
377 if (copy_from_user(user_data, datap, sizeof(user_data)))
378 return -EFAULT;
379
380 if (dbreak) {
381 bp = child->thread.ptrace_wp[idx];
382 if (user_data[1] & DBREAKC_LOAD_MASK)
383 bp_type |= HW_BREAKPOINT_R;
384 if (user_data[1] & DBREAKC_STOR_MASK)
385 bp_type |= HW_BREAKPOINT_W;
386 } else {
387 bp = child->thread.ptrace_bp[idx];
388 bp_type = HW_BREAKPOINT_X;
389 }
390
391 if (!bp) {
392 bp = ptrace_hbp_create(child,
393 bp_type ? bp_type : HW_BREAKPOINT_RW);
394 if (IS_ERR(bp))
395 return PTR_ERR(bp);
396 if (dbreak)
397 child->thread.ptrace_wp[idx] = bp;
398 else
399 child->thread.ptrace_bp[idx] = bp;
400 }
401
402 attr = bp->attr;
403 attr.bp_addr = user_data[0];
404 attr.bp_len = user_data[1] & ~(DBREAKC_LOAD_MASK | DBREAKC_STOR_MASK);
405 attr.bp_type = bp_type;
406 attr.disabled = !attr.bp_len;
407
408 return modify_user_hw_breakpoint(bp, &attr);
409}
410#endif
411
270long arch_ptrace(struct task_struct *child, long request, 412long arch_ptrace(struct task_struct *child, long request,
271 unsigned long addr, unsigned long data) 413 unsigned long addr, unsigned long data)
272{ 414{
@@ -307,7 +449,15 @@ long arch_ptrace(struct task_struct *child, long request,
307 case PTRACE_SETXTREGS: 449 case PTRACE_SETXTREGS:
308 ret = ptrace_setxregs(child, datap); 450 ret = ptrace_setxregs(child, datap);
309 break; 451 break;
452#ifdef CONFIG_HAVE_HW_BREAKPOINT
453 case PTRACE_GETHBPREGS:
454 ret = ptrace_gethbpregs(child, addr, datap);
455 break;
310 456
457 case PTRACE_SETHBPREGS:
458 ret = ptrace_sethbpregs(child, addr, datap);
459 break;
460#endif
311 default: 461 default:
312 ret = ptrace_request(child, request, addr, data); 462 ret = ptrace_request(child, request, addr, data);
313 break; 463 break;
diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c
index 42d441f7898b..d02fc304b31c 100644
--- a/arch/xtensa/kernel/traps.c
+++ b/arch/xtensa/kernel/traps.c
@@ -39,11 +39,7 @@
39#include <asm/pgtable.h> 39#include <asm/pgtable.h>
40#include <asm/processor.h> 40#include <asm/processor.h>
41#include <asm/traps.h> 41#include <asm/traps.h>
42 42#include <asm/hw_breakpoint.h>
43#ifdef CONFIG_KGDB
44extern int gdb_enter;
45extern int return_from_debug_flag;
46#endif
47 43
48/* 44/*
49 * Machine specific interrupt handlers 45 * Machine specific interrupt handlers
@@ -162,6 +158,8 @@ COPROCESSOR(7),
162 158
163DEFINE_PER_CPU(unsigned long, exc_table[EXC_TABLE_SIZE/4]); 159DEFINE_PER_CPU(unsigned long, exc_table[EXC_TABLE_SIZE/4]);
164 160
161DEFINE_PER_CPU(struct debug_table, debug_table);
162
165void die(const char*, struct pt_regs*, long); 163void die(const char*, struct pt_regs*, long);
166 164
167static inline void 165static inline void
@@ -205,6 +203,32 @@ extern void do_IRQ(int, struct pt_regs *);
205 203
206#if XTENSA_FAKE_NMI 204#if XTENSA_FAKE_NMI
207 205
206#define IS_POW2(v) (((v) & ((v) - 1)) == 0)
207
208#if !(PROFILING_INTLEVEL == XCHAL_EXCM_LEVEL && \
209 IS_POW2(XTENSA_INTLEVEL_MASK(PROFILING_INTLEVEL)))
210#warning "Fake NMI is requested for PMM, but there are other IRQs at or above its level."
211#warning "Fake NMI will be used, but there will be a bugcheck if one of those IRQs fire."
212
213static inline void check_valid_nmi(void)
214{
215 unsigned intread = get_sr(interrupt);
216 unsigned intenable = get_sr(intenable);
217
218 BUG_ON(intread & intenable &
219 ~(XTENSA_INTLEVEL_ANDBELOW_MASK(PROFILING_INTLEVEL) ^
220 XTENSA_INTLEVEL_MASK(PROFILING_INTLEVEL) ^
221 BIT(XCHAL_PROFILING_INTERRUPT)));
222}
223
224#else
225
226static inline void check_valid_nmi(void)
227{
228}
229
230#endif
231
208irqreturn_t xtensa_pmu_irq_handler(int irq, void *dev_id); 232irqreturn_t xtensa_pmu_irq_handler(int irq, void *dev_id);
209 233
210DEFINE_PER_CPU(unsigned long, nmi_count); 234DEFINE_PER_CPU(unsigned long, nmi_count);
@@ -219,6 +243,7 @@ void do_nmi(struct pt_regs *regs)
219 old_regs = set_irq_regs(regs); 243 old_regs = set_irq_regs(regs);
220 nmi_enter(); 244 nmi_enter();
221 ++*this_cpu_ptr(&nmi_count); 245 ++*this_cpu_ptr(&nmi_count);
246 check_valid_nmi();
222 xtensa_pmu_irq_handler(0, NULL); 247 xtensa_pmu_irq_handler(0, NULL);
223 nmi_exit(); 248 nmi_exit();
224 set_irq_regs(old_regs); 249 set_irq_regs(old_regs);
@@ -314,23 +339,22 @@ do_unaligned_user (struct pt_regs *regs)
314} 339}
315#endif 340#endif
316 341
342/* Handle debug events.
343 * When CONFIG_HAVE_HW_BREAKPOINT is on this handler is called with
344 * preemption disabled to avoid rescheduling and keep mapping of hardware
345 * breakpoint structures to debug registers intact, so that
346 * DEBUGCAUSE.DBNUM could be used in case of data breakpoint hit.
347 */
317void 348void
318do_debug(struct pt_regs *regs) 349do_debug(struct pt_regs *regs)
319{ 350{
320#ifdef CONFIG_KGDB 351#ifdef CONFIG_HAVE_HW_BREAKPOINT
321 /* If remote debugging is configured AND enabled, we give control to 352 int ret = check_hw_breakpoint(regs);
322 * kgdb. Otherwise, we fall through, perhaps giving control to the 353
323 * native debugger. 354 preempt_enable();
324 */ 355 if (ret == 0)
325
326 if (gdb_enter) {
327 extern void gdb_handle_exception(struct pt_regs *);
328 gdb_handle_exception(regs);
329 return_from_debug_flag = 1;
330 return; 356 return;
331 }
332#endif 357#endif
333
334 __die_if_kernel("Breakpoint in kernel", regs, SIGKILL); 358 __die_if_kernel("Breakpoint in kernel", regs, SIGKILL);
335 359
336 /* If in user mode, send SIGTRAP signal to current process */ 360 /* If in user mode, send SIGTRAP signal to current process */
@@ -364,6 +388,15 @@ static void trap_init_excsave(void)
364 __asm__ __volatile__("wsr %0, excsave1\n" : : "a" (excsave1)); 388 __asm__ __volatile__("wsr %0, excsave1\n" : : "a" (excsave1));
365} 389}
366 390
391static void trap_init_debug(void)
392{
393 unsigned long debugsave = (unsigned long)this_cpu_ptr(&debug_table);
394
395 this_cpu_ptr(&debug_table)->debug_exception = debug_exception;
396 __asm__ __volatile__("wsr %0, excsave" __stringify(XCHAL_DEBUGLEVEL)
397 :: "a"(debugsave));
398}
399
367/* 400/*
368 * Initialize dispatch tables. 401 * Initialize dispatch tables.
369 * 402 *
@@ -407,12 +440,14 @@ void __init trap_init(void)
407 440
408 /* Initialize EXCSAVE_1 to hold the address of the exception table. */ 441 /* Initialize EXCSAVE_1 to hold the address of the exception table. */
409 trap_init_excsave(); 442 trap_init_excsave();
443 trap_init_debug();
410} 444}
411 445
412#ifdef CONFIG_SMP 446#ifdef CONFIG_SMP
413void secondary_trap_init(void) 447void secondary_trap_init(void)
414{ 448{
415 trap_init_excsave(); 449 trap_init_excsave();
450 trap_init_debug();
416} 451}
417#endif 452#endif
418 453
diff --git a/arch/xtensa/kernel/vectors.S b/arch/xtensa/kernel/vectors.S
index fc25318e75ad..332e9d635fb6 100644
--- a/arch/xtensa/kernel/vectors.S
+++ b/arch/xtensa/kernel/vectors.S
@@ -601,7 +601,9 @@ ENDPROC(window_overflow_restore_a0_fixup)
601 601
602ENTRY(_DebugInterruptVector) 602ENTRY(_DebugInterruptVector)
603 603
604 xsr a0, SREG_EXCSAVE + XCHAL_DEBUGLEVEL 604 xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
605 s32i a0, a3, DT_DEBUG_SAVE
606 l32i a0, a3, DT_DEBUG_EXCEPTION
605 jx a0 607 jx a0
606 608
607ENDPROC(_DebugInterruptVector) 609ENDPROC(_DebugInterruptVector)
diff --git a/arch/xtensa/mm/Makefile b/arch/xtensa/mm/Makefile
index e601e2fbe8e6..0b3d296a016a 100644
--- a/arch/xtensa/mm/Makefile
+++ b/arch/xtensa/mm/Makefile
@@ -3,5 +3,5 @@
3# 3#
4 4
5obj-y := init.o misc.o 5obj-y := init.o misc.o
6obj-$(CONFIG_MMU) += cache.o fault.o mmu.o tlb.o 6obj-$(CONFIG_MMU) += cache.o fault.o ioremap.o mmu.o tlb.o
7obj-$(CONFIG_HIGHMEM) += highmem.o 7obj-$(CONFIG_HIGHMEM) += highmem.o
diff --git a/arch/xtensa/mm/cache.c b/arch/xtensa/mm/cache.c
index d75aa1476da7..1a804a2f9a5b 100644
--- a/arch/xtensa/mm/cache.c
+++ b/arch/xtensa/mm/cache.c
@@ -97,11 +97,11 @@ void clear_user_highpage(struct page *page, unsigned long vaddr)
97 unsigned long paddr; 97 unsigned long paddr;
98 void *kvaddr = coherent_kvaddr(page, TLBTEMP_BASE_1, vaddr, &paddr); 98 void *kvaddr = coherent_kvaddr(page, TLBTEMP_BASE_1, vaddr, &paddr);
99 99
100 pagefault_disable(); 100 preempt_disable();
101 kmap_invalidate_coherent(page, vaddr); 101 kmap_invalidate_coherent(page, vaddr);
102 set_bit(PG_arch_1, &page->flags); 102 set_bit(PG_arch_1, &page->flags);
103 clear_page_alias(kvaddr, paddr); 103 clear_page_alias(kvaddr, paddr);
104 pagefault_enable(); 104 preempt_enable();
105} 105}
106 106
107void copy_user_highpage(struct page *dst, struct page *src, 107void copy_user_highpage(struct page *dst, struct page *src,
@@ -113,11 +113,11 @@ void copy_user_highpage(struct page *dst, struct page *src,
113 void *src_vaddr = coherent_kvaddr(src, TLBTEMP_BASE_2, vaddr, 113 void *src_vaddr = coherent_kvaddr(src, TLBTEMP_BASE_2, vaddr,
114 &src_paddr); 114 &src_paddr);
115 115
116 pagefault_disable(); 116 preempt_disable();
117 kmap_invalidate_coherent(dst, vaddr); 117 kmap_invalidate_coherent(dst, vaddr);
118 set_bit(PG_arch_1, &dst->flags); 118 set_bit(PG_arch_1, &dst->flags);
119 copy_page_alias(dst_vaddr, src_vaddr, dst_paddr, src_paddr); 119 copy_page_alias(dst_vaddr, src_vaddr, dst_paddr, src_paddr);
120 pagefault_enable(); 120 preempt_enable();
121} 121}
122 122
123#endif /* DCACHE_WAY_SIZE > PAGE_SIZE */ 123#endif /* DCACHE_WAY_SIZE > PAGE_SIZE */
diff --git a/arch/xtensa/mm/ioremap.c b/arch/xtensa/mm/ioremap.c
new file mode 100644
index 000000000000..d89c3c5fd962
--- /dev/null
+++ b/arch/xtensa/mm/ioremap.c
@@ -0,0 +1,68 @@
1/*
2 * ioremap implementation.
3 *
4 * Copyright (C) 2015 Cadence Design Systems Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/io.h>
12#include <linux/vmalloc.h>
13#include <asm/cacheflush.h>
14#include <asm/io.h>
15#include <asm/pgtable.h>
16
17static void __iomem *xtensa_ioremap(unsigned long paddr, unsigned long size,
18 pgprot_t prot)
19{
20 unsigned long offset = paddr & ~PAGE_MASK;
21 unsigned long pfn = __phys_to_pfn(paddr);
22 struct vm_struct *area;
23 unsigned long vaddr;
24 int err;
25
26 paddr &= PAGE_MASK;
27
28 WARN_ON(pfn_valid(pfn));
29
30 size = PAGE_ALIGN(offset + size);
31
32 area = get_vm_area(size, VM_IOREMAP);
33 if (!area)
34 return NULL;
35
36 vaddr = (unsigned long)area->addr;
37 area->phys_addr = paddr;
38
39 err = ioremap_page_range(vaddr, vaddr + size, paddr, prot);
40
41 if (err) {
42 vunmap((void *)vaddr);
43 return NULL;
44 }
45
46 flush_cache_vmap(vaddr, vaddr + size);
47 return (void __iomem *)(offset + vaddr);
48}
49
50void __iomem *xtensa_ioremap_nocache(unsigned long addr, unsigned long size)
51{
52 return xtensa_ioremap(addr, size, pgprot_noncached(PAGE_KERNEL));
53}
54EXPORT_SYMBOL(xtensa_ioremap_nocache);
55
56void __iomem *xtensa_ioremap_cache(unsigned long addr, unsigned long size)
57{
58 return xtensa_ioremap(addr, size, PAGE_KERNEL);
59}
60EXPORT_SYMBOL(xtensa_ioremap_cache);
61
62void xtensa_iounmap(volatile void __iomem *io_addr)
63{
64 void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr);
65
66 vunmap(addr);
67}
68EXPORT_SYMBOL(xtensa_iounmap);
diff --git a/arch/xtensa/platforms/iss/console.c b/arch/xtensa/platforms/iss/console.c
index c54505dcf4db..c68f1e6158aa 100644
--- a/arch/xtensa/platforms/iss/console.c
+++ b/arch/xtensa/platforms/iss/console.c
@@ -96,21 +96,23 @@ static void rs_poll(unsigned long priv)
96{ 96{
97 struct tty_port *port = (struct tty_port *)priv; 97 struct tty_port *port = (struct tty_port *)priv;
98 int i = 0; 98 int i = 0;
99 int rd = 1;
99 unsigned char c; 100 unsigned char c;
100 101
101 spin_lock(&timer_lock); 102 spin_lock(&timer_lock);
102 103
103 while (simc_poll(0)) { 104 while (simc_poll(0)) {
104 simc_read(0, &c, 1); 105 rd = simc_read(0, &c, 1);
106 if (rd <= 0)
107 break;
105 tty_insert_flip_char(port, c, TTY_NORMAL); 108 tty_insert_flip_char(port, c, TTY_NORMAL);
106 i++; 109 i++;
107 } 110 }
108 111
109 if (i) 112 if (i)
110 tty_flip_buffer_push(port); 113 tty_flip_buffer_push(port);
111 114 if (rd)
112 115 mod_timer(&serial_timer, jiffies + SERIAL_TIMER_VALUE);
113 mod_timer(&serial_timer, jiffies + SERIAL_TIMER_VALUE);
114 spin_unlock(&timer_lock); 116 spin_unlock(&timer_lock);
115} 117}
116 118
diff --git a/arch/xtensa/platforms/xtfpga/setup.c b/arch/xtensa/platforms/xtfpga/setup.c
index e9f65f79cf2e..b509d1f55ed5 100644
--- a/arch/xtensa/platforms/xtfpga/setup.c
+++ b/arch/xtensa/platforms/xtfpga/setup.c
@@ -223,6 +223,7 @@ static struct ethoc_platform_data ethoc_pdata = {
223 */ 223 */
224 .hwaddr = { 0x00, 0x50, 0xc2, 0x13, 0x6f, 0 }, 224 .hwaddr = { 0x00, 0x50, 0xc2, 0x13, 0x6f, 0 },
225 .phy_id = -1, 225 .phy_id = -1,
226 .big_endian = XCHAL_HAVE_BE,
226}; 227};
227 228
228static struct platform_device ethoc_device = { 229static struct platform_device ethoc_device = {
@@ -283,7 +284,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
283 .irq = DUART16552_INTNUM, 284 .irq = DUART16552_INTNUM,
284 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 285 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
285 UPF_IOREMAP, 286 UPF_IOREMAP,
286 .iotype = UPIO_MEM32, 287 .iotype = XCHAL_HAVE_BE ? UPIO_MEM32BE : UPIO_MEM32,
287 .regshift = 2, 288 .regshift = 2,
288 .uartclk = 0, /* set in xtavnet_init() */ 289 .uartclk = 0, /* set in xtavnet_init() */
289 }, 290 },
diff --git a/arch/xtensa/variants/test_kc705_hifi/include/variant/core.h b/arch/xtensa/variants/test_kc705_hifi/include/variant/core.h
new file mode 100644
index 000000000000..4a2222979f86
--- /dev/null
+++ b/arch/xtensa/variants/test_kc705_hifi/include/variant/core.h
@@ -0,0 +1,531 @@
1/*
2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
3 * processor CORE configuration
4 *
5 * See <xtensa/config/core.h>, which includes this file, for more details.
6 */
7
8/* Xtensa processor core configuration information.
9
10 Copyright (c) 1999-2014 Tensilica Inc.
11
12 Permission is hereby granted, free of charge, to any person obtaining
13 a copy of this software and associated documentation files (the
14 "Software"), to deal in the Software without restriction, including
15 without limitation the rights to use, copy, modify, merge, publish,
16 distribute, sublicense, and/or sell copies of the Software, and to
17 permit persons to whom the Software is furnished to do so, subject to
18 the following conditions:
19
20 The above copyright notice and this permission notice shall be included
21 in all copies or substantial portions of the Software.
22
23 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
26 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
27 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
28 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
29 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
30
31#ifndef _XTENSA_CORE_CONFIGURATION_H
32#define _XTENSA_CORE_CONFIGURATION_H
33
34
35/****************************************************************************
36 Parameters Useful for Any Code, USER or PRIVILEGED
37 ****************************************************************************/
38
39/*
40 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
41 * configured, and a value of 0 otherwise. These macros are always defined.
42 */
43
44
45/*----------------------------------------------------------------------
46 ISA
47 ----------------------------------------------------------------------*/
48
49#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
50#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
51#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
52#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
53#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
54#define XCHAL_HAVE_DEBUG 1 /* debug option */
55#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
56#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
57#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
58#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
59#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
60#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
61#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
62#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
63#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
64#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
65#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
66#define XCHAL_HAVE_L32R 1 /* L32R instruction */
67#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
68#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
69#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
70#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
71#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
72#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
73#define XCHAL_HAVE_ABS 1 /* ABS instruction */
74/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
75/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
76#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
77#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
78#define XCHAL_HAVE_SPECULATION 0 /* speculation */
79#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
80#define XCHAL_NUM_CONTEXTS 1 /* */
81#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
82#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
83#define XCHAL_HAVE_PRID 1 /* processor ID register */
84#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
85#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
86#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
87#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
88#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
89#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
90#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
91#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
92#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
93#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
94#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
95#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
96#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
97#define XCHAL_HAVE_FP 0 /* single prec floating point */
98#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */
99#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */
100#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */
101#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */
102#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
103#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
104#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
105#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
106#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
107#define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */
108#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
109#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
110#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
111#define XCHAL_HAVE_HIFI3 1 /* HiFi3 Audio Engine pkg */
112#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
113#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
114#define XCHAL_HAVE_HIFI_MINI 0
115#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
116#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
117#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
118#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
119#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
120#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
121#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
122#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
123#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
124#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
125#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
126#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
127#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
128
129
130/*----------------------------------------------------------------------
131 MISC
132 ----------------------------------------------------------------------*/
133
134#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
135#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
136#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
137#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
138#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
139 (1 = 5-stage, 2 = 7-stage) */
140/* In T1050, applies to selected core load and store instructions (see ISA): */
141#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
142#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
143#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
144#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
145
146#define XCHAL_SW_VERSION 1000004 /* sw version of this header */
147
148#define XCHAL_CORE_ID "test_kc705_hifi" /* alphanum core name
149 (CoreID) set in the Xtensa
150 Processor Generator */
151
152#define XCHAL_BUILD_UNIQUE_ID 0x0004983D /* 22-bit sw build ID */
153
154/*
155 * These definitions describe the hardware targeted by this software.
156 */
157#define XCHAL_HW_CONFIGID0 0xC1B3FFFE /* ConfigID hi 32 bits*/
158#define XCHAL_HW_CONFIGID1 0x1904983D /* ConfigID lo 32 bits*/
159#define XCHAL_HW_VERSION_NAME "LX5.0.4" /* full version name */
160#define XCHAL_HW_VERSION_MAJOR 2500 /* major ver# of targeted hw */
161#define XCHAL_HW_VERSION_MINOR 4 /* minor ver# of targeted hw */
162#define XCHAL_HW_VERSION 250004 /* major*100+minor */
163#define XCHAL_HW_REL_LX5 1
164#define XCHAL_HW_REL_LX5_0 1
165#define XCHAL_HW_REL_LX5_0_4 1
166#define XCHAL_HW_CONFIGID_RELIABLE 1
167/* If software targets a *range* of hardware versions, these are the bounds: */
168#define XCHAL_HW_MIN_VERSION_MAJOR 2500 /* major v of earliest tgt hw */
169#define XCHAL_HW_MIN_VERSION_MINOR 4 /* minor v of earliest tgt hw */
170#define XCHAL_HW_MIN_VERSION 250004 /* earliest targeted hw */
171#define XCHAL_HW_MAX_VERSION_MAJOR 2500 /* major v of latest tgt hw */
172#define XCHAL_HW_MAX_VERSION_MINOR 4 /* minor v of latest tgt hw */
173#define XCHAL_HW_MAX_VERSION 250004 /* latest targeted hw */
174
175
176/*----------------------------------------------------------------------
177 CACHE
178 ----------------------------------------------------------------------*/
179
180#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
181#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
182#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
183#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
184
185#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */
186#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */
187
188#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
189#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
190
191#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */
192#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
193#define XCHAL_PREFETCH_CASTOUT_LINES 1 /* dcache pref. castout bufsz */
194
195
196
197
198/****************************************************************************
199 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
200 ****************************************************************************/
201
202
203#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
204
205/*----------------------------------------------------------------------
206 CACHE
207 ----------------------------------------------------------------------*/
208
209#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
210
211/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
212
213/* Number of cache sets in log2(lines per way): */
214#define XCHAL_ICACHE_SETWIDTH 7
215#define XCHAL_DCACHE_SETWIDTH 7
216
217/* Cache set associativity (number of ways): */
218#define XCHAL_ICACHE_WAYS 4
219#define XCHAL_DCACHE_WAYS 4
220
221/* Cache features: */
222#define XCHAL_ICACHE_LINE_LOCKABLE 1
223#define XCHAL_DCACHE_LINE_LOCKABLE 1
224#define XCHAL_ICACHE_ECC_PARITY 0
225#define XCHAL_DCACHE_ECC_PARITY 0
226
227/* Cache access size in bytes (affects operation of SICW instruction): */
228#define XCHAL_ICACHE_ACCESS_SIZE 8
229#define XCHAL_DCACHE_ACCESS_SIZE 8
230
231#define XCHAL_DCACHE_BANKS 1 /* number of banks */
232
233/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
234#define XCHAL_CA_BITS 4
235
236
237/*----------------------------------------------------------------------
238 INTERNAL I/D RAM/ROMs and XLMI
239 ----------------------------------------------------------------------*/
240
241#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
242#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
243#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
244#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
245#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
246#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
247
248#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
249
250
251/*----------------------------------------------------------------------
252 INTERRUPTS and TIMERS
253 ----------------------------------------------------------------------*/
254
255#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
256#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
257#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
258#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
259#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
260#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
261#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
262#define XCHAL_NUM_EXTINTERRUPTS 16 /* num of external interrupts */
263#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
264 (not including level zero) */
265#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
266 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
267
268/* Masks of interrupts at each interrupt level: */
269#define XCHAL_INTLEVEL1_MASK 0x001F00BF
270#define XCHAL_INTLEVEL2_MASK 0x00000140
271#define XCHAL_INTLEVEL3_MASK 0x00200E00
272#define XCHAL_INTLEVEL4_MASK 0x00009000
273#define XCHAL_INTLEVEL5_MASK 0x00002000
274#define XCHAL_INTLEVEL6_MASK 0x00000000
275#define XCHAL_INTLEVEL7_MASK 0x00004000
276
277/* Masks of interrupts at each range 1..n of interrupt levels: */
278#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F00BF
279#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F01FF
280#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F0FFF
281#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF
282#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF
283#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF
284#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
285
286/* Level of each interrupt: */
287#define XCHAL_INT0_LEVEL 1
288#define XCHAL_INT1_LEVEL 1
289#define XCHAL_INT2_LEVEL 1
290#define XCHAL_INT3_LEVEL 1
291#define XCHAL_INT4_LEVEL 1
292#define XCHAL_INT5_LEVEL 1
293#define XCHAL_INT6_LEVEL 2
294#define XCHAL_INT7_LEVEL 1
295#define XCHAL_INT8_LEVEL 2
296#define XCHAL_INT9_LEVEL 3
297#define XCHAL_INT10_LEVEL 3
298#define XCHAL_INT11_LEVEL 3
299#define XCHAL_INT12_LEVEL 4
300#define XCHAL_INT13_LEVEL 5
301#define XCHAL_INT14_LEVEL 7
302#define XCHAL_INT15_LEVEL 4
303#define XCHAL_INT16_LEVEL 1
304#define XCHAL_INT17_LEVEL 1
305#define XCHAL_INT18_LEVEL 1
306#define XCHAL_INT19_LEVEL 1
307#define XCHAL_INT20_LEVEL 1
308#define XCHAL_INT21_LEVEL 3
309#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
310#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
311#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
312 EXCSAVE/EPS/EPC_n, RFI n) */
313
314/* Type of each interrupt: */
315#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
316#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
317#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
318#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
319#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
320#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
321#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
322#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
323#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
324#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
325#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
326#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
327#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
328#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
329#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
330#define XCHAL_INT15_TYPE XTHAL_INTTYPE_PROFILING
331#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
332#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
333#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
334#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
335#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
336#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
337
338/* Masks of interrupts for each type of interrupt: */
339#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
340#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
341#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F0000
342#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F
343#define XCHAL_INTTYPE_MASK_TIMER 0x00002440
344#define XCHAL_INTTYPE_MASK_NMI 0x00004000
345#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
346#define XCHAL_INTTYPE_MASK_PROFILING 0x00008000
347
348/* Interrupt numbers assigned to specific interrupt sources: */
349#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
350#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
351#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
352#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
353#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
354#define XCHAL_PROFILING_INTERRUPT 15 /* profiling interrupt */
355
356/* Interrupt numbers for levels at which only one interrupt is configured: */
357#define XCHAL_INTLEVEL5_NUM 13
358#define XCHAL_INTLEVEL7_NUM 14
359/* (There are many interrupts each at level(s) 1, 2, 3, 4.) */
360
361
362/*
363 * External interrupt mapping.
364 * These macros describe how Xtensa processor interrupt numbers
365 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
366 * map to external BInterrupt<n> pins, for those interrupts
367 * configured as external (level-triggered, edge-triggered, or NMI).
368 * See the Xtensa processor databook for more details.
369 */
370
371/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
372#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
373#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
374#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
375#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
376#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
377#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
378#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
379#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
380#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
381#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
382#define XCHAL_EXTINT10_NUM 16 /* (intlevel 1) */
383#define XCHAL_EXTINT11_NUM 17 /* (intlevel 1) */
384#define XCHAL_EXTINT12_NUM 18 /* (intlevel 1) */
385#define XCHAL_EXTINT13_NUM 19 /* (intlevel 1) */
386#define XCHAL_EXTINT14_NUM 20 /* (intlevel 1) */
387#define XCHAL_EXTINT15_NUM 21 /* (intlevel 3) */
388/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
389#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
390#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
391#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
392#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
393#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
394#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
395#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */
396#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */
397#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */
398#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */
399#define XCHAL_INT16_EXTNUM 10 /* (intlevel 1) */
400#define XCHAL_INT17_EXTNUM 11 /* (intlevel 1) */
401#define XCHAL_INT18_EXTNUM 12 /* (intlevel 1) */
402#define XCHAL_INT19_EXTNUM 13 /* (intlevel 1) */
403#define XCHAL_INT20_EXTNUM 14 /* (intlevel 1) */
404#define XCHAL_INT21_EXTNUM 15 /* (intlevel 3) */
405
406
407/*----------------------------------------------------------------------
408 EXCEPTIONS and VECTORS
409 ----------------------------------------------------------------------*/
410
411#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
412 number: 1 == XEA1 (old)
413 2 == XEA2 (new)
414 0 == XEAX (extern) or TX */
415#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
416#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
417#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
418#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
419#define XCHAL_HAVE_HALT 0 /* halt architecture option */
420#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
421#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
422#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
423#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
424#define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */
425#define XCHAL_VECBASE_RESET_PADDR 0x00002000
426#define XCHAL_RESET_VECBASE_OVERLAP 0
427
428#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000
429#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000
430#define XCHAL_RESET_VECTOR1_VADDR 0x00001000
431#define XCHAL_RESET_VECTOR1_PADDR 0x00001000
432#define XCHAL_RESET_VECTOR_VADDR 0xFE000000
433#define XCHAL_RESET_VECTOR_PADDR 0xFE000000
434#define XCHAL_USER_VECOFS 0x00000340
435#define XCHAL_USER_VECTOR_VADDR 0x00002340
436#define XCHAL_USER_VECTOR_PADDR 0x00002340
437#define XCHAL_KERNEL_VECOFS 0x00000300
438#define XCHAL_KERNEL_VECTOR_VADDR 0x00002300
439#define XCHAL_KERNEL_VECTOR_PADDR 0x00002300
440#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
441#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000023C0
442#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000023C0
443#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
444#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
445#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
446#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
447#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
448#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
449#define XCHAL_WINDOW_VECTORS_VADDR 0x00002000
450#define XCHAL_WINDOW_VECTORS_PADDR 0x00002000
451#define XCHAL_INTLEVEL2_VECOFS 0x00000180
452#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00002180
453#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00002180
454#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
455#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x000021C0
456#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000021C0
457#define XCHAL_INTLEVEL4_VECOFS 0x00000200
458#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200
459#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200
460#define XCHAL_INTLEVEL5_VECOFS 0x00000240
461#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x00002240
462#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00002240
463#define XCHAL_INTLEVEL6_VECOFS 0x00000280
464#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280
465#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00002280
466#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
467#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
468#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
469#define XCHAL_NMI_VECOFS 0x000002C0
470#define XCHAL_NMI_VECTOR_VADDR 0x000022C0
471#define XCHAL_NMI_VECTOR_PADDR 0x000022C0
472#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
473#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
474#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
475
476
477/*----------------------------------------------------------------------
478 DEBUG MODULE
479 ----------------------------------------------------------------------*/
480
481/* Misc */
482#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
483#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
484#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
485
486/* On-Chip Debug (OCD) */
487#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
488#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
489#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
490#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
491#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
492
493/* TRAX (in core) */
494#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */
495#define XCHAL_TRAX_MEM_SIZE 262144 /* TRAX memory size in bytes */
496#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */
497#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
498#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
499
500/* Perf counters */
501#define XCHAL_NUM_PERF_COUNTERS 8 /* performance counters */
502
503
504/*----------------------------------------------------------------------
505 MMU
506 ----------------------------------------------------------------------*/
507
508/* See core-matmap.h header file for more details. */
509
510#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
511#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
512#define XCHAL_SPANNING_WAY 6 /* TLB spanning way number */
513#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
514#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
515#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
516#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
517#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
518 [autorefill] and protection)
519 usable for an MMU-based OS */
520/* If none of the above last 4 are set, it's a custom TLB configuration. */
521#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
522#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
523
524#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */
525#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */
526#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */
527
528#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
529
530
531#endif /* _XTENSA_CORE_CONFIGURATION_H */
diff --git a/arch/xtensa/variants/test_kc705_hifi/include/variant/tie-asm.h b/arch/xtensa/variants/test_kc705_hifi/include/variant/tie-asm.h
new file mode 100644
index 000000000000..378163c0a7ad
--- /dev/null
+++ b/arch/xtensa/variants/test_kc705_hifi/include/variant/tie-asm.h
@@ -0,0 +1,328 @@
1/*
2 * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
3 *
4 * NOTE: This header file is not meant to be included directly.
5 */
6
7/* This header file contains assembly-language definitions (assembly
8 macros, etc.) for this specific Xtensa processor's TIE extensions
9 and options. It is customized to this Xtensa processor configuration.
10
11 Copyright (c) 1999-2014 Tensilica Inc.
12
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
15 "Software"), to deal in the Software without restriction, including
16 without limitation the rights to use, copy, modify, merge, publish,
17 distribute, sublicense, and/or sell copies of the Software, and to
18 permit persons to whom the Software is furnished to do so, subject to
19 the following conditions:
20
21 The above copyright notice and this permission notice shall be included
22 in all copies or substantial portions of the Software.
23
24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
27 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
30 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
31
32#ifndef _XTENSA_CORE_TIE_ASM_H
33#define _XTENSA_CORE_TIE_ASM_H
34
35/* Selection parameter values for save-area save/restore macros: */
36/* Option vs. TIE: */
37#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
38#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
39#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
40/* Whether used automatically by compiler: */
41#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
42#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
43#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
44/* ABI handling across function calls: */
45#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
46#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
47#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
48#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
49/* Misc */
50#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
51#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
52 | ((ccuse) & XTHAL_SAS_ANYCC) \
53 | ((abi) & XTHAL_SAS_ANYABI) )
54
55
56
57 /*
58 * Macro to save all non-coprocessor (extra) custom TIE and optional state
59 * (not including zero-overhead loop registers).
60 * Required parameters:
61 * ptr Save area pointer address register (clobbered)
62 * (register must contain a 4 byte aligned address).
63 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
64 * registers are clobbered, the remaining are unused).
65 * Optional parameters:
66 * continue If macro invoked as part of a larger store sequence, set to 1
67 * if this is not the first in the sequence. Defaults to 0.
68 * ofs Offset from start of larger sequence (from value of first ptr
69 * in sequence) at which to store. Defaults to next available space
70 * (or 0 if <continue> is 0).
71 * select Select what category(ies) of registers to store, as a bitmask
72 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
73 * alloc Select what category(ies) of registers to allocate; if any
74 * category is selected here that is not in <select>, space for
75 * the corresponding registers is skipped without doing any store.
76 */
77 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
78 xchal_sa_start \continue, \ofs
79 // Optional global register used by default by the compiler:
80 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
81 xchal_sa_align \ptr, 0, 1020, 4, 4
82 rur.THREADPTR \at1 // threadptr option
83 s32i \at1, \ptr, .Lxchal_ofs_+0
84 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
85 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
86 xchal_sa_align \ptr, 0, 1020, 4, 4
87 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
88 .endif
89 // Optional caller-saved registers used by default by the compiler:
90 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
91 xchal_sa_align \ptr, 0, 1016, 4, 4
92 rsr.ACCLO \at1 // MAC16 option
93 s32i \at1, \ptr, .Lxchal_ofs_+0
94 rsr.ACCHI \at1 // MAC16 option
95 s32i \at1, \ptr, .Lxchal_ofs_+4
96 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
97 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
98 xchal_sa_align \ptr, 0, 1016, 4, 4
99 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
100 .endif
101 // Optional caller-saved registers not used by default by the compiler:
102 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
103 xchal_sa_align \ptr, 0, 1000, 4, 4
104 rsr.M0 \at1 // MAC16 option
105 s32i \at1, \ptr, .Lxchal_ofs_+0
106 rsr.M1 \at1 // MAC16 option
107 s32i \at1, \ptr, .Lxchal_ofs_+4
108 rsr.M2 \at1 // MAC16 option
109 s32i \at1, \ptr, .Lxchal_ofs_+8
110 rsr.M3 \at1 // MAC16 option
111 s32i \at1, \ptr, .Lxchal_ofs_+12
112 rsr.BR \at1 // boolean option
113 s32i \at1, \ptr, .Lxchal_ofs_+16
114 rsr.SCOMPARE1 \at1 // conditional store option
115 s32i \at1, \ptr, .Lxchal_ofs_+20
116 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24
117 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
118 xchal_sa_align \ptr, 0, 1000, 4, 4
119 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24
120 .endif
121 .endm // xchal_ncp_store
122
123 /*
124 * Macro to restore all non-coprocessor (extra) custom TIE and optional state
125 * (not including zero-overhead loop registers).
126 * Required parameters:
127 * ptr Save area pointer address register (clobbered)
128 * (register must contain a 4 byte aligned address).
129 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
130 * registers are clobbered, the remaining are unused).
131 * Optional parameters:
132 * continue If macro invoked as part of a larger load sequence, set to 1
133 * if this is not the first in the sequence. Defaults to 0.
134 * ofs Offset from start of larger sequence (from value of first ptr
135 * in sequence) at which to load. Defaults to next available space
136 * (or 0 if <continue> is 0).
137 * select Select what category(ies) of registers to load, as a bitmask
138 * (see XTHAL_SAS_xxx constants). Defaults to all registers.
139 * alloc Select what category(ies) of registers to allocate; if any
140 * category is selected here that is not in <select>, space for
141 * the corresponding registers is skipped without doing any load.
142 */
143 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
144 xchal_sa_start \continue, \ofs
145 // Optional global register used by default by the compiler:
146 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
147 xchal_sa_align \ptr, 0, 1020, 4, 4
148 l32i \at1, \ptr, .Lxchal_ofs_+0
149 wur.THREADPTR \at1 // threadptr option
150 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
151 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
152 xchal_sa_align \ptr, 0, 1020, 4, 4
153 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
154 .endif
155 // Optional caller-saved registers used by default by the compiler:
156 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
157 xchal_sa_align \ptr, 0, 1016, 4, 4
158 l32i \at1, \ptr, .Lxchal_ofs_+0
159 wsr.ACCLO \at1 // MAC16 option
160 l32i \at1, \ptr, .Lxchal_ofs_+4
161 wsr.ACCHI \at1 // MAC16 option
162 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
163 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
164 xchal_sa_align \ptr, 0, 1016, 4, 4
165 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
166 .endif
167 // Optional caller-saved registers not used by default by the compiler:
168 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
169 xchal_sa_align \ptr, 0, 1000, 4, 4
170 l32i \at1, \ptr, .Lxchal_ofs_+0
171 wsr.M0 \at1 // MAC16 option
172 l32i \at1, \ptr, .Lxchal_ofs_+4
173 wsr.M1 \at1 // MAC16 option
174 l32i \at1, \ptr, .Lxchal_ofs_+8
175 wsr.M2 \at1 // MAC16 option
176 l32i \at1, \ptr, .Lxchal_ofs_+12
177 wsr.M3 \at1 // MAC16 option
178 l32i \at1, \ptr, .Lxchal_ofs_+16
179 wsr.BR \at1 // boolean option
180 l32i \at1, \ptr, .Lxchal_ofs_+20
181 wsr.SCOMPARE1 \at1 // conditional store option
182 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24
183 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
184 xchal_sa_align \ptr, 0, 1000, 4, 4
185 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24
186 .endif
187 .endm // xchal_ncp_load
188
189
190#define XCHAL_NCP_NUM_ATMPS 1
191
192
193
194
195 /*
196 * Macro to save the state of TIE coprocessor AudioEngineLX.
197 * Required parameters:
198 * ptr Save area pointer address register (clobbered)
199 * (register must contain a 8 byte aligned address).
200 * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
201 * registers are clobbered, the remaining are unused).
202 * Optional parameters are the same as for xchal_ncp_store.
203 */
204#define xchal_cp_AudioEngineLX_store xchal_cp1_store
205 .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
206 xchal_sa_start \continue, \ofs
207 // Custom caller-saved registers not used by default by the compiler:
208 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
209 xchal_sa_align \ptr, 0, 0, 8, 8
210 rur.AE_OVF_SAR \at1 // ureg 240
211 s32i \at1, \ptr, .Lxchal_ofs_+0
212 rur.AE_BITHEAD \at1 // ureg 241
213 s32i \at1, \ptr, .Lxchal_ofs_+4
214 rur.AE_TS_FTS_BU_BP \at1 // ureg 242
215 s32i \at1, \ptr, .Lxchal_ofs_+8
216 rur.AE_CW_SD_NO \at1 // ureg 243
217 s32i \at1, \ptr, .Lxchal_ofs_+12
218 rur.AE_CBEGIN0 \at1 // ureg 246
219 s32i \at1, \ptr, .Lxchal_ofs_+16
220 rur.AE_CEND0 \at1 // ureg 247
221 s32i \at1, \ptr, .Lxchal_ofs_+20
222 AE_S64.I aed0, \ptr, .Lxchal_ofs_+24
223 AE_S64.I aed1, \ptr, .Lxchal_ofs_+32
224 AE_S64.I aed2, \ptr, .Lxchal_ofs_+40
225 AE_S64.I aed3, \ptr, .Lxchal_ofs_+48
226 AE_S64.I aed4, \ptr, .Lxchal_ofs_+56
227 addi \ptr, \ptr, 64
228 AE_S64.I aed5, \ptr, .Lxchal_ofs_+0
229 AE_S64.I aed6, \ptr, .Lxchal_ofs_+8
230 AE_S64.I aed7, \ptr, .Lxchal_ofs_+16
231 AE_S64.I aed8, \ptr, .Lxchal_ofs_+24
232 AE_S64.I aed9, \ptr, .Lxchal_ofs_+32
233 AE_S64.I aed10, \ptr, .Lxchal_ofs_+40
234 AE_S64.I aed11, \ptr, .Lxchal_ofs_+48
235 AE_S64.I aed12, \ptr, .Lxchal_ofs_+56
236 addi \ptr, \ptr, 64
237 AE_S64.I aed13, \ptr, .Lxchal_ofs_+0
238 AE_S64.I aed14, \ptr, .Lxchal_ofs_+8
239 AE_S64.I aed15, \ptr, .Lxchal_ofs_+16
240 AE_SALIGN64.I u0, \ptr, .Lxchal_ofs_+24
241 AE_SALIGN64.I u1, \ptr, .Lxchal_ofs_+32
242 AE_SALIGN64.I u2, \ptr, .Lxchal_ofs_+40
243 AE_SALIGN64.I u3, \ptr, .Lxchal_ofs_+48
244 .set .Lxchal_pofs_, .Lxchal_pofs_ + 128
245 .set .Lxchal_ofs_, .Lxchal_ofs_ + 56
246 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
247 xchal_sa_align \ptr, 0, 0, 8, 8
248 .set .Lxchal_ofs_, .Lxchal_ofs_ + 184
249 .endif
250 .endm // xchal_cp1_store
251
252 /*
253 * Macro to restore the state of TIE coprocessor AudioEngineLX.
254 * Required parameters:
255 * ptr Save area pointer address register (clobbered)
256 * (register must contain a 8 byte aligned address).
257 * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
258 * registers are clobbered, the remaining are unused).
259 * Optional parameters are the same as for xchal_ncp_load.
260 */
261#define xchal_cp_AudioEngineLX_load xchal_cp1_load
262 .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
263 xchal_sa_start \continue, \ofs
264 // Custom caller-saved registers not used by default by the compiler:
265 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
266 xchal_sa_align \ptr, 0, 0, 8, 8
267 l32i \at1, \ptr, .Lxchal_ofs_+0
268 wur.AE_OVF_SAR \at1 // ureg 240
269 l32i \at1, \ptr, .Lxchal_ofs_+4
270 wur.AE_BITHEAD \at1 // ureg 241
271 l32i \at1, \ptr, .Lxchal_ofs_+8
272 wur.AE_TS_FTS_BU_BP \at1 // ureg 242
273 l32i \at1, \ptr, .Lxchal_ofs_+12
274 wur.AE_CW_SD_NO \at1 // ureg 243
275 l32i \at1, \ptr, .Lxchal_ofs_+16
276 wur.AE_CBEGIN0 \at1 // ureg 246
277 l32i \at1, \ptr, .Lxchal_ofs_+20
278 wur.AE_CEND0 \at1 // ureg 247
279 AE_L64.I aed0, \ptr, .Lxchal_ofs_+24
280 AE_L64.I aed1, \ptr, .Lxchal_ofs_+32
281 AE_L64.I aed2, \ptr, .Lxchal_ofs_+40
282 AE_L64.I aed3, \ptr, .Lxchal_ofs_+48
283 AE_L64.I aed4, \ptr, .Lxchal_ofs_+56
284 addi \ptr, \ptr, 64
285 AE_L64.I aed5, \ptr, .Lxchal_ofs_+0
286 AE_L64.I aed6, \ptr, .Lxchal_ofs_+8
287 AE_L64.I aed7, \ptr, .Lxchal_ofs_+16
288 AE_L64.I aed8, \ptr, .Lxchal_ofs_+24
289 AE_L64.I aed9, \ptr, .Lxchal_ofs_+32
290 AE_L64.I aed10, \ptr, .Lxchal_ofs_+40
291 AE_L64.I aed11, \ptr, .Lxchal_ofs_+48
292 AE_L64.I aed12, \ptr, .Lxchal_ofs_+56
293 addi \ptr, \ptr, 64
294 AE_L64.I aed13, \ptr, .Lxchal_ofs_+0
295 AE_L64.I aed14, \ptr, .Lxchal_ofs_+8
296 AE_L64.I aed15, \ptr, .Lxchal_ofs_+16
297 AE_LALIGN64.I u0, \ptr, .Lxchal_ofs_+24
298 AE_LALIGN64.I u1, \ptr, .Lxchal_ofs_+32
299 AE_LALIGN64.I u2, \ptr, .Lxchal_ofs_+40
300 AE_LALIGN64.I u3, \ptr, .Lxchal_ofs_+48
301 .set .Lxchal_pofs_, .Lxchal_pofs_ + 128
302 .set .Lxchal_ofs_, .Lxchal_ofs_ + 56
303 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
304 xchal_sa_align \ptr, 0, 0, 8, 8
305 .set .Lxchal_ofs_, .Lxchal_ofs_ + 184
306 .endif
307 .endm // xchal_cp1_load
308
309#define XCHAL_CP1_NUM_ATMPS 1
310#define XCHAL_SA_NUM_ATMPS 1
311
312 /* Empty macros for unconfigured coprocessors: */
313 .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
314 .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
315 .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
316 .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
317 .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
318 .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
319 .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
320 .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
321 .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
322 .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
323 .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
324 .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
325 .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
326 .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
327
328#endif /*_XTENSA_CORE_TIE_ASM_H*/
diff --git a/arch/xtensa/variants/test_kc705_hifi/include/variant/tie.h b/arch/xtensa/variants/test_kc705_hifi/include/variant/tie.h
new file mode 100644
index 000000000000..e39fea64391e
--- /dev/null
+++ b/arch/xtensa/variants/test_kc705_hifi/include/variant/tie.h
@@ -0,0 +1,189 @@
1/*
2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
3 *
4 * NOTE: This header file is not meant to be included directly.
5 */
6
7/* This header file describes this specific Xtensa processor's TIE extensions
8 that extend basic Xtensa core functionality. It is customized to this
9 Xtensa processor configuration.
10
11 Copyright (c) 1999-2014 Tensilica Inc.
12
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
15 "Software"), to deal in the Software without restriction, including
16 without limitation the rights to use, copy, modify, merge, publish,
17 distribute, sublicense, and/or sell copies of the Software, and to
18 permit persons to whom the Software is furnished to do so, subject to
19 the following conditions:
20
21 The above copyright notice and this permission notice shall be included
22 in all copies or substantial portions of the Software.
23
24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
27 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
30 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
31
32#ifndef _XTENSA_CORE_TIE_H
33#define _XTENSA_CORE_TIE_H
34
35#define XCHAL_CP_NUM 2 /* number of coprocessors */
36#define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37#define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */
38#define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
39
40/* Basic parameters of each coprocessor: */
41#define XCHAL_CP1_NAME "AudioEngineLX"
42#define XCHAL_CP1_IDENT AudioEngineLX
43#define XCHAL_CP1_SA_SIZE 184 /* size of state save area */
44#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
45#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
46#define XCHAL_CP7_NAME "XTIOP"
47#define XCHAL_CP7_IDENT XTIOP
48#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
49#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
50#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
51
52/* Filler info for unassigned coprocessors, to simplify arrays etc: */
53#define XCHAL_CP0_SA_SIZE 0
54#define XCHAL_CP0_SA_ALIGN 1
55#define XCHAL_CP2_SA_SIZE 0
56#define XCHAL_CP2_SA_ALIGN 1
57#define XCHAL_CP3_SA_SIZE 0
58#define XCHAL_CP3_SA_ALIGN 1
59#define XCHAL_CP4_SA_SIZE 0
60#define XCHAL_CP4_SA_ALIGN 1
61#define XCHAL_CP5_SA_SIZE 0
62#define XCHAL_CP5_SA_ALIGN 1
63#define XCHAL_CP6_SA_SIZE 0
64#define XCHAL_CP6_SA_ALIGN 1
65
66/* Save area for non-coprocessor optional and custom (TIE) state: */
67#define XCHAL_NCP_SA_SIZE 36
68#define XCHAL_NCP_SA_ALIGN 4
69
70/* Total save area for optional and custom state (NCP + CPn): */
71#define XCHAL_TOTAL_SA_SIZE 240 /* with 16-byte align padding */
72#define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */
73
74/*
75 * Detailed contents of save areas.
76 * NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
77 * before expanding the XCHAL_xxx_SA_LIST() macros.
78 *
79 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
80 * dbnum,base,regnum,bitsz,gapsz,reset,x...)
81 *
82 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
83 * ccused = set if used by compiler without special options or code
84 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
85 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
86 * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
87 * name = lowercase reg name (no quotes)
88 * galign = group byte alignment (power of 2) (galign >= align)
89 * align = register byte alignment (power of 2)
90 * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
91 * (not including any pad bytes required to galign this or next reg)
92 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
93 * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
94 * regnum = reg index in regfile, or special/TIE-user reg number
95 * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
96 * gapsz = intervening bits, if bitsz bits not stored contiguously
97 * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
98 * reset = register reset value (or 0 if undefined at reset)
99 * x = reserved for future use (0 until then)
100 *
101 * To filter out certain registers, e.g. to expand only the non-global
102 * registers used by the compiler, you can do something like this:
103 *
104 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
105 * #define SELCC0(p...)
106 * #define SELCC1(abikind,p...) SELAK##abikind(p)
107 * #define SELAK0(p...) REG(p)
108 * #define SELAK1(p...) REG(p)
109 * #define SELAK2(p...)
110 * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
111 * ...what you want to expand...
112 */
113
114#define XCHAL_NCP_SA_NUM 9
115#define XCHAL_NCP_SA_LIST(s) \
116 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
117 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
118 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
120 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
121 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
122 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
123 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
124 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0)
125
126#define XCHAL_CP0_SA_NUM 0
127#define XCHAL_CP0_SA_LIST(s) /* empty */
128
129#define XCHAL_CP1_SA_NUM 26
130#define XCHAL_CP1_SA_LIST(s) \
131 XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 8,0,0,0) \
132 XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \
133 XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \
134 XCHAL_SA_REG(s,0,0,1,0, ae_cw_sd_no, 4, 4, 4,0x03F3, ur,243, 29,0,0,0) \
135 XCHAL_SA_REG(s,0,0,1,0, ae_cbegin0, 4, 4, 4,0x03F6, ur,246, 32,0,0,0) \
136 XCHAL_SA_REG(s,0,0,1,0, ae_cend0, 4, 4, 4,0x03F7, ur,247, 32,0,0,0) \
137 XCHAL_SA_REG(s,0,0,2,0, aed0, 8, 8, 8,0x1010, aed,0 , 64,0,0,0) \
138 XCHAL_SA_REG(s,0,0,2,0, aed1, 8, 8, 8,0x1011, aed,1 , 64,0,0,0) \
139 XCHAL_SA_REG(s,0,0,2,0, aed2, 8, 8, 8,0x1012, aed,2 , 64,0,0,0) \
140 XCHAL_SA_REG(s,0,0,2,0, aed3, 8, 8, 8,0x1013, aed,3 , 64,0,0,0) \
141 XCHAL_SA_REG(s,0,0,2,0, aed4, 8, 8, 8,0x1014, aed,4 , 64,0,0,0) \
142 XCHAL_SA_REG(s,0,0,2,0, aed5, 8, 8, 8,0x1015, aed,5 , 64,0,0,0) \
143 XCHAL_SA_REG(s,0,0,2,0, aed6, 8, 8, 8,0x1016, aed,6 , 64,0,0,0) \
144 XCHAL_SA_REG(s,0,0,2,0, aed7, 8, 8, 8,0x1017, aed,7 , 64,0,0,0) \
145 XCHAL_SA_REG(s,0,0,2,0, aed8, 8, 8, 8,0x1018, aed,8 , 64,0,0,0) \
146 XCHAL_SA_REG(s,0,0,2,0, aed9, 8, 8, 8,0x1019, aed,9 , 64,0,0,0) \
147 XCHAL_SA_REG(s,0,0,2,0, aed10, 8, 8, 8,0x101A, aed,10 , 64,0,0,0) \
148 XCHAL_SA_REG(s,0,0,2,0, aed11, 8, 8, 8,0x101B, aed,11 , 64,0,0,0) \
149 XCHAL_SA_REG(s,0,0,2,0, aed12, 8, 8, 8,0x101C, aed,12 , 64,0,0,0) \
150 XCHAL_SA_REG(s,0,0,2,0, aed13, 8, 8, 8,0x101D, aed,13 , 64,0,0,0) \
151 XCHAL_SA_REG(s,0,0,2,0, aed14, 8, 8, 8,0x101E, aed,14 , 64,0,0,0) \
152 XCHAL_SA_REG(s,0,0,2,0, aed15, 8, 8, 8,0x101F, aed,15 , 64,0,0,0) \
153 XCHAL_SA_REG(s,0,0,2,0, u0, 8, 8, 8,0x1020, u,0 , 64,0,0,0) \
154 XCHAL_SA_REG(s,0,0,2,0, u1, 8, 8, 8,0x1021, u,1 , 64,0,0,0) \
155 XCHAL_SA_REG(s,0,0,2,0, u2, 8, 8, 8,0x1022, u,2 , 64,0,0,0) \
156 XCHAL_SA_REG(s,0,0,2,0, u3, 8, 8, 8,0x1023, u,3 , 64,0,0,0)
157
158#define XCHAL_CP2_SA_NUM 0
159#define XCHAL_CP2_SA_LIST(s) /* empty */
160
161#define XCHAL_CP3_SA_NUM 0
162#define XCHAL_CP3_SA_LIST(s) /* empty */
163
164#define XCHAL_CP4_SA_NUM 0
165#define XCHAL_CP4_SA_LIST(s) /* empty */
166
167#define XCHAL_CP5_SA_NUM 0
168#define XCHAL_CP5_SA_LIST(s) /* empty */
169
170#define XCHAL_CP6_SA_NUM 0
171#define XCHAL_CP6_SA_LIST(s) /* empty */
172
173#define XCHAL_CP7_SA_NUM 0
174#define XCHAL_CP7_SA_LIST(s) /* empty */
175
176/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
177#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8
178/* Byte length of instruction from its first byte, per FLIX. */
179#define XCHAL_BYTE0_FORMAT_LENGTHS \
180 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
181 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
182 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
183 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
184 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
185 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
186 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
187 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8
188
189#endif /*_XTENSA_CORE_TIE_H*/
diff --git a/arch/xtensa/variants/test_mmuhifi_c3/include/variant/core.h b/arch/xtensa/variants/test_mmuhifi_c3/include/variant/core.h
new file mode 100644
index 000000000000..7c5d3a22da12
--- /dev/null
+++ b/arch/xtensa/variants/test_mmuhifi_c3/include/variant/core.h
@@ -0,0 +1,383 @@
1/*
2 * Xtensa processor core configuration information.
3 *
4 * This file is subject to the terms and conditions of version 2.1 of the GNU
5 * Lesser General Public License as published by the Free Software Foundation.
6 *
7 * Copyright (c) 1999-2009 Tensilica Inc.
8 */
9
10#ifndef _XTENSA_CORE_CONFIGURATION_H
11#define _XTENSA_CORE_CONFIGURATION_H
12
13
14/****************************************************************************
15 Parameters Useful for Any Code, USER or PRIVILEGED
16 ****************************************************************************/
17
18/*
19 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
20 * configured, and a value of 0 otherwise. These macros are always defined.
21 */
22
23
24/*----------------------------------------------------------------------
25 ISA
26 ----------------------------------------------------------------------*/
27
28#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
29#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
30#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
31#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
32#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
33#define XCHAL_HAVE_DEBUG 1 /* debug option */
34#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
35#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
36#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
37#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
38#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
39#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
40#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
41#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
42#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
43#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */
44#define XCHAL_HAVE_L32R 1 /* L32R instruction */
45#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
46#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
47#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
48#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
49#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
50#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
51#define XCHAL_HAVE_ABS 1 /* ABS instruction */
52/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
53/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
54#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
55#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
56#define XCHAL_HAVE_SPECULATION 0 /* speculation */
57#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
58#define XCHAL_NUM_CONTEXTS 1 /* */
59#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
60#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
61#define XCHAL_HAVE_PRID 1 /* processor ID register */
62#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
63#define XCHAL_HAVE_MP_INTERRUPTS 1 /* interrupt distributor port */
64#define XCHAL_HAVE_MP_RUNSTALL 1 /* core RunStall control port */
65#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
66#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
67#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
68#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */
69#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
70#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
71#define XCHAL_HAVE_FP 0 /* floating point pkg */
72#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
73#define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */
74#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
75#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
76#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
77#define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */
78#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
79
80
81/*----------------------------------------------------------------------
82 MISC
83 ----------------------------------------------------------------------*/
84
85#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
86#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
87#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
88/* In T1050, applies to selected core load and store instructions (see ISA): */
89#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
90#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
91#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
92#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
93
94#define XCHAL_SW_VERSION 800000 /* sw version of this header */
95
96#define XCHAL_CORE_ID "test_mmuhifi_c3" /* alphanum core name
97 (CoreID) set in the Xtensa
98 Processor Generator */
99
100#define XCHAL_CORE_DESCRIPTION "test_mmuhifi_c3"
101#define XCHAL_BUILD_UNIQUE_ID 0x00005A6A /* 22-bit sw build ID */
102
103/*
104 * These definitions describe the hardware targeted by this software.
105 */
106#define XCHAL_HW_CONFIGID0 0xC1B3CBFE /* ConfigID hi 32 bits*/
107#define XCHAL_HW_CONFIGID1 0x10405A6A /* ConfigID lo 32 bits*/
108#define XCHAL_HW_VERSION_NAME "LX3.0.0" /* full version name */
109#define XCHAL_HW_VERSION_MAJOR 2300 /* major ver# of targeted hw */
110#define XCHAL_HW_VERSION_MINOR 0 /* minor ver# of targeted hw */
111#define XCHAL_HW_VERSION 230000 /* major*100+minor */
112#define XCHAL_HW_REL_LX3 1
113#define XCHAL_HW_REL_LX3_0 1
114#define XCHAL_HW_REL_LX3_0_0 1
115#define XCHAL_HW_CONFIGID_RELIABLE 1
116/* If software targets a *range* of hardware versions, these are the bounds: */
117#define XCHAL_HW_MIN_VERSION_MAJOR 2300 /* major v of earliest tgt hw */
118#define XCHAL_HW_MIN_VERSION_MINOR 0 /* minor v of earliest tgt hw */
119#define XCHAL_HW_MIN_VERSION 230000 /* earliest targeted hw */
120#define XCHAL_HW_MAX_VERSION_MAJOR 2300 /* major v of latest tgt hw */
121#define XCHAL_HW_MAX_VERSION_MINOR 0 /* minor v of latest tgt hw */
122#define XCHAL_HW_MAX_VERSION 230000 /* latest targeted hw */
123
124
125/*----------------------------------------------------------------------
126 CACHE
127 ----------------------------------------------------------------------*/
128
129#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
130#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
131#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
132#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
133
134#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */
135#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */
136
137#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
138#define XCHAL_DCACHE_IS_COHERENT 1 /* MP coherence feature */
139
140
141
142
143/****************************************************************************
144 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
145 ****************************************************************************/
146
147
148#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
149
150/*----------------------------------------------------------------------
151 CACHE
152 ----------------------------------------------------------------------*/
153
154#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
155
156/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
157
158/* Number of cache sets in log2(lines per way): */
159#define XCHAL_ICACHE_SETWIDTH 8
160#define XCHAL_DCACHE_SETWIDTH 8
161
162/* Cache set associativity (number of ways): */
163#define XCHAL_ICACHE_WAYS 2
164#define XCHAL_DCACHE_WAYS 2
165
166/* Cache features: */
167#define XCHAL_ICACHE_LINE_LOCKABLE 0
168#define XCHAL_DCACHE_LINE_LOCKABLE 0
169#define XCHAL_ICACHE_ECC_PARITY 0
170#define XCHAL_DCACHE_ECC_PARITY 0
171
172/* Cache access size in bytes (affects operation of SICW instruction): */
173#define XCHAL_ICACHE_ACCESS_SIZE 8
174#define XCHAL_DCACHE_ACCESS_SIZE 8
175
176/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
177#define XCHAL_CA_BITS 4
178
179
180/*----------------------------------------------------------------------
181 INTERNAL I/D RAM/ROMs and XLMI
182 ----------------------------------------------------------------------*/
183
184#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
185#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
186#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
187#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
188#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
189#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
190
191
192/*----------------------------------------------------------------------
193 INTERRUPTS and TIMERS
194 ----------------------------------------------------------------------*/
195
196#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
197#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
198#define XCHAL_HAVE_NMI 0 /* non-maskable interrupt */
199#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
200#define XCHAL_NUM_TIMERS 2 /* number of CCOMPAREn regs */
201#define XCHAL_NUM_INTERRUPTS 12 /* number of interrupts */
202#define XCHAL_NUM_INTERRUPTS_LOG2 4 /* ceil(log2(NUM_INTERRUPTS)) */
203#define XCHAL_NUM_EXTINTERRUPTS 9 /* num of external interrupts */
204#define XCHAL_NUM_INTLEVELS 2 /* number of interrupt levels
205 (not including level zero) */
206#define XCHAL_EXCM_LEVEL 1 /* level masked by PS.EXCM */
207 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
208
209/* Masks of interrupts at each interrupt level: */
210#define XCHAL_INTLEVEL1_MASK 0x00000FFF
211#define XCHAL_INTLEVEL2_MASK 0x00000000
212#define XCHAL_INTLEVEL3_MASK 0x00000000
213#define XCHAL_INTLEVEL4_MASK 0x00000000
214#define XCHAL_INTLEVEL5_MASK 0x00000000
215#define XCHAL_INTLEVEL6_MASK 0x00000000
216#define XCHAL_INTLEVEL7_MASK 0x00000000
217
218/* Masks of interrupts at each range 1..n of interrupt levels: */
219#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x00000FFF
220#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x00000FFF
221#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00000FFF
222#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00000FFF
223#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x00000FFF
224#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x00000FFF
225#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x00000FFF
226
227/* Level of each interrupt: */
228#define XCHAL_INT0_LEVEL 1
229#define XCHAL_INT1_LEVEL 1
230#define XCHAL_INT2_LEVEL 1
231#define XCHAL_INT3_LEVEL 1
232#define XCHAL_INT4_LEVEL 1
233#define XCHAL_INT5_LEVEL 1
234#define XCHAL_INT6_LEVEL 1
235#define XCHAL_INT7_LEVEL 1
236#define XCHAL_INT8_LEVEL 1
237#define XCHAL_INT9_LEVEL 1
238#define XCHAL_INT10_LEVEL 1
239#define XCHAL_INT11_LEVEL 1
240#define XCHAL_DEBUGLEVEL 2 /* debug interrupt level */
241#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
242
243/* Type of each interrupt: */
244#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
245#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
246#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_EDGE
247#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
248#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
249#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
250#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
251#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
252#define XCHAL_INT8_TYPE XTHAL_INTTYPE_TIMER
253#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
254#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
255#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
256
257/* Masks of interrupts for each type of interrupt: */
258#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFFF000
259#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000080
260#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000004
261#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x00000E3B
262#define XCHAL_INTTYPE_MASK_TIMER 0x00000140
263#define XCHAL_INTTYPE_MASK_NMI 0x00000000
264#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
265
266/* Interrupt numbers assigned to specific interrupt sources: */
267#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
268#define XCHAL_TIMER1_INTERRUPT 8 /* CCOMPARE1 */
269#define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED
270#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
271
272/* Interrupt numbers for levels at which only one interrupt is configured: */
273/* (There are many interrupts each at level(s) 1.) */
274
275
276/*
277 * External interrupt vectors/levels.
278 * These macros describe how Xtensa processor interrupt numbers
279 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
280 * map to external BInterrupt<n> pins, for those interrupts
281 * configured as external (level-triggered, edge-triggered, or NMI).
282 * See the Xtensa processor databook for more details.
283 */
284
285/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
286#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
287#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
288#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
289#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
290#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
291#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
292#define XCHAL_EXTINT6_NUM 9 /* (intlevel 1) */
293#define XCHAL_EXTINT7_NUM 10 /* (intlevel 1) */
294#define XCHAL_EXTINT8_NUM 11 /* (intlevel 1) */
295
296
297/*----------------------------------------------------------------------
298 EXCEPTIONS and VECTORS
299 ----------------------------------------------------------------------*/
300
301#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
302 number: 1 == XEA1 (old)
303 2 == XEA2 (new)
304 0 == XEAX (extern) */
305#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
306#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
307#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
308#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
309#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
310#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
311#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
312#define XCHAL_VECBASE_RESET_VADDR 0xD0000000 /* VECBASE reset value */
313#define XCHAL_VECBASE_RESET_PADDR 0x00000000
314#define XCHAL_RESET_VECBASE_OVERLAP 0
315
316#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000
317#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000
318#define XCHAL_RESET_VECTOR1_VADDR 0xD8000500
319#define XCHAL_RESET_VECTOR1_PADDR 0x00000500
320#define XCHAL_RESET_VECTOR_VADDR 0xFE000000
321#define XCHAL_RESET_VECTOR_PADDR 0xFE000000
322#define XCHAL_USER_VECOFS 0x00000340
323#define XCHAL_USER_VECTOR_VADDR 0xD0000340
324#define XCHAL_USER_VECTOR_PADDR 0x00000340
325#define XCHAL_KERNEL_VECOFS 0x00000300
326#define XCHAL_KERNEL_VECTOR_VADDR 0xD0000300
327#define XCHAL_KERNEL_VECTOR_PADDR 0x00000300
328#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
329#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xD00003C0
330#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000003C0
331#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
332#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
333#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
334#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
335#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
336#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
337#define XCHAL_WINDOW_VECTORS_VADDR 0xD0000000
338#define XCHAL_WINDOW_VECTORS_PADDR 0x00000000
339#define XCHAL_INTLEVEL2_VECOFS 0x00000280
340#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xD0000280
341#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000280
342#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL2_VECOFS
343#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL2_VECTOR_VADDR
344#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL2_VECTOR_PADDR
345
346
347/*----------------------------------------------------------------------
348 DEBUG
349 ----------------------------------------------------------------------*/
350
351#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
352#define XCHAL_NUM_IBREAK 0 /* number of IBREAKn regs */
353#define XCHAL_NUM_DBREAK 0 /* number of DBREAKn regs */
354#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option */
355
356
357/*----------------------------------------------------------------------
358 MMU
359 ----------------------------------------------------------------------*/
360
361/* See core-matmap.h header file for more details. */
362
363#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
364#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */
365#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
366#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
367#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
368#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
369#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
370 [autorefill] and protection)
371 usable for an MMU-based OS */
372/* If none of the above last 4 are set, it's a custom TLB configuration. */
373#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
374#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
375
376#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */
377#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */
378#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */
379
380#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
381
382
383#endif /* _XTENSA_CORE_CONFIGURATION_H */
diff --git a/arch/xtensa/variants/test_mmuhifi_c3/include/variant/tie-asm.h b/arch/xtensa/variants/test_mmuhifi_c3/include/variant/tie-asm.h
new file mode 100644
index 000000000000..6e9d69caf7e6
--- /dev/null
+++ b/arch/xtensa/variants/test_mmuhifi_c3/include/variant/tie-asm.h
@@ -0,0 +1,182 @@
1/*
2 * This header file contains assembly-language definitions (assembly
3 * macros, etc.) for this specific Xtensa processor's TIE extensions
4 * and options. It is customized to this Xtensa processor configuration.
5 *
6 * This file is subject to the terms and conditions of version 2.1 of the GNU
7 * Lesser General Public License as published by the Free Software Foundation.
8 *
9 * Copyright (C) 1999-2009 Tensilica Inc.
10 */
11
12#ifndef _XTENSA_CORE_TIE_ASM_H
13#define _XTENSA_CORE_TIE_ASM_H
14
15/* Selection parameter values for save-area save/restore macros: */
16/* Option vs. TIE: */
17#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
18#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
19/* Whether used automatically by compiler: */
20#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
21#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
22/* ABI handling across function calls: */
23#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
24#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
25#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
26/* Misc */
27#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
28
29
30
31/* Macro to save all non-coprocessor (extra) custom TIE and optional state
32 * (not including zero-overhead loop registers).
33 * Save area ptr (clobbered): ptr (8 byte aligned)
34 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
35 */
36 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
37 xchal_sa_start \continue, \ofs
38 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
39 xchal_sa_align \ptr, 0, 1024-4, 4, 4
40 rsr \at1, BR // boolean option
41 s32i \at1, \ptr, .Lxchal_ofs_ + 0
42 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
43 .endif
44 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
45 xchal_sa_align \ptr, 0, 1024-4, 4, 4
46 rsr \at1, SCOMPARE1 // conditional store option
47 s32i \at1, \ptr, .Lxchal_ofs_ + 0
48 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
49 .endif
50 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
51 xchal_sa_align \ptr, 0, 1024-4, 4, 4
52 rur \at1, THREADPTR // threadptr option
53 s32i \at1, \ptr, .Lxchal_ofs_ + 0
54 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
55 .endif
56 .endm // xchal_ncp_store
57
58/* Macro to save all non-coprocessor (extra) custom TIE and optional state
59 * (not including zero-overhead loop registers).
60 * Save area ptr (clobbered): ptr (8 byte aligned)
61 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
62 */
63 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
64 xchal_sa_start \continue, \ofs
65 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
66 xchal_sa_align \ptr, 0, 1024-4, 4, 4
67 l32i \at1, \ptr, .Lxchal_ofs_ + 0
68 wsr \at1, BR // boolean option
69 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
70 .endif
71 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
72 xchal_sa_align \ptr, 0, 1024-4, 4, 4
73 l32i \at1, \ptr, .Lxchal_ofs_ + 0
74 wsr \at1, SCOMPARE1 // conditional store option
75 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
76 .endif
77 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
78 xchal_sa_align \ptr, 0, 1024-4, 4, 4
79 l32i \at1, \ptr, .Lxchal_ofs_ + 0
80 wur \at1, THREADPTR // threadptr option
81 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
82 .endif
83 .endm // xchal_ncp_load
84
85
86
87#define XCHAL_NCP_NUM_ATMPS 1
88
89
90
91/* Macro to save the state of TIE coprocessor AudioEngineLX.
92 * Save area ptr (clobbered): ptr (8 byte aligned)
93 * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP1_NUM_ATMPS needed)
94 */
95#define xchal_cp_AudioEngineLX_store xchal_cp1_store
96/* #define xchal_cp_AudioEngineLX_store_a2 xchal_cp1_store a2 a3 a4 a5 a6 */
97 .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
98 xchal_sa_start \continue, \ofs
99 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
100 xchal_sa_align \ptr, 0, 0, 1, 8
101 rur240 \at1 // AE_OVF_SAR
102 s32i \at1, \ptr, 0
103 rur241 \at1 // AE_BITHEAD
104 s32i \at1, \ptr, 4
105 rur242 \at1 // AE_TS_FTS_BU_BP
106 s32i \at1, \ptr, 8
107 rur243 \at1 // AE_SD_NO
108 s32i \at1, \ptr, 12
109 AE_SP24X2S.I aep0, \ptr, 16
110 AE_SP24X2S.I aep1, \ptr, 24
111 AE_SP24X2S.I aep2, \ptr, 32
112 AE_SP24X2S.I aep3, \ptr, 40
113 AE_SP24X2S.I aep4, \ptr, 48
114 AE_SP24X2S.I aep5, \ptr, 56
115 addi \ptr, \ptr, 64
116 AE_SP24X2S.I aep6, \ptr, 0
117 AE_SP24X2S.I aep7, \ptr, 8
118 AE_SQ56S.I aeq0, \ptr, 16
119 AE_SQ56S.I aeq1, \ptr, 24
120 AE_SQ56S.I aeq2, \ptr, 32
121 AE_SQ56S.I aeq3, \ptr, 40
122 .set .Lxchal_pofs_, .Lxchal_pofs_ + 64
123 .set .Lxchal_ofs_, .Lxchal_ofs_ + 112
124 .endif
125 .endm // xchal_cp1_store
126
127/* Macro to restore the state of TIE coprocessor AudioEngineLX.
128 * Save area ptr (clobbered): ptr (8 byte aligned)
129 * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP1_NUM_ATMPS needed)
130 */
131#define xchal_cp_AudioEngineLX_load xchal_cp1_load
132/* #define xchal_cp_AudioEngineLX_load_a2 xchal_cp1_load a2 a3 a4 a5 a6 */
133 .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
134 xchal_sa_start \continue, \ofs
135 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
136 xchal_sa_align \ptr, 0, 0, 1, 8
137 l32i \at1, \ptr, 0
138 wur240 \at1 // AE_OVF_SAR
139 l32i \at1, \ptr, 4
140 wur241 \at1 // AE_BITHEAD
141 l32i \at1, \ptr, 8
142 wur242 \at1 // AE_TS_FTS_BU_BP
143 l32i \at1, \ptr, 12
144 wur243 \at1 // AE_SD_NO
145 addi \ptr, \ptr, 80
146 AE_LQ56.I aeq0, \ptr, 0
147 AE_LQ56.I aeq1, \ptr, 8
148 AE_LQ56.I aeq2, \ptr, 16
149 AE_LQ56.I aeq3, \ptr, 24
150 AE_LP24X2.I aep0, \ptr, -64
151 AE_LP24X2.I aep1, \ptr, -56
152 AE_LP24X2.I aep2, \ptr, -48
153 AE_LP24X2.I aep3, \ptr, -40
154 AE_LP24X2.I aep4, \ptr, -32
155 AE_LP24X2.I aep5, \ptr, -24
156 AE_LP24X2.I aep6, \ptr, -16
157 AE_LP24X2.I aep7, \ptr, -8
158 .set .Lxchal_pofs_, .Lxchal_pofs_ + 80
159 .set .Lxchal_ofs_, .Lxchal_ofs_ + 112
160 .endif
161 .endm // xchal_cp1_load
162
163#define XCHAL_CP1_NUM_ATMPS 1
164#define XCHAL_SA_NUM_ATMPS 1
165
166 /* Empty macros for unconfigured coprocessors: */
167 .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
168 .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
169 .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
170 .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
171 .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
172 .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
173 .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
174 .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
175 .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
176 .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
177 .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
178 .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
179 .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
180 .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
181
182#endif /*_XTENSA_CORE_TIE_ASM_H*/
diff --git a/arch/xtensa/variants/test_mmuhifi_c3/include/variant/tie.h b/arch/xtensa/variants/test_mmuhifi_c3/include/variant/tie.h
new file mode 100644
index 000000000000..fb1f5f004c92
--- /dev/null
+++ b/arch/xtensa/variants/test_mmuhifi_c3/include/variant/tie.h
@@ -0,0 +1,140 @@
1/*
2 * This header file describes this specific Xtensa processor's TIE extensions
3 * that extend basic Xtensa core functionality. It is customized to this
4 * Xtensa processor configuration.
5 *
6 * This file is subject to the terms and conditions of version 2.1 of the GNU
7 * Lesser General Public License as published by the Free Software Foundation.
8 *
9 * Copyright (C) 1999-2009 Tensilica Inc.
10 */
11
12#ifndef _XTENSA_CORE_TIE_H
13#define _XTENSA_CORE_TIE_H
14
15#define XCHAL_CP_NUM 1 /* number of coprocessors */
16#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
17#define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */
18#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
19
20/* Basic parameters of each coprocessor: */
21#define XCHAL_CP1_NAME "AudioEngineLX"
22#define XCHAL_CP1_IDENT AudioEngineLX
23#define XCHAL_CP1_SA_SIZE 112 /* size of state save area */
24#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
25#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
26
27/* Filler info for unassigned coprocessors, to simplify arrays etc: */
28#define XCHAL_CP0_SA_SIZE 0
29#define XCHAL_CP0_SA_ALIGN 1
30#define XCHAL_CP2_SA_SIZE 0
31#define XCHAL_CP2_SA_ALIGN 1
32#define XCHAL_CP3_SA_SIZE 0
33#define XCHAL_CP3_SA_ALIGN 1
34#define XCHAL_CP4_SA_SIZE 0
35#define XCHAL_CP4_SA_ALIGN 1
36#define XCHAL_CP5_SA_SIZE 0
37#define XCHAL_CP5_SA_ALIGN 1
38#define XCHAL_CP6_SA_SIZE 0
39#define XCHAL_CP6_SA_ALIGN 1
40#define XCHAL_CP7_SA_SIZE 0
41#define XCHAL_CP7_SA_ALIGN 1
42
43/* Save area for non-coprocessor optional and custom (TIE) state: */
44#define XCHAL_NCP_SA_SIZE 12
45#define XCHAL_NCP_SA_ALIGN 4
46
47/* Total save area for optional and custom state (NCP + CPn): */
48#define XCHAL_TOTAL_SA_SIZE 128 /* with 16-byte align padding */
49#define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */
50
51/*
52 * Detailed contents of save areas.
53 * NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
54 * before expanding the XCHAL_xxx_SA_LIST() macros.
55 *
56 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
57 * dbnum,base,regnum,bitsz,gapsz,reset,x...)
58 *
59 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
60 * ccused = set if used by compiler without special options or code
61 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
62 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
63 * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
64 * name = lowercase reg name (no quotes)
65 * galign = group byte alignment (power of 2) (galign >= align)
66 * align = register byte alignment (power of 2)
67 * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
68 * (not including any pad bytes required to galign this or next reg)
69 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
70 * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
71 * regnum = reg index in regfile, or special/TIE-user reg number
72 * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
73 * gapsz = intervening bits, if bitsz bits not stored contiguously
74 * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
75 * reset = register reset value (or 0 if undefined at reset)
76 * x = reserved for future use (0 until then)
77 *
78 * To filter out certain registers, e.g. to expand only the non-global
79 * registers used by the compiler, you can do something like this:
80 *
81 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
82 * #define SELCC0(p...)
83 * #define SELCC1(abikind,p...) SELAK##abikind(p)
84 * #define SELAK0(p...) REG(p)
85 * #define SELAK1(p...) REG(p)
86 * #define SELAK2(p...)
87 * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
88 * ...what you want to expand...
89 */
90
91#define XCHAL_NCP_SA_NUM 3
92#define XCHAL_NCP_SA_LIST(s) \
93 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
94 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
95 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0)
96
97#define XCHAL_CP0_SA_NUM 0
98#define XCHAL_CP0_SA_LIST(s) /* empty */
99
100#define XCHAL_CP1_SA_NUM 16
101#define XCHAL_CP1_SA_LIST(s) \
102 XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 7,0,0,0) \
103 XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \
104 XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \
105 XCHAL_SA_REG(s,0,0,1,0, ae_sd_no, 4, 4, 4,0x03F3, ur,243, 28,0,0,0) \
106 XCHAL_SA_REG(s,0,0,2,0, aep0, 8, 8, 8,0x0060, aep,0 , 48,0,0,0) \
107 XCHAL_SA_REG(s,0,0,2,0, aep1, 8, 8, 8,0x0061, aep,1 , 48,0,0,0) \
108 XCHAL_SA_REG(s,0,0,2,0, aep2, 8, 8, 8,0x0062, aep,2 , 48,0,0,0) \
109 XCHAL_SA_REG(s,0,0,2,0, aep3, 8, 8, 8,0x0063, aep,3 , 48,0,0,0) \
110 XCHAL_SA_REG(s,0,0,2,0, aep4, 8, 8, 8,0x0064, aep,4 , 48,0,0,0) \
111 XCHAL_SA_REG(s,0,0,2,0, aep5, 8, 8, 8,0x0065, aep,5 , 48,0,0,0) \
112 XCHAL_SA_REG(s,0,0,2,0, aep6, 8, 8, 8,0x0066, aep,6 , 48,0,0,0) \
113 XCHAL_SA_REG(s,0,0,2,0, aep7, 8, 8, 8,0x0067, aep,7 , 48,0,0,0) \
114 XCHAL_SA_REG(s,0,0,2,0, aeq0, 8, 8, 8,0x0068, aeq,0 , 56,0,0,0) \
115 XCHAL_SA_REG(s,0,0,2,0, aeq1, 8, 8, 8,0x0069, aeq,1 , 56,0,0,0) \
116 XCHAL_SA_REG(s,0,0,2,0, aeq2, 8, 8, 8,0x006A, aeq,2 , 56,0,0,0) \
117 XCHAL_SA_REG(s,0,0,2,0, aeq3, 8, 8, 8,0x006B, aeq,3 , 56,0,0,0)
118
119#define XCHAL_CP2_SA_NUM 0
120#define XCHAL_CP2_SA_LIST(s) /* empty */
121
122#define XCHAL_CP3_SA_NUM 0
123#define XCHAL_CP3_SA_LIST(s) /* empty */
124
125#define XCHAL_CP4_SA_NUM 0
126#define XCHAL_CP4_SA_LIST(s) /* empty */
127
128#define XCHAL_CP5_SA_NUM 0
129#define XCHAL_CP5_SA_LIST(s) /* empty */
130
131#define XCHAL_CP6_SA_NUM 0
132#define XCHAL_CP6_SA_LIST(s) /* empty */
133
134#define XCHAL_CP7_SA_NUM 0
135#define XCHAL_CP7_SA_LIST(s) /* empty */
136
137/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
138#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8
139
140#endif /*_XTENSA_CORE_TIE_H*/
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-02 20:33:44 -0500