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-rw-r--r--Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt98
-rw-r--r--Documentation/devicetree/bindings/pinctrl/cirrus,lochnagar.txt141
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt6
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt1
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt132
-rw-r--r--Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt2
-rw-r--r--MAINTAINERS2
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7786.h2
-rw-r--r--drivers/gpio/gpiolib-devprop.c2
-rw-r--r--drivers/gpio/gpiolib.h3
-rw-r--r--drivers/pinctrl/Kconfig8
-rw-r--r--drivers/pinctrl/Makefile1
-rw-r--r--drivers/pinctrl/cirrus/Kconfig10
-rw-r--r--drivers/pinctrl/cirrus/Makefile2
-rw-r--r--drivers/pinctrl/cirrus/pinctrl-lochnagar.c1235
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx.c25
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx.h1
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx8mq.c1
-rw-r--r--drivers/pinctrl/freescale/pinctrl-scu.c2
-rw-r--r--drivers/pinctrl/intel/pinctrl-baytrail.c2
-rw-r--r--drivers/pinctrl/intel/pinctrl-cedarfork.c18
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.c66
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.h11
-rw-r--r--drivers/pinctrl/mediatek/Kconfig7
-rw-r--r--drivers/pinctrl/mediatek/Makefile1
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mt8183.c50
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mt8516.c362
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c49
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h11
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h1182
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-paris.c21
-rw-r--r--drivers/pinctrl/pinctrl-amd.c4
-rw-r--r--drivers/pinctrl/pinctrl-artpec6.c19
-rw-r--r--drivers/pinctrl/pinctrl-axp209.c2
-rw-r--r--drivers/pinctrl/pinctrl-bm1880.c965
-rw-r--r--drivers/pinctrl/pinctrl-mcp23s08.c3
-rw-r--r--drivers/pinctrl/pinctrl-pistachio.c2
-rw-r--r--drivers/pinctrl/pinctrl-rza1.c18
-rw-r--r--drivers/pinctrl/pinctrl-st.c15
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos-arm.c1
-rw-r--r--drivers/pinctrl/sh-pfc/Kconfig204
-rw-r--r--drivers/pinctrl/sh-pfc/Makefile15
-rw-r--r--drivers/pinctrl/sh-pfc/core.c130
-rw-r--r--drivers/pinctrl/sh-pfc/gpio.c8
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-emev2.c67
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a73a4.c64
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7740.c56
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a77470.c136
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7778.c101
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7779.c235
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7790.c132
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7791.c156
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7792.c134
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7794.c127
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c222
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7795.c201
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7796.c225
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a77965.c294
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a77970.c123
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a77980.c135
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a77990.c214
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a77995.c120
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7203.c152
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7264.c232
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7269.c252
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh73a0.c52
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7720.c144
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7722.c220
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7723.c200
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7724.c204
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7734.c140
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7757.c244
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7785.c136
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7786.c80
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-shx3.c32
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h68
-rw-r--r--drivers/pinctrl/stm32/pinctrl-stm32.c105
-rw-r--r--drivers/pinctrl/stm32/pinctrl-stm32.h14
-rw-r--r--drivers/pinctrl/stm32/pinctrl-stm32mp157.c1089
-rw-r--r--drivers/pinctrl/sunxi/Kconfig57
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c2
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c2
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.c96
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.h18
-rw-r--r--drivers/pinctrl/zte/pinctrl-zx.c1
-rw-r--r--include/dt-bindings/pinctrl/stm32-pinfunc.h6
-rw-r--r--include/linux/gpio/driver.h3
88 files changed, 8120 insertions, 3012 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt
new file mode 100644
index 000000000000..ed34bb1ee81c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt
@@ -0,0 +1,98 @@
1Bitmain BM1880 Pin Controller
2
3This binding describes the pin controller found in the BM1880 SoC.
4
5Required Properties:
6
7- compatible: Should be "bitmain,bm1880-pinctrl"
8- reg: Offset and length of pinctrl space in SCTRL.
9
10Please refer to pinctrl-bindings.txt in this directory for details of the
11common pinctrl bindings used by client devices, including the meaning of the
12phrase "pin configuration node".
13
14The pin configuration nodes act as a container for an arbitrary number of
15subnodes. Each of these subnodes represents some desired configuration for a
16pin, a group, or a list of pins or groups. This configuration for BM1880 SoC
17includes only pinmux as there is no pinconf support available in SoC.
18
19Each configuration node can consist of multiple nodes describing the pinmux
20options. The name of each subnode is not important; all subnodes should be
21enumerated and processed purely based on their content.
22
23The following generic properties as defined in pinctrl-bindings.txt are valid
24to specify in a pinmux subnode:
25
26Required Properties:
27
28- pins: An array of strings, each string containing the name of a pin.
29 Valid values for pins are:
30
31 MIO0 - MIO111
32
33- groups: An array of strings, each string containing the name of a pin
34 group. Valid values for groups are:
35
36 nand_grp, spi_grp, emmc_grp, sdio_grp, eth0_grp, pwm0_grp,
37 pwm1_grp, pwm2_grp, pwm3_grp, pwm4_grp, pwm5_grp, pwm6_grp,
38 pwm7_grp, pwm8_grp, pwm9_grp, pwm10_grp, pwm11_grp, pwm12_grp,
39 pwm13_grp, pwm14_grp, pwm15_grp, pwm16_grp, pwm17_grp,
40 pwm18_grp, pwm19_grp, pwm20_grp, pwm21_grp, pwm22_grp,
41 pwm23_grp, pwm24_grp, pwm25_grp, pwm26_grp, pwm27_grp,
42 pwm28_grp, pwm29_grp, pwm30_grp, pwm31_grp, pwm32_grp,
43 pwm33_grp, pwm34_grp, pwm35_grp, pwm36_grp, i2c0_grp,
44 i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, uart0_grp, uart1_grp,
45 uart2_grp, uart3_grp, uart4_grp, uart5_grp, uart6_grp,
46 uart7_grp, uart8_grp, uart9_grp, uart10_grp, uart11_grp,
47 uart12_grp, uart13_grp, uart14_grp, uart15_grp, gpio0_grp,
48 gpio1_grp, gpio2_grp, gpio3_grp, gpio4_grp, gpio5_grp,
49 gpio6_grp, gpio7_grp, gpio8_grp, gpio9_grp, gpio10_grp,
50 gpio11_grp, gpio12_grp, gpio13_grp, gpio14_grp, gpio15_grp,
51 gpio16_grp, gpio17_grp, gpio18_grp, gpio19_grp, gpio20_grp,
52 gpio21_grp, gpio22_grp, gpio23_grp, gpio24_grp, gpio25_grp,
53 gpio26_grp, gpio27_grp, gpio28_grp, gpio29_grp, gpio30_grp,
54 gpio31_grp, gpio32_grp, gpio33_grp, gpio34_grp, gpio35_grp,
55 gpio36_grp, gpio37_grp, gpio38_grp, gpio39_grp, gpio40_grp,
56 gpio41_grp, gpio42_grp, gpio43_grp, gpio44_grp, gpio45_grp,
57 gpio46_grp, gpio47_grp, gpio48_grp, gpio49_grp, gpio50_grp,
58 gpio51_grp, gpio52_grp, gpio53_grp, gpio54_grp, gpio55_grp,
59 gpio56_grp, gpio57_grp, gpio58_grp, gpio59_grp, gpio60_grp,
60 gpio61_grp, gpio62_grp, gpio63_grp, gpio64_grp, gpio65_grp,
61 gpio66_grp, gpio67_grp, eth1_grp, i2s0_grp, i2s0_mclkin_grp,
62 i2s1_grp, i2s1_mclkin_grp, spi0_grp
63
64- function: An array of strings, each string containing the name of the
65 pinmux functions. The following are the list of pinmux
66 functions available:
67
68 nand, spi, emmc, sdio, eth0, pwm0, pwm1, pwm2, pwm3, pwm4,
69 pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, pwm12, pwm13,
70 pwm14, pwm15, pwm16, pwm17, pwm18, pwm19, pwm20, pwm21, pwm22,
71 pwm23, pwm24, pwm25, pwm26, pwm27, pwm28, pwm29, pwm30, pwm31,
72 pwm32, pwm33, pwm34, pwm35, pwm36, i2c0, i2c1, i2c2, i2c3,
73 i2c4, uart0, uart1, uart2, uart3, uart4, uart5, uart6, uart7,
74 uart8, uart9, uart10, uart11, uart12, uart13, uart14, uart15,
75 gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8,
76 gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, gpio16,
77 gpio17, gpio18, gpio19, gpio20, gpio21, gpio22, gpio23,
78 gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30,
79 gpio31, gpio32, gpio33, gpio34, gpio35, gpio36, gpio37,
80 gpio38, gpio39, gpio40, gpio41, gpio42, gpio43, gpio44,
81 gpio45, gpio46, gpio47, gpio48, gpio49, gpio50, gpio51,
82 gpio52, gpio53, gpio54, gpio55, gpio56, gpio57, gpio58,
83 gpio59, gpio60, gpio61, gpio62, gpio63, gpio64, gpio65,
84 gpio66, gpio67, eth1, i2s0, i2s0_mclkin, i2s1, i2s1_mclkin,
85 spi0
86
87Example:
88 pinctrl: pinctrl@50 {
89 compatible = "bitmain,bm1880-pinctrl";
90 reg = <0x50 0x4B0>;
91
92 pinctrl_uart0_default: uart0-default {
93 pinmux {
94 groups = "uart0_grp";
95 function = "uart0";
96 };
97 };
98 };
diff --git a/Documentation/devicetree/bindings/pinctrl/cirrus,lochnagar.txt b/Documentation/devicetree/bindings/pinctrl/cirrus,lochnagar.txt
new file mode 100644
index 000000000000..a87447180e83
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/cirrus,lochnagar.txt
@@ -0,0 +1,141 @@
1Cirrus Logic Lochnagar Audio Development Board
2
3Lochnagar is an evaluation and development board for Cirrus Logic
4Smart CODEC and Amp devices. It allows the connection of most Cirrus
5Logic devices on mini-cards, as well as allowing connection of
6various application processor systems to provide a full evaluation
7platform. Audio system topology, clocking and power can all be
8controlled through the Lochnagar, allowing the device under test
9to be used in a variety of possible use cases.
10
11This binding document describes the binding for the pinctrl portion
12of the driver.
13
14Also see these documents for generic binding information:
15 [1] GPIO : ../gpio/gpio.txt
16 [2] Pinctrl: ../pinctrl/pinctrl-bindings.txt
17
18And these for relevant defines:
19 [3] include/dt-bindings/pinctrl/lochnagar.h
20
21This binding must be part of the Lochnagar MFD binding:
22 [4] ../mfd/cirrus,lochnagar.txt
23
24Required properties:
25
26 - compatible : One of the following strings:
27 "cirrus,lochnagar-pinctrl"
28
29 - gpio-controller : Indicates this device is a GPIO controller.
30 - #gpio-cells : Must be 2. The first cell is the pin number, see
31 [3] for available pins and the second cell is used to specify
32 optional parameters, see [1].
33 - gpio-ranges : Range of pins managed by the GPIO controller, see
34 [1]. Both the GPIO and Pinctrl base should be set to zero and the
35 count to the appropriate of the LOCHNAGARx_PIN_NUM_GPIOS define,
36 see [3].
37
38 - pinctrl-names : A pinctrl state named "default" must be defined.
39 - pinctrl-0 : A phandle to the default pinctrl state.
40
41Required sub-nodes:
42
43The pin configurations are defined as a child of the pinctrl states
44node, see [2]. Each sub-node can have the following properties:
45 - groups : A list of groups to select (either this or "pins" must be
46 specified), available groups:
47 codec-aif1, codec-aif2, codec-aif3, dsp-aif1, dsp-aif2, psia1,
48 psia2, gf-aif1, gf-aif2, gf-aif3, gf-aif4, spdif-aif, usb-aif1,
49 usb-aif2, adat-aif, soundcard-aif
50 - pins : A list of pin names to select (either this or "groups" must
51 be specified), available pins:
52 fpga-gpio1, fpga-gpio2, fpga-gpio3, fpga-gpio4, fpga-gpio5,
53 fpga-gpio6, codec-gpio1, codec-gpio2, codec-gpio3, codec-gpio4,
54 codec-gpio5, codec-gpio6, codec-gpio7, codec-gpio8, dsp-gpio1,
55 dsp-gpio2, dsp-gpio3, dsp-gpio4, dsp-gpio5, dsp-gpio6, gf-gpio2,
56 gf-gpio3, gf-gpio7, codec-aif1-bclk, codec-aif1-rxdat,
57 codec-aif1-lrclk, codec-aif1-txdat, codec-aif2-bclk,
58 codec-aif2-rxdat, codec-aif2-lrclk, codec-aif2-txdat,
59 codec-aif3-bclk, codec-aif3-rxdat, codec-aif3-lrclk,
60 codec-aif3-txdat, dsp-aif1-bclk, dsp-aif1-rxdat, dsp-aif1-lrclk,
61 dsp-aif1-txdat, dsp-aif2-bclk, dsp-aif2-rxdat,
62 dsp-aif2-lrclk, dsp-aif2-txdat, psia1-bclk, psia1-rxdat,
63 psia1-lrclk, psia1-txdat, psia2-bclk, psia2-rxdat, psia2-lrclk,
64 psia2-txdat, gf-aif3-bclk, gf-aif3-rxdat, gf-aif3-lrclk,
65 gf-aif3-txdat, gf-aif4-bclk, gf-aif4-rxdat, gf-aif4-lrclk,
66 gf-aif4-txdat, gf-aif1-bclk, gf-aif1-rxdat, gf-aif1-lrclk,
67 gf-aif1-txdat, gf-aif2-bclk, gf-aif2-rxdat, gf-aif2-lrclk,
68 gf-aif2-txdat, dsp-uart1-rx, dsp-uart1-tx, dsp-uart2-rx,
69 dsp-uart2-tx, gf-uart2-rx, gf-uart2-tx, usb-uart-rx,
70 codec-pdmclk1, codec-pdmdat1, codec-pdmclk2, codec-pdmdat2,
71 codec-dmicclk1, codec-dmicdat1, codec-dmicclk2, codec-dmicdat2,
72 codec-dmicclk3, codec-dmicdat3, codec-dmicclk4, codec-dmicdat4,
73 dsp-dmicclk1, dsp-dmicdat1, dsp-dmicclk2, dsp-dmicdat2, i2c2-scl,
74 i2c2-sda, i2c3-scl, i2c3-sda, i2c4-scl, i2c4-sda, dsp-standby,
75 codec-mclk1, codec-mclk2, dsp-clkin, psia1-mclk, psia2-mclk,
76 gf-gpio1, gf-gpio5, dsp-gpio20, led1, led2
77 - function : The mux function to select, available functions:
78 aif, fpga-gpio1, fpga-gpio2, fpga-gpio3, fpga-gpio4, fpga-gpio5,
79 fpga-gpio6, codec-gpio1, codec-gpio2, codec-gpio3, codec-gpio4,
80 codec-gpio5, codec-gpio6, codec-gpio7, codec-gpio8, dsp-gpio1,
81 dsp-gpio2, dsp-gpio3, dsp-gpio4, dsp-gpio5, dsp-gpio6, gf-gpio2,
82 gf-gpio3, gf-gpio7, gf-gpio1, gf-gpio5, dsp-gpio20, codec-clkout,
83 dsp-clkout, pmic-32k, spdif-clkout, clk-12m288, clk-11m2986,
84 clk-24m576, clk-22m5792, xmos-mclk, gf-clkout1, gf-mclk1,
85 gf-mclk3, gf-mclk2, gf-clkout2, codec-mclk1, codec-mclk2,
86 dsp-clkin, psia1-mclk, psia2-mclk, spdif-mclk, codec-irq,
87 codec-reset, dsp-reset, dsp-irq, dsp-standby, codec-pdmclk1,
88 codec-pdmdat1, codec-pdmclk2, codec-pdmdat2, codec-dmicclk1,
89 codec-dmicdat1, codec-dmicclk2, codec-dmicdat2, codec-dmicclk3,
90 codec-dmicdat3, codec-dmicclk4, codec-dmicdat4, dsp-dmicclk1,
91 dsp-dmicdat1, dsp-dmicclk2, dsp-dmicdat2, dsp-uart1-rx,
92 dsp-uart1-tx, dsp-uart2-rx, dsp-uart2-tx, gf-uart2-rx,
93 gf-uart2-tx, usb-uart-rx, usb-uart-tx, i2c2-scl, i2c2-sda,
94 i2c3-scl, i2c3-sda, i2c4-scl, i2c4-sda, spdif-aif, psia1,
95 psia1-bclk, psia1-lrclk, psia1-rxdat, psia1-txdat, psia2,
96 psia2-bclk, psia2-lrclk, psia2-rxdat, psia2-txdat, codec-aif1,
97 codec-aif1-bclk, codec-aif1-lrclk, codec-aif1-rxdat,
98 codec-aif1-txdat, codec-aif2, codec-aif2-bclk, codec-aif2-lrclk,
99 codec-aif2-rxdat, codec-aif2-txdat, codec-aif3, codec-aif3-bclk,
100 codec-aif3-lrclk, codec-aif3-rxdat, codec-aif3-txdat, dsp-aif1,
101 dsp-aif1-bclk, dsp-aif1-lrclk, dsp-aif1-rxdat, dsp-aif1-txdat,
102 dsp-aif2, dsp-aif2-bclk, dsp-aif2-lrclk, dsp-aif2-rxdat,
103 dsp-aif2-txdat, gf-aif3, gf-aif3-bclk, gf-aif3-lrclk,
104 gf-aif3-rxdat, gf-aif3-txdat, gf-aif4, gf-aif4-bclk,
105 gf-aif4-lrclk, gf-aif4-rxdat, gf-aif4-txdat, gf-aif1,
106 gf-aif1-bclk, gf-aif1-lrclk, gf-aif1-rxdat, gf-aif1-txdat,
107 gf-aif2, gf-aif2-bclk, gf-aif2-lrclk, gf-aif2-rxdat,
108 gf-aif2-txdat, usb-aif1, usb-aif2, adat-aif, soundcard-aif,
109
110 - output-enable : Specifies that an AIF group will be used as a master
111 interface (either this or input-enable is required if a group is
112 being muxed to an AIF)
113 - input-enable : Specifies that an AIF group will be used as a slave
114 interface (either this or output-enable is required if a group is
115 being muxed to an AIF)
116
117Example:
118
119lochnagar-pinctrl {
120 compatible = "cirrus,lochnagar-pinctrl";
121
122 gpio-controller;
123 #gpio-cells = <2>;
124 gpio-ranges = <&lochnagar 0 0 LOCHNAGAR2_PIN_NUM_GPIOS>;
125
126 pinctrl-names = "default";
127 pinctrl-0 = <&pin-settings>;
128
129 pin-settings: pin-settings {
130 ap-aif {
131 input-enable;
132 groups = "gf-aif1";
133 function = "codec-aif3";
134 };
135 codec-aif {
136 output-enable;
137 groups = "codec-aif3";
138 function = "gf-aif1";
139 };
140 };
141};
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
index 6666277c3acb..8ac1d0851a0f 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
@@ -48,9 +48,9 @@ PAD_CTL_HYS (1 << 3)
48PAD_CTL_SRE_SLOW (1 << 2) 48PAD_CTL_SRE_SLOW (1 << 2)
49PAD_CTL_SRE_FAST (0 << 2) 49PAD_CTL_SRE_FAST (0 << 2)
50PAD_CTL_DSE_X1 (0 << 0) 50PAD_CTL_DSE_X1 (0 << 0)
51PAD_CTL_DSE_X2 (1 << 0) 51PAD_CTL_DSE_X4 (1 << 0)
52PAD_CTL_DSE_X3 (2 << 0) 52PAD_CTL_DSE_X2 (2 << 0)
53PAD_CTL_DSE_X4 (3 << 0) 53PAD_CTL_DSE_X6 (3 << 0)
54 54
55Examples: 55Examples:
56While iomuxc-lpsr is intended to be used by dedicated peripherals to take 56While iomuxc-lpsr is intended to be used by dedicated peripherals to take
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
index e7d6f81c227f..205be98ae078 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
@@ -11,6 +11,7 @@ Required properties:
11 "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl. 11 "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
12 "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl. 12 "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
13 "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl. 13 "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
14 "mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl.
14- pins-are-numbered: Specify the subnodes are using numbered pinmux to 15- pins-are-numbered: Specify the subnodes are using numbered pinmux to
15 specify pins. 16 specify pins.
16- gpio-controller : Marks the device node as a gpio controller. 17- gpio-controller : Marks the device node as a gpio controller.
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt
new file mode 100644
index 000000000000..eccbe3f55d3f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt
@@ -0,0 +1,132 @@
1* Mediatek MT8183 Pin Controller
2
3The Mediatek's Pin controller is used to control SoC pins.
4
5Required properties:
6- compatible: value should be one of the following.
7 "mediatek,mt8183-pinctrl", compatible with mt8183 pinctrl.
8- gpio-controller : Marks the device node as a gpio controller.
9- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
10 binding is used, the amount of cells must be specified as 2. See the below
11 mentioned gpio binding representation for description of particular cells.
12- gpio-ranges : gpio valid number range.
13- reg: physical address base for gpio base registers. There are 10 GPIO
14 physical address base in mt8183.
15
16Optional properties:
17- reg-names: gpio base register names. There are 10 gpio base register
18 names in mt8183. They are "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4",
19 "iocfg5", "iocfg6", "iocfg7", "iocfg8", "eint".
20- interrupt-controller: Marks the device node as an interrupt controller
21- #interrupt-cells: Should be two.
22- interrupts : The interrupt outputs to sysirq.
23
24Please refer to pinctrl-bindings.txt in this directory for details of the
25common pinctrl bindings used by client devices.
26
27Subnode format
28A pinctrl node should contain at least one subnodes representing the
29pinctrl groups available on the machine. Each subnode will list the
30pins it needs, and how they should be configured, with regard to muxer
31configuration, pullups, drive strength, input enable/disable and input schmitt.
32
33 node {
34 pinmux = <PIN_NUMBER_PINMUX>;
35 GENERIC_PINCONFIG;
36 };
37
38Required properties:
39- pinmux: integer array, represents gpio pin number and mux setting.
40 Supported pin number and mux varies for different SoCs, and are defined
41 as macros in boot/dts/<soc>-pinfunc.h directly.
42
43Optional properties:
44- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
45 bias-pull-down, bias-pull-up, input-enable, input-disable, output-low,
46 output-high, input-schmitt-enable, input-schmitt-disable
47 and drive-strength are valid.
48
49 Some special pins have extra pull up strength, there are R0 and R1 pull-up
50 resistors available, but for user, it's only need to set R1R0 as 00, 01,
51 10 or 11. So It needs config "mediatek,pull-up-adv" or
52 "mediatek,pull-down-adv" to support arguments for those special pins.
53 Valid arguments are from 0 to 3.
54
55 mediatek,tdsel: An integer describing the steps for output level shifter
56 duty cycle when asserted (high pulse width adjustment). Valid arguments
57 are from 0 to 15.
58 mediatek,rdsel: An integer describing the steps for input level shifter
59 duty cycle when asserted (high pulse width adjustment). Valid arguments
60 are from 0 to 63.
61
62 When config drive-strength, it can support some arguments, such as
63 MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h.
64 It can only support 2/4/6/8/10/12/14/16mA in mt8183.
65 For I2C pins, there are existing generic driving setup and the specific
66 driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA driving
67 adjustment in generic driving setup. But in specific driving setup,
68 they can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
69 driving setup for I2C pins, the existing generic driving setup will be
70 disabled. For some special features, we need the I2C pins specific
71 driving setup. The specific driving setup is controlled by E1E0EN.
72 So we need add extra vendor driving preperty instead of
73 the generic driving property.
74 We can add "mediatek,drive-strength-adv = <XXX>;" to describe the specific
75 driving setup property. "XXX" means the value of E1E0EN. EN is 0 or 1.
76 It is used to enable or disable the specific driving setup.
77 E1E0 is used to describe the detail strength specification of the I2C pin.
78 When E1=0/E0=0, the strength is 0.125mA.
79 When E1=0/E0=1, the strength is 0.25mA.
80 When E1=1/E0=0, the strength is 0.5mA.
81 When E1=1/E0=1, the strength is 1mA.
82 So the valid arguments of "mediatek,drive-strength-adv" are from 0 to 7.
83
84Examples:
85
86#include "mt8183-pinfunc.h"
87
88...
89{
90 pio: pinctrl@10005000 {
91 compatible = "mediatek,mt8183-pinctrl";
92 reg = <0 0x10005000 0 0x1000>,
93 <0 0x11f20000 0 0x1000>,
94 <0 0x11e80000 0 0x1000>,
95 <0 0x11e70000 0 0x1000>,
96 <0 0x11e90000 0 0x1000>,
97 <0 0x11d30000 0 0x1000>,
98 <0 0x11d20000 0 0x1000>,
99 <0 0x11c50000 0 0x1000>,
100 <0 0x11f30000 0 0x1000>,
101 <0 0x1000b000 0 0x1000>;
102 reg-names = "iocfg0", "iocfg1", "iocfg2",
103 "iocfg3", "iocfg4", "iocfg5",
104 "iocfg6", "iocfg7", "iocfg8",
105 "eint";
106 gpio-controller;
107 #gpio-cells = <2>;
108 gpio-ranges = <&pio 0 0 192>;
109 interrupt-controller;
110 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
111 #interrupt-cells = <2>;
112
113 i2c0_pins_a: i2c0 {
114 pins1 {
115 pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
116 <PINMUX_GPIO49__FUNC_SDA5>;
117 mediatek,pull-up-adv = <3>;
118 mediatek,drive-strength-adv = <7>;
119 };
120 };
121
122 i2c1_pins_a: i2c1 {
123 pins {
124 pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
125 <PINMUX_GPIO51__FUNC_SDA3>;
126 mediatek,pull-down-adv = <2>;
127 mediatek,drive-strength-adv = <4>;
128 };
129 };
130 ...
131 };
132};
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
index 48df30a36b01..00169255e48c 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -57,6 +57,8 @@ Optional properties:
57 - st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line 57 - st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line
58 used to select GPIOs as interrupts). 58 used to select GPIOs as interrupts).
59 - hwlocks: reference to a phandle of a hardware spinlock provider node. 59 - hwlocks: reference to a phandle of a hardware spinlock provider node.
60 - st,package: Indicates the SOC package used.
61 More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
60 62
61Example 1: 63Example 1:
62#include <dt-bindings/pinctrl/stm32f429-pinfunc.h> 64#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
diff --git a/MAINTAINERS b/MAINTAINERS
index ee134110a502..d58d215a7c9b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1418,7 +1418,9 @@ M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
1418L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1418L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1419S: Maintained 1419S: Maintained
1420F: arch/arm64/boot/dts/bitmain/ 1420F: arch/arm64/boot/dts/bitmain/
1421F: drivers/pinctrl/pinctrl-bm1880.c
1421F: Documentation/devicetree/bindings/arm/bitmain.yaml 1422F: Documentation/devicetree/bindings/arm/bitmain.yaml
1423F: Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt
1422 1424
1423ARM/CALXEDA HIGHBANK ARCHITECTURE 1425ARM/CALXEDA HIGHBANK ARCHITECTURE
1424M: Rob Herring <robh@kernel.org> 1426M: Rob Herring <robh@kernel.org>
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7786.h b/arch/sh/include/cpu-sh4/cpu/sh7786.h
index 8f9bfbf3cdb1..d6cce65b4871 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7786.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7786.h
@@ -132,7 +132,7 @@ enum {
132 132
133static inline u32 sh7786_mm_sel(void) 133static inline u32 sh7786_mm_sel(void)
134{ 134{
135 return __raw_readl(0xFC400020) & 0x7; 135 return __raw_readl((const volatile void __iomem *)0xFC400020) & 0x7;
136} 136}
137 137
138#endif /* __CPU_SH7786_H__ */ 138#endif /* __CPU_SH7786_H__ */
diff --git a/drivers/gpio/gpiolib-devprop.c b/drivers/gpio/gpiolib-devprop.c
index dd517098ab95..53781b253986 100644
--- a/drivers/gpio/gpiolib-devprop.c
+++ b/drivers/gpio/gpiolib-devprop.c
@@ -10,6 +10,7 @@
10#include <linux/slab.h> 10#include <linux/slab.h>
11#include <linux/gpio/consumer.h> 11#include <linux/gpio/consumer.h>
12#include <linux/gpio/driver.h> 12#include <linux/gpio/driver.h>
13#include <linux/export.h>
13 14
14#include "gpiolib.h" 15#include "gpiolib.h"
15 16
@@ -56,3 +57,4 @@ void devprop_gpiochip_set_names(struct gpio_chip *chip,
56 57
57 kfree(names); 58 kfree(names);
58} 59}
60EXPORT_SYMBOL_GPL(devprop_gpiochip_set_names);
diff --git a/drivers/gpio/gpiolib.h b/drivers/gpio/gpiolib.h
index 078ab17b96bf..3243c1eb5c88 100644
--- a/drivers/gpio/gpiolib.h
+++ b/drivers/gpio/gpiolib.h
@@ -243,9 +243,6 @@ static inline int gpio_chip_hwgpio(const struct gpio_desc *desc)
243 return desc - &desc->gdev->descs[0]; 243 return desc - &desc->gdev->descs[0];
244} 244}
245 245
246void devprop_gpiochip_set_names(struct gpio_chip *chip,
247 const struct fwnode_handle *fwnode);
248
249/* With descriptor prefix */ 246/* With descriptor prefix */
250 247
251#define gpiod_emerg(desc, fmt, ...) \ 248#define gpiod_emerg(desc, fmt, ...) \
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 2764d713fea8..19d8af9a36a2 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -108,6 +108,14 @@ config PINCTRL_AMD
108 Requires ACPI/FDT device enumeration code to set up a platform 108 Requires ACPI/FDT device enumeration code to set up a platform
109 device. 109 device.
110 110
111config PINCTRL_BM1880
112 bool "Bitmain BM1880 Pinctrl driver"
113 depends on OF && (ARCH_BITMAIN || COMPILE_TEST)
114 default ARCH_BITMAIN
115 select PINMUX
116 help
117 Pinctrl driver for Bitmain BM1880 SoC.
118
111config PINCTRL_DA850_PUPD 119config PINCTRL_DA850_PUPD
112 tristate "TI DA850/OMAP-L138/AM18XX pullup/pulldown groups" 120 tristate "TI DA850/OMAP-L138/AM18XX pullup/pulldown groups"
113 depends on OF && (ARCH_DAVINCI_DA850 || COMPILE_TEST) 121 depends on OF && (ARCH_DAVINCI_DA850 || COMPILE_TEST)
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 712184b74a5c..62df40647e02 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o
14obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o 14obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
15obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o 15obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
16obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o 16obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
17obj-$(CONFIG_PINCTRL_BM1880) += pinctrl-bm1880.o
17obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o 18obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o
18obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o 19obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
19obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o 20obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
diff --git a/drivers/pinctrl/cirrus/Kconfig b/drivers/pinctrl/cirrus/Kconfig
index 27013e5949bc..74af07e25174 100644
--- a/drivers/pinctrl/cirrus/Kconfig
+++ b/drivers/pinctrl/cirrus/Kconfig
@@ -1,3 +1,13 @@
1config PINCTRL_LOCHNAGAR
2 tristate "Cirrus Logic Lochnagar pinctrl driver"
3 depends on MFD_LOCHNAGAR
4 select PINMUX
5 select PINCONF
6 select GENERIC_PINCONF
7 help
8 This driver supports configuring the GPIO and other pin configuration
9 of the Cirrus Logic Lochnagar audio development board.
10
1# This is all selected by the Madera MFD driver Kconfig options 11# This is all selected by the Madera MFD driver Kconfig options
2config PINCTRL_MADERA 12config PINCTRL_MADERA
3 tristate 13 tristate
diff --git a/drivers/pinctrl/cirrus/Makefile b/drivers/pinctrl/cirrus/Makefile
index 6e4938cde9e3..20baebf438f6 100644
--- a/drivers/pinctrl/cirrus/Makefile
+++ b/drivers/pinctrl/cirrus/Makefile
@@ -1,4 +1,6 @@
1# Cirrus Logic pinctrl drivers 1# Cirrus Logic pinctrl drivers
2obj-$(CONFIG_PINCTRL_LOCHNAGAR) += pinctrl-lochnagar.o
3
2pinctrl-madera-objs := pinctrl-madera-core.o 4pinctrl-madera-objs := pinctrl-madera-core.o
3ifeq ($(CONFIG_PINCTRL_CS47L35),y) 5ifeq ($(CONFIG_PINCTRL_CS47L35),y)
4pinctrl-madera-objs += pinctrl-cs47l35.o 6pinctrl-madera-objs += pinctrl-cs47l35.o
diff --git a/drivers/pinctrl/cirrus/pinctrl-lochnagar.c b/drivers/pinctrl/cirrus/pinctrl-lochnagar.c
new file mode 100644
index 000000000000..670ac53a3141
--- /dev/null
+++ b/drivers/pinctrl/cirrus/pinctrl-lochnagar.c
@@ -0,0 +1,1235 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Lochnagar pin and GPIO control
4 *
5 * Copyright (c) 2017-2018 Cirrus Logic, Inc. and
6 * Cirrus Logic International Semiconductor Ltd.
7 *
8 * Author: Charles Keepax <ckeepax@opensource.cirrus.com>
9 */
10
11#include <linux/err.h>
12#include <linux/errno.h>
13#include <linux/gpio/driver.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/regmap.h>
18#include <linux/pinctrl/pinctrl.h>
19#include <linux/pinctrl/pinmux.h>
20#include <linux/pinctrl/pinconf.h>
21#include <linux/pinctrl/pinconf-generic.h>
22
23#include <linux/mfd/lochnagar.h>
24#include <linux/mfd/lochnagar1_regs.h>
25#include <linux/mfd/lochnagar2_regs.h>
26
27#include <dt-bindings/pinctrl/lochnagar.h>
28
29#include "../pinctrl-utils.h"
30
31#define LN2_NUM_GPIO_CHANNELS 16
32
33#define LN_CDC_AIF1_STR "codec-aif1"
34#define LN_CDC_AIF2_STR "codec-aif2"
35#define LN_CDC_AIF3_STR "codec-aif3"
36#define LN_DSP_AIF1_STR "dsp-aif1"
37#define LN_DSP_AIF2_STR "dsp-aif2"
38#define LN_PSIA1_STR "psia1"
39#define LN_PSIA2_STR "psia2"
40#define LN_GF_AIF1_STR "gf-aif1"
41#define LN_GF_AIF2_STR "gf-aif2"
42#define LN_GF_AIF3_STR "gf-aif3"
43#define LN_GF_AIF4_STR "gf-aif4"
44#define LN_SPDIF_AIF_STR "spdif-aif"
45#define LN_USB_AIF1_STR "usb-aif1"
46#define LN_USB_AIF2_STR "usb-aif2"
47#define LN_ADAT_AIF_STR "adat-aif"
48#define LN_SOUNDCARD_AIF_STR "soundcard-aif"
49
50#define LN_PIN_GPIO(REV, ID, NAME, REG, SHIFT, INVERT) \
51static const struct lochnagar_pin lochnagar##REV##_##ID##_pin = { \
52 .name = NAME, .type = LN_PTYPE_GPIO, .reg = LOCHNAGAR##REV##_##REG, \
53 .shift = LOCHNAGAR##REV##_##SHIFT##_SHIFT, .invert = INVERT, \
54}
55
56#define LN_PIN_SAIF(REV, ID, NAME) \
57static const struct lochnagar_pin lochnagar##REV##_##ID##_pin = \
58 { .name = NAME, .type = LN_PTYPE_AIF, }
59
60#define LN_PIN_AIF(REV, ID) \
61 LN_PIN_SAIF(REV, ID##_BCLK, LN_##ID##_STR"-bclk"); \
62 LN_PIN_SAIF(REV, ID##_LRCLK, LN_##ID##_STR"-lrclk"); \
63 LN_PIN_SAIF(REV, ID##_RXDAT, LN_##ID##_STR"-rxdat"); \
64 LN_PIN_SAIF(REV, ID##_TXDAT, LN_##ID##_STR"-txdat")
65
66#define LN1_PIN_GPIO(ID, NAME, REG, SHIFT, INVERT) \
67 LN_PIN_GPIO(1, ID, NAME, REG, SHIFT, INVERT)
68
69#define LN1_PIN_MUX(ID, NAME) \
70static const struct lochnagar_pin lochnagar1_##ID##_pin = \
71 { .name = NAME, .type = LN_PTYPE_MUX, .reg = LOCHNAGAR1_##ID, }
72
73#define LN1_PIN_AIF(ID) LN_PIN_AIF(1, ID)
74
75#define LN2_PIN_GPIO(ID, NAME, REG, SHIFT, INVERT) \
76 LN_PIN_GPIO(2, ID, NAME, REG, SHIFT, INVERT)
77
78#define LN2_PIN_MUX(ID, NAME) \
79static const struct lochnagar_pin lochnagar2_##ID##_pin = \
80 { .name = NAME, .type = LN_PTYPE_MUX, .reg = LOCHNAGAR2_GPIO_##ID, }
81
82#define LN2_PIN_AIF(ID) LN_PIN_AIF(2, ID)
83
84#define LN2_PIN_GAI(ID) \
85 LN2_PIN_MUX(ID##_BCLK, LN_##ID##_STR"-bclk"); \
86 LN2_PIN_MUX(ID##_LRCLK, LN_##ID##_STR"-lrclk"); \
87 LN2_PIN_MUX(ID##_RXDAT, LN_##ID##_STR"-rxdat"); \
88 LN2_PIN_MUX(ID##_TXDAT, LN_##ID##_STR"-txdat")
89
90#define LN_PIN(REV, ID) [LOCHNAGAR##REV##_PIN_##ID] = { \
91 .number = LOCHNAGAR##REV##_PIN_##ID, \
92 .name = lochnagar##REV##_##ID##_pin.name, \
93 .drv_data = (void *)&lochnagar##REV##_##ID##_pin, \
94}
95
96#define LN1_PIN(ID) LN_PIN(1, ID)
97#define LN2_PIN(ID) LN_PIN(2, ID)
98
99#define LN_PINS(REV, ID) \
100 LN_PIN(REV, ID##_BCLK), LN_PIN(REV, ID##_LRCLK), \
101 LN_PIN(REV, ID##_RXDAT), LN_PIN(REV, ID##_TXDAT)
102
103#define LN1_PINS(ID) LN_PINS(1, ID)
104#define LN2_PINS(ID) LN_PINS(2, ID)
105
106enum {
107 LOCHNAGAR1_PIN_GF_GPIO2 = LOCHNAGAR1_PIN_NUM_GPIOS,
108 LOCHNAGAR1_PIN_GF_GPIO3,
109 LOCHNAGAR1_PIN_GF_GPIO7,
110 LOCHNAGAR1_PIN_LED1,
111 LOCHNAGAR1_PIN_LED2,
112 LOCHNAGAR1_PIN_CDC_AIF1_BCLK,
113 LOCHNAGAR1_PIN_CDC_AIF1_LRCLK,
114 LOCHNAGAR1_PIN_CDC_AIF1_RXDAT,
115 LOCHNAGAR1_PIN_CDC_AIF1_TXDAT,
116 LOCHNAGAR1_PIN_CDC_AIF2_BCLK,
117 LOCHNAGAR1_PIN_CDC_AIF2_LRCLK,
118 LOCHNAGAR1_PIN_CDC_AIF2_RXDAT,
119 LOCHNAGAR1_PIN_CDC_AIF2_TXDAT,
120 LOCHNAGAR1_PIN_CDC_AIF3_BCLK,
121 LOCHNAGAR1_PIN_CDC_AIF3_LRCLK,
122 LOCHNAGAR1_PIN_CDC_AIF3_RXDAT,
123 LOCHNAGAR1_PIN_CDC_AIF3_TXDAT,
124 LOCHNAGAR1_PIN_DSP_AIF1_BCLK,
125 LOCHNAGAR1_PIN_DSP_AIF1_LRCLK,
126 LOCHNAGAR1_PIN_DSP_AIF1_RXDAT,
127 LOCHNAGAR1_PIN_DSP_AIF1_TXDAT,
128 LOCHNAGAR1_PIN_DSP_AIF2_BCLK,
129 LOCHNAGAR1_PIN_DSP_AIF2_LRCLK,
130 LOCHNAGAR1_PIN_DSP_AIF2_RXDAT,
131 LOCHNAGAR1_PIN_DSP_AIF2_TXDAT,
132 LOCHNAGAR1_PIN_PSIA1_BCLK,
133 LOCHNAGAR1_PIN_PSIA1_LRCLK,
134 LOCHNAGAR1_PIN_PSIA1_RXDAT,
135 LOCHNAGAR1_PIN_PSIA1_TXDAT,
136 LOCHNAGAR1_PIN_PSIA2_BCLK,
137 LOCHNAGAR1_PIN_PSIA2_LRCLK,
138 LOCHNAGAR1_PIN_PSIA2_RXDAT,
139 LOCHNAGAR1_PIN_PSIA2_TXDAT,
140 LOCHNAGAR1_PIN_SPDIF_AIF_BCLK,
141 LOCHNAGAR1_PIN_SPDIF_AIF_LRCLK,
142 LOCHNAGAR1_PIN_SPDIF_AIF_RXDAT,
143 LOCHNAGAR1_PIN_SPDIF_AIF_TXDAT,
144 LOCHNAGAR1_PIN_GF_AIF3_BCLK,
145 LOCHNAGAR1_PIN_GF_AIF3_RXDAT,
146 LOCHNAGAR1_PIN_GF_AIF3_LRCLK,
147 LOCHNAGAR1_PIN_GF_AIF3_TXDAT,
148 LOCHNAGAR1_PIN_GF_AIF4_BCLK,
149 LOCHNAGAR1_PIN_GF_AIF4_RXDAT,
150 LOCHNAGAR1_PIN_GF_AIF4_LRCLK,
151 LOCHNAGAR1_PIN_GF_AIF4_TXDAT,
152 LOCHNAGAR1_PIN_GF_AIF1_BCLK,
153 LOCHNAGAR1_PIN_GF_AIF1_RXDAT,
154 LOCHNAGAR1_PIN_GF_AIF1_LRCLK,
155 LOCHNAGAR1_PIN_GF_AIF1_TXDAT,
156 LOCHNAGAR1_PIN_GF_AIF2_BCLK,
157 LOCHNAGAR1_PIN_GF_AIF2_RXDAT,
158 LOCHNAGAR1_PIN_GF_AIF2_LRCLK,
159 LOCHNAGAR1_PIN_GF_AIF2_TXDAT,
160
161 LOCHNAGAR2_PIN_SPDIF_AIF_BCLK = LOCHNAGAR2_PIN_NUM_GPIOS,
162 LOCHNAGAR2_PIN_SPDIF_AIF_LRCLK,
163 LOCHNAGAR2_PIN_SPDIF_AIF_RXDAT,
164 LOCHNAGAR2_PIN_SPDIF_AIF_TXDAT,
165 LOCHNAGAR2_PIN_USB_AIF1_BCLK,
166 LOCHNAGAR2_PIN_USB_AIF1_LRCLK,
167 LOCHNAGAR2_PIN_USB_AIF1_RXDAT,
168 LOCHNAGAR2_PIN_USB_AIF1_TXDAT,
169 LOCHNAGAR2_PIN_USB_AIF2_BCLK,
170 LOCHNAGAR2_PIN_USB_AIF2_LRCLK,
171 LOCHNAGAR2_PIN_USB_AIF2_RXDAT,
172 LOCHNAGAR2_PIN_USB_AIF2_TXDAT,
173 LOCHNAGAR2_PIN_ADAT_AIF_BCLK,
174 LOCHNAGAR2_PIN_ADAT_AIF_LRCLK,
175 LOCHNAGAR2_PIN_ADAT_AIF_RXDAT,
176 LOCHNAGAR2_PIN_ADAT_AIF_TXDAT,
177 LOCHNAGAR2_PIN_SOUNDCARD_AIF_BCLK,
178 LOCHNAGAR2_PIN_SOUNDCARD_AIF_LRCLK,
179 LOCHNAGAR2_PIN_SOUNDCARD_AIF_RXDAT,
180 LOCHNAGAR2_PIN_SOUNDCARD_AIF_TXDAT,
181};
182
183enum lochnagar_pin_type {
184 LN_PTYPE_GPIO,
185 LN_PTYPE_MUX,
186 LN_PTYPE_AIF,
187 LN_PTYPE_COUNT,
188};
189
190struct lochnagar_pin {
191 const char name[20];
192
193 enum lochnagar_pin_type type;
194
195 unsigned int reg;
196 int shift;
197 bool invert;
198};
199
200LN1_PIN_GPIO(CDC_RESET, "codec-reset", RST, CDC_RESET, 1);
201LN1_PIN_GPIO(DSP_RESET, "dsp-reset", RST, DSP_RESET, 1);
202LN1_PIN_GPIO(CDC_CIF1MODE, "codec-cif1mode", I2C_CTRL, CDC_CIF_MODE, 0);
203LN1_PIN_MUX(GF_GPIO2, "gf-gpio2");
204LN1_PIN_MUX(GF_GPIO3, "gf-gpio3");
205LN1_PIN_MUX(GF_GPIO7, "gf-gpio7");
206LN1_PIN_MUX(LED1, "led1");
207LN1_PIN_MUX(LED2, "led2");
208LN1_PIN_AIF(CDC_AIF1);
209LN1_PIN_AIF(CDC_AIF2);
210LN1_PIN_AIF(CDC_AIF3);
211LN1_PIN_AIF(DSP_AIF1);
212LN1_PIN_AIF(DSP_AIF2);
213LN1_PIN_AIF(PSIA1);
214LN1_PIN_AIF(PSIA2);
215LN1_PIN_AIF(SPDIF_AIF);
216LN1_PIN_AIF(GF_AIF1);
217LN1_PIN_AIF(GF_AIF2);
218LN1_PIN_AIF(GF_AIF3);
219LN1_PIN_AIF(GF_AIF4);
220
221LN2_PIN_GPIO(CDC_RESET, "codec-reset", MINICARD_RESETS, CDC_RESET, 1);
222LN2_PIN_GPIO(DSP_RESET, "dsp-reset", MINICARD_RESETS, DSP_RESET, 1);
223LN2_PIN_GPIO(CDC_CIF1MODE, "codec-cif1mode", COMMS_CTRL4, CDC_CIF1MODE, 0);
224LN2_PIN_GPIO(CDC_LDOENA, "codec-ldoena", POWER_CTRL, PWR_ENA, 0);
225LN2_PIN_GPIO(SPDIF_HWMODE, "spdif-hwmode", SPDIF_CTRL, SPDIF_HWMODE, 0);
226LN2_PIN_GPIO(SPDIF_RESET, "spdif-reset", SPDIF_CTRL, SPDIF_RESET, 1);
227LN2_PIN_MUX(FPGA_GPIO1, "fpga-gpio1");
228LN2_PIN_MUX(FPGA_GPIO2, "fpga-gpio2");
229LN2_PIN_MUX(FPGA_GPIO3, "fpga-gpio3");
230LN2_PIN_MUX(FPGA_GPIO4, "fpga-gpio4");
231LN2_PIN_MUX(FPGA_GPIO5, "fpga-gpio5");
232LN2_PIN_MUX(FPGA_GPIO6, "fpga-gpio6");
233LN2_PIN_MUX(CDC_GPIO1, "codec-gpio1");
234LN2_PIN_MUX(CDC_GPIO2, "codec-gpio2");
235LN2_PIN_MUX(CDC_GPIO3, "codec-gpio3");
236LN2_PIN_MUX(CDC_GPIO4, "codec-gpio4");
237LN2_PIN_MUX(CDC_GPIO5, "codec-gpio5");
238LN2_PIN_MUX(CDC_GPIO6, "codec-gpio6");
239LN2_PIN_MUX(CDC_GPIO7, "codec-gpio7");
240LN2_PIN_MUX(CDC_GPIO8, "codec-gpio8");
241LN2_PIN_MUX(DSP_GPIO1, "dsp-gpio1");
242LN2_PIN_MUX(DSP_GPIO2, "dsp-gpio2");
243LN2_PIN_MUX(DSP_GPIO3, "dsp-gpio3");
244LN2_PIN_MUX(DSP_GPIO4, "dsp-gpio4");
245LN2_PIN_MUX(DSP_GPIO5, "dsp-gpio5");
246LN2_PIN_MUX(DSP_GPIO6, "dsp-gpio6");
247LN2_PIN_MUX(GF_GPIO2, "gf-gpio2");
248LN2_PIN_MUX(GF_GPIO3, "gf-gpio3");
249LN2_PIN_MUX(GF_GPIO7, "gf-gpio7");
250LN2_PIN_MUX(DSP_UART1_RX, "dsp-uart1-rx");
251LN2_PIN_MUX(DSP_UART1_TX, "dsp-uart1-tx");
252LN2_PIN_MUX(DSP_UART2_RX, "dsp-uart2-rx");
253LN2_PIN_MUX(DSP_UART2_TX, "dsp-uart2-tx");
254LN2_PIN_MUX(GF_UART2_RX, "gf-uart2-rx");
255LN2_PIN_MUX(GF_UART2_TX, "gf-uart2-tx");
256LN2_PIN_MUX(USB_UART_RX, "usb-uart-rx");
257LN2_PIN_MUX(CDC_PDMCLK1, "codec-pdmclk1");
258LN2_PIN_MUX(CDC_PDMDAT1, "codec-pdmdat1");
259LN2_PIN_MUX(CDC_PDMCLK2, "codec-pdmclk2");
260LN2_PIN_MUX(CDC_PDMDAT2, "codec-pdmdat2");
261LN2_PIN_MUX(CDC_DMICCLK1, "codec-dmicclk1");
262LN2_PIN_MUX(CDC_DMICDAT1, "codec-dmicdat1");
263LN2_PIN_MUX(CDC_DMICCLK2, "codec-dmicclk2");
264LN2_PIN_MUX(CDC_DMICDAT2, "codec-dmicdat2");
265LN2_PIN_MUX(CDC_DMICCLK3, "codec-dmicclk3");
266LN2_PIN_MUX(CDC_DMICDAT3, "codec-dmicdat3");
267LN2_PIN_MUX(CDC_DMICCLK4, "codec-dmicclk4");
268LN2_PIN_MUX(CDC_DMICDAT4, "codec-dmicdat4");
269LN2_PIN_MUX(DSP_DMICCLK1, "dsp-dmicclk1");
270LN2_PIN_MUX(DSP_DMICDAT1, "dsp-dmicdat1");
271LN2_PIN_MUX(DSP_DMICCLK2, "dsp-dmicclk2");
272LN2_PIN_MUX(DSP_DMICDAT2, "dsp-dmicdat2");
273LN2_PIN_MUX(I2C2_SCL, "i2c2-scl");
274LN2_PIN_MUX(I2C2_SDA, "i2c2-sda");
275LN2_PIN_MUX(I2C3_SCL, "i2c3-scl");
276LN2_PIN_MUX(I2C3_SDA, "i2c3-sda");
277LN2_PIN_MUX(I2C4_SCL, "i2c4-scl");
278LN2_PIN_MUX(I2C4_SDA, "i2c4-sda");
279LN2_PIN_MUX(DSP_STANDBY, "dsp-standby");
280LN2_PIN_MUX(CDC_MCLK1, "codec-mclk1");
281LN2_PIN_MUX(CDC_MCLK2, "codec-mclk2");
282LN2_PIN_MUX(DSP_CLKIN, "dsp-clkin");
283LN2_PIN_MUX(PSIA1_MCLK, "psia1-mclk");
284LN2_PIN_MUX(PSIA2_MCLK, "psia2-mclk");
285LN2_PIN_MUX(GF_GPIO1, "gf-gpio1");
286LN2_PIN_MUX(GF_GPIO5, "gf-gpio5");
287LN2_PIN_MUX(DSP_GPIO20, "dsp-gpio20");
288LN2_PIN_GAI(CDC_AIF1);
289LN2_PIN_GAI(CDC_AIF2);
290LN2_PIN_GAI(CDC_AIF3);
291LN2_PIN_GAI(DSP_AIF1);
292LN2_PIN_GAI(DSP_AIF2);
293LN2_PIN_GAI(PSIA1);
294LN2_PIN_GAI(PSIA2);
295LN2_PIN_GAI(GF_AIF1);
296LN2_PIN_GAI(GF_AIF2);
297LN2_PIN_GAI(GF_AIF3);
298LN2_PIN_GAI(GF_AIF4);
299LN2_PIN_AIF(SPDIF_AIF);
300LN2_PIN_AIF(USB_AIF1);
301LN2_PIN_AIF(USB_AIF2);
302LN2_PIN_AIF(ADAT_AIF);
303LN2_PIN_AIF(SOUNDCARD_AIF);
304
305static const struct pinctrl_pin_desc lochnagar1_pins[] = {
306 LN1_PIN(CDC_RESET), LN1_PIN(DSP_RESET), LN1_PIN(CDC_CIF1MODE),
307 LN1_PIN(GF_GPIO2), LN1_PIN(GF_GPIO3), LN1_PIN(GF_GPIO7),
308 LN1_PIN(LED1), LN1_PIN(LED2),
309 LN1_PINS(CDC_AIF1), LN1_PINS(CDC_AIF2), LN1_PINS(CDC_AIF3),
310 LN1_PINS(DSP_AIF1), LN1_PINS(DSP_AIF2),
311 LN1_PINS(PSIA1), LN1_PINS(PSIA2),
312 LN1_PINS(SPDIF_AIF),
313 LN1_PINS(GF_AIF1), LN1_PINS(GF_AIF2),
314 LN1_PINS(GF_AIF3), LN1_PINS(GF_AIF4),
315};
316
317static const struct pinctrl_pin_desc lochnagar2_pins[] = {
318 LN2_PIN(CDC_RESET), LN2_PIN(DSP_RESET), LN2_PIN(CDC_CIF1MODE),
319 LN2_PIN(CDC_LDOENA),
320 LN2_PIN(SPDIF_HWMODE), LN2_PIN(SPDIF_RESET),
321 LN2_PIN(FPGA_GPIO1), LN2_PIN(FPGA_GPIO2), LN2_PIN(FPGA_GPIO3),
322 LN2_PIN(FPGA_GPIO4), LN2_PIN(FPGA_GPIO5), LN2_PIN(FPGA_GPIO6),
323 LN2_PIN(CDC_GPIO1), LN2_PIN(CDC_GPIO2), LN2_PIN(CDC_GPIO3),
324 LN2_PIN(CDC_GPIO4), LN2_PIN(CDC_GPIO5), LN2_PIN(CDC_GPIO6),
325 LN2_PIN(CDC_GPIO7), LN2_PIN(CDC_GPIO8),
326 LN2_PIN(DSP_GPIO1), LN2_PIN(DSP_GPIO2), LN2_PIN(DSP_GPIO3),
327 LN2_PIN(DSP_GPIO4), LN2_PIN(DSP_GPIO5), LN2_PIN(DSP_GPIO6),
328 LN2_PIN(DSP_GPIO20),
329 LN2_PIN(GF_GPIO1), LN2_PIN(GF_GPIO2), LN2_PIN(GF_GPIO3),
330 LN2_PIN(GF_GPIO5), LN2_PIN(GF_GPIO7),
331 LN2_PINS(CDC_AIF1), LN2_PINS(CDC_AIF2), LN2_PINS(CDC_AIF3),
332 LN2_PINS(DSP_AIF1), LN2_PINS(DSP_AIF2),
333 LN2_PINS(PSIA1), LN2_PINS(PSIA2),
334 LN2_PINS(GF_AIF1), LN2_PINS(GF_AIF2),
335 LN2_PINS(GF_AIF3), LN2_PINS(GF_AIF4),
336 LN2_PIN(DSP_UART1_RX), LN2_PIN(DSP_UART1_TX),
337 LN2_PIN(DSP_UART2_RX), LN2_PIN(DSP_UART2_TX),
338 LN2_PIN(GF_UART2_RX), LN2_PIN(GF_UART2_TX),
339 LN2_PIN(USB_UART_RX),
340 LN2_PIN(CDC_PDMCLK1), LN2_PIN(CDC_PDMDAT1),
341 LN2_PIN(CDC_PDMCLK2), LN2_PIN(CDC_PDMDAT2),
342 LN2_PIN(CDC_DMICCLK1), LN2_PIN(CDC_DMICDAT1),
343 LN2_PIN(CDC_DMICCLK2), LN2_PIN(CDC_DMICDAT2),
344 LN2_PIN(CDC_DMICCLK3), LN2_PIN(CDC_DMICDAT3),
345 LN2_PIN(CDC_DMICCLK4), LN2_PIN(CDC_DMICDAT4),
346 LN2_PIN(DSP_DMICCLK1), LN2_PIN(DSP_DMICDAT1),
347 LN2_PIN(DSP_DMICCLK2), LN2_PIN(DSP_DMICDAT2),
348 LN2_PIN(I2C2_SCL), LN2_PIN(I2C2_SDA),
349 LN2_PIN(I2C3_SCL), LN2_PIN(I2C3_SDA),
350 LN2_PIN(I2C4_SCL), LN2_PIN(I2C4_SDA),
351 LN2_PIN(DSP_STANDBY),
352 LN2_PIN(CDC_MCLK1), LN2_PIN(CDC_MCLK2),
353 LN2_PIN(DSP_CLKIN),
354 LN2_PIN(PSIA1_MCLK), LN2_PIN(PSIA2_MCLK),
355 LN2_PINS(SPDIF_AIF),
356 LN2_PINS(USB_AIF1), LN2_PINS(USB_AIF2),
357 LN2_PINS(ADAT_AIF),
358 LN2_PINS(SOUNDCARD_AIF),
359};
360
361#define LN_AIF_PINS(REV, ID) \
362 LOCHNAGAR##REV##_PIN_##ID##_BCLK, \
363 LOCHNAGAR##REV##_PIN_##ID##_LRCLK, \
364 LOCHNAGAR##REV##_PIN_##ID##_TXDAT, \
365 LOCHNAGAR##REV##_PIN_##ID##_RXDAT,
366
367#define LN1_AIF(ID, CTRL) \
368static const struct lochnagar_aif lochnagar1_##ID##_aif = { \
369 .name = LN_##ID##_STR, \
370 .pins = { LN_AIF_PINS(1, ID) }, \
371 .src_reg = LOCHNAGAR1_##ID##_SEL, \
372 .src_mask = LOCHNAGAR1_SRC_MASK, \
373 .ctrl_reg = LOCHNAGAR1_##CTRL, \
374 .ena_mask = LOCHNAGAR1_##ID##_ENA_MASK, \
375 .master_mask = LOCHNAGAR1_##ID##_LRCLK_DIR_MASK | \
376 LOCHNAGAR1_##ID##_BCLK_DIR_MASK, \
377}
378
379#define LN2_AIF(ID) \
380static const struct lochnagar_aif lochnagar2_##ID##_aif = { \
381 .name = LN_##ID##_STR, \
382 .pins = { LN_AIF_PINS(2, ID) }, \
383 .src_reg = LOCHNAGAR2_##ID##_CTRL, \
384 .src_mask = LOCHNAGAR2_AIF_SRC_MASK, \
385 .ctrl_reg = LOCHNAGAR2_##ID##_CTRL, \
386 .ena_mask = LOCHNAGAR2_AIF_ENA_MASK, \
387 .master_mask = LOCHNAGAR2_AIF_LRCLK_DIR_MASK | \
388 LOCHNAGAR2_AIF_BCLK_DIR_MASK, \
389}
390
391struct lochnagar_aif {
392 const char name[16];
393
394 unsigned int pins[4];
395
396 u16 src_reg;
397 u16 src_mask;
398
399 u16 ctrl_reg;
400 u16 ena_mask;
401 u16 master_mask;
402};
403
404LN1_AIF(CDC_AIF1, CDC_AIF_CTRL1);
405LN1_AIF(CDC_AIF2, CDC_AIF_CTRL1);
406LN1_AIF(CDC_AIF3, CDC_AIF_CTRL2);
407LN1_AIF(DSP_AIF1, DSP_AIF);
408LN1_AIF(DSP_AIF2, DSP_AIF);
409LN1_AIF(PSIA1, PSIA_AIF);
410LN1_AIF(PSIA2, PSIA_AIF);
411LN1_AIF(GF_AIF1, GF_AIF1);
412LN1_AIF(GF_AIF2, GF_AIF2);
413LN1_AIF(GF_AIF3, GF_AIF1);
414LN1_AIF(GF_AIF4, GF_AIF2);
415LN1_AIF(SPDIF_AIF, EXT_AIF_CTRL);
416
417LN2_AIF(CDC_AIF1);
418LN2_AIF(CDC_AIF2);
419LN2_AIF(CDC_AIF3);
420LN2_AIF(DSP_AIF1);
421LN2_AIF(DSP_AIF2);
422LN2_AIF(PSIA1);
423LN2_AIF(PSIA2);
424LN2_AIF(GF_AIF1);
425LN2_AIF(GF_AIF2);
426LN2_AIF(GF_AIF3);
427LN2_AIF(GF_AIF4);
428LN2_AIF(SPDIF_AIF);
429LN2_AIF(USB_AIF1);
430LN2_AIF(USB_AIF2);
431LN2_AIF(ADAT_AIF);
432LN2_AIF(SOUNDCARD_AIF);
433
434#define LN2_OP_AIF 0x00
435#define LN2_OP_GPIO 0xFE
436
437#define LN_FUNC(NAME, TYPE, OP) \
438 { .name = NAME, .type = LN_FTYPE_##TYPE, .op = OP }
439
440#define LN_FUNC_PIN(REV, ID, OP) \
441 LN_FUNC(lochnagar##REV##_##ID##_pin.name, PIN, OP)
442
443#define LN1_FUNC_PIN(ID, OP) LN_FUNC_PIN(1, ID, OP)
444#define LN2_FUNC_PIN(ID, OP) LN_FUNC_PIN(2, ID, OP)
445
446#define LN_FUNC_AIF(REV, ID, OP) \
447 LN_FUNC(lochnagar##REV##_##ID##_aif.name, AIF, OP)
448
449#define LN1_FUNC_AIF(ID, OP) LN_FUNC_AIF(1, ID, OP)
450#define LN2_FUNC_AIF(ID, OP) LN_FUNC_AIF(2, ID, OP)
451
452#define LN2_FUNC_GAI(ID, OP, BOP, LROP, RXOP, TXOP) \
453 LN2_FUNC_AIF(ID, OP), \
454 LN_FUNC(lochnagar2_##ID##_BCLK_pin.name, PIN, BOP), \
455 LN_FUNC(lochnagar2_##ID##_LRCLK_pin.name, PIN, LROP), \
456 LN_FUNC(lochnagar2_##ID##_RXDAT_pin.name, PIN, RXOP), \
457 LN_FUNC(lochnagar2_##ID##_TXDAT_pin.name, PIN, TXOP)
458
459enum lochnagar_func_type {
460 LN_FTYPE_PIN,
461 LN_FTYPE_AIF,
462 LN_FTYPE_COUNT,
463};
464
465struct lochnagar_func {
466 const char * const name;
467
468 enum lochnagar_func_type type;
469
470 u8 op;
471};
472
473static const struct lochnagar_func lochnagar1_funcs[] = {
474 LN_FUNC("dsp-gpio1", PIN, 0x01),
475 LN_FUNC("dsp-gpio2", PIN, 0x02),
476 LN_FUNC("dsp-gpio3", PIN, 0x03),
477 LN_FUNC("codec-gpio1", PIN, 0x04),
478 LN_FUNC("codec-gpio2", PIN, 0x05),
479 LN_FUNC("codec-gpio3", PIN, 0x06),
480 LN_FUNC("codec-gpio4", PIN, 0x07),
481 LN_FUNC("codec-gpio5", PIN, 0x08),
482 LN_FUNC("codec-gpio6", PIN, 0x09),
483 LN_FUNC("codec-gpio7", PIN, 0x0A),
484 LN_FUNC("codec-gpio8", PIN, 0x0B),
485 LN1_FUNC_PIN(GF_GPIO2, 0x0C),
486 LN1_FUNC_PIN(GF_GPIO3, 0x0D),
487 LN1_FUNC_PIN(GF_GPIO7, 0x0E),
488
489 LN1_FUNC_AIF(SPDIF_AIF, 0x01),
490 LN1_FUNC_AIF(PSIA1, 0x02),
491 LN1_FUNC_AIF(PSIA2, 0x03),
492 LN1_FUNC_AIF(CDC_AIF1, 0x04),
493 LN1_FUNC_AIF(CDC_AIF2, 0x05),
494 LN1_FUNC_AIF(CDC_AIF3, 0x06),
495 LN1_FUNC_AIF(DSP_AIF1, 0x07),
496 LN1_FUNC_AIF(DSP_AIF2, 0x08),
497 LN1_FUNC_AIF(GF_AIF3, 0x09),
498 LN1_FUNC_AIF(GF_AIF4, 0x0A),
499 LN1_FUNC_AIF(GF_AIF1, 0x0B),
500 LN1_FUNC_AIF(GF_AIF2, 0x0C),
501};
502
503static const struct lochnagar_func lochnagar2_funcs[] = {
504 LN_FUNC("aif", PIN, LN2_OP_AIF),
505 LN2_FUNC_PIN(FPGA_GPIO1, 0x01),
506 LN2_FUNC_PIN(FPGA_GPIO2, 0x02),
507 LN2_FUNC_PIN(FPGA_GPIO3, 0x03),
508 LN2_FUNC_PIN(FPGA_GPIO4, 0x04),
509 LN2_FUNC_PIN(FPGA_GPIO5, 0x05),
510 LN2_FUNC_PIN(FPGA_GPIO6, 0x06),
511 LN2_FUNC_PIN(CDC_GPIO1, 0x07),
512 LN2_FUNC_PIN(CDC_GPIO2, 0x08),
513 LN2_FUNC_PIN(CDC_GPIO3, 0x09),
514 LN2_FUNC_PIN(CDC_GPIO4, 0x0A),
515 LN2_FUNC_PIN(CDC_GPIO5, 0x0B),
516 LN2_FUNC_PIN(CDC_GPIO6, 0x0C),
517 LN2_FUNC_PIN(CDC_GPIO7, 0x0D),
518 LN2_FUNC_PIN(CDC_GPIO8, 0x0E),
519 LN2_FUNC_PIN(DSP_GPIO1, 0x0F),
520 LN2_FUNC_PIN(DSP_GPIO2, 0x10),
521 LN2_FUNC_PIN(DSP_GPIO3, 0x11),
522 LN2_FUNC_PIN(DSP_GPIO4, 0x12),
523 LN2_FUNC_PIN(DSP_GPIO5, 0x13),
524 LN2_FUNC_PIN(DSP_GPIO6, 0x14),
525 LN2_FUNC_PIN(GF_GPIO2, 0x15),
526 LN2_FUNC_PIN(GF_GPIO3, 0x16),
527 LN2_FUNC_PIN(GF_GPIO7, 0x17),
528 LN2_FUNC_PIN(GF_GPIO1, 0x18),
529 LN2_FUNC_PIN(GF_GPIO5, 0x19),
530 LN2_FUNC_PIN(DSP_GPIO20, 0x1A),
531 LN_FUNC("codec-clkout", PIN, 0x20),
532 LN_FUNC("dsp-clkout", PIN, 0x21),
533 LN_FUNC("pmic-32k", PIN, 0x22),
534 LN_FUNC("spdif-clkout", PIN, 0x23),
535 LN_FUNC("clk-12m288", PIN, 0x24),
536 LN_FUNC("clk-11m2986", PIN, 0x25),
537 LN_FUNC("clk-24m576", PIN, 0x26),
538 LN_FUNC("clk-22m5792", PIN, 0x27),
539 LN_FUNC("xmos-mclk", PIN, 0x29),
540 LN_FUNC("gf-clkout1", PIN, 0x2A),
541 LN_FUNC("gf-mclk1", PIN, 0x2B),
542 LN_FUNC("gf-mclk3", PIN, 0x2C),
543 LN_FUNC("gf-mclk2", PIN, 0x2D),
544 LN_FUNC("gf-clkout2", PIN, 0x2E),
545 LN2_FUNC_PIN(CDC_MCLK1, 0x2F),
546 LN2_FUNC_PIN(CDC_MCLK2, 0x30),
547 LN2_FUNC_PIN(DSP_CLKIN, 0x31),
548 LN2_FUNC_PIN(PSIA1_MCLK, 0x32),
549 LN2_FUNC_PIN(PSIA2_MCLK, 0x33),
550 LN_FUNC("spdif-mclk", PIN, 0x34),
551 LN_FUNC("codec-irq", PIN, 0x42),
552 LN2_FUNC_PIN(CDC_RESET, 0x43),
553 LN2_FUNC_PIN(DSP_RESET, 0x44),
554 LN_FUNC("dsp-irq", PIN, 0x45),
555 LN2_FUNC_PIN(DSP_STANDBY, 0x46),
556 LN2_FUNC_PIN(CDC_PDMCLK1, 0x90),
557 LN2_FUNC_PIN(CDC_PDMDAT1, 0x91),
558 LN2_FUNC_PIN(CDC_PDMCLK2, 0x92),
559 LN2_FUNC_PIN(CDC_PDMDAT2, 0x93),
560 LN2_FUNC_PIN(CDC_DMICCLK1, 0xA0),
561 LN2_FUNC_PIN(CDC_DMICDAT1, 0xA1),
562 LN2_FUNC_PIN(CDC_DMICCLK2, 0xA2),
563 LN2_FUNC_PIN(CDC_DMICDAT2, 0xA3),
564 LN2_FUNC_PIN(CDC_DMICCLK3, 0xA4),
565 LN2_FUNC_PIN(CDC_DMICDAT3, 0xA5),
566 LN2_FUNC_PIN(CDC_DMICCLK4, 0xA6),
567 LN2_FUNC_PIN(CDC_DMICDAT4, 0xA7),
568 LN2_FUNC_PIN(DSP_DMICCLK1, 0xA8),
569 LN2_FUNC_PIN(DSP_DMICDAT1, 0xA9),
570 LN2_FUNC_PIN(DSP_DMICCLK2, 0xAA),
571 LN2_FUNC_PIN(DSP_DMICDAT2, 0xAB),
572 LN2_FUNC_PIN(DSP_UART1_RX, 0xC0),
573 LN2_FUNC_PIN(DSP_UART1_TX, 0xC1),
574 LN2_FUNC_PIN(DSP_UART2_RX, 0xC2),
575 LN2_FUNC_PIN(DSP_UART2_TX, 0xC3),
576 LN2_FUNC_PIN(GF_UART2_RX, 0xC4),
577 LN2_FUNC_PIN(GF_UART2_TX, 0xC5),
578 LN2_FUNC_PIN(USB_UART_RX, 0xC6),
579 LN_FUNC("usb-uart-tx", PIN, 0xC7),
580 LN2_FUNC_PIN(I2C2_SCL, 0xE0),
581 LN2_FUNC_PIN(I2C2_SDA, 0xE1),
582 LN2_FUNC_PIN(I2C3_SCL, 0xE2),
583 LN2_FUNC_PIN(I2C3_SDA, 0xE3),
584 LN2_FUNC_PIN(I2C4_SCL, 0xE4),
585 LN2_FUNC_PIN(I2C4_SDA, 0xE5),
586
587 LN2_FUNC_AIF(SPDIF_AIF, 0x01),
588 LN2_FUNC_GAI(PSIA1, 0x02, 0x50, 0x51, 0x52, 0x53),
589 LN2_FUNC_GAI(PSIA2, 0x03, 0x54, 0x55, 0x56, 0x57),
590 LN2_FUNC_GAI(CDC_AIF1, 0x04, 0x59, 0x5B, 0x5A, 0x58),
591 LN2_FUNC_GAI(CDC_AIF2, 0x05, 0x5D, 0x5F, 0x5E, 0x5C),
592 LN2_FUNC_GAI(CDC_AIF3, 0x06, 0x61, 0x62, 0x63, 0x60),
593 LN2_FUNC_GAI(DSP_AIF1, 0x07, 0x65, 0x67, 0x66, 0x64),
594 LN2_FUNC_GAI(DSP_AIF2, 0x08, 0x69, 0x6B, 0x6A, 0x68),
595 LN2_FUNC_GAI(GF_AIF3, 0x09, 0x6D, 0x6F, 0x6C, 0x6E),
596 LN2_FUNC_GAI(GF_AIF4, 0x0A, 0x71, 0x73, 0x70, 0x72),
597 LN2_FUNC_GAI(GF_AIF1, 0x0B, 0x75, 0x77, 0x74, 0x76),
598 LN2_FUNC_GAI(GF_AIF2, 0x0C, 0x79, 0x7B, 0x78, 0x7A),
599 LN2_FUNC_AIF(USB_AIF1, 0x0D),
600 LN2_FUNC_AIF(USB_AIF2, 0x0E),
601 LN2_FUNC_AIF(ADAT_AIF, 0x0F),
602 LN2_FUNC_AIF(SOUNDCARD_AIF, 0x10),
603};
604
605#define LN_GROUP_PIN(REV, ID) { \
606 .name = lochnagar##REV##_##ID##_pin.name, \
607 .type = LN_FTYPE_PIN, \
608 .pins = &lochnagar##REV##_pins[LOCHNAGAR##REV##_PIN_##ID].number, \
609 .npins = 1, \
610 .priv = &lochnagar##REV##_pins[LOCHNAGAR##REV##_PIN_##ID], \
611}
612
613#define LN_GROUP_AIF(REV, ID) { \
614 .name = lochnagar##REV##_##ID##_aif.name, \
615 .type = LN_FTYPE_AIF, \
616 .pins = lochnagar##REV##_##ID##_aif.pins, \
617 .npins = ARRAY_SIZE(lochnagar##REV##_##ID##_aif.pins), \
618 .priv = &lochnagar##REV##_##ID##_aif, \
619}
620
621#define LN1_GROUP_PIN(ID) LN_GROUP_PIN(1, ID)
622#define LN2_GROUP_PIN(ID) LN_GROUP_PIN(2, ID)
623
624#define LN1_GROUP_AIF(ID) LN_GROUP_AIF(1, ID)
625#define LN2_GROUP_AIF(ID) LN_GROUP_AIF(2, ID)
626
627#define LN2_GROUP_GAI(ID) \
628 LN2_GROUP_AIF(ID), \
629 LN2_GROUP_PIN(ID##_BCLK), LN2_GROUP_PIN(ID##_LRCLK), \
630 LN2_GROUP_PIN(ID##_RXDAT), LN2_GROUP_PIN(ID##_TXDAT)
631
632struct lochnagar_group {
633 const char * const name;
634
635 enum lochnagar_func_type type;
636
637 const unsigned int *pins;
638 unsigned int npins;
639
640 const void *priv;
641};
642
643static const struct lochnagar_group lochnagar1_groups[] = {
644 LN1_GROUP_PIN(GF_GPIO2), LN1_GROUP_PIN(GF_GPIO3),
645 LN1_GROUP_PIN(GF_GPIO7),
646 LN1_GROUP_PIN(LED1), LN1_GROUP_PIN(LED2),
647 LN1_GROUP_AIF(CDC_AIF1), LN1_GROUP_AIF(CDC_AIF2),
648 LN1_GROUP_AIF(CDC_AIF3),
649 LN1_GROUP_AIF(DSP_AIF1), LN1_GROUP_AIF(DSP_AIF2),
650 LN1_GROUP_AIF(PSIA1), LN1_GROUP_AIF(PSIA2),
651 LN1_GROUP_AIF(GF_AIF1), LN1_GROUP_AIF(GF_AIF2),
652 LN1_GROUP_AIF(GF_AIF3), LN1_GROUP_AIF(GF_AIF4),
653 LN1_GROUP_AIF(SPDIF_AIF),
654};
655
656static const struct lochnagar_group lochnagar2_groups[] = {
657 LN2_GROUP_PIN(FPGA_GPIO1), LN2_GROUP_PIN(FPGA_GPIO2),
658 LN2_GROUP_PIN(FPGA_GPIO3), LN2_GROUP_PIN(FPGA_GPIO4),
659 LN2_GROUP_PIN(FPGA_GPIO5), LN2_GROUP_PIN(FPGA_GPIO6),
660 LN2_GROUP_PIN(CDC_GPIO1), LN2_GROUP_PIN(CDC_GPIO2),
661 LN2_GROUP_PIN(CDC_GPIO3), LN2_GROUP_PIN(CDC_GPIO4),
662 LN2_GROUP_PIN(CDC_GPIO5), LN2_GROUP_PIN(CDC_GPIO6),
663 LN2_GROUP_PIN(CDC_GPIO7), LN2_GROUP_PIN(CDC_GPIO8),
664 LN2_GROUP_PIN(DSP_GPIO1), LN2_GROUP_PIN(DSP_GPIO2),
665 LN2_GROUP_PIN(DSP_GPIO3), LN2_GROUP_PIN(DSP_GPIO4),
666 LN2_GROUP_PIN(DSP_GPIO5), LN2_GROUP_PIN(DSP_GPIO6),
667 LN2_GROUP_PIN(DSP_GPIO20),
668 LN2_GROUP_PIN(GF_GPIO1),
669 LN2_GROUP_PIN(GF_GPIO2), LN2_GROUP_PIN(GF_GPIO5),
670 LN2_GROUP_PIN(GF_GPIO3), LN2_GROUP_PIN(GF_GPIO7),
671 LN2_GROUP_PIN(DSP_UART1_RX), LN2_GROUP_PIN(DSP_UART1_TX),
672 LN2_GROUP_PIN(DSP_UART2_RX), LN2_GROUP_PIN(DSP_UART2_TX),
673 LN2_GROUP_PIN(GF_UART2_RX), LN2_GROUP_PIN(GF_UART2_TX),
674 LN2_GROUP_PIN(USB_UART_RX),
675 LN2_GROUP_PIN(CDC_PDMCLK1), LN2_GROUP_PIN(CDC_PDMDAT1),
676 LN2_GROUP_PIN(CDC_PDMCLK2), LN2_GROUP_PIN(CDC_PDMDAT2),
677 LN2_GROUP_PIN(CDC_DMICCLK1), LN2_GROUP_PIN(CDC_DMICDAT1),
678 LN2_GROUP_PIN(CDC_DMICCLK2), LN2_GROUP_PIN(CDC_DMICDAT2),
679 LN2_GROUP_PIN(CDC_DMICCLK3), LN2_GROUP_PIN(CDC_DMICDAT3),
680 LN2_GROUP_PIN(CDC_DMICCLK4), LN2_GROUP_PIN(CDC_DMICDAT4),
681 LN2_GROUP_PIN(DSP_DMICCLK1), LN2_GROUP_PIN(DSP_DMICDAT1),
682 LN2_GROUP_PIN(DSP_DMICCLK2), LN2_GROUP_PIN(DSP_DMICDAT2),
683 LN2_GROUP_PIN(I2C2_SCL), LN2_GROUP_PIN(I2C2_SDA),
684 LN2_GROUP_PIN(I2C3_SCL), LN2_GROUP_PIN(I2C3_SDA),
685 LN2_GROUP_PIN(I2C4_SCL), LN2_GROUP_PIN(I2C4_SDA),
686 LN2_GROUP_PIN(DSP_STANDBY),
687 LN2_GROUP_PIN(CDC_MCLK1), LN2_GROUP_PIN(CDC_MCLK2),
688 LN2_GROUP_PIN(DSP_CLKIN),
689 LN2_GROUP_PIN(PSIA1_MCLK), LN2_GROUP_PIN(PSIA2_MCLK),
690 LN2_GROUP_GAI(CDC_AIF1), LN2_GROUP_GAI(CDC_AIF2),
691 LN2_GROUP_GAI(CDC_AIF3),
692 LN2_GROUP_GAI(DSP_AIF1), LN2_GROUP_GAI(DSP_AIF2),
693 LN2_GROUP_GAI(PSIA1), LN2_GROUP_GAI(PSIA2),
694 LN2_GROUP_GAI(GF_AIF1), LN2_GROUP_GAI(GF_AIF2),
695 LN2_GROUP_GAI(GF_AIF3), LN2_GROUP_GAI(GF_AIF4),
696 LN2_GROUP_AIF(SPDIF_AIF),
697 LN2_GROUP_AIF(USB_AIF1), LN2_GROUP_AIF(USB_AIF2),
698 LN2_GROUP_AIF(ADAT_AIF),
699 LN2_GROUP_AIF(SOUNDCARD_AIF),
700};
701
702struct lochnagar_func_groups {
703 const char **groups;
704 unsigned int ngroups;
705};
706
707struct lochnagar_pin_priv {
708 struct lochnagar *lochnagar;
709 struct device *dev;
710
711 const struct lochnagar_func *funcs;
712 unsigned int nfuncs;
713
714 const struct pinctrl_pin_desc *pins;
715 unsigned int npins;
716
717 const struct lochnagar_group *groups;
718 unsigned int ngroups;
719
720 struct lochnagar_func_groups func_groups[LN_FTYPE_COUNT];
721
722 struct gpio_chip gpio_chip;
723};
724
725static int lochnagar_get_groups_count(struct pinctrl_dev *pctldev)
726{
727 struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
728
729 return priv->ngroups;
730}
731
732static const char *lochnagar_get_group_name(struct pinctrl_dev *pctldev,
733 unsigned int group_idx)
734{
735 struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
736
737 return priv->groups[group_idx].name;
738}
739
740static int lochnagar_get_group_pins(struct pinctrl_dev *pctldev,
741 unsigned int group_idx,
742 const unsigned int **pins,
743 unsigned int *num_pins)
744{
745 struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
746
747 *pins = priv->groups[group_idx].pins;
748 *num_pins = priv->groups[group_idx].npins;
749
750 return 0;
751}
752
753static const struct pinctrl_ops lochnagar_pin_group_ops = {
754 .get_groups_count = lochnagar_get_groups_count,
755 .get_group_name = lochnagar_get_group_name,
756 .get_group_pins = lochnagar_get_group_pins,
757 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
758 .dt_free_map = pinctrl_utils_free_map,
759};
760
761static int lochnagar_get_funcs_count(struct pinctrl_dev *pctldev)
762{
763 struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
764
765 return priv->nfuncs;
766}
767
768static const char *lochnagar_get_func_name(struct pinctrl_dev *pctldev,
769 unsigned int func_idx)
770{
771 struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
772
773 return priv->funcs[func_idx].name;
774}
775
776static int lochnagar_get_func_groups(struct pinctrl_dev *pctldev,
777 unsigned int func_idx,
778 const char * const **groups,
779 unsigned int * const num_groups)
780{
781 struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
782 int func_type;
783
784 func_type = priv->funcs[func_idx].type;
785
786 *groups = priv->func_groups[func_type].groups;
787 *num_groups = priv->func_groups[func_type].ngroups;
788
789 return 0;
790}
791
792static int lochnagar2_get_gpio_chan(struct lochnagar_pin_priv *priv,
793 unsigned int op)
794{
795 struct regmap *regmap = priv->lochnagar->regmap;
796 unsigned int val;
797 int free = -1;
798 int i, ret;
799
800 for (i = 0; i < LN2_NUM_GPIO_CHANNELS; i++) {
801 ret = regmap_read(regmap, LOCHNAGAR2_GPIO_CHANNEL1 + i, &val);
802 if (ret)
803 return ret;
804
805 val &= LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK;
806
807 if (val == op)
808 return i + 1;
809
810 if (free < 0 && !val)
811 free = i;
812 }
813
814 if (free >= 0) {
815 ret = regmap_update_bits(regmap,
816 LOCHNAGAR2_GPIO_CHANNEL1 + free,
817 LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK, op);
818 if (ret)
819 return ret;
820
821 free++;
822
823 dev_dbg(priv->dev, "Set channel %d to 0x%x\n", free, op);
824
825 return free;
826 }
827
828 return -ENOSPC;
829}
830
831static int lochnagar_pin_set_mux(struct lochnagar_pin_priv *priv,
832 const struct lochnagar_pin *pin,
833 unsigned int op)
834{
835 int ret;
836
837 switch (priv->lochnagar->type) {
838 case LOCHNAGAR1:
839 break;
840 default:
841 ret = lochnagar2_get_gpio_chan(priv, op);
842 if (ret < 0) {
843 dev_err(priv->dev, "Failed to get channel for %s: %d\n",
844 pin->name, ret);
845 return ret;
846 }
847
848 op = ret;
849 break;
850 }
851
852 dev_dbg(priv->dev, "Set pin %s to 0x%x\n", pin->name, op);
853
854 ret = regmap_write(priv->lochnagar->regmap, pin->reg, op);
855 if (ret)
856 dev_err(priv->dev, "Failed to set %s mux: %d\n",
857 pin->name, ret);
858
859 return 0;
860}
861
862static int lochnagar_aif_set_mux(struct lochnagar_pin_priv *priv,
863 const struct lochnagar_group *group,
864 unsigned int op)
865{
866 struct regmap *regmap = priv->lochnagar->regmap;
867 const struct lochnagar_aif *aif = group->priv;
868 const struct lochnagar_pin *pin;
869 int i, ret;
870
871 ret = regmap_update_bits(regmap, aif->src_reg, aif->src_mask, op);
872 if (ret) {
873 dev_err(priv->dev, "Failed to set %s source: %d\n",
874 group->name, ret);
875 return ret;
876 }
877
878 ret = regmap_update_bits(regmap, aif->ctrl_reg,
879 aif->ena_mask, aif->ena_mask);
880 if (ret) {
881 dev_err(priv->dev, "Failed to set %s enable: %d\n",
882 group->name, ret);
883 return ret;
884 }
885
886 for (i = 0; i < group->npins; i++) {
887 pin = priv->pins[group->pins[i]].drv_data;
888
889 if (pin->type != LN_PTYPE_MUX)
890 continue;
891
892 dev_dbg(priv->dev, "Set pin %s to AIF\n", pin->name);
893
894 ret = regmap_update_bits(regmap, pin->reg,
895 LOCHNAGAR2_GPIO_SRC_MASK,
896 LN2_OP_AIF);
897 if (ret) {
898 dev_err(priv->dev, "Failed to set %s to AIF: %d\n",
899 pin->name, ret);
900 return ret;
901 }
902 }
903
904 return 0;
905}
906
907static int lochnagar_set_mux(struct pinctrl_dev *pctldev,
908 unsigned int func_idx, unsigned int group_idx)
909{
910 struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
911 const struct lochnagar_func *func = &priv->funcs[func_idx];
912 const struct lochnagar_group *group = &priv->groups[group_idx];
913 const struct lochnagar_pin *pin;
914
915 switch (func->type) {
916 case LN_FTYPE_AIF:
917 dev_dbg(priv->dev, "Set group %s to %s\n",
918 group->name, func->name);
919
920 return lochnagar_aif_set_mux(priv, group, func->op);
921 case LN_FTYPE_PIN:
922 pin = priv->pins[*group->pins].drv_data;
923
924 dev_dbg(priv->dev, "Set pin %s to %s\n", pin->name, func->name);
925
926 return lochnagar_pin_set_mux(priv, pin, func->op);
927 default:
928 return -EINVAL;
929 }
930}
931
932static int lochnagar_gpio_request(struct pinctrl_dev *pctldev,
933 struct pinctrl_gpio_range *range,
934 unsigned int offset)
935{
936 struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
937 struct lochnagar *lochnagar = priv->lochnagar;
938 const struct lochnagar_pin *pin = priv->pins[offset].drv_data;
939 int ret;
940
941 dev_dbg(priv->dev, "Requesting GPIO %s\n", pin->name);
942
943 if (lochnagar->type == LOCHNAGAR1 || pin->type != LN_PTYPE_MUX)
944 return 0;
945
946 ret = lochnagar2_get_gpio_chan(priv, LN2_OP_GPIO);
947 if (ret < 0) {
948 dev_err(priv->dev, "Failed to get low channel: %d\n", ret);
949 return ret;
950 }
951
952 ret = lochnagar2_get_gpio_chan(priv, LN2_OP_GPIO | 0x1);
953 if (ret < 0) {
954 dev_err(priv->dev, "Failed to get high channel: %d\n", ret);
955 return ret;
956 }
957
958 return 0;
959}
960
961static int lochnagar_gpio_set_direction(struct pinctrl_dev *pctldev,
962 struct pinctrl_gpio_range *range,
963 unsigned int offset,
964 bool input)
965{
966 /* The GPIOs only support output */
967 if (input)
968 return -EINVAL;
969
970 return 0;
971}
972
973static const struct pinmux_ops lochnagar_pin_mux_ops = {
974 .get_functions_count = lochnagar_get_funcs_count,
975 .get_function_name = lochnagar_get_func_name,
976 .get_function_groups = lochnagar_get_func_groups,
977 .set_mux = lochnagar_set_mux,
978
979 .gpio_request_enable = lochnagar_gpio_request,
980 .gpio_set_direction = lochnagar_gpio_set_direction,
981
982 .strict = true,
983};
984
985static int lochnagar_aif_set_master(struct lochnagar_pin_priv *priv,
986 unsigned int group_idx, bool master)
987{
988 struct regmap *regmap = priv->lochnagar->regmap;
989 const struct lochnagar_group *group = &priv->groups[group_idx];
990 const struct lochnagar_aif *aif = group->priv;
991 unsigned int val = 0;
992 int ret;
993
994 if (group->type != LN_FTYPE_AIF)
995 return -EINVAL;
996
997 if (!master)
998 val = aif->master_mask;
999
1000 dev_dbg(priv->dev, "Set AIF %s to %s\n",
1001 group->name, master ? "master" : "slave");
1002
1003 ret = regmap_update_bits(regmap, aif->ctrl_reg, aif->master_mask, val);
1004 if (ret) {
1005 dev_err(priv->dev, "Failed to set %s mode: %d\n",
1006 group->name, ret);
1007 return ret;
1008 }
1009
1010 return 0;
1011}
1012
1013static int lochnagar_conf_group_set(struct pinctrl_dev *pctldev,
1014 unsigned int group_idx,
1015 unsigned long *configs,
1016 unsigned int num_configs)
1017{
1018 struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
1019 int i, ret;
1020
1021 for (i = 0; i < num_configs; i++) {
1022 unsigned int param = pinconf_to_config_param(*configs);
1023
1024 switch (param) {
1025 case PIN_CONFIG_OUTPUT_ENABLE:
1026 ret = lochnagar_aif_set_master(priv, group_idx, true);
1027 if (ret)
1028 return ret;
1029 break;
1030 case PIN_CONFIG_INPUT_ENABLE:
1031 ret = lochnagar_aif_set_master(priv, group_idx, false);
1032 if (ret)
1033 return ret;
1034 break;
1035 default:
1036 return -ENOTSUPP;
1037 }
1038
1039 configs++;
1040 }
1041
1042 return 0;
1043}
1044
1045static const struct pinconf_ops lochnagar_pin_conf_ops = {
1046 .pin_config_group_set = lochnagar_conf_group_set,
1047};
1048
1049static const struct pinctrl_desc lochnagar_pin_desc = {
1050 .name = "lochnagar-pinctrl",
1051 .owner = THIS_MODULE,
1052
1053 .pctlops = &lochnagar_pin_group_ops,
1054 .pmxops = &lochnagar_pin_mux_ops,
1055 .confops = &lochnagar_pin_conf_ops,
1056};
1057
1058static void lochnagar_gpio_set(struct gpio_chip *chip,
1059 unsigned int offset, int value)
1060{
1061 struct lochnagar_pin_priv *priv = gpiochip_get_data(chip);
1062 struct lochnagar *lochnagar = priv->lochnagar;
1063 const struct lochnagar_pin *pin = priv->pins[offset].drv_data;
1064 int ret;
1065
1066 value = !!value;
1067
1068 dev_dbg(priv->dev, "Set GPIO %s to %s\n",
1069 pin->name, value ? "high" : "low");
1070
1071 switch (pin->type) {
1072 case LN_PTYPE_MUX:
1073 value |= LN2_OP_GPIO;
1074
1075 ret = lochnagar_pin_set_mux(priv, pin, value);
1076 break;
1077 case LN_PTYPE_GPIO:
1078 if (pin->invert)
1079 value = !value;
1080
1081 ret = regmap_update_bits(lochnagar->regmap, pin->reg,
1082 BIT(pin->shift), value << pin->shift);
1083 break;
1084 default:
1085 ret = -EINVAL;
1086 break;
1087 }
1088
1089 if (ret < 0)
1090 dev_err(chip->parent, "Failed to set %s value: %d\n",
1091 pin->name, ret);
1092}
1093
1094static int lochnagar_gpio_direction_out(struct gpio_chip *chip,
1095 unsigned int offset, int value)
1096{
1097 lochnagar_gpio_set(chip, offset, value);
1098
1099 return pinctrl_gpio_direction_output(chip->base + offset);
1100}
1101
1102static int lochnagar_fill_func_groups(struct lochnagar_pin_priv *priv)
1103{
1104 struct lochnagar_func_groups *funcs;
1105 int i;
1106
1107 for (i = 0; i < priv->ngroups; i++)
1108 priv->func_groups[priv->groups[i].type].ngroups++;
1109
1110 for (i = 0; i < LN_FTYPE_COUNT; i++) {
1111 funcs = &priv->func_groups[i];
1112
1113 if (!funcs->ngroups)
1114 continue;
1115
1116 funcs->groups = devm_kcalloc(priv->dev, funcs->ngroups,
1117 sizeof(*funcs->groups),
1118 GFP_KERNEL);
1119 if (!funcs->groups)
1120 return -ENOMEM;
1121
1122 funcs->ngroups = 0;
1123 }
1124
1125 for (i = 0; i < priv->ngroups; i++) {
1126 funcs = &priv->func_groups[priv->groups[i].type];
1127
1128 funcs->groups[funcs->ngroups++] = priv->groups[i].name;
1129 }
1130
1131 return 0;
1132}
1133
1134static int lochnagar_pin_probe(struct platform_device *pdev)
1135{
1136 struct lochnagar *lochnagar = dev_get_drvdata(pdev->dev.parent);
1137 struct lochnagar_pin_priv *priv;
1138 struct pinctrl_desc *desc;
1139 struct pinctrl_dev *pctl;
1140 struct device *dev = &pdev->dev;
1141 int ret;
1142
1143 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1144 if (!priv)
1145 return -ENOMEM;
1146
1147 priv->dev = dev;
1148 priv->lochnagar = lochnagar;
1149
1150 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
1151 if (!desc)
1152 return -ENOMEM;
1153
1154 *desc = lochnagar_pin_desc;
1155
1156 priv->gpio_chip.label = dev_name(dev);
1157 priv->gpio_chip.request = gpiochip_generic_request;
1158 priv->gpio_chip.free = gpiochip_generic_free;
1159 priv->gpio_chip.direction_output = lochnagar_gpio_direction_out;
1160 priv->gpio_chip.set = lochnagar_gpio_set;
1161 priv->gpio_chip.can_sleep = true;
1162 priv->gpio_chip.parent = dev;
1163 priv->gpio_chip.base = -1;
1164#ifdef CONFIG_OF_GPIO
1165 priv->gpio_chip.of_node = dev->of_node;
1166#endif
1167
1168 switch (lochnagar->type) {
1169 case LOCHNAGAR1:
1170 priv->funcs = lochnagar1_funcs;
1171 priv->nfuncs = ARRAY_SIZE(lochnagar1_funcs);
1172 priv->pins = lochnagar1_pins;
1173 priv->npins = ARRAY_SIZE(lochnagar1_pins);
1174 priv->groups = lochnagar1_groups;
1175 priv->ngroups = ARRAY_SIZE(lochnagar1_groups);
1176
1177 priv->gpio_chip.ngpio = LOCHNAGAR1_PIN_NUM_GPIOS;
1178 break;
1179 case LOCHNAGAR2:
1180 priv->funcs = lochnagar2_funcs;
1181 priv->nfuncs = ARRAY_SIZE(lochnagar2_funcs);
1182 priv->pins = lochnagar2_pins;
1183 priv->npins = ARRAY_SIZE(lochnagar2_pins);
1184 priv->groups = lochnagar2_groups;
1185 priv->ngroups = ARRAY_SIZE(lochnagar2_groups);
1186
1187 priv->gpio_chip.ngpio = LOCHNAGAR2_PIN_NUM_GPIOS;
1188 break;
1189 default:
1190 dev_err(dev, "Unknown Lochnagar type: %d\n", lochnagar->type);
1191 return -EINVAL;
1192 }
1193
1194 ret = lochnagar_fill_func_groups(priv);
1195 if (ret < 0)
1196 return ret;
1197
1198 desc->pins = priv->pins;
1199 desc->npins = priv->npins;
1200
1201 pctl = devm_pinctrl_register(dev, desc, priv);
1202 if (IS_ERR(pctl)) {
1203 ret = PTR_ERR(pctl);
1204 dev_err(priv->dev, "Failed to register pinctrl: %d\n", ret);
1205 return ret;
1206 }
1207
1208 ret = devm_gpiochip_add_data(dev, &priv->gpio_chip, priv);
1209 if (ret < 0) {
1210 dev_err(&pdev->dev, "Failed to register gpiochip: %d\n", ret);
1211 return ret;
1212 }
1213
1214 return 0;
1215}
1216
1217static const struct of_device_id lochnagar_of_match[] = {
1218 { .compatible = "cirrus,lochnagar-pinctrl" },
1219 {}
1220};
1221MODULE_DEVICE_TABLE(of, lochnagar_of_match);
1222
1223static struct platform_driver lochnagar_pin_driver = {
1224 .driver = {
1225 .name = "lochnagar-pinctrl",
1226 .of_match_table = of_match_ptr(lochnagar_of_match),
1227 },
1228
1229 .probe = lochnagar_pin_probe,
1230};
1231module_platform_driver(lochnagar_pin_driver);
1232
1233MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>");
1234MODULE_DESCRIPTION("Pinctrl driver for Cirrus Logic Lochnagar Board");
1235MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 188001beb298..83ff9532bae6 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -449,7 +449,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
449 } 449 }
450 } else { 450 } else {
451 pin_reg = &ipctl->pin_regs[pin_id]; 451 pin_reg = &ipctl->pin_regs[pin_id];
452 if (!pin_reg || pin_reg->conf_reg == -1) { 452 if (pin_reg->conf_reg == -1) {
453 seq_puts(s, "N/A"); 453 seq_puts(s, "N/A");
454 return; 454 return;
455 } 455 }
@@ -785,7 +785,6 @@ int imx_pinctrl_probe(struct platform_device *pdev,
785 struct pinctrl_desc *imx_pinctrl_desc; 785 struct pinctrl_desc *imx_pinctrl_desc;
786 struct device_node *np; 786 struct device_node *np;
787 struct imx_pinctrl *ipctl; 787 struct imx_pinctrl *ipctl;
788 struct resource *res;
789 struct regmap *gpr; 788 struct regmap *gpr;
790 int ret, i; 789 int ret, i;
791 790
@@ -817,8 +816,7 @@ int imx_pinctrl_probe(struct platform_device *pdev,
817 ipctl->pin_regs[i].conf_reg = -1; 816 ipctl->pin_regs[i].conf_reg = -1;
818 } 817 }
819 818
820 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 819 ipctl->base = devm_platform_ioremap_resource(pdev, 0);
821 ipctl->base = devm_ioremap_resource(&pdev->dev, res);
822 if (IS_ERR(ipctl->base)) 820 if (IS_ERR(ipctl->base))
823 return PTR_ERR(ipctl->base); 821 return PTR_ERR(ipctl->base);
824 822
@@ -887,3 +885,22 @@ free:
887 885
888 return ret; 886 return ret;
889} 887}
888
889static int __maybe_unused imx_pinctrl_suspend(struct device *dev)
890{
891 struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
892
893 return pinctrl_force_sleep(ipctl->pctl);
894}
895
896static int __maybe_unused imx_pinctrl_resume(struct device *dev)
897{
898 struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
899
900 return pinctrl_force_default(ipctl->pctl);
901}
902
903const struct dev_pm_ops imx_pinctrl_pm_ops = {
904 SET_LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend,
905 imx_pinctrl_resume)
906};
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
index 98a4889af4ef..333d32b947b1 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -17,6 +17,7 @@
17struct platform_device; 17struct platform_device;
18 18
19extern struct pinmux_ops imx_pmx_ops; 19extern struct pinmux_ops imx_pmx_ops;
20extern const struct dev_pm_ops imx_pinctrl_pm_ops;
20 21
21/** 22/**
22 * struct imx_pin_mmio - MMIO pin configurations 23 * struct imx_pin_mmio - MMIO pin configurations
diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mq.c b/drivers/pinctrl/freescale/pinctrl-imx8mq.c
index 8d39af541d5f..50aa1c00c4b2 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx8mq.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx8mq.c
@@ -339,6 +339,7 @@ static struct platform_driver imx8mq_pinctrl_driver = {
339 .driver = { 339 .driver = {
340 .name = "imx8mq-pinctrl", 340 .name = "imx8mq-pinctrl",
341 .of_match_table = of_match_ptr(imx8mq_pinctrl_of_match), 341 .of_match_table = of_match_ptr(imx8mq_pinctrl_of_match),
342 .pm = &imx_pinctrl_pm_ops,
342 .suppress_bind_attrs = true, 343 .suppress_bind_attrs = true,
343 }, 344 },
344 .probe = imx8mq_pinctrl_probe, 345 .probe = imx8mq_pinctrl_probe,
diff --git a/drivers/pinctrl/freescale/pinctrl-scu.c b/drivers/pinctrl/freescale/pinctrl-scu.c
index 83e69c0f39e6..73bf1d9f9cc6 100644
--- a/drivers/pinctrl/freescale/pinctrl-scu.c
+++ b/drivers/pinctrl/freescale/pinctrl-scu.c
@@ -35,7 +35,7 @@ struct imx_sc_msg_resp_pad_get {
35 u32 val; 35 u32 val;
36} __packed; 36} __packed;
37 37
38struct imx_sc_ipc *pinctrl_ipc_handle; 38static struct imx_sc_ipc *pinctrl_ipc_handle;
39 39
40int imx_pinctrl_sc_ipc_init(struct platform_device *pdev) 40int imx_pinctrl_sc_ipc_init(struct platform_device *pdev)
41{ 41{
diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c
index 241384ead4ed..18d9ad504194 100644
--- a/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@ -1710,6 +1710,8 @@ static int byt_gpio_probe(struct byt_gpio *vg)
1710#ifdef CONFIG_PM_SLEEP 1710#ifdef CONFIG_PM_SLEEP
1711 vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio, 1711 vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,
1712 sizeof(*vg->saved_context), GFP_KERNEL); 1712 sizeof(*vg->saved_context), GFP_KERNEL);
1713 if (!vg->saved_context)
1714 return -ENOMEM;
1713#endif 1715#endif
1714 ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg); 1716 ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg);
1715 if (ret) { 1717 if (ret) {
diff --git a/drivers/pinctrl/intel/pinctrl-cedarfork.c b/drivers/pinctrl/intel/pinctrl-cedarfork.c
index b7d632f1dbf6..aa6f9040d3d8 100644
--- a/drivers/pinctrl/intel/pinctrl-cedarfork.c
+++ b/drivers/pinctrl/intel/pinctrl-cedarfork.c
@@ -91,13 +91,13 @@ static const struct pinctrl_pin_desc cdf_pins[] = {
91 PINCTRL_PIN(43, "MEMTRIP_N"), 91 PINCTRL_PIN(43, "MEMTRIP_N"),
92 PINCTRL_PIN(44, "UART0_RXD"), 92 PINCTRL_PIN(44, "UART0_RXD"),
93 PINCTRL_PIN(45, "UART0_TXD"), 93 PINCTRL_PIN(45, "UART0_TXD"),
94 PINCTRL_PIN(46, "UART1_RXD"), 94 PINCTRL_PIN(46, "GBE_UART_RXD"),
95 PINCTRL_PIN(47, "UART1_TXD"), 95 PINCTRL_PIN(47, "GBE_UART_TXD"),
96 /* WEST01 */ 96 /* WEST01 */
97 PINCTRL_PIN(48, "GBE_GPIO13"), 97 PINCTRL_PIN(48, "GBE_GPIO13"),
98 PINCTRL_PIN(49, "AUX_PWR"), 98 PINCTRL_PIN(49, "AUX_PWR"),
99 PINCTRL_PIN(50, "CPU_GP_2"), 99 PINCTRL_PIN(50, "UART0_RTS"),
100 PINCTRL_PIN(51, "CPU_GP_3"), 100 PINCTRL_PIN(51, "UART0_CTS"),
101 PINCTRL_PIN(52, "FAN_PWM_0"), 101 PINCTRL_PIN(52, "FAN_PWM_0"),
102 PINCTRL_PIN(53, "FAN_PWM_1"), 102 PINCTRL_PIN(53, "FAN_PWM_1"),
103 PINCTRL_PIN(54, "FAN_PWM_2"), 103 PINCTRL_PIN(54, "FAN_PWM_2"),
@@ -201,8 +201,8 @@ static const struct pinctrl_pin_desc cdf_pins[] = {
201 /* WESTF */ 201 /* WESTF */
202 PINCTRL_PIN(145, "NAC_RMII_CLK"), 202 PINCTRL_PIN(145, "NAC_RMII_CLK"),
203 PINCTRL_PIN(146, "NAC_RGMII_CLK"), 203 PINCTRL_PIN(146, "NAC_RGMII_CLK"),
204 PINCTRL_PIN(147, "NAC_SPARE0"), 204 PINCTRL_PIN(147, "NAC_GBE_SMB_CLK_TX_N2S"),
205 PINCTRL_PIN(148, "NAC_SPARE1"), 205 PINCTRL_PIN(148, "NAC_GBE_SMB_DATA_TX_N2S"),
206 PINCTRL_PIN(149, "NAC_SPARE2"), 206 PINCTRL_PIN(149, "NAC_SPARE2"),
207 PINCTRL_PIN(150, "NAC_INIT_SX_WAKE_N"), 207 PINCTRL_PIN(150, "NAC_INIT_SX_WAKE_N"),
208 PINCTRL_PIN(151, "NAC_GBE_GPIO0_S2N"), 208 PINCTRL_PIN(151, "NAC_GBE_GPIO0_S2N"),
@@ -219,8 +219,8 @@ static const struct pinctrl_pin_desc cdf_pins[] = {
219 PINCTRL_PIN(162, "NAC_NCSI_TXD1"), 219 PINCTRL_PIN(162, "NAC_NCSI_TXD1"),
220 PINCTRL_PIN(163, "NAC_NCSI_ARB_OUT"), 220 PINCTRL_PIN(163, "NAC_NCSI_ARB_OUT"),
221 PINCTRL_PIN(164, "NAC_NCSI_OE_N"), 221 PINCTRL_PIN(164, "NAC_NCSI_OE_N"),
222 PINCTRL_PIN(165, "NAC_GBE_SMB_CLK"), 222 PINCTRL_PIN(165, "NAC_GBE_SMB_CLK_RX_S2N"),
223 PINCTRL_PIN(166, "NAC_GBE_SMB_DATA"), 223 PINCTRL_PIN(166, "NAC_GBE_SMB_DATA_RX_S2N"),
224 PINCTRL_PIN(167, "NAC_GBE_SMB_ALRT_N"), 224 PINCTRL_PIN(167, "NAC_GBE_SMB_ALRT_N"),
225 /* EAST2 */ 225 /* EAST2 */
226 PINCTRL_PIN(168, "USB_OC0_N"), 226 PINCTRL_PIN(168, "USB_OC0_N"),
@@ -232,7 +232,7 @@ static const struct pinctrl_pin_desc cdf_pins[] = {
232 PINCTRL_PIN(174, "GBE_GPIO5"), 232 PINCTRL_PIN(174, "GBE_GPIO5"),
233 PINCTRL_PIN(175, "GBE_GPIO6"), 233 PINCTRL_PIN(175, "GBE_GPIO6"),
234 PINCTRL_PIN(176, "GBE_GPIO7"), 234 PINCTRL_PIN(176, "GBE_GPIO7"),
235 PINCTRL_PIN(177, "GBE_GPIO8"), 235 PINCTRL_PIN(177, "SPI_TPM_CS_N"),
236 PINCTRL_PIN(178, "GBE_GPIO9"), 236 PINCTRL_PIN(178, "GBE_GPIO9"),
237 PINCTRL_PIN(179, "GBE_GPIO10"), 237 PINCTRL_PIN(179, "GBE_GPIO10"),
238 PINCTRL_PIN(180, "GBE_GPIO11"), 238 PINCTRL_PIN(180, "GBE_GPIO11"),
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 3b1818184207..d7acbb79cdf7 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -81,6 +81,7 @@ struct intel_pad_context {
81 81
82struct intel_community_context { 82struct intel_community_context {
83 u32 *intmask; 83 u32 *intmask;
84 u32 *hostown;
84}; 85};
85 86
86struct intel_pinctrl_context { 87struct intel_pinctrl_context {
@@ -1284,7 +1285,7 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1284 1285
1285 for (i = 0; i < pctrl->ncommunities; i++) { 1286 for (i = 0; i < pctrl->ncommunities; i++) {
1286 struct intel_community *community = &pctrl->communities[i]; 1287 struct intel_community *community = &pctrl->communities[i];
1287 u32 *intmask; 1288 u32 *intmask, *hostown;
1288 1289
1289 intmask = devm_kcalloc(pctrl->dev, community->ngpps, 1290 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1290 sizeof(*intmask), GFP_KERNEL); 1291 sizeof(*intmask), GFP_KERNEL);
@@ -1292,6 +1293,13 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1292 return -ENOMEM; 1293 return -ENOMEM;
1293 1294
1294 communities[i].intmask = intmask; 1295 communities[i].intmask = intmask;
1296
1297 hostown = devm_kcalloc(pctrl->dev, community->ngpps,
1298 sizeof(*hostown), GFP_KERNEL);
1299 if (!hostown)
1300 return -ENOMEM;
1301
1302 communities[i].hostown = hostown;
1295 } 1303 }
1296 1304
1297 pctrl->context.pads = pads; 1305 pctrl->context.pads = pads;
@@ -1466,7 +1474,7 @@ static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int
1466 return false; 1474 return false;
1467} 1475}
1468 1476
1469int intel_pinctrl_suspend(struct device *dev) 1477int intel_pinctrl_suspend_noirq(struct device *dev)
1470{ 1478{
1471 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1479 struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1472 struct intel_community_context *communities; 1480 struct intel_community_context *communities;
@@ -1501,11 +1509,15 @@ int intel_pinctrl_suspend(struct device *dev)
1501 base = community->regs + community->ie_offset; 1509 base = community->regs + community->ie_offset;
1502 for (gpp = 0; gpp < community->ngpps; gpp++) 1510 for (gpp = 0; gpp < community->ngpps; gpp++)
1503 communities[i].intmask[gpp] = readl(base + gpp * 4); 1511 communities[i].intmask[gpp] = readl(base + gpp * 4);
1512
1513 base = community->regs + community->hostown_offset;
1514 for (gpp = 0; gpp < community->ngpps; gpp++)
1515 communities[i].hostown[gpp] = readl(base + gpp * 4);
1504 } 1516 }
1505 1517
1506 return 0; 1518 return 0;
1507} 1519}
1508EXPORT_SYMBOL_GPL(intel_pinctrl_suspend); 1520EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
1509 1521
1510static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) 1522static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1511{ 1523{
@@ -1527,7 +1539,32 @@ static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1527 } 1539 }
1528} 1540}
1529 1541
1530int intel_pinctrl_resume(struct device *dev) 1542static u32
1543intel_gpio_is_requested(struct gpio_chip *chip, int base, unsigned int size)
1544{
1545 u32 requested = 0;
1546 unsigned int i;
1547
1548 for (i = 0; i < size; i++)
1549 if (gpiochip_is_requested(chip, base + i))
1550 requested |= BIT(i);
1551
1552 return requested;
1553}
1554
1555static u32
1556intel_gpio_update_pad_mode(void __iomem *hostown, u32 mask, u32 value)
1557{
1558 u32 curr, updated;
1559
1560 curr = readl(hostown);
1561 updated = (curr & ~mask) | (value & mask);
1562 writel(updated, hostown);
1563
1564 return curr;
1565}
1566
1567int intel_pinctrl_resume_noirq(struct device *dev)
1531{ 1568{
1532 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1569 struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1533 const struct intel_community_context *communities; 1570 const struct intel_community_context *communities;
@@ -1585,11 +1622,30 @@ int intel_pinctrl_resume(struct device *dev)
1585 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp, 1622 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1586 readl(base + gpp * 4)); 1623 readl(base + gpp * 4));
1587 } 1624 }
1625
1626 base = community->regs + community->hostown_offset;
1627 for (gpp = 0; gpp < community->ngpps; gpp++) {
1628 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1629 u32 requested = 0, value = 0;
1630 u32 saved = communities[i].hostown[gpp];
1631
1632 if (padgrp->gpio_base < 0)
1633 continue;
1634
1635 requested = intel_gpio_is_requested(&pctrl->chip,
1636 padgrp->gpio_base, padgrp->size);
1637 value = intel_gpio_update_pad_mode(base + gpp * 4,
1638 requested, saved);
1639 if ((value ^ saved) & requested) {
1640 dev_warn(dev, "restore hostown %d/%u %#8x->%#8x\n",
1641 i, gpp, value, saved);
1642 }
1643 }
1588 } 1644 }
1589 1645
1590 return 0; 1646 return 0;
1591} 1647}
1592EXPORT_SYMBOL_GPL(intel_pinctrl_resume); 1648EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq);
1593#endif 1649#endif
1594 1650
1595MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); 1651MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h
index b8a07d37d18f..a8e958f1dcf5 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.h
+++ b/drivers/pinctrl/intel/pinctrl-intel.h
@@ -177,13 +177,14 @@ int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
177int intel_pinctrl_probe_by_uid(struct platform_device *pdev); 177int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
178 178
179#ifdef CONFIG_PM_SLEEP 179#ifdef CONFIG_PM_SLEEP
180int intel_pinctrl_suspend(struct device *dev); 180int intel_pinctrl_suspend_noirq(struct device *dev);
181int intel_pinctrl_resume(struct device *dev); 181int intel_pinctrl_resume_noirq(struct device *dev);
182#endif 182#endif
183 183
184#define INTEL_PINCTRL_PM_OPS(_name) \ 184#define INTEL_PINCTRL_PM_OPS(_name) \
185const struct dev_pm_ops _name = { \ 185const struct dev_pm_ops _name = { \
186 SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend, intel_pinctrl_resume) \ 186 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq, \
187 intel_pinctrl_resume_noirq) \
187} 188}
188 189
189#endif /* PINCTRL_INTEL_H */ 190#endif /* PINCTRL_INTEL_H */
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index a005cbccb4f7..26ed5dca1460 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -113,6 +113,13 @@ config PINCTRL_MT8183
113 default ARM64 && ARCH_MEDIATEK 113 default ARM64 && ARCH_MEDIATEK
114 select PINCTRL_MTK_PARIS 114 select PINCTRL_MTK_PARIS
115 115
116config PINCTRL_MT8516
117 bool "Mediatek MT8516 pin control"
118 depends on OF
119 depends on ARM64 || COMPILE_TEST
120 default ARM64 && ARCH_MEDIATEK
121 select PINCTRL_MTK
122
116# For PMIC 123# For PMIC
117config PINCTRL_MT6397 124config PINCTRL_MT6397
118 bool "Mediatek MT6397 pin control" 125 bool "Mediatek MT6397 pin control"
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index 4b4e2eaf6f2d..a74325abd877 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -17,4 +17,5 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
17obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o 17obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
18obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o 18obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
19obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o 19obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
20obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
20obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o 21obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8183.c b/drivers/pinctrl/mediatek/pinctrl-mt8183.c
index 6262fd3678ea..2c7409ed16fa 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8183.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8183.c
@@ -472,6 +472,51 @@ static const struct mtk_pin_field_calc mt8183_pin_r1_range[] = {
472 PIN_FIELD_BASE(133, 133, 8, 0x0D0, 0x10, 13, 1), 472 PIN_FIELD_BASE(133, 133, 8, 0x0D0, 0x10, 13, 1),
473}; 473};
474 474
475static const struct mtk_pin_field_calc mt8183_pin_e1e0en_range[] = {
476 PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 20, 1),
477 PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 15, 1),
478 PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 12, 1),
479 PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 7, 1),
480 PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 12, 1),
481 PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 9, 1),
482 PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 19, 1),
483 PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 22, 1),
484 PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 24, 1),
485 PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 14, 1),
486 PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 27, 1),
487 PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 17, 1),
488};
489
490static const struct mtk_pin_field_calc mt8183_pin_e0_range[] = {
491 PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 21, 1),
492 PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 16, 1),
493 PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 13, 1),
494 PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 8, 1),
495 PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 13, 1),
496 PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 10, 1),
497 PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 20, 1),
498 PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 23, 1),
499 PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 25, 1),
500 PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 15, 1),
501 PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 28, 1),
502 PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 18, 1),
503};
504
505static const struct mtk_pin_field_calc mt8183_pin_e1_range[] = {
506 PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 22, 1),
507 PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 17, 1),
508 PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 14, 1),
509 PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 9, 1),
510 PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 14, 1),
511 PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 11, 1),
512 PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 21, 1),
513 PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 24, 1),
514 PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 26, 1),
515 PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 16, 1),
516 PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 29, 1),
517 PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 19, 1),
518};
519
475static const struct mtk_pin_reg_calc mt8183_reg_cals[PINCTRL_PIN_REG_MAX] = { 520static const struct mtk_pin_reg_calc mt8183_reg_cals[PINCTRL_PIN_REG_MAX] = {
476 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8183_pin_mode_range), 521 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8183_pin_mode_range),
477 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8183_pin_dir_range), 522 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8183_pin_dir_range),
@@ -485,6 +530,9 @@ static const struct mtk_pin_reg_calc mt8183_reg_cals[PINCTRL_PIN_REG_MAX] = {
485 [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8183_pin_pupd_range), 530 [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8183_pin_pupd_range),
486 [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8183_pin_r0_range), 531 [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8183_pin_r0_range),
487 [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8183_pin_r1_range), 532 [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8183_pin_r1_range),
533 [PINCTRL_PIN_REG_DRV_EN] = MTK_RANGE(mt8183_pin_e1e0en_range),
534 [PINCTRL_PIN_REG_DRV_E0] = MTK_RANGE(mt8183_pin_e0_range),
535 [PINCTRL_PIN_REG_DRV_E1] = MTK_RANGE(mt8183_pin_e1_range),
488}; 536};
489 537
490static const char * const mt8183_pinctrl_register_base_names[] = { 538static const char * const mt8183_pinctrl_register_base_names[] = {
@@ -517,6 +565,8 @@ static const struct mtk_pin_soc mt8183_data = {
517 .drive_get = mtk_pinconf_drive_get_rev1, 565 .drive_get = mtk_pinconf_drive_get_rev1,
518 .adv_pull_get = mtk_pinconf_adv_pull_get, 566 .adv_pull_get = mtk_pinconf_adv_pull_get,
519 .adv_pull_set = mtk_pinconf_adv_pull_set, 567 .adv_pull_set = mtk_pinconf_adv_pull_set,
568 .adv_drive_get = mtk_pinconf_adv_drive_get,
569 .adv_drive_set = mtk_pinconf_adv_drive_set,
520}; 570};
521 571
522static const struct of_device_id mt8183_pinctrl_of_match[] = { 572static const struct of_device_id mt8183_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
new file mode 100644
index 000000000000..b375426aa61e
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
@@ -0,0 +1,362 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Min.Guo <min.guo@mediatek.com>
5 */
6
7#include <dt-bindings/pinctrl/mt65xx.h>
8#include <linux/of.h>
9#include <linux/of_device.h>
10#include <linux/module.h>
11#include <linux/pinctrl/pinctrl.h>
12#include <linux/platform_device.h>
13#include <linux/regmap.h>
14
15#include "pinctrl-mtk-common.h"
16#include "pinctrl-mtk-mt8516.h"
17
18static const struct mtk_drv_group_desc mt8516_drv_grp[] = {
19 /* 0E4E8SR 4/8/12/16 */
20 MTK_DRV_GRP(4, 16, 1, 2, 4),
21 /* 0E2E4SR 2/4/6/8 */
22 MTK_DRV_GRP(2, 8, 1, 2, 2),
23 /* E8E4E2 2/4/6/8/10/12/14/16 */
24 MTK_DRV_GRP(2, 16, 0, 2, 2)
25};
26
27static const struct mtk_pin_drv_grp mt8516_pin_drv[] = {
28 MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
29 MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
30 MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
31 MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
32 MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
33
34 MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
35 MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
36 MTK_PIN_DRV_GRP(7, 0xd00, 4, 0),
37 MTK_PIN_DRV_GRP(8, 0xd00, 4, 0),
38 MTK_PIN_DRV_GRP(9, 0xd00, 4, 0),
39 MTK_PIN_DRV_GRP(10, 0xd00, 4, 0),
40
41 MTK_PIN_DRV_GRP(11, 0xd00, 8, 0),
42 MTK_PIN_DRV_GRP(12, 0xd00, 8, 0),
43 MTK_PIN_DRV_GRP(13, 0xd00, 8, 0),
44
45 MTK_PIN_DRV_GRP(14, 0xd00, 12, 2),
46 MTK_PIN_DRV_GRP(15, 0xd00, 12, 2),
47 MTK_PIN_DRV_GRP(16, 0xd00, 12, 2),
48 MTK_PIN_DRV_GRP(17, 0xd00, 12, 2),
49
50 MTK_PIN_DRV_GRP(18, 0xd10, 0, 0),
51 MTK_PIN_DRV_GRP(19, 0xd10, 0, 0),
52 MTK_PIN_DRV_GRP(20, 0xd10, 0, 0),
53
54 MTK_PIN_DRV_GRP(21, 0xd00, 12, 2),
55 MTK_PIN_DRV_GRP(22, 0xd00, 12, 2),
56 MTK_PIN_DRV_GRP(23, 0xd00, 12, 2),
57
58 MTK_PIN_DRV_GRP(24, 0xd00, 8, 0),
59 MTK_PIN_DRV_GRP(25, 0xd00, 8, 0),
60
61 MTK_PIN_DRV_GRP(26, 0xd10, 4, 1),
62 MTK_PIN_DRV_GRP(27, 0xd10, 4, 1),
63 MTK_PIN_DRV_GRP(28, 0xd10, 4, 1),
64 MTK_PIN_DRV_GRP(29, 0xd10, 4, 1),
65 MTK_PIN_DRV_GRP(30, 0xd10, 4, 1),
66
67 MTK_PIN_DRV_GRP(31, 0xd10, 8, 1),
68 MTK_PIN_DRV_GRP(32, 0xd10, 8, 1),
69 MTK_PIN_DRV_GRP(33, 0xd10, 8, 1),
70
71 MTK_PIN_DRV_GRP(34, 0xd10, 12, 0),
72 MTK_PIN_DRV_GRP(35, 0xd10, 12, 0),
73
74 MTK_PIN_DRV_GRP(36, 0xd20, 0, 0),
75 MTK_PIN_DRV_GRP(37, 0xd20, 0, 0),
76 MTK_PIN_DRV_GRP(38, 0xd20, 0, 0),
77 MTK_PIN_DRV_GRP(39, 0xd20, 0, 0),
78
79 MTK_PIN_DRV_GRP(40, 0xd20, 4, 1),
80
81 MTK_PIN_DRV_GRP(41, 0xd20, 8, 1),
82 MTK_PIN_DRV_GRP(42, 0xd20, 8, 1),
83 MTK_PIN_DRV_GRP(43, 0xd20, 8, 1),
84
85 MTK_PIN_DRV_GRP(44, 0xd20, 12, 1),
86 MTK_PIN_DRV_GRP(45, 0xd20, 12, 1),
87 MTK_PIN_DRV_GRP(46, 0xd20, 12, 1),
88 MTK_PIN_DRV_GRP(47, 0xd20, 12, 1),
89
90 MTK_PIN_DRV_GRP(48, 0xd30, 0, 1),
91 MTK_PIN_DRV_GRP(49, 0xd30, 0, 1),
92 MTK_PIN_DRV_GRP(50, 0xd30, 0, 1),
93 MTK_PIN_DRV_GRP(51, 0xd30, 0, 1),
94
95 MTK_PIN_DRV_GRP(54, 0xd30, 8, 1),
96
97 MTK_PIN_DRV_GRP(55, 0xd30, 12, 1),
98 MTK_PIN_DRV_GRP(56, 0xd30, 12, 1),
99 MTK_PIN_DRV_GRP(57, 0xd30, 12, 1),
100
101 MTK_PIN_DRV_GRP(62, 0xd40, 8, 1),
102 MTK_PIN_DRV_GRP(63, 0xd40, 8, 1),
103 MTK_PIN_DRV_GRP(64, 0xd40, 8, 1),
104 MTK_PIN_DRV_GRP(65, 0xd40, 8, 1),
105 MTK_PIN_DRV_GRP(66, 0xd40, 8, 1),
106 MTK_PIN_DRV_GRP(67, 0xd40, 8, 1),
107
108 MTK_PIN_DRV_GRP(68, 0xd40, 12, 2),
109
110 MTK_PIN_DRV_GRP(69, 0xd50, 0, 2),
111
112 MTK_PIN_DRV_GRP(70, 0xd50, 4, 2),
113 MTK_PIN_DRV_GRP(71, 0xd50, 4, 2),
114 MTK_PIN_DRV_GRP(72, 0xd50, 4, 2),
115 MTK_PIN_DRV_GRP(73, 0xd50, 4, 2),
116
117 MTK_PIN_DRV_GRP(100, 0xd50, 8, 1),
118 MTK_PIN_DRV_GRP(101, 0xd50, 8, 1),
119 MTK_PIN_DRV_GRP(102, 0xd50, 8, 1),
120 MTK_PIN_DRV_GRP(103, 0xd50, 8, 1),
121
122 MTK_PIN_DRV_GRP(104, 0xd50, 12, 2),
123
124 MTK_PIN_DRV_GRP(105, 0xd60, 0, 2),
125
126 MTK_PIN_DRV_GRP(106, 0xd60, 4, 2),
127 MTK_PIN_DRV_GRP(107, 0xd60, 4, 2),
128 MTK_PIN_DRV_GRP(108, 0xd60, 4, 2),
129 MTK_PIN_DRV_GRP(109, 0xd60, 4, 2),
130
131 MTK_PIN_DRV_GRP(110, 0xd70, 0, 2),
132 MTK_PIN_DRV_GRP(111, 0xd70, 0, 2),
133 MTK_PIN_DRV_GRP(112, 0xd70, 0, 2),
134 MTK_PIN_DRV_GRP(113, 0xd70, 0, 2),
135
136 MTK_PIN_DRV_GRP(114, 0xd70, 4, 2),
137
138 MTK_PIN_DRV_GRP(115, 0xd60, 12, 2),
139
140 MTK_PIN_DRV_GRP(116, 0xd60, 8, 2),
141
142 MTK_PIN_DRV_GRP(117, 0xd70, 0, 2),
143 MTK_PIN_DRV_GRP(118, 0xd70, 0, 2),
144 MTK_PIN_DRV_GRP(119, 0xd70, 0, 2),
145 MTK_PIN_DRV_GRP(120, 0xd70, 0, 2),
146};
147
148static const struct mtk_pin_spec_pupd_set_samereg mt8516_spec_pupd[] = {
149 MTK_PIN_PUPD_SPEC_SR(14, 0xe50, 14, 13, 12),
150 MTK_PIN_PUPD_SPEC_SR(15, 0xe60, 2, 1, 0),
151 MTK_PIN_PUPD_SPEC_SR(16, 0xe60, 6, 5, 4),
152 MTK_PIN_PUPD_SPEC_SR(17, 0xe60, 10, 9, 8),
153
154 MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 14, 13, 12),
155 MTK_PIN_PUPD_SPEC_SR(22, 0xe70, 2, 1, 0),
156 MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 6, 5, 4),
157
158 MTK_PIN_PUPD_SPEC_SR(40, 0xe80, 2, 1, 0),
159 MTK_PIN_PUPD_SPEC_SR(41, 0xe80, 6, 5, 4),
160 MTK_PIN_PUPD_SPEC_SR(42, 0xe90, 2, 1, 0),
161 MTK_PIN_PUPD_SPEC_SR(43, 0xe90, 6, 5, 4),
162
163 MTK_PIN_PUPD_SPEC_SR(68, 0xe50, 10, 9, 8),
164 MTK_PIN_PUPD_SPEC_SR(69, 0xe50, 6, 5, 4),
165 MTK_PIN_PUPD_SPEC_SR(70, 0xe40, 6, 5, 4),
166 MTK_PIN_PUPD_SPEC_SR(71, 0xe40, 10, 9, 8),
167 MTK_PIN_PUPD_SPEC_SR(72, 0xe40, 14, 13, 12),
168 MTK_PIN_PUPD_SPEC_SR(73, 0xe50, 2, 1, 0),
169
170 MTK_PIN_PUPD_SPEC_SR(104, 0xe40, 2, 1, 0),
171 MTK_PIN_PUPD_SPEC_SR(105, 0xe30, 14, 13, 12),
172 MTK_PIN_PUPD_SPEC_SR(106, 0xe20, 14, 13, 12),
173 MTK_PIN_PUPD_SPEC_SR(107, 0xe30, 2, 1, 0),
174 MTK_PIN_PUPD_SPEC_SR(108, 0xe30, 6, 5, 4),
175 MTK_PIN_PUPD_SPEC_SR(109, 0xe30, 10, 9, 8),
176 MTK_PIN_PUPD_SPEC_SR(110, 0xe10, 14, 13, 12),
177 MTK_PIN_PUPD_SPEC_SR(111, 0xe10, 10, 9, 8),
178 MTK_PIN_PUPD_SPEC_SR(112, 0xe10, 6, 5, 4),
179 MTK_PIN_PUPD_SPEC_SR(113, 0xe10, 2, 1, 0),
180 MTK_PIN_PUPD_SPEC_SR(114, 0xe20, 10, 9, 8),
181 MTK_PIN_PUPD_SPEC_SR(115, 0xe20, 2, 1, 0),
182 MTK_PIN_PUPD_SPEC_SR(116, 0xe20, 6, 5, 4),
183 MTK_PIN_PUPD_SPEC_SR(117, 0xe00, 14, 13, 12),
184 MTK_PIN_PUPD_SPEC_SR(118, 0xe00, 10, 9, 8),
185 MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 6, 5, 4),
186 MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
187};
188
189static int mt8516_spec_pull_set(struct regmap *regmap, unsigned int pin,
190 unsigned char align, bool isup, unsigned int r1r0)
191{
192 return mtk_pctrl_spec_pull_set_samereg(regmap, mt8516_spec_pupd,
193 ARRAY_SIZE(mt8516_spec_pupd), pin, align, isup, r1r0);
194}
195
196static const struct mtk_pin_ies_smt_set mt8516_ies_set[] = {
197 MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
198 MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
199 MTK_PIN_IES_SMT_SPEC(11, 13, 0x900, 12),
200 MTK_PIN_IES_SMT_SPEC(14, 17, 0x900, 13),
201 MTK_PIN_IES_SMT_SPEC(18, 20, 0x910, 10),
202 MTK_PIN_IES_SMT_SPEC(21, 23, 0x900, 13),
203 MTK_PIN_IES_SMT_SPEC(24, 25, 0x900, 12),
204 MTK_PIN_IES_SMT_SPEC(26, 30, 0x900, 0),
205 MTK_PIN_IES_SMT_SPEC(31, 33, 0x900, 1),
206 MTK_PIN_IES_SMT_SPEC(34, 39, 0x900, 2),
207 MTK_PIN_IES_SMT_SPEC(40, 40, 0x910, 11),
208 MTK_PIN_IES_SMT_SPEC(41, 43, 0x900, 10),
209 MTK_PIN_IES_SMT_SPEC(44, 47, 0x900, 11),
210 MTK_PIN_IES_SMT_SPEC(48, 51, 0x900, 14),
211 MTK_PIN_IES_SMT_SPEC(52, 53, 0x910, 0),
212 MTK_PIN_IES_SMT_SPEC(54, 54, 0x910, 2),
213 MTK_PIN_IES_SMT_SPEC(55, 57, 0x910, 4),
214 MTK_PIN_IES_SMT_SPEC(58, 59, 0x900, 15),
215 MTK_PIN_IES_SMT_SPEC(60, 61, 0x910, 1),
216 MTK_PIN_IES_SMT_SPEC(62, 65, 0x910, 5),
217 MTK_PIN_IES_SMT_SPEC(66, 67, 0x910, 6),
218 MTK_PIN_IES_SMT_SPEC(68, 68, 0x930, 2),
219 MTK_PIN_IES_SMT_SPEC(69, 69, 0x930, 1),
220 MTK_PIN_IES_SMT_SPEC(70, 70, 0x930, 6),
221 MTK_PIN_IES_SMT_SPEC(71, 71, 0x930, 5),
222 MTK_PIN_IES_SMT_SPEC(72, 72, 0x930, 4),
223 MTK_PIN_IES_SMT_SPEC(73, 73, 0x930, 3),
224 MTK_PIN_IES_SMT_SPEC(100, 103, 0x910, 7),
225 MTK_PIN_IES_SMT_SPEC(104, 104, 0x920, 12),
226 MTK_PIN_IES_SMT_SPEC(105, 105, 0x920, 11),
227 MTK_PIN_IES_SMT_SPEC(106, 106, 0x930, 0),
228 MTK_PIN_IES_SMT_SPEC(107, 107, 0x920, 15),
229 MTK_PIN_IES_SMT_SPEC(108, 108, 0x920, 14),
230 MTK_PIN_IES_SMT_SPEC(109, 109, 0x920, 13),
231 MTK_PIN_IES_SMT_SPEC(110, 110, 0x920, 9),
232 MTK_PIN_IES_SMT_SPEC(111, 111, 0x920, 8),
233 MTK_PIN_IES_SMT_SPEC(112, 112, 0x920, 7),
234 MTK_PIN_IES_SMT_SPEC(113, 113, 0x920, 6),
235 MTK_PIN_IES_SMT_SPEC(114, 114, 0x920, 10),
236 MTK_PIN_IES_SMT_SPEC(115, 115, 0x920, 1),
237 MTK_PIN_IES_SMT_SPEC(116, 116, 0x920, 0),
238 MTK_PIN_IES_SMT_SPEC(117, 117, 0x920, 5),
239 MTK_PIN_IES_SMT_SPEC(118, 118, 0x920, 4),
240 MTK_PIN_IES_SMT_SPEC(119, 119, 0x920, 3),
241 MTK_PIN_IES_SMT_SPEC(120, 120, 0x920, 2),
242 MTK_PIN_IES_SMT_SPEC(121, 124, 0x910, 9),
243};
244
245static const struct mtk_pin_ies_smt_set mt8516_smt_set[] = {
246 MTK_PIN_IES_SMT_SPEC(0, 6, 0xA00, 2),
247 MTK_PIN_IES_SMT_SPEC(7, 10, 0xA00, 3),
248 MTK_PIN_IES_SMT_SPEC(11, 13, 0xA00, 12),
249 MTK_PIN_IES_SMT_SPEC(14, 17, 0xA00, 13),
250 MTK_PIN_IES_SMT_SPEC(18, 20, 0xA10, 10),
251 MTK_PIN_IES_SMT_SPEC(21, 23, 0xA00, 13),
252 MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),
253 MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),
254 MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),
255 MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2),
256 MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),
257 MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),
258 MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),
259 MTK_PIN_IES_SMT_SPEC(48, 51, 0xA00, 14),
260 MTK_PIN_IES_SMT_SPEC(52, 53, 0xA10, 0),
261 MTK_PIN_IES_SMT_SPEC(54, 54, 0xA10, 2),
262 MTK_PIN_IES_SMT_SPEC(55, 57, 0xA10, 4),
263 MTK_PIN_IES_SMT_SPEC(58, 59, 0xA00, 15),
264 MTK_PIN_IES_SMT_SPEC(60, 61, 0xA10, 1),
265 MTK_PIN_IES_SMT_SPEC(62, 65, 0xA10, 5),
266 MTK_PIN_IES_SMT_SPEC(66, 67, 0xA10, 6),
267 MTK_PIN_IES_SMT_SPEC(68, 68, 0xA30, 2),
268 MTK_PIN_IES_SMT_SPEC(69, 69, 0xA30, 1),
269 MTK_PIN_IES_SMT_SPEC(70, 70, 0xA30, 3),
270 MTK_PIN_IES_SMT_SPEC(71, 71, 0xA30, 4),
271 MTK_PIN_IES_SMT_SPEC(72, 72, 0xA30, 5),
272 MTK_PIN_IES_SMT_SPEC(73, 73, 0xA30, 6),
273
274 MTK_PIN_IES_SMT_SPEC(100, 103, 0xA10, 7),
275 MTK_PIN_IES_SMT_SPEC(104, 104, 0xA20, 12),
276 MTK_PIN_IES_SMT_SPEC(105, 105, 0xA20, 11),
277 MTK_PIN_IES_SMT_SPEC(106, 106, 0xA30, 13),
278 MTK_PIN_IES_SMT_SPEC(107, 107, 0xA20, 14),
279 MTK_PIN_IES_SMT_SPEC(108, 108, 0xA20, 15),
280 MTK_PIN_IES_SMT_SPEC(109, 109, 0xA30, 0),
281 MTK_PIN_IES_SMT_SPEC(110, 110, 0xA20, 9),
282 MTK_PIN_IES_SMT_SPEC(111, 111, 0xA20, 8),
283 MTK_PIN_IES_SMT_SPEC(112, 112, 0xA20, 7),
284 MTK_PIN_IES_SMT_SPEC(113, 113, 0xA20, 6),
285 MTK_PIN_IES_SMT_SPEC(114, 114, 0xA20, 10),
286 MTK_PIN_IES_SMT_SPEC(115, 115, 0xA20, 1),
287 MTK_PIN_IES_SMT_SPEC(116, 116, 0xA20, 0),
288 MTK_PIN_IES_SMT_SPEC(117, 117, 0xA20, 5),
289 MTK_PIN_IES_SMT_SPEC(118, 118, 0xA20, 4),
290 MTK_PIN_IES_SMT_SPEC(119, 119, 0xA20, 3),
291 MTK_PIN_IES_SMT_SPEC(120, 120, 0xA20, 2),
292 MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
293};
294
295static int mt8516_ies_smt_set(struct regmap *regmap, unsigned int pin,
296 unsigned char align, int value, enum pin_config_param arg)
297{
298 if (arg == PIN_CONFIG_INPUT_ENABLE)
299 return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_ies_set,
300 ARRAY_SIZE(mt8516_ies_set), pin, align, value);
301 else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
302 return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_smt_set,
303 ARRAY_SIZE(mt8516_smt_set), pin, align, value);
304 return -EINVAL;
305}
306
307static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = {
308 .pins = mtk_pins_mt8516,
309 .npins = ARRAY_SIZE(mtk_pins_mt8516),
310 .grp_desc = mt8516_drv_grp,
311 .n_grp_cls = ARRAY_SIZE(mt8516_drv_grp),
312 .pin_drv_grp = mt8516_pin_drv,
313 .n_pin_drv_grps = ARRAY_SIZE(mt8516_pin_drv),
314 .spec_pull_set = mt8516_spec_pull_set,
315 .spec_ies_smt_set = mt8516_ies_smt_set,
316 .dir_offset = 0x0000,
317 .pullen_offset = 0x0500,
318 .pullsel_offset = 0x0600,
319 .dout_offset = 0x0100,
320 .din_offset = 0x0200,
321 .pinmux_offset = 0x0300,
322 .type1_start = 125,
323 .type1_end = 125,
324 .port_shf = 4,
325 .port_mask = 0xf,
326 .port_align = 4,
327 .eint_hw = {
328 .port_mask = 7,
329 .ports = 6,
330 .ap_num = 169,
331 .db_cnt = 64,
332 },
333};
334
335static int mt8516_pinctrl_probe(struct platform_device *pdev)
336{
337 return mtk_pctrl_init(pdev, &mt8516_pinctrl_data, NULL);
338}
339
340static const struct of_device_id mt8516_pctrl_match[] = {
341 {
342 .compatible = "mediatek,mt8516-pinctrl",
343 },
344 {}
345};
346
347MODULE_DEVICE_TABLE(of, mt8516_pctrl_match);
348
349static struct platform_driver mtk_pinctrl_driver = {
350 .probe = mt8516_pinctrl_probe,
351 .driver = {
352 .name = "mediatek-mt8516-pinctrl",
353 .of_match_table = mt8516_pctrl_match,
354 .pm = &mtk_eint_pm_ops,
355 },
356};
357
358static int __init mtk_pinctrl_init(void)
359{
360 return platform_driver_register(&mtk_pinctrl_driver);
361}
362arch_initcall(mtk_pinctrl_init);
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
index b1c368455d30..20e1c890e73b 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
@@ -674,3 +674,52 @@ int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
674 674
675 return 0; 675 return 0;
676} 676}
677
678int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
679 const struct mtk_pin_desc *desc, u32 arg)
680{
681 int err;
682 int en = arg & 1;
683 int e0 = !!(arg & 2);
684 int e1 = !!(arg & 4);
685
686 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, en);
687 if (err)
688 return err;
689
690 if (!en)
691 return err;
692
693 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, e0);
694 if (err)
695 return err;
696
697 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1);
698 if (err)
699 return err;
700
701 return err;
702}
703
704int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
705 const struct mtk_pin_desc *desc, u32 *val)
706{
707 u32 en, e0, e1;
708 int err;
709
710 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, &en);
711 if (err)
712 return err;
713
714 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, &e0);
715 if (err)
716 return err;
717
718 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, &e1);
719 if (err)
720 return err;
721
722 *val = (en | e0 << 1 | e1 << 2) & 0x7;
723
724 return 0;
725}
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
index 6d24522739d9..1b7da42aa1d5 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
@@ -63,6 +63,9 @@ enum {
63 PINCTRL_PIN_REG_IES, 63 PINCTRL_PIN_REG_IES,
64 PINCTRL_PIN_REG_PULLEN, 64 PINCTRL_PIN_REG_PULLEN,
65 PINCTRL_PIN_REG_PULLSEL, 65 PINCTRL_PIN_REG_PULLSEL,
66 PINCTRL_PIN_REG_DRV_EN,
67 PINCTRL_PIN_REG_DRV_E0,
68 PINCTRL_PIN_REG_DRV_E1,
66 PINCTRL_PIN_REG_MAX, 69 PINCTRL_PIN_REG_MAX,
67}; 70};
68 71
@@ -224,6 +227,10 @@ struct mtk_pin_soc {
224 int (*adv_pull_get)(struct mtk_pinctrl *hw, 227 int (*adv_pull_get)(struct mtk_pinctrl *hw,
225 const struct mtk_pin_desc *desc, bool pullup, 228 const struct mtk_pin_desc *desc, bool pullup,
226 u32 *val); 229 u32 *val);
230 int (*adv_drive_set)(struct mtk_pinctrl *hw,
231 const struct mtk_pin_desc *desc, u32 arg);
232 int (*adv_drive_get)(struct mtk_pinctrl *hw,
233 const struct mtk_pin_desc *desc, u32 *val);
227 234
228 /* Specific driver data */ 235 /* Specific driver data */
229 void *driver_data; 236 void *driver_data;
@@ -287,5 +294,9 @@ int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
287int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw, 294int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
288 const struct mtk_pin_desc *desc, bool pullup, 295 const struct mtk_pin_desc *desc, bool pullup,
289 u32 *val); 296 u32 *val);
297int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
298 const struct mtk_pin_desc *desc, u32 arg);
299int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
300 const struct mtk_pin_desc *desc, u32 *val);
290 301
291#endif /* __PINCTRL_MTK_COMMON_V2_H */ 302#endif /* __PINCTRL_MTK_COMMON_V2_H */
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h
new file mode 100644
index 000000000000..f7a4c6e4a026
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h
@@ -0,0 +1,1182 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2019 MediaTek Inc.
4 */
5#ifndef __PINCTRL_MTK_MT8516_H
6#define __PINCTRL_MTK_MT8516_H
7
8#include <linux/pinctrl/pinctrl.h>
9#include "pinctrl-mtk-common.h"
10
11static const struct mtk_desc_pin mtk_pins_mt8516[] = {
12 MTK_PIN(
13 PINCTRL_PIN(0, "EINT0"),
14 NULL, "mt8516",
15 MTK_EINT_FUNCTION(0, 0),
16 MTK_FUNCTION(0, "GPIO0"),
17 MTK_FUNCTION(1, "PWM_B"),
18 MTK_FUNCTION(3, "I2S2_BCK"),
19 MTK_FUNCTION(4, "EXT_TXD0"),
20 MTK_FUNCTION(6, "SQICS"),
21 MTK_FUNCTION(7, "DBG_MON_A[6]")
22 ),
23 MTK_PIN(
24 PINCTRL_PIN(1, "EINT1"),
25 NULL, "mt8516",
26 MTK_EINT_FUNCTION(0, 1),
27 MTK_FUNCTION(0, "GPIO1"),
28 MTK_FUNCTION(1, "PWM_C"),
29 MTK_FUNCTION(3, "I2S2_DI"),
30 MTK_FUNCTION(4, "EXT_TXD1"),
31 MTK_FUNCTION(5, "CONN_MCU_TDO"),
32 MTK_FUNCTION(6, "SQISO"),
33 MTK_FUNCTION(7, "DBG_MON_A[7]")
34 ),
35 MTK_PIN(
36 PINCTRL_PIN(2, "EINT2"),
37 NULL, "mt8516",
38 MTK_EINT_FUNCTION(0, 2),
39 MTK_FUNCTION(0, "GPIO2"),
40 MTK_FUNCTION(1, "CLKM0"),
41 MTK_FUNCTION(3, "I2S2_LRCK"),
42 MTK_FUNCTION(4, "EXT_TXD2"),
43 MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"),
44 MTK_FUNCTION(6, "SQISI"),
45 MTK_FUNCTION(7, "DBG_MON_A[8]")
46 ),
47 MTK_PIN(
48 PINCTRL_PIN(3, "EINT3"),
49 NULL, "mt8516",
50 MTK_EINT_FUNCTION(0, 3),
51 MTK_FUNCTION(0, "GPIO3"),
52 MTK_FUNCTION(1, "CLKM1"),
53 MTK_FUNCTION(3, "SPI_MI"),
54 MTK_FUNCTION(4, "EXT_TXD3"),
55 MTK_FUNCTION(5, "CONN_MCU_DBGI_N"),
56 MTK_FUNCTION(6, "SQIWP"),
57 MTK_FUNCTION(7, "DBG_MON_A[9]")
58 ),
59 MTK_PIN(
60 PINCTRL_PIN(4, "EINT4"),
61 NULL, "mt8516",
62 MTK_EINT_FUNCTION(0, 4),
63 MTK_FUNCTION(0, "GPIO4"),
64 MTK_FUNCTION(1, "CLKM2"),
65 MTK_FUNCTION(3, "SPI_MO"),
66 MTK_FUNCTION(4, "EXT_TXC"),
67 MTK_FUNCTION(5, "CONN_MCU_TCK"),
68 MTK_FUNCTION(6, "CONN_MCU_AICE_JCKC"),
69 MTK_FUNCTION(7, "DBG_MON_A[10]")
70 ),
71 MTK_PIN(
72 PINCTRL_PIN(5, "EINT5"),
73 NULL, "mt8516",
74 MTK_EINT_FUNCTION(0, 5),
75 MTK_FUNCTION(0, "GPIO5"),
76 MTK_FUNCTION(1, "UCTS2"),
77 MTK_FUNCTION(3, "SPI_CSB"),
78 MTK_FUNCTION(4, "EXT_RXER"),
79 MTK_FUNCTION(5, "CONN_MCU_TDI"),
80 MTK_FUNCTION(6, "CONN_TEST_CK"),
81 MTK_FUNCTION(7, "DBG_MON_A[11]")
82 ),
83 MTK_PIN(
84 PINCTRL_PIN(6, "EINT6"),
85 NULL, "mt8516",
86 MTK_EINT_FUNCTION(0, 6),
87 MTK_FUNCTION(0, "GPIO6"),
88 MTK_FUNCTION(1, "URTS2"),
89 MTK_FUNCTION(3, "SPI_CLK"),
90 MTK_FUNCTION(4, "EXT_RXC"),
91 MTK_FUNCTION(5, "CONN_MCU_TRST_B"),
92 MTK_FUNCTION(7, "DBG_MON_A[12]")
93 ),
94 MTK_PIN(
95 PINCTRL_PIN(7, "EINT7"),
96 NULL, "mt8516",
97 MTK_EINT_FUNCTION(0, 7),
98 MTK_FUNCTION(0, "GPIO7"),
99 MTK_FUNCTION(1, "SQIRST"),
100 MTK_FUNCTION(3, "SDA1_0"),
101 MTK_FUNCTION(4, "EXT_RXDV"),
102 MTK_FUNCTION(5, "CONN_MCU_TMS"),
103 MTK_FUNCTION(6, "CONN_MCU_AICE_JMSC"),
104 MTK_FUNCTION(7, "DBG_MON_A[13]")
105 ),
106 MTK_PIN(
107 PINCTRL_PIN(8, "EINT8"),
108 NULL, "mt8516",
109 MTK_EINT_FUNCTION(0, 8),
110 MTK_FUNCTION(0, "GPIO8"),
111 MTK_FUNCTION(1, "SQICK"),
112 MTK_FUNCTION(2, "CLKM3"),
113 MTK_FUNCTION(3, "SCL1_0"),
114 MTK_FUNCTION(4, "EXT_RXD0"),
115 MTK_FUNCTION(5, "ANT_SEL0"),
116 MTK_FUNCTION(7, "DBG_MON_A[14]")
117 ),
118 MTK_PIN(
119 PINCTRL_PIN(9, "EINT9"),
120 NULL, "mt8516",
121 MTK_EINT_FUNCTION(0, 9),
122 MTK_FUNCTION(0, "GPIO9"),
123 MTK_FUNCTION(1, "CLKM4"),
124 MTK_FUNCTION(2, "SDA2_0"),
125 MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
126 MTK_FUNCTION(4, "EXT_RXD1"),
127 MTK_FUNCTION(5, "ANT_SEL1"),
128 MTK_FUNCTION(7, "DBG_MON_A[15]")
129 ),
130 MTK_PIN(
131 PINCTRL_PIN(10, "EINT10"),
132 NULL, "mt8516",
133 MTK_EINT_FUNCTION(0, 10),
134 MTK_FUNCTION(0, "GPIO10"),
135 MTK_FUNCTION(1, "CLKM5"),
136 MTK_FUNCTION(2, "SCL2_0"),
137 MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
138 MTK_FUNCTION(4, "EXT_RXD2"),
139 MTK_FUNCTION(5, "ANT_SEL2"),
140 MTK_FUNCTION(7, "DBG_MON_A[16]")
141 ),
142 MTK_PIN(
143 PINCTRL_PIN(11, "EINT11"),
144 NULL, "mt8516",
145 MTK_EINT_FUNCTION(0, 11),
146 MTK_FUNCTION(0, "GPIO11"),
147 MTK_FUNCTION(1, "CLKM4"),
148 MTK_FUNCTION(2, "PWM_C"),
149 MTK_FUNCTION(3, "CONN_TEST_CK"),
150 MTK_FUNCTION(4, "ANT_SEL3"),
151 MTK_FUNCTION(6, "EXT_RXD3"),
152 MTK_FUNCTION(7, "DBG_MON_A[17]")
153 ),
154 MTK_PIN(
155 PINCTRL_PIN(12, "EINT12"),
156 NULL, "mt8516",
157 MTK_EINT_FUNCTION(0, 12),
158 MTK_FUNCTION(0, "GPIO12"),
159 MTK_FUNCTION(1, "CLKM5"),
160 MTK_FUNCTION(2, "PWM_A"),
161 MTK_FUNCTION(3, "SPDIF_OUT"),
162 MTK_FUNCTION(4, "ANT_SEL4"),
163 MTK_FUNCTION(6, "EXT_TXEN"),
164 MTK_FUNCTION(7, "DBG_MON_A[18]")
165 ),
166 MTK_PIN(
167 PINCTRL_PIN(13, "EINT13"),
168 NULL, "mt8516",
169 MTK_EINT_FUNCTION(0, 13),
170 MTK_FUNCTION(0, "GPIO13"),
171 MTK_FUNCTION(3, "TSF_IN"),
172 MTK_FUNCTION(4, "ANT_SEL5"),
173 MTK_FUNCTION(6, "SPDIF_IN"),
174 MTK_FUNCTION(7, "DBG_MON_A[19]")
175 ),
176 MTK_PIN(
177 PINCTRL_PIN(14, "EINT14"),
178 NULL, "mt8516",
179 MTK_EINT_FUNCTION(0, 14),
180 MTK_FUNCTION(0, "GPIO14"),
181 MTK_FUNCTION(2, "I2S_8CH_DO1"),
182 MTK_FUNCTION(3, "TDM_RX_MCK"),
183 MTK_FUNCTION(4, "ANT_SEL1"),
184 MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"),
185 MTK_FUNCTION(6, "NCLE"),
186 MTK_FUNCTION(7, "DBG_MON_B[8]")
187 ),
188 MTK_PIN(
189 PINCTRL_PIN(15, "EINT15"),
190 NULL, "mt8516",
191 MTK_EINT_FUNCTION(0, 15),
192 MTK_FUNCTION(0, "GPIO15"),
193 MTK_FUNCTION(2, "I2S_8CH_LRCK"),
194 MTK_FUNCTION(3, "TDM_RX_BCK"),
195 MTK_FUNCTION(4, "ANT_SEL2"),
196 MTK_FUNCTION(5, "CONN_MCU_DBGI_N"),
197 MTK_FUNCTION(6, "NCEB1"),
198 MTK_FUNCTION(7, "DBG_MON_B[9]")
199 ),
200 MTK_PIN(
201 PINCTRL_PIN(16, "EINT16"),
202 NULL, "mt8516",
203 MTK_EINT_FUNCTION(0, 16),
204 MTK_FUNCTION(0, "GPIO16"),
205 MTK_FUNCTION(2, "I2S_8CH_BCK"),
206 MTK_FUNCTION(3, "TDM_RX_LRCK"),
207 MTK_FUNCTION(4, "ANT_SEL3"),
208 MTK_FUNCTION(5, "CONN_MCU_TRST_B"),
209 MTK_FUNCTION(6, "NCEB0"),
210 MTK_FUNCTION(7, "DBG_MON_B[10]")
211 ),
212 MTK_PIN(
213 PINCTRL_PIN(17, "EINT17"),
214 NULL, "mt8516",
215 MTK_EINT_FUNCTION(0, 17),
216 MTK_FUNCTION(0, "GPIO17"),
217 MTK_FUNCTION(2, "I2S_8CH_MCK"),
218 MTK_FUNCTION(3, "TDM_RX_DI"),
219 MTK_FUNCTION(4, "IDDIG"),
220 MTK_FUNCTION(5, "ANT_SEL4"),
221 MTK_FUNCTION(6, "NREB"),
222 MTK_FUNCTION(7, "DBG_MON_B[11]")
223 ),
224 MTK_PIN(
225 PINCTRL_PIN(18, "EINT18"),
226 NULL, "mt8516",
227 MTK_EINT_FUNCTION(0, 18),
228 MTK_FUNCTION(0, "GPIO18"),
229 MTK_FUNCTION(2, "USB_DRVVBUS"),
230 MTK_FUNCTION(3, "I2S3_LRCK"),
231 MTK_FUNCTION(4, "CLKM1"),
232 MTK_FUNCTION(5, "ANT_SEL3"),
233 MTK_FUNCTION(6, "I2S2_BCK"),
234 MTK_FUNCTION(7, "DBG_MON_A[20]")
235 ),
236 MTK_PIN(
237 PINCTRL_PIN(19, "EINT19"),
238 NULL, "mt8516",
239 MTK_EINT_FUNCTION(0, 19),
240 MTK_FUNCTION(0, "GPIO19"),
241 MTK_FUNCTION(1, "UCTS1"),
242 MTK_FUNCTION(2, "IDDIG"),
243 MTK_FUNCTION(3, "I2S3_BCK"),
244 MTK_FUNCTION(4, "CLKM2"),
245 MTK_FUNCTION(5, "ANT_SEL4"),
246 MTK_FUNCTION(6, "I2S2_DI"),
247 MTK_FUNCTION(7, "DBG_MON_A[21]")
248 ),
249 MTK_PIN(
250 PINCTRL_PIN(20, "EINT20"),
251 NULL, "mt8516",
252 MTK_EINT_FUNCTION(0, 20),
253 MTK_FUNCTION(0, "GPIO20"),
254 MTK_FUNCTION(1, "URTS1"),
255 MTK_FUNCTION(3, "I2S3_DO"),
256 MTK_FUNCTION(4, "CLKM3"),
257 MTK_FUNCTION(5, "ANT_SEL5"),
258 MTK_FUNCTION(6, "I2S2_LRCK"),
259 MTK_FUNCTION(7, "DBG_MON_A[22]")
260 ),
261 MTK_PIN(
262 PINCTRL_PIN(21, "EINT21"),
263 NULL, "mt8516",
264 MTK_EINT_FUNCTION(0, 21),
265 MTK_FUNCTION(0, "GPIO21"),
266 MTK_FUNCTION(1, "NRNB"),
267 MTK_FUNCTION(2, "ANT_SEL0"),
268 MTK_FUNCTION(3, "I2S_8CH_DO4"),
269 MTK_FUNCTION(7, "DBG_MON_B[31]")
270 ),
271 MTK_PIN(
272 PINCTRL_PIN(22, "EINT22"),
273 NULL, "mt8516",
274 MTK_EINT_FUNCTION(0, 22),
275 MTK_FUNCTION(0, "GPIO22"),
276 MTK_FUNCTION(2, "I2S_8CH_DO2"),
277 MTK_FUNCTION(3, "TSF_IN"),
278 MTK_FUNCTION(4, "USB_DRVVBUS"),
279 MTK_FUNCTION(5, "SPDIF_OUT"),
280 MTK_FUNCTION(6, "NRE_C"),
281 MTK_FUNCTION(7, "DBG_MON_B[12]")
282 ),
283 MTK_PIN(
284 PINCTRL_PIN(23, "EINT23"),
285 NULL, "mt8516",
286 MTK_EINT_FUNCTION(0, 23),
287 MTK_FUNCTION(0, "GPIO23"),
288 MTK_FUNCTION(2, "I2S_8CH_DO3"),
289 MTK_FUNCTION(3, "CLKM0"),
290 MTK_FUNCTION(4, "IR"),
291 MTK_FUNCTION(5, "SPDIF_IN"),
292 MTK_FUNCTION(6, "NDQS_C"),
293 MTK_FUNCTION(7, "DBG_MON_B[13]")
294 ),
295 MTK_PIN(
296 PINCTRL_PIN(24, "EINT24"),
297 NULL, "mt8516",
298 MTK_EINT_FUNCTION(0, 24),
299 MTK_FUNCTION(0, "GPIO24"),
300 MTK_FUNCTION(3, "ANT_SEL1"),
301 MTK_FUNCTION(4, "UCTS2"),
302 MTK_FUNCTION(5, "PWM_A"),
303 MTK_FUNCTION(6, "I2S0_MCK"),
304 MTK_FUNCTION(7, "DBG_MON_A[0]")
305 ),
306 MTK_PIN(
307 PINCTRL_PIN(25, "EINT25"),
308 NULL, "mt8516",
309 MTK_EINT_FUNCTION(0, 25),
310 MTK_FUNCTION(0, "GPIO25"),
311 MTK_FUNCTION(3, "ANT_SEL0"),
312 MTK_FUNCTION(4, "URTS2"),
313 MTK_FUNCTION(5, "PWM_B"),
314 MTK_FUNCTION(6, "I2S_8CH_MCK"),
315 MTK_FUNCTION(7, "DBG_MON_A[1]")
316 ),
317 MTK_PIN(
318 PINCTRL_PIN(26, "PWRAP_SPI0_MI"),
319 NULL, "mt8516",
320 MTK_EINT_FUNCTION(0, 26),
321 MTK_FUNCTION(0, "GPIO26"),
322 MTK_FUNCTION(1, "PWRAP_SPI0_MO"),
323 MTK_FUNCTION(2, "PWRAP_SPI0_MI")
324 ),
325 MTK_PIN(
326 PINCTRL_PIN(27, "PWRAP_SPI0_MO"),
327 NULL, "mt8516",
328 MTK_EINT_FUNCTION(0, 27),
329 MTK_FUNCTION(0, "GPIO27"),
330 MTK_FUNCTION(1, "PWRAP_SPI0_MI"),
331 MTK_FUNCTION(2, "PWRAP_SPI0_MO")
332 ),
333 MTK_PIN(
334 PINCTRL_PIN(28, "PWRAP_INT"),
335 NULL, "mt8516",
336 MTK_EINT_FUNCTION(0, 28),
337 MTK_FUNCTION(0, "GPIO28"),
338 MTK_FUNCTION(1, "I2S0_MCK"),
339 MTK_FUNCTION(4, "I2S_8CH_MCK"),
340 MTK_FUNCTION(5, "I2S2_MCK"),
341 MTK_FUNCTION(6, "I2S3_MCK")
342 ),
343 MTK_PIN(
344 PINCTRL_PIN(29, "PWRAP_SPI0_CK"),
345 NULL, "mt8516",
346 MTK_EINT_FUNCTION(0, 29),
347 MTK_FUNCTION(0, "GPIO29"),
348 MTK_FUNCTION(1, "PWRAP_SPI0_CK")
349 ),
350 MTK_PIN(
351 PINCTRL_PIN(30, "PWRAP_SPI0_CSN"),
352 NULL, "mt8516",
353 MTK_EINT_FUNCTION(0, 30),
354 MTK_FUNCTION(0, "GPIO30"),
355 MTK_FUNCTION(1, "PWRAP_SPI0_CSN")
356 ),
357 MTK_PIN(
358 PINCTRL_PIN(31, "RTC32K_CK"),
359 NULL, "mt8516",
360 MTK_EINT_FUNCTION(0, 31),
361 MTK_FUNCTION(0, "GPIO31"),
362 MTK_FUNCTION(1, "RTC32K_CK")
363 ),
364 MTK_PIN(
365 PINCTRL_PIN(32, "WATCHDOG"),
366 NULL, "mt8516",
367 MTK_EINT_FUNCTION(0, 32),
368 MTK_FUNCTION(0, "GPIO32"),
369 MTK_FUNCTION(1, "WATCHDOG")
370 ),
371 MTK_PIN(
372 PINCTRL_PIN(33, "SRCLKENA"),
373 NULL, "mt8516",
374 MTK_EINT_FUNCTION(0, 33),
375 MTK_FUNCTION(0, "GPIO33"),
376 MTK_FUNCTION(1, "SRCLKENA0")
377 ),
378 MTK_PIN(
379 PINCTRL_PIN(34, "URXD2"),
380 NULL, "mt8516",
381 MTK_EINT_FUNCTION(0, 34),
382 MTK_FUNCTION(0, "GPIO34"),
383 MTK_FUNCTION(1, "URXD2"),
384 MTK_FUNCTION(3, "UTXD2"),
385 MTK_FUNCTION(4, "DBG_SCL"),
386 MTK_FUNCTION(6, "I2S2_MCK"),
387 MTK_FUNCTION(7, "DBG_MON_B[0]")
388 ),
389 MTK_PIN(
390 PINCTRL_PIN(35, "UTXD2"),
391 NULL, "mt8516",
392 MTK_EINT_FUNCTION(0, 35),
393 MTK_FUNCTION(0, "GPIO35"),
394 MTK_FUNCTION(1, "UTXD2"),
395 MTK_FUNCTION(3, "URXD2"),
396 MTK_FUNCTION(4, "DBG_SDA"),
397 MTK_FUNCTION(6, "I2S3_MCK"),
398 MTK_FUNCTION(7, "DBG_MON_B[1]")
399 ),
400 MTK_PIN(
401 PINCTRL_PIN(36, "MRG_CLK"),
402 NULL, "mt8516",
403 MTK_EINT_FUNCTION(0, 36),
404 MTK_FUNCTION(0, "GPIO36"),
405 MTK_FUNCTION(1, "MRG_CLK"),
406 MTK_FUNCTION(3, "I2S0_BCK"),
407 MTK_FUNCTION(4, "I2S3_BCK"),
408 MTK_FUNCTION(5, "PCM0_CLK"),
409 MTK_FUNCTION(6, "IR"),
410 MTK_FUNCTION(7, "DBG_MON_A[2]")
411 ),
412 MTK_PIN(
413 PINCTRL_PIN(37, "MRG_SYNC"),
414 NULL, "mt8516",
415 MTK_EINT_FUNCTION(0, 37),
416 MTK_FUNCTION(0, "GPIO37"),
417 MTK_FUNCTION(1, "MRG_SYNC"),
418 MTK_FUNCTION(3, "I2S0_LRCK"),
419 MTK_FUNCTION(4, "I2S3_LRCK"),
420 MTK_FUNCTION(5, "PCM0_SYNC"),
421 MTK_FUNCTION(6, "EXT_COL"),
422 MTK_FUNCTION(7, "DBG_MON_A[3]")
423 ),
424 MTK_PIN(
425 PINCTRL_PIN(38, "MRG_DI"),
426 NULL, "mt8516",
427 MTK_EINT_FUNCTION(0, 38),
428 MTK_FUNCTION(0, "GPIO38"),
429 MTK_FUNCTION(1, "MRG_DI"),
430 MTK_FUNCTION(3, "I2S0_DI"),
431 MTK_FUNCTION(4, "I2S3_DO"),
432 MTK_FUNCTION(5, "PCM0_DI"),
433 MTK_FUNCTION(6, "EXT_MDIO"),
434 MTK_FUNCTION(7, "DBG_MON_A[4]")
435 ),
436 MTK_PIN(
437 PINCTRL_PIN(39, "MRG_DO"),
438 NULL, "mt8516",
439 MTK_EINT_FUNCTION(0, 39),
440 MTK_FUNCTION(0, "GPIO39"),
441 MTK_FUNCTION(1, "MRG_DO"),
442 MTK_FUNCTION(3, "I2S0_MCK"),
443 MTK_FUNCTION(4, "I2S3_MCK"),
444 MTK_FUNCTION(5, "PCM0_DO"),
445 MTK_FUNCTION(6, "EXT_MDC"),
446 MTK_FUNCTION(7, "DBG_MON_A[5]")
447 ),
448 MTK_PIN(
449 PINCTRL_PIN(40, "KPROW0"),
450 NULL, "mt8516",
451 MTK_EINT_FUNCTION(0, 40),
452 MTK_FUNCTION(0, "GPIO40"),
453 MTK_FUNCTION(1, "KPROW0"),
454 MTK_FUNCTION(7, "DBG_MON_B[4]")
455 ),
456 MTK_PIN(
457 PINCTRL_PIN(41, "KPROW1"),
458 NULL, "mt8516",
459 MTK_EINT_FUNCTION(0, 41),
460 MTK_FUNCTION(0, "GPIO41"),
461 MTK_FUNCTION(1, "KPROW1"),
462 MTK_FUNCTION(2, "IDDIG"),
463 MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
464 MTK_FUNCTION(7, "DBG_MON_B[5]")
465 ),
466 MTK_PIN(
467 PINCTRL_PIN(42, "KPCOL0"),
468 NULL, "mt8516",
469 MTK_EINT_FUNCTION(0, 42),
470 MTK_FUNCTION(0, "GPIO42"),
471 MTK_FUNCTION(1, "KPCOL0"),
472 MTK_FUNCTION(7, "DBG_MON_B[6]")
473 ),
474 MTK_PIN(
475 PINCTRL_PIN(43, "KPCOL1"),
476 NULL, "mt8516",
477 MTK_EINT_FUNCTION(0, 43),
478 MTK_FUNCTION(0, "GPIO43"),
479 MTK_FUNCTION(1, "KPCOL1"),
480 MTK_FUNCTION(2, "USB_DRVVBUS"),
481 MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
482 MTK_FUNCTION(4, "TSF_IN"),
483 MTK_FUNCTION(7, "DBG_MON_B[7]")
484 ),
485 MTK_PIN(
486 PINCTRL_PIN(44, "JTMS"),
487 NULL, "mt8516",
488 MTK_EINT_FUNCTION(0, 44),
489 MTK_FUNCTION(0, "GPIO44"),
490 MTK_FUNCTION(1, "JTMS"),
491 MTK_FUNCTION(2, "CONN_MCU_TMS"),
492 MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC")
493 ),
494 MTK_PIN(
495 PINCTRL_PIN(45, "JTCK"),
496 NULL, "mt8516",
497 MTK_EINT_FUNCTION(0, 45),
498 MTK_FUNCTION(0, "GPIO45"),
499 MTK_FUNCTION(1, "JTCK"),
500 MTK_FUNCTION(2, "CONN_MCU_TCK"),
501 MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC")
502 ),
503 MTK_PIN(
504 PINCTRL_PIN(46, "JTDI"),
505 NULL, "mt8516",
506 MTK_EINT_FUNCTION(0, 46),
507 MTK_FUNCTION(0, "GPIO46"),
508 MTK_FUNCTION(1, "JTDI"),
509 MTK_FUNCTION(2, "CONN_MCU_TDI")
510 ),
511 MTK_PIN(
512 PINCTRL_PIN(47, "JTDO"),
513 NULL, "mt8516",
514 MTK_EINT_FUNCTION(0, 47),
515 MTK_FUNCTION(0, "GPIO47"),
516 MTK_FUNCTION(1, "JTDO"),
517 MTK_FUNCTION(2, "CONN_MCU_TDO")
518 ),
519 MTK_PIN(
520 PINCTRL_PIN(48, "SPI_CS"),
521 NULL, "mt8516",
522 MTK_EINT_FUNCTION(0, 48),
523 MTK_FUNCTION(0, "GPIO48"),
524 MTK_FUNCTION(1, "SPI_CSB"),
525 MTK_FUNCTION(3, "I2S0_DI"),
526 MTK_FUNCTION(4, "I2S2_BCK"),
527 MTK_FUNCTION(7, "DBG_MON_A[23]")
528 ),
529 MTK_PIN(
530 PINCTRL_PIN(49, "SPI_CK"),
531 NULL, "mt8516",
532 MTK_EINT_FUNCTION(0, 49),
533 MTK_FUNCTION(0, "GPIO49"),
534 MTK_FUNCTION(1, "SPI_CLK"),
535 MTK_FUNCTION(3, "I2S0_LRCK"),
536 MTK_FUNCTION(4, "I2S2_DI"),
537 MTK_FUNCTION(7, "DBG_MON_A[24]")
538 ),
539 MTK_PIN(
540 PINCTRL_PIN(50, "SPI_MI"),
541 NULL, "mt8516",
542 MTK_EINT_FUNCTION(0, 50),
543 MTK_FUNCTION(0, "GPIO50"),
544 MTK_FUNCTION(1, "SPI_MI"),
545 MTK_FUNCTION(2, "SPI_MO"),
546 MTK_FUNCTION(3, "I2S0_BCK"),
547 MTK_FUNCTION(4, "I2S2_LRCK"),
548 MTK_FUNCTION(7, "DBG_MON_A[25]")
549 ),
550 MTK_PIN(
551 PINCTRL_PIN(51, "SPI_MO"),
552 NULL, "mt8516",
553 MTK_EINT_FUNCTION(0, 51),
554 MTK_FUNCTION(0, "GPIO51"),
555 MTK_FUNCTION(1, "SPI_MO"),
556 MTK_FUNCTION(2, "SPI_MI"),
557 MTK_FUNCTION(3, "I2S0_MCK"),
558 MTK_FUNCTION(4, "I2S2_MCK"),
559 MTK_FUNCTION(7, "DBG_MON_A[26]")
560 ),
561 MTK_PIN(
562 PINCTRL_PIN(52, "SDA1"),
563 NULL, "mt8516",
564 MTK_EINT_FUNCTION(0, 52),
565 MTK_FUNCTION(0, "GPIO52"),
566 MTK_FUNCTION(1, "SDA1_0")
567 ),
568 MTK_PIN(
569 PINCTRL_PIN(53, "SCL1"),
570 NULL, "mt8516",
571 MTK_EINT_FUNCTION(0, 53),
572 MTK_FUNCTION(0, "GPIO53"),
573 MTK_FUNCTION(1, "SCL1_0")
574 ),
575 MTK_PIN(
576 PINCTRL_PIN(54, "GPIO54"),
577 NULL, "mt8516",
578 MTK_EINT_FUNCTION(0, 54),
579 MTK_FUNCTION(0, "GPIO54"),
580 MTK_FUNCTION(2, "PWM_B"),
581 MTK_FUNCTION(7, "DBG_MON_B[2]")
582 ),
583 MTK_PIN(
584 PINCTRL_PIN(55, "I2S_DATA_IN"),
585 NULL, "mt8516",
586 MTK_EINT_FUNCTION(0, 55),
587 MTK_FUNCTION(0, "GPIO55"),
588 MTK_FUNCTION(1, "I2S0_DI"),
589 MTK_FUNCTION(2, "UCTS0"),
590 MTK_FUNCTION(3, "I2S3_DO"),
591 MTK_FUNCTION(4, "I2S_8CH_DO1"),
592 MTK_FUNCTION(5, "PWM_A"),
593 MTK_FUNCTION(6, "I2S2_BCK"),
594 MTK_FUNCTION(7, "DBG_MON_A[28]")
595 ),
596 MTK_PIN(
597 PINCTRL_PIN(56, "I2S_LRCK"),
598 NULL, "mt8516",
599 MTK_EINT_FUNCTION(0, 56),
600 MTK_FUNCTION(0, "GPIO56"),
601 MTK_FUNCTION(1, "I2S0_LRCK"),
602 MTK_FUNCTION(3, "I2S3_LRCK"),
603 MTK_FUNCTION(4, "I2S_8CH_LRCK"),
604 MTK_FUNCTION(5, "PWM_B"),
605 MTK_FUNCTION(6, "I2S2_DI"),
606 MTK_FUNCTION(7, "DBG_MON_A[29]")
607 ),
608 MTK_PIN(
609 PINCTRL_PIN(57, "I2S_BCK"),
610 NULL, "mt8516",
611 MTK_EINT_FUNCTION(0, 57),
612 MTK_FUNCTION(0, "GPIO57"),
613 MTK_FUNCTION(1, "I2S0_BCK"),
614 MTK_FUNCTION(2, "URTS0"),
615 MTK_FUNCTION(3, "I2S3_BCK"),
616 MTK_FUNCTION(4, "I2S_8CH_BCK"),
617 MTK_FUNCTION(5, "PWM_C"),
618 MTK_FUNCTION(6, "I2S2_LRCK"),
619 MTK_FUNCTION(7, "DBG_MON_A[30]")
620 ),
621 MTK_PIN(
622 PINCTRL_PIN(58, "SDA0"),
623 NULL, "mt8516",
624 MTK_EINT_FUNCTION(0, 58),
625 MTK_FUNCTION(0, "GPIO58"),
626 MTK_FUNCTION(1, "SDA0_0")
627 ),
628 MTK_PIN(
629 PINCTRL_PIN(59, "SCL0"),
630 NULL, "mt8516",
631 MTK_EINT_FUNCTION(0, 59),
632 MTK_FUNCTION(0, "GPIO59"),
633 MTK_FUNCTION(1, "SCL0_0")
634 ),
635 MTK_PIN(
636 PINCTRL_PIN(60, "SDA2"),
637 NULL, "mt8516",
638 MTK_EINT_FUNCTION(0, 60),
639 MTK_FUNCTION(0, "GPIO60"),
640 MTK_FUNCTION(1, "SDA2_0"),
641 MTK_FUNCTION(2, "PWM_B")
642 ),
643 MTK_PIN(
644 PINCTRL_PIN(61, "SCL2"),
645 NULL, "mt8516",
646 MTK_EINT_FUNCTION(0, 61),
647 MTK_FUNCTION(0, "GPIO61"),
648 MTK_FUNCTION(1, "SCL2_0"),
649 MTK_FUNCTION(2, "PWM_C")
650 ),
651 MTK_PIN(
652 PINCTRL_PIN(62, "URXD0"),
653 NULL, "mt8516",
654 MTK_EINT_FUNCTION(0, 62),
655 MTK_FUNCTION(0, "GPIO62"),
656 MTK_FUNCTION(1, "URXD0"),
657 MTK_FUNCTION(2, "UTXD0")
658 ),
659 MTK_PIN(
660 PINCTRL_PIN(63, "UTXD0"),
661 NULL, "mt8516",
662 MTK_EINT_FUNCTION(0, 63),
663 MTK_FUNCTION(0, "GPIO63"),
664 MTK_FUNCTION(1, "UTXD0"),
665 MTK_FUNCTION(2, "URXD0")
666 ),
667 MTK_PIN(
668 PINCTRL_PIN(64, "URXD1"),
669 NULL, "mt8516",
670 MTK_EINT_FUNCTION(0, 64),
671 MTK_FUNCTION(0, "GPIO64"),
672 MTK_FUNCTION(1, "URXD1"),
673 MTK_FUNCTION(2, "UTXD1"),
674 MTK_FUNCTION(7, "DBG_MON_A[27]")
675 ),
676 MTK_PIN(
677 PINCTRL_PIN(65, "UTXD1"),
678 NULL, "mt8516",
679 MTK_EINT_FUNCTION(0, 65),
680 MTK_FUNCTION(0, "GPIO65"),
681 MTK_FUNCTION(1, "UTXD1"),
682 MTK_FUNCTION(2, "URXD1"),
683 MTK_FUNCTION(7, "DBG_MON_A[31]")
684 ),
685 MTK_PIN(
686 PINCTRL_PIN(66, "LCM_RST"),
687 NULL, "mt8516",
688 MTK_EINT_FUNCTION(0, 66),
689 MTK_FUNCTION(0, "GPIO66"),
690 MTK_FUNCTION(1, "LCM_RST"),
691 MTK_FUNCTION(3, "I2S0_MCK"),
692 MTK_FUNCTION(7, "DBG_MON_B[3]")
693 ),
694 MTK_PIN(
695 PINCTRL_PIN(67, "GPIO67"),
696 NULL, "mt8516",
697 MTK_EINT_FUNCTION(0, 67),
698 MTK_FUNCTION(0, "GPIO67"),
699 MTK_FUNCTION(3, "I2S_8CH_MCK"),
700 MTK_FUNCTION(7, "DBG_MON_B[14]")
701 ),
702 MTK_PIN(
703 PINCTRL_PIN(68, "MSDC2_CMD"),
704 NULL, "mt8516",
705 MTK_EINT_FUNCTION(0, 68),
706 MTK_FUNCTION(0, "GPIO68"),
707 MTK_FUNCTION(1, "MSDC2_CMD"),
708 MTK_FUNCTION(2, "I2S_8CH_DO4"),
709 MTK_FUNCTION(3, "SDA1_0"),
710 MTK_FUNCTION(5, "USB_SDA"),
711 MTK_FUNCTION(6, "I2S3_BCK"),
712 MTK_FUNCTION(7, "DBG_MON_B[15]")
713 ),
714 MTK_PIN(
715 PINCTRL_PIN(69, "MSDC2_CLK"),
716 NULL, "mt8516",
717 MTK_EINT_FUNCTION(0, 69),
718 MTK_FUNCTION(0, "GPIO69"),
719 MTK_FUNCTION(1, "MSDC2_CLK"),
720 MTK_FUNCTION(2, "I2S_8CH_DO3"),
721 MTK_FUNCTION(3, "SCL1_0"),
722 MTK_FUNCTION(5, "USB_SCL"),
723 MTK_FUNCTION(6, "I2S3_LRCK"),
724 MTK_FUNCTION(7, "DBG_MON_B[16]")
725 ),
726 MTK_PIN(
727 PINCTRL_PIN(70, "MSDC2_DAT0"),
728 NULL, "mt8516",
729 MTK_EINT_FUNCTION(0, 70),
730 MTK_FUNCTION(0, "GPIO70"),
731 MTK_FUNCTION(1, "MSDC2_DAT0"),
732 MTK_FUNCTION(2, "I2S_8CH_DO2"),
733 MTK_FUNCTION(5, "UTXD0"),
734 MTK_FUNCTION(6, "I2S3_DO"),
735 MTK_FUNCTION(7, "DBG_MON_B[17]")
736 ),
737 MTK_PIN(
738 PINCTRL_PIN(71, "MSDC2_DAT1"),
739 NULL, "mt8516",
740 MTK_EINT_FUNCTION(0, 71),
741 MTK_FUNCTION(0, "GPIO71"),
742 MTK_FUNCTION(1, "MSDC2_DAT1"),
743 MTK_FUNCTION(2, "I2S_8CH_DO1"),
744 MTK_FUNCTION(3, "PWM_A"),
745 MTK_FUNCTION(4, "I2S3_MCK"),
746 MTK_FUNCTION(5, "URXD0"),
747 MTK_FUNCTION(6, "PWM_B"),
748 MTK_FUNCTION(7, "DBG_MON_B[18]")
749 ),
750 MTK_PIN(
751 PINCTRL_PIN(72, "MSDC2_DAT2"),
752 NULL, "mt8516",
753 MTK_EINT_FUNCTION(0, 72),
754 MTK_FUNCTION(0, "GPIO72"),
755 MTK_FUNCTION(1, "MSDC2_DAT2"),
756 MTK_FUNCTION(2, "I2S_8CH_LRCK"),
757 MTK_FUNCTION(3, "SDA2_0"),
758 MTK_FUNCTION(5, "UTXD1"),
759 MTK_FUNCTION(6, "PWM_C"),
760 MTK_FUNCTION(7, "DBG_MON_B[19]")
761 ),
762 MTK_PIN(
763 PINCTRL_PIN(73, "MSDC2_DAT3"),
764 NULL, "mt8516",
765 MTK_EINT_FUNCTION(0, 73),
766 MTK_FUNCTION(0, "GPIO73"),
767 MTK_FUNCTION(1, "MSDC2_DAT3"),
768 MTK_FUNCTION(2, "I2S_8CH_BCK"),
769 MTK_FUNCTION(3, "SCL2_0"),
770 MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
771 MTK_FUNCTION(5, "URXD1"),
772 MTK_FUNCTION(6, "PWM_A"),
773 MTK_FUNCTION(7, "DBG_MON_B[20]")
774 ),
775 MTK_PIN(
776 PINCTRL_PIN(74, "TDN3"),
777 NULL, "mt8516",
778 MTK_EINT_FUNCTION(0, 74),
779 MTK_FUNCTION(0, "GPIO74"),
780 MTK_FUNCTION(1, "TDN3")
781 ),
782 MTK_PIN(
783 PINCTRL_PIN(75, "TDP3"),
784 NULL, "mt8516",
785 MTK_EINT_FUNCTION(0, 75),
786 MTK_FUNCTION(0, "GPIO75"),
787 MTK_FUNCTION(1, "TDP3")
788 ),
789 MTK_PIN(
790 PINCTRL_PIN(76, "TDN2"),
791 NULL, "mt8516",
792 MTK_EINT_FUNCTION(0, 76),
793 MTK_FUNCTION(0, "GPIO76"),
794 MTK_FUNCTION(1, "TDN2")
795 ),
796 MTK_PIN(
797 PINCTRL_PIN(77, "TDP2"),
798 NULL, "mt8516",
799 MTK_EINT_FUNCTION(0, 77),
800 MTK_FUNCTION(0, "GPIO77"),
801 MTK_FUNCTION(1, "TDP2")
802 ),
803 MTK_PIN(
804 PINCTRL_PIN(78, "TCN"),
805 NULL, "mt8516",
806 MTK_EINT_FUNCTION(0, 78),
807 MTK_FUNCTION(0, "GPIO78"),
808 MTK_FUNCTION(1, "TCN")
809 ),
810 MTK_PIN(
811 PINCTRL_PIN(79, "TCP"),
812 NULL, "mt8516",
813 MTK_EINT_FUNCTION(0, 79),
814 MTK_FUNCTION(0, "GPIO79"),
815 MTK_FUNCTION(1, "TCP")
816 ),
817 MTK_PIN(
818 PINCTRL_PIN(80, "TDN1"),
819 NULL, "mt8516",
820 MTK_EINT_FUNCTION(0, 80),
821 MTK_FUNCTION(0, "GPIO80"),
822 MTK_FUNCTION(1, "TDN1")
823 ),
824 MTK_PIN(
825 PINCTRL_PIN(81, "TDP1"),
826 NULL, "mt8516",
827 MTK_EINT_FUNCTION(0, 81),
828 MTK_FUNCTION(0, "GPIO81"),
829 MTK_FUNCTION(1, "TDP1")
830 ),
831 MTK_PIN(
832 PINCTRL_PIN(82, "TDN0"),
833 NULL, "mt8516",
834 MTK_EINT_FUNCTION(0, 82),
835 MTK_FUNCTION(0, "GPIO82"),
836 MTK_FUNCTION(1, "TDN0")
837 ),
838 MTK_PIN(
839 PINCTRL_PIN(83, "TDP0"),
840 NULL, "mt8516",
841 MTK_EINT_FUNCTION(0, 83),
842 MTK_FUNCTION(0, "GPIO83"),
843 MTK_FUNCTION(1, "TDP0")
844 ),
845 MTK_PIN(
846 PINCTRL_PIN(84, "RDN0"),
847 NULL, "mt8516",
848 MTK_EINT_FUNCTION(0, 84),
849 MTK_FUNCTION(0, "GPIO84"),
850 MTK_FUNCTION(1, "RDN0")
851 ),
852 MTK_PIN(
853 PINCTRL_PIN(85, "RDP0"),
854 NULL, "mt8516",
855 MTK_EINT_FUNCTION(0, 85),
856 MTK_FUNCTION(0, "GPIO85"),
857 MTK_FUNCTION(1, "RDP0")
858 ),
859 MTK_PIN(
860 PINCTRL_PIN(86, "RDN1"),
861 NULL, "mt8516",
862 MTK_EINT_FUNCTION(0, 86),
863 MTK_FUNCTION(0, "GPIO86"),
864 MTK_FUNCTION(1, "RDN1")
865 ),
866 MTK_PIN(
867 PINCTRL_PIN(87, "RDP1"),
868 NULL, "mt8516",
869 MTK_EINT_FUNCTION(0, 87),
870 MTK_FUNCTION(0, "GPIO87"),
871 MTK_FUNCTION(1, "RDP1")
872 ),
873 MTK_PIN(
874 PINCTRL_PIN(88, "RCN"),
875 NULL, "mt8516",
876 MTK_EINT_FUNCTION(0, 88),
877 MTK_FUNCTION(0, "GPIO88"),
878 MTK_FUNCTION(1, "RCN")
879 ),
880 MTK_PIN(
881 PINCTRL_PIN(89, "RCP"),
882 NULL, "mt8516",
883 MTK_EINT_FUNCTION(0, 89),
884 MTK_FUNCTION(0, "GPIO89"),
885 MTK_FUNCTION(1, "RCP")
886 ),
887 MTK_PIN(
888 PINCTRL_PIN(90, "RDN2"),
889 NULL, "mt8516",
890 MTK_EINT_FUNCTION(0, 90),
891 MTK_FUNCTION(0, "GPIO90"),
892 MTK_FUNCTION(1, "RDN2"),
893 MTK_FUNCTION(2, "CMDAT8")
894 ),
895 MTK_PIN(
896 PINCTRL_PIN(91, "RDP2"),
897 NULL, "mt8516",
898 MTK_EINT_FUNCTION(0, 91),
899 MTK_FUNCTION(0, "GPIO91"),
900 MTK_FUNCTION(1, "RDP2"),
901 MTK_FUNCTION(2, "CMDAT9")
902 ),
903 MTK_PIN(
904 PINCTRL_PIN(92, "RDN3"),
905 NULL, "mt8516",
906 MTK_EINT_FUNCTION(0, 92),
907 MTK_FUNCTION(0, "GPIO92"),
908 MTK_FUNCTION(1, "RDN3"),
909 MTK_FUNCTION(2, "CMDAT4")
910 ),
911 MTK_PIN(
912 PINCTRL_PIN(93, "RDP3"),
913 NULL, "mt8516",
914 MTK_EINT_FUNCTION(0, 93),
915 MTK_FUNCTION(0, "GPIO93"),
916 MTK_FUNCTION(1, "RDP3"),
917 MTK_FUNCTION(2, "CMDAT5")
918 ),
919 MTK_PIN(
920 PINCTRL_PIN(94, "RCN_A"),
921 NULL, "mt8516",
922 MTK_EINT_FUNCTION(0, 94),
923 MTK_FUNCTION(0, "GPIO94"),
924 MTK_FUNCTION(1, "RCN_A"),
925 MTK_FUNCTION(2, "CMDAT6")
926 ),
927 MTK_PIN(
928 PINCTRL_PIN(95, "RCP_A"),
929 NULL, "mt8516",
930 MTK_EINT_FUNCTION(0, 95),
931 MTK_FUNCTION(0, "GPIO95"),
932 MTK_FUNCTION(1, "RCP_A"),
933 MTK_FUNCTION(2, "CMDAT7")
934 ),
935 MTK_PIN(
936 PINCTRL_PIN(96, "RDN1_A"),
937 NULL, "mt8516",
938 MTK_EINT_FUNCTION(0, 96),
939 MTK_FUNCTION(0, "GPIO96"),
940 MTK_FUNCTION(1, "RDN1_A"),
941 MTK_FUNCTION(2, "CMDAT2"),
942 MTK_FUNCTION(3, "CMCSD2")
943 ),
944 MTK_PIN(
945 PINCTRL_PIN(97, "RDP1_A"),
946 NULL, "mt8516",
947 MTK_EINT_FUNCTION(0, 97),
948 MTK_FUNCTION(0, "GPIO97"),
949 MTK_FUNCTION(1, "RDP1_A"),
950 MTK_FUNCTION(2, "CMDAT3"),
951 MTK_FUNCTION(3, "CMCSD3")
952 ),
953 MTK_PIN(
954 PINCTRL_PIN(98, "RDN0_A"),
955 NULL, "mt8516",
956 MTK_EINT_FUNCTION(0, 98),
957 MTK_FUNCTION(0, "GPIO98"),
958 MTK_FUNCTION(1, "RDN0_A"),
959 MTK_FUNCTION(2, "CMHSYNC")
960 ),
961 MTK_PIN(
962 PINCTRL_PIN(99, "RDP0_A"),
963 NULL, "mt8516",
964 MTK_EINT_FUNCTION(0, 99),
965 MTK_FUNCTION(0, "GPIO99"),
966 MTK_FUNCTION(1, "RDP0_A"),
967 MTK_FUNCTION(2, "CMVSYNC")
968 ),
969 MTK_PIN(
970 PINCTRL_PIN(100, "CMDAT0"),
971 NULL, "mt8516",
972 MTK_EINT_FUNCTION(0, 100),
973 MTK_FUNCTION(0, "GPIO100"),
974 MTK_FUNCTION(1, "CMDAT0"),
975 MTK_FUNCTION(2, "CMCSD0"),
976 MTK_FUNCTION(3, "ANT_SEL2"),
977 MTK_FUNCTION(5, "TDM_RX_MCK"),
978 MTK_FUNCTION(7, "DBG_MON_B[21]")
979 ),
980 MTK_PIN(
981 PINCTRL_PIN(101, "CMDAT1"),
982 NULL, "mt8516",
983 MTK_EINT_FUNCTION(0, 101),
984 MTK_FUNCTION(0, "GPIO101"),
985 MTK_FUNCTION(1, "CMDAT1"),
986 MTK_FUNCTION(2, "CMCSD1"),
987 MTK_FUNCTION(3, "ANT_SEL3"),
988 MTK_FUNCTION(4, "CMFLASH"),
989 MTK_FUNCTION(5, "TDM_RX_BCK"),
990 MTK_FUNCTION(7, "DBG_MON_B[22]")
991 ),
992 MTK_PIN(
993 PINCTRL_PIN(102, "CMMCLK"),
994 NULL, "mt8516",
995 MTK_EINT_FUNCTION(0, 102),
996 MTK_FUNCTION(0, "GPIO102"),
997 MTK_FUNCTION(1, "CMMCLK"),
998 MTK_FUNCTION(3, "ANT_SEL4"),
999 MTK_FUNCTION(5, "TDM_RX_LRCK"),
1000 MTK_FUNCTION(7, "DBG_MON_B[23]")
1001 ),
1002 MTK_PIN(
1003 PINCTRL_PIN(103, "CMPCLK"),
1004 NULL, "mt8516",
1005 MTK_EINT_FUNCTION(0, 103),
1006 MTK_FUNCTION(0, "GPIO103"),
1007 MTK_FUNCTION(1, "CMPCLK"),
1008 MTK_FUNCTION(2, "CMCSK"),
1009 MTK_FUNCTION(3, "ANT_SEL5"),
1010 MTK_FUNCTION(5, " TDM_RX_DI"),
1011 MTK_FUNCTION(7, "DBG_MON_B[24]")
1012 ),
1013 MTK_PIN(
1014 PINCTRL_PIN(104, "MSDC1_CMD"),
1015 NULL, "mt8516",
1016 MTK_EINT_FUNCTION(0, 104),
1017 MTK_FUNCTION(0, "GPIO104"),
1018 MTK_FUNCTION(1, "MSDC1_CMD"),
1019 MTK_FUNCTION(4, "SQICS"),
1020 MTK_FUNCTION(7, "DBG_MON_B[25]")
1021 ),
1022 MTK_PIN(
1023 PINCTRL_PIN(105, "MSDC1_CLK"),
1024 NULL, "mt8516",
1025 MTK_EINT_FUNCTION(0, 105),
1026 MTK_FUNCTION(0, "GPIO105"),
1027 MTK_FUNCTION(1, "MSDC1_CLK"),
1028 MTK_FUNCTION(4, "SQISO"),
1029 MTK_FUNCTION(7, "DBG_MON_B[26]")
1030 ),
1031 MTK_PIN(
1032 PINCTRL_PIN(106, "MSDC1_DAT0"),
1033 NULL, "mt8516",
1034 MTK_EINT_FUNCTION(0, 106),
1035 MTK_FUNCTION(0, "GPIO106"),
1036 MTK_FUNCTION(1, "MSDC1_DAT0"),
1037 MTK_FUNCTION(4, "SQISI"),
1038 MTK_FUNCTION(7, "DBG_MON_B[27]")
1039 ),
1040 MTK_PIN(
1041 PINCTRL_PIN(107, "MSDC1_DAT1"),
1042 NULL, "mt8516",
1043 MTK_EINT_FUNCTION(0, 107),
1044 MTK_FUNCTION(0, "GPIO107"),
1045 MTK_FUNCTION(1, "MSDC1_DAT1"),
1046 MTK_FUNCTION(4, "SQIWP"),
1047 MTK_FUNCTION(7, "DBG_MON_B[28]")
1048 ),
1049 MTK_PIN(
1050 PINCTRL_PIN(108, "MSDC1_DAT2"),
1051 NULL, "mt8516",
1052 MTK_EINT_FUNCTION(0, 108),
1053 MTK_FUNCTION(0, "GPIO108"),
1054 MTK_FUNCTION(1, "MSDC1_DAT2"),
1055 MTK_FUNCTION(4, "SQIRST"),
1056 MTK_FUNCTION(7, "DBG_MON_B[29]")
1057 ),
1058 MTK_PIN(
1059 PINCTRL_PIN(109, "MSDC1_DAT3"),
1060 NULL, "mt8516",
1061 MTK_EINT_FUNCTION(0, 109),
1062 MTK_FUNCTION(0, "GPIO109"),
1063 MTK_FUNCTION(1, "MSDC1_DAT3"),
1064 MTK_FUNCTION(4, "SQICK"), /* WIP */
1065 MTK_FUNCTION(7, "DBG_MON_B[30]")
1066 ),
1067 MTK_PIN(
1068 PINCTRL_PIN(110, "MSDC0_DAT7"),
1069 NULL, "mt8516",
1070 MTK_EINT_FUNCTION(0, 110),
1071 MTK_FUNCTION(0, "GPIO110"),
1072 MTK_FUNCTION(1, "MSDC0_DAT7"),
1073 MTK_FUNCTION(4, "NLD7")
1074 ),
1075 MTK_PIN(
1076 PINCTRL_PIN(111, "MSDC0_DAT6"),
1077 NULL, "mt8516",
1078 MTK_EINT_FUNCTION(0, 111),
1079 MTK_FUNCTION(0, "GPIO111"),
1080 MTK_FUNCTION(1, "MSDC0_DAT6"),
1081 MTK_FUNCTION(4, "NLD6")
1082 ),
1083 MTK_PIN(
1084 PINCTRL_PIN(112, "MSDC0_DAT5"),
1085 NULL, "mt8516",
1086 MTK_EINT_FUNCTION(0, 112),
1087 MTK_FUNCTION(0, "GPIO112"),
1088 MTK_FUNCTION(1, "MSDC0_DAT5"),
1089 MTK_FUNCTION(4, "NLD4")
1090 ),
1091 MTK_PIN(
1092 PINCTRL_PIN(113, "MSDC0_DAT4"),
1093 NULL, "mt8516",
1094 MTK_EINT_FUNCTION(0, 113),
1095 MTK_FUNCTION(0, "GPIO113"),
1096 MTK_FUNCTION(1, "MSDC0_DAT4"),
1097 MTK_FUNCTION(4, "NLD3")
1098 ),
1099 MTK_PIN(
1100 PINCTRL_PIN(114, "MSDC0_RSTB"),
1101 NULL, "mt8516",
1102 MTK_EINT_FUNCTION(0, 114),
1103 MTK_FUNCTION(0, "GPIO114"),
1104 MTK_FUNCTION(1, "MSDC0_RSTB"),
1105 MTK_FUNCTION(4, "NLD0")
1106 ),
1107 MTK_PIN(
1108 PINCTRL_PIN(115, "MSDC0_CMD"),
1109 NULL, "mt8516",
1110 MTK_EINT_FUNCTION(0, 115),
1111 MTK_FUNCTION(0, "GPIO115"),
1112 MTK_FUNCTION(1, "MSDC0_CMD"),
1113 MTK_FUNCTION(4, "NALE")
1114 ),
1115 MTK_PIN(
1116 PINCTRL_PIN(116, "MSDC0_CLK"),
1117 NULL, "mt8516",
1118 MTK_EINT_FUNCTION(0, 116),
1119 MTK_FUNCTION(0, "GPIO116"),
1120 MTK_FUNCTION(1, "MSDC0_CLK"),
1121 MTK_FUNCTION(4, "NWEB")
1122 ),
1123 MTK_PIN(
1124 PINCTRL_PIN(117, "MSDC0_DAT3"),
1125 NULL, "mt8516",
1126 MTK_EINT_FUNCTION(0, 117),
1127 MTK_FUNCTION(0, "GPIO117"),
1128 MTK_FUNCTION(1, "MSDC0_DAT3"),
1129 MTK_FUNCTION(4, "NLD1")
1130 ),
1131 MTK_PIN(
1132 PINCTRL_PIN(118, "MSDC0_DAT2"),
1133 NULL, "mt8516",
1134 MTK_EINT_FUNCTION(0, 118),
1135 MTK_FUNCTION(0, "GPIO118"),
1136 MTK_FUNCTION(1, "MSDC0_DAT2"),
1137 MTK_FUNCTION(4, "NLD5")
1138 ),
1139 MTK_PIN(
1140 PINCTRL_PIN(119, "MSDC0_DAT1"),
1141 NULL, "mt8516",
1142 MTK_EINT_FUNCTION(0, 119),
1143 MTK_FUNCTION(0, "GPIO119"),
1144 MTK_FUNCTION(1, "MSDC0_DAT1"),
1145 MTK_FUNCTION(4, "NLD8")
1146 ),
1147 MTK_PIN(
1148 PINCTRL_PIN(120, "MSDC0_DAT0"),
1149 NULL, "mt8516",
1150 MTK_EINT_FUNCTION(0, 120),
1151 MTK_FUNCTION(0, "GPIO120"),
1152 MTK_FUNCTION(1, "MSDC0_DAT0"),
1153 MTK_FUNCTION(4, "WATCHDOG"),
1154 MTK_FUNCTION(5, "NLD2")
1155 ),
1156 MTK_PIN(
1157 PINCTRL_PIN(121, "GPIO121"),
1158 NULL, "mt8516",
1159 MTK_EINT_FUNCTION(0, 121),
1160 MTK_FUNCTION(0, "GPIO121")
1161 ),
1162 MTK_PIN(
1163 PINCTRL_PIN(122, "GPIO122"),
1164 NULL, "mt8516",
1165 MTK_EINT_FUNCTION(0, 122),
1166 MTK_FUNCTION(0, "GPIO122")
1167 ),
1168 MTK_PIN(
1169 PINCTRL_PIN(123, "GPIO123"),
1170 NULL, "mt8516",
1171 MTK_EINT_FUNCTION(0, 123),
1172 MTK_FUNCTION(0, "GPIO123")
1173 ),
1174 MTK_PIN(
1175 PINCTRL_PIN(124, "GPIO124"),
1176 NULL, "mt8516",
1177 MTK_EINT_FUNCTION(0, 124),
1178 MTK_FUNCTION(0, "GPIO124")
1179 ),
1180};
1181
1182#endif /* __PINCTRL_MTK_MT8516_H */
diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c
index b59e10852bfb..d3b34e9a7507 100644
--- a/drivers/pinctrl/mediatek/pinctrl-paris.c
+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
@@ -20,12 +20,14 @@
20#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2) 20#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
21#define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3) 21#define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
22#define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4) 22#define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
23#define MTK_PIN_CONFIG_DRV_ADV (PIN_CONFIG_END + 5)
23 24
24static const struct pinconf_generic_params mtk_custom_bindings[] = { 25static const struct pinconf_generic_params mtk_custom_bindings[] = {
25 {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0}, 26 {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
26 {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0}, 27 {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
27 {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1}, 28 {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
28 {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1}, 29 {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
30 {"mediatek,drive-strength-adv", MTK_PIN_CONFIG_DRV_ADV, 2},
29}; 31};
30 32
31#ifdef CONFIG_DEBUG_FS 33#ifdef CONFIG_DEBUG_FS
@@ -34,6 +36,7 @@ static const struct pin_config_item mtk_conf_items[] = {
34 PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true), 36 PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
35 PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true), 37 PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
36 PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true), 38 PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
39 PCONFDUMP(MTK_PIN_CONFIG_DRV_ADV, "drive-strength-adv", NULL, true),
37}; 40};
38#endif 41#endif
39 42
@@ -176,6 +179,15 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
176 return -ENOTSUPP; 179 return -ENOTSUPP;
177 } 180 }
178 break; 181 break;
182 case MTK_PIN_CONFIG_DRV_ADV:
183 if (hw->soc->adv_drive_get) {
184 err = hw->soc->adv_drive_get(hw, desc, &ret);
185 if (err)
186 return err;
187 } else {
188 return -ENOTSUPP;
189 }
190 break;
179 default: 191 default:
180 return -ENOTSUPP; 192 return -ENOTSUPP;
181 } 193 }
@@ -311,6 +323,15 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
311 return -ENOTSUPP; 323 return -ENOTSUPP;
312 } 324 }
313 break; 325 break;
326 case MTK_PIN_CONFIG_DRV_ADV:
327 if (hw->soc->adv_drive_set) {
328 err = hw->soc->adv_drive_set(hw, desc, arg);
329 if (err)
330 return err;
331 } else {
332 return -ENOTSUPP;
333 }
334 break;
314 default: 335 default:
315 err = -ENOTSUPP; 336 err = -ENOTSUPP;
316 } 337 }
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 6689995fa3aa..e18ebb2c78d9 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -930,8 +930,8 @@ static int amd_gpio_probe(struct platform_device *pdev)
930 goto out2; 930 goto out2;
931 } 931 }
932 932
933 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0, 933 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler,
934 KBUILD_MODNAME, gpio_dev); 934 IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
935 if (ret) 935 if (ret)
936 goto out2; 936 goto out2;
937 937
diff --git a/drivers/pinctrl/pinctrl-artpec6.c b/drivers/pinctrl/pinctrl-artpec6.c
index d89dc43c5757..e3239cf926f9 100644
--- a/drivers/pinctrl/pinctrl-artpec6.c
+++ b/drivers/pinctrl/pinctrl-artpec6.c
@@ -688,8 +688,9 @@ static void artpec6_pmx_select_func(struct pinctrl_dev *pctldev,
688 } 688 }
689} 689}
690 690
691int artpec6_pmx_enable(struct pinctrl_dev *pctldev, unsigned int function, 691static int artpec6_pmx_set(struct pinctrl_dev *pctldev,
692 unsigned int group) 692 unsigned int function,
693 unsigned int group)
693{ 694{
694 struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 695 struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
695 696
@@ -702,18 +703,6 @@ int artpec6_pmx_enable(struct pinctrl_dev *pctldev, unsigned int function,
702 return 0; 703 return 0;
703} 704}
704 705
705void artpec6_pmx_disable(struct pinctrl_dev *pctldev, unsigned int function,
706 unsigned int group)
707{
708 struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
709
710 dev_dbg(pmx->dev, "disabling %s function for pin group %s\n",
711 artpec6_pmx_get_fname(pctldev, function),
712 artpec6_get_group_name(pctldev, group));
713
714 artpec6_pmx_select_func(pctldev, function, group, false);
715}
716
717static int artpec6_pmx_request_gpio(struct pinctrl_dev *pctldev, 706static int artpec6_pmx_request_gpio(struct pinctrl_dev *pctldev,
718 struct pinctrl_gpio_range *range, 707 struct pinctrl_gpio_range *range,
719 unsigned int pin) 708 unsigned int pin)
@@ -737,7 +726,7 @@ static const struct pinmux_ops artpec6_pmx_ops = {
737 .get_functions_count = artpec6_pmx_get_functions_count, 726 .get_functions_count = artpec6_pmx_get_functions_count,
738 .get_function_name = artpec6_pmx_get_fname, 727 .get_function_name = artpec6_pmx_get_fname,
739 .get_function_groups = artpec6_pmx_get_fgroups, 728 .get_function_groups = artpec6_pmx_get_fgroups,
740 .set_mux = artpec6_pmx_enable, 729 .set_mux = artpec6_pmx_set,
741 .gpio_request_enable = artpec6_pmx_request_gpio, 730 .gpio_request_enable = artpec6_pmx_request_gpio,
742}; 731};
743 732
diff --git a/drivers/pinctrl/pinctrl-axp209.c b/drivers/pinctrl/pinctrl-axp209.c
index afd0b533c40a..4fcf7262bed9 100644
--- a/drivers/pinctrl/pinctrl-axp209.c
+++ b/drivers/pinctrl/pinctrl-axp209.c
@@ -366,6 +366,8 @@ static int axp20x_build_funcs_groups(struct platform_device *pdev)
366 pctl->funcs[i].groups = devm_kcalloc(&pdev->dev, 366 pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
367 npins, sizeof(char *), 367 npins, sizeof(char *),
368 GFP_KERNEL); 368 GFP_KERNEL);
369 if (!pctl->funcs[i].groups)
370 return -ENOMEM;
369 for (pin = 0; pin < npins; pin++) 371 for (pin = 0; pin < npins; pin++)
370 pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name; 372 pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
371 } 373 }
diff --git a/drivers/pinctrl/pinctrl-bm1880.c b/drivers/pinctrl/pinctrl-bm1880.c
new file mode 100644
index 000000000000..446b07d8fbfc
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-bm1880.c
@@ -0,0 +1,965 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Bitmain BM1880 SoC Pinctrl driver
4 *
5 * Copyright (c) 2019 Linaro Ltd.
6 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
7 */
8
9#include <linux/io.h>
10#include <linux/of.h>
11#include <linux/platform_device.h>
12#include <linux/pinctrl/pinctrl.h>
13#include <linux/pinctrl/pinmux.h>
14#include <linux/pinctrl/pinconf-generic.h>
15#include <linux/slab.h>
16
17#include "core.h"
18#include "pinctrl-utils.h"
19
20#define BM1880_REG_MUX 0x20
21
22/**
23 * struct bm1880_pinctrl - driver data
24 * @base: Pinctrl base address
25 * @pctrl: Pinctrl device
26 * @groups: Pingroups
27 * @ngroups: Number of @groups
28 * @funcs: Pinmux functions
29 * @nfuncs: Number of @funcs
30 */
31struct bm1880_pinctrl {
32 void __iomem *base;
33 struct pinctrl_dev *pctrldev;
34 const struct bm1880_pctrl_group *groups;
35 unsigned int ngroups;
36 const struct bm1880_pinmux_function *funcs;
37 unsigned int nfuncs;
38};
39
40/**
41 * struct bm1880_pctrl_group - pinctrl group
42 * @name: Name of the group
43 * @pins: Array of pins belonging to this group
44 * @npins: Number of @pins
45 */
46struct bm1880_pctrl_group {
47 const char *name;
48 const unsigned int *pins;
49 const unsigned int npins;
50};
51
52/**
53 * struct bm1880_pinmux_function - a pinmux function
54 * @name: Name of the pinmux function.
55 * @groups: List of pingroups for this function.
56 * @ngroups: Number of entries in @groups.
57 * @mux_val: Selector for this function
58 * @mux_mask: Mask for function specific selector
59 * @mux: Offset of function specific mux
60 * @mux_shift: Shift for function specific selector
61 */
62struct bm1880_pinmux_function {
63 const char *name;
64 const char * const *groups;
65 unsigned int ngroups;
66 u32 mux_val;
67 u32 mux_mask;
68 u32 mux;
69 u8 mux_shift;
70};
71
72static const struct pinctrl_pin_desc bm1880_pins[] = {
73 PINCTRL_PIN(0, "MIO0"),
74 PINCTRL_PIN(1, "MIO1"),
75 PINCTRL_PIN(2, "MIO2"),
76 PINCTRL_PIN(3, "MIO3"),
77 PINCTRL_PIN(4, "MIO4"),
78 PINCTRL_PIN(5, "MIO5"),
79 PINCTRL_PIN(6, "MIO6"),
80 PINCTRL_PIN(7, "MIO7"),
81 PINCTRL_PIN(8, "MIO8"),
82 PINCTRL_PIN(9, "MIO9"),
83 PINCTRL_PIN(10, "MIO10"),
84 PINCTRL_PIN(11, "MIO11"),
85 PINCTRL_PIN(12, "MIO12"),
86 PINCTRL_PIN(13, "MIO13"),
87 PINCTRL_PIN(14, "MIO14"),
88 PINCTRL_PIN(15, "MIO15"),
89 PINCTRL_PIN(16, "MIO16"),
90 PINCTRL_PIN(17, "MIO17"),
91 PINCTRL_PIN(18, "MIO18"),
92 PINCTRL_PIN(19, "MIO19"),
93 PINCTRL_PIN(20, "MIO20"),
94 PINCTRL_PIN(21, "MIO21"),
95 PINCTRL_PIN(22, "MIO22"),
96 PINCTRL_PIN(23, "MIO23"),
97 PINCTRL_PIN(24, "MIO24"),
98 PINCTRL_PIN(25, "MIO25"),
99 PINCTRL_PIN(26, "MIO26"),
100 PINCTRL_PIN(27, "MIO27"),
101 PINCTRL_PIN(28, "MIO28"),
102 PINCTRL_PIN(29, "MIO29"),
103 PINCTRL_PIN(30, "MIO30"),
104 PINCTRL_PIN(31, "MIO31"),
105 PINCTRL_PIN(32, "MIO32"),
106 PINCTRL_PIN(33, "MIO33"),
107 PINCTRL_PIN(34, "MIO34"),
108 PINCTRL_PIN(35, "MIO35"),
109 PINCTRL_PIN(36, "MIO36"),
110 PINCTRL_PIN(37, "MIO37"),
111 PINCTRL_PIN(38, "MIO38"),
112 PINCTRL_PIN(39, "MIO39"),
113 PINCTRL_PIN(40, "MIO40"),
114 PINCTRL_PIN(41, "MIO41"),
115 PINCTRL_PIN(42, "MIO42"),
116 PINCTRL_PIN(43, "MIO43"),
117 PINCTRL_PIN(44, "MIO44"),
118 PINCTRL_PIN(45, "MIO45"),
119 PINCTRL_PIN(46, "MIO46"),
120 PINCTRL_PIN(47, "MIO47"),
121 PINCTRL_PIN(48, "MIO48"),
122 PINCTRL_PIN(49, "MIO49"),
123 PINCTRL_PIN(50, "MIO50"),
124 PINCTRL_PIN(51, "MIO51"),
125 PINCTRL_PIN(52, "MIO52"),
126 PINCTRL_PIN(53, "MIO53"),
127 PINCTRL_PIN(54, "MIO54"),
128 PINCTRL_PIN(55, "MIO55"),
129 PINCTRL_PIN(56, "MIO56"),
130 PINCTRL_PIN(57, "MIO57"),
131 PINCTRL_PIN(58, "MIO58"),
132 PINCTRL_PIN(59, "MIO59"),
133 PINCTRL_PIN(60, "MIO60"),
134 PINCTRL_PIN(61, "MIO61"),
135 PINCTRL_PIN(62, "MIO62"),
136 PINCTRL_PIN(63, "MIO63"),
137 PINCTRL_PIN(64, "MIO64"),
138 PINCTRL_PIN(65, "MIO65"),
139 PINCTRL_PIN(66, "MIO66"),
140 PINCTRL_PIN(67, "MIO67"),
141 PINCTRL_PIN(68, "MIO68"),
142 PINCTRL_PIN(69, "MIO69"),
143 PINCTRL_PIN(70, "MIO70"),
144 PINCTRL_PIN(71, "MIO71"),
145 PINCTRL_PIN(72, "MIO72"),
146 PINCTRL_PIN(73, "MIO73"),
147 PINCTRL_PIN(74, "MIO74"),
148 PINCTRL_PIN(75, "MIO75"),
149 PINCTRL_PIN(76, "MIO76"),
150 PINCTRL_PIN(77, "MIO77"),
151 PINCTRL_PIN(78, "MIO78"),
152 PINCTRL_PIN(79, "MIO79"),
153 PINCTRL_PIN(80, "MIO80"),
154 PINCTRL_PIN(81, "MIO81"),
155 PINCTRL_PIN(82, "MIO82"),
156 PINCTRL_PIN(83, "MIO83"),
157 PINCTRL_PIN(84, "MIO84"),
158 PINCTRL_PIN(85, "MIO85"),
159 PINCTRL_PIN(86, "MIO86"),
160 PINCTRL_PIN(87, "MIO87"),
161 PINCTRL_PIN(88, "MIO88"),
162 PINCTRL_PIN(89, "MIO89"),
163 PINCTRL_PIN(90, "MIO90"),
164 PINCTRL_PIN(91, "MIO91"),
165 PINCTRL_PIN(92, "MIO92"),
166 PINCTRL_PIN(93, "MIO93"),
167 PINCTRL_PIN(94, "MIO94"),
168 PINCTRL_PIN(95, "MIO95"),
169 PINCTRL_PIN(96, "MIO96"),
170 PINCTRL_PIN(97, "MIO97"),
171 PINCTRL_PIN(98, "MIO98"),
172 PINCTRL_PIN(99, "MIO99"),
173 PINCTRL_PIN(100, "MIO100"),
174 PINCTRL_PIN(101, "MIO101"),
175 PINCTRL_PIN(102, "MIO102"),
176 PINCTRL_PIN(103, "MIO103"),
177 PINCTRL_PIN(104, "MIO104"),
178 PINCTRL_PIN(105, "MIO105"),
179 PINCTRL_PIN(106, "MIO106"),
180 PINCTRL_PIN(107, "MIO107"),
181 PINCTRL_PIN(108, "MIO108"),
182 PINCTRL_PIN(109, "MIO109"),
183 PINCTRL_PIN(110, "MIO110"),
184 PINCTRL_PIN(111, "MIO111"),
185};
186
187enum bm1880_pinmux_functions {
188 F_nand, F_spi, F_emmc, F_sdio, F_eth0, F_pwm0, F_pwm1, F_pwm2,
189 F_pwm3, F_pwm4, F_pwm5, F_pwm6, F_pwm7, F_pwm8, F_pwm9, F_pwm10,
190 F_pwm11, F_pwm12, F_pwm13, F_pwm14, F_pwm15, F_pwm16, F_pwm17,
191 F_pwm18, F_pwm19, F_pwm20, F_pwm21, F_pwm22, F_pwm23, F_pwm24,
192 F_pwm25, F_pwm26, F_pwm27, F_pwm28, F_pwm29, F_pwm30, F_pwm31,
193 F_pwm32, F_pwm33, F_pwm34, F_pwm35, F_pwm36, F_pwm37, F_i2c0, F_i2c1,
194 F_i2c2, F_i2c3, F_i2c4, F_uart0, F_uart1, F_uart2, F_uart3, F_uart4,
195 F_uart5, F_uart6, F_uart7, F_uart8, F_uart9, F_uart10, F_uart11,
196 F_uart12, F_uart13, F_uart14, F_uart15, F_gpio0, F_gpio1, F_gpio2,
197 F_gpio3, F_gpio4, F_gpio5, F_gpio6, F_gpio7, F_gpio8, F_gpio9, F_gpio10,
198 F_gpio11, F_gpio12, F_gpio13, F_gpio14, F_gpio15, F_gpio16, F_gpio17,
199 F_gpio18, F_gpio19, F_gpio20, F_gpio21, F_gpio22, F_gpio23, F_gpio24,
200 F_gpio25, F_gpio26, F_gpio27, F_gpio28, F_gpio29, F_gpio30, F_gpio31,
201 F_gpio32, F_gpio33, F_gpio34, F_gpio35, F_gpio36, F_gpio37, F_gpio38,
202 F_gpio39, F_gpio40, F_gpio41, F_gpio42, F_gpio43, F_gpio44, F_gpio45,
203 F_gpio46, F_gpio47, F_gpio48, F_gpio49, F_gpio50, F_gpio51, F_gpio52,
204 F_gpio53, F_gpio54, F_gpio55, F_gpio56, F_gpio57, F_gpio58, F_gpio59,
205 F_gpio60, F_gpio61, F_gpio62, F_gpio63, F_gpio64, F_gpio65, F_gpio66,
206 F_gpio67, F_eth1, F_i2s0, F_i2s0_mclkin, F_i2s1, F_i2s1_mclkin, F_spi0,
207 F_max
208};
209
210static const unsigned int nand_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
211 10, 11, 12, 13, 14, 15, 16 };
212static const unsigned int spi_pins[] = { 0, 1, 8, 10, 11, 12, 13 };
213static const unsigned int emmc_pins[] = { 2, 3, 4, 5, 6, 7, 9, 14, 15, 16 };
214static const unsigned int sdio_pins[] = { 17, 18, 19, 20, 21, 22, 23, 24,
215 25, 26 };
216static const unsigned int eth0_pins[] = { 27, 28, 29, 30, 31, 32, 33, 34, 35,
217 36, 37, 38, 39, 40, 41, 42 };
218static const unsigned int pwm0_pins[] = { 29 };
219static const unsigned int pwm1_pins[] = { 30 };
220static const unsigned int pwm2_pins[] = { 34 };
221static const unsigned int pwm3_pins[] = { 35 };
222static const unsigned int pwm4_pins[] = { 43 };
223static const unsigned int pwm5_pins[] = { 44 };
224static const unsigned int pwm6_pins[] = { 45 };
225static const unsigned int pwm7_pins[] = { 46 };
226static const unsigned int pwm8_pins[] = { 47 };
227static const unsigned int pwm9_pins[] = { 48 };
228static const unsigned int pwm10_pins[] = { 49 };
229static const unsigned int pwm11_pins[] = { 50 };
230static const unsigned int pwm12_pins[] = { 51 };
231static const unsigned int pwm13_pins[] = { 52 };
232static const unsigned int pwm14_pins[] = { 53 };
233static const unsigned int pwm15_pins[] = { 54 };
234static const unsigned int pwm16_pins[] = { 55 };
235static const unsigned int pwm17_pins[] = { 56 };
236static const unsigned int pwm18_pins[] = { 57 };
237static const unsigned int pwm19_pins[] = { 58 };
238static const unsigned int pwm20_pins[] = { 59 };
239static const unsigned int pwm21_pins[] = { 60 };
240static const unsigned int pwm22_pins[] = { 61 };
241static const unsigned int pwm23_pins[] = { 62 };
242static const unsigned int pwm24_pins[] = { 97 };
243static const unsigned int pwm25_pins[] = { 98 };
244static const unsigned int pwm26_pins[] = { 99 };
245static const unsigned int pwm27_pins[] = { 100 };
246static const unsigned int pwm28_pins[] = { 101 };
247static const unsigned int pwm29_pins[] = { 102 };
248static const unsigned int pwm30_pins[] = { 103 };
249static const unsigned int pwm31_pins[] = { 104 };
250static const unsigned int pwm32_pins[] = { 105 };
251static const unsigned int pwm33_pins[] = { 106 };
252static const unsigned int pwm34_pins[] = { 107 };
253static const unsigned int pwm35_pins[] = { 108 };
254static const unsigned int pwm36_pins[] = { 109 };
255static const unsigned int pwm37_pins[] = { 110 };
256static const unsigned int i2c0_pins[] = { 63, 64 };
257static const unsigned int i2c1_pins[] = { 65, 66 };
258static const unsigned int i2c2_pins[] = { 67, 68 };
259static const unsigned int i2c3_pins[] = { 69, 70 };
260static const unsigned int i2c4_pins[] = { 71, 72 };
261static const unsigned int uart0_pins[] = { 73, 74 };
262static const unsigned int uart1_pins[] = { 75, 76 };
263static const unsigned int uart2_pins[] = { 77, 78 };
264static const unsigned int uart3_pins[] = { 79, 80 };
265static const unsigned int uart4_pins[] = { 81, 82 };
266static const unsigned int uart5_pins[] = { 83, 84 };
267static const unsigned int uart6_pins[] = { 85, 86 };
268static const unsigned int uart7_pins[] = { 87, 88 };
269static const unsigned int uart8_pins[] = { 89, 90 };
270static const unsigned int uart9_pins[] = { 91, 92 };
271static const unsigned int uart10_pins[] = { 93, 94 };
272static const unsigned int uart11_pins[] = { 95, 96 };
273static const unsigned int uart12_pins[] = { 73, 74, 75, 76 };
274static const unsigned int uart13_pins[] = { 77, 78, 83, 84 };
275static const unsigned int uart14_pins[] = { 79, 80, 85, 86 };
276static const unsigned int uart15_pins[] = { 81, 82, 87, 88 };
277static const unsigned int gpio0_pins[] = { 97 };
278static const unsigned int gpio1_pins[] = { 98 };
279static const unsigned int gpio2_pins[] = { 99 };
280static const unsigned int gpio3_pins[] = { 100 };
281static const unsigned int gpio4_pins[] = { 101 };
282static const unsigned int gpio5_pins[] = { 102 };
283static const unsigned int gpio6_pins[] = { 103 };
284static const unsigned int gpio7_pins[] = { 104 };
285static const unsigned int gpio8_pins[] = { 105 };
286static const unsigned int gpio9_pins[] = { 106 };
287static const unsigned int gpio10_pins[] = { 107 };
288static const unsigned int gpio11_pins[] = { 108 };
289static const unsigned int gpio12_pins[] = { 109 };
290static const unsigned int gpio13_pins[] = { 110 };
291static const unsigned int gpio14_pins[] = { 43 };
292static const unsigned int gpio15_pins[] = { 44 };
293static const unsigned int gpio16_pins[] = { 45 };
294static const unsigned int gpio17_pins[] = { 46 };
295static const unsigned int gpio18_pins[] = { 47 };
296static const unsigned int gpio19_pins[] = { 48 };
297static const unsigned int gpio20_pins[] = { 49 };
298static const unsigned int gpio21_pins[] = { 50 };
299static const unsigned int gpio22_pins[] = { 51 };
300static const unsigned int gpio23_pins[] = { 52 };
301static const unsigned int gpio24_pins[] = { 53 };
302static const unsigned int gpio25_pins[] = { 54 };
303static const unsigned int gpio26_pins[] = { 55 };
304static const unsigned int gpio27_pins[] = { 56 };
305static const unsigned int gpio28_pins[] = { 57 };
306static const unsigned int gpio29_pins[] = { 58 };
307static const unsigned int gpio30_pins[] = { 59 };
308static const unsigned int gpio31_pins[] = { 60 };
309static const unsigned int gpio32_pins[] = { 61 };
310static const unsigned int gpio33_pins[] = { 62 };
311static const unsigned int gpio34_pins[] = { 63 };
312static const unsigned int gpio35_pins[] = { 64 };
313static const unsigned int gpio36_pins[] = { 65 };
314static const unsigned int gpio37_pins[] = { 66 };
315static const unsigned int gpio38_pins[] = { 67 };
316static const unsigned int gpio39_pins[] = { 68 };
317static const unsigned int gpio40_pins[] = { 69 };
318static const unsigned int gpio41_pins[] = { 70 };
319static const unsigned int gpio42_pins[] = { 71 };
320static const unsigned int gpio43_pins[] = { 72 };
321static const unsigned int gpio44_pins[] = { 73 };
322static const unsigned int gpio45_pins[] = { 74 };
323static const unsigned int gpio46_pins[] = { 75 };
324static const unsigned int gpio47_pins[] = { 76 };
325static const unsigned int gpio48_pins[] = { 77 };
326static const unsigned int gpio49_pins[] = { 78 };
327static const unsigned int gpio50_pins[] = { 79 };
328static const unsigned int gpio51_pins[] = { 80 };
329static const unsigned int gpio52_pins[] = { 81 };
330static const unsigned int gpio53_pins[] = { 82 };
331static const unsigned int gpio54_pins[] = { 83 };
332static const unsigned int gpio55_pins[] = { 84 };
333static const unsigned int gpio56_pins[] = { 85 };
334static const unsigned int gpio57_pins[] = { 86 };
335static const unsigned int gpio58_pins[] = { 87 };
336static const unsigned int gpio59_pins[] = { 88 };
337static const unsigned int gpio60_pins[] = { 89 };
338static const unsigned int gpio61_pins[] = { 90 };
339static const unsigned int gpio62_pins[] = { 91 };
340static const unsigned int gpio63_pins[] = { 92 };
341static const unsigned int gpio64_pins[] = { 93 };
342static const unsigned int gpio65_pins[] = { 94 };
343static const unsigned int gpio66_pins[] = { 95 };
344static const unsigned int gpio67_pins[] = { 96 };
345static const unsigned int eth1_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51,
346 52, 53, 54, 55, 56, 57, 58 };
347static const unsigned int i2s0_pins[] = { 87, 88, 89, 90, 91 };
348static const unsigned int i2s0_mclkin_pins[] = { 97 };
349static const unsigned int i2s1_pins[] = { 92, 93, 94, 95, 96 };
350static const unsigned int i2s1_mclkin_pins[] = { 98 };
351static const unsigned int spi0_pins[] = { 59, 60, 61, 62 };
352
353#define BM1880_PINCTRL_GRP(nm) \
354 { \
355 .name = #nm "_grp", \
356 .pins = nm ## _pins, \
357 .npins = ARRAY_SIZE(nm ## _pins), \
358 }
359
360static const struct bm1880_pctrl_group bm1880_pctrl_groups[] = {
361 BM1880_PINCTRL_GRP(nand),
362 BM1880_PINCTRL_GRP(spi),
363 BM1880_PINCTRL_GRP(emmc),
364 BM1880_PINCTRL_GRP(sdio),
365 BM1880_PINCTRL_GRP(eth0),
366 BM1880_PINCTRL_GRP(pwm0),
367 BM1880_PINCTRL_GRP(pwm1),
368 BM1880_PINCTRL_GRP(pwm2),
369 BM1880_PINCTRL_GRP(pwm3),
370 BM1880_PINCTRL_GRP(pwm4),
371 BM1880_PINCTRL_GRP(pwm5),
372 BM1880_PINCTRL_GRP(pwm6),
373 BM1880_PINCTRL_GRP(pwm7),
374 BM1880_PINCTRL_GRP(pwm8),
375 BM1880_PINCTRL_GRP(pwm9),
376 BM1880_PINCTRL_GRP(pwm10),
377 BM1880_PINCTRL_GRP(pwm11),
378 BM1880_PINCTRL_GRP(pwm12),
379 BM1880_PINCTRL_GRP(pwm13),
380 BM1880_PINCTRL_GRP(pwm14),
381 BM1880_PINCTRL_GRP(pwm15),
382 BM1880_PINCTRL_GRP(pwm16),
383 BM1880_PINCTRL_GRP(pwm17),
384 BM1880_PINCTRL_GRP(pwm18),
385 BM1880_PINCTRL_GRP(pwm19),
386 BM1880_PINCTRL_GRP(pwm20),
387 BM1880_PINCTRL_GRP(pwm21),
388 BM1880_PINCTRL_GRP(pwm22),
389 BM1880_PINCTRL_GRP(pwm23),
390 BM1880_PINCTRL_GRP(pwm24),
391 BM1880_PINCTRL_GRP(pwm25),
392 BM1880_PINCTRL_GRP(pwm26),
393 BM1880_PINCTRL_GRP(pwm27),
394 BM1880_PINCTRL_GRP(pwm28),
395 BM1880_PINCTRL_GRP(pwm29),
396 BM1880_PINCTRL_GRP(pwm30),
397 BM1880_PINCTRL_GRP(pwm31),
398 BM1880_PINCTRL_GRP(pwm32),
399 BM1880_PINCTRL_GRP(pwm33),
400 BM1880_PINCTRL_GRP(pwm34),
401 BM1880_PINCTRL_GRP(pwm35),
402 BM1880_PINCTRL_GRP(pwm36),
403 BM1880_PINCTRL_GRP(i2c0),
404 BM1880_PINCTRL_GRP(i2c1),
405 BM1880_PINCTRL_GRP(i2c2),
406 BM1880_PINCTRL_GRP(i2c3),
407 BM1880_PINCTRL_GRP(i2c4),
408 BM1880_PINCTRL_GRP(uart0),
409 BM1880_PINCTRL_GRP(uart1),
410 BM1880_PINCTRL_GRP(uart2),
411 BM1880_PINCTRL_GRP(uart3),
412 BM1880_PINCTRL_GRP(uart4),
413 BM1880_PINCTRL_GRP(uart5),
414 BM1880_PINCTRL_GRP(uart6),
415 BM1880_PINCTRL_GRP(uart7),
416 BM1880_PINCTRL_GRP(uart8),
417 BM1880_PINCTRL_GRP(uart9),
418 BM1880_PINCTRL_GRP(uart10),
419 BM1880_PINCTRL_GRP(uart11),
420 BM1880_PINCTRL_GRP(uart12),
421 BM1880_PINCTRL_GRP(uart13),
422 BM1880_PINCTRL_GRP(uart14),
423 BM1880_PINCTRL_GRP(uart15),
424 BM1880_PINCTRL_GRP(gpio0),
425 BM1880_PINCTRL_GRP(gpio1),
426 BM1880_PINCTRL_GRP(gpio2),
427 BM1880_PINCTRL_GRP(gpio3),
428 BM1880_PINCTRL_GRP(gpio4),
429 BM1880_PINCTRL_GRP(gpio5),
430 BM1880_PINCTRL_GRP(gpio6),
431 BM1880_PINCTRL_GRP(gpio7),
432 BM1880_PINCTRL_GRP(gpio8),
433 BM1880_PINCTRL_GRP(gpio9),
434 BM1880_PINCTRL_GRP(gpio10),
435 BM1880_PINCTRL_GRP(gpio11),
436 BM1880_PINCTRL_GRP(gpio12),
437 BM1880_PINCTRL_GRP(gpio13),
438 BM1880_PINCTRL_GRP(gpio14),
439 BM1880_PINCTRL_GRP(gpio15),
440 BM1880_PINCTRL_GRP(gpio16),
441 BM1880_PINCTRL_GRP(gpio17),
442 BM1880_PINCTRL_GRP(gpio18),
443 BM1880_PINCTRL_GRP(gpio19),
444 BM1880_PINCTRL_GRP(gpio20),
445 BM1880_PINCTRL_GRP(gpio21),
446 BM1880_PINCTRL_GRP(gpio22),
447 BM1880_PINCTRL_GRP(gpio23),
448 BM1880_PINCTRL_GRP(gpio24),
449 BM1880_PINCTRL_GRP(gpio25),
450 BM1880_PINCTRL_GRP(gpio26),
451 BM1880_PINCTRL_GRP(gpio27),
452 BM1880_PINCTRL_GRP(gpio28),
453 BM1880_PINCTRL_GRP(gpio29),
454 BM1880_PINCTRL_GRP(gpio30),
455 BM1880_PINCTRL_GRP(gpio31),
456 BM1880_PINCTRL_GRP(gpio32),
457 BM1880_PINCTRL_GRP(gpio33),
458 BM1880_PINCTRL_GRP(gpio34),
459 BM1880_PINCTRL_GRP(gpio35),
460 BM1880_PINCTRL_GRP(gpio36),
461 BM1880_PINCTRL_GRP(gpio37),
462 BM1880_PINCTRL_GRP(gpio38),
463 BM1880_PINCTRL_GRP(gpio39),
464 BM1880_PINCTRL_GRP(gpio40),
465 BM1880_PINCTRL_GRP(gpio41),
466 BM1880_PINCTRL_GRP(gpio42),
467 BM1880_PINCTRL_GRP(gpio43),
468 BM1880_PINCTRL_GRP(gpio44),
469 BM1880_PINCTRL_GRP(gpio45),
470 BM1880_PINCTRL_GRP(gpio46),
471 BM1880_PINCTRL_GRP(gpio47),
472 BM1880_PINCTRL_GRP(gpio48),
473 BM1880_PINCTRL_GRP(gpio49),
474 BM1880_PINCTRL_GRP(gpio50),
475 BM1880_PINCTRL_GRP(gpio51),
476 BM1880_PINCTRL_GRP(gpio52),
477 BM1880_PINCTRL_GRP(gpio53),
478 BM1880_PINCTRL_GRP(gpio54),
479 BM1880_PINCTRL_GRP(gpio55),
480 BM1880_PINCTRL_GRP(gpio56),
481 BM1880_PINCTRL_GRP(gpio57),
482 BM1880_PINCTRL_GRP(gpio58),
483 BM1880_PINCTRL_GRP(gpio59),
484 BM1880_PINCTRL_GRP(gpio60),
485 BM1880_PINCTRL_GRP(gpio61),
486 BM1880_PINCTRL_GRP(gpio62),
487 BM1880_PINCTRL_GRP(gpio63),
488 BM1880_PINCTRL_GRP(gpio64),
489 BM1880_PINCTRL_GRP(gpio65),
490 BM1880_PINCTRL_GRP(gpio66),
491 BM1880_PINCTRL_GRP(gpio67),
492 BM1880_PINCTRL_GRP(eth1),
493 BM1880_PINCTRL_GRP(i2s0),
494 BM1880_PINCTRL_GRP(i2s0_mclkin),
495 BM1880_PINCTRL_GRP(i2s1),
496 BM1880_PINCTRL_GRP(i2s1_mclkin),
497 BM1880_PINCTRL_GRP(spi0),
498};
499
500static const char * const nand_group[] = { "nand_grp" };
501static const char * const spi_group[] = { "spi_grp" };
502static const char * const emmc_group[] = { "emmc_grp" };
503static const char * const sdio_group[] = { "sdio_grp" };
504static const char * const eth0_group[] = { "eth0_grp" };
505static const char * const pwm0_group[] = { "pwm0_grp" };
506static const char * const pwm1_group[] = { "pwm1_grp" };
507static const char * const pwm2_group[] = { "pwm2_grp" };
508static const char * const pwm3_group[] = { "pwm3_grp" };
509static const char * const pwm4_group[] = { "pwm4_grp" };
510static const char * const pwm5_group[] = { "pwm5_grp" };
511static const char * const pwm6_group[] = { "pwm6_grp" };
512static const char * const pwm7_group[] = { "pwm7_grp" };
513static const char * const pwm8_group[] = { "pwm8_grp" };
514static const char * const pwm9_group[] = { "pwm9_grp" };
515static const char * const pwm10_group[] = { "pwm10_grp" };
516static const char * const pwm11_group[] = { "pwm11_grp" };
517static const char * const pwm12_group[] = { "pwm12_grp" };
518static const char * const pwm13_group[] = { "pwm13_grp" };
519static const char * const pwm14_group[] = { "pwm14_grp" };
520static const char * const pwm15_group[] = { "pwm15_grp" };
521static const char * const pwm16_group[] = { "pwm16_grp" };
522static const char * const pwm17_group[] = { "pwm17_grp" };
523static const char * const pwm18_group[] = { "pwm18_grp" };
524static const char * const pwm19_group[] = { "pwm19_grp" };
525static const char * const pwm20_group[] = { "pwm20_grp" };
526static const char * const pwm21_group[] = { "pwm21_grp" };
527static const char * const pwm22_group[] = { "pwm22_grp" };
528static const char * const pwm23_group[] = { "pwm23_grp" };
529static const char * const pwm24_group[] = { "pwm24_grp" };
530static const char * const pwm25_group[] = { "pwm25_grp" };
531static const char * const pwm26_group[] = { "pwm26_grp" };
532static const char * const pwm27_group[] = { "pwm27_grp" };
533static const char * const pwm28_group[] = { "pwm28_grp" };
534static const char * const pwm29_group[] = { "pwm29_grp" };
535static const char * const pwm30_group[] = { "pwm30_grp" };
536static const char * const pwm31_group[] = { "pwm31_grp" };
537static const char * const pwm32_group[] = { "pwm32_grp" };
538static const char * const pwm33_group[] = { "pwm33_grp" };
539static const char * const pwm34_group[] = { "pwm34_grp" };
540static const char * const pwm35_group[] = { "pwm35_grp" };
541static const char * const pwm36_group[] = { "pwm36_grp" };
542static const char * const pwm37_group[] = { "pwm37_grp" };
543static const char * const i2c0_group[] = { "i2c0_grp" };
544static const char * const i2c1_group[] = { "i2c1_grp" };
545static const char * const i2c2_group[] = { "i2c2_grp" };
546static const char * const i2c3_group[] = { "i2c3_grp" };
547static const char * const i2c4_group[] = { "i2c4_grp" };
548static const char * const uart0_group[] = { "uart0_grp" };
549static const char * const uart1_group[] = { "uart1_grp" };
550static const char * const uart2_group[] = { "uart2_grp" };
551static const char * const uart3_group[] = { "uart3_grp" };
552static const char * const uart4_group[] = { "uart4_grp" };
553static const char * const uart5_group[] = { "uart5_grp" };
554static const char * const uart6_group[] = { "uart6_grp" };
555static const char * const uart7_group[] = { "uart7_grp" };
556static const char * const uart8_group[] = { "uart8_grp" };
557static const char * const uart9_group[] = { "uart9_grp" };
558static const char * const uart10_group[] = { "uart10_grp" };
559static const char * const uart11_group[] = { "uart11_grp" };
560static const char * const uart12_group[] = { "uart12_grp" };
561static const char * const uart13_group[] = { "uart13_grp" };
562static const char * const uart14_group[] = { "uart14_grp" };
563static const char * const uart15_group[] = { "uart15_grp" };
564static const char * const gpio0_group[] = { "gpio0_grp" };
565static const char * const gpio1_group[] = { "gpio1_grp" };
566static const char * const gpio2_group[] = { "gpio2_grp" };
567static const char * const gpio3_group[] = { "gpio3_grp" };
568static const char * const gpio4_group[] = { "gpio4_grp" };
569static const char * const gpio5_group[] = { "gpio5_grp" };
570static const char * const gpio6_group[] = { "gpio6_grp" };
571static const char * const gpio7_group[] = { "gpio7_grp" };
572static const char * const gpio8_group[] = { "gpio8_grp" };
573static const char * const gpio9_group[] = { "gpio9_grp" };
574static const char * const gpio10_group[] = { "gpio10_grp" };
575static const char * const gpio11_group[] = { "gpio11_grp" };
576static const char * const gpio12_group[] = { "gpio12_grp" };
577static const char * const gpio13_group[] = { "gpio13_grp" };
578static const char * const gpio14_group[] = { "gpio14_grp" };
579static const char * const gpio15_group[] = { "gpio15_grp" };
580static const char * const gpio16_group[] = { "gpio16_grp" };
581static const char * const gpio17_group[] = { "gpio17_grp" };
582static const char * const gpio18_group[] = { "gpio18_grp" };
583static const char * const gpio19_group[] = { "gpio19_grp" };
584static const char * const gpio20_group[] = { "gpio20_grp" };
585static const char * const gpio21_group[] = { "gpio21_grp" };
586static const char * const gpio22_group[] = { "gpio22_grp" };
587static const char * const gpio23_group[] = { "gpio23_grp" };
588static const char * const gpio24_group[] = { "gpio24_grp" };
589static const char * const gpio25_group[] = { "gpio25_grp" };
590static const char * const gpio26_group[] = { "gpio26_grp" };
591static const char * const gpio27_group[] = { "gpio27_grp" };
592static const char * const gpio28_group[] = { "gpio28_grp" };
593static const char * const gpio29_group[] = { "gpio29_grp" };
594static const char * const gpio30_group[] = { "gpio30_grp" };
595static const char * const gpio31_group[] = { "gpio31_grp" };
596static const char * const gpio32_group[] = { "gpio32_grp" };
597static const char * const gpio33_group[] = { "gpio33_grp" };
598static const char * const gpio34_group[] = { "gpio34_grp" };
599static const char * const gpio35_group[] = { "gpio35_grp" };
600static const char * const gpio36_group[] = { "gpio36_grp" };
601static const char * const gpio37_group[] = { "gpio37_grp" };
602static const char * const gpio38_group[] = { "gpio38_grp" };
603static const char * const gpio39_group[] = { "gpio39_grp" };
604static const char * const gpio40_group[] = { "gpio40_grp" };
605static const char * const gpio41_group[] = { "gpio41_grp" };
606static const char * const gpio42_group[] = { "gpio42_grp" };
607static const char * const gpio43_group[] = { "gpio43_grp" };
608static const char * const gpio44_group[] = { "gpio44_grp" };
609static const char * const gpio45_group[] = { "gpio45_grp" };
610static const char * const gpio46_group[] = { "gpio46_grp" };
611static const char * const gpio47_group[] = { "gpio47_grp" };
612static const char * const gpio48_group[] = { "gpio48_grp" };
613static const char * const gpio49_group[] = { "gpio49_grp" };
614static const char * const gpio50_group[] = { "gpio50_grp" };
615static const char * const gpio51_group[] = { "gpio51_grp" };
616static const char * const gpio52_group[] = { "gpio52_grp" };
617static const char * const gpio53_group[] = { "gpio53_grp" };
618static const char * const gpio54_group[] = { "gpio54_grp" };
619static const char * const gpio55_group[] = { "gpio55_grp" };
620static const char * const gpio56_group[] = { "gpio56_grp" };
621static const char * const gpio57_group[] = { "gpio57_grp" };
622static const char * const gpio58_group[] = { "gpio58_grp" };
623static const char * const gpio59_group[] = { "gpio59_grp" };
624static const char * const gpio60_group[] = { "gpio60_grp" };
625static const char * const gpio61_group[] = { "gpio61_grp" };
626static const char * const gpio62_group[] = { "gpio62_grp" };
627static const char * const gpio63_group[] = { "gpio63_grp" };
628static const char * const gpio64_group[] = { "gpio64_grp" };
629static const char * const gpio65_group[] = { "gpio65_grp" };
630static const char * const gpio66_group[] = { "gpio66_grp" };
631static const char * const gpio67_group[] = { "gpio67_grp" };
632static const char * const eth1_group[] = { "eth1_grp" };
633static const char * const i2s0_group[] = { "i2s0_grp" };
634static const char * const i2s0_mclkin_group[] = { "i2s0_mclkin_grp" };
635static const char * const i2s1_group[] = { "i2s1_grp" };
636static const char * const i2s1_mclkin_group[] = { "i2s1_mclkin_grp" };
637static const char * const spi0_group[] = { "spi0_grp" };
638
639#define BM1880_PINMUX_FUNCTION(fname, mval, mask) \
640 [F_##fname] = { \
641 .name = #fname, \
642 .groups = fname##_group, \
643 .ngroups = ARRAY_SIZE(fname##_group), \
644 .mux_val = mval, \
645 .mux_mask = mask, \
646 }
647
648#define BM1880_PINMUX_FUNCTION_MUX(fname, mval, mask, offset, shift)\
649 [F_##fname] = { \
650 .name = #fname, \
651 .groups = fname##_group, \
652 .ngroups = ARRAY_SIZE(fname##_group), \
653 .mux_val = mval, \
654 .mux_mask = mask, \
655 .mux = offset, \
656 .mux_shift = shift, \
657 }
658
659static const struct bm1880_pinmux_function bm1880_pmux_functions[] = {
660 BM1880_PINMUX_FUNCTION(nand, 2, 0x03),
661 BM1880_PINMUX_FUNCTION(spi, 0, 0x03),
662 BM1880_PINMUX_FUNCTION(emmc, 1, 0x03),
663 BM1880_PINMUX_FUNCTION(sdio, 0, 0x03),
664 BM1880_PINMUX_FUNCTION(eth0, 0, 0x03),
665 BM1880_PINMUX_FUNCTION_MUX(pwm0, 2, 0x0F, 0x50, 0x00),
666 BM1880_PINMUX_FUNCTION_MUX(pwm1, 2, 0x0F, 0x50, 0x04),
667 BM1880_PINMUX_FUNCTION_MUX(pwm2, 2, 0x0F, 0x50, 0x08),
668 BM1880_PINMUX_FUNCTION_MUX(pwm3, 2, 0x0F, 0x50, 0x0C),
669 BM1880_PINMUX_FUNCTION_MUX(pwm4, 2, 0x0F, 0x50, 0x10),
670 BM1880_PINMUX_FUNCTION_MUX(pwm5, 2, 0x0F, 0x50, 0x14),
671 BM1880_PINMUX_FUNCTION_MUX(pwm6, 2, 0x0F, 0x50, 0x18),
672 BM1880_PINMUX_FUNCTION_MUX(pwm7, 2, 0x0F, 0x50, 0x1C),
673 BM1880_PINMUX_FUNCTION_MUX(pwm8, 2, 0x0F, 0x54, 0x00),
674 BM1880_PINMUX_FUNCTION_MUX(pwm9, 2, 0x0F, 0x54, 0x04),
675 BM1880_PINMUX_FUNCTION_MUX(pwm10, 2, 0x0F, 0x54, 0x08),
676 BM1880_PINMUX_FUNCTION_MUX(pwm11, 2, 0x0F, 0x54, 0x0C),
677 BM1880_PINMUX_FUNCTION_MUX(pwm12, 2, 0x0F, 0x54, 0x10),
678 BM1880_PINMUX_FUNCTION_MUX(pwm13, 2, 0x0F, 0x54, 0x14),
679 BM1880_PINMUX_FUNCTION_MUX(pwm14, 2, 0x0F, 0x54, 0x18),
680 BM1880_PINMUX_FUNCTION_MUX(pwm15, 2, 0x0F, 0x54, 0x1C),
681 BM1880_PINMUX_FUNCTION_MUX(pwm16, 2, 0x0F, 0x58, 0x00),
682 BM1880_PINMUX_FUNCTION_MUX(pwm17, 2, 0x0F, 0x58, 0x04),
683 BM1880_PINMUX_FUNCTION_MUX(pwm18, 2, 0x0F, 0x58, 0x08),
684 BM1880_PINMUX_FUNCTION_MUX(pwm19, 2, 0x0F, 0x58, 0x0C),
685 BM1880_PINMUX_FUNCTION_MUX(pwm20, 2, 0x0F, 0x58, 0x10),
686 BM1880_PINMUX_FUNCTION_MUX(pwm21, 2, 0x0F, 0x58, 0x14),
687 BM1880_PINMUX_FUNCTION_MUX(pwm22, 2, 0x0F, 0x58, 0x18),
688 BM1880_PINMUX_FUNCTION_MUX(pwm23, 2, 0x0F, 0x58, 0x1C),
689 BM1880_PINMUX_FUNCTION_MUX(pwm24, 2, 0x0F, 0x5C, 0x00),
690 BM1880_PINMUX_FUNCTION_MUX(pwm25, 2, 0x0F, 0x5C, 0x04),
691 BM1880_PINMUX_FUNCTION_MUX(pwm26, 2, 0x0F, 0x5C, 0x08),
692 BM1880_PINMUX_FUNCTION_MUX(pwm27, 2, 0x0F, 0x5C, 0x0C),
693 BM1880_PINMUX_FUNCTION_MUX(pwm28, 2, 0x0F, 0x5C, 0x10),
694 BM1880_PINMUX_FUNCTION_MUX(pwm29, 2, 0x0F, 0x5C, 0x14),
695 BM1880_PINMUX_FUNCTION_MUX(pwm30, 2, 0x0F, 0x5C, 0x18),
696 BM1880_PINMUX_FUNCTION_MUX(pwm31, 2, 0x0F, 0x5C, 0x1C),
697 BM1880_PINMUX_FUNCTION_MUX(pwm32, 2, 0x0F, 0x60, 0x00),
698 BM1880_PINMUX_FUNCTION_MUX(pwm33, 2, 0x0F, 0x60, 0x04),
699 BM1880_PINMUX_FUNCTION_MUX(pwm34, 2, 0x0F, 0x60, 0x08),
700 BM1880_PINMUX_FUNCTION_MUX(pwm35, 2, 0x0F, 0x60, 0x0C),
701 BM1880_PINMUX_FUNCTION_MUX(pwm36, 2, 0x0F, 0x60, 0x10),
702 BM1880_PINMUX_FUNCTION_MUX(pwm37, 2, 0x0F, 0x60, 0x1C),
703 BM1880_PINMUX_FUNCTION(i2c0, 1, 0x03),
704 BM1880_PINMUX_FUNCTION(i2c1, 1, 0x03),
705 BM1880_PINMUX_FUNCTION(i2c2, 1, 0x03),
706 BM1880_PINMUX_FUNCTION(i2c3, 1, 0x03),
707 BM1880_PINMUX_FUNCTION(i2c4, 1, 0x03),
708 BM1880_PINMUX_FUNCTION(uart0, 1, 0x03),
709 BM1880_PINMUX_FUNCTION(uart1, 1, 0x03),
710 BM1880_PINMUX_FUNCTION(uart2, 1, 0x03),
711 BM1880_PINMUX_FUNCTION(uart3, 1, 0x03),
712 BM1880_PINMUX_FUNCTION(uart4, 1, 0x03),
713 BM1880_PINMUX_FUNCTION(uart5, 1, 0x03),
714 BM1880_PINMUX_FUNCTION(uart6, 1, 0x03),
715 BM1880_PINMUX_FUNCTION(uart7, 1, 0x03),
716 BM1880_PINMUX_FUNCTION(uart8, 1, 0x03),
717 BM1880_PINMUX_FUNCTION(uart9, 1, 0x03),
718 BM1880_PINMUX_FUNCTION(uart10, 1, 0x03),
719 BM1880_PINMUX_FUNCTION(uart11, 1, 0x03),
720 BM1880_PINMUX_FUNCTION(uart12, 3, 0x03),
721 BM1880_PINMUX_FUNCTION(uart13, 3, 0x03),
722 BM1880_PINMUX_FUNCTION(uart14, 3, 0x03),
723 BM1880_PINMUX_FUNCTION(uart15, 3, 0x03),
724 BM1880_PINMUX_FUNCTION_MUX(gpio0, 0, 0x03, 0x4E0, 0x14),
725 BM1880_PINMUX_FUNCTION_MUX(gpio1, 0, 0x03, 0x4E4, 0x04),
726 BM1880_PINMUX_FUNCTION_MUX(gpio2, 0, 0x03, 0x4E4, 0x14),
727 BM1880_PINMUX_FUNCTION_MUX(gpio3, 0, 0x03, 0x4E8, 0x04),
728 BM1880_PINMUX_FUNCTION_MUX(gpio4, 0, 0x03, 0x4E8, 0x14),
729 BM1880_PINMUX_FUNCTION_MUX(gpio5, 0, 0x03, 0x4EC, 0x04),
730 BM1880_PINMUX_FUNCTION_MUX(gpio6, 0, 0x03, 0x4EC, 0x14),
731 BM1880_PINMUX_FUNCTION_MUX(gpio7, 0, 0x03, 0x4F0, 0x04),
732 BM1880_PINMUX_FUNCTION_MUX(gpio8, 0, 0x03, 0x4F0, 0x14),
733 BM1880_PINMUX_FUNCTION_MUX(gpio9, 0, 0x03, 0x4F4, 0x04),
734 BM1880_PINMUX_FUNCTION_MUX(gpio10, 0, 0x03, 0x4F4, 0x14),
735 BM1880_PINMUX_FUNCTION_MUX(gpio11, 0, 0x03, 0x4F8, 0x04),
736 BM1880_PINMUX_FUNCTION_MUX(gpio12, 1, 0x03, 0x4F8, 0x14),
737 BM1880_PINMUX_FUNCTION_MUX(gpio13, 1, 0x03, 0x4FC, 0x04),
738 BM1880_PINMUX_FUNCTION_MUX(gpio14, 0, 0x03, 0x474, 0x14),
739 BM1880_PINMUX_FUNCTION_MUX(gpio15, 0, 0x03, 0x478, 0x04),
740 BM1880_PINMUX_FUNCTION_MUX(gpio16, 0, 0x03, 0x478, 0x14),
741 BM1880_PINMUX_FUNCTION_MUX(gpio17, 0, 0x03, 0x47C, 0x04),
742 BM1880_PINMUX_FUNCTION_MUX(gpio18, 0, 0x03, 0x47C, 0x14),
743 BM1880_PINMUX_FUNCTION_MUX(gpio19, 0, 0x03, 0x480, 0x04),
744 BM1880_PINMUX_FUNCTION_MUX(gpio20, 0, 0x03, 0x480, 0x14),
745 BM1880_PINMUX_FUNCTION_MUX(gpio21, 0, 0x03, 0x484, 0x04),
746 BM1880_PINMUX_FUNCTION_MUX(gpio22, 0, 0x03, 0x484, 0x14),
747 BM1880_PINMUX_FUNCTION_MUX(gpio23, 0, 0x03, 0x488, 0x04),
748 BM1880_PINMUX_FUNCTION_MUX(gpio24, 0, 0x03, 0x488, 0x14),
749 BM1880_PINMUX_FUNCTION_MUX(gpio25, 0, 0x03, 0x48C, 0x04),
750 BM1880_PINMUX_FUNCTION_MUX(gpio26, 0, 0x03, 0x48C, 0x14),
751 BM1880_PINMUX_FUNCTION_MUX(gpio27, 0, 0x03, 0x490, 0x04),
752 BM1880_PINMUX_FUNCTION_MUX(gpio28, 0, 0x03, 0x490, 0x14),
753 BM1880_PINMUX_FUNCTION_MUX(gpio29, 0, 0x03, 0x494, 0x04),
754 BM1880_PINMUX_FUNCTION_MUX(gpio30, 0, 0x03, 0x494, 0x14),
755 BM1880_PINMUX_FUNCTION_MUX(gpio31, 0, 0x03, 0x498, 0x04),
756 BM1880_PINMUX_FUNCTION_MUX(gpio32, 0, 0x03, 0x498, 0x14),
757 BM1880_PINMUX_FUNCTION_MUX(gpio33, 0, 0x03, 0x49C, 0x04),
758 BM1880_PINMUX_FUNCTION_MUX(gpio34, 0, 0x03, 0x49C, 0x14),
759 BM1880_PINMUX_FUNCTION_MUX(gpio35, 0, 0x03, 0x4A0, 0x04),
760 BM1880_PINMUX_FUNCTION_MUX(gpio36, 0, 0x03, 0x4A0, 0x14),
761 BM1880_PINMUX_FUNCTION_MUX(gpio37, 0, 0x03, 0x4A4, 0x04),
762 BM1880_PINMUX_FUNCTION_MUX(gpio38, 0, 0x03, 0x4A4, 0x14),
763 BM1880_PINMUX_FUNCTION_MUX(gpio39, 0, 0x03, 0x4A8, 0x04),
764 BM1880_PINMUX_FUNCTION_MUX(gpio40, 0, 0x03, 0x4A8, 0x14),
765 BM1880_PINMUX_FUNCTION_MUX(gpio41, 0, 0x03, 0x4AC, 0x04),
766 BM1880_PINMUX_FUNCTION_MUX(gpio42, 0, 0x03, 0x4AC, 0x14),
767 BM1880_PINMUX_FUNCTION_MUX(gpio43, 0, 0x03, 0x4B0, 0x04),
768 BM1880_PINMUX_FUNCTION_MUX(gpio44, 0, 0x03, 0x4B0, 0x14),
769 BM1880_PINMUX_FUNCTION_MUX(gpio45, 0, 0x03, 0x4B4, 0x04),
770 BM1880_PINMUX_FUNCTION_MUX(gpio46, 0, 0x03, 0x4B4, 0x14),
771 BM1880_PINMUX_FUNCTION_MUX(gpio47, 0, 0x03, 0x4B8, 0x04),
772 BM1880_PINMUX_FUNCTION_MUX(gpio48, 0, 0x03, 0x4B8, 0x14),
773 BM1880_PINMUX_FUNCTION_MUX(gpio49, 0, 0x03, 0x4BC, 0x04),
774 BM1880_PINMUX_FUNCTION_MUX(gpio50, 0, 0x03, 0x4BC, 0x14),
775 BM1880_PINMUX_FUNCTION_MUX(gpio51, 0, 0x03, 0x4C0, 0x04),
776 BM1880_PINMUX_FUNCTION_MUX(gpio52, 0, 0x03, 0x4C0, 0x14),
777 BM1880_PINMUX_FUNCTION_MUX(gpio53, 0, 0x03, 0x4C4, 0x04),
778 BM1880_PINMUX_FUNCTION_MUX(gpio54, 0, 0x03, 0x4C4, 0x14),
779 BM1880_PINMUX_FUNCTION_MUX(gpio55, 0, 0x03, 0x4C8, 0x04),
780 BM1880_PINMUX_FUNCTION_MUX(gpio56, 0, 0x03, 0x4C8, 0x14),
781 BM1880_PINMUX_FUNCTION_MUX(gpio57, 0, 0x03, 0x4CC, 0x04),
782 BM1880_PINMUX_FUNCTION_MUX(gpio58, 0, 0x03, 0x4CC, 0x14),
783 BM1880_PINMUX_FUNCTION_MUX(gpio59, 0, 0x03, 0x4D0, 0x04),
784 BM1880_PINMUX_FUNCTION_MUX(gpio60, 0, 0x03, 0x4D0, 0x14),
785 BM1880_PINMUX_FUNCTION_MUX(gpio61, 0, 0x03, 0x4D4, 0x04),
786 BM1880_PINMUX_FUNCTION_MUX(gpio62, 0, 0x03, 0x4D4, 0x14),
787 BM1880_PINMUX_FUNCTION_MUX(gpio63, 0, 0x03, 0x4D8, 0x04),
788 BM1880_PINMUX_FUNCTION_MUX(gpio64, 0, 0x03, 0x4D8, 0x14),
789 BM1880_PINMUX_FUNCTION_MUX(gpio65, 0, 0x03, 0x4DC, 0x04),
790 BM1880_PINMUX_FUNCTION_MUX(gpio66, 0, 0x03, 0x4DC, 0x14),
791 BM1880_PINMUX_FUNCTION_MUX(gpio67, 0, 0x03, 0x4E0, 0x04),
792 BM1880_PINMUX_FUNCTION(eth1, 1, 0x03),
793 BM1880_PINMUX_FUNCTION(i2s0, 2, 0x03),
794 BM1880_PINMUX_FUNCTION(i2s0_mclkin, 1, 0x03),
795 BM1880_PINMUX_FUNCTION(i2s1, 2, 0x03),
796 BM1880_PINMUX_FUNCTION(i2s1_mclkin, 1, 0x03),
797 BM1880_PINMUX_FUNCTION(spi0, 1, 0x03),
798};
799
800static int bm1880_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
801{
802 struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
803
804 return pctrl->ngroups;
805}
806
807static const char *bm1880_pctrl_get_group_name(struct pinctrl_dev *pctldev,
808 unsigned int selector)
809{
810 struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
811
812 return pctrl->groups[selector].name;
813}
814
815static int bm1880_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
816 unsigned int selector,
817 const unsigned int **pins,
818 unsigned int *num_pins)
819{
820 struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
821
822 *pins = pctrl->groups[selector].pins;
823 *num_pins = pctrl->groups[selector].npins;
824
825 return 0;
826}
827
828static const struct pinctrl_ops bm1880_pctrl_ops = {
829 .get_groups_count = bm1880_pctrl_get_groups_count,
830 .get_group_name = bm1880_pctrl_get_group_name,
831 .get_group_pins = bm1880_pctrl_get_group_pins,
832 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
833 .dt_free_map = pinctrl_utils_free_map,
834};
835
836/* pinmux */
837static int bm1880_pmux_get_functions_count(struct pinctrl_dev *pctldev)
838{
839 struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
840
841 return pctrl->nfuncs;
842}
843
844static const char *bm1880_pmux_get_function_name(struct pinctrl_dev *pctldev,
845 unsigned int selector)
846{
847 struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
848
849 return pctrl->funcs[selector].name;
850}
851
852static int bm1880_pmux_get_function_groups(struct pinctrl_dev *pctldev,
853 unsigned int selector,
854 const char * const **groups,
855 unsigned * const num_groups)
856{
857 struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
858
859 *groups = pctrl->funcs[selector].groups;
860 *num_groups = pctrl->funcs[selector].ngroups;
861 return 0;
862}
863
864static int bm1880_pinmux_set_mux(struct pinctrl_dev *pctldev,
865 unsigned int function,
866 unsigned int group)
867{
868 struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
869 const struct bm1880_pctrl_group *pgrp = &pctrl->groups[group];
870 const struct bm1880_pinmux_function *func = &pctrl->funcs[function];
871 int i;
872
873 if (func->mux) {
874 u32 regval = readl_relaxed(pctrl->base + BM1880_REG_MUX +
875 func->mux);
876
877 regval &= ~(func->mux_mask << func->mux_shift);
878 regval |= func->mux_val << func->mux_shift;
879 writel_relaxed(regval, pctrl->base + BM1880_REG_MUX +
880 func->mux);
881 } else {
882 for (i = 0; i < pgrp->npins; i++) {
883 unsigned int pin = pgrp->pins[i];
884 u32 offset = (pin >> 1) << 2;
885 u32 mux_offset = ((!((pin + 1) & 1) << 4) + 4);
886 u32 regval = readl_relaxed(pctrl->base +
887 BM1880_REG_MUX + offset);
888
889 regval &= ~(func->mux_mask << mux_offset);
890 regval |= func->mux_val << mux_offset;
891
892 writel_relaxed(regval, pctrl->base +
893 BM1880_REG_MUX + offset);
894 }
895 }
896
897 return 0;
898}
899
900static const struct pinmux_ops bm1880_pinmux_ops = {
901 .get_functions_count = bm1880_pmux_get_functions_count,
902 .get_function_name = bm1880_pmux_get_function_name,
903 .get_function_groups = bm1880_pmux_get_function_groups,
904 .set_mux = bm1880_pinmux_set_mux,
905};
906
907static struct pinctrl_desc bm1880_desc = {
908 .name = "bm1880_pinctrl",
909 .pins = bm1880_pins,
910 .npins = ARRAY_SIZE(bm1880_pins),
911 .pctlops = &bm1880_pctrl_ops,
912 .pmxops = &bm1880_pinmux_ops,
913 .owner = THIS_MODULE,
914};
915
916static int bm1880_pinctrl_probe(struct platform_device *pdev)
917
918{
919 struct resource *res;
920 struct bm1880_pinctrl *pctrl;
921
922 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
923 if (!pctrl)
924 return -ENOMEM;
925
926 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
927 pctrl->base = devm_ioremap_resource(&pdev->dev, res);
928 if (IS_ERR(pctrl->base))
929 return PTR_ERR(pctrl->base);
930
931 pctrl->groups = bm1880_pctrl_groups;
932 pctrl->ngroups = ARRAY_SIZE(bm1880_pctrl_groups);
933 pctrl->funcs = bm1880_pmux_functions;
934 pctrl->nfuncs = ARRAY_SIZE(bm1880_pmux_functions);
935
936 pctrl->pctrldev = devm_pinctrl_register(&pdev->dev, &bm1880_desc,
937 pctrl);
938 if (IS_ERR(pctrl->pctrldev))
939 return PTR_ERR(pctrl->pctrldev);
940
941 platform_set_drvdata(pdev, pctrl);
942
943 dev_info(&pdev->dev, "BM1880 pinctrl driver initialized\n");
944
945 return 0;
946}
947
948static const struct of_device_id bm1880_pinctrl_of_match[] = {
949 { .compatible = "bitmain,bm1880-pinctrl" },
950 { }
951};
952
953static struct platform_driver bm1880_pinctrl_driver = {
954 .driver = {
955 .name = "pinctrl-bm1880",
956 .of_match_table = of_match_ptr(bm1880_pinctrl_of_match),
957 },
958 .probe = bm1880_pinctrl_probe,
959};
960
961static int __init bm1880_pinctrl_init(void)
962{
963 return platform_driver_register(&bm1880_pinctrl_driver);
964}
965arch_initcall(bm1880_pinctrl_init);
diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c
index 5d7a8514def9..fd9d6f026d70 100644
--- a/drivers/pinctrl/pinctrl-mcp23s08.c
+++ b/drivers/pinctrl/pinctrl-mcp23s08.c
@@ -266,7 +266,6 @@ static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
266 status = (data & BIT(pin)) ? 1 : 0; 266 status = (data & BIT(pin)) ? 1 : 0;
267 break; 267 break;
268 default: 268 default:
269 dev_err(mcp->dev, "Invalid config param %04x\n", param);
270 return -ENOTSUPP; 269 return -ENOTSUPP;
271 } 270 }
272 271
@@ -293,7 +292,7 @@ static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
293 ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg); 292 ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg);
294 break; 293 break;
295 default: 294 default:
296 dev_err(mcp->dev, "Invalid config param %04x\n", param); 295 dev_dbg(mcp->dev, "Invalid config param %04x\n", param);
297 return -ENOTSUPP; 296 return -ENOTSUPP;
298 } 297 }
299 } 298 }
diff --git a/drivers/pinctrl/pinctrl-pistachio.c b/drivers/pinctrl/pinctrl-pistachio.c
index aa5f949ef219..5b0678f310e5 100644
--- a/drivers/pinctrl/pinctrl-pistachio.c
+++ b/drivers/pinctrl/pinctrl-pistachio.c
@@ -1367,6 +1367,7 @@ static int pistachio_gpio_register(struct pistachio_pinctrl *pctl)
1367 if (!of_find_property(child, "gpio-controller", NULL)) { 1367 if (!of_find_property(child, "gpio-controller", NULL)) {
1368 dev_err(pctl->dev, 1368 dev_err(pctl->dev,
1369 "No gpio-controller property for bank %u\n", i); 1369 "No gpio-controller property for bank %u\n", i);
1370 of_node_put(child);
1370 ret = -ENODEV; 1371 ret = -ENODEV;
1371 goto err; 1372 goto err;
1372 } 1373 }
@@ -1374,6 +1375,7 @@ static int pistachio_gpio_register(struct pistachio_pinctrl *pctl)
1374 irq = irq_of_parse_and_map(child, 0); 1375 irq = irq_of_parse_and_map(child, 0);
1375 if (irq < 0) { 1376 if (irq < 0) {
1376 dev_err(pctl->dev, "No IRQ for bank %u: %d\n", i, irq); 1377 dev_err(pctl->dev, "No IRQ for bank %u: %d\n", i, irq);
1378 of_node_put(child);
1377 ret = irq; 1379 ret = irq;
1378 goto err; 1380 goto err;
1379 } 1381 }
diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/pinctrl-rza1.c
index 9cfe9d0520ac..021e37b7689e 100644
--- a/drivers/pinctrl/pinctrl-rza1.c
+++ b/drivers/pinctrl/pinctrl-rza1.c
@@ -620,14 +620,7 @@ static void rza1_pin_reset(struct rza1_port *port, unsigned int pin)
620static inline int rza1_pin_get_direction(struct rza1_port *port, 620static inline int rza1_pin_get_direction(struct rza1_port *port,
621 unsigned int pin) 621 unsigned int pin)
622{ 622{
623 unsigned long irqflags; 623 return !!rza1_get_bit(port, RZA1_PM_REG, pin);
624 int input;
625
626 spin_lock_irqsave(&port->lock, irqflags);
627 input = rza1_get_bit(port, RZA1_PM_REG, pin);
628 spin_unlock_irqrestore(&port->lock, irqflags);
629
630 return !!input;
631} 624}
632 625
633/** 626/**
@@ -671,14 +664,7 @@ static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin,
671 664
672static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin) 665static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin)
673{ 666{
674 unsigned long irqflags; 667 return rza1_get_bit(port, RZA1_PPR_REG, pin);
675 int val;
676
677 spin_lock_irqsave(&port->lock, irqflags);
678 val = rza1_get_bit(port, RZA1_PPR_REG, pin);
679 spin_unlock_irqrestore(&port->lock, irqflags);
680
681 return val;
682} 668}
683 669
684/** 670/**
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index e66af93f2cbf..195b442a2343 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -1170,7 +1170,7 @@ static int st_pctl_dt_parse_groups(struct device_node *np,
1170 struct property *pp; 1170 struct property *pp;
1171 struct st_pinconf *conf; 1171 struct st_pinconf *conf;
1172 struct device_node *pins; 1172 struct device_node *pins;
1173 int i = 0, npins = 0, nr_props; 1173 int i = 0, npins = 0, nr_props, ret = 0;
1174 1174
1175 pins = of_get_child_by_name(np, "st,pins"); 1175 pins = of_get_child_by_name(np, "st,pins");
1176 if (!pins) 1176 if (!pins)
@@ -1185,7 +1185,8 @@ static int st_pctl_dt_parse_groups(struct device_node *np,
1185 npins++; 1185 npins++;
1186 } else { 1186 } else {
1187 pr_warn("Invalid st,pins in %pOFn node\n", np); 1187 pr_warn("Invalid st,pins in %pOFn node\n", np);
1188 return -EINVAL; 1188 ret = -EINVAL;
1189 goto out_put_node;
1189 } 1190 }
1190 } 1191 }
1191 1192
@@ -1195,8 +1196,10 @@ static int st_pctl_dt_parse_groups(struct device_node *np,
1195 grp->pin_conf = devm_kcalloc(info->dev, 1196 grp->pin_conf = devm_kcalloc(info->dev,
1196 npins, sizeof(*conf), GFP_KERNEL); 1197 npins, sizeof(*conf), GFP_KERNEL);
1197 1198
1198 if (!grp->pins || !grp->pin_conf) 1199 if (!grp->pins || !grp->pin_conf) {
1199 return -ENOMEM; 1200 ret = -ENOMEM;
1201 goto out_put_node;
1202 }
1200 1203
1201 /* <bank offset mux direction rt_type rt_delay rt_clk> */ 1204 /* <bank offset mux direction rt_type rt_delay rt_clk> */
1202 for_each_property_of_node(pins, pp) { 1205 for_each_property_of_node(pins, pp) {
@@ -1229,9 +1232,11 @@ static int st_pctl_dt_parse_groups(struct device_node *np,
1229 } 1232 }
1230 i++; 1233 i++;
1231 } 1234 }
1235
1236out_put_node:
1232 of_node_put(pins); 1237 of_node_put(pins);
1233 1238
1234 return 0; 1239 return ret;
1235} 1240}
1236 1241
1237static int st_pctl_parse_functions(struct device_node *np, 1242static int st_pctl_parse_functions(struct device_node *np,
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c
index 44c6b753f692..85ddf49a5188 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c
@@ -71,6 +71,7 @@ s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata,
71 } 71 }
72 72
73 clk_base = of_iomap(np, 0); 73 clk_base = of_iomap(np, 0);
74 of_node_put(np);
74 if (!clk_base) { 75 if (!clk_base) {
75 pr_err("%s: failed to map clock registers\n", __func__); 76 pr_err("%s: failed to map clock registers\n", __func__);
76 return ERR_PTR(-EINVAL); 77 return ERR_PTR(-EINVAL);
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index e941ba60d4b7..2dd716b016a3 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -3,201 +3,183 @@
3# Renesas SH and SH Mobile PINCTRL drivers 3# Renesas SH and SH Mobile PINCTRL drivers
4# 4#
5 5
6if ARCH_RENESAS || SUPERH
7
8config PINCTRL_SH_PFC 6config PINCTRL_SH_PFC
7 bool "Renesas SoC pin control support" if COMPILE_TEST && !(ARCH_RENESAS || SUPERH)
8 default y if ARCH_RENESAS || SUPERH
9 select PINMUX 9 select PINMUX
10 select PINCONF 10 select PINCONF
11 select GENERIC_PINCONF 11 select GENERIC_PINCONF
12 def_bool y 12 select PINCTRL_PFC_EMEV2 if ARCH_EMEV2
13 select PINCTRL_PFC_R8A73A4 if ARCH_R8A73A4
14 select PINCTRL_PFC_R8A7740 if ARCH_R8A7740
15 select PINCTRL_PFC_R8A7743 if ARCH_R8A7743
16 select PINCTRL_PFC_R8A7744 if ARCH_R8A7744
17 select PINCTRL_PFC_R8A7745 if ARCH_R8A7745
18 select PINCTRL_PFC_R8A77470 if ARCH_R8A77470
19 select PINCTRL_PFC_R8A774A1 if ARCH_R8A774A1
20 select PINCTRL_PFC_R8A774C0 if ARCH_R8A774C0
21 select PINCTRL_PFC_R8A7778 if ARCH_R8A7778
22 select PINCTRL_PFC_R8A7779 if ARCH_R8A7779
23 select PINCTRL_PFC_R8A7790 if ARCH_R8A7790
24 select PINCTRL_PFC_R8A7791 if ARCH_R8A7791
25 select PINCTRL_PFC_R8A7792 if ARCH_R8A7792
26 select PINCTRL_PFC_R8A7793 if ARCH_R8A7793
27 select PINCTRL_PFC_R8A7794 if ARCH_R8A7794
28 select PINCTRL_PFC_R8A7795 if ARCH_R8A7795
29 select PINCTRL_PFC_R8A7796 if ARCH_R8A7796
30 select PINCTRL_PFC_R8A77965 if ARCH_R8A77965
31 select PINCTRL_PFC_R8A77970 if ARCH_R8A77970
32 select PINCTRL_PFC_R8A77980 if ARCH_R8A77980
33 select PINCTRL_PFC_R8A77990 if ARCH_R8A77990
34 select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
35 select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
36 select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
37 select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
38 select PINCTRL_PFC_SH73A0 if ARCH_SH73A0
39 select PINCTRL_PFC_SH7720 if CPU_SUBTYPE_SH7720
40 select PINCTRL_PFC_SH7722 if CPU_SUBTYPE_SH7722
41 select PINCTRL_PFC_SH7723 if CPU_SUBTYPE_SH7723
42 select PINCTRL_PFC_SH7724 if CPU_SUBTYPE_SH7724
43 select PINCTRL_PFC_SH7734 if CPU_SUBTYPE_SH7734
44 select PINCTRL_PFC_SH7757 if CPU_SUBTYPE_SH7757
45 select PINCTRL_PFC_SH7785 if CPU_SUBTYPE_SH7785
46 select PINCTRL_PFC_SH7786 if CPU_SUBTYPE_SH7786
47 select PINCTRL_PFC_SHX3 if CPU_SUBTYPE_SHX3
13 help 48 help
14 This enables pin control drivers for SH and SH Mobile platforms 49 This enables pin control drivers for Renesas SuperH and ARM platforms
15 50
16config PINCTRL_SH_PFC_GPIO 51config PINCTRL_SH_PFC_GPIO
17 select GPIOLIB 52 select GPIOLIB
18 select PINCTRL_SH_PFC
19 bool 53 bool
20 help 54 help
21 This enables pin control and GPIO drivers for SH/SH Mobile platforms 55 This enables pin control and GPIO drivers for SH/SH Mobile platforms
22 56
57config PINCTRL_SH_FUNC_GPIO
58 select PINCTRL_SH_PFC_GPIO
59 bool
60 help
61 This enables legacy function GPIOs for SH platforms
62
23config PINCTRL_PFC_EMEV2 63config PINCTRL_PFC_EMEV2
24 def_bool y 64 bool "Emma Mobile AV2 pin control support" if COMPILE_TEST
25 depends on ARCH_EMEV2
26 select PINCTRL_SH_PFC
27 65
28config PINCTRL_PFC_R8A73A4 66config PINCTRL_PFC_R8A73A4
29 def_bool y 67 bool "R-Mobile APE6 pin control support" if COMPILE_TEST
30 depends on ARCH_R8A73A4
31 select PINCTRL_SH_PFC_GPIO 68 select PINCTRL_SH_PFC_GPIO
32 69
33config PINCTRL_PFC_R8A7740 70config PINCTRL_PFC_R8A7740
34 def_bool y 71 bool "R-Mobile A1 pin control support" if COMPILE_TEST
35 depends on ARCH_R8A7740
36 select PINCTRL_SH_PFC_GPIO 72 select PINCTRL_SH_PFC_GPIO
37 73
38config PINCTRL_PFC_R8A7743 74config PINCTRL_PFC_R8A7743
39 def_bool y 75 bool "RZ/G1M pin control support" if COMPILE_TEST
40 depends on ARCH_R8A7743
41 select PINCTRL_SH_PFC
42 76
43config PINCTRL_PFC_R8A7744 77config PINCTRL_PFC_R8A7744
44 def_bool y 78 bool "RZ/G1N pin control support" if COMPILE_TEST
45 depends on ARCH_R8A7744
46 select PINCTRL_SH_PFC
47 79
48config PINCTRL_PFC_R8A7745 80config PINCTRL_PFC_R8A7745
49 def_bool y 81 bool "RZ/G1E pin control support" if COMPILE_TEST
50 depends on ARCH_R8A7745
51 select PINCTRL_SH_PFC
52 82
53config PINCTRL_PFC_R8A77470 83config PINCTRL_PFC_R8A77470
54 def_bool y 84 bool "RZ/G1C pin control support" if COMPILE_TEST
55 depends on ARCH_R8A77470
56 select PINCTRL_SH_PFC
57 85
58config PINCTRL_PFC_R8A774A1 86config PINCTRL_PFC_R8A774A1
59 def_bool y 87 bool "RZ/G2M pin control support" if COMPILE_TEST
60 depends on ARCH_R8A774A1
61 select PINCTRL_SH_PFC
62 88
63config PINCTRL_PFC_R8A774C0 89config PINCTRL_PFC_R8A774C0
64 def_bool y 90 bool "RZ/G2E pin control support" if COMPILE_TEST
65 depends on ARCH_R8A774C0
66 select PINCTRL_SH_PFC
67 91
68config PINCTRL_PFC_R8A7778 92config PINCTRL_PFC_R8A7778
69 def_bool y 93 bool "R-Car M1A pin control support" if COMPILE_TEST
70 depends on ARCH_R8A7778
71 select PINCTRL_SH_PFC
72 94
73config PINCTRL_PFC_R8A7779 95config PINCTRL_PFC_R8A7779
74 def_bool y 96 bool "R-Car H1 pin control support" if COMPILE_TEST
75 depends on ARCH_R8A7779
76 select PINCTRL_SH_PFC
77 97
78config PINCTRL_PFC_R8A7790 98config PINCTRL_PFC_R8A7790
79 def_bool y 99 bool "R-Car H2 pin control support" if COMPILE_TEST
80 depends on ARCH_R8A7790
81 select PINCTRL_SH_PFC
82 100
83config PINCTRL_PFC_R8A7791 101config PINCTRL_PFC_R8A7791
84 def_bool y 102 bool "R-Car M2-W pin control support" if COMPILE_TEST
85 depends on ARCH_R8A7791
86 select PINCTRL_SH_PFC
87 103
88config PINCTRL_PFC_R8A7792 104config PINCTRL_PFC_R8A7792
89 def_bool y 105 bool "R-Car V2H pin control support" if COMPILE_TEST
90 depends on ARCH_R8A7792
91 select PINCTRL_SH_PFC
92 106
93config PINCTRL_PFC_R8A7793 107config PINCTRL_PFC_R8A7793
94 def_bool y 108 bool "R-Car M2-N pin control support" if COMPILE_TEST
95 depends on ARCH_R8A7793
96 select PINCTRL_SH_PFC
97 109
98config PINCTRL_PFC_R8A7794 110config PINCTRL_PFC_R8A7794
99 def_bool y 111 bool "R-Car E2 pin control support" if COMPILE_TEST
100 depends on ARCH_R8A7794
101 select PINCTRL_SH_PFC
102 112
103config PINCTRL_PFC_R8A7795 113config PINCTRL_PFC_R8A7795
104 def_bool y 114 bool "R-Car H3 pin control support" if COMPILE_TEST
105 depends on ARCH_R8A7795
106 select PINCTRL_SH_PFC
107 115
108config PINCTRL_PFC_R8A7796 116config PINCTRL_PFC_R8A7796
109 def_bool y 117 bool "R-Car M3-W pin control support" if COMPILE_TEST
110 depends on ARCH_R8A7796
111 select PINCTRL_SH_PFC
112 118
113config PINCTRL_PFC_R8A77965 119config PINCTRL_PFC_R8A77965
114 def_bool y 120 bool "R-Car M3-N pin control support" if COMPILE_TEST
115 depends on ARCH_R8A77965
116 select PINCTRL_SH_PFC
117 121
118config PINCTRL_PFC_R8A77970 122config PINCTRL_PFC_R8A77970
119 def_bool y 123 bool "R-Car V3M pin control support" if COMPILE_TEST
120 depends on ARCH_R8A77970
121 select PINCTRL_SH_PFC
122 124
123config PINCTRL_PFC_R8A77980 125config PINCTRL_PFC_R8A77980
124 def_bool y 126 bool "R-Car V3H pin control support" if COMPILE_TEST
125 depends on ARCH_R8A77980
126 select PINCTRL_SH_PFC
127 127
128config PINCTRL_PFC_R8A77990 128config PINCTRL_PFC_R8A77990
129 def_bool y 129 bool "R-Car E3 pin control support" if COMPILE_TEST
130 depends on ARCH_R8A77990
131 select PINCTRL_SH_PFC
132 130
133config PINCTRL_PFC_R8A77995 131config PINCTRL_PFC_R8A77995
134 def_bool y 132 bool "R-Car D3 pin control support" if COMPILE_TEST
135 depends on ARCH_R8A77995
136 select PINCTRL_SH_PFC
137 133
138config PINCTRL_PFC_SH7203 134config PINCTRL_PFC_SH7203
139 def_bool y 135 bool "SH7203 pin control support" if COMPILE_TEST
140 depends on CPU_SUBTYPE_SH7203 136 select PINCTRL_SH_FUNC_GPIO
141 select PINCTRL_SH_PFC_GPIO
142 137
143config PINCTRL_PFC_SH7264 138config PINCTRL_PFC_SH7264
144 def_bool y 139 bool "SH7264 pin control support" if COMPILE_TEST
145 depends on CPU_SUBTYPE_SH7264 140 select PINCTRL_SH_FUNC_GPIO
146 select PINCTRL_SH_PFC_GPIO
147 141
148config PINCTRL_PFC_SH7269 142config PINCTRL_PFC_SH7269
149 def_bool y 143 bool "SH7269 pin control support" if COMPILE_TEST
150 depends on CPU_SUBTYPE_SH7269 144 select PINCTRL_SH_FUNC_GPIO
151 select PINCTRL_SH_PFC_GPIO
152 145
153config PINCTRL_PFC_SH73A0 146config PINCTRL_PFC_SH73A0
154 def_bool y 147 bool "SH-Mobile AG5 pin control support" if COMPILE_TEST
155 depends on ARCH_SH73A0
156 select PINCTRL_SH_PFC_GPIO 148 select PINCTRL_SH_PFC_GPIO
157 select REGULATOR 149 select REGULATOR
158 150
159config PINCTRL_PFC_SH7720 151config PINCTRL_PFC_SH7720
160 def_bool y 152 bool "SH7720 pin control support" if COMPILE_TEST
161 depends on CPU_SUBTYPE_SH7720 153 select PINCTRL_SH_FUNC_GPIO
162 select PINCTRL_SH_PFC_GPIO
163 154
164config PINCTRL_PFC_SH7722 155config PINCTRL_PFC_SH7722
165 def_bool y 156 bool "SH7722 pin control support" if COMPILE_TEST
166 depends on CPU_SUBTYPE_SH7722 157 select PINCTRL_SH_FUNC_GPIO
167 select PINCTRL_SH_PFC_GPIO
168 158
169config PINCTRL_PFC_SH7723 159config PINCTRL_PFC_SH7723
170 def_bool y 160 bool "SH-Mobile R2 pin control support" if COMPILE_TEST
171 depends on CPU_SUBTYPE_SH7723 161 select PINCTRL_SH_FUNC_GPIO
172 select PINCTRL_SH_PFC_GPIO
173 162
174config PINCTRL_PFC_SH7724 163config PINCTRL_PFC_SH7724
175 def_bool y 164 bool "SH-Mobile R2R pin control support" if COMPILE_TEST
176 depends on CPU_SUBTYPE_SH7724 165 select PINCTRL_SH_FUNC_GPIO
177 select PINCTRL_SH_PFC_GPIO
178 166
179config PINCTRL_PFC_SH7734 167config PINCTRL_PFC_SH7734
180 def_bool y 168 bool "SH7734 pin control support" if COMPILE_TEST
181 depends on CPU_SUBTYPE_SH7734 169 select PINCTRL_SH_FUNC_GPIO
182 select PINCTRL_SH_PFC_GPIO
183 170
184config PINCTRL_PFC_SH7757 171config PINCTRL_PFC_SH7757
185 def_bool y 172 bool "SH7757 pin control support" if COMPILE_TEST
186 depends on CPU_SUBTYPE_SH7757 173 select PINCTRL_SH_FUNC_GPIO
187 select PINCTRL_SH_PFC_GPIO
188 174
189config PINCTRL_PFC_SH7785 175config PINCTRL_PFC_SH7785
190 def_bool y 176 bool "SH7785 pin control support" if COMPILE_TEST
191 depends on CPU_SUBTYPE_SH7785 177 select PINCTRL_SH_FUNC_GPIO
192 select PINCTRL_SH_PFC_GPIO
193 178
194config PINCTRL_PFC_SH7786 179config PINCTRL_PFC_SH7786
195 def_bool y 180 bool "SH7786 pin control support" if COMPILE_TEST
196 depends on CPU_SUBTYPE_SH7786 181 select PINCTRL_SH_FUNC_GPIO
197 select PINCTRL_SH_PFC_GPIO
198 182
199config PINCTRL_PFC_SHX3 183config PINCTRL_PFC_SHX3
200 def_bool y 184 bool "SH-X3 pin control support" if COMPILE_TEST
201 depends on CPU_SUBTYPE_SHX3 185 select PINCTRL_SH_FUNC_GPIO
202 select PINCTRL_SH_PFC_GPIO
203endif
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 82ebb2a91ee0..8c95abcfcc00 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -38,3 +38,18 @@ obj-$(CONFIG_PINCTRL_PFC_SH7757) += pfc-sh7757.o
38obj-$(CONFIG_PINCTRL_PFC_SH7785) += pfc-sh7785.o 38obj-$(CONFIG_PINCTRL_PFC_SH7785) += pfc-sh7785.o
39obj-$(CONFIG_PINCTRL_PFC_SH7786) += pfc-sh7786.o 39obj-$(CONFIG_PINCTRL_PFC_SH7786) += pfc-sh7786.o
40obj-$(CONFIG_PINCTRL_PFC_SHX3) += pfc-shx3.o 40obj-$(CONFIG_PINCTRL_PFC_SHX3) += pfc-shx3.o
41
42ifeq ($(CONFIG_COMPILE_TEST),y)
43CFLAGS_pfc-sh7203.o += -I$(srctree)/arch/sh/include/cpu-sh2a
44CFLAGS_pfc-sh7264.o += -I$(srctree)/arch/sh/include/cpu-sh2a
45CFLAGS_pfc-sh7269.o += -I$(srctree)/arch/sh/include/cpu-sh2a
46CFLAGS_pfc-sh7720.o += -I$(srctree)/arch/sh/include/cpu-sh3
47CFLAGS_pfc-sh7722.o += -I$(srctree)/arch/sh/include/cpu-sh4
48CFLAGS_pfc-sh7723.o += -I$(srctree)/arch/sh/include/cpu-sh4
49CFLAGS_pfc-sh7724.o += -I$(srctree)/arch/sh/include/cpu-sh4
50CFLAGS_pfc-sh7734.o += -I$(srctree)/arch/sh/include/cpu-sh4
51CFLAGS_pfc-sh7757.o += -I$(srctree)/arch/sh/include/cpu-sh4
52CFLAGS_pfc-sh7785.o += -I$(srctree)/arch/sh/include/cpu-sh4
53CFLAGS_pfc-sh7786.o += -I$(srctree)/arch/sh/include/cpu-sh4
54CFLAGS_pfc-shx3.o += -I$(srctree)/arch/sh/include/cpu-sh4
55endif
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index f1cfcc8c6544..3f989f5cb021 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -571,6 +571,13 @@ static const struct of_device_id sh_pfc_of_table[] = {
571 .compatible = "renesas,pfc-r8a7795", 571 .compatible = "renesas,pfc-r8a7795",
572 .data = &r8a7795_pinmux_info, 572 .data = &r8a7795_pinmux_info,
573 }, 573 },
574#ifdef DEBUG
575 {
576 /* For sanity checks only (nothing matches against this) */
577 .compatible = "renesas,pfc-r8a77950", /* R-Car H3 ES1.0 */
578 .data = &r8a7795es1_pinmux_info,
579 },
580#endif /* DEBUG */
574#endif 581#endif
575#ifdef CONFIG_PINCTRL_PFC_R8A7796 582#ifdef CONFIG_PINCTRL_PFC_R8A7796
576 { 583 {
@@ -709,6 +716,128 @@ static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
709#define DEV_PM_OPS NULL 716#define DEV_PM_OPS NULL
710#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */ 717#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
711 718
719#ifdef DEBUG
720static bool is0s(const u16 *enum_ids, unsigned int n)
721{
722 unsigned int i;
723
724 for (i = 0; i < n; i++)
725 if (enum_ids[i])
726 return false;
727
728 return true;
729}
730
731static unsigned int sh_pfc_errors;
732static unsigned int sh_pfc_warnings;
733
734static void sh_pfc_check_cfg_reg(const char *drvname,
735 const struct pinmux_cfg_reg *cfg_reg)
736{
737 unsigned int i, n, rw, fw;
738
739 if (cfg_reg->field_width) {
740 /* Checked at build time */
741 return;
742 }
743
744 for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {
745 if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw)) {
746 pr_warn("%s: reg 0x%x: reserved field [%u:%u] can be split to reduce table size\n",
747 drvname, cfg_reg->reg, rw, rw + fw - 1);
748 sh_pfc_warnings++;
749 }
750 n += 1 << fw;
751 rw += fw;
752 }
753
754 if (rw != cfg_reg->reg_width) {
755 pr_err("%s: reg 0x%x: var_field_width declares %u instead of %u bits\n",
756 drvname, cfg_reg->reg, rw, cfg_reg->reg_width);
757 sh_pfc_errors++;
758 }
759
760 if (n != cfg_reg->nr_enum_ids) {
761 pr_err("%s: reg 0x%x: enum_ids[] has %u instead of %u values\n",
762 drvname, cfg_reg->reg, cfg_reg->nr_enum_ids, n);
763 sh_pfc_errors++;
764 }
765}
766
767static void sh_pfc_check_info(const struct sh_pfc_soc_info *info)
768{
769 const struct sh_pfc_function *func;
770 const char *drvname = info->name;
771 unsigned int *refcnts;
772 unsigned int i, j, k;
773
774 pr_info("Checking %s\n", drvname);
775
776 /* Check groups and functions */
777 refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);
778 if (!refcnts)
779 return;
780
781 for (i = 0; i < info->nr_functions; i++) {
782 func = &info->functions[i];
783 for (j = 0; j < func->nr_groups; j++) {
784 for (k = 0; k < info->nr_groups; k++) {
785 if (!strcmp(func->groups[j],
786 info->groups[k].name)) {
787 refcnts[k]++;
788 break;
789 }
790 }
791
792 if (k == info->nr_groups) {
793 pr_err("%s: function %s: group %s not found\n",
794 drvname, func->name, func->groups[j]);
795 sh_pfc_errors++;
796 }
797 }
798 }
799
800 for (i = 0; i < info->nr_groups; i++) {
801 if (!refcnts[i]) {
802 pr_err("%s: orphan group %s\n", drvname,
803 info->groups[i].name);
804 sh_pfc_errors++;
805 } else if (refcnts[i] > 1) {
806 pr_err("%s: group %s referred by %u functions\n",
807 drvname, info->groups[i].name, refcnts[i]);
808 sh_pfc_warnings++;
809 }
810 }
811
812 kfree(refcnts);
813
814 /* Check config register descriptions */
815 for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++)
816 sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
817}
818
819static void sh_pfc_check_driver(const struct platform_driver *pdrv)
820{
821 unsigned int i;
822
823 pr_warn("Checking builtin pinmux tables\n");
824
825 for (i = 0; pdrv->id_table[i].name[0]; i++)
826 sh_pfc_check_info((void *)pdrv->id_table[i].driver_data);
827
828#ifdef CONFIG_OF
829 for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++)
830 sh_pfc_check_info(pdrv->driver.of_match_table[i].data);
831#endif
832
833 pr_warn("Detected %u errors and %u warnings\n", sh_pfc_errors,
834 sh_pfc_warnings);
835}
836
837#else /* !DEBUG */
838static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
839#endif /* !DEBUG */
840
712static int sh_pfc_probe(struct platform_device *pdev) 841static int sh_pfc_probe(struct platform_device *pdev)
713{ 842{
714#ifdef CONFIG_OF 843#ifdef CONFIG_OF
@@ -840,6 +969,7 @@ static struct platform_driver sh_pfc_driver = {
840 969
841static int __init sh_pfc_init(void) 970static int __init sh_pfc_init(void)
842{ 971{
972 sh_pfc_check_driver(&sh_pfc_driver);
843 return platform_driver_register(&sh_pfc_driver); 973 return platform_driver_register(&sh_pfc_driver);
844} 974}
845postcore_initcall(sh_pfc_init); 975postcore_initcall(sh_pfc_init);
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 4f3a34ee1cd4..97c1332c1045 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -252,7 +252,7 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip)
252 * Function GPIOs 252 * Function GPIOs
253 */ 253 */
254 254
255#ifdef CONFIG_SUPERH 255#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
256static int gpio_function_request(struct gpio_chip *gc, unsigned offset) 256static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
257{ 257{
258 static bool __print_once; 258 static bool __print_once;
@@ -292,7 +292,7 @@ static int gpio_function_setup(struct sh_pfc_chip *chip)
292 292
293 return 0; 293 return 0;
294} 294}
295#endif 295#endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
296 296
297/* ----------------------------------------------------------------------------- 297/* -----------------------------------------------------------------------------
298 * Register/unregister 298 * Register/unregister
@@ -369,7 +369,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
369 if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node) 369 if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node)
370 return 0; 370 return 0;
371 371
372#ifdef CONFIG_SUPERH 372#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
373 /* 373 /*
374 * Register the GPIO to pin mappings. As pins with GPIO ports 374 * Register the GPIO to pin mappings. As pins with GPIO ports
375 * must come first in the ranges, skip the pins without GPIO 375 * must come first in the ranges, skip the pins without GPIO
@@ -397,7 +397,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
397 chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL); 397 chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
398 if (IS_ERR(chip)) 398 if (IS_ERR(chip))
399 return PTR_ERR(chip); 399 return PTR_ERR(chip);
400#endif /* CONFIG_SUPERH */ 400#endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
401 401
402 return 0; 402 return 0;
403} 403}
diff --git a/drivers/pinctrl/sh-pfc/pfc-emev2.c b/drivers/pinctrl/sh-pfc/pfc-emev2.c
index 310c6f3ee7cc..0af1ef82a1a8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-emev2.c
+++ b/drivers/pinctrl/sh-pfc/pfc-emev2.c
@@ -1433,7 +1433,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
1433}; 1433};
1434 1434
1435static const struct pinmux_cfg_reg pinmux_config_regs[] = { 1435static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1436 { PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1) { 1436 { PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1, GROUP(
1437 0, PORT31_FN, /* PIN: J18 */ 1437 0, PORT31_FN, /* PIN: J18 */
1438 0, PORT30_FN, /* PIN: H18 */ 1438 0, PORT30_FN, /* PIN: H18 */
1439 0, PORT29_FN, /* PIN: G18 */ 1439 0, PORT29_FN, /* PIN: G18 */
@@ -1466,9 +1466,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1466 FN_JT_SEL, PORT2_FN, /* PIN: V9 */ 1466 FN_JT_SEL, PORT2_FN, /* PIN: V9 */
1467 0, PORT1_FN, /* PIN: U10 */ 1467 0, PORT1_FN, /* PIN: U10 */
1468 0, PORT0_FN, /* PIN: V10 */ 1468 0, PORT0_FN, /* PIN: V10 */
1469 } 1469 ))
1470 }, 1470 },
1471 { PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1) { 1471 { PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1, GROUP(
1472 FN_SDI1_CMD, PORT63_FN, /* PIN: AC21 */ 1472 FN_SDI1_CMD, PORT63_FN, /* PIN: AC21 */
1473 FN_SDI1_CKI, PORT62_FN, /* PIN: AA23 */ 1473 FN_SDI1_CKI, PORT62_FN, /* PIN: AA23 */
1474 FN_SDI1_CKO, PORT61_FN, /* PIN: AB22 */ 1474 FN_SDI1_CKO, PORT61_FN, /* PIN: AB22 */
@@ -1501,9 +1501,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1501 FN_LCD3_R2, PORT34_FN, /* PIN: A19 */ 1501 FN_LCD3_R2, PORT34_FN, /* PIN: A19 */
1502 FN_LCD3_R1, PORT33_FN, /* PIN: B20 */ 1502 FN_LCD3_R1, PORT33_FN, /* PIN: B20 */
1503 FN_LCD3_R0, PORT32_FN, /* PIN: A20 */ 1503 FN_LCD3_R0, PORT32_FN, /* PIN: A20 */
1504 } 1504 ))
1505 }, 1505 },
1506 { PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1) { 1506 { PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1, GROUP(
1507 FN_AB_1_0_PORT95, PORT95_FN, /* PIN: L21 */ 1507 FN_AB_1_0_PORT95, PORT95_FN, /* PIN: L21 */
1508 FN_AB_1_0_PORT94, PORT94_FN, /* PIN: K21 */ 1508 FN_AB_1_0_PORT94, PORT94_FN, /* PIN: K21 */
1509 FN_AB_1_0_PORT93, PORT93_FN, /* PIN: J21 */ 1509 FN_AB_1_0_PORT93, PORT93_FN, /* PIN: J21 */
@@ -1536,9 +1536,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1536 FN_SDI1_DATA2, PORT66_FN, /* PIN: AB19 */ 1536 FN_SDI1_DATA2, PORT66_FN, /* PIN: AB19 */
1537 FN_SDI1_DATA1, PORT65_FN, /* PIN: AB20 */ 1537 FN_SDI1_DATA1, PORT65_FN, /* PIN: AB20 */
1538 FN_SDI1_DATA0, PORT64_FN, /* PIN: AB21 */ 1538 FN_SDI1_DATA0, PORT64_FN, /* PIN: AB21 */
1539 } 1539 ))
1540 }, 1540 },
1541 { PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1) { 1541 { PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1, GROUP(
1542 FN_NTSC_DATA4, PORT127_FN, /* PIN: T20 */ 1542 FN_NTSC_DATA4, PORT127_FN, /* PIN: T20 */
1543 FN_NTSC_DATA3, PORT126_FN, /* PIN: R18 */ 1543 FN_NTSC_DATA3, PORT126_FN, /* PIN: R18 */
1544 FN_NTSC_DATA2, PORT125_FN, /* PIN: R20 */ 1544 FN_NTSC_DATA2, PORT125_FN, /* PIN: R20 */
@@ -1571,9 +1571,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1571 FN_AB_9_8_PORT98, PORT98_FN, /* PIN: M20 */ 1571 FN_AB_9_8_PORT98, PORT98_FN, /* PIN: M20 */
1572 FN_AB_9_8_PORT97, PORT97_FN, /* PIN: N21 */ 1572 FN_AB_9_8_PORT97, PORT97_FN, /* PIN: N21 */
1573 FN_AB_A20, PORT96_FN, /* PIN: M21 */ 1573 FN_AB_A20, PORT96_FN, /* PIN: M21 */
1574 } 1574 ))
1575 }, 1575 },
1576 { PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1) { 1576 { PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1, GROUP(
1577 0, 0, 1577 0, 0,
1578 FN_UART_1_0_PORT158, PORT158_FN, /* PIN: AB10 */ 1578 FN_UART_1_0_PORT158, PORT158_FN, /* PIN: AB10 */
1579 FN_UART_1_0_PORT157, PORT157_FN, /* PIN: AA10 */ 1579 FN_UART_1_0_PORT157, PORT157_FN, /* PIN: AA10 */
@@ -1606,11 +1606,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1606 FN_NTSC_DATA7, PORT130_FN, /* PIN: U18 */ 1606 FN_NTSC_DATA7, PORT130_FN, /* PIN: U18 */
1607 FN_NTSC_DATA6, PORT129_FN, /* PIN: U20 */ 1607 FN_NTSC_DATA6, PORT129_FN, /* PIN: U20 */
1608 FN_NTSC_DATA5, PORT128_FN, /* PIN: T18 */ 1608 FN_NTSC_DATA5, PORT128_FN, /* PIN: T18 */
1609 } 1609 ))
1610 }, 1610 },
1611 { PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32, 1611 { PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,
1612 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1612 GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1613 1, 1, 1, 1, 2, 2, 2, 2, 2, 2) { 1613 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
1614 2, 2),
1615 GROUP(
1614 /* 31 - 12 */ 1616 /* 31 - 12 */
1615 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1617 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1616 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1618 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1624,11 +1626,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1624 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1626 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1625 /* 1 - 0 */ 1627 /* 1 - 0 */
1626 FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01, 0, 0, 1628 FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01, 0, 0,
1627 } 1629 ))
1628 }, 1630 },
1629 { PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32, 1631 { PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32,
1630 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1632 GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1631 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) { 1633 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1634 1, 1, 1, 1, 1, 1, 2),
1635 GROUP(
1632 /* 31 - 2 */ 1636 /* 31 - 2 */
1633 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1637 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1634 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1638 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1636,11 +1640,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1636 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1640 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1637 /* 1 - 0 */ 1641 /* 1 - 0 */
1638 FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01, 0, 0, 1642 FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01, 0, 0,
1639 } 1643 ))
1640 }, 1644 },
1641 { PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32, 1645 { PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32,
1642 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1646 GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1643 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) { 1647 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1648 1, 1, 1, 1, 1, 1, 2),
1649 GROUP(
1644 /* 31 - 2 */ 1650 /* 31 - 2 */
1645 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1651 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1646 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1652 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1648,11 +1654,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1648 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1654 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1649 /* 1 - 0 */ 1655 /* 1 - 0 */
1650 FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01, 0, 0, 1656 FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01, 0, 0,
1651 } 1657 ))
1652 }, 1658 },
1653 { PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32, 1659 { PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32,
1654 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1660 GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1655 2, 2, 2, 2, 2, 2, 2, 2) { 1661 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2),
1662 GROUP(
1656 /* 31 - 14 */ 1663 /* 31 - 14 */
1657 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1664 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1658 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1665 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1673,11 +1680,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1673 FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11, 1680 FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11,
1674 /* 1 - 0 */ 1681 /* 1 - 0 */
1675 FN_SEL_AB_1_0_00, 0, FN_SEL_AB_1_0_10, 0, 1682 FN_SEL_AB_1_0_00, 0, FN_SEL_AB_1_0_10, 0,
1676 } 1683 ))
1677 }, 1684 },
1678 { PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32, 1685 { PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32,
1679 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1686 GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1680 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2) { 1687 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
1688 2, 2, 2),
1689 GROUP(
1681 /* 31 - 10 */ 1690 /* 31 - 10 */
1682 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1691 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1683 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1692 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1692,11 +1701,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1692 FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01, 0, 0, 1701 FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01, 0, 0,
1693 /* 1 - 0 */ 1702 /* 1 - 0 */
1694 FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01, 0, 0, 1703 FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01, 0, 0,
1695 } 1704 ))
1696 }, 1705 },
1697 { PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32, 1706 { PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32,
1698 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1707 GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1699 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) { 1708 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1709 1, 1, 1, 1, 1, 1, 2),
1710 GROUP(
1700 /* 31 - 2 */ 1711 /* 31 - 2 */
1701 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1712 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1702 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1713 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1704,7 +1715,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1704 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1715 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1705 /* 1 - 0 */ 1716 /* 1 - 0 */
1706 FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 0, 0, 1717 FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 0, 0,
1707 } 1718 ))
1708 }, 1719 },
1709 { }, 1720 { },
1710}; 1721};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 5acbacb3727f..bf12849defdb 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -2284,7 +2284,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2284 PORTCR(328, 0xe6053148), 2284 PORTCR(328, 0xe6053148),
2285 PORTCR(329, 0xe6053149), 2285 PORTCR(329, 0xe6053149),
2286 2286
2287 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) { 2287 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP(
2288 MSEL1CR_31_0, MSEL1CR_31_1, 2288 MSEL1CR_31_0, MSEL1CR_31_1,
2289 0, 0, 2289 0, 0,
2290 0, 0, 2290 0, 0,
@@ -2317,9 +2317,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2317 MSEL1CR_02_0, MSEL1CR_02_1, 2317 MSEL1CR_02_0, MSEL1CR_02_1,
2318 MSEL1CR_01_0, MSEL1CR_01_1, 2318 MSEL1CR_01_0, MSEL1CR_01_1,
2319 MSEL1CR_00_0, MSEL1CR_00_1, 2319 MSEL1CR_00_0, MSEL1CR_00_1,
2320 } 2320 ))
2321 }, 2321 },
2322 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) { 2322 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1, GROUP(
2323 MSEL3CR_31_0, MSEL3CR_31_1, 2323 MSEL3CR_31_0, MSEL3CR_31_1,
2324 0, 0, 2324 0, 0,
2325 0, 0, 2325 0, 0,
@@ -2352,9 +2352,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2352 0, 0, 2352 0, 0,
2353 MSEL3CR_01_0, MSEL3CR_01_1, 2353 MSEL3CR_01_0, MSEL3CR_01_1,
2354 MSEL3CR_00_0, MSEL3CR_00_1, 2354 MSEL3CR_00_0, MSEL3CR_00_1,
2355 } 2355 ))
2356 }, 2356 },
2357 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) { 2357 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1, GROUP(
2358 0, 0, 2358 0, 0,
2359 MSEL4CR_30_0, MSEL4CR_30_1, 2359 MSEL4CR_30_0, MSEL4CR_30_1,
2360 MSEL4CR_29_0, MSEL4CR_29_1, 2360 MSEL4CR_29_0, MSEL4CR_29_1,
@@ -2387,9 +2387,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2387 0, 0, 2387 0, 0,
2388 MSEL4CR_01_0, MSEL4CR_01_1, 2388 MSEL4CR_01_0, MSEL4CR_01_1,
2389 0, 0, 2389 0, 0,
2390 } 2390 ))
2391 }, 2391 },
2392 { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) { 2392 { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1, GROUP(
2393 MSEL5CR_31_0, MSEL5CR_31_1, 2393 MSEL5CR_31_0, MSEL5CR_31_1,
2394 MSEL5CR_30_0, MSEL5CR_30_1, 2394 MSEL5CR_30_0, MSEL5CR_30_1,
2395 MSEL5CR_29_0, MSEL5CR_29_1, 2395 MSEL5CR_29_0, MSEL5CR_29_1,
@@ -2422,9 +2422,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2422 0, 0, 2422 0, 0,
2423 0, 0, 2423 0, 0,
2424 0, 0, 2424 0, 0,
2425 } 2425 ))
2426 }, 2426 },
2427 { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) { 2427 { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1, GROUP(
2428 0, 0, 2428 0, 0,
2429 0, 0, 2429 0, 0,
2430 0, 0, 2430 0, 0,
@@ -2457,14 +2457,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2457 0, 0, 2457 0, 0,
2458 MSEL8CR_01_0, MSEL8CR_01_1, 2458 MSEL8CR_01_0, MSEL8CR_01_1,
2459 MSEL8CR_00_0, MSEL8CR_00_1, 2459 MSEL8CR_00_0, MSEL8CR_00_1,
2460 } 2460 ))
2461 }, 2461 },
2462 { }, 2462 { },
2463}; 2463};
2464 2464
2465static const struct pinmux_data_reg pinmux_data_regs[] = { 2465static const struct pinmux_data_reg pinmux_data_regs[] = {
2466 2466
2467 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) { 2467 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32, GROUP(
2468 0, PORT30_DATA, PORT29_DATA, PORT28_DATA, 2468 0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2469 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, 2469 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2470 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, 2470 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
@@ -2473,9 +2473,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
2473 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, 2473 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2474 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, 2474 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2475 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA, 2475 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
2476 } 2476 ))
2477 }, 2477 },
2478 { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) { 2478 { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32, GROUP(
2479 0, 0, 0, 0, 2479 0, 0, 0, 0,
2480 0, 0, 0, 0, 2480 0, 0, 0, 0,
2481 0, 0, 0, 0, 2481 0, 0, 0, 0,
@@ -2484,9 +2484,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
2484 0, 0, 0, PORT40_DATA, 2484 0, 0, 0, PORT40_DATA,
2485 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, 2485 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2486 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA, 2486 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
2487 } 2487 ))
2488 }, 2488 },
2489 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32) { 2489 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32, GROUP(
2490 0, 0, 0, 0, 2490 0, 0, 0, 0,
2491 0, 0, 0, 0, 2491 0, 0, 0, 0,
2492 0, 0, PORT85_DATA, PORT84_DATA, 2492 0, 0, PORT85_DATA, PORT84_DATA,
@@ -2495,9 +2495,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
2495 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, 2495 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2496 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, 2496 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2497 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA, 2497 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
2498 } 2498 ))
2499 }, 2499 },
2500 { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) { 2500 { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32, GROUP(
2501 0, PORT126_DATA, PORT125_DATA, PORT124_DATA, 2501 0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2502 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA, 2502 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
2503 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA, 2503 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
@@ -2506,9 +2506,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
2506 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, 2506 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2507 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, 2507 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2508 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA, 2508 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
2509 } 2509 ))
2510 }, 2510 },
2511 { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) { 2511 { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32, GROUP(
2512 0, 0, 0, 0, 2512 0, 0, 0, 0,
2513 0, 0, 0, 0, 2513 0, 0, 0, 0,
2514 0, 0, 0, 0, 2514 0, 0, 0, 0,
@@ -2517,9 +2517,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
2517 0, 0, 0, 0, 2517 0, 0, 0, 0,
2518 0, PORT134_DATA, PORT133_DATA, PORT132_DATA, 2518 0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2519 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA, 2519 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
2520 } 2520 ))
2521 }, 2521 },
2522 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) { 2522 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32, GROUP(
2523 0, 0, 0, 0, 2523 0, 0, 0, 0,
2524 0, 0, 0, 0, 2524 0, 0, 0, 0,
2525 0, 0, 0, 0, 2525 0, 0, 0, 0,
@@ -2528,9 +2528,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
2528 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA, 2528 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2529 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA, 2529 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
2530 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA, 2530 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
2531 } 2531 ))
2532 }, 2532 },
2533 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) { 2533 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32, GROUP(
2534 0, PORT222_DATA, PORT221_DATA, PORT220_DATA, 2534 0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
2535 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA, 2535 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
2536 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA, 2536 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
@@ -2539,9 +2539,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
2539 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, 2539 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
2540 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, 2540 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
2541 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA, 2541 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
2542 } 2542 ))
2543 }, 2543 },
2544 { PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32) { 2544 { PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32, GROUP(
2545 0, 0, 0, 0, 2545 0, 0, 0, 0,
2546 0, PORT250_DATA, PORT249_DATA, PORT248_DATA, 2546 0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
2547 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA, 2547 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
@@ -2550,9 +2550,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
2550 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA, 2550 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
2551 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA, 2551 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
2552 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA, 2552 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
2553 } 2553 ))
2554 }, 2554 },
2555 { PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32) { 2555 { PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32, GROUP(
2556 0, 0, 0, 0, 2556 0, 0, 0, 0,
2557 PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA, 2557 PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
2558 PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA, 2558 PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
@@ -2561,9 +2561,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
2561 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA, 2561 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
2562 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA, 2562 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
2563 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA, 2563 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
2564 } 2564 ))
2565 }, 2565 },
2566 { PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32) { 2566 { PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32, GROUP(
2567 0, 0, 0, 0, 2567 0, 0, 0, 0,
2568 0, 0, 0, 0, 2568 0, 0, 0, 0,
2569 0, 0, 0, PORT308_DATA, 2569 0, 0, 0, PORT308_DATA,
@@ -2572,9 +2572,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
2572 PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA, 2572 PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
2573 PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA, 2573 PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
2574 PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA, 2574 PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
2575 } 2575 ))
2576 }, 2576 },
2577 { PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32) { 2577 { PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32, GROUP(
2578 0, 0, 0, 0, 2578 0, 0, 0, 0,
2579 0, 0, 0, 0, 2579 0, 0, 0, 0,
2580 0, 0, 0, 0, 2580 0, 0, 0, 0,
@@ -2583,7 +2583,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
2583 0, 0, PORT329_DATA, PORT328_DATA, 2583 0, 0, PORT329_DATA, PORT328_DATA,
2584 PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA, 2584 PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
2585 PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA, 2585 PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
2586 } 2586 ))
2587 }, 2587 },
2588 { }, 2588 { },
2589}; 2589};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 6d761e62c6c8..696a0f6fc1da 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -3436,7 +3436,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3436 PORTCR(210, 0xe60530d2), /* PORT210CR */ 3436 PORTCR(210, 0xe60530d2), /* PORT210CR */
3437 PORTCR(211, 0xe60530d3), /* PORT211CR */ 3437 PORTCR(211, 0xe60530d3), /* PORT211CR */
3438 3438
3439 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) { 3439 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP(
3440 MSEL1CR_31_0, MSEL1CR_31_1, 3440 MSEL1CR_31_0, MSEL1CR_31_1,
3441 MSEL1CR_30_0, MSEL1CR_30_1, 3441 MSEL1CR_30_0, MSEL1CR_30_1,
3442 MSEL1CR_29_0, MSEL1CR_29_1, 3442 MSEL1CR_29_0, MSEL1CR_29_1,
@@ -3461,9 +3461,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3461 MSEL1CR_2_0, MSEL1CR_2_1, 3461 MSEL1CR_2_0, MSEL1CR_2_1,
3462 0, 0, 3462 0, 0,
3463 MSEL1CR_0_0, MSEL1CR_0_1, 3463 MSEL1CR_0_0, MSEL1CR_0_1,
3464 } 3464 ))
3465 }, 3465 },
3466 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) { 3466 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1, GROUP(
3467 0, 0, 0, 0, 0, 0, 0, 0, 3467 0, 0, 0, 0, 0, 0, 0, 0,
3468 0, 0, 0, 0, 0, 0, 0, 0, 3468 0, 0, 0, 0, 0, 0, 0, 0,
3469 0, 0, 0, 0, 0, 0, 0, 0, 3469 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3474,9 +3474,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3474 MSEL3CR_6_0, MSEL3CR_6_1, 3474 MSEL3CR_6_0, MSEL3CR_6_1,
3475 0, 0, 0, 0, 0, 0, 0, 0, 3475 0, 0, 0, 0, 0, 0, 0, 0,
3476 0, 0, 0, 0, 3476 0, 0, 0, 0,
3477 } 3477 ))
3478 }, 3478 },
3479 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) { 3479 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1, GROUP(
3480 0, 0, 0, 0, 0, 0, 0, 0, 3480 0, 0, 0, 0, 0, 0, 0, 0,
3481 0, 0, 0, 0, 0, 0, 0, 0, 3481 0, 0, 0, 0, 0, 0, 0, 0,
3482 0, 0, 0, 0, 0, 0, 0, 0, 3482 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3493,9 +3493,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3493 0, 0, 0, 0, 3493 0, 0, 0, 0,
3494 MSEL4CR_1_0, MSEL4CR_1_1, 3494 MSEL4CR_1_0, MSEL4CR_1_1,
3495 0, 0, 3495 0, 0,
3496 } 3496 ))
3497 }, 3497 },
3498 { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) { 3498 { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1, GROUP(
3499 MSEL5CR_31_0, MSEL5CR_31_1, 3499 MSEL5CR_31_0, MSEL5CR_31_1,
3500 MSEL5CR_30_0, MSEL5CR_30_1, 3500 MSEL5CR_30_0, MSEL5CR_30_1,
3501 MSEL5CR_29_0, MSEL5CR_29_1, 3501 MSEL5CR_29_0, MSEL5CR_29_1,
@@ -3528,13 +3528,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3528 MSEL5CR_2_0, MSEL5CR_2_1, 3528 MSEL5CR_2_0, MSEL5CR_2_1,
3529 0, 0, 3529 0, 0,
3530 MSEL5CR_0_0, MSEL5CR_0_1, 3530 MSEL5CR_0_0, MSEL5CR_0_1,
3531 } 3531 ))
3532 }, 3532 },
3533 { }, 3533 { },
3534}; 3534};
3535 3535
3536static const struct pinmux_data_reg pinmux_data_regs[] = { 3536static const struct pinmux_data_reg pinmux_data_regs[] = {
3537 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) { 3537 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32, GROUP(
3538 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, 3538 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
3539 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, 3539 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
3540 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, 3540 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
@@ -3542,9 +3542,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
3542 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, 3542 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
3543 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, 3543 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
3544 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, 3544 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
3545 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA } 3545 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA ))
3546 }, 3546 },
3547 { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) { 3547 { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32, GROUP(
3548 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA, 3548 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
3549 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA, 3549 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
3550 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA, 3550 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
@@ -3552,9 +3552,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
3552 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA, 3552 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
3553 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA, 3553 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
3554 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, 3554 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
3555 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA } 3555 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA ))
3556 }, 3556 },
3557 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) { 3557 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32, GROUP(
3558 0, 0, 0, 0, 3558 0, 0, 0, 0,
3559 0, 0, 0, 0, 3559 0, 0, 0, 0,
3560 0, 0, 0, 0, 3560 0, 0, 0, 0,
@@ -3562,9 +3562,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
3562 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, 3562 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
3563 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, 3563 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
3564 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, 3564 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
3565 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA } 3565 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA ))
3566 }, 3566 },
3567 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) { 3567 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32, GROUP(
3568 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, 3568 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
3569 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, 3569 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
3570 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA, 3570 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
@@ -3572,9 +3572,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
3572 0, 0, 0, 0, 3572 0, 0, 0, 0,
3573 0, 0, 0, 0, 3573 0, 0, 0, 0,
3574 0, 0, 0, 0, 3574 0, 0, 0, 0,
3575 0, 0, 0, 0 } 3575 0, 0, 0, 0 ))
3576 }, 3576 },
3577 { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) { 3577 { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32, GROUP(
3578 0, 0, 0, 0, 3578 0, 0, 0, 0,
3579 0, 0, 0, 0, 3579 0, 0, 0, 0,
3580 0, 0, 0, 0, 3580 0, 0, 0, 0,
@@ -3582,9 +3582,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
3582 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, 3582 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
3583 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, 3583 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
3584 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, 3584 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
3585 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA } 3585 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA ))
3586 }, 3586 },
3587 { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) { 3587 { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32, GROUP(
3588 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA, 3588 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
3589 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA, 3589 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
3590 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA, 3590 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
@@ -3592,9 +3592,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
3592 0, 0, 0, 0, 3592 0, 0, 0, 0,
3593 0, 0, 0, 0, 3593 0, 0, 0, 0,
3594 0, 0, 0, 0, 3594 0, 0, 0, 0,
3595 0, 0, 0, 0 } 3595 0, 0, 0, 0 ))
3596 }, 3596 },
3597 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) { 3597 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32, GROUP(
3598 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA, 3598 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
3599 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA, 3599 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
3600 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA, 3600 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
@@ -3602,9 +3602,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
3602 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA, 3602 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
3603 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA, 3603 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
3604 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA, 3604 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
3605 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA } 3605 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA ))
3606 }, 3606 },
3607 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) { 3607 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32, GROUP(
3608 PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA, 3608 PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
3609 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA, 3609 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
3610 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA, 3610 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
@@ -3612,9 +3612,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
3612 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA, 3612 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
3613 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA, 3613 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
3614 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA, 3614 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
3615 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA } 3615 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA ))
3616 }, 3616 },
3617 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) { 3617 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32, GROUP(
3618 0, 0, 0, 0, 3618 0, 0, 0, 0,
3619 0, 0, 0, 0, 3619 0, 0, 0, 0,
3620 0, 0, 0, 0, 3620 0, 0, 0, 0,
@@ -3622,9 +3622,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
3622 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA, 3622 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
3623 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, 3623 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
3624 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, 3624 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
3625 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA } 3625 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA ))
3626 }, 3626 },
3627 { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) { 3627 { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32, GROUP(
3628 0, 0, 0, 0, 3628 0, 0, 0, 0,
3629 0, 0, 0, 0, 3629 0, 0, 0, 0,
3630 0, 0, 0, 0, 3630 0, 0, 0, 0,
@@ -3632,7 +3632,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
3632 0, 0, 0, 0, 3632 0, 0, 0, 0,
3633 0, 0, 0, 0, 3633 0, 0, 0, 0,
3634 0, 0, 0, 0, 3634 0, 0, 0, 0,
3635 0, 0, 0, 0 } 3635 0, 0, 0, 0 ))
3636 }, 3636 },
3637 { }, 3637 { },
3638}; 3638};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
index 4359aeb35dbd..c05dc1490486 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
@@ -5,6 +5,7 @@
5 * Copyright (C) 2018 Renesas Electronics Corp. 5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */ 6 */
7 7
8#include <linux/errno.h>
8#include <linux/kernel.h> 9#include <linux/kernel.h>
9 10
10#include "sh_pfc.h" 11#include "sh_pfc.h"
@@ -2540,7 +2541,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
2540}; 2541};
2541 2542
2542static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2543static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2543 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { 2544 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
2544 0, 0, 2545 0, 0,
2545 0, 0, 2546 0, 0,
2546 0, 0, 2547 0, 0,
@@ -2572,9 +2573,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2572 GP_0_3_FN, FN_USB1_OVC, 2573 GP_0_3_FN, FN_USB1_OVC,
2573 GP_0_2_FN, FN_USB1_PWEN, 2574 GP_0_2_FN, FN_USB1_PWEN,
2574 GP_0_1_FN, FN_USB0_OVC, 2575 GP_0_1_FN, FN_USB0_OVC,
2575 GP_0_0_FN, FN_USB0_PWEN, } 2576 GP_0_0_FN, FN_USB0_PWEN, ))
2576 }, 2577 },
2577 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { 2578 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
2578 0, 0, 2579 0, 0,
2579 0, 0, 2580 0, 0,
2580 0, 0, 2581 0, 0,
@@ -2606,9 +2607,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2606 GP_1_3_FN, FN_IP1_23_20, 2607 GP_1_3_FN, FN_IP1_23_20,
2607 GP_1_2_FN, FN_IP1_19_16, 2608 GP_1_2_FN, FN_IP1_19_16,
2608 GP_1_1_FN, FN_IP1_15_12, 2609 GP_1_1_FN, FN_IP1_15_12,
2609 GP_1_0_FN, FN_IP1_11_8, } 2610 GP_1_0_FN, FN_IP1_11_8, ))
2610 }, 2611 },
2611 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { 2612 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
2612 GP_2_31_FN, FN_IP8_3_0, 2613 GP_2_31_FN, FN_IP8_3_0,
2613 GP_2_30_FN, FN_IP7_31_28, 2614 GP_2_30_FN, FN_IP7_31_28,
2614 GP_2_29_FN, FN_IP7_27_24, 2615 GP_2_29_FN, FN_IP7_27_24,
@@ -2640,9 +2641,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2640 GP_2_3_FN, FN_IP4_19_16, 2641 GP_2_3_FN, FN_IP4_19_16,
2641 GP_2_2_FN, FN_IP4_15_12, 2642 GP_2_2_FN, FN_IP4_15_12,
2642 GP_2_1_FN, FN_IP4_11_8, 2643 GP_2_1_FN, FN_IP4_11_8,
2643 GP_2_0_FN, FN_IP4_7_4, } 2644 GP_2_0_FN, FN_IP4_7_4, ))
2644 }, 2645 },
2645 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { 2646 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
2646 0, 0, 2647 0, 0,
2647 0, 0, 2648 0, 0,
2648 GP_3_29_FN, FN_IP10_19_16, 2649 GP_3_29_FN, FN_IP10_19_16,
@@ -2674,9 +2675,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2674 GP_3_3_FN, FN_IP8_19_16, 2675 GP_3_3_FN, FN_IP8_19_16,
2675 GP_3_2_FN, FN_IP8_15_12, 2676 GP_3_2_FN, FN_IP8_15_12,
2676 GP_3_1_FN, FN_IP8_11_8, 2677 GP_3_1_FN, FN_IP8_11_8,
2677 GP_3_0_FN, FN_IP8_7_4, } 2678 GP_3_0_FN, FN_IP8_7_4, ))
2678 }, 2679 },
2679 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { 2680 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
2680 0, 0, 2681 0, 0,
2681 0, 0, 2682 0, 0,
2682 0, 0, 2683 0, 0,
@@ -2708,9 +2709,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2708 GP_4_3_FN, FN_IP11_3_0, 2709 GP_4_3_FN, FN_IP11_3_0,
2709 GP_4_2_FN, FN_IP10_31_28, 2710 GP_4_2_FN, FN_IP10_31_28,
2710 GP_4_1_FN, FN_IP10_27_24, 2711 GP_4_1_FN, FN_IP10_27_24,
2711 GP_4_0_FN, FN_IP10_23_20, } 2712 GP_4_0_FN, FN_IP10_23_20, ))
2712 }, 2713 },
2713 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { 2714 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
2714 GP_5_31_FN, FN_IP17_27_24, 2715 GP_5_31_FN, FN_IP17_27_24,
2715 GP_5_30_FN, FN_IP17_23_20, 2716 GP_5_30_FN, FN_IP17_23_20,
2716 GP_5_29_FN, FN_IP17_19_16, 2717 GP_5_29_FN, FN_IP17_19_16,
@@ -2742,10 +2743,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2742 GP_5_3_FN, FN_IP14_11_8, 2743 GP_5_3_FN, FN_IP14_11_8,
2743 GP_5_2_FN, FN_IP14_7_4, 2744 GP_5_2_FN, FN_IP14_7_4,
2744 GP_5_1_FN, FN_IP14_3_0, 2745 GP_5_1_FN, FN_IP14_3_0,
2745 GP_5_0_FN, FN_IP13_31_28, } 2746 GP_5_0_FN, FN_IP13_31_28, ))
2746 }, 2747 },
2747 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32, 2748 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2748 4, 4, 4, 4, 4, 4, 4, 4) { 2749 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2750 GROUP(
2749 /* IP0_31_28 [4] */ 2751 /* IP0_31_28 [4] */
2750 FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 0, 0, 0, 0, 0, 2752 FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 0, 0, 0, 0, 0,
2751 0, 0, 0, 0, 0, 0, 0, 0, 2753 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2769,10 +2771,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2769 0, 0, 0, 0, 0, 0, 0, 0, 2771 0, 0, 0, 0, 0, 0, 0, 0,
2770 /* IP0_3_0 [4] */ 2772 /* IP0_3_0 [4] */
2771 FN_SD0_CLK, 0, 0, FN_SSI_SCK1_C, FN_RX3_C, 0, 0, 0, 2773 FN_SD0_CLK, 0, 0, FN_SSI_SCK1_C, FN_RX3_C, 0, 0, 0,
2772 0, 0, 0, 0, 0, 0, 0, 0, } 2774 0, 0, 0, 0, 0, 0, 0, 0, ))
2773 }, 2775 },
2774 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32, 2776 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2775 4, 4, 4, 4, 4, 4, 4, 4) { 2777 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2778 GROUP(
2776 /* IP1_31_28 [4] */ 2779 /* IP1_31_28 [4] */
2777 FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0, 2780 FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0,
2778 0, 0, 0, 0, 0, 0, 0, 0, 2781 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2796,10 +2799,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2796 0, 0, 0, 0, 0, 0, 0, 0, 2799 0, 0, 0, 0, 0, 0, 0, 0,
2797 /* IP1_3_0 [4] */ 2800 /* IP1_3_0 [4] */
2798 FN_MMC0_D4, FN_SD1_CD, 0, 0, 0, 0, 0, 0, 2801 FN_MMC0_D4, FN_SD1_CD, 0, 0, 0, 0, 0, 0,
2799 0, 0, 0, 0, 0, 0, 0, 0, } 2802 0, 0, 0, 0, 0, 0, 0, 0, ))
2800 }, 2803 },
2801 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32, 2804 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2802 4, 4, 4, 4, 4, 4, 4, 4) { 2805 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2806 GROUP(
2803 /* IP2_31_28 [4] */ 2807 /* IP2_31_28 [4] */
2804 FN_D13, FN_MSIOF2_SYNC_A, 0, FN_RX4_C, 0, 0, 0, 0, 0, 2808 FN_D13, FN_MSIOF2_SYNC_A, 0, FN_RX4_C, 0, 0, 0, 0, 0,
2805 0, 0, 0, 0, 0, 0, 0, 2809 0, 0, 0, 0, 0, 0, 0,
@@ -2823,10 +2827,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2823 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2827 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2824 /* IP2_3_0 [4] */ 2828 /* IP2_3_0 [4] */
2825 FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 0, 0, 0, 0, 2829 FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 0, 0, 0, 0,
2826 0, 0, 0, 0, 0, 0, 0, 0, } 2830 0, 0, 0, 0, 0, 0, 0, 0, ))
2827 }, 2831 },
2828 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32, 2832 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2829 4, 4, 4, 4, 4, 4, 4, 4) { 2833 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2834 GROUP(
2830 /* IP3_31_28 [4] */ 2835 /* IP3_31_28 [4] */
2831 FN_QSPI0_SSL, FN_WE1_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2836 FN_QSPI0_SSL, FN_WE1_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2832 0, 0, 2837 0, 0,
@@ -2851,10 +2856,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2851 /* IP3_3_0 [4] */ 2856 /* IP3_3_0 [4] */
2852 FN_D14, FN_MSIOF2_SS1, 0, FN_TX4_C, FN_CAN1_RX_B, 2857 FN_D14, FN_MSIOF2_SS1, 0, FN_TX4_C, FN_CAN1_RX_B,
2853 0, FN_AVB_AVTP_CAPTURE_A, 2858 0, FN_AVB_AVTP_CAPTURE_A,
2854 0, 0, 0, 0, 0, 0, 0, 0, 0, } 2859 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
2855 }, 2860 },
2856 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32, 2861 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2857 4, 4, 4, 4, 4, 4, 4, 4) { 2862 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2863 GROUP(
2858 /* IP4_31_28 [4] */ 2864 /* IP4_31_28 [4] */
2859 FN_DU0_DR6, 0, FN_RX2_C, 0, 0, 0, FN_A6, 0, 2865 FN_DU0_DR6, 0, FN_RX2_C, 0, 0, 0, FN_A6, 0,
2860 0, 0, 0, 0, 0, 0, 0, 0, 2866 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2878,10 +2884,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2878 0, 0, 0, 0, 0, 0, 0, 0, 2884 0, 0, 0, 0, 0, 0, 0, 0,
2879 /* IP4_3_0 [4] */ 2885 /* IP4_3_0 [4] */
2880 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 0, 0, 0, 0, 2886 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 0, 0, 0, 0,
2881 0, 0, 0, 0, 0, 0, 0, 0, 0, } 2887 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
2882 }, 2888 },
2883 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32, 2889 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2884 4, 4, 4, 4, 4, 4, 4, 4) { 2890 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2891 GROUP(
2885 /* IP5_31_28 [4] */ 2892 /* IP5_31_28 [4] */
2886 FN_DU0_DG6, 0, FN_HRX1_C, 0, 0, 0, FN_A14, 0, 0, 0, 2893 FN_DU0_DG6, 0, FN_HRX1_C, 0, 0, 0, FN_A14, 0, 0, 0,
2887 0, 0, 0, 0, 0, 0, 2894 0, 0, 0, 0, 0, 0,
@@ -2905,10 +2912,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2905 0, 0, 0, 0, 0, 0, 0, 0, 2912 0, 0, 0, 0, 0, 0, 0, 0,
2906 /* IP5_3_0 [4] */ 2913 /* IP5_3_0 [4] */
2907 FN_DU0_DR7, 0, FN_TX2_C, 0, FN_PWM2_B, 0, FN_A7, 0, 2914 FN_DU0_DR7, 0, FN_TX2_C, 0, FN_PWM2_B, 0, FN_A7, 0,
2908 0, 0, 0, 0, 0, 0, 0, 0, } 2915 0, 0, 0, 0, 0, 0, 0, 0, ))
2909 }, 2916 },
2910 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32, 2917 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2911 4, 4, 4, 4, 4, 4, 4, 4) { 2918 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2919 GROUP(
2912 /* IP6_31_28 [4] */ 2920 /* IP6_31_28 [4] */
2913 FN_DU0_DB6, 0, 0, 0, 0, 0, FN_A22, 0, 0, 2921 FN_DU0_DB6, 0, 0, 0, 0, 0, FN_A22, 0, 0,
2914 0, 0, 0, 0, 0, 0, 0, 2922 0, 0, 0, 0, 0, 0, 0,
@@ -2932,10 +2940,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2932 0, 0, 0, 0, 0, 0, 0, 0, 0, 2940 0, 0, 0, 0, 0, 0, 0, 0, 0,
2933 /* IP6_3_0 [4] */ 2941 /* IP6_3_0 [4] */
2934 FN_DU0_DG7, 0, FN_HTX1_C, 0, FN_PWM6_B, 0, FN_A15, 2942 FN_DU0_DG7, 0, FN_HTX1_C, 0, FN_PWM6_B, 0, FN_A15,
2935 0, 0, 0, 0, 0, 0, 0, 0, 0, } 2943 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
2936 }, 2944 },
2937 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32, 2945 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
2938 4, 4, 4, 4, 4, 4, 4, 4) { 2946 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2947 GROUP(
2939 /* IP7_31_28 [4] */ 2948 /* IP7_31_28 [4] */
2940 FN_DU0_DISP, 0, 0, 0, FN_CAN1_RX_C, 0, 0, 0, 0, 0, 0, 2949 FN_DU0_DISP, 0, 0, 0, FN_CAN1_RX_C, 0, 0, 0, 0, 0, 0,
2941 0, 0, 0, 0, 0, 2950 0, 0, 0, 0, 0,
@@ -2959,10 +2968,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2959 0, 0, 0, 0, 0, 0, 2968 0, 0, 0, 0, 0, 0,
2960 /* IP7_3_0 [4] */ 2969 /* IP7_3_0 [4] */
2961 FN_DU0_DB7, 0, 0, 0, 0, 0, FN_A23, 0, 0, 2970 FN_DU0_DB7, 0, 0, 0, 0, 0, FN_A23, 0, 0,
2962 0, 0, 0, 0, 0, 0, 0, } 2971 0, 0, 0, 0, 0, 0, 0, ))
2963 }, 2972 },
2964 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32, 2973 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32,
2965 4, 4, 4, 4, 4, 4, 4, 4) { 2974 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2975 GROUP(
2966 /* IP8_31_28 [4] */ 2976 /* IP8_31_28 [4] */
2967 FN_VI1_DATA5, 0, 0, 0, FN_AVB_RXD4, FN_ETH_LINK, 0, 0, 0, 0, 2977 FN_VI1_DATA5, 0, 0, 0, FN_AVB_RXD4, FN_ETH_LINK, 0, 0, 0, 0,
2968 0, 0, 0, 0, 0, 0, 2978 0, 0, 0, 0, 0, 0,
@@ -2986,10 +2996,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2986 0, 0, 0, 0, 0, 0, 0, 2996 0, 0, 0, 0, 0, 0, 0,
2987 /* IP8_3_0 [4] */ 2997 /* IP8_3_0 [4] */
2988 FN_DU0_CDE, 0, 0, 0, FN_CAN1_TX_C, 0, 0, 0, 0, 0, 0, 0, 2998 FN_DU0_CDE, 0, 0, 0, FN_CAN1_TX_C, 0, 0, 0, 0, 0, 0, 0,
2989 0, 0, 0, 0, } 2999 0, 0, 0, 0, ))
2990 }, 3000 },
2991 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32, 3001 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32,
2992 4, 4, 4, 4, 4, 4, 4, 4) { 3002 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3003 GROUP(
2993 /* IP9_31_28 [4] */ 3004 /* IP9_31_28 [4] */
2994 FN_VI1_DATA9, 0, 0, FN_SDA2_B, FN_AVB_TXD0, 0, 0, 0, 0, 0, 0, 3005 FN_VI1_DATA9, 0, 0, FN_SDA2_B, FN_AVB_TXD0, 0, 0, 0, 0, 0, 0,
2995 0, 0, 0, 0, 0, 3006 0, 0, 0, 0, 0,
@@ -3013,10 +3024,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3013 0, 0, 0, 0, 0, 0, 3024 0, 0, 0, 0, 0, 0,
3014 /* IP9_3_0 [4] */ 3025 /* IP9_3_0 [4] */
3015 FN_VI1_DATA6, 0, 0, 0, FN_AVB_RXD5, FN_ETH_TXD1, 0, 0, 0, 0, 3026 FN_VI1_DATA6, 0, 0, 0, FN_AVB_RXD5, FN_ETH_TXD1, 0, 0, 0, 0,
3016 0, 0, 0, 0, 0, 0, } 3027 0, 0, 0, 0, 0, 0, ))
3017 }, 3028 },
3018 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060068, 32, 3029 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060068, 32,
3019 4, 4, 4, 4, 4, 4, 4, 4) { 3030 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3031 GROUP(
3020 /* IP10_31_28 [4] */ 3032 /* IP10_31_28 [4] */
3021 FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, 0, 0, 3033 FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, 0, 0,
3022 FN_SSI_SCK6_B, FN_VI0_G0, 0, 0, 0, 0, 0, 0, 0, 0, 3034 FN_SSI_SCK6_B, FN_VI0_G0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3041,10 +3053,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3041 0, 0, 0, 0, 0, 0, 0, 3053 0, 0, 0, 0, 0, 0, 0,
3042 /* IP10_3_0 [4] */ 3054 /* IP10_3_0 [4] */
3043 FN_VI1_DATA10, 0, 0, FN_CAN0_RX_B, FN_AVB_TXD1, 0, 0, 0, 0, 3055 FN_VI1_DATA10, 0, 0, FN_CAN0_RX_B, FN_AVB_TXD1, 0, 0, 0, 0,
3044 0, 0, 0, 0, 0, 0, 0, } 3056 0, 0, 0, 0, 0, 0, 0, ))
3045 }, 3057 },
3046 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606006C, 32, 3058 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606006C, 32,
3047 4, 4, 4, 4, 4, 4, 4, 4) { 3059 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3060 GROUP(
3048 /* IP11_31_28 [4] */ 3061 /* IP11_31_28 [4] */
3049 FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 0, 0, 3062 FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 0, 0,
3050 0, 0, 0, 0, 0, 0, 0, 0, 0, 3063 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3072,10 +3085,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3072 0, 0, 0, 0, 0, 0, 0, 0, 3085 0, 0, 0, 0, 0, 0, 0, 0,
3073 /* IP11_3_0 [4] */ 3086 /* IP11_3_0 [4] */
3074 FN_SDA1_A, FN_TX4_A, 0, FN_DU1_DR1, 0, 0, FN_SSI_WS6_B, 3087 FN_SDA1_A, FN_TX4_A, 0, FN_DU1_DR1, 0, 0, FN_SSI_WS6_B,
3075 FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, } 3088 FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, ))
3076 }, 3089 },
3077 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060070, 32, 3090 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060070, 32,
3078 4, 4, 4, 4, 4, 4, 4, 4) { 3091 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3092 GROUP(
3079 /* IP12_31_28 [4] */ 3093 /* IP12_31_28 [4] */
3080 FN_SD2_DAT2, FN_RX2_A, 0, FN_DU1_DB0, FN_SSI_SDATA2_B, 0, 0, 3094 FN_SD2_DAT2, FN_RX2_A, 0, FN_DU1_DB0, FN_SSI_SDATA2_B, 0, 0,
3081 0, 0, 0, 0, 0, 0, 0, 0, 0, 3095 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3099,10 +3113,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3099 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3113 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3100 /* IP12_3_0 [4] */ 3114 /* IP12_3_0 [4] */
3101 FN_HTX1_A, FN_SDA4_A, 0, FN_DU1_DG1, FN_TX0_A, 0, 0, 0, 0, 0, 3115 FN_HTX1_A, FN_SDA4_A, 0, FN_DU1_DG1, FN_TX0_A, 0, 0, 0, 0, 0,
3102 0, 0, 0, 0, 0, 0, } 3116 0, 0, 0, 0, 0, 0, ))
3103 }, 3117 },
3104 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060074, 32, 3118 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060074, 32,
3105 4, 4, 4, 4, 4, 4, 4, 4) { 3119 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3120 GROUP(
3106 /* IP13_31_28 [4] */ 3121 /* IP13_31_28 [4] */
3107 FN_SSI_SCK5_A, 0, 0, FN_DU1_DOTCLKOUT1, 0, 0, 0, 0, 0, 0, 0, 3122 FN_SSI_SCK5_A, 0, 0, FN_DU1_DOTCLKOUT1, 0, 0, 0, 0, 0, 0, 0,
3108 0, 0, 0, 0, 0, 3123 0, 0, 0, 0, 0,
@@ -3127,10 +3142,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3127 0, 0, 0, 0, 0, 0, 0, 0, 0, 3142 0, 0, 0, 0, 0, 0, 0, 0, 0,
3128 /* IP13_3_0 [4] */ 3143 /* IP13_3_0 [4] */
3129 FN_SD2_DAT3, FN_TX2_A, 0, FN_DU1_DB1, FN_SSI_WS9_B, 0, 0, 0, 3144 FN_SD2_DAT3, FN_TX2_A, 0, FN_DU1_DB1, FN_SSI_WS9_B, 0, 0, 0,
3130 0, 0, 0, 0, 0, 0, 0, 0, } 3145 0, 0, 0, 0, 0, 0, 0, 0, ))
3131 }, 3146 },
3132 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060078, 32, 3147 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060078, 32,
3133 4, 4, 4, 4, 4, 4, 4, 4) { 3148 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3149 GROUP(
3134 /* IP14_31_28 [4] */ 3150 /* IP14_31_28 [4] */
3135 FN_SSI_SDATA7_A, 0, 0, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, 3151 FN_SSI_SDATA7_A, 0, 0, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
3136 FN_VI0_G5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3152 FN_VI0_G5, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3154,10 +3170,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3154 0, 0, 0, 0, 0, 0, 0, 0, 0, 3170 0, 0, 0, 0, 0, 0, 0, 0, 0,
3155 /* IP14_3_0 [4] */ 3171 /* IP14_3_0 [4] */
3156 FN_SSI_WS5_A, 0, FN_SCL3_C, FN_DU1_DOTCLKIN, 0, 0, 0, 0, 0, 0, 3172 FN_SSI_WS5_A, 0, FN_SCL3_C, FN_DU1_DOTCLKIN, 0, 0, 0, 0, 0, 0,
3157 0, 0, 0, 0, 0, 0, } 3173 0, 0, 0, 0, 0, 0, ))
3158 }, 3174 },
3159 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606007C, 32, 3175 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606007C, 32,
3160 4, 4, 4, 4, 4, 4, 4, 4) { 3176 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3177 GROUP(
3161 /* IP15_31_28 [4] */ 3178 /* IP15_31_28 [4] */
3162 FN_SSI_WS4_A, 0, FN_AVB_PHY_INT, 0, 0, 0, FN_VI0_R5, 0, 0, 0, 3179 FN_SSI_WS4_A, 0, FN_AVB_PHY_INT, 0, 0, 0, FN_VI0_R5, 0, 0, 0,
3163 0, 0, 0, 0, 0, 0, 3180 0, 0, 0, 0, 0, 0,
@@ -3181,10 +3198,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3181 FN_VI0_G7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3198 FN_VI0_G7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3182 /* IP15_3_0 [4] */ 3199 /* IP15_3_0 [4] */
3183 FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, 0, 0, 0, 3200 FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, 0, 0, 0,
3184 FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, } 3201 FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
3185 }, 3202 },
3186 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060080, 32, 3203 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060080, 32,
3187 4, 4, 4, 4, 4, 4, 4, 4) { 3204 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3205 GROUP(
3188 /* IP16_31_28 [4] */ 3206 /* IP16_31_28 [4] */
3189 FN_SSI_SDATA2_A, FN_HRTS1_N_B, 0, 0, 0, 0, 3207 FN_SSI_SDATA2_A, FN_HRTS1_N_B, 0, 0, 0, 0,
3190 FN_VI0_DATA4_VI0_B4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3208 FN_VI0_DATA4_VI0_B4, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3209,10 +3227,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3209 FN_DACK2, FN_VI0_CLK, FN_AVB_COL, 0, 0, 0, 0, 0, 0, 0, 0, 3227 FN_DACK2, FN_VI0_CLK, FN_AVB_COL, 0, 0, 0, 0, 0, 0, 0, 0,
3210 /* IP16_3_0 [4] */ 3228 /* IP16_3_0 [4] */
3211 FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0, 3229 FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0,
3212 0, 0, 0, 0, 0, 0, } 3230 0, 0, 0, 0, 0, 0, ))
3213 }, 3231 },
3214 { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32, 3232 { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32,
3215 4, 4, 4, 4, 4, 4, 4, 4) { 3233 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3234 GROUP(
3216 /* IP17_31_28 [4] */ 3235 /* IP17_31_28 [4] */
3217 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3236 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3218 /* IP17_27_24 [4] */ 3237 /* IP17_27_24 [4] */
@@ -3235,11 +3254,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3235 FN_VI0_DATA6_VI0_B6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3254 FN_VI0_DATA6_VI0_B6, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3236 /* IP17_3_0 [4] */ 3255 /* IP17_3_0 [4] */
3237 FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, 0, 0, FN_EX_WAIT1, 3256 FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, 0, 0, FN_EX_WAIT1,
3238 FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, } 3257 FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
3239 }, 3258 },
3240 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32, 3259 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32,
3241 1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 2, 1, 3, 3, 3260 GROUP(1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 2, 1,
3242 1, 2, 3, 3, 1) { 3261 3, 3, 1, 2, 3, 3, 1),
3262 GROUP(
3243 /* RESERVED [1] */ 3263 /* RESERVED [1] */
3244 0, 0, 3264 0, 0,
3245 /* RESERVED [1] */ 3265 /* RESERVED [1] */
@@ -3282,11 +3302,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3282 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, 3302 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
3283 FN_SEL_I2C00_4, 0, 0, 0, 3303 FN_SEL_I2C00_4, 0, 0, 0,
3284 /* SEL_AVB [1] */ 3304 /* SEL_AVB [1] */
3285 FN_SEL_AVB_0, FN_SEL_AVB_1, } 3305 FN_SEL_AVB_0, FN_SEL_AVB_1, ))
3286 }, 3306 },
3287 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32, 3307 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32,
3288 1, 3, 3, 2, 2, 1, 2, 2, 3308 GROUP(1, 3, 3, 2, 2, 1, 2, 2, 2, 1, 1, 1,
3289 2, 1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 1) { 3309 1, 1, 2, 1, 1, 2, 2, 1),
3310 GROUP(
3290 /* SEL_SCIFCLK [1] */ 3311 /* SEL_SCIFCLK [1] */
3291 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, 3312 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
3292 /* SEL_SCIF5 [3] */ 3313 /* SEL_SCIF5 [3] */
@@ -3328,11 +3349,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3328 /* SEL_HSCIF1 [2] */ 3349 /* SEL_HSCIF1 [2] */
3329 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 0, 3350 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 0,
3330 /* SEL_HSCIF0 [1] */ 3351 /* SEL_HSCIF0 [1] */
3331 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,} 3352 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, ))
3332 }, 3353 },
3333 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32, 3354 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32,
3334 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3355 GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
3335 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) { 3356 2, 2, 2, 2, 2, 2, 2, 2, 2),
3357 GROUP(
3336 /* RESERVED [1] */ 3358 /* RESERVED [1] */
3337 0, 0, 3359 0, 0,
3338 /* RESERVED [1] */ 3360 /* RESERVED [1] */
@@ -3374,7 +3396,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3374 /* SEL_SSI1 [2] */ 3396 /* SEL_SSI1 [2] */
3375 FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3, 3397 FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,
3376 /* SEL_SSI0 [2] */ 3398 /* SEL_SSI0 [2] */
3377 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, } 3399 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, ))
3378 }, 3400 },
3379 { }, 3401 { },
3380}; 3402};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index 068b5e6334d1..49fe52d35f30 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -2104,7 +2104,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
2104}; 2104};
2105 2105
2106static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2106static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2107 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { 2107 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1, GROUP(
2108 GP_0_31_FN, FN_IP1_14_11, 2108 GP_0_31_FN, FN_IP1_14_11,
2109 GP_0_30_FN, FN_IP1_10_8, 2109 GP_0_30_FN, FN_IP1_10_8,
2110 GP_0_29_FN, FN_IP1_7_5, 2110 GP_0_29_FN, FN_IP1_7_5,
@@ -2136,9 +2136,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2136 GP_0_3_FN, FN_IP0_4_2, 2136 GP_0_3_FN, FN_IP0_4_2,
2137 GP_0_2_FN, FN_PENC1, 2137 GP_0_2_FN, FN_PENC1,
2138 GP_0_1_FN, FN_PENC0, 2138 GP_0_1_FN, FN_PENC0,
2139 GP_0_0_FN, FN_IP0_1_0 } 2139 GP_0_0_FN, FN_IP0_1_0 ))
2140 }, 2140 },
2141 { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) { 2141 { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1, GROUP(
2142 GP_1_31_FN, FN_IP4_6_4, 2142 GP_1_31_FN, FN_IP4_6_4,
2143 GP_1_30_FN, FN_IP4_3_1, 2143 GP_1_30_FN, FN_IP4_3_1,
2144 GP_1_29_FN, FN_IP4_0, 2144 GP_1_29_FN, FN_IP4_0,
@@ -2170,9 +2170,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2170 GP_1_3_FN, FN_IP1_27_25, 2170 GP_1_3_FN, FN_IP1_27_25,
2171 GP_1_2_FN, FN_IP1_24, 2171 GP_1_2_FN, FN_IP1_24,
2172 GP_1_1_FN, FN_WE0, 2172 GP_1_1_FN, FN_WE0,
2173 GP_1_0_FN, FN_IP1_23_21 } 2173 GP_1_0_FN, FN_IP1_23_21 ))
2174 }, 2174 },
2175 { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) { 2175 { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1, GROUP(
2176 GP_2_31_FN, FN_IP6_7, 2176 GP_2_31_FN, FN_IP6_7,
2177 GP_2_30_FN, FN_IP6_6_5, 2177 GP_2_30_FN, FN_IP6_6_5,
2178 GP_2_29_FN, FN_IP6_4_2, 2178 GP_2_29_FN, FN_IP6_4_2,
@@ -2204,9 +2204,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2204 GP_2_3_FN, FN_IP4_12_11, 2204 GP_2_3_FN, FN_IP4_12_11,
2205 GP_2_2_FN, FN_IP4_10_9, 2205 GP_2_2_FN, FN_IP4_10_9,
2206 GP_2_1_FN, FN_IP4_8, 2206 GP_2_1_FN, FN_IP4_8,
2207 GP_2_0_FN, FN_IP4_7 } 2207 GP_2_0_FN, FN_IP4_7 ))
2208 }, 2208 },
2209 { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) { 2209 { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1, GROUP(
2210 GP_3_31_FN, FN_IP8_10_9, 2210 GP_3_31_FN, FN_IP8_10_9,
2211 GP_3_30_FN, FN_IP8_8_6, 2211 GP_3_30_FN, FN_IP8_8_6,
2212 GP_3_29_FN, FN_IP8_5_3, 2212 GP_3_29_FN, FN_IP8_5_3,
@@ -2238,9 +2238,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2238 GP_3_3_FN, FN_IP6_10, 2238 GP_3_3_FN, FN_IP6_10,
2239 GP_3_2_FN, FN_SSI_SCK34, 2239 GP_3_2_FN, FN_SSI_SCK34,
2240 GP_3_1_FN, FN_IP6_9, 2240 GP_3_1_FN, FN_IP6_9,
2241 GP_3_0_FN, FN_IP6_8 } 2241 GP_3_0_FN, FN_IP6_8 ))
2242 }, 2242 },
2243 { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) { 2243 { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1, GROUP(
2244 0, 0, 2244 0, 0,
2245 0, 0, 2245 0, 0,
2246 0, 0, 2246 0, 0,
@@ -2272,12 +2272,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2272 GP_4_3_FN, FN_IP8_21_19, 2272 GP_4_3_FN, FN_IP8_21_19,
2273 GP_4_2_FN, FN_IP8_18_16, 2273 GP_4_2_FN, FN_IP8_18_16,
2274 GP_4_1_FN, FN_IP8_15_14, 2274 GP_4_1_FN, FN_IP8_15_14,
2275 GP_4_0_FN, FN_IP8_13_11 } 2275 GP_4_0_FN, FN_IP8_13_11 ))
2276 }, 2276 },
2277 2277
2278 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32, 2278 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
2279 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2279 GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2280 1, 1, 1, 1, 1, 1, 3, 4, 3, 3, 2) { 2280 1, 1, 1, 1, 1, 3, 4, 3, 3, 2),
2281 GROUP(
2281 /* IP0_31 [1] */ 2282 /* IP0_31 [1] */
2282 0, 0, 2283 0, 0,
2283 /* IP0_30 [1] */ 2284 /* IP0_30 [1] */
@@ -2328,10 +2329,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2328 FN_TX2_E, FN_SDA2_B, 0, 0, 2329 FN_TX2_E, FN_SDA2_B, 0, 0,
2329 /* IP0_1_0 [2] */ 2330 /* IP0_1_0 [2] */
2330 FN_PRESETOUT, 0, FN_PWM1, 0, 2331 FN_PRESETOUT, 0, FN_PWM1, 0,
2331 } 2332 ))
2332 }, 2333 },
2333 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32, 2334 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
2334 1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3, 3, 1, 1) { 2335 GROUP(1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3,
2336 3, 1, 1),
2337 GROUP(
2335 /* IP1_31 [1] */ 2338 /* IP1_31 [1] */
2336 0, 0, 2339 0, 0,
2337 /* IP1_30 [1] */ 2340 /* IP1_30 [1] */
@@ -2371,11 +2374,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2371 FN_A21, FN_HSPI_CLK1_B, 2374 FN_A21, FN_HSPI_CLK1_B,
2372 /* IP1_0 [1] */ 2375 /* IP1_0 [1] */
2373 FN_A20, FN_HSPI_CS1_B, 2376 FN_A20, FN_HSPI_CS1_B,
2374 } 2377 ))
2375 }, 2378 },
2376 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32, 2379 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
2377 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2380 GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2378 1, 1, 1, 1, 3, 2, 3, 3, 3, 3) { 2381 1, 1, 1, 3, 2, 3, 3, 3, 3),
2382 GROUP(
2379 /* IP2_31 [1] */ 2383 /* IP2_31 [1] */
2380 FN_MLB_CLK, FN_IRQ1_A, 2384 FN_MLB_CLK, FN_IRQ1_A,
2381 /* IP2_30 [1] */ 2385 /* IP2_30 [1] */
@@ -2423,11 +2427,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2423 /* IP2_2_0 [3] */ 2427 /* IP2_2_0 [3] */
2424 FN_SD1_CLK_A, FN_MMC_CLK, 0, FN_ATACS00, 2428 FN_SD1_CLK_A, FN_MMC_CLK, 0, FN_ATACS00,
2425 FN_EX_CS2, 0, 0, 0, 2429 FN_EX_CS2, 0, 0, 0,
2426 } 2430 ))
2427 }, 2431 },
2428 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32, 2432 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
2429 1, 1, 1, 1, 1, 3, 3, 2, 2433 GROUP(1, 1, 1, 1, 1, 3, 3, 2, 3, 3, 3, 2,
2430 3, 3, 3, 2, 3, 3, 2) { 2434 3, 3, 2),
2435 GROUP(
2431 /* IP3_31 [1] */ 2436 /* IP3_31 [1] */
2432 FN_DU0_DR6, FN_LCDOUT6, 2437 FN_DU0_DR6, FN_LCDOUT6,
2433 /* IP3_30 [1] */ 2438 /* IP3_30 [1] */
@@ -2465,10 +2470,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2465 FN_SDSELF_B, 0, 0, 0, 2470 FN_SDSELF_B, 0, 0, 0,
2466 /* IP3_1_0 [2] */ 2471 /* IP3_1_0 [2] */
2467 FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A, 2472 FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A,
2468 } 2473 ))
2469 }, 2474 },
2470 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32, 2475 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
2471 1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1, 3, 3, 1) { 2476 GROUP(1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1,
2477 3, 3, 1),
2478 GROUP(
2472 /* IP4_31 [1] */ 2479 /* IP4_31 [1] */
2473 0, 0, 2480 0, 0,
2474 /* IP4_30_29 [2] */ 2481 /* IP4_30_29 [2] */
@@ -2507,10 +2514,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2507 FN_TX1_D, FN_CAN0_TX_A, FN_ADICHS0, 0, 2514 FN_TX1_D, FN_CAN0_TX_A, FN_ADICHS0, 0,
2508 /* IP4_0 [1] */ 2515 /* IP4_0 [1] */
2509 FN_DU0_DR7, FN_LCDOUT7, 2516 FN_DU0_DR7, FN_LCDOUT7,
2510 } 2517 ))
2511 }, 2518 },
2512 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32, 2519 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
2513 1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1, 1, 2, 2, 2) { 2520 GROUP(1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1,
2521 1, 2, 2, 2),
2522 GROUP(
2514 2523
2515 /* IP5_31 [1] */ 2524 /* IP5_31 [1] */
2516 0, 0, 2525 0, 0,
@@ -2551,11 +2560,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2551 FN_VI1_DATA10_B, FN_DU0_DB6, FN_LCDOUT22, 0, 2560 FN_VI1_DATA10_B, FN_DU0_DB6, FN_LCDOUT22, 0,
2552 /* IP5_1_0 [2] */ 2561 /* IP5_1_0 [2] */
2553 FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, 0, 2562 FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, 0,
2554 } 2563 ))
2555 }, 2564 },
2556 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32, 2565 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
2557 2, 2, 2, 2, 2, 1, 2, 2, 1, 2, 2566 GROUP(2, 2, 2, 2, 2, 1, 2, 2, 1, 2, 1, 2,
2558 1, 2, 1, 1, 1, 1, 2, 3, 2) { 2567 1, 1, 1, 1, 2, 3, 2),
2568 GROUP(
2559 /* IP6_31_30 [2] */ 2569 /* IP6_31_30 [2] */
2560 FN_SD0_DAT2, 0, FN_SUB_TDI, 0, 2570 FN_SD0_DAT2, 0, FN_SUB_TDI, 0,
2561 /* IP6_29_28 [2] */ 2571 /* IP6_29_28 [2] */
@@ -2602,10 +2612,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2602 /* IP6_1_0 [2] */ 2612 /* IP6_1_0 [2] */
2603 FN_SSI_SCK6, FN_HSPI_RX2_A, 2613 FN_SSI_SCK6, FN_HSPI_RX2_A,
2604 FN_FMCLK_B, FN_CAN1_TX_B, 2614 FN_FMCLK_B, FN_CAN1_TX_B,
2605 } 2615 ))
2606 }, 2616 },
2607 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32, 2617 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
2608 3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2) { 2618 GROUP(3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2),
2619 GROUP(
2609 2620
2610 /* IP7_31_29 [3] */ 2621 /* IP7_31_29 [3] */
2611 FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, FN_DU1_DR2, 2622 FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, FN_DU1_DR2,
@@ -2641,10 +2652,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2641 FN_SD0_CD, 0, FN_TX5_A, 0, 2652 FN_SD0_CD, 0, FN_TX5_A, 0,
2642 /* IP7_1_0 [2] */ 2653 /* IP7_1_0 [2] */
2643 FN_SD0_DAT3, 0, FN_IRQ1_B, 0, 2654 FN_SD0_DAT3, 0, FN_IRQ1_B, 0,
2644 } 2655 ))
2645 }, 2656 },
2646 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32, 2657 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
2647 1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3) { 2658 GROUP(1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3),
2659 GROUP(
2648 /* IP8_31 [1] */ 2660 /* IP8_31 [1] */
2649 0, 0, 2661 0, 0,
2650 /* IP8_30 [1] */ 2662 /* IP8_30 [1] */
@@ -2681,10 +2693,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2681 /* IP8_2_0 [3] */ 2693 /* IP8_2_0 [3] */
2682 FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3, 2694 FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3,
2683 0, FN_HSPI_TX1_A, FN_TX3_B, 0, 2695 0, FN_HSPI_TX1_A, FN_TX3_B, 0,
2684 } 2696 ))
2685 }, 2697 },
2686 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32, 2698 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
2687 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { 2699 GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
2700 GROUP(
2688 /* IP9_31 [1] */ 2701 /* IP9_31 [1] */
2689 0, 0, 2702 0, 0,
2690 /* IP9_30 [1] */ 2703 /* IP9_30 [1] */
@@ -2723,10 +2736,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2723 /* IP9_2_0 [3] */ 2736 /* IP9_2_0 [3] */
2724 FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6, 2737 FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6,
2725 0, FN_HRTS1_B, 0, 0, 2738 0, FN_HRTS1_B, 0, 0,
2726 } 2739 ))
2727 }, 2740 },
2728 { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32, 2741 { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
2729 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4, 3, 3, 3) { 2742 GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4,
2743 3, 3, 3),
2744 GROUP(
2730 2745
2731 /* IP10_31 [1] */ 2746 /* IP10_31 [1] */
2732 0, 0, 2747 0, 0,
@@ -2772,11 +2787,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2772 FN_ATARD1, FN_ETH_MDC, 2787 FN_ATARD1, FN_ETH_MDC,
2773 FN_SDA1_B, 0, 2788 FN_SDA1_B, 0,
2774 0, 0, 2789 0, 0,
2775 } 2790 ))
2776 }, 2791 },
2777 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32, 2792 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,
2778 1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2, 2793 GROUP(1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
2779 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { 2794 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
2795 GROUP(
2780 2796
2781 /* SEL 31 [1] */ 2797 /* SEL 31 [1] */
2782 0, 0, 2798 0, 0,
@@ -2835,11 +2851,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2835 FN_SEL_WAIT2_A, FN_SEL_WAIT2_B, 2851 FN_SEL_WAIT2_A, FN_SEL_WAIT2_B,
2836 /* SEL_0 (WAIT1) [1] */ 2852 /* SEL_0 (WAIT1) [1] */
2837 FN_SEL_WAIT1_A, FN_SEL_WAIT1_B, 2853 FN_SEL_WAIT1_A, FN_SEL_WAIT1_B,
2838 } 2854 ))
2839 }, 2855 },
2840 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32, 2856 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,
2841 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 2857 GROUP(1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1,
2842 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1) { 2858 1, 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1),
2859 GROUP(
2843 2860
2844 /* SEL_31 [1] */ 2861 /* SEL_31 [1] */
2845 0, 0, 2862 0, 0,
@@ -2899,7 +2916,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2899 FN_SEL_I2C2_C, 0, 2916 FN_SEL_I2C2_C, 0,
2900 /* SEL_0 (I2C1) [1] */ 2917 /* SEL_0 (I2C1) [1] */
2901 FN_SEL_I2C1_A, FN_SEL_I2C1_B, 2918 FN_SEL_I2C1_A, FN_SEL_I2C1_B,
2902 } 2919 ))
2903 }, 2920 },
2904 { }, 2921 { },
2905}; 2922};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 64bace100316..0c121b28ec3f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1595,6 +1595,92 @@ static const unsigned int ether_magic_pins[] = {
1595static const unsigned int ether_magic_mux[] = { 1595static const unsigned int ether_magic_mux[] = {
1596 ETH_MAGIC_MARK, 1596 ETH_MAGIC_MARK,
1597}; 1597};
1598/* - HSCIF0 ----------------------------------------------------------------- */
1599static const unsigned int hscif0_data_pins[] = {
1600 /* TX, RX */
1601 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21)
1602};
1603static const unsigned int hscif0_data_mux[] = {
1604 HTX0_MARK, HRX0_MARK
1605};
1606static const unsigned int hscif0_data_b_pins[] = {
1607 /* TX, RX */
1608 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13)
1609};
1610static const unsigned int hscif0_data_b_mux[] = {
1611 HTX0_B_MARK, HRX0_B_MARK
1612};
1613static const unsigned int hscif0_ctrl_pins[] = {
1614 /* CTS, RTS */
1615 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19)
1616};
1617static const unsigned int hscif0_ctrl_mux[] = {
1618 HCTS0_MARK, HRTS0_MARK
1619};
1620static const unsigned int hscif0_ctrl_b_pins[] = {
1621 /* CTS, RTS */
1622 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10)
1623};
1624static const unsigned int hscif0_ctrl_b_mux[] = {
1625 HCTS0_B_MARK, HRTS0_B_MARK
1626};
1627static const unsigned int hscif0_clk_pins[] = {
1628 /* SCK */
1629 RCAR_GP_PIN(4, 17)
1630};
1631static const unsigned int hscif0_clk_mux[] = {
1632 HSCK0_MARK
1633};
1634static const unsigned int hscif0_clk_b_pins[] = {
1635 /* SCK */
1636 RCAR_GP_PIN(3, 11)
1637};
1638static const unsigned int hscif0_clk_b_mux[] = {
1639 HSCK0_B_MARK
1640};
1641/* - HSCIF1 ----------------------------------------------------------------- */
1642static const unsigned int hscif1_data_pins[] = {
1643 /* TX, RX */
1644 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20)
1645};
1646static const unsigned int hscif1_data_mux[] = {
1647 HTX1_MARK, HRX1_MARK
1648};
1649static const unsigned int hscif1_data_b_pins[] = {
1650 /* TX, RX */
1651 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3)
1652};
1653static const unsigned int hscif1_data_b_mux[] = {
1654 HTX1_B_MARK, HRX1_B_MARK
1655};
1656static const unsigned int hscif1_ctrl_pins[] = {
1657 /* CTS, RTS */
1658 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22)
1659};
1660static const unsigned int hscif1_ctrl_mux[] = {
1661 HCTS1_MARK, HRTS1_MARK
1662};
1663static const unsigned int hscif1_ctrl_b_pins[] = {
1664 /* CTS, RTS */
1665 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6)
1666};
1667static const unsigned int hscif1_ctrl_b_mux[] = {
1668 HCTS1_B_MARK, HRTS1_B_MARK
1669};
1670static const unsigned int hscif1_clk_pins[] = {
1671 /* SCK */
1672 RCAR_GP_PIN(0, 18)
1673};
1674static const unsigned int hscif1_clk_mux[] = {
1675 HSCK1_MARK
1676};
1677static const unsigned int hscif1_clk_b_pins[] = {
1678 /* SCK */
1679 RCAR_GP_PIN(2, 4)
1680};
1681static const unsigned int hscif1_clk_b_mux[] = {
1682 HSCK1_B_MARK
1683};
1598/* - HSPI0 ------------------------------------------------------------------ */ 1684/* - HSPI0 ------------------------------------------------------------------ */
1599static const unsigned int hspi0_pins[] = { 1685static const unsigned int hspi0_pins[] = {
1600 /* CLK, CS, RX, TX */ 1686 /* CLK, CS, RX, TX */
@@ -2618,6 +2704,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2618 SH_PFC_PIN_GROUP(ether_rmii), 2704 SH_PFC_PIN_GROUP(ether_rmii),
2619 SH_PFC_PIN_GROUP(ether_link), 2705 SH_PFC_PIN_GROUP(ether_link),
2620 SH_PFC_PIN_GROUP(ether_magic), 2706 SH_PFC_PIN_GROUP(ether_magic),
2707 SH_PFC_PIN_GROUP(hscif0_data),
2708 SH_PFC_PIN_GROUP(hscif0_data_b),
2709 SH_PFC_PIN_GROUP(hscif0_ctrl),
2710 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
2711 SH_PFC_PIN_GROUP(hscif0_clk),
2712 SH_PFC_PIN_GROUP(hscif0_clk_b),
2713 SH_PFC_PIN_GROUP(hscif1_data),
2714 SH_PFC_PIN_GROUP(hscif1_data_b),
2715 SH_PFC_PIN_GROUP(hscif1_ctrl),
2716 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
2717 SH_PFC_PIN_GROUP(hscif1_clk),
2718 SH_PFC_PIN_GROUP(hscif1_clk_b),
2621 SH_PFC_PIN_GROUP(hspi0), 2719 SH_PFC_PIN_GROUP(hspi0),
2622 SH_PFC_PIN_GROUP(hspi1), 2720 SH_PFC_PIN_GROUP(hspi1),
2623 SH_PFC_PIN_GROUP(hspi1_b), 2721 SH_PFC_PIN_GROUP(hspi1_b),
@@ -2783,6 +2881,24 @@ static const char * const ether_groups[] = {
2783 "ether_magic", 2881 "ether_magic",
2784}; 2882};
2785 2883
2884static const char * const hscif0_groups[] = {
2885 "hscif0_data",
2886 "hscif0_data_b",
2887 "hscif0_ctrl",
2888 "hscif0_ctrl_b",
2889 "hscif0_clk",
2890 "hscif0_clk_b",
2891};
2892
2893static const char * const hscif1_groups[] = {
2894 "hscif1_data",
2895 "hscif1_data_b",
2896 "hscif1_ctrl",
2897 "hscif1_ctrl_b",
2898 "hscif1_clk",
2899 "hscif1_clk_b",
2900};
2901
2786static const char * const hspi0_groups[] = { 2902static const char * const hspi0_groups[] = {
2787 "hspi0", 2903 "hspi0",
2788}; 2904};
@@ -3005,6 +3121,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
3005 SH_PFC_FUNCTION(du0), 3121 SH_PFC_FUNCTION(du0),
3006 SH_PFC_FUNCTION(du1), 3122 SH_PFC_FUNCTION(du1),
3007 SH_PFC_FUNCTION(ether), 3123 SH_PFC_FUNCTION(ether),
3124 SH_PFC_FUNCTION(hscif0),
3125 SH_PFC_FUNCTION(hscif1),
3008 SH_PFC_FUNCTION(hspi0), 3126 SH_PFC_FUNCTION(hspi0),
3009 SH_PFC_FUNCTION(hspi1), 3127 SH_PFC_FUNCTION(hspi1),
3010 SH_PFC_FUNCTION(hspi2), 3128 SH_PFC_FUNCTION(hspi2),
@@ -3036,7 +3154,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
3036}; 3154};
3037 3155
3038static const struct pinmux_cfg_reg pinmux_config_regs[] = { 3156static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3039 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { 3157 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1, GROUP(
3040 GP_0_31_FN, FN_IP3_31_29, 3158 GP_0_31_FN, FN_IP3_31_29,
3041 GP_0_30_FN, FN_IP3_26_24, 3159 GP_0_30_FN, FN_IP3_26_24,
3042 GP_0_29_FN, FN_IP3_22_21, 3160 GP_0_29_FN, FN_IP3_22_21,
@@ -3068,9 +3186,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3068 GP_0_3_FN, FN_A17, 3186 GP_0_3_FN, FN_A17,
3069 GP_0_2_FN, FN_IP0_7_6, 3187 GP_0_2_FN, FN_IP0_7_6,
3070 GP_0_1_FN, FN_AVS2, 3188 GP_0_1_FN, FN_AVS2,
3071 GP_0_0_FN, FN_AVS1 } 3189 GP_0_0_FN, FN_AVS1 ))
3072 }, 3190 },
3073 { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) { 3191 { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1, GROUP(
3074 GP_1_31_FN, FN_IP5_23_21, 3192 GP_1_31_FN, FN_IP5_23_21,
3075 GP_1_30_FN, FN_IP5_20_17, 3193 GP_1_30_FN, FN_IP5_20_17,
3076 GP_1_29_FN, FN_IP5_16_15, 3194 GP_1_29_FN, FN_IP5_16_15,
@@ -3102,9 +3220,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3102 GP_1_3_FN, FN_IP4_10_8, 3220 GP_1_3_FN, FN_IP4_10_8,
3103 GP_1_2_FN, FN_IP4_7_5, 3221 GP_1_2_FN, FN_IP4_7_5,
3104 GP_1_1_FN, FN_IP4_4_2, 3222 GP_1_1_FN, FN_IP4_4_2,
3105 GP_1_0_FN, FN_IP4_1_0 } 3223 GP_1_0_FN, FN_IP4_1_0 ))
3106 }, 3224 },
3107 { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) { 3225 { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1, GROUP(
3108 GP_2_31_FN, FN_IP10_28_26, 3226 GP_2_31_FN, FN_IP10_28_26,
3109 GP_2_30_FN, FN_IP10_25_24, 3227 GP_2_30_FN, FN_IP10_25_24,
3110 GP_2_29_FN, FN_IP10_23_21, 3228 GP_2_29_FN, FN_IP10_23_21,
@@ -3136,9 +3254,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3136 GP_2_3_FN, FN_IP8_24_23, 3254 GP_2_3_FN, FN_IP8_24_23,
3137 GP_2_2_FN, FN_IP8_22_21, 3255 GP_2_2_FN, FN_IP8_22_21,
3138 GP_2_1_FN, FN_IP8_20, 3256 GP_2_1_FN, FN_IP8_20,
3139 GP_2_0_FN, FN_IP5_27_24 } 3257 GP_2_0_FN, FN_IP5_27_24 ))
3140 }, 3258 },
3141 { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) { 3259 { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1, GROUP(
3142 GP_3_31_FN, FN_IP6_3_2, 3260 GP_3_31_FN, FN_IP6_3_2,
3143 GP_3_30_FN, FN_IP6_1_0, 3261 GP_3_30_FN, FN_IP6_1_0,
3144 GP_3_29_FN, FN_IP5_30_29, 3262 GP_3_29_FN, FN_IP5_30_29,
@@ -3170,9 +3288,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3170 GP_3_3_FN, FN_IP11_8_6, 3288 GP_3_3_FN, FN_IP11_8_6,
3171 GP_3_2_FN, FN_IP11_5_3, 3289 GP_3_2_FN, FN_IP11_5_3,
3172 GP_3_1_FN, FN_IP11_2_0, 3290 GP_3_1_FN, FN_IP11_2_0,
3173 GP_3_0_FN, FN_IP10_31_29 } 3291 GP_3_0_FN, FN_IP10_31_29 ))
3174 }, 3292 },
3175 { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) { 3293 { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1, GROUP(
3176 GP_4_31_FN, FN_IP8_19, 3294 GP_4_31_FN, FN_IP8_19,
3177 GP_4_30_FN, FN_IP8_18, 3295 GP_4_30_FN, FN_IP8_18,
3178 GP_4_29_FN, FN_IP8_17_16, 3296 GP_4_29_FN, FN_IP8_17_16,
@@ -3204,9 +3322,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3204 GP_4_3_FN, FN_IP6_11_9, 3322 GP_4_3_FN, FN_IP6_11_9,
3205 GP_4_2_FN, FN_IP6_8, 3323 GP_4_2_FN, FN_IP6_8,
3206 GP_4_1_FN, FN_IP6_7_6, 3324 GP_4_1_FN, FN_IP6_7_6,
3207 GP_4_0_FN, FN_IP6_5_4 } 3325 GP_4_0_FN, FN_IP6_5_4 ))
3208 }, 3326 },
3209 { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1) { 3327 { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1, GROUP(
3210 GP_5_31_FN, FN_IP3_5, 3328 GP_5_31_FN, FN_IP3_5,
3211 GP_5_30_FN, FN_IP3_4, 3329 GP_5_30_FN, FN_IP3_4,
3212 GP_5_29_FN, FN_IP3_3, 3330 GP_5_29_FN, FN_IP3_3,
@@ -3238,9 +3356,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3238 GP_5_3_FN, FN_A4, 3356 GP_5_3_FN, FN_A4,
3239 GP_5_2_FN, FN_A3, 3357 GP_5_2_FN, FN_A3,
3240 GP_5_1_FN, FN_A2, 3358 GP_5_1_FN, FN_A2,
3241 GP_5_0_FN, FN_A1 } 3359 GP_5_0_FN, FN_A1 ))
3242 }, 3360 },
3243 { PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1) { 3361 { PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1, GROUP(
3244 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3362 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3245 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3363 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3246 0, 0, 0, 0, 0, 0, 0, 0, 3364 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3255,11 +3373,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3255 GP_6_3_FN, FN_IP3_15, 3373 GP_6_3_FN, FN_IP3_15,
3256 GP_6_2_FN, FN_IP3_8, 3374 GP_6_2_FN, FN_IP3_8,
3257 GP_6_1_FN, FN_IP3_7, 3375 GP_6_1_FN, FN_IP3_7,
3258 GP_6_0_FN, FN_IP3_6 } 3376 GP_6_0_FN, FN_IP3_6 ))
3259 }, 3377 },
3260 3378
3261 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32, 3379 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
3262 1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3) { 3380 GROUP(1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3),
3381 GROUP(
3263 /* IP0_31 [1] */ 3382 /* IP0_31 [1] */
3264 0, 0, 3383 0, 0,
3265 /* IP0_30_28 [3] */ 3384 /* IP0_30_28 [3] */
@@ -3294,10 +3413,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3294 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C, 3413 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
3295 /* IP0_2_0 [3] */ 3414 /* IP0_2_0 [3] */
3296 FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0, 3415 FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
3297 FN_SCIF_CLK, FN_TCLK0_C, 0, 0 } 3416 FN_SCIF_CLK, FN_TCLK0_C, 0, 0 ))
3298 }, 3417 },
3299 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32, 3418 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
3300 3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2) { 3419 GROUP(3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2),
3420 GROUP(
3301 /* IP1_31_29 [3] */ 3421 /* IP1_31_29 [3] */
3302 0, 0, 0, 0, 0, 0, 0, 0, 3422 0, 0, 0, 0, 0, 0, 0, 0,
3303 /* IP1_28_25 [4] */ 3423 /* IP1_28_25 [4] */
@@ -3332,10 +3452,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3332 /* IP1_3_2 [2] */ 3452 /* IP1_3_2 [2] */
3333 FN_EX_CS1, FN_MMC0_D7, FN_FD7, 0, 3453 FN_EX_CS1, FN_MMC0_D7, FN_FD7, 0,
3334 /* IP1_1_0 [2] */ 3454 /* IP1_1_0 [2] */
3335 FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 } 3455 FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 ))
3336 }, 3456 },
3337 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32, 3457 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
3338 1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4) { 3458 GROUP(1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4),
3459 GROUP(
3339 /* IP2_31 [1] */ 3460 /* IP2_31 [1] */
3340 0, 0, 3461 0, 0,
3341 /* IP2_30_28 [3] */ 3462 /* IP2_30_28 [3] */
@@ -3378,11 +3499,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3378 FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C, 3499 FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
3379 FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19, 3500 FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
3380 FN_CC5_STATE27, FN_CC5_STATE35, 0, 0, 3501 FN_CC5_STATE27, FN_CC5_STATE35, 0, 0,
3381 0, 0, 0, 0 } 3502 0, 0, 0, 0 ))
3382 }, 3503 },
3383 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32, 3504 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
3384 3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1, 3505 GROUP(3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1, 1,
3385 1, 3, 3, 1, 1, 1, 1, 1, 1, 3) { 3506 3, 3, 1, 1, 1, 1, 1, 1, 3),
3507 GROUP(
3386 /* IP3_31_29 [3] */ 3508 /* IP3_31_29 [3] */
3387 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, FN_TX2_C, 3509 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, FN_TX2_C,
3388 FN_SCL2_C, FN_REMOCON, 0, 0, 3510 FN_SCL2_C, FN_REMOCON, 0, 0,
@@ -3429,11 +3551,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3429 FN_DU0_DG2, FN_LCDOUT10, 3551 FN_DU0_DG2, FN_LCDOUT10,
3430 /* IP3_2_0 [3] */ 3552 /* IP3_2_0 [3] */
3431 FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2, 3553 FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
3432 FN_AUDATA3, 0, 0, 0 } 3554 FN_AUDATA3, 0, 0, 0 ))
3433 }, 3555 },
3434 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32, 3556 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
3435 3, 1, 1, 1, 1, 1, 1, 3, 3, 3557 GROUP(3, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
3436 1, 1, 1, 1, 1, 1, 3, 3, 3, 2) { 3558 1, 1, 1, 3, 3, 3, 2),
3559 GROUP(
3437 /* IP4_31_29 [3] */ 3560 /* IP4_31_29 [3] */
3438 FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, 3561 FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0,
3439 FN_TX5, FN_SCK0_D, 0, 0, 3562 FN_TX5, FN_SCK0_D, 0, 0,
@@ -3477,11 +3600,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3477 FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C, 3600 FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
3478 FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, 0, 3601 FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, 0,
3479 /* IP4_1_0 [2] */ 3602 /* IP4_1_0 [2] */
3480 FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C } 3603 FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C ))
3481 }, 3604 },
3482 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32, 3605 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
3483 1, 2, 1, 4, 3, 4, 2, 2, 3606 GROUP(1, 2, 1, 4, 3, 4, 2, 2, 2, 2, 1, 1,
3484 2, 2, 1, 1, 1, 1, 1, 1, 3) { 3607 1, 1, 1, 1, 3),
3608 GROUP(
3485 /* IP5_31 [1] */ 3609 /* IP5_31 [1] */
3486 0, 0, 3610 0, 0,
3487 /* IP5_30_29 [2] */ 3611 /* IP5_30_29 [2] */
@@ -3523,10 +3647,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3523 FN_DU1_DB2, FN_VI2_R4, 3647 FN_DU1_DB2, FN_VI2_R4,
3524 /* IP5_2_0 [3] */ 3648 /* IP5_2_0 [3] */
3525 FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1, 3649 FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
3526 FN_RX5, FN_RTS0_D_TANS_D, 0, 0 } 3650 FN_RX5, FN_RTS0_D_TANS_D, 0, 0 ))
3527 }, 3651 },
3528 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32, 3652 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
3529 1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2, 2, 2, 2) { 3653 GROUP(1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2,
3654 2, 2, 2),
3655 GROUP(
3530 /* IP6_31 [1] */ 3656 /* IP6_31 [1] */
3531 0, 0, 3657 0, 0,
3532 /* IP6_30_29 [2] */ 3658 /* IP6_30_29 [2] */
@@ -3560,10 +3686,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3560 /* IP6_3_2 [2] */ 3686 /* IP6_3_2 [2] */
3561 FN_SSI_WS0129, FN_CAN_DEBUGOUT2, FN_MOUT2, 0, 3687 FN_SSI_WS0129, FN_CAN_DEBUGOUT2, FN_MOUT2, 0,
3562 /* IP6_1_0 [2] */ 3688 /* IP6_1_0 [2] */
3563 FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 } 3689 FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 ))
3564 }, 3690 },
3565 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32, 3691 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
3566 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 2, 2) { 3692 GROUP(1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
3693 3, 2, 2),
3694 GROUP(
3567 /* IP7_31 [1] */ 3695 /* IP7_31 [1] */
3568 0, 0, 3696 0, 0,
3569 /* IP7_30_29 [2] */ 3697 /* IP7_30_29 [2] */
@@ -3596,10 +3724,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3596 /* IP7_3_2 [2] */ 3724 /* IP7_3_2 [2] */
3597 FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B, 3725 FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
3598 /* IP7_1_0 [2] */ 3726 /* IP7_1_0 [2] */
3599 FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B } 3727 FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B ))
3600 }, 3728 },
3601 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32, 3729 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
3602 1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4) { 3730 GROUP(1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4),
3731 GROUP(
3603 /* IP8_31 [1] */ 3732 /* IP8_31 [1] */
3604 0, 0, 3733 0, 0,
3605 /* IP8_30_28 [3] */ 3734 /* IP8_30_28 [3] */
@@ -3639,11 +3768,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3639 FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK, 3768 FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
3640 FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28, 3769 FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
3641 FN_CC5_STATE36, 0, 0, 0, 3770 FN_CC5_STATE36, 0, 0, 0,
3642 0, 0, 0, 0 } 3771 0, 0, 0, 0 ))
3643 }, 3772 },
3644 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32, 3773 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
3645 2, 2, 2, 2, 2, 3, 3, 2, 2, 3774 GROUP(2, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 1,
3646 2, 2, 1, 1, 1, 1, 2, 2) { 3775 1, 1, 1, 2, 2),
3776 GROUP(
3647 /* IP9_31_30 [2] */ 3777 /* IP9_31_30 [2] */
3648 0, 0, 0, 0, 3778 0, 0, 0, 0,
3649 /* IP9_29_28 [2] */ 3779 /* IP9_29_28 [2] */
@@ -3679,10 +3809,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3679 /* IP9_3_2 [2] */ 3809 /* IP9_3_2 [2] */
3680 FN_VI0_DATA1_VI0_B1, FN_HCTS1_B, FN_MT1_PWM, 0, 3810 FN_VI0_DATA1_VI0_B1, FN_HCTS1_B, FN_MT1_PWM, 0,
3681 /* IP9_1_0 [2] */ 3811 /* IP9_1_0 [2] */
3682 FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 } 3812 FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 ))
3683 }, 3813 },
3684 { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32, 3814 { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
3685 3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3) { 3815 GROUP(3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3),
3816 GROUP(
3686 /* IP10_31_29 [3] */ 3817 /* IP10_31_29 [3] */
3687 FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, FN_SIM_CLK, 3818 FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, FN_SIM_CLK,
3688 FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 0, 3819 FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 0,
@@ -3714,10 +3845,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3714 FN_DACK0_C, FN_DRACK0_C, 0, 0, 3845 FN_DACK0_C, FN_DRACK0_C, 0, 0,
3715 /* IP10_2_0 [3] */ 3846 /* IP10_2_0 [3] */
3716 FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B, 3847 FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
3717 FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 } 3848 FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 ))
3718 }, 3849 },
3719 { PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32, 3850 { PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32,
3720 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { 3851 GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
3852 GROUP(
3721 /* IP11_31_30 [2] */ 3853 /* IP11_31_30 [2] */
3722 0, 0, 0, 0, 3854 0, 0, 0, 0,
3723 /* IP11_29_27 [3] */ 3855 /* IP11_29_27 [3] */
@@ -3749,10 +3881,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3749 FN_ADICS_B_SAMP_B, 0, 0, 0, 3881 FN_ADICS_B_SAMP_B, 0, 0, 0,
3750 /* IP11_2_0 [3] */ 3882 /* IP11_2_0 [3] */
3751 FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK, 3883 FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
3752 FN_ADICLK_B, 0, 0, 0 } 3884 FN_ADICLK_B, 0, 0, 0 ))
3753 }, 3885 },
3754 { PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32, 3886 { PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32,
3755 4, 4, 4, 2, 3, 3, 3, 3, 3, 3) { 3887 GROUP(4, 4, 4, 2, 3, 3, 3, 3, 3, 3),
3888 GROUP(
3756 /* IP12_31_28 [4] */ 3889 /* IP12_31_28 [4] */
3757 0, 0, 0, 0, 0, 0, 0, 0, 3890 0, 0, 0, 0, 0, 0, 0, 0,
3758 0, 0, 0, 0, 0, 0, 0, 0, 3891 0, 0, 0, 0, 0, 0, 0, 0,
@@ -3781,11 +3914,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3781 FN_SCL1_C, FN_HTX0_B, 0, 0, 3914 FN_SCL1_C, FN_HTX0_B, 0, 0,
3782 /* IP12_2_0 [3] */ 3915 /* IP12_2_0 [3] */
3783 FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1, 3916 FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
3784 FN_SCK2, FN_HSCK0_B, 0, 0 } 3917 FN_SCK2, FN_HSCK0_B, 0, 0 ))
3785 }, 3918 },
3786 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xfffc0090, 32, 3919 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xfffc0090, 32,
3787 2, 2, 3, 3, 2, 2, 2, 2, 2, 3920 GROUP(2, 2, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1,
3788 1, 1, 1, 1, 1, 1, 1, 2, 1, 2) { 3921 1, 1, 1, 1, 2, 1, 2),
3922 GROUP(
3789 /* SEL_SCIF5 [2] */ 3923 /* SEL_SCIF5 [2] */
3790 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, 3924 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
3791 /* SEL_SCIF4 [2] */ 3925 /* SEL_SCIF4 [2] */
@@ -3825,11 +3959,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3825 /* SEL_EXBUS1 [1] */ 3959 /* SEL_EXBUS1 [1] */
3826 FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1, 3960 FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
3827 /* SEL_EXBUS0 [2] */ 3961 /* SEL_EXBUS0 [2] */
3828 FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 } 3962 FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 ))
3829 }, 3963 },
3830 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32, 3964 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32,
3831 2, 2, 2, 2, 1, 1, 1, 3, 1, 3965 GROUP(2, 2, 2, 2, 1, 1, 1, 3, 1, 2, 2, 2,
3832 2, 2, 2, 2, 1, 1, 2, 1, 2, 2) { 3966 2, 1, 1, 2, 1, 2, 2),
3967 GROUP(
3833 /* SEL_TMU1 [2] */ 3968 /* SEL_TMU1 [2] */
3834 FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 0, 3969 FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 0,
3835 /* SEL_TMU0 [2] */ 3970 /* SEL_TMU0 [2] */
@@ -3868,7 +4003,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3868 /* SEL_I2C2 [2] */ 4003 /* SEL_I2C2 [2] */
3869 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 4004 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
3870 /* SEL_I2C1 [2] */ 4005 /* SEL_I2C1 [2] */
3871 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 } 4006 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 ))
3872 }, 4007 },
3873 { }, 4008 { },
3874}; 4009};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index a84229cb8cd4..c41a6761cf9d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -8,6 +8,7 @@
8 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 8 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
9 */ 9 */
10 10
11#include <linux/errno.h>
11#include <linux/io.h> 12#include <linux/io.h>
12#include <linux/kernel.h> 13#include <linux/kernel.h>
13#include <linux/sys_soc.h> 14#include <linux/sys_soc.h>
@@ -4744,7 +4745,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
4744}; 4745};
4745 4746
4746static const struct pinmux_cfg_reg pinmux_config_regs[] = { 4747static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4747 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { 4748 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
4748 GP_0_31_FN, FN_IP3_17_15, 4749 GP_0_31_FN, FN_IP3_17_15,
4749 GP_0_30_FN, FN_IP3_14_12, 4750 GP_0_30_FN, FN_IP3_14_12,
4750 GP_0_29_FN, FN_IP3_11_8, 4751 GP_0_29_FN, FN_IP3_11_8,
@@ -4776,9 +4777,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4776 GP_0_3_FN, FN_IP0_11_9, 4777 GP_0_3_FN, FN_IP0_11_9,
4777 GP_0_2_FN, FN_IP0_8_6, 4778 GP_0_2_FN, FN_IP0_8_6,
4778 GP_0_1_FN, FN_IP0_5_3, 4779 GP_0_1_FN, FN_IP0_5_3,
4779 GP_0_0_FN, FN_IP0_2_0 } 4780 GP_0_0_FN, FN_IP0_2_0 ))
4780 }, 4781 },
4781 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { 4782 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
4782 0, 0, 4783 0, 0,
4783 0, 0, 4784 0, 0,
4784 GP_1_29_FN, FN_IP6_13_11, 4785 GP_1_29_FN, FN_IP6_13_11,
@@ -4810,9 +4811,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4810 GP_1_3_FN, FN_IP3_28_26, 4811 GP_1_3_FN, FN_IP3_28_26,
4811 GP_1_2_FN, FN_IP3_25_23, 4812 GP_1_2_FN, FN_IP3_25_23,
4812 GP_1_1_FN, FN_IP3_22_20, 4813 GP_1_1_FN, FN_IP3_22_20,
4813 GP_1_0_FN, FN_IP3_19_18, } 4814 GP_1_0_FN, FN_IP3_19_18, ))
4814 }, 4815 },
4815 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { 4816 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
4816 0, 0, 4817 0, 0,
4817 0, 0, 4818 0, 0,
4818 GP_2_29_FN, FN_IP7_15_13, 4819 GP_2_29_FN, FN_IP7_15_13,
@@ -4844,9 +4845,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4844 GP_2_3_FN, FN_IP8_3_2, 4845 GP_2_3_FN, FN_IP8_3_2,
4845 GP_2_2_FN, FN_IP8_1_0, 4846 GP_2_2_FN, FN_IP8_1_0,
4846 GP_2_1_FN, FN_IP7_30_29, 4847 GP_2_1_FN, FN_IP7_30_29,
4847 GP_2_0_FN, FN_IP7_28_27 } 4848 GP_2_0_FN, FN_IP7_28_27 ))
4848 }, 4849 },
4849 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { 4850 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
4850 GP_3_31_FN, FN_IP11_21_18, 4851 GP_3_31_FN, FN_IP11_21_18,
4851 GP_3_30_FN, FN_IP11_17_15, 4852 GP_3_30_FN, FN_IP11_17_15,
4852 GP_3_29_FN, FN_IP11_14_13, 4853 GP_3_29_FN, FN_IP11_14_13,
@@ -4878,9 +4879,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4878 GP_3_3_FN, FN_IP9_3_2, 4879 GP_3_3_FN, FN_IP9_3_2,
4879 GP_3_2_FN, FN_IP9_1_0, 4880 GP_3_2_FN, FN_IP9_1_0,
4880 GP_3_1_FN, FN_IP8_30_29, 4881 GP_3_1_FN, FN_IP8_30_29,
4881 GP_3_0_FN, FN_IP8_28 } 4882 GP_3_0_FN, FN_IP8_28 ))
4882 }, 4883 },
4883 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { 4884 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
4884 GP_4_31_FN, FN_IP14_18_16, 4885 GP_4_31_FN, FN_IP14_18_16,
4885 GP_4_30_FN, FN_IP14_15_12, 4886 GP_4_30_FN, FN_IP14_15_12,
4886 GP_4_29_FN, FN_IP14_11_9, 4887 GP_4_29_FN, FN_IP14_11_9,
@@ -4912,9 +4913,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4912 GP_4_3_FN, FN_IP11_31_30, 4913 GP_4_3_FN, FN_IP11_31_30,
4913 GP_4_2_FN, FN_IP11_29_27, 4914 GP_4_2_FN, FN_IP11_29_27,
4914 GP_4_1_FN, FN_IP11_26_24, 4915 GP_4_1_FN, FN_IP11_26_24,
4915 GP_4_0_FN, FN_IP11_23_22 } 4916 GP_4_0_FN, FN_IP11_23_22 ))
4916 }, 4917 },
4917 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { 4918 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
4918 GP_5_31_FN, FN_IP7_24_22, 4919 GP_5_31_FN, FN_IP7_24_22,
4919 GP_5_30_FN, FN_IP7_21_19, 4920 GP_5_30_FN, FN_IP7_21_19,
4920 GP_5_29_FN, FN_IP7_18_16, 4921 GP_5_29_FN, FN_IP7_18_16,
@@ -4946,10 +4947,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4946 GP_5_3_FN, FN_IP14_30_28, 4947 GP_5_3_FN, FN_IP14_30_28,
4947 GP_5_2_FN, FN_IP14_27_25, 4948 GP_5_2_FN, FN_IP14_27_25,
4948 GP_5_1_FN, FN_IP14_24_22, 4949 GP_5_1_FN, FN_IP14_24_22,
4949 GP_5_0_FN, FN_IP14_21_19 } 4950 GP_5_0_FN, FN_IP14_21_19 ))
4950 }, 4951 },
4951 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, 4952 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4952 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) { 4953 GROUP(1, 4, 4, 3, 4, 4, 3, 3, 3, 3),
4954 GROUP(
4953 /* IP0_31 [1] */ 4955 /* IP0_31 [1] */
4954 0, 0, 4956 0, 0,
4955 /* IP0_30_27 [4] */ 4957 /* IP0_30_27 [4] */
@@ -4982,10 +4984,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4982 0, 0, 0, 4984 0, 0, 0,
4983 /* IP0_2_0 [3] */ 4985 /* IP0_2_0 [3] */
4984 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, 4986 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
4985 0, 0, 0, } 4987 0, 0, 0, ))
4986 }, 4988 },
4987 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, 4989 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4988 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) { 4990 GROUP(2, 2, 2, 4, 4, 3, 3, 4, 4, 4),
4991 GROUP(
4989 /* IP1_31_30 [2] */ 4992 /* IP1_31_30 [2] */
4990 0, 0, 0, 0, 4993 0, 0, 0, 0,
4991 /* IP1_29_28 [2] */ 4994 /* IP1_29_28 [2] */
@@ -5019,10 +5022,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5019 /* IP1_3_0 [4] */ 5022 /* IP1_3_0 [4] */
5020 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0, 5023 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
5021 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, 5024 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
5022 0, 0, 0, 0, 0, 0, 0, 0, 0, } 5025 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
5023 }, 5026 },
5024 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, 5027 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5025 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) { 5028 GROUP(3, 3, 4, 4, 3, 3, 3, 3, 3, 3),
5029 GROUP(
5026 /* IP2_31_29 [3] */ 5030 /* IP2_31_29 [3] */
5027 0, 0, 0, 0, 0, 0, 0, 0, 5031 0, 0, 0, 0, 0, 0, 0, 0,
5028 /* IP2_28_26 [3] */ 5032 /* IP2_28_26 [3] */
@@ -5048,10 +5052,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5048 /* IP2_5_3 [3] */ 5052 /* IP2_5_3 [3] */
5049 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0, 5053 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
5050 /* IP2_2_0 [3] */ 5054 /* IP2_2_0 [3] */
5051 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, } 5055 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, ))
5052 }, 5056 },
5053 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, 5057 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5054 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) { 5058 GROUP(3, 3, 3, 3, 2, 3, 3, 4, 4, 4),
5059 GROUP(
5055 /* IP3_31_29 [3] */ 5060 /* IP3_31_29 [3] */
5056 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, 5061 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
5057 0, 0, 0, 5062 0, 0, 0,
@@ -5081,10 +5086,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5081 /* IP3_3_0 [4] */ 5086 /* IP3_3_0 [4] */
5082 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, 5087 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
5083 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0, 5088 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
5084 0, 0, 0, 0, 0, 0, 0, 0, } 5089 0, 0, 0, 0, 0, 0, 0, 0, ))
5085 }, 5090 },
5086 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, 5091 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5087 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { 5092 GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
5093 GROUP(
5088 /* IP4_31_30 [2] */ 5094 /* IP4_31_30 [2] */
5089 0, 0, 0, 0, 5095 0, 0, 0, 0,
5090 /* IP4_29_27 [3] */ 5096 /* IP4_29_27 [3] */
@@ -5114,10 +5120,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5114 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0, 5120 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
5115 /* IP4_2_0 [3] */ 5121 /* IP4_2_0 [3] */
5116 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0, 5122 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
5117 } 5123 ))
5118 }, 5124 },
5119 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, 5125 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5120 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) { 5126 GROUP(2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3),
5127 GROUP(
5121 /* IP5_31_30 [2] */ 5128 /* IP5_31_30 [2] */
5122 0, 0, 0, 0, 5129 0, 0, 0, 0,
5123 /* IP5_29_27 [3] */ 5130 /* IP5_29_27 [3] */
@@ -5151,10 +5158,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5151 FN_INTC_EN0_N, FN_I2C1_SCL, 5158 FN_INTC_EN0_N, FN_I2C1_SCL,
5152 /* IP5_2_0 [3] */ 5159 /* IP5_2_0 [3] */
5153 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, 5160 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
5154 FN_VI2_R3, 0, 0, } 5161 FN_VI2_R3, 0, 0, ))
5155 }, 5162 },
5156 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, 5163 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5157 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { 5164 GROUP(3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3),
5165 GROUP(
5158 /* IP6_31_29 [3] */ 5166 /* IP6_31_29 [3] */
5159 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E, 5167 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
5160 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, 5168 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
@@ -5187,10 +5195,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5187 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, 5195 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
5188 /* IP6_2_0 [3] */ 5196 /* IP6_2_0 [3] */
5189 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, 5197 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
5190 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, } 5198 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
5191 }, 5199 },
5192 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, 5200 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5193 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) { 5201 GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
5202 GROUP(
5194 /* IP7_31 [1] */ 5203 /* IP7_31 [1] */
5195 0, 0, 5204 0, 0,
5196 /* IP7_30_29 [2] */ 5205 /* IP7_30_29 [2] */
@@ -5222,11 +5231,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5222 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0, 5231 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
5223 /* IP7_2_0 [3] */ 5232 /* IP7_2_0 [3] */
5224 FN_ETH_MDIO, 0, FN_HRTS0_N_E, 5233 FN_ETH_MDIO, 0, FN_HRTS0_N_E,
5225 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } 5234 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, ))
5226 }, 5235 },
5227 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, 5236 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5228 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 5237 GROUP(1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
5229 2, 2, 2, 2, 2, 2, 2) { 5238 2, 2, 2, 2, 2, 2),
5239 GROUP(
5230 /* IP8_31 [1] */ 5240 /* IP8_31 [1] */
5231 0, 0, 5241 0, 0,
5232 /* IP8_30_29 [2] */ 5242 /* IP8_30_29 [2] */
@@ -5263,10 +5273,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5263 /* IP8_3_2 [2] */ 5273 /* IP8_3_2 [2] */
5264 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, 5274 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
5265 /* IP8_1_0 [2] */ 5275 /* IP8_1_0 [2] */
5266 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, } 5276 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, ))
5267 }, 5277 },
5268 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, 5278 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5269 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { 5279 GROUP(4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2),
5280 GROUP(
5270 /* IP9_31_28 [4] */ 5281 /* IP9_31_28 [4] */
5271 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP, 5282 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
5272 FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D, 5283 FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
@@ -5298,10 +5309,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5298 /* IP9_3_2 [2] */ 5309 /* IP9_3_2 [2] */
5299 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0, 5310 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
5300 /* IP9_1_0 [2] */ 5311 /* IP9_1_0 [2] */
5301 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, } 5312 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, ))
5302 }, 5313 },
5303 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, 5314 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5304 2, 4, 3, 4, 4, 4, 4, 3, 4) { 5315 GROUP(2, 4, 3, 4, 4, 4, 4, 3, 4),
5316 GROUP(
5305 /* IP10_31_30 [2] */ 5317 /* IP10_31_30 [2] */
5306 0, 0, 0, 0, 5318 0, 0, 0, 0,
5307 /* IP10_29_26 [4] */ 5319 /* IP10_29_26 [4] */
@@ -5337,10 +5349,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5337 /* IP10_3_0 [4] */ 5349 /* IP10_3_0 [4] */
5338 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, 5350 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
5339 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, 5351 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
5340 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, } 5352 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, ))
5341 }, 5353 },
5342 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, 5354 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5343 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) { 5355 GROUP(2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4),
5356 GROUP(
5344 /* IP11_31_30 [2] */ 5357 /* IP11_31_30 [2] */
5345 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, 5358 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
5346 /* IP11_29_27 [3] */ 5359 /* IP11_29_27 [3] */
@@ -5372,10 +5385,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5372 /* IP11_3_0 [4] */ 5385 /* IP11_3_0 [4] */
5373 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, 5386 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
5374 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, 5387 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
5375 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, } 5388 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, ))
5376 }, 5389 },
5377 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, 5390 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5378 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) { 5391 GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2),
5392 GROUP(
5379 /* IP12_31 [1] */ 5393 /* IP12_31 [1] */
5380 0, 0, 5394 0, 0,
5381 /* IP12_30_28 [3] */ 5395 /* IP12_30_28 [3] */
@@ -5411,10 +5425,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5411 /* IP12_3_2 [2] */ 5425 /* IP12_3_2 [2] */
5412 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0, 5426 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
5413 /* IP12_1_0 [2] */ 5427 /* IP12_1_0 [2] */
5414 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, } 5428 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, ))
5415 }, 5429 },
5416 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, 5430 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5417 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) { 5431 GROUP(1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3),
5432 GROUP(
5418 /* IP13_31 [1] */ 5433 /* IP13_31 [1] */
5419 0, 0, 5434 0, 0,
5420 /* IP13_30_29 [2] */ 5435 /* IP13_30_29 [2] */
@@ -5447,10 +5462,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5447 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0, 5462 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
5448 /* IP13_2_0 [3] */ 5463 /* IP13_2_0 [3] */
5449 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, 5464 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
5450 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, } 5465 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, ))
5451 }, 5466 },
5452 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, 5467 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
5453 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) { 5468 GROUP(1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3),
5469 GROUP(
5454 /* IP14_30 [1] */ 5470 /* IP14_30 [1] */
5455 0, 0, 5471 0, 0,
5456 /* IP14_30_28 [3] */ 5472 /* IP14_30_28 [3] */
@@ -5485,10 +5501,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5485 /* IP14_2_0 [3] */ 5501 /* IP14_2_0 [3] */
5486 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, 5502 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
5487 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, 5503 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
5488 FN_REMOCON, 0, } 5504 FN_REMOCON, 0, ))
5489 }, 5505 },
5490 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, 5506 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
5491 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) { 5507 GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3),
5508 GROUP(
5492 /* IP15_31_30 [2] */ 5509 /* IP15_31_30 [2] */
5493 0, 0, 0, 0, 5510 0, 0, 0, 0,
5494 /* IP15_29_28 [2] */ 5511 /* IP15_29_28 [2] */
@@ -5520,10 +5537,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5520 FN_IIC2_SCL, FN_I2C2_SCL, 0, 5537 FN_IIC2_SCL, FN_I2C2_SCL, 0,
5521 /* IP15_2_0 [3] */ 5538 /* IP15_2_0 [3] */
5522 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, 5539 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
5523 FN_LCDOUT15, FN_SCIF_CLK_B, 0, } 5540 FN_LCDOUT15, FN_SCIF_CLK_B, 0, ))
5524 }, 5541 },
5525 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, 5542 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5526 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) { 5543 GROUP(4, 4, 4, 4, 4, 4, 1, 1, 3, 3),
5544 GROUP(
5527 /* IP16_31_28 [4] */ 5545 /* IP16_31_28 [4] */
5528 0, 0, 0, 0, 0, 0, 0, 0, 5546 0, 0, 0, 0, 0, 0, 0, 0,
5529 0, 0, 0, 0, 0, 0, 0, 0, 5547 0, 0, 0, 0, 0, 0, 0, 0,
@@ -5551,11 +5569,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5551 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0, 5569 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
5552 /* IP16_2_0 [3] */ 5570 /* IP16_2_0 [3] */
5553 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, 5571 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
5554 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, } 5572 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, ))
5555 }, 5573 },
5556 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, 5574 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5557 3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 5575 GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1,
5558 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) { 5576 1, 1, 1, 2, 1, 1, 2, 1, 1),
5577 GROUP(
5559 /* SEL_SCIF1 [3] */ 5578 /* SEL_SCIF1 [3] */
5560 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 5579 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
5561 FN_SEL_SCIF1_4, 0, 0, 0, 5580 FN_SEL_SCIF1_4, 0, 0, 0,
@@ -5601,11 +5620,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5601 /* SEL_SOF3 [1] */ 5620 /* SEL_SOF3 [1] */
5602 FN_SEL_SOF3_0, FN_SEL_SOF3_1, 5621 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
5603 /* SEL_SOF0 [1] */ 5622 /* SEL_SOF0 [1] */
5604 FN_SEL_SOF0_0, FN_SEL_SOF0_1, } 5623 FN_SEL_SOF0_0, FN_SEL_SOF0_1, ))
5605 }, 5624 },
5606 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, 5625 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5607 3, 1, 1, 1, 2, 1, 2, 1, 2, 5626 GROUP(3, 1, 1, 1, 2, 1, 2, 1, 2, 1, 1, 1,
5608 1, 1, 1, 3, 3, 2, 3, 2, 2) { 5627 3, 3, 2, 3, 2, 2),
5628 GROUP(
5609 /* RESERVED [3] */ 5629 /* RESERVED [3] */
5610 0, 0, 0, 0, 0, 0, 0, 0, 5630 0, 0, 0, 0, 0, 0, 0, 0,
5611 /* SEL_TMU1 [1] */ 5631 /* SEL_TMU1 [1] */
@@ -5643,11 +5663,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5643 /* SEL_SIM [2] */ 5663 /* SEL_SIM [2] */
5644 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0, 5664 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
5645 /* SEL_SSI8 [2] */ 5665 /* SEL_SSI8 [2] */
5646 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, } 5666 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, ))
5647 }, 5667 },
5648 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, 5668 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5649 1, 1, 2, 4, 4, 2, 2, 5669 GROUP(1, 1, 2, 4, 4, 2, 2, 4, 2, 3, 2, 3, 2),
5650 4, 2, 3, 2, 3, 2) { 5670 GROUP(
5651 /* SEL_IICDVFS [1] */ 5671 /* SEL_IICDVFS [1] */
5652 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, 5672 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
5653 /* SEL_IIC0 [1] */ 5673 /* SEL_IIC0 [1] */
@@ -5678,7 +5698,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5678 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, 5698 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
5679 FN_SEL_I2C2_4, 0, 0, 0, 5699 FN_SEL_I2C2_4, 0, 0, 0,
5680 /* SEL_I2C1 [2] */ 5700 /* SEL_I2C1 [2] */
5681 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, } 5701 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, ))
5682 }, 5702 },
5683 { }, 5703 { },
5684}; 5704};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index d8b13d4e9bbf..1292ec8d268f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -6,6 +6,7 @@
6 * Copyright (C) 2014-2017 Cogent Embedded, Inc. 6 * Copyright (C) 2014-2017 Cogent Embedded, Inc.
7 */ 7 */
8 8
9#include <linux/errno.h>
9#include <linux/kernel.h> 10#include <linux/kernel.h>
10 11
11#include "sh_pfc.h" 12#include "sh_pfc.h"
@@ -5427,7 +5428,7 @@ static const struct {
5427}; 5428};
5428 5429
5429static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5430static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5430 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { 5431 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
5431 GP_0_31_FN, FN_IP1_22_20, 5432 GP_0_31_FN, FN_IP1_22_20,
5432 GP_0_30_FN, FN_IP1_19_17, 5433 GP_0_30_FN, FN_IP1_19_17,
5433 GP_0_29_FN, FN_IP1_16_14, 5434 GP_0_29_FN, FN_IP1_16_14,
@@ -5459,9 +5460,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5459 GP_0_3_FN, FN_IP0_3, 5460 GP_0_3_FN, FN_IP0_3,
5460 GP_0_2_FN, FN_IP0_2, 5461 GP_0_2_FN, FN_IP0_2,
5461 GP_0_1_FN, FN_IP0_1, 5462 GP_0_1_FN, FN_IP0_1,
5462 GP_0_0_FN, FN_IP0_0, } 5463 GP_0_0_FN, FN_IP0_0, ))
5463 }, 5464 },
5464 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { 5465 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
5465 0, 0, 5466 0, 0,
5466 0, 0, 5467 0, 0,
5467 0, 0, 5468 0, 0,
@@ -5493,9 +5494,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5493 GP_1_3_FN, FN_IP2_2_0, 5494 GP_1_3_FN, FN_IP2_2_0,
5494 GP_1_2_FN, FN_IP1_31_29, 5495 GP_1_2_FN, FN_IP1_31_29,
5495 GP_1_1_FN, FN_IP1_28_26, 5496 GP_1_1_FN, FN_IP1_28_26,
5496 GP_1_0_FN, FN_IP1_25_23, } 5497 GP_1_0_FN, FN_IP1_25_23, ))
5497 }, 5498 },
5498 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { 5499 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
5499 GP_2_31_FN, FN_IP6_7_6, 5500 GP_2_31_FN, FN_IP6_7_6,
5500 GP_2_30_FN, FN_IP6_5_3, 5501 GP_2_30_FN, FN_IP6_5_3,
5501 GP_2_29_FN, FN_IP6_2_0, 5502 GP_2_29_FN, FN_IP6_2_0,
@@ -5527,9 +5528,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5527 GP_2_3_FN, FN_IP4_4_2, 5528 GP_2_3_FN, FN_IP4_4_2,
5528 GP_2_2_FN, FN_IP4_1_0, 5529 GP_2_2_FN, FN_IP4_1_0,
5529 GP_2_1_FN, FN_IP3_30_28, 5530 GP_2_1_FN, FN_IP3_30_28,
5530 GP_2_0_FN, FN_IP3_27_25 } 5531 GP_2_0_FN, FN_IP3_27_25 ))
5531 }, 5532 },
5532 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { 5533 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
5533 GP_3_31_FN, FN_IP9_18_17, 5534 GP_3_31_FN, FN_IP9_18_17,
5534 GP_3_30_FN, FN_IP9_16, 5535 GP_3_30_FN, FN_IP9_16,
5535 GP_3_29_FN, FN_IP9_15_13, 5536 GP_3_29_FN, FN_IP9_15_13,
@@ -5561,9 +5562,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5561 GP_3_3_FN, FN_IP7_12_11, 5562 GP_3_3_FN, FN_IP7_12_11,
5562 GP_3_2_FN, FN_IP7_10_9, 5563 GP_3_2_FN, FN_IP7_10_9,
5563 GP_3_1_FN, FN_IP7_8_6, 5564 GP_3_1_FN, FN_IP7_8_6,
5564 GP_3_0_FN, FN_IP7_5_3 } 5565 GP_3_0_FN, FN_IP7_5_3 ))
5565 }, 5566 },
5566 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { 5567 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
5567 GP_4_31_FN, FN_IP15_5_4, 5568 GP_4_31_FN, FN_IP15_5_4,
5568 GP_4_30_FN, FN_IP15_3_2, 5569 GP_4_30_FN, FN_IP15_3_2,
5569 GP_4_29_FN, FN_IP15_1_0, 5570 GP_4_29_FN, FN_IP15_1_0,
@@ -5595,9 +5596,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5595 GP_4_3_FN, FN_IP9_24_23, 5596 GP_4_3_FN, FN_IP9_24_23,
5596 GP_4_2_FN, FN_IP9_22_21, 5597 GP_4_2_FN, FN_IP9_22_21,
5597 GP_4_1_FN, FN_IP9_20_19, 5598 GP_4_1_FN, FN_IP9_20_19,
5598 GP_4_0_FN, FN_VI0_CLK } 5599 GP_4_0_FN, FN_VI0_CLK ))
5599 }, 5600 },
5600 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { 5601 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
5601 GP_5_31_FN, FN_IP3_24_22, 5602 GP_5_31_FN, FN_IP3_24_22,
5602 GP_5_30_FN, FN_IP13_9_7, 5603 GP_5_30_FN, FN_IP13_9_7,
5603 GP_5_29_FN, FN_IP13_6_5, 5604 GP_5_29_FN, FN_IP13_6_5,
@@ -5629,9 +5630,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5629 GP_5_3_FN, FN_IP11_18_17, 5630 GP_5_3_FN, FN_IP11_18_17,
5630 GP_5_2_FN, FN_IP11_16_15, 5631 GP_5_2_FN, FN_IP11_16_15,
5631 GP_5_1_FN, FN_IP11_14_12, 5632 GP_5_1_FN, FN_IP11_14_12,
5632 GP_5_0_FN, FN_IP11_11_9 } 5633 GP_5_0_FN, FN_IP11_11_9 ))
5633 }, 5634 },
5634 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { 5635 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
5635 GP_6_31_FN, FN_DU0_DOTCLKIN, 5636 GP_6_31_FN, FN_DU0_DOTCLKIN,
5636 GP_6_30_FN, FN_USB1_OVC, 5637 GP_6_30_FN, FN_USB1_OVC,
5637 GP_6_29_FN, FN_IP14_31_29, 5638 GP_6_29_FN, FN_IP14_31_29,
@@ -5663,9 +5664,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5663 GP_6_3_FN, FN_IP13_13, 5664 GP_6_3_FN, FN_IP13_13,
5664 GP_6_2_FN, FN_IP13_12, 5665 GP_6_2_FN, FN_IP13_12,
5665 GP_6_1_FN, FN_IP13_11, 5666 GP_6_1_FN, FN_IP13_11,
5666 GP_6_0_FN, FN_IP13_10 } 5667 GP_6_0_FN, FN_IP13_10 ))
5667 }, 5668 },
5668 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) { 5669 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP(
5669 0, 0, 5670 0, 0,
5670 0, 0, 5671 0, 0,
5671 0, 0, 5672 0, 0,
@@ -5697,11 +5698,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5697 GP_7_3_FN, FN_IP15_26_24, 5698 GP_7_3_FN, FN_IP15_26_24,
5698 GP_7_2_FN, FN_IP15_23_21, 5699 GP_7_2_FN, FN_IP15_23_21,
5699 GP_7_1_FN, FN_IP15_20_18, 5700 GP_7_1_FN, FN_IP15_20_18,
5700 GP_7_0_FN, FN_IP15_17_15 } 5701 GP_7_0_FN, FN_IP15_17_15 ))
5701 }, 5702 },
5702 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, 5703 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5703 1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1, 5704 GROUP(1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1,
5704 1, 1, 1, 1, 1, 1, 1, 1) { 5705 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
5706 GROUP(
5705 /* IP0_31 [1] */ 5707 /* IP0_31 [1] */
5706 0, 0, 5708 0, 0,
5707 /* IP0_30_29 [2] */ 5709 /* IP0_30_29 [2] */
@@ -5756,10 +5758,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5756 /* IP0_1 [1] */ 5758 /* IP0_1 [1] */
5757 FN_D1, 0, 5759 FN_D1, 0,
5758 /* IP0_0 [1] */ 5760 /* IP0_0 [1] */
5759 FN_D0, 0, } 5761 FN_D0, 0, ))
5760 }, 5762 },
5761 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, 5763 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5762 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) { 5764 GROUP(3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2),
5765 GROUP(
5763 /* IP1_31_29 [3] */ 5766 /* IP1_31_29 [3] */
5764 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C, 5767 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
5765 0, 0, 0, 5768 0, 0, 0,
@@ -5792,10 +5795,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5792 FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0, 5795 FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0,
5793 /* IP1_1_0 [2] */ 5796 /* IP1_1_0 [2] */
5794 FN_A7, FN_MSIOF1_SYNC, 5797 FN_A7, FN_MSIOF1_SYNC,
5795 0, 0, } 5798 0, 0, ))
5796 }, 5799 },
5797 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, 5800 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5798 2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) { 5801 GROUP(2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3),
5802 GROUP(
5799 /* IP2_31_30 [2] */ 5803 /* IP2_31_30 [2] */
5800 0, 0, 0, 0, 5804 0, 0, 0, 0,
5801 /* IP2_29_27 [3] */ 5805 /* IP2_29_27 [3] */
@@ -5828,10 +5832,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5828 FN_A20, FN_SPCLK, 0, 0, 5832 FN_A20, FN_SPCLK, 0, 0,
5829 /* IP2_2_0 [3] */ 5833 /* IP2_2_0 [3] */
5830 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0, 5834 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
5831 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, } 5835 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, ))
5832 }, 5836 },
5833 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, 5837 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5834 1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) { 5838 GROUP(1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3),
5839 GROUP(
5835 /* IP3_31 [1] */ 5840 /* IP3_31 [1] */
5836 0, 0, 5841 0, 0,
5837 /* IP3_30_28 [3] */ 5842 /* IP3_30_28 [3] */
@@ -5866,10 +5871,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5866 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0, 5871 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
5867 /* IP3_2_0 [3] */ 5872 /* IP3_2_0 [3] */
5868 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2, 5873 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
5869 0, 0, 0, } 5874 0, 0, 0, ))
5870 }, 5875 },
5871 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, 5876 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5872 1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) { 5877 GROUP(1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2,
5878 3, 3, 2),
5879 GROUP(
5873 /* IP4_31 [1] */ 5880 /* IP4_31 [1] */
5874 0, 0, 5881 0, 0,
5875 /* IP4_30_28 [3] */ 5882 /* IP4_30_28 [3] */
@@ -5908,10 +5915,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5908 FN_MSIOF2_SYNC_C, FN_GLO_I0_D, 5915 FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
5909 0, 0, 0, 5916 0, 0, 0,
5910 /* IP4_1_0 [2] */ 5917 /* IP4_1_0 [2] */
5911 FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, } 5918 FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
5919 ))
5912 }, 5920 },
5913 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, 5921 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5914 3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) { 5922 GROUP(3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3),
5923 GROUP(
5915 /* IP5_31_29 [3] */ 5924 /* IP5_31_29 [3] */
5916 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D, 5925 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
5917 0, 0, 0, 0, 0, 5926 0, 0, 0, 0, 0,
@@ -5946,10 +5955,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5946 /* IP5_2_0 [3] */ 5955 /* IP5_2_0 [3] */
5947 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1, 5956 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
5948 FN_MSIOF2_TXD_D, FN_VI1_R3_B, 5957 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
5949 0, 0, } 5958 0, 0, ))
5950 }, 5959 },
5951 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, 5960 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5952 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) { 5961 GROUP(2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3),
5962 GROUP(
5953 /* IP6_31_30 [2] */ 5963 /* IP6_31_30 [2] */
5954 0, 0, 0, 0, 5964 0, 0, 0, 0,
5955 /* IP6_29_27 [3] */ 5965 /* IP6_29_27 [3] */
@@ -5986,10 +5996,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5986 /* IP6_2_0 [3] */ 5996 /* IP6_2_0 [3] */
5987 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, 5997 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
5988 FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E, 5998 FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
5989 0, 0, } 5999 0, 0, ))
5990 }, 6000 },
5991 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, 6001 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5992 2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) { 6002 GROUP(2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3),
6003 GROUP(
5993 /* IP7_31_30 [2] */ 6004 /* IP7_31_30 [2] */
5994 0, 0, 0, 0, 6005 0, 0, 0, 0,
5995 /* IP7_29_27 [3] */ 6006 /* IP7_29_27 [3] */
@@ -6027,10 +6038,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
6027 /* IP7_2_0 [3] */ 6038 /* IP7_2_0 [3] */
6028 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C, 6039 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
6029 FN_SCIF_CLK_B, FN_GPS_MAG_D, 6040 FN_SCIF_CLK_B, FN_GPS_MAG_D,
6030 0, 0, } 6041 0, 0, ))
6031 }, 6042 },
6032 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, 6043 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
6033 1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) { 6044 GROUP(1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3),
6045 GROUP(
6034 /* IP8_31 [1] */ 6046 /* IP8_31 [1] */
6035 0, 0, 6047 0, 0,
6036 /* IP8_30_28 [3] */ 6048 /* IP8_30_28 [3] */
@@ -6070,10 +6082,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
6070 0, 0, 6082 0, 0,
6071 /* IP8_2_0 [3] */ 6083 /* IP8_2_0 [3] */
6072 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B, 6084 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
6073 0, 0, 0, } 6085 0, 0, 0, ))
6074 }, 6086 },
6075 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, 6087 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
6076 3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) { 6088 GROUP(3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3,
6089 1, 1, 3, 3),
6090 GROUP(
6077 /* IP9_31_29 [3] */ 6091 /* IP9_31_29 [3] */
6078 FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL, 6092 FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
6079 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0, 6093 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
@@ -6113,10 +6127,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
6113 0, 0, 0, 6127 0, 0, 0,
6114 /* IP9_2_0 [3] */ 6128 /* IP9_2_0 [3] */
6115 FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD, 6129 FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
6116 0, 0, 0, } 6130 0, 0, 0, ))
6117 }, 6131 },
6118 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, 6132 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
6119 3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) { 6133 GROUP(3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3),
6134 GROUP(
6120 /* IP10_31_29 [3] */ 6135 /* IP10_31_29 [3] */
6121 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D, 6136 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
6122 0, 0, 0, 6137 0, 0, 0,
@@ -6150,11 +6165,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
6150 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0, 6165 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
6151 /* IP10_2_0 [3] */ 6166 /* IP10_2_0 [3] */
6152 FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA, 6167 FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
6153 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, } 6168 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, ))
6154 }, 6169 },
6155 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, 6170 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
6156 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 6171 GROUP(2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
6157 3, 3, 3, 3, 3) { 6172 2, 3, 3, 3, 3, 3),
6173 GROUP(
6158 /* IP11_31_30 [2] */ 6174 /* IP11_31_30 [2] */
6159 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0, 6175 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0,
6160 /* IP11_29_28 [2] */ 6176 /* IP11_29_28 [2] */
@@ -6197,10 +6213,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
6197 0, 0, 0, 6213 0, 0, 0,
6198 /* IP11_2_0 [3] */ 6214 /* IP11_2_0 [3] */
6199 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, 6215 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C,
6200 FN_I2C1_SDA_D, 0, 0, 0, } 6216 FN_I2C1_SDA_D, 0, 0, 0, ))
6201 }, 6217 },
6202 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, 6218 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
6203 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) { 6219 GROUP(2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2),
6220 GROUP(
6204 /* IP12_31_30 [2] */ 6221 /* IP12_31_30 [2] */
6205 0, 0, 0, 0, 6222 0, 0, 0, 0,
6206 /* IP12_29_27 [3] */ 6223 /* IP12_29_27 [3] */
@@ -6238,11 +6255,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
6238 /* IP12_3_2 [2] */ 6255 /* IP12_3_2 [2] */
6239 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA, 6256 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
6240 /* IP12_1_0 [2] */ 6257 /* IP12_1_0 [2] */
6241 FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, } 6258 FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, ))
6242 }, 6259 },
6243 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, 6260 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
6244 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1, 6261 GROUP(1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1,
6245 3, 2, 2, 3) { 6262 1, 1, 1, 3, 2, 2, 3),
6263 GROUP(
6246 /* IP13_31 [1] */ 6264 /* IP13_31 [1] */
6247 0, 0, 6265 0, 0,
6248 /* IP13_30_28 [3] */ 6266 /* IP13_30_28 [3] */
@@ -6289,10 +6307,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
6289 /* IP13_2_0 [3] */ 6307 /* IP13_2_0 [3] */
6290 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C, 6308 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
6291 FN_ADICLK_B, FN_MSIOF0_SS1_C, 6309 FN_ADICLK_B, FN_MSIOF0_SS1_C,
6292 0, 0, 0, } 6310 0, 0, 0, ))
6293 }, 6311 },
6294 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, 6312 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
6295 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) { 6313 GROUP(3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1,
6314 1, 1, 2),
6315 GROUP(
6296 /* IP14_31_29 [3] */ 6316 /* IP14_31_29 [3] */
6297 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, 6317 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
6298 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0, 6318 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0,
@@ -6332,10 +6352,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
6332 /* IP14_2 [1] */ 6352 /* IP14_2 [1] */
6333 FN_SD2_CLK, FN_MMC_CLK, 6353 FN_SD2_CLK, FN_MMC_CLK,
6334 /* IP14_1_0 [2] */ 6354 /* IP14_1_0 [2] */
6335 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, } 6355 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, ))
6336 }, 6356 },
6337 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, 6357 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
6338 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) { 6358 GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2),
6359 GROUP(
6339 /* IP15_31_30 [2] */ 6360 /* IP15_31_30 [2] */
6340 0, 0, 0, 0, 6361 0, 0, 0, 0,
6341 /* IP15_29_27 [3] */ 6362 /* IP15_29_27 [3] */
@@ -6373,10 +6394,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
6373 /* IP15_3_2 [2] */ 6394 /* IP15_3_2 [2] */
6374 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0, 6395 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
6375 /* IP15_1_0 [2] */ 6396 /* IP15_1_0 [2] */
6376 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, } 6397 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, ))
6377 }, 6398 },
6378 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, 6399 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
6379 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) { 6400 GROUP(4, 4, 4, 4, 4, 2, 2, 2, 3, 3),
6401 GROUP(
6380 /* IP16_31_28 [4] */ 6402 /* IP16_31_28 [4] */
6381 0, 0, 0, 0, 0, 0, 0, 0, 6403 0, 0, 0, 0, 0, 0, 0, 0,
6382 0, 0, 0, 0, 0, 0, 0, 0, 6404 0, 0, 0, 0, 0, 0, 0, 0,
@@ -6405,11 +6427,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
6405 /* IP16_2_0 [3] */ 6427 /* IP16_2_0 [3] */
6406 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, 6428 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
6407 FN_GLO_SDATA_C, FN_VI1_DATA6_C, 6429 FN_GLO_SDATA_C, FN_VI1_DATA6_C,
6408 0, 0, 0, } 6430 0, 0, 0, ))
6409 }, 6431 },
6410 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, 6432 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
6411 1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 6433 GROUP(1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2,
6412 3, 2, 2, 2, 1, 2, 2, 2) { 6434 2, 2, 1, 2, 2, 2),
6435 GROUP(
6413 /* RESERVED [1] */ 6436 /* RESERVED [1] */
6414 0, 0, 6437 0, 0,
6415 /* SEL_SCIF1 [2] */ 6438 /* SEL_SCIF1 [2] */
@@ -6450,11 +6473,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
6450 /* SEL_TSIF0 [2] */ 6473 /* SEL_TSIF0 [2] */
6451 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, 6474 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
6452 /* SEL_SOF0 [2] */ 6475 /* SEL_SOF0 [2] */
6453 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, } 6476 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, ))
6454 }, 6477 },
6455 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, 6478 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
6456 3, 1, 1, 3, 2, 1, 1, 2, 2, 6479 GROUP(3, 1, 1, 3, 2, 1, 1, 2, 2, 1, 3, 2,
6457 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) { 6480 1, 2, 2, 2, 1, 1, 1),
6481 GROUP(
6458 /* SEL_SCIF0 [3] */ 6482 /* SEL_SCIF0 [3] */
6459 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 6483 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
6460 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4, 6484 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
@@ -6498,11 +6522,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
6498 /* RESERVED [1] */ 6522 /* RESERVED [1] */
6499 0, 0, 6523 0, 0,
6500 /* SEL_SSI8 [1] */ 6524 /* SEL_SSI8 [1] */
6501 FN_SEL_SSI8_0, FN_SEL_SSI8_1, } 6525 FN_SEL_SSI8_0, FN_SEL_SSI8_1, ))
6502 }, 6526 },
6503 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, 6527 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
6504 2, 2, 2, 2, 2, 2, 2, 2, 6528 GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 2, 2,
6505 1, 1, 2, 2, 3, 2, 2, 2, 1) { 6529 3, 2, 2, 2, 1),
6530 GROUP(
6506 /* SEL_HSCIF2 [2] */ 6531 /* SEL_HSCIF2 [2] */
6507 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, 6532 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
6508 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, 6533 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
@@ -6540,11 +6565,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
6540 /* RESERVED [2] */ 6565 /* RESERVED [2] */
6541 0, 0, 0, 0, 6566 0, 0, 0, 0,
6542 /* RESERVED [1] */ 6567 /* RESERVED [1] */
6543 0, 0, } 6568 0, 0, ))
6544 }, 6569 },
6545 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32, 6570 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
6546 3, 2, 2, 1, 1, 1, 1, 3, 2, 6571 GROUP(3, 2, 2, 1, 1, 1, 1, 3, 2, 2, 3, 1,
6547 2, 3, 1, 1, 1, 2, 2, 2, 2) { 6572 1, 1, 2, 2, 2, 2),
6573 GROUP(
6548 /* SEL_SOF1 [3] */ 6574 /* SEL_SOF1 [3] */
6549 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, 6575 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
6550 FN_SEL_SOF1_4, 6576 FN_SEL_SOF1_4,
@@ -6586,7 +6612,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
6586 /* RESERVED [2] */ 6612 /* RESERVED [2] */
6587 0, 0, 0, 0, 6613 0, 0, 0, 0,
6588 /* RESERVED [2] */ 6614 /* RESERVED [2] */
6589 0, 0, 0, 0, } 6615 0, 0, 0, 0, ))
6590 }, 6616 },
6591 { }, 6617 { },
6592}; 6618};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
index d36da5652de6..bbace1478613 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
@@ -1988,7 +1988,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
1988}; 1988};
1989 1989
1990static const struct pinmux_cfg_reg pinmux_config_regs[] = { 1990static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1991 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { 1991 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
1992 0, 0, 1992 0, 0,
1993 0, 0, 1993 0, 0,
1994 0, 0, 1994 0, 0,
@@ -2020,9 +2020,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2020 GP_0_3_FN, FN_IP0_3, 2020 GP_0_3_FN, FN_IP0_3,
2021 GP_0_2_FN, FN_IP0_2, 2021 GP_0_2_FN, FN_IP0_2,
2022 GP_0_1_FN, FN_IP0_1, 2022 GP_0_1_FN, FN_IP0_1,
2023 GP_0_0_FN, FN_IP0_0 } 2023 GP_0_0_FN, FN_IP0_0 ))
2024 }, 2024 },
2025 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { 2025 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
2026 0, 0, 2026 0, 0,
2027 0, 0, 2027 0, 0,
2028 0, 0, 2028 0, 0,
@@ -2054,9 +2054,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2054 GP_1_3_FN, FN_IP1_8, 2054 GP_1_3_FN, FN_IP1_8,
2055 GP_1_2_FN, FN_IP1_7, 2055 GP_1_2_FN, FN_IP1_7,
2056 GP_1_1_FN, FN_IP1_6, 2056 GP_1_1_FN, FN_IP1_6,
2057 GP_1_0_FN, FN_IP1_5, } 2057 GP_1_0_FN, FN_IP1_5, ))
2058 }, 2058 },
2059 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { 2059 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
2060 GP_2_31_FN, FN_A15, 2060 GP_2_31_FN, FN_A15,
2061 GP_2_30_FN, FN_A14, 2061 GP_2_30_FN, FN_A14,
2062 GP_2_29_FN, FN_A13, 2062 GP_2_29_FN, FN_A13,
@@ -2088,9 +2088,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2088 GP_2_3_FN, FN_D3, 2088 GP_2_3_FN, FN_D3,
2089 GP_2_2_FN, FN_D2, 2089 GP_2_2_FN, FN_D2,
2090 GP_2_1_FN, FN_D1, 2090 GP_2_1_FN, FN_D1,
2091 GP_2_0_FN, FN_D0 } 2091 GP_2_0_FN, FN_D0 ))
2092 }, 2092 },
2093 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { 2093 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
2094 0, 0, 2094 0, 0,
2095 0, 0, 2095 0, 0,
2096 0, 0, 2096 0, 0,
@@ -2122,9 +2122,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2122 GP_3_3_FN, FN_A19, 2122 GP_3_3_FN, FN_A19,
2123 GP_3_2_FN, FN_A18, 2123 GP_3_2_FN, FN_A18,
2124 GP_3_1_FN, FN_A17, 2124 GP_3_1_FN, FN_A17,
2125 GP_3_0_FN, FN_A16 } 2125 GP_3_0_FN, FN_A16 ))
2126 }, 2126 },
2127 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { 2127 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
2128 0, 0, 2128 0, 0,
2129 0, 0, 2129 0, 0,
2130 0, 0, 2130 0, 0,
@@ -2156,9 +2156,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2156 GP_4_3_FN, FN_VI0_VSYNC_N, 2156 GP_4_3_FN, FN_VI0_VSYNC_N,
2157 GP_4_2_FN, FN_VI0_HSYNC_N, 2157 GP_4_2_FN, FN_VI0_HSYNC_N,
2158 GP_4_1_FN, FN_VI0_CLKENB, 2158 GP_4_1_FN, FN_VI0_CLKENB,
2159 GP_4_0_FN, FN_VI0_CLK } 2159 GP_4_0_FN, FN_VI0_CLK ))
2160 }, 2160 },
2161 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { 2161 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
2162 0, 0, 2162 0, 0,
2163 0, 0, 2163 0, 0,
2164 0, 0, 2164 0, 0,
@@ -2190,9 +2190,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2190 GP_5_3_FN, FN_VI1_VSYNC_N, 2190 GP_5_3_FN, FN_VI1_VSYNC_N,
2191 GP_5_2_FN, FN_VI1_HSYNC_N, 2191 GP_5_2_FN, FN_VI1_HSYNC_N,
2192 GP_5_1_FN, FN_VI1_CLKENB, 2192 GP_5_1_FN, FN_VI1_CLKENB,
2193 GP_5_0_FN, FN_VI1_CLK } 2193 GP_5_0_FN, FN_VI1_CLK ))
2194 }, 2194 },
2195 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { 2195 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
2196 0, 0, 2196 0, 0,
2197 0, 0, 2197 0, 0,
2198 0, 0, 2198 0, 0,
@@ -2224,9 +2224,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2224 GP_6_3_FN, FN_IP2_3, 2224 GP_6_3_FN, FN_IP2_3,
2225 GP_6_2_FN, FN_IP2_2, 2225 GP_6_2_FN, FN_IP2_2,
2226 GP_6_1_FN, FN_IP2_1, 2226 GP_6_1_FN, FN_IP2_1,
2227 GP_6_0_FN, FN_IP2_0 } 2227 GP_6_0_FN, FN_IP2_0 ))
2228 }, 2228 },
2229 { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) { 2229 { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1, GROUP(
2230 0, 0, 2230 0, 0,
2231 0, 0, 2231 0, 0,
2232 0, 0, 2232 0, 0,
@@ -2258,9 +2258,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2258 GP_7_3_FN, FN_IP3_3, 2258 GP_7_3_FN, FN_IP3_3,
2259 GP_7_2_FN, FN_IP3_2, 2259 GP_7_2_FN, FN_IP3_2,
2260 GP_7_1_FN, FN_IP3_1, 2260 GP_7_1_FN, FN_IP3_1,
2261 GP_7_0_FN, FN_IP3_0 } 2261 GP_7_0_FN, FN_IP3_0 ))
2262 }, 2262 },
2263 { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) { 2263 { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1, GROUP(
2264 0, 0, 2264 0, 0,
2265 0, 0, 2265 0, 0,
2266 0, 0, 2266 0, 0,
@@ -2292,9 +2292,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2292 GP_8_3_FN, FN_IP4_3_2, 2292 GP_8_3_FN, FN_IP4_3_2,
2293 GP_8_2_FN, FN_IP4_1, 2293 GP_8_2_FN, FN_IP4_1,
2294 GP_8_1_FN, FN_IP4_0, 2294 GP_8_1_FN, FN_IP4_0,
2295 GP_8_0_FN, FN_VI4_CLK } 2295 GP_8_0_FN, FN_VI4_CLK ))
2296 }, 2296 },
2297 { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) { 2297 { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1, GROUP(
2298 0, 0, 2298 0, 0,
2299 0, 0, 2299 0, 0,
2300 0, 0, 2300 0, 0,
@@ -2326,9 +2326,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2326 GP_9_3_FN, FN_IP5_2, 2326 GP_9_3_FN, FN_IP5_2,
2327 GP_9_2_FN, FN_IP5_1, 2327 GP_9_2_FN, FN_IP5_1,
2328 GP_9_1_FN, FN_IP5_0, 2328 GP_9_1_FN, FN_IP5_0,
2329 GP_9_0_FN, FN_VI5_CLK } 2329 GP_9_0_FN, FN_VI5_CLK ))
2330 }, 2330 },
2331 { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1) { 2331 { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1, GROUP(
2332 GP_10_31_FN, FN_CAN1_RX, 2332 GP_10_31_FN, FN_CAN1_RX,
2333 GP_10_30_FN, FN_CAN1_TX, 2333 GP_10_30_FN, FN_CAN1_TX,
2334 GP_10_29_FN, FN_CAN_CLK, 2334 GP_10_29_FN, FN_CAN_CLK,
@@ -2360,9 +2360,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2360 GP_10_3_FN, FN_IP6_2, 2360 GP_10_3_FN, FN_IP6_2,
2361 GP_10_2_FN, FN_HRTS0_N, 2361 GP_10_2_FN, FN_HRTS0_N,
2362 GP_10_1_FN, FN_IP6_1, 2362 GP_10_1_FN, FN_IP6_1,
2363 GP_10_0_FN, FN_IP6_0 } 2363 GP_10_0_FN, FN_IP6_0 ))
2364 }, 2364 },
2365 { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1) { 2365 { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1, GROUP(
2366 0, 0, 2366 0, 0,
2367 0, 0, 2367 0, 0,
2368 GP_11_29_FN, FN_AVS2, 2368 GP_11_29_FN, FN_AVS2,
@@ -2394,13 +2394,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2394 GP_11_3_FN, FN_IP7_6, 2394 GP_11_3_FN, FN_IP7_6,
2395 GP_11_2_FN, FN_IP7_5_4, 2395 GP_11_2_FN, FN_IP7_5_4,
2396 GP_11_1_FN, FN_IP7_3_2, 2396 GP_11_1_FN, FN_IP7_3_2,
2397 GP_11_0_FN, FN_IP7_1_0 } 2397 GP_11_0_FN, FN_IP7_1_0 ))
2398 }, 2398 },
2399 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32, 2399 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2400 4, 4, 2400 GROUP(4, 4,
2401 1, 1, 1, 1, 1, 1, 1, 1, 2401 1, 1, 1, 1, 1, 1, 1, 1,
2402 1, 1, 1, 1, 1, 1, 1, 1, 2402 1, 1, 1, 1, 1, 1, 1, 1,
2403 1, 1, 1, 1, 1, 1, 1, 1) { 2403 1, 1, 1, 1, 1, 1, 1, 1),
2404 GROUP(
2404 /* IP0_31_28 [4] */ 2405 /* IP0_31_28 [4] */
2405 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2406 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2406 /* IP0_27_24 [4] */ 2407 /* IP0_27_24 [4] */
@@ -2452,13 +2453,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2452 /* IP0_1 [1] */ 2453 /* IP0_1 [1] */
2453 FN_DU0_DR1_DATA1, 0, 2454 FN_DU0_DR1_DATA1, 0,
2454 /* IP0_0 [1] */ 2455 /* IP0_0 [1] */
2455 FN_DU0_DR0_DATA0, 0 } 2456 FN_DU0_DR0_DATA0, 0 ))
2456 }, 2457 },
2457 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32, 2458 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2458 4, 4, 2459 GROUP(4, 4,
2459 1, 1, 1, 1, 1, 1, 1, 1, 2460 1, 1, 1, 1, 1, 1, 1, 1,
2460 1, 1, 1, 1, 1, 1, 1, 1, 2461 1, 1, 1, 1, 1, 1, 1, 1,
2461 1, 1, 1, 1, 1, 1, 1, 1) { 2462 1, 1, 1, 1, 1, 1, 1, 1),
2463 GROUP(
2462 /* IP1_31_28 [4] */ 2464 /* IP1_31_28 [4] */
2463 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2465 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2464 /* IP1_27_24 [4] */ 2466 /* IP1_27_24 [4] */
@@ -2510,13 +2512,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2510 /* IP1_1 [1] */ 2512 /* IP1_1 [1] */
2511 FN_DU0_EXVSYNC_DU0_VSYNC, 0, 2513 FN_DU0_EXVSYNC_DU0_VSYNC, 0,
2512 /* IP1_0 [1] */ 2514 /* IP1_0 [1] */
2513 FN_DU0_EXHSYNC_DU0_HSYNC, 0 } 2515 FN_DU0_EXHSYNC_DU0_HSYNC, 0 ))
2514 }, 2516 },
2515 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32, 2517 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2516 4, 4, 2518 GROUP(4, 4,
2517 4, 3, 1, 2519 4, 3, 1,
2518 1, 1, 1, 1, 1, 1, 1, 1, 2520 1, 1, 1, 1, 1, 1, 1, 1,
2519 1, 1, 1, 1, 1, 1, 1, 1) { 2521 1, 1, 1, 1, 1, 1, 1, 1),
2522 GROUP(
2520 /* IP2_31_28 [4] */ 2523 /* IP2_31_28 [4] */
2521 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2524 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2522 /* IP2_27_24 [4] */ 2525 /* IP2_27_24 [4] */
@@ -2558,13 +2561,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2558 /* IP2_1 [1] */ 2561 /* IP2_1 [1] */
2559 FN_VI2_CLKENB, FN_AVB_RX_DV, 2562 FN_VI2_CLKENB, FN_AVB_RX_DV,
2560 /* IP2_0 [1] */ 2563 /* IP2_0 [1] */
2561 FN_VI2_CLK, FN_AVB_RX_CLK } 2564 FN_VI2_CLK, FN_AVB_RX_CLK ))
2562 }, 2565 },
2563 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32, 2566 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2564 4, 4, 2567 GROUP(4, 4,
2565 4, 4, 2568 4, 4,
2566 1, 1, 1, 1, 1, 1, 1, 1, 2569 1, 1, 1, 1, 1, 1, 1, 1,
2567 1, 1, 1, 1, 1, 1, 1, 1) { 2570 1, 1, 1, 1, 1, 1, 1, 1),
2571 GROUP(
2568 /* IP3_31_28 [4] */ 2572 /* IP3_31_28 [4] */
2569 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2573 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2570 /* IP3_27_24 [4] */ 2574 /* IP3_27_24 [4] */
@@ -2604,12 +2608,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2604 /* IP3_1 [1] */ 2608 /* IP3_1 [1] */
2605 FN_VI3_CLKENB, FN_AVB_TXD4, 2609 FN_VI3_CLKENB, FN_AVB_TXD4,
2606 /* IP3_0 [1] */ 2610 /* IP3_0 [1] */
2607 FN_VI3_CLK, FN_AVB_TX_CLK } 2611 FN_VI3_CLK, FN_AVB_TX_CLK ))
2608 }, 2612 },
2609 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32, 2613 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2610 4, 3, 1, 2614 GROUP(4, 3, 1,
2611 1, 1, 1, 2, 2, 2, 2615 1, 1, 1, 2, 2, 2,
2612 2, 2, 2, 2, 2, 1, 2, 1, 1) { 2616 2, 2, 2, 2, 2, 1, 2, 1, 1),
2617 GROUP(
2613 /* IP4_31_28 [4] */ 2618 /* IP4_31_28 [4] */
2614 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2619 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2615 /* IP4_27_25 [3] */ 2620 /* IP4_27_25 [3] */
@@ -2645,13 +2650,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2645 /* IP4_1 [1] */ 2650 /* IP4_1 [1] */
2646 FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5, 2651 FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
2647 /* IP4_0 [1] */ 2652 /* IP4_0 [1] */
2648 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 } 2653 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 ))
2649 }, 2654 },
2650 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32, 2655 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2651 4, 4, 2656 GROUP(4, 4,
2652 4, 4, 2657 4, 4,
2653 4, 1, 1, 1, 1, 2658 4, 1, 1, 1, 1,
2654 1, 1, 1, 1, 1, 1, 1, 1) { 2659 1, 1, 1, 1, 1, 1, 1, 1),
2660 GROUP(
2655 /* IP5_31_28 [4] */ 2661 /* IP5_31_28 [4] */
2656 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2662 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2657 /* IP5_27_24 [4] */ 2663 /* IP5_27_24 [4] */
@@ -2685,13 +2691,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2685 /* IP5_1 [1] */ 2691 /* IP5_1 [1] */
2686 FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B, 2692 FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
2687 /* IP5_0 [1] */ 2693 /* IP5_0 [1] */
2688 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B } 2694 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B ))
2689 }, 2695 },
2690 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32, 2696 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2691 4, 4, 2697 GROUP(4, 4,
2692 4, 1, 2, 1, 2698 4, 1, 2, 1,
2693 2, 2, 2, 2, 2699 2, 2, 2, 2,
2694 1, 1, 1, 1, 1, 1, 1, 1) { 2700 1, 1, 1, 1, 1, 1, 1, 1),
2701 GROUP(
2695 /* IP6_31_28 [4] */ 2702 /* IP6_31_28 [4] */
2696 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2703 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2697 /* IP6_27_24 [4] */ 2704 /* IP6_27_24 [4] */
@@ -2727,13 +2734,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2727 /* IP6_1 [1] */ 2734 /* IP6_1 [1] */
2728 FN_MSIOF0_SYNC, FN_HCTS0_N, 2735 FN_MSIOF0_SYNC, FN_HCTS0_N,
2729 /* IP6_0 [1] */ 2736 /* IP6_0 [1] */
2730 FN_MSIOF0_SCK, FN_HSCK0 } 2737 FN_MSIOF0_SCK, FN_HSCK0 ))
2731 }, 2738 },
2732 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32, 2739 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
2733 4, 4, 2740 GROUP(4, 4,
2734 3, 1, 1, 1, 1, 1, 2741 3, 1, 1, 1, 1, 1,
2735 2, 2, 2, 2, 2742 2, 2, 2, 2,
2736 1, 1, 2, 2, 2) { 2743 1, 1, 2, 2, 2),
2744 GROUP(
2737 /* IP7_31_28 [4] */ 2745 /* IP7_31_28 [4] */
2738 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2746 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2739 /* IP7_27_24 [4] */ 2747 /* IP7_27_24 [4] */
@@ -2767,7 +2775,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2767 /* IP7_3_2 [2] */ 2775 /* IP7_3_2 [2] */
2768 FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0, 2776 FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
2769 /* IP7_1_0 [2] */ 2777 /* IP7_1_0 [2] */
2770 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 } 2778 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 ))
2771 }, 2779 },
2772 { }, 2780 { },
2773}; 2781};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
index 958a5f714c93..1ff4969d8381 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
@@ -7,6 +7,7 @@
7 * Copyright (C) 2015-2017 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * Copyright (C) 2015-2017 Cogent Embedded, Inc. <source@cogentembedded.com>
8 */ 8 */
9 9
10#include <linux/errno.h>
10#include <linux/kernel.h> 11#include <linux/kernel.h>
11#include <linux/sys_soc.h> 12#include <linux/sys_soc.h>
12 13
@@ -4617,7 +4618,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
4617}; 4618};
4618 4619
4619static const struct pinmux_cfg_reg pinmux_config_regs[] = { 4620static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4620 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { 4621 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
4621 GP_0_31_FN, FN_IP2_17_16, 4622 GP_0_31_FN, FN_IP2_17_16,
4622 GP_0_30_FN, FN_IP2_15_14, 4623 GP_0_30_FN, FN_IP2_15_14,
4623 GP_0_29_FN, FN_IP2_13_12, 4624 GP_0_29_FN, FN_IP2_13_12,
@@ -4649,9 +4650,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4649 GP_0_3_FN, FN_IP0_27_26, 4650 GP_0_3_FN, FN_IP0_27_26,
4650 GP_0_2_FN, FN_IP0_25, 4651 GP_0_2_FN, FN_IP0_25,
4651 GP_0_1_FN, FN_IP0_24, 4652 GP_0_1_FN, FN_IP0_24,
4652 GP_0_0_FN, FN_IP0_23_22, } 4653 GP_0_0_FN, FN_IP0_23_22, ))
4653 }, 4654 },
4654 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { 4655 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
4655 0, 0, 4656 0, 0,
4656 0, 0, 4657 0, 0,
4657 0, 0, 4658 0, 0,
@@ -4683,9 +4684,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4683 GP_1_3_FN, FN_IP2_29_27, 4684 GP_1_3_FN, FN_IP2_29_27,
4684 GP_1_2_FN, FN_IP2_26_24, 4685 GP_1_2_FN, FN_IP2_26_24,
4685 GP_1_1_FN, FN_IP2_23_21, 4686 GP_1_1_FN, FN_IP2_23_21,
4686 GP_1_0_FN, FN_IP2_20_18, } 4687 GP_1_0_FN, FN_IP2_20_18, ))
4687 }, 4688 },
4688 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { 4689 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
4689 GP_2_31_FN, FN_IP6_7_6, 4690 GP_2_31_FN, FN_IP6_7_6,
4690 GP_2_30_FN, FN_IP6_5_4, 4691 GP_2_30_FN, FN_IP6_5_4,
4691 GP_2_29_FN, FN_IP6_3_2, 4692 GP_2_29_FN, FN_IP6_3_2,
@@ -4717,9 +4718,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4717 GP_2_3_FN, FN_IP4_11_10, 4718 GP_2_3_FN, FN_IP4_11_10,
4718 GP_2_2_FN, FN_IP4_9_8, 4719 GP_2_2_FN, FN_IP4_9_8,
4719 GP_2_1_FN, FN_IP4_7_5, 4720 GP_2_1_FN, FN_IP4_7_5,
4720 GP_2_0_FN, FN_IP4_4_2 } 4721 GP_2_0_FN, FN_IP4_4_2 ))
4721 }, 4722 },
4722 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { 4723 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
4723 GP_3_31_FN, FN_IP8_22_20, 4724 GP_3_31_FN, FN_IP8_22_20,
4724 GP_3_30_FN, FN_IP8_19_17, 4725 GP_3_30_FN, FN_IP8_19_17,
4725 GP_3_29_FN, FN_IP8_16_15, 4726 GP_3_29_FN, FN_IP8_16_15,
@@ -4751,9 +4752,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4751 GP_3_3_FN, FN_IP6_11, 4752 GP_3_3_FN, FN_IP6_11,
4752 GP_3_2_FN, FN_IP6_10, 4753 GP_3_2_FN, FN_IP6_10,
4753 GP_3_1_FN, FN_IP6_9, 4754 GP_3_1_FN, FN_IP6_9,
4754 GP_3_0_FN, FN_IP6_8 } 4755 GP_3_0_FN, FN_IP6_8 ))
4755 }, 4756 },
4756 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { 4757 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
4757 GP_4_31_FN, FN_IP11_17_16, 4758 GP_4_31_FN, FN_IP11_17_16,
4758 GP_4_30_FN, FN_IP11_15_14, 4759 GP_4_30_FN, FN_IP11_15_14,
4759 GP_4_29_FN, FN_IP11_13_11, 4760 GP_4_29_FN, FN_IP11_13_11,
@@ -4785,9 +4786,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4785 GP_4_3_FN, FN_IP9_2_0, 4786 GP_4_3_FN, FN_IP9_2_0,
4786 GP_4_2_FN, FN_IP8_31_29, 4787 GP_4_2_FN, FN_IP8_31_29,
4787 GP_4_1_FN, FN_IP8_28_26, 4788 GP_4_1_FN, FN_IP8_28_26,
4788 GP_4_0_FN, FN_IP8_25_23 } 4789 GP_4_0_FN, FN_IP8_25_23 ))
4789 }, 4790 },
4790 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { 4791 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
4791 0, 0, 4792 0, 0,
4792 0, 0, 4793 0, 0,
4793 0, 0, 4794 0, 0,
@@ -4819,9 +4820,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4819 GP_5_3_FN, FN_IP11_29_27, 4820 GP_5_3_FN, FN_IP11_29_27,
4820 GP_5_2_FN, FN_IP11_26_24, 4821 GP_5_2_FN, FN_IP11_26_24,
4821 GP_5_1_FN, FN_IP11_23_21, 4822 GP_5_1_FN, FN_IP11_23_21,
4822 GP_5_0_FN, FN_IP11_20_18 } 4823 GP_5_0_FN, FN_IP11_20_18 ))
4823 }, 4824 },
4824 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { 4825 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
4825 0, 0, 4826 0, 0,
4826 0, 0, 4827 0, 0,
4827 0, 0, 4828 0, 0,
@@ -4853,11 +4854,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4853 GP_6_3_FN, FN_SD0_DATA1, 4854 GP_6_3_FN, FN_SD0_DATA1,
4854 GP_6_2_FN, FN_SD0_DATA0, 4855 GP_6_2_FN, FN_SD0_DATA0,
4855 GP_6_1_FN, FN_SD0_CMD, 4856 GP_6_1_FN, FN_SD0_CMD,
4856 GP_6_0_FN, FN_SD0_CLK } 4857 GP_6_0_FN, FN_SD0_CLK ))
4857 }, 4858 },
4858 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, 4859 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4859 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 4860 GROUP(2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1,
4860 2, 1, 1, 1, 1, 1, 1, 1, 1) { 4861 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1),
4862 GROUP(
4861 /* IP0_31_30 [2] */ 4863 /* IP0_31_30 [2] */
4862 FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0, 4864 FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
4863 /* IP0_29_28 [2] */ 4865 /* IP0_29_28 [2] */
@@ -4907,11 +4909,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4907 /* IP0_1 [1] */ 4909 /* IP0_1 [1] */
4908 0, 0, 4910 0, 0,
4909 /* IP0_0 [1] */ 4911 /* IP0_0 [1] */
4910 FN_SD1_CD, FN_CAN0_RX, } 4912 FN_SD1_CD, FN_CAN0_RX, ))
4911 }, 4913 },
4912 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, 4914 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4913 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2, 4915 GROUP(2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2,
4914 2, 2) { 4916 3, 2, 2, 2, 2),
4917 GROUP(
4915 /* IP1_31_30 [2] */ 4918 /* IP1_31_30 [2] */
4916 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C, 4919 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
4917 /* IP1_29_28 [2] */ 4920 /* IP1_29_28 [2] */
@@ -4947,10 +4950,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4947 /* IP1_3_2 [2] */ 4950 /* IP1_3_2 [2] */
4948 FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B, 4951 FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
4949 /* IP1_1_0 [2] */ 4952 /* IP1_1_0 [2] */
4950 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, } 4953 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, ))
4951 }, 4954 },
4952 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, 4955 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4953 2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) { 4956 GROUP(2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2),
4957 GROUP(
4954 /* IP2_31_30 [2] */ 4958 /* IP2_31_30 [2] */
4955 FN_A20, FN_SPCLK, 0, 0, 4959 FN_A20, FN_SPCLK, 0, 0,
4956 /* IP2_29_27 [3] */ 4960 /* IP2_29_27 [3] */
@@ -4982,10 +4986,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4982 /* IP2_3_2 [2] */ 4986 /* IP2_3_2 [2] */
4983 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0, 4987 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
4984 /* IP2_1_0 [2] */ 4988 /* IP2_1_0 [2] */
4985 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, } 4989 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, ))
4986 }, 4990 },
4987 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, 4991 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4988 1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) { 4992 GROUP(1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2,
4993 2, 2, 2, 2),
4994 GROUP(
4989 /* IP3_31 [1] */ 4995 /* IP3_31 [1] */
4990 FN_RD_WR_N, FN_ATAG1_N, 4996 FN_RD_WR_N, FN_ATAG1_N,
4991 /* IP3_30 [1] */ 4997 /* IP3_30 [1] */
@@ -5022,10 +5028,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5022 /* IP3_3_2 [2] */ 5028 /* IP3_3_2 [2] */
5023 FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N, 5029 FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N,
5024 /* IP3_1_0 [2] */ 5030 /* IP3_1_0 [2] */
5025 FN_A21, FN_MOSI_IO0, 0, 0, } 5031 FN_A21, FN_MOSI_IO0, 0, 0, ))
5026 }, 5032 },
5027 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, 5033 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5028 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) { 5034 GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2),
5035 GROUP(
5029 /* IP4_31_30 [2] */ 5036 /* IP4_31_30 [2] */
5030 FN_DU0_DG4, FN_LCDOUT12, 0, 0, 5037 FN_DU0_DG4, FN_LCDOUT12, 0, 0,
5031 /* IP4_29_28 [2] */ 5038 /* IP4_29_28 [2] */
@@ -5057,10 +5064,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5057 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, 5064 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
5058 0, 0, 0, 0, 5065 0, 0, 0, 0,
5059 /* IP4_1_0 [2] */ 5066 /* IP4_1_0 [2] */
5060 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, } 5067 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, ))
5061 }, 5068 },
5062 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, 5069 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5063 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) { 5070 GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
5071 2, 2, 2),
5072 GROUP(
5064 /* IP5_31_30 [2] */ 5073 /* IP5_31_30 [2] */
5065 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0, 5074 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0,
5066 /* IP5_29_28 [2] */ 5075 /* IP5_29_28 [2] */
@@ -5092,11 +5101,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5092 /* IP5_3_2 [2] */ 5101 /* IP5_3_2 [2] */
5093 FN_DU0_DG6, FN_LCDOUT14, 0, 0, 5102 FN_DU0_DG6, FN_LCDOUT14, 0, 0,
5094 /* IP5_1_0 [2] */ 5103 /* IP5_1_0 [2] */
5095 FN_DU0_DG5, FN_LCDOUT13, 0, 0, } 5104 FN_DU0_DG5, FN_LCDOUT13, 0, 0, ))
5096 }, 5105 },
5097 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, 5106 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5098 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 5107 GROUP(3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1,
5099 2, 2) { 5108 1, 1, 2, 2, 2, 2),
5109 GROUP(
5100 /* IP6_31_29 [3] */ 5110 /* IP6_31_29 [3] */
5101 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, 5111 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D,
5102 FN_AVB_TX_CLK, FN_ADIDATA, 0, 0, 5112 FN_AVB_TX_CLK, FN_ADIDATA, 0, 0,
@@ -5138,10 +5148,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5138 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 5148 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0,
5139 0, 5149 0,
5140 /* IP6_1_0 [2] */ 5150 /* IP6_1_0 [2] */
5141 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, } 5151 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, ))
5142 }, 5152 },
5143 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, 5153 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5144 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { 5154 GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
5155 GROUP(
5145 /* IP7_31 [1] */ 5156 /* IP7_31 [1] */
5146 FN_DREQ0_N, FN_SCIFB1_RXD, 5157 FN_DREQ0_N, FN_SCIFB1_RXD,
5147 /* IP7_30 [1] */ 5158 /* IP7_30 [1] */
@@ -5175,10 +5186,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5175 FN_AVB_TXD1, FN_ADICLK, 0, 0, 5186 FN_AVB_TXD1, FN_ADICLK, 0, 0,
5176 /* IP7_2_0 [3] */ 5187 /* IP7_2_0 [3] */
5177 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, 5188 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D,
5178 FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, } 5189 FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, ))
5179 }, 5190 },
5180 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, 5191 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5181 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) { 5192 GROUP(3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3),
5193 GROUP(
5182 /* IP8_31_29 [3] */ 5194 /* IP8_31_29 [3] */
5183 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, 5195 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
5184 0, FN_TS_SDEN_D, FN_FMCLK_C, 0, 5196 0, FN_TS_SDEN_D, FN_FMCLK_C, 0,
@@ -5210,10 +5222,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5210 FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0, 5222 FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
5211 /* IP8_2_0 [3] */ 5223 /* IP8_2_0 [3] */
5212 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, 5224 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
5213 FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, } 5225 FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, ))
5214 }, 5226 },
5215 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, 5227 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5216 1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3) { 5228 GROUP(1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3),
5229 GROUP(
5217 /* IP9_31 [1] */ 5230 /* IP9_31 [1] */
5218 0, 0, 5231 0, 0,
5219 /* IP9_30_28 [3] */ 5232 /* IP9_30_28 [3] */
@@ -5246,10 +5259,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5246 0, FN_TPUTO1_C, 0, 0, 5259 0, FN_TPUTO1_C, 0, 0,
5247 /* IP9_2_0 [3] */ 5260 /* IP9_2_0 [3] */
5248 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, 5261 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
5249 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, } 5262 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, ))
5250 }, 5263 },
5251 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, 5264 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5252 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { 5265 GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
5266 GROUP(
5253 /* IP10_31_30 [2] */ 5267 /* IP10_31_30 [2] */
5254 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0, 5268 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0,
5255 /* IP10_29_27 [3] */ 5269 /* IP10_29_27 [3] */
@@ -5281,10 +5295,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5281 0, 0, 0, 0, 5295 0, 0, 0, 0,
5282 /* IP10_2_0 [3] */ 5296 /* IP10_2_0 [3] */
5283 FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, 5297 FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
5284 0, 0, 0, 0, } 5298 0, 0, 0, 0, ))
5285 }, 5299 },
5286 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, 5300 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5287 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) { 5301 GROUP(2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3),
5302 GROUP(
5288 /* IP11_31_30 [2] */ 5303 /* IP11_31_30 [2] */
5289 0, 0, 0, 0, 5304 0, 0, 0, 0,
5290 /* IP11_29_27 [3] */ 5305 /* IP11_29_27 [3] */
@@ -5316,10 +5331,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5316 0, 0, 0, 0, 5331 0, 0, 0, 0,
5317 /* IP11_2_0 [3] */ 5332 /* IP11_2_0 [3] */
5318 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, 5333 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
5319 0, 0, 0, 0, } 5334 0, 0, 0, 0, ))
5320 }, 5335 },
5321 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, 5336 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5322 2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) { 5337 GROUP(2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3),
5338 GROUP(
5323 /* IP12_31_30 [2] */ 5339 /* IP12_31_30 [2] */
5324 0, 0, 0, 0, 5340 0, 0, 0, 0,
5325 /* IP12_29_27 [3] */ 5341 /* IP12_29_27 [3] */
@@ -5351,10 +5367,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5351 FN_CAN1_RX_C, FN_DACK1_B, 0, 0, 5367 FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
5352 /* IP12_2_0 [3] */ 5368 /* IP12_2_0 [3] */
5353 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, 5369 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
5354 0, FN_DREQ1_N_B, 0, 0, } 5370 0, FN_DREQ1_N_B, 0, 0, ))
5355 }, 5371 },
5356 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, 5372 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5357 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) { 5373 GROUP(1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3),
5374 GROUP(
5358 /* IP13_31 [1] */ 5375 /* IP13_31 [1] */
5359 0, 0, 5376 0, 0,
5360 /* IP13_30 [1] */ 5377 /* IP13_30 [1] */
@@ -5391,11 +5408,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5391 FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0, 5408 FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
5392 /* IP13_2_0 [3] */ 5409 /* IP13_2_0 [3] */
5393 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, 5410 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
5394 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, } 5411 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, ))
5395 }, 5412 },
5396 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, 5413 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5397 2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 5414 GROUP(2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 2, 1),
5398 2, 1) { 5415 GROUP(
5399 /* SEL_ADG [2] */ 5416 /* SEL_ADG [2] */
5400 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, 5417 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
5401 /* RESERVED [1] */ 5418 /* RESERVED [1] */
@@ -5429,11 +5446,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5429 /* SEL_I2C05 [2] */ 5446 /* SEL_I2C05 [2] */
5430 FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3, 5447 FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
5431 /* RESERVED [1] */ 5448 /* RESERVED [1] */
5432 0, 0, } 5449 0, 0, ))
5433 }, 5450 },
5434 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, 5451 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5435 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 5452 GROUP(2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1,
5436 2, 2, 2, 1, 1, 2) { 5453 2, 2, 1, 1, 2, 2, 2, 1, 1, 2),
5454 GROUP(
5437 /* SEL_IEB [2] */ 5455 /* SEL_IEB [2] */
5438 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, 5456 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5439 /* SEL_IIC0 [2] */ 5457 /* SEL_IIC0 [2] */
@@ -5480,11 +5498,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5480 /* SEL_HSCIF1 [1] */ 5498 /* SEL_HSCIF1 [1] */
5481 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, 5499 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5482 /* RESERVED [2] */ 5500 /* RESERVED [2] */
5483 0, 0, 0, 0, } 5501 0, 0, 0, 0, ))
5484 }, 5502 },
5485 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, 5503 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5486 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 5504 GROUP(2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1,
5487 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { 5505 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
5506 GROUP(
5488 /* SEL_SCIF0 [2] */ 5507 /* SEL_SCIF0 [2] */
5489 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, 5508 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
5490 /* SEL_SCIF1 [2] */ 5509 /* SEL_SCIF1 [2] */
@@ -5537,7 +5556,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5537 /* RESERVED [1] */ 5556 /* RESERVED [1] */
5538 0, 0, 5557 0, 0,
5539 /* RESERVED [1] */ 5558 /* RESERVED [1] */
5540 0, 0, } 5559 0, 0, ))
5541 }, 5560 },
5542 { }, 5561 { },
5543}; 5562};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
index 287cfbb7e992..f16dfbad3f17 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
@@ -5,6 +5,7 @@
5 * Copyright (C) 2015-2017 Renesas Electronics Corporation 5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
6 */ 6 */
7 7
8#include <linux/errno.h>
8#include <linux/kernel.h> 9#include <linux/kernel.h>
9 10
10#include "core.h" 11#include "core.h"
@@ -153,11 +154,11 @@
153#define GPSR5_11 F_(RX2_A, IP12_7_4) 154#define GPSR5_11 F_(RX2_A, IP12_7_4)
154#define GPSR5_10 F_(TX2_A, IP12_3_0) 155#define GPSR5_10 F_(TX2_A, IP12_3_0)
155#define GPSR5_9 F_(SCK2, IP11_31_28) 156#define GPSR5_9 F_(SCK2, IP11_31_28)
156#define GPSR5_8 F_(RTS1_N_TANS, IP11_27_24) 157#define GPSR5_8 F_(RTS1_N, IP11_27_24)
157#define GPSR5_7 F_(CTS1_N, IP11_23_20) 158#define GPSR5_7 F_(CTS1_N, IP11_23_20)
158#define GPSR5_6 F_(TX1_A, IP11_19_16) 159#define GPSR5_6 F_(TX1_A, IP11_19_16)
159#define GPSR5_5 F_(RX1_A, IP11_15_12) 160#define GPSR5_5 F_(RX1_A, IP11_15_12)
160#define GPSR5_4 F_(RTS0_N_TANS, IP11_11_8) 161#define GPSR5_4 F_(RTS0_N, IP11_11_8)
161#define GPSR5_3 F_(CTS0_N, IP11_7_4) 162#define GPSR5_3 F_(CTS0_N, IP11_7_4)
162#define GPSR5_2 F_(TX0, IP11_3_0) 163#define GPSR5_2 F_(TX0, IP11_3_0)
163#define GPSR5_1 F_(RX0, IP10_31_28) 164#define GPSR5_1 F_(RX0, IP10_31_28)
@@ -198,8 +199,8 @@
198#define GPSR6_0 F_(SSI_SCK01239, IP13_23_20) 199#define GPSR6_0 F_(SSI_SCK01239, IP13_23_20)
199 200
200/* GPSR7 */ 201/* GPSR7 */
201#define GPSR7_3 FM(HDMI1_CEC) 202#define GPSR7_3 FM(GP7_03)
202#define GPSR7_2 FM(HDMI0_CEC) 203#define GPSR7_2 FM(GP7_02)
203#define GPSR7_1 FM(AVS2) 204#define GPSR7_1 FM(AVS2)
204#define GPSR7_0 FM(AVS1) 205#define GPSR7_0 FM(AVS1)
205 206
@@ -210,7 +211,7 @@
210#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 211#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 212#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 213#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 214#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 215#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 216#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 217#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -232,7 +233,7 @@
232#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 233#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 234#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 235#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 236#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 237#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 238#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 239#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -248,7 +249,7 @@
248#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 249#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 250#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 251#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 252#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 253#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 254#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 255#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -261,7 +262,7 @@
261#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 262#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 263#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 264#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 265#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 266#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 267#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 268#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -299,11 +300,11 @@
299#define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 300#define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301#define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302#define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP11_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303#define IP11_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304#define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305#define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306#define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP11_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307#define IP11_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308#define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309#define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 310#define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -339,7 +340,7 @@
339#define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 340#define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 341#define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342#define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 343#define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 344#define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 345#define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 346#define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -576,8 +577,8 @@ static const u16 pinmux_data[] = {
576 577
577 PINMUX_SINGLE(AVS1), 578 PINMUX_SINGLE(AVS1),
578 PINMUX_SINGLE(AVS2), 579 PINMUX_SINGLE(AVS2),
579 PINMUX_SINGLE(HDMI0_CEC), 580 PINMUX_SINGLE(GP7_02),
580 PINMUX_SINGLE(HDMI1_CEC), 581 PINMUX_SINGLE(GP7_03),
581 PINMUX_SINGLE(MSIOF0_RXD), 582 PINMUX_SINGLE(MSIOF0_RXD),
582 PINMUX_SINGLE(MSIOF0_SCK), 583 PINMUX_SINGLE(MSIOF0_SCK),
583 PINMUX_SINGLE(MSIOF0_TXD), 584 PINMUX_SINGLE(MSIOF0_TXD),
@@ -616,7 +617,7 @@ static const u16 pinmux_data[] = {
616 617
617 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), 618 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
618 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), 619 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
619 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_TANS_A, I2C_SEL_5_0, SEL_SCIF4_0), 620 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
620 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), 621 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
621 622
622 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), 623 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
@@ -756,7 +757,7 @@ static const u16 pinmux_data[] = {
756 757
757 PINMUX_IPSR_GPSR(IP3_7_4, A10), 758 PINMUX_IPSR_GPSR(IP3_7_4, A10),
758 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), 759 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
759 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1), 760 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
760 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), 761 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
761 762
762 PINMUX_IPSR_GPSR(IP3_11_8, A11), 763 PINMUX_IPSR_GPSR(IP3_11_8, A11),
@@ -859,7 +860,7 @@ static const u16 pinmux_data[] = {
859 860
860 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), 861 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
861 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), 862 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
862 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS), 863 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
863 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), 864 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
864 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), 865 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
865 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), 866 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
@@ -940,7 +941,7 @@ static const u16 pinmux_data[] = {
940 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), 941 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
941 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), 942 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
942 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), 943 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
943 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), 944 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
944 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), 945 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
945 946
946 PINMUX_IPSR_GPSR(IP6_31_28, D12), 947 PINMUX_IPSR_GPSR(IP6_31_28, D12),
@@ -1112,7 +1113,7 @@ static const u16 pinmux_data[] = {
1112 PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2), 1113 PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2),
1113 PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP), 1114 PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP),
1114 1115
1115 PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N_TANS), 1116 PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N),
1116 PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1), 1117 PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1117 PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), 1118 PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1118 PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1), 1119 PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1),
@@ -1141,7 +1142,7 @@ static const u16 pinmux_data[] = {
1141 PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1), 1142 PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1),
1142 PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA), 1143 PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA),
1143 1144
1144 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS), 1145 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N),
1145 PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0), 1146 PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1146 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), 1147 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1147 PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2), 1148 PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2),
@@ -1358,7 +1359,6 @@ static const u16 pinmux_data[] = {
1358 1359
1359 /* IPSR16 */ 1360 /* IPSR16 */
1360 PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0), 1361 PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0),
1361 PINMUX_IPSR_GPSR(IP16_3_0, CC5_OSCOUT),
1362 1362
1363 PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1), 1363 PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1),
1364 PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0), 1364 PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0),
@@ -2071,22 +2071,6 @@ static const unsigned int du_disp_pins[] = {
2071static const unsigned int du_disp_mux[] = { 2071static const unsigned int du_disp_mux[] = {
2072 DU_DISP_MARK, 2072 DU_DISP_MARK,
2073}; 2073};
2074/* - HDMI ------------------------------------------------------------------- */
2075static const unsigned int hdmi0_cec_pins[] = {
2076 /* HDMI0_CEC */
2077 RCAR_GP_PIN(7, 2),
2078};
2079static const unsigned int hdmi0_cec_mux[] = {
2080 HDMI0_CEC_MARK,
2081};
2082static const unsigned int hdmi1_cec_pins[] = {
2083 /* HDMI1_CEC */
2084 RCAR_GP_PIN(7, 3),
2085};
2086static const unsigned int hdmi1_cec_mux[] = {
2087 HDMI1_CEC_MARK,
2088};
2089
2090/* - HSCIF0 ----------------------------------------------------------------- */ 2074/* - HSCIF0 ----------------------------------------------------------------- */
2091static const unsigned int hscif0_data_pins[] = { 2075static const unsigned int hscif0_data_pins[] = {
2092 /* RX, TX */ 2076 /* RX, TX */
@@ -3235,7 +3219,7 @@ static const unsigned int scif0_ctrl_pins[] = {
3235 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), 3219 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3236}; 3220};
3237static const unsigned int scif0_ctrl_mux[] = { 3221static const unsigned int scif0_ctrl_mux[] = {
3238 RTS0_N_TANS_MARK, CTS0_N_MARK, 3222 RTS0_N_MARK, CTS0_N_MARK,
3239}; 3223};
3240/* - SCIF1 ------------------------------------------------------------------ */ 3224/* - SCIF1 ------------------------------------------------------------------ */
3241static const unsigned int scif1_data_a_pins[] = { 3225static const unsigned int scif1_data_a_pins[] = {
@@ -3257,7 +3241,7 @@ static const unsigned int scif1_ctrl_pins[] = {
3257 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), 3241 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3258}; 3242};
3259static const unsigned int scif1_ctrl_mux[] = { 3243static const unsigned int scif1_ctrl_mux[] = {
3260 RTS1_N_TANS_MARK, CTS1_N_MARK, 3244 RTS1_N_MARK, CTS1_N_MARK,
3261}; 3245};
3262 3246
3263static const unsigned int scif1_data_b_pins[] = { 3247static const unsigned int scif1_data_b_pins[] = {
@@ -3309,7 +3293,7 @@ static const unsigned int scif3_ctrl_pins[] = {
3309 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 3293 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3310}; 3294};
3311static const unsigned int scif3_ctrl_mux[] = { 3295static const unsigned int scif3_ctrl_mux[] = {
3312 RTS3_N_TANS_MARK, CTS3_N_MARK, 3296 RTS3_N_MARK, CTS3_N_MARK,
3313}; 3297};
3314static const unsigned int scif3_data_b_pins[] = { 3298static const unsigned int scif3_data_b_pins[] = {
3315 /* RX, TX */ 3299 /* RX, TX */
@@ -3338,7 +3322,7 @@ static const unsigned int scif4_ctrl_a_pins[] = {
3338 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), 3322 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3339}; 3323};
3340static const unsigned int scif4_ctrl_a_mux[] = { 3324static const unsigned int scif4_ctrl_a_mux[] = {
3341 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK, 3325 RTS4_N_A_MARK, CTS4_N_A_MARK,
3342}; 3326};
3343static const unsigned int scif4_data_b_pins[] = { 3327static const unsigned int scif4_data_b_pins[] = {
3344 /* RX, TX */ 3328 /* RX, TX */
@@ -3359,7 +3343,7 @@ static const unsigned int scif4_ctrl_b_pins[] = {
3359 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), 3343 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3360}; 3344};
3361static const unsigned int scif4_ctrl_b_mux[] = { 3345static const unsigned int scif4_ctrl_b_mux[] = {
3362 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK, 3346 RTS4_N_B_MARK, CTS4_N_B_MARK,
3363}; 3347};
3364static const unsigned int scif4_data_c_pins[] = { 3348static const unsigned int scif4_data_c_pins[] = {
3365 /* RX, TX */ 3349 /* RX, TX */
@@ -3380,7 +3364,7 @@ static const unsigned int scif4_ctrl_c_pins[] = {
3380 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), 3364 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3381}; 3365};
3382static const unsigned int scif4_ctrl_c_mux[] = { 3366static const unsigned int scif4_ctrl_c_mux[] = {
3383 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK, 3367 RTS4_N_C_MARK, CTS4_N_C_MARK,
3384}; 3368};
3385/* - SCIF5 ------------------------------------------------------------------ */ 3369/* - SCIF5 ------------------------------------------------------------------ */
3386static const unsigned int scif5_data_pins[] = { 3370static const unsigned int scif5_data_pins[] = {
@@ -3944,8 +3928,6 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3944 SH_PFC_PIN_GROUP(du_oddf), 3928 SH_PFC_PIN_GROUP(du_oddf),
3945 SH_PFC_PIN_GROUP(du_cde), 3929 SH_PFC_PIN_GROUP(du_cde),
3946 SH_PFC_PIN_GROUP(du_disp), 3930 SH_PFC_PIN_GROUP(du_disp),
3947 SH_PFC_PIN_GROUP(hdmi0_cec),
3948 SH_PFC_PIN_GROUP(hdmi1_cec),
3949 SH_PFC_PIN_GROUP(hscif0_data), 3931 SH_PFC_PIN_GROUP(hscif0_data),
3950 SH_PFC_PIN_GROUP(hscif0_clk), 3932 SH_PFC_PIN_GROUP(hscif0_clk),
3951 SH_PFC_PIN_GROUP(hscif0_ctrl), 3933 SH_PFC_PIN_GROUP(hscif0_ctrl),
@@ -4299,14 +4281,6 @@ static const char * const du_groups[] = {
4299 "du_disp", 4281 "du_disp",
4300}; 4282};
4301 4283
4302static const char * const hdmi0_groups[] = {
4303 "hdmi0_cec",
4304};
4305
4306static const char * const hdmi1_groups[] = {
4307 "hdmi1_cec",
4308};
4309
4310static const char * const hscif0_groups[] = { 4284static const char * const hscif0_groups[] = {
4311 "hscif0_data", 4285 "hscif0_data",
4312 "hscif0_clk", 4286 "hscif0_clk",
@@ -4694,8 +4668,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
4694 SH_PFC_FUNCTION(drif2), 4668 SH_PFC_FUNCTION(drif2),
4695 SH_PFC_FUNCTION(drif3), 4669 SH_PFC_FUNCTION(drif3),
4696 SH_PFC_FUNCTION(du), 4670 SH_PFC_FUNCTION(du),
4697 SH_PFC_FUNCTION(hdmi0),
4698 SH_PFC_FUNCTION(hdmi1),
4699 SH_PFC_FUNCTION(hscif0), 4671 SH_PFC_FUNCTION(hscif0),
4700 SH_PFC_FUNCTION(hscif1), 4672 SH_PFC_FUNCTION(hscif1),
4701 SH_PFC_FUNCTION(hscif2), 4673 SH_PFC_FUNCTION(hscif2),
@@ -4745,7 +4717,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
4745static const struct pinmux_cfg_reg pinmux_config_regs[] = { 4717static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4746#define F_(x, y) FN_##y 4718#define F_(x, y) FN_##y
4747#define FM(x) FN_##x 4719#define FM(x) FN_##x
4748 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { 4720 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
4749 0, 0, 4721 0, 0,
4750 0, 0, 4722 0, 0,
4751 0, 0, 4723 0, 0,
@@ -4777,9 +4749,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4777 GP_0_3_FN, GPSR0_3, 4749 GP_0_3_FN, GPSR0_3,
4778 GP_0_2_FN, GPSR0_2, 4750 GP_0_2_FN, GPSR0_2,
4779 GP_0_1_FN, GPSR0_1, 4751 GP_0_1_FN, GPSR0_1,
4780 GP_0_0_FN, GPSR0_0, } 4752 GP_0_0_FN, GPSR0_0, ))
4781 }, 4753 },
4782 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { 4754 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
4783 0, 0, 4755 0, 0,
4784 0, 0, 4756 0, 0,
4785 0, 0, 4757 0, 0,
@@ -4811,9 +4783,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4811 GP_1_3_FN, GPSR1_3, 4783 GP_1_3_FN, GPSR1_3,
4812 GP_1_2_FN, GPSR1_2, 4784 GP_1_2_FN, GPSR1_2,
4813 GP_1_1_FN, GPSR1_1, 4785 GP_1_1_FN, GPSR1_1,
4814 GP_1_0_FN, GPSR1_0, } 4786 GP_1_0_FN, GPSR1_0, ))
4815 }, 4787 },
4816 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { 4788 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
4817 0, 0, 4789 0, 0,
4818 0, 0, 4790 0, 0,
4819 0, 0, 4791 0, 0,
@@ -4845,9 +4817,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4845 GP_2_3_FN, GPSR2_3, 4817 GP_2_3_FN, GPSR2_3,
4846 GP_2_2_FN, GPSR2_2, 4818 GP_2_2_FN, GPSR2_2,
4847 GP_2_1_FN, GPSR2_1, 4819 GP_2_1_FN, GPSR2_1,
4848 GP_2_0_FN, GPSR2_0, } 4820 GP_2_0_FN, GPSR2_0, ))
4849 }, 4821 },
4850 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { 4822 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
4851 0, 0, 4823 0, 0,
4852 0, 0, 4824 0, 0,
4853 0, 0, 4825 0, 0,
@@ -4879,9 +4851,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4879 GP_3_3_FN, GPSR3_3, 4851 GP_3_3_FN, GPSR3_3,
4880 GP_3_2_FN, GPSR3_2, 4852 GP_3_2_FN, GPSR3_2,
4881 GP_3_1_FN, GPSR3_1, 4853 GP_3_1_FN, GPSR3_1,
4882 GP_3_0_FN, GPSR3_0, } 4854 GP_3_0_FN, GPSR3_0, ))
4883 }, 4855 },
4884 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { 4856 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
4885 0, 0, 4857 0, 0,
4886 0, 0, 4858 0, 0,
4887 0, 0, 4859 0, 0,
@@ -4913,9 +4885,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4913 GP_4_3_FN, GPSR4_3, 4885 GP_4_3_FN, GPSR4_3,
4914 GP_4_2_FN, GPSR4_2, 4886 GP_4_2_FN, GPSR4_2,
4915 GP_4_1_FN, GPSR4_1, 4887 GP_4_1_FN, GPSR4_1,
4916 GP_4_0_FN, GPSR4_0, } 4888 GP_4_0_FN, GPSR4_0, ))
4917 }, 4889 },
4918 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { 4890 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
4919 0, 0, 4891 0, 0,
4920 0, 0, 4892 0, 0,
4921 0, 0, 4893 0, 0,
@@ -4947,9 +4919,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4947 GP_5_3_FN, GPSR5_3, 4919 GP_5_3_FN, GPSR5_3,
4948 GP_5_2_FN, GPSR5_2, 4920 GP_5_2_FN, GPSR5_2,
4949 GP_5_1_FN, GPSR5_1, 4921 GP_5_1_FN, GPSR5_1,
4950 GP_5_0_FN, GPSR5_0, } 4922 GP_5_0_FN, GPSR5_0, ))
4951 }, 4923 },
4952 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { 4924 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
4953 GP_6_31_FN, GPSR6_31, 4925 GP_6_31_FN, GPSR6_31,
4954 GP_6_30_FN, GPSR6_30, 4926 GP_6_30_FN, GPSR6_30,
4955 GP_6_29_FN, GPSR6_29, 4927 GP_6_29_FN, GPSR6_29,
@@ -4981,9 +4953,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4981 GP_6_3_FN, GPSR6_3, 4953 GP_6_3_FN, GPSR6_3,
4982 GP_6_2_FN, GPSR6_2, 4954 GP_6_2_FN, GPSR6_2,
4983 GP_6_1_FN, GPSR6_1, 4955 GP_6_1_FN, GPSR6_1,
4984 GP_6_0_FN, GPSR6_0, } 4956 GP_6_0_FN, GPSR6_0, ))
4985 }, 4957 },
4986 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) { 4958 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
4987 0, 0, 4959 0, 0,
4988 0, 0, 4960 0, 0,
4989 0, 0, 4961 0, 0,
@@ -5015,14 +4987,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5015 GP_7_3_FN, GPSR7_3, 4987 GP_7_3_FN, GPSR7_3,
5016 GP_7_2_FN, GPSR7_2, 4988 GP_7_2_FN, GPSR7_2,
5017 GP_7_1_FN, GPSR7_1, 4989 GP_7_1_FN, GPSR7_1,
5018 GP_7_0_FN, GPSR7_0, } 4990 GP_7_0_FN, GPSR7_0, ))
5019 }, 4991 },
5020#undef F_ 4992#undef F_
5021#undef FM 4993#undef FM
5022 4994
5023#define F_(x, y) x, 4995#define F_(x, y) x,
5024#define FM(x) FN_##x, 4996#define FM(x) FN_##x,
5025 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { 4997 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5026 IP0_31_28 4998 IP0_31_28
5027 IP0_27_24 4999 IP0_27_24
5028 IP0_23_20 5000 IP0_23_20
@@ -5030,9 +5002,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5030 IP0_15_12 5002 IP0_15_12
5031 IP0_11_8 5003 IP0_11_8
5032 IP0_7_4 5004 IP0_7_4
5033 IP0_3_0 } 5005 IP0_3_0 ))
5034 }, 5006 },
5035 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { 5007 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5036 IP1_31_28 5008 IP1_31_28
5037 IP1_27_24 5009 IP1_27_24
5038 IP1_23_20 5010 IP1_23_20
@@ -5040,9 +5012,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5040 IP1_15_12 5012 IP1_15_12
5041 IP1_11_8 5013 IP1_11_8
5042 IP1_7_4 5014 IP1_7_4
5043 IP1_3_0 } 5015 IP1_3_0 ))
5044 }, 5016 },
5045 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { 5017 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5046 IP2_31_28 5018 IP2_31_28
5047 IP2_27_24 5019 IP2_27_24
5048 IP2_23_20 5020 IP2_23_20
@@ -5050,9 +5022,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5050 IP2_15_12 5022 IP2_15_12
5051 IP2_11_8 5023 IP2_11_8
5052 IP2_7_4 5024 IP2_7_4
5053 IP2_3_0 } 5025 IP2_3_0 ))
5054 }, 5026 },
5055 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { 5027 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5056 IP3_31_28 5028 IP3_31_28
5057 IP3_27_24 5029 IP3_27_24
5058 IP3_23_20 5030 IP3_23_20
@@ -5060,9 +5032,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5060 IP3_15_12 5032 IP3_15_12
5061 IP3_11_8 5033 IP3_11_8
5062 IP3_7_4 5034 IP3_7_4
5063 IP3_3_0 } 5035 IP3_3_0 ))
5064 }, 5036 },
5065 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { 5037 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5066 IP4_31_28 5038 IP4_31_28
5067 IP4_27_24 5039 IP4_27_24
5068 IP4_23_20 5040 IP4_23_20
@@ -5070,9 +5042,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5070 IP4_15_12 5042 IP4_15_12
5071 IP4_11_8 5043 IP4_11_8
5072 IP4_7_4 5044 IP4_7_4
5073 IP4_3_0 } 5045 IP4_3_0 ))
5074 }, 5046 },
5075 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { 5047 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5076 IP5_31_28 5048 IP5_31_28
5077 IP5_27_24 5049 IP5_27_24
5078 IP5_23_20 5050 IP5_23_20
@@ -5080,9 +5052,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5080 IP5_15_12 5052 IP5_15_12
5081 IP5_11_8 5053 IP5_11_8
5082 IP5_7_4 5054 IP5_7_4
5083 IP5_3_0 } 5055 IP5_3_0 ))
5084 }, 5056 },
5085 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { 5057 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5086 IP6_31_28 5058 IP6_31_28
5087 IP6_27_24 5059 IP6_27_24
5088 IP6_23_20 5060 IP6_23_20
@@ -5090,9 +5062,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5090 IP6_15_12 5062 IP6_15_12
5091 IP6_11_8 5063 IP6_11_8
5092 IP6_7_4 5064 IP6_7_4
5093 IP6_3_0 } 5065 IP6_3_0 ))
5094 }, 5066 },
5095 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { 5067 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
5096 IP7_31_28 5068 IP7_31_28
5097 IP7_27_24 5069 IP7_27_24
5098 IP7_23_20 5070 IP7_23_20
@@ -5100,9 +5072,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5100 IP7_15_12 5072 IP7_15_12
5101 IP7_11_8 5073 IP7_11_8
5102 IP7_7_4 5074 IP7_7_4
5103 IP7_3_0 } 5075 IP7_3_0 ))
5104 }, 5076 },
5105 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { 5077 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5106 IP8_31_28 5078 IP8_31_28
5107 IP8_27_24 5079 IP8_27_24
5108 IP8_23_20 5080 IP8_23_20
@@ -5110,9 +5082,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5110 IP8_15_12 5082 IP8_15_12
5111 IP8_11_8 5083 IP8_11_8
5112 IP8_7_4 5084 IP8_7_4
5113 IP8_3_0 } 5085 IP8_3_0 ))
5114 }, 5086 },
5115 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { 5087 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5116 IP9_31_28 5088 IP9_31_28
5117 IP9_27_24 5089 IP9_27_24
5118 IP9_23_20 5090 IP9_23_20
@@ -5120,9 +5092,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5120 IP9_15_12 5092 IP9_15_12
5121 IP9_11_8 5093 IP9_11_8
5122 IP9_7_4 5094 IP9_7_4
5123 IP9_3_0 } 5095 IP9_3_0 ))
5124 }, 5096 },
5125 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { 5097 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5126 IP10_31_28 5098 IP10_31_28
5127 IP10_27_24 5099 IP10_27_24
5128 IP10_23_20 5100 IP10_23_20
@@ -5130,9 +5102,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5130 IP10_15_12 5102 IP10_15_12
5131 IP10_11_8 5103 IP10_11_8
5132 IP10_7_4 5104 IP10_7_4
5133 IP10_3_0 } 5105 IP10_3_0 ))
5134 }, 5106 },
5135 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { 5107 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5136 IP11_31_28 5108 IP11_31_28
5137 IP11_27_24 5109 IP11_27_24
5138 IP11_23_20 5110 IP11_23_20
@@ -5140,9 +5112,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5140 IP11_15_12 5112 IP11_15_12
5141 IP11_11_8 5113 IP11_11_8
5142 IP11_7_4 5114 IP11_7_4
5143 IP11_3_0 } 5115 IP11_3_0 ))
5144 }, 5116 },
5145 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { 5117 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5146 IP12_31_28 5118 IP12_31_28
5147 IP12_27_24 5119 IP12_27_24
5148 IP12_23_20 5120 IP12_23_20
@@ -5150,9 +5122,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5150 IP12_15_12 5122 IP12_15_12
5151 IP12_11_8 5123 IP12_11_8
5152 IP12_7_4 5124 IP12_7_4
5153 IP12_3_0 } 5125 IP12_3_0 ))
5154 }, 5126 },
5155 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { 5127 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5156 IP13_31_28 5128 IP13_31_28
5157 IP13_27_24 5129 IP13_27_24
5158 IP13_23_20 5130 IP13_23_20
@@ -5160,9 +5132,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5160 IP13_15_12 5132 IP13_15_12
5161 IP13_11_8 5133 IP13_11_8
5162 IP13_7_4 5134 IP13_7_4
5163 IP13_3_0 } 5135 IP13_3_0 ))
5164 }, 5136 },
5165 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { 5137 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5166 IP14_31_28 5138 IP14_31_28
5167 IP14_27_24 5139 IP14_27_24
5168 IP14_23_20 5140 IP14_23_20
@@ -5170,9 +5142,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5170 IP14_15_12 5142 IP14_15_12
5171 IP14_11_8 5143 IP14_11_8
5172 IP14_7_4 5144 IP14_7_4
5173 IP14_3_0 } 5145 IP14_3_0 ))
5174 }, 5146 },
5175 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { 5147 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5176 IP15_31_28 5148 IP15_31_28
5177 IP15_27_24 5149 IP15_27_24
5178 IP15_23_20 5150 IP15_23_20
@@ -5180,9 +5152,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5180 IP15_15_12 5152 IP15_15_12
5181 IP15_11_8 5153 IP15_11_8
5182 IP15_7_4 5154 IP15_7_4
5183 IP15_3_0 } 5155 IP15_3_0 ))
5184 }, 5156 },
5185 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) { 5157 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5186 IP16_31_28 5158 IP16_31_28
5187 IP16_27_24 5159 IP16_27_24
5188 IP16_23_20 5160 IP16_23_20
@@ -5190,9 +5162,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5190 IP16_15_12 5162 IP16_15_12
5191 IP16_11_8 5163 IP16_11_8
5192 IP16_7_4 5164 IP16_7_4
5193 IP16_3_0 } 5165 IP16_3_0 ))
5194 }, 5166 },
5195 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) { 5167 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5196 /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5168 /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5197 /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5169 /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5198 /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5170 /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -5200,7 +5172,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5200 /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5172 /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5201 /* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5173 /* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5202 IP17_7_4 5174 IP17_7_4
5203 IP17_3_0 } 5175 IP17_3_0 ))
5204 }, 5176 },
5205#undef F_ 5177#undef F_
5206#undef FM 5178#undef FM
@@ -5208,8 +5180,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5208#define F_(x, y) x, 5180#define F_(x, y) x,
5209#define FM(x) FN_##x, 5181#define FM(x) FN_##x,
5210 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 5182 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5211 1, 2, 2, 3, 1, 1, 2, 1, 1, 1, 5183 GROUP(1, 2, 2, 3, 1, 1, 2, 1, 1, 1, 2, 1,
5212 2, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) { 5184 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1),
5185 GROUP(
5213 0, 0, /* RESERVED 31 */ 5186 0, 0, /* RESERVED 31 */
5214 MOD_SEL0_30_29 5187 MOD_SEL0_30_29
5215 MOD_SEL0_28_27 5188 MOD_SEL0_28_27
@@ -5232,11 +5205,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5232 MOD_SEL0_5_4 5205 MOD_SEL0_5_4
5233 MOD_SEL0_3 5206 MOD_SEL0_3
5234 MOD_SEL0_2_1 5207 MOD_SEL0_2_1
5235 0, 0, /* RESERVED 0 */ } 5208 0, 0, /* RESERVED 0 */ ))
5236 }, 5209 },
5237 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 5210 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5238 2, 3, 1, 2, 3, 1, 1, 2, 1, 5211 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5239 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { 5212 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5213 GROUP(
5240 MOD_SEL1_31_30 5214 MOD_SEL1_31_30
5241 MOD_SEL1_29_28_27 5215 MOD_SEL1_29_28_27
5242 MOD_SEL1_26 5216 MOD_SEL1_26
@@ -5259,11 +5233,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5259 MOD_SEL1_3 5233 MOD_SEL1_3
5260 MOD_SEL1_2 5234 MOD_SEL1_2
5261 MOD_SEL1_1 5235 MOD_SEL1_1
5262 MOD_SEL1_0 } 5236 MOD_SEL1_0 ))
5263 }, 5237 },
5264 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, 5238 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5265 1, 1, 1, 1, 4, 4, 4, 5239 GROUP(1, 1, 1, 1, 4, 4, 4, 4, 4, 4, 1, 2, 1),
5266 4, 4, 4, 1, 2, 1) { 5240 GROUP(
5267 MOD_SEL2_31 5241 MOD_SEL2_31
5268 MOD_SEL2_30 5242 MOD_SEL2_30
5269 MOD_SEL2_29 5243 MOD_SEL2_29
@@ -5291,7 +5265,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5291 0, 0, 5265 0, 0,
5292 /* RESERVED 2, 1 */ 5266 /* RESERVED 2, 1 */
5293 0, 0, 0, 0, 5267 0, 0, 0, 0,
5294 MOD_SEL2_0 } 5268 MOD_SEL2_0 ))
5295 }, 5269 },
5296 { }, 5270 { },
5297}; 5271};
@@ -5412,8 +5386,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5412 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ 5386 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5413 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ 5387 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5414 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ 5388 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5415 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ 5389 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5416 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */ 5390 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5417 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ 5391 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5418 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ 5392 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5419 } }, 5393 } },
@@ -5474,11 +5448,11 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5474 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ 5448 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5475 } }, 5449 } },
5476 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { 5450 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5477 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */ 5451 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
5478 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ 5452 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5479 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ 5453 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5480 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ 5454 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5481 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */ 5455 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
5482 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ 5456 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5483 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ 5457 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5484 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ 5458 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
@@ -5547,10 +5521,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5547 5521
5548enum ioctrl_regs { 5522enum ioctrl_regs {
5549 POCCTRL, 5523 POCCTRL,
5524 TDSELCTRL,
5550}; 5525};
5551 5526
5552static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 5527static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5553 [POCCTRL] = { 0xe6060380, }, 5528 [POCCTRL] = { 0xe6060380, },
5529 [TDSELCTRL] = { 0xe60603c0, },
5554 { /* sentinel */ }, 5530 { /* sentinel */ },
5555}; 5531};
5556 5532
@@ -5668,8 +5644,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5668 [25] = RCAR_GP_PIN(0, 15), /* D15 */ 5644 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5669 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ 5645 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5670 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ 5646 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
5671 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */ 5647 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
5672 [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */ 5648 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
5673 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ 5649 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
5674 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ 5650 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
5675 } }, 5651 } },
@@ -5724,11 +5700,11 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5724 [13] = RCAR_GP_PIN(5, 1), /* RX0 */ 5700 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
5725 [14] = RCAR_GP_PIN(5, 2), /* TX0 */ 5701 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
5726 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ 5702 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
5727 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N_TANS */ 5703 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
5728 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ 5704 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
5729 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ 5705 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
5730 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ 5706 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
5731 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N_TANS */ 5707 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
5732 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ 5708 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
5733 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ 5709 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
5734 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ 5710 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index db9add1405c5..68bcb8980b16 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -2,9 +2,10 @@
2/* 2/*
3 * R8A7795 ES2.0+ processor support - PFC hardware block. 3 * R8A7795 ES2.0+ processor support - PFC hardware block.
4 * 4 *
5 * Copyright (C) 2015-2017 Renesas Electronics Corporation 5 * Copyright (C) 2015-2019 Renesas Electronics Corporation
6 */ 6 */
7 7
8#include <linux/errno.h>
8#include <linux/kernel.h> 9#include <linux/kernel.h>
9#include <linux/sys_soc.h> 10#include <linux/sys_soc.h>
10 11
@@ -200,8 +201,8 @@
200#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) 201#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
201 202
202/* GPSR7 */ 203/* GPSR7 */
203#define GPSR7_3 FM(HDMI1_CEC) 204#define GPSR7_3 FM(GP7_03)
204#define GPSR7_2 FM(HDMI0_CEC) 205#define GPSR7_2 FM(GP7_02)
205#define GPSR7_1 FM(AVS2) 206#define GPSR7_1 FM(AVS2)
206#define GPSR7_0 FM(AVS1) 207#define GPSR7_0 FM(AVS1)
207 208
@@ -350,7 +351,7 @@
350#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 351#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 352#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 353#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 354#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 355#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) 356#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
356#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) 357#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
@@ -461,7 +462,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
461#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) 462#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
462#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) 463#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
463#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 464#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
464#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3) 465#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
465 466
466/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 467/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
467#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) 468#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
@@ -497,8 +498,8 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
497#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) 498#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
498#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 499#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
499#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) 500#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
500#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1) 501#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
501#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1) 502#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
502#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) 503#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
503 504
504#define PINMUX_MOD_SELS \ 505#define PINMUX_MOD_SELS \
@@ -590,8 +591,8 @@ static const u16 pinmux_data[] = {
590 PINMUX_SINGLE(AVS1), 591 PINMUX_SINGLE(AVS1),
591 PINMUX_SINGLE(AVS2), 592 PINMUX_SINGLE(AVS2),
592 PINMUX_SINGLE(CLKOUT), 593 PINMUX_SINGLE(CLKOUT),
593 PINMUX_SINGLE(HDMI0_CEC), 594 PINMUX_SINGLE(GP7_02),
594 PINMUX_SINGLE(HDMI1_CEC), 595 PINMUX_SINGLE(GP7_03),
595 PINMUX_SINGLE(MSIOF0_RXD), 596 PINMUX_SINGLE(MSIOF0_RXD),
596 PINMUX_SINGLE(MSIOF0_SCK), 597 PINMUX_SINGLE(MSIOF0_SCK),
597 PINMUX_SINGLE(MSIOF0_TXD), 598 PINMUX_SINGLE(MSIOF0_TXD),
@@ -1129,7 +1130,7 @@ static const u16 pinmux_data[] = {
1129 PINMUX_IPSR_GPSR(IP11_27_24, SCK0), 1130 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1130 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), 1131 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1131 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), 1132 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1132 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1), 1133 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
1133 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), 1134 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1134 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), 1135 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1135 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), 1136 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
@@ -1162,7 +1163,7 @@ static const u16 pinmux_data[] = {
1162 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), 1163 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1163 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), 1164 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1164 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), 1165 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1165 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), 1166 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
1166 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), 1167 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1167 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), 1168 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1168 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), 1169 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
@@ -1221,7 +1222,7 @@ static const u16 pinmux_data[] = {
1221 1222
1222 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), 1223 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1223 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), 1224 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1224 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0), 1225 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
1225 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), 1226 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1226 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), 1227 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1227 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), 1228 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
@@ -1268,7 +1269,7 @@ static const u16 pinmux_data[] = {
1268 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), 1269 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1269 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), 1270 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1270 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A), 1271 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
1271 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), 1272 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
1272 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), 1273 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1273 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), 1274 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1274 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), 1275 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
@@ -1277,7 +1278,7 @@ static const u16 pinmux_data[] = {
1277 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), 1278 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1278 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), 1279 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1279 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), 1280 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1280 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0), 1281 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
1281 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), 1282 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1282 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), 1283 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1283 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), 1284 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
@@ -1408,10 +1409,9 @@ static const u16 pinmux_data[] = {
1408 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), 1409 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1409 1410
1410 /* IPSR17 */ 1411 /* IPSR17 */
1411 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), 1412 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
1412 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1413 1413
1414 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), 1414 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
1415 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), 1415 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1416 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), 1416 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1417 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), 1417 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
@@ -2131,22 +2131,6 @@ static const unsigned int du_disp_mux[] = {
2131 DU_DISP_MARK, 2131 DU_DISP_MARK,
2132}; 2132};
2133 2133
2134/* - HDMI ------------------------------------------------------------------- */
2135static const unsigned int hdmi0_cec_pins[] = {
2136 /* HDMI0_CEC */
2137 RCAR_GP_PIN(7, 2),
2138};
2139static const unsigned int hdmi0_cec_mux[] = {
2140 HDMI0_CEC_MARK,
2141};
2142static const unsigned int hdmi1_cec_pins[] = {
2143 /* HDMI1_CEC */
2144 RCAR_GP_PIN(7, 3),
2145};
2146static const unsigned int hdmi1_cec_mux[] = {
2147 HDMI1_CEC_MARK,
2148};
2149
2150/* - HSCIF0 ----------------------------------------------------------------- */ 2134/* - HSCIF0 ----------------------------------------------------------------- */
2151static const unsigned int hscif0_data_pins[] = { 2135static const unsigned int hscif0_data_pins[] = {
2152 /* RX, TX */ 2136 /* RX, TX */
@@ -4225,8 +4209,6 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
4225 SH_PFC_PIN_GROUP(du_oddf), 4209 SH_PFC_PIN_GROUP(du_oddf),
4226 SH_PFC_PIN_GROUP(du_cde), 4210 SH_PFC_PIN_GROUP(du_cde),
4227 SH_PFC_PIN_GROUP(du_disp), 4211 SH_PFC_PIN_GROUP(du_disp),
4228 SH_PFC_PIN_GROUP(hdmi0_cec),
4229 SH_PFC_PIN_GROUP(hdmi1_cec),
4230 SH_PFC_PIN_GROUP(hscif0_data), 4212 SH_PFC_PIN_GROUP(hscif0_data),
4231 SH_PFC_PIN_GROUP(hscif0_clk), 4213 SH_PFC_PIN_GROUP(hscif0_clk),
4232 SH_PFC_PIN_GROUP(hscif0_ctrl), 4214 SH_PFC_PIN_GROUP(hscif0_ctrl),
@@ -4611,14 +4593,6 @@ static const char * const du_groups[] = {
4611 "du_disp", 4593 "du_disp",
4612}; 4594};
4613 4595
4614static const char * const hdmi0_groups[] = {
4615 "hdmi0_cec",
4616};
4617
4618static const char * const hdmi1_groups[] = {
4619 "hdmi1_cec",
4620};
4621
4622static const char * const hscif0_groups[] = { 4596static const char * const hscif0_groups[] = {
4623 "hscif0_data", 4597 "hscif0_data",
4624 "hscif0_clk", 4598 "hscif0_clk",
@@ -5037,8 +5011,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
5037 SH_PFC_FUNCTION(drif2), 5011 SH_PFC_FUNCTION(drif2),
5038 SH_PFC_FUNCTION(drif3), 5012 SH_PFC_FUNCTION(drif3),
5039 SH_PFC_FUNCTION(du), 5013 SH_PFC_FUNCTION(du),
5040 SH_PFC_FUNCTION(hdmi0),
5041 SH_PFC_FUNCTION(hdmi1),
5042 SH_PFC_FUNCTION(hscif0), 5014 SH_PFC_FUNCTION(hscif0),
5043 SH_PFC_FUNCTION(hscif1), 5015 SH_PFC_FUNCTION(hscif1),
5044 SH_PFC_FUNCTION(hscif2), 5016 SH_PFC_FUNCTION(hscif2),
@@ -5088,7 +5060,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
5088static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5060static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5089#define F_(x, y) FN_##y 5061#define F_(x, y) FN_##y
5090#define FM(x) FN_##x 5062#define FM(x) FN_##x
5091 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { 5063 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
5092 0, 0, 5064 0, 0,
5093 0, 0, 5065 0, 0,
5094 0, 0, 5066 0, 0,
@@ -5120,9 +5092,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5120 GP_0_3_FN, GPSR0_3, 5092 GP_0_3_FN, GPSR0_3,
5121 GP_0_2_FN, GPSR0_2, 5093 GP_0_2_FN, GPSR0_2,
5122 GP_0_1_FN, GPSR0_1, 5094 GP_0_1_FN, GPSR0_1,
5123 GP_0_0_FN, GPSR0_0, } 5095 GP_0_0_FN, GPSR0_0, ))
5124 }, 5096 },
5125 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { 5097 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5126 0, 0, 5098 0, 0,
5127 0, 0, 5099 0, 0,
5128 0, 0, 5100 0, 0,
@@ -5154,9 +5126,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5154 GP_1_3_FN, GPSR1_3, 5126 GP_1_3_FN, GPSR1_3,
5155 GP_1_2_FN, GPSR1_2, 5127 GP_1_2_FN, GPSR1_2,
5156 GP_1_1_FN, GPSR1_1, 5128 GP_1_1_FN, GPSR1_1,
5157 GP_1_0_FN, GPSR1_0, } 5129 GP_1_0_FN, GPSR1_0, ))
5158 }, 5130 },
5159 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { 5131 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
5160 0, 0, 5132 0, 0,
5161 0, 0, 5133 0, 0,
5162 0, 0, 5134 0, 0,
@@ -5188,9 +5160,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5188 GP_2_3_FN, GPSR2_3, 5160 GP_2_3_FN, GPSR2_3,
5189 GP_2_2_FN, GPSR2_2, 5161 GP_2_2_FN, GPSR2_2,
5190 GP_2_1_FN, GPSR2_1, 5162 GP_2_1_FN, GPSR2_1,
5191 GP_2_0_FN, GPSR2_0, } 5163 GP_2_0_FN, GPSR2_0, ))
5192 }, 5164 },
5193 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { 5165 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
5194 0, 0, 5166 0, 0,
5195 0, 0, 5167 0, 0,
5196 0, 0, 5168 0, 0,
@@ -5222,9 +5194,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5222 GP_3_3_FN, GPSR3_3, 5194 GP_3_3_FN, GPSR3_3,
5223 GP_3_2_FN, GPSR3_2, 5195 GP_3_2_FN, GPSR3_2,
5224 GP_3_1_FN, GPSR3_1, 5196 GP_3_1_FN, GPSR3_1,
5225 GP_3_0_FN, GPSR3_0, } 5197 GP_3_0_FN, GPSR3_0, ))
5226 }, 5198 },
5227 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { 5199 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
5228 0, 0, 5200 0, 0,
5229 0, 0, 5201 0, 0,
5230 0, 0, 5202 0, 0,
@@ -5256,9 +5228,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5256 GP_4_3_FN, GPSR4_3, 5228 GP_4_3_FN, GPSR4_3,
5257 GP_4_2_FN, GPSR4_2, 5229 GP_4_2_FN, GPSR4_2,
5258 GP_4_1_FN, GPSR4_1, 5230 GP_4_1_FN, GPSR4_1,
5259 GP_4_0_FN, GPSR4_0, } 5231 GP_4_0_FN, GPSR4_0, ))
5260 }, 5232 },
5261 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { 5233 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5262 0, 0, 5234 0, 0,
5263 0, 0, 5235 0, 0,
5264 0, 0, 5236 0, 0,
@@ -5290,9 +5262,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5290 GP_5_3_FN, GPSR5_3, 5262 GP_5_3_FN, GPSR5_3,
5291 GP_5_2_FN, GPSR5_2, 5263 GP_5_2_FN, GPSR5_2,
5292 GP_5_1_FN, GPSR5_1, 5264 GP_5_1_FN, GPSR5_1,
5293 GP_5_0_FN, GPSR5_0, } 5265 GP_5_0_FN, GPSR5_0, ))
5294 }, 5266 },
5295 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { 5267 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5296 GP_6_31_FN, GPSR6_31, 5268 GP_6_31_FN, GPSR6_31,
5297 GP_6_30_FN, GPSR6_30, 5269 GP_6_30_FN, GPSR6_30,
5298 GP_6_29_FN, GPSR6_29, 5270 GP_6_29_FN, GPSR6_29,
@@ -5324,9 +5296,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5324 GP_6_3_FN, GPSR6_3, 5296 GP_6_3_FN, GPSR6_3,
5325 GP_6_2_FN, GPSR6_2, 5297 GP_6_2_FN, GPSR6_2,
5326 GP_6_1_FN, GPSR6_1, 5298 GP_6_1_FN, GPSR6_1,
5327 GP_6_0_FN, GPSR6_0, } 5299 GP_6_0_FN, GPSR6_0, ))
5328 }, 5300 },
5329 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) { 5301 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
5330 0, 0, 5302 0, 0,
5331 0, 0, 5303 0, 0,
5332 0, 0, 5304 0, 0,
@@ -5358,14 +5330,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5358 GP_7_3_FN, GPSR7_3, 5330 GP_7_3_FN, GPSR7_3,
5359 GP_7_2_FN, GPSR7_2, 5331 GP_7_2_FN, GPSR7_2,
5360 GP_7_1_FN, GPSR7_1, 5332 GP_7_1_FN, GPSR7_1,
5361 GP_7_0_FN, GPSR7_0, } 5333 GP_7_0_FN, GPSR7_0, ))
5362 }, 5334 },
5363#undef F_ 5335#undef F_
5364#undef FM 5336#undef FM
5365 5337
5366#define F_(x, y) x, 5338#define F_(x, y) x,
5367#define FM(x) FN_##x, 5339#define FM(x) FN_##x,
5368 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { 5340 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5369 IP0_31_28 5341 IP0_31_28
5370 IP0_27_24 5342 IP0_27_24
5371 IP0_23_20 5343 IP0_23_20
@@ -5373,9 +5345,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5373 IP0_15_12 5345 IP0_15_12
5374 IP0_11_8 5346 IP0_11_8
5375 IP0_7_4 5347 IP0_7_4
5376 IP0_3_0 } 5348 IP0_3_0 ))
5377 }, 5349 },
5378 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { 5350 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5379 IP1_31_28 5351 IP1_31_28
5380 IP1_27_24 5352 IP1_27_24
5381 IP1_23_20 5353 IP1_23_20
@@ -5383,9 +5355,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5383 IP1_15_12 5355 IP1_15_12
5384 IP1_11_8 5356 IP1_11_8
5385 IP1_7_4 5357 IP1_7_4
5386 IP1_3_0 } 5358 IP1_3_0 ))
5387 }, 5359 },
5388 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { 5360 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5389 IP2_31_28 5361 IP2_31_28
5390 IP2_27_24 5362 IP2_27_24
5391 IP2_23_20 5363 IP2_23_20
@@ -5393,9 +5365,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5393 IP2_15_12 5365 IP2_15_12
5394 IP2_11_8 5366 IP2_11_8
5395 IP2_7_4 5367 IP2_7_4
5396 IP2_3_0 } 5368 IP2_3_0 ))
5397 }, 5369 },
5398 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { 5370 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5399 IP3_31_28 5371 IP3_31_28
5400 IP3_27_24 5372 IP3_27_24
5401 IP3_23_20 5373 IP3_23_20
@@ -5403,9 +5375,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5403 IP3_15_12 5375 IP3_15_12
5404 IP3_11_8 5376 IP3_11_8
5405 IP3_7_4 5377 IP3_7_4
5406 IP3_3_0 } 5378 IP3_3_0 ))
5407 }, 5379 },
5408 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { 5380 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5409 IP4_31_28 5381 IP4_31_28
5410 IP4_27_24 5382 IP4_27_24
5411 IP4_23_20 5383 IP4_23_20
@@ -5413,9 +5385,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5413 IP4_15_12 5385 IP4_15_12
5414 IP4_11_8 5386 IP4_11_8
5415 IP4_7_4 5387 IP4_7_4
5416 IP4_3_0 } 5388 IP4_3_0 ))
5417 }, 5389 },
5418 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { 5390 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5419 IP5_31_28 5391 IP5_31_28
5420 IP5_27_24 5392 IP5_27_24
5421 IP5_23_20 5393 IP5_23_20
@@ -5423,9 +5395,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5423 IP5_15_12 5395 IP5_15_12
5424 IP5_11_8 5396 IP5_11_8
5425 IP5_7_4 5397 IP5_7_4
5426 IP5_3_0 } 5398 IP5_3_0 ))
5427 }, 5399 },
5428 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { 5400 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5429 IP6_31_28 5401 IP6_31_28
5430 IP6_27_24 5402 IP6_27_24
5431 IP6_23_20 5403 IP6_23_20
@@ -5433,9 +5405,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5433 IP6_15_12 5405 IP6_15_12
5434 IP6_11_8 5406 IP6_11_8
5435 IP6_7_4 5407 IP6_7_4
5436 IP6_3_0 } 5408 IP6_3_0 ))
5437 }, 5409 },
5438 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { 5410 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
5439 IP7_31_28 5411 IP7_31_28
5440 IP7_27_24 5412 IP7_27_24
5441 IP7_23_20 5413 IP7_23_20
@@ -5443,9 +5415,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5443 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5415 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5444 IP7_11_8 5416 IP7_11_8
5445 IP7_7_4 5417 IP7_7_4
5446 IP7_3_0 } 5418 IP7_3_0 ))
5447 }, 5419 },
5448 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { 5420 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5449 IP8_31_28 5421 IP8_31_28
5450 IP8_27_24 5422 IP8_27_24
5451 IP8_23_20 5423 IP8_23_20
@@ -5453,9 +5425,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5453 IP8_15_12 5425 IP8_15_12
5454 IP8_11_8 5426 IP8_11_8
5455 IP8_7_4 5427 IP8_7_4
5456 IP8_3_0 } 5428 IP8_3_0 ))
5457 }, 5429 },
5458 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { 5430 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5459 IP9_31_28 5431 IP9_31_28
5460 IP9_27_24 5432 IP9_27_24
5461 IP9_23_20 5433 IP9_23_20
@@ -5463,9 +5435,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5463 IP9_15_12 5435 IP9_15_12
5464 IP9_11_8 5436 IP9_11_8
5465 IP9_7_4 5437 IP9_7_4
5466 IP9_3_0 } 5438 IP9_3_0 ))
5467 }, 5439 },
5468 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { 5440 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5469 IP10_31_28 5441 IP10_31_28
5470 IP10_27_24 5442 IP10_27_24
5471 IP10_23_20 5443 IP10_23_20
@@ -5473,9 +5445,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5473 IP10_15_12 5445 IP10_15_12
5474 IP10_11_8 5446 IP10_11_8
5475 IP10_7_4 5447 IP10_7_4
5476 IP10_3_0 } 5448 IP10_3_0 ))
5477 }, 5449 },
5478 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { 5450 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5479 IP11_31_28 5451 IP11_31_28
5480 IP11_27_24 5452 IP11_27_24
5481 IP11_23_20 5453 IP11_23_20
@@ -5483,9 +5455,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5483 IP11_15_12 5455 IP11_15_12
5484 IP11_11_8 5456 IP11_11_8
5485 IP11_7_4 5457 IP11_7_4
5486 IP11_3_0 } 5458 IP11_3_0 ))
5487 }, 5459 },
5488 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { 5460 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5489 IP12_31_28 5461 IP12_31_28
5490 IP12_27_24 5462 IP12_27_24
5491 IP12_23_20 5463 IP12_23_20
@@ -5493,9 +5465,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5493 IP12_15_12 5465 IP12_15_12
5494 IP12_11_8 5466 IP12_11_8
5495 IP12_7_4 5467 IP12_7_4
5496 IP12_3_0 } 5468 IP12_3_0 ))
5497 }, 5469 },
5498 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { 5470 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5499 IP13_31_28 5471 IP13_31_28
5500 IP13_27_24 5472 IP13_27_24
5501 IP13_23_20 5473 IP13_23_20
@@ -5503,9 +5475,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5503 IP13_15_12 5475 IP13_15_12
5504 IP13_11_8 5476 IP13_11_8
5505 IP13_7_4 5477 IP13_7_4
5506 IP13_3_0 } 5478 IP13_3_0 ))
5507 }, 5479 },
5508 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { 5480 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5509 IP14_31_28 5481 IP14_31_28
5510 IP14_27_24 5482 IP14_27_24
5511 IP14_23_20 5483 IP14_23_20
@@ -5513,9 +5485,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5513 IP14_15_12 5485 IP14_15_12
5514 IP14_11_8 5486 IP14_11_8
5515 IP14_7_4 5487 IP14_7_4
5516 IP14_3_0 } 5488 IP14_3_0 ))
5517 }, 5489 },
5518 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { 5490 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5519 IP15_31_28 5491 IP15_31_28
5520 IP15_27_24 5492 IP15_27_24
5521 IP15_23_20 5493 IP15_23_20
@@ -5523,9 +5495,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5523 IP15_15_12 5495 IP15_15_12
5524 IP15_11_8 5496 IP15_11_8
5525 IP15_7_4 5497 IP15_7_4
5526 IP15_3_0 } 5498 IP15_3_0 ))
5527 }, 5499 },
5528 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) { 5500 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5529 IP16_31_28 5501 IP16_31_28
5530 IP16_27_24 5502 IP16_27_24
5531 IP16_23_20 5503 IP16_23_20
@@ -5533,9 +5505,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5533 IP16_15_12 5505 IP16_15_12
5534 IP16_11_8 5506 IP16_11_8
5535 IP16_7_4 5507 IP16_7_4
5536 IP16_3_0 } 5508 IP16_3_0 ))
5537 }, 5509 },
5538 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) { 5510 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5539 IP17_31_28 5511 IP17_31_28
5540 IP17_27_24 5512 IP17_27_24
5541 IP17_23_20 5513 IP17_23_20
@@ -5543,9 +5515,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5543 IP17_15_12 5515 IP17_15_12
5544 IP17_11_8 5516 IP17_11_8
5545 IP17_7_4 5517 IP17_7_4
5546 IP17_3_0 } 5518 IP17_3_0 ))
5547 }, 5519 },
5548 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) { 5520 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
5549 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5521 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5550 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5522 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5551 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5523 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -5553,7 +5525,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5553 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5525 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5554 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5526 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5555 IP18_7_4 5527 IP18_7_4
5556 IP18_3_0 } 5528 IP18_3_0 ))
5557 }, 5529 },
5558#undef F_ 5530#undef F_
5559#undef FM 5531#undef FM
@@ -5561,8 +5533,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5561#define F_(x, y) x, 5533#define F_(x, y) x,
5562#define FM(x) FN_##x, 5534#define FM(x) FN_##x,
5563 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 5535 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5564 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 5536 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5565 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) { 5537 1, 1, 1, 2, 2, 1, 2, 3),
5538 GROUP(
5566 MOD_SEL0_31_30_29 5539 MOD_SEL0_31_30_29
5567 MOD_SEL0_28_27 5540 MOD_SEL0_28_27
5568 MOD_SEL0_26_25_24 5541 MOD_SEL0_26_25_24
@@ -5583,11 +5556,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5583 MOD_SEL0_5 5556 MOD_SEL0_5
5584 MOD_SEL0_4_3 5557 MOD_SEL0_4_3
5585 /* RESERVED 2, 1, 0 */ 5558 /* RESERVED 2, 1, 0 */
5586 0, 0, 0, 0, 0, 0, 0, 0 } 5559 0, 0, 0, 0, 0, 0, 0, 0 ))
5587 }, 5560 },
5588 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 5561 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5589 2, 3, 1, 2, 3, 1, 1, 2, 1, 5562 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5590 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { 5563 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5564 GROUP(
5591 MOD_SEL1_31_30 5565 MOD_SEL1_31_30
5592 MOD_SEL1_29_28_27 5566 MOD_SEL1_29_28_27
5593 MOD_SEL1_26 5567 MOD_SEL1_26
@@ -5610,11 +5584,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5610 MOD_SEL1_3 5584 MOD_SEL1_3
5611 MOD_SEL1_2 5585 MOD_SEL1_2
5612 MOD_SEL1_1 5586 MOD_SEL1_1
5613 MOD_SEL1_0 } 5587 MOD_SEL1_0 ))
5614 }, 5588 },
5615 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, 5589 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5616 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, 5590 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5617 4, 4, 4, 3, 1) { 5591 1, 4, 4, 4, 3, 1),
5592 GROUP(
5618 MOD_SEL2_31 5593 MOD_SEL2_31
5619 MOD_SEL2_30 5594 MOD_SEL2_30
5620 MOD_SEL2_29 5595 MOD_SEL2_29
@@ -5641,7 +5616,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5641 0, 0, 0, 0, 0, 0, 0, 0, 5616 0, 0, 0, 0, 0, 0, 0, 0,
5642 /* RESERVED 3, 2, 1 */ 5617 /* RESERVED 3, 2, 1 */
5643 0, 0, 0, 0, 0, 0, 0, 0, 5618 0, 0, 0, 0, 0, 0, 0, 0,
5644 MOD_SEL2_0 } 5619 MOD_SEL2_0 ))
5645 }, 5620 },
5646 { }, 5621 { },
5647}; 5622};
@@ -5762,8 +5737,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5762 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ 5737 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5763 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ 5738 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5764 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ 5739 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5765 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ 5740 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5766 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */ 5741 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5767 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ 5742 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5768 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ 5743 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5769 } }, 5744 } },
@@ -5897,10 +5872,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5897 5872
5898enum ioctrl_regs { 5873enum ioctrl_regs {
5899 POCCTRL, 5874 POCCTRL,
5875 TDSELCTRL,
5900}; 5876};
5901 5877
5902static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 5878static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5903 [POCCTRL] = { 0xe6060380, }, 5879 [POCCTRL] = { 0xe6060380, },
5880 [TDSELCTRL] = { 0xe60603c0, },
5904 { /* sentinel */ }, 5881 { /* sentinel */ },
5905}; 5882};
5906 5883
@@ -6017,8 +5994,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
6017 [25] = RCAR_GP_PIN(0, 15), /* D15 */ 5994 [25] = RCAR_GP_PIN(0, 15), /* D15 */
6018 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ 5995 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
6019 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ 5996 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
6020 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */ 5997 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
6021 [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */ 5998 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
6022 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ 5999 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
6023 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ 6000 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
6024 } }, 6001 } },
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 72348a4f2ece..38cce690db70 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -2,7 +2,7 @@
2/* 2/*
3 * R8A7796 processor support - PFC hardware block. 3 * R8A7796 processor support - PFC hardware block.
4 * 4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 5 * Copyright (C) 2016-2019 Renesas Electronics Corp.
6 * 6 *
7 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c 7 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
8 * 8 *
@@ -11,6 +11,7 @@
11 * Copyright (C) 2015 Renesas Electronics Corporation 11 * Copyright (C) 2015 Renesas Electronics Corporation
12 */ 12 */
13 13
14#include <linux/errno.h>
14#include <linux/kernel.h> 15#include <linux/kernel.h>
15 16
16#include "core.h" 17#include "core.h"
@@ -206,7 +207,7 @@
206 207
207/* GPSR7 */ 208/* GPSR7 */
208#define GPSR7_3 FM(GP7_03) 209#define GPSR7_3 FM(GP7_03)
209#define GPSR7_2 FM(HDMI0_CEC) 210#define GPSR7_2 FM(GP7_02)
210#define GPSR7_1 FM(AVS2) 211#define GPSR7_1 FM(AVS2)
211#define GPSR7_0 FM(AVS1) 212#define GPSR7_0 FM(AVS1)
212 213
@@ -355,7 +356,7 @@
355#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 356#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 357#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 358#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 359#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 360#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) 361#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
361#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) 362#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
@@ -466,7 +467,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
466#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) 467#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
467#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) 468#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
468#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 469#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
469#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3) 470#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
470 471
471/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 472/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
472#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) 473#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
@@ -499,12 +500,12 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
499#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) 500#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
500#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) 501#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
501#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 502#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
502#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1) 503#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
503#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) 504#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
504#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 505#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
505#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) 506#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
506#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1) 507#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
507#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1) 508#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
508#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) 509#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
509 510
510#define PINMUX_MOD_SELS \ 511#define PINMUX_MOD_SELS \
@@ -597,7 +598,7 @@ static const u16 pinmux_data[] = {
597 PINMUX_SINGLE(AVS2), 598 PINMUX_SINGLE(AVS2),
598 PINMUX_SINGLE(CLKOUT), 599 PINMUX_SINGLE(CLKOUT),
599 PINMUX_SINGLE(GP7_03), 600 PINMUX_SINGLE(GP7_03),
600 PINMUX_SINGLE(HDMI0_CEC), 601 PINMUX_SINGLE(GP7_02),
601 PINMUX_SINGLE(MSIOF0_RXD), 602 PINMUX_SINGLE(MSIOF0_RXD),
602 PINMUX_SINGLE(MSIOF0_SCK), 603 PINMUX_SINGLE(MSIOF0_SCK),
603 PINMUX_SINGLE(MSIOF0_TXD), 604 PINMUX_SINGLE(MSIOF0_TXD),
@@ -1021,35 +1022,35 @@ static const u16 pinmux_data[] = {
1021 1022
1022 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), 1023 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1023 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), 1024 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1024 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1), 1025 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
1025 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), 1026 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1026 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), 1027 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1027 1028
1028 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), 1029 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1029 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), 1030 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1030 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), 1031 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1031 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1), 1032 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
1032 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), 1033 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1033 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), 1034 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1034 1035
1035 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), 1036 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1036 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), 1037 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1037 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), 1038 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1038 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1), 1039 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
1039 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), 1040 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1040 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), 1041 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1041 1042
1042 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), 1043 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1043 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), 1044 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1044 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), 1045 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1045 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1), 1046 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
1046 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), 1047 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1047 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), 1048 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1048 1049
1049 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), 1050 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1050 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), 1051 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1051 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), 1052 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1052 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1), 1053 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
1053 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), 1054 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1054 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), 1055 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1055 1056
@@ -1115,28 +1116,28 @@ static const u16 pinmux_data[] = {
1115 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), 1116 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1116 1117
1117 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), 1118 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1118 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0), 1119 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
1119 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), 1120 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1120 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), 1121 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1121 1122
1122 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), 1123 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1123 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0), 1124 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
1124 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), 1125 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1125 1126
1126 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), 1127 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1127 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDFC_0), 1128 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
1128 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1129 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1129 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), 1130 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
1130 1131
1131 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), 1132 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1132 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDFC_0), 1133 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
1133 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), 1134 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1134 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), 1135 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
1135 1136
1136 PINMUX_IPSR_GPSR(IP11_27_24, SCK0), 1137 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1137 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), 1138 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1138 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), 1139 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1139 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1), 1140 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
1140 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), 1141 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1141 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), 1142 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1142 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), 1143 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
@@ -1169,7 +1170,7 @@ static const u16 pinmux_data[] = {
1169 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), 1170 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1170 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), 1171 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1171 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), 1172 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1172 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), 1173 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
1173 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), 1174 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1174 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), 1175 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1175 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), 1176 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
@@ -1228,7 +1229,7 @@ static const u16 pinmux_data[] = {
1228 1229
1229 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), 1230 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1230 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), 1231 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1231 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0), 1232 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
1232 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), 1233 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1233 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), 1234 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1234 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), 1235 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
@@ -1274,8 +1275,8 @@ static const u16 pinmux_data[] = {
1274 /* IPSR14 */ 1275 /* IPSR14 */
1275 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), 1276 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1276 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), 1277 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1277 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0), 1278 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1278 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), 1279 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
1279 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), 1280 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1280 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), 1281 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1281 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), 1282 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
@@ -1284,7 +1285,7 @@ static const u16 pinmux_data[] = {
1284 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), 1285 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1285 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), 1286 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1286 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), 1287 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1287 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0), 1288 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
1288 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), 1289 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1289 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), 1290 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1290 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), 1291 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
@@ -1412,10 +1413,9 @@ static const u16 pinmux_data[] = {
1412 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), 1413 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1413 1414
1414 /* IPSR17 */ 1415 /* IPSR17 */
1415 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), 1416 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
1416 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1417 1417
1418 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), 1418 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
1419 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), 1419 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1420 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), 1420 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1421 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), 1421 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
@@ -1499,11 +1499,6 @@ static const u16 pinmux_data[] = {
1499 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), 1499 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1500 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), 1500 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1501 1501
1502 /* I2C */
1503 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1504 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1505 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
1506
1507/* 1502/*
1508 * Static pins can not be muxed between different functions but 1503 * Static pins can not be muxed between different functions but
1509 * still need mark entries in the pinmux list. Add each static 1504 * still need mark entries in the pinmux list. Add each static
@@ -2140,15 +2135,6 @@ static const unsigned int du_disp_mux[] = {
2140 DU_DISP_MARK, 2135 DU_DISP_MARK,
2141}; 2136};
2142 2137
2143/* - HDMI ------------------------------------------------------------------- */
2144static const unsigned int hdmi0_cec_pins[] = {
2145 /* HDMI0_CEC */
2146 RCAR_GP_PIN(7, 2),
2147};
2148static const unsigned int hdmi0_cec_mux[] = {
2149 HDMI0_CEC_MARK,
2150};
2151
2152/* - HSCIF0 ----------------------------------------------------------------- */ 2138/* - HSCIF0 ----------------------------------------------------------------- */
2153static const unsigned int hscif0_data_pins[] = { 2139static const unsigned int hscif0_data_pins[] = {
2154 /* RX, TX */ 2140 /* RX, TX */
@@ -4124,8 +4110,8 @@ static const unsigned int vin5_clk_mux[] = {
4124}; 4110};
4125 4111
4126static const struct { 4112static const struct {
4127 struct sh_pfc_pin_group common[310]; 4113 struct sh_pfc_pin_group common[312];
4128 struct sh_pfc_pin_group automotive[33]; 4114 struct sh_pfc_pin_group automotive[30];
4129} pinmux_groups = { 4115} pinmux_groups = {
4130 .common = { 4116 .common = {
4131 SH_PFC_PIN_GROUP(audio_clk_a_a), 4117 SH_PFC_PIN_GROUP(audio_clk_a_a),
@@ -4160,6 +4146,9 @@ static const struct {
4160 SH_PFC_PIN_GROUP(can0_data_b), 4146 SH_PFC_PIN_GROUP(can0_data_b),
4161 SH_PFC_PIN_GROUP(can1_data), 4147 SH_PFC_PIN_GROUP(can1_data),
4162 SH_PFC_PIN_GROUP(can_clk), 4148 SH_PFC_PIN_GROUP(can_clk),
4149 SH_PFC_PIN_GROUP(canfd0_data_a),
4150 SH_PFC_PIN_GROUP(canfd0_data_b),
4151 SH_PFC_PIN_GROUP(canfd1_data),
4163 SH_PFC_PIN_GROUP(du_rgb666), 4152 SH_PFC_PIN_GROUP(du_rgb666),
4164 SH_PFC_PIN_GROUP(du_rgb888), 4153 SH_PFC_PIN_GROUP(du_rgb888),
4165 SH_PFC_PIN_GROUP(du_clk_out_0), 4154 SH_PFC_PIN_GROUP(du_clk_out_0),
@@ -4168,7 +4157,6 @@ static const struct {
4168 SH_PFC_PIN_GROUP(du_oddf), 4157 SH_PFC_PIN_GROUP(du_oddf),
4169 SH_PFC_PIN_GROUP(du_cde), 4158 SH_PFC_PIN_GROUP(du_cde),
4170 SH_PFC_PIN_GROUP(du_disp), 4159 SH_PFC_PIN_GROUP(du_disp),
4171 SH_PFC_PIN_GROUP(hdmi0_cec),
4172 SH_PFC_PIN_GROUP(hscif0_data), 4160 SH_PFC_PIN_GROUP(hscif0_data),
4173 SH_PFC_PIN_GROUP(hscif0_clk), 4161 SH_PFC_PIN_GROUP(hscif0_clk),
4174 SH_PFC_PIN_GROUP(hscif0_ctrl), 4162 SH_PFC_PIN_GROUP(hscif0_ctrl),
@@ -4440,9 +4428,6 @@ static const struct {
4440 SH_PFC_PIN_GROUP(vin5_clk), 4428 SH_PFC_PIN_GROUP(vin5_clk),
4441 }, 4429 },
4442 .automotive = { 4430 .automotive = {
4443 SH_PFC_PIN_GROUP(canfd0_data_a),
4444 SH_PFC_PIN_GROUP(canfd0_data_b),
4445 SH_PFC_PIN_GROUP(canfd1_data),
4446 SH_PFC_PIN_GROUP(drif0_ctrl_a), 4431 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4447 SH_PFC_PIN_GROUP(drif0_data0_a), 4432 SH_PFC_PIN_GROUP(drif0_data0_a),
4448 SH_PFC_PIN_GROUP(drif0_data1_a), 4433 SH_PFC_PIN_GROUP(drif0_data1_a),
@@ -4585,10 +4570,6 @@ static const char * const du_groups[] = {
4585 "du_disp", 4570 "du_disp",
4586}; 4571};
4587 4572
4588static const char * const hdmi0_groups[] = {
4589 "hdmi0_cec",
4590};
4591
4592static const char * const hscif0_groups[] = { 4573static const char * const hscif0_groups[] = {
4593 "hscif0_data", 4574 "hscif0_data",
4594 "hscif0_clk", 4575 "hscif0_clk",
@@ -4982,8 +4963,8 @@ static const char * const vin5_groups[] = {
4982}; 4963};
4983 4964
4984static const struct { 4965static const struct {
4985 struct sh_pfc_function common[48]; 4966 struct sh_pfc_function common[49];
4986 struct sh_pfc_function automotive[6]; 4967 struct sh_pfc_function automotive[4];
4987} pinmux_functions = { 4968} pinmux_functions = {
4988 .common = { 4969 .common = {
4989 SH_PFC_FUNCTION(audio_clk), 4970 SH_PFC_FUNCTION(audio_clk),
@@ -4991,8 +4972,9 @@ static const struct {
4991 SH_PFC_FUNCTION(can0), 4972 SH_PFC_FUNCTION(can0),
4992 SH_PFC_FUNCTION(can1), 4973 SH_PFC_FUNCTION(can1),
4993 SH_PFC_FUNCTION(can_clk), 4974 SH_PFC_FUNCTION(can_clk),
4975 SH_PFC_FUNCTION(canfd0),
4976 SH_PFC_FUNCTION(canfd1),
4994 SH_PFC_FUNCTION(du), 4977 SH_PFC_FUNCTION(du),
4995 SH_PFC_FUNCTION(hdmi0),
4996 SH_PFC_FUNCTION(hscif0), 4978 SH_PFC_FUNCTION(hscif0),
4997 SH_PFC_FUNCTION(hscif1), 4979 SH_PFC_FUNCTION(hscif1),
4998 SH_PFC_FUNCTION(hscif2), 4980 SH_PFC_FUNCTION(hscif2),
@@ -5036,8 +5018,6 @@ static const struct {
5036 SH_PFC_FUNCTION(vin5), 5018 SH_PFC_FUNCTION(vin5),
5037 }, 5019 },
5038 .automotive = { 5020 .automotive = {
5039 SH_PFC_FUNCTION(canfd0),
5040 SH_PFC_FUNCTION(canfd1),
5041 SH_PFC_FUNCTION(drif0), 5021 SH_PFC_FUNCTION(drif0),
5042 SH_PFC_FUNCTION(drif1), 5022 SH_PFC_FUNCTION(drif1),
5043 SH_PFC_FUNCTION(drif2), 5023 SH_PFC_FUNCTION(drif2),
@@ -5048,7 +5028,7 @@ static const struct {
5048static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5028static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5049#define F_(x, y) FN_##y 5029#define F_(x, y) FN_##y
5050#define FM(x) FN_##x 5030#define FM(x) FN_##x
5051 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { 5031 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
5052 0, 0, 5032 0, 0,
5053 0, 0, 5033 0, 0,
5054 0, 0, 5034 0, 0,
@@ -5080,9 +5060,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5080 GP_0_3_FN, GPSR0_3, 5060 GP_0_3_FN, GPSR0_3,
5081 GP_0_2_FN, GPSR0_2, 5061 GP_0_2_FN, GPSR0_2,
5082 GP_0_1_FN, GPSR0_1, 5062 GP_0_1_FN, GPSR0_1,
5083 GP_0_0_FN, GPSR0_0, } 5063 GP_0_0_FN, GPSR0_0, ))
5084 }, 5064 },
5085 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { 5065 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5086 0, 0, 5066 0, 0,
5087 0, 0, 5067 0, 0,
5088 0, 0, 5068 0, 0,
@@ -5114,9 +5094,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5114 GP_1_3_FN, GPSR1_3, 5094 GP_1_3_FN, GPSR1_3,
5115 GP_1_2_FN, GPSR1_2, 5095 GP_1_2_FN, GPSR1_2,
5116 GP_1_1_FN, GPSR1_1, 5096 GP_1_1_FN, GPSR1_1,
5117 GP_1_0_FN, GPSR1_0, } 5097 GP_1_0_FN, GPSR1_0, ))
5118 }, 5098 },
5119 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { 5099 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
5120 0, 0, 5100 0, 0,
5121 0, 0, 5101 0, 0,
5122 0, 0, 5102 0, 0,
@@ -5148,9 +5128,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5148 GP_2_3_FN, GPSR2_3, 5128 GP_2_3_FN, GPSR2_3,
5149 GP_2_2_FN, GPSR2_2, 5129 GP_2_2_FN, GPSR2_2,
5150 GP_2_1_FN, GPSR2_1, 5130 GP_2_1_FN, GPSR2_1,
5151 GP_2_0_FN, GPSR2_0, } 5131 GP_2_0_FN, GPSR2_0, ))
5152 }, 5132 },
5153 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { 5133 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
5154 0, 0, 5134 0, 0,
5155 0, 0, 5135 0, 0,
5156 0, 0, 5136 0, 0,
@@ -5182,9 +5162,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5182 GP_3_3_FN, GPSR3_3, 5162 GP_3_3_FN, GPSR3_3,
5183 GP_3_2_FN, GPSR3_2, 5163 GP_3_2_FN, GPSR3_2,
5184 GP_3_1_FN, GPSR3_1, 5164 GP_3_1_FN, GPSR3_1,
5185 GP_3_0_FN, GPSR3_0, } 5165 GP_3_0_FN, GPSR3_0, ))
5186 }, 5166 },
5187 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { 5167 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
5188 0, 0, 5168 0, 0,
5189 0, 0, 5169 0, 0,
5190 0, 0, 5170 0, 0,
@@ -5216,9 +5196,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5216 GP_4_3_FN, GPSR4_3, 5196 GP_4_3_FN, GPSR4_3,
5217 GP_4_2_FN, GPSR4_2, 5197 GP_4_2_FN, GPSR4_2,
5218 GP_4_1_FN, GPSR4_1, 5198 GP_4_1_FN, GPSR4_1,
5219 GP_4_0_FN, GPSR4_0, } 5199 GP_4_0_FN, GPSR4_0, ))
5220 }, 5200 },
5221 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { 5201 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5222 0, 0, 5202 0, 0,
5223 0, 0, 5203 0, 0,
5224 0, 0, 5204 0, 0,
@@ -5250,9 +5230,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5250 GP_5_3_FN, GPSR5_3, 5230 GP_5_3_FN, GPSR5_3,
5251 GP_5_2_FN, GPSR5_2, 5231 GP_5_2_FN, GPSR5_2,
5252 GP_5_1_FN, GPSR5_1, 5232 GP_5_1_FN, GPSR5_1,
5253 GP_5_0_FN, GPSR5_0, } 5233 GP_5_0_FN, GPSR5_0, ))
5254 }, 5234 },
5255 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { 5235 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5256 GP_6_31_FN, GPSR6_31, 5236 GP_6_31_FN, GPSR6_31,
5257 GP_6_30_FN, GPSR6_30, 5237 GP_6_30_FN, GPSR6_30,
5258 GP_6_29_FN, GPSR6_29, 5238 GP_6_29_FN, GPSR6_29,
@@ -5284,9 +5264,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5284 GP_6_3_FN, GPSR6_3, 5264 GP_6_3_FN, GPSR6_3,
5285 GP_6_2_FN, GPSR6_2, 5265 GP_6_2_FN, GPSR6_2,
5286 GP_6_1_FN, GPSR6_1, 5266 GP_6_1_FN, GPSR6_1,
5287 GP_6_0_FN, GPSR6_0, } 5267 GP_6_0_FN, GPSR6_0, ))
5288 }, 5268 },
5289 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) { 5269 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
5290 0, 0, 5270 0, 0,
5291 0, 0, 5271 0, 0,
5292 0, 0, 5272 0, 0,
@@ -5318,14 +5298,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5318 GP_7_3_FN, GPSR7_3, 5298 GP_7_3_FN, GPSR7_3,
5319 GP_7_2_FN, GPSR7_2, 5299 GP_7_2_FN, GPSR7_2,
5320 GP_7_1_FN, GPSR7_1, 5300 GP_7_1_FN, GPSR7_1,
5321 GP_7_0_FN, GPSR7_0, } 5301 GP_7_0_FN, GPSR7_0, ))
5322 }, 5302 },
5323#undef F_ 5303#undef F_
5324#undef FM 5304#undef FM
5325 5305
5326#define F_(x, y) x, 5306#define F_(x, y) x,
5327#define FM(x) FN_##x, 5307#define FM(x) FN_##x,
5328 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { 5308 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5329 IP0_31_28 5309 IP0_31_28
5330 IP0_27_24 5310 IP0_27_24
5331 IP0_23_20 5311 IP0_23_20
@@ -5333,9 +5313,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5333 IP0_15_12 5313 IP0_15_12
5334 IP0_11_8 5314 IP0_11_8
5335 IP0_7_4 5315 IP0_7_4
5336 IP0_3_0 } 5316 IP0_3_0 ))
5337 }, 5317 },
5338 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { 5318 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5339 IP1_31_28 5319 IP1_31_28
5340 IP1_27_24 5320 IP1_27_24
5341 IP1_23_20 5321 IP1_23_20
@@ -5343,9 +5323,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5343 IP1_15_12 5323 IP1_15_12
5344 IP1_11_8 5324 IP1_11_8
5345 IP1_7_4 5325 IP1_7_4
5346 IP1_3_0 } 5326 IP1_3_0 ))
5347 }, 5327 },
5348 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { 5328 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5349 IP2_31_28 5329 IP2_31_28
5350 IP2_27_24 5330 IP2_27_24
5351 IP2_23_20 5331 IP2_23_20
@@ -5353,9 +5333,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5353 IP2_15_12 5333 IP2_15_12
5354 IP2_11_8 5334 IP2_11_8
5355 IP2_7_4 5335 IP2_7_4
5356 IP2_3_0 } 5336 IP2_3_0 ))
5357 }, 5337 },
5358 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { 5338 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5359 IP3_31_28 5339 IP3_31_28
5360 IP3_27_24 5340 IP3_27_24
5361 IP3_23_20 5341 IP3_23_20
@@ -5363,9 +5343,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5363 IP3_15_12 5343 IP3_15_12
5364 IP3_11_8 5344 IP3_11_8
5365 IP3_7_4 5345 IP3_7_4
5366 IP3_3_0 } 5346 IP3_3_0 ))
5367 }, 5347 },
5368 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { 5348 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5369 IP4_31_28 5349 IP4_31_28
5370 IP4_27_24 5350 IP4_27_24
5371 IP4_23_20 5351 IP4_23_20
@@ -5373,9 +5353,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5373 IP4_15_12 5353 IP4_15_12
5374 IP4_11_8 5354 IP4_11_8
5375 IP4_7_4 5355 IP4_7_4
5376 IP4_3_0 } 5356 IP4_3_0 ))
5377 }, 5357 },
5378 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { 5358 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5379 IP5_31_28 5359 IP5_31_28
5380 IP5_27_24 5360 IP5_27_24
5381 IP5_23_20 5361 IP5_23_20
@@ -5383,9 +5363,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5383 IP5_15_12 5363 IP5_15_12
5384 IP5_11_8 5364 IP5_11_8
5385 IP5_7_4 5365 IP5_7_4
5386 IP5_3_0 } 5366 IP5_3_0 ))
5387 }, 5367 },
5388 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { 5368 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5389 IP6_31_28 5369 IP6_31_28
5390 IP6_27_24 5370 IP6_27_24
5391 IP6_23_20 5371 IP6_23_20
@@ -5393,9 +5373,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5393 IP6_15_12 5373 IP6_15_12
5394 IP6_11_8 5374 IP6_11_8
5395 IP6_7_4 5375 IP6_7_4
5396 IP6_3_0 } 5376 IP6_3_0 ))
5397 }, 5377 },
5398 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { 5378 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
5399 IP7_31_28 5379 IP7_31_28
5400 IP7_27_24 5380 IP7_27_24
5401 IP7_23_20 5381 IP7_23_20
@@ -5403,9 +5383,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5403 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5383 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5404 IP7_11_8 5384 IP7_11_8
5405 IP7_7_4 5385 IP7_7_4
5406 IP7_3_0 } 5386 IP7_3_0 ))
5407 }, 5387 },
5408 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { 5388 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5409 IP8_31_28 5389 IP8_31_28
5410 IP8_27_24 5390 IP8_27_24
5411 IP8_23_20 5391 IP8_23_20
@@ -5413,9 +5393,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5413 IP8_15_12 5393 IP8_15_12
5414 IP8_11_8 5394 IP8_11_8
5415 IP8_7_4 5395 IP8_7_4
5416 IP8_3_0 } 5396 IP8_3_0 ))
5417 }, 5397 },
5418 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { 5398 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5419 IP9_31_28 5399 IP9_31_28
5420 IP9_27_24 5400 IP9_27_24
5421 IP9_23_20 5401 IP9_23_20
@@ -5423,9 +5403,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5423 IP9_15_12 5403 IP9_15_12
5424 IP9_11_8 5404 IP9_11_8
5425 IP9_7_4 5405 IP9_7_4
5426 IP9_3_0 } 5406 IP9_3_0 ))
5427 }, 5407 },
5428 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { 5408 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5429 IP10_31_28 5409 IP10_31_28
5430 IP10_27_24 5410 IP10_27_24
5431 IP10_23_20 5411 IP10_23_20
@@ -5433,9 +5413,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5433 IP10_15_12 5413 IP10_15_12
5434 IP10_11_8 5414 IP10_11_8
5435 IP10_7_4 5415 IP10_7_4
5436 IP10_3_0 } 5416 IP10_3_0 ))
5437 }, 5417 },
5438 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { 5418 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5439 IP11_31_28 5419 IP11_31_28
5440 IP11_27_24 5420 IP11_27_24
5441 IP11_23_20 5421 IP11_23_20
@@ -5443,9 +5423,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5443 IP11_15_12 5423 IP11_15_12
5444 IP11_11_8 5424 IP11_11_8
5445 IP11_7_4 5425 IP11_7_4
5446 IP11_3_0 } 5426 IP11_3_0 ))
5447 }, 5427 },
5448 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { 5428 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5449 IP12_31_28 5429 IP12_31_28
5450 IP12_27_24 5430 IP12_27_24
5451 IP12_23_20 5431 IP12_23_20
@@ -5453,9 +5433,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5453 IP12_15_12 5433 IP12_15_12
5454 IP12_11_8 5434 IP12_11_8
5455 IP12_7_4 5435 IP12_7_4
5456 IP12_3_0 } 5436 IP12_3_0 ))
5457 }, 5437 },
5458 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { 5438 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5459 IP13_31_28 5439 IP13_31_28
5460 IP13_27_24 5440 IP13_27_24
5461 IP13_23_20 5441 IP13_23_20
@@ -5463,9 +5443,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5463 IP13_15_12 5443 IP13_15_12
5464 IP13_11_8 5444 IP13_11_8
5465 IP13_7_4 5445 IP13_7_4
5466 IP13_3_0 } 5446 IP13_3_0 ))
5467 }, 5447 },
5468 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { 5448 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5469 IP14_31_28 5449 IP14_31_28
5470 IP14_27_24 5450 IP14_27_24
5471 IP14_23_20 5451 IP14_23_20
@@ -5473,9 +5453,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5473 IP14_15_12 5453 IP14_15_12
5474 IP14_11_8 5454 IP14_11_8
5475 IP14_7_4 5455 IP14_7_4
5476 IP14_3_0 } 5456 IP14_3_0 ))
5477 }, 5457 },
5478 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { 5458 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5479 IP15_31_28 5459 IP15_31_28
5480 IP15_27_24 5460 IP15_27_24
5481 IP15_23_20 5461 IP15_23_20
@@ -5483,9 +5463,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5483 IP15_15_12 5463 IP15_15_12
5484 IP15_11_8 5464 IP15_11_8
5485 IP15_7_4 5465 IP15_7_4
5486 IP15_3_0 } 5466 IP15_3_0 ))
5487 }, 5467 },
5488 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) { 5468 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5489 IP16_31_28 5469 IP16_31_28
5490 IP16_27_24 5470 IP16_27_24
5491 IP16_23_20 5471 IP16_23_20
@@ -5493,9 +5473,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5493 IP16_15_12 5473 IP16_15_12
5494 IP16_11_8 5474 IP16_11_8
5495 IP16_7_4 5475 IP16_7_4
5496 IP16_3_0 } 5476 IP16_3_0 ))
5497 }, 5477 },
5498 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) { 5478 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5499 IP17_31_28 5479 IP17_31_28
5500 IP17_27_24 5480 IP17_27_24
5501 IP17_23_20 5481 IP17_23_20
@@ -5503,9 +5483,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5503 IP17_15_12 5483 IP17_15_12
5504 IP17_11_8 5484 IP17_11_8
5505 IP17_7_4 5485 IP17_7_4
5506 IP17_3_0 } 5486 IP17_3_0 ))
5507 }, 5487 },
5508 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) { 5488 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
5509 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5489 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5510 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5490 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5511 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5491 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -5513,7 +5493,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5513 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5493 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5514 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5494 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5515 IP18_7_4 5495 IP18_7_4
5516 IP18_3_0 } 5496 IP18_3_0 ))
5517 }, 5497 },
5518#undef F_ 5498#undef F_
5519#undef FM 5499#undef FM
@@ -5521,8 +5501,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5521#define F_(x, y) x, 5501#define F_(x, y) x,
5522#define FM(x) FN_##x, 5502#define FM(x) FN_##x,
5523 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 5503 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5524 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 5504 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5525 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) { 5505 1, 1, 1, 2, 2, 1, 2, 3),
5506 GROUP(
5526 MOD_SEL0_31_30_29 5507 MOD_SEL0_31_30_29
5527 MOD_SEL0_28_27 5508 MOD_SEL0_28_27
5528 MOD_SEL0_26_25_24 5509 MOD_SEL0_26_25_24
@@ -5543,11 +5524,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5543 MOD_SEL0_5 5524 MOD_SEL0_5
5544 MOD_SEL0_4_3 5525 MOD_SEL0_4_3
5545 /* RESERVED 2, 1, 0 */ 5526 /* RESERVED 2, 1, 0 */
5546 0, 0, 0, 0, 0, 0, 0, 0 } 5527 0, 0, 0, 0, 0, 0, 0, 0 ))
5547 }, 5528 },
5548 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 5529 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5549 2, 3, 1, 2, 3, 1, 1, 2, 1, 5530 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5550 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { 5531 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5532 GROUP(
5551 MOD_SEL1_31_30 5533 MOD_SEL1_31_30
5552 MOD_SEL1_29_28_27 5534 MOD_SEL1_29_28_27
5553 MOD_SEL1_26 5535 MOD_SEL1_26
@@ -5570,11 +5552,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5570 MOD_SEL1_3 5552 MOD_SEL1_3
5571 MOD_SEL1_2 5553 MOD_SEL1_2
5572 MOD_SEL1_1 5554 MOD_SEL1_1
5573 MOD_SEL1_0 } 5555 MOD_SEL1_0 ))
5574 }, 5556 },
5575 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, 5557 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5576 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, 5558 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5577 4, 4, 4, 3, 1) { 5559 1, 4, 4, 4, 3, 1),
5560 GROUP(
5578 MOD_SEL2_31 5561 MOD_SEL2_31
5579 MOD_SEL2_30 5562 MOD_SEL2_30
5580 MOD_SEL2_29 5563 MOD_SEL2_29
@@ -5600,7 +5583,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5600 0, 0, 0, 0, 0, 0, 0, 0, 5583 0, 0, 0, 0, 0, 0, 0, 0,
5601 /* RESERVED 3, 2, 1 */ 5584 /* RESERVED 3, 2, 1 */
5602 0, 0, 0, 0, 0, 0, 0, 0, 5585 0, 0, 0, 0, 0, 0, 0, 0,
5603 MOD_SEL2_0 } 5586 MOD_SEL2_0 ))
5604 }, 5587 },
5605 { }, 5588 { },
5606}; 5589};
@@ -5721,7 +5704,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5721 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ 5704 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5722 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ 5705 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5723 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ 5706 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5724 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ 5707 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5725 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ 5708 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5726 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ 5709 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5727 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ 5710 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
@@ -5855,10 +5838,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5855 5838
5856enum ioctrl_regs { 5839enum ioctrl_regs {
5857 POCCTRL, 5840 POCCTRL,
5841 TDSELCTRL,
5858}; 5842};
5859 5843
5860static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 5844static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5861 [POCCTRL] = { 0xe6060380, }, 5845 [POCCTRL] = { 0xe6060380, },
5846 [TDSELCTRL] = { 0xe60603c0, },
5862 { /* sentinel */ }, 5847 { /* sentinel */ },
5863}; 5848};
5864 5849
@@ -5975,7 +5960,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5975 [25] = RCAR_GP_PIN(0, 15), /* D15 */ 5960 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5976 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ 5961 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5977 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ 5962 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
5978 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */ 5963 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
5979 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ 5964 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
5980 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ 5965 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
5981 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ 5966 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
index 14c4b671cddf..090024355eba 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -3,7 +3,7 @@
3 * R8A77965 processor support - PFC hardware block. 3 * R8A77965 processor support - PFC hardware block.
4 * 4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> 5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 * Copyright (C) 2016 Renesas Electronics Corp. 6 * Copyright (C) 2016-2019 Renesas Electronics Corp.
7 * 7 *
8 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c 8 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
9 * 9 *
@@ -12,6 +12,7 @@
12 * Copyright (C) 2015 Renesas Electronics Corporation 12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */ 13 */
14 14
15#include <linux/errno.h>
15#include <linux/kernel.h> 16#include <linux/kernel.h>
16 17
17#include "core.h" 18#include "core.h"
@@ -207,7 +208,7 @@
207 208
208/* GPSR7 */ 209/* GPSR7 */
209#define GPSR7_3 FM(GP7_03) 210#define GPSR7_3 FM(GP7_03)
210#define GPSR7_2 FM(HDMI0_CEC) 211#define GPSR7_2 FM(GP7_02)
211#define GPSR7_1 FM(AVS2) 212#define GPSR7_1 FM(AVS2)
212#define GPSR7_0 FM(AVS1) 213#define GPSR7_0 FM(AVS1)
213 214
@@ -356,7 +357,7 @@
356#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 357#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 358#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 359#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 360#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 361#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) 362#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
362#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) 363#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
@@ -467,7 +468,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
467#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) 468#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
468#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) 469#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
469#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 470#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
470#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3) 471#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
471 472
472/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 473/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
473#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) 474#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
@@ -500,12 +501,12 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
500#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) 501#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
501#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) 502#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
502#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 503#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
503#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1) 504#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
504#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) 505#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
505#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 506#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
506#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) 507#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
507#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1) 508#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
508#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1) 509#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
509#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) 510#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
510 511
511#define PINMUX_MOD_SELS \ 512#define PINMUX_MOD_SELS \
@@ -557,6 +558,9 @@ MOD_SEL0_4_3 MOD_SEL1_4 \
557 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \ 558 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
558 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) 559 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
559 560
561#define PINMUX_PHYS \
562 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
563
560enum { 564enum {
561 PINMUX_RESERVED = 0, 565 PINMUX_RESERVED = 0,
562 566
@@ -582,6 +586,7 @@ enum {
582 PINMUX_IPSR 586 PINMUX_IPSR
583 PINMUX_MOD_SELS 587 PINMUX_MOD_SELS
584 PINMUX_STATIC 588 PINMUX_STATIC
589 PINMUX_PHYS
585 PINMUX_MARK_END, 590 PINMUX_MARK_END,
586#undef F_ 591#undef F_
587#undef FM 592#undef FM
@@ -594,7 +599,7 @@ static const u16 pinmux_data[] = {
594 PINMUX_SINGLE(AVS2), 599 PINMUX_SINGLE(AVS2),
595 PINMUX_SINGLE(CLKOUT), 600 PINMUX_SINGLE(CLKOUT),
596 PINMUX_SINGLE(GP7_03), 601 PINMUX_SINGLE(GP7_03),
597 PINMUX_SINGLE(HDMI0_CEC), 602 PINMUX_SINGLE(GP7_02),
598 PINMUX_SINGLE(MSIOF0_RXD), 603 PINMUX_SINGLE(MSIOF0_RXD),
599 PINMUX_SINGLE(MSIOF0_SCK), 604 PINMUX_SINGLE(MSIOF0_SCK),
600 PINMUX_SINGLE(MSIOF0_TXD), 605 PINMUX_SINGLE(MSIOF0_TXD),
@@ -619,13 +624,15 @@ static const u16 pinmux_data[] = {
619 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), 624 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
620 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A), 625 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
621 626
622 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0), 627 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
623 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2), 628 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
624 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0), 629 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
630 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
625 631
626 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), 632 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
627 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), 633 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
628 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0), 634 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
635 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
629 636
630 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), 637 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
631 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), 638 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
@@ -678,14 +685,16 @@ static const u16 pinmux_data[] = {
678 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), 685 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
679 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), 686 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
680 687
681 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), 688 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
682 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), 689 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
683 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), 690 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
684 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), 691 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
692 PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
685 693
686 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), 694 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
687 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), 695 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
688 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), 696 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
697 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
689 698
690 PINMUX_IPSR_GPSR(IP1_31_28, A0), 699 PINMUX_IPSR_GPSR(IP1_31_28, A0),
691 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), 700 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
@@ -1016,35 +1025,35 @@ static const u16 pinmux_data[] = {
1016 1025
1017 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), 1026 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1018 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), 1027 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1019 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1), 1028 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
1020 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), 1029 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1021 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), 1030 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1022 1031
1023 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), 1032 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1024 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), 1033 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1025 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), 1034 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1026 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1), 1035 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
1027 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), 1036 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1028 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), 1037 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1029 1038
1030 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), 1039 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1031 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), 1040 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1032 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), 1041 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1033 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1), 1042 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
1034 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), 1043 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1035 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), 1044 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1036 1045
1037 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), 1046 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1038 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), 1047 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1039 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), 1048 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1040 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1), 1049 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
1041 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), 1050 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1042 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), 1051 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1043 1052
1044 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), 1053 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1045 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), 1054 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1046 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), 1055 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1047 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1), 1056 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
1048 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), 1057 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1049 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), 1058 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1050 1059
@@ -1111,26 +1120,28 @@ static const u16 pinmux_data[] = {
1111 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), 1120 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1112 1121
1113 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), 1122 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1114 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0), 1123 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
1115 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), 1124 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1116 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), 1125 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1117 1126
1118 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), 1127 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1119 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0), 1128 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
1120 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), 1129 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1121 1130
1122 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD), 1131 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1123 PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0), 1132 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
1124 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1), 1133 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1134 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
1125 1135
1126 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP), 1136 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1127 PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0), 1137 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
1128 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1), 1138 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1139 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
1129 1140
1130 PINMUX_IPSR_GPSR(IP11_27_24, SCK0), 1141 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1131 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), 1142 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1132 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), 1143 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1133 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1), 1144 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
1134 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), 1145 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1135 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), 1146 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1136 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), 1147 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
@@ -1163,7 +1174,7 @@ static const u16 pinmux_data[] = {
1163 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), 1174 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1164 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), 1175 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1165 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), 1176 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1166 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), 1177 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
1167 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), 1178 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1168 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), 1179 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1169 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), 1180 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
@@ -1222,7 +1233,7 @@ static const u16 pinmux_data[] = {
1222 1233
1223 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), 1234 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1224 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), 1235 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1225 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0), 1236 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
1226 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), 1237 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1227 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), 1238 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1228 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), 1239 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
@@ -1268,8 +1279,8 @@ static const u16 pinmux_data[] = {
1268 /* IPSR14 */ 1279 /* IPSR14 */
1269 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), 1280 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1270 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), 1281 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1271 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0), 1282 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1272 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), 1283 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
1273 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), 1284 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1274 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), 1285 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1275 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), 1286 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
@@ -1278,7 +1289,7 @@ static const u16 pinmux_data[] = {
1278 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), 1289 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1279 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), 1290 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1280 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), 1291 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1281 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0), 1292 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
1282 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), 1293 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1283 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), 1294 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1284 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), 1295 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
@@ -1407,10 +1418,9 @@ static const u16 pinmux_data[] = {
1407 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), 1418 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1408 1419
1409 /* IPSR17 */ 1420 /* IPSR17 */
1410 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), 1421 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
1411 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1412 1422
1413 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), 1423 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
1414 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), 1424 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1415 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), 1425 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1416 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), 1426 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
@@ -1494,11 +1504,6 @@ static const u16 pinmux_data[] = {
1494 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), 1504 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1495 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), 1505 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1496 1506
1497 /* I2C */
1498 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1499 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1500 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
1501
1502/* 1507/*
1503 * Static pins can not be muxed between different functions but 1508 * Static pins can not be muxed between different functions but
1504 * still need mark entries in the pinmux list. Add each static 1509 * still need mark entries in the pinmux list. Add each static
@@ -2478,52 +2483,92 @@ static const unsigned int hscif4_data_b_mux[] = {
2478}; 2483};
2479 2484
2480/* - I2C -------------------------------------------------------------------- */ 2485/* - I2C -------------------------------------------------------------------- */
2486static const unsigned int i2c0_pins[] = {
2487 /* SCL, SDA */
2488 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2489};
2490
2491static const unsigned int i2c0_mux[] = {
2492 SCL0_MARK, SDA0_MARK,
2493};
2494
2481static const unsigned int i2c1_a_pins[] = { 2495static const unsigned int i2c1_a_pins[] = {
2482 /* SDA, SCL */ 2496 /* SDA, SCL */
2483 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), 2497 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2484}; 2498};
2499
2485static const unsigned int i2c1_a_mux[] = { 2500static const unsigned int i2c1_a_mux[] = {
2486 SDA1_A_MARK, SCL1_A_MARK, 2501 SDA1_A_MARK, SCL1_A_MARK,
2487}; 2502};
2503
2488static const unsigned int i2c1_b_pins[] = { 2504static const unsigned int i2c1_b_pins[] = {
2489 /* SDA, SCL */ 2505 /* SDA, SCL */
2490 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), 2506 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2491}; 2507};
2508
2492static const unsigned int i2c1_b_mux[] = { 2509static const unsigned int i2c1_b_mux[] = {
2493 SDA1_B_MARK, SCL1_B_MARK, 2510 SDA1_B_MARK, SCL1_B_MARK,
2494}; 2511};
2512
2495static const unsigned int i2c2_a_pins[] = { 2513static const unsigned int i2c2_a_pins[] = {
2496 /* SDA, SCL */ 2514 /* SDA, SCL */
2497 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), 2515 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2498}; 2516};
2517
2499static const unsigned int i2c2_a_mux[] = { 2518static const unsigned int i2c2_a_mux[] = {
2500 SDA2_A_MARK, SCL2_A_MARK, 2519 SDA2_A_MARK, SCL2_A_MARK,
2501}; 2520};
2521
2502static const unsigned int i2c2_b_pins[] = { 2522static const unsigned int i2c2_b_pins[] = {
2503 /* SDA, SCL */ 2523 /* SDA, SCL */
2504 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 2524 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2505}; 2525};
2526
2506static const unsigned int i2c2_b_mux[] = { 2527static const unsigned int i2c2_b_mux[] = {
2507 SDA2_B_MARK, SCL2_B_MARK, 2528 SDA2_B_MARK, SCL2_B_MARK,
2508}; 2529};
2530
2531static const unsigned int i2c3_pins[] = {
2532 /* SCL, SDA */
2533 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2534};
2535
2536static const unsigned int i2c3_mux[] = {
2537 SCL3_MARK, SDA3_MARK,
2538};
2539
2540static const unsigned int i2c5_pins[] = {
2541 /* SCL, SDA */
2542 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2543};
2544
2545static const unsigned int i2c5_mux[] = {
2546 SCL5_MARK, SDA5_MARK,
2547};
2548
2509static const unsigned int i2c6_a_pins[] = { 2549static const unsigned int i2c6_a_pins[] = {
2510 /* SDA, SCL */ 2550 /* SDA, SCL */
2511 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), 2551 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2512}; 2552};
2553
2513static const unsigned int i2c6_a_mux[] = { 2554static const unsigned int i2c6_a_mux[] = {
2514 SDA6_A_MARK, SCL6_A_MARK, 2555 SDA6_A_MARK, SCL6_A_MARK,
2515}; 2556};
2557
2516static const unsigned int i2c6_b_pins[] = { 2558static const unsigned int i2c6_b_pins[] = {
2517 /* SDA, SCL */ 2559 /* SDA, SCL */
2518 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), 2560 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2519}; 2561};
2562
2520static const unsigned int i2c6_b_mux[] = { 2563static const unsigned int i2c6_b_mux[] = {
2521 SDA6_B_MARK, SCL6_B_MARK, 2564 SDA6_B_MARK, SCL6_B_MARK,
2522}; 2565};
2566
2523static const unsigned int i2c6_c_pins[] = { 2567static const unsigned int i2c6_c_pins[] = {
2524 /* SDA, SCL */ 2568 /* SDA, SCL */
2525 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), 2569 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2526}; 2570};
2571
2527static const unsigned int i2c6_c_mux[] = { 2572static const unsigned int i2c6_c_mux[] = {
2528 SDA6_C_MARK, SCL6_C_MARK, 2573 SDA6_C_MARK, SCL6_C_MARK,
2529}; 2574};
@@ -4413,10 +4458,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
4413 SH_PFC_PIN_GROUP(hscif4_clk), 4458 SH_PFC_PIN_GROUP(hscif4_clk),
4414 SH_PFC_PIN_GROUP(hscif4_ctrl), 4459 SH_PFC_PIN_GROUP(hscif4_ctrl),
4415 SH_PFC_PIN_GROUP(hscif4_data_b), 4460 SH_PFC_PIN_GROUP(hscif4_data_b),
4461 SH_PFC_PIN_GROUP(i2c0),
4416 SH_PFC_PIN_GROUP(i2c1_a), 4462 SH_PFC_PIN_GROUP(i2c1_a),
4417 SH_PFC_PIN_GROUP(i2c1_b), 4463 SH_PFC_PIN_GROUP(i2c1_b),
4418 SH_PFC_PIN_GROUP(i2c2_a), 4464 SH_PFC_PIN_GROUP(i2c2_a),
4419 SH_PFC_PIN_GROUP(i2c2_b), 4465 SH_PFC_PIN_GROUP(i2c2_b),
4466 SH_PFC_PIN_GROUP(i2c3),
4467 SH_PFC_PIN_GROUP(i2c5),
4420 SH_PFC_PIN_GROUP(i2c6_a), 4468 SH_PFC_PIN_GROUP(i2c6_a),
4421 SH_PFC_PIN_GROUP(i2c6_b), 4469 SH_PFC_PIN_GROUP(i2c6_b),
4422 SH_PFC_PIN_GROUP(i2c6_c), 4470 SH_PFC_PIN_GROUP(i2c6_c),
@@ -4807,6 +4855,10 @@ static const char * const hscif4_groups[] = {
4807 "hscif4_data_b", 4855 "hscif4_data_b",
4808}; 4856};
4809 4857
4858static const char * const i2c0_groups[] = {
4859 "i2c0",
4860};
4861
4810static const char * const i2c1_groups[] = { 4862static const char * const i2c1_groups[] = {
4811 "i2c1_a", 4863 "i2c1_a",
4812 "i2c1_b", 4864 "i2c1_b",
@@ -4817,6 +4869,14 @@ static const char * const i2c2_groups[] = {
4817 "i2c2_b", 4869 "i2c2_b",
4818}; 4870};
4819 4871
4872static const char * const i2c3_groups[] = {
4873 "i2c3",
4874};
4875
4876static const char * const i2c5_groups[] = {
4877 "i2c5",
4878};
4879
4820static const char * const i2c6_groups[] = { 4880static const char * const i2c6_groups[] = {
4821 "i2c6_a", 4881 "i2c6_a",
4822 "i2c6_b", 4882 "i2c6_b",
@@ -5166,8 +5226,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
5166 SH_PFC_FUNCTION(hscif2), 5226 SH_PFC_FUNCTION(hscif2),
5167 SH_PFC_FUNCTION(hscif3), 5227 SH_PFC_FUNCTION(hscif3),
5168 SH_PFC_FUNCTION(hscif4), 5228 SH_PFC_FUNCTION(hscif4),
5229 SH_PFC_FUNCTION(i2c0),
5169 SH_PFC_FUNCTION(i2c1), 5230 SH_PFC_FUNCTION(i2c1),
5170 SH_PFC_FUNCTION(i2c2), 5231 SH_PFC_FUNCTION(i2c2),
5232 SH_PFC_FUNCTION(i2c3),
5233 SH_PFC_FUNCTION(i2c5),
5171 SH_PFC_FUNCTION(i2c6), 5234 SH_PFC_FUNCTION(i2c6),
5172 SH_PFC_FUNCTION(intc_ex), 5235 SH_PFC_FUNCTION(intc_ex),
5173 SH_PFC_FUNCTION(msiof0), 5236 SH_PFC_FUNCTION(msiof0),
@@ -5205,7 +5268,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
5205static const struct pinmux_cfg_reg pinmux_config_regs[] = { 5268static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5206#define F_(x, y) FN_##y 5269#define F_(x, y) FN_##y
5207#define FM(x) FN_##x 5270#define FM(x) FN_##x
5208 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { 5271 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
5209 0, 0, 5272 0, 0,
5210 0, 0, 5273 0, 0,
5211 0, 0, 5274 0, 0,
@@ -5237,9 +5300,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5237 GP_0_3_FN, GPSR0_3, 5300 GP_0_3_FN, GPSR0_3,
5238 GP_0_2_FN, GPSR0_2, 5301 GP_0_2_FN, GPSR0_2,
5239 GP_0_1_FN, GPSR0_1, 5302 GP_0_1_FN, GPSR0_1,
5240 GP_0_0_FN, GPSR0_0, } 5303 GP_0_0_FN, GPSR0_0, ))
5241 }, 5304 },
5242 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { 5305 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5243 0, 0, 5306 0, 0,
5244 0, 0, 5307 0, 0,
5245 0, 0, 5308 0, 0,
@@ -5271,9 +5334,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5271 GP_1_3_FN, GPSR1_3, 5334 GP_1_3_FN, GPSR1_3,
5272 GP_1_2_FN, GPSR1_2, 5335 GP_1_2_FN, GPSR1_2,
5273 GP_1_1_FN, GPSR1_1, 5336 GP_1_1_FN, GPSR1_1,
5274 GP_1_0_FN, GPSR1_0, } 5337 GP_1_0_FN, GPSR1_0, ))
5275 }, 5338 },
5276 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { 5339 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
5277 0, 0, 5340 0, 0,
5278 0, 0, 5341 0, 0,
5279 0, 0, 5342 0, 0,
@@ -5305,9 +5368,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5305 GP_2_3_FN, GPSR2_3, 5368 GP_2_3_FN, GPSR2_3,
5306 GP_2_2_FN, GPSR2_2, 5369 GP_2_2_FN, GPSR2_2,
5307 GP_2_1_FN, GPSR2_1, 5370 GP_2_1_FN, GPSR2_1,
5308 GP_2_0_FN, GPSR2_0, } 5371 GP_2_0_FN, GPSR2_0, ))
5309 }, 5372 },
5310 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { 5373 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
5311 0, 0, 5374 0, 0,
5312 0, 0, 5375 0, 0,
5313 0, 0, 5376 0, 0,
@@ -5339,9 +5402,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5339 GP_3_3_FN, GPSR3_3, 5402 GP_3_3_FN, GPSR3_3,
5340 GP_3_2_FN, GPSR3_2, 5403 GP_3_2_FN, GPSR3_2,
5341 GP_3_1_FN, GPSR3_1, 5404 GP_3_1_FN, GPSR3_1,
5342 GP_3_0_FN, GPSR3_0, } 5405 GP_3_0_FN, GPSR3_0, ))
5343 }, 5406 },
5344 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { 5407 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
5345 0, 0, 5408 0, 0,
5346 0, 0, 5409 0, 0,
5347 0, 0, 5410 0, 0,
@@ -5373,9 +5436,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5373 GP_4_3_FN, GPSR4_3, 5436 GP_4_3_FN, GPSR4_3,
5374 GP_4_2_FN, GPSR4_2, 5437 GP_4_2_FN, GPSR4_2,
5375 GP_4_1_FN, GPSR4_1, 5438 GP_4_1_FN, GPSR4_1,
5376 GP_4_0_FN, GPSR4_0, } 5439 GP_4_0_FN, GPSR4_0, ))
5377 }, 5440 },
5378 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { 5441 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5379 0, 0, 5442 0, 0,
5380 0, 0, 5443 0, 0,
5381 0, 0, 5444 0, 0,
@@ -5407,9 +5470,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5407 GP_5_3_FN, GPSR5_3, 5470 GP_5_3_FN, GPSR5_3,
5408 GP_5_2_FN, GPSR5_2, 5471 GP_5_2_FN, GPSR5_2,
5409 GP_5_1_FN, GPSR5_1, 5472 GP_5_1_FN, GPSR5_1,
5410 GP_5_0_FN, GPSR5_0, } 5473 GP_5_0_FN, GPSR5_0, ))
5411 }, 5474 },
5412 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { 5475 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5413 GP_6_31_FN, GPSR6_31, 5476 GP_6_31_FN, GPSR6_31,
5414 GP_6_30_FN, GPSR6_30, 5477 GP_6_30_FN, GPSR6_30,
5415 GP_6_29_FN, GPSR6_29, 5478 GP_6_29_FN, GPSR6_29,
@@ -5441,9 +5504,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5441 GP_6_3_FN, GPSR6_3, 5504 GP_6_3_FN, GPSR6_3,
5442 GP_6_2_FN, GPSR6_2, 5505 GP_6_2_FN, GPSR6_2,
5443 GP_6_1_FN, GPSR6_1, 5506 GP_6_1_FN, GPSR6_1,
5444 GP_6_0_FN, GPSR6_0, } 5507 GP_6_0_FN, GPSR6_0, ))
5445 }, 5508 },
5446 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) { 5509 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
5447 0, 0, 5510 0, 0,
5448 0, 0, 5511 0, 0,
5449 0, 0, 5512 0, 0,
@@ -5475,14 +5538,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5475 GP_7_3_FN, GPSR7_3, 5538 GP_7_3_FN, GPSR7_3,
5476 GP_7_2_FN, GPSR7_2, 5539 GP_7_2_FN, GPSR7_2,
5477 GP_7_1_FN, GPSR7_1, 5540 GP_7_1_FN, GPSR7_1,
5478 GP_7_0_FN, GPSR7_0, } 5541 GP_7_0_FN, GPSR7_0, ))
5479 }, 5542 },
5480#undef F_ 5543#undef F_
5481#undef FM 5544#undef FM
5482 5545
5483#define F_(x, y) x, 5546#define F_(x, y) x,
5484#define FM(x) FN_##x, 5547#define FM(x) FN_##x,
5485 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { 5548 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5486 IP0_31_28 5549 IP0_31_28
5487 IP0_27_24 5550 IP0_27_24
5488 IP0_23_20 5551 IP0_23_20
@@ -5490,9 +5553,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5490 IP0_15_12 5553 IP0_15_12
5491 IP0_11_8 5554 IP0_11_8
5492 IP0_7_4 5555 IP0_7_4
5493 IP0_3_0 } 5556 IP0_3_0 ))
5494 }, 5557 },
5495 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { 5558 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5496 IP1_31_28 5559 IP1_31_28
5497 IP1_27_24 5560 IP1_27_24
5498 IP1_23_20 5561 IP1_23_20
@@ -5500,9 +5563,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5500 IP1_15_12 5563 IP1_15_12
5501 IP1_11_8 5564 IP1_11_8
5502 IP1_7_4 5565 IP1_7_4
5503 IP1_3_0 } 5566 IP1_3_0 ))
5504 }, 5567 },
5505 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { 5568 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5506 IP2_31_28 5569 IP2_31_28
5507 IP2_27_24 5570 IP2_27_24
5508 IP2_23_20 5571 IP2_23_20
@@ -5510,9 +5573,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5510 IP2_15_12 5573 IP2_15_12
5511 IP2_11_8 5574 IP2_11_8
5512 IP2_7_4 5575 IP2_7_4
5513 IP2_3_0 } 5576 IP2_3_0 ))
5514 }, 5577 },
5515 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { 5578 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5516 IP3_31_28 5579 IP3_31_28
5517 IP3_27_24 5580 IP3_27_24
5518 IP3_23_20 5581 IP3_23_20
@@ -5520,9 +5583,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5520 IP3_15_12 5583 IP3_15_12
5521 IP3_11_8 5584 IP3_11_8
5522 IP3_7_4 5585 IP3_7_4
5523 IP3_3_0 } 5586 IP3_3_0 ))
5524 }, 5587 },
5525 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { 5588 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5526 IP4_31_28 5589 IP4_31_28
5527 IP4_27_24 5590 IP4_27_24
5528 IP4_23_20 5591 IP4_23_20
@@ -5530,9 +5593,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5530 IP4_15_12 5593 IP4_15_12
5531 IP4_11_8 5594 IP4_11_8
5532 IP4_7_4 5595 IP4_7_4
5533 IP4_3_0 } 5596 IP4_3_0 ))
5534 }, 5597 },
5535 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { 5598 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5536 IP5_31_28 5599 IP5_31_28
5537 IP5_27_24 5600 IP5_27_24
5538 IP5_23_20 5601 IP5_23_20
@@ -5540,9 +5603,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5540 IP5_15_12 5603 IP5_15_12
5541 IP5_11_8 5604 IP5_11_8
5542 IP5_7_4 5605 IP5_7_4
5543 IP5_3_0 } 5606 IP5_3_0 ))
5544 }, 5607 },
5545 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { 5608 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5546 IP6_31_28 5609 IP6_31_28
5547 IP6_27_24 5610 IP6_27_24
5548 IP6_23_20 5611 IP6_23_20
@@ -5550,9 +5613,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5550 IP6_15_12 5613 IP6_15_12
5551 IP6_11_8 5614 IP6_11_8
5552 IP6_7_4 5615 IP6_7_4
5553 IP6_3_0 } 5616 IP6_3_0 ))
5554 }, 5617 },
5555 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { 5618 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
5556 IP7_31_28 5619 IP7_31_28
5557 IP7_27_24 5620 IP7_27_24
5558 IP7_23_20 5621 IP7_23_20
@@ -5560,9 +5623,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5560 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5623 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5561 IP7_11_8 5624 IP7_11_8
5562 IP7_7_4 5625 IP7_7_4
5563 IP7_3_0 } 5626 IP7_3_0 ))
5564 }, 5627 },
5565 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { 5628 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5566 IP8_31_28 5629 IP8_31_28
5567 IP8_27_24 5630 IP8_27_24
5568 IP8_23_20 5631 IP8_23_20
@@ -5570,9 +5633,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5570 IP8_15_12 5633 IP8_15_12
5571 IP8_11_8 5634 IP8_11_8
5572 IP8_7_4 5635 IP8_7_4
5573 IP8_3_0 } 5636 IP8_3_0 ))
5574 }, 5637 },
5575 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { 5638 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5576 IP9_31_28 5639 IP9_31_28
5577 IP9_27_24 5640 IP9_27_24
5578 IP9_23_20 5641 IP9_23_20
@@ -5580,9 +5643,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5580 IP9_15_12 5643 IP9_15_12
5581 IP9_11_8 5644 IP9_11_8
5582 IP9_7_4 5645 IP9_7_4
5583 IP9_3_0 } 5646 IP9_3_0 ))
5584 }, 5647 },
5585 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { 5648 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5586 IP10_31_28 5649 IP10_31_28
5587 IP10_27_24 5650 IP10_27_24
5588 IP10_23_20 5651 IP10_23_20
@@ -5590,9 +5653,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5590 IP10_15_12 5653 IP10_15_12
5591 IP10_11_8 5654 IP10_11_8
5592 IP10_7_4 5655 IP10_7_4
5593 IP10_3_0 } 5656 IP10_3_0 ))
5594 }, 5657 },
5595 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { 5658 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5596 IP11_31_28 5659 IP11_31_28
5597 IP11_27_24 5660 IP11_27_24
5598 IP11_23_20 5661 IP11_23_20
@@ -5600,9 +5663,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5600 IP11_15_12 5663 IP11_15_12
5601 IP11_11_8 5664 IP11_11_8
5602 IP11_7_4 5665 IP11_7_4
5603 IP11_3_0 } 5666 IP11_3_0 ))
5604 }, 5667 },
5605 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { 5668 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5606 IP12_31_28 5669 IP12_31_28
5607 IP12_27_24 5670 IP12_27_24
5608 IP12_23_20 5671 IP12_23_20
@@ -5610,9 +5673,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5610 IP12_15_12 5673 IP12_15_12
5611 IP12_11_8 5674 IP12_11_8
5612 IP12_7_4 5675 IP12_7_4
5613 IP12_3_0 } 5676 IP12_3_0 ))
5614 }, 5677 },
5615 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { 5678 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5616 IP13_31_28 5679 IP13_31_28
5617 IP13_27_24 5680 IP13_27_24
5618 IP13_23_20 5681 IP13_23_20
@@ -5620,9 +5683,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5620 IP13_15_12 5683 IP13_15_12
5621 IP13_11_8 5684 IP13_11_8
5622 IP13_7_4 5685 IP13_7_4
5623 IP13_3_0 } 5686 IP13_3_0 ))
5624 }, 5687 },
5625 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { 5688 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5626 IP14_31_28 5689 IP14_31_28
5627 IP14_27_24 5690 IP14_27_24
5628 IP14_23_20 5691 IP14_23_20
@@ -5630,9 +5693,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5630 IP14_15_12 5693 IP14_15_12
5631 IP14_11_8 5694 IP14_11_8
5632 IP14_7_4 5695 IP14_7_4
5633 IP14_3_0 } 5696 IP14_3_0 ))
5634 }, 5697 },
5635 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { 5698 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5636 IP15_31_28 5699 IP15_31_28
5637 IP15_27_24 5700 IP15_27_24
5638 IP15_23_20 5701 IP15_23_20
@@ -5640,9 +5703,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5640 IP15_15_12 5703 IP15_15_12
5641 IP15_11_8 5704 IP15_11_8
5642 IP15_7_4 5705 IP15_7_4
5643 IP15_3_0 } 5706 IP15_3_0 ))
5644 }, 5707 },
5645 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) { 5708 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5646 IP16_31_28 5709 IP16_31_28
5647 IP16_27_24 5710 IP16_27_24
5648 IP16_23_20 5711 IP16_23_20
@@ -5650,9 +5713,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5650 IP16_15_12 5713 IP16_15_12
5651 IP16_11_8 5714 IP16_11_8
5652 IP16_7_4 5715 IP16_7_4
5653 IP16_3_0 } 5716 IP16_3_0 ))
5654 }, 5717 },
5655 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) { 5718 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5656 IP17_31_28 5719 IP17_31_28
5657 IP17_27_24 5720 IP17_27_24
5658 IP17_23_20 5721 IP17_23_20
@@ -5660,9 +5723,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5660 IP17_15_12 5723 IP17_15_12
5661 IP17_11_8 5724 IP17_11_8
5662 IP17_7_4 5725 IP17_7_4
5663 IP17_3_0 } 5726 IP17_3_0 ))
5664 }, 5727 },
5665 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) { 5728 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
5666 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5729 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5667 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5730 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5668 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5731 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -5670,7 +5733,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5670 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5733 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5671 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5734 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5672 IP18_7_4 5735 IP18_7_4
5673 IP18_3_0 } 5736 IP18_3_0 ))
5674 }, 5737 },
5675#undef F_ 5738#undef F_
5676#undef FM 5739#undef FM
@@ -5678,8 +5741,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5678#define F_(x, y) x, 5741#define F_(x, y) x,
5679#define FM(x) FN_##x, 5742#define FM(x) FN_##x,
5680 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 5743 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5681 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 5744 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5682 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) { 5745 1, 1, 1, 2, 2, 1, 2, 3),
5746 GROUP(
5683 MOD_SEL0_31_30_29 5747 MOD_SEL0_31_30_29
5684 MOD_SEL0_28_27 5748 MOD_SEL0_28_27
5685 MOD_SEL0_26_25_24 5749 MOD_SEL0_26_25_24
@@ -5700,11 +5764,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5700 MOD_SEL0_5 5764 MOD_SEL0_5
5701 MOD_SEL0_4_3 5765 MOD_SEL0_4_3
5702 /* RESERVED 2, 1, 0 */ 5766 /* RESERVED 2, 1, 0 */
5703 0, 0, 0, 0, 0, 0, 0, 0 } 5767 0, 0, 0, 0, 0, 0, 0, 0 ))
5704 }, 5768 },
5705 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 5769 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5706 2, 3, 1, 2, 3, 1, 1, 2, 1, 5770 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5707 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { 5771 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5772 GROUP(
5708 MOD_SEL1_31_30 5773 MOD_SEL1_31_30
5709 MOD_SEL1_29_28_27 5774 MOD_SEL1_29_28_27
5710 MOD_SEL1_26 5775 MOD_SEL1_26
@@ -5727,11 +5792,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5727 MOD_SEL1_3 5792 MOD_SEL1_3
5728 MOD_SEL1_2 5793 MOD_SEL1_2
5729 MOD_SEL1_1 5794 MOD_SEL1_1
5730 MOD_SEL1_0 } 5795 MOD_SEL1_0 ))
5731 }, 5796 },
5732 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, 5797 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5733 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, 5798 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5734 4, 4, 4, 3, 1) { 5799 1, 4, 4, 4, 3, 1),
5800 GROUP(
5735 MOD_SEL2_31 5801 MOD_SEL2_31
5736 MOD_SEL2_30 5802 MOD_SEL2_30
5737 MOD_SEL2_29 5803 MOD_SEL2_29
@@ -5757,7 +5823,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5757 0, 0, 0, 0, 0, 0, 0, 0, 5823 0, 0, 0, 0, 0, 0, 0, 0,
5758 /* RESERVED 3, 2, 1 */ 5824 /* RESERVED 3, 2, 1 */
5759 0, 0, 0, 0, 0, 0, 0, 0, 5825 0, 0, 0, 0, 0, 0, 0, 0,
5760 MOD_SEL2_0 } 5826 MOD_SEL2_0 ))
5761 }, 5827 },
5762 { }, 5828 { },
5763}; 5829};
@@ -5878,7 +5944,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5878 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ 5944 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5879 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ 5945 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5880 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ 5946 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5881 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ 5947 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5882 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ 5948 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5883 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ 5949 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5884 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ 5950 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
@@ -6012,10 +6078,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
6012 6078
6013enum ioctrl_regs { 6079enum ioctrl_regs {
6014 POCCTRL, 6080 POCCTRL,
6081 TDSELCTRL,
6015}; 6082};
6016 6083
6017static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 6084static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
6018 [POCCTRL] = { 0xe6060380, }, 6085 [POCCTRL] = { 0xe6060380, },
6086 [TDSELCTRL] = { 0xe60603c0, },
6019 { /* sentinel */ }, 6087 { /* sentinel */ },
6020}; 6088};
6021 6089
@@ -6132,7 +6200,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
6132 [25] = RCAR_GP_PIN(0, 15), /* D15 */ 6200 [25] = RCAR_GP_PIN(0, 15), /* D15 */
6133 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ 6201 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
6134 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ 6202 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
6135 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */ 6203 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
6136 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ 6204 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
6137 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ 6205 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
6138 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ 6206 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
index c5e67ba29f7c..2d76b548b942 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
@@ -12,6 +12,7 @@
12 * Copyright (C) 2015 Renesas Electronics Corporation 12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */ 13 */
14 14
15#include <linux/errno.h>
15#include <linux/io.h> 16#include <linux/io.h>
16#include <linux/kernel.h> 17#include <linux/kernel.h>
17 18
@@ -171,19 +172,19 @@
171#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 172#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
172#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 173#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
173#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 174#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
174#define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 175#define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
175#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 176#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
176#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 177#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
177#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 178#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
178#define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 179#define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
179#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 180#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
180#define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 181#define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
181#define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 182#define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
182#define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 183#define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
183#define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 184#define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
184#define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 185#define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
185#define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 186#define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
186#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 187#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
187#define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 188#define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
188#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 189#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
189#define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 190#define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -198,18 +199,18 @@
198#define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 199#define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
199#define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 200#define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200#define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 201#define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201#define IP6_7_4 FM(VI1_DATA5) F_(0,0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 202#define IP6_7_4 FM(VI1_DATA5) F_(0, 0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202#define IP6_11_8 FM(VI1_DATA6) F_(0,0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 203#define IP6_11_8 FM(VI1_DATA6) F_(0, 0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203#define IP6_15_12 FM(VI1_DATA7) F_(0,0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 204#define IP6_15_12 FM(VI1_DATA7) F_(0, 0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204#define IP6_19_16 FM(VI1_DATA8) F_(0,0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 205#define IP6_19_16 FM(VI1_DATA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205#define IP6_23_20 FM(VI1_DATA9) F_(0,0) FM(RTS4_N_TANS) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 206#define IP6_23_20 FM(VI1_DATA9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206#define IP6_27_24 FM(VI1_DATA10) F_(0,0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 207#define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 208#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 209#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209#define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 210#define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210#define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 211#define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211#define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 212#define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 213#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 214#define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 215#define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 216#define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -470,7 +471,6 @@ static const u16 pinmux_data[] = {
470 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC), 471 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
471 472
472 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0), 473 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
473 PINMUX_IPSR_GPSR(IP2_27_24, CC5_OSCOUT),
474 474
475 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK), 475 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
476 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK), 476 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
@@ -496,7 +496,7 @@ static const u16 pinmux_data[] = {
496 496
497 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0), 497 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
498 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1), 498 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
499 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N_TANS), 499 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
500 PINMUX_IPSR_GPSR(IP3_15_12, HRX3), 500 PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
501 501
502 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1), 502 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
@@ -527,7 +527,7 @@ static const u16 pinmux_data[] = {
527 527
528 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7), 528 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
529 PINMUX_IPSR_GPSR(IP4_11_8, HRX1), 529 PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
530 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N_TANS), 530 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
531 531
532 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8), 532 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
533 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2), 533 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
@@ -617,7 +617,7 @@ static const u16 pinmux_data[] = {
617 PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5), 617 PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5),
618 618
619 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9), 619 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
620 PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N_TANS), 620 PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N),
621 PINMUX_IPSR_GPSR(IP6_23_20, D12), 621 PINMUX_IPSR_GPSR(IP6_23_20, D12),
622 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6), 622 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6),
623 PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1), 623 PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1),
@@ -664,7 +664,7 @@ static const u16 pinmux_data[] = {
664 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1), 664 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1),
665 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3), 665 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
666 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N), 666 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
667 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N_TANS), 667 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
668 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC), 668 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC),
669 669
670 PINMUX_IPSR_GPSR(IP7_23_20, SCL2), 670 PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
@@ -1468,7 +1468,7 @@ static const unsigned int scif0_ctrl_pins[] = {
1468 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1468 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1469}; 1469};
1470static const unsigned int scif0_ctrl_mux[] = { 1470static const unsigned int scif0_ctrl_mux[] = {
1471 RTS0_N_TANS_MARK, CTS0_N_MARK, 1471 RTS0_N_MARK, CTS0_N_MARK,
1472}; 1472};
1473 1473
1474/* - SCIF1 ------------------------------------------------------------------ */ 1474/* - SCIF1 ------------------------------------------------------------------ */
@@ -1491,7 +1491,7 @@ static const unsigned int scif1_ctrl_pins[] = {
1491 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), 1491 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1492}; 1492};
1493static const unsigned int scif1_ctrl_mux[] = { 1493static const unsigned int scif1_ctrl_mux[] = {
1494 RTS1_N_TANS_MARK, CTS1_N_MARK, 1494 RTS1_N_MARK, CTS1_N_MARK,
1495}; 1495};
1496static const unsigned int scif1_data_b_pins[] = { 1496static const unsigned int scif1_data_b_pins[] = {
1497 /* RX, TX */ 1497 /* RX, TX */
@@ -1521,7 +1521,7 @@ static const unsigned int scif3_ctrl_pins[] = {
1521 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), 1521 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1522}; 1522};
1523static const unsigned int scif3_ctrl_mux[] = { 1523static const unsigned int scif3_ctrl_mux[] = {
1524 RTS3_N_TANS_MARK, CTS3_N_MARK, 1524 RTS3_N_MARK, CTS3_N_MARK,
1525}; 1525};
1526 1526
1527/* - SCIF4 ------------------------------------------------------------------ */ 1527/* - SCIF4 ------------------------------------------------------------------ */
@@ -1544,7 +1544,7 @@ static const unsigned int scif4_ctrl_pins[] = {
1544 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), 1544 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1545}; 1545};
1546static const unsigned int scif4_ctrl_mux[] = { 1546static const unsigned int scif4_ctrl_mux[] = {
1547 RTS4_N_TANS_MARK, CTS4_N_MARK, 1547 RTS4_N_MARK, CTS4_N_MARK,
1548}; 1548};
1549 1549
1550/* - TMU -------------------------------------------------------------------- */ 1550/* - TMU -------------------------------------------------------------------- */
@@ -2072,7 +2072,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
2072static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2072static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2073#define F_(x, y) FN_##y 2073#define F_(x, y) FN_##y
2074#define FM(x) FN_##x 2074#define FM(x) FN_##x
2075 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { 2075 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
2076 0, 0, 2076 0, 0,
2077 0, 0, 2077 0, 0,
2078 0, 0, 2078 0, 0,
@@ -2104,9 +2104,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2104 GP_0_3_FN, GPSR0_3, 2104 GP_0_3_FN, GPSR0_3,
2105 GP_0_2_FN, GPSR0_2, 2105 GP_0_2_FN, GPSR0_2,
2106 GP_0_1_FN, GPSR0_1, 2106 GP_0_1_FN, GPSR0_1,
2107 GP_0_0_FN, GPSR0_0, } 2107 GP_0_0_FN, GPSR0_0, ))
2108 }, 2108 },
2109 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { 2109 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2110 0, 0, 2110 0, 0,
2111 0, 0, 2111 0, 0,
2112 0, 0, 2112 0, 0,
@@ -2138,9 +2138,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2138 GP_1_3_FN, GPSR1_3, 2138 GP_1_3_FN, GPSR1_3,
2139 GP_1_2_FN, GPSR1_2, 2139 GP_1_2_FN, GPSR1_2,
2140 GP_1_1_FN, GPSR1_1, 2140 GP_1_1_FN, GPSR1_1,
2141 GP_1_0_FN, GPSR1_0, } 2141 GP_1_0_FN, GPSR1_0, ))
2142 }, 2142 },
2143 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { 2143 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2144 0, 0, 2144 0, 0,
2145 0, 0, 2145 0, 0,
2146 0, 0, 2146 0, 0,
@@ -2172,9 +2172,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2172 GP_2_3_FN, GPSR2_3, 2172 GP_2_3_FN, GPSR2_3,
2173 GP_2_2_FN, GPSR2_2, 2173 GP_2_2_FN, GPSR2_2,
2174 GP_2_1_FN, GPSR2_1, 2174 GP_2_1_FN, GPSR2_1,
2175 GP_2_0_FN, GPSR2_0, } 2175 GP_2_0_FN, GPSR2_0, ))
2176 }, 2176 },
2177 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { 2177 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
2178 0, 0, 2178 0, 0,
2179 0, 0, 2179 0, 0,
2180 0, 0, 2180 0, 0,
@@ -2206,9 +2206,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2206 GP_3_3_FN, GPSR3_3, 2206 GP_3_3_FN, GPSR3_3,
2207 GP_3_2_FN, GPSR3_2, 2207 GP_3_2_FN, GPSR3_2,
2208 GP_3_1_FN, GPSR3_1, 2208 GP_3_1_FN, GPSR3_1,
2209 GP_3_0_FN, GPSR3_0, } 2209 GP_3_0_FN, GPSR3_0, ))
2210 }, 2210 },
2211 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { 2211 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
2212 0, 0, 2212 0, 0,
2213 0, 0, 2213 0, 0,
2214 0, 0, 2214 0, 0,
@@ -2240,9 +2240,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2240 GP_4_3_FN, GPSR4_3, 2240 GP_4_3_FN, GPSR4_3,
2241 GP_4_2_FN, GPSR4_2, 2241 GP_4_2_FN, GPSR4_2,
2242 GP_4_1_FN, GPSR4_1, 2242 GP_4_1_FN, GPSR4_1,
2243 GP_4_0_FN, GPSR4_0, } 2243 GP_4_0_FN, GPSR4_0, ))
2244 }, 2244 },
2245 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { 2245 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
2246 0, 0, 2246 0, 0,
2247 0, 0, 2247 0, 0,
2248 0, 0, 2248 0, 0,
@@ -2274,14 +2274,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2274 GP_5_3_FN, GPSR5_3, 2274 GP_5_3_FN, GPSR5_3,
2275 GP_5_2_FN, GPSR5_2, 2275 GP_5_2_FN, GPSR5_2,
2276 GP_5_1_FN, GPSR5_1, 2276 GP_5_1_FN, GPSR5_1,
2277 GP_5_0_FN, GPSR5_0, } 2277 GP_5_0_FN, GPSR5_0, ))
2278 }, 2278 },
2279#undef F_ 2279#undef F_
2280#undef FM 2280#undef FM
2281 2281
2282#define F_(x, y) x, 2282#define F_(x, y) x,
2283#define FM(x) FN_##x, 2283#define FM(x) FN_##x,
2284 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { 2284 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2285 IP0_31_28 2285 IP0_31_28
2286 IP0_27_24 2286 IP0_27_24
2287 IP0_23_20 2287 IP0_23_20
@@ -2289,9 +2289,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2289 IP0_15_12 2289 IP0_15_12
2290 IP0_11_8 2290 IP0_11_8
2291 IP0_7_4 2291 IP0_7_4
2292 IP0_3_0 } 2292 IP0_3_0 ))
2293 }, 2293 },
2294 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { 2294 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2295 IP1_31_28 2295 IP1_31_28
2296 IP1_27_24 2296 IP1_27_24
2297 IP1_23_20 2297 IP1_23_20
@@ -2299,9 +2299,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2299 IP1_15_12 2299 IP1_15_12
2300 IP1_11_8 2300 IP1_11_8
2301 IP1_7_4 2301 IP1_7_4
2302 IP1_3_0 } 2302 IP1_3_0 ))
2303 }, 2303 },
2304 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { 2304 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2305 IP2_31_28 2305 IP2_31_28
2306 IP2_27_24 2306 IP2_27_24
2307 IP2_23_20 2307 IP2_23_20
@@ -2309,9 +2309,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2309 IP2_15_12 2309 IP2_15_12
2310 IP2_11_8 2310 IP2_11_8
2311 IP2_7_4 2311 IP2_7_4
2312 IP2_3_0 } 2312 IP2_3_0 ))
2313 }, 2313 },
2314 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { 2314 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2315 IP3_31_28 2315 IP3_31_28
2316 IP3_27_24 2316 IP3_27_24
2317 IP3_23_20 2317 IP3_23_20
@@ -2319,9 +2319,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2319 IP3_15_12 2319 IP3_15_12
2320 IP3_11_8 2320 IP3_11_8
2321 IP3_7_4 2321 IP3_7_4
2322 IP3_3_0 } 2322 IP3_3_0 ))
2323 }, 2323 },
2324 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { 2324 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2325 IP4_31_28 2325 IP4_31_28
2326 IP4_27_24 2326 IP4_27_24
2327 IP4_23_20 2327 IP4_23_20
@@ -2329,9 +2329,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2329 IP4_15_12 2329 IP4_15_12
2330 IP4_11_8 2330 IP4_11_8
2331 IP4_7_4 2331 IP4_7_4
2332 IP4_3_0 } 2332 IP4_3_0 ))
2333 }, 2333 },
2334 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { 2334 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2335 IP5_31_28 2335 IP5_31_28
2336 IP5_27_24 2336 IP5_27_24
2337 IP5_23_20 2337 IP5_23_20
@@ -2339,9 +2339,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2339 IP5_15_12 2339 IP5_15_12
2340 IP5_11_8 2340 IP5_11_8
2341 IP5_7_4 2341 IP5_7_4
2342 IP5_3_0 } 2342 IP5_3_0 ))
2343 }, 2343 },
2344 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { 2344 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2345 IP6_31_28 2345 IP6_31_28
2346 IP6_27_24 2346 IP6_27_24
2347 IP6_23_20 2347 IP6_23_20
@@ -2349,9 +2349,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2349 IP6_15_12 2349 IP6_15_12
2350 IP6_11_8 2350 IP6_11_8
2351 IP6_7_4 2351 IP6_7_4
2352 IP6_3_0 } 2352 IP6_3_0 ))
2353 }, 2353 },
2354 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { 2354 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2355 IP7_31_28 2355 IP7_31_28
2356 IP7_27_24 2356 IP7_27_24
2357 IP7_23_20 2357 IP7_23_20
@@ -2359,9 +2359,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2359 IP7_15_12 2359 IP7_15_12
2360 IP7_11_8 2360 IP7_11_8
2361 IP7_7_4 2361 IP7_7_4
2362 IP7_3_0 } 2362 IP7_3_0 ))
2363 }, 2363 },
2364 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { 2364 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2365 IP8_31_28 2365 IP8_31_28
2366 IP8_27_24 2366 IP8_27_24
2367 IP8_23_20 2367 IP8_23_20
@@ -2369,7 +2369,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2369 IP8_15_12 2369 IP8_15_12
2370 IP8_11_8 2370 IP8_11_8
2371 IP8_7_4 2371 IP8_7_4
2372 IP8_3_0 } 2372 IP8_3_0 ))
2373 }, 2373 },
2374#undef F_ 2374#undef F_
2375#undef FM 2375#undef FM
@@ -2377,8 +2377,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2377#define F_(x, y) x, 2377#define F_(x, y) x,
2378#define FM(x) FN_##x, 2378#define FM(x) FN_##x,
2379 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 2379 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2380 4, 4, 4, 4, 4, 2380 GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
2381 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { 2381 1, 1, 1, 1, 1),
2382 GROUP(
2382 /* RESERVED 31, 30, 29, 28 */ 2383 /* RESERVED 31, 30, 29, 28 */
2383 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2384 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2384 /* RESERVED 27, 26, 25, 24 */ 2385 /* RESERVED 27, 26, 25, 24 */
@@ -2400,21 +2401,23 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2400 MOD_SEL0_3 2401 MOD_SEL0_3
2401 MOD_SEL0_2 2402 MOD_SEL0_2
2402 MOD_SEL0_1 2403 MOD_SEL0_1
2403 MOD_SEL0_0 } 2404 MOD_SEL0_0 ))
2404 }, 2405 },
2405 { }, 2406 { },
2406}; 2407};
2407 2408
2408enum ioctrl_regs { 2409enum ioctrl_regs {
2409 IOCTRL30, 2410 POCCTRL0,
2410 IOCTRL31, 2411 POCCTRL1,
2411 IOCTRL32, 2412 POCCTRL2,
2413 TDSELCTRL,
2412}; 2414};
2413 2415
2414static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 2416static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2415 [IOCTRL30] = { 0xe6060380 }, 2417 [POCCTRL0] = { 0xe6060380 },
2416 [IOCTRL31] = { 0xe6060384 }, 2418 [POCCTRL1] = { 0xe6060384 },
2417 [IOCTRL32] = { 0xe6060388 }, 2419 [POCCTRL2] = { 0xe6060388 },
2420 [TDSELCTRL] = { 0xe60603c0, },
2418 { /* sentinel */ }, 2421 { /* sentinel */ },
2419}; 2422};
2420 2423
@@ -2423,13 +2426,13 @@ static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
2423{ 2426{
2424 int bit = pin & 0x1f; 2427 int bit = pin & 0x1f;
2425 2428
2426 *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg; 2429 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
2427 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21)) 2430 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
2428 return bit; 2431 return bit;
2429 if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9)) 2432 if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
2430 return bit + 22; 2433 return bit + 22;
2431 2434
2432 *pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg; 2435 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
2433 if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16)) 2436 if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
2434 return bit - 10; 2437 return bit - 10;
2435 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16)) 2438 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
index b807b67ae143..473da65890a7 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
@@ -12,6 +12,7 @@
12 * Copyright (C) 2015 Renesas Electronics Corporation 12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */ 13 */
14 14
15#include <linux/errno.h>
15#include <linux/io.h> 16#include <linux/io.h>
16#include <linux/kernel.h> 17#include <linux/kernel.h>
17 18
@@ -186,7 +187,7 @@
186#define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 187#define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
187#define IP0_11_8 FM(DU_DR4) FM(TX4) FM(GETHER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 188#define IP0_11_8 FM(DU_DR4) FM(TX4) FM(GETHER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
188#define IP0_15_12 FM(DU_DR5) FM(CTS4_N) FM(GETHER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 189#define IP0_15_12 FM(DU_DR5) FM(CTS4_N) FM(GETHER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
189#define IP0_19_16 FM(DU_DR6) FM(RTS4_N_TANS) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 190#define IP0_19_16 FM(DU_DR6) FM(RTS4_N) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
190#define IP0_23_20 FM(DU_DR7) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 191#define IP0_23_20 FM(DU_DR7) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
191#define IP0_27_24 FM(DU_DG2) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 192#define IP0_27_24 FM(DU_DG2) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
192#define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 193#define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -204,19 +205,19 @@
204#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(MSIOF3_SS2) FM(GETHER_PHY_INT_B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 205#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(MSIOF3_SS2) FM(GETHER_PHY_INT_B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 206#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 207#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207#define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 208#define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 209#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 210#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 211#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211#define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 212#define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 213#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 214#define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP3_23_20 FM(VI0_DATA2) FM(AVB_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 215#define IP3_23_20 FM(VI0_DATA2) FM(AVB_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 216#define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 217#define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 218#define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 219#define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 220#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 221#define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 222#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 223#define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -242,7 +243,7 @@
242#define IP7_7_4 FM(SCL0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 243#define IP7_7_4 FM(SCL0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP7_11_8 FM(SDA0) F_(0, 0) F_(0, 0) FM(BS_N) FM(SCK0) FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 244#define IP7_11_8 FM(SDA0) F_(0, 0) F_(0, 0) FM(BS_N) FM(SCK0) FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP7_15_12 FM(SCL1) F_(0, 0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(HCTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 245#define IP7_15_12 FM(SCL1) F_(0, 0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(HCTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 246#define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP7_23_20 FM(SCL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 247#define IP7_23_20 FM(SCL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP7_27_24 FM(SDA2) F_(0, 0) F_(0, 0) FM(EX_WAIT0) FM(TX0) FM(HTX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 248#define IP7_27_24 FM(SDA2) F_(0, 0) F_(0, 0) FM(EX_WAIT0) FM(TX0) FM(HTX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP7_31_28 FM(AVB_AVTP_MATCH) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 249#define IP7_31_28 FM(AVB_AVTP_MATCH) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -469,7 +470,7 @@ static const u16 pinmux_data[] = {
469 PINMUX_IPSR_GPSR(IP0_15_12, A3), 470 PINMUX_IPSR_GPSR(IP0_15_12, A3),
470 471
471 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6), 472 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
472 PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N_TANS), 473 PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N),
473 PINMUX_IPSR_GPSR(IP0_19_16, GETHER_RMII_TXD_EN), 474 PINMUX_IPSR_GPSR(IP0_19_16, GETHER_RMII_TXD_EN),
474 PINMUX_IPSR_GPSR(IP0_19_16, A4), 475 PINMUX_IPSR_GPSR(IP0_19_16, A4),
475 476
@@ -554,7 +555,6 @@ static const u16 pinmux_data[] = {
554 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC), 555 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
555 556
556 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0), 557 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
557 PINMUX_IPSR_GPSR(IP2_27_24, CC5_OSCOUT),
558 558
559 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK), 559 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
560 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK), 560 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
@@ -580,7 +580,7 @@ static const u16 pinmux_data[] = {
580 580
581 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0), 581 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
582 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1), 582 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
583 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N_TANS), 583 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
584 PINMUX_IPSR_GPSR(IP3_15_12, HRX3), 584 PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
585 585
586 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1), 586 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
@@ -609,7 +609,7 @@ static const u16 pinmux_data[] = {
609 609
610 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7), 610 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
611 PINMUX_IPSR_GPSR(IP4_11_8, HRX1), 611 PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
612 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N_TANS), 612 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
613 613
614 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8), 614 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
615 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2), 615 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
@@ -728,7 +728,7 @@ static const u16 pinmux_data[] = {
728 PINMUX_IPSR_GPSR(IP7_19_16, SDA1), 728 PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
729 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3), 729 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
730 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N), 730 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
731 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N_TANS), 731 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
732 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_B, SEL_HSCIF0_1), 732 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_B, SEL_HSCIF0_1),
733 733
734 PINMUX_IPSR_GPSR(IP7_23_20, SCL2), 734 PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
@@ -1726,11 +1726,11 @@ static const unsigned int scif0_clk_mux[] = {
1726 SCK0_MARK, 1726 SCK0_MARK,
1727}; 1727};
1728static const unsigned int scif0_ctrl_pins[] = { 1728static const unsigned int scif0_ctrl_pins[] = {
1729 /* RTS0#/TANS, CTS0# */ 1729 /* RTS0#, CTS0# */
1730 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), 1730 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1731}; 1731};
1732static const unsigned int scif0_ctrl_mux[] = { 1732static const unsigned int scif0_ctrl_mux[] = {
1733 RTS0_N_TANS_MARK, CTS0_N_MARK, 1733 RTS0_N_MARK, CTS0_N_MARK,
1734}; 1734};
1735 1735
1736/* - SCIF1 ------------------------------------------------------------------ */ 1736/* - SCIF1 ------------------------------------------------------------------ */
@@ -1749,11 +1749,11 @@ static const unsigned int scif1_clk_mux[] = {
1749 SCK1_MARK, 1749 SCK1_MARK,
1750}; 1750};
1751static const unsigned int scif1_ctrl_pins[] = { 1751static const unsigned int scif1_ctrl_pins[] = {
1752 /* RTS1#/TANS, CTS1# */ 1752 /* RTS1#, CTS1# */
1753 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), 1753 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1754}; 1754};
1755static const unsigned int scif1_ctrl_mux[] = { 1755static const unsigned int scif1_ctrl_mux[] = {
1756 RTS1_N_TANS_MARK, CTS1_N_MARK, 1756 RTS1_N_MARK, CTS1_N_MARK,
1757}; 1757};
1758static const unsigned int scif1_data_b_pins[] = { 1758static const unsigned int scif1_data_b_pins[] = {
1759 /* RX1, TX1 */ 1759 /* RX1, TX1 */
@@ -1779,11 +1779,11 @@ static const unsigned int scif3_clk_mux[] = {
1779 SCK3_MARK, 1779 SCK3_MARK,
1780}; 1780};
1781static const unsigned int scif3_ctrl_pins[] = { 1781static const unsigned int scif3_ctrl_pins[] = {
1782 /* RTS3#/TANS, CTS3# */ 1782 /* RTS3#, CTS3# */
1783 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), 1783 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1784}; 1784};
1785static const unsigned int scif3_ctrl_mux[] = { 1785static const unsigned int scif3_ctrl_mux[] = {
1786 RTS3_N_TANS_MARK, CTS3_N_MARK, 1786 RTS3_N_MARK, CTS3_N_MARK,
1787}; 1787};
1788 1788
1789/* - SCIF4 ------------------------------------------------------------------ */ 1789/* - SCIF4 ------------------------------------------------------------------ */
@@ -1802,11 +1802,11 @@ static const unsigned int scif4_clk_mux[] = {
1802 SCK4_MARK, 1802 SCK4_MARK,
1803}; 1803};
1804static const unsigned int scif4_ctrl_pins[] = { 1804static const unsigned int scif4_ctrl_pins[] = {
1805 /* RTS4#/TANS, CTS4# */ 1805 /* RTS4#, CTS4# */
1806 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), 1806 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
1807}; 1807};
1808static const unsigned int scif4_ctrl_mux[] = { 1808static const unsigned int scif4_ctrl_mux[] = {
1809 RTS4_N_TANS_MARK, CTS4_N_MARK, 1809 RTS4_N_MARK, CTS4_N_MARK,
1810}; 1810};
1811 1811
1812/* - SCIF Clock ------------------------------------------------------------- */ 1812/* - SCIF Clock ------------------------------------------------------------- */
@@ -2474,7 +2474,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
2474static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2474static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2475#define F_(x, y) FN_##y 2475#define F_(x, y) FN_##y
2476#define FM(x) FN_##x 2476#define FM(x) FN_##x
2477 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { 2477 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
2478 0, 0, 2478 0, 0,
2479 0, 0, 2479 0, 0,
2480 0, 0, 2480 0, 0,
@@ -2506,9 +2506,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2506 GP_0_3_FN, GPSR0_3, 2506 GP_0_3_FN, GPSR0_3,
2507 GP_0_2_FN, GPSR0_2, 2507 GP_0_2_FN, GPSR0_2,
2508 GP_0_1_FN, GPSR0_1, 2508 GP_0_1_FN, GPSR0_1,
2509 GP_0_0_FN, GPSR0_0, } 2509 GP_0_0_FN, GPSR0_0, ))
2510 }, 2510 },
2511 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { 2511 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2512 0, 0, 2512 0, 0,
2513 0, 0, 2513 0, 0,
2514 0, 0, 2514 0, 0,
@@ -2540,9 +2540,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2540 GP_1_3_FN, GPSR1_3, 2540 GP_1_3_FN, GPSR1_3,
2541 GP_1_2_FN, GPSR1_2, 2541 GP_1_2_FN, GPSR1_2,
2542 GP_1_1_FN, GPSR1_1, 2542 GP_1_1_FN, GPSR1_1,
2543 GP_1_0_FN, GPSR1_0, } 2543 GP_1_0_FN, GPSR1_0, ))
2544 }, 2544 },
2545 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { 2545 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2546 0, 0, 2546 0, 0,
2547 0, 0, 2547 0, 0,
2548 GP_2_29_FN, GPSR2_29, 2548 GP_2_29_FN, GPSR2_29,
@@ -2574,9 +2574,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2574 GP_2_3_FN, GPSR2_3, 2574 GP_2_3_FN, GPSR2_3,
2575 GP_2_2_FN, GPSR2_2, 2575 GP_2_2_FN, GPSR2_2,
2576 GP_2_1_FN, GPSR2_1, 2576 GP_2_1_FN, GPSR2_1,
2577 GP_2_0_FN, GPSR2_0, } 2577 GP_2_0_FN, GPSR2_0, ))
2578 }, 2578 },
2579 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { 2579 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
2580 0, 0, 2580 0, 0,
2581 0, 0, 2581 0, 0,
2582 0, 0, 2582 0, 0,
@@ -2608,9 +2608,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2608 GP_3_3_FN, GPSR3_3, 2608 GP_3_3_FN, GPSR3_3,
2609 GP_3_2_FN, GPSR3_2, 2609 GP_3_2_FN, GPSR3_2,
2610 GP_3_1_FN, GPSR3_1, 2610 GP_3_1_FN, GPSR3_1,
2611 GP_3_0_FN, GPSR3_0, } 2611 GP_3_0_FN, GPSR3_0, ))
2612 }, 2612 },
2613 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { 2613 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
2614 0, 0, 2614 0, 0,
2615 0, 0, 2615 0, 0,
2616 0, 0, 2616 0, 0,
@@ -2642,9 +2642,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2642 GP_4_3_FN, GPSR4_3, 2642 GP_4_3_FN, GPSR4_3,
2643 GP_4_2_FN, GPSR4_2, 2643 GP_4_2_FN, GPSR4_2,
2644 GP_4_1_FN, GPSR4_1, 2644 GP_4_1_FN, GPSR4_1,
2645 GP_4_0_FN, GPSR4_0, } 2645 GP_4_0_FN, GPSR4_0, ))
2646 }, 2646 },
2647 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { 2647 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
2648 0, 0, 2648 0, 0,
2649 0, 0, 2649 0, 0,
2650 0, 0, 2650 0, 0,
@@ -2676,14 +2676,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2676 GP_5_3_FN, GPSR5_3, 2676 GP_5_3_FN, GPSR5_3,
2677 GP_5_2_FN, GPSR5_2, 2677 GP_5_2_FN, GPSR5_2,
2678 GP_5_1_FN, GPSR5_1, 2678 GP_5_1_FN, GPSR5_1,
2679 GP_5_0_FN, GPSR5_0, } 2679 GP_5_0_FN, GPSR5_0, ))
2680 }, 2680 },
2681#undef F_ 2681#undef F_
2682#undef FM 2682#undef FM
2683 2683
2684#define F_(x, y) x, 2684#define F_(x, y) x,
2685#define FM(x) FN_##x, 2685#define FM(x) FN_##x,
2686 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { 2686 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2687 IP0_31_28 2687 IP0_31_28
2688 IP0_27_24 2688 IP0_27_24
2689 IP0_23_20 2689 IP0_23_20
@@ -2691,9 +2691,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2691 IP0_15_12 2691 IP0_15_12
2692 IP0_11_8 2692 IP0_11_8
2693 IP0_7_4 2693 IP0_7_4
2694 IP0_3_0 } 2694 IP0_3_0 ))
2695 }, 2695 },
2696 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { 2696 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2697 IP1_31_28 2697 IP1_31_28
2698 IP1_27_24 2698 IP1_27_24
2699 IP1_23_20 2699 IP1_23_20
@@ -2701,9 +2701,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2701 IP1_15_12 2701 IP1_15_12
2702 IP1_11_8 2702 IP1_11_8
2703 IP1_7_4 2703 IP1_7_4
2704 IP1_3_0 } 2704 IP1_3_0 ))
2705 }, 2705 },
2706 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { 2706 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2707 IP2_31_28 2707 IP2_31_28
2708 IP2_27_24 2708 IP2_27_24
2709 IP2_23_20 2709 IP2_23_20
@@ -2711,9 +2711,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2711 IP2_15_12 2711 IP2_15_12
2712 IP2_11_8 2712 IP2_11_8
2713 IP2_7_4 2713 IP2_7_4
2714 IP2_3_0 } 2714 IP2_3_0 ))
2715 }, 2715 },
2716 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { 2716 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2717 IP3_31_28 2717 IP3_31_28
2718 IP3_27_24 2718 IP3_27_24
2719 IP3_23_20 2719 IP3_23_20
@@ -2721,9 +2721,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2721 IP3_15_12 2721 IP3_15_12
2722 IP3_11_8 2722 IP3_11_8
2723 IP3_7_4 2723 IP3_7_4
2724 IP3_3_0 } 2724 IP3_3_0 ))
2725 }, 2725 },
2726 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { 2726 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2727 IP4_31_28 2727 IP4_31_28
2728 IP4_27_24 2728 IP4_27_24
2729 IP4_23_20 2729 IP4_23_20
@@ -2731,9 +2731,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2731 IP4_15_12 2731 IP4_15_12
2732 IP4_11_8 2732 IP4_11_8
2733 IP4_7_4 2733 IP4_7_4
2734 IP4_3_0 } 2734 IP4_3_0 ))
2735 }, 2735 },
2736 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { 2736 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2737 IP5_31_28 2737 IP5_31_28
2738 IP5_27_24 2738 IP5_27_24
2739 IP5_23_20 2739 IP5_23_20
@@ -2741,9 +2741,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2741 IP5_15_12 2741 IP5_15_12
2742 IP5_11_8 2742 IP5_11_8
2743 IP5_7_4 2743 IP5_7_4
2744 IP5_3_0 } 2744 IP5_3_0 ))
2745 }, 2745 },
2746 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { 2746 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2747 IP6_31_28 2747 IP6_31_28
2748 IP6_27_24 2748 IP6_27_24
2749 IP6_23_20 2749 IP6_23_20
@@ -2751,9 +2751,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2751 IP6_15_12 2751 IP6_15_12
2752 IP6_11_8 2752 IP6_11_8
2753 IP6_7_4 2753 IP6_7_4
2754 IP6_3_0 } 2754 IP6_3_0 ))
2755 }, 2755 },
2756 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { 2756 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2757 IP7_31_28 2757 IP7_31_28
2758 IP7_27_24 2758 IP7_27_24
2759 IP7_23_20 2759 IP7_23_20
@@ -2761,9 +2761,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2761 IP7_15_12 2761 IP7_15_12
2762 IP7_11_8 2762 IP7_11_8
2763 IP7_7_4 2763 IP7_7_4
2764 IP7_3_0 } 2764 IP7_3_0 ))
2765 }, 2765 },
2766 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { 2766 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2767 IP8_31_28 2767 IP8_31_28
2768 IP8_27_24 2768 IP8_27_24
2769 IP8_23_20 2769 IP8_23_20
@@ -2771,9 +2771,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2771 IP8_15_12 2771 IP8_15_12
2772 IP8_11_8 2772 IP8_11_8
2773 IP8_7_4 2773 IP8_7_4
2774 IP8_3_0 } 2774 IP8_3_0 ))
2775 }, 2775 },
2776 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { 2776 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
2777 IP9_31_28 2777 IP9_31_28
2778 IP9_27_24 2778 IP9_27_24
2779 IP9_23_20 2779 IP9_23_20
@@ -2781,9 +2781,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2781 IP9_15_12 2781 IP9_15_12
2782 IP9_11_8 2782 IP9_11_8
2783 IP9_7_4 2783 IP9_7_4
2784 IP9_3_0 } 2784 IP9_3_0 ))
2785 }, 2785 },
2786 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { 2786 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
2787 IP10_31_28 2787 IP10_31_28
2788 IP10_27_24 2788 IP10_27_24
2789 IP10_23_20 2789 IP10_23_20
@@ -2791,7 +2791,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2791 IP10_15_12 2791 IP10_15_12
2792 IP10_11_8 2792 IP10_11_8
2793 IP10_7_4 2793 IP10_7_4
2794 IP10_3_0 } 2794 IP10_3_0 ))
2795 }, 2795 },
2796#undef F_ 2796#undef F_
2797#undef FM 2797#undef FM
@@ -2799,8 +2799,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2799#define F_(x, y) x, 2799#define F_(x, y) x,
2800#define FM(x) FN_##x, 2800#define FM(x) FN_##x,
2801 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 2801 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2802 4, 4, 4, 4, 4, 2802 GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
2803 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { 2803 1, 1, 1, 1, 1),
2804 GROUP(
2804 /* RESERVED 31, 30, 29, 28 */ 2805 /* RESERVED 31, 30, 29, 28 */
2805 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2806 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2806 /* RESERVED 27, 26, 25, 24 */ 2807 /* RESERVED 27, 26, 25, 24 */
@@ -2822,23 +2823,25 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2822 0, 0, 2823 0, 0,
2823 MOD_SEL0_2 2824 MOD_SEL0_2
2824 MOD_SEL0_1 2825 MOD_SEL0_1
2825 MOD_SEL0_0 } 2826 MOD_SEL0_0 ))
2826 }, 2827 },
2827 { }, 2828 { },
2828}; 2829};
2829 2830
2830enum ioctrl_regs { 2831enum ioctrl_regs {
2831 IOCTRL30, 2832 POCCTRL0,
2832 IOCTRL31, 2833 POCCTRL1,
2833 IOCTRL32, 2834 POCCTRL2,
2834 IOCTRL33, 2835 POCCTRL3,
2836 TDSELCTRL,
2835}; 2837};
2836 2838
2837static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 2839static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2838 [IOCTRL30] = { 0xe6060380, }, 2840 [POCCTRL0] = { 0xe6060380, },
2839 [IOCTRL31] = { 0xe6060384, }, 2841 [POCCTRL1] = { 0xe6060384, },
2840 [IOCTRL32] = { 0xe6060388, }, 2842 [POCCTRL2] = { 0xe6060388, },
2841 [IOCTRL33] = { 0xe606038c, }, 2843 [POCCTRL3] = { 0xe606038c, },
2844 [TDSELCTRL] = { 0xe60603c0, },
2842 { /* sentinel */ }, 2845 { /* sentinel */ },
2843}; 2846};
2844 2847
@@ -2847,20 +2850,20 @@ static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
2847{ 2850{
2848 int bit = pin & 0x1f; 2851 int bit = pin & 0x1f;
2849 2852
2850 *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg; 2853 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
2851 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21)) 2854 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
2852 return bit; 2855 return bit;
2853 else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9)) 2856 else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
2854 return bit + 22; 2857 return bit + 22;
2855 2858
2856 *pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg; 2859 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
2857 if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16)) 2860 if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
2858 return bit - 10; 2861 return bit - 10;
2859 if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) || 2862 if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) ||
2860 (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))) 2863 (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16)))
2861 return bit + 7; 2864 return bit + 7;
2862 2865
2863 *pocctrl = pinmux_ioctrl_regs[IOCTRL32].reg; 2866 *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
2864 if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29)) 2867 if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29))
2865 return pin - 25; 2868 return pin - 25;
2866 2869
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 151640c30e9d..91a837b02a36 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -2,7 +2,7 @@
2/* 2/*
3 * R8A77990 processor support - PFC hardware block. 3 * R8A77990 processor support - PFC hardware block.
4 * 4 *
5 * Copyright (C) 2018 Renesas Electronics Corp. 5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 * 6 *
7 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c 7 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
8 * 8 *
@@ -11,6 +11,7 @@
11 * Copyright (C) 2016-2017 Renesas Electronics Corp. 11 * Copyright (C) 2016-2017 Renesas Electronics Corp.
12 */ 12 */
13 13
14#include <linux/errno.h>
14#include <linux/kernel.h> 15#include <linux/kernel.h>
15 16
16#include "core.h" 17#include "core.h"
@@ -165,7 +166,7 @@
165#define GPSR5_7 F_(SCK2_A, IP12_7_4) 166#define GPSR5_7 F_(SCK2_A, IP12_7_4)
166#define GPSR5_6 F_(TX1, IP12_3_0) 167#define GPSR5_6 F_(TX1, IP12_3_0)
167#define GPSR5_5 F_(RX1, IP11_31_28) 168#define GPSR5_5 F_(RX1, IP11_31_28)
168#define GPSR5_4 F_(RTS0_N_TANS_A, IP11_23_20) 169#define GPSR5_4 F_(RTS0_N_A, IP11_23_20)
169#define GPSR5_3 F_(CTS0_N_A, IP11_19_16) 170#define GPSR5_3 F_(CTS0_N_A, IP11_19_16)
170#define GPSR5_2 F_(TX0_A, IP11_15_12) 171#define GPSR5_2 F_(TX0_A, IP11_15_12)
171#define GPSR5_1 F_(RX0_A, IP11_11_8) 172#define GPSR5_1 F_(RX0_A, IP11_11_8)
@@ -219,7 +220,7 @@
219#define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 220#define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 221#define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 222#define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP3_15_12 FM(A4) FM(RTS4_N_TANS_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 223#define IP3_15_12 FM(A4) FM(RTS4_N_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 224#define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 225#define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 226#define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -240,10 +241,10 @@
240#define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 241#define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 242#define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 243#define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_TANS_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 244#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 245#define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 246#define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_TANS_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 247#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 248#define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 249#define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 250#define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -289,8 +290,8 @@
289#define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290#define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291#define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292#define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP11_23_20 FM(RTS0_N_TANS_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293#define IP11_23_20 FM(RTS0_N_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N_TANS) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295#define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 296
296/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ 297/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
@@ -414,7 +415,7 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
414#define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) 415#define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
415#define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3)) 416#define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3))
416#define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0)) 417#define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0))
417#define MOD_SEL0_16 FM(SEL_NDFC_0) FM(SEL_NDFC_1) 418#define MOD_SEL0_16 FM(SEL_NDF_0) FM(SEL_NDF_1)
418#define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1) 419#define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
419#define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 420#define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
420#define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0)) 421#define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
@@ -429,8 +430,6 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
429#define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0)) 430#define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))
430 431
431/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 432/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
432#define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1)
433#define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
434#define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) 433#define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
435#define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1) 434#define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
436#define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) 435#define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
@@ -451,8 +450,7 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
451 450
452#define PINMUX_MOD_SELS \ 451#define PINMUX_MOD_SELS \
453\ 452\
454 MOD_SEL1_31 \ 453MOD_SEL0_30_29 \
455MOD_SEL0_30_29 MOD_SEL1_30 \
456 MOD_SEL1_29 \ 454 MOD_SEL1_29 \
457MOD_SEL0_28 MOD_SEL1_28 \ 455MOD_SEL0_28 MOD_SEL1_28 \
458MOD_SEL0_27_26 \ 456MOD_SEL0_27_26 \
@@ -671,7 +669,7 @@ static const u16 pinmux_data[] = {
671 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12), 669 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12),
672 670
673 PINMUX_IPSR_GPSR(IP3_15_12, A4), 671 PINMUX_IPSR_GPSR(IP3_15_12, A4),
674 PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_TANS_A, SEL_SCIF4_0), 672 PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_A, SEL_SCIF4_0),
675 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1), 673 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1),
676 PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8), 674 PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8),
677 PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1), 675 PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1),
@@ -821,7 +819,7 @@ static const u16 pinmux_data[] = {
821 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23), 819 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23),
822 PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0), 820 PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0),
823 PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7), 821 PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7),
824 PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), 822 PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_C, SEL_SCIF4_2),
825 PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7), 823 PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7),
826 824
827 PINMUX_IPSR_GPSR(IP5_31_28, D2), 825 PINMUX_IPSR_GPSR(IP5_31_28, D2),
@@ -845,7 +843,7 @@ static const u16 pinmux_data[] = {
845 PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX), 843 PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX),
846 PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1), 844 PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1),
847 PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX), 845 PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX),
848 PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_TANS_A, SEL_SCIF3_0), 846 PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_A, SEL_SCIF3_0),
849 PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A), 847 PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A),
850 PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1), 848 PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1),
851 849
@@ -984,23 +982,23 @@ static const u16 pinmux_data[] = {
984 PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2), 982 PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2),
985 983
986 PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK), 984 PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK),
987 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1), 985 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
988 986
989 PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD), 987 PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD),
990 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1), 988 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
991 989
992 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0), 990 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0),
993 PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDFC_1), 991 PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDF_1),
994 992
995 /* IPSR9 */ 993 /* IPSR9 */
996 PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1), 994 PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1),
997 PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDFC_1), 995 PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDF_1),
998 996
999 PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2), 997 PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2),
1000 PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDFC_1), 998 PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDF_1),
1001 999
1002 PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3), 1000 PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3),
1003 PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDFC_1), 1001 PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDF_1),
1004 1002
1005 PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK), 1003 PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK),
1006 PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N), 1004 PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N),
@@ -1037,57 +1035,57 @@ static const u16 pinmux_data[] = {
1037 PINMUX_IPSR_GPSR(IP10_23_20, NFCLE), 1035 PINMUX_IPSR_GPSR(IP10_23_20, NFCLE),
1038 1036
1039 PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD), 1037 PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD),
1040 PINMUX_IPSR_GPSR(IP10_27_24, NFALE_A), 1038 PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDF_0),
1041 PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD), 1039 PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD),
1042 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1), 1040 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1043 PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1), 1041 PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
1044 PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0), 1042 PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0),
1045 PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1), 1043 PINMUX_IPSR_GPSR(IP10_27_24, SSI_SCK2_B),
1046 PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0), 1044 PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),
1047 1045
1048 PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP), 1046 PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
1049 PINMUX_IPSR_GPSR(IP10_31_28, NFRB_N_A), 1047 PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDF_0),
1050 PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP), 1048 PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP),
1051 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1), 1049 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1052 PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1), 1050 PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
1053 PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0), 1051 PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0),
1054 PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1), 1052 PINMUX_IPSR_GPSR(IP10_31_28, SSI_WS2_B),
1055 PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0), 1053 PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0),
1056 1054
1057 /* IPSR11 */ 1055 /* IPSR11 */
1058 PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD), 1056 PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD),
1059 PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDFC_0), 1057 PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDF_0),
1060 PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1), 1058 PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1),
1061 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1), 1059 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1062 PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0), 1060 PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0),
1063 1061
1064 PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP), 1062 PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP),
1065 PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDFC_0), 1063 PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDF_0),
1066 PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1), 1064 PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1),
1067 PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1), 1065 PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1),
1068 PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0), 1066 PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0),
1069 1067
1070 PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0), 1068 PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0),
1071 PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0), 1069 PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0),
1072 PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0), 1070 PINMUX_IPSR_GPSR(IP11_11_8, SSI_SCK2_A),
1073 PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC), 1071 PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC),
1074 PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1), 1072 PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1),
1075 1073
1076 PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0), 1074 PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0),
1077 PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A), 1075 PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A),
1078 PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0), 1076 PINMUX_IPSR_GPSR(IP11_15_12, SSI_WS2_A),
1079 PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0), 1077 PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0),
1080 PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1), 1078 PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),
1081 1079
1082 PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0), 1080 PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0),
1083 PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDFC_0), 1081 PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDF_0),
1084 PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A), 1082 PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A),
1085 PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1), 1083 PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1),
1086 PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0), 1084 PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0),
1087 PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0), 1085 PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0),
1088 1086
1089 PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_TANS_A, SEL_SCIF0_0), 1087 PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0),
1090 PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDFC_0), 1088 PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDF_0),
1091 PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A), 1089 PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A),
1092 PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK), 1090 PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK),
1093 PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0), 1091 PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0),
@@ -1096,7 +1094,7 @@ static const u16 pinmux_data[] = {
1096 PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0), 1094 PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0),
1097 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0), 1095 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0),
1098 PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID), 1096 PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID),
1099 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS), 1097 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N),
1100 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), 1098 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1101 PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2), 1099 PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2),
1102 PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID), 1100 PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID),
@@ -1180,7 +1178,7 @@ static const u16 pinmux_data[] = {
1180 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0), 1178 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0),
1181 PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1), 1179 PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1),
1182 PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1), 1180 PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1),
1183 PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0), 1181 PINMUX_IPSR_GPSR(IP13_19_16, SIM0_D_A),
1184 1182
1185 PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT), 1183 PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT),
1186 PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1), 1184 PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1),
@@ -1248,7 +1246,7 @@ static const u16 pinmux_data[] = {
1248 PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2), 1246 PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2),
1249 PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3), 1247 PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3),
1250 PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1), 1248 PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1),
1251 PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1), 1249 PINMUX_IPSR_GPSR(IP15_15_12, SIM0_D_B),
1252 1250
1253 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6), 1251 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6),
1254 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), 1252 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
@@ -2839,7 +2837,7 @@ static const unsigned int scif0_ctrl_a_pins[] = {
2839}; 2837};
2840 2838
2841static const unsigned int scif0_ctrl_a_mux[] = { 2839static const unsigned int scif0_ctrl_a_mux[] = {
2842 RTS0_N_TANS_A_MARK, CTS0_N_A_MARK, 2840 RTS0_N_A_MARK, CTS0_N_A_MARK,
2843}; 2841};
2844 2842
2845static const unsigned int scif0_data_b_pins[] = { 2843static const unsigned int scif0_data_b_pins[] = {
@@ -2885,7 +2883,7 @@ static const unsigned int scif1_ctrl_pins[] = {
2885}; 2883};
2886 2884
2887static const unsigned int scif1_ctrl_mux[] = { 2885static const unsigned int scif1_ctrl_mux[] = {
2888 RTS1_N_TANS_MARK, CTS1_N_MARK, 2886 RTS1_N_MARK, CTS1_N_MARK,
2889}; 2887};
2890 2888
2891/* - SCIF2 ------------------------------------------------------------------ */ 2889/* - SCIF2 ------------------------------------------------------------------ */
@@ -2941,7 +2939,7 @@ static const unsigned int scif3_ctrl_a_pins[] = {
2941}; 2939};
2942 2940
2943static const unsigned int scif3_ctrl_a_mux[] = { 2941static const unsigned int scif3_ctrl_a_mux[] = {
2944 RTS3_N_TANS_A_MARK, CTS3_N_A_MARK, 2942 RTS3_N_A_MARK, CTS3_N_A_MARK,
2945}; 2943};
2946 2944
2947static const unsigned int scif3_data_b_pins[] = { 2945static const unsigned int scif3_data_b_pins[] = {
@@ -2996,7 +2994,7 @@ static const unsigned int scif4_ctrl_a_pins[] = {
2996}; 2994};
2997 2995
2998static const unsigned int scif4_ctrl_a_mux[] = { 2996static const unsigned int scif4_ctrl_a_mux[] = {
2999 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK, 2997 RTS4_N_A_MARK, CTS4_N_A_MARK,
3000}; 2998};
3001 2999
3002static const unsigned int scif4_data_b_pins[] = { 3000static const unsigned int scif4_data_b_pins[] = {
@@ -3032,7 +3030,7 @@ static const unsigned int scif4_ctrl_c_pins[] = {
3032}; 3030};
3033 3031
3034static const unsigned int scif4_ctrl_c_mux[] = { 3032static const unsigned int scif4_ctrl_c_mux[] = {
3035 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK, 3033 RTS4_N_C_MARK, CTS4_N_C_MARK,
3036}; 3034};
3037 3035
3038/* - SCIF5 ------------------------------------------------------------------ */ 3036/* - SCIF5 ------------------------------------------------------------------ */
@@ -3766,8 +3764,8 @@ static const unsigned int vin5_clk_b_mux[] = {
3766}; 3764};
3767 3765
3768static const struct { 3766static const struct {
3769 struct sh_pfc_pin_group common[245]; 3767 struct sh_pfc_pin_group common[247];
3770 struct sh_pfc_pin_group automotive[23]; 3768 struct sh_pfc_pin_group automotive[21];
3771} pinmux_groups = { 3769} pinmux_groups = {
3772 .common = { 3770 .common = {
3773 SH_PFC_PIN_GROUP(audio_clk_a), 3771 SH_PFC_PIN_GROUP(audio_clk_a),
@@ -3798,6 +3796,8 @@ static const struct {
3798 SH_PFC_PIN_GROUP(can0_data), 3796 SH_PFC_PIN_GROUP(can0_data),
3799 SH_PFC_PIN_GROUP(can1_data), 3797 SH_PFC_PIN_GROUP(can1_data),
3800 SH_PFC_PIN_GROUP(can_clk), 3798 SH_PFC_PIN_GROUP(can_clk),
3799 SH_PFC_PIN_GROUP(canfd0_data),
3800 SH_PFC_PIN_GROUP(canfd1_data),
3801 SH_PFC_PIN_GROUP(du_rgb666), 3801 SH_PFC_PIN_GROUP(du_rgb666),
3802 SH_PFC_PIN_GROUP(du_rgb888), 3802 SH_PFC_PIN_GROUP(du_rgb888),
3803 SH_PFC_PIN_GROUP(du_clk_in_0), 3803 SH_PFC_PIN_GROUP(du_clk_in_0),
@@ -4017,8 +4017,6 @@ static const struct {
4017 SH_PFC_PIN_GROUP(vin5_clk_b), 4017 SH_PFC_PIN_GROUP(vin5_clk_b),
4018 }, 4018 },
4019 .automotive = { 4019 .automotive = {
4020 SH_PFC_PIN_GROUP(canfd0_data),
4021 SH_PFC_PIN_GROUP(canfd1_data),
4022 SH_PFC_PIN_GROUP(drif0_ctrl_a), 4020 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4023 SH_PFC_PIN_GROUP(drif0_data0_a), 4021 SH_PFC_PIN_GROUP(drif0_data0_a),
4024 SH_PFC_PIN_GROUP(drif0_data1_a), 4022 SH_PFC_PIN_GROUP(drif0_data1_a),
@@ -4465,8 +4463,8 @@ static const char * const vin5_groups[] = {
4465}; 4463};
4466 4464
4467static const struct { 4465static const struct {
4468 struct sh_pfc_function common[45]; 4466 struct sh_pfc_function common[47];
4469 struct sh_pfc_function automotive[6]; 4467 struct sh_pfc_function automotive[4];
4470} pinmux_functions = { 4468} pinmux_functions = {
4471 .common = { 4469 .common = {
4472 SH_PFC_FUNCTION(audio_clk), 4470 SH_PFC_FUNCTION(audio_clk),
@@ -4474,6 +4472,8 @@ static const struct {
4474 SH_PFC_FUNCTION(can0), 4472 SH_PFC_FUNCTION(can0),
4475 SH_PFC_FUNCTION(can1), 4473 SH_PFC_FUNCTION(can1),
4476 SH_PFC_FUNCTION(can_clk), 4474 SH_PFC_FUNCTION(can_clk),
4475 SH_PFC_FUNCTION(canfd0),
4476 SH_PFC_FUNCTION(canfd1),
4477 SH_PFC_FUNCTION(du), 4477 SH_PFC_FUNCTION(du),
4478 SH_PFC_FUNCTION(hscif0), 4478 SH_PFC_FUNCTION(hscif0),
4479 SH_PFC_FUNCTION(hscif1), 4479 SH_PFC_FUNCTION(hscif1),
@@ -4516,8 +4516,6 @@ static const struct {
4516 SH_PFC_FUNCTION(vin5), 4516 SH_PFC_FUNCTION(vin5),
4517 }, 4517 },
4518 .automotive = { 4518 .automotive = {
4519 SH_PFC_FUNCTION(canfd0),
4520 SH_PFC_FUNCTION(canfd1),
4521 SH_PFC_FUNCTION(drif0), 4519 SH_PFC_FUNCTION(drif0),
4522 SH_PFC_FUNCTION(drif1), 4520 SH_PFC_FUNCTION(drif1),
4523 SH_PFC_FUNCTION(drif2), 4521 SH_PFC_FUNCTION(drif2),
@@ -4528,7 +4526,7 @@ static const struct {
4528static const struct pinmux_cfg_reg pinmux_config_regs[] = { 4526static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4529#define F_(x, y) FN_##y 4527#define F_(x, y) FN_##y
4530#define FM(x) FN_##x 4528#define FM(x) FN_##x
4531 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { 4529 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
4532 0, 0, 4530 0, 0,
4533 0, 0, 4531 0, 0,
4534 0, 0, 4532 0, 0,
@@ -4560,9 +4558,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4560 GP_0_3_FN, GPSR0_3, 4558 GP_0_3_FN, GPSR0_3,
4561 GP_0_2_FN, GPSR0_2, 4559 GP_0_2_FN, GPSR0_2,
4562 GP_0_1_FN, GPSR0_1, 4560 GP_0_1_FN, GPSR0_1,
4563 GP_0_0_FN, GPSR0_0, } 4561 GP_0_0_FN, GPSR0_0, ))
4564 }, 4562 },
4565 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { 4563 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
4566 0, 0, 4564 0, 0,
4567 0, 0, 4565 0, 0,
4568 0, 0, 4566 0, 0,
@@ -4594,9 +4592,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4594 GP_1_3_FN, GPSR1_3, 4592 GP_1_3_FN, GPSR1_3,
4595 GP_1_2_FN, GPSR1_2, 4593 GP_1_2_FN, GPSR1_2,
4596 GP_1_1_FN, GPSR1_1, 4594 GP_1_1_FN, GPSR1_1,
4597 GP_1_0_FN, GPSR1_0, } 4595 GP_1_0_FN, GPSR1_0, ))
4598 }, 4596 },
4599 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { 4597 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
4600 0, 0, 4598 0, 0,
4601 0, 0, 4599 0, 0,
4602 0, 0, 4600 0, 0,
@@ -4628,9 +4626,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4628 GP_2_3_FN, GPSR2_3, 4626 GP_2_3_FN, GPSR2_3,
4629 GP_2_2_FN, GPSR2_2, 4627 GP_2_2_FN, GPSR2_2,
4630 GP_2_1_FN, GPSR2_1, 4628 GP_2_1_FN, GPSR2_1,
4631 GP_2_0_FN, GPSR2_0, } 4629 GP_2_0_FN, GPSR2_0, ))
4632 }, 4630 },
4633 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { 4631 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
4634 0, 0, 4632 0, 0,
4635 0, 0, 4633 0, 0,
4636 0, 0, 4634 0, 0,
@@ -4662,9 +4660,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4662 GP_3_3_FN, GPSR3_3, 4660 GP_3_3_FN, GPSR3_3,
4663 GP_3_2_FN, GPSR3_2, 4661 GP_3_2_FN, GPSR3_2,
4664 GP_3_1_FN, GPSR3_1, 4662 GP_3_1_FN, GPSR3_1,
4665 GP_3_0_FN, GPSR3_0, } 4663 GP_3_0_FN, GPSR3_0, ))
4666 }, 4664 },
4667 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { 4665 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
4668 0, 0, 4666 0, 0,
4669 0, 0, 4667 0, 0,
4670 0, 0, 4668 0, 0,
@@ -4696,9 +4694,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4696 GP_4_3_FN, GPSR4_3, 4694 GP_4_3_FN, GPSR4_3,
4697 GP_4_2_FN, GPSR4_2, 4695 GP_4_2_FN, GPSR4_2,
4698 GP_4_1_FN, GPSR4_1, 4696 GP_4_1_FN, GPSR4_1,
4699 GP_4_0_FN, GPSR4_0, } 4697 GP_4_0_FN, GPSR4_0, ))
4700 }, 4698 },
4701 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { 4699 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
4702 0, 0, 4700 0, 0,
4703 0, 0, 4701 0, 0,
4704 0, 0, 4702 0, 0,
@@ -4730,9 +4728,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4730 GP_5_3_FN, GPSR5_3, 4728 GP_5_3_FN, GPSR5_3,
4731 GP_5_2_FN, GPSR5_2, 4729 GP_5_2_FN, GPSR5_2,
4732 GP_5_1_FN, GPSR5_1, 4730 GP_5_1_FN, GPSR5_1,
4733 GP_5_0_FN, GPSR5_0, } 4731 GP_5_0_FN, GPSR5_0, ))
4734 }, 4732 },
4735 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { 4733 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
4736 0, 0, 4734 0, 0,
4737 0, 0, 4735 0, 0,
4738 0, 0, 4736 0, 0,
@@ -4764,14 +4762,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4764 GP_6_3_FN, GPSR6_3, 4762 GP_6_3_FN, GPSR6_3,
4765 GP_6_2_FN, GPSR6_2, 4763 GP_6_2_FN, GPSR6_2,
4766 GP_6_1_FN, GPSR6_1, 4764 GP_6_1_FN, GPSR6_1,
4767 GP_6_0_FN, GPSR6_0, } 4765 GP_6_0_FN, GPSR6_0, ))
4768 }, 4766 },
4769#undef F_ 4767#undef F_
4770#undef FM 4768#undef FM
4771 4769
4772#define F_(x, y) x, 4770#define F_(x, y) x,
4773#define FM(x) FN_##x, 4771#define FM(x) FN_##x,
4774 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { 4772 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
4775 IP0_31_28 4773 IP0_31_28
4776 IP0_27_24 4774 IP0_27_24
4777 IP0_23_20 4775 IP0_23_20
@@ -4779,9 +4777,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4779 IP0_15_12 4777 IP0_15_12
4780 IP0_11_8 4778 IP0_11_8
4781 IP0_7_4 4779 IP0_7_4
4782 IP0_3_0 } 4780 IP0_3_0 ))
4783 }, 4781 },
4784 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { 4782 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
4785 IP1_31_28 4783 IP1_31_28
4786 IP1_27_24 4784 IP1_27_24
4787 IP1_23_20 4785 IP1_23_20
@@ -4789,9 +4787,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4789 IP1_15_12 4787 IP1_15_12
4790 IP1_11_8 4788 IP1_11_8
4791 IP1_7_4 4789 IP1_7_4
4792 IP1_3_0 } 4790 IP1_3_0 ))
4793 }, 4791 },
4794 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { 4792 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
4795 IP2_31_28 4793 IP2_31_28
4796 IP2_27_24 4794 IP2_27_24
4797 IP2_23_20 4795 IP2_23_20
@@ -4799,9 +4797,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4799 IP2_15_12 4797 IP2_15_12
4800 IP2_11_8 4798 IP2_11_8
4801 IP2_7_4 4799 IP2_7_4
4802 IP2_3_0 } 4800 IP2_3_0 ))
4803 }, 4801 },
4804 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { 4802 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
4805 IP3_31_28 4803 IP3_31_28
4806 IP3_27_24 4804 IP3_27_24
4807 IP3_23_20 4805 IP3_23_20
@@ -4809,9 +4807,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4809 IP3_15_12 4807 IP3_15_12
4810 IP3_11_8 4808 IP3_11_8
4811 IP3_7_4 4809 IP3_7_4
4812 IP3_3_0 } 4810 IP3_3_0 ))
4813 }, 4811 },
4814 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { 4812 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
4815 IP4_31_28 4813 IP4_31_28
4816 IP4_27_24 4814 IP4_27_24
4817 IP4_23_20 4815 IP4_23_20
@@ -4819,9 +4817,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4819 IP4_15_12 4817 IP4_15_12
4820 IP4_11_8 4818 IP4_11_8
4821 IP4_7_4 4819 IP4_7_4
4822 IP4_3_0 } 4820 IP4_3_0 ))
4823 }, 4821 },
4824 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { 4822 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
4825 IP5_31_28 4823 IP5_31_28
4826 IP5_27_24 4824 IP5_27_24
4827 IP5_23_20 4825 IP5_23_20
@@ -4829,9 +4827,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4829 IP5_15_12 4827 IP5_15_12
4830 IP5_11_8 4828 IP5_11_8
4831 IP5_7_4 4829 IP5_7_4
4832 IP5_3_0 } 4830 IP5_3_0 ))
4833 }, 4831 },
4834 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { 4832 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
4835 IP6_31_28 4833 IP6_31_28
4836 IP6_27_24 4834 IP6_27_24
4837 IP6_23_20 4835 IP6_23_20
@@ -4839,9 +4837,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4839 IP6_15_12 4837 IP6_15_12
4840 IP6_11_8 4838 IP6_11_8
4841 IP6_7_4 4839 IP6_7_4
4842 IP6_3_0 } 4840 IP6_3_0 ))
4843 }, 4841 },
4844 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { 4842 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
4845 IP7_31_28 4843 IP7_31_28
4846 IP7_27_24 4844 IP7_27_24
4847 IP7_23_20 4845 IP7_23_20
@@ -4849,9 +4847,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4849 IP7_15_12 4847 IP7_15_12
4850 IP7_11_8 4848 IP7_11_8
4851 IP7_7_4 4849 IP7_7_4
4852 IP7_3_0 } 4850 IP7_3_0 ))
4853 }, 4851 },
4854 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { 4852 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
4855 IP8_31_28 4853 IP8_31_28
4856 IP8_27_24 4854 IP8_27_24
4857 IP8_23_20 4855 IP8_23_20
@@ -4859,9 +4857,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4859 IP8_15_12 4857 IP8_15_12
4860 IP8_11_8 4858 IP8_11_8
4861 IP8_7_4 4859 IP8_7_4
4862 IP8_3_0 } 4860 IP8_3_0 ))
4863 }, 4861 },
4864 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { 4862 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
4865 IP9_31_28 4863 IP9_31_28
4866 IP9_27_24 4864 IP9_27_24
4867 IP9_23_20 4865 IP9_23_20
@@ -4869,9 +4867,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4869 IP9_15_12 4867 IP9_15_12
4870 IP9_11_8 4868 IP9_11_8
4871 IP9_7_4 4869 IP9_7_4
4872 IP9_3_0 } 4870 IP9_3_0 ))
4873 }, 4871 },
4874 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { 4872 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
4875 IP10_31_28 4873 IP10_31_28
4876 IP10_27_24 4874 IP10_27_24
4877 IP10_23_20 4875 IP10_23_20
@@ -4879,9 +4877,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4879 IP10_15_12 4877 IP10_15_12
4880 IP10_11_8 4878 IP10_11_8
4881 IP10_7_4 4879 IP10_7_4
4882 IP10_3_0 } 4880 IP10_3_0 ))
4883 }, 4881 },
4884 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { 4882 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
4885 IP11_31_28 4883 IP11_31_28
4886 IP11_27_24 4884 IP11_27_24
4887 IP11_23_20 4885 IP11_23_20
@@ -4889,9 +4887,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4889 IP11_15_12 4887 IP11_15_12
4890 IP11_11_8 4888 IP11_11_8
4891 IP11_7_4 4889 IP11_7_4
4892 IP11_3_0 } 4890 IP11_3_0 ))
4893 }, 4891 },
4894 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { 4892 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
4895 IP12_31_28 4893 IP12_31_28
4896 IP12_27_24 4894 IP12_27_24
4897 IP12_23_20 4895 IP12_23_20
@@ -4899,9 +4897,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4899 IP12_15_12 4897 IP12_15_12
4900 IP12_11_8 4898 IP12_11_8
4901 IP12_7_4 4899 IP12_7_4
4902 IP12_3_0 } 4900 IP12_3_0 ))
4903 }, 4901 },
4904 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { 4902 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
4905 IP13_31_28 4903 IP13_31_28
4906 IP13_27_24 4904 IP13_27_24
4907 IP13_23_20 4905 IP13_23_20
@@ -4909,9 +4907,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4909 IP13_15_12 4907 IP13_15_12
4910 IP13_11_8 4908 IP13_11_8
4911 IP13_7_4 4909 IP13_7_4
4912 IP13_3_0 } 4910 IP13_3_0 ))
4913 }, 4911 },
4914 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { 4912 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
4915 IP14_31_28 4913 IP14_31_28
4916 IP14_27_24 4914 IP14_27_24
4917 IP14_23_20 4915 IP14_23_20
@@ -4919,9 +4917,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4919 IP14_15_12 4917 IP14_15_12
4920 IP14_11_8 4918 IP14_11_8
4921 IP14_7_4 4919 IP14_7_4
4922 IP14_3_0 } 4920 IP14_3_0 ))
4923 }, 4921 },
4924 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { 4922 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
4925 IP15_31_28 4923 IP15_31_28
4926 IP15_27_24 4924 IP15_27_24
4927 IP15_23_20 4925 IP15_23_20
@@ -4929,7 +4927,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4929 IP15_15_12 4927 IP15_15_12
4930 IP15_11_8 4928 IP15_11_8
4931 IP15_7_4 4929 IP15_7_4
4932 IP15_3_0 } 4930 IP15_3_0 ))
4933 }, 4931 },
4934#undef F_ 4932#undef F_
4935#undef FM 4933#undef FM
@@ -4937,8 +4935,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4937#define F_(x, y) x, 4935#define F_(x, y) x,
4938#define FM(x) FN_##x, 4936#define FM(x) FN_##x,
4939 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 4937 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4940 1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 4938 GROUP(1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1,
4941 1, 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2) { 4939 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2),
4940 GROUP(
4942 /* RESERVED 31 */ 4941 /* RESERVED 31 */
4943 0, 0, 4942 0, 0,
4944 MOD_SEL0_30_29 4943 MOD_SEL0_30_29
@@ -4962,13 +4961,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4962 MOD_SEL0_4 4961 MOD_SEL0_4
4963 MOD_SEL0_3 4962 MOD_SEL0_3
4964 MOD_SEL0_2 4963 MOD_SEL0_2
4965 MOD_SEL0_1_0 } 4964 MOD_SEL0_1_0 ))
4966 }, 4965 },
4967 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 4966 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4968 1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 4967 GROUP(2, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 1,
4969 1, 2, 2, 2, 1, 1, 2, 1, 4) { 4968 2, 2, 2, 1, 1, 2, 1, 4),
4970 MOD_SEL1_31 4969 GROUP(
4971 MOD_SEL1_30 4970 /* RESERVED 31, 30 */
4971 0, 0, 0, 0,
4972 MOD_SEL1_29 4972 MOD_SEL1_29
4973 MOD_SEL1_28 4973 MOD_SEL1_28
4974 /* RESERVED 27 */ 4974 /* RESERVED 27 */
@@ -4989,17 +4989,19 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4989 MOD_SEL1_6_5 4989 MOD_SEL1_6_5
4990 MOD_SEL1_4 4990 MOD_SEL1_4
4991 /* RESERVED 3, 2, 1, 0 */ 4991 /* RESERVED 3, 2, 1, 0 */
4992 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 4992 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
4993 }, 4993 },
4994 { }, 4994 { },
4995}; 4995};
4996 4996
4997enum ioctrl_regs { 4997enum ioctrl_regs {
4998 IOCTRL30, 4998 POCCTRL0,
4999 TDSELCTRL,
4999}; 5000};
5000 5001
5001static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 5002static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5002 [IOCTRL30] = { 0xe6060380, }, 5003 [POCCTRL0] = { 0xe6060380, },
5004 [TDSELCTRL] = { 0xe60603c0, },
5003 { /* sentinel */ }, 5005 { /* sentinel */ },
5004}; 5006};
5005 5007
@@ -5008,7 +5010,7 @@ static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
5008{ 5010{
5009 int bit = -EINVAL; 5011 int bit = -EINVAL;
5010 5012
5011 *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg; 5013 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
5012 5014
5013 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) 5015 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5014 bit = pin & 0x1f; 5016 bit = pin & 0x1f;
@@ -5124,7 +5126,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5124 } }, 5126 } },
5125 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { 5127 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5126 [0] = RCAR_GP_PIN(5, 0), /* SCK0_A */ 5128 [0] = RCAR_GP_PIN(5, 0), /* SCK0_A */
5127 [1] = RCAR_GP_PIN(5, 4), /* RTS0#/TANS_A */ 5129 [1] = RCAR_GP_PIN(5, 4), /* RTS0#_A */
5128 [2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */ 5130 [2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */
5129 [3] = RCAR_GP_PIN(5, 2), /* TX0_A */ 5131 [3] = RCAR_GP_PIN(5, 2), /* TX0_A */
5130 [4] = RCAR_GP_PIN(5, 1), /* RX0_A */ 5132 [4] = RCAR_GP_PIN(5, 1), /* RX0_A */
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
index 9e377e3b9cb3..dd87085d48cb 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
@@ -11,6 +11,7 @@
11 * Copyright (C) 2015 Renesas Electronics Corporation 11 * Copyright (C) 2015 Renesas Electronics Corporation
12 */ 12 */
13 13
14#include <linux/errno.h>
14#include <linux/kernel.h> 15#include <linux/kernel.h>
15 16
16#include "core.h" 17#include "core.h"
@@ -287,7 +288,7 @@
287#define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 288#define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 289#define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290#define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP11_3_0 FM(SDA1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291#define IP11_3_0 FM(SDA1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292#define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293#define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294#define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -298,7 +299,7 @@
298 299
299/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 300/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
300#define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301#define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP12_7_4 FM(TX1_A) FM(RTS0_N_TANS) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302#define IP12_7_4 FM(TX1_A) FM(RTS0_N) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303#define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304#define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305#define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -857,7 +858,7 @@ static const u16 pinmux_data[] = {
857 858
858 /* IPSR11 */ 859 /* IPSR11 */
859 PINMUX_IPSR_GPSR(IP11_3_0, SDA1), 860 PINMUX_IPSR_GPSR(IP11_3_0, SDA1),
860 PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N_TANS), 861 PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N),
861 862
862 PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK), 863 PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK),
863 PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1), 864 PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1),
@@ -892,7 +893,7 @@ static const u16 pinmux_data[] = {
892 PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B), 893 PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B),
893 894
894 PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0), 895 PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0),
895 PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N_TANS), 896 PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N),
896 PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B), 897 PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B),
897 898
898 PINMUX_IPSR_GPSR(IP12_11_8, SCK2), 899 PINMUX_IPSR_GPSR(IP12_11_8, SCK2),
@@ -1704,7 +1705,7 @@ static const unsigned int scif0_ctrl_pins[] = {
1704 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23), 1705 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
1705}; 1706};
1706static const unsigned int scif0_ctrl_mux[] = { 1707static const unsigned int scif0_ctrl_mux[] = {
1707 RTS0_N_TANS_MARK, CTS0_N_MARK, 1708 RTS0_N_MARK, CTS0_N_MARK,
1708}; 1709};
1709/* - SCIF1 ------------------------------------------------------------------ */ 1710/* - SCIF1 ------------------------------------------------------------------ */
1710static const unsigned int scif1_data_a_pins[] = { 1711static const unsigned int scif1_data_a_pins[] = {
@@ -1740,7 +1741,7 @@ static const unsigned int scif1_ctrl_pins[] = {
1740 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10), 1741 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1741}; 1742};
1742static const unsigned int scif1_ctrl_mux[] = { 1743static const unsigned int scif1_ctrl_mux[] = {
1743 RTS1_N_TANS_MARK, CTS1_N_MARK, 1744 RTS1_N_MARK, CTS1_N_MARK,
1744}; 1745};
1745 1746
1746/* - SCIF2 ------------------------------------------------------------------ */ 1747/* - SCIF2 ------------------------------------------------------------------ */
@@ -2374,7 +2375,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
2374static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2375static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2375#define F_(x, y) FN_##y 2376#define F_(x, y) FN_##y
2376#define FM(x) FN_##x 2377#define FM(x) FN_##x
2377 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { 2378 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
2378 0, 0, 2379 0, 0,
2379 0, 0, 2380 0, 0,
2380 0, 0, 2381 0, 0,
@@ -2406,9 +2407,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2406 GP_0_3_FN, GPSR0_3, 2407 GP_0_3_FN, GPSR0_3,
2407 GP_0_2_FN, GPSR0_2, 2408 GP_0_2_FN, GPSR0_2,
2408 GP_0_1_FN, GPSR0_1, 2409 GP_0_1_FN, GPSR0_1,
2409 GP_0_0_FN, GPSR0_0, } 2410 GP_0_0_FN, GPSR0_0, ))
2410 }, 2411 },
2411 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { 2412 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2412 GP_1_31_FN, GPSR1_31, 2413 GP_1_31_FN, GPSR1_31,
2413 GP_1_30_FN, GPSR1_30, 2414 GP_1_30_FN, GPSR1_30,
2414 GP_1_29_FN, GPSR1_29, 2415 GP_1_29_FN, GPSR1_29,
@@ -2440,9 +2441,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2440 GP_1_3_FN, GPSR1_3, 2441 GP_1_3_FN, GPSR1_3,
2441 GP_1_2_FN, GPSR1_2, 2442 GP_1_2_FN, GPSR1_2,
2442 GP_1_1_FN, GPSR1_1, 2443 GP_1_1_FN, GPSR1_1,
2443 GP_1_0_FN, GPSR1_0, } 2444 GP_1_0_FN, GPSR1_0, ))
2444 }, 2445 },
2445 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { 2446 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2446 GP_2_31_FN, GPSR2_31, 2447 GP_2_31_FN, GPSR2_31,
2447 GP_2_30_FN, GPSR2_30, 2448 GP_2_30_FN, GPSR2_30,
2448 GP_2_29_FN, GPSR2_29, 2449 GP_2_29_FN, GPSR2_29,
@@ -2474,9 +2475,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2474 GP_2_3_FN, GPSR2_3, 2475 GP_2_3_FN, GPSR2_3,
2475 GP_2_2_FN, GPSR2_2, 2476 GP_2_2_FN, GPSR2_2,
2476 GP_2_1_FN, GPSR2_1, 2477 GP_2_1_FN, GPSR2_1,
2477 GP_2_0_FN, GPSR2_0, } 2478 GP_2_0_FN, GPSR2_0, ))
2478 }, 2479 },
2479 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { 2480 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
2480 0, 0, 2481 0, 0,
2481 0, 0, 2482 0, 0,
2482 0, 0, 2483 0, 0,
@@ -2508,9 +2509,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2508 GP_3_3_FN, GPSR3_3, 2509 GP_3_3_FN, GPSR3_3,
2509 GP_3_2_FN, GPSR3_2, 2510 GP_3_2_FN, GPSR3_2,
2510 GP_3_1_FN, GPSR3_1, 2511 GP_3_1_FN, GPSR3_1,
2511 GP_3_0_FN, GPSR3_0, } 2512 GP_3_0_FN, GPSR3_0, ))
2512 }, 2513 },
2513 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { 2514 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
2514 GP_4_31_FN, GPSR4_31, 2515 GP_4_31_FN, GPSR4_31,
2515 GP_4_30_FN, GPSR4_30, 2516 GP_4_30_FN, GPSR4_30,
2516 GP_4_29_FN, GPSR4_29, 2517 GP_4_29_FN, GPSR4_29,
@@ -2542,9 +2543,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2542 GP_4_3_FN, GPSR4_3, 2543 GP_4_3_FN, GPSR4_3,
2543 GP_4_2_FN, GPSR4_2, 2544 GP_4_2_FN, GPSR4_2,
2544 GP_4_1_FN, GPSR4_1, 2545 GP_4_1_FN, GPSR4_1,
2545 GP_4_0_FN, GPSR4_0, } 2546 GP_4_0_FN, GPSR4_0, ))
2546 }, 2547 },
2547 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { 2548 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
2548 0, 0, 2549 0, 0,
2549 0, 0, 2550 0, 0,
2550 0, 0, 2551 0, 0,
@@ -2576,9 +2577,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2576 GP_5_3_FN, GPSR5_3, 2577 GP_5_3_FN, GPSR5_3,
2577 GP_5_2_FN, GPSR5_2, 2578 GP_5_2_FN, GPSR5_2,
2578 GP_5_1_FN, GPSR5_1, 2579 GP_5_1_FN, GPSR5_1,
2579 GP_5_0_FN, GPSR5_0, } 2580 GP_5_0_FN, GPSR5_0, ))
2580 }, 2581 },
2581 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { 2582 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
2582 0, 0, 2583 0, 0,
2583 0, 0, 2584 0, 0,
2584 0, 0, 2585 0, 0,
@@ -2610,14 +2611,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2610 GP_6_3_FN, GPSR6_3, 2611 GP_6_3_FN, GPSR6_3,
2611 GP_6_2_FN, GPSR6_2, 2612 GP_6_2_FN, GPSR6_2,
2612 GP_6_1_FN, GPSR6_1, 2613 GP_6_1_FN, GPSR6_1,
2613 GP_6_0_FN, GPSR6_0, } 2614 GP_6_0_FN, GPSR6_0, ))
2614 }, 2615 },
2615#undef F_ 2616#undef F_
2616#undef FM 2617#undef FM
2617 2618
2618#define F_(x, y) x, 2619#define F_(x, y) x,
2619#define FM(x) FN_##x, 2620#define FM(x) FN_##x,
2620 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { 2621 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2621 IP0_31_28 2622 IP0_31_28
2622 IP0_27_24 2623 IP0_27_24
2623 IP0_23_20 2624 IP0_23_20
@@ -2625,9 +2626,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2625 IP0_15_12 2626 IP0_15_12
2626 IP0_11_8 2627 IP0_11_8
2627 IP0_7_4 2628 IP0_7_4
2628 IP0_3_0 } 2629 IP0_3_0 ))
2629 }, 2630 },
2630 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { 2631 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2631 IP1_31_28 2632 IP1_31_28
2632 IP1_27_24 2633 IP1_27_24
2633 IP1_23_20 2634 IP1_23_20
@@ -2635,9 +2636,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2635 IP1_15_12 2636 IP1_15_12
2636 IP1_11_8 2637 IP1_11_8
2637 IP1_7_4 2638 IP1_7_4
2638 IP1_3_0 } 2639 IP1_3_0 ))
2639 }, 2640 },
2640 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { 2641 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2641 IP2_31_28 2642 IP2_31_28
2642 IP2_27_24 2643 IP2_27_24
2643 IP2_23_20 2644 IP2_23_20
@@ -2645,9 +2646,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2645 IP2_15_12 2646 IP2_15_12
2646 IP2_11_8 2647 IP2_11_8
2647 IP2_7_4 2648 IP2_7_4
2648 IP2_3_0 } 2649 IP2_3_0 ))
2649 }, 2650 },
2650 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { 2651 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2651 IP3_31_28 2652 IP3_31_28
2652 IP3_27_24 2653 IP3_27_24
2653 IP3_23_20 2654 IP3_23_20
@@ -2655,9 +2656,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2655 IP3_15_12 2656 IP3_15_12
2656 IP3_11_8 2657 IP3_11_8
2657 IP3_7_4 2658 IP3_7_4
2658 IP3_3_0 } 2659 IP3_3_0 ))
2659 }, 2660 },
2660 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { 2661 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2661 IP4_31_28 2662 IP4_31_28
2662 IP4_27_24 2663 IP4_27_24
2663 IP4_23_20 2664 IP4_23_20
@@ -2665,9 +2666,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2665 IP4_15_12 2666 IP4_15_12
2666 IP4_11_8 2667 IP4_11_8
2667 IP4_7_4 2668 IP4_7_4
2668 IP4_3_0 } 2669 IP4_3_0 ))
2669 }, 2670 },
2670 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { 2671 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2671 IP5_31_28 2672 IP5_31_28
2672 IP5_27_24 2673 IP5_27_24
2673 IP5_23_20 2674 IP5_23_20
@@ -2675,9 +2676,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2675 IP5_15_12 2676 IP5_15_12
2676 IP5_11_8 2677 IP5_11_8
2677 IP5_7_4 2678 IP5_7_4
2678 IP5_3_0 } 2679 IP5_3_0 ))
2679 }, 2680 },
2680 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { 2681 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2681 IP6_31_28 2682 IP6_31_28
2682 IP6_27_24 2683 IP6_27_24
2683 IP6_23_20 2684 IP6_23_20
@@ -2685,9 +2686,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2685 IP6_15_12 2686 IP6_15_12
2686 IP6_11_8 2687 IP6_11_8
2687 IP6_7_4 2688 IP6_7_4
2688 IP6_3_0 } 2689 IP6_3_0 ))
2689 }, 2690 },
2690 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { 2691 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2691 IP7_31_28 2692 IP7_31_28
2692 IP7_27_24 2693 IP7_27_24
2693 IP7_23_20 2694 IP7_23_20
@@ -2695,9 +2696,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2695 IP7_15_12 2696 IP7_15_12
2696 IP7_11_8 2697 IP7_11_8
2697 IP7_7_4 2698 IP7_7_4
2698 IP7_3_0 } 2699 IP7_3_0 ))
2699 }, 2700 },
2700 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { 2701 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2701 IP8_31_28 2702 IP8_31_28
2702 IP8_27_24 2703 IP8_27_24
2703 IP8_23_20 2704 IP8_23_20
@@ -2705,9 +2706,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2705 IP8_15_12 2706 IP8_15_12
2706 IP8_11_8 2707 IP8_11_8
2707 IP8_7_4 2708 IP8_7_4
2708 IP8_3_0 } 2709 IP8_3_0 ))
2709 }, 2710 },
2710 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { 2711 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
2711 IP9_31_28 2712 IP9_31_28
2712 IP9_27_24 2713 IP9_27_24
2713 IP9_23_20 2714 IP9_23_20
@@ -2715,9 +2716,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2715 IP9_15_12 2716 IP9_15_12
2716 IP9_11_8 2717 IP9_11_8
2717 IP9_7_4 2718 IP9_7_4
2718 IP9_3_0 } 2719 IP9_3_0 ))
2719 }, 2720 },
2720 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { 2721 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
2721 IP10_31_28 2722 IP10_31_28
2722 IP10_27_24 2723 IP10_27_24
2723 IP10_23_20 2724 IP10_23_20
@@ -2725,9 +2726,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2725 IP10_15_12 2726 IP10_15_12
2726 IP10_11_8 2727 IP10_11_8
2727 IP10_7_4 2728 IP10_7_4
2728 IP10_3_0 } 2729 IP10_3_0 ))
2729 }, 2730 },
2730 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { 2731 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
2731 IP11_31_28 2732 IP11_31_28
2732 IP11_27_24 2733 IP11_27_24
2733 IP11_23_20 2734 IP11_23_20
@@ -2735,9 +2736,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2735 IP11_15_12 2736 IP11_15_12
2736 IP11_11_8 2737 IP11_11_8
2737 IP11_7_4 2738 IP11_7_4
2738 IP11_3_0 } 2739 IP11_3_0 ))
2739 }, 2740 },
2740 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { 2741 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
2741 IP12_31_28 2742 IP12_31_28
2742 IP12_27_24 2743 IP12_27_24
2743 IP12_23_20 2744 IP12_23_20
@@ -2745,9 +2746,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2745 IP12_15_12 2746 IP12_15_12
2746 IP12_11_8 2747 IP12_11_8
2747 IP12_7_4 2748 IP12_7_4
2748 IP12_3_0 } 2749 IP12_3_0 ))
2749 }, 2750 },
2750 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { 2751 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
2751 /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2752 /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2752 /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2753 /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2753 /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2754 /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2755,7 +2756,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2755 /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2756 /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2756 /* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2757 /* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2757 IP13_7_4 2758 IP13_7_4
2758 IP13_3_0 } 2759 IP13_3_0 ))
2759 }, 2760 },
2760#undef F_ 2761#undef F_
2761#undef FM 2762#undef FM
@@ -2763,8 +2764,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2763#define F_(x, y) x, 2764#define F_(x, y) x,
2764#define FM(x) FN_##x, 2765#define FM(x) FN_##x,
2765 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, 2766 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2766 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1, 2767 GROUP(1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
2767 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1) { 2768 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1),
2769 GROUP(
2768 /* RESERVED 31 */ 2770 /* RESERVED 31 */
2769 0, 0, 2771 0, 0,
2770 MOD_SEL0_30 2772 MOD_SEL0_30
@@ -2792,11 +2794,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2792 MOD_SEL0_3 2794 MOD_SEL0_3
2793 MOD_SEL0_2 2795 MOD_SEL0_2
2794 MOD_SEL0_1 2796 MOD_SEL0_1
2795 MOD_SEL0_0 } 2797 MOD_SEL0_0 ))
2796 }, 2798 },
2797 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, 2799 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2798 1, 1, 1, 1, 1, 1, 2, 4, 4, 2800 GROUP(1, 1, 1, 1, 1, 1, 2, 4, 4, 4, 4, 4, 4),
2799 4, 4, 4, 4) { 2801 GROUP(
2800 MOD_SEL1_31 2802 MOD_SEL1_31
2801 MOD_SEL1_30 2803 MOD_SEL1_30
2802 MOD_SEL1_29 2804 MOD_SEL1_29
@@ -2816,7 +2818,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2816 /* RESERVED 7, 6, 5, 4 */ 2818 /* RESERVED 7, 6, 5, 4 */
2817 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2819 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2818 /* RESERVED 3, 2, 1, 0 */ 2820 /* RESERVED 3, 2, 1, 0 */
2819 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 2821 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
2820 }, 2822 },
2821 { }, 2823 { },
2822}; 2824};
@@ -2833,6 +2835,15 @@ static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po
2833 return bit; 2835 return bit;
2834} 2836}
2835 2837
2838enum ioctrl_regs {
2839 TDSELCTRL,
2840};
2841
2842static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2843 [TDSELCTRL] = { 0xe60603c0, },
2844 { /* sentinel */ },
2845};
2846
2836static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = { 2847static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
2837 .pin_to_pocctrl = r8a77995_pin_to_pocctrl, 2848 .pin_to_pocctrl = r8a77995_pin_to_pocctrl,
2838}; 2849};
@@ -2852,6 +2863,7 @@ const struct sh_pfc_soc_info r8a77995_pinmux_info = {
2852 .nr_functions = ARRAY_SIZE(pinmux_functions), 2863 .nr_functions = ARRAY_SIZE(pinmux_functions),
2853 2864
2854 .cfg_regs = pinmux_config_regs, 2865 .cfg_regs = pinmux_config_regs,
2866 .ioctrl_regs = pinmux_ioctrl_regs,
2855 2867
2856 .pinmux_data = pinmux_data, 2868 .pinmux_data = pinmux_data,
2857 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 2869 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
index 9ee468a9bd0e..811a6f2cb1fc 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
@@ -1073,7 +1073,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
1073}; 1073};
1074 1074
1075static const struct pinmux_cfg_reg pinmux_config_regs[] = { 1075static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1076 { PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1) { 1076 { PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1, GROUP(
1077 0, 0, 1077 0, 0,
1078 0, 0, 1078 0, 0,
1079 0, 0, 1079 0, 0,
@@ -1089,9 +1089,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1089 0, 0, 1089 0, 0,
1090 0, 0, 1090 0, 0,
1091 0, 0, 1091 0, 0,
1092 0, 0 } 1092 0, 0 ))
1093 }, 1093 },
1094 { PINMUX_CFG_REG("PBCRL4", 0xfffe3890, 16, 4) { 1094 { PINMUX_CFG_REG("PBCRL4", 0xfffe3890, 16, 4, GROUP(
1095 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1095 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1096 1096
1097 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1097 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1099,9 +1099,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1099 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1099 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1100 1100
1101 PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11, 1101 PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11,
1102 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1102 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
1103 }, 1103 },
1104 { PINMUX_CFG_REG("PBCRL3", 0xfffe3892, 16, 4) { 1104 { PINMUX_CFG_REG("PBCRL3", 0xfffe3892, 16, 4, GROUP(
1105 PB11MD_0, PB11MD_1, 1105 PB11MD_0, PB11MD_1,
1106 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1106 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1107 1107
@@ -1112,9 +1112,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1112 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1112 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1113 1113
1114 PB8MD_00, PB8MD_01, PB8MD_10, 0, 1114 PB8MD_00, PB8MD_01, PB8MD_10, 0,
1115 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1115 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
1116 }, 1116 },
1117 { PINMUX_CFG_REG("PBCRL2", 0xfffe3894, 16, 4) { 1117 { PINMUX_CFG_REG("PBCRL2", 0xfffe3894, 16, 4, GROUP(
1118 PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11, 1118 PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11,
1119 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1119 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1120 1120
@@ -1125,9 +1125,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1125 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1125 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1126 1126
1127 PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11, 1127 PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11,
1128 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1128 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
1129 }, 1129 },
1130 { PINMUX_CFG_REG("PBCRL1", 0xfffe3896, 16, 4) { 1130 { PINMUX_CFG_REG("PBCRL1", 0xfffe3896, 16, 4, GROUP(
1131 PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11, 1131 PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11,
1132 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1132 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1133 1133
@@ -1138,9 +1138,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1138 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1138 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1139 1139
1140 PB0MD_00, PB0MD_01, PB0MD_10, PB0MD_11, 1140 PB0MD_00, PB0MD_01, PB0MD_10, PB0MD_11,
1141 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1141 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
1142 }, 1142 },
1143 { PINMUX_CFG_REG("IFCR", 0xfffe38a2, 16, 4) { 1143 { PINMUX_CFG_REG("IFCR", 0xfffe38a2, 16, 4, GROUP(
1144 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1144 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1145 1145
1146 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1146 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1148,9 +1148,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1148 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1148 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1149 1149
1150 PB12IRQ_00, PB12IRQ_01, PB12IRQ_10, 0, 1150 PB12IRQ_00, PB12IRQ_01, PB12IRQ_10, 0,
1151 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1151 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
1152 }, 1152 },
1153 { PINMUX_CFG_REG("PCIORL", 0xfffe3906, 16, 1) { 1153 { PINMUX_CFG_REG("PCIORL", 0xfffe3906, 16, 1, GROUP(
1154 0, 0, 1154 0, 0,
1155 PC14_IN, PC14_OUT, 1155 PC14_IN, PC14_OUT,
1156 PC13_IN, PC13_OUT, 1156 PC13_IN, PC13_OUT,
@@ -1166,9 +1166,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1166 PC3_IN, PC3_OUT, 1166 PC3_IN, PC3_OUT,
1167 PC2_IN, PC2_OUT, 1167 PC2_IN, PC2_OUT,
1168 PC1_IN, PC1_OUT, 1168 PC1_IN, PC1_OUT,
1169 PC0_IN, PC0_OUT } 1169 PC0_IN, PC0_OUT ))
1170 }, 1170 },
1171 { PINMUX_CFG_REG("PCCRL4", 0xfffe3910, 16, 4) { 1171 { PINMUX_CFG_REG("PCCRL4", 0xfffe3910, 16, 4, GROUP(
1172 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1172 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1173 1173
1174 PC14MD_0, PC14MD_1, 1174 PC14MD_0, PC14MD_1,
@@ -1178,9 +1178,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1178 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1178 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1179 1179
1180 PC12MD_0, PC12MD_1, 1180 PC12MD_0, PC12MD_1,
1181 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1181 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
1182 }, 1182 },
1183 { PINMUX_CFG_REG("PCCRL3", 0xfffe3912, 16, 4) { 1183 { PINMUX_CFG_REG("PCCRL3", 0xfffe3912, 16, 4, GROUP(
1184 PC11MD_00, PC11MD_01, PC11MD_10, 0, 1184 PC11MD_00, PC11MD_01, PC11MD_10, 0,
1185 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1185 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1186 1186
@@ -1191,9 +1191,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1191 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1191 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1192 1192
1193 PC8MD_0, PC8MD_1, 1193 PC8MD_0, PC8MD_1,
1194 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1194 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
1195 }, 1195 },
1196 { PINMUX_CFG_REG("PCCRL2", 0xfffe3914, 16, 4) { 1196 { PINMUX_CFG_REG("PCCRL2", 0xfffe3914, 16, 4, GROUP(
1197 PC7MD_0, PC7MD_1, 1197 PC7MD_0, PC7MD_1,
1198 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1198 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1199 1199
@@ -1204,9 +1204,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1204 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1204 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1205 1205
1206 PC4MD_0, PC4MD_1, 1206 PC4MD_0, PC4MD_1,
1207 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1207 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
1208 }, 1208 },
1209 { PINMUX_CFG_REG("PCCRL1", 0xfffe3916, 16, 4) { 1209 { PINMUX_CFG_REG("PCCRL1", 0xfffe3916, 16, 4, GROUP(
1210 PC3MD_0, PC3MD_1, 1210 PC3MD_0, PC3MD_1,
1211 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1211 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1212 1212
@@ -1217,9 +1217,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1217 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1217 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1218 1218
1219 PC0MD_00, PC0MD_01, PC0MD_10, 0, 1219 PC0MD_00, PC0MD_01, PC0MD_10, 0,
1220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
1221 }, 1221 },
1222 { PINMUX_CFG_REG("PDIORL", 0xfffe3986, 16, 1) { 1222 { PINMUX_CFG_REG("PDIORL", 0xfffe3986, 16, 1, GROUP(
1223 PD15_IN, PD15_OUT, 1223 PD15_IN, PD15_OUT,
1224 PD14_IN, PD14_OUT, 1224 PD14_IN, PD14_OUT,
1225 PD13_IN, PD13_OUT, 1225 PD13_IN, PD13_OUT,
@@ -1235,9 +1235,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1235 PD3_IN, PD3_OUT, 1235 PD3_IN, PD3_OUT,
1236 PD2_IN, PD2_OUT, 1236 PD2_IN, PD2_OUT,
1237 PD1_IN, PD1_OUT, 1237 PD1_IN, PD1_OUT,
1238 PD0_IN, PD0_OUT } 1238 PD0_IN, PD0_OUT ))
1239 }, 1239 },
1240 { PINMUX_CFG_REG("PDCRL4", 0xfffe3990, 16, 4) { 1240 { PINMUX_CFG_REG("PDCRL4", 0xfffe3990, 16, 4, GROUP(
1241 PD15MD_000, PD15MD_001, PD15MD_010, 0, 1241 PD15MD_000, PD15MD_001, PD15MD_010, 0,
1242 PD15MD_100, PD15MD_101, 0, 0, 1242 PD15MD_100, PD15MD_101, 0, 0,
1243 0, 0, 0, 0, 0, 0, 0, 0, 1243 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1252,9 +1252,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1252 1252
1253 PD12MD_000, PD12MD_001, PD12MD_010, 0, 1253 PD12MD_000, PD12MD_001, PD12MD_010, 0,
1254 PD12MD_100, PD12MD_101, 0, 0, 1254 PD12MD_100, PD12MD_101, 0, 0,
1255 0, 0, 0, 0, 0, 0, 0, 0 } 1255 0, 0, 0, 0, 0, 0, 0, 0 ))
1256 }, 1256 },
1257 { PINMUX_CFG_REG("PDCRL3", 0xfffe3992, 16, 4) { 1257 { PINMUX_CFG_REG("PDCRL3", 0xfffe3992, 16, 4, GROUP(
1258 PD11MD_000, PD11MD_001, PD11MD_010, 0, 1258 PD11MD_000, PD11MD_001, PD11MD_010, 0,
1259 PD11MD_100, PD11MD_101, 0, 0, 1259 PD11MD_100, PD11MD_101, 0, 0,
1260 0, 0, 0, 0, 0, 0, 0, 0, 1260 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1269,9 +1269,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1269 1269
1270 PD8MD_000, PD8MD_001, PD8MD_010, 0, 1270 PD8MD_000, PD8MD_001, PD8MD_010, 0,
1271 PD8MD_100, PD8MD_101, 0, 0, 1271 PD8MD_100, PD8MD_101, 0, 0,
1272 0, 0, 0, 0, 0, 0, 0, 0 } 1272 0, 0, 0, 0, 0, 0, 0, 0 ))
1273 }, 1273 },
1274 { PINMUX_CFG_REG("PDCRL2", 0xfffe3994, 16, 4) { 1274 { PINMUX_CFG_REG("PDCRL2", 0xfffe3994, 16, 4, GROUP(
1275 PD7MD_000, PD7MD_001, PD7MD_010, PD7MD_011, 1275 PD7MD_000, PD7MD_001, PD7MD_010, PD7MD_011,
1276 PD7MD_100, PD7MD_101, 0, 0, 1276 PD7MD_100, PD7MD_101, 0, 0,
1277 0, 0, 0, 0, 0, 0, 0, 0, 1277 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1286,9 +1286,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1286 1286
1287 PD4MD_000, PD4MD_001, PD4MD_010, PD4MD_011, 1287 PD4MD_000, PD4MD_001, PD4MD_010, PD4MD_011,
1288 PD4MD_100, PD4MD_101, 0, 0, 1288 PD4MD_100, PD4MD_101, 0, 0,
1289 0, 0, 0, 0, 0, 0, 0, 0 } 1289 0, 0, 0, 0, 0, 0, 0, 0 ))
1290 }, 1290 },
1291 { PINMUX_CFG_REG("PDCRL1", 0xfffe3996, 16, 4) { 1291 { PINMUX_CFG_REG("PDCRL1", 0xfffe3996, 16, 4, GROUP(
1292 PD3MD_000, PD3MD_001, PD3MD_010, PD3MD_011, 1292 PD3MD_000, PD3MD_001, PD3MD_010, PD3MD_011,
1293 PD3MD_100, PD3MD_101, 0, 0, 1293 PD3MD_100, PD3MD_101, 0, 0,
1294 0, 0, 0, 0, 0, 0, 0, 0, 1294 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1303,9 +1303,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1303 1303
1304 PD0MD_000, PD0MD_001, PD0MD_010, PD0MD_011, 1304 PD0MD_000, PD0MD_001, PD0MD_010, PD0MD_011,
1305 PD0MD_100, PD0MD_101, 0, 0, 1305 PD0MD_100, PD0MD_101, 0, 0,
1306 0, 0, 0, 0, 0, 0, 0, 0 } 1306 0, 0, 0, 0, 0, 0, 0, 0 ))
1307 }, 1307 },
1308 { PINMUX_CFG_REG("PEIORL", 0xfffe3a06, 16, 1) { 1308 { PINMUX_CFG_REG("PEIORL", 0xfffe3a06, 16, 1, GROUP(
1309 PE15_IN, PE15_OUT, 1309 PE15_IN, PE15_OUT,
1310 PE14_IN, PE14_OUT, 1310 PE14_IN, PE14_OUT,
1311 PE13_IN, PE13_OUT, 1311 PE13_IN, PE13_OUT,
@@ -1321,9 +1321,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1321 PE3_IN, PE3_OUT, 1321 PE3_IN, PE3_OUT,
1322 PE2_IN, PE2_OUT, 1322 PE2_IN, PE2_OUT,
1323 PE1_IN, PE1_OUT, 1323 PE1_IN, PE1_OUT,
1324 PE0_IN, PE0_OUT } 1324 PE0_IN, PE0_OUT ))
1325 }, 1325 },
1326 { PINMUX_CFG_REG("PECRL4", 0xfffe3a10, 16, 4) { 1326 { PINMUX_CFG_REG("PECRL4", 0xfffe3a10, 16, 4, GROUP(
1327 PE15MD_00, PE15MD_01, 0, PE15MD_11, 1327 PE15MD_00, PE15MD_01, 0, PE15MD_11,
1328 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1328 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1329 1329
@@ -1334,9 +1334,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1334 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1334 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1335 1335
1336 PE12MD_00, 0, 0, PE12MD_11, 1336 PE12MD_00, 0, 0, PE12MD_11,
1337 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1337 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
1338 }, 1338 },
1339 { PINMUX_CFG_REG("PECRL3", 0xfffe3a12, 16, 4) { 1339 { PINMUX_CFG_REG("PECRL3", 0xfffe3a12, 16, 4, GROUP(
1340 PE11MD_000, PE11MD_001, PE11MD_010, 0, 1340 PE11MD_000, PE11MD_001, PE11MD_010, 0,
1341 PE11MD_100, 0, 0, 0, 1341 PE11MD_100, 0, 0, 0,
1342 0, 0, 0, 0, 0, 0, 0, 0, 1342 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1349,9 +1349,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1349 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1349 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1350 1350
1351 PE8MD_00, PE8MD_01, PE8MD_10, PE8MD_11, 1351 PE8MD_00, PE8MD_01, PE8MD_10, PE8MD_11,
1352 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1352 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
1353 }, 1353 },
1354 { PINMUX_CFG_REG("PECRL2", 0xfffe3a14, 16, 4) { 1354 { PINMUX_CFG_REG("PECRL2", 0xfffe3a14, 16, 4, GROUP(
1355 PE7MD_000, PE7MD_001, PE7MD_010, PE7MD_011, 1355 PE7MD_000, PE7MD_001, PE7MD_010, PE7MD_011,
1356 PE7MD_100, 0, 0, 0, 1356 PE7MD_100, 0, 0, 0,
1357 0, 0, 0, 0, 0, 0, 0, 0, 1357 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1366,9 +1366,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1366 1366
1367 PE4MD_000, PE4MD_001, PE4MD_010, PE4MD_011, 1367 PE4MD_000, PE4MD_001, PE4MD_010, PE4MD_011,
1368 PE4MD_100, 0, 0, 0, 1368 PE4MD_100, 0, 0, 0,
1369 0, 0, 0, 0, 0, 0, 0, 0 } 1369 0, 0, 0, 0, 0, 0, 0, 0 ))
1370 }, 1370 },
1371 { PINMUX_CFG_REG("PECRL1", 0xfffe3a16, 16, 4) { 1371 { PINMUX_CFG_REG("PECRL1", 0xfffe3a16, 16, 4, GROUP(
1372 PE3MD_00, PE3MD_01, 0, PE3MD_11, 1372 PE3MD_00, PE3MD_01, 0, PE3MD_11,
1373 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1373 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1374 1374
@@ -1380,9 +1380,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1380 1380
1381 PE0MD_000, PE0MD_001, 0, PE0MD_011, 1381 PE0MD_000, PE0MD_001, 0, PE0MD_011,
1382 PE0MD_100, 0, 0, 0, 1382 PE0MD_100, 0, 0, 0,
1383 0, 0, 0, 0, 0, 0, 0, 0 } 1383 0, 0, 0, 0, 0, 0, 0, 0 ))
1384 }, 1384 },
1385 { PINMUX_CFG_REG("PFIORH", 0xfffe3a84, 16, 1) { 1385 { PINMUX_CFG_REG("PFIORH", 0xfffe3a84, 16, 1, GROUP(
1386 0, 0, 1386 0, 0,
1387 PF30_IN, PF30_OUT, 1387 PF30_IN, PF30_OUT,
1388 PF29_IN, PF29_OUT, 1388 PF29_IN, PF29_OUT,
@@ -1398,9 +1398,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1398 PF19_IN, PF19_OUT, 1398 PF19_IN, PF19_OUT,
1399 PF18_IN, PF18_OUT, 1399 PF18_IN, PF18_OUT,
1400 PF17_IN, PF17_OUT, 1400 PF17_IN, PF17_OUT,
1401 PF16_IN, PF16_OUT } 1401 PF16_IN, PF16_OUT ))
1402 }, 1402 },
1403 { PINMUX_CFG_REG("PFIORL", 0xfffe3a86, 16, 1) { 1403 { PINMUX_CFG_REG("PFIORL", 0xfffe3a86, 16, 1, GROUP(
1404 PF15_IN, PF15_OUT, 1404 PF15_IN, PF15_OUT,
1405 PF14_IN, PF14_OUT, 1405 PF14_IN, PF14_OUT,
1406 PF13_IN, PF13_OUT, 1406 PF13_IN, PF13_OUT,
@@ -1416,9 +1416,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1416 PF3_IN, PF3_OUT, 1416 PF3_IN, PF3_OUT,
1417 PF2_IN, PF2_OUT, 1417 PF2_IN, PF2_OUT,
1418 PF1_IN, PF1_OUT, 1418 PF1_IN, PF1_OUT,
1419 PF0_IN, PF0_OUT } 1419 PF0_IN, PF0_OUT ))
1420 }, 1420 },
1421 { PINMUX_CFG_REG("PFCRH4", 0xfffe3a88, 16, 4) { 1421 { PINMUX_CFG_REG("PFCRH4", 0xfffe3a88, 16, 4, GROUP(
1422 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1422 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1423 1423
1424 PF30MD_0, PF30MD_1, 1424 PF30MD_0, PF30MD_1,
@@ -1428,9 +1428,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1428 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1428 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1429 1429
1430 PF28MD_0, PF28MD_1, 1430 PF28MD_0, PF28MD_1,
1431 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1431 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
1432 }, 1432 },
1433 { PINMUX_CFG_REG("PFCRH3", 0xfffe3a8a, 16, 4) { 1433 { PINMUX_CFG_REG("PFCRH3", 0xfffe3a8a, 16, 4, GROUP(
1434 PF27MD_0, PF27MD_1, 1434 PF27MD_0, PF27MD_1,
1435 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1435 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1436 1436
@@ -1441,9 +1441,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1441 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1441 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1442 1442
1443 PF24MD_0, PF24MD_1, 1443 PF24MD_0, PF24MD_1,
1444 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1444 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
1445 }, 1445 },
1446 { PINMUX_CFG_REG("PFCRH2", 0xfffe3a8c, 16, 4) { 1446 { PINMUX_CFG_REG("PFCRH2", 0xfffe3a8c, 16, 4, GROUP(
1447 PF23MD_00, PF23MD_01, PF23MD_10, 0, 1447 PF23MD_00, PF23MD_01, PF23MD_10, 0,
1448 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1448 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1449 1449
@@ -1454,9 +1454,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1454 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1454 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1455 1455
1456 PF20MD_00, PF20MD_01, PF20MD_10, 0, 1456 PF20MD_00, PF20MD_01, PF20MD_10, 0,
1457 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1457 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
1458 }, 1458 },
1459 { PINMUX_CFG_REG("PFCRH1", 0xfffe3a8e, 16, 4) { 1459 { PINMUX_CFG_REG("PFCRH1", 0xfffe3a8e, 16, 4, GROUP(
1460 PF19MD_00, PF19MD_01, PF19MD_10, 0, 1460 PF19MD_00, PF19MD_01, PF19MD_10, 0,
1461 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1461 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1462 1462
@@ -1467,9 +1467,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1467 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1467 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1468 1468
1469 PF16MD_00, PF16MD_01, PF16MD_10, 0, 1469 PF16MD_00, PF16MD_01, PF16MD_10, 0,
1470 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1470 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
1471 }, 1471 },
1472 { PINMUX_CFG_REG("PFCRL4", 0xfffe3a90, 16, 4) { 1472 { PINMUX_CFG_REG("PFCRL4", 0xfffe3a90, 16, 4, GROUP(
1473 PF15MD_00, PF15MD_01, PF15MD_10, 0, 1473 PF15MD_00, PF15MD_01, PF15MD_10, 0,
1474 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1474 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1475 1475
@@ -1480,9 +1480,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1480 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1480 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1481 1481
1482 PF12MD_00, PF12MD_01, PF12MD_10, 0, 1482 PF12MD_00, PF12MD_01, PF12MD_10, 0,
1483 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1483 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
1484 }, 1484 },
1485 { PINMUX_CFG_REG("PFCRL3", 0xfffe3a92, 16, 4) { 1485 { PINMUX_CFG_REG("PFCRL3", 0xfffe3a92, 16, 4, GROUP(
1486 PF11MD_00, PF11MD_01, PF11MD_10, 0, 1486 PF11MD_00, PF11MD_01, PF11MD_10, 0,
1487 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1487 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1488 1488
@@ -1493,9 +1493,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1493 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1493 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1494 1494
1495 PF8MD_00, PF8MD_01, PF8MD_10, 0, 1495 PF8MD_00, PF8MD_01, PF8MD_10, 0,
1496 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1496 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
1497 }, 1497 },
1498 { PINMUX_CFG_REG("PFCRL2", 0xfffe3a94, 16, 4) { 1498 { PINMUX_CFG_REG("PFCRL2", 0xfffe3a94, 16, 4, GROUP(
1499 PF7MD_00, PF7MD_01, PF7MD_10, PF7MD_11, 1499 PF7MD_00, PF7MD_01, PF7MD_10, PF7MD_11,
1500 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1500 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1501 1501
@@ -1506,9 +1506,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1506 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1506 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1507 1507
1508 PF4MD_00, PF4MD_01, PF4MD_10, PF4MD_11, 1508 PF4MD_00, PF4MD_01, PF4MD_10, PF4MD_11,
1509 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1509 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
1510 }, 1510 },
1511 { PINMUX_CFG_REG("PFCRL1", 0xfffe3a96, 16, 4) { 1511 { PINMUX_CFG_REG("PFCRL1", 0xfffe3a96, 16, 4, GROUP(
1512 PF3MD_00, PF3MD_01, PF3MD_10, PF3MD_11, 1512 PF3MD_00, PF3MD_01, PF3MD_10, PF3MD_11,
1513 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1513 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1514 1514
@@ -1519,53 +1519,53 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1519 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1519 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1520 1520
1521 PF0MD_00, PF0MD_01, PF0MD_10, PF0MD_11, 1521 PF0MD_00, PF0MD_01, PF0MD_10, PF0MD_11,
1522 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1522 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
1523 }, 1523 },
1524 {} 1524 {}
1525}; 1525};
1526 1526
1527static const struct pinmux_data_reg pinmux_data_regs[] = { 1527static const struct pinmux_data_reg pinmux_data_regs[] = {
1528 { PINMUX_DATA_REG("PADRL", 0xfffe3802, 16) { 1528 { PINMUX_DATA_REG("PADRL", 0xfffe3802, 16, GROUP(
1529 0, 0, 0, 0, 1529 0, 0, 0, 0,
1530 0, 0, 0, 0, 1530 0, 0, 0, 0,
1531 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, 1531 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
1532 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA } 1532 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA ))
1533 }, 1533 },
1534 { PINMUX_DATA_REG("PBDRL", 0xfffe3882, 16) { 1534 { PINMUX_DATA_REG("PBDRL", 0xfffe3882, 16, GROUP(
1535 0, 0, 0, PB12_DATA, 1535 0, 0, 0, PB12_DATA,
1536 PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA, 1536 PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
1537 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, 1537 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
1538 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA } 1538 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA ))
1539 }, 1539 },
1540 { PINMUX_DATA_REG("PCDRL", 0xfffe3902, 16) { 1540 { PINMUX_DATA_REG("PCDRL", 0xfffe3902, 16, GROUP(
1541 0, PC14_DATA, PC13_DATA, PC12_DATA, 1541 0, PC14_DATA, PC13_DATA, PC12_DATA,
1542 PC11_DATA, PC10_DATA, PC9_DATA, PC8_DATA, 1542 PC11_DATA, PC10_DATA, PC9_DATA, PC8_DATA,
1543 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, 1543 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
1544 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA } 1544 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
1545 }, 1545 },
1546 { PINMUX_DATA_REG("PDDRL", 0xfffe3982, 16) { 1546 { PINMUX_DATA_REG("PDDRL", 0xfffe3982, 16, GROUP(
1547 PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA, 1547 PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
1548 PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA, 1548 PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
1549 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, 1549 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
1550 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA } 1550 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
1551 }, 1551 },
1552 { PINMUX_DATA_REG("PEDRL", 0xfffe3a02, 16) { 1552 { PINMUX_DATA_REG("PEDRL", 0xfffe3a02, 16, GROUP(
1553 PE15_DATA, PE14_DATA, PE13_DATA, PE12_DATA, 1553 PE15_DATA, PE14_DATA, PE13_DATA, PE12_DATA,
1554 PE11_DATA, PE10_DATA, PE9_DATA, PE8_DATA, 1554 PE11_DATA, PE10_DATA, PE9_DATA, PE8_DATA,
1555 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA, 1555 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
1556 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA } 1556 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA ))
1557 }, 1557 },
1558 { PINMUX_DATA_REG("PFDRH", 0xfffe3a80, 16) { 1558 { PINMUX_DATA_REG("PFDRH", 0xfffe3a80, 16, GROUP(
1559 0, PF30_DATA, PF29_DATA, PF28_DATA, 1559 0, PF30_DATA, PF29_DATA, PF28_DATA,
1560 PF27_DATA, PF26_DATA, PF25_DATA, PF24_DATA, 1560 PF27_DATA, PF26_DATA, PF25_DATA, PF24_DATA,
1561 PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA, 1561 PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA,
1562 PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA } 1562 PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA ))
1563 }, 1563 },
1564 { PINMUX_DATA_REG("PFDRL", 0xfffe3a82, 16) { 1564 { PINMUX_DATA_REG("PFDRL", 0xfffe3a82, 16, GROUP(
1565 PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA, 1565 PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA,
1566 PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA, 1566 PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
1567 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, 1567 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
1568 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA } 1568 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
1569 }, 1569 },
1570 { }, 1570 { },
1571}; 1571};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
index 501de63e6c5f..4a95867deb8a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
@@ -1466,17 +1466,17 @@ static const struct pinmux_func pinmux_func_gpios[] = {
1466}; 1466};
1467 1467
1468static const struct pinmux_cfg_reg pinmux_config_regs[] = { 1468static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1469 { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) { 1469 { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1, GROUP(
1470 0, 0, 0, 0, 0, 0, 0, 0, 1470 0, 0, 0, 0, 0, 0, 0, 0,
1471 0, 0, 0, 0, 0, 0, 0, 0, 1471 0, 0, 0, 0, 0, 0, 0, 0,
1472 0, 0, 0, 0, 0, 0, 0, 0, 1472 0, 0, 0, 0, 0, 0, 0, 0,
1473 PA3_IN, PA3_OUT, 1473 PA3_IN, PA3_OUT,
1474 PA2_IN, PA2_OUT, 1474 PA2_IN, PA2_OUT,
1475 PA1_IN, PA1_OUT, 1475 PA1_IN, PA1_OUT,
1476 PA0_IN, PA0_OUT } 1476 PA0_IN, PA0_OUT ))
1477 }, 1477 },
1478 1478
1479 { PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4) { 1479 { PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4, GROUP(
1480 0, 0, 0, 0, 0, 0, 0, 0, 1480 0, 0, 0, 0, 0, 0, 0, 0,
1481 0, 0, 0, 0, 0, 0, 0, 0, 1481 0, 0, 0, 0, 0, 0, 0, 0,
1482 PB22MD_00, PB22MD_01, PB22MD_10, 0, 0, 0, 0, 0, 1482 PB22MD_00, PB22MD_01, PB22MD_10, 0, 0, 0, 0, 0,
@@ -1484,10 +1484,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1484 PB21MD_0, PB21MD_1, 0, 0, 0, 0, 0, 0, 1484 PB21MD_0, PB21MD_1, 0, 0, 0, 0, 0, 0,
1485 0, 0, 0, 0, 0, 0, 0, 0, 1485 0, 0, 0, 0, 0, 0, 0, 0,
1486 0, PB20MD_1, 0, 0, 0, 0, 0, 0, 1486 0, PB20MD_1, 0, 0, 0, 0, 0, 0,
1487 0, 0, 0, 0, 0, 0, 0, 0 } 1487 0, 0, 0, 0, 0, 0, 0, 0 ))
1488 1488
1489 }, 1489 },
1490 { PINMUX_CFG_REG("PBCR4", 0xfffe3826, 16, 4) { 1490 { PINMUX_CFG_REG("PBCR4", 0xfffe3826, 16, 4, GROUP(
1491 0, PB19MD_01, 0, 0, 0, 0, 0, 0, 1491 0, PB19MD_01, 0, 0, 0, 0, 0, 0,
1492 0, 0, 0, 0, 0, 0, 0, 0, 1492 0, 0, 0, 0, 0, 0, 0, 0,
1493 0, PB18MD_01, 0, 0, 0, 0, 0, 0, 1493 0, PB18MD_01, 0, 0, 0, 0, 0, 0,
@@ -1495,9 +1495,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1495 0, PB17MD_01, 0, 0, 0, 0, 0, 0, 1495 0, PB17MD_01, 0, 0, 0, 0, 0, 0,
1496 0, 0, 0, 0, 0, 0, 0, 0, 1496 0, 0, 0, 0, 0, 0, 0, 0,
1497 0, PB16MD_01, 0, 0, 0, 0, 0, 0, 1497 0, PB16MD_01, 0, 0, 0, 0, 0, 0,
1498 0, 0, 0, 0, 0, 0, 0, 0 } 1498 0, 0, 0, 0, 0, 0, 0, 0 ))
1499 }, 1499 },
1500 { PINMUX_CFG_REG("PBCR3", 0xfffe3828, 16, 4) { 1500 { PINMUX_CFG_REG("PBCR3", 0xfffe3828, 16, 4, GROUP(
1501 0, PB15MD_01, 0, 0, 0, 0, 0, 0, 1501 0, PB15MD_01, 0, 0, 0, 0, 0, 0,
1502 0, 0, 0, 0, 0, 0, 0, 0, 1502 0, 0, 0, 0, 0, 0, 0, 0,
1503 0, PB14MD_01, 0, 0, 0, 0, 0, 0, 1503 0, PB14MD_01, 0, 0, 0, 0, 0, 0,
@@ -1505,9 +1505,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1505 0, PB13MD_01, 0, 0, 0, 0, 0, 0, 1505 0, PB13MD_01, 0, 0, 0, 0, 0, 0,
1506 0, 0, 0, 0, 0, 0, 0, 0, 1506 0, 0, 0, 0, 0, 0, 0, 0,
1507 0, PB12MD_01, 0, 0, 0, 0, 0, 0, 1507 0, PB12MD_01, 0, 0, 0, 0, 0, 0,
1508 0, 0, 0, 0, 0, 0, 0, 0 } 1508 0, 0, 0, 0, 0, 0, 0, 0 ))
1509 }, 1509 },
1510 { PINMUX_CFG_REG("PBCR2", 0xfffe382a, 16, 4) { 1510 { PINMUX_CFG_REG("PBCR2", 0xfffe382a, 16, 4, GROUP(
1511 0, PB11MD_01, 0, 0, 0, 0, 0, 0, 1511 0, PB11MD_01, 0, 0, 0, 0, 0, 0,
1512 0, 0, 0, 0, 0, 0, 0, 0, 1512 0, 0, 0, 0, 0, 0, 0, 0,
1513 0, PB10MD_01, 0, 0, 0, 0, 0, 0, 1513 0, PB10MD_01, 0, 0, 0, 0, 0, 0,
@@ -1515,9 +1515,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1515 0, PB9MD_01, 0, 0, 0, 0, 0, 0, 1515 0, PB9MD_01, 0, 0, 0, 0, 0, 0,
1516 0, 0, 0, 0, 0, 0, 0, 0, 1516 0, 0, 0, 0, 0, 0, 0, 0,
1517 0, PB8MD_01, 0, 0, 0, 0, 0, 0, 1517 0, PB8MD_01, 0, 0, 0, 0, 0, 0,
1518 0, 0, 0, 0, 0, 0, 0, 0 } 1518 0, 0, 0, 0, 0, 0, 0, 0 ))
1519 }, 1519 },
1520 { PINMUX_CFG_REG("PBCR1", 0xfffe382c, 16, 4) { 1520 { PINMUX_CFG_REG("PBCR1", 0xfffe382c, 16, 4, GROUP(
1521 0, PB7MD_01, 0, 0, 0, 0, 0, 0, 1521 0, PB7MD_01, 0, 0, 0, 0, 0, 0,
1522 0, 0, 0, 0, 0, 0, 0, 0, 1522 0, 0, 0, 0, 0, 0, 0, 0,
1523 0, PB6MD_01, 0, 0, 0, 0, 0, 0, 1523 0, PB6MD_01, 0, 0, 0, 0, 0, 0,
@@ -1525,9 +1525,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1525 0, PB5MD_01, 0, 0, 0, 0, 0, 0, 1525 0, PB5MD_01, 0, 0, 0, 0, 0, 0,
1526 0, 0, 0, 0, 0, 0, 0, 0, 1526 0, 0, 0, 0, 0, 0, 0, 0,
1527 0, PB4MD_01, 0, 0, 0, 0, 0, 0, 1527 0, PB4MD_01, 0, 0, 0, 0, 0, 0,
1528 0, 0, 0, 0, 0, 0, 0, 0 } 1528 0, 0, 0, 0, 0, 0, 0, 0 ))
1529 }, 1529 },
1530 { PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4) { 1530 { PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4, GROUP(
1531 0, PB3MD_1, 0, 0, 0, 0, 0, 0, 1531 0, PB3MD_1, 0, 0, 0, 0, 0, 0,
1532 0, 0, 0, 0, 0, 0, 0, 0, 1532 0, 0, 0, 0, 0, 0, 0, 0,
1533 0, PB2MD_1, 0, 0, 0, 0, 0, 0, 1533 0, PB2MD_1, 0, 0, 0, 0, 0, 0,
@@ -1535,10 +1535,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1535 0, PB1MD_1, 0, 0, 0, 0, 0, 0, 1535 0, PB1MD_1, 0, 0, 0, 0, 0, 0,
1536 0, 0, 0, 0, 0, 0, 0, 0, 1536 0, 0, 0, 0, 0, 0, 0, 0,
1537 0, 0, 0, 0, 0, 0, 0, 0, 1537 0, 0, 0, 0, 0, 0, 0, 0,
1538 0, 0, 0, 0, 0, 0, 0, 0 } 1538 0, 0, 0, 0, 0, 0, 0, 0 ))
1539 }, 1539 },
1540 1540
1541 { PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1) { 1541 { PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1, GROUP(
1542 0, 0, 0, 0, 0, 0, 0, 0, 1542 0, 0, 0, 0, 0, 0, 0, 0,
1543 0, 0, 0, 0, 0, 0, 0, 0, 1543 0, 0, 0, 0, 0, 0, 0, 0,
1544 0, 0, 1544 0, 0,
@@ -1548,10 +1548,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1548 PB19_IN, PB19_OUT, 1548 PB19_IN, PB19_OUT,
1549 PB18_IN, PB18_OUT, 1549 PB18_IN, PB18_OUT,
1550 PB17_IN, PB17_OUT, 1550 PB17_IN, PB17_OUT,
1551 PB16_IN, PB16_OUT } 1551 PB16_IN, PB16_OUT ))
1552 }, 1552 },
1553 1553
1554 { PINMUX_CFG_REG("PBIOR0", 0xfffe3832, 16, 1) { 1554 { PINMUX_CFG_REG("PBIOR0", 0xfffe3832, 16, 1, GROUP(
1555 PB15_IN, PB15_OUT, 1555 PB15_IN, PB15_OUT,
1556 PB14_IN, PB14_OUT, 1556 PB14_IN, PB14_OUT,
1557 PB13_IN, PB13_OUT, 1557 PB13_IN, PB13_OUT,
@@ -1567,10 +1567,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1567 PB3_IN, PB3_OUT, 1567 PB3_IN, PB3_OUT,
1568 PB2_IN, PB2_OUT, 1568 PB2_IN, PB2_OUT,
1569 PB1_IN, PB1_OUT, 1569 PB1_IN, PB1_OUT,
1570 0, 0 } 1570 0, 0 ))
1571 }, 1571 },
1572 1572
1573 { PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4) { 1573 { PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4, GROUP(
1574 0, 0, 0, 0, 0, 0, 0, 0, 1574 0, 0, 0, 0, 0, 0, 0, 0,
1575 0, 0, 0, 0, 0, 0, 0, 0, 1575 0, 0, 0, 0, 0, 0, 0, 0,
1576 PC10MD_0, PC10MD_1, 0, 0, 0, 0, 0, 0, 1576 PC10MD_0, PC10MD_1, 0, 0, 0, 0, 0, 0,
@@ -1578,9 +1578,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1578 PC9MD_0, PC9MD_1, 0, 0, 0, 0, 0, 0, 1578 PC9MD_0, PC9MD_1, 0, 0, 0, 0, 0, 0,
1579 0, 0, 0, 0, 0, 0, 0, 0, 1579 0, 0, 0, 0, 0, 0, 0, 0,
1580 PC8MD_00, PC8MD_01, PC8MD_10, PC8MD_11, 0, 0, 0, 0, 1580 PC8MD_00, PC8MD_01, PC8MD_10, PC8MD_11, 0, 0, 0, 0,
1581 0, 0, 0, 0, 0, 0, 0, 0 } 1581 0, 0, 0, 0, 0, 0, 0, 0 ))
1582 }, 1582 },
1583 { PINMUX_CFG_REG("PCCR1", 0xfffe384c, 16, 4) { 1583 { PINMUX_CFG_REG("PCCR1", 0xfffe384c, 16, 4, GROUP(
1584 PC7MD_00, PC7MD_01, PC7MD_10, PC7MD_11, 0, 0, 0, 0, 1584 PC7MD_00, PC7MD_01, PC7MD_10, PC7MD_11, 0, 0, 0, 0,
1585 0, 0, 0, 0, 0, 0, 0, 0, 1585 0, 0, 0, 0, 0, 0, 0, 0,
1586 PC6MD_00, PC6MD_01, PC6MD_10, PC6MD_11, 0, 0, 0, 0, 1586 PC6MD_00, PC6MD_01, PC6MD_10, PC6MD_11, 0, 0, 0, 0,
@@ -1588,9 +1588,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1588 PC5MD_00, PC5MD_01, PC5MD_10, PC5MD_11, 0, 0, 0, 0, 1588 PC5MD_00, PC5MD_01, PC5MD_10, PC5MD_11, 0, 0, 0, 0,
1589 0, 0, 0, 0, 0, 0, 0, 0, 1589 0, 0, 0, 0, 0, 0, 0, 0,
1590 PC4MD_0, PC4MD_1, 0, 0, 0, 0, 0, 0, 1590 PC4MD_0, PC4MD_1, 0, 0, 0, 0, 0, 0,
1591 0, 0, 0, 0, 0, 0, 0, 0 } 1591 0, 0, 0, 0, 0, 0, 0, 0 ))
1592 }, 1592 },
1593 { PINMUX_CFG_REG("PCCR0", 0xfffe384e, 16, 4) { 1593 { PINMUX_CFG_REG("PCCR0", 0xfffe384e, 16, 4, GROUP(
1594 PC3MD_0, PC3MD_1, 0, 0, 0, 0, 0, 0, 1594 PC3MD_0, PC3MD_1, 0, 0, 0, 0, 0, 0,
1595 0, 0, 0, 0, 0, 0, 0, 0, 1595 0, 0, 0, 0, 0, 0, 0, 0,
1596 PC2MD_0, PC2MD_1, 0, 0, 0, 0, 0, 0, 1596 PC2MD_0, PC2MD_1, 0, 0, 0, 0, 0, 0,
@@ -1598,10 +1598,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1598 PC1MD_0, PC1MD_1, 0, 0, 0, 0, 0, 0, 1598 PC1MD_0, PC1MD_1, 0, 0, 0, 0, 0, 0,
1599 0, 0, 0, 0, 0, 0, 0, 0, 1599 0, 0, 0, 0, 0, 0, 0, 0,
1600 PC0MD_0, PC0MD_1, 0, 0, 0, 0, 0, 0, 1600 PC0MD_0, PC0MD_1, 0, 0, 0, 0, 0, 0,
1601 0, 0, 0, 0, 0, 0, 0, 0 } 1601 0, 0, 0, 0, 0, 0, 0, 0 ))
1602 }, 1602 },
1603 1603
1604 { PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1) { 1604 { PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1, GROUP(
1605 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1605 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1606 PC10_IN, PC10_OUT, 1606 PC10_IN, PC10_OUT,
1607 PC9_IN, PC9_OUT, 1607 PC9_IN, PC9_OUT,
@@ -1614,10 +1614,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1614 PC2_IN, PC2_OUT, 1614 PC2_IN, PC2_OUT,
1615 PC1_IN, PC1_OUT, 1615 PC1_IN, PC1_OUT,
1616 PC0_IN, PC0_OUT 1616 PC0_IN, PC0_OUT
1617 } 1617 ))
1618 }, 1618 },
1619 1619
1620 { PINMUX_CFG_REG("PDCR3", 0xfffe3868, 16, 4) { 1620 { PINMUX_CFG_REG("PDCR3", 0xfffe3868, 16, 4, GROUP(
1621 0, PD15MD_01, 0, 0, 0, 0, 0, 0, 1621 0, PD15MD_01, 0, 0, 0, 0, 0, 0,
1622 0, 0, 0, 0, 0, 0, 0, 0, 1622 0, 0, 0, 0, 0, 0, 0, 0,
1623 0, PD14MD_01, 0, 0, 0, 0, 0, 0, 1623 0, PD14MD_01, 0, 0, 0, 0, 0, 0,
@@ -1625,9 +1625,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1625 0, PD13MD_01, 0, 0, 0, 0, 0, 0, 1625 0, PD13MD_01, 0, 0, 0, 0, 0, 0,
1626 0, 0, 0, 0, 0, 0, 0, 0, 1626 0, 0, 0, 0, 0, 0, 0, 0,
1627 0, PD12MD_01, 0, 0, 0, 0, 0, 0, 1627 0, PD12MD_01, 0, 0, 0, 0, 0, 0,
1628 0, 0, 0, 0, 0, 0, 0, 0 } 1628 0, 0, 0, 0, 0, 0, 0, 0 ))
1629 }, 1629 },
1630 { PINMUX_CFG_REG("PDCR2", 0xfffe386a, 16, 4) { 1630 { PINMUX_CFG_REG("PDCR2", 0xfffe386a, 16, 4, GROUP(
1631 0, PD11MD_01, 0, 0, 0, 0, 0, 0, 1631 0, PD11MD_01, 0, 0, 0, 0, 0, 0,
1632 0, 0, 0, 0, 0, 0, 0, 0, 1632 0, 0, 0, 0, 0, 0, 0, 0,
1633 0, PD10MD_01, 0, 0, 0, 0, 0, 0, 1633 0, PD10MD_01, 0, 0, 0, 0, 0, 0,
@@ -1635,9 +1635,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1635 0, PD9MD_01, 0, 0, 0, 0, 0, 0, 1635 0, PD9MD_01, 0, 0, 0, 0, 0, 0,
1636 0, 0, 0, 0, 0, 0, 0, 0, 1636 0, 0, 0, 0, 0, 0, 0, 0,
1637 0, PD8MD_01, 0, 0, 0, 0, 0, 0, 1637 0, PD8MD_01, 0, 0, 0, 0, 0, 0,
1638 0, 0, 0, 0, 0, 0, 0, 0 } 1638 0, 0, 0, 0, 0, 0, 0, 0 ))
1639 }, 1639 },
1640 { PINMUX_CFG_REG("PDCR1", 0xfffe386c, 16, 4) { 1640 { PINMUX_CFG_REG("PDCR1", 0xfffe386c, 16, 4, GROUP(
1641 0, PD7MD_01, 0, 0, 0, 0, 0, 0, 1641 0, PD7MD_01, 0, 0, 0, 0, 0, 0,
1642 0, 0, 0, 0, 0, 0, 0, 0, 1642 0, 0, 0, 0, 0, 0, 0, 0,
1643 0, PD6MD_01, 0, 0, 0, 0, 0, 0, 1643 0, PD6MD_01, 0, 0, 0, 0, 0, 0,
@@ -1645,9 +1645,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1645 0, PD5MD_01, 0, 0, 0, 0, 0, 0, 1645 0, PD5MD_01, 0, 0, 0, 0, 0, 0,
1646 0, 0, 0, 0, 0, 0, 0, 0, 1646 0, 0, 0, 0, 0, 0, 0, 0,
1647 0, PD4MD_01, 0, 0, 0, 0, 0, 0, 1647 0, PD4MD_01, 0, 0, 0, 0, 0, 0,
1648 0, 0, 0, 0, 0, 0, 0, 0 } 1648 0, 0, 0, 0, 0, 0, 0, 0 ))
1649 }, 1649 },
1650 { PINMUX_CFG_REG("PDCR0", 0xfffe386e, 16, 4) { 1650 { PINMUX_CFG_REG("PDCR0", 0xfffe386e, 16, 4, GROUP(
1651 0, PD3MD_01, 0, 0, 0, 0, 0, 0, 1651 0, PD3MD_01, 0, 0, 0, 0, 0, 0,
1652 0, 0, 0, 0, 0, 0, 0, 0, 1652 0, 0, 0, 0, 0, 0, 0, 0,
1653 0, PD2MD_01, 0, 0, 0, 0, 0, 0, 1653 0, PD2MD_01, 0, 0, 0, 0, 0, 0,
@@ -1655,10 +1655,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1655 0, PD1MD_01, 0, 0, 0, 0, 0, 0, 1655 0, PD1MD_01, 0, 0, 0, 0, 0, 0,
1656 0, 0, 0, 0, 0, 0, 0, 0, 1656 0, 0, 0, 0, 0, 0, 0, 0,
1657 0, PD0MD_01, 0, 0, 0, 0, 0, 0, 1657 0, PD0MD_01, 0, 0, 0, 0, 0, 0,
1658 0, 0, 0, 0, 0, 0, 0, 0 } 1658 0, 0, 0, 0, 0, 0, 0, 0 ))
1659 }, 1659 },
1660 1660
1661 { PINMUX_CFG_REG("PDIOR0", 0xfffe3872, 16, 1) { 1661 { PINMUX_CFG_REG("PDIOR0", 0xfffe3872, 16, 1, GROUP(
1662 PD15_IN, PD15_OUT, 1662 PD15_IN, PD15_OUT,
1663 PD14_IN, PD14_OUT, 1663 PD14_IN, PD14_OUT,
1664 PD13_IN, PD13_OUT, 1664 PD13_IN, PD13_OUT,
@@ -1674,10 +1674,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1674 PD3_IN, PD3_OUT, 1674 PD3_IN, PD3_OUT,
1675 PD2_IN, PD2_OUT, 1675 PD2_IN, PD2_OUT,
1676 PD1_IN, PD1_OUT, 1676 PD1_IN, PD1_OUT,
1677 PD0_IN, PD0_OUT } 1677 PD0_IN, PD0_OUT ))
1678 }, 1678 },
1679 1679
1680 { PINMUX_CFG_REG("PECR1", 0xfffe388c, 16, 4) { 1680 { PINMUX_CFG_REG("PECR1", 0xfffe388c, 16, 4, GROUP(
1681 0, 0, 0, 0, 0, 0, 0, 0, 1681 0, 0, 0, 0, 0, 0, 0, 0,
1682 0, 0, 0, 0, 0, 0, 0, 0, 1682 0, 0, 0, 0, 0, 0, 0, 0,
1683 0, 0, 0, 0, 0, 0, 0, 0, 1683 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1685,10 +1685,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1685 PE5MD_00, PE5MD_01, 0, PE5MD_11, 0, 0, 0, 0, 1685 PE5MD_00, PE5MD_01, 0, PE5MD_11, 0, 0, 0, 0,
1686 0, 0, 0, 0, 0, 0, 0, 0, 1686 0, 0, 0, 0, 0, 0, 0, 0,
1687 PE4MD_00, PE4MD_01, 0, PE4MD_11, 0, 0, 0, 0, 1687 PE4MD_00, PE4MD_01, 0, PE4MD_11, 0, 0, 0, 0,
1688 0, 0, 0, 0, 0, 0, 0, 0 } 1688 0, 0, 0, 0, 0, 0, 0, 0 ))
1689 }, 1689 },
1690 1690
1691 { PINMUX_CFG_REG("PECR0", 0xfffe388e, 16, 4) { 1691 { PINMUX_CFG_REG("PECR0", 0xfffe388e, 16, 4, GROUP(
1692 PE3MD_00, PE3MD_01, 0, PE3MD_11, 0, 0, 0, 0, 1692 PE3MD_00, PE3MD_01, 0, PE3MD_11, 0, 0, 0, 0,
1693 0, 0, 0, 0, 0, 0, 0, 0, 1693 0, 0, 0, 0, 0, 0, 0, 0,
1694 PE2MD_00, PE2MD_01, 0, PE2MD_11, 0, 0, 0, 0, 1694 PE2MD_00, PE2MD_01, 0, PE2MD_11, 0, 0, 0, 0,
@@ -1697,10 +1697,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1697 PE1MD_100, PE1MD_101, 0, 0, 1697 PE1MD_100, PE1MD_101, 0, 0,
1698 0, 0, 0, 0, 0, 0, 0, 0, 1698 0, 0, 0, 0, 0, 0, 0, 0,
1699 PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11, 0, 0, 0, 0, 1699 PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11, 0, 0, 0, 0,
1700 0, 0, 0, 0, 0, 0, 0, 0 } 1700 0, 0, 0, 0, 0, 0, 0, 0 ))
1701 }, 1701 },
1702 1702
1703 { PINMUX_CFG_REG("PEIOR0", 0xfffe3892, 16, 1) { 1703 { PINMUX_CFG_REG("PEIOR0", 0xfffe3892, 16, 1, GROUP(
1704 0, 0, 0, 0, 0, 0, 0, 0, 1704 0, 0, 0, 0, 0, 0, 0, 0,
1705 0, 0, 0, 0, 0, 0, 0, 0, 1705 0, 0, 0, 0, 0, 0, 0, 0,
1706 0, 0, 0, 0, 1706 0, 0, 0, 0,
@@ -1709,19 +1709,19 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1709 PE3_IN, PE3_OUT, 1709 PE3_IN, PE3_OUT,
1710 PE2_IN, PE2_OUT, 1710 PE2_IN, PE2_OUT,
1711 PE1_IN, PE1_OUT, 1711 PE1_IN, PE1_OUT,
1712 PE0_IN, PE0_OUT } 1712 PE0_IN, PE0_OUT ))
1713 }, 1713 },
1714 1714
1715 { PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4) { 1715 { PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4, GROUP(
1716 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1716 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1717 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1717 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1718 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1718 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1719 PF12MD_000, PF12MD_001, 0, PF12MD_011, 1719 PF12MD_000, PF12MD_001, 0, PF12MD_011,
1720 PF12MD_100, PF12MD_101, 0, 0, 1720 PF12MD_100, PF12MD_101, 0, 0,
1721 0, 0, 0, 0, 0, 0, 0, 0 } 1721 0, 0, 0, 0, 0, 0, 0, 0 ))
1722 }, 1722 },
1723 1723
1724 { PINMUX_CFG_REG("PFCR2", 0xfffe38aa, 16, 4) { 1724 { PINMUX_CFG_REG("PFCR2", 0xfffe38aa, 16, 4, GROUP(
1725 PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011, 1725 PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011,
1726 PF11MD_100, PF11MD_101, 0, 0, 1726 PF11MD_100, PF11MD_101, 0, 0,
1727 0, 0, 0, 0, 0, 0, 0, 0, 1727 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1732,10 +1732,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1732 PF9MD_100, PF9MD_101, 0, 0, 1732 PF9MD_100, PF9MD_101, 0, 0,
1733 0, 0, 0, 0, 0, 0, 0, 0, 1733 0, 0, 0, 0, 0, 0, 0, 0,
1734 PF8MD_00, PF8MD_01, PF8MD_10, PF8MD_11, 0, 0, 0, 0, 1734 PF8MD_00, PF8MD_01, PF8MD_10, PF8MD_11, 0, 0, 0, 0,
1735 0, 0, 0, 0, 0, 0, 0, 0 } 1735 0, 0, 0, 0, 0, 0, 0, 0 ))
1736 }, 1736 },
1737 1737
1738 { PINMUX_CFG_REG("PFCR1", 0xfffe38ac, 16, 4) { 1738 { PINMUX_CFG_REG("PFCR1", 0xfffe38ac, 16, 4, GROUP(
1739 PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011, 1739 PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011,
1740 PF7MD_100, 0, 0, 0, 1740 PF7MD_100, 0, 0, 0,
1741 0, 0, 0, 0, 0, 0, 0, 0, 1741 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1747,10 +1747,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1747 0, 0, 0, 0, 0, 0, 0, 0, 1747 0, 0, 0, 0, 0, 0, 0, 0,
1748 PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011, 1748 PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011,
1749 PF4MD_100, 0, 0, 0, 1749 PF4MD_100, 0, 0, 0,
1750 0, 0, 0, 0, 0, 0, 0, 0 } 1750 0, 0, 0, 0, 0, 0, 0, 0 ))
1751 }, 1751 },
1752 1752
1753 { PINMUX_CFG_REG("PFCR0", 0xfffe38ae, 16, 4) { 1753 { PINMUX_CFG_REG("PFCR0", 0xfffe38ae, 16, 4, GROUP(
1754 PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011, 1754 PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011,
1755 PF3MD_100, 0, 0, 0, 1755 PF3MD_100, 0, 0, 0,
1756 0, 0, 0, 0, 0, 0, 0, 0, 1756 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1762,10 +1762,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1762 0, 0, 0, 0, 0, 0, 0, 0, 1762 0, 0, 0, 0, 0, 0, 0, 0,
1763 PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011, 1763 PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011,
1764 PF0MD_100, PF0MD_101, 0, 0, 1764 PF0MD_100, PF0MD_101, 0, 0,
1765 0, 0, 0, 0, 0, 0, 0, 0 } 1765 0, 0, 0, 0, 0, 0, 0, 0 ))
1766 }, 1766 },
1767 1767
1768 { PINMUX_CFG_REG("PFIOR0", 0xfffe38b2, 16, 1) { 1768 { PINMUX_CFG_REG("PFIOR0", 0xfffe38b2, 16, 1, GROUP(
1769 0, 0, 0, 0, 0, 0, 1769 0, 0, 0, 0, 0, 0,
1770 PF12_IN, PF12_OUT, 1770 PF12_IN, PF12_OUT,
1771 PF11_IN, PF11_OUT, 1771 PF11_IN, PF11_OUT,
@@ -1779,10 +1779,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1779 PF3_IN, PF3_OUT, 1779 PF3_IN, PF3_OUT,
1780 PF2_IN, PF2_OUT, 1780 PF2_IN, PF2_OUT,
1781 PF1_IN, PF1_OUT, 1781 PF1_IN, PF1_OUT,
1782 PF0_IN, PF0_OUT } 1782 PF0_IN, PF0_OUT ))
1783 }, 1783 },
1784 1784
1785 { PINMUX_CFG_REG("PGCR7", 0xfffe38c0, 16, 4) { 1785 { PINMUX_CFG_REG("PGCR7", 0xfffe38c0, 16, 4, GROUP(
1786 0, 0, 0, 0, 0, 0, 0, 0, 1786 0, 0, 0, 0, 0, 0, 0, 0,
1787 0, 0, 0, 0, 0, 0, 0, 0, 1787 0, 0, 0, 0, 0, 0, 0, 0,
1788 0, 0, 0, 0, 0, 0, 0, 0, 1788 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1791,10 +1791,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1791 0, 0, 0, 0, 0, 0, 0, 0, 1791 0, 0, 0, 0, 0, 0, 0, 0,
1792 PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011, 1792 PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011,
1793 PG0MD_100, 0, 0, 0, 1793 PG0MD_100, 0, 0, 0,
1794 0, 0, 0, 0, 0, 0, 0, 0 } 1794 0, 0, 0, 0, 0, 0, 0, 0 ))
1795 }, 1795 },
1796 1796
1797 { PINMUX_CFG_REG("PGCR6", 0xfffe38c2, 16, 4) { 1797 { PINMUX_CFG_REG("PGCR6", 0xfffe38c2, 16, 4, GROUP(
1798 0, 0, 0, 0, 0, 0, 0, 0, 1798 0, 0, 0, 0, 0, 0, 0, 0,
1799 0, 0, 0, 0, 0, 0, 0, 0, 1799 0, 0, 0, 0, 0, 0, 0, 0,
1800 0, 0, 0, 0, 0, 0, 0, 0, 1800 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1802,10 +1802,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1802 0, 0, 0, 0, 0, 0, 0, 0, 1802 0, 0, 0, 0, 0, 0, 0, 0,
1803 0, 0, 0, 0, 0, 0, 0, 0, 1803 0, 0, 0, 0, 0, 0, 0, 0,
1804 PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11, 0, 0, 0, 0, 1804 PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11, 0, 0, 0, 0,
1805 0, 0, 0, 0, 0, 0, 0, 0 } 1805 0, 0, 0, 0, 0, 0, 0, 0 ))
1806 }, 1806 },
1807 1807
1808 { PINMUX_CFG_REG("PGCR5", 0xfffe38c4, 16, 4) { 1808 { PINMUX_CFG_REG("PGCR5", 0xfffe38c4, 16, 4, GROUP(
1809 PG23MD_00, PG23MD_01, PG23MD_10, PG23MD_11, 0, 0, 0, 0, 1809 PG23MD_00, PG23MD_01, PG23MD_10, PG23MD_11, 0, 0, 0, 0,
1810 0, 0, 0, 0, 0, 0, 0, 0, 1810 0, 0, 0, 0, 0, 0, 0, 0,
1811 PG22MD_00, PG22MD_01, PG22MD_10, PG22MD_11, 0, 0, 0, 0, 1811 PG22MD_00, PG22MD_01, PG22MD_10, PG22MD_11, 0, 0, 0, 0,
@@ -1814,10 +1814,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1814 0, 0, 0, 0, 0, 0, 0, 0, 1814 0, 0, 0, 0, 0, 0, 0, 0,
1815 PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011, 1815 PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011,
1816 PG20MD_100, 0, 0, 0, 1816 PG20MD_100, 0, 0, 0,
1817 0, 0, 0, 0, 0, 0, 0, 0 } 1817 0, 0, 0, 0, 0, 0, 0, 0 ))
1818 }, 1818 },
1819 1819
1820 { PINMUX_CFG_REG("PGCR4", 0xfffe38c6, 16, 4) { 1820 { PINMUX_CFG_REG("PGCR4", 0xfffe38c6, 16, 4, GROUP(
1821 PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011, 1821 PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011,
1822 PG19MD_100, 0, 0, 0, 1822 PG19MD_100, 0, 0, 0,
1823 0, 0, 0, 0, 0, 0, 0, 0, 1823 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1829,10 +1829,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1829 0, 0, 0, 0, 0, 0, 0, 0, 1829 0, 0, 0, 0, 0, 0, 0, 0,
1830 PG16MD_000, PG16MD_001, PG16MD_010, PG16MD_011, 1830 PG16MD_000, PG16MD_001, PG16MD_010, PG16MD_011,
1831 PG16MD_100, 0, 0, 0, 1831 PG16MD_100, 0, 0, 0,
1832 0, 0, 0, 0, 0, 0, 0, 0 } 1832 0, 0, 0, 0, 0, 0, 0, 0 ))
1833 }, 1833 },
1834 1834
1835 { PINMUX_CFG_REG("PGCR3", 0xfffe38c8, 16, 4) { 1835 { PINMUX_CFG_REG("PGCR3", 0xfffe38c8, 16, 4, GROUP(
1836 PG15MD_000, PG15MD_001, PG15MD_010, PG15MD_011, 1836 PG15MD_000, PG15MD_001, PG15MD_010, PG15MD_011,
1837 PG15MD_100, 0, 0, 0, 1837 PG15MD_100, 0, 0, 0,
1838 0, 0, 0, 0, 0, 0, 0, 0, 1838 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1844,9 +1844,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1844 0, 0, 0, 0, 0, 0, 0, 0, 1844 0, 0, 0, 0, 0, 0, 0, 0,
1845 PG12MD_000, PG12MD_001, PG12MD_010, 0, 1845 PG12MD_000, PG12MD_001, PG12MD_010, 0,
1846 PG12MD_100, 0, 0, 0, 1846 PG12MD_100, 0, 0, 0,
1847 0, 0, 0, 0, 0, 0, 0, 0 } 1847 0, 0, 0, 0, 0, 0, 0, 0 ))
1848 }, 1848 },
1849 { PINMUX_CFG_REG("PGCR2", 0xfffe38ca, 16, 4) { 1849 { PINMUX_CFG_REG("PGCR2", 0xfffe38ca, 16, 4, GROUP(
1850 PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011, 1850 PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011,
1851 PG11MD_100, PG11MD_101, 0, 0, 1851 PG11MD_100, PG11MD_101, 0, 0,
1852 0, 0, 0, 0, 0, 0, 0, 0, 1852 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1858,10 +1858,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1858 0, 0, 0, 0, 0, 0, 0, 0, 1858 0, 0, 0, 0, 0, 0, 0, 0,
1859 PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011, 1859 PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011,
1860 PG8MD_100, PG8MD_101, 0, 0, 1860 PG8MD_100, PG8MD_101, 0, 0,
1861 0, 0, 0, 0, 0, 0, 0, 0 } 1861 0, 0, 0, 0, 0, 0, 0, 0 ))
1862 }, 1862 },
1863 1863
1864 { PINMUX_CFG_REG("PGCR1", 0xfffe38cc, 16, 4) { 1864 { PINMUX_CFG_REG("PGCR1", 0xfffe38cc, 16, 4, GROUP(
1865 PG7MD_00, PG7MD_01, PG7MD_10, PG7MD_11, 0, 0, 0, 0, 1865 PG7MD_00, PG7MD_01, PG7MD_10, PG7MD_11, 0, 0, 0, 0,
1866 0, 0, 0, 0, 0, 0, 0, 0, 1866 0, 0, 0, 0, 0, 0, 0, 0,
1867 PG6MD_00, PG6MD_01, PG6MD_10, PG6MD_11, 0, 0, 0, 0, 1867 PG6MD_00, PG6MD_01, PG6MD_10, PG6MD_11, 0, 0, 0, 0,
@@ -1869,9 +1869,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1869 PG5MD_00, PG5MD_01, PG5MD_10, PG5MD_11, 0, 0, 0, 0, 1869 PG5MD_00, PG5MD_01, PG5MD_10, PG5MD_11, 0, 0, 0, 0,
1870 0, 0, 0, 0, 0, 0, 0, 0, 1870 0, 0, 0, 0, 0, 0, 0, 0,
1871 PG4MD_00, PG4MD_01, PG4MD_10, PG4MD_11, 0, 0, 0, 0, 1871 PG4MD_00, PG4MD_01, PG4MD_10, PG4MD_11, 0, 0, 0, 0,
1872 0, 0, 0, 0, 0, 0, 0, 0 } 1872 0, 0, 0, 0, 0, 0, 0, 0 ))
1873 }, 1873 },
1874 { PINMUX_CFG_REG("PGCR0", 0xfffe38ce, 16, 4) { 1874 { PINMUX_CFG_REG("PGCR0", 0xfffe38ce, 16, 4, GROUP(
1875 PG3MD_00, PG3MD_01, PG3MD_10, PG3MD_11, 0, 0, 0, 0, 1875 PG3MD_00, PG3MD_01, PG3MD_10, PG3MD_11, 0, 0, 0, 0,
1876 0, 0, 0, 0, 0, 0, 0, 0, 1876 0, 0, 0, 0, 0, 0, 0, 0,
1877 PG2MD_00, PG2MD_01, PG2MD_10, PG2MD_11, 0, 0, 0, 0, 1877 PG2MD_00, PG2MD_01, PG2MD_10, PG2MD_11, 0, 0, 0, 0,
@@ -1879,9 +1879,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1879 PG1MD_00, PG1MD_01, PG1MD_10, PG1MD_11, 0, 0, 0, 0, 1879 PG1MD_00, PG1MD_01, PG1MD_10, PG1MD_11, 0, 0, 0, 0,
1880 0, 0, 0, 0, 0, 0, 0, 0, 1880 0, 0, 0, 0, 0, 0, 0, 0,
1881 0, 0, 0, 0, 0, 0, 0, 0, 1881 0, 0, 0, 0, 0, 0, 0, 0,
1882 0, 0, 0, 0, 0, 0, 0, 0 } 1882 0, 0, 0, 0, 0, 0, 0, 0 ))
1883 }, 1883 },
1884 { PINMUX_CFG_REG("PGIOR1", 0xfffe38d0, 16, 1) { 1884 { PINMUX_CFG_REG("PGIOR1", 0xfffe38d0, 16, 1, GROUP(
1885 0, 0, 0, 0, 0, 0, 0, 0, 1885 0, 0, 0, 0, 0, 0, 0, 0,
1886 0, 0, 0, 0, 0, 0, 1886 0, 0, 0, 0, 0, 0,
1887 PG24_IN, PG24_OUT, 1887 PG24_IN, PG24_OUT,
@@ -1892,10 +1892,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1892 PG19_IN, PG19_OUT, 1892 PG19_IN, PG19_OUT,
1893 PG18_IN, PG18_OUT, 1893 PG18_IN, PG18_OUT,
1894 PG17_IN, PG17_OUT, 1894 PG17_IN, PG17_OUT,
1895 PG16_IN, PG16_OUT } 1895 PG16_IN, PG16_OUT ))
1896 }, 1896 },
1897 1897
1898 { PINMUX_CFG_REG("PGIOR0", 0xfffe38d2, 16, 1) { 1898 { PINMUX_CFG_REG("PGIOR0", 0xfffe38d2, 16, 1, GROUP(
1899 PG15_IN, PG15_OUT, 1899 PG15_IN, PG15_OUT,
1900 PG14_IN, PG14_OUT, 1900 PG14_IN, PG14_OUT,
1901 PG13_IN, PG13_OUT, 1901 PG13_IN, PG13_OUT,
@@ -1912,10 +1912,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1912 PG2_IN, PG2_OUT, 1912 PG2_IN, PG2_OUT,
1913 PG1_IN, PG1_OUT, 1913 PG1_IN, PG1_OUT,
1914 PG0_IN, PG0_OUT 1914 PG0_IN, PG0_OUT
1915 } 1915 ))
1916 }, 1916 },
1917 1917
1918 { PINMUX_CFG_REG("PHCR1", 0xfffe38ec, 16, 4) { 1918 { PINMUX_CFG_REG("PHCR1", 0xfffe38ec, 16, 4, GROUP(
1919 PH7MD_0, PH7MD_1, 0, 0, 0, 0, 0, 0, 1919 PH7MD_0, PH7MD_1, 0, 0, 0, 0, 0, 0,
1920 0, 0, 0, 0, 0, 0, 0, 0, 1920 0, 0, 0, 0, 0, 0, 0, 0,
1921 PH6MD_0, PH6MD_1, 0, 0, 0, 0, 0, 0, 1921 PH6MD_0, PH6MD_1, 0, 0, 0, 0, 0, 0,
@@ -1923,10 +1923,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1923 PH5MD_0, PH5MD_1, 0, 0, 0, 0, 0, 0, 1923 PH5MD_0, PH5MD_1, 0, 0, 0, 0, 0, 0,
1924 0, 0, 0, 0, 0, 0, 0, 0, 1924 0, 0, 0, 0, 0, 0, 0, 0,
1925 PH4MD_0, PH4MD_1, 0, 0, 0, 0, 0, 0, 1925 PH4MD_0, PH4MD_1, 0, 0, 0, 0, 0, 0,
1926 0, 0, 0, 0, 0, 0, 0, 0 } 1926 0, 0, 0, 0, 0, 0, 0, 0 ))
1927 }, 1927 },
1928 1928
1929 { PINMUX_CFG_REG("PHCR0", 0xfffe38ee, 16, 4) { 1929 { PINMUX_CFG_REG("PHCR0", 0xfffe38ee, 16, 4, GROUP(
1930 PH3MD_0, PH3MD_1, 0, 0, 0, 0, 0, 0, 1930 PH3MD_0, PH3MD_1, 0, 0, 0, 0, 0, 0,
1931 0, 0, 0, 0, 0, 0, 0, 0, 1931 0, 0, 0, 0, 0, 0, 0, 0,
1932 PH2MD_0, PH2MD_1, 0, 0, 0, 0, 0, 0, 1932 PH2MD_0, PH2MD_1, 0, 0, 0, 0, 0, 0,
@@ -1934,10 +1934,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1934 PH1MD_0, PH1MD_1, 0, 0, 0, 0, 0, 0, 1934 PH1MD_0, PH1MD_1, 0, 0, 0, 0, 0, 0,
1935 0, 0, 0, 0, 0, 0, 0, 0, 1935 0, 0, 0, 0, 0, 0, 0, 0,
1936 PH0MD_0, PH0MD_1, 0, 0, 0, 0, 0, 0, 1936 PH0MD_0, PH0MD_1, 0, 0, 0, 0, 0, 0,
1937 0, 0, 0, 0, 0, 0, 0, 0 } 1937 0, 0, 0, 0, 0, 0, 0, 0 ))
1938 }, 1938 },
1939 1939
1940 { PINMUX_CFG_REG("PJCR2", 0xfffe390a, 16, 4) { 1940 { PINMUX_CFG_REG("PJCR2", 0xfffe390a, 16, 4, GROUP(
1941 PJ11MD_00, PJ11MD_01, PJ11MD_10, 0, 0, 0, 0, 0, 1941 PJ11MD_00, PJ11MD_01, PJ11MD_10, 0, 0, 0, 0, 0,
1942 0, 0, 0, 0, 0, 0, 0, 0, 1942 0, 0, 0, 0, 0, 0, 0, 0,
1943 PJ10MD_00, PJ10MD_01, PJ10MD_10, 0, 0, 0, 0, 0, 1943 PJ10MD_00, PJ10MD_01, PJ10MD_10, 0, 0, 0, 0, 0,
@@ -1945,9 +1945,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1945 PJ9MD_00, PJ9MD_01, PJ9MD_10, 0, 0, 0, 0, 0, 1945 PJ9MD_00, PJ9MD_01, PJ9MD_10, 0, 0, 0, 0, 0,
1946 0, 0, 0, 0, 0, 0, 0, 0, 1946 0, 0, 0, 0, 0, 0, 0, 0,
1947 PJ8MD_00, PJ8MD_01, PJ8MD_10, 0, 0, 0, 0, 0, 1947 PJ8MD_00, PJ8MD_01, PJ8MD_10, 0, 0, 0, 0, 0,
1948 0, 0, 0, 0, 0, 0, 0, 0 } 1948 0, 0, 0, 0, 0, 0, 0, 0 ))
1949 }, 1949 },
1950 { PINMUX_CFG_REG("PJCR1", 0xfffe390c, 16, 4) { 1950 { PINMUX_CFG_REG("PJCR1", 0xfffe390c, 16, 4, GROUP(
1951 PJ7MD_00, PJ7MD_01, PJ7MD_10, 0, 0, 0, 0, 0, 1951 PJ7MD_00, PJ7MD_01, PJ7MD_10, 0, 0, 0, 0, 0,
1952 0, 0, 0, 0, 0, 0, 0, 0, 1952 0, 0, 0, 0, 0, 0, 0, 0,
1953 PJ6MD_00, PJ6MD_01, PJ6MD_10, 0, 0, 0, 0, 0, 1953 PJ6MD_00, PJ6MD_01, PJ6MD_10, 0, 0, 0, 0, 0,
@@ -1955,9 +1955,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1955 PJ5MD_00, PJ5MD_01, PJ5MD_10, 0, 0, 0, 0, 0, 1955 PJ5MD_00, PJ5MD_01, PJ5MD_10, 0, 0, 0, 0, 0,
1956 0, 0, 0, 0, 0, 0, 0, 0, 1956 0, 0, 0, 0, 0, 0, 0, 0,
1957 PJ4MD_00, PJ4MD_01, PJ4MD_10, 0, 0, 0, 0, 0, 1957 PJ4MD_00, PJ4MD_01, PJ4MD_10, 0, 0, 0, 0, 0,
1958 0, 0, 0, 0, 0, 0, 0, 0 } 1958 0, 0, 0, 0, 0, 0, 0, 0 ))
1959 }, 1959 },
1960 { PINMUX_CFG_REG("PJCR0", 0xfffe390e, 16, 4) { 1960 { PINMUX_CFG_REG("PJCR0", 0xfffe390e, 16, 4, GROUP(
1961 PJ3MD_00, PJ3MD_01, PJ3MD_10, PJ3MD_11, 0, 0, 0, 0, 1961 PJ3MD_00, PJ3MD_01, PJ3MD_10, PJ3MD_11, 0, 0, 0, 0,
1962 0, 0, 0, 0, 0, 0, 0, 0, 1962 0, 0, 0, 0, 0, 0, 0, 0,
1963 PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011, 1963 PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011,
@@ -1968,9 +1968,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1968 0, 0, 0, 0, 0, 0, 0, 0, 1968 0, 0, 0, 0, 0, 0, 0, 0,
1969 PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011, 1969 PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011,
1970 PJ0MD_100, PJ0MD_101, 0, 0, 1970 PJ0MD_100, PJ0MD_101, 0, 0,
1971 0, 0, 0, 0, 0, 0, 0, 0, } 1971 0, 0, 0, 0, 0, 0, 0, 0, ))
1972 }, 1972 },
1973 { PINMUX_CFG_REG("PJIOR0", 0xfffe3912, 16, 1) { 1973 { PINMUX_CFG_REG("PJIOR0", 0xfffe3912, 16, 1, GROUP(
1974 0, 0, 0, 0, 0, 0, 0, 0, 1974 0, 0, 0, 0, 0, 0, 0, 0,
1975 PJ11_IN, PJ11_OUT, 1975 PJ11_IN, PJ11_OUT,
1976 PJ10_IN, PJ10_OUT, 1976 PJ10_IN, PJ10_OUT,
@@ -1983,10 +1983,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1983 PJ3_IN, PJ3_OUT, 1983 PJ3_IN, PJ3_OUT,
1984 PJ2_IN, PJ2_OUT, 1984 PJ2_IN, PJ2_OUT,
1985 PJ1_IN, PJ1_OUT, 1985 PJ1_IN, PJ1_OUT,
1986 PJ0_IN, PJ0_OUT } 1986 PJ0_IN, PJ0_OUT ))
1987 }, 1987 },
1988 1988
1989 { PINMUX_CFG_REG("PKCR2", 0xfffe392a, 16, 4) { 1989 { PINMUX_CFG_REG("PKCR2", 0xfffe392a, 16, 4, GROUP(
1990 PK11MD_00, PK11MD_01, PK11MD_10, 0, 0, 0, 0, 0, 1990 PK11MD_00, PK11MD_01, PK11MD_10, 0, 0, 0, 0, 0,
1991 0, 0, 0, 0, 0, 0, 0, 0, 1991 0, 0, 0, 0, 0, 0, 0, 0,
1992 PK10MD_00, PK10MD_01, PK10MD_10, 0, 0, 0, 0, 0, 1992 PK10MD_00, PK10MD_01, PK10MD_10, 0, 0, 0, 0, 0,
@@ -1994,10 +1994,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1994 PK9MD_00, PK9MD_01, PK9MD_10, 0, 0, 0, 0, 0, 1994 PK9MD_00, PK9MD_01, PK9MD_10, 0, 0, 0, 0, 0,
1995 0, 0, 0, 0, 0, 0, 0, 0, 1995 0, 0, 0, 0, 0, 0, 0, 0,
1996 PK8MD_00, PK8MD_01, PK8MD_10, 0, 0, 0, 0, 0, 1996 PK8MD_00, PK8MD_01, PK8MD_10, 0, 0, 0, 0, 0,
1997 0, 0, 0, 0, 0, 0, 0, 0 } 1997 0, 0, 0, 0, 0, 0, 0, 0 ))
1998 }, 1998 },
1999 1999
2000 { PINMUX_CFG_REG("PKCR1", 0xfffe392c, 16, 4) { 2000 { PINMUX_CFG_REG("PKCR1", 0xfffe392c, 16, 4, GROUP(
2001 PK7MD_00, PK7MD_01, PK7MD_10, 0, 0, 0, 0, 0, 2001 PK7MD_00, PK7MD_01, PK7MD_10, 0, 0, 0, 0, 0,
2002 0, 0, 0, 0, 0, 0, 0, 0, 2002 0, 0, 0, 0, 0, 0, 0, 0,
2003 PK6MD_00, PK6MD_01, PK6MD_10, 0, 0, 0, 0, 0, 2003 PK6MD_00, PK6MD_01, PK6MD_10, 0, 0, 0, 0, 0,
@@ -2005,9 +2005,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2005 PK5MD_00, PK5MD_01, PK5MD_10, 0, 0, 0, 0, 0, 2005 PK5MD_00, PK5MD_01, PK5MD_10, 0, 0, 0, 0, 0,
2006 0, 0, 0, 0, 0, 0, 0, 0, 2006 0, 0, 0, 0, 0, 0, 0, 0,
2007 PK4MD_00, PK4MD_01, PK4MD_10, 0, 0, 0, 0, 0, 2007 PK4MD_00, PK4MD_01, PK4MD_10, 0, 0, 0, 0, 0,
2008 0, 0, 0, 0, 0, 0, 0, 0 } 2008 0, 0, 0, 0, 0, 0, 0, 0 ))
2009 }, 2009 },
2010 { PINMUX_CFG_REG("PKCR0", 0xfffe392e, 16, 4) { 2010 { PINMUX_CFG_REG("PKCR0", 0xfffe392e, 16, 4, GROUP(
2011 PK3MD_00, PK3MD_01, PK3MD_10, 0, 0, 0, 0, 0, 2011 PK3MD_00, PK3MD_01, PK3MD_10, 0, 0, 0, 0, 0,
2012 0, 0, 0, 0, 0, 0, 0, 0, 2012 0, 0, 0, 0, 0, 0, 0, 0,
2013 PK2MD_00, PK2MD_01, PK2MD_10, 0, 0, 0, 0, 0, 2013 PK2MD_00, PK2MD_01, PK2MD_10, 0, 0, 0, 0, 0,
@@ -2015,10 +2015,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2015 PK1MD_00, PK1MD_01, PK1MD_10, 0, 0, 0, 0, 0, 2015 PK1MD_00, PK1MD_01, PK1MD_10, 0, 0, 0, 0, 0,
2016 0, 0, 0, 0, 0, 0, 0, 0, 2016 0, 0, 0, 0, 0, 0, 0, 0,
2017 PK0MD_00, PK0MD_01, PK0MD_10, 0, 0, 0, 0, 0, 2017 PK0MD_00, PK0MD_01, PK0MD_10, 0, 0, 0, 0, 0,
2018 0, 0, 0, 0, 0, 0, 0, 0 } 2018 0, 0, 0, 0, 0, 0, 0, 0 ))
2019 }, 2019 },
2020 2020
2021 { PINMUX_CFG_REG("PKIOR0", 0xfffe3932, 16, 1) { 2021 { PINMUX_CFG_REG("PKIOR0", 0xfffe3932, 16, 1, GROUP(
2022 0, 0, 0, 0, 0, 0, 0, 0, 2022 0, 0, 0, 0, 0, 0, 0, 0,
2023 PJ11_IN, PJ11_OUT, 2023 PJ11_IN, PJ11_OUT,
2024 PJ10_IN, PJ10_OUT, 2024 PJ10_IN, PJ10_OUT,
@@ -2031,85 +2031,85 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2031 PJ3_IN, PJ3_OUT, 2031 PJ3_IN, PJ3_OUT,
2032 PJ2_IN, PJ2_OUT, 2032 PJ2_IN, PJ2_OUT,
2033 PJ1_IN, PJ1_OUT, 2033 PJ1_IN, PJ1_OUT,
2034 PJ0_IN, PJ0_OUT } 2034 PJ0_IN, PJ0_OUT ))
2035 }, 2035 },
2036 {} 2036 {}
2037}; 2037};
2038 2038
2039static const struct pinmux_data_reg pinmux_data_regs[] = { 2039static const struct pinmux_data_reg pinmux_data_regs[] = {
2040 { PINMUX_DATA_REG("PADR1", 0xfffe3814, 16) { 2040 { PINMUX_DATA_REG("PADR1", 0xfffe3814, 16, GROUP(
2041 0, 0, 0, 0, 0, 0, 0, PA3_DATA, 2041 0, 0, 0, 0, 0, 0, 0, PA3_DATA,
2042 0, 0, 0, 0, 0, 0, 0, PA2_DATA } 2042 0, 0, 0, 0, 0, 0, 0, PA2_DATA ))
2043 }, 2043 },
2044 2044
2045 { PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) { 2045 { PINMUX_DATA_REG("PADR0", 0xfffe3816, 16, GROUP(
2046 0, 0, 0, 0, 0, 0, 0, PA1_DATA, 2046 0, 0, 0, 0, 0, 0, 0, PA1_DATA,
2047 0, 0, 0, 0, 0, 0, 0, PA0_DATA } 2047 0, 0, 0, 0, 0, 0, 0, PA0_DATA ))
2048 }, 2048 },
2049 2049
2050 { PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16) { 2050 { PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16, GROUP(
2051 0, 0, 0, 0, 0, 0, 0, 0, 2051 0, 0, 0, 0, 0, 0, 0, 0,
2052 0, PB22_DATA, PB21_DATA, PB20_DATA, 2052 0, PB22_DATA, PB21_DATA, PB20_DATA,
2053 PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA } 2053 PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA ))
2054 }, 2054 },
2055 2055
2056 { PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16) { 2056 { PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16, GROUP(
2057 PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA, 2057 PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA,
2058 PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA, 2058 PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
2059 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, 2059 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
2060 PB3_DATA, PB2_DATA, PB1_DATA, 0 } 2060 PB3_DATA, PB2_DATA, PB1_DATA, 0 ))
2061 }, 2061 },
2062 2062
2063 { PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16) { 2063 { PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16, GROUP(
2064 0, 0, 0, 0, 2064 0, 0, 0, 0,
2065 0, PC10_DATA, PC9_DATA, PC8_DATA, 2065 0, PC10_DATA, PC9_DATA, PC8_DATA,
2066 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, 2066 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
2067 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA } 2067 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
2068 }, 2068 },
2069 2069
2070 { PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16) { 2070 { PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16, GROUP(
2071 PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA, 2071 PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
2072 PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA, 2072 PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
2073 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, 2073 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
2074 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA } 2074 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
2075 }, 2075 },
2076 2076
2077 { PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16) { 2077 { PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16, GROUP(
2078 0, 0, 0, 0, 0, 0, 0, 0, 2078 0, 0, 0, 0, 0, 0, 0, 0,
2079 0, 0, PE5_DATA, PE4_DATA, 2079 0, 0, PE5_DATA, PE4_DATA,
2080 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA } 2080 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA ))
2081 }, 2081 },
2082 2082
2083 { PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16) { 2083 { PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16, GROUP(
2084 0, 0, 0, PF12_DATA, 2084 0, 0, 0, PF12_DATA,
2085 PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA, 2085 PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
2086 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, 2086 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
2087 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA } 2087 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
2088 }, 2088 },
2089 2089
2090 { PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16) { 2090 { PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16, GROUP(
2091 0, 0, 0, 0, 0, 0, 0, PG24_DATA, 2091 0, 0, 0, 0, 0, 0, 0, PG24_DATA,
2092 PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA, 2092 PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA,
2093 PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA } 2093 PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA ))
2094 }, 2094 },
2095 2095
2096 { PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16) { 2096 { PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16, GROUP(
2097 PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA, 2097 PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA,
2098 PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA, 2098 PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA,
2099 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA, 2099 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
2100 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA } 2100 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA ))
2101 }, 2101 },
2102 { PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16) { 2102 { PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16, GROUP(
2103 0, 0, 0, PJ12_DATA, 2103 0, 0, 0, PJ12_DATA,
2104 PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA, 2104 PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA,
2105 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA, 2105 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
2106 PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA } 2106 PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA ))
2107 }, 2107 },
2108 { PINMUX_DATA_REG("PKDR0", 0xfffe3936, 16) { 2108 { PINMUX_DATA_REG("PKDR0", 0xfffe3936, 16, GROUP(
2109 0, 0, 0, PK12_DATA, 2109 0, 0, 0, PK12_DATA,
2110 PK11_DATA, PK10_DATA, PK9_DATA, PK8_DATA, 2110 PK11_DATA, PK10_DATA, PK9_DATA, PK8_DATA,
2111 PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA, 2111 PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
2112 PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA } 2112 PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA ))
2113 }, 2113 },
2114 { } 2114 { }
2115}; 2115};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
index a95997a389a4..6cbb18ef77dc 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
@@ -1951,13 +1951,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1951 /* where Field_Width is 1 for single mode registers or 4 for upto 16 1951 /* where Field_Width is 1 for single mode registers or 4 for upto 16
1952 mode registers and modes are described in assending order [0..16] */ 1952 mode registers and modes are described in assending order [0..16] */
1953 1953
1954 { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) { 1954 { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1, GROUP(
1955 0, 0, 0, 0, 0, 0, 0, 0, 1955 0, 0, 0, 0, 0, 0, 0, 0,
1956 0, 0, 0, 0, 0, 0, PA1_IN, PA1_OUT, 1956 0, 0, 0, 0, 0, 0, PA1_IN, PA1_OUT,
1957 0, 0, 0, 0, 0, 0, 0, 0, 1957 0, 0, 0, 0, 0, 0, 0, 0,
1958 0, 0, 0, 0, 0, 0, PA0_IN, PA0_OUT } 1958 0, 0, 0, 0, 0, 0, PA0_IN, PA0_OUT ))
1959 }, 1959 },
1960 { PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4) { 1960 { PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4, GROUP(
1961 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1961 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1962 1962
1963 PB22MD_000, PB22MD_001, PB22MD_010, PB22MD_011, 1963 PB22MD_000, PB22MD_001, PB22MD_010, PB22MD_011,
@@ -1969,9 +1969,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1969 1969
1970 PB20MD_000, PB20MD_001, PB20MD_010, PB20MD_011, 1970 PB20MD_000, PB20MD_001, PB20MD_010, PB20MD_011,
1971 PB20MD_100, PB20MD_101, PB20MD_110, PB20MD_111, 1971 PB20MD_100, PB20MD_101, PB20MD_110, PB20MD_111,
1972 0, 0, 0, 0, 0, 0, 0, 0 } 1972 0, 0, 0, 0, 0, 0, 0, 0 ))
1973 }, 1973 },
1974 { PINMUX_CFG_REG("PBCR4", 0xfffe3826, 16, 4) { 1974 { PINMUX_CFG_REG("PBCR4", 0xfffe3826, 16, 4, GROUP(
1975 PB19MD_000, PB19MD_001, PB19MD_010, PB19MD_011, 1975 PB19MD_000, PB19MD_001, PB19MD_010, PB19MD_011,
1976 PB19MD_100, PB19MD_101, PB19MD_110, PB19MD_111, 1976 PB19MD_100, PB19MD_101, PB19MD_110, PB19MD_111,
1977 0, 0, 0, 0, 0, 0, 0, 0, 1977 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1986,9 +1986,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1986 1986
1987 PB16MD_000, PB16MD_001, PB16MD_010, PB16MD_011, 1987 PB16MD_000, PB16MD_001, PB16MD_010, PB16MD_011,
1988 PB16MD_100, PB16MD_101, PB16MD_110, PB16MD_111, 1988 PB16MD_100, PB16MD_101, PB16MD_110, PB16MD_111,
1989 0, 0, 0, 0, 0, 0, 0, 0 } 1989 0, 0, 0, 0, 0, 0, 0, 0 ))
1990 }, 1990 },
1991 { PINMUX_CFG_REG("PBCR3", 0xfffe3828, 16, 4) { 1991 { PINMUX_CFG_REG("PBCR3", 0xfffe3828, 16, 4, GROUP(
1992 PB15MD_000, PB15MD_001, PB15MD_010, PB15MD_011, 1992 PB15MD_000, PB15MD_001, PB15MD_010, PB15MD_011,
1993 PB15MD_100, PB15MD_101, PB15MD_110, PB15MD_111, 1993 PB15MD_100, PB15MD_101, PB15MD_110, PB15MD_111,
1994 0, 0, 0, 0, 0, 0, 0, 0, 1994 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2002,9 +2002,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2002 0, 0, 0, 0, 0, 0, 0, 0, 2002 0, 0, 0, 0, 0, 0, 0, 0,
2003 2003
2004 PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11, 0, 0, 0, 0, 2004 PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11, 0, 0, 0, 0,
2005 0, 0, 0, 0, 0, 0, 0, 0 } 2005 0, 0, 0, 0, 0, 0, 0, 0 ))
2006 }, 2006 },
2007 { PINMUX_CFG_REG("PBCR2", 0xfffe382a, 16, 4) { 2007 { PINMUX_CFG_REG("PBCR2", 0xfffe382a, 16, 4, GROUP(
2008 PB11MD_00, PB11MD_01, PB11MD_10, PB11MD_11, 0, 0, 0, 0, 2008 PB11MD_00, PB11MD_01, PB11MD_10, PB11MD_11, 0, 0, 0, 0,
2009 0, 0, 0, 0, 0, 0, 0, 0, 2009 0, 0, 0, 0, 0, 0, 0, 0,
2010 2010
@@ -2015,9 +2015,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2015 0, 0, 0, 0, 0, 0, 0, 0, 2015 0, 0, 0, 0, 0, 0, 0, 0,
2016 2016
2017 PB8MD_00, PB8MD_01, PB8MD_10, PB8MD_11, 0, 0, 0, 0, 2017 PB8MD_00, PB8MD_01, PB8MD_10, PB8MD_11, 0, 0, 0, 0,
2018 0, 0, 0, 0, 0, 0, 0, 0 } 2018 0, 0, 0, 0, 0, 0, 0, 0 ))
2019 }, 2019 },
2020 { PINMUX_CFG_REG("PBCR1", 0xfffe382c, 16, 4) { 2020 { PINMUX_CFG_REG("PBCR1", 0xfffe382c, 16, 4, GROUP(
2021 PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11, 0, 0, 0, 0, 2021 PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11, 0, 0, 0, 0,
2022 0, 0, 0, 0, 0, 0, 0, 0, 2022 0, 0, 0, 0, 0, 0, 0, 0,
2023 2023
@@ -2028,9 +2028,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2028 0, 0, 0, 0, 0, 0, 0, 0, 2028 0, 0, 0, 0, 0, 0, 0, 0,
2029 2029
2030 PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11, 0, 0, 0, 0, 2030 PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11, 0, 0, 0, 0,
2031 0, 0, 0, 0, 0, 0, 0, 0 } 2031 0, 0, 0, 0, 0, 0, 0, 0 ))
2032 }, 2032 },
2033 { PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4) { 2033 { PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4, GROUP(
2034 PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11, 0, 0, 0, 0, 2034 PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11, 0, 0, 0, 0,
2035 0, 0, 0, 0, 0, 0, 0, 0, 2035 0, 0, 0, 0, 0, 0, 0, 0,
2036 2036
@@ -2040,10 +2040,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2040 PB1MD_00, PB1MD_01, PB1MD_10, PB1MD_11, 0, 0, 0, 0, 2040 PB1MD_00, PB1MD_01, PB1MD_10, PB1MD_11, 0, 0, 0, 0,
2041 0, 0, 0, 0, 0, 0, 0, 0, 2041 0, 0, 0, 0, 0, 0, 0, 0,
2042 2042
2043 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 2043 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
2044 }, 2044 },
2045 2045
2046 { PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1) { 2046 { PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1, GROUP(
2047 0, 0, 0, 0, 0, 0, 0, 0, 2047 0, 0, 0, 0, 0, 0, 0, 0,
2048 0, 0, 0, 0, 0, 0, 0, 0, 2048 0, 0, 0, 0, 0, 0, 0, 0,
2049 0, 0, 2049 0, 0,
@@ -2053,9 +2053,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2053 PB19_IN, PB19_OUT, 2053 PB19_IN, PB19_OUT,
2054 PB18_IN, PB18_OUT, 2054 PB18_IN, PB18_OUT,
2055 PB17_IN, PB17_OUT, 2055 PB17_IN, PB17_OUT,
2056 PB16_IN, PB16_OUT } 2056 PB16_IN, PB16_OUT ))
2057 }, 2057 },
2058 { PINMUX_CFG_REG("PBIOR0", 0xfffe3832, 16, 1) { 2058 { PINMUX_CFG_REG("PBIOR0", 0xfffe3832, 16, 1, GROUP(
2059 PB15_IN, PB15_OUT, 2059 PB15_IN, PB15_OUT,
2060 PB14_IN, PB14_OUT, 2060 PB14_IN, PB14_OUT,
2061 PB13_IN, PB13_OUT, 2061 PB13_IN, PB13_OUT,
@@ -2071,10 +2071,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2071 PB3_IN, PB3_OUT, 2071 PB3_IN, PB3_OUT,
2072 PB2_IN, PB2_OUT, 2072 PB2_IN, PB2_OUT,
2073 PB1_IN, PB1_OUT, 2073 PB1_IN, PB1_OUT,
2074 0, 0 } 2074 0, 0 ))
2075 }, 2075 },
2076 2076
2077 { PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4) { 2077 { PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4, GROUP(
2078 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2078 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2079 2079
2080 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2080 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2083,9 +2083,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2083 2083
2084 PC8MD_000, PC8MD_001, PC8MD_010, PC8MD_011, 2084 PC8MD_000, PC8MD_001, PC8MD_010, PC8MD_011,
2085 PC8MD_100, PC8MD_101, PC8MD_110, PC8MD_111, 2085 PC8MD_100, PC8MD_101, PC8MD_110, PC8MD_111,
2086 0, 0, 0, 0, 0, 0, 0, 0 } 2086 0, 0, 0, 0, 0, 0, 0, 0 ))
2087 }, 2087 },
2088 { PINMUX_CFG_REG("PCCR1", 0xfffe384c, 16, 4) { 2088 { PINMUX_CFG_REG("PCCR1", 0xfffe384c, 16, 4, GROUP(
2089 PC7MD_000, PC7MD_001, PC7MD_010, PC7MD_011, 2089 PC7MD_000, PC7MD_001, PC7MD_010, PC7MD_011,
2090 PC7MD_100, PC7MD_101, PC7MD_110, PC7MD_111, 2090 PC7MD_100, PC7MD_101, PC7MD_110, PC7MD_111,
2091 0, 0, 0, 0, 0, 0, 0, 0, 2091 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2099,9 +2099,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2099 0, 0, 0, 0, 0, 0, 0, 0, 2099 0, 0, 0, 0, 0, 0, 0, 0,
2100 2100
2101 PC4MD_00, PC4MD_01, PC4MD_10, PC4MD_11, 0, 0, 0, 0, 2101 PC4MD_00, PC4MD_01, PC4MD_10, PC4MD_11, 0, 0, 0, 0,
2102 0, 0, 0, 0, 0, 0, 0, 0 } 2102 0, 0, 0, 0, 0, 0, 0, 0 ))
2103 }, 2103 },
2104 { PINMUX_CFG_REG("PCCR0", 0xfffe384e, 16, 4) { 2104 { PINMUX_CFG_REG("PCCR0", 0xfffe384e, 16, 4, GROUP(
2105 PC3MD_00, PC3MD_01, PC3MD_10, PC3MD_11, 0, 0, 0, 0, 2105 PC3MD_00, PC3MD_01, PC3MD_10, PC3MD_11, 0, 0, 0, 0,
2106 0, 0, 0, 0, 0, 0, 0, 0, 2106 0, 0, 0, 0, 0, 0, 0, 0,
2107 2107
@@ -2112,10 +2112,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2112 0, 0, 0, 0, 0, 0, 0, 0, 2112 0, 0, 0, 0, 0, 0, 0, 0,
2113 2113
2114 PC0MD_0, PC0MD_1, 0, 0, 0, 0, 0, 0, 2114 PC0MD_0, PC0MD_1, 0, 0, 0, 0, 0, 0,
2115 0, 0, 0, 0, 0, 0, 0, 0 } 2115 0, 0, 0, 0, 0, 0, 0, 0 ))
2116 }, 2116 },
2117 2117
2118 { PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1) { 2118 { PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1, GROUP(
2119 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2119 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2120 PC8_IN, PC8_OUT, 2120 PC8_IN, PC8_OUT,
2121 PC7_IN, PC7_OUT, 2121 PC7_IN, PC7_OUT,
@@ -2125,10 +2125,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2125 PC3_IN, PC3_OUT, 2125 PC3_IN, PC3_OUT,
2126 PC2_IN, PC2_OUT, 2126 PC2_IN, PC2_OUT,
2127 PC1_IN, PC1_OUT, 2127 PC1_IN, PC1_OUT,
2128 PC0_IN, PC0_OUT } 2128 PC0_IN, PC0_OUT ))
2129 }, 2129 },
2130 2130
2131 { PINMUX_CFG_REG("PDCR3", 0xfffe3868, 16, 4) { 2131 { PINMUX_CFG_REG("PDCR3", 0xfffe3868, 16, 4, GROUP(
2132 PD15MD_00, PD15MD_01, PD15MD_10, PD15MD_11, 0, 0, 0, 0, 2132 PD15MD_00, PD15MD_01, PD15MD_10, PD15MD_11, 0, 0, 0, 0,
2133 0, 0, 0, 0, 0, 0, 0, 0, 2133 0, 0, 0, 0, 0, 0, 0, 0,
2134 2134
@@ -2139,9 +2139,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2139 0, 0, 0, 0, 0, 0, 0, 0, 2139 0, 0, 0, 0, 0, 0, 0, 0,
2140 2140
2141 PD12MD_00, PD12MD_01, PD12MD_10, PD12MD_11, 0, 0, 0, 0, 2141 PD12MD_00, PD12MD_01, PD12MD_10, PD12MD_11, 0, 0, 0, 0,
2142 0, 0, 0, 0, 0, 0, 0, 0 } 2142 0, 0, 0, 0, 0, 0, 0, 0 ))
2143 }, 2143 },
2144 { PINMUX_CFG_REG("PDCR2", 0xfffe386a, 16, 4) { 2144 { PINMUX_CFG_REG("PDCR2", 0xfffe386a, 16, 4, GROUP(
2145 PD11MD_00, PD11MD_01, PD11MD_10, PD11MD_11, 0, 0, 0, 0, 2145 PD11MD_00, PD11MD_01, PD11MD_10, PD11MD_11, 0, 0, 0, 0,
2146 0, 0, 0, 0, 0, 0, 0, 0, 2146 0, 0, 0, 0, 0, 0, 0, 0,
2147 2147
@@ -2152,9 +2152,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2152 0, 0, 0, 0, 0, 0, 0, 0, 2152 0, 0, 0, 0, 0, 0, 0, 0,
2153 2153
2154 PD8MD_00, PD8MD_01, PD8MD_10, PD8MD_11, 0, 0, 0, 0, 2154 PD8MD_00, PD8MD_01, PD8MD_10, PD8MD_11, 0, 0, 0, 0,
2155 0, 0, 0, 0, 0, 0, 0, 0 } 2155 0, 0, 0, 0, 0, 0, 0, 0 ))
2156 }, 2156 },
2157 { PINMUX_CFG_REG("PDCR1", 0xfffe386c, 16, 4) { 2157 { PINMUX_CFG_REG("PDCR1", 0xfffe386c, 16, 4, GROUP(
2158 PD7MD_00, PD7MD_01, PD7MD_10, PD7MD_11, 0, 0, 0, 0, 2158 PD7MD_00, PD7MD_01, PD7MD_10, PD7MD_11, 0, 0, 0, 0,
2159 0, 0, 0, 0, 0, 0, 0, 0, 2159 0, 0, 0, 0, 0, 0, 0, 0,
2160 2160
@@ -2165,9 +2165,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2165 0, 0, 0, 0, 0, 0, 0, 0, 2165 0, 0, 0, 0, 0, 0, 0, 0,
2166 2166
2167 PD4MD_00, PD4MD_01, PD4MD_10, PD4MD_11, 0, 0, 0, 0, 2167 PD4MD_00, PD4MD_01, PD4MD_10, PD4MD_11, 0, 0, 0, 0,
2168 0, 0, 0, 0, 0, 0, 0, 0 } 2168 0, 0, 0, 0, 0, 0, 0, 0 ))
2169 }, 2169 },
2170 { PINMUX_CFG_REG("PDCR0", 0xfffe386e, 16, 4) { 2170 { PINMUX_CFG_REG("PDCR0", 0xfffe386e, 16, 4, GROUP(
2171 PD3MD_00, PD3MD_01, PD3MD_10, PD3MD_11, 0, 0, 0, 0, 2171 PD3MD_00, PD3MD_01, PD3MD_10, PD3MD_11, 0, 0, 0, 0,
2172 0, 0, 0, 0, 0, 0, 0, 0, 2172 0, 0, 0, 0, 0, 0, 0, 0,
2173 2173
@@ -2178,10 +2178,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2178 0, 0, 0, 0, 0, 0, 0, 0, 2178 0, 0, 0, 0, 0, 0, 0, 0,
2179 2179
2180 PD0MD_00, PD0MD_01, PD0MD_10, PD0MD_11, 0, 0, 0, 0, 2180 PD0MD_00, PD0MD_01, PD0MD_10, PD0MD_11, 0, 0, 0, 0,
2181 0, 0, 0, 0, 0, 0, 0, 0 } 2181 0, 0, 0, 0, 0, 0, 0, 0 ))
2182 }, 2182 },
2183 2183
2184 { PINMUX_CFG_REG("PDIOR0", 0xfffe3872, 16, 1) { 2184 { PINMUX_CFG_REG("PDIOR0", 0xfffe3872, 16, 1, GROUP(
2185 PD15_IN, PD15_OUT, 2185 PD15_IN, PD15_OUT,
2186 PD14_IN, PD14_OUT, 2186 PD14_IN, PD14_OUT,
2187 PD13_IN, PD13_OUT, 2187 PD13_IN, PD13_OUT,
@@ -2197,10 +2197,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2197 PD3_IN, PD3_OUT, 2197 PD3_IN, PD3_OUT,
2198 PD2_IN, PD2_OUT, 2198 PD2_IN, PD2_OUT,
2199 PD1_IN, PD1_OUT, 2199 PD1_IN, PD1_OUT,
2200 PD0_IN, PD0_OUT } 2200 PD0_IN, PD0_OUT ))
2201 }, 2201 },
2202 2202
2203 { PINMUX_CFG_REG("PECR1", 0xfffe388c, 16, 4) { 2203 { PINMUX_CFG_REG("PECR1", 0xfffe388c, 16, 4, GROUP(
2204 PE7MD_00, PE7MD_01, PE7MD_10, PE7MD_11, 0, 0, 0, 0, 2204 PE7MD_00, PE7MD_01, PE7MD_10, PE7MD_11, 0, 0, 0, 0,
2205 0, 0, 0, 0, 0, 0, 0, 0, 2205 0, 0, 0, 0, 0, 0, 0, 0,
2206 2206
@@ -2211,9 +2211,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2211 0, 0, 0, 0, 0, 0, 0, 0, 2211 0, 0, 0, 0, 0, 0, 0, 0,
2212 2212
2213 PE4MD_00, PE4MD_01, PE4MD_10, PE4MD_11, 0, 0, 0, 0, 2213 PE4MD_00, PE4MD_01, PE4MD_10, PE4MD_11, 0, 0, 0, 0,
2214 0, 0, 0, 0, 0, 0, 0, 0 } 2214 0, 0, 0, 0, 0, 0, 0, 0 ))
2215 }, 2215 },
2216 { PINMUX_CFG_REG("PECR0", 0xfffe388e, 16, 4) { 2216 { PINMUX_CFG_REG("PECR0", 0xfffe388e, 16, 4, GROUP(
2217 PE3MD_000, PE3MD_001, PE3MD_010, PE3MD_011, 2217 PE3MD_000, PE3MD_001, PE3MD_010, PE3MD_011,
2218 PE3MD_100, PE3MD_101, PE3MD_110, PE3MD_111, 2218 PE3MD_100, PE3MD_101, PE3MD_110, PE3MD_111,
2219 0, 0, 0, 0, 0, 0, 0, 0, 2219 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2227,9 +2227,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2227 0, 0, 0, 0, 0, 0, 0, 0, 2227 0, 0, 0, 0, 0, 0, 0, 0,
2228 2228
2229 PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11, 0, 0, 0, 0, 2229 PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11, 0, 0, 0, 0,
2230 0, 0, 0, 0, 0, 0, 0, 0 } 2230 0, 0, 0, 0, 0, 0, 0, 0 ))
2231 }, 2231 },
2232 { PINMUX_CFG_REG("PEIOR0", 0xfffe3892, 16, 1) { 2232 { PINMUX_CFG_REG("PEIOR0", 0xfffe3892, 16, 1, GROUP(
2233 0, 0, 0, 0, 0, 0, 0, 0, 2233 0, 0, 0, 0, 0, 0, 0, 0,
2234 0, 0, 0, 0, 0, 0, 0, 0, 2234 0, 0, 0, 0, 0, 0, 0, 0,
2235 PE7_IN, PE7_OUT, 2235 PE7_IN, PE7_OUT,
@@ -2239,10 +2239,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2239 PE3_IN, PE3_OUT, 2239 PE3_IN, PE3_OUT,
2240 PE2_IN, PE2_OUT, 2240 PE2_IN, PE2_OUT,
2241 PE1_IN, PE1_OUT, 2241 PE1_IN, PE1_OUT,
2242 PE0_IN, PE0_OUT } 2242 PE0_IN, PE0_OUT ))
2243 }, 2243 },
2244 2244
2245 { PINMUX_CFG_REG("PFCR6", 0xfffe38a2, 16, 4) { 2245 { PINMUX_CFG_REG("PFCR6", 0xfffe38a2, 16, 4, GROUP(
2246 PF23MD_000, PF23MD_001, PF23MD_010, PF23MD_011, 2246 PF23MD_000, PF23MD_001, PF23MD_010, PF23MD_011,
2247 PF23MD_100, PF23MD_101, PF23MD_110, PF23MD_111, 2247 PF23MD_100, PF23MD_101, PF23MD_110, PF23MD_111,
2248 0, 0, 0, 0, 0, 0, 0, 0, 2248 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2257,9 +2257,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2257 2257
2258 PF20MD_000, PF20MD_001, PF20MD_010, PF20MD_011, 2258 PF20MD_000, PF20MD_001, PF20MD_010, PF20MD_011,
2259 PF20MD_100, PF20MD_101, PF20MD_110, PF20MD_111, 2259 PF20MD_100, PF20MD_101, PF20MD_110, PF20MD_111,
2260 0, 0, 0, 0, 0, 0, 0, 0 } 2260 0, 0, 0, 0, 0, 0, 0, 0 ))
2261 }, 2261 },
2262 { PINMUX_CFG_REG("PFCR5", 0xfffe38a4, 16, 4) { 2262 { PINMUX_CFG_REG("PFCR5", 0xfffe38a4, 16, 4, GROUP(
2263 PF19MD_000, PF19MD_001, PF19MD_010, PF19MD_011, 2263 PF19MD_000, PF19MD_001, PF19MD_010, PF19MD_011,
2264 PF19MD_100, PF19MD_101, PF19MD_110, PF19MD_111, 2264 PF19MD_100, PF19MD_101, PF19MD_110, PF19MD_111,
2265 0, 0, 0, 0, 0, 0, 0, 0, 2265 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2274,9 +2274,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2274 2274
2275 PF16MD_000, PF16MD_001, PF16MD_010, PF16MD_011, 2275 PF16MD_000, PF16MD_001, PF16MD_010, PF16MD_011,
2276 PF16MD_100, PF16MD_101, PF16MD_110, PF16MD_111, 2276 PF16MD_100, PF16MD_101, PF16MD_110, PF16MD_111,
2277 0, 0, 0, 0, 0, 0, 0, 0 } 2277 0, 0, 0, 0, 0, 0, 0, 0 ))
2278 }, 2278 },
2279 { PINMUX_CFG_REG("PFCR4", 0xfffe38a6, 16, 4) { 2279 { PINMUX_CFG_REG("PFCR4", 0xfffe38a6, 16, 4, GROUP(
2280 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2280 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2281 2281
2282 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2282 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2285,9 +2285,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2285 2285
2286 PF15MD_000, PF15MD_001, PF15MD_010, PF15MD_011, 2286 PF15MD_000, PF15MD_001, PF15MD_010, PF15MD_011,
2287 PF15MD_100, PF15MD_101, PF15MD_110, PF15MD_111, 2287 PF15MD_100, PF15MD_101, PF15MD_110, PF15MD_111,
2288 0, 0, 0, 0, 0, 0, 0, 0 } 2288 0, 0, 0, 0, 0, 0, 0, 0 ))
2289 }, 2289 },
2290 { PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4) { 2290 { PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4, GROUP(
2291 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2291 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2292 2292
2293 PF14MD_000, PF14MD_001, PF14MD_010, PF14MD_011, 2293 PF14MD_000, PF14MD_001, PF14MD_010, PF14MD_011,
@@ -2300,9 +2300,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2300 2300
2301 PF12MD_000, PF12MD_001, PF12MD_010, PF12MD_011, 2301 PF12MD_000, PF12MD_001, PF12MD_010, PF12MD_011,
2302 PF12MD_100, PF12MD_101, PF12MD_110, PF12MD_111, 2302 PF12MD_100, PF12MD_101, PF12MD_110, PF12MD_111,
2303 0, 0, 0, 0, 0, 0, 0, 0 } 2303 0, 0, 0, 0, 0, 0, 0, 0 ))
2304 }, 2304 },
2305 { PINMUX_CFG_REG("PFCR2", 0xfffe38aa, 16, 4) { 2305 { PINMUX_CFG_REG("PFCR2", 0xfffe38aa, 16, 4, GROUP(
2306 PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011, 2306 PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011,
2307 PF11MD_100, PF11MD_101, PF11MD_110, PF11MD_111, 2307 PF11MD_100, PF11MD_101, PF11MD_110, PF11MD_111,
2308 0, 0, 0, 0, 0, 0, 0, 0, 2308 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2317,9 +2317,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2317 2317
2318 PF8MD_000, PF8MD_001, PF8MD_010, PF8MD_011, 2318 PF8MD_000, PF8MD_001, PF8MD_010, PF8MD_011,
2319 PF8MD_100, PF8MD_101, PF8MD_110, PF8MD_111, 2319 PF8MD_100, PF8MD_101, PF8MD_110, PF8MD_111,
2320 0, 0, 0, 0, 0, 0, 0, 0 } 2320 0, 0, 0, 0, 0, 0, 0, 0 ))
2321 }, 2321 },
2322 { PINMUX_CFG_REG("PFCR1", 0xfffe38ac, 16, 4) { 2322 { PINMUX_CFG_REG("PFCR1", 0xfffe38ac, 16, 4, GROUP(
2323 PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011, 2323 PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011,
2324 PF7MD_100, PF7MD_101, PF7MD_110, PF7MD_111, 2324 PF7MD_100, PF7MD_101, PF7MD_110, PF7MD_111,
2325 0, 0, 0, 0, 0, 0, 0, 0, 2325 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2334,9 +2334,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2334 2334
2335 PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011, 2335 PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011,
2336 PF4MD_100, PF4MD_101, PF4MD_110, PF4MD_111, 2336 PF4MD_100, PF4MD_101, PF4MD_110, PF4MD_111,
2337 0, 0, 0, 0, 0, 0, 0, 0 } 2337 0, 0, 0, 0, 0, 0, 0, 0 ))
2338 }, 2338 },
2339 { PINMUX_CFG_REG("PFCR0", 0xfffe38ae, 16, 4) { 2339 { PINMUX_CFG_REG("PFCR0", 0xfffe38ae, 16, 4, GROUP(
2340 PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011, 2340 PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011,
2341 PF3MD_100, PF3MD_101, PF3MD_110, PF3MD_111, 2341 PF3MD_100, PF3MD_101, PF3MD_110, PF3MD_111,
2342 0, 0, 0, 0, 0, 0, 0, 0, 2342 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2351,10 +2351,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2351 2351
2352 PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011, 2352 PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011,
2353 PF0MD_100, PF0MD_101, PF0MD_110, PF0MD_111, 2353 PF0MD_100, PF0MD_101, PF0MD_110, PF0MD_111,
2354 0, 0, 0, 0, 0, 0, 0, 0 } 2354 0, 0, 0, 0, 0, 0, 0, 0 ))
2355 }, 2355 },
2356 2356
2357 { PINMUX_CFG_REG("PFIOR1", 0xfffe38b0, 16, 1) { 2357 { PINMUX_CFG_REG("PFIOR1", 0xfffe38b0, 16, 1, GROUP(
2358 0, 0, 0, 0, 0, 0, 0, 0, 2358 0, 0, 0, 0, 0, 0, 0, 0,
2359 0, 0, 0, 0, 0, 0, 0, 0, 2359 0, 0, 0, 0, 0, 0, 0, 0,
2360 PF23_IN, PF23_OUT, 2360 PF23_IN, PF23_OUT,
@@ -2364,9 +2364,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2364 PF19_IN, PF19_OUT, 2364 PF19_IN, PF19_OUT,
2365 PF18_IN, PF18_OUT, 2365 PF18_IN, PF18_OUT,
2366 PF17_IN, PF17_OUT, 2366 PF17_IN, PF17_OUT,
2367 PF16_IN, PF16_OUT } 2367 PF16_IN, PF16_OUT ))
2368 }, 2368 },
2369 { PINMUX_CFG_REG("PFIOR0", 0xfffe38b2, 16, 1) { 2369 { PINMUX_CFG_REG("PFIOR0", 0xfffe38b2, 16, 1, GROUP(
2370 PF15_IN, PF15_OUT, 2370 PF15_IN, PF15_OUT,
2371 PF14_IN, PF14_OUT, 2371 PF14_IN, PF14_OUT,
2372 PF13_IN, PF13_OUT, 2372 PF13_IN, PF13_OUT,
@@ -2382,10 +2382,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2382 PF3_IN, PF3_OUT, 2382 PF3_IN, PF3_OUT,
2383 PF2_IN, PF2_OUT, 2383 PF2_IN, PF2_OUT,
2384 PF1_IN, PF1_OUT, 2384 PF1_IN, PF1_OUT,
2385 PF0_IN, PF0_OUT } 2385 PF0_IN, PF0_OUT ))
2386 }, 2386 },
2387 2387
2388 { PINMUX_CFG_REG("PGCR6", 0xfffe38c2, 16, 4) { 2388 { PINMUX_CFG_REG("PGCR6", 0xfffe38c2, 16, 4, GROUP(
2389 PG27MD_00, PG27MD_01, PG27MD_10, PG27MD_11, 0, 0, 0, 0, 2389 PG27MD_00, PG27MD_01, PG27MD_10, PG27MD_11, 0, 0, 0, 0,
2390 0, 0, 0, 0, 0, 0, 0, 0, 2390 0, 0, 0, 0, 0, 0, 0, 0,
2391 2391
@@ -2396,9 +2396,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2396 0, 0, 0, 0, 0, 0, 0, 0, 2396 0, 0, 0, 0, 0, 0, 0, 0,
2397 2397
2398 PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11, 0, 0, 0, 0, 2398 PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11, 0, 0, 0, 0,
2399 0, 0, 0, 0, 0, 0, 0, 0 } 2399 0, 0, 0, 0, 0, 0, 0, 0 ))
2400 }, 2400 },
2401 { PINMUX_CFG_REG("PGCR5", 0xfffe38c4, 16, 4) { 2401 { PINMUX_CFG_REG("PGCR5", 0xfffe38c4, 16, 4, GROUP(
2402 PG23MD_000, PG23MD_001, PG23MD_010, PG23MD_011, 2402 PG23MD_000, PG23MD_001, PG23MD_010, PG23MD_011,
2403 PG23MD_100, PG23MD_101, PG23MD_110, PG23MD_111, 2403 PG23MD_100, PG23MD_101, PG23MD_110, PG23MD_111,
2404 0, 0, 0, 0, 0, 0, 0, 0, 2404 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2413,9 +2413,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2413 2413
2414 PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011, 2414 PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011,
2415 PG20MD_100, PG20MD_101, PG20MD_110, PG20MD_111, 2415 PG20MD_100, PG20MD_101, PG20MD_110, PG20MD_111,
2416 0, 0, 0, 0, 0, 0, 0, 0 } 2416 0, 0, 0, 0, 0, 0, 0, 0 ))
2417 }, 2417 },
2418 { PINMUX_CFG_REG("PGCR4", 0xfffe38c6, 16, 4) { 2418 { PINMUX_CFG_REG("PGCR4", 0xfffe38c6, 16, 4, GROUP(
2419 PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011, 2419 PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011,
2420 PG19MD_100, PG19MD_101, PG19MD_110, PG19MD_111, 2420 PG19MD_100, PG19MD_101, PG19MD_110, PG19MD_111,
2421 0, 0, 0, 0, 0, 0, 0, 0, 2421 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2428,9 +2428,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2428 0, 0, 0, 0, 0, 0, 0, 0, 2428 0, 0, 0, 0, 0, 0, 0, 0,
2429 2429
2430 PG16MD_00, PG16MD_01, PG16MD_10, PG16MD_11, 0, 0, 0, 0, 2430 PG16MD_00, PG16MD_01, PG16MD_10, PG16MD_11, 0, 0, 0, 0,
2431 0, 0, 0, 0, 0, 0, 0, 0 } 2431 0, 0, 0, 0, 0, 0, 0, 0 ))
2432 }, 2432 },
2433 { PINMUX_CFG_REG("PGCR3", 0xfffe38c8, 16, 4) { 2433 { PINMUX_CFG_REG("PGCR3", 0xfffe38c8, 16, 4, GROUP(
2434 PG15MD_00, PG15MD_01, PG15MD_10, PG15MD_11, 0, 0, 0, 0, 2434 PG15MD_00, PG15MD_01, PG15MD_10, PG15MD_11, 0, 0, 0, 0,
2435 0, 0, 0, 0, 0, 0, 0, 0, 2435 0, 0, 0, 0, 0, 0, 0, 0,
2436 2436
@@ -2441,9 +2441,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2441 0, 0, 0, 0, 0, 0, 0, 0, 2441 0, 0, 0, 0, 0, 0, 0, 0,
2442 2442
2443 PG12MD_00, PG12MD_01, PG12MD_10, PG12MD_11, 0, 0, 0, 0, 2443 PG12MD_00, PG12MD_01, PG12MD_10, PG12MD_11, 0, 0, 0, 0,
2444 0, 0, 0, 0, 0, 0, 0, 0 } 2444 0, 0, 0, 0, 0, 0, 0, 0 ))
2445 }, 2445 },
2446 { PINMUX_CFG_REG("PGCR2", 0xfffe38ca, 16, 4) { 2446 { PINMUX_CFG_REG("PGCR2", 0xfffe38ca, 16, 4, GROUP(
2447 PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011, 2447 PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011,
2448 PG11MD_100, PG11MD_101, PG11MD_110, PG11MD_111, 2448 PG11MD_100, PG11MD_101, PG11MD_110, PG11MD_111,
2449 0, 0, 0, 0, 0, 0, 0, 0, 2449 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2458,10 +2458,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2458 2458
2459 PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011, 2459 PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011,
2460 PG8MD_100, PG8MD_101, PG8MD_110, PG8MD_111, 2460 PG8MD_100, PG8MD_101, PG8MD_110, PG8MD_111,
2461 0, 0, 0, 0, 0, 0, 0, 0 } 2461 0, 0, 0, 0, 0, 0, 0, 0 ))
2462 }, 2462 },
2463 2463
2464 { PINMUX_CFG_REG("PGCR1", 0xfffe38cc, 16, 4) { 2464 { PINMUX_CFG_REG("PGCR1", 0xfffe38cc, 16, 4, GROUP(
2465 PG7MD_000, PG7MD_001, PG7MD_010, PG7MD_011, 2465 PG7MD_000, PG7MD_001, PG7MD_010, PG7MD_011,
2466 PG7MD_100, PG7MD_101, PG7MD_110, PG7MD_111, 2466 PG7MD_100, PG7MD_101, PG7MD_110, PG7MD_111,
2467 0, 0, 0, 0, 0, 0, 0, 0, 2467 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2476,9 +2476,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2476 2476
2477 PG4MD_000, PG4MD_001, PG4MD_010, PG4MD_011, 2477 PG4MD_000, PG4MD_001, PG4MD_010, PG4MD_011,
2478 PG4MD_100, PG4MD_101, PG4MD_110, PG4MD_111, 2478 PG4MD_100, PG4MD_101, PG4MD_110, PG4MD_111,
2479 0, 0, 0, 0, 0, 0, 0, 0 } 2479 0, 0, 0, 0, 0, 0, 0, 0 ))
2480 }, 2480 },
2481 { PINMUX_CFG_REG("PGCR0", 0xfffe38ce, 16, 4) { 2481 { PINMUX_CFG_REG("PGCR0", 0xfffe38ce, 16, 4, GROUP(
2482 PG3MD_000, PG3MD_001, PG3MD_010, PG3MD_011, 2482 PG3MD_000, PG3MD_001, PG3MD_010, PG3MD_011,
2483 PG3MD_100, PG3MD_101, PG3MD_110, PG3MD_111, 2483 PG3MD_100, PG3MD_101, PG3MD_110, PG3MD_111,
2484 0, 0, 0, 0, 0, 0, 0, 0, 2484 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2493,10 +2493,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2493 2493
2494 PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011, 2494 PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011,
2495 PG0MD_100, PG0MD_101, PG0MD_110, PG0MD_111, 2495 PG0MD_100, PG0MD_101, PG0MD_110, PG0MD_111,
2496 0, 0, 0, 0, 0, 0, 0, 0 } 2496 0, 0, 0, 0, 0, 0, 0, 0 ))
2497 }, 2497 },
2498 2498
2499 { PINMUX_CFG_REG("PGIOR1", 0xfffe38d0, 16, 1) { 2499 { PINMUX_CFG_REG("PGIOR1", 0xfffe38d0, 16, 1, GROUP(
2500 0, 0, 0, 0, 0, 0, 0, 0, 2500 0, 0, 0, 0, 0, 0, 0, 0,
2501 PG27_IN, PG27_OUT, 2501 PG27_IN, PG27_OUT,
2502 PG26_IN, PG26_OUT, 2502 PG26_IN, PG26_OUT,
@@ -2509,9 +2509,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2509 PG19_IN, PG19_OUT, 2509 PG19_IN, PG19_OUT,
2510 PG18_IN, PG18_OUT, 2510 PG18_IN, PG18_OUT,
2511 PG17_IN, PG17_OUT, 2511 PG17_IN, PG17_OUT,
2512 PG16_IN, PG16_OUT } 2512 PG16_IN, PG16_OUT ))
2513 }, 2513 },
2514 { PINMUX_CFG_REG("PGIOR0", 0xfffe38d2, 16, 1) { 2514 { PINMUX_CFG_REG("PGIOR0", 0xfffe38d2, 16, 1, GROUP(
2515 PG15_IN, PG15_OUT, 2515 PG15_IN, PG15_OUT,
2516 PG14_IN, PG14_OUT, 2516 PG14_IN, PG14_OUT,
2517 PG13_IN, PG13_OUT, 2517 PG13_IN, PG13_OUT,
@@ -2527,10 +2527,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2527 PG3_IN, PG3_OUT, 2527 PG3_IN, PG3_OUT,
2528 PG2_IN, PG2_OUT, 2528 PG2_IN, PG2_OUT,
2529 PG1_IN, PG1_OUT, 2529 PG1_IN, PG1_OUT,
2530 PG0_IN, PG0_OUT } 2530 PG0_IN, PG0_OUT ))
2531 }, 2531 },
2532 2532
2533 { PINMUX_CFG_REG("PHCR1", 0xfffe38ec, 16, 4) { 2533 { PINMUX_CFG_REG("PHCR1", 0xfffe38ec, 16, 4, GROUP(
2534 PH7MD_00, PH7MD_01, PH7MD_10, PH7MD_11, 0, 0, 0, 0, 2534 PH7MD_00, PH7MD_01, PH7MD_10, PH7MD_11, 0, 0, 0, 0,
2535 0, 0, 0, 0, 0, 0, 0, 0, 2535 0, 0, 0, 0, 0, 0, 0, 0,
2536 2536
@@ -2541,10 +2541,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2541 0, 0, 0, 0, 0, 0, 0, 0, 2541 0, 0, 0, 0, 0, 0, 0, 0,
2542 2542
2543 PH4MD_00, PH4MD_01, PH4MD_10, PH4MD_11, 0, 0, 0, 0, 2543 PH4MD_00, PH4MD_01, PH4MD_10, PH4MD_11, 0, 0, 0, 0,
2544 0, 0, 0, 0, 0, 0, 0, 0 } 2544 0, 0, 0, 0, 0, 0, 0, 0 ))
2545 }, 2545 },
2546 2546
2547 { PINMUX_CFG_REG("PHCR0", 0xfffe38ee, 16, 4) { 2547 { PINMUX_CFG_REG("PHCR0", 0xfffe38ee, 16, 4, GROUP(
2548 PH3MD_00, PH3MD_01, PH3MD_10, PH3MD_11, 0, 0, 0, 0, 2548 PH3MD_00, PH3MD_01, PH3MD_10, PH3MD_11, 0, 0, 0, 0,
2549 0, 0, 0, 0, 0, 0, 0, 0, 2549 0, 0, 0, 0, 0, 0, 0, 0,
2550 2550
@@ -2555,10 +2555,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2555 0, 0, 0, 0, 0, 0, 0, 0, 2555 0, 0, 0, 0, 0, 0, 0, 0,
2556 2556
2557 PH0MD_00, PH0MD_01, PH0MD_10, PH0MD_11, 0, 0, 0, 0, 2557 PH0MD_00, PH0MD_01, PH0MD_10, PH0MD_11, 0, 0, 0, 0,
2558 0, 0, 0, 0, 0, 0, 0, 0 } 2558 0, 0, 0, 0, 0, 0, 0, 0 ))
2559 }, 2559 },
2560 2560
2561 { PINMUX_CFG_REG("PJCR7", 0xfffe3900, 16, 4) { 2561 { PINMUX_CFG_REG("PJCR7", 0xfffe3900, 16, 4, GROUP(
2562 PJ31MD_0, PJ31MD_1, 0, 0, 0, 0, 0, 0, 2562 PJ31MD_0, PJ31MD_1, 0, 0, 0, 0, 0, 0,
2563 0, 0, 0, 0, 0, 0, 0, 0, 2563 0, 0, 0, 0, 0, 0, 0, 0,
2564 2564
@@ -2572,9 +2572,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2572 2572
2573 PJ28MD_000, PJ28MD_001, PJ28MD_010, PJ28MD_011, 2573 PJ28MD_000, PJ28MD_001, PJ28MD_010, PJ28MD_011,
2574 PJ28MD_100, PJ28MD_101, PJ28MD_110, PJ28MD_111, 2574 PJ28MD_100, PJ28MD_101, PJ28MD_110, PJ28MD_111,
2575 0, 0, 0, 0, 0, 0, 0, 0 } 2575 0, 0, 0, 0, 0, 0, 0, 0 ))
2576 }, 2576 },
2577 { PINMUX_CFG_REG("PJCR6", 0xfffe3902, 16, 4) { 2577 { PINMUX_CFG_REG("PJCR6", 0xfffe3902, 16, 4, GROUP(
2578 PJ27MD_000, PJ27MD_001, PJ27MD_010, PJ27MD_011, 2578 PJ27MD_000, PJ27MD_001, PJ27MD_010, PJ27MD_011,
2579 PJ27MD_100, PJ27MD_101, PJ27MD_110, PJ27MD_111, 2579 PJ27MD_100, PJ27MD_101, PJ27MD_110, PJ27MD_111,
2580 0, 0, 0, 0, 0, 0, 0, 0, 2580 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2589,9 +2589,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2589 2589
2590 PJ24MD_000, PJ24MD_001, PJ24MD_010, PJ24MD_011, 2590 PJ24MD_000, PJ24MD_001, PJ24MD_010, PJ24MD_011,
2591 PJ24MD_100, PJ24MD_101, PJ24MD_110, PJ24MD_111, 2591 PJ24MD_100, PJ24MD_101, PJ24MD_110, PJ24MD_111,
2592 0, 0, 0, 0, 0, 0, 0, 0 } 2592 0, 0, 0, 0, 0, 0, 0, 0 ))
2593 }, 2593 },
2594 { PINMUX_CFG_REG("PJCR5", 0xfffe3904, 16, 4) { 2594 { PINMUX_CFG_REG("PJCR5", 0xfffe3904, 16, 4, GROUP(
2595 PJ23MD_000, PJ23MD_001, PJ23MD_010, PJ23MD_011, 2595 PJ23MD_000, PJ23MD_001, PJ23MD_010, PJ23MD_011,
2596 PJ23MD_100, PJ23MD_101, PJ23MD_110, PJ23MD_111, 2596 PJ23MD_100, PJ23MD_101, PJ23MD_110, PJ23MD_111,
2597 0, 0, 0, 0, 0, 0, 0, 0, 2597 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2606,9 +2606,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2606 2606
2607 PJ20MD_000, PJ20MD_001, PJ20MD_010, PJ20MD_011, 2607 PJ20MD_000, PJ20MD_001, PJ20MD_010, PJ20MD_011,
2608 PJ20MD_100, PJ20MD_101, PJ20MD_110, PJ20MD_111, 2608 PJ20MD_100, PJ20MD_101, PJ20MD_110, PJ20MD_111,
2609 0, 0, 0, 0, 0, 0, 0, 0 } 2609 0, 0, 0, 0, 0, 0, 0, 0 ))
2610 }, 2610 },
2611 { PINMUX_CFG_REG("PJCR4", 0xfffe3906, 16, 4) { 2611 { PINMUX_CFG_REG("PJCR4", 0xfffe3906, 16, 4, GROUP(
2612 PJ19MD_000, PJ19MD_001, PJ19MD_010, PJ19MD_011, 2612 PJ19MD_000, PJ19MD_001, PJ19MD_010, PJ19MD_011,
2613 PJ19MD_100, PJ19MD_101, PJ19MD_110, PJ19MD_111, 2613 PJ19MD_100, PJ19MD_101, PJ19MD_110, PJ19MD_111,
2614 0, 0, 0, 0, 0, 0, 0, 0, 2614 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2623,9 +2623,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2623 2623
2624 PJ16MD_000, PJ16MD_001, PJ16MD_010, PJ16MD_011, 2624 PJ16MD_000, PJ16MD_001, PJ16MD_010, PJ16MD_011,
2625 PJ16MD_100, PJ16MD_101, PJ16MD_110, PJ16MD_111, 2625 PJ16MD_100, PJ16MD_101, PJ16MD_110, PJ16MD_111,
2626 0, 0, 0, 0, 0, 0, 0, 0 } 2626 0, 0, 0, 0, 0, 0, 0, 0 ))
2627 }, 2627 },
2628 { PINMUX_CFG_REG("PJCR3", 0xfffe3908, 16, 4) { 2628 { PINMUX_CFG_REG("PJCR3", 0xfffe3908, 16, 4, GROUP(
2629 PJ15MD_000, PJ15MD_001, PJ15MD_010, PJ15MD_011, 2629 PJ15MD_000, PJ15MD_001, PJ15MD_010, PJ15MD_011,
2630 PJ15MD_100, PJ15MD_101, PJ15MD_110, PJ15MD_111, 2630 PJ15MD_100, PJ15MD_101, PJ15MD_110, PJ15MD_111,
2631 0, 0, 0, 0, 0, 0, 0, 0, 2631 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2640,9 +2640,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2640 2640
2641 PJ12MD_000, PJ12MD_001, PJ12MD_010, PJ12MD_011, 2641 PJ12MD_000, PJ12MD_001, PJ12MD_010, PJ12MD_011,
2642 PJ12MD_100, PJ12MD_101, PJ12MD_110, PJ12MD_111, 2642 PJ12MD_100, PJ12MD_101, PJ12MD_110, PJ12MD_111,
2643 0, 0, 0, 0, 0, 0, 0, 0 } 2643 0, 0, 0, 0, 0, 0, 0, 0 ))
2644 }, 2644 },
2645 { PINMUX_CFG_REG("PJCR2", 0xfffe390a, 16, 4) { 2645 { PINMUX_CFG_REG("PJCR2", 0xfffe390a, 16, 4, GROUP(
2646 PJ11MD_000, PJ11MD_001, PJ11MD_010, PJ11MD_011, 2646 PJ11MD_000, PJ11MD_001, PJ11MD_010, PJ11MD_011,
2647 PJ11MD_100, PJ11MD_101, PJ11MD_110, PJ11MD_111, 2647 PJ11MD_100, PJ11MD_101, PJ11MD_110, PJ11MD_111,
2648 0, 0, 0, 0, 0, 0, 0, 0, 2648 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2657,9 +2657,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2657 2657
2658 PJ8MD_000, PJ8MD_001, PJ8MD_010, PJ8MD_011, 2658 PJ8MD_000, PJ8MD_001, PJ8MD_010, PJ8MD_011,
2659 PJ8MD_100, PJ8MD_101, PJ8MD_110, PJ8MD_111, 2659 PJ8MD_100, PJ8MD_101, PJ8MD_110, PJ8MD_111,
2660 0, 0, 0, 0, 0, 0, 0, 0 } 2660 0, 0, 0, 0, 0, 0, 0, 0 ))
2661 }, 2661 },
2662 { PINMUX_CFG_REG("PJCR1", 0xfffe390c, 16, 4) { 2662 { PINMUX_CFG_REG("PJCR1", 0xfffe390c, 16, 4, GROUP(
2663 PJ7MD_000, PJ7MD_001, PJ7MD_010, PJ7MD_011, 2663 PJ7MD_000, PJ7MD_001, PJ7MD_010, PJ7MD_011,
2664 PJ7MD_100, PJ7MD_101, PJ7MD_110, PJ7MD_111, 2664 PJ7MD_100, PJ7MD_101, PJ7MD_110, PJ7MD_111,
2665 0, 0, 0, 0, 0, 0, 0, 0, 2665 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2674,9 +2674,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2674 2674
2675 PJ4MD_000, PJ4MD_001, PJ4MD_010, PJ4MD_011, 2675 PJ4MD_000, PJ4MD_001, PJ4MD_010, PJ4MD_011,
2676 PJ4MD_100, PJ4MD_101, PJ4MD_110, PJ4MD_111, 2676 PJ4MD_100, PJ4MD_101, PJ4MD_110, PJ4MD_111,
2677 0, 0, 0, 0, 0, 0, 0, 0 } 2677 0, 0, 0, 0, 0, 0, 0, 0 ))
2678 }, 2678 },
2679 { PINMUX_CFG_REG("PJCR0", 0xfffe390e, 16, 4) { 2679 { PINMUX_CFG_REG("PJCR0", 0xfffe390e, 16, 4, GROUP(
2680 PJ3MD_000, PJ3MD_001, PJ3MD_010, PJ3MD_011, 2680 PJ3MD_000, PJ3MD_001, PJ3MD_010, PJ3MD_011,
2681 PJ3MD_100, PJ3MD_101, PJ3MD_110, PJ3MD_111, 2681 PJ3MD_100, PJ3MD_101, PJ3MD_110, PJ3MD_111,
2682 0, 0, 0, 0, 0, 0, 0, 0, 2682 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2691,10 +2691,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2691 2691
2692 PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011, 2692 PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011,
2693 PJ0MD_100, PJ0MD_101, PJ0MD_110, PJ0MD_111, 2693 PJ0MD_100, PJ0MD_101, PJ0MD_110, PJ0MD_111,
2694 0, 0, 0, 0, 0, 0, 0, 0 } 2694 0, 0, 0, 0, 0, 0, 0, 0 ))
2695 }, 2695 },
2696 2696
2697 { PINMUX_CFG_REG("PJIOR1", 0xfffe3910, 16, 1) { 2697 { PINMUX_CFG_REG("PJIOR1", 0xfffe3910, 16, 1, GROUP(
2698 PJ31_IN, PJ31_OUT, 2698 PJ31_IN, PJ31_OUT,
2699 PJ30_IN, PJ30_OUT, 2699 PJ30_IN, PJ30_OUT,
2700 PJ29_IN, PJ29_OUT, 2700 PJ29_IN, PJ29_OUT,
@@ -2710,9 +2710,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2710 PJ19_IN, PJ19_OUT, 2710 PJ19_IN, PJ19_OUT,
2711 PJ18_IN, PJ18_OUT, 2711 PJ18_IN, PJ18_OUT,
2712 PJ17_IN, PJ17_OUT, 2712 PJ17_IN, PJ17_OUT,
2713 PJ16_IN, PJ16_OUT } 2713 PJ16_IN, PJ16_OUT ))
2714 }, 2714 },
2715 { PINMUX_CFG_REG("PJIOR0", 0xfffe3912, 16, 1) { 2715 { PINMUX_CFG_REG("PJIOR0", 0xfffe3912, 16, 1, GROUP(
2716 PJ15_IN, PJ15_OUT, 2716 PJ15_IN, PJ15_OUT,
2717 PJ14_IN, PJ14_OUT, 2717 PJ14_IN, PJ14_OUT,
2718 PJ13_IN, PJ13_OUT, 2718 PJ13_IN, PJ13_OUT,
@@ -2728,86 +2728,86 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2728 PJ3_IN, PJ3_OUT, 2728 PJ3_IN, PJ3_OUT,
2729 PJ2_IN, PJ2_OUT, 2729 PJ2_IN, PJ2_OUT,
2730 PJ1_IN, PJ1_OUT, 2730 PJ1_IN, PJ1_OUT,
2731 PJ0_IN, PJ0_OUT } 2731 PJ0_IN, PJ0_OUT ))
2732 }, 2732 },
2733 2733
2734 {} 2734 {}
2735}; 2735};
2736 2736
2737static const struct pinmux_data_reg pinmux_data_regs[] = { 2737static const struct pinmux_data_reg pinmux_data_regs[] = {
2738 { PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) { 2738 { PINMUX_DATA_REG("PADR0", 0xfffe3816, 16, GROUP(
2739 0, 0, 0, 0, 0, 0, 0, PA1_DATA, 2739 0, 0, 0, 0, 0, 0, 0, PA1_DATA,
2740 0, 0, 0, 0, 0, 0, 0, PA0_DATA } 2740 0, 0, 0, 0, 0, 0, 0, PA0_DATA ))
2741 }, 2741 },
2742 2742
2743 { PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16) { 2743 { PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16, GROUP(
2744 0, 0, 0, 0, 0, 0, 0, 0, 2744 0, 0, 0, 0, 0, 0, 0, 0,
2745 0, PB22_DATA, PB21_DATA, PB20_DATA, 2745 0, PB22_DATA, PB21_DATA, PB20_DATA,
2746 PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA } 2746 PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA ))
2747 }, 2747 },
2748 { PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16) { 2748 { PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16, GROUP(
2749 PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA, 2749 PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA,
2750 PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA, 2750 PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
2751 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, 2751 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
2752 PB3_DATA, PB2_DATA, PB1_DATA, 0 } 2752 PB3_DATA, PB2_DATA, PB1_DATA, 0 ))
2753 }, 2753 },
2754 2754
2755 { PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16) { 2755 { PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16, GROUP(
2756 0, 0, 0, 0, 2756 0, 0, 0, 0,
2757 0, 0, 0, PC8_DATA, 2757 0, 0, 0, PC8_DATA,
2758 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, 2758 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
2759 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA } 2759 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
2760 }, 2760 },
2761 2761
2762 { PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16) { 2762 { PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16, GROUP(
2763 PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA, 2763 PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
2764 PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA, 2764 PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
2765 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, 2765 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
2766 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA } 2766 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
2767 }, 2767 },
2768 2768
2769 { PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16) { 2769 { PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16, GROUP(
2770 0, 0, 0, 0, 0, 0, 0, 0, 2770 0, 0, 0, 0, 0, 0, 0, 0,
2771 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA, 2771 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
2772 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA } 2772 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA ))
2773 }, 2773 },
2774 2774
2775 { PINMUX_DATA_REG("PFDR1", 0xfffe38b4, 16) { 2775 { PINMUX_DATA_REG("PFDR1", 0xfffe38b4, 16, GROUP(
2776 0, 0, 0, 0, 0, 0, 0, 0, 2776 0, 0, 0, 0, 0, 0, 0, 0,
2777 PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA, 2777 PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA,
2778 PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA } 2778 PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA ))
2779 }, 2779 },
2780 { PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16) { 2780 { PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16, GROUP(
2781 PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA, 2781 PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA,
2782 PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA, 2782 PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
2783 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, 2783 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
2784 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA } 2784 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
2785 }, 2785 },
2786 2786
2787 { PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16) { 2787 { PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16, GROUP(
2788 0, 0, 0, 0, 2788 0, 0, 0, 0,
2789 PG27_DATA, PG26_DATA, PG25_DATA, PG24_DATA, 2789 PG27_DATA, PG26_DATA, PG25_DATA, PG24_DATA,
2790 PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA, 2790 PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA,
2791 PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA } 2791 PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA ))
2792 }, 2792 },
2793 { PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16) { 2793 { PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16, GROUP(
2794 PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA, 2794 PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA,
2795 PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA, 2795 PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA,
2796 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA, 2796 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
2797 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA } 2797 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA ))
2798 }, 2798 },
2799 2799
2800 { PINMUX_DATA_REG("PJDR1", 0xfffe3914, 16) { 2800 { PINMUX_DATA_REG("PJDR1", 0xfffe3914, 16, GROUP(
2801 PJ31_DATA, PJ30_DATA, PJ29_DATA, PJ28_DATA, 2801 PJ31_DATA, PJ30_DATA, PJ29_DATA, PJ28_DATA,
2802 PJ27_DATA, PJ26_DATA, PJ25_DATA, PJ24_DATA, 2802 PJ27_DATA, PJ26_DATA, PJ25_DATA, PJ24_DATA,
2803 PJ23_DATA, PJ22_DATA, PJ21_DATA, PJ20_DATA, 2803 PJ23_DATA, PJ22_DATA, PJ21_DATA, PJ20_DATA,
2804 PJ19_DATA, PJ18_DATA, PJ17_DATA, PJ16_DATA } 2804 PJ19_DATA, PJ18_DATA, PJ17_DATA, PJ16_DATA ))
2805 }, 2805 },
2806 { PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16) { 2806 { PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16, GROUP(
2807 PJ15_DATA, PJ14_DATA, PJ13_DATA, PJ12_DATA, 2807 PJ15_DATA, PJ14_DATA, PJ13_DATA, PJ12_DATA,
2808 PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA, 2808 PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA,
2809 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA, 2809 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
2810 PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA } 2810 PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA ))
2811 }, 2811 },
2812 2812
2813 { } 2813 { }
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index ef3da8bf1d87..e1276d143117 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -3971,7 +3971,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3971 PORTCR(308, 0xe6052134), /* PORT308CR */ 3971 PORTCR(308, 0xe6052134), /* PORT308CR */
3972 PORTCR(309, 0xe6052135), /* PORT309CR */ 3972 PORTCR(309, 0xe6052135), /* PORT309CR */
3973 3973
3974 { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) { 3974 { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1, GROUP(
3975 0, 0, 3975 0, 0,
3976 0, 0, 3976 0, 0,
3977 0, 0, 3977 0, 0,
@@ -4004,9 +4004,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4004 MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1, 4004 MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
4005 MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1, 4005 MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
4006 MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1, 4006 MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
4007 } 4007 ))
4008 }, 4008 },
4009 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) { 4009 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1, GROUP(
4010 0, 0, 4010 0, 0,
4011 0, 0, 4011 0, 0,
4012 0, 0, 4012 0, 0,
@@ -4039,9 +4039,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4039 MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1, 4039 MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
4040 0, 0, 4040 0, 0,
4041 0, 0, 4041 0, 0,
4042 } 4042 ))
4043 }, 4043 },
4044 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) { 4044 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1, GROUP(
4045 0, 0, 4045 0, 0,
4046 0, 0, 4046 0, 0,
4047 MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1, 4047 MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
@@ -4074,13 +4074,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4074 0, 0, 4074 0, 0,
4075 MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1, 4075 MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
4076 0, 0, 4076 0, 0,
4077 } 4077 ))
4078 }, 4078 },
4079 { }, 4079 { },
4080}; 4080};
4081 4081
4082static const struct pinmux_data_reg pinmux_data_regs[] = { 4082static const struct pinmux_data_reg pinmux_data_regs[] = {
4083 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) { 4083 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32, GROUP(
4084 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, 4084 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
4085 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, 4085 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
4086 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, 4086 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
@@ -4088,9 +4088,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
4088 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, 4088 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
4089 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, 4089 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
4090 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, 4090 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
4091 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA } 4091 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA ))
4092 }, 4092 },
4093 { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) { 4093 { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32, GROUP(
4094 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA, 4094 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
4095 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA, 4095 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
4096 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA, 4096 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
@@ -4098,9 +4098,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
4098 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA, 4098 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
4099 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA, 4099 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
4100 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, 4100 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
4101 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA } 4101 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA ))
4102 }, 4102 },
4103 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) { 4103 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32, GROUP(
4104 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, 4104 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
4105 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, 4105 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
4106 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA, 4106 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
@@ -4108,9 +4108,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
4108 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, 4108 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
4109 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, 4109 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
4110 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, 4110 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
4111 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA } 4111 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA ))
4112 }, 4112 },
4113 { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) { 4113 { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32, GROUP(
4114 0, 0, 0, 0, 4114 0, 0, 0, 0,
4115 0, 0, 0, 0, 4115 0, 0, 0, 0,
4116 0, PORT118_DATA, PORT117_DATA, PORT116_DATA, 4116 0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
@@ -4118,9 +4118,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
4118 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, 4118 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
4119 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, 4119 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
4120 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, 4120 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
4121 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA } 4121 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA ))
4122 }, 4122 },
4123 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) { 4123 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32, GROUP(
4124 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA, 4124 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
4125 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA, 4125 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
4126 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA, 4126 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
@@ -4128,9 +4128,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
4128 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA, 4128 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
4129 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA, 4129 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
4130 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA, 4130 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
4131 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA } 4131 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA ))
4132 }, 4132 },
4133 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) { 4133 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32, GROUP(
4134 0, 0, 0, 0, 4134 0, 0, 0, 0,
4135 0, 0, 0, 0, 4135 0, 0, 0, 0,
4136 0, 0, 0, 0, 4136 0, 0, 0, 0,
@@ -4138,9 +4138,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
4138 0, 0, 0, 0, 4138 0, 0, 0, 0,
4139 0, 0, 0, 0, 4139 0, 0, 0, 0,
4140 0, 0, 0, PORT164_DATA, 4140 0, 0, 0, PORT164_DATA,
4141 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA } 4141 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA ))
4142 }, 4142 },
4143 { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) { 4143 { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32, GROUP(
4144 PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA, 4144 PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
4145 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA, 4145 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
4146 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA, 4146 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
@@ -4148,9 +4148,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
4148 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA, 4148 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
4149 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, 4149 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
4150 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, 4150 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
4151 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA } 4151 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA ))
4152 }, 4152 },
4153 { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) { 4153 { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32, GROUP(
4154 PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA, 4154 PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
4155 PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA, 4155 PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
4156 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA, 4156 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
@@ -4158,9 +4158,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
4158 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA, 4158 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
4159 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA, 4159 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
4160 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA, 4160 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
4161 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA } 4161 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA ))
4162 }, 4162 },
4163 { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) { 4163 { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32, GROUP(
4164 0, 0, 0, 0, 4164 0, 0, 0, 0,
4165 0, PORT282_DATA, PORT281_DATA, PORT280_DATA, 4165 0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
4166 PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA, 4166 PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
@@ -4168,9 +4168,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
4168 PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA, 4168 PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
4169 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA, 4169 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
4170 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA, 4170 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
4171 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA } 4171 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA ))
4172 }, 4172 },
4173 { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) { 4173 { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32, GROUP(
4174 0, 0, 0, 0, 4174 0, 0, 0, 0,
4175 0, 0, 0, 0, 4175 0, 0, 0, 0,
4176 0, 0, PORT309_DATA, PORT308_DATA, 4176 0, 0, PORT309_DATA, PORT308_DATA,
@@ -4178,7 +4178,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
4178 PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA, 4178 PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
4179 PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA, 4179 PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
4180 PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA, 4180 PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
4181 PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA } 4181 PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA ))
4182 }, 4182 },
4183 { }, 4183 { },
4184}; 4184};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
index 65694bfaa08d..37bcae6b3208 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
@@ -925,7 +925,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
925}; 925};
926 926
927static const struct pinmux_cfg_reg pinmux_config_regs[] = { 927static const struct pinmux_cfg_reg pinmux_config_regs[] = {
928 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { 928 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2, GROUP(
929 PTA7_FN, PTA7_OUT, 0, PTA7_IN, 929 PTA7_FN, PTA7_OUT, 0, PTA7_IN,
930 PTA6_FN, PTA6_OUT, 0, PTA6_IN, 930 PTA6_FN, PTA6_OUT, 0, PTA6_IN,
931 PTA5_FN, PTA5_OUT, 0, PTA5_IN, 931 PTA5_FN, PTA5_OUT, 0, PTA5_IN,
@@ -933,9 +933,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
933 PTA3_FN, PTA3_OUT, 0, PTA3_IN, 933 PTA3_FN, PTA3_OUT, 0, PTA3_IN,
934 PTA2_FN, PTA2_OUT, 0, PTA2_IN, 934 PTA2_FN, PTA2_OUT, 0, PTA2_IN,
935 PTA1_FN, PTA1_OUT, 0, PTA1_IN, 935 PTA1_FN, PTA1_OUT, 0, PTA1_IN,
936 PTA0_FN, PTA0_OUT, 0, PTA0_IN } 936 PTA0_FN, PTA0_OUT, 0, PTA0_IN ))
937 }, 937 },
938 { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) { 938 { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2, GROUP(
939 PTB7_FN, PTB7_OUT, 0, PTB7_IN, 939 PTB7_FN, PTB7_OUT, 0, PTB7_IN,
940 PTB6_FN, PTB6_OUT, 0, PTB6_IN, 940 PTB6_FN, PTB6_OUT, 0, PTB6_IN,
941 PTB5_FN, PTB5_OUT, 0, PTB5_IN, 941 PTB5_FN, PTB5_OUT, 0, PTB5_IN,
@@ -943,9 +943,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
943 PTB3_FN, PTB3_OUT, 0, PTB3_IN, 943 PTB3_FN, PTB3_OUT, 0, PTB3_IN,
944 PTB2_FN, PTB2_OUT, 0, PTB2_IN, 944 PTB2_FN, PTB2_OUT, 0, PTB2_IN,
945 PTB1_FN, PTB1_OUT, 0, PTB1_IN, 945 PTB1_FN, PTB1_OUT, 0, PTB1_IN,
946 PTB0_FN, PTB0_OUT, 0, PTB0_IN } 946 PTB0_FN, PTB0_OUT, 0, PTB0_IN ))
947 }, 947 },
948 { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) { 948 { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2, GROUP(
949 PTC7_FN, PTC7_OUT, 0, PTC7_IN, 949 PTC7_FN, PTC7_OUT, 0, PTC7_IN,
950 PTC6_FN, PTC6_OUT, 0, PTC6_IN, 950 PTC6_FN, PTC6_OUT, 0, PTC6_IN,
951 PTC5_FN, PTC5_OUT, 0, PTC5_IN, 951 PTC5_FN, PTC5_OUT, 0, PTC5_IN,
@@ -953,9 +953,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
953 PTC3_FN, PTC3_OUT, 0, PTC3_IN, 953 PTC3_FN, PTC3_OUT, 0, PTC3_IN,
954 PTC2_FN, PTC2_OUT, 0, PTC2_IN, 954 PTC2_FN, PTC2_OUT, 0, PTC2_IN,
955 PTC1_FN, PTC1_OUT, 0, PTC1_IN, 955 PTC1_FN, PTC1_OUT, 0, PTC1_IN,
956 PTC0_FN, PTC0_OUT, 0, PTC0_IN } 956 PTC0_FN, PTC0_OUT, 0, PTC0_IN ))
957 }, 957 },
958 { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) { 958 { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2, GROUP(
959 PTD7_FN, PTD7_OUT, 0, PTD7_IN, 959 PTD7_FN, PTD7_OUT, 0, PTD7_IN,
960 PTD6_FN, PTD6_OUT, 0, PTD6_IN, 960 PTD6_FN, PTD6_OUT, 0, PTD6_IN,
961 PTD5_FN, PTD5_OUT, 0, PTD5_IN, 961 PTD5_FN, PTD5_OUT, 0, PTD5_IN,
@@ -963,9 +963,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
963 PTD3_FN, PTD3_OUT, 0, PTD3_IN, 963 PTD3_FN, PTD3_OUT, 0, PTD3_IN,
964 PTD2_FN, PTD2_OUT, 0, PTD2_IN, 964 PTD2_FN, PTD2_OUT, 0, PTD2_IN,
965 PTD1_FN, PTD1_OUT, 0, PTD1_IN, 965 PTD1_FN, PTD1_OUT, 0, PTD1_IN,
966 PTD0_FN, PTD0_OUT, 0, PTD0_IN } 966 PTD0_FN, PTD0_OUT, 0, PTD0_IN ))
967 }, 967 },
968 { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) { 968 { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2, GROUP(
969 0, 0, 0, 0, 969 0, 0, 0, 0,
970 PTE6_FN, 0, 0, PTE6_IN, 970 PTE6_FN, 0, 0, PTE6_IN,
971 PTE5_FN, 0, 0, PTE5_IN, 971 PTE5_FN, 0, 0, PTE5_IN,
@@ -973,9 +973,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
973 PTE3_FN, PTE3_OUT, 0, PTE3_IN, 973 PTE3_FN, PTE3_OUT, 0, PTE3_IN,
974 PTE2_FN, PTE2_OUT, 0, PTE2_IN, 974 PTE2_FN, PTE2_OUT, 0, PTE2_IN,
975 PTE1_FN, PTE1_OUT, 0, PTE1_IN, 975 PTE1_FN, PTE1_OUT, 0, PTE1_IN,
976 PTE0_FN, PTE0_OUT, 0, PTE0_IN } 976 PTE0_FN, PTE0_OUT, 0, PTE0_IN ))
977 }, 977 },
978 { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) { 978 { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2, GROUP(
979 0, 0, 0, 0, 979 0, 0, 0, 0,
980 PTF6_FN, 0, 0, PTF6_IN, 980 PTF6_FN, 0, 0, PTF6_IN,
981 PTF5_FN, 0, 0, PTF5_IN, 981 PTF5_FN, 0, 0, PTF5_IN,
@@ -983,9 +983,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
983 PTF3_FN, 0, 0, PTF3_IN, 983 PTF3_FN, 0, 0, PTF3_IN,
984 PTF2_FN, 0, 0, PTF2_IN, 984 PTF2_FN, 0, 0, PTF2_IN,
985 PTF1_FN, 0, 0, PTF1_IN, 985 PTF1_FN, 0, 0, PTF1_IN,
986 PTF0_FN, 0, 0, PTF0_IN } 986 PTF0_FN, 0, 0, PTF0_IN ))
987 }, 987 },
988 { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) { 988 { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2, GROUP(
989 0, 0, 0, 0, 989 0, 0, 0, 0,
990 PTG6_FN, PTG6_OUT, 0, PTG6_IN, 990 PTG6_FN, PTG6_OUT, 0, PTG6_IN,
991 PTG5_FN, PTG5_OUT, 0, PTG5_IN, 991 PTG5_FN, PTG5_OUT, 0, PTG5_IN,
@@ -993,9 +993,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
993 PTG3_FN, PTG3_OUT, 0, PTG3_IN, 993 PTG3_FN, PTG3_OUT, 0, PTG3_IN,
994 PTG2_FN, PTG2_OUT, 0, PTG2_IN, 994 PTG2_FN, PTG2_OUT, 0, PTG2_IN,
995 PTG1_FN, PTG1_OUT, 0, PTG1_IN, 995 PTG1_FN, PTG1_OUT, 0, PTG1_IN,
996 PTG0_FN, PTG0_OUT, 0, PTG0_IN } 996 PTG0_FN, PTG0_OUT, 0, PTG0_IN ))
997 }, 997 },
998 { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) { 998 { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2, GROUP(
999 0, 0, 0, 0, 999 0, 0, 0, 0,
1000 PTH6_FN, PTH6_OUT, 0, PTH6_IN, 1000 PTH6_FN, PTH6_OUT, 0, PTH6_IN,
1001 PTH5_FN, PTH5_OUT, 0, PTH5_IN, 1001 PTH5_FN, PTH5_OUT, 0, PTH5_IN,
@@ -1003,9 +1003,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1003 PTH3_FN, PTH3_OUT, 0, PTH3_IN, 1003 PTH3_FN, PTH3_OUT, 0, PTH3_IN,
1004 PTH2_FN, PTH2_OUT, 0, PTH2_IN, 1004 PTH2_FN, PTH2_OUT, 0, PTH2_IN,
1005 PTH1_FN, PTH1_OUT, 0, PTH1_IN, 1005 PTH1_FN, PTH1_OUT, 0, PTH1_IN,
1006 PTH0_FN, PTH0_OUT, 0, PTH0_IN } 1006 PTH0_FN, PTH0_OUT, 0, PTH0_IN ))
1007 }, 1007 },
1008 { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) { 1008 { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2, GROUP(
1009 0, 0, 0, 0, 1009 0, 0, 0, 0,
1010 PTJ6_FN, PTJ6_OUT, 0, PTJ6_IN, 1010 PTJ6_FN, PTJ6_OUT, 0, PTJ6_IN,
1011 PTJ5_FN, PTJ5_OUT, 0, PTJ5_IN, 1011 PTJ5_FN, PTJ5_OUT, 0, PTJ5_IN,
@@ -1013,9 +1013,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1013 PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN, 1013 PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN,
1014 PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN, 1014 PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN,
1015 PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN, 1015 PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN,
1016 PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN } 1016 PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN ))
1017 }, 1017 },
1018 { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) { 1018 { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2, GROUP(
1019 0, 0, 0, 0, 1019 0, 0, 0, 0,
1020 0, 0, 0, 0, 1020 0, 0, 0, 0,
1021 0, 0, 0, 0, 1021 0, 0, 0, 0,
@@ -1023,9 +1023,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1023 PTK3_FN, PTK3_OUT, 0, PTK3_IN, 1023 PTK3_FN, PTK3_OUT, 0, PTK3_IN,
1024 PTK2_FN, PTK2_OUT, 0, PTK2_IN, 1024 PTK2_FN, PTK2_OUT, 0, PTK2_IN,
1025 PTK1_FN, PTK1_OUT, 0, PTK1_IN, 1025 PTK1_FN, PTK1_OUT, 0, PTK1_IN,
1026 PTK0_FN, PTK0_OUT, 0, PTK0_IN } 1026 PTK0_FN, PTK0_OUT, 0, PTK0_IN ))
1027 }, 1027 },
1028 { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) { 1028 { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2, GROUP(
1029 PTL7_FN, PTL7_OUT, 0, PTL7_IN, 1029 PTL7_FN, PTL7_OUT, 0, PTL7_IN,
1030 PTL6_FN, PTL6_OUT, 0, PTL6_IN, 1030 PTL6_FN, PTL6_OUT, 0, PTL6_IN,
1031 PTL5_FN, PTL5_OUT, 0, PTL5_IN, 1031 PTL5_FN, PTL5_OUT, 0, PTL5_IN,
@@ -1033,9 +1033,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1033 PTL3_FN, PTL3_OUT, 0, PTL3_IN, 1033 PTL3_FN, PTL3_OUT, 0, PTL3_IN,
1034 0, 0, 0, 0, 1034 0, 0, 0, 0,
1035 0, 0, 0, 0, 1035 0, 0, 0, 0,
1036 0, 0, 0, 0 } 1036 0, 0, 0, 0 ))
1037 }, 1037 },
1038 { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) { 1038 { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2, GROUP(
1039 PTM7_FN, PTM7_OUT, 0, PTM7_IN, 1039 PTM7_FN, PTM7_OUT, 0, PTM7_IN,
1040 PTM6_FN, PTM6_OUT, 0, PTM6_IN, 1040 PTM6_FN, PTM6_OUT, 0, PTM6_IN,
1041 PTM5_FN, PTM5_OUT, 0, PTM5_IN, 1041 PTM5_FN, PTM5_OUT, 0, PTM5_IN,
@@ -1043,9 +1043,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1043 PTM3_FN, PTM3_OUT, 0, PTM3_IN, 1043 PTM3_FN, PTM3_OUT, 0, PTM3_IN,
1044 PTM2_FN, PTM2_OUT, 0, PTM2_IN, 1044 PTM2_FN, PTM2_OUT, 0, PTM2_IN,
1045 PTM1_FN, PTM1_OUT, 0, PTM1_IN, 1045 PTM1_FN, PTM1_OUT, 0, PTM1_IN,
1046 PTM0_FN, PTM0_OUT, 0, PTM0_IN } 1046 PTM0_FN, PTM0_OUT, 0, PTM0_IN ))
1047 }, 1047 },
1048 { PINMUX_CFG_REG("PPCR", 0xa4050118, 16, 2) { 1048 { PINMUX_CFG_REG("PPCR", 0xa4050118, 16, 2, GROUP(
1049 0, 0, 0, 0, 1049 0, 0, 0, 0,
1050 0, 0, 0, 0, 1050 0, 0, 0, 0,
1051 0, 0, 0, 0, 1051 0, 0, 0, 0,
@@ -1053,9 +1053,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1053 PTP3_FN, PTP3_OUT, 0, PTP3_IN, 1053 PTP3_FN, PTP3_OUT, 0, PTP3_IN,
1054 PTP2_FN, PTP2_OUT, 0, PTP2_IN, 1054 PTP2_FN, PTP2_OUT, 0, PTP2_IN,
1055 PTP1_FN, PTP1_OUT, 0, PTP1_IN, 1055 PTP1_FN, PTP1_OUT, 0, PTP1_IN,
1056 PTP0_FN, PTP0_OUT, 0, PTP0_IN } 1056 PTP0_FN, PTP0_OUT, 0, PTP0_IN ))
1057 }, 1057 },
1058 { PINMUX_CFG_REG("PRCR", 0xa405011a, 16, 2) { 1058 { PINMUX_CFG_REG("PRCR", 0xa405011a, 16, 2, GROUP(
1059 PTR7_FN, PTR7_OUT, 0, PTR7_IN, 1059 PTR7_FN, PTR7_OUT, 0, PTR7_IN,
1060 PTR6_FN, PTR6_OUT, 0, PTR6_IN, 1060 PTR6_FN, PTR6_OUT, 0, PTR6_IN,
1061 PTR5_FN, PTR5_OUT, 0, PTR5_IN, 1061 PTR5_FN, PTR5_OUT, 0, PTR5_IN,
@@ -1063,9 +1063,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1063 PTR3_FN, PTR3_OUT, 0, PTR3_IN, 1063 PTR3_FN, PTR3_OUT, 0, PTR3_IN,
1064 PTR2_FN, PTR2_OUT, 0, PTR2_IN, 1064 PTR2_FN, PTR2_OUT, 0, PTR2_IN,
1065 PTR1_FN, PTR1_OUT, 0, PTR1_IN, 1065 PTR1_FN, PTR1_OUT, 0, PTR1_IN,
1066 PTR0_FN, PTR0_OUT, 0, PTR0_IN } 1066 PTR0_FN, PTR0_OUT, 0, PTR0_IN ))
1067 }, 1067 },
1068 { PINMUX_CFG_REG("PSCR", 0xa405011c, 16, 2) { 1068 { PINMUX_CFG_REG("PSCR", 0xa405011c, 16, 2, GROUP(
1069 0, 0, 0, 0, 1069 0, 0, 0, 0,
1070 0, 0, 0, 0, 1070 0, 0, 0, 0,
1071 0, 0, 0, 0, 1071 0, 0, 0, 0,
@@ -1073,9 +1073,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1073 PTS3_FN, PTS3_OUT, 0, PTS3_IN, 1073 PTS3_FN, PTS3_OUT, 0, PTS3_IN,
1074 PTS2_FN, PTS2_OUT, 0, PTS2_IN, 1074 PTS2_FN, PTS2_OUT, 0, PTS2_IN,
1075 PTS1_FN, PTS1_OUT, 0, PTS1_IN, 1075 PTS1_FN, PTS1_OUT, 0, PTS1_IN,
1076 PTS0_FN, PTS0_OUT, 0, PTS0_IN } 1076 PTS0_FN, PTS0_OUT, 0, PTS0_IN ))
1077 }, 1077 },
1078 { PINMUX_CFG_REG("PTCR", 0xa405011e, 16, 2) { 1078 { PINMUX_CFG_REG("PTCR", 0xa405011e, 16, 2, GROUP(
1079 0, 0, 0, 0, 1079 0, 0, 0, 0,
1080 0, 0, 0, 0, 1080 0, 0, 0, 0,
1081 0, 0, 0, 0, 1081 0, 0, 0, 0,
@@ -1083,9 +1083,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1083 PTT3_FN, PTT3_OUT, 0, PTT3_IN, 1083 PTT3_FN, PTT3_OUT, 0, PTT3_IN,
1084 PTT2_FN, PTT2_OUT, 0, PTT2_IN, 1084 PTT2_FN, PTT2_OUT, 0, PTT2_IN,
1085 PTT1_FN, PTT1_OUT, 0, PTT1_IN, 1085 PTT1_FN, PTT1_OUT, 0, PTT1_IN,
1086 PTT0_FN, PTT0_OUT, 0, PTT0_IN } 1086 PTT0_FN, PTT0_OUT, 0, PTT0_IN ))
1087 }, 1087 },
1088 { PINMUX_CFG_REG("PUCR", 0xa4050120, 16, 2) { 1088 { PINMUX_CFG_REG("PUCR", 0xa4050120, 16, 2, GROUP(
1089 0, 0, 0, 0, 1089 0, 0, 0, 0,
1090 0, 0, 0, 0, 1090 0, 0, 0, 0,
1091 0, 0, 0, 0, 1091 0, 0, 0, 0,
@@ -1093,9 +1093,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1093 PTU3_FN, PTU3_OUT, 0, PTU3_IN, 1093 PTU3_FN, PTU3_OUT, 0, PTU3_IN,
1094 PTU2_FN, PTU2_OUT, 0, PTU2_IN, 1094 PTU2_FN, PTU2_OUT, 0, PTU2_IN,
1095 PTU1_FN, PTU1_OUT, 0, PTU1_IN, 1095 PTU1_FN, PTU1_OUT, 0, PTU1_IN,
1096 PTU0_FN, PTU0_OUT, 0, PTU0_IN } 1096 PTU0_FN, PTU0_OUT, 0, PTU0_IN ))
1097 }, 1097 },
1098 { PINMUX_CFG_REG("PVCR", 0xa4050122, 16, 2) { 1098 { PINMUX_CFG_REG("PVCR", 0xa4050122, 16, 2, GROUP(
1099 0, 0, 0, 0, 1099 0, 0, 0, 0,
1100 0, 0, 0, 0, 1100 0, 0, 0, 0,
1101 0, 0, 0, 0, 1101 0, 0, 0, 0,
@@ -1103,83 +1103,83 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1103 PTV3_FN, PTV3_OUT, 0, PTV3_IN, 1103 PTV3_FN, PTV3_OUT, 0, PTV3_IN,
1104 PTV2_FN, PTV2_OUT, 0, PTV2_IN, 1104 PTV2_FN, PTV2_OUT, 0, PTV2_IN,
1105 PTV1_FN, PTV1_OUT, 0, PTV1_IN, 1105 PTV1_FN, PTV1_OUT, 0, PTV1_IN,
1106 PTV0_FN, PTV0_OUT, 0, PTV0_IN } 1106 PTV0_FN, PTV0_OUT, 0, PTV0_IN ))
1107 }, 1107 },
1108 {} 1108 {}
1109}; 1109};
1110 1110
1111static const struct pinmux_data_reg pinmux_data_regs[] = { 1111static const struct pinmux_data_reg pinmux_data_regs[] = {
1112 { PINMUX_DATA_REG("PADR", 0xa4050140, 8) { 1112 { PINMUX_DATA_REG("PADR", 0xa4050140, 8, GROUP(
1113 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, 1113 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
1114 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } 1114 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA ))
1115 }, 1115 },
1116 { PINMUX_DATA_REG("PBDR", 0xa4050142, 8) { 1116 { PINMUX_DATA_REG("PBDR", 0xa4050142, 8, GROUP(
1117 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, 1117 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
1118 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA } 1118 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA ))
1119 }, 1119 },
1120 { PINMUX_DATA_REG("PCDR", 0xa4050144, 8) { 1120 { PINMUX_DATA_REG("PCDR", 0xa4050144, 8, GROUP(
1121 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA, 1121 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
1122 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA } 1122 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA ))
1123 }, 1123 },
1124 { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) { 1124 { PINMUX_DATA_REG("PDDR", 0xa4050126, 8, GROUP(
1125 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, 1125 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
1126 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA } 1126 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA ))
1127 }, 1127 },
1128 { PINMUX_DATA_REG("PEDR", 0xa4050148, 8) { 1128 { PINMUX_DATA_REG("PEDR", 0xa4050148, 8, GROUP(
1129 0, PTE6_DATA, PTE5_DATA, PTE4_DATA, 1129 0, PTE6_DATA, PTE5_DATA, PTE4_DATA,
1130 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA } 1130 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA ))
1131 }, 1131 },
1132 { PINMUX_DATA_REG("PFDR", 0xa405014a, 8) { 1132 { PINMUX_DATA_REG("PFDR", 0xa405014a, 8, GROUP(
1133 0, PTF6_DATA, PTF5_DATA, PTF4_DATA, 1133 0, PTF6_DATA, PTF5_DATA, PTF4_DATA,
1134 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA } 1134 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA ))
1135 }, 1135 },
1136 { PINMUX_DATA_REG("PGDR", 0xa405014c, 8) { 1136 { PINMUX_DATA_REG("PGDR", 0xa405014c, 8, GROUP(
1137 0, PTG6_DATA, PTG5_DATA, PTG4_DATA, 1137 0, PTG6_DATA, PTG5_DATA, PTG4_DATA,
1138 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA } 1138 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA ))
1139 }, 1139 },
1140 { PINMUX_DATA_REG("PHDR", 0xa405014e, 8) { 1140 { PINMUX_DATA_REG("PHDR", 0xa405014e, 8, GROUP(
1141 0, PTH6_DATA, PTH5_DATA, PTH4_DATA, 1141 0, PTH6_DATA, PTH5_DATA, PTH4_DATA,
1142 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA } 1142 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA ))
1143 }, 1143 },
1144 { PINMUX_DATA_REG("PJDR", 0xa4050150, 8) { 1144 { PINMUX_DATA_REG("PJDR", 0xa4050150, 8, GROUP(
1145 0, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA, 1145 0, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
1146 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA } 1146 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA ))
1147 }, 1147 },
1148 { PINMUX_DATA_REG("PKDR", 0xa4050152, 8) { 1148 { PINMUX_DATA_REG("PKDR", 0xa4050152, 8, GROUP(
1149 0, 0, 0, 0, 1149 0, 0, 0, 0,
1150 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA } 1150 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA ))
1151 }, 1151 },
1152 { PINMUX_DATA_REG("PLDR", 0xa4050154, 8) { 1152 { PINMUX_DATA_REG("PLDR", 0xa4050154, 8, GROUP(
1153 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, 1153 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
1154 PTL3_DATA, 0, 0, 0 } 1154 PTL3_DATA, 0, 0, 0 ))
1155 }, 1155 },
1156 { PINMUX_DATA_REG("PMDR", 0xa4050156, 8) { 1156 { PINMUX_DATA_REG("PMDR", 0xa4050156, 8, GROUP(
1157 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, 1157 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
1158 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA } 1158 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA ))
1159 }, 1159 },
1160 { PINMUX_DATA_REG("PPDR", 0xa4050158, 8) { 1160 { PINMUX_DATA_REG("PPDR", 0xa4050158, 8, GROUP(
1161 0, 0, 0, PTP4_DATA, 1161 0, 0, 0, PTP4_DATA,
1162 PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA } 1162 PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA ))
1163 }, 1163 },
1164 { PINMUX_DATA_REG("PRDR", 0xa405015a, 8) { 1164 { PINMUX_DATA_REG("PRDR", 0xa405015a, 8, GROUP(
1165 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA, 1165 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
1166 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA } 1166 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA ))
1167 }, 1167 },
1168 { PINMUX_DATA_REG("PSDR", 0xa405015c, 8) { 1168 { PINMUX_DATA_REG("PSDR", 0xa405015c, 8, GROUP(
1169 0, 0, 0, PTS4_DATA, 1169 0, 0, 0, PTS4_DATA,
1170 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA } 1170 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA ))
1171 }, 1171 },
1172 { PINMUX_DATA_REG("PTDR", 0xa405015e, 8) { 1172 { PINMUX_DATA_REG("PTDR", 0xa405015e, 8, GROUP(
1173 0, 0, 0, PTT4_DATA, 1173 0, 0, 0, PTT4_DATA,
1174 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA } 1174 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA ))
1175 }, 1175 },
1176 { PINMUX_DATA_REG("PUDR", 0xa4050160, 8) { 1176 { PINMUX_DATA_REG("PUDR", 0xa4050160, 8, GROUP(
1177 0, 0, 0, PTU4_DATA, 1177 0, 0, 0, PTU4_DATA,
1178 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA } 1178 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA ))
1179 }, 1179 },
1180 { PINMUX_DATA_REG("PVDR", 0xa4050162, 8) { 1180 { PINMUX_DATA_REG("PVDR", 0xa4050162, 8, GROUP(
1181 0, 0, 0, PTV4_DATA, 1181 0, 0, 0, PTV4_DATA,
1182 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA } 1182 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
1183 }, 1183 },
1184 { }, 1184 { },
1185}; 1185};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
index 0e733bffdb38..95295be4e703 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
@@ -1237,7 +1237,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
1237}; 1237};
1238 1238
1239static const struct pinmux_cfg_reg pinmux_config_regs[] = { 1239static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1240 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { 1240 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2, GROUP(
1241 VIO_D7_SCIF1_SCK, PTA7_OUT, 0, PTA7_IN, 1241 VIO_D7_SCIF1_SCK, PTA7_OUT, 0, PTA7_IN,
1242 VIO_D6_SCIF1_RXD, 0, 0, PTA6_IN, 1242 VIO_D6_SCIF1_RXD, 0, 0, PTA6_IN,
1243 VIO_D5_SCIF1_TXD, PTA5_OUT, 0, PTA5_IN, 1243 VIO_D5_SCIF1_TXD, PTA5_OUT, 0, PTA5_IN,
@@ -1245,9 +1245,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1245 VIO_D3, 0, 0, PTA3_IN, 1245 VIO_D3, 0, 0, PTA3_IN,
1246 VIO_D2, 0, 0, PTA2_IN, 1246 VIO_D2, 0, 0, PTA2_IN,
1247 VIO_D1, 0, 0, PTA1_IN, 1247 VIO_D1, 0, 0, PTA1_IN,
1248 VIO_D0_LCDLCLK, 0, 0, PTA0_IN } 1248 VIO_D0_LCDLCLK, 0, 0, PTA0_IN ))
1249 }, 1249 },
1250 { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) { 1250 { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2, GROUP(
1251 HPD55, PTB7_OUT, 0, PTB7_IN, 1251 HPD55, PTB7_OUT, 0, PTB7_IN,
1252 HPD54, PTB6_OUT, 0, PTB6_IN, 1252 HPD54, PTB6_OUT, 0, PTB6_IN,
1253 HPD53, PTB5_OUT, 0, PTB5_IN, 1253 HPD53, PTB5_OUT, 0, PTB5_IN,
@@ -1255,9 +1255,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1255 HPD51, PTB3_OUT, 0, PTB3_IN, 1255 HPD51, PTB3_OUT, 0, PTB3_IN,
1256 HPD50, PTB2_OUT, 0, PTB2_IN, 1256 HPD50, PTB2_OUT, 0, PTB2_IN,
1257 HPD49, PTB1_OUT, 0, PTB1_IN, 1257 HPD49, PTB1_OUT, 0, PTB1_IN,
1258 HPD48, PTB0_OUT, 0, PTB0_IN } 1258 HPD48, PTB0_OUT, 0, PTB0_IN ))
1259 }, 1259 },
1260 { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) { 1260 { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2, GROUP(
1261 0, 0, 0, PTC7_IN, 1261 0, 0, 0, PTC7_IN,
1262 0, 0, 0, 0, 1262 0, 0, 0, 0,
1263 IOIS16, 0, 0, PTC5_IN, 1263 IOIS16, 0, 0, PTC5_IN,
@@ -1265,9 +1265,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1265 HPDQM6, PTC3_OUT, 0, PTC3_IN, 1265 HPDQM6, PTC3_OUT, 0, PTC3_IN,
1266 HPDQM5, PTC2_OUT, 0, PTC2_IN, 1266 HPDQM5, PTC2_OUT, 0, PTC2_IN,
1267 0, 0, 0, 0, 1267 0, 0, 0, 0,
1268 HPDQM4, PTC0_OUT, 0, PTC0_IN } 1268 HPDQM4, PTC0_OUT, 0, PTC0_IN ))
1269 }, 1269 },
1270 { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) { 1270 { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2, GROUP(
1271 SDHICD, 0, 0, PTD7_IN, 1271 SDHICD, 0, 0, PTD7_IN,
1272 SDHIWP, PTD6_OUT, 0, PTD6_IN, 1272 SDHIWP, PTD6_OUT, 0, PTD6_IN,
1273 SDHID3, PTD5_OUT, 0, PTD5_IN, 1273 SDHID3, PTD5_OUT, 0, PTD5_IN,
@@ -1275,9 +1275,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1275 SDHID1, PTD3_OUT, 0, PTD3_IN, 1275 SDHID1, PTD3_OUT, 0, PTD3_IN,
1276 SDHID0, PTD2_OUT, 0, PTD2_IN, 1276 SDHID0, PTD2_OUT, 0, PTD2_IN,
1277 SDHICMD, PTD1_OUT, 0, PTD1_IN, 1277 SDHICMD, PTD1_OUT, 0, PTD1_IN,
1278 SDHICLK, PTD0_OUT, 0, 0 } 1278 SDHICLK, PTD0_OUT, 0, 0 ))
1279 }, 1279 },
1280 { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) { 1280 { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2, GROUP(
1281 A25, PTE7_OUT, 0, PTE7_IN, 1281 A25, PTE7_OUT, 0, PTE7_IN,
1282 A24, PTE6_OUT, 0, PTE6_IN, 1282 A24, PTE6_OUT, 0, PTE6_IN,
1283 A23, PTE5_OUT, 0, PTE5_IN, 1283 A23, PTE5_OUT, 0, PTE5_IN,
@@ -1285,9 +1285,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1285 0, 0, 0, 0, 1285 0, 0, 0, 0,
1286 0, 0, 0, 0, 1286 0, 0, 0, 0,
1287 IRQ5, PTE1_OUT, 0, PTE1_IN, 1287 IRQ5, PTE1_OUT, 0, PTE1_IN,
1288 IRQ4_BS, PTE0_OUT, 0, PTE0_IN } 1288 IRQ4_BS, PTE0_OUT, 0, PTE0_IN ))
1289 }, 1289 },
1290 { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) { 1290 { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2, GROUP(
1291 0, 0, 0, 0, 1291 0, 0, 0, 0,
1292 PTF6, PTF6_OUT, 0, PTF6_IN, 1292 PTF6, PTF6_OUT, 0, PTF6_IN,
1293 SIOSCK_SIUBOBT, PTF5_OUT, 0, PTF5_IN, 1293 SIOSCK_SIUBOBT, PTF5_OUT, 0, PTF5_IN,
@@ -1295,9 +1295,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1295 SIOSTRB0_SIUBIBT, PTF3_OUT, 0, PTF3_IN, 1295 SIOSTRB0_SIUBIBT, PTF3_OUT, 0, PTF3_IN,
1296 SIOD_SIUBILR, PTF2_OUT, 0, PTF2_IN, 1296 SIOD_SIUBILR, PTF2_OUT, 0, PTF2_IN,
1297 SIORXD_SIUBISLD, 0, 0, PTF1_IN, 1297 SIORXD_SIUBISLD, 0, 0, PTF1_IN,
1298 SIOTXD_SIUBOSLD, PTF0_OUT, 0, 0 } 1298 SIOTXD_SIUBOSLD, PTF0_OUT, 0, 0 ))
1299 }, 1299 },
1300 { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) { 1300 { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2, GROUP(
1301 0, 0, 0, 0, 1301 0, 0, 0, 0,
1302 0, 0, 0, 0, 1302 0, 0, 0, 0,
1303 0, 0, 0, 0, 1303 0, 0, 0, 0,
@@ -1305,9 +1305,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1305 AUDATA3, PTG3_OUT, 0, 0, 1305 AUDATA3, PTG3_OUT, 0, 0,
1306 AUDATA2, PTG2_OUT, 0, 0, 1306 AUDATA2, PTG2_OUT, 0, 0,
1307 AUDATA1, PTG1_OUT, 0, 0, 1307 AUDATA1, PTG1_OUT, 0, 0,
1308 AUDATA0, PTG0_OUT, 0, 0 } 1308 AUDATA0, PTG0_OUT, 0, 0 ))
1309 }, 1309 },
1310 { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) { 1310 { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2, GROUP(
1311 LCDVCPWC_LCDVCPWC2, PTH7_OUT, 0, 0, 1311 LCDVCPWC_LCDVCPWC2, PTH7_OUT, 0, 0,
1312 LCDVSYN2_DACK, PTH6_OUT, 0, PTH6_IN, 1312 LCDVSYN2_DACK, PTH6_OUT, 0, PTH6_IN,
1313 LCDVSYN, PTH5_OUT, 0, PTH5_IN, 1313 LCDVSYN, PTH5_OUT, 0, PTH5_IN,
@@ -1315,9 +1315,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1315 LCDHSYN_LCDCS, PTH3_OUT, 0, 0, 1315 LCDHSYN_LCDCS, PTH3_OUT, 0, 0,
1316 LCDDON_LCDDON2, PTH2_OUT, 0, 0, 1316 LCDDON_LCDDON2, PTH2_OUT, 0, 0,
1317 LCDD17_DV_HSYNC, PTH1_OUT, 0, PTH1_IN, 1317 LCDD17_DV_HSYNC, PTH1_OUT, 0, PTH1_IN,
1318 LCDD16_DV_VSYNC, PTH0_OUT, 0, PTH0_IN } 1318 LCDD16_DV_VSYNC, PTH0_OUT, 0, PTH0_IN ))
1319 }, 1319 },
1320 { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) { 1320 { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2, GROUP(
1321 STATUS0, PTJ7_OUT, 0, 0, 1321 STATUS0, PTJ7_OUT, 0, 0,
1322 0, PTJ6_OUT, 0, 0, 1322 0, PTJ6_OUT, 0, 0,
1323 PDSTATUS, PTJ5_OUT, 0, 0, 1323 PDSTATUS, PTJ5_OUT, 0, 0,
@@ -1325,9 +1325,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1325 0, 0, 0, 0, 1325 0, 0, 0, 0,
1326 0, 0, 0, 0, 1326 0, 0, 0, 0,
1327 IRQ1, PTJ1_OUT, 0, PTJ1_IN, 1327 IRQ1, PTJ1_OUT, 0, PTJ1_IN,
1328 IRQ0, PTJ0_OUT, 0, PTJ0_IN } 1328 IRQ0, PTJ0_OUT, 0, PTJ0_IN ))
1329 }, 1329 },
1330 { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) { 1330 { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2, GROUP(
1331 0, 0, 0, 0, 1331 0, 0, 0, 0,
1332 SIUAILR_SIOF1_SS2, PTK6_OUT, 0, PTK6_IN, 1332 SIUAILR_SIOF1_SS2, PTK6_OUT, 0, PTK6_IN,
1333 SIUAIBT_SIOF1_SS1, PTK5_OUT, 0, PTK5_IN, 1333 SIUAIBT_SIOF1_SS1, PTK5_OUT, 0, PTK5_IN,
@@ -1335,9 +1335,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1335 SIUAOBT_SIOF1_SCK, PTK3_OUT, 0, PTK3_IN, 1335 SIUAOBT_SIOF1_SCK, PTK3_OUT, 0, PTK3_IN,
1336 SIUAISLD_SIOF1_RXD, 0, 0, PTK2_IN, 1336 SIUAISLD_SIOF1_RXD, 0, 0, PTK2_IN,
1337 SIUAOSLD_SIOF1_TXD, PTK1_OUT, 0, 0, 1337 SIUAOSLD_SIOF1_TXD, PTK1_OUT, 0, 0,
1338 PTK0, PTK0_OUT, 0, PTK0_IN } 1338 PTK0, PTK0_OUT, 0, PTK0_IN ))
1339 }, 1339 },
1340 { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) { 1340 { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2, GROUP(
1341 LCDD15_DV_D15, PTL7_OUT, 0, PTL7_IN, 1341 LCDD15_DV_D15, PTL7_OUT, 0, PTL7_IN,
1342 LCDD14_DV_D14, PTL6_OUT, 0, PTL6_IN, 1342 LCDD14_DV_D14, PTL6_OUT, 0, PTL6_IN,
1343 LCDD13_DV_D13, PTL5_OUT, 0, PTL5_IN, 1343 LCDD13_DV_D13, PTL5_OUT, 0, PTL5_IN,
@@ -1345,9 +1345,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1345 LCDD11_DV_D11, PTL3_OUT, 0, PTL3_IN, 1345 LCDD11_DV_D11, PTL3_OUT, 0, PTL3_IN,
1346 LCDD10_DV_D10, PTL2_OUT, 0, PTL2_IN, 1346 LCDD10_DV_D10, PTL2_OUT, 0, PTL2_IN,
1347 LCDD9_DV_D9, PTL1_OUT, 0, PTL1_IN, 1347 LCDD9_DV_D9, PTL1_OUT, 0, PTL1_IN,
1348 LCDD8_DV_D8, PTL0_OUT, 0, PTL0_IN } 1348 LCDD8_DV_D8, PTL0_OUT, 0, PTL0_IN ))
1349 }, 1349 },
1350 { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) { 1350 { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2, GROUP(
1351 LCDD7_DV_D7, PTM7_OUT, 0, PTM7_IN, 1351 LCDD7_DV_D7, PTM7_OUT, 0, PTM7_IN,
1352 LCDD6_DV_D6, PTM6_OUT, 0, PTM6_IN, 1352 LCDD6_DV_D6, PTM6_OUT, 0, PTM6_IN,
1353 LCDD5_DV_D5, PTM5_OUT, 0, PTM5_IN, 1353 LCDD5_DV_D5, PTM5_OUT, 0, PTM5_IN,
@@ -1355,9 +1355,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1355 LCDD3_DV_D3, PTM3_OUT, 0, PTM3_IN, 1355 LCDD3_DV_D3, PTM3_OUT, 0, PTM3_IN,
1356 LCDD2_DV_D2, PTM2_OUT, 0, PTM2_IN, 1356 LCDD2_DV_D2, PTM2_OUT, 0, PTM2_IN,
1357 LCDD1_DV_D1, PTM1_OUT, 0, PTM1_IN, 1357 LCDD1_DV_D1, PTM1_OUT, 0, PTM1_IN,
1358 LCDD0_DV_D0, PTM0_OUT, 0, PTM0_IN } 1358 LCDD0_DV_D0, PTM0_OUT, 0, PTM0_IN ))
1359 }, 1359 },
1360 { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) { 1360 { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2, GROUP(
1361 HPD63, PTN7_OUT, 0, PTN7_IN, 1361 HPD63, PTN7_OUT, 0, PTN7_IN,
1362 HPD62, PTN6_OUT, 0, PTN6_IN, 1362 HPD62, PTN6_OUT, 0, PTN6_IN,
1363 HPD61, PTN5_OUT, 0, PTN5_IN, 1363 HPD61, PTN5_OUT, 0, PTN5_IN,
@@ -1365,9 +1365,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1365 HPD59, PTN3_OUT, 0, PTN3_IN, 1365 HPD59, PTN3_OUT, 0, PTN3_IN,
1366 HPD58, PTN2_OUT, 0, PTN2_IN, 1366 HPD58, PTN2_OUT, 0, PTN2_IN,
1367 HPD57, PTN1_OUT, 0, PTN1_IN, 1367 HPD57, PTN1_OUT, 0, PTN1_IN,
1368 HPD56, PTN0_OUT, 0, PTN0_IN } 1368 HPD56, PTN0_OUT, 0, PTN0_IN ))
1369 }, 1369 },
1370 { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) { 1370 { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2, GROUP(
1371 0, 0, 0, 0, 1371 0, 0, 0, 0,
1372 SIOF0_SS2_SIM_RST, PTQ6_OUT, 0, 0, 1372 SIOF0_SS2_SIM_RST, PTQ6_OUT, 0, 0,
1373 SIOF0_SS1_TS_SPSYNC, PTQ5_OUT, 0, PTQ5_IN, 1373 SIOF0_SS1_TS_SPSYNC, PTQ5_OUT, 0, PTQ5_IN,
@@ -1375,9 +1375,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1375 SIOF0_SCK_TS_SCK, PTQ3_OUT, 0, PTQ3_IN, 1375 SIOF0_SCK_TS_SCK, PTQ3_OUT, 0, PTQ3_IN,
1376 PTQ2, 0, 0, PTQ2_IN, 1376 PTQ2, 0, 0, PTQ2_IN,
1377 PTQ1, PTQ1_OUT, 0, 0, 1377 PTQ1, PTQ1_OUT, 0, 0,
1378 PTQ0, PTQ0_OUT, 0, PTQ0_IN } 1378 PTQ0, PTQ0_OUT, 0, PTQ0_IN ))
1379 }, 1379 },
1380 { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) { 1380 { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2, GROUP(
1381 0, 0, 0, 0, 1381 0, 0, 0, 0,
1382 0, 0, 0, 0, 1382 0, 0, 0, 0,
1383 0, 0, 0, 0, 1383 0, 0, 0, 0,
@@ -1385,9 +1385,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1385 CS6B_CE1B_LCDCS2, PTR3_OUT, 0, 0, 1385 CS6B_CE1B_LCDCS2, PTR3_OUT, 0, 0,
1386 WAIT, 0, 0, PTR2_IN, 1386 WAIT, 0, 0, PTR2_IN,
1387 LCDDCK_LCDWR, PTR1_OUT, 0, 0, 1387 LCDDCK_LCDWR, PTR1_OUT, 0, 0,
1388 LCDVEPWC_LCDVEPWC2, PTR0_OUT, 0, 0 } 1388 LCDVEPWC_LCDVEPWC2, PTR0_OUT, 0, 0 ))
1389 }, 1389 },
1390 { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) { 1390 { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2, GROUP(
1391 0, 0, 0, 0, 1391 0, 0, 0, 0,
1392 0, 0, 0, 0, 1392 0, 0, 0, 0,
1393 0, 0, 0, 0, 1393 0, 0, 0, 0,
@@ -1395,9 +1395,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1395 SCIF0_RTS_SIUAOSPD, PTS3_OUT, 0, 0, 1395 SCIF0_RTS_SIUAOSPD, PTS3_OUT, 0, 0,
1396 SCIF0_SCK_TPUTO, PTS2_OUT, 0, PTS2_IN, 1396 SCIF0_SCK_TPUTO, PTS2_OUT, 0, PTS2_IN,
1397 SCIF0_RXD, 0, 0, PTS1_IN, 1397 SCIF0_RXD, 0, 0, PTS1_IN,
1398 SCIF0_TXD, PTS0_OUT, 0, 0 } 1398 SCIF0_TXD, PTS0_OUT, 0, 0 ))
1399 }, 1399 },
1400 { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) { 1400 { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2, GROUP(
1401 0, 0, 0, 0, 1401 0, 0, 0, 0,
1402 0, 0, 0, 0, 1402 0, 0, 0, 0,
1403 0, 0, 0, 0, 1403 0, 0, 0, 0,
@@ -1405,9 +1405,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1405 FWE, PTT3_OUT, 0, PTT3_IN, 1405 FWE, PTT3_OUT, 0, PTT3_IN,
1406 FSC, PTT2_OUT, 0, PTT2_IN, 1406 FSC, PTT2_OUT, 0, PTT2_IN,
1407 DREQ0, 0, 0, PTT1_IN, 1407 DREQ0, 0, 0, PTT1_IN,
1408 FCDE, PTT0_OUT, 0, 0 } 1408 FCDE, PTT0_OUT, 0, 0 ))
1409 }, 1409 },
1410 { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) { 1410 { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2, GROUP(
1411 0, 0, 0, 0, 1411 0, 0, 0, 0,
1412 0, 0, 0, 0, 1412 0, 0, 0, 0,
1413 0, 0, 0, 0, 1413 0, 0, 0, 0,
@@ -1415,9 +1415,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1415 NAF1_VIO_D9, PTU3_OUT, 0, PTU3_IN, 1415 NAF1_VIO_D9, PTU3_OUT, 0, PTU3_IN,
1416 NAF0_VIO_D8, PTU2_OUT, 0, PTU2_IN, 1416 NAF0_VIO_D8, PTU2_OUT, 0, PTU2_IN,
1417 FRB_VIO_CLK2, 0, 0, PTU1_IN, 1417 FRB_VIO_CLK2, 0, 0, PTU1_IN,
1418 FCE_VIO_HD2, PTU0_OUT, 0, PTU0_IN } 1418 FCE_VIO_HD2, PTU0_OUT, 0, PTU0_IN ))
1419 }, 1419 },
1420 { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) { 1420 { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2, GROUP(
1421 0, 0, 0, 0, 1421 0, 0, 0, 0,
1422 0, 0, 0, 0, 1422 0, 0, 0, 0,
1423 0, 0, 0, 0, 1423 0, 0, 0, 0,
@@ -1425,9 +1425,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1425 NAF6_VIO_D14, PTV3_OUT, 0, PTV3_IN, 1425 NAF6_VIO_D14, PTV3_OUT, 0, PTV3_IN,
1426 NAF5_VIO_D13, PTV2_OUT, 0, PTV2_IN, 1426 NAF5_VIO_D13, PTV2_OUT, 0, PTV2_IN,
1427 NAF4_VIO_D12, PTV1_OUT, 0, PTV1_IN, 1427 NAF4_VIO_D12, PTV1_OUT, 0, PTV1_IN,
1428 NAF3_VIO_D11, PTV0_OUT, 0, PTV0_IN } 1428 NAF3_VIO_D11, PTV0_OUT, 0, PTV0_IN ))
1429 }, 1429 },
1430 { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) { 1430 { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2, GROUP(
1431 0, 0, 0, 0, 1431 0, 0, 0, 0,
1432 VIO_FLD_SCIF2_CTS, 0, 0, PTW6_IN, 1432 VIO_FLD_SCIF2_CTS, 0, 0, PTW6_IN,
1433 VIO_CKO_SCIF2_RTS, PTW5_OUT, 0, 0, 1433 VIO_CKO_SCIF2_RTS, PTW5_OUT, 0, 0,
@@ -1435,9 +1435,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1435 VIO_STEM_SCIF2_TXD, PTW3_OUT, 0, PTW3_IN, 1435 VIO_STEM_SCIF2_TXD, PTW3_OUT, 0, PTW3_IN,
1436 VIO_HD_SCIF2_RXD, PTW2_OUT, 0, PTW2_IN, 1436 VIO_HD_SCIF2_RXD, PTW2_OUT, 0, PTW2_IN,
1437 VIO_VD_SCIF1_CTS, PTW1_OUT, 0, PTW1_IN, 1437 VIO_VD_SCIF1_CTS, PTW1_OUT, 0, PTW1_IN,
1438 VIO_CLK_SCIF1_RTS, PTW0_OUT, 0, PTW0_IN } 1438 VIO_CLK_SCIF1_RTS, PTW0_OUT, 0, PTW0_IN ))
1439 }, 1439 },
1440 { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) { 1440 { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2, GROUP(
1441 0, 0, 0, 0, 1441 0, 0, 0, 0,
1442 CS6A_CE2B, PTX6_OUT, 0, PTX6_IN, 1442 CS6A_CE2B, PTX6_OUT, 0, PTX6_IN,
1443 LCDD23, PTX5_OUT, 0, PTX5_IN, 1443 LCDD23, PTX5_OUT, 0, PTX5_IN,
@@ -1445,9 +1445,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1445 LCDD21, PTX3_OUT, 0, PTX3_IN, 1445 LCDD21, PTX3_OUT, 0, PTX3_IN,
1446 LCDD20, PTX2_OUT, 0, PTX2_IN, 1446 LCDD20, PTX2_OUT, 0, PTX2_IN,
1447 LCDD19_DV_CLKI, PTX1_OUT, 0, PTX1_IN, 1447 LCDD19_DV_CLKI, PTX1_OUT, 0, PTX1_IN,
1448 LCDD18_DV_CLK, PTX0_OUT, 0, PTX0_IN } 1448 LCDD18_DV_CLK, PTX0_OUT, 0, PTX0_IN ))
1449 }, 1449 },
1450 { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) { 1450 { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2, GROUP(
1451 0, 0, 0, 0, 1451 0, 0, 0, 0,
1452 0, 0, 0, 0, 1452 0, 0, 0, 0,
1453 KEYOUT5_IN5, PTY5_OUT, 0, PTY5_IN, 1453 KEYOUT5_IN5, PTY5_OUT, 0, PTY5_IN,
@@ -1455,9 +1455,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1455 KEYOUT3, PTY3_OUT, 0, PTY3_IN, 1455 KEYOUT3, PTY3_OUT, 0, PTY3_IN,
1456 KEYOUT2, PTY2_OUT, 0, PTY2_IN, 1456 KEYOUT2, PTY2_OUT, 0, PTY2_IN,
1457 KEYOUT1, PTY1_OUT, 0, 0, 1457 KEYOUT1, PTY1_OUT, 0, 0,
1458 KEYOUT0, PTY0_OUT, 0, PTY0_IN } 1458 KEYOUT0, PTY0_OUT, 0, PTY0_IN ))
1459 }, 1459 },
1460 { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) { 1460 { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2, GROUP(
1461 0, 0, 0, 0, 1461 0, 0, 0, 0,
1462 0, 0, 0, 0, 1462 0, 0, 0, 0,
1463 KEYIN4_IRQ7, 0, 0, PTZ5_IN, 1463 KEYIN4_IRQ7, 0, 0, PTZ5_IN,
@@ -1465,9 +1465,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1465 KEYIN2, 0, 0, PTZ3_IN, 1465 KEYIN2, 0, 0, PTZ3_IN,
1466 KEYIN1, 0, 0, PTZ2_IN, 1466 KEYIN1, 0, 0, PTZ2_IN,
1467 KEYIN0_IRQ6, 0, 0, PTZ1_IN, 1467 KEYIN0_IRQ6, 0, 0, PTZ1_IN,
1468 0, 0, 0, 0 } 1468 0, 0, 0, 0 ))
1469 }, 1469 },
1470 { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) { 1470 { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1, GROUP(
1471 PSA15_KEYIN0, PSA15_IRQ6, 1471 PSA15_KEYIN0, PSA15_IRQ6,
1472 PSA14_KEYIN4, PSA14_IRQ7, 1472 PSA14_KEYIN4, PSA14_IRQ7,
1473 0, 0, 1473 0, 0,
@@ -1483,9 +1483,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1483 0, 0, 1483 0, 0,
1484 0, 0, 1484 0, 0,
1485 0, 0, 1485 0, 0,
1486 0, 0 } 1486 0, 0 ))
1487 }, 1487 },
1488 { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1) { 1488 { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1, GROUP(
1489 PSB15_SIOTXD, PSB15_SIUBOSLD, 1489 PSB15_SIOTXD, PSB15_SIUBOSLD,
1490 PSB14_SIORXD, PSB14_SIUBISLD, 1490 PSB14_SIORXD, PSB14_SIUBISLD,
1491 PSB13_SIOD, PSB13_SIUBILR, 1491 PSB13_SIOD, PSB13_SIUBILR,
@@ -1501,9 +1501,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1501 PSB3_SIOF0_SS1, PSB3_TS_SPSYNC, 1501 PSB3_SIOF0_SS1, PSB3_TS_SPSYNC,
1502 PSB2_SIOF0_SS2, PSB2_SIM_RST, 1502 PSB2_SIOF0_SS2, PSB2_SIM_RST,
1503 PSB1_SIUMCKA, PSB1_SIOF1_MCK, 1503 PSB1_SIUMCKA, PSB1_SIOF1_MCK,
1504 PSB0_SIUAOSLD, PSB0_SIOF1_TXD } 1504 PSB0_SIUAOSLD, PSB0_SIOF1_TXD ))
1505 }, 1505 },
1506 { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1) { 1506 { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1, GROUP(
1507 PSC15_SIUAISLD, PSC15_SIOF1_RXD, 1507 PSC15_SIUAISLD, PSC15_SIOF1_RXD,
1508 PSC14_SIUAOBT, PSC14_SIOF1_SCK, 1508 PSC14_SIUAOBT, PSC14_SIOF1_SCK,
1509 PSC13_SIUAOLR, PSC13_SIOF1_SYNC, 1509 PSC13_SIUAOLR, PSC13_SIOF1_SYNC,
@@ -1519,9 +1519,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1519 0, 0, 1519 0, 0,
1520 0, 0, 1520 0, 0,
1521 0, 0, 1521 0, 0,
1522 PSC0_NAF, PSC0_VIO } 1522 PSC0_NAF, PSC0_VIO ))
1523 }, 1523 },
1524 { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1) { 1524 { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1, GROUP(
1525 0, 0, 1525 0, 0,
1526 0, 0, 1526 0, 0,
1527 PSD13_VIO, PSD13_SCIF2, 1527 PSD13_VIO, PSD13_SCIF2,
@@ -1537,9 +1537,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1537 PSD3_LCDVEPWC_LCDVCPWC, PSD3_LCDVEPWC2_LCDVCPWC2, 1537 PSD3_LCDVEPWC_LCDVCPWC, PSD3_LCDVEPWC2_LCDVCPWC2,
1538 PSD2_LCDDON, PSD2_LCDDON2, 1538 PSD2_LCDDON, PSD2_LCDDON2,
1539 0, 0, 1539 0, 0,
1540 PSD0_LCDD19_LCDD0, PSD0_DV } 1540 PSD0_LCDD19_LCDD0, PSD0_DV ))
1541 }, 1541 },
1542 { PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1) { 1542 { PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1, GROUP(
1543 PSE15_SIOF0_MCK_IRQ3, PSE15_SIM_D, 1543 PSE15_SIOF0_MCK_IRQ3, PSE15_SIM_D,
1544 PSE14_SIOF0_TXD_IRDA_OUT, PSE14_SIM_CLK, 1544 PSE14_SIOF0_TXD_IRDA_OUT, PSE14_SIM_CLK,
1545 PSE13_SIOF0_RXD_IRDA_IN, PSE13_TS_SDAT, 1545 PSE13_SIOF0_RXD_IRDA_IN, PSE13_TS_SDAT,
@@ -1555,9 +1555,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1555 PSE3_FLCTL, PSE3_VIO, 1555 PSE3_FLCTL, PSE3_VIO,
1556 PSE2_NAF2, PSE2_VIO_D10, 1556 PSE2_NAF2, PSE2_VIO_D10,
1557 PSE1_NAF1, PSE1_VIO_D9, 1557 PSE1_NAF1, PSE1_VIO_D9,
1558 PSE0_NAF0, PSE0_VIO_D8 } 1558 PSE0_NAF0, PSE0_VIO_D8 ))
1559 }, 1559 },
1560 { PINMUX_CFG_REG("HIZCRA", 0xa4050158, 16, 1) { 1560 { PINMUX_CFG_REG("HIZCRA", 0xa4050158, 16, 1, GROUP(
1561 0, 0, 1561 0, 0,
1562 HIZA14_KEYSC, HIZA14_HIZ, 1562 HIZA14_KEYSC, HIZA14_HIZ,
1563 0, 0, 1563 0, 0,
@@ -1573,9 +1573,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1573 0, 0, 1573 0, 0,
1574 0, 0, 1574 0, 0,
1575 0, 0, 1575 0, 0,
1576 0, 0 } 1576 0, 0 ))
1577 }, 1577 },
1578 { PINMUX_CFG_REG("HIZCRB", 0xa405015a, 16, 1) { 1578 { PINMUX_CFG_REG("HIZCRB", 0xa405015a, 16, 1, GROUP(
1579 0, 0, 1579 0, 0,
1580 0, 0, 1580 0, 0,
1581 0, 0, 1581 0, 0,
@@ -1591,9 +1591,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1591 0, 0, 1591 0, 0,
1592 0, 0, 1592 0, 0,
1593 HIZB1_VIO, HIZB1_HIZ, 1593 HIZB1_VIO, HIZB1_HIZ,
1594 HIZB0_VIO, HIZB0_HIZ } 1594 HIZB0_VIO, HIZB0_HIZ ))
1595 }, 1595 },
1596 { PINMUX_CFG_REG("HIZCRC", 0xa405015c, 16, 1) { 1596 { PINMUX_CFG_REG("HIZCRC", 0xa405015c, 16, 1, GROUP(
1597 HIZC15_IRQ7, HIZC15_HIZ, 1597 HIZC15_IRQ7, HIZC15_HIZ,
1598 HIZC14_IRQ6, HIZC14_HIZ, 1598 HIZC14_IRQ6, HIZC14_HIZ,
1599 HIZC13_IRQ5, HIZC13_HIZ, 1599 HIZC13_IRQ5, HIZC13_HIZ,
@@ -1609,9 +1609,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1609 0, 0, 1609 0, 0,
1610 0, 0, 1610 0, 0,
1611 0, 0, 1611 0, 0,
1612 0, 0 } 1612 0, 0 ))
1613 }, 1613 },
1614 { PINMUX_CFG_REG("MSELCRB", 0xa4050182, 16, 1) { 1614 { PINMUX_CFG_REG("MSELCRB", 0xa4050182, 16, 1, GROUP(
1615 0, 0, 1615 0, 0,
1616 0, 0, 1616 0, 0,
1617 0, 0, 1617 0, 0,
@@ -1627,103 +1627,103 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1627 0, 0, 1627 0, 0,
1628 0, 0, 1628 0, 0,
1629 0, 0, 1629 0, 0,
1630 0, 0 } 1630 0, 0 ))
1631 }, 1631 },
1632 {} 1632 {}
1633}; 1633};
1634 1634
1635static const struct pinmux_data_reg pinmux_data_regs[] = { 1635static const struct pinmux_data_reg pinmux_data_regs[] = {
1636 { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { 1636 { PINMUX_DATA_REG("PADR", 0xa4050120, 8, GROUP(
1637 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, 1637 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
1638 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } 1638 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA ))
1639 }, 1639 },
1640 { PINMUX_DATA_REG("PBDR", 0xa4050122, 8) { 1640 { PINMUX_DATA_REG("PBDR", 0xa4050122, 8, GROUP(
1641 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, 1641 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
1642 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA } 1642 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA ))
1643 }, 1643 },
1644 { PINMUX_DATA_REG("PCDR", 0xa4050124, 8) { 1644 { PINMUX_DATA_REG("PCDR", 0xa4050124, 8, GROUP(
1645 PTC7_DATA, 0, PTC5_DATA, PTC4_DATA, 1645 PTC7_DATA, 0, PTC5_DATA, PTC4_DATA,
1646 PTC3_DATA, PTC2_DATA, 0, PTC0_DATA } 1646 PTC3_DATA, PTC2_DATA, 0, PTC0_DATA ))
1647 }, 1647 },
1648 { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) { 1648 { PINMUX_DATA_REG("PDDR", 0xa4050126, 8, GROUP(
1649 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, 1649 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
1650 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA } 1650 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA ))
1651 }, 1651 },
1652 { PINMUX_DATA_REG("PEDR", 0xa4050128, 8) { 1652 { PINMUX_DATA_REG("PEDR", 0xa4050128, 8, GROUP(
1653 PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA, 1653 PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
1654 0, 0, PTE1_DATA, PTE0_DATA } 1654 0, 0, PTE1_DATA, PTE0_DATA ))
1655 }, 1655 },
1656 { PINMUX_DATA_REG("PFDR", 0xa405012a, 8) { 1656 { PINMUX_DATA_REG("PFDR", 0xa405012a, 8, GROUP(
1657 0, PTF6_DATA, PTF5_DATA, PTF4_DATA, 1657 0, PTF6_DATA, PTF5_DATA, PTF4_DATA,
1658 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA } 1658 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA ))
1659 }, 1659 },
1660 { PINMUX_DATA_REG("PGDR", 0xa405012c, 8) { 1660 { PINMUX_DATA_REG("PGDR", 0xa405012c, 8, GROUP(
1661 0, 0, 0, PTG4_DATA, 1661 0, 0, 0, PTG4_DATA,
1662 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA } 1662 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA ))
1663 }, 1663 },
1664 { PINMUX_DATA_REG("PHDR", 0xa405012e, 8) { 1664 { PINMUX_DATA_REG("PHDR", 0xa405012e, 8, GROUP(
1665 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA, 1665 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
1666 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA } 1666 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA ))
1667 }, 1667 },
1668 { PINMUX_DATA_REG("PJDR", 0xa4050130, 8) { 1668 { PINMUX_DATA_REG("PJDR", 0xa4050130, 8, GROUP(
1669 PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0, 1669 PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0,
1670 0, 0, PTJ1_DATA, PTJ0_DATA } 1670 0, 0, PTJ1_DATA, PTJ0_DATA ))
1671 }, 1671 },
1672 { PINMUX_DATA_REG("PKDR", 0xa4050132, 8) { 1672 { PINMUX_DATA_REG("PKDR", 0xa4050132, 8, GROUP(
1673 0, PTK6_DATA, PTK5_DATA, PTK4_DATA, 1673 0, PTK6_DATA, PTK5_DATA, PTK4_DATA,
1674 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA } 1674 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA ))
1675 }, 1675 },
1676 { PINMUX_DATA_REG("PLDR", 0xa4050134, 8) { 1676 { PINMUX_DATA_REG("PLDR", 0xa4050134, 8, GROUP(
1677 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, 1677 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
1678 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA } 1678 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA ))
1679 }, 1679 },
1680 { PINMUX_DATA_REG("PMDR", 0xa4050136, 8) { 1680 { PINMUX_DATA_REG("PMDR", 0xa4050136, 8, GROUP(
1681 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, 1681 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
1682 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA } 1682 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA ))
1683 }, 1683 },
1684 { PINMUX_DATA_REG("PNDR", 0xa4050138, 8) { 1684 { PINMUX_DATA_REG("PNDR", 0xa4050138, 8, GROUP(
1685 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, 1685 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
1686 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA } 1686 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA ))
1687 }, 1687 },
1688 { PINMUX_DATA_REG("PQDR", 0xa405013a, 8) { 1688 { PINMUX_DATA_REG("PQDR", 0xa405013a, 8, GROUP(
1689 0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA, 1689 0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
1690 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA } 1690 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA ))
1691 }, 1691 },
1692 { PINMUX_DATA_REG("PRDR", 0xa405013c, 8) { 1692 { PINMUX_DATA_REG("PRDR", 0xa405013c, 8, GROUP(
1693 0, 0, 0, PTR4_DATA, 1693 0, 0, 0, PTR4_DATA,
1694 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA } 1694 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA ))
1695 }, 1695 },
1696 { PINMUX_DATA_REG("PSDR", 0xa405013e, 8) { 1696 { PINMUX_DATA_REG("PSDR", 0xa405013e, 8, GROUP(
1697 0, 0, 0, PTS4_DATA, 1697 0, 0, 0, PTS4_DATA,
1698 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA } 1698 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA ))
1699 }, 1699 },
1700 { PINMUX_DATA_REG("PTDR", 0xa4050160, 8) { 1700 { PINMUX_DATA_REG("PTDR", 0xa4050160, 8, GROUP(
1701 0, 0, 0, PTT4_DATA, 1701 0, 0, 0, PTT4_DATA,
1702 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA } 1702 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA ))
1703 }, 1703 },
1704 { PINMUX_DATA_REG("PUDR", 0xa4050162, 8) { 1704 { PINMUX_DATA_REG("PUDR", 0xa4050162, 8, GROUP(
1705 0, 0, 0, PTU4_DATA, 1705 0, 0, 0, PTU4_DATA,
1706 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA } 1706 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA ))
1707 }, 1707 },
1708 { PINMUX_DATA_REG("PVDR", 0xa4050164, 8) { 1708 { PINMUX_DATA_REG("PVDR", 0xa4050164, 8, GROUP(
1709 0, 0, 0, PTV4_DATA, 1709 0, 0, 0, PTV4_DATA,
1710 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA } 1710 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
1711 }, 1711 },
1712 { PINMUX_DATA_REG("PWDR", 0xa4050166, 8) { 1712 { PINMUX_DATA_REG("PWDR", 0xa4050166, 8, GROUP(
1713 0, PTW6_DATA, PTW5_DATA, PTW4_DATA, 1713 0, PTW6_DATA, PTW5_DATA, PTW4_DATA,
1714 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA } 1714 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA ))
1715 }, 1715 },
1716 { PINMUX_DATA_REG("PXDR", 0xa4050168, 8) { 1716 { PINMUX_DATA_REG("PXDR", 0xa4050168, 8, GROUP(
1717 0, PTX6_DATA, PTX5_DATA, PTX4_DATA, 1717 0, PTX6_DATA, PTX5_DATA, PTX4_DATA,
1718 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA } 1718 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA ))
1719 }, 1719 },
1720 { PINMUX_DATA_REG("PYDR", 0xa405016a, 8) { 1720 { PINMUX_DATA_REG("PYDR", 0xa405016a, 8, GROUP(
1721 0, PTY6_DATA, PTY5_DATA, PTY4_DATA, 1721 0, PTY6_DATA, PTY5_DATA, PTY4_DATA,
1722 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA } 1722 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA ))
1723 }, 1723 },
1724 { PINMUX_DATA_REG("PZDR", 0xa405016c, 8) { 1724 { PINMUX_DATA_REG("PZDR", 0xa405016c, 8, GROUP(
1725 0, 0, PTZ5_DATA, PTZ4_DATA, 1725 0, 0, PTZ5_DATA, PTZ4_DATA,
1726 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA } 1726 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
1727 }, 1727 },
1728 { }, 1728 { },
1729}; 1729};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
index 86f9a88726b7..6f08f527c010 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
@@ -1507,7 +1507,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
1507}; 1507};
1508 1508
1509static const struct pinmux_cfg_reg pinmux_config_regs[] = { 1509static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1510 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { 1510 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2, GROUP(
1511 PTA7_FN, PTA7_OUT, 0, PTA7_IN, 1511 PTA7_FN, PTA7_OUT, 0, PTA7_IN,
1512 PTA6_FN, PTA6_OUT, 0, PTA6_IN, 1512 PTA6_FN, PTA6_OUT, 0, PTA6_IN,
1513 PTA5_FN, PTA5_OUT, 0, PTA5_IN, 1513 PTA5_FN, PTA5_OUT, 0, PTA5_IN,
@@ -1515,9 +1515,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1515 PTA3_FN, PTA3_OUT, 0, PTA3_IN, 1515 PTA3_FN, PTA3_OUT, 0, PTA3_IN,
1516 PTA2_FN, PTA2_OUT, 0, PTA2_IN, 1516 PTA2_FN, PTA2_OUT, 0, PTA2_IN,
1517 PTA1_FN, PTA1_OUT, 0, PTA1_IN, 1517 PTA1_FN, PTA1_OUT, 0, PTA1_IN,
1518 PTA0_FN, PTA0_OUT, 0, PTA0_IN } 1518 PTA0_FN, PTA0_OUT, 0, PTA0_IN ))
1519 }, 1519 },
1520 { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) { 1520 { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2, GROUP(
1521 PTB7_FN, PTB7_OUT, 0, PTB7_IN, 1521 PTB7_FN, PTB7_OUT, 0, PTB7_IN,
1522 PTB6_FN, PTB6_OUT, 0, PTB6_IN, 1522 PTB6_FN, PTB6_OUT, 0, PTB6_IN,
1523 PTB5_FN, PTB5_OUT, 0, PTB5_IN, 1523 PTB5_FN, PTB5_OUT, 0, PTB5_IN,
@@ -1525,9 +1525,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1525 PTB3_FN, PTB3_OUT, 0, PTB3_IN, 1525 PTB3_FN, PTB3_OUT, 0, PTB3_IN,
1526 PTB2_FN, PTB2_OUT, 0, PTB2_IN, 1526 PTB2_FN, PTB2_OUT, 0, PTB2_IN,
1527 PTB1_FN, PTB1_OUT, 0, PTB1_IN, 1527 PTB1_FN, PTB1_OUT, 0, PTB1_IN,
1528 PTB0_FN, PTB0_OUT, 0, PTB0_IN } 1528 PTB0_FN, PTB0_OUT, 0, PTB0_IN ))
1529 }, 1529 },
1530 { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) { 1530 { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2, GROUP(
1531 PTC7_FN, PTC7_OUT, 0, PTC7_IN, 1531 PTC7_FN, PTC7_OUT, 0, PTC7_IN,
1532 PTC6_FN, PTC6_OUT, 0, PTC6_IN, 1532 PTC6_FN, PTC6_OUT, 0, PTC6_IN,
1533 PTC5_FN, PTC5_OUT, 0, PTC5_IN, 1533 PTC5_FN, PTC5_OUT, 0, PTC5_IN,
@@ -1535,9 +1535,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1535 PTC3_FN, PTC3_OUT, 0, PTC3_IN, 1535 PTC3_FN, PTC3_OUT, 0, PTC3_IN,
1536 PTC2_FN, PTC2_OUT, 0, PTC2_IN, 1536 PTC2_FN, PTC2_OUT, 0, PTC2_IN,
1537 PTC1_FN, PTC1_OUT, 0, PTC1_IN, 1537 PTC1_FN, PTC1_OUT, 0, PTC1_IN,
1538 PTC0_FN, PTC0_OUT, 0, PTC0_IN } 1538 PTC0_FN, PTC0_OUT, 0, PTC0_IN ))
1539 }, 1539 },
1540 { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) { 1540 { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2, GROUP(
1541 PTD7_FN, PTD7_OUT, 0, PTD7_IN, 1541 PTD7_FN, PTD7_OUT, 0, PTD7_IN,
1542 PTD6_FN, PTD6_OUT, 0, PTD6_IN, 1542 PTD6_FN, PTD6_OUT, 0, PTD6_IN,
1543 PTD5_FN, PTD5_OUT, 0, PTD5_IN, 1543 PTD5_FN, PTD5_OUT, 0, PTD5_IN,
@@ -1545,9 +1545,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1545 PTD3_FN, PTD3_OUT, 0, PTD3_IN, 1545 PTD3_FN, PTD3_OUT, 0, PTD3_IN,
1546 PTD2_FN, PTD2_OUT, 0, PTD2_IN, 1546 PTD2_FN, PTD2_OUT, 0, PTD2_IN,
1547 PTD1_FN, PTD1_OUT, 0, PTD1_IN, 1547 PTD1_FN, PTD1_OUT, 0, PTD1_IN,
1548 PTD0_FN, PTD0_OUT, 0, PTD0_IN } 1548 PTD0_FN, PTD0_OUT, 0, PTD0_IN ))
1549 }, 1549 },
1550 { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) { 1550 { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2, GROUP(
1551 0, 0, 0, 0, 1551 0, 0, 0, 0,
1552 0, 0, 0, 0, 1552 0, 0, 0, 0,
1553 PTE5_FN, PTE5_OUT, 0, PTE5_IN, 1553 PTE5_FN, PTE5_OUT, 0, PTE5_IN,
@@ -1555,9 +1555,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1555 PTE3_FN, PTE3_OUT, 0, PTE3_IN, 1555 PTE3_FN, PTE3_OUT, 0, PTE3_IN,
1556 PTE2_FN, PTE2_OUT, 0, PTE2_IN, 1556 PTE2_FN, PTE2_OUT, 0, PTE2_IN,
1557 PTE1_FN, PTE1_OUT, 0, PTE1_IN, 1557 PTE1_FN, PTE1_OUT, 0, PTE1_IN,
1558 PTE0_FN, PTE0_OUT, 0, PTE0_IN } 1558 PTE0_FN, PTE0_OUT, 0, PTE0_IN ))
1559 }, 1559 },
1560 { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) { 1560 { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2, GROUP(
1561 PTF7_FN, PTF7_OUT, 0, PTF7_IN, 1561 PTF7_FN, PTF7_OUT, 0, PTF7_IN,
1562 PTF6_FN, PTF6_OUT, 0, PTF6_IN, 1562 PTF6_FN, PTF6_OUT, 0, PTF6_IN,
1563 PTF5_FN, PTF5_OUT, 0, PTF5_IN, 1563 PTF5_FN, PTF5_OUT, 0, PTF5_IN,
@@ -1565,9 +1565,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1565 PTF3_FN, PTF3_OUT, 0, PTF3_IN, 1565 PTF3_FN, PTF3_OUT, 0, PTF3_IN,
1566 PTF2_FN, PTF2_OUT, 0, PTF2_IN, 1566 PTF2_FN, PTF2_OUT, 0, PTF2_IN,
1567 PTF1_FN, PTF1_OUT, 0, PTF1_IN, 1567 PTF1_FN, PTF1_OUT, 0, PTF1_IN,
1568 PTF0_FN, PTF0_OUT, 0, PTF0_IN } 1568 PTF0_FN, PTF0_OUT, 0, PTF0_IN ))
1569 }, 1569 },
1570 { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) { 1570 { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2, GROUP(
1571 0, 0, 0, 0, 1571 0, 0, 0, 0,
1572 0, 0, 0, 0, 1572 0, 0, 0, 0,
1573 PTG5_FN, PTG5_OUT, 0, 0, 1573 PTG5_FN, PTG5_OUT, 0, 0,
@@ -1575,9 +1575,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1575 PTG3_FN, PTG3_OUT, 0, 0, 1575 PTG3_FN, PTG3_OUT, 0, 0,
1576 PTG2_FN, PTG2_OUT, 0, 0, 1576 PTG2_FN, PTG2_OUT, 0, 0,
1577 PTG1_FN, PTG1_OUT, 0, 0, 1577 PTG1_FN, PTG1_OUT, 0, 0,
1578 PTG0_FN, PTG0_OUT, 0, 0 } 1578 PTG0_FN, PTG0_OUT, 0, 0 ))
1579 }, 1579 },
1580 { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) { 1580 { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2, GROUP(
1581 PTH7_FN, PTH7_OUT, 0, PTH7_IN, 1581 PTH7_FN, PTH7_OUT, 0, PTH7_IN,
1582 PTH6_FN, PTH6_OUT, 0, PTH6_IN, 1582 PTH6_FN, PTH6_OUT, 0, PTH6_IN,
1583 PTH5_FN, PTH5_OUT, 0, PTH5_IN, 1583 PTH5_FN, PTH5_OUT, 0, PTH5_IN,
@@ -1585,9 +1585,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1585 PTH3_FN, PTH3_OUT, 0, PTH3_IN, 1585 PTH3_FN, PTH3_OUT, 0, PTH3_IN,
1586 PTH2_FN, PTH2_OUT, 0, PTH2_IN, 1586 PTH2_FN, PTH2_OUT, 0, PTH2_IN,
1587 PTH1_FN, PTH1_OUT, 0, PTH1_IN, 1587 PTH1_FN, PTH1_OUT, 0, PTH1_IN,
1588 PTH0_FN, PTH0_OUT, 0, PTH0_IN } 1588 PTH0_FN, PTH0_OUT, 0, PTH0_IN ))
1589 }, 1589 },
1590 { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) { 1590 { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2, GROUP(
1591 PTJ7_FN, PTJ7_OUT, 0, 0, 1591 PTJ7_FN, PTJ7_OUT, 0, 0,
1592 0, 0, 0, 0, 1592 0, 0, 0, 0,
1593 PTJ5_FN, PTJ5_OUT, 0, 0, 1593 PTJ5_FN, PTJ5_OUT, 0, 0,
@@ -1595,9 +1595,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1595 PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN, 1595 PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN,
1596 PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN, 1596 PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN,
1597 PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN, 1597 PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN,
1598 PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN } 1598 PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN ))
1599 }, 1599 },
1600 { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) { 1600 { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2, GROUP(
1601 PTK7_FN, PTK7_OUT, 0, PTK7_IN, 1601 PTK7_FN, PTK7_OUT, 0, PTK7_IN,
1602 PTK6_FN, PTK6_OUT, 0, PTK6_IN, 1602 PTK6_FN, PTK6_OUT, 0, PTK6_IN,
1603 PTK5_FN, PTK5_OUT, 0, PTK5_IN, 1603 PTK5_FN, PTK5_OUT, 0, PTK5_IN,
@@ -1605,9 +1605,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1605 PTK3_FN, PTK3_OUT, 0, PTK3_IN, 1605 PTK3_FN, PTK3_OUT, 0, PTK3_IN,
1606 PTK2_FN, PTK2_OUT, 0, PTK2_IN, 1606 PTK2_FN, PTK2_OUT, 0, PTK2_IN,
1607 PTK1_FN, PTK1_OUT, 0, PTK1_IN, 1607 PTK1_FN, PTK1_OUT, 0, PTK1_IN,
1608 PTK0_FN, PTK0_OUT, 0, PTK0_IN } 1608 PTK0_FN, PTK0_OUT, 0, PTK0_IN ))
1609 }, 1609 },
1610 { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) { 1610 { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2, GROUP(
1611 PTL7_FN, PTL7_OUT, 0, PTL7_IN, 1611 PTL7_FN, PTL7_OUT, 0, PTL7_IN,
1612 PTL6_FN, PTL6_OUT, 0, PTL6_IN, 1612 PTL6_FN, PTL6_OUT, 0, PTL6_IN,
1613 PTL5_FN, PTL5_OUT, 0, PTL5_IN, 1613 PTL5_FN, PTL5_OUT, 0, PTL5_IN,
@@ -1615,9 +1615,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1615 PTL3_FN, PTL3_OUT, 0, PTL3_IN, 1615 PTL3_FN, PTL3_OUT, 0, PTL3_IN,
1616 PTL2_FN, PTL2_OUT, 0, PTL2_IN, 1616 PTL2_FN, PTL2_OUT, 0, PTL2_IN,
1617 PTL1_FN, PTL1_OUT, 0, PTL1_IN, 1617 PTL1_FN, PTL1_OUT, 0, PTL1_IN,
1618 PTL0_FN, PTL0_OUT, 0, PTL0_IN } 1618 PTL0_FN, PTL0_OUT, 0, PTL0_IN ))
1619 }, 1619 },
1620 { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) { 1620 { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2, GROUP(
1621 PTM7_FN, PTM7_OUT, 0, PTM7_IN, 1621 PTM7_FN, PTM7_OUT, 0, PTM7_IN,
1622 PTM6_FN, PTM6_OUT, 0, PTM6_IN, 1622 PTM6_FN, PTM6_OUT, 0, PTM6_IN,
1623 PTM5_FN, PTM5_OUT, 0, PTM5_IN, 1623 PTM5_FN, PTM5_OUT, 0, PTM5_IN,
@@ -1625,9 +1625,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1625 PTM3_FN, PTM3_OUT, 0, PTM3_IN, 1625 PTM3_FN, PTM3_OUT, 0, PTM3_IN,
1626 PTM2_FN, PTM2_OUT, 0, PTM2_IN, 1626 PTM2_FN, PTM2_OUT, 0, PTM2_IN,
1627 PTM1_FN, PTM1_OUT, 0, PTM1_IN, 1627 PTM1_FN, PTM1_OUT, 0, PTM1_IN,
1628 PTM0_FN, PTM0_OUT, 0, PTM0_IN } 1628 PTM0_FN, PTM0_OUT, 0, PTM0_IN ))
1629 }, 1629 },
1630 { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) { 1630 { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2, GROUP(
1631 PTN7_FN, PTN7_OUT, 0, PTN7_IN, 1631 PTN7_FN, PTN7_OUT, 0, PTN7_IN,
1632 PTN6_FN, PTN6_OUT, 0, PTN6_IN, 1632 PTN6_FN, PTN6_OUT, 0, PTN6_IN,
1633 PTN5_FN, PTN5_OUT, 0, PTN5_IN, 1633 PTN5_FN, PTN5_OUT, 0, PTN5_IN,
@@ -1635,9 +1635,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1635 PTN3_FN, PTN3_OUT, 0, PTN3_IN, 1635 PTN3_FN, PTN3_OUT, 0, PTN3_IN,
1636 PTN2_FN, PTN2_OUT, 0, PTN2_IN, 1636 PTN2_FN, PTN2_OUT, 0, PTN2_IN,
1637 PTN1_FN, PTN1_OUT, 0, PTN1_IN, 1637 PTN1_FN, PTN1_OUT, 0, PTN1_IN,
1638 PTN0_FN, PTN0_OUT, 0, PTN0_IN } 1638 PTN0_FN, PTN0_OUT, 0, PTN0_IN ))
1639 }, 1639 },
1640 { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) { 1640 { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2, GROUP(
1641 0, 0, 0, 0, 1641 0, 0, 0, 0,
1642 0, 0, 0, 0, 1642 0, 0, 0, 0,
1643 0, 0, 0, 0, 1643 0, 0, 0, 0,
@@ -1645,9 +1645,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1645 PTQ3_FN, 0, 0, PTQ3_IN, 1645 PTQ3_FN, 0, 0, PTQ3_IN,
1646 PTQ2_FN, 0, 0, PTQ2_IN, 1646 PTQ2_FN, 0, 0, PTQ2_IN,
1647 PTQ1_FN, 0, 0, PTQ1_IN, 1647 PTQ1_FN, 0, 0, PTQ1_IN,
1648 PTQ0_FN, 0, 0, PTQ0_IN } 1648 PTQ0_FN, 0, 0, PTQ0_IN ))
1649 }, 1649 },
1650 { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) { 1650 { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2, GROUP(
1651 PTR7_FN, PTR7_OUT, 0, PTR7_IN, 1651 PTR7_FN, PTR7_OUT, 0, PTR7_IN,
1652 PTR6_FN, PTR6_OUT, 0, PTR6_IN, 1652 PTR6_FN, PTR6_OUT, 0, PTR6_IN,
1653 PTR5_FN, PTR5_OUT, 0, PTR5_IN, 1653 PTR5_FN, PTR5_OUT, 0, PTR5_IN,
@@ -1655,9 +1655,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1655 PTR3_FN, 0, 0, PTR3_IN, 1655 PTR3_FN, 0, 0, PTR3_IN,
1656 PTR2_FN, 0, 0, PTR2_IN, 1656 PTR2_FN, 0, 0, PTR2_IN,
1657 PTR1_FN, PTR1_OUT, 0, PTR1_IN, 1657 PTR1_FN, PTR1_OUT, 0, PTR1_IN,
1658 PTR0_FN, PTR0_OUT, 0, PTR0_IN } 1658 PTR0_FN, PTR0_OUT, 0, PTR0_IN ))
1659 }, 1659 },
1660 { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) { 1660 { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2, GROUP(
1661 PTS7_FN, PTS7_OUT, 0, PTS7_IN, 1661 PTS7_FN, PTS7_OUT, 0, PTS7_IN,
1662 PTS6_FN, PTS6_OUT, 0, PTS6_IN, 1662 PTS6_FN, PTS6_OUT, 0, PTS6_IN,
1663 PTS5_FN, PTS5_OUT, 0, PTS5_IN, 1663 PTS5_FN, PTS5_OUT, 0, PTS5_IN,
@@ -1665,9 +1665,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1665 PTS3_FN, PTS3_OUT, 0, PTS3_IN, 1665 PTS3_FN, PTS3_OUT, 0, PTS3_IN,
1666 PTS2_FN, PTS2_OUT, 0, PTS2_IN, 1666 PTS2_FN, PTS2_OUT, 0, PTS2_IN,
1667 PTS1_FN, PTS1_OUT, 0, PTS1_IN, 1667 PTS1_FN, PTS1_OUT, 0, PTS1_IN,
1668 PTS0_FN, PTS0_OUT, 0, PTS0_IN } 1668 PTS0_FN, PTS0_OUT, 0, PTS0_IN ))
1669 }, 1669 },
1670 { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) { 1670 { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2, GROUP(
1671 0, 0, 0, 0, 1671 0, 0, 0, 0,
1672 0, 0, 0, 0, 1672 0, 0, 0, 0,
1673 PTT5_FN, PTT5_OUT, 0, PTT5_IN, 1673 PTT5_FN, PTT5_OUT, 0, PTT5_IN,
@@ -1675,9 +1675,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1675 PTT3_FN, PTT3_OUT, 0, PTT3_IN, 1675 PTT3_FN, PTT3_OUT, 0, PTT3_IN,
1676 PTT2_FN, PTT2_OUT, 0, PTT2_IN, 1676 PTT2_FN, PTT2_OUT, 0, PTT2_IN,
1677 PTT1_FN, PTT1_OUT, 0, PTT1_IN, 1677 PTT1_FN, PTT1_OUT, 0, PTT1_IN,
1678 PTT0_FN, PTT0_OUT, 0, PTT0_IN } 1678 PTT0_FN, PTT0_OUT, 0, PTT0_IN ))
1679 }, 1679 },
1680 { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) { 1680 { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2, GROUP(
1681 0, 0, 0, 0, 1681 0, 0, 0, 0,
1682 0, 0, 0, 0, 1682 0, 0, 0, 0,
1683 PTU5_FN, PTU5_OUT, 0, PTU5_IN, 1683 PTU5_FN, PTU5_OUT, 0, PTU5_IN,
@@ -1685,9 +1685,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1685 PTU3_FN, PTU3_OUT, 0, PTU3_IN, 1685 PTU3_FN, PTU3_OUT, 0, PTU3_IN,
1686 PTU2_FN, PTU2_OUT, 0, PTU2_IN, 1686 PTU2_FN, PTU2_OUT, 0, PTU2_IN,
1687 PTU1_FN, PTU1_OUT, 0, PTU1_IN, 1687 PTU1_FN, PTU1_OUT, 0, PTU1_IN,
1688 PTU0_FN, PTU0_OUT, 0, PTU0_IN } 1688 PTU0_FN, PTU0_OUT, 0, PTU0_IN ))
1689 }, 1689 },
1690 { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) { 1690 { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2, GROUP(
1691 PTV7_FN, PTV7_OUT, 0, PTV7_IN, 1691 PTV7_FN, PTV7_OUT, 0, PTV7_IN,
1692 PTV6_FN, PTV6_OUT, 0, PTV6_IN, 1692 PTV6_FN, PTV6_OUT, 0, PTV6_IN,
1693 PTV5_FN, PTV5_OUT, 0, PTV5_IN, 1693 PTV5_FN, PTV5_OUT, 0, PTV5_IN,
@@ -1695,9 +1695,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1695 PTV3_FN, PTV3_OUT, 0, PTV3_IN, 1695 PTV3_FN, PTV3_OUT, 0, PTV3_IN,
1696 PTV2_FN, PTV2_OUT, 0, PTV2_IN, 1696 PTV2_FN, PTV2_OUT, 0, PTV2_IN,
1697 PTV1_FN, PTV1_OUT, 0, PTV1_IN, 1697 PTV1_FN, PTV1_OUT, 0, PTV1_IN,
1698 PTV0_FN, PTV0_OUT, 0, PTV0_IN } 1698 PTV0_FN, PTV0_OUT, 0, PTV0_IN ))
1699 }, 1699 },
1700 { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) { 1700 { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2, GROUP(
1701 PTW7_FN, PTW7_OUT, 0, PTW7_IN, 1701 PTW7_FN, PTW7_OUT, 0, PTW7_IN,
1702 PTW6_FN, PTW6_OUT, 0, PTW6_IN, 1702 PTW6_FN, PTW6_OUT, 0, PTW6_IN,
1703 PTW5_FN, PTW5_OUT, 0, PTW5_IN, 1703 PTW5_FN, PTW5_OUT, 0, PTW5_IN,
@@ -1705,9 +1705,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1705 PTW3_FN, PTW3_OUT, 0, PTW3_IN, 1705 PTW3_FN, PTW3_OUT, 0, PTW3_IN,
1706 PTW2_FN, PTW2_OUT, 0, PTW2_IN, 1706 PTW2_FN, PTW2_OUT, 0, PTW2_IN,
1707 PTW1_FN, PTW1_OUT, 0, PTW1_IN, 1707 PTW1_FN, PTW1_OUT, 0, PTW1_IN,
1708 PTW0_FN, PTW0_OUT, 0, PTW0_IN } 1708 PTW0_FN, PTW0_OUT, 0, PTW0_IN ))
1709 }, 1709 },
1710 { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) { 1710 { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2, GROUP(
1711 PTX7_FN, PTX7_OUT, 0, PTX7_IN, 1711 PTX7_FN, PTX7_OUT, 0, PTX7_IN,
1712 PTX6_FN, PTX6_OUT, 0, PTX6_IN, 1712 PTX6_FN, PTX6_OUT, 0, PTX6_IN,
1713 PTX5_FN, PTX5_OUT, 0, PTX5_IN, 1713 PTX5_FN, PTX5_OUT, 0, PTX5_IN,
@@ -1715,9 +1715,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1715 PTX3_FN, PTX3_OUT, 0, PTX3_IN, 1715 PTX3_FN, PTX3_OUT, 0, PTX3_IN,
1716 PTX2_FN, PTX2_OUT, 0, PTX2_IN, 1716 PTX2_FN, PTX2_OUT, 0, PTX2_IN,
1717 PTX1_FN, PTX1_OUT, 0, PTX1_IN, 1717 PTX1_FN, PTX1_OUT, 0, PTX1_IN,
1718 PTX0_FN, PTX0_OUT, 0, PTX0_IN } 1718 PTX0_FN, PTX0_OUT, 0, PTX0_IN ))
1719 }, 1719 },
1720 { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) { 1720 { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2, GROUP(
1721 PTY7_FN, PTY7_OUT, 0, PTY7_IN, 1721 PTY7_FN, PTY7_OUT, 0, PTY7_IN,
1722 PTY6_FN, PTY6_OUT, 0, PTY6_IN, 1722 PTY6_FN, PTY6_OUT, 0, PTY6_IN,
1723 PTY5_FN, PTY5_OUT, 0, PTY5_IN, 1723 PTY5_FN, PTY5_OUT, 0, PTY5_IN,
@@ -1725,9 +1725,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1725 PTY3_FN, PTY3_OUT, 0, PTY3_IN, 1725 PTY3_FN, PTY3_OUT, 0, PTY3_IN,
1726 PTY2_FN, PTY2_OUT, 0, PTY2_IN, 1726 PTY2_FN, PTY2_OUT, 0, PTY2_IN,
1727 PTY1_FN, PTY1_OUT, 0, PTY1_IN, 1727 PTY1_FN, PTY1_OUT, 0, PTY1_IN,
1728 PTY0_FN, PTY0_OUT, 0, PTY0_IN } 1728 PTY0_FN, PTY0_OUT, 0, PTY0_IN ))
1729 }, 1729 },
1730 { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) { 1730 { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2, GROUP(
1731 PTZ7_FN, PTZ7_OUT, 0, PTZ7_IN, 1731 PTZ7_FN, PTZ7_OUT, 0, PTZ7_IN,
1732 PTZ6_FN, PTZ6_OUT, 0, PTZ6_IN, 1732 PTZ6_FN, PTZ6_OUT, 0, PTZ6_IN,
1733 PTZ5_FN, PTZ5_OUT, 0, PTZ5_IN, 1733 PTZ5_FN, PTZ5_OUT, 0, PTZ5_IN,
@@ -1735,9 +1735,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1735 PTZ3_FN, PTZ3_OUT, 0, PTZ3_IN, 1735 PTZ3_FN, PTZ3_OUT, 0, PTZ3_IN,
1736 PTZ2_FN, PTZ2_OUT, 0, PTZ2_IN, 1736 PTZ2_FN, PTZ2_OUT, 0, PTZ2_IN,
1737 PTZ1_FN, PTZ1_OUT, 0, PTZ1_IN, 1737 PTZ1_FN, PTZ1_OUT, 0, PTZ1_IN,
1738 PTZ0_FN, PTZ0_OUT, 0, PTZ0_IN } 1738 PTZ0_FN, PTZ0_OUT, 0, PTZ0_IN ))
1739 }, 1739 },
1740 { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 2) { 1740 { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 2, GROUP(
1741 PSA15_PSA14_FN1, PSA15_PSA14_FN2, 0, 0, 1741 PSA15_PSA14_FN1, PSA15_PSA14_FN2, 0, 0,
1742 PSA13_PSA12_FN1, PSA13_PSA12_FN2, 0, 0, 1742 PSA13_PSA12_FN1, PSA13_PSA12_FN2, 0, 0,
1743 PSA11_PSA10_FN1, PSA11_PSA10_FN2, 0, 0, 1743 PSA11_PSA10_FN1, PSA11_PSA10_FN2, 0, 0,
@@ -1745,9 +1745,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1745 0, 0, 0, 0, 1745 0, 0, 0, 0,
1746 PSA5_PSA4_FN1, PSA5_PSA4_FN2, PSA5_PSA4_FN3, 0, 1746 PSA5_PSA4_FN1, PSA5_PSA4_FN2, PSA5_PSA4_FN3, 0,
1747 PSA3_PSA2_FN1, PSA3_PSA2_FN2, 0, 0, 1747 PSA3_PSA2_FN1, PSA3_PSA2_FN2, 0, 0,
1748 0, 0, 0, 0 } 1748 0, 0, 0, 0 ))
1749 }, 1749 },
1750 { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 2) { 1750 { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 2, GROUP(
1751 PSB15_PSB14_FN1, PSB15_PSB14_FN2, 0, 0, 1751 PSB15_PSB14_FN1, PSB15_PSB14_FN2, 0, 0,
1752 PSB13_PSB12_LCDC_RGB, PSB13_PSB12_LCDC_SYS, 0, 0, 1752 PSB13_PSB12_LCDC_RGB, PSB13_PSB12_LCDC_SYS, 0, 0,
1753 0, 0, 0, 0, 1753 0, 0, 0, 0,
@@ -1755,9 +1755,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1755 PSB7_PSB6_FN1, PSB7_PSB6_FN2, 0, 0, 1755 PSB7_PSB6_FN1, PSB7_PSB6_FN2, 0, 0,
1756 PSB5_PSB4_FN1, PSB5_PSB4_FN2, 0, 0, 1756 PSB5_PSB4_FN1, PSB5_PSB4_FN2, 0, 0,
1757 PSB3_PSB2_FN1, PSB3_PSB2_FN2, 0, 0, 1757 PSB3_PSB2_FN1, PSB3_PSB2_FN2, 0, 0,
1758 0, 0, 0, 0 } 1758 0, 0, 0, 0 ))
1759 }, 1759 },
1760 { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 2) { 1760 { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 2, GROUP(
1761 PSC15_PSC14_FN1, PSC15_PSC14_FN2, 0, 0, 1761 PSC15_PSC14_FN1, PSC15_PSC14_FN2, 0, 0,
1762 PSC13_PSC12_FN1, PSC13_PSC12_FN2, 0, 0, 1762 PSC13_PSC12_FN1, PSC13_PSC12_FN2, 0, 0,
1763 PSC11_PSC10_FN1, PSC11_PSC10_FN2, PSC11_PSC10_FN3, 0, 1763 PSC11_PSC10_FN1, PSC11_PSC10_FN2, PSC11_PSC10_FN3, 0,
@@ -1765,9 +1765,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1765 PSC7_PSC6_FN1, PSC7_PSC6_FN2, PSC7_PSC6_FN3, 0, 1765 PSC7_PSC6_FN1, PSC7_PSC6_FN2, PSC7_PSC6_FN3, 0,
1766 0, 0, 0, 0, 1766 0, 0, 0, 0,
1767 0, 0, 0, 0, 1767 0, 0, 0, 0,
1768 0, 0, 0, 0 } 1768 0, 0, 0, 0 ))
1769 }, 1769 },
1770 { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 2) { 1770 { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 2, GROUP(
1771 PSD15_PSD14_FN1, PSD15_PSD14_FN2, 0, 0, 1771 PSD15_PSD14_FN1, PSD15_PSD14_FN2, 0, 0,
1772 PSD13_PSD12_FN1, PSD13_PSD12_FN2, 0, 0, 1772 PSD13_PSD12_FN1, PSD13_PSD12_FN2, 0, 0,
1773 PSD11_PSD10_FN1, PSD11_PSD10_FN2, PSD11_PSD10_FN3, 0, 1773 PSD11_PSD10_FN1, PSD11_PSD10_FN2, PSD11_PSD10_FN3, 0,
@@ -1775,103 +1775,103 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1775 PSD7_PSD6_FN1, PSD7_PSD6_FN2, 0, 0, 1775 PSD7_PSD6_FN1, PSD7_PSD6_FN2, 0, 0,
1776 PSD5_PSD4_FN1, PSD5_PSD4_FN2, 0, 0, 1776 PSD5_PSD4_FN1, PSD5_PSD4_FN2, 0, 0,
1777 PSD3_PSD2_FN1, PSD3_PSD2_FN2, 0, 0, 1777 PSD3_PSD2_FN1, PSD3_PSD2_FN2, 0, 0,
1778 PSD1_PSD0_FN1, PSD1_PSD0_FN2, 0, 0 } 1778 PSD1_PSD0_FN1, PSD1_PSD0_FN2, 0, 0 ))
1779 }, 1779 },
1780 {} 1780 {}
1781}; 1781};
1782 1782
1783static const struct pinmux_data_reg pinmux_data_regs[] = { 1783static const struct pinmux_data_reg pinmux_data_regs[] = {
1784 { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { 1784 { PINMUX_DATA_REG("PADR", 0xa4050120, 8, GROUP(
1785 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, 1785 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
1786 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } 1786 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA ))
1787 }, 1787 },
1788 { PINMUX_DATA_REG("PBDR", 0xa4050122, 8) { 1788 { PINMUX_DATA_REG("PBDR", 0xa4050122, 8, GROUP(
1789 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, 1789 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
1790 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA } 1790 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA ))
1791 }, 1791 },
1792 { PINMUX_DATA_REG("PCDR", 0xa4050124, 8) { 1792 { PINMUX_DATA_REG("PCDR", 0xa4050124, 8, GROUP(
1793 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA, 1793 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
1794 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA } 1794 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA ))
1795 }, 1795 },
1796 { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) { 1796 { PINMUX_DATA_REG("PDDR", 0xa4050126, 8, GROUP(
1797 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, 1797 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
1798 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA } 1798 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA ))
1799 }, 1799 },
1800 { PINMUX_DATA_REG("PEDR", 0xa4050128, 8) { 1800 { PINMUX_DATA_REG("PEDR", 0xa4050128, 8, GROUP(
1801 0, 0, PTE5_DATA, PTE4_DATA, 1801 0, 0, PTE5_DATA, PTE4_DATA,
1802 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA } 1802 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA ))
1803 }, 1803 },
1804 { PINMUX_DATA_REG("PFDR", 0xa405012a, 8) { 1804 { PINMUX_DATA_REG("PFDR", 0xa405012a, 8, GROUP(
1805 PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA, 1805 PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
1806 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA } 1806 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA ))
1807 }, 1807 },
1808 { PINMUX_DATA_REG("PGDR", 0xa405012c, 8) { 1808 { PINMUX_DATA_REG("PGDR", 0xa405012c, 8, GROUP(
1809 0, 0, PTG5_DATA, PTG4_DATA, 1809 0, 0, PTG5_DATA, PTG4_DATA,
1810 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA } 1810 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA ))
1811 }, 1811 },
1812 { PINMUX_DATA_REG("PHDR", 0xa405012e, 8) { 1812 { PINMUX_DATA_REG("PHDR", 0xa405012e, 8, GROUP(
1813 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA, 1813 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
1814 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA } 1814 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA ))
1815 }, 1815 },
1816 { PINMUX_DATA_REG("PJDR", 0xa4050130, 8) { 1816 { PINMUX_DATA_REG("PJDR", 0xa4050130, 8, GROUP(
1817 PTJ7_DATA, 0, PTJ5_DATA, 0, 1817 PTJ7_DATA, 0, PTJ5_DATA, 0,
1818 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA } 1818 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA ))
1819 }, 1819 },
1820 { PINMUX_DATA_REG("PKDR", 0xa4050132, 8) { 1820 { PINMUX_DATA_REG("PKDR", 0xa4050132, 8, GROUP(
1821 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA, 1821 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
1822 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA } 1822 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA ))
1823 }, 1823 },
1824 { PINMUX_DATA_REG("PLDR", 0xa4050134, 8) { 1824 { PINMUX_DATA_REG("PLDR", 0xa4050134, 8, GROUP(
1825 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, 1825 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
1826 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA } 1826 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA ))
1827 }, 1827 },
1828 { PINMUX_DATA_REG("PMDR", 0xa4050136, 8) { 1828 { PINMUX_DATA_REG("PMDR", 0xa4050136, 8, GROUP(
1829 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, 1829 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
1830 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA } 1830 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA ))
1831 }, 1831 },
1832 { PINMUX_DATA_REG("PNDR", 0xa4050138, 8) { 1832 { PINMUX_DATA_REG("PNDR", 0xa4050138, 8, GROUP(
1833 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, 1833 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
1834 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA } 1834 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA ))
1835 }, 1835 },
1836 { PINMUX_DATA_REG("PQDR", 0xa405013a, 8) { 1836 { PINMUX_DATA_REG("PQDR", 0xa405013a, 8, GROUP(
1837 0, 0, 0, 0, 1837 0, 0, 0, 0,
1838 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA } 1838 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA ))
1839 }, 1839 },
1840 { PINMUX_DATA_REG("PRDR", 0xa405013c, 8) { 1840 { PINMUX_DATA_REG("PRDR", 0xa405013c, 8, GROUP(
1841 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA, 1841 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
1842 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA } 1842 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA ))
1843 }, 1843 },
1844 { PINMUX_DATA_REG("PSDR", 0xa405013e, 8) { 1844 { PINMUX_DATA_REG("PSDR", 0xa405013e, 8, GROUP(
1845 PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA, 1845 PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
1846 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA } 1846 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA ))
1847 }, 1847 },
1848 { PINMUX_DATA_REG("PTDR", 0xa4050160, 8) { 1848 { PINMUX_DATA_REG("PTDR", 0xa4050160, 8, GROUP(
1849 0, 0, PTT5_DATA, PTT4_DATA, 1849 0, 0, PTT5_DATA, PTT4_DATA,
1850 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA } 1850 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA ))
1851 }, 1851 },
1852 { PINMUX_DATA_REG("PUDR", 0xa4050162, 8) { 1852 { PINMUX_DATA_REG("PUDR", 0xa4050162, 8, GROUP(
1853 0, 0, PTU5_DATA, PTU4_DATA, 1853 0, 0, PTU5_DATA, PTU4_DATA,
1854 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA } 1854 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA ))
1855 }, 1855 },
1856 { PINMUX_DATA_REG("PVDR", 0xa4050164, 8) { 1856 { PINMUX_DATA_REG("PVDR", 0xa4050164, 8, GROUP(
1857 PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA, 1857 PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
1858 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA } 1858 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
1859 }, 1859 },
1860 { PINMUX_DATA_REG("PWDR", 0xa4050166, 8) { 1860 { PINMUX_DATA_REG("PWDR", 0xa4050166, 8, GROUP(
1861 PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA, 1861 PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
1862 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA } 1862 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA ))
1863 }, 1863 },
1864 { PINMUX_DATA_REG("PXDR", 0xa4050168, 8) { 1864 { PINMUX_DATA_REG("PXDR", 0xa4050168, 8, GROUP(
1865 PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA, 1865 PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
1866 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA } 1866 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA ))
1867 }, 1867 },
1868 { PINMUX_DATA_REG("PYDR", 0xa405016a, 8) { 1868 { PINMUX_DATA_REG("PYDR", 0xa405016a, 8, GROUP(
1869 PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA, 1869 PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
1870 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA } 1870 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA ))
1871 }, 1871 },
1872 { PINMUX_DATA_REG("PZDR", 0xa405016c, 8) { 1872 { PINMUX_DATA_REG("PZDR", 0xa405016c, 8, GROUP(
1873 PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA, 1873 PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
1874 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA } 1874 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
1875 }, 1875 },
1876 { }, 1876 { },
1877}; 1877};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
index 2cc4aa7df613..7a18afecda2c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
@@ -1739,7 +1739,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
1739}; 1739};
1740 1740
1741static const struct pinmux_cfg_reg pinmux_config_regs[] = { 1741static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1742 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { 1742 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2, GROUP(
1743 PTA7_FN, PTA7_OUT, 0, PTA7_IN, 1743 PTA7_FN, PTA7_OUT, 0, PTA7_IN,
1744 PTA6_FN, PTA6_OUT, 0, PTA6_IN, 1744 PTA6_FN, PTA6_OUT, 0, PTA6_IN,
1745 PTA5_FN, PTA5_OUT, 0, PTA5_IN, 1745 PTA5_FN, PTA5_OUT, 0, PTA5_IN,
@@ -1747,9 +1747,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1747 PTA3_FN, PTA3_OUT, 0, PTA3_IN, 1747 PTA3_FN, PTA3_OUT, 0, PTA3_IN,
1748 PTA2_FN, PTA2_OUT, 0, PTA2_IN, 1748 PTA2_FN, PTA2_OUT, 0, PTA2_IN,
1749 PTA1_FN, PTA1_OUT, 0, PTA1_IN, 1749 PTA1_FN, PTA1_OUT, 0, PTA1_IN,
1750 PTA0_FN, PTA0_OUT, 0, PTA0_IN } 1750 PTA0_FN, PTA0_OUT, 0, PTA0_IN ))
1751 }, 1751 },
1752 { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) { 1752 { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2, GROUP(
1753 PTB7_FN, PTB7_OUT, 0, PTB7_IN, 1753 PTB7_FN, PTB7_OUT, 0, PTB7_IN,
1754 PTB6_FN, PTB6_OUT, 0, PTB6_IN, 1754 PTB6_FN, PTB6_OUT, 0, PTB6_IN,
1755 PTB5_FN, PTB5_OUT, 0, PTB5_IN, 1755 PTB5_FN, PTB5_OUT, 0, PTB5_IN,
@@ -1757,9 +1757,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1757 PTB3_FN, PTB3_OUT, 0, PTB3_IN, 1757 PTB3_FN, PTB3_OUT, 0, PTB3_IN,
1758 PTB2_FN, PTB2_OUT, 0, PTB2_IN, 1758 PTB2_FN, PTB2_OUT, 0, PTB2_IN,
1759 PTB1_FN, PTB1_OUT, 0, PTB1_IN, 1759 PTB1_FN, PTB1_OUT, 0, PTB1_IN,
1760 PTB0_FN, PTB0_OUT, 0, PTB0_IN } 1760 PTB0_FN, PTB0_OUT, 0, PTB0_IN ))
1761 }, 1761 },
1762 { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) { 1762 { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2, GROUP(
1763 PTC7_FN, PTC7_OUT, 0, PTC7_IN, 1763 PTC7_FN, PTC7_OUT, 0, PTC7_IN,
1764 PTC6_FN, PTC6_OUT, 0, PTC6_IN, 1764 PTC6_FN, PTC6_OUT, 0, PTC6_IN,
1765 PTC5_FN, PTC5_OUT, 0, PTC5_IN, 1765 PTC5_FN, PTC5_OUT, 0, PTC5_IN,
@@ -1767,9 +1767,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1767 PTC3_FN, PTC3_OUT, 0, PTC3_IN, 1767 PTC3_FN, PTC3_OUT, 0, PTC3_IN,
1768 PTC2_FN, PTC2_OUT, 0, PTC2_IN, 1768 PTC2_FN, PTC2_OUT, 0, PTC2_IN,
1769 PTC1_FN, PTC1_OUT, 0, PTC1_IN, 1769 PTC1_FN, PTC1_OUT, 0, PTC1_IN,
1770 PTC0_FN, PTC0_OUT, 0, PTC0_IN } 1770 PTC0_FN, PTC0_OUT, 0, PTC0_IN ))
1771 }, 1771 },
1772 { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) { 1772 { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2, GROUP(
1773 PTD7_FN, PTD7_OUT, 0, PTD7_IN, 1773 PTD7_FN, PTD7_OUT, 0, PTD7_IN,
1774 PTD6_FN, PTD6_OUT, 0, PTD6_IN, 1774 PTD6_FN, PTD6_OUT, 0, PTD6_IN,
1775 PTD5_FN, PTD5_OUT, 0, PTD5_IN, 1775 PTD5_FN, PTD5_OUT, 0, PTD5_IN,
@@ -1777,9 +1777,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1777 PTD3_FN, PTD3_OUT, 0, PTD3_IN, 1777 PTD3_FN, PTD3_OUT, 0, PTD3_IN,
1778 PTD2_FN, PTD2_OUT, 0, PTD2_IN, 1778 PTD2_FN, PTD2_OUT, 0, PTD2_IN,
1779 PTD1_FN, PTD1_OUT, 0, PTD1_IN, 1779 PTD1_FN, PTD1_OUT, 0, PTD1_IN,
1780 PTD0_FN, PTD0_OUT, 0, PTD0_IN } 1780 PTD0_FN, PTD0_OUT, 0, PTD0_IN ))
1781 }, 1781 },
1782 { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) { 1782 { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2, GROUP(
1783 PTE7_FN, PTE7_OUT, 0, PTE7_IN, 1783 PTE7_FN, PTE7_OUT, 0, PTE7_IN,
1784 PTE6_FN, PTE6_OUT, 0, PTE6_IN, 1784 PTE6_FN, PTE6_OUT, 0, PTE6_IN,
1785 PTE5_FN, PTE5_OUT, 0, PTE5_IN, 1785 PTE5_FN, PTE5_OUT, 0, PTE5_IN,
@@ -1787,9 +1787,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1787 PTE3_FN, PTE3_OUT, 0, PTE3_IN, 1787 PTE3_FN, PTE3_OUT, 0, PTE3_IN,
1788 PTE2_FN, PTE2_OUT, 0, PTE2_IN, 1788 PTE2_FN, PTE2_OUT, 0, PTE2_IN,
1789 PTE1_FN, PTE1_OUT, 0, PTE1_IN, 1789 PTE1_FN, PTE1_OUT, 0, PTE1_IN,
1790 PTE0_FN, PTE0_OUT, 0, PTE0_IN } 1790 PTE0_FN, PTE0_OUT, 0, PTE0_IN ))
1791 }, 1791 },
1792 { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) { 1792 { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2, GROUP(
1793 PTF7_FN, PTF7_OUT, 0, PTF7_IN, 1793 PTF7_FN, PTF7_OUT, 0, PTF7_IN,
1794 PTF6_FN, PTF6_OUT, 0, PTF6_IN, 1794 PTF6_FN, PTF6_OUT, 0, PTF6_IN,
1795 PTF5_FN, PTF5_OUT, 0, PTF5_IN, 1795 PTF5_FN, PTF5_OUT, 0, PTF5_IN,
@@ -1797,9 +1797,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1797 PTF3_FN, PTF3_OUT, 0, PTF3_IN, 1797 PTF3_FN, PTF3_OUT, 0, PTF3_IN,
1798 PTF2_FN, PTF2_OUT, 0, PTF2_IN, 1798 PTF2_FN, PTF2_OUT, 0, PTF2_IN,
1799 PTF1_FN, PTF1_OUT, 0, PTF1_IN, 1799 PTF1_FN, PTF1_OUT, 0, PTF1_IN,
1800 PTF0_FN, PTF0_OUT, 0, PTF0_IN } 1800 PTF0_FN, PTF0_OUT, 0, PTF0_IN ))
1801 }, 1801 },
1802 { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) { 1802 { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2, GROUP(
1803 0, 0, 0, 0, 1803 0, 0, 0, 0,
1804 0, 0, 0, 0, 1804 0, 0, 0, 0,
1805 PTG5_FN, PTG5_OUT, 0, 0, 1805 PTG5_FN, PTG5_OUT, 0, 0,
@@ -1807,9 +1807,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1807 PTG3_FN, PTG3_OUT, 0, 0, 1807 PTG3_FN, PTG3_OUT, 0, 0,
1808 PTG2_FN, PTG2_OUT, 0, 0, 1808 PTG2_FN, PTG2_OUT, 0, 0,
1809 PTG1_FN, PTG1_OUT, 0, 0, 1809 PTG1_FN, PTG1_OUT, 0, 0,
1810 PTG0_FN, PTG0_OUT, 0, 0 } 1810 PTG0_FN, PTG0_OUT, 0, 0 ))
1811 }, 1811 },
1812 { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) { 1812 { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2, GROUP(
1813 PTH7_FN, PTH7_OUT, 0, PTH7_IN, 1813 PTH7_FN, PTH7_OUT, 0, PTH7_IN,
1814 PTH6_FN, PTH6_OUT, 0, PTH6_IN, 1814 PTH6_FN, PTH6_OUT, 0, PTH6_IN,
1815 PTH5_FN, PTH5_OUT, 0, PTH5_IN, 1815 PTH5_FN, PTH5_OUT, 0, PTH5_IN,
@@ -1817,9 +1817,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1817 PTH3_FN, PTH3_OUT, 0, PTH3_IN, 1817 PTH3_FN, PTH3_OUT, 0, PTH3_IN,
1818 PTH2_FN, PTH2_OUT, 0, PTH2_IN, 1818 PTH2_FN, PTH2_OUT, 0, PTH2_IN,
1819 PTH1_FN, PTH1_OUT, 0, PTH1_IN, 1819 PTH1_FN, PTH1_OUT, 0, PTH1_IN,
1820 PTH0_FN, PTH0_OUT, 0, PTH0_IN } 1820 PTH0_FN, PTH0_OUT, 0, PTH0_IN ))
1821 }, 1821 },
1822 { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) { 1822 { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2, GROUP(
1823 PTJ7_FN, PTJ7_OUT, 0, 0, 1823 PTJ7_FN, PTJ7_OUT, 0, 0,
1824 PTJ6_FN, PTJ6_OUT, 0, 0, 1824 PTJ6_FN, PTJ6_OUT, 0, 0,
1825 PTJ5_FN, PTJ5_OUT, 0, 0, 1825 PTJ5_FN, PTJ5_OUT, 0, 0,
@@ -1827,9 +1827,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1827 PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN, 1827 PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN,
1828 PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN, 1828 PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN,
1829 PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN, 1829 PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN,
1830 PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN } 1830 PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN ))
1831 }, 1831 },
1832 { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) { 1832 { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2, GROUP(
1833 PTK7_FN, PTK7_OUT, 0, PTK7_IN, 1833 PTK7_FN, PTK7_OUT, 0, PTK7_IN,
1834 PTK6_FN, PTK6_OUT, 0, PTK6_IN, 1834 PTK6_FN, PTK6_OUT, 0, PTK6_IN,
1835 PTK5_FN, PTK5_OUT, 0, PTK5_IN, 1835 PTK5_FN, PTK5_OUT, 0, PTK5_IN,
@@ -1837,9 +1837,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1837 PTK3_FN, PTK3_OUT, 0, PTK3_IN, 1837 PTK3_FN, PTK3_OUT, 0, PTK3_IN,
1838 PTK2_FN, PTK2_OUT, 0, PTK2_IN, 1838 PTK2_FN, PTK2_OUT, 0, PTK2_IN,
1839 PTK1_FN, PTK1_OUT, 0, PTK1_IN, 1839 PTK1_FN, PTK1_OUT, 0, PTK1_IN,
1840 PTK0_FN, PTK0_OUT, 0, PTK0_IN } 1840 PTK0_FN, PTK0_OUT, 0, PTK0_IN ))
1841 }, 1841 },
1842 { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) { 1842 { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2, GROUP(
1843 PTL7_FN, PTL7_OUT, 0, PTL7_IN, 1843 PTL7_FN, PTL7_OUT, 0, PTL7_IN,
1844 PTL6_FN, PTL6_OUT, 0, PTL6_IN, 1844 PTL6_FN, PTL6_OUT, 0, PTL6_IN,
1845 PTL5_FN, PTL5_OUT, 0, PTL5_IN, 1845 PTL5_FN, PTL5_OUT, 0, PTL5_IN,
@@ -1847,9 +1847,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1847 PTL3_FN, PTL3_OUT, 0, PTL3_IN, 1847 PTL3_FN, PTL3_OUT, 0, PTL3_IN,
1848 PTL2_FN, PTL2_OUT, 0, PTL2_IN, 1848 PTL2_FN, PTL2_OUT, 0, PTL2_IN,
1849 PTL1_FN, PTL1_OUT, 0, PTL1_IN, 1849 PTL1_FN, PTL1_OUT, 0, PTL1_IN,
1850 PTL0_FN, PTL0_OUT, 0, PTL0_IN } 1850 PTL0_FN, PTL0_OUT, 0, PTL0_IN ))
1851 }, 1851 },
1852 { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) { 1852 { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2, GROUP(
1853 PTM7_FN, PTM7_OUT, 0, PTM7_IN, 1853 PTM7_FN, PTM7_OUT, 0, PTM7_IN,
1854 PTM6_FN, PTM6_OUT, 0, PTM6_IN, 1854 PTM6_FN, PTM6_OUT, 0, PTM6_IN,
1855 PTM5_FN, PTM5_OUT, 0, PTM5_IN, 1855 PTM5_FN, PTM5_OUT, 0, PTM5_IN,
@@ -1857,9 +1857,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1857 PTM3_FN, PTM3_OUT, 0, PTM3_IN, 1857 PTM3_FN, PTM3_OUT, 0, PTM3_IN,
1858 PTM2_FN, PTM2_OUT, 0, PTM2_IN, 1858 PTM2_FN, PTM2_OUT, 0, PTM2_IN,
1859 PTM1_FN, PTM1_OUT, 0, PTM1_IN, 1859 PTM1_FN, PTM1_OUT, 0, PTM1_IN,
1860 PTM0_FN, PTM0_OUT, 0, PTM0_IN } 1860 PTM0_FN, PTM0_OUT, 0, PTM0_IN ))
1861 }, 1861 },
1862 { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) { 1862 { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2, GROUP(
1863 PTN7_FN, PTN7_OUT, 0, PTN7_IN, 1863 PTN7_FN, PTN7_OUT, 0, PTN7_IN,
1864 PTN6_FN, PTN6_OUT, 0, PTN6_IN, 1864 PTN6_FN, PTN6_OUT, 0, PTN6_IN,
1865 PTN5_FN, PTN5_OUT, 0, PTN5_IN, 1865 PTN5_FN, PTN5_OUT, 0, PTN5_IN,
@@ -1867,9 +1867,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1867 PTN3_FN, PTN3_OUT, 0, PTN3_IN, 1867 PTN3_FN, PTN3_OUT, 0, PTN3_IN,
1868 PTN2_FN, PTN2_OUT, 0, PTN2_IN, 1868 PTN2_FN, PTN2_OUT, 0, PTN2_IN,
1869 PTN1_FN, PTN1_OUT, 0, PTN1_IN, 1869 PTN1_FN, PTN1_OUT, 0, PTN1_IN,
1870 PTN0_FN, PTN0_OUT, 0, PTN0_IN } 1870 PTN0_FN, PTN0_OUT, 0, PTN0_IN ))
1871 }, 1871 },
1872 { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) { 1872 { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2, GROUP(
1873 PTQ7_FN, PTQ7_OUT, 0, PTQ7_IN, 1873 PTQ7_FN, PTQ7_OUT, 0, PTQ7_IN,
1874 PTQ6_FN, PTQ6_OUT, 0, PTQ6_IN, 1874 PTQ6_FN, PTQ6_OUT, 0, PTQ6_IN,
1875 PTQ5_FN, PTQ5_OUT, 0, PTQ5_IN, 1875 PTQ5_FN, PTQ5_OUT, 0, PTQ5_IN,
@@ -1877,9 +1877,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1877 PTQ3_FN, PTQ3_OUT, 0, PTQ3_IN, 1877 PTQ3_FN, PTQ3_OUT, 0, PTQ3_IN,
1878 PTQ2_FN, PTQ2_OUT, 0, PTQ2_IN, 1878 PTQ2_FN, PTQ2_OUT, 0, PTQ2_IN,
1879 PTQ1_FN, PTQ1_OUT, 0, PTQ1_IN, 1879 PTQ1_FN, PTQ1_OUT, 0, PTQ1_IN,
1880 PTQ0_FN, PTQ0_OUT, 0, PTQ0_IN } 1880 PTQ0_FN, PTQ0_OUT, 0, PTQ0_IN ))
1881 }, 1881 },
1882 { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) { 1882 { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2, GROUP(
1883 PTR7_FN, PTR7_OUT, 0, PTR7_IN, 1883 PTR7_FN, PTR7_OUT, 0, PTR7_IN,
1884 PTR6_FN, PTR6_OUT, 0, PTR6_IN, 1884 PTR6_FN, PTR6_OUT, 0, PTR6_IN,
1885 PTR5_FN, PTR5_OUT, 0, PTR5_IN, 1885 PTR5_FN, PTR5_OUT, 0, PTR5_IN,
@@ -1887,9 +1887,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1887 PTR3_FN, 0, 0, PTR3_IN, 1887 PTR3_FN, 0, 0, PTR3_IN,
1888 PTR2_FN, 0, 0, PTR2_IN, 1888 PTR2_FN, 0, 0, PTR2_IN,
1889 PTR1_FN, PTR1_OUT, 0, PTR1_IN, 1889 PTR1_FN, PTR1_OUT, 0, PTR1_IN,
1890 PTR0_FN, PTR0_OUT, 0, PTR0_IN } 1890 PTR0_FN, PTR0_OUT, 0, PTR0_IN ))
1891 }, 1891 },
1892 { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) { 1892 { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2, GROUP(
1893 0, 0, 0, 0, 1893 0, 0, 0, 0,
1894 PTS6_FN, PTS6_OUT, 0, PTS6_IN, 1894 PTS6_FN, PTS6_OUT, 0, PTS6_IN,
1895 PTS5_FN, PTS5_OUT, 0, PTS5_IN, 1895 PTS5_FN, PTS5_OUT, 0, PTS5_IN,
@@ -1897,9 +1897,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1897 PTS3_FN, PTS3_OUT, 0, PTS3_IN, 1897 PTS3_FN, PTS3_OUT, 0, PTS3_IN,
1898 PTS2_FN, PTS2_OUT, 0, PTS2_IN, 1898 PTS2_FN, PTS2_OUT, 0, PTS2_IN,
1899 PTS1_FN, PTS1_OUT, 0, PTS1_IN, 1899 PTS1_FN, PTS1_OUT, 0, PTS1_IN,
1900 PTS0_FN, PTS0_OUT, 0, PTS0_IN } 1900 PTS0_FN, PTS0_OUT, 0, PTS0_IN ))
1901 }, 1901 },
1902 { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) { 1902 { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2, GROUP(
1903 PTT7_FN, PTT7_OUT, 0, PTT7_IN, 1903 PTT7_FN, PTT7_OUT, 0, PTT7_IN,
1904 PTT6_FN, PTT6_OUT, 0, PTT6_IN, 1904 PTT6_FN, PTT6_OUT, 0, PTT6_IN,
1905 PTT5_FN, PTT5_OUT, 0, PTT5_IN, 1905 PTT5_FN, PTT5_OUT, 0, PTT5_IN,
@@ -1907,9 +1907,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1907 PTT3_FN, PTT3_OUT, 0, PTT3_IN, 1907 PTT3_FN, PTT3_OUT, 0, PTT3_IN,
1908 PTT2_FN, PTT2_OUT, 0, PTT2_IN, 1908 PTT2_FN, PTT2_OUT, 0, PTT2_IN,
1909 PTT1_FN, PTT1_OUT, 0, PTT1_IN, 1909 PTT1_FN, PTT1_OUT, 0, PTT1_IN,
1910 PTT0_FN, PTT0_OUT, 0, PTT0_IN } 1910 PTT0_FN, PTT0_OUT, 0, PTT0_IN ))
1911 }, 1911 },
1912 { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) { 1912 { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2, GROUP(
1913 PTU7_FN, PTU7_OUT, 0, PTU7_IN, 1913 PTU7_FN, PTU7_OUT, 0, PTU7_IN,
1914 PTU6_FN, PTU6_OUT, 0, PTU6_IN, 1914 PTU6_FN, PTU6_OUT, 0, PTU6_IN,
1915 PTU5_FN, PTU5_OUT, 0, PTU5_IN, 1915 PTU5_FN, PTU5_OUT, 0, PTU5_IN,
@@ -1917,9 +1917,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1917 PTU3_FN, PTU3_OUT, 0, PTU3_IN, 1917 PTU3_FN, PTU3_OUT, 0, PTU3_IN,
1918 PTU2_FN, PTU2_OUT, 0, PTU2_IN, 1918 PTU2_FN, PTU2_OUT, 0, PTU2_IN,
1919 PTU1_FN, PTU1_OUT, 0, PTU1_IN, 1919 PTU1_FN, PTU1_OUT, 0, PTU1_IN,
1920 PTU0_FN, PTU0_OUT, 0, PTU0_IN } 1920 PTU0_FN, PTU0_OUT, 0, PTU0_IN ))
1921 }, 1921 },
1922 { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) { 1922 { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2, GROUP(
1923 PTV7_FN, PTV7_OUT, 0, PTV7_IN, 1923 PTV7_FN, PTV7_OUT, 0, PTV7_IN,
1924 PTV6_FN, PTV6_OUT, 0, PTV6_IN, 1924 PTV6_FN, PTV6_OUT, 0, PTV6_IN,
1925 PTV5_FN, PTV5_OUT, 0, PTV5_IN, 1925 PTV5_FN, PTV5_OUT, 0, PTV5_IN,
@@ -1927,9 +1927,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1927 PTV3_FN, PTV3_OUT, 0, PTV3_IN, 1927 PTV3_FN, PTV3_OUT, 0, PTV3_IN,
1928 PTV2_FN, PTV2_OUT, 0, PTV2_IN, 1928 PTV2_FN, PTV2_OUT, 0, PTV2_IN,
1929 PTV1_FN, PTV1_OUT, 0, PTV1_IN, 1929 PTV1_FN, PTV1_OUT, 0, PTV1_IN,
1930 PTV0_FN, PTV0_OUT, 0, PTV0_IN } 1930 PTV0_FN, PTV0_OUT, 0, PTV0_IN ))
1931 }, 1931 },
1932 { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) { 1932 { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2, GROUP(
1933 PTW7_FN, PTW7_OUT, 0, PTW7_IN, 1933 PTW7_FN, PTW7_OUT, 0, PTW7_IN,
1934 PTW6_FN, PTW6_OUT, 0, PTW6_IN, 1934 PTW6_FN, PTW6_OUT, 0, PTW6_IN,
1935 PTW5_FN, PTW5_OUT, 0, PTW5_IN, 1935 PTW5_FN, PTW5_OUT, 0, PTW5_IN,
@@ -1937,9 +1937,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1937 PTW3_FN, PTW3_OUT, 0, PTW3_IN, 1937 PTW3_FN, PTW3_OUT, 0, PTW3_IN,
1938 PTW2_FN, PTW2_OUT, 0, PTW2_IN, 1938 PTW2_FN, PTW2_OUT, 0, PTW2_IN,
1939 PTW1_FN, PTW1_OUT, 0, PTW1_IN, 1939 PTW1_FN, PTW1_OUT, 0, PTW1_IN,
1940 PTW0_FN, PTW0_OUT, 0, PTW0_IN } 1940 PTW0_FN, PTW0_OUT, 0, PTW0_IN ))
1941 }, 1941 },
1942 { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) { 1942 { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2, GROUP(
1943 PTX7_FN, PTX7_OUT, 0, PTX7_IN, 1943 PTX7_FN, PTX7_OUT, 0, PTX7_IN,
1944 PTX6_FN, PTX6_OUT, 0, PTX6_IN, 1944 PTX6_FN, PTX6_OUT, 0, PTX6_IN,
1945 PTX5_FN, PTX5_OUT, 0, PTX5_IN, 1945 PTX5_FN, PTX5_OUT, 0, PTX5_IN,
@@ -1947,9 +1947,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1947 PTX3_FN, PTX3_OUT, 0, PTX3_IN, 1947 PTX3_FN, PTX3_OUT, 0, PTX3_IN,
1948 PTX2_FN, PTX2_OUT, 0, PTX2_IN, 1948 PTX2_FN, PTX2_OUT, 0, PTX2_IN,
1949 PTX1_FN, PTX1_OUT, 0, PTX1_IN, 1949 PTX1_FN, PTX1_OUT, 0, PTX1_IN,
1950 PTX0_FN, PTX0_OUT, 0, PTX0_IN } 1950 PTX0_FN, PTX0_OUT, 0, PTX0_IN ))
1951 }, 1951 },
1952 { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) { 1952 { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2, GROUP(
1953 PTY7_FN, PTY7_OUT, 0, PTY7_IN, 1953 PTY7_FN, PTY7_OUT, 0, PTY7_IN,
1954 PTY6_FN, PTY6_OUT, 0, PTY6_IN, 1954 PTY6_FN, PTY6_OUT, 0, PTY6_IN,
1955 PTY5_FN, PTY5_OUT, 0, PTY5_IN, 1955 PTY5_FN, PTY5_OUT, 0, PTY5_IN,
@@ -1957,9 +1957,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1957 PTY3_FN, PTY3_OUT, 0, PTY3_IN, 1957 PTY3_FN, PTY3_OUT, 0, PTY3_IN,
1958 PTY2_FN, PTY2_OUT, 0, PTY2_IN, 1958 PTY2_FN, PTY2_OUT, 0, PTY2_IN,
1959 PTY1_FN, PTY1_OUT, 0, PTY1_IN, 1959 PTY1_FN, PTY1_OUT, 0, PTY1_IN,
1960 PTY0_FN, PTY0_OUT, 0, PTY0_IN } 1960 PTY0_FN, PTY0_OUT, 0, PTY0_IN ))
1961 }, 1961 },
1962 { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) { 1962 { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2, GROUP(
1963 PTZ7_FN, PTZ7_OUT, 0, PTZ7_IN, 1963 PTZ7_FN, PTZ7_OUT, 0, PTZ7_IN,
1964 PTZ6_FN, PTZ6_OUT, 0, PTZ6_IN, 1964 PTZ6_FN, PTZ6_OUT, 0, PTZ6_IN,
1965 PTZ5_FN, PTZ5_OUT, 0, PTZ5_IN, 1965 PTZ5_FN, PTZ5_OUT, 0, PTZ5_IN,
@@ -1967,9 +1967,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1967 PTZ3_FN, PTZ3_OUT, 0, PTZ3_IN, 1967 PTZ3_FN, PTZ3_OUT, 0, PTZ3_IN,
1968 PTZ2_FN, PTZ2_OUT, 0, PTZ2_IN, 1968 PTZ2_FN, PTZ2_OUT, 0, PTZ2_IN,
1969 PTZ1_FN, PTZ1_OUT, 0, PTZ1_IN, 1969 PTZ1_FN, PTZ1_OUT, 0, PTZ1_IN,
1970 PTZ0_FN, PTZ0_OUT, 0, PTZ0_IN } 1970 PTZ0_FN, PTZ0_OUT, 0, PTZ0_IN ))
1971 }, 1971 },
1972 { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) { 1972 { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1, GROUP(
1973 PSA15_0, PSA15_1, 1973 PSA15_0, PSA15_1,
1974 PSA14_0, PSA14_1, 1974 PSA14_0, PSA14_1,
1975 PSA13_0, PSA13_1, 1975 PSA13_0, PSA13_1,
@@ -1985,9 +1985,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1985 PSA3_0, PSA3_1, 1985 PSA3_0, PSA3_1,
1986 PSA2_0, PSA2_1, 1986 PSA2_0, PSA2_1,
1987 PSA1_0, PSA1_1, 1987 PSA1_0, PSA1_1,
1988 PSA0_0, PSA0_1} 1988 PSA0_0, PSA0_1))
1989 }, 1989 },
1990 { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1) { 1990 { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1, GROUP(
1991 0, 0, 1991 0, 0,
1992 PSB14_0, PSB14_1, 1992 PSB14_0, PSB14_1,
1993 PSB13_0, PSB13_1, 1993 PSB13_0, PSB13_1,
@@ -2003,9 +2003,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2003 PSB3_0, PSB3_1, 2003 PSB3_0, PSB3_1,
2004 PSB2_0, PSB2_1, 2004 PSB2_0, PSB2_1,
2005 PSB1_0, PSB1_1, 2005 PSB1_0, PSB1_1,
2006 PSB0_0, PSB0_1} 2006 PSB0_0, PSB0_1))
2007 }, 2007 },
2008 { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1) { 2008 { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1, GROUP(
2009 PSC15_0, PSC15_1, 2009 PSC15_0, PSC15_1,
2010 PSC14_0, PSC14_1, 2010 PSC14_0, PSC14_1,
2011 PSC13_0, PSC13_1, 2011 PSC13_0, PSC13_1,
@@ -2021,9 +2021,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2021 0, 0, 2021 0, 0,
2022 PSC2_0, PSC2_1, 2022 PSC2_0, PSC2_1,
2023 PSC1_0, PSC1_1, 2023 PSC1_0, PSC1_1,
2024 PSC0_0, PSC0_1} 2024 PSC0_0, PSC0_1))
2025 }, 2025 },
2026 { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1) { 2026 { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1, GROUP(
2027 PSD15_0, PSD15_1, 2027 PSD15_0, PSD15_1,
2028 PSD14_0, PSD14_1, 2028 PSD14_0, PSD14_1,
2029 PSD13_0, PSD13_1, 2029 PSD13_0, PSD13_1,
@@ -2039,9 +2039,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2039 PSD3_0, PSD3_1, 2039 PSD3_0, PSD3_1,
2040 PSD2_0, PSD2_1, 2040 PSD2_0, PSD2_1,
2041 PSD1_0, PSD1_1, 2041 PSD1_0, PSD1_1,
2042 PSD0_0, PSD0_1} 2042 PSD0_0, PSD0_1))
2043 }, 2043 },
2044 { PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1) { 2044 { PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1, GROUP(
2045 PSE15_0, PSE15_1, 2045 PSE15_0, PSE15_1,
2046 PSE14_0, PSE14_1, 2046 PSE14_0, PSE14_1,
2047 PSE13_0, PSE13_1, 2047 PSE13_0, PSE13_1,
@@ -2057,103 +2057,103 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2057 PSE3_0, PSE3_1, 2057 PSE3_0, PSE3_1,
2058 PSE2_0, PSE2_1, 2058 PSE2_0, PSE2_1,
2059 PSE1_0, PSE1_1, 2059 PSE1_0, PSE1_1,
2060 PSE0_0, PSE0_1} 2060 PSE0_0, PSE0_1))
2061 }, 2061 },
2062 {} 2062 {}
2063}; 2063};
2064 2064
2065static const struct pinmux_data_reg pinmux_data_regs[] = { 2065static const struct pinmux_data_reg pinmux_data_regs[] = {
2066 { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { 2066 { PINMUX_DATA_REG("PADR", 0xa4050120, 8, GROUP(
2067 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, 2067 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
2068 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } 2068 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA ))
2069 }, 2069 },
2070 { PINMUX_DATA_REG("PBDR", 0xa4050122, 8) { 2070 { PINMUX_DATA_REG("PBDR", 0xa4050122, 8, GROUP(
2071 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, 2071 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
2072 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA } 2072 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA ))
2073 }, 2073 },
2074 { PINMUX_DATA_REG("PCDR", 0xa4050124, 8) { 2074 { PINMUX_DATA_REG("PCDR", 0xa4050124, 8, GROUP(
2075 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA, 2075 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
2076 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA } 2076 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA ))
2077 }, 2077 },
2078 { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) { 2078 { PINMUX_DATA_REG("PDDR", 0xa4050126, 8, GROUP(
2079 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, 2079 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
2080 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA } 2080 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA ))
2081 }, 2081 },
2082 { PINMUX_DATA_REG("PEDR", 0xa4050128, 8) { 2082 { PINMUX_DATA_REG("PEDR", 0xa4050128, 8, GROUP(
2083 PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA, 2083 PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
2084 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA } 2084 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA ))
2085 }, 2085 },
2086 { PINMUX_DATA_REG("PFDR", 0xa405012a, 8) { 2086 { PINMUX_DATA_REG("PFDR", 0xa405012a, 8, GROUP(
2087 PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA, 2087 PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
2088 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA } 2088 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA ))
2089 }, 2089 },
2090 { PINMUX_DATA_REG("PGDR", 0xa405012c, 8) { 2090 { PINMUX_DATA_REG("PGDR", 0xa405012c, 8, GROUP(
2091 0, 0, PTG5_DATA, PTG4_DATA, 2091 0, 0, PTG5_DATA, PTG4_DATA,
2092 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA } 2092 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA ))
2093 }, 2093 },
2094 { PINMUX_DATA_REG("PHDR", 0xa405012e, 8) { 2094 { PINMUX_DATA_REG("PHDR", 0xa405012e, 8, GROUP(
2095 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA, 2095 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
2096 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA } 2096 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA ))
2097 }, 2097 },
2098 { PINMUX_DATA_REG("PJDR", 0xa4050130, 8) { 2098 { PINMUX_DATA_REG("PJDR", 0xa4050130, 8, GROUP(
2099 PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0, 2099 PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0,
2100 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA } 2100 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA ))
2101 }, 2101 },
2102 { PINMUX_DATA_REG("PKDR", 0xa4050132, 8) { 2102 { PINMUX_DATA_REG("PKDR", 0xa4050132, 8, GROUP(
2103 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA, 2103 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
2104 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA } 2104 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA ))
2105 }, 2105 },
2106 { PINMUX_DATA_REG("PLDR", 0xa4050134, 8) { 2106 { PINMUX_DATA_REG("PLDR", 0xa4050134, 8, GROUP(
2107 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, 2107 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
2108 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA } 2108 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA ))
2109 }, 2109 },
2110 { PINMUX_DATA_REG("PMDR", 0xa4050136, 8) { 2110 { PINMUX_DATA_REG("PMDR", 0xa4050136, 8, GROUP(
2111 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, 2111 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
2112 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA } 2112 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA ))
2113 }, 2113 },
2114 { PINMUX_DATA_REG("PNDR", 0xa4050138, 8) { 2114 { PINMUX_DATA_REG("PNDR", 0xa4050138, 8, GROUP(
2115 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, 2115 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
2116 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA } 2116 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA ))
2117 }, 2117 },
2118 { PINMUX_DATA_REG("PQDR", 0xa405013a, 8) { 2118 { PINMUX_DATA_REG("PQDR", 0xa405013a, 8, GROUP(
2119 PTQ7_DATA, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA, 2119 PTQ7_DATA, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
2120 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA } 2120 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA ))
2121 }, 2121 },
2122 { PINMUX_DATA_REG("PRDR", 0xa405013c, 8) { 2122 { PINMUX_DATA_REG("PRDR", 0xa405013c, 8, GROUP(
2123 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA, 2123 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
2124 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA } 2124 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA ))
2125 }, 2125 },
2126 { PINMUX_DATA_REG("PSDR", 0xa405013e, 8) { 2126 { PINMUX_DATA_REG("PSDR", 0xa405013e, 8, GROUP(
2127 0, PTS6_DATA, PTS5_DATA, PTS4_DATA, 2127 0, PTS6_DATA, PTS5_DATA, PTS4_DATA,
2128 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA } 2128 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA ))
2129 }, 2129 },
2130 { PINMUX_DATA_REG("PTDR", 0xa4050160, 8) { 2130 { PINMUX_DATA_REG("PTDR", 0xa4050160, 8, GROUP(
2131 PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA, 2131 PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
2132 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA } 2132 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA ))
2133 }, 2133 },
2134 { PINMUX_DATA_REG("PUDR", 0xa4050162, 8) { 2134 { PINMUX_DATA_REG("PUDR", 0xa4050162, 8, GROUP(
2135 PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA, 2135 PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
2136 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA } 2136 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA ))
2137 }, 2137 },
2138 { PINMUX_DATA_REG("PVDR", 0xa4050164, 8) { 2138 { PINMUX_DATA_REG("PVDR", 0xa4050164, 8, GROUP(
2139 PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA, 2139 PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
2140 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA } 2140 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
2141 }, 2141 },
2142 { PINMUX_DATA_REG("PWDR", 0xa4050166, 8) { 2142 { PINMUX_DATA_REG("PWDR", 0xa4050166, 8, GROUP(
2143 PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA, 2143 PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
2144 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA } 2144 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA ))
2145 }, 2145 },
2146 { PINMUX_DATA_REG("PXDR", 0xa4050168, 8) { 2146 { PINMUX_DATA_REG("PXDR", 0xa4050168, 8, GROUP(
2147 PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA, 2147 PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
2148 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA } 2148 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA ))
2149 }, 2149 },
2150 { PINMUX_DATA_REG("PYDR", 0xa405016a, 8) { 2150 { PINMUX_DATA_REG("PYDR", 0xa405016a, 8, GROUP(
2151 PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA, 2151 PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
2152 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA } 2152 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA ))
2153 }, 2153 },
2154 { PINMUX_DATA_REG("PZDR", 0xa405016c, 8) { 2154 { PINMUX_DATA_REG("PZDR", 0xa405016c, 8, GROUP(
2155 PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA, 2155 PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
2156 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA } 2156 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
2157 }, 2157 },
2158 { }, 2158 { },
2159}; 2159};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
index 748a32a3af82..fac7b4699121 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
@@ -1635,7 +1635,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
1635}; 1635};
1636 1636
1637static const struct pinmux_cfg_reg pinmux_config_regs[] = { 1637static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1638 { PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1) { 1638 { PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1, GROUP(
1639 GP_0_31_FN, FN_IP2_2_0, 1639 GP_0_31_FN, FN_IP2_2_0,
1640 GP_0_30_FN, FN_IP1_31_29, 1640 GP_0_30_FN, FN_IP1_31_29,
1641 GP_0_29_FN, FN_IP1_28_26, 1641 GP_0_29_FN, FN_IP1_28_26,
@@ -1667,9 +1667,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1667 GP_0_3_FN, FN_IP1_15_14, 1667 GP_0_3_FN, FN_IP1_15_14,
1668 GP_0_2_FN, FN_IP1_13_12, 1668 GP_0_2_FN, FN_IP1_13_12,
1669 GP_0_1_FN, FN_IP1_11_10, 1669 GP_0_1_FN, FN_IP1_11_10,
1670 GP_0_0_FN, FN_IP1_9_8 } 1670 GP_0_0_FN, FN_IP1_9_8 ))
1671 }, 1671 },
1672 { PINMUX_CFG_REG("GPSR1", 0xFFFC0008, 32, 1) { 1672 { PINMUX_CFG_REG("GPSR1", 0xFFFC0008, 32, 1, GROUP(
1673 GP_1_31_FN, FN_IP11_25_23, 1673 GP_1_31_FN, FN_IP11_25_23,
1674 GP_1_30_FN, FN_IP2_13_11, 1674 GP_1_30_FN, FN_IP2_13_11,
1675 GP_1_29_FN, FN_IP2_10_8, 1675 GP_1_29_FN, FN_IP2_10_8,
@@ -1701,9 +1701,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1701 GP_1_3_FN, FN_IP11_22_21, 1701 GP_1_3_FN, FN_IP11_22_21,
1702 GP_1_2_FN, FN_IP11_20_19, 1702 GP_1_2_FN, FN_IP11_20_19,
1703 GP_1_1_FN, FN_IP3_29_27, 1703 GP_1_1_FN, FN_IP3_29_27,
1704 GP_1_0_FN, FN_IP3_20 } 1704 GP_1_0_FN, FN_IP3_20 ))
1705 }, 1705 },
1706 { PINMUX_CFG_REG("GPSR2", 0xFFFC000C, 32, 1) { 1706 { PINMUX_CFG_REG("GPSR2", 0xFFFC000C, 32, 1, GROUP(
1707 GP_2_31_FN, FN_IP4_31_30, 1707 GP_2_31_FN, FN_IP4_31_30,
1708 GP_2_30_FN, FN_IP5_2_0, 1708 GP_2_30_FN, FN_IP5_2_0,
1709 GP_2_29_FN, FN_IP5_5_3, 1709 GP_2_29_FN, FN_IP5_5_3,
@@ -1735,9 +1735,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1735 GP_2_3_FN, FN_IP4_2_0, 1735 GP_2_3_FN, FN_IP4_2_0,
1736 GP_2_2_FN, FN_IP11_11_10, 1736 GP_2_2_FN, FN_IP11_11_10,
1737 GP_2_1_FN, FN_IP11_9_7, 1737 GP_2_1_FN, FN_IP11_9_7,
1738 GP_2_0_FN, FN_IP11_6_4 } 1738 GP_2_0_FN, FN_IP11_6_4 ))
1739 }, 1739 },
1740 { PINMUX_CFG_REG("GPSR3", 0xFFFC0010, 32, 1) { 1740 { PINMUX_CFG_REG("GPSR3", 0xFFFC0010, 32, 1, GROUP(
1741 GP_3_31_FN, FN_IP9_1_0, 1741 GP_3_31_FN, FN_IP9_1_0,
1742 GP_3_30_FN, FN_IP8_19_18, 1742 GP_3_30_FN, FN_IP8_19_18,
1743 GP_3_29_FN, FN_IP8_17_16, 1743 GP_3_29_FN, FN_IP8_17_16,
@@ -1769,10 +1769,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1769 GP_3_3_FN, FN_IP6_9_8, 1769 GP_3_3_FN, FN_IP6_9_8,
1770 GP_3_2_FN, FN_IP6_7_6, 1770 GP_3_2_FN, FN_IP6_7_6,
1771 GP_3_1_FN, FN_IP6_5_3, 1771 GP_3_1_FN, FN_IP6_5_3,
1772 GP_3_0_FN, FN_IP6_2_0 } 1772 GP_3_0_FN, FN_IP6_2_0 ))
1773 }, 1773 },
1774 1774
1775 { PINMUX_CFG_REG("GPSR4", 0xFFFC0014, 32, 1) { 1775 { PINMUX_CFG_REG("GPSR4", 0xFFFC0014, 32, 1, GROUP(
1776 GP_4_31_FN, FN_IP10_24_23, 1776 GP_4_31_FN, FN_IP10_24_23,
1777 GP_4_30_FN, FN_IP10_22, 1777 GP_4_30_FN, FN_IP10_22,
1778 GP_4_29_FN, FN_IP11_18_16, 1778 GP_4_29_FN, FN_IP11_18_16,
@@ -1804,9 +1804,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1804 GP_4_3_FN, FN_IP9_25_24, 1804 GP_4_3_FN, FN_IP9_25_24,
1805 GP_4_2_FN, FN_IP9_23_22, 1805 GP_4_2_FN, FN_IP9_23_22,
1806 GP_4_1_FN, FN_IP9_21_20, 1806 GP_4_1_FN, FN_IP9_21_20,
1807 GP_4_0_FN, FN_IP9_19_18 } 1807 GP_4_0_FN, FN_IP9_19_18 ))
1808 }, 1808 },
1809 { PINMUX_CFG_REG("GPSR5", 0xFFFC0018, 32, 1) { 1809 { PINMUX_CFG_REG("GPSR5", 0xFFFC0018, 32, 1, GROUP(
1810 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 28 */ 1810 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 28 */
1811 0, 0, 0, 0, 0, 0, 0, 0, /* 27 - 24 */ 1811 0, 0, 0, 0, 0, 0, 0, 0, /* 27 - 24 */
1812 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 20 */ 1812 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 20 */
@@ -1819,12 +1819,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1819 GP_5_3_FN, FN_IRQ3_B, 1819 GP_5_3_FN, FN_IRQ3_B,
1820 GP_5_2_FN, FN_IRQ2_B, 1820 GP_5_2_FN, FN_IRQ2_B,
1821 GP_5_1_FN, FN_IP11_3, 1821 GP_5_1_FN, FN_IP11_3,
1822 GP_5_0_FN, FN_IP10_25 } 1822 GP_5_0_FN, FN_IP10_25 ))
1823 }, 1823 },
1824 1824
1825 { PINMUX_CFG_REG_VAR("IPSR0", 0xFFFC001C, 32, 1825 { PINMUX_CFG_REG_VAR("IPSR0", 0xFFFC001C, 32,
1826 2, 2, 2, 2, 2, 2, 2, 2, 1826 GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2),
1827 2, 2, 2, 2, 2, 2, 2, 2) { 1827 GROUP(
1828 /* IP0_31_30 [2] */ 1828 /* IP0_31_30 [2] */
1829 FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A, 1829 FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A,
1830 FN_TIOC3D_C, 1830 FN_TIOC3D_C,
@@ -1857,10 +1857,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1857 /* IP0_3_2 [2] */ 1857 /* IP0_3_2 [2] */
1858 FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C, 1858 FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C,
1859 /* IP0_1_0 [2] */ 1859 /* IP0_1_0 [2] */
1860 FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C } 1860 FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C ))
1861 }, 1861 },
1862 { PINMUX_CFG_REG_VAR("IPSR1", 0xFFFC0020, 32, 1862 { PINMUX_CFG_REG_VAR("IPSR1", 0xFFFC0020, 32,
1863 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) { 1863 GROUP(3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2),
1864 GROUP(
1864 /* IP1_31_29 [3] */ 1865 /* IP1_31_29 [3] */
1865 FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6, 1866 FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6,
1866 FN_FD3_A, 0, 0, 0, 1867 FN_FD3_A, 0, 0, 0,
@@ -1892,10 +1893,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1892 /* IP1_3_2 [2] */ 1893 /* IP1_3_2 [2] */
1893 FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A, FN_TIOC4B_C, 1894 FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A, FN_TIOC4B_C,
1894 /* IP1_1_0 [2] */ 1895 /* IP1_1_0 [2] */
1895 FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C } 1896 FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C ))
1896 }, 1897 },
1897 { PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32, 1898 { PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32,
1898 1, 3, 3, 2, 3, 3, 3, 3, 3, 3, 2, 3) { 1899 GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 3, 2, 3),
1900 GROUP(
1899 /* IP2_31 [1] */ 1901 /* IP2_31 [1] */
1900 0, 0, 1902 0, 0,
1901 /* IP2_30_28 [3] */ 1903 /* IP2_30_28 [3] */
@@ -1928,10 +1930,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1928 FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A, 1930 FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A,
1929 /* IP2_2_0 [3] */ 1931 /* IP2_2_0 [3] */
1930 FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7, 1932 FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7,
1931 FN_FD4_A, 0, 0, 0 } 1933 FN_FD4_A, 0, 0, 0 ))
1932 }, 1934 },
1933 { PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32, 1935 { PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32,
1934 2, 3, 3, 3, 1, 2, 3, 3, 3, 3, 3, 1, 2) { 1936 GROUP(2, 3, 3, 3, 1, 2, 3, 3, 3, 3, 3, 1, 2),
1937 GROUP(
1935 /* IP3_31_30 [2] */ 1938 /* IP3_31_30 [2] */
1936 0, 0, 0, 0, 1939 0, 0, 0, 0,
1937 /* IP3_29_27 [3] */ 1940 /* IP3_29_27 [3] */
@@ -1965,10 +1968,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1965 /* IP3_2 [1] */ 1968 /* IP3_2 [1] */
1966 FN_CS1_A26, FN_QIO3_B, 1969 FN_CS1_A26, FN_QIO3_B,
1967 /* IP3_1_0 [2] */ 1970 /* IP3_1_0 [2] */
1968 FN_D15, FN_SCK2_B, 0, 0 } 1971 FN_D15, FN_SCK2_B, 0, 0 ))
1969 }, 1972 },
1970 { PINMUX_CFG_REG_VAR("IPSR4", 0xFFFC002C, 32, 1973 { PINMUX_CFG_REG_VAR("IPSR4", 0xFFFC002C, 32,
1971 2, 2, 2, 2, 2, 2 , 2, 3, 3, 3, 3, 3, 3) { 1974 GROUP(2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3),
1975 GROUP(
1972 /* IP4_31_30 [2] */ 1976 /* IP4_31_30 [2] */
1973 0, FN_SCK2_A, FN_VI0_G3, 0, 1977 0, FN_SCK2_A, FN_VI0_G3, 0,
1974 /* IP4_29_28 [2] */ 1978 /* IP4_29_28 [2] */
@@ -2000,10 +2004,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2000 FN_ET0_RX_DV, 0, 0, 0, 2004 FN_ET0_RX_DV, 0, 0, 0,
2001 /* IP4_2_0 [3] */ 2005 /* IP4_2_0 [3] */
2002 FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A, 2006 FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A,
2003 FN_ET0_ERXD7, 0, 0, 0 } 2007 FN_ET0_ERXD7, 0, 0, 0 ))
2004 }, 2008 },
2005 { PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32, 2009 { PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32,
2006 1, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3) { 2010 GROUP(1, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3,
2011 3, 3, 3),
2012 GROUP(
2007 /* IP5_31 [1] */ 2013 /* IP5_31 [1] */
2008 0, 0, 2014 0, 0,
2009 /* IP5_30 [1] */ 2015 /* IP5_30 [1] */
@@ -2040,11 +2046,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2040 0, 0, 0, FN_ET0_ERXD2_B, 2046 0, 0, 0, FN_ET0_ERXD2_B,
2041 /* IP5_2_0 [3] */ 2047 /* IP5_2_0 [3] */
2042 FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, 0, 2048 FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, 0,
2043 FN_ET0_RX_CLK_B, 0, 0, 0 } 2049 FN_ET0_RX_CLK_B, 0, 0, 0 ))
2044 }, 2050 },
2045 { PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32, 2051 { PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32,
2046 1, 1, 1, 1, 1, 1, 1, 1, 2052 GROUP(1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 2, 2,
2047 3, 3, 2, 2, 2, 2, 2, 2, 3, 3) { 2053 2, 2, 2, 2, 3, 3),
2054 GROUP(
2048 /* IP5_31 [1] */ 2055 /* IP5_31 [1] */
2049 0, 0, 2056 0, 0,
2050 /* IP6_30 [1] */ 2057 /* IP6_30 [1] */
@@ -2084,10 +2091,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2084 FN_TCLKB_A, FN_HIFD01, 0, 0, 2091 FN_TCLKB_A, FN_HIFD01, 0, 0,
2085 /* IP6_2_0 [3] */ 2092 /* IP6_2_0 [3] */
2086 FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A, 2093 FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A,
2087 FN_TCLKA_A, FN_HIFD00, 0, 0 } 2094 FN_TCLKA_A, FN_HIFD00, 0, 0 ))
2088 }, 2095 },
2089 { PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32, 2096 { PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32,
2090 1, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3) { 2097 GROUP(1, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3),
2098 GROUP(
2091 /* IP7_31 [1] */ 2099 /* IP7_31 [1] */
2092 0, 0, 2100 0, 0,
2093 /* IP7_30_29 [2] */ 2101 /* IP7_30_29 [2] */
@@ -2120,10 +2128,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2120 FN_HIFD11, 0, 0, 0, 2128 FN_HIFD11, 0, 0, 0,
2121 /* IP7_2_0 [3] */ 2129 /* IP7_2_0 [3] */
2122 FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A, 2130 FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A,
2123 FN_HIFD10, 0, 0, 0 } 2131 FN_HIFD10, 0, 0, 0 ))
2124 }, 2132 },
2125 { PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32, 2133 { PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32,
2126 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) { 2134 GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2,
2135 2, 2, 2),
2136 GROUP(
2127 /* IP9_31_30 [2] */ 2137 /* IP9_31_30 [2] */
2128 0, 0, 0, 0, 2138 0, 0, 0, 0,
2129 /* IP8_29_28 [2] */ 2139 /* IP8_29_28 [2] */
@@ -2156,11 +2166,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2156 /* IP8_3_2 [2] */ 2166 /* IP8_3_2 [2] */
2157 FN_DU0_DB6, 0, FN_HIFRDY, 0, 2167 FN_DU0_DB6, 0, FN_HIFRDY, 0,
2158 /* IP8_1_0 [2] */ 2168 /* IP8_1_0 [2] */
2159 FN_DU0_DB5, 0, FN_HIFDREQ, 0 } 2169 FN_DU0_DB5, 0, FN_HIFDREQ, 0 ))
2160 }, 2170 },
2161 { PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32, 2171 { PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32,
2162 2, 2, 2, 2, 2, 2, 2, 2, 2172 GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2163 2, 2, 2, 2, 2, 2, 2, 2) { 2173 2, 2, 2, 2),
2174 GROUP(
2164 /* IP9_31_30 [2] */ 2175 /* IP9_31_30 [2] */
2165 0, 0, 0, 0, 2176 0, 0, 0, 0,
2166 /* IP9_29_28 [2] */ 2177 /* IP9_29_28 [2] */
@@ -2192,11 +2203,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2192 /* IP9_3_2 [2] */ 2203 /* IP9_3_2 [2] */
2193 FN_VI1_0_A, 0, FN_FD1_B, FN_LCD_DATA1_B, 2204 FN_VI1_0_A, 0, FN_FD1_B, FN_LCD_DATA1_B,
2194 /* IP9_1_0 [2] */ 2205 /* IP9_1_0 [2] */
2195 FN_VI1_CLK_A, 0, FN_FD0_B, FN_LCD_DATA0_B } 2206 FN_VI1_CLK_A, 0, FN_FD0_B, FN_LCD_DATA0_B ))
2196 }, 2207 },
2197 { PINMUX_CFG_REG_VAR("IPSR10", 0xFFFC0044, 32, 2208 { PINMUX_CFG_REG_VAR("IPSR10", 0xFFFC0044, 32,
2198 2, 2, 2, 1, 2, 1, 3, 2209 GROUP(2, 2, 2, 1, 2, 1, 3, 3, 1, 3, 3, 3, 3, 3),
2199 3, 1, 3, 3, 3, 3, 3) { 2210 GROUP(
2200 /* IP9_31_30 [2] */ 2211 /* IP9_31_30 [2] */
2201 0, 0, 0, 0, 2212 0, 0, 0, 0,
2202 /* IP10_29_28 [2] */ 2213 /* IP10_29_28 [2] */
@@ -2231,10 +2242,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2231 FN_LCD_DON_B, 0, 0, 2242 FN_LCD_DON_B, 0, 0,
2232 /* IP10_2_0 [3] */ 2243 /* IP10_2_0 [3] */
2233 FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B, 2244 FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B,
2234 FN_LCD_DATA15_B, 0, 0, 0 } 2245 FN_LCD_DATA15_B, 0, 0, 0 ))
2235 }, 2246 },
2236 { PINMUX_CFG_REG_VAR("IPSR11", 0xFFFC0048, 32, 2247 { PINMUX_CFG_REG_VAR("IPSR11", 0xFFFC0048, 32,
2237 3, 1, 2, 3, 2, 2, 3, 3, 1, 2, 3, 3, 1, 1, 1, 1) { 2248 GROUP(3, 1, 2, 3, 2, 2, 3, 3, 1, 2, 3, 3,
2249 1, 1, 1, 1),
2250 GROUP(
2238 /* IP11_31_29 [3] */ 2251 /* IP11_31_29 [3] */
2239 0, 0, 0, 0, 0, 0, 0, 0, 2252 0, 0, 0, 0, 0, 0, 0, 0,
2240 /* IP11_28 [1] */ 2253 /* IP11_28 [1] */
@@ -2271,11 +2284,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2271 /* IP11_1 [1] */ 2284 /* IP11_1 [1] */
2272 FN_SDA1, FN_RX1_E, 2285 FN_SDA1, FN_RX1_E,
2273 /* IP11_0 [1] */ 2286 /* IP11_0 [1] */
2274 FN_SCL1, FN_SCIF_CLK_C } 2287 FN_SCL1, FN_SCIF_CLK_C ))
2275 }, 2288 },
2276 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xFFFC004C, 32, 2289 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xFFFC004C, 32,
2277 3, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2290 GROUP(3, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 2,
2278 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { 2291 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2292 GROUP(
2279 /* SEL1_31_29 [3] */ 2293 /* SEL1_31_29 [3] */
2280 0, 0, 0, 0, 0, 0, 0, 0, 2294 0, 0, 0, 0, 0, 0, 0, 0,
2281 /* SEL1_28 [1] */ 2295 /* SEL1_28 [1] */
@@ -2327,11 +2341,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2327 /* SEL1_1 [1] */ 2341 /* SEL1_1 [1] */
2328 FN_SEL_MMC_0, FN_SEL_MMC_1, 2342 FN_SEL_MMC_0, FN_SEL_MMC_1,
2329 /* SEL1_0 [1] */ 2343 /* SEL1_0 [1] */
2330 FN_SEL_INTC_0, FN_SEL_INTC_1 } 2344 FN_SEL_INTC_0, FN_SEL_INTC_1 ))
2331 }, 2345 },
2332 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xFFFC0050, 32, 2346 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xFFFC0050, 32,
2333 1, 1, 1, 1, 1, 1, 1, 1, 2347 GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
2334 1, 1, 1, 2, 2, 1, 2, 2, 3, 2, 3, 2, 2) { 2348 2, 1, 2, 2, 3, 2, 3, 2, 2),
2349 GROUP(
2335 /* SEL2_31 [1] */ 2350 /* SEL2_31 [1] */
2336 0, 0, 2351 0, 0,
2337 /* SEL2_30 [1] */ 2352 /* SEL2_30 [1] */
@@ -2375,15 +2390,20 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2375 /* SEL2_3_2 [2] */ 2390 /* SEL2_3_2 [2] */
2376 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 0, 2391 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 0,
2377 /* SEL2_1_0 [2] */ 2392 /* SEL2_1_0 [2] */
2378 FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2, 0 } 2393 FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2, 0 ))
2379 }, 2394 },
2380 /* GPIO 0 - 5*/ 2395 /* GPIO 0 - 5*/
2381 { PINMUX_CFG_REG("INOUTSEL0", 0xFFC40004, 32, 1) { GP_INOUTSEL(0) } }, 2396 { PINMUX_CFG_REG("INOUTSEL0", 0xFFC40004, 32, 1, GROUP(GP_INOUTSEL(0)))
2382 { PINMUX_CFG_REG("INOUTSEL1", 0xFFC41004, 32, 1) { GP_INOUTSEL(1) } }, 2397 },
2383 { PINMUX_CFG_REG("INOUTSEL2", 0xFFC42004, 32, 1) { GP_INOUTSEL(2) } }, 2398 { PINMUX_CFG_REG("INOUTSEL1", 0xFFC41004, 32, 1, GROUP(GP_INOUTSEL(1)))
2384 { PINMUX_CFG_REG("INOUTSEL3", 0xFFC43004, 32, 1) { GP_INOUTSEL(3) } }, 2399 },
2385 { PINMUX_CFG_REG("INOUTSEL4", 0xFFC44004, 32, 1) { GP_INOUTSEL(4) } }, 2400 { PINMUX_CFG_REG("INOUTSEL2", 0xFFC42004, 32, 1, GROUP(GP_INOUTSEL(2)))
2386 { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) { 2401 },
2402 { PINMUX_CFG_REG("INOUTSEL3", 0xFFC43004, 32, 1, GROUP(GP_INOUTSEL(3)))
2403 },
2404 { PINMUX_CFG_REG("INOUTSEL4", 0xFFC44004, 32, 1, GROUP(GP_INOUTSEL(4)))
2405 },
2406 { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1, GROUP(
2387 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 24 */ 2407 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 24 */
2388 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 16 */ 2408 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 16 */
2389 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */ 2409 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */
@@ -2398,24 +2418,24 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2398 GP_5_3_IN, GP_5_3_OUT, 2418 GP_5_3_IN, GP_5_3_OUT,
2399 GP_5_2_IN, GP_5_2_OUT, 2419 GP_5_2_IN, GP_5_2_OUT,
2400 GP_5_1_IN, GP_5_1_OUT, 2420 GP_5_1_IN, GP_5_1_OUT,
2401 GP_5_0_IN, GP_5_0_OUT } 2421 GP_5_0_IN, GP_5_0_OUT ))
2402 }, 2422 },
2403 { }, 2423 { },
2404}; 2424};
2405 2425
2406static const struct pinmux_data_reg pinmux_data_regs[] = { 2426static const struct pinmux_data_reg pinmux_data_regs[] = {
2407 /* GPIO 0 - 5*/ 2427 /* GPIO 0 - 5*/
2408 { PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32) { GP_INDT(0) } }, 2428 { PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32, GROUP(GP_INDT(0))) },
2409 { PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32) { GP_INDT(1) } }, 2429 { PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32, GROUP(GP_INDT(1))) },
2410 { PINMUX_DATA_REG("INDT2", 0xFFC4200C, 32) { GP_INDT(2) } }, 2430 { PINMUX_DATA_REG("INDT2", 0xFFC4200C, 32, GROUP(GP_INDT(2))) },
2411 { PINMUX_DATA_REG("INDT3", 0xFFC4300C, 32) { GP_INDT(3) } }, 2431 { PINMUX_DATA_REG("INDT3", 0xFFC4300C, 32, GROUP(GP_INDT(3))) },
2412 { PINMUX_DATA_REG("INDT4", 0xFFC4400C, 32) { GP_INDT(4) } }, 2432 { PINMUX_DATA_REG("INDT4", 0xFFC4400C, 32, GROUP(GP_INDT(4))) },
2413 { PINMUX_DATA_REG("INDT5", 0xFFC4500C, 32) { 2433 { PINMUX_DATA_REG("INDT5", 0xFFC4500C, 32, GROUP(
2414 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2434 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2415 0, 0, 0, 0, 2435 0, 0, 0, 0,
2416 GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA, 2436 GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
2417 GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA, 2437 GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
2418 GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA } 2438 GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA ))
2419 }, 2439 },
2420 { }, 2440 { },
2421}; 2441};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
index b16090690ee3..064e987b09cb 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
@@ -1683,7 +1683,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
1683}; 1683};
1684 1684
1685static const struct pinmux_cfg_reg pinmux_config_regs[] = { 1685static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1686 { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) { 1686 { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2, GROUP(
1687 PTA7_FN, PTA7_OUT, PTA7_IN, 0, 1687 PTA7_FN, PTA7_OUT, PTA7_IN, 0,
1688 PTA6_FN, PTA6_OUT, PTA6_IN, 0, 1688 PTA6_FN, PTA6_OUT, PTA6_IN, 0,
1689 PTA5_FN, PTA5_OUT, PTA5_IN, 0, 1689 PTA5_FN, PTA5_OUT, PTA5_IN, 0,
@@ -1691,9 +1691,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1691 PTA3_FN, PTA3_OUT, PTA3_IN, 0, 1691 PTA3_FN, PTA3_OUT, PTA3_IN, 0,
1692 PTA2_FN, PTA2_OUT, PTA2_IN, 0, 1692 PTA2_FN, PTA2_OUT, PTA2_IN, 0,
1693 PTA1_FN, PTA1_OUT, PTA1_IN, 0, 1693 PTA1_FN, PTA1_OUT, PTA1_IN, 0,
1694 PTA0_FN, PTA0_OUT, PTA0_IN, 0 } 1694 PTA0_FN, PTA0_OUT, PTA0_IN, 0 ))
1695 }, 1695 },
1696 { PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2) { 1696 { PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2, GROUP(
1697 PTB7_FN, PTB7_OUT, PTB7_IN, 0, 1697 PTB7_FN, PTB7_OUT, PTB7_IN, 0,
1698 PTB6_FN, PTB6_OUT, PTB6_IN, 0, 1698 PTB6_FN, PTB6_OUT, PTB6_IN, 0,
1699 PTB5_FN, PTB5_OUT, PTB5_IN, 0, 1699 PTB5_FN, PTB5_OUT, PTB5_IN, 0,
@@ -1701,9 +1701,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1701 PTB3_FN, PTB3_OUT, PTB3_IN, 0, 1701 PTB3_FN, PTB3_OUT, PTB3_IN, 0,
1702 PTB2_FN, PTB2_OUT, PTB2_IN, 0, 1702 PTB2_FN, PTB2_OUT, PTB2_IN, 0,
1703 PTB1_FN, PTB1_OUT, PTB1_IN, 0, 1703 PTB1_FN, PTB1_OUT, PTB1_IN, 0,
1704 PTB0_FN, PTB0_OUT, PTB0_IN, 0 } 1704 PTB0_FN, PTB0_OUT, PTB0_IN, 0 ))
1705 }, 1705 },
1706 { PINMUX_CFG_REG("PCCR", 0xffec0004, 16, 2) { 1706 { PINMUX_CFG_REG("PCCR", 0xffec0004, 16, 2, GROUP(
1707 PTC7_FN, PTC7_OUT, PTC7_IN, 0, 1707 PTC7_FN, PTC7_OUT, PTC7_IN, 0,
1708 PTC6_FN, PTC6_OUT, PTC6_IN, 0, 1708 PTC6_FN, PTC6_OUT, PTC6_IN, 0,
1709 PTC5_FN, PTC5_OUT, PTC5_IN, 0, 1709 PTC5_FN, PTC5_OUT, PTC5_IN, 0,
@@ -1711,9 +1711,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1711 PTC3_FN, PTC3_OUT, PTC3_IN, 0, 1711 PTC3_FN, PTC3_OUT, PTC3_IN, 0,
1712 PTC2_FN, PTC2_OUT, PTC2_IN, 0, 1712 PTC2_FN, PTC2_OUT, PTC2_IN, 0,
1713 PTC1_FN, PTC1_OUT, PTC1_IN, 0, 1713 PTC1_FN, PTC1_OUT, PTC1_IN, 0,
1714 PTC0_FN, PTC0_OUT, PTC0_IN, 0 } 1714 PTC0_FN, PTC0_OUT, PTC0_IN, 0 ))
1715 }, 1715 },
1716 { PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2) { 1716 { PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2, GROUP(
1717 PTD7_FN, PTD7_OUT, PTD7_IN, 0, 1717 PTD7_FN, PTD7_OUT, PTD7_IN, 0,
1718 PTD6_FN, PTD6_OUT, PTD6_IN, 0, 1718 PTD6_FN, PTD6_OUT, PTD6_IN, 0,
1719 PTD5_FN, PTD5_OUT, PTD5_IN, 0, 1719 PTD5_FN, PTD5_OUT, PTD5_IN, 0,
@@ -1721,9 +1721,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1721 PTD3_FN, PTD3_OUT, PTD3_IN, 0, 1721 PTD3_FN, PTD3_OUT, PTD3_IN, 0,
1722 PTD2_FN, PTD2_OUT, PTD2_IN, 0, 1722 PTD2_FN, PTD2_OUT, PTD2_IN, 0,
1723 PTD1_FN, PTD1_OUT, PTD1_IN, 0, 1723 PTD1_FN, PTD1_OUT, PTD1_IN, 0,
1724 PTD0_FN, PTD0_OUT, PTD0_IN, 0 } 1724 PTD0_FN, PTD0_OUT, PTD0_IN, 0 ))
1725 }, 1725 },
1726 { PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2) { 1726 { PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2, GROUP(
1727 PTE7_FN, PTE7_OUT, PTE7_IN, 0, 1727 PTE7_FN, PTE7_OUT, PTE7_IN, 0,
1728 PTE6_FN, PTE6_OUT, PTE6_IN, 0, 1728 PTE6_FN, PTE6_OUT, PTE6_IN, 0,
1729 PTE5_FN, PTE5_OUT, PTE5_IN, 0, 1729 PTE5_FN, PTE5_OUT, PTE5_IN, 0,
@@ -1731,9 +1731,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1731 PTE3_FN, PTE3_OUT, PTE3_IN, 0, 1731 PTE3_FN, PTE3_OUT, PTE3_IN, 0,
1732 PTE2_FN, PTE2_OUT, PTE2_IN, 0, 1732 PTE2_FN, PTE2_OUT, PTE2_IN, 0,
1733 PTE1_FN, PTE1_OUT, PTE1_IN, 0, 1733 PTE1_FN, PTE1_OUT, PTE1_IN, 0,
1734 PTE0_FN, PTE0_OUT, PTE0_IN, 0 } 1734 PTE0_FN, PTE0_OUT, PTE0_IN, 0 ))
1735 }, 1735 },
1736 { PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2) { 1736 { PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2, GROUP(
1737 PTF7_FN, PTF7_OUT, PTF7_IN, 0, 1737 PTF7_FN, PTF7_OUT, PTF7_IN, 0,
1738 PTF6_FN, PTF6_OUT, PTF6_IN, 0, 1738 PTF6_FN, PTF6_OUT, PTF6_IN, 0,
1739 PTF5_FN, PTF5_OUT, PTF5_IN, 0, 1739 PTF5_FN, PTF5_OUT, PTF5_IN, 0,
@@ -1741,9 +1741,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1741 PTF3_FN, PTF3_OUT, PTF3_IN, 0, 1741 PTF3_FN, PTF3_OUT, PTF3_IN, 0,
1742 PTF2_FN, PTF2_OUT, PTF2_IN, 0, 1742 PTF2_FN, PTF2_OUT, PTF2_IN, 0,
1743 PTF1_FN, PTF1_OUT, PTF1_IN, 0, 1743 PTF1_FN, PTF1_OUT, PTF1_IN, 0,
1744 PTF0_FN, PTF0_OUT, PTF0_IN, 0 } 1744 PTF0_FN, PTF0_OUT, PTF0_IN, 0 ))
1745 }, 1745 },
1746 { PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2) { 1746 { PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2, GROUP(
1747 PTG7_FN, PTG7_OUT, PTG7_IN, 0, 1747 PTG7_FN, PTG7_OUT, PTG7_IN, 0,
1748 PTG6_FN, PTG6_OUT, PTG6_IN, 0, 1748 PTG6_FN, PTG6_OUT, PTG6_IN, 0,
1749 PTG5_FN, PTG5_OUT, PTG5_IN, 0, 1749 PTG5_FN, PTG5_OUT, PTG5_IN, 0,
@@ -1751,9 +1751,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1751 PTG3_FN, PTG3_OUT, PTG3_IN, 0, 1751 PTG3_FN, PTG3_OUT, PTG3_IN, 0,
1752 PTG2_FN, PTG2_OUT, PTG2_IN, 0, 1752 PTG2_FN, PTG2_OUT, PTG2_IN, 0,
1753 PTG1_FN, PTG1_OUT, PTG1_IN, 0, 1753 PTG1_FN, PTG1_OUT, PTG1_IN, 0,
1754 PTG0_FN, PTG0_OUT, PTG0_IN, 0 } 1754 PTG0_FN, PTG0_OUT, PTG0_IN, 0 ))
1755 }, 1755 },
1756 { PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2) { 1756 { PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2, GROUP(
1757 PTH7_FN, PTH7_OUT, PTH7_IN, 0, 1757 PTH7_FN, PTH7_OUT, PTH7_IN, 0,
1758 PTH6_FN, PTH6_OUT, PTH6_IN, 0, 1758 PTH6_FN, PTH6_OUT, PTH6_IN, 0,
1759 PTH5_FN, PTH5_OUT, PTH5_IN, 0, 1759 PTH5_FN, PTH5_OUT, PTH5_IN, 0,
@@ -1761,9 +1761,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1761 PTH3_FN, PTH3_OUT, PTH3_IN, 0, 1761 PTH3_FN, PTH3_OUT, PTH3_IN, 0,
1762 PTH2_FN, PTH2_OUT, PTH2_IN, 0, 1762 PTH2_FN, PTH2_OUT, PTH2_IN, 0,
1763 PTH1_FN, PTH1_OUT, PTH1_IN, 0, 1763 PTH1_FN, PTH1_OUT, PTH1_IN, 0,
1764 PTH0_FN, PTH0_OUT, PTH0_IN, 0 } 1764 PTH0_FN, PTH0_OUT, PTH0_IN, 0 ))
1765 }, 1765 },
1766 { PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2) { 1766 { PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2, GROUP(
1767 PTI7_FN, PTI7_OUT, PTI7_IN, 0, 1767 PTI7_FN, PTI7_OUT, PTI7_IN, 0,
1768 PTI6_FN, PTI6_OUT, PTI6_IN, 0, 1768 PTI6_FN, PTI6_OUT, PTI6_IN, 0,
1769 PTI5_FN, PTI5_OUT, PTI5_IN, 0, 1769 PTI5_FN, PTI5_OUT, PTI5_IN, 0,
@@ -1771,9 +1771,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1771 PTI3_FN, PTI3_OUT, PTI3_IN, 0, 1771 PTI3_FN, PTI3_OUT, PTI3_IN, 0,
1772 PTI2_FN, PTI2_OUT, PTI2_IN, 0, 1772 PTI2_FN, PTI2_OUT, PTI2_IN, 0,
1773 PTI1_FN, PTI1_OUT, PTI1_IN, 0, 1773 PTI1_FN, PTI1_OUT, PTI1_IN, 0,
1774 PTI0_FN, PTI0_OUT, PTI0_IN, 0 } 1774 PTI0_FN, PTI0_OUT, PTI0_IN, 0 ))
1775 }, 1775 },
1776 { PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2) { 1776 { PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2, GROUP(
1777 0, 0, 0, 0, /* reserved: always set 1 */ 1777 0, 0, 0, 0, /* reserved: always set 1 */
1778 PTJ6_FN, PTJ6_OUT, PTJ6_IN, 0, 1778 PTJ6_FN, PTJ6_OUT, PTJ6_IN, 0,
1779 PTJ5_FN, PTJ5_OUT, PTJ5_IN, 0, 1779 PTJ5_FN, PTJ5_OUT, PTJ5_IN, 0,
@@ -1781,9 +1781,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1781 PTJ3_FN, PTJ3_OUT, PTJ3_IN, 0, 1781 PTJ3_FN, PTJ3_OUT, PTJ3_IN, 0,
1782 PTJ2_FN, PTJ2_OUT, PTJ2_IN, 0, 1782 PTJ2_FN, PTJ2_OUT, PTJ2_IN, 0,
1783 PTJ1_FN, PTJ1_OUT, PTJ1_IN, 0, 1783 PTJ1_FN, PTJ1_OUT, PTJ1_IN, 0,
1784 PTJ0_FN, PTJ0_OUT, PTJ0_IN, 0 } 1784 PTJ0_FN, PTJ0_OUT, PTJ0_IN, 0 ))
1785 }, 1785 },
1786 { PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2) { 1786 { PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2, GROUP(
1787 PTK7_FN, PTK7_OUT, PTK7_IN, 0, 1787 PTK7_FN, PTK7_OUT, PTK7_IN, 0,
1788 PTK6_FN, PTK6_OUT, PTK6_IN, 0, 1788 PTK6_FN, PTK6_OUT, PTK6_IN, 0,
1789 PTK5_FN, PTK5_OUT, PTK5_IN, 0, 1789 PTK5_FN, PTK5_OUT, PTK5_IN, 0,
@@ -1791,9 +1791,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1791 PTK3_FN, PTK3_OUT, PTK3_IN, 0, 1791 PTK3_FN, PTK3_OUT, PTK3_IN, 0,
1792 PTK2_FN, PTK2_OUT, PTK2_IN, 0, 1792 PTK2_FN, PTK2_OUT, PTK2_IN, 0,
1793 PTK1_FN, PTK1_OUT, PTK1_IN, 0, 1793 PTK1_FN, PTK1_OUT, PTK1_IN, 0,
1794 PTK0_FN, PTK0_OUT, PTK0_IN, 0 } 1794 PTK0_FN, PTK0_OUT, PTK0_IN, 0 ))
1795 }, 1795 },
1796 { PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2) { 1796 { PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2, GROUP(
1797 0, 0, 0, 0, /* reserved: always set 1 */ 1797 0, 0, 0, 0, /* reserved: always set 1 */
1798 PTL6_FN, PTL6_OUT, PTL6_IN, 0, 1798 PTL6_FN, PTL6_OUT, PTL6_IN, 0,
1799 PTL5_FN, PTL5_OUT, PTL5_IN, 0, 1799 PTL5_FN, PTL5_OUT, PTL5_IN, 0,
@@ -1801,9 +1801,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1801 PTL3_FN, PTL3_OUT, PTL3_IN, 0, 1801 PTL3_FN, PTL3_OUT, PTL3_IN, 0,
1802 PTL2_FN, PTL2_OUT, PTL2_IN, 0, 1802 PTL2_FN, PTL2_OUT, PTL2_IN, 0,
1803 PTL1_FN, PTL1_OUT, PTL1_IN, 0, 1803 PTL1_FN, PTL1_OUT, PTL1_IN, 0,
1804 PTL0_FN, PTL0_OUT, PTL0_IN, 0 } 1804 PTL0_FN, PTL0_OUT, PTL0_IN, 0 ))
1805 }, 1805 },
1806 { PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2) { 1806 { PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2, GROUP(
1807 PTM7_FN, PTM7_OUT, PTM7_IN, 0, 1807 PTM7_FN, PTM7_OUT, PTM7_IN, 0,
1808 PTM6_FN, PTM6_OUT, PTM6_IN, 0, 1808 PTM6_FN, PTM6_OUT, PTM6_IN, 0,
1809 PTM5_FN, PTM5_OUT, PTM5_IN, 0, 1809 PTM5_FN, PTM5_OUT, PTM5_IN, 0,
@@ -1811,9 +1811,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1811 PTM3_FN, PTM3_OUT, PTM3_IN, 0, 1811 PTM3_FN, PTM3_OUT, PTM3_IN, 0,
1812 PTM2_FN, PTM2_OUT, PTM2_IN, 0, 1812 PTM2_FN, PTM2_OUT, PTM2_IN, 0,
1813 PTM1_FN, PTM1_OUT, PTM1_IN, 0, 1813 PTM1_FN, PTM1_OUT, PTM1_IN, 0,
1814 PTM0_FN, PTM0_OUT, PTM0_IN, 0 } 1814 PTM0_FN, PTM0_OUT, PTM0_IN, 0 ))
1815 }, 1815 },
1816 { PINMUX_CFG_REG("PNCR", 0xffec001a, 16, 2) { 1816 { PINMUX_CFG_REG("PNCR", 0xffec001a, 16, 2, GROUP(
1817 0, 0, 0, 0, /* reserved: always set 1 */ 1817 0, 0, 0, 0, /* reserved: always set 1 */
1818 PTN6_FN, PTN6_OUT, PTN6_IN, 0, 1818 PTN6_FN, PTN6_OUT, PTN6_IN, 0,
1819 PTN5_FN, PTN5_OUT, PTN5_IN, 0, 1819 PTN5_FN, PTN5_OUT, PTN5_IN, 0,
@@ -1821,9 +1821,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1821 PTN3_FN, PTN3_OUT, PTN3_IN, 0, 1821 PTN3_FN, PTN3_OUT, PTN3_IN, 0,
1822 PTN2_FN, PTN2_OUT, PTN2_IN, 0, 1822 PTN2_FN, PTN2_OUT, PTN2_IN, 0,
1823 PTN1_FN, PTN1_OUT, PTN1_IN, 0, 1823 PTN1_FN, PTN1_OUT, PTN1_IN, 0,
1824 PTN0_FN, PTN0_OUT, PTN0_IN, 0 } 1824 PTN0_FN, PTN0_OUT, PTN0_IN, 0 ))
1825 }, 1825 },
1826 { PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2) { 1826 { PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2, GROUP(
1827 PTO7_FN, PTO7_OUT, PTO7_IN, 0, 1827 PTO7_FN, PTO7_OUT, PTO7_IN, 0,
1828 PTO6_FN, PTO6_OUT, PTO6_IN, 0, 1828 PTO6_FN, PTO6_OUT, PTO6_IN, 0,
1829 PTO5_FN, PTO5_OUT, PTO5_IN, 0, 1829 PTO5_FN, PTO5_OUT, PTO5_IN, 0,
@@ -1831,10 +1831,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1831 PTO3_FN, PTO3_OUT, PTO3_IN, 0, 1831 PTO3_FN, PTO3_OUT, PTO3_IN, 0,
1832 PTO2_FN, PTO2_OUT, PTO2_IN, 0, 1832 PTO2_FN, PTO2_OUT, PTO2_IN, 0,
1833 PTO1_FN, PTO1_OUT, PTO1_IN, 0, 1833 PTO1_FN, PTO1_OUT, PTO1_IN, 0,
1834 PTO0_FN, PTO0_OUT, PTO0_IN, 0 } 1834 PTO0_FN, PTO0_OUT, PTO0_IN, 0 ))
1835 }, 1835 },
1836#if 0 /* FIXME: Remove it? */ 1836#if 0 /* FIXME: Remove it? */
1837 { PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2) { 1837 { PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2, GROUP(
1838 0, 0, 0, 0, /* reserved: always set 1 */ 1838 0, 0, 0, 0, /* reserved: always set 1 */
1839 PTP6_FN, PTP6_OUT, PTP6_IN, 0, 1839 PTP6_FN, PTP6_OUT, PTP6_IN, 0,
1840 PTP5_FN, PTP5_OUT, PTP5_IN, 0, 1840 PTP5_FN, PTP5_OUT, PTP5_IN, 0,
@@ -1842,10 +1842,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1842 PTP3_FN, PTP3_OUT, PTP3_IN, 0, 1842 PTP3_FN, PTP3_OUT, PTP3_IN, 0,
1843 PTP2_FN, PTP2_OUT, PTP2_IN, 0, 1843 PTP2_FN, PTP2_OUT, PTP2_IN, 0,
1844 PTP1_FN, PTP1_OUT, PTP1_IN, 0, 1844 PTP1_FN, PTP1_OUT, PTP1_IN, 0,
1845 PTP0_FN, PTP0_OUT, PTP0_IN, 0 } 1845 PTP0_FN, PTP0_OUT, PTP0_IN, 0 ))
1846 }, 1846 },
1847#endif 1847#endif
1848 { PINMUX_CFG_REG("PQCR", 0xffec0020, 16, 2) { 1848 { PINMUX_CFG_REG("PQCR", 0xffec0020, 16, 2, GROUP(
1849 0, 0, 0, 0, /* reserved: always set 1 */ 1849 0, 0, 0, 0, /* reserved: always set 1 */
1850 PTQ6_FN, PTQ6_OUT, PTQ6_IN, 0, 1850 PTQ6_FN, PTQ6_OUT, PTQ6_IN, 0,
1851 PTQ5_FN, PTQ5_OUT, PTQ5_IN, 0, 1851 PTQ5_FN, PTQ5_OUT, PTQ5_IN, 0,
@@ -1853,9 +1853,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1853 PTQ3_FN, PTQ3_OUT, PTQ3_IN, 0, 1853 PTQ3_FN, PTQ3_OUT, PTQ3_IN, 0,
1854 PTQ2_FN, PTQ2_OUT, PTQ2_IN, 0, 1854 PTQ2_FN, PTQ2_OUT, PTQ2_IN, 0,
1855 PTQ1_FN, PTQ1_OUT, PTQ1_IN, 0, 1855 PTQ1_FN, PTQ1_OUT, PTQ1_IN, 0,
1856 PTQ0_FN, PTQ0_OUT, PTQ0_IN, 0 } 1856 PTQ0_FN, PTQ0_OUT, PTQ0_IN, 0 ))
1857 }, 1857 },
1858 { PINMUX_CFG_REG("PRCR", 0xffec0022, 16, 2) { 1858 { PINMUX_CFG_REG("PRCR", 0xffec0022, 16, 2, GROUP(
1859 PTR7_FN, PTR7_OUT, PTR7_IN, 0, 1859 PTR7_FN, PTR7_OUT, PTR7_IN, 0,
1860 PTR6_FN, PTR6_OUT, PTR6_IN, 0, 1860 PTR6_FN, PTR6_OUT, PTR6_IN, 0,
1861 PTR5_FN, PTR5_OUT, PTR5_IN, 0, 1861 PTR5_FN, PTR5_OUT, PTR5_IN, 0,
@@ -1863,9 +1863,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1863 PTR3_FN, PTR3_OUT, PTR3_IN, 0, 1863 PTR3_FN, PTR3_OUT, PTR3_IN, 0,
1864 PTR2_FN, PTR2_OUT, PTR2_IN, 0, 1864 PTR2_FN, PTR2_OUT, PTR2_IN, 0,
1865 PTR1_FN, PTR1_OUT, PTR1_IN, 0, 1865 PTR1_FN, PTR1_OUT, PTR1_IN, 0,
1866 PTR0_FN, PTR0_OUT, PTR0_IN, 0 } 1866 PTR0_FN, PTR0_OUT, PTR0_IN, 0 ))
1867 }, 1867 },
1868 { PINMUX_CFG_REG("PSCR", 0xffec0024, 16, 2) { 1868 { PINMUX_CFG_REG("PSCR", 0xffec0024, 16, 2, GROUP(
1869 PTS7_FN, PTS7_OUT, PTS7_IN, 0, 1869 PTS7_FN, PTS7_OUT, PTS7_IN, 0,
1870 PTS6_FN, PTS6_OUT, PTS6_IN, 0, 1870 PTS6_FN, PTS6_OUT, PTS6_IN, 0,
1871 PTS5_FN, PTS5_OUT, PTS5_IN, 0, 1871 PTS5_FN, PTS5_OUT, PTS5_IN, 0,
@@ -1873,9 +1873,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1873 PTS3_FN, PTS3_OUT, PTS3_IN, 0, 1873 PTS3_FN, PTS3_OUT, PTS3_IN, 0,
1874 PTS2_FN, PTS2_OUT, PTS2_IN, 0, 1874 PTS2_FN, PTS2_OUT, PTS2_IN, 0,
1875 PTS1_FN, PTS1_OUT, PTS1_IN, 0, 1875 PTS1_FN, PTS1_OUT, PTS1_IN, 0,
1876 PTS0_FN, PTS0_OUT, PTS0_IN, 0 } 1876 PTS0_FN, PTS0_OUT, PTS0_IN, 0 ))
1877 }, 1877 },
1878 { PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2) { 1878 { PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2, GROUP(
1879 PTT7_FN, PTT7_OUT, PTT7_IN, 0, 1879 PTT7_FN, PTT7_OUT, PTT7_IN, 0,
1880 PTT6_FN, PTT6_OUT, PTT6_IN, 0, 1880 PTT6_FN, PTT6_OUT, PTT6_IN, 0,
1881 PTT5_FN, PTT5_OUT, PTT5_IN, 0, 1881 PTT5_FN, PTT5_OUT, PTT5_IN, 0,
@@ -1883,9 +1883,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1883 PTT3_FN, PTT3_OUT, PTT3_IN, 0, 1883 PTT3_FN, PTT3_OUT, PTT3_IN, 0,
1884 PTT2_FN, PTT2_OUT, PTT2_IN, 0, 1884 PTT2_FN, PTT2_OUT, PTT2_IN, 0,
1885 PTT1_FN, PTT1_OUT, PTT1_IN, 0, 1885 PTT1_FN, PTT1_OUT, PTT1_IN, 0,
1886 PTT0_FN, PTT0_OUT, PTT0_IN, 0 } 1886 PTT0_FN, PTT0_OUT, PTT0_IN, 0 ))
1887 }, 1887 },
1888 { PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2) { 1888 { PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2, GROUP(
1889 PTU7_FN, PTU7_OUT, PTU7_IN, 0, 1889 PTU7_FN, PTU7_OUT, PTU7_IN, 0,
1890 PTU6_FN, PTU6_OUT, PTU6_IN, 0, 1890 PTU6_FN, PTU6_OUT, PTU6_IN, 0,
1891 PTU5_FN, PTU5_OUT, PTU5_IN, 0, 1891 PTU5_FN, PTU5_OUT, PTU5_IN, 0,
@@ -1893,9 +1893,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1893 PTU3_FN, PTU3_OUT, PTU3_IN, 0, 1893 PTU3_FN, PTU3_OUT, PTU3_IN, 0,
1894 PTU2_FN, PTU2_OUT, PTU2_IN, 0, 1894 PTU2_FN, PTU2_OUT, PTU2_IN, 0,
1895 PTU1_FN, PTU1_OUT, PTU1_IN, 0, 1895 PTU1_FN, PTU1_OUT, PTU1_IN, 0,
1896 PTU0_FN, PTU0_OUT, PTU0_IN, 0 } 1896 PTU0_FN, PTU0_OUT, PTU0_IN, 0 ))
1897 }, 1897 },
1898 { PINMUX_CFG_REG("PVCR", 0xffec002a, 16, 2) { 1898 { PINMUX_CFG_REG("PVCR", 0xffec002a, 16, 2, GROUP(
1899 PTV7_FN, PTV7_OUT, PTV7_IN, 0, 1899 PTV7_FN, PTV7_OUT, PTV7_IN, 0,
1900 PTV6_FN, PTV6_OUT, PTV6_IN, 0, 1900 PTV6_FN, PTV6_OUT, PTV6_IN, 0,
1901 PTV5_FN, PTV5_OUT, PTV5_IN, 0, 1901 PTV5_FN, PTV5_OUT, PTV5_IN, 0,
@@ -1903,9 +1903,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1903 PTV3_FN, PTV3_OUT, PTV3_IN, 0, 1903 PTV3_FN, PTV3_OUT, PTV3_IN, 0,
1904 PTV2_FN, PTV2_OUT, PTV2_IN, 0, 1904 PTV2_FN, PTV2_OUT, PTV2_IN, 0,
1905 PTV1_FN, PTV1_OUT, PTV1_IN, 0, 1905 PTV1_FN, PTV1_OUT, PTV1_IN, 0,
1906 PTV0_FN, PTV0_OUT, PTV0_IN, 0 } 1906 PTV0_FN, PTV0_OUT, PTV0_IN, 0 ))
1907 }, 1907 },
1908 { PINMUX_CFG_REG("PWCR", 0xffec002c, 16, 2) { 1908 { PINMUX_CFG_REG("PWCR", 0xffec002c, 16, 2, GROUP(
1909 PTW7_FN, PTW7_OUT, PTW7_IN, 0, 1909 PTW7_FN, PTW7_OUT, PTW7_IN, 0,
1910 PTW6_FN, PTW6_OUT, PTW6_IN, 0, 1910 PTW6_FN, PTW6_OUT, PTW6_IN, 0,
1911 PTW5_FN, PTW5_OUT, PTW5_IN, 0, 1911 PTW5_FN, PTW5_OUT, PTW5_IN, 0,
@@ -1913,9 +1913,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1913 PTW3_FN, PTW3_OUT, PTW3_IN, 0, 1913 PTW3_FN, PTW3_OUT, PTW3_IN, 0,
1914 PTW2_FN, PTW2_OUT, PTW2_IN, 0, 1914 PTW2_FN, PTW2_OUT, PTW2_IN, 0,
1915 PTW1_FN, PTW1_OUT, PTW1_IN, 0, 1915 PTW1_FN, PTW1_OUT, PTW1_IN, 0,
1916 PTW0_FN, PTW0_OUT, PTW0_IN, 0 } 1916 PTW0_FN, PTW0_OUT, PTW0_IN, 0 ))
1917 }, 1917 },
1918 { PINMUX_CFG_REG("PXCR", 0xffec002e, 16, 2) { 1918 { PINMUX_CFG_REG("PXCR", 0xffec002e, 16, 2, GROUP(
1919 PTX7_FN, PTX7_OUT, PTX7_IN, 0, 1919 PTX7_FN, PTX7_OUT, PTX7_IN, 0,
1920 PTX6_FN, PTX6_OUT, PTX6_IN, 0, 1920 PTX6_FN, PTX6_OUT, PTX6_IN, 0,
1921 PTX5_FN, PTX5_OUT, PTX5_IN, 0, 1921 PTX5_FN, PTX5_OUT, PTX5_IN, 0,
@@ -1923,9 +1923,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1923 PTX3_FN, PTX3_OUT, PTX3_IN, 0, 1923 PTX3_FN, PTX3_OUT, PTX3_IN, 0,
1924 PTX2_FN, PTX2_OUT, PTX2_IN, 0, 1924 PTX2_FN, PTX2_OUT, PTX2_IN, 0,
1925 PTX1_FN, PTX1_OUT, PTX1_IN, 0, 1925 PTX1_FN, PTX1_OUT, PTX1_IN, 0,
1926 PTX0_FN, PTX0_OUT, PTX0_IN, 0 } 1926 PTX0_FN, PTX0_OUT, PTX0_IN, 0 ))
1927 }, 1927 },
1928 { PINMUX_CFG_REG("PYCR", 0xffec0030, 16, 2) { 1928 { PINMUX_CFG_REG("PYCR", 0xffec0030, 16, 2, GROUP(
1929 PTY7_FN, PTY7_OUT, PTY7_IN, 0, 1929 PTY7_FN, PTY7_OUT, PTY7_IN, 0,
1930 PTY6_FN, PTY6_OUT, PTY6_IN, 0, 1930 PTY6_FN, PTY6_OUT, PTY6_IN, 0,
1931 PTY5_FN, PTY5_OUT, PTY5_IN, 0, 1931 PTY5_FN, PTY5_OUT, PTY5_IN, 0,
@@ -1933,9 +1933,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1933 PTY3_FN, PTY3_OUT, PTY3_IN, 0, 1933 PTY3_FN, PTY3_OUT, PTY3_IN, 0,
1934 PTY2_FN, PTY2_OUT, PTY2_IN, 0, 1934 PTY2_FN, PTY2_OUT, PTY2_IN, 0,
1935 PTY1_FN, PTY1_OUT, PTY1_IN, 0, 1935 PTY1_FN, PTY1_OUT, PTY1_IN, 0,
1936 PTY0_FN, PTY0_OUT, PTY0_IN, 0 } 1936 PTY0_FN, PTY0_OUT, PTY0_IN, 0 ))
1937 }, 1937 },
1938 { PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2) { 1938 { PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2, GROUP(
1939 PTZ7_FN, PTZ7_OUT, PTZ7_IN, 0, 1939 PTZ7_FN, PTZ7_OUT, PTZ7_IN, 0,
1940 PTZ6_FN, PTZ6_OUT, PTZ6_IN, 0, 1940 PTZ6_FN, PTZ6_OUT, PTZ6_IN, 0,
1941 PTZ5_FN, PTZ5_OUT, PTZ5_IN, 0, 1941 PTZ5_FN, PTZ5_OUT, PTZ5_IN, 0,
@@ -1943,10 +1943,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1943 PTZ3_FN, PTZ3_OUT, PTZ3_IN, 0, 1943 PTZ3_FN, PTZ3_OUT, PTZ3_IN, 0,
1944 PTZ2_FN, PTZ2_OUT, PTZ2_IN, 0, 1944 PTZ2_FN, PTZ2_OUT, PTZ2_IN, 0,
1945 PTZ1_FN, PTZ1_OUT, PTZ1_IN, 0, 1945 PTZ1_FN, PTZ1_OUT, PTZ1_IN, 0,
1946 PTZ0_FN, PTZ0_OUT, PTZ0_IN, 0 } 1946 PTZ0_FN, PTZ0_OUT, PTZ0_IN, 0 ))
1947 }, 1947 },
1948 1948
1949 { PINMUX_CFG_REG("PSEL0", 0xffec0070, 16, 1) { 1949 { PINMUX_CFG_REG("PSEL0", 0xffec0070, 16, 1, GROUP(
1950 PS0_15_FN1, PS0_15_FN2, 1950 PS0_15_FN1, PS0_15_FN2,
1951 PS0_14_FN1, PS0_14_FN2, 1951 PS0_14_FN1, PS0_14_FN2,
1952 PS0_13_FN1, PS0_13_FN2, 1952 PS0_13_FN1, PS0_13_FN2,
@@ -1962,9 +1962,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1962 PS0_3_FN1, PS0_3_FN2, 1962 PS0_3_FN1, PS0_3_FN2,
1963 PS0_2_FN1, PS0_2_FN2, 1963 PS0_2_FN1, PS0_2_FN2,
1964 0, 0, 1964 0, 0,
1965 0, 0, } 1965 0, 0, ))
1966 }, 1966 },
1967 { PINMUX_CFG_REG("PSEL1", 0xffec0072, 16, 1) { 1967 { PINMUX_CFG_REG("PSEL1", 0xffec0072, 16, 1, GROUP(
1968 0, 0, 1968 0, 0,
1969 0, 0, 1969 0, 0,
1970 0, 0, 1970 0, 0,
@@ -1980,9 +1980,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1980 0, 0, 1980 0, 0,
1981 PS1_2_FN1, PS1_2_FN2, 1981 PS1_2_FN1, PS1_2_FN2,
1982 0, 0, 1982 0, 0,
1983 0, 0, } 1983 0, 0, ))
1984 }, 1984 },
1985 { PINMUX_CFG_REG("PSEL2", 0xffec0074, 16, 1) { 1985 { PINMUX_CFG_REG("PSEL2", 0xffec0074, 16, 1, GROUP(
1986 0, 0, 1986 0, 0,
1987 0, 0, 1987 0, 0,
1988 PS2_13_FN1, PS2_13_FN2, 1988 PS2_13_FN1, PS2_13_FN2,
@@ -1998,9 +1998,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1998 0, 0, 1998 0, 0,
1999 PS2_2_FN1, PS2_2_FN2, 1999 PS2_2_FN1, PS2_2_FN2,
2000 0, 0, 2000 0, 0,
2001 0, 0, } 2001 0, 0, ))
2002 }, 2002 },
2003 { PINMUX_CFG_REG("PSEL3", 0xffec0076, 16, 1) { 2003 { PINMUX_CFG_REG("PSEL3", 0xffec0076, 16, 1, GROUP(
2004 PS3_15_FN1, PS3_15_FN2, 2004 PS3_15_FN1, PS3_15_FN2,
2005 PS3_14_FN1, PS3_14_FN2, 2005 PS3_14_FN1, PS3_14_FN2,
2006 PS3_13_FN1, PS3_13_FN2, 2006 PS3_13_FN1, PS3_13_FN2,
@@ -2016,10 +2016,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2016 0, 0, 2016 0, 0,
2017 PS3_2_FN1, PS3_2_FN2, 2017 PS3_2_FN1, PS3_2_FN2,
2018 PS3_1_FN1, PS3_1_FN2, 2018 PS3_1_FN1, PS3_1_FN2,
2019 0, 0, } 2019 0, 0, ))
2020 }, 2020 },
2021 2021
2022 { PINMUX_CFG_REG("PSEL4", 0xffec0078, 16, 1) { 2022 { PINMUX_CFG_REG("PSEL4", 0xffec0078, 16, 1, GROUP(
2023 0, 0, 2023 0, 0,
2024 PS4_14_FN1, PS4_14_FN2, 2024 PS4_14_FN1, PS4_14_FN2,
2025 PS4_13_FN1, PS4_13_FN2, 2025 PS4_13_FN1, PS4_13_FN2,
@@ -2035,9 +2035,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2035 PS4_3_FN1, PS4_3_FN2, 2035 PS4_3_FN1, PS4_3_FN2,
2036 PS4_2_FN1, PS4_2_FN2, 2036 PS4_2_FN1, PS4_2_FN2,
2037 PS4_1_FN1, PS4_1_FN2, 2037 PS4_1_FN1, PS4_1_FN2,
2038 PS4_0_FN1, PS4_0_FN2, } 2038 PS4_0_FN1, PS4_0_FN2, ))
2039 }, 2039 },
2040 { PINMUX_CFG_REG("PSEL5", 0xffec007a, 16, 1) { 2040 { PINMUX_CFG_REG("PSEL5", 0xffec007a, 16, 1, GROUP(
2041 0, 0, 2041 0, 0,
2042 0, 0, 2042 0, 0,
2043 0, 0, 2043 0, 0,
@@ -2053,9 +2053,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2053 PS5_3_FN1, PS5_3_FN2, 2053 PS5_3_FN1, PS5_3_FN2,
2054 PS5_2_FN1, PS5_2_FN2, 2054 PS5_2_FN1, PS5_2_FN2,
2055 0, 0, 2055 0, 0,
2056 0, 0, } 2056 0, 0, ))
2057 }, 2057 },
2058 { PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1) { 2058 { PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1, GROUP(
2059 PS6_15_FN1, PS6_15_FN2, 2059 PS6_15_FN1, PS6_15_FN2,
2060 PS6_14_FN1, PS6_14_FN2, 2060 PS6_14_FN1, PS6_14_FN2,
2061 PS6_13_FN1, PS6_13_FN2, 2061 PS6_13_FN1, PS6_13_FN2,
@@ -2071,9 +2071,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2071 PS6_3_FN1, PS6_3_FN2, 2071 PS6_3_FN1, PS6_3_FN2,
2072 PS6_2_FN1, PS6_2_FN2, 2072 PS6_2_FN1, PS6_2_FN2,
2073 PS6_1_FN1, PS6_1_FN2, 2073 PS6_1_FN1, PS6_1_FN2,
2074 PS6_0_FN1, PS6_0_FN2, } 2074 PS6_0_FN1, PS6_0_FN2, ))
2075 }, 2075 },
2076 { PINMUX_CFG_REG("PSEL7", 0xffec0082, 16, 1) { 2076 { PINMUX_CFG_REG("PSEL7", 0xffec0082, 16, 1, GROUP(
2077 PS7_15_FN1, PS7_15_FN2, 2077 PS7_15_FN1, PS7_15_FN2,
2078 PS7_14_FN1, PS7_14_FN2, 2078 PS7_14_FN1, PS7_14_FN2,
2079 PS7_13_FN1, PS7_13_FN2, 2079 PS7_13_FN1, PS7_13_FN2,
@@ -2089,9 +2089,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2089 0, 0, 2089 0, 0,
2090 0, 0, 2090 0, 0,
2091 0, 0, 2091 0, 0,
2092 0, 0, } 2092 0, 0, ))
2093 }, 2093 },
2094 { PINMUX_CFG_REG("PSEL8", 0xffec0084, 16, 1) { 2094 { PINMUX_CFG_REG("PSEL8", 0xffec0084, 16, 1, GROUP(
2095 PS8_15_FN1, PS8_15_FN2, 2095 PS8_15_FN1, PS8_15_FN2,
2096 PS8_14_FN1, PS8_14_FN2, 2096 PS8_14_FN1, PS8_14_FN2,
2097 PS8_13_FN1, PS8_13_FN2, 2097 PS8_13_FN1, PS8_13_FN2,
@@ -2107,115 +2107,115 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2107 0, 0, 2107 0, 0,
2108 0, 0, 2108 0, 0,
2109 0, 0, 2109 0, 0,
2110 0, 0, } 2110 0, 0, ))
2111 }, 2111 },
2112 {} 2112 {}
2113}; 2113};
2114 2114
2115static const struct pinmux_data_reg pinmux_data_regs[] = { 2115static const struct pinmux_data_reg pinmux_data_regs[] = {
2116 { PINMUX_DATA_REG("PADR", 0xffec0034, 8) { 2116 { PINMUX_DATA_REG("PADR", 0xffec0034, 8, GROUP(
2117 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, 2117 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
2118 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } 2118 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA ))
2119 }, 2119 },
2120 { PINMUX_DATA_REG("PBDR", 0xffec0036, 8) { 2120 { PINMUX_DATA_REG("PBDR", 0xffec0036, 8, GROUP(
2121 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, 2121 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
2122 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA } 2122 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA ))
2123 }, 2123 },
2124 { PINMUX_DATA_REG("PCDR", 0xffec0038, 8) { 2124 { PINMUX_DATA_REG("PCDR", 0xffec0038, 8, GROUP(
2125 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA, 2125 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
2126 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA } 2126 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA ))
2127 }, 2127 },
2128 { PINMUX_DATA_REG("PDDR", 0xffec003a, 8) { 2128 { PINMUX_DATA_REG("PDDR", 0xffec003a, 8, GROUP(
2129 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, 2129 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
2130 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA } 2130 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA ))
2131 }, 2131 },
2132 { PINMUX_DATA_REG("PEDR", 0xffec003c, 8) { 2132 { PINMUX_DATA_REG("PEDR", 0xffec003c, 8, GROUP(
2133 PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA, 2133 PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
2134 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA } 2134 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA ))
2135 }, 2135 },
2136 { PINMUX_DATA_REG("PFDR", 0xffec003e, 8) { 2136 { PINMUX_DATA_REG("PFDR", 0xffec003e, 8, GROUP(
2137 PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA, 2137 PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
2138 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA } 2138 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA ))
2139 }, 2139 },
2140 { PINMUX_DATA_REG("PGDR", 0xffec0040, 8) { 2140 { PINMUX_DATA_REG("PGDR", 0xffec0040, 8, GROUP(
2141 PTG7_DATA, PTG6_DATA, PTG5_DATA, PTG4_DATA, 2141 PTG7_DATA, PTG6_DATA, PTG5_DATA, PTG4_DATA,
2142 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA } 2142 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA ))
2143 }, 2143 },
2144 { PINMUX_DATA_REG("PHDR", 0xffec0042, 8) { 2144 { PINMUX_DATA_REG("PHDR", 0xffec0042, 8, GROUP(
2145 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA, 2145 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
2146 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA } 2146 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA ))
2147 }, 2147 },
2148 { PINMUX_DATA_REG("PIDR", 0xffec0044, 8) { 2148 { PINMUX_DATA_REG("PIDR", 0xffec0044, 8, GROUP(
2149 PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA, 2149 PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA,
2150 PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA } 2150 PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA ))
2151 }, 2151 },
2152 { PINMUX_DATA_REG("PJDR", 0xffec0046, 8) { 2152 { PINMUX_DATA_REG("PJDR", 0xffec0046, 8, GROUP(
2153 0, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA, 2153 0, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
2154 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA } 2154 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA ))
2155 }, 2155 },
2156 { PINMUX_DATA_REG("PKDR", 0xffec0048, 8) { 2156 { PINMUX_DATA_REG("PKDR", 0xffec0048, 8, GROUP(
2157 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA, 2157 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
2158 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA } 2158 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA ))
2159 }, 2159 },
2160 { PINMUX_DATA_REG("PLDR", 0xffec004a, 8) { 2160 { PINMUX_DATA_REG("PLDR", 0xffec004a, 8, GROUP(
2161 0, PTL6_DATA, PTL5_DATA, PTL4_DATA, 2161 0, PTL6_DATA, PTL5_DATA, PTL4_DATA,
2162 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA } 2162 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA ))
2163 }, 2163 },
2164 { PINMUX_DATA_REG("PMDR", 0xffec004c, 8) { 2164 { PINMUX_DATA_REG("PMDR", 0xffec004c, 8, GROUP(
2165 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, 2165 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
2166 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA } 2166 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA ))
2167 }, 2167 },
2168 { PINMUX_DATA_REG("PNDR", 0xffec004e, 8) { 2168 { PINMUX_DATA_REG("PNDR", 0xffec004e, 8, GROUP(
2169 0, PTN6_DATA, PTN5_DATA, PTN4_DATA, 2169 0, PTN6_DATA, PTN5_DATA, PTN4_DATA,
2170 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA } 2170 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA ))
2171 }, 2171 },
2172 { PINMUX_DATA_REG("PODR", 0xffec0050, 8) { 2172 { PINMUX_DATA_REG("PODR", 0xffec0050, 8, GROUP(
2173 PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA, 2173 PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA,
2174 PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA } 2174 PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA ))
2175 }, 2175 },
2176 { PINMUX_DATA_REG("PPDR", 0xffec0052, 8) { 2176 { PINMUX_DATA_REG("PPDR", 0xffec0052, 8, GROUP(
2177 PTP7_DATA, PTP6_DATA, PTP5_DATA, PTP4_DATA, 2177 PTP7_DATA, PTP6_DATA, PTP5_DATA, PTP4_DATA,
2178 PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA } 2178 PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA ))
2179 }, 2179 },
2180 { PINMUX_DATA_REG("PQDR", 0xffec0054, 8) { 2180 { PINMUX_DATA_REG("PQDR", 0xffec0054, 8, GROUP(
2181 0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA, 2181 0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
2182 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA } 2182 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA ))
2183 }, 2183 },
2184 { PINMUX_DATA_REG("PRDR", 0xffec0056, 8) { 2184 { PINMUX_DATA_REG("PRDR", 0xffec0056, 8, GROUP(
2185 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA, 2185 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
2186 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA } 2186 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA ))
2187 }, 2187 },
2188 { PINMUX_DATA_REG("PSDR", 0xffec0058, 8) { 2188 { PINMUX_DATA_REG("PSDR", 0xffec0058, 8, GROUP(
2189 PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA, 2189 PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
2190 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA } 2190 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA ))
2191 }, 2191 },
2192 { PINMUX_DATA_REG("PTDR", 0xffec005a, 8) { 2192 { PINMUX_DATA_REG("PTDR", 0xffec005a, 8, GROUP(
2193 PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA, 2193 PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
2194 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA } 2194 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA ))
2195 }, 2195 },
2196 { PINMUX_DATA_REG("PUDR", 0xffec005c, 8) { 2196 { PINMUX_DATA_REG("PUDR", 0xffec005c, 8, GROUP(
2197 PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA, 2197 PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
2198 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA } 2198 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA ))
2199 }, 2199 },
2200 { PINMUX_DATA_REG("PVDR", 0xffec005e, 8) { 2200 { PINMUX_DATA_REG("PVDR", 0xffec005e, 8, GROUP(
2201 PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA, 2201 PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
2202 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA } 2202 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
2203 }, 2203 },
2204 { PINMUX_DATA_REG("PWDR", 0xffec0060, 8) { 2204 { PINMUX_DATA_REG("PWDR", 0xffec0060, 8, GROUP(
2205 PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA, 2205 PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
2206 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA } 2206 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA ))
2207 }, 2207 },
2208 { PINMUX_DATA_REG("PXDR", 0xffec0062, 8) { 2208 { PINMUX_DATA_REG("PXDR", 0xffec0062, 8, GROUP(
2209 PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA, 2209 PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
2210 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA } 2210 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA ))
2211 }, 2211 },
2212 { PINMUX_DATA_REG("PYDR", 0xffec0064, 8) { 2212 { PINMUX_DATA_REG("PYDR", 0xffec0064, 8, GROUP(
2213 PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA, 2213 PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
2214 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA } 2214 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA ))
2215 }, 2215 },
2216 { PINMUX_DATA_REG("PZDR", 0xffec0066, 8) { 2216 { PINMUX_DATA_REG("PZDR", 0xffec0066, 8, GROUP(
2217 PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA, 2217 PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
2218 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA } 2218 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
2219 }, 2219 },
2220 { }, 2220 { },
2221}; 2221};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
index 193179f7fdd9..c4c1e288c53e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
@@ -985,7 +985,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
985}; 985};
986 986
987static const struct pinmux_cfg_reg pinmux_config_regs[] = { 987static const struct pinmux_cfg_reg pinmux_config_regs[] = {
988 { PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2) { 988 { PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2, GROUP(
989 PA7_FN, PA7_OUT, PA7_IN, 0, 989 PA7_FN, PA7_OUT, PA7_IN, 0,
990 PA6_FN, PA6_OUT, PA6_IN, 0, 990 PA6_FN, PA6_OUT, PA6_IN, 0,
991 PA5_FN, PA5_OUT, PA5_IN, 0, 991 PA5_FN, PA5_OUT, PA5_IN, 0,
@@ -993,9 +993,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
993 PA3_FN, PA3_OUT, PA3_IN, 0, 993 PA3_FN, PA3_OUT, PA3_IN, 0,
994 PA2_FN, PA2_OUT, PA2_IN, 0, 994 PA2_FN, PA2_OUT, PA2_IN, 0,
995 PA1_FN, PA1_OUT, PA1_IN, 0, 995 PA1_FN, PA1_OUT, PA1_IN, 0,
996 PA0_FN, PA0_OUT, PA0_IN, 0 } 996 PA0_FN, PA0_OUT, PA0_IN, 0 ))
997 }, 997 },
998 { PINMUX_CFG_REG("PBCR", 0xffe70002, 16, 2) { 998 { PINMUX_CFG_REG("PBCR", 0xffe70002, 16, 2, GROUP(
999 PB7_FN, PB7_OUT, PB7_IN, 0, 999 PB7_FN, PB7_OUT, PB7_IN, 0,
1000 PB6_FN, PB6_OUT, PB6_IN, 0, 1000 PB6_FN, PB6_OUT, PB6_IN, 0,
1001 PB5_FN, PB5_OUT, PB5_IN, 0, 1001 PB5_FN, PB5_OUT, PB5_IN, 0,
@@ -1003,9 +1003,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1003 PB3_FN, PB3_OUT, PB3_IN, 0, 1003 PB3_FN, PB3_OUT, PB3_IN, 0,
1004 PB2_FN, PB2_OUT, PB2_IN, 0, 1004 PB2_FN, PB2_OUT, PB2_IN, 0,
1005 PB1_FN, PB1_OUT, PB1_IN, 0, 1005 PB1_FN, PB1_OUT, PB1_IN, 0,
1006 PB0_FN, PB0_OUT, PB0_IN, 0 } 1006 PB0_FN, PB0_OUT, PB0_IN, 0 ))
1007 }, 1007 },
1008 { PINMUX_CFG_REG("PCCR", 0xffe70004, 16, 2) { 1008 { PINMUX_CFG_REG("PCCR", 0xffe70004, 16, 2, GROUP(
1009 PC7_FN, PC7_OUT, PC7_IN, 0, 1009 PC7_FN, PC7_OUT, PC7_IN, 0,
1010 PC6_FN, PC6_OUT, PC6_IN, 0, 1010 PC6_FN, PC6_OUT, PC6_IN, 0,
1011 PC5_FN, PC5_OUT, PC5_IN, 0, 1011 PC5_FN, PC5_OUT, PC5_IN, 0,
@@ -1013,9 +1013,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1013 PC3_FN, PC3_OUT, PC3_IN, 0, 1013 PC3_FN, PC3_OUT, PC3_IN, 0,
1014 PC2_FN, PC2_OUT, PC2_IN, 0, 1014 PC2_FN, PC2_OUT, PC2_IN, 0,
1015 PC1_FN, PC1_OUT, PC1_IN, 0, 1015 PC1_FN, PC1_OUT, PC1_IN, 0,
1016 PC0_FN, PC0_OUT, PC0_IN, 0 } 1016 PC0_FN, PC0_OUT, PC0_IN, 0 ))
1017 }, 1017 },
1018 { PINMUX_CFG_REG("PDCR", 0xffe70006, 16, 2) { 1018 { PINMUX_CFG_REG("PDCR", 0xffe70006, 16, 2, GROUP(
1019 PD7_FN, PD7_OUT, PD7_IN, 0, 1019 PD7_FN, PD7_OUT, PD7_IN, 0,
1020 PD6_FN, PD6_OUT, PD6_IN, 0, 1020 PD6_FN, PD6_OUT, PD6_IN, 0,
1021 PD5_FN, PD5_OUT, PD5_IN, 0, 1021 PD5_FN, PD5_OUT, PD5_IN, 0,
@@ -1023,9 +1023,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1023 PD3_FN, PD3_OUT, PD3_IN, 0, 1023 PD3_FN, PD3_OUT, PD3_IN, 0,
1024 PD2_FN, PD2_OUT, PD2_IN, 0, 1024 PD2_FN, PD2_OUT, PD2_IN, 0,
1025 PD1_FN, PD1_OUT, PD1_IN, 0, 1025 PD1_FN, PD1_OUT, PD1_IN, 0,
1026 PD0_FN, PD0_OUT, PD0_IN, 0 } 1026 PD0_FN, PD0_OUT, PD0_IN, 0 ))
1027 }, 1027 },
1028 { PINMUX_CFG_REG("PECR", 0xffe70008, 16, 2) { 1028 { PINMUX_CFG_REG("PECR", 0xffe70008, 16, 2, GROUP(
1029 0, 0, 0, 0, 1029 0, 0, 0, 0,
1030 0, 0, 0, 0, 1030 0, 0, 0, 0,
1031 PE5_FN, PE5_OUT, PE5_IN, 0, 1031 PE5_FN, PE5_OUT, PE5_IN, 0,
@@ -1033,9 +1033,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1033 PE3_FN, PE3_OUT, PE3_IN, 0, 1033 PE3_FN, PE3_OUT, PE3_IN, 0,
1034 PE2_FN, PE2_OUT, PE2_IN, 0, 1034 PE2_FN, PE2_OUT, PE2_IN, 0,
1035 PE1_FN, PE1_OUT, PE1_IN, 0, 1035 PE1_FN, PE1_OUT, PE1_IN, 0,
1036 PE0_FN, PE0_OUT, PE0_IN, 0 } 1036 PE0_FN, PE0_OUT, PE0_IN, 0 ))
1037 }, 1037 },
1038 { PINMUX_CFG_REG("PFCR", 0xffe7000a, 16, 2) { 1038 { PINMUX_CFG_REG("PFCR", 0xffe7000a, 16, 2, GROUP(
1039 PF7_FN, PF7_OUT, PF7_IN, 0, 1039 PF7_FN, PF7_OUT, PF7_IN, 0,
1040 PF6_FN, PF6_OUT, PF6_IN, 0, 1040 PF6_FN, PF6_OUT, PF6_IN, 0,
1041 PF5_FN, PF5_OUT, PF5_IN, 0, 1041 PF5_FN, PF5_OUT, PF5_IN, 0,
@@ -1043,9 +1043,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1043 PF3_FN, PF3_OUT, PF3_IN, 0, 1043 PF3_FN, PF3_OUT, PF3_IN, 0,
1044 PF2_FN, PF2_OUT, PF2_IN, 0, 1044 PF2_FN, PF2_OUT, PF2_IN, 0,
1045 PF1_FN, PF1_OUT, PF1_IN, 0, 1045 PF1_FN, PF1_OUT, PF1_IN, 0,
1046 PF0_FN, PF0_OUT, PF0_IN, 0 } 1046 PF0_FN, PF0_OUT, PF0_IN, 0 ))
1047 }, 1047 },
1048 { PINMUX_CFG_REG("PGCR", 0xffe7000c, 16, 2) { 1048 { PINMUX_CFG_REG("PGCR", 0xffe7000c, 16, 2, GROUP(
1049 PG7_FN, PG7_OUT, PG7_IN, 0, 1049 PG7_FN, PG7_OUT, PG7_IN, 0,
1050 PG6_FN, PG6_OUT, PG6_IN, 0, 1050 PG6_FN, PG6_OUT, PG6_IN, 0,
1051 PG5_FN, PG5_OUT, PG5_IN, 0, 1051 PG5_FN, PG5_OUT, PG5_IN, 0,
@@ -1053,9 +1053,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1053 PG3_FN, PG3_OUT, PG3_IN, 0, 1053 PG3_FN, PG3_OUT, PG3_IN, 0,
1054 PG2_FN, PG2_OUT, PG2_IN, 0, 1054 PG2_FN, PG2_OUT, PG2_IN, 0,
1055 PG1_FN, PG1_OUT, PG1_IN, 0, 1055 PG1_FN, PG1_OUT, PG1_IN, 0,
1056 PG0_FN, PG0_OUT, PG0_IN, 0 } 1056 PG0_FN, PG0_OUT, PG0_IN, 0 ))
1057 }, 1057 },
1058 { PINMUX_CFG_REG("PHCR", 0xffe7000e, 16, 2) { 1058 { PINMUX_CFG_REG("PHCR", 0xffe7000e, 16, 2, GROUP(
1059 PH7_FN, PH7_OUT, PH7_IN, 0, 1059 PH7_FN, PH7_OUT, PH7_IN, 0,
1060 PH6_FN, PH6_OUT, PH6_IN, 0, 1060 PH6_FN, PH6_OUT, PH6_IN, 0,
1061 PH5_FN, PH5_OUT, PH5_IN, 0, 1061 PH5_FN, PH5_OUT, PH5_IN, 0,
@@ -1063,9 +1063,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1063 PH3_FN, PH3_OUT, PH3_IN, 0, 1063 PH3_FN, PH3_OUT, PH3_IN, 0,
1064 PH2_FN, PH2_OUT, PH2_IN, 0, 1064 PH2_FN, PH2_OUT, PH2_IN, 0,
1065 PH1_FN, PH1_OUT, PH1_IN, 0, 1065 PH1_FN, PH1_OUT, PH1_IN, 0,
1066 PH0_FN, PH0_OUT, PH0_IN, 0 } 1066 PH0_FN, PH0_OUT, PH0_IN, 0 ))
1067 }, 1067 },
1068 { PINMUX_CFG_REG("PJCR", 0xffe70010, 16, 2) { 1068 { PINMUX_CFG_REG("PJCR", 0xffe70010, 16, 2, GROUP(
1069 PJ7_FN, PJ7_OUT, PJ7_IN, 0, 1069 PJ7_FN, PJ7_OUT, PJ7_IN, 0,
1070 PJ6_FN, PJ6_OUT, PJ6_IN, 0, 1070 PJ6_FN, PJ6_OUT, PJ6_IN, 0,
1071 PJ5_FN, PJ5_OUT, PJ5_IN, 0, 1071 PJ5_FN, PJ5_OUT, PJ5_IN, 0,
@@ -1073,9 +1073,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1073 PJ3_FN, PJ3_OUT, PJ3_IN, 0, 1073 PJ3_FN, PJ3_OUT, PJ3_IN, 0,
1074 PJ2_FN, PJ2_OUT, PJ2_IN, 0, 1074 PJ2_FN, PJ2_OUT, PJ2_IN, 0,
1075 PJ1_FN, PJ1_OUT, PJ1_IN, 0, 1075 PJ1_FN, PJ1_OUT, PJ1_IN, 0,
1076 PJ0_FN, PJ0_OUT, PJ0_IN, 0 } 1076 PJ0_FN, PJ0_OUT, PJ0_IN, 0 ))
1077 }, 1077 },
1078 { PINMUX_CFG_REG("PKCR", 0xffe70012, 16, 2) { 1078 { PINMUX_CFG_REG("PKCR", 0xffe70012, 16, 2, GROUP(
1079 PK7_FN, PK7_OUT, PK7_IN, 0, 1079 PK7_FN, PK7_OUT, PK7_IN, 0,
1080 PK6_FN, PK6_OUT, PK6_IN, 0, 1080 PK6_FN, PK6_OUT, PK6_IN, 0,
1081 PK5_FN, PK5_OUT, PK5_IN, 0, 1081 PK5_FN, PK5_OUT, PK5_IN, 0,
@@ -1083,9 +1083,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1083 PK3_FN, PK3_OUT, PK3_IN, 0, 1083 PK3_FN, PK3_OUT, PK3_IN, 0,
1084 PK2_FN, PK2_OUT, PK2_IN, 0, 1084 PK2_FN, PK2_OUT, PK2_IN, 0,
1085 PK1_FN, PK1_OUT, PK1_IN, 0, 1085 PK1_FN, PK1_OUT, PK1_IN, 0,
1086 PK0_FN, PK0_OUT, PK0_IN, 0 } 1086 PK0_FN, PK0_OUT, PK0_IN, 0 ))
1087 }, 1087 },
1088 { PINMUX_CFG_REG("PLCR", 0xffe70014, 16, 2) { 1088 { PINMUX_CFG_REG("PLCR", 0xffe70014, 16, 2, GROUP(
1089 PL7_FN, PL7_OUT, PL7_IN, 0, 1089 PL7_FN, PL7_OUT, PL7_IN, 0,
1090 PL6_FN, PL6_OUT, PL6_IN, 0, 1090 PL6_FN, PL6_OUT, PL6_IN, 0,
1091 PL5_FN, PL5_OUT, PL5_IN, 0, 1091 PL5_FN, PL5_OUT, PL5_IN, 0,
@@ -1093,9 +1093,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1093 PL3_FN, PL3_OUT, PL3_IN, 0, 1093 PL3_FN, PL3_OUT, PL3_IN, 0,
1094 PL2_FN, PL2_OUT, PL2_IN, 0, 1094 PL2_FN, PL2_OUT, PL2_IN, 0,
1095 PL1_FN, PL1_OUT, PL1_IN, 0, 1095 PL1_FN, PL1_OUT, PL1_IN, 0,
1096 PL0_FN, PL0_OUT, PL0_IN, 0 } 1096 PL0_FN, PL0_OUT, PL0_IN, 0 ))
1097 }, 1097 },
1098 { PINMUX_CFG_REG("PMCR", 0xffe70016, 16, 2) { 1098 { PINMUX_CFG_REG("PMCR", 0xffe70016, 16, 2, GROUP(
1099 0, 0, 0, 0, 1099 0, 0, 0, 0,
1100 0, 0, 0, 0, 1100 0, 0, 0, 0,
1101 0, 0, 0, 0, 1101 0, 0, 0, 0,
@@ -1103,9 +1103,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1103 0, 0, 0, 0, 1103 0, 0, 0, 0,
1104 0, 0, 0, 0, 1104 0, 0, 0, 0,
1105 PM1_FN, PM1_OUT, PM1_IN, 0, 1105 PM1_FN, PM1_OUT, PM1_IN, 0,
1106 PM0_FN, PM0_OUT, PM0_IN, 0 } 1106 PM0_FN, PM0_OUT, PM0_IN, 0 ))
1107 }, 1107 },
1108 { PINMUX_CFG_REG("PNCR", 0xffe70018, 16, 2) { 1108 { PINMUX_CFG_REG("PNCR", 0xffe70018, 16, 2, GROUP(
1109 PN7_FN, PN7_OUT, PN7_IN, 0, 1109 PN7_FN, PN7_OUT, PN7_IN, 0,
1110 PN6_FN, PN6_OUT, PN6_IN, 0, 1110 PN6_FN, PN6_OUT, PN6_IN, 0,
1111 PN5_FN, PN5_OUT, PN5_IN, 0, 1111 PN5_FN, PN5_OUT, PN5_IN, 0,
@@ -1113,9 +1113,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1113 PN3_FN, PN3_OUT, PN3_IN, 0, 1113 PN3_FN, PN3_OUT, PN3_IN, 0,
1114 PN2_FN, PN2_OUT, PN2_IN, 0, 1114 PN2_FN, PN2_OUT, PN2_IN, 0,
1115 PN1_FN, PN1_OUT, PN1_IN, 0, 1115 PN1_FN, PN1_OUT, PN1_IN, 0,
1116 PN0_FN, PN0_OUT, PN0_IN, 0 } 1116 PN0_FN, PN0_OUT, PN0_IN, 0 ))
1117 }, 1117 },
1118 { PINMUX_CFG_REG("PPCR", 0xffe7001a, 16, 2) { 1118 { PINMUX_CFG_REG("PPCR", 0xffe7001a, 16, 2, GROUP(
1119 0, 0, 0, 0, 1119 0, 0, 0, 0,
1120 0, 0, 0, 0, 1120 0, 0, 0, 0,
1121 PP5_FN, PP5_OUT, PP5_IN, 0, 1121 PP5_FN, PP5_OUT, PP5_IN, 0,
@@ -1123,9 +1123,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1123 PP3_FN, PP3_OUT, PP3_IN, 0, 1123 PP3_FN, PP3_OUT, PP3_IN, 0,
1124 PP2_FN, PP2_OUT, PP2_IN, 0, 1124 PP2_FN, PP2_OUT, PP2_IN, 0,
1125 PP1_FN, PP1_OUT, PP1_IN, 0, 1125 PP1_FN, PP1_OUT, PP1_IN, 0,
1126 PP0_FN, PP0_OUT, PP0_IN, 0 } 1126 PP0_FN, PP0_OUT, PP0_IN, 0 ))
1127 }, 1127 },
1128 { PINMUX_CFG_REG("PQCR", 0xffe7001c, 16, 2) { 1128 { PINMUX_CFG_REG("PQCR", 0xffe7001c, 16, 2, GROUP(
1129 0, 0, 0, 0, 1129 0, 0, 0, 0,
1130 0, 0, 0, 0, 1130 0, 0, 0, 0,
1131 0, 0, 0, 0, 1131 0, 0, 0, 0,
@@ -1133,9 +1133,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1133 PQ3_FN, PQ3_OUT, PQ3_IN, 0, 1133 PQ3_FN, PQ3_OUT, PQ3_IN, 0,
1134 PQ2_FN, PQ2_OUT, PQ2_IN, 0, 1134 PQ2_FN, PQ2_OUT, PQ2_IN, 0,
1135 PQ1_FN, PQ1_OUT, PQ1_IN, 0, 1135 PQ1_FN, PQ1_OUT, PQ1_IN, 0,
1136 PQ0_FN, PQ0_OUT, PQ0_IN, 0 } 1136 PQ0_FN, PQ0_OUT, PQ0_IN, 0 ))
1137 }, 1137 },
1138 { PINMUX_CFG_REG("PRCR", 0xffe7001e, 16, 2) { 1138 { PINMUX_CFG_REG("PRCR", 0xffe7001e, 16, 2, GROUP(
1139 0, 0, 0, 0, 1139 0, 0, 0, 0,
1140 0, 0, 0, 0, 1140 0, 0, 0, 0,
1141 0, 0, 0, 0, 1141 0, 0, 0, 0,
@@ -1143,9 +1143,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1143 PR3_FN, PR3_OUT, PR3_IN, 0, 1143 PR3_FN, PR3_OUT, PR3_IN, 0,
1144 PR2_FN, PR2_OUT, PR2_IN, 0, 1144 PR2_FN, PR2_OUT, PR2_IN, 0,
1145 PR1_FN, PR1_OUT, PR1_IN, 0, 1145 PR1_FN, PR1_OUT, PR1_IN, 0,
1146 PR0_FN, PR0_OUT, PR0_IN, 0 } 1146 PR0_FN, PR0_OUT, PR0_IN, 0 ))
1147 }, 1147 },
1148 { PINMUX_CFG_REG("P1MSELR", 0xffe70080, 16, 1) { 1148 { PINMUX_CFG_REG("P1MSELR", 0xffe70080, 16, 1, GROUP(
1149 P1MSEL15_0, P1MSEL15_1, 1149 P1MSEL15_0, P1MSEL15_1,
1150 P1MSEL14_0, P1MSEL14_1, 1150 P1MSEL14_0, P1MSEL14_1,
1151 P1MSEL13_0, P1MSEL13_1, 1151 P1MSEL13_0, P1MSEL13_1,
@@ -1161,9 +1161,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1161 P1MSEL3_0, P1MSEL3_1, 1161 P1MSEL3_0, P1MSEL3_1,
1162 P1MSEL2_0, P1MSEL2_1, 1162 P1MSEL2_0, P1MSEL2_1,
1163 P1MSEL1_0, P1MSEL1_1, 1163 P1MSEL1_0, P1MSEL1_1,
1164 P1MSEL0_0, P1MSEL0_1 } 1164 P1MSEL0_0, P1MSEL0_1 ))
1165 }, 1165 },
1166 { PINMUX_CFG_REG("P2MSELR", 0xffe70082, 16, 1) { 1166 { PINMUX_CFG_REG("P2MSELR", 0xffe70082, 16, 1, GROUP(
1167 0, 0, 1167 0, 0,
1168 0, 0, 1168 0, 0,
1169 0, 0, 1169 0, 0,
@@ -1179,75 +1179,75 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1179 0, 0, 1179 0, 0,
1180 P2MSEL2_0, P2MSEL2_1, 1180 P2MSEL2_0, P2MSEL2_1,
1181 P2MSEL1_0, P2MSEL1_1, 1181 P2MSEL1_0, P2MSEL1_1,
1182 P2MSEL0_0, P2MSEL0_1 } 1182 P2MSEL0_0, P2MSEL0_1 ))
1183 }, 1183 },
1184 {} 1184 {}
1185}; 1185};
1186 1186
1187static const struct pinmux_data_reg pinmux_data_regs[] = { 1187static const struct pinmux_data_reg pinmux_data_regs[] = {
1188 { PINMUX_DATA_REG("PADR", 0xffe70020, 8) { 1188 { PINMUX_DATA_REG("PADR", 0xffe70020, 8, GROUP(
1189 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, 1189 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
1190 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA } 1190 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA ))
1191 }, 1191 },
1192 { PINMUX_DATA_REG("PBDR", 0xffe70022, 8) { 1192 { PINMUX_DATA_REG("PBDR", 0xffe70022, 8, GROUP(
1193 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, 1193 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
1194 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA } 1194 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA ))
1195 }, 1195 },
1196 { PINMUX_DATA_REG("PCDR", 0xffe70024, 8) { 1196 { PINMUX_DATA_REG("PCDR", 0xffe70024, 8, GROUP(
1197 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, 1197 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
1198 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA } 1198 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
1199 }, 1199 },
1200 { PINMUX_DATA_REG("PDDR", 0xffe70026, 8) { 1200 { PINMUX_DATA_REG("PDDR", 0xffe70026, 8, GROUP(
1201 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, 1201 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
1202 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA } 1202 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
1203 }, 1203 },
1204 { PINMUX_DATA_REG("PEDR", 0xffe70028, 8) { 1204 { PINMUX_DATA_REG("PEDR", 0xffe70028, 8, GROUP(
1205 0, 0, PE5_DATA, PE4_DATA, 1205 0, 0, PE5_DATA, PE4_DATA,
1206 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA } 1206 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA ))
1207 }, 1207 },
1208 { PINMUX_DATA_REG("PFDR", 0xffe7002a, 8) { 1208 { PINMUX_DATA_REG("PFDR", 0xffe7002a, 8, GROUP(
1209 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, 1209 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
1210 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA } 1210 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
1211 }, 1211 },
1212 { PINMUX_DATA_REG("PGDR", 0xffe7002c, 8) { 1212 { PINMUX_DATA_REG("PGDR", 0xffe7002c, 8, GROUP(
1213 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA, 1213 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
1214 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA } 1214 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA ))
1215 }, 1215 },
1216 { PINMUX_DATA_REG("PHDR", 0xffe7002e, 8) { 1216 { PINMUX_DATA_REG("PHDR", 0xffe7002e, 8, GROUP(
1217 PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA, 1217 PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
1218 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA } 1218 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA ))
1219 }, 1219 },
1220 { PINMUX_DATA_REG("PJDR", 0xffe70030, 8) { 1220 { PINMUX_DATA_REG("PJDR", 0xffe70030, 8, GROUP(
1221 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA, 1221 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
1222 PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA } 1222 PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA ))
1223 }, 1223 },
1224 { PINMUX_DATA_REG("PKDR", 0xffe70032, 8) { 1224 { PINMUX_DATA_REG("PKDR", 0xffe70032, 8, GROUP(
1225 PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA, 1225 PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
1226 PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA } 1226 PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA ))
1227 }, 1227 },
1228 { PINMUX_DATA_REG("PLDR", 0xffe70034, 8) { 1228 { PINMUX_DATA_REG("PLDR", 0xffe70034, 8, GROUP(
1229 PL7_DATA, PL6_DATA, PL5_DATA, PL4_DATA, 1229 PL7_DATA, PL6_DATA, PL5_DATA, PL4_DATA,
1230 PL3_DATA, PL2_DATA, PL1_DATA, PL0_DATA } 1230 PL3_DATA, PL2_DATA, PL1_DATA, PL0_DATA ))
1231 }, 1231 },
1232 { PINMUX_DATA_REG("PMDR", 0xffe70036, 8) { 1232 { PINMUX_DATA_REG("PMDR", 0xffe70036, 8, GROUP(
1233 0, 0, 0, 0, 1233 0, 0, 0, 0,
1234 0, 0, PM1_DATA, PM0_DATA } 1234 0, 0, PM1_DATA, PM0_DATA ))
1235 }, 1235 },
1236 { PINMUX_DATA_REG("PNDR", 0xffe70038, 8) { 1236 { PINMUX_DATA_REG("PNDR", 0xffe70038, 8, GROUP(
1237 PN7_DATA, PN6_DATA, PN5_DATA, PN4_DATA, 1237 PN7_DATA, PN6_DATA, PN5_DATA, PN4_DATA,
1238 PN3_DATA, PN2_DATA, PN1_DATA, PN0_DATA } 1238 PN3_DATA, PN2_DATA, PN1_DATA, PN0_DATA ))
1239 }, 1239 },
1240 { PINMUX_DATA_REG("PPDR", 0xffe7003a, 8) { 1240 { PINMUX_DATA_REG("PPDR", 0xffe7003a, 8, GROUP(
1241 0, 0, PP5_DATA, PP4_DATA, 1241 0, 0, PP5_DATA, PP4_DATA,
1242 PP3_DATA, PP2_DATA, PP1_DATA, PP0_DATA } 1242 PP3_DATA, PP2_DATA, PP1_DATA, PP0_DATA ))
1243 }, 1243 },
1244 { PINMUX_DATA_REG("PQDR", 0xffe7003c, 8) { 1244 { PINMUX_DATA_REG("PQDR", 0xffe7003c, 8, GROUP(
1245 0, 0, 0, PQ4_DATA, 1245 0, 0, 0, PQ4_DATA,
1246 PQ3_DATA, PQ2_DATA, PQ1_DATA, PQ0_DATA } 1246 PQ3_DATA, PQ2_DATA, PQ1_DATA, PQ0_DATA ))
1247 }, 1247 },
1248 { PINMUX_DATA_REG("PRDR", 0xffe7003e, 8) { 1248 { PINMUX_DATA_REG("PRDR", 0xffe7003e, 8, GROUP(
1249 0, 0, 0, 0, 1249 0, 0, 0, 0,
1250 PR3_DATA, PR2_DATA, PR1_DATA, PR0_DATA } 1250 PR3_DATA, PR2_DATA, PR1_DATA, PR0_DATA ))
1251 }, 1251 },
1252 { }, 1252 { },
1253}; 1253};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
index cc2657c4f85c..b8a098cd7721 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
@@ -627,7 +627,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
627}; 627};
628 628
629static const struct pinmux_cfg_reg pinmux_config_regs[] = { 629static const struct pinmux_cfg_reg pinmux_config_regs[] = {
630 { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) { 630 { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2, GROUP(
631 PA7_FN, PA7_OUT, PA7_IN, 0, 631 PA7_FN, PA7_OUT, PA7_IN, 0,
632 PA6_FN, PA6_OUT, PA6_IN, 0, 632 PA6_FN, PA6_OUT, PA6_IN, 0,
633 PA5_FN, PA5_OUT, PA5_IN, 0, 633 PA5_FN, PA5_OUT, PA5_IN, 0,
@@ -635,9 +635,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
635 PA3_FN, PA3_OUT, PA3_IN, 0, 635 PA3_FN, PA3_OUT, PA3_IN, 0,
636 PA2_FN, PA2_OUT, PA2_IN, 0, 636 PA2_FN, PA2_OUT, PA2_IN, 0,
637 PA1_FN, PA1_OUT, PA1_IN, 0, 637 PA1_FN, PA1_OUT, PA1_IN, 0,
638 PA0_FN, PA0_OUT, PA0_IN, 0 } 638 PA0_FN, PA0_OUT, PA0_IN, 0 ))
639 }, 639 },
640 { PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2) { 640 { PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2, GROUP(
641 PB7_FN, PB7_OUT, PB7_IN, 0, 641 PB7_FN, PB7_OUT, PB7_IN, 0,
642 PB6_FN, PB6_OUT, PB6_IN, 0, 642 PB6_FN, PB6_OUT, PB6_IN, 0,
643 PB5_FN, PB5_OUT, PB5_IN, 0, 643 PB5_FN, PB5_OUT, PB5_IN, 0,
@@ -645,9 +645,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
645 PB3_FN, PB3_OUT, PB3_IN, 0, 645 PB3_FN, PB3_OUT, PB3_IN, 0,
646 PB2_FN, PB2_OUT, PB2_IN, 0, 646 PB2_FN, PB2_OUT, PB2_IN, 0,
647 PB1_FN, PB1_OUT, PB1_IN, 0, 647 PB1_FN, PB1_OUT, PB1_IN, 0,
648 PB0_FN, PB0_OUT, PB0_IN, 0 } 648 PB0_FN, PB0_OUT, PB0_IN, 0 ))
649 }, 649 },
650 { PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2) { 650 { PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2, GROUP(
651 PC7_FN, PC7_OUT, PC7_IN, 0, 651 PC7_FN, PC7_OUT, PC7_IN, 0,
652 PC6_FN, PC6_OUT, PC6_IN, 0, 652 PC6_FN, PC6_OUT, PC6_IN, 0,
653 PC5_FN, PC5_OUT, PC5_IN, 0, 653 PC5_FN, PC5_OUT, PC5_IN, 0,
@@ -655,9 +655,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
655 PC3_FN, PC3_OUT, PC3_IN, 0, 655 PC3_FN, PC3_OUT, PC3_IN, 0,
656 PC2_FN, PC2_OUT, PC2_IN, 0, 656 PC2_FN, PC2_OUT, PC2_IN, 0,
657 PC1_FN, PC1_OUT, PC1_IN, 0, 657 PC1_FN, PC1_OUT, PC1_IN, 0,
658 PC0_FN, PC0_OUT, PC0_IN, 0 } 658 PC0_FN, PC0_OUT, PC0_IN, 0 ))
659 }, 659 },
660 { PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2) { 660 { PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2, GROUP(
661 PD7_FN, PD7_OUT, PD7_IN, 0, 661 PD7_FN, PD7_OUT, PD7_IN, 0,
662 PD6_FN, PD6_OUT, PD6_IN, 0, 662 PD6_FN, PD6_OUT, PD6_IN, 0,
663 PD5_FN, PD5_OUT, PD5_IN, 0, 663 PD5_FN, PD5_OUT, PD5_IN, 0,
@@ -665,9 +665,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
665 PD3_FN, PD3_OUT, PD3_IN, 0, 665 PD3_FN, PD3_OUT, PD3_IN, 0,
666 PD2_FN, PD2_OUT, PD2_IN, 0, 666 PD2_FN, PD2_OUT, PD2_IN, 0,
667 PD1_FN, PD1_OUT, PD1_IN, 0, 667 PD1_FN, PD1_OUT, PD1_IN, 0,
668 PD0_FN, PD0_OUT, PD0_IN, 0 } 668 PD0_FN, PD0_OUT, PD0_IN, 0 ))
669 }, 669 },
670 { PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2) { 670 { PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2, GROUP(
671 PE7_FN, PE7_OUT, PE7_IN, 0, 671 PE7_FN, PE7_OUT, PE7_IN, 0,
672 PE6_FN, PE6_OUT, PE6_IN, 0, 672 PE6_FN, PE6_OUT, PE6_IN, 0,
673 0, 0, 0, 0, 673 0, 0, 0, 0,
@@ -675,9 +675,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
675 0, 0, 0, 0, 675 0, 0, 0, 0,
676 0, 0, 0, 0, 676 0, 0, 0, 0,
677 0, 0, 0, 0, 677 0, 0, 0, 0,
678 0, 0, 0, 0, } 678 0, 0, 0, 0, ))
679 }, 679 },
680 { PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2) { 680 { PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2, GROUP(
681 PF7_FN, PF7_OUT, PF7_IN, 0, 681 PF7_FN, PF7_OUT, PF7_IN, 0,
682 PF6_FN, PF6_OUT, PF6_IN, 0, 682 PF6_FN, PF6_OUT, PF6_IN, 0,
683 PF5_FN, PF5_OUT, PF5_IN, 0, 683 PF5_FN, PF5_OUT, PF5_IN, 0,
@@ -685,9 +685,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
685 PF3_FN, PF3_OUT, PF3_IN, 0, 685 PF3_FN, PF3_OUT, PF3_IN, 0,
686 PF2_FN, PF2_OUT, PF2_IN, 0, 686 PF2_FN, PF2_OUT, PF2_IN, 0,
687 PF1_FN, PF1_OUT, PF1_IN, 0, 687 PF1_FN, PF1_OUT, PF1_IN, 0,
688 PF0_FN, PF0_OUT, PF0_IN, 0 } 688 PF0_FN, PF0_OUT, PF0_IN, 0 ))
689 }, 689 },
690 { PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2) { 690 { PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2, GROUP(
691 PG7_FN, PG7_OUT, PG7_IN, 0, 691 PG7_FN, PG7_OUT, PG7_IN, 0,
692 PG6_FN, PG6_OUT, PG6_IN, 0, 692 PG6_FN, PG6_OUT, PG6_IN, 0,
693 PG5_FN, PG5_OUT, PG5_IN, 0, 693 PG5_FN, PG5_OUT, PG5_IN, 0,
@@ -695,9 +695,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
695 0, 0, 0, 0, 695 0, 0, 0, 0,
696 0, 0, 0, 0, 696 0, 0, 0, 0,
697 0, 0, 0, 0, 697 0, 0, 0, 0,
698 0, 0, 0, 0, } 698 0, 0, 0, 0, ))
699 }, 699 },
700 { PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2) { 700 { PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2, GROUP(
701 PH7_FN, PH7_OUT, PH7_IN, 0, 701 PH7_FN, PH7_OUT, PH7_IN, 0,
702 PH6_FN, PH6_OUT, PH6_IN, 0, 702 PH6_FN, PH6_OUT, PH6_IN, 0,
703 PH5_FN, PH5_OUT, PH5_IN, 0, 703 PH5_FN, PH5_OUT, PH5_IN, 0,
@@ -705,9 +705,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
705 PH3_FN, PH3_OUT, PH3_IN, 0, 705 PH3_FN, PH3_OUT, PH3_IN, 0,
706 PH2_FN, PH2_OUT, PH2_IN, 0, 706 PH2_FN, PH2_OUT, PH2_IN, 0,
707 PH1_FN, PH1_OUT, PH1_IN, 0, 707 PH1_FN, PH1_OUT, PH1_IN, 0,
708 PH0_FN, PH0_OUT, PH0_IN, 0 } 708 PH0_FN, PH0_OUT, PH0_IN, 0 ))
709 }, 709 },
710 { PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2) { 710 { PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2, GROUP(
711 PJ7_FN, PJ7_OUT, PJ7_IN, 0, 711 PJ7_FN, PJ7_OUT, PJ7_IN, 0,
712 PJ6_FN, PJ6_OUT, PJ6_IN, 0, 712 PJ6_FN, PJ6_OUT, PJ6_IN, 0,
713 PJ5_FN, PJ5_OUT, PJ5_IN, 0, 713 PJ5_FN, PJ5_OUT, PJ5_IN, 0,
@@ -715,9 +715,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
715 PJ3_FN, PJ3_OUT, PJ3_IN, 0, 715 PJ3_FN, PJ3_OUT, PJ3_IN, 0,
716 PJ2_FN, PJ2_OUT, PJ2_IN, 0, 716 PJ2_FN, PJ2_OUT, PJ2_IN, 0,
717 PJ1_FN, PJ1_OUT, PJ1_IN, 0, 717 PJ1_FN, PJ1_OUT, PJ1_IN, 0,
718 0, 0, 0, 0, } 718 0, 0, 0, 0, ))
719 }, 719 },
720 { PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1) { 720 { PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1, GROUP(
721 0, 0, 721 0, 0,
722 P1MSEL14_0, P1MSEL14_1, 722 P1MSEL14_0, P1MSEL14_1,
723 P1MSEL13_0, P1MSEL13_1, 723 P1MSEL13_0, P1MSEL13_1,
@@ -733,9 +733,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
733 P1MSEL3_0, P1MSEL3_1, 733 P1MSEL3_0, P1MSEL3_1,
734 P1MSEL2_0, P1MSEL2_1, 734 P1MSEL2_0, P1MSEL2_1,
735 P1MSEL1_0, P1MSEL1_1, 735 P1MSEL1_0, P1MSEL1_1,
736 P1MSEL0_0, P1MSEL0_1 } 736 P1MSEL0_0, P1MSEL0_1 ))
737 }, 737 },
738 { PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1) { 738 { PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1, GROUP(
739 P2MSEL15_0, P2MSEL15_1, 739 P2MSEL15_0, P2MSEL15_1,
740 P2MSEL14_0, P2MSEL14_1, 740 P2MSEL14_0, P2MSEL14_1,
741 P2MSEL13_0, P2MSEL13_1, 741 P2MSEL13_0, P2MSEL13_1,
@@ -751,47 +751,47 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
751 P2MSEL3_0, P2MSEL3_1, 751 P2MSEL3_0, P2MSEL3_1,
752 P2MSEL2_0, P2MSEL2_1, 752 P2MSEL2_0, P2MSEL2_1,
753 P2MSEL1_0, P2MSEL1_1, 753 P2MSEL1_0, P2MSEL1_1,
754 P2MSEL0_0, P2MSEL0_1 } 754 P2MSEL0_0, P2MSEL0_1 ))
755 }, 755 },
756 {} 756 {}
757}; 757};
758 758
759static const struct pinmux_data_reg pinmux_data_regs[] = { 759static const struct pinmux_data_reg pinmux_data_regs[] = {
760 { PINMUX_DATA_REG("PADR", 0xffcc0020, 8) { 760 { PINMUX_DATA_REG("PADR", 0xffcc0020, 8, GROUP(
761 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, 761 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
762 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA } 762 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA ))
763 }, 763 },
764 { PINMUX_DATA_REG("PBDR", 0xffcc0022, 8) { 764 { PINMUX_DATA_REG("PBDR", 0xffcc0022, 8, GROUP(
765 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, 765 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
766 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA } 766 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA ))
767 }, 767 },
768 { PINMUX_DATA_REG("PCDR", 0xffcc0024, 8) { 768 { PINMUX_DATA_REG("PCDR", 0xffcc0024, 8, GROUP(
769 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, 769 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
770 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA } 770 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
771 }, 771 },
772 { PINMUX_DATA_REG("PDDR", 0xffcc0026, 8) { 772 { PINMUX_DATA_REG("PDDR", 0xffcc0026, 8, GROUP(
773 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, 773 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
774 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA } 774 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
775 }, 775 },
776 { PINMUX_DATA_REG("PEDR", 0xffcc0028, 8) { 776 { PINMUX_DATA_REG("PEDR", 0xffcc0028, 8, GROUP(
777 PE7_DATA, PE6_DATA, 777 PE7_DATA, PE6_DATA,
778 0, 0, 0, 0, 0, 0 } 778 0, 0, 0, 0, 0, 0 ))
779 }, 779 },
780 { PINMUX_DATA_REG("PFDR", 0xffcc002a, 8) { 780 { PINMUX_DATA_REG("PFDR", 0xffcc002a, 8, GROUP(
781 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, 781 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
782 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA } 782 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
783 }, 783 },
784 { PINMUX_DATA_REG("PGDR", 0xffcc002c, 8) { 784 { PINMUX_DATA_REG("PGDR", 0xffcc002c, 8, GROUP(
785 PG7_DATA, PG6_DATA, PG5_DATA, 0, 785 PG7_DATA, PG6_DATA, PG5_DATA, 0,
786 0, 0, 0, 0 } 786 0, 0, 0, 0 ))
787 }, 787 },
788 { PINMUX_DATA_REG("PHDR", 0xffcc002e, 8) { 788 { PINMUX_DATA_REG("PHDR", 0xffcc002e, 8, GROUP(
789 PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA, 789 PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
790 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA } 790 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA ))
791 }, 791 },
792 { PINMUX_DATA_REG("PJDR", 0xffcc0030, 8) { 792 { PINMUX_DATA_REG("PJDR", 0xffcc0030, 8, GROUP(
793 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA, 793 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
794 PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 } 794 PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 ))
795 }, 795 },
796 { }, 796 { },
797}; 797};
diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c
index 905ae00cc6f1..22e812850964 100644
--- a/drivers/pinctrl/sh-pfc/pfc-shx3.c
+++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c
@@ -431,7 +431,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
431}; 431};
432 432
433static const struct pinmux_cfg_reg pinmux_config_regs[] = { 433static const struct pinmux_cfg_reg pinmux_config_regs[] = {
434 { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) { 434 { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2, GROUP(
435 PA7_FN, PA7_OUT, PA7_IN, 0, 435 PA7_FN, PA7_OUT, PA7_IN, 0,
436 PA6_FN, PA6_OUT, PA6_IN, 0, 436 PA6_FN, PA6_OUT, PA6_IN, 0,
437 PA5_FN, PA5_OUT, PA5_IN, 0, 437 PA5_FN, PA5_OUT, PA5_IN, 0,
@@ -447,9 +447,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
447 PB3_FN, PB3_OUT, PB3_IN, 0, 447 PB3_FN, PB3_OUT, PB3_IN, 0,
448 PB2_FN, PB2_OUT, PB2_IN, 0, 448 PB2_FN, PB2_OUT, PB2_IN, 0,
449 PB1_FN, PB1_OUT, PB1_IN, 0, 449 PB1_FN, PB1_OUT, PB1_IN, 0,
450 PB0_FN, PB0_OUT, PB0_IN, 0, }, 450 PB0_FN, PB0_OUT, PB0_IN, 0, ))
451 }, 451 },
452 { PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2) { 452 { PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2, GROUP(
453 PC7_FN, PC7_OUT, PC7_IN, 0, 453 PC7_FN, PC7_OUT, PC7_IN, 0,
454 PC6_FN, PC6_OUT, PC6_IN, 0, 454 PC6_FN, PC6_OUT, PC6_IN, 0,
455 PC5_FN, PC5_OUT, PC5_IN, 0, 455 PC5_FN, PC5_OUT, PC5_IN, 0,
@@ -465,9 +465,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
465 PD3_FN, PD3_OUT, PD3_IN, 0, 465 PD3_FN, PD3_OUT, PD3_IN, 0,
466 PD2_FN, PD2_OUT, PD2_IN, 0, 466 PD2_FN, PD2_OUT, PD2_IN, 0,
467 PD1_FN, PD1_OUT, PD1_IN, 0, 467 PD1_FN, PD1_OUT, PD1_IN, 0,
468 PD0_FN, PD0_OUT, PD0_IN, 0, }, 468 PD0_FN, PD0_OUT, PD0_IN, 0, ))
469 }, 469 },
470 { PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2) { 470 { PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2, GROUP(
471 PE7_FN, PE7_OUT, PE7_IN, 0, 471 PE7_FN, PE7_OUT, PE7_IN, 0,
472 PE6_FN, PE6_OUT, PE6_IN, 0, 472 PE6_FN, PE6_OUT, PE6_IN, 0,
473 PE5_FN, PE5_OUT, PE5_IN, 0, 473 PE5_FN, PE5_OUT, PE5_IN, 0,
@@ -483,9 +483,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
483 PF3_FN, PF3_OUT, PF3_IN, 0, 483 PF3_FN, PF3_OUT, PF3_IN, 0,
484 PF2_FN, PF2_OUT, PF2_IN, 0, 484 PF2_FN, PF2_OUT, PF2_IN, 0,
485 PF1_FN, PF1_OUT, PF1_IN, 0, 485 PF1_FN, PF1_OUT, PF1_IN, 0,
486 PF0_FN, PF0_OUT, PF0_IN, 0, }, 486 PF0_FN, PF0_OUT, PF0_IN, 0, ))
487 }, 487 },
488 { PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2) { 488 { PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2, GROUP(
489 PG7_FN, PG7_OUT, PG7_IN, 0, 489 PG7_FN, PG7_OUT, PG7_IN, 0,
490 PG6_FN, PG6_OUT, PG6_IN, 0, 490 PG6_FN, PG6_OUT, PG6_IN, 0,
491 PG5_FN, PG5_OUT, PG5_IN, 0, 491 PG5_FN, PG5_OUT, PG5_IN, 0,
@@ -501,43 +501,43 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
501 PH3_FN, PH3_OUT, PH3_IN, 0, 501 PH3_FN, PH3_OUT, PH3_IN, 0,
502 PH2_FN, PH2_OUT, PH2_IN, 0, 502 PH2_FN, PH2_OUT, PH2_IN, 0,
503 PH1_FN, PH1_OUT, PH1_IN, 0, 503 PH1_FN, PH1_OUT, PH1_IN, 0,
504 PH0_FN, PH0_OUT, PH0_IN, 0, }, 504 PH0_FN, PH0_OUT, PH0_IN, 0, ))
505 }, 505 },
506 { }, 506 { },
507}; 507};
508 508
509static const struct pinmux_data_reg pinmux_data_regs[] = { 509static const struct pinmux_data_reg pinmux_data_regs[] = {
510 { PINMUX_DATA_REG("PABDR", 0xffc70010, 32) { 510 { PINMUX_DATA_REG("PABDR", 0xffc70010, 32, GROUP(
511 0, 0, 0, 0, 0, 0, 0, 0, 511 0, 0, 0, 0, 0, 0, 0, 0,
512 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, 512 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
513 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA, 513 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
514 0, 0, 0, 0, 0, 0, 0, 0, 514 0, 0, 0, 0, 0, 0, 0, 0,
515 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, 515 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
516 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, }, 516 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, ))
517 }, 517 },
518 { PINMUX_DATA_REG("PCDDR", 0xffc70014, 32) { 518 { PINMUX_DATA_REG("PCDDR", 0xffc70014, 32, GROUP(
519 0, 0, 0, 0, 0, 0, 0, 0, 519 0, 0, 0, 0, 0, 0, 0, 0,
520 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, 520 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
521 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA, 521 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
522 0, 0, 0, 0, 0, 0, 0, 0, 522 0, 0, 0, 0, 0, 0, 0, 0,
523 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, 523 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
524 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, }, 524 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, ))
525 }, 525 },
526 { PINMUX_DATA_REG("PEFDR", 0xffc70018, 32) { 526 { PINMUX_DATA_REG("PEFDR", 0xffc70018, 32, GROUP(
527 0, 0, 0, 0, 0, 0, 0, 0, 527 0, 0, 0, 0, 0, 0, 0, 0,
528 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA, 528 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
529 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA, 529 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
530 0, 0, 0, 0, 0, 0, 0, 0, 530 0, 0, 0, 0, 0, 0, 0, 0,
531 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, 531 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
532 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, }, 532 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, ))
533 }, 533 },
534 { PINMUX_DATA_REG("PGHDR", 0xffc7001c, 32) { 534 { PINMUX_DATA_REG("PGHDR", 0xffc7001c, 32, GROUP(
535 0, 0, 0, 0, 0, 0, 0, 0, 535 0, 0, 0, 0, 0, 0, 0, 0,
536 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA, 536 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
537 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA, 537 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
538 0, 0, 0, 0, 0, 0, 0, 0, 538 0, 0, 0, 0, 0, 0, 0, 0,
539 0, 0, PH5_DATA, PH4_DATA, 539 0, 0, PH5_DATA, PH4_DATA,
540 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, }, 540 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, ))
541 }, 541 },
542 { }, 542 { },
543}; 543};
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 56016cb76769..7db5819eea7e 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -111,40 +111,54 @@ struct pinmux_func {
111struct pinmux_cfg_reg { 111struct pinmux_cfg_reg {
112 u32 reg; 112 u32 reg;
113 u8 reg_width, field_width; 113 u8 reg_width, field_width;
114#ifdef DEBUG
115 u16 nr_enum_ids; /* for variable width regs only */
116#define SET_NR_ENUM_IDS(n) .nr_enum_ids = n,
117#else
118#define SET_NR_ENUM_IDS(n)
119#endif
114 const u16 *enum_ids; 120 const u16 *enum_ids;
115 const u8 *var_field_width; 121 const u8 *var_field_width;
116}; 122};
117 123
124#define GROUP(...) __VA_ARGS__
125
118/* 126/*
119 * Describe a config register consisting of several fields of the same width 127 * Describe a config register consisting of several fields of the same width
120 * - name: Register name (unused, for documentation purposes only) 128 * - name: Register name (unused, for documentation purposes only)
121 * - r: Physical register address 129 * - r: Physical register address
122 * - r_width: Width of the register (in bits) 130 * - r_width: Width of the register (in bits)
123 * - f_width: Width of the fixed-width register fields (in bits) 131 * - f_width: Width of the fixed-width register fields (in bits)
124 * This macro must be followed by initialization data: For each register field 132 * - ids: For each register field (from left to right, i.e. MSB to LSB),
125 * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified, 133 * 2^f_width enum IDs must be specified, one for each possible
126 * one for each possible combination of the register field bit values. 134 * combination of the register field bit values, all wrapped using
135 * the GROUP() macro.
127 */ 136 */
128#define PINMUX_CFG_REG(name, r, r_width, f_width) \ 137#define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \
129 .reg = r, .reg_width = r_width, \ 138 .reg = r, .reg_width = r_width, \
130 .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width), \ 139 .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \
131 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) 140 BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
141 (r_width / f_width) * (1 << f_width)), \
142 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \
143 { ids }
132 144
133/* 145/*
134 * Describe a config register consisting of several fields of different widths 146 * Describe a config register consisting of several fields of different widths
135 * - name: Register name (unused, for documentation purposes only) 147 * - name: Register name (unused, for documentation purposes only)
136 * - r: Physical register address 148 * - r: Physical register address
137 * - r_width: Width of the register (in bits) 149 * - r_width: Width of the register (in bits)
138 * - var_fw0, var_fwn...: List of widths of the register fields (in bits), 150 * - f_widths: List of widths of the register fields (in bits), from left
139 * From left to right (i.e. MSB to LSB) 151 * to right (i.e. MSB to LSB), wrapped using the GROUP() macro.
140 * This macro must be followed by initialization data: For each register field 152 * - ids: For each register field (from left to right, i.e. MSB to LSB),
141 * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified, 153 * 2^f_widths[i] enum IDs must be specified, one for each possible
142 * one for each possible combination of the register field bit values. 154 * combination of the register field bit values, all wrapped using
155 * the GROUP() macro.
143 */ 156 */
144#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ 157#define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \
145 .reg = r, .reg_width = r_width, \ 158 .reg = r, .reg_width = r_width, \
146 .var_field_width = (const u8 []) { var_fw0, var_fwn, 0 }, \ 159 .var_field_width = (const u8 []) { f_widths, 0 }, \
147 .enum_ids = (const u16 []) 160 SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \
161 .enum_ids = (const u16 []) { ids }
148 162
149struct pinmux_drive_reg_field { 163struct pinmux_drive_reg_field {
150 u16 pin; 164 u16 pin;
@@ -187,12 +201,14 @@ struct pinmux_data_reg {
187 * - name: Register name (unused, for documentation purposes only) 201 * - name: Register name (unused, for documentation purposes only)
188 * - r: Physical register address 202 * - r: Physical register address
189 * - r_width: Width of the register (in bits) 203 * - r_width: Width of the register (in bits)
190 * This macro must be followed by initialization data: For each register bit 204 * - ids: For each register bit (from left to right, i.e. MSB to LSB), one
191 * (from left to right, i.e. MSB to LSB), one enum ID must be specified. 205 * enum ID must be specified, all wrapped using the GROUP() macro.
192 */ 206 */
193#define PINMUX_DATA_REG(name, r, r_width) \ 207#define PINMUX_DATA_REG(name, r, r_width, ids) \
194 .reg = r, .reg_width = r_width, \ 208 .reg = r, .reg_width = r_width + \
195 .enum_ids = (const u16 [r_width]) \ 209 BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
210 r_width), \
211 .enum_ids = (const u16 [r_width]) { ids }
196 212
197struct pinmux_irq { 213struct pinmux_irq {
198 const short *gpios; 214 const short *gpios;
@@ -261,7 +277,7 @@ struct sh_pfc_soc_info {
261 const struct sh_pfc_function *functions; 277 const struct sh_pfc_function *functions;
262 unsigned int nr_functions; 278 unsigned int nr_functions;
263 279
264#ifdef CONFIG_SUPERH 280#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
265 const struct pinmux_func *func_gpios; 281 const struct pinmux_func *func_gpios;
266 unsigned int nr_func_gpios; 282 unsigned int nr_func_gpios;
267#endif 283#endif
@@ -402,8 +418,8 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
402/* 418/*
403 * Describe a pinmux configuration in which a pin is physically multiplexed 419 * Describe a pinmux configuration in which a pin is physically multiplexed
404 * with other pins. 420 * with other pins.
405 * - ipsr: IPSR field 421 * - ipsr: IPSR field (unused, for documentation purposes only)
406 * - fn: Function name, also referring to the IPSR field 422 * - fn: Function name
407 * - psel: Physical multiplexing selector 423 * - psel: Physical multiplexing selector
408 */ 424 */
409#define PINMUX_IPSR_PHYS(ipsr, fn, psel) \ 425#define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
@@ -663,7 +679,9 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
663 */ 679 */
664#define PORTCR(nr, reg) \ 680#define PORTCR(nr, reg) \
665 { \ 681 { \
666 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\ 682 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \
683 GROUP(2, 2, 1, 3), \
684 GROUP( \
667 /* PULMD[1:0], handled by .set_bias() */ \ 685 /* PULMD[1:0], handled by .set_bias() */ \
668 0, 0, 0, 0, \ 686 0, 0, 0, 0, \
669 /* IE and OE */ \ 687 /* IE and OE */ \
@@ -675,7 +693,7 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
675 PORT##nr##_FN2, PORT##nr##_FN3, \ 693 PORT##nr##_FN2, PORT##nr##_FN3, \
676 PORT##nr##_FN4, PORT##nr##_FN5, \ 694 PORT##nr##_FN4, PORT##nr##_FN5, \
677 PORT##nr##_FN6, PORT##nr##_FN7 \ 695 PORT##nr##_FN6, PORT##nr##_FN7 \
678 } \ 696 )) \
679 } 697 }
680 698
681/* 699/*
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 0b9ff5aa6bb5..2317ccf63321 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -95,6 +95,9 @@ struct stm32_pinctrl {
95 struct regmap *regmap; 95 struct regmap *regmap;
96 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK]; 96 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
97 struct hwspinlock *hwlock; 97 struct hwspinlock *hwlock;
98 struct stm32_desc_pin *pins;
99 u32 npins;
100 u32 pkg;
98}; 101};
99 102
100static inline int stm32_gpio_pin(int gpio) 103static inline int stm32_gpio_pin(int gpio)
@@ -358,8 +361,8 @@ static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
358{ 361{
359 int i; 362 int i;
360 363
361 for (i = 0; i < pctl->match_data->npins; i++) { 364 for (i = 0; i < pctl->npins; i++) {
362 const struct stm32_desc_pin *pin = pctl->match_data->pins + i; 365 const struct stm32_desc_pin *pin = pctl->pins + i;
363 const struct stm32_desc_function *func = pin->functions; 366 const struct stm32_desc_function *func = pin->functions;
364 367
365 if (pin->pin.number != pin_num) 368 if (pin->pin.number != pin_num)
@@ -1119,23 +1122,35 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
1119 return 0; 1122 return 0;
1120} 1123}
1121 1124
1125static struct irq_domain *stm32_pctrl_get_irq_domain(struct device_node *np)
1126{
1127 struct device_node *parent;
1128 struct irq_domain *domain;
1129
1130 if (!of_find_property(np, "interrupt-parent", NULL))
1131 return NULL;
1132
1133 parent = of_irq_find_parent(np);
1134 if (!parent)
1135 return ERR_PTR(-ENXIO);
1136
1137 domain = irq_find_host(parent);
1138 if (!domain)
1139 /* domain not registered yet */
1140 return ERR_PTR(-EPROBE_DEFER);
1141
1142 return domain;
1143}
1144
1122static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, 1145static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1123 struct stm32_pinctrl *pctl) 1146 struct stm32_pinctrl *pctl)
1124{ 1147{
1125 struct device_node *np = pdev->dev.of_node, *parent; 1148 struct device_node *np = pdev->dev.of_node;
1126 struct device *dev = &pdev->dev; 1149 struct device *dev = &pdev->dev;
1127 struct regmap *rm; 1150 struct regmap *rm;
1128 int offset, ret, i; 1151 int offset, ret, i;
1129 int mask, mask_width; 1152 int mask, mask_width;
1130 1153
1131 parent = of_irq_find_parent(np);
1132 if (!parent)
1133 return -ENXIO;
1134
1135 pctl->domain = irq_find_host(parent);
1136 if (!pctl->domain)
1137 return -ENXIO;
1138
1139 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1154 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1140 if (IS_ERR(pctl->regmap)) 1155 if (IS_ERR(pctl->regmap))
1141 return PTR_ERR(pctl->regmap); 1156 return PTR_ERR(pctl->regmap);
@@ -1175,7 +1190,7 @@ static int stm32_pctrl_build_state(struct platform_device *pdev)
1175 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); 1190 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1176 int i; 1191 int i;
1177 1192
1178 pctl->ngroups = pctl->match_data->npins; 1193 pctl->ngroups = pctl->npins;
1179 1194
1180 /* Allocate groups */ 1195 /* Allocate groups */
1181 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, 1196 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
@@ -1189,19 +1204,50 @@ static int stm32_pctrl_build_state(struct platform_device *pdev)
1189 if (!pctl->grp_names) 1204 if (!pctl->grp_names)
1190 return -ENOMEM; 1205 return -ENOMEM;
1191 1206
1192 for (i = 0; i < pctl->match_data->npins; i++) { 1207 for (i = 0; i < pctl->npins; i++) {
1193 const struct stm32_desc_pin *pin = pctl->match_data->pins + i; 1208 const struct stm32_desc_pin *pin = pctl->pins + i;
1194 struct stm32_pinctrl_group *group = pctl->groups + i; 1209 struct stm32_pinctrl_group *group = pctl->groups + i;
1195 1210
1196 group->name = pin->pin.name; 1211 group->name = pin->pin.name;
1197 group->pin = pin->pin.number; 1212 group->pin = pin->pin.number;
1198
1199 pctl->grp_names[i] = pin->pin.name; 1213 pctl->grp_names[i] = pin->pin.name;
1200 } 1214 }
1201 1215
1202 return 0; 1216 return 0;
1203} 1217}
1204 1218
1219static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
1220 struct stm32_desc_pin *pins)
1221{
1222 const struct stm32_desc_pin *p;
1223 int i, nb_pins_available = 0;
1224
1225 for (i = 0; i < pctl->match_data->npins; i++) {
1226 p = pctl->match_data->pins + i;
1227 if (pctl->pkg && !(pctl->pkg & p->pkg))
1228 continue;
1229 pins->pin = p->pin;
1230 pins->functions = p->functions;
1231 pins++;
1232 nb_pins_available++;
1233 }
1234
1235 pctl->npins = nb_pins_available;
1236
1237 return 0;
1238}
1239
1240static void stm32_pctl_get_package(struct device_node *np,
1241 struct stm32_pinctrl *pctl)
1242{
1243 if (of_property_read_u32(np, "st,package", &pctl->pkg)) {
1244 pctl->pkg = 0;
1245 dev_warn(pctl->dev, "No package detected, use default one\n");
1246 } else {
1247 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
1248 }
1249}
1250
1205int stm32_pctl_probe(struct platform_device *pdev) 1251int stm32_pctl_probe(struct platform_device *pdev)
1206{ 1252{
1207 struct device_node *np = pdev->dev.of_node; 1253 struct device_node *np = pdev->dev.of_node;
@@ -1230,6 +1276,11 @@ int stm32_pctl_probe(struct platform_device *pdev)
1230 1276
1231 platform_set_drvdata(pdev, pctl); 1277 platform_set_drvdata(pdev, pctl);
1232 1278
1279 /* check for IRQ controller (may require deferred probe) */
1280 pctl->domain = stm32_pctrl_get_irq_domain(np);
1281 if (IS_ERR(pctl->domain))
1282 return PTR_ERR(pctl->domain);
1283
1233 /* hwspinlock is optional */ 1284 /* hwspinlock is optional */
1234 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); 1285 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
1235 if (hwlock_id < 0) { 1286 if (hwlock_id < 0) {
@@ -1241,30 +1292,43 @@ int stm32_pctl_probe(struct platform_device *pdev)
1241 1292
1242 pctl->dev = dev; 1293 pctl->dev = dev;
1243 pctl->match_data = match->data; 1294 pctl->match_data = match->data;
1295
1296 /* get package information */
1297 stm32_pctl_get_package(np, pctl);
1298
1299 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
1300 sizeof(*pctl->pins), GFP_KERNEL);
1301 if (!pctl->pins)
1302 return -ENOMEM;
1303
1304 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
1305 if (ret)
1306 return ret;
1307
1244 ret = stm32_pctrl_build_state(pdev); 1308 ret = stm32_pctrl_build_state(pdev);
1245 if (ret) { 1309 if (ret) {
1246 dev_err(dev, "build state failed: %d\n", ret); 1310 dev_err(dev, "build state failed: %d\n", ret);
1247 return -EINVAL; 1311 return -EINVAL;
1248 } 1312 }
1249 1313
1250 if (of_find_property(np, "interrupt-parent", NULL)) { 1314 if (pctl->domain) {
1251 ret = stm32_pctrl_dt_setup_irq(pdev, pctl); 1315 ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1252 if (ret) 1316 if (ret)
1253 return ret; 1317 return ret;
1254 } 1318 }
1255 1319
1256 pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins), 1320 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
1257 GFP_KERNEL); 1321 GFP_KERNEL);
1258 if (!pins) 1322 if (!pins)
1259 return -ENOMEM; 1323 return -ENOMEM;
1260 1324
1261 for (i = 0; i < pctl->match_data->npins; i++) 1325 for (i = 0; i < pctl->npins; i++)
1262 pins[i] = pctl->match_data->pins[i].pin; 1326 pins[i] = pctl->pins[i].pin;
1263 1327
1264 pctl->pctl_desc.name = dev_name(&pdev->dev); 1328 pctl->pctl_desc.name = dev_name(&pdev->dev);
1265 pctl->pctl_desc.owner = THIS_MODULE; 1329 pctl->pctl_desc.owner = THIS_MODULE;
1266 pctl->pctl_desc.pins = pins; 1330 pctl->pctl_desc.pins = pins;
1267 pctl->pctl_desc.npins = pctl->match_data->npins; 1331 pctl->pctl_desc.npins = pctl->npins;
1268 pctl->pctl_desc.confops = &stm32_pconf_ops; 1332 pctl->pctl_desc.confops = &stm32_pconf_ops;
1269 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; 1333 pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1270 pctl->pctl_desc.pmxops = &stm32_pmx_ops; 1334 pctl->pctl_desc.pmxops = &stm32_pmx_ops;
@@ -1305,4 +1369,3 @@ int stm32_pctl_probe(struct platform_device *pdev)
1305 1369
1306 return 0; 1370 return 0;
1307} 1371}
1308
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h
index 473a6238a27b..de5e7012ca03 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.h
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.h
@@ -18,6 +18,12 @@
18#define STM32_PIN_AF(x) ((x) + 1) 18#define STM32_PIN_AF(x) ((x) + 1)
19#define STM32_PIN_ANALOG (STM32_PIN_AF(15) + 1) 19#define STM32_PIN_ANALOG (STM32_PIN_AF(15) + 1)
20 20
21/* package information */
22#define STM32MP_PKG_AA BIT(0)
23#define STM32MP_PKG_AB BIT(1)
24#define STM32MP_PKG_AC BIT(2)
25#define STM32MP_PKG_AD BIT(3)
26
21struct stm32_desc_function { 27struct stm32_desc_function {
22 const char *name; 28 const char *name;
23 const unsigned char num; 29 const unsigned char num;
@@ -26,6 +32,7 @@ struct stm32_desc_function {
26struct stm32_desc_pin { 32struct stm32_desc_pin {
27 struct pinctrl_pin_desc pin; 33 struct pinctrl_pin_desc pin;
28 const struct stm32_desc_function *functions; 34 const struct stm32_desc_function *functions;
35 const unsigned int pkg;
29}; 36};
30 37
31#define STM32_PIN(_pin, ...) \ 38#define STM32_PIN(_pin, ...) \
@@ -35,6 +42,13 @@ struct stm32_desc_pin {
35 __VA_ARGS__, { } }, \ 42 __VA_ARGS__, { } }, \
36 } 43 }
37 44
45#define STM32_PIN_PKG(_pin, _pkg, ...) \
46 { \
47 .pin = _pin, \
48 .pkg = _pkg, \
49 .functions = (struct stm32_desc_function[]){ \
50 __VA_ARGS__, { } }, \
51 }
38#define STM32_FUNCTION(_num, _name) \ 52#define STM32_FUNCTION(_num, _name) \
39 { \ 53 { \
40 .num = _num, \ 54 .num = _num, \
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32mp157.c b/drivers/pinctrl/stm32/pinctrl-stm32mp157.c
index 7c7d6284b23c..320544f69e57 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32mp157.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32mp157.c
@@ -10,77 +10,82 @@
10#include "pinctrl-stm32.h" 10#include "pinctrl-stm32.h"
11 11
12static const struct stm32_desc_pin stm32mp157_pins[] = { 12static const struct stm32_desc_pin stm32mp157_pins[] = {
13 STM32_PIN( 13 STM32_PIN_PKG(
14 PINCTRL_PIN(0, "PA0"), 14 PINCTRL_PIN(0, "PA0"),
15 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
15 STM32_FUNCTION(0, "GPIOA0"), 16 STM32_FUNCTION(0, "GPIOA0"),
16 STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"), 17 STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
17 STM32_FUNCTION(3, "TIM5_CH1"), 18 STM32_FUNCTION(3, "TIM5_CH1"),
18 STM32_FUNCTION(4, "TIM8_ETR"), 19 STM32_FUNCTION(4, "TIM8_ETR"),
19 STM32_FUNCTION(5, "TIM15_BKIN"), 20 STM32_FUNCTION(5, "TIM15_BKIN"),
20 STM32_FUNCTION(8, "USART2_CTS_NSS USART_BOOT2_CTS_NSS"), 21 STM32_FUNCTION(8, "USART2_CTS USART2_NSS"),
21 STM32_FUNCTION(9, "UART4_TX"), 22 STM32_FUNCTION(9, "UART4_TX"),
22 STM32_FUNCTION(10, "SDMMC2_CMD"), 23 STM32_FUNCTION(10, "SDMMC2_CMD"),
23 STM32_FUNCTION(11, "SAI2_SD_B"), 24 STM32_FUNCTION(11, "SAI2_SD_B"),
24 STM32_FUNCTION(12, "ETH_GMII_CRS ETH_MII_CRS"), 25 STM32_FUNCTION(12, "ETH1_GMII_CRS ETH1_MII_CRS"),
25 STM32_FUNCTION(16, "EVENTOUT"), 26 STM32_FUNCTION(16, "EVENTOUT"),
26 STM32_FUNCTION(17, "ANALOG") 27 STM32_FUNCTION(17, "ANALOG")
27 ), 28 ),
28 STM32_PIN( 29 STM32_PIN_PKG(
29 PINCTRL_PIN(1, "PA1"), 30 PINCTRL_PIN(1, "PA1"),
31 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
30 STM32_FUNCTION(0, "GPIOA1"), 32 STM32_FUNCTION(0, "GPIOA1"),
31 STM32_FUNCTION(1, "ETH_CLK"), 33 STM32_FUNCTION(1, "ETH_CLK"),
32 STM32_FUNCTION(2, "TIM2_CH2"), 34 STM32_FUNCTION(2, "TIM2_CH2"),
33 STM32_FUNCTION(3, "TIM5_CH2"), 35 STM32_FUNCTION(3, "TIM5_CH2"),
34 STM32_FUNCTION(4, "LPTIM3_OUT"), 36 STM32_FUNCTION(4, "LPTIM3_OUT"),
35 STM32_FUNCTION(5, "TIM15_CH1N"), 37 STM32_FUNCTION(5, "TIM15_CH1N"),
36 STM32_FUNCTION(8, "USART2_RTS USART_BOOT2_RTS"), 38 STM32_FUNCTION(8, "USART2_RTS USART2_DE"),
37 STM32_FUNCTION(9, "UART4_RX"), 39 STM32_FUNCTION(9, "UART4_RX"),
38 STM32_FUNCTION(10, "QUADSPI_BK1_IO3 QUADSPI_BOOTBK1_IO3"), 40 STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
39 STM32_FUNCTION(11, "SAI2_MCLK_B"), 41 STM32_FUNCTION(11, "SAI2_MCLK_B"),
40 STM32_FUNCTION(12, "ETH_GMII_RX_CLK ETH_MII_RX_CLK ETH_RGMII_RX_CLK ETH_RMII_REF_CLK"), 42 STM32_FUNCTION(12, "ETH1_GMII_RX_CLK ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"),
41 STM32_FUNCTION(15, "LCD_R2"), 43 STM32_FUNCTION(15, "LCD_R2"),
42 STM32_FUNCTION(16, "EVENTOUT"), 44 STM32_FUNCTION(16, "EVENTOUT"),
43 STM32_FUNCTION(17, "ANALOG") 45 STM32_FUNCTION(17, "ANALOG")
44 ), 46 ),
45 STM32_PIN( 47 STM32_PIN_PKG(
46 PINCTRL_PIN(2, "PA2"), 48 PINCTRL_PIN(2, "PA2"),
49 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
47 STM32_FUNCTION(0, "GPIOA2"), 50 STM32_FUNCTION(0, "GPIOA2"),
48 STM32_FUNCTION(2, "TIM2_CH3"), 51 STM32_FUNCTION(2, "TIM2_CH3"),
49 STM32_FUNCTION(3, "TIM5_CH3"), 52 STM32_FUNCTION(3, "TIM5_CH3"),
50 STM32_FUNCTION(4, "LPTIM4_OUT"), 53 STM32_FUNCTION(4, "LPTIM4_OUT"),
51 STM32_FUNCTION(5, "TIM15_CH1"), 54 STM32_FUNCTION(5, "TIM15_CH1"),
52 STM32_FUNCTION(8, "USART2_TX USART_BOOT2_TX"), 55 STM32_FUNCTION(8, "USART2_TX"),
53 STM32_FUNCTION(9, "SAI2_SCK_B"), 56 STM32_FUNCTION(9, "SAI2_SCK_B"),
54 STM32_FUNCTION(11, "SDMMC2_D0DIR SDMMC_BOOT2_D0DIR"), 57 STM32_FUNCTION(11, "SDMMC2_D0DIR"),
55 STM32_FUNCTION(12, "ETH_MDIO"), 58 STM32_FUNCTION(12, "ETH1_MDIO"),
56 STM32_FUNCTION(13, "MDIOS_MDIO"), 59 STM32_FUNCTION(13, "MDIOS_MDIO"),
57 STM32_FUNCTION(15, "LCD_R1"), 60 STM32_FUNCTION(15, "LCD_R1"),
58 STM32_FUNCTION(16, "EVENTOUT"), 61 STM32_FUNCTION(16, "EVENTOUT"),
59 STM32_FUNCTION(17, "ANALOG") 62 STM32_FUNCTION(17, "ANALOG")
60 ), 63 ),
61 STM32_PIN( 64 STM32_PIN_PKG(
62 PINCTRL_PIN(3, "PA3"), 65 PINCTRL_PIN(3, "PA3"),
66 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
63 STM32_FUNCTION(0, "GPIOA3"), 67 STM32_FUNCTION(0, "GPIOA3"),
64 STM32_FUNCTION(2, "TIM2_CH4"), 68 STM32_FUNCTION(2, "TIM2_CH4"),
65 STM32_FUNCTION(3, "TIM5_CH4"), 69 STM32_FUNCTION(3, "TIM5_CH4"),
66 STM32_FUNCTION(4, "LPTIM5_OUT"), 70 STM32_FUNCTION(4, "LPTIM5_OUT"),
67 STM32_FUNCTION(5, "TIM15_CH2"), 71 STM32_FUNCTION(5, "TIM15_CH2"),
68 STM32_FUNCTION(8, "USART2_RX USART_BOOT2_RX"), 72 STM32_FUNCTION(8, "USART2_RX"),
69 STM32_FUNCTION(10, "LCD_B2"), 73 STM32_FUNCTION(10, "LCD_B2"),
70 STM32_FUNCTION(12, "ETH_GMII_COL ETH_MII_COL"), 74 STM32_FUNCTION(12, "ETH1_GMII_COL ETH1_MII_COL"),
71 STM32_FUNCTION(15, "LCD_B5"), 75 STM32_FUNCTION(15, "LCD_B5"),
72 STM32_FUNCTION(16, "EVENTOUT"), 76 STM32_FUNCTION(16, "EVENTOUT"),
73 STM32_FUNCTION(17, "ANALOG") 77 STM32_FUNCTION(17, "ANALOG")
74 ), 78 ),
75 STM32_PIN( 79 STM32_PIN_PKG(
76 PINCTRL_PIN(4, "PA4"), 80 PINCTRL_PIN(4, "PA4"),
81 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
77 STM32_FUNCTION(0, "GPIOA4"), 82 STM32_FUNCTION(0, "GPIOA4"),
78 STM32_FUNCTION(1, "HDP0"), 83 STM32_FUNCTION(1, "HDP0"),
79 STM32_FUNCTION(3, "TIM5_ETR"), 84 STM32_FUNCTION(3, "TIM5_ETR"),
80 STM32_FUNCTION(5, "SAI4_D2"), 85 STM32_FUNCTION(5, "SAI4_D2"),
81 STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"), 86 STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
82 STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"), 87 STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
83 STM32_FUNCTION(8, "USART2_CK USART_BOOT2_CK"), 88 STM32_FUNCTION(8, "USART2_CK"),
84 STM32_FUNCTION(9, "SPI6_NSS"), 89 STM32_FUNCTION(9, "SPI6_NSS"),
85 STM32_FUNCTION(13, "SAI4_FS_A"), 90 STM32_FUNCTION(13, "SAI4_FS_A"),
86 STM32_FUNCTION(14, "DCMI_HSYNC"), 91 STM32_FUNCTION(14, "DCMI_HSYNC"),
@@ -88,8 +93,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
88 STM32_FUNCTION(16, "EVENTOUT"), 93 STM32_FUNCTION(16, "EVENTOUT"),
89 STM32_FUNCTION(17, "ANALOG") 94 STM32_FUNCTION(17, "ANALOG")
90 ), 95 ),
91 STM32_PIN( 96 STM32_PIN_PKG(
92 PINCTRL_PIN(5, "PA5"), 97 PINCTRL_PIN(5, "PA5"),
98 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
93 STM32_FUNCTION(0, "GPIOA5"), 99 STM32_FUNCTION(0, "GPIOA5"),
94 STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"), 100 STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
95 STM32_FUNCTION(4, "TIM8_CH1N"), 101 STM32_FUNCTION(4, "TIM8_CH1N"),
@@ -101,8 +107,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
101 STM32_FUNCTION(16, "EVENTOUT"), 107 STM32_FUNCTION(16, "EVENTOUT"),
102 STM32_FUNCTION(17, "ANALOG") 108 STM32_FUNCTION(17, "ANALOG")
103 ), 109 ),
104 STM32_PIN( 110 STM32_PIN_PKG(
105 PINCTRL_PIN(6, "PA6"), 111 PINCTRL_PIN(6, "PA6"),
112 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
106 STM32_FUNCTION(0, "GPIOA6"), 113 STM32_FUNCTION(0, "GPIOA6"),
107 STM32_FUNCTION(2, "TIM1_BKIN"), 114 STM32_FUNCTION(2, "TIM1_BKIN"),
108 STM32_FUNCTION(3, "TIM3_CH1"), 115 STM32_FUNCTION(3, "TIM3_CH1"),
@@ -118,8 +125,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
118 STM32_FUNCTION(16, "EVENTOUT"), 125 STM32_FUNCTION(16, "EVENTOUT"),
119 STM32_FUNCTION(17, "ANALOG") 126 STM32_FUNCTION(17, "ANALOG")
120 ), 127 ),
121 STM32_PIN( 128 STM32_PIN_PKG(
122 PINCTRL_PIN(7, "PA7"), 129 PINCTRL_PIN(7, "PA7"),
130 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
123 STM32_FUNCTION(0, "GPIOA7"), 131 STM32_FUNCTION(0, "GPIOA7"),
124 STM32_FUNCTION(2, "TIM1_CH1N"), 132 STM32_FUNCTION(2, "TIM1_CH1N"),
125 STM32_FUNCTION(3, "TIM3_CH2"), 133 STM32_FUNCTION(3, "TIM3_CH2"),
@@ -129,13 +137,14 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
129 STM32_FUNCTION(9, "SPI6_MOSI"), 137 STM32_FUNCTION(9, "SPI6_MOSI"),
130 STM32_FUNCTION(10, "TIM14_CH1"), 138 STM32_FUNCTION(10, "TIM14_CH1"),
131 STM32_FUNCTION(11, "QUADSPI_CLK"), 139 STM32_FUNCTION(11, "QUADSPI_CLK"),
132 STM32_FUNCTION(12, "ETH_GMII_RX_DV ETH_MII_RX_DV ETH_RGMII_RX_CTL ETH_RMII_CRS_DV"), 140 STM32_FUNCTION(12, "ETH1_GMII_RX_DV ETH1_MII_RX_DV ETH1_RGMII_RX_CTL ETH1_RMII_CRS_DV"),
133 STM32_FUNCTION(13, "SAI4_SD_A"), 141 STM32_FUNCTION(13, "SAI4_SD_A"),
134 STM32_FUNCTION(16, "EVENTOUT"), 142 STM32_FUNCTION(16, "EVENTOUT"),
135 STM32_FUNCTION(17, "ANALOG") 143 STM32_FUNCTION(17, "ANALOG")
136 ), 144 ),
137 STM32_PIN( 145 STM32_PIN_PKG(
138 PINCTRL_PIN(8, "PA8"), 146 PINCTRL_PIN(8, "PA8"),
147 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
139 STM32_FUNCTION(0, "GPIOA8"), 148 STM32_FUNCTION(0, "GPIOA8"),
140 STM32_FUNCTION(1, "MCO1"), 149 STM32_FUNCTION(1, "MCO1"),
141 STM32_FUNCTION(2, "TIM1_CH1"), 150 STM32_FUNCTION(2, "TIM1_CH1"),
@@ -143,37 +152,37 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
143 STM32_FUNCTION(5, "I2C3_SCL"), 152 STM32_FUNCTION(5, "I2C3_SCL"),
144 STM32_FUNCTION(6, "SPI3_MOSI I2S3_SDO"), 153 STM32_FUNCTION(6, "SPI3_MOSI I2S3_SDO"),
145 STM32_FUNCTION(8, "USART1_CK"), 154 STM32_FUNCTION(8, "USART1_CK"),
146 STM32_FUNCTION(9, "SDMMC2_CKIN SDMMC_BOOT2_CKIN"), 155 STM32_FUNCTION(9, "SDMMC2_CKIN"),
147 STM32_FUNCTION(10, "SDMMC2_D4 SDMMC_BOOT2_D4"), 156 STM32_FUNCTION(10, "SDMMC2_D4"),
148 STM32_FUNCTION(11, "USBO_SOF"), 157 STM32_FUNCTION(11, "OTG_FS_SOF OTG_HS_SOF"),
149 STM32_FUNCTION(13, "SAI4_SD_B"), 158 STM32_FUNCTION(13, "SAI4_SD_B"),
150 STM32_FUNCTION(14, "UART7_RX"), 159 STM32_FUNCTION(14, "UART7_RX"),
151 STM32_FUNCTION(15, "LCD_R6"), 160 STM32_FUNCTION(15, "LCD_R6"),
152 STM32_FUNCTION(16, "EVENTOUT"), 161 STM32_FUNCTION(16, "EVENTOUT"),
153 STM32_FUNCTION(17, "ANALOG") 162 STM32_FUNCTION(17, "ANALOG")
154 ), 163 ),
155 STM32_PIN( 164 STM32_PIN_PKG(
156 PINCTRL_PIN(9, "PA9"), 165 PINCTRL_PIN(9, "PA9"),
166 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
157 STM32_FUNCTION(0, "GPIOA9"), 167 STM32_FUNCTION(0, "GPIOA9"),
158 STM32_FUNCTION(2, "TIM1_CH2"), 168 STM32_FUNCTION(2, "TIM1_CH2"),
159 STM32_FUNCTION(5, "I2C3_SMBA"), 169 STM32_FUNCTION(5, "I2C3_SMBA"),
160 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), 170 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
161 STM32_FUNCTION(8, "USART1_TX"), 171 STM32_FUNCTION(8, "USART1_TX"),
162 STM32_FUNCTION(9, "SDMMC2_CDIR SDMMC_BOOT2_CDIR"), 172 STM32_FUNCTION(9, "SDMMC2_CDIR"),
163 STM32_FUNCTION(10, "CAN1_RXFD"), 173 STM32_FUNCTION(11, "SDMMC2_D5"),
164 STM32_FUNCTION(11, "SDMMC2_D5 SDMMC_BOOT2_D5"),
165 STM32_FUNCTION(14, "DCMI_D0"), 174 STM32_FUNCTION(14, "DCMI_D0"),
166 STM32_FUNCTION(15, "LCD_R5"), 175 STM32_FUNCTION(15, "LCD_R5"),
167 STM32_FUNCTION(16, "EVENTOUT"), 176 STM32_FUNCTION(16, "EVENTOUT"),
168 STM32_FUNCTION(17, "ANALOG") 177 STM32_FUNCTION(17, "ANALOG")
169 ), 178 ),
170 STM32_PIN( 179 STM32_PIN_PKG(
171 PINCTRL_PIN(10, "PA10"), 180 PINCTRL_PIN(10, "PA10"),
181 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
172 STM32_FUNCTION(0, "GPIOA10"), 182 STM32_FUNCTION(0, "GPIOA10"),
173 STM32_FUNCTION(2, "TIM1_CH3"), 183 STM32_FUNCTION(2, "TIM1_CH3"),
174 STM32_FUNCTION(6, "SPI3_NSS I2S3_WS"), 184 STM32_FUNCTION(6, "SPI3_NSS I2S3_WS"),
175 STM32_FUNCTION(8, "USART1_RX"), 185 STM32_FUNCTION(8, "USART1_RX"),
176 STM32_FUNCTION(10, "CAN1_TXFD"),
177 STM32_FUNCTION(12, "MDIOS_MDIO"), 186 STM32_FUNCTION(12, "MDIOS_MDIO"),
178 STM32_FUNCTION(13, "SAI4_FS_B"), 187 STM32_FUNCTION(13, "SAI4_FS_B"),
179 STM32_FUNCTION(14, "DCMI_D1"), 188 STM32_FUNCTION(14, "DCMI_D1"),
@@ -181,37 +190,39 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
181 STM32_FUNCTION(16, "EVENTOUT"), 190 STM32_FUNCTION(16, "EVENTOUT"),
182 STM32_FUNCTION(17, "ANALOG") 191 STM32_FUNCTION(17, "ANALOG")
183 ), 192 ),
184 STM32_PIN( 193 STM32_PIN_PKG(
185 PINCTRL_PIN(11, "PA11"), 194 PINCTRL_PIN(11, "PA11"),
195 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
186 STM32_FUNCTION(0, "GPIOA11"), 196 STM32_FUNCTION(0, "GPIOA11"),
187 STM32_FUNCTION(2, "TIM1_CH4"), 197 STM32_FUNCTION(2, "TIM1_CH4"),
188 STM32_FUNCTION(3, "I2C6_SCL"), 198 STM32_FUNCTION(3, "I2C6_SCL"),
189 STM32_FUNCTION(5, "I2C5_SCL"), 199 STM32_FUNCTION(5, "I2C5_SCL"),
190 STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"), 200 STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
191 STM32_FUNCTION(7, "UART4_RX"), 201 STM32_FUNCTION(7, "UART4_RX"),
192 STM32_FUNCTION(8, "USART1_CTS_NSS"), 202 STM32_FUNCTION(8, "USART1_CTS USART1_NSS"),
193 STM32_FUNCTION(10, "CAN1_RX"), 203 STM32_FUNCTION(10, "FDCAN1_RX"),
194 STM32_FUNCTION(15, "LCD_R4"), 204 STM32_FUNCTION(15, "LCD_R4"),
195 STM32_FUNCTION(16, "EVENTOUT"), 205 STM32_FUNCTION(16, "EVENTOUT"),
196 STM32_FUNCTION(17, "ANALOG") 206 STM32_FUNCTION(17, "ANALOG")
197 ), 207 ),
198 STM32_PIN( 208 STM32_PIN_PKG(
199 PINCTRL_PIN(12, "PA12"), 209 PINCTRL_PIN(12, "PA12"),
210 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
200 STM32_FUNCTION(0, "GPIOA12"), 211 STM32_FUNCTION(0, "GPIOA12"),
201 STM32_FUNCTION(2, "TIM1_ETR"), 212 STM32_FUNCTION(2, "TIM1_ETR"),
202 STM32_FUNCTION(3, "I2C6_SDA"), 213 STM32_FUNCTION(3, "I2C6_SDA"),
203 STM32_FUNCTION(5, "I2C5_SDA"), 214 STM32_FUNCTION(5, "I2C5_SDA"),
204 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
205 STM32_FUNCTION(7, "UART4_TX"), 215 STM32_FUNCTION(7, "UART4_TX"),
206 STM32_FUNCTION(8, "USART1_RTS"), 216 STM32_FUNCTION(8, "USART1_RTS USART1_DE"),
207 STM32_FUNCTION(9, "SAI2_FS_B"), 217 STM32_FUNCTION(9, "SAI2_FS_B"),
208 STM32_FUNCTION(10, "CAN1_TX"), 218 STM32_FUNCTION(10, "FDCAN1_TX"),
209 STM32_FUNCTION(15, "LCD_R5"), 219 STM32_FUNCTION(15, "LCD_R5"),
210 STM32_FUNCTION(16, "EVENTOUT"), 220 STM32_FUNCTION(16, "EVENTOUT"),
211 STM32_FUNCTION(17, "ANALOG") 221 STM32_FUNCTION(17, "ANALOG")
212 ), 222 ),
213 STM32_PIN( 223 STM32_PIN_PKG(
214 PINCTRL_PIN(13, "PA13"), 224 PINCTRL_PIN(13, "PA13"),
225 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
215 STM32_FUNCTION(0, "GPIOA13"), 226 STM32_FUNCTION(0, "GPIOA13"),
216 STM32_FUNCTION(1, "DBTRGO"), 227 STM32_FUNCTION(1, "DBTRGO"),
217 STM32_FUNCTION(2, "DBTRGI"), 228 STM32_FUNCTION(2, "DBTRGI"),
@@ -220,8 +231,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
220 STM32_FUNCTION(16, "EVENTOUT"), 231 STM32_FUNCTION(16, "EVENTOUT"),
221 STM32_FUNCTION(17, "ANALOG") 232 STM32_FUNCTION(17, "ANALOG")
222 ), 233 ),
223 STM32_PIN( 234 STM32_PIN_PKG(
224 PINCTRL_PIN(14, "PA14"), 235 PINCTRL_PIN(14, "PA14"),
236 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
225 STM32_FUNCTION(0, "GPIOA14"), 237 STM32_FUNCTION(0, "GPIOA14"),
226 STM32_FUNCTION(1, "DBTRGO"), 238 STM32_FUNCTION(1, "DBTRGO"),
227 STM32_FUNCTION(2, "DBTRGI"), 239 STM32_FUNCTION(2, "DBTRGI"),
@@ -229,73 +241,79 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
229 STM32_FUNCTION(16, "EVENTOUT"), 241 STM32_FUNCTION(16, "EVENTOUT"),
230 STM32_FUNCTION(17, "ANALOG") 242 STM32_FUNCTION(17, "ANALOG")
231 ), 243 ),
232 STM32_PIN( 244 STM32_PIN_PKG(
233 PINCTRL_PIN(15, "PA15"), 245 PINCTRL_PIN(15, "PA15"),
246 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
234 STM32_FUNCTION(0, "GPIOA15"), 247 STM32_FUNCTION(0, "GPIOA15"),
235 STM32_FUNCTION(1, "DBTRGI"), 248 STM32_FUNCTION(1, "DBTRGI"),
236 STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"), 249 STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
237 STM32_FUNCTION(3, "SAI4_D2"), 250 STM32_FUNCTION(3, "SAI4_D2"),
238 STM32_FUNCTION(4, "SDMMC1_CDIR"), 251 STM32_FUNCTION(4, "SDMMC1_CDIR"),
239 STM32_FUNCTION(5, "HDMI_CEC"), 252 STM32_FUNCTION(5, "CEC"),
240 STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"), 253 STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
241 STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"), 254 STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
242 STM32_FUNCTION(8, "SPI6_NSS"), 255 STM32_FUNCTION(8, "SPI6_NSS"),
243 STM32_FUNCTION(9, "UART4_RTS UART_BOOT4_RTS"), 256 STM32_FUNCTION(9, "UART4_RTS UART4_DE"),
244 STM32_FUNCTION(10, "SDMMC2_D5 SDMMC_BOOT2_D5"), 257 STM32_FUNCTION(10, "SDMMC2_D5"),
245 STM32_FUNCTION(11, "SDMMC2_CDIR SDMMC_BOOT2_CDIR"), 258 STM32_FUNCTION(11, "SDMMC2_CDIR"),
246 STM32_FUNCTION(12, "SDMMC1_D5 SDMMC_BOOT1_D5"), 259 STM32_FUNCTION(12, "SDMMC1_D5"),
247 STM32_FUNCTION(13, "SAI4_FS_A"), 260 STM32_FUNCTION(13, "SAI4_FS_A"),
248 STM32_FUNCTION(14, "UART7_TX"), 261 STM32_FUNCTION(14, "UART7_TX"),
262 STM32_FUNCTION(15, "LCD_R1"),
249 STM32_FUNCTION(16, "EVENTOUT"), 263 STM32_FUNCTION(16, "EVENTOUT"),
250 STM32_FUNCTION(17, "ANALOG") 264 STM32_FUNCTION(17, "ANALOG")
251 ), 265 ),
252 STM32_PIN( 266 STM32_PIN_PKG(
253 PINCTRL_PIN(16, "PB0"), 267 PINCTRL_PIN(16, "PB0"),
268 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
254 STM32_FUNCTION(0, "GPIOB0"), 269 STM32_FUNCTION(0, "GPIOB0"),
255 STM32_FUNCTION(2, "TIM1_CH2N"), 270 STM32_FUNCTION(2, "TIM1_CH2N"),
256 STM32_FUNCTION(3, "TIM3_CH3"), 271 STM32_FUNCTION(3, "TIM3_CH3"),
257 STM32_FUNCTION(4, "TIM8_CH2N"), 272 STM32_FUNCTION(4, "TIM8_CH2N"),
258 STM32_FUNCTION(7, "DFSDM_CKOUT"), 273 STM32_FUNCTION(7, "DFSDM1_CKOUT"),
259 STM32_FUNCTION(9, "UART4_CTS UART_BOOT4_CTS"), 274 STM32_FUNCTION(9, "UART4_CTS"),
260 STM32_FUNCTION(10, "LCD_R3"), 275 STM32_FUNCTION(10, "LCD_R3"),
261 STM32_FUNCTION(12, "ETH_GMII_RXD2 ETH_MII_RXD2 ETH_RGMII_RXD2"), 276 STM32_FUNCTION(12, "ETH1_GMII_RXD2 ETH1_MII_RXD2 ETH1_RGMII_RXD2"),
262 STM32_FUNCTION(13, "MDIOS_MDIO"), 277 STM32_FUNCTION(13, "MDIOS_MDIO"),
263 STM32_FUNCTION(15, "LCD_G1"), 278 STM32_FUNCTION(15, "LCD_G1"),
264 STM32_FUNCTION(16, "EVENTOUT"), 279 STM32_FUNCTION(16, "EVENTOUT"),
265 STM32_FUNCTION(17, "ANALOG") 280 STM32_FUNCTION(17, "ANALOG")
266 ), 281 ),
267 STM32_PIN( 282 STM32_PIN_PKG(
268 PINCTRL_PIN(17, "PB1"), 283 PINCTRL_PIN(17, "PB1"),
284 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
269 STM32_FUNCTION(0, "GPIOB1"), 285 STM32_FUNCTION(0, "GPIOB1"),
270 STM32_FUNCTION(2, "TIM1_CH3N"), 286 STM32_FUNCTION(2, "TIM1_CH3N"),
271 STM32_FUNCTION(3, "TIM3_CH4"), 287 STM32_FUNCTION(3, "TIM3_CH4"),
272 STM32_FUNCTION(4, "TIM8_CH3N"), 288 STM32_FUNCTION(4, "TIM8_CH3N"),
273 STM32_FUNCTION(7, "DFSDM_DATA1"), 289 STM32_FUNCTION(7, "DFSDM1_DATIN1"),
274 STM32_FUNCTION(10, "LCD_R6"), 290 STM32_FUNCTION(10, "LCD_R6"),
275 STM32_FUNCTION(12, "ETH_GMII_RXD3 ETH_MII_RXD3 ETH_RGMII_RXD3"), 291 STM32_FUNCTION(12, "ETH1_GMII_RXD3 ETH1_MII_RXD3 ETH1_RGMII_RXD3"),
276 STM32_FUNCTION(13, "MDIOS_MDC"), 292 STM32_FUNCTION(13, "MDIOS_MDC"),
277 STM32_FUNCTION(15, "LCD_G0"), 293 STM32_FUNCTION(15, "LCD_G0"),
278 STM32_FUNCTION(16, "EVENTOUT"), 294 STM32_FUNCTION(16, "EVENTOUT"),
279 STM32_FUNCTION(17, "ANALOG") 295 STM32_FUNCTION(17, "ANALOG")
280 ), 296 ),
281 STM32_PIN( 297 STM32_PIN_PKG(
282 PINCTRL_PIN(18, "PB2"), 298 PINCTRL_PIN(18, "PB2"),
299 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
283 STM32_FUNCTION(0, "GPIOB2"), 300 STM32_FUNCTION(0, "GPIOB2"),
284 STM32_FUNCTION(1, "TRACED4"), 301 STM32_FUNCTION(1, "TRACED4"),
285 STM32_FUNCTION(2, "RTC_OUT2"), 302 STM32_FUNCTION(2, "RTC_OUT2"),
286 STM32_FUNCTION(3, "SAI1_D1"), 303 STM32_FUNCTION(3, "SAI1_D1"),
287 STM32_FUNCTION(4, "DFSDM_CK1"), 304 STM32_FUNCTION(4, "DFSDM1_CKIN1"),
288 STM32_FUNCTION(5, "USART1_RX"), 305 STM32_FUNCTION(5, "USART1_RX"),
289 STM32_FUNCTION(6, "I2S_CKIN"), 306 STM32_FUNCTION(6, "I2S_CKIN"),
290 STM32_FUNCTION(7, "SAI1_SD_A"), 307 STM32_FUNCTION(7, "SAI1_SD_A"),
291 STM32_FUNCTION(8, "SPI3_MOSI I2S3_SDO"), 308 STM32_FUNCTION(8, "SPI3_MOSI I2S3_SDO"),
292 STM32_FUNCTION(9, "UART4_RX UART_BOOT4_RX"), 309 STM32_FUNCTION(9, "UART4_RX"),
293 STM32_FUNCTION(10, "QUADSPI_CLK"), 310 STM32_FUNCTION(10, "QUADSPI_CLK"),
294 STM32_FUNCTION(16, "EVENTOUT"), 311 STM32_FUNCTION(16, "EVENTOUT"),
295 STM32_FUNCTION(17, "ANALOG") 312 STM32_FUNCTION(17, "ANALOG")
296 ), 313 ),
297 STM32_PIN( 314 STM32_PIN_PKG(
298 PINCTRL_PIN(19, "PB3"), 315 PINCTRL_PIN(19, "PB3"),
316 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
299 STM32_FUNCTION(0, "GPIOB3"), 317 STM32_FUNCTION(0, "GPIOB3"),
300 STM32_FUNCTION(1, "TRACED9"), 318 STM32_FUNCTION(1, "TRACED9"),
301 STM32_FUNCTION(2, "TIM2_CH2"), 319 STM32_FUNCTION(2, "TIM2_CH2"),
@@ -303,14 +321,15 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
303 STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"), 321 STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
304 STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"), 322 STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
305 STM32_FUNCTION(9, "SPI6_SCK"), 323 STM32_FUNCTION(9, "SPI6_SCK"),
306 STM32_FUNCTION(10, "SDMMC2_D2 SDMMC_BOOT2_D2"), 324 STM32_FUNCTION(10, "SDMMC2_D2"),
307 STM32_FUNCTION(13, "SAI4_MCLK_A"), 325 STM32_FUNCTION(13, "SAI4_MCLK_A"),
308 STM32_FUNCTION(14, "UART7_RX"), 326 STM32_FUNCTION(14, "UART7_RX"),
309 STM32_FUNCTION(16, "EVENTOUT"), 327 STM32_FUNCTION(16, "EVENTOUT"),
310 STM32_FUNCTION(17, "ANALOG") 328 STM32_FUNCTION(17, "ANALOG")
311 ), 329 ),
312 STM32_PIN( 330 STM32_PIN_PKG(
313 PINCTRL_PIN(20, "PB4"), 331 PINCTRL_PIN(20, "PB4"),
332 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
314 STM32_FUNCTION(0, "GPIOB4"), 333 STM32_FUNCTION(0, "GPIOB4"),
315 STM32_FUNCTION(1, "TRACED8"), 334 STM32_FUNCTION(1, "TRACED8"),
316 STM32_FUNCTION(2, "TIM16_BKIN"), 335 STM32_FUNCTION(2, "TIM16_BKIN"),
@@ -320,14 +339,15 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
320 STM32_FUNCTION(7, "SPI3_MISO I2S3_SDI"), 339 STM32_FUNCTION(7, "SPI3_MISO I2S3_SDI"),
321 STM32_FUNCTION(8, "SPI2_NSS I2S2_WS"), 340 STM32_FUNCTION(8, "SPI2_NSS I2S2_WS"),
322 STM32_FUNCTION(9, "SPI6_MISO"), 341 STM32_FUNCTION(9, "SPI6_MISO"),
323 STM32_FUNCTION(10, "SDMMC2_D3 SDMMC_BOOT2_D3"), 342 STM32_FUNCTION(10, "SDMMC2_D3"),
324 STM32_FUNCTION(13, "SAI4_SCK_A"), 343 STM32_FUNCTION(13, "SAI4_SCK_A"),
325 STM32_FUNCTION(14, "UART7_TX"), 344 STM32_FUNCTION(14, "UART7_TX"),
326 STM32_FUNCTION(16, "EVENTOUT"), 345 STM32_FUNCTION(16, "EVENTOUT"),
327 STM32_FUNCTION(17, "ANALOG") 346 STM32_FUNCTION(17, "ANALOG")
328 ), 347 ),
329 STM32_PIN( 348 STM32_PIN_PKG(
330 PINCTRL_PIN(21, "PB5"), 349 PINCTRL_PIN(21, "PB5"),
350 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
331 STM32_FUNCTION(0, "GPIOB5"), 351 STM32_FUNCTION(0, "GPIOB5"),
332 STM32_FUNCTION(1, "ETH_CLK"), 352 STM32_FUNCTION(1, "ETH_CLK"),
333 STM32_FUNCTION(2, "TIM17_BKIN"), 353 STM32_FUNCTION(2, "TIM17_BKIN"),
@@ -338,166 +358,175 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
338 STM32_FUNCTION(7, "I2C4_SMBA"), 358 STM32_FUNCTION(7, "I2C4_SMBA"),
339 STM32_FUNCTION(8, "SPI3_MOSI I2S3_SDO"), 359 STM32_FUNCTION(8, "SPI3_MOSI I2S3_SDO"),
340 STM32_FUNCTION(9, "SPI6_MOSI"), 360 STM32_FUNCTION(9, "SPI6_MOSI"),
341 STM32_FUNCTION(10, "CAN2_RX"), 361 STM32_FUNCTION(10, "FDCAN2_RX"),
342 STM32_FUNCTION(11, "SAI4_SD_A"), 362 STM32_FUNCTION(11, "SAI4_SD_A"),
343 STM32_FUNCTION(12, "ETH_PPS_OUT"), 363 STM32_FUNCTION(12, "ETH1_PPS_OUT"),
344 STM32_FUNCTION(13, "UART5_RX UART_BOOT5_RX"), 364 STM32_FUNCTION(13, "UART5_RX"),
345 STM32_FUNCTION(14, "DCMI_D10"), 365 STM32_FUNCTION(14, "DCMI_D10"),
346 STM32_FUNCTION(15, "LCD_G7"), 366 STM32_FUNCTION(15, "LCD_G7"),
347 STM32_FUNCTION(16, "EVENTOUT"), 367 STM32_FUNCTION(16, "EVENTOUT"),
348 STM32_FUNCTION(17, "ANALOG") 368 STM32_FUNCTION(17, "ANALOG")
349 ), 369 ),
350 STM32_PIN( 370 STM32_PIN_PKG(
351 PINCTRL_PIN(22, "PB6"), 371 PINCTRL_PIN(22, "PB6"),
372 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
352 STM32_FUNCTION(0, "GPIOB6"), 373 STM32_FUNCTION(0, "GPIOB6"),
353 STM32_FUNCTION(2, "TIM16_CH1N"), 374 STM32_FUNCTION(2, "TIM16_CH1N"),
354 STM32_FUNCTION(3, "TIM4_CH1"), 375 STM32_FUNCTION(3, "TIM4_CH1"),
355 STM32_FUNCTION(5, "I2C1_SCL"), 376 STM32_FUNCTION(5, "I2C1_SCL"),
356 STM32_FUNCTION(6, "HDMI_CEC"), 377 STM32_FUNCTION(6, "CEC"),
357 STM32_FUNCTION(7, "I2C4_SCL"), 378 STM32_FUNCTION(7, "I2C4_SCL"),
358 STM32_FUNCTION(8, "USART1_TX"), 379 STM32_FUNCTION(8, "USART1_TX"),
359 STM32_FUNCTION(10, "CAN2_TX"), 380 STM32_FUNCTION(10, "FDCAN2_TX"),
360 STM32_FUNCTION(11, "QUADSPI_BK1_NCS QUADSPI_BOOTBK1_NCS"), 381 STM32_FUNCTION(11, "QUADSPI_BK1_NCS"),
361 STM32_FUNCTION(12, "DFSDM_DATA5"), 382 STM32_FUNCTION(12, "DFSDM1_DATIN5"),
362 STM32_FUNCTION(13, "UART5_TX"), 383 STM32_FUNCTION(13, "UART5_TX"),
363 STM32_FUNCTION(14, "DCMI_D5"), 384 STM32_FUNCTION(14, "DCMI_D5"),
364 STM32_FUNCTION(16, "EVENTOUT"), 385 STM32_FUNCTION(16, "EVENTOUT"),
365 STM32_FUNCTION(17, "ANALOG") 386 STM32_FUNCTION(17, "ANALOG")
366 ), 387 ),
367 STM32_PIN( 388 STM32_PIN_PKG(
368 PINCTRL_PIN(23, "PB7"), 389 PINCTRL_PIN(23, "PB7"),
390 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
369 STM32_FUNCTION(0, "GPIOB7"), 391 STM32_FUNCTION(0, "GPIOB7"),
370 STM32_FUNCTION(2, "TIM17_CH1N"), 392 STM32_FUNCTION(2, "TIM17_CH1N"),
371 STM32_FUNCTION(3, "TIM4_CH2"), 393 STM32_FUNCTION(3, "TIM4_CH2"),
372 STM32_FUNCTION(5, "I2C1_SDA"), 394 STM32_FUNCTION(5, "I2C1_SDA"),
373 STM32_FUNCTION(7, "I2C4_SDA"), 395 STM32_FUNCTION(7, "I2C4_SDA"),
374 STM32_FUNCTION(8, "USART1_RX"), 396 STM32_FUNCTION(8, "USART1_RX"),
375 STM32_FUNCTION(10, "CAN2_TXFD"), 397 STM32_FUNCTION(11, "SDMMC2_D1"),
376 STM32_FUNCTION(11, "SDMMC2_D1 SDMMC_BOOT2_D1"), 398 STM32_FUNCTION(12, "DFSDM1_CKIN5"),
377 STM32_FUNCTION(12, "DFSDM_CK5"),
378 STM32_FUNCTION(13, "FMC_NL"), 399 STM32_FUNCTION(13, "FMC_NL"),
379 STM32_FUNCTION(14, "DCMI_VSYNC"), 400 STM32_FUNCTION(14, "DCMI_VSYNC"),
380 STM32_FUNCTION(16, "EVENTOUT"), 401 STM32_FUNCTION(16, "EVENTOUT"),
381 STM32_FUNCTION(17, "ANALOG") 402 STM32_FUNCTION(17, "ANALOG")
382 ), 403 ),
383 STM32_PIN( 404 STM32_PIN_PKG(
384 PINCTRL_PIN(24, "PB8"), 405 PINCTRL_PIN(24, "PB8"),
406 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
385 STM32_FUNCTION(0, "GPIOB8"), 407 STM32_FUNCTION(0, "GPIOB8"),
386 STM32_FUNCTION(1, "HDP6"), 408 STM32_FUNCTION(1, "HDP6"),
387 STM32_FUNCTION(2, "TIM16_CH1"), 409 STM32_FUNCTION(2, "TIM16_CH1"),
388 STM32_FUNCTION(3, "TIM4_CH3"), 410 STM32_FUNCTION(3, "TIM4_CH3"),
389 STM32_FUNCTION(4, "DFSDM_CK7"), 411 STM32_FUNCTION(4, "DFSDM1_CKIN7"),
390 STM32_FUNCTION(5, "I2C1_SCL"), 412 STM32_FUNCTION(5, "I2C1_SCL"),
391 STM32_FUNCTION(6, "SDMMC1_CKIN SDMMC_BOOT1_CKIN"), 413 STM32_FUNCTION(6, "SDMMC1_CKIN"),
392 STM32_FUNCTION(7, "I2C4_SCL"), 414 STM32_FUNCTION(7, "I2C4_SCL"),
393 STM32_FUNCTION(8, "SDMMC2_CKIN SDMMC_BOOT2_CKIN"), 415 STM32_FUNCTION(8, "SDMMC2_CKIN"),
394 STM32_FUNCTION(9, "UART4_RX"), 416 STM32_FUNCTION(9, "UART4_RX"),
395 STM32_FUNCTION(10, "CAN1_RX"), 417 STM32_FUNCTION(10, "FDCAN1_RX"),
396 STM32_FUNCTION(11, "SDMMC2_D4 SDMMC_BOOT2_D4"), 418 STM32_FUNCTION(11, "SDMMC2_D4"),
397 STM32_FUNCTION(12, "ETH_GMII_TXD3 ETH_MII_TXD3 ETH_RGMII_TXD3"), 419 STM32_FUNCTION(12, "ETH1_GMII_TXD3 ETH1_MII_TXD3 ETH1_RGMII_TXD3"),
398 STM32_FUNCTION(13, "SDMMC1_D4 SDMMC_BOOT1_D4"), 420 STM32_FUNCTION(13, "SDMMC1_D4"),
399 STM32_FUNCTION(14, "DCMI_D6"), 421 STM32_FUNCTION(14, "DCMI_D6"),
400 STM32_FUNCTION(15, "LCD_B6"), 422 STM32_FUNCTION(15, "LCD_B6"),
401 STM32_FUNCTION(16, "EVENTOUT"), 423 STM32_FUNCTION(16, "EVENTOUT"),
402 STM32_FUNCTION(17, "ANALOG") 424 STM32_FUNCTION(17, "ANALOG")
403 ), 425 ),
404 STM32_PIN( 426 STM32_PIN_PKG(
405 PINCTRL_PIN(25, "PB9"), 427 PINCTRL_PIN(25, "PB9"),
428 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
406 STM32_FUNCTION(0, "GPIOB9"), 429 STM32_FUNCTION(0, "GPIOB9"),
407 STM32_FUNCTION(1, "HDP7"), 430 STM32_FUNCTION(1, "HDP7"),
408 STM32_FUNCTION(2, "TIM17_CH1"), 431 STM32_FUNCTION(2, "TIM17_CH1"),
409 STM32_FUNCTION(3, "TIM4_CH4"), 432 STM32_FUNCTION(3, "TIM4_CH4"),
410 STM32_FUNCTION(4, "DFSDM_DATA7"), 433 STM32_FUNCTION(4, "DFSDM1_DATIN7"),
411 STM32_FUNCTION(5, "I2C1_SDA"), 434 STM32_FUNCTION(5, "I2C1_SDA"),
412 STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"), 435 STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
413 STM32_FUNCTION(7, "I2C4_SDA"), 436 STM32_FUNCTION(7, "I2C4_SDA"),
414 STM32_FUNCTION(8, "SDMMC2_CDIR SDMMC_BOOT2_CDIR"), 437 STM32_FUNCTION(8, "SDMMC2_CDIR"),
415 STM32_FUNCTION(9, "UART4_TX"), 438 STM32_FUNCTION(9, "UART4_TX"),
416 STM32_FUNCTION(10, "CAN1_TX"), 439 STM32_FUNCTION(10, "FDCAN1_TX"),
417 STM32_FUNCTION(11, "SDMMC2_D5 SDMMC_BOOT2_D5"), 440 STM32_FUNCTION(11, "SDMMC2_D5"),
418 STM32_FUNCTION(12, "SDMMC1_CDIR SDMMC_BOOT1_CDIR"), 441 STM32_FUNCTION(12, "SDMMC1_CDIR"),
419 STM32_FUNCTION(13, "SDMMC1_D5 SDMMC_BOOT1_D5"), 442 STM32_FUNCTION(13, "SDMMC1_D5"),
420 STM32_FUNCTION(14, "DCMI_D7"), 443 STM32_FUNCTION(14, "DCMI_D7"),
421 STM32_FUNCTION(15, "LCD_B7"), 444 STM32_FUNCTION(15, "LCD_B7"),
422 STM32_FUNCTION(16, "EVENTOUT"), 445 STM32_FUNCTION(16, "EVENTOUT"),
423 STM32_FUNCTION(17, "ANALOG") 446 STM32_FUNCTION(17, "ANALOG")
424 ), 447 ),
425 STM32_PIN( 448 STM32_PIN_PKG(
426 PINCTRL_PIN(26, "PB10"), 449 PINCTRL_PIN(26, "PB10"),
450 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
427 STM32_FUNCTION(0, "GPIOB10"), 451 STM32_FUNCTION(0, "GPIOB10"),
428 STM32_FUNCTION(2, "TIM2_CH3"), 452 STM32_FUNCTION(2, "TIM2_CH3"),
429 STM32_FUNCTION(4, "LPTIM2_IN1"), 453 STM32_FUNCTION(4, "LPTIM2_IN1"),
430 STM32_FUNCTION(5, "I2C2_SCL"), 454 STM32_FUNCTION(5, "I2C2_SCL"),
431 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), 455 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
432 STM32_FUNCTION(7, "DFSDM_DATA7"), 456 STM32_FUNCTION(7, "DFSDM1_DATIN7"),
433 STM32_FUNCTION(8, "USART3_TX USART_BOOT3_TX"), 457 STM32_FUNCTION(8, "USART3_TX"),
434 STM32_FUNCTION(10, "QUADSPI_BK1_NCS"), 458 STM32_FUNCTION(10, "QUADSPI_BK1_NCS"),
435 STM32_FUNCTION(12, "ETH_GMII_RX_ER ETH_MII_RX_ER"), 459 STM32_FUNCTION(12, "ETH1_GMII_RX_ER ETH1_MII_RX_ER"),
436 STM32_FUNCTION(15, "LCD_G4"), 460 STM32_FUNCTION(15, "LCD_G4"),
437 STM32_FUNCTION(16, "EVENTOUT"), 461 STM32_FUNCTION(16, "EVENTOUT"),
438 STM32_FUNCTION(17, "ANALOG") 462 STM32_FUNCTION(17, "ANALOG")
439 ), 463 ),
440 STM32_PIN( 464 STM32_PIN_PKG(
441 PINCTRL_PIN(27, "PB11"), 465 PINCTRL_PIN(27, "PB11"),
466 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
442 STM32_FUNCTION(0, "GPIOB11"), 467 STM32_FUNCTION(0, "GPIOB11"),
443 STM32_FUNCTION(2, "TIM2_CH4"), 468 STM32_FUNCTION(2, "TIM2_CH4"),
444 STM32_FUNCTION(4, "LPTIM2_ETR"), 469 STM32_FUNCTION(4, "LPTIM2_ETR"),
445 STM32_FUNCTION(5, "I2C2_SDA"), 470 STM32_FUNCTION(5, "I2C2_SDA"),
446 STM32_FUNCTION(7, "DFSDM_CK7"), 471 STM32_FUNCTION(7, "DFSDM1_CKIN7"),
447 STM32_FUNCTION(8, "USART3_RX"), 472 STM32_FUNCTION(8, "USART3_RX"),
448 STM32_FUNCTION(12, "ETH_GMII_TX_EN ETH_MII_TX_EN ETH_RGMII_TX_CTL ETH_RMII_TX_EN"), 473 STM32_FUNCTION(12, "ETH1_GMII_TX_EN ETH1_MII_TX_EN ETH1_RGMII_TX_CTL ETH1_RMII_TX_EN"),
449 STM32_FUNCTION(14, "DSI_TE"), 474 STM32_FUNCTION(14, "DSI_TE"),
450 STM32_FUNCTION(15, "LCD_G5"), 475 STM32_FUNCTION(15, "LCD_G5"),
451 STM32_FUNCTION(16, "EVENTOUT"), 476 STM32_FUNCTION(16, "EVENTOUT"),
452 STM32_FUNCTION(17, "ANALOG") 477 STM32_FUNCTION(17, "ANALOG")
453 ), 478 ),
454 STM32_PIN( 479 STM32_PIN_PKG(
455 PINCTRL_PIN(28, "PB12"), 480 PINCTRL_PIN(28, "PB12"),
481 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
456 STM32_FUNCTION(0, "GPIOB12"), 482 STM32_FUNCTION(0, "GPIOB12"),
457 STM32_FUNCTION(2, "TIM1_BKIN"), 483 STM32_FUNCTION(2, "TIM1_BKIN"),
458 STM32_FUNCTION(3, "I2C6_SMBA"), 484 STM32_FUNCTION(3, "I2C6_SMBA"),
459 STM32_FUNCTION(5, "I2C2_SMBA"), 485 STM32_FUNCTION(5, "I2C2_SMBA"),
460 STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"), 486 STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
461 STM32_FUNCTION(7, "DFSDM_DATA1"), 487 STM32_FUNCTION(7, "DFSDM1_DATIN1"),
462 STM32_FUNCTION(8, "USART3_CK USART_BOOT3_CK"), 488 STM32_FUNCTION(8, "USART3_CK"),
463 STM32_FUNCTION(9, "USART3_RX USART_BOOT3_RX"), 489 STM32_FUNCTION(9, "USART3_RX"),
464 STM32_FUNCTION(10, "CAN2_RX"), 490 STM32_FUNCTION(10, "FDCAN2_RX"),
465 STM32_FUNCTION(12, "ETH_GMII_TXD0 ETH_MII_TXD0 ETH_RGMII_TXD0 ETH_RMII_TXD0"), 491 STM32_FUNCTION(12, "ETH1_GMII_TXD0 ETH1_MII_TXD0 ETH1_RGMII_TXD0 ETH1_RMII_TXD0"),
466 STM32_FUNCTION(15, "UART5_RX"), 492 STM32_FUNCTION(15, "UART5_RX"),
467 STM32_FUNCTION(16, "EVENTOUT"), 493 STM32_FUNCTION(16, "EVENTOUT"),
468 STM32_FUNCTION(17, "ANALOG") 494 STM32_FUNCTION(17, "ANALOG")
469 ), 495 ),
470 STM32_PIN( 496 STM32_PIN_PKG(
471 PINCTRL_PIN(29, "PB13"), 497 PINCTRL_PIN(29, "PB13"),
498 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
472 STM32_FUNCTION(0, "GPIOB13"), 499 STM32_FUNCTION(0, "GPIOB13"),
473 STM32_FUNCTION(2, "TIM1_CH1N"), 500 STM32_FUNCTION(2, "TIM1_CH1N"),
474 STM32_FUNCTION(4, "DFSDM_CKOUT"), 501 STM32_FUNCTION(4, "DFSDM1_CKOUT"),
475 STM32_FUNCTION(5, "LPTIM2_OUT"), 502 STM32_FUNCTION(5, "LPTIM2_OUT"),
476 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), 503 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
477 STM32_FUNCTION(7, "DFSDM_CK1"), 504 STM32_FUNCTION(7, "DFSDM1_CKIN1"),
478 STM32_FUNCTION(8, "USART3_CTS_NSS USART_BOOT3_CTS_NSS"), 505 STM32_FUNCTION(8, "USART3_CTS USART3_NSS"),
479 STM32_FUNCTION(10, "CAN2_TX"), 506 STM32_FUNCTION(10, "FDCAN2_TX"),
480 STM32_FUNCTION(12, "ETH_GMII_TXD1 ETH_MII_TXD1 ETH_RGMII_TXD1 ETH_RMII_TXD1"), 507 STM32_FUNCTION(12, "ETH1_GMII_TXD1 ETH1_MII_TXD1 ETH1_RGMII_TXD1 ETH1_RMII_TXD1"),
481 STM32_FUNCTION(15, "UART5_TX UART_BOOT5_TX"), 508 STM32_FUNCTION(15, "UART5_TX"),
482 STM32_FUNCTION(16, "EVENTOUT"), 509 STM32_FUNCTION(16, "EVENTOUT"),
483 STM32_FUNCTION(17, "ANALOG") 510 STM32_FUNCTION(17, "ANALOG")
484 ), 511 ),
485 STM32_PIN( 512 STM32_PIN_PKG(
486 PINCTRL_PIN(30, "PB14"), 513 PINCTRL_PIN(30, "PB14"),
514 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
487 STM32_FUNCTION(0, "GPIOB14"), 515 STM32_FUNCTION(0, "GPIOB14"),
488 STM32_FUNCTION(2, "TIM1_CH2N"), 516 STM32_FUNCTION(2, "TIM1_CH2N"),
489 STM32_FUNCTION(3, "TIM12_CH1"), 517 STM32_FUNCTION(3, "TIM12_CH1"),
490 STM32_FUNCTION(4, "TIM8_CH2N"), 518 STM32_FUNCTION(4, "TIM8_CH2N"),
491 STM32_FUNCTION(5, "USART1_TX"), 519 STM32_FUNCTION(5, "USART1_TX"),
492 STM32_FUNCTION(6, "SPI2_MISO I2S2_SDI"), 520 STM32_FUNCTION(6, "SPI2_MISO I2S2_SDI"),
493 STM32_FUNCTION(7, "DFSDM_DATA2"), 521 STM32_FUNCTION(7, "DFSDM1_DATIN2"),
494 STM32_FUNCTION(8, "USART3_RTS USART_BOOT3_RTS"), 522 STM32_FUNCTION(8, "USART3_RTS USART3_DE"),
495 STM32_FUNCTION(10, "SDMMC2_D0 SDMMC_BOOT2_D0"), 523 STM32_FUNCTION(10, "SDMMC2_D0"),
496 STM32_FUNCTION(16, "EVENTOUT"), 524 STM32_FUNCTION(16, "EVENTOUT"),
497 STM32_FUNCTION(17, "ANALOG") 525 STM32_FUNCTION(17, "ANALOG")
498 ), 526 ),
499 STM32_PIN( 527 STM32_PIN_PKG(
500 PINCTRL_PIN(31, "PB15"), 528 PINCTRL_PIN(31, "PB15"),
529 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
501 STM32_FUNCTION(0, "GPIOB15"), 530 STM32_FUNCTION(0, "GPIOB15"),
502 STM32_FUNCTION(1, "RTC_REFIN"), 531 STM32_FUNCTION(1, "RTC_REFIN"),
503 STM32_FUNCTION(2, "TIM1_CH3N"), 532 STM32_FUNCTION(2, "TIM1_CH3N"),
@@ -505,523 +534,557 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
505 STM32_FUNCTION(4, "TIM8_CH3N"), 534 STM32_FUNCTION(4, "TIM8_CH3N"),
506 STM32_FUNCTION(5, "USART1_RX"), 535 STM32_FUNCTION(5, "USART1_RX"),
507 STM32_FUNCTION(6, "SPI2_MOSI I2S2_SDO"), 536 STM32_FUNCTION(6, "SPI2_MOSI I2S2_SDO"),
508 STM32_FUNCTION(7, "DFSDM_CK2"), 537 STM32_FUNCTION(7, "DFSDM1_CKIN2"),
509 STM32_FUNCTION(10, "SDMMC2_D1 SDMMC_BOOT2_D1"), 538 STM32_FUNCTION(10, "SDMMC2_D1"),
510 STM32_FUNCTION(16, "EVENTOUT"), 539 STM32_FUNCTION(16, "EVENTOUT"),
511 STM32_FUNCTION(17, "ANALOG") 540 STM32_FUNCTION(17, "ANALOG")
512 ), 541 ),
513 STM32_PIN( 542 STM32_PIN_PKG(
514 PINCTRL_PIN(32, "PC0"), 543 PINCTRL_PIN(32, "PC0"),
544 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
515 STM32_FUNCTION(0, "GPIOC0"), 545 STM32_FUNCTION(0, "GPIOC0"),
516 STM32_FUNCTION(4, "DFSDM_CK0"), 546 STM32_FUNCTION(4, "DFSDM1_CKIN0"),
517 STM32_FUNCTION(5, "LPTIM2_IN2"), 547 STM32_FUNCTION(5, "LPTIM2_IN2"),
518 STM32_FUNCTION(7, "DFSDM_DATA4"), 548 STM32_FUNCTION(7, "DFSDM1_DATIN4"),
519 STM32_FUNCTION(9, "SAI2_FS_B"), 549 STM32_FUNCTION(9, "SAI2_FS_B"),
520 STM32_FUNCTION(11, "QUADSPI_BK2_NCS QUADSPI_BOOTBK2_NCS"), 550 STM32_FUNCTION(11, "QUADSPI_BK2_NCS"),
521 STM32_FUNCTION(15, "LCD_R5"), 551 STM32_FUNCTION(15, "LCD_R5"),
522 STM32_FUNCTION(16, "EVENTOUT"), 552 STM32_FUNCTION(16, "EVENTOUT"),
523 STM32_FUNCTION(17, "ANALOG") 553 STM32_FUNCTION(17, "ANALOG")
524 ), 554 ),
525 STM32_PIN( 555 STM32_PIN_PKG(
526 PINCTRL_PIN(33, "PC1"), 556 PINCTRL_PIN(33, "PC1"),
557 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
527 STM32_FUNCTION(0, "GPIOC1"), 558 STM32_FUNCTION(0, "GPIOC1"),
528 STM32_FUNCTION(1, "TRACED0"), 559 STM32_FUNCTION(1, "TRACED0"),
529 STM32_FUNCTION(3, "SAI1_D1"), 560 STM32_FUNCTION(3, "SAI1_D1"),
530 STM32_FUNCTION(4, "DFSDM_DATA0"), 561 STM32_FUNCTION(4, "DFSDM1_DATIN0"),
531 STM32_FUNCTION(5, "DFSDM_CK4"), 562 STM32_FUNCTION(5, "DFSDM1_CKIN4"),
532 STM32_FUNCTION(6, "SPI2_MOSI I2S2_SDO"), 563 STM32_FUNCTION(6, "SPI2_MOSI I2S2_SDO"),
533 STM32_FUNCTION(7, "SAI1_SD_A"), 564 STM32_FUNCTION(7, "SAI1_SD_A"),
534 STM32_FUNCTION(10, "SDMMC2_CK"), 565 STM32_FUNCTION(10, "SDMMC2_CK"),
535 STM32_FUNCTION(12, "ETH_MDC"), 566 STM32_FUNCTION(12, "ETH1_MDC"),
536 STM32_FUNCTION(13, "MDIOS_MDC"), 567 STM32_FUNCTION(13, "MDIOS_MDC"),
537 STM32_FUNCTION(16, "EVENTOUT"), 568 STM32_FUNCTION(16, "EVENTOUT"),
538 STM32_FUNCTION(17, "ANALOG") 569 STM32_FUNCTION(17, "ANALOG")
539 ), 570 ),
540 STM32_PIN( 571 STM32_PIN_PKG(
541 PINCTRL_PIN(34, "PC2"), 572 PINCTRL_PIN(34, "PC2"),
573 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
542 STM32_FUNCTION(0, "GPIOC2"), 574 STM32_FUNCTION(0, "GPIOC2"),
543 STM32_FUNCTION(4, "DFSDM_CK1"), 575 STM32_FUNCTION(4, "DFSDM1_CKIN1"),
544 STM32_FUNCTION(6, "SPI2_MISO I2S2_SDI"), 576 STM32_FUNCTION(6, "SPI2_MISO I2S2_SDI"),
545 STM32_FUNCTION(7, "DFSDM_CKOUT"), 577 STM32_FUNCTION(7, "DFSDM1_CKOUT"),
546 STM32_FUNCTION(12, "ETH_GMII_TXD2 ETH_MII_TXD2 ETH_RGMII_TXD2"), 578 STM32_FUNCTION(12, "ETH1_GMII_TXD2 ETH1_MII_TXD2 ETH1_RGMII_TXD2"),
579 STM32_FUNCTION(14, "DCMI_PIXCLK"),
547 STM32_FUNCTION(16, "EVENTOUT"), 580 STM32_FUNCTION(16, "EVENTOUT"),
548 STM32_FUNCTION(17, "ANALOG") 581 STM32_FUNCTION(17, "ANALOG")
549 ), 582 ),
550 STM32_PIN( 583 STM32_PIN_PKG(
551 PINCTRL_PIN(35, "PC3"), 584 PINCTRL_PIN(35, "PC3"),
585 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
552 STM32_FUNCTION(0, "GPIOC3"), 586 STM32_FUNCTION(0, "GPIOC3"),
553 STM32_FUNCTION(1, "TRACECLK"), 587 STM32_FUNCTION(1, "TRACECLK"),
554 STM32_FUNCTION(4, "DFSDM_DATA1"), 588 STM32_FUNCTION(4, "DFSDM1_DATIN1"),
555 STM32_FUNCTION(6, "SPI2_MOSI I2S2_SDO"), 589 STM32_FUNCTION(6, "SPI2_MOSI I2S2_SDO"),
556 STM32_FUNCTION(12, "ETH_GMII_TX_CLK ETH_MII_TX_CLK"), 590 STM32_FUNCTION(12, "ETH1_GMII_TX_CLK ETH1_MII_TX_CLK"),
557 STM32_FUNCTION(16, "EVENTOUT"), 591 STM32_FUNCTION(16, "EVENTOUT"),
558 STM32_FUNCTION(17, "ANALOG") 592 STM32_FUNCTION(17, "ANALOG")
559 ), 593 ),
560 STM32_PIN( 594 STM32_PIN_PKG(
561 PINCTRL_PIN(36, "PC4"), 595 PINCTRL_PIN(36, "PC4"),
596 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
562 STM32_FUNCTION(0, "GPIOC4"), 597 STM32_FUNCTION(0, "GPIOC4"),
563 STM32_FUNCTION(4, "DFSDM_CK2"), 598 STM32_FUNCTION(4, "DFSDM1_CKIN2"),
564 STM32_FUNCTION(6, "I2S1_MCK"), 599 STM32_FUNCTION(6, "I2S1_MCK"),
565 STM32_FUNCTION(10, "SPDIF_IN2"), 600 STM32_FUNCTION(10, "SPDIFRX_IN2"),
566 STM32_FUNCTION(12, "ETH_GMII_RXD0 ETH_MII_RXD0 ETH_RGMII_RXD0 ETH_RMII_RXD0"), 601 STM32_FUNCTION(12, "ETH1_GMII_RXD0 ETH1_MII_RXD0 ETH1_RGMII_RXD0 ETH1_RMII_RXD0"),
567 STM32_FUNCTION(16, "EVENTOUT"), 602 STM32_FUNCTION(16, "EVENTOUT"),
568 STM32_FUNCTION(17, "ANALOG") 603 STM32_FUNCTION(17, "ANALOG")
569 ), 604 ),
570 STM32_PIN( 605 STM32_PIN_PKG(
571 PINCTRL_PIN(37, "PC5"), 606 PINCTRL_PIN(37, "PC5"),
607 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
572 STM32_FUNCTION(0, "GPIOC5"), 608 STM32_FUNCTION(0, "GPIOC5"),
573 STM32_FUNCTION(3, "SAI1_D3"), 609 STM32_FUNCTION(3, "SAI1_D3"),
574 STM32_FUNCTION(4, "DFSDM_DATA2"), 610 STM32_FUNCTION(4, "DFSDM1_DATIN2"),
575 STM32_FUNCTION(5, "SAI4_D4"), 611 STM32_FUNCTION(5, "SAI4_D4"),
576 STM32_FUNCTION(7, "SAI1_D4"), 612 STM32_FUNCTION(7, "SAI1_D4"),
577 STM32_FUNCTION(10, "SPDIF_IN3"), 613 STM32_FUNCTION(10, "SPDIFRX_IN3"),
578 STM32_FUNCTION(12, "ETH_GMII_RXD1 ETH_MII_RXD1 ETH_RGMII_RXD1 ETH_RMII_RXD1"), 614 STM32_FUNCTION(12, "ETH1_GMII_RXD1 ETH1_MII_RXD1 ETH1_RGMII_RXD1 ETH1_RMII_RXD1"),
579 STM32_FUNCTION(13, "SAI4_D3"), 615 STM32_FUNCTION(13, "SAI4_D3"),
580 STM32_FUNCTION(16, "EVENTOUT"), 616 STM32_FUNCTION(16, "EVENTOUT"),
581 STM32_FUNCTION(17, "ANALOG") 617 STM32_FUNCTION(17, "ANALOG")
582 ), 618 ),
583 STM32_PIN( 619 STM32_PIN_PKG(
584 PINCTRL_PIN(38, "PC6"), 620 PINCTRL_PIN(38, "PC6"),
621 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
585 STM32_FUNCTION(0, "GPIOC6"), 622 STM32_FUNCTION(0, "GPIOC6"),
586 STM32_FUNCTION(1, "HDP1"), 623 STM32_FUNCTION(1, "HDP1"),
587 STM32_FUNCTION(3, "TIM3_CH1"), 624 STM32_FUNCTION(3, "TIM3_CH1"),
588 STM32_FUNCTION(4, "TIM8_CH1"), 625 STM32_FUNCTION(4, "TIM8_CH1"),
589 STM32_FUNCTION(5, "DFSDM_CK3"), 626 STM32_FUNCTION(5, "DFSDM1_CKIN3"),
590 STM32_FUNCTION(6, "I2S2_MCK"), 627 STM32_FUNCTION(6, "I2S2_MCK"),
591 STM32_FUNCTION(8, "USART6_TX USART_BOOT6_TX"), 628 STM32_FUNCTION(8, "USART6_TX"),
592 STM32_FUNCTION(9, "SDMMC1_D0DIR SDMMC_BOOT1_D0DIR"), 629 STM32_FUNCTION(9, "SDMMC1_D0DIR"),
593 STM32_FUNCTION(10, "SDMMC2_D0DIR SDMMC_BOOT2_D0DIR"), 630 STM32_FUNCTION(10, "SDMMC2_D0DIR"),
594 STM32_FUNCTION(11, "SDMMC2_D6 SDMMC_BOOT2_D6"), 631 STM32_FUNCTION(11, "SDMMC2_D6"),
595 STM32_FUNCTION(12, "DSI_TE"), 632 STM32_FUNCTION(12, "DSI_TE"),
596 STM32_FUNCTION(13, "SDMMC1_D6 SDMMC_BOOT1_D6"), 633 STM32_FUNCTION(13, "SDMMC1_D6"),
597 STM32_FUNCTION(14, "DCMI_D0"), 634 STM32_FUNCTION(14, "DCMI_D0"),
598 STM32_FUNCTION(15, "LCD_HSYNC"), 635 STM32_FUNCTION(15, "LCD_HSYNC"),
599 STM32_FUNCTION(16, "EVENTOUT"), 636 STM32_FUNCTION(16, "EVENTOUT"),
600 STM32_FUNCTION(17, "ANALOG") 637 STM32_FUNCTION(17, "ANALOG")
601 ), 638 ),
602 STM32_PIN( 639 STM32_PIN_PKG(
603 PINCTRL_PIN(39, "PC7"), 640 PINCTRL_PIN(39, "PC7"),
641 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
604 STM32_FUNCTION(0, "GPIOC7"), 642 STM32_FUNCTION(0, "GPIOC7"),
605 STM32_FUNCTION(1, "HDP4"), 643 STM32_FUNCTION(1, "HDP4"),
606 STM32_FUNCTION(3, "TIM3_CH2"), 644 STM32_FUNCTION(3, "TIM3_CH2"),
607 STM32_FUNCTION(4, "TIM8_CH2"), 645 STM32_FUNCTION(4, "TIM8_CH2"),
608 STM32_FUNCTION(5, "DFSDM_DATA3"), 646 STM32_FUNCTION(5, "DFSDM1_DATIN3"),
609 STM32_FUNCTION(7, "I2S3_MCK"), 647 STM32_FUNCTION(7, "I2S3_MCK"),
610 STM32_FUNCTION(8, "USART6_RX USART_BOOT6_RX"), 648 STM32_FUNCTION(8, "USART6_RX"),
611 STM32_FUNCTION(9, "SDMMC1_D123DIR SDMMC_BOOT1_D123DIR"), 649 STM32_FUNCTION(9, "SDMMC1_D123DIR"),
612 STM32_FUNCTION(10, "SDMMC2_D123DIR SDMMC_BOOT2_D123DIR"), 650 STM32_FUNCTION(10, "SDMMC2_D123DIR"),
613 STM32_FUNCTION(11, "SDMMC2_D7 SDMMC_BOOT2_D7"), 651 STM32_FUNCTION(11, "SDMMC2_D7"),
614 STM32_FUNCTION(13, "SDMMC1_D7 SDMMC_BOOT1_D7"), 652 STM32_FUNCTION(13, "SDMMC1_D7"),
615 STM32_FUNCTION(14, "DCMI_D1"), 653 STM32_FUNCTION(14, "DCMI_D1"),
616 STM32_FUNCTION(15, "LCD_G6"), 654 STM32_FUNCTION(15, "LCD_G6"),
617 STM32_FUNCTION(16, "EVENTOUT"), 655 STM32_FUNCTION(16, "EVENTOUT"),
618 STM32_FUNCTION(17, "ANALOG") 656 STM32_FUNCTION(17, "ANALOG")
619 ), 657 ),
620 STM32_PIN( 658 STM32_PIN_PKG(
621 PINCTRL_PIN(40, "PC8"), 659 PINCTRL_PIN(40, "PC8"),
660 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
622 STM32_FUNCTION(0, "GPIOC8"), 661 STM32_FUNCTION(0, "GPIOC8"),
623 STM32_FUNCTION(1, "TRACED0"), 662 STM32_FUNCTION(1, "TRACED0"),
624 STM32_FUNCTION(3, "TIM3_CH3"), 663 STM32_FUNCTION(3, "TIM3_CH3"),
625 STM32_FUNCTION(4, "TIM8_CH3"), 664 STM32_FUNCTION(4, "TIM8_CH3"),
626 STM32_FUNCTION(7, "UART4_TX"), 665 STM32_FUNCTION(7, "UART4_TX"),
627 STM32_FUNCTION(8, "USART6_CK USART_BOOT6_CK"), 666 STM32_FUNCTION(8, "USART6_CK"),
628 STM32_FUNCTION(9, "UART5_RTS UART_BOOT5_RTS"), 667 STM32_FUNCTION(9, "UART5_RTS UART5_DE"),
629 STM32_FUNCTION(13, "SDMMC1_D0 SDMMC_BOOT1_D0"), 668 STM32_FUNCTION(13, "SDMMC1_D0"),
630 STM32_FUNCTION(14, "DCMI_D2"), 669 STM32_FUNCTION(14, "DCMI_D2"),
631 STM32_FUNCTION(16, "EVENTOUT"), 670 STM32_FUNCTION(16, "EVENTOUT"),
632 STM32_FUNCTION(17, "ANALOG") 671 STM32_FUNCTION(17, "ANALOG")
633 ), 672 ),
634 STM32_PIN( 673 STM32_PIN_PKG(
635 PINCTRL_PIN(41, "PC9"), 674 PINCTRL_PIN(41, "PC9"),
675 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
636 STM32_FUNCTION(0, "GPIOC9"), 676 STM32_FUNCTION(0, "GPIOC9"),
637 STM32_FUNCTION(1, "TRACED1"), 677 STM32_FUNCTION(1, "TRACED1"),
638 STM32_FUNCTION(3, "TIM3_CH4"), 678 STM32_FUNCTION(3, "TIM3_CH4"),
639 STM32_FUNCTION(4, "TIM8_CH4"), 679 STM32_FUNCTION(4, "TIM8_CH4"),
640 STM32_FUNCTION(5, "I2C3_SDA"), 680 STM32_FUNCTION(5, "I2C3_SDA"),
641 STM32_FUNCTION(6, "I2S_CKIN"), 681 STM32_FUNCTION(6, "I2S_CKIN"),
642 STM32_FUNCTION(9, "UART5_CTS UART_BOOT5_CTS"), 682 STM32_FUNCTION(9, "UART5_CTS"),
643 STM32_FUNCTION(10, "QUADSPI_BK1_IO0"), 683 STM32_FUNCTION(10, "QUADSPI_BK1_IO0"),
644 STM32_FUNCTION(13, "SDMMC1_D1 SDMMC_BOOT1_D1"), 684 STM32_FUNCTION(13, "SDMMC1_D1"),
645 STM32_FUNCTION(14, "DCMI_D3"), 685 STM32_FUNCTION(14, "DCMI_D3"),
646 STM32_FUNCTION(15, "LCD_B2"), 686 STM32_FUNCTION(15, "LCD_B2"),
647 STM32_FUNCTION(16, "EVENTOUT"), 687 STM32_FUNCTION(16, "EVENTOUT"),
648 STM32_FUNCTION(17, "ANALOG") 688 STM32_FUNCTION(17, "ANALOG")
649 ), 689 ),
650 STM32_PIN( 690 STM32_PIN_PKG(
651 PINCTRL_PIN(42, "PC10"), 691 PINCTRL_PIN(42, "PC10"),
692 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
652 STM32_FUNCTION(0, "GPIOC10"), 693 STM32_FUNCTION(0, "GPIOC10"),
653 STM32_FUNCTION(1, "TRACED2"), 694 STM32_FUNCTION(1, "TRACED2"),
654 STM32_FUNCTION(4, "DFSDM_CK5"), 695 STM32_FUNCTION(4, "DFSDM1_CKIN5"),
655 STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"), 696 STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
656 STM32_FUNCTION(8, "USART3_TX"), 697 STM32_FUNCTION(8, "USART3_TX"),
657 STM32_FUNCTION(9, "UART4_TX"), 698 STM32_FUNCTION(9, "UART4_TX"),
658 STM32_FUNCTION(10, "QUADSPI_BK1_IO1"), 699 STM32_FUNCTION(10, "QUADSPI_BK1_IO1"),
659 STM32_FUNCTION(11, "SAI4_MCLK_B"), 700 STM32_FUNCTION(11, "SAI4_MCLK_B"),
660 STM32_FUNCTION(13, "SDMMC1_D2 SDMMC_BOOT1_D2"), 701 STM32_FUNCTION(13, "SDMMC1_D2"),
661 STM32_FUNCTION(14, "DCMI_D8"), 702 STM32_FUNCTION(14, "DCMI_D8"),
662 STM32_FUNCTION(15, "LCD_R2"), 703 STM32_FUNCTION(15, "LCD_R2"),
663 STM32_FUNCTION(16, "EVENTOUT"), 704 STM32_FUNCTION(16, "EVENTOUT"),
664 STM32_FUNCTION(17, "ANALOG") 705 STM32_FUNCTION(17, "ANALOG")
665 ), 706 ),
666 STM32_PIN( 707 STM32_PIN_PKG(
667 PINCTRL_PIN(43, "PC11"), 708 PINCTRL_PIN(43, "PC11"),
709 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
668 STM32_FUNCTION(0, "GPIOC11"), 710 STM32_FUNCTION(0, "GPIOC11"),
669 STM32_FUNCTION(1, "TRACED3"), 711 STM32_FUNCTION(1, "TRACED3"),
670 STM32_FUNCTION(4, "DFSDM_DATA5"), 712 STM32_FUNCTION(4, "DFSDM1_DATIN5"),
671 STM32_FUNCTION(7, "SPI3_MISO I2S3_SDI"), 713 STM32_FUNCTION(7, "SPI3_MISO I2S3_SDI"),
672 STM32_FUNCTION(8, "USART3_RX"), 714 STM32_FUNCTION(8, "USART3_RX"),
673 STM32_FUNCTION(9, "UART4_RX"), 715 STM32_FUNCTION(9, "UART4_RX"),
674 STM32_FUNCTION(10, "QUADSPI_BK2_NCS QUADSPI_BOOTBK2_NCS"), 716 STM32_FUNCTION(10, "QUADSPI_BK2_NCS"),
675 STM32_FUNCTION(11, "SAI4_SCK_B"), 717 STM32_FUNCTION(11, "SAI4_SCK_B"),
676 STM32_FUNCTION(13, "SDMMC1_D3 SDMMC_BOOT1_D3"), 718 STM32_FUNCTION(13, "SDMMC1_D3"),
677 STM32_FUNCTION(14, "DCMI_D4"), 719 STM32_FUNCTION(14, "DCMI_D4"),
678 STM32_FUNCTION(16, "EVENTOUT"), 720 STM32_FUNCTION(16, "EVENTOUT"),
679 STM32_FUNCTION(17, "ANALOG") 721 STM32_FUNCTION(17, "ANALOG")
680 ), 722 ),
681 STM32_PIN( 723 STM32_PIN_PKG(
682 PINCTRL_PIN(44, "PC12"), 724 PINCTRL_PIN(44, "PC12"),
725 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
683 STM32_FUNCTION(0, "GPIOC12"), 726 STM32_FUNCTION(0, "GPIOC12"),
684 STM32_FUNCTION(1, "TRACECLK"), 727 STM32_FUNCTION(1, "TRACECLK"),
685 STM32_FUNCTION(2, "MCO2"), 728 STM32_FUNCTION(2, "MCO2"),
686 STM32_FUNCTION(3, "SAI4_D3"), 729 STM32_FUNCTION(3, "SAI4_D3"),
687 STM32_FUNCTION(7, "SPI3_MOSI I2S3_SDO"), 730 STM32_FUNCTION(7, "SPI3_MOSI I2S3_SDO"),
688 STM32_FUNCTION(8, "USART3_CK USART_BOOT3_CK"), 731 STM32_FUNCTION(8, "USART3_CK"),
689 STM32_FUNCTION(9, "UART5_TX"), 732 STM32_FUNCTION(9, "UART5_TX"),
690 STM32_FUNCTION(11, "SAI4_SD_B"), 733 STM32_FUNCTION(11, "SAI4_SD_B"),
691 STM32_FUNCTION(13, "SDMMC1_CK SDMMC_BOOT1_CK"), 734 STM32_FUNCTION(13, "SDMMC1_CK"),
692 STM32_FUNCTION(14, "DCMI_D9"), 735 STM32_FUNCTION(14, "DCMI_D9"),
693 STM32_FUNCTION(16, "EVENTOUT"), 736 STM32_FUNCTION(16, "EVENTOUT"),
694 STM32_FUNCTION(17, "ANALOG") 737 STM32_FUNCTION(17, "ANALOG")
695 ), 738 ),
696 STM32_PIN( 739 STM32_PIN_PKG(
697 PINCTRL_PIN(45, "PC13"), 740 PINCTRL_PIN(45, "PC13"),
741 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
698 STM32_FUNCTION(0, "GPIOC13"), 742 STM32_FUNCTION(0, "GPIOC13"),
699 STM32_FUNCTION(16, "EVENTOUT"), 743 STM32_FUNCTION(16, "EVENTOUT"),
700 STM32_FUNCTION(17, "ANALOG") 744 STM32_FUNCTION(17, "ANALOG")
701 ), 745 ),
702 STM32_PIN( 746 STM32_PIN_PKG(
703 PINCTRL_PIN(46, "PC14"), 747 PINCTRL_PIN(46, "PC14"),
748 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
704 STM32_FUNCTION(0, "GPIOC14"), 749 STM32_FUNCTION(0, "GPIOC14"),
705 STM32_FUNCTION(16, "EVENTOUT"), 750 STM32_FUNCTION(16, "EVENTOUT"),
706 STM32_FUNCTION(17, "ANALOG") 751 STM32_FUNCTION(17, "ANALOG")
707 ), 752 ),
708 STM32_PIN( 753 STM32_PIN_PKG(
709 PINCTRL_PIN(47, "PC15"), 754 PINCTRL_PIN(47, "PC15"),
755 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
710 STM32_FUNCTION(0, "GPIOC15"), 756 STM32_FUNCTION(0, "GPIOC15"),
711 STM32_FUNCTION(16, "EVENTOUT"), 757 STM32_FUNCTION(16, "EVENTOUT"),
712 STM32_FUNCTION(17, "ANALOG") 758 STM32_FUNCTION(17, "ANALOG")
713 ), 759 ),
714 STM32_PIN( 760 STM32_PIN_PKG(
715 PINCTRL_PIN(48, "PD0"), 761 PINCTRL_PIN(48, "PD0"),
762 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
716 STM32_FUNCTION(0, "GPIOD0"), 763 STM32_FUNCTION(0, "GPIOD0"),
717 STM32_FUNCTION(3, "I2C6_SDA"), 764 STM32_FUNCTION(3, "I2C6_SDA"),
718 STM32_FUNCTION(4, "DFSDM_CK6"), 765 STM32_FUNCTION(4, "DFSDM1_CKIN6"),
719 STM32_FUNCTION(5, "I2C5_SDA"), 766 STM32_FUNCTION(5, "I2C5_SDA"),
720 STM32_FUNCTION(7, "SAI3_SCK_A"), 767 STM32_FUNCTION(7, "SAI3_SCK_A"),
721 STM32_FUNCTION(9, "UART4_RX"), 768 STM32_FUNCTION(9, "UART4_RX"),
722 STM32_FUNCTION(10, "CAN1_RX"), 769 STM32_FUNCTION(10, "FDCAN1_RX"),
723 STM32_FUNCTION(11, "SDMMC3_CMD"), 770 STM32_FUNCTION(11, "SDMMC3_CMD"),
724 STM32_FUNCTION(12, "DFSDM_DATA7"), 771 STM32_FUNCTION(12, "DFSDM1_DATIN7"),
725 STM32_FUNCTION(13, "FMC_D2"), 772 STM32_FUNCTION(13, "FMC_D2 FMC_DA2"),
726 STM32_FUNCTION(16, "EVENTOUT"), 773 STM32_FUNCTION(16, "EVENTOUT"),
727 STM32_FUNCTION(17, "ANALOG") 774 STM32_FUNCTION(17, "ANALOG")
728 ), 775 ),
729 STM32_PIN( 776 STM32_PIN_PKG(
730 PINCTRL_PIN(49, "PD1"), 777 PINCTRL_PIN(49, "PD1"),
778 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
731 STM32_FUNCTION(0, "GPIOD1"), 779 STM32_FUNCTION(0, "GPIOD1"),
732 STM32_FUNCTION(3, "I2C6_SCL"), 780 STM32_FUNCTION(3, "I2C6_SCL"),
733 STM32_FUNCTION(4, "DFSDM_DATA6"), 781 STM32_FUNCTION(4, "DFSDM1_DATIN6"),
734 STM32_FUNCTION(5, "I2C5_SCL"), 782 STM32_FUNCTION(5, "I2C5_SCL"),
735 STM32_FUNCTION(7, "SAI3_SD_A"), 783 STM32_FUNCTION(7, "SAI3_SD_A"),
736 STM32_FUNCTION(9, "UART4_TX"), 784 STM32_FUNCTION(9, "UART4_TX"),
737 STM32_FUNCTION(10, "CAN1_TX"), 785 STM32_FUNCTION(10, "FDCAN1_TX"),
738 STM32_FUNCTION(11, "SDMMC3_D0"), 786 STM32_FUNCTION(11, "SDMMC3_D0"),
739 STM32_FUNCTION(12, "DFSDM_CK7"), 787 STM32_FUNCTION(12, "DFSDM1_CKIN7"),
740 STM32_FUNCTION(13, "FMC_D3"), 788 STM32_FUNCTION(13, "FMC_D3 FMC_DA3"),
741 STM32_FUNCTION(16, "EVENTOUT"), 789 STM32_FUNCTION(16, "EVENTOUT"),
742 STM32_FUNCTION(17, "ANALOG") 790 STM32_FUNCTION(17, "ANALOG")
743 ), 791 ),
744 STM32_PIN( 792 STM32_PIN_PKG(
745 PINCTRL_PIN(50, "PD2"), 793 PINCTRL_PIN(50, "PD2"),
794 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
746 STM32_FUNCTION(0, "GPIOD2"), 795 STM32_FUNCTION(0, "GPIOD2"),
747 STM32_FUNCTION(3, "TIM3_ETR"), 796 STM32_FUNCTION(3, "TIM3_ETR"),
748 STM32_FUNCTION(5, "I2C5_SMBA"), 797 STM32_FUNCTION(5, "I2C5_SMBA"),
749 STM32_FUNCTION(7, "UART4_RX"), 798 STM32_FUNCTION(7, "UART4_RX"),
750 STM32_FUNCTION(9, "UART5_RX"), 799 STM32_FUNCTION(9, "UART5_RX"),
751 STM32_FUNCTION(13, "SDMMC1_CMD SDMMC_BOOT1_CMD"), 800 STM32_FUNCTION(13, "SDMMC1_CMD"),
752 STM32_FUNCTION(14, "DCMI_D11"), 801 STM32_FUNCTION(14, "DCMI_D11"),
753 STM32_FUNCTION(16, "EVENTOUT"), 802 STM32_FUNCTION(16, "EVENTOUT"),
754 STM32_FUNCTION(17, "ANALOG") 803 STM32_FUNCTION(17, "ANALOG")
755 ), 804 ),
756 STM32_PIN( 805 STM32_PIN_PKG(
757 PINCTRL_PIN(51, "PD3"), 806 PINCTRL_PIN(51, "PD3"),
807 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
758 STM32_FUNCTION(0, "GPIOD3"), 808 STM32_FUNCTION(0, "GPIOD3"),
759 STM32_FUNCTION(1, "HDP5"), 809 STM32_FUNCTION(1, "HDP5"),
760 STM32_FUNCTION(4, "DFSDM_CKOUT"), 810 STM32_FUNCTION(4, "DFSDM1_CKOUT"),
761 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), 811 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
762 STM32_FUNCTION(7, "DFSDM_DATA0"), 812 STM32_FUNCTION(7, "DFSDM1_DATIN0"),
763 STM32_FUNCTION(8, "USART2_CTS_NSS USART_BOOT2_CTS_NSS"), 813 STM32_FUNCTION(8, "USART2_CTS USART2_NSS"),
764 STM32_FUNCTION(9, "SDMMC1_D123DIR SDMMC_BOOT1_D123DIR"), 814 STM32_FUNCTION(9, "SDMMC1_D123DIR"),
765 STM32_FUNCTION(10, "SDMMC2_D7 SDMMC_BOOT2_D7"), 815 STM32_FUNCTION(10, "SDMMC2_D7"),
766 STM32_FUNCTION(11, "SDMMC2_D123DIR SDMMC_BOOT2_D123DIR"), 816 STM32_FUNCTION(11, "SDMMC2_D123DIR"),
767 STM32_FUNCTION(12, "SDMMC1_D7 SDMMC_BOOT1_D7"), 817 STM32_FUNCTION(12, "SDMMC1_D7"),
768 STM32_FUNCTION(13, "FMC_CLK"), 818 STM32_FUNCTION(13, "FMC_CLK"),
769 STM32_FUNCTION(14, "DCMI_D5"), 819 STM32_FUNCTION(14, "DCMI_D5"),
770 STM32_FUNCTION(15, "LCD_G7"), 820 STM32_FUNCTION(15, "LCD_G7"),
771 STM32_FUNCTION(16, "EVENTOUT"), 821 STM32_FUNCTION(16, "EVENTOUT"),
772 STM32_FUNCTION(17, "ANALOG") 822 STM32_FUNCTION(17, "ANALOG")
773 ), 823 ),
774 STM32_PIN( 824 STM32_PIN_PKG(
775 PINCTRL_PIN(52, "PD4"), 825 PINCTRL_PIN(52, "PD4"),
826 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
776 STM32_FUNCTION(0, "GPIOD4"), 827 STM32_FUNCTION(0, "GPIOD4"),
777 STM32_FUNCTION(7, "SAI3_FS_A"), 828 STM32_FUNCTION(7, "SAI3_FS_A"),
778 STM32_FUNCTION(8, "USART2_RTS USART_BOOT2_RTS"), 829 STM32_FUNCTION(8, "USART2_RTS USART2_DE"),
779 STM32_FUNCTION(10, "CAN1_RXFD"),
780 STM32_FUNCTION(11, "SDMMC3_D1"), 830 STM32_FUNCTION(11, "SDMMC3_D1"),
781 STM32_FUNCTION(12, "DFSDM_CK0"), 831 STM32_FUNCTION(12, "DFSDM1_CKIN0"),
782 STM32_FUNCTION(13, "FMC_NOE"), 832 STM32_FUNCTION(13, "FMC_NOE"),
783 STM32_FUNCTION(16, "EVENTOUT"), 833 STM32_FUNCTION(16, "EVENTOUT"),
784 STM32_FUNCTION(17, "ANALOG") 834 STM32_FUNCTION(17, "ANALOG")
785 ), 835 ),
786 STM32_PIN( 836 STM32_PIN_PKG(
787 PINCTRL_PIN(53, "PD5"), 837 PINCTRL_PIN(53, "PD5"),
838 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
788 STM32_FUNCTION(0, "GPIOD5"), 839 STM32_FUNCTION(0, "GPIOD5"),
789 STM32_FUNCTION(8, "USART2_TX"), 840 STM32_FUNCTION(8, "USART2_TX"),
790 STM32_FUNCTION(10, "CAN1_TXFD"),
791 STM32_FUNCTION(11, "SDMMC3_D2"), 841 STM32_FUNCTION(11, "SDMMC3_D2"),
792 STM32_FUNCTION(13, "FMC_NWE"), 842 STM32_FUNCTION(13, "FMC_NWE"),
793 STM32_FUNCTION(16, "EVENTOUT"), 843 STM32_FUNCTION(16, "EVENTOUT"),
794 STM32_FUNCTION(17, "ANALOG") 844 STM32_FUNCTION(17, "ANALOG")
795 ), 845 ),
796 STM32_PIN( 846 STM32_PIN_PKG(
797 PINCTRL_PIN(54, "PD6"), 847 PINCTRL_PIN(54, "PD6"),
848 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
798 STM32_FUNCTION(0, "GPIOD6"), 849 STM32_FUNCTION(0, "GPIOD6"),
799 STM32_FUNCTION(2, "TIM16_CH1N"), 850 STM32_FUNCTION(2, "TIM16_CH1N"),
800 STM32_FUNCTION(3, "SAI1_D1"), 851 STM32_FUNCTION(3, "SAI1_D1"),
801 STM32_FUNCTION(4, "DFSDM_CK4"), 852 STM32_FUNCTION(4, "DFSDM1_CKIN4"),
802 STM32_FUNCTION(5, "DFSDM_DATA1"), 853 STM32_FUNCTION(5, "DFSDM1_DATIN1"),
803 STM32_FUNCTION(6, "SPI3_MOSI I2S3_SDO"), 854 STM32_FUNCTION(6, "SPI3_MOSI I2S3_SDO"),
804 STM32_FUNCTION(7, "SAI1_SD_A"), 855 STM32_FUNCTION(7, "SAI1_SD_A"),
805 STM32_FUNCTION(8, "USART2_RX"), 856 STM32_FUNCTION(8, "USART2_RX"),
806 STM32_FUNCTION(10, "CAN2_RXFD"),
807 STM32_FUNCTION(11, "FMC_INT"),
808 STM32_FUNCTION(13, "FMC_NWAIT"), 857 STM32_FUNCTION(13, "FMC_NWAIT"),
809 STM32_FUNCTION(14, "DCMI_D10"), 858 STM32_FUNCTION(14, "DCMI_D10"),
810 STM32_FUNCTION(15, "LCD_B2"), 859 STM32_FUNCTION(15, "LCD_B2"),
811 STM32_FUNCTION(16, "EVENTOUT"), 860 STM32_FUNCTION(16, "EVENTOUT"),
812 STM32_FUNCTION(17, "ANALOG") 861 STM32_FUNCTION(17, "ANALOG")
813 ), 862 ),
814 STM32_PIN( 863 STM32_PIN_PKG(
815 PINCTRL_PIN(55, "PD7"), 864 PINCTRL_PIN(55, "PD7"),
865 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
816 STM32_FUNCTION(0, "GPIOD7"), 866 STM32_FUNCTION(0, "GPIOD7"),
817 STM32_FUNCTION(1, "TRACED6"), 867 STM32_FUNCTION(1, "TRACED6"),
818 STM32_FUNCTION(4, "DFSDM_DATA4"), 868 STM32_FUNCTION(4, "DFSDM1_DATIN4"),
819 STM32_FUNCTION(5, "I2C2_SCL"), 869 STM32_FUNCTION(5, "I2C2_SCL"),
820 STM32_FUNCTION(7, "DFSDM_CK1"), 870 STM32_FUNCTION(7, "DFSDM1_CKIN1"),
821 STM32_FUNCTION(8, "USART2_CK USART_BOOT2_CK"), 871 STM32_FUNCTION(8, "USART2_CK"),
822 STM32_FUNCTION(10, "SPDIF_IN0"), 872 STM32_FUNCTION(10, "SPDIFRX_IN0"),
823 STM32_FUNCTION(11, "SDMMC3_D3"), 873 STM32_FUNCTION(11, "SDMMC3_D3"),
824 STM32_FUNCTION(13, "FMC_NE1"), 874 STM32_FUNCTION(13, "FMC_NE1"),
825 STM32_FUNCTION(16, "EVENTOUT"), 875 STM32_FUNCTION(16, "EVENTOUT"),
826 STM32_FUNCTION(17, "ANALOG") 876 STM32_FUNCTION(17, "ANALOG")
827 ), 877 ),
828 STM32_PIN( 878 STM32_PIN_PKG(
829 PINCTRL_PIN(56, "PD8"), 879 PINCTRL_PIN(56, "PD8"),
880 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
830 STM32_FUNCTION(0, "GPIOD8"), 881 STM32_FUNCTION(0, "GPIOD8"),
831 STM32_FUNCTION(4, "DFSDM_CK3"), 882 STM32_FUNCTION(4, "DFSDM1_CKIN3"),
832 STM32_FUNCTION(7, "SAI3_SCK_B"), 883 STM32_FUNCTION(7, "SAI3_SCK_B"),
833 STM32_FUNCTION(8, "USART3_TX"), 884 STM32_FUNCTION(8, "USART3_TX"),
834 STM32_FUNCTION(10, "SPDIF_IN1"), 885 STM32_FUNCTION(10, "SPDIFRX_IN1"),
835 STM32_FUNCTION(13, "FMC_D13"), 886 STM32_FUNCTION(13, "FMC_D13 FMC_DA13"),
836 STM32_FUNCTION(15, "LCD_B7"), 887 STM32_FUNCTION(15, "LCD_B7"),
837 STM32_FUNCTION(16, "EVENTOUT"), 888 STM32_FUNCTION(16, "EVENTOUT"),
838 STM32_FUNCTION(17, "ANALOG") 889 STM32_FUNCTION(17, "ANALOG")
839 ), 890 ),
840 STM32_PIN( 891 STM32_PIN_PKG(
841 PINCTRL_PIN(57, "PD9"), 892 PINCTRL_PIN(57, "PD9"),
893 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
842 STM32_FUNCTION(0, "GPIOD9"), 894 STM32_FUNCTION(0, "GPIOD9"),
843 STM32_FUNCTION(4, "DFSDM_DATA3"), 895 STM32_FUNCTION(4, "DFSDM1_DATIN3"),
844 STM32_FUNCTION(7, "SAI3_SD_B"), 896 STM32_FUNCTION(7, "SAI3_SD_B"),
845 STM32_FUNCTION(8, "USART3_RX"), 897 STM32_FUNCTION(8, "USART3_RX"),
846 STM32_FUNCTION(10, "CAN2_RXFD"), 898 STM32_FUNCTION(13, "FMC_D14 FMC_DA14"),
847 STM32_FUNCTION(13, "FMC_D14"), 899 STM32_FUNCTION(14, "DCMI_HSYNC"),
848 STM32_FUNCTION(15, "LCD_B0"), 900 STM32_FUNCTION(15, "LCD_B0"),
849 STM32_FUNCTION(16, "EVENTOUT"), 901 STM32_FUNCTION(16, "EVENTOUT"),
850 STM32_FUNCTION(17, "ANALOG") 902 STM32_FUNCTION(17, "ANALOG")
851 ), 903 ),
852 STM32_PIN( 904 STM32_PIN_PKG(
853 PINCTRL_PIN(58, "PD10"), 905 PINCTRL_PIN(58, "PD10"),
906 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
854 STM32_FUNCTION(0, "GPIOD10"), 907 STM32_FUNCTION(0, "GPIOD10"),
855 STM32_FUNCTION(1, "RTC_REFIN"), 908 STM32_FUNCTION(1, "RTC_REFIN"),
856 STM32_FUNCTION(2, "TIM16_BKIN"), 909 STM32_FUNCTION(2, "TIM16_BKIN"),
857 STM32_FUNCTION(4, "DFSDM_CKOUT"), 910 STM32_FUNCTION(4, "DFSDM1_CKOUT"),
858 STM32_FUNCTION(5, "I2C5_SMBA"), 911 STM32_FUNCTION(5, "I2C5_SMBA"),
859 STM32_FUNCTION(6, "SPI3_MISO I2S3_SDI"), 912 STM32_FUNCTION(6, "SPI3_MISO I2S3_SDI"),
860 STM32_FUNCTION(7, "SAI3_FS_B"), 913 STM32_FUNCTION(7, "SAI3_FS_B"),
861 STM32_FUNCTION(8, "USART3_CK USART_BOOT3_CK"), 914 STM32_FUNCTION(8, "USART3_CK"),
862 STM32_FUNCTION(10, "CAN2_TXFD"), 915 STM32_FUNCTION(13, "FMC_D15 FMC_DA15"),
863 STM32_FUNCTION(13, "FMC_D15"),
864 STM32_FUNCTION(15, "LCD_B3"), 916 STM32_FUNCTION(15, "LCD_B3"),
865 STM32_FUNCTION(16, "EVENTOUT"), 917 STM32_FUNCTION(16, "EVENTOUT"),
866 STM32_FUNCTION(17, "ANALOG") 918 STM32_FUNCTION(17, "ANALOG")
867 ), 919 ),
868 STM32_PIN( 920 STM32_PIN_PKG(
869 PINCTRL_PIN(59, "PD11"), 921 PINCTRL_PIN(59, "PD11"),
922 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
870 STM32_FUNCTION(0, "GPIOD11"), 923 STM32_FUNCTION(0, "GPIOD11"),
871 STM32_FUNCTION(4, "LPTIM2_IN2"), 924 STM32_FUNCTION(4, "LPTIM2_IN2"),
872 STM32_FUNCTION(5, "I2C4_SMBA"), 925 STM32_FUNCTION(5, "I2C4_SMBA"),
873 STM32_FUNCTION(6, "I2C1_SMBA"), 926 STM32_FUNCTION(6, "I2C1_SMBA"),
874 STM32_FUNCTION(8, "USART3_CTS_NSS USART_BOOT3_CTS_NSS"), 927 STM32_FUNCTION(8, "USART3_CTS USART3_NSS"),
875 STM32_FUNCTION(10, "QUADSPI_BK1_IO0"), 928 STM32_FUNCTION(10, "QUADSPI_BK1_IO0"),
876 STM32_FUNCTION(11, "SAI2_SD_A"), 929 STM32_FUNCTION(11, "SAI2_SD_A"),
877 STM32_FUNCTION(13, "FMC_A16 FMC_CLE"), 930 STM32_FUNCTION(13, "FMC_CLE FMC_A16"),
878 STM32_FUNCTION(16, "EVENTOUT"), 931 STM32_FUNCTION(16, "EVENTOUT"),
879 STM32_FUNCTION(17, "ANALOG") 932 STM32_FUNCTION(17, "ANALOG")
880 ), 933 ),
881 STM32_PIN( 934 STM32_PIN_PKG(
882 PINCTRL_PIN(60, "PD12"), 935 PINCTRL_PIN(60, "PD12"),
936 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
883 STM32_FUNCTION(0, "GPIOD12"), 937 STM32_FUNCTION(0, "GPIOD12"),
884 STM32_FUNCTION(2, "LPTIM1_IN1"), 938 STM32_FUNCTION(2, "LPTIM1_IN1"),
885 STM32_FUNCTION(3, "TIM4_CH1"), 939 STM32_FUNCTION(3, "TIM4_CH1"),
886 STM32_FUNCTION(4, "LPTIM2_IN1"), 940 STM32_FUNCTION(4, "LPTIM2_IN1"),
887 STM32_FUNCTION(5, "I2C4_SCL"), 941 STM32_FUNCTION(5, "I2C4_SCL"),
888 STM32_FUNCTION(6, "I2C1_SCL"), 942 STM32_FUNCTION(6, "I2C1_SCL"),
889 STM32_FUNCTION(8, "USART3_RTS USART_BOOT3_RTS"), 943 STM32_FUNCTION(8, "USART3_RTS USART3_DE"),
890 STM32_FUNCTION(10, "QUADSPI_BK1_IO1"), 944 STM32_FUNCTION(10, "QUADSPI_BK1_IO1"),
891 STM32_FUNCTION(11, "SAI2_FS_A"), 945 STM32_FUNCTION(11, "SAI2_FS_A"),
892 STM32_FUNCTION(13, "FMC_A17 FMC_ALE"), 946 STM32_FUNCTION(13, "FMC_ALE FMC_A17"),
893 STM32_FUNCTION(16, "EVENTOUT"), 947 STM32_FUNCTION(16, "EVENTOUT"),
894 STM32_FUNCTION(17, "ANALOG") 948 STM32_FUNCTION(17, "ANALOG")
895 ), 949 ),
896 STM32_PIN( 950 STM32_PIN_PKG(
897 PINCTRL_PIN(61, "PD13"), 951 PINCTRL_PIN(61, "PD13"),
952 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
898 STM32_FUNCTION(0, "GPIOD13"), 953 STM32_FUNCTION(0, "GPIOD13"),
899 STM32_FUNCTION(2, "LPTIM1_OUT"), 954 STM32_FUNCTION(2, "LPTIM1_OUT"),
900 STM32_FUNCTION(3, "TIM4_CH2"), 955 STM32_FUNCTION(3, "TIM4_CH2"),
901 STM32_FUNCTION(5, "I2C4_SDA"), 956 STM32_FUNCTION(5, "I2C4_SDA"),
902 STM32_FUNCTION(6, "I2C1_SDA"), 957 STM32_FUNCTION(6, "I2C1_SDA"),
903 STM32_FUNCTION(7, "I2S3_MCK"), 958 STM32_FUNCTION(7, "I2S3_MCK"),
904 STM32_FUNCTION(10, "QUADSPI_BK1_IO3 QUADSPI_BOOTBK1_IO3"), 959 STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
905 STM32_FUNCTION(11, "SAI2_SCK_A"), 960 STM32_FUNCTION(11, "SAI2_SCK_A"),
906 STM32_FUNCTION(13, "FMC_A18"), 961 STM32_FUNCTION(13, "FMC_A18"),
907 STM32_FUNCTION(14, "DSI_TE"), 962 STM32_FUNCTION(14, "DSI_TE"),
908 STM32_FUNCTION(16, "EVENTOUT"), 963 STM32_FUNCTION(16, "EVENTOUT"),
909 STM32_FUNCTION(17, "ANALOG") 964 STM32_FUNCTION(17, "ANALOG")
910 ), 965 ),
911 STM32_PIN( 966 STM32_PIN_PKG(
912 PINCTRL_PIN(62, "PD14"), 967 PINCTRL_PIN(62, "PD14"),
968 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
913 STM32_FUNCTION(0, "GPIOD14"), 969 STM32_FUNCTION(0, "GPIOD14"),
914 STM32_FUNCTION(3, "TIM4_CH3"), 970 STM32_FUNCTION(3, "TIM4_CH3"),
915 STM32_FUNCTION(7, "SAI3_MCLK_B"), 971 STM32_FUNCTION(7, "SAI3_MCLK_B"),
916 STM32_FUNCTION(9, "UART8_CTS UART_BOOT8_CTS"), 972 STM32_FUNCTION(9, "UART8_CTS"),
917 STM32_FUNCTION(13, "FMC_D0"), 973 STM32_FUNCTION(13, "FMC_D0 FMC_DA0"),
918 STM32_FUNCTION(16, "EVENTOUT"), 974 STM32_FUNCTION(16, "EVENTOUT"),
919 STM32_FUNCTION(17, "ANALOG") 975 STM32_FUNCTION(17, "ANALOG")
920 ), 976 ),
921 STM32_PIN( 977 STM32_PIN_PKG(
922 PINCTRL_PIN(63, "PD15"), 978 PINCTRL_PIN(63, "PD15"),
979 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
923 STM32_FUNCTION(0, "GPIOD15"), 980 STM32_FUNCTION(0, "GPIOD15"),
924 STM32_FUNCTION(3, "TIM4_CH4"), 981 STM32_FUNCTION(3, "TIM4_CH4"),
925 STM32_FUNCTION(7, "SAI3_MCLK_A"), 982 STM32_FUNCTION(7, "SAI3_MCLK_A"),
926 STM32_FUNCTION(9, "UART8_CTS UART_BOOT8_CTS"), 983 STM32_FUNCTION(9, "UART8_CTS"),
927 STM32_FUNCTION(13, "FMC_D1"), 984 STM32_FUNCTION(13, "FMC_D1 FMC_DA1"),
985 STM32_FUNCTION(15, "LCD_R1"),
928 STM32_FUNCTION(16, "EVENTOUT"), 986 STM32_FUNCTION(16, "EVENTOUT"),
929 STM32_FUNCTION(17, "ANALOG") 987 STM32_FUNCTION(17, "ANALOG")
930 ), 988 ),
931 STM32_PIN( 989 STM32_PIN_PKG(
932 PINCTRL_PIN(64, "PE0"), 990 PINCTRL_PIN(64, "PE0"),
991 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
933 STM32_FUNCTION(0, "GPIOE0"), 992 STM32_FUNCTION(0, "GPIOE0"),
934 STM32_FUNCTION(2, "LPTIM1_ETR"), 993 STM32_FUNCTION(2, "LPTIM1_ETR"),
935 STM32_FUNCTION(3, "TIM4_ETR"), 994 STM32_FUNCTION(3, "TIM4_ETR"),
936 STM32_FUNCTION(5, "LPTIM2_ETR"), 995 STM32_FUNCTION(5, "LPTIM2_ETR"),
937 STM32_FUNCTION(6, "SPI3_SCK I2S3_CK"), 996 STM32_FUNCTION(6, "SPI3_SCK I2S3_CK"),
938 STM32_FUNCTION(7, "SAI4_MCLK_B"), 997 STM32_FUNCTION(7, "SAI4_MCLK_B"),
939 STM32_FUNCTION(9, "UART8_RX UART_BOOT8_RX"), 998 STM32_FUNCTION(9, "UART8_RX"),
940 STM32_FUNCTION(10, "CAN1_RXFD"),
941 STM32_FUNCTION(11, "SAI2_MCLK_A"), 999 STM32_FUNCTION(11, "SAI2_MCLK_A"),
942 STM32_FUNCTION(13, "FMC_NBL0"), 1000 STM32_FUNCTION(13, "FMC_NBL0"),
943 STM32_FUNCTION(14, "DCMI_D2"), 1001 STM32_FUNCTION(14, "DCMI_D2"),
944 STM32_FUNCTION(16, "EVENTOUT"), 1002 STM32_FUNCTION(16, "EVENTOUT"),
945 STM32_FUNCTION(17, "ANALOG") 1003 STM32_FUNCTION(17, "ANALOG")
946 ), 1004 ),
947 STM32_PIN( 1005 STM32_PIN_PKG(
948 PINCTRL_PIN(65, "PE1"), 1006 PINCTRL_PIN(65, "PE1"),
1007 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
949 STM32_FUNCTION(0, "GPIOE1"), 1008 STM32_FUNCTION(0, "GPIOE1"),
950 STM32_FUNCTION(2, "LPTIM1_IN2"), 1009 STM32_FUNCTION(2, "LPTIM1_IN2"),
951 STM32_FUNCTION(6, "I2S2_MCK"), 1010 STM32_FUNCTION(6, "I2S2_MCK"),
952 STM32_FUNCTION(7, "SAI3_SD_B"), 1011 STM32_FUNCTION(7, "SAI3_SD_B"),
953 STM32_FUNCTION(9, "UART8_TX UART_BOOT8_TX"), 1012 STM32_FUNCTION(9, "UART8_TX"),
954 STM32_FUNCTION(10, "CAN1_TXFD"),
955 STM32_FUNCTION(13, "FMC_NBL1"), 1013 STM32_FUNCTION(13, "FMC_NBL1"),
956 STM32_FUNCTION(14, "DCMI_D3"), 1014 STM32_FUNCTION(14, "DCMI_D3"),
957 STM32_FUNCTION(16, "EVENTOUT"), 1015 STM32_FUNCTION(16, "EVENTOUT"),
958 STM32_FUNCTION(17, "ANALOG") 1016 STM32_FUNCTION(17, "ANALOG")
959 ), 1017 ),
960 STM32_PIN( 1018 STM32_PIN_PKG(
961 PINCTRL_PIN(66, "PE2"), 1019 PINCTRL_PIN(66, "PE2"),
1020 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
962 STM32_FUNCTION(0, "GPIOE2"), 1021 STM32_FUNCTION(0, "GPIOE2"),
963 STM32_FUNCTION(1, "TRACECLK"), 1022 STM32_FUNCTION(1, "TRACECLK"),
964 STM32_FUNCTION(3, "SAI1_CK1"), 1023 STM32_FUNCTION(3, "SAI1_CK1"),
965 STM32_FUNCTION(5, "I2C4_SCL"), 1024 STM32_FUNCTION(5, "I2C4_SCL"),
966 STM32_FUNCTION(6, "SPI4_SCK"), 1025 STM32_FUNCTION(6, "SPI4_SCK"),
967 STM32_FUNCTION(7, "SAI1_MCLK_A"), 1026 STM32_FUNCTION(7, "SAI1_MCLK_A"),
968 STM32_FUNCTION(10, "QUADSPI_BK1_IO2 QUADSPI_BOOTBK1_IO2"), 1027 STM32_FUNCTION(10, "QUADSPI_BK1_IO2"),
969 STM32_FUNCTION(12, "ETH_GMII_TXD3 ETH_MII_TXD3 ETH_RGMII_TXD3"), 1028 STM32_FUNCTION(12, "ETH1_GMII_TXD3 ETH1_MII_TXD3 ETH1_RGMII_TXD3"),
970 STM32_FUNCTION(13, "FMC_A23"), 1029 STM32_FUNCTION(13, "FMC_A23"),
971 STM32_FUNCTION(16, "EVENTOUT"), 1030 STM32_FUNCTION(16, "EVENTOUT"),
972 STM32_FUNCTION(17, "ANALOG") 1031 STM32_FUNCTION(17, "ANALOG")
973 ), 1032 ),
974 STM32_PIN( 1033 STM32_PIN_PKG(
975 PINCTRL_PIN(67, "PE3"), 1034 PINCTRL_PIN(67, "PE3"),
1035 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
976 STM32_FUNCTION(0, "GPIOE3"), 1036 STM32_FUNCTION(0, "GPIOE3"),
977 STM32_FUNCTION(1, "TRACED0"), 1037 STM32_FUNCTION(1, "TRACED0"),
978 STM32_FUNCTION(5, "TIM15_BKIN"), 1038 STM32_FUNCTION(5, "TIM15_BKIN"),
979 STM32_FUNCTION(7, "SAI1_SD_B"), 1039 STM32_FUNCTION(7, "SAI1_SD_B"),
980 STM32_FUNCTION(10, "SDMMC2_CK SDMMC_BOOT2_CK"), 1040 STM32_FUNCTION(10, "SDMMC2_CK"),
981 STM32_FUNCTION(13, "FMC_A19"), 1041 STM32_FUNCTION(13, "FMC_A19"),
982 STM32_FUNCTION(16, "EVENTOUT"), 1042 STM32_FUNCTION(16, "EVENTOUT"),
983 STM32_FUNCTION(17, "ANALOG") 1043 STM32_FUNCTION(17, "ANALOG")
984 ), 1044 ),
985 STM32_PIN( 1045 STM32_PIN_PKG(
986 PINCTRL_PIN(68, "PE4"), 1046 PINCTRL_PIN(68, "PE4"),
1047 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
987 STM32_FUNCTION(0, "GPIOE4"), 1048 STM32_FUNCTION(0, "GPIOE4"),
988 STM32_FUNCTION(1, "TRACED1"), 1049 STM32_FUNCTION(1, "TRACED1"),
989 STM32_FUNCTION(3, "SAI1_D2"), 1050 STM32_FUNCTION(3, "SAI1_D2"),
990 STM32_FUNCTION(4, "DFSDM_DATA3"), 1051 STM32_FUNCTION(4, "DFSDM1_DATIN3"),
991 STM32_FUNCTION(5, "TIM15_CH1N"), 1052 STM32_FUNCTION(5, "TIM15_CH1N"),
992 STM32_FUNCTION(6, "SPI4_NSS"), 1053 STM32_FUNCTION(6, "SPI4_NSS"),
993 STM32_FUNCTION(7, "SAI1_FS_A"), 1054 STM32_FUNCTION(7, "SAI1_FS_A"),
994 STM32_FUNCTION(8, "SDMMC2_CKIN SDMMC_BOOT2_CKIN"), 1055 STM32_FUNCTION(8, "SDMMC2_CKIN"),
995 STM32_FUNCTION(9, "SDMMC1_CKIN SDMMC_BOOT1_CKIN"), 1056 STM32_FUNCTION(9, "SDMMC1_CKIN"),
996 STM32_FUNCTION(10, "SDMMC2_D4 SDMMC_BOOT2_D4"), 1057 STM32_FUNCTION(10, "SDMMC2_D4"),
997 STM32_FUNCTION(12, "SDMMC1_D4 SDMMC_BOOT1_D4"), 1058 STM32_FUNCTION(12, "SDMMC1_D4"),
998 STM32_FUNCTION(13, "FMC_A20"), 1059 STM32_FUNCTION(13, "FMC_A20"),
999 STM32_FUNCTION(14, "DCMI_D4"), 1060 STM32_FUNCTION(14, "DCMI_D4"),
1000 STM32_FUNCTION(15, "LCD_B0"), 1061 STM32_FUNCTION(15, "LCD_B0"),
1001 STM32_FUNCTION(16, "EVENTOUT"), 1062 STM32_FUNCTION(16, "EVENTOUT"),
1002 STM32_FUNCTION(17, "ANALOG") 1063 STM32_FUNCTION(17, "ANALOG")
1003 ), 1064 ),
1004 STM32_PIN( 1065 STM32_PIN_PKG(
1005 PINCTRL_PIN(69, "PE5"), 1066 PINCTRL_PIN(69, "PE5"),
1067 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1006 STM32_FUNCTION(0, "GPIOE5"), 1068 STM32_FUNCTION(0, "GPIOE5"),
1007 STM32_FUNCTION(1, "TRACED3"), 1069 STM32_FUNCTION(1, "TRACED3"),
1008 STM32_FUNCTION(3, "SAI1_CK2"), 1070 STM32_FUNCTION(3, "SAI1_CK2"),
1009 STM32_FUNCTION(4, "DFSDM_CK3"), 1071 STM32_FUNCTION(4, "DFSDM1_CKIN3"),
1010 STM32_FUNCTION(5, "TIM15_CH1"), 1072 STM32_FUNCTION(5, "TIM15_CH1"),
1011 STM32_FUNCTION(6, "SPI4_MISO"), 1073 STM32_FUNCTION(6, "SPI4_MISO"),
1012 STM32_FUNCTION(7, "SAI1_SCK_A"), 1074 STM32_FUNCTION(7, "SAI1_SCK_A"),
1013 STM32_FUNCTION(8, "SDMMC2_D0DIR SDMMC_BOOT2_D0DIR"), 1075 STM32_FUNCTION(8, "SDMMC2_D0DIR"),
1014 STM32_FUNCTION(9, "SDMMC1_D0DIR SDMMC_BOOT1_D0DIR"), 1076 STM32_FUNCTION(9, "SDMMC1_D0DIR"),
1015 STM32_FUNCTION(10, "SDMMC2_D6 SDMMC_BOOT2_D6"), 1077 STM32_FUNCTION(10, "SDMMC2_D6"),
1016 STM32_FUNCTION(12, "SDMMC1_D6 SDMMC_BOOT1_D6"), 1078 STM32_FUNCTION(12, "SDMMC1_D6"),
1017 STM32_FUNCTION(13, "FMC_A21"), 1079 STM32_FUNCTION(13, "FMC_A21"),
1018 STM32_FUNCTION(14, "DCMI_D6"), 1080 STM32_FUNCTION(14, "DCMI_D6"),
1019 STM32_FUNCTION(15, "LCD_G0"), 1081 STM32_FUNCTION(15, "LCD_G0"),
1020 STM32_FUNCTION(16, "EVENTOUT"), 1082 STM32_FUNCTION(16, "EVENTOUT"),
1021 STM32_FUNCTION(17, "ANALOG") 1083 STM32_FUNCTION(17, "ANALOG")
1022 ), 1084 ),
1023 STM32_PIN( 1085 STM32_PIN_PKG(
1024 PINCTRL_PIN(70, "PE6"), 1086 PINCTRL_PIN(70, "PE6"),
1087 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1025 STM32_FUNCTION(0, "GPIOE6"), 1088 STM32_FUNCTION(0, "GPIOE6"),
1026 STM32_FUNCTION(1, "TRACED2"), 1089 STM32_FUNCTION(1, "TRACED2"),
1027 STM32_FUNCTION(2, "TIM1_BKIN2"), 1090 STM32_FUNCTION(2, "TIM1_BKIN2"),
@@ -1030,7 +1093,7 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1030 STM32_FUNCTION(6, "SPI4_MOSI"), 1093 STM32_FUNCTION(6, "SPI4_MOSI"),
1031 STM32_FUNCTION(7, "SAI1_SD_A"), 1094 STM32_FUNCTION(7, "SAI1_SD_A"),
1032 STM32_FUNCTION(8, "SDMMC2_D0"), 1095 STM32_FUNCTION(8, "SDMMC2_D0"),
1033 STM32_FUNCTION(9, "SDMMC1_D2 SDMMC_BOOT1_D2"), 1096 STM32_FUNCTION(9, "SDMMC1_D2"),
1034 STM32_FUNCTION(11, "SAI2_MCLK_B"), 1097 STM32_FUNCTION(11, "SAI2_MCLK_B"),
1035 STM32_FUNCTION(13, "FMC_A22"), 1098 STM32_FUNCTION(13, "FMC_A22"),
1036 STM32_FUNCTION(14, "DCMI_D7"), 1099 STM32_FUNCTION(14, "DCMI_D7"),
@@ -1038,119 +1101,132 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1038 STM32_FUNCTION(16, "EVENTOUT"), 1101 STM32_FUNCTION(16, "EVENTOUT"),
1039 STM32_FUNCTION(17, "ANALOG") 1102 STM32_FUNCTION(17, "ANALOG")
1040 ), 1103 ),
1041 STM32_PIN( 1104 STM32_PIN_PKG(
1042 PINCTRL_PIN(71, "PE7"), 1105 PINCTRL_PIN(71, "PE7"),
1106 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1043 STM32_FUNCTION(0, "GPIOE7"), 1107 STM32_FUNCTION(0, "GPIOE7"),
1044 STM32_FUNCTION(2, "TIM1_ETR"), 1108 STM32_FUNCTION(2, "TIM1_ETR"),
1045 STM32_FUNCTION(3, "TIM3_ETR"), 1109 STM32_FUNCTION(3, "TIM3_ETR"),
1046 STM32_FUNCTION(4, "DFSDM_DATA2"), 1110 STM32_FUNCTION(4, "DFSDM1_DATIN2"),
1047 STM32_FUNCTION(8, "UART7_RX"), 1111 STM32_FUNCTION(8, "UART7_RX"),
1048 STM32_FUNCTION(11, "QUADSPI_BK2_IO0 QUADSPI_BOOTBK2_IO0"), 1112 STM32_FUNCTION(11, "QUADSPI_BK2_IO0"),
1049 STM32_FUNCTION(13, "FMC_D4"), 1113 STM32_FUNCTION(13, "FMC_D4 FMC_DA4"),
1050 STM32_FUNCTION(16, "EVENTOUT"), 1114 STM32_FUNCTION(16, "EVENTOUT"),
1051 STM32_FUNCTION(17, "ANALOG") 1115 STM32_FUNCTION(17, "ANALOG")
1052 ), 1116 ),
1053 STM32_PIN( 1117 STM32_PIN_PKG(
1054 PINCTRL_PIN(72, "PE8"), 1118 PINCTRL_PIN(72, "PE8"),
1119 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1055 STM32_FUNCTION(0, "GPIOE8"), 1120 STM32_FUNCTION(0, "GPIOE8"),
1056 STM32_FUNCTION(2, "TIM1_CH1N"), 1121 STM32_FUNCTION(2, "TIM1_CH1N"),
1057 STM32_FUNCTION(4, "DFSDM_CK2"), 1122 STM32_FUNCTION(4, "DFSDM1_CKIN2"),
1058 STM32_FUNCTION(8, "UART7_TX"), 1123 STM32_FUNCTION(8, "UART7_TX"),
1059 STM32_FUNCTION(11, "QUADSPI_BK2_IO1 QUADSPI_BOOTBK2_IO1"), 1124 STM32_FUNCTION(11, "QUADSPI_BK2_IO1"),
1060 STM32_FUNCTION(13, "FMC_D5"), 1125 STM32_FUNCTION(13, "FMC_D5 FMC_DA5"),
1061 STM32_FUNCTION(16, "EVENTOUT"), 1126 STM32_FUNCTION(16, "EVENTOUT"),
1062 STM32_FUNCTION(17, "ANALOG") 1127 STM32_FUNCTION(17, "ANALOG")
1063 ), 1128 ),
1064 STM32_PIN( 1129 STM32_PIN_PKG(
1065 PINCTRL_PIN(73, "PE9"), 1130 PINCTRL_PIN(73, "PE9"),
1131 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1066 STM32_FUNCTION(0, "GPIOE9"), 1132 STM32_FUNCTION(0, "GPIOE9"),
1067 STM32_FUNCTION(2, "TIM1_CH1"), 1133 STM32_FUNCTION(2, "TIM1_CH1"),
1068 STM32_FUNCTION(4, "DFSDM_CKOUT"), 1134 STM32_FUNCTION(4, "DFSDM1_CKOUT"),
1069 STM32_FUNCTION(8, "UART7_RTS UART_BOOT7_RTS"), 1135 STM32_FUNCTION(8, "UART7_RTS UART7_DE"),
1070 STM32_FUNCTION(11, "QUADSPI_BK2_IO2 QUADSPI_BOOTBK2_IO2"), 1136 STM32_FUNCTION(11, "QUADSPI_BK2_IO2"),
1071 STM32_FUNCTION(13, "FMC_D6"), 1137 STM32_FUNCTION(13, "FMC_D6 FMC_DA6"),
1072 STM32_FUNCTION(16, "EVENTOUT"), 1138 STM32_FUNCTION(16, "EVENTOUT"),
1073 STM32_FUNCTION(17, "ANALOG") 1139 STM32_FUNCTION(17, "ANALOG")
1074 ), 1140 ),
1075 STM32_PIN( 1141 STM32_PIN_PKG(
1076 PINCTRL_PIN(74, "PE10"), 1142 PINCTRL_PIN(74, "PE10"),
1143 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1077 STM32_FUNCTION(0, "GPIOE10"), 1144 STM32_FUNCTION(0, "GPIOE10"),
1078 STM32_FUNCTION(2, "TIM1_CH2N"), 1145 STM32_FUNCTION(2, "TIM1_CH2N"),
1079 STM32_FUNCTION(4, "DFSDM_DATA4"), 1146 STM32_FUNCTION(4, "DFSDM1_DATIN4"),
1080 STM32_FUNCTION(8, "UART7_CTS UART_BOOT7_CTS"), 1147 STM32_FUNCTION(8, "UART7_CTS"),
1081 STM32_FUNCTION(11, "QUADSPI_BK2_IO3 QUADSPI_BOOTBK2_IO3"), 1148 STM32_FUNCTION(11, "QUADSPI_BK2_IO3"),
1082 STM32_FUNCTION(13, "FMC_D7"), 1149 STM32_FUNCTION(13, "FMC_D7 FMC_DA7"),
1083 STM32_FUNCTION(16, "EVENTOUT"), 1150 STM32_FUNCTION(16, "EVENTOUT"),
1084 STM32_FUNCTION(17, "ANALOG") 1151 STM32_FUNCTION(17, "ANALOG")
1085 ), 1152 ),
1086 STM32_PIN( 1153 STM32_PIN_PKG(
1087 PINCTRL_PIN(75, "PE11"), 1154 PINCTRL_PIN(75, "PE11"),
1155 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1088 STM32_FUNCTION(0, "GPIOE11"), 1156 STM32_FUNCTION(0, "GPIOE11"),
1089 STM32_FUNCTION(2, "TIM1_CH2"), 1157 STM32_FUNCTION(2, "TIM1_CH2"),
1090 STM32_FUNCTION(4, "DFSDM_CK4"), 1158 STM32_FUNCTION(4, "DFSDM1_CKIN4"),
1091 STM32_FUNCTION(6, "SPI4_NSS"), 1159 STM32_FUNCTION(6, "SPI4_NSS"),
1092 STM32_FUNCTION(8, "USART6_CK USART_BOOT6_CK"), 1160 STM32_FUNCTION(8, "USART6_CK"),
1093 STM32_FUNCTION(11, "SAI2_SD_B"), 1161 STM32_FUNCTION(11, "SAI2_SD_B"),
1094 STM32_FUNCTION(13, "FMC_D8"), 1162 STM32_FUNCTION(13, "FMC_D8 FMC_DA8"),
1163 STM32_FUNCTION(14, "DCMI_D4"),
1095 STM32_FUNCTION(15, "LCD_G3"), 1164 STM32_FUNCTION(15, "LCD_G3"),
1096 STM32_FUNCTION(16, "EVENTOUT"), 1165 STM32_FUNCTION(16, "EVENTOUT"),
1097 STM32_FUNCTION(17, "ANALOG") 1166 STM32_FUNCTION(17, "ANALOG")
1098 ), 1167 ),
1099 STM32_PIN( 1168 STM32_PIN_PKG(
1100 PINCTRL_PIN(76, "PE12"), 1169 PINCTRL_PIN(76, "PE12"),
1170 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1101 STM32_FUNCTION(0, "GPIOE12"), 1171 STM32_FUNCTION(0, "GPIOE12"),
1102 STM32_FUNCTION(2, "TIM1_CH3N"), 1172 STM32_FUNCTION(2, "TIM1_CH3N"),
1103 STM32_FUNCTION(4, "DFSDM_DATA5"), 1173 STM32_FUNCTION(4, "DFSDM1_DATIN5"),
1104 STM32_FUNCTION(6, "SPI4_SCK"), 1174 STM32_FUNCTION(6, "SPI4_SCK"),
1105 STM32_FUNCTION(9, "SDMMC1_D0DIR SDMMC_BOOT1_D0DIR"), 1175 STM32_FUNCTION(9, "SDMMC1_D0DIR"),
1106 STM32_FUNCTION(11, "SAI2_SCK_B"), 1176 STM32_FUNCTION(11, "SAI2_SCK_B"),
1107 STM32_FUNCTION(13, "FMC_D9"), 1177 STM32_FUNCTION(13, "FMC_D9 FMC_DA9"),
1108 STM32_FUNCTION(15, "LCD_B4"), 1178 STM32_FUNCTION(15, "LCD_B4"),
1109 STM32_FUNCTION(16, "EVENTOUT"), 1179 STM32_FUNCTION(16, "EVENTOUT"),
1110 STM32_FUNCTION(17, "ANALOG") 1180 STM32_FUNCTION(17, "ANALOG")
1111 ), 1181 ),
1112 STM32_PIN( 1182 STM32_PIN_PKG(
1113 PINCTRL_PIN(77, "PE13"), 1183 PINCTRL_PIN(77, "PE13"),
1184 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1114 STM32_FUNCTION(0, "GPIOE13"), 1185 STM32_FUNCTION(0, "GPIOE13"),
1115 STM32_FUNCTION(1, "HDP2"), 1186 STM32_FUNCTION(1, "HDP2"),
1116 STM32_FUNCTION(2, "TIM1_CH3"), 1187 STM32_FUNCTION(2, "TIM1_CH3"),
1117 STM32_FUNCTION(4, "DFSDM_CK5"), 1188 STM32_FUNCTION(4, "DFSDM1_CKIN5"),
1118 STM32_FUNCTION(6, "SPI4_MISO"), 1189 STM32_FUNCTION(6, "SPI4_MISO"),
1119 STM32_FUNCTION(11, "SAI2_FS_B"), 1190 STM32_FUNCTION(11, "SAI2_FS_B"),
1120 STM32_FUNCTION(13, "FMC_D10"), 1191 STM32_FUNCTION(13, "FMC_D10 FMC_DA10"),
1192 STM32_FUNCTION(14, "DCMI_D6"),
1121 STM32_FUNCTION(15, "LCD_DE"), 1193 STM32_FUNCTION(15, "LCD_DE"),
1122 STM32_FUNCTION(16, "EVENTOUT"), 1194 STM32_FUNCTION(16, "EVENTOUT"),
1123 STM32_FUNCTION(17, "ANALOG") 1195 STM32_FUNCTION(17, "ANALOG")
1124 ), 1196 ),
1125 STM32_PIN( 1197 STM32_PIN_PKG(
1126 PINCTRL_PIN(78, "PE14"), 1198 PINCTRL_PIN(78, "PE14"),
1199 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1127 STM32_FUNCTION(0, "GPIOE14"), 1200 STM32_FUNCTION(0, "GPIOE14"),
1128 STM32_FUNCTION(2, "TIM1_CH4"), 1201 STM32_FUNCTION(2, "TIM1_CH4"),
1129 STM32_FUNCTION(6, "SPI4_MOSI"), 1202 STM32_FUNCTION(6, "SPI4_MOSI"),
1130 STM32_FUNCTION(9, "UART8_RTS UART_BOOT8_RTS"), 1203 STM32_FUNCTION(9, "UART8_RTS UART8_DE"),
1131 STM32_FUNCTION(11, "SAI2_MCLK_B"), 1204 STM32_FUNCTION(11, "SAI2_MCLK_B"),
1132 STM32_FUNCTION(12, "SDMMC1_D123DIR SDMMC_BOOT1_D123DIR"), 1205 STM32_FUNCTION(12, "SDMMC1_D123DIR"),
1133 STM32_FUNCTION(13, "FMC_D11"), 1206 STM32_FUNCTION(13, "FMC_D11 FMC_DA11"),
1134 STM32_FUNCTION(14, "LCD_G0"), 1207 STM32_FUNCTION(14, "LCD_G0"),
1135 STM32_FUNCTION(15, "LCD_CLK"), 1208 STM32_FUNCTION(15, "LCD_CLK"),
1136 STM32_FUNCTION(16, "EVENTOUT"), 1209 STM32_FUNCTION(16, "EVENTOUT"),
1137 STM32_FUNCTION(17, "ANALOG") 1210 STM32_FUNCTION(17, "ANALOG")
1138 ), 1211 ),
1139 STM32_PIN( 1212 STM32_PIN_PKG(
1140 PINCTRL_PIN(79, "PE15"), 1213 PINCTRL_PIN(79, "PE15"),
1214 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1141 STM32_FUNCTION(0, "GPIOE15"), 1215 STM32_FUNCTION(0, "GPIOE15"),
1142 STM32_FUNCTION(1, "HDP3"), 1216 STM32_FUNCTION(1, "HDP3"),
1143 STM32_FUNCTION(2, "TIM1_BKIN"), 1217 STM32_FUNCTION(2, "TIM1_BKIN"),
1144 STM32_FUNCTION(5, "TIM15_BKIN"), 1218 STM32_FUNCTION(5, "TIM15_BKIN"),
1145 STM32_FUNCTION(8, "USART2_CTS_NSS USART_BOOT2_CTS_NSS"), 1219 STM32_FUNCTION(8, "USART2_CTS USART2_NSS"),
1146 STM32_FUNCTION(9, "UART8_CTS UART_BOOT8_CTS"), 1220 STM32_FUNCTION(9, "UART8_CTS"),
1147 STM32_FUNCTION(13, "FMC_D12"), 1221 STM32_FUNCTION(11, "FMC_NCE2"),
1222 STM32_FUNCTION(13, "FMC_D12 FMC_DA12"),
1148 STM32_FUNCTION(15, "LCD_R7"), 1223 STM32_FUNCTION(15, "LCD_R7"),
1149 STM32_FUNCTION(16, "EVENTOUT"), 1224 STM32_FUNCTION(16, "EVENTOUT"),
1150 STM32_FUNCTION(17, "ANALOG") 1225 STM32_FUNCTION(17, "ANALOG")
1151 ), 1226 ),
1152 STM32_PIN( 1227 STM32_PIN_PKG(
1153 PINCTRL_PIN(80, "PF0"), 1228 PINCTRL_PIN(80, "PF0"),
1229 STM32MP_PKG_AA | STM32MP_PKG_AC,
1154 STM32_FUNCTION(0, "GPIOF0"), 1230 STM32_FUNCTION(0, "GPIOF0"),
1155 STM32_FUNCTION(5, "I2C2_SDA"), 1231 STM32_FUNCTION(5, "I2C2_SDA"),
1156 STM32_FUNCTION(10, "SDMMC3_D0"), 1232 STM32_FUNCTION(10, "SDMMC3_D0"),
@@ -1159,8 +1235,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1159 STM32_FUNCTION(16, "EVENTOUT"), 1235 STM32_FUNCTION(16, "EVENTOUT"),
1160 STM32_FUNCTION(17, "ANALOG") 1236 STM32_FUNCTION(17, "ANALOG")
1161 ), 1237 ),
1162 STM32_PIN( 1238 STM32_PIN_PKG(
1163 PINCTRL_PIN(81, "PF1"), 1239 PINCTRL_PIN(81, "PF1"),
1240 STM32MP_PKG_AA | STM32MP_PKG_AC,
1164 STM32_FUNCTION(0, "GPIOF1"), 1241 STM32_FUNCTION(0, "GPIOF1"),
1165 STM32_FUNCTION(5, "I2C2_SCL"), 1242 STM32_FUNCTION(5, "I2C2_SCL"),
1166 STM32_FUNCTION(10, "SDMMC3_CMD"), 1243 STM32_FUNCTION(10, "SDMMC3_CMD"),
@@ -1169,27 +1246,30 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1169 STM32_FUNCTION(16, "EVENTOUT"), 1246 STM32_FUNCTION(16, "EVENTOUT"),
1170 STM32_FUNCTION(17, "ANALOG") 1247 STM32_FUNCTION(17, "ANALOG")
1171 ), 1248 ),
1172 STM32_PIN( 1249 STM32_PIN_PKG(
1173 PINCTRL_PIN(82, "PF2"), 1250 PINCTRL_PIN(82, "PF2"),
1251 STM32MP_PKG_AA | STM32MP_PKG_AC,
1174 STM32_FUNCTION(0, "GPIOF2"), 1252 STM32_FUNCTION(0, "GPIOF2"),
1175 STM32_FUNCTION(5, "I2C2_SMBA"), 1253 STM32_FUNCTION(5, "I2C2_SMBA"),
1176 STM32_FUNCTION(10, "SDMMC2_D0DIR SDMMC_BOOT2_D0DIR"), 1254 STM32_FUNCTION(10, "SDMMC2_D0DIR"),
1177 STM32_FUNCTION(11, "SDMMC3_D0DIR"), 1255 STM32_FUNCTION(11, "SDMMC3_D0DIR"),
1178 STM32_FUNCTION(12, "SDMMC1_D0DIR SDMMC_BOOT1_D0DIR"), 1256 STM32_FUNCTION(12, "SDMMC1_D0DIR"),
1179 STM32_FUNCTION(13, "FMC_A2"), 1257 STM32_FUNCTION(13, "FMC_A2"),
1180 STM32_FUNCTION(16, "EVENTOUT"), 1258 STM32_FUNCTION(16, "EVENTOUT"),
1181 STM32_FUNCTION(17, "ANALOG") 1259 STM32_FUNCTION(17, "ANALOG")
1182 ), 1260 ),
1183 STM32_PIN( 1261 STM32_PIN_PKG(
1184 PINCTRL_PIN(83, "PF3"), 1262 PINCTRL_PIN(83, "PF3"),
1263 STM32MP_PKG_AA | STM32MP_PKG_AC,
1185 STM32_FUNCTION(0, "GPIOF3"), 1264 STM32_FUNCTION(0, "GPIOF3"),
1186 STM32_FUNCTION(12, "ETH_GMII_TX_ER ETH_MII_TX_ER"), 1265 STM32_FUNCTION(12, "ETH1_GMII_TX_ER ETH1_MII_TX_ER"),
1187 STM32_FUNCTION(13, "FMC_A3"), 1266 STM32_FUNCTION(13, "FMC_A3"),
1188 STM32_FUNCTION(16, "EVENTOUT"), 1267 STM32_FUNCTION(16, "EVENTOUT"),
1189 STM32_FUNCTION(17, "ANALOG") 1268 STM32_FUNCTION(17, "ANALOG")
1190 ), 1269 ),
1191 STM32_PIN( 1270 STM32_PIN_PKG(
1192 PINCTRL_PIN(84, "PF4"), 1271 PINCTRL_PIN(84, "PF4"),
1272 STM32MP_PKG_AA | STM32MP_PKG_AC,
1193 STM32_FUNCTION(0, "GPIOF4"), 1273 STM32_FUNCTION(0, "GPIOF4"),
1194 STM32_FUNCTION(8, "USART2_RX"), 1274 STM32_FUNCTION(8, "USART2_RX"),
1195 STM32_FUNCTION(10, "SDMMC3_D1"), 1275 STM32_FUNCTION(10, "SDMMC3_D1"),
@@ -1198,8 +1278,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1198 STM32_FUNCTION(16, "EVENTOUT"), 1278 STM32_FUNCTION(16, "EVENTOUT"),
1199 STM32_FUNCTION(17, "ANALOG") 1279 STM32_FUNCTION(17, "ANALOG")
1200 ), 1280 ),
1201 STM32_PIN( 1281 STM32_PIN_PKG(
1202 PINCTRL_PIN(85, "PF5"), 1282 PINCTRL_PIN(85, "PF5"),
1283 STM32MP_PKG_AA | STM32MP_PKG_AC,
1203 STM32_FUNCTION(0, "GPIOF5"), 1284 STM32_FUNCTION(0, "GPIOF5"),
1204 STM32_FUNCTION(8, "USART2_TX"), 1285 STM32_FUNCTION(8, "USART2_TX"),
1205 STM32_FUNCTION(10, "SDMMC3_D2"), 1286 STM32_FUNCTION(10, "SDMMC3_D2"),
@@ -1207,71 +1288,77 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1207 STM32_FUNCTION(16, "EVENTOUT"), 1288 STM32_FUNCTION(16, "EVENTOUT"),
1208 STM32_FUNCTION(17, "ANALOG") 1289 STM32_FUNCTION(17, "ANALOG")
1209 ), 1290 ),
1210 STM32_PIN( 1291 STM32_PIN_PKG(
1211 PINCTRL_PIN(86, "PF6"), 1292 PINCTRL_PIN(86, "PF6"),
1293 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1212 STM32_FUNCTION(0, "GPIOF6"), 1294 STM32_FUNCTION(0, "GPIOF6"),
1213 STM32_FUNCTION(2, "TIM16_CH1"), 1295 STM32_FUNCTION(2, "TIM16_CH1"),
1214 STM32_FUNCTION(6, "SPI5_NSS"), 1296 STM32_FUNCTION(6, "SPI5_NSS"),
1215 STM32_FUNCTION(7, "SAI1_SD_B"), 1297 STM32_FUNCTION(7, "SAI1_SD_B"),
1216 STM32_FUNCTION(8, "UART7_RX UART_BOOT7_RX"), 1298 STM32_FUNCTION(8, "UART7_RX"),
1217 STM32_FUNCTION(10, "QUADSPI_BK1_IO3 QUADSPI_BOOTBK1_IO3"), 1299 STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
1218 STM32_FUNCTION(13, "SAI4_SCK_B"), 1300 STM32_FUNCTION(13, "SAI4_SCK_B"),
1219 STM32_FUNCTION(16, "EVENTOUT"), 1301 STM32_FUNCTION(16, "EVENTOUT"),
1220 STM32_FUNCTION(17, "ANALOG") 1302 STM32_FUNCTION(17, "ANALOG")
1221 ), 1303 ),
1222 STM32_PIN( 1304 STM32_PIN_PKG(
1223 PINCTRL_PIN(87, "PF7"), 1305 PINCTRL_PIN(87, "PF7"),
1306 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1224 STM32_FUNCTION(0, "GPIOF7"), 1307 STM32_FUNCTION(0, "GPIOF7"),
1225 STM32_FUNCTION(2, "TIM17_CH1"), 1308 STM32_FUNCTION(2, "TIM17_CH1"),
1226 STM32_FUNCTION(6, "SPI5_SCK"), 1309 STM32_FUNCTION(6, "SPI5_SCK"),
1227 STM32_FUNCTION(7, "SAI1_MCLK_B"), 1310 STM32_FUNCTION(7, "SAI1_MCLK_B"),
1228 STM32_FUNCTION(8, "UART7_TX UART_BOOT7_TX"), 1311 STM32_FUNCTION(8, "UART7_TX"),
1229 STM32_FUNCTION(10, "QUADSPI_BK1_IO2 QUADSPI_BOOTBK1_IO2"), 1312 STM32_FUNCTION(10, "QUADSPI_BK1_IO2"),
1230 STM32_FUNCTION(16, "EVENTOUT"), 1313 STM32_FUNCTION(16, "EVENTOUT"),
1231 STM32_FUNCTION(17, "ANALOG") 1314 STM32_FUNCTION(17, "ANALOG")
1232 ), 1315 ),
1233 STM32_PIN( 1316 STM32_PIN_PKG(
1234 PINCTRL_PIN(88, "PF8"), 1317 PINCTRL_PIN(88, "PF8"),
1318 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1235 STM32_FUNCTION(0, "GPIOF8"), 1319 STM32_FUNCTION(0, "GPIOF8"),
1236 STM32_FUNCTION(1, "TRACED12"), 1320 STM32_FUNCTION(1, "TRACED12"),
1237 STM32_FUNCTION(2, "TIM16_CH1N"), 1321 STM32_FUNCTION(2, "TIM16_CH1N"),
1238 STM32_FUNCTION(6, "SPI5_MISO"), 1322 STM32_FUNCTION(6, "SPI5_MISO"),
1239 STM32_FUNCTION(7, "SAI1_SCK_B"), 1323 STM32_FUNCTION(7, "SAI1_SCK_B"),
1240 STM32_FUNCTION(8, "UART7_RTS UART_BOOT7_RTS"), 1324 STM32_FUNCTION(8, "UART7_RTS UART7_DE"),
1241 STM32_FUNCTION(10, "TIM13_CH1"), 1325 STM32_FUNCTION(10, "TIM13_CH1"),
1242 STM32_FUNCTION(11, "QUADSPI_BK1_IO0 QUADSPI_BOOTBK1_IO0"), 1326 STM32_FUNCTION(11, "QUADSPI_BK1_IO0"),
1243 STM32_FUNCTION(16, "EVENTOUT"), 1327 STM32_FUNCTION(16, "EVENTOUT"),
1244 STM32_FUNCTION(17, "ANALOG") 1328 STM32_FUNCTION(17, "ANALOG")
1245 ), 1329 ),
1246 STM32_PIN( 1330 STM32_PIN_PKG(
1247 PINCTRL_PIN(89, "PF9"), 1331 PINCTRL_PIN(89, "PF9"),
1332 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1248 STM32_FUNCTION(0, "GPIOF9"), 1333 STM32_FUNCTION(0, "GPIOF9"),
1249 STM32_FUNCTION(1, "TRACED13"), 1334 STM32_FUNCTION(1, "TRACED13"),
1250 STM32_FUNCTION(2, "TIM17_CH1N"), 1335 STM32_FUNCTION(2, "TIM17_CH1N"),
1251 STM32_FUNCTION(6, "SPI5_MOSI"), 1336 STM32_FUNCTION(6, "SPI5_MOSI"),
1252 STM32_FUNCTION(7, "SAI1_FS_B"), 1337 STM32_FUNCTION(7, "SAI1_FS_B"),
1253 STM32_FUNCTION(8, "UART7_CTS UART_BOOT7_CTS"), 1338 STM32_FUNCTION(8, "UART7_CTS"),
1254 STM32_FUNCTION(10, "TIM14_CH1"), 1339 STM32_FUNCTION(10, "TIM14_CH1"),
1255 STM32_FUNCTION(11, "QUADSPI_BK1_IO1 QUADSPI_BOOTBK1_IO1"), 1340 STM32_FUNCTION(11, "QUADSPI_BK1_IO1"),
1256 STM32_FUNCTION(16, "EVENTOUT"), 1341 STM32_FUNCTION(16, "EVENTOUT"),
1257 STM32_FUNCTION(17, "ANALOG") 1342 STM32_FUNCTION(17, "ANALOG")
1258 ), 1343 ),
1259 STM32_PIN( 1344 STM32_PIN_PKG(
1260 PINCTRL_PIN(90, "PF10"), 1345 PINCTRL_PIN(90, "PF10"),
1346 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1261 STM32_FUNCTION(0, "GPIOF10"), 1347 STM32_FUNCTION(0, "GPIOF10"),
1262 STM32_FUNCTION(2, "TIM16_BKIN"), 1348 STM32_FUNCTION(2, "TIM16_BKIN"),
1263 STM32_FUNCTION(3, "SAI1_D3"), 1349 STM32_FUNCTION(3, "SAI1_D3"),
1264 STM32_FUNCTION(4, "SAI4_D4"), 1350 STM32_FUNCTION(4, "SAI4_D4"),
1265 STM32_FUNCTION(7, "SAI1_D4"), 1351 STM32_FUNCTION(7, "SAI1_D4"),
1266 STM32_FUNCTION(10, "QUADSPI_CLK QUADSPI_BOOTCLK"), 1352 STM32_FUNCTION(10, "QUADSPI_CLK"),
1267 STM32_FUNCTION(13, "SAI4_D3"), 1353 STM32_FUNCTION(13, "SAI4_D3"),
1268 STM32_FUNCTION(14, "DCMI_D11"), 1354 STM32_FUNCTION(14, "DCMI_D11"),
1269 STM32_FUNCTION(15, "LCD_DE"), 1355 STM32_FUNCTION(15, "LCD_DE"),
1270 STM32_FUNCTION(16, "EVENTOUT"), 1356 STM32_FUNCTION(16, "EVENTOUT"),
1271 STM32_FUNCTION(17, "ANALOG") 1357 STM32_FUNCTION(17, "ANALOG")
1272 ), 1358 ),
1273 STM32_PIN( 1359 STM32_PIN_PKG(
1274 PINCTRL_PIN(91, "PF11"), 1360 PINCTRL_PIN(91, "PF11"),
1361 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1275 STM32_FUNCTION(0, "GPIOF11"), 1362 STM32_FUNCTION(0, "GPIOF11"),
1276 STM32_FUNCTION(6, "SPI5_MOSI"), 1363 STM32_FUNCTION(6, "SPI5_MOSI"),
1277 STM32_FUNCTION(11, "SAI2_SD_B"), 1364 STM32_FUNCTION(11, "SAI2_SD_B"),
@@ -1280,138 +1367,151 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1280 STM32_FUNCTION(16, "EVENTOUT"), 1367 STM32_FUNCTION(16, "EVENTOUT"),
1281 STM32_FUNCTION(17, "ANALOG") 1368 STM32_FUNCTION(17, "ANALOG")
1282 ), 1369 ),
1283 STM32_PIN( 1370 STM32_PIN_PKG(
1284 PINCTRL_PIN(92, "PF12"), 1371 PINCTRL_PIN(92, "PF12"),
1372 STM32MP_PKG_AA | STM32MP_PKG_AC,
1285 STM32_FUNCTION(0, "GPIOF12"), 1373 STM32_FUNCTION(0, "GPIOF12"),
1286 STM32_FUNCTION(1, "TRACED4"), 1374 STM32_FUNCTION(1, "TRACED4"),
1287 STM32_FUNCTION(12, "ETH_GMII_RXD4"), 1375 STM32_FUNCTION(12, "ETH1_GMII_RXD4"),
1288 STM32_FUNCTION(13, "FMC_A6"), 1376 STM32_FUNCTION(13, "FMC_A6"),
1289 STM32_FUNCTION(16, "EVENTOUT"), 1377 STM32_FUNCTION(16, "EVENTOUT"),
1290 STM32_FUNCTION(17, "ANALOG") 1378 STM32_FUNCTION(17, "ANALOG")
1291 ), 1379 ),
1292 STM32_PIN( 1380 STM32_PIN_PKG(
1293 PINCTRL_PIN(93, "PF13"), 1381 PINCTRL_PIN(93, "PF13"),
1382 STM32MP_PKG_AA | STM32MP_PKG_AC,
1294 STM32_FUNCTION(0, "GPIOF13"), 1383 STM32_FUNCTION(0, "GPIOF13"),
1295 STM32_FUNCTION(1, "TRACED5"), 1384 STM32_FUNCTION(1, "TRACED5"),
1296 STM32_FUNCTION(4, "DFSDM_DATA6"), 1385 STM32_FUNCTION(4, "DFSDM1_DATIN6"),
1297 STM32_FUNCTION(5, "I2C4_SMBA"), 1386 STM32_FUNCTION(5, "I2C4_SMBA"),
1298 STM32_FUNCTION(6, "I2C1_SMBA"), 1387 STM32_FUNCTION(6, "I2C1_SMBA"),
1299 STM32_FUNCTION(7, "DFSDM_DATA3"), 1388 STM32_FUNCTION(7, "DFSDM1_DATIN3"),
1300 STM32_FUNCTION(12, "ETH_GMII_RXD5"), 1389 STM32_FUNCTION(12, "ETH1_GMII_RXD5"),
1301 STM32_FUNCTION(13, "FMC_A7"), 1390 STM32_FUNCTION(13, "FMC_A7"),
1302 STM32_FUNCTION(16, "EVENTOUT"), 1391 STM32_FUNCTION(16, "EVENTOUT"),
1303 STM32_FUNCTION(17, "ANALOG") 1392 STM32_FUNCTION(17, "ANALOG")
1304 ), 1393 ),
1305 STM32_PIN( 1394 STM32_PIN_PKG(
1306 PINCTRL_PIN(94, "PF14"), 1395 PINCTRL_PIN(94, "PF14"),
1396 STM32MP_PKG_AA | STM32MP_PKG_AC,
1307 STM32_FUNCTION(0, "GPIOF14"), 1397 STM32_FUNCTION(0, "GPIOF14"),
1308 STM32_FUNCTION(1, "TRACED6"), 1398 STM32_FUNCTION(1, "TRACED6"),
1309 STM32_FUNCTION(4, "DFSDM_CK6"), 1399 STM32_FUNCTION(4, "DFSDM1_CKIN6"),
1310 STM32_FUNCTION(5, "I2C4_SCL"), 1400 STM32_FUNCTION(5, "I2C4_SCL"),
1311 STM32_FUNCTION(6, "I2C1_SCL"), 1401 STM32_FUNCTION(6, "I2C1_SCL"),
1312 STM32_FUNCTION(12, "ETH_GMII_RXD6"), 1402 STM32_FUNCTION(12, "ETH1_GMII_RXD6"),
1313 STM32_FUNCTION(13, "FMC_A8"), 1403 STM32_FUNCTION(13, "FMC_A8"),
1314 STM32_FUNCTION(16, "EVENTOUT"), 1404 STM32_FUNCTION(16, "EVENTOUT"),
1315 STM32_FUNCTION(17, "ANALOG") 1405 STM32_FUNCTION(17, "ANALOG")
1316 ), 1406 ),
1317 STM32_PIN( 1407 STM32_PIN_PKG(
1318 PINCTRL_PIN(95, "PF15"), 1408 PINCTRL_PIN(95, "PF15"),
1409 STM32MP_PKG_AA | STM32MP_PKG_AC,
1319 STM32_FUNCTION(0, "GPIOF15"), 1410 STM32_FUNCTION(0, "GPIOF15"),
1320 STM32_FUNCTION(1, "TRACED7"), 1411 STM32_FUNCTION(1, "TRACED7"),
1321 STM32_FUNCTION(5, "I2C4_SDA"), 1412 STM32_FUNCTION(5, "I2C4_SDA"),
1322 STM32_FUNCTION(6, "I2C1_SDA"), 1413 STM32_FUNCTION(6, "I2C1_SDA"),
1323 STM32_FUNCTION(12, "ETH_GMII_RXD7"), 1414 STM32_FUNCTION(12, "ETH1_GMII_RXD7"),
1324 STM32_FUNCTION(13, "FMC_A9"), 1415 STM32_FUNCTION(13, "FMC_A9"),
1325 STM32_FUNCTION(16, "EVENTOUT"), 1416 STM32_FUNCTION(16, "EVENTOUT"),
1326 STM32_FUNCTION(17, "ANALOG") 1417 STM32_FUNCTION(17, "ANALOG")
1327 ), 1418 ),
1328 STM32_PIN( 1419 STM32_PIN_PKG(
1329 PINCTRL_PIN(96, "PG0"), 1420 PINCTRL_PIN(96, "PG0"),
1421 STM32MP_PKG_AA | STM32MP_PKG_AC,
1330 STM32_FUNCTION(0, "GPIOG0"), 1422 STM32_FUNCTION(0, "GPIOG0"),
1331 STM32_FUNCTION(1, "TRACED0"), 1423 STM32_FUNCTION(1, "TRACED0"),
1332 STM32_FUNCTION(4, "DFSDM_DATA0"), 1424 STM32_FUNCTION(4, "DFSDM1_DATIN0"),
1333 STM32_FUNCTION(12, "ETH_GMII_TXD4"), 1425 STM32_FUNCTION(12, "ETH1_GMII_TXD4"),
1334 STM32_FUNCTION(13, "FMC_A10"), 1426 STM32_FUNCTION(13, "FMC_A10"),
1335 STM32_FUNCTION(16, "EVENTOUT"), 1427 STM32_FUNCTION(16, "EVENTOUT"),
1336 STM32_FUNCTION(17, "ANALOG") 1428 STM32_FUNCTION(17, "ANALOG")
1337 ), 1429 ),
1338 STM32_PIN( 1430 STM32_PIN_PKG(
1339 PINCTRL_PIN(97, "PG1"), 1431 PINCTRL_PIN(97, "PG1"),
1432 STM32MP_PKG_AA | STM32MP_PKG_AC,
1340 STM32_FUNCTION(0, "GPIOG1"), 1433 STM32_FUNCTION(0, "GPIOG1"),
1341 STM32_FUNCTION(1, "TRACED1"), 1434 STM32_FUNCTION(1, "TRACED1"),
1342 STM32_FUNCTION(12, "ETH_GMII_TXD5"), 1435 STM32_FUNCTION(12, "ETH1_GMII_TXD5"),
1343 STM32_FUNCTION(13, "FMC_A11"), 1436 STM32_FUNCTION(13, "FMC_A11"),
1344 STM32_FUNCTION(16, "EVENTOUT"), 1437 STM32_FUNCTION(16, "EVENTOUT"),
1345 STM32_FUNCTION(17, "ANALOG") 1438 STM32_FUNCTION(17, "ANALOG")
1346 ), 1439 ),
1347 STM32_PIN( 1440 STM32_PIN_PKG(
1348 PINCTRL_PIN(98, "PG2"), 1441 PINCTRL_PIN(98, "PG2"),
1442 STM32MP_PKG_AA | STM32MP_PKG_AC,
1349 STM32_FUNCTION(0, "GPIOG2"), 1443 STM32_FUNCTION(0, "GPIOG2"),
1350 STM32_FUNCTION(1, "TRACED2"), 1444 STM32_FUNCTION(1, "TRACED2"),
1351 STM32_FUNCTION(2, "MCO2"), 1445 STM32_FUNCTION(2, "MCO2"),
1352 STM32_FUNCTION(4, "TIM8_BKIN"), 1446 STM32_FUNCTION(4, "TIM8_BKIN"),
1353 STM32_FUNCTION(12, "ETH_GMII_TXD6"), 1447 STM32_FUNCTION(12, "ETH1_GMII_TXD6"),
1354 STM32_FUNCTION(13, "FMC_A12"), 1448 STM32_FUNCTION(13, "FMC_A12"),
1355 STM32_FUNCTION(16, "EVENTOUT"), 1449 STM32_FUNCTION(16, "EVENTOUT"),
1356 STM32_FUNCTION(17, "ANALOG") 1450 STM32_FUNCTION(17, "ANALOG")
1357 ), 1451 ),
1358 STM32_PIN( 1452 STM32_PIN_PKG(
1359 PINCTRL_PIN(99, "PG3"), 1453 PINCTRL_PIN(99, "PG3"),
1454 STM32MP_PKG_AA | STM32MP_PKG_AC,
1360 STM32_FUNCTION(0, "GPIOG3"), 1455 STM32_FUNCTION(0, "GPIOG3"),
1361 STM32_FUNCTION(1, "TRACED3"), 1456 STM32_FUNCTION(1, "TRACED3"),
1362 STM32_FUNCTION(4, "TIM8_BKIN2"), 1457 STM32_FUNCTION(4, "TIM8_BKIN2"),
1363 STM32_FUNCTION(5, "DFSDM_CK1"), 1458 STM32_FUNCTION(5, "DFSDM1_CKIN1"),
1364 STM32_FUNCTION(12, "ETH_GMII_TXD7"), 1459 STM32_FUNCTION(12, "ETH1_GMII_TXD7"),
1365 STM32_FUNCTION(13, "FMC_A13"), 1460 STM32_FUNCTION(13, "FMC_A13"),
1366 STM32_FUNCTION(16, "EVENTOUT"), 1461 STM32_FUNCTION(16, "EVENTOUT"),
1367 STM32_FUNCTION(17, "ANALOG") 1462 STM32_FUNCTION(17, "ANALOG")
1368 ), 1463 ),
1369 STM32_PIN( 1464 STM32_PIN_PKG(
1370 PINCTRL_PIN(100, "PG4"), 1465 PINCTRL_PIN(100, "PG4"),
1466 STM32MP_PKG_AA | STM32MP_PKG_AC,
1371 STM32_FUNCTION(0, "GPIOG4"), 1467 STM32_FUNCTION(0, "GPIOG4"),
1372 STM32_FUNCTION(2, "TIM1_BKIN2"), 1468 STM32_FUNCTION(2, "TIM1_BKIN2"),
1373 STM32_FUNCTION(12, "ETH_GMII_GTX_CLK ETH_RGMII_GTX_CLK"), 1469 STM32_FUNCTION(12, "ETH1_GMII_GTX_CLK ETH1_RGMII_GTX_CLK"),
1374 STM32_FUNCTION(13, "FMC_A14"), 1470 STM32_FUNCTION(13, "FMC_A14"),
1375 STM32_FUNCTION(16, "EVENTOUT"), 1471 STM32_FUNCTION(16, "EVENTOUT"),
1376 STM32_FUNCTION(17, "ANALOG") 1472 STM32_FUNCTION(17, "ANALOG")
1377 ), 1473 ),
1378 STM32_PIN( 1474 STM32_PIN_PKG(
1379 PINCTRL_PIN(101, "PG5"), 1475 PINCTRL_PIN(101, "PG5"),
1476 STM32MP_PKG_AA | STM32MP_PKG_AC,
1380 STM32_FUNCTION(0, "GPIOG5"), 1477 STM32_FUNCTION(0, "GPIOG5"),
1381 STM32_FUNCTION(2, "TIM1_ETR"), 1478 STM32_FUNCTION(2, "TIM1_ETR"),
1382 STM32_FUNCTION(12, "ETH_GMII_CLK125 ETH_RGMII_CLK125"), 1479 STM32_FUNCTION(12, "ETH1_GMII_CLK125 ETH1_RGMII_CLK125"),
1383 STM32_FUNCTION(13, "FMC_A15"), 1480 STM32_FUNCTION(13, "FMC_A15"),
1384 STM32_FUNCTION(16, "EVENTOUT"), 1481 STM32_FUNCTION(16, "EVENTOUT"),
1385 STM32_FUNCTION(17, "ANALOG") 1482 STM32_FUNCTION(17, "ANALOG")
1386 ), 1483 ),
1387 STM32_PIN( 1484 STM32_PIN_PKG(
1388 PINCTRL_PIN(102, "PG6"), 1485 PINCTRL_PIN(102, "PG6"),
1486 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1389 STM32_FUNCTION(0, "GPIOG6"), 1487 STM32_FUNCTION(0, "GPIOG6"),
1390 STM32_FUNCTION(1, "TRACED14"), 1488 STM32_FUNCTION(1, "TRACED14"),
1391 STM32_FUNCTION(2, "TIM17_BKIN"), 1489 STM32_FUNCTION(2, "TIM17_BKIN"),
1392 STM32_FUNCTION(11, "SDMMC2_CMD SDMMC_BOOT2_CMD"), 1490 STM32_FUNCTION(11, "SDMMC2_CMD"),
1393 STM32_FUNCTION(14, "DCMI_D12"), 1491 STM32_FUNCTION(14, "DCMI_D12"),
1394 STM32_FUNCTION(15, "LCD_R7"), 1492 STM32_FUNCTION(15, "LCD_R7"),
1395 STM32_FUNCTION(16, "EVENTOUT"), 1493 STM32_FUNCTION(16, "EVENTOUT"),
1396 STM32_FUNCTION(17, "ANALOG") 1494 STM32_FUNCTION(17, "ANALOG")
1397 ), 1495 ),
1398 STM32_PIN( 1496 STM32_PIN_PKG(
1399 PINCTRL_PIN(103, "PG7"), 1497 PINCTRL_PIN(103, "PG7"),
1498 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1400 STM32_FUNCTION(0, "GPIOG7"), 1499 STM32_FUNCTION(0, "GPIOG7"),
1401 STM32_FUNCTION(1, "TRACED5"), 1500 STM32_FUNCTION(1, "TRACED5"),
1402 STM32_FUNCTION(7, "SAI1_MCLK_A"), 1501 STM32_FUNCTION(7, "SAI1_MCLK_A"),
1403 STM32_FUNCTION(8, "USART6_CK USART_BOOT6_CK"), 1502 STM32_FUNCTION(8, "USART6_CK"),
1404 STM32_FUNCTION(9, "UART8_RTS UART_BOOT8_RTS"), 1503 STM32_FUNCTION(9, "UART8_RTS UART8_DE"),
1405 STM32_FUNCTION(10, "QUADSPI_CLK"), 1504 STM32_FUNCTION(10, "QUADSPI_CLK"),
1406 STM32_FUNCTION(12, "QUADSPI_BK2_IO3 QUADSPI_BOOTBK2_IO3"), 1505 STM32_FUNCTION(12, "QUADSPI_BK2_IO3"),
1407 STM32_FUNCTION(13, "FMC_INT"), 1506 STM32_FUNCTION(13, "FMC_INT"),
1408 STM32_FUNCTION(14, "DCMI_D13"), 1507 STM32_FUNCTION(14, "DCMI_D13"),
1409 STM32_FUNCTION(15, "LCD_CLK"), 1508 STM32_FUNCTION(15, "LCD_CLK"),
1410 STM32_FUNCTION(16, "EVENTOUT"), 1509 STM32_FUNCTION(16, "EVENTOUT"),
1411 STM32_FUNCTION(17, "ANALOG") 1510 STM32_FUNCTION(17, "ANALOG")
1412 ), 1511 ),
1413 STM32_PIN( 1512 STM32_PIN_PKG(
1414 PINCTRL_PIN(104, "PG8"), 1513 PINCTRL_PIN(104, "PG8"),
1514 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1415 STM32_FUNCTION(0, "GPIOG8"), 1515 STM32_FUNCTION(0, "GPIOG8"),
1416 STM32_FUNCTION(1, "TRACED15"), 1516 STM32_FUNCTION(1, "TRACED15"),
1417 STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"), 1517 STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
@@ -1419,73 +1519,79 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1419 STM32_FUNCTION(4, "TIM8_ETR"), 1519 STM32_FUNCTION(4, "TIM8_ETR"),
1420 STM32_FUNCTION(6, "SPI6_NSS"), 1520 STM32_FUNCTION(6, "SPI6_NSS"),
1421 STM32_FUNCTION(7, "SAI4_D2"), 1521 STM32_FUNCTION(7, "SAI4_D2"),
1422 STM32_FUNCTION(8, "USART6_RTS USART_BOOT6_RTS"), 1522 STM32_FUNCTION(8, "USART6_RTS USART6_DE"),
1423 STM32_FUNCTION(9, "USART3_RTS"), 1523 STM32_FUNCTION(9, "USART3_RTS USART3_DE"),
1424 STM32_FUNCTION(10, "SPDIF_IN2"), 1524 STM32_FUNCTION(10, "SPDIFRX_IN2"),
1425 STM32_FUNCTION(11, "SAI4_FS_A"), 1525 STM32_FUNCTION(11, "SAI4_FS_A"),
1426 STM32_FUNCTION(12, "ETH_PPS_OUT"), 1526 STM32_FUNCTION(12, "ETH1_PPS_OUT"),
1427 STM32_FUNCTION(15, "LCD_G7"), 1527 STM32_FUNCTION(15, "LCD_G7"),
1428 STM32_FUNCTION(16, "EVENTOUT"), 1528 STM32_FUNCTION(16, "EVENTOUT"),
1429 STM32_FUNCTION(17, "ANALOG") 1529 STM32_FUNCTION(17, "ANALOG")
1430 ), 1530 ),
1431 STM32_PIN( 1531 STM32_PIN_PKG(
1432 PINCTRL_PIN(105, "PG9"), 1532 PINCTRL_PIN(105, "PG9"),
1533 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1433 STM32_FUNCTION(0, "GPIOG9"), 1534 STM32_FUNCTION(0, "GPIOG9"),
1434 STM32_FUNCTION(1, "DBTRGO"), 1535 STM32_FUNCTION(1, "DBTRGO"),
1435 STM32_FUNCTION(8, "USART6_RX"), 1536 STM32_FUNCTION(8, "USART6_RX"),
1436 STM32_FUNCTION(9, "SPDIF_IN3"), 1537 STM32_FUNCTION(9, "SPDIFRX_IN3"),
1437 STM32_FUNCTION(10, "QUADSPI_BK2_IO2 QUADSPI_BOOTBK2_IO2"), 1538 STM32_FUNCTION(10, "QUADSPI_BK2_IO2"),
1438 STM32_FUNCTION(11, "SAI2_FS_B"), 1539 STM32_FUNCTION(11, "SAI2_FS_B"),
1439 STM32_FUNCTION(13, "FMC_NE2 FMC_NCE"), 1540 STM32_FUNCTION(13, "FMC_NCE FMC_NE2"),
1440 STM32_FUNCTION(14, "DCMI_VSYNC"), 1541 STM32_FUNCTION(14, "DCMI_VSYNC"),
1542 STM32_FUNCTION(15, "LCD_R1"),
1441 STM32_FUNCTION(16, "EVENTOUT"), 1543 STM32_FUNCTION(16, "EVENTOUT"),
1442 STM32_FUNCTION(17, "ANALOG") 1544 STM32_FUNCTION(17, "ANALOG")
1443 ), 1545 ),
1444 STM32_PIN( 1546 STM32_PIN_PKG(
1445 PINCTRL_PIN(106, "PG10"), 1547 PINCTRL_PIN(106, "PG10"),
1548 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1446 STM32_FUNCTION(0, "GPIOG10"), 1549 STM32_FUNCTION(0, "GPIOG10"),
1447 STM32_FUNCTION(1, "TRACED10"), 1550 STM32_FUNCTION(1, "TRACED10"),
1448 STM32_FUNCTION(9, "UART8_CTS UART_BOOT8_CTS"), 1551 STM32_FUNCTION(9, "UART8_CTS"),
1449 STM32_FUNCTION(10, "LCD_G3"), 1552 STM32_FUNCTION(10, "LCD_G3"),
1450 STM32_FUNCTION(11, "SAI2_SD_B"), 1553 STM32_FUNCTION(11, "SAI2_SD_B"),
1451 STM32_FUNCTION(12, "QUADSPI_BK2_IO2 QUADSPI_BOOTBK2_IO2"), 1554 STM32_FUNCTION(12, "QUADSPI_BK2_IO2"),
1452 STM32_FUNCTION(13, "FMC_NE3"), 1555 STM32_FUNCTION(13, "FMC_NE3"),
1453 STM32_FUNCTION(14, "DCMI_D2"), 1556 STM32_FUNCTION(14, "DCMI_D2"),
1454 STM32_FUNCTION(15, "LCD_B2"), 1557 STM32_FUNCTION(15, "LCD_B2"),
1455 STM32_FUNCTION(16, "EVENTOUT"), 1558 STM32_FUNCTION(16, "EVENTOUT"),
1456 STM32_FUNCTION(17, "ANALOG") 1559 STM32_FUNCTION(17, "ANALOG")
1457 ), 1560 ),
1458 STM32_PIN( 1561 STM32_PIN_PKG(
1459 PINCTRL_PIN(107, "PG11"), 1562 PINCTRL_PIN(107, "PG11"),
1563 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1460 STM32_FUNCTION(0, "GPIOG11"), 1564 STM32_FUNCTION(0, "GPIOG11"),
1461 STM32_FUNCTION(1, "TRACED11"), 1565 STM32_FUNCTION(1, "TRACED11"),
1462 STM32_FUNCTION(5, "USART1_TX"), 1566 STM32_FUNCTION(5, "USART1_TX"),
1463 STM32_FUNCTION(7, "UART4_TX UART_BOOT4_TX"), 1567 STM32_FUNCTION(7, "UART4_TX"),
1464 STM32_FUNCTION(9, "SPDIF_IN0"), 1568 STM32_FUNCTION(9, "SPDIFRX_IN0"),
1465 STM32_FUNCTION(12, "ETH_GMII_TX_EN ETH_MII_TX_EN ETH_RGMII_TX_CTL ETH_RMII_TX_EN"), 1569 STM32_FUNCTION(12, "ETH1_GMII_TX_EN ETH1_MII_TX_EN ETH1_RGMII_TX_CTL ETH1_RMII_TX_EN"),
1466 STM32_FUNCTION(14, "DCMI_D3"), 1570 STM32_FUNCTION(14, "DCMI_D3"),
1467 STM32_FUNCTION(15, "LCD_B3"), 1571 STM32_FUNCTION(15, "LCD_B3"),
1468 STM32_FUNCTION(16, "EVENTOUT"), 1572 STM32_FUNCTION(16, "EVENTOUT"),
1469 STM32_FUNCTION(17, "ANALOG") 1573 STM32_FUNCTION(17, "ANALOG")
1470 ), 1574 ),
1471 STM32_PIN( 1575 STM32_PIN_PKG(
1472 PINCTRL_PIN(108, "PG12"), 1576 PINCTRL_PIN(108, "PG12"),
1577 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1473 STM32_FUNCTION(0, "GPIOG12"), 1578 STM32_FUNCTION(0, "GPIOG12"),
1474 STM32_FUNCTION(2, "LPTIM1_IN1"), 1579 STM32_FUNCTION(2, "LPTIM1_IN1"),
1475 STM32_FUNCTION(6, "SPI6_MISO"), 1580 STM32_FUNCTION(6, "SPI6_MISO"),
1476 STM32_FUNCTION(7, "SAI4_CK2"), 1581 STM32_FUNCTION(7, "SAI4_CK2"),
1477 STM32_FUNCTION(8, "USART6_RTS USART_BOOT6_RTS"), 1582 STM32_FUNCTION(8, "USART6_RTS USART6_DE"),
1478 STM32_FUNCTION(9, "SPDIF_IN1"), 1583 STM32_FUNCTION(9, "SPDIFRX_IN1"),
1479 STM32_FUNCTION(10, "LCD_B4"), 1584 STM32_FUNCTION(10, "LCD_B4"),
1480 STM32_FUNCTION(11, "SAI4_SCK_A"), 1585 STM32_FUNCTION(11, "SAI4_SCK_A"),
1481 STM32_FUNCTION(12, "ETH_PHY_INTN"), 1586 STM32_FUNCTION(12, "ETH1_PHY_INTN"),
1482 STM32_FUNCTION(13, "FMC_NE4"), 1587 STM32_FUNCTION(13, "FMC_NE4"),
1483 STM32_FUNCTION(15, "LCD_B1"), 1588 STM32_FUNCTION(15, "LCD_B1"),
1484 STM32_FUNCTION(16, "EVENTOUT"), 1589 STM32_FUNCTION(16, "EVENTOUT"),
1485 STM32_FUNCTION(17, "ANALOG") 1590 STM32_FUNCTION(17, "ANALOG")
1486 ), 1591 ),
1487 STM32_PIN( 1592 STM32_PIN_PKG(
1488 PINCTRL_PIN(109, "PG13"), 1593 PINCTRL_PIN(109, "PG13"),
1594 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1489 STM32_FUNCTION(0, "GPIOG13"), 1595 STM32_FUNCTION(0, "GPIOG13"),
1490 STM32_FUNCTION(1, "TRACED0"), 1596 STM32_FUNCTION(1, "TRACED0"),
1491 STM32_FUNCTION(2, "LPTIM1_OUT"), 1597 STM32_FUNCTION(2, "LPTIM1_OUT"),
@@ -1493,79 +1599,86 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1493 STM32_FUNCTION(5, "SAI4_CK1"), 1599 STM32_FUNCTION(5, "SAI4_CK1"),
1494 STM32_FUNCTION(6, "SPI6_SCK"), 1600 STM32_FUNCTION(6, "SPI6_SCK"),
1495 STM32_FUNCTION(7, "SAI1_SCK_A"), 1601 STM32_FUNCTION(7, "SAI1_SCK_A"),
1496 STM32_FUNCTION(8, "USART6_CTS_NSS USART_BOOT6_CTS_NSS"), 1602 STM32_FUNCTION(8, "USART6_CTS USART6_NSS"),
1497 STM32_FUNCTION(11, "SAI4_MCLK_A"), 1603 STM32_FUNCTION(11, "SAI4_MCLK_A"),
1498 STM32_FUNCTION(12, "ETH_GMII_TXD0 ETH_MII_TXD0 ETH_RGMII_TXD0 ETH_RMII_TXD0"), 1604 STM32_FUNCTION(12, "ETH1_GMII_TXD0 ETH1_MII_TXD0 ETH1_RGMII_TXD0 ETH1_RMII_TXD0"),
1499 STM32_FUNCTION(13, "FMC_A24"), 1605 STM32_FUNCTION(13, "FMC_A24"),
1500 STM32_FUNCTION(15, "LCD_R0"), 1606 STM32_FUNCTION(15, "LCD_R0"),
1501 STM32_FUNCTION(16, "EVENTOUT"), 1607 STM32_FUNCTION(16, "EVENTOUT"),
1502 STM32_FUNCTION(17, "ANALOG") 1608 STM32_FUNCTION(17, "ANALOG")
1503 ), 1609 ),
1504 STM32_PIN( 1610 STM32_PIN_PKG(
1505 PINCTRL_PIN(110, "PG14"), 1611 PINCTRL_PIN(110, "PG14"),
1612 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1506 STM32_FUNCTION(0, "GPIOG14"), 1613 STM32_FUNCTION(0, "GPIOG14"),
1507 STM32_FUNCTION(1, "TRACED1"), 1614 STM32_FUNCTION(1, "TRACED1"),
1508 STM32_FUNCTION(2, "LPTIM1_ETR"), 1615 STM32_FUNCTION(2, "LPTIM1_ETR"),
1509 STM32_FUNCTION(6, "SPI6_MOSI"), 1616 STM32_FUNCTION(6, "SPI6_MOSI"),
1510 STM32_FUNCTION(7, "SAI4_D1"), 1617 STM32_FUNCTION(7, "SAI4_D1"),
1511 STM32_FUNCTION(8, "USART6_TX"), 1618 STM32_FUNCTION(8, "USART6_TX"),
1512 STM32_FUNCTION(10, "QUADSPI_BK2_IO3 QUADSPI_BOOTBK2_IO3"), 1619 STM32_FUNCTION(10, "QUADSPI_BK2_IO3"),
1513 STM32_FUNCTION(11, "SAI4_SD_A"), 1620 STM32_FUNCTION(11, "SAI4_SD_A"),
1514 STM32_FUNCTION(12, "ETH_GMII_TXD1 ETH_MII_TXD1 ETH_RGMII_TXD1 ETH_RMII_TXD1"), 1621 STM32_FUNCTION(12, "ETH1_GMII_TXD1 ETH1_MII_TXD1 ETH1_RGMII_TXD1 ETH1_RMII_TXD1"),
1515 STM32_FUNCTION(13, "FMC_A25"), 1622 STM32_FUNCTION(13, "FMC_A25"),
1516 STM32_FUNCTION(15, "LCD_B0"), 1623 STM32_FUNCTION(15, "LCD_B0"),
1517 STM32_FUNCTION(16, "EVENTOUT"), 1624 STM32_FUNCTION(16, "EVENTOUT"),
1518 STM32_FUNCTION(17, "ANALOG") 1625 STM32_FUNCTION(17, "ANALOG")
1519 ), 1626 ),
1520 STM32_PIN( 1627 STM32_PIN_PKG(
1521 PINCTRL_PIN(111, "PG15"), 1628 PINCTRL_PIN(111, "PG15"),
1629 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1522 STM32_FUNCTION(0, "GPIOG15"), 1630 STM32_FUNCTION(0, "GPIOG15"),
1523 STM32_FUNCTION(1, "TRACED7"), 1631 STM32_FUNCTION(1, "TRACED7"),
1524 STM32_FUNCTION(3, "SAI1_D2"), 1632 STM32_FUNCTION(3, "SAI1_D2"),
1525 STM32_FUNCTION(5, "I2C2_SDA"), 1633 STM32_FUNCTION(5, "I2C2_SDA"),
1526 STM32_FUNCTION(7, "SAI1_FS_A"), 1634 STM32_FUNCTION(7, "SAI1_FS_A"),
1527 STM32_FUNCTION(8, "USART6_CTS_NSS USART_BOOT6_CTS_NSS"), 1635 STM32_FUNCTION(8, "USART6_CTS USART6_NSS"),
1528 STM32_FUNCTION(11, "SDMMC3_CK"), 1636 STM32_FUNCTION(11, "SDMMC3_CK"),
1529 STM32_FUNCTION(14, "DCMI_D13"), 1637 STM32_FUNCTION(14, "DCMI_D13"),
1530 STM32_FUNCTION(16, "EVENTOUT"), 1638 STM32_FUNCTION(16, "EVENTOUT"),
1531 STM32_FUNCTION(17, "ANALOG") 1639 STM32_FUNCTION(17, "ANALOG")
1532 ), 1640 ),
1533 STM32_PIN( 1641 STM32_PIN_PKG(
1534 PINCTRL_PIN(112, "PH0"), 1642 PINCTRL_PIN(112, "PH0"),
1643 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1535 STM32_FUNCTION(0, "GPIOH0"), 1644 STM32_FUNCTION(0, "GPIOH0"),
1536 STM32_FUNCTION(16, "EVENTOUT"), 1645 STM32_FUNCTION(16, "EVENTOUT"),
1537 STM32_FUNCTION(17, "ANALOG") 1646 STM32_FUNCTION(17, "ANALOG")
1538 ), 1647 ),
1539 STM32_PIN( 1648 STM32_PIN_PKG(
1540 PINCTRL_PIN(113, "PH1"), 1649 PINCTRL_PIN(113, "PH1"),
1650 STM32MP_PKG_AA | STM32MP_PKG_AC | STM32MP_PKG_AB | STM32MP_PKG_AD,
1541 STM32_FUNCTION(0, "GPIOH1"), 1651 STM32_FUNCTION(0, "GPIOH1"),
1542 STM32_FUNCTION(16, "EVENTOUT"), 1652 STM32_FUNCTION(16, "EVENTOUT"),
1543 STM32_FUNCTION(17, "ANALOG") 1653 STM32_FUNCTION(17, "ANALOG")
1544 ), 1654 ),
1545 STM32_PIN( 1655 STM32_PIN_PKG(
1546 PINCTRL_PIN(114, "PH2"), 1656 PINCTRL_PIN(114, "PH2"),
1657 STM32MP_PKG_AA | STM32MP_PKG_AC,
1547 STM32_FUNCTION(0, "GPIOH2"), 1658 STM32_FUNCTION(0, "GPIOH2"),
1548 STM32_FUNCTION(2, "LPTIM1_IN2"), 1659 STM32_FUNCTION(2, "LPTIM1_IN2"),
1549 STM32_FUNCTION(10, "QUADSPI_BK2_IO0 QUADSPI_BOOTBK2_IO0"), 1660 STM32_FUNCTION(10, "QUADSPI_BK2_IO0"),
1550 STM32_FUNCTION(11, "SAI2_SCK_B"), 1661 STM32_FUNCTION(11, "SAI2_SCK_B"),
1551 STM32_FUNCTION(12, "ETH_GMII_CRS ETH_MII_CRS"), 1662 STM32_FUNCTION(12, "ETH1_GMII_CRS ETH1_MII_CRS"),
1552 STM32_FUNCTION(15, "LCD_R0"), 1663 STM32_FUNCTION(15, "LCD_R0"),
1553 STM32_FUNCTION(16, "EVENTOUT"), 1664 STM32_FUNCTION(16, "EVENTOUT"),
1554 STM32_FUNCTION(17, "ANALOG") 1665 STM32_FUNCTION(17, "ANALOG")
1555 ), 1666 ),
1556 STM32_PIN( 1667 STM32_PIN_PKG(
1557 PINCTRL_PIN(115, "PH3"), 1668 PINCTRL_PIN(115, "PH3"),
1669 STM32MP_PKG_AA | STM32MP_PKG_AC,
1558 STM32_FUNCTION(0, "GPIOH3"), 1670 STM32_FUNCTION(0, "GPIOH3"),
1559 STM32_FUNCTION(4, "DFSDM_CK4"), 1671 STM32_FUNCTION(4, "DFSDM1_CKIN4"),
1560 STM32_FUNCTION(10, "QUADSPI_BK2_IO1 QUADSPI_BOOTBK2_IO1"), 1672 STM32_FUNCTION(10, "QUADSPI_BK2_IO1"),
1561 STM32_FUNCTION(11, "SAI2_MCLK_B"), 1673 STM32_FUNCTION(11, "SAI2_MCLK_B"),
1562 STM32_FUNCTION(12, "ETH_GMII_COL ETH_MII_COL"), 1674 STM32_FUNCTION(12, "ETH1_GMII_COL ETH1_MII_COL"),
1563 STM32_FUNCTION(15, "LCD_R1"), 1675 STM32_FUNCTION(15, "LCD_R1"),
1564 STM32_FUNCTION(16, "EVENTOUT"), 1676 STM32_FUNCTION(16, "EVENTOUT"),
1565 STM32_FUNCTION(17, "ANALOG") 1677 STM32_FUNCTION(17, "ANALOG")
1566 ), 1678 ),
1567 STM32_PIN( 1679 STM32_PIN_PKG(
1568 PINCTRL_PIN(116, "PH4"), 1680 PINCTRL_PIN(116, "PH4"),
1681 STM32MP_PKG_AA | STM32MP_PKG_AC,
1569 STM32_FUNCTION(0, "GPIOH4"), 1682 STM32_FUNCTION(0, "GPIOH4"),
1570 STM32_FUNCTION(5, "I2C2_SCL"), 1683 STM32_FUNCTION(5, "I2C2_SCL"),
1571 STM32_FUNCTION(10, "LCD_G5"), 1684 STM32_FUNCTION(10, "LCD_G5"),
@@ -1573,8 +1686,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1573 STM32_FUNCTION(16, "EVENTOUT"), 1686 STM32_FUNCTION(16, "EVENTOUT"),
1574 STM32_FUNCTION(17, "ANALOG") 1687 STM32_FUNCTION(17, "ANALOG")
1575 ), 1688 ),
1576 STM32_PIN( 1689 STM32_PIN_PKG(
1577 PINCTRL_PIN(117, "PH5"), 1690 PINCTRL_PIN(117, "PH5"),
1691 STM32MP_PKG_AA | STM32MP_PKG_AC,
1578 STM32_FUNCTION(0, "GPIOH5"), 1692 STM32_FUNCTION(0, "GPIOH5"),
1579 STM32_FUNCTION(5, "I2C2_SDA"), 1693 STM32_FUNCTION(5, "I2C2_SDA"),
1580 STM32_FUNCTION(6, "SPI5_NSS"), 1694 STM32_FUNCTION(6, "SPI5_NSS"),
@@ -1582,31 +1696,34 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1582 STM32_FUNCTION(16, "EVENTOUT"), 1696 STM32_FUNCTION(16, "EVENTOUT"),
1583 STM32_FUNCTION(17, "ANALOG") 1697 STM32_FUNCTION(17, "ANALOG")
1584 ), 1698 ),
1585 STM32_PIN( 1699 STM32_PIN_PKG(
1586 PINCTRL_PIN(118, "PH6"), 1700 PINCTRL_PIN(118, "PH6"),
1701 STM32MP_PKG_AA | STM32MP_PKG_AC,
1587 STM32_FUNCTION(0, "GPIOH6"), 1702 STM32_FUNCTION(0, "GPIOH6"),
1588 STM32_FUNCTION(3, "TIM12_CH1"), 1703 STM32_FUNCTION(3, "TIM12_CH1"),
1589 STM32_FUNCTION(5, "I2C2_SMBA"), 1704 STM32_FUNCTION(5, "I2C2_SMBA"),
1590 STM32_FUNCTION(6, "SPI5_SCK"), 1705 STM32_FUNCTION(6, "SPI5_SCK"),
1591 STM32_FUNCTION(12, "ETH_GMII_RXD2 ETH_MII_RXD2 ETH_RGMII_RXD2"), 1706 STM32_FUNCTION(12, "ETH1_GMII_RXD2 ETH1_MII_RXD2 ETH1_RGMII_RXD2"),
1592 STM32_FUNCTION(13, "MDIOS_MDIO"), 1707 STM32_FUNCTION(13, "MDIOS_MDIO"),
1593 STM32_FUNCTION(14, "DCMI_D8"), 1708 STM32_FUNCTION(14, "DCMI_D8"),
1594 STM32_FUNCTION(16, "EVENTOUT"), 1709 STM32_FUNCTION(16, "EVENTOUT"),
1595 STM32_FUNCTION(17, "ANALOG") 1710 STM32_FUNCTION(17, "ANALOG")
1596 ), 1711 ),
1597 STM32_PIN( 1712 STM32_PIN_PKG(
1598 PINCTRL_PIN(119, "PH7"), 1713 PINCTRL_PIN(119, "PH7"),
1714 STM32MP_PKG_AA | STM32MP_PKG_AC,
1599 STM32_FUNCTION(0, "GPIOH7"), 1715 STM32_FUNCTION(0, "GPIOH7"),
1600 STM32_FUNCTION(5, "I2C3_SCL"), 1716 STM32_FUNCTION(5, "I2C3_SCL"),
1601 STM32_FUNCTION(6, "SPI5_MISO"), 1717 STM32_FUNCTION(6, "SPI5_MISO"),
1602 STM32_FUNCTION(12, "ETH_GMII_RXD3 ETH_MII_RXD3 ETH_RGMII_RXD3"), 1718 STM32_FUNCTION(12, "ETH1_GMII_RXD3 ETH1_MII_RXD3 ETH1_RGMII_RXD3"),
1603 STM32_FUNCTION(13, "MDIOS_MDC"), 1719 STM32_FUNCTION(13, "MDIOS_MDC"),
1604 STM32_FUNCTION(14, "DCMI_D9"), 1720 STM32_FUNCTION(14, "DCMI_D9"),
1605 STM32_FUNCTION(16, "EVENTOUT"), 1721 STM32_FUNCTION(16, "EVENTOUT"),
1606 STM32_FUNCTION(17, "ANALOG") 1722 STM32_FUNCTION(17, "ANALOG")
1607 ), 1723 ),
1608 STM32_PIN( 1724 STM32_PIN_PKG(
1609 PINCTRL_PIN(120, "PH8"), 1725 PINCTRL_PIN(120, "PH8"),
1726 STM32MP_PKG_AA | STM32MP_PKG_AC,
1610 STM32_FUNCTION(0, "GPIOH8"), 1727 STM32_FUNCTION(0, "GPIOH8"),
1611 STM32_FUNCTION(3, "TIM5_ETR"), 1728 STM32_FUNCTION(3, "TIM5_ETR"),
1612 STM32_FUNCTION(5, "I2C3_SDA"), 1729 STM32_FUNCTION(5, "I2C3_SDA"),
@@ -1615,8 +1732,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1615 STM32_FUNCTION(16, "EVENTOUT"), 1732 STM32_FUNCTION(16, "EVENTOUT"),
1616 STM32_FUNCTION(17, "ANALOG") 1733 STM32_FUNCTION(17, "ANALOG")
1617 ), 1734 ),
1618 STM32_PIN( 1735 STM32_PIN_PKG(
1619 PINCTRL_PIN(121, "PH9"), 1736 PINCTRL_PIN(121, "PH9"),
1737 STM32MP_PKG_AA | STM32MP_PKG_AC,
1620 STM32_FUNCTION(0, "GPIOH9"), 1738 STM32_FUNCTION(0, "GPIOH9"),
1621 STM32_FUNCTION(3, "TIM12_CH2"), 1739 STM32_FUNCTION(3, "TIM12_CH2"),
1622 STM32_FUNCTION(5, "I2C3_SMBA"), 1740 STM32_FUNCTION(5, "I2C3_SMBA"),
@@ -1625,8 +1743,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1625 STM32_FUNCTION(16, "EVENTOUT"), 1743 STM32_FUNCTION(16, "EVENTOUT"),
1626 STM32_FUNCTION(17, "ANALOG") 1744 STM32_FUNCTION(17, "ANALOG")
1627 ), 1745 ),
1628 STM32_PIN( 1746 STM32_PIN_PKG(
1629 PINCTRL_PIN(122, "PH10"), 1747 PINCTRL_PIN(122, "PH10"),
1748 STM32MP_PKG_AA | STM32MP_PKG_AC,
1630 STM32_FUNCTION(0, "GPIOH10"), 1749 STM32_FUNCTION(0, "GPIOH10"),
1631 STM32_FUNCTION(3, "TIM5_CH1"), 1750 STM32_FUNCTION(3, "TIM5_CH1"),
1632 STM32_FUNCTION(5, "I2C4_SMBA"), 1751 STM32_FUNCTION(5, "I2C4_SMBA"),
@@ -1636,8 +1755,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1636 STM32_FUNCTION(16, "EVENTOUT"), 1755 STM32_FUNCTION(16, "EVENTOUT"),
1637 STM32_FUNCTION(17, "ANALOG") 1756 STM32_FUNCTION(17, "ANALOG")
1638 ), 1757 ),
1639 STM32_PIN( 1758 STM32_PIN_PKG(
1640 PINCTRL_PIN(123, "PH11"), 1759 PINCTRL_PIN(123, "PH11"),
1760 STM32MP_PKG_AA | STM32MP_PKG_AC,
1641 STM32_FUNCTION(0, "GPIOH11"), 1761 STM32_FUNCTION(0, "GPIOH11"),
1642 STM32_FUNCTION(3, "TIM5_CH2"), 1762 STM32_FUNCTION(3, "TIM5_CH2"),
1643 STM32_FUNCTION(5, "I2C4_SCL"), 1763 STM32_FUNCTION(5, "I2C4_SCL"),
@@ -1647,8 +1767,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1647 STM32_FUNCTION(16, "EVENTOUT"), 1767 STM32_FUNCTION(16, "EVENTOUT"),
1648 STM32_FUNCTION(17, "ANALOG") 1768 STM32_FUNCTION(17, "ANALOG")
1649 ), 1769 ),
1650 STM32_PIN( 1770 STM32_PIN_PKG(
1651 PINCTRL_PIN(124, "PH12"), 1771 PINCTRL_PIN(124, "PH12"),
1772 STM32MP_PKG_AA | STM32MP_PKG_AC,
1652 STM32_FUNCTION(0, "GPIOH12"), 1773 STM32_FUNCTION(0, "GPIOH12"),
1653 STM32_FUNCTION(1, "HDP2"), 1774 STM32_FUNCTION(1, "HDP2"),
1654 STM32_FUNCTION(3, "TIM5_CH3"), 1775 STM32_FUNCTION(3, "TIM5_CH3"),
@@ -1659,50 +1780,53 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1659 STM32_FUNCTION(16, "EVENTOUT"), 1780 STM32_FUNCTION(16, "EVENTOUT"),
1660 STM32_FUNCTION(17, "ANALOG") 1781 STM32_FUNCTION(17, "ANALOG")
1661 ), 1782 ),
1662 STM32_PIN( 1783 STM32_PIN_PKG(
1663 PINCTRL_PIN(125, "PH13"), 1784 PINCTRL_PIN(125, "PH13"),
1785 STM32MP_PKG_AA | STM32MP_PKG_AC,
1664 STM32_FUNCTION(0, "GPIOH13"), 1786 STM32_FUNCTION(0, "GPIOH13"),
1665 STM32_FUNCTION(4, "TIM8_CH1N"), 1787 STM32_FUNCTION(4, "TIM8_CH1N"),
1666 STM32_FUNCTION(9, "UART4_TX"), 1788 STM32_FUNCTION(9, "UART4_TX"),
1667 STM32_FUNCTION(10, "CAN1_TX"), 1789 STM32_FUNCTION(10, "FDCAN1_TX"),
1668 STM32_FUNCTION(15, "LCD_G2"), 1790 STM32_FUNCTION(15, "LCD_G2"),
1669 STM32_FUNCTION(16, "EVENTOUT"), 1791 STM32_FUNCTION(16, "EVENTOUT"),
1670 STM32_FUNCTION(17, "ANALOG") 1792 STM32_FUNCTION(17, "ANALOG")
1671 ), 1793 ),
1672 STM32_PIN( 1794 STM32_PIN_PKG(
1673 PINCTRL_PIN(126, "PH14"), 1795 PINCTRL_PIN(126, "PH14"),
1796 STM32MP_PKG_AA | STM32MP_PKG_AC,
1674 STM32_FUNCTION(0, "GPIOH14"), 1797 STM32_FUNCTION(0, "GPIOH14"),
1675 STM32_FUNCTION(4, "TIM8_CH2N"), 1798 STM32_FUNCTION(4, "TIM8_CH2N"),
1676 STM32_FUNCTION(9, "UART4_RX"), 1799 STM32_FUNCTION(9, "UART4_RX"),
1677 STM32_FUNCTION(10, "CAN1_RX"), 1800 STM32_FUNCTION(10, "FDCAN1_RX"),
1678 STM32_FUNCTION(14, "DCMI_D4"), 1801 STM32_FUNCTION(14, "DCMI_D4"),
1679 STM32_FUNCTION(15, "LCD_G3"), 1802 STM32_FUNCTION(15, "LCD_G3"),
1680 STM32_FUNCTION(16, "EVENTOUT"), 1803 STM32_FUNCTION(16, "EVENTOUT"),
1681 STM32_FUNCTION(17, "ANALOG") 1804 STM32_FUNCTION(17, "ANALOG")
1682 ), 1805 ),
1683 STM32_PIN( 1806 STM32_PIN_PKG(
1684 PINCTRL_PIN(127, "PH15"), 1807 PINCTRL_PIN(127, "PH15"),
1808 STM32MP_PKG_AA | STM32MP_PKG_AC,
1685 STM32_FUNCTION(0, "GPIOH15"), 1809 STM32_FUNCTION(0, "GPIOH15"),
1686 STM32_FUNCTION(4, "TIM8_CH3N"), 1810 STM32_FUNCTION(4, "TIM8_CH3N"),
1687 STM32_FUNCTION(10, "CAN1_TXFD"),
1688 STM32_FUNCTION(14, "DCMI_D11"), 1811 STM32_FUNCTION(14, "DCMI_D11"),
1689 STM32_FUNCTION(15, "LCD_G4"), 1812 STM32_FUNCTION(15, "LCD_G4"),
1690 STM32_FUNCTION(16, "EVENTOUT"), 1813 STM32_FUNCTION(16, "EVENTOUT"),
1691 STM32_FUNCTION(17, "ANALOG") 1814 STM32_FUNCTION(17, "ANALOG")
1692 ), 1815 ),
1693 STM32_PIN( 1816 STM32_PIN_PKG(
1694 PINCTRL_PIN(128, "PI0"), 1817 PINCTRL_PIN(128, "PI0"),
1818 STM32MP_PKG_AA | STM32MP_PKG_AC,
1695 STM32_FUNCTION(0, "GPIOI0"), 1819 STM32_FUNCTION(0, "GPIOI0"),
1696 STM32_FUNCTION(3, "TIM5_CH4"), 1820 STM32_FUNCTION(3, "TIM5_CH4"),
1697 STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"), 1821 STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
1698 STM32_FUNCTION(10, "CAN1_RXFD"),
1699 STM32_FUNCTION(14, "DCMI_D13"), 1822 STM32_FUNCTION(14, "DCMI_D13"),
1700 STM32_FUNCTION(15, "LCD_G5"), 1823 STM32_FUNCTION(15, "LCD_G5"),
1701 STM32_FUNCTION(16, "EVENTOUT"), 1824 STM32_FUNCTION(16, "EVENTOUT"),
1702 STM32_FUNCTION(17, "ANALOG") 1825 STM32_FUNCTION(17, "ANALOG")
1703 ), 1826 ),
1704 STM32_PIN( 1827 STM32_PIN_PKG(
1705 PINCTRL_PIN(129, "PI1"), 1828 PINCTRL_PIN(129, "PI1"),
1829 STM32MP_PKG_AA | STM32MP_PKG_AC,
1706 STM32_FUNCTION(0, "GPIOI1"), 1830 STM32_FUNCTION(0, "GPIOI1"),
1707 STM32_FUNCTION(4, "TIM8_BKIN2"), 1831 STM32_FUNCTION(4, "TIM8_BKIN2"),
1708 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"), 1832 STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
@@ -1711,8 +1835,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1711 STM32_FUNCTION(16, "EVENTOUT"), 1835 STM32_FUNCTION(16, "EVENTOUT"),
1712 STM32_FUNCTION(17, "ANALOG") 1836 STM32_FUNCTION(17, "ANALOG")
1713 ), 1837 ),
1714 STM32_PIN( 1838 STM32_PIN_PKG(
1715 PINCTRL_PIN(130, "PI2"), 1839 PINCTRL_PIN(130, "PI2"),
1840 STM32MP_PKG_AA | STM32MP_PKG_AC,
1716 STM32_FUNCTION(0, "GPIOI2"), 1841 STM32_FUNCTION(0, "GPIOI2"),
1717 STM32_FUNCTION(4, "TIM8_CH4"), 1842 STM32_FUNCTION(4, "TIM8_CH4"),
1718 STM32_FUNCTION(6, "SPI2_MISO I2S2_SDI"), 1843 STM32_FUNCTION(6, "SPI2_MISO I2S2_SDI"),
@@ -1721,8 +1846,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1721 STM32_FUNCTION(16, "EVENTOUT"), 1846 STM32_FUNCTION(16, "EVENTOUT"),
1722 STM32_FUNCTION(17, "ANALOG") 1847 STM32_FUNCTION(17, "ANALOG")
1723 ), 1848 ),
1724 STM32_PIN( 1849 STM32_PIN_PKG(
1725 PINCTRL_PIN(131, "PI3"), 1850 PINCTRL_PIN(131, "PI3"),
1851 STM32MP_PKG_AA | STM32MP_PKG_AC,
1726 STM32_FUNCTION(0, "GPIOI3"), 1852 STM32_FUNCTION(0, "GPIOI3"),
1727 STM32_FUNCTION(4, "TIM8_ETR"), 1853 STM32_FUNCTION(4, "TIM8_ETR"),
1728 STM32_FUNCTION(6, "SPI2_MOSI I2S2_SDO"), 1854 STM32_FUNCTION(6, "SPI2_MOSI I2S2_SDO"),
@@ -1730,8 +1856,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1730 STM32_FUNCTION(16, "EVENTOUT"), 1856 STM32_FUNCTION(16, "EVENTOUT"),
1731 STM32_FUNCTION(17, "ANALOG") 1857 STM32_FUNCTION(17, "ANALOG")
1732 ), 1858 ),
1733 STM32_PIN( 1859 STM32_PIN_PKG(
1734 PINCTRL_PIN(132, "PI4"), 1860 PINCTRL_PIN(132, "PI4"),
1861 STM32MP_PKG_AA | STM32MP_PKG_AC,
1735 STM32_FUNCTION(0, "GPIOI4"), 1862 STM32_FUNCTION(0, "GPIOI4"),
1736 STM32_FUNCTION(4, "TIM8_BKIN"), 1863 STM32_FUNCTION(4, "TIM8_BKIN"),
1737 STM32_FUNCTION(11, "SAI2_MCLK_A"), 1864 STM32_FUNCTION(11, "SAI2_MCLK_A"),
@@ -1740,8 +1867,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1740 STM32_FUNCTION(16, "EVENTOUT"), 1867 STM32_FUNCTION(16, "EVENTOUT"),
1741 STM32_FUNCTION(17, "ANALOG") 1868 STM32_FUNCTION(17, "ANALOG")
1742 ), 1869 ),
1743 STM32_PIN( 1870 STM32_PIN_PKG(
1744 PINCTRL_PIN(133, "PI5"), 1871 PINCTRL_PIN(133, "PI5"),
1872 STM32MP_PKG_AA | STM32MP_PKG_AC,
1745 STM32_FUNCTION(0, "GPIOI5"), 1873 STM32_FUNCTION(0, "GPIOI5"),
1746 STM32_FUNCTION(4, "TIM8_CH1"), 1874 STM32_FUNCTION(4, "TIM8_CH1"),
1747 STM32_FUNCTION(11, "SAI2_SCK_A"), 1875 STM32_FUNCTION(11, "SAI2_SCK_A"),
@@ -1750,8 +1878,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1750 STM32_FUNCTION(16, "EVENTOUT"), 1878 STM32_FUNCTION(16, "EVENTOUT"),
1751 STM32_FUNCTION(17, "ANALOG") 1879 STM32_FUNCTION(17, "ANALOG")
1752 ), 1880 ),
1753 STM32_PIN( 1881 STM32_PIN_PKG(
1754 PINCTRL_PIN(134, "PI6"), 1882 PINCTRL_PIN(134, "PI6"),
1883 STM32MP_PKG_AA | STM32MP_PKG_AC,
1755 STM32_FUNCTION(0, "GPIOI6"), 1884 STM32_FUNCTION(0, "GPIOI6"),
1756 STM32_FUNCTION(4, "TIM8_CH2"), 1885 STM32_FUNCTION(4, "TIM8_CH2"),
1757 STM32_FUNCTION(11, "SAI2_SD_A"), 1886 STM32_FUNCTION(11, "SAI2_SD_A"),
@@ -1760,8 +1889,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1760 STM32_FUNCTION(16, "EVENTOUT"), 1889 STM32_FUNCTION(16, "EVENTOUT"),
1761 STM32_FUNCTION(17, "ANALOG") 1890 STM32_FUNCTION(17, "ANALOG")
1762 ), 1891 ),
1763 STM32_PIN( 1892 STM32_PIN_PKG(
1764 PINCTRL_PIN(135, "PI7"), 1893 PINCTRL_PIN(135, "PI7"),
1894 STM32MP_PKG_AA | STM32MP_PKG_AC,
1765 STM32_FUNCTION(0, "GPIOI7"), 1895 STM32_FUNCTION(0, "GPIOI7"),
1766 STM32_FUNCTION(4, "TIM8_CH3"), 1896 STM32_FUNCTION(4, "TIM8_CH3"),
1767 STM32_FUNCTION(11, "SAI2_FS_A"), 1897 STM32_FUNCTION(11, "SAI2_FS_A"),
@@ -1770,35 +1900,38 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1770 STM32_FUNCTION(16, "EVENTOUT"), 1900 STM32_FUNCTION(16, "EVENTOUT"),
1771 STM32_FUNCTION(17, "ANALOG") 1901 STM32_FUNCTION(17, "ANALOG")
1772 ), 1902 ),
1773 STM32_PIN( 1903 STM32_PIN_PKG(
1774 PINCTRL_PIN(136, "PI8"), 1904 PINCTRL_PIN(136, "PI8"),
1905 STM32MP_PKG_AA | STM32MP_PKG_AC,
1775 STM32_FUNCTION(0, "GPIOI8"), 1906 STM32_FUNCTION(0, "GPIOI8"),
1776 STM32_FUNCTION(16, "EVENTOUT"), 1907 STM32_FUNCTION(16, "EVENTOUT"),
1777 STM32_FUNCTION(17, "ANALOG") 1908 STM32_FUNCTION(17, "ANALOG")
1778 ), 1909 ),
1779 STM32_PIN( 1910 STM32_PIN_PKG(
1780 PINCTRL_PIN(137, "PI9"), 1911 PINCTRL_PIN(137, "PI9"),
1912 STM32MP_PKG_AA | STM32MP_PKG_AC,
1781 STM32_FUNCTION(0, "GPIOI9"), 1913 STM32_FUNCTION(0, "GPIOI9"),
1782 STM32_FUNCTION(1, "HDP1"), 1914 STM32_FUNCTION(1, "HDP1"),
1783 STM32_FUNCTION(9, "UART4_RX"), 1915 STM32_FUNCTION(9, "UART4_RX"),
1784 STM32_FUNCTION(10, "CAN1_RX"), 1916 STM32_FUNCTION(10, "FDCAN1_RX"),
1785 STM32_FUNCTION(15, "LCD_VSYNC"), 1917 STM32_FUNCTION(15, "LCD_VSYNC"),
1786 STM32_FUNCTION(16, "EVENTOUT"), 1918 STM32_FUNCTION(16, "EVENTOUT"),
1787 STM32_FUNCTION(17, "ANALOG") 1919 STM32_FUNCTION(17, "ANALOG")
1788 ), 1920 ),
1789 STM32_PIN( 1921 STM32_PIN_PKG(
1790 PINCTRL_PIN(138, "PI10"), 1922 PINCTRL_PIN(138, "PI10"),
1923 STM32MP_PKG_AA | STM32MP_PKG_AC,
1791 STM32_FUNCTION(0, "GPIOI10"), 1924 STM32_FUNCTION(0, "GPIOI10"),
1792 STM32_FUNCTION(1, "HDP0"), 1925 STM32_FUNCTION(1, "HDP0"),
1793 STM32_FUNCTION(9, "USART3_CTS_NSS USART_BOOT3_CTS_NSS"), 1926 STM32_FUNCTION(9, "USART3_CTS USART3_NSS"),
1794 STM32_FUNCTION(10, "CAN1_RXFD"), 1927 STM32_FUNCTION(12, "ETH1_GMII_RX_ER ETH1_MII_RX_ER"),
1795 STM32_FUNCTION(12, "ETH_GMII_RX_ER ETH_MII_RX_ER"),
1796 STM32_FUNCTION(15, "LCD_HSYNC"), 1928 STM32_FUNCTION(15, "LCD_HSYNC"),
1797 STM32_FUNCTION(16, "EVENTOUT"), 1929 STM32_FUNCTION(16, "EVENTOUT"),
1798 STM32_FUNCTION(17, "ANALOG") 1930 STM32_FUNCTION(17, "ANALOG")
1799 ), 1931 ),
1800 STM32_PIN( 1932 STM32_PIN_PKG(
1801 PINCTRL_PIN(139, "PI11"), 1933 PINCTRL_PIN(139, "PI11"),
1934 STM32MP_PKG_AA | STM32MP_PKG_AC,
1802 STM32_FUNCTION(0, "GPIOI11"), 1935 STM32_FUNCTION(0, "GPIOI11"),
1803 STM32_FUNCTION(1, "MCO1"), 1936 STM32_FUNCTION(1, "MCO1"),
1804 STM32_FUNCTION(6, "I2S_CKIN"), 1937 STM32_FUNCTION(6, "I2S_CKIN"),
@@ -1806,8 +1939,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1806 STM32_FUNCTION(16, "EVENTOUT"), 1939 STM32_FUNCTION(16, "EVENTOUT"),
1807 STM32_FUNCTION(17, "ANALOG") 1940 STM32_FUNCTION(17, "ANALOG")
1808 ), 1941 ),
1809 STM32_PIN( 1942 STM32_PIN_PKG(
1810 PINCTRL_PIN(140, "PI12"), 1943 PINCTRL_PIN(140, "PI12"),
1944 STM32MP_PKG_AA,
1811 STM32_FUNCTION(0, "GPIOI12"), 1945 STM32_FUNCTION(0, "GPIOI12"),
1812 STM32_FUNCTION(1, "TRACED0"), 1946 STM32_FUNCTION(1, "TRACED0"),
1813 STM32_FUNCTION(3, "HDP0"), 1947 STM32_FUNCTION(3, "HDP0"),
@@ -1815,8 +1949,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1815 STM32_FUNCTION(16, "EVENTOUT"), 1949 STM32_FUNCTION(16, "EVENTOUT"),
1816 STM32_FUNCTION(17, "ANALOG") 1950 STM32_FUNCTION(17, "ANALOG")
1817 ), 1951 ),
1818 STM32_PIN( 1952 STM32_PIN_PKG(
1819 PINCTRL_PIN(141, "PI13"), 1953 PINCTRL_PIN(141, "PI13"),
1954 STM32MP_PKG_AA,
1820 STM32_FUNCTION(0, "GPIOI13"), 1955 STM32_FUNCTION(0, "GPIOI13"),
1821 STM32_FUNCTION(1, "TRACED1"), 1956 STM32_FUNCTION(1, "TRACED1"),
1822 STM32_FUNCTION(3, "HDP1"), 1957 STM32_FUNCTION(3, "HDP1"),
@@ -1824,24 +1959,27 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1824 STM32_FUNCTION(16, "EVENTOUT"), 1959 STM32_FUNCTION(16, "EVENTOUT"),
1825 STM32_FUNCTION(17, "ANALOG") 1960 STM32_FUNCTION(17, "ANALOG")
1826 ), 1961 ),
1827 STM32_PIN( 1962 STM32_PIN_PKG(
1828 PINCTRL_PIN(142, "PI14"), 1963 PINCTRL_PIN(142, "PI14"),
1964 STM32MP_PKG_AA,
1829 STM32_FUNCTION(0, "GPIOI14"), 1965 STM32_FUNCTION(0, "GPIOI14"),
1830 STM32_FUNCTION(1, "TRACECLK"), 1966 STM32_FUNCTION(1, "TRACECLK"),
1831 STM32_FUNCTION(15, "LCD_CLK"), 1967 STM32_FUNCTION(15, "LCD_CLK"),
1832 STM32_FUNCTION(16, "EVENTOUT"), 1968 STM32_FUNCTION(16, "EVENTOUT"),
1833 STM32_FUNCTION(17, "ANALOG") 1969 STM32_FUNCTION(17, "ANALOG")
1834 ), 1970 ),
1835 STM32_PIN( 1971 STM32_PIN_PKG(
1836 PINCTRL_PIN(143, "PI15"), 1972 PINCTRL_PIN(143, "PI15"),
1973 STM32MP_PKG_AA,
1837 STM32_FUNCTION(0, "GPIOI15"), 1974 STM32_FUNCTION(0, "GPIOI15"),
1838 STM32_FUNCTION(10, "LCD_G2"), 1975 STM32_FUNCTION(10, "LCD_G2"),
1839 STM32_FUNCTION(15, "LCD_R0"), 1976 STM32_FUNCTION(15, "LCD_R0"),
1840 STM32_FUNCTION(16, "EVENTOUT"), 1977 STM32_FUNCTION(16, "EVENTOUT"),
1841 STM32_FUNCTION(17, "ANALOG") 1978 STM32_FUNCTION(17, "ANALOG")
1842 ), 1979 ),
1843 STM32_PIN( 1980 STM32_PIN_PKG(
1844 PINCTRL_PIN(144, "PJ0"), 1981 PINCTRL_PIN(144, "PJ0"),
1982 STM32MP_PKG_AA,
1845 STM32_FUNCTION(0, "GPIOJ0"), 1983 STM32_FUNCTION(0, "GPIOJ0"),
1846 STM32_FUNCTION(1, "TRACED8"), 1984 STM32_FUNCTION(1, "TRACED8"),
1847 STM32_FUNCTION(10, "LCD_R7"), 1985 STM32_FUNCTION(10, "LCD_R7"),
@@ -1849,16 +1987,18 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1849 STM32_FUNCTION(16, "EVENTOUT"), 1987 STM32_FUNCTION(16, "EVENTOUT"),
1850 STM32_FUNCTION(17, "ANALOG") 1988 STM32_FUNCTION(17, "ANALOG")
1851 ), 1989 ),
1852 STM32_PIN( 1990 STM32_PIN_PKG(
1853 PINCTRL_PIN(145, "PJ1"), 1991 PINCTRL_PIN(145, "PJ1"),
1992 STM32MP_PKG_AA,
1854 STM32_FUNCTION(0, "GPIOJ1"), 1993 STM32_FUNCTION(0, "GPIOJ1"),
1855 STM32_FUNCTION(1, "TRACED9"), 1994 STM32_FUNCTION(1, "TRACED9"),
1856 STM32_FUNCTION(15, "LCD_R2"), 1995 STM32_FUNCTION(15, "LCD_R2"),
1857 STM32_FUNCTION(16, "EVENTOUT"), 1996 STM32_FUNCTION(16, "EVENTOUT"),
1858 STM32_FUNCTION(17, "ANALOG") 1997 STM32_FUNCTION(17, "ANALOG")
1859 ), 1998 ),
1860 STM32_PIN( 1999 STM32_PIN_PKG(
1861 PINCTRL_PIN(146, "PJ2"), 2000 PINCTRL_PIN(146, "PJ2"),
2001 STM32MP_PKG_AA,
1862 STM32_FUNCTION(0, "GPIOJ2"), 2002 STM32_FUNCTION(0, "GPIOJ2"),
1863 STM32_FUNCTION(1, "TRACED10"), 2003 STM32_FUNCTION(1, "TRACED10"),
1864 STM32_FUNCTION(14, "DSI_TE"), 2004 STM32_FUNCTION(14, "DSI_TE"),
@@ -1866,24 +2006,27 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1866 STM32_FUNCTION(16, "EVENTOUT"), 2006 STM32_FUNCTION(16, "EVENTOUT"),
1867 STM32_FUNCTION(17, "ANALOG") 2007 STM32_FUNCTION(17, "ANALOG")
1868 ), 2008 ),
1869 STM32_PIN( 2009 STM32_PIN_PKG(
1870 PINCTRL_PIN(147, "PJ3"), 2010 PINCTRL_PIN(147, "PJ3"),
2011 STM32MP_PKG_AA,
1871 STM32_FUNCTION(0, "GPIOJ3"), 2012 STM32_FUNCTION(0, "GPIOJ3"),
1872 STM32_FUNCTION(1, "TRACED11"), 2013 STM32_FUNCTION(1, "TRACED11"),
1873 STM32_FUNCTION(15, "LCD_R4"), 2014 STM32_FUNCTION(15, "LCD_R4"),
1874 STM32_FUNCTION(16, "EVENTOUT"), 2015 STM32_FUNCTION(16, "EVENTOUT"),
1875 STM32_FUNCTION(17, "ANALOG") 2016 STM32_FUNCTION(17, "ANALOG")
1876 ), 2017 ),
1877 STM32_PIN( 2018 STM32_PIN_PKG(
1878 PINCTRL_PIN(148, "PJ4"), 2019 PINCTRL_PIN(148, "PJ4"),
2020 STM32MP_PKG_AA,
1879 STM32_FUNCTION(0, "GPIOJ4"), 2021 STM32_FUNCTION(0, "GPIOJ4"),
1880 STM32_FUNCTION(1, "TRACED12"), 2022 STM32_FUNCTION(1, "TRACED12"),
1881 STM32_FUNCTION(15, "LCD_R5"), 2023 STM32_FUNCTION(15, "LCD_R5"),
1882 STM32_FUNCTION(16, "EVENTOUT"), 2024 STM32_FUNCTION(16, "EVENTOUT"),
1883 STM32_FUNCTION(17, "ANALOG") 2025 STM32_FUNCTION(17, "ANALOG")
1884 ), 2026 ),
1885 STM32_PIN( 2027 STM32_PIN_PKG(
1886 PINCTRL_PIN(149, "PJ5"), 2028 PINCTRL_PIN(149, "PJ5"),
2029 STM32MP_PKG_AA,
1887 STM32_FUNCTION(0, "GPIOJ5"), 2030 STM32_FUNCTION(0, "GPIOJ5"),
1888 STM32_FUNCTION(1, "TRACED2"), 2031 STM32_FUNCTION(1, "TRACED2"),
1889 STM32_FUNCTION(3, "HDP2"), 2032 STM32_FUNCTION(3, "HDP2"),
@@ -1891,8 +2034,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1891 STM32_FUNCTION(16, "EVENTOUT"), 2034 STM32_FUNCTION(16, "EVENTOUT"),
1892 STM32_FUNCTION(17, "ANALOG") 2035 STM32_FUNCTION(17, "ANALOG")
1893 ), 2036 ),
1894 STM32_PIN( 2037 STM32_PIN_PKG(
1895 PINCTRL_PIN(150, "PJ6"), 2038 PINCTRL_PIN(150, "PJ6"),
2039 STM32MP_PKG_AA,
1896 STM32_FUNCTION(0, "GPIOJ6"), 2040 STM32_FUNCTION(0, "GPIOJ6"),
1897 STM32_FUNCTION(1, "TRACED3"), 2041 STM32_FUNCTION(1, "TRACED3"),
1898 STM32_FUNCTION(3, "HDP3"), 2042 STM32_FUNCTION(3, "HDP3"),
@@ -1901,8 +2045,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1901 STM32_FUNCTION(16, "EVENTOUT"), 2045 STM32_FUNCTION(16, "EVENTOUT"),
1902 STM32_FUNCTION(17, "ANALOG") 2046 STM32_FUNCTION(17, "ANALOG")
1903 ), 2047 ),
1904 STM32_PIN( 2048 STM32_PIN_PKG(
1905 PINCTRL_PIN(151, "PJ7"), 2049 PINCTRL_PIN(151, "PJ7"),
2050 STM32MP_PKG_AA,
1906 STM32_FUNCTION(0, "GPIOJ7"), 2051 STM32_FUNCTION(0, "GPIOJ7"),
1907 STM32_FUNCTION(1, "TRACED13"), 2052 STM32_FUNCTION(1, "TRACED13"),
1908 STM32_FUNCTION(4, "TIM8_CH2N"), 2053 STM32_FUNCTION(4, "TIM8_CH2N"),
@@ -1910,8 +2055,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1910 STM32_FUNCTION(16, "EVENTOUT"), 2055 STM32_FUNCTION(16, "EVENTOUT"),
1911 STM32_FUNCTION(17, "ANALOG") 2056 STM32_FUNCTION(17, "ANALOG")
1912 ), 2057 ),
1913 STM32_PIN( 2058 STM32_PIN_PKG(
1914 PINCTRL_PIN(152, "PJ8"), 2059 PINCTRL_PIN(152, "PJ8"),
2060 STM32MP_PKG_AA,
1915 STM32_FUNCTION(0, "GPIOJ8"), 2061 STM32_FUNCTION(0, "GPIOJ8"),
1916 STM32_FUNCTION(1, "TRACED14"), 2062 STM32_FUNCTION(1, "TRACED14"),
1917 STM32_FUNCTION(2, "TIM1_CH3N"), 2063 STM32_FUNCTION(2, "TIM1_CH3N"),
@@ -1921,8 +2067,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1921 STM32_FUNCTION(16, "EVENTOUT"), 2067 STM32_FUNCTION(16, "EVENTOUT"),
1922 STM32_FUNCTION(17, "ANALOG") 2068 STM32_FUNCTION(17, "ANALOG")
1923 ), 2069 ),
1924 STM32_PIN( 2070 STM32_PIN_PKG(
1925 PINCTRL_PIN(153, "PJ9"), 2071 PINCTRL_PIN(153, "PJ9"),
2072 STM32MP_PKG_AA,
1926 STM32_FUNCTION(0, "GPIOJ9"), 2073 STM32_FUNCTION(0, "GPIOJ9"),
1927 STM32_FUNCTION(1, "TRACED15"), 2074 STM32_FUNCTION(1, "TRACED15"),
1928 STM32_FUNCTION(2, "TIM1_CH3"), 2075 STM32_FUNCTION(2, "TIM1_CH3"),
@@ -1932,8 +2079,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1932 STM32_FUNCTION(16, "EVENTOUT"), 2079 STM32_FUNCTION(16, "EVENTOUT"),
1933 STM32_FUNCTION(17, "ANALOG") 2080 STM32_FUNCTION(17, "ANALOG")
1934 ), 2081 ),
1935 STM32_PIN( 2082 STM32_PIN_PKG(
1936 PINCTRL_PIN(154, "PJ10"), 2083 PINCTRL_PIN(154, "PJ10"),
2084 STM32MP_PKG_AA,
1937 STM32_FUNCTION(0, "GPIOJ10"), 2085 STM32_FUNCTION(0, "GPIOJ10"),
1938 STM32_FUNCTION(2, "TIM1_CH2N"), 2086 STM32_FUNCTION(2, "TIM1_CH2N"),
1939 STM32_FUNCTION(4, "TIM8_CH2"), 2087 STM32_FUNCTION(4, "TIM8_CH2"),
@@ -1942,8 +2090,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1942 STM32_FUNCTION(16, "EVENTOUT"), 2090 STM32_FUNCTION(16, "EVENTOUT"),
1943 STM32_FUNCTION(17, "ANALOG") 2091 STM32_FUNCTION(17, "ANALOG")
1944 ), 2092 ),
1945 STM32_PIN( 2093 STM32_PIN_PKG(
1946 PINCTRL_PIN(155, "PJ11"), 2094 PINCTRL_PIN(155, "PJ11"),
2095 STM32MP_PKG_AA,
1947 STM32_FUNCTION(0, "GPIOJ11"), 2096 STM32_FUNCTION(0, "GPIOJ11"),
1948 STM32_FUNCTION(2, "TIM1_CH2"), 2097 STM32_FUNCTION(2, "TIM1_CH2"),
1949 STM32_FUNCTION(4, "TIM8_CH2N"), 2098 STM32_FUNCTION(4, "TIM8_CH2N"),
@@ -1952,38 +2101,43 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1952 STM32_FUNCTION(16, "EVENTOUT"), 2101 STM32_FUNCTION(16, "EVENTOUT"),
1953 STM32_FUNCTION(17, "ANALOG") 2102 STM32_FUNCTION(17, "ANALOG")
1954 ), 2103 ),
1955 STM32_PIN( 2104 STM32_PIN_PKG(
1956 PINCTRL_PIN(156, "PJ12"), 2105 PINCTRL_PIN(156, "PJ12"),
2106 STM32MP_PKG_AA,
1957 STM32_FUNCTION(0, "GPIOJ12"), 2107 STM32_FUNCTION(0, "GPIOJ12"),
1958 STM32_FUNCTION(10, "LCD_G3"), 2108 STM32_FUNCTION(10, "LCD_G3"),
1959 STM32_FUNCTION(15, "LCD_B0"), 2109 STM32_FUNCTION(15, "LCD_B0"),
1960 STM32_FUNCTION(16, "EVENTOUT"), 2110 STM32_FUNCTION(16, "EVENTOUT"),
1961 STM32_FUNCTION(17, "ANALOG") 2111 STM32_FUNCTION(17, "ANALOG")
1962 ), 2112 ),
1963 STM32_PIN( 2113 STM32_PIN_PKG(
1964 PINCTRL_PIN(157, "PJ13"), 2114 PINCTRL_PIN(157, "PJ13"),
2115 STM32MP_PKG_AA,
1965 STM32_FUNCTION(0, "GPIOJ13"), 2116 STM32_FUNCTION(0, "GPIOJ13"),
1966 STM32_FUNCTION(10, "LCD_G4"), 2117 STM32_FUNCTION(10, "LCD_G4"),
1967 STM32_FUNCTION(15, "LCD_B1"), 2118 STM32_FUNCTION(15, "LCD_B1"),
1968 STM32_FUNCTION(16, "EVENTOUT"), 2119 STM32_FUNCTION(16, "EVENTOUT"),
1969 STM32_FUNCTION(17, "ANALOG") 2120 STM32_FUNCTION(17, "ANALOG")
1970 ), 2121 ),
1971 STM32_PIN( 2122 STM32_PIN_PKG(
1972 PINCTRL_PIN(158, "PJ14"), 2123 PINCTRL_PIN(158, "PJ14"),
2124 STM32MP_PKG_AA,
1973 STM32_FUNCTION(0, "GPIOJ14"), 2125 STM32_FUNCTION(0, "GPIOJ14"),
1974 STM32_FUNCTION(15, "LCD_B2"), 2126 STM32_FUNCTION(15, "LCD_B2"),
1975 STM32_FUNCTION(16, "EVENTOUT"), 2127 STM32_FUNCTION(16, "EVENTOUT"),
1976 STM32_FUNCTION(17, "ANALOG") 2128 STM32_FUNCTION(17, "ANALOG")
1977 ), 2129 ),
1978 STM32_PIN( 2130 STM32_PIN_PKG(
1979 PINCTRL_PIN(159, "PJ15"), 2131 PINCTRL_PIN(159, "PJ15"),
2132 STM32MP_PKG_AA,
1980 STM32_FUNCTION(0, "GPIOJ15"), 2133 STM32_FUNCTION(0, "GPIOJ15"),
1981 STM32_FUNCTION(15, "LCD_B3"), 2134 STM32_FUNCTION(15, "LCD_B3"),
1982 STM32_FUNCTION(16, "EVENTOUT"), 2135 STM32_FUNCTION(16, "EVENTOUT"),
1983 STM32_FUNCTION(17, "ANALOG") 2136 STM32_FUNCTION(17, "ANALOG")
1984 ), 2137 ),
1985 STM32_PIN( 2138 STM32_PIN_PKG(
1986 PINCTRL_PIN(160, "PK0"), 2139 PINCTRL_PIN(160, "PK0"),
2140 STM32MP_PKG_AA,
1987 STM32_FUNCTION(0, "GPIOK0"), 2141 STM32_FUNCTION(0, "GPIOK0"),
1988 STM32_FUNCTION(2, "TIM1_CH1N"), 2142 STM32_FUNCTION(2, "TIM1_CH1N"),
1989 STM32_FUNCTION(4, "TIM8_CH3"), 2143 STM32_FUNCTION(4, "TIM8_CH3"),
@@ -1992,8 +2146,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
1992 STM32_FUNCTION(16, "EVENTOUT"), 2146 STM32_FUNCTION(16, "EVENTOUT"),
1993 STM32_FUNCTION(17, "ANALOG") 2147 STM32_FUNCTION(17, "ANALOG")
1994 ), 2148 ),
1995 STM32_PIN( 2149 STM32_PIN_PKG(
1996 PINCTRL_PIN(161, "PK1"), 2150 PINCTRL_PIN(161, "PK1"),
2151 STM32MP_PKG_AA,
1997 STM32_FUNCTION(0, "GPIOK1"), 2152 STM32_FUNCTION(0, "GPIOK1"),
1998 STM32_FUNCTION(1, "TRACED4"), 2153 STM32_FUNCTION(1, "TRACED4"),
1999 STM32_FUNCTION(2, "TIM1_CH1"), 2154 STM32_FUNCTION(2, "TIM1_CH1"),
@@ -2004,8 +2159,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
2004 STM32_FUNCTION(16, "EVENTOUT"), 2159 STM32_FUNCTION(16, "EVENTOUT"),
2005 STM32_FUNCTION(17, "ANALOG") 2160 STM32_FUNCTION(17, "ANALOG")
2006 ), 2161 ),
2007 STM32_PIN( 2162 STM32_PIN_PKG(
2008 PINCTRL_PIN(162, "PK2"), 2163 PINCTRL_PIN(162, "PK2"),
2164 STM32MP_PKG_AA,
2009 STM32_FUNCTION(0, "GPIOK2"), 2165 STM32_FUNCTION(0, "GPIOK2"),
2010 STM32_FUNCTION(1, "TRACED5"), 2166 STM32_FUNCTION(1, "TRACED5"),
2011 STM32_FUNCTION(2, "TIM1_BKIN"), 2167 STM32_FUNCTION(2, "TIM1_BKIN"),
@@ -2015,22 +2171,25 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
2015 STM32_FUNCTION(16, "EVENTOUT"), 2171 STM32_FUNCTION(16, "EVENTOUT"),
2016 STM32_FUNCTION(17, "ANALOG") 2172 STM32_FUNCTION(17, "ANALOG")
2017 ), 2173 ),
2018 STM32_PIN( 2174 STM32_PIN_PKG(
2019 PINCTRL_PIN(163, "PK3"), 2175 PINCTRL_PIN(163, "PK3"),
2176 STM32MP_PKG_AA,
2020 STM32_FUNCTION(0, "GPIOK3"), 2177 STM32_FUNCTION(0, "GPIOK3"),
2021 STM32_FUNCTION(15, "LCD_B4"), 2178 STM32_FUNCTION(15, "LCD_B4"),
2022 STM32_FUNCTION(16, "EVENTOUT"), 2179 STM32_FUNCTION(16, "EVENTOUT"),
2023 STM32_FUNCTION(17, "ANALOG") 2180 STM32_FUNCTION(17, "ANALOG")
2024 ), 2181 ),
2025 STM32_PIN( 2182 STM32_PIN_PKG(
2026 PINCTRL_PIN(164, "PK4"), 2183 PINCTRL_PIN(164, "PK4"),
2184 STM32MP_PKG_AA,
2027 STM32_FUNCTION(0, "GPIOK4"), 2185 STM32_FUNCTION(0, "GPIOK4"),
2028 STM32_FUNCTION(15, "LCD_B5"), 2186 STM32_FUNCTION(15, "LCD_B5"),
2029 STM32_FUNCTION(16, "EVENTOUT"), 2187 STM32_FUNCTION(16, "EVENTOUT"),
2030 STM32_FUNCTION(17, "ANALOG") 2188 STM32_FUNCTION(17, "ANALOG")
2031 ), 2189 ),
2032 STM32_PIN( 2190 STM32_PIN_PKG(
2033 PINCTRL_PIN(165, "PK5"), 2191 PINCTRL_PIN(165, "PK5"),
2192 STM32MP_PKG_AA,
2034 STM32_FUNCTION(0, "GPIOK5"), 2193 STM32_FUNCTION(0, "GPIOK5"),
2035 STM32_FUNCTION(1, "TRACED6"), 2194 STM32_FUNCTION(1, "TRACED6"),
2036 STM32_FUNCTION(3, "HDP6"), 2195 STM32_FUNCTION(3, "HDP6"),
@@ -2038,8 +2197,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
2038 STM32_FUNCTION(16, "EVENTOUT"), 2197 STM32_FUNCTION(16, "EVENTOUT"),
2039 STM32_FUNCTION(17, "ANALOG") 2198 STM32_FUNCTION(17, "ANALOG")
2040 ), 2199 ),
2041 STM32_PIN( 2200 STM32_PIN_PKG(
2042 PINCTRL_PIN(166, "PK6"), 2201 PINCTRL_PIN(166, "PK6"),
2202 STM32MP_PKG_AA,
2043 STM32_FUNCTION(0, "GPIOK6"), 2203 STM32_FUNCTION(0, "GPIOK6"),
2044 STM32_FUNCTION(1, "TRACED7"), 2204 STM32_FUNCTION(1, "TRACED7"),
2045 STM32_FUNCTION(3, "HDP7"), 2205 STM32_FUNCTION(3, "HDP7"),
@@ -2047,8 +2207,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
2047 STM32_FUNCTION(16, "EVENTOUT"), 2207 STM32_FUNCTION(16, "EVENTOUT"),
2048 STM32_FUNCTION(17, "ANALOG") 2208 STM32_FUNCTION(17, "ANALOG")
2049 ), 2209 ),
2050 STM32_PIN( 2210 STM32_PIN_PKG(
2051 PINCTRL_PIN(167, "PK7"), 2211 PINCTRL_PIN(167, "PK7"),
2212 STM32MP_PKG_AA,
2052 STM32_FUNCTION(0, "GPIOK7"), 2213 STM32_FUNCTION(0, "GPIOK7"),
2053 STM32_FUNCTION(15, "LCD_DE"), 2214 STM32_FUNCTION(15, "LCD_DE"),
2054 STM32_FUNCTION(16, "EVENTOUT"), 2215 STM32_FUNCTION(16, "EVENTOUT"),
@@ -2057,8 +2218,9 @@ static const struct stm32_desc_pin stm32mp157_pins[] = {
2057}; 2218};
2058 2219
2059static const struct stm32_desc_pin stm32mp157_z_pins[] = { 2220static const struct stm32_desc_pin stm32mp157_z_pins[] = {
2060 STM32_PIN( 2221 STM32_PIN_PKG(
2061 PINCTRL_PIN(400, "PZ0"), 2222 PINCTRL_PIN(400, "PZ0"),
2223 STM32MP_PKG_AA | STM32MP_PKG_AC,
2062 STM32_FUNCTION(0, "GPIOZ0"), 2224 STM32_FUNCTION(0, "GPIOZ0"),
2063 STM32_FUNCTION(3, "I2C6_SCL"), 2225 STM32_FUNCTION(3, "I2C6_SCL"),
2064 STM32_FUNCTION(4, "I2C2_SCL"), 2226 STM32_FUNCTION(4, "I2C2_SCL"),
@@ -2068,8 +2230,9 @@ static const struct stm32_desc_pin stm32mp157_z_pins[] = {
2068 STM32_FUNCTION(16, "EVENTOUT"), 2230 STM32_FUNCTION(16, "EVENTOUT"),
2069 STM32_FUNCTION(17, "ANALOG") 2231 STM32_FUNCTION(17, "ANALOG")
2070 ), 2232 ),
2071 STM32_PIN( 2233 STM32_PIN_PKG(
2072 PINCTRL_PIN(401, "PZ1"), 2234 PINCTRL_PIN(401, "PZ1"),
2235 STM32MP_PKG_AA | STM32MP_PKG_AC,
2073 STM32_FUNCTION(0, "GPIOZ1"), 2236 STM32_FUNCTION(0, "GPIOZ1"),
2074 STM32_FUNCTION(3, "I2C6_SDA"), 2237 STM32_FUNCTION(3, "I2C6_SDA"),
2075 STM32_FUNCTION(4, "I2C2_SDA"), 2238 STM32_FUNCTION(4, "I2C2_SDA"),
@@ -2081,8 +2244,9 @@ static const struct stm32_desc_pin stm32mp157_z_pins[] = {
2081 STM32_FUNCTION(16, "EVENTOUT"), 2244 STM32_FUNCTION(16, "EVENTOUT"),
2082 STM32_FUNCTION(17, "ANALOG") 2245 STM32_FUNCTION(17, "ANALOG")
2083 ), 2246 ),
2084 STM32_PIN( 2247 STM32_PIN_PKG(
2085 PINCTRL_PIN(402, "PZ2"), 2248 PINCTRL_PIN(402, "PZ2"),
2249 STM32MP_PKG_AA | STM32MP_PKG_AC,
2086 STM32_FUNCTION(0, "GPIOZ2"), 2250 STM32_FUNCTION(0, "GPIOZ2"),
2087 STM32_FUNCTION(3, "I2C6_SCL"), 2251 STM32_FUNCTION(3, "I2C6_SCL"),
2088 STM32_FUNCTION(4, "I2C2_SCL"), 2252 STM32_FUNCTION(4, "I2C2_SCL"),
@@ -2094,21 +2258,23 @@ static const struct stm32_desc_pin stm32mp157_z_pins[] = {
2094 STM32_FUNCTION(16, "EVENTOUT"), 2258 STM32_FUNCTION(16, "EVENTOUT"),
2095 STM32_FUNCTION(17, "ANALOG") 2259 STM32_FUNCTION(17, "ANALOG")
2096 ), 2260 ),
2097 STM32_PIN( 2261 STM32_PIN_PKG(
2098 PINCTRL_PIN(403, "PZ3"), 2262 PINCTRL_PIN(403, "PZ3"),
2263 STM32MP_PKG_AA | STM32MP_PKG_AC,
2099 STM32_FUNCTION(0, "GPIOZ3"), 2264 STM32_FUNCTION(0, "GPIOZ3"),
2100 STM32_FUNCTION(3, "I2C6_SDA"), 2265 STM32_FUNCTION(3, "I2C6_SDA"),
2101 STM32_FUNCTION(4, "I2C2_SDA"), 2266 STM32_FUNCTION(4, "I2C2_SDA"),
2102 STM32_FUNCTION(5, "I2C5_SDA"), 2267 STM32_FUNCTION(5, "I2C5_SDA"),
2103 STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"), 2268 STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
2104 STM32_FUNCTION(7, "I2C4_SDA"), 2269 STM32_FUNCTION(7, "I2C4_SDA"),
2105 STM32_FUNCTION(8, "USART1_CTS_NSS"), 2270 STM32_FUNCTION(8, "USART1_CTS USART1_NSS"),
2106 STM32_FUNCTION(9, "SPI6_NSS"), 2271 STM32_FUNCTION(9, "SPI6_NSS"),
2107 STM32_FUNCTION(16, "EVENTOUT"), 2272 STM32_FUNCTION(16, "EVENTOUT"),
2108 STM32_FUNCTION(17, "ANALOG") 2273 STM32_FUNCTION(17, "ANALOG")
2109 ), 2274 ),
2110 STM32_PIN( 2275 STM32_PIN_PKG(
2111 PINCTRL_PIN(404, "PZ4"), 2276 PINCTRL_PIN(404, "PZ4"),
2277 STM32MP_PKG_AA | STM32MP_PKG_AC,
2112 STM32_FUNCTION(0, "GPIOZ4"), 2278 STM32_FUNCTION(0, "GPIOZ4"),
2113 STM32_FUNCTION(3, "I2C6_SCL"), 2279 STM32_FUNCTION(3, "I2C6_SCL"),
2114 STM32_FUNCTION(4, "I2C2_SCL"), 2280 STM32_FUNCTION(4, "I2C2_SCL"),
@@ -2117,19 +2283,21 @@ static const struct stm32_desc_pin stm32mp157_z_pins[] = {
2117 STM32_FUNCTION(16, "EVENTOUT"), 2283 STM32_FUNCTION(16, "EVENTOUT"),
2118 STM32_FUNCTION(17, "ANALOG") 2284 STM32_FUNCTION(17, "ANALOG")
2119 ), 2285 ),
2120 STM32_PIN( 2286 STM32_PIN_PKG(
2121 PINCTRL_PIN(405, "PZ5"), 2287 PINCTRL_PIN(405, "PZ5"),
2288 STM32MP_PKG_AA | STM32MP_PKG_AC,
2122 STM32_FUNCTION(0, "GPIOZ5"), 2289 STM32_FUNCTION(0, "GPIOZ5"),
2123 STM32_FUNCTION(3, "I2C6_SDA"), 2290 STM32_FUNCTION(3, "I2C6_SDA"),
2124 STM32_FUNCTION(4, "I2C2_SDA"), 2291 STM32_FUNCTION(4, "I2C2_SDA"),
2125 STM32_FUNCTION(5, "I2C5_SDA"), 2292 STM32_FUNCTION(5, "I2C5_SDA"),
2126 STM32_FUNCTION(7, "I2C4_SDA"), 2293 STM32_FUNCTION(7, "I2C4_SDA"),
2127 STM32_FUNCTION(8, "USART1_RTS"), 2294 STM32_FUNCTION(8, "USART1_RTS USART1_DE"),
2128 STM32_FUNCTION(16, "EVENTOUT"), 2295 STM32_FUNCTION(16, "EVENTOUT"),
2129 STM32_FUNCTION(17, "ANALOG") 2296 STM32_FUNCTION(17, "ANALOG")
2130 ), 2297 ),
2131 STM32_PIN( 2298 STM32_PIN_PKG(
2132 PINCTRL_PIN(406, "PZ6"), 2299 PINCTRL_PIN(406, "PZ6"),
2300 STM32MP_PKG_AA | STM32MP_PKG_AC,
2133 STM32_FUNCTION(0, "GPIOZ6"), 2301 STM32_FUNCTION(0, "GPIOZ6"),
2134 STM32_FUNCTION(3, "I2C6_SCL"), 2302 STM32_FUNCTION(3, "I2C6_SCL"),
2135 STM32_FUNCTION(4, "I2C2_SCL"), 2303 STM32_FUNCTION(4, "I2C2_SCL"),
@@ -2140,8 +2308,9 @@ static const struct stm32_desc_pin stm32mp157_z_pins[] = {
2140 STM32_FUNCTION(16, "EVENTOUT"), 2308 STM32_FUNCTION(16, "EVENTOUT"),
2141 STM32_FUNCTION(17, "ANALOG") 2309 STM32_FUNCTION(17, "ANALOG")
2142 ), 2310 ),
2143 STM32_PIN( 2311 STM32_PIN_PKG(
2144 PINCTRL_PIN(407, "PZ7"), 2312 PINCTRL_PIN(407, "PZ7"),
2313 STM32MP_PKG_AA | STM32MP_PKG_AC,
2145 STM32_FUNCTION(0, "GPIOZ7"), 2314 STM32_FUNCTION(0, "GPIOZ7"),
2146 STM32_FUNCTION(3, "I2C6_SDA"), 2315 STM32_FUNCTION(3, "I2C6_SDA"),
2147 STM32_FUNCTION(4, "I2C2_SDA"), 2316 STM32_FUNCTION(4, "I2C2_SDA"),
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index a731fc966b63..9093a420d310 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -11,82 +11,101 @@ config PINCTRL_SUNIV_F1C100S
11 select PINCTRL_SUNXI 11 select PINCTRL_SUNXI
12 12
13config PINCTRL_SUN4I_A10 13config PINCTRL_SUN4I_A10
14 def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I 14 bool "Support for the Allwinner A10, A20 and R40 PIO"
15 default MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
15 select PINCTRL_SUNXI 16 select PINCTRL_SUNXI
16 17
17config PINCTRL_SUN5I 18config PINCTRL_SUN5I
18 def_bool MACH_SUN5I 19 bool "Support for the Allwinner A10s, A13, R8 and NextThing GR8 PIO"
20 default MACH_SUN5I
19 select PINCTRL_SUNXI 21 select PINCTRL_SUNXI
20 22
21config PINCTRL_SUN6I_A31 23config PINCTRL_SUN6I_A31
22 def_bool MACH_SUN6I 24 bool "Support for the Allwinner A31 PIO"
25 default MACH_SUN6I
23 select PINCTRL_SUNXI 26 select PINCTRL_SUNXI
24 27
25config PINCTRL_SUN6I_A31_R 28config PINCTRL_SUN6I_A31_R
26 def_bool MACH_SUN6I 29 bool "Support for the Allwinner A31 R-PIO"
30 default MACH_SUN6I
27 depends on RESET_CONTROLLER 31 depends on RESET_CONTROLLER
28 select PINCTRL_SUNXI 32 select PINCTRL_SUNXI
29 33
30config PINCTRL_SUN8I_A23 34config PINCTRL_SUN8I_A23
31 def_bool MACH_SUN8I 35 bool "Support for the Allwinner A23 PIO"
36 default MACH_SUN8I
32 select PINCTRL_SUNXI 37 select PINCTRL_SUNXI
33 38
34config PINCTRL_SUN8I_A33 39config PINCTRL_SUN8I_A33
35 def_bool MACH_SUN8I 40 bool "Support for the Allwinner A33 PIO"
41 default MACH_SUN8I
36 select PINCTRL_SUNXI 42 select PINCTRL_SUNXI
37 43
38config PINCTRL_SUN8I_A83T 44config PINCTRL_SUN8I_A83T
39 def_bool MACH_SUN8I 45 bool "Support for the Allwinner A83T PIO"
46 default MACH_SUN8I
40 select PINCTRL_SUNXI 47 select PINCTRL_SUNXI
41 48
42config PINCTRL_SUN8I_A83T_R 49config PINCTRL_SUN8I_A83T_R
43 def_bool MACH_SUN8I 50 bool "Support for the Allwinner A83T R-PIO"
51 default MACH_SUN8I
44 select PINCTRL_SUNXI 52 select PINCTRL_SUNXI
45 53
46config PINCTRL_SUN8I_A23_R 54config PINCTRL_SUN8I_A23_R
47 def_bool MACH_SUN8I 55 bool "Support for the Allwinner A23 and A33 R-PIO"
56 default MACH_SUN8I
48 depends on RESET_CONTROLLER 57 depends on RESET_CONTROLLER
49 select PINCTRL_SUNXI 58 select PINCTRL_SUNXI
50 59
51config PINCTRL_SUN8I_H3 60config PINCTRL_SUN8I_H3
52 def_bool MACH_SUN8I 61 bool "Support for the Allwinner H3 PIO"
62 default MACH_SUN8I
53 select PINCTRL_SUNXI 63 select PINCTRL_SUNXI
54 64
55config PINCTRL_SUN8I_H3_R 65config PINCTRL_SUN8I_H3_R
56 def_bool MACH_SUN8I || (ARM64 && ARCH_SUNXI) 66 bool "Support for the Allwinner H3 and H5 R-PIO"
67 default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
57 select PINCTRL_SUNXI 68 select PINCTRL_SUNXI
58 69
59config PINCTRL_SUN8I_V3S 70config PINCTRL_SUN8I_V3S
60 def_bool MACH_SUN8I 71 bool "Support for the Allwinner V3s PIO"
72 default MACH_SUN8I
61 select PINCTRL_SUNXI 73 select PINCTRL_SUNXI
62 74
63config PINCTRL_SUN9I_A80 75config PINCTRL_SUN9I_A80
64 def_bool MACH_SUN9I 76 bool "Support for the Allwinner A80 PIO"
77 default MACH_SUN9I
65 select PINCTRL_SUNXI 78 select PINCTRL_SUNXI
66 79
67config PINCTRL_SUN9I_A80_R 80config PINCTRL_SUN9I_A80_R
68 def_bool MACH_SUN9I 81 bool "Support for the Allwinner A80 R-PIO"
82 default MACH_SUN9I
69 depends on RESET_CONTROLLER 83 depends on RESET_CONTROLLER
70 select PINCTRL_SUNXI 84 select PINCTRL_SUNXI
71 85
72config PINCTRL_SUN50I_A64 86config PINCTRL_SUN50I_A64
73 def_bool ARM64 && ARCH_SUNXI 87 bool "Support for the Allwinner A64 PIO"
88 default ARM64 && ARCH_SUNXI
74 select PINCTRL_SUNXI 89 select PINCTRL_SUNXI
75 90
76config PINCTRL_SUN50I_A64_R 91config PINCTRL_SUN50I_A64_R
77 def_bool ARM64 && ARCH_SUNXI 92 bool "Support for the Allwinner A64 R-PIO"
93 default ARM64 && ARCH_SUNXI
78 select PINCTRL_SUNXI 94 select PINCTRL_SUNXI
79 95
80config PINCTRL_SUN50I_H5 96config PINCTRL_SUN50I_H5
81 def_bool ARM64 && ARCH_SUNXI 97 bool "Support for the Allwinner H5 PIO"
98 default ARM64 && ARCH_SUNXI
82 select PINCTRL_SUNXI 99 select PINCTRL_SUNXI
83 100
84config PINCTRL_SUN50I_H6 101config PINCTRL_SUN50I_H6
85 def_bool ARM64 && ARCH_SUNXI 102 bool "Support for the Allwinner H6 PIO"
103 default ARM64 && ARCH_SUNXI
86 select PINCTRL_SUNXI 104 select PINCTRL_SUNXI
87 105
88config PINCTRL_SUN50I_H6_R 106config PINCTRL_SUN50I_H6_R
89 def_bool ARM64 && ARCH_SUNXI 107 bool "Support for the Allwinner H6 R-PIO"
108 default ARM64 && ARCH_SUNXI
90 select PINCTRL_SUNXI 109 select PINCTRL_SUNXI
91 110
92endif 111endif
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
index ef4268cc6227..3cc1121589c9 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
@@ -591,6 +591,7 @@ static const struct sunxi_pinctrl_desc h6_pinctrl_data = {
591 .irq_banks = 4, 591 .irq_banks = 4,
592 .irq_bank_map = h6_irq_bank_map, 592 .irq_bank_map = h6_irq_bank_map,
593 .irq_read_needs_mux = true, 593 .irq_read_needs_mux = true,
594 .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
594}; 595};
595 596
596static int h6_pinctrl_probe(struct platform_device *pdev) 597static int h6_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
index e05dd9a5551d..a191a65217ac 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
@@ -153,7 +153,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = {
153 .pin_base = PL_BASE, 153 .pin_base = PL_BASE,
154 .irq_banks = 2, 154 .irq_banks = 2,
155 .disable_strict_mode = true, 155 .disable_strict_mode = true,
156 .has_io_bias_cfg = true, 156 .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG,
157}; 157};
158 158
159static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev) 159static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c
index da37d594a13d..0633a03d5e13 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c
@@ -722,7 +722,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_data = {
722 .npins = ARRAY_SIZE(sun9i_a80_pins), 722 .npins = ARRAY_SIZE(sun9i_a80_pins),
723 .irq_banks = 5, 723 .irq_banks = 5,
724 .disable_strict_mode = true, 724 .disable_strict_mode = true,
725 .has_io_bias_cfg = true, 725 .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG,
726}; 726};
727 727
728static int sun9i_a80_pinctrl_probe(struct platform_device *pdev) 728static int sun9i_a80_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 8dd25caea2cf..0cbca30b75dc 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -530,14 +530,10 @@ static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
530 return sunxi_pconf_get(pctldev, g->pin, config); 530 return sunxi_pconf_get(pctldev, g->pin, config);
531} 531}
532 532
533static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, 533static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
534 unsigned group, 534 unsigned long *configs, unsigned num_configs)
535 unsigned long *configs,
536 unsigned num_configs)
537{ 535{
538 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 536 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
539 struct sunxi_pinctrl_group *g = &pctl->groups[group];
540 unsigned pin = g->pin - pctl->desc->pin_base;
541 int i; 537 int i;
542 538
543 for (i = 0; i < num_configs; i++) { 539 for (i = 0; i < num_configs; i++) {
@@ -596,9 +592,20 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
596 return 0; 592 return 0;
597} 593}
598 594
595static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
596 unsigned long *configs, unsigned num_configs)
597{
598 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
599 struct sunxi_pinctrl_group *g = &pctl->groups[group];
600
601 /* We only support 1 pin per group. Chain it to the pin callback */
602 return sunxi_pconf_set(pctldev, g->pin, configs, num_configs);
603}
604
599static const struct pinconf_ops sunxi_pconf_ops = { 605static const struct pinconf_ops sunxi_pconf_ops = {
600 .is_generic = true, 606 .is_generic = true,
601 .pin_config_get = sunxi_pconf_get, 607 .pin_config_get = sunxi_pconf_get,
608 .pin_config_set = sunxi_pconf_set,
602 .pin_config_group_get = sunxi_pconf_group_get, 609 .pin_config_group_get = sunxi_pconf_group_get,
603 .pin_config_group_set = sunxi_pconf_group_set, 610 .pin_config_group_set = sunxi_pconf_group_set,
604}; 611};
@@ -607,10 +614,12 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
607 unsigned pin, 614 unsigned pin,
608 struct regulator *supply) 615 struct regulator *supply)
609{ 616{
617 unsigned short bank = pin / PINS_PER_BANK;
618 unsigned long flags;
610 u32 val, reg; 619 u32 val, reg;
611 int uV; 620 int uV;
612 621
613 if (!pctl->desc->has_io_bias_cfg) 622 if (!pctl->desc->io_bias_cfg_variant)
614 return 0; 623 return 0;
615 624
616 uV = regulator_get_voltage(supply); 625 uV = regulator_get_voltage(supply);
@@ -621,25 +630,41 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
621 if (uV == 0) 630 if (uV == 0)
622 return 0; 631 return 0;
623 632
624 /* Configured value must be equal or greater to actual voltage */ 633 switch (pctl->desc->io_bias_cfg_variant) {
625 if (uV <= 1800000) 634 case BIAS_VOLTAGE_GRP_CONFIG:
626 val = 0x0; /* 1.8V */ 635 /*
627 else if (uV <= 2500000) 636 * Configured value must be equal or greater to actual
628 val = 0x6; /* 2.5V */ 637 * voltage.
629 else if (uV <= 2800000) 638 */
630 val = 0x9; /* 2.8V */ 639 if (uV <= 1800000)
631 else if (uV <= 3000000) 640 val = 0x0; /* 1.8V */
632 val = 0xA; /* 3.0V */ 641 else if (uV <= 2500000)
633 else 642 val = 0x6; /* 2.5V */
634 val = 0xD; /* 3.3V */ 643 else if (uV <= 2800000)
635 644 val = 0x9; /* 2.8V */
636 pin -= pctl->desc->pin_base; 645 else if (uV <= 3000000)
637 646 val = 0xA; /* 3.0V */
638 reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); 647 else
639 reg &= ~IO_BIAS_MASK; 648 val = 0xD; /* 3.3V */
640 writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); 649
650 pin -= pctl->desc->pin_base;
651
652 reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
653 reg &= ~IO_BIAS_MASK;
654 writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
655 return 0;
656 case BIAS_VOLTAGE_PIO_POW_MODE_SEL:
657 val = uV <= 1800000 ? 1 : 0;
641 658
642 return 0; 659 raw_spin_lock_irqsave(&pctl->lock, flags);
660 reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);
661 reg &= ~(1 << bank);
662 writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);
663 raw_spin_unlock_irqrestore(&pctl->lock, flags);
664 return 0;
665 default:
666 return -EINVAL;
667 }
643} 668}
644 669
645static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 670static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
@@ -1443,16 +1468,17 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
1443 1468
1444 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; 1469 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
1445 pctl->chip->owner = THIS_MODULE; 1470 pctl->chip->owner = THIS_MODULE;
1446 pctl->chip->request = gpiochip_generic_request, 1471 pctl->chip->request = gpiochip_generic_request;
1447 pctl->chip->free = gpiochip_generic_free, 1472 pctl->chip->free = gpiochip_generic_free;
1448 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input, 1473 pctl->chip->set_config = gpiochip_generic_config;
1449 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output, 1474 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input;
1450 pctl->chip->get = sunxi_pinctrl_gpio_get, 1475 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output;
1451 pctl->chip->set = sunxi_pinctrl_gpio_set, 1476 pctl->chip->get = sunxi_pinctrl_gpio_get;
1452 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate, 1477 pctl->chip->set = sunxi_pinctrl_gpio_set;
1453 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq, 1478 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate;
1454 pctl->chip->of_gpio_n_cells = 3, 1479 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq;
1455 pctl->chip->can_sleep = false, 1480 pctl->chip->of_gpio_n_cells = 3;
1481 pctl->chip->can_sleep = false;
1456 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) - 1482 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
1457 pctl->desc->pin_base; 1483 pctl->desc->pin_base;
1458 pctl->chip->label = dev_name(&pdev->dev); 1484 pctl->chip->label = dev_name(&pdev->dev);
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index ee15ab067b5f..44e30deeee38 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -95,6 +95,22 @@
95#define PINCTRL_SUN7I_A20 BIT(7) 95#define PINCTRL_SUN7I_A20 BIT(7)
96#define PINCTRL_SUN8I_R40 BIT(8) 96#define PINCTRL_SUN8I_R40 BIT(8)
97 97
98#define PIO_POW_MOD_SEL_REG 0x340
99
100enum sunxi_desc_bias_voltage {
101 BIAS_VOLTAGE_NONE,
102 /*
103 * Bias voltage configuration is done through
104 * Pn_GRP_CONFIG registers, as seen on A80 SoC.
105 */
106 BIAS_VOLTAGE_GRP_CONFIG,
107 /*
108 * Bias voltage is set through PIO_POW_MOD_SEL_REG
109 * register, as seen on H6 SoC, for example.
110 */
111 BIAS_VOLTAGE_PIO_POW_MODE_SEL,
112};
113
98struct sunxi_desc_function { 114struct sunxi_desc_function {
99 unsigned long variant; 115 unsigned long variant;
100 const char *name; 116 const char *name;
@@ -117,7 +133,7 @@ struct sunxi_pinctrl_desc {
117 const unsigned int *irq_bank_map; 133 const unsigned int *irq_bank_map;
118 bool irq_read_needs_mux; 134 bool irq_read_needs_mux;
119 bool disable_strict_mode; 135 bool disable_strict_mode;
120 bool has_io_bias_cfg; 136 enum sunxi_desc_bias_voltage io_bias_cfg_variant;
121}; 137};
122 138
123struct sunxi_pinctrl_function { 139struct sunxi_pinctrl_function {
diff --git a/drivers/pinctrl/zte/pinctrl-zx.c b/drivers/pinctrl/zte/pinctrl-zx.c
index caa44dd2880a..3cb69309912b 100644
--- a/drivers/pinctrl/zte/pinctrl-zx.c
+++ b/drivers/pinctrl/zte/pinctrl-zx.c
@@ -411,6 +411,7 @@ int zx_pinctrl_init(struct platform_device *pdev,
411 } 411 }
412 412
413 zpctl->aux_base = of_iomap(np, 0); 413 zpctl->aux_base = of_iomap(np, 0);
414 of_node_put(np);
414 if (!zpctl->aux_base) 415 if (!zpctl->aux_base)
415 return -ENOMEM; 416 return -ENOMEM;
416 417
diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h
index b5a2174a6386..e6fb8ada3f4d 100644
--- a/include/dt-bindings/pinctrl/stm32-pinfunc.h
+++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h
@@ -32,5 +32,11 @@
32 32
33#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode)) 33#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode))
34 34
35/* package information */
36#define STM32MP_PKG_AA 0x1
37#define STM32MP_PKG_AB 0x2
38#define STM32MP_PKG_AC 0x4
39#define STM32MP_PKG_AD 0x8
40
35#endif /* _DT_BINDINGS_STM32_PINFUNC_H */ 41#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
36 42
diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h
index 01497910f023..951be1715c12 100644
--- a/include/linux/gpio/driver.h
+++ b/include/linux/gpio/driver.h
@@ -614,6 +614,9 @@ struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
614 enum gpiod_flags flags); 614 enum gpiod_flags flags);
615void gpiochip_free_own_desc(struct gpio_desc *desc); 615void gpiochip_free_own_desc(struct gpio_desc *desc);
616 616
617void devprop_gpiochip_set_names(struct gpio_chip *chip,
618 const struct fwnode_handle *fwnode);
619
617#else /* CONFIG_GPIOLIB */ 620#else /* CONFIG_GPIOLIB */
618 621
619static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc) 622static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-30 11:56:00 -0500