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-rw-r--r--drivers/clk/rockchip/clk-rk3288.c13
1 files changed, 4 insertions, 9 deletions
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index e8b5a6bfcc8a..24baeb56a1b3 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -313,13 +313,13 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
313 COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED, 313 COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
314 RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 314 RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
315 RK3288_CLKGATE_CON(12), 6, GFLAGS), 315 RK3288_CLKGATE_CON(12), 6, GFLAGS),
316 COMPOSITE_NOMUX(0, "atclk", "armclk", CLK_IGNORE_UNUSED, 316 COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
317 RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 317 RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
318 RK3288_CLKGATE_CON(12), 7, GFLAGS), 318 RK3288_CLKGATE_CON(12), 7, GFLAGS),
319 COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED, 319 COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
320 RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 320 RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
321 RK3288_CLKGATE_CON(12), 8, GFLAGS), 321 RK3288_CLKGATE_CON(12), 8, GFLAGS),
322 GATE(0, "pclk_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED, 322 GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
323 RK3288_CLKGATE_CON(12), 9, GFLAGS), 323 RK3288_CLKGATE_CON(12), 9, GFLAGS),
324 GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED, 324 GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
325 RK3288_CLKGATE_CON(12), 10, GFLAGS), 325 RK3288_CLKGATE_CON(12), 10, GFLAGS),
@@ -647,7 +647,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
647 INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out", 647 INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
648 RK3288_CLKSEL_CON(22), 7, IFLAGS), 648 RK3288_CLKSEL_CON(22), 7, IFLAGS),
649 649
650 GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED, 650 GATE(0, "jtag", "ext_jtag", 0,
651 RK3288_CLKGATE_CON(4), 14, GFLAGS), 651 RK3288_CLKGATE_CON(4), 14, GFLAGS),
652 652
653 COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0, 653 COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,
@@ -656,7 +656,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
656 COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0, 656 COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
657 RK3288_CLKSEL_CON(29), 0, 2, MFLAGS, 657 RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
658 RK3288_CLKGATE_CON(3), 6, GFLAGS), 658 RK3288_CLKGATE_CON(3), 6, GFLAGS),
659 GATE(0, "hsicphy12m_xin12m", "xin12m", CLK_IGNORE_UNUSED, 659 GATE(0, "hsicphy12m_xin12m", "xin12m", 0,
660 RK3288_CLKGATE_CON(13), 9, GFLAGS), 660 RK3288_CLKGATE_CON(13), 9, GFLAGS),
661 DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0, 661 DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,
662 RK3288_CLKSEL_CON(11), 8, 6, DFLAGS), 662 RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
@@ -837,11 +837,6 @@ static const char *const rk3288_critical_clocks[] __initconst = {
837 "pclk_alive_niu", 837 "pclk_alive_niu",
838 "pclk_pd_pmu", 838 "pclk_pd_pmu",
839 "pclk_pmu_niu", 839 "pclk_pmu_niu",
840 "pclk_core_niu",
841 "pclk_ddrupctl0",
842 "pclk_publ0",
843 "pclk_ddrupctl1",
844 "pclk_publ1",
845 "pmu_hclk_otg0", 840 "pmu_hclk_otg0",
846 /* pwm-regulators on some boards, so handoff-critical later */ 841 /* pwm-regulators on some boards, so handoff-critical later */
847 "pclk_rkpwm", 842 "pclk_rkpwm",