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-rw-r--r--arch/powerpc/include/asm/opal-api.h74
-rw-r--r--arch/powerpc/include/asm/opal.h36
-rw-r--r--arch/powerpc/platforms/powernv/opal-wrappers.S15
3 files changed, 124 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h
index a0aa285869b5..bc8ac3c0e649 100644
--- a/arch/powerpc/include/asm/opal-api.h
+++ b/arch/powerpc/include/asm/opal-api.h
@@ -40,6 +40,8 @@
40#define OPAL_I2C_ARBT_LOST -22 40#define OPAL_I2C_ARBT_LOST -22
41#define OPAL_I2C_NACK_RCVD -23 41#define OPAL_I2C_NACK_RCVD -23
42#define OPAL_I2C_STOP_ERR -24 42#define OPAL_I2C_STOP_ERR -24
43#define OPAL_XIVE_PROVISIONING -31
44#define OPAL_XIVE_FREE_ACTIVE -32
43 45
44/* API Tokens (in r0) */ 46/* API Tokens (in r0) */
45#define OPAL_INVALID_CALL -1 47#define OPAL_INVALID_CALL -1
@@ -168,7 +170,24 @@
168#define OPAL_INT_SET_MFRR 125 170#define OPAL_INT_SET_MFRR 125
169#define OPAL_PCI_TCE_KILL 126 171#define OPAL_PCI_TCE_KILL 126
170#define OPAL_NMMU_SET_PTCR 127 172#define OPAL_NMMU_SET_PTCR 127
171#define OPAL_LAST 127 173#define OPAL_XIVE_RESET 128
174#define OPAL_XIVE_GET_IRQ_INFO 129
175#define OPAL_XIVE_GET_IRQ_CONFIG 130
176#define OPAL_XIVE_SET_IRQ_CONFIG 131
177#define OPAL_XIVE_GET_QUEUE_INFO 132
178#define OPAL_XIVE_SET_QUEUE_INFO 133
179#define OPAL_XIVE_DONATE_PAGE 134
180#define OPAL_XIVE_ALLOCATE_VP_BLOCK 135
181#define OPAL_XIVE_FREE_VP_BLOCK 136
182#define OPAL_XIVE_GET_VP_INFO 137
183#define OPAL_XIVE_SET_VP_INFO 138
184#define OPAL_XIVE_ALLOCATE_IRQ 139
185#define OPAL_XIVE_FREE_IRQ 140
186#define OPAL_XIVE_SYNC 141
187#define OPAL_XIVE_DUMP 142
188#define OPAL_XIVE_RESERVED3 143
189#define OPAL_XIVE_RESERVED4 144
190#define OPAL_LAST 144
172 191
173/* Device tree flags */ 192/* Device tree flags */
174 193
@@ -928,6 +947,59 @@ enum {
928 OPAL_PCI_TCE_KILL_ALL, 947 OPAL_PCI_TCE_KILL_ALL,
929}; 948};
930 949
950/* The xive operation mode indicates the active "API" and
951 * corresponds to the "mode" parameter of the opal_xive_reset()
952 * call
953 */
954enum {
955 OPAL_XIVE_MODE_EMU = 0,
956 OPAL_XIVE_MODE_EXPL = 1,
957};
958
959/* Flags for OPAL_XIVE_GET_IRQ_INFO */
960enum {
961 OPAL_XIVE_IRQ_TRIGGER_PAGE = 0x00000001,
962 OPAL_XIVE_IRQ_STORE_EOI = 0x00000002,
963 OPAL_XIVE_IRQ_LSI = 0x00000004,
964 OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008,
965 OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010,
966 OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020,
967};
968
969/* Flags for OPAL_XIVE_GET/SET_QUEUE_INFO */
970enum {
971 OPAL_XIVE_EQ_ENABLED = 0x00000001,
972 OPAL_XIVE_EQ_ALWAYS_NOTIFY = 0x00000002,
973 OPAL_XIVE_EQ_ESCALATE = 0x00000004,
974};
975
976/* Flags for OPAL_XIVE_GET/SET_VP_INFO */
977enum {
978 OPAL_XIVE_VP_ENABLED = 0x00000001,
979};
980
981/* "Any chip" replacement for chip ID for allocation functions */
982enum {
983 OPAL_XIVE_ANY_CHIP = 0xffffffff,
984};
985
986/* Xive sync options */
987enum {
988 /* This bits are cumulative, arg is a girq */
989 XIVE_SYNC_EAS = 0x00000001, /* Sync irq source */
990 XIVE_SYNC_QUEUE = 0x00000002, /* Sync irq target */
991};
992
993/* Dump options */
994enum {
995 XIVE_DUMP_TM_HYP = 0,
996 XIVE_DUMP_TM_POOL = 1,
997 XIVE_DUMP_TM_OS = 2,
998 XIVE_DUMP_TM_USER = 3,
999 XIVE_DUMP_VP = 4,
1000 XIVE_DUMP_EMU_STATE = 5,
1001};
1002
931#endif /* __ASSEMBLY__ */ 1003#endif /* __ASSEMBLY__ */
932 1004
933#endif /* __OPAL_API_H */ 1005#endif /* __OPAL_API_H */
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 1ff03a6da76e..cb7d6078b03a 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -226,6 +226,42 @@ int64_t opal_pci_tce_kill(uint64_t phb_id, uint32_t kill_type,
226 uint32_t pe_num, uint32_t tce_size, 226 uint32_t pe_num, uint32_t tce_size,
227 uint64_t dma_addr, uint32_t npages); 227 uint64_t dma_addr, uint32_t npages);
228int64_t opal_nmmu_set_ptcr(uint64_t chip_id, uint64_t ptcr); 228int64_t opal_nmmu_set_ptcr(uint64_t chip_id, uint64_t ptcr);
229int64_t opal_xive_reset(uint64_t version);
230int64_t opal_xive_get_irq_info(uint32_t girq,
231 __be64 *out_flags,
232 __be64 *out_eoi_page,
233 __be64 *out_trig_page,
234 __be32 *out_esb_shift,
235 __be32 *out_src_chip);
236int64_t opal_xive_get_irq_config(uint32_t girq, __be64 *out_vp,
237 uint8_t *out_prio, __be32 *out_lirq);
238int64_t opal_xive_set_irq_config(uint32_t girq, uint64_t vp, uint8_t prio,
239 uint32_t lirq);
240int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio,
241 __be64 *out_qpage,
242 __be64 *out_qsize,
243 __be64 *out_qeoi_page,
244 __be32 *out_escalate_irq,
245 __be64 *out_qflags);
246int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio,
247 uint64_t qpage,
248 uint64_t qsize,
249 uint64_t qflags);
250int64_t opal_xive_donate_page(uint32_t chip_id, uint64_t addr);
251int64_t opal_xive_alloc_vp_block(uint32_t alloc_order);
252int64_t opal_xive_free_vp_block(uint64_t vp);
253int64_t opal_xive_get_vp_info(uint64_t vp,
254 __be64 *out_flags,
255 __be64 *out_cam_value,
256 __be64 *out_report_cl_pair,
257 __be32 *out_chip_id);
258int64_t opal_xive_set_vp_info(uint64_t vp,
259 uint64_t flags,
260 uint64_t report_cl_pair);
261int64_t opal_xive_allocate_irq(uint32_t chip_id);
262int64_t opal_xive_free_irq(uint32_t girq);
263int64_t opal_xive_sync(uint32_t type, uint32_t id);
264int64_t opal_xive_dump(uint32_t type, uint32_t id);
229 265
230/* Internal functions */ 266/* Internal functions */
231extern int early_init_dt_scan_opal(unsigned long node, const char *uname, 267extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S
index da8a0f7a035c..085605a73168 100644
--- a/arch/powerpc/platforms/powernv/opal-wrappers.S
+++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
@@ -301,3 +301,18 @@ OPAL_CALL(opal_int_eoi, OPAL_INT_EOI);
301OPAL_CALL(opal_int_set_mfrr, OPAL_INT_SET_MFRR); 301OPAL_CALL(opal_int_set_mfrr, OPAL_INT_SET_MFRR);
302OPAL_CALL(opal_pci_tce_kill, OPAL_PCI_TCE_KILL); 302OPAL_CALL(opal_pci_tce_kill, OPAL_PCI_TCE_KILL);
303OPAL_CALL(opal_nmmu_set_ptcr, OPAL_NMMU_SET_PTCR); 303OPAL_CALL(opal_nmmu_set_ptcr, OPAL_NMMU_SET_PTCR);
304OPAL_CALL(opal_xive_reset, OPAL_XIVE_RESET);
305OPAL_CALL(opal_xive_get_irq_info, OPAL_XIVE_GET_IRQ_INFO);
306OPAL_CALL(opal_xive_get_irq_config, OPAL_XIVE_GET_IRQ_CONFIG);
307OPAL_CALL(opal_xive_set_irq_config, OPAL_XIVE_SET_IRQ_CONFIG);
308OPAL_CALL(opal_xive_get_queue_info, OPAL_XIVE_GET_QUEUE_INFO);
309OPAL_CALL(opal_xive_set_queue_info, OPAL_XIVE_SET_QUEUE_INFO);
310OPAL_CALL(opal_xive_donate_page, OPAL_XIVE_DONATE_PAGE);
311OPAL_CALL(opal_xive_alloc_vp_block, OPAL_XIVE_ALLOCATE_VP_BLOCK);
312OPAL_CALL(opal_xive_free_vp_block, OPAL_XIVE_FREE_VP_BLOCK);
313OPAL_CALL(opal_xive_allocate_irq, OPAL_XIVE_ALLOCATE_IRQ);
314OPAL_CALL(opal_xive_free_irq, OPAL_XIVE_FREE_IRQ);
315OPAL_CALL(opal_xive_get_vp_info, OPAL_XIVE_GET_VP_INFO);
316OPAL_CALL(opal_xive_set_vp_info, OPAL_XIVE_SET_VP_INFO);
317OPAL_CALL(opal_xive_sync, OPAL_XIVE_SYNC);
318OPAL_CALL(opal_xive_dump, OPAL_XIVE_DUMP);