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-rw-r--r--drivers/irqchip/irq-nvic.c13
-rw-r--r--drivers/irqchip/spear-shirq.c304
-rw-r--r--include/linux/irqchip/spear-shirq.h64
3 files changed, 141 insertions, 240 deletions
diff --git a/drivers/irqchip/irq-nvic.c b/drivers/irqchip/irq-nvic.c
index 70bdf6edb7bb..4ff0805fca01 100644
--- a/drivers/irqchip/irq-nvic.c
+++ b/drivers/irqchip/irq-nvic.c
@@ -49,14 +49,6 @@ nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs)
49 handle_IRQ(irq, regs); 49 handle_IRQ(irq, regs);
50} 50}
51 51
52static void nvic_eoi(struct irq_data *d)
53{
54 /*
55 * This is a no-op as end of interrupt is signaled by the exception
56 * return sequence.
57 */
58}
59
60static int __init nvic_of_init(struct device_node *node, 52static int __init nvic_of_init(struct device_node *node,
61 struct device_node *parent) 53 struct device_node *parent)
62{ 54{
@@ -102,7 +94,10 @@ static int __init nvic_of_init(struct device_node *node,
102 gc->chip_types[0].regs.disable = NVIC_ICER; 94 gc->chip_types[0].regs.disable = NVIC_ICER;
103 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; 95 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
104 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; 96 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
105 gc->chip_types[0].chip.irq_eoi = nvic_eoi; 97 /* This is a no-op as end of interrupt is signaled by the
98 * exception return sequence.
99 */
100 gc->chip_types[0].chip.irq_eoi = irq_gc_noop;
106 101
107 /* disable interrupts */ 102 /* disable interrupts */
108 writel_relaxed(~0, gc->reg_base + NVIC_ICER); 103 writel_relaxed(~0, gc->reg_base + NVIC_ICER);
diff --git a/drivers/irqchip/spear-shirq.c b/drivers/irqchip/spear-shirq.c
index 6ce6bd3441bf..9c145a7cb056 100644
--- a/drivers/irqchip/spear-shirq.c
+++ b/drivers/irqchip/spear-shirq.c
@@ -19,7 +19,6 @@
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/irqdomain.h> 21#include <linux/irqdomain.h>
22#include <linux/irqchip/spear-shirq.h>
23#include <linux/of.h> 22#include <linux/of.h>
24#include <linux/of_address.h> 23#include <linux/of_address.h>
25#include <linux/of_irq.h> 24#include <linux/of_irq.h>
@@ -27,20 +26,73 @@
27 26
28#include "irqchip.h" 27#include "irqchip.h"
29 28
30static DEFINE_SPINLOCK(lock); 29/*
30 * struct spear_shirq: shared irq structure
31 *
32 * base: Base register address
33 * status_reg: Status register offset for chained interrupt handler
34 * mask_reg: Mask register offset for irq chip
35 * mask: Mask to apply to the status register
36 * virq_base: Base virtual interrupt number
37 * nr_irqs: Number of interrupts handled by this block
38 * offset: Bit offset of the first interrupt
39 * irq_chip: Interrupt controller chip used for this instance,
40 * if NULL group is disabled, but accounted
41 */
42struct spear_shirq {
43 void __iomem *base;
44 u32 status_reg;
45 u32 mask_reg;
46 u32 mask;
47 u32 virq_base;
48 u32 nr_irqs;
49 u32 offset;
50 struct irq_chip *irq_chip;
51};
31 52
32/* spear300 shared irq registers offsets and masks */ 53/* spear300 shared irq registers offsets and masks */
33#define SPEAR300_INT_ENB_MASK_REG 0x54 54#define SPEAR300_INT_ENB_MASK_REG 0x54
34#define SPEAR300_INT_STS_MASK_REG 0x58 55#define SPEAR300_INT_STS_MASK_REG 0x58
35 56
57static DEFINE_RAW_SPINLOCK(shirq_lock);
58
59static void shirq_irq_mask(struct irq_data *d)
60{
61 struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
62 u32 val, shift = d->irq - shirq->virq_base + shirq->offset;
63 u32 __iomem *reg = shirq->base + shirq->mask_reg;
64
65 raw_spin_lock(&shirq_lock);
66 val = readl(reg) & ~(0x1 << shift);
67 writel(val, reg);
68 raw_spin_unlock(&shirq_lock);
69}
70
71static void shirq_irq_unmask(struct irq_data *d)
72{
73 struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
74 u32 val, shift = d->irq - shirq->virq_base + shirq->offset;
75 u32 __iomem *reg = shirq->base + shirq->mask_reg;
76
77 raw_spin_lock(&shirq_lock);
78 val = readl(reg) | (0x1 << shift);
79 writel(val, reg);
80 raw_spin_unlock(&shirq_lock);
81}
82
83static struct irq_chip shirq_chip = {
84 .name = "spear-shirq",
85 .irq_mask = shirq_irq_mask,
86 .irq_unmask = shirq_irq_unmask,
87};
88
36static struct spear_shirq spear300_shirq_ras1 = { 89static struct spear_shirq spear300_shirq_ras1 = {
37 .irq_nr = 9, 90 .offset = 0,
38 .irq_bit_off = 0, 91 .nr_irqs = 9,
39 .regs = { 92 .mask = ((0x1 << 9) - 1) << 0,
40 .enb_reg = SPEAR300_INT_ENB_MASK_REG, 93 .irq_chip = &shirq_chip,
41 .status_reg = SPEAR300_INT_STS_MASK_REG, 94 .status_reg = SPEAR300_INT_STS_MASK_REG,
42 .clear_reg = -1, 95 .mask_reg = SPEAR300_INT_ENB_MASK_REG,
43 },
44}; 96};
45 97
46static struct spear_shirq *spear300_shirq_blocks[] = { 98static struct spear_shirq *spear300_shirq_blocks[] = {
@@ -51,43 +103,35 @@ static struct spear_shirq *spear300_shirq_blocks[] = {
51#define SPEAR310_INT_STS_MASK_REG 0x04 103#define SPEAR310_INT_STS_MASK_REG 0x04
52 104
53static struct spear_shirq spear310_shirq_ras1 = { 105static struct spear_shirq spear310_shirq_ras1 = {
54 .irq_nr = 8, 106 .offset = 0,
55 .irq_bit_off = 0, 107 .nr_irqs = 8,
56 .regs = { 108 .mask = ((0x1 << 8) - 1) << 0,
57 .enb_reg = -1, 109 .irq_chip = &dummy_irq_chip,
58 .status_reg = SPEAR310_INT_STS_MASK_REG, 110 .status_reg = SPEAR310_INT_STS_MASK_REG,
59 .clear_reg = -1,
60 },
61}; 111};
62 112
63static struct spear_shirq spear310_shirq_ras2 = { 113static struct spear_shirq spear310_shirq_ras2 = {
64 .irq_nr = 5, 114 .offset = 8,
65 .irq_bit_off = 8, 115 .nr_irqs = 5,
66 .regs = { 116 .mask = ((0x1 << 5) - 1) << 8,
67 .enb_reg = -1, 117 .irq_chip = &dummy_irq_chip,
68 .status_reg = SPEAR310_INT_STS_MASK_REG, 118 .status_reg = SPEAR310_INT_STS_MASK_REG,
69 .clear_reg = -1,
70 },
71}; 119};
72 120
73static struct spear_shirq spear310_shirq_ras3 = { 121static struct spear_shirq spear310_shirq_ras3 = {
74 .irq_nr = 1, 122 .offset = 13,
75 .irq_bit_off = 13, 123 .nr_irqs = 1,
76 .regs = { 124 .mask = ((0x1 << 1) - 1) << 13,
77 .enb_reg = -1, 125 .irq_chip = &dummy_irq_chip,
78 .status_reg = SPEAR310_INT_STS_MASK_REG, 126 .status_reg = SPEAR310_INT_STS_MASK_REG,
79 .clear_reg = -1,
80 },
81}; 127};
82 128
83static struct spear_shirq spear310_shirq_intrcomm_ras = { 129static struct spear_shirq spear310_shirq_intrcomm_ras = {
84 .irq_nr = 3, 130 .offset = 14,
85 .irq_bit_off = 14, 131 .nr_irqs = 3,
86 .regs = { 132 .mask = ((0x1 << 3) - 1) << 14,
87 .enb_reg = -1, 133 .irq_chip = &dummy_irq_chip,
88 .status_reg = SPEAR310_INT_STS_MASK_REG, 134 .status_reg = SPEAR310_INT_STS_MASK_REG,
89 .clear_reg = -1,
90 },
91}; 135};
92 136
93static struct spear_shirq *spear310_shirq_blocks[] = { 137static struct spear_shirq *spear310_shirq_blocks[] = {
@@ -102,50 +146,34 @@ static struct spear_shirq *spear310_shirq_blocks[] = {
102#define SPEAR320_INT_CLR_MASK_REG 0x04 146#define SPEAR320_INT_CLR_MASK_REG 0x04
103#define SPEAR320_INT_ENB_MASK_REG 0x08 147#define SPEAR320_INT_ENB_MASK_REG 0x08
104 148
105static struct spear_shirq spear320_shirq_ras1 = { 149static struct spear_shirq spear320_shirq_ras3 = {
106 .irq_nr = 3, 150 .offset = 0,
107 .irq_bit_off = 7, 151 .nr_irqs = 7,
108 .regs = { 152 .mask = ((0x1 << 7) - 1) << 0,
109 .enb_reg = -1,
110 .status_reg = SPEAR320_INT_STS_MASK_REG,
111 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
112 .reset_to_clear = 1,
113 },
114}; 153};
115 154
116static struct spear_shirq spear320_shirq_ras2 = { 155static struct spear_shirq spear320_shirq_ras1 = {
117 .irq_nr = 1, 156 .offset = 7,
118 .irq_bit_off = 10, 157 .nr_irqs = 3,
119 .regs = { 158 .mask = ((0x1 << 3) - 1) << 7,
120 .enb_reg = -1, 159 .irq_chip = &dummy_irq_chip,
121 .status_reg = SPEAR320_INT_STS_MASK_REG, 160 .status_reg = SPEAR320_INT_STS_MASK_REG,
122 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
123 .reset_to_clear = 1,
124 },
125}; 161};
126 162
127static struct spear_shirq spear320_shirq_ras3 = { 163static struct spear_shirq spear320_shirq_ras2 = {
128 .irq_nr = 7, 164 .offset = 10,
129 .irq_bit_off = 0, 165 .nr_irqs = 1,
130 .invalid_irq = 1, 166 .mask = ((0x1 << 1) - 1) << 10,
131 .regs = { 167 .irq_chip = &dummy_irq_chip,
132 .enb_reg = SPEAR320_INT_ENB_MASK_REG, 168 .status_reg = SPEAR320_INT_STS_MASK_REG,
133 .reset_to_enb = 1,
134 .status_reg = SPEAR320_INT_STS_MASK_REG,
135 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
136 .reset_to_clear = 1,
137 },
138}; 169};
139 170
140static struct spear_shirq spear320_shirq_intrcomm_ras = { 171static struct spear_shirq spear320_shirq_intrcomm_ras = {
141 .irq_nr = 11, 172 .offset = 11,
142 .irq_bit_off = 11, 173 .nr_irqs = 11,
143 .regs = { 174 .mask = ((0x1 << 11) - 1) << 11,
144 .enb_reg = -1, 175 .irq_chip = &dummy_irq_chip,
145 .status_reg = SPEAR320_INT_STS_MASK_REG, 176 .status_reg = SPEAR320_INT_STS_MASK_REG,
146 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
147 .reset_to_clear = 1,
148 },
149}; 177};
150 178
151static struct spear_shirq *spear320_shirq_blocks[] = { 179static struct spear_shirq *spear320_shirq_blocks[] = {
@@ -155,104 +183,46 @@ static struct spear_shirq *spear320_shirq_blocks[] = {
155 &spear320_shirq_intrcomm_ras, 183 &spear320_shirq_intrcomm_ras,
156}; 184};
157 185
158static void shirq_irq_mask_unmask(struct irq_data *d, bool mask)
159{
160 struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
161 u32 val, offset = d->irq - shirq->irq_base;
162 unsigned long flags;
163
164 if (shirq->regs.enb_reg == -1)
165 return;
166
167 spin_lock_irqsave(&lock, flags);
168 val = readl(shirq->base + shirq->regs.enb_reg);
169
170 if (mask ^ shirq->regs.reset_to_enb)
171 val &= ~(0x1 << shirq->irq_bit_off << offset);
172 else
173 val |= 0x1 << shirq->irq_bit_off << offset;
174
175 writel(val, shirq->base + shirq->regs.enb_reg);
176 spin_unlock_irqrestore(&lock, flags);
177
178}
179
180static void shirq_irq_mask(struct irq_data *d)
181{
182 shirq_irq_mask_unmask(d, 1);
183}
184
185static void shirq_irq_unmask(struct irq_data *d)
186{
187 shirq_irq_mask_unmask(d, 0);
188}
189
190static struct irq_chip shirq_chip = {
191 .name = "spear-shirq",
192 .irq_ack = shirq_irq_mask,
193 .irq_mask = shirq_irq_mask,
194 .irq_unmask = shirq_irq_unmask,
195};
196
197static void shirq_handler(unsigned irq, struct irq_desc *desc) 186static void shirq_handler(unsigned irq, struct irq_desc *desc)
198{ 187{
199 u32 i, j, val, mask, tmp;
200 struct irq_chip *chip;
201 struct spear_shirq *shirq = irq_get_handler_data(irq); 188 struct spear_shirq *shirq = irq_get_handler_data(irq);
189 u32 pend;
202 190
203 chip = irq_get_chip(irq); 191 pend = readl(shirq->base + shirq->status_reg) & shirq->mask;
204 chip->irq_ack(&desc->irq_data); 192 pend >>= shirq->offset;
205
206 mask = ((0x1 << shirq->irq_nr) - 1) << shirq->irq_bit_off;
207 while ((val = readl(shirq->base + shirq->regs.status_reg) &
208 mask)) {
209
210 val >>= shirq->irq_bit_off;
211 for (i = 0, j = 1; i < shirq->irq_nr; i++, j <<= 1) {
212
213 if (!(j & val))
214 continue;
215 193
216 generic_handle_irq(shirq->irq_base + i); 194 while (pend) {
195 int irq = __ffs(pend);
217 196
218 /* clear interrupt */ 197 pend &= ~(0x1 << irq);
219 if (shirq->regs.clear_reg == -1) 198 generic_handle_irq(shirq->virq_base + irq);
220 continue;
221
222 tmp = readl(shirq->base + shirq->regs.clear_reg);
223 if (shirq->regs.reset_to_clear)
224 tmp &= ~(j << shirq->irq_bit_off);
225 else
226 tmp |= (j << shirq->irq_bit_off);
227 writel(tmp, shirq->base + shirq->regs.clear_reg);
228 }
229 } 199 }
230 chip->irq_unmask(&desc->irq_data);
231} 200}
232 201
233static void __init spear_shirq_register(struct spear_shirq *shirq) 202static void __init spear_shirq_register(struct spear_shirq *shirq,
203 int parent_irq)
234{ 204{
235 int i; 205 int i;
236 206
237 if (shirq->invalid_irq) 207 if (!shirq->irq_chip)
238 return; 208 return;
239 209
240 irq_set_chained_handler(shirq->irq, shirq_handler); 210 irq_set_chained_handler(parent_irq, shirq_handler);
241 for (i = 0; i < shirq->irq_nr; i++) { 211 irq_set_handler_data(parent_irq, shirq);
242 irq_set_chip_and_handler(shirq->irq_base + i,
243 &shirq_chip, handle_simple_irq);
244 set_irq_flags(shirq->irq_base + i, IRQF_VALID);
245 irq_set_chip_data(shirq->irq_base + i, shirq);
246 }
247 212
248 irq_set_handler_data(shirq->irq, shirq); 213 for (i = 0; i < shirq->nr_irqs; i++) {
214 irq_set_chip_and_handler(shirq->virq_base + i,
215 shirq->irq_chip, handle_simple_irq);
216 set_irq_flags(shirq->virq_base + i, IRQF_VALID);
217 irq_set_chip_data(shirq->virq_base + i, shirq);
218 }
249} 219}
250 220
251static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr, 221static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
252 struct device_node *np) 222 struct device_node *np)
253{ 223{
254 int i, irq_base, hwirq = 0, irq_nr = 0; 224 int i, parent_irq, virq_base, hwirq = 0, nr_irqs = 0;
255 static struct irq_domain *shirq_domain; 225 struct irq_domain *shirq_domain;
256 void __iomem *base; 226 void __iomem *base;
257 227
258 base = of_iomap(np, 0); 228 base = of_iomap(np, 0);
@@ -262,15 +232,15 @@ static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
262 } 232 }
263 233
264 for (i = 0; i < block_nr; i++) 234 for (i = 0; i < block_nr; i++)
265 irq_nr += shirq_blocks[i]->irq_nr; 235 nr_irqs += shirq_blocks[i]->nr_irqs;
266 236
267 irq_base = irq_alloc_descs(-1, 0, irq_nr, 0); 237 virq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
268 if (IS_ERR_VALUE(irq_base)) { 238 if (IS_ERR_VALUE(virq_base)) {
269 pr_err("%s: irq desc alloc failed\n", __func__); 239 pr_err("%s: irq desc alloc failed\n", __func__);
270 goto err_unmap; 240 goto err_unmap;
271 } 241 }
272 242
273 shirq_domain = irq_domain_add_legacy(np, irq_nr, irq_base, 0, 243 shirq_domain = irq_domain_add_legacy(np, nr_irqs, virq_base, 0,
274 &irq_domain_simple_ops, NULL); 244 &irq_domain_simple_ops, NULL);
275 if (WARN_ON(!shirq_domain)) { 245 if (WARN_ON(!shirq_domain)) {
276 pr_warn("%s: irq domain init failed\n", __func__); 246 pr_warn("%s: irq domain init failed\n", __func__);
@@ -279,41 +249,41 @@ static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
279 249
280 for (i = 0; i < block_nr; i++) { 250 for (i = 0; i < block_nr; i++) {
281 shirq_blocks[i]->base = base; 251 shirq_blocks[i]->base = base;
282 shirq_blocks[i]->irq_base = irq_find_mapping(shirq_domain, 252 shirq_blocks[i]->virq_base = irq_find_mapping(shirq_domain,
283 hwirq); 253 hwirq);
284 shirq_blocks[i]->irq = irq_of_parse_and_map(np, i);
285 254
286 spear_shirq_register(shirq_blocks[i]); 255 parent_irq = irq_of_parse_and_map(np, i);
287 hwirq += shirq_blocks[i]->irq_nr; 256 spear_shirq_register(shirq_blocks[i], parent_irq);
257 hwirq += shirq_blocks[i]->nr_irqs;
288 } 258 }
289 259
290 return 0; 260 return 0;
291 261
292err_free_desc: 262err_free_desc:
293 irq_free_descs(irq_base, irq_nr); 263 irq_free_descs(virq_base, nr_irqs);
294err_unmap: 264err_unmap:
295 iounmap(base); 265 iounmap(base);
296 return -ENXIO; 266 return -ENXIO;
297} 267}
298 268
299int __init spear300_shirq_of_init(struct device_node *np, 269static int __init spear300_shirq_of_init(struct device_node *np,
300 struct device_node *parent) 270 struct device_node *parent)
301{ 271{
302 return shirq_init(spear300_shirq_blocks, 272 return shirq_init(spear300_shirq_blocks,
303 ARRAY_SIZE(spear300_shirq_blocks), np); 273 ARRAY_SIZE(spear300_shirq_blocks), np);
304} 274}
305IRQCHIP_DECLARE(spear300_shirq, "st,spear300-shirq", spear300_shirq_of_init); 275IRQCHIP_DECLARE(spear300_shirq, "st,spear300-shirq", spear300_shirq_of_init);
306 276
307int __init spear310_shirq_of_init(struct device_node *np, 277static int __init spear310_shirq_of_init(struct device_node *np,
308 struct device_node *parent) 278 struct device_node *parent)
309{ 279{
310 return shirq_init(spear310_shirq_blocks, 280 return shirq_init(spear310_shirq_blocks,
311 ARRAY_SIZE(spear310_shirq_blocks), np); 281 ARRAY_SIZE(spear310_shirq_blocks), np);
312} 282}
313IRQCHIP_DECLARE(spear310_shirq, "st,spear310-shirq", spear310_shirq_of_init); 283IRQCHIP_DECLARE(spear310_shirq, "st,spear310-shirq", spear310_shirq_of_init);
314 284
315int __init spear320_shirq_of_init(struct device_node *np, 285static int __init spear320_shirq_of_init(struct device_node *np,
316 struct device_node *parent) 286 struct device_node *parent)
317{ 287{
318 return shirq_init(spear320_shirq_blocks, 288 return shirq_init(spear320_shirq_blocks,
319 ARRAY_SIZE(spear320_shirq_blocks), np); 289 ARRAY_SIZE(spear320_shirq_blocks), np);
diff --git a/include/linux/irqchip/spear-shirq.h b/include/linux/irqchip/spear-shirq.h
deleted file mode 100644
index c8be16d213a3..000000000000
--- a/include/linux/irqchip/spear-shirq.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * SPEAr platform shared irq layer header file
3 *
4 * Copyright (C) 2009-2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#ifndef __SPEAR_SHIRQ_H
13#define __SPEAR_SHIRQ_H
14
15#include <linux/irq.h>
16#include <linux/types.h>
17
18/*
19 * struct shirq_regs: shared irq register configuration
20 *
21 * enb_reg: enable register offset
22 * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt
23 * status_reg: status register offset
24 * status_reg_mask: status register valid mask
25 * clear_reg: clear register offset
26 * reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt
27 */
28struct shirq_regs {
29 u32 enb_reg;
30 u32 reset_to_enb;
31 u32 status_reg;
32 u32 clear_reg;
33 u32 reset_to_clear;
34};
35
36/*
37 * struct spear_shirq: shared irq structure
38 *
39 * irq: hardware irq number
40 * irq_base: base irq in linux domain
41 * irq_nr: no. of shared interrupts in a particular block
42 * irq_bit_off: starting bit offset in the status register
43 * invalid_irq: irq group is currently disabled
44 * base: base address of shared irq register
45 * regs: register configuration for shared irq block
46 */
47struct spear_shirq {
48 u32 irq;
49 u32 irq_base;
50 u32 irq_nr;
51 u32 irq_bit_off;
52 int invalid_irq;
53 void __iomem *base;
54 struct shirq_regs regs;
55};
56
57int __init spear300_shirq_of_init(struct device_node *np,
58 struct device_node *parent);
59int __init spear310_shirq_of_init(struct device_node *np,
60 struct device_node *parent);
61int __init spear320_shirq_of_init(struct device_node *np,
62 struct device_node *parent);
63
64#endif /* __SPEAR_SHIRQ_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-28 00:05:03 -0500