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-rw-r--r--Documentation/ABI/testing/sysfs-class-cxl7
-rw-r--r--Documentation/arm/stm32/overview.txt3
-rw-r--r--Documentation/arm/stm32/stm32f746-overview.txt34
-rw-r--r--Documentation/devicetree/bindings/arm/omap/omap.txt6
-rw-r--r--Documentation/devicetree/bindings/arm/shmobile.txt14
-rw-r--r--Documentation/devicetree/bindings/ipmi/aspeed,ast2400-bt-bmc.txt23
-rw-r--r--Documentation/devicetree/bindings/ipmi/ipmi-smic.txt (renamed from Documentation/devicetree/bindings/ipmi.txt)0
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt4
-rw-r--r--Documentation/devicetree/bindings/timer/jcore,pit.txt24
-rw-r--r--Documentation/filesystems/proc.txt26
-rw-r--r--MAINTAINERS7
-rw-r--r--Makefile2
-rw-r--r--arch/alpha/kernel/ptrace.c9
-rw-r--r--arch/arm/Kconfig5
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/kvm/arm.c7
-rw-r--r--arch/arm/mach-artpec/Kconfig1
-rw-r--r--arch/arm/mach-davinci/board-da830-evm.c54
-rw-r--r--arch/arm/mach-davinci/board-da850-evm.c4
-rw-r--r--arch/arm/mach-davinci/board-mityomapl138.c4
-rw-r--r--arch/arm/mach-davinci/board-omapl138-hawk.c26
-rw-r--r--arch/arm/mach-davinci/da830.c4
-rw-r--r--arch/arm/mach-davinci/da850.c4
-rw-r--r--arch/arm/mach-davinci/da8xx-dt.c15
-rw-r--r--arch/arm/mach-davinci/devices-da8xx.c57
-rw-r--r--arch/arm/mach-davinci/devices.c3
-rw-r--r--arch/arm/mach-davinci/dm355.c8
-rw-r--r--arch/arm/mach-davinci/dm365.c8
-rw-r--r--arch/arm/mach-davinci/include/mach/da8xx.h6
-rw-r--r--arch/arm/mach-davinci/usb-da8xx.c276
-rw-r--r--arch/arm/mach-imx/Kconfig1
-rw-r--r--arch/arm/mach-imx/mach-imx6ul.c1
-rw-r--r--arch/arm/mach-imx/mmdc.c495
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c54
-rw-r--r--arch/arm/mach-lpc32xx/clock.h38
-rw-r--r--arch/arm/mach-lpc32xx/common.h1
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/irqs.h117
-rw-r--r--arch/arm/mach-lpc32xx/pm.c1
-rw-r--r--arch/arm/mach-mediatek/Makefile6
-rw-r--r--arch/arm/mach-omap1/Kconfig26
-rw-r--r--arch/arm/mach-omap1/i2c.c83
-rw-r--r--arch/arm/mach-omap2/Makefile18
-rw-r--r--arch/arm/mach-omap2/board-flash.c242
-rw-r--r--arch/arm/mach-omap2/board-flash.h56
-rw-r--r--arch/arm/mach-omap2/board-generic.c1
-rw-r--r--arch/arm/mach-omap2/clockdomains7xx_data.c2
-rw-r--r--arch/arm/mach-omap2/common-board-devices.c102
-rw-r--r--arch/arm/mach-omap2/common-board-devices.h8
-rw-r--r--arch/arm/mach-omap2/common.h47
-rw-r--r--arch/arm/mach-omap2/cpuidle44xx.c80
-rw-r--r--arch/arm/mach-omap2/devices.c1
-rw-r--r--arch/arm/mach-omap2/dss-common.c37
-rw-r--r--arch/arm/mach-omap2/dss-common.h13
-rw-r--r--arch/arm/mach-omap2/gpmc-smsc911x.c100
-rw-r--r--arch/arm/mach-omap2/gpmc-smsc911x.h35
-rw-r--r--arch/arm/mach-omap2/hsmmc.c88
-rw-r--r--arch/arm/mach-omap2/i2c.c97
-rw-r--r--arch/arm/mach-omap2/io.c4
-rw-r--r--arch/arm/mach-omap2/msdi.c1
-rw-r--r--arch/arm/mach-omap2/mux.c1153
-rw-r--r--arch/arm/mach-omap2/mux.h352
-rw-r--r--arch/arm/mach-omap2/mux34xx.c2061
-rw-r--r--arch/arm/mach-omap2/mux34xx.h402
-rw-r--r--arch/arm/mach-omap2/omap-mpuss-lowpower.c37
-rw-r--r--arch/arm/mach-omap2/omap4-sar-layout.h2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c107
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c149
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c201
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c4
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c8
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c29
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_data.c35
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c787
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_43xx_data.c34
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c182
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.h15
-rw-r--r--arch/arm/mach-omap2/pdata-quirks.c1
-rw-r--r--arch/arm/mach-omap2/pm.c66
-rw-r--r--arch/arm/mach-omap2/pm44xx.c2
-rw-r--r--arch/arm/mach-omap2/prcm43xx.h2
-rw-r--r--arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h51
-rw-r--r--arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h55
-rw-r--r--arch/arm/mach-omap2/sdram-nokia.c299
-rw-r--r--arch/arm/mach-omap2/sdram-nokia.h12
-rw-r--r--arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h51
-rw-r--r--arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h54
-rw-r--r--arch/arm/mach-omap2/serial.c332
-rw-r--r--arch/arm/mach-omap2/twl-common.c564
-rw-r--r--arch/arm/mach-omap2/twl-common.h66
-rw-r--r--arch/arm/mach-omap2/usb-host.c496
-rw-r--r--arch/arm/mach-omap2/usb-musb.c106
-rw-r--r--arch/arm/mach-omap2/usb-tusb6010.c21
-rw-r--r--arch/arm/mach-oxnas/Kconfig30
-rw-r--r--arch/arm/mach-oxnas/Makefile2
-rw-r--r--arch/arm/mach-oxnas/headsmp.S26
-rw-r--r--arch/arm/mach-oxnas/hotplug.c109
-rw-r--r--arch/arm/mach-oxnas/platsmp.c102
-rw-r--r--arch/arm/mach-pxa/corgi.c1
-rw-r--r--arch/arm/mach-pxa/em-x270.c89
-rw-r--r--arch/arm/mach-pxa/ezx.c176
-rw-r--r--arch/arm/mach-pxa/generic.c18
-rw-r--r--arch/arm/mach-pxa/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-pxa/mioa701.c13
-rw-r--r--arch/arm/mach-pxa/pxa25x.c2
-rw-r--r--arch/arm/mach-pxa/pxa_cplds_irqs.c11
-rw-r--r--arch/arm/mach-pxa/spitz.c1
-rw-r--r--arch/arm/mach-sa1100/generic.c2
-rw-r--r--arch/arm/mach-sa1100/include/mach/hardware.h4
-rw-r--r--arch/arm/mach-shmobile/Kconfig20
-rw-r--r--arch/arm/mach-shmobile/Makefile3
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7792.c35
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7793.c33
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7794.c33
-rw-r--r--arch/arm/mach-shmobile/setup-rcar-gen2.c45
-rw-r--r--arch/arm/mach-stm32/board-dt.c1
-rw-r--r--arch/arm/mach-vexpress/platsmp.c34
-rw-r--r--arch/arm/plat-omap/Kconfig26
-rw-r--r--arch/arm/plat-omap/Makefile3
-rw-r--r--arch/arm/plat-omap/i2c.c116
-rw-r--r--arch/arm/plat-orion/gpio.c6
-rw-r--r--arch/arm64/Kconfig2
-rw-r--r--arch/arm64/Makefile2
-rw-r--r--arch/arm64/include/asm/cpufeature.h2
-rw-r--r--arch/arm64/include/asm/exec.h3
-rw-r--r--arch/arm64/include/asm/kvm_emulate.h11
-rw-r--r--arch/arm64/include/asm/module.h5
-rw-r--r--arch/arm64/include/asm/percpu.h120
-rw-r--r--arch/arm64/include/asm/processor.h6
-rw-r--r--arch/arm64/include/asm/sysreg.h2
-rw-r--r--arch/arm64/include/asm/uaccess.h8
-rw-r--r--arch/arm64/kernel/armv8_deprecated.c36
-rw-r--r--arch/arm64/kernel/cpu_errata.c3
-rw-r--r--arch/arm64/kernel/cpufeature.c10
-rw-r--r--arch/arm64/kernel/head.S3
-rw-r--r--arch/arm64/kernel/process.c18
-rw-r--r--arch/arm64/kernel/sleep.S2
-rw-r--r--arch/arm64/kernel/smp.c1
-rw-r--r--arch/arm64/kernel/suspend.c11
-rw-r--r--arch/arm64/kernel/traps.c30
-rw-r--r--arch/arm64/mm/fault.c15
-rw-r--r--arch/arm64/mm/init.c26
-rw-r--r--arch/blackfin/kernel/ptrace.c5
-rw-r--r--arch/cris/arch-v32/drivers/cryptocop.c4
-rw-r--r--arch/cris/arch-v32/kernel/ptrace.c4
-rw-r--r--arch/ia64/kernel/err_inject.c2
-rw-r--r--arch/ia64/kernel/ptrace.c14
-rw-r--r--arch/m32r/kernel/ptrace.c15
-rw-r--r--arch/mips/kernel/ptrace32.c5
-rw-r--r--arch/mips/kvm/mips.c1
-rw-r--r--arch/mips/mm/gup.c2
-rw-r--r--arch/powerpc/boot/main.c18
-rw-r--r--arch/powerpc/include/asm/unistd.h4
-rw-r--r--arch/powerpc/kernel/ptrace32.c5
-rw-r--r--arch/powerpc/mm/copro_fault.c2
-rw-r--r--arch/powerpc/mm/numa.c46
-rw-r--r--arch/s390/kvm/intercept.c9
-rw-r--r--arch/s390/mm/gup.c3
-rw-r--r--arch/score/kernel/ptrace.c10
-rw-r--r--arch/sh/Makefile2
-rw-r--r--arch/sh/boards/Kconfig10
-rw-r--r--arch/sh/configs/j2_defconfig2
-rw-r--r--arch/sh/mm/gup.c3
-rw-r--r--arch/sparc/kernel/ptrace_64.c24
-rw-r--r--arch/sparc/mm/gup.c3
-rw-r--r--arch/x86/entry/syscalls/syscall_32.tbl2
-rw-r--r--arch/x86/entry/syscalls/syscall_64.tbl2
-rw-r--r--arch/x86/events/intel/core.c3
-rw-r--r--arch/x86/events/intel/lbr.c4
-rw-r--r--arch/x86/events/intel/rapl.c1
-rw-r--r--arch/x86/events/intel/uncore.c1
-rw-r--r--arch/x86/include/asm/cpufeatures.h2
-rw-r--r--arch/x86/include/asm/intel-family.h1
-rw-r--r--arch/x86/include/asm/msr-index.h1
-rw-r--r--arch/x86/include/asm/rwsem.h6
-rw-r--r--arch/x86/include/asm/thread_info.h9
-rw-r--r--arch/x86/kernel/cpu/scattered.c2
-rw-r--r--arch/x86/kernel/cpu/vmware.c5
-rw-r--r--arch/x86/kernel/e820.c2
-rw-r--r--arch/x86/kernel/fpu/xstate.c2
-rw-r--r--arch/x86/kernel/kprobes/core.c11
-rw-r--r--arch/x86/kernel/signal_compat.c3
-rw-r--r--arch/x86/kernel/smp.c2
-rw-r--r--arch/x86/kernel/smpboot.c16
-rw-r--r--arch/x86/kernel/step.c3
-rw-r--r--arch/x86/kvm/ioapic.c2
-rw-r--r--arch/x86/kvm/x86.c4
-rw-r--r--arch/x86/mm/gup.c2
-rw-r--r--arch/x86/mm/mpx.c5
-rw-r--r--arch/x86/platform/uv/bios_uv.c10
-rw-r--r--arch/x86/um/ptrace_32.c3
-rw-r--r--arch/x86/um/ptrace_64.c3
-rw-r--r--block/badblocks.c6
-rw-r--r--drivers/Makefile2
-rw-r--r--drivers/block/rbd.c50
-rw-r--r--drivers/bus/arm-cci.c10
-rw-r--r--drivers/char/ipmi/Kconfig8
-rw-r--r--drivers/char/ipmi/Makefile1
-rw-r--r--drivers/char/ipmi/bt-bmc.c505
-rw-r--r--drivers/char/ipmi/ipmi_msghandler.c7
-rw-r--r--drivers/clk/pxa/clk-pxa25x.c2
-rw-r--r--drivers/clocksource/Kconfig10
-rw-r--r--drivers/clocksource/Makefile1
-rw-r--r--drivers/clocksource/jcore-pit.c249
-rw-r--r--drivers/clocksource/pxa_timer.c11
-rw-r--r--drivers/clocksource/timer-sun5i.c16
-rw-r--r--drivers/firewire/nosy.c13
-rw-r--r--drivers/firmware/efi/libstub/Makefile5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c13
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c69
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c14
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_dpm.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v10_0.c12
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c30
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c13
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c14
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si_dpm.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/tonga_ih.c14
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c14
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v3_0.c15
-rw-r--r--drivers/gpu/drm/amd/include/amd_shared.h2
-rw-r--r--drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c1
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c18
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c53
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c2
-rw-r--r--drivers/gpu/drm/armada/armada_crtc.c18
-rw-r--r--drivers/gpu/drm/drm_info.c4
-rw-r--r--drivers/gpu/drm/etnaviv/etnaviv_buffer.c24
-rw-r--r--drivers/gpu/drm/etnaviv/etnaviv_gem.c7
-rw-r--r--drivers/gpu/drm/etnaviv/etnaviv_mmu.c3
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_g2d.c3
-rw-r--r--drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c4
-rw-r--r--drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c23
-rw-r--r--drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c5
-rw-r--r--drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c39
-rw-r--r--drivers/gpu/drm/i915/i915_gem_userptr.c6
-rw-r--r--drivers/gpu/drm/radeon/r600_dpm.c15
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c17
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c14
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_i2c.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_ttm.c3
-rw-r--r--drivers/gpu/drm/radeon/si.c1
-rw-r--r--drivers/gpu/drm/radeon/sid.h1
-rw-r--r--drivers/gpu/drm/via/via_dmablit.c4
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.c10
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.h2
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c145
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_resource.c6
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_surface.c56
-rw-r--r--drivers/hid/hid-dr.c83
-rw-r--r--drivers/hid/hid-ids.h3
-rw-r--r--drivers/hid/hid-led.c23
-rw-r--r--drivers/hid/usbhid/hid-quirks.c1
-rw-r--r--drivers/hwmon/adm9240.c6
-rw-r--r--drivers/hwmon/max31790.c4
-rw-r--r--drivers/infiniband/core/umem.c6
-rw-r--r--drivers/infiniband/core/umem_odp.c7
-rw-r--r--drivers/infiniband/hw/mthca/mthca_memfree.c2
-rw-r--r--drivers/infiniband/hw/qib/qib_user_pages.c3
-rw-r--r--drivers/infiniband/hw/usnic/usnic_uiom.c5
-rw-r--r--drivers/irqchip/Kconfig4
-rw-r--r--drivers/irqchip/irq-eznps.c6
-rw-r--r--drivers/irqchip/irq-gic-v3-its.c10
-rw-r--r--drivers/irqchip/irq-gic-v3.c2
-rw-r--r--drivers/irqchip/irq-gic.c2
-rw-r--r--drivers/irqchip/irq-jcore-aic.c20
-rw-r--r--drivers/media/pci/ivtv/ivtv-udma.c4
-rw-r--r--drivers/media/pci/ivtv/ivtv-yuv.c5
-rw-r--r--drivers/media/platform/omap/omap_vout.c2
-rw-r--r--drivers/media/v4l2-core/videobuf-dma-sg.c7
-rw-r--r--drivers/media/v4l2-core/videobuf2-memops.c6
-rw-r--r--drivers/memstick/host/rtsx_usb_ms.c6
-rw-r--r--drivers/misc/cxl/api.c9
-rw-r--r--drivers/misc/cxl/context.c3
-rw-r--r--drivers/misc/cxl/cxl.h24
-rw-r--r--drivers/misc/cxl/file.c11
-rw-r--r--drivers/misc/cxl/guest.c3
-rw-r--r--drivers/misc/cxl/main.c42
-rw-r--r--drivers/misc/cxl/pci.c2
-rw-r--r--drivers/misc/cxl/sysfs.c27
-rw-r--r--drivers/misc/mic/scif/scif_rma.c3
-rw-r--r--drivers/misc/sgi-gru/grufault.c2
-rw-r--r--drivers/mmc/card/block.c3
-rw-r--r--drivers/mmc/card/queue.h2
-rw-r--r--drivers/mmc/core/mmc.c12
-rw-r--r--drivers/mmc/host/rtsx_usb_sdmmc.c7
-rw-r--r--drivers/mmc/host/sdhci-esdhc-imx.c23
-rw-r--r--drivers/mmc/host/sdhci-of-arasan.c26
-rw-r--r--drivers/mmc/host/sdhci-pci-core.c54
-rw-r--r--drivers/mmc/host/sdhci-pci.h2
-rw-r--r--drivers/mmc/host/sdhci-pxav3.c2
-rw-r--r--drivers/mmc/host/sdhci.c42
-rw-r--r--drivers/mmc/host/sdhci.h2
-rw-r--r--drivers/mtd/ubi/eba.c1
-rw-r--r--drivers/mtd/ubi/fastmap.c2
-rw-r--r--drivers/nvme/host/core.c14
-rw-r--r--drivers/nvme/host/pci.c77
-rw-r--r--drivers/nvme/host/scsi.c4
-rw-r--r--drivers/nvme/target/admin-cmd.c8
-rw-r--r--drivers/nvme/target/core.c2
-rw-r--r--drivers/nvme/target/discovery.c4
-rw-r--r--drivers/pci/host/pci-layerscape.c2
-rw-r--r--drivers/pci/host/pcie-designware-plat.c2
-rw-r--r--drivers/perf/xgene_pmu.c2
-rw-r--r--drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c100
-rw-r--r--drivers/pinctrl/aspeed/pinctrl-aspeed.c12
-rw-r--r--drivers/pinctrl/intel/pinctrl-baytrail.c3
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.c25
-rw-r--r--drivers/platform/goldfish/goldfish_pipe.c3
-rw-r--r--drivers/platform/x86/Kconfig1
-rw-r--r--drivers/platform/x86/ideapad-laptop.c7
-rw-r--r--drivers/rapidio/devices/rio_mport_cdev.c3
-rw-r--r--drivers/s390/scsi/zfcp_dbf.c2
-rw-r--r--drivers/scsi/ipr.c3
-rw-r--r--drivers/scsi/scsi_dh.c6
-rw-r--r--drivers/scsi/scsi_scan.c6
-rw-r--r--drivers/scsi/st.c5
-rw-r--r--drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c3
-rw-r--r--drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c3
-rw-r--r--drivers/target/iscsi/iscsi_target.c6
-rw-r--r--drivers/target/iscsi/iscsi_target_login.c4
-rw-r--r--drivers/target/target_core_transport.c39
-rw-r--r--drivers/target/target_core_user.c50
-rw-r--r--drivers/target/target_core_xcopy.c34
-rw-r--r--drivers/target/tcm_fc/tfc_cmd.c4
-rw-r--r--drivers/target/tcm_fc/tfc_sess.c42
-rw-r--r--drivers/video/fbdev/pvr2fb.c4
-rw-r--r--drivers/virt/fsl_hypervisor.c4
-rw-r--r--drivers/watchdog/sa1100_wdt.c24
-rw-r--r--drivers/watchdog/wdat_wdt.c4
-rw-r--r--fs/btrfs/compression.c4
-rw-r--r--fs/ceph/file.c3
-rw-r--r--fs/ceph/inode.c3
-rw-r--r--fs/ceph/super.c2
-rw-r--r--fs/ceph/xattr.c4
-rw-r--r--fs/crypto/crypto.c15
-rw-r--r--fs/crypto/policy.c4
-rw-r--r--fs/exec.c9
-rw-r--r--fs/ext2/inode.c7
-rw-r--r--fs/ext4/block_validity.c4
-rw-r--r--fs/ext4/mballoc.h17
-rw-r--r--fs/ext4/namei.c18
-rw-r--r--fs/ext4/super.c21
-rw-r--r--fs/ext4/sysfs.c4
-rw-r--r--fs/ext4/xattr.c20
-rw-r--r--fs/f2fs/gc.c10
-rw-r--r--fs/isofs/inode.c8
-rw-r--r--fs/jbd2/transaction.c3
-rw-r--r--fs/locks.c6
-rw-r--r--fs/nfs/blocklayout/blocklayout.c3
-rw-r--r--fs/nfs/nfs4proc.c2
-rw-r--r--fs/proc/array.c9
-rw-r--r--fs/proc/base.c19
-rw-r--r--fs/proc/task_mmu.c29
-rw-r--r--fs/proc/task_nommu.c28
-rw-r--r--fs/ubifs/dir.c20
-rw-r--r--fs/ubifs/xattr.c2
-rw-r--r--include/acpi/pcc.h2
-rw-r--r--include/clocksource/pxa.h3
-rw-r--r--include/linux/cpufreq.h4
-rw-r--r--include/linux/cpuhotplug.h1
-rw-r--r--include/linux/irqchip/arm-gic-v3.h2
-rw-r--r--include/linux/kasan.h2
-rw-r--r--include/linux/mm.h21
-rw-r--r--include/linux/nvme.h49
-rw-r--r--include/linux/platform_data/usb-davinci.h23
-rw-r--r--include/linux/syscalls.h3
-rw-r--r--include/linux/thread_info.h11
-rw-r--r--include/target/target_core_base.h1
-rw-r--r--include/uapi/asm-generic/unistd.h4
-rw-r--r--include/uapi/linux/Kbuild1
-rw-r--r--include/uapi/linux/bt-bmc.h18
-rw-r--r--kernel/cpu.c2
-rw-r--r--kernel/events/uprobes.c6
-rw-r--r--kernel/irq/manage.c1
-rw-r--r--kernel/printk/printk.c4
-rw-r--r--kernel/ptrace.c16
-rw-r--r--kernel/sched/fair.c20
-rw-r--r--kernel/time/alarmtimer.c2
-rw-r--r--mm/frame_vector.c9
-rw-r--r--mm/gup.c64
-rw-r--r--mm/kasan/kasan.c22
-rw-r--r--mm/memory.c16
-rw-r--r--mm/mempolicy.c2
-rw-r--r--mm/mprotect.c1
-rw-r--r--mm/nommu.c38
-rw-r--r--mm/process_vm_access.c7
-rw-r--r--mm/util.c12
-rw-r--r--net/ceph/pagevec.c2
-rw-r--r--security/selinux/hooks.c2
-rw-r--r--security/tomoyo/domain.c2
-rw-r--r--tools/arch/x86/include/asm/cpufeatures.h2
-rw-r--r--tools/objtool/arch/x86/decode.c9
-rw-r--r--tools/objtool/builtin-check.c68
-rw-r--r--tools/perf/jvmti/Makefile2
-rw-r--r--tools/perf/ui/browsers/hists.c3
-rw-r--r--tools/perf/util/header.c2
-rw-r--r--tools/perf/util/parse-events.l4
-rw-r--r--virt/kvm/async_pf.c3
-rw-r--r--virt/kvm/kvm_main.c11
405 files changed, 4865 insertions, 10238 deletions
diff --git a/Documentation/ABI/testing/sysfs-class-cxl b/Documentation/ABI/testing/sysfs-class-cxl
index 4ba0a2a61926..640f65e79ef1 100644
--- a/Documentation/ABI/testing/sysfs-class-cxl
+++ b/Documentation/ABI/testing/sysfs-class-cxl
@@ -220,8 +220,11 @@ What: /sys/class/cxl/<card>/reset
220Date: October 2014 220Date: October 2014
221Contact: linuxppc-dev@lists.ozlabs.org 221Contact: linuxppc-dev@lists.ozlabs.org
222Description: write only 222Description: write only
223 Writing 1 will issue a PERST to card which may cause the card 223 Writing 1 will issue a PERST to card provided there are no
224 to reload the FPGA depending on load_image_on_perst. 224 contexts active on any one of the card AFUs. This may cause
225 the card to reload the FPGA depending on load_image_on_perst.
226 Writing -1 will do a force PERST irrespective of any active
227 contexts on the card AFUs.
225Users: https://github.com/ibm-capi/libcxl 228Users: https://github.com/ibm-capi/libcxl
226 229
227What: /sys/class/cxl/<card>/perst_reloads_same_image (not in a guest) 230What: /sys/class/cxl/<card>/perst_reloads_same_image (not in a guest)
diff --git a/Documentation/arm/stm32/overview.txt b/Documentation/arm/stm32/overview.txt
index 09aed5588d7c..a03b0357c017 100644
--- a/Documentation/arm/stm32/overview.txt
+++ b/Documentation/arm/stm32/overview.txt
@@ -5,7 +5,8 @@ Introduction
5------------ 5------------
6 6
7 The STMicroelectronics family of Cortex-M based MCUs are supported by the 7 The STMicroelectronics family of Cortex-M based MCUs are supported by the
8 'STM32' platform of ARM Linux. Currently only the STM32F429 is supported. 8 'STM32' platform of ARM Linux. Currently only the STM32F429 (Cortex-M4)
9 and STM32F746 (Cortex-M7) are supported.
9 10
10 11
11Configuration 12Configuration
diff --git a/Documentation/arm/stm32/stm32f746-overview.txt b/Documentation/arm/stm32/stm32f746-overview.txt
new file mode 100644
index 000000000000..cffd2b1ccd6f
--- /dev/null
+++ b/Documentation/arm/stm32/stm32f746-overview.txt
@@ -0,0 +1,34 @@
1 STM32F746 Overview
2 ==================
3
4 Introduction
5 ------------
6 The STM32F746 is a Cortex-M7 MCU aimed at various applications.
7 It features:
8 - Cortex-M7 core running up to @216MHz
9 - 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM)
10 - FMC controller to connect SDRAM, NOR and NAND memories
11 - Dual mode QSPI
12 - SD/MMC/SDIO support
13 - Ethernet controller
14 - USB OTFG FS & HS controllers
15 - I2C, SPI, CAN busses support
16 - Several 16 & 32 bits general purpose timers
17 - Serial Audio interface
18 - LCD controller
19 - HDMI-CEC
20 - SPDIFRX
21
22 Resources
23 ---------
24 Datasheet and reference manual are publicly available on ST website:
25 - http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32f7-series/stm32f7x6/stm32f746ng.html
26
27 Document Author
28 ---------------
29 Alexandre Torgue <alexandre.torgue@st.com>
30
31
32
33
34
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index f53e2ee65e35..454b1bec7542 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -86,6 +86,9 @@ SoCs:
86- DRA722 86- DRA722
87 compatible = "ti,dra722", "ti,dra72", "ti,dra7" 87 compatible = "ti,dra722", "ti,dra72", "ti,dra7"
88 88
89- DRA718
90 compatible = "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7"
91
89- AM5728 92- AM5728
90 compatible = "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7" 93 compatible = "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
91 94
@@ -181,6 +184,9 @@ Boards:
181- DRA722 EVM: Software Development Board for DRA722 184- DRA722 EVM: Software Development Board for DRA722
182 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7" 185 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"
183 186
187- DRA718 EVM: Software Development Board for DRA718
188 compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7"
189
184- DM3730 Logic PD Torpedo + Wireless: Commercial System on Module with WiFi and Bluetooth 190- DM3730 Logic PD Torpedo + Wireless: Commercial System on Module with WiFi and Bluetooth
185 compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3" 191 compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3"
186 192
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 2f0b7169f132..3c7acf22957a 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -13,6 +13,10 @@ SoCs:
13 compatible = "renesas,r8a73a4" 13 compatible = "renesas,r8a73a4"
14 - R-Mobile A1 (R8A77400) 14 - R-Mobile A1 (R8A77400)
15 compatible = "renesas,r8a7740" 15 compatible = "renesas,r8a7740"
16 - RZ/G1M (R8A77430)
17 compatible = "renesas,r8a7743"
18 - RZ/G1E (R8A77450)
19 compatible = "renesas,r8a7745"
16 - R-Car M1A (R8A77781) 20 - R-Car M1A (R8A77781)
17 compatible = "renesas,r8a7778" 21 compatible = "renesas,r8a7778"
18 - R-Car H1 (R8A77790) 22 - R-Car H1 (R8A77790)
@@ -35,7 +39,7 @@ SoCs:
35 39
36Boards: 40Boards:
37 41
38 - Alt 42 - Alt (RTP0RC7794SEB00010S)
39 compatible = "renesas,alt", "renesas,r8a7794" 43 compatible = "renesas,alt", "renesas,r8a7794"
40 - APE6-EVM 44 - APE6-EVM
41 compatible = "renesas,ape6evm", "renesas,r8a73a4" 45 compatible = "renesas,ape6evm", "renesas,r8a73a4"
@@ -47,7 +51,7 @@ Boards:
47 compatible = "renesas,bockw", "renesas,r8a7778" 51 compatible = "renesas,bockw", "renesas,r8a7778"
48 - Genmai (RTK772100BC00000BR) 52 - Genmai (RTK772100BC00000BR)
49 compatible = "renesas,genmai", "renesas,r7s72100" 53 compatible = "renesas,genmai", "renesas,r7s72100"
50 - Gose 54 - Gose (RTP0RC7793SEB00010S)
51 compatible = "renesas,gose", "renesas,r8a7793" 55 compatible = "renesas,gose", "renesas,r8a7793"
52 - H3ULCB (RTP0RC7795SKB00010S) 56 - H3ULCB (RTP0RC7795SKB00010S)
53 compatible = "renesas,h3ulcb", "renesas,r8a7795"; 57 compatible = "renesas,h3ulcb", "renesas,r8a7795";
@@ -61,7 +65,7 @@ Boards:
61 compatible = "renesas,kzm9g", "renesas,sh73a0" 65 compatible = "renesas,kzm9g", "renesas,sh73a0"
62 - Lager (RTP0RC7790SEB00010S) 66 - Lager (RTP0RC7790SEB00010S)
63 compatible = "renesas,lager", "renesas,r8a7790" 67 compatible = "renesas,lager", "renesas,r8a7790"
64 - Marzen 68 - Marzen (R0P7779A00010S)
65 compatible = "renesas,marzen", "renesas,r8a7779" 69 compatible = "renesas,marzen", "renesas,r8a7779"
66 - Porter (M2-LCDP) 70 - Porter (M2-LCDP)
67 compatible = "renesas,porter", "renesas,r8a7791" 71 compatible = "renesas,porter", "renesas,r8a7791"
@@ -73,5 +77,9 @@ Boards:
73 compatible = "renesas,salvator-x", "renesas,r8a7796"; 77 compatible = "renesas,salvator-x", "renesas,r8a7796";
74 - SILK (RTP0RC7794LCB00011S) 78 - SILK (RTP0RC7794LCB00011S)
75 compatible = "renesas,silk", "renesas,r8a7794" 79 compatible = "renesas,silk", "renesas,r8a7794"
80 - SK-RZG1E (YR8A77450S000BE)
81 compatible = "renesas,sk-rzg1e", "renesas,r8a7745"
82 - SK-RZG1M (YR8A77430S000BE)
83 compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
76 - Wheat 84 - Wheat
77 compatible = "renesas,wheat", "renesas,r8a7792" 85 compatible = "renesas,wheat", "renesas,r8a7792"
diff --git a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-bt-bmc.txt b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-bt-bmc.txt
new file mode 100644
index 000000000000..fbbacd958240
--- /dev/null
+++ b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-bt-bmc.txt
@@ -0,0 +1,23 @@
1* Aspeed BT (Block Transfer) IPMI interface
2
3The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs
4(BaseBoard Management Controllers) and the BT interface can be used to
5perform in-band IPMI communication with their host.
6
7Required properties:
8
9- compatible : should be "aspeed,ast2400-bt-bmc"
10- reg: physical address and size of the registers
11
12Optional properties:
13
14- interrupts: interrupt generated by the BT interface. without an
15 interrupt, the driver will operate in poll mode.
16
17Example:
18
19 ibt@1e789140 {
20 compatible = "aspeed,ast2400-bt-bmc";
21 reg = <0x1e789140 0x18>;
22 interrupts = <8>;
23 };
diff --git a/Documentation/devicetree/bindings/ipmi.txt b/Documentation/devicetree/bindings/ipmi/ipmi-smic.txt
index d5f1a877ed3e..d5f1a877ed3e 100644
--- a/Documentation/devicetree/bindings/ipmi.txt
+++ b/Documentation/devicetree/bindings/ipmi/ipmi-smic.txt
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
index 5e60ad18f147..2ad18c4ea55c 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
@@ -43,7 +43,9 @@ aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
43 43
44GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8 44GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8
45I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 45I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7
46RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 46RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 SPI1DEBUG SPI1PASSTHRU TIMER4 TIMER5 TIMER6
47TIMER7 TIMER8 VGABIOSROM
48
47 49
48Examples: 50Examples:
49 51
diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt
new file mode 100644
index 000000000000..af5dd35469d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/jcore,pit.txt
@@ -0,0 +1,24 @@
1J-Core Programmable Interval Timer and Clocksource
2
3Required properties:
4
5- compatible: Must be "jcore,pit".
6
7- reg: Memory region(s) for timer/clocksource registers. For SMP,
8 there should be one region per cpu, indexed by the sequential,
9 zero-based hardware cpu number.
10
11- interrupts: An interrupt to assign for the timer. The actual pit
12 core is integrated with the aic and allows the timer interrupt
13 assignment to be programmed by software, but this property is
14 required in order to reserve an interrupt number that doesn't
15 conflict with other devices.
16
17
18Example:
19
20timer@200 {
21 compatible = "jcore,pit";
22 reg = < 0x200 0x30 0x500 0x30 >;
23 interrupts = < 0x48 >;
24};
diff --git a/Documentation/filesystems/proc.txt b/Documentation/filesystems/proc.txt
index 219ffd41a911..74329fd0add2 100644
--- a/Documentation/filesystems/proc.txt
+++ b/Documentation/filesystems/proc.txt
@@ -395,32 +395,6 @@ is not associated with a file:
395 395
396 or if empty, the mapping is anonymous. 396 or if empty, the mapping is anonymous.
397 397
398The /proc/PID/task/TID/maps is a view of the virtual memory from the viewpoint
399of the individual tasks of a process. In this file you will see a mapping marked
400as [stack] if that task sees it as a stack. Hence, for the example above, the
401task-level map, i.e. /proc/PID/task/TID/maps for thread 1001 will look like this:
402
40308048000-08049000 r-xp 00000000 03:00 8312 /opt/test
40408049000-0804a000 rw-p 00001000 03:00 8312 /opt/test
4050804a000-0806b000 rw-p 00000000 00:00 0 [heap]
406a7cb1000-a7cb2000 ---p 00000000 00:00 0
407a7cb2000-a7eb2000 rw-p 00000000 00:00 0
408a7eb2000-a7eb3000 ---p 00000000 00:00 0
409a7eb3000-a7ed5000 rw-p 00000000 00:00 0 [stack]
410a7ed5000-a8008000 r-xp 00000000 03:00 4222 /lib/libc.so.6
411a8008000-a800a000 r--p 00133000 03:00 4222 /lib/libc.so.6
412a800a000-a800b000 rw-p 00135000 03:00 4222 /lib/libc.so.6
413a800b000-a800e000 rw-p 00000000 00:00 0
414a800e000-a8022000 r-xp 00000000 03:00 14462 /lib/libpthread.so.0
415a8022000-a8023000 r--p 00013000 03:00 14462 /lib/libpthread.so.0
416a8023000-a8024000 rw-p 00014000 03:00 14462 /lib/libpthread.so.0
417a8024000-a8027000 rw-p 00000000 00:00 0
418a8027000-a8043000 r-xp 00000000 03:00 8317 /lib/ld-linux.so.2
419a8043000-a8044000 r--p 0001b000 03:00 8317 /lib/ld-linux.so.2
420a8044000-a8045000 rw-p 0001c000 03:00 8317 /lib/ld-linux.so.2
421aff35000-aff4a000 rw-p 00000000 00:00 0
422ffffe000-fffff000 r-xp 00000000 00:00 0 [vdso]
423
424The /proc/PID/smaps is an extension based on maps, showing the memory 398The /proc/PID/smaps is an extension based on maps, showing the memory
425consumption for each of the process's mappings. For each of mappings there 399consumption for each of the process's mappings. For each of mappings there
426is a series of lines such as the following: 400is a series of lines such as the following:
diff --git a/MAINTAINERS b/MAINTAINERS
index 1cd38a7e0064..c44795306342 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4620,8 +4620,9 @@ F: sound/usb/misc/ua101.c
4620 4620
4621EXTENSIBLE FIRMWARE INTERFACE (EFI) 4621EXTENSIBLE FIRMWARE INTERFACE (EFI)
4622M: Matt Fleming <matt@codeblueprint.co.uk> 4622M: Matt Fleming <matt@codeblueprint.co.uk>
4623M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
4623L: linux-efi@vger.kernel.org 4624L: linux-efi@vger.kernel.org
4624T: git git://git.kernel.org/pub/scm/linux/kernel/git/mfleming/efi.git 4625T: git git://git.kernel.org/pub/scm/linux/kernel/git/efi/efi.git
4625S: Maintained 4626S: Maintained
4626F: Documentation/efi-stub.txt 4627F: Documentation/efi-stub.txt
4627F: arch/ia64/kernel/efi.c 4628F: arch/ia64/kernel/efi.c
@@ -8212,7 +8213,7 @@ F: include/linux/mfd/
8212MULTIMEDIA CARD (MMC), SECURE DIGITAL (SD) AND SDIO SUBSYSTEM 8213MULTIMEDIA CARD (MMC), SECURE DIGITAL (SD) AND SDIO SUBSYSTEM
8213M: Ulf Hansson <ulf.hansson@linaro.org> 8214M: Ulf Hansson <ulf.hansson@linaro.org>
8214L: linux-mmc@vger.kernel.org 8215L: linux-mmc@vger.kernel.org
8215T: git git://git.linaro.org/people/ulf.hansson/mmc.git 8216T: git git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git
8216S: Maintained 8217S: Maintained
8217F: Documentation/devicetree/bindings/mmc/ 8218F: Documentation/devicetree/bindings/mmc/
8218F: drivers/mmc/ 8219F: drivers/mmc/
@@ -9299,7 +9300,7 @@ S: Maintained
9299F: drivers/pci/host/*designware* 9300F: drivers/pci/host/*designware*
9300 9301
9301PCI DRIVER FOR SYNOPSYS PROTOTYPING DEVICE 9302PCI DRIVER FOR SYNOPSYS PROTOTYPING DEVICE
9302M: Joao Pinto <jpinto@synopsys.com> 9303M: Jose Abreu <Jose.Abreu@synopsys.com>
9303L: linux-pci@vger.kernel.org 9304L: linux-pci@vger.kernel.org
9304S: Maintained 9305S: Maintained
9305F: Documentation/devicetree/bindings/pci/designware-pcie.txt 9306F: Documentation/devicetree/bindings/pci/designware-pcie.txt
diff --git a/Makefile b/Makefile
index 512e47a53e9a..93beca4312c4 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
1VERSION = 4 1VERSION = 4
2PATCHLEVEL = 9 2PATCHLEVEL = 9
3SUBLEVEL = 0 3SUBLEVEL = 0
4EXTRAVERSION = -rc1 4EXTRAVERSION = -rc2
5NAME = Psychotic Stoned Sheep 5NAME = Psychotic Stoned Sheep
6 6
7# *DOCUMENTATION* 7# *DOCUMENTATION*
diff --git a/arch/alpha/kernel/ptrace.c b/arch/alpha/kernel/ptrace.c
index d9ee81769899..940dfb406591 100644
--- a/arch/alpha/kernel/ptrace.c
+++ b/arch/alpha/kernel/ptrace.c
@@ -157,14 +157,16 @@ put_reg(struct task_struct *task, unsigned long regno, unsigned long data)
157static inline int 157static inline int
158read_int(struct task_struct *task, unsigned long addr, int * data) 158read_int(struct task_struct *task, unsigned long addr, int * data)
159{ 159{
160 int copied = access_process_vm(task, addr, data, sizeof(int), 0); 160 int copied = access_process_vm(task, addr, data, sizeof(int),
161 FOLL_FORCE);
161 return (copied == sizeof(int)) ? 0 : -EIO; 162 return (copied == sizeof(int)) ? 0 : -EIO;
162} 163}
163 164
164static inline int 165static inline int
165write_int(struct task_struct *task, unsigned long addr, int data) 166write_int(struct task_struct *task, unsigned long addr, int data)
166{ 167{
167 int copied = access_process_vm(task, addr, &data, sizeof(int), 1); 168 int copied = access_process_vm(task, addr, &data, sizeof(int),
169 FOLL_FORCE | FOLL_WRITE);
168 return (copied == sizeof(int)) ? 0 : -EIO; 170 return (copied == sizeof(int)) ? 0 : -EIO;
169} 171}
170 172
@@ -281,7 +283,8 @@ long arch_ptrace(struct task_struct *child, long request,
281 /* When I and D space are separate, these will need to be fixed. */ 283 /* When I and D space are separate, these will need to be fixed. */
282 case PTRACE_PEEKTEXT: /* read word at location addr. */ 284 case PTRACE_PEEKTEXT: /* read word at location addr. */
283 case PTRACE_PEEKDATA: 285 case PTRACE_PEEKDATA:
284 copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0); 286 copied = access_process_vm(child, addr, &tmp, sizeof(tmp),
287 FOLL_FORCE);
285 ret = -EIO; 288 ret = -EIO;
286 if (copied != sizeof(tmp)) 289 if (copied != sizeof(tmp))
287 break; 290 break;
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b5d529fdffab..4353765a592f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -887,6 +887,11 @@ config MACH_STM32F429
887 depends on ARCH_STM32 887 depends on ARCH_STM32
888 default y 888 default y
889 889
890config MACH_STM32F746
891 bool "STMicrolectronics STM32F746"
892 depends on ARCH_STM32
893 default y
894
890config ARCH_MPS2 895config ARCH_MPS2
891 bool "ARM MPS2 platform" 896 bool "ARM MPS2 platform"
892 depends on ARM_SINGLE_ARMV7M 897 depends on ARM_SINGLE_ARMV7M
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6be9ee148b78..68312a9f660a 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MXS) += mxs
191machine-$(CONFIG_ARCH_NETX) += netx 191machine-$(CONFIG_ARCH_NETX) += netx
192machine-$(CONFIG_ARCH_NOMADIK) += nomadik 192machine-$(CONFIG_ARCH_NOMADIK) += nomadik
193machine-$(CONFIG_ARCH_NSPIRE) += nspire 193machine-$(CONFIG_ARCH_NSPIRE) += nspire
194machine-$(CONFIG_ARCH_OXNAS) += oxnas
194machine-$(CONFIG_ARCH_OMAP1) += omap1 195machine-$(CONFIG_ARCH_OMAP1) += omap1
195machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2 196machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
196machine-$(CONFIG_ARCH_ORION5X) += orion5x 197machine-$(CONFIG_ARCH_ORION5X) += orion5x
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index 03e9273f1876..08bb84f2ad58 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -1312,6 +1312,13 @@ static int init_hyp_mode(void)
1312 goto out_err; 1312 goto out_err;
1313 } 1313 }
1314 1314
1315 err = create_hyp_mappings(kvm_ksym_ref(__bss_start),
1316 kvm_ksym_ref(__bss_stop), PAGE_HYP_RO);
1317 if (err) {
1318 kvm_err("Cannot map bss section\n");
1319 goto out_err;
1320 }
1321
1315 /* 1322 /*
1316 * Map the Hyp stack pages 1323 * Map the Hyp stack pages
1317 */ 1324 */
diff --git a/arch/arm/mach-artpec/Kconfig b/arch/arm/mach-artpec/Kconfig
index 6cbe5a2eabab..85a962abb77f 100644
--- a/arch/arm/mach-artpec/Kconfig
+++ b/arch/arm/mach-artpec/Kconfig
@@ -14,6 +14,7 @@ config MACH_ARTPEC6
14 select HAVE_ARM_ARCH_TIMER 14 select HAVE_ARM_ARCH_TIMER
15 select HAVE_ARM_SCU 15 select HAVE_ARM_SCU
16 select HAVE_ARM_TWD if SMP 16 select HAVE_ARM_TWD if SMP
17 select MFD_SYSCON
17 help 18 help
18 Support for Axis ARTPEC-6 ARM Cortex A9 Platform 19 Support for Axis ARTPEC-6 ARM Cortex A9 Platform
19 20
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 3d8cf8cbd98a..5db09014f55a 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -27,6 +27,7 @@
27#include <linux/platform_data/mtd-davinci-aemif.h> 27#include <linux/platform_data/mtd-davinci-aemif.h>
28#include <linux/platform_data/spi-davinci.h> 28#include <linux/platform_data/spi-davinci.h>
29#include <linux/platform_data/usb-davinci.h> 29#include <linux/platform_data/usb-davinci.h>
30#include <linux/regulator/machine.h>
30 31
31#include <asm/mach-types.h> 32#include <asm/mach-types.h>
32#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
@@ -106,43 +107,24 @@ static irqreturn_t da830_evm_usb_ocic_irq(int irq, void *dev_id)
106 107
107static __init void da830_evm_usb_init(void) 108static __init void da830_evm_usb_init(void)
108{ 109{
109 u32 cfgchip2;
110 int ret; 110 int ret;
111 111
112 /* 112 /* USB_REFCLKIN is not used. */
113 * Set up USB clock/mode in the CFGCHIP2 register. 113 ret = da8xx_register_usb20_phy_clk(false);
114 * FYI: CFGCHIP2 is 0x0000ef00 initially. 114 if (ret)
115 */ 115 pr_warn("%s: USB 2.0 PHY CLK registration failed: %d\n",
116 cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); 116 __func__, ret);
117 117
118 /* USB2.0 PHY reference clock is 24 MHz */ 118 ret = da8xx_register_usb11_phy_clk(false);
119 cfgchip2 &= ~CFGCHIP2_REFFREQ; 119 if (ret)
120 cfgchip2 |= CFGCHIP2_REFFREQ_24MHZ; 120 pr_warn("%s: USB 1.1 PHY CLK registration failed: %d\n",
121 121 __func__, ret);
122 /*
123 * Select internal reference clock for USB 2.0 PHY
124 * and use it as a clock source for USB 1.1 PHY
125 * (this is the default setting anyway).
126 */
127 cfgchip2 &= ~CFGCHIP2_USB1PHYCLKMUX;
128 cfgchip2 |= CFGCHIP2_USB2PHYCLKMUX;
129
130 /*
131 * We have to override VBUS/ID signals when MUSB is configured into the
132 * host-only mode -- ID pin will float if no cable is connected, so the
133 * controller won't be able to drive VBUS thinking that it's a B-device.
134 * Otherwise, we want to use the OTG mode and enable VBUS comparators.
135 */
136 cfgchip2 &= ~CFGCHIP2_OTGMODE;
137#ifdef CONFIG_USB_MUSB_HOST
138 cfgchip2 |= CFGCHIP2_FORCE_HOST;
139#else
140 cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN;
141#endif
142 122
143 __raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); 123 ret = da8xx_register_usb_phy();
124 if (ret)
125 pr_warn("%s: USB PHY registration failed: %d\n",
126 __func__, ret);
144 127
145 /* USB_REFCLKIN is not used. */
146 ret = davinci_cfg_reg(DA830_USB0_DRVVBUS); 128 ret = davinci_cfg_reg(DA830_USB0_DRVVBUS);
147 if (ret) 129 if (ret)
148 pr_warn("%s: USB 2.0 PinMux setup failed: %d\n", __func__, ret); 130 pr_warn("%s: USB 2.0 PinMux setup failed: %d\n", __func__, ret);
@@ -588,6 +570,10 @@ static __init void da830_evm_init(void)
588 struct davinci_soc_info *soc_info = &davinci_soc_info; 570 struct davinci_soc_info *soc_info = &davinci_soc_info;
589 int ret; 571 int ret;
590 572
573 ret = da8xx_register_cfgchip();
574 if (ret)
575 pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret);
576
591 ret = da830_register_gpio(); 577 ret = da830_register_gpio();
592 if (ret) 578 if (ret)
593 pr_warn("%s: GPIO init failed: %d\n", __func__, ret); 579 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
@@ -647,6 +633,8 @@ static __init void da830_evm_init(void)
647 ret = da8xx_register_spi_bus(0, ARRAY_SIZE(da830evm_spi_info)); 633 ret = da8xx_register_spi_bus(0, ARRAY_SIZE(da830evm_spi_info));
648 if (ret) 634 if (ret)
649 pr_warn("%s: spi 0 registration failed: %d\n", __func__, ret); 635 pr_warn("%s: spi 0 registration failed: %d\n", __func__, ret);
636
637 regulator_has_full_constraints();
650} 638}
651 639
652#ifdef CONFIG_SERIAL_8250_CONSOLE 640#ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 8e4539f69fdc..ec5cb105e1d6 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -1345,6 +1345,10 @@ static __init void da850_evm_init(void)
1345{ 1345{
1346 int ret; 1346 int ret;
1347 1347
1348 ret = da8xx_register_cfgchip();
1349 if (ret)
1350 pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret);
1351
1348 ret = da850_register_gpio(); 1352 ret = da850_register_gpio();
1349 if (ret) 1353 if (ret)
1350 pr_warn("%s: GPIO init failed: %d\n", __func__, ret); 1354 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index bc4e63fa9808..1a6d430742d4 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -514,6 +514,10 @@ static void __init mityomapl138_init(void)
514{ 514{
515 int ret; 515 int ret;
516 516
517 ret = da8xx_register_cfgchip();
518 if (ret)
519 pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret);
520
517 /* for now, no special EDMA channels are reserved */ 521 /* for now, no special EDMA channels are reserved */
518 ret = da850_register_edma(NULL); 522 ret = da850_register_edma(NULL);
519 if (ret) 523 if (ret)
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index ee624861ca66..a4e87264ebd7 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -14,6 +14,7 @@
14#include <linux/console.h> 14#include <linux/console.h>
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16#include <linux/platform_data/gpio-davinci.h> 16#include <linux/platform_data/gpio-davinci.h>
17#include <linux/regulator/machine.h>
17 18
18#include <asm/mach-types.h> 19#include <asm/mach-types.h>
19#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
@@ -243,7 +244,6 @@ static irqreturn_t omapl138_hawk_usb_ocic_irq(int irq, void *dev_id)
243static __init void omapl138_hawk_usb_init(void) 244static __init void omapl138_hawk_usb_init(void)
244{ 245{
245 int ret; 246 int ret;
246 u32 cfgchip2;
247 247
248 ret = davinci_cfg_reg_list(da850_hawk_usb11_pins); 248 ret = davinci_cfg_reg_list(da850_hawk_usb11_pins);
249 if (ret) { 249 if (ret) {
@@ -251,12 +251,20 @@ static __init void omapl138_hawk_usb_init(void)
251 return; 251 return;
252 } 252 }
253 253
254 /* Setup the Ref. clock frequency for the HAWK at 24 MHz. */ 254 ret = da8xx_register_usb20_phy_clk(false);
255 if (ret)
256 pr_warn("%s: USB 2.0 PHY CLK registration failed: %d\n",
257 __func__, ret);
258
259 ret = da8xx_register_usb11_phy_clk(false);
260 if (ret)
261 pr_warn("%s: USB 1.1 PHY CLK registration failed: %d\n",
262 __func__, ret);
255 263
256 cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); 264 ret = da8xx_register_usb_phy();
257 cfgchip2 &= ~CFGCHIP2_REFFREQ; 265 if (ret)
258 cfgchip2 |= CFGCHIP2_REFFREQ_24MHZ; 266 pr_warn("%s: USB PHY registration failed: %d\n",
259 __raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); 267 __func__, ret);
260 268
261 ret = gpio_request_one(DA850_USB1_VBUS_PIN, 269 ret = gpio_request_one(DA850_USB1_VBUS_PIN,
262 GPIOF_DIR_OUT, "USB1 VBUS"); 270 GPIOF_DIR_OUT, "USB1 VBUS");
@@ -292,6 +300,10 @@ static __init void omapl138_hawk_init(void)
292{ 300{
293 int ret; 301 int ret;
294 302
303 ret = da8xx_register_cfgchip();
304 if (ret)
305 pr_warn("%s: CFGCHIP registration failed: %d\n", __func__, ret);
306
295 ret = da850_register_gpio(); 307 ret = da850_register_gpio();
296 if (ret) 308 if (ret)
297 pr_warn("%s: GPIO init failed: %d\n", __func__, ret); 309 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
@@ -317,6 +329,8 @@ static __init void omapl138_hawk_init(void)
317 if (ret) 329 if (ret)
318 pr_warn("%s: dsp/rproc registration failed: %d\n", 330 pr_warn("%s: dsp/rproc registration failed: %d\n",
319 __func__, ret); 331 __func__, ret);
332
333 regulator_has_full_constraints();
320} 334}
321 335
322#ifdef CONFIG_SERIAL_8250_CONSOLE 336#ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 426fd7477357..41459bd91c85 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -412,7 +412,7 @@ static struct clk_lookup da830_clks[] = {
412 CLK("davinci-mcasp.0", NULL, &mcasp0_clk), 412 CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
413 CLK("davinci-mcasp.1", NULL, &mcasp1_clk), 413 CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
414 CLK("davinci-mcasp.2", NULL, &mcasp2_clk), 414 CLK("davinci-mcasp.2", NULL, &mcasp2_clk),
415 CLK(NULL, "usb20", &usb20_clk), 415 CLK("musb-da8xx", "usb20", &usb20_clk),
416 CLK(NULL, "aemif", &aemif_clk), 416 CLK(NULL, "aemif", &aemif_clk),
417 CLK(NULL, "aintc", &aintc_clk), 417 CLK(NULL, "aintc", &aintc_clk),
418 CLK(NULL, "secu_mgr", &secu_mgr_clk), 418 CLK(NULL, "secu_mgr", &secu_mgr_clk),
@@ -420,7 +420,7 @@ static struct clk_lookup da830_clks[] = {
420 CLK("davinci_mdio.0", "fck", &emac_clk), 420 CLK("davinci_mdio.0", "fck", &emac_clk),
421 CLK(NULL, "gpio", &gpio_clk), 421 CLK(NULL, "gpio", &gpio_clk),
422 CLK("i2c_davinci.2", NULL, &i2c1_clk), 422 CLK("i2c_davinci.2", NULL, &i2c1_clk),
423 CLK(NULL, "usb11", &usb11_clk), 423 CLK("ohci", "usb11", &usb11_clk),
424 CLK(NULL, "emif3", &emif3_clk), 424 CLK(NULL, "emif3", &emif3_clk),
425 CLK(NULL, "arm", &arm_clk), 425 CLK(NULL, "arm", &arm_clk),
426 CLK(NULL, "rmii", &rmii_clk), 426 CLK(NULL, "rmii", &rmii_clk),
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index ed3d0e9f72ac..196e262b7147 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -503,8 +503,8 @@ static struct clk_lookup da850_clks[] = {
503 CLK("da830-mmc.1", NULL, &mmcsd1_clk), 503 CLK("da830-mmc.1", NULL, &mmcsd1_clk),
504 CLK("ti-aemif", NULL, &aemif_clk), 504 CLK("ti-aemif", NULL, &aemif_clk),
505 CLK(NULL, "aemif", &aemif_clk), 505 CLK(NULL, "aemif", &aemif_clk),
506 CLK(NULL, "usb11", &usb11_clk), 506 CLK("ohci", "usb11", &usb11_clk),
507 CLK(NULL, "usb20", &usb20_clk), 507 CLK("musb-da8xx", "usb20", &usb20_clk),
508 CLK("spi_davinci.0", NULL, &spi0_clk), 508 CLK("spi_davinci.0", NULL, &spi0_clk),
509 CLK("spi_davinci.1", NULL, &spi1_clk), 509 CLK("spi_davinci.1", NULL, &spi1_clk),
510 CLK("vpif", NULL, &vpif_clk), 510 CLK("vpif", NULL, &vpif_clk),
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index c9f7e9274aa8..92ae093a2120 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -38,6 +38,10 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
38 NULL), 38 NULL),
39 OF_DEV_AUXDATA("ti,da830-mcasp-audio", 0x01d00000, "davinci-mcasp.0", NULL), 39 OF_DEV_AUXDATA("ti,da830-mcasp-audio", 0x01d00000, "davinci-mcasp.0", NULL),
40 OF_DEV_AUXDATA("ti,da850-aemif", 0x68000000, "ti-aemif", NULL), 40 OF_DEV_AUXDATA("ti,da850-aemif", 0x68000000, "ti-aemif", NULL),
41 OF_DEV_AUXDATA("ti,da850-tilcdc", 0x01e13000, "da8xx_lcdc.0", NULL),
42 OF_DEV_AUXDATA("ti,da830-ohci", 0x01e25000, "ohci", NULL),
43 OF_DEV_AUXDATA("ti,da830-musb", 0x01e00000, "musb-da8xx", NULL),
44 OF_DEV_AUXDATA("ti,da830-usb-phy", 0x01c1417c, "da8xx-usb-phy", NULL),
41 {} 45 {}
42}; 46};
43 47
@@ -45,6 +49,17 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
45 49
46static void __init da850_init_machine(void) 50static void __init da850_init_machine(void)
47{ 51{
52 int ret;
53
54 ret = da8xx_register_usb20_phy_clk(false);
55 if (ret)
56 pr_warn("%s: registering USB 2.0 PHY clock failed: %d",
57 __func__, ret);
58 ret = da8xx_register_usb11_phy_clk(false);
59 if (ret)
60 pr_warn("%s: registering USB 1.1 PHY clock failed: %d",
61 __func__, ret);
62
48 of_platform_default_populate(NULL, da850_auxdata_lookup, NULL); 63 of_platform_default_populate(NULL, da850_auxdata_lookup, NULL);
49} 64}
50 65
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index add3771d38f6..c2457b3fdb5f 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -11,6 +11,7 @@
11 * (at your option) any later version. 11 * (at your option) any later version.
12 */ 12 */
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/platform_data/syscon.h>
14#include <linux/platform_device.h> 15#include <linux/platform_device.h>
15#include <linux/dma-contiguous.h> 16#include <linux/dma-contiguous.h>
16#include <linux/serial_8250.h> 17#include <linux/serial_8250.h>
@@ -57,15 +58,6 @@
57#define DA8XX_EMAC_RAM_OFFSET 0x0000 58#define DA8XX_EMAC_RAM_OFFSET 0x0000
58#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K 59#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
59 60
60#define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14)
61#define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15)
62#define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16)
63#define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17)
64#define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18)
65#define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19)
66#define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28)
67#define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29)
68
69void __iomem *da8xx_syscfg0_base; 61void __iomem *da8xx_syscfg0_base;
70void __iomem *da8xx_syscfg1_base; 62void __iomem *da8xx_syscfg1_base;
71 63
@@ -964,16 +956,6 @@ static struct resource da8xx_spi0_resources[] = {
964 .end = IRQ_DA8XX_SPINT0, 956 .end = IRQ_DA8XX_SPINT0,
965 .flags = IORESOURCE_IRQ, 957 .flags = IORESOURCE_IRQ,
966 }, 958 },
967 [2] = {
968 .start = DA8XX_DMA_SPI0_RX,
969 .end = DA8XX_DMA_SPI0_RX,
970 .flags = IORESOURCE_DMA,
971 },
972 [3] = {
973 .start = DA8XX_DMA_SPI0_TX,
974 .end = DA8XX_DMA_SPI0_TX,
975 .flags = IORESOURCE_DMA,
976 },
977}; 959};
978 960
979static struct resource da8xx_spi1_resources[] = { 961static struct resource da8xx_spi1_resources[] = {
@@ -987,16 +969,6 @@ static struct resource da8xx_spi1_resources[] = {
987 .end = IRQ_DA8XX_SPINT1, 969 .end = IRQ_DA8XX_SPINT1,
988 .flags = IORESOURCE_IRQ, 970 .flags = IORESOURCE_IRQ,
989 }, 971 },
990 [2] = {
991 .start = DA8XX_DMA_SPI1_RX,
992 .end = DA8XX_DMA_SPI1_RX,
993 .flags = IORESOURCE_DMA,
994 },
995 [3] = {
996 .start = DA8XX_DMA_SPI1_TX,
997 .end = DA8XX_DMA_SPI1_TX,
998 .flags = IORESOURCE_DMA,
999 },
1000}; 972};
1001 973
1002static struct davinci_spi_platform_data da8xx_spi_pdata[] = { 974static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
@@ -1089,3 +1061,30 @@ int __init da850_register_sata(unsigned long refclkpn)
1089 return platform_device_register(&da850_sata_device); 1061 return platform_device_register(&da850_sata_device);
1090} 1062}
1091#endif 1063#endif
1064
1065static struct syscon_platform_data da8xx_cfgchip_platform_data = {
1066 .label = "cfgchip",
1067};
1068
1069static struct resource da8xx_cfgchip_resources[] = {
1070 {
1071 .start = DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP0_REG,
1072 .end = DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP4_REG + 3,
1073 .flags = IORESOURCE_MEM,
1074 },
1075};
1076
1077static struct platform_device da8xx_cfgchip_device = {
1078 .name = "syscon",
1079 .id = -1,
1080 .dev = {
1081 .platform_data = &da8xx_cfgchip_platform_data,
1082 },
1083 .num_resources = ARRAY_SIZE(da8xx_cfgchip_resources),
1084 .resource = da8xx_cfgchip_resources,
1085};
1086
1087int __init da8xx_register_cfgchip(void)
1088{
1089 return platform_device_register(&da8xx_cfgchip_device);
1090}
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 67d26c5bda0b..3ae70f2909b0 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -36,9 +36,6 @@
36#define DM365_MMCSD0_BASE 0x01D11000 36#define DM365_MMCSD0_BASE 0x01D11000
37#define DM365_MMCSD1_BASE 0x01D00000 37#define DM365_MMCSD1_BASE 0x01D00000
38 38
39#define DAVINCI_DMA_MMCRXEVT 26
40#define DAVINCI_DMA_MMCTXEVT 27
41
42void __iomem *davinci_sysmod_base; 39void __iomem *davinci_sysmod_base;
43 40
44void davinci_map_sysmod(void) 41void davinci_map_sysmod(void)
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index d33322ddedab..bd50367f654e 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -397,14 +397,6 @@ static struct resource dm355_spi0_resources[] = {
397 .start = IRQ_DM355_SPINT0_0, 397 .start = IRQ_DM355_SPINT0_0,
398 .flags = IORESOURCE_IRQ, 398 .flags = IORESOURCE_IRQ,
399 }, 399 },
400 {
401 .start = 17,
402 .flags = IORESOURCE_DMA,
403 },
404 {
405 .start = 16,
406 .flags = IORESOURCE_DMA,
407 },
408}; 400};
409 401
410static struct davinci_spi_platform_data dm355_spi0_pdata = { 402static struct davinci_spi_platform_data dm355_spi0_pdata = {
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index ef3add999263..8be04ec95adf 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -660,14 +660,6 @@ static struct resource dm365_spi0_resources[] = {
660 .start = IRQ_DM365_SPIINT0_0, 660 .start = IRQ_DM365_SPIINT0_0,
661 .flags = IORESOURCE_IRQ, 661 .flags = IORESOURCE_IRQ,
662 }, 662 },
663 {
664 .start = 17,
665 .flags = IORESOURCE_DMA,
666 },
667 {
668 .start = 16,
669 .flags = IORESOURCE_DMA,
670 },
671}; 663};
672 664
673static struct platform_device dm365_spi0_device = { 665static struct platform_device dm365_spi0_device = {
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index f9f9713aacdd..43322be26bd5 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -61,6 +61,7 @@ extern unsigned int da850_max_speed;
61#define DA8XX_CFGCHIP1_REG 0x180 61#define DA8XX_CFGCHIP1_REG 0x180
62#define DA8XX_CFGCHIP2_REG 0x184 62#define DA8XX_CFGCHIP2_REG 0x184
63#define DA8XX_CFGCHIP3_REG 0x188 63#define DA8XX_CFGCHIP3_REG 0x188
64#define DA8XX_CFGCHIP4_REG 0x18c
64 65
65#define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000) 66#define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000)
66#define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x)) 67#define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x))
@@ -88,8 +89,12 @@ int da850_register_edma(struct edma_rsv_info *rsv[2]);
88int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); 89int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
89int da8xx_register_spi_bus(int instance, unsigned num_chipselect); 90int da8xx_register_spi_bus(int instance, unsigned num_chipselect);
90int da8xx_register_watchdog(void); 91int da8xx_register_watchdog(void);
92int da8xx_register_usb_phy(void);
91int da8xx_register_usb20(unsigned mA, unsigned potpgt); 93int da8xx_register_usb20(unsigned mA, unsigned potpgt);
92int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata); 94int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
95int da8xx_register_usb_refclkin(int rate);
96int da8xx_register_usb20_phy_clk(bool use_usb_refclkin);
97int da8xx_register_usb11_phy_clk(bool use_usb_refclkin);
93int da8xx_register_emac(void); 98int da8xx_register_emac(void);
94int da8xx_register_uio_pruss(void); 99int da8xx_register_uio_pruss(void);
95int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata); 100int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
@@ -113,6 +118,7 @@ void da8xx_rproc_reserve_cma(void);
113int da8xx_register_rproc(void); 118int da8xx_register_rproc(void);
114int da850_register_gpio(void); 119int da850_register_gpio(void);
115int da830_register_gpio(void); 120int da830_register_gpio(void);
121int da8xx_register_cfgchip(void);
116 122
117extern struct platform_device da8xx_serial_device[]; 123extern struct platform_device da8xx_serial_device[];
118extern struct emac_platform_data da8xx_emac_pdata; 124extern struct emac_platform_data da8xx_emac_pdata;
diff --git a/arch/arm/mach-davinci/usb-da8xx.c b/arch/arm/mach-davinci/usb-da8xx.c
index f141f5171906..b010e5f80c5f 100644
--- a/arch/arm/mach-davinci/usb-da8xx.c
+++ b/arch/arm/mach-davinci/usb-da8xx.c
@@ -1,21 +1,44 @@
1/* 1/*
2 * DA8xx USB 2 * DA8xx USB
3 */ 3 */
4#include <linux/clk.h>
5#include <linux/delay.h>
4#include <linux/dma-mapping.h> 6#include <linux/dma-mapping.h>
5#include <linux/init.h> 7#include <linux/init.h>
8#include <linux/mfd/da8xx-cfgchip.h>
9#include <linux/phy/phy.h>
6#include <linux/platform_data/usb-davinci.h> 10#include <linux/platform_data/usb-davinci.h>
7#include <linux/platform_device.h> 11#include <linux/platform_device.h>
8#include <linux/usb/musb.h> 12#include <linux/usb/musb.h>
9 13
14#include <mach/clock.h>
10#include <mach/common.h> 15#include <mach/common.h>
11#include <mach/cputype.h> 16#include <mach/cputype.h>
12#include <mach/da8xx.h> 17#include <mach/da8xx.h>
13#include <mach/irqs.h> 18#include <mach/irqs.h>
14 19
20#include "clock.h"
21
15#define DA8XX_USB0_BASE 0x01e00000 22#define DA8XX_USB0_BASE 0x01e00000
16#define DA8XX_USB1_BASE 0x01e25000 23#define DA8XX_USB1_BASE 0x01e25000
17 24
18#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) 25static struct platform_device da8xx_usb_phy = {
26 .name = "da8xx-usb-phy",
27 .id = -1,
28 .dev = {
29 /*
30 * Setting init_name so that clock lookup will work in
31 * da8xx_register_usb11_phy_clk() even if this device is not
32 * registered yet.
33 */
34 .init_name = "da8xx-usb-phy",
35 },
36};
37
38int __init da8xx_register_usb_phy(void)
39{
40 return platform_device_register(&da8xx_usb_phy);
41}
19 42
20static struct musb_hdrc_config musb_config = { 43static struct musb_hdrc_config musb_config = {
21 .multipoint = true, 44 .multipoint = true,
@@ -45,10 +68,15 @@ static struct resource da8xx_usb20_resources[] = {
45 68
46static u64 usb_dmamask = DMA_BIT_MASK(32); 69static u64 usb_dmamask = DMA_BIT_MASK(32);
47 70
48static struct platform_device usb_dev = { 71static struct platform_device da8xx_usb20_dev = {
49 .name = "musb-da8xx", 72 .name = "musb-da8xx",
50 .id = -1, 73 .id = -1,
51 .dev = { 74 .dev = {
75 /*
76 * Setting init_name so that clock lookup will work in
77 * usb20_phy_clk_enable() even if this device is not registered.
78 */
79 .init_name = "musb-da8xx",
52 .platform_data = &usb_data, 80 .platform_data = &usb_data,
53 .dma_mask = &usb_dmamask, 81 .dma_mask = &usb_dmamask,
54 .coherent_dma_mask = DMA_BIT_MASK(32), 82 .coherent_dma_mask = DMA_BIT_MASK(32),
@@ -62,18 +90,9 @@ int __init da8xx_register_usb20(unsigned int mA, unsigned int potpgt)
62 usb_data.power = mA > 510 ? 255 : mA / 2; 90 usb_data.power = mA > 510 ? 255 : mA / 2;
63 usb_data.potpgt = (potpgt + 1) / 2; 91 usb_data.potpgt = (potpgt + 1) / 2;
64 92
65 return platform_device_register(&usb_dev); 93 return platform_device_register(&da8xx_usb20_dev);
66}
67
68#else
69
70int __init da8xx_register_usb20(unsigned int mA, unsigned int potpgt)
71{
72 return 0;
73} 94}
74 95
75#endif /* CONFIG_USB_MUSB_HDRC */
76
77static struct resource da8xx_usb11_resources[] = { 96static struct resource da8xx_usb11_resources[] = {
78 [0] = { 97 [0] = {
79 .start = DA8XX_USB1_BASE, 98 .start = DA8XX_USB1_BASE,
@@ -105,3 +124,236 @@ int __init da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata)
105 da8xx_usb11_device.dev.platform_data = pdata; 124 da8xx_usb11_device.dev.platform_data = pdata;
106 return platform_device_register(&da8xx_usb11_device); 125 return platform_device_register(&da8xx_usb11_device);
107} 126}
127
128static struct clk usb_refclkin = {
129 .name = "usb_refclkin",
130 .set_rate = davinci_simple_set_rate,
131};
132
133static struct clk_lookup usb_refclkin_lookup =
134 CLK(NULL, "usb_refclkin", &usb_refclkin);
135
136/**
137 * da8xx_register_usb_refclkin - register USB_REFCLKIN clock
138 *
139 * @rate: The clock rate in Hz
140 *
141 * This clock is only needed if the board provides an external USB_REFCLKIN
142 * signal, in which case it will be used as the parent of usb20_phy_clk and/or
143 * usb11_phy_clk.
144 */
145int __init da8xx_register_usb_refclkin(int rate)
146{
147 int ret;
148
149 usb_refclkin.rate = rate;
150 ret = clk_register(&usb_refclkin);
151 if (ret)
152 return ret;
153
154 clkdev_add(&usb_refclkin_lookup);
155
156 return 0;
157}
158
159static void usb20_phy_clk_enable(struct clk *clk)
160{
161 struct clk *usb20_clk;
162 int err;
163 u32 val;
164 u32 timeout = 500000; /* 500 msec */
165
166 val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
167
168 usb20_clk = clk_get(&da8xx_usb20_dev.dev, "usb20");
169 if (IS_ERR(usb20_clk)) {
170 pr_err("could not get usb20 clk: %ld\n", PTR_ERR(usb20_clk));
171 return;
172 }
173
174 /* The USB 2.O PLL requires that the USB 2.O PSC is enabled as well. */
175 err = clk_prepare_enable(usb20_clk);
176 if (err) {
177 pr_err("failed to enable usb20 clk: %d\n", err);
178 clk_put(usb20_clk);
179 return;
180 }
181
182 /*
183 * Turn on the USB 2.0 PHY, but just the PLL, and not OTG. The USB 1.1
184 * host may use the PLL clock without USB 2.0 OTG being used.
185 */
186 val &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN);
187 val |= CFGCHIP2_PHY_PLLON;
188
189 writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
190
191 while (--timeout) {
192 val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
193 if (val & CFGCHIP2_PHYCLKGD)
194 goto done;
195 udelay(1);
196 }
197
198 pr_err("Timeout waiting for USB 2.0 PHY clock good\n");
199done:
200 clk_disable_unprepare(usb20_clk);
201 clk_put(usb20_clk);
202}
203
204static void usb20_phy_clk_disable(struct clk *clk)
205{
206 u32 val;
207
208 val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
209 val |= CFGCHIP2_PHYPWRDN;
210 writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
211}
212
213static int usb20_phy_clk_set_parent(struct clk *clk, struct clk *parent)
214{
215 u32 val;
216
217 val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
218
219 /* Set the mux depending on the parent clock. */
220 if (parent == &usb_refclkin) {
221 val &= ~CFGCHIP2_USB2PHYCLKMUX;
222 } else if (strcmp(parent->name, "pll0_aux_clk") == 0) {
223 val |= CFGCHIP2_USB2PHYCLKMUX;
224 } else {
225 pr_err("Bad parent on USB 2.0 PHY clock\n");
226 return -EINVAL;
227 }
228
229 /* reference frequency also comes from parent clock */
230 val &= ~CFGCHIP2_REFFREQ_MASK;
231 switch (clk_get_rate(parent)) {
232 case 12000000:
233 val |= CFGCHIP2_REFFREQ_12MHZ;
234 break;
235 case 13000000:
236 val |= CFGCHIP2_REFFREQ_13MHZ;
237 break;
238 case 19200000:
239 val |= CFGCHIP2_REFFREQ_19_2MHZ;
240 break;
241 case 20000000:
242 val |= CFGCHIP2_REFFREQ_20MHZ;
243 break;
244 case 24000000:
245 val |= CFGCHIP2_REFFREQ_24MHZ;
246 break;
247 case 26000000:
248 val |= CFGCHIP2_REFFREQ_26MHZ;
249 break;
250 case 38400000:
251 val |= CFGCHIP2_REFFREQ_38_4MHZ;
252 break;
253 case 40000000:
254 val |= CFGCHIP2_REFFREQ_40MHZ;
255 break;
256 case 48000000:
257 val |= CFGCHIP2_REFFREQ_48MHZ;
258 break;
259 default:
260 pr_err("Bad parent clock rate on USB 2.0 PHY clock\n");
261 return -EINVAL;
262 }
263
264 writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
265
266 return 0;
267}
268
269static struct clk usb20_phy_clk = {
270 .name = "usb20_phy",
271 .clk_enable = usb20_phy_clk_enable,
272 .clk_disable = usb20_phy_clk_disable,
273 .set_parent = usb20_phy_clk_set_parent,
274};
275
276static struct clk_lookup usb20_phy_clk_lookup =
277 CLK("da8xx-usb-phy", "usb20_phy", &usb20_phy_clk);
278
279/**
280 * da8xx_register_usb20_phy_clk - register USB0PHYCLKMUX clock
281 *
282 * @use_usb_refclkin: Selects the parent clock - either "usb_refclkin" if true
283 * or "pll0_aux" if false.
284 */
285int __init da8xx_register_usb20_phy_clk(bool use_usb_refclkin)
286{
287 struct clk *parent;
288 int ret = 0;
289
290 parent = clk_get(NULL, use_usb_refclkin ? "usb_refclkin" : "pll0_aux");
291 if (IS_ERR(parent))
292 return PTR_ERR(parent);
293
294 usb20_phy_clk.parent = parent;
295 ret = clk_register(&usb20_phy_clk);
296 if (!ret)
297 clkdev_add(&usb20_phy_clk_lookup);
298
299 clk_put(parent);
300
301 return ret;
302}
303
304static int usb11_phy_clk_set_parent(struct clk *clk, struct clk *parent)
305{
306 u32 val;
307
308 val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
309
310 /* Set the USB 1.1 PHY clock mux based on the parent clock. */
311 if (parent == &usb20_phy_clk) {
312 val &= ~CFGCHIP2_USB1PHYCLKMUX;
313 } else if (parent == &usb_refclkin) {
314 val |= CFGCHIP2_USB1PHYCLKMUX;
315 } else {
316 pr_err("Bad parent on USB 1.1 PHY clock\n");
317 return -EINVAL;
318 }
319
320 writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
321
322 return 0;
323}
324
325static struct clk usb11_phy_clk = {
326 .name = "usb11_phy",
327 .set_parent = usb11_phy_clk_set_parent,
328};
329
330static struct clk_lookup usb11_phy_clk_lookup =
331 CLK("da8xx-usb-phy", "usb11_phy", &usb11_phy_clk);
332
333/**
334 * da8xx_register_usb11_phy_clk - register USB1PHYCLKMUX clock
335 *
336 * @use_usb_refclkin: Selects the parent clock - either "usb_refclkin" if true
337 * or "usb20_phy" if false.
338 */
339int __init da8xx_register_usb11_phy_clk(bool use_usb_refclkin)
340{
341 struct clk *parent;
342 int ret = 0;
343
344 if (use_usb_refclkin)
345 parent = clk_get(NULL, "usb_refclkin");
346 else
347 parent = clk_get(&da8xx_usb_phy.dev, "usb20_phy");
348 if (IS_ERR(parent))
349 return PTR_ERR(parent);
350
351 usb11_phy_clk.parent = parent;
352 ret = clk_register(&usb11_phy_clk);
353 if (!ret)
354 clkdev_add(&usb11_phy_clk_lookup);
355
356 clk_put(parent);
357
358 return ret;
359}
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 9155b639c9aa..936c59d0e18b 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -557,7 +557,6 @@ config SOC_VF610
557 bool "Vybrid Family VF610 support" 557 bool "Vybrid Family VF610 support"
558 select ARM_GIC if ARCH_MULTI_V7 558 select ARM_GIC if ARCH_MULTI_V7
559 select PINCTRL_VF610 559 select PINCTRL_VF610
560 select PL310_ERRATA_769419 if CACHE_L2X0
561 560
562 help 561 help
563 This enables support for Freescale Vybrid VF610 processor. 562 This enables support for Freescale Vybrid VF610 processor.
diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c
index 58a2b88233e6..6cb8a22b617d 100644
--- a/arch/arm/mach-imx/mach-imx6ul.c
+++ b/arch/arm/mach-imx/mach-imx6ul.c
@@ -89,6 +89,7 @@ static void __init imx6ul_init_late(void)
89 89
90static const char * const imx6ul_dt_compat[] __initconst = { 90static const char * const imx6ul_dt_compat[] __initconst = {
91 "fsl,imx6ul", 91 "fsl,imx6ul",
92 "fsl,imx6ull",
92 NULL, 93 NULL,
93}; 94};
94 95
diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c
index db9621c718ec..ba96bf979625 100644
--- a/arch/arm/mach-imx/mmdc.c
+++ b/arch/arm/mach-imx/mmdc.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. 2 * Copyright 2011,2016 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd. 3 * Copyright 2011 Linaro Ltd.
4 * 4 *
5 * The code contained herein is licensed under the GNU General Public 5 * The code contained herein is licensed under the GNU General Public
@@ -10,12 +10,16 @@
10 * http://www.gnu.org/copyleft/gpl.html 10 * http://www.gnu.org/copyleft/gpl.html
11 */ 11 */
12 12
13#include <linux/hrtimer.h>
13#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/interrupt.h>
14#include <linux/io.h> 16#include <linux/io.h>
15#include <linux/module.h> 17#include <linux/module.h>
16#include <linux/of.h> 18#include <linux/of.h>
17#include <linux/of_address.h> 19#include <linux/of_address.h>
18#include <linux/of_device.h> 20#include <linux/of_device.h>
21#include <linux/perf_event.h>
22#include <linux/slab.h>
19 23
20#include "common.h" 24#include "common.h"
21 25
@@ -27,8 +31,489 @@
27#define BM_MMDC_MDMISC_DDR_TYPE 0x18 31#define BM_MMDC_MDMISC_DDR_TYPE 0x18
28#define BP_MMDC_MDMISC_DDR_TYPE 0x3 32#define BP_MMDC_MDMISC_DDR_TYPE 0x3
29 33
34#define TOTAL_CYCLES 0x0
35#define BUSY_CYCLES 0x1
36#define READ_ACCESSES 0x2
37#define WRITE_ACCESSES 0x3
38#define READ_BYTES 0x4
39#define WRITE_BYTES 0x5
40
41/* Enables, resets, freezes, overflow profiling*/
42#define DBG_DIS 0x0
43#define DBG_EN 0x1
44#define DBG_RST 0x2
45#define PRF_FRZ 0x4
46#define CYC_OVF 0x8
47#define PROFILE_SEL 0x10
48
49#define MMDC_MADPCR0 0x410
50#define MMDC_MADPSR0 0x418
51#define MMDC_MADPSR1 0x41C
52#define MMDC_MADPSR2 0x420
53#define MMDC_MADPSR3 0x424
54#define MMDC_MADPSR4 0x428
55#define MMDC_MADPSR5 0x42C
56
57#define MMDC_NUM_COUNTERS 6
58
59#define MMDC_FLAG_PROFILE_SEL 0x1
60
61#define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu)
62
30static int ddr_type; 63static int ddr_type;
31 64
65struct fsl_mmdc_devtype_data {
66 unsigned int flags;
67};
68
69static const struct fsl_mmdc_devtype_data imx6q_data = {
70};
71
72static const struct fsl_mmdc_devtype_data imx6qp_data = {
73 .flags = MMDC_FLAG_PROFILE_SEL,
74};
75
76static const struct of_device_id imx_mmdc_dt_ids[] = {
77 { .compatible = "fsl,imx6q-mmdc", .data = (void *)&imx6q_data},
78 { .compatible = "fsl,imx6qp-mmdc", .data = (void *)&imx6qp_data},
79 { /* sentinel */ }
80};
81
82#ifdef CONFIG_PERF_EVENTS
83
84static DEFINE_IDA(mmdc_ida);
85
86PMU_EVENT_ATTR_STRING(total-cycles, mmdc_pmu_total_cycles, "event=0x00")
87PMU_EVENT_ATTR_STRING(busy-cycles, mmdc_pmu_busy_cycles, "event=0x01")
88PMU_EVENT_ATTR_STRING(read-accesses, mmdc_pmu_read_accesses, "event=0x02")
89PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "config=0x03")
90PMU_EVENT_ATTR_STRING(read-bytes, mmdc_pmu_read_bytes, "event=0x04")
91PMU_EVENT_ATTR_STRING(read-bytes.unit, mmdc_pmu_read_bytes_unit, "MB");
92PMU_EVENT_ATTR_STRING(read-bytes.scale, mmdc_pmu_read_bytes_scale, "0.000001");
93PMU_EVENT_ATTR_STRING(write-bytes, mmdc_pmu_write_bytes, "event=0x05")
94PMU_EVENT_ATTR_STRING(write-bytes.unit, mmdc_pmu_write_bytes_unit, "MB");
95PMU_EVENT_ATTR_STRING(write-bytes.scale, mmdc_pmu_write_bytes_scale, "0.000001");
96
97struct mmdc_pmu {
98 struct pmu pmu;
99 void __iomem *mmdc_base;
100 cpumask_t cpu;
101 struct hrtimer hrtimer;
102 unsigned int active_events;
103 struct device *dev;
104 struct perf_event *mmdc_events[MMDC_NUM_COUNTERS];
105 struct hlist_node node;
106 struct fsl_mmdc_devtype_data *devtype_data;
107};
108
109/*
110 * Polling period is set to one second, overflow of total-cycles (the fastest
111 * increasing counter) takes ten seconds so one second is safe
112 */
113static unsigned int mmdc_pmu_poll_period_us = 1000000;
114
115module_param_named(pmu_pmu_poll_period_us, mmdc_pmu_poll_period_us, uint,
116 S_IRUGO | S_IWUSR);
117
118static ktime_t mmdc_pmu_timer_period(void)
119{
120 return ns_to_ktime((u64)mmdc_pmu_poll_period_us * 1000);
121}
122
123static ssize_t mmdc_pmu_cpumask_show(struct device *dev,
124 struct device_attribute *attr, char *buf)
125{
126 struct mmdc_pmu *pmu_mmdc = dev_get_drvdata(dev);
127
128 return cpumap_print_to_pagebuf(true, buf, &pmu_mmdc->cpu);
129}
130
131static struct device_attribute mmdc_pmu_cpumask_attr =
132 __ATTR(cpumask, S_IRUGO, mmdc_pmu_cpumask_show, NULL);
133
134static struct attribute *mmdc_pmu_cpumask_attrs[] = {
135 &mmdc_pmu_cpumask_attr.attr,
136 NULL,
137};
138
139static struct attribute_group mmdc_pmu_cpumask_attr_group = {
140 .attrs = mmdc_pmu_cpumask_attrs,
141};
142
143static struct attribute *mmdc_pmu_events_attrs[] = {
144 &mmdc_pmu_total_cycles.attr.attr,
145 &mmdc_pmu_busy_cycles.attr.attr,
146 &mmdc_pmu_read_accesses.attr.attr,
147 &mmdc_pmu_write_accesses.attr.attr,
148 &mmdc_pmu_read_bytes.attr.attr,
149 &mmdc_pmu_read_bytes_unit.attr.attr,
150 &mmdc_pmu_read_bytes_scale.attr.attr,
151 &mmdc_pmu_write_bytes.attr.attr,
152 &mmdc_pmu_write_bytes_unit.attr.attr,
153 &mmdc_pmu_write_bytes_scale.attr.attr,
154 NULL,
155};
156
157static struct attribute_group mmdc_pmu_events_attr_group = {
158 .name = "events",
159 .attrs = mmdc_pmu_events_attrs,
160};
161
162PMU_FORMAT_ATTR(event, "config:0-63");
163static struct attribute *mmdc_pmu_format_attrs[] = {
164 &format_attr_event.attr,
165 NULL,
166};
167
168static struct attribute_group mmdc_pmu_format_attr_group = {
169 .name = "format",
170 .attrs = mmdc_pmu_format_attrs,
171};
172
173static const struct attribute_group *attr_groups[] = {
174 &mmdc_pmu_events_attr_group,
175 &mmdc_pmu_format_attr_group,
176 &mmdc_pmu_cpumask_attr_group,
177 NULL,
178};
179
180static u32 mmdc_pmu_read_counter(struct mmdc_pmu *pmu_mmdc, int cfg)
181{
182 void __iomem *mmdc_base, *reg;
183
184 mmdc_base = pmu_mmdc->mmdc_base;
185
186 switch (cfg) {
187 case TOTAL_CYCLES:
188 reg = mmdc_base + MMDC_MADPSR0;
189 break;
190 case BUSY_CYCLES:
191 reg = mmdc_base + MMDC_MADPSR1;
192 break;
193 case READ_ACCESSES:
194 reg = mmdc_base + MMDC_MADPSR2;
195 break;
196 case WRITE_ACCESSES:
197 reg = mmdc_base + MMDC_MADPSR3;
198 break;
199 case READ_BYTES:
200 reg = mmdc_base + MMDC_MADPSR4;
201 break;
202 case WRITE_BYTES:
203 reg = mmdc_base + MMDC_MADPSR5;
204 break;
205 default:
206 return WARN_ONCE(1,
207 "invalid configuration %d for mmdc counter", cfg);
208 }
209 return readl(reg);
210}
211
212static int mmdc_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
213{
214 struct mmdc_pmu *pmu_mmdc = hlist_entry_safe(node, struct mmdc_pmu, node);
215 int target;
216
217 if (!cpumask_test_and_clear_cpu(cpu, &pmu_mmdc->cpu))
218 return 0;
219
220 target = cpumask_any_but(cpu_online_mask, cpu);
221 if (target >= nr_cpu_ids)
222 return 0;
223
224 perf_pmu_migrate_context(&pmu_mmdc->pmu, cpu, target);
225 cpumask_set_cpu(target, &pmu_mmdc->cpu);
226
227 return 0;
228}
229
230static bool mmdc_pmu_group_event_is_valid(struct perf_event *event,
231 struct pmu *pmu,
232 unsigned long *used_counters)
233{
234 int cfg = event->attr.config;
235
236 if (is_software_event(event))
237 return true;
238
239 if (event->pmu != pmu)
240 return false;
241
242 return !test_and_set_bit(cfg, used_counters);
243}
244
245/*
246 * Each event has a single fixed-purpose counter, so we can only have a
247 * single active event for each at any point in time. Here we just check
248 * for duplicates, and rely on mmdc_pmu_event_init to verify that the HW
249 * event numbers are valid.
250 */
251static bool mmdc_pmu_group_is_valid(struct perf_event *event)
252{
253 struct pmu *pmu = event->pmu;
254 struct perf_event *leader = event->group_leader;
255 struct perf_event *sibling;
256 unsigned long counter_mask = 0;
257
258 set_bit(leader->attr.config, &counter_mask);
259
260 if (event != leader) {
261 if (!mmdc_pmu_group_event_is_valid(event, pmu, &counter_mask))
262 return false;
263 }
264
265 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
266 if (!mmdc_pmu_group_event_is_valid(sibling, pmu, &counter_mask))
267 return false;
268 }
269
270 return true;
271}
272
273static int mmdc_pmu_event_init(struct perf_event *event)
274{
275 struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
276 int cfg = event->attr.config;
277
278 if (event->attr.type != event->pmu->type)
279 return -ENOENT;
280
281 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
282 return -EOPNOTSUPP;
283
284 if (event->cpu < 0) {
285 dev_warn(pmu_mmdc->dev, "Can't provide per-task data!\n");
286 return -EOPNOTSUPP;
287 }
288
289 if (event->attr.exclude_user ||
290 event->attr.exclude_kernel ||
291 event->attr.exclude_hv ||
292 event->attr.exclude_idle ||
293 event->attr.exclude_host ||
294 event->attr.exclude_guest ||
295 event->attr.sample_period)
296 return -EINVAL;
297
298 if (cfg < 0 || cfg >= MMDC_NUM_COUNTERS)
299 return -EINVAL;
300
301 if (!mmdc_pmu_group_is_valid(event))
302 return -EINVAL;
303
304 event->cpu = cpumask_first(&pmu_mmdc->cpu);
305 return 0;
306}
307
308static void mmdc_pmu_event_update(struct perf_event *event)
309{
310 struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
311 struct hw_perf_event *hwc = &event->hw;
312 u64 delta, prev_raw_count, new_raw_count;
313
314 do {
315 prev_raw_count = local64_read(&hwc->prev_count);
316 new_raw_count = mmdc_pmu_read_counter(pmu_mmdc,
317 event->attr.config);
318 } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
319 new_raw_count) != prev_raw_count);
320
321 delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF;
322
323 local64_add(delta, &event->count);
324}
325
326static void mmdc_pmu_event_start(struct perf_event *event, int flags)
327{
328 struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
329 struct hw_perf_event *hwc = &event->hw;
330 void __iomem *mmdc_base, *reg;
331 u32 val;
332
333 mmdc_base = pmu_mmdc->mmdc_base;
334 reg = mmdc_base + MMDC_MADPCR0;
335
336 /*
337 * hrtimer is required because mmdc does not provide an interrupt so
338 * polling is necessary
339 */
340 hrtimer_start(&pmu_mmdc->hrtimer, mmdc_pmu_timer_period(),
341 HRTIMER_MODE_REL_PINNED);
342
343 local64_set(&hwc->prev_count, 0);
344
345 writel(DBG_RST, reg);
346
347 val = DBG_EN;
348 if (pmu_mmdc->devtype_data->flags & MMDC_FLAG_PROFILE_SEL)
349 val |= PROFILE_SEL;
350
351 writel(val, reg);
352}
353
354static int mmdc_pmu_event_add(struct perf_event *event, int flags)
355{
356 struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
357 struct hw_perf_event *hwc = &event->hw;
358
359 int cfg = event->attr.config;
360
361 if (flags & PERF_EF_START)
362 mmdc_pmu_event_start(event, flags);
363
364 if (pmu_mmdc->mmdc_events[cfg] != NULL)
365 return -EAGAIN;
366
367 pmu_mmdc->mmdc_events[cfg] = event;
368 pmu_mmdc->active_events++;
369
370 local64_set(&hwc->prev_count, mmdc_pmu_read_counter(pmu_mmdc, cfg));
371
372 return 0;
373}
374
375static void mmdc_pmu_event_stop(struct perf_event *event, int flags)
376{
377 struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
378 void __iomem *mmdc_base, *reg;
379
380 mmdc_base = pmu_mmdc->mmdc_base;
381 reg = mmdc_base + MMDC_MADPCR0;
382
383 writel(PRF_FRZ, reg);
384 mmdc_pmu_event_update(event);
385}
386
387static void mmdc_pmu_event_del(struct perf_event *event, int flags)
388{
389 struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu);
390 int cfg = event->attr.config;
391
392 pmu_mmdc->mmdc_events[cfg] = NULL;
393 pmu_mmdc->active_events--;
394
395 if (pmu_mmdc->active_events == 0)
396 hrtimer_cancel(&pmu_mmdc->hrtimer);
397
398 mmdc_pmu_event_stop(event, PERF_EF_UPDATE);
399}
400
401static void mmdc_pmu_overflow_handler(struct mmdc_pmu *pmu_mmdc)
402{
403 int i;
404
405 for (i = 0; i < MMDC_NUM_COUNTERS; i++) {
406 struct perf_event *event = pmu_mmdc->mmdc_events[i];
407
408 if (event)
409 mmdc_pmu_event_update(event);
410 }
411}
412
413static enum hrtimer_restart mmdc_pmu_timer_handler(struct hrtimer *hrtimer)
414{
415 struct mmdc_pmu *pmu_mmdc = container_of(hrtimer, struct mmdc_pmu,
416 hrtimer);
417
418 mmdc_pmu_overflow_handler(pmu_mmdc);
419 hrtimer_forward_now(hrtimer, mmdc_pmu_timer_period());
420
421 return HRTIMER_RESTART;
422}
423
424static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc,
425 void __iomem *mmdc_base, struct device *dev)
426{
427 int mmdc_num;
428
429 *pmu_mmdc = (struct mmdc_pmu) {
430 .pmu = (struct pmu) {
431 .task_ctx_nr = perf_invalid_context,
432 .attr_groups = attr_groups,
433 .event_init = mmdc_pmu_event_init,
434 .add = mmdc_pmu_event_add,
435 .del = mmdc_pmu_event_del,
436 .start = mmdc_pmu_event_start,
437 .stop = mmdc_pmu_event_stop,
438 .read = mmdc_pmu_event_update,
439 },
440 .mmdc_base = mmdc_base,
441 .dev = dev,
442 .active_events = 0,
443 };
444
445 mmdc_num = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL);
446
447 return mmdc_num;
448}
449
450static int imx_mmdc_remove(struct platform_device *pdev)
451{
452 struct mmdc_pmu *pmu_mmdc = platform_get_drvdata(pdev);
453
454 perf_pmu_unregister(&pmu_mmdc->pmu);
455 cpuhp_remove_state_nocalls(CPUHP_ONLINE);
456 kfree(pmu_mmdc);
457 return 0;
458}
459
460static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_base)
461{
462 struct mmdc_pmu *pmu_mmdc;
463 char *name;
464 int mmdc_num;
465 int ret;
466 const struct of_device_id *of_id =
467 of_match_device(imx_mmdc_dt_ids, &pdev->dev);
468
469 pmu_mmdc = kzalloc(sizeof(*pmu_mmdc), GFP_KERNEL);
470 if (!pmu_mmdc) {
471 pr_err("failed to allocate PMU device!\n");
472 return -ENOMEM;
473 }
474
475 mmdc_num = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev);
476 if (mmdc_num == 0)
477 name = "mmdc";
478 else
479 name = devm_kasprintf(&pdev->dev,
480 GFP_KERNEL, "mmdc%d", mmdc_num);
481
482 pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data;
483
484 hrtimer_init(&pmu_mmdc->hrtimer, CLOCK_MONOTONIC,
485 HRTIMER_MODE_REL);
486 pmu_mmdc->hrtimer.function = mmdc_pmu_timer_handler;
487
488 cpuhp_state_add_instance_nocalls(CPUHP_ONLINE,
489 &pmu_mmdc->node);
490 cpumask_set_cpu(smp_processor_id(), &pmu_mmdc->cpu);
491 ret = cpuhp_setup_state_multi(CPUHP_AP_NOTIFY_ONLINE,
492 "MMDC_ONLINE", NULL,
493 mmdc_pmu_offline_cpu);
494 if (ret) {
495 pr_err("cpuhp_setup_state_multi failure\n");
496 goto pmu_register_err;
497 }
498
499 ret = perf_pmu_register(&(pmu_mmdc->pmu), name, -1);
500 platform_set_drvdata(pdev, pmu_mmdc);
501 if (ret)
502 goto pmu_register_err;
503 return 0;
504
505pmu_register_err:
506 pr_warn("MMDC Perf PMU failed (%d), disabled\n", ret);
507 hrtimer_cancel(&pmu_mmdc->hrtimer);
508 kfree(pmu_mmdc);
509 return ret;
510}
511
512#else
513#define imx_mmdc_remove NULL
514#define imx_mmdc_perf_init(pdev, mmdc_base) 0
515#endif
516
32static int imx_mmdc_probe(struct platform_device *pdev) 517static int imx_mmdc_probe(struct platform_device *pdev)
33{ 518{
34 struct device_node *np = pdev->dev.of_node; 519 struct device_node *np = pdev->dev.of_node;
@@ -62,7 +547,7 @@ static int imx_mmdc_probe(struct platform_device *pdev)
62 return -EBUSY; 547 return -EBUSY;
63 } 548 }
64 549
65 return 0; 550 return imx_mmdc_perf_init(pdev, mmdc_base);
66} 551}
67 552
68int imx_mmdc_get_ddr_type(void) 553int imx_mmdc_get_ddr_type(void)
@@ -70,17 +555,13 @@ int imx_mmdc_get_ddr_type(void)
70 return ddr_type; 555 return ddr_type;
71} 556}
72 557
73static const struct of_device_id imx_mmdc_dt_ids[] = {
74 { .compatible = "fsl,imx6q-mmdc", },
75 { /* sentinel */ }
76};
77
78static struct platform_driver imx_mmdc_driver = { 558static struct platform_driver imx_mmdc_driver = {
79 .driver = { 559 .driver = {
80 .name = "imx-mmdc", 560 .name = "imx-mmdc",
81 .of_match_table = imx_mmdc_dt_ids, 561 .of_match_table = imx_mmdc_dt_ids,
82 }, 562 },
83 .probe = imx_mmdc_probe, 563 .probe = imx_mmdc_probe,
564 .remove = imx_mmdc_remove,
84}; 565};
85 566
86static int __init imx_mmdc_init(void) 567static int __init imx_mmdc_init(void)
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 23b98fd414bf..a1af634f8709 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -27,6 +27,8 @@
27#include <linux/of_address.h> 27#include <linux/of_address.h>
28#include <linux/of_platform.h> 28#include <linux/of_platform.h>
29#include <linux/termios.h> 29#include <linux/termios.h>
30#include <linux/mfd/syscon.h>
31#include <linux/regmap.h>
30 32
31#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
32#include <asm/mach/map.h> 34#include <asm/mach/map.h>
@@ -37,11 +39,8 @@
37#include "pci_v3.h" 39#include "pci_v3.h"
38#include "lm.h" 40#include "lm.h"
39 41
40/* Base address to the AP system controller */ 42/* Regmap to the AP system controller */
41void __iomem *ap_syscon_base; 43static struct regmap *ap_syscon_map;
42/* Base address to the external bus interface */
43static void __iomem *ebi_base;
44
45 44
46/* 45/*
47 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx 46 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
@@ -125,6 +124,7 @@ static void integrator_uart_set_mctrl(struct amba_device *dev,
125{ 124{
126 unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask; 125 unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
127 u32 phybase = dev->res.start; 126 u32 phybase = dev->res.start;
127 int ret;
128 128
129 if (phybase == INTEGRATOR_UART0_BASE) { 129 if (phybase == INTEGRATOR_UART0_BASE) {
130 /* UART0 */ 130 /* UART0 */
@@ -146,8 +146,17 @@ static void integrator_uart_set_mctrl(struct amba_device *dev,
146 else 146 else
147 ctrls |= dtr_mask; 147 ctrls |= dtr_mask;
148 148
149 __raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET); 149 ret = regmap_write(ap_syscon_map,
150 __raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET); 150 INTEGRATOR_SC_CTRLS_OFFSET,
151 ctrls);
152 if (ret)
153 pr_err("MODEM: unable to write PL010 UART CTRLS\n");
154
155 ret = regmap_write(ap_syscon_map,
156 INTEGRATOR_SC_CTRLC_OFFSET,
157 ctrlc);
158 if (ret)
159 pr_err("MODEM: unable to write PL010 UART CRTLC\n");
151} 160}
152 161
153struct amba_pl010_data ap_uart_data = { 162struct amba_pl010_data ap_uart_data = {
@@ -178,35 +187,32 @@ static const struct of_device_id ap_syscon_match[] = {
178 { }, 187 { },
179}; 188};
180 189
181static const struct of_device_id ebi_match[] = {
182 { .compatible = "arm,external-bus-interface"},
183 { },
184};
185
186static void __init ap_init_of(void) 190static void __init ap_init_of(void)
187{ 191{
188 unsigned long sc_dec; 192 u32 sc_dec;
189 struct device_node *syscon; 193 struct device_node *syscon;
190 struct device_node *ebi; 194 int ret;
191 int i; 195 int i;
192 196
197 of_platform_default_populate(NULL, ap_auxdata_lookup, NULL);
198
193 syscon = of_find_matching_node(NULL, ap_syscon_match); 199 syscon = of_find_matching_node(NULL, ap_syscon_match);
194 if (!syscon) 200 if (!syscon)
195 return; 201 return;
196 ebi = of_find_matching_node(NULL, ebi_match); 202 ap_syscon_map = syscon_node_to_regmap(syscon);
197 if (!ebi) 203 if (IS_ERR(ap_syscon_map)) {
204 pr_crit("could not find Integrator/AP system controller\n");
198 return; 205 return;
206 }
199 207
200 ap_syscon_base = of_iomap(syscon, 0); 208 ret = regmap_read(ap_syscon_map,
201 if (!ap_syscon_base) 209 INTEGRATOR_SC_DEC_OFFSET,
202 return; 210 &sc_dec);
203 ebi_base = of_iomap(ebi, 0); 211 if (ret) {
204 if (!ebi_base) 212 pr_crit("could not read from Integrator/AP syscon\n");
205 return; 213 return;
214 }
206 215
207 of_platform_default_populate(NULL, ap_auxdata_lookup, NULL);
208
209 sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
210 for (i = 0; i < 4; i++) { 216 for (i = 0; i < 4; i++) {
211 struct lm_device *lmdev; 217 struct lm_device *lmdev;
212 218
diff --git a/arch/arm/mach-lpc32xx/clock.h b/arch/arm/mach-lpc32xx/clock.h
deleted file mode 100644
index c0a8434307f7..000000000000
--- a/arch/arm/mach-lpc32xx/clock.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * arch/arm/mach-lpc32xx/clock.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __LPC32XX_CLOCK_H
20#define __LPC32XX_CLOCK_H
21
22struct clk {
23 struct list_head node;
24 struct clk *parent;
25 u32 rate;
26 u32 usecount;
27
28 int (*set_rate) (struct clk *, unsigned long);
29 unsigned long (*round_rate) (struct clk *, unsigned long);
30 unsigned long (*get_rate) (struct clk *clk);
31 int (*enable) (struct clk *, int);
32
33 /* Register address and bit mask for simple clocks */
34 void __iomem *enable_reg;
35 u32 enable_mask;
36};
37
38#endif
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index 30c9e64fc65b..02575c2444e4 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -24,7 +24,6 @@
24/* 24/*
25 * Other arch specific structures and functions 25 * Other arch specific structures and functions
26 */ 26 */
27extern void __init lpc32xx_init_irq(void);
28extern void __init lpc32xx_map_io(void); 27extern void __init lpc32xx_map_io(void);
29extern void __init lpc32xx_serial_init(void); 28extern void __init lpc32xx_serial_init(void);
30 29
diff --git a/arch/arm/mach-lpc32xx/include/mach/irqs.h b/arch/arm/mach-lpc32xx/include/mach/irqs.h
deleted file mode 100644
index 00190535df90..000000000000
--- a/arch/arm/mach-lpc32xx/include/mach/irqs.h
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/irqs.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARM_ARCH_IRQS_H
20#define __ASM_ARM_ARCH_IRQS_H
21
22#define LPC32XX_SIC1_IRQ(n) (32 + (n))
23#define LPC32XX_SIC2_IRQ(n) (64 + (n))
24
25/*
26 * MIC interrupts
27 */
28#define IRQ_LPC32XX_SUB1IRQ 0
29#define IRQ_LPC32XX_SUB2IRQ 1
30#define IRQ_LPC32XX_PWM3 3
31#define IRQ_LPC32XX_PWM4 4
32#define IRQ_LPC32XX_HSTIMER 5
33#define IRQ_LPC32XX_WATCH 6
34#define IRQ_LPC32XX_UART_IIR3 7
35#define IRQ_LPC32XX_UART_IIR4 8
36#define IRQ_LPC32XX_UART_IIR5 9
37#define IRQ_LPC32XX_UART_IIR6 10
38#define IRQ_LPC32XX_FLASH 11
39#define IRQ_LPC32XX_SD1 13
40#define IRQ_LPC32XX_LCD 14
41#define IRQ_LPC32XX_SD0 15
42#define IRQ_LPC32XX_TIMER0 16
43#define IRQ_LPC32XX_TIMER1 17
44#define IRQ_LPC32XX_TIMER2 18
45#define IRQ_LPC32XX_TIMER3 19
46#define IRQ_LPC32XX_SSP0 20
47#define IRQ_LPC32XX_SSP1 21
48#define IRQ_LPC32XX_I2S0 22
49#define IRQ_LPC32XX_I2S1 23
50#define IRQ_LPC32XX_UART_IIR7 24
51#define IRQ_LPC32XX_UART_IIR2 25
52#define IRQ_LPC32XX_UART_IIR1 26
53#define IRQ_LPC32XX_MSTIMER 27
54#define IRQ_LPC32XX_DMA 28
55#define IRQ_LPC32XX_ETHERNET 29
56#define IRQ_LPC32XX_SUB1FIQ 30
57#define IRQ_LPC32XX_SUB2FIQ 31
58
59/*
60 * SIC1 interrupts start at offset 32
61 */
62#define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1)
63#define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2)
64#define IRQ_LPC32XX_GPI_28 LPC32XX_SIC1_IRQ(4)
65#define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6)
66#define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7)
67#define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8)
68#define IRQ_LPC32XX_SPI2 LPC32XX_SIC1_IRQ(12)
69#define IRQ_LPC32XX_PLLUSB LPC32XX_SIC1_IRQ(13)
70#define IRQ_LPC32XX_PLLHCLK LPC32XX_SIC1_IRQ(14)
71#define IRQ_LPC32XX_PLL397 LPC32XX_SIC1_IRQ(17)
72#define IRQ_LPC32XX_I2C_2 LPC32XX_SIC1_IRQ(18)
73#define IRQ_LPC32XX_I2C_1 LPC32XX_SIC1_IRQ(19)
74#define IRQ_LPC32XX_RTC LPC32XX_SIC1_IRQ(20)
75#define IRQ_LPC32XX_KEY LPC32XX_SIC1_IRQ(22)
76#define IRQ_LPC32XX_SPI1 LPC32XX_SIC1_IRQ(23)
77#define IRQ_LPC32XX_SW LPC32XX_SIC1_IRQ(24)
78#define IRQ_LPC32XX_USB_OTG_TIMER LPC32XX_SIC1_IRQ(25)
79#define IRQ_LPC32XX_USB_OTG_ATX LPC32XX_SIC1_IRQ(26)
80#define IRQ_LPC32XX_USB_HOST LPC32XX_SIC1_IRQ(27)
81#define IRQ_LPC32XX_USB_DEV_DMA LPC32XX_SIC1_IRQ(28)
82#define IRQ_LPC32XX_USB_DEV_LP LPC32XX_SIC1_IRQ(29)
83#define IRQ_LPC32XX_USB_DEV_HP LPC32XX_SIC1_IRQ(30)
84#define IRQ_LPC32XX_USB_I2C LPC32XX_SIC1_IRQ(31)
85
86/*
87 * SIC2 interrupts start at offset 64
88 */
89#define IRQ_LPC32XX_GPIO_00 LPC32XX_SIC2_IRQ(0)
90#define IRQ_LPC32XX_GPIO_01 LPC32XX_SIC2_IRQ(1)
91#define IRQ_LPC32XX_GPIO_02 LPC32XX_SIC2_IRQ(2)
92#define IRQ_LPC32XX_GPIO_03 LPC32XX_SIC2_IRQ(3)
93#define IRQ_LPC32XX_GPIO_04 LPC32XX_SIC2_IRQ(4)
94#define IRQ_LPC32XX_GPIO_05 LPC32XX_SIC2_IRQ(5)
95#define IRQ_LPC32XX_SPI2_DATAIN LPC32XX_SIC2_IRQ(6)
96#define IRQ_LPC32XX_U2_HCTS LPC32XX_SIC2_IRQ(7)
97#define IRQ_LPC32XX_P0_P1_IRQ LPC32XX_SIC2_IRQ(8)
98#define IRQ_LPC32XX_GPI_08 LPC32XX_SIC2_IRQ(9)
99#define IRQ_LPC32XX_GPI_09 LPC32XX_SIC2_IRQ(10)
100#define IRQ_LPC32XX_GPI_19 LPC32XX_SIC2_IRQ(11)
101#define IRQ_LPC32XX_U7_HCTS LPC32XX_SIC2_IRQ(12)
102#define IRQ_LPC32XX_GPI_07 LPC32XX_SIC2_IRQ(15)
103#define IRQ_LPC32XX_SDIO LPC32XX_SIC2_IRQ(18)
104#define IRQ_LPC32XX_U5_RX LPC32XX_SIC2_IRQ(19)
105#define IRQ_LPC32XX_SPI1_DATAIN LPC32XX_SIC2_IRQ(20)
106#define IRQ_LPC32XX_GPI_00 LPC32XX_SIC2_IRQ(22)
107#define IRQ_LPC32XX_GPI_01 LPC32XX_SIC2_IRQ(23)
108#define IRQ_LPC32XX_GPI_02 LPC32XX_SIC2_IRQ(24)
109#define IRQ_LPC32XX_GPI_03 LPC32XX_SIC2_IRQ(25)
110#define IRQ_LPC32XX_GPI_04 LPC32XX_SIC2_IRQ(26)
111#define IRQ_LPC32XX_GPI_05 LPC32XX_SIC2_IRQ(27)
112#define IRQ_LPC32XX_GPI_06 LPC32XX_SIC2_IRQ(28)
113#define IRQ_LPC32XX_SYSCLK LPC32XX_SIC2_IRQ(31)
114
115#define LPC32XX_NR_IRQS 96
116
117#endif
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
index 207e81275ff0..62471570d586 100644
--- a/arch/arm/mach-lpc32xx/pm.c
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -73,7 +73,6 @@
73#include <mach/hardware.h> 73#include <mach/hardware.h>
74#include <mach/platform.h> 74#include <mach/platform.h>
75#include "common.h" 75#include "common.h"
76#include "clock.h"
77 76
78#define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE) 77#define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE)
79 78
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index 21164605b83f..dadae67d79b7 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -1,4 +1,2 @@
1ifeq ($(CONFIG_SMP),y) 1obj-$(CONFIG_SMP) += platsmp.o
2obj-$(CONFIG_ARCH_MEDIATEK) += platsmp.o 2obj-y += mediatek.o
3endif
4obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index afb809509140..45c6b733c881 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -31,6 +31,32 @@ config ARCH_OMAP16XX
31 select ARCH_OMAP_OTG 31 select ARCH_OMAP_OTG
32 select CPU_ARM926T 32 select CPU_ARM926T
33 33
34config OMAP_MUX
35 bool "OMAP multiplexing support"
36 depends on ARCH_OMAP
37 default y
38 help
39 Pin multiplexing support for OMAP boards. If your bootloader
40 sets the multiplexing correctly, say N. Otherwise, or if unsure,
41 say Y.
42
43config OMAP_MUX_DEBUG
44 bool "Multiplexing debug output"
45 depends on OMAP_MUX
46 help
47 Makes the multiplexing functions print out a lot of debug info.
48 This is useful if you want to find out the correct values of the
49 multiplexing registers.
50
51config OMAP_MUX_WARNINGS
52 bool "Warn about pins the bootloader didn't set up"
53 depends on OMAP_MUX
54 default y
55 help
56 Choose Y here to warn whenever driver initialization logic needs
57 to change the pin multiplexing setup. When there are no warnings
58 printed, it's safe to deselect OMAP_MUX for your product.
59
34comment "OMAP Board Type" 60comment "OMAP Board Type"
35 depends on ARCH_OMAP1 61 depends on ARCH_OMAP1
36 62
diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c
index 82887d645a6a..32f6c53367bf 100644
--- a/arch/arm/mach-omap1/i2c.c
+++ b/arch/arm/mach-omap1/i2c.c
@@ -19,6 +19,7 @@
19 * 19 *
20 */ 20 */
21 21
22#include <linux/i2c.h>
22#include <linux/i2c-omap.h> 23#include <linux/i2c-omap.h>
23#include <mach/mux.h> 24#include <mach/mux.h>
24#include "soc.h" 25#include "soc.h"
@@ -91,6 +92,88 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *pdata,
91 return platform_device_register(pdev); 92 return platform_device_register(pdev);
92} 93}
93 94
95#define OMAP_I2C_MAX_CONTROLLERS 4
96static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS];
97
98#define OMAP_I2C_CMDLINE_SETUP (BIT(31))
99
100/**
101 * omap_i2c_bus_setup - Process command line options for the I2C bus speed
102 * @str: String of options
103 *
104 * This function allow to override the default I2C bus speed for given I2C
105 * bus with a command line option.
106 *
107 * Format: i2c_bus=bus_id,clkrate (in kHz)
108 *
109 * Returns 1 on success, 0 otherwise.
110 */
111static int __init omap_i2c_bus_setup(char *str)
112{
113 int ints[3];
114
115 get_options(str, 3, ints);
116 if (ints[0] < 2 || ints[1] < 1 ||
117 ints[1] > OMAP_I2C_MAX_CONTROLLERS)
118 return 0;
119 i2c_pdata[ints[1] - 1].clkrate = ints[2];
120 i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP;
121
122 return 1;
123}
124__setup("i2c_bus=", omap_i2c_bus_setup);
125
126/*
127 * Register busses defined in command line but that are not registered with
128 * omap_register_i2c_bus from board initialization code.
129 */
130int __init omap_register_i2c_bus_cmdline(void)
131{
132 int i, err = 0;
133
134 for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++)
135 if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) {
136 i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
137 err = omap_i2c_add_bus(&i2c_pdata[i], i + 1);
138 if (err)
139 goto out;
140 }
141
142out:
143 return err;
144}
145
146/**
147 * omap_register_i2c_bus - register I2C bus with device descriptors
148 * @bus_id: bus id counting from number 1
149 * @clkrate: clock rate of the bus in kHz
150 * @info: pointer into I2C device descriptor table or NULL
151 * @len: number of descriptors in the table
152 *
153 * Returns 0 on success or an error code.
154 */
155int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
156 struct i2c_board_info const *info,
157 unsigned len)
158{
159 int err;
160
161 BUG_ON(bus_id < 1 || bus_id > OMAP_I2C_MAX_CONTROLLERS);
162
163 if (info) {
164 err = i2c_register_board_info(bus_id, info, len);
165 if (err)
166 return err;
167 }
168
169 if (!i2c_pdata[bus_id - 1].clkrate)
170 i2c_pdata[bus_id - 1].clkrate = clkrate;
171
172 i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
173
174 return omap_i2c_add_bus(&i2c_pdata[bus_id - 1], bus_id);
175}
176
94static int __init omap_i2c_cmdline(void) 177static int __init omap_i2c_cmdline(void)
95{ 178{
96 return omap_register_i2c_bus_cmdline(); 179 return omap_register_i2c_bus_cmdline();
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 5b37ec29996e..469894082fea 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -6,7 +6,7 @@ ccflags-y := -I$(srctree)/$(src)/include \
6 -I$(srctree)/arch/arm/plat-omap/include 6 -I$(srctree)/arch/arm/plat-omap/include
7 7
8# Common support 8# Common support
9obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o timer.o pm.o \ 9obj-y := id.o io.o control.o devices.o fb.o timer.o pm.o \
10 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \ 10 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
11 omap_device.o omap-headsmp.o sram.o drm.o 11 omap_device.o omap-headsmp.o sram.o drm.o
12 12
@@ -63,9 +63,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o
63obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o 63obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
64obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o 64obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o
65 65
66# Pin multiplexing
67obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
68
69# SMS/SDRC 66# SMS/SDRC
70obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o 67obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
71# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o 68# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o
@@ -80,7 +77,7 @@ endif
80# Power Management 77# Power Management
81omap-4-5-pm-common = omap-mpuss-lowpower.o 78omap-4-5-pm-common = omap-mpuss-lowpower.o
82obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common) 79obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common)
83obj-$(CONFIG_ARCH_OMAP5) += $(omap-4-5-pm-common) 80obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-pm-common)
84obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o 81obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
85 82
86ifeq ($(CONFIG_PM),y) 83ifeq ($(CONFIG_PM),y)
@@ -235,26 +232,15 @@ obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
235 232
236# Platform specific device init code 233# Platform specific device init code
237 234
238omap-flash-$(CONFIG_MTD_NAND_OMAP2) := board-flash.o
239omap-flash-$(CONFIG_MTD_ONENAND_OMAP2) := board-flash.o
240obj-y += $(omap-flash-y) $(omap-flash-m)
241
242omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o 235omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o
243obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y) 236obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y)
244 237
245obj-y += usb-musb.o
246obj-y += omap_phy_internal.o 238obj-y += omap_phy_internal.o
247 239
248obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o 240obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o
249obj-y += usb-host.o
250 241
251onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o 242onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o
252obj-y += $(onenand-m) $(onenand-y) 243obj-y += $(onenand-m) $(onenand-y)
253 244
254nand-$(CONFIG_MTD_NAND_OMAP2) := gpmc-nand.o 245nand-$(CONFIG_MTD_NAND_OMAP2) := gpmc-nand.o
255obj-y += $(nand-m) $(nand-y) 246obj-y += $(nand-m) $(nand-y)
256
257smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o
258obj-y += $(smsc911x-m) $(smsc911x-y)
259
260obj-y += common-board-devices.o twl-common.o dss-common.o
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
deleted file mode 100644
index 2188dc30e232..000000000000
--- a/arch/arm/mach-omap2/board-flash.c
+++ /dev/null
@@ -1,242 +0,0 @@
1/*
2 * board-flash.c
3 * Modified from mach-omap2/board-3430sdp-flash.c
4 *
5 * Copyright (C) 2009 Nokia Corporation
6 * Copyright (C) 2009 Texas Instruments
7 *
8 * Vimal Singh <vimalsingh@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/omap-gpmc.h>
17#include <linux/platform_device.h>
18#include <linux/mtd/physmap.h>
19#include <linux/io.h>
20
21#include <linux/platform_data/mtd-nand-omap2.h>
22#include <linux/platform_data/mtd-onenand-omap2.h>
23
24#include "soc.h"
25#include "common.h"
26#include "board-flash.h"
27
28#define REG_FPGA_REV 0x10
29#define REG_FPGA_DIP_SWITCH_INPUT2 0x60
30#define MAX_SUPPORTED_GPMC_CONFIG 3
31
32#define DEBUG_BASE 0x08000000 /* debug board */
33
34/* various memory sizes */
35#define FLASH_SIZE_SDPV1 SZ_64M /* NOR flash (64 Meg aligned) */
36#define FLASH_SIZE_SDPV2 SZ_128M /* NOR flash (256 Meg aligned) */
37
38static struct physmap_flash_data board_nor_data = {
39 .width = 2,
40};
41
42static struct resource board_nor_resource = {
43 .flags = IORESOURCE_MEM,
44};
45
46static struct platform_device board_nor_device = {
47 .name = "physmap-flash",
48 .id = 0,
49 .dev = {
50 .platform_data = &board_nor_data,
51 },
52 .num_resources = 1,
53 .resource = &board_nor_resource,
54};
55
56static void
57__init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
58{
59 int err;
60
61 board_nor_data.parts = nor_parts;
62 board_nor_data.nr_parts = nr_parts;
63
64 /* Configure start address and size of NOR device */
65 if (omap_rev() >= OMAP3430_REV_ES1_0) {
66 err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1,
67 (unsigned long *)&board_nor_resource.start);
68 board_nor_resource.end = board_nor_resource.start
69 + FLASH_SIZE_SDPV2 - 1;
70 } else {
71 err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1,
72 (unsigned long *)&board_nor_resource.start);
73 board_nor_resource.end = board_nor_resource.start
74 + FLASH_SIZE_SDPV1 - 1;
75 }
76 if (err < 0) {
77 pr_err("NOR: Can't request GPMC CS\n");
78 return;
79 }
80 if (platform_device_register(&board_nor_device) < 0)
81 pr_err("Unable to register NOR device\n");
82}
83
84#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
85static struct omap_onenand_platform_data board_onenand_data = {
86 .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */
87};
88
89void
90__init board_onenand_init(struct mtd_partition *onenand_parts,
91 u8 nr_parts, u8 cs)
92{
93 board_onenand_data.cs = cs;
94 board_onenand_data.parts = onenand_parts;
95 board_onenand_data.nr_parts = nr_parts;
96
97 gpmc_onenand_init(&board_onenand_data);
98}
99#endif /* IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2) */
100
101#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
102
103/* Note that all values in this struct are in nanoseconds */
104struct gpmc_timings nand_default_timings[1] = {
105 {
106 .sync_clk = 0,
107
108 .cs_on = 0,
109 .cs_rd_off = 36,
110 .cs_wr_off = 36,
111
112 .we_on = 6,
113 .oe_on = 6,
114
115 .adv_on = 6,
116 .adv_rd_off = 24,
117 .adv_wr_off = 36,
118
119 .we_off = 30,
120 .oe_off = 48,
121
122 .access = 54,
123 .rd_cycle = 72,
124 .wr_cycle = 72,
125
126 .wr_access = 30,
127 .wr_data_mux_bus = 0,
128 },
129};
130
131static struct omap_nand_platform_data board_nand_data;
132
133void
134__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
135 int nand_type, struct gpmc_timings *gpmc_t)
136{
137 board_nand_data.cs = cs;
138 board_nand_data.parts = nand_parts;
139 board_nand_data.nr_parts = nr_parts;
140 board_nand_data.devsize = nand_type;
141
142 board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_SW;
143 gpmc_nand_init(&board_nand_data, gpmc_t);
144}
145#endif /* IS_ENABLED(CONFIG_MTD_NAND_OMAP2) */
146
147/**
148 * get_gpmc0_type - Reads the FPGA DIP_SWITCH_INPUT_REGISTER2 to get
149 * the various cs values.
150 */
151static u8 get_gpmc0_type(void)
152{
153 u8 cs = 0;
154 void __iomem *fpga_map_addr;
155
156 fpga_map_addr = ioremap(DEBUG_BASE, 4096);
157 if (!fpga_map_addr)
158 return -ENOMEM;
159
160 if (!(readw_relaxed(fpga_map_addr + REG_FPGA_REV)))
161 /* we dont have an DEBUG FPGA??? */
162 /* Depend on #defines!! default to strata boot return param */
163 goto unmap;
164
165 /* S8-DIP-OFF = 1, S8-DIP-ON = 0 */
166 cs = readw_relaxed(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
167
168 /* ES2.0 SDP's onwards 4 dip switches are provided for CS */
169 if (omap_rev() >= OMAP3430_REV_ES1_0)
170 /* change (S8-1:4=DS-2:0) to (S8-4:1=DS-2:0) */
171 cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) |
172 ((cs & 2) << 1) | ((cs & 1) << 3);
173 else
174 /* change (S8-1:3=DS-2:0) to (S8-3:1=DS-2:0) */
175 cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2);
176unmap:
177 iounmap(fpga_map_addr);
178 return cs;
179}
180
181/**
182 * board_flash_init - Identify devices connected to GPMC and register.
183 *
184 * @return - void.
185 */
186void __init board_flash_init(struct flash_partitions partition_info[],
187 char chip_sel_board[][GPMC_CS_NUM], int nand_type)
188{
189 u8 cs = 0;
190 u8 norcs = GPMC_CS_NUM + 1;
191 u8 nandcs = GPMC_CS_NUM + 1;
192 u8 onenandcs = GPMC_CS_NUM + 1;
193 u8 idx;
194 unsigned char *config_sel = NULL;
195
196 /* REVISIT: Is this return correct idx for 2430 SDP?
197 * for which cs configuration matches for 2430 SDP?
198 */
199 idx = get_gpmc0_type();
200 if (idx >= MAX_SUPPORTED_GPMC_CONFIG) {
201 pr_err("%s: Invalid chip select: %d\n", __func__, cs);
202 return;
203 }
204 config_sel = (unsigned char *)(chip_sel_board[idx]);
205
206 while (cs < GPMC_CS_NUM) {
207 switch (config_sel[cs]) {
208 case PDC_NOR:
209 if (norcs > GPMC_CS_NUM)
210 norcs = cs;
211 break;
212 case PDC_NAND:
213 if (nandcs > GPMC_CS_NUM)
214 nandcs = cs;
215 break;
216 case PDC_ONENAND:
217 if (onenandcs > GPMC_CS_NUM)
218 onenandcs = cs;
219 break;
220 }
221 cs++;
222 }
223
224 if (norcs > GPMC_CS_NUM)
225 pr_err("NOR: Unable to find configuration in GPMC\n");
226 else
227 board_nor_init(partition_info[0].parts,
228 partition_info[0].nr_parts, norcs);
229
230 if (onenandcs > GPMC_CS_NUM)
231 pr_err("OneNAND: Unable to find configuration in GPMC\n");
232 else
233 board_onenand_init(partition_info[1].parts,
234 partition_info[1].nr_parts, onenandcs);
235
236 if (nandcs > GPMC_CS_NUM)
237 pr_err("NAND: Unable to find configuration in GPMC\n");
238 else
239 board_nand_init(partition_info[2].parts,
240 partition_info[2].nr_parts, nandcs,
241 nand_type, nand_default_timings);
242}
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
deleted file mode 100644
index 8b39eec07318..000000000000
--- a/arch/arm/mach-omap2/board-flash.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * board-sdp.h
3 *
4 * Information structures for SDP-specific board config data
5 *
6 * Copyright (C) 2009 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/mtd/mtd.h>
14#include <linux/mtd/partitions.h>
15
16#define PDC_NOR 1
17#define PDC_NAND 2
18#define PDC_ONENAND 3
19#define DBG_MPDB 4
20
21struct flash_partitions {
22 struct mtd_partition *parts;
23 int nr_parts;
24};
25
26#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2) || IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
27extern void board_flash_init(struct flash_partitions [],
28 char chip_sel[][GPMC_CS_NUM], int nand_type);
29#else
30static inline void board_flash_init(struct flash_partitions part[],
31 char chip_sel[][GPMC_CS_NUM], int nand_type)
32{
33}
34#endif
35
36#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
37extern void board_nand_init(struct mtd_partition *nand_parts,
38 u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t);
39extern struct gpmc_timings nand_default_timings[];
40#else
41static inline void board_nand_init(struct mtd_partition *nand_parts,
42 u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t)
43{
44}
45#define nand_default_timings NULL
46#endif
47
48#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
49extern void board_onenand_init(struct mtd_partition *nand_parts,
50 u8 nr_parts, u8 cs);
51#else
52static inline void board_onenand_init(struct mtd_partition *nand_parts,
53 u8 nr_parts, u8 cs)
54{
55}
56#endif
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index bab814d2f37d..981b23a39f29 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -341,6 +341,7 @@ static const char *const dra72x_boards_compat[] __initconst = {
341 "ti,am5718", 341 "ti,am5718",
342 "ti,am5716", 342 "ti,am5716",
343 "ti,dra722", 343 "ti,dra722",
344 "ti,dra718",
344 NULL, 345 NULL,
345}; 346};
346 347
diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c
index ef9ed36e8a61..6c679659cda5 100644
--- a/arch/arm/mach-omap2/clockdomains7xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains7xx_data.c
@@ -409,7 +409,7 @@ static struct clockdomain l4sec_7xx_clkdm = {
409 .dep_bit = DRA7XX_L4SEC_STATDEP_SHIFT, 409 .dep_bit = DRA7XX_L4SEC_STATDEP_SHIFT,
410 .wkdep_srcs = l4sec_wkup_sleep_deps, 410 .wkdep_srcs = l4sec_wkup_sleep_deps,
411 .sleepdep_srcs = l4sec_wkup_sleep_deps, 411 .sleepdep_srcs = l4sec_wkup_sleep_deps,
412 .flags = CLKDM_CAN_HWSUP_SWSUP, 412 .flags = CLKDM_CAN_SWSUP,
413}; 413};
414 414
415static struct clockdomain l3main1_7xx_clkdm = { 415static struct clockdomain l3main1_7xx_clkdm = {
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
deleted file mode 100644
index 5388fcd3de72..000000000000
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ /dev/null
@@ -1,102 +0,0 @@
1/*
2 * common-board-devices.c
3 *
4 * Copyright (C) 2011 CompuLab, Ltd.
5 * Author: Mike Rapoport <mike@compulab.co.il>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 */
22
23#include <linux/gpio.h>
24#include <linux/spi/spi.h>
25#include <linux/spi/ads7846.h>
26
27#include <linux/platform_data/spi-omap2-mcspi.h>
28
29#include "common.h"
30#include "common-board-devices.h"
31
32#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846)
33static struct omap2_mcspi_device_config ads7846_mcspi_config = {
34 .turbo_mode = 0,
35};
36
37static struct ads7846_platform_data ads7846_config = {
38 .x_max = 0x0fff,
39 .y_max = 0x0fff,
40 .x_plate_ohms = 180,
41 .pressure_max = 255,
42 .debounce_max = 10,
43 .debounce_tol = 3,
44 .debounce_rep = 1,
45 .gpio_pendown = -EINVAL,
46 .keep_vref_on = 1,
47};
48
49static struct spi_board_info ads7846_spi_board_info __initdata = {
50 .modalias = "ads7846",
51 .bus_num = -EINVAL,
52 .chip_select = 0,
53 .max_speed_hz = 1500000,
54 .controller_data = &ads7846_mcspi_config,
55 .irq = -EINVAL,
56 .platform_data = &ads7846_config,
57};
58
59void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
60 struct ads7846_platform_data *board_pdata)
61{
62 struct spi_board_info *spi_bi = &ads7846_spi_board_info;
63 int err;
64
65 /*
66 * If a board defines get_pendown_state() function, request the pendown
67 * GPIO and set the GPIO debounce time.
68 * If a board does not define the get_pendown_state() function, then
69 * the ads7846 driver will setup the pendown GPIO itself.
70 */
71 if (board_pdata && board_pdata->get_pendown_state) {
72 err = gpio_request_one(gpio_pendown, GPIOF_IN, "TSPenDown");
73 if (err) {
74 pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err);
75 return;
76 }
77
78 if (gpio_debounce)
79 gpio_set_debounce(gpio_pendown, gpio_debounce);
80
81 gpio_export(gpio_pendown, 0);
82 }
83
84 spi_bi->bus_num = bus_num;
85 spi_bi->irq = gpio_to_irq(gpio_pendown);
86
87 ads7846_config.gpio_pendown = gpio_pendown;
88
89 if (board_pdata) {
90 board_pdata->gpio_pendown = gpio_pendown;
91 board_pdata->gpio_pendown_debounce = gpio_debounce;
92 spi_bi->platform_data = board_pdata;
93 }
94
95 spi_register_board_info(&ads7846_spi_board_info, 1);
96}
97#else
98void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
99 struct ads7846_platform_data *board_pdata)
100{
101}
102#endif
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
index 07c88ae083fb..335c7822fea1 100644
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -3,15 +3,7 @@
3 3
4#include <sound/tlv320aic3x.h> 4#include <sound/tlv320aic3x.h>
5#include <linux/mfd/menelaus.h> 5#include <linux/mfd/menelaus.h>
6#include "twl-common.h"
7 6
8#define NAND_BLOCK_SIZE SZ_128K
9
10struct mtd_partition;
11struct ads7846_platform_data;
12
13void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
14 struct ads7846_platform_data *board_pdata);
15void *n8x0_legacy_init(void); 7void *n8x0_legacy_init(void);
16 8
17extern struct menelaus_platform_data n8x0_menelaus_platform_data; 9extern struct menelaus_platform_data n8x0_menelaus_platform_data;
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index deed42e1dd9c..14652e78bde7 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -77,15 +77,6 @@ static inline int omap4_pm_init_early(void)
77} 77}
78#endif 78#endif
79 79
80#ifdef CONFIG_OMAP_MUX
81int omap_mux_late_init(void);
82#else
83static inline int omap_mux_late_init(void)
84{
85 return 0;
86}
87#endif
88
89extern void omap2_init_common_infrastructure(void); 80extern void omap2_init_common_infrastructure(void);
90 81
91extern void omap_init_time(void); 82extern void omap_init_time(void);
@@ -262,8 +253,6 @@ extern void __iomem *omap4_get_sar_ram_base(void);
262extern void omap4_mpuss_early_init(void); 253extern void omap4_mpuss_early_init(void);
263extern void omap_do_wfi(void); 254extern void omap_do_wfi(void);
264 255
265extern void omap4_secondary_startup(void);
266extern void omap4460_secondary_startup(void);
267 256
268#ifdef CONFIG_SMP 257#ifdef CONFIG_SMP
269/* Needed for secondary core boot */ 258/* Needed for secondary core boot */
@@ -275,16 +264,11 @@ extern void omap4_cpu_die(unsigned int cpu);
275extern int omap4_cpu_kill(unsigned int cpu); 264extern int omap4_cpu_kill(unsigned int cpu);
276 265
277extern const struct smp_operations omap4_smp_ops; 266extern const struct smp_operations omap4_smp_ops;
278
279extern void omap5_secondary_startup(void);
280extern void omap5_secondary_hyp_startup(void);
281#endif 267#endif
282 268
283#if defined(CONFIG_SMP) && defined(CONFIG_PM) 269#if defined(CONFIG_SMP) && defined(CONFIG_PM)
284extern int omap4_mpuss_init(void); 270extern int omap4_mpuss_init(void);
285extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state); 271extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
286extern int omap4_finish_suspend(unsigned long cpu_state);
287extern void omap4_cpu_resume(void);
288extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state); 272extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
289#else 273#else
290static inline int omap4_enter_lowpower(unsigned int cpu, 274static inline int omap4_enter_lowpower(unsigned int cpu,
@@ -305,14 +289,41 @@ static inline int omap4_mpuss_init(void)
305 return 0; 289 return 0;
306} 290}
307 291
292#endif
293
294#ifdef CONFIG_ARCH_OMAP4
295void omap4_secondary_startup(void);
296void omap4460_secondary_startup(void);
297int omap4_finish_suspend(unsigned long cpu_state);
298void omap4_cpu_resume(void);
299#else
300static inline void omap4_secondary_startup(void)
301{
302}
303
304static inline void omap4460_secondary_startup(void)
305{
306}
308static inline int omap4_finish_suspend(unsigned long cpu_state) 307static inline int omap4_finish_suspend(unsigned long cpu_state)
309{ 308{
310 return 0; 309 return 0;
311} 310}
312
313static inline void omap4_cpu_resume(void) 311static inline void omap4_cpu_resume(void)
314{} 312{
313}
314#endif
315 315
316#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
317void omap5_secondary_startup(void);
318void omap5_secondary_hyp_startup(void);
319#else
320static inline void omap5_secondary_startup(void)
321{
322}
323
324static inline void omap5_secondary_hyp_startup(void)
325{
326}
316#endif 327#endif
317 328
318void pdata_quirks_init(const struct of_device_id *); 329void pdata_quirks_init(const struct of_device_id *);
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index fa138d4032b6..a8b291f00109 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -21,6 +21,7 @@
21#include "common.h" 21#include "common.h"
22#include "pm.h" 22#include "pm.h"
23#include "prm.h" 23#include "prm.h"
24#include "soc.h"
24#include "clockdomain.h" 25#include "clockdomain.h"
25 26
26#define MAX_CPUS 2 27#define MAX_CPUS 2
@@ -30,6 +31,7 @@ struct idle_statedata {
30 u32 cpu_state; 31 u32 cpu_state;
31 u32 mpu_logic_state; 32 u32 mpu_logic_state;
32 u32 mpu_state; 33 u32 mpu_state;
34 u32 mpu_state_vote;
33}; 35};
34 36
35static struct idle_statedata omap4_idle_data[] = { 37static struct idle_statedata omap4_idle_data[] = {
@@ -50,12 +52,26 @@ static struct idle_statedata omap4_idle_data[] = {
50 }, 52 },
51}; 53};
52 54
55static struct idle_statedata omap5_idle_data[] = {
56 {
57 .cpu_state = PWRDM_POWER_ON,
58 .mpu_state = PWRDM_POWER_ON,
59 .mpu_logic_state = PWRDM_POWER_ON,
60 },
61 {
62 .cpu_state = PWRDM_POWER_RET,
63 .mpu_state = PWRDM_POWER_RET,
64 .mpu_logic_state = PWRDM_POWER_RET,
65 },
66};
67
53static struct powerdomain *mpu_pd, *cpu_pd[MAX_CPUS]; 68static struct powerdomain *mpu_pd, *cpu_pd[MAX_CPUS];
54static struct clockdomain *cpu_clkdm[MAX_CPUS]; 69static struct clockdomain *cpu_clkdm[MAX_CPUS];
55 70
56static atomic_t abort_barrier; 71static atomic_t abort_barrier;
57static bool cpu_done[MAX_CPUS]; 72static bool cpu_done[MAX_CPUS];
58static struct idle_statedata *state_ptr = &omap4_idle_data[0]; 73static struct idle_statedata *state_ptr = &omap4_idle_data[0];
74static DEFINE_RAW_SPINLOCK(mpu_lock);
59 75
60/* Private functions */ 76/* Private functions */
61 77
@@ -77,6 +93,32 @@ static int omap_enter_idle_simple(struct cpuidle_device *dev,
77 return index; 93 return index;
78} 94}
79 95
96static int omap_enter_idle_smp(struct cpuidle_device *dev,
97 struct cpuidle_driver *drv,
98 int index)
99{
100 struct idle_statedata *cx = state_ptr + index;
101 unsigned long flag;
102
103 raw_spin_lock_irqsave(&mpu_lock, flag);
104 cx->mpu_state_vote++;
105 if (cx->mpu_state_vote == num_online_cpus()) {
106 pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
107 omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
108 }
109 raw_spin_unlock_irqrestore(&mpu_lock, flag);
110
111 omap4_enter_lowpower(dev->cpu, cx->cpu_state);
112
113 raw_spin_lock_irqsave(&mpu_lock, flag);
114 if (cx->mpu_state_vote == num_online_cpus())
115 omap_set_pwrdm_state(mpu_pd, PWRDM_POWER_ON);
116 cx->mpu_state_vote--;
117 raw_spin_unlock_irqrestore(&mpu_lock, flag);
118
119 return index;
120}
121
80static int omap_enter_idle_coupled(struct cpuidle_device *dev, 122static int omap_enter_idle_coupled(struct cpuidle_device *dev,
81 struct cpuidle_driver *drv, 123 struct cpuidle_driver *drv,
82 int index) 124 int index)
@@ -220,6 +262,32 @@ static struct cpuidle_driver omap4_idle_driver = {
220 .safe_state_index = 0, 262 .safe_state_index = 0,
221}; 263};
222 264
265static struct cpuidle_driver omap5_idle_driver = {
266 .name = "omap5_idle",
267 .owner = THIS_MODULE,
268 .states = {
269 {
270 /* C1 - CPU0 ON + CPU1 ON + MPU ON */
271 .exit_latency = 2 + 2,
272 .target_residency = 5,
273 .enter = omap_enter_idle_simple,
274 .name = "C1",
275 .desc = "CPUx WFI, MPUSS ON"
276 },
277 {
278 /* C2 - CPU0 RET + CPU1 RET + MPU CSWR */
279 .exit_latency = 48 + 60,
280 .target_residency = 100,
281 .flags = CPUIDLE_FLAG_TIMER_STOP,
282 .enter = omap_enter_idle_smp,
283 .name = "C2",
284 .desc = "CPUx CSWR, MPUSS CSWR",
285 },
286 },
287 .state_count = ARRAY_SIZE(omap5_idle_data),
288 .safe_state_index = 0,
289};
290
223/* Public functions */ 291/* Public functions */
224 292
225/** 293/**
@@ -230,6 +298,16 @@ static struct cpuidle_driver omap4_idle_driver = {
230 */ 298 */
231int __init omap4_idle_init(void) 299int __init omap4_idle_init(void)
232{ 300{
301 struct cpuidle_driver *idle_driver;
302
303 if (soc_is_omap54xx()) {
304 state_ptr = &omap5_idle_data[0];
305 idle_driver = &omap5_idle_driver;
306 } else {
307 state_ptr = &omap4_idle_data[0];
308 idle_driver = &omap4_idle_driver;
309 }
310
233 mpu_pd = pwrdm_lookup("mpu_pwrdm"); 311 mpu_pd = pwrdm_lookup("mpu_pwrdm");
234 cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm"); 312 cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
235 cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm"); 313 cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
@@ -244,5 +322,5 @@ int __init omap4_idle_init(void)
244 /* Configure the broadcast timer on each cpu */ 322 /* Configure the broadcast timer on each cpu */
245 on_each_cpu(omap_setup_broadcast_timer, NULL, 1); 323 on_each_cpu(omap_setup_broadcast_timer, NULL, 1);
246 324
247 return cpuidle_register(&omap4_idle_driver, cpu_online_mask); 325 return cpuidle_register(idle_driver, cpu_online_mask);
248} 326}
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 60a20f3b44de..3fdb94599184 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -30,7 +30,6 @@
30 30
31#include "soc.h" 31#include "soc.h"
32#include "common.h" 32#include "common.h"
33#include "mux.h"
34#include "control.h" 33#include "control.h"
35#include "display.h" 34#include "display.h"
36 35
diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c
deleted file mode 100644
index 1d583bc0b1a9..000000000000
--- a/arch/arm/mach-omap2/dss-common.c
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * Copyright (C) 2012 Texas Instruments, Inc..
3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
17 * 02110-1301 USA
18 *
19 */
20
21/*
22 * NOTE: this is a transitional file to help with DT adaptation.
23 * This file will be removed when DSS supports DT.
24 */
25
26#include <linux/kernel.h>
27#include <linux/gpio.h>
28#include <linux/platform_device.h>
29
30#include <linux/platform_data/omapdss.h>
31#include <video/omap-panel-data.h>
32
33#include "soc.h"
34#include "dss-common.h"
35#include "mux.h"
36#include "display.h"
37
diff --git a/arch/arm/mach-omap2/dss-common.h b/arch/arm/mach-omap2/dss-common.h
deleted file mode 100644
index a9becf0d5be8..000000000000
--- a/arch/arm/mach-omap2/dss-common.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef __OMAP_DSS_COMMON__
2#define __OMAP_DSS_COMMON__
3
4/*
5 * NOTE: this is a transitional file to help with DT adaptation.
6 * This file will be removed when DSS supports DT.
7 */
8
9void __init omap4_panda_display_init_of(void);
10void __init omap_4430sdp_display_init_of(void);
11void __init omap3_igep2_display_init_of(void);
12
13#endif
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
deleted file mode 100644
index 2757504a13c4..000000000000
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ /dev/null
@@ -1,100 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/gpmc-smsc911x.c
3 *
4 * Copyright (C) 2009 Li-Pro.Net
5 * Stephan Linz <linz@li-pro.net>
6 *
7 * Modified from linux/arch/arm/mach-omap2/gpmc-smc91x.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#define pr_fmt(fmt) "%s: " fmt, __func__
14
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/gpio.h>
18#include <linux/delay.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/smsc911x.h>
22
23#include "gpmc.h"
24#include "gpmc-smsc911x.h"
25
26static struct resource gpmc_smsc911x_resources[] = {
27 [0] = {
28 .flags = IORESOURCE_MEM,
29 },
30 [1] = {
31 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
32 },
33};
34
35static struct smsc911x_platform_config gpmc_smsc911x_config = {
36 .phy_interface = PHY_INTERFACE_MODE_MII,
37 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
38 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
39};
40
41/*
42 * Initialize smsc911x device connected to the GPMC. Note that we
43 * assume that pin multiplexing is done in the board-*.c file,
44 * or in the bootloader.
45 */
46void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *gpmc_cfg)
47{
48 struct platform_device *pdev;
49 unsigned long cs_mem_base;
50 int ret;
51
52 if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
53 pr_err("Failed to request GPMC mem region\n");
54 return;
55 }
56
57 gpmc_smsc911x_resources[0].start = cs_mem_base + 0x0;
58 gpmc_smsc911x_resources[0].end = cs_mem_base + 0xff;
59
60 if (gpio_request_one(gpmc_cfg->gpio_irq, GPIOF_IN, "smsc911x irq")) {
61 pr_err("Failed to request IRQ GPIO%d\n", gpmc_cfg->gpio_irq);
62 goto free1;
63 }
64
65 gpmc_smsc911x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq);
66
67 if (gpio_is_valid(gpmc_cfg->gpio_reset)) {
68 ret = gpio_request_one(gpmc_cfg->gpio_reset,
69 GPIOF_OUT_INIT_HIGH, "smsc911x reset");
70 if (ret) {
71 pr_err("Failed to request reset GPIO%d\n",
72 gpmc_cfg->gpio_reset);
73 goto free2;
74 }
75
76 gpio_set_value(gpmc_cfg->gpio_reset, 0);
77 msleep(100);
78 gpio_set_value(gpmc_cfg->gpio_reset, 1);
79 }
80
81 gpmc_smsc911x_config.flags = gpmc_cfg->flags ? : SMSC911X_USE_16BIT;
82
83 pdev = platform_device_register_resndata(NULL, "smsc911x", gpmc_cfg->id,
84 gpmc_smsc911x_resources, ARRAY_SIZE(gpmc_smsc911x_resources),
85 &gpmc_smsc911x_config, sizeof(gpmc_smsc911x_config));
86 if (IS_ERR(pdev)) {
87 pr_err("Unable to register platform device\n");
88 gpio_free(gpmc_cfg->gpio_reset);
89 goto free2;
90 }
91
92 return;
93
94free2:
95 gpio_free(gpmc_cfg->gpio_irq);
96free1:
97 gpmc_cs_free(gpmc_cfg->cs);
98
99 pr_err("Could not initialize smsc911x device\n");
100}
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.h b/arch/arm/mach-omap2/gpmc-smsc911x.h
deleted file mode 100644
index 99a05b8412fa..000000000000
--- a/arch/arm/mach-omap2/gpmc-smsc911x.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
3 *
4 * Copyright (C) 2009 Li-Pro.Net
5 * Stephan Linz <linz@li-pro.net>
6 *
7 * Modified from arch/arm/plat-omap/include/plat/gpmc-smc91x.h
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ASM_ARCH_OMAP_GPMC_SMSC911X_H__
15
16struct omap_smsc911x_platform_data {
17 int id;
18 int cs;
19 int gpio_irq;
20 int gpio_reset;
21 u32 flags;
22};
23
24#if IS_ENABLED(CONFIG_SMSC911X)
25
26extern void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d);
27
28#else
29
30static inline void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d)
31{
32}
33
34#endif
35#endif
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 478097741bce..cb754c46747e 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -22,7 +22,6 @@
22#include "omap_device.h" 22#include "omap_device.h"
23#include "omap-pm.h" 23#include "omap-pm.h"
24 24
25#include "mux.h"
26#include "hsmmc.h" 25#include "hsmmc.h"
27#include "control.h" 26#include "control.h"
28 27
@@ -147,91 +146,6 @@ static int nop_mmc_set_power(struct device *dev, int power_on, int vdd)
147 return 0; 146 return 0;
148} 147}
149 148
150static inline void omap_hsmmc_mux(struct omap_hsmmc_platform_data
151 *mmc_controller, int controller_nr)
152{
153 if (gpio_is_valid(mmc_controller->gpio_cd) &&
154 (mmc_controller->gpio_cd < OMAP_MAX_GPIO_LINES))
155 omap_mux_init_gpio(mmc_controller->gpio_cd,
156 OMAP_PIN_INPUT_PULLUP);
157 if (gpio_is_valid(mmc_controller->gpio_cod) &&
158 (mmc_controller->gpio_cod < OMAP_MAX_GPIO_LINES))
159 omap_mux_init_gpio(mmc_controller->gpio_cod,
160 OMAP_PIN_INPUT_PULLUP);
161 if (gpio_is_valid(mmc_controller->gpio_wp) &&
162 (mmc_controller->gpio_wp < OMAP_MAX_GPIO_LINES))
163 omap_mux_init_gpio(mmc_controller->gpio_wp,
164 OMAP_PIN_INPUT_PULLUP);
165 if (cpu_is_omap34xx()) {
166 if (controller_nr == 0) {
167 omap_mux_init_signal("sdmmc1_clk",
168 OMAP_PIN_INPUT_PULLUP);
169 omap_mux_init_signal("sdmmc1_cmd",
170 OMAP_PIN_INPUT_PULLUP);
171 omap_mux_init_signal("sdmmc1_dat0",
172 OMAP_PIN_INPUT_PULLUP);
173 if (mmc_controller->caps &
174 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
175 omap_mux_init_signal("sdmmc1_dat1",
176 OMAP_PIN_INPUT_PULLUP);
177 omap_mux_init_signal("sdmmc1_dat2",
178 OMAP_PIN_INPUT_PULLUP);
179 omap_mux_init_signal("sdmmc1_dat3",
180 OMAP_PIN_INPUT_PULLUP);
181 }
182 if (mmc_controller->caps &
183 MMC_CAP_8_BIT_DATA) {
184 omap_mux_init_signal("sdmmc1_dat4",
185 OMAP_PIN_INPUT_PULLUP);
186 omap_mux_init_signal("sdmmc1_dat5",
187 OMAP_PIN_INPUT_PULLUP);
188 omap_mux_init_signal("sdmmc1_dat6",
189 OMAP_PIN_INPUT_PULLUP);
190 omap_mux_init_signal("sdmmc1_dat7",
191 OMAP_PIN_INPUT_PULLUP);
192 }
193 }
194 if (controller_nr == 1) {
195 /* MMC2 */
196 omap_mux_init_signal("sdmmc2_clk",
197 OMAP_PIN_INPUT_PULLUP);
198 omap_mux_init_signal("sdmmc2_cmd",
199 OMAP_PIN_INPUT_PULLUP);
200 omap_mux_init_signal("sdmmc2_dat0",
201 OMAP_PIN_INPUT_PULLUP);
202
203 /*
204 * For 8 wire configurations, Lines DAT4, 5, 6 and 7
205 * need to be muxed in the board-*.c files
206 */
207 if (mmc_controller->caps &
208 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
209 omap_mux_init_signal("sdmmc2_dat1",
210 OMAP_PIN_INPUT_PULLUP);
211 omap_mux_init_signal("sdmmc2_dat2",
212 OMAP_PIN_INPUT_PULLUP);
213 omap_mux_init_signal("sdmmc2_dat3",
214 OMAP_PIN_INPUT_PULLUP);
215 }
216 if (mmc_controller->caps &
217 MMC_CAP_8_BIT_DATA) {
218 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
219 OMAP_PIN_INPUT_PULLUP);
220 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
221 OMAP_PIN_INPUT_PULLUP);
222 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
223 OMAP_PIN_INPUT_PULLUP);
224 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
225 OMAP_PIN_INPUT_PULLUP);
226 }
227 }
228
229 /*
230 * For MMC3 the pins need to be muxed in the board-*.c files
231 */
232 }
233}
234
235static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, 149static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
236 struct omap_hsmmc_platform_data *mmc) 150 struct omap_hsmmc_platform_data *mmc)
237{ 151{
@@ -410,8 +324,6 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
410 if (res < 0) 324 if (res < 0)
411 goto free_mmc; 325 goto free_mmc;
412 326
413 omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
414
415 name = "omap_hsmmc"; 327 name = "omap_hsmmc";
416 res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN, 328 res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
417 "mmc%d", ctrl_nr); 329 "mmc%d", ctrl_nr);
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index b9d8e47ffe8e..91a21c3923b2 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -26,7 +26,6 @@
26 26
27#include "prm.h" 27#include "prm.h"
28#include "common.h" 28#include "common.h"
29#include "mux.h"
30#include "i2c.h" 29#include "i2c.h"
31 30
32/* In register I2C_CON, Bit 15 is the I2C enable bit */ 31/* In register I2C_CON, Bit 15 is the I2C enable bit */
@@ -36,20 +35,6 @@
36 35
37#define MAX_OMAP_I2C_HWMOD_NAME_LEN 16 36#define MAX_OMAP_I2C_HWMOD_NAME_LEN 16
38 37
39static void __init omap2_i2c_mux_pins(int bus_id)
40{
41 char mux_name[sizeof("i2c2_scl.i2c2_scl")];
42
43 /* First I2C bus is not muxable */
44 if (bus_id == 1)
45 return;
46
47 sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id);
48 omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
49 sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
50 omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
51}
52
53/** 38/**
54 * omap_i2c_reset - reset the omap i2c module. 39 * omap_i2c_reset - reset the omap i2c module.
55 * @oh: struct omap_hwmod * 40 * @oh: struct omap_hwmod *
@@ -107,85 +92,3 @@ int omap_i2c_reset(struct omap_hwmod *oh)
107 92
108 return 0; 93 return 0;
109} 94}
110
111static int __init omap_i2c_nr_ports(void)
112{
113 int ports = 0;
114
115 if (cpu_is_omap24xx())
116 ports = 2;
117 else if (cpu_is_omap34xx())
118 ports = 3;
119 else if (cpu_is_omap44xx())
120 ports = 4;
121 return ports;
122}
123
124/*
125 * XXX This function is a temporary compatibility wrapper - only
126 * needed until the I2C driver can be converted to call
127 * omap_pm_set_max_dev_wakeup_lat() and handle a return code.
128 */
129static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
130{
131 omap_pm_set_max_mpu_wakeup_lat(dev, t);
132}
133
134static const char name[] = "omap_i2c";
135
136int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
137 int bus_id)
138{
139 int l;
140 struct omap_hwmod *oh;
141 struct platform_device *pdev;
142 char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
143 struct omap_i2c_bus_platform_data *pdata;
144 struct omap_i2c_dev_attr *dev_attr;
145
146 if (bus_id > omap_i2c_nr_ports())
147 return -EINVAL;
148
149 omap2_i2c_mux_pins(bus_id);
150
151 l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
152 WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
153 "String buffer overflow in I2C%d device setup\n", bus_id);
154 oh = omap_hwmod_lookup(oh_name);
155 if (!oh) {
156 pr_err("Could not look up %s\n", oh_name);
157 return -EEXIST;
158 }
159
160 pdata = i2c_pdata;
161 /*
162 * pass the hwmod class's CPU-specific knowledge of I2C IP revision in
163 * use, and functionality implementation flags, up to the OMAP I2C
164 * driver via platform data
165 */
166 pdata->rev = oh->class->rev;
167
168 dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr;
169 pdata->flags = dev_attr->flags;
170
171 /*
172 * When waiting for completion of a i2c transfer, we need to
173 * set a wake up latency constraint for the MPU. This is to
174 * ensure quick enough wakeup from idle, when transfer
175 * completes.
176 * Only omap3 has support for constraints
177 */
178 if (cpu_is_omap34xx())
179 pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
180 pdev = omap_device_build(name, bus_id, oh, pdata,
181 sizeof(struct omap_i2c_bus_platform_data));
182 WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);
183
184 return PTR_ERR_OR_ZERO(pdev);
185}
186
187static int __init omap_i2c_cmdline(void)
188{
189 return omap_register_i2c_bus_cmdline();
190}
191omap_subsys_initcall(omap_i2c_cmdline);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 0e9acdd95d70..5aafb8449c40 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -427,7 +427,6 @@ static void __init omap_hwmod_init_postsetup(void)
427 427
428static void __init __maybe_unused omap_common_late_init(void) 428static void __init __maybe_unused omap_common_late_init(void)
429{ 429{
430 omap_mux_late_init();
431 omap2_common_pm_late_init(); 430 omap2_common_pm_late_init();
432 omap_soc_device_init(); 431 omap_soc_device_init();
433} 432}
@@ -717,10 +716,11 @@ void __init omap5_init_early(void)
717 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); 716 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
718 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 717 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
719 omap2_control_base_init(); 718 omap2_control_base_init();
720 omap4_pm_init_early();
721 omap2_prcm_base_init(); 719 omap2_prcm_base_init();
722 omap5xxx_check_revision(); 720 omap5xxx_check_revision();
723 omap4_sar_ram_init(); 721 omap4_sar_ram_init();
722 omap4_mpuss_early_init();
723 omap4_pm_init_early();
724 omap54xx_voltagedomains_init(); 724 omap54xx_voltagedomains_init();
725 omap54xx_powerdomains_init(); 725 omap54xx_powerdomains_init();
726 omap54xx_clockdomains_init(); 726 omap54xx_clockdomains_init();
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
index 8bdf182422bd..5a3bc3de58d0 100644
--- a/arch/arm/mach-omap2/msdi.c
+++ b/arch/arm/mach-omap2/msdi.c
@@ -30,7 +30,6 @@
30#include "control.h" 30#include "control.h"
31#include "omap_hwmod.h" 31#include "omap_hwmod.h"
32#include "omap_device.h" 32#include "omap_device.h"
33#include "mux.h"
34#include "mmc.h" 33#include "mmc.h"
35 34
36/* 35/*
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
deleted file mode 100644
index 176eef6ef338..000000000000
--- a/arch/arm/mach-omap2/mux.c
+++ /dev/null
@@ -1,1153 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/mux.c
3 *
4 * OMAP2, OMAP3 and OMAP4 pin multiplexing configurations
5 *
6 * Copyright (C) 2004 - 2010 Texas Instruments Inc.
7 * Copyright (C) 2003 - 2008 Nokia Corporation
8 *
9 * Written by Tony Lindgren
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 */
26#include <linux/kernel.h>
27#include <linux/init.h>
28#include <linux/io.h>
29#include <linux/list.h>
30#include <linux/slab.h>
31#include <linux/ctype.h>
32#include <linux/debugfs.h>
33#include <linux/seq_file.h>
34#include <linux/uaccess.h>
35#include <linux/irq.h>
36#include <linux/interrupt.h>
37
38
39#include "omap_hwmod.h"
40
41#include "soc.h"
42#include "control.h"
43#include "mux.h"
44#include "prm.h"
45#include "common.h"
46
47#define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */
48#define OMAP_MUX_BASE_SZ 0x5ca
49
50struct omap_mux_entry {
51 struct omap_mux mux;
52 struct list_head node;
53};
54
55static LIST_HEAD(mux_partitions);
56static DEFINE_MUTEX(muxmode_mutex);
57
58struct omap_mux_partition *omap_mux_get(const char *name)
59{
60 struct omap_mux_partition *partition;
61
62 list_for_each_entry(partition, &mux_partitions, node) {
63 if (!strcmp(name, partition->name))
64 return partition;
65 }
66
67 return NULL;
68}
69
70u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg)
71{
72 if (partition->flags & OMAP_MUX_REG_8BIT)
73 return readb_relaxed(partition->base + reg);
74 else
75 return readw_relaxed(partition->base + reg);
76}
77
78void omap_mux_write(struct omap_mux_partition *partition, u16 val,
79 u16 reg)
80{
81 if (partition->flags & OMAP_MUX_REG_8BIT)
82 writeb_relaxed(val, partition->base + reg);
83 else
84 writew_relaxed(val, partition->base + reg);
85}
86
87void omap_mux_write_array(struct omap_mux_partition *partition,
88 struct omap_board_mux *board_mux)
89{
90 if (!board_mux)
91 return;
92
93 while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
94 omap_mux_write(partition, board_mux->value,
95 board_mux->reg_offset);
96 board_mux++;
97 }
98}
99
100#ifdef CONFIG_OMAP_MUX
101
102static char *omap_mux_options;
103
104static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition,
105 int gpio, int val)
106{
107 struct omap_mux_entry *e;
108 struct omap_mux *gpio_mux = NULL;
109 u16 old_mode;
110 u16 mux_mode;
111 int found = 0;
112 struct list_head *muxmodes = &partition->muxmodes;
113
114 if (!gpio)
115 return -EINVAL;
116
117 list_for_each_entry(e, muxmodes, node) {
118 struct omap_mux *m = &e->mux;
119 if (gpio == m->gpio) {
120 gpio_mux = m;
121 found++;
122 }
123 }
124
125 if (found == 0) {
126 pr_err("%s: Could not set gpio%i\n", __func__, gpio);
127 return -ENODEV;
128 }
129
130 if (found > 1) {
131 pr_info("%s: Multiple gpio paths (%d) for gpio%i\n", __func__,
132 found, gpio);
133 return -EINVAL;
134 }
135
136 old_mode = omap_mux_read(partition, gpio_mux->reg_offset);
137 mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
138 mux_mode |= partition->gpio;
139 pr_debug("%s: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", __func__,
140 gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
141 omap_mux_write(partition, mux_mode, gpio_mux->reg_offset);
142
143 return 0;
144}
145
146int __init omap_mux_init_gpio(int gpio, int val)
147{
148 struct omap_mux_partition *partition;
149 int ret;
150
151 list_for_each_entry(partition, &mux_partitions, node) {
152 ret = _omap_mux_init_gpio(partition, gpio, val);
153 if (!ret)
154 return ret;
155 }
156
157 return -ENODEV;
158}
159
160static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition,
161 const char *muxname,
162 struct omap_mux **found_mux)
163{
164 struct omap_mux *mux = NULL;
165 struct omap_mux_entry *e;
166 const char *mode_name;
167 int found = 0, found_mode = 0, mode0_len = 0;
168 struct list_head *muxmodes = &partition->muxmodes;
169
170 mode_name = strchr(muxname, '.');
171 if (mode_name) {
172 mode0_len = strlen(muxname) - strlen(mode_name);
173 mode_name++;
174 } else {
175 mode_name = muxname;
176 }
177
178 list_for_each_entry(e, muxmodes, node) {
179 char *m0_entry;
180 int i;
181
182 mux = &e->mux;
183 m0_entry = mux->muxnames[0];
184
185 /* First check for full name in mode0.muxmode format */
186 if (mode0_len)
187 if (strncmp(muxname, m0_entry, mode0_len) ||
188 (strlen(m0_entry) != mode0_len))
189 continue;
190
191 /* Then check for muxmode only */
192 for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
193 char *mode_cur = mux->muxnames[i];
194
195 if (!mode_cur)
196 continue;
197
198 if (!strcmp(mode_name, mode_cur)) {
199 *found_mux = mux;
200 found++;
201 found_mode = i;
202 }
203 }
204 }
205
206 if (found == 1) {
207 return found_mode;
208 }
209
210 if (found > 1) {
211 pr_err("%s: Multiple signal paths (%i) for %s\n", __func__,
212 found, muxname);
213 return -EINVAL;
214 }
215
216 return -ENODEV;
217}
218
219int __init omap_mux_get_by_name(const char *muxname,
220 struct omap_mux_partition **found_partition,
221 struct omap_mux **found_mux)
222{
223 struct omap_mux_partition *partition;
224
225 list_for_each_entry(partition, &mux_partitions, node) {
226 struct omap_mux *mux = NULL;
227 int mux_mode = _omap_mux_get_by_name(partition, muxname, &mux);
228 if (mux_mode < 0)
229 continue;
230
231 *found_partition = partition;
232 *found_mux = mux;
233
234 return mux_mode;
235 }
236
237 pr_err("%s: Could not find signal %s\n", __func__, muxname);
238
239 return -ENODEV;
240}
241
242int __init omap_mux_init_signal(const char *muxname, int val)
243{
244 struct omap_mux_partition *partition = NULL;
245 struct omap_mux *mux = NULL;
246 u16 old_mode;
247 int mux_mode;
248
249 mux_mode = omap_mux_get_by_name(muxname, &partition, &mux);
250 if (mux_mode < 0 || !mux)
251 return mux_mode;
252
253 old_mode = omap_mux_read(partition, mux->reg_offset);
254 mux_mode |= val;
255 pr_debug("%s: Setting signal %s 0x%04x -> 0x%04x\n",
256 __func__, muxname, old_mode, mux_mode);
257 omap_mux_write(partition, mux_mode, mux->reg_offset);
258
259 return 0;
260}
261
262struct omap_hwmod_mux_info * __init
263omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
264{
265 struct omap_hwmod_mux_info *hmux;
266 int i, nr_pads_dynamic = 0;
267
268 if (!bpads || nr_pads < 1)
269 return NULL;
270
271 hmux = kzalloc(sizeof(struct omap_hwmod_mux_info), GFP_KERNEL);
272 if (!hmux)
273 goto err1;
274
275 hmux->nr_pads = nr_pads;
276
277 hmux->pads = kzalloc(sizeof(struct omap_device_pad) *
278 nr_pads, GFP_KERNEL);
279 if (!hmux->pads)
280 goto err2;
281
282 for (i = 0; i < hmux->nr_pads; i++) {
283 struct omap_mux_partition *partition;
284 struct omap_device_pad *bpad = &bpads[i], *pad = &hmux->pads[i];
285 struct omap_mux *mux;
286 int mux_mode;
287
288 mux_mode = omap_mux_get_by_name(bpad->name, &partition, &mux);
289 if (mux_mode < 0)
290 goto err3;
291 if (!pad->partition)
292 pad->partition = partition;
293 if (!pad->mux)
294 pad->mux = mux;
295
296 pad->name = kzalloc(strlen(bpad->name) + 1, GFP_KERNEL);
297 if (!pad->name) {
298 int j;
299
300 for (j = i - 1; j >= 0; j--)
301 kfree(hmux->pads[j].name);
302 goto err3;
303 }
304 strcpy(pad->name, bpad->name);
305
306 pad->flags = bpad->flags;
307 pad->enable = bpad->enable;
308 pad->idle = bpad->idle;
309 pad->off = bpad->off;
310
311 if (pad->flags &
312 (OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP))
313 nr_pads_dynamic++;
314
315 pr_debug("%s: Initialized %s\n", __func__, pad->name);
316 }
317
318 if (!nr_pads_dynamic)
319 return hmux;
320
321 /*
322 * Add pads that need dynamic muxing into a separate list
323 */
324
325 hmux->nr_pads_dynamic = nr_pads_dynamic;
326 hmux->pads_dynamic = kzalloc(sizeof(struct omap_device_pad *) *
327 nr_pads_dynamic, GFP_KERNEL);
328 if (!hmux->pads_dynamic) {
329 pr_err("%s: Could not allocate dynamic pads\n", __func__);
330 return hmux;
331 }
332
333 nr_pads_dynamic = 0;
334 for (i = 0; i < hmux->nr_pads; i++) {
335 struct omap_device_pad *pad = &hmux->pads[i];
336
337 if (pad->flags &
338 (OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP)) {
339 pr_debug("%s: pad %s tagged dynamic\n",
340 __func__, pad->name);
341 hmux->pads_dynamic[nr_pads_dynamic] = pad;
342 nr_pads_dynamic++;
343 }
344 }
345
346 return hmux;
347
348err3:
349 kfree(hmux->pads);
350err2:
351 kfree(hmux);
352err1:
353 pr_err("%s: Could not allocate device mux entry\n", __func__);
354
355 return NULL;
356}
357
358/**
359 * omap_hwmod_mux_scan_wakeups - omap hwmod scan wakeup pads
360 * @hmux: Pads for a hwmod
361 * @mpu_irqs: MPU irq array for a hwmod
362 *
363 * Scans the wakeup status of pads for a single hwmod. If an irq
364 * array is defined for this mux, the parser will call the registered
365 * ISRs for corresponding pads, otherwise the parser will stop at the
366 * first wakeup active pad and return. Returns true if there is a
367 * pending and non-served wakeup event for the mux, otherwise false.
368 */
369static bool omap_hwmod_mux_scan_wakeups(struct omap_hwmod_mux_info *hmux,
370 struct omap_hwmod_irq_info *mpu_irqs)
371{
372 int i, irq;
373 unsigned int val;
374 u32 handled_irqs = 0;
375
376 for (i = 0; i < hmux->nr_pads_dynamic; i++) {
377 struct omap_device_pad *pad = hmux->pads_dynamic[i];
378
379 if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP) ||
380 !(pad->idle & OMAP_WAKEUP_EN))
381 continue;
382
383 val = omap_mux_read(pad->partition, pad->mux->reg_offset);
384 if (!(val & OMAP_WAKEUP_EVENT))
385 continue;
386
387 if (!hmux->irqs)
388 return true;
389
390 irq = hmux->irqs[i];
391 /* make sure we only handle each irq once */
392 if (handled_irqs & 1 << irq)
393 continue;
394
395 handled_irqs |= 1 << irq;
396
397 generic_handle_irq(mpu_irqs[irq].irq);
398 }
399
400 return false;
401}
402
403/**
404 * _omap_hwmod_mux_handle_irq - Process wakeup events for a single hwmod
405 *
406 * Checks a single hwmod for every wakeup capable pad to see if there is an
407 * active wakeup event. If this is the case, call the corresponding ISR.
408 */
409static int _omap_hwmod_mux_handle_irq(struct omap_hwmod *oh, void *data)
410{
411 if (!oh->mux || !oh->mux->enabled)
412 return 0;
413 if (omap_hwmod_mux_scan_wakeups(oh->mux, oh->mpu_irqs))
414 generic_handle_irq(oh->mpu_irqs[0].irq);
415 return 0;
416}
417
418/**
419 * omap_hwmod_mux_handle_irq - Process pad wakeup irqs.
420 *
421 * Calls a function for each registered omap_hwmod to check
422 * pad wakeup statuses.
423 */
424static irqreturn_t omap_hwmod_mux_handle_irq(int irq, void *unused)
425{
426 omap_hwmod_for_each(_omap_hwmod_mux_handle_irq, NULL);
427 return IRQ_HANDLED;
428}
429
430/* Assumes the calling function takes care of locking */
431void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
432{
433 int i;
434
435 /* Runtime idling of dynamic pads */
436 if (state == _HWMOD_STATE_IDLE && hmux->enabled) {
437 for (i = 0; i < hmux->nr_pads_dynamic; i++) {
438 struct omap_device_pad *pad = hmux->pads_dynamic[i];
439 int val = -EINVAL;
440
441 val = pad->idle;
442 omap_mux_write(pad->partition, val,
443 pad->mux->reg_offset);
444 }
445
446 return;
447 }
448
449 /* Runtime enabling of dynamic pads */
450 if ((state == _HWMOD_STATE_ENABLED) && hmux->pads_dynamic
451 && hmux->enabled) {
452 for (i = 0; i < hmux->nr_pads_dynamic; i++) {
453 struct omap_device_pad *pad = hmux->pads_dynamic[i];
454 int val = -EINVAL;
455
456 val = pad->enable;
457 omap_mux_write(pad->partition, val,
458 pad->mux->reg_offset);
459 }
460
461 return;
462 }
463
464 /* Enabling or disabling of all pads */
465 for (i = 0; i < hmux->nr_pads; i++) {
466 struct omap_device_pad *pad = &hmux->pads[i];
467 int flags, val = -EINVAL;
468
469 flags = pad->flags;
470
471 switch (state) {
472 case _HWMOD_STATE_ENABLED:
473 val = pad->enable;
474 pr_debug("%s: Enabling %s %x\n", __func__,
475 pad->name, val);
476 break;
477 case _HWMOD_STATE_DISABLED:
478 /* Use safe mode unless OMAP_DEVICE_PAD_REMUX */
479 if (flags & OMAP_DEVICE_PAD_REMUX)
480 val = pad->off;
481 else
482 val = OMAP_MUX_MODE7;
483 pr_debug("%s: Disabling %s %x\n", __func__,
484 pad->name, val);
485 break;
486 default:
487 /* Nothing to be done */
488 break;
489 }
490
491 if (val >= 0) {
492 omap_mux_write(pad->partition, val,
493 pad->mux->reg_offset);
494 pad->flags = flags;
495 }
496 }
497
498 if (state == _HWMOD_STATE_ENABLED)
499 hmux->enabled = true;
500 else
501 hmux->enabled = false;
502}
503
504#ifdef CONFIG_DEBUG_FS
505
506#define OMAP_MUX_MAX_NR_FLAGS 10
507#define OMAP_MUX_TEST_FLAG(val, mask) \
508 if (((val) & (mask)) == (mask)) { \
509 i++; \
510 flags[i] = #mask; \
511 }
512
513/* REVISIT: Add checking for non-optimal mux settings */
514static inline void omap_mux_decode(struct seq_file *s, u16 val)
515{
516 char *flags[OMAP_MUX_MAX_NR_FLAGS];
517 char mode[sizeof("OMAP_MUX_MODE") + 1];
518 int i = -1;
519
520 sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
521 i++;
522 flags[i] = mode;
523
524 OMAP_MUX_TEST_FLAG(val, OMAP_PIN_OFF_WAKEUPENABLE);
525 if (val & OMAP_OFF_EN) {
526 if (!(val & OMAP_OFFOUT_EN)) {
527 if (!(val & OMAP_OFF_PULL_UP)) {
528 OMAP_MUX_TEST_FLAG(val,
529 OMAP_PIN_OFF_INPUT_PULLDOWN);
530 } else {
531 OMAP_MUX_TEST_FLAG(val,
532 OMAP_PIN_OFF_INPUT_PULLUP);
533 }
534 } else {
535 if (!(val & OMAP_OFFOUT_VAL)) {
536 OMAP_MUX_TEST_FLAG(val,
537 OMAP_PIN_OFF_OUTPUT_LOW);
538 } else {
539 OMAP_MUX_TEST_FLAG(val,
540 OMAP_PIN_OFF_OUTPUT_HIGH);
541 }
542 }
543 }
544
545 if (val & OMAP_INPUT_EN) {
546 if (val & OMAP_PULL_ENA) {
547 if (!(val & OMAP_PULL_UP)) {
548 OMAP_MUX_TEST_FLAG(val,
549 OMAP_PIN_INPUT_PULLDOWN);
550 } else {
551 OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT_PULLUP);
552 }
553 } else {
554 OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT);
555 }
556 } else {
557 i++;
558 flags[i] = "OMAP_PIN_OUTPUT";
559 }
560
561 do {
562 seq_printf(s, "%s", flags[i]);
563 if (i > 0)
564 seq_printf(s, " | ");
565 } while (i-- > 0);
566}
567
568#define OMAP_MUX_DEFNAME_LEN 32
569
570static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
571{
572 struct omap_mux_partition *partition = s->private;
573 struct omap_mux_entry *e;
574 u8 omap_gen = omap_rev() >> 28;
575
576 list_for_each_entry(e, &partition->muxmodes, node) {
577 struct omap_mux *m = &e->mux;
578 char m0_def[OMAP_MUX_DEFNAME_LEN];
579 char *m0_name = m->muxnames[0];
580 u16 val;
581 int i, mode;
582
583 if (!m0_name)
584 continue;
585
586 /* REVISIT: Needs to be updated if mode0 names get longer */
587 for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) {
588 if (m0_name[i] == '\0') {
589 m0_def[i] = m0_name[i];
590 break;
591 }
592 m0_def[i] = toupper(m0_name[i]);
593 }
594 val = omap_mux_read(partition, m->reg_offset);
595 mode = val & OMAP_MUX_MODE7;
596 if (mode != 0)
597 seq_printf(s, "/* %s */\n", m->muxnames[mode]);
598
599 /*
600 * XXX: Might be revisited to support differences across
601 * same OMAP generation.
602 */
603 seq_printf(s, "OMAP%d_MUX(%s, ", omap_gen, m0_def);
604 omap_mux_decode(s, val);
605 seq_printf(s, "),\n");
606 }
607
608 return 0;
609}
610
611static int omap_mux_dbg_board_open(struct inode *inode, struct file *file)
612{
613 return single_open(file, omap_mux_dbg_board_show, inode->i_private);
614}
615
616static const struct file_operations omap_mux_dbg_board_fops = {
617 .open = omap_mux_dbg_board_open,
618 .read = seq_read,
619 .llseek = seq_lseek,
620 .release = single_release,
621};
622
623static struct omap_mux_partition *omap_mux_get_partition(struct omap_mux *mux)
624{
625 struct omap_mux_partition *partition;
626
627 list_for_each_entry(partition, &mux_partitions, node) {
628 struct list_head *muxmodes = &partition->muxmodes;
629 struct omap_mux_entry *e;
630
631 list_for_each_entry(e, muxmodes, node) {
632 struct omap_mux *m = &e->mux;
633
634 if (m == mux)
635 return partition;
636 }
637 }
638
639 return NULL;
640}
641
642static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
643{
644 struct omap_mux *m = s->private;
645 struct omap_mux_partition *partition;
646 const char *none = "NA";
647 u16 val;
648 int mode;
649
650 partition = omap_mux_get_partition(m);
651 if (!partition)
652 return 0;
653
654 val = omap_mux_read(partition, m->reg_offset);
655 mode = val & OMAP_MUX_MODE7;
656
657 seq_printf(s, "name: %s.%s (0x%08x/0x%03x = 0x%04x), b %s, t %s\n",
658 m->muxnames[0], m->muxnames[mode],
659 partition->phys + m->reg_offset, m->reg_offset, val,
660 m->balls[0] ? m->balls[0] : none,
661 m->balls[1] ? m->balls[1] : none);
662 seq_printf(s, "mode: ");
663 omap_mux_decode(s, val);
664 seq_printf(s, "\n");
665 seq_printf(s, "signals: %s | %s | %s | %s | %s | %s | %s | %s\n",
666 m->muxnames[0] ? m->muxnames[0] : none,
667 m->muxnames[1] ? m->muxnames[1] : none,
668 m->muxnames[2] ? m->muxnames[2] : none,
669 m->muxnames[3] ? m->muxnames[3] : none,
670 m->muxnames[4] ? m->muxnames[4] : none,
671 m->muxnames[5] ? m->muxnames[5] : none,
672 m->muxnames[6] ? m->muxnames[6] : none,
673 m->muxnames[7] ? m->muxnames[7] : none);
674
675 return 0;
676}
677
678#define OMAP_MUX_MAX_ARG_CHAR 7
679
680static ssize_t omap_mux_dbg_signal_write(struct file *file,
681 const char __user *user_buf,
682 size_t count, loff_t *ppos)
683{
684 struct seq_file *seqf;
685 struct omap_mux *m;
686 u16 val;
687 int ret;
688 struct omap_mux_partition *partition;
689
690 if (count > OMAP_MUX_MAX_ARG_CHAR)
691 return -EINVAL;
692
693 ret = kstrtou16_from_user(user_buf, count, 0x10, &val);
694 if (ret < 0)
695 return ret;
696
697 seqf = file->private_data;
698 m = seqf->private;
699
700 partition = omap_mux_get_partition(m);
701 if (!partition)
702 return -ENODEV;
703
704 omap_mux_write(partition, val, m->reg_offset);
705 *ppos += count;
706
707 return count;
708}
709
710static int omap_mux_dbg_signal_open(struct inode *inode, struct file *file)
711{
712 return single_open(file, omap_mux_dbg_signal_show, inode->i_private);
713}
714
715static const struct file_operations omap_mux_dbg_signal_fops = {
716 .open = omap_mux_dbg_signal_open,
717 .read = seq_read,
718 .write = omap_mux_dbg_signal_write,
719 .llseek = seq_lseek,
720 .release = single_release,
721};
722
723static struct dentry *mux_dbg_dir;
724
725static void __init omap_mux_dbg_create_entry(
726 struct omap_mux_partition *partition,
727 struct dentry *mux_dbg_dir)
728{
729 struct omap_mux_entry *e;
730
731 list_for_each_entry(e, &partition->muxmodes, node) {
732 struct omap_mux *m = &e->mux;
733
734 (void)debugfs_create_file(m->muxnames[0], S_IWUSR | S_IRUGO,
735 mux_dbg_dir, m,
736 &omap_mux_dbg_signal_fops);
737 }
738}
739
740static void __init omap_mux_dbg_init(void)
741{
742 struct omap_mux_partition *partition;
743 static struct dentry *mux_dbg_board_dir;
744
745 mux_dbg_dir = debugfs_create_dir("omap_mux", NULL);
746 if (!mux_dbg_dir)
747 return;
748
749 mux_dbg_board_dir = debugfs_create_dir("board", mux_dbg_dir);
750 if (!mux_dbg_board_dir)
751 return;
752
753 list_for_each_entry(partition, &mux_partitions, node) {
754 omap_mux_dbg_create_entry(partition, mux_dbg_dir);
755 (void)debugfs_create_file(partition->name, S_IRUGO,
756 mux_dbg_board_dir, partition,
757 &omap_mux_dbg_board_fops);
758 }
759}
760
761#else
762static inline void omap_mux_dbg_init(void)
763{
764}
765#endif /* CONFIG_DEBUG_FS */
766
767static void __init omap_mux_free_names(struct omap_mux *m)
768{
769 int i;
770
771 for (i = 0; i < OMAP_MUX_NR_MODES; i++)
772 kfree(m->muxnames[i]);
773
774#ifdef CONFIG_DEBUG_FS
775 for (i = 0; i < OMAP_MUX_NR_SIDES; i++)
776 kfree(m->balls[i]);
777#endif
778
779}
780
781/* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */
782int __init omap_mux_late_init(void)
783{
784 struct omap_mux_partition *partition;
785 int ret;
786
787 list_for_each_entry(partition, &mux_partitions, node) {
788 struct omap_mux_entry *e, *tmp;
789 list_for_each_entry_safe(e, tmp, &partition->muxmodes, node) {
790 struct omap_mux *m = &e->mux;
791 u16 mode = omap_mux_read(partition, m->reg_offset);
792
793 if (OMAP_MODE_GPIO(partition, mode))
794 continue;
795
796#ifndef CONFIG_DEBUG_FS
797 mutex_lock(&muxmode_mutex);
798 list_del(&e->node);
799 mutex_unlock(&muxmode_mutex);
800 omap_mux_free_names(m);
801 kfree(m);
802#endif
803 }
804 }
805
806 omap_mux_dbg_init();
807
808 /* see pinctrl-single-omap for the wake-up interrupt handling */
809 if (of_have_populated_dt())
810 return 0;
811
812 ret = request_irq(omap_prcm_event_to_irq("io"),
813 omap_hwmod_mux_handle_irq, IRQF_SHARED | IRQF_NO_SUSPEND,
814 "hwmod_io", omap_mux_late_init);
815
816 if (ret)
817 pr_warn("mux: Failed to setup hwmod io irq %d\n", ret);
818
819 return 0;
820}
821
822static void __init omap_mux_package_fixup(struct omap_mux *p,
823 struct omap_mux *superset)
824{
825 while (p->reg_offset != OMAP_MUX_TERMINATOR) {
826 struct omap_mux *s = superset;
827 int found = 0;
828
829 while (s->reg_offset != OMAP_MUX_TERMINATOR) {
830 if (s->reg_offset == p->reg_offset) {
831 *s = *p;
832 found++;
833 break;
834 }
835 s++;
836 }
837 if (!found)
838 pr_err("%s: Unknown entry offset 0x%x\n", __func__,
839 p->reg_offset);
840 p++;
841 }
842}
843
844#ifdef CONFIG_DEBUG_FS
845
846static void __init omap_mux_package_init_balls(struct omap_ball *b,
847 struct omap_mux *superset)
848{
849 while (b->reg_offset != OMAP_MUX_TERMINATOR) {
850 struct omap_mux *s = superset;
851 int found = 0;
852
853 while (s->reg_offset != OMAP_MUX_TERMINATOR) {
854 if (s->reg_offset == b->reg_offset) {
855 s->balls[0] = b->balls[0];
856 s->balls[1] = b->balls[1];
857 found++;
858 break;
859 }
860 s++;
861 }
862 if (!found)
863 pr_err("%s: Unknown ball offset 0x%x\n", __func__,
864 b->reg_offset);
865 b++;
866 }
867}
868
869#else /* CONFIG_DEBUG_FS */
870
871static inline void omap_mux_package_init_balls(struct omap_ball *b,
872 struct omap_mux *superset)
873{
874}
875
876#endif /* CONFIG_DEBUG_FS */
877
878static int __init omap_mux_setup(char *options)
879{
880 if (!options)
881 return 0;
882
883 omap_mux_options = options;
884
885 return 1;
886}
887__setup("omap_mux=", omap_mux_setup);
888
889/*
890 * Note that the omap_mux=some.signal1=0x1234,some.signal2=0x1234
891 * cmdline options only override the bootloader values.
892 * During development, please enable CONFIG_DEBUG_FS, and use the
893 * signal specific entries under debugfs.
894 */
895static void __init omap_mux_set_cmdline_signals(void)
896{
897 char *options, *next_opt, *token;
898
899 if (!omap_mux_options)
900 return;
901
902 options = kstrdup(omap_mux_options, GFP_KERNEL);
903 if (!options)
904 return;
905
906 next_opt = options;
907
908 while ((token = strsep(&next_opt, ",")) != NULL) {
909 char *keyval, *name;
910 u16 val;
911
912 keyval = token;
913 name = strsep(&keyval, "=");
914 if (name) {
915 int res;
916
917 res = kstrtou16(keyval, 0x10, &val);
918 if (res < 0)
919 continue;
920
921 omap_mux_init_signal(name, (u16)val);
922 }
923 }
924
925 kfree(options);
926}
927
928static int __init omap_mux_copy_names(struct omap_mux *src,
929 struct omap_mux *dst)
930{
931 int i;
932
933 for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
934 if (src->muxnames[i]) {
935 dst->muxnames[i] = kstrdup(src->muxnames[i],
936 GFP_KERNEL);
937 if (!dst->muxnames[i])
938 goto free;
939 }
940 }
941
942#ifdef CONFIG_DEBUG_FS
943 for (i = 0; i < OMAP_MUX_NR_SIDES; i++) {
944 if (src->balls[i]) {
945 dst->balls[i] = kstrdup(src->balls[i], GFP_KERNEL);
946 if (!dst->balls[i])
947 goto free;
948 }
949 }
950#endif
951
952 return 0;
953
954free:
955 omap_mux_free_names(dst);
956 return -ENOMEM;
957
958}
959
960#endif /* CONFIG_OMAP_MUX */
961
962static struct omap_mux *omap_mux_get_by_gpio(
963 struct omap_mux_partition *partition,
964 int gpio)
965{
966 struct omap_mux_entry *e;
967 struct omap_mux *ret = NULL;
968
969 list_for_each_entry(e, &partition->muxmodes, node) {
970 struct omap_mux *m = &e->mux;
971 if (m->gpio == gpio) {
972 ret = m;
973 break;
974 }
975 }
976
977 return ret;
978}
979
980/* Needed for dynamic muxing of GPIO pins for off-idle */
981u16 omap_mux_get_gpio(int gpio)
982{
983 struct omap_mux_partition *partition;
984 struct omap_mux *m = NULL;
985
986 list_for_each_entry(partition, &mux_partitions, node) {
987 m = omap_mux_get_by_gpio(partition, gpio);
988 if (m)
989 return omap_mux_read(partition, m->reg_offset);
990 }
991
992 if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
993 pr_err("%s: Could not get gpio%i\n", __func__, gpio);
994
995 return OMAP_MUX_TERMINATOR;
996}
997
998/* Needed for dynamic muxing of GPIO pins for off-idle */
999void omap_mux_set_gpio(u16 val, int gpio)
1000{
1001 struct omap_mux_partition *partition;
1002 struct omap_mux *m = NULL;
1003
1004 list_for_each_entry(partition, &mux_partitions, node) {
1005 m = omap_mux_get_by_gpio(partition, gpio);
1006 if (m) {
1007 omap_mux_write(partition, val, m->reg_offset);
1008 return;
1009 }
1010 }
1011
1012 if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
1013 pr_err("%s: Could not set gpio%i\n", __func__, gpio);
1014}
1015
1016static struct omap_mux * __init omap_mux_list_add(
1017 struct omap_mux_partition *partition,
1018 struct omap_mux *src)
1019{
1020 struct omap_mux_entry *entry;
1021 struct omap_mux *m;
1022
1023 entry = kzalloc(sizeof(struct omap_mux_entry), GFP_KERNEL);
1024 if (!entry)
1025 return NULL;
1026
1027 m = &entry->mux;
1028 entry->mux = *src;
1029
1030#ifdef CONFIG_OMAP_MUX
1031 if (omap_mux_copy_names(src, m)) {
1032 kfree(entry);
1033 return NULL;
1034 }
1035#endif
1036
1037 mutex_lock(&muxmode_mutex);
1038 list_add_tail(&entry->node, &partition->muxmodes);
1039 mutex_unlock(&muxmode_mutex);
1040
1041 return m;
1042}
1043
1044/*
1045 * Note if CONFIG_OMAP_MUX is not selected, we will only initialize
1046 * the GPIO to mux offset mapping that is needed for dynamic muxing
1047 * of GPIO pins for off-idle.
1048 */
1049static void __init omap_mux_init_list(struct omap_mux_partition *partition,
1050 struct omap_mux *superset)
1051{
1052 while (superset->reg_offset != OMAP_MUX_TERMINATOR) {
1053 struct omap_mux *entry;
1054
1055#ifdef CONFIG_OMAP_MUX
1056 if (!superset->muxnames[0]) {
1057 superset++;
1058 continue;
1059 }
1060#else
1061 /* Skip pins that are not muxed as GPIO by bootloader */
1062 if (!OMAP_MODE_GPIO(partition, omap_mux_read(partition,
1063 superset->reg_offset))) {
1064 superset++;
1065 continue;
1066 }
1067#endif
1068
1069 entry = omap_mux_list_add(partition, superset);
1070 if (!entry) {
1071 pr_err("%s: Could not add entry\n", __func__);
1072 return;
1073 }
1074 superset++;
1075 }
1076}
1077
1078#ifdef CONFIG_OMAP_MUX
1079
1080static void omap_mux_init_package(struct omap_mux *superset,
1081 struct omap_mux *package_subset,
1082 struct omap_ball *package_balls)
1083{
1084 if (package_subset)
1085 omap_mux_package_fixup(package_subset, superset);
1086 if (package_balls)
1087 omap_mux_package_init_balls(package_balls, superset);
1088}
1089
1090static void __init omap_mux_init_signals(struct omap_mux_partition *partition,
1091 struct omap_board_mux *board_mux)
1092{
1093 omap_mux_set_cmdline_signals();
1094 omap_mux_write_array(partition, board_mux);
1095}
1096
1097#else
1098
1099static void omap_mux_init_package(struct omap_mux *superset,
1100 struct omap_mux *package_subset,
1101 struct omap_ball *package_balls)
1102{
1103}
1104
1105static void __init omap_mux_init_signals(struct omap_mux_partition *partition,
1106 struct omap_board_mux *board_mux)
1107{
1108}
1109
1110#endif
1111
1112static u32 mux_partitions_cnt;
1113
1114int __init omap_mux_init(const char *name, u32 flags,
1115 u32 mux_pbase, u32 mux_size,
1116 struct omap_mux *superset,
1117 struct omap_mux *package_subset,
1118 struct omap_board_mux *board_mux,
1119 struct omap_ball *package_balls)
1120{
1121 struct omap_mux_partition *partition;
1122
1123 partition = kzalloc(sizeof(struct omap_mux_partition), GFP_KERNEL);
1124 if (!partition)
1125 return -ENOMEM;
1126
1127 partition->name = name;
1128 partition->flags = flags;
1129 partition->gpio = flags & OMAP_MUX_MODE7;
1130 partition->size = mux_size;
1131 partition->phys = mux_pbase;
1132 partition->base = ioremap(mux_pbase, mux_size);
1133 if (!partition->base) {
1134 pr_err("%s: Could not ioremap mux partition at 0x%08x\n",
1135 __func__, partition->phys);
1136 kfree(partition);
1137 return -ENODEV;
1138 }
1139
1140 INIT_LIST_HEAD(&partition->muxmodes);
1141
1142 list_add_tail(&partition->node, &mux_partitions);
1143 mux_partitions_cnt++;
1144 pr_info("%s: Add partition: #%d: %s, flags: %x\n", __func__,
1145 mux_partitions_cnt, partition->name, partition->flags);
1146
1147 omap_mux_init_package(superset, package_subset, package_balls);
1148 omap_mux_init_list(partition, superset);
1149 omap_mux_init_signals(partition, board_mux);
1150
1151 return 0;
1152}
1153
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
deleted file mode 100644
index d121fb6df4e6..000000000000
--- a/arch/arm/mach-omap2/mux.h
+++ /dev/null
@@ -1,352 +0,0 @@
1/*
2 * Copyright (C) 2009 Nokia
3 * Copyright (C) 2009-2010 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include "mux34xx.h"
11
12#define OMAP_MUX_TERMINATOR 0xffff
13
14/* 34xx mux mode options for each pin. See TRM for options */
15#define OMAP_MUX_MODE0 0
16#define OMAP_MUX_MODE1 1
17#define OMAP_MUX_MODE2 2
18#define OMAP_MUX_MODE3 3
19#define OMAP_MUX_MODE4 4
20#define OMAP_MUX_MODE5 5
21#define OMAP_MUX_MODE6 6
22#define OMAP_MUX_MODE7 7
23
24/* 24xx/34xx mux bit defines */
25#define OMAP_PULL_ENA (1 << 3)
26#define OMAP_PULL_UP (1 << 4)
27#define OMAP_ALTELECTRICALSEL (1 << 5)
28
29/* omap3/4/5 specific mux bit defines */
30#define OMAP_INPUT_EN (1 << 8)
31#define OMAP_OFF_EN (1 << 9)
32#define OMAP_OFFOUT_EN (1 << 10)
33#define OMAP_OFFOUT_VAL (1 << 11)
34#define OMAP_OFF_PULL_EN (1 << 12)
35#define OMAP_OFF_PULL_UP (1 << 13)
36#define OMAP_WAKEUP_EN (1 << 14)
37#define OMAP_WAKEUP_EVENT (1 << 15)
38
39/* Active pin states */
40#define OMAP_PIN_OUTPUT 0
41#define OMAP_PIN_INPUT OMAP_INPUT_EN
42#define OMAP_PIN_INPUT_PULLUP (OMAP_PULL_ENA | OMAP_INPUT_EN \
43 | OMAP_PULL_UP)
44#define OMAP_PIN_INPUT_PULLDOWN (OMAP_PULL_ENA | OMAP_INPUT_EN)
45
46/* Off mode states */
47#define OMAP_PIN_OFF_NONE 0
48#define OMAP_PIN_OFF_OUTPUT_HIGH (OMAP_OFF_EN | OMAP_OFFOUT_EN \
49 | OMAP_OFFOUT_VAL)
50#define OMAP_PIN_OFF_OUTPUT_LOW (OMAP_OFF_EN | OMAP_OFFOUT_EN)
51#define OMAP_PIN_OFF_INPUT_PULLUP (OMAP_OFF_EN | OMAP_OFF_PULL_EN \
52 | OMAP_OFF_PULL_UP)
53#define OMAP_PIN_OFF_INPUT_PULLDOWN (OMAP_OFF_EN | OMAP_OFF_PULL_EN)
54#define OMAP_PIN_OFF_WAKEUPENABLE OMAP_WAKEUP_EN
55
56#define OMAP_MODE_GPIO(partition, x) (((x) & OMAP_MUX_MODE7) == \
57 partition->gpio)
58#define OMAP_MODE_UART(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE0)
59
60/* Flags for omapX_mux_init */
61#define OMAP_PACKAGE_MASK 0xffff
62#define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */
63#define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */
64#define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */
65#define OMAP_PACKAGE_CBC 3 /* 515-pin 0.50 0.65 */
66
67#define OMAP_MUX_NR_MODES 8 /* Available modes */
68#define OMAP_MUX_NR_SIDES 2 /* Bottom & top */
69
70/*
71 * omap_mux_init flags definition:
72 *
73 * OMAP_GPIO_MUX_MODE, bits 0-2: gpio muxing mode, same like pad control
74 * register which includes values from 0-7.
75 * OMAP_MUX_REG_8BIT: Ensure that access to padconf is done in 8 bits.
76 * The default value is 16 bits.
77 */
78#define OMAP_MUX_GPIO_IN_MODE0 OMAP_MUX_MODE0
79#define OMAP_MUX_GPIO_IN_MODE1 OMAP_MUX_MODE1
80#define OMAP_MUX_GPIO_IN_MODE2 OMAP_MUX_MODE2
81#define OMAP_MUX_GPIO_IN_MODE3 OMAP_MUX_MODE3
82#define OMAP_MUX_GPIO_IN_MODE4 OMAP_MUX_MODE4
83#define OMAP_MUX_GPIO_IN_MODE5 OMAP_MUX_MODE5
84#define OMAP_MUX_GPIO_IN_MODE6 OMAP_MUX_MODE6
85#define OMAP_MUX_GPIO_IN_MODE7 OMAP_MUX_MODE7
86#define OMAP_MUX_REG_8BIT (1 << 3)
87
88/**
89 * struct omap_board_data - board specific device data
90 * @id: instance id
91 * @flags: additional flags for platform init code
92 * @pads: array of device specific pads
93 * @pads_cnt: ARRAY_SIZE() of pads
94 */
95struct omap_board_data {
96 int id;
97 u32 flags;
98 struct omap_device_pad *pads;
99 int pads_cnt;
100};
101
102/**
103 * struct mux_partition - contain partition related information
104 * @name: name of the current partition
105 * @flags: flags specific to this partition
106 * @gpio: gpio mux mode
107 * @phys: physical address
108 * @size: partition size
109 * @base: virtual address after ioremap
110 * @muxmodes: list of nodes that belong to a partition
111 * @node: list node for the partitions linked list
112 */
113struct omap_mux_partition {
114 const char *name;
115 u32 flags;
116 u32 gpio;
117 u32 phys;
118 u32 size;
119 void __iomem *base;
120 struct list_head muxmodes;
121 struct list_head node;
122};
123
124/**
125 * struct omap_mux - data for omap mux register offset and it's value
126 * @reg_offset: mux register offset from the mux base
127 * @gpio: GPIO number
128 * @muxnames: available signal modes for a ball
129 * @balls: available balls on the package
130 */
131struct omap_mux {
132 u16 reg_offset;
133 u16 gpio;
134#ifdef CONFIG_OMAP_MUX
135 char *muxnames[OMAP_MUX_NR_MODES];
136#ifdef CONFIG_DEBUG_FS
137 char *balls[OMAP_MUX_NR_SIDES];
138#endif
139#endif
140};
141
142/**
143 * struct omap_ball - data for balls on omap package
144 * @reg_offset: mux register offset from the mux base
145 * @balls: available balls on the package
146 */
147struct omap_ball {
148 u16 reg_offset;
149 char *balls[OMAP_MUX_NR_SIDES];
150};
151
152/**
153 * struct omap_board_mux - data for initializing mux registers
154 * @reg_offset: mux register offset from the mux base
155 * @mux_value: desired mux value to set
156 */
157struct omap_board_mux {
158 u16 reg_offset;
159 u16 value;
160};
161
162#define OMAP_DEVICE_PAD_REMUX BIT(1) /* Dynamically remux a pad,
163 needs enable, idle and off
164 values */
165#define OMAP_DEVICE_PAD_WAKEUP BIT(0) /* Pad is wake-up capable */
166
167/**
168 * struct omap_device_pad - device specific pad configuration
169 * @name: signal name
170 * @flags: pad specific runtime flags
171 * @enable: runtime value for a pad
172 * @idle: idle value for a pad
173 * @off: off value for a pad, defaults to safe mode
174 * @partition: mux partition
175 * @mux: mux register
176 */
177struct omap_device_pad {
178 char *name;
179 u8 flags;
180 u16 enable;
181 u16 idle;
182 u16 off;
183 struct omap_mux_partition *partition;
184 struct omap_mux *mux;
185};
186
187struct omap_hwmod_mux_info;
188
189#define OMAP_MUX_STATIC(signal, mode) \
190{ \
191 .name = (signal), \
192 .enable = (mode), \
193}
194
195#if defined(CONFIG_OMAP_MUX)
196
197/**
198 * omap_mux_init_gpio - initialize a signal based on the GPIO number
199 * @gpio: GPIO number
200 * @val: Options for the mux register value
201 */
202int omap_mux_init_gpio(int gpio, int val);
203
204/**
205 * omap_mux_init_signal - initialize a signal based on the signal name
206 * @muxname: Mux name in mode0_name.signal_name format
207 * @val: Options for the mux register value
208 */
209int omap_mux_init_signal(const char *muxname, int val);
210
211/**
212 * omap_hwmod_mux_init - initialize hwmod specific mux data
213 * @bpads: Board specific device signal names
214 * @nr_pads: Number of signal names for the device
215 */
216extern struct omap_hwmod_mux_info *
217omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads);
218
219/**
220 * omap_hwmod_mux - omap hwmod specific pin muxing
221 * @hmux: Pads for a hwmod
222 * @state: Desired _HWMOD_STATE
223 *
224 * Called only from omap_hwmod.c, do not use.
225 */
226void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state);
227
228int omap_mux_get_by_name(const char *muxname,
229 struct omap_mux_partition **found_partition,
230 struct omap_mux **found_mux);
231#else
232
233static inline int omap_mux_get_by_name(const char *muxname,
234 struct omap_mux_partition **found_partition,
235 struct omap_mux **found_mux)
236{
237 return 0;
238}
239
240static inline int omap_mux_init_gpio(int gpio, int val)
241{
242 return 0;
243}
244static inline int omap_mux_init_signal(char *muxname, int val)
245{
246 return 0;
247}
248
249static inline struct omap_hwmod_mux_info *
250omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
251{
252 return NULL;
253}
254
255static inline void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
256{
257}
258
259static struct omap_board_mux *board_mux __maybe_unused;
260
261#endif
262
263/**
264 * omap_mux_get_gpio() - get mux register value based on GPIO number
265 * @gpio: GPIO number
266 *
267 */
268u16 omap_mux_get_gpio(int gpio);
269
270/**
271 * omap_mux_set_gpio() - set mux register value based on GPIO number
272 * @val: New mux register value
273 * @gpio: GPIO number
274 *
275 */
276void omap_mux_set_gpio(u16 val, int gpio);
277
278/**
279 * omap_mux_get() - get a mux partition by name
280 * @name: Name of the mux partition
281 *
282 */
283struct omap_mux_partition *omap_mux_get(const char *name);
284
285/**
286 * omap_mux_read() - read mux register
287 * @partition: Mux partition
288 * @mux_offset: Offset of the mux register
289 *
290 */
291u16 omap_mux_read(struct omap_mux_partition *p, u16 mux_offset);
292
293/**
294 * omap_mux_write() - write mux register
295 * @partition: Mux partition
296 * @val: New mux register value
297 * @mux_offset: Offset of the mux register
298 *
299 * This should be only needed for dynamic remuxing of non-gpio signals.
300 */
301void omap_mux_write(struct omap_mux_partition *p, u16 val, u16 mux_offset);
302
303/**
304 * omap_mux_write_array() - write an array of mux registers
305 * @partition: Mux partition
306 * @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR
307 *
308 * This should be only needed for dynamic remuxing of non-gpio signals.
309 */
310void omap_mux_write_array(struct omap_mux_partition *p,
311 struct omap_board_mux *board_mux);
312
313/**
314 * omap2420_mux_init() - initialize mux system with board specific set
315 * @board_mux: Board specific mux table
316 * @flags: OMAP package type used for the board
317 */
318int omap2420_mux_init(struct omap_board_mux *board_mux, int flags);
319
320/**
321 * omap2430_mux_init() - initialize mux system with board specific set
322 * @board_mux: Board specific mux table
323 * @flags: OMAP package type used for the board
324 */
325int omap2430_mux_init(struct omap_board_mux *board_mux, int flags);
326
327/**
328 * omap3_mux_init() - initialize mux system with board specific set
329 * @board_mux: Board specific mux table
330 * @flags: OMAP package type used for the board
331 */
332int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
333
334/**
335 * omap4_mux_init() - initialize mux system with board specific set
336 * @board_subset: Board specific mux table
337 * @board_wkup_subset: Board specific mux table for wakeup instance
338 * @flags: OMAP package type used for the board
339 */
340int omap4_mux_init(struct omap_board_mux *board_subset,
341 struct omap_board_mux *board_wkup_subset, int flags);
342
343/**
344 * omap_mux_init - private mux init function, do not call
345 */
346int omap_mux_init(const char *name, u32 flags,
347 u32 mux_pbase, u32 mux_size,
348 struct omap_mux *superset,
349 struct omap_mux *package_subset,
350 struct omap_board_mux *board_mux,
351 struct omap_ball *package_balls);
352
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
deleted file mode 100644
index 393e687f99e2..000000000000
--- a/arch/arm/mach-omap2/mux34xx.c
+++ /dev/null
@@ -1,2061 +0,0 @@
1/*
2 * Copyright (C) 2009 Nokia
3 * Copyright (C) 2009 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/module.h>
11#include <linux/init.h>
12
13#include "mux.h"
14
15#ifdef CONFIG_OMAP_MUX
16
17#define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
18{ \
19 .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
20 .gpio = (g), \
21 .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
22}
23
24#else
25
26#define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
27{ \
28 .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
29 .gpio = (g), \
30}
31
32#endif
33
34#define _OMAP3_BALLENTRY(M0, bb, bt) \
35{ \
36 .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
37 .balls = { bb, bt }, \
38}
39
40/*
41 * Superset of all mux modes for omap3
42 */
43static struct omap_mux __initdata omap3_muxmodes[] = {
44 _OMAP3_MUXENTRY(CAM_D0, 99,
45 "cam_d0", NULL, NULL, NULL,
46 "gpio_99", NULL, NULL, "safe_mode"),
47 _OMAP3_MUXENTRY(CAM_D1, 100,
48 "cam_d1", NULL, NULL, NULL,
49 "gpio_100", NULL, NULL, "safe_mode"),
50 _OMAP3_MUXENTRY(CAM_D10, 109,
51 "cam_d10", NULL, NULL, NULL,
52 "gpio_109", "hw_dbg8", NULL, "safe_mode"),
53 _OMAP3_MUXENTRY(CAM_D11, 110,
54 "cam_d11", NULL, NULL, NULL,
55 "gpio_110", "hw_dbg9", NULL, "safe_mode"),
56 _OMAP3_MUXENTRY(CAM_D2, 101,
57 "cam_d2", NULL, NULL, NULL,
58 "gpio_101", "hw_dbg4", NULL, "safe_mode"),
59 _OMAP3_MUXENTRY(CAM_D3, 102,
60 "cam_d3", NULL, NULL, NULL,
61 "gpio_102", "hw_dbg5", NULL, "safe_mode"),
62 _OMAP3_MUXENTRY(CAM_D4, 103,
63 "cam_d4", NULL, NULL, NULL,
64 "gpio_103", "hw_dbg6", NULL, "safe_mode"),
65 _OMAP3_MUXENTRY(CAM_D5, 104,
66 "cam_d5", NULL, NULL, NULL,
67 "gpio_104", "hw_dbg7", NULL, "safe_mode"),
68 _OMAP3_MUXENTRY(CAM_D6, 105,
69 "cam_d6", NULL, NULL, NULL,
70 "gpio_105", NULL, NULL, "safe_mode"),
71 _OMAP3_MUXENTRY(CAM_D7, 106,
72 "cam_d7", NULL, NULL, NULL,
73 "gpio_106", NULL, NULL, "safe_mode"),
74 _OMAP3_MUXENTRY(CAM_D8, 107,
75 "cam_d8", NULL, NULL, NULL,
76 "gpio_107", NULL, NULL, "safe_mode"),
77 _OMAP3_MUXENTRY(CAM_D9, 108,
78 "cam_d9", NULL, NULL, NULL,
79 "gpio_108", NULL, NULL, "safe_mode"),
80 _OMAP3_MUXENTRY(CAM_FLD, 98,
81 "cam_fld", NULL, "cam_global_reset", NULL,
82 "gpio_98", "hw_dbg3", NULL, "safe_mode"),
83 _OMAP3_MUXENTRY(CAM_HS, 94,
84 "cam_hs", NULL, NULL, NULL,
85 "gpio_94", "hw_dbg0", NULL, "safe_mode"),
86 _OMAP3_MUXENTRY(CAM_PCLK, 97,
87 "cam_pclk", NULL, NULL, NULL,
88 "gpio_97", "hw_dbg2", NULL, "safe_mode"),
89 _OMAP3_MUXENTRY(CAM_STROBE, 126,
90 "cam_strobe", NULL, NULL, NULL,
91 "gpio_126", "hw_dbg11", NULL, "safe_mode"),
92 _OMAP3_MUXENTRY(CAM_VS, 95,
93 "cam_vs", NULL, NULL, NULL,
94 "gpio_95", "hw_dbg1", NULL, "safe_mode"),
95 _OMAP3_MUXENTRY(CAM_WEN, 167,
96 "cam_wen", NULL, "cam_shutter", NULL,
97 "gpio_167", "hw_dbg10", NULL, "safe_mode"),
98 _OMAP3_MUXENTRY(CAM_XCLKA, 96,
99 "cam_xclka", NULL, NULL, NULL,
100 "gpio_96", NULL, NULL, "safe_mode"),
101 _OMAP3_MUXENTRY(CAM_XCLKB, 111,
102 "cam_xclkb", NULL, NULL, NULL,
103 "gpio_111", NULL, NULL, "safe_mode"),
104 _OMAP3_MUXENTRY(CSI2_DX0, 112,
105 "csi2_dx0", NULL, NULL, NULL,
106 "gpio_112", NULL, NULL, "safe_mode"),
107 _OMAP3_MUXENTRY(CSI2_DX1, 114,
108 "csi2_dx1", NULL, NULL, NULL,
109 "gpio_114", NULL, NULL, "safe_mode"),
110 _OMAP3_MUXENTRY(CSI2_DY0, 113,
111 "csi2_dy0", NULL, NULL, NULL,
112 "gpio_113", NULL, NULL, "safe_mode"),
113 _OMAP3_MUXENTRY(CSI2_DY1, 115,
114 "csi2_dy1", NULL, NULL, NULL,
115 "gpio_115", NULL, NULL, "safe_mode"),
116 _OMAP3_MUXENTRY(DSS_ACBIAS, 69,
117 "dss_acbias", NULL, NULL, NULL,
118 "gpio_69", NULL, NULL, "safe_mode"),
119 _OMAP3_MUXENTRY(DSS_DATA0, 70,
120 "dss_data0", NULL, "uart1_cts", NULL,
121 "gpio_70", NULL, NULL, "safe_mode"),
122 _OMAP3_MUXENTRY(DSS_DATA1, 71,
123 "dss_data1", NULL, "uart1_rts", NULL,
124 "gpio_71", NULL, NULL, "safe_mode"),
125 _OMAP3_MUXENTRY(DSS_DATA10, 80,
126 "dss_data10", NULL, NULL, NULL,
127 "gpio_80", NULL, NULL, "safe_mode"),
128 _OMAP3_MUXENTRY(DSS_DATA11, 81,
129 "dss_data11", NULL, NULL, NULL,
130 "gpio_81", NULL, NULL, "safe_mode"),
131 _OMAP3_MUXENTRY(DSS_DATA12, 82,
132 "dss_data12", NULL, NULL, NULL,
133 "gpio_82", NULL, NULL, "safe_mode"),
134 _OMAP3_MUXENTRY(DSS_DATA13, 83,
135 "dss_data13", NULL, NULL, NULL,
136 "gpio_83", NULL, NULL, "safe_mode"),
137 _OMAP3_MUXENTRY(DSS_DATA14, 84,
138 "dss_data14", NULL, NULL, NULL,
139 "gpio_84", NULL, NULL, "safe_mode"),
140 _OMAP3_MUXENTRY(DSS_DATA15, 85,
141 "dss_data15", NULL, NULL, NULL,
142 "gpio_85", NULL, NULL, "safe_mode"),
143 _OMAP3_MUXENTRY(DSS_DATA16, 86,
144 "dss_data16", NULL, NULL, NULL,
145 "gpio_86", NULL, NULL, "safe_mode"),
146 _OMAP3_MUXENTRY(DSS_DATA17, 87,
147 "dss_data17", NULL, NULL, NULL,
148 "gpio_87", NULL, NULL, "safe_mode"),
149 _OMAP3_MUXENTRY(DSS_DATA18, 88,
150 "dss_data18", NULL, "mcspi3_clk", "dss_data0",
151 "gpio_88", NULL, NULL, "safe_mode"),
152 _OMAP3_MUXENTRY(DSS_DATA19, 89,
153 "dss_data19", NULL, "mcspi3_simo", "dss_data1",
154 "gpio_89", NULL, NULL, "safe_mode"),
155 _OMAP3_MUXENTRY(DSS_DATA20, 90,
156 "dss_data20", NULL, "mcspi3_somi", "dss_data2",
157 "gpio_90", NULL, NULL, "safe_mode"),
158 _OMAP3_MUXENTRY(DSS_DATA21, 91,
159 "dss_data21", NULL, "mcspi3_cs0", "dss_data3",
160 "gpio_91", NULL, NULL, "safe_mode"),
161 _OMAP3_MUXENTRY(DSS_DATA22, 92,
162 "dss_data22", NULL, "mcspi3_cs1", "dss_data4",
163 "gpio_92", NULL, NULL, "safe_mode"),
164 _OMAP3_MUXENTRY(DSS_DATA23, 93,
165 "dss_data23", NULL, NULL, "dss_data5",
166 "gpio_93", NULL, NULL, "safe_mode"),
167 _OMAP3_MUXENTRY(DSS_DATA2, 72,
168 "dss_data2", NULL, NULL, NULL,
169 "gpio_72", NULL, NULL, "safe_mode"),
170 _OMAP3_MUXENTRY(DSS_DATA3, 73,
171 "dss_data3", NULL, NULL, NULL,
172 "gpio_73", NULL, NULL, "safe_mode"),
173 _OMAP3_MUXENTRY(DSS_DATA4, 74,
174 "dss_data4", NULL, "uart3_rx_irrx", NULL,
175 "gpio_74", NULL, NULL, "safe_mode"),
176 _OMAP3_MUXENTRY(DSS_DATA5, 75,
177 "dss_data5", NULL, "uart3_tx_irtx", NULL,
178 "gpio_75", NULL, NULL, "safe_mode"),
179 _OMAP3_MUXENTRY(DSS_DATA6, 76,
180 "dss_data6", NULL, "uart1_tx", NULL,
181 "gpio_76", "hw_dbg14", NULL, "safe_mode"),
182 _OMAP3_MUXENTRY(DSS_DATA7, 77,
183 "dss_data7", NULL, "uart1_rx", NULL,
184 "gpio_77", "hw_dbg15", NULL, "safe_mode"),
185 _OMAP3_MUXENTRY(DSS_DATA8, 78,
186 "dss_data8", NULL, NULL, NULL,
187 "gpio_78", "hw_dbg16", NULL, "safe_mode"),
188 _OMAP3_MUXENTRY(DSS_DATA9, 79,
189 "dss_data9", NULL, NULL, NULL,
190 "gpio_79", "hw_dbg17", NULL, "safe_mode"),
191 _OMAP3_MUXENTRY(DSS_HSYNC, 67,
192 "dss_hsync", NULL, NULL, NULL,
193 "gpio_67", "hw_dbg13", NULL, "safe_mode"),
194 _OMAP3_MUXENTRY(DSS_PCLK, 66,
195 "dss_pclk", NULL, NULL, NULL,
196 "gpio_66", "hw_dbg12", NULL, "safe_mode"),
197 _OMAP3_MUXENTRY(DSS_VSYNC, 68,
198 "dss_vsync", NULL, NULL, NULL,
199 "gpio_68", NULL, NULL, "safe_mode"),
200 _OMAP3_MUXENTRY(ETK_CLK, 12,
201 "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
202 "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", "hw_dbg0"),
203 _OMAP3_MUXENTRY(ETK_CTL, 13,
204 "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
205 "gpio_13", NULL, "hsusb1_tll_clk", "hw_dbg1"),
206 _OMAP3_MUXENTRY(ETK_D0, 14,
207 "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
208 "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", "hw_dbg2"),
209 _OMAP3_MUXENTRY(ETK_D1, 15,
210 "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
211 "gpio_15", "mm1_txse0", "hsusb1_tll_data1", "hw_dbg3"),
212 _OMAP3_MUXENTRY(ETK_D10, 24,
213 "etk_d10", NULL, "uart1_rx", "hsusb2_clk",
214 "gpio_24", NULL, "hsusb2_tll_clk", "hw_dbg12"),
215 _OMAP3_MUXENTRY(ETK_D11, 25,
216 "etk_d11", NULL, NULL, "hsusb2_stp",
217 "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", "hw_dbg13"),
218 _OMAP3_MUXENTRY(ETK_D12, 26,
219 "etk_d12", NULL, NULL, "hsusb2_dir",
220 "gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"),
221 _OMAP3_MUXENTRY(ETK_D13, 27,
222 "etk_d13", NULL, NULL, "hsusb2_nxt",
223 "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", "hw_dbg15"),
224 _OMAP3_MUXENTRY(ETK_D14, 28,
225 "etk_d14", NULL, NULL, "hsusb2_data0",
226 "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", "hw_dbg16"),
227 _OMAP3_MUXENTRY(ETK_D15, 29,
228 "etk_d15", NULL, NULL, "hsusb2_data1",
229 "gpio_29", "mm2_txse0", "hsusb2_tll_data1", "hw_dbg17"),
230 _OMAP3_MUXENTRY(ETK_D2, 16,
231 "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
232 "gpio_16", "mm1_txdat", "hsusb1_tll_data2", "hw_dbg4"),
233 _OMAP3_MUXENTRY(ETK_D3, 17,
234 "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
235 "gpio_17", NULL, "hsusb1_tll_data7", "hw_dbg5"),
236 _OMAP3_MUXENTRY(ETK_D4, 18,
237 "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
238 "gpio_18", NULL, "hsusb1_tll_data4", "hw_dbg6"),
239 _OMAP3_MUXENTRY(ETK_D5, 19,
240 "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
241 "gpio_19", NULL, "hsusb1_tll_data5", "hw_dbg7"),
242 _OMAP3_MUXENTRY(ETK_D6, 20,
243 "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
244 "gpio_20", NULL, "hsusb1_tll_data6", "hw_dbg8"),
245 _OMAP3_MUXENTRY(ETK_D7, 21,
246 "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
247 "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", "hw_dbg9"),
248 _OMAP3_MUXENTRY(ETK_D8, 22,
249 "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
250 "gpio_22", NULL, "hsusb1_tll_dir", "hw_dbg10"),
251 _OMAP3_MUXENTRY(ETK_D9, 23,
252 "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
253 "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", "hw_dbg11"),
254 _OMAP3_MUXENTRY(GPMC_A1, 34,
255 "gpmc_a1", NULL, NULL, NULL,
256 "gpio_34", NULL, NULL, "safe_mode"),
257 _OMAP3_MUXENTRY(GPMC_A10, 43,
258 "gpmc_a10", "sys_ndmareq3", NULL, NULL,
259 "gpio_43", NULL, NULL, "safe_mode"),
260 _OMAP3_MUXENTRY(GPMC_A2, 35,
261 "gpmc_a2", NULL, NULL, NULL,
262 "gpio_35", NULL, NULL, "safe_mode"),
263 _OMAP3_MUXENTRY(GPMC_A3, 36,
264 "gpmc_a3", NULL, NULL, NULL,
265 "gpio_36", NULL, NULL, "safe_mode"),
266 _OMAP3_MUXENTRY(GPMC_A4, 37,
267 "gpmc_a4", NULL, NULL, NULL,
268 "gpio_37", NULL, NULL, "safe_mode"),
269 _OMAP3_MUXENTRY(GPMC_A5, 38,
270 "gpmc_a5", NULL, NULL, NULL,
271 "gpio_38", NULL, NULL, "safe_mode"),
272 _OMAP3_MUXENTRY(GPMC_A6, 39,
273 "gpmc_a6", NULL, NULL, NULL,
274 "gpio_39", NULL, NULL, "safe_mode"),
275 _OMAP3_MUXENTRY(GPMC_A7, 40,
276 "gpmc_a7", NULL, NULL, NULL,
277 "gpio_40", NULL, NULL, "safe_mode"),
278 _OMAP3_MUXENTRY(GPMC_A8, 41,
279 "gpmc_a8", NULL, NULL, NULL,
280 "gpio_41", NULL, NULL, "safe_mode"),
281 _OMAP3_MUXENTRY(GPMC_A9, 42,
282 "gpmc_a9", "sys_ndmareq2", NULL, NULL,
283 "gpio_42", NULL, NULL, "safe_mode"),
284 _OMAP3_MUXENTRY(GPMC_CLK, 59,
285 "gpmc_clk", NULL, NULL, NULL,
286 "gpio_59", NULL, NULL, "safe_mode"),
287 _OMAP3_MUXENTRY(GPMC_D10, 46,
288 "gpmc_d10", NULL, NULL, NULL,
289 "gpio_46", NULL, NULL, "safe_mode"),
290 _OMAP3_MUXENTRY(GPMC_D11, 47,
291 "gpmc_d11", NULL, NULL, NULL,
292 "gpio_47", NULL, NULL, "safe_mode"),
293 _OMAP3_MUXENTRY(GPMC_D12, 48,
294 "gpmc_d12", NULL, NULL, NULL,
295 "gpio_48", NULL, NULL, "safe_mode"),
296 _OMAP3_MUXENTRY(GPMC_D13, 49,
297 "gpmc_d13", NULL, NULL, NULL,
298 "gpio_49", NULL, NULL, "safe_mode"),
299 _OMAP3_MUXENTRY(GPMC_D14, 50,
300 "gpmc_d14", NULL, NULL, NULL,
301 "gpio_50", NULL, NULL, "safe_mode"),
302 _OMAP3_MUXENTRY(GPMC_D15, 51,
303 "gpmc_d15", NULL, NULL, NULL,
304 "gpio_51", NULL, NULL, "safe_mode"),
305 _OMAP3_MUXENTRY(GPMC_D8, 44,
306 "gpmc_d8", NULL, NULL, NULL,
307 "gpio_44", NULL, NULL, "safe_mode"),
308 _OMAP3_MUXENTRY(GPMC_D9, 45,
309 "gpmc_d9", NULL, NULL, NULL,
310 "gpio_45", NULL, NULL, "safe_mode"),
311 _OMAP3_MUXENTRY(GPMC_NBE0_CLE, 60,
312 "gpmc_nbe0_cle", NULL, NULL, NULL,
313 "gpio_60", NULL, NULL, "safe_mode"),
314 _OMAP3_MUXENTRY(GPMC_NBE1, 61,
315 "gpmc_nbe1", NULL, NULL, NULL,
316 "gpio_61", NULL, NULL, "safe_mode"),
317 _OMAP3_MUXENTRY(GPMC_NCS1, 52,
318 "gpmc_ncs1", NULL, NULL, NULL,
319 "gpio_52", NULL, NULL, "safe_mode"),
320 _OMAP3_MUXENTRY(GPMC_NCS2, 53,
321 "gpmc_ncs2", NULL, NULL, NULL,
322 "gpio_53", NULL, NULL, "safe_mode"),
323 _OMAP3_MUXENTRY(GPMC_NCS3, 54,
324 "gpmc_ncs3", "sys_ndmareq0", NULL, NULL,
325 "gpio_54", NULL, NULL, "safe_mode"),
326 _OMAP3_MUXENTRY(GPMC_NCS4, 55,
327 "gpmc_ncs4", "sys_ndmareq1", "mcbsp4_clkx", "gpt9_pwm_evt",
328 "gpio_55", NULL, NULL, "safe_mode"),
329 _OMAP3_MUXENTRY(GPMC_NCS5, 56,
330 "gpmc_ncs5", "sys_ndmareq2", "mcbsp4_dr", "gpt10_pwm_evt",
331 "gpio_56", NULL, NULL, "safe_mode"),
332 _OMAP3_MUXENTRY(GPMC_NCS6, 57,
333 "gpmc_ncs6", "sys_ndmareq3", "mcbsp4_dx", "gpt11_pwm_evt",
334 "gpio_57", NULL, NULL, "safe_mode"),
335 _OMAP3_MUXENTRY(GPMC_NCS7, 58,
336 "gpmc_ncs7", "gpmc_io_dir", "mcbsp4_fsx", "gpt8_pwm_evt",
337 "gpio_58", NULL, NULL, "safe_mode"),
338 _OMAP3_MUXENTRY(GPMC_NWP, 62,
339 "gpmc_nwp", NULL, NULL, NULL,
340 "gpio_62", NULL, NULL, "safe_mode"),
341 _OMAP3_MUXENTRY(GPMC_WAIT1, 63,
342 "gpmc_wait1", NULL, NULL, NULL,
343 "gpio_63", NULL, NULL, "safe_mode"),
344 _OMAP3_MUXENTRY(GPMC_WAIT2, 64,
345 "gpmc_wait2", NULL, NULL, NULL,
346 "gpio_64", NULL, NULL, "safe_mode"),
347 _OMAP3_MUXENTRY(GPMC_WAIT3, 65,
348 "gpmc_wait3", "sys_ndmareq1", NULL, NULL,
349 "gpio_65", NULL, NULL, "safe_mode"),
350 _OMAP3_MUXENTRY(HDQ_SIO, 170,
351 "hdq_sio", "sys_altclk", "i2c2_sccbe", "i2c3_sccbe",
352 "gpio_170", NULL, NULL, "safe_mode"),
353 _OMAP3_MUXENTRY(HSUSB0_CLK, 120,
354 "hsusb0_clk", NULL, NULL, NULL,
355 "gpio_120", NULL, NULL, "safe_mode"),
356 _OMAP3_MUXENTRY(HSUSB0_DATA0, 125,
357 "hsusb0_data0", NULL, "uart3_tx_irtx", NULL,
358 "gpio_125", NULL, NULL, "safe_mode"),
359 _OMAP3_MUXENTRY(HSUSB0_DATA1, 130,
360 "hsusb0_data1", NULL, "uart3_rx_irrx", NULL,
361 "gpio_130", NULL, NULL, "safe_mode"),
362 _OMAP3_MUXENTRY(HSUSB0_DATA2, 131,
363 "hsusb0_data2", NULL, "uart3_rts_sd", NULL,
364 "gpio_131", NULL, NULL, "safe_mode"),
365 _OMAP3_MUXENTRY(HSUSB0_DATA3, 169,
366 "hsusb0_data3", NULL, "uart3_cts_rctx", NULL,
367 "gpio_169", NULL, NULL, "safe_mode"),
368 _OMAP3_MUXENTRY(HSUSB0_DATA4, 188,
369 "hsusb0_data4", NULL, NULL, NULL,
370 "gpio_188", NULL, NULL, "safe_mode"),
371 _OMAP3_MUXENTRY(HSUSB0_DATA5, 189,
372 "hsusb0_data5", NULL, NULL, NULL,
373 "gpio_189", NULL, NULL, "safe_mode"),
374 _OMAP3_MUXENTRY(HSUSB0_DATA6, 190,
375 "hsusb0_data6", NULL, NULL, NULL,
376 "gpio_190", NULL, NULL, "safe_mode"),
377 _OMAP3_MUXENTRY(HSUSB0_DATA7, 191,
378 "hsusb0_data7", NULL, NULL, NULL,
379 "gpio_191", NULL, NULL, "safe_mode"),
380 _OMAP3_MUXENTRY(HSUSB0_DIR, 122,
381 "hsusb0_dir", NULL, NULL, NULL,
382 "gpio_122", NULL, NULL, "safe_mode"),
383 _OMAP3_MUXENTRY(HSUSB0_NXT, 124,
384 "hsusb0_nxt", NULL, NULL, NULL,
385 "gpio_124", NULL, NULL, "safe_mode"),
386 _OMAP3_MUXENTRY(HSUSB0_STP, 121,
387 "hsusb0_stp", NULL, NULL, NULL,
388 "gpio_121", NULL, NULL, "safe_mode"),
389 _OMAP3_MUXENTRY(I2C2_SCL, 168,
390 "i2c2_scl", NULL, NULL, NULL,
391 "gpio_168", NULL, NULL, "safe_mode"),
392 _OMAP3_MUXENTRY(I2C2_SDA, 183,
393 "i2c2_sda", NULL, NULL, NULL,
394 "gpio_183", NULL, NULL, "safe_mode"),
395 _OMAP3_MUXENTRY(I2C3_SCL, 184,
396 "i2c3_scl", NULL, NULL, NULL,
397 "gpio_184", NULL, NULL, "safe_mode"),
398 _OMAP3_MUXENTRY(I2C3_SDA, 185,
399 "i2c3_sda", NULL, NULL, NULL,
400 "gpio_185", NULL, NULL, "safe_mode"),
401 _OMAP3_MUXENTRY(I2C4_SCL, 0,
402 "i2c4_scl", "sys_nvmode1", NULL, NULL,
403 NULL, NULL, NULL, "safe_mode"),
404 _OMAP3_MUXENTRY(I2C4_SDA, 0,
405 "i2c4_sda", "sys_nvmode2", NULL, NULL,
406 NULL, NULL, NULL, "safe_mode"),
407 _OMAP3_MUXENTRY(JTAG_EMU0, 11,
408 "jtag_emu0", NULL, NULL, NULL,
409 "gpio_11", NULL, NULL, "safe_mode"),
410 _OMAP3_MUXENTRY(JTAG_EMU1, 31,
411 "jtag_emu1", NULL, NULL, NULL,
412 "gpio_31", NULL, NULL, "safe_mode"),
413 _OMAP3_MUXENTRY(MCBSP1_CLKR, 156,
414 "mcbsp1_clkr", "mcspi4_clk", NULL, NULL,
415 "gpio_156", NULL, NULL, "safe_mode"),
416 _OMAP3_MUXENTRY(MCBSP1_CLKX, 162,
417 "mcbsp1_clkx", NULL, "mcbsp3_clkx", NULL,
418 "gpio_162", NULL, NULL, "safe_mode"),
419 _OMAP3_MUXENTRY(MCBSP1_DR, 159,
420 "mcbsp1_dr", "mcspi4_somi", "mcbsp3_dr", NULL,
421 "gpio_159", NULL, NULL, "safe_mode"),
422 _OMAP3_MUXENTRY(MCBSP1_DX, 158,
423 "mcbsp1_dx", "mcspi4_simo", "mcbsp3_dx", NULL,
424 "gpio_158", NULL, NULL, "safe_mode"),
425 _OMAP3_MUXENTRY(MCBSP1_FSR, 157,
426 "mcbsp1_fsr", NULL, "cam_global_reset", NULL,
427 "gpio_157", NULL, NULL, "safe_mode"),
428 _OMAP3_MUXENTRY(MCBSP1_FSX, 161,
429 "mcbsp1_fsx", "mcspi4_cs0", "mcbsp3_fsx", NULL,
430 "gpio_161", NULL, NULL, "safe_mode"),
431 _OMAP3_MUXENTRY(MCBSP2_CLKX, 117,
432 "mcbsp2_clkx", NULL, NULL, NULL,
433 "gpio_117", NULL, NULL, "safe_mode"),
434 _OMAP3_MUXENTRY(MCBSP2_DR, 118,
435 "mcbsp2_dr", NULL, NULL, NULL,
436 "gpio_118", NULL, NULL, "safe_mode"),
437 _OMAP3_MUXENTRY(MCBSP2_DX, 119,
438 "mcbsp2_dx", NULL, NULL, NULL,
439 "gpio_119", NULL, NULL, "safe_mode"),
440 _OMAP3_MUXENTRY(MCBSP2_FSX, 116,
441 "mcbsp2_fsx", NULL, NULL, NULL,
442 "gpio_116", NULL, NULL, "safe_mode"),
443 _OMAP3_MUXENTRY(MCBSP3_CLKX, 142,
444 "mcbsp3_clkx", "uart2_tx", NULL, NULL,
445 "gpio_142", "hsusb3_tll_data6", NULL, "safe_mode"),
446 _OMAP3_MUXENTRY(MCBSP3_DR, 141,
447 "mcbsp3_dr", "uart2_rts", NULL, NULL,
448 "gpio_141", "hsusb3_tll_data5", NULL, "safe_mode"),
449 _OMAP3_MUXENTRY(MCBSP3_DX, 140,
450 "mcbsp3_dx", "uart2_cts", NULL, NULL,
451 "gpio_140", "hsusb3_tll_data4", NULL, "safe_mode"),
452 _OMAP3_MUXENTRY(MCBSP3_FSX, 143,
453 "mcbsp3_fsx", "uart2_rx", NULL, NULL,
454 "gpio_143", "hsusb3_tll_data7", NULL, "safe_mode"),
455 _OMAP3_MUXENTRY(MCBSP4_CLKX, 152,
456 "mcbsp4_clkx", NULL, NULL, NULL,
457 "gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"),
458 _OMAP3_MUXENTRY(MCBSP4_DR, 153,
459 "mcbsp4_dr", NULL, NULL, NULL,
460 "gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"),
461 _OMAP3_MUXENTRY(MCBSP4_DX, 154,
462 "mcbsp4_dx", NULL, NULL, NULL,
463 "gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"),
464 _OMAP3_MUXENTRY(MCBSP4_FSX, 155,
465 "mcbsp4_fsx", NULL, NULL, NULL,
466 "gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"),
467 _OMAP3_MUXENTRY(MCBSP_CLKS, 160,
468 "mcbsp_clks", NULL, "cam_shutter", NULL,
469 "gpio_160", "uart1_cts", NULL, "safe_mode"),
470 _OMAP3_MUXENTRY(MCSPI1_CLK, 171,
471 "mcspi1_clk", "sdmmc2_dat4", NULL, NULL,
472 "gpio_171", NULL, NULL, "safe_mode"),
473 _OMAP3_MUXENTRY(MCSPI1_CS0, 174,
474 "mcspi1_cs0", "sdmmc2_dat7", NULL, NULL,
475 "gpio_174", NULL, NULL, "safe_mode"),
476 _OMAP3_MUXENTRY(MCSPI1_CS1, 175,
477 "mcspi1_cs1", NULL, NULL, "sdmmc3_cmd",
478 "gpio_175", NULL, NULL, "safe_mode"),
479 _OMAP3_MUXENTRY(MCSPI1_CS2, 176,
480 "mcspi1_cs2", NULL, NULL, "sdmmc3_clk",
481 "gpio_176", NULL, NULL, "safe_mode"),
482 _OMAP3_MUXENTRY(MCSPI1_CS3, 177,
483 "mcspi1_cs3", NULL, "hsusb2_tll_data2", "hsusb2_data2",
484 "gpio_177", "mm2_txdat", NULL, "safe_mode"),
485 _OMAP3_MUXENTRY(MCSPI1_SIMO, 172,
486 "mcspi1_simo", "sdmmc2_dat5", NULL, NULL,
487 "gpio_172", NULL, NULL, "safe_mode"),
488 _OMAP3_MUXENTRY(MCSPI1_SOMI, 173,
489 "mcspi1_somi", "sdmmc2_dat6", NULL, NULL,
490 "gpio_173", NULL, NULL, "safe_mode"),
491 _OMAP3_MUXENTRY(MCSPI2_CLK, 178,
492 "mcspi2_clk", NULL, "hsusb2_tll_data7", "hsusb2_data7",
493 "gpio_178", NULL, NULL, "safe_mode"),
494 _OMAP3_MUXENTRY(MCSPI2_CS0, 181,
495 "mcspi2_cs0", "gpt11_pwm_evt",
496 "hsusb2_tll_data6", "hsusb2_data6",
497 "gpio_181", NULL, NULL, "safe_mode"),
498 _OMAP3_MUXENTRY(MCSPI2_CS1, 182,
499 "mcspi2_cs1", "gpt8_pwm_evt",
500 "hsusb2_tll_data3", "hsusb2_data3",
501 "gpio_182", "mm2_txen_n", NULL, "safe_mode"),
502 _OMAP3_MUXENTRY(MCSPI2_SIMO, 179,
503 "mcspi2_simo", "gpt9_pwm_evt",
504 "hsusb2_tll_data4", "hsusb2_data4",
505 "gpio_179", NULL, NULL, "safe_mode"),
506 _OMAP3_MUXENTRY(MCSPI2_SOMI, 180,
507 "mcspi2_somi", "gpt10_pwm_evt",
508 "hsusb2_tll_data5", "hsusb2_data5",
509 "gpio_180", NULL, NULL, "safe_mode"),
510 _OMAP3_MUXENTRY(SDMMC1_CLK, 120,
511 "sdmmc1_clk", NULL, NULL, NULL,
512 "gpio_120", NULL, NULL, "safe_mode"),
513 _OMAP3_MUXENTRY(SDMMC1_CMD, 121,
514 "sdmmc1_cmd", NULL, NULL, NULL,
515 "gpio_121", NULL, NULL, "safe_mode"),
516 _OMAP3_MUXENTRY(SDMMC1_DAT0, 122,
517 "sdmmc1_dat0", NULL, NULL, NULL,
518 "gpio_122", NULL, NULL, "safe_mode"),
519 _OMAP3_MUXENTRY(SDMMC1_DAT1, 123,
520 "sdmmc1_dat1", NULL, NULL, NULL,
521 "gpio_123", NULL, NULL, "safe_mode"),
522 _OMAP3_MUXENTRY(SDMMC1_DAT2, 124,
523 "sdmmc1_dat2", NULL, NULL, NULL,
524 "gpio_124", NULL, NULL, "safe_mode"),
525 _OMAP3_MUXENTRY(SDMMC1_DAT3, 125,
526 "sdmmc1_dat3", NULL, NULL, NULL,
527 "gpio_125", NULL, NULL, "safe_mode"),
528 _OMAP3_MUXENTRY(SDMMC1_DAT4, 126,
529 "sdmmc1_dat4", NULL, "sim_io", NULL,
530 "gpio_126", NULL, NULL, "safe_mode"),
531 _OMAP3_MUXENTRY(SDMMC1_DAT5, 127,
532 "sdmmc1_dat5", NULL, "sim_clk", NULL,
533 "gpio_127", NULL, NULL, "safe_mode"),
534 _OMAP3_MUXENTRY(SDMMC1_DAT6, 128,
535 "sdmmc1_dat6", NULL, "sim_pwrctrl", NULL,
536 "gpio_128", NULL, NULL, "safe_mode"),
537 _OMAP3_MUXENTRY(SDMMC1_DAT7, 129,
538 "sdmmc1_dat7", NULL, "sim_rst", NULL,
539 "gpio_129", NULL, NULL, "safe_mode"),
540 _OMAP3_MUXENTRY(SDMMC2_CLK, 130,
541 "sdmmc2_clk", "mcspi3_clk", NULL, NULL,
542 "gpio_130", NULL, NULL, "safe_mode"),
543 _OMAP3_MUXENTRY(SDMMC2_CMD, 131,
544 "sdmmc2_cmd", "mcspi3_simo", NULL, NULL,
545 "gpio_131", NULL, NULL, "safe_mode"),
546 _OMAP3_MUXENTRY(SDMMC2_DAT0, 132,
547 "sdmmc2_dat0", "mcspi3_somi", NULL, NULL,
548 "gpio_132", NULL, NULL, "safe_mode"),
549 _OMAP3_MUXENTRY(SDMMC2_DAT1, 133,
550 "sdmmc2_dat1", NULL, NULL, NULL,
551 "gpio_133", NULL, NULL, "safe_mode"),
552 _OMAP3_MUXENTRY(SDMMC2_DAT2, 134,
553 "sdmmc2_dat2", "mcspi3_cs1", NULL, NULL,
554 "gpio_134", NULL, NULL, "safe_mode"),
555 _OMAP3_MUXENTRY(SDMMC2_DAT3, 135,
556 "sdmmc2_dat3", "mcspi3_cs0", NULL, NULL,
557 "gpio_135", NULL, NULL, "safe_mode"),
558 _OMAP3_MUXENTRY(SDMMC2_DAT4, 136,
559 "sdmmc2_dat4", "sdmmc2_dir_dat0", NULL, "sdmmc3_dat0",
560 "gpio_136", NULL, NULL, "safe_mode"),
561 _OMAP3_MUXENTRY(SDMMC2_DAT5, 137,
562 "sdmmc2_dat5", "sdmmc2_dir_dat1",
563 "cam_global_reset", "sdmmc3_dat1",
564 "gpio_137", "hsusb3_tll_stp", "mm3_rxdp", "safe_mode"),
565 _OMAP3_MUXENTRY(SDMMC2_DAT6, 138,
566 "sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2",
567 "gpio_138", "hsusb3_tll_dir", NULL, "safe_mode"),
568 _OMAP3_MUXENTRY(SDMMC2_DAT7, 139,
569 "sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3",
570 "gpio_139", "hsusb3_tll_nxt", "mm3_rxdm", "safe_mode"),
571 _OMAP3_MUXENTRY(SDRC_CKE0, 0,
572 "sdrc_cke0", NULL, NULL, NULL,
573 NULL, NULL, NULL, "safe_mode"),
574 _OMAP3_MUXENTRY(SDRC_CKE1, 0,
575 "sdrc_cke1", NULL, NULL, NULL,
576 NULL, NULL, NULL, "safe_mode"),
577 _OMAP3_MUXENTRY(SYS_BOOT0, 2,
578 "sys_boot0", NULL, NULL, NULL,
579 "gpio_2", NULL, NULL, "safe_mode"),
580 _OMAP3_MUXENTRY(SYS_BOOT1, 3,
581 "sys_boot1", NULL, NULL, NULL,
582 "gpio_3", NULL, NULL, "safe_mode"),
583 _OMAP3_MUXENTRY(SYS_BOOT2, 4,
584 "sys_boot2", NULL, NULL, NULL,
585 "gpio_4", NULL, NULL, "safe_mode"),
586 _OMAP3_MUXENTRY(SYS_BOOT3, 5,
587 "sys_boot3", NULL, NULL, NULL,
588 "gpio_5", NULL, NULL, "safe_mode"),
589 _OMAP3_MUXENTRY(SYS_BOOT4, 6,
590 "sys_boot4", "sdmmc2_dir_dat2", NULL, NULL,
591 "gpio_6", NULL, NULL, "safe_mode"),
592 _OMAP3_MUXENTRY(SYS_BOOT5, 7,
593 "sys_boot5", "sdmmc2_dir_dat3", NULL, NULL,
594 "gpio_7", NULL, NULL, "safe_mode"),
595 _OMAP3_MUXENTRY(SYS_BOOT6, 8,
596 "sys_boot6", NULL, NULL, NULL,
597 "gpio_8", NULL, NULL, "safe_mode"),
598 _OMAP3_MUXENTRY(SYS_CLKOUT1, 10,
599 "sys_clkout1", NULL, NULL, NULL,
600 "gpio_10", NULL, NULL, "safe_mode"),
601 _OMAP3_MUXENTRY(SYS_CLKOUT2, 186,
602 "sys_clkout2", NULL, NULL, NULL,
603 "gpio_186", NULL, NULL, "safe_mode"),
604 _OMAP3_MUXENTRY(SYS_CLKREQ, 1,
605 "sys_clkreq", NULL, NULL, NULL,
606 "gpio_1", NULL, NULL, "safe_mode"),
607 _OMAP3_MUXENTRY(SYS_NIRQ, 0,
608 "sys_nirq", NULL, NULL, NULL,
609 "gpio_0", NULL, NULL, "safe_mode"),
610 _OMAP3_MUXENTRY(SYS_NRESWARM, 30,
611 "sys_nreswarm", NULL, NULL, NULL,
612 "gpio_30", NULL, NULL, "safe_mode"),
613 _OMAP3_MUXENTRY(SYS_OFF_MODE, 9,
614 "sys_off_mode", NULL, NULL, NULL,
615 "gpio_9", NULL, NULL, "safe_mode"),
616 _OMAP3_MUXENTRY(UART1_CTS, 150,
617 "uart1_cts", "ssi1_rdy_tx", NULL, NULL,
618 "gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
619 _OMAP3_MUXENTRY(UART1_RTS, 149,
620 "uart1_rts", "ssi1_flag_tx", NULL, NULL,
621 "gpio_149", NULL, NULL, "safe_mode"),
622 _OMAP3_MUXENTRY(UART1_RX, 151,
623 "uart1_rx", "ssi1_wake_tx", "mcbsp1_clkr", "mcspi4_clk",
624 "gpio_151", NULL, NULL, "safe_mode"),
625 _OMAP3_MUXENTRY(UART1_TX, 148,
626 "uart1_tx", "ssi1_dat_tx", NULL, NULL,
627 "gpio_148", NULL, NULL, "safe_mode"),
628 _OMAP3_MUXENTRY(UART2_CTS, 144,
629 "uart2_cts", "mcbsp3_dx", "gpt9_pwm_evt", NULL,
630 "gpio_144", NULL, NULL, "safe_mode"),
631 _OMAP3_MUXENTRY(UART2_RTS, 145,
632 "uart2_rts", "mcbsp3_dr", "gpt10_pwm_evt", NULL,
633 "gpio_145", NULL, NULL, "safe_mode"),
634 _OMAP3_MUXENTRY(UART2_RX, 147,
635 "uart2_rx", "mcbsp3_fsx", "gpt8_pwm_evt", NULL,
636 "gpio_147", NULL, NULL, "safe_mode"),
637 _OMAP3_MUXENTRY(UART2_TX, 146,
638 "uart2_tx", "mcbsp3_clkx", "gpt11_pwm_evt", NULL,
639 "gpio_146", NULL, NULL, "safe_mode"),
640 _OMAP3_MUXENTRY(UART3_CTS_RCTX, 163,
641 "uart3_cts_rctx", NULL, NULL, NULL,
642 "gpio_163", NULL, NULL, "safe_mode"),
643 _OMAP3_MUXENTRY(UART3_RTS_SD, 164,
644 "uart3_rts_sd", NULL, NULL, NULL,
645 "gpio_164", NULL, NULL, "safe_mode"),
646 _OMAP3_MUXENTRY(UART3_RX_IRRX, 165,
647 "uart3_rx_irrx", NULL, NULL, NULL,
648 "gpio_165", NULL, NULL, "safe_mode"),
649 _OMAP3_MUXENTRY(UART3_TX_IRTX, 166,
650 "uart3_tx_irtx", NULL, NULL, NULL,
651 "gpio_166", NULL, NULL, "safe_mode"),
652
653 /* Only on 3630, see omap36xx_cbp_subset for the signals */
654 _OMAP3_MUXENTRY(GPMC_A11, 0,
655 NULL, NULL, NULL, NULL,
656 NULL, NULL, NULL, NULL),
657 _OMAP3_MUXENTRY(SAD2D_MBUSFLAG, 0,
658 NULL, NULL, NULL, NULL,
659 NULL, NULL, NULL, NULL),
660 _OMAP3_MUXENTRY(SAD2D_MREAD, 0,
661 NULL, NULL, NULL, NULL,
662 NULL, NULL, NULL, NULL),
663 _OMAP3_MUXENTRY(SAD2D_MWRITE, 0,
664 NULL, NULL, NULL, NULL,
665 NULL, NULL, NULL, NULL),
666 _OMAP3_MUXENTRY(SAD2D_SBUSFLAG, 0,
667 NULL, NULL, NULL, NULL,
668 NULL, NULL, NULL, NULL),
669 _OMAP3_MUXENTRY(SAD2D_SREAD, 0,
670 NULL, NULL, NULL, NULL,
671 NULL, NULL, NULL, NULL),
672 _OMAP3_MUXENTRY(SAD2D_SWRITE, 0,
673 NULL, NULL, NULL, NULL,
674 NULL, NULL, NULL, NULL),
675 _OMAP3_MUXENTRY(GPMC_A11, 0,
676 NULL, NULL, NULL, NULL,
677 NULL, NULL, NULL, NULL),
678 _OMAP3_MUXENTRY(SAD2D_MCAD28, 0,
679 NULL, NULL, NULL, NULL,
680 NULL, NULL, NULL, NULL),
681 _OMAP3_MUXENTRY(SAD2D_MCAD29, 0,
682 NULL, NULL, NULL, NULL,
683 NULL, NULL, NULL, NULL),
684 _OMAP3_MUXENTRY(SAD2D_MCAD32, 0,
685 NULL, NULL, NULL, NULL,
686 NULL, NULL, NULL, NULL),
687 _OMAP3_MUXENTRY(SAD2D_MCAD33, 0,
688 NULL, NULL, NULL, NULL,
689 NULL, NULL, NULL, NULL),
690 _OMAP3_MUXENTRY(SAD2D_MCAD34, 0,
691 NULL, NULL, NULL, NULL,
692 NULL, NULL, NULL, NULL),
693 _OMAP3_MUXENTRY(SAD2D_MCAD35, 0,
694 NULL, NULL, NULL, NULL,
695 NULL, NULL, NULL, NULL),
696 _OMAP3_MUXENTRY(SAD2D_MCAD36, 0,
697 NULL, NULL, NULL, NULL,
698 NULL, NULL, NULL, NULL),
699 { .reg_offset = OMAP_MUX_TERMINATOR },
700};
701
702/*
703 * Signals different on CBC package compared to the superset
704 */
705#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBC)
706static struct omap_mux __initdata omap3_cbc_subset[] = {
707 { .reg_offset = OMAP_MUX_TERMINATOR },
708};
709#else
710#define omap3_cbc_subset NULL
711#endif
712
713/*
714 * Balls for CBC package
715 * 515-pin s-PBGA Package, 0.65mm Ball Pitch (Top), 0.50mm Ball Pitch (Bottom)
716 *
717 * FIXME: What's up with the outdated TI documentation? See:
718 *
719 * http://wiki.davincidsp.com/index.php/Datasheet_Errata_for_OMAP35x_CBC_Package
720 * http://community.ti.com/forums/t/10982.aspx
721 */
722#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
723 && defined(CONFIG_OMAP_PACKAGE_CBC)
724static struct omap_ball __initdata omap3_cbc_ball[] = {
725 _OMAP3_BALLENTRY(CAM_D0, "ae16", NULL),
726 _OMAP3_BALLENTRY(CAM_D1, "ae15", NULL),
727 _OMAP3_BALLENTRY(CAM_D10, "d25", NULL),
728 _OMAP3_BALLENTRY(CAM_D11, "e26", NULL),
729 _OMAP3_BALLENTRY(CAM_D2, "a24", NULL),
730 _OMAP3_BALLENTRY(CAM_D3, "b24", NULL),
731 _OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
732 _OMAP3_BALLENTRY(CAM_D5, "c24", NULL),
733 _OMAP3_BALLENTRY(CAM_D6, "p25", NULL),
734 _OMAP3_BALLENTRY(CAM_D7, "p26", NULL),
735 _OMAP3_BALLENTRY(CAM_D8, "n25", NULL),
736 _OMAP3_BALLENTRY(CAM_D9, "n26", NULL),
737 _OMAP3_BALLENTRY(CAM_FLD, "b23", NULL),
738 _OMAP3_BALLENTRY(CAM_HS, "c23", NULL),
739 _OMAP3_BALLENTRY(CAM_PCLK, "c26", NULL),
740 _OMAP3_BALLENTRY(CAM_STROBE, "d26", NULL),
741 _OMAP3_BALLENTRY(CAM_VS, "d23", NULL),
742 _OMAP3_BALLENTRY(CAM_WEN, "a23", NULL),
743 _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
744 _OMAP3_BALLENTRY(CAM_XCLKB, "e25", NULL),
745 _OMAP3_BALLENTRY(CSI2_DX0, "ad17", NULL),
746 _OMAP3_BALLENTRY(CSI2_DX1, "ae18", NULL),
747 _OMAP3_BALLENTRY(CSI2_DY0, "ad16", NULL),
748 _OMAP3_BALLENTRY(CSI2_DY1, "ae17", NULL),
749 _OMAP3_BALLENTRY(DSS_ACBIAS, "f26", NULL),
750 _OMAP3_BALLENTRY(DSS_DATA0, "ae21", NULL),
751 _OMAP3_BALLENTRY(DSS_DATA1, "ae22", NULL),
752 _OMAP3_BALLENTRY(DSS_DATA10, "ac26", NULL),
753 _OMAP3_BALLENTRY(DSS_DATA11, "ad26", NULL),
754 _OMAP3_BALLENTRY(DSS_DATA12, "aa25", NULL),
755 _OMAP3_BALLENTRY(DSS_DATA13, "y25", NULL),
756 _OMAP3_BALLENTRY(DSS_DATA14, "aa26", NULL),
757 _OMAP3_BALLENTRY(DSS_DATA15, "ab26", NULL),
758 _OMAP3_BALLENTRY(DSS_DATA16, "l25", NULL),
759 _OMAP3_BALLENTRY(DSS_DATA17, "l26", NULL),
760 _OMAP3_BALLENTRY(DSS_DATA18, "m24", NULL),
761 _OMAP3_BALLENTRY(DSS_DATA19, "m26", NULL),
762 _OMAP3_BALLENTRY(DSS_DATA2, "ae23", NULL),
763 _OMAP3_BALLENTRY(DSS_DATA20, "f25", NULL),
764 _OMAP3_BALLENTRY(DSS_DATA21, "n24", NULL),
765 _OMAP3_BALLENTRY(DSS_DATA22, "ac25", NULL),
766 _OMAP3_BALLENTRY(DSS_DATA23, "ab25", NULL),
767 _OMAP3_BALLENTRY(DSS_DATA3, "ae24", NULL),
768 _OMAP3_BALLENTRY(DSS_DATA4, "ad23", NULL),
769 _OMAP3_BALLENTRY(DSS_DATA5, "ad24", NULL),
770 _OMAP3_BALLENTRY(DSS_DATA6, "g26", NULL),
771 _OMAP3_BALLENTRY(DSS_DATA7, "h25", NULL),
772 _OMAP3_BALLENTRY(DSS_DATA8, "h26", NULL),
773 _OMAP3_BALLENTRY(DSS_DATA9, "j26", NULL),
774 _OMAP3_BALLENTRY(DSS_HSYNC, "k24", NULL),
775 _OMAP3_BALLENTRY(DSS_PCLK, "g25", NULL),
776 _OMAP3_BALLENTRY(DSS_VSYNC, "m25", NULL),
777 _OMAP3_BALLENTRY(ETK_CLK, "ab2", NULL),
778 _OMAP3_BALLENTRY(ETK_CTL, "ab3", NULL),
779 _OMAP3_BALLENTRY(ETK_D0, "ac3", NULL),
780 _OMAP3_BALLENTRY(ETK_D1, "ad4", NULL),
781 _OMAP3_BALLENTRY(ETK_D10, "ae4", NULL),
782 _OMAP3_BALLENTRY(ETK_D11, "af6", NULL),
783 _OMAP3_BALLENTRY(ETK_D12, "ae6", NULL),
784 _OMAP3_BALLENTRY(ETK_D13, "af7", NULL),
785 _OMAP3_BALLENTRY(ETK_D14, "af9", NULL),
786 _OMAP3_BALLENTRY(ETK_D15, "ae9", NULL),
787 _OMAP3_BALLENTRY(ETK_D2, "ad3", NULL),
788 _OMAP3_BALLENTRY(ETK_D3, "aa3", NULL),
789 _OMAP3_BALLENTRY(ETK_D4, "y3", NULL),
790 _OMAP3_BALLENTRY(ETK_D5, "ab1", NULL),
791 _OMAP3_BALLENTRY(ETK_D6, "ae3", NULL),
792 _OMAP3_BALLENTRY(ETK_D7, "ad2", NULL),
793 _OMAP3_BALLENTRY(ETK_D8, "aa4", NULL),
794 _OMAP3_BALLENTRY(ETK_D9, "v2", NULL),
795 _OMAP3_BALLENTRY(GPMC_A1, "j2", NULL),
796 _OMAP3_BALLENTRY(GPMC_A10, "d2", NULL),
797 _OMAP3_BALLENTRY(GPMC_A2, "h1", NULL),
798 _OMAP3_BALLENTRY(GPMC_A3, "h2", NULL),
799 _OMAP3_BALLENTRY(GPMC_A4, "g2", NULL),
800 _OMAP3_BALLENTRY(GPMC_A5, "f1", NULL),
801 _OMAP3_BALLENTRY(GPMC_A6, "f2", NULL),
802 _OMAP3_BALLENTRY(GPMC_A7, "e1", NULL),
803 _OMAP3_BALLENTRY(GPMC_A8, "e2", NULL),
804 _OMAP3_BALLENTRY(GPMC_A9, "d1", NULL),
805 _OMAP3_BALLENTRY(GPMC_CLK, "n1", "l1"),
806 _OMAP3_BALLENTRY(GPMC_D10, "t1", "n1"),
807 _OMAP3_BALLENTRY(GPMC_D11, "u2", "p2"),
808 _OMAP3_BALLENTRY(GPMC_D12, "u1", "p1"),
809 _OMAP3_BALLENTRY(GPMC_D13, "p1", "m1"),
810 _OMAP3_BALLENTRY(GPMC_D14, "l2", "j2"),
811 _OMAP3_BALLENTRY(GPMC_D15, "m2", "k2"),
812 _OMAP3_BALLENTRY(GPMC_D8, "v1", "r1"),
813 _OMAP3_BALLENTRY(GPMC_D9, "y1", "t1"),
814 _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k2", NULL),
815 _OMAP3_BALLENTRY(GPMC_NBE1, "j1", NULL),
816 _OMAP3_BALLENTRY(GPMC_NCS1, "ad1", "w1"),
817 _OMAP3_BALLENTRY(GPMC_NCS2, "a3", NULL),
818 _OMAP3_BALLENTRY(GPMC_NCS3, "b6", NULL),
819 _OMAP3_BALLENTRY(GPMC_NCS4, "b4", NULL),
820 _OMAP3_BALLENTRY(GPMC_NCS5, "c4", NULL),
821 _OMAP3_BALLENTRY(GPMC_NCS6, "b5", NULL),
822 _OMAP3_BALLENTRY(GPMC_NCS7, "c5", NULL),
823 _OMAP3_BALLENTRY(GPMC_NWP, "ac6", "y5"),
824 _OMAP3_BALLENTRY(GPMC_WAIT1, "ac8", "y8"),
825 _OMAP3_BALLENTRY(GPMC_WAIT2, "b3", NULL),
826 _OMAP3_BALLENTRY(GPMC_WAIT3, "c6", NULL),
827 _OMAP3_BALLENTRY(HDQ_SIO, "j23", NULL),
828 _OMAP3_BALLENTRY(HSUSB0_CLK, "w19", NULL),
829 _OMAP3_BALLENTRY(HSUSB0_DATA0, "v20", NULL),
830 _OMAP3_BALLENTRY(HSUSB0_DATA1, "y20", NULL),
831 _OMAP3_BALLENTRY(HSUSB0_DATA2, "v18", NULL),
832 _OMAP3_BALLENTRY(HSUSB0_DATA3, "w20", NULL),
833 _OMAP3_BALLENTRY(HSUSB0_DATA4, "w17", NULL),
834 _OMAP3_BALLENTRY(HSUSB0_DATA5, "y18", NULL),
835 _OMAP3_BALLENTRY(HSUSB0_DATA6, "y19", NULL),
836 _OMAP3_BALLENTRY(HSUSB0_DATA7, "y17", NULL),
837 _OMAP3_BALLENTRY(HSUSB0_DIR, "v19", NULL),
838 _OMAP3_BALLENTRY(HSUSB0_NXT, "w18", NULL),
839 _OMAP3_BALLENTRY(HSUSB0_STP, "u20", NULL),
840 _OMAP3_BALLENTRY(I2C2_SCL, "c2", NULL),
841 _OMAP3_BALLENTRY(I2C2_SDA, "c1", NULL),
842 _OMAP3_BALLENTRY(I2C3_SCL, "ab4", NULL),
843 _OMAP3_BALLENTRY(I2C3_SDA, "ac4", NULL),
844 _OMAP3_BALLENTRY(I2C4_SCL, "ad15", NULL),
845 _OMAP3_BALLENTRY(I2C4_SDA, "w16", NULL),
846 _OMAP3_BALLENTRY(JTAG_EMU0, "y15", NULL),
847 _OMAP3_BALLENTRY(JTAG_EMU1, "y14", NULL),
848 _OMAP3_BALLENTRY(MCBSP1_CLKR, "u19", NULL),
849 _OMAP3_BALLENTRY(MCBSP1_CLKX, "t17", NULL),
850 _OMAP3_BALLENTRY(MCBSP1_DR, "t20", NULL),
851 _OMAP3_BALLENTRY(MCBSP1_DX, "u17", NULL),
852 _OMAP3_BALLENTRY(MCBSP1_FSR, "v17", NULL),
853 _OMAP3_BALLENTRY(MCBSP1_FSX, "p20", NULL),
854 _OMAP3_BALLENTRY(MCBSP2_CLKX, "r18", NULL),
855 _OMAP3_BALLENTRY(MCBSP2_DR, "t18", NULL),
856 _OMAP3_BALLENTRY(MCBSP2_DX, "r19", NULL),
857 _OMAP3_BALLENTRY(MCBSP2_FSX, "u18", NULL),
858 _OMAP3_BALLENTRY(MCBSP3_CLKX, "u3", NULL),
859 _OMAP3_BALLENTRY(MCBSP3_DR, "n3", NULL),
860 _OMAP3_BALLENTRY(MCBSP3_DX, "p3", NULL),
861 _OMAP3_BALLENTRY(MCBSP3_FSX, "w3", NULL),
862 _OMAP3_BALLENTRY(MCBSP4_CLKX, "v3", NULL),
863 _OMAP3_BALLENTRY(MCBSP4_DR, "u4", NULL),
864 _OMAP3_BALLENTRY(MCBSP4_DX, "r3", NULL),
865 _OMAP3_BALLENTRY(MCBSP4_FSX, "t3", NULL),
866 _OMAP3_BALLENTRY(MCBSP_CLKS, "t19", NULL),
867 _OMAP3_BALLENTRY(MCSPI1_CLK, "p9", NULL),
868 _OMAP3_BALLENTRY(MCSPI1_CS0, "r7", NULL),
869 _OMAP3_BALLENTRY(MCSPI1_CS1, "r8", NULL),
870 _OMAP3_BALLENTRY(MCSPI1_CS2, "r9", NULL),
871 _OMAP3_BALLENTRY(MCSPI1_CS3, "t8", NULL),
872 _OMAP3_BALLENTRY(MCSPI1_SIMO, "p8", NULL),
873 _OMAP3_BALLENTRY(MCSPI1_SOMI, "p7", NULL),
874 _OMAP3_BALLENTRY(MCSPI2_CLK, "w7", NULL),
875 _OMAP3_BALLENTRY(MCSPI2_CS0, "v8", NULL),
876 _OMAP3_BALLENTRY(MCSPI2_CS1, "v9", NULL),
877 _OMAP3_BALLENTRY(MCSPI2_SIMO, "w8", NULL),
878 _OMAP3_BALLENTRY(MCSPI2_SOMI, "u8", NULL),
879 _OMAP3_BALLENTRY(SDMMC1_CLK, "n19", NULL),
880 _OMAP3_BALLENTRY(SDMMC1_CMD, "l18", NULL),
881 _OMAP3_BALLENTRY(SDMMC1_DAT0, "m19", NULL),
882 _OMAP3_BALLENTRY(SDMMC1_DAT1, "m18", NULL),
883 _OMAP3_BALLENTRY(SDMMC1_DAT2, "k18", NULL),
884 _OMAP3_BALLENTRY(SDMMC1_DAT3, "n20", NULL),
885 _OMAP3_BALLENTRY(SDMMC1_DAT4, "m20", NULL),
886 _OMAP3_BALLENTRY(SDMMC1_DAT5, "p17", NULL),
887 _OMAP3_BALLENTRY(SDMMC1_DAT6, "p18", NULL),
888 _OMAP3_BALLENTRY(SDMMC1_DAT7, "p19", NULL),
889 _OMAP3_BALLENTRY(SDMMC2_CLK, "w10", NULL),
890 _OMAP3_BALLENTRY(SDMMC2_CMD, "r10", NULL),
891 _OMAP3_BALLENTRY(SDMMC2_DAT0, "t10", NULL),
892 _OMAP3_BALLENTRY(SDMMC2_DAT1, "t9", NULL),
893 _OMAP3_BALLENTRY(SDMMC2_DAT2, "u10", NULL),
894 _OMAP3_BALLENTRY(SDMMC2_DAT3, "u9", NULL),
895 _OMAP3_BALLENTRY(SDMMC2_DAT4, "v10", NULL),
896 _OMAP3_BALLENTRY(SDMMC2_DAT5, "m3", NULL),
897 _OMAP3_BALLENTRY(SDMMC2_DAT6, "l3", NULL),
898 _OMAP3_BALLENTRY(SDMMC2_DAT7, "k3", NULL),
899 _OMAP3_BALLENTRY(SYS_BOOT0, "f3", NULL),
900 _OMAP3_BALLENTRY(SYS_BOOT1, "d3", NULL),
901 _OMAP3_BALLENTRY(SYS_BOOT2, "c3", NULL),
902 _OMAP3_BALLENTRY(SYS_BOOT3, "e3", NULL),
903 _OMAP3_BALLENTRY(SYS_BOOT4, "e4", NULL),
904 _OMAP3_BALLENTRY(SYS_BOOT5, "g3", NULL),
905 _OMAP3_BALLENTRY(SYS_BOOT6, "d4", NULL),
906 _OMAP3_BALLENTRY(SYS_CLKOUT1, "ae14", NULL),
907 _OMAP3_BALLENTRY(SYS_CLKOUT2, "w11", NULL),
908 _OMAP3_BALLENTRY(SYS_CLKREQ, "w15", NULL),
909 _OMAP3_BALLENTRY(SYS_NIRQ, "v16", NULL),
910 _OMAP3_BALLENTRY(SYS_NRESWARM, "ad7", "aa5"),
911 _OMAP3_BALLENTRY(SYS_OFF_MODE, "v12", NULL),
912 _OMAP3_BALLENTRY(UART1_CTS, "w2", NULL),
913 _OMAP3_BALLENTRY(UART1_RTS, "r2", NULL),
914 _OMAP3_BALLENTRY(UART1_RX, "h3", NULL),
915 _OMAP3_BALLENTRY(UART1_TX, "l4", NULL),
916 _OMAP3_BALLENTRY(UART2_CTS, "y24", NULL),
917 _OMAP3_BALLENTRY(UART2_RTS, "aa24", NULL),
918 _OMAP3_BALLENTRY(UART2_RX, "ad21", NULL),
919 _OMAP3_BALLENTRY(UART2_TX, "ad22", NULL),
920 _OMAP3_BALLENTRY(UART3_CTS_RCTX, "f23", NULL),
921 _OMAP3_BALLENTRY(UART3_RTS_SD, "f24", NULL),
922 _OMAP3_BALLENTRY(UART3_RX_IRRX, "h24", NULL),
923 _OMAP3_BALLENTRY(UART3_TX_IRTX, "g24", NULL),
924 { .reg_offset = OMAP_MUX_TERMINATOR },
925};
926#else
927#define omap3_cbc_ball NULL
928#endif
929
930/*
931 * Signals different on CUS package compared to superset
932 */
933#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CUS)
934static struct omap_mux __initdata omap3_cus_subset[] = {
935 _OMAP3_MUXENTRY(CAM_D10, 109,
936 "cam_d10", NULL, NULL, NULL,
937 "gpio_109", NULL, NULL, "safe_mode"),
938 _OMAP3_MUXENTRY(CAM_D11, 110,
939 "cam_d11", NULL, NULL, NULL,
940 "gpio_110", NULL, NULL, "safe_mode"),
941 _OMAP3_MUXENTRY(CAM_D2, 101,
942 "cam_d2", NULL, NULL, NULL,
943 "gpio_101", NULL, NULL, "safe_mode"),
944 _OMAP3_MUXENTRY(CAM_D3, 102,
945 "cam_d3", NULL, NULL, NULL,
946 "gpio_102", NULL, NULL, "safe_mode"),
947 _OMAP3_MUXENTRY(CAM_D4, 103,
948 "cam_d4", NULL, NULL, NULL,
949 "gpio_103", NULL, NULL, "safe_mode"),
950 _OMAP3_MUXENTRY(CAM_D5, 104,
951 "cam_d5", NULL, NULL, NULL,
952 "gpio_104", NULL, NULL, "safe_mode"),
953 _OMAP3_MUXENTRY(CAM_FLD, 98,
954 "cam_fld", NULL, "cam_global_reset", NULL,
955 "gpio_98", NULL, NULL, "safe_mode"),
956 _OMAP3_MUXENTRY(CAM_HS, 94,
957 "cam_hs", NULL, NULL, NULL,
958 "gpio_94", NULL, NULL, "safe_mode"),
959 _OMAP3_MUXENTRY(CAM_PCLK, 97,
960 "cam_pclk", NULL, NULL, NULL,
961 "gpio_97", NULL, NULL, "safe_mode"),
962 _OMAP3_MUXENTRY(CAM_STROBE, 126,
963 "cam_strobe", NULL, NULL, NULL,
964 "gpio_126", NULL, NULL, "safe_mode"),
965 _OMAP3_MUXENTRY(CAM_VS, 95,
966 "cam_vs", NULL, NULL, NULL,
967 "gpio_95", NULL, NULL, "safe_mode"),
968 _OMAP3_MUXENTRY(CAM_WEN, 167,
969 "cam_wen", NULL, "cam_shutter", NULL,
970 "gpio_167", NULL, NULL, "safe_mode"),
971 _OMAP3_MUXENTRY(DSS_DATA6, 76,
972 "dss_data6", NULL, "uart1_tx", NULL,
973 "gpio_76", NULL, NULL, "safe_mode"),
974 _OMAP3_MUXENTRY(DSS_DATA7, 77,
975 "dss_data7", NULL, "uart1_rx", NULL,
976 "gpio_77", NULL, NULL, "safe_mode"),
977 _OMAP3_MUXENTRY(DSS_DATA8, 78,
978 "dss_data8", NULL, NULL, NULL,
979 "gpio_78", NULL, NULL, "safe_mode"),
980 _OMAP3_MUXENTRY(DSS_DATA9, 79,
981 "dss_data9", NULL, NULL, NULL,
982 "gpio_79", NULL, NULL, "safe_mode"),
983 _OMAP3_MUXENTRY(DSS_HSYNC, 67,
984 "dss_hsync", NULL, NULL, NULL,
985 "gpio_67", NULL, NULL, "safe_mode"),
986 _OMAP3_MUXENTRY(DSS_PCLK, 66,
987 "dss_pclk", NULL, NULL, NULL,
988 "gpio_66", NULL, NULL, "safe_mode"),
989 _OMAP3_MUXENTRY(ETK_CLK, 12,
990 "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
991 "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL),
992 _OMAP3_MUXENTRY(ETK_CTL, 13,
993 "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
994 "gpio_13", NULL, "hsusb1_tll_clk", NULL),
995 _OMAP3_MUXENTRY(ETK_D0, 14,
996 "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
997 "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL),
998 _OMAP3_MUXENTRY(ETK_D1, 15,
999 "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
1000 "gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL),
1001 _OMAP3_MUXENTRY(ETK_D10, 24,
1002 "etk_d10", NULL, "uart1_rx", "hsusb2_clk",
1003 "gpio_24", NULL, "hsusb2_tll_clk", NULL),
1004 _OMAP3_MUXENTRY(ETK_D11, 25,
1005 "etk_d11", NULL, NULL, "hsusb2_stp",
1006 "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL),
1007 _OMAP3_MUXENTRY(ETK_D12, 26,
1008 "etk_d12", NULL, NULL, "hsusb2_dir",
1009 "gpio_26", NULL, "hsusb2_tll_dir", NULL),
1010 _OMAP3_MUXENTRY(ETK_D13, 27,
1011 "etk_d13", NULL, NULL, "hsusb2_nxt",
1012 "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL),
1013 _OMAP3_MUXENTRY(ETK_D14, 28,
1014 "etk_d14", NULL, NULL, "hsusb2_data0",
1015 "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL),
1016 _OMAP3_MUXENTRY(ETK_D15, 29,
1017 "etk_d15", NULL, NULL, "hsusb2_data1",
1018 "gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL),
1019 _OMAP3_MUXENTRY(ETK_D2, 16,
1020 "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
1021 "gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL),
1022 _OMAP3_MUXENTRY(ETK_D3, 17,
1023 "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
1024 "gpio_17", NULL, "hsusb1_tll_data7", NULL),
1025 _OMAP3_MUXENTRY(ETK_D4, 18,
1026 "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
1027 "gpio_18", NULL, "hsusb1_tll_data4", NULL),
1028 _OMAP3_MUXENTRY(ETK_D5, 19,
1029 "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
1030 "gpio_19", NULL, "hsusb1_tll_data5", NULL),
1031 _OMAP3_MUXENTRY(ETK_D6, 20,
1032 "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
1033 "gpio_20", NULL, "hsusb1_tll_data6", NULL),
1034 _OMAP3_MUXENTRY(ETK_D7, 21,
1035 "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
1036 "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL),
1037 _OMAP3_MUXENTRY(ETK_D8, 22,
1038 "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
1039 "gpio_22", NULL, "hsusb1_tll_dir", NULL),
1040 _OMAP3_MUXENTRY(ETK_D9, 23,
1041 "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
1042 "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL),
1043 _OMAP3_MUXENTRY(MCBSP3_CLKX, 142,
1044 "mcbsp3_clkx", "uart2_tx", NULL, NULL,
1045 "gpio_142", NULL, NULL, "safe_mode"),
1046 _OMAP3_MUXENTRY(MCBSP3_DR, 141,
1047 "mcbsp3_dr", "uart2_rts", NULL, NULL,
1048 "gpio_141", NULL, NULL, "safe_mode"),
1049 _OMAP3_MUXENTRY(MCBSP3_DX, 140,
1050 "mcbsp3_dx", "uart2_cts", NULL, NULL,
1051 "gpio_140", NULL, NULL, "safe_mode"),
1052 _OMAP3_MUXENTRY(MCBSP3_FSX, 143,
1053 "mcbsp3_fsx", "uart2_rx", NULL, NULL,
1054 "gpio_143", NULL, NULL, "safe_mode"),
1055 _OMAP3_MUXENTRY(SDMMC2_DAT5, 137,
1056 "sdmmc2_dat5", "sdmmc2_dir_dat1",
1057 "cam_global_reset", "sdmmc3_dat1",
1058 "gpio_137", NULL, NULL, "safe_mode"),
1059 _OMAP3_MUXENTRY(SDMMC2_DAT6, 138,
1060 "sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2",
1061 "gpio_138", NULL, NULL, "safe_mode"),
1062 _OMAP3_MUXENTRY(SDMMC2_DAT7, 139,
1063 "sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3",
1064 "gpio_139", NULL, NULL, "safe_mode"),
1065 _OMAP3_MUXENTRY(UART1_CTS, 150,
1066 "uart1_cts", NULL, NULL, NULL,
1067 "gpio_150", NULL, NULL, "safe_mode"),
1068 { .reg_offset = OMAP_MUX_TERMINATOR },
1069};
1070#else
1071#define omap3_cus_subset NULL
1072#endif
1073
1074/*
1075 * Balls for CUS package
1076 * 423-pin s-PBGA Package, 0.65mm Ball Pitch (Bottom)
1077 */
1078#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
1079 && defined(CONFIG_OMAP_PACKAGE_CUS)
1080static struct omap_ball __initdata omap3_cus_ball[] = {
1081 _OMAP3_BALLENTRY(CAM_D0, "ab18", NULL),
1082 _OMAP3_BALLENTRY(CAM_D1, "ac18", NULL),
1083 _OMAP3_BALLENTRY(CAM_D10, "f21", NULL),
1084 _OMAP3_BALLENTRY(CAM_D11, "g21", NULL),
1085 _OMAP3_BALLENTRY(CAM_D2, "g19", NULL),
1086 _OMAP3_BALLENTRY(CAM_D3, "f19", NULL),
1087 _OMAP3_BALLENTRY(CAM_D4, "g20", NULL),
1088 _OMAP3_BALLENTRY(CAM_D5, "b21", NULL),
1089 _OMAP3_BALLENTRY(CAM_D6, "l24", NULL),
1090 _OMAP3_BALLENTRY(CAM_D7, "k24", NULL),
1091 _OMAP3_BALLENTRY(CAM_D8, "j23", NULL),
1092 _OMAP3_BALLENTRY(CAM_D9, "k23", NULL),
1093 _OMAP3_BALLENTRY(CAM_FLD, "h24", NULL),
1094 _OMAP3_BALLENTRY(CAM_HS, "a22", NULL),
1095 _OMAP3_BALLENTRY(CAM_PCLK, "j19", NULL),
1096 _OMAP3_BALLENTRY(CAM_STROBE, "j20", NULL),
1097 _OMAP3_BALLENTRY(CAM_VS, "e18", NULL),
1098 _OMAP3_BALLENTRY(CAM_WEN, "f18", NULL),
1099 _OMAP3_BALLENTRY(CAM_XCLKA, "b22", NULL),
1100 _OMAP3_BALLENTRY(CAM_XCLKB, "c22", NULL),
1101 _OMAP3_BALLENTRY(DSS_ACBIAS, "j21", NULL),
1102 _OMAP3_BALLENTRY(DSS_DATA0, "ac19", NULL),
1103 _OMAP3_BALLENTRY(DSS_DATA1, "ab19", NULL),
1104 _OMAP3_BALLENTRY(DSS_DATA10, "ac22", NULL),
1105 _OMAP3_BALLENTRY(DSS_DATA11, "ac23", NULL),
1106 _OMAP3_BALLENTRY(DSS_DATA12, "ab22", NULL),
1107 _OMAP3_BALLENTRY(DSS_DATA13, "y22", NULL),
1108 _OMAP3_BALLENTRY(DSS_DATA14, "w22", NULL),
1109 _OMAP3_BALLENTRY(DSS_DATA15, "v22", NULL),
1110 _OMAP3_BALLENTRY(DSS_DATA16, "j22", NULL),
1111 _OMAP3_BALLENTRY(DSS_DATA17, "g23", NULL),
1112 _OMAP3_BALLENTRY(DSS_DATA18, "g24", NULL),
1113 _OMAP3_BALLENTRY(DSS_DATA19, "h23", NULL),
1114 _OMAP3_BALLENTRY(DSS_DATA2, "ad20", NULL),
1115 _OMAP3_BALLENTRY(DSS_DATA20, "d23", NULL),
1116 _OMAP3_BALLENTRY(DSS_DATA21, "k22", NULL),
1117 _OMAP3_BALLENTRY(DSS_DATA22, "v21", NULL),
1118 _OMAP3_BALLENTRY(DSS_DATA23, "w21", NULL),
1119 _OMAP3_BALLENTRY(DSS_DATA3, "ac20", NULL),
1120 _OMAP3_BALLENTRY(DSS_DATA4, "ad21", NULL),
1121 _OMAP3_BALLENTRY(DSS_DATA5, "ac21", NULL),
1122 _OMAP3_BALLENTRY(DSS_DATA6, "d24", NULL),
1123 _OMAP3_BALLENTRY(DSS_DATA7, "e23", NULL),
1124 _OMAP3_BALLENTRY(DSS_DATA8, "e24", NULL),
1125 _OMAP3_BALLENTRY(DSS_DATA9, "f23", NULL),
1126 _OMAP3_BALLENTRY(DSS_HSYNC, "e22", NULL),
1127 _OMAP3_BALLENTRY(DSS_PCLK, "g22", NULL),
1128 _OMAP3_BALLENTRY(DSS_VSYNC, "f22", NULL),
1129 _OMAP3_BALLENTRY(ETK_CLK, "ac1", NULL),
1130 _OMAP3_BALLENTRY(ETK_CTL, "ad3", NULL),
1131 _OMAP3_BALLENTRY(ETK_D0, "ad6", NULL),
1132 _OMAP3_BALLENTRY(ETK_D1, "ac6", NULL),
1133 _OMAP3_BALLENTRY(ETK_D10, "ac3", NULL),
1134 _OMAP3_BALLENTRY(ETK_D11, "ac9", NULL),
1135 _OMAP3_BALLENTRY(ETK_D12, "ac10", NULL),
1136 _OMAP3_BALLENTRY(ETK_D13, "ad11", NULL),
1137 _OMAP3_BALLENTRY(ETK_D14, "ac11", NULL),
1138 _OMAP3_BALLENTRY(ETK_D15, "ad12", NULL),
1139 _OMAP3_BALLENTRY(ETK_D2, "ac7", NULL),
1140 _OMAP3_BALLENTRY(ETK_D3, "ad8", NULL),
1141 _OMAP3_BALLENTRY(ETK_D4, "ac5", NULL),
1142 _OMAP3_BALLENTRY(ETK_D5, "ad2", NULL),
1143 _OMAP3_BALLENTRY(ETK_D6, "ac8", NULL),
1144 _OMAP3_BALLENTRY(ETK_D7, "ad9", NULL),
1145 _OMAP3_BALLENTRY(ETK_D8, "ac4", NULL),
1146 _OMAP3_BALLENTRY(ETK_D9, "ad5", NULL),
1147 _OMAP3_BALLENTRY(GPMC_A1, "k4", NULL),
1148 _OMAP3_BALLENTRY(GPMC_A10, "g2", NULL),
1149 _OMAP3_BALLENTRY(GPMC_A2, "k3", NULL),
1150 _OMAP3_BALLENTRY(GPMC_A3, "k2", NULL),
1151 _OMAP3_BALLENTRY(GPMC_A4, "j4", NULL),
1152 _OMAP3_BALLENTRY(GPMC_A5, "j3", NULL),
1153 _OMAP3_BALLENTRY(GPMC_A6, "j2", NULL),
1154 _OMAP3_BALLENTRY(GPMC_A7, "j1", NULL),
1155 _OMAP3_BALLENTRY(GPMC_A8, "h1", NULL),
1156 _OMAP3_BALLENTRY(GPMC_A9, "h2", NULL),
1157 _OMAP3_BALLENTRY(GPMC_CLK, "w2", NULL),
1158 _OMAP3_BALLENTRY(GPMC_D10, "u1", NULL),
1159 _OMAP3_BALLENTRY(GPMC_D11, "r3", NULL),
1160 _OMAP3_BALLENTRY(GPMC_D12, "t3", NULL),
1161 _OMAP3_BALLENTRY(GPMC_D13, "u2", NULL),
1162 _OMAP3_BALLENTRY(GPMC_D14, "v1", NULL),
1163 _OMAP3_BALLENTRY(GPMC_D15, "v2", NULL),
1164 _OMAP3_BALLENTRY(GPMC_D8, "r2", NULL),
1165 _OMAP3_BALLENTRY(GPMC_D9, "t2", NULL),
1166 _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k5", NULL),
1167 _OMAP3_BALLENTRY(GPMC_NBE1, "l1", NULL),
1168 _OMAP3_BALLENTRY(GPMC_NCS3, "d2", NULL),
1169 _OMAP3_BALLENTRY(GPMC_NCS4, "f4", NULL),
1170 _OMAP3_BALLENTRY(GPMC_NCS5, "g5", NULL),
1171 _OMAP3_BALLENTRY(GPMC_NCS6, "f3", NULL),
1172 _OMAP3_BALLENTRY(GPMC_NCS7, "g4", NULL),
1173 _OMAP3_BALLENTRY(GPMC_NWP, "e1", NULL),
1174 _OMAP3_BALLENTRY(GPMC_WAIT3, "c2", NULL),
1175 _OMAP3_BALLENTRY(HDQ_SIO, "a24", NULL),
1176 _OMAP3_BALLENTRY(HSUSB0_CLK, "r21", NULL),
1177 _OMAP3_BALLENTRY(HSUSB0_DATA0, "t24", NULL),
1178 _OMAP3_BALLENTRY(HSUSB0_DATA1, "t23", NULL),
1179 _OMAP3_BALLENTRY(HSUSB0_DATA2, "u24", NULL),
1180 _OMAP3_BALLENTRY(HSUSB0_DATA3, "u23", NULL),
1181 _OMAP3_BALLENTRY(HSUSB0_DATA4, "w24", NULL),
1182 _OMAP3_BALLENTRY(HSUSB0_DATA5, "v23", NULL),
1183 _OMAP3_BALLENTRY(HSUSB0_DATA6, "w23", NULL),
1184 _OMAP3_BALLENTRY(HSUSB0_DATA7, "t22", NULL),
1185 _OMAP3_BALLENTRY(HSUSB0_DIR, "p23", NULL),
1186 _OMAP3_BALLENTRY(HSUSB0_NXT, "r22", NULL),
1187 _OMAP3_BALLENTRY(HSUSB0_STP, "r23", NULL),
1188 _OMAP3_BALLENTRY(I2C2_SCL, "ac15", NULL),
1189 _OMAP3_BALLENTRY(I2C2_SDA, "ac14", NULL),
1190 _OMAP3_BALLENTRY(I2C3_SCL, "ac13", NULL),
1191 _OMAP3_BALLENTRY(I2C3_SDA, "ac12", NULL),
1192 _OMAP3_BALLENTRY(I2C4_SCL, "y16", NULL),
1193 _OMAP3_BALLENTRY(I2C4_SDA, "y15", NULL),
1194 _OMAP3_BALLENTRY(JTAG_EMU0, "ac24", NULL),
1195 _OMAP3_BALLENTRY(JTAG_EMU1, "ad24", NULL),
1196 _OMAP3_BALLENTRY(MCBSP1_CLKR, "w19", NULL),
1197 _OMAP3_BALLENTRY(MCBSP1_CLKX, "v18", NULL),
1198 _OMAP3_BALLENTRY(MCBSP1_DR, "y18", NULL),
1199 _OMAP3_BALLENTRY(MCBSP1_DX, "w18", NULL),
1200 _OMAP3_BALLENTRY(MCBSP1_FSR, "ab20", NULL),
1201 _OMAP3_BALLENTRY(MCBSP1_FSX, "aa19", NULL),
1202 _OMAP3_BALLENTRY(MCBSP2_CLKX, "t21", NULL),
1203 _OMAP3_BALLENTRY(MCBSP2_DR, "v19", NULL),
1204 _OMAP3_BALLENTRY(MCBSP2_DX, "r20", NULL),
1205 _OMAP3_BALLENTRY(MCBSP2_FSX, "v20", NULL),
1206 _OMAP3_BALLENTRY(MCBSP3_CLKX, "w4", NULL),
1207 _OMAP3_BALLENTRY(MCBSP3_DR, "v5", NULL),
1208 _OMAP3_BALLENTRY(MCBSP3_DX, "v6", NULL),
1209 _OMAP3_BALLENTRY(MCBSP3_FSX, "v4", NULL),
1210 _OMAP3_BALLENTRY(MCBSP_CLKS, "aa18", NULL),
1211 _OMAP3_BALLENTRY(MCSPI1_CLK, "t5", NULL),
1212 _OMAP3_BALLENTRY(MCSPI1_CS0, "t6", NULL),
1213 _OMAP3_BALLENTRY(MCSPI1_CS3, "r5", NULL),
1214 _OMAP3_BALLENTRY(MCSPI1_SIMO, "r4", NULL),
1215 _OMAP3_BALLENTRY(MCSPI1_SOMI, "t4", NULL),
1216 _OMAP3_BALLENTRY(MCSPI2_CLK, "n5", NULL),
1217 _OMAP3_BALLENTRY(MCSPI2_CS0, "m5", NULL),
1218 _OMAP3_BALLENTRY(MCSPI2_CS1, "m4", NULL),
1219 _OMAP3_BALLENTRY(MCSPI2_SIMO, "n4", NULL),
1220 _OMAP3_BALLENTRY(MCSPI2_SOMI, "n3", NULL),
1221 _OMAP3_BALLENTRY(SDMMC1_CLK, "m23", NULL),
1222 _OMAP3_BALLENTRY(SDMMC1_CMD, "l23", NULL),
1223 _OMAP3_BALLENTRY(SDMMC1_DAT0, "m22", NULL),
1224 _OMAP3_BALLENTRY(SDMMC1_DAT1, "m21", NULL),
1225 _OMAP3_BALLENTRY(SDMMC1_DAT2, "m20", NULL),
1226 _OMAP3_BALLENTRY(SDMMC1_DAT3, "n23", NULL),
1227 _OMAP3_BALLENTRY(SDMMC1_DAT4, "n22", NULL),
1228 _OMAP3_BALLENTRY(SDMMC1_DAT5, "n21", NULL),
1229 _OMAP3_BALLENTRY(SDMMC1_DAT6, "n20", NULL),
1230 _OMAP3_BALLENTRY(SDMMC1_DAT7, "p24", NULL),
1231 _OMAP3_BALLENTRY(SDMMC2_CLK, "y1", NULL),
1232 _OMAP3_BALLENTRY(SDMMC2_CMD, "ab5", NULL),
1233 _OMAP3_BALLENTRY(SDMMC2_DAT0, "ab3", NULL),
1234 _OMAP3_BALLENTRY(SDMMC2_DAT1, "y3", NULL),
1235 _OMAP3_BALLENTRY(SDMMC2_DAT2, "w3", NULL),
1236 _OMAP3_BALLENTRY(SDMMC2_DAT3, "v3", NULL),
1237 _OMAP3_BALLENTRY(SDMMC2_DAT4, "ab2", NULL),
1238 _OMAP3_BALLENTRY(SDMMC2_DAT5, "aa2", NULL),
1239 _OMAP3_BALLENTRY(SDMMC2_DAT6, "y2", NULL),
1240 _OMAP3_BALLENTRY(SDMMC2_DAT7, "aa1", NULL),
1241 _OMAP3_BALLENTRY(SYS_BOOT0, "ab12", NULL),
1242 _OMAP3_BALLENTRY(SYS_BOOT1, "ac16", NULL),
1243 _OMAP3_BALLENTRY(SYS_BOOT2, "ad17", NULL),
1244 _OMAP3_BALLENTRY(SYS_BOOT3, "ad18", NULL),
1245 _OMAP3_BALLENTRY(SYS_BOOT4, "ac17", NULL),
1246 _OMAP3_BALLENTRY(SYS_BOOT5, "ab16", NULL),
1247 _OMAP3_BALLENTRY(SYS_BOOT6, "aa15", NULL),
1248 _OMAP3_BALLENTRY(SYS_CLKOUT1, "y7", NULL),
1249 _OMAP3_BALLENTRY(SYS_CLKOUT2, "aa6", NULL),
1250 _OMAP3_BALLENTRY(SYS_CLKREQ, "y13", NULL),
1251 _OMAP3_BALLENTRY(SYS_NIRQ, "w16", NULL),
1252 _OMAP3_BALLENTRY(SYS_NRESWARM, "y10", NULL),
1253 _OMAP3_BALLENTRY(SYS_OFF_MODE, "ad23", NULL),
1254 _OMAP3_BALLENTRY(UART1_CTS, "ac2", NULL),
1255 _OMAP3_BALLENTRY(UART1_RTS, "w6", NULL),
1256 _OMAP3_BALLENTRY(UART1_RX, "v7", NULL),
1257 _OMAP3_BALLENTRY(UART1_TX, "w7", NULL),
1258 _OMAP3_BALLENTRY(UART3_CTS_RCTX, "a23", NULL),
1259 _OMAP3_BALLENTRY(UART3_RTS_SD, "b23", NULL),
1260 _OMAP3_BALLENTRY(UART3_RX_IRRX, "b24", NULL),
1261 _OMAP3_BALLENTRY(UART3_TX_IRTX, "c23", NULL),
1262 { .reg_offset = OMAP_MUX_TERMINATOR },
1263};
1264#else
1265#define omap3_cus_ball NULL
1266#endif
1267
1268/*
1269 * Signals different on CBB package compared to superset
1270 */
1271#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBB)
1272static struct omap_mux __initdata omap3_cbb_subset[] = {
1273 _OMAP3_MUXENTRY(CAM_D10, 109,
1274 "cam_d10", NULL, NULL, NULL,
1275 "gpio_109", NULL, NULL, "safe_mode"),
1276 _OMAP3_MUXENTRY(CAM_D11, 110,
1277 "cam_d11", NULL, NULL, NULL,
1278 "gpio_110", NULL, NULL, "safe_mode"),
1279 _OMAP3_MUXENTRY(CAM_D2, 101,
1280 "cam_d2", NULL, NULL, NULL,
1281 "gpio_101", NULL, NULL, "safe_mode"),
1282 _OMAP3_MUXENTRY(CAM_D3, 102,
1283 "cam_d3", NULL, NULL, NULL,
1284 "gpio_102", NULL, NULL, "safe_mode"),
1285 _OMAP3_MUXENTRY(CAM_D4, 103,
1286 "cam_d4", NULL, NULL, NULL,
1287 "gpio_103", NULL, NULL, "safe_mode"),
1288 _OMAP3_MUXENTRY(CAM_D5, 104,
1289 "cam_d5", NULL, NULL, NULL,
1290 "gpio_104", NULL, NULL, "safe_mode"),
1291 _OMAP3_MUXENTRY(CAM_FLD, 98,
1292 "cam_fld", NULL, "cam_global_reset", NULL,
1293 "gpio_98", NULL, NULL, "safe_mode"),
1294 _OMAP3_MUXENTRY(CAM_HS, 94,
1295 "cam_hs", NULL, NULL, NULL,
1296 "gpio_94", NULL, NULL, "safe_mode"),
1297 _OMAP3_MUXENTRY(CAM_PCLK, 97,
1298 "cam_pclk", NULL, NULL, NULL,
1299 "gpio_97", NULL, NULL, "safe_mode"),
1300 _OMAP3_MUXENTRY(CAM_STROBE, 126,
1301 "cam_strobe", NULL, NULL, NULL,
1302 "gpio_126", NULL, NULL, "safe_mode"),
1303 _OMAP3_MUXENTRY(CAM_VS, 95,
1304 "cam_vs", NULL, NULL, NULL,
1305 "gpio_95", NULL, NULL, "safe_mode"),
1306 _OMAP3_MUXENTRY(CAM_WEN, 167,
1307 "cam_wen", NULL, "cam_shutter", NULL,
1308 "gpio_167", NULL, NULL, "safe_mode"),
1309 _OMAP3_MUXENTRY(DSS_DATA6, 76,
1310 "dss_data6", NULL, "uart1_tx", NULL,
1311 "gpio_76", NULL, NULL, "safe_mode"),
1312 _OMAP3_MUXENTRY(DSS_DATA7, 77,
1313 "dss_data7", NULL, "uart1_rx", NULL,
1314 "gpio_77", NULL, NULL, "safe_mode"),
1315 _OMAP3_MUXENTRY(DSS_DATA8, 78,
1316 "dss_data8", NULL, NULL, NULL,
1317 "gpio_78", NULL, NULL, "safe_mode"),
1318 _OMAP3_MUXENTRY(DSS_DATA9, 79,
1319 "dss_data9", NULL, NULL, NULL,
1320 "gpio_79", NULL, NULL, "safe_mode"),
1321 _OMAP3_MUXENTRY(DSS_HSYNC, 67,
1322 "dss_hsync", NULL, NULL, NULL,
1323 "gpio_67", NULL, NULL, "safe_mode"),
1324 _OMAP3_MUXENTRY(DSS_PCLK, 66,
1325 "dss_pclk", NULL, NULL, NULL,
1326 "gpio_66", NULL, NULL, "safe_mode"),
1327 _OMAP3_MUXENTRY(ETK_CLK, 12,
1328 "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
1329 "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL),
1330 _OMAP3_MUXENTRY(ETK_CTL, 13,
1331 "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
1332 "gpio_13", NULL, "hsusb1_tll_clk", NULL),
1333 _OMAP3_MUXENTRY(ETK_D0, 14,
1334 "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
1335 "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL),
1336 _OMAP3_MUXENTRY(ETK_D1, 15,
1337 "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
1338 "gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL),
1339 _OMAP3_MUXENTRY(ETK_D10, 24,
1340 "etk_d10", NULL, "uart1_rx", "hsusb2_clk",
1341 "gpio_24", NULL, "hsusb2_tll_clk", NULL),
1342 _OMAP3_MUXENTRY(ETK_D11, 25,
1343 "etk_d11", NULL, NULL, "hsusb2_stp",
1344 "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL),
1345 _OMAP3_MUXENTRY(ETK_D12, 26,
1346 "etk_d12", NULL, NULL, "hsusb2_dir",
1347 "gpio_26", NULL, "hsusb2_tll_dir", NULL),
1348 _OMAP3_MUXENTRY(ETK_D13, 27,
1349 "etk_d13", NULL, NULL, "hsusb2_nxt",
1350 "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL),
1351 _OMAP3_MUXENTRY(ETK_D14, 28,
1352 "etk_d14", NULL, NULL, "hsusb2_data0",
1353 "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL),
1354 _OMAP3_MUXENTRY(ETK_D15, 29,
1355 "etk_d15", NULL, NULL, "hsusb2_data1",
1356 "gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL),
1357 _OMAP3_MUXENTRY(ETK_D2, 16,
1358 "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
1359 "gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL),
1360 _OMAP3_MUXENTRY(ETK_D3, 17,
1361 "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
1362 "gpio_17", NULL, "hsusb1_tll_data7", NULL),
1363 _OMAP3_MUXENTRY(ETK_D4, 18,
1364 "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
1365 "gpio_18", NULL, "hsusb1_tll_data4", NULL),
1366 _OMAP3_MUXENTRY(ETK_D5, 19,
1367 "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
1368 "gpio_19", NULL, "hsusb1_tll_data5", NULL),
1369 _OMAP3_MUXENTRY(ETK_D6, 20,
1370 "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
1371 "gpio_20", NULL, "hsusb1_tll_data6", NULL),
1372 _OMAP3_MUXENTRY(ETK_D7, 21,
1373 "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
1374 "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL),
1375 _OMAP3_MUXENTRY(ETK_D8, 22,
1376 "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
1377 "gpio_22", NULL, "hsusb1_tll_dir", NULL),
1378 _OMAP3_MUXENTRY(ETK_D9, 23,
1379 "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
1380 "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL),
1381 { .reg_offset = OMAP_MUX_TERMINATOR },
1382};
1383#else
1384#define omap3_cbb_subset NULL
1385#endif
1386
1387/*
1388 * Balls for CBB package
1389 * 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom)
1390 */
1391#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
1392 && defined(CONFIG_OMAP_PACKAGE_CBB)
1393static struct omap_ball __initdata omap3_cbb_ball[] = {
1394 _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
1395 _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
1396 _OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
1397 _OMAP3_BALLENTRY(CAM_D11, "c26", NULL),
1398 _OMAP3_BALLENTRY(CAM_D2, "b24", NULL),
1399 _OMAP3_BALLENTRY(CAM_D3, "c24", NULL),
1400 _OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
1401 _OMAP3_BALLENTRY(CAM_D5, "a25", NULL),
1402 _OMAP3_BALLENTRY(CAM_D6, "k28", NULL),
1403 _OMAP3_BALLENTRY(CAM_D7, "l28", NULL),
1404 _OMAP3_BALLENTRY(CAM_D8, "k27", NULL),
1405 _OMAP3_BALLENTRY(CAM_D9, "l27", NULL),
1406 _OMAP3_BALLENTRY(CAM_FLD, "c23", NULL),
1407 _OMAP3_BALLENTRY(CAM_HS, "a24", NULL),
1408 _OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL),
1409 _OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL),
1410 _OMAP3_BALLENTRY(CAM_VS, "a23", NULL),
1411 _OMAP3_BALLENTRY(CAM_WEN, "b23", NULL),
1412 _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
1413 _OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL),
1414 _OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL),
1415 _OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL),
1416 _OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL),
1417 _OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL),
1418 _OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL),
1419 _OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL),
1420 _OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL),
1421 _OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL),
1422 _OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL),
1423 _OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL),
1424 _OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL),
1425 _OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL),
1426 _OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL),
1427 _OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL),
1428 _OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL),
1429 _OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL),
1430 _OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL),
1431 _OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL),
1432 _OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL),
1433 _OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL),
1434 _OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL),
1435 _OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL),
1436 _OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL),
1437 _OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL),
1438 _OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL),
1439 _OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL),
1440 _OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL),
1441 _OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL),
1442 _OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL),
1443 _OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL),
1444 _OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL),
1445 _OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL),
1446 _OMAP3_BALLENTRY(ETK_CLK, "af10", NULL),
1447 _OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL),
1448 _OMAP3_BALLENTRY(ETK_D0, "af11", NULL),
1449 _OMAP3_BALLENTRY(ETK_D1, "ag12", NULL),
1450 _OMAP3_BALLENTRY(ETK_D10, "ae7", NULL),
1451 _OMAP3_BALLENTRY(ETK_D11, "af7", NULL),
1452 _OMAP3_BALLENTRY(ETK_D12, "ag7", NULL),
1453 _OMAP3_BALLENTRY(ETK_D13, "ah7", NULL),
1454 _OMAP3_BALLENTRY(ETK_D14, "ag8", NULL),
1455 _OMAP3_BALLENTRY(ETK_D15, "ah8", NULL),
1456 _OMAP3_BALLENTRY(ETK_D2, "ah12", NULL),
1457 _OMAP3_BALLENTRY(ETK_D3, "ae13", NULL),
1458 _OMAP3_BALLENTRY(ETK_D4, "ae11", NULL),
1459 _OMAP3_BALLENTRY(ETK_D5, "ah9", NULL),
1460 _OMAP3_BALLENTRY(ETK_D6, "af13", NULL),
1461 _OMAP3_BALLENTRY(ETK_D7, "ah14", NULL),
1462 _OMAP3_BALLENTRY(ETK_D8, "af9", NULL),
1463 _OMAP3_BALLENTRY(ETK_D9, "ag9", NULL),
1464 _OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"),
1465 _OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"),
1466 _OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"),
1467 _OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"),
1468 _OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"),
1469 _OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"),
1470 _OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"),
1471 _OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"),
1472 _OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"),
1473 _OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"),
1474 _OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"),
1475 _OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"),
1476 _OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"),
1477 _OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"),
1478 _OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"),
1479 _OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"),
1480 _OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"),
1481 _OMAP3_BALLENTRY(GPMC_D8, "h2", "ab3"),
1482 _OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"),
1483 _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"),
1484 _OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL),
1485 _OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"),
1486 _OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL),
1487 _OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL),
1488 _OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL),
1489 _OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL),
1490 _OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL),
1491 _OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL),
1492 _OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"),
1493 _OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"),
1494 _OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL),
1495 _OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL),
1496 _OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL),
1497 _OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL),
1498 _OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL),
1499 _OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL),
1500 _OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL),
1501 _OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL),
1502 _OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL),
1503 _OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL),
1504 _OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL),
1505 _OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL),
1506 _OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL),
1507 _OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL),
1508 _OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL),
1509 _OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL),
1510 _OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL),
1511 _OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL),
1512 _OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL),
1513 _OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL),
1514 _OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL),
1515 _OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL),
1516 _OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL),
1517 _OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL),
1518 _OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL),
1519 _OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL),
1520 _OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL),
1521 _OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL),
1522 _OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL),
1523 _OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL),
1524 _OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL),
1525 _OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL),
1526 _OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL),
1527 _OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL),
1528 _OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL),
1529 _OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL),
1530 _OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL),
1531 _OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL),
1532 _OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL),
1533 _OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL),
1534 _OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL),
1535 _OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL),
1536 _OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL),
1537 _OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL),
1538 _OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL),
1539 _OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL),
1540 _OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL),
1541 _OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL),
1542 _OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL),
1543 _OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL),
1544 _OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL),
1545 _OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL),
1546 _OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL),
1547 _OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL),
1548 _OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL),
1549 _OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL),
1550 _OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL),
1551 _OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL),
1552 _OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL),
1553 _OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL),
1554 _OMAP3_BALLENTRY(SDMMC1_DAT4, "p27", NULL),
1555 _OMAP3_BALLENTRY(SDMMC1_DAT5, "p26", NULL),
1556 _OMAP3_BALLENTRY(SDMMC1_DAT6, "r27", NULL),
1557 _OMAP3_BALLENTRY(SDMMC1_DAT7, "r25", NULL),
1558 _OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL),
1559 _OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL),
1560 _OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL),
1561 _OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL),
1562 _OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL),
1563 _OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL),
1564 _OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL),
1565 _OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL),
1566 _OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL),
1567 _OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL),
1568 _OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL),
1569 _OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL),
1570 _OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL),
1571 _OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL),
1572 _OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL),
1573 _OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL),
1574 _OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL),
1575 _OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL),
1576 _OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL),
1577 _OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL),
1578 _OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL),
1579 _OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL),
1580 _OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL),
1581 _OMAP3_BALLENTRY(UART1_CTS, "w8", NULL),
1582 _OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL),
1583 _OMAP3_BALLENTRY(UART1_RX, "y8", NULL),
1584 _OMAP3_BALLENTRY(UART1_TX, "aa8", NULL),
1585 _OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL),
1586 _OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL),
1587 _OMAP3_BALLENTRY(UART2_RX, "ad25", NULL),
1588 _OMAP3_BALLENTRY(UART2_TX, "aa25", NULL),
1589 _OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL),
1590 _OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL),
1591 _OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL),
1592 _OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL),
1593 { .reg_offset = OMAP_MUX_TERMINATOR },
1594};
1595#else
1596#define omap3_cbb_ball NULL
1597#endif
1598
1599/*
1600 * Signals different on 36XX CBP package compared to 34XX CBC package
1601 */
1602#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBP)
1603static struct omap_mux __initdata omap36xx_cbp_subset[] = {
1604 _OMAP3_MUXENTRY(CAM_D0, 99,
1605 "cam_d0", NULL, "csi2_dx2", NULL,
1606 "gpio_99", NULL, NULL, "safe_mode"),
1607 _OMAP3_MUXENTRY(CAM_D1, 100,
1608 "cam_d1", NULL, "csi2_dy2", NULL,
1609 "gpio_100", NULL, NULL, "safe_mode"),
1610 _OMAP3_MUXENTRY(CAM_D10, 109,
1611 "cam_d10", "ssi2_wake", NULL, NULL,
1612 "gpio_109", "hw_dbg8", NULL, "safe_mode"),
1613 _OMAP3_MUXENTRY(CAM_D2, 101,
1614 "cam_d2", "ssi2_rdy_tx", NULL, NULL,
1615 "gpio_101", "hw_dbg4", NULL, "safe_mode"),
1616 _OMAP3_MUXENTRY(CAM_D3, 102,
1617 "cam_d3", "ssi2_dat_rx", NULL, NULL,
1618 "gpio_102", "hw_dbg5", NULL, "safe_mode"),
1619 _OMAP3_MUXENTRY(CAM_D4, 103,
1620 "cam_d4", "ssi2_flag_rx", NULL, NULL,
1621 "gpio_103", "hw_dbg6", NULL, "safe_mode"),
1622 _OMAP3_MUXENTRY(CAM_D5, 104,
1623 "cam_d5", "ssi2_rdy_rx", NULL, NULL,
1624 "gpio_104", "hw_dbg7", NULL, "safe_mode"),
1625 _OMAP3_MUXENTRY(CAM_HS, 94,
1626 "cam_hs", "ssi2_dat_tx", NULL, NULL,
1627 "gpio_94", "hw_dbg0", NULL, "safe_mode"),
1628 _OMAP3_MUXENTRY(CAM_VS, 95,
1629 "cam_vs", "ssi2_flag_tx", NULL, NULL,
1630 "gpio_95", "hw_dbg1", NULL, "safe_mode"),
1631 _OMAP3_MUXENTRY(DSS_DATA0, 70,
1632 "dss_data0", "dsi_dx0", "uart1_cts", NULL,
1633 "gpio_70", NULL, NULL, "safe_mode"),
1634 _OMAP3_MUXENTRY(DSS_DATA1, 71,
1635 "dss_data1", "dsi_dy0", "uart1_rts", NULL,
1636 "gpio_71", NULL, NULL, "safe_mode"),
1637 _OMAP3_MUXENTRY(DSS_DATA2, 72,
1638 "dss_data2", "dsi_dx1", NULL, NULL,
1639 "gpio_72", NULL, NULL, "safe_mode"),
1640 _OMAP3_MUXENTRY(DSS_DATA3, 73,
1641 "dss_data3", "dsi_dy1", NULL, NULL,
1642 "gpio_73", NULL, NULL, "safe_mode"),
1643 _OMAP3_MUXENTRY(DSS_DATA4, 74,
1644 "dss_data4", "dsi_dx2", "uart3_rx_irrx", NULL,
1645 "gpio_74", NULL, NULL, "safe_mode"),
1646 _OMAP3_MUXENTRY(DSS_DATA5, 75,
1647 "dss_data5", "dsi_dy2", "uart3_tx_irtx", NULL,
1648 "gpio_75", NULL, NULL, "safe_mode"),
1649 _OMAP3_MUXENTRY(DSS_DATA6, 76,
1650 "dss_data6", NULL, "uart1_tx", "dssvenc656_data6",
1651 "gpio_76", "hw_dbg14", NULL, "safe_mode"),
1652 _OMAP3_MUXENTRY(DSS_DATA7, 77,
1653 "dss_data7", NULL, "uart1_rx", "dssvenc656_data7",
1654 "gpio_77", "hw_dbg15", NULL, "safe_mode"),
1655 _OMAP3_MUXENTRY(DSS_DATA8, 78,
1656 "dss_data8", NULL, "uart3_rx_irrx", NULL,
1657 "gpio_78", "hw_dbg16", NULL, "safe_mode"),
1658 _OMAP3_MUXENTRY(DSS_DATA9, 79,
1659 "dss_data9", NULL, "uart3_tx_irtx", NULL,
1660 "gpio_79", "hw_dbg17", NULL, "safe_mode"),
1661 _OMAP3_MUXENTRY(ETK_D12, 26,
1662 "etk_d12", "sys_drm_msecure", NULL, "hsusb2_dir",
1663 "gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"),
1664 _OMAP3_MUXENTRY(GPMC_A11, 0,
1665 "gpmc_a11", NULL, NULL, NULL,
1666 NULL, NULL, NULL, "safe_mode"),
1667 _OMAP3_MUXENTRY(GPMC_WAIT2, 64,
1668 "gpmc_wait2", NULL, "uart4_tx", NULL,
1669 "gpio_64", NULL, NULL, "safe_mode"),
1670 _OMAP3_MUXENTRY(GPMC_WAIT3, 65,
1671 "gpmc_wait3", "sys_ndmareq1", "uart4_rx", NULL,
1672 "gpio_65", NULL, NULL, "safe_mode"),
1673 _OMAP3_MUXENTRY(HSUSB0_DATA0, 125,
1674 "hsusb0_data0", NULL, "uart3_tx_irtx", NULL,
1675 "gpio_125", "uart2_tx", NULL, "safe_mode"),
1676 _OMAP3_MUXENTRY(HSUSB0_DATA1, 130,
1677 "hsusb0_data1", NULL, "uart3_rx_irrx", NULL,
1678 "gpio_130", "uart2_rx", NULL, "safe_mode"),
1679 _OMAP3_MUXENTRY(HSUSB0_DATA2, 131,
1680 "hsusb0_data2", NULL, "uart3_rts_sd", NULL,
1681 "gpio_131", "uart2_rts", NULL, "safe_mode"),
1682 _OMAP3_MUXENTRY(HSUSB0_DATA3, 169,
1683 "hsusb0_data3", NULL, "uart3_cts_rctx", NULL,
1684 "gpio_169", "uart2_cts", NULL, "safe_mode"),
1685 _OMAP3_MUXENTRY(MCBSP1_CLKR, 156,
1686 "mcbsp1_clkr", "mcspi4_clk", "sim_cd", NULL,
1687 "gpio_156", NULL, NULL, "safe_mode"),
1688 _OMAP3_MUXENTRY(MCBSP1_FSR, 157,
1689 "mcbsp1_fsr", "adpllv2d_dithering_en1",
1690 "cam_global_reset", NULL,
1691 "gpio_157", NULL, NULL, "safe_mode"),
1692 _OMAP3_MUXENTRY(MCBSP4_CLKX, 152,
1693 "mcbsp4_clkx", "ssi1_dat_rx", NULL, NULL,
1694 "gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"),
1695 _OMAP3_MUXENTRY(MCBSP4_DR, 153,
1696 "mcbsp4_dr", "ssi1_flag_rx", NULL, NULL,
1697 "gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"),
1698 _OMAP3_MUXENTRY(MCBSP4_DX, 154,
1699 "mcbsp4_dx", "ssi1_rdy_rx", NULL, NULL,
1700 "gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"),
1701 _OMAP3_MUXENTRY(MCBSP4_FSX, 155,
1702 "mcbsp4_fsx", "ssi1_wake", NULL, NULL,
1703 "gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"),
1704 _OMAP3_MUXENTRY(MCSPI1_CS1, 175,
1705 "mcspi1_cs1", "adpllv2d_dithering_en2", NULL, "sdmmc3_cmd",
1706 "gpio_175", NULL, NULL, "safe_mode"),
1707 _OMAP3_MUXENTRY(SAD2D_MBUSFLAG, 0,
1708 "sad2d_mbusflag", "mad2d_sbusflag", NULL, NULL,
1709 NULL, NULL, NULL, NULL),
1710 _OMAP3_MUXENTRY(SAD2D_MCAD28, 0,
1711 "sad2d_mcad28", "mad2d_mcad28", NULL, NULL,
1712 NULL, NULL, NULL, NULL),
1713 _OMAP3_MUXENTRY(SAD2D_MCAD29, 0,
1714 "sad2d_mcad29", "mad2d_mcad29", NULL, NULL,
1715 NULL, NULL, NULL, NULL),
1716 _OMAP3_MUXENTRY(SAD2D_MCAD32, 0,
1717 "sad2d_mcad32", "mad2d_mcad32", NULL, NULL,
1718 NULL, NULL, NULL, NULL),
1719 _OMAP3_MUXENTRY(SAD2D_MCAD33, 0,
1720 "sad2d_mcad33", "mad2d_mcad33", NULL, NULL,
1721 NULL, NULL, NULL, NULL),
1722 _OMAP3_MUXENTRY(SAD2D_MCAD34, 0,
1723 "sad2d_mcad34", "mad2d_mcad34", NULL, NULL,
1724 NULL, NULL, NULL, NULL),
1725 _OMAP3_MUXENTRY(SAD2D_MCAD35, 0,
1726 "sad2d_mcad35", "mad2d_mcad35", NULL, NULL,
1727 NULL, NULL, NULL, NULL),
1728 _OMAP3_MUXENTRY(SAD2D_MCAD36, 0,
1729 "sad2d_mcad36", "mad2d_mcad36", NULL, NULL,
1730 NULL, NULL, NULL, NULL),
1731 _OMAP3_MUXENTRY(SAD2D_MREAD, 0,
1732 "sad2d_mread", "mad2d_sread", NULL, NULL,
1733 NULL, NULL, NULL, NULL),
1734 _OMAP3_MUXENTRY(SAD2D_MWRITE, 0,
1735 "sad2d_mwrite", "mad2d_swrite", NULL, NULL,
1736 NULL, NULL, NULL, NULL),
1737 _OMAP3_MUXENTRY(SAD2D_SBUSFLAG, 0,
1738 "sad2d_sbusflag", "mad2d_mbusflag", NULL, NULL,
1739 NULL, NULL, NULL, NULL),
1740 _OMAP3_MUXENTRY(SAD2D_SREAD, 0,
1741 "sad2d_sread", "mad2d_mread", NULL, NULL,
1742 NULL, NULL, NULL, NULL),
1743 _OMAP3_MUXENTRY(SAD2D_SWRITE, 0,
1744 "sad2d_swrite", "mad2d_mwrite", NULL, NULL,
1745 NULL, NULL, NULL, NULL),
1746 _OMAP3_MUXENTRY(SDMMC1_CLK, 120,
1747 "sdmmc1_clk", "ms_clk", NULL, NULL,
1748 "gpio_120", NULL, NULL, "safe_mode"),
1749 _OMAP3_MUXENTRY(SDMMC1_CMD, 121,
1750 "sdmmc1_cmd", "ms_bs", NULL, NULL,
1751 "gpio_121", NULL, NULL, "safe_mode"),
1752 _OMAP3_MUXENTRY(SDMMC1_DAT0, 122,
1753 "sdmmc1_dat0", "ms_dat0", NULL, NULL,
1754 "gpio_122", NULL, NULL, "safe_mode"),
1755 _OMAP3_MUXENTRY(SDMMC1_DAT1, 123,
1756 "sdmmc1_dat1", "ms_dat1", NULL, NULL,
1757 "gpio_123", NULL, NULL, "safe_mode"),
1758 _OMAP3_MUXENTRY(SDMMC1_DAT2, 124,
1759 "sdmmc1_dat2", "ms_dat2", NULL, NULL,
1760 "gpio_124", NULL, NULL, "safe_mode"),
1761 _OMAP3_MUXENTRY(SDMMC1_DAT3, 125,
1762 "sdmmc1_dat3", "ms_dat3", NULL, NULL,
1763 "gpio_125", NULL, NULL, "safe_mode"),
1764 _OMAP3_MUXENTRY(SDRC_CKE0, 0,
1765 "sdrc_cke0", NULL, NULL, NULL,
1766 NULL, NULL, NULL, "safe_mode_out1"),
1767 _OMAP3_MUXENTRY(SDRC_CKE1, 0,
1768 "sdrc_cke1", NULL, NULL, NULL,
1769 NULL, NULL, NULL, "safe_mode_out1"),
1770 _OMAP3_MUXENTRY(SIM_IO, 126,
1771 "sim_io", "sim_io_low_impedance", NULL, NULL,
1772 "gpio_126", NULL, NULL, "safe_mode"),
1773 _OMAP3_MUXENTRY(SIM_CLK, 127,
1774 "sim_clk", NULL, NULL, NULL,
1775 "gpio_127", NULL, NULL, "safe_mode"),
1776 _OMAP3_MUXENTRY(SIM_PWRCTRL, 128,
1777 "sim_pwrctrl", NULL, NULL, NULL,
1778 "gpio_128", NULL, NULL, "safe_mode"),
1779 _OMAP3_MUXENTRY(SIM_RST, 129,
1780 "sim_rst", NULL, NULL, NULL,
1781 "gpio_129", NULL, NULL, "safe_mode"),
1782 _OMAP3_MUXENTRY(SYS_BOOT0, 2,
1783 "sys_boot0", NULL, NULL, "dss_data18",
1784 "gpio_2", NULL, NULL, "safe_mode"),
1785 _OMAP3_MUXENTRY(SYS_BOOT1, 3,
1786 "sys_boot1", NULL, NULL, "dss_data19",
1787 "gpio_3", NULL, NULL, "safe_mode"),
1788 _OMAP3_MUXENTRY(SYS_BOOT3, 5,
1789 "sys_boot3", NULL, NULL, "dss_data20",
1790 "gpio_5", NULL, NULL, "safe_mode"),
1791 _OMAP3_MUXENTRY(SYS_BOOT4, 6,
1792 "sys_boot4", "sdmmc2_dir_dat2", NULL, "dss_data21",
1793 "gpio_6", NULL, NULL, "safe_mode"),
1794 _OMAP3_MUXENTRY(SYS_BOOT5, 7,
1795 "sys_boot5", "sdmmc2_dir_dat3", NULL, "dss_data22",
1796 "gpio_7", NULL, NULL, "safe_mode"),
1797 _OMAP3_MUXENTRY(SYS_BOOT6, 8,
1798 "sys_boot6", NULL, NULL, "dss_data23",
1799 "gpio_8", NULL, NULL, "safe_mode"),
1800 _OMAP3_MUXENTRY(UART1_CTS, 150,
1801 "uart1_cts", "ssi1_rdy_tx", NULL, NULL,
1802 "gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
1803 _OMAP3_MUXENTRY(UART1_RTS, 149,
1804 "uart1_rts", "ssi1_flag_tx", NULL, NULL,
1805 "gpio_149", NULL, NULL, "safe_mode"),
1806 _OMAP3_MUXENTRY(UART1_TX, 148,
1807 "uart1_tx", "ssi1_dat_tx", NULL, NULL,
1808 "gpio_148", NULL, NULL, "safe_mode"),
1809 { .reg_offset = OMAP_MUX_TERMINATOR },
1810};
1811#else
1812#define omap36xx_cbp_subset NULL
1813#endif
1814
1815/*
1816 * Balls for 36XX CBP package
1817 * 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom)
1818 */
1819#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
1820 && defined (CONFIG_OMAP_PACKAGE_CBP)
1821static struct omap_ball __initdata omap36xx_cbp_ball[] = {
1822 _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
1823 _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
1824 _OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
1825 _OMAP3_BALLENTRY(CAM_D11, "c26", NULL),
1826 _OMAP3_BALLENTRY(CAM_D2, "b24", NULL),
1827 _OMAP3_BALLENTRY(CAM_D3, "c24", NULL),
1828 _OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
1829 _OMAP3_BALLENTRY(CAM_D5, "a25", NULL),
1830 _OMAP3_BALLENTRY(CAM_D6, "k28", NULL),
1831 _OMAP3_BALLENTRY(CAM_D7, "l28", NULL),
1832 _OMAP3_BALLENTRY(CAM_D8, "k27", NULL),
1833 _OMAP3_BALLENTRY(CAM_D9, "l27", NULL),
1834 _OMAP3_BALLENTRY(CAM_FLD, "c23", NULL),
1835 _OMAP3_BALLENTRY(CAM_HS, "a24", NULL),
1836 _OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL),
1837 _OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL),
1838 _OMAP3_BALLENTRY(CAM_VS, "a23", NULL),
1839 _OMAP3_BALLENTRY(CAM_WEN, "b23", NULL),
1840 _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
1841 _OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL),
1842 _OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL),
1843 _OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL),
1844 _OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL),
1845 _OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL),
1846 _OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL),
1847 _OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL),
1848 _OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL),
1849 _OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL),
1850 _OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL),
1851 _OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL),
1852 _OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL),
1853 _OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL),
1854 _OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL),
1855 _OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL),
1856 _OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL),
1857 _OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL),
1858 _OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL),
1859 _OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL),
1860 _OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL),
1861 _OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL),
1862 _OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL),
1863 _OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL),
1864 _OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL),
1865 _OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL),
1866 _OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL),
1867 _OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL),
1868 _OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL),
1869 _OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL),
1870 _OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL),
1871 _OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL),
1872 _OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL),
1873 _OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL),
1874 _OMAP3_BALLENTRY(ETK_CLK, "af10", NULL),
1875 _OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL),
1876 _OMAP3_BALLENTRY(ETK_D0, "af11", NULL),
1877 _OMAP3_BALLENTRY(ETK_D1, "ag12", NULL),
1878 _OMAP3_BALLENTRY(ETK_D10, "ae7", NULL),
1879 _OMAP3_BALLENTRY(ETK_D11, "af7", NULL),
1880 _OMAP3_BALLENTRY(ETK_D12, "ag7", NULL),
1881 _OMAP3_BALLENTRY(ETK_D13, "ah7", NULL),
1882 _OMAP3_BALLENTRY(ETK_D14, "ag8", NULL),
1883 _OMAP3_BALLENTRY(ETK_D15, "ah8", NULL),
1884 _OMAP3_BALLENTRY(ETK_D2, "ah12", NULL),
1885 _OMAP3_BALLENTRY(ETK_D3, "ae13", NULL),
1886 _OMAP3_BALLENTRY(ETK_D4, "ae11", NULL),
1887 _OMAP3_BALLENTRY(ETK_D5, "ah9", NULL),
1888 _OMAP3_BALLENTRY(ETK_D6, "af13", NULL),
1889 _OMAP3_BALLENTRY(ETK_D7, "ah14", NULL),
1890 _OMAP3_BALLENTRY(ETK_D8, "af9", NULL),
1891 _OMAP3_BALLENTRY(ETK_D9, "ag9", NULL),
1892 _OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"),
1893 _OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"),
1894 _OMAP3_BALLENTRY(GPMC_A11, NULL, "ac20"),
1895 _OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"),
1896 _OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"),
1897 _OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"),
1898 _OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"),
1899 _OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"),
1900 _OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"),
1901 _OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"),
1902 _OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"),
1903 _OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"),
1904 _OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"),
1905 _OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"),
1906 _OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"),
1907 _OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"),
1908 _OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"),
1909 _OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"),
1910 _OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"),
1911 _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"),
1912 _OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL),
1913 _OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"),
1914 _OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL),
1915 _OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL),
1916 _OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL),
1917 _OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL),
1918 _OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL),
1919 _OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL),
1920 _OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"),
1921 _OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"),
1922 _OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL),
1923 _OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL),
1924 _OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL),
1925 _OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL),
1926 _OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL),
1927 _OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL),
1928 _OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL),
1929 _OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL),
1930 _OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL),
1931 _OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL),
1932 _OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL),
1933 _OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL),
1934 _OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL),
1935 _OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL),
1936 _OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL),
1937 _OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL),
1938 _OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL),
1939 _OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL),
1940 _OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL),
1941 _OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL),
1942 _OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL),
1943 _OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL),
1944 _OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL),
1945 _OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL),
1946 _OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL),
1947 _OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL),
1948 _OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL),
1949 _OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL),
1950 _OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL),
1951 _OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL),
1952 _OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL),
1953 _OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL),
1954 _OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL),
1955 _OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL),
1956 _OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL),
1957 _OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL),
1958 _OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL),
1959 _OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL),
1960 _OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL),
1961 _OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL),
1962 _OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL),
1963 _OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL),
1964 _OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL),
1965 _OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL),
1966 _OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL),
1967 _OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL),
1968 _OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL),
1969 _OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL),
1970 _OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL),
1971 _OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL),
1972 _OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL),
1973 _OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL),
1974 _OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL),
1975 _OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL),
1976 _OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL),
1977 _OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL),
1978 _OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL),
1979 _OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL),
1980 _OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL),
1981 _OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL),
1982 _OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL),
1983 _OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL),
1984 _OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL),
1985 _OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL),
1986 _OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL),
1987 _OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL),
1988 _OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL),
1989 _OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL),
1990 _OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL),
1991 _OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL),
1992 _OMAP3_BALLENTRY(SDRC_CKE0, "h16", "j22"),
1993 _OMAP3_BALLENTRY(SDRC_CKE1, "h17", "j23"),
1994 _OMAP3_BALLENTRY(SIM_CLK, "p26", NULL),
1995 _OMAP3_BALLENTRY(SIM_IO, "p27", NULL),
1996 _OMAP3_BALLENTRY(SIM_PWRCTRL, "r27", NULL),
1997 _OMAP3_BALLENTRY(SIM_RST, "r25", NULL),
1998 _OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL),
1999 _OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL),
2000 _OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL),
2001 _OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL),
2002 _OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL),
2003 _OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL),
2004 _OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL),
2005 _OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL),
2006 _OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL),
2007 _OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL),
2008 _OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL),
2009 _OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL),
2010 _OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL),
2011 _OMAP3_BALLENTRY(UART1_CTS, "w8", NULL),
2012 _OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL),
2013 _OMAP3_BALLENTRY(UART1_RX, "y8", NULL),
2014 _OMAP3_BALLENTRY(UART1_TX, "aa8", NULL),
2015 _OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL),
2016 _OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL),
2017 _OMAP3_BALLENTRY(UART2_RX, "ad25", NULL),
2018 _OMAP3_BALLENTRY(UART2_TX, "aa25", NULL),
2019 _OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL),
2020 _OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL),
2021 _OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL),
2022 _OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL),
2023 { .reg_offset = OMAP_MUX_TERMINATOR },
2024};
2025#else
2026#define omap36xx_cbp_ball NULL
2027#endif
2028
2029int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags)
2030{
2031 struct omap_mux *package_subset;
2032 struct omap_ball *package_balls;
2033
2034 switch (flags & OMAP_PACKAGE_MASK) {
2035 case OMAP_PACKAGE_CBC:
2036 package_subset = omap3_cbc_subset;
2037 package_balls = omap3_cbc_ball;
2038 break;
2039 case OMAP_PACKAGE_CBB:
2040 package_subset = omap3_cbb_subset;
2041 package_balls = omap3_cbb_ball;
2042 break;
2043 case OMAP_PACKAGE_CUS:
2044 package_subset = omap3_cus_subset;
2045 package_balls = omap3_cus_ball;
2046 break;
2047 case OMAP_PACKAGE_CBP:
2048 package_subset = omap36xx_cbp_subset;
2049 package_balls = omap36xx_cbp_ball;
2050 break;
2051 default:
2052 pr_err("%s Unknown omap package, mux disabled\n", __func__);
2053 return -EINVAL;
2054 }
2055
2056 return omap_mux_init("core", OMAP_MUX_GPIO_IN_MODE4,
2057 OMAP3_CONTROL_PADCONF_MUX_PBASE,
2058 OMAP3_CONTROL_PADCONF_MUX_SIZE,
2059 omap3_muxmodes, package_subset, board_subset,
2060 package_balls);
2061}
diff --git a/arch/arm/mach-omap2/mux34xx.h b/arch/arm/mach-omap2/mux34xx.h
deleted file mode 100644
index 3f26d297c082..000000000000
--- a/arch/arm/mach-omap2/mux34xx.h
+++ /dev/null
@@ -1,402 +0,0 @@
1/*
2 * Copyright (C) 2009 Nokia
3 * Copyright (C) 2009 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#define OMAP3_CONTROL_PADCONF_MUX_PBASE 0x48002030LU
11
12#define OMAP3_MUX(mode0, mux_value) \
13{ \
14 .reg_offset = (OMAP3_CONTROL_PADCONF_##mode0##_OFFSET), \
15 .value = (mux_value), \
16}
17
18/*
19 * OMAP3 CONTROL_PADCONF* register offsets for pin-muxing
20 *
21 * Extracted from the TRM. Add 0x48002030 to these values to get the
22 * absolute addresses. The name in the macro is the mode-0 name of
23 * the pin. NOTE: These registers are 16-bits wide.
24 *
25 * Note that 34XX TRM uses MMC instead of SDMMC and SAD2D instead
26 * of CHASSIS for some registers. For the defines, we follow the
27 * 36XX naming, and use SDMMC and CHASSIS.
28 */
29#define OMAP3_CONTROL_PADCONF_SDRC_D0_OFFSET 0x000
30#define OMAP3_CONTROL_PADCONF_SDRC_D1_OFFSET 0x002
31#define OMAP3_CONTROL_PADCONF_SDRC_D2_OFFSET 0x004
32#define OMAP3_CONTROL_PADCONF_SDRC_D3_OFFSET 0x006
33#define OMAP3_CONTROL_PADCONF_SDRC_D4_OFFSET 0x008
34#define OMAP3_CONTROL_PADCONF_SDRC_D5_OFFSET 0x00a
35#define OMAP3_CONTROL_PADCONF_SDRC_D6_OFFSET 0x00c
36#define OMAP3_CONTROL_PADCONF_SDRC_D7_OFFSET 0x00e
37#define OMAP3_CONTROL_PADCONF_SDRC_D8_OFFSET 0x010
38#define OMAP3_CONTROL_PADCONF_SDRC_D9_OFFSET 0x012
39#define OMAP3_CONTROL_PADCONF_SDRC_D10_OFFSET 0x014
40#define OMAP3_CONTROL_PADCONF_SDRC_D11_OFFSET 0x016
41#define OMAP3_CONTROL_PADCONF_SDRC_D12_OFFSET 0x018
42#define OMAP3_CONTROL_PADCONF_SDRC_D13_OFFSET 0x01a
43#define OMAP3_CONTROL_PADCONF_SDRC_D14_OFFSET 0x01c
44#define OMAP3_CONTROL_PADCONF_SDRC_D15_OFFSET 0x01e
45#define OMAP3_CONTROL_PADCONF_SDRC_D16_OFFSET 0x020
46#define OMAP3_CONTROL_PADCONF_SDRC_D17_OFFSET 0x022
47#define OMAP3_CONTROL_PADCONF_SDRC_D18_OFFSET 0x024
48#define OMAP3_CONTROL_PADCONF_SDRC_D19_OFFSET 0x026
49#define OMAP3_CONTROL_PADCONF_SDRC_D20_OFFSET 0x028
50#define OMAP3_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02a
51#define OMAP3_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02c
52#define OMAP3_CONTROL_PADCONF_SDRC_D23_OFFSET 0x02e
53#define OMAP3_CONTROL_PADCONF_SDRC_D24_OFFSET 0x030
54#define OMAP3_CONTROL_PADCONF_SDRC_D25_OFFSET 0x032
55#define OMAP3_CONTROL_PADCONF_SDRC_D26_OFFSET 0x034
56#define OMAP3_CONTROL_PADCONF_SDRC_D27_OFFSET 0x036
57#define OMAP3_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038
58#define OMAP3_CONTROL_PADCONF_SDRC_D29_OFFSET 0x03a
59#define OMAP3_CONTROL_PADCONF_SDRC_D30_OFFSET 0x03c
60#define OMAP3_CONTROL_PADCONF_SDRC_D31_OFFSET 0x03e
61#define OMAP3_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x040
62#define OMAP3_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x042
63#define OMAP3_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x044
64#define OMAP3_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x046
65#define OMAP3_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x048
66#define OMAP3_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a
67#define OMAP3_CONTROL_PADCONF_GPMC_A2_OFFSET 0x04c
68#define OMAP3_CONTROL_PADCONF_GPMC_A3_OFFSET 0x04e
69#define OMAP3_CONTROL_PADCONF_GPMC_A4_OFFSET 0x050
70#define OMAP3_CONTROL_PADCONF_GPMC_A5_OFFSET 0x052
71#define OMAP3_CONTROL_PADCONF_GPMC_A6_OFFSET 0x054
72#define OMAP3_CONTROL_PADCONF_GPMC_A7_OFFSET 0x056
73#define OMAP3_CONTROL_PADCONF_GPMC_A8_OFFSET 0x058
74#define OMAP3_CONTROL_PADCONF_GPMC_A9_OFFSET 0x05a
75#define OMAP3_CONTROL_PADCONF_GPMC_A10_OFFSET 0x05c
76#define OMAP3_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05e
77#define OMAP3_CONTROL_PADCONF_GPMC_D1_OFFSET 0x060
78#define OMAP3_CONTROL_PADCONF_GPMC_D2_OFFSET 0x062
79#define OMAP3_CONTROL_PADCONF_GPMC_D3_OFFSET 0x064
80#define OMAP3_CONTROL_PADCONF_GPMC_D4_OFFSET 0x066
81#define OMAP3_CONTROL_PADCONF_GPMC_D5_OFFSET 0x068
82#define OMAP3_CONTROL_PADCONF_GPMC_D6_OFFSET 0x06a
83#define OMAP3_CONTROL_PADCONF_GPMC_D7_OFFSET 0x06c
84#define OMAP3_CONTROL_PADCONF_GPMC_D8_OFFSET 0x06e
85#define OMAP3_CONTROL_PADCONF_GPMC_D9_OFFSET 0x070
86#define OMAP3_CONTROL_PADCONF_GPMC_D10_OFFSET 0x072
87#define OMAP3_CONTROL_PADCONF_GPMC_D11_OFFSET 0x074
88#define OMAP3_CONTROL_PADCONF_GPMC_D12_OFFSET 0x076
89#define OMAP3_CONTROL_PADCONF_GPMC_D13_OFFSET 0x078
90#define OMAP3_CONTROL_PADCONF_GPMC_D14_OFFSET 0x07a
91#define OMAP3_CONTROL_PADCONF_GPMC_D15_OFFSET 0x07c
92#define OMAP3_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x07e
93#define OMAP3_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x080
94#define OMAP3_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x082
95#define OMAP3_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x084
96#define OMAP3_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x086
97#define OMAP3_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x088
98#define OMAP3_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x08a
99#define OMAP3_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x08c
100#define OMAP3_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x08e
101#define OMAP3_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x090
102#define OMAP3_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x092
103#define OMAP3_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x094
104#define OMAP3_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x096
105#define OMAP3_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x098
106#define OMAP3_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x09a
107#define OMAP3_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x09c
108#define OMAP3_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x09e
109#define OMAP3_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x0a0
110#define OMAP3_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x0a2
111#define OMAP3_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x0a4
112#define OMAP3_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x0a6
113#define OMAP3_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x0a8
114#define OMAP3_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x0aa
115#define OMAP3_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x0ac
116#define OMAP3_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x0ae
117#define OMAP3_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x0b0
118#define OMAP3_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x0b2
119#define OMAP3_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x0b4
120#define OMAP3_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x0b6
121#define OMAP3_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x0b8
122#define OMAP3_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x0ba
123#define OMAP3_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x0bc
124#define OMAP3_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x0be
125#define OMAP3_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x0c0
126#define OMAP3_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x0c2
127#define OMAP3_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x0c4
128#define OMAP3_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x0c6
129#define OMAP3_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x0c8
130#define OMAP3_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x0ca
131#define OMAP3_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x0cc
132#define OMAP3_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x0ce
133#define OMAP3_CONTROL_PADCONF_DSS_DATA18_OFFSET 0x0d0
134#define OMAP3_CONTROL_PADCONF_DSS_DATA19_OFFSET 0x0d2
135#define OMAP3_CONTROL_PADCONF_DSS_DATA20_OFFSET 0x0d4
136#define OMAP3_CONTROL_PADCONF_DSS_DATA21_OFFSET 0x0d6
137#define OMAP3_CONTROL_PADCONF_DSS_DATA22_OFFSET 0x0d8
138#define OMAP3_CONTROL_PADCONF_DSS_DATA23_OFFSET 0x0da
139#define OMAP3_CONTROL_PADCONF_CAM_HS_OFFSET 0x0dc
140#define OMAP3_CONTROL_PADCONF_CAM_VS_OFFSET 0x0de
141#define OMAP3_CONTROL_PADCONF_CAM_XCLKA_OFFSET 0x0e0
142#define OMAP3_CONTROL_PADCONF_CAM_PCLK_OFFSET 0x0e2
143#define OMAP3_CONTROL_PADCONF_CAM_FLD_OFFSET 0x0e4
144#define OMAP3_CONTROL_PADCONF_CAM_D0_OFFSET 0x0e6
145#define OMAP3_CONTROL_PADCONF_CAM_D1_OFFSET 0x0e8
146#define OMAP3_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ea
147#define OMAP3_CONTROL_PADCONF_CAM_D3_OFFSET 0x0ec
148#define OMAP3_CONTROL_PADCONF_CAM_D4_OFFSET 0x0ee
149#define OMAP3_CONTROL_PADCONF_CAM_D5_OFFSET 0x0f0
150#define OMAP3_CONTROL_PADCONF_CAM_D6_OFFSET 0x0f2
151#define OMAP3_CONTROL_PADCONF_CAM_D7_OFFSET 0x0f4
152#define OMAP3_CONTROL_PADCONF_CAM_D8_OFFSET 0x0f6
153#define OMAP3_CONTROL_PADCONF_CAM_D9_OFFSET 0x0f8
154#define OMAP3_CONTROL_PADCONF_CAM_D10_OFFSET 0x0fa
155#define OMAP3_CONTROL_PADCONF_CAM_D11_OFFSET 0x0fc
156#define OMAP3_CONTROL_PADCONF_CAM_XCLKB_OFFSET 0x0fe
157#define OMAP3_CONTROL_PADCONF_CAM_WEN_OFFSET 0x100
158#define OMAP3_CONTROL_PADCONF_CAM_STROBE_OFFSET 0x102
159#define OMAP3_CONTROL_PADCONF_CSI2_DX0_OFFSET 0x104
160#define OMAP3_CONTROL_PADCONF_CSI2_DY0_OFFSET 0x106
161#define OMAP3_CONTROL_PADCONF_CSI2_DX1_OFFSET 0x108
162#define OMAP3_CONTROL_PADCONF_CSI2_DY1_OFFSET 0x10a
163#define OMAP3_CONTROL_PADCONF_MCBSP2_FSX_OFFSET 0x10c
164#define OMAP3_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x10e
165#define OMAP3_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x110
166#define OMAP3_CONTROL_PADCONF_MCBSP2_DX_OFFSET 0x112
167#define OMAP3_CONTROL_PADCONF_SDMMC1_CLK_OFFSET 0x114
168#define OMAP3_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x116
169#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x118
170#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x11a
171#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x11c
172#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x11e
173
174/* SDMMC1_DAT4 - DAT7 are SIM_IO SIM_CLK SIM_PWRCTRL and SIM_RST on 36xx */
175#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT4_OFFSET 0x120
176#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT5_OFFSET 0x122
177#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT6_OFFSET 0x124
178#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT7_OFFSET 0x126
179
180#define OMAP3_CONTROL_PADCONF_SDMMC2_CLK_OFFSET 0x128
181#define OMAP3_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x12a
182#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x12c
183#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x12e
184#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x130
185#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x132
186#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT4_OFFSET 0x134
187#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT5_OFFSET 0x136
188#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT6_OFFSET 0x138
189#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT7_OFFSET 0x13a
190#define OMAP3_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x13c
191#define OMAP3_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x13e
192#define OMAP3_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x140
193#define OMAP3_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x142
194#define OMAP3_CONTROL_PADCONF_UART2_CTS_OFFSET 0x144
195#define OMAP3_CONTROL_PADCONF_UART2_RTS_OFFSET 0x146
196#define OMAP3_CONTROL_PADCONF_UART2_TX_OFFSET 0x148
197#define OMAP3_CONTROL_PADCONF_UART2_RX_OFFSET 0x14a
198#define OMAP3_CONTROL_PADCONF_UART1_TX_OFFSET 0x14c
199#define OMAP3_CONTROL_PADCONF_UART1_RTS_OFFSET 0x14e
200#define OMAP3_CONTROL_PADCONF_UART1_CTS_OFFSET 0x150
201#define OMAP3_CONTROL_PADCONF_UART1_RX_OFFSET 0x152
202#define OMAP3_CONTROL_PADCONF_MCBSP4_CLKX_OFFSET 0x154
203#define OMAP3_CONTROL_PADCONF_MCBSP4_DR_OFFSET 0x156
204#define OMAP3_CONTROL_PADCONF_MCBSP4_DX_OFFSET 0x158
205#define OMAP3_CONTROL_PADCONF_MCBSP4_FSX_OFFSET 0x15a
206#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x15c
207#define OMAP3_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x15e
208#define OMAP3_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x160
209#define OMAP3_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x162
210#define OMAP3_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x164
211#define OMAP3_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x166
212#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x168
213#define OMAP3_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x16a
214#define OMAP3_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x16c
215#define OMAP3_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x16e
216#define OMAP3_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x170
217#define OMAP3_CONTROL_PADCONF_HSUSB0_CLK_OFFSET 0x172
218#define OMAP3_CONTROL_PADCONF_HSUSB0_STP_OFFSET 0x174
219#define OMAP3_CONTROL_PADCONF_HSUSB0_DIR_OFFSET 0x176
220#define OMAP3_CONTROL_PADCONF_HSUSB0_NXT_OFFSET 0x178
221#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA0_OFFSET 0x17a
222#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA1_OFFSET 0x17c
223#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA2_OFFSET 0x17e
224#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA3_OFFSET 0x180
225#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA4_OFFSET 0x182
226#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA5_OFFSET 0x184
227#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA6_OFFSET 0x186
228#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA7_OFFSET 0x188
229#define OMAP3_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x18a
230#define OMAP3_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x18c
231#define OMAP3_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x18e
232#define OMAP3_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x190
233#define OMAP3_CONTROL_PADCONF_I2C3_SCL_OFFSET 0x192
234#define OMAP3_CONTROL_PADCONF_I2C3_SDA_OFFSET 0x194
235#define OMAP3_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x196
236#define OMAP3_CONTROL_PADCONF_MCSPI1_CLK_OFFSET 0x198
237#define OMAP3_CONTROL_PADCONF_MCSPI1_SIMO_OFFSET 0x19a
238#define OMAP3_CONTROL_PADCONF_MCSPI1_SOMI_OFFSET 0x19c
239#define OMAP3_CONTROL_PADCONF_MCSPI1_CS0_OFFSET 0x19e
240#define OMAP3_CONTROL_PADCONF_MCSPI1_CS1_OFFSET 0x1a0
241#define OMAP3_CONTROL_PADCONF_MCSPI1_CS2_OFFSET 0x1a2
242#define OMAP3_CONTROL_PADCONF_MCSPI1_CS3_OFFSET 0x1a4
243#define OMAP3_CONTROL_PADCONF_MCSPI2_CLK_OFFSET 0x1a6
244#define OMAP3_CONTROL_PADCONF_MCSPI2_SIMO_OFFSET 0x1a8
245#define OMAP3_CONTROL_PADCONF_MCSPI2_SOMI_OFFSET 0x1aa
246#define OMAP3_CONTROL_PADCONF_MCSPI2_CS0_OFFSET 0x1ac
247#define OMAP3_CONTROL_PADCONF_MCSPI2_CS1_OFFSET 0x1ae
248#define OMAP3_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x1b0
249#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT2_OFFSET 0x1b2
250#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD0_OFFSET 0x1b4
251#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD1_OFFSET 0x1b6
252#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD2_OFFSET 0x1b8
253#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD3_OFFSET 0x1ba
254#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD4_OFFSET 0x1bc
255#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD5_OFFSET 0x1be
256#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD6_OFFSET 0x1c0
257#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD7_OFFSET 0x1c2
258#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD8_OFFSET 0x1c4
259#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD9_OFFSET 0x1c6
260#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD10_OFFSET 0x1c8
261#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD11_OFFSET 0x1ca
262#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD12_OFFSET 0x1cc
263#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD13_OFFSET 0x1ce
264#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD14_OFFSET 0x1d0
265#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD15_OFFSET 0x1d2
266#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD16_OFFSET 0x1d4
267#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD17_OFFSET 0x1d6
268#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD18_OFFSET 0x1d8
269#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD19_OFFSET 0x1da
270#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD20_OFFSET 0x1dc
271#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD21_OFFSET 0x1de
272#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD22_OFFSET 0x1e0
273#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD23_OFFSET 0x1e2
274#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD24_OFFSET 0x1e4
275#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD25_OFFSET 0x1e6
276#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD26_OFFSET 0x1e8
277#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD27_OFFSET 0x1ea
278#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD28_OFFSET 0x1ec
279#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD29_OFFSET 0x1ee
280#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD30_OFFSET 0x1f0
281#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD31_OFFSET 0x1f2
282#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD32_OFFSET 0x1f4
283#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD33_OFFSET 0x1f6
284#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD34_OFFSET 0x1f8
285#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD35_OFFSET 0x1fa
286#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD36_OFFSET 0x1fc
287
288/* Note that 34xx TRM has SAD2D instead of CHASSIS for these */
289#define OMAP3_CONTROL_PADCONF_CHASSIS_CLK26MI_OFFSET 0x1fe
290#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESPWRON_OFFSET 0x200
291#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESWARW_OFFSET 0x202
292#define OMAP3_CONTROL_PADCONF_CHASSIS_NIRQ_OFFSET 0x204
293#define OMAP3_CONTROL_PADCONF_CHASSIS_FIQ_OFFSET 0x206
294#define OMAP3_CONTROL_PADCONF_CHASSIS_ARMIRQ_OFFSET 0x208
295#define OMAP3_CONTROL_PADCONF_CHASSIS_IVAIRQ_OFFSET 0x20a
296#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ0_OFFSET 0x20c
297#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ1_OFFSET 0x20e
298#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ2_OFFSET 0x210
299#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ3_OFFSET 0x212
300#define OMAP3_CONTROL_PADCONF_CHASSIS_NTRST_OFFSET 0x214
301#define OMAP3_CONTROL_PADCONF_CHASSIS_TDI_OFFSET 0x216
302#define OMAP3_CONTROL_PADCONF_CHASSIS_TDO_OFFSET 0x218
303#define OMAP3_CONTROL_PADCONF_CHASSIS_TMS_OFFSET 0x21a
304#define OMAP3_CONTROL_PADCONF_CHASSIS_TCK_OFFSET 0x21c
305#define OMAP3_CONTROL_PADCONF_CHASSIS_RTCK_OFFSET 0x21e
306#define OMAP3_CONTROL_PADCONF_CHASSIS_MSTDBY_OFFSET 0x220
307#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEREQ_OFFSET 0x222
308#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEACK_OFFSET 0x224
309
310#define OMAP3_CONTROL_PADCONF_SAD2D_MWRITE_OFFSET 0x226
311#define OMAP3_CONTROL_PADCONF_SAD2D_SWRITE_OFFSET 0x228
312#define OMAP3_CONTROL_PADCONF_SAD2D_MREAD_OFFSET 0x22a
313#define OMAP3_CONTROL_PADCONF_SAD2D_SREAD_OFFSET 0x22c
314#define OMAP3_CONTROL_PADCONF_SAD2D_MBUSFLAG_OFFSET 0x22e
315#define OMAP3_CONTROL_PADCONF_SAD2D_SBUSFLAG_OFFSET 0x230
316#define OMAP3_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x232
317#define OMAP3_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x234
318
319/* 36xx only */
320#define OMAP3_CONTROL_PADCONF_GPMC_A11_OFFSET 0x236
321#define OMAP3_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x570
322#define OMAP3_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x572
323#define OMAP3_CONTROL_PADCONF_SDRC_A0_OFFSET 0x574
324#define OMAP3_CONTROL_PADCONF_SDRC_A1_OFFSET 0x576
325#define OMAP3_CONTROL_PADCONF_SDRC_A2_OFFSET 0x578
326#define OMAP3_CONTROL_PADCONF_SDRC_A3_OFFSET 0x57a
327#define OMAP3_CONTROL_PADCONF_SDRC_A4_OFFSET 0x57c
328#define OMAP3_CONTROL_PADCONF_SDRC_A5_OFFSET 0x57e
329#define OMAP3_CONTROL_PADCONF_SDRC_A6_OFFSET 0x580
330#define OMAP3_CONTROL_PADCONF_SDRC_A7_OFFSET 0x582
331#define OMAP3_CONTROL_PADCONF_SDRC_A8_OFFSET 0x584
332#define OMAP3_CONTROL_PADCONF_SDRC_A9_OFFSET 0x586
333#define OMAP3_CONTROL_PADCONF_SDRC_A10_OFFSET 0x588
334#define OMAP3_CONTROL_PADCONF_SDRC_A11_OFFSET 0x58a
335#define OMAP3_CONTROL_PADCONF_SDRC_A12_OFFSET 0x58c
336#define OMAP3_CONTROL_PADCONF_SDRC_A13_OFFSET 0x58e
337#define OMAP3_CONTROL_PADCONF_SDRC_A14_OFFSET 0x590
338#define OMAP3_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x592
339#define OMAP3_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x594
340#define OMAP3_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x596
341#define OMAP3_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x598
342#define OMAP3_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x59a
343#define OMAP3_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x59c
344#define OMAP3_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x59e
345#define OMAP3_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x5a0
346#define OMAP3_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x5a2
347#define OMAP3_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x5a4
348
349/* 36xx only, these are SDMMC1_DAT4 - DAT7 on 34xx */
350#define OMAP3_CONTROL_PADCONF_SIM_IO_OFFSET 0x120
351#define OMAP3_CONTROL_PADCONF_SIM_CLK_OFFSET 0x122
352#define OMAP3_CONTROL_PADCONF_SIM_PWRCTRL_OFFSET 0x124
353#define OMAP3_CONTROL_PADCONF_SIM_RST_OFFSET 0x126
354
355#define OMAP3_CONTROL_PADCONF_ETK_CLK_OFFSET 0x5a8
356#define OMAP3_CONTROL_PADCONF_ETK_CTL_OFFSET 0x5aa
357#define OMAP3_CONTROL_PADCONF_ETK_D0_OFFSET 0x5ac
358#define OMAP3_CONTROL_PADCONF_ETK_D1_OFFSET 0x5ae
359#define OMAP3_CONTROL_PADCONF_ETK_D2_OFFSET 0x5b0
360#define OMAP3_CONTROL_PADCONF_ETK_D3_OFFSET 0x5b2
361#define OMAP3_CONTROL_PADCONF_ETK_D4_OFFSET 0x5b4
362#define OMAP3_CONTROL_PADCONF_ETK_D5_OFFSET 0x5b6
363#define OMAP3_CONTROL_PADCONF_ETK_D6_OFFSET 0x5b8
364#define OMAP3_CONTROL_PADCONF_ETK_D7_OFFSET 0x5ba
365#define OMAP3_CONTROL_PADCONF_ETK_D8_OFFSET 0x5bc
366#define OMAP3_CONTROL_PADCONF_ETK_D9_OFFSET 0x5be
367#define OMAP3_CONTROL_PADCONF_ETK_D10_OFFSET 0x5c0
368#define OMAP3_CONTROL_PADCONF_ETK_D11_OFFSET 0x5c2
369#define OMAP3_CONTROL_PADCONF_ETK_D12_OFFSET 0x5c4
370#define OMAP3_CONTROL_PADCONF_ETK_D13_OFFSET 0x5c6
371#define OMAP3_CONTROL_PADCONF_ETK_D14_OFFSET 0x5c8
372#define OMAP3_CONTROL_PADCONF_ETK_D15_OFFSET 0x5ca
373#define OMAP3_CONTROL_PADCONF_I2C4_SCL_OFFSET 0x9d0
374#define OMAP3_CONTROL_PADCONF_I2C4_SDA_OFFSET 0x9d2
375#define OMAP3_CONTROL_PADCONF_SYS_32K_OFFSET 0x9d4
376#define OMAP3_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x9d6
377#define OMAP3_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x9d8
378#define OMAP3_CONTROL_PADCONF_SYS_BOOT0_OFFSET 0x9da
379#define OMAP3_CONTROL_PADCONF_SYS_BOOT1_OFFSET 0x9dc
380#define OMAP3_CONTROL_PADCONF_SYS_BOOT2_OFFSET 0x9de
381#define OMAP3_CONTROL_PADCONF_SYS_BOOT3_OFFSET 0x9e0
382#define OMAP3_CONTROL_PADCONF_SYS_BOOT4_OFFSET 0x9e2
383#define OMAP3_CONTROL_PADCONF_SYS_BOOT5_OFFSET 0x9e4
384#define OMAP3_CONTROL_PADCONF_SYS_BOOT6_OFFSET 0x9e6
385#define OMAP3_CONTROL_PADCONF_SYS_OFF_MODE_OFFSET 0x9e8
386#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT1_OFFSET 0x9ea
387#define OMAP3_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x9ec
388#define OMAP3_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x9ee
389#define OMAP3_CONTROL_PADCONF_JTAG_TMS_TMSC_OFFSET 0x9f0
390#define OMAP3_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x9f2
391#define OMAP3_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x9f4
392#define OMAP3_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x9f6
393#define OMAP3_CONTROL_PADCONF_SAD2D_SWAKEUP_OFFSET 0xa1c
394#define OMAP3_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0xa1e
395#define OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET 0xa20
396#define OMAP3_CONTROL_PADCONF_GPIO_127 0xa24
397#define OMAP3_CONTROL_PADCONF_GPIO_126 0xa26
398#define OMAP3_CONTROL_PADCONF_GPIO_128 0xa28
399#define OMAP3_CONTROL_PADCONF_GPIO_129 0xa2a
400
401#define OMAP3_CONTROL_PADCONF_MUX_SIZE \
402 (OMAP3_CONTROL_PADCONF_GPIO_129 + 0x2)
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index ad982465efd0..7d62ad48c7c9 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -48,6 +48,7 @@
48#include <asm/smp_scu.h> 48#include <asm/smp_scu.h>
49#include <asm/pgalloc.h> 49#include <asm/pgalloc.h>
50#include <asm/suspend.h> 50#include <asm/suspend.h>
51#include <asm/virt.h>
51#include <asm/hardware/cache-l2x0.h> 52#include <asm/hardware/cache-l2x0.h>
52 53
53#include "soc.h" 54#include "soc.h"
@@ -244,10 +245,9 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
244 save_state = 1; 245 save_state = 1;
245 break; 246 break;
246 case PWRDM_POWER_RET: 247 case PWRDM_POWER_RET:
247 if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) { 248 if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
248 save_state = 0; 249 save_state = 0;
249 break; 250 break;
250 }
251 default: 251 default:
252 /* 252 /*
253 * CPUx CSWR is invalid hardware state. Also CPUx OSWR 253 * CPUx CSWR is invalid hardware state. Also CPUx OSWR
@@ -371,8 +371,12 @@ int __init omap4_mpuss_init(void)
371 pm_info = &per_cpu(omap4_pm_info, 0x0); 371 pm_info = &per_cpu(omap4_pm_info, 0x0);
372 if (sar_base) { 372 if (sar_base) {
373 pm_info->scu_sar_addr = sar_base + SCU_OFFSET0; 373 pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
374 pm_info->wkup_sar_addr = sar_base + 374 if (cpu_is_omap44xx())
375 CPU0_WAKEUP_NS_PA_ADDR_OFFSET; 375 pm_info->wkup_sar_addr = sar_base +
376 CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
377 else
378 pm_info->wkup_sar_addr = sar_base +
379 OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
376 pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0; 380 pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
377 } 381 }
378 pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm"); 382 pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
@@ -391,8 +395,12 @@ int __init omap4_mpuss_init(void)
391 pm_info = &per_cpu(omap4_pm_info, 0x1); 395 pm_info = &per_cpu(omap4_pm_info, 0x1);
392 if (sar_base) { 396 if (sar_base) {
393 pm_info->scu_sar_addr = sar_base + SCU_OFFSET1; 397 pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
394 pm_info->wkup_sar_addr = sar_base + 398 if (cpu_is_omap44xx())
395 CPU1_WAKEUP_NS_PA_ADDR_OFFSET; 399 pm_info->wkup_sar_addr = sar_base +
400 CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
401 else
402 pm_info->wkup_sar_addr = sar_base +
403 OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
396 pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1; 404 pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
397 } 405 }
398 406
@@ -453,15 +461,24 @@ void __init omap4_mpuss_early_init(void)
453{ 461{
454 unsigned long startup_pa; 462 unsigned long startup_pa;
455 463
456 if (!cpu_is_omap44xx()) 464 if (!(cpu_is_omap44xx() || soc_is_omap54xx()))
457 return; 465 return;
458 466
459 sar_base = omap4_get_sar_ram_base(); 467 sar_base = omap4_get_sar_ram_base();
460 468
461 if (cpu_is_omap443x()) 469 if (cpu_is_omap443x())
462 startup_pa = virt_to_phys(omap4_secondary_startup); 470 startup_pa = virt_to_phys(omap4_secondary_startup);
463 else 471 else if (cpu_is_omap446x())
464 startup_pa = virt_to_phys(omap4460_secondary_startup); 472 startup_pa = virt_to_phys(omap4460_secondary_startup);
473 else if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
474 startup_pa = virt_to_phys(omap5_secondary_hyp_startup);
475 else
476 startup_pa = virt_to_phys(omap5_secondary_startup);
465 477
466 writel_relaxed(startup_pa, sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET); 478 if (cpu_is_omap44xx())
479 writel_relaxed(startup_pa, sar_base +
480 CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
481 else
482 writel_relaxed(startup_pa, sar_base +
483 OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
467} 484}
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index 792b1069f724..5b2966a0f733 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -31,6 +31,8 @@
31/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */ 31/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
32#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04 32#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04
33#define CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xa08 33#define CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xa08
34#define OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xe00
35#define OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xe04
34 36
35#define SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x500) 37#define SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x500)
36#define SAR_SECURE_RAM_SIZE_OFFSET (SAR_BANK3_OFFSET + 0x504) 38#define SAR_SECURE_RAM_SIZE_OFFSET (SAR_BANK3_OFFSET + 0x504)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 1052b29697b8..759e1d45ba25 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -160,7 +160,6 @@
160#include "prm44xx.h" 160#include "prm44xx.h"
161#include "prm33xx.h" 161#include "prm33xx.h"
162#include "prminst44xx.h" 162#include "prminst44xx.h"
163#include "mux.h"
164#include "pm.h" 163#include "pm.h"
165 164
166/* Name of the OMAP hwmod for the MPU */ 165/* Name of the OMAP hwmod for the MPU */
@@ -217,9 +216,6 @@ static LIST_HEAD(omap_hwmod_list);
217/* mpu_oh: used to add/remove MPU initiator from sleepdep list */ 216/* mpu_oh: used to add/remove MPU initiator from sleepdep list */
218static struct omap_hwmod *mpu_oh; 217static struct omap_hwmod *mpu_oh;
219 218
220/* io_chain_lock: used to serialize reconfigurations of the I/O chain */
221static DEFINE_SPINLOCK(io_chain_lock);
222
223/* 219/*
224 * linkspace: ptr to a buffer that struct omap_hwmod_link records are 220 * linkspace: ptr to a buffer that struct omap_hwmod_link records are
225 * allocated from - used to reduce the number of small memory 221 * allocated from - used to reduce the number of small memory
@@ -594,51 +590,6 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
594} 590}
595 591
596/** 592/**
597 * _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux
598 * @oh: struct omap_hwmod *
599 * @set_wake: bool value indicating to set (true) or clear (false) wakeup enable
600 *
601 * Set or clear the I/O pad wakeup flag in the mux entries for the
602 * hwmod @oh. This function changes the @oh->mux->pads_dynamic array
603 * in memory. If the hwmod is currently idled, and the new idle
604 * values don't match the previous ones, this function will also
605 * update the SCM PADCTRL registers. Otherwise, if the hwmod is not
606 * currently idled, this function won't touch the hardware: the new
607 * mux settings are written to the SCM PADCTRL registers when the
608 * hwmod is idled. No return value.
609 */
610static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake)
611{
612 struct omap_device_pad *pad;
613 bool change = false;
614 u16 prev_idle;
615 int j;
616
617 if (!oh->mux || !oh->mux->enabled)
618 return;
619
620 for (j = 0; j < oh->mux->nr_pads_dynamic; j++) {
621 pad = oh->mux->pads_dynamic[j];
622
623 if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP))
624 continue;
625
626 prev_idle = pad->idle;
627
628 if (set_wake)
629 pad->idle |= OMAP_WAKEUP_EN;
630 else
631 pad->idle &= ~OMAP_WAKEUP_EN;
632
633 if (prev_idle != pad->idle)
634 change = true;
635 }
636
637 if (change && oh->_state == _HWMOD_STATE_IDLE)
638 omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
639}
640
641/**
642 * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware 593 * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
643 * @oh: struct omap_hwmod * 594 * @oh: struct omap_hwmod *
644 * 595 *
@@ -2018,29 +1969,6 @@ static int _reset(struct omap_hwmod *oh)
2018} 1969}
2019 1970
2020/** 1971/**
2021 * _reconfigure_io_chain - clear any I/O chain wakeups and reconfigure chain
2022 *
2023 * Call the appropriate PRM function to clear any logged I/O chain
2024 * wakeups and to reconfigure the chain. This apparently needs to be
2025 * done upon every mux change. Since hwmods can be concurrently
2026 * enabled and idled, hold a spinlock around the I/O chain
2027 * reconfiguration sequence. No return value.
2028 *
2029 * XXX When the PRM code is moved to drivers, this function can be removed,
2030 * as the PRM infrastructure should abstract this.
2031 */
2032static void _reconfigure_io_chain(void)
2033{
2034 unsigned long flags;
2035
2036 spin_lock_irqsave(&io_chain_lock, flags);
2037
2038 omap_prm_reconfigure_io_chain();
2039
2040 spin_unlock_irqrestore(&io_chain_lock, flags);
2041}
2042
2043/**
2044 * _omap4_update_context_lost - increment hwmod context loss counter if 1972 * _omap4_update_context_lost - increment hwmod context loss counter if
2045 * hwmod context was lost, and clear hardware context loss reg 1973 * hwmod context was lost, and clear hardware context loss reg
2046 * @oh: hwmod to check for context loss 1974 * @oh: hwmod to check for context loss
@@ -2109,18 +2037,9 @@ static int _enable(struct omap_hwmod *oh)
2109 2037
2110 /* 2038 /*
2111 * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled 2039 * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled
2112 * state at init. Now that someone is really trying to enable 2040 * state at init.
2113 * them, just ensure that the hwmod mux is set.
2114 */ 2041 */
2115 if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { 2042 if (oh->_int_flags & _HWMOD_SKIP_ENABLE) {
2116 /*
2117 * If the caller has mux data populated, do the mux'ing
2118 * which wouldn't have been done as part of the _enable()
2119 * done during setup.
2120 */
2121 if (oh->mux)
2122 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
2123
2124 oh->_int_flags &= ~_HWMOD_SKIP_ENABLE; 2043 oh->_int_flags &= ~_HWMOD_SKIP_ENABLE;
2125 return 0; 2044 return 0;
2126 } 2045 }
@@ -2145,16 +2064,6 @@ static int _enable(struct omap_hwmod *oh)
2145 if (_are_all_hardreset_lines_asserted(oh)) 2064 if (_are_all_hardreset_lines_asserted(oh))
2146 return 0; 2065 return 0;
2147 2066
2148 /* Mux pins for device runtime if populated */
2149 if (oh->mux && (!oh->mux->enabled ||
2150 ((oh->_state == _HWMOD_STATE_IDLE) &&
2151 oh->mux->pads_dynamic))) {
2152 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
2153 _reconfigure_io_chain();
2154 } else if (oh->flags & HWMOD_RECONFIG_IO_CHAIN) {
2155 _reconfigure_io_chain();
2156 }
2157
2158 _add_initiator_dep(oh, mpu_oh); 2067 _add_initiator_dep(oh, mpu_oh);
2159 2068
2160 if (oh->clkdm) { 2069 if (oh->clkdm) {
@@ -2260,14 +2169,6 @@ static int _idle(struct omap_hwmod *oh)
2260 clkdm_hwmod_disable(oh->clkdm, oh); 2169 clkdm_hwmod_disable(oh->clkdm, oh);
2261 } 2170 }
2262 2171
2263 /* Mux pins for device idle if populated */
2264 if (oh->mux && oh->mux->pads_dynamic) {
2265 omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
2266 _reconfigure_io_chain();
2267 } else if (oh->flags & HWMOD_RECONFIG_IO_CHAIN) {
2268 _reconfigure_io_chain();
2269 }
2270
2271 oh->_state = _HWMOD_STATE_IDLE; 2172 oh->_state = _HWMOD_STATE_IDLE;
2272 2173
2273 return 0; 2174 return 0;
@@ -2334,10 +2235,6 @@ static int _shutdown(struct omap_hwmod *oh)
2334 for (i = 0; i < oh->rst_lines_cnt; i++) 2235 for (i = 0; i < oh->rst_lines_cnt; i++)
2335 _assert_hardreset(oh, oh->rst_lines[i].name); 2236 _assert_hardreset(oh, oh->rst_lines[i].name);
2336 2237
2337 /* Mux pins to safe mode or use populated off mode values */
2338 if (oh->mux)
2339 omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED);
2340
2341 oh->_state = _HWMOD_STATE_DISABLED; 2238 oh->_state = _HWMOD_STATE_DISABLED;
2342 2239
2343 return 0; 2240 return 0;
@@ -3729,7 +3626,6 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
3729 _write_sysconfig(v, oh); 3626 _write_sysconfig(v, oh);
3730 } 3627 }
3731 3628
3732 _set_idle_ioring_wakeup(oh, true);
3733 spin_unlock_irqrestore(&oh->_lock, flags); 3629 spin_unlock_irqrestore(&oh->_lock, flags);
3734 3630
3735 return 0; 3631 return 0;
@@ -3762,7 +3658,6 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
3762 _write_sysconfig(v, oh); 3658 _write_sysconfig(v, oh);
3763 } 3659 }
3764 3660
3765 _set_idle_ioring_wakeup(oh, false);
3766 spin_unlock_irqrestore(&oh->_lock, flags); 3661 spin_unlock_irqrestore(&oh->_lock, flags);
3767 3662
3768 return 0; 3663 return 0;
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
index c1e98d589100..6d2e32462df9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
@@ -17,156 +17,11 @@
17 17
18#include "omap_hwmod_common_data.h" 18#include "omap_hwmod_common_data.h"
19 19
20struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
21 {
22 .pa_start = 0x4809c000,
23 .pa_end = 0x4809c1ff,
24 .flags = ADDR_TYPE_RT,
25 },
26 { }
27};
28
29struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
30 {
31 .pa_start = 0x480b4000,
32 .pa_end = 0x480b41ff,
33 .flags = ADDR_TYPE_RT,
34 },
35 { }
36};
37
38struct omap_hwmod_addr_space omap2_i2c1_addr_space[] = {
39 {
40 .pa_start = 0x48070000,
41 .pa_end = 0x48070000 + SZ_128 - 1,
42 .flags = ADDR_TYPE_RT,
43 },
44 { }
45};
46
47struct omap_hwmod_addr_space omap2_i2c2_addr_space[] = {
48 {
49 .pa_start = 0x48072000,
50 .pa_end = 0x48072000 + SZ_128 - 1,
51 .flags = ADDR_TYPE_RT,
52 },
53 { }
54};
55
56struct omap_hwmod_addr_space omap2_dss_addrs[] = {
57 {
58 .pa_start = 0x48050000,
59 .pa_end = 0x48050000 + SZ_1K - 1,
60 .flags = ADDR_TYPE_RT
61 },
62 { }
63};
64
65struct omap_hwmod_addr_space omap2_dss_dispc_addrs[] = {
66 {
67 .pa_start = 0x48050400,
68 .pa_end = 0x48050400 + SZ_1K - 1,
69 .flags = ADDR_TYPE_RT
70 },
71 { }
72};
73
74struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[] = {
75 {
76 .pa_start = 0x48050800,
77 .pa_end = 0x48050800 + SZ_1K - 1,
78 .flags = ADDR_TYPE_RT
79 },
80 { }
81};
82
83struct omap_hwmod_addr_space omap2_dss_venc_addrs[] = {
84 {
85 .pa_start = 0x48050C00,
86 .pa_end = 0x48050C00 + SZ_1K - 1,
87 .flags = ADDR_TYPE_RT
88 },
89 { }
90};
91
92struct omap_hwmod_addr_space omap2_timer10_addrs[] = {
93 {
94 .pa_start = 0x48086000,
95 .pa_end = 0x48086000 + SZ_1K - 1,
96 .flags = ADDR_TYPE_RT
97 },
98 { }
99};
100
101struct omap_hwmod_addr_space omap2_timer11_addrs[] = {
102 {
103 .pa_start = 0x48088000,
104 .pa_end = 0x48088000 + SZ_1K - 1,
105 .flags = ADDR_TYPE_RT
106 },
107 { }
108};
109
110struct omap_hwmod_addr_space omap2xxx_timer12_addrs[] = {
111 {
112 .pa_start = 0x4808a000,
113 .pa_end = 0x4808a000 + SZ_1K - 1,
114 .flags = ADDR_TYPE_RT
115 },
116 { }
117};
118
119struct omap_hwmod_addr_space omap2_mcspi1_addr_space[] = {
120 {
121 .pa_start = 0x48098000,
122 .pa_end = 0x48098000 + SZ_256 - 1,
123 .flags = ADDR_TYPE_RT,
124 },
125 { }
126};
127
128struct omap_hwmod_addr_space omap2_mcspi2_addr_space[] = {
129 {
130 .pa_start = 0x4809a000,
131 .pa_end = 0x4809a000 + SZ_256 - 1,
132 .flags = ADDR_TYPE_RT,
133 },
134 { }
135};
136
137struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
138 {
139 .pa_start = 0x480b8000,
140 .pa_end = 0x480b8000 + SZ_256 - 1,
141 .flags = ADDR_TYPE_RT,
142 },
143 { }
144};
145
146struct omap_hwmod_addr_space omap2_dma_system_addrs[] = { 20struct omap_hwmod_addr_space omap2_dma_system_addrs[] = {
147 { 21 {
148 .pa_start = 0x48056000, 22 .pa_start = 0x48056000,
149 .pa_end = 0x48056000 + SZ_4K - 1, 23 .pa_end = 0x48056000 + SZ_4K - 1,
150 .flags = ADDR_TYPE_RT 24 .flags = ADDR_TYPE_RT,
151 },
152 { }
153};
154
155struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = {
156 {
157 .name = "mpu",
158 .pa_start = 0x48074000,
159 .pa_end = 0x480740ff,
160 .flags = ADDR_TYPE_RT
161 },
162 { }
163};
164
165struct omap_hwmod_addr_space omap2_hdq1w_addr_space[] = {
166 {
167 .pa_start = 0x480b2000,
168 .pa_end = 0x480b2fff,
169 .flags = ADDR_TYPE_RT,
170 }, 25 },
171 { } 26 { },
172}; 27};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index c6c6384de867..cfaeb0f78cc8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -45,204 +45,31 @@ struct omap_hwmod_class omap2_venc_hwmod_class = {
45 .name = "venc", 45 .name = "venc",
46}; 46};
47 47
48
49/* Common DMA request line data */
50struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
51 { .name = "rx", .dma_req = 50, },
52 { .name = "tx", .dma_req = 49, },
53 { .dma_req = -1 }
54};
55
56struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
57 { .name = "rx", .dma_req = 52, },
58 { .name = "tx", .dma_req = 51, },
59 { .dma_req = -1 }
60};
61
62struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
63 { .name = "rx", .dma_req = 54, },
64 { .name = "tx", .dma_req = 53, },
65 { .dma_req = -1 }
66};
67
68struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
69 { .name = "tx", .dma_req = 27 },
70 { .name = "rx", .dma_req = 28 },
71 { .dma_req = -1 }
72};
73
74struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
75 { .name = "tx", .dma_req = 29 },
76 { .name = "rx", .dma_req = 30 },
77 { .dma_req = -1 }
78};
79
80struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
81 { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
82 { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
83 { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
84 { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
85 { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
86 { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
87 { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
88 { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
89 { .dma_req = -1 }
90};
91
92struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
93 { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
94 { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
95 { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
96 { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
97 { .dma_req = -1 }
98};
99
100struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
101 { .name = "rx", .dma_req = 32 },
102 { .name = "tx", .dma_req = 31 },
103 { .dma_req = -1 }
104};
105
106struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
107 { .name = "rx", .dma_req = 34 },
108 { .name = "tx", .dma_req = 33 },
109 { .dma_req = -1 }
110};
111
112struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
113 { .name = "rx", .dma_req = 18 },
114 { .name = "tx", .dma_req = 17 },
115 { .dma_req = -1 }
116};
117
118/* Other IP block data */
119
120
121/* 48/*
122 * omap_hwmod class data 49 * omap_hwmod class data
123 */ 50 */
124 51
125struct omap_hwmod_class l3_hwmod_class = { 52struct omap_hwmod_class l3_hwmod_class = {
126 .name = "l3" 53 .name = "l3",
127}; 54};
128 55
129struct omap_hwmod_class l4_hwmod_class = { 56struct omap_hwmod_class l4_hwmod_class = {
130 .name = "l4" 57 .name = "l4",
131}; 58};
132 59
133struct omap_hwmod_class mpu_hwmod_class = { 60struct omap_hwmod_class mpu_hwmod_class = {
134 .name = "mpu" 61 .name = "mpu",
135}; 62};
136 63
137struct omap_hwmod_class iva_hwmod_class = { 64struct omap_hwmod_class iva_hwmod_class = {
138 .name = "iva" 65 .name = "iva",
139}; 66};
140 67
141/* Common MPU IRQ line data */ 68/* Common MPU IRQ line data */
142 69
143struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
144 { .irq = 37 + OMAP_INTC_START, },
145 { .irq = -1 },
146};
147
148struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
149 { .irq = 38 + OMAP_INTC_START, },
150 { .irq = -1 },
151};
152
153struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
154 { .irq = 39 + OMAP_INTC_START, },
155 { .irq = -1 },
156};
157
158struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
159 { .irq = 40 + OMAP_INTC_START, },
160 { .irq = -1 },
161};
162
163struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
164 { .irq = 41 + OMAP_INTC_START, },
165 { .irq = -1 },
166};
167
168struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
169 { .irq = 42 + OMAP_INTC_START, },
170 { .irq = -1 },
171};
172
173struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
174 { .irq = 43 + OMAP_INTC_START, },
175 { .irq = -1 },
176};
177
178struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
179 { .irq = 44 + OMAP_INTC_START, },
180 { .irq = -1 },
181};
182
183struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
184 { .irq = 45 + OMAP_INTC_START, },
185 { .irq = -1 },
186};
187
188struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
189 { .irq = 46 + OMAP_INTC_START, },
190 { .irq = -1 },
191};
192
193struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
194 { .irq = 47 + OMAP_INTC_START, },
195 { .irq = -1 },
196};
197
198struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
199 { .irq = 72 + OMAP_INTC_START, },
200 { .irq = -1 },
201};
202
203struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
204 { .irq = 73 + OMAP_INTC_START, },
205 { .irq = -1 },
206};
207
208struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
209 { .irq = 74 + OMAP_INTC_START, },
210 { .irq = -1 },
211};
212
213struct omap_hwmod_irq_info omap2_dispc_irqs[] = { 70struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
214 { .irq = 25 + OMAP_INTC_START, }, 71 { .irq = 25 + OMAP_INTC_START, },
215 { .irq = -1 }, 72 { .irq = -1, },
216};
217
218struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
219 { .irq = 56 + OMAP_INTC_START, },
220 { .irq = -1 },
221};
222
223struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
224 { .irq = 57 + OMAP_INTC_START, },
225 { .irq = -1 },
226};
227
228struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
229 { .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */
230 { .irq = -1 },
231};
232
233struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
234 { .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */
235 { .irq = -1 },
236};
237
238struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
239 { .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */
240 { .irq = -1 },
241};
242
243struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
244 { .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */
245 { .irq = -1 },
246}; 73};
247 74
248struct omap_hwmod_irq_info omap2_dma_system_irqs[] = { 75struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
@@ -250,17 +77,7 @@ struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
250 { .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */ 77 { .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */
251 { .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */ 78 { .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */
252 { .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */ 79 { .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */
253 { .irq = -1 }, 80 { .irq = -1, },
254};
255
256struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
257 { .irq = 65 + OMAP_INTC_START, },
258 { .irq = -1 },
259};
260
261struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
262 { .irq = 66 + OMAP_INTC_START, },
263 { .irq = -1 },
264}; 81};
265 82
266struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = { 83struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
@@ -277,9 +94,3 @@ struct omap_hwmod_class omap2_hdq1w_class = {
277 .sysc = &omap2_hdq1w_sysc, 94 .sysc = &omap2_hdq1w_sysc,
278 .reset = &omap_hdq1w_reset, 95 .reset = &omap_hdq1w_reset,
279}; 96};
280
281struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
282 { .irq = 58 + OMAP_INTC_START, },
283 { .irq = -1 },
284};
285
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 656861c29d5c..9b30b6b471ae 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -191,7 +191,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
191 .master = &omap2xxx_l4_core_hwmod, 191 .master = &omap2xxx_l4_core_hwmod,
192 .slave = &omap2xxx_dss_core_hwmod, 192 .slave = &omap2xxx_dss_core_hwmod,
193 .clk = "dss_ick", 193 .clk = "dss_ick",
194 .addr = omap2_dss_addrs,
195 .fw = { 194 .fw = {
196 .omap2 = { 195 .omap2 = {
197 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 196 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
@@ -206,7 +205,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
206 .master = &omap2xxx_l4_core_hwmod, 205 .master = &omap2xxx_l4_core_hwmod,
207 .slave = &omap2xxx_dss_dispc_hwmod, 206 .slave = &omap2xxx_dss_dispc_hwmod,
208 .clk = "dss_ick", 207 .clk = "dss_ick",
209 .addr = omap2_dss_dispc_addrs,
210 .fw = { 208 .fw = {
211 .omap2 = { 209 .omap2 = {
212 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, 210 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
@@ -221,7 +219,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
221 .master = &omap2xxx_l4_core_hwmod, 219 .master = &omap2xxx_l4_core_hwmod,
222 .slave = &omap2xxx_dss_rfbi_hwmod, 220 .slave = &omap2xxx_dss_rfbi_hwmod,
223 .clk = "dss_ick", 221 .clk = "dss_ick",
224 .addr = omap2_dss_rfbi_addrs,
225 .fw = { 222 .fw = {
226 .omap2 = { 223 .omap2 = {
227 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 224 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
@@ -236,7 +233,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
236 .master = &omap2xxx_l4_core_hwmod, 233 .master = &omap2xxx_l4_core_hwmod,
237 .slave = &omap2xxx_dss_venc_hwmod, 234 .slave = &omap2xxx_dss_venc_hwmod,
238 .clk = "dss_ick", 235 .clk = "dss_ick",
239 .addr = omap2_dss_venc_addrs,
240 .fw = { 236 .fw = {
241 .omap2 = { 237 .omap2 = {
242 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, 238 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 36bcd2e75422..e047033caa3e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -569,7 +569,6 @@ struct omap_hwmod omap2xxx_dss_core_hwmod = {
569struct omap_hwmod omap2xxx_dss_dispc_hwmod = { 569struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
570 .name = "dss_dispc", 570 .name = "dss_dispc",
571 .class = &omap2_dispc_hwmod_class, 571 .class = &omap2_dispc_hwmod_class,
572 .mpu_irqs = omap2_dispc_irqs,
573 .main_clk = "dss1_fck", 572 .main_clk = "dss1_fck",
574 .prcm = { 573 .prcm = {
575 .omap2 = { 574 .omap2 = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
index d3e61d1a02d7..434bd1a77229 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
@@ -68,6 +68,7 @@ extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart6;
68extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc; 68extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc;
69extern struct omap_hwmod_ocp_if am33xx_l3_main__sha0; 69extern struct omap_hwmod_ocp_if am33xx_l3_main__sha0;
70extern struct omap_hwmod_ocp_if am33xx_l3_main__aes0; 70extern struct omap_hwmod_ocp_if am33xx_l3_main__aes0;
71extern struct omap_hwmod_ocp_if am33xx_l4_per__rng;
71 72
72extern struct omap_hwmod am33xx_l3_main_hwmod; 73extern struct omap_hwmod am33xx_l3_main_hwmod;
73extern struct omap_hwmod am33xx_l3_s_hwmod; 74extern struct omap_hwmod am33xx_l3_s_hwmod;
@@ -80,6 +81,7 @@ extern struct omap_hwmod am33xx_gfx_hwmod;
80extern struct omap_hwmod am33xx_prcm_hwmod; 81extern struct omap_hwmod am33xx_prcm_hwmod;
81extern struct omap_hwmod am33xx_aes0_hwmod; 82extern struct omap_hwmod am33xx_aes0_hwmod;
82extern struct omap_hwmod am33xx_sha0_hwmod; 83extern struct omap_hwmod am33xx_sha0_hwmod;
84extern struct omap_hwmod am33xx_rng_hwmod;
83extern struct omap_hwmod am33xx_ocmcram_hwmod; 85extern struct omap_hwmod am33xx_ocmcram_hwmod;
84extern struct omap_hwmod am33xx_smartreflex0_hwmod; 86extern struct omap_hwmod am33xx_smartreflex0_hwmod;
85extern struct omap_hwmod am33xx_smartreflex1_hwmod; 87extern struct omap_hwmod am33xx_smartreflex1_hwmod;
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
index 10dff2f0086a..8236e5c49ec3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
@@ -547,3 +547,11 @@ struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
547 .addr = am33xx_aes0_addrs, 547 .addr = am33xx_aes0_addrs,
548 .user = OCP_USER_MPU | OCP_USER_SDMA, 548 .user = OCP_USER_MPU | OCP_USER_SDMA,
549}; 549};
550
551/* l4 per -> rng */
552struct omap_hwmod_ocp_if am33xx_l4_per__rng = {
553 .master = &am33xx_l4_ls_hwmod,
554 .slave = &am33xx_rng_hwmod,
555 .clk = "rng_fck",
556 .user = OCP_USER_MPU,
557};
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
index e2d84aa7f595..de06a1d5ffab 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
@@ -268,6 +268,33 @@ struct omap_hwmod am33xx_sha0_hwmod = {
268 }, 268 },
269}; 269};
270 270
271/* rng */
272static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
273 .rev_offs = 0x1fe0,
274 .sysc_offs = 0x1fe4,
275 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
276 .idlemodes = SIDLE_FORCE | SIDLE_NO,
277 .sysc_fields = &omap_hwmod_sysc_type1,
278};
279
280static struct omap_hwmod_class am33xx_rng_hwmod_class = {
281 .name = "rng",
282 .sysc = &am33xx_rng_sysc,
283};
284
285struct omap_hwmod am33xx_rng_hwmod = {
286 .name = "rng",
287 .class = &am33xx_rng_hwmod_class,
288 .clkdm_name = "l4ls_clkdm",
289 .flags = HWMOD_SWSUP_SIDLE,
290 .main_clk = "rng_fck",
291 .prcm = {
292 .omap4 = {
293 .modulemode = MODULEMODE_SWCTRL,
294 },
295 },
296};
297
271/* ocmcram */ 298/* ocmcram */
272static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { 299static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
273 .name = "ocmcram", 300 .name = "ocmcram",
@@ -1315,6 +1342,7 @@ static void omap_hwmod_am33xx_clkctrl(void)
1315 CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET); 1342 CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1316 CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET); 1343 CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1317 CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET); 1344 CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
1345 CLKCTRL(am33xx_rng_hwmod, AM33XX_CM_PER_RNG_CLKCTRL_OFFSET);
1318} 1346}
1319 1347
1320static void omap_hwmod_am33xx_rst(void) 1348static void omap_hwmod_am33xx_rst(void)
@@ -1388,6 +1416,7 @@ static void omap_hwmod_am43xx_clkctrl(void)
1388 CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET); 1416 CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1389 CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET); 1417 CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1390 CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET); 1418 CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1419 CLKCTRL(am33xx_rng_hwmod, AM43XX_CM_PER_RNG_CLKCTRL_OFFSET);
1391} 1420}
1392 1421
1393static void omap_hwmod_am43xx_rst(void) 1422static void omap_hwmod_am43xx_rst(void)
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index e1c2025d6d3e..6dc51a774a26 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -503,41 +503,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
503 .flags = OCPIF_SWSUP_IDLE, 503 .flags = OCPIF_SWSUP_IDLE,
504}; 504};
505 505
506/* rng */
507static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
508 .rev_offs = 0x1fe0,
509 .sysc_offs = 0x1fe4,
510 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
511 .idlemodes = SIDLE_FORCE | SIDLE_NO,
512 .sysc_fields = &omap_hwmod_sysc_type1,
513};
514
515static struct omap_hwmod_class am33xx_rng_hwmod_class = {
516 .name = "rng",
517 .sysc = &am33xx_rng_sysc,
518};
519
520static struct omap_hwmod am33xx_rng_hwmod = {
521 .name = "rng",
522 .class = &am33xx_rng_hwmod_class,
523 .clkdm_name = "l4ls_clkdm",
524 .flags = HWMOD_SWSUP_SIDLE,
525 .main_clk = "rng_fck",
526 .prcm = {
527 .omap4 = {
528 .clkctrl_offs = AM33XX_CM_PER_RNG_CLKCTRL_OFFSET,
529 .modulemode = MODULEMODE_SWCTRL,
530 },
531 },
532};
533
534static struct omap_hwmod_ocp_if am33xx_l4_per__rng = {
535 .master = &am33xx_l4_ls_hwmod,
536 .slave = &am33xx_rng_hwmod,
537 .clk = "rng_fck",
538 .user = OCP_USER_MPU,
539};
540
541static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { 506static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
542 &am33xx_l3_main__emif, 507 &am33xx_l3_main__emif,
543 &am33xx_mpu__l3_main, 508 &am33xx_mpu__l3_main,
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 1cc4a6f3954e..56f917ec8621 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -53,16 +53,10 @@
53 */ 53 */
54 54
55/* L3 */ 55/* L3 */
56static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
57 { .irq = 9 + OMAP_INTC_START, },
58 { .irq = 10 + OMAP_INTC_START, },
59 { .irq = -1 },
60};
61 56
62static struct omap_hwmod omap3xxx_l3_main_hwmod = { 57static struct omap_hwmod omap3xxx_l3_main_hwmod = {
63 .name = "l3_main", 58 .name = "l3_main",
64 .class = &l3_hwmod_class, 59 .class = &l3_hwmod_class,
65 .mpu_irqs = omap3xxx_l3_main_irqs,
66 .flags = HWMOD_NO_IDLEST, 60 .flags = HWMOD_NO_IDLEST,
67}; 61};
68 62
@@ -95,14 +89,9 @@ static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
95}; 89};
96 90
97/* MPU */ 91/* MPU */
98static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
99 { .name = "pmu", .irq = 3 + OMAP_INTC_START },
100 { .irq = -1 }
101};
102 92
103static struct omap_hwmod omap3xxx_mpu_hwmod = { 93static struct omap_hwmod omap3xxx_mpu_hwmod = {
104 .name = "mpu", 94 .name = "mpu",
105 .mpu_irqs = omap3xxx_mpu_irqs,
106 .class = &mpu_hwmod_class, 95 .class = &mpu_hwmod_class,
107 .main_clk = "arm_fck", 96 .main_clk = "arm_fck",
108}; 97};
@@ -128,7 +117,7 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
128 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, 117 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
129 .idlest_reg_id = 1, 118 .idlest_reg_id = 1,
130 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, 119 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
131 } 120 },
132 }, 121 },
133}; 122};
134 123
@@ -197,7 +186,6 @@ static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
197/* timer1 */ 186/* timer1 */
198static struct omap_hwmod omap3xxx_timer1_hwmod = { 187static struct omap_hwmod omap3xxx_timer1_hwmod = {
199 .name = "timer1", 188 .name = "timer1",
200 .mpu_irqs = omap2_timer1_mpu_irqs,
201 .main_clk = "gpt1_fck", 189 .main_clk = "gpt1_fck",
202 .prcm = { 190 .prcm = {
203 .omap2 = { 191 .omap2 = {
@@ -216,7 +204,6 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
216/* timer2 */ 204/* timer2 */
217static struct omap_hwmod omap3xxx_timer2_hwmod = { 205static struct omap_hwmod omap3xxx_timer2_hwmod = {
218 .name = "timer2", 206 .name = "timer2",
219 .mpu_irqs = omap2_timer2_mpu_irqs,
220 .main_clk = "gpt2_fck", 207 .main_clk = "gpt2_fck",
221 .prcm = { 208 .prcm = {
222 .omap2 = { 209 .omap2 = {
@@ -234,7 +221,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
234/* timer3 */ 221/* timer3 */
235static struct omap_hwmod omap3xxx_timer3_hwmod = { 222static struct omap_hwmod omap3xxx_timer3_hwmod = {
236 .name = "timer3", 223 .name = "timer3",
237 .mpu_irqs = omap2_timer3_mpu_irqs,
238 .main_clk = "gpt3_fck", 224 .main_clk = "gpt3_fck",
239 .prcm = { 225 .prcm = {
240 .omap2 = { 226 .omap2 = {
@@ -252,7 +238,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
252/* timer4 */ 238/* timer4 */
253static struct omap_hwmod omap3xxx_timer4_hwmod = { 239static struct omap_hwmod omap3xxx_timer4_hwmod = {
254 .name = "timer4", 240 .name = "timer4",
255 .mpu_irqs = omap2_timer4_mpu_irqs,
256 .main_clk = "gpt4_fck", 241 .main_clk = "gpt4_fck",
257 .prcm = { 242 .prcm = {
258 .omap2 = { 243 .omap2 = {
@@ -270,7 +255,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
270/* timer5 */ 255/* timer5 */
271static struct omap_hwmod omap3xxx_timer5_hwmod = { 256static struct omap_hwmod omap3xxx_timer5_hwmod = {
272 .name = "timer5", 257 .name = "timer5",
273 .mpu_irqs = omap2_timer5_mpu_irqs,
274 .main_clk = "gpt5_fck", 258 .main_clk = "gpt5_fck",
275 .prcm = { 259 .prcm = {
276 .omap2 = { 260 .omap2 = {
@@ -289,7 +273,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
289/* timer6 */ 273/* timer6 */
290static struct omap_hwmod omap3xxx_timer6_hwmod = { 274static struct omap_hwmod omap3xxx_timer6_hwmod = {
291 .name = "timer6", 275 .name = "timer6",
292 .mpu_irqs = omap2_timer6_mpu_irqs,
293 .main_clk = "gpt6_fck", 276 .main_clk = "gpt6_fck",
294 .prcm = { 277 .prcm = {
295 .omap2 = { 278 .omap2 = {
@@ -308,7 +291,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
308/* timer7 */ 291/* timer7 */
309static struct omap_hwmod omap3xxx_timer7_hwmod = { 292static struct omap_hwmod omap3xxx_timer7_hwmod = {
310 .name = "timer7", 293 .name = "timer7",
311 .mpu_irqs = omap2_timer7_mpu_irqs,
312 .main_clk = "gpt7_fck", 294 .main_clk = "gpt7_fck",
313 .prcm = { 295 .prcm = {
314 .omap2 = { 296 .omap2 = {
@@ -327,7 +309,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
327/* timer8 */ 309/* timer8 */
328static struct omap_hwmod omap3xxx_timer8_hwmod = { 310static struct omap_hwmod omap3xxx_timer8_hwmod = {
329 .name = "timer8", 311 .name = "timer8",
330 .mpu_irqs = omap2_timer8_mpu_irqs,
331 .main_clk = "gpt8_fck", 312 .main_clk = "gpt8_fck",
332 .prcm = { 313 .prcm = {
333 .omap2 = { 314 .omap2 = {
@@ -346,7 +327,6 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
346/* timer9 */ 327/* timer9 */
347static struct omap_hwmod omap3xxx_timer9_hwmod = { 328static struct omap_hwmod omap3xxx_timer9_hwmod = {
348 .name = "timer9", 329 .name = "timer9",
349 .mpu_irqs = omap2_timer9_mpu_irqs,
350 .main_clk = "gpt9_fck", 330 .main_clk = "gpt9_fck",
351 .prcm = { 331 .prcm = {
352 .omap2 = { 332 .omap2 = {
@@ -365,7 +345,6 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
365/* timer10 */ 345/* timer10 */
366static struct omap_hwmod omap3xxx_timer10_hwmod = { 346static struct omap_hwmod omap3xxx_timer10_hwmod = {
367 .name = "timer10", 347 .name = "timer10",
368 .mpu_irqs = omap2_timer10_mpu_irqs,
369 .main_clk = "gpt10_fck", 348 .main_clk = "gpt10_fck",
370 .prcm = { 349 .prcm = {
371 .omap2 = { 350 .omap2 = {
@@ -384,7 +363,6 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
384/* timer11 */ 363/* timer11 */
385static struct omap_hwmod omap3xxx_timer11_hwmod = { 364static struct omap_hwmod omap3xxx_timer11_hwmod = {
386 .name = "timer11", 365 .name = "timer11",
387 .mpu_irqs = omap2_timer11_mpu_irqs,
388 .main_clk = "gpt11_fck", 366 .main_clk = "gpt11_fck",
389 .prcm = { 367 .prcm = {
390 .omap2 = { 368 .omap2 = {
@@ -401,14 +379,9 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
401}; 379};
402 380
403/* timer12 */ 381/* timer12 */
404static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
405 { .irq = 95 + OMAP_INTC_START, },
406 { .irq = -1 },
407};
408 382
409static struct omap_hwmod omap3xxx_timer12_hwmod = { 383static struct omap_hwmod omap3xxx_timer12_hwmod = {
410 .name = "timer12", 384 .name = "timer12",
411 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
412 .main_clk = "gpt12_fck", 385 .main_clk = "gpt12_fck",
413 .prcm = { 386 .prcm = {
414 .omap2 = { 387 .omap2 = {
@@ -485,8 +458,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
485/* UART1 */ 458/* UART1 */
486static struct omap_hwmod omap3xxx_uart1_hwmod = { 459static struct omap_hwmod omap3xxx_uart1_hwmod = {
487 .name = "uart1", 460 .name = "uart1",
488 .mpu_irqs = omap2_uart1_mpu_irqs,
489 .sdma_reqs = omap2_uart1_sdma_reqs,
490 .main_clk = "uart1_fck", 461 .main_clk = "uart1_fck",
491 .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE, 462 .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
492 .prcm = { 463 .prcm = {
@@ -504,8 +475,6 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
504/* UART2 */ 475/* UART2 */
505static struct omap_hwmod omap3xxx_uart2_hwmod = { 476static struct omap_hwmod omap3xxx_uart2_hwmod = {
506 .name = "uart2", 477 .name = "uart2",
507 .mpu_irqs = omap2_uart2_mpu_irqs,
508 .sdma_reqs = omap2_uart2_sdma_reqs,
509 .main_clk = "uart2_fck", 478 .main_clk = "uart2_fck",
510 .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE, 479 .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
511 .prcm = { 480 .prcm = {
@@ -523,8 +492,6 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
523/* UART3 */ 492/* UART3 */
524static struct omap_hwmod omap3xxx_uart3_hwmod = { 493static struct omap_hwmod omap3xxx_uart3_hwmod = {
525 .name = "uart3", 494 .name = "uart3",
526 .mpu_irqs = omap2_uart3_mpu_irqs,
527 .sdma_reqs = omap2_uart3_sdma_reqs,
528 .main_clk = "uart3_fck", 495 .main_clk = "uart3_fck",
529 .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS | 496 .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
530 HWMOD_SWSUP_SIDLE, 497 HWMOD_SWSUP_SIDLE,
@@ -541,21 +508,10 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
541}; 508};
542 509
543/* UART4 */ 510/* UART4 */
544static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
545 { .irq = 80 + OMAP_INTC_START, },
546 { .irq = -1 },
547};
548 511
549static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
550 { .name = "rx", .dma_req = 82, },
551 { .name = "tx", .dma_req = 81, },
552 { .dma_req = -1 }
553};
554 512
555static struct omap_hwmod omap36xx_uart4_hwmod = { 513static struct omap_hwmod omap36xx_uart4_hwmod = {
556 .name = "uart4", 514 .name = "uart4",
557 .mpu_irqs = uart4_mpu_irqs,
558 .sdma_reqs = uart4_sdma_reqs,
559 .main_clk = "uart4_fck", 515 .main_clk = "uart4_fck",
560 .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE, 516 .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
561 .prcm = { 517 .prcm = {
@@ -570,16 +526,7 @@ static struct omap_hwmod omap36xx_uart4_hwmod = {
570 .class = &omap2_uart_class, 526 .class = &omap2_uart_class,
571}; 527};
572 528
573static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
574 { .irq = 84 + OMAP_INTC_START, },
575 { .irq = -1 },
576};
577 529
578static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
579 { .name = "rx", .dma_req = 55, },
580 { .name = "tx", .dma_req = 54, },
581 { .dma_req = -1 }
582};
583 530
584/* 531/*
585 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or 532 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
@@ -597,8 +544,6 @@ static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
597 544
598static struct omap_hwmod am35xx_uart4_hwmod = { 545static struct omap_hwmod am35xx_uart4_hwmod = {
599 .name = "uart4", 546 .name = "uart4",
600 .mpu_irqs = am35xx_uart4_mpu_irqs,
601 .sdma_reqs = am35xx_uart4_sdma_reqs,
602 .main_clk = "uart4_fck", 547 .main_clk = "uart4_fck",
603 .prcm = { 548 .prcm = {
604 .omap2 = { 549 .omap2 = {
@@ -625,7 +570,7 @@ static struct omap_hwmod_class i2c_class = {
625static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { 570static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
626 { .name = "dispc", .dma_req = 5 }, 571 { .name = "dispc", .dma_req = 5 },
627 { .name = "dsi1", .dma_req = 74 }, 572 { .name = "dsi1", .dma_req = 74 },
628 { .dma_req = -1 } 573 { .dma_req = -1, },
629}; 574};
630 575
631/* dss */ 576/* dss */
@@ -714,7 +659,7 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
714 }, 659 },
715 }, 660 },
716 .flags = HWMOD_NO_IDLEST, 661 .flags = HWMOD_NO_IDLEST,
717 .dev_attr = &omap2_3_dss_dispc_dev_attr 662 .dev_attr = &omap2_3_dss_dispc_dev_attr,
718}; 663};
719 664
720/* 665/*
@@ -738,11 +683,6 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
738 .sysc = &omap3xxx_dsi_sysc, 683 .sysc = &omap3xxx_dsi_sysc,
739}; 684};
740 685
741static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
742 { .irq = 25 + OMAP_INTC_START, },
743 { .irq = -1 },
744};
745
746/* dss_dsi1 */ 686/* dss_dsi1 */
747static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { 687static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
748 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 688 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
@@ -751,7 +691,6 @@ static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
751static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { 691static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
752 .name = "dss_dsi1", 692 .name = "dss_dsi1",
753 .class = &omap3xxx_dsi_hwmod_class, 693 .class = &omap3xxx_dsi_hwmod_class,
754 .mpu_irqs = omap3xxx_dsi1_irqs,
755 .main_clk = "dss1_alwon_fck", 694 .main_clk = "dss1_alwon_fck",
756 .prcm = { 695 .prcm = {
757 .omap2 = { 696 .omap2 = {
@@ -815,8 +754,6 @@ static struct omap_i2c_dev_attr i2c1_dev_attr = {
815static struct omap_hwmod omap3xxx_i2c1_hwmod = { 754static struct omap_hwmod omap3xxx_i2c1_hwmod = {
816 .name = "i2c1", 755 .name = "i2c1",
817 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 756 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
818 .mpu_irqs = omap2_i2c1_mpu_irqs,
819 .sdma_reqs = omap2_i2c1_sdma_reqs,
820 .main_clk = "i2c1_fck", 757 .main_clk = "i2c1_fck",
821 .prcm = { 758 .prcm = {
822 .omap2 = { 759 .omap2 = {
@@ -840,8 +777,6 @@ static struct omap_i2c_dev_attr i2c2_dev_attr = {
840static struct omap_hwmod omap3xxx_i2c2_hwmod = { 777static struct omap_hwmod omap3xxx_i2c2_hwmod = {
841 .name = "i2c2", 778 .name = "i2c2",
842 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 779 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
843 .mpu_irqs = omap2_i2c2_mpu_irqs,
844 .sdma_reqs = omap2_i2c2_sdma_reqs,
845 .main_clk = "i2c2_fck", 780 .main_clk = "i2c2_fck",
846 .prcm = { 781 .prcm = {
847 .omap2 = { 782 .omap2 = {
@@ -862,22 +797,11 @@ static struct omap_i2c_dev_attr i2c3_dev_attr = {
862 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 797 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
863}; 798};
864 799
865static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
866 { .irq = 61 + OMAP_INTC_START, },
867 { .irq = -1 },
868};
869 800
870static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
871 { .name = "tx", .dma_req = 25 },
872 { .name = "rx", .dma_req = 26 },
873 { .dma_req = -1 }
874};
875 801
876static struct omap_hwmod omap3xxx_i2c3_hwmod = { 802static struct omap_hwmod omap3xxx_i2c3_hwmod = {
877 .name = "i2c3", 803 .name = "i2c3",
878 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 804 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
879 .mpu_irqs = i2c3_mpu_irqs,
880 .sdma_reqs = i2c3_sdma_reqs,
881 .main_clk = "i2c3_fck", 805 .main_clk = "i2c3_fck",
882 .prcm = { 806 .prcm = {
883 .omap2 = { 807 .omap2 = {
@@ -928,7 +852,6 @@ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
928static struct omap_hwmod omap3xxx_gpio1_hwmod = { 852static struct omap_hwmod omap3xxx_gpio1_hwmod = {
929 .name = "gpio1", 853 .name = "gpio1",
930 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 854 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
931 .mpu_irqs = omap2_gpio1_irqs,
932 .main_clk = "gpio1_ick", 855 .main_clk = "gpio1_ick",
933 .opt_clks = gpio1_opt_clks, 856 .opt_clks = gpio1_opt_clks,
934 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 857 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
@@ -953,7 +876,6 @@ static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
953static struct omap_hwmod omap3xxx_gpio2_hwmod = { 876static struct omap_hwmod omap3xxx_gpio2_hwmod = {
954 .name = "gpio2", 877 .name = "gpio2",
955 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 878 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
956 .mpu_irqs = omap2_gpio2_irqs,
957 .main_clk = "gpio2_ick", 879 .main_clk = "gpio2_ick",
958 .opt_clks = gpio2_opt_clks, 880 .opt_clks = gpio2_opt_clks,
959 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 881 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
@@ -978,7 +900,6 @@ static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
978static struct omap_hwmod omap3xxx_gpio3_hwmod = { 900static struct omap_hwmod omap3xxx_gpio3_hwmod = {
979 .name = "gpio3", 901 .name = "gpio3",
980 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 902 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
981 .mpu_irqs = omap2_gpio3_irqs,
982 .main_clk = "gpio3_ick", 903 .main_clk = "gpio3_ick",
983 .opt_clks = gpio3_opt_clks, 904 .opt_clks = gpio3_opt_clks,
984 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), 905 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
@@ -1003,7 +924,6 @@ static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1003static struct omap_hwmod omap3xxx_gpio4_hwmod = { 924static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1004 .name = "gpio4", 925 .name = "gpio4",
1005 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 926 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1006 .mpu_irqs = omap2_gpio4_irqs,
1007 .main_clk = "gpio4_ick", 927 .main_clk = "gpio4_ick",
1008 .opt_clks = gpio4_opt_clks, 928 .opt_clks = gpio4_opt_clks,
1009 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), 929 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
@@ -1021,10 +941,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1021}; 941};
1022 942
1023/* gpio5 */ 943/* gpio5 */
1024static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1025 { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
1026 { .irq = -1 },
1027};
1028 944
1029static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { 945static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1030 { .role = "dbclk", .clk = "gpio5_dbck", }, 946 { .role = "dbclk", .clk = "gpio5_dbck", },
@@ -1033,7 +949,6 @@ static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1033static struct omap_hwmod omap3xxx_gpio5_hwmod = { 949static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1034 .name = "gpio5", 950 .name = "gpio5",
1035 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 951 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1036 .mpu_irqs = omap3xxx_gpio5_irqs,
1037 .main_clk = "gpio5_ick", 952 .main_clk = "gpio5_ick",
1038 .opt_clks = gpio5_opt_clks, 953 .opt_clks = gpio5_opt_clks,
1039 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), 954 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
@@ -1051,10 +966,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1051}; 966};
1052 967
1053/* gpio6 */ 968/* gpio6 */
1054static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1055 { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1056 { .irq = -1 },
1057};
1058 969
1059static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { 970static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1060 { .role = "dbclk", .clk = "gpio6_dbck", }, 971 { .role = "dbclk", .clk = "gpio6_dbck", },
@@ -1063,7 +974,6 @@ static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1063static struct omap_hwmod omap3xxx_gpio6_hwmod = { 974static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1064 .name = "gpio6", 975 .name = "gpio6",
1065 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 976 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1066 .mpu_irqs = omap3xxx_gpio6_irqs,
1067 .main_clk = "gpio6_ick", 977 .main_clk = "gpio6_ick",
1068 .opt_clks = gpio6_opt_clks, 978 .opt_clks = gpio6_opt_clks,
1069 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), 979 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
@@ -1156,18 +1066,10 @@ static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1156}; 1066};
1157 1067
1158/* mcbsp1 */ 1068/* mcbsp1 */
1159static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1160 { .name = "common", .irq = 16 + OMAP_INTC_START, },
1161 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1162 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1163 { .irq = -1 },
1164};
1165 1069
1166static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { 1070static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1167 .name = "mcbsp1", 1071 .name = "mcbsp1",
1168 .class = &omap3xxx_mcbsp_hwmod_class, 1072 .class = &omap3xxx_mcbsp_hwmod_class,
1169 .mpu_irqs = omap3xxx_mcbsp1_irqs,
1170 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1171 .main_clk = "mcbsp1_fck", 1073 .main_clk = "mcbsp1_fck",
1172 .prcm = { 1074 .prcm = {
1173 .omap2 = { 1075 .omap2 = {
@@ -1183,12 +1085,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1183}; 1085};
1184 1086
1185/* mcbsp2 */ 1087/* mcbsp2 */
1186static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1187 { .name = "common", .irq = 17 + OMAP_INTC_START, },
1188 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1189 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1190 { .irq = -1 },
1191};
1192 1088
1193static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { 1089static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1194 .sidetone = "mcbsp2_sidetone", 1090 .sidetone = "mcbsp2_sidetone",
@@ -1197,8 +1093,6 @@ static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1197static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { 1093static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1198 .name = "mcbsp2", 1094 .name = "mcbsp2",
1199 .class = &omap3xxx_mcbsp_hwmod_class, 1095 .class = &omap3xxx_mcbsp_hwmod_class,
1200 .mpu_irqs = omap3xxx_mcbsp2_irqs,
1201 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1202 .main_clk = "mcbsp2_fck", 1096 .main_clk = "mcbsp2_fck",
1203 .prcm = { 1097 .prcm = {
1204 .omap2 = { 1098 .omap2 = {
@@ -1215,12 +1109,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1215}; 1109};
1216 1110
1217/* mcbsp3 */ 1111/* mcbsp3 */
1218static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1219 { .name = "common", .irq = 22 + OMAP_INTC_START, },
1220 { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1221 { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1222 { .irq = -1 },
1223};
1224 1112
1225static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { 1113static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1226 .sidetone = "mcbsp3_sidetone", 1114 .sidetone = "mcbsp3_sidetone",
@@ -1229,8 +1117,6 @@ static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1229static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { 1117static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1230 .name = "mcbsp3", 1118 .name = "mcbsp3",
1231 .class = &omap3xxx_mcbsp_hwmod_class, 1119 .class = &omap3xxx_mcbsp_hwmod_class,
1232 .mpu_irqs = omap3xxx_mcbsp3_irqs,
1233 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
1234 .main_clk = "mcbsp3_fck", 1120 .main_clk = "mcbsp3_fck",
1235 .prcm = { 1121 .prcm = {
1236 .omap2 = { 1122 .omap2 = {
@@ -1247,24 +1133,11 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1247}; 1133};
1248 1134
1249/* mcbsp4 */ 1135/* mcbsp4 */
1250static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1251 { .name = "common", .irq = 23 + OMAP_INTC_START, },
1252 { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1253 { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1254 { .irq = -1 },
1255};
1256 1136
1257static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1258 { .name = "rx", .dma_req = 20 },
1259 { .name = "tx", .dma_req = 19 },
1260 { .dma_req = -1 }
1261};
1262 1137
1263static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { 1138static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1264 .name = "mcbsp4", 1139 .name = "mcbsp4",
1265 .class = &omap3xxx_mcbsp_hwmod_class, 1140 .class = &omap3xxx_mcbsp_hwmod_class,
1266 .mpu_irqs = omap3xxx_mcbsp4_irqs,
1267 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
1268 .main_clk = "mcbsp4_fck", 1141 .main_clk = "mcbsp4_fck",
1269 .prcm = { 1142 .prcm = {
1270 .omap2 = { 1143 .omap2 = {
@@ -1280,24 +1153,11 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1280}; 1153};
1281 1154
1282/* mcbsp5 */ 1155/* mcbsp5 */
1283static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1284 { .name = "common", .irq = 27 + OMAP_INTC_START, },
1285 { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1286 { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1287 { .irq = -1 },
1288};
1289 1156
1290static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1291 { .name = "rx", .dma_req = 22 },
1292 { .name = "tx", .dma_req = 21 },
1293 { .dma_req = -1 }
1294};
1295 1157
1296static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { 1158static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1297 .name = "mcbsp5", 1159 .name = "mcbsp5",
1298 .class = &omap3xxx_mcbsp_hwmod_class, 1160 .class = &omap3xxx_mcbsp_hwmod_class,
1299 .mpu_irqs = omap3xxx_mcbsp5_irqs,
1300 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
1301 .main_clk = "mcbsp5_fck", 1161 .main_clk = "mcbsp5_fck",
1302 .prcm = { 1162 .prcm = {
1303 .omap2 = { 1163 .omap2 = {
@@ -1325,29 +1185,19 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1325}; 1185};
1326 1186
1327/* mcbsp2_sidetone */ 1187/* mcbsp2_sidetone */
1328static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1329 { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1330 { .irq = -1 },
1331};
1332 1188
1333static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { 1189static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1334 .name = "mcbsp2_sidetone", 1190 .name = "mcbsp2_sidetone",
1335 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1191 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1336 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
1337 .main_clk = "mcbsp2_ick", 1192 .main_clk = "mcbsp2_ick",
1338 .flags = HWMOD_NO_IDLEST, 1193 .flags = HWMOD_NO_IDLEST,
1339}; 1194};
1340 1195
1341/* mcbsp3_sidetone */ 1196/* mcbsp3_sidetone */
1342static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1343 { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1344 { .irq = -1 },
1345};
1346 1197
1347static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { 1198static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1348 .name = "mcbsp3_sidetone", 1199 .name = "mcbsp3_sidetone",
1349 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1200 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1350 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
1351 .main_clk = "mcbsp3_ick", 1201 .main_clk = "mcbsp3_ick",
1352 .flags = HWMOD_NO_IDLEST, 1202 .flags = HWMOD_NO_IDLEST,
1353}; 1203};
@@ -1394,10 +1244,6 @@ static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1394 .sensor_voltdm_name = "mpu_iva", 1244 .sensor_voltdm_name = "mpu_iva",
1395}; 1245};
1396 1246
1397static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1398 { .irq = 18 + OMAP_INTC_START, },
1399 { .irq = -1 },
1400};
1401 1247
1402static struct omap_hwmod omap34xx_sr1_hwmod = { 1248static struct omap_hwmod omap34xx_sr1_hwmod = {
1403 .name = "smartreflex_mpu_iva", 1249 .name = "smartreflex_mpu_iva",
@@ -1413,7 +1259,6 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
1413 }, 1259 },
1414 }, 1260 },
1415 .dev_attr = &sr1_dev_attr, 1261 .dev_attr = &sr1_dev_attr,
1416 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1417 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1262 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1418}; 1263};
1419 1264
@@ -1431,7 +1276,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
1431 }, 1276 },
1432 }, 1277 },
1433 .dev_attr = &sr1_dev_attr, 1278 .dev_attr = &sr1_dev_attr,
1434 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1435}; 1279};
1436 1280
1437/* SR2 */ 1281/* SR2 */
@@ -1439,10 +1283,6 @@ static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1439 .sensor_voltdm_name = "core", 1283 .sensor_voltdm_name = "core",
1440}; 1284};
1441 1285
1442static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1443 { .irq = 19 + OMAP_INTC_START, },
1444 { .irq = -1 },
1445};
1446 1286
1447static struct omap_hwmod omap34xx_sr2_hwmod = { 1287static struct omap_hwmod omap34xx_sr2_hwmod = {
1448 .name = "smartreflex_core", 1288 .name = "smartreflex_core",
@@ -1458,7 +1298,6 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
1458 }, 1298 },
1459 }, 1299 },
1460 .dev_attr = &sr2_dev_attr, 1300 .dev_attr = &sr2_dev_attr,
1461 .mpu_irqs = omap3_smartreflex_core_irqs,
1462 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1301 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1463}; 1302};
1464 1303
@@ -1476,7 +1315,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
1476 }, 1315 },
1477 }, 1316 },
1478 .dev_attr = &sr2_dev_attr, 1317 .dev_attr = &sr2_dev_attr,
1479 .mpu_irqs = omap3_smartreflex_core_irqs,
1480}; 1318};
1481 1319
1482/* 1320/*
@@ -1545,8 +1383,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1545 1383
1546static struct omap_hwmod omap34xx_mcspi1 = { 1384static struct omap_hwmod omap34xx_mcspi1 = {
1547 .name = "mcspi1", 1385 .name = "mcspi1",
1548 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1549 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1550 .main_clk = "mcspi1_fck", 1386 .main_clk = "mcspi1_fck",
1551 .prcm = { 1387 .prcm = {
1552 .omap2 = { 1388 .omap2 = {
@@ -1568,8 +1404,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1568 1404
1569static struct omap_hwmod omap34xx_mcspi2 = { 1405static struct omap_hwmod omap34xx_mcspi2 = {
1570 .name = "mcspi2", 1406 .name = "mcspi2",
1571 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1572 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1573 .main_clk = "mcspi2_fck", 1407 .main_clk = "mcspi2_fck",
1574 .prcm = { 1408 .prcm = {
1575 .omap2 = { 1409 .omap2 = {
@@ -1585,18 +1419,7 @@ static struct omap_hwmod omap34xx_mcspi2 = {
1585}; 1419};
1586 1420
1587/* mcspi3 */ 1421/* mcspi3 */
1588static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1589 { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1590 { .irq = -1 },
1591};
1592 1422
1593static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1594 { .name = "tx0", .dma_req = 15 },
1595 { .name = "rx0", .dma_req = 16 },
1596 { .name = "tx1", .dma_req = 23 },
1597 { .name = "rx1", .dma_req = 24 },
1598 { .dma_req = -1 }
1599};
1600 1423
1601static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 1424static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1602 .num_chipselect = 2, 1425 .num_chipselect = 2,
@@ -1604,8 +1427,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1604 1427
1605static struct omap_hwmod omap34xx_mcspi3 = { 1428static struct omap_hwmod omap34xx_mcspi3 = {
1606 .name = "mcspi3", 1429 .name = "mcspi3",
1607 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
1608 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
1609 .main_clk = "mcspi3_fck", 1430 .main_clk = "mcspi3_fck",
1610 .prcm = { 1431 .prcm = {
1611 .omap2 = { 1432 .omap2 = {
@@ -1621,16 +1442,7 @@ static struct omap_hwmod omap34xx_mcspi3 = {
1621}; 1442};
1622 1443
1623/* mcspi4 */ 1444/* mcspi4 */
1624static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1625 { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1626 { .irq = -1 },
1627};
1628 1445
1629static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1630 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1631 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1632 { .dma_req = -1 }
1633};
1634 1446
1635static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { 1447static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1636 .num_chipselect = 1, 1448 .num_chipselect = 1,
@@ -1638,8 +1450,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1638 1450
1639static struct omap_hwmod omap34xx_mcspi4 = { 1451static struct omap_hwmod omap34xx_mcspi4 = {
1640 .name = "mcspi4", 1452 .name = "mcspi4",
1641 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
1642 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
1643 .main_clk = "mcspi4_fck", 1453 .main_clk = "mcspi4_fck",
1644 .prcm = { 1454 .prcm = {
1645 .omap2 = { 1455 .omap2 = {
@@ -1673,16 +1483,9 @@ static struct omap_hwmod_class usbotg_class = {
1673}; 1483};
1674 1484
1675/* usb_otg_hs */ 1485/* usb_otg_hs */
1676static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1677
1678 { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1679 { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1680 { .irq = -1 },
1681};
1682 1486
1683static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { 1487static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1684 .name = "usb_otg_hs", 1488 .name = "usb_otg_hs",
1685 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
1686 .main_clk = "hsotgusb_ick", 1489 .main_clk = "hsotgusb_ick",
1687 .prcm = { 1490 .prcm = {
1688 .omap2 = { 1491 .omap2 = {
@@ -1691,7 +1494,7 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1691 .module_offs = CORE_MOD, 1494 .module_offs = CORE_MOD,
1692 .idlest_reg_id = 1, 1495 .idlest_reg_id = 1,
1693 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, 1496 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1694 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 1497 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT,
1695 }, 1498 },
1696 }, 1499 },
1697 .class = &usbotg_class, 1500 .class = &usbotg_class,
@@ -1711,10 +1514,6 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1711}; 1514};
1712 1515
1713/* usb_otg_hs */ 1516/* usb_otg_hs */
1714static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1715 { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1716 { .irq = -1 },
1717};
1718 1517
1719static struct omap_hwmod_class am35xx_usbotg_class = { 1518static struct omap_hwmod_class am35xx_usbotg_class = {
1720 .name = "am35xx_usbotg", 1519 .name = "am35xx_usbotg",
@@ -1722,7 +1521,6 @@ static struct omap_hwmod_class am35xx_usbotg_class = {
1722 1521
1723static struct omap_hwmod am35xx_usbhsotg_hwmod = { 1522static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1724 .name = "am35x_otg_hs", 1523 .name = "am35x_otg_hs",
1725 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
1726 .main_clk = "hsotgusb_fck", 1524 .main_clk = "hsotgusb_fck",
1727 .class = &am35xx_usbotg_class, 1525 .class = &am35xx_usbotg_class,
1728 .flags = HWMOD_NO_IDLEST, 1526 .flags = HWMOD_NO_IDLEST,
@@ -1747,16 +1545,7 @@ static struct omap_hwmod_class omap34xx_mmc_class = {
1747 1545
1748/* MMC/SD/SDIO1 */ 1546/* MMC/SD/SDIO1 */
1749 1547
1750static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1751 { .irq = 83 + OMAP_INTC_START, },
1752 { .irq = -1 },
1753};
1754 1548
1755static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1756 { .name = "tx", .dma_req = 61, },
1757 { .name = "rx", .dma_req = 62, },
1758 { .dma_req = -1 }
1759};
1760 1549
1761static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { 1550static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1762 { .role = "dbck", .clk = "omap_32k_fck", }, 1551 { .role = "dbck", .clk = "omap_32k_fck", },
@@ -1774,8 +1563,6 @@ static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = {
1774 1563
1775static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { 1564static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1776 .name = "mmc1", 1565 .name = "mmc1",
1777 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1778 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1779 .opt_clks = omap34xx_mmc1_opt_clks, 1566 .opt_clks = omap34xx_mmc1_opt_clks,
1780 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 1567 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1781 .main_clk = "mmchs1_fck", 1568 .main_clk = "mmchs1_fck",
@@ -1794,8 +1581,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1794 1581
1795static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { 1582static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1796 .name = "mmc1", 1583 .name = "mmc1",
1797 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1798 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1799 .opt_clks = omap34xx_mmc1_opt_clks, 1584 .opt_clks = omap34xx_mmc1_opt_clks,
1800 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 1585 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1801 .main_clk = "mmchs1_fck", 1586 .main_clk = "mmchs1_fck",
@@ -1814,16 +1599,7 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1814 1599
1815/* MMC/SD/SDIO2 */ 1600/* MMC/SD/SDIO2 */
1816 1601
1817static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1818 { .irq = 86 + OMAP_INTC_START, },
1819 { .irq = -1 },
1820};
1821 1602
1822static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1823 { .name = "tx", .dma_req = 47, },
1824 { .name = "rx", .dma_req = 48, },
1825 { .dma_req = -1 }
1826};
1827 1603
1828static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { 1604static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1829 { .role = "dbck", .clk = "omap_32k_fck", }, 1605 { .role = "dbck", .clk = "omap_32k_fck", },
@@ -1836,8 +1612,6 @@ static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = {
1836 1612
1837static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { 1613static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1838 .name = "mmc2", 1614 .name = "mmc2",
1839 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1840 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1841 .opt_clks = omap34xx_mmc2_opt_clks, 1615 .opt_clks = omap34xx_mmc2_opt_clks,
1842 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 1616 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1843 .main_clk = "mmchs2_fck", 1617 .main_clk = "mmchs2_fck",
@@ -1856,8 +1630,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1856 1630
1857static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { 1631static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1858 .name = "mmc2", 1632 .name = "mmc2",
1859 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1860 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1861 .opt_clks = omap34xx_mmc2_opt_clks, 1633 .opt_clks = omap34xx_mmc2_opt_clks,
1862 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 1634 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1863 .main_clk = "mmchs2_fck", 1635 .main_clk = "mmchs2_fck",
@@ -1875,16 +1647,7 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1875 1647
1876/* MMC/SD/SDIO3 */ 1648/* MMC/SD/SDIO3 */
1877 1649
1878static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1879 { .irq = 94 + OMAP_INTC_START, },
1880 { .irq = -1 },
1881};
1882 1650
1883static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1884 { .name = "tx", .dma_req = 77, },
1885 { .name = "rx", .dma_req = 78, },
1886 { .dma_req = -1 }
1887};
1888 1651
1889static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { 1652static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1890 { .role = "dbck", .clk = "omap_32k_fck", }, 1653 { .role = "dbck", .clk = "omap_32k_fck", },
@@ -1892,8 +1655,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1892 1655
1893static struct omap_hwmod omap3xxx_mmc3_hwmod = { 1656static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1894 .name = "mmc3", 1657 .name = "mmc3",
1895 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
1896 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
1897 .opt_clks = omap34xx_mmc3_opt_clks, 1658 .opt_clks = omap34xx_mmc3_opt_clks,
1898 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), 1659 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1899 .main_clk = "mmchs3_fck", 1660 .main_clk = "mmchs3_fck",
@@ -1931,17 +1692,11 @@ static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1931 .sysc = &omap3xxx_usb_host_hs_sysc, 1692 .sysc = &omap3xxx_usb_host_hs_sysc,
1932}; 1693};
1933 1694
1934static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1935 { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1936 { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1937 { .irq = -1 },
1938};
1939 1695
1940static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { 1696static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1941 .name = "usb_host_hs", 1697 .name = "usb_host_hs",
1942 .class = &omap3xxx_usb_host_hs_hwmod_class, 1698 .class = &omap3xxx_usb_host_hs_hwmod_class,
1943 .clkdm_name = "usbhost_clkdm", 1699 .clkdm_name = "usbhost_clkdm",
1944 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
1945 .main_clk = "usbhost_48m_fck", 1700 .main_clk = "usbhost_48m_fck",
1946 .prcm = { 1701 .prcm = {
1947 .omap2 = { 1702 .omap2 = {
@@ -2015,16 +1770,11 @@ static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
2015 .sysc = &omap3xxx_usb_tll_hs_sysc, 1770 .sysc = &omap3xxx_usb_tll_hs_sysc,
2016}; 1771};
2017 1772
2018static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
2019 { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2020 { .irq = -1 },
2021};
2022 1773
2023static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { 1774static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2024 .name = "usb_tll_hs", 1775 .name = "usb_tll_hs",
2025 .class = &omap3xxx_usb_tll_hs_hwmod_class, 1776 .class = &omap3xxx_usb_tll_hs_hwmod_class,
2026 .clkdm_name = "core_l4_clkdm", 1777 .clkdm_name = "core_l4_clkdm",
2027 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
2028 .main_clk = "usbtll_fck", 1778 .main_clk = "usbtll_fck",
2029 .prcm = { 1779 .prcm = {
2030 .omap2 = { 1780 .omap2 = {
@@ -2039,7 +1789,6 @@ static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2039 1789
2040static struct omap_hwmod omap3xxx_hdq1w_hwmod = { 1790static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2041 .name = "hdq1w", 1791 .name = "hdq1w",
2042 .mpu_irqs = omap2_hdq1w_mpu_irqs,
2043 .main_clk = "hdq_fck", 1792 .main_clk = "hdq_fck",
2044 .prcm = { 1793 .prcm = {
2045 .omap2 = { 1794 .omap2 = {
@@ -2134,16 +1883,10 @@ static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2134 .sysc = &omap3xxx_gpmc_sysc, 1883 .sysc = &omap3xxx_gpmc_sysc,
2135}; 1884};
2136 1885
2137static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2138 { .irq = 20 + OMAP_INTC_START, },
2139 { .irq = -1 }
2140};
2141
2142static struct omap_hwmod omap3xxx_gpmc_hwmod = { 1886static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2143 .name = "gpmc", 1887 .name = "gpmc",
2144 .class = &omap3xxx_gpmc_hwmod_class, 1888 .class = &omap3xxx_gpmc_hwmod_class,
2145 .clkdm_name = "core_l3_clkdm", 1889 .clkdm_name = "core_l3_clkdm",
2146 .mpu_irqs = omap3xxx_gpmc_irqs,
2147 .main_clk = "gpmc_fck", 1890 .main_clk = "gpmc_fck",
2148 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ 1891 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
2149 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS, 1892 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
@@ -2167,37 +1910,19 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2167 .user = OCP_USER_MPU | OCP_USER_SDMA, 1910 .user = OCP_USER_MPU | OCP_USER_SDMA,
2168}; 1911};
2169 1912
2170static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2171 {
2172 .pa_start = 0x68000000,
2173 .pa_end = 0x6800ffff,
2174 .flags = ADDR_TYPE_RT,
2175 },
2176 { }
2177};
2178 1913
2179/* MPU -> L3 interface */ 1914/* MPU -> L3 interface */
2180static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { 1915static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2181 .master = &omap3xxx_mpu_hwmod, 1916 .master = &omap3xxx_mpu_hwmod,
2182 .slave = &omap3xxx_l3_main_hwmod, 1917 .slave = &omap3xxx_l3_main_hwmod,
2183 .addr = omap3xxx_l3_main_addrs,
2184 .user = OCP_USER_MPU, 1918 .user = OCP_USER_MPU,
2185}; 1919};
2186 1920
2187static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
2188 {
2189 .pa_start = 0x54000000,
2190 .pa_end = 0x547fffff,
2191 .flags = ADDR_TYPE_RT,
2192 },
2193 { }
2194};
2195 1921
2196/* l3 -> debugss */ 1922/* l3 -> debugss */
2197static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = { 1923static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
2198 .master = &omap3xxx_l3_main_hwmod, 1924 .master = &omap3xxx_l3_main_hwmod,
2199 .slave = &omap3xxx_debugss_hwmod, 1925 .slave = &omap3xxx_debugss_hwmod,
2200 .addr = omap3xxx_l4_emu_addrs,
2201 .user = OCP_USER_MPU, 1926 .user = OCP_USER_MPU,
2202}; 1927};
2203 1928
@@ -2215,7 +1940,7 @@ static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2215 .omap2 = { 1940 .omap2 = {
2216 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, 1941 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2217 .flags = OMAP_FIREWALL_L3, 1942 .flags = OMAP_FIREWALL_L3,
2218 } 1943 },
2219 }, 1944 },
2220 .user = OCP_USER_MPU | OCP_USER_SDMA, 1945 .user = OCP_USER_MPU | OCP_USER_SDMA,
2221}; 1946};
@@ -2256,18 +1981,16 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2256 .master = &omap3xxx_l4_core_hwmod, 1981 .master = &omap3xxx_l4_core_hwmod,
2257 .slave = &omap3xxx_pre_es3_mmc1_hwmod, 1982 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2258 .clk = "mmchs1_ick", 1983 .clk = "mmchs1_ick",
2259 .addr = omap2430_mmc1_addr_space,
2260 .user = OCP_USER_MPU | OCP_USER_SDMA, 1984 .user = OCP_USER_MPU | OCP_USER_SDMA,
2261 .flags = OMAP_FIREWALL_L4 1985 .flags = OMAP_FIREWALL_L4,
2262}; 1986};
2263 1987
2264static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { 1988static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2265 .master = &omap3xxx_l4_core_hwmod, 1989 .master = &omap3xxx_l4_core_hwmod,
2266 .slave = &omap3xxx_es3plus_mmc1_hwmod, 1990 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2267 .clk = "mmchs1_ick", 1991 .clk = "mmchs1_ick",
2268 .addr = omap2430_mmc1_addr_space,
2269 .user = OCP_USER_MPU | OCP_USER_SDMA, 1992 .user = OCP_USER_MPU | OCP_USER_SDMA,
2270 .flags = OMAP_FIREWALL_L4 1993 .flags = OMAP_FIREWALL_L4,
2271}; 1994};
2272 1995
2273/* L4 CORE -> MMC2 interface */ 1996/* L4 CORE -> MMC2 interface */
@@ -2275,126 +1998,70 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2275 .master = &omap3xxx_l4_core_hwmod, 1998 .master = &omap3xxx_l4_core_hwmod,
2276 .slave = &omap3xxx_pre_es3_mmc2_hwmod, 1999 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2277 .clk = "mmchs2_ick", 2000 .clk = "mmchs2_ick",
2278 .addr = omap2430_mmc2_addr_space,
2279 .user = OCP_USER_MPU | OCP_USER_SDMA, 2001 .user = OCP_USER_MPU | OCP_USER_SDMA,
2280 .flags = OMAP_FIREWALL_L4 2002 .flags = OMAP_FIREWALL_L4,
2281}; 2003};
2282 2004
2283static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { 2005static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2284 .master = &omap3xxx_l4_core_hwmod, 2006 .master = &omap3xxx_l4_core_hwmod,
2285 .slave = &omap3xxx_es3plus_mmc2_hwmod, 2007 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2286 .clk = "mmchs2_ick", 2008 .clk = "mmchs2_ick",
2287 .addr = omap2430_mmc2_addr_space,
2288 .user = OCP_USER_MPU | OCP_USER_SDMA, 2009 .user = OCP_USER_MPU | OCP_USER_SDMA,
2289 .flags = OMAP_FIREWALL_L4 2010 .flags = OMAP_FIREWALL_L4,
2290}; 2011};
2291 2012
2292/* L4 CORE -> MMC3 interface */ 2013/* L4 CORE -> MMC3 interface */
2293static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2294 {
2295 .pa_start = 0x480ad000,
2296 .pa_end = 0x480ad1ff,
2297 .flags = ADDR_TYPE_RT,
2298 },
2299 { }
2300};
2301 2014
2302static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { 2015static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2303 .master = &omap3xxx_l4_core_hwmod, 2016 .master = &omap3xxx_l4_core_hwmod,
2304 .slave = &omap3xxx_mmc3_hwmod, 2017 .slave = &omap3xxx_mmc3_hwmod,
2305 .clk = "mmchs3_ick", 2018 .clk = "mmchs3_ick",
2306 .addr = omap3xxx_mmc3_addr_space,
2307 .user = OCP_USER_MPU | OCP_USER_SDMA, 2019 .user = OCP_USER_MPU | OCP_USER_SDMA,
2308 .flags = OMAP_FIREWALL_L4 2020 .flags = OMAP_FIREWALL_L4,
2309}; 2021};
2310 2022
2311/* L4 CORE -> UART1 interface */ 2023/* L4 CORE -> UART1 interface */
2312static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2313 {
2314 .pa_start = OMAP3_UART1_BASE,
2315 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2316 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2317 },
2318 { }
2319};
2320 2024
2321static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { 2025static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2322 .master = &omap3xxx_l4_core_hwmod, 2026 .master = &omap3xxx_l4_core_hwmod,
2323 .slave = &omap3xxx_uart1_hwmod, 2027 .slave = &omap3xxx_uart1_hwmod,
2324 .clk = "uart1_ick", 2028 .clk = "uart1_ick",
2325 .addr = omap3xxx_uart1_addr_space,
2326 .user = OCP_USER_MPU | OCP_USER_SDMA, 2029 .user = OCP_USER_MPU | OCP_USER_SDMA,
2327}; 2030};
2328 2031
2329/* L4 CORE -> UART2 interface */ 2032/* L4 CORE -> UART2 interface */
2330static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2331 {
2332 .pa_start = OMAP3_UART2_BASE,
2333 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2334 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2335 },
2336 { }
2337};
2338 2033
2339static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { 2034static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2340 .master = &omap3xxx_l4_core_hwmod, 2035 .master = &omap3xxx_l4_core_hwmod,
2341 .slave = &omap3xxx_uart2_hwmod, 2036 .slave = &omap3xxx_uart2_hwmod,
2342 .clk = "uart2_ick", 2037 .clk = "uart2_ick",
2343 .addr = omap3xxx_uart2_addr_space,
2344 .user = OCP_USER_MPU | OCP_USER_SDMA, 2038 .user = OCP_USER_MPU | OCP_USER_SDMA,
2345}; 2039};
2346 2040
2347/* L4 PER -> UART3 interface */ 2041/* L4 PER -> UART3 interface */
2348static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2349 {
2350 .pa_start = OMAP3_UART3_BASE,
2351 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2352 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2353 },
2354 { }
2355};
2356 2042
2357static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { 2043static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2358 .master = &omap3xxx_l4_per_hwmod, 2044 .master = &omap3xxx_l4_per_hwmod,
2359 .slave = &omap3xxx_uart3_hwmod, 2045 .slave = &omap3xxx_uart3_hwmod,
2360 .clk = "uart3_ick", 2046 .clk = "uart3_ick",
2361 .addr = omap3xxx_uart3_addr_space,
2362 .user = OCP_USER_MPU | OCP_USER_SDMA, 2047 .user = OCP_USER_MPU | OCP_USER_SDMA,
2363}; 2048};
2364 2049
2365/* L4 PER -> UART4 interface */ 2050/* L4 PER -> UART4 interface */
2366static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2367 {
2368 .pa_start = OMAP3_UART4_BASE,
2369 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2370 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2371 },
2372 { }
2373};
2374 2051
2375static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { 2052static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2376 .master = &omap3xxx_l4_per_hwmod, 2053 .master = &omap3xxx_l4_per_hwmod,
2377 .slave = &omap36xx_uart4_hwmod, 2054 .slave = &omap36xx_uart4_hwmod,
2378 .clk = "uart4_ick", 2055 .clk = "uart4_ick",
2379 .addr = omap36xx_uart4_addr_space,
2380 .user = OCP_USER_MPU | OCP_USER_SDMA, 2056 .user = OCP_USER_MPU | OCP_USER_SDMA,
2381}; 2057};
2382 2058
2383/* AM35xx: L4 CORE -> UART4 interface */ 2059/* AM35xx: L4 CORE -> UART4 interface */
2384static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2385 {
2386 .pa_start = OMAP3_UART4_AM35XX_BASE,
2387 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2388 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2389 },
2390 { }
2391};
2392 2060
2393static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { 2061static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2394 .master = &omap3xxx_l4_core_hwmod, 2062 .master = &omap3xxx_l4_core_hwmod,
2395 .slave = &am35xx_uart4_hwmod, 2063 .slave = &am35xx_uart4_hwmod,
2396 .clk = "uart4_ick", 2064 .clk = "uart4_ick",
2397 .addr = am35xx_uart4_addr_space,
2398 .user = OCP_USER_MPU | OCP_USER_SDMA, 2065 .user = OCP_USER_MPU | OCP_USER_SDMA,
2399}; 2066};
2400 2067
@@ -2403,13 +2070,12 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2403 .master = &omap3xxx_l4_core_hwmod, 2070 .master = &omap3xxx_l4_core_hwmod,
2404 .slave = &omap3xxx_i2c1_hwmod, 2071 .slave = &omap3xxx_i2c1_hwmod,
2405 .clk = "i2c1_ick", 2072 .clk = "i2c1_ick",
2406 .addr = omap2_i2c1_addr_space,
2407 .fw = { 2073 .fw = {
2408 .omap2 = { 2074 .omap2 = {
2409 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, 2075 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2410 .l4_prot_group = 7, 2076 .l4_prot_group = 7,
2411 .flags = OMAP_FIREWALL_L4, 2077 .flags = OMAP_FIREWALL_L4,
2412 } 2078 },
2413 }, 2079 },
2414 .user = OCP_USER_MPU | OCP_USER_SDMA, 2080 .user = OCP_USER_MPU | OCP_USER_SDMA,
2415}; 2081};
@@ -2419,57 +2085,38 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2419 .master = &omap3xxx_l4_core_hwmod, 2085 .master = &omap3xxx_l4_core_hwmod,
2420 .slave = &omap3xxx_i2c2_hwmod, 2086 .slave = &omap3xxx_i2c2_hwmod,
2421 .clk = "i2c2_ick", 2087 .clk = "i2c2_ick",
2422 .addr = omap2_i2c2_addr_space,
2423 .fw = { 2088 .fw = {
2424 .omap2 = { 2089 .omap2 = {
2425 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, 2090 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2426 .l4_prot_group = 7, 2091 .l4_prot_group = 7,
2427 .flags = OMAP_FIREWALL_L4, 2092 .flags = OMAP_FIREWALL_L4,
2428 } 2093 },
2429 }, 2094 },
2430 .user = OCP_USER_MPU | OCP_USER_SDMA, 2095 .user = OCP_USER_MPU | OCP_USER_SDMA,
2431}; 2096};
2432 2097
2433/* L4 CORE -> I2C3 interface */ 2098/* L4 CORE -> I2C3 interface */
2434static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2435 {
2436 .pa_start = 0x48060000,
2437 .pa_end = 0x48060000 + SZ_128 - 1,
2438 .flags = ADDR_TYPE_RT,
2439 },
2440 { }
2441};
2442 2099
2443static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { 2100static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2444 .master = &omap3xxx_l4_core_hwmod, 2101 .master = &omap3xxx_l4_core_hwmod,
2445 .slave = &omap3xxx_i2c3_hwmod, 2102 .slave = &omap3xxx_i2c3_hwmod,
2446 .clk = "i2c3_ick", 2103 .clk = "i2c3_ick",
2447 .addr = omap3xxx_i2c3_addr_space,
2448 .fw = { 2104 .fw = {
2449 .omap2 = { 2105 .omap2 = {
2450 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, 2106 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2451 .l4_prot_group = 7, 2107 .l4_prot_group = 7,
2452 .flags = OMAP_FIREWALL_L4, 2108 .flags = OMAP_FIREWALL_L4,
2453 } 2109 },
2454 }, 2110 },
2455 .user = OCP_USER_MPU | OCP_USER_SDMA, 2111 .user = OCP_USER_MPU | OCP_USER_SDMA,
2456}; 2112};
2457 2113
2458/* L4 CORE -> SR1 interface */ 2114/* L4 CORE -> SR1 interface */
2459static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2460 {
2461 .pa_start = OMAP34XX_SR1_BASE,
2462 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2463 .flags = ADDR_TYPE_RT,
2464 },
2465 { }
2466};
2467 2115
2468static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { 2116static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2469 .master = &omap3xxx_l4_core_hwmod, 2117 .master = &omap3xxx_l4_core_hwmod,
2470 .slave = &omap34xx_sr1_hwmod, 2118 .slave = &omap34xx_sr1_hwmod,
2471 .clk = "sr_l4_ick", 2119 .clk = "sr_l4_ick",
2472 .addr = omap3_sr1_addr_space,
2473 .user = OCP_USER_MPU, 2120 .user = OCP_USER_MPU,
2474}; 2121};
2475 2122
@@ -2477,25 +2124,15 @@ static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2477 .master = &omap3xxx_l4_core_hwmod, 2124 .master = &omap3xxx_l4_core_hwmod,
2478 .slave = &omap36xx_sr1_hwmod, 2125 .slave = &omap36xx_sr1_hwmod,
2479 .clk = "sr_l4_ick", 2126 .clk = "sr_l4_ick",
2480 .addr = omap3_sr1_addr_space,
2481 .user = OCP_USER_MPU, 2127 .user = OCP_USER_MPU,
2482}; 2128};
2483 2129
2484/* L4 CORE -> SR1 interface */ 2130/* L4 CORE -> SR1 interface */
2485static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2486 {
2487 .pa_start = OMAP34XX_SR2_BASE,
2488 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2489 .flags = ADDR_TYPE_RT,
2490 },
2491 { }
2492};
2493 2131
2494static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { 2132static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2495 .master = &omap3xxx_l4_core_hwmod, 2133 .master = &omap3xxx_l4_core_hwmod,
2496 .slave = &omap34xx_sr2_hwmod, 2134 .slave = &omap34xx_sr2_hwmod,
2497 .clk = "sr_l4_ick", 2135 .clk = "sr_l4_ick",
2498 .addr = omap3_sr2_addr_space,
2499 .user = OCP_USER_MPU, 2136 .user = OCP_USER_MPU,
2500}; 2137};
2501 2138
@@ -2503,43 +2140,24 @@ static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2503 .master = &omap3xxx_l4_core_hwmod, 2140 .master = &omap3xxx_l4_core_hwmod,
2504 .slave = &omap36xx_sr2_hwmod, 2141 .slave = &omap36xx_sr2_hwmod,
2505 .clk = "sr_l4_ick", 2142 .clk = "sr_l4_ick",
2506 .addr = omap3_sr2_addr_space,
2507 .user = OCP_USER_MPU, 2143 .user = OCP_USER_MPU,
2508}; 2144};
2509 2145
2510static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2511 {
2512 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2513 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2514 .flags = ADDR_TYPE_RT
2515 },
2516 { }
2517};
2518 2146
2519/* l4_core -> usbhsotg */ 2147/* l4_core -> usbhsotg */
2520static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { 2148static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2521 .master = &omap3xxx_l4_core_hwmod, 2149 .master = &omap3xxx_l4_core_hwmod,
2522 .slave = &omap3xxx_usbhsotg_hwmod, 2150 .slave = &omap3xxx_usbhsotg_hwmod,
2523 .clk = "l4_ick", 2151 .clk = "l4_ick",
2524 .addr = omap3xxx_usbhsotg_addrs,
2525 .user = OCP_USER_MPU, 2152 .user = OCP_USER_MPU,
2526}; 2153};
2527 2154
2528static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2529 {
2530 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2531 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2532 .flags = ADDR_TYPE_RT
2533 },
2534 { }
2535};
2536 2155
2537/* l4_core -> usbhsotg */ 2156/* l4_core -> usbhsotg */
2538static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { 2157static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2539 .master = &omap3xxx_l4_core_hwmod, 2158 .master = &omap3xxx_l4_core_hwmod,
2540 .slave = &am35xx_usbhsotg_hwmod, 2159 .slave = &am35xx_usbhsotg_hwmod,
2541 .clk = "hsotgusb_ick", 2160 .clk = "hsotgusb_ick",
2542 .addr = am35xx_usbhsotg_addrs,
2543 .user = OCP_USER_MPU, 2161 .user = OCP_USER_MPU,
2544}; 2162};
2545 2163
@@ -2558,165 +2176,84 @@ static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2558 .user = OCP_USER_MPU | OCP_USER_SDMA, 2176 .user = OCP_USER_MPU | OCP_USER_SDMA,
2559}; 2177};
2560 2178
2561static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2562 {
2563 .pa_start = 0x48318000,
2564 .pa_end = 0x48318000 + SZ_1K - 1,
2565 .flags = ADDR_TYPE_RT
2566 },
2567 { }
2568};
2569 2179
2570/* l4_wkup -> timer1 */ 2180/* l4_wkup -> timer1 */
2571static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { 2181static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2572 .master = &omap3xxx_l4_wkup_hwmod, 2182 .master = &omap3xxx_l4_wkup_hwmod,
2573 .slave = &omap3xxx_timer1_hwmod, 2183 .slave = &omap3xxx_timer1_hwmod,
2574 .clk = "gpt1_ick", 2184 .clk = "gpt1_ick",
2575 .addr = omap3xxx_timer1_addrs,
2576 .user = OCP_USER_MPU | OCP_USER_SDMA, 2185 .user = OCP_USER_MPU | OCP_USER_SDMA,
2577}; 2186};
2578 2187
2579static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2580 {
2581 .pa_start = 0x49032000,
2582 .pa_end = 0x49032000 + SZ_1K - 1,
2583 .flags = ADDR_TYPE_RT
2584 },
2585 { }
2586};
2587 2188
2588/* l4_per -> timer2 */ 2189/* l4_per -> timer2 */
2589static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { 2190static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2590 .master = &omap3xxx_l4_per_hwmod, 2191 .master = &omap3xxx_l4_per_hwmod,
2591 .slave = &omap3xxx_timer2_hwmod, 2192 .slave = &omap3xxx_timer2_hwmod,
2592 .clk = "gpt2_ick", 2193 .clk = "gpt2_ick",
2593 .addr = omap3xxx_timer2_addrs,
2594 .user = OCP_USER_MPU | OCP_USER_SDMA, 2194 .user = OCP_USER_MPU | OCP_USER_SDMA,
2595}; 2195};
2596 2196
2597static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2598 {
2599 .pa_start = 0x49034000,
2600 .pa_end = 0x49034000 + SZ_1K - 1,
2601 .flags = ADDR_TYPE_RT
2602 },
2603 { }
2604};
2605 2197
2606/* l4_per -> timer3 */ 2198/* l4_per -> timer3 */
2607static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { 2199static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2608 .master = &omap3xxx_l4_per_hwmod, 2200 .master = &omap3xxx_l4_per_hwmod,
2609 .slave = &omap3xxx_timer3_hwmod, 2201 .slave = &omap3xxx_timer3_hwmod,
2610 .clk = "gpt3_ick", 2202 .clk = "gpt3_ick",
2611 .addr = omap3xxx_timer3_addrs,
2612 .user = OCP_USER_MPU | OCP_USER_SDMA, 2203 .user = OCP_USER_MPU | OCP_USER_SDMA,
2613}; 2204};
2614 2205
2615static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2616 {
2617 .pa_start = 0x49036000,
2618 .pa_end = 0x49036000 + SZ_1K - 1,
2619 .flags = ADDR_TYPE_RT
2620 },
2621 { }
2622};
2623 2206
2624/* l4_per -> timer4 */ 2207/* l4_per -> timer4 */
2625static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { 2208static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2626 .master = &omap3xxx_l4_per_hwmod, 2209 .master = &omap3xxx_l4_per_hwmod,
2627 .slave = &omap3xxx_timer4_hwmod, 2210 .slave = &omap3xxx_timer4_hwmod,
2628 .clk = "gpt4_ick", 2211 .clk = "gpt4_ick",
2629 .addr = omap3xxx_timer4_addrs,
2630 .user = OCP_USER_MPU | OCP_USER_SDMA, 2212 .user = OCP_USER_MPU | OCP_USER_SDMA,
2631}; 2213};
2632 2214
2633static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2634 {
2635 .pa_start = 0x49038000,
2636 .pa_end = 0x49038000 + SZ_1K - 1,
2637 .flags = ADDR_TYPE_RT
2638 },
2639 { }
2640};
2641 2215
2642/* l4_per -> timer5 */ 2216/* l4_per -> timer5 */
2643static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { 2217static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2644 .master = &omap3xxx_l4_per_hwmod, 2218 .master = &omap3xxx_l4_per_hwmod,
2645 .slave = &omap3xxx_timer5_hwmod, 2219 .slave = &omap3xxx_timer5_hwmod,
2646 .clk = "gpt5_ick", 2220 .clk = "gpt5_ick",
2647 .addr = omap3xxx_timer5_addrs,
2648 .user = OCP_USER_MPU | OCP_USER_SDMA, 2221 .user = OCP_USER_MPU | OCP_USER_SDMA,
2649}; 2222};
2650 2223
2651static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2652 {
2653 .pa_start = 0x4903A000,
2654 .pa_end = 0x4903A000 + SZ_1K - 1,
2655 .flags = ADDR_TYPE_RT
2656 },
2657 { }
2658};
2659 2224
2660/* l4_per -> timer6 */ 2225/* l4_per -> timer6 */
2661static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { 2226static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2662 .master = &omap3xxx_l4_per_hwmod, 2227 .master = &omap3xxx_l4_per_hwmod,
2663 .slave = &omap3xxx_timer6_hwmod, 2228 .slave = &omap3xxx_timer6_hwmod,
2664 .clk = "gpt6_ick", 2229 .clk = "gpt6_ick",
2665 .addr = omap3xxx_timer6_addrs,
2666 .user = OCP_USER_MPU | OCP_USER_SDMA, 2230 .user = OCP_USER_MPU | OCP_USER_SDMA,
2667}; 2231};
2668 2232
2669static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2670 {
2671 .pa_start = 0x4903C000,
2672 .pa_end = 0x4903C000 + SZ_1K - 1,
2673 .flags = ADDR_TYPE_RT
2674 },
2675 { }
2676};
2677 2233
2678/* l4_per -> timer7 */ 2234/* l4_per -> timer7 */
2679static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { 2235static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2680 .master = &omap3xxx_l4_per_hwmod, 2236 .master = &omap3xxx_l4_per_hwmod,
2681 .slave = &omap3xxx_timer7_hwmod, 2237 .slave = &omap3xxx_timer7_hwmod,
2682 .clk = "gpt7_ick", 2238 .clk = "gpt7_ick",
2683 .addr = omap3xxx_timer7_addrs,
2684 .user = OCP_USER_MPU | OCP_USER_SDMA, 2239 .user = OCP_USER_MPU | OCP_USER_SDMA,
2685}; 2240};
2686 2241
2687static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2688 {
2689 .pa_start = 0x4903E000,
2690 .pa_end = 0x4903E000 + SZ_1K - 1,
2691 .flags = ADDR_TYPE_RT
2692 },
2693 { }
2694};
2695 2242
2696/* l4_per -> timer8 */ 2243/* l4_per -> timer8 */
2697static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { 2244static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2698 .master = &omap3xxx_l4_per_hwmod, 2245 .master = &omap3xxx_l4_per_hwmod,
2699 .slave = &omap3xxx_timer8_hwmod, 2246 .slave = &omap3xxx_timer8_hwmod,
2700 .clk = "gpt8_ick", 2247 .clk = "gpt8_ick",
2701 .addr = omap3xxx_timer8_addrs,
2702 .user = OCP_USER_MPU | OCP_USER_SDMA, 2248 .user = OCP_USER_MPU | OCP_USER_SDMA,
2703}; 2249};
2704 2250
2705static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2706 {
2707 .pa_start = 0x49040000,
2708 .pa_end = 0x49040000 + SZ_1K - 1,
2709 .flags = ADDR_TYPE_RT
2710 },
2711 { }
2712};
2713 2251
2714/* l4_per -> timer9 */ 2252/* l4_per -> timer9 */
2715static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { 2253static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2716 .master = &omap3xxx_l4_per_hwmod, 2254 .master = &omap3xxx_l4_per_hwmod,
2717 .slave = &omap3xxx_timer9_hwmod, 2255 .slave = &omap3xxx_timer9_hwmod,
2718 .clk = "gpt9_ick", 2256 .clk = "gpt9_ick",
2719 .addr = omap3xxx_timer9_addrs,
2720 .user = OCP_USER_MPU | OCP_USER_SDMA, 2257 .user = OCP_USER_MPU | OCP_USER_SDMA,
2721}; 2258};
2722 2259
@@ -2725,7 +2262,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2725 .master = &omap3xxx_l4_core_hwmod, 2262 .master = &omap3xxx_l4_core_hwmod,
2726 .slave = &omap3xxx_timer10_hwmod, 2263 .slave = &omap3xxx_timer10_hwmod,
2727 .clk = "gpt10_ick", 2264 .clk = "gpt10_ick",
2728 .addr = omap2_timer10_addrs,
2729 .user = OCP_USER_MPU | OCP_USER_SDMA, 2265 .user = OCP_USER_MPU | OCP_USER_SDMA,
2730}; 2266};
2731 2267
@@ -2734,43 +2270,24 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2734 .master = &omap3xxx_l4_core_hwmod, 2270 .master = &omap3xxx_l4_core_hwmod,
2735 .slave = &omap3xxx_timer11_hwmod, 2271 .slave = &omap3xxx_timer11_hwmod,
2736 .clk = "gpt11_ick", 2272 .clk = "gpt11_ick",
2737 .addr = omap2_timer11_addrs,
2738 .user = OCP_USER_MPU | OCP_USER_SDMA, 2273 .user = OCP_USER_MPU | OCP_USER_SDMA,
2739}; 2274};
2740 2275
2741static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2742 {
2743 .pa_start = 0x48304000,
2744 .pa_end = 0x48304000 + SZ_1K - 1,
2745 .flags = ADDR_TYPE_RT
2746 },
2747 { }
2748};
2749 2276
2750/* l4_core -> timer12 */ 2277/* l4_core -> timer12 */
2751static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { 2278static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2752 .master = &omap3xxx_l4_sec_hwmod, 2279 .master = &omap3xxx_l4_sec_hwmod,
2753 .slave = &omap3xxx_timer12_hwmod, 2280 .slave = &omap3xxx_timer12_hwmod,
2754 .clk = "gpt12_ick", 2281 .clk = "gpt12_ick",
2755 .addr = omap3xxx_timer12_addrs,
2756 .user = OCP_USER_MPU | OCP_USER_SDMA, 2282 .user = OCP_USER_MPU | OCP_USER_SDMA,
2757}; 2283};
2758 2284
2759/* l4_wkup -> wd_timer2 */ 2285/* l4_wkup -> wd_timer2 */
2760static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2761 {
2762 .pa_start = 0x48314000,
2763 .pa_end = 0x4831407f,
2764 .flags = ADDR_TYPE_RT
2765 },
2766 { }
2767};
2768 2286
2769static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { 2287static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2770 .master = &omap3xxx_l4_wkup_hwmod, 2288 .master = &omap3xxx_l4_wkup_hwmod,
2771 .slave = &omap3xxx_wd_timer2_hwmod, 2289 .slave = &omap3xxx_wd_timer2_hwmod,
2772 .clk = "wdt2_ick", 2290 .clk = "wdt2_ick",
2773 .addr = omap3xxx_wd_timer2_addrs,
2774 .user = OCP_USER_MPU | OCP_USER_SDMA, 2291 .user = OCP_USER_MPU | OCP_USER_SDMA,
2775}; 2292};
2776 2293
@@ -2779,13 +2296,12 @@ static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2779 .master = &omap3xxx_l4_core_hwmod, 2296 .master = &omap3xxx_l4_core_hwmod,
2780 .slave = &omap3430es1_dss_core_hwmod, 2297 .slave = &omap3430es1_dss_core_hwmod,
2781 .clk = "dss_ick", 2298 .clk = "dss_ick",
2782 .addr = omap2_dss_addrs,
2783 .fw = { 2299 .fw = {
2784 .omap2 = { 2300 .omap2 = {
2785 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, 2301 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2786 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2302 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2787 .flags = OMAP_FIREWALL_L4, 2303 .flags = OMAP_FIREWALL_L4,
2788 } 2304 },
2789 }, 2305 },
2790 .user = OCP_USER_MPU | OCP_USER_SDMA, 2306 .user = OCP_USER_MPU | OCP_USER_SDMA,
2791}; 2307};
@@ -2794,13 +2310,12 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2794 .master = &omap3xxx_l4_core_hwmod, 2310 .master = &omap3xxx_l4_core_hwmod,
2795 .slave = &omap3xxx_dss_core_hwmod, 2311 .slave = &omap3xxx_dss_core_hwmod,
2796 .clk = "dss_ick", 2312 .clk = "dss_ick",
2797 .addr = omap2_dss_addrs,
2798 .fw = { 2313 .fw = {
2799 .omap2 = { 2314 .omap2 = {
2800 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, 2315 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2801 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2316 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2802 .flags = OMAP_FIREWALL_L4, 2317 .flags = OMAP_FIREWALL_L4,
2803 } 2318 },
2804 }, 2319 },
2805 .user = OCP_USER_MPU | OCP_USER_SDMA, 2320 .user = OCP_USER_MPU | OCP_USER_SDMA,
2806}; 2321};
@@ -2810,38 +2325,27 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2810 .master = &omap3xxx_l4_core_hwmod, 2325 .master = &omap3xxx_l4_core_hwmod,
2811 .slave = &omap3xxx_dss_dispc_hwmod, 2326 .slave = &omap3xxx_dss_dispc_hwmod,
2812 .clk = "dss_ick", 2327 .clk = "dss_ick",
2813 .addr = omap2_dss_dispc_addrs,
2814 .fw = { 2328 .fw = {
2815 .omap2 = { 2329 .omap2 = {
2816 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, 2330 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2817 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2331 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2818 .flags = OMAP_FIREWALL_L4, 2332 .flags = OMAP_FIREWALL_L4,
2819 } 2333 },
2820 }, 2334 },
2821 .user = OCP_USER_MPU | OCP_USER_SDMA, 2335 .user = OCP_USER_MPU | OCP_USER_SDMA,
2822}; 2336};
2823 2337
2824static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2825 {
2826 .pa_start = 0x4804FC00,
2827 .pa_end = 0x4804FFFF,
2828 .flags = ADDR_TYPE_RT
2829 },
2830 { }
2831};
2832
2833/* l4_core -> dss_dsi1 */ 2338/* l4_core -> dss_dsi1 */
2834static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { 2339static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2835 .master = &omap3xxx_l4_core_hwmod, 2340 .master = &omap3xxx_l4_core_hwmod,
2836 .slave = &omap3xxx_dss_dsi1_hwmod, 2341 .slave = &omap3xxx_dss_dsi1_hwmod,
2837 .clk = "dss_ick", 2342 .clk = "dss_ick",
2838 .addr = omap3xxx_dss_dsi1_addrs,
2839 .fw = { 2343 .fw = {
2840 .omap2 = { 2344 .omap2 = {
2841 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, 2345 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2842 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2346 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2843 .flags = OMAP_FIREWALL_L4, 2347 .flags = OMAP_FIREWALL_L4,
2844 } 2348 },
2845 }, 2349 },
2846 .user = OCP_USER_MPU | OCP_USER_SDMA, 2350 .user = OCP_USER_MPU | OCP_USER_SDMA,
2847}; 2351};
@@ -2851,13 +2355,12 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2851 .master = &omap3xxx_l4_core_hwmod, 2355 .master = &omap3xxx_l4_core_hwmod,
2852 .slave = &omap3xxx_dss_rfbi_hwmod, 2356 .slave = &omap3xxx_dss_rfbi_hwmod,
2853 .clk = "dss_ick", 2357 .clk = "dss_ick",
2854 .addr = omap2_dss_rfbi_addrs,
2855 .fw = { 2358 .fw = {
2856 .omap2 = { 2359 .omap2 = {
2857 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, 2360 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2858 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , 2361 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2859 .flags = OMAP_FIREWALL_L4, 2362 .flags = OMAP_FIREWALL_L4,
2860 } 2363 },
2861 }, 2364 },
2862 .user = OCP_USER_MPU | OCP_USER_SDMA, 2365 .user = OCP_USER_MPU | OCP_USER_SDMA,
2863}; 2366};
@@ -2867,66 +2370,38 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2867 .master = &omap3xxx_l4_core_hwmod, 2370 .master = &omap3xxx_l4_core_hwmod,
2868 .slave = &omap3xxx_dss_venc_hwmod, 2371 .slave = &omap3xxx_dss_venc_hwmod,
2869 .clk = "dss_ick", 2372 .clk = "dss_ick",
2870 .addr = omap2_dss_venc_addrs,
2871 .fw = { 2373 .fw = {
2872 .omap2 = { 2374 .omap2 = {
2873 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, 2375 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2874 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2376 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2875 .flags = OMAP_FIREWALL_L4, 2377 .flags = OMAP_FIREWALL_L4,
2876 } 2378 },
2877 }, 2379 },
2878 .flags = OCPIF_SWSUP_IDLE, 2380 .flags = OCPIF_SWSUP_IDLE,
2879 .user = OCP_USER_MPU | OCP_USER_SDMA, 2381 .user = OCP_USER_MPU | OCP_USER_SDMA,
2880}; 2382};
2881 2383
2882/* l4_wkup -> gpio1 */ 2384/* l4_wkup -> gpio1 */
2883static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2884 {
2885 .pa_start = 0x48310000,
2886 .pa_end = 0x483101ff,
2887 .flags = ADDR_TYPE_RT
2888 },
2889 { }
2890};
2891 2385
2892static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { 2386static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2893 .master = &omap3xxx_l4_wkup_hwmod, 2387 .master = &omap3xxx_l4_wkup_hwmod,
2894 .slave = &omap3xxx_gpio1_hwmod, 2388 .slave = &omap3xxx_gpio1_hwmod,
2895 .addr = omap3xxx_gpio1_addrs,
2896 .user = OCP_USER_MPU | OCP_USER_SDMA, 2389 .user = OCP_USER_MPU | OCP_USER_SDMA,
2897}; 2390};
2898 2391
2899/* l4_per -> gpio2 */ 2392/* l4_per -> gpio2 */
2900static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2901 {
2902 .pa_start = 0x49050000,
2903 .pa_end = 0x490501ff,
2904 .flags = ADDR_TYPE_RT
2905 },
2906 { }
2907};
2908 2393
2909static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { 2394static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2910 .master = &omap3xxx_l4_per_hwmod, 2395 .master = &omap3xxx_l4_per_hwmod,
2911 .slave = &omap3xxx_gpio2_hwmod, 2396 .slave = &omap3xxx_gpio2_hwmod,
2912 .addr = omap3xxx_gpio2_addrs,
2913 .user = OCP_USER_MPU | OCP_USER_SDMA, 2397 .user = OCP_USER_MPU | OCP_USER_SDMA,
2914}; 2398};
2915 2399
2916/* l4_per -> gpio3 */ 2400/* l4_per -> gpio3 */
2917static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2918 {
2919 .pa_start = 0x49052000,
2920 .pa_end = 0x490521ff,
2921 .flags = ADDR_TYPE_RT
2922 },
2923 { }
2924};
2925 2401
2926static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { 2402static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2927 .master = &omap3xxx_l4_per_hwmod, 2403 .master = &omap3xxx_l4_per_hwmod,
2928 .slave = &omap3xxx_gpio3_hwmod, 2404 .slave = &omap3xxx_gpio3_hwmod,
2929 .addr = omap3xxx_gpio3_addrs,
2930 .user = OCP_USER_MPU | OCP_USER_SDMA, 2405 .user = OCP_USER_MPU | OCP_USER_SDMA,
2931}; 2406};
2932 2407
@@ -3002,53 +2477,26 @@ static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
3002}; 2477};
3003 2478
3004/* l4_per -> gpio4 */ 2479/* l4_per -> gpio4 */
3005static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
3006 {
3007 .pa_start = 0x49054000,
3008 .pa_end = 0x490541ff,
3009 .flags = ADDR_TYPE_RT
3010 },
3011 { }
3012};
3013 2480
3014static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { 2481static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3015 .master = &omap3xxx_l4_per_hwmod, 2482 .master = &omap3xxx_l4_per_hwmod,
3016 .slave = &omap3xxx_gpio4_hwmod, 2483 .slave = &omap3xxx_gpio4_hwmod,
3017 .addr = omap3xxx_gpio4_addrs,
3018 .user = OCP_USER_MPU | OCP_USER_SDMA, 2484 .user = OCP_USER_MPU | OCP_USER_SDMA,
3019}; 2485};
3020 2486
3021/* l4_per -> gpio5 */ 2487/* l4_per -> gpio5 */
3022static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3023 {
3024 .pa_start = 0x49056000,
3025 .pa_end = 0x490561ff,
3026 .flags = ADDR_TYPE_RT
3027 },
3028 { }
3029};
3030 2488
3031static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { 2489static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3032 .master = &omap3xxx_l4_per_hwmod, 2490 .master = &omap3xxx_l4_per_hwmod,
3033 .slave = &omap3xxx_gpio5_hwmod, 2491 .slave = &omap3xxx_gpio5_hwmod,
3034 .addr = omap3xxx_gpio5_addrs,
3035 .user = OCP_USER_MPU | OCP_USER_SDMA, 2492 .user = OCP_USER_MPU | OCP_USER_SDMA,
3036}; 2493};
3037 2494
3038/* l4_per -> gpio6 */ 2495/* l4_per -> gpio6 */
3039static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3040 {
3041 .pa_start = 0x49058000,
3042 .pa_end = 0x490581ff,
3043 .flags = ADDR_TYPE_RT
3044 },
3045 { }
3046};
3047 2496
3048static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { 2497static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3049 .master = &omap3xxx_l4_per_hwmod, 2498 .master = &omap3xxx_l4_per_hwmod,
3050 .slave = &omap3xxx_gpio6_hwmod, 2499 .slave = &omap3xxx_gpio6_hwmod,
3051 .addr = omap3xxx_gpio6_addrs,
3052 .user = OCP_USER_MPU | OCP_USER_SDMA, 2500 .user = OCP_USER_MPU | OCP_USER_SDMA,
3053}; 2501};
3054 2502
@@ -3064,9 +2512,9 @@ static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3064 { 2512 {
3065 .pa_start = 0x48056000, 2513 .pa_start = 0x48056000,
3066 .pa_end = 0x48056fff, 2514 .pa_end = 0x48056fff,
3067 .flags = ADDR_TYPE_RT 2515 .flags = ADDR_TYPE_RT,
3068 }, 2516 },
3069 { } 2517 { },
3070}; 2518};
3071 2519
3072/* l4_cfg -> dma_system */ 2520/* l4_cfg -> dma_system */
@@ -3078,136 +2526,66 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3078 .user = OCP_USER_MPU | OCP_USER_SDMA, 2526 .user = OCP_USER_MPU | OCP_USER_SDMA,
3079}; 2527};
3080 2528
3081static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3082 {
3083 .name = "mpu",
3084 .pa_start = 0x48074000,
3085 .pa_end = 0x480740ff,
3086 .flags = ADDR_TYPE_RT
3087 },
3088 { }
3089};
3090 2529
3091/* l4_core -> mcbsp1 */ 2530/* l4_core -> mcbsp1 */
3092static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { 2531static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3093 .master = &omap3xxx_l4_core_hwmod, 2532 .master = &omap3xxx_l4_core_hwmod,
3094 .slave = &omap3xxx_mcbsp1_hwmod, 2533 .slave = &omap3xxx_mcbsp1_hwmod,
3095 .clk = "mcbsp1_ick", 2534 .clk = "mcbsp1_ick",
3096 .addr = omap3xxx_mcbsp1_addrs,
3097 .user = OCP_USER_MPU | OCP_USER_SDMA, 2535 .user = OCP_USER_MPU | OCP_USER_SDMA,
3098}; 2536};
3099 2537
3100static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3101 {
3102 .name = "mpu",
3103 .pa_start = 0x49022000,
3104 .pa_end = 0x490220ff,
3105 .flags = ADDR_TYPE_RT
3106 },
3107 { }
3108};
3109 2538
3110/* l4_per -> mcbsp2 */ 2539/* l4_per -> mcbsp2 */
3111static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { 2540static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3112 .master = &omap3xxx_l4_per_hwmod, 2541 .master = &omap3xxx_l4_per_hwmod,
3113 .slave = &omap3xxx_mcbsp2_hwmod, 2542 .slave = &omap3xxx_mcbsp2_hwmod,
3114 .clk = "mcbsp2_ick", 2543 .clk = "mcbsp2_ick",
3115 .addr = omap3xxx_mcbsp2_addrs,
3116 .user = OCP_USER_MPU | OCP_USER_SDMA, 2544 .user = OCP_USER_MPU | OCP_USER_SDMA,
3117}; 2545};
3118 2546
3119static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3120 {
3121 .name = "mpu",
3122 .pa_start = 0x49024000,
3123 .pa_end = 0x490240ff,
3124 .flags = ADDR_TYPE_RT
3125 },
3126 { }
3127};
3128 2547
3129/* l4_per -> mcbsp3 */ 2548/* l4_per -> mcbsp3 */
3130static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { 2549static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3131 .master = &omap3xxx_l4_per_hwmod, 2550 .master = &omap3xxx_l4_per_hwmod,
3132 .slave = &omap3xxx_mcbsp3_hwmod, 2551 .slave = &omap3xxx_mcbsp3_hwmod,
3133 .clk = "mcbsp3_ick", 2552 .clk = "mcbsp3_ick",
3134 .addr = omap3xxx_mcbsp3_addrs,
3135 .user = OCP_USER_MPU | OCP_USER_SDMA, 2553 .user = OCP_USER_MPU | OCP_USER_SDMA,
3136}; 2554};
3137 2555
3138static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3139 {
3140 .name = "mpu",
3141 .pa_start = 0x49026000,
3142 .pa_end = 0x490260ff,
3143 .flags = ADDR_TYPE_RT
3144 },
3145 { }
3146};
3147 2556
3148/* l4_per -> mcbsp4 */ 2557/* l4_per -> mcbsp4 */
3149static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { 2558static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3150 .master = &omap3xxx_l4_per_hwmod, 2559 .master = &omap3xxx_l4_per_hwmod,
3151 .slave = &omap3xxx_mcbsp4_hwmod, 2560 .slave = &omap3xxx_mcbsp4_hwmod,
3152 .clk = "mcbsp4_ick", 2561 .clk = "mcbsp4_ick",
3153 .addr = omap3xxx_mcbsp4_addrs,
3154 .user = OCP_USER_MPU | OCP_USER_SDMA, 2562 .user = OCP_USER_MPU | OCP_USER_SDMA,
3155}; 2563};
3156 2564
3157static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3158 {
3159 .name = "mpu",
3160 .pa_start = 0x48096000,
3161 .pa_end = 0x480960ff,
3162 .flags = ADDR_TYPE_RT
3163 },
3164 { }
3165};
3166 2565
3167/* l4_core -> mcbsp5 */ 2566/* l4_core -> mcbsp5 */
3168static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { 2567static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3169 .master = &omap3xxx_l4_core_hwmod, 2568 .master = &omap3xxx_l4_core_hwmod,
3170 .slave = &omap3xxx_mcbsp5_hwmod, 2569 .slave = &omap3xxx_mcbsp5_hwmod,
3171 .clk = "mcbsp5_ick", 2570 .clk = "mcbsp5_ick",
3172 .addr = omap3xxx_mcbsp5_addrs,
3173 .user = OCP_USER_MPU | OCP_USER_SDMA, 2571 .user = OCP_USER_MPU | OCP_USER_SDMA,
3174}; 2572};
3175 2573
3176static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3177 {
3178 .name = "sidetone",
3179 .pa_start = 0x49028000,
3180 .pa_end = 0x490280ff,
3181 .flags = ADDR_TYPE_RT
3182 },
3183 { }
3184};
3185 2574
3186/* l4_per -> mcbsp2_sidetone */ 2575/* l4_per -> mcbsp2_sidetone */
3187static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { 2576static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3188 .master = &omap3xxx_l4_per_hwmod, 2577 .master = &omap3xxx_l4_per_hwmod,
3189 .slave = &omap3xxx_mcbsp2_sidetone_hwmod, 2578 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
3190 .clk = "mcbsp2_ick", 2579 .clk = "mcbsp2_ick",
3191 .addr = omap3xxx_mcbsp2_sidetone_addrs,
3192 .user = OCP_USER_MPU, 2580 .user = OCP_USER_MPU,
3193}; 2581};
3194 2582
3195static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3196 {
3197 .name = "sidetone",
3198 .pa_start = 0x4902A000,
3199 .pa_end = 0x4902A0ff,
3200 .flags = ADDR_TYPE_RT
3201 },
3202 { }
3203};
3204 2583
3205/* l4_per -> mcbsp3_sidetone */ 2584/* l4_per -> mcbsp3_sidetone */
3206static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { 2585static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3207 .master = &omap3xxx_l4_per_hwmod, 2586 .master = &omap3xxx_l4_per_hwmod,
3208 .slave = &omap3xxx_mcbsp3_sidetone_hwmod, 2587 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
3209 .clk = "mcbsp3_ick", 2588 .clk = "mcbsp3_ick",
3210 .addr = omap3xxx_mcbsp3_sidetone_addrs,
3211 .user = OCP_USER_MPU, 2589 .user = OCP_USER_MPU,
3212}; 2590};
3213 2591
@@ -3223,7 +2601,6 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3223 .master = &omap3xxx_l4_core_hwmod, 2601 .master = &omap3xxx_l4_core_hwmod,
3224 .slave = &omap34xx_mcspi1, 2602 .slave = &omap34xx_mcspi1,
3225 .clk = "mcspi1_ick", 2603 .clk = "mcspi1_ick",
3226 .addr = omap2_mcspi1_addr_space,
3227 .user = OCP_USER_MPU | OCP_USER_SDMA, 2604 .user = OCP_USER_MPU | OCP_USER_SDMA,
3228}; 2605};
3229 2606
@@ -3232,7 +2609,6 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3232 .master = &omap3xxx_l4_core_hwmod, 2609 .master = &omap3xxx_l4_core_hwmod,
3233 .slave = &omap34xx_mcspi2, 2610 .slave = &omap34xx_mcspi2,
3234 .clk = "mcspi2_ick", 2611 .clk = "mcspi2_ick",
3235 .addr = omap2_mcspi2_addr_space,
3236 .user = OCP_USER_MPU | OCP_USER_SDMA, 2612 .user = OCP_USER_MPU | OCP_USER_SDMA,
3237}; 2613};
3238 2614
@@ -3241,25 +2617,15 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3241 .master = &omap3xxx_l4_core_hwmod, 2617 .master = &omap3xxx_l4_core_hwmod,
3242 .slave = &omap34xx_mcspi3, 2618 .slave = &omap34xx_mcspi3,
3243 .clk = "mcspi3_ick", 2619 .clk = "mcspi3_ick",
3244 .addr = omap2430_mcspi3_addr_space,
3245 .user = OCP_USER_MPU | OCP_USER_SDMA, 2620 .user = OCP_USER_MPU | OCP_USER_SDMA,
3246}; 2621};
3247 2622
3248/* l4 core -> mcspi4 interface */ 2623/* l4 core -> mcspi4 interface */
3249static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3250 {
3251 .pa_start = 0x480ba000,
3252 .pa_end = 0x480ba0ff,
3253 .flags = ADDR_TYPE_RT,
3254 },
3255 { }
3256};
3257 2624
3258static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { 2625static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3259 .master = &omap3xxx_l4_core_hwmod, 2626 .master = &omap3xxx_l4_core_hwmod,
3260 .slave = &omap34xx_mcspi4, 2627 .slave = &omap34xx_mcspi4,
3261 .clk = "mcspi4_ick", 2628 .clk = "mcspi4_ick",
3262 .addr = omap34xx_mcspi4_addr_space,
3263 .user = OCP_USER_MPU | OCP_USER_SDMA, 2629 .user = OCP_USER_MPU | OCP_USER_SDMA,
3264}; 2630};
3265 2631
@@ -3270,49 +2636,19 @@ static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3270 .user = OCP_USER_MPU, 2636 .user = OCP_USER_MPU,
3271}; 2637};
3272 2638
3273static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3274 {
3275 .name = "uhh",
3276 .pa_start = 0x48064000,
3277 .pa_end = 0x480643ff,
3278 .flags = ADDR_TYPE_RT
3279 },
3280 {
3281 .name = "ohci",
3282 .pa_start = 0x48064400,
3283 .pa_end = 0x480647ff,
3284 },
3285 {
3286 .name = "ehci",
3287 .pa_start = 0x48064800,
3288 .pa_end = 0x48064cff,
3289 },
3290 {}
3291};
3292 2639
3293static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { 2640static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3294 .master = &omap3xxx_l4_core_hwmod, 2641 .master = &omap3xxx_l4_core_hwmod,
3295 .slave = &omap3xxx_usb_host_hs_hwmod, 2642 .slave = &omap3xxx_usb_host_hs_hwmod,
3296 .clk = "usbhost_ick", 2643 .clk = "usbhost_ick",
3297 .addr = omap3xxx_usb_host_hs_addrs,
3298 .user = OCP_USER_MPU | OCP_USER_SDMA, 2644 .user = OCP_USER_MPU | OCP_USER_SDMA,
3299}; 2645};
3300 2646
3301static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3302 {
3303 .name = "tll",
3304 .pa_start = 0x48062000,
3305 .pa_end = 0x48062fff,
3306 .flags = ADDR_TYPE_RT
3307 },
3308 {}
3309};
3310 2647
3311static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { 2648static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3312 .master = &omap3xxx_l4_core_hwmod, 2649 .master = &omap3xxx_l4_core_hwmod,
3313 .slave = &omap3xxx_usb_tll_hs_hwmod, 2650 .slave = &omap3xxx_usb_tll_hs_hwmod,
3314 .clk = "usbtll_ick", 2651 .clk = "usbtll_ick",
3315 .addr = omap3xxx_usb_tll_hs_addrs,
3316 .user = OCP_USER_MPU | OCP_USER_SDMA, 2652 .user = OCP_USER_MPU | OCP_USER_SDMA,
3317}; 2653};
3318 2654
@@ -3321,35 +2657,17 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3321 .master = &omap3xxx_l4_core_hwmod, 2657 .master = &omap3xxx_l4_core_hwmod,
3322 .slave = &omap3xxx_hdq1w_hwmod, 2658 .slave = &omap3xxx_hdq1w_hwmod,
3323 .clk = "hdq_ick", 2659 .clk = "hdq_ick",
3324 .addr = omap2_hdq1w_addr_space,
3325 .user = OCP_USER_MPU | OCP_USER_SDMA, 2660 .user = OCP_USER_MPU | OCP_USER_SDMA,
3326 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, 2661 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3327}; 2662};
3328 2663
3329/* l4_wkup -> 32ksync_counter */ 2664/* l4_wkup -> 32ksync_counter */
3330static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3331 {
3332 .pa_start = 0x48320000,
3333 .pa_end = 0x4832001f,
3334 .flags = ADDR_TYPE_RT
3335 },
3336 { }
3337};
3338 2665
3339static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3340 {
3341 .pa_start = 0x6e000000,
3342 .pa_end = 0x6e000fff,
3343 .flags = ADDR_TYPE_RT
3344 },
3345 { }
3346};
3347 2666
3348static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { 2667static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3349 .master = &omap3xxx_l4_wkup_hwmod, 2668 .master = &omap3xxx_l4_wkup_hwmod,
3350 .slave = &omap3xxx_counter_32k_hwmod, 2669 .slave = &omap3xxx_counter_32k_hwmod,
3351 .clk = "omap_32ksync_ick", 2670 .clk = "omap_32ksync_ick",
3352 .addr = omap3xxx_counter_32k_addrs,
3353 .user = OCP_USER_MPU | OCP_USER_SDMA, 2671 .user = OCP_USER_MPU | OCP_USER_SDMA,
3354}; 2672};
3355 2673
@@ -3434,7 +2752,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3434 .master = &omap3xxx_l3_main_hwmod, 2752 .master = &omap3xxx_l3_main_hwmod,
3435 .slave = &omap3xxx_gpmc_hwmod, 2753 .slave = &omap3xxx_gpmc_hwmod,
3436 .clk = "core_l3_ick", 2754 .clk = "core_l3_ick",
3437 .addr = omap3xxx_gpmc_addrs,
3438 .user = OCP_USER_MPU | OCP_USER_SDMA, 2755 .user = OCP_USER_MPU | OCP_USER_SDMA,
3439}; 2756};
3440 2757
@@ -3459,20 +2776,10 @@ static struct omap_hwmod_class omap3xxx_sham_class = {
3459 .sysc = &omap3_sham_sysc, 2776 .sysc = &omap3_sham_sysc,
3460}; 2777};
3461 2778
3462static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
3463 { .irq = 49 + OMAP_INTC_START, },
3464 { .irq = -1 }
3465};
3466 2779
3467static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
3468 { .name = "rx", .dma_req = 69, },
3469 { .dma_req = -1 }
3470};
3471 2780
3472static struct omap_hwmod omap3xxx_sham_hwmod = { 2781static struct omap_hwmod omap3xxx_sham_hwmod = {
3473 .name = "sham", 2782 .name = "sham",
3474 .mpu_irqs = omap3_sham_mpu_irqs,
3475 .sdma_reqs = omap3_sham_sdma_reqs,
3476 .main_clk = "sha12_ick", 2783 .main_clk = "sha12_ick",
3477 .prcm = { 2784 .prcm = {
3478 .omap2 = { 2785 .omap2 = {
@@ -3486,20 +2793,11 @@ static struct omap_hwmod omap3xxx_sham_hwmod = {
3486 .class = &omap3xxx_sham_class, 2793 .class = &omap3xxx_sham_class,
3487}; 2794};
3488 2795
3489static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
3490 {
3491 .pa_start = 0x480c3000,
3492 .pa_end = 0x480c3000 + 0x64 - 1,
3493 .flags = ADDR_TYPE_RT
3494 },
3495 { }
3496};
3497 2796
3498static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = { 2797static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
3499 .master = &omap3xxx_l4_core_hwmod, 2798 .master = &omap3xxx_l4_core_hwmod,
3500 .slave = &omap3xxx_sham_hwmod, 2799 .slave = &omap3xxx_sham_hwmod,
3501 .clk = "sha12_ick", 2800 .clk = "sha12_ick",
3502 .addr = omap3xxx_sham_addrs,
3503 .user = OCP_USER_MPU | OCP_USER_SDMA, 2801 .user = OCP_USER_MPU | OCP_USER_SDMA,
3504}; 2802};
3505 2803
@@ -3525,15 +2823,9 @@ static struct omap_hwmod_class omap3xxx_aes_class = {
3525 .sysc = &omap3_aes_sysc, 2823 .sysc = &omap3_aes_sysc,
3526}; 2824};
3527 2825
3528static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
3529 { .name = "tx", .dma_req = 65, },
3530 { .name = "rx", .dma_req = 66, },
3531 { .dma_req = -1 }
3532};
3533 2826
3534static struct omap_hwmod omap3xxx_aes_hwmod = { 2827static struct omap_hwmod omap3xxx_aes_hwmod = {
3535 .name = "aes", 2828 .name = "aes",
3536 .sdma_reqs = omap3_aes_sdma_reqs,
3537 .main_clk = "aes2_ick", 2829 .main_clk = "aes2_ick",
3538 .prcm = { 2830 .prcm = {
3539 .omap2 = { 2831 .omap2 = {
@@ -3547,20 +2839,11 @@ static struct omap_hwmod omap3xxx_aes_hwmod = {
3547 .class = &omap3xxx_aes_class, 2839 .class = &omap3xxx_aes_class,
3548}; 2840};
3549 2841
3550static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = {
3551 {
3552 .pa_start = 0x480c5000,
3553 .pa_end = 0x480c5000 + 0x50 - 1,
3554 .flags = ADDR_TYPE_RT
3555 },
3556 { }
3557};
3558 2842
3559static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = { 2843static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
3560 .master = &omap3xxx_l4_core_hwmod, 2844 .master = &omap3xxx_l4_core_hwmod,
3561 .slave = &omap3xxx_aes_hwmod, 2845 .slave = &omap3xxx_aes_hwmod,
3562 .clk = "aes2_ick", 2846 .clk = "aes2_ick",
3563 .addr = omap3xxx_aes_addrs,
3564 .user = OCP_USER_MPU | OCP_USER_SDMA, 2847 .user = OCP_USER_MPU | OCP_USER_SDMA,
3565}; 2848};
3566 2849
@@ -3661,28 +2944,28 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3661/* GP-only hwmod links */ 2944/* GP-only hwmod links */
3662static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = { 2945static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
3663 &omap3xxx_l4_sec__timer12, 2946 &omap3xxx_l4_sec__timer12,
3664 NULL 2947 NULL,
3665}; 2948};
3666 2949
3667static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = { 2950static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
3668 &omap3xxx_l4_sec__timer12, 2951 &omap3xxx_l4_sec__timer12,
3669 NULL 2952 NULL,
3670}; 2953};
3671 2954
3672static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = { 2955static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
3673 &omap3xxx_l4_sec__timer12, 2956 &omap3xxx_l4_sec__timer12,
3674 NULL 2957 NULL,
3675}; 2958};
3676 2959
3677/* crypto hwmod links */ 2960/* crypto hwmod links */
3678static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = { 2961static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
3679 &omap3xxx_l4_core__sham, 2962 &omap3xxx_l4_core__sham,
3680 NULL 2963 NULL,
3681}; 2964};
3682 2965
3683static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = { 2966static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
3684 &omap3xxx_l4_core__aes, 2967 &omap3xxx_l4_core__aes,
3685 NULL 2968 NULL,
3686}; 2969};
3687 2970
3688static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = { 2971static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
@@ -3710,14 +2993,14 @@ static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
3710 2993
3711static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = { 2994static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
3712 /* &omap3xxx_l4_core__aes, */ 2995 /* &omap3xxx_l4_core__aes, */
3713 NULL 2996 NULL,
3714}; 2997};
3715 2998
3716/* 3430ES1-only hwmod links */ 2999/* 3430ES1-only hwmod links */
3717static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { 3000static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3718 &omap3430es1_dss__l3, 3001 &omap3430es1_dss__l3,
3719 &omap3430es1_l4_core__dss, 3002 &omap3430es1_l4_core__dss,
3720 NULL 3003 NULL,
3721}; 3004};
3722 3005
3723/* 3430ES2+-only hwmod links */ 3006/* 3430ES2+-only hwmod links */
@@ -3729,21 +3012,21 @@ static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3729 &omap3xxx_usb_host_hs__l3_main_2, 3012 &omap3xxx_usb_host_hs__l3_main_2,
3730 &omap3xxx_l4_core__usb_host_hs, 3013 &omap3xxx_l4_core__usb_host_hs,
3731 &omap3xxx_l4_core__usb_tll_hs, 3014 &omap3xxx_l4_core__usb_tll_hs,
3732 NULL 3015 NULL,
3733}; 3016};
3734 3017
3735/* <= 3430ES3-only hwmod links */ 3018/* <= 3430ES3-only hwmod links */
3736static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { 3019static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3737 &omap3xxx_l4_core__pre_es3_mmc1, 3020 &omap3xxx_l4_core__pre_es3_mmc1,
3738 &omap3xxx_l4_core__pre_es3_mmc2, 3021 &omap3xxx_l4_core__pre_es3_mmc2,
3739 NULL 3022 NULL,
3740}; 3023};
3741 3024
3742/* 3430ES3+-only hwmod links */ 3025/* 3430ES3+-only hwmod links */
3743static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { 3026static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3744 &omap3xxx_l4_core__es3plus_mmc1, 3027 &omap3xxx_l4_core__es3plus_mmc1,
3745 &omap3xxx_l4_core__es3plus_mmc2, 3028 &omap3xxx_l4_core__es3plus_mmc2,
3746 NULL 3029 NULL,
3747}; 3030};
3748 3031
3749/* 34xx-only hwmod links (all ES revisions) */ 3032/* 34xx-only hwmod links (all ES revisions) */
@@ -3757,7 +3040,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3757 &omap3xxx_l4_core__mmu_isp, 3040 &omap3xxx_l4_core__mmu_isp,
3758 &omap3xxx_l3_main__mmu_iva, 3041 &omap3xxx_l3_main__mmu_iva,
3759 &omap3xxx_l4_core__ssi, 3042 &omap3xxx_l4_core__ssi,
3760 NULL 3043 NULL,
3761}; 3044};
3762 3045
3763/* 36xx-only hwmod links (all ES revisions) */ 3046/* 36xx-only hwmod links (all ES revisions) */
@@ -3781,7 +3064,7 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3781 &omap3xxx_l4_core__mmu_isp, 3064 &omap3xxx_l4_core__mmu_isp,
3782 &omap3xxx_l3_main__mmu_iva, 3065 &omap3xxx_l3_main__mmu_iva,
3783 &omap3xxx_l4_core__ssi, 3066 &omap3xxx_l4_core__ssi,
3784 NULL 3067 NULL,
3785}; 3068};
3786 3069
3787static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { 3070static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
@@ -3800,7 +3083,7 @@ static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3800 &am35xx_l4_core__mdio, 3083 &am35xx_l4_core__mdio,
3801 &am35xx_emac__l3, 3084 &am35xx_emac__l3,
3802 &am35xx_l4_core__emac, 3085 &am35xx_l4_core__emac,
3803 NULL 3086 NULL,
3804}; 3087};
3805 3088
3806static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { 3089static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
@@ -3808,7 +3091,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3808 &omap3xxx_l4_core__dss_dsi1, 3091 &omap3xxx_l4_core__dss_dsi1,
3809 &omap3xxx_l4_core__dss_rfbi, 3092 &omap3xxx_l4_core__dss_rfbi,
3810 &omap3xxx_l4_core__dss_venc, 3093 &omap3xxx_l4_core__dss_venc,
3811 NULL 3094 NULL,
3812}; 3095};
3813 3096
3814/** 3097/**
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index 61f2f301d739..afbce1f6f641 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -442,6 +442,31 @@ static struct omap_hwmod am43xx_adc_tsc_hwmod = {
442 }, 442 },
443}; 443};
444 444
445static struct omap_hwmod_class_sysconfig am43xx_des_sysc = {
446 .rev_offs = 0x30,
447 .sysc_offs = 0x34,
448 .syss_offs = 0x38,
449 .sysc_flags = SYSS_HAS_RESET_STATUS,
450};
451
452static struct omap_hwmod_class am43xx_des_hwmod_class = {
453 .name = "des",
454 .sysc = &am43xx_des_sysc,
455};
456
457static struct omap_hwmod am43xx_des_hwmod = {
458 .name = "des",
459 .class = &am43xx_des_hwmod_class,
460 .clkdm_name = "l3_clkdm",
461 .main_clk = "l3_gclk",
462 .prcm = {
463 .omap4 = {
464 .clkctrl_offs = AM43XX_CM_PER_DES_CLKCTRL_OFFSET,
465 .modulemode = MODULEMODE_SWCTRL,
466 },
467 },
468};
469
445/* dss */ 470/* dss */
446 471
447static struct omap_hwmod am43xx_dss_core_hwmod = { 472static struct omap_hwmod am43xx_dss_core_hwmod = {
@@ -870,6 +895,13 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe1 = {
870 .user = OCP_USER_MPU | OCP_USER_SDMA, 895 .user = OCP_USER_MPU | OCP_USER_SDMA,
871}; 896};
872 897
898static struct omap_hwmod_ocp_if am43xx_l3_main__des = {
899 .master = &am33xx_l3_main_hwmod,
900 .slave = &am43xx_des_hwmod,
901 .clk = "l3_gclk",
902 .user = OCP_USER_MPU,
903};
904
873static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { 905static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
874 &am33xx_l4_wkup__synctimer, 906 &am33xx_l4_wkup__synctimer,
875 &am43xx_l4_ls__timer8, 907 &am43xx_l4_ls__timer8,
@@ -917,6 +949,7 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
917 &am33xx_l4_per__i2c2, 949 &am33xx_l4_per__i2c2,
918 &am33xx_l4_per__i2c3, 950 &am33xx_l4_per__i2c3,
919 &am33xx_l4_per__mailbox, 951 &am33xx_l4_per__mailbox,
952 &am33xx_l4_per__rng,
920 &am33xx_l4_ls__mcasp0, 953 &am33xx_l4_ls__mcasp0,
921 &am33xx_l4_ls__mcasp1, 954 &am33xx_l4_ls__mcasp1,
922 &am33xx_l4_ls__mmc0, 955 &am33xx_l4_ls__mmc0,
@@ -950,6 +983,7 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
950 &am33xx_cpgmac0__mdio, 983 &am33xx_cpgmac0__mdio,
951 &am33xx_l3_main__sha0, 984 &am33xx_l3_main__sha0,
952 &am33xx_l3_main__aes0, 985 &am33xx_l3_main__aes0,
986 &am43xx_l3_main__des,
953 &am43xx_l4_ls__ocp2scp0, 987 &am43xx_l4_ls__ocp2scp0,
954 &am43xx_l4_ls__ocp2scp1, 988 &am43xx_l4_ls__ocp2scp1,
955 &am43xx_l3_s__usbotgss0, 989 &am43xx_l3_s__usbotgss0,
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 1ab7096af8e2..d0585293a381 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -690,6 +690,78 @@ static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
690 .parent_hwmod = &dra7xx_dss_hwmod, 690 .parent_hwmod = &dra7xx_dss_hwmod,
691}; 691};
692 692
693/* AES (the 'P' (public) device) */
694static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
695 .rev_offs = 0x0080,
696 .sysc_offs = 0x0084,
697 .syss_offs = 0x0088,
698 .sysc_flags = SYSS_HAS_RESET_STATUS,
699};
700
701static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
702 .name = "aes",
703 .sysc = &dra7xx_aes_sysc,
704 .rev = 2,
705};
706
707/* AES1 */
708static struct omap_hwmod dra7xx_aes1_hwmod = {
709 .name = "aes1",
710 .class = &dra7xx_aes_hwmod_class,
711 .clkdm_name = "l4sec_clkdm",
712 .main_clk = "l3_iclk_div",
713 .prcm = {
714 .omap4 = {
715 .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
716 .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
717 .modulemode = MODULEMODE_HWCTRL,
718 },
719 },
720};
721
722/* AES2 */
723static struct omap_hwmod dra7xx_aes2_hwmod = {
724 .name = "aes2",
725 .class = &dra7xx_aes_hwmod_class,
726 .clkdm_name = "l4sec_clkdm",
727 .main_clk = "l3_iclk_div",
728 .prcm = {
729 .omap4 = {
730 .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
731 .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
732 .modulemode = MODULEMODE_HWCTRL,
733 },
734 },
735};
736
737/* sha0 HIB2 (the 'P' (public) device) */
738static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
739 .rev_offs = 0x100,
740 .sysc_offs = 0x110,
741 .syss_offs = 0x114,
742 .sysc_flags = SYSS_HAS_RESET_STATUS,
743};
744
745static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
746 .name = "sham",
747 .sysc = &dra7xx_sha0_sysc,
748 .rev = 2,
749};
750
751struct omap_hwmod dra7xx_sha0_hwmod = {
752 .name = "sham",
753 .class = &dra7xx_sha0_hwmod_class,
754 .clkdm_name = "l4sec_clkdm",
755 .main_clk = "l3_iclk_div",
756 .prcm = {
757 .omap4 = {
758 .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
759 .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
760 .modulemode = MODULEMODE_HWCTRL,
761 },
762 },
763};
764
693/* 765/*
694 * 'elm' class 766 * 'elm' class
695 * 767 *
@@ -2541,6 +2613,62 @@ static struct omap_hwmod dra7xx_uart10_hwmod = {
2541 }, 2613 },
2542}; 2614};
2543 2615
2616/* DES (the 'P' (public) device) */
2617static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
2618 .rev_offs = 0x0030,
2619 .sysc_offs = 0x0034,
2620 .syss_offs = 0x0038,
2621 .sysc_flags = SYSS_HAS_RESET_STATUS,
2622};
2623
2624static struct omap_hwmod_class dra7xx_des_hwmod_class = {
2625 .name = "des",
2626 .sysc = &dra7xx_des_sysc,
2627};
2628
2629/* DES */
2630static struct omap_hwmod dra7xx_des_hwmod = {
2631 .name = "des",
2632 .class = &dra7xx_des_hwmod_class,
2633 .clkdm_name = "l4sec_clkdm",
2634 .main_clk = "l3_iclk_div",
2635 .prcm = {
2636 .omap4 = {
2637 .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
2638 .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
2639 .modulemode = MODULEMODE_HWCTRL,
2640 },
2641 },
2642};
2643
2644/* rng */
2645static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
2646 .rev_offs = 0x1fe0,
2647 .sysc_offs = 0x1fe4,
2648 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
2649 .idlemodes = SIDLE_FORCE | SIDLE_NO,
2650 .sysc_fields = &omap_hwmod_sysc_type1,
2651};
2652
2653static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
2654 .name = "rng",
2655 .sysc = &dra7xx_rng_sysc,
2656};
2657
2658static struct omap_hwmod dra7xx_rng_hwmod = {
2659 .name = "rng",
2660 .class = &dra7xx_rng_hwmod_class,
2661 .flags = HWMOD_SWSUP_SIDLE,
2662 .clkdm_name = "l4sec_clkdm",
2663 .prcm = {
2664 .omap4 = {
2665 .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
2666 .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
2667 .modulemode = MODULEMODE_HWCTRL,
2668 },
2669 },
2670};
2671
2544/* 2672/*
2545 * 'usb_otg_ss' class 2673 * 'usb_otg_ss' class
2546 * 2674 *
@@ -2929,6 +3057,30 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2929 .user = OCP_USER_MPU | OCP_USER_SDMA, 3057 .user = OCP_USER_MPU | OCP_USER_SDMA,
2930}; 3058};
2931 3059
3060/* l3_main_1 -> aes1 */
3061static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
3062 .master = &dra7xx_l3_main_1_hwmod,
3063 .slave = &dra7xx_aes1_hwmod,
3064 .clk = "l3_iclk_div",
3065 .user = OCP_USER_MPU | OCP_USER_SDMA,
3066};
3067
3068/* l3_main_1 -> aes2 */
3069static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
3070 .master = &dra7xx_l3_main_1_hwmod,
3071 .slave = &dra7xx_aes2_hwmod,
3072 .clk = "l3_iclk_div",
3073 .user = OCP_USER_MPU | OCP_USER_SDMA,
3074};
3075
3076/* l3_main_1 -> sha0 */
3077static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
3078 .master = &dra7xx_l3_main_1_hwmod,
3079 .slave = &dra7xx_sha0_hwmod,
3080 .clk = "l3_iclk_div",
3081 .user = OCP_USER_MPU | OCP_USER_SDMA,
3082};
3083
2932/* l4_per2 -> mcasp1 */ 3084/* l4_per2 -> mcasp1 */
2933static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = { 3085static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
2934 .master = &dra7xx_l4_per2_hwmod, 3086 .master = &dra7xx_l4_per2_hwmod,
@@ -3642,6 +3794,14 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3642 .user = OCP_USER_MPU | OCP_USER_SDMA, 3794 .user = OCP_USER_MPU | OCP_USER_SDMA,
3643}; 3795};
3644 3796
3797/* l4_per1 -> des */
3798static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
3799 .master = &dra7xx_l4_per1_hwmod,
3800 .slave = &dra7xx_des_hwmod,
3801 .clk = "l3_iclk_div",
3802 .user = OCP_USER_MPU | OCP_USER_SDMA,
3803};
3804
3645/* l4_per2 -> uart8 */ 3805/* l4_per2 -> uart8 */
3646static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = { 3806static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3647 .master = &dra7xx_l4_per2_hwmod, 3807 .master = &dra7xx_l4_per2_hwmod,
@@ -3666,6 +3826,13 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3666 .user = OCP_USER_MPU | OCP_USER_SDMA, 3826 .user = OCP_USER_MPU | OCP_USER_SDMA,
3667}; 3827};
3668 3828
3829/* l4_per1 -> rng */
3830static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
3831 .master = &dra7xx_l4_per1_hwmod,
3832 .slave = &dra7xx_rng_hwmod,
3833 .user = OCP_USER_MPU,
3834};
3835
3669/* l4_per3 -> usb_otg_ss1 */ 3836/* l4_per3 -> usb_otg_ss1 */
3670static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = { 3837static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3671 .master = &dra7xx_l4_per3_hwmod, 3838 .master = &dra7xx_l4_per3_hwmod,
@@ -3800,6 +3967,9 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3800 &dra7xx_l3_main_1__dss, 3967 &dra7xx_l3_main_1__dss,
3801 &dra7xx_l3_main_1__dispc, 3968 &dra7xx_l3_main_1__dispc,
3802 &dra7xx_l3_main_1__hdmi, 3969 &dra7xx_l3_main_1__hdmi,
3970 &dra7xx_l3_main_1__aes1,
3971 &dra7xx_l3_main_1__aes2,
3972 &dra7xx_l3_main_1__sha0,
3803 &dra7xx_l4_per1__elm, 3973 &dra7xx_l4_per1__elm,
3804 &dra7xx_l4_wkup__gpio1, 3974 &dra7xx_l4_wkup__gpio1,
3805 &dra7xx_l4_per1__gpio2, 3975 &dra7xx_l4_per1__gpio2,
@@ -3845,7 +4015,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3845 &dra7xx_l3_main_1__pciess2, 4015 &dra7xx_l3_main_1__pciess2,
3846 &dra7xx_l4_cfg__pciess2, 4016 &dra7xx_l4_cfg__pciess2,
3847 &dra7xx_l3_main_1__qspi, 4017 &dra7xx_l3_main_1__qspi,
3848 &dra7xx_l4_per3__rtcss,
3849 &dra7xx_l4_cfg__sata, 4018 &dra7xx_l4_cfg__sata,
3850 &dra7xx_l4_cfg__smartreflex_core, 4019 &dra7xx_l4_cfg__smartreflex_core,
3851 &dra7xx_l4_cfg__smartreflex_mpu, 4020 &dra7xx_l4_cfg__smartreflex_mpu,
@@ -3875,6 +4044,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3875 &dra7xx_l4_per2__uart8, 4044 &dra7xx_l4_per2__uart8,
3876 &dra7xx_l4_per2__uart9, 4045 &dra7xx_l4_per2__uart9,
3877 &dra7xx_l4_wkup__uart10, 4046 &dra7xx_l4_wkup__uart10,
4047 &dra7xx_l4_per1__des,
3878 &dra7xx_l4_per3__usb_otg_ss1, 4048 &dra7xx_l4_per3__usb_otg_ss1,
3879 &dra7xx_l4_per3__usb_otg_ss2, 4049 &dra7xx_l4_per3__usb_otg_ss2,
3880 &dra7xx_l4_per3__usb_otg_ss3, 4050 &dra7xx_l4_per3__usb_otg_ss3,
@@ -3892,6 +4062,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3892/* GP-only hwmod links */ 4062/* GP-only hwmod links */
3893static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = { 4063static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
3894 &dra7xx_l4_wkup__timer12, 4064 &dra7xx_l4_wkup__timer12,
4065 &dra7xx_l4_per1__rng,
3895 NULL, 4066 NULL,
3896}; 4067};
3897 4068
@@ -3905,6 +4076,11 @@ static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3905 NULL, 4076 NULL,
3906}; 4077};
3907 4078
4079static struct omap_hwmod_ocp_if *dra74x_dra72x_hwmod_ocp_ifs[] __initdata = {
4080 &dra7xx_l4_per3__rtcss,
4081 NULL,
4082};
4083
3908int __init dra7xx_hwmod_init(void) 4084int __init dra7xx_hwmod_init(void)
3909{ 4085{
3910 int ret; 4086 int ret;
@@ -3920,5 +4096,9 @@ int __init dra7xx_hwmod_init(void)
3920 if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP) 4096 if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
3921 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs); 4097 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
3922 4098
4099 /* now for the IPs *NOT* in dra71 */
4100 if (!ret && !of_machine_is_compatible("ti,dra718"))
4101 ret = omap_hwmod_register_links(dra74x_dra72x_hwmod_ocp_ifs);
4102
3923 return ret; 4103 return ret;
3924} 4104}
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 11ed5a17dd77..cdfbb44ceb0c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -19,22 +19,7 @@
19#include "display.h" 19#include "display.h"
20 20
21/* Common address space across OMAP2xxx/3xxx */ 21/* Common address space across OMAP2xxx/3xxx */
22extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[];
23extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[];
24extern struct omap_hwmod_addr_space omap2_dss_addrs[];
25extern struct omap_hwmod_addr_space omap2_dss_dispc_addrs[];
26extern struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[];
27extern struct omap_hwmod_addr_space omap2_dss_venc_addrs[];
28extern struct omap_hwmod_addr_space omap2_timer10_addrs[];
29extern struct omap_hwmod_addr_space omap2_timer11_addrs[];
30extern struct omap_hwmod_addr_space omap2430_mmc1_addr_space[];
31extern struct omap_hwmod_addr_space omap2430_mmc2_addr_space[];
32extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[];
33extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[];
34extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
35extern struct omap_hwmod_addr_space omap2_dma_system_addrs[]; 22extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
36extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
37extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[];
38 23
39/* Common IP block data across OMAP2xxx */ 24/* Common IP block data across OMAP2xxx */
40extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr; 25extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr;
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 05e20aaf68dd..477910a48448 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -31,7 +31,6 @@
31 31
32#include "common.h" 32#include "common.h"
33#include "common-board-devices.h" 33#include "common-board-devices.h"
34#include "dss-common.h"
35#include "control.h" 34#include "control.h"
36#include "omap_device.h" 35#include "omap_device.h"
37#include "omap-pm.h" 36#include "omap-pm.h"
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 678d2a31dcb8..76b0454ddc49 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -30,7 +30,6 @@
30#include "powerdomain.h" 30#include "powerdomain.h"
31#include "clockdomain.h" 31#include "clockdomain.h"
32#include "pm.h" 32#include "pm.h"
33#include "twl-common.h"
34 33
35#ifdef CONFIG_SUSPEND 34#ifdef CONFIG_SUSPEND
36/* 35/*
@@ -72,42 +71,6 @@ void omap_pm_get_oscillator(u32 *tstart, u32 *tshut)
72} 71}
73#endif 72#endif
74 73
75static int __init _init_omap_device(char *name)
76{
77 struct omap_hwmod *oh;
78 struct platform_device *pdev;
79
80 oh = omap_hwmod_lookup(name);
81 if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
82 __func__, name))
83 return -ENODEV;
84
85 pdev = omap_device_build(oh->name, 0, oh, NULL, 0);
86 if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n",
87 __func__, name))
88 return -ENODEV;
89
90 return 0;
91}
92
93/*
94 * Build omap_devices for processors and bus.
95 */
96static void __init omap2_init_processor_devices(void)
97{
98 _init_omap_device("mpu");
99 if (omap3_has_iva())
100 _init_omap_device("iva");
101
102 if (cpu_is_omap44xx()) {
103 _init_omap_device("l3_main_1");
104 _init_omap_device("dsp");
105 _init_omap_device("iva");
106 } else {
107 _init_omap_device("l3_main");
108 }
109}
110
111int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused) 74int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
112{ 75{
113 clkdm_allow_idle(clkdm); 76 clkdm_allow_idle(clkdm);
@@ -215,7 +178,7 @@ static int omap_pm_enter(suspend_state_t suspend_state)
215static int omap_pm_begin(suspend_state_t state) 178static int omap_pm_begin(suspend_state_t state)
216{ 179{
217 cpu_idle_poll_ctrl(true); 180 cpu_idle_poll_ctrl(true);
218 if (cpu_is_omap34xx()) 181 if (soc_is_omap34xx())
219 omap_prcm_irq_prepare(); 182 omap_prcm_irq_prepare();
220 return 0; 183 return 0;
221} 184}
@@ -227,7 +190,7 @@ static void omap_pm_end(void)
227 190
228static void omap_pm_finish(void) 191static void omap_pm_finish(void)
229{ 192{
230 if (cpu_is_omap34xx()) 193 if (soc_is_omap34xx())
231 omap_prcm_irq_complete(); 194 omap_prcm_irq_complete();
232} 195}
233 196
@@ -252,7 +215,7 @@ void omap_common_suspend_init(void *pm_suspend)
252 215
253static void __init omap3_init_voltages(void) 216static void __init omap3_init_voltages(void)
254{ 217{
255 if (!cpu_is_omap34xx()) 218 if (!soc_is_omap34xx())
256 return; 219 return;
257 220
258 omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu"); 221 omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu");
@@ -261,7 +224,7 @@ static void __init omap3_init_voltages(void)
261 224
262static void __init omap4_init_voltages(void) 225static void __init omap4_init_voltages(void)
263{ 226{
264 if (!cpu_is_omap44xx()) 227 if (!soc_is_omap44xx())
265 return; 228 return;
266 229
267 omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu"); 230 omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu");
@@ -269,18 +232,8 @@ static void __init omap4_init_voltages(void)
269 omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva"); 232 omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva");
270} 233}
271 234
272static inline void omap_init_cpufreq(void)
273{
274 struct platform_device_info devinfo = { .name = "omap-cpufreq" };
275
276 if (!of_have_populated_dt())
277 platform_device_register_full(&devinfo);
278}
279
280static int __init omap2_common_pm_init(void) 235static int __init omap2_common_pm_init(void)
281{ 236{
282 if (!of_have_populated_dt())
283 omap2_init_processor_devices();
284 omap_pm_if_init(); 237 omap_pm_if_init();
285 238
286 return 0; 239 return 0;
@@ -289,13 +242,9 @@ omap_postcore_initcall(omap2_common_pm_init);
289 242
290int __init omap2_common_pm_late_init(void) 243int __init omap2_common_pm_late_init(void)
291{ 244{
292 if (of_have_populated_dt()) {
293 omap3_twl_init();
294 omap4_twl_init();
295 }
296
297 /* Init the voltage layer */ 245 /* Init the voltage layer */
298 omap_pmic_late_init(); 246 omap3_twl_init();
247 omap4_twl_init();
299 omap_voltage_late_init(); 248 omap_voltage_late_init();
300 249
301 /* Initialize the voltages */ 250 /* Initialize the voltages */
@@ -305,8 +254,5 @@ int __init omap2_common_pm_late_init(void)
305 /* Smartreflex device init */ 254 /* Smartreflex device init */
306 omap_devinit_smartreflex(); 255 omap_devinit_smartreflex();
307 256
308 /* cpufreq dummy device instantiation */
309 omap_init_cpufreq();
310
311 return 0; 257 return 0;
312} 258}
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 178e22c146b7..b3870220612e 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -287,7 +287,7 @@ int __init omap4_pm_init(void)
287 /* Overwrite the default cpu_do_idle() */ 287 /* Overwrite the default cpu_do_idle() */
288 arm_pm_idle = omap_default_idle; 288 arm_pm_idle = omap_default_idle;
289 289
290 if (cpu_is_omap44xx()) 290 if (cpu_is_omap44xx() || soc_is_omap54xx())
291 omap4_idle_init(); 291 omap4_idle_init();
292 292
293err2: 293err2:
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h
index babb5db5a3a4..e2ad14e77064 100644
--- a/arch/arm/mach-omap2/prcm43xx.h
+++ b/arch/arm/mach-omap2/prcm43xx.h
@@ -92,6 +92,7 @@
92#define AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x04b8 92#define AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x04b8
93#define AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x04c0 93#define AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x04c0
94#define AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x04c8 94#define AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x04c8
95#define AM43XX_CM_PER_RNG_CLKCTRL_OFFSET 0x04e0
95#define AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x0500 96#define AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x0500
96#define AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0508 97#define AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0508
97#define AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x0528 98#define AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x0528
@@ -133,6 +134,7 @@
133#define AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x0050 134#define AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x0050
134#define AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x0058 135#define AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x0058
135#define AM43XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0028 136#define AM43XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0028
137#define AM43XX_CM_PER_DES_CLKCTRL_OFFSET 0x0030
136#define AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET 0x0560 138#define AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET 0x0560
137#define AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET 0x0568 139#define AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET 0x0568
138#define AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET 0x0570 140#define AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET 0x0570
diff --git a/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h b/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h
deleted file mode 100644
index 1ee58c281a31..000000000000
--- a/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * SDRC register values for the Hynix H8MBX00U0MER-0EM
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8MBX00U0MER0EM
12#define __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8MBX00U0MER0EM
13
14#include "sdrc.h"
15
16/* Hynix H8MBX00U0MER-0EM */
17static struct omap_sdrc_params h8mbx00u0mer0em_sdrc_params[] = {
18 [0] = {
19 .rate = 200000000,
20 .actim_ctrla = 0xa2e1b4c6,
21 .actim_ctrlb = 0x0002131c,
22 .rfr_ctrl = 0x0005e601,
23 .mr = 0x00000032,
24 },
25 [1] = {
26 .rate = 166000000,
27 .actim_ctrla = 0x629db4c6,
28 .actim_ctrlb = 0x00012214,
29 .rfr_ctrl = 0x0004dc01,
30 .mr = 0x00000032,
31 },
32 [2] = {
33 .rate = 100000000,
34 .actim_ctrla = 0x51912284,
35 .actim_ctrlb = 0x0002120e,
36 .rfr_ctrl = 0x0002d101,
37 .mr = 0x00000022,
38 },
39 [3] = {
40 .rate = 83000000,
41 .actim_ctrla = 0x31512283,
42 .actim_ctrlb = 0x0001220a,
43 .rfr_ctrl = 0x00025501,
44 .mr = 0x00000022,
45 },
46 [4] = {
47 .rate = 0
48 },
49};
50
51#endif
diff --git a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
deleted file mode 100644
index 85cccc004c06..000000000000
--- a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * SDRC register values for the Micron MT46H32M32LF-6
3 *
4 * Copyright (C) 2008 Texas Instruments, Inc.
5 * Copyright (C) 2008-2009 Nokia Corporation
6 *
7 * Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
15#define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
16
17#include "sdrc.h"
18
19/* Micron MT46H32M32LF-6 */
20/* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */
21static struct omap_sdrc_params mt46h32m32lf6_sdrc_params[] = {
22 [0] = {
23 .rate = 166000000,
24 .actim_ctrla = 0x9a9db4c6,
25 .actim_ctrlb = 0x00011217,
26 .rfr_ctrl = 0x0004dc01,
27 .mr = 0x00000032,
28 },
29 [1] = {
30 .rate = 165941176,
31 .actim_ctrla = 0x9a9db4c6,
32 .actim_ctrlb = 0x00011217,
33 .rfr_ctrl = 0x0004dc01,
34 .mr = 0x00000032,
35 },
36 [2] = {
37 .rate = 83000000,
38 .actim_ctrla = 0x51512283,
39 .actim_ctrlb = 0x0001120c,
40 .rfr_ctrl = 0x00025501,
41 .mr = 0x00000032,
42 },
43 [3] = {
44 .rate = 82970588,
45 .actim_ctrla = 0x51512283,
46 .actim_ctrlb = 0x0001120c,
47 .rfr_ctrl = 0x00025501,
48 .mr = 0x00000032,
49 },
50 [4] = {
51 .rate = 0
52 },
53};
54
55#endif
diff --git a/arch/arm/mach-omap2/sdram-nokia.c b/arch/arm/mach-omap2/sdram-nokia.c
deleted file mode 100644
index 0fa7ffa9b5ed..000000000000
--- a/arch/arm/mach-omap2/sdram-nokia.c
+++ /dev/null
@@ -1,299 +0,0 @@
1/*
2 * SDRC register values for Nokia boards
3 *
4 * Copyright (C) 2008, 2010-2011 Nokia Corporation
5 *
6 * Lauri Leukkunen <lauri.leukkunen@nokia.com>
7 *
8 * Original code by Juha Yrjola <juha.yrjola@solidboot.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/clk.h>
17#include <linux/err.h>
18#include <linux/io.h>
19
20#include "common.h"
21#include "sdram-nokia.h"
22#include "sdrc.h"
23
24/* In picoseconds, except for tREF (ns), tXP, tCKE, tWTR (clks) */
25struct sdram_timings {
26 u32 casl;
27 u32 tDAL;
28 u32 tDPL;
29 u32 tRRD;
30 u32 tRCD;
31 u32 tRP;
32 u32 tRAS;
33 u32 tRC;
34 u32 tRFC;
35 u32 tXSR;
36
37 u32 tREF; /* in ns */
38
39 u32 tXP;
40 u32 tCKE;
41 u32 tWTR;
42};
43
44static const struct sdram_timings nokia_97dot6mhz_timings[] = {
45 {
46 .casl = 3,
47 .tDAL = 30725,
48 .tDPL = 15362,
49 .tRRD = 10241,
50 .tRCD = 20483,
51 .tRP = 15362,
52 .tRAS = 40967,
53 .tRC = 56330,
54 .tRFC = 138266,
55 .tXSR = 204839,
56
57 .tREF = 7798,
58
59 .tXP = 2,
60 .tCKE = 4,
61 .tWTR = 2,
62 },
63};
64
65static const struct sdram_timings nokia_166mhz_timings[] = {
66 {
67 .casl = 3,
68 .tDAL = 33000,
69 .tDPL = 15000,
70 .tRRD = 12000,
71 .tRCD = 22500,
72 .tRP = 18000,
73 .tRAS = 42000,
74 .tRC = 66000,
75 .tRFC = 138000,
76 .tXSR = 200000,
77
78 .tREF = 7800,
79
80 .tXP = 2,
81 .tCKE = 2,
82 .tWTR = 2
83 },
84};
85
86static const struct sdram_timings nokia_195dot2mhz_timings[] = {
87 {
88 .casl = 3,
89 .tDAL = 30725,
90 .tDPL = 15362,
91 .tRRD = 10241,
92 .tRCD = 20483,
93 .tRP = 15362,
94 .tRAS = 40967,
95 .tRC = 56330,
96 .tRFC = 138266,
97 .tXSR = 204839,
98
99 .tREF = 7752,
100
101 .tXP = 2,
102 .tCKE = 4,
103 .tWTR = 2,
104 },
105};
106
107static const struct sdram_timings nokia_200mhz_timings[] = {
108 {
109 .casl = 3,
110 .tDAL = 30000,
111 .tDPL = 15000,
112 .tRRD = 10000,
113 .tRCD = 20000,
114 .tRP = 15000,
115 .tRAS = 40000,
116 .tRC = 55000,
117 .tRFC = 140000,
118 .tXSR = 200000,
119
120 .tREF = 7800,
121
122 .tXP = 2,
123 .tCKE = 4,
124 .tWTR = 2
125 },
126};
127
128static const struct {
129 long rate;
130 struct sdram_timings const *data;
131} nokia_timings[] = {
132 { 83000000, nokia_166mhz_timings },
133 { 97600000, nokia_97dot6mhz_timings },
134 { 100000000, nokia_200mhz_timings },
135 { 166000000, nokia_166mhz_timings },
136 { 195200000, nokia_195dot2mhz_timings },
137 { 200000000, nokia_200mhz_timings },
138};
139static struct omap_sdrc_params nokia_sdrc_params[ARRAY_SIZE(nokia_timings) + 1];
140
141static unsigned long sdrc_get_fclk_period(long rate)
142{
143 /* In picoseconds */
144 return 1000000000 / rate;
145}
146
147static unsigned int sdrc_ps_to_ticks(unsigned int time_ps, long rate)
148{
149 unsigned long tick_ps;
150
151 /* Calculate in picosecs to yield more exact results */
152 tick_ps = sdrc_get_fclk_period(rate);
153
154 return (time_ps + tick_ps - 1) / tick_ps;
155}
156#undef DEBUG
157#ifdef DEBUG
158static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit,
159 int ticks, long rate, const char *name)
160#else
161static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit,
162 int ticks)
163#endif
164{
165 int mask, nr_bits;
166
167 nr_bits = end_bit - st_bit + 1;
168 if (ticks >= 1 << nr_bits)
169 return -1;
170 mask = (1 << nr_bits) - 1;
171 *regval &= ~(mask << st_bit);
172 *regval |= ticks << st_bit;
173#ifdef DEBUG
174 printk(KERN_INFO "SDRC %s: %i ticks %i ns\n", name, ticks,
175 (unsigned int)sdrc_get_fclk_period(rate) * ticks /
176 1000);
177#endif
178
179 return 0;
180}
181
182#ifdef DEBUG
183#define SDRC_SET_ONE(reg, st, end, field, rate) \
184 if (set_sdrc_timing_regval((reg), (st), (end), \
185 memory_timings->field, (rate), #field) < 0) \
186 err = -1;
187#else
188#define SDRC_SET_ONE(reg, st, end, field, rate) \
189 if (set_sdrc_timing_regval((reg), (st), (end), \
190 memory_timings->field) < 0) \
191 err = -1;
192#endif
193
194#ifdef DEBUG
195static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit,
196 int time, long rate, const char *name)
197#else
198static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit,
199 int time, long rate)
200#endif
201{
202 int ticks, ret;
203 ret = 0;
204
205 if (time == 0)
206 ticks = 0;
207 else
208 ticks = sdrc_ps_to_ticks(time, rate);
209
210#ifdef DEBUG
211 ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks,
212 rate, name);
213#else
214 ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks);
215#endif
216
217 return ret;
218}
219
220#ifdef DEBUG
221#define SDRC_SET_ONE_PS(reg, st, end, field, rate) \
222 if (set_sdrc_timing_regval_ps((reg), (st), (end), \
223 memory_timings->field, \
224 (rate), #field) < 0) \
225 err = -1;
226
227#else
228#define SDRC_SET_ONE_PS(reg, st, end, field, rate) \
229 if (set_sdrc_timing_regval_ps((reg), (st), (end), \
230 memory_timings->field, (rate)) < 0) \
231 err = -1;
232#endif
233
234static int sdrc_timings(int id, long rate,
235 const struct sdram_timings *memory_timings)
236{
237 u32 ticks_per_ms;
238 u32 rfr, l;
239 u32 actim_ctrla = 0, actim_ctrlb = 0;
240 u32 rfr_ctrl;
241 int err = 0;
242 long l3_rate = rate / 1000;
243
244 SDRC_SET_ONE_PS(&actim_ctrla, 0, 4, tDAL, l3_rate);
245 SDRC_SET_ONE_PS(&actim_ctrla, 6, 8, tDPL, l3_rate);
246 SDRC_SET_ONE_PS(&actim_ctrla, 9, 11, tRRD, l3_rate);
247 SDRC_SET_ONE_PS(&actim_ctrla, 12, 14, tRCD, l3_rate);
248 SDRC_SET_ONE_PS(&actim_ctrla, 15, 17, tRP, l3_rate);
249 SDRC_SET_ONE_PS(&actim_ctrla, 18, 21, tRAS, l3_rate);
250 SDRC_SET_ONE_PS(&actim_ctrla, 22, 26, tRC, l3_rate);
251 SDRC_SET_ONE_PS(&actim_ctrla, 27, 31, tRFC, l3_rate);
252
253 SDRC_SET_ONE_PS(&actim_ctrlb, 0, 7, tXSR, l3_rate);
254
255 SDRC_SET_ONE(&actim_ctrlb, 8, 10, tXP, l3_rate);
256 SDRC_SET_ONE(&actim_ctrlb, 12, 14, tCKE, l3_rate);
257 SDRC_SET_ONE(&actim_ctrlb, 16, 17, tWTR, l3_rate);
258
259 ticks_per_ms = l3_rate;
260 rfr = memory_timings[0].tREF * ticks_per_ms / 1000000;
261 if (rfr > 65535 + 50)
262 rfr = 65535;
263 else
264 rfr -= 50;
265
266#ifdef DEBUG
267 printk(KERN_INFO "SDRC tREF: %i ticks\n", rfr);
268#endif
269
270 l = rfr << 8;
271 rfr_ctrl = l | 0x1; /* autorefresh, reload counter with 1xARCV */
272
273 nokia_sdrc_params[id].rate = rate;
274 nokia_sdrc_params[id].actim_ctrla = actim_ctrla;
275 nokia_sdrc_params[id].actim_ctrlb = actim_ctrlb;
276 nokia_sdrc_params[id].rfr_ctrl = rfr_ctrl;
277 nokia_sdrc_params[id].mr = 0x32;
278
279 nokia_sdrc_params[id + 1].rate = 0;
280
281 return err;
282}
283
284struct omap_sdrc_params *nokia_get_sdram_timings(void)
285{
286 int err = 0;
287 int i;
288
289 for (i = 0; i < ARRAY_SIZE(nokia_timings); i++) {
290 err |= sdrc_timings(i, nokia_timings[i].rate,
291 nokia_timings[i].data);
292 if (err)
293 pr_err("%s: error with rate %ld: %d\n", __func__,
294 nokia_timings[i].rate, err);
295 }
296
297 return err ? NULL : nokia_sdrc_params;
298}
299
diff --git a/arch/arm/mach-omap2/sdram-nokia.h b/arch/arm/mach-omap2/sdram-nokia.h
deleted file mode 100644
index ee63da5f8df0..000000000000
--- a/arch/arm/mach-omap2/sdram-nokia.h
+++ /dev/null
@@ -1,12 +0,0 @@
1/*
2 * SDRC register values for Nokia boards
3 *
4 * Copyright (C) 2010 Nokia
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11struct omap_sdrc_params *nokia_get_sdram_timings(void);
12
diff --git a/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h b/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h
deleted file mode 100644
index 003f7bf4e2e3..000000000000
--- a/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * SDRC register values for the Numonyx M65KXXXXAM
3 *
4 * Copyright (C) 2009 Integration Software and Electronic Engineering.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM
12#define __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM
13
14#include "sdrc.h"
15
16/* Numonyx M65KXXXXAM */
17static struct omap_sdrc_params m65kxxxxam_sdrc_params[] = {
18 [0] = {
19 .rate = 200000000,
20 .actim_ctrla = 0xe321d4c6,
21 .actim_ctrlb = 0x00022328,
22 .rfr_ctrl = 0x0005e601,
23 .mr = 0x00000032,
24 },
25 [1] = {
26 .rate = 166000000,
27 .actim_ctrla = 0xba9dc485,
28 .actim_ctrlb = 0x00022321,
29 .rfr_ctrl = 0x0004dc01,
30 .mr = 0x00000032,
31 },
32 [2] = {
33 .rate = 133000000,
34 .actim_ctrla = 0x9a19b485,
35 .actim_ctrlb = 0x0002231b,
36 .rfr_ctrl = 0x0003de01,
37 .mr = 0x00000032,
38 },
39 [3] = {
40 .rate = 83000000,
41 .actim_ctrla = 0x594ca242,
42 .actim_ctrlb = 0x00022310,
43 .rfr_ctrl = 0x00025501,
44 .mr = 0x00000032,
45 },
46 [4] = {
47 .rate = 0
48 },
49};
50
51#endif
diff --git a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
deleted file mode 100644
index 8dc3de5ebb5b..000000000000
--- a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * SDRC register values for the Qimonda HYB18M512160AF-6
3 *
4 * Copyright (C) 2008-2009 Texas Instruments, Inc.
5 * Copyright (C) 2008-2009 Nokia Corporation
6 *
7 * Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
15#define ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
16
17#include "sdrc.h"
18
19/* Qimonda HYB18M512160AF-6 */
20static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = {
21 [0] = {
22 .rate = 166000000,
23 .actim_ctrla = 0x629db4c6,
24 .actim_ctrlb = 0x00012214,
25 .rfr_ctrl = 0x0004dc01,
26 .mr = 0x00000032,
27 },
28 [1] = {
29 .rate = 165941176,
30 .actim_ctrla = 0x629db4c6,
31 .actim_ctrlb = 0x00012214,
32 .rfr_ctrl = 0x0004dc01,
33 .mr = 0x00000032,
34 },
35 [2] = {
36 .rate = 83000000,
37 .actim_ctrla = 0x31512283,
38 .actim_ctrlb = 0x0001220a,
39 .rfr_ctrl = 0x00025501,
40 .mr = 0x00000022,
41 },
42 [3] = {
43 .rate = 82970588,
44 .actim_ctrla = 0x31512283,
45 .actim_ctrlb = 0x0001220a,
46 .rfr_ctrl = 0x00025501,
47 .mr = 0x00000022,
48 },
49 [4] = {
50 .rate = 0
51 },
52};
53
54#endif
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
deleted file mode 100644
index 8e072de89fed..000000000000
--- a/arch/arm/mach-omap2/serial.c
+++ /dev/null
@@ -1,332 +0,0 @@
1/*
2 * arch/arm/mach-omap2/serial.c
3 *
4 * OMAP2 serial support.
5 *
6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
9 * Major rework for PM support by Kevin Hilman
10 *
11 * Based off of arch/arm/mach-omap/omap1/serial.c
12 *
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24#include <linux/delay.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27#include <linux/pm_runtime.h>
28#include <linux/console.h>
29#include <linux/omap-dma.h>
30#include <linux/platform_data/serial-omap.h>
31
32#include "common.h"
33#include "omap_hwmod.h"
34#include "omap_device.h"
35#include "omap-pm.h"
36#include "soc.h"
37#include "prm2xxx_3xxx.h"
38#include "pm.h"
39#include "cm2xxx_3xxx.h"
40#include "prm-regbits-34xx.h"
41#include "control.h"
42#include "mux.h"
43#include "serial.h"
44
45/*
46 * NOTE: By default the serial auto_suspend timeout is disabled as it causes
47 * lost characters over the serial ports. This means that the UART clocks will
48 * stay on until power/autosuspend_delay is set for the uart from sysfs.
49 * This also causes that any deeper omap sleep states are blocked.
50 */
51#define DEFAULT_AUTOSUSPEND_DELAY -1
52
53#define MAX_UART_HWMOD_NAME_LEN 16
54
55struct omap_uart_state {
56 int num;
57
58 struct list_head node;
59 struct omap_hwmod *oh;
60 struct omap_device_pad default_omap_uart_pads[2];
61};
62
63static LIST_HEAD(uart_list);
64static u8 num_uarts;
65static u8 console_uart_id = -1;
66static u8 uart_debug;
67
68#define DEFAULT_RXDMA_POLLRATE 1 /* RX DMA polling rate (us) */
69#define DEFAULT_RXDMA_BUFSIZE 4096 /* RX DMA buffer size */
70#define DEFAULT_RXDMA_TIMEOUT (3 * HZ)/* RX DMA timeout (jiffies) */
71
72static struct omap_uart_port_info omap_serial_default_info[] __initdata = {
73 {
74 .dma_enabled = false,
75 .dma_rx_buf_size = DEFAULT_RXDMA_BUFSIZE,
76 .dma_rx_poll_rate = DEFAULT_RXDMA_POLLRATE,
77 .dma_rx_timeout = DEFAULT_RXDMA_TIMEOUT,
78 .autosuspend_timeout = DEFAULT_AUTOSUSPEND_DELAY,
79 },
80};
81
82#ifdef CONFIG_PM
83static void omap_uart_enable_wakeup(struct device *dev, bool enable)
84{
85 struct platform_device *pdev = to_platform_device(dev);
86 struct omap_device *od = to_omap_device(pdev);
87
88 if (!od)
89 return;
90
91 if (enable)
92 omap_hwmod_enable_wakeup(od->hwmods[0]);
93 else
94 omap_hwmod_disable_wakeup(od->hwmods[0]);
95}
96
97#else
98static void omap_uart_enable_wakeup(struct device *dev, bool enable)
99{}
100#endif /* CONFIG_PM */
101
102#ifdef CONFIG_OMAP_MUX
103
104#define OMAP_UART_DEFAULT_PAD_NAME_LEN 28
105static char rx_pad_name[OMAP_UART_DEFAULT_PAD_NAME_LEN],
106 tx_pad_name[OMAP_UART_DEFAULT_PAD_NAME_LEN] __initdata;
107
108static void __init
109omap_serial_fill_uart_tx_rx_pads(struct omap_board_data *bdata,
110 struct omap_uart_state *uart)
111{
112 uart->default_omap_uart_pads[0].name = rx_pad_name;
113 uart->default_omap_uart_pads[0].flags = OMAP_DEVICE_PAD_REMUX |
114 OMAP_DEVICE_PAD_WAKEUP;
115 uart->default_omap_uart_pads[0].enable = OMAP_PIN_INPUT |
116 OMAP_MUX_MODE0;
117 uart->default_omap_uart_pads[0].idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0;
118 uart->default_omap_uart_pads[1].name = tx_pad_name;
119 uart->default_omap_uart_pads[1].enable = OMAP_PIN_OUTPUT |
120 OMAP_MUX_MODE0;
121 bdata->pads = uart->default_omap_uart_pads;
122 bdata->pads_cnt = ARRAY_SIZE(uart->default_omap_uart_pads);
123}
124
125static void __init omap_serial_check_wakeup(struct omap_board_data *bdata,
126 struct omap_uart_state *uart)
127{
128 struct omap_mux_partition *tx_partition = NULL, *rx_partition = NULL;
129 struct omap_mux *rx_mux = NULL, *tx_mux = NULL;
130 char *rx_fmt, *tx_fmt;
131 int uart_nr = bdata->id + 1;
132
133 if (bdata->id != 2) {
134 rx_fmt = "uart%d_rx.uart%d_rx";
135 tx_fmt = "uart%d_tx.uart%d_tx";
136 } else {
137 rx_fmt = "uart%d_rx_irrx.uart%d_rx_irrx";
138 tx_fmt = "uart%d_tx_irtx.uart%d_tx_irtx";
139 }
140
141 snprintf(rx_pad_name, OMAP_UART_DEFAULT_PAD_NAME_LEN, rx_fmt,
142 uart_nr, uart_nr);
143 snprintf(tx_pad_name, OMAP_UART_DEFAULT_PAD_NAME_LEN, tx_fmt,
144 uart_nr, uart_nr);
145
146 if (omap_mux_get_by_name(rx_pad_name, &rx_partition, &rx_mux) >= 0 &&
147 omap_mux_get_by_name
148 (tx_pad_name, &tx_partition, &tx_mux) >= 0) {
149 u16 tx_mode, rx_mode;
150
151 tx_mode = omap_mux_read(tx_partition, tx_mux->reg_offset);
152 rx_mode = omap_mux_read(rx_partition, rx_mux->reg_offset);
153
154 /*
155 * Check if uart is used in default tx/rx mode i.e. in mux mode0
156 * if yes then configure rx pin for wake up capability
157 */
158 if (OMAP_MODE_UART(rx_mode) && OMAP_MODE_UART(tx_mode))
159 omap_serial_fill_uart_tx_rx_pads(bdata, uart);
160 }
161}
162#else
163static void __init omap_serial_check_wakeup(struct omap_board_data *bdata,
164 struct omap_uart_state *uart)
165{
166}
167#endif
168
169static char *cmdline_find_option(char *str)
170{
171 extern char *saved_command_line;
172
173 return strstr(saved_command_line, str);
174}
175
176static int __init omap_serial_early_init(void)
177{
178 if (of_have_populated_dt())
179 return -ENODEV;
180
181 do {
182 char oh_name[MAX_UART_HWMOD_NAME_LEN];
183 struct omap_hwmod *oh;
184 struct omap_uart_state *uart;
185 char uart_name[MAX_UART_HWMOD_NAME_LEN];
186
187 snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
188 "uart%d", num_uarts + 1);
189 oh = omap_hwmod_lookup(oh_name);
190 if (!oh)
191 break;
192
193 uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
194 if (WARN_ON(!uart))
195 return -ENODEV;
196
197 uart->oh = oh;
198 uart->num = num_uarts++;
199 list_add_tail(&uart->node, &uart_list);
200 snprintf(uart_name, MAX_UART_HWMOD_NAME_LEN,
201 "%s%d", OMAP_SERIAL_NAME, uart->num);
202
203 if (cmdline_find_option(uart_name)) {
204 console_uart_id = uart->num;
205
206 if (console_loglevel >= CONSOLE_LOGLEVEL_DEBUG) {
207 uart_debug = true;
208 pr_info("%s used as console in debug mode: uart%d clocks will not be gated",
209 uart_name, uart->num);
210 }
211 }
212 } while (1);
213
214 return 0;
215}
216omap_postcore_initcall(omap_serial_early_init);
217
218/**
219 * omap_serial_init_port() - initialize single serial port
220 * @bdata: port specific board data pointer
221 * @info: platform specific data pointer
222 *
223 * This function initialies serial driver for given port only.
224 * Platforms can call this function instead of omap_serial_init()
225 * if they don't plan to use all available UARTs as serial ports.
226 *
227 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
228 * use only one of the two.
229 */
230void __init omap_serial_init_port(struct omap_board_data *bdata,
231 struct omap_uart_port_info *info)
232{
233 struct omap_uart_state *uart;
234 struct omap_hwmod *oh;
235 struct platform_device *pdev;
236 void *pdata = NULL;
237 u32 pdata_size = 0;
238 char *name;
239 struct omap_uart_port_info omap_up;
240
241 if (WARN_ON(!bdata))
242 return;
243 if (WARN_ON(bdata->id < 0))
244 return;
245 if (WARN_ON(bdata->id >= num_uarts))
246 return;
247
248 list_for_each_entry(uart, &uart_list, node)
249 if (bdata->id == uart->num)
250 break;
251 if (!info)
252 info = omap_serial_default_info;
253
254 oh = uart->oh;
255 name = OMAP_SERIAL_DRIVER_NAME;
256
257 omap_up.dma_enabled = info->dma_enabled;
258 omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
259 omap_up.flags = UPF_BOOT_AUTOCONF;
260 omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count;
261 omap_up.enable_wakeup = omap_uart_enable_wakeup;
262 omap_up.dma_rx_buf_size = info->dma_rx_buf_size;
263 omap_up.dma_rx_timeout = info->dma_rx_timeout;
264 omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
265 omap_up.autosuspend_timeout = info->autosuspend_timeout;
266
267 pdata = &omap_up;
268 pdata_size = sizeof(struct omap_uart_port_info);
269
270 if (WARN_ON(!oh))
271 return;
272
273 pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size);
274 if (IS_ERR(pdev)) {
275 WARN(1, "Could not build omap_device for %s: %s.\n", name,
276 oh->name);
277 return;
278 }
279
280 oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
281
282 if (console_uart_id == bdata->id) {
283 omap_device_enable(pdev);
284 pm_runtime_set_active(&pdev->dev);
285 }
286
287 oh->dev_attr = uart;
288
289 if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads)
290 && !uart_debug)
291 device_init_wakeup(&pdev->dev, true);
292}
293
294/**
295 * omap_serial_board_init() - initialize all supported serial ports
296 * @info: platform specific data pointer
297 *
298 * Initializes all available UARTs as serial ports. Platforms
299 * can call this function when they want to have default behaviour
300 * for serial ports (e.g initialize them all as serial ports).
301 */
302void __init omap_serial_board_init(struct omap_uart_port_info *info)
303{
304 struct omap_uart_state *uart;
305 struct omap_board_data bdata;
306
307 list_for_each_entry(uart, &uart_list, node) {
308 bdata.id = uart->num;
309 bdata.flags = 0;
310 bdata.pads = NULL;
311 bdata.pads_cnt = 0;
312
313 omap_serial_check_wakeup(&bdata, uart);
314
315 if (!info)
316 omap_serial_init_port(&bdata, NULL);
317 else
318 omap_serial_init_port(&bdata, &info[uart->num]);
319 }
320}
321
322/**
323 * omap_serial_init() - initialize all supported serial ports
324 *
325 * Initializes all available UARTs.
326 * Platforms can call this function when they want to have default behaviour
327 * for serial ports (e.g initialize them all as serial ports).
328 */
329void __init omap_serial_init(void)
330{
331 omap_serial_board_init(NULL);
332}
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
deleted file mode 100644
index a72738eab009..000000000000
--- a/arch/arm/mach-omap2/twl-common.c
+++ /dev/null
@@ -1,564 +0,0 @@
1/*
2 * twl-common.c
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc..
5 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 */
22
23#include <linux/i2c.h>
24#include <linux/i2c/twl.h>
25#include <linux/gpio.h>
26#include <linux/string.h>
27#include <linux/phy/phy.h>
28#include <linux/regulator/machine.h>
29#include <linux/regulator/fixed.h>
30
31#include "soc.h"
32#include "twl-common.h"
33#include "pm.h"
34#include "voltage.h"
35#include "mux.h"
36
37static struct i2c_board_info __initdata pmic_i2c_board_info = {
38 .addr = 0x48,
39 .flags = I2C_CLIENT_WAKE,
40};
41
42#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
43static int twl_set_voltage(void *data, int target_uV)
44{
45 struct voltagedomain *voltdm = (struct voltagedomain *)data;
46 return voltdm_scale(voltdm, target_uV);
47}
48
49static int twl_get_voltage(void *data)
50{
51 struct voltagedomain *voltdm = (struct voltagedomain *)data;
52 return voltdm_get_voltage(voltdm);
53}
54#endif
55
56void __init omap_pmic_init(int bus, u32 clkrate,
57 const char *pmic_type, int pmic_irq,
58 struct twl4030_platform_data *pmic_data)
59{
60 omap_mux_init_signal("sys_nirq", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
61 strlcpy(pmic_i2c_board_info.type, pmic_type,
62 sizeof(pmic_i2c_board_info.type));
63 pmic_i2c_board_info.irq = pmic_irq;
64 pmic_i2c_board_info.platform_data = pmic_data;
65
66 omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
67}
68
69#ifdef CONFIG_ARCH_OMAP4
70void __init omap4_pmic_init(const char *pmic_type,
71 struct twl4030_platform_data *pmic_data,
72 struct i2c_board_info *devices, int nr_devices)
73{
74 /* PMIC part*/
75 unsigned int irq;
76
77 omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
78 omap_mux_init_signal("fref_clk0_out.sys_drm_msecure", OMAP_PIN_OUTPUT);
79 irq = omap4_xlate_irq(7 + OMAP44XX_IRQ_GIC_START);
80 omap_pmic_init(1, 400, pmic_type, irq, pmic_data);
81
82 /* Register additional devices on i2c1 bus if needed */
83 if (devices)
84 i2c_register_board_info(1, devices, nr_devices);
85}
86#endif
87
88void __init omap_pmic_late_init(void)
89{
90 /* Init the OMAP TWL parameters (if PMIC has been registerd) */
91 if (!pmic_i2c_board_info.irq)
92 return;
93
94 omap3_twl_init();
95 omap4_twl_init();
96}
97
98#if defined(CONFIG_ARCH_OMAP3)
99static struct twl4030_usb_data omap3_usb_pdata = {
100 .usb_mode = T2_USB_MODE_ULPI,
101};
102
103static int omap3_batt_table[] = {
104/* 0 C */
10530800, 29500, 28300, 27100,
10626000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
10717200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
10811600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
1098020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
1105640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
1114040, 3910, 3790, 3670, 3550
112};
113
114static struct twl4030_bci_platform_data omap3_bci_pdata = {
115 .battery_tmp_tbl = omap3_batt_table,
116 .tblsize = ARRAY_SIZE(omap3_batt_table),
117};
118
119static struct twl4030_madc_platform_data omap3_madc_pdata = {
120 .irq_line = 1,
121};
122
123static struct twl4030_codec_data omap3_codec;
124
125static struct twl4030_audio_data omap3_audio_pdata = {
126 .audio_mclk = 26000000,
127 .codec = &omap3_codec,
128};
129
130static struct regulator_consumer_supply omap3_vdda_dac_supplies[] = {
131 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
132};
133
134static struct regulator_init_data omap3_vdac_idata = {
135 .constraints = {
136 .min_uV = 1800000,
137 .max_uV = 1800000,
138 .valid_modes_mask = REGULATOR_MODE_NORMAL
139 | REGULATOR_MODE_STANDBY,
140 .valid_ops_mask = REGULATOR_CHANGE_MODE
141 | REGULATOR_CHANGE_STATUS,
142 },
143 .num_consumer_supplies = ARRAY_SIZE(omap3_vdda_dac_supplies),
144 .consumer_supplies = omap3_vdda_dac_supplies,
145};
146
147static struct regulator_consumer_supply omap3_vpll2_supplies[] = {
148 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
149 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
150 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
151};
152
153static struct regulator_init_data omap3_vpll2_idata = {
154 .constraints = {
155 .min_uV = 1800000,
156 .max_uV = 1800000,
157 .valid_modes_mask = REGULATOR_MODE_NORMAL
158 | REGULATOR_MODE_STANDBY,
159 .valid_ops_mask = REGULATOR_CHANGE_MODE
160 | REGULATOR_CHANGE_STATUS,
161 },
162 .num_consumer_supplies = ARRAY_SIZE(omap3_vpll2_supplies),
163 .consumer_supplies = omap3_vpll2_supplies,
164};
165
166static struct regulator_consumer_supply omap3_vdd1_supply[] = {
167 REGULATOR_SUPPLY("vcc", "cpu0"),
168};
169
170static struct regulator_consumer_supply omap3_vdd2_supply[] = {
171 REGULATOR_SUPPLY("vcc", "l3_main.0"),
172};
173
174static struct regulator_init_data omap3_vdd1 = {
175 .constraints = {
176 .name = "vdd_mpu_iva",
177 .min_uV = 600000,
178 .max_uV = 1450000,
179 .valid_modes_mask = REGULATOR_MODE_NORMAL,
180 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
181 },
182 .num_consumer_supplies = ARRAY_SIZE(omap3_vdd1_supply),
183 .consumer_supplies = omap3_vdd1_supply,
184};
185
186static struct regulator_init_data omap3_vdd2 = {
187 .constraints = {
188 .name = "vdd_core",
189 .min_uV = 600000,
190 .max_uV = 1450000,
191 .valid_modes_mask = REGULATOR_MODE_NORMAL,
192 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
193 },
194 .num_consumer_supplies = ARRAY_SIZE(omap3_vdd2_supply),
195 .consumer_supplies = omap3_vdd2_supply,
196};
197
198static struct twl_regulator_driver_data omap3_vdd1_drvdata = {
199 .get_voltage = twl_get_voltage,
200 .set_voltage = twl_set_voltage,
201};
202
203static struct twl_regulator_driver_data omap3_vdd2_drvdata = {
204 .get_voltage = twl_get_voltage,
205 .set_voltage = twl_set_voltage,
206};
207
208void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
209 u32 pdata_flags, u32 regulators_flags)
210{
211 if (!pmic_data->vdd1) {
212 omap3_vdd1.driver_data = &omap3_vdd1_drvdata;
213 omap3_vdd1_drvdata.data = voltdm_lookup("mpu_iva");
214 pmic_data->vdd1 = &omap3_vdd1;
215 }
216 if (!pmic_data->vdd2) {
217 omap3_vdd2.driver_data = &omap3_vdd2_drvdata;
218 omap3_vdd2_drvdata.data = voltdm_lookup("core");
219 pmic_data->vdd2 = &omap3_vdd2;
220 }
221
222 /* Common platform data configurations */
223 if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
224 pmic_data->usb = &omap3_usb_pdata;
225
226 if (pdata_flags & TWL_COMMON_PDATA_BCI && !pmic_data->bci)
227 pmic_data->bci = &omap3_bci_pdata;
228
229 if (pdata_flags & TWL_COMMON_PDATA_MADC && !pmic_data->madc)
230 pmic_data->madc = &omap3_madc_pdata;
231
232 if (pdata_flags & TWL_COMMON_PDATA_AUDIO && !pmic_data->audio)
233 pmic_data->audio = &omap3_audio_pdata;
234
235 /* Common regulator configurations */
236 if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
237 pmic_data->vdac = &omap3_vdac_idata;
238
239 if (regulators_flags & TWL_COMMON_REGULATOR_VPLL2 && !pmic_data->vpll2)
240 pmic_data->vpll2 = &omap3_vpll2_idata;
241}
242#endif /* CONFIG_ARCH_OMAP3 */
243
244#if defined(CONFIG_ARCH_OMAP4)
245static struct twl4030_usb_data omap4_usb_pdata = {
246};
247
248static struct regulator_consumer_supply omap4_vdda_hdmi_dac_supplies[] = {
249 REGULATOR_SUPPLY("vdda_hdmi_dac", "omapdss_hdmi"),
250};
251
252static struct regulator_init_data omap4_vdac_idata = {
253 .constraints = {
254 .min_uV = 1800000,
255 .max_uV = 1800000,
256 .valid_modes_mask = REGULATOR_MODE_NORMAL
257 | REGULATOR_MODE_STANDBY,
258 .valid_ops_mask = REGULATOR_CHANGE_MODE
259 | REGULATOR_CHANGE_STATUS,
260 },
261 .num_consumer_supplies = ARRAY_SIZE(omap4_vdda_hdmi_dac_supplies),
262 .consumer_supplies = omap4_vdda_hdmi_dac_supplies,
263 .supply_regulator = "V2V1",
264};
265
266static struct regulator_init_data omap4_vaux2_idata = {
267 .constraints = {
268 .min_uV = 1200000,
269 .max_uV = 2800000,
270 .apply_uV = true,
271 .valid_modes_mask = REGULATOR_MODE_NORMAL
272 | REGULATOR_MODE_STANDBY,
273 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
274 | REGULATOR_CHANGE_MODE
275 | REGULATOR_CHANGE_STATUS,
276 },
277};
278
279static struct regulator_init_data omap4_vaux3_idata = {
280 .constraints = {
281 .min_uV = 1000000,
282 .max_uV = 3000000,
283 .apply_uV = true,
284 .valid_modes_mask = REGULATOR_MODE_NORMAL
285 | REGULATOR_MODE_STANDBY,
286 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
287 | REGULATOR_CHANGE_MODE
288 | REGULATOR_CHANGE_STATUS,
289 },
290};
291
292static struct regulator_consumer_supply omap4_vmmc_supply[] = {
293 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
294};
295
296/* VMMC1 for MMC1 card */
297static struct regulator_init_data omap4_vmmc_idata = {
298 .constraints = {
299 .min_uV = 1200000,
300 .max_uV = 3000000,
301 .apply_uV = true,
302 .valid_modes_mask = REGULATOR_MODE_NORMAL
303 | REGULATOR_MODE_STANDBY,
304 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
305 | REGULATOR_CHANGE_MODE
306 | REGULATOR_CHANGE_STATUS,
307 },
308 .num_consumer_supplies = ARRAY_SIZE(omap4_vmmc_supply),
309 .consumer_supplies = omap4_vmmc_supply,
310};
311
312static struct regulator_init_data omap4_vpp_idata = {
313 .constraints = {
314 .min_uV = 1800000,
315 .max_uV = 2500000,
316 .apply_uV = true,
317 .valid_modes_mask = REGULATOR_MODE_NORMAL
318 | REGULATOR_MODE_STANDBY,
319 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
320 | REGULATOR_CHANGE_MODE
321 | REGULATOR_CHANGE_STATUS,
322 },
323};
324
325static struct regulator_init_data omap4_vana_idata = {
326 .constraints = {
327 .min_uV = 2100000,
328 .max_uV = 2100000,
329 .valid_modes_mask = REGULATOR_MODE_NORMAL
330 | REGULATOR_MODE_STANDBY,
331 .valid_ops_mask = REGULATOR_CHANGE_MODE
332 | REGULATOR_CHANGE_STATUS,
333 },
334};
335
336static struct regulator_consumer_supply omap4_vcxio_supply[] = {
337 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dss"),
338 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
339 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.1"),
340};
341
342static struct regulator_init_data omap4_vcxio_idata = {
343 .constraints = {
344 .min_uV = 1800000,
345 .max_uV = 1800000,
346 .valid_modes_mask = REGULATOR_MODE_NORMAL
347 | REGULATOR_MODE_STANDBY,
348 .valid_ops_mask = REGULATOR_CHANGE_MODE
349 | REGULATOR_CHANGE_STATUS,
350 .always_on = true,
351 },
352 .num_consumer_supplies = ARRAY_SIZE(omap4_vcxio_supply),
353 .consumer_supplies = omap4_vcxio_supply,
354 .supply_regulator = "V2V1",
355};
356
357static struct regulator_init_data omap4_vusb_idata = {
358 .constraints = {
359 .min_uV = 3300000,
360 .max_uV = 3300000,
361 .valid_modes_mask = REGULATOR_MODE_NORMAL
362 | REGULATOR_MODE_STANDBY,
363 .valid_ops_mask = REGULATOR_CHANGE_MODE
364 | REGULATOR_CHANGE_STATUS,
365 },
366};
367
368static struct regulator_init_data omap4_clk32kg_idata = {
369 .constraints = {
370 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
371 },
372};
373
374static struct regulator_consumer_supply omap4_vdd1_supply[] = {
375 REGULATOR_SUPPLY("vcc", "cpu0"),
376};
377
378static struct regulator_consumer_supply omap4_vdd2_supply[] = {
379 REGULATOR_SUPPLY("vcc", "iva.0"),
380};
381
382static struct regulator_consumer_supply omap4_vdd3_supply[] = {
383 REGULATOR_SUPPLY("vcc", "l3_main.0"),
384};
385
386static struct regulator_init_data omap4_vdd1 = {
387 .constraints = {
388 .name = "vdd_mpu",
389 .min_uV = 500000,
390 .max_uV = 1500000,
391 .valid_modes_mask = REGULATOR_MODE_NORMAL,
392 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
393 },
394 .num_consumer_supplies = ARRAY_SIZE(omap4_vdd1_supply),
395 .consumer_supplies = omap4_vdd1_supply,
396};
397
398static struct regulator_init_data omap4_vdd2 = {
399 .constraints = {
400 .name = "vdd_iva",
401 .min_uV = 500000,
402 .max_uV = 1500000,
403 .valid_modes_mask = REGULATOR_MODE_NORMAL,
404 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
405 },
406 .num_consumer_supplies = ARRAY_SIZE(omap4_vdd2_supply),
407 .consumer_supplies = omap4_vdd2_supply,
408};
409
410static struct regulator_init_data omap4_vdd3 = {
411 .constraints = {
412 .name = "vdd_core",
413 .min_uV = 500000,
414 .max_uV = 1500000,
415 .valid_modes_mask = REGULATOR_MODE_NORMAL,
416 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
417 },
418 .num_consumer_supplies = ARRAY_SIZE(omap4_vdd3_supply),
419 .consumer_supplies = omap4_vdd3_supply,
420};
421
422
423static struct twl_regulator_driver_data omap4_vdd1_drvdata = {
424 .get_voltage = twl_get_voltage,
425 .set_voltage = twl_set_voltage,
426};
427
428static struct twl_regulator_driver_data omap4_vdd2_drvdata = {
429 .get_voltage = twl_get_voltage,
430 .set_voltage = twl_set_voltage,
431};
432
433static struct twl_regulator_driver_data omap4_vdd3_drvdata = {
434 .get_voltage = twl_get_voltage,
435 .set_voltage = twl_set_voltage,
436};
437
438static struct regulator_consumer_supply omap4_v1v8_supply[] = {
439 REGULATOR_SUPPLY("vio", "1-004b"),
440};
441
442static struct regulator_init_data omap4_v1v8_idata = {
443 .constraints = {
444 .min_uV = 1800000,
445 .max_uV = 1800000,
446 .valid_modes_mask = REGULATOR_MODE_NORMAL
447 | REGULATOR_MODE_STANDBY,
448 .valid_ops_mask = REGULATOR_CHANGE_MODE
449 | REGULATOR_CHANGE_STATUS,
450 .always_on = true,
451 },
452 .num_consumer_supplies = ARRAY_SIZE(omap4_v1v8_supply),
453 .consumer_supplies = omap4_v1v8_supply,
454};
455
456static struct regulator_consumer_supply omap4_v2v1_supply[] = {
457 REGULATOR_SUPPLY("v2v1", "1-004b"),
458};
459
460static struct regulator_init_data omap4_v2v1_idata = {
461 .constraints = {
462 .min_uV = 2100000,
463 .max_uV = 2100000,
464 .valid_modes_mask = REGULATOR_MODE_NORMAL
465 | REGULATOR_MODE_STANDBY,
466 .valid_ops_mask = REGULATOR_CHANGE_MODE
467 | REGULATOR_CHANGE_STATUS,
468 },
469 .num_consumer_supplies = ARRAY_SIZE(omap4_v2v1_supply),
470 .consumer_supplies = omap4_v2v1_supply,
471};
472
473void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
474 u32 pdata_flags, u32 regulators_flags)
475{
476 if (!pmic_data->vdd1) {
477 omap4_vdd1.driver_data = &omap4_vdd1_drvdata;
478 omap4_vdd1_drvdata.data = voltdm_lookup("mpu");
479 pmic_data->vdd1 = &omap4_vdd1;
480 }
481
482 if (!pmic_data->vdd2) {
483 omap4_vdd2.driver_data = &omap4_vdd2_drvdata;
484 omap4_vdd2_drvdata.data = voltdm_lookup("iva");
485 pmic_data->vdd2 = &omap4_vdd2;
486 }
487
488 if (!pmic_data->vdd3) {
489 omap4_vdd3.driver_data = &omap4_vdd3_drvdata;
490 omap4_vdd3_drvdata.data = voltdm_lookup("core");
491 pmic_data->vdd3 = &omap4_vdd3;
492 }
493
494 /* Common platform data configurations */
495 if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
496 pmic_data->usb = &omap4_usb_pdata;
497
498 /* Common regulator configurations */
499 if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
500 pmic_data->vdac = &omap4_vdac_idata;
501
502 if (regulators_flags & TWL_COMMON_REGULATOR_VAUX2 && !pmic_data->vaux2)
503 pmic_data->vaux2 = &omap4_vaux2_idata;
504
505 if (regulators_flags & TWL_COMMON_REGULATOR_VAUX3 && !pmic_data->vaux3)
506 pmic_data->vaux3 = &omap4_vaux3_idata;
507
508 if (regulators_flags & TWL_COMMON_REGULATOR_VMMC && !pmic_data->vmmc)
509 pmic_data->vmmc = &omap4_vmmc_idata;
510
511 if (regulators_flags & TWL_COMMON_REGULATOR_VPP && !pmic_data->vpp)
512 pmic_data->vpp = &omap4_vpp_idata;
513
514 if (regulators_flags & TWL_COMMON_REGULATOR_VANA && !pmic_data->vana)
515 pmic_data->vana = &omap4_vana_idata;
516
517 if (regulators_flags & TWL_COMMON_REGULATOR_VCXIO && !pmic_data->vcxio)
518 pmic_data->vcxio = &omap4_vcxio_idata;
519
520 if (regulators_flags & TWL_COMMON_REGULATOR_VUSB && !pmic_data->vusb)
521 pmic_data->vusb = &omap4_vusb_idata;
522
523 if (regulators_flags & TWL_COMMON_REGULATOR_CLK32KG &&
524 !pmic_data->clk32kg)
525 pmic_data->clk32kg = &omap4_clk32kg_idata;
526
527 if (regulators_flags & TWL_COMMON_REGULATOR_V1V8 && !pmic_data->v1v8)
528 pmic_data->v1v8 = &omap4_v1v8_idata;
529
530 if (regulators_flags & TWL_COMMON_REGULATOR_V2V1 && !pmic_data->v2v1)
531 pmic_data->v2v1 = &omap4_v2v1_idata;
532}
533#endif /* CONFIG_ARCH_OMAP4 */
534
535#if IS_ENABLED(CONFIG_SND_OMAP_SOC_OMAP_TWL4030)
536#include <linux/platform_data/omap-twl4030.h>
537
538/* Commonly used configuration */
539static struct omap_tw4030_pdata omap_twl4030_audio_data;
540
541static struct platform_device audio_device = {
542 .name = "omap-twl4030",
543 .id = -1,
544};
545
546void omap_twl4030_audio_init(char *card_name,
547 struct omap_tw4030_pdata *pdata)
548{
549 if (!pdata)
550 pdata = &omap_twl4030_audio_data;
551
552 pdata->card_name = card_name;
553
554 audio_device.dev.platform_data = pdata;
555 platform_device_register(&audio_device);
556}
557
558#else /* SOC_OMAP_TWL4030 */
559void omap_twl4030_audio_init(char *card_name,
560 struct omap_tw4030_pdata *pdata)
561{
562 return;
563}
564#endif /* SOC_OMAP_TWL4030 */
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
deleted file mode 100644
index 24b65d081b69..000000000000
--- a/arch/arm/mach-omap2/twl-common.h
+++ /dev/null
@@ -1,66 +0,0 @@
1#ifndef __OMAP_PMIC_COMMON__
2#define __OMAP_PMIC_COMMON__
3
4#include "common.h"
5
6#define TWL_COMMON_PDATA_USB (1 << 0)
7#define TWL_COMMON_PDATA_BCI (1 << 1)
8#define TWL_COMMON_PDATA_MADC (1 << 2)
9#define TWL_COMMON_PDATA_AUDIO (1 << 3)
10
11/* Common LDO regulators for TWL4030/TWL6030 */
12#define TWL_COMMON_REGULATOR_VDAC (1 << 0)
13#define TWL_COMMON_REGULATOR_VAUX1 (1 << 1)
14#define TWL_COMMON_REGULATOR_VAUX2 (1 << 2)
15#define TWL_COMMON_REGULATOR_VAUX3 (1 << 3)
16
17/* TWL6030 LDO regulators */
18#define TWL_COMMON_REGULATOR_VMMC (1 << 4)
19#define TWL_COMMON_REGULATOR_VPP (1 << 5)
20#define TWL_COMMON_REGULATOR_VUSIM (1 << 6)
21#define TWL_COMMON_REGULATOR_VANA (1 << 7)
22#define TWL_COMMON_REGULATOR_VCXIO (1 << 8)
23#define TWL_COMMON_REGULATOR_VUSB (1 << 9)
24#define TWL_COMMON_REGULATOR_CLK32KG (1 << 10)
25#define TWL_COMMON_REGULATOR_V1V8 (1 << 11)
26#define TWL_COMMON_REGULATOR_V2V1 (1 << 12)
27
28/* TWL4030 LDO regulators */
29#define TWL_COMMON_REGULATOR_VPLL1 (1 << 4)
30#define TWL_COMMON_REGULATOR_VPLL2 (1 << 5)
31
32
33struct twl4030_platform_data;
34struct twl6040_platform_data;
35struct omap_tw4030_pdata;
36struct i2c_board_info;
37
38void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
39 struct twl4030_platform_data *pmic_data);
40void omap_pmic_late_init(void);
41
42static inline void omap2_pmic_init(const char *pmic_type,
43 struct twl4030_platform_data *pmic_data)
44{
45 omap_pmic_init(2, 2600, pmic_type, 7 + OMAP_INTC_START, pmic_data);
46}
47
48static inline void omap3_pmic_init(const char *pmic_type,
49 struct twl4030_platform_data *pmic_data)
50{
51 omap_pmic_init(1, 2600, pmic_type, 7 + OMAP_INTC_START, pmic_data);
52}
53
54void omap4_pmic_init(const char *pmic_type,
55 struct twl4030_platform_data *pmic_data,
56 struct i2c_board_info *devices, int nr_devices);
57
58void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
59 u32 pdata_flags, u32 regulators_flags);
60
61void omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
62 u32 pdata_flags, u32 regulators_flags);
63
64void omap_twl4030_audio_init(char *card_name, struct omap_tw4030_pdata *pdata);
65
66#endif /* __OMAP_PMIC_COMMON__ */
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
deleted file mode 100644
index 745367c0c2bb..000000000000
--- a/arch/arm/mach-omap2/usb-host.c
+++ /dev/null
@@ -1,496 +0,0 @@
1/*
2 * usb-host.c - OMAP USB Host
3 *
4 * This file will contain the board specific details for the
5 * Synopsys EHCI/OHCI host controller on OMAP3430 and onwards
6 *
7 * Copyright (C) 2007-2011 Texas Instruments
8 * Author: Vikram Pandita <vikram.pandita@ti.com>
9 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
10 *
11 * Generalization by:
12 * Felipe Balbi <balbi@ti.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/delay.h>
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24#include <linux/dma-mapping.h>
25#include <linux/regulator/machine.h>
26#include <linux/regulator/fixed.h>
27#include <linux/string.h>
28#include <linux/io.h>
29#include <linux/gpio.h>
30#include <linux/usb/phy.h>
31#include <linux/usb/usb_phy_generic.h>
32
33#include "soc.h"
34#include "omap_device.h"
35#include "mux.h"
36#include "usb.h"
37
38#ifdef CONFIG_MFD_OMAP_USB_HOST
39
40#define OMAP_USBHS_DEVICE "usbhs_omap"
41#define OMAP_USBTLL_DEVICE "usbhs_tll"
42#define USBHS_UHH_HWMODNAME "usb_host_hs"
43#define USBHS_TLL_HWMODNAME "usb_tll_hs"
44
45/* MUX settings for EHCI pins */
46/*
47 * setup_ehci_io_mux - initialize IO pad mux for USBHOST
48 */
49static void __init setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
50{
51 switch (port_mode[0]) {
52 case OMAP_EHCI_PORT_MODE_PHY:
53 omap_mux_init_signal("hsusb1_stp", OMAP_PIN_OUTPUT);
54 omap_mux_init_signal("hsusb1_clk", OMAP_PIN_OUTPUT);
55 omap_mux_init_signal("hsusb1_dir", OMAP_PIN_INPUT_PULLDOWN);
56 omap_mux_init_signal("hsusb1_nxt", OMAP_PIN_INPUT_PULLDOWN);
57 omap_mux_init_signal("hsusb1_data0", OMAP_PIN_INPUT_PULLDOWN);
58 omap_mux_init_signal("hsusb1_data1", OMAP_PIN_INPUT_PULLDOWN);
59 omap_mux_init_signal("hsusb1_data2", OMAP_PIN_INPUT_PULLDOWN);
60 omap_mux_init_signal("hsusb1_data3", OMAP_PIN_INPUT_PULLDOWN);
61 omap_mux_init_signal("hsusb1_data4", OMAP_PIN_INPUT_PULLDOWN);
62 omap_mux_init_signal("hsusb1_data5", OMAP_PIN_INPUT_PULLDOWN);
63 omap_mux_init_signal("hsusb1_data6", OMAP_PIN_INPUT_PULLDOWN);
64 omap_mux_init_signal("hsusb1_data7", OMAP_PIN_INPUT_PULLDOWN);
65 break;
66 case OMAP_EHCI_PORT_MODE_TLL:
67 omap_mux_init_signal("hsusb1_tll_stp",
68 OMAP_PIN_INPUT_PULLUP);
69 omap_mux_init_signal("hsusb1_tll_clk",
70 OMAP_PIN_INPUT_PULLDOWN);
71 omap_mux_init_signal("hsusb1_tll_dir",
72 OMAP_PIN_INPUT_PULLDOWN);
73 omap_mux_init_signal("hsusb1_tll_nxt",
74 OMAP_PIN_INPUT_PULLDOWN);
75 omap_mux_init_signal("hsusb1_tll_data0",
76 OMAP_PIN_INPUT_PULLDOWN);
77 omap_mux_init_signal("hsusb1_tll_data1",
78 OMAP_PIN_INPUT_PULLDOWN);
79 omap_mux_init_signal("hsusb1_tll_data2",
80 OMAP_PIN_INPUT_PULLDOWN);
81 omap_mux_init_signal("hsusb1_tll_data3",
82 OMAP_PIN_INPUT_PULLDOWN);
83 omap_mux_init_signal("hsusb1_tll_data4",
84 OMAP_PIN_INPUT_PULLDOWN);
85 omap_mux_init_signal("hsusb1_tll_data5",
86 OMAP_PIN_INPUT_PULLDOWN);
87 omap_mux_init_signal("hsusb1_tll_data6",
88 OMAP_PIN_INPUT_PULLDOWN);
89 omap_mux_init_signal("hsusb1_tll_data7",
90 OMAP_PIN_INPUT_PULLDOWN);
91 break;
92 case OMAP_USBHS_PORT_MODE_UNUSED:
93 /* FALLTHROUGH */
94 default:
95 break;
96 }
97
98 switch (port_mode[1]) {
99 case OMAP_EHCI_PORT_MODE_PHY:
100 omap_mux_init_signal("hsusb2_stp", OMAP_PIN_OUTPUT);
101 omap_mux_init_signal("hsusb2_clk", OMAP_PIN_OUTPUT);
102 omap_mux_init_signal("hsusb2_dir", OMAP_PIN_INPUT_PULLDOWN);
103 omap_mux_init_signal("hsusb2_nxt", OMAP_PIN_INPUT_PULLDOWN);
104 omap_mux_init_signal("hsusb2_data0",
105 OMAP_PIN_INPUT_PULLDOWN);
106 omap_mux_init_signal("hsusb2_data1",
107 OMAP_PIN_INPUT_PULLDOWN);
108 omap_mux_init_signal("hsusb2_data2",
109 OMAP_PIN_INPUT_PULLDOWN);
110 omap_mux_init_signal("hsusb2_data3",
111 OMAP_PIN_INPUT_PULLDOWN);
112 omap_mux_init_signal("hsusb2_data4",
113 OMAP_PIN_INPUT_PULLDOWN);
114 omap_mux_init_signal("hsusb2_data5",
115 OMAP_PIN_INPUT_PULLDOWN);
116 omap_mux_init_signal("hsusb2_data6",
117 OMAP_PIN_INPUT_PULLDOWN);
118 omap_mux_init_signal("hsusb2_data7",
119 OMAP_PIN_INPUT_PULLDOWN);
120 break;
121 case OMAP_EHCI_PORT_MODE_TLL:
122 omap_mux_init_signal("hsusb2_tll_stp",
123 OMAP_PIN_INPUT_PULLUP);
124 omap_mux_init_signal("hsusb2_tll_clk",
125 OMAP_PIN_INPUT_PULLDOWN);
126 omap_mux_init_signal("hsusb2_tll_dir",
127 OMAP_PIN_INPUT_PULLDOWN);
128 omap_mux_init_signal("hsusb2_tll_nxt",
129 OMAP_PIN_INPUT_PULLDOWN);
130 omap_mux_init_signal("hsusb2_tll_data0",
131 OMAP_PIN_INPUT_PULLDOWN);
132 omap_mux_init_signal("hsusb2_tll_data1",
133 OMAP_PIN_INPUT_PULLDOWN);
134 omap_mux_init_signal("hsusb2_tll_data2",
135 OMAP_PIN_INPUT_PULLDOWN);
136 omap_mux_init_signal("hsusb2_tll_data3",
137 OMAP_PIN_INPUT_PULLDOWN);
138 omap_mux_init_signal("hsusb2_tll_data4",
139 OMAP_PIN_INPUT_PULLDOWN);
140 omap_mux_init_signal("hsusb2_tll_data5",
141 OMAP_PIN_INPUT_PULLDOWN);
142 omap_mux_init_signal("hsusb2_tll_data6",
143 OMAP_PIN_INPUT_PULLDOWN);
144 omap_mux_init_signal("hsusb2_tll_data7",
145 OMAP_PIN_INPUT_PULLDOWN);
146 break;
147 case OMAP_USBHS_PORT_MODE_UNUSED:
148 /* FALLTHROUGH */
149 default:
150 break;
151 }
152
153 switch (port_mode[2]) {
154 case OMAP_EHCI_PORT_MODE_PHY:
155 printk(KERN_WARNING "Port3 can't be used in PHY mode\n");
156 break;
157 case OMAP_EHCI_PORT_MODE_TLL:
158 omap_mux_init_signal("hsusb3_tll_stp",
159 OMAP_PIN_INPUT_PULLUP);
160 omap_mux_init_signal("hsusb3_tll_clk",
161 OMAP_PIN_INPUT_PULLDOWN);
162 omap_mux_init_signal("hsusb3_tll_dir",
163 OMAP_PIN_INPUT_PULLDOWN);
164 omap_mux_init_signal("hsusb3_tll_nxt",
165 OMAP_PIN_INPUT_PULLDOWN);
166 omap_mux_init_signal("hsusb3_tll_data0",
167 OMAP_PIN_INPUT_PULLDOWN);
168 omap_mux_init_signal("hsusb3_tll_data1",
169 OMAP_PIN_INPUT_PULLDOWN);
170 omap_mux_init_signal("hsusb3_tll_data2",
171 OMAP_PIN_INPUT_PULLDOWN);
172 omap_mux_init_signal("hsusb3_tll_data3",
173 OMAP_PIN_INPUT_PULLDOWN);
174 omap_mux_init_signal("hsusb3_tll_data4",
175 OMAP_PIN_INPUT_PULLDOWN);
176 omap_mux_init_signal("hsusb3_tll_data5",
177 OMAP_PIN_INPUT_PULLDOWN);
178 omap_mux_init_signal("hsusb3_tll_data6",
179 OMAP_PIN_INPUT_PULLDOWN);
180 omap_mux_init_signal("hsusb3_tll_data7",
181 OMAP_PIN_INPUT_PULLDOWN);
182 break;
183 case OMAP_USBHS_PORT_MODE_UNUSED:
184 /* FALLTHROUGH */
185 default:
186 break;
187 }
188
189 return;
190}
191
192static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
193{
194 switch (port_mode[0]) {
195 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
196 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
197 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
198 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
199 omap_mux_init_signal("mm1_rxdp",
200 OMAP_PIN_INPUT_PULLDOWN);
201 omap_mux_init_signal("mm1_rxdm",
202 OMAP_PIN_INPUT_PULLDOWN);
203 /* FALLTHROUGH */
204 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
205 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
206 omap_mux_init_signal("mm1_rxrcv",
207 OMAP_PIN_INPUT_PULLDOWN);
208 /* FALLTHROUGH */
209 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
210 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
211 omap_mux_init_signal("mm1_txen_n", OMAP_PIN_OUTPUT);
212 /* FALLTHROUGH */
213 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
214 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
215 omap_mux_init_signal("mm1_txse0",
216 OMAP_PIN_INPUT_PULLDOWN);
217 omap_mux_init_signal("mm1_txdat",
218 OMAP_PIN_INPUT_PULLDOWN);
219 break;
220 case OMAP_USBHS_PORT_MODE_UNUSED:
221 /* FALLTHROUGH */
222 default:
223 break;
224 }
225 switch (port_mode[1]) {
226 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
227 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
228 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
229 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
230 omap_mux_init_signal("mm2_rxdp",
231 OMAP_PIN_INPUT_PULLDOWN);
232 omap_mux_init_signal("mm2_rxdm",
233 OMAP_PIN_INPUT_PULLDOWN);
234 /* FALLTHROUGH */
235 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
236 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
237 omap_mux_init_signal("mm2_rxrcv",
238 OMAP_PIN_INPUT_PULLDOWN);
239 /* FALLTHROUGH */
240 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
241 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
242 omap_mux_init_signal("mm2_txen_n", OMAP_PIN_OUTPUT);
243 /* FALLTHROUGH */
244 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
245 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
246 omap_mux_init_signal("mm2_txse0",
247 OMAP_PIN_INPUT_PULLDOWN);
248 omap_mux_init_signal("mm2_txdat",
249 OMAP_PIN_INPUT_PULLDOWN);
250 break;
251 case OMAP_USBHS_PORT_MODE_UNUSED:
252 /* FALLTHROUGH */
253 default:
254 break;
255 }
256 switch (port_mode[2]) {
257 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
258 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
259 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
260 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
261 omap_mux_init_signal("mm3_rxdp",
262 OMAP_PIN_INPUT_PULLDOWN);
263 omap_mux_init_signal("mm3_rxdm",
264 OMAP_PIN_INPUT_PULLDOWN);
265 /* FALLTHROUGH */
266 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
267 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
268 omap_mux_init_signal("mm3_rxrcv",
269 OMAP_PIN_INPUT_PULLDOWN);
270 /* FALLTHROUGH */
271 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
272 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
273 omap_mux_init_signal("mm3_txen_n", OMAP_PIN_OUTPUT);
274 /* FALLTHROUGH */
275 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
276 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
277 omap_mux_init_signal("mm3_txse0",
278 OMAP_PIN_INPUT_PULLDOWN);
279 omap_mux_init_signal("mm3_txdat",
280 OMAP_PIN_INPUT_PULLDOWN);
281 break;
282 case OMAP_USBHS_PORT_MODE_UNUSED:
283 /* FALLTHROUGH */
284 default:
285 break;
286 }
287}
288
289void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
290{
291 struct omap_hwmod *uhh_hwm, *tll_hwm;
292 struct platform_device *pdev;
293 int bus_id = -1;
294
295 if (cpu_is_omap34xx()) {
296 setup_ehci_io_mux(pdata->port_mode);
297 setup_ohci_io_mux(pdata->port_mode);
298
299 if (omap_rev() <= OMAP3430_REV_ES2_1)
300 pdata->single_ulpi_bypass = true;
301
302 }
303
304 uhh_hwm = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
305 if (!uhh_hwm) {
306 pr_err("Could not look up %s\n", USBHS_UHH_HWMODNAME);
307 return;
308 }
309
310 tll_hwm = omap_hwmod_lookup(USBHS_TLL_HWMODNAME);
311 if (!tll_hwm) {
312 pr_err("Could not look up %s\n", USBHS_TLL_HWMODNAME);
313 return;
314 }
315
316 pdev = omap_device_build(OMAP_USBTLL_DEVICE, bus_id, tll_hwm,
317 pdata, sizeof(*pdata));
318 if (IS_ERR(pdev)) {
319 pr_err("Could not build hwmod device %s\n",
320 USBHS_TLL_HWMODNAME);
321 return;
322 }
323
324 pdev = omap_device_build(OMAP_USBHS_DEVICE, bus_id, uhh_hwm,
325 pdata, sizeof(*pdata));
326 if (IS_ERR(pdev)) {
327 pr_err("Could not build hwmod devices %s\n",
328 USBHS_UHH_HWMODNAME);
329 return;
330 }
331}
332
333#else
334
335void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
336{
337}
338
339#endif
340
341/* Template for PHY regulators */
342static struct fixed_voltage_config hsusb_reg_config = {
343 /* .supply_name filled later */
344 .microvolts = 3300000,
345 .gpio = -1, /* updated later */
346 .startup_delay = 70000, /* 70msec */
347 .enable_high = 1, /* updated later */
348 .enabled_at_boot = 0, /* keep in RESET */
349 /* .init_data filled later */
350};
351
352static const char *nop_name = "usb_phy_generic"; /* NOP PHY driver */
353static const char *reg_name = "reg-fixed-voltage"; /* Regulator driver */
354
355/**
356 * usbhs_add_regulator - Add a gpio based fixed voltage regulator device
357 * @name: name for the regulator
358 * @dev_id: device id of the device this regulator supplies power to
359 * @dev_supply: supply name that the device expects
360 * @gpio: GPIO number
361 * @polarity: 1 - Active high, 0 - Active low
362 */
363static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
364 int gpio, int polarity)
365{
366 struct regulator_consumer_supply *supplies;
367 struct regulator_init_data *reg_data;
368 struct fixed_voltage_config *config;
369 struct platform_device *pdev;
370 struct platform_device_info pdevinfo;
371 int ret = -ENOMEM;
372
373 supplies = kzalloc(sizeof(*supplies), GFP_KERNEL);
374 if (!supplies)
375 return -ENOMEM;
376
377 supplies->supply = dev_supply;
378 supplies->dev_name = dev_id;
379
380 reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
381 if (!reg_data)
382 goto err_data;
383
384 reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
385 reg_data->consumer_supplies = supplies;
386 reg_data->num_consumer_supplies = 1;
387
388 config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
389 GFP_KERNEL);
390 if (!config)
391 goto err_config;
392
393 config->supply_name = kstrdup(name, GFP_KERNEL);
394 if (!config->supply_name)
395 goto err_supplyname;
396
397 config->gpio = gpio;
398 config->enable_high = polarity;
399 config->init_data = reg_data;
400
401 /* create a regulator device */
402 memset(&pdevinfo, 0, sizeof(pdevinfo));
403 pdevinfo.name = reg_name;
404 pdevinfo.id = PLATFORM_DEVID_AUTO;
405 pdevinfo.data = config;
406 pdevinfo.size_data = sizeof(*config);
407
408 pdev = platform_device_register_full(&pdevinfo);
409 if (IS_ERR(pdev)) {
410 ret = PTR_ERR(pdev);
411 pr_err("%s: Failed registering regulator %s for %s : %d\n",
412 __func__, name, dev_id, ret);
413 goto err_register;
414 }
415
416 return 0;
417
418err_register:
419 kfree(config->supply_name);
420err_supplyname:
421 kfree(config);
422err_config:
423 kfree(reg_data);
424err_data:
425 kfree(supplies);
426 return ret;
427}
428
429#define MAX_STR 20
430
431int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
432{
433 char rail_name[MAX_STR];
434 int i;
435 struct platform_device *pdev;
436 char *phy_id;
437 struct platform_device_info pdevinfo;
438 struct usb_phy_generic_platform_data nop_pdata;
439
440 for (i = 0; i < num_phys; i++) {
441
442 if (!phy->port) {
443 pr_err("%s: Invalid port 0. Must start from 1\n",
444 __func__);
445 continue;
446 }
447
448 /* do we need a NOP PHY device ? */
449 if (!gpio_is_valid(phy->reset_gpio) &&
450 !gpio_is_valid(phy->vcc_gpio))
451 continue;
452
453 phy_id = kmalloc(MAX_STR, GFP_KERNEL);
454 if (!phy_id) {
455 pr_err("%s: kmalloc() failed\n", __func__);
456 return -ENOMEM;
457 }
458
459 /* set platform data */
460 memset(&nop_pdata, 0, sizeof(nop_pdata));
461 if (gpio_is_valid(phy->vcc_gpio))
462 nop_pdata.needs_vcc = true;
463 nop_pdata.gpio_reset = phy->reset_gpio;
464 nop_pdata.type = USB_PHY_TYPE_USB2;
465
466 /* create a NOP PHY device */
467 memset(&pdevinfo, 0, sizeof(pdevinfo));
468 pdevinfo.name = nop_name;
469 pdevinfo.id = phy->port;
470 pdevinfo.data = &nop_pdata;
471 pdevinfo.size_data =
472 sizeof(struct usb_phy_generic_platform_data);
473 scnprintf(phy_id, MAX_STR, "usb_phy_generic.%d",
474 phy->port);
475 pdev = platform_device_register_full(&pdevinfo);
476 if (IS_ERR(pdev)) {
477 pr_err("%s: Failed to register device %s : %ld\n",
478 __func__, phy_id, PTR_ERR(pdev));
479 kfree(phy_id);
480 continue;
481 }
482
483 usb_bind_phy("ehci-omap.0", phy->port - 1, phy_id);
484
485 /* Do we need VCC regulator ? */
486 if (gpio_is_valid(phy->vcc_gpio)) {
487 scnprintf(rail_name, MAX_STR, "hsusb%d_vcc", phy->port);
488 usbhs_add_regulator(rail_name, phy_id, "vcc",
489 phy->vcc_gpio, phy->vcc_polarity);
490 }
491
492 phy++;
493 }
494
495 return 0;
496}
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
deleted file mode 100644
index e4562b2b973b..000000000000
--- a/arch/arm/mach-omap2/usb-musb.c
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/usb-musb.c
3 *
4 * This file will contain the board specific details for the
5 * MENTOR USB OTG controller on OMAP3430
6 *
7 * Copyright (C) 2007-2008 Texas Instruments
8 * Copyright (C) 2008 Nokia Corporation
9 * Author: Vikram Pandita
10 *
11 * Generalization by:
12 * Felipe Balbi <felipe.balbi@nokia.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/delay.h>
22#include <linux/platform_device.h>
23#include <linux/clk.h>
24#include <linux/dma-mapping.h>
25#include <linux/io.h>
26#include <linux/usb/musb.h>
27
28#include "omap_device.h"
29#include "soc.h"
30#include "mux.h"
31#include "usb.h"
32
33static struct musb_hdrc_config musb_config = {
34 .multipoint = 1,
35 .dyn_fifo = 1,
36 .num_eps = 16,
37 .ram_bits = 12,
38};
39
40static struct musb_hdrc_platform_data musb_plat = {
41 .mode = MUSB_OTG,
42
43 /* .clock is set dynamically */
44 .config = &musb_config,
45
46 /* REVISIT charge pump on TWL4030 can supply up to
47 * 100 mA ... but this value is board-specific, like
48 * "mode", and should be passed to usb_musb_init().
49 */
50 .power = 50, /* up to 100 mA */
51};
52
53static u64 musb_dmamask = DMA_BIT_MASK(32);
54
55static struct omap_musb_board_data musb_default_board_data = {
56 .interface_type = MUSB_INTERFACE_ULPI,
57 .mode = MUSB_OTG,
58 .power = 100,
59};
60
61void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
62{
63 struct omap_hwmod *oh;
64 struct platform_device *pdev;
65 struct device *dev;
66 int bus_id = -1;
67 const char *oh_name, *name;
68 struct omap_musb_board_data *board_data;
69
70 if (musb_board_data)
71 board_data = musb_board_data;
72 else
73 board_data = &musb_default_board_data;
74
75 /*
76 * REVISIT: This line can be removed once all the platforms using
77 * musb_core.c have been converted to use use clkdev.
78 */
79 musb_plat.clock = "ick";
80 musb_plat.board_data = board_data;
81 musb_plat.power = board_data->power >> 1;
82 musb_plat.mode = board_data->mode;
83 musb_plat.extvbus = board_data->extvbus;
84
85 oh_name = "usb_otg_hs";
86 name = "musb-omap2430";
87
88 oh = omap_hwmod_lookup(oh_name);
89 if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
90 __func__, oh_name))
91 return;
92
93 pdev = omap_device_build(name, bus_id, oh, &musb_plat,
94 sizeof(musb_plat));
95 if (IS_ERR(pdev)) {
96 pr_err("Could not build omap_device for %s %s\n",
97 name, oh_name);
98 return;
99 }
100
101 dev = &pdev->dev;
102 get_device(dev);
103 dev->dma_mask = &musb_dmamask;
104 dev->coherent_dma_mask = musb_dmamask;
105 put_device(dev);
106}
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index e554d9e66a1c..c2a6fbd7f8a9 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -22,8 +22,6 @@
22 22
23#include "gpmc.h" 23#include "gpmc.h"
24 24
25#include "mux.h"
26
27static u8 async_cs, sync_cs; 25static u8 async_cs, sync_cs;
28static unsigned refclk_psec; 26static unsigned refclk_psec;
29 27
@@ -226,25 +224,6 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
226 } 224 }
227 tusb_device.dev.platform_data = data; 225 tusb_device.dev.platform_data = data;
228 226
229 /* REVISIT let the driver know what DMA channels work */
230 if (!dmachan)
231 tusb_device.dev.dma_mask = NULL;
232 else {
233 /* assume OMAP 2420 ES2.0 and later */
234 if (dmachan & (1 << 0))
235 omap_mux_init_signal("sys_ndmareq0", 0);
236 if (dmachan & (1 << 1))
237 omap_mux_init_signal("sys_ndmareq1", 0);
238 if (dmachan & (1 << 2))
239 omap_mux_init_signal("sys_ndmareq2", 0);
240 if (dmachan & (1 << 3))
241 omap_mux_init_signal("sys_ndmareq3", 0);
242 if (dmachan & (1 << 4))
243 omap_mux_init_signal("sys_ndmareq4", 0);
244 if (dmachan & (1 << 5))
245 omap_mux_init_signal("sys_ndmareq5", 0);
246 }
247
248 /* so far so good ... register the device */ 227 /* so far so good ... register the device */
249 status = platform_device_register(&tusb_device); 228 status = platform_device_register(&tusb_device);
250 if (status < 0) { 229 if (status < 0) {
diff --git a/arch/arm/mach-oxnas/Kconfig b/arch/arm/mach-oxnas/Kconfig
index 29100beb2e7f..8fa4557e27a9 100644
--- a/arch/arm/mach-oxnas/Kconfig
+++ b/arch/arm/mach-oxnas/Kconfig
@@ -1,9 +1,16 @@
1menuconfig ARCH_OXNAS 1menuconfig ARCH_OXNAS
2 bool "Oxford Semiconductor OXNAS Family SoCs" 2 bool "Oxford Semiconductor OXNAS Family SoCs"
3 select ARCH_HAS_RESET_CONTROLLER 3 select ARCH_HAS_RESET_CONTROLLER
4 select COMMON_CLK_OXNAS
4 select GPIOLIB 5 select GPIOLIB
6 select MFD_SYSCON
7 select OXNAS_RPS_TIMER
8 select PINCTRL_OXNAS
9 select RESET_CONTROLLER
10 select RESET_OXNAS
11 select VERSATILE_FPGA_IRQ
5 select PINCTRL 12 select PINCTRL
6 depends on ARCH_MULTI_V5 13 depends on ARCH_MULTI_V5 || ARCH_MULTI_V6
7 help 14 help
8 Support for OxNas SoC family developed by Oxford Semiconductor. 15 Support for OxNas SoC family developed by Oxford Semiconductor.
9 16
@@ -11,16 +18,21 @@ if ARCH_OXNAS
11 18
12config MACH_OX810SE 19config MACH_OX810SE
13 bool "Support OX810SE Based Products" 20 bool "Support OX810SE Based Products"
14 select ARCH_HAS_RESET_CONTROLLER 21 depends on ARCH_MULTI_V5
15 select COMMON_CLK_OXNAS
16 select CPU_ARM926T 22 select CPU_ARM926T
17 select MFD_SYSCON
18 select OXNAS_RPS_TIMER
19 select PINCTRL_OXNAS
20 select RESET_CONTROLLER
21 select RESET_OXNAS
22 select VERSATILE_FPGA_IRQ
23 help 23 help
24 Include Support for the Oxford Semiconductor OX810SE SoC Based Products. 24 Include Support for the Oxford Semiconductor OX810SE SoC Based Products.
25 25
26config MACH_OX820
27 bool "Support OX820 Based Products"
28 depends on ARCH_MULTI_V6
29 select ARM_GIC
30 select DMA_CACHE_RWFO if SMP
31 select CPU_V6K
32 select HAVE_SMP
33 select HAVE_ARM_SCU if SMP
34 select HAVE_ARM_TWD if SMP
35 help
36 Include Support for the Oxford Semiconductor OX820 SoC Based Products.
37
26endif 38endif
diff --git a/arch/arm/mach-oxnas/Makefile b/arch/arm/mach-oxnas/Makefile
new file mode 100644
index 000000000000..b625906a9970
--- /dev/null
+++ b/arch/arm/mach-oxnas/Makefile
@@ -0,0 +1,2 @@
1obj-$(CONFIG_SMP) += platsmp.o headsmp.o
2obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-oxnas/headsmp.S b/arch/arm/mach-oxnas/headsmp.S
new file mode 100644
index 000000000000..25fd4f82ab3a
--- /dev/null
+++ b/arch/arm/mach-oxnas/headsmp.S
@@ -0,0 +1,26 @@
1/*
2 * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
3 * Copyright (c) 2003 ARM Limited
4 * All Rights Reserved
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <linux/init.h>
12
13 __INIT
14
15/*
16 * OX820 specific entry point for secondary CPUs.
17 */
18ENTRY(ox820_secondary_startup)
19 mov r4, #0
20 /* invalidate both caches and branch target cache */
21 mcr p15, 0, r4, c7, c7, 0
22 /*
23 * we've been released from the holding pen: secondary_stack
24 * should now contain the SVC stack for this core
25 */
26 b secondary_startup
diff --git a/arch/arm/mach-oxnas/hotplug.c b/arch/arm/mach-oxnas/hotplug.c
new file mode 100644
index 000000000000..854f29b8cba6
--- /dev/null
+++ b/arch/arm/mach-oxnas/hotplug.c
@@ -0,0 +1,109 @@
1/*
2 * Copyright (C) 2002 ARM Ltd.
3 * All Rights Reserved
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/kernel.h>
10#include <linux/errno.h>
11#include <linux/smp.h>
12
13#include <asm/cp15.h>
14#include <asm/smp_plat.h>
15
16static inline void cpu_enter_lowpower(void)
17{
18 unsigned int v;
19
20 asm volatile(
21 " mcr p15, 0, %1, c7, c5, 0\n"
22 " mcr p15, 0, %1, c7, c10, 4\n"
23 /*
24 * Turn off coherency
25 */
26 " mrc p15, 0, %0, c1, c0, 1\n"
27 " bic %0, %0, #0x20\n"
28 " mcr p15, 0, %0, c1, c0, 1\n"
29 " mrc p15, 0, %0, c1, c0, 0\n"
30 " bic %0, %0, %2\n"
31 " mcr p15, 0, %0, c1, c0, 0\n"
32 : "=&r" (v)
33 : "r" (0), "Ir" (CR_C)
34 : "cc");
35}
36
37static inline void cpu_leave_lowpower(void)
38{
39 unsigned int v;
40
41 asm volatile( "mrc p15, 0, %0, c1, c0, 0\n"
42 " orr %0, %0, %1\n"
43 " mcr p15, 0, %0, c1, c0, 0\n"
44 " mrc p15, 0, %0, c1, c0, 1\n"
45 " orr %0, %0, #0x20\n"
46 " mcr p15, 0, %0, c1, c0, 1\n"
47 : "=&r" (v)
48 : "Ir" (CR_C)
49 : "cc");
50}
51
52static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
53{
54 /*
55 * there is no power-control hardware on this platform, so all
56 * we can do is put the core into WFI; this is safe as the calling
57 * code will have already disabled interrupts
58 */
59 for (;;) {
60 /*
61 * here's the WFI
62 */
63 asm(".word 0xe320f003\n"
64 :
65 :
66 : "memory", "cc");
67
68 if (pen_release == cpu_logical_map(cpu)) {
69 /*
70 * OK, proper wakeup, we're done
71 */
72 break;
73 }
74
75 /*
76 * Getting here, means that we have come out of WFI without
77 * having been woken up - this shouldn't happen
78 *
79 * Just note it happening - when we're woken, we can report
80 * its occurrence.
81 */
82 (*spurious)++;
83 }
84}
85
86/*
87 * platform-specific code to shutdown a CPU
88 *
89 * Called with IRQs disabled
90 */
91void ox820_cpu_die(unsigned int cpu)
92{
93 int spurious = 0;
94
95 /*
96 * we're ready for shutdown now, so do it
97 */
98 cpu_enter_lowpower();
99 platform_do_lowpower(cpu, &spurious);
100
101 /*
102 * bring this CPU back into the world of cache
103 * coherency, and then restore interrupts
104 */
105 cpu_leave_lowpower();
106
107 if (spurious)
108 pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
109}
diff --git a/arch/arm/mach-oxnas/platsmp.c b/arch/arm/mach-oxnas/platsmp.c
new file mode 100644
index 000000000000..442cc8a2f7dc
--- /dev/null
+++ b/arch/arm/mach-oxnas/platsmp.c
@@ -0,0 +1,102 @@
1/*
2 * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
3 * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
4 * Copyright (C) 2002 ARM Ltd.
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/io.h>
12#include <linux/delay.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15
16#include <asm/cacheflush.h>
17#include <asm/cp15.h>
18#include <asm/smp_plat.h>
19#include <asm/smp_scu.h>
20
21extern void ox820_secondary_startup(void);
22extern void ox820_cpu_die(unsigned int cpu);
23
24static void __iomem *cpu_ctrl;
25static void __iomem *gic_cpu_ctrl;
26
27#define HOLDINGPEN_CPU_OFFSET 0xc8
28#define HOLDINGPEN_LOCATION_OFFSET 0xc4
29
30#define GIC_NCPU_OFFSET(cpu) (0x100 + (cpu)*0x100)
31#define GIC_CPU_CTRL 0x00
32#define GIC_CPU_CTRL_ENABLE 1
33
34int __init ox820_boot_secondary(unsigned int cpu, struct task_struct *idle)
35{
36 /*
37 * Write the address of secondary startup into the
38 * system-wide flags register. The BootMonitor waits
39 * until it receives a soft interrupt, and then the
40 * secondary CPU branches to this address.
41 */
42 writel(virt_to_phys(ox820_secondary_startup),
43 cpu_ctrl + HOLDINGPEN_LOCATION_OFFSET);
44
45 writel(cpu, cpu_ctrl + HOLDINGPEN_CPU_OFFSET);
46
47 /*
48 * Enable GIC cpu interface in CPU Interface Control Register
49 */
50 writel(GIC_CPU_CTRL_ENABLE,
51 gic_cpu_ctrl + GIC_NCPU_OFFSET(cpu) + GIC_CPU_CTRL);
52
53 /*
54 * Send the secondary CPU a soft interrupt, thereby causing
55 * the boot monitor to read the system wide flags register,
56 * and branch to the address found there.
57 */
58 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
59
60 return 0;
61}
62
63static void __init ox820_smp_prepare_cpus(unsigned int max_cpus)
64{
65 struct device_node *np;
66 void __iomem *scu_base;
67
68 np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-scu");
69 scu_base = of_iomap(np, 0);
70 of_node_put(np);
71 if (!scu_base)
72 return;
73
74 /* Remap CPU Interrupt Interface Registers */
75 np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-gic");
76 gic_cpu_ctrl = of_iomap(np, 1);
77 of_node_put(np);
78 if (!gic_cpu_ctrl)
79 goto unmap_scu;
80
81 np = of_find_compatible_node(NULL, NULL, "oxsemi,ox820-sys-ctrl");
82 cpu_ctrl = of_iomap(np, 0);
83 of_node_put(np);
84 if (!cpu_ctrl)
85 goto unmap_scu;
86
87 scu_enable(scu_base);
88 flush_cache_all();
89
90unmap_scu:
91 iounmap(scu_base);
92}
93
94static const struct smp_operations ox820_smp_ops __initconst = {
95 .smp_prepare_cpus = ox820_smp_prepare_cpus,
96 .smp_boot_secondary = ox820_boot_secondary,
97#ifdef CONFIG_HOTPLUG_CPU
98 .cpu_die = ox820_cpu_die,
99#endif
100};
101
102CPU_METHOD_OF_DECLARE(ox820_smp, "oxsemi,ox820-smp", &ox820_smp_ops);
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 10bfdb169366..183cd3446f25 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -35,7 +35,6 @@
35#include <linux/mtd/sharpsl.h> 35#include <linux/mtd/sharpsl.h>
36#include <linux/input/matrix_keypad.h> 36#include <linux/input/matrix_keypad.h>
37#include <linux/gpio_keys.h> 37#include <linux/gpio_keys.h>
38#include <linux/module.h>
39#include <linux/memblock.h> 38#include <linux/memblock.h>
40#include <video/w100fb.h> 39#include <video/w100fb.h>
41 40
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 03354c21e1f2..811a7317f3ea 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -23,6 +23,7 @@
23#include <linux/gpio.h> 23#include <linux/gpio.h>
24#include <linux/mfd/da903x.h> 24#include <linux/mfd/da903x.h>
25#include <linux/regulator/machine.h> 25#include <linux/regulator/machine.h>
26#include <linux/regulator/fixed.h>
26#include <linux/spi/spi.h> 27#include <linux/spi/spi.h>
27#include <linux/spi/tdo24m.h> 28#include <linux/spi/tdo24m.h>
28#include <linux/spi/libertas_spi.h> 29#include <linux/spi/libertas_spi.h>
@@ -34,8 +35,6 @@
34#include <linux/i2c/pxa-i2c.h> 35#include <linux/i2c/pxa-i2c.h>
35#include <linux/regulator/userspace-consumer.h> 36#include <linux/regulator/userspace-consumer.h>
36 37
37#include <media/soc_camera.h>
38
39#include <asm/mach-types.h> 38#include <asm/mach-types.h>
40#include <asm/mach/arch.h> 39#include <asm/mach/arch.h>
41 40
@@ -958,8 +957,6 @@ static inline void em_x270_init_gpio_keys(void) {}
958 957
959/* Quick Capture Interface and sensor setup */ 958/* Quick Capture Interface and sensor setup */
960#if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE) 959#if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE)
961static struct regulator *em_x270_camera_ldo;
962
963static int em_x270_sensor_init(void) 960static int em_x270_sensor_init(void)
964{ 961{
965 int ret; 962 int ret;
@@ -969,81 +966,53 @@ static int em_x270_sensor_init(void)
969 return ret; 966 return ret;
970 967
971 gpio_direction_output(cam_reset, 0); 968 gpio_direction_output(cam_reset, 0);
972
973 em_x270_camera_ldo = regulator_get(NULL, "vcc cam");
974 if (em_x270_camera_ldo == NULL) {
975 gpio_free(cam_reset);
976 return -ENODEV;
977 }
978
979 ret = regulator_enable(em_x270_camera_ldo);
980 if (ret) {
981 regulator_put(em_x270_camera_ldo);
982 gpio_free(cam_reset);
983 return ret;
984 }
985
986 gpio_set_value(cam_reset, 1); 969 gpio_set_value(cam_reset, 1);
987 970
988 return 0; 971 return 0;
989} 972}
990 973
991struct pxacamera_platform_data em_x270_camera_platform_data = { 974static struct regulator_consumer_supply camera_dummy_supplies[] = {
992 .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | 975 REGULATOR_SUPPLY("vdd", "0-005d"),
993 PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN,
994 .mclk_10khz = 2600,
995}; 976};
996 977
997static int em_x270_sensor_power(struct device *dev, int on) 978static struct regulator_init_data camera_dummy_initdata = {
998{ 979 .consumer_supplies = camera_dummy_supplies,
999 int ret; 980 .num_consumer_supplies = ARRAY_SIZE(camera_dummy_supplies),
1000 int is_on = regulator_is_enabled(em_x270_camera_ldo); 981 .constraints = {
1001 982 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1002 if (on == is_on)
1003 return 0;
1004
1005 gpio_set_value(cam_reset, !on);
1006
1007 if (on)
1008 ret = regulator_enable(em_x270_camera_ldo);
1009 else
1010 ret = regulator_disable(em_x270_camera_ldo);
1011
1012 if (ret)
1013 return ret;
1014
1015 gpio_set_value(cam_reset, on);
1016
1017 return 0;
1018}
1019
1020static struct i2c_board_info em_x270_i2c_cam_info[] = {
1021 {
1022 I2C_BOARD_INFO("mt9m111", 0x48),
1023 }, 983 },
1024}; 984};
1025 985
1026static struct soc_camera_link iclink = { 986static struct fixed_voltage_config camera_dummy_config = {
1027 .bus_id = 0, 987 .supply_name = "camera_vdd",
1028 .power = em_x270_sensor_power, 988 .input_supply = "vcc cam",
1029 .board_info = &em_x270_i2c_cam_info[0], 989 .microvolts = 2800000,
1030 .i2c_adapter_id = 0, 990 .gpio = -1,
991 .enable_high = 0,
992 .init_data = &camera_dummy_initdata,
1031}; 993};
1032 994
1033static struct platform_device em_x270_camera = { 995static struct platform_device camera_supply_dummy_device = {
1034 .name = "soc-camera-pdrv", 996 .name = "reg-fixed-voltage",
1035 .id = -1, 997 .id = 1,
1036 .dev = { 998 .dev = {
1037 .platform_data = &iclink, 999 .platform_data = &camera_dummy_config,
1038 }, 1000 },
1039}; 1001};
1040 1002
1003struct pxacamera_platform_data em_x270_camera_platform_data = {
1004 .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 |
1005 PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN,
1006 .mclk_10khz = 2600,
1007 .sensor_i2c_adapter_id = 0,
1008 .sensor_i2c_address = 0x5d,
1009};
1010
1041static void __init em_x270_init_camera(void) 1011static void __init em_x270_init_camera(void)
1042{ 1012{
1043 if (em_x270_sensor_init() == 0) { 1013 if (em_x270_sensor_init() == 0)
1044 pxa_set_camera_info(&em_x270_camera_platform_data); 1014 pxa_set_camera_info(&em_x270_camera_platform_data);
1045 platform_device_register(&em_x270_camera); 1015 platform_device_register(&camera_supply_dummy_device);
1046 }
1047} 1016}
1048#else 1017#else
1049static inline void em_x270_init_camera(void) {} 1018static inline void em_x270_init_camera(void) {}
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index 34ad0a89d4a9..0b8300e6fca3 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -17,14 +17,14 @@
17#include <linux/delay.h> 17#include <linux/delay.h>
18#include <linux/pwm.h> 18#include <linux/pwm.h>
19#include <linux/pwm_backlight.h> 19#include <linux/pwm_backlight.h>
20#include <linux/regulator/machine.h>
21#include <linux/regulator/fixed.h>
20#include <linux/input.h> 22#include <linux/input.h>
21#include <linux/gpio.h> 23#include <linux/gpio.h>
22#include <linux/gpio_keys.h> 24#include <linux/gpio_keys.h>
23#include <linux/leds-lp3944.h> 25#include <linux/leds-lp3944.h>
24#include <linux/i2c/pxa-i2c.h> 26#include <linux/i2c/pxa-i2c.h>
25 27
26#include <media/soc_camera.h>
27
28#include <asm/setup.h> 28#include <asm/setup.h>
29#include <asm/mach-types.h> 29#include <asm/mach-types.h>
30#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
@@ -723,6 +723,42 @@ static struct platform_device a780_gpio_keys = {
723}; 723};
724 724
725/* camera */ 725/* camera */
726static struct regulator_consumer_supply camera_dummy_supplies[] = {
727 REGULATOR_SUPPLY("vdd", "0-005d"),
728};
729
730static struct regulator_init_data camera_dummy_initdata = {
731 .consumer_supplies = camera_dummy_supplies,
732 .num_consumer_supplies = ARRAY_SIZE(camera_dummy_supplies),
733 .constraints = {
734 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
735 },
736};
737
738static struct fixed_voltage_config camera_dummy_config = {
739 .supply_name = "camera_vdd",
740 .microvolts = 2800000,
741 .gpio = GPIO50_nCAM_EN,
742 .enable_high = 0,
743 .init_data = &camera_dummy_initdata,
744};
745
746static struct platform_device camera_supply_dummy_device = {
747 .name = "reg-fixed-voltage",
748 .id = 1,
749 .dev = {
750 .platform_data = &camera_dummy_config,
751 },
752};
753static int a780_camera_reset(struct device *dev)
754{
755 gpio_set_value(GPIO19_GEN1_CAM_RST, 0);
756 msleep(10);
757 gpio_set_value(GPIO19_GEN1_CAM_RST, 1);
758
759 return 0;
760}
761
726static int a780_camera_init(void) 762static int a780_camera_init(void)
727{ 763{
728 int err; 764 int err;
@@ -731,73 +767,36 @@ static int a780_camera_init(void)
731 * GPIO50_nCAM_EN is active low 767 * GPIO50_nCAM_EN is active low
732 * GPIO19_GEN1_CAM_RST is active on rising edge 768 * GPIO19_GEN1_CAM_RST is active on rising edge
733 */ 769 */
734 err = gpio_request(GPIO50_nCAM_EN, "nCAM_EN");
735 if (err) {
736 pr_err("%s: Failed to request nCAM_EN\n", __func__);
737 goto fail;
738 }
739
740 err = gpio_request(GPIO19_GEN1_CAM_RST, "CAM_RST"); 770 err = gpio_request(GPIO19_GEN1_CAM_RST, "CAM_RST");
741 if (err) { 771 if (err) {
742 pr_err("%s: Failed to request CAM_RST\n", __func__); 772 pr_err("%s: Failed to request CAM_RST\n", __func__);
743 goto fail_gpio_cam_rst; 773 return err;
744 } 774 }
745 775
746 gpio_direction_output(GPIO50_nCAM_EN, 1);
747 gpio_direction_output(GPIO19_GEN1_CAM_RST, 0); 776 gpio_direction_output(GPIO19_GEN1_CAM_RST, 0);
748 777 a780_camera_reset(NULL);
749 return 0;
750
751fail_gpio_cam_rst:
752 gpio_free(GPIO50_nCAM_EN);
753fail:
754 return err;
755}
756
757static int a780_camera_power(struct device *dev, int on)
758{
759 gpio_set_value(GPIO50_nCAM_EN, !on);
760 return 0;
761}
762
763static int a780_camera_reset(struct device *dev)
764{
765 gpio_set_value(GPIO19_GEN1_CAM_RST, 0);
766 msleep(10);
767 gpio_set_value(GPIO19_GEN1_CAM_RST, 1);
768 778
769 return 0; 779 return 0;
770} 780}
771 781
772struct pxacamera_platform_data a780_pxacamera_platform_data = { 782struct pxacamera_platform_data a780_pxacamera_platform_data = {
773 .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | 783 .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 |
774 PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN, 784 PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN |
785 PXA_CAMERA_PCP,
775 .mclk_10khz = 5000, 786 .mclk_10khz = 5000,
787 .sensor_i2c_adapter_id = 0,
788 .sensor_i2c_address = 0x5d,
776}; 789};
777 790
778static struct i2c_board_info a780_camera_i2c_board_info = { 791static struct i2c_board_info a780_i2c_board_info[] = {
779 I2C_BOARD_INFO("mt9m111", 0x5d), 792 {
780}; 793 I2C_BOARD_INFO("mt9m111", 0x5d),
781
782static struct soc_camera_link a780_iclink = {
783 .bus_id = 0,
784 .flags = SOCAM_SENSOR_INVERT_PCLK,
785 .i2c_adapter_id = 0,
786 .board_info = &a780_camera_i2c_board_info,
787 .power = a780_camera_power,
788 .reset = a780_camera_reset,
789};
790
791static struct platform_device a780_camera = {
792 .name = "soc-camera-pdrv",
793 .id = 0,
794 .dev = {
795 .platform_data = &a780_iclink,
796 }, 794 },
797}; 795};
798 796
799static struct platform_device *a780_devices[] __initdata = { 797static struct platform_device *a780_devices[] __initdata = {
800 &a780_gpio_keys, 798 &a780_gpio_keys,
799 &camera_supply_dummy_device,
801}; 800};
802 801
803static void __init a780_init(void) 802static void __init a780_init(void)
@@ -811,19 +810,19 @@ static void __init a780_init(void)
811 pxa_set_stuart_info(NULL); 810 pxa_set_stuart_info(NULL);
812 811
813 pxa_set_i2c_info(NULL); 812 pxa_set_i2c_info(NULL);
813 i2c_register_board_info(0, ARRAY_AND_SIZE(a780_i2c_board_info));
814 814
815 pxa_set_fb_info(NULL, &ezx_fb_info_1); 815 pxa_set_fb_info(NULL, &ezx_fb_info_1);
816 816
817 pxa_set_keypad_info(&a780_keypad_platform_data); 817 pxa_set_keypad_info(&a780_keypad_platform_data);
818 818
819 if (a780_camera_init() == 0) { 819 if (a780_camera_init() == 0)
820 pxa_set_camera_info(&a780_pxacamera_platform_data); 820 pxa_set_camera_info(&a780_pxacamera_platform_data);
821 platform_device_register(&a780_camera);
822 }
823 821
824 pwm_add_table(ezx_pwm_lookup, ARRAY_SIZE(ezx_pwm_lookup)); 822 pwm_add_table(ezx_pwm_lookup, ARRAY_SIZE(ezx_pwm_lookup));
825 platform_add_devices(ARRAY_AND_SIZE(ezx_devices)); 823 platform_add_devices(ARRAY_AND_SIZE(ezx_devices));
826 platform_add_devices(ARRAY_AND_SIZE(a780_devices)); 824 platform_add_devices(ARRAY_AND_SIZE(a780_devices));
825 regulator_has_full_constraints();
827} 826}
828 827
829MACHINE_START(EZX_A780, "Motorola EZX A780") 828MACHINE_START(EZX_A780, "Motorola EZX A780")
@@ -1001,6 +1000,15 @@ static struct platform_device a910_gpio_keys = {
1001}; 1000};
1002 1001
1003/* camera */ 1002/* camera */
1003static int a910_camera_reset(struct device *dev)
1004{
1005 gpio_set_value(GPIO28_GEN2_CAM_RST, 0);
1006 msleep(10);
1007 gpio_set_value(GPIO28_GEN2_CAM_RST, 1);
1008
1009 return 0;
1010}
1011
1004static int a910_camera_init(void) 1012static int a910_camera_init(void)
1005{ 1013{
1006 int err; 1014 int err;
@@ -1009,68 +1017,25 @@ static int a910_camera_init(void)
1009 * GPIO50_nCAM_EN is active low 1017 * GPIO50_nCAM_EN is active low
1010 * GPIO28_GEN2_CAM_RST is active on rising edge 1018 * GPIO28_GEN2_CAM_RST is active on rising edge
1011 */ 1019 */
1012 err = gpio_request(GPIO50_nCAM_EN, "nCAM_EN");
1013 if (err) {
1014 pr_err("%s: Failed to request nCAM_EN\n", __func__);
1015 goto fail;
1016 }
1017
1018 err = gpio_request(GPIO28_GEN2_CAM_RST, "CAM_RST"); 1020 err = gpio_request(GPIO28_GEN2_CAM_RST, "CAM_RST");
1019 if (err) { 1021 if (err) {
1020 pr_err("%s: Failed to request CAM_RST\n", __func__); 1022 pr_err("%s: Failed to request CAM_RST\n", __func__);
1021 goto fail_gpio_cam_rst; 1023 return err;
1022 } 1024 }
1023 1025
1024 gpio_direction_output(GPIO50_nCAM_EN, 1);
1025 gpio_direction_output(GPIO28_GEN2_CAM_RST, 0); 1026 gpio_direction_output(GPIO28_GEN2_CAM_RST, 0);
1026 1027 a910_camera_reset(NULL);
1027 return 0;
1028
1029fail_gpio_cam_rst:
1030 gpio_free(GPIO50_nCAM_EN);
1031fail:
1032 return err;
1033}
1034
1035static int a910_camera_power(struct device *dev, int on)
1036{
1037 gpio_set_value(GPIO50_nCAM_EN, !on);
1038 return 0;
1039}
1040
1041static int a910_camera_reset(struct device *dev)
1042{
1043 gpio_set_value(GPIO28_GEN2_CAM_RST, 0);
1044 msleep(10);
1045 gpio_set_value(GPIO28_GEN2_CAM_RST, 1);
1046 1028
1047 return 0; 1029 return 0;
1048} 1030}
1049 1031
1050struct pxacamera_platform_data a910_pxacamera_platform_data = { 1032struct pxacamera_platform_data a910_pxacamera_platform_data = {
1051 .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | 1033 .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 |
1052 PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN, 1034 PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN |
1035 PXA_CAMERA_PCP,
1053 .mclk_10khz = 5000, 1036 .mclk_10khz = 5000,
1054}; 1037 .sensor_i2c_adapter_id = 0,
1055 1038 .sensor_i2c_address = 0x5d,
1056static struct i2c_board_info a910_camera_i2c_board_info = {
1057 I2C_BOARD_INFO("mt9m111", 0x5d),
1058};
1059
1060static struct soc_camera_link a910_iclink = {
1061 .bus_id = 0,
1062 .i2c_adapter_id = 0,
1063 .board_info = &a910_camera_i2c_board_info,
1064 .power = a910_camera_power,
1065 .reset = a910_camera_reset,
1066};
1067
1068static struct platform_device a910_camera = {
1069 .name = "soc-camera-pdrv",
1070 .id = 0,
1071 .dev = {
1072 .platform_data = &a910_iclink,
1073 },
1074}; 1039};
1075 1040
1076/* leds-lp3944 */ 1041/* leds-lp3944 */
@@ -1122,10 +1087,14 @@ static struct i2c_board_info __initdata a910_i2c_board_info[] = {
1122 I2C_BOARD_INFO("lp3944", 0x60), 1087 I2C_BOARD_INFO("lp3944", 0x60),
1123 .platform_data = &a910_lp3944_leds, 1088 .platform_data = &a910_lp3944_leds,
1124 }, 1089 },
1090 {
1091 I2C_BOARD_INFO("mt9m111", 0x5d),
1092 },
1125}; 1093};
1126 1094
1127static struct platform_device *a910_devices[] __initdata = { 1095static struct platform_device *a910_devices[] __initdata = {
1128 &a910_gpio_keys, 1096 &a910_gpio_keys,
1097 &camera_supply_dummy_device,
1129}; 1098};
1130 1099
1131static void __init a910_init(void) 1100static void __init a910_init(void)
@@ -1145,14 +1114,13 @@ static void __init a910_init(void)
1145 1114
1146 pxa_set_keypad_info(&a910_keypad_platform_data); 1115 pxa_set_keypad_info(&a910_keypad_platform_data);
1147 1116
1148 if (a910_camera_init() == 0) { 1117 if (a910_camera_init() == 0)
1149 pxa_set_camera_info(&a910_pxacamera_platform_data); 1118 pxa_set_camera_info(&a910_pxacamera_platform_data);
1150 platform_device_register(&a910_camera);
1151 }
1152 1119
1153 pwm_add_table(ezx_pwm_lookup, ARRAY_SIZE(ezx_pwm_lookup)); 1120 pwm_add_table(ezx_pwm_lookup, ARRAY_SIZE(ezx_pwm_lookup));
1154 platform_add_devices(ARRAY_AND_SIZE(ezx_devices)); 1121 platform_add_devices(ARRAY_AND_SIZE(ezx_devices));
1155 platform_add_devices(ARRAY_AND_SIZE(a910_devices)); 1122 platform_add_devices(ARRAY_AND_SIZE(a910_devices));
1123 regulator_has_full_constraints();
1156} 1124}
1157 1125
1158MACHINE_START(EZX_A910, "Motorola EZX A910") 1126MACHINE_START(EZX_A910, "Motorola EZX A910")
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index ec510ecf8370..cb73a9723d0e 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -43,21 +43,6 @@ void clear_reset_status(unsigned int mask)
43 } 43 }
44} 44}
45 45
46unsigned long get_clock_tick_rate(void)
47{
48 unsigned long clock_tick_rate;
49
50 if (cpu_is_pxa25x())
51 clock_tick_rate = 3686400;
52 else if (machine_is_mainstone())
53 clock_tick_rate = 3249600;
54 else
55 clock_tick_rate = 3250000;
56
57 return clock_tick_rate;
58}
59EXPORT_SYMBOL(get_clock_tick_rate);
60
61/* 46/*
62 * For non device-tree builds, keep legacy timer init 47 * For non device-tree builds, keep legacy timer init
63 */ 48 */
@@ -69,8 +54,7 @@ void __init pxa_timer_init(void)
69 pxa27x_clocks_init(); 54 pxa27x_clocks_init();
70 if (cpu_is_pxa3xx()) 55 if (cpu_is_pxa3xx())
71 pxa3xx_clocks_init(); 56 pxa3xx_clocks_init();
72 pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000), 57 pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000));
73 get_clock_tick_rate());
74} 58}
75 59
76/* 60/*
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index 8d63c211b22f..55064124ca4e 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -303,8 +303,6 @@
303 */ 303 */
304extern unsigned int get_memclk_frequency_10khz(void); 304extern unsigned int get_memclk_frequency_10khz(void);
305 305
306/* return the clock tick rate of the OS timer */
307extern unsigned long get_clock_tick_rate(void);
308#endif 306#endif
309 307
310#endif /* _ASM_ARCH_HARDWARE_H */ 308#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index 38a96a193dc4..8a5d0491e73c 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -57,7 +57,6 @@
57#include <linux/platform_data/media/camera-pxa.h> 57#include <linux/platform_data/media/camera-pxa.h>
58#include <mach/audio.h> 58#include <mach/audio.h>
59#include <mach/smemc.h> 59#include <mach/smemc.h>
60#include <media/soc_camera.h>
61 60
62#include "mioa701.h" 61#include "mioa701.h"
63 62
@@ -627,6 +626,8 @@ struct pxacamera_platform_data mioa701_pxacamera_platform_data = {
627 .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | 626 .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 |
628 PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN, 627 PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN,
629 .mclk_10khz = 5000, 628 .mclk_10khz = 5000,
629 .sensor_i2c_adapter_id = 0,
630 .sensor_i2c_address = 0x5d,
630}; 631};
631 632
632static struct i2c_board_info __initdata mioa701_pi2c_devices[] = { 633static struct i2c_board_info __initdata mioa701_pi2c_devices[] = {
@@ -643,12 +644,6 @@ static struct i2c_board_info mioa701_i2c_devices[] = {
643 }, 644 },
644}; 645};
645 646
646static struct soc_camera_link iclink = {
647 .bus_id = 0, /* Match id in pxa27x_device_camera in device.c */
648 .board_info = &mioa701_i2c_devices[0],
649 .i2c_adapter_id = 0,
650};
651
652struct i2c_pxa_platform_data i2c_pdata = { 647struct i2c_pxa_platform_data i2c_pdata = {
653 .fast_mode = 1, 648 .fast_mode = 1,
654}; 649};
@@ -684,7 +679,6 @@ MIO_SIMPLE_DEV(mioa701_sound, "mioa701-wm9713", NULL)
684MIO_SIMPLE_DEV(mioa701_board, "mioa701-board", NULL) 679MIO_SIMPLE_DEV(mioa701_board, "mioa701-board", NULL)
685MIO_SIMPLE_DEV(wm9713_acodec, "wm9713-codec", NULL); 680MIO_SIMPLE_DEV(wm9713_acodec, "wm9713-codec", NULL);
686MIO_SIMPLE_DEV(gpio_vbus, "gpio-vbus", &gpio_vbus_data); 681MIO_SIMPLE_DEV(gpio_vbus, "gpio-vbus", &gpio_vbus_data);
687MIO_SIMPLE_DEV(mioa701_camera, "soc-camera-pdrv",&iclink);
688 682
689static struct platform_device *devices[] __initdata = { 683static struct platform_device *devices[] __initdata = {
690 &mioa701_gpio_keys, 684 &mioa701_gpio_keys,
@@ -696,7 +690,6 @@ static struct platform_device *devices[] __initdata = {
696 &power_dev, 690 &power_dev,
697 &docg3, 691 &docg3,
698 &gpio_vbus, 692 &gpio_vbus,
699 &mioa701_camera,
700 &mioa701_board, 693 &mioa701_board,
701}; 694};
702 695
@@ -761,6 +754,7 @@ static void __init mioa701_machine_init(void)
761 platform_add_devices(devices, ARRAY_SIZE(devices)); 754 platform_add_devices(devices, ARRAY_SIZE(devices));
762 gsm_init(); 755 gsm_init();
763 756
757 i2c_register_board_info(0, ARRAY_AND_SIZE(mioa701_i2c_devices));
764 i2c_register_board_info(1, ARRAY_AND_SIZE(mioa701_pi2c_devices)); 758 i2c_register_board_info(1, ARRAY_AND_SIZE(mioa701_pi2c_devices));
765 pxa_set_i2c_info(&i2c_pdata); 759 pxa_set_i2c_info(&i2c_pdata);
766 pxa27x_set_i2c_power_info(NULL); 760 pxa27x_set_i2c_power_info(NULL);
@@ -769,6 +763,7 @@ static void __init mioa701_machine_init(void)
769 regulator_register_always_on(0, "fixed-5.0V", fixed_5v0_consumers, 763 regulator_register_always_on(0, "fixed-5.0V", fixed_5v0_consumers,
770 ARRAY_SIZE(fixed_5v0_consumers), 764 ARRAY_SIZE(fixed_5v0_consumers),
771 5000000); 765 5000000);
766 regulator_has_full_constraints();
772} 767}
773 768
774static void mioa701_machine_exit(void) 769static void mioa701_machine_exit(void)
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 12b94357fbc1..c725baf119e1 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -156,7 +156,7 @@ static int __init __init
156pxa25x_dt_init_irq(struct device_node *node, struct device_node *parent) 156pxa25x_dt_init_irq(struct device_node *node, struct device_node *parent)
157{ 157{
158 pxa_dt_irq_init(pxa25x_set_wake); 158 pxa_dt_irq_init(pxa25x_set_wake);
159 set_handle_irq(ichp_handle_irq); 159 set_handle_irq(icip_handle_irq);
160 160
161 return 0; 161 return 0;
162} 162}
diff --git a/arch/arm/mach-pxa/pxa_cplds_irqs.c b/arch/arm/mach-pxa/pxa_cplds_irqs.c
index e362f865fcd2..941508585e34 100644
--- a/arch/arm/mach-pxa/pxa_cplds_irqs.c
+++ b/arch/arm/mach-pxa/pxa_cplds_irqs.c
@@ -120,13 +120,9 @@ static int cplds_probe(struct platform_device *pdev)
120 if (!fpga) 120 if (!fpga)
121 return -ENOMEM; 121 return -ENOMEM;
122 122
123 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 123 fpga->irq = platform_get_irq(pdev, 0);
124 if (res) { 124 if (fpga->irq <= 0)
125 fpga->irq = (unsigned int)res->start; 125 return fpga->irq;
126 irqflags = res->flags;
127 }
128 if (!fpga->irq)
129 return -ENODEV;
130 126
131 base_irq = platform_get_irq(pdev, 1); 127 base_irq = platform_get_irq(pdev, 1);
132 if (base_irq < 0) 128 if (base_irq < 0)
@@ -142,6 +138,7 @@ static int cplds_probe(struct platform_device *pdev)
142 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); 138 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
143 writel(0, fpga->base + FPGA_IRQ_SET_CLR); 139 writel(0, fpga->base + FPGA_IRQ_SET_CLR);
144 140
141 irqflags = irq_get_trigger_type(fpga->irq);
145 ret = devm_request_irq(&pdev->dev, fpga->irq, cplds_irq_handler, 142 ret = devm_request_irq(&pdev->dev, fpga->irq, cplds_irq_handler,
146 irqflags, dev_name(&pdev->dev), fpga); 143 irqflags, dev_name(&pdev->dev), fpga);
147 if (ret == -ENOSYS) 144 if (ret == -ENOSYS)
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 2c150bfc0cd5..67d66c702574 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -31,7 +31,6 @@
31#include <linux/input/matrix_keypad.h> 31#include <linux/input/matrix_keypad.h>
32#include <linux/regulator/machine.h> 32#include <linux/regulator/machine.h>
33#include <linux/io.h> 33#include <linux/io.h>
34#include <linux/module.h>
35#include <linux/reboot.h> 34#include <linux/reboot.h>
36#include <linux/memblock.h> 35#include <linux/memblock.h>
37 36
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 3e09beddb6e8..2eb00691b07d 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -378,7 +378,7 @@ void __init sa1100_map_io(void)
378 378
379void __init sa1100_timer_init(void) 379void __init sa1100_timer_init(void)
380{ 380{
381 pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x90000000), 3686400); 381 pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x90000000));
382} 382}
383 383
384static struct resource irq_resource = 384static struct resource irq_resource =
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
index d944fd7e464f..52b8f6d25bef 100644
--- a/arch/arm/mach-sa1100/include/mach/hardware.h
+++ b/arch/arm/mach-sa1100/include/mach/hardware.h
@@ -43,10 +43,6 @@
43# define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x))) 43# define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x)))
44# define __PREG(x) (io_v2p((unsigned long)&(x))) 44# define __PREG(x) (io_v2p((unsigned long)&(x)))
45 45
46static inline unsigned long get_clock_tick_rate(void)
47{
48 return 3686400;
49}
50#else 46#else
51 47
52# define __REG(x) io_p2v(x) 48# define __REG(x) io_p2v(x)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 09817bae4558..f0b5e7dfa6d0 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -32,15 +32,15 @@ config ARCH_RMOBILE
32menuconfig ARCH_RENESAS 32menuconfig ARCH_RENESAS
33 bool "Renesas ARM SoCs" 33 bool "Renesas ARM SoCs"
34 depends on ARCH_MULTI_V7 && MMU 34 depends on ARCH_MULTI_V7 && MMU
35 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
35 select ARCH_SHMOBILE 36 select ARCH_SHMOBILE
36 select ARCH_SHMOBILE_MULTI 37 select ARCH_SHMOBILE_MULTI
38 select ARM_GIC
39 select GPIOLIB
37 select HAVE_ARM_SCU if SMP 40 select HAVE_ARM_SCU if SMP
38 select HAVE_ARM_TWD if SMP 41 select HAVE_ARM_TWD if SMP
39 select ARM_GIC
40 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
41 select NO_IOPORT_MAP 42 select NO_IOPORT_MAP
42 select PINCTRL 43 select PINCTRL
43 select GPIOLIB
44 select ZONE_DMA if ARM_LPAE 44 select ZONE_DMA if ARM_LPAE
45 45
46if ARCH_RENESAS 46if ARCH_RENESAS
@@ -60,6 +60,7 @@ config ARCH_R7S72100
60config ARCH_R8A73A4 60config ARCH_R8A73A4
61 bool "R-Mobile APE6 (R8A73A40)" 61 bool "R-Mobile APE6 (R8A73A40)"
62 select ARCH_RMOBILE 62 select ARCH_RMOBILE
63 select ARM_ERRATA_798181 if SMP
63 select RENESAS_IRQC 64 select RENESAS_IRQC
64 65
65config ARCH_R8A7740 66config ARCH_R8A7740
@@ -67,6 +68,15 @@ config ARCH_R8A7740
67 select ARCH_RMOBILE 68 select ARCH_RMOBILE
68 select RENESAS_INTC_IRQPIN 69 select RENESAS_INTC_IRQPIN
69 70
71config ARCH_R8A7743
72 bool "RZ/G1M (R8A77430)"
73 select ARCH_RCAR_GEN2
74 select ARM_ERRATA_798181 if SMP
75
76config ARCH_R8A7745
77 bool "RZ/G1E (R8A77450)"
78 select ARCH_RCAR_GEN2
79
70config ARCH_R8A7778 80config ARCH_R8A7778
71 bool "R-Car M1A (R8A77781)" 81 bool "R-Car M1A (R8A77781)"
72 select ARCH_RCAR_GEN1 82 select ARCH_RCAR_GEN1
@@ -78,20 +88,24 @@ config ARCH_R8A7779
78config ARCH_R8A7790 88config ARCH_R8A7790
79 bool "R-Car H2 (R8A77900)" 89 bool "R-Car H2 (R8A77900)"
80 select ARCH_RCAR_GEN2 90 select ARCH_RCAR_GEN2
91 select ARM_ERRATA_798181 if SMP
81 select I2C 92 select I2C
82 93
83config ARCH_R8A7791 94config ARCH_R8A7791
84 bool "R-Car M2-W (R8A77910)" 95 bool "R-Car M2-W (R8A77910)"
85 select ARCH_RCAR_GEN2 96 select ARCH_RCAR_GEN2
97 select ARM_ERRATA_798181 if SMP
86 select I2C 98 select I2C
87 99
88config ARCH_R8A7792 100config ARCH_R8A7792
89 bool "R-Car V2H (R8A77920)" 101 bool "R-Car V2H (R8A77920)"
90 select ARCH_RCAR_GEN2 102 select ARCH_RCAR_GEN2
103 select ARM_ERRATA_798181 if SMP
91 104
92config ARCH_R8A7793 105config ARCH_R8A7793
93 bool "R-Car M2-N (R8A7793)" 106 bool "R-Car M2-N (R8A7793)"
94 select ARCH_RCAR_GEN2 107 select ARCH_RCAR_GEN2
108 select ARM_ERRATA_798181 if SMP
95 select I2C 109 select I2C
96 110
97config ARCH_R8A7794 111config ARCH_R8A7794
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 3fc48b02eb4f..64611a1b4276 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -13,9 +13,6 @@ obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o
13obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o pm-r8a7779.o 13obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o pm-r8a7779.o
14obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o 14obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o
15obj-$(CONFIG_ARCH_R8A7791) += setup-r8a7791.o 15obj-$(CONFIG_ARCH_R8A7791) += setup-r8a7791.o
16obj-$(CONFIG_ARCH_R8A7792) += setup-r8a7792.o
17obj-$(CONFIG_ARCH_R8A7793) += setup-r8a7793.o
18obj-$(CONFIG_ARCH_R8A7794) += setup-r8a7794.o
19obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o 16obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o
20obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o 17obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o
21 18
diff --git a/arch/arm/mach-shmobile/setup-r8a7792.c b/arch/arm/mach-shmobile/setup-r8a7792.c
deleted file mode 100644
index a0910395da09..000000000000
--- a/arch/arm/mach-shmobile/setup-r8a7792.c
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * r8a7792 processor support
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2016 Cogent Embedded, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/of_platform.h>
18
19#include <asm/mach/arch.h>
20
21#include "common.h"
22#include "rcar-gen2.h"
23
24static const char * const r8a7792_boards_compat_dt[] __initconst = {
25 "renesas,r8a7792",
26 NULL,
27};
28
29DT_MACHINE_START(R8A7792_DT, "Generic R8A7792 (Flattened Device Tree)")
30 .init_early = shmobile_init_delay,
31 .init_late = shmobile_init_late,
32 .init_time = rcar_gen2_timer_init,
33 .reserve = rcar_gen2_reserve,
34 .dt_compat = r8a7792_boards_compat_dt,
35MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-r8a7793.c b/arch/arm/mach-shmobile/setup-r8a7793.c
deleted file mode 100644
index 5fce87f7f254..000000000000
--- a/arch/arm/mach-shmobile/setup-r8a7793.c
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * r8a7793 processor support
3 *
4 * Copyright (C) 2015 Ulrich Hecht
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/init.h>
17#include <asm/mach/arch.h>
18
19#include "common.h"
20#include "rcar-gen2.h"
21
22static const char * const r8a7793_boards_compat_dt[] __initconst = {
23 "renesas,r8a7793",
24 NULL,
25};
26
27DT_MACHINE_START(R8A7793_DT, "Generic R8A7793 (Flattened Device Tree)")
28 .init_early = shmobile_init_delay,
29 .init_time = rcar_gen2_timer_init,
30 .init_late = shmobile_init_late,
31 .reserve = rcar_gen2_reserve,
32 .dt_compat = r8a7793_boards_compat_dt,
33MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-r8a7794.c b/arch/arm/mach-shmobile/setup-r8a7794.c
deleted file mode 100644
index d2b093033132..000000000000
--- a/arch/arm/mach-shmobile/setup-r8a7794.c
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * r8a7794 processor support
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2014 Ulrich Hecht
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/of_platform.h>
18#include "common.h"
19#include "rcar-gen2.h"
20#include <asm/mach/arch.h>
21
22static const char * const r8a7794_boards_compat_dt[] __initconst = {
23 "renesas,r8a7794",
24 NULL,
25};
26
27DT_MACHINE_START(R8A7794_DT, "Generic R8A7794 (Flattened Device Tree)")
28 .init_early = shmobile_init_delay,
29 .init_late = shmobile_init_late,
30 .init_time = rcar_gen2_timer_init,
31 .reserve = rcar_gen2_reserve,
32 .dt_compat = r8a7794_boards_compat_dt,
33MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index afb9fdcd3d90..14c1f0ed2ecb 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -15,6 +15,7 @@
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 */ 16 */
17 17
18#include <linux/clk-provider.h>
18#include <linux/clk/renesas.h> 19#include <linux/clk/renesas.h>
19#include <linux/clocksource.h> 20#include <linux/clocksource.h>
20#include <linux/device.h> 21#include <linux/device.h>
@@ -24,6 +25,7 @@
24#include <linux/memblock.h> 25#include <linux/memblock.h>
25#include <linux/of.h> 26#include <linux/of.h>
26#include <linux/of_fdt.h> 27#include <linux/of_fdt.h>
28#include <linux/of_platform.h>
27#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
28#include "common.h" 30#include "common.h"
29#include "rcar-gen2.h" 31#include "rcar-gen2.h"
@@ -130,7 +132,15 @@ void __init rcar_gen2_timer_init(void)
130 iounmap(base); 132 iounmap(base);
131#endif /* CONFIG_ARM_ARCH_TIMER */ 133#endif /* CONFIG_ARM_ARCH_TIMER */
132 134
133 rcar_gen2_clocks_init(mode); 135 if (IS_ENABLED(CONFIG_ARCH_R8A7790) ||
136 IS_ENABLED(CONFIG_ARCH_R8A7791) ||
137 IS_ENABLED(CONFIG_ARCH_R8A7792) ||
138 IS_ENABLED(CONFIG_ARCH_R8A7793) ||
139 IS_ENABLED(CONFIG_ARCH_R8A7794))
140 rcar_gen2_clocks_init(mode);
141 else
142 of_clk_init(NULL);
143
134 clocksource_probe(); 144 clocksource_probe();
135} 145}
136 146
@@ -203,3 +213,36 @@ void __init rcar_gen2_reserve(void)
203 } 213 }
204#endif 214#endif
205} 215}
216
217static const char * const rcar_gen2_boards_compat_dt[] __initconst = {
218 /*
219 * R8A7790 and R8A7791 can't be handled here as long as they need SMP
220 * initialization fallback.
221 */
222 "renesas,r8a7792",
223 "renesas,r8a7793",
224 "renesas,r8a7794",
225 NULL,
226};
227
228DT_MACHINE_START(RCAR_GEN2_DT, "Generic R-Car Gen2 (Flattened Device Tree)")
229 .init_early = shmobile_init_delay,
230 .init_late = shmobile_init_late,
231 .init_time = rcar_gen2_timer_init,
232 .reserve = rcar_gen2_reserve,
233 .dt_compat = rcar_gen2_boards_compat_dt,
234MACHINE_END
235
236static const char * const rz_g1_boards_compat_dt[] __initconst = {
237 "renesas,r8a7743",
238 "renesas,r8a7745",
239 NULL,
240};
241
242DT_MACHINE_START(RZ_G1_DT, "Generic RZ/G1 (Flattened Device Tree)")
243 .init_early = shmobile_init_delay,
244 .init_late = shmobile_init_late,
245 .init_time = rcar_gen2_timer_init,
246 .reserve = rcar_gen2_reserve,
247 .dt_compat = rz_g1_boards_compat_dt,
248MACHINE_END
diff --git a/arch/arm/mach-stm32/board-dt.c b/arch/arm/mach-stm32/board-dt.c
index ceee47735eec..c354222a4158 100644
--- a/arch/arm/mach-stm32/board-dt.c
+++ b/arch/arm/mach-stm32/board-dt.c
@@ -11,6 +11,7 @@
11static const char *const stm32_compat[] __initconst = { 11static const char *const stm32_compat[] __initconst = {
12 "st,stm32f429", 12 "st,stm32f429",
13 "st,stm32f469", 13 "st,stm32f469",
14 "st,stm32f746",
14 NULL 15 NULL
15}; 16};
16 17
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 8b8d0724f6c6..98e29dee91e8 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -26,19 +26,37 @@
26bool __init vexpress_smp_init_ops(void) 26bool __init vexpress_smp_init_ops(void)
27{ 27{
28#ifdef CONFIG_MCPM 28#ifdef CONFIG_MCPM
29 int cpu;
30 struct device_node *cpu_node, *cci_node;
31
29 /* 32 /*
30 * The best way to detect a multi-cluster configuration at the moment 33 * The best way to detect a multi-cluster configuration
31 * is to look for the presence of a CCI in the system. 34 * is to detect if the kernel can take over CCI ports
35 * control. Loop over possible CPUs and check if CCI
36 * port control is available.
32 * Override the default vexpress_smp_ops if so. 37 * Override the default vexpress_smp_ops if so.
33 */ 38 */
34 struct device_node *node; 39 for_each_possible_cpu(cpu) {
35 node = of_find_compatible_node(NULL, NULL, "arm,cci-400"); 40 bool available;
36 if (node && of_device_is_available(node)) { 41
37 mcpm_smp_set_ops(); 42 cpu_node = of_get_cpu_node(cpu, NULL);
38 return true; 43 if (WARN(!cpu_node, "Missing cpu device node!"))
44 return false;
45
46 cci_node = of_parse_phandle(cpu_node, "cci-control-port", 0);
47 available = cci_node && of_device_is_available(cci_node);
48 of_node_put(cci_node);
49 of_node_put(cpu_node);
50
51 if (!available)
52 return false;
39 } 53 }
40#endif 54
55 mcpm_smp_set_ops();
56 return true;
57#else
41 return false; 58 return false;
59#endif
42} 60}
43 61
44static const struct of_device_id vexpress_smp_dt_scu_match[] __initconst = { 62static const struct of_device_id vexpress_smp_dt_scu_match[] __initconst = {
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index d055db32ffcb..3e27bffb352d 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -63,32 +63,6 @@ config OMAP_RESET_CLOCKS
63 probably do not want this option enabled until your 63 probably do not want this option enabled until your
64 device drivers work properly. 64 device drivers work properly.
65 65
66config OMAP_MUX
67 bool "OMAP multiplexing support"
68 depends on ARCH_OMAP
69 default y
70 help
71 Pin multiplexing support for OMAP boards. If your bootloader
72 sets the multiplexing correctly, say N. Otherwise, or if unsure,
73 say Y.
74
75config OMAP_MUX_DEBUG
76 bool "Multiplexing debug output"
77 depends on OMAP_MUX
78 help
79 Makes the multiplexing functions print out a lot of debug info.
80 This is useful if you want to find out the correct values of the
81 multiplexing registers.
82
83config OMAP_MUX_WARNINGS
84 bool "Warn about pins the bootloader didn't set up"
85 depends on OMAP_MUX
86 default y
87 help
88 Choose Y here to warn whenever driver initialization logic needs
89 to change the pin multiplexing setup. When there are no warnings
90 printed, it's safe to deselect OMAP_MUX for your product.
91
92config OMAP_MPU_TIMER 66config OMAP_MPU_TIMER
93 bool "Use mpu timer" 67 bool "Use mpu timer"
94 depends on ARCH_OMAP1 68 depends on ARCH_OMAP1
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 97a50e8883f9..47e186729d44 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -11,6 +11,3 @@ obj-y := sram.o dma.o counter_32k.o
11 11
12obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o 12obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
13obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o 13obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
14i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
15obj-y += $(i2c-omap-m) $(i2c-omap-y)
16
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
deleted file mode 100644
index 58213d9714cd..000000000000
--- a/arch/arm/plat-omap/i2c.c
+++ /dev/null
@@ -1,116 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/i2c.c
3 *
4 * Helper module for board specific I2C bus registration
5 *
6 * Copyright (C) 2007 Nokia Corporation.
7 *
8 * Contact: Jarkko Nikula <jhnikula@gmail.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * 02110-1301 USA
23 *
24 */
25
26#include <linux/kernel.h>
27#include <linux/platform_device.h>
28#include <linux/i2c.h>
29#include <linux/i2c-omap.h>
30#include <linux/slab.h>
31#include <linux/err.h>
32#include <linux/clk.h>
33
34#include <plat/i2c.h>
35
36#define OMAP_I2C_MAX_CONTROLLERS 4
37static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS];
38
39#define OMAP_I2C_CMDLINE_SETUP (BIT(31))
40
41/**
42 * omap_i2c_bus_setup - Process command line options for the I2C bus speed
43 * @str: String of options
44 *
45 * This function allow to override the default I2C bus speed for given I2C
46 * bus with a command line option.
47 *
48 * Format: i2c_bus=bus_id,clkrate (in kHz)
49 *
50 * Returns 1 on success, 0 otherwise.
51 */
52static int __init omap_i2c_bus_setup(char *str)
53{
54 int ints[3];
55
56 get_options(str, 3, ints);
57 if (ints[0] < 2 || ints[1] < 1 ||
58 ints[1] > OMAP_I2C_MAX_CONTROLLERS)
59 return 0;
60 i2c_pdata[ints[1] - 1].clkrate = ints[2];
61 i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP;
62
63 return 1;
64}
65__setup("i2c_bus=", omap_i2c_bus_setup);
66
67/*
68 * Register busses defined in command line but that are not registered with
69 * omap_register_i2c_bus from board initialization code.
70 */
71int __init omap_register_i2c_bus_cmdline(void)
72{
73 int i, err = 0;
74
75 for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++)
76 if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) {
77 i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
78 err = omap_i2c_add_bus(&i2c_pdata[i], i + 1);
79 if (err)
80 goto out;
81 }
82
83out:
84 return err;
85}
86
87/**
88 * omap_register_i2c_bus - register I2C bus with device descriptors
89 * @bus_id: bus id counting from number 1
90 * @clkrate: clock rate of the bus in kHz
91 * @info: pointer into I2C device descriptor table or NULL
92 * @len: number of descriptors in the table
93 *
94 * Returns 0 on success or an error code.
95 */
96int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
97 struct i2c_board_info const *info,
98 unsigned len)
99{
100 int err;
101
102 BUG_ON(bus_id < 1 || bus_id > OMAP_I2C_MAX_CONTROLLERS);
103
104 if (info) {
105 err = i2c_register_board_info(bus_id, info, len);
106 if (err)
107 return err;
108 }
109
110 if (!i2c_pdata[bus_id - 1].clkrate)
111 i2c_pdata[bus_id - 1].clkrate = clkrate;
112
113 i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
114
115 return omap_i2c_add_bus(&i2c_pdata[bus_id - 1], bus_id);
116}
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index f74069386c13..26a531ebb6e9 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -478,13 +478,13 @@ static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
478 (data_in ^ in_pol) & msk ? "hi" : "lo", 478 (data_in ^ in_pol) & msk ? "hi" : "lo",
479 in_pol & msk ? "lo" : "hi"); 479 in_pol & msk ? "lo" : "hi");
480 if (!((edg_msk | lvl_msk) & msk)) { 480 if (!((edg_msk | lvl_msk) & msk)) {
481 seq_printf(s, " disabled\n"); 481 seq_puts(s, " disabled\n");
482 continue; 482 continue;
483 } 483 }
484 if (edg_msk & msk) 484 if (edg_msk & msk)
485 seq_printf(s, " edge "); 485 seq_puts(s, " edge ");
486 if (lvl_msk & msk) 486 if (lvl_msk & msk)
487 seq_printf(s, " level"); 487 seq_puts(s, " level");
488 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); 488 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
489 } 489 }
490} 490}
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 30398dbc940a..969ef880d234 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -915,7 +915,7 @@ config RANDOMIZE_BASE
915 915
916config RANDOMIZE_MODULE_REGION_FULL 916config RANDOMIZE_MODULE_REGION_FULL
917 bool "Randomize the module region independently from the core kernel" 917 bool "Randomize the module region independently from the core kernel"
918 depends on RANDOMIZE_BASE 918 depends on RANDOMIZE_BASE && !DYNAMIC_FTRACE
919 default y 919 default y
920 help 920 help
921 Randomizes the location of the module region without considering the 921 Randomizes the location of the module region without considering the
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index ab51aed6b6c1..3635b8662724 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -15,7 +15,7 @@ CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET)
15GZFLAGS :=-9 15GZFLAGS :=-9
16 16
17ifneq ($(CONFIG_RELOCATABLE),) 17ifneq ($(CONFIG_RELOCATABLE),)
18LDFLAGS_vmlinux += -pie -Bsymbolic 18LDFLAGS_vmlinux += -pie -shared -Bsymbolic
19endif 19endif
20 20
21ifeq ($(CONFIG_ARM64_ERRATUM_843419),y) 21ifeq ($(CONFIG_ARM64_ERRATUM_843419),y)
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 758d74fedfad..a27c3245ba21 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -94,7 +94,7 @@ struct arm64_cpu_capabilities {
94 u16 capability; 94 u16 capability;
95 int def_scope; /* default scope */ 95 int def_scope; /* default scope */
96 bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope); 96 bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope);
97 void (*enable)(void *); /* Called on all active CPUs */ 97 int (*enable)(void *); /* Called on all active CPUs */
98 union { 98 union {
99 struct { /* To be used for erratum handling only */ 99 struct { /* To be used for erratum handling only */
100 u32 midr_model; 100 u32 midr_model;
diff --git a/arch/arm64/include/asm/exec.h b/arch/arm64/include/asm/exec.h
index db0563c23482..f7865dd9d868 100644
--- a/arch/arm64/include/asm/exec.h
+++ b/arch/arm64/include/asm/exec.h
@@ -18,6 +18,9 @@
18#ifndef __ASM_EXEC_H 18#ifndef __ASM_EXEC_H
19#define __ASM_EXEC_H 19#define __ASM_EXEC_H
20 20
21#include <linux/sched.h>
22
21extern unsigned long arch_align_stack(unsigned long sp); 23extern unsigned long arch_align_stack(unsigned long sp);
24void uao_thread_switch(struct task_struct *next);
22 25
23#endif /* __ASM_EXEC_H */ 26#endif /* __ASM_EXEC_H */
diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
index fd9d5fd788f5..f5ea0ba70f07 100644
--- a/arch/arm64/include/asm/kvm_emulate.h
+++ b/arch/arm64/include/asm/kvm_emulate.h
@@ -178,11 +178,6 @@ static inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
178 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_ISV); 178 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_ISV);
179} 179}
180 180
181static inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)
182{
183 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WNR);
184}
185
186static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu) 181static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)
187{ 182{
188 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SSE); 183 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SSE);
@@ -203,6 +198,12 @@ static inline bool kvm_vcpu_dabt_iss1tw(const struct kvm_vcpu *vcpu)
203 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_S1PTW); 198 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_S1PTW);
204} 199}
205 200
201static inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)
202{
203 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WNR) ||
204 kvm_vcpu_dabt_iss1tw(vcpu); /* AF/DBM update */
205}
206
206static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu) 207static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu)
207{ 208{
208 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_CM); 209 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_CM);
diff --git a/arch/arm64/include/asm/module.h b/arch/arm64/include/asm/module.h
index e12af6754634..06ff7fd9e81f 100644
--- a/arch/arm64/include/asm/module.h
+++ b/arch/arm64/include/asm/module.h
@@ -17,6 +17,7 @@
17#define __ASM_MODULE_H 17#define __ASM_MODULE_H
18 18
19#include <asm-generic/module.h> 19#include <asm-generic/module.h>
20#include <asm/memory.h>
20 21
21#define MODULE_ARCH_VERMAGIC "aarch64" 22#define MODULE_ARCH_VERMAGIC "aarch64"
22 23
@@ -32,6 +33,10 @@ u64 module_emit_plt_entry(struct module *mod, const Elf64_Rela *rela,
32 Elf64_Sym *sym); 33 Elf64_Sym *sym);
33 34
34#ifdef CONFIG_RANDOMIZE_BASE 35#ifdef CONFIG_RANDOMIZE_BASE
36#ifdef CONFIG_MODVERSIONS
37#define ARCH_RELOCATES_KCRCTAB
38#define reloc_start (kimage_vaddr - KIMAGE_VADDR)
39#endif
35extern u64 module_alloc_base; 40extern u64 module_alloc_base;
36#else 41#else
37#define module_alloc_base ((u64)_etext - MODULES_VSIZE) 42#define module_alloc_base ((u64)_etext - MODULES_VSIZE)
diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h
index 2fee2f59288c..5394c8405e66 100644
--- a/arch/arm64/include/asm/percpu.h
+++ b/arch/arm64/include/asm/percpu.h
@@ -44,48 +44,44 @@ static inline unsigned long __percpu_##op(void *ptr, \
44 \ 44 \
45 switch (size) { \ 45 switch (size) { \
46 case 1: \ 46 case 1: \
47 do { \ 47 asm ("//__per_cpu_" #op "_1\n" \
48 asm ("//__per_cpu_" #op "_1\n" \ 48 "1: ldxrb %w[ret], %[ptr]\n" \
49 "ldxrb %w[ret], %[ptr]\n" \
50 #asm_op " %w[ret], %w[ret], %w[val]\n" \ 49 #asm_op " %w[ret], %w[ret], %w[val]\n" \
51 "stxrb %w[loop], %w[ret], %[ptr]\n" \ 50 " stxrb %w[loop], %w[ret], %[ptr]\n" \
52 : [loop] "=&r" (loop), [ret] "=&r" (ret), \ 51 " cbnz %w[loop], 1b" \
53 [ptr] "+Q"(*(u8 *)ptr) \ 52 : [loop] "=&r" (loop), [ret] "=&r" (ret), \
54 : [val] "Ir" (val)); \ 53 [ptr] "+Q"(*(u8 *)ptr) \
55 } while (loop); \ 54 : [val] "Ir" (val)); \
56 break; \ 55 break; \
57 case 2: \ 56 case 2: \
58 do { \ 57 asm ("//__per_cpu_" #op "_2\n" \
59 asm ("//__per_cpu_" #op "_2\n" \ 58 "1: ldxrh %w[ret], %[ptr]\n" \
60 "ldxrh %w[ret], %[ptr]\n" \
61 #asm_op " %w[ret], %w[ret], %w[val]\n" \ 59 #asm_op " %w[ret], %w[ret], %w[val]\n" \
62 "stxrh %w[loop], %w[ret], %[ptr]\n" \ 60 " stxrh %w[loop], %w[ret], %[ptr]\n" \
63 : [loop] "=&r" (loop), [ret] "=&r" (ret), \ 61 " cbnz %w[loop], 1b" \
64 [ptr] "+Q"(*(u16 *)ptr) \ 62 : [loop] "=&r" (loop), [ret] "=&r" (ret), \
65 : [val] "Ir" (val)); \ 63 [ptr] "+Q"(*(u16 *)ptr) \
66 } while (loop); \ 64 : [val] "Ir" (val)); \
67 break; \ 65 break; \
68 case 4: \ 66 case 4: \
69 do { \ 67 asm ("//__per_cpu_" #op "_4\n" \
70 asm ("//__per_cpu_" #op "_4\n" \ 68 "1: ldxr %w[ret], %[ptr]\n" \
71 "ldxr %w[ret], %[ptr]\n" \
72 #asm_op " %w[ret], %w[ret], %w[val]\n" \ 69 #asm_op " %w[ret], %w[ret], %w[val]\n" \
73 "stxr %w[loop], %w[ret], %[ptr]\n" \ 70 " stxr %w[loop], %w[ret], %[ptr]\n" \
74 : [loop] "=&r" (loop), [ret] "=&r" (ret), \ 71 " cbnz %w[loop], 1b" \
75 [ptr] "+Q"(*(u32 *)ptr) \ 72 : [loop] "=&r" (loop), [ret] "=&r" (ret), \
76 : [val] "Ir" (val)); \ 73 [ptr] "+Q"(*(u32 *)ptr) \
77 } while (loop); \ 74 : [val] "Ir" (val)); \
78 break; \ 75 break; \
79 case 8: \ 76 case 8: \
80 do { \ 77 asm ("//__per_cpu_" #op "_8\n" \
81 asm ("//__per_cpu_" #op "_8\n" \ 78 "1: ldxr %[ret], %[ptr]\n" \
82 "ldxr %[ret], %[ptr]\n" \
83 #asm_op " %[ret], %[ret], %[val]\n" \ 79 #asm_op " %[ret], %[ret], %[val]\n" \
84 "stxr %w[loop], %[ret], %[ptr]\n" \ 80 " stxr %w[loop], %[ret], %[ptr]\n" \
85 : [loop] "=&r" (loop), [ret] "=&r" (ret), \ 81 " cbnz %w[loop], 1b" \
86 [ptr] "+Q"(*(u64 *)ptr) \ 82 : [loop] "=&r" (loop), [ret] "=&r" (ret), \
87 : [val] "Ir" (val)); \ 83 [ptr] "+Q"(*(u64 *)ptr) \
88 } while (loop); \ 84 : [val] "Ir" (val)); \
89 break; \ 85 break; \
90 default: \ 86 default: \
91 BUILD_BUG(); \ 87 BUILD_BUG(); \
@@ -150,44 +146,40 @@ static inline unsigned long __percpu_xchg(void *ptr, unsigned long val,
150 146
151 switch (size) { 147 switch (size) {
152 case 1: 148 case 1:
153 do { 149 asm ("//__percpu_xchg_1\n"
154 asm ("//__percpu_xchg_1\n" 150 "1: ldxrb %w[ret], %[ptr]\n"
155 "ldxrb %w[ret], %[ptr]\n" 151 " stxrb %w[loop], %w[val], %[ptr]\n"
156 "stxrb %w[loop], %w[val], %[ptr]\n" 152 " cbnz %w[loop], 1b"
157 : [loop] "=&r"(loop), [ret] "=&r"(ret), 153 : [loop] "=&r"(loop), [ret] "=&r"(ret),
158 [ptr] "+Q"(*(u8 *)ptr) 154 [ptr] "+Q"(*(u8 *)ptr)
159 : [val] "r" (val)); 155 : [val] "r" (val));
160 } while (loop);
161 break; 156 break;
162 case 2: 157 case 2:
163 do { 158 asm ("//__percpu_xchg_2\n"
164 asm ("//__percpu_xchg_2\n" 159 "1: ldxrh %w[ret], %[ptr]\n"
165 "ldxrh %w[ret], %[ptr]\n" 160 " stxrh %w[loop], %w[val], %[ptr]\n"
166 "stxrh %w[loop], %w[val], %[ptr]\n" 161 " cbnz %w[loop], 1b"
167 : [loop] "=&r"(loop), [ret] "=&r"(ret), 162 : [loop] "=&r"(loop), [ret] "=&r"(ret),
168 [ptr] "+Q"(*(u16 *)ptr) 163 [ptr] "+Q"(*(u16 *)ptr)
169 : [val] "r" (val)); 164 : [val] "r" (val));
170 } while (loop);
171 break; 165 break;
172 case 4: 166 case 4:
173 do { 167 asm ("//__percpu_xchg_4\n"
174 asm ("//__percpu_xchg_4\n" 168 "1: ldxr %w[ret], %[ptr]\n"
175 "ldxr %w[ret], %[ptr]\n" 169 " stxr %w[loop], %w[val], %[ptr]\n"
176 "stxr %w[loop], %w[val], %[ptr]\n" 170 " cbnz %w[loop], 1b"
177 : [loop] "=&r"(loop), [ret] "=&r"(ret), 171 : [loop] "=&r"(loop), [ret] "=&r"(ret),
178 [ptr] "+Q"(*(u32 *)ptr) 172 [ptr] "+Q"(*(u32 *)ptr)
179 : [val] "r" (val)); 173 : [val] "r" (val));
180 } while (loop);
181 break; 174 break;
182 case 8: 175 case 8:
183 do { 176 asm ("//__percpu_xchg_8\n"
184 asm ("//__percpu_xchg_8\n" 177 "1: ldxr %[ret], %[ptr]\n"
185 "ldxr %[ret], %[ptr]\n" 178 " stxr %w[loop], %[val], %[ptr]\n"
186 "stxr %w[loop], %[val], %[ptr]\n" 179 " cbnz %w[loop], 1b"
187 : [loop] "=&r"(loop), [ret] "=&r"(ret), 180 : [loop] "=&r"(loop), [ret] "=&r"(ret),
188 [ptr] "+Q"(*(u64 *)ptr) 181 [ptr] "+Q"(*(u64 *)ptr)
189 : [val] "r" (val)); 182 : [val] "r" (val));
190 } while (loop);
191 break; 183 break;
192 default: 184 default:
193 BUILD_BUG(); 185 BUILD_BUG();
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index df2e53d3a969..60e34824e18c 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -188,8 +188,8 @@ static inline void spin_lock_prefetch(const void *ptr)
188 188
189#endif 189#endif
190 190
191void cpu_enable_pan(void *__unused); 191int cpu_enable_pan(void *__unused);
192void cpu_enable_uao(void *__unused); 192int cpu_enable_uao(void *__unused);
193void cpu_enable_cache_maint_trap(void *__unused); 193int cpu_enable_cache_maint_trap(void *__unused);
194 194
195#endif /* __ASM_PROCESSOR_H */ 195#endif /* __ASM_PROCESSOR_H */
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index e8d46e8e6079..6c80b3699cb8 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -286,7 +286,7 @@ asm(
286 286
287#define write_sysreg_s(v, r) do { \ 287#define write_sysreg_s(v, r) do { \
288 u64 __val = (u64)v; \ 288 u64 __val = (u64)v; \
289 asm volatile("msr_s " __stringify(r) ", %0" : : "rZ" (__val)); \ 289 asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \
290} while (0) 290} while (0)
291 291
292static inline void config_sctlr_el1(u32 clear, u32 set) 292static inline void config_sctlr_el1(u32 clear, u32 set)
diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h
index bcaf6fba1b65..55d0adbf6509 100644
--- a/arch/arm64/include/asm/uaccess.h
+++ b/arch/arm64/include/asm/uaccess.h
@@ -21,6 +21,7 @@
21/* 21/*
22 * User space memory access functions 22 * User space memory access functions
23 */ 23 */
24#include <linux/bitops.h>
24#include <linux/kasan-checks.h> 25#include <linux/kasan-checks.h>
25#include <linux/string.h> 26#include <linux/string.h>
26#include <linux/thread_info.h> 27#include <linux/thread_info.h>
@@ -102,6 +103,13 @@ static inline void set_fs(mm_segment_t fs)
102 flag; \ 103 flag; \
103}) 104})
104 105
106/*
107 * When dealing with data aborts or instruction traps we may end up with
108 * a tagged userland pointer. Clear the tag to get a sane pointer to pass
109 * on to access_ok(), for instance.
110 */
111#define untagged_addr(addr) sign_extend64(addr, 55)
112
105#define access_ok(type, addr, size) __range_ok(addr, size) 113#define access_ok(type, addr, size) __range_ok(addr, size)
106#define user_addr_max get_fs 114#define user_addr_max get_fs
107 115
diff --git a/arch/arm64/kernel/armv8_deprecated.c b/arch/arm64/kernel/armv8_deprecated.c
index 42ffdb54e162..b0988bb1bf64 100644
--- a/arch/arm64/kernel/armv8_deprecated.c
+++ b/arch/arm64/kernel/armv8_deprecated.c
@@ -280,35 +280,43 @@ static void __init register_insn_emulation_sysctl(struct ctl_table *table)
280/* 280/*
281 * Error-checking SWP macros implemented using ldxr{b}/stxr{b} 281 * Error-checking SWP macros implemented using ldxr{b}/stxr{b}
282 */ 282 */
283#define __user_swpX_asm(data, addr, res, temp, B) \ 283
284/* Arbitrary constant to ensure forward-progress of the LL/SC loop */
285#define __SWP_LL_SC_LOOPS 4
286
287#define __user_swpX_asm(data, addr, res, temp, temp2, B) \
284 __asm__ __volatile__( \ 288 __asm__ __volatile__( \
289 " mov %w3, %w7\n" \
285 ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, \ 290 ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, \
286 CONFIG_ARM64_PAN) \ 291 CONFIG_ARM64_PAN) \
287 "0: ldxr"B" %w2, [%3]\n" \ 292 "0: ldxr"B" %w2, [%4]\n" \
288 "1: stxr"B" %w0, %w1, [%3]\n" \ 293 "1: stxr"B" %w0, %w1, [%4]\n" \
289 " cbz %w0, 2f\n" \ 294 " cbz %w0, 2f\n" \
290 " mov %w0, %w4\n" \ 295 " sub %w3, %w3, #1\n" \
296 " cbnz %w3, 0b\n" \
297 " mov %w0, %w5\n" \
291 " b 3f\n" \ 298 " b 3f\n" \
292 "2:\n" \ 299 "2:\n" \
293 " mov %w1, %w2\n" \ 300 " mov %w1, %w2\n" \
294 "3:\n" \ 301 "3:\n" \
295 " .pushsection .fixup,\"ax\"\n" \ 302 " .pushsection .fixup,\"ax\"\n" \
296 " .align 2\n" \ 303 " .align 2\n" \
297 "4: mov %w0, %w5\n" \ 304 "4: mov %w0, %w6\n" \
298 " b 3b\n" \ 305 " b 3b\n" \
299 " .popsection" \ 306 " .popsection" \
300 _ASM_EXTABLE(0b, 4b) \ 307 _ASM_EXTABLE(0b, 4b) \
301 _ASM_EXTABLE(1b, 4b) \ 308 _ASM_EXTABLE(1b, 4b) \
302 ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, \ 309 ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, \
303 CONFIG_ARM64_PAN) \ 310 CONFIG_ARM64_PAN) \
304 : "=&r" (res), "+r" (data), "=&r" (temp) \ 311 : "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2) \
305 : "r" (addr), "i" (-EAGAIN), "i" (-EFAULT) \ 312 : "r" (addr), "i" (-EAGAIN), "i" (-EFAULT), \
313 "i" (__SWP_LL_SC_LOOPS) \
306 : "memory") 314 : "memory")
307 315
308#define __user_swp_asm(data, addr, res, temp) \ 316#define __user_swp_asm(data, addr, res, temp, temp2) \
309 __user_swpX_asm(data, addr, res, temp, "") 317 __user_swpX_asm(data, addr, res, temp, temp2, "")
310#define __user_swpb_asm(data, addr, res, temp) \ 318#define __user_swpb_asm(data, addr, res, temp, temp2) \
311 __user_swpX_asm(data, addr, res, temp, "b") 319 __user_swpX_asm(data, addr, res, temp, temp2, "b")
312 320
313/* 321/*
314 * Bit 22 of the instruction encoding distinguishes between 322 * Bit 22 of the instruction encoding distinguishes between
@@ -328,12 +336,12 @@ static int emulate_swpX(unsigned int address, unsigned int *data,
328 } 336 }
329 337
330 while (1) { 338 while (1) {
331 unsigned long temp; 339 unsigned long temp, temp2;
332 340
333 if (type == TYPE_SWPB) 341 if (type == TYPE_SWPB)
334 __user_swpb_asm(*data, address, res, temp); 342 __user_swpb_asm(*data, address, res, temp, temp2);
335 else 343 else
336 __user_swp_asm(*data, address, res, temp); 344 __user_swp_asm(*data, address, res, temp, temp2);
337 345
338 if (likely(res != -EAGAIN) || signal_pending(current)) 346 if (likely(res != -EAGAIN) || signal_pending(current))
339 break; 347 break;
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 0150394f4cab..b75e917aac46 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -39,10 +39,11 @@ has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry,
39 (arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask); 39 (arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask);
40} 40}
41 41
42static void cpu_enable_trap_ctr_access(void *__unused) 42static int cpu_enable_trap_ctr_access(void *__unused)
43{ 43{
44 /* Clear SCTLR_EL1.UCT */ 44 /* Clear SCTLR_EL1.UCT */
45 config_sctlr_el1(SCTLR_EL1_UCT, 0); 45 config_sctlr_el1(SCTLR_EL1_UCT, 0);
46 return 0;
46} 47}
47 48
48#define MIDR_RANGE(model, min, max) \ 49#define MIDR_RANGE(model, min, max) \
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index d577f263cc4a..c02504ea304b 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -19,7 +19,9 @@
19#define pr_fmt(fmt) "CPU features: " fmt 19#define pr_fmt(fmt) "CPU features: " fmt
20 20
21#include <linux/bsearch.h> 21#include <linux/bsearch.h>
22#include <linux/cpumask.h>
22#include <linux/sort.h> 23#include <linux/sort.h>
24#include <linux/stop_machine.h>
23#include <linux/types.h> 25#include <linux/types.h>
24#include <asm/cpu.h> 26#include <asm/cpu.h>
25#include <asm/cpufeature.h> 27#include <asm/cpufeature.h>
@@ -941,7 +943,13 @@ void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
941{ 943{
942 for (; caps->matches; caps++) 944 for (; caps->matches; caps++)
943 if (caps->enable && cpus_have_cap(caps->capability)) 945 if (caps->enable && cpus_have_cap(caps->capability))
944 on_each_cpu(caps->enable, NULL, true); 946 /*
947 * Use stop_machine() as it schedules the work allowing
948 * us to modify PSTATE, instead of on_each_cpu() which
949 * uses an IPI, giving us a PSTATE that disappears when
950 * we return.
951 */
952 stop_machine(caps->enable, NULL, cpu_online_mask);
945} 953}
946 954
947/* 955/*
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 427f6d3f084c..332e33193ccf 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -586,8 +586,9 @@ CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
586 b.lt 4f // Skip if no PMU present 586 b.lt 4f // Skip if no PMU present
587 mrs x0, pmcr_el0 // Disable debug access traps 587 mrs x0, pmcr_el0 // Disable debug access traps
588 ubfx x0, x0, #11, #5 // to EL2 and allow access to 588 ubfx x0, x0, #11, #5 // to EL2 and allow access to
589 msr mdcr_el2, x0 // all PMU counters from EL1
5904: 5894:
590 csel x0, xzr, x0, lt // all PMU counters from EL1
591 msr mdcr_el2, x0 // (if they exist)
591 592
592 /* Stage-2 translation */ 593 /* Stage-2 translation */
593 msr vttbr_el2, xzr 594 msr vttbr_el2, xzr
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 27b2f1387df4..01753cd7d3f0 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -49,6 +49,7 @@
49#include <asm/alternative.h> 49#include <asm/alternative.h>
50#include <asm/compat.h> 50#include <asm/compat.h>
51#include <asm/cacheflush.h> 51#include <asm/cacheflush.h>
52#include <asm/exec.h>
52#include <asm/fpsimd.h> 53#include <asm/fpsimd.h>
53#include <asm/mmu_context.h> 54#include <asm/mmu_context.h>
54#include <asm/processor.h> 55#include <asm/processor.h>
@@ -186,10 +187,19 @@ void __show_regs(struct pt_regs *regs)
186 printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n", 187 printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
187 regs->pc, lr, regs->pstate); 188 regs->pc, lr, regs->pstate);
188 printk("sp : %016llx\n", sp); 189 printk("sp : %016llx\n", sp);
189 for (i = top_reg; i >= 0; i--) { 190
191 i = top_reg;
192
193 while (i >= 0) {
190 printk("x%-2d: %016llx ", i, regs->regs[i]); 194 printk("x%-2d: %016llx ", i, regs->regs[i]);
191 if (i % 2 == 0) 195 i--;
192 printk("\n"); 196
197 if (i % 2 == 0) {
198 pr_cont("x%-2d: %016llx ", i, regs->regs[i]);
199 i--;
200 }
201
202 pr_cont("\n");
193 } 203 }
194 printk("\n"); 204 printk("\n");
195} 205}
@@ -301,7 +311,7 @@ static void tls_thread_switch(struct task_struct *next)
301} 311}
302 312
303/* Restore the UAO state depending on next's addr_limit */ 313/* Restore the UAO state depending on next's addr_limit */
304static void uao_thread_switch(struct task_struct *next) 314void uao_thread_switch(struct task_struct *next)
305{ 315{
306 if (IS_ENABLED(CONFIG_ARM64_UAO)) { 316 if (IS_ENABLED(CONFIG_ARM64_UAO)) {
307 if (task_thread_info(next)->addr_limit == KERNEL_DS) 317 if (task_thread_info(next)->addr_limit == KERNEL_DS)
diff --git a/arch/arm64/kernel/sleep.S b/arch/arm64/kernel/sleep.S
index b8799e7c79de..1bec41b5fda3 100644
--- a/arch/arm64/kernel/sleep.S
+++ b/arch/arm64/kernel/sleep.S
@@ -135,7 +135,7 @@ ENTRY(_cpu_resume)
135 135
136#ifdef CONFIG_KASAN 136#ifdef CONFIG_KASAN
137 mov x0, sp 137 mov x0, sp
138 bl kasan_unpoison_remaining_stack 138 bl kasan_unpoison_task_stack_below
139#endif 139#endif
140 140
141 ldp x19, x20, [x29, #16] 141 ldp x19, x20, [x29, #16]
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index d3f151cfd4a1..8507703dabe4 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -544,6 +544,7 @@ acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor)
544 return; 544 return;
545 } 545 }
546 bootcpu_valid = true; 546 bootcpu_valid = true;
547 early_map_cpu_to_node(0, acpi_numa_get_nid(0, hwid));
547 return; 548 return;
548 } 549 }
549 550
diff --git a/arch/arm64/kernel/suspend.c b/arch/arm64/kernel/suspend.c
index ad734142070d..bb0cd787a9d3 100644
--- a/arch/arm64/kernel/suspend.c
+++ b/arch/arm64/kernel/suspend.c
@@ -1,8 +1,11 @@
1#include <linux/ftrace.h> 1#include <linux/ftrace.h>
2#include <linux/percpu.h> 2#include <linux/percpu.h>
3#include <linux/slab.h> 3#include <linux/slab.h>
4#include <asm/alternative.h>
4#include <asm/cacheflush.h> 5#include <asm/cacheflush.h>
6#include <asm/cpufeature.h>
5#include <asm/debug-monitors.h> 7#include <asm/debug-monitors.h>
8#include <asm/exec.h>
6#include <asm/pgtable.h> 9#include <asm/pgtable.h>
7#include <asm/memory.h> 10#include <asm/memory.h>
8#include <asm/mmu_context.h> 11#include <asm/mmu_context.h>
@@ -50,6 +53,14 @@ void notrace __cpu_suspend_exit(void)
50 set_my_cpu_offset(per_cpu_offset(cpu)); 53 set_my_cpu_offset(per_cpu_offset(cpu));
51 54
52 /* 55 /*
56 * PSTATE was not saved over suspend/resume, re-enable any detected
57 * features that might not have been set correctly.
58 */
59 asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN,
60 CONFIG_ARM64_PAN));
61 uao_thread_switch(current);
62
63 /*
53 * Restore HW breakpoint registers to sane values 64 * Restore HW breakpoint registers to sane values
54 * before debug exceptions are possibly reenabled 65 * before debug exceptions are possibly reenabled
55 * through local_dbg_restore. 66 * through local_dbg_restore.
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index 5ff020f8fb7f..c9986b3e0a96 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -428,24 +428,28 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
428 force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0); 428 force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0);
429} 429}
430 430
431void cpu_enable_cache_maint_trap(void *__unused) 431int cpu_enable_cache_maint_trap(void *__unused)
432{ 432{
433 config_sctlr_el1(SCTLR_EL1_UCI, 0); 433 config_sctlr_el1(SCTLR_EL1_UCI, 0);
434 return 0;
434} 435}
435 436
436#define __user_cache_maint(insn, address, res) \ 437#define __user_cache_maint(insn, address, res) \
437 asm volatile ( \ 438 if (untagged_addr(address) >= user_addr_max()) \
438 "1: " insn ", %1\n" \ 439 res = -EFAULT; \
439 " mov %w0, #0\n" \ 440 else \
440 "2:\n" \ 441 asm volatile ( \
441 " .pushsection .fixup,\"ax\"\n" \ 442 "1: " insn ", %1\n" \
442 " .align 2\n" \ 443 " mov %w0, #0\n" \
443 "3: mov %w0, %w2\n" \ 444 "2:\n" \
444 " b 2b\n" \ 445 " .pushsection .fixup,\"ax\"\n" \
445 " .popsection\n" \ 446 " .align 2\n" \
446 _ASM_EXTABLE(1b, 3b) \ 447 "3: mov %w0, %w2\n" \
447 : "=r" (res) \ 448 " b 2b\n" \
448 : "r" (address), "i" (-EFAULT) ) 449 " .popsection\n" \
450 _ASM_EXTABLE(1b, 3b) \
451 : "=r" (res) \
452 : "r" (address), "i" (-EFAULT) )
449 453
450static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs) 454static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
451{ 455{
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index 53d9159662fe..0f8788374815 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -29,7 +29,9 @@
29#include <linux/sched.h> 29#include <linux/sched.h>
30#include <linux/highmem.h> 30#include <linux/highmem.h>
31#include <linux/perf_event.h> 31#include <linux/perf_event.h>
32#include <linux/preempt.h>
32 33
34#include <asm/bug.h>
33#include <asm/cpufeature.h> 35#include <asm/cpufeature.h>
34#include <asm/exception.h> 36#include <asm/exception.h>
35#include <asm/debug-monitors.h> 37#include <asm/debug-monitors.h>
@@ -670,9 +672,17 @@ asmlinkage int __exception do_debug_exception(unsigned long addr,
670NOKPROBE_SYMBOL(do_debug_exception); 672NOKPROBE_SYMBOL(do_debug_exception);
671 673
672#ifdef CONFIG_ARM64_PAN 674#ifdef CONFIG_ARM64_PAN
673void cpu_enable_pan(void *__unused) 675int cpu_enable_pan(void *__unused)
674{ 676{
677 /*
678 * We modify PSTATE. This won't work from irq context as the PSTATE
679 * is discarded once we return from the exception.
680 */
681 WARN_ON_ONCE(in_interrupt());
682
675 config_sctlr_el1(SCTLR_EL1_SPAN, 0); 683 config_sctlr_el1(SCTLR_EL1_SPAN, 0);
684 asm(SET_PSTATE_PAN(1));
685 return 0;
676} 686}
677#endif /* CONFIG_ARM64_PAN */ 687#endif /* CONFIG_ARM64_PAN */
678 688
@@ -683,8 +693,9 @@ void cpu_enable_pan(void *__unused)
683 * We need to enable the feature at runtime (instead of adding it to 693 * We need to enable the feature at runtime (instead of adding it to
684 * PSR_MODE_EL1h) as the feature may not be implemented by the cpu. 694 * PSR_MODE_EL1h) as the feature may not be implemented by the cpu.
685 */ 695 */
686void cpu_enable_uao(void *__unused) 696int cpu_enable_uao(void *__unused)
687{ 697{
688 asm(SET_PSTATE_UAO(1)); 698 asm(SET_PSTATE_UAO(1));
699 return 0;
689} 700}
690#endif /* CONFIG_ARM64_UAO */ 701#endif /* CONFIG_ARM64_UAO */
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index 21c489bdeb4e..212c4d1e2f26 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -421,35 +421,35 @@ void __init mem_init(void)
421 421
422 pr_notice("Virtual kernel memory layout:\n"); 422 pr_notice("Virtual kernel memory layout:\n");
423#ifdef CONFIG_KASAN 423#ifdef CONFIG_KASAN
424 pr_cont(" kasan : 0x%16lx - 0x%16lx (%6ld GB)\n", 424 pr_notice(" kasan : 0x%16lx - 0x%16lx (%6ld GB)\n",
425 MLG(KASAN_SHADOW_START, KASAN_SHADOW_END)); 425 MLG(KASAN_SHADOW_START, KASAN_SHADOW_END));
426#endif 426#endif
427 pr_cont(" modules : 0x%16lx - 0x%16lx (%6ld MB)\n", 427 pr_notice(" modules : 0x%16lx - 0x%16lx (%6ld MB)\n",
428 MLM(MODULES_VADDR, MODULES_END)); 428 MLM(MODULES_VADDR, MODULES_END));
429 pr_cont(" vmalloc : 0x%16lx - 0x%16lx (%6ld GB)\n", 429 pr_notice(" vmalloc : 0x%16lx - 0x%16lx (%6ld GB)\n",
430 MLG(VMALLOC_START, VMALLOC_END)); 430 MLG(VMALLOC_START, VMALLOC_END));
431 pr_cont(" .text : 0x%p" " - 0x%p" " (%6ld KB)\n", 431 pr_notice(" .text : 0x%p" " - 0x%p" " (%6ld KB)\n",
432 MLK_ROUNDUP(_text, _etext)); 432 MLK_ROUNDUP(_text, _etext));
433 pr_cont(" .rodata : 0x%p" " - 0x%p" " (%6ld KB)\n", 433 pr_notice(" .rodata : 0x%p" " - 0x%p" " (%6ld KB)\n",
434 MLK_ROUNDUP(__start_rodata, __init_begin)); 434 MLK_ROUNDUP(__start_rodata, __init_begin));
435 pr_cont(" .init : 0x%p" " - 0x%p" " (%6ld KB)\n", 435 pr_notice(" .init : 0x%p" " - 0x%p" " (%6ld KB)\n",
436 MLK_ROUNDUP(__init_begin, __init_end)); 436 MLK_ROUNDUP(__init_begin, __init_end));
437 pr_cont(" .data : 0x%p" " - 0x%p" " (%6ld KB)\n", 437 pr_notice(" .data : 0x%p" " - 0x%p" " (%6ld KB)\n",
438 MLK_ROUNDUP(_sdata, _edata)); 438 MLK_ROUNDUP(_sdata, _edata));
439 pr_cont(" .bss : 0x%p" " - 0x%p" " (%6ld KB)\n", 439 pr_notice(" .bss : 0x%p" " - 0x%p" " (%6ld KB)\n",
440 MLK_ROUNDUP(__bss_start, __bss_stop)); 440 MLK_ROUNDUP(__bss_start, __bss_stop));
441 pr_cont(" fixed : 0x%16lx - 0x%16lx (%6ld KB)\n", 441 pr_notice(" fixed : 0x%16lx - 0x%16lx (%6ld KB)\n",
442 MLK(FIXADDR_START, FIXADDR_TOP)); 442 MLK(FIXADDR_START, FIXADDR_TOP));
443 pr_cont(" PCI I/O : 0x%16lx - 0x%16lx (%6ld MB)\n", 443 pr_notice(" PCI I/O : 0x%16lx - 0x%16lx (%6ld MB)\n",
444 MLM(PCI_IO_START, PCI_IO_END)); 444 MLM(PCI_IO_START, PCI_IO_END));
445#ifdef CONFIG_SPARSEMEM_VMEMMAP 445#ifdef CONFIG_SPARSEMEM_VMEMMAP
446 pr_cont(" vmemmap : 0x%16lx - 0x%16lx (%6ld GB maximum)\n", 446 pr_notice(" vmemmap : 0x%16lx - 0x%16lx (%6ld GB maximum)\n",
447 MLG(VMEMMAP_START, VMEMMAP_START + VMEMMAP_SIZE)); 447 MLG(VMEMMAP_START, VMEMMAP_START + VMEMMAP_SIZE));
448 pr_cont(" 0x%16lx - 0x%16lx (%6ld MB actual)\n", 448 pr_notice(" 0x%16lx - 0x%16lx (%6ld MB actual)\n",
449 MLM((unsigned long)phys_to_page(memblock_start_of_DRAM()), 449 MLM((unsigned long)phys_to_page(memblock_start_of_DRAM()),
450 (unsigned long)virt_to_page(high_memory))); 450 (unsigned long)virt_to_page(high_memory)));
451#endif 451#endif
452 pr_cont(" memory : 0x%16lx - 0x%16lx (%6ld MB)\n", 452 pr_notice(" memory : 0x%16lx - 0x%16lx (%6ld MB)\n",
453 MLM(__phys_to_virt(memblock_start_of_DRAM()), 453 MLM(__phys_to_virt(memblock_start_of_DRAM()),
454 (unsigned long)high_memory)); 454 (unsigned long)high_memory));
455 455
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c
index 8b8fe671b1a6..8d79286ee4e8 100644
--- a/arch/blackfin/kernel/ptrace.c
+++ b/arch/blackfin/kernel/ptrace.c
@@ -271,7 +271,7 @@ long arch_ptrace(struct task_struct *child, long request,
271 case BFIN_MEM_ACCESS_CORE: 271 case BFIN_MEM_ACCESS_CORE:
272 case BFIN_MEM_ACCESS_CORE_ONLY: 272 case BFIN_MEM_ACCESS_CORE_ONLY:
273 copied = access_process_vm(child, addr, &tmp, 273 copied = access_process_vm(child, addr, &tmp,
274 to_copy, 0); 274 to_copy, FOLL_FORCE);
275 if (copied) 275 if (copied)
276 break; 276 break;
277 277
@@ -324,7 +324,8 @@ long arch_ptrace(struct task_struct *child, long request,
324 case BFIN_MEM_ACCESS_CORE: 324 case BFIN_MEM_ACCESS_CORE:
325 case BFIN_MEM_ACCESS_CORE_ONLY: 325 case BFIN_MEM_ACCESS_CORE_ONLY:
326 copied = access_process_vm(child, addr, &data, 326 copied = access_process_vm(child, addr, &data,
327 to_copy, 1); 327 to_copy,
328 FOLL_FORCE | FOLL_WRITE);
328 break; 329 break;
329 case BFIN_MEM_ACCESS_DMA: 330 case BFIN_MEM_ACCESS_DMA:
330 if (safe_dma_memcpy(paddr, &data, to_copy)) 331 if (safe_dma_memcpy(paddr, &data, to_copy))
diff --git a/arch/cris/arch-v32/drivers/cryptocop.c b/arch/cris/arch-v32/drivers/cryptocop.c
index b5698c876fcc..099e170a93ee 100644
--- a/arch/cris/arch-v32/drivers/cryptocop.c
+++ b/arch/cris/arch-v32/drivers/cryptocop.c
@@ -2722,7 +2722,6 @@ static int cryptocop_ioctl_process(struct inode *inode, struct file *filp, unsig
2722 err = get_user_pages((unsigned long int)(oper.indata + prev_ix), 2722 err = get_user_pages((unsigned long int)(oper.indata + prev_ix),
2723 noinpages, 2723 noinpages,
2724 0, /* read access only for in data */ 2724 0, /* read access only for in data */
2725 0, /* no force */
2726 inpages, 2725 inpages,
2727 NULL); 2726 NULL);
2728 2727
@@ -2736,8 +2735,7 @@ static int cryptocop_ioctl_process(struct inode *inode, struct file *filp, unsig
2736 if (oper.do_cipher){ 2735 if (oper.do_cipher){
2737 err = get_user_pages((unsigned long int)oper.cipher_outdata, 2736 err = get_user_pages((unsigned long int)oper.cipher_outdata,
2738 nooutpages, 2737 nooutpages,
2739 1, /* write access for out data */ 2738 FOLL_WRITE, /* write access for out data */
2740 0, /* no force */
2741 outpages, 2739 outpages,
2742 NULL); 2740 NULL);
2743 up_read(&current->mm->mmap_sem); 2741 up_read(&current->mm->mmap_sem);
diff --git a/arch/cris/arch-v32/kernel/ptrace.c b/arch/cris/arch-v32/kernel/ptrace.c
index f085229cf870..f0df654ac6fc 100644
--- a/arch/cris/arch-v32/kernel/ptrace.c
+++ b/arch/cris/arch-v32/kernel/ptrace.c
@@ -147,7 +147,7 @@ long arch_ptrace(struct task_struct *child, long request,
147 /* The trampoline page is globally mapped, no page table to traverse.*/ 147 /* The trampoline page is globally mapped, no page table to traverse.*/
148 tmp = *(unsigned long*)addr; 148 tmp = *(unsigned long*)addr;
149 } else { 149 } else {
150 copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0); 150 copied = access_process_vm(child, addr, &tmp, sizeof(tmp), FOLL_FORCE);
151 151
152 if (copied != sizeof(tmp)) 152 if (copied != sizeof(tmp))
153 break; 153 break;
@@ -279,7 +279,7 @@ static int insn_size(struct task_struct *child, unsigned long pc)
279 int opsize = 0; 279 int opsize = 0;
280 280
281 /* Read the opcode at pc (do what PTRACE_PEEKTEXT would do). */ 281 /* Read the opcode at pc (do what PTRACE_PEEKTEXT would do). */
282 copied = access_process_vm(child, pc, &opcode, sizeof(opcode), 0); 282 copied = access_process_vm(child, pc, &opcode, sizeof(opcode), FOLL_FORCE);
283 if (copied != sizeof(opcode)) 283 if (copied != sizeof(opcode))
284 return 0; 284 return 0;
285 285
diff --git a/arch/ia64/kernel/err_inject.c b/arch/ia64/kernel/err_inject.c
index 09f845793d12..5ed0ea92c5bf 100644
--- a/arch/ia64/kernel/err_inject.c
+++ b/arch/ia64/kernel/err_inject.c
@@ -142,7 +142,7 @@ store_virtual_to_phys(struct device *dev, struct device_attribute *attr,
142 u64 virt_addr=simple_strtoull(buf, NULL, 16); 142 u64 virt_addr=simple_strtoull(buf, NULL, 16);
143 int ret; 143 int ret;
144 144
145 ret = get_user_pages(virt_addr, 1, VM_READ, 0, NULL, NULL); 145 ret = get_user_pages(virt_addr, 1, FOLL_WRITE, NULL, NULL);
146 if (ret<=0) { 146 if (ret<=0) {
147#ifdef ERR_INJ_DEBUG 147#ifdef ERR_INJ_DEBUG
148 printk("Virtual address %lx is not existing.\n",virt_addr); 148 printk("Virtual address %lx is not existing.\n",virt_addr);
diff --git a/arch/ia64/kernel/ptrace.c b/arch/ia64/kernel/ptrace.c
index 6f54d511cc50..31aa8c0f68e1 100644
--- a/arch/ia64/kernel/ptrace.c
+++ b/arch/ia64/kernel/ptrace.c
@@ -453,7 +453,7 @@ ia64_peek (struct task_struct *child, struct switch_stack *child_stack,
453 return 0; 453 return 0;
454 } 454 }
455 } 455 }
456 copied = access_process_vm(child, addr, &ret, sizeof(ret), 0); 456 copied = access_process_vm(child, addr, &ret, sizeof(ret), FOLL_FORCE);
457 if (copied != sizeof(ret)) 457 if (copied != sizeof(ret))
458 return -EIO; 458 return -EIO;
459 *val = ret; 459 *val = ret;
@@ -489,7 +489,8 @@ ia64_poke (struct task_struct *child, struct switch_stack *child_stack,
489 *ia64_rse_skip_regs(krbs, regnum) = val; 489 *ia64_rse_skip_regs(krbs, regnum) = val;
490 } 490 }
491 } 491 }
492 } else if (access_process_vm(child, addr, &val, sizeof(val), 1) 492 } else if (access_process_vm(child, addr, &val, sizeof(val),
493 FOLL_FORCE | FOLL_WRITE)
493 != sizeof(val)) 494 != sizeof(val))
494 return -EIO; 495 return -EIO;
495 return 0; 496 return 0;
@@ -543,7 +544,8 @@ ia64_sync_user_rbs (struct task_struct *child, struct switch_stack *sw,
543 ret = ia64_peek(child, sw, user_rbs_end, addr, &val); 544 ret = ia64_peek(child, sw, user_rbs_end, addr, &val);
544 if (ret < 0) 545 if (ret < 0)
545 return ret; 546 return ret;
546 if (access_process_vm(child, addr, &val, sizeof(val), 1) 547 if (access_process_vm(child, addr, &val, sizeof(val),
548 FOLL_FORCE | FOLL_WRITE)
547 != sizeof(val)) 549 != sizeof(val))
548 return -EIO; 550 return -EIO;
549 } 551 }
@@ -559,7 +561,8 @@ ia64_sync_kernel_rbs (struct task_struct *child, struct switch_stack *sw,
559 561
560 /* now copy word for word from user rbs to kernel rbs: */ 562 /* now copy word for word from user rbs to kernel rbs: */
561 for (addr = user_rbs_start; addr < user_rbs_end; addr += 8) { 563 for (addr = user_rbs_start; addr < user_rbs_end; addr += 8) {
562 if (access_process_vm(child, addr, &val, sizeof(val), 0) 564 if (access_process_vm(child, addr, &val, sizeof(val),
565 FOLL_FORCE)
563 != sizeof(val)) 566 != sizeof(val))
564 return -EIO; 567 return -EIO;
565 568
@@ -1156,7 +1159,8 @@ arch_ptrace (struct task_struct *child, long request,
1156 case PTRACE_PEEKTEXT: 1159 case PTRACE_PEEKTEXT:
1157 case PTRACE_PEEKDATA: 1160 case PTRACE_PEEKDATA:
1158 /* read word at location addr */ 1161 /* read word at location addr */
1159 if (access_process_vm(child, addr, &data, sizeof(data), 0) 1162 if (access_process_vm(child, addr, &data, sizeof(data),
1163 FOLL_FORCE)
1160 != sizeof(data)) 1164 != sizeof(data))
1161 return -EIO; 1165 return -EIO;
1162 /* ensure return value is not mistaken for error code */ 1166 /* ensure return value is not mistaken for error code */
diff --git a/arch/m32r/kernel/ptrace.c b/arch/m32r/kernel/ptrace.c
index 51f5e9aa4901..c145605a981f 100644
--- a/arch/m32r/kernel/ptrace.c
+++ b/arch/m32r/kernel/ptrace.c
@@ -493,7 +493,8 @@ unregister_all_debug_traps(struct task_struct *child)
493 int i; 493 int i;
494 494
495 for (i = 0; i < p->nr_trap; i++) 495 for (i = 0; i < p->nr_trap; i++)
496 access_process_vm(child, p->addr[i], &p->insn[i], sizeof(p->insn[i]), 1); 496 access_process_vm(child, p->addr[i], &p->insn[i], sizeof(p->insn[i]),
497 FOLL_FORCE | FOLL_WRITE);
497 p->nr_trap = 0; 498 p->nr_trap = 0;
498} 499}
499 500
@@ -537,7 +538,8 @@ embed_debug_trap(struct task_struct *child, unsigned long next_pc)
537 unsigned long next_insn, code; 538 unsigned long next_insn, code;
538 unsigned long addr = next_pc & ~3; 539 unsigned long addr = next_pc & ~3;
539 540
540 if (access_process_vm(child, addr, &next_insn, sizeof(next_insn), 0) 541 if (access_process_vm(child, addr, &next_insn, sizeof(next_insn),
542 FOLL_FORCE)
541 != sizeof(next_insn)) { 543 != sizeof(next_insn)) {
542 return -1; /* error */ 544 return -1; /* error */
543 } 545 }
@@ -546,7 +548,8 @@ embed_debug_trap(struct task_struct *child, unsigned long next_pc)
546 if (register_debug_trap(child, next_pc, next_insn, &code)) { 548 if (register_debug_trap(child, next_pc, next_insn, &code)) {
547 return -1; /* error */ 549 return -1; /* error */
548 } 550 }
549 if (access_process_vm(child, addr, &code, sizeof(code), 1) 551 if (access_process_vm(child, addr, &code, sizeof(code),
552 FOLL_FORCE | FOLL_WRITE)
550 != sizeof(code)) { 553 != sizeof(code)) {
551 return -1; /* error */ 554 return -1; /* error */
552 } 555 }
@@ -562,7 +565,8 @@ withdraw_debug_trap(struct pt_regs *regs)
562 addr = (regs->bpc - 2) & ~3; 565 addr = (regs->bpc - 2) & ~3;
563 regs->bpc -= 2; 566 regs->bpc -= 2;
564 if (unregister_debug_trap(current, addr, &code)) { 567 if (unregister_debug_trap(current, addr, &code)) {
565 access_process_vm(current, addr, &code, sizeof(code), 1); 568 access_process_vm(current, addr, &code, sizeof(code),
569 FOLL_FORCE | FOLL_WRITE);
566 invalidate_cache(); 570 invalidate_cache();
567 } 571 }
568} 572}
@@ -589,7 +593,8 @@ void user_enable_single_step(struct task_struct *child)
589 /* Compute next pc. */ 593 /* Compute next pc. */
590 pc = get_stack_long(child, PT_BPC); 594 pc = get_stack_long(child, PT_BPC);
591 595
592 if (access_process_vm(child, pc&~3, &insn, sizeof(insn), 0) 596 if (access_process_vm(child, pc&~3, &insn, sizeof(insn),
597 FOLL_FORCE)
593 != sizeof(insn)) 598 != sizeof(insn))
594 return; 599 return;
595 600
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index 283b5a1967d1..7e71a4e0281b 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -70,7 +70,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
70 break; 70 break;
71 71
72 copied = access_process_vm(child, (u64)addrOthers, &tmp, 72 copied = access_process_vm(child, (u64)addrOthers, &tmp,
73 sizeof(tmp), 0); 73 sizeof(tmp), FOLL_FORCE);
74 if (copied != sizeof(tmp)) 74 if (copied != sizeof(tmp))
75 break; 75 break;
76 ret = put_user(tmp, (u32 __user *) (unsigned long) data); 76 ret = put_user(tmp, (u32 __user *) (unsigned long) data);
@@ -179,7 +179,8 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
179 break; 179 break;
180 ret = 0; 180 ret = 0;
181 if (access_process_vm(child, (u64)addrOthers, &data, 181 if (access_process_vm(child, (u64)addrOthers, &data,
182 sizeof(data), 1) == sizeof(data)) 182 sizeof(data),
183 FOLL_FORCE | FOLL_WRITE) == sizeof(data))
183 break; 184 break;
184 ret = -EIO; 185 ret = -EIO;
185 break; 186 break;
diff --git a/arch/mips/kvm/mips.c b/arch/mips/kvm/mips.c
index ce961495b5e1..622037d851a3 100644
--- a/arch/mips/kvm/mips.c
+++ b/arch/mips/kvm/mips.c
@@ -14,6 +14,7 @@
14#include <linux/err.h> 14#include <linux/err.h>
15#include <linux/kdebug.h> 15#include <linux/kdebug.h>
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/uaccess.h>
17#include <linux/vmalloc.h> 18#include <linux/vmalloc.h>
18#include <linux/fs.h> 19#include <linux/fs.h>
19#include <linux/bootmem.h> 20#include <linux/bootmem.h>
diff --git a/arch/mips/mm/gup.c b/arch/mips/mm/gup.c
index 42d124fb6474..d8c3c159289a 100644
--- a/arch/mips/mm/gup.c
+++ b/arch/mips/mm/gup.c
@@ -287,7 +287,7 @@ slow_irqon:
287 pages += nr; 287 pages += nr;
288 288
289 ret = get_user_pages_unlocked(start, (end - start) >> PAGE_SHIFT, 289 ret = get_user_pages_unlocked(start, (end - start) >> PAGE_SHIFT,
290 write, 0, pages); 290 pages, write ? FOLL_WRITE : 0);
291 291
292 /* Have to be a bit careful with return values */ 292 /* Have to be a bit careful with return values */
293 if (nr > 0) { 293 if (nr > 0) {
diff --git a/arch/powerpc/boot/main.c b/arch/powerpc/boot/main.c
index f7a184b6c35b..57d42d129033 100644
--- a/arch/powerpc/boot/main.c
+++ b/arch/powerpc/boot/main.c
@@ -32,9 +32,16 @@ static struct addr_range prep_kernel(void)
32 void *addr = 0; 32 void *addr = 0;
33 struct elf_info ei; 33 struct elf_info ei;
34 long len; 34 long len;
35 int uncompressed_image = 0;
35 36
36 partial_decompress(vmlinuz_addr, vmlinuz_size, 37 len = partial_decompress(vmlinuz_addr, vmlinuz_size,
37 elfheader, sizeof(elfheader), 0); 38 elfheader, sizeof(elfheader), 0);
39 /* assume uncompressed data if -1 is returned */
40 if (len == -1) {
41 uncompressed_image = 1;
42 memcpy(elfheader, vmlinuz_addr, sizeof(elfheader));
43 printf("No valid compressed data found, assume uncompressed data\n\r");
44 }
38 45
39 if (!parse_elf64(elfheader, &ei) && !parse_elf32(elfheader, &ei)) 46 if (!parse_elf64(elfheader, &ei) && !parse_elf32(elfheader, &ei))
40 fatal("Error: not a valid PPC32 or PPC64 ELF file!\n\r"); 47 fatal("Error: not a valid PPC32 or PPC64 ELF file!\n\r");
@@ -67,6 +74,13 @@ static struct addr_range prep_kernel(void)
67 "device tree\n\r"); 74 "device tree\n\r");
68 } 75 }
69 76
77 if (uncompressed_image) {
78 memcpy(addr, vmlinuz_addr + ei.elfoffset, ei.loadsize);
79 printf("0x%lx bytes of uncompressed data copied\n\r",
80 ei.loadsize);
81 goto out;
82 }
83
70 /* Finally, decompress the kernel */ 84 /* Finally, decompress the kernel */
71 printf("Decompressing (0x%p <- 0x%p:0x%p)...\n\r", addr, 85 printf("Decompressing (0x%p <- 0x%p:0x%p)...\n\r", addr,
72 vmlinuz_addr, vmlinuz_addr+vmlinuz_size); 86 vmlinuz_addr, vmlinuz_addr+vmlinuz_size);
@@ -82,7 +96,7 @@ static struct addr_range prep_kernel(void)
82 len, ei.loadsize); 96 len, ei.loadsize);
83 97
84 printf("Done! Decompressed 0x%lx bytes\n\r", len); 98 printf("Done! Decompressed 0x%lx bytes\n\r", len);
85 99out:
86 flush_cache(addr, ei.loadsize); 100 flush_cache(addr, ei.loadsize);
87 101
88 return (struct addr_range){addr, ei.memsize}; 102 return (struct addr_range){addr, ei.memsize};
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h
index cf12c580f6b2..e8cdfec8d512 100644
--- a/arch/powerpc/include/asm/unistd.h
+++ b/arch/powerpc/include/asm/unistd.h
@@ -16,6 +16,10 @@
16 16
17#define __NR__exit __NR_exit 17#define __NR__exit __NR_exit
18 18
19#define __IGNORE_pkey_mprotect
20#define __IGNORE_pkey_alloc
21#define __IGNORE_pkey_free
22
19#ifndef __ASSEMBLY__ 23#ifndef __ASSEMBLY__
20 24
21#include <linux/types.h> 25#include <linux/types.h>
diff --git a/arch/powerpc/kernel/ptrace32.c b/arch/powerpc/kernel/ptrace32.c
index f52b7db327c8..010b7b310237 100644
--- a/arch/powerpc/kernel/ptrace32.c
+++ b/arch/powerpc/kernel/ptrace32.c
@@ -74,7 +74,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
74 break; 74 break;
75 75
76 copied = access_process_vm(child, (u64)addrOthers, &tmp, 76 copied = access_process_vm(child, (u64)addrOthers, &tmp,
77 sizeof(tmp), 0); 77 sizeof(tmp), FOLL_FORCE);
78 if (copied != sizeof(tmp)) 78 if (copied != sizeof(tmp))
79 break; 79 break;
80 ret = put_user(tmp, (u32 __user *)data); 80 ret = put_user(tmp, (u32 __user *)data);
@@ -179,7 +179,8 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
179 break; 179 break;
180 ret = 0; 180 ret = 0;
181 if (access_process_vm(child, (u64)addrOthers, &tmp, 181 if (access_process_vm(child, (u64)addrOthers, &tmp,
182 sizeof(tmp), 1) == sizeof(tmp)) 182 sizeof(tmp),
183 FOLL_FORCE | FOLL_WRITE) == sizeof(tmp))
183 break; 184 break;
184 ret = -EIO; 185 ret = -EIO;
185 break; 186 break;
diff --git a/arch/powerpc/mm/copro_fault.c b/arch/powerpc/mm/copro_fault.c
index bb0354222b11..362954f98029 100644
--- a/arch/powerpc/mm/copro_fault.c
+++ b/arch/powerpc/mm/copro_fault.c
@@ -106,6 +106,8 @@ int copro_calculate_slb(struct mm_struct *mm, u64 ea, struct copro_slb *slb)
106 switch (REGION_ID(ea)) { 106 switch (REGION_ID(ea)) {
107 case USER_REGION_ID: 107 case USER_REGION_ID:
108 pr_devel("%s: 0x%llx -- USER_REGION_ID\n", __func__, ea); 108 pr_devel("%s: 0x%llx -- USER_REGION_ID\n", __func__, ea);
109 if (mm == NULL)
110 return 1;
109 psize = get_slice_psize(mm, ea); 111 psize = get_slice_psize(mm, ea);
110 ssize = user_segment_size(ea); 112 ssize = user_segment_size(ea);
111 vsid = get_vsid(mm->context.id, ea, ssize); 113 vsid = get_vsid(mm->context.id, ea, ssize);
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index 75b9cd6150cc..a51c188b81f3 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -845,7 +845,7 @@ void __init dump_numa_cpu_topology(void)
845 return; 845 return;
846 846
847 for_each_online_node(node) { 847 for_each_online_node(node) {
848 printk(KERN_DEBUG "Node %d CPUs:", node); 848 pr_info("Node %d CPUs:", node);
849 849
850 count = 0; 850 count = 0;
851 /* 851 /*
@@ -856,52 +856,18 @@ void __init dump_numa_cpu_topology(void)
856 if (cpumask_test_cpu(cpu, 856 if (cpumask_test_cpu(cpu,
857 node_to_cpumask_map[node])) { 857 node_to_cpumask_map[node])) {
858 if (count == 0) 858 if (count == 0)
859 printk(" %u", cpu); 859 pr_cont(" %u", cpu);
860 ++count; 860 ++count;
861 } else { 861 } else {
862 if (count > 1) 862 if (count > 1)
863 printk("-%u", cpu - 1); 863 pr_cont("-%u", cpu - 1);
864 count = 0; 864 count = 0;
865 } 865 }
866 } 866 }
867 867
868 if (count > 1) 868 if (count > 1)
869 printk("-%u", nr_cpu_ids - 1); 869 pr_cont("-%u", nr_cpu_ids - 1);
870 printk("\n"); 870 pr_cont("\n");
871 }
872}
873
874static void __init dump_numa_memory_topology(void)
875{
876 unsigned int node;
877 unsigned int count;
878
879 if (min_common_depth == -1 || !numa_enabled)
880 return;
881
882 for_each_online_node(node) {
883 unsigned long i;
884
885 printk(KERN_DEBUG "Node %d Memory:", node);
886
887 count = 0;
888
889 for (i = 0; i < memblock_end_of_DRAM();
890 i += (1 << SECTION_SIZE_BITS)) {
891 if (early_pfn_to_nid(i >> PAGE_SHIFT) == node) {
892 if (count == 0)
893 printk(" 0x%lx", i);
894 ++count;
895 } else {
896 if (count > 0)
897 printk("-0x%lx", i);
898 count = 0;
899 }
900 }
901
902 if (count > 0)
903 printk("-0x%lx", i);
904 printk("\n");
905 } 871 }
906} 872}
907 873
@@ -947,8 +913,6 @@ void __init initmem_init(void)
947 913
948 if (parse_numa_properties()) 914 if (parse_numa_properties())
949 setup_nonnuma(); 915 setup_nonnuma();
950 else
951 dump_numa_memory_topology();
952 916
953 memblock_dump_all(); 917 memblock_dump_all();
954 918
diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c
index 1cab8a177d0e..7a27eebab28a 100644
--- a/arch/s390/kvm/intercept.c
+++ b/arch/s390/kvm/intercept.c
@@ -119,8 +119,13 @@ static int handle_validity(struct kvm_vcpu *vcpu)
119 119
120 vcpu->stat.exit_validity++; 120 vcpu->stat.exit_validity++;
121 trace_kvm_s390_intercept_validity(vcpu, viwhy); 121 trace_kvm_s390_intercept_validity(vcpu, viwhy);
122 WARN_ONCE(true, "kvm: unhandled validity intercept 0x%x\n", viwhy); 122 KVM_EVENT(3, "validity intercept 0x%x for pid %u (kvm 0x%pK)", viwhy,
123 return -EOPNOTSUPP; 123 current->pid, vcpu->kvm);
124
125 /* do not warn on invalid runtime instrumentation mode */
126 WARN_ONCE(viwhy != 0x44, "kvm: unhandled validity intercept 0x%x\n",
127 viwhy);
128 return -EINVAL;
124} 129}
125 130
126static int handle_instruction(struct kvm_vcpu *vcpu) 131static int handle_instruction(struct kvm_vcpu *vcpu)
diff --git a/arch/s390/mm/gup.c b/arch/s390/mm/gup.c
index adb0c34bf431..18d4107e10ee 100644
--- a/arch/s390/mm/gup.c
+++ b/arch/s390/mm/gup.c
@@ -266,7 +266,8 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write,
266 /* Try to get the remaining pages with get_user_pages */ 266 /* Try to get the remaining pages with get_user_pages */
267 start += nr << PAGE_SHIFT; 267 start += nr << PAGE_SHIFT;
268 pages += nr; 268 pages += nr;
269 ret = get_user_pages_unlocked(start, nr_pages - nr, write, 0, pages); 269 ret = get_user_pages_unlocked(start, nr_pages - nr, pages,
270 write ? FOLL_WRITE : 0);
270 /* Have to be a bit careful with return values */ 271 /* Have to be a bit careful with return values */
271 if (nr > 0) 272 if (nr > 0)
272 ret = (ret < 0) ? nr : ret + nr; 273 ret = (ret < 0) ? nr : ret + nr;
diff --git a/arch/score/kernel/ptrace.c b/arch/score/kernel/ptrace.c
index 55836188b217..4f7314d5f334 100644
--- a/arch/score/kernel/ptrace.c
+++ b/arch/score/kernel/ptrace.c
@@ -131,7 +131,7 @@ read_tsk_long(struct task_struct *child,
131{ 131{
132 int copied; 132 int copied;
133 133
134 copied = access_process_vm(child, addr, res, sizeof(*res), 0); 134 copied = access_process_vm(child, addr, res, sizeof(*res), FOLL_FORCE);
135 135
136 return copied != sizeof(*res) ? -EIO : 0; 136 return copied != sizeof(*res) ? -EIO : 0;
137} 137}
@@ -142,7 +142,7 @@ read_tsk_short(struct task_struct *child,
142{ 142{
143 int copied; 143 int copied;
144 144
145 copied = access_process_vm(child, addr, res, sizeof(*res), 0); 145 copied = access_process_vm(child, addr, res, sizeof(*res), FOLL_FORCE);
146 146
147 return copied != sizeof(*res) ? -EIO : 0; 147 return copied != sizeof(*res) ? -EIO : 0;
148} 148}
@@ -153,7 +153,8 @@ write_tsk_short(struct task_struct *child,
153{ 153{
154 int copied; 154 int copied;
155 155
156 copied = access_process_vm(child, addr, &val, sizeof(val), 1); 156 copied = access_process_vm(child, addr, &val, sizeof(val),
157 FOLL_FORCE | FOLL_WRITE);
157 158
158 return copied != sizeof(val) ? -EIO : 0; 159 return copied != sizeof(val) ? -EIO : 0;
159} 160}
@@ -164,7 +165,8 @@ write_tsk_long(struct task_struct *child,
164{ 165{
165 int copied; 166 int copied;
166 167
167 copied = access_process_vm(child, addr, &val, sizeof(val), 1); 168 copied = access_process_vm(child, addr, &val, sizeof(val),
169 FOLL_FORCE | FOLL_WRITE);
168 170
169 return copied != sizeof(val) ? -EIO : 0; 171 return copied != sizeof(val) ? -EIO : 0;
170} 172}
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index 00476662ac2c..336f33a419d9 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -31,7 +31,7 @@ isa-y := $(isa-y)-up
31endif 31endif
32 32
33cflags-$(CONFIG_CPU_SH2) := $(call cc-option,-m2,) 33cflags-$(CONFIG_CPU_SH2) := $(call cc-option,-m2,)
34cflags-$(CONFIG_CPU_J2) := $(call cc-option,-mj2,) 34cflags-$(CONFIG_CPU_J2) += $(call cc-option,-mj2,)
35cflags-$(CONFIG_CPU_SH2A) += $(call cc-option,-m2a,) \ 35cflags-$(CONFIG_CPU_SH2A) += $(call cc-option,-m2a,) \
36 $(call cc-option,-m2a-nofpu,) \ 36 $(call cc-option,-m2a-nofpu,) \
37 $(call cc-option,-m4-nofpu,) 37 $(call cc-option,-m4-nofpu,)
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig
index e9c2c42031fe..4e21949593cf 100644
--- a/arch/sh/boards/Kconfig
+++ b/arch/sh/boards/Kconfig
@@ -22,6 +22,16 @@ config SH_DEVICE_TREE
22 have sufficient driver coverage to use this option; do not 22 have sufficient driver coverage to use this option; do not
23 select it if you are using original SuperH hardware. 23 select it if you are using original SuperH hardware.
24 24
25config SH_JCORE_SOC
26 bool "J-Core SoC"
27 depends on SH_DEVICE_TREE && (CPU_SH2 || CPU_J2)
28 select CLKSRC_JCORE_PIT
29 select JCORE_AIC
30 default y if CPU_J2
31 help
32 Select this option to include drivers core components of the
33 J-Core SoC, including interrupt controllers and timers.
34
25config SH_SOLUTION_ENGINE 35config SH_SOLUTION_ENGINE
26 bool "SolutionEngine" 36 bool "SolutionEngine"
27 select SOLUTION_ENGINE 37 select SOLUTION_ENGINE
diff --git a/arch/sh/configs/j2_defconfig b/arch/sh/configs/j2_defconfig
index 94d1eca52f72..2eb81ebe3888 100644
--- a/arch/sh/configs/j2_defconfig
+++ b/arch/sh/configs/j2_defconfig
@@ -8,6 +8,7 @@ CONFIG_MEMORY_START=0x10000000
8CONFIG_MEMORY_SIZE=0x04000000 8CONFIG_MEMORY_SIZE=0x04000000
9CONFIG_CPU_BIG_ENDIAN=y 9CONFIG_CPU_BIG_ENDIAN=y
10CONFIG_SH_DEVICE_TREE=y 10CONFIG_SH_DEVICE_TREE=y
11CONFIG_SH_JCORE_SOC=y
11CONFIG_HZ_100=y 12CONFIG_HZ_100=y
12CONFIG_CMDLINE_OVERWRITE=y 13CONFIG_CMDLINE_OVERWRITE=y
13CONFIG_CMDLINE="console=ttyUL0 earlycon" 14CONFIG_CMDLINE="console=ttyUL0 earlycon"
@@ -20,6 +21,7 @@ CONFIG_INET=y
20CONFIG_DEVTMPFS=y 21CONFIG_DEVTMPFS=y
21CONFIG_DEVTMPFS_MOUNT=y 22CONFIG_DEVTMPFS_MOUNT=y
22CONFIG_NETDEVICES=y 23CONFIG_NETDEVICES=y
24CONFIG_SERIAL_EARLYCON=y
23CONFIG_SERIAL_UARTLITE=y 25CONFIG_SERIAL_UARTLITE=y
24CONFIG_SERIAL_UARTLITE_CONSOLE=y 26CONFIG_SERIAL_UARTLITE_CONSOLE=y
25CONFIG_I2C=y 27CONFIG_I2C=y
diff --git a/arch/sh/mm/gup.c b/arch/sh/mm/gup.c
index 40fa6c8adc43..063c298ba56c 100644
--- a/arch/sh/mm/gup.c
+++ b/arch/sh/mm/gup.c
@@ -258,7 +258,8 @@ slow_irqon:
258 pages += nr; 258 pages += nr;
259 259
260 ret = get_user_pages_unlocked(start, 260 ret = get_user_pages_unlocked(start,
261 (end - start) >> PAGE_SHIFT, write, 0, pages); 261 (end - start) >> PAGE_SHIFT, pages,
262 write ? FOLL_WRITE : 0);
262 263
263 /* Have to be a bit careful with return values */ 264 /* Have to be a bit careful with return values */
264 if (nr > 0) { 265 if (nr > 0) {
diff --git a/arch/sparc/kernel/ptrace_64.c b/arch/sparc/kernel/ptrace_64.c
index 9ddc4928a089..ac082dd8c67d 100644
--- a/arch/sparc/kernel/ptrace_64.c
+++ b/arch/sparc/kernel/ptrace_64.c
@@ -127,7 +127,8 @@ static int get_from_target(struct task_struct *target, unsigned long uaddr,
127 if (copy_from_user(kbuf, (void __user *) uaddr, len)) 127 if (copy_from_user(kbuf, (void __user *) uaddr, len))
128 return -EFAULT; 128 return -EFAULT;
129 } else { 129 } else {
130 int len2 = access_process_vm(target, uaddr, kbuf, len, 0); 130 int len2 = access_process_vm(target, uaddr, kbuf, len,
131 FOLL_FORCE);
131 if (len2 != len) 132 if (len2 != len)
132 return -EFAULT; 133 return -EFAULT;
133 } 134 }
@@ -141,7 +142,8 @@ static int set_to_target(struct task_struct *target, unsigned long uaddr,
141 if (copy_to_user((void __user *) uaddr, kbuf, len)) 142 if (copy_to_user((void __user *) uaddr, kbuf, len))
142 return -EFAULT; 143 return -EFAULT;
143 } else { 144 } else {
144 int len2 = access_process_vm(target, uaddr, kbuf, len, 1); 145 int len2 = access_process_vm(target, uaddr, kbuf, len,
146 FOLL_FORCE | FOLL_WRITE);
145 if (len2 != len) 147 if (len2 != len)
146 return -EFAULT; 148 return -EFAULT;
147 } 149 }
@@ -505,7 +507,8 @@ static int genregs32_get(struct task_struct *target,
505 if (access_process_vm(target, 507 if (access_process_vm(target,
506 (unsigned long) 508 (unsigned long)
507 &reg_window[pos], 509 &reg_window[pos],
508 k, sizeof(*k), 0) 510 k, sizeof(*k),
511 FOLL_FORCE)
509 != sizeof(*k)) 512 != sizeof(*k))
510 return -EFAULT; 513 return -EFAULT;
511 k++; 514 k++;
@@ -531,12 +534,14 @@ static int genregs32_get(struct task_struct *target,
531 if (access_process_vm(target, 534 if (access_process_vm(target,
532 (unsigned long) 535 (unsigned long)
533 &reg_window[pos], 536 &reg_window[pos],
534 &reg, sizeof(reg), 0) 537 &reg, sizeof(reg),
538 FOLL_FORCE)
535 != sizeof(reg)) 539 != sizeof(reg))
536 return -EFAULT; 540 return -EFAULT;
537 if (access_process_vm(target, 541 if (access_process_vm(target,
538 (unsigned long) u, 542 (unsigned long) u,
539 &reg, sizeof(reg), 1) 543 &reg, sizeof(reg),
544 FOLL_FORCE | FOLL_WRITE)
540 != sizeof(reg)) 545 != sizeof(reg))
541 return -EFAULT; 546 return -EFAULT;
542 pos++; 547 pos++;
@@ -615,7 +620,8 @@ static int genregs32_set(struct task_struct *target,
615 (unsigned long) 620 (unsigned long)
616 &reg_window[pos], 621 &reg_window[pos],
617 (void *) k, 622 (void *) k,
618 sizeof(*k), 1) 623 sizeof(*k),
624 FOLL_FORCE | FOLL_WRITE)
619 != sizeof(*k)) 625 != sizeof(*k))
620 return -EFAULT; 626 return -EFAULT;
621 k++; 627 k++;
@@ -642,13 +648,15 @@ static int genregs32_set(struct task_struct *target,
642 if (access_process_vm(target, 648 if (access_process_vm(target,
643 (unsigned long) 649 (unsigned long)
644 u, 650 u,
645 &reg, sizeof(reg), 0) 651 &reg, sizeof(reg),
652 FOLL_FORCE)
646 != sizeof(reg)) 653 != sizeof(reg))
647 return -EFAULT; 654 return -EFAULT;
648 if (access_process_vm(target, 655 if (access_process_vm(target,
649 (unsigned long) 656 (unsigned long)
650 &reg_window[pos], 657 &reg_window[pos],
651 &reg, sizeof(reg), 1) 658 &reg, sizeof(reg),
659 FOLL_FORCE | FOLL_WRITE)
652 != sizeof(reg)) 660 != sizeof(reg))
653 return -EFAULT; 661 return -EFAULT;
654 pos++; 662 pos++;
diff --git a/arch/sparc/mm/gup.c b/arch/sparc/mm/gup.c
index 4e06750a5d29..cd0e32bbcb1d 100644
--- a/arch/sparc/mm/gup.c
+++ b/arch/sparc/mm/gup.c
@@ -238,7 +238,8 @@ slow:
238 pages += nr; 238 pages += nr;
239 239
240 ret = get_user_pages_unlocked(start, 240 ret = get_user_pages_unlocked(start,
241 (end - start) >> PAGE_SHIFT, write, 0, pages); 241 (end - start) >> PAGE_SHIFT, pages,
242 write ? FOLL_WRITE : 0);
242 243
243 /* Have to be a bit careful with return values */ 244 /* Have to be a bit careful with return values */
244 if (nr > 0) { 245 if (nr > 0) {
diff --git a/arch/x86/entry/syscalls/syscall_32.tbl b/arch/x86/entry/syscalls/syscall_32.tbl
index ff6ef7b30822..2b3618542544 100644
--- a/arch/x86/entry/syscalls/syscall_32.tbl
+++ b/arch/x86/entry/syscalls/syscall_32.tbl
@@ -389,5 +389,3 @@
389380 i386 pkey_mprotect sys_pkey_mprotect 389380 i386 pkey_mprotect sys_pkey_mprotect
390381 i386 pkey_alloc sys_pkey_alloc 390381 i386 pkey_alloc sys_pkey_alloc
391382 i386 pkey_free sys_pkey_free 391382 i386 pkey_free sys_pkey_free
392#383 i386 pkey_get sys_pkey_get
393#384 i386 pkey_set sys_pkey_set
diff --git a/arch/x86/entry/syscalls/syscall_64.tbl b/arch/x86/entry/syscalls/syscall_64.tbl
index 2f024d02511d..e93ef0b38db8 100644
--- a/arch/x86/entry/syscalls/syscall_64.tbl
+++ b/arch/x86/entry/syscalls/syscall_64.tbl
@@ -338,8 +338,6 @@
338329 common pkey_mprotect sys_pkey_mprotect 338329 common pkey_mprotect sys_pkey_mprotect
339330 common pkey_alloc sys_pkey_alloc 339330 common pkey_alloc sys_pkey_alloc
340331 common pkey_free sys_pkey_free 340331 common pkey_free sys_pkey_free
341#332 common pkey_get sys_pkey_get
342#333 common pkey_set sys_pkey_set
343 341
344# 342#
345# x32-specific system call numbers start at 512 to avoid cache impact 343# x32-specific system call numbers start at 512 to avoid cache impact
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index a3a9eb84b5cf..eab0915f5995 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3898,6 +3898,7 @@ __init int intel_pmu_init(void)
3898 break; 3898 break;
3899 3899
3900 case INTEL_FAM6_XEON_PHI_KNL: 3900 case INTEL_FAM6_XEON_PHI_KNL:
3901 case INTEL_FAM6_XEON_PHI_KNM:
3901 memcpy(hw_cache_event_ids, 3902 memcpy(hw_cache_event_ids,
3902 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 3903 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3903 memcpy(hw_cache_extra_regs, 3904 memcpy(hw_cache_extra_regs,
@@ -3912,7 +3913,7 @@ __init int intel_pmu_init(void)
3912 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 3913 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3913 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 3914 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3914 3915
3915 pr_cont("Knights Landing events, "); 3916 pr_cont("Knights Landing/Mill events, ");
3916 break; 3917 break;
3917 3918
3918 case INTEL_FAM6_SKYLAKE_MOBILE: 3919 case INTEL_FAM6_SKYLAKE_MOBILE:
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index fc6cf21c535e..81b321ace8e0 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -458,8 +458,8 @@ void intel_pmu_lbr_del(struct perf_event *event)
458 if (!x86_pmu.lbr_nr) 458 if (!x86_pmu.lbr_nr)
459 return; 459 return;
460 460
461 if (branch_user_callstack(cpuc->br_sel) && event->ctx && 461 if (branch_user_callstack(cpuc->br_sel) &&
462 event->ctx->task_ctx_data) { 462 event->ctx->task_ctx_data) {
463 task_ctx = event->ctx->task_ctx_data; 463 task_ctx = event->ctx->task_ctx_data;
464 task_ctx->lbr_callstack_users--; 464 task_ctx->lbr_callstack_users--;
465 } 465 }
diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c
index b0f0e835a770..0a535cea8ff3 100644
--- a/arch/x86/events/intel/rapl.c
+++ b/arch/x86/events/intel/rapl.c
@@ -763,6 +763,7 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = {
763 X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_XEON_D, hsw_rapl_init), 763 X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_XEON_D, hsw_rapl_init),
764 764
765 X86_RAPL_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNL, knl_rapl_init), 765 X86_RAPL_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNL, knl_rapl_init),
766 X86_RAPL_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNM, knl_rapl_init),
766 767
767 X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_MOBILE, skl_rapl_init), 768 X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_MOBILE, skl_rapl_init),
768 X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_DESKTOP, skl_rapl_init), 769 X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_DESKTOP, skl_rapl_init),
diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
index d9844cc74486..efca2685d876 100644
--- a/arch/x86/events/intel/uncore.c
+++ b/arch/x86/events/intel/uncore.c
@@ -1349,6 +1349,7 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = {
1349 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_X, bdx_uncore_init), 1349 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_X, bdx_uncore_init),
1350 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_XEON_D, bdx_uncore_init), 1350 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_XEON_D, bdx_uncore_init),
1351 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNL, knl_uncore_init), 1351 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNL, knl_uncore_init),
1352 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNM, knl_uncore_init),
1352 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE_DESKTOP,skl_uncore_init), 1353 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE_DESKTOP,skl_uncore_init),
1353 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE_MOBILE, skl_uncore_init), 1354 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE_MOBILE, skl_uncore_init),
1354 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE_X, skx_uncore_init), 1355 X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE_X, skx_uncore_init),
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 1188bc849ee3..a39629206864 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -194,6 +194,8 @@
194#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ 194#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
195 195
196#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ 196#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
197#define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */
198#define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */
197 199
198/* Virtualization flags: Linux defined, word 8 */ 200/* Virtualization flags: Linux defined, word 8 */
199#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ 201#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index 9ae5ab80a497..34a46dc076d3 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -64,5 +64,6 @@
64/* Xeon Phi */ 64/* Xeon Phi */
65 65
66#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */ 66#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */
67#define INTEL_FAM6_XEON_PHI_KNM 0x85 /* Knights Mill */
67 68
68#endif /* _ASM_X86_INTEL_FAMILY_H */ 69#endif /* _ASM_X86_INTEL_FAMILY_H */
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 56f4c6676b29..78f3760ca1f2 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -88,7 +88,6 @@
88 88
89#define MSR_IA32_RTIT_CTL 0x00000570 89#define MSR_IA32_RTIT_CTL 0x00000570
90#define MSR_IA32_RTIT_STATUS 0x00000571 90#define MSR_IA32_RTIT_STATUS 0x00000571
91#define MSR_IA32_RTIT_STATUS 0x00000571
92#define MSR_IA32_RTIT_ADDR0_A 0x00000580 91#define MSR_IA32_RTIT_ADDR0_A 0x00000580
93#define MSR_IA32_RTIT_ADDR0_B 0x00000581 92#define MSR_IA32_RTIT_ADDR0_B 0x00000581
94#define MSR_IA32_RTIT_ADDR1_A 0x00000582 93#define MSR_IA32_RTIT_ADDR1_A 0x00000582
diff --git a/arch/x86/include/asm/rwsem.h b/arch/x86/include/asm/rwsem.h
index 3d33a719f5c1..a34e0d4b957d 100644
--- a/arch/x86/include/asm/rwsem.h
+++ b/arch/x86/include/asm/rwsem.h
@@ -103,8 +103,10 @@ static inline bool __down_read_trylock(struct rw_semaphore *sem)
103({ \ 103({ \
104 long tmp; \ 104 long tmp; \
105 struct rw_semaphore* ret; \ 105 struct rw_semaphore* ret; \
106 register void *__sp asm(_ASM_SP); \
107 \
106 asm volatile("# beginning down_write\n\t" \ 108 asm volatile("# beginning down_write\n\t" \
107 LOCK_PREFIX " xadd %1,(%3)\n\t" \ 109 LOCK_PREFIX " xadd %1,(%4)\n\t" \
108 /* adds 0xffff0001, returns the old value */ \ 110 /* adds 0xffff0001, returns the old value */ \
109 " test " __ASM_SEL(%w1,%k1) "," __ASM_SEL(%w1,%k1) "\n\t" \ 111 " test " __ASM_SEL(%w1,%k1) "," __ASM_SEL(%w1,%k1) "\n\t" \
110 /* was the active mask 0 before? */\ 112 /* was the active mask 0 before? */\
@@ -112,7 +114,7 @@ static inline bool __down_read_trylock(struct rw_semaphore *sem)
112 " call " slow_path "\n" \ 114 " call " slow_path "\n" \
113 "1:\n" \ 115 "1:\n" \
114 "# ending down_write" \ 116 "# ending down_write" \
115 : "+m" (sem->count), "=d" (tmp), "=a" (ret) \ 117 : "+m" (sem->count), "=d" (tmp), "=a" (ret), "+r" (__sp) \
116 : "a" (sem), "1" (RWSEM_ACTIVE_WRITE_BIAS) \ 118 : "a" (sem), "1" (RWSEM_ACTIVE_WRITE_BIAS) \
117 : "memory", "cc"); \ 119 : "memory", "cc"); \
118 ret; \ 120 ret; \
diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
index 2aaca53c0974..ad6f5eb07a95 100644
--- a/arch/x86/include/asm/thread_info.h
+++ b/arch/x86/include/asm/thread_info.h
@@ -52,6 +52,15 @@ struct task_struct;
52#include <asm/cpufeature.h> 52#include <asm/cpufeature.h>
53#include <linux/atomic.h> 53#include <linux/atomic.h>
54 54
55struct thread_info {
56 unsigned long flags; /* low level flags */
57};
58
59#define INIT_THREAD_INFO(tsk) \
60{ \
61 .flags = 0, \
62}
63
55#define init_stack (init_thread_union.stack) 64#define init_stack (init_thread_union.stack)
56 65
57#else /* !__ASSEMBLY__ */ 66#else /* !__ASSEMBLY__ */
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 8cb57df9398d..1db8dc490b66 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -32,6 +32,8 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
32 32
33 static const struct cpuid_bit cpuid_bits[] = { 33 static const struct cpuid_bit cpuid_bits[] = {
34 { X86_FEATURE_INTEL_PT, CR_EBX,25, 0x00000007, 0 }, 34 { X86_FEATURE_INTEL_PT, CR_EBX,25, 0x00000007, 0 },
35 { X86_FEATURE_AVX512_4VNNIW, CR_EDX, 2, 0x00000007, 0 },
36 { X86_FEATURE_AVX512_4FMAPS, CR_EDX, 3, 0x00000007, 0 },
35 { X86_FEATURE_APERFMPERF, CR_ECX, 0, 0x00000006, 0 }, 37 { X86_FEATURE_APERFMPERF, CR_ECX, 0, 0x00000006, 0 },
36 { X86_FEATURE_EPB, CR_ECX, 3, 0x00000006, 0 }, 38 { X86_FEATURE_EPB, CR_ECX, 3, 0x00000006, 0 },
37 { X86_FEATURE_HW_PSTATE, CR_EDX, 7, 0x80000007, 0 }, 39 { X86_FEATURE_HW_PSTATE, CR_EDX, 7, 0x80000007, 0 },
diff --git a/arch/x86/kernel/cpu/vmware.c b/arch/x86/kernel/cpu/vmware.c
index 81160578b91a..5130985b758b 100644
--- a/arch/x86/kernel/cpu/vmware.c
+++ b/arch/x86/kernel/cpu/vmware.c
@@ -27,6 +27,7 @@
27#include <asm/div64.h> 27#include <asm/div64.h>
28#include <asm/x86_init.h> 28#include <asm/x86_init.h>
29#include <asm/hypervisor.h> 29#include <asm/hypervisor.h>
30#include <asm/timer.h>
30#include <asm/apic.h> 31#include <asm/apic.h>
31 32
32#define CPUID_VMWARE_INFO_LEAF 0x40000000 33#define CPUID_VMWARE_INFO_LEAF 0x40000000
@@ -94,6 +95,10 @@ static void __init vmware_platform_setup(void)
94 } else { 95 } else {
95 pr_warn("Failed to get TSC freq from the hypervisor\n"); 96 pr_warn("Failed to get TSC freq from the hypervisor\n");
96 } 97 }
98
99#ifdef CONFIG_X86_IO_APIC
100 no_timer_check = 1;
101#endif
97} 102}
98 103
99/* 104/*
diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c
index b85fe5f91c3f..90e8dde3ec26 100644
--- a/arch/x86/kernel/e820.c
+++ b/arch/x86/kernel/e820.c
@@ -350,7 +350,7 @@ int __init sanitize_e820_map(struct e820entry *biosmap, int max_nr_map,
350 * continue building up new bios map based on this 350 * continue building up new bios map based on this
351 * information 351 * information
352 */ 352 */
353 if (current_type != last_type) { 353 if (current_type != last_type || current_type == E820_PRAM) {
354 if (last_type != 0) { 354 if (last_type != 0) {
355 new_bios[new_bios_entry].size = 355 new_bios[new_bios_entry].size =
356 change_point[chgidx]->addr - last_addr; 356 change_point[chgidx]->addr - last_addr;
diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
index 124aa5c593f8..095ef7ddd6ae 100644
--- a/arch/x86/kernel/fpu/xstate.c
+++ b/arch/x86/kernel/fpu/xstate.c
@@ -74,6 +74,8 @@ void fpu__xstate_clear_all_cpu_caps(void)
74 setup_clear_cpu_cap(X86_FEATURE_MPX); 74 setup_clear_cpu_cap(X86_FEATURE_MPX);
75 setup_clear_cpu_cap(X86_FEATURE_XGETBV1); 75 setup_clear_cpu_cap(X86_FEATURE_XGETBV1);
76 setup_clear_cpu_cap(X86_FEATURE_PKU); 76 setup_clear_cpu_cap(X86_FEATURE_PKU);
77 setup_clear_cpu_cap(X86_FEATURE_AVX512_4VNNIW);
78 setup_clear_cpu_cap(X86_FEATURE_AVX512_4FMAPS);
77} 79}
78 80
79/* 81/*
diff --git a/arch/x86/kernel/kprobes/core.c b/arch/x86/kernel/kprobes/core.c
index 28cee019209c..d9d8d16b69db 100644
--- a/arch/x86/kernel/kprobes/core.c
+++ b/arch/x86/kernel/kprobes/core.c
@@ -50,6 +50,7 @@
50#include <linux/kallsyms.h> 50#include <linux/kallsyms.h>
51#include <linux/ftrace.h> 51#include <linux/ftrace.h>
52#include <linux/frame.h> 52#include <linux/frame.h>
53#include <linux/kasan.h>
53 54
54#include <asm/text-patching.h> 55#include <asm/text-patching.h>
55#include <asm/cacheflush.h> 56#include <asm/cacheflush.h>
@@ -1057,9 +1058,10 @@ int setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs)
1057 * tailcall optimization. So, to be absolutely safe 1058 * tailcall optimization. So, to be absolutely safe
1058 * we also save and restore enough stack bytes to cover 1059 * we also save and restore enough stack bytes to cover
1059 * the argument area. 1060 * the argument area.
1061 * Use __memcpy() to avoid KASAN stack out-of-bounds reports as we copy
1062 * raw stack chunk with redzones:
1060 */ 1063 */
1061 memcpy(kcb->jprobes_stack, (kprobe_opcode_t *)addr, 1064 __memcpy(kcb->jprobes_stack, (kprobe_opcode_t *)addr, MIN_STACK_SIZE(addr));
1062 MIN_STACK_SIZE(addr));
1063 regs->flags &= ~X86_EFLAGS_IF; 1065 regs->flags &= ~X86_EFLAGS_IF;
1064 trace_hardirqs_off(); 1066 trace_hardirqs_off();
1065 regs->ip = (unsigned long)(jp->entry); 1067 regs->ip = (unsigned long)(jp->entry);
@@ -1080,6 +1082,9 @@ void jprobe_return(void)
1080{ 1082{
1081 struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); 1083 struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
1082 1084
1085 /* Unpoison stack redzones in the frames we are going to jump over. */
1086 kasan_unpoison_stack_above_sp_to(kcb->jprobe_saved_sp);
1087
1083 asm volatile ( 1088 asm volatile (
1084#ifdef CONFIG_X86_64 1089#ifdef CONFIG_X86_64
1085 " xchg %%rbx,%%rsp \n" 1090 " xchg %%rbx,%%rsp \n"
@@ -1118,7 +1123,7 @@ int longjmp_break_handler(struct kprobe *p, struct pt_regs *regs)
1118 /* It's OK to start function graph tracing again */ 1123 /* It's OK to start function graph tracing again */
1119 unpause_graph_tracing(); 1124 unpause_graph_tracing();
1120 *regs = kcb->jprobe_saved_regs; 1125 *regs = kcb->jprobe_saved_regs;
1121 memcpy(saved_sp, kcb->jprobes_stack, MIN_STACK_SIZE(saved_sp)); 1126 __memcpy(saved_sp, kcb->jprobes_stack, MIN_STACK_SIZE(saved_sp));
1122 preempt_enable_no_resched(); 1127 preempt_enable_no_resched();
1123 return 1; 1128 return 1;
1124 } 1129 }
diff --git a/arch/x86/kernel/signal_compat.c b/arch/x86/kernel/signal_compat.c
index 40df33753bae..ec1f756f9dc9 100644
--- a/arch/x86/kernel/signal_compat.c
+++ b/arch/x86/kernel/signal_compat.c
@@ -105,9 +105,6 @@ void sigaction_compat_abi(struct k_sigaction *act, struct k_sigaction *oact)
105 /* Don't let flags to be set from userspace */ 105 /* Don't let flags to be set from userspace */
106 act->sa.sa_flags &= ~(SA_IA32_ABI | SA_X32_ABI); 106 act->sa.sa_flags &= ~(SA_IA32_ABI | SA_X32_ABI);
107 107
108 if (user_64bit_mode(current_pt_regs()))
109 return;
110
111 if (in_ia32_syscall()) 108 if (in_ia32_syscall())
112 act->sa.sa_flags |= SA_IA32_ABI; 109 act->sa.sa_flags |= SA_IA32_ABI;
113 if (in_x32_syscall()) 110 if (in_x32_syscall())
diff --git a/arch/x86/kernel/smp.c b/arch/x86/kernel/smp.c
index 68f8cc222f25..c00cb64bc0a1 100644
--- a/arch/x86/kernel/smp.c
+++ b/arch/x86/kernel/smp.c
@@ -261,8 +261,10 @@ static inline void __smp_reschedule_interrupt(void)
261 261
262__visible void smp_reschedule_interrupt(struct pt_regs *regs) 262__visible void smp_reschedule_interrupt(struct pt_regs *regs)
263{ 263{
264 irq_enter();
264 ack_APIC_irq(); 265 ack_APIC_irq();
265 __smp_reschedule_interrupt(); 266 __smp_reschedule_interrupt();
267 irq_exit();
266 /* 268 /*
267 * KVM uses this interrupt to force a cpu out of guest mode 269 * KVM uses this interrupt to force a cpu out of guest mode
268 */ 270 */
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 951f093a96fe..42f5eb7b4f6c 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -1409,15 +1409,17 @@ __init void prefill_possible_map(void)
1409 1409
1410 /* No boot processor was found in mptable or ACPI MADT */ 1410 /* No boot processor was found in mptable or ACPI MADT */
1411 if (!num_processors) { 1411 if (!num_processors) {
1412 int apicid = boot_cpu_physical_apicid; 1412 if (boot_cpu_has(X86_FEATURE_APIC)) {
1413 int cpu = hard_smp_processor_id(); 1413 int apicid = boot_cpu_physical_apicid;
1414 int cpu = hard_smp_processor_id();
1414 1415
1415 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1416 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1416 1417
1417 /* Make sure boot cpu is enumerated */ 1418 /* Make sure boot cpu is enumerated */
1418 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1419 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1419 apic->apic_id_valid(apicid)) 1420 apic->apic_id_valid(apicid))
1420 generic_processor_info(apicid, boot_cpu_apic_version); 1421 generic_processor_info(apicid, boot_cpu_apic_version);
1422 }
1421 1423
1422 if (!num_processors) 1424 if (!num_processors)
1423 num_processors = 1; 1425 num_processors = 1;
diff --git a/arch/x86/kernel/step.c b/arch/x86/kernel/step.c
index c9a073866ca7..a23ce84a3f6c 100644
--- a/arch/x86/kernel/step.c
+++ b/arch/x86/kernel/step.c
@@ -57,7 +57,8 @@ static int is_setting_trap_flag(struct task_struct *child, struct pt_regs *regs)
57 unsigned char opcode[15]; 57 unsigned char opcode[15];
58 unsigned long addr = convert_ip_to_linear(child, regs); 58 unsigned long addr = convert_ip_to_linear(child, regs);
59 59
60 copied = access_process_vm(child, addr, opcode, sizeof(opcode), 0); 60 copied = access_process_vm(child, addr, opcode, sizeof(opcode),
61 FOLL_FORCE);
61 for (i = 0; i < copied; i++) { 62 for (i = 0; i < copied; i++) {
62 switch (opcode[i]) { 63 switch (opcode[i]) {
63 /* popf and iret */ 64 /* popf and iret */
diff --git a/arch/x86/kvm/ioapic.c b/arch/x86/kvm/ioapic.c
index c7220ba94aa7..1a22de70f7f7 100644
--- a/arch/x86/kvm/ioapic.c
+++ b/arch/x86/kvm/ioapic.c
@@ -594,7 +594,7 @@ static void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
594 ioapic->irr = 0; 594 ioapic->irr = 0;
595 ioapic->irr_delivered = 0; 595 ioapic->irr_delivered = 0;
596 ioapic->id = 0; 596 ioapic->id = 0;
597 memset(ioapic->irq_eoi, 0x00, IOAPIC_NUM_PINS); 597 memset(ioapic->irq_eoi, 0x00, sizeof(ioapic->irq_eoi));
598 rtc_irq_eoi_tracking_reset(ioapic); 598 rtc_irq_eoi_tracking_reset(ioapic);
599} 599}
600 600
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 6c633de84dd7..e375235d81c9 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -5733,13 +5733,13 @@ static int kvmclock_cpu_online(unsigned int cpu)
5733 5733
5734static void kvm_timer_init(void) 5734static void kvm_timer_init(void)
5735{ 5735{
5736 int cpu;
5737
5738 max_tsc_khz = tsc_khz; 5736 max_tsc_khz = tsc_khz;
5739 5737
5740 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 5738 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5741#ifdef CONFIG_CPU_FREQ 5739#ifdef CONFIG_CPU_FREQ
5742 struct cpufreq_policy policy; 5740 struct cpufreq_policy policy;
5741 int cpu;
5742
5743 memset(&policy, 0, sizeof(policy)); 5743 memset(&policy, 0, sizeof(policy));
5744 cpu = get_cpu(); 5744 cpu = get_cpu();
5745 cpufreq_get_policy(&policy, cpu); 5745 cpufreq_get_policy(&policy, cpu);
diff --git a/arch/x86/mm/gup.c b/arch/x86/mm/gup.c
index b8b6a60b32cf..0d4fb3ebbbac 100644
--- a/arch/x86/mm/gup.c
+++ b/arch/x86/mm/gup.c
@@ -435,7 +435,7 @@ slow_irqon:
435 435
436 ret = get_user_pages_unlocked(start, 436 ret = get_user_pages_unlocked(start,
437 (end - start) >> PAGE_SHIFT, 437 (end - start) >> PAGE_SHIFT,
438 write, 0, pages); 438 pages, write ? FOLL_WRITE : 0);
439 439
440 /* Have to be a bit careful with return values */ 440 /* Have to be a bit careful with return values */
441 if (nr > 0) { 441 if (nr > 0) {
diff --git a/arch/x86/mm/mpx.c b/arch/x86/mm/mpx.c
index 80476878eb4c..e4f800999b32 100644
--- a/arch/x86/mm/mpx.c
+++ b/arch/x86/mm/mpx.c
@@ -544,10 +544,9 @@ static int mpx_resolve_fault(long __user *addr, int write)
544{ 544{
545 long gup_ret; 545 long gup_ret;
546 int nr_pages = 1; 546 int nr_pages = 1;
547 int force = 0;
548 547
549 gup_ret = get_user_pages((unsigned long)addr, nr_pages, write, 548 gup_ret = get_user_pages((unsigned long)addr, nr_pages,
550 force, NULL, NULL); 549 write ? FOLL_WRITE : 0, NULL, NULL);
551 /* 550 /*
552 * get_user_pages() returns number of pages gotten. 551 * get_user_pages() returns number of pages gotten.
553 * 0 means we failed to fault in and get anything, 552 * 0 means we failed to fault in and get anything,
diff --git a/arch/x86/platform/uv/bios_uv.c b/arch/x86/platform/uv/bios_uv.c
index b4d5e95fe4df..4a6a5a26c582 100644
--- a/arch/x86/platform/uv/bios_uv.c
+++ b/arch/x86/platform/uv/bios_uv.c
@@ -40,7 +40,15 @@ s64 uv_bios_call(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3, u64 a4, u64 a5)
40 */ 40 */
41 return BIOS_STATUS_UNIMPLEMENTED; 41 return BIOS_STATUS_UNIMPLEMENTED;
42 42
43 ret = efi_call_virt_pointer(tab, function, (u64)which, a1, a2, a3, a4, a5); 43 /*
44 * If EFI_OLD_MEMMAP is set, we need to fall back to using our old EFI
45 * callback method, which uses efi_call() directly, with the kernel page tables:
46 */
47 if (unlikely(test_bit(EFI_OLD_MEMMAP, &efi.flags)))
48 ret = efi_call((void *)__va(tab->function), (u64)which, a1, a2, a3, a4, a5);
49 else
50 ret = efi_call_virt_pointer(tab, function, (u64)which, a1, a2, a3, a4, a5);
51
44 return ret; 52 return ret;
45} 53}
46EXPORT_SYMBOL_GPL(uv_bios_call); 54EXPORT_SYMBOL_GPL(uv_bios_call);
diff --git a/arch/x86/um/ptrace_32.c b/arch/x86/um/ptrace_32.c
index 5766ead6fdb9..60a5a5a85505 100644
--- a/arch/x86/um/ptrace_32.c
+++ b/arch/x86/um/ptrace_32.c
@@ -36,7 +36,8 @@ int is_syscall(unsigned long addr)
36 * slow, but that doesn't matter, since it will be called only 36 * slow, but that doesn't matter, since it will be called only
37 * in case of singlestepping, if copy_from_user failed. 37 * in case of singlestepping, if copy_from_user failed.
38 */ 38 */
39 n = access_process_vm(current, addr, &instr, sizeof(instr), 0); 39 n = access_process_vm(current, addr, &instr, sizeof(instr),
40 FOLL_FORCE);
40 if (n != sizeof(instr)) { 41 if (n != sizeof(instr)) {
41 printk(KERN_ERR "is_syscall : failed to read " 42 printk(KERN_ERR "is_syscall : failed to read "
42 "instruction from 0x%lx\n", addr); 43 "instruction from 0x%lx\n", addr);
diff --git a/arch/x86/um/ptrace_64.c b/arch/x86/um/ptrace_64.c
index 0b5c184dd5b3..e30202b1716e 100644
--- a/arch/x86/um/ptrace_64.c
+++ b/arch/x86/um/ptrace_64.c
@@ -212,7 +212,8 @@ int is_syscall(unsigned long addr)
212 * slow, but that doesn't matter, since it will be called only 212 * slow, but that doesn't matter, since it will be called only
213 * in case of singlestepping, if copy_from_user failed. 213 * in case of singlestepping, if copy_from_user failed.
214 */ 214 */
215 n = access_process_vm(current, addr, &instr, sizeof(instr), 0); 215 n = access_process_vm(current, addr, &instr, sizeof(instr),
216 FOLL_FORCE);
216 if (n != sizeof(instr)) { 217 if (n != sizeof(instr)) {
217 printk("is_syscall : failed to read instruction from " 218 printk("is_syscall : failed to read instruction from "
218 "0x%lx\n", addr); 219 "0x%lx\n", addr);
diff --git a/block/badblocks.c b/block/badblocks.c
index 7be53cb1cc3c..6610e282a03e 100644
--- a/block/badblocks.c
+++ b/block/badblocks.c
@@ -354,7 +354,8 @@ int badblocks_clear(struct badblocks *bb, sector_t s, int sectors)
354 * current range. Earlier ranges could also overlap, 354 * current range. Earlier ranges could also overlap,
355 * but only this one can overlap the end of the range. 355 * but only this one can overlap the end of the range.
356 */ 356 */
357 if (BB_OFFSET(p[lo]) + BB_LEN(p[lo]) > target) { 357 if ((BB_OFFSET(p[lo]) + BB_LEN(p[lo]) > target) &&
358 (BB_OFFSET(p[lo]) < target)) {
358 /* Partial overlap, leave the tail of this range */ 359 /* Partial overlap, leave the tail of this range */
359 int ack = BB_ACK(p[lo]); 360 int ack = BB_ACK(p[lo]);
360 sector_t a = BB_OFFSET(p[lo]); 361 sector_t a = BB_OFFSET(p[lo]);
@@ -377,7 +378,8 @@ int badblocks_clear(struct badblocks *bb, sector_t s, int sectors)
377 lo--; 378 lo--;
378 } 379 }
379 while (lo >= 0 && 380 while (lo >= 0 &&
380 BB_OFFSET(p[lo]) + BB_LEN(p[lo]) > s) { 381 (BB_OFFSET(p[lo]) + BB_LEN(p[lo]) > s) &&
382 (BB_OFFSET(p[lo]) < target)) {
381 /* This range does overlap */ 383 /* This range does overlap */
382 if (BB_OFFSET(p[lo]) < s) { 384 if (BB_OFFSET(p[lo]) < s) {
383 /* Keep the early parts of this range. */ 385 /* Keep the early parts of this range. */
diff --git a/drivers/Makefile b/drivers/Makefile
index f0afdfb3c7df..194d20bee7dc 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -21,7 +21,7 @@ obj-y += video/
21obj-y += idle/ 21obj-y += idle/
22 22
23# IPMI must come before ACPI in order to provide IPMI opregion support 23# IPMI must come before ACPI in order to provide IPMI opregion support
24obj-$(CONFIG_IPMI_HANDLER) += char/ipmi/ 24obj-y += char/ipmi/
25 25
26obj-$(CONFIG_ACPI) += acpi/ 26obj-$(CONFIG_ACPI) += acpi/
27obj-$(CONFIG_SFI) += sfi/ 27obj-$(CONFIG_SFI) += sfi/
diff --git a/drivers/block/rbd.c b/drivers/block/rbd.c
index abb71628ab61..7b274ff4632c 100644
--- a/drivers/block/rbd.c
+++ b/drivers/block/rbd.c
@@ -415,15 +415,15 @@ struct rbd_device {
415}; 415};
416 416
417/* 417/*
418 * Flag bits for rbd_dev->flags. If atomicity is required, 418 * Flag bits for rbd_dev->flags:
419 * rbd_dev->lock is used to protect access. 419 * - REMOVING (which is coupled with rbd_dev->open_count) is protected
420 * 420 * by rbd_dev->lock
421 * Currently, only the "removing" flag (which is coupled with the 421 * - BLACKLISTED is protected by rbd_dev->lock_rwsem
422 * "open_count" field) requires atomic access.
423 */ 422 */
424enum rbd_dev_flags { 423enum rbd_dev_flags {
425 RBD_DEV_FLAG_EXISTS, /* mapped snapshot has not been deleted */ 424 RBD_DEV_FLAG_EXISTS, /* mapped snapshot has not been deleted */
426 RBD_DEV_FLAG_REMOVING, /* this mapping is being removed */ 425 RBD_DEV_FLAG_REMOVING, /* this mapping is being removed */
426 RBD_DEV_FLAG_BLACKLISTED, /* our ceph_client is blacklisted */
427}; 427};
428 428
429static DEFINE_MUTEX(client_mutex); /* Serialize client creation */ 429static DEFINE_MUTEX(client_mutex); /* Serialize client creation */
@@ -3926,6 +3926,7 @@ static void rbd_reregister_watch(struct work_struct *work)
3926 struct rbd_device *rbd_dev = container_of(to_delayed_work(work), 3926 struct rbd_device *rbd_dev = container_of(to_delayed_work(work),
3927 struct rbd_device, watch_dwork); 3927 struct rbd_device, watch_dwork);
3928 bool was_lock_owner = false; 3928 bool was_lock_owner = false;
3929 bool need_to_wake = false;
3929 int ret; 3930 int ret;
3930 3931
3931 dout("%s rbd_dev %p\n", __func__, rbd_dev); 3932 dout("%s rbd_dev %p\n", __func__, rbd_dev);
@@ -3935,19 +3936,27 @@ static void rbd_reregister_watch(struct work_struct *work)
3935 was_lock_owner = rbd_release_lock(rbd_dev); 3936 was_lock_owner = rbd_release_lock(rbd_dev);
3936 3937
3937 mutex_lock(&rbd_dev->watch_mutex); 3938 mutex_lock(&rbd_dev->watch_mutex);
3938 if (rbd_dev->watch_state != RBD_WATCH_STATE_ERROR) 3939 if (rbd_dev->watch_state != RBD_WATCH_STATE_ERROR) {
3939 goto fail_unlock; 3940 mutex_unlock(&rbd_dev->watch_mutex);
3941 goto out;
3942 }
3940 3943
3941 ret = __rbd_register_watch(rbd_dev); 3944 ret = __rbd_register_watch(rbd_dev);
3942 if (ret) { 3945 if (ret) {
3943 rbd_warn(rbd_dev, "failed to reregister watch: %d", ret); 3946 rbd_warn(rbd_dev, "failed to reregister watch: %d", ret);
3944 if (ret != -EBLACKLISTED) 3947 if (ret == -EBLACKLISTED || ret == -ENOENT) {
3948 set_bit(RBD_DEV_FLAG_BLACKLISTED, &rbd_dev->flags);
3949 need_to_wake = true;
3950 } else {
3945 queue_delayed_work(rbd_dev->task_wq, 3951 queue_delayed_work(rbd_dev->task_wq,
3946 &rbd_dev->watch_dwork, 3952 &rbd_dev->watch_dwork,
3947 RBD_RETRY_DELAY); 3953 RBD_RETRY_DELAY);
3948 goto fail_unlock; 3954 }
3955 mutex_unlock(&rbd_dev->watch_mutex);
3956 goto out;
3949 } 3957 }
3950 3958
3959 need_to_wake = true;
3951 rbd_dev->watch_state = RBD_WATCH_STATE_REGISTERED; 3960 rbd_dev->watch_state = RBD_WATCH_STATE_REGISTERED;
3952 rbd_dev->watch_cookie = rbd_dev->watch_handle->linger_id; 3961 rbd_dev->watch_cookie = rbd_dev->watch_handle->linger_id;
3953 mutex_unlock(&rbd_dev->watch_mutex); 3962 mutex_unlock(&rbd_dev->watch_mutex);
@@ -3963,13 +3972,10 @@ static void rbd_reregister_watch(struct work_struct *work)
3963 ret); 3972 ret);
3964 } 3973 }
3965 3974
3975out:
3966 up_write(&rbd_dev->lock_rwsem); 3976 up_write(&rbd_dev->lock_rwsem);
3967 wake_requests(rbd_dev, true); 3977 if (need_to_wake)
3968 return; 3978 wake_requests(rbd_dev, true);
3969
3970fail_unlock:
3971 mutex_unlock(&rbd_dev->watch_mutex);
3972 up_write(&rbd_dev->lock_rwsem);
3973} 3979}
3974 3980
3975/* 3981/*
@@ -4074,7 +4080,9 @@ static void rbd_wait_state_locked(struct rbd_device *rbd_dev)
4074 up_read(&rbd_dev->lock_rwsem); 4080 up_read(&rbd_dev->lock_rwsem);
4075 schedule(); 4081 schedule();
4076 down_read(&rbd_dev->lock_rwsem); 4082 down_read(&rbd_dev->lock_rwsem);
4077 } while (rbd_dev->lock_state != RBD_LOCK_STATE_LOCKED); 4083 } while (rbd_dev->lock_state != RBD_LOCK_STATE_LOCKED &&
4084 !test_bit(RBD_DEV_FLAG_BLACKLISTED, &rbd_dev->flags));
4085
4078 finish_wait(&rbd_dev->lock_waitq, &wait); 4086 finish_wait(&rbd_dev->lock_waitq, &wait);
4079} 4087}
4080 4088
@@ -4166,8 +4174,16 @@ static void rbd_queue_workfn(struct work_struct *work)
4166 4174
4167 if (must_be_locked) { 4175 if (must_be_locked) {
4168 down_read(&rbd_dev->lock_rwsem); 4176 down_read(&rbd_dev->lock_rwsem);
4169 if (rbd_dev->lock_state != RBD_LOCK_STATE_LOCKED) 4177 if (rbd_dev->lock_state != RBD_LOCK_STATE_LOCKED &&
4178 !test_bit(RBD_DEV_FLAG_BLACKLISTED, &rbd_dev->flags))
4170 rbd_wait_state_locked(rbd_dev); 4179 rbd_wait_state_locked(rbd_dev);
4180
4181 WARN_ON((rbd_dev->lock_state == RBD_LOCK_STATE_LOCKED) ^
4182 !test_bit(RBD_DEV_FLAG_BLACKLISTED, &rbd_dev->flags));
4183 if (test_bit(RBD_DEV_FLAG_BLACKLISTED, &rbd_dev->flags)) {
4184 result = -EBLACKLISTED;
4185 goto err_unlock;
4186 }
4171 } 4187 }
4172 4188
4173 img_request = rbd_img_request_create(rbd_dev, offset, length, op_type, 4189 img_request = rbd_img_request_create(rbd_dev, offset, length, op_type,
diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
index 890082315054..231633328dfa 100644
--- a/drivers/bus/arm-cci.c
+++ b/drivers/bus/arm-cci.c
@@ -2190,6 +2190,9 @@ static int cci_probe_ports(struct device_node *np)
2190 if (!of_match_node(arm_cci_ctrl_if_matches, cp)) 2190 if (!of_match_node(arm_cci_ctrl_if_matches, cp))
2191 continue; 2191 continue;
2192 2192
2193 if (!of_device_is_available(cp))
2194 continue;
2195
2193 i = nb_ace + nb_ace_lite; 2196 i = nb_ace + nb_ace_lite;
2194 2197
2195 if (i >= nb_cci_ports) 2198 if (i >= nb_cci_ports)
@@ -2232,6 +2235,13 @@ static int cci_probe_ports(struct device_node *np)
2232 ports[i].dn = cp; 2235 ports[i].dn = cp;
2233 } 2236 }
2234 2237
2238 /*
2239 * If there is no CCI port that is under kernel control
2240 * return early and report probe status.
2241 */
2242 if (!nb_ace && !nb_ace_lite)
2243 return -ENODEV;
2244
2235 /* initialize a stashed array of ACE ports to speed-up look-up */ 2245 /* initialize a stashed array of ACE ports to speed-up look-up */
2236 cci_ace_init_ports(); 2246 cci_ace_init_ports();
2237 2247
diff --git a/drivers/char/ipmi/Kconfig b/drivers/char/ipmi/Kconfig
index 5a9350b1069a..7f816655cbbf 100644
--- a/drivers/char/ipmi/Kconfig
+++ b/drivers/char/ipmi/Kconfig
@@ -76,3 +76,11 @@ config IPMI_POWEROFF
76 the IPMI management controller is capable of this. 76 the IPMI management controller is capable of this.
77 77
78endif # IPMI_HANDLER 78endif # IPMI_HANDLER
79
80config ASPEED_BT_IPMI_BMC
81 depends on ARCH_ASPEED
82 tristate "BT IPMI bmc driver"
83 help
84 Provides a driver for the BT (Block Transfer) IPMI interface
85 found on Aspeed SOCs (AST2400 and AST2500). The driver
86 implements the BMC side of the BT interface.
diff --git a/drivers/char/ipmi/Makefile b/drivers/char/ipmi/Makefile
index f3ffde1f5f1f..0d98cd91def1 100644
--- a/drivers/char/ipmi/Makefile
+++ b/drivers/char/ipmi/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_IPMI_SSIF) += ipmi_ssif.o
11obj-$(CONFIG_IPMI_POWERNV) += ipmi_powernv.o 11obj-$(CONFIG_IPMI_POWERNV) += ipmi_powernv.o
12obj-$(CONFIG_IPMI_WATCHDOG) += ipmi_watchdog.o 12obj-$(CONFIG_IPMI_WATCHDOG) += ipmi_watchdog.o
13obj-$(CONFIG_IPMI_POWEROFF) += ipmi_poweroff.o 13obj-$(CONFIG_IPMI_POWEROFF) += ipmi_poweroff.o
14obj-$(CONFIG_ASPEED_BT_IPMI_BMC) += bt-bmc.o
diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c
new file mode 100644
index 000000000000..b49e61320952
--- /dev/null
+++ b/drivers/char/ipmi/bt-bmc.c
@@ -0,0 +1,505 @@
1/*
2 * Copyright (c) 2015-2016, IBM Corporation.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#include <linux/atomic.h>
11#include <linux/bt-bmc.h>
12#include <linux/errno.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/miscdevice.h>
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/poll.h>
19#include <linux/sched.h>
20#include <linux/timer.h>
21
22/*
23 * This is a BMC device used to communicate to the host
24 */
25#define DEVICE_NAME "ipmi-bt-host"
26
27#define BT_IO_BASE 0xe4
28#define BT_IRQ 10
29
30#define BT_CR0 0x0
31#define BT_CR0_IO_BASE 16
32#define BT_CR0_IRQ 12
33#define BT_CR0_EN_CLR_SLV_RDP 0x8
34#define BT_CR0_EN_CLR_SLV_WRP 0x4
35#define BT_CR0_ENABLE_IBT 0x1
36#define BT_CR1 0x4
37#define BT_CR1_IRQ_H2B 0x01
38#define BT_CR1_IRQ_HBUSY 0x40
39#define BT_CR2 0x8
40#define BT_CR2_IRQ_H2B 0x01
41#define BT_CR2_IRQ_HBUSY 0x40
42#define BT_CR3 0xc
43#define BT_CTRL 0x10
44#define BT_CTRL_B_BUSY 0x80
45#define BT_CTRL_H_BUSY 0x40
46#define BT_CTRL_OEM0 0x20
47#define BT_CTRL_SMS_ATN 0x10
48#define BT_CTRL_B2H_ATN 0x08
49#define BT_CTRL_H2B_ATN 0x04
50#define BT_CTRL_CLR_RD_PTR 0x02
51#define BT_CTRL_CLR_WR_PTR 0x01
52#define BT_BMC2HOST 0x14
53#define BT_INTMASK 0x18
54#define BT_INTMASK_B2H_IRQEN 0x01
55#define BT_INTMASK_B2H_IRQ 0x02
56#define BT_INTMASK_BMC_HWRST 0x80
57
58#define BT_BMC_BUFFER_SIZE 256
59
60struct bt_bmc {
61 struct device dev;
62 struct miscdevice miscdev;
63 void __iomem *base;
64 int irq;
65 wait_queue_head_t queue;
66 struct timer_list poll_timer;
67 struct mutex mutex;
68};
69
70static atomic_t open_count = ATOMIC_INIT(0);
71
72static u8 bt_inb(struct bt_bmc *bt_bmc, int reg)
73{
74 return ioread8(bt_bmc->base + reg);
75}
76
77static void bt_outb(struct bt_bmc *bt_bmc, u8 data, int reg)
78{
79 iowrite8(data, bt_bmc->base + reg);
80}
81
82static void clr_rd_ptr(struct bt_bmc *bt_bmc)
83{
84 bt_outb(bt_bmc, BT_CTRL_CLR_RD_PTR, BT_CTRL);
85}
86
87static void clr_wr_ptr(struct bt_bmc *bt_bmc)
88{
89 bt_outb(bt_bmc, BT_CTRL_CLR_WR_PTR, BT_CTRL);
90}
91
92static void clr_h2b_atn(struct bt_bmc *bt_bmc)
93{
94 bt_outb(bt_bmc, BT_CTRL_H2B_ATN, BT_CTRL);
95}
96
97static void set_b_busy(struct bt_bmc *bt_bmc)
98{
99 if (!(bt_inb(bt_bmc, BT_CTRL) & BT_CTRL_B_BUSY))
100 bt_outb(bt_bmc, BT_CTRL_B_BUSY, BT_CTRL);
101}
102
103static void clr_b_busy(struct bt_bmc *bt_bmc)
104{
105 if (bt_inb(bt_bmc, BT_CTRL) & BT_CTRL_B_BUSY)
106 bt_outb(bt_bmc, BT_CTRL_B_BUSY, BT_CTRL);
107}
108
109static void set_b2h_atn(struct bt_bmc *bt_bmc)
110{
111 bt_outb(bt_bmc, BT_CTRL_B2H_ATN, BT_CTRL);
112}
113
114static u8 bt_read(struct bt_bmc *bt_bmc)
115{
116 return bt_inb(bt_bmc, BT_BMC2HOST);
117}
118
119static ssize_t bt_readn(struct bt_bmc *bt_bmc, u8 *buf, size_t n)
120{
121 int i;
122
123 for (i = 0; i < n; i++)
124 buf[i] = bt_read(bt_bmc);
125 return n;
126}
127
128static void bt_write(struct bt_bmc *bt_bmc, u8 c)
129{
130 bt_outb(bt_bmc, c, BT_BMC2HOST);
131}
132
133static ssize_t bt_writen(struct bt_bmc *bt_bmc, u8 *buf, size_t n)
134{
135 int i;
136
137 for (i = 0; i < n; i++)
138 bt_write(bt_bmc, buf[i]);
139 return n;
140}
141
142static void set_sms_atn(struct bt_bmc *bt_bmc)
143{
144 bt_outb(bt_bmc, BT_CTRL_SMS_ATN, BT_CTRL);
145}
146
147static struct bt_bmc *file_bt_bmc(struct file *file)
148{
149 return container_of(file->private_data, struct bt_bmc, miscdev);
150}
151
152static int bt_bmc_open(struct inode *inode, struct file *file)
153{
154 struct bt_bmc *bt_bmc = file_bt_bmc(file);
155
156 if (atomic_inc_return(&open_count) == 1) {
157 clr_b_busy(bt_bmc);
158 return 0;
159 }
160
161 atomic_dec(&open_count);
162 return -EBUSY;
163}
164
165/*
166 * The BT (Block Transfer) interface means that entire messages are
167 * buffered by the host before a notification is sent to the BMC that
168 * there is data to be read. The first byte is the length and the
169 * message data follows. The read operation just tries to capture the
170 * whole before returning it to userspace.
171 *
172 * BT Message format :
173 *
174 * Byte 1 Byte 2 Byte 3 Byte 4 Byte 5:N
175 * Length NetFn/LUN Seq Cmd Data
176 *
177 */
178static ssize_t bt_bmc_read(struct file *file, char __user *buf,
179 size_t count, loff_t *ppos)
180{
181 struct bt_bmc *bt_bmc = file_bt_bmc(file);
182 u8 len;
183 int len_byte = 1;
184 u8 kbuffer[BT_BMC_BUFFER_SIZE];
185 ssize_t ret = 0;
186 ssize_t nread;
187
188 if (!access_ok(VERIFY_WRITE, buf, count))
189 return -EFAULT;
190
191 WARN_ON(*ppos);
192
193 if (wait_event_interruptible(bt_bmc->queue,
194 bt_inb(bt_bmc, BT_CTRL) & BT_CTRL_H2B_ATN))
195 return -ERESTARTSYS;
196
197 mutex_lock(&bt_bmc->mutex);
198
199 if (unlikely(!(bt_inb(bt_bmc, BT_CTRL) & BT_CTRL_H2B_ATN))) {
200 ret = -EIO;
201 goto out_unlock;
202 }
203
204 set_b_busy(bt_bmc);
205 clr_h2b_atn(bt_bmc);
206 clr_rd_ptr(bt_bmc);
207
208 /*
209 * The BT frames start with the message length, which does not
210 * include the length byte.
211 */
212 kbuffer[0] = bt_read(bt_bmc);
213 len = kbuffer[0];
214
215 /* We pass the length back to userspace as well */
216 if (len + 1 > count)
217 len = count - 1;
218
219 while (len) {
220 nread = min_t(ssize_t, len, sizeof(kbuffer) - len_byte);
221
222 bt_readn(bt_bmc, kbuffer + len_byte, nread);
223
224 if (copy_to_user(buf, kbuffer, nread + len_byte)) {
225 ret = -EFAULT;
226 break;
227 }
228 len -= nread;
229 buf += nread + len_byte;
230 ret += nread + len_byte;
231 len_byte = 0;
232 }
233
234 clr_b_busy(bt_bmc);
235
236out_unlock:
237 mutex_unlock(&bt_bmc->mutex);
238 return ret;
239}
240
241/*
242 * BT Message response format :
243 *
244 * Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6:N
245 * Length NetFn/LUN Seq Cmd Code Data
246 */
247static ssize_t bt_bmc_write(struct file *file, const char __user *buf,
248 size_t count, loff_t *ppos)
249{
250 struct bt_bmc *bt_bmc = file_bt_bmc(file);
251 u8 kbuffer[BT_BMC_BUFFER_SIZE];
252 ssize_t ret = 0;
253 ssize_t nwritten;
254
255 /*
256 * send a minimum response size
257 */
258 if (count < 5)
259 return -EINVAL;
260
261 if (!access_ok(VERIFY_READ, buf, count))
262 return -EFAULT;
263
264 WARN_ON(*ppos);
265
266 /*
267 * There's no interrupt for clearing bmc busy so we have to
268 * poll
269 */
270 if (wait_event_interruptible(bt_bmc->queue,
271 !(bt_inb(bt_bmc, BT_CTRL) &
272 (BT_CTRL_H_BUSY | BT_CTRL_B2H_ATN))))
273 return -ERESTARTSYS;
274
275 mutex_lock(&bt_bmc->mutex);
276
277 if (unlikely(bt_inb(bt_bmc, BT_CTRL) &
278 (BT_CTRL_H_BUSY | BT_CTRL_B2H_ATN))) {
279 ret = -EIO;
280 goto out_unlock;
281 }
282
283 clr_wr_ptr(bt_bmc);
284
285 while (count) {
286 nwritten = min_t(ssize_t, count, sizeof(kbuffer));
287 if (copy_from_user(&kbuffer, buf, nwritten)) {
288 ret = -EFAULT;
289 break;
290 }
291
292 bt_writen(bt_bmc, kbuffer, nwritten);
293
294 count -= nwritten;
295 buf += nwritten;
296 ret += nwritten;
297 }
298
299 set_b2h_atn(bt_bmc);
300
301out_unlock:
302 mutex_unlock(&bt_bmc->mutex);
303 return ret;
304}
305
306static long bt_bmc_ioctl(struct file *file, unsigned int cmd,
307 unsigned long param)
308{
309 struct bt_bmc *bt_bmc = file_bt_bmc(file);
310
311 switch (cmd) {
312 case BT_BMC_IOCTL_SMS_ATN:
313 set_sms_atn(bt_bmc);
314 return 0;
315 }
316 return -EINVAL;
317}
318
319static int bt_bmc_release(struct inode *inode, struct file *file)
320{
321 struct bt_bmc *bt_bmc = file_bt_bmc(file);
322
323 atomic_dec(&open_count);
324 set_b_busy(bt_bmc);
325 return 0;
326}
327
328static unsigned int bt_bmc_poll(struct file *file, poll_table *wait)
329{
330 struct bt_bmc *bt_bmc = file_bt_bmc(file);
331 unsigned int mask = 0;
332 u8 ctrl;
333
334 poll_wait(file, &bt_bmc->queue, wait);
335
336 ctrl = bt_inb(bt_bmc, BT_CTRL);
337
338 if (ctrl & BT_CTRL_H2B_ATN)
339 mask |= POLLIN;
340
341 if (!(ctrl & (BT_CTRL_H_BUSY | BT_CTRL_B2H_ATN)))
342 mask |= POLLOUT;
343
344 return mask;
345}
346
347static const struct file_operations bt_bmc_fops = {
348 .owner = THIS_MODULE,
349 .open = bt_bmc_open,
350 .read = bt_bmc_read,
351 .write = bt_bmc_write,
352 .release = bt_bmc_release,
353 .poll = bt_bmc_poll,
354 .unlocked_ioctl = bt_bmc_ioctl,
355};
356
357static void poll_timer(unsigned long data)
358{
359 struct bt_bmc *bt_bmc = (void *)data;
360
361 bt_bmc->poll_timer.expires += msecs_to_jiffies(500);
362 wake_up(&bt_bmc->queue);
363 add_timer(&bt_bmc->poll_timer);
364}
365
366static irqreturn_t bt_bmc_irq(int irq, void *arg)
367{
368 struct bt_bmc *bt_bmc = arg;
369 u32 reg;
370
371 reg = ioread32(bt_bmc->base + BT_CR2);
372 reg &= BT_CR2_IRQ_H2B | BT_CR2_IRQ_HBUSY;
373 if (!reg)
374 return IRQ_NONE;
375
376 /* ack pending IRQs */
377 iowrite32(reg, bt_bmc->base + BT_CR2);
378
379 wake_up(&bt_bmc->queue);
380 return IRQ_HANDLED;
381}
382
383static int bt_bmc_config_irq(struct bt_bmc *bt_bmc,
384 struct platform_device *pdev)
385{
386 struct device *dev = &pdev->dev;
387 u32 reg;
388 int rc;
389
390 bt_bmc->irq = platform_get_irq(pdev, 0);
391 if (!bt_bmc->irq)
392 return -ENODEV;
393
394 rc = devm_request_irq(dev, bt_bmc->irq, bt_bmc_irq, IRQF_SHARED,
395 DEVICE_NAME, bt_bmc);
396 if (rc < 0) {
397 dev_warn(dev, "Unable to request IRQ %d\n", bt_bmc->irq);
398 bt_bmc->irq = 0;
399 return rc;
400 }
401
402 /*
403 * Configure IRQs on the bmc clearing the H2B and HBUSY bits;
404 * H2B will be asserted when the bmc has data for us; HBUSY
405 * will be cleared (along with B2H) when we can write the next
406 * message to the BT buffer
407 */
408 reg = ioread32(bt_bmc->base + BT_CR1);
409 reg |= BT_CR1_IRQ_H2B | BT_CR1_IRQ_HBUSY;
410 iowrite32(reg, bt_bmc->base + BT_CR1);
411
412 return 0;
413}
414
415static int bt_bmc_probe(struct platform_device *pdev)
416{
417 struct bt_bmc *bt_bmc;
418 struct device *dev;
419 struct resource *res;
420 int rc;
421
422 if (!pdev || !pdev->dev.of_node)
423 return -ENODEV;
424
425 dev = &pdev->dev;
426 dev_info(dev, "Found bt bmc device\n");
427
428 bt_bmc = devm_kzalloc(dev, sizeof(*bt_bmc), GFP_KERNEL);
429 if (!bt_bmc)
430 return -ENOMEM;
431
432 dev_set_drvdata(&pdev->dev, bt_bmc);
433
434 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
435 bt_bmc->base = devm_ioremap_resource(&pdev->dev, res);
436 if (IS_ERR(bt_bmc->base))
437 return PTR_ERR(bt_bmc->base);
438
439 mutex_init(&bt_bmc->mutex);
440 init_waitqueue_head(&bt_bmc->queue);
441
442 bt_bmc->miscdev.minor = MISC_DYNAMIC_MINOR,
443 bt_bmc->miscdev.name = DEVICE_NAME,
444 bt_bmc->miscdev.fops = &bt_bmc_fops,
445 bt_bmc->miscdev.parent = dev;
446 rc = misc_register(&bt_bmc->miscdev);
447 if (rc) {
448 dev_err(dev, "Unable to register misc device\n");
449 return rc;
450 }
451
452 bt_bmc_config_irq(bt_bmc, pdev);
453
454 if (bt_bmc->irq) {
455 dev_info(dev, "Using IRQ %d\n", bt_bmc->irq);
456 } else {
457 dev_info(dev, "No IRQ; using timer\n");
458 setup_timer(&bt_bmc->poll_timer, poll_timer,
459 (unsigned long)bt_bmc);
460 bt_bmc->poll_timer.expires = jiffies + msecs_to_jiffies(10);
461 add_timer(&bt_bmc->poll_timer);
462 }
463
464 iowrite32((BT_IO_BASE << BT_CR0_IO_BASE) |
465 (BT_IRQ << BT_CR0_IRQ) |
466 BT_CR0_EN_CLR_SLV_RDP |
467 BT_CR0_EN_CLR_SLV_WRP |
468 BT_CR0_ENABLE_IBT,
469 bt_bmc->base + BT_CR0);
470
471 clr_b_busy(bt_bmc);
472
473 return 0;
474}
475
476static int bt_bmc_remove(struct platform_device *pdev)
477{
478 struct bt_bmc *bt_bmc = dev_get_drvdata(&pdev->dev);
479
480 misc_deregister(&bt_bmc->miscdev);
481 if (!bt_bmc->irq)
482 del_timer_sync(&bt_bmc->poll_timer);
483 return 0;
484}
485
486static const struct of_device_id bt_bmc_match[] = {
487 { .compatible = "aspeed,ast2400-bt-bmc" },
488 { },
489};
490
491static struct platform_driver bt_bmc_driver = {
492 .driver = {
493 .name = DEVICE_NAME,
494 .of_match_table = bt_bmc_match,
495 },
496 .probe = bt_bmc_probe,
497 .remove = bt_bmc_remove,
498};
499
500module_platform_driver(bt_bmc_driver);
501
502MODULE_DEVICE_TABLE(of, bt_bmc_match);
503MODULE_LICENSE("GPL");
504MODULE_AUTHOR("Alistair Popple <alistair@popple.id.au>");
505MODULE_DESCRIPTION("Linux device interface to the BT interface");
diff --git a/drivers/char/ipmi/ipmi_msghandler.c b/drivers/char/ipmi/ipmi_msghandler.c
index d8619998cfb5..fcdd886819f5 100644
--- a/drivers/char/ipmi/ipmi_msghandler.c
+++ b/drivers/char/ipmi/ipmi_msghandler.c
@@ -2891,11 +2891,11 @@ int ipmi_register_smi(const struct ipmi_smi_handlers *handlers,
2891 intf->curr_channel = IPMI_MAX_CHANNELS; 2891 intf->curr_channel = IPMI_MAX_CHANNELS;
2892 } 2892 }
2893 2893
2894 rv = ipmi_bmc_register(intf, i);
2895
2894 if (rv == 0) 2896 if (rv == 0)
2895 rv = add_proc_entries(intf, i); 2897 rv = add_proc_entries(intf, i);
2896 2898
2897 rv = ipmi_bmc_register(intf, i);
2898
2899 out: 2899 out:
2900 if (rv) { 2900 if (rv) {
2901 if (intf->proc_dir) 2901 if (intf->proc_dir)
@@ -2982,8 +2982,6 @@ int ipmi_unregister_smi(ipmi_smi_t intf)
2982 int intf_num = intf->intf_num; 2982 int intf_num = intf->intf_num;
2983 ipmi_user_t user; 2983 ipmi_user_t user;
2984 2984
2985 ipmi_bmc_unregister(intf);
2986
2987 mutex_lock(&smi_watchers_mutex); 2985 mutex_lock(&smi_watchers_mutex);
2988 mutex_lock(&ipmi_interfaces_mutex); 2986 mutex_lock(&ipmi_interfaces_mutex);
2989 intf->intf_num = -1; 2987 intf->intf_num = -1;
@@ -3007,6 +3005,7 @@ int ipmi_unregister_smi(ipmi_smi_t intf)
3007 mutex_unlock(&ipmi_interfaces_mutex); 3005 mutex_unlock(&ipmi_interfaces_mutex);
3008 3006
3009 remove_proc_entries(intf); 3007 remove_proc_entries(intf);
3008 ipmi_bmc_unregister(intf);
3010 3009
3011 /* 3010 /*
3012 * Call all the watcher interfaces to tell them that 3011 * Call all the watcher interfaces to tell them that
diff --git a/drivers/clk/pxa/clk-pxa25x.c b/drivers/clk/pxa/clk-pxa25x.c
index a98b98e2a9e4..56b0a6027e38 100644
--- a/drivers/clk/pxa/clk-pxa25x.c
+++ b/drivers/clk/pxa/clk-pxa25x.c
@@ -230,7 +230,7 @@ static struct dummy_clk dummy_clks[] __initdata = {
230 DUMMY_CLK("GPIO11_CLK", NULL, "osc_3_6864mhz"), 230 DUMMY_CLK("GPIO11_CLK", NULL, "osc_3_6864mhz"),
231 DUMMY_CLK("GPIO12_CLK", NULL, "osc_32_768khz"), 231 DUMMY_CLK("GPIO12_CLK", NULL, "osc_32_768khz"),
232 DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"), 232 DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
233 DUMMY_CLK("OSTIMER0", NULL, "osc_32_768khz"), 233 DUMMY_CLK("OSTIMER0", NULL, "osc_3_6864mhz"),
234 DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"), 234 DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
235}; 235};
236 236
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 245190839359..e2c6e43cf8ca 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -417,6 +417,16 @@ config SYS_SUPPORTS_SH_TMU
417config SYS_SUPPORTS_EM_STI 417config SYS_SUPPORTS_EM_STI
418 bool 418 bool
419 419
420config CLKSRC_JCORE_PIT
421 bool "J-Core PIT timer driver" if COMPILE_TEST
422 depends on OF
423 depends on GENERIC_CLOCKEVENTS
424 depends on HAS_IOMEM
425 select CLKSRC_MMIO
426 help
427 This enables build of clocksource and clockevent driver for
428 the integrated PIT in the J-Core synthesizable, open source SoC.
429
420config SH_TIMER_CMT 430config SH_TIMER_CMT
421 bool "Renesas CMT timer driver" if COMPILE_TEST 431 bool "Renesas CMT timer driver" if COMPILE_TEST
422 depends on GENERIC_CLOCKEVENTS 432 depends on GENERIC_CLOCKEVENTS
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index fd9d6df0bbc0..cf87f407f1ad 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
5obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o 5obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
6obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o 6obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
7obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += cs5535-clockevt.o 7obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += cs5535-clockevt.o
8obj-$(CONFIG_CLKSRC_JCORE_PIT) += jcore-pit.o
8obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o 9obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o
9obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o 10obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o
10obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o 11obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o
diff --git a/drivers/clocksource/jcore-pit.c b/drivers/clocksource/jcore-pit.c
new file mode 100644
index 000000000000..54e1665aa03c
--- /dev/null
+++ b/drivers/clocksource/jcore-pit.c
@@ -0,0 +1,249 @@
1/*
2 * J-Core SoC PIT/clocksource driver
3 *
4 * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/slab.h>
13#include <linux/interrupt.h>
14#include <linux/clockchips.h>
15#include <linux/clocksource.h>
16#include <linux/sched_clock.h>
17#include <linux/cpu.h>
18#include <linux/cpuhotplug.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
21
22#define PIT_IRQ_SHIFT 12
23#define PIT_PRIO_SHIFT 20
24#define PIT_ENABLE_SHIFT 26
25#define PIT_PRIO_MASK 0xf
26
27#define REG_PITEN 0x00
28#define REG_THROT 0x10
29#define REG_COUNT 0x14
30#define REG_BUSPD 0x18
31#define REG_SECHI 0x20
32#define REG_SECLO 0x24
33#define REG_NSEC 0x28
34
35struct jcore_pit {
36 struct clock_event_device ced;
37 void __iomem *base;
38 unsigned long periodic_delta;
39 u32 enable_val;
40};
41
42static void __iomem *jcore_pit_base;
43static struct jcore_pit __percpu *jcore_pit_percpu;
44
45static notrace u64 jcore_sched_clock_read(void)
46{
47 u32 seclo, nsec, seclo0;
48 __iomem void *base = jcore_pit_base;
49
50 seclo = readl(base + REG_SECLO);
51 do {
52 seclo0 = seclo;
53 nsec = readl(base + REG_NSEC);
54 seclo = readl(base + REG_SECLO);
55 } while (seclo0 != seclo);
56
57 return seclo * NSEC_PER_SEC + nsec;
58}
59
60static cycle_t jcore_clocksource_read(struct clocksource *cs)
61{
62 return jcore_sched_clock_read();
63}
64
65static int jcore_pit_disable(struct jcore_pit *pit)
66{
67 writel(0, pit->base + REG_PITEN);
68 return 0;
69}
70
71static int jcore_pit_set(unsigned long delta, struct jcore_pit *pit)
72{
73 jcore_pit_disable(pit);
74 writel(delta, pit->base + REG_THROT);
75 writel(pit->enable_val, pit->base + REG_PITEN);
76 return 0;
77}
78
79static int jcore_pit_set_state_shutdown(struct clock_event_device *ced)
80{
81 struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
82
83 return jcore_pit_disable(pit);
84}
85
86static int jcore_pit_set_state_oneshot(struct clock_event_device *ced)
87{
88 struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
89
90 return jcore_pit_disable(pit);
91}
92
93static int jcore_pit_set_state_periodic(struct clock_event_device *ced)
94{
95 struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
96
97 return jcore_pit_set(pit->periodic_delta, pit);
98}
99
100static int jcore_pit_set_next_event(unsigned long delta,
101 struct clock_event_device *ced)
102{
103 struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
104
105 return jcore_pit_set(delta, pit);
106}
107
108static int jcore_pit_local_init(unsigned cpu)
109{
110 struct jcore_pit *pit = this_cpu_ptr(jcore_pit_percpu);
111 unsigned buspd, freq;
112
113 pr_info("Local J-Core PIT init on cpu %u\n", cpu);
114
115 buspd = readl(pit->base + REG_BUSPD);
116 freq = DIV_ROUND_CLOSEST(NSEC_PER_SEC, buspd);
117 pit->periodic_delta = DIV_ROUND_CLOSEST(NSEC_PER_SEC, HZ * buspd);
118
119 clockevents_config_and_register(&pit->ced, freq, 1, ULONG_MAX);
120
121 return 0;
122}
123
124static irqreturn_t jcore_timer_interrupt(int irq, void *dev_id)
125{
126 struct jcore_pit *pit = this_cpu_ptr(dev_id);
127
128 if (clockevent_state_oneshot(&pit->ced))
129 jcore_pit_disable(pit);
130
131 pit->ced.event_handler(&pit->ced);
132
133 return IRQ_HANDLED;
134}
135
136static int __init jcore_pit_init(struct device_node *node)
137{
138 int err;
139 unsigned pit_irq, cpu;
140 unsigned long hwirq;
141 u32 irqprio, enable_val;
142
143 jcore_pit_base = of_iomap(node, 0);
144 if (!jcore_pit_base) {
145 pr_err("Error: Cannot map base address for J-Core PIT\n");
146 return -ENXIO;
147 }
148
149 pit_irq = irq_of_parse_and_map(node, 0);
150 if (!pit_irq) {
151 pr_err("Error: J-Core PIT has no IRQ\n");
152 return -ENXIO;
153 }
154
155 pr_info("Initializing J-Core PIT at %p IRQ %d\n",
156 jcore_pit_base, pit_irq);
157
158 err = clocksource_mmio_init(jcore_pit_base, "jcore_pit_cs",
159 NSEC_PER_SEC, 400, 32,
160 jcore_clocksource_read);
161 if (err) {
162 pr_err("Error registering clocksource device: %d\n", err);
163 return err;
164 }
165
166 sched_clock_register(jcore_sched_clock_read, 32, NSEC_PER_SEC);
167
168 jcore_pit_percpu = alloc_percpu(struct jcore_pit);
169 if (!jcore_pit_percpu) {
170 pr_err("Failed to allocate memory for clock event device\n");
171 return -ENOMEM;
172 }
173
174 err = request_irq(pit_irq, jcore_timer_interrupt,
175 IRQF_TIMER | IRQF_PERCPU,
176 "jcore_pit", jcore_pit_percpu);
177 if (err) {
178 pr_err("pit irq request failed: %d\n", err);
179 free_percpu(jcore_pit_percpu);
180 return err;
181 }
182
183 /*
184 * The J-Core PIT is not hard-wired to a particular IRQ, but
185 * integrated with the interrupt controller such that the IRQ it
186 * generates is programmable, as follows:
187 *
188 * The bit layout of the PIT enable register is:
189 *
190 * .....e..ppppiiiiiiii............
191 *
192 * where the .'s indicate unrelated/unused bits, e is enable,
193 * p is priority, and i is hard irq number.
194 *
195 * For the PIT included in AIC1 (obsolete but still in use),
196 * any hard irq (trap number) can be programmed via the 8
197 * iiiiiiii bits, and a priority (0-15) is programmable
198 * separately in the pppp bits.
199 *
200 * For the PIT included in AIC2 (current), the programming
201 * interface is equivalent modulo interrupt mapping. This is
202 * why a different compatible tag was not used. However only
203 * traps 64-127 (the ones actually intended to be used for
204 * interrupts, rather than syscalls/exceptions/etc.) can be
205 * programmed (the high 2 bits of i are ignored) and the
206 * priority pppp is <<2'd and or'd onto the irq number. This
207 * choice seems to have been made on the hardware engineering
208 * side under an assumption that preserving old AIC1 priority
209 * mappings was important. Future models will likely ignore
210 * the pppp field.
211 */
212 hwirq = irq_get_irq_data(pit_irq)->hwirq;
213 irqprio = (hwirq >> 2) & PIT_PRIO_MASK;
214 enable_val = (1U << PIT_ENABLE_SHIFT)
215 | (hwirq << PIT_IRQ_SHIFT)
216 | (irqprio << PIT_PRIO_SHIFT);
217
218 for_each_present_cpu(cpu) {
219 struct jcore_pit *pit = per_cpu_ptr(jcore_pit_percpu, cpu);
220
221 pit->base = of_iomap(node, cpu);
222 if (!pit->base) {
223 pr_err("Unable to map PIT for cpu %u\n", cpu);
224 continue;
225 }
226
227 pit->ced.name = "jcore_pit";
228 pit->ced.features = CLOCK_EVT_FEAT_PERIODIC
229 | CLOCK_EVT_FEAT_ONESHOT
230 | CLOCK_EVT_FEAT_PERCPU;
231 pit->ced.cpumask = cpumask_of(cpu);
232 pit->ced.rating = 400;
233 pit->ced.irq = pit_irq;
234 pit->ced.set_state_shutdown = jcore_pit_set_state_shutdown;
235 pit->ced.set_state_periodic = jcore_pit_set_state_periodic;
236 pit->ced.set_state_oneshot = jcore_pit_set_state_oneshot;
237 pit->ced.set_next_event = jcore_pit_set_next_event;
238
239 pit->enable_val = enable_val;
240 }
241
242 cpuhp_setup_state(CPUHP_AP_JCORE_TIMER_STARTING,
243 "AP_JCORE_TIMER_STARTING",
244 jcore_pit_local_init, NULL);
245
246 return 0;
247}
248
249CLOCKSOURCE_OF_DECLARE(jcore_pit, "jcore,pit", jcore_pit_init);
diff --git a/drivers/clocksource/pxa_timer.c b/drivers/clocksource/pxa_timer.c
index 3e1cb512f3ce..9cae38eebec2 100644
--- a/drivers/clocksource/pxa_timer.c
+++ b/drivers/clocksource/pxa_timer.c
@@ -220,17 +220,16 @@ CLOCKSOURCE_OF_DECLARE(pxa_timer, "marvell,pxa-timer", pxa_timer_dt_init);
220/* 220/*
221 * Legacy timer init for non device-tree boards. 221 * Legacy timer init for non device-tree boards.
222 */ 222 */
223void __init pxa_timer_nodt_init(int irq, void __iomem *base, 223void __init pxa_timer_nodt_init(int irq, void __iomem *base)
224 unsigned long clock_tick_rate)
225{ 224{
226 struct clk *clk; 225 struct clk *clk;
227 226
228 timer_base = base; 227 timer_base = base;
229 clk = clk_get(NULL, "OSTIMER0"); 228 clk = clk_get(NULL, "OSTIMER0");
230 if (clk && !IS_ERR(clk)) 229 if (clk && !IS_ERR(clk)) {
231 clk_prepare_enable(clk); 230 clk_prepare_enable(clk);
232 else 231 pxa_timer_common_init(irq, clk_get_rate(clk));
232 } else {
233 pr_crit("%s: unable to get clk\n", __func__); 233 pr_crit("%s: unable to get clk\n", __func__);
234 234 }
235 pxa_timer_common_init(irq, clock_tick_rate);
236} 235}
diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-sun5i.c
index c184eb84101e..4f87f3e76d83 100644
--- a/drivers/clocksource/timer-sun5i.c
+++ b/drivers/clocksource/timer-sun5i.c
@@ -152,6 +152,13 @@ static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
152 return IRQ_HANDLED; 152 return IRQ_HANDLED;
153} 153}
154 154
155static cycle_t sun5i_clksrc_read(struct clocksource *clksrc)
156{
157 struct sun5i_timer_clksrc *cs = to_sun5i_timer_clksrc(clksrc);
158
159 return ~readl(cs->timer.base + TIMER_CNTVAL_LO_REG(1));
160}
161
155static int sun5i_rate_cb_clksrc(struct notifier_block *nb, 162static int sun5i_rate_cb_clksrc(struct notifier_block *nb,
156 unsigned long event, void *data) 163 unsigned long event, void *data)
157{ 164{
@@ -210,8 +217,13 @@ static int __init sun5i_setup_clocksource(struct device_node *node,
210 writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, 217 writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
211 base + TIMER_CTL_REG(1)); 218 base + TIMER_CTL_REG(1));
212 219
213 ret = clocksource_mmio_init(base + TIMER_CNTVAL_LO_REG(1), node->name, 220 cs->clksrc.name = node->name;
214 rate, 340, 32, clocksource_mmio_readl_down); 221 cs->clksrc.rating = 340;
222 cs->clksrc.read = sun5i_clksrc_read;
223 cs->clksrc.mask = CLOCKSOURCE_MASK(32);
224 cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
225
226 ret = clocksource_register_hz(&cs->clksrc, rate);
215 if (ret) { 227 if (ret) {
216 pr_err("Couldn't register clock source.\n"); 228 pr_err("Couldn't register clock source.\n");
217 goto err_remove_notifier; 229 goto err_remove_notifier;
diff --git a/drivers/firewire/nosy.c b/drivers/firewire/nosy.c
index 631c977b0da5..180f0a96528c 100644
--- a/drivers/firewire/nosy.c
+++ b/drivers/firewire/nosy.c
@@ -566,6 +566,11 @@ add_card(struct pci_dev *dev, const struct pci_device_id *unused)
566 566
567 lynx->registers = ioremap_nocache(pci_resource_start(dev, 0), 567 lynx->registers = ioremap_nocache(pci_resource_start(dev, 0),
568 PCILYNX_MAX_REGISTER); 568 PCILYNX_MAX_REGISTER);
569 if (lynx->registers == NULL) {
570 dev_err(&dev->dev, "Failed to map registers\n");
571 ret = -ENOMEM;
572 goto fail_deallocate_lynx;
573 }
569 574
570 lynx->rcv_start_pcl = pci_alloc_consistent(lynx->pci_device, 575 lynx->rcv_start_pcl = pci_alloc_consistent(lynx->pci_device,
571 sizeof(struct pcl), &lynx->rcv_start_pcl_bus); 576 sizeof(struct pcl), &lynx->rcv_start_pcl_bus);
@@ -578,7 +583,7 @@ add_card(struct pci_dev *dev, const struct pci_device_id *unused)
578 lynx->rcv_buffer == NULL) { 583 lynx->rcv_buffer == NULL) {
579 dev_err(&dev->dev, "Failed to allocate receive buffer\n"); 584 dev_err(&dev->dev, "Failed to allocate receive buffer\n");
580 ret = -ENOMEM; 585 ret = -ENOMEM;
581 goto fail_deallocate; 586 goto fail_deallocate_buffers;
582 } 587 }
583 lynx->rcv_start_pcl->next = cpu_to_le32(lynx->rcv_pcl_bus); 588 lynx->rcv_start_pcl->next = cpu_to_le32(lynx->rcv_pcl_bus);
584 lynx->rcv_pcl->next = cpu_to_le32(PCL_NEXT_INVALID); 589 lynx->rcv_pcl->next = cpu_to_le32(PCL_NEXT_INVALID);
@@ -641,7 +646,7 @@ add_card(struct pci_dev *dev, const struct pci_device_id *unused)
641 dev_err(&dev->dev, 646 dev_err(&dev->dev,
642 "Failed to allocate shared interrupt %d\n", dev->irq); 647 "Failed to allocate shared interrupt %d\n", dev->irq);
643 ret = -EIO; 648 ret = -EIO;
644 goto fail_deallocate; 649 goto fail_deallocate_buffers;
645 } 650 }
646 651
647 lynx->misc.parent = &dev->dev; 652 lynx->misc.parent = &dev->dev;
@@ -668,7 +673,7 @@ fail_free_irq:
668 reg_write(lynx, PCI_INT_ENABLE, 0); 673 reg_write(lynx, PCI_INT_ENABLE, 0);
669 free_irq(lynx->pci_device->irq, lynx); 674 free_irq(lynx->pci_device->irq, lynx);
670 675
671fail_deallocate: 676fail_deallocate_buffers:
672 if (lynx->rcv_start_pcl) 677 if (lynx->rcv_start_pcl)
673 pci_free_consistent(lynx->pci_device, sizeof(struct pcl), 678 pci_free_consistent(lynx->pci_device, sizeof(struct pcl),
674 lynx->rcv_start_pcl, lynx->rcv_start_pcl_bus); 679 lynx->rcv_start_pcl, lynx->rcv_start_pcl_bus);
@@ -679,6 +684,8 @@ fail_deallocate:
679 pci_free_consistent(lynx->pci_device, PAGE_SIZE, 684 pci_free_consistent(lynx->pci_device, PAGE_SIZE,
680 lynx->rcv_buffer, lynx->rcv_buffer_bus); 685 lynx->rcv_buffer, lynx->rcv_buffer_bus);
681 iounmap(lynx->registers); 686 iounmap(lynx->registers);
687
688fail_deallocate_lynx:
682 kfree(lynx); 689 kfree(lynx);
683 690
684fail_disable: 691fail_disable:
diff --git a/drivers/firmware/efi/libstub/Makefile b/drivers/firmware/efi/libstub/Makefile
index c06945160a41..5e23e2d305e7 100644
--- a/drivers/firmware/efi/libstub/Makefile
+++ b/drivers/firmware/efi/libstub/Makefile
@@ -11,7 +11,7 @@ cflags-$(CONFIG_X86) += -m$(BITS) -D__KERNEL__ $(LINUX_INCLUDE) -O2 \
11 -mno-mmx -mno-sse 11 -mno-mmx -mno-sse
12 12
13cflags-$(CONFIG_ARM64) := $(subst -pg,,$(KBUILD_CFLAGS)) 13cflags-$(CONFIG_ARM64) := $(subst -pg,,$(KBUILD_CFLAGS))
14cflags-$(CONFIG_ARM) := $(subst -pg,,$(KBUILD_CFLAGS)) \ 14cflags-$(CONFIG_ARM) := $(subst -pg,,$(KBUILD_CFLAGS)) -g0 \
15 -fno-builtin -fpic -mno-single-pic-base 15 -fno-builtin -fpic -mno-single-pic-base
16 16
17cflags-$(CONFIG_EFI_ARMSTUB) += -I$(srctree)/scripts/dtc/libfdt 17cflags-$(CONFIG_EFI_ARMSTUB) += -I$(srctree)/scripts/dtc/libfdt
@@ -79,5 +79,6 @@ quiet_cmd_stubcopy = STUBCPY $@
79# decompressor. So move our .data to .data.efistub, which is preserved 79# decompressor. So move our .data to .data.efistub, which is preserved
80# explicitly by the decompressor linker script. 80# explicitly by the decompressor linker script.
81# 81#
82STUBCOPY_FLAGS-$(CONFIG_ARM) += --rename-section .data=.data.efistub 82STUBCOPY_FLAGS-$(CONFIG_ARM) += --rename-section .data=.data.efistub \
83 -R ___ksymtab+sort -R ___kcrctab+sort
83STUBCOPY_RELOC-$(CONFIG_ARM) := R_ARM_ABS 84STUBCOPY_RELOC-$(CONFIG_ARM) := R_ARM_ABS
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
index 2e3a0543760d..e3281d4e3e41 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
@@ -765,7 +765,7 @@ amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
765 return ret; 765 return ret;
766} 766}
767 767
768static void amdgpu_connector_destroy(struct drm_connector *connector) 768static void amdgpu_connector_unregister(struct drm_connector *connector)
769{ 769{
770 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 770 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
771 771
@@ -773,6 +773,12 @@ static void amdgpu_connector_destroy(struct drm_connector *connector)
773 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 773 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
774 amdgpu_connector->ddc_bus->has_aux = false; 774 amdgpu_connector->ddc_bus->has_aux = false;
775 } 775 }
776}
777
778static void amdgpu_connector_destroy(struct drm_connector *connector)
779{
780 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
781
776 amdgpu_connector_free_edid(connector); 782 amdgpu_connector_free_edid(connector);
777 kfree(amdgpu_connector->con_priv); 783 kfree(amdgpu_connector->con_priv);
778 drm_connector_unregister(connector); 784 drm_connector_unregister(connector);
@@ -826,6 +832,7 @@ static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
826 .dpms = drm_helper_connector_dpms, 832 .dpms = drm_helper_connector_dpms,
827 .detect = amdgpu_connector_lvds_detect, 833 .detect = amdgpu_connector_lvds_detect,
828 .fill_modes = drm_helper_probe_single_connector_modes, 834 .fill_modes = drm_helper_probe_single_connector_modes,
835 .early_unregister = amdgpu_connector_unregister,
829 .destroy = amdgpu_connector_destroy, 836 .destroy = amdgpu_connector_destroy,
830 .set_property = amdgpu_connector_set_lcd_property, 837 .set_property = amdgpu_connector_set_lcd_property,
831}; 838};
@@ -936,6 +943,7 @@ static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
936 .dpms = drm_helper_connector_dpms, 943 .dpms = drm_helper_connector_dpms,
937 .detect = amdgpu_connector_vga_detect, 944 .detect = amdgpu_connector_vga_detect,
938 .fill_modes = drm_helper_probe_single_connector_modes, 945 .fill_modes = drm_helper_probe_single_connector_modes,
946 .early_unregister = amdgpu_connector_unregister,
939 .destroy = amdgpu_connector_destroy, 947 .destroy = amdgpu_connector_destroy,
940 .set_property = amdgpu_connector_set_property, 948 .set_property = amdgpu_connector_set_property,
941}; 949};
@@ -1203,6 +1211,7 @@ static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1203 .detect = amdgpu_connector_dvi_detect, 1211 .detect = amdgpu_connector_dvi_detect,
1204 .fill_modes = drm_helper_probe_single_connector_modes, 1212 .fill_modes = drm_helper_probe_single_connector_modes,
1205 .set_property = amdgpu_connector_set_property, 1213 .set_property = amdgpu_connector_set_property,
1214 .early_unregister = amdgpu_connector_unregister,
1206 .destroy = amdgpu_connector_destroy, 1215 .destroy = amdgpu_connector_destroy,
1207 .force = amdgpu_connector_dvi_force, 1216 .force = amdgpu_connector_dvi_force,
1208}; 1217};
@@ -1493,6 +1502,7 @@ static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1493 .detect = amdgpu_connector_dp_detect, 1502 .detect = amdgpu_connector_dp_detect,
1494 .fill_modes = drm_helper_probe_single_connector_modes, 1503 .fill_modes = drm_helper_probe_single_connector_modes,
1495 .set_property = amdgpu_connector_set_property, 1504 .set_property = amdgpu_connector_set_property,
1505 .early_unregister = amdgpu_connector_unregister,
1496 .destroy = amdgpu_connector_destroy, 1506 .destroy = amdgpu_connector_destroy,
1497 .force = amdgpu_connector_dvi_force, 1507 .force = amdgpu_connector_dvi_force,
1498}; 1508};
@@ -1502,6 +1512,7 @@ static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1502 .detect = amdgpu_connector_dp_detect, 1512 .detect = amdgpu_connector_dp_detect,
1503 .fill_modes = drm_helper_probe_single_connector_modes, 1513 .fill_modes = drm_helper_probe_single_connector_modes,
1504 .set_property = amdgpu_connector_set_lcd_property, 1514 .set_property = amdgpu_connector_set_lcd_property,
1515 .early_unregister = amdgpu_connector_unregister,
1505 .destroy = amdgpu_connector_destroy, 1516 .destroy = amdgpu_connector_destroy,
1506 .force = amdgpu_connector_dvi_force, 1517 .force = amdgpu_connector_dvi_force,
1507}; 1518};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index e203e5561107..a5e2fcbef0f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -43,6 +43,9 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, struct amdgpu_ctx *ctx)
43 ctx->rings[i].sequence = 1; 43 ctx->rings[i].sequence = 1;
44 ctx->rings[i].fences = &ctx->fences[amdgpu_sched_jobs * i]; 44 ctx->rings[i].fences = &ctx->fences[amdgpu_sched_jobs * i];
45 } 45 }
46
47 ctx->reset_counter = atomic_read(&adev->gpu_reset_counter);
48
46 /* create context entity for each ring */ 49 /* create context entity for each ring */
47 for (i = 0; i < adev->num_rings; i++) { 50 for (i = 0; i < adev->num_rings; i++) {
48 struct amdgpu_ring *ring = adev->rings[i]; 51 struct amdgpu_ring *ring = adev->rings[i];
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7dbe85d67d26..b4f4a9239069 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1408,16 +1408,6 @@ static int amdgpu_late_init(struct amdgpu_device *adev)
1408 for (i = 0; i < adev->num_ip_blocks; i++) { 1408 for (i = 0; i < adev->num_ip_blocks; i++) {
1409 if (!adev->ip_block_status[i].valid) 1409 if (!adev->ip_block_status[i].valid)
1410 continue; 1410 continue;
1411 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_UVD ||
1412 adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_VCE)
1413 continue;
1414 /* enable clockgating to save power */
1415 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1416 AMD_CG_STATE_GATE);
1417 if (r) {
1418 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1419 return r;
1420 }
1421 if (adev->ip_blocks[i].funcs->late_init) { 1411 if (adev->ip_blocks[i].funcs->late_init) {
1422 r = adev->ip_blocks[i].funcs->late_init((void *)adev); 1412 r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1423 if (r) { 1413 if (r) {
@@ -1426,6 +1416,18 @@ static int amdgpu_late_init(struct amdgpu_device *adev)
1426 } 1416 }
1427 adev->ip_block_status[i].late_initialized = true; 1417 adev->ip_block_status[i].late_initialized = true;
1428 } 1418 }
1419 /* skip CG for VCE/UVD, it's handled specially */
1420 if (adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_UVD &&
1421 adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_VCE) {
1422 /* enable clockgating to save power */
1423 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1424 AMD_CG_STATE_GATE);
1425 if (r) {
1426 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1427 adev->ip_blocks[i].funcs->name, r);
1428 return r;
1429 }
1430 }
1429 } 1431 }
1430 1432
1431 return 0; 1433 return 0;
@@ -1435,6 +1437,30 @@ static int amdgpu_fini(struct amdgpu_device *adev)
1435{ 1437{
1436 int i, r; 1438 int i, r;
1437 1439
1440 /* need to disable SMC first */
1441 for (i = 0; i < adev->num_ip_blocks; i++) {
1442 if (!adev->ip_block_status[i].hw)
1443 continue;
1444 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) {
1445 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1446 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1447 AMD_CG_STATE_UNGATE);
1448 if (r) {
1449 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1450 adev->ip_blocks[i].funcs->name, r);
1451 return r;
1452 }
1453 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1454 /* XXX handle errors */
1455 if (r) {
1456 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1457 adev->ip_blocks[i].funcs->name, r);
1458 }
1459 adev->ip_block_status[i].hw = false;
1460 break;
1461 }
1462 }
1463
1438 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 1464 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1439 if (!adev->ip_block_status[i].hw) 1465 if (!adev->ip_block_status[i].hw)
1440 continue; 1466 continue;
@@ -2073,7 +2099,8 @@ static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
2073 if (!adev->ip_block_status[i].valid) 2099 if (!adev->ip_block_status[i].valid)
2074 continue; 2100 continue;
2075 if (adev->ip_blocks[i].funcs->check_soft_reset) 2101 if (adev->ip_blocks[i].funcs->check_soft_reset)
2076 adev->ip_blocks[i].funcs->check_soft_reset(adev); 2102 adev->ip_block_status[i].hang =
2103 adev->ip_blocks[i].funcs->check_soft_reset(adev);
2077 if (adev->ip_block_status[i].hang) { 2104 if (adev->ip_block_status[i].hang) {
2078 DRM_INFO("IP block:%d is hang!\n", i); 2105 DRM_INFO("IP block:%d is hang!\n", i);
2079 asic_hang = true; 2106 asic_hang = true;
@@ -2102,12 +2129,20 @@ static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
2102 2129
2103static bool amdgpu_need_full_reset(struct amdgpu_device *adev) 2130static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
2104{ 2131{
2105 if (adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang || 2132 int i;
2106 adev->ip_block_status[AMD_IP_BLOCK_TYPE_SMC].hang || 2133
2107 adev->ip_block_status[AMD_IP_BLOCK_TYPE_ACP].hang || 2134 for (i = 0; i < adev->num_ip_blocks; i++) {
2108 adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang) { 2135 if (!adev->ip_block_status[i].valid)
2109 DRM_INFO("Some block need full reset!\n"); 2136 continue;
2110 return true; 2137 if ((adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) ||
2138 (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) ||
2139 (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_ACP) ||
2140 (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_DCE)) {
2141 if (adev->ip_block_status[i].hang) {
2142 DRM_INFO("Some block need full reset!\n");
2143 return true;
2144 }
2145 }
2111 } 2146 }
2112 return false; 2147 return false;
2113} 2148}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
index fe36caf1b7d7..14f57d9915e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
@@ -113,24 +113,26 @@ void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev,
113 printk("\n"); 113 printk("\n");
114} 114}
115 115
116
116u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev) 117u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev)
117{ 118{
118 struct drm_device *dev = adev->ddev; 119 struct drm_device *dev = adev->ddev;
119 struct drm_crtc *crtc; 120 struct drm_crtc *crtc;
120 struct amdgpu_crtc *amdgpu_crtc; 121 struct amdgpu_crtc *amdgpu_crtc;
121 u32 line_time_us, vblank_lines; 122 u32 vblank_in_pixels;
122 u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */ 123 u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */
123 124
124 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { 125 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
125 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 126 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
126 amdgpu_crtc = to_amdgpu_crtc(crtc); 127 amdgpu_crtc = to_amdgpu_crtc(crtc);
127 if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) { 128 if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) {
128 line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) / 129 vblank_in_pixels =
129 amdgpu_crtc->hw_mode.clock; 130 amdgpu_crtc->hw_mode.crtc_htotal *
130 vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end - 131 (amdgpu_crtc->hw_mode.crtc_vblank_end -
131 amdgpu_crtc->hw_mode.crtc_vdisplay + 132 amdgpu_crtc->hw_mode.crtc_vdisplay +
132 (amdgpu_crtc->v_border * 2); 133 (amdgpu_crtc->v_border * 2));
133 vblank_time_us = vblank_lines * line_time_us; 134
135 vblank_time_us = vblank_in_pixels * 1000 / amdgpu_crtc->hw_mode.clock;
134 break; 136 break;
135 } 137 }
136 } 138 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index e1fa8731d1e2..3cb5e903cd62 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -345,8 +345,8 @@ static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
345 ent = debugfs_create_file(name, 345 ent = debugfs_create_file(name,
346 S_IFREG | S_IRUGO, root, 346 S_IFREG | S_IRUGO, root,
347 ring, &amdgpu_debugfs_ring_fops); 347 ring, &amdgpu_debugfs_ring_fops);
348 if (IS_ERR(ent)) 348 if (!ent)
349 return PTR_ERR(ent); 349 return -ENOMEM;
350 350
351 i_size_write(ent->d_inode, ring->ring_size + 12); 351 i_size_write(ent->d_inode, ring->ring_size + 12);
352 ring->ent = ent; 352 ring->ent = ent;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 887483b8b818..dcaf691f56b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -555,10 +555,13 @@ struct amdgpu_ttm_tt {
555int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages) 555int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
556{ 556{
557 struct amdgpu_ttm_tt *gtt = (void *)ttm; 557 struct amdgpu_ttm_tt *gtt = (void *)ttm;
558 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 558 unsigned int flags = 0;
559 unsigned pinned = 0; 559 unsigned pinned = 0;
560 int r; 560 int r;
561 561
562 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
563 flags |= FOLL_WRITE;
564
562 if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) { 565 if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
563 /* check that we only use anonymous memory 566 /* check that we only use anonymous memory
564 to prevent problems with writeback */ 567 to prevent problems with writeback */
@@ -581,7 +584,7 @@ int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
581 list_add(&guptask.list, &gtt->guptasks); 584 list_add(&guptask.list, &gtt->guptasks);
582 spin_unlock(&gtt->guptasklock); 585 spin_unlock(&gtt->guptasklock);
583 586
584 r = get_user_pages(userptr, num_pages, write, 0, p, NULL); 587 r = get_user_pages(userptr, num_pages, flags, p, NULL);
585 588
586 spin_lock(&gtt->guptasklock); 589 spin_lock(&gtt->guptasklock);
587 list_del(&guptask.list); 590 list_del(&guptask.list);
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
index f80a0834e889..3c082e143730 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
@@ -1514,14 +1514,16 @@ static int cz_dpm_set_powergating_state(void *handle,
1514 return 0; 1514 return 0;
1515} 1515}
1516 1516
1517/* borrowed from KV, need future unify */
1518static int cz_dpm_get_temperature(struct amdgpu_device *adev) 1517static int cz_dpm_get_temperature(struct amdgpu_device *adev)
1519{ 1518{
1520 int actual_temp = 0; 1519 int actual_temp = 0;
1521 uint32_t temp = RREG32_SMC(0xC0300E0C); 1520 uint32_t val = RREG32_SMC(ixTHM_TCON_CUR_TMP);
1521 uint32_t temp = REG_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP);
1522 1522
1523 if (temp) 1523 if (REG_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP_RANGE_SEL))
1524 actual_temp = 1000 * ((temp / 8) - 49); 1524 actual_temp = 1000 * ((temp / 8) - 49);
1525 else
1526 actual_temp = 1000 * (temp / 8);
1525 1527
1526 return actual_temp; 1528 return actual_temp;
1527} 1529}
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 613ebb7ed50f..4108c686aa7c 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -3188,16 +3188,11 @@ static int dce_v10_0_wait_for_idle(void *handle)
3188 return 0; 3188 return 0;
3189} 3189}
3190 3190
3191static int dce_v10_0_check_soft_reset(void *handle) 3191static bool dce_v10_0_check_soft_reset(void *handle)
3192{ 3192{
3193 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3193 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3194 3194
3195 if (dce_v10_0_is_display_hung(adev)) 3195 return dce_v10_0_is_display_hung(adev);
3196 adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang = true;
3197 else
3198 adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang = false;
3199
3200 return 0;
3201} 3196}
3202 3197
3203static int dce_v10_0_soft_reset(void *handle) 3198static int dce_v10_0_soft_reset(void *handle)
@@ -3205,9 +3200,6 @@ static int dce_v10_0_soft_reset(void *handle)
3205 u32 srbm_soft_reset = 0, tmp; 3200 u32 srbm_soft_reset = 0, tmp;
3206 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3201 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3207 3202
3208 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang)
3209 return 0;
3210
3211 if (dce_v10_0_is_display_hung(adev)) 3203 if (dce_v10_0_is_display_hung(adev))
3212 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3204 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3213 3205
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 6c6ff57b1c95..ee6a48a09214 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4087,14 +4087,21 @@ static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
4087static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev) 4087static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
4088{ 4088{
4089 int r; 4089 int r;
4090 u32 tmp;
4090 4091
4091 gfx_v8_0_rlc_stop(adev); 4092 gfx_v8_0_rlc_stop(adev);
4092 4093
4093 /* disable CG */ 4094 /* disable CG */
4094 WREG32(mmRLC_CGCG_CGLS_CTRL, 0); 4095 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL);
4096 tmp &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
4097 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
4098 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
4095 if (adev->asic_type == CHIP_POLARIS11 || 4099 if (adev->asic_type == CHIP_POLARIS11 ||
4096 adev->asic_type == CHIP_POLARIS10) 4100 adev->asic_type == CHIP_POLARIS10) {
4097 WREG32(mmRLC_CGCG_CGLS_CTRL_3D, 0); 4101 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL_3D);
4102 tmp &= ~0x3;
4103 WREG32(mmRLC_CGCG_CGLS_CTRL_3D, tmp);
4104 }
4098 4105
4099 /* disable PG */ 4106 /* disable PG */
4100 WREG32(mmRLC_PG_CNTL, 0); 4107 WREG32(mmRLC_PG_CNTL, 0);
@@ -5137,7 +5144,7 @@ static int gfx_v8_0_wait_for_idle(void *handle)
5137 return -ETIMEDOUT; 5144 return -ETIMEDOUT;
5138} 5145}
5139 5146
5140static int gfx_v8_0_check_soft_reset(void *handle) 5147static bool gfx_v8_0_check_soft_reset(void *handle)
5141{ 5148{
5142 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5149 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5143 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 5150 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
@@ -5189,16 +5196,14 @@ static int gfx_v8_0_check_soft_reset(void *handle)
5189 SRBM_SOFT_RESET, SOFT_RESET_SEM, 1); 5196 SRBM_SOFT_RESET, SOFT_RESET_SEM, 1);
5190 5197
5191 if (grbm_soft_reset || srbm_soft_reset) { 5198 if (grbm_soft_reset || srbm_soft_reset) {
5192 adev->ip_block_status[AMD_IP_BLOCK_TYPE_GFX].hang = true;
5193 adev->gfx.grbm_soft_reset = grbm_soft_reset; 5199 adev->gfx.grbm_soft_reset = grbm_soft_reset;
5194 adev->gfx.srbm_soft_reset = srbm_soft_reset; 5200 adev->gfx.srbm_soft_reset = srbm_soft_reset;
5201 return true;
5195 } else { 5202 } else {
5196 adev->ip_block_status[AMD_IP_BLOCK_TYPE_GFX].hang = false;
5197 adev->gfx.grbm_soft_reset = 0; 5203 adev->gfx.grbm_soft_reset = 0;
5198 adev->gfx.srbm_soft_reset = 0; 5204 adev->gfx.srbm_soft_reset = 0;
5205 return false;
5199 } 5206 }
5200
5201 return 0;
5202} 5207}
5203 5208
5204static void gfx_v8_0_inactive_hqd(struct amdgpu_device *adev, 5209static void gfx_v8_0_inactive_hqd(struct amdgpu_device *adev,
@@ -5226,7 +5231,8 @@ static int gfx_v8_0_pre_soft_reset(void *handle)
5226 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5231 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5227 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 5232 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5228 5233
5229 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_GFX].hang) 5234 if ((!adev->gfx.grbm_soft_reset) &&
5235 (!adev->gfx.srbm_soft_reset))
5230 return 0; 5236 return 0;
5231 5237
5232 grbm_soft_reset = adev->gfx.grbm_soft_reset; 5238 grbm_soft_reset = adev->gfx.grbm_soft_reset;
@@ -5264,7 +5270,8 @@ static int gfx_v8_0_soft_reset(void *handle)
5264 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 5270 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5265 u32 tmp; 5271 u32 tmp;
5266 5272
5267 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_GFX].hang) 5273 if ((!adev->gfx.grbm_soft_reset) &&
5274 (!adev->gfx.srbm_soft_reset))
5268 return 0; 5275 return 0;
5269 5276
5270 grbm_soft_reset = adev->gfx.grbm_soft_reset; 5277 grbm_soft_reset = adev->gfx.grbm_soft_reset;
@@ -5334,7 +5341,8 @@ static int gfx_v8_0_post_soft_reset(void *handle)
5334 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5341 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5335 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 5342 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5336 5343
5337 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_GFX].hang) 5344 if ((!adev->gfx.grbm_soft_reset) &&
5345 (!adev->gfx.srbm_soft_reset))
5338 return 0; 5346 return 0;
5339 5347
5340 grbm_soft_reset = adev->gfx.grbm_soft_reset; 5348 grbm_soft_reset = adev->gfx.grbm_soft_reset;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 1b319f5bc696..c22ef140a542 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1099,7 +1099,7 @@ static int gmc_v8_0_wait_for_idle(void *handle)
1099 1099
1100} 1100}
1101 1101
1102static int gmc_v8_0_check_soft_reset(void *handle) 1102static bool gmc_v8_0_check_soft_reset(void *handle)
1103{ 1103{
1104 u32 srbm_soft_reset = 0; 1104 u32 srbm_soft_reset = 0;
1105 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1105 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1116,20 +1116,19 @@ static int gmc_v8_0_check_soft_reset(void *handle)
1116 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1116 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1117 } 1117 }
1118 if (srbm_soft_reset) { 1118 if (srbm_soft_reset) {
1119 adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang = true;
1120 adev->mc.srbm_soft_reset = srbm_soft_reset; 1119 adev->mc.srbm_soft_reset = srbm_soft_reset;
1120 return true;
1121 } else { 1121 } else {
1122 adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang = false;
1123 adev->mc.srbm_soft_reset = 0; 1122 adev->mc.srbm_soft_reset = 0;
1123 return false;
1124 } 1124 }
1125 return 0;
1126} 1125}
1127 1126
1128static int gmc_v8_0_pre_soft_reset(void *handle) 1127static int gmc_v8_0_pre_soft_reset(void *handle)
1129{ 1128{
1130 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1129 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1131 1130
1132 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang) 1131 if (!adev->mc.srbm_soft_reset)
1133 return 0; 1132 return 0;
1134 1133
1135 gmc_v8_0_mc_stop(adev, &adev->mc.save); 1134 gmc_v8_0_mc_stop(adev, &adev->mc.save);
@@ -1145,7 +1144,7 @@ static int gmc_v8_0_soft_reset(void *handle)
1145 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1144 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1146 u32 srbm_soft_reset; 1145 u32 srbm_soft_reset;
1147 1146
1148 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang) 1147 if (!adev->mc.srbm_soft_reset)
1149 return 0; 1148 return 0;
1150 srbm_soft_reset = adev->mc.srbm_soft_reset; 1149 srbm_soft_reset = adev->mc.srbm_soft_reset;
1151 1150
@@ -1175,7 +1174,7 @@ static int gmc_v8_0_post_soft_reset(void *handle)
1175{ 1174{
1176 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1175 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1177 1176
1178 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang) 1177 if (!adev->mc.srbm_soft_reset)
1179 return 0; 1178 return 0;
1180 1179
1181 gmc_v8_0_mc_resume(adev, &adev->mc.save); 1180 gmc_v8_0_mc_resume(adev, &adev->mc.save);
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index f325fd86430b..a9d10941fb53 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1268,7 +1268,7 @@ static int sdma_v3_0_wait_for_idle(void *handle)
1268 return -ETIMEDOUT; 1268 return -ETIMEDOUT;
1269} 1269}
1270 1270
1271static int sdma_v3_0_check_soft_reset(void *handle) 1271static bool sdma_v3_0_check_soft_reset(void *handle)
1272{ 1272{
1273 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1273 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1274 u32 srbm_soft_reset = 0; 1274 u32 srbm_soft_reset = 0;
@@ -1281,14 +1281,12 @@ static int sdma_v3_0_check_soft_reset(void *handle)
1281 } 1281 }
1282 1282
1283 if (srbm_soft_reset) { 1283 if (srbm_soft_reset) {
1284 adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang = true;
1285 adev->sdma.srbm_soft_reset = srbm_soft_reset; 1284 adev->sdma.srbm_soft_reset = srbm_soft_reset;
1285 return true;
1286 } else { 1286 } else {
1287 adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang = false;
1288 adev->sdma.srbm_soft_reset = 0; 1287 adev->sdma.srbm_soft_reset = 0;
1288 return false;
1289 } 1289 }
1290
1291 return 0;
1292} 1290}
1293 1291
1294static int sdma_v3_0_pre_soft_reset(void *handle) 1292static int sdma_v3_0_pre_soft_reset(void *handle)
@@ -1296,7 +1294,7 @@ static int sdma_v3_0_pre_soft_reset(void *handle)
1296 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1294 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1297 u32 srbm_soft_reset = 0; 1295 u32 srbm_soft_reset = 0;
1298 1296
1299 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang) 1297 if (!adev->sdma.srbm_soft_reset)
1300 return 0; 1298 return 0;
1301 1299
1302 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1300 srbm_soft_reset = adev->sdma.srbm_soft_reset;
@@ -1315,7 +1313,7 @@ static int sdma_v3_0_post_soft_reset(void *handle)
1315 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1313 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1316 u32 srbm_soft_reset = 0; 1314 u32 srbm_soft_reset = 0;
1317 1315
1318 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang) 1316 if (!adev->sdma.srbm_soft_reset)
1319 return 0; 1317 return 0;
1320 1318
1321 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1319 srbm_soft_reset = adev->sdma.srbm_soft_reset;
@@ -1335,7 +1333,7 @@ static int sdma_v3_0_soft_reset(void *handle)
1335 u32 srbm_soft_reset = 0; 1333 u32 srbm_soft_reset = 0;
1336 u32 tmp; 1334 u32 tmp;
1337 1335
1338 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang) 1336 if (!adev->sdma.srbm_soft_reset)
1339 return 0; 1337 return 0;
1340 1338
1341 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1339 srbm_soft_reset = adev->sdma.srbm_soft_reset;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 8bd08925b370..3de7bca5854b 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -3499,6 +3499,12 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3499 max_sclk = 75000; 3499 max_sclk = 75000;
3500 max_mclk = 80000; 3500 max_mclk = 80000;
3501 } 3501 }
3502 /* Limit clocks for some HD8600 parts */
3503 if (adev->pdev->device == 0x6660 &&
3504 adev->pdev->revision == 0x83) {
3505 max_sclk = 75000;
3506 max_mclk = 80000;
3507 }
3502 3508
3503 if (rps->vce_active) { 3509 if (rps->vce_active) {
3504 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; 3510 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index d127d59f953a..b4ea229bb449 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -373,7 +373,7 @@ static int tonga_ih_wait_for_idle(void *handle)
373 return -ETIMEDOUT; 373 return -ETIMEDOUT;
374} 374}
375 375
376static int tonga_ih_check_soft_reset(void *handle) 376static bool tonga_ih_check_soft_reset(void *handle)
377{ 377{
378 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 378 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
379 u32 srbm_soft_reset = 0; 379 u32 srbm_soft_reset = 0;
@@ -384,21 +384,19 @@ static int tonga_ih_check_soft_reset(void *handle)
384 SOFT_RESET_IH, 1); 384 SOFT_RESET_IH, 1);
385 385
386 if (srbm_soft_reset) { 386 if (srbm_soft_reset) {
387 adev->ip_block_status[AMD_IP_BLOCK_TYPE_IH].hang = true;
388 adev->irq.srbm_soft_reset = srbm_soft_reset; 387 adev->irq.srbm_soft_reset = srbm_soft_reset;
388 return true;
389 } else { 389 } else {
390 adev->ip_block_status[AMD_IP_BLOCK_TYPE_IH].hang = false;
391 adev->irq.srbm_soft_reset = 0; 390 adev->irq.srbm_soft_reset = 0;
391 return false;
392 } 392 }
393
394 return 0;
395} 393}
396 394
397static int tonga_ih_pre_soft_reset(void *handle) 395static int tonga_ih_pre_soft_reset(void *handle)
398{ 396{
399 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 397 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
400 398
401 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_IH].hang) 399 if (!adev->irq.srbm_soft_reset)
402 return 0; 400 return 0;
403 401
404 return tonga_ih_hw_fini(adev); 402 return tonga_ih_hw_fini(adev);
@@ -408,7 +406,7 @@ static int tonga_ih_post_soft_reset(void *handle)
408{ 406{
409 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 407 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
410 408
411 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_IH].hang) 409 if (!adev->irq.srbm_soft_reset)
412 return 0; 410 return 0;
413 411
414 return tonga_ih_hw_init(adev); 412 return tonga_ih_hw_init(adev);
@@ -419,7 +417,7 @@ static int tonga_ih_soft_reset(void *handle)
419 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 417 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
420 u32 srbm_soft_reset; 418 u32 srbm_soft_reset;
421 419
422 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_IH].hang) 420 if (!adev->irq.srbm_soft_reset)
423 return 0; 421 return 0;
424 srbm_soft_reset = adev->irq.srbm_soft_reset; 422 srbm_soft_reset = adev->irq.srbm_soft_reset;
425 423
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index e0fd9f21ed95..ab3df6d75656 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -770,7 +770,7 @@ static int uvd_v6_0_wait_for_idle(void *handle)
770} 770}
771 771
772#define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd 772#define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd
773static int uvd_v6_0_check_soft_reset(void *handle) 773static bool uvd_v6_0_check_soft_reset(void *handle)
774{ 774{
775 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 775 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
776 u32 srbm_soft_reset = 0; 776 u32 srbm_soft_reset = 0;
@@ -782,19 +782,19 @@ static int uvd_v6_0_check_soft_reset(void *handle)
782 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1); 782 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
783 783
784 if (srbm_soft_reset) { 784 if (srbm_soft_reset) {
785 adev->ip_block_status[AMD_IP_BLOCK_TYPE_UVD].hang = true;
786 adev->uvd.srbm_soft_reset = srbm_soft_reset; 785 adev->uvd.srbm_soft_reset = srbm_soft_reset;
786 return true;
787 } else { 787 } else {
788 adev->ip_block_status[AMD_IP_BLOCK_TYPE_UVD].hang = false;
789 adev->uvd.srbm_soft_reset = 0; 788 adev->uvd.srbm_soft_reset = 0;
789 return false;
790 } 790 }
791 return 0;
792} 791}
792
793static int uvd_v6_0_pre_soft_reset(void *handle) 793static int uvd_v6_0_pre_soft_reset(void *handle)
794{ 794{
795 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 795 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
796 796
797 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_UVD].hang) 797 if (!adev->uvd.srbm_soft_reset)
798 return 0; 798 return 0;
799 799
800 uvd_v6_0_stop(adev); 800 uvd_v6_0_stop(adev);
@@ -806,7 +806,7 @@ static int uvd_v6_0_soft_reset(void *handle)
806 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 806 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
807 u32 srbm_soft_reset; 807 u32 srbm_soft_reset;
808 808
809 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_UVD].hang) 809 if (!adev->uvd.srbm_soft_reset)
810 return 0; 810 return 0;
811 srbm_soft_reset = adev->uvd.srbm_soft_reset; 811 srbm_soft_reset = adev->uvd.srbm_soft_reset;
812 812
@@ -836,7 +836,7 @@ static int uvd_v6_0_post_soft_reset(void *handle)
836{ 836{
837 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 837 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
838 838
839 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_UVD].hang) 839 if (!adev->uvd.srbm_soft_reset)
840 return 0; 840 return 0;
841 841
842 mdelay(5); 842 mdelay(5);
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 3f6db4ec0102..8533269ec160 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -561,7 +561,7 @@ static int vce_v3_0_wait_for_idle(void *handle)
561#define AMDGPU_VCE_STATUS_BUSY_MASK (VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK | \ 561#define AMDGPU_VCE_STATUS_BUSY_MASK (VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK | \
562 VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK) 562 VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK)
563 563
564static int vce_v3_0_check_soft_reset(void *handle) 564static bool vce_v3_0_check_soft_reset(void *handle)
565{ 565{
566 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 566 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
567 u32 srbm_soft_reset = 0; 567 u32 srbm_soft_reset = 0;
@@ -591,16 +591,15 @@ static int vce_v3_0_check_soft_reset(void *handle)
591 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1); 591 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
592 } 592 }
593 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0); 593 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
594 mutex_unlock(&adev->grbm_idx_mutex);
594 595
595 if (srbm_soft_reset) { 596 if (srbm_soft_reset) {
596 adev->ip_block_status[AMD_IP_BLOCK_TYPE_VCE].hang = true;
597 adev->vce.srbm_soft_reset = srbm_soft_reset; 597 adev->vce.srbm_soft_reset = srbm_soft_reset;
598 return true;
598 } else { 599 } else {
599 adev->ip_block_status[AMD_IP_BLOCK_TYPE_VCE].hang = false;
600 adev->vce.srbm_soft_reset = 0; 600 adev->vce.srbm_soft_reset = 0;
601 return false;
601 } 602 }
602 mutex_unlock(&adev->grbm_idx_mutex);
603 return 0;
604} 603}
605 604
606static int vce_v3_0_soft_reset(void *handle) 605static int vce_v3_0_soft_reset(void *handle)
@@ -608,7 +607,7 @@ static int vce_v3_0_soft_reset(void *handle)
608 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 607 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
609 u32 srbm_soft_reset; 608 u32 srbm_soft_reset;
610 609
611 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_VCE].hang) 610 if (!adev->vce.srbm_soft_reset)
612 return 0; 611 return 0;
613 srbm_soft_reset = adev->vce.srbm_soft_reset; 612 srbm_soft_reset = adev->vce.srbm_soft_reset;
614 613
@@ -638,7 +637,7 @@ static int vce_v3_0_pre_soft_reset(void *handle)
638{ 637{
639 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 638 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
640 639
641 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_VCE].hang) 640 if (!adev->vce.srbm_soft_reset)
642 return 0; 641 return 0;
643 642
644 mdelay(5); 643 mdelay(5);
@@ -651,7 +650,7 @@ static int vce_v3_0_post_soft_reset(void *handle)
651{ 650{
652 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 651 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
653 652
654 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_VCE].hang) 653 if (!adev->vce.srbm_soft_reset)
655 return 0; 654 return 0;
656 655
657 mdelay(5); 656 mdelay(5);
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index c934b78c9e2f..bec8125bceb0 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -165,7 +165,7 @@ struct amd_ip_funcs {
165 /* poll for idle */ 165 /* poll for idle */
166 int (*wait_for_idle)(void *handle); 166 int (*wait_for_idle)(void *handle);
167 /* check soft reset the IP block */ 167 /* check soft reset the IP block */
168 int (*check_soft_reset)(void *handle); 168 bool (*check_soft_reset)(void *handle);
169 /* pre soft reset the IP block */ 169 /* pre soft reset the IP block */
170 int (*pre_soft_reset)(void *handle); 170 int (*pre_soft_reset)(void *handle);
171 /* soft reset the IP block */ 171 /* soft reset the IP block */
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
index 92b117843875..8cee4e0f9fde 100644
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
@@ -49,6 +49,7 @@ static const pem_event_action * const uninitialize_event[] = {
49 uninitialize_display_phy_access_tasks, 49 uninitialize_display_phy_access_tasks,
50 disable_gfx_voltage_island_power_gating_tasks, 50 disable_gfx_voltage_island_power_gating_tasks,
51 disable_gfx_clock_gating_tasks, 51 disable_gfx_clock_gating_tasks,
52 uninitialize_thermal_controller_tasks,
52 set_boot_state_tasks, 53 set_boot_state_tasks,
53 adjust_power_state_tasks, 54 adjust_power_state_tasks,
54 disable_dynamic_state_management_tasks, 55 disable_dynamic_state_management_tasks,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index 7e4fcbbbe086..960424913496 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1785,6 +1785,21 @@ static int cz_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_c
1785 return 0; 1785 return 0;
1786} 1786}
1787 1787
1788static int cz_thermal_get_temperature(struct pp_hwmgr *hwmgr)
1789{
1790 int actual_temp = 0;
1791 uint32_t val = cgs_read_ind_register(hwmgr->device,
1792 CGS_IND_REG__SMC, ixTHM_TCON_CUR_TMP);
1793 uint32_t temp = PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP);
1794
1795 if (PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP_RANGE_SEL))
1796 actual_temp = ((temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1797 else
1798 actual_temp = (temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1799
1800 return actual_temp;
1801}
1802
1788static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value) 1803static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
1789{ 1804{
1790 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); 1805 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
@@ -1881,6 +1896,9 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
1881 case AMDGPU_PP_SENSOR_VCE_POWER: 1896 case AMDGPU_PP_SENSOR_VCE_POWER:
1882 *value = cz_hwmgr->vce_power_gated ? 0 : 1; 1897 *value = cz_hwmgr->vce_power_gated ? 0 : 1;
1883 return 0; 1898 return 0;
1899 case AMDGPU_PP_SENSOR_GPU_TEMP:
1900 *value = cz_thermal_get_temperature(hwmgr);
1901 return 0;
1884 default: 1902 default:
1885 return -EINVAL; 1903 return -EINVAL;
1886 } 1904 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 508245d49d33..609996c84ad5 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -1030,20 +1030,19 @@ static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1030 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1030 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1031 1031
1032 /* disable SCLK dpm */ 1032 /* disable SCLK dpm */
1033 if (!data->sclk_dpm_key_disabled) 1033 if (!data->sclk_dpm_key_disabled) {
1034 PP_ASSERT_WITH_CODE( 1034 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1035 (smum_send_msg_to_smc(hwmgr->smumgr, 1035 "Trying to disable SCLK DPM when DPM is disabled",
1036 PPSMC_MSG_DPM_Disable) == 0), 1036 return 0);
1037 "Failed to disable SCLK DPM!", 1037 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Disable);
1038 return -EINVAL); 1038 }
1039 1039
1040 /* disable MCLK dpm */ 1040 /* disable MCLK dpm */
1041 if (!data->mclk_dpm_key_disabled) { 1041 if (!data->mclk_dpm_key_disabled) {
1042 PP_ASSERT_WITH_CODE( 1042 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1043 (smum_send_msg_to_smc(hwmgr->smumgr, 1043 "Trying to disable MCLK DPM when DPM is disabled",
1044 PPSMC_MSG_MCLKDPM_Disable) == 0), 1044 return 0);
1045 "Failed to disable MCLK DPM!", 1045 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MCLKDPM_Disable);
1046 return -EINVAL);
1047 } 1046 }
1048 1047
1049 return 0; 1048 return 0;
@@ -1069,10 +1068,13 @@ static int smu7_stop_dpm(struct pp_hwmgr *hwmgr)
1069 return -EINVAL); 1068 return -EINVAL);
1070 } 1069 }
1071 1070
1072 if (smu7_disable_sclk_mclk_dpm(hwmgr)) { 1071 smu7_disable_sclk_mclk_dpm(hwmgr);
1073 printk(KERN_ERR "Failed to disable Sclk DPM and Mclk DPM!"); 1072
1074 return -EINVAL; 1073 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1075 } 1074 "Trying to disable voltage DPM when DPM is disabled",
1075 return 0);
1076
1077 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Disable);
1076 1078
1077 return 0; 1079 return 0;
1078} 1080}
@@ -1226,7 +1228,7 @@ int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1226 PP_ASSERT_WITH_CODE((0 == tmp_result), 1228 PP_ASSERT_WITH_CODE((0 == tmp_result),
1227 "Failed to enable VR hot GPIO interrupt!", result = tmp_result); 1229 "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
1228 1230
1229 smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay); 1231 smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_NoDisplay);
1230 1232
1231 tmp_result = smu7_enable_sclk_control(hwmgr); 1233 tmp_result = smu7_enable_sclk_control(hwmgr);
1232 PP_ASSERT_WITH_CODE((0 == tmp_result), 1234 PP_ASSERT_WITH_CODE((0 == tmp_result),
@@ -1306,6 +1308,12 @@ int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
1306 PP_ASSERT_WITH_CODE((tmp_result == 0), 1308 PP_ASSERT_WITH_CODE((tmp_result == 0),
1307 "Failed to disable thermal auto throttle!", result = tmp_result); 1309 "Failed to disable thermal auto throttle!", result = tmp_result);
1308 1310
1311 if (1 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
1312 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableAvfs)),
1313 "Failed to disable AVFS!",
1314 return -EINVAL);
1315 }
1316
1309 tmp_result = smu7_stop_dpm(hwmgr); 1317 tmp_result = smu7_stop_dpm(hwmgr);
1310 PP_ASSERT_WITH_CODE((tmp_result == 0), 1318 PP_ASSERT_WITH_CODE((tmp_result == 0),
1311 "Failed to stop DPM!", result = tmp_result); 1319 "Failed to stop DPM!", result = tmp_result);
@@ -1452,8 +1460,10 @@ static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
1452 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL; 1460 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL;
1453 1461
1454 1462
1455 if (table_info != NULL) 1463 if (table_info == NULL)
1456 sclk_table = table_info->vdd_dep_on_sclk; 1464 return -EINVAL;
1465
1466 sclk_table = table_info->vdd_dep_on_sclk;
1457 1467
1458 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) { 1468 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
1459 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 1469 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
@@ -3802,13 +3812,15 @@ static inline bool smu7_are_power_levels_equal(const struct smu7_performance_lev
3802 3812
3803int smu7_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal) 3813int smu7_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
3804{ 3814{
3805 const struct smu7_power_state *psa = cast_const_phw_smu7_power_state(pstate1); 3815 const struct smu7_power_state *psa;
3806 const struct smu7_power_state *psb = cast_const_phw_smu7_power_state(pstate2); 3816 const struct smu7_power_state *psb;
3807 int i; 3817 int i;
3808 3818
3809 if (pstate1 == NULL || pstate2 == NULL || equal == NULL) 3819 if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
3810 return -EINVAL; 3820 return -EINVAL;
3811 3821
3822 psa = cast_const_phw_smu7_power_state(pstate1);
3823 psb = cast_const_phw_smu7_power_state(pstate2);
3812 /* If the two states don't even have the same number of performance levels they cannot be the same state. */ 3824 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
3813 if (psa->performance_level_count != psb->performance_level_count) { 3825 if (psa->performance_level_count != psb->performance_level_count) {
3814 *equal = false; 3826 *equal = false;
@@ -4324,6 +4336,7 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
4324 .set_mclk_od = smu7_set_mclk_od, 4336 .set_mclk_od = smu7_set_mclk_od,
4325 .get_clock_by_type = smu7_get_clock_by_type, 4337 .get_clock_by_type = smu7_get_clock_by_type,
4326 .read_sensor = smu7_read_sensor, 4338 .read_sensor = smu7_read_sensor,
4339 .dynamic_state_management_disable = smu7_disable_dpm_tasks,
4327}; 4340};
4328 4341
4329uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock, 4342uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
index eda802bc63c8..8c889caba420 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
@@ -2458,7 +2458,7 @@ static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr,
2458 PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), 2458 PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2459 "Invalid VramInfo table.", return -EINVAL); 2459 "Invalid VramInfo table.", return -EINVAL);
2460 2460
2461 if (!data->is_memory_gddr5) { 2461 if (!data->is_memory_gddr5 && j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE) {
2462 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; 2462 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
2463 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; 2463 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
2464 for (k = 0; k < table->num_entries; k++) { 2464 for (k = 0; k < table->num_entries; k++) {
diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c
index 2f58e9e2a59c..a51f8cbcfe26 100644
--- a/drivers/gpu/drm/armada/armada_crtc.c
+++ b/drivers/gpu/drm/armada/armada_crtc.c
@@ -332,17 +332,19 @@ static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
332{ 332{
333 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 333 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
334 334
335 if (dcrtc->dpms != dpms) { 335 if (dpms_blanked(dcrtc->dpms) != dpms_blanked(dpms)) {
336 dcrtc->dpms = dpms;
337 if (!IS_ERR(dcrtc->clk) && !dpms_blanked(dpms))
338 WARN_ON(clk_prepare_enable(dcrtc->clk));
339 armada_drm_crtc_update(dcrtc);
340 if (!IS_ERR(dcrtc->clk) && dpms_blanked(dpms))
341 clk_disable_unprepare(dcrtc->clk);
342 if (dpms_blanked(dpms)) 336 if (dpms_blanked(dpms))
343 armada_drm_vblank_off(dcrtc); 337 armada_drm_vblank_off(dcrtc);
344 else 338 else if (!IS_ERR(dcrtc->clk))
339 WARN_ON(clk_prepare_enable(dcrtc->clk));
340 dcrtc->dpms = dpms;
341 armada_drm_crtc_update(dcrtc);
342 if (!dpms_blanked(dpms))
345 drm_crtc_vblank_on(&dcrtc->crtc); 343 drm_crtc_vblank_on(&dcrtc->crtc);
344 else if (!IS_ERR(dcrtc->clk))
345 clk_disable_unprepare(dcrtc->clk);
346 } else if (dcrtc->dpms != dpms) {
347 dcrtc->dpms = dpms;
346 } 348 }
347} 349}
348 350
diff --git a/drivers/gpu/drm/drm_info.c b/drivers/gpu/drm/drm_info.c
index 1df2d33d0b40..ffb2ab389d1d 100644
--- a/drivers/gpu/drm/drm_info.c
+++ b/drivers/gpu/drm/drm_info.c
@@ -54,9 +54,6 @@ int drm_name_info(struct seq_file *m, void *data)
54 54
55 mutex_lock(&dev->master_mutex); 55 mutex_lock(&dev->master_mutex);
56 master = dev->master; 56 master = dev->master;
57 if (!master)
58 goto out_unlock;
59
60 seq_printf(m, "%s", dev->driver->name); 57 seq_printf(m, "%s", dev->driver->name);
61 if (dev->dev) 58 if (dev->dev)
62 seq_printf(m, " dev=%s", dev_name(dev->dev)); 59 seq_printf(m, " dev=%s", dev_name(dev->dev));
@@ -65,7 +62,6 @@ int drm_name_info(struct seq_file *m, void *data)
65 if (dev->unique) 62 if (dev->unique)
66 seq_printf(m, " unique=%s", dev->unique); 63 seq_printf(m, " unique=%s", dev->unique);
67 seq_printf(m, "\n"); 64 seq_printf(m, "\n");
68out_unlock:
69 mutex_unlock(&dev->master_mutex); 65 mutex_unlock(&dev->master_mutex);
70 66
71 return 0; 67 return 0;
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
index cb86c7e5495c..d9230132dfbc 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
@@ -329,20 +329,34 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, unsigned int event,
329 /* 329 /*
330 * Append a LINK to the submitted command buffer to return to 330 * Append a LINK to the submitted command buffer to return to
331 * the ring buffer. return_target is the ring target address. 331 * the ring buffer. return_target is the ring target address.
332 * We need three dwords: event, wait, link. 332 * We need at most 7 dwords in the return target: 2 cache flush +
333 * 2 semaphore stall + 1 event + 1 wait + 1 link.
333 */ 334 */
334 return_dwords = 3; 335 return_dwords = 7;
335 return_target = etnaviv_buffer_reserve(gpu, buffer, return_dwords); 336 return_target = etnaviv_buffer_reserve(gpu, buffer, return_dwords);
336 CMD_LINK(cmdbuf, return_dwords, return_target); 337 CMD_LINK(cmdbuf, return_dwords, return_target);
337 338
338 /* 339 /*
339 * Append event, wait and link pointing back to the wait 340 * Append a cache flush, stall, event, wait and link pointing back to
340 * command to the ring buffer. 341 * the wait command to the ring buffer.
341 */ 342 */
343 if (gpu->exec_state == ETNA_PIPE_2D) {
344 CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE,
345 VIVS_GL_FLUSH_CACHE_PE2D);
346 } else {
347 CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE,
348 VIVS_GL_FLUSH_CACHE_DEPTH |
349 VIVS_GL_FLUSH_CACHE_COLOR);
350 CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE,
351 VIVS_TS_FLUSH_CACHE_FLUSH);
352 }
353 CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
354 CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
342 CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) | 355 CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) |
343 VIVS_GL_EVENT_FROM_PE); 356 VIVS_GL_EVENT_FROM_PE);
344 CMD_WAIT(buffer); 357 CMD_WAIT(buffer);
345 CMD_LINK(buffer, 2, return_target + 8); 358 CMD_LINK(buffer, 2, etnaviv_iommu_get_cmdbuf_va(gpu, buffer) +
359 buffer->user_size - 4);
346 360
347 if (drm_debug & DRM_UT_DRIVER) 361 if (drm_debug & DRM_UT_DRIVER)
348 pr_info("stream link to 0x%08x @ 0x%08x %p\n", 362 pr_info("stream link to 0x%08x @ 0x%08x %p\n",
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem.c b/drivers/gpu/drm/etnaviv/etnaviv_gem.c
index 5ce3603e6eac..0370b842d9cc 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gem.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gem.c
@@ -748,19 +748,22 @@ static struct page **etnaviv_gem_userptr_do_get_pages(
748 int ret = 0, pinned, npages = etnaviv_obj->base.size >> PAGE_SHIFT; 748 int ret = 0, pinned, npages = etnaviv_obj->base.size >> PAGE_SHIFT;
749 struct page **pvec; 749 struct page **pvec;
750 uintptr_t ptr; 750 uintptr_t ptr;
751 unsigned int flags = 0;
751 752
752 pvec = drm_malloc_ab(npages, sizeof(struct page *)); 753 pvec = drm_malloc_ab(npages, sizeof(struct page *));
753 if (!pvec) 754 if (!pvec)
754 return ERR_PTR(-ENOMEM); 755 return ERR_PTR(-ENOMEM);
755 756
757 if (!etnaviv_obj->userptr.ro)
758 flags |= FOLL_WRITE;
759
756 pinned = 0; 760 pinned = 0;
757 ptr = etnaviv_obj->userptr.ptr; 761 ptr = etnaviv_obj->userptr.ptr;
758 762
759 down_read(&mm->mmap_sem); 763 down_read(&mm->mmap_sem);
760 while (pinned < npages) { 764 while (pinned < npages) {
761 ret = get_user_pages_remote(task, mm, ptr, npages - pinned, 765 ret = get_user_pages_remote(task, mm, ptr, npages - pinned,
762 !etnaviv_obj->userptr.ro, 0, 766 flags, pvec + pinned, NULL);
763 pvec + pinned, NULL);
764 if (ret < 0) 767 if (ret < 0)
765 break; 768 break;
766 769
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_mmu.c b/drivers/gpu/drm/etnaviv/etnaviv_mmu.c
index d3796ed8d8c5..169ac96e8f08 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_mmu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_mmu.c
@@ -330,7 +330,8 @@ u32 etnaviv_iommu_get_cmdbuf_va(struct etnaviv_gpu *gpu,
330 return (u32)buf->vram_node.start; 330 return (u32)buf->vram_node.start;
331 331
332 mutex_lock(&mmu->lock); 332 mutex_lock(&mmu->lock);
333 ret = etnaviv_iommu_find_iova(mmu, &buf->vram_node, buf->size); 333 ret = etnaviv_iommu_find_iova(mmu, &buf->vram_node,
334 buf->size + SZ_64K);
334 if (ret < 0) { 335 if (ret < 0) {
335 mutex_unlock(&mmu->lock); 336 mutex_unlock(&mmu->lock);
336 return 0; 337 return 0;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
index aa92decf4233..fbd13fabdf2d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
@@ -488,7 +488,8 @@ static dma_addr_t *g2d_userptr_get_dma_addr(struct drm_device *drm_dev,
488 goto err_free; 488 goto err_free;
489 } 489 }
490 490
491 ret = get_vaddr_frames(start, npages, true, true, g2d_userptr->vec); 491 ret = get_vaddr_frames(start, npages, FOLL_FORCE | FOLL_WRITE,
492 g2d_userptr->vec);
492 if (ret != npages) { 493 if (ret != npages) {
493 DRM_ERROR("failed to get user pages from userptr.\n"); 494 DRM_ERROR("failed to get user pages from userptr.\n");
494 if (ret < 0) 495 if (ret < 0)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index 3371635cd4d7..b2d5e188b1b8 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
@@ -51,6 +51,7 @@ static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc)
51 DCU_MODE_DCU_MODE(DCU_MODE_OFF)); 51 DCU_MODE_DCU_MODE(DCU_MODE_OFF));
52 regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE, 52 regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
53 DCU_UPDATE_MODE_READREG); 53 DCU_UPDATE_MODE_READREG);
54 clk_disable_unprepare(fsl_dev->pix_clk);
54} 55}
55 56
56static void fsl_dcu_drm_crtc_enable(struct drm_crtc *crtc) 57static void fsl_dcu_drm_crtc_enable(struct drm_crtc *crtc)
@@ -58,6 +59,7 @@ static void fsl_dcu_drm_crtc_enable(struct drm_crtc *crtc)
58 struct drm_device *dev = crtc->dev; 59 struct drm_device *dev = crtc->dev;
59 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; 60 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
60 61
62 clk_prepare_enable(fsl_dev->pix_clk);
61 regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE, 63 regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
62 DCU_MODE_DCU_MODE_MASK, 64 DCU_MODE_DCU_MODE_MASK,
63 DCU_MODE_DCU_MODE(DCU_MODE_NORMAL)); 65 DCU_MODE_DCU_MODE(DCU_MODE_NORMAL));
@@ -116,8 +118,6 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
116 DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) | 118 DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) |
117 DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) | 119 DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) |
118 DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL)); 120 DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL));
119 regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
120 DCU_UPDATE_MODE_READREG);
121 return; 121 return;
122} 122}
123 123
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index 0884c45aefe8..e04efbed1a54 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -267,12 +267,8 @@ static int fsl_dcu_drm_pm_resume(struct device *dev)
267 return ret; 267 return ret;
268 } 268 }
269 269
270 ret = clk_prepare_enable(fsl_dev->pix_clk); 270 if (fsl_dev->tcon)
271 if (ret < 0) { 271 fsl_tcon_bypass_enable(fsl_dev->tcon);
272 dev_err(dev, "failed to enable pix clk\n");
273 goto disable_dcu_clk;
274 }
275
276 fsl_dcu_drm_init_planes(fsl_dev->drm); 272 fsl_dcu_drm_init_planes(fsl_dev->drm);
277 drm_atomic_helper_resume(fsl_dev->drm, fsl_dev->state); 273 drm_atomic_helper_resume(fsl_dev->drm, fsl_dev->state);
278 274
@@ -284,10 +280,6 @@ static int fsl_dcu_drm_pm_resume(struct device *dev)
284 enable_irq(fsl_dev->irq); 280 enable_irq(fsl_dev->irq);
285 281
286 return 0; 282 return 0;
287
288disable_dcu_clk:
289 clk_disable_unprepare(fsl_dev->clk);
290 return ret;
291} 283}
292#endif 284#endif
293 285
@@ -401,18 +393,12 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
401 goto disable_clk; 393 goto disable_clk;
402 } 394 }
403 395
404 ret = clk_prepare_enable(fsl_dev->pix_clk);
405 if (ret < 0) {
406 dev_err(dev, "failed to enable pix clk\n");
407 goto unregister_pix_clk;
408 }
409
410 fsl_dev->tcon = fsl_tcon_init(dev); 396 fsl_dev->tcon = fsl_tcon_init(dev);
411 397
412 drm = drm_dev_alloc(driver, dev); 398 drm = drm_dev_alloc(driver, dev);
413 if (IS_ERR(drm)) { 399 if (IS_ERR(drm)) {
414 ret = PTR_ERR(drm); 400 ret = PTR_ERR(drm);
415 goto disable_pix_clk; 401 goto unregister_pix_clk;
416 } 402 }
417 403
418 fsl_dev->dev = dev; 404 fsl_dev->dev = dev;
@@ -433,8 +419,6 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
433 419
434unref: 420unref:
435 drm_dev_unref(drm); 421 drm_dev_unref(drm);
436disable_pix_clk:
437 clk_disable_unprepare(fsl_dev->pix_clk);
438unregister_pix_clk: 422unregister_pix_clk:
439 clk_unregister(fsl_dev->pix_clk); 423 clk_unregister(fsl_dev->pix_clk);
440disable_clk: 424disable_clk:
@@ -447,7 +431,6 @@ static int fsl_dcu_drm_remove(struct platform_device *pdev)
447 struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev); 431 struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev);
448 432
449 clk_disable_unprepare(fsl_dev->clk); 433 clk_disable_unprepare(fsl_dev->clk);
450 clk_disable_unprepare(fsl_dev->pix_clk);
451 clk_unregister(fsl_dev->pix_clk); 434 clk_unregister(fsl_dev->pix_clk);
452 drm_put_dev(fsl_dev->drm); 435 drm_put_dev(fsl_dev->drm);
453 436
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c
index a7e5486bd1e9..9e6f7d8112b3 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c
@@ -211,11 +211,6 @@ void fsl_dcu_drm_init_planes(struct drm_device *dev)
211 for (j = 1; j <= fsl_dev->soc->layer_regs; j++) 211 for (j = 1; j <= fsl_dev->soc->layer_regs; j++)
212 regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(i, j), 0); 212 regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(i, j), 0);
213 } 213 }
214 regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
215 DCU_MODE_DCU_MODE_MASK,
216 DCU_MODE_DCU_MODE(DCU_MODE_OFF));
217 regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
218 DCU_UPDATE_MODE_READREG);
219} 214}
220 215
221struct drm_plane *fsl_dcu_drm_primary_create_plane(struct drm_device *dev) 216struct drm_plane *fsl_dcu_drm_primary_create_plane(struct drm_device *dev)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
index 26edcc899712..e1dd75b18118 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
@@ -20,38 +20,6 @@
20#include "fsl_dcu_drm_drv.h" 20#include "fsl_dcu_drm_drv.h"
21#include "fsl_tcon.h" 21#include "fsl_tcon.h"
22 22
23static int
24fsl_dcu_drm_encoder_atomic_check(struct drm_encoder *encoder,
25 struct drm_crtc_state *crtc_state,
26 struct drm_connector_state *conn_state)
27{
28 return 0;
29}
30
31static void fsl_dcu_drm_encoder_disable(struct drm_encoder *encoder)
32{
33 struct drm_device *dev = encoder->dev;
34 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
35
36 if (fsl_dev->tcon)
37 fsl_tcon_bypass_disable(fsl_dev->tcon);
38}
39
40static void fsl_dcu_drm_encoder_enable(struct drm_encoder *encoder)
41{
42 struct drm_device *dev = encoder->dev;
43 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
44
45 if (fsl_dev->tcon)
46 fsl_tcon_bypass_enable(fsl_dev->tcon);
47}
48
49static const struct drm_encoder_helper_funcs encoder_helper_funcs = {
50 .atomic_check = fsl_dcu_drm_encoder_atomic_check,
51 .disable = fsl_dcu_drm_encoder_disable,
52 .enable = fsl_dcu_drm_encoder_enable,
53};
54
55static void fsl_dcu_drm_encoder_destroy(struct drm_encoder *encoder) 23static void fsl_dcu_drm_encoder_destroy(struct drm_encoder *encoder)
56{ 24{
57 drm_encoder_cleanup(encoder); 25 drm_encoder_cleanup(encoder);
@@ -68,13 +36,16 @@ int fsl_dcu_drm_encoder_create(struct fsl_dcu_drm_device *fsl_dev,
68 int ret; 36 int ret;
69 37
70 encoder->possible_crtcs = 1; 38 encoder->possible_crtcs = 1;
39
40 /* Use bypass mode for parallel RGB/LVDS encoder */
41 if (fsl_dev->tcon)
42 fsl_tcon_bypass_enable(fsl_dev->tcon);
43
71 ret = drm_encoder_init(fsl_dev->drm, encoder, &encoder_funcs, 44 ret = drm_encoder_init(fsl_dev->drm, encoder, &encoder_funcs,
72 DRM_MODE_ENCODER_LVDS, NULL); 45 DRM_MODE_ENCODER_LVDS, NULL);
73 if (ret < 0) 46 if (ret < 0)
74 return ret; 47 return ret;
75 48
76 drm_encoder_helper_add(encoder, &encoder_helper_funcs);
77
78 return 0; 49 return 0;
79} 50}
80 51
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/drm/i915/i915_gem_userptr.c
index e537930c64b5..c6f780f5abc9 100644
--- a/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@ -508,6 +508,10 @@ __i915_gem_userptr_get_pages_worker(struct work_struct *_work)
508 pvec = drm_malloc_gfp(npages, sizeof(struct page *), GFP_TEMPORARY); 508 pvec = drm_malloc_gfp(npages, sizeof(struct page *), GFP_TEMPORARY);
509 if (pvec != NULL) { 509 if (pvec != NULL) {
510 struct mm_struct *mm = obj->userptr.mm->mm; 510 struct mm_struct *mm = obj->userptr.mm->mm;
511 unsigned int flags = 0;
512
513 if (!obj->userptr.read_only)
514 flags |= FOLL_WRITE;
511 515
512 ret = -EFAULT; 516 ret = -EFAULT;
513 if (atomic_inc_not_zero(&mm->mm_users)) { 517 if (atomic_inc_not_zero(&mm->mm_users)) {
@@ -517,7 +521,7 @@ __i915_gem_userptr_get_pages_worker(struct work_struct *_work)
517 (work->task, mm, 521 (work->task, mm,
518 obj->userptr.ptr + pinned * PAGE_SIZE, 522 obj->userptr.ptr + pinned * PAGE_SIZE,
519 npages - pinned, 523 npages - pinned,
520 !obj->userptr.read_only, 0, 524 flags,
521 pvec + pinned, NULL); 525 pvec + pinned, NULL);
522 if (ret < 0) 526 if (ret < 0)
523 break; 527 break;
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c
index 6a4b020dd0b4..5a26eb4545aa 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -156,19 +156,20 @@ u32 r600_dpm_get_vblank_time(struct radeon_device *rdev)
156 struct drm_device *dev = rdev->ddev; 156 struct drm_device *dev = rdev->ddev;
157 struct drm_crtc *crtc; 157 struct drm_crtc *crtc;
158 struct radeon_crtc *radeon_crtc; 158 struct radeon_crtc *radeon_crtc;
159 u32 line_time_us, vblank_lines; 159 u32 vblank_in_pixels;
160 u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */ 160 u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */
161 161
162 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 162 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
163 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 163 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
164 radeon_crtc = to_radeon_crtc(crtc); 164 radeon_crtc = to_radeon_crtc(crtc);
165 if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) { 165 if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
166 line_time_us = (radeon_crtc->hw_mode.crtc_htotal * 1000) / 166 vblank_in_pixels =
167 radeon_crtc->hw_mode.clock; 167 radeon_crtc->hw_mode.crtc_htotal *
168 vblank_lines = radeon_crtc->hw_mode.crtc_vblank_end - 168 (radeon_crtc->hw_mode.crtc_vblank_end -
169 radeon_crtc->hw_mode.crtc_vdisplay + 169 radeon_crtc->hw_mode.crtc_vdisplay +
170 (radeon_crtc->v_border * 2); 170 (radeon_crtc->v_border * 2));
171 vblank_time_us = vblank_lines * line_time_us; 171
172 vblank_time_us = vblank_in_pixels * 1000 / radeon_crtc->hw_mode.clock;
172 break; 173 break;
173 } 174 }
174 } 175 }
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 50e96d2c593d..e18839d52e3e 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -927,6 +927,16 @@ radeon_lvds_detect(struct drm_connector *connector, bool force)
927 return ret; 927 return ret;
928} 928}
929 929
930static void radeon_connector_unregister(struct drm_connector *connector)
931{
932 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
933
934 if (radeon_connector->ddc_bus->has_aux) {
935 drm_dp_aux_unregister(&radeon_connector->ddc_bus->aux);
936 radeon_connector->ddc_bus->has_aux = false;
937 }
938}
939
930static void radeon_connector_destroy(struct drm_connector *connector) 940static void radeon_connector_destroy(struct drm_connector *connector)
931{ 941{
932 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 942 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
@@ -984,6 +994,7 @@ static const struct drm_connector_funcs radeon_lvds_connector_funcs = {
984 .dpms = drm_helper_connector_dpms, 994 .dpms = drm_helper_connector_dpms,
985 .detect = radeon_lvds_detect, 995 .detect = radeon_lvds_detect,
986 .fill_modes = drm_helper_probe_single_connector_modes, 996 .fill_modes = drm_helper_probe_single_connector_modes,
997 .early_unregister = radeon_connector_unregister,
987 .destroy = radeon_connector_destroy, 998 .destroy = radeon_connector_destroy,
988 .set_property = radeon_lvds_set_property, 999 .set_property = radeon_lvds_set_property,
989}; 1000};
@@ -1111,6 +1122,7 @@ static const struct drm_connector_funcs radeon_vga_connector_funcs = {
1111 .dpms = drm_helper_connector_dpms, 1122 .dpms = drm_helper_connector_dpms,
1112 .detect = radeon_vga_detect, 1123 .detect = radeon_vga_detect,
1113 .fill_modes = drm_helper_probe_single_connector_modes, 1124 .fill_modes = drm_helper_probe_single_connector_modes,
1125 .early_unregister = radeon_connector_unregister,
1114 .destroy = radeon_connector_destroy, 1126 .destroy = radeon_connector_destroy,
1115 .set_property = radeon_connector_set_property, 1127 .set_property = radeon_connector_set_property,
1116}; 1128};
@@ -1188,6 +1200,7 @@ static const struct drm_connector_funcs radeon_tv_connector_funcs = {
1188 .dpms = drm_helper_connector_dpms, 1200 .dpms = drm_helper_connector_dpms,
1189 .detect = radeon_tv_detect, 1201 .detect = radeon_tv_detect,
1190 .fill_modes = drm_helper_probe_single_connector_modes, 1202 .fill_modes = drm_helper_probe_single_connector_modes,
1203 .early_unregister = radeon_connector_unregister,
1191 .destroy = radeon_connector_destroy, 1204 .destroy = radeon_connector_destroy,
1192 .set_property = radeon_connector_set_property, 1205 .set_property = radeon_connector_set_property,
1193}; 1206};
@@ -1519,6 +1532,7 @@ static const struct drm_connector_funcs radeon_dvi_connector_funcs = {
1519 .detect = radeon_dvi_detect, 1532 .detect = radeon_dvi_detect,
1520 .fill_modes = drm_helper_probe_single_connector_modes, 1533 .fill_modes = drm_helper_probe_single_connector_modes,
1521 .set_property = radeon_connector_set_property, 1534 .set_property = radeon_connector_set_property,
1535 .early_unregister = radeon_connector_unregister,
1522 .destroy = radeon_connector_destroy, 1536 .destroy = radeon_connector_destroy,
1523 .force = radeon_dvi_force, 1537 .force = radeon_dvi_force,
1524}; 1538};
@@ -1832,6 +1846,7 @@ static const struct drm_connector_funcs radeon_dp_connector_funcs = {
1832 .detect = radeon_dp_detect, 1846 .detect = radeon_dp_detect,
1833 .fill_modes = drm_helper_probe_single_connector_modes, 1847 .fill_modes = drm_helper_probe_single_connector_modes,
1834 .set_property = radeon_connector_set_property, 1848 .set_property = radeon_connector_set_property,
1849 .early_unregister = radeon_connector_unregister,
1835 .destroy = radeon_connector_destroy, 1850 .destroy = radeon_connector_destroy,
1836 .force = radeon_dvi_force, 1851 .force = radeon_dvi_force,
1837}; 1852};
@@ -1841,6 +1856,7 @@ static const struct drm_connector_funcs radeon_edp_connector_funcs = {
1841 .detect = radeon_dp_detect, 1856 .detect = radeon_dp_detect,
1842 .fill_modes = drm_helper_probe_single_connector_modes, 1857 .fill_modes = drm_helper_probe_single_connector_modes,
1843 .set_property = radeon_lvds_set_property, 1858 .set_property = radeon_lvds_set_property,
1859 .early_unregister = radeon_connector_unregister,
1844 .destroy = radeon_connector_destroy, 1860 .destroy = radeon_connector_destroy,
1845 .force = radeon_dvi_force, 1861 .force = radeon_dvi_force,
1846}; 1862};
@@ -1850,6 +1866,7 @@ static const struct drm_connector_funcs radeon_lvds_bridge_connector_funcs = {
1850 .detect = radeon_dp_detect, 1866 .detect = radeon_dp_detect,
1851 .fill_modes = drm_helper_probe_single_connector_modes, 1867 .fill_modes = drm_helper_probe_single_connector_modes,
1852 .set_property = radeon_lvds_set_property, 1868 .set_property = radeon_lvds_set_property,
1869 .early_unregister = radeon_connector_unregister,
1853 .destroy = radeon_connector_destroy, 1870 .destroy = radeon_connector_destroy,
1854 .force = radeon_dvi_force, 1871 .force = radeon_dvi_force,
1855}; 1872};
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index b8ab30a7dd6d..cdb8cb568c15 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -1675,20 +1675,20 @@ int radeon_modeset_init(struct radeon_device *rdev)
1675 1675
1676void radeon_modeset_fini(struct radeon_device *rdev) 1676void radeon_modeset_fini(struct radeon_device *rdev)
1677{ 1677{
1678 radeon_fbdev_fini(rdev);
1679 kfree(rdev->mode_info.bios_hardcoded_edid);
1680
1681 /* free i2c buses */
1682 radeon_i2c_fini(rdev);
1683
1684 if (rdev->mode_info.mode_config_initialized) { 1678 if (rdev->mode_info.mode_config_initialized) {
1685 radeon_afmt_fini(rdev);
1686 drm_kms_helper_poll_fini(rdev->ddev); 1679 drm_kms_helper_poll_fini(rdev->ddev);
1687 radeon_hpd_fini(rdev); 1680 radeon_hpd_fini(rdev);
1688 drm_crtc_force_disable_all(rdev->ddev); 1681 drm_crtc_force_disable_all(rdev->ddev);
1682 radeon_fbdev_fini(rdev);
1683 radeon_afmt_fini(rdev);
1689 drm_mode_config_cleanup(rdev->ddev); 1684 drm_mode_config_cleanup(rdev->ddev);
1690 rdev->mode_info.mode_config_initialized = false; 1685 rdev->mode_info.mode_config_initialized = false;
1691 } 1686 }
1687
1688 kfree(rdev->mode_info.bios_hardcoded_edid);
1689
1690 /* free i2c buses */
1691 radeon_i2c_fini(rdev);
1692} 1692}
1693 1693
1694static bool is_hdtv_mode(const struct drm_display_mode *mode) 1694static bool is_hdtv_mode(const struct drm_display_mode *mode)
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 91c8f4339566..00ea0002b539 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -96,9 +96,10 @@
96 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI 96 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
97 * 2.46.0 - Add PFP_SYNC_ME support on evergreen 97 * 2.46.0 - Add PFP_SYNC_ME support on evergreen
98 * 2.47.0 - Add UVD_NO_OP register support 98 * 2.47.0 - Add UVD_NO_OP register support
99 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
99 */ 100 */
100#define KMS_DRIVER_MAJOR 2 101#define KMS_DRIVER_MAJOR 2
101#define KMS_DRIVER_MINOR 47 102#define KMS_DRIVER_MINOR 48
102#define KMS_DRIVER_PATCHLEVEL 0 103#define KMS_DRIVER_PATCHLEVEL 0
103int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 104int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
104int radeon_driver_unload_kms(struct drm_device *dev); 105int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
index 021aa005623f..29f7817af821 100644
--- a/drivers/gpu/drm/radeon/radeon_i2c.c
+++ b/drivers/gpu/drm/radeon/radeon_i2c.c
@@ -982,9 +982,8 @@ void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
982{ 982{
983 if (!i2c) 983 if (!i2c)
984 return; 984 return;
985 WARN_ON(i2c->has_aux);
985 i2c_del_adapter(&i2c->adapter); 986 i2c_del_adapter(&i2c->adapter);
986 if (i2c->has_aux)
987 drm_dp_aux_unregister(&i2c->aux);
988 kfree(i2c); 987 kfree(i2c);
989} 988}
990 989
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 455268214b89..3de5e6e21662 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -566,7 +566,8 @@ static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm)
566 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; 566 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
567 struct page **pages = ttm->pages + pinned; 567 struct page **pages = ttm->pages + pinned;
568 568
569 r = get_user_pages(userptr, num_pages, write, 0, pages, NULL); 569 r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0,
570 pages, NULL);
570 if (r < 0) 571 if (r < 0)
571 goto release_pages; 572 goto release_pages;
572 573
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 7ee9aafbdf74..e402be8821c4 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -4431,6 +4431,7 @@ static bool si_vm_reg_valid(u32 reg)
4431 case SPI_CONFIG_CNTL: 4431 case SPI_CONFIG_CNTL:
4432 case SPI_CONFIG_CNTL_1: 4432 case SPI_CONFIG_CNTL_1:
4433 case TA_CNTL_AUX: 4433 case TA_CNTL_AUX:
4434 case TA_CS_BC_BASE_ADDR:
4434 return true; 4435 return true;
4435 default: 4436 default:
4436 DRM_ERROR("Invalid register 0x%x in CS\n", reg); 4437 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index eb220eecba78..65a911ddd509 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -1145,6 +1145,7 @@
1145#define SPI_LB_CU_MASK 0x9354 1145#define SPI_LB_CU_MASK 0x9354
1146 1146
1147#define TA_CNTL_AUX 0x9508 1147#define TA_CNTL_AUX 0x9508
1148#define TA_CS_BC_BASE_ADDR 0x950C
1148 1149
1149#define CC_RB_BACKEND_DISABLE 0x98F4 1150#define CC_RB_BACKEND_DISABLE 0x98F4
1150#define BACKEND_DISABLE(x) ((x) << 16) 1151#define BACKEND_DISABLE(x) ((x) << 16)
diff --git a/drivers/gpu/drm/via/via_dmablit.c b/drivers/gpu/drm/via/via_dmablit.c
index 7e2a12c4fed2..1a3ad769f8c8 100644
--- a/drivers/gpu/drm/via/via_dmablit.c
+++ b/drivers/gpu/drm/via/via_dmablit.c
@@ -241,8 +241,8 @@ via_lock_all_dma_pages(drm_via_sg_info_t *vsg, drm_via_dmablit_t *xfer)
241 down_read(&current->mm->mmap_sem); 241 down_read(&current->mm->mmap_sem);
242 ret = get_user_pages((unsigned long)xfer->mem_addr, 242 ret = get_user_pages((unsigned long)xfer->mem_addr,
243 vsg->num_pages, 243 vsg->num_pages,
244 (vsg->direction == DMA_FROM_DEVICE), 244 (vsg->direction == DMA_FROM_DEVICE) ? FOLL_WRITE : 0,
245 0, vsg->pages, NULL); 245 vsg->pages, NULL);
246 246
247 up_read(&current->mm->mmap_sem); 247 up_read(&current->mm->mmap_sem);
248 if (ret != vsg->num_pages) { 248 if (ret != vsg->num_pages) {
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index e8ae3dc476d1..18061a4bc2f2 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -241,15 +241,15 @@ static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
241 void *ptr); 241 void *ptr);
242 242
243MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 243MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
244module_param_named(enable_fbdev, enable_fbdev, int, 0600); 244module_param_named(enable_fbdev, enable_fbdev, int, S_IRUSR | S_IWUSR);
245MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); 245MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
246module_param_named(force_dma_api, vmw_force_iommu, int, 0600); 246module_param_named(force_dma_api, vmw_force_iommu, int, S_IRUSR | S_IWUSR);
247MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 247MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
248module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 248module_param_named(restrict_iommu, vmw_restrict_iommu, int, S_IRUSR | S_IWUSR);
249MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 249MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
250module_param_named(force_coherent, vmw_force_coherent, int, 0600); 250module_param_named(force_coherent, vmw_force_coherent, int, S_IRUSR | S_IWUSR);
251MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 251MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
252module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 252module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, S_IRUSR | S_IWUSR);
253MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 253MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
254module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 254module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600);
255 255
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
index 070d750af16d..1e59a486bba8 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
@@ -43,7 +43,7 @@
43 43
44#define VMWGFX_DRIVER_DATE "20160210" 44#define VMWGFX_DRIVER_DATE "20160210"
45#define VMWGFX_DRIVER_MAJOR 2 45#define VMWGFX_DRIVER_MAJOR 2
46#define VMWGFX_DRIVER_MINOR 10 46#define VMWGFX_DRIVER_MINOR 11
47#define VMWGFX_DRIVER_PATCHLEVEL 0 47#define VMWGFX_DRIVER_PATCHLEVEL 0
48#define VMWGFX_FILE_PAGE_OFFSET 0x00100000 48#define VMWGFX_FILE_PAGE_OFFSET 0x00100000
49#define VMWGFX_FIFO_STATIC_SIZE (1024*1024) 49#define VMWGFX_FIFO_STATIC_SIZE (1024*1024)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index dc5beff2b4aa..c7b53d987f06 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -35,17 +35,37 @@
35#define VMW_RES_HT_ORDER 12 35#define VMW_RES_HT_ORDER 12
36 36
37/** 37/**
38 * enum vmw_resource_relocation_type - Relocation type for resources
39 *
40 * @vmw_res_rel_normal: Traditional relocation. The resource id in the
41 * command stream is replaced with the actual id after validation.
42 * @vmw_res_rel_nop: NOP relocation. The command is unconditionally replaced
43 * with a NOP.
44 * @vmw_res_rel_cond_nop: Conditional NOP relocation. If the resource id
45 * after validation is -1, the command is replaced with a NOP. Otherwise no
46 * action.
47 */
48enum vmw_resource_relocation_type {
49 vmw_res_rel_normal,
50 vmw_res_rel_nop,
51 vmw_res_rel_cond_nop,
52 vmw_res_rel_max
53};
54
55/**
38 * struct vmw_resource_relocation - Relocation info for resources 56 * struct vmw_resource_relocation - Relocation info for resources
39 * 57 *
40 * @head: List head for the software context's relocation list. 58 * @head: List head for the software context's relocation list.
41 * @res: Non-ref-counted pointer to the resource. 59 * @res: Non-ref-counted pointer to the resource.
42 * @offset: Offset of 4 byte entries into the command buffer where the 60 * @offset: Offset of single byte entries into the command buffer where the
43 * id that needs fixup is located. 61 * id that needs fixup is located.
62 * @rel_type: Type of relocation.
44 */ 63 */
45struct vmw_resource_relocation { 64struct vmw_resource_relocation {
46 struct list_head head; 65 struct list_head head;
47 const struct vmw_resource *res; 66 const struct vmw_resource *res;
48 unsigned long offset; 67 u32 offset:29;
68 enum vmw_resource_relocation_type rel_type:3;
49}; 69};
50 70
51/** 71/**
@@ -109,7 +129,18 @@ static int vmw_bo_to_validate_list(struct vmw_sw_context *sw_context,
109 struct vmw_dma_buffer *vbo, 129 struct vmw_dma_buffer *vbo,
110 bool validate_as_mob, 130 bool validate_as_mob,
111 uint32_t *p_val_node); 131 uint32_t *p_val_node);
112 132/**
133 * vmw_ptr_diff - Compute the offset from a to b in bytes
134 *
135 * @a: A starting pointer.
136 * @b: A pointer offset in the same address space.
137 *
138 * Returns: The offset in bytes between the two pointers.
139 */
140static size_t vmw_ptr_diff(void *a, void *b)
141{
142 return (unsigned long) b - (unsigned long) a;
143}
113 144
114/** 145/**
115 * vmw_resources_unreserve - unreserve resources previously reserved for 146 * vmw_resources_unreserve - unreserve resources previously reserved for
@@ -409,11 +440,14 @@ static int vmw_resource_context_res_add(struct vmw_private *dev_priv,
409 * @list: Pointer to head of relocation list. 440 * @list: Pointer to head of relocation list.
410 * @res: The resource. 441 * @res: The resource.
411 * @offset: Offset into the command buffer currently being parsed where the 442 * @offset: Offset into the command buffer currently being parsed where the
412 * id that needs fixup is located. Granularity is 4 bytes. 443 * id that needs fixup is located. Granularity is one byte.
444 * @rel_type: Relocation type.
413 */ 445 */
414static int vmw_resource_relocation_add(struct list_head *list, 446static int vmw_resource_relocation_add(struct list_head *list,
415 const struct vmw_resource *res, 447 const struct vmw_resource *res,
416 unsigned long offset) 448 unsigned long offset,
449 enum vmw_resource_relocation_type
450 rel_type)
417{ 451{
418 struct vmw_resource_relocation *rel; 452 struct vmw_resource_relocation *rel;
419 453
@@ -425,6 +459,7 @@ static int vmw_resource_relocation_add(struct list_head *list,
425 459
426 rel->res = res; 460 rel->res = res;
427 rel->offset = offset; 461 rel->offset = offset;
462 rel->rel_type = rel_type;
428 list_add_tail(&rel->head, list); 463 list_add_tail(&rel->head, list);
429 464
430 return 0; 465 return 0;
@@ -459,11 +494,24 @@ static void vmw_resource_relocations_apply(uint32_t *cb,
459{ 494{
460 struct vmw_resource_relocation *rel; 495 struct vmw_resource_relocation *rel;
461 496
497 /* Validate the struct vmw_resource_relocation member size */
498 BUILD_BUG_ON(SVGA_CB_MAX_SIZE >= (1 << 29));
499 BUILD_BUG_ON(vmw_res_rel_max >= (1 << 3));
500
462 list_for_each_entry(rel, list, head) { 501 list_for_each_entry(rel, list, head) {
463 if (likely(rel->res != NULL)) 502 u32 *addr = (u32 *)((unsigned long) cb + rel->offset);
464 cb[rel->offset] = rel->res->id; 503 switch (rel->rel_type) {
465 else 504 case vmw_res_rel_normal:
466 cb[rel->offset] = SVGA_3D_CMD_NOP; 505 *addr = rel->res->id;
506 break;
507 case vmw_res_rel_nop:
508 *addr = SVGA_3D_CMD_NOP;
509 break;
510 default:
511 if (rel->res->id == -1)
512 *addr = SVGA_3D_CMD_NOP;
513 break;
514 }
467 } 515 }
468} 516}
469 517
@@ -655,7 +703,9 @@ static int vmw_cmd_res_reloc_add(struct vmw_private *dev_priv,
655 *p_val = NULL; 703 *p_val = NULL;
656 ret = vmw_resource_relocation_add(&sw_context->res_relocations, 704 ret = vmw_resource_relocation_add(&sw_context->res_relocations,
657 res, 705 res,
658 id_loc - sw_context->buf_start); 706 vmw_ptr_diff(sw_context->buf_start,
707 id_loc),
708 vmw_res_rel_normal);
659 if (unlikely(ret != 0)) 709 if (unlikely(ret != 0))
660 return ret; 710 return ret;
661 711
@@ -721,7 +771,8 @@ vmw_cmd_res_check(struct vmw_private *dev_priv,
721 771
722 return vmw_resource_relocation_add 772 return vmw_resource_relocation_add
723 (&sw_context->res_relocations, res, 773 (&sw_context->res_relocations, res,
724 id_loc - sw_context->buf_start); 774 vmw_ptr_diff(sw_context->buf_start, id_loc),
775 vmw_res_rel_normal);
725 } 776 }
726 777
727 ret = vmw_user_resource_lookup_handle(dev_priv, 778 ret = vmw_user_resource_lookup_handle(dev_priv,
@@ -2143,10 +2194,10 @@ static int vmw_cmd_shader_define(struct vmw_private *dev_priv,
2143 return ret; 2194 return ret;
2144 2195
2145 return vmw_resource_relocation_add(&sw_context->res_relocations, 2196 return vmw_resource_relocation_add(&sw_context->res_relocations,
2146 NULL, &cmd->header.id - 2197 NULL,
2147 sw_context->buf_start); 2198 vmw_ptr_diff(sw_context->buf_start,
2148 2199 &cmd->header.id),
2149 return 0; 2200 vmw_res_rel_nop);
2150} 2201}
2151 2202
2152/** 2203/**
@@ -2188,10 +2239,10 @@ static int vmw_cmd_shader_destroy(struct vmw_private *dev_priv,
2188 return ret; 2239 return ret;
2189 2240
2190 return vmw_resource_relocation_add(&sw_context->res_relocations, 2241 return vmw_resource_relocation_add(&sw_context->res_relocations,
2191 NULL, &cmd->header.id - 2242 NULL,
2192 sw_context->buf_start); 2243 vmw_ptr_diff(sw_context->buf_start,
2193 2244 &cmd->header.id),
2194 return 0; 2245 vmw_res_rel_nop);
2195} 2246}
2196 2247
2197/** 2248/**
@@ -2848,8 +2899,7 @@ static int vmw_cmd_dx_cid_check(struct vmw_private *dev_priv,
2848 * @header: Pointer to the command header in the command stream. 2899 * @header: Pointer to the command header in the command stream.
2849 * 2900 *
2850 * Check that the view exists, and if it was not created using this 2901 * Check that the view exists, and if it was not created using this
2851 * command batch, make sure it's validated (present in the device) so that 2902 * command batch, conditionally make this command a NOP.
2852 * the remove command will not confuse the device.
2853 */ 2903 */
2854static int vmw_cmd_dx_view_remove(struct vmw_private *dev_priv, 2904static int vmw_cmd_dx_view_remove(struct vmw_private *dev_priv,
2855 struct vmw_sw_context *sw_context, 2905 struct vmw_sw_context *sw_context,
@@ -2877,10 +2927,16 @@ static int vmw_cmd_dx_view_remove(struct vmw_private *dev_priv,
2877 return ret; 2927 return ret;
2878 2928
2879 /* 2929 /*
2880 * Add view to the validate list iff it was not created using this 2930 * If the view wasn't created during this command batch, it might
2881 * command batch. 2931 * have been removed due to a context swapout, so add a
2932 * relocation to conditionally make this command a NOP to avoid
2933 * device errors.
2882 */ 2934 */
2883 return vmw_view_res_val_add(sw_context, view); 2935 return vmw_resource_relocation_add(&sw_context->res_relocations,
2936 view,
2937 vmw_ptr_diff(sw_context->buf_start,
2938 &cmd->header.id),
2939 vmw_res_rel_cond_nop);
2884} 2940}
2885 2941
2886/** 2942/**
@@ -3029,6 +3085,35 @@ static int vmw_cmd_dx_genmips(struct vmw_private *dev_priv,
3029 cmd->body.shaderResourceViewId); 3085 cmd->body.shaderResourceViewId);
3030} 3086}
3031 3087
3088/**
3089 * vmw_cmd_dx_transfer_from_buffer -
3090 * Validate an SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER command
3091 *
3092 * @dev_priv: Pointer to a device private struct.
3093 * @sw_context: The software context being used for this batch.
3094 * @header: Pointer to the command header in the command stream.
3095 */
3096static int vmw_cmd_dx_transfer_from_buffer(struct vmw_private *dev_priv,
3097 struct vmw_sw_context *sw_context,
3098 SVGA3dCmdHeader *header)
3099{
3100 struct {
3101 SVGA3dCmdHeader header;
3102 SVGA3dCmdDXTransferFromBuffer body;
3103 } *cmd = container_of(header, typeof(*cmd), header);
3104 int ret;
3105
3106 ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
3107 user_surface_converter,
3108 &cmd->body.srcSid, NULL);
3109 if (ret != 0)
3110 return ret;
3111
3112 return vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
3113 user_surface_converter,
3114 &cmd->body.destSid, NULL);
3115}
3116
3032static int vmw_cmd_check_not_3d(struct vmw_private *dev_priv, 3117static int vmw_cmd_check_not_3d(struct vmw_private *dev_priv,
3033 struct vmw_sw_context *sw_context, 3118 struct vmw_sw_context *sw_context,
3034 void *buf, uint32_t *size) 3119 void *buf, uint32_t *size)
@@ -3379,6 +3464,9 @@ static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = {
3379 &vmw_cmd_buffer_copy_check, true, false, true), 3464 &vmw_cmd_buffer_copy_check, true, false, true),
3380 VMW_CMD_DEF(SVGA_3D_CMD_DX_PRED_COPY_REGION, 3465 VMW_CMD_DEF(SVGA_3D_CMD_DX_PRED_COPY_REGION,
3381 &vmw_cmd_pred_copy_check, true, false, true), 3466 &vmw_cmd_pred_copy_check, true, false, true),
3467 VMW_CMD_DEF(SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER,
3468 &vmw_cmd_dx_transfer_from_buffer,
3469 true, false, true),
3382}; 3470};
3383 3471
3384static int vmw_cmd_check(struct vmw_private *dev_priv, 3472static int vmw_cmd_check(struct vmw_private *dev_priv,
@@ -3848,14 +3936,14 @@ static void *vmw_execbuf_cmdbuf(struct vmw_private *dev_priv,
3848 int ret; 3936 int ret;
3849 3937
3850 *header = NULL; 3938 *header = NULL;
3851 if (!dev_priv->cman || kernel_commands)
3852 return kernel_commands;
3853
3854 if (command_size > SVGA_CB_MAX_SIZE) { 3939 if (command_size > SVGA_CB_MAX_SIZE) {
3855 DRM_ERROR("Command buffer is too large.\n"); 3940 DRM_ERROR("Command buffer is too large.\n");
3856 return ERR_PTR(-EINVAL); 3941 return ERR_PTR(-EINVAL);
3857 } 3942 }
3858 3943
3944 if (!dev_priv->cman || kernel_commands)
3945 return kernel_commands;
3946
3859 /* If possible, add a little space for fencing. */ 3947 /* If possible, add a little space for fencing. */
3860 cmdbuf_size = command_size + 512; 3948 cmdbuf_size = command_size + 512;
3861 cmdbuf_size = min_t(size_t, cmdbuf_size, SVGA_CB_MAX_SIZE); 3949 cmdbuf_size = min_t(size_t, cmdbuf_size, SVGA_CB_MAX_SIZE);
@@ -4232,9 +4320,6 @@ void __vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv,
4232 ttm_bo_unref(&query_val.bo); 4320 ttm_bo_unref(&query_val.bo);
4233 ttm_bo_unref(&pinned_val.bo); 4321 ttm_bo_unref(&pinned_val.bo);
4234 vmw_dmabuf_unreference(&dev_priv->pinned_bo); 4322 vmw_dmabuf_unreference(&dev_priv->pinned_bo);
4235 DRM_INFO("Dummy query bo pin count: %d\n",
4236 dev_priv->dummy_query_bo->pin_count);
4237
4238out_unlock: 4323out_unlock:
4239 return; 4324 return;
4240 4325
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
index 6a328d507a28..52ca1c9d070e 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
@@ -574,10 +574,8 @@ static int vmw_user_dmabuf_synccpu_grab(struct vmw_user_dma_buffer *user_bo,
574 bool nonblock = !!(flags & drm_vmw_synccpu_dontblock); 574 bool nonblock = !!(flags & drm_vmw_synccpu_dontblock);
575 long lret; 575 long lret;
576 576
577 if (nonblock) 577 lret = reservation_object_wait_timeout_rcu(bo->resv, true, true,
578 return reservation_object_test_signaled_rcu(bo->resv, true) ? 0 : -EBUSY; 578 nonblock ? 0 : MAX_SCHEDULE_TIMEOUT);
579
580 lret = reservation_object_wait_timeout_rcu(bo->resv, true, true, MAX_SCHEDULE_TIMEOUT);
581 if (!lret) 579 if (!lret)
582 return -EBUSY; 580 return -EBUSY;
583 else if (lret < 0) 581 else if (lret < 0)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c b/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
index c2a721a8cef9..b445ce9b9757 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
@@ -324,7 +324,7 @@ static void vmw_hw_surface_destroy(struct vmw_resource *res)
324 if (res->id != -1) { 324 if (res->id != -1) {
325 325
326 cmd = vmw_fifo_reserve(dev_priv, vmw_surface_destroy_size()); 326 cmd = vmw_fifo_reserve(dev_priv, vmw_surface_destroy_size());
327 if (unlikely(cmd == NULL)) { 327 if (unlikely(!cmd)) {
328 DRM_ERROR("Failed reserving FIFO space for surface " 328 DRM_ERROR("Failed reserving FIFO space for surface "
329 "destruction.\n"); 329 "destruction.\n");
330 return; 330 return;
@@ -397,7 +397,7 @@ static int vmw_legacy_srf_create(struct vmw_resource *res)
397 397
398 submit_size = vmw_surface_define_size(srf); 398 submit_size = vmw_surface_define_size(srf);
399 cmd = vmw_fifo_reserve(dev_priv, submit_size); 399 cmd = vmw_fifo_reserve(dev_priv, submit_size);
400 if (unlikely(cmd == NULL)) { 400 if (unlikely(!cmd)) {
401 DRM_ERROR("Failed reserving FIFO space for surface " 401 DRM_ERROR("Failed reserving FIFO space for surface "
402 "creation.\n"); 402 "creation.\n");
403 ret = -ENOMEM; 403 ret = -ENOMEM;
@@ -446,11 +446,10 @@ static int vmw_legacy_srf_dma(struct vmw_resource *res,
446 uint8_t *cmd; 446 uint8_t *cmd;
447 struct vmw_private *dev_priv = res->dev_priv; 447 struct vmw_private *dev_priv = res->dev_priv;
448 448
449 BUG_ON(val_buf->bo == NULL); 449 BUG_ON(!val_buf->bo);
450
451 submit_size = vmw_surface_dma_size(srf); 450 submit_size = vmw_surface_dma_size(srf);
452 cmd = vmw_fifo_reserve(dev_priv, submit_size); 451 cmd = vmw_fifo_reserve(dev_priv, submit_size);
453 if (unlikely(cmd == NULL)) { 452 if (unlikely(!cmd)) {
454 DRM_ERROR("Failed reserving FIFO space for surface " 453 DRM_ERROR("Failed reserving FIFO space for surface "
455 "DMA.\n"); 454 "DMA.\n");
456 return -ENOMEM; 455 return -ENOMEM;
@@ -538,7 +537,7 @@ static int vmw_legacy_srf_destroy(struct vmw_resource *res)
538 537
539 submit_size = vmw_surface_destroy_size(); 538 submit_size = vmw_surface_destroy_size();
540 cmd = vmw_fifo_reserve(dev_priv, submit_size); 539 cmd = vmw_fifo_reserve(dev_priv, submit_size);
541 if (unlikely(cmd == NULL)) { 540 if (unlikely(!cmd)) {
542 DRM_ERROR("Failed reserving FIFO space for surface " 541 DRM_ERROR("Failed reserving FIFO space for surface "
543 "eviction.\n"); 542 "eviction.\n");
544 return -ENOMEM; 543 return -ENOMEM;
@@ -578,7 +577,7 @@ static int vmw_surface_init(struct vmw_private *dev_priv,
578 int ret; 577 int ret;
579 struct vmw_resource *res = &srf->res; 578 struct vmw_resource *res = &srf->res;
580 579
581 BUG_ON(res_free == NULL); 580 BUG_ON(!res_free);
582 if (!dev_priv->has_mob) 581 if (!dev_priv->has_mob)
583 vmw_fifo_resource_inc(dev_priv); 582 vmw_fifo_resource_inc(dev_priv);
584 ret = vmw_resource_init(dev_priv, res, true, res_free, 583 ret = vmw_resource_init(dev_priv, res, true, res_free,
@@ -700,7 +699,6 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
700 struct drm_vmw_surface_create_req *req = &arg->req; 699 struct drm_vmw_surface_create_req *req = &arg->req;
701 struct drm_vmw_surface_arg *rep = &arg->rep; 700 struct drm_vmw_surface_arg *rep = &arg->rep;
702 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile; 701 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
703 struct drm_vmw_size __user *user_sizes;
704 int ret; 702 int ret;
705 int i, j; 703 int i, j;
706 uint32_t cur_bo_offset; 704 uint32_t cur_bo_offset;
@@ -748,7 +746,7 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
748 } 746 }
749 747
750 user_srf = kzalloc(sizeof(*user_srf), GFP_KERNEL); 748 user_srf = kzalloc(sizeof(*user_srf), GFP_KERNEL);
751 if (unlikely(user_srf == NULL)) { 749 if (unlikely(!user_srf)) {
752 ret = -ENOMEM; 750 ret = -ENOMEM;
753 goto out_no_user_srf; 751 goto out_no_user_srf;
754 } 752 }
@@ -763,29 +761,21 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
763 memcpy(srf->mip_levels, req->mip_levels, sizeof(srf->mip_levels)); 761 memcpy(srf->mip_levels, req->mip_levels, sizeof(srf->mip_levels));
764 srf->num_sizes = num_sizes; 762 srf->num_sizes = num_sizes;
765 user_srf->size = size; 763 user_srf->size = size;
766 764 srf->sizes = memdup_user((struct drm_vmw_size __user *)(unsigned long)
767 srf->sizes = kmalloc(srf->num_sizes * sizeof(*srf->sizes), GFP_KERNEL); 765 req->size_addr,
768 if (unlikely(srf->sizes == NULL)) { 766 sizeof(*srf->sizes) * srf->num_sizes);
769 ret = -ENOMEM; 767 if (IS_ERR(srf->sizes)) {
768 ret = PTR_ERR(srf->sizes);
770 goto out_no_sizes; 769 goto out_no_sizes;
771 } 770 }
772 srf->offsets = kmalloc(srf->num_sizes * sizeof(*srf->offsets), 771 srf->offsets = kmalloc_array(srf->num_sizes,
773 GFP_KERNEL); 772 sizeof(*srf->offsets),
774 if (unlikely(srf->offsets == NULL)) { 773 GFP_KERNEL);
774 if (unlikely(!srf->offsets)) {
775 ret = -ENOMEM; 775 ret = -ENOMEM;
776 goto out_no_offsets; 776 goto out_no_offsets;
777 } 777 }
778 778
779 user_sizes = (struct drm_vmw_size __user *)(unsigned long)
780 req->size_addr;
781
782 ret = copy_from_user(srf->sizes, user_sizes,
783 srf->num_sizes * sizeof(*srf->sizes));
784 if (unlikely(ret != 0)) {
785 ret = -EFAULT;
786 goto out_no_copy;
787 }
788
789 srf->base_size = *srf->sizes; 779 srf->base_size = *srf->sizes;
790 srf->autogen_filter = SVGA3D_TEX_FILTER_NONE; 780 srf->autogen_filter = SVGA3D_TEX_FILTER_NONE;
791 srf->multisample_count = 0; 781 srf->multisample_count = 0;
@@ -923,7 +913,7 @@ vmw_surface_handle_reference(struct vmw_private *dev_priv,
923 913
924 ret = -EINVAL; 914 ret = -EINVAL;
925 base = ttm_base_object_lookup_for_ref(dev_priv->tdev, handle); 915 base = ttm_base_object_lookup_for_ref(dev_priv->tdev, handle);
926 if (unlikely(base == NULL)) { 916 if (unlikely(!base)) {
927 DRM_ERROR("Could not find surface to reference.\n"); 917 DRM_ERROR("Could not find surface to reference.\n");
928 goto out_no_lookup; 918 goto out_no_lookup;
929 } 919 }
@@ -1069,7 +1059,7 @@ static int vmw_gb_surface_create(struct vmw_resource *res)
1069 1059
1070 cmd = vmw_fifo_reserve(dev_priv, submit_len); 1060 cmd = vmw_fifo_reserve(dev_priv, submit_len);
1071 cmd2 = (typeof(cmd2))cmd; 1061 cmd2 = (typeof(cmd2))cmd;
1072 if (unlikely(cmd == NULL)) { 1062 if (unlikely(!cmd)) {
1073 DRM_ERROR("Failed reserving FIFO space for surface " 1063 DRM_ERROR("Failed reserving FIFO space for surface "
1074 "creation.\n"); 1064 "creation.\n");
1075 ret = -ENOMEM; 1065 ret = -ENOMEM;
@@ -1135,7 +1125,7 @@ static int vmw_gb_surface_bind(struct vmw_resource *res,
1135 submit_size = sizeof(*cmd1) + (res->backup_dirty ? sizeof(*cmd2) : 0); 1125 submit_size = sizeof(*cmd1) + (res->backup_dirty ? sizeof(*cmd2) : 0);
1136 1126
1137 cmd1 = vmw_fifo_reserve(dev_priv, submit_size); 1127 cmd1 = vmw_fifo_reserve(dev_priv, submit_size);
1138 if (unlikely(cmd1 == NULL)) { 1128 if (unlikely(!cmd1)) {
1139 DRM_ERROR("Failed reserving FIFO space for surface " 1129 DRM_ERROR("Failed reserving FIFO space for surface "
1140 "binding.\n"); 1130 "binding.\n");
1141 return -ENOMEM; 1131 return -ENOMEM;
@@ -1185,7 +1175,7 @@ static int vmw_gb_surface_unbind(struct vmw_resource *res,
1185 1175
1186 submit_size = sizeof(*cmd3) + (readback ? sizeof(*cmd1) : sizeof(*cmd2)); 1176 submit_size = sizeof(*cmd3) + (readback ? sizeof(*cmd1) : sizeof(*cmd2));
1187 cmd = vmw_fifo_reserve(dev_priv, submit_size); 1177 cmd = vmw_fifo_reserve(dev_priv, submit_size);
1188 if (unlikely(cmd == NULL)) { 1178 if (unlikely(!cmd)) {
1189 DRM_ERROR("Failed reserving FIFO space for surface " 1179 DRM_ERROR("Failed reserving FIFO space for surface "
1190 "unbinding.\n"); 1180 "unbinding.\n");
1191 return -ENOMEM; 1181 return -ENOMEM;
@@ -1244,7 +1234,7 @@ static int vmw_gb_surface_destroy(struct vmw_resource *res)
1244 vmw_binding_res_list_scrub(&res->binding_head); 1234 vmw_binding_res_list_scrub(&res->binding_head);
1245 1235
1246 cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd)); 1236 cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
1247 if (unlikely(cmd == NULL)) { 1237 if (unlikely(!cmd)) {
1248 DRM_ERROR("Failed reserving FIFO space for surface " 1238 DRM_ERROR("Failed reserving FIFO space for surface "
1249 "destruction.\n"); 1239 "destruction.\n");
1250 mutex_unlock(&dev_priv->binding_mutex); 1240 mutex_unlock(&dev_priv->binding_mutex);
@@ -1410,7 +1400,7 @@ int vmw_gb_surface_reference_ioctl(struct drm_device *dev, void *data,
1410 1400
1411 user_srf = container_of(base, struct vmw_user_surface, prime.base); 1401 user_srf = container_of(base, struct vmw_user_surface, prime.base);
1412 srf = &user_srf->srf; 1402 srf = &user_srf->srf;
1413 if (srf->res.backup == NULL) { 1403 if (!srf->res.backup) {
1414 DRM_ERROR("Shared GB surface is missing a backup buffer.\n"); 1404 DRM_ERROR("Shared GB surface is missing a backup buffer.\n");
1415 goto out_bad_resource; 1405 goto out_bad_resource;
1416 } 1406 }
@@ -1524,7 +1514,7 @@ int vmw_surface_gb_priv_define(struct drm_device *dev,
1524 } 1514 }
1525 1515
1526 user_srf = kzalloc(sizeof(*user_srf), GFP_KERNEL); 1516 user_srf = kzalloc(sizeof(*user_srf), GFP_KERNEL);
1527 if (unlikely(user_srf == NULL)) { 1517 if (unlikely(!user_srf)) {
1528 ret = -ENOMEM; 1518 ret = -ENOMEM;
1529 goto out_no_user_srf; 1519 goto out_no_user_srf;
1530 } 1520 }
diff --git a/drivers/hid/hid-dr.c b/drivers/hid/hid-dr.c
index 8fd4bf77f264..818ea7d93533 100644
--- a/drivers/hid/hid-dr.c
+++ b/drivers/hid/hid-dr.c
@@ -234,58 +234,6 @@ static __u8 pid0011_rdesc_fixed[] = {
234 0xC0 /* End Collection */ 234 0xC0 /* End Collection */
235}; 235};
236 236
237static __u8 pid0006_rdesc_fixed[] = {
238 0x05, 0x01, /* Usage Page (Generic Desktop) */
239 0x09, 0x04, /* Usage (Joystick) */
240 0xA1, 0x01, /* Collection (Application) */
241 0xA1, 0x02, /* Collection (Logical) */
242 0x75, 0x08, /* Report Size (8) */
243 0x95, 0x05, /* Report Count (5) */
244 0x15, 0x00, /* Logical Minimum (0) */
245 0x26, 0xFF, 0x00, /* Logical Maximum (255) */
246 0x35, 0x00, /* Physical Minimum (0) */
247 0x46, 0xFF, 0x00, /* Physical Maximum (255) */
248 0x09, 0x30, /* Usage (X) */
249 0x09, 0x33, /* Usage (Ry) */
250 0x09, 0x32, /* Usage (Z) */
251 0x09, 0x31, /* Usage (Y) */
252 0x09, 0x34, /* Usage (Ry) */
253 0x81, 0x02, /* Input (Variable) */
254 0x75, 0x04, /* Report Size (4) */
255 0x95, 0x01, /* Report Count (1) */
256 0x25, 0x07, /* Logical Maximum (7) */
257 0x46, 0x3B, 0x01, /* Physical Maximum (315) */
258 0x65, 0x14, /* Unit (Centimeter) */
259 0x09, 0x39, /* Usage (Hat switch) */
260 0x81, 0x42, /* Input (Variable) */
261 0x65, 0x00, /* Unit (None) */
262 0x75, 0x01, /* Report Size (1) */
263 0x95, 0x0C, /* Report Count (12) */
264 0x25, 0x01, /* Logical Maximum (1) */
265 0x45, 0x01, /* Physical Maximum (1) */
266 0x05, 0x09, /* Usage Page (Button) */
267 0x19, 0x01, /* Usage Minimum (0x01) */
268 0x29, 0x0C, /* Usage Maximum (0x0C) */
269 0x81, 0x02, /* Input (Variable) */
270 0x06, 0x00, 0xFF, /* Usage Page (Vendor Defined) */
271 0x75, 0x01, /* Report Size (1) */
272 0x95, 0x08, /* Report Count (8) */
273 0x25, 0x01, /* Logical Maximum (1) */
274 0x45, 0x01, /* Physical Maximum (1) */
275 0x09, 0x01, /* Usage (0x01) */
276 0x81, 0x02, /* Input (Variable) */
277 0xC0, /* End Collection */
278 0xA1, 0x02, /* Collection (Logical) */
279 0x75, 0x08, /* Report Size (8) */
280 0x95, 0x07, /* Report Count (7) */
281 0x46, 0xFF, 0x00, /* Physical Maximum (255) */
282 0x26, 0xFF, 0x00, /* Logical Maximum (255) */
283 0x09, 0x02, /* Usage (0x02) */
284 0x91, 0x02, /* Output (Variable) */
285 0xC0, /* End Collection */
286 0xC0 /* End Collection */
287};
288
289static __u8 *dr_report_fixup(struct hid_device *hdev, __u8 *rdesc, 237static __u8 *dr_report_fixup(struct hid_device *hdev, __u8 *rdesc,
290 unsigned int *rsize) 238 unsigned int *rsize)
291{ 239{
@@ -296,16 +244,34 @@ static __u8 *dr_report_fixup(struct hid_device *hdev, __u8 *rdesc,
296 *rsize = sizeof(pid0011_rdesc_fixed); 244 *rsize = sizeof(pid0011_rdesc_fixed);
297 } 245 }
298 break; 246 break;
299 case 0x0006:
300 if (*rsize == sizeof(pid0006_rdesc_fixed)) {
301 rdesc = pid0006_rdesc_fixed;
302 *rsize = sizeof(pid0006_rdesc_fixed);
303 }
304 break;
305 } 247 }
306 return rdesc; 248 return rdesc;
307} 249}
308 250
251#define map_abs(c) hid_map_usage(hi, usage, bit, max, EV_ABS, (c))
252#define map_rel(c) hid_map_usage(hi, usage, bit, max, EV_REL, (c))
253
254static int dr_input_mapping(struct hid_device *hdev, struct hid_input *hi,
255 struct hid_field *field, struct hid_usage *usage,
256 unsigned long **bit, int *max)
257{
258 switch (usage->hid) {
259 /*
260 * revert to the old hid-input behavior where axes
261 * can be randomly assigned when hid->usage is reused.
262 */
263 case HID_GD_X: case HID_GD_Y: case HID_GD_Z:
264 case HID_GD_RX: case HID_GD_RY: case HID_GD_RZ:
265 if (field->flags & HID_MAIN_ITEM_RELATIVE)
266 map_rel(usage->hid & 0xf);
267 else
268 map_abs(usage->hid & 0xf);
269 return 1;
270 }
271
272 return 0;
273}
274
309static int dr_probe(struct hid_device *hdev, const struct hid_device_id *id) 275static int dr_probe(struct hid_device *hdev, const struct hid_device_id *id)
310{ 276{
311 int ret; 277 int ret;
@@ -352,6 +318,7 @@ static struct hid_driver dr_driver = {
352 .id_table = dr_devices, 318 .id_table = dr_devices,
353 .report_fixup = dr_report_fixup, 319 .report_fixup = dr_report_fixup,
354 .probe = dr_probe, 320 .probe = dr_probe,
321 .input_mapping = dr_input_mapping,
355}; 322};
356module_hid_driver(dr_driver); 323module_hid_driver(dr_driver);
357 324
diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h
index cd59c79eebdd..6cfb5cacc253 100644
--- a/drivers/hid/hid-ids.h
+++ b/drivers/hid/hid-ids.h
@@ -64,6 +64,9 @@
64#define USB_VENDOR_ID_AKAI 0x2011 64#define USB_VENDOR_ID_AKAI 0x2011
65#define USB_DEVICE_ID_AKAI_MPKMINI2 0x0715 65#define USB_DEVICE_ID_AKAI_MPKMINI2 0x0715
66 66
67#define USB_VENDOR_ID_AKAI_09E8 0x09E8
68#define USB_DEVICE_ID_AKAI_09E8_MIDIMIX 0x0031
69
67#define USB_VENDOR_ID_ALCOR 0x058f 70#define USB_VENDOR_ID_ALCOR 0x058f
68#define USB_DEVICE_ID_ALCOR_USBRS232 0x9720 71#define USB_DEVICE_ID_ALCOR_USBRS232 0x9720
69 72
diff --git a/drivers/hid/hid-led.c b/drivers/hid/hid-led.c
index d8d55f37b4f5..d3e1ab162f7c 100644
--- a/drivers/hid/hid-led.c
+++ b/drivers/hid/hid-led.c
@@ -100,6 +100,7 @@ struct hidled_device {
100 const struct hidled_config *config; 100 const struct hidled_config *config;
101 struct hid_device *hdev; 101 struct hid_device *hdev;
102 struct hidled_rgb *rgb; 102 struct hidled_rgb *rgb;
103 u8 *buf;
103 struct mutex lock; 104 struct mutex lock;
104}; 105};
105 106
@@ -118,13 +119,19 @@ static int hidled_send(struct hidled_device *ldev, __u8 *buf)
118 119
119 mutex_lock(&ldev->lock); 120 mutex_lock(&ldev->lock);
120 121
122 /*
123 * buffer provided to hid_hw_raw_request must not be on the stack
124 * and must not be part of a data structure
125 */
126 memcpy(ldev->buf, buf, ldev->config->report_size);
127
121 if (ldev->config->report_type == RAW_REQUEST) 128 if (ldev->config->report_type == RAW_REQUEST)
122 ret = hid_hw_raw_request(ldev->hdev, buf[0], buf, 129 ret = hid_hw_raw_request(ldev->hdev, buf[0], ldev->buf,
123 ldev->config->report_size, 130 ldev->config->report_size,
124 HID_FEATURE_REPORT, 131 HID_FEATURE_REPORT,
125 HID_REQ_SET_REPORT); 132 HID_REQ_SET_REPORT);
126 else if (ldev->config->report_type == OUTPUT_REPORT) 133 else if (ldev->config->report_type == OUTPUT_REPORT)
127 ret = hid_hw_output_report(ldev->hdev, buf, 134 ret = hid_hw_output_report(ldev->hdev, ldev->buf,
128 ldev->config->report_size); 135 ldev->config->report_size);
129 else 136 else
130 ret = -EINVAL; 137 ret = -EINVAL;
@@ -147,17 +154,21 @@ static int hidled_recv(struct hidled_device *ldev, __u8 *buf)
147 154
148 mutex_lock(&ldev->lock); 155 mutex_lock(&ldev->lock);
149 156
150 ret = hid_hw_raw_request(ldev->hdev, buf[0], buf, 157 memcpy(ldev->buf, buf, ldev->config->report_size);
158
159 ret = hid_hw_raw_request(ldev->hdev, buf[0], ldev->buf,
151 ldev->config->report_size, 160 ldev->config->report_size,
152 HID_FEATURE_REPORT, 161 HID_FEATURE_REPORT,
153 HID_REQ_SET_REPORT); 162 HID_REQ_SET_REPORT);
154 if (ret < 0) 163 if (ret < 0)
155 goto err; 164 goto err;
156 165
157 ret = hid_hw_raw_request(ldev->hdev, buf[0], buf, 166 ret = hid_hw_raw_request(ldev->hdev, buf[0], ldev->buf,
158 ldev->config->report_size, 167 ldev->config->report_size,
159 HID_FEATURE_REPORT, 168 HID_FEATURE_REPORT,
160 HID_REQ_GET_REPORT); 169 HID_REQ_GET_REPORT);
170
171 memcpy(buf, ldev->buf, ldev->config->report_size);
161err: 172err:
162 mutex_unlock(&ldev->lock); 173 mutex_unlock(&ldev->lock);
163 174
@@ -447,6 +458,10 @@ static int hidled_probe(struct hid_device *hdev, const struct hid_device_id *id)
447 if (!ldev) 458 if (!ldev)
448 return -ENOMEM; 459 return -ENOMEM;
449 460
461 ldev->buf = devm_kmalloc(&hdev->dev, MAX_REPORT_SIZE, GFP_KERNEL);
462 if (!ldev->buf)
463 return -ENOMEM;
464
450 ret = hid_parse(hdev); 465 ret = hid_parse(hdev);
451 if (ret) 466 if (ret)
452 return ret; 467 return ret;
diff --git a/drivers/hid/usbhid/hid-quirks.c b/drivers/hid/usbhid/hid-quirks.c
index 0a0eca5da47d..354d49ea36dd 100644
--- a/drivers/hid/usbhid/hid-quirks.c
+++ b/drivers/hid/usbhid/hid-quirks.c
@@ -56,6 +56,7 @@ static const struct hid_blacklist {
56 56
57 { USB_VENDOR_ID_AIREN, USB_DEVICE_ID_AIREN_SLIMPLUS, HID_QUIRK_NOGET }, 57 { USB_VENDOR_ID_AIREN, USB_DEVICE_ID_AIREN_SLIMPLUS, HID_QUIRK_NOGET },
58 { USB_VENDOR_ID_AKAI, USB_DEVICE_ID_AKAI_MPKMINI2, HID_QUIRK_NO_INIT_REPORTS }, 58 { USB_VENDOR_ID_AKAI, USB_DEVICE_ID_AKAI_MPKMINI2, HID_QUIRK_NO_INIT_REPORTS },
59 { USB_VENDOR_ID_AKAI_09E8, USB_DEVICE_ID_AKAI_09E8_MIDIMIX, HID_QUIRK_NO_INIT_REPORTS },
59 { USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_UC100KM, HID_QUIRK_NOGET }, 60 { USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_UC100KM, HID_QUIRK_NOGET },
60 { USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_CS124U, HID_QUIRK_NOGET }, 61 { USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_CS124U, HID_QUIRK_NOGET },
61 { USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_2PORTKVM, HID_QUIRK_NOGET }, 62 { USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_2PORTKVM, HID_QUIRK_NOGET },
diff --git a/drivers/hwmon/adm9240.c b/drivers/hwmon/adm9240.c
index 98114cef1e43..2fe1828bd10b 100644
--- a/drivers/hwmon/adm9240.c
+++ b/drivers/hwmon/adm9240.c
@@ -194,10 +194,10 @@ static struct adm9240_data *adm9240_update_device(struct device *dev)
194 * 0.5'C per two measurement cycles thus ignore possible 194 * 0.5'C per two measurement cycles thus ignore possible
195 * but unlikely aliasing error on lsb reading. --Grant 195 * but unlikely aliasing error on lsb reading. --Grant
196 */ 196 */
197 data->temp = ((i2c_smbus_read_byte_data(client, 197 data->temp = (i2c_smbus_read_byte_data(client,
198 ADM9240_REG_TEMP) << 8) | 198 ADM9240_REG_TEMP) << 8) |
199 i2c_smbus_read_byte_data(client, 199 i2c_smbus_read_byte_data(client,
200 ADM9240_REG_TEMP_CONF)) / 128; 200 ADM9240_REG_TEMP_CONF);
201 201
202 for (i = 0; i < 2; i++) { /* read fans */ 202 for (i = 0; i < 2; i++) { /* read fans */
203 data->fan[i] = i2c_smbus_read_byte_data(client, 203 data->fan[i] = i2c_smbus_read_byte_data(client,
@@ -263,7 +263,7 @@ static ssize_t show_temp(struct device *dev, struct device_attribute *dummy,
263 char *buf) 263 char *buf)
264{ 264{
265 struct adm9240_data *data = adm9240_update_device(dev); 265 struct adm9240_data *data = adm9240_update_device(dev);
266 return sprintf(buf, "%d\n", data->temp * 500); /* 9-bit value */ 266 return sprintf(buf, "%d\n", data->temp / 128 * 500); /* 9-bit value */
267} 267}
268 268
269static ssize_t show_max(struct device *dev, struct device_attribute *devattr, 269static ssize_t show_max(struct device *dev, struct device_attribute *devattr,
diff --git a/drivers/hwmon/max31790.c b/drivers/hwmon/max31790.c
index bef84e085973..c1b9275978f9 100644
--- a/drivers/hwmon/max31790.c
+++ b/drivers/hwmon/max31790.c
@@ -268,11 +268,13 @@ static int max31790_read_pwm(struct device *dev, u32 attr, int channel,
268 long *val) 268 long *val)
269{ 269{
270 struct max31790_data *data = max31790_update_device(dev); 270 struct max31790_data *data = max31790_update_device(dev);
271 u8 fan_config = data->fan_config[channel]; 271 u8 fan_config;
272 272
273 if (IS_ERR(data)) 273 if (IS_ERR(data))
274 return PTR_ERR(data); 274 return PTR_ERR(data);
275 275
276 fan_config = data->fan_config[channel];
277
276 switch (attr) { 278 switch (attr) {
277 case hwmon_pwm_input: 279 case hwmon_pwm_input:
278 *val = data->pwm[channel] >> 8; 280 *val = data->pwm[channel] >> 8;
diff --git a/drivers/infiniband/core/umem.c b/drivers/infiniband/core/umem.c
index c68746ce6624..224ad274ea0b 100644
--- a/drivers/infiniband/core/umem.c
+++ b/drivers/infiniband/core/umem.c
@@ -94,6 +94,7 @@ struct ib_umem *ib_umem_get(struct ib_ucontext *context, unsigned long addr,
94 unsigned long dma_attrs = 0; 94 unsigned long dma_attrs = 0;
95 struct scatterlist *sg, *sg_list_start; 95 struct scatterlist *sg, *sg_list_start;
96 int need_release = 0; 96 int need_release = 0;
97 unsigned int gup_flags = FOLL_WRITE;
97 98
98 if (dmasync) 99 if (dmasync)
99 dma_attrs |= DMA_ATTR_WRITE_BARRIER; 100 dma_attrs |= DMA_ATTR_WRITE_BARRIER;
@@ -183,6 +184,9 @@ struct ib_umem *ib_umem_get(struct ib_ucontext *context, unsigned long addr,
183 if (ret) 184 if (ret)
184 goto out; 185 goto out;
185 186
187 if (!umem->writable)
188 gup_flags |= FOLL_FORCE;
189
186 need_release = 1; 190 need_release = 1;
187 sg_list_start = umem->sg_head.sgl; 191 sg_list_start = umem->sg_head.sgl;
188 192
@@ -190,7 +194,7 @@ struct ib_umem *ib_umem_get(struct ib_ucontext *context, unsigned long addr,
190 ret = get_user_pages(cur_base, 194 ret = get_user_pages(cur_base,
191 min_t(unsigned long, npages, 195 min_t(unsigned long, npages,
192 PAGE_SIZE / sizeof (struct page *)), 196 PAGE_SIZE / sizeof (struct page *)),
193 1, !umem->writable, page_list, vma_list); 197 gup_flags, page_list, vma_list);
194 198
195 if (ret < 0) 199 if (ret < 0)
196 goto out; 200 goto out;
diff --git a/drivers/infiniband/core/umem_odp.c b/drivers/infiniband/core/umem_odp.c
index 75077a018675..1f0fe3217f23 100644
--- a/drivers/infiniband/core/umem_odp.c
+++ b/drivers/infiniband/core/umem_odp.c
@@ -527,6 +527,7 @@ int ib_umem_odp_map_dma_pages(struct ib_umem *umem, u64 user_virt, u64 bcnt,
527 u64 off; 527 u64 off;
528 int j, k, ret = 0, start_idx, npages = 0; 528 int j, k, ret = 0, start_idx, npages = 0;
529 u64 base_virt_addr; 529 u64 base_virt_addr;
530 unsigned int flags = 0;
530 531
531 if (access_mask == 0) 532 if (access_mask == 0)
532 return -EINVAL; 533 return -EINVAL;
@@ -556,6 +557,9 @@ int ib_umem_odp_map_dma_pages(struct ib_umem *umem, u64 user_virt, u64 bcnt,
556 goto out_put_task; 557 goto out_put_task;
557 } 558 }
558 559
560 if (access_mask & ODP_WRITE_ALLOWED_BIT)
561 flags |= FOLL_WRITE;
562
559 start_idx = (user_virt - ib_umem_start(umem)) >> PAGE_SHIFT; 563 start_idx = (user_virt - ib_umem_start(umem)) >> PAGE_SHIFT;
560 k = start_idx; 564 k = start_idx;
561 565
@@ -574,8 +578,7 @@ int ib_umem_odp_map_dma_pages(struct ib_umem *umem, u64 user_virt, u64 bcnt,
574 */ 578 */
575 npages = get_user_pages_remote(owning_process, owning_mm, 579 npages = get_user_pages_remote(owning_process, owning_mm,
576 user_virt, gup_num_pages, 580 user_virt, gup_num_pages,
577 access_mask & ODP_WRITE_ALLOWED_BIT, 581 flags, local_page_list, NULL);
578 0, local_page_list, NULL);
579 up_read(&owning_mm->mmap_sem); 582 up_read(&owning_mm->mmap_sem);
580 583
581 if (npages < 0) 584 if (npages < 0)
diff --git a/drivers/infiniband/hw/mthca/mthca_memfree.c b/drivers/infiniband/hw/mthca/mthca_memfree.c
index 6c00d04b8b28..c6fe89d79248 100644
--- a/drivers/infiniband/hw/mthca/mthca_memfree.c
+++ b/drivers/infiniband/hw/mthca/mthca_memfree.c
@@ -472,7 +472,7 @@ int mthca_map_user_db(struct mthca_dev *dev, struct mthca_uar *uar,
472 goto out; 472 goto out;
473 } 473 }
474 474
475 ret = get_user_pages(uaddr & PAGE_MASK, 1, 1, 0, pages, NULL); 475 ret = get_user_pages(uaddr & PAGE_MASK, 1, FOLL_WRITE, pages, NULL);
476 if (ret < 0) 476 if (ret < 0)
477 goto out; 477 goto out;
478 478
diff --git a/drivers/infiniband/hw/qib/qib_user_pages.c b/drivers/infiniband/hw/qib/qib_user_pages.c
index 2d2b94fd3633..75f08624ac05 100644
--- a/drivers/infiniband/hw/qib/qib_user_pages.c
+++ b/drivers/infiniband/hw/qib/qib_user_pages.c
@@ -67,7 +67,8 @@ static int __qib_get_user_pages(unsigned long start_page, size_t num_pages,
67 67
68 for (got = 0; got < num_pages; got += ret) { 68 for (got = 0; got < num_pages; got += ret) {
69 ret = get_user_pages(start_page + got * PAGE_SIZE, 69 ret = get_user_pages(start_page + got * PAGE_SIZE,
70 num_pages - got, 1, 1, 70 num_pages - got,
71 FOLL_WRITE | FOLL_FORCE,
71 p + got, NULL); 72 p + got, NULL);
72 if (ret < 0) 73 if (ret < 0)
73 goto bail_release; 74 goto bail_release;
diff --git a/drivers/infiniband/hw/usnic/usnic_uiom.c b/drivers/infiniband/hw/usnic/usnic_uiom.c
index a0b6ebee4d8a..1ccee6ea5bc3 100644
--- a/drivers/infiniband/hw/usnic/usnic_uiom.c
+++ b/drivers/infiniband/hw/usnic/usnic_uiom.c
@@ -111,6 +111,7 @@ static int usnic_uiom_get_pages(unsigned long addr, size_t size, int writable,
111 int i; 111 int i;
112 int flags; 112 int flags;
113 dma_addr_t pa; 113 dma_addr_t pa;
114 unsigned int gup_flags;
114 115
115 if (!can_do_mlock()) 116 if (!can_do_mlock())
116 return -EPERM; 117 return -EPERM;
@@ -135,6 +136,8 @@ static int usnic_uiom_get_pages(unsigned long addr, size_t size, int writable,
135 136
136 flags = IOMMU_READ | IOMMU_CACHE; 137 flags = IOMMU_READ | IOMMU_CACHE;
137 flags |= (writable) ? IOMMU_WRITE : 0; 138 flags |= (writable) ? IOMMU_WRITE : 0;
139 gup_flags = FOLL_WRITE;
140 gup_flags |= (writable) ? 0 : FOLL_FORCE;
138 cur_base = addr & PAGE_MASK; 141 cur_base = addr & PAGE_MASK;
139 ret = 0; 142 ret = 0;
140 143
@@ -142,7 +145,7 @@ static int usnic_uiom_get_pages(unsigned long addr, size_t size, int writable,
142 ret = get_user_pages(cur_base, 145 ret = get_user_pages(cur_base,
143 min_t(unsigned long, npages, 146 min_t(unsigned long, npages,
144 PAGE_SIZE / sizeof(struct page *)), 147 PAGE_SIZE / sizeof(struct page *)),
145 1, !writable, page_list, NULL); 148 gup_flags, page_list, NULL);
146 149
147 if (ret < 0) 150 if (ret < 0)
148 goto out; 151 goto out;
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 82b0b5daf3f5..bc0af3307bbf 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -158,8 +158,8 @@ config PIC32_EVIC
158 select IRQ_DOMAIN 158 select IRQ_DOMAIN
159 159
160config JCORE_AIC 160config JCORE_AIC
161 bool "J-Core integrated AIC" 161 bool "J-Core integrated AIC" if COMPILE_TEST
162 depends on OF && (SUPERH || COMPILE_TEST) 162 depends on OF
163 select IRQ_DOMAIN 163 select IRQ_DOMAIN
164 help 164 help
165 Support for the J-Core integrated AIC. 165 Support for the J-Core integrated AIC.
diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
index efbf0e4304b7..2a7a38830a8d 100644
--- a/drivers/irqchip/irq-eznps.c
+++ b/drivers/irqchip/irq-eznps.c
@@ -85,7 +85,7 @@ static void nps400_irq_eoi_global(struct irq_data *irqd)
85 nps_ack_gic(); 85 nps_ack_gic();
86} 86}
87 87
88static void nps400_irq_eoi(struct irq_data *irqd) 88static void nps400_irq_ack(struct irq_data *irqd)
89{ 89{
90 unsigned int __maybe_unused irq = irqd_to_hwirq(irqd); 90 unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
91 91
@@ -103,7 +103,7 @@ static struct irq_chip nps400_irq_chip_percpu = {
103 .name = "NPS400 IC", 103 .name = "NPS400 IC",
104 .irq_mask = nps400_irq_mask, 104 .irq_mask = nps400_irq_mask,
105 .irq_unmask = nps400_irq_unmask, 105 .irq_unmask = nps400_irq_unmask,
106 .irq_eoi = nps400_irq_eoi, 106 .irq_ack = nps400_irq_ack,
107}; 107};
108 108
109static int nps400_irq_map(struct irq_domain *d, unsigned int virq, 109static int nps400_irq_map(struct irq_domain *d, unsigned int virq,
@@ -135,7 +135,7 @@ static const struct irq_domain_ops nps400_irq_ops = {
135static int __init nps400_of_init(struct device_node *node, 135static int __init nps400_of_init(struct device_node *node,
136 struct device_node *parent) 136 struct device_node *parent)
137{ 137{
138 static struct irq_domain *nps400_root_domain; 138 struct irq_domain *nps400_root_domain;
139 139
140 if (parent) { 140 if (parent) {
141 pr_err("DeviceTree incore ic not a root irq controller\n"); 141 pr_err("DeviceTree incore ic not a root irq controller\n");
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 003495d91f9c..c5dee300e8a3 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1023,7 +1023,7 @@ static void its_free_tables(struct its_node *its)
1023 1023
1024static int its_alloc_tables(struct its_node *its) 1024static int its_alloc_tables(struct its_node *its)
1025{ 1025{
1026 u64 typer = readq_relaxed(its->base + GITS_TYPER); 1026 u64 typer = gic_read_typer(its->base + GITS_TYPER);
1027 u32 ids = GITS_TYPER_DEVBITS(typer); 1027 u32 ids = GITS_TYPER_DEVBITS(typer);
1028 u64 shr = GITS_BASER_InnerShareable; 1028 u64 shr = GITS_BASER_InnerShareable;
1029 u64 cache = GITS_BASER_WaWb; 1029 u64 cache = GITS_BASER_WaWb;
@@ -1198,7 +1198,7 @@ static void its_cpu_init_collection(void)
1198 * We now have to bind each collection to its target 1198 * We now have to bind each collection to its target
1199 * redistributor. 1199 * redistributor.
1200 */ 1200 */
1201 if (readq_relaxed(its->base + GITS_TYPER) & GITS_TYPER_PTA) { 1201 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
1202 /* 1202 /*
1203 * This ITS wants the physical address of the 1203 * This ITS wants the physical address of the
1204 * redistributor. 1204 * redistributor.
@@ -1208,7 +1208,7 @@ static void its_cpu_init_collection(void)
1208 /* 1208 /*
1209 * This ITS wants a linear CPU number. 1209 * This ITS wants a linear CPU number.
1210 */ 1210 */
1211 target = readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER); 1211 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
1212 target = GICR_TYPER_CPU_NUMBER(target) << 16; 1212 target = GICR_TYPER_CPU_NUMBER(target) << 16;
1213 } 1213 }
1214 1214
@@ -1691,7 +1691,7 @@ static int __init its_probe_one(struct resource *res,
1691 INIT_LIST_HEAD(&its->its_device_list); 1691 INIT_LIST_HEAD(&its->its_device_list);
1692 its->base = its_base; 1692 its->base = its_base;
1693 its->phys_base = res->start; 1693 its->phys_base = res->start;
1694 its->ite_size = ((readl_relaxed(its_base + GITS_TYPER) >> 4) & 0xf) + 1; 1694 its->ite_size = ((gic_read_typer(its_base + GITS_TYPER) >> 4) & 0xf) + 1;
1695 its->numa_node = numa_node; 1695 its->numa_node = numa_node;
1696 1696
1697 its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL); 1697 its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL);
@@ -1763,7 +1763,7 @@ out_unmap:
1763 1763
1764static bool gic_rdists_supports_plpis(void) 1764static bool gic_rdists_supports_plpis(void)
1765{ 1765{
1766 return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); 1766 return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
1767} 1767}
1768 1768
1769int its_cpu_init(void) 1769int its_cpu_init(void)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 9b81bd8b929c..19d642eae096 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -153,7 +153,7 @@ static void gic_enable_redist(bool enable)
153 return; /* No PM support in this redistributor */ 153 return; /* No PM support in this redistributor */
154 } 154 }
155 155
156 while (count--) { 156 while (--count) {
157 val = readl_relaxed(rbase + GICR_WAKER); 157 val = readl_relaxed(rbase + GICR_WAKER);
158 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) 158 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep))
159 break; 159 break;
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 58e5b4e87056..d6c404b3584d 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -1279,7 +1279,7 @@ static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1279 */ 1279 */
1280 *base += 0xf000; 1280 *base += 0xf000;
1281 cpuif_res.start += 0xf000; 1281 cpuif_res.start += 0xf000;
1282 pr_warn("GIC: Adjusting CPU interface base to %pa", 1282 pr_warn("GIC: Adjusting CPU interface base to %pa\n",
1283 &cpuif_res.start); 1283 &cpuif_res.start);
1284 } 1284 }
1285 1285
diff --git a/drivers/irqchip/irq-jcore-aic.c b/drivers/irqchip/irq-jcore-aic.c
index 84b01dec277d..033bccb41455 100644
--- a/drivers/irqchip/irq-jcore-aic.c
+++ b/drivers/irqchip/irq-jcore-aic.c
@@ -25,12 +25,30 @@
25 25
26static struct irq_chip jcore_aic; 26static struct irq_chip jcore_aic;
27 27
28/*
29 * The J-Core AIC1 and AIC2 are cpu-local interrupt controllers and do
30 * not distinguish or use distinct irq number ranges for per-cpu event
31 * interrupts (timer, IPI). Since information to determine whether a
32 * particular irq number should be treated as per-cpu is not available
33 * at mapping time, we use a wrapper handler function which chooses
34 * the right handler at runtime based on whether IRQF_PERCPU was used
35 * when requesting the irq.
36 */
37
38static void handle_jcore_irq(struct irq_desc *desc)
39{
40 if (irqd_is_per_cpu(irq_desc_get_irq_data(desc)))
41 handle_percpu_irq(desc);
42 else
43 handle_simple_irq(desc);
44}
45
28static int jcore_aic_irqdomain_map(struct irq_domain *d, unsigned int irq, 46static int jcore_aic_irqdomain_map(struct irq_domain *d, unsigned int irq,
29 irq_hw_number_t hwirq) 47 irq_hw_number_t hwirq)
30{ 48{
31 struct irq_chip *aic = d->host_data; 49 struct irq_chip *aic = d->host_data;
32 50
33 irq_set_chip_and_handler(irq, aic, handle_simple_irq); 51 irq_set_chip_and_handler(irq, aic, handle_jcore_irq);
34 52
35 return 0; 53 return 0;
36} 54}
diff --git a/drivers/media/pci/ivtv/ivtv-udma.c b/drivers/media/pci/ivtv/ivtv-udma.c
index 4769469fe842..2c9232ef7baa 100644
--- a/drivers/media/pci/ivtv/ivtv-udma.c
+++ b/drivers/media/pci/ivtv/ivtv-udma.c
@@ -124,8 +124,8 @@ int ivtv_udma_setup(struct ivtv *itv, unsigned long ivtv_dest_addr,
124 } 124 }
125 125
126 /* Get user pages for DMA Xfer */ 126 /* Get user pages for DMA Xfer */
127 err = get_user_pages_unlocked(user_dma.uaddr, user_dma.page_count, 0, 127 err = get_user_pages_unlocked(user_dma.uaddr, user_dma.page_count,
128 1, dma->map); 128 dma->map, FOLL_FORCE);
129 129
130 if (user_dma.page_count != err) { 130 if (user_dma.page_count != err) {
131 IVTV_DEBUG_WARN("failed to map user pages, returned %d instead of %d\n", 131 IVTV_DEBUG_WARN("failed to map user pages, returned %d instead of %d\n",
diff --git a/drivers/media/pci/ivtv/ivtv-yuv.c b/drivers/media/pci/ivtv/ivtv-yuv.c
index b094054cda6e..f7299d3d8244 100644
--- a/drivers/media/pci/ivtv/ivtv-yuv.c
+++ b/drivers/media/pci/ivtv/ivtv-yuv.c
@@ -76,11 +76,12 @@ static int ivtv_yuv_prep_user_dma(struct ivtv *itv, struct ivtv_user_dma *dma,
76 76
77 /* Get user pages for DMA Xfer */ 77 /* Get user pages for DMA Xfer */
78 y_pages = get_user_pages_unlocked(y_dma.uaddr, 78 y_pages = get_user_pages_unlocked(y_dma.uaddr,
79 y_dma.page_count, 0, 1, &dma->map[0]); 79 y_dma.page_count, &dma->map[0], FOLL_FORCE);
80 uv_pages = 0; /* silence gcc. value is set and consumed only if: */ 80 uv_pages = 0; /* silence gcc. value is set and consumed only if: */
81 if (y_pages == y_dma.page_count) { 81 if (y_pages == y_dma.page_count) {
82 uv_pages = get_user_pages_unlocked(uv_dma.uaddr, 82 uv_pages = get_user_pages_unlocked(uv_dma.uaddr,
83 uv_dma.page_count, 0, 1, &dma->map[y_pages]); 83 uv_dma.page_count, &dma->map[y_pages],
84 FOLL_FORCE);
84 } 85 }
85 86
86 if (y_pages != y_dma.page_count || uv_pages != uv_dma.page_count) { 87 if (y_pages != y_dma.page_count || uv_pages != uv_dma.page_count) {
diff --git a/drivers/media/platform/omap/omap_vout.c b/drivers/media/platform/omap/omap_vout.c
index e668dde6d857..a31b95cb3b09 100644
--- a/drivers/media/platform/omap/omap_vout.c
+++ b/drivers/media/platform/omap/omap_vout.c
@@ -214,7 +214,7 @@ static int omap_vout_get_userptr(struct videobuf_buffer *vb, u32 virtp,
214 if (!vec) 214 if (!vec)
215 return -ENOMEM; 215 return -ENOMEM;
216 216
217 ret = get_vaddr_frames(virtp, 1, true, false, vec); 217 ret = get_vaddr_frames(virtp, 1, FOLL_WRITE, vec);
218 if (ret != 1) { 218 if (ret != 1) {
219 frame_vector_destroy(vec); 219 frame_vector_destroy(vec);
220 return -EINVAL; 220 return -EINVAL;
diff --git a/drivers/media/v4l2-core/videobuf-dma-sg.c b/drivers/media/v4l2-core/videobuf-dma-sg.c
index f300f060b3f3..1db0af6c7f94 100644
--- a/drivers/media/v4l2-core/videobuf-dma-sg.c
+++ b/drivers/media/v4l2-core/videobuf-dma-sg.c
@@ -156,6 +156,7 @@ static int videobuf_dma_init_user_locked(struct videobuf_dmabuf *dma,
156{ 156{
157 unsigned long first, last; 157 unsigned long first, last;
158 int err, rw = 0; 158 int err, rw = 0;
159 unsigned int flags = FOLL_FORCE;
159 160
160 dma->direction = direction; 161 dma->direction = direction;
161 switch (dma->direction) { 162 switch (dma->direction) {
@@ -178,12 +179,14 @@ static int videobuf_dma_init_user_locked(struct videobuf_dmabuf *dma,
178 if (NULL == dma->pages) 179 if (NULL == dma->pages)
179 return -ENOMEM; 180 return -ENOMEM;
180 181
182 if (rw == READ)
183 flags |= FOLL_WRITE;
184
181 dprintk(1, "init user [0x%lx+0x%lx => %d pages]\n", 185 dprintk(1, "init user [0x%lx+0x%lx => %d pages]\n",
182 data, size, dma->nr_pages); 186 data, size, dma->nr_pages);
183 187
184 err = get_user_pages(data & PAGE_MASK, dma->nr_pages, 188 err = get_user_pages(data & PAGE_MASK, dma->nr_pages,
185 rw == READ, 1, /* force */ 189 flags, dma->pages, NULL);
186 dma->pages, NULL);
187 190
188 if (err != dma->nr_pages) { 191 if (err != dma->nr_pages) {
189 dma->nr_pages = (err >= 0) ? err : 0; 192 dma->nr_pages = (err >= 0) ? err : 0;
diff --git a/drivers/media/v4l2-core/videobuf2-memops.c b/drivers/media/v4l2-core/videobuf2-memops.c
index 3c3b517f1d1c..1cd322e939c7 100644
--- a/drivers/media/v4l2-core/videobuf2-memops.c
+++ b/drivers/media/v4l2-core/videobuf2-memops.c
@@ -42,6 +42,10 @@ struct frame_vector *vb2_create_framevec(unsigned long start,
42 unsigned long first, last; 42 unsigned long first, last;
43 unsigned long nr; 43 unsigned long nr;
44 struct frame_vector *vec; 44 struct frame_vector *vec;
45 unsigned int flags = FOLL_FORCE;
46
47 if (write)
48 flags |= FOLL_WRITE;
45 49
46 first = start >> PAGE_SHIFT; 50 first = start >> PAGE_SHIFT;
47 last = (start + length - 1) >> PAGE_SHIFT; 51 last = (start + length - 1) >> PAGE_SHIFT;
@@ -49,7 +53,7 @@ struct frame_vector *vb2_create_framevec(unsigned long start,
49 vec = frame_vector_create(nr); 53 vec = frame_vector_create(nr);
50 if (!vec) 54 if (!vec)
51 return ERR_PTR(-ENOMEM); 55 return ERR_PTR(-ENOMEM);
52 ret = get_vaddr_frames(start & PAGE_MASK, nr, write, true, vec); 56 ret = get_vaddr_frames(start & PAGE_MASK, nr, flags, vec);
53 if (ret < 0) 57 if (ret < 0)
54 goto out_destroy; 58 goto out_destroy;
55 /* We accept only complete set of PFNs */ 59 /* We accept only complete set of PFNs */
diff --git a/drivers/memstick/host/rtsx_usb_ms.c b/drivers/memstick/host/rtsx_usb_ms.c
index d34bc3530385..2e3cf012ef48 100644
--- a/drivers/memstick/host/rtsx_usb_ms.c
+++ b/drivers/memstick/host/rtsx_usb_ms.c
@@ -524,6 +524,7 @@ static void rtsx_usb_ms_handle_req(struct work_struct *work)
524 int rc; 524 int rc;
525 525
526 if (!host->req) { 526 if (!host->req) {
527 pm_runtime_get_sync(ms_dev(host));
527 do { 528 do {
528 rc = memstick_next_req(msh, &host->req); 529 rc = memstick_next_req(msh, &host->req);
529 dev_dbg(ms_dev(host), "next req %d\n", rc); 530 dev_dbg(ms_dev(host), "next req %d\n", rc);
@@ -544,6 +545,7 @@ static void rtsx_usb_ms_handle_req(struct work_struct *work)
544 host->req->error); 545 host->req->error);
545 } 546 }
546 } while (!rc); 547 } while (!rc);
548 pm_runtime_put(ms_dev(host));
547 } 549 }
548 550
549} 551}
@@ -570,6 +572,7 @@ static int rtsx_usb_ms_set_param(struct memstick_host *msh,
570 dev_dbg(ms_dev(host), "%s: param = %d, value = %d\n", 572 dev_dbg(ms_dev(host), "%s: param = %d, value = %d\n",
571 __func__, param, value); 573 __func__, param, value);
572 574
575 pm_runtime_get_sync(ms_dev(host));
573 mutex_lock(&ucr->dev_mutex); 576 mutex_lock(&ucr->dev_mutex);
574 577
575 err = rtsx_usb_card_exclusive_check(ucr, RTSX_USB_MS_CARD); 578 err = rtsx_usb_card_exclusive_check(ucr, RTSX_USB_MS_CARD);
@@ -635,6 +638,7 @@ static int rtsx_usb_ms_set_param(struct memstick_host *msh,
635 } 638 }
636out: 639out:
637 mutex_unlock(&ucr->dev_mutex); 640 mutex_unlock(&ucr->dev_mutex);
641 pm_runtime_put(ms_dev(host));
638 642
639 /* power-on delay */ 643 /* power-on delay */
640 if (param == MEMSTICK_POWER && value == MEMSTICK_POWER_ON) 644 if (param == MEMSTICK_POWER && value == MEMSTICK_POWER_ON)
@@ -681,6 +685,7 @@ static int rtsx_usb_detect_ms_card(void *__host)
681 int err; 685 int err;
682 686
683 for (;;) { 687 for (;;) {
688 pm_runtime_get_sync(ms_dev(host));
684 mutex_lock(&ucr->dev_mutex); 689 mutex_lock(&ucr->dev_mutex);
685 690
686 /* Check pending MS card changes */ 691 /* Check pending MS card changes */
@@ -703,6 +708,7 @@ static int rtsx_usb_detect_ms_card(void *__host)
703 } 708 }
704 709
705poll_again: 710poll_again:
711 pm_runtime_put(ms_dev(host));
706 if (host->eject) 712 if (host->eject)
707 break; 713 break;
708 714
diff --git a/drivers/misc/cxl/api.c b/drivers/misc/cxl/api.c
index f3d34b941f85..af23d7dfe752 100644
--- a/drivers/misc/cxl/api.c
+++ b/drivers/misc/cxl/api.c
@@ -229,6 +229,14 @@ int cxl_start_context(struct cxl_context *ctx, u64 wed,
229 if (ctx->status == STARTED) 229 if (ctx->status == STARTED)
230 goto out; /* already started */ 230 goto out; /* already started */
231 231
232 /*
233 * Increment the mapped context count for adapter. This also checks
234 * if adapter_context_lock is taken.
235 */
236 rc = cxl_adapter_context_get(ctx->afu->adapter);
237 if (rc)
238 goto out;
239
232 if (task) { 240 if (task) {
233 ctx->pid = get_task_pid(task, PIDTYPE_PID); 241 ctx->pid = get_task_pid(task, PIDTYPE_PID);
234 ctx->glpid = get_task_pid(task->group_leader, PIDTYPE_PID); 242 ctx->glpid = get_task_pid(task->group_leader, PIDTYPE_PID);
@@ -240,6 +248,7 @@ int cxl_start_context(struct cxl_context *ctx, u64 wed,
240 248
241 if ((rc = cxl_ops->attach_process(ctx, kernel, wed, 0))) { 249 if ((rc = cxl_ops->attach_process(ctx, kernel, wed, 0))) {
242 put_pid(ctx->pid); 250 put_pid(ctx->pid);
251 cxl_adapter_context_put(ctx->afu->adapter);
243 cxl_ctx_put(); 252 cxl_ctx_put();
244 goto out; 253 goto out;
245 } 254 }
diff --git a/drivers/misc/cxl/context.c b/drivers/misc/cxl/context.c
index c466ee2b0c97..5e506c19108a 100644
--- a/drivers/misc/cxl/context.c
+++ b/drivers/misc/cxl/context.c
@@ -238,6 +238,9 @@ int __detach_context(struct cxl_context *ctx)
238 put_pid(ctx->glpid); 238 put_pid(ctx->glpid);
239 239
240 cxl_ctx_put(); 240 cxl_ctx_put();
241
242 /* Decrease the attached context count on the adapter */
243 cxl_adapter_context_put(ctx->afu->adapter);
241 return 0; 244 return 0;
242} 245}
243 246
diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h
index 01d372aba131..a144073593fa 100644
--- a/drivers/misc/cxl/cxl.h
+++ b/drivers/misc/cxl/cxl.h
@@ -618,6 +618,14 @@ struct cxl {
618 bool perst_select_user; 618 bool perst_select_user;
619 bool perst_same_image; 619 bool perst_same_image;
620 bool psl_timebase_synced; 620 bool psl_timebase_synced;
621
622 /*
623 * number of contexts mapped on to this card. Possible values are:
624 * >0: Number of contexts mapped and new one can be mapped.
625 * 0: No active contexts and new ones can be mapped.
626 * -1: No contexts mapped and new ones cannot be mapped.
627 */
628 atomic_t contexts_num;
621}; 629};
622 630
623int cxl_pci_alloc_one_irq(struct cxl *adapter); 631int cxl_pci_alloc_one_irq(struct cxl *adapter);
@@ -944,4 +952,20 @@ bool cxl_pci_is_vphb_device(struct pci_dev *dev);
944 952
945/* decode AFU error bits in the PSL register PSL_SERR_An */ 953/* decode AFU error bits in the PSL register PSL_SERR_An */
946void cxl_afu_decode_psl_serr(struct cxl_afu *afu, u64 serr); 954void cxl_afu_decode_psl_serr(struct cxl_afu *afu, u64 serr);
955
956/*
957 * Increments the number of attached contexts on an adapter.
958 * In case an adapter_context_lock is taken the return -EBUSY.
959 */
960int cxl_adapter_context_get(struct cxl *adapter);
961
962/* Decrements the number of attached contexts on an adapter */
963void cxl_adapter_context_put(struct cxl *adapter);
964
965/* If no active contexts then prevents contexts from being attached */
966int cxl_adapter_context_lock(struct cxl *adapter);
967
968/* Unlock the contexts-lock if taken. Warn and force unlock otherwise */
969void cxl_adapter_context_unlock(struct cxl *adapter);
970
947#endif 971#endif
diff --git a/drivers/misc/cxl/file.c b/drivers/misc/cxl/file.c
index 5fb9894b157f..d0b421f49b39 100644
--- a/drivers/misc/cxl/file.c
+++ b/drivers/misc/cxl/file.c
@@ -205,11 +205,22 @@ static long afu_ioctl_start_work(struct cxl_context *ctx,
205 ctx->pid = get_task_pid(current, PIDTYPE_PID); 205 ctx->pid = get_task_pid(current, PIDTYPE_PID);
206 ctx->glpid = get_task_pid(current->group_leader, PIDTYPE_PID); 206 ctx->glpid = get_task_pid(current->group_leader, PIDTYPE_PID);
207 207
208 /*
209 * Increment the mapped context count for adapter. This also checks
210 * if adapter_context_lock is taken.
211 */
212 rc = cxl_adapter_context_get(ctx->afu->adapter);
213 if (rc) {
214 afu_release_irqs(ctx, ctx);
215 goto out;
216 }
217
208 trace_cxl_attach(ctx, work.work_element_descriptor, work.num_interrupts, amr); 218 trace_cxl_attach(ctx, work.work_element_descriptor, work.num_interrupts, amr);
209 219
210 if ((rc = cxl_ops->attach_process(ctx, false, work.work_element_descriptor, 220 if ((rc = cxl_ops->attach_process(ctx, false, work.work_element_descriptor,
211 amr))) { 221 amr))) {
212 afu_release_irqs(ctx, ctx); 222 afu_release_irqs(ctx, ctx);
223 cxl_adapter_context_put(ctx->afu->adapter);
213 goto out; 224 goto out;
214 } 225 }
215 226
diff --git a/drivers/misc/cxl/guest.c b/drivers/misc/cxl/guest.c
index 9aa58a77a24d..3e102cd6ed91 100644
--- a/drivers/misc/cxl/guest.c
+++ b/drivers/misc/cxl/guest.c
@@ -1152,6 +1152,9 @@ struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_devic
1152 if ((rc = cxl_sysfs_adapter_add(adapter))) 1152 if ((rc = cxl_sysfs_adapter_add(adapter)))
1153 goto err_put1; 1153 goto err_put1;
1154 1154
1155 /* release the context lock as the adapter is configured */
1156 cxl_adapter_context_unlock(adapter);
1157
1155 return adapter; 1158 return adapter;
1156 1159
1157err_put1: 1160err_put1:
diff --git a/drivers/misc/cxl/main.c b/drivers/misc/cxl/main.c
index d9be23b24aa3..62e0dfb5f15b 100644
--- a/drivers/misc/cxl/main.c
+++ b/drivers/misc/cxl/main.c
@@ -243,8 +243,10 @@ struct cxl *cxl_alloc_adapter(void)
243 if (dev_set_name(&adapter->dev, "card%i", adapter->adapter_num)) 243 if (dev_set_name(&adapter->dev, "card%i", adapter->adapter_num))
244 goto err2; 244 goto err2;
245 245
246 return adapter; 246 /* start with context lock taken */
247 atomic_set(&adapter->contexts_num, -1);
247 248
249 return adapter;
248err2: 250err2:
249 cxl_remove_adapter_nr(adapter); 251 cxl_remove_adapter_nr(adapter);
250err1: 252err1:
@@ -286,6 +288,44 @@ int cxl_afu_select_best_mode(struct cxl_afu *afu)
286 return 0; 288 return 0;
287} 289}
288 290
291int cxl_adapter_context_get(struct cxl *adapter)
292{
293 int rc;
294
295 rc = atomic_inc_unless_negative(&adapter->contexts_num);
296 return rc >= 0 ? 0 : -EBUSY;
297}
298
299void cxl_adapter_context_put(struct cxl *adapter)
300{
301 atomic_dec_if_positive(&adapter->contexts_num);
302}
303
304int cxl_adapter_context_lock(struct cxl *adapter)
305{
306 int rc;
307 /* no active contexts -> contexts_num == 0 */
308 rc = atomic_cmpxchg(&adapter->contexts_num, 0, -1);
309 return rc ? -EBUSY : 0;
310}
311
312void cxl_adapter_context_unlock(struct cxl *adapter)
313{
314 int val = atomic_cmpxchg(&adapter->contexts_num, -1, 0);
315
316 /*
317 * contexts lock taken -> contexts_num == -1
318 * If not true then show a warning and force reset the lock.
319 * This will happen when context_unlock was requested without
320 * doing a context_lock.
321 */
322 if (val != -1) {
323 atomic_set(&adapter->contexts_num, 0);
324 WARN(1, "Adapter context unlocked with %d active contexts",
325 val);
326 }
327}
328
289static int __init init_cxl(void) 329static int __init init_cxl(void)
290{ 330{
291 int rc = 0; 331 int rc = 0;
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 7afad8477ad5..e96be9ca4e60 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -1487,6 +1487,8 @@ static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev)
1487 if ((rc = cxl_native_register_psl_err_irq(adapter))) 1487 if ((rc = cxl_native_register_psl_err_irq(adapter)))
1488 goto err; 1488 goto err;
1489 1489
1490 /* Release the context lock as adapter is configured */
1491 cxl_adapter_context_unlock(adapter);
1490 return 0; 1492 return 0;
1491 1493
1492err: 1494err:
diff --git a/drivers/misc/cxl/sysfs.c b/drivers/misc/cxl/sysfs.c
index b043c20f158f..a8b6d6a635e9 100644
--- a/drivers/misc/cxl/sysfs.c
+++ b/drivers/misc/cxl/sysfs.c
@@ -75,12 +75,31 @@ static ssize_t reset_adapter_store(struct device *device,
75 int val; 75 int val;
76 76
77 rc = sscanf(buf, "%i", &val); 77 rc = sscanf(buf, "%i", &val);
78 if ((rc != 1) || (val != 1)) 78 if ((rc != 1) || (val != 1 && val != -1))
79 return -EINVAL; 79 return -EINVAL;
80 80
81 if ((rc = cxl_ops->adapter_reset(adapter))) 81 /*
82 return rc; 82 * See if we can lock the context mapping that's only allowed
83 return count; 83 * when there are no contexts attached to the adapter. Once
84 * taken this will also prevent any context from getting activated.
85 */
86 if (val == 1) {
87 rc = cxl_adapter_context_lock(adapter);
88 if (rc)
89 goto out;
90
91 rc = cxl_ops->adapter_reset(adapter);
92 /* In case reset failed release context lock */
93 if (rc)
94 cxl_adapter_context_unlock(adapter);
95
96 } else if (val == -1) {
97 /* Perform a forced adapter reset */
98 rc = cxl_ops->adapter_reset(adapter);
99 }
100
101out:
102 return rc ? rc : count;
84} 103}
85 104
86static ssize_t load_image_on_perst_show(struct device *device, 105static ssize_t load_image_on_perst_show(struct device *device,
diff --git a/drivers/misc/mic/scif/scif_rma.c b/drivers/misc/mic/scif/scif_rma.c
index e0203b1a20fd..f806a4471eb9 100644
--- a/drivers/misc/mic/scif/scif_rma.c
+++ b/drivers/misc/mic/scif/scif_rma.c
@@ -1396,8 +1396,7 @@ retry:
1396 pinned_pages->nr_pages = get_user_pages( 1396 pinned_pages->nr_pages = get_user_pages(
1397 (u64)addr, 1397 (u64)addr,
1398 nr_pages, 1398 nr_pages,
1399 !!(prot & SCIF_PROT_WRITE), 1399 (prot & SCIF_PROT_WRITE) ? FOLL_WRITE : 0,
1400 0,
1401 pinned_pages->pages, 1400 pinned_pages->pages,
1402 NULL); 1401 NULL);
1403 up_write(&mm->mmap_sem); 1402 up_write(&mm->mmap_sem);
diff --git a/drivers/misc/sgi-gru/grufault.c b/drivers/misc/sgi-gru/grufault.c
index a2d97b9b17e3..6fb773dbcd0c 100644
--- a/drivers/misc/sgi-gru/grufault.c
+++ b/drivers/misc/sgi-gru/grufault.c
@@ -198,7 +198,7 @@ static int non_atomic_pte_lookup(struct vm_area_struct *vma,
198#else 198#else
199 *pageshift = PAGE_SHIFT; 199 *pageshift = PAGE_SHIFT;
200#endif 200#endif
201 if (get_user_pages(vaddr, 1, write, 0, &page, NULL) <= 0) 201 if (get_user_pages(vaddr, 1, write ? FOLL_WRITE : 0, &page, NULL) <= 0)
202 return -EFAULT; 202 return -EFAULT;
203 *paddr = page_to_phys(page); 203 *paddr = page_to_phys(page);
204 put_page(page); 204 put_page(page);
diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index c3335112e68c..709a872ed484 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -46,6 +46,7 @@
46#include <asm/uaccess.h> 46#include <asm/uaccess.h>
47 47
48#include "queue.h" 48#include "queue.h"
49#include "block.h"
49 50
50MODULE_ALIAS("mmc:block"); 51MODULE_ALIAS("mmc:block");
51#ifdef MODULE_PARAM_PREFIX 52#ifdef MODULE_PARAM_PREFIX
@@ -1786,7 +1787,7 @@ static void mmc_blk_packed_hdr_wrq_prep(struct mmc_queue_req *mqrq,
1786 struct mmc_blk_data *md = mq->data; 1787 struct mmc_blk_data *md = mq->data;
1787 struct mmc_packed *packed = mqrq->packed; 1788 struct mmc_packed *packed = mqrq->packed;
1788 bool do_rel_wr, do_data_tag; 1789 bool do_rel_wr, do_data_tag;
1789 u32 *packed_cmd_hdr; 1790 __le32 *packed_cmd_hdr;
1790 u8 hdr_blocks; 1791 u8 hdr_blocks;
1791 u8 i = 1; 1792 u8 i = 1;
1792 1793
diff --git a/drivers/mmc/card/queue.h b/drivers/mmc/card/queue.h
index 3c15a75bae86..342f1e3f301e 100644
--- a/drivers/mmc/card/queue.h
+++ b/drivers/mmc/card/queue.h
@@ -31,7 +31,7 @@ enum mmc_packed_type {
31 31
32struct mmc_packed { 32struct mmc_packed {
33 struct list_head list; 33 struct list_head list;
34 u32 cmd_hdr[1024]; 34 __le32 cmd_hdr[1024];
35 unsigned int blocks; 35 unsigned int blocks;
36 u8 nr_entries; 36 u8 nr_entries;
37 u8 retries; 37 u8 retries;
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 3486bc7fbb64..39fc5b2b96c5 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -1263,6 +1263,16 @@ static int mmc_select_hs400es(struct mmc_card *card)
1263 goto out_err; 1263 goto out_err;
1264 } 1264 }
1265 1265
1266 if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400_1_2V)
1267 err = __mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_120);
1268
1269 if (err && card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400_1_8V)
1270 err = __mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180);
1271
1272 /* If fails try again during next card power cycle */
1273 if (err)
1274 goto out_err;
1275
1266 err = mmc_select_bus_width(card); 1276 err = mmc_select_bus_width(card);
1267 if (err < 0) 1277 if (err < 0)
1268 goto out_err; 1278 goto out_err;
@@ -1272,6 +1282,8 @@ static int mmc_select_hs400es(struct mmc_card *card)
1272 if (err) 1282 if (err)
1273 goto out_err; 1283 goto out_err;
1274 1284
1285 mmc_set_clock(host, card->ext_csd.hs_max_dtr);
1286
1275 err = mmc_switch_status(card); 1287 err = mmc_switch_status(card);
1276 if (err) 1288 if (err)
1277 goto out_err; 1289 goto out_err;
diff --git a/drivers/mmc/host/rtsx_usb_sdmmc.c b/drivers/mmc/host/rtsx_usb_sdmmc.c
index 4106295527b9..6e9c0f8fddb1 100644
--- a/drivers/mmc/host/rtsx_usb_sdmmc.c
+++ b/drivers/mmc/host/rtsx_usb_sdmmc.c
@@ -1138,11 +1138,6 @@ static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1138 dev_dbg(sdmmc_dev(host), "%s\n", __func__); 1138 dev_dbg(sdmmc_dev(host), "%s\n", __func__);
1139 mutex_lock(&ucr->dev_mutex); 1139 mutex_lock(&ucr->dev_mutex);
1140 1140
1141 if (rtsx_usb_card_exclusive_check(ucr, RTSX_USB_SD_CARD)) {
1142 mutex_unlock(&ucr->dev_mutex);
1143 return;
1144 }
1145
1146 sd_set_power_mode(host, ios->power_mode); 1141 sd_set_power_mode(host, ios->power_mode);
1147 sd_set_bus_width(host, ios->bus_width); 1142 sd_set_bus_width(host, ios->bus_width);
1148 sd_set_timing(host, ios->timing, &host->ddr_mode); 1143 sd_set_timing(host, ios->timing, &host->ddr_mode);
@@ -1314,6 +1309,7 @@ static void rtsx_usb_update_led(struct work_struct *work)
1314 container_of(work, struct rtsx_usb_sdmmc, led_work); 1309 container_of(work, struct rtsx_usb_sdmmc, led_work);
1315 struct rtsx_ucr *ucr = host->ucr; 1310 struct rtsx_ucr *ucr = host->ucr;
1316 1311
1312 pm_runtime_get_sync(sdmmc_dev(host));
1317 mutex_lock(&ucr->dev_mutex); 1313 mutex_lock(&ucr->dev_mutex);
1318 1314
1319 if (host->led.brightness == LED_OFF) 1315 if (host->led.brightness == LED_OFF)
@@ -1322,6 +1318,7 @@ static void rtsx_usb_update_led(struct work_struct *work)
1322 rtsx_usb_turn_on_led(ucr); 1318 rtsx_usb_turn_on_led(ucr);
1323 1319
1324 mutex_unlock(&ucr->dev_mutex); 1320 mutex_unlock(&ucr->dev_mutex);
1321 pm_runtime_put(sdmmc_dev(host));
1325} 1322}
1326#endif 1323#endif
1327 1324
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 1f54fd8755c8..7123ef96ed18 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -346,7 +346,8 @@ static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
346 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 346 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
347 u32 data; 347 u32 data;
348 348
349 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 349 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
350 reg == SDHCI_INT_STATUS)) {
350 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 351 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
351 /* 352 /*
352 * Clear and then set D3CD bit to avoid missing the 353 * Clear and then set D3CD bit to avoid missing the
@@ -555,6 +556,25 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
555 esdhc_clrset_le(host, 0xffff, val, reg); 556 esdhc_clrset_le(host, 0xffff, val, reg);
556} 557}
557 558
559static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
560{
561 u8 ret;
562 u32 val;
563
564 switch (reg) {
565 case SDHCI_HOST_CONTROL:
566 val = readl(host->ioaddr + reg);
567
568 ret = val & SDHCI_CTRL_LED;
569 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
570 ret |= (val & ESDHC_CTRL_4BITBUS);
571 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
572 return ret;
573 }
574
575 return readb(host->ioaddr + reg);
576}
577
558static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 578static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
559{ 579{
560 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 580 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -947,6 +967,7 @@ static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
947static struct sdhci_ops sdhci_esdhc_ops = { 967static struct sdhci_ops sdhci_esdhc_ops = {
948 .read_l = esdhc_readl_le, 968 .read_l = esdhc_readl_le,
949 .read_w = esdhc_readw_le, 969 .read_w = esdhc_readw_le,
970 .read_b = esdhc_readb_le,
950 .write_l = esdhc_writel_le, 971 .write_l = esdhc_writel_le,
951 .write_w = esdhc_writew_le, 972 .write_w = esdhc_writew_le,
952 .write_b = esdhc_writeb_le, 973 .write_b = esdhc_writeb_le,
diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index da8e40af6f85..410a55b1c25f 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -250,7 +250,7 @@ static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
250 writel(vendor, host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER); 250 writel(vendor, host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER);
251} 251}
252 252
253void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) 253static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
254{ 254{
255 u8 ctrl; 255 u8 ctrl;
256 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 256 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -265,6 +265,28 @@ void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
265 } 265 }
266} 266}
267 267
268static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
269 struct mmc_ios *ios)
270{
271 switch (ios->signal_voltage) {
272 case MMC_SIGNAL_VOLTAGE_180:
273 /*
274 * Plese don't switch to 1V8 as arasan,5.1 doesn't
275 * actually refer to this setting to indicate the
276 * signal voltage and the state machine will be broken
277 * actually if we force to enable 1V8. That's something
278 * like broken quirk but we could work around here.
279 */
280 return 0;
281 case MMC_SIGNAL_VOLTAGE_330:
282 case MMC_SIGNAL_VOLTAGE_120:
283 /* We don't support 3V3 and 1V2 */
284 break;
285 }
286
287 return -EINVAL;
288}
289
268static struct sdhci_ops sdhci_arasan_ops = { 290static struct sdhci_ops sdhci_arasan_ops = {
269 .set_clock = sdhci_arasan_set_clock, 291 .set_clock = sdhci_arasan_set_clock,
270 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 292 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
@@ -661,6 +683,8 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
661 683
662 host->mmc_host_ops.hs400_enhanced_strobe = 684 host->mmc_host_ops.hs400_enhanced_strobe =
663 sdhci_arasan_hs400_enhanced_strobe; 685 sdhci_arasan_hs400_enhanced_strobe;
686 host->mmc_host_ops.start_signal_voltage_switch =
687 sdhci_arasan_voltage_switch;
664 } 688 }
665 689
666 ret = sdhci_add_host(host); 690 ret = sdhci_add_host(host);
diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c
index 72a1f1f5180a..1d9e00a00e9f 100644
--- a/drivers/mmc/host/sdhci-pci-core.c
+++ b/drivers/mmc/host/sdhci-pci-core.c
@@ -32,6 +32,14 @@
32#include "sdhci-pci.h" 32#include "sdhci-pci.h"
33#include "sdhci-pci-o2micro.h" 33#include "sdhci-pci-o2micro.h"
34 34
35static int sdhci_pci_enable_dma(struct sdhci_host *host);
36static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width);
37static void sdhci_pci_hw_reset(struct sdhci_host *host);
38static int sdhci_pci_select_drive_strength(struct sdhci_host *host,
39 struct mmc_card *card,
40 unsigned int max_dtr, int host_drv,
41 int card_drv, int *drv_type);
42
35/*****************************************************************************\ 43/*****************************************************************************\
36 * * 44 * *
37 * Hardware specific quirk handling * 45 * Hardware specific quirk handling *
@@ -390,6 +398,45 @@ static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
390 return 0; 398 return 0;
391} 399}
392 400
401#define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
402#define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
403
404static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
405 unsigned short vdd)
406{
407 int cntr;
408 u8 reg;
409
410 sdhci_set_power(host, mode, vdd);
411
412 if (mode == MMC_POWER_OFF)
413 return;
414
415 /*
416 * Bus power might not enable after D3 -> D0 transition due to the
417 * present state not yet having propagated. Retry for up to 2ms.
418 */
419 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
420 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
421 if (reg & SDHCI_POWER_ON)
422 break;
423 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
424 reg |= SDHCI_POWER_ON;
425 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
426 }
427}
428
429static const struct sdhci_ops sdhci_intel_byt_ops = {
430 .set_clock = sdhci_set_clock,
431 .set_power = sdhci_intel_set_power,
432 .enable_dma = sdhci_pci_enable_dma,
433 .set_bus_width = sdhci_pci_set_bus_width,
434 .reset = sdhci_reset,
435 .set_uhs_signaling = sdhci_set_uhs_signaling,
436 .hw_reset = sdhci_pci_hw_reset,
437 .select_drive_strength = sdhci_pci_select_drive_strength,
438};
439
393static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 440static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
394 .allow_runtime_pm = true, 441 .allow_runtime_pm = true,
395 .probe_slot = byt_emmc_probe_slot, 442 .probe_slot = byt_emmc_probe_slot,
@@ -397,6 +444,7 @@ static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
397 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 444 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
398 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 445 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
399 SDHCI_QUIRK2_STOP_WITH_TC, 446 SDHCI_QUIRK2_STOP_WITH_TC,
447 .ops = &sdhci_intel_byt_ops,
400}; 448};
401 449
402static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 450static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
@@ -405,6 +453,7 @@ static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
405 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 453 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
406 .allow_runtime_pm = true, 454 .allow_runtime_pm = true,
407 .probe_slot = byt_sdio_probe_slot, 455 .probe_slot = byt_sdio_probe_slot,
456 .ops = &sdhci_intel_byt_ops,
408}; 457};
409 458
410static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 459static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
@@ -415,6 +464,7 @@ static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
415 .allow_runtime_pm = true, 464 .allow_runtime_pm = true,
416 .own_cd_for_runtime_pm = true, 465 .own_cd_for_runtime_pm = true,
417 .probe_slot = byt_sd_probe_slot, 466 .probe_slot = byt_sd_probe_slot,
467 .ops = &sdhci_intel_byt_ops,
418}; 468};
419 469
420/* Define Host controllers for Intel Merrifield platform */ 470/* Define Host controllers for Intel Merrifield platform */
@@ -1648,7 +1698,9 @@ static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1648 } 1698 }
1649 1699
1650 host->hw_name = "PCI"; 1700 host->hw_name = "PCI";
1651 host->ops = &sdhci_pci_ops; 1701 host->ops = chip->fixes && chip->fixes->ops ?
1702 chip->fixes->ops :
1703 &sdhci_pci_ops;
1652 host->quirks = chip->quirks; 1704 host->quirks = chip->quirks;
1653 host->quirks2 = chip->quirks2; 1705 host->quirks2 = chip->quirks2;
1654 1706
diff --git a/drivers/mmc/host/sdhci-pci.h b/drivers/mmc/host/sdhci-pci.h
index 9c7c08b93223..6bccf56bc5ff 100644
--- a/drivers/mmc/host/sdhci-pci.h
+++ b/drivers/mmc/host/sdhci-pci.h
@@ -65,6 +65,8 @@ struct sdhci_pci_fixes {
65 65
66 int (*suspend) (struct sdhci_pci_chip *); 66 int (*suspend) (struct sdhci_pci_chip *);
67 int (*resume) (struct sdhci_pci_chip *); 67 int (*resume) (struct sdhci_pci_chip *);
68
69 const struct sdhci_ops *ops;
68}; 70};
69 71
70struct sdhci_pci_slot { 72struct sdhci_pci_slot {
diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index dd1938d341f7..d0f5c05fbc19 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -315,7 +315,7 @@ static void pxav3_set_power(struct sdhci_host *host, unsigned char mode,
315 struct mmc_host *mmc = host->mmc; 315 struct mmc_host *mmc = host->mmc;
316 u8 pwr = host->pwr; 316 u8 pwr = host->pwr;
317 317
318 sdhci_set_power(host, mode, vdd); 318 sdhci_set_power_noreg(host, mode, vdd);
319 319
320 if (host->pwr == pwr) 320 if (host->pwr == pwr)
321 return; 321 return;
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 48055666c655..71654b90227f 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -687,7 +687,7 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
687 * host->clock is in Hz. target_timeout is in us. 687 * host->clock is in Hz. target_timeout is in us.
688 * Hence, us = 1000000 * cycles / Hz. Round up. 688 * Hence, us = 1000000 * cycles / Hz. Round up.
689 */ 689 */
690 val = 1000000 * data->timeout_clks; 690 val = 1000000ULL * data->timeout_clks;
691 if (do_div(val, host->clock)) 691 if (do_div(val, host->clock))
692 target_timeout++; 692 target_timeout++;
693 target_timeout += val; 693 target_timeout += val;
@@ -1077,6 +1077,10 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1077 /* Initially, a command has no error */ 1077 /* Initially, a command has no error */
1078 cmd->error = 0; 1078 cmd->error = 0;
1079 1079
1080 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1081 cmd->opcode == MMC_STOP_TRANSMISSION)
1082 cmd->flags |= MMC_RSP_BUSY;
1083
1080 /* Wait max 10 ms */ 1084 /* Wait max 10 ms */
1081 timeout = 10; 1085 timeout = 10;
1082 1086
@@ -1390,8 +1394,8 @@ static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1390 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1394 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1391} 1395}
1392 1396
1393void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 1397void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
1394 unsigned short vdd) 1398 unsigned short vdd)
1395{ 1399{
1396 u8 pwr = 0; 1400 u8 pwr = 0;
1397 1401
@@ -1455,20 +1459,17 @@ void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1455 mdelay(10); 1459 mdelay(10);
1456 } 1460 }
1457} 1461}
1458EXPORT_SYMBOL_GPL(sdhci_set_power); 1462EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
1459 1463
1460static void __sdhci_set_power(struct sdhci_host *host, unsigned char mode, 1464void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1461 unsigned short vdd) 1465 unsigned short vdd)
1462{ 1466{
1463 struct mmc_host *mmc = host->mmc; 1467 if (IS_ERR(host->mmc->supply.vmmc))
1464 1468 sdhci_set_power_noreg(host, mode, vdd);
1465 if (host->ops->set_power)
1466 host->ops->set_power(host, mode, vdd);
1467 else if (!IS_ERR(mmc->supply.vmmc))
1468 sdhci_set_power_reg(host, mode, vdd);
1469 else 1469 else
1470 sdhci_set_power(host, mode, vdd); 1470 sdhci_set_power_reg(host, mode, vdd);
1471} 1471}
1472EXPORT_SYMBOL_GPL(sdhci_set_power);
1472 1473
1473/*****************************************************************************\ 1474/*****************************************************************************\
1474 * * 1475 * *
@@ -1609,7 +1610,10 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1609 } 1610 }
1610 } 1611 }
1611 1612
1612 __sdhci_set_power(host, ios->power_mode, ios->vdd); 1613 if (host->ops->set_power)
1614 host->ops->set_power(host, ios->power_mode, ios->vdd);
1615 else
1616 sdhci_set_power(host, ios->power_mode, ios->vdd);
1613 1617
1614 if (host->ops->platform_send_init_74_clocks) 1618 if (host->ops->platform_send_init_74_clocks)
1615 host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1619 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
@@ -2409,7 +2413,7 @@ static void sdhci_timeout_data_timer(unsigned long data)
2409 * * 2413 * *
2410\*****************************************************************************/ 2414\*****************************************************************************/
2411 2415
2412static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask) 2416static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2413{ 2417{
2414 if (!host->cmd) { 2418 if (!host->cmd) {
2415 /* 2419 /*
@@ -2453,11 +2457,6 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2453 return; 2457 return;
2454 } 2458 }
2455 2459
2456 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2457 !(host->cmd->flags & MMC_RSP_BUSY) && !host->data &&
2458 host->cmd->opcode == MMC_STOP_TRANSMISSION)
2459 *mask &= ~SDHCI_INT_DATA_END;
2460
2461 if (intmask & SDHCI_INT_RESPONSE) 2460 if (intmask & SDHCI_INT_RESPONSE)
2462 sdhci_finish_command(host); 2461 sdhci_finish_command(host);
2463} 2462}
@@ -2680,8 +2679,7 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id)
2680 } 2679 }
2681 2680
2682 if (intmask & SDHCI_INT_CMD_MASK) 2681 if (intmask & SDHCI_INT_CMD_MASK)
2683 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, 2682 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2684 &intmask);
2685 2683
2686 if (intmask & SDHCI_INT_DATA_MASK) 2684 if (intmask & SDHCI_INT_DATA_MASK)
2687 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 2685 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index c722cd23205c..766df17fb7eb 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -683,6 +683,8 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
683void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); 683void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
684void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 684void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
685 unsigned short vdd); 685 unsigned short vdd);
686void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
687 unsigned short vdd);
686void sdhci_set_bus_width(struct sdhci_host *host, int width); 688void sdhci_set_bus_width(struct sdhci_host *host, int width);
687void sdhci_reset(struct sdhci_host *host, u8 mask); 689void sdhci_reset(struct sdhci_host *host, u8 mask);
688void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); 690void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c
index 95c4048a371e..388e46be6ad9 100644
--- a/drivers/mtd/ubi/eba.c
+++ b/drivers/mtd/ubi/eba.c
@@ -741,6 +741,7 @@ static int try_recover_peb(struct ubi_volume *vol, int pnum, int lnum,
741 goto out_put; 741 goto out_put;
742 } 742 }
743 743
744 vid_hdr = ubi_get_vid_hdr(vidb);
744 ubi_assert(vid_hdr->vol_type == UBI_VID_DYNAMIC); 745 ubi_assert(vid_hdr->vol_type == UBI_VID_DYNAMIC);
745 746
746 mutex_lock(&ubi->buf_mutex); 747 mutex_lock(&ubi->buf_mutex);
diff --git a/drivers/mtd/ubi/fastmap.c b/drivers/mtd/ubi/fastmap.c
index d6384d965788..2ff62157d3bb 100644
--- a/drivers/mtd/ubi/fastmap.c
+++ b/drivers/mtd/ubi/fastmap.c
@@ -287,7 +287,7 @@ static int update_vol(struct ubi_device *ubi, struct ubi_attach_info *ai,
287 287
288 /* new_aeb is newer */ 288 /* new_aeb is newer */
289 if (cmp_res & 1) { 289 if (cmp_res & 1) {
290 victim = ubi_alloc_aeb(ai, aeb->ec, aeb->pnum); 290 victim = ubi_alloc_aeb(ai, aeb->pnum, aeb->ec);
291 if (!victim) 291 if (!victim)
292 return -ENOMEM; 292 return -ENOMEM;
293 293
diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c
index 329381a28edf..79e679d12f3b 100644
--- a/drivers/nvme/host/core.c
+++ b/drivers/nvme/host/core.c
@@ -554,7 +554,7 @@ int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
554 554
555 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */ 555 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
556 c.identify.opcode = nvme_admin_identify; 556 c.identify.opcode = nvme_admin_identify;
557 c.identify.cns = cpu_to_le32(1); 557 c.identify.cns = cpu_to_le32(NVME_ID_CNS_CTRL);
558 558
559 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL); 559 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
560 if (!*id) 560 if (!*id)
@@ -572,7 +572,7 @@ static int nvme_identify_ns_list(struct nvme_ctrl *dev, unsigned nsid, __le32 *n
572 struct nvme_command c = { }; 572 struct nvme_command c = { };
573 573
574 c.identify.opcode = nvme_admin_identify; 574 c.identify.opcode = nvme_admin_identify;
575 c.identify.cns = cpu_to_le32(2); 575 c.identify.cns = cpu_to_le32(NVME_ID_CNS_NS_ACTIVE_LIST);
576 c.identify.nsid = cpu_to_le32(nsid); 576 c.identify.nsid = cpu_to_le32(nsid);
577 return nvme_submit_sync_cmd(dev->admin_q, &c, ns_list, 0x1000); 577 return nvme_submit_sync_cmd(dev->admin_q, &c, ns_list, 0x1000);
578} 578}
@@ -900,9 +900,9 @@ static int nvme_revalidate_ns(struct nvme_ns *ns, struct nvme_id_ns **id)
900 return -ENODEV; 900 return -ENODEV;
901 } 901 }
902 902
903 if (ns->ctrl->vs >= NVME_VS(1, 1)) 903 if (ns->ctrl->vs >= NVME_VS(1, 1, 0))
904 memcpy(ns->eui, (*id)->eui64, sizeof(ns->eui)); 904 memcpy(ns->eui, (*id)->eui64, sizeof(ns->eui));
905 if (ns->ctrl->vs >= NVME_VS(1, 2)) 905 if (ns->ctrl->vs >= NVME_VS(1, 2, 0))
906 memcpy(ns->uuid, (*id)->nguid, sizeof(ns->uuid)); 906 memcpy(ns->uuid, (*id)->nguid, sizeof(ns->uuid));
907 907
908 return 0; 908 return 0;
@@ -1086,6 +1086,8 @@ static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
1086 int ret; 1086 int ret;
1087 1087
1088 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) { 1088 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
1089 if (csts == ~0)
1090 return -ENODEV;
1089 if ((csts & NVME_CSTS_RDY) == bit) 1091 if ((csts & NVME_CSTS_RDY) == bit)
1090 break; 1092 break;
1091 1093
@@ -1240,7 +1242,7 @@ int nvme_init_identify(struct nvme_ctrl *ctrl)
1240 } 1242 }
1241 page_shift = NVME_CAP_MPSMIN(cap) + 12; 1243 page_shift = NVME_CAP_MPSMIN(cap) + 12;
1242 1244
1243 if (ctrl->vs >= NVME_VS(1, 1)) 1245 if (ctrl->vs >= NVME_VS(1, 1, 0))
1244 ctrl->subsystem = NVME_CAP_NSSRC(cap); 1246 ctrl->subsystem = NVME_CAP_NSSRC(cap);
1245 1247
1246 ret = nvme_identify_ctrl(ctrl, &id); 1248 ret = nvme_identify_ctrl(ctrl, &id);
@@ -1840,7 +1842,7 @@ static void nvme_scan_work(struct work_struct *work)
1840 return; 1842 return;
1841 1843
1842 nn = le32_to_cpu(id->nn); 1844 nn = le32_to_cpu(id->nn);
1843 if (ctrl->vs >= NVME_VS(1, 1) && 1845 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
1844 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) { 1846 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
1845 if (!nvme_scan_ns_list(ctrl, nn)) 1847 if (!nvme_scan_ns_list(ctrl, nn))
1846 goto done; 1848 goto done;
diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 0fc99f0f2571..0248d0e21fee 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -99,6 +99,7 @@ struct nvme_dev {
99 dma_addr_t cmb_dma_addr; 99 dma_addr_t cmb_dma_addr;
100 u64 cmb_size; 100 u64 cmb_size;
101 u32 cmbsz; 101 u32 cmbsz;
102 u32 cmbloc;
102 struct nvme_ctrl ctrl; 103 struct nvme_ctrl ctrl;
103 struct completion ioq_wait; 104 struct completion ioq_wait;
104}; 105};
@@ -893,7 +894,7 @@ static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
893 "I/O %d QID %d timeout, reset controller\n", 894 "I/O %d QID %d timeout, reset controller\n",
894 req->tag, nvmeq->qid); 895 req->tag, nvmeq->qid);
895 nvme_dev_disable(dev, false); 896 nvme_dev_disable(dev, false);
896 queue_work(nvme_workq, &dev->reset_work); 897 nvme_reset(dev);
897 898
898 /* 899 /*
899 * Mark the request as handled, since the inline shutdown 900 * Mark the request as handled, since the inline shutdown
@@ -1214,7 +1215,7 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev)
1214 u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 1215 u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1215 struct nvme_queue *nvmeq; 1216 struct nvme_queue *nvmeq;
1216 1217
1217 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ? 1218 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1218 NVME_CAP_NSSRC(cap) : 0; 1219 NVME_CAP_NSSRC(cap) : 0;
1219 1220
1220 if (dev->subsystem && 1221 if (dev->subsystem &&
@@ -1291,7 +1292,7 @@ static void nvme_watchdog_timer(unsigned long data)
1291 1292
1292 /* Skip controllers under certain specific conditions. */ 1293 /* Skip controllers under certain specific conditions. */
1293 if (nvme_should_reset(dev, csts)) { 1294 if (nvme_should_reset(dev, csts)) {
1294 if (queue_work(nvme_workq, &dev->reset_work)) 1295 if (!nvme_reset(dev))
1295 dev_warn(dev->dev, 1296 dev_warn(dev->dev,
1296 "Failed status: 0x%x, reset controller.\n", 1297 "Failed status: 0x%x, reset controller.\n",
1297 csts); 1298 csts);
@@ -1331,28 +1332,37 @@ static int nvme_create_io_queues(struct nvme_dev *dev)
1331 return ret >= 0 ? 0 : ret; 1332 return ret >= 0 ? 0 : ret;
1332} 1333}
1333 1334
1335static ssize_t nvme_cmb_show(struct device *dev,
1336 struct device_attribute *attr,
1337 char *buf)
1338{
1339 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1340
1341 return snprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1342 ndev->cmbloc, ndev->cmbsz);
1343}
1344static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1345
1334static void __iomem *nvme_map_cmb(struct nvme_dev *dev) 1346static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1335{ 1347{
1336 u64 szu, size, offset; 1348 u64 szu, size, offset;
1337 u32 cmbloc;
1338 resource_size_t bar_size; 1349 resource_size_t bar_size;
1339 struct pci_dev *pdev = to_pci_dev(dev->dev); 1350 struct pci_dev *pdev = to_pci_dev(dev->dev);
1340 void __iomem *cmb; 1351 void __iomem *cmb;
1341 dma_addr_t dma_addr; 1352 dma_addr_t dma_addr;
1342 1353
1343 if (!use_cmb_sqes)
1344 return NULL;
1345
1346 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1354 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1347 if (!(NVME_CMB_SZ(dev->cmbsz))) 1355 if (!(NVME_CMB_SZ(dev->cmbsz)))
1348 return NULL; 1356 return NULL;
1357 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1349 1358
1350 cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1359 if (!use_cmb_sqes)
1360 return NULL;
1351 1361
1352 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); 1362 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1353 size = szu * NVME_CMB_SZ(dev->cmbsz); 1363 size = szu * NVME_CMB_SZ(dev->cmbsz);
1354 offset = szu * NVME_CMB_OFST(cmbloc); 1364 offset = szu * NVME_CMB_OFST(dev->cmbloc);
1355 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); 1365 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
1356 1366
1357 if (offset > bar_size) 1367 if (offset > bar_size)
1358 return NULL; 1368 return NULL;
@@ -1365,7 +1375,7 @@ static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1365 if (size > bar_size - offset) 1375 if (size > bar_size - offset)
1366 size = bar_size - offset; 1376 size = bar_size - offset;
1367 1377
1368 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; 1378 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
1369 cmb = ioremap_wc(dma_addr, size); 1379 cmb = ioremap_wc(dma_addr, size);
1370 if (!cmb) 1380 if (!cmb)
1371 return NULL; 1381 return NULL;
@@ -1511,9 +1521,9 @@ static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1511 return 0; 1521 return 0;
1512} 1522}
1513 1523
1514static void nvme_disable_io_queues(struct nvme_dev *dev) 1524static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
1515{ 1525{
1516 int pass, queues = dev->online_queues - 1; 1526 int pass;
1517 unsigned long timeout; 1527 unsigned long timeout;
1518 u8 opcode = nvme_admin_delete_sq; 1528 u8 opcode = nvme_admin_delete_sq;
1519 1529
@@ -1616,9 +1626,25 @@ static int nvme_pci_enable(struct nvme_dev *dev)
1616 dev->q_depth); 1626 dev->q_depth);
1617 } 1627 }
1618 1628
1619 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2)) 1629 /*
1630 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1631 * populate sysfs if a CMB is implemented. Note that we add the
1632 * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1633 * it on exit. Since nvme_dev_attrs_group has no name we can pass
1634 * NULL as final argument to sysfs_add_file_to_group.
1635 */
1636
1637 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
1620 dev->cmb = nvme_map_cmb(dev); 1638 dev->cmb = nvme_map_cmb(dev);
1621 1639
1640 if (dev->cmbsz) {
1641 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1642 &dev_attr_cmb.attr, NULL))
1643 dev_warn(dev->dev,
1644 "failed to add sysfs attribute for CMB\n");
1645 }
1646 }
1647
1622 pci_enable_pcie_error_reporting(pdev); 1648 pci_enable_pcie_error_reporting(pdev);
1623 pci_save_state(pdev); 1649 pci_save_state(pdev);
1624 return 0; 1650 return 0;
@@ -1649,7 +1675,7 @@ static void nvme_pci_disable(struct nvme_dev *dev)
1649 1675
1650static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 1676static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1651{ 1677{
1652 int i; 1678 int i, queues;
1653 u32 csts = -1; 1679 u32 csts = -1;
1654 1680
1655 del_timer_sync(&dev->watchdog_timer); 1681 del_timer_sync(&dev->watchdog_timer);
@@ -1660,6 +1686,7 @@ static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1660 csts = readl(dev->bar + NVME_REG_CSTS); 1686 csts = readl(dev->bar + NVME_REG_CSTS);
1661 } 1687 }
1662 1688
1689 queues = dev->online_queues - 1;
1663 for (i = dev->queue_count - 1; i > 0; i--) 1690 for (i = dev->queue_count - 1; i > 0; i--)
1664 nvme_suspend_queue(dev->queues[i]); 1691 nvme_suspend_queue(dev->queues[i]);
1665 1692
@@ -1671,7 +1698,7 @@ static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1671 if (dev->queue_count) 1698 if (dev->queue_count)
1672 nvme_suspend_queue(dev->queues[0]); 1699 nvme_suspend_queue(dev->queues[0]);
1673 } else { 1700 } else {
1674 nvme_disable_io_queues(dev); 1701 nvme_disable_io_queues(dev, queues);
1675 nvme_disable_admin_queue(dev, shutdown); 1702 nvme_disable_admin_queue(dev, shutdown);
1676 } 1703 }
1677 nvme_pci_disable(dev); 1704 nvme_pci_disable(dev);
@@ -1818,11 +1845,10 @@ static int nvme_reset(struct nvme_dev *dev)
1818{ 1845{
1819 if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) 1846 if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1820 return -ENODEV; 1847 return -ENODEV;
1821 1848 if (work_busy(&dev->reset_work))
1849 return -ENODEV;
1822 if (!queue_work(nvme_workq, &dev->reset_work)) 1850 if (!queue_work(nvme_workq, &dev->reset_work))
1823 return -EBUSY; 1851 return -EBUSY;
1824
1825 flush_work(&dev->reset_work);
1826 return 0; 1852 return 0;
1827} 1853}
1828 1854
@@ -1846,7 +1872,12 @@ static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
1846 1872
1847static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) 1873static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
1848{ 1874{
1849 return nvme_reset(to_nvme_dev(ctrl)); 1875 struct nvme_dev *dev = to_nvme_dev(ctrl);
1876 int ret = nvme_reset(dev);
1877
1878 if (!ret)
1879 flush_work(&dev->reset_work);
1880 return ret;
1850} 1881}
1851 1882
1852static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 1883static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
@@ -1940,7 +1971,7 @@ static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
1940 if (prepare) 1971 if (prepare)
1941 nvme_dev_disable(dev, false); 1972 nvme_dev_disable(dev, false);
1942 else 1973 else
1943 queue_work(nvme_workq, &dev->reset_work); 1974 nvme_reset(dev);
1944} 1975}
1945 1976
1946static void nvme_shutdown(struct pci_dev *pdev) 1977static void nvme_shutdown(struct pci_dev *pdev)
@@ -2009,7 +2040,7 @@ static int nvme_resume(struct device *dev)
2009 struct pci_dev *pdev = to_pci_dev(dev); 2040 struct pci_dev *pdev = to_pci_dev(dev);
2010 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2041 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2011 2042
2012 queue_work(nvme_workq, &ndev->reset_work); 2043 nvme_reset(ndev);
2013 return 0; 2044 return 0;
2014} 2045}
2015#endif 2046#endif
@@ -2048,7 +2079,7 @@ static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2048 2079
2049 dev_info(dev->ctrl.device, "restart after slot reset\n"); 2080 dev_info(dev->ctrl.device, "restart after slot reset\n");
2050 pci_restore_state(pdev); 2081 pci_restore_state(pdev);
2051 queue_work(nvme_workq, &dev->reset_work); 2082 nvme_reset(dev);
2052 return PCI_ERS_RESULT_RECOVERED; 2083 return PCI_ERS_RESULT_RECOVERED;
2053} 2084}
2054 2085
diff --git a/drivers/nvme/host/scsi.c b/drivers/nvme/host/scsi.c
index c2a0a1c7d05d..3eaa4d27801e 100644
--- a/drivers/nvme/host/scsi.c
+++ b/drivers/nvme/host/scsi.c
@@ -606,7 +606,7 @@ static int nvme_fill_device_id_eui64(struct nvme_ns *ns, struct sg_io_hdr *hdr,
606 eui = id_ns->eui64; 606 eui = id_ns->eui64;
607 len = sizeof(id_ns->eui64); 607 len = sizeof(id_ns->eui64);
608 608
609 if (ns->ctrl->vs >= NVME_VS(1, 2)) { 609 if (ns->ctrl->vs >= NVME_VS(1, 2, 0)) {
610 if (bitmap_empty(eui, len * 8)) { 610 if (bitmap_empty(eui, len * 8)) {
611 eui = id_ns->nguid; 611 eui = id_ns->nguid;
612 len = sizeof(id_ns->nguid); 612 len = sizeof(id_ns->nguid);
@@ -679,7 +679,7 @@ static int nvme_trans_device_id_page(struct nvme_ns *ns, struct sg_io_hdr *hdr,
679{ 679{
680 int res; 680 int res;
681 681
682 if (ns->ctrl->vs >= NVME_VS(1, 1)) { 682 if (ns->ctrl->vs >= NVME_VS(1, 1, 0)) {
683 res = nvme_fill_device_id_eui64(ns, hdr, resp, alloc_len); 683 res = nvme_fill_device_id_eui64(ns, hdr, resp, alloc_len);
684 if (res != -EOPNOTSUPP) 684 if (res != -EOPNOTSUPP)
685 return res; 685 return res;
diff --git a/drivers/nvme/target/admin-cmd.c b/drivers/nvme/target/admin-cmd.c
index 7ab9c9381b98..6fe4c48a21e4 100644
--- a/drivers/nvme/target/admin-cmd.c
+++ b/drivers/nvme/target/admin-cmd.c
@@ -199,7 +199,7 @@ static void nvmet_execute_identify_ctrl(struct nvmet_req *req)
199 */ 199 */
200 200
201 /* we support multiple ports and multiples hosts: */ 201 /* we support multiple ports and multiples hosts: */
202 id->mic = (1 << 0) | (1 << 1); 202 id->cmic = (1 << 0) | (1 << 1);
203 203
204 /* no limit on data transfer sizes for now */ 204 /* no limit on data transfer sizes for now */
205 id->mdts = 0; 205 id->mdts = 0;
@@ -511,13 +511,13 @@ int nvmet_parse_admin_cmd(struct nvmet_req *req)
511 case nvme_admin_identify: 511 case nvme_admin_identify:
512 req->data_len = 4096; 512 req->data_len = 4096;
513 switch (le32_to_cpu(cmd->identify.cns)) { 513 switch (le32_to_cpu(cmd->identify.cns)) {
514 case 0x00: 514 case NVME_ID_CNS_NS:
515 req->execute = nvmet_execute_identify_ns; 515 req->execute = nvmet_execute_identify_ns;
516 return 0; 516 return 0;
517 case 0x01: 517 case NVME_ID_CNS_CTRL:
518 req->execute = nvmet_execute_identify_ctrl; 518 req->execute = nvmet_execute_identify_ctrl;
519 return 0; 519 return 0;
520 case 0x02: 520 case NVME_ID_CNS_NS_ACTIVE_LIST:
521 req->execute = nvmet_execute_identify_nslist; 521 req->execute = nvmet_execute_identify_nslist;
522 return 0; 522 return 0;
523 } 523 }
diff --git a/drivers/nvme/target/core.c b/drivers/nvme/target/core.c
index 6559d5afa7bf..b4cacb6f0258 100644
--- a/drivers/nvme/target/core.c
+++ b/drivers/nvme/target/core.c
@@ -882,7 +882,7 @@ struct nvmet_subsys *nvmet_subsys_alloc(const char *subsysnqn,
882 if (!subsys) 882 if (!subsys)
883 return NULL; 883 return NULL;
884 884
885 subsys->ver = (1 << 16) | (2 << 8) | 1; /* NVMe 1.2.1 */ 885 subsys->ver = NVME_VS(1, 2, 1); /* NVMe 1.2.1 */
886 886
887 switch (type) { 887 switch (type) {
888 case NVME_NQN_NVME: 888 case NVME_NQN_NVME:
diff --git a/drivers/nvme/target/discovery.c b/drivers/nvme/target/discovery.c
index 6f65646e89cf..12f39eea569f 100644
--- a/drivers/nvme/target/discovery.c
+++ b/drivers/nvme/target/discovery.c
@@ -54,7 +54,7 @@ static void nvmet_format_discovery_entry(struct nvmf_disc_rsp_page_hdr *hdr,
54 /* we support only dynamic controllers */ 54 /* we support only dynamic controllers */
55 e->cntlid = cpu_to_le16(NVME_CNTLID_DYNAMIC); 55 e->cntlid = cpu_to_le16(NVME_CNTLID_DYNAMIC);
56 e->asqsz = cpu_to_le16(NVMF_AQ_DEPTH); 56 e->asqsz = cpu_to_le16(NVMF_AQ_DEPTH);
57 e->nqntype = type; 57 e->subtype = type;
58 memcpy(e->trsvcid, port->disc_addr.trsvcid, NVMF_TRSVCID_SIZE); 58 memcpy(e->trsvcid, port->disc_addr.trsvcid, NVMF_TRSVCID_SIZE);
59 memcpy(e->traddr, port->disc_addr.traddr, NVMF_TRADDR_SIZE); 59 memcpy(e->traddr, port->disc_addr.traddr, NVMF_TRADDR_SIZE);
60 memcpy(e->tsas.common, port->disc_addr.tsas.common, NVMF_TSAS_SIZE); 60 memcpy(e->tsas.common, port->disc_addr.tsas.common, NVMF_TSAS_SIZE);
@@ -187,7 +187,7 @@ int nvmet_parse_discovery_cmd(struct nvmet_req *req)
187 case nvme_admin_identify: 187 case nvme_admin_identify:
188 req->data_len = 4096; 188 req->data_len = 4096;
189 switch (le32_to_cpu(cmd->identify.cns)) { 189 switch (le32_to_cpu(cmd->identify.cns)) {
190 case 0x01: 190 case NVME_ID_CNS_CTRL:
191 req->execute = 191 req->execute =
192 nvmet_execute_identify_disc_ctrl; 192 nvmet_execute_identify_disc_ctrl;
193 return 0; 193 return 0;
diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c
index 2cb7315e26d0..653707996342 100644
--- a/drivers/pci/host/pci-layerscape.c
+++ b/drivers/pci/host/pci-layerscape.c
@@ -247,6 +247,7 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
247 247
248 pp = &pcie->pp; 248 pp = &pcie->pp;
249 pp->dev = dev; 249 pp->dev = dev;
250 pcie->drvdata = match->data;
250 pp->ops = pcie->drvdata->ops; 251 pp->ops = pcie->drvdata->ops;
251 252
252 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); 253 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
@@ -256,7 +257,6 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
256 return PTR_ERR(pcie->pp.dbi_base); 257 return PTR_ERR(pcie->pp.dbi_base);
257 } 258 }
258 259
259 pcie->drvdata = match->data;
260 pcie->lut = pcie->pp.dbi_base + pcie->drvdata->lut_offset; 260 pcie->lut = pcie->pp.dbi_base + pcie->drvdata->lut_offset;
261 261
262 if (!ls_pcie_is_bridge(pcie)) 262 if (!ls_pcie_is_bridge(pcie))
diff --git a/drivers/pci/host/pcie-designware-plat.c b/drivers/pci/host/pcie-designware-plat.c
index 537f58a664fa..8df6312ed300 100644
--- a/drivers/pci/host/pcie-designware-plat.c
+++ b/drivers/pci/host/pcie-designware-plat.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com) 4 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
5 * 5 *
6 * Authors: Joao Pinto <jpinto@synopsys.com> 6 * Authors: Joao Pinto <jpmpinto@gmail.com>
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/drivers/perf/xgene_pmu.c b/drivers/perf/xgene_pmu.c
index c2ac7646b99f..a8ac4bcef2c0 100644
--- a/drivers/perf/xgene_pmu.c
+++ b/drivers/perf/xgene_pmu.c
@@ -1011,7 +1011,7 @@ xgene_pmu_dev_ctx *acpi_get_pmu_hw_inf(struct xgene_pmu *xgene_pmu,
1011 rc = acpi_dev_get_resources(adev, &resource_list, 1011 rc = acpi_dev_get_resources(adev, &resource_list,
1012 acpi_pmu_dev_add_resource, &res); 1012 acpi_pmu_dev_add_resource, &res);
1013 acpi_dev_free_resource_list(&resource_list); 1013 acpi_dev_free_resource_list(&resource_list);
1014 if (rc < 0 || IS_ERR(&res)) { 1014 if (rc < 0) {
1015 dev_err(dev, "PMU type %d: No resource address found\n", type); 1015 dev_err(dev, "PMU type %d: No resource address found\n", type);
1016 goto err; 1016 goto err;
1017 } 1017 }
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
index e1ab864e1a7f..c8c72e8259d3 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
@@ -151,21 +151,21 @@ FUNC_GROUP_DECL(GPID0, F19, E21);
151 151
152#define GPID2_DESC SIG_DESC_SET(SCU8C, 9) 152#define GPID2_DESC SIG_DESC_SET(SCU8C, 9)
153 153
154#define D20 26 154#define F20 26
155SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC); 155SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC);
156SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC); 156SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC);
157SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC); 157SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC);
158SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID); 158SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID);
159MS_PIN_DECL(D20, GPIOD2, SD2DAT0, GPID2IN); 159MS_PIN_DECL(F20, GPIOD2, SD2DAT0, GPID2IN);
160 160
161#define D21 27 161#define D20 27
162SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC); 162SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC);
163SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC); 163SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC);
164SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC); 164SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC);
165SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID); 165SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID);
166MS_PIN_DECL(D21, GPIOD3, SD2DAT1, GPID2OUT); 166MS_PIN_DECL(D20, GPIOD3, SD2DAT1, GPID2OUT);
167 167
168FUNC_GROUP_DECL(GPID2, D20, D21); 168FUNC_GROUP_DECL(GPID2, F20, D20);
169 169
170#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 21) 170#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 21)
171#define GPIE0_DESC SIG_DESC_SET(SCU8C, 12) 171#define GPIE0_DESC SIG_DESC_SET(SCU8C, 12)
@@ -182,28 +182,88 @@ SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17));
182SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC); 182SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC);
183SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC); 183SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC);
184SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE); 184SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE);
185MS_PIN_DECL(C20, GPIE0, NDCD3, GPIE0OUT); 185MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT);
186 186
187FUNC_GROUP_DECL(GPIE0, B20, C20); 187FUNC_GROUP_DECL(GPIE0, B20, C20);
188 188
189#define SPI1_DESC SIG_DESC_SET(HW_STRAP1, 13) 189#define SPI1_DESC { HW_STRAP1, GENMASK(13, 12), 1, 0 }
190#define SPI1DEBUG_DESC { HW_STRAP1, GENMASK(13, 12), 2, 0 }
191#define SPI1PASSTHRU_DESC { HW_STRAP1, GENMASK(13, 12), 3, 0 }
192
190#define C18 64 193#define C18 64
191SIG_EXPR_LIST_DECL_SINGLE(SYSCS, SPI1, COND1, SPI1_DESC); 194SIG_EXPR_DECL(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
195SIG_EXPR_DECL(SYSCS, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
196SIG_EXPR_LIST_DECL_DUAL(SYSCS, SPI1DEBUG, SPI1PASSTHRU);
192SS_PIN_DECL(C18, GPIOI0, SYSCS); 197SS_PIN_DECL(C18, GPIOI0, SYSCS);
193 198
194#define E15 65 199#define E15 65
195SIG_EXPR_LIST_DECL_SINGLE(SYSCK, SPI1, COND1, SPI1_DESC); 200SIG_EXPR_DECL(SYSCK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
201SIG_EXPR_DECL(SYSCK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
202SIG_EXPR_LIST_DECL_DUAL(SYSCK, SPI1DEBUG, SPI1PASSTHRU);
196SS_PIN_DECL(E15, GPIOI1, SYSCK); 203SS_PIN_DECL(E15, GPIOI1, SYSCK);
197 204
198#define A14 66 205#define B16 66
199SIG_EXPR_LIST_DECL_SINGLE(SYSMOSI, SPI1, COND1, SPI1_DESC); 206SIG_EXPR_DECL(SYSMOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
200SS_PIN_DECL(A14, GPIOI2, SYSMOSI); 207SIG_EXPR_DECL(SYSMOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
208SIG_EXPR_LIST_DECL_DUAL(SYSMOSI, SPI1DEBUG, SPI1PASSTHRU);
209SS_PIN_DECL(B16, GPIOI2, SYSMOSI);
201 210
202#define C16 67 211#define C16 67
203SIG_EXPR_LIST_DECL_SINGLE(SYSMISO, SPI1, COND1, SPI1_DESC); 212SIG_EXPR_DECL(SYSMISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
213SIG_EXPR_DECL(SYSMISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
214SIG_EXPR_LIST_DECL_DUAL(SYSMISO, SPI1DEBUG, SPI1PASSTHRU);
204SS_PIN_DECL(C16, GPIOI3, SYSMISO); 215SS_PIN_DECL(C16, GPIOI3, SYSMISO);
205 216
206FUNC_GROUP_DECL(SPI1, C18, E15, A14, C16); 217#define VB_DESC SIG_DESC_SET(HW_STRAP1, 5)
218
219#define B15 68
220SIG_EXPR_DECL(SPI1CS0, SPI1, COND1, SPI1_DESC);
221SIG_EXPR_DECL(SPI1CS0, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
222SIG_EXPR_DECL(SPI1CS0, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
223SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1),
224 SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG),
225 SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU));
226SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOSROM, COND1, VB_DESC);
227MS_PIN_DECL(B15, GPIOI4, SPI1CS0, VBCS);
228
229#define C15 69
230SIG_EXPR_DECL(SPI1CK, SPI1, COND1, SPI1_DESC);
231SIG_EXPR_DECL(SPI1CK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
232SIG_EXPR_DECL(SPI1CK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
233SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1),
234 SIG_EXPR_PTR(SPI1CK, SPI1DEBUG),
235 SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU));
236SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOSROM, COND1, VB_DESC);
237MS_PIN_DECL(C15, GPIOI5, SPI1CK, VBCK);
238
239#define A14 70
240SIG_EXPR_DECL(SPI1MOSI, SPI1, COND1, SPI1_DESC);
241SIG_EXPR_DECL(SPI1MOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
242SIG_EXPR_DECL(SPI1MOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
243SIG_EXPR_LIST_DECL(SPI1MOSI, SIG_EXPR_PTR(SPI1MOSI, SPI1),
244 SIG_EXPR_PTR(SPI1MOSI, SPI1DEBUG),
245 SIG_EXPR_PTR(SPI1MOSI, SPI1PASSTHRU));
246SIG_EXPR_LIST_DECL_SINGLE(VBMOSI, VGABIOSROM, COND1, VB_DESC);
247MS_PIN_DECL(A14, GPIOI6, SPI1MOSI, VBMOSI);
248
249#define A15 71
250SIG_EXPR_DECL(SPI1MISO, SPI1, COND1, SPI1_DESC);
251SIG_EXPR_DECL(SPI1MISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
252SIG_EXPR_DECL(SPI1MISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
253SIG_EXPR_LIST_DECL(SPI1MISO, SIG_EXPR_PTR(SPI1MISO, SPI1),
254 SIG_EXPR_PTR(SPI1MISO, SPI1DEBUG),
255 SIG_EXPR_PTR(SPI1MISO, SPI1PASSTHRU));
256SIG_EXPR_LIST_DECL_SINGLE(VBMISO, VGABIOSROM, COND1, VB_DESC);
257MS_PIN_DECL(A15, GPIOI7, SPI1MISO, VBMISO);
258
259FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15);
260FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15);
261FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15, B16, C16, B15, C15, A14, A15);
262FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15);
263
264#define R2 72
265SIG_EXPR_LIST_DECL_SINGLE(SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8));
266SS_PIN_DECL(R2, GPIOJ0, SGPMCK);
207 267
208#define L2 73 268#define L2 73
209SIG_EXPR_LIST_DECL_SINGLE(SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9)); 269SIG_EXPR_LIST_DECL_SINGLE(SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9));
@@ -580,6 +640,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
580 ASPEED_PINCTRL_PIN(A12), 640 ASPEED_PINCTRL_PIN(A12),
581 ASPEED_PINCTRL_PIN(A13), 641 ASPEED_PINCTRL_PIN(A13),
582 ASPEED_PINCTRL_PIN(A14), 642 ASPEED_PINCTRL_PIN(A14),
643 ASPEED_PINCTRL_PIN(A15),
583 ASPEED_PINCTRL_PIN(A2), 644 ASPEED_PINCTRL_PIN(A2),
584 ASPEED_PINCTRL_PIN(A3), 645 ASPEED_PINCTRL_PIN(A3),
585 ASPEED_PINCTRL_PIN(A4), 646 ASPEED_PINCTRL_PIN(A4),
@@ -592,6 +653,8 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
592 ASPEED_PINCTRL_PIN(B12), 653 ASPEED_PINCTRL_PIN(B12),
593 ASPEED_PINCTRL_PIN(B13), 654 ASPEED_PINCTRL_PIN(B13),
594 ASPEED_PINCTRL_PIN(B14), 655 ASPEED_PINCTRL_PIN(B14),
656 ASPEED_PINCTRL_PIN(B15),
657 ASPEED_PINCTRL_PIN(B16),
595 ASPEED_PINCTRL_PIN(B2), 658 ASPEED_PINCTRL_PIN(B2),
596 ASPEED_PINCTRL_PIN(B20), 659 ASPEED_PINCTRL_PIN(B20),
597 ASPEED_PINCTRL_PIN(B3), 660 ASPEED_PINCTRL_PIN(B3),
@@ -603,6 +666,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
603 ASPEED_PINCTRL_PIN(C12), 666 ASPEED_PINCTRL_PIN(C12),
604 ASPEED_PINCTRL_PIN(C13), 667 ASPEED_PINCTRL_PIN(C13),
605 ASPEED_PINCTRL_PIN(C14), 668 ASPEED_PINCTRL_PIN(C14),
669 ASPEED_PINCTRL_PIN(C15),
606 ASPEED_PINCTRL_PIN(C16), 670 ASPEED_PINCTRL_PIN(C16),
607 ASPEED_PINCTRL_PIN(C18), 671 ASPEED_PINCTRL_PIN(C18),
608 ASPEED_PINCTRL_PIN(C2), 672 ASPEED_PINCTRL_PIN(C2),
@@ -614,7 +678,6 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
614 ASPEED_PINCTRL_PIN(D10), 678 ASPEED_PINCTRL_PIN(D10),
615 ASPEED_PINCTRL_PIN(D2), 679 ASPEED_PINCTRL_PIN(D2),
616 ASPEED_PINCTRL_PIN(D20), 680 ASPEED_PINCTRL_PIN(D20),
617 ASPEED_PINCTRL_PIN(D21),
618 ASPEED_PINCTRL_PIN(D4), 681 ASPEED_PINCTRL_PIN(D4),
619 ASPEED_PINCTRL_PIN(D5), 682 ASPEED_PINCTRL_PIN(D5),
620 ASPEED_PINCTRL_PIN(D6), 683 ASPEED_PINCTRL_PIN(D6),
@@ -630,6 +693,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
630 ASPEED_PINCTRL_PIN(E7), 693 ASPEED_PINCTRL_PIN(E7),
631 ASPEED_PINCTRL_PIN(E9), 694 ASPEED_PINCTRL_PIN(E9),
632 ASPEED_PINCTRL_PIN(F19), 695 ASPEED_PINCTRL_PIN(F19),
696 ASPEED_PINCTRL_PIN(F20),
633 ASPEED_PINCTRL_PIN(F9), 697 ASPEED_PINCTRL_PIN(F9),
634 ASPEED_PINCTRL_PIN(H20), 698 ASPEED_PINCTRL_PIN(H20),
635 ASPEED_PINCTRL_PIN(L1), 699 ASPEED_PINCTRL_PIN(L1),
@@ -691,11 +755,14 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = {
691 ASPEED_PINCTRL_GROUP(RMII2), 755 ASPEED_PINCTRL_GROUP(RMII2),
692 ASPEED_PINCTRL_GROUP(SD1), 756 ASPEED_PINCTRL_GROUP(SD1),
693 ASPEED_PINCTRL_GROUP(SPI1), 757 ASPEED_PINCTRL_GROUP(SPI1),
758 ASPEED_PINCTRL_GROUP(SPI1DEBUG),
759 ASPEED_PINCTRL_GROUP(SPI1PASSTHRU),
694 ASPEED_PINCTRL_GROUP(TIMER4), 760 ASPEED_PINCTRL_GROUP(TIMER4),
695 ASPEED_PINCTRL_GROUP(TIMER5), 761 ASPEED_PINCTRL_GROUP(TIMER5),
696 ASPEED_PINCTRL_GROUP(TIMER6), 762 ASPEED_PINCTRL_GROUP(TIMER6),
697 ASPEED_PINCTRL_GROUP(TIMER7), 763 ASPEED_PINCTRL_GROUP(TIMER7),
698 ASPEED_PINCTRL_GROUP(TIMER8), 764 ASPEED_PINCTRL_GROUP(TIMER8),
765 ASPEED_PINCTRL_GROUP(VGABIOSROM),
699}; 766};
700 767
701static const struct aspeed_pin_function aspeed_g5_functions[] = { 768static const struct aspeed_pin_function aspeed_g5_functions[] = {
@@ -733,11 +800,14 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = {
733 ASPEED_PINCTRL_FUNC(RMII2), 800 ASPEED_PINCTRL_FUNC(RMII2),
734 ASPEED_PINCTRL_FUNC(SD1), 801 ASPEED_PINCTRL_FUNC(SD1),
735 ASPEED_PINCTRL_FUNC(SPI1), 802 ASPEED_PINCTRL_FUNC(SPI1),
803 ASPEED_PINCTRL_FUNC(SPI1DEBUG),
804 ASPEED_PINCTRL_FUNC(SPI1PASSTHRU),
736 ASPEED_PINCTRL_FUNC(TIMER4), 805 ASPEED_PINCTRL_FUNC(TIMER4),
737 ASPEED_PINCTRL_FUNC(TIMER5), 806 ASPEED_PINCTRL_FUNC(TIMER5),
738 ASPEED_PINCTRL_FUNC(TIMER6), 807 ASPEED_PINCTRL_FUNC(TIMER6),
739 ASPEED_PINCTRL_FUNC(TIMER7), 808 ASPEED_PINCTRL_FUNC(TIMER7),
740 ASPEED_PINCTRL_FUNC(TIMER8), 809 ASPEED_PINCTRL_FUNC(TIMER8),
810 ASPEED_PINCTRL_FUNC(VGABIOSROM),
741}; 811};
742 812
743static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = { 813static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
index 0391f9f13f3e..49aeba912531 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
@@ -166,13 +166,9 @@ static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr,
166 bool enable, struct regmap *map) 166 bool enable, struct regmap *map)
167{ 167{
168 int i; 168 int i;
169 bool ret;
170
171 ret = aspeed_sig_expr_eval(expr, enable, map);
172 if (ret)
173 return ret;
174 169
175 for (i = 0; i < expr->ndescs; i++) { 170 for (i = 0; i < expr->ndescs; i++) {
171 bool ret;
176 const struct aspeed_sig_desc *desc = &expr->descs[i]; 172 const struct aspeed_sig_desc *desc = &expr->descs[i];
177 u32 pattern = enable ? desc->enable : desc->disable; 173 u32 pattern = enable ? desc->enable : desc->disable;
178 174
@@ -199,12 +195,18 @@ static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr,
199static bool aspeed_sig_expr_enable(const struct aspeed_sig_expr *expr, 195static bool aspeed_sig_expr_enable(const struct aspeed_sig_expr *expr,
200 struct regmap *map) 196 struct regmap *map)
201{ 197{
198 if (aspeed_sig_expr_eval(expr, true, map))
199 return true;
200
202 return aspeed_sig_expr_set(expr, true, map); 201 return aspeed_sig_expr_set(expr, true, map);
203} 202}
204 203
205static bool aspeed_sig_expr_disable(const struct aspeed_sig_expr *expr, 204static bool aspeed_sig_expr_disable(const struct aspeed_sig_expr *expr,
206 struct regmap *map) 205 struct regmap *map)
207{ 206{
207 if (!aspeed_sig_expr_eval(expr, true, map))
208 return true;
209
208 return aspeed_sig_expr_set(expr, false, map); 210 return aspeed_sig_expr_set(expr, false, map);
209} 211}
210 212
diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c
index d22a9fe2e6df..71bbeb9321ba 100644
--- a/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@ -1808,6 +1808,8 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
1808 return PTR_ERR(vg->pctl_dev); 1808 return PTR_ERR(vg->pctl_dev);
1809 } 1809 }
1810 1810
1811 raw_spin_lock_init(&vg->lock);
1812
1811 ret = byt_gpio_probe(vg); 1813 ret = byt_gpio_probe(vg);
1812 if (ret) { 1814 if (ret) {
1813 pinctrl_unregister(vg->pctl_dev); 1815 pinctrl_unregister(vg->pctl_dev);
@@ -1815,7 +1817,6 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
1815 } 1817 }
1816 1818
1817 platform_set_drvdata(pdev, vg); 1819 platform_set_drvdata(pdev, vg);
1818 raw_spin_lock_init(&vg->lock);
1819 pm_runtime_enable(&pdev->dev); 1820 pm_runtime_enable(&pdev->dev);
1820 1821
1821 return 0; 1822 return 0;
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 63387a40b973..01443762e570 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -19,6 +19,7 @@
19#include <linux/pinctrl/pinconf.h> 19#include <linux/pinctrl/pinconf.h>
20#include <linux/pinctrl/pinconf-generic.h> 20#include <linux/pinctrl/pinconf-generic.h>
21 21
22#include "../core.h"
22#include "pinctrl-intel.h" 23#include "pinctrl-intel.h"
23 24
24/* Offset from regs */ 25/* Offset from regs */
@@ -1056,6 +1057,26 @@ int intel_pinctrl_remove(struct platform_device *pdev)
1056EXPORT_SYMBOL_GPL(intel_pinctrl_remove); 1057EXPORT_SYMBOL_GPL(intel_pinctrl_remove);
1057 1058
1058#ifdef CONFIG_PM_SLEEP 1059#ifdef CONFIG_PM_SLEEP
1060static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
1061{
1062 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1063
1064 if (!pd || !intel_pad_usable(pctrl, pin))
1065 return false;
1066
1067 /*
1068 * Only restore the pin if it is actually in use by the kernel (or
1069 * by userspace). It is possible that some pins are used by the
1070 * BIOS during resume and those are not always locked down so leave
1071 * them alone.
1072 */
1073 if (pd->mux_owner || pd->gpio_owner ||
1074 gpiochip_line_is_irq(&pctrl->chip, pin))
1075 return true;
1076
1077 return false;
1078}
1079
1059int intel_pinctrl_suspend(struct device *dev) 1080int intel_pinctrl_suspend(struct device *dev)
1060{ 1081{
1061 struct platform_device *pdev = to_platform_device(dev); 1082 struct platform_device *pdev = to_platform_device(dev);
@@ -1069,7 +1090,7 @@ int intel_pinctrl_suspend(struct device *dev)
1069 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; 1090 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1070 u32 val; 1091 u32 val;
1071 1092
1072 if (!intel_pad_usable(pctrl, desc->number)) 1093 if (!intel_pinctrl_should_save(pctrl, desc->number))
1073 continue; 1094 continue;
1074 1095
1075 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); 1096 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
@@ -1130,7 +1151,7 @@ int intel_pinctrl_resume(struct device *dev)
1130 void __iomem *padcfg; 1151 void __iomem *padcfg;
1131 u32 val; 1152 u32 val;
1132 1153
1133 if (!intel_pad_usable(pctrl, desc->number)) 1154 if (!intel_pinctrl_should_save(pctrl, desc->number))
1134 continue; 1155 continue;
1135 1156
1136 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0); 1157 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
diff --git a/drivers/platform/goldfish/goldfish_pipe.c b/drivers/platform/goldfish/goldfish_pipe.c
index 07462d79d040..1aba2c74160e 100644
--- a/drivers/platform/goldfish/goldfish_pipe.c
+++ b/drivers/platform/goldfish/goldfish_pipe.c
@@ -309,7 +309,8 @@ static ssize_t goldfish_pipe_read_write(struct file *filp, char __user *buffer,
309 * much memory to the process. 309 * much memory to the process.
310 */ 310 */
311 down_read(&current->mm->mmap_sem); 311 down_read(&current->mm->mmap_sem);
312 ret = get_user_pages(address, 1, !is_write, 0, &page, NULL); 312 ret = get_user_pages(address, 1, is_write ? 0 : FOLL_WRITE,
313 &page, NULL);
313 up_read(&current->mm->mmap_sem); 314 up_read(&current->mm->mmap_sem);
314 if (ret < 0) 315 if (ret < 0)
315 break; 316 break;
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index 81b8dcca8891..b8a21d7b25d4 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -576,6 +576,7 @@ config ASUS_WMI
576config ASUS_NB_WMI 576config ASUS_NB_WMI
577 tristate "Asus Notebook WMI Driver" 577 tristate "Asus Notebook WMI Driver"
578 depends on ASUS_WMI 578 depends on ASUS_WMI
579 depends on SERIO_I8042 || SERIO_I8042 = n
579 ---help--- 580 ---help---
580 This is a driver for newer Asus notebooks. It adds extra features 581 This is a driver for newer Asus notebooks. It adds extra features
581 like wireless radio and bluetooth control, leds, hotkeys, backlight... 582 like wireless radio and bluetooth control, leds, hotkeys, backlight...
diff --git a/drivers/platform/x86/ideapad-laptop.c b/drivers/platform/x86/ideapad-laptop.c
index d1a091b93192..a2323941e677 100644
--- a/drivers/platform/x86/ideapad-laptop.c
+++ b/drivers/platform/x86/ideapad-laptop.c
@@ -933,6 +933,13 @@ static const struct dmi_system_id no_hw_rfkill_list[] = {
933 DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo YOGA 900"), 933 DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo YOGA 900"),
934 }, 934 },
935 }, 935 },
936 {
937 .ident = "Lenovo YOGA 910-13IKB",
938 .matches = {
939 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
940 DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo YOGA 910-13IKB"),
941 },
942 },
936 {} 943 {}
937}; 944};
938 945
diff --git a/drivers/rapidio/devices/rio_mport_cdev.c b/drivers/rapidio/devices/rio_mport_cdev.c
index 436dfe871d32..9013a585507e 100644
--- a/drivers/rapidio/devices/rio_mport_cdev.c
+++ b/drivers/rapidio/devices/rio_mport_cdev.c
@@ -892,7 +892,8 @@ rio_dma_transfer(struct file *filp, u32 transfer_mode,
892 down_read(&current->mm->mmap_sem); 892 down_read(&current->mm->mmap_sem);
893 pinned = get_user_pages( 893 pinned = get_user_pages(
894 (unsigned long)xfer->loc_addr & PAGE_MASK, 894 (unsigned long)xfer->loc_addr & PAGE_MASK,
895 nr_pages, dir == DMA_FROM_DEVICE, 0, 895 nr_pages,
896 dir == DMA_FROM_DEVICE ? FOLL_WRITE : 0,
896 page_list, NULL); 897 page_list, NULL);
897 up_read(&current->mm->mmap_sem); 898 up_read(&current->mm->mmap_sem);
898 899
diff --git a/drivers/s390/scsi/zfcp_dbf.c b/drivers/s390/scsi/zfcp_dbf.c
index 637cf8973c9e..581001989937 100644
--- a/drivers/s390/scsi/zfcp_dbf.c
+++ b/drivers/s390/scsi/zfcp_dbf.c
@@ -384,7 +384,7 @@ void zfcp_dbf_san(char *tag, struct zfcp_dbf *dbf,
384 /* if (len > rec_len): 384 /* if (len > rec_len):
385 * dump data up to cap_len ignoring small duplicate in rec->payload 385 * dump data up to cap_len ignoring small duplicate in rec->payload
386 */ 386 */
387 spin_lock_irqsave(&dbf->pay_lock, flags); 387 spin_lock(&dbf->pay_lock);
388 memset(payload, 0, sizeof(*payload)); 388 memset(payload, 0, sizeof(*payload));
389 memcpy(payload->area, paytag, ZFCP_DBF_TAG_LEN); 389 memcpy(payload->area, paytag, ZFCP_DBF_TAG_LEN);
390 payload->fsf_req_id = req_id; 390 payload->fsf_req_id = req_id;
diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c
index a8762a3efeef..532474109624 100644
--- a/drivers/scsi/ipr.c
+++ b/drivers/scsi/ipr.c
@@ -2586,7 +2586,6 @@ static void ipr_process_error(struct ipr_cmnd *ipr_cmd)
2586 struct ipr_hostrcb *hostrcb = ipr_cmd->u.hostrcb; 2586 struct ipr_hostrcb *hostrcb = ipr_cmd->u.hostrcb;
2587 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc); 2587 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
2588 u32 fd_ioasc; 2588 u32 fd_ioasc;
2589 char *envp[] = { "ASYNC_ERR_LOG=1", NULL };
2590 2589
2591 if (ioa_cfg->sis64) 2590 if (ioa_cfg->sis64)
2592 fd_ioasc = be32_to_cpu(hostrcb->hcam.u.error64.fd_ioasc); 2591 fd_ioasc = be32_to_cpu(hostrcb->hcam.u.error64.fd_ioasc);
@@ -2607,8 +2606,8 @@ static void ipr_process_error(struct ipr_cmnd *ipr_cmd)
2607 } 2606 }
2608 2607
2609 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_report_q); 2608 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_report_q);
2609 schedule_work(&ioa_cfg->work_q);
2610 hostrcb = ipr_get_free_hostrcb(ioa_cfg); 2610 hostrcb = ipr_get_free_hostrcb(ioa_cfg);
2611 kobject_uevent_env(&ioa_cfg->host->shost_dev.kobj, KOBJ_CHANGE, envp);
2612 2611
2613 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_LOG_DATA, hostrcb); 2612 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_LOG_DATA, hostrcb);
2614} 2613}
diff --git a/drivers/scsi/scsi_dh.c b/drivers/scsi/scsi_dh.c
index 54d446c9f56e..b8d3b97b217a 100644
--- a/drivers/scsi/scsi_dh.c
+++ b/drivers/scsi/scsi_dh.c
@@ -36,9 +36,9 @@ struct scsi_dh_blist {
36}; 36};
37 37
38static const struct scsi_dh_blist scsi_dh_blist[] = { 38static const struct scsi_dh_blist scsi_dh_blist[] = {
39 {"DGC", "RAID", "clariion" }, 39 {"DGC", "RAID", "emc" },
40 {"DGC", "DISK", "clariion" }, 40 {"DGC", "DISK", "emc" },
41 {"DGC", "VRAID", "clariion" }, 41 {"DGC", "VRAID", "emc" },
42 42
43 {"COMPAQ", "MSA1000 VOLUME", "hp_sw" }, 43 {"COMPAQ", "MSA1000 VOLUME", "hp_sw" },
44 {"COMPAQ", "HSV110", "hp_sw" }, 44 {"COMPAQ", "HSV110", "hp_sw" },
diff --git a/drivers/scsi/scsi_scan.c b/drivers/scsi/scsi_scan.c
index 212e98d940bc..6f7128f49c30 100644
--- a/drivers/scsi/scsi_scan.c
+++ b/drivers/scsi/scsi_scan.c
@@ -1307,7 +1307,6 @@ static void scsi_sequential_lun_scan(struct scsi_target *starget,
1307static int scsi_report_lun_scan(struct scsi_target *starget, int bflags, 1307static int scsi_report_lun_scan(struct scsi_target *starget, int bflags,
1308 enum scsi_scan_mode rescan) 1308 enum scsi_scan_mode rescan)
1309{ 1309{
1310 char devname[64];
1311 unsigned char scsi_cmd[MAX_COMMAND_SIZE]; 1310 unsigned char scsi_cmd[MAX_COMMAND_SIZE];
1312 unsigned int length; 1311 unsigned int length;
1313 u64 lun; 1312 u64 lun;
@@ -1349,9 +1348,6 @@ static int scsi_report_lun_scan(struct scsi_target *starget, int bflags,
1349 } 1348 }
1350 } 1349 }
1351 1350
1352 sprintf(devname, "host %d channel %d id %d",
1353 shost->host_no, sdev->channel, sdev->id);
1354
1355 /* 1351 /*
1356 * Allocate enough to hold the header (the same size as one scsi_lun) 1352 * Allocate enough to hold the header (the same size as one scsi_lun)
1357 * plus the number of luns we are requesting. 511 was the default 1353 * plus the number of luns we are requesting. 511 was the default
@@ -1470,12 +1466,12 @@ retry:
1470 out_err: 1466 out_err:
1471 kfree(lun_data); 1467 kfree(lun_data);
1472 out: 1468 out:
1473 scsi_device_put(sdev);
1474 if (scsi_device_created(sdev)) 1469 if (scsi_device_created(sdev))
1475 /* 1470 /*
1476 * the sdev we used didn't appear in the report luns scan 1471 * the sdev we used didn't appear in the report luns scan
1477 */ 1472 */
1478 __scsi_remove_device(sdev); 1473 __scsi_remove_device(sdev);
1474 scsi_device_put(sdev);
1479 return ret; 1475 return ret;
1480} 1476}
1481 1477
diff --git a/drivers/scsi/st.c b/drivers/scsi/st.c
index 7af5226aa55b..618422ea3a41 100644
--- a/drivers/scsi/st.c
+++ b/drivers/scsi/st.c
@@ -4922,9 +4922,8 @@ static int sgl_map_user_pages(struct st_buffer *STbp,
4922 res = get_user_pages_unlocked( 4922 res = get_user_pages_unlocked(
4923 uaddr, 4923 uaddr,
4924 nr_pages, 4924 nr_pages,
4925 rw == READ, 4925 pages,
4926 0, /* don't force */ 4926 rw == READ ? FOLL_WRITE : 0); /* don't force */
4927 pages);
4928 4927
4929 /* Errors and no page mapped should return here */ 4928 /* Errors and no page mapped should return here */
4930 if (res < nr_pages) 4929 if (res < nr_pages)
diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
index c29040fdf9a7..1091b9f1dd07 100644
--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
@@ -423,8 +423,7 @@ create_pagelist(char __user *buf, size_t count, unsigned short type,
423 actual_pages = get_user_pages(task, task->mm, 423 actual_pages = get_user_pages(task, task->mm,
424 (unsigned long)buf & ~(PAGE_SIZE - 1), 424 (unsigned long)buf & ~(PAGE_SIZE - 1),
425 num_pages, 425 num_pages,
426 (type == PAGELIST_READ) /*Write */ , 426 (type == PAGELIST_READ) ? FOLL_WRITE : 0,
427 0 /*Force */ ,
428 pages, 427 pages,
429 NULL /*vmas */); 428 NULL /*vmas */);
430 up_read(&task->mm->mmap_sem); 429 up_read(&task->mm->mmap_sem);
diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
index e11c0e07471b..7b6cd4d80621 100644
--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
@@ -1477,8 +1477,7 @@ dump_phys_mem(void *virt_addr, uint32_t num_bytes)
1477 current->mm, /* mm */ 1477 current->mm, /* mm */
1478 (unsigned long)virt_addr, /* start */ 1478 (unsigned long)virt_addr, /* start */
1479 num_pages, /* len */ 1479 num_pages, /* len */
1480 0, /* write */ 1480 0, /* gup_flags */
1481 0, /* force */
1482 pages, /* pages (array of page pointers) */ 1481 pages, /* pages (array of page pointers) */
1483 NULL); /* vmas */ 1482 NULL); /* vmas */
1484 up_read(&current->mm->mmap_sem); 1483 up_read(&current->mm->mmap_sem);
diff --git a/drivers/target/iscsi/iscsi_target.c b/drivers/target/iscsi/iscsi_target.c
index 39b928c2849d..b7d747e92c7a 100644
--- a/drivers/target/iscsi/iscsi_target.c
+++ b/drivers/target/iscsi/iscsi_target.c
@@ -1804,6 +1804,10 @@ int iscsit_process_nop_out(struct iscsi_conn *conn, struct iscsi_cmd *cmd,
1804 * Otherwise, initiator is not expecting a NOPIN is response. 1804 * Otherwise, initiator is not expecting a NOPIN is response.
1805 * Just ignore for now. 1805 * Just ignore for now.
1806 */ 1806 */
1807
1808 if (cmd)
1809 iscsit_free_cmd(cmd, false);
1810
1807 return 0; 1811 return 0;
1808} 1812}
1809EXPORT_SYMBOL(iscsit_process_nop_out); 1813EXPORT_SYMBOL(iscsit_process_nop_out);
@@ -2982,7 +2986,7 @@ iscsit_build_nopin_rsp(struct iscsi_cmd *cmd, struct iscsi_conn *conn,
2982 2986
2983 pr_debug("Built NOPIN %s Response ITT: 0x%08x, TTT: 0x%08x," 2987 pr_debug("Built NOPIN %s Response ITT: 0x%08x, TTT: 0x%08x,"
2984 " StatSN: 0x%08x, Length %u\n", (nopout_response) ? 2988 " StatSN: 0x%08x, Length %u\n", (nopout_response) ?
2985 "Solicitied" : "Unsolicitied", cmd->init_task_tag, 2989 "Solicited" : "Unsolicited", cmd->init_task_tag,
2986 cmd->targ_xfer_tag, cmd->stat_sn, cmd->buf_ptr_size); 2990 cmd->targ_xfer_tag, cmd->stat_sn, cmd->buf_ptr_size);
2987} 2991}
2988EXPORT_SYMBOL(iscsit_build_nopin_rsp); 2992EXPORT_SYMBOL(iscsit_build_nopin_rsp);
diff --git a/drivers/target/iscsi/iscsi_target_login.c b/drivers/target/iscsi/iscsi_target_login.c
index adf419fa4291..15f79a2ca34a 100644
--- a/drivers/target/iscsi/iscsi_target_login.c
+++ b/drivers/target/iscsi/iscsi_target_login.c
@@ -434,7 +434,7 @@ static int iscsi_login_zero_tsih_s2(
434 434
435 /* 435 /*
436 * Make MaxRecvDataSegmentLength PAGE_SIZE aligned for 436 * Make MaxRecvDataSegmentLength PAGE_SIZE aligned for
437 * Immediate Data + Unsolicitied Data-OUT if necessary.. 437 * Immediate Data + Unsolicited Data-OUT if necessary..
438 */ 438 */
439 param = iscsi_find_param_from_key("MaxRecvDataSegmentLength", 439 param = iscsi_find_param_from_key("MaxRecvDataSegmentLength",
440 conn->param_list); 440 conn->param_list);
@@ -646,7 +646,7 @@ static void iscsi_post_login_start_timers(struct iscsi_conn *conn)
646{ 646{
647 struct iscsi_session *sess = conn->sess; 647 struct iscsi_session *sess = conn->sess;
648 /* 648 /*
649 * FIXME: Unsolicitied NopIN support for ISER 649 * FIXME: Unsolicited NopIN support for ISER
650 */ 650 */
651 if (conn->conn_transport->transport_type == ISCSI_INFINIBAND) 651 if (conn->conn_transport->transport_type == ISCSI_INFINIBAND)
652 return; 652 return;
diff --git a/drivers/target/target_core_transport.c b/drivers/target/target_core_transport.c
index 6094a6beddde..7dfefd66df93 100644
--- a/drivers/target/target_core_transport.c
+++ b/drivers/target/target_core_transport.c
@@ -754,15 +754,7 @@ EXPORT_SYMBOL(target_complete_cmd);
754 754
755void target_complete_cmd_with_length(struct se_cmd *cmd, u8 scsi_status, int length) 755void target_complete_cmd_with_length(struct se_cmd *cmd, u8 scsi_status, int length)
756{ 756{
757 if (scsi_status != SAM_STAT_GOOD) { 757 if (scsi_status == SAM_STAT_GOOD && length < cmd->data_length) {
758 return;
759 }
760
761 /*
762 * Calculate new residual count based upon length of SCSI data
763 * transferred.
764 */
765 if (length < cmd->data_length) {
766 if (cmd->se_cmd_flags & SCF_UNDERFLOW_BIT) { 758 if (cmd->se_cmd_flags & SCF_UNDERFLOW_BIT) {
767 cmd->residual_count += cmd->data_length - length; 759 cmd->residual_count += cmd->data_length - length;
768 } else { 760 } else {
@@ -771,12 +763,6 @@ void target_complete_cmd_with_length(struct se_cmd *cmd, u8 scsi_status, int len
771 } 763 }
772 764
773 cmd->data_length = length; 765 cmd->data_length = length;
774 } else if (length > cmd->data_length) {
775 cmd->se_cmd_flags |= SCF_OVERFLOW_BIT;
776 cmd->residual_count = length - cmd->data_length;
777 } else {
778 cmd->se_cmd_flags &= ~(SCF_OVERFLOW_BIT | SCF_UNDERFLOW_BIT);
779 cmd->residual_count = 0;
780 } 766 }
781 767
782 target_complete_cmd(cmd, scsi_status); 768 target_complete_cmd(cmd, scsi_status);
@@ -1706,6 +1692,7 @@ void transport_generic_request_failure(struct se_cmd *cmd,
1706 case TCM_LOGICAL_BLOCK_GUARD_CHECK_FAILED: 1692 case TCM_LOGICAL_BLOCK_GUARD_CHECK_FAILED:
1707 case TCM_LOGICAL_BLOCK_APP_TAG_CHECK_FAILED: 1693 case TCM_LOGICAL_BLOCK_APP_TAG_CHECK_FAILED:
1708 case TCM_LOGICAL_BLOCK_REF_TAG_CHECK_FAILED: 1694 case TCM_LOGICAL_BLOCK_REF_TAG_CHECK_FAILED:
1695 case TCM_COPY_TARGET_DEVICE_NOT_REACHABLE:
1709 break; 1696 break;
1710 case TCM_OUT_OF_RESOURCES: 1697 case TCM_OUT_OF_RESOURCES:
1711 sense_reason = TCM_LOGICAL_UNIT_COMMUNICATION_FAILURE; 1698 sense_reason = TCM_LOGICAL_UNIT_COMMUNICATION_FAILURE;
@@ -2547,8 +2534,12 @@ int target_get_sess_cmd(struct se_cmd *se_cmd, bool ack_kref)
2547 * fabric acknowledgement that requires two target_put_sess_cmd() 2534 * fabric acknowledgement that requires two target_put_sess_cmd()
2548 * invocations before se_cmd descriptor release. 2535 * invocations before se_cmd descriptor release.
2549 */ 2536 */
2550 if (ack_kref) 2537 if (ack_kref) {
2551 kref_get(&se_cmd->cmd_kref); 2538 if (!kref_get_unless_zero(&se_cmd->cmd_kref))
2539 return -EINVAL;
2540
2541 se_cmd->se_cmd_flags |= SCF_ACK_KREF;
2542 }
2552 2543
2553 spin_lock_irqsave(&se_sess->sess_cmd_lock, flags); 2544 spin_lock_irqsave(&se_sess->sess_cmd_lock, flags);
2554 if (se_sess->sess_tearing_down) { 2545 if (se_sess->sess_tearing_down) {
@@ -2627,7 +2618,7 @@ EXPORT_SYMBOL(target_put_sess_cmd);
2627 */ 2618 */
2628void target_sess_cmd_list_set_waiting(struct se_session *se_sess) 2619void target_sess_cmd_list_set_waiting(struct se_session *se_sess)
2629{ 2620{
2630 struct se_cmd *se_cmd; 2621 struct se_cmd *se_cmd, *tmp_cmd;
2631 unsigned long flags; 2622 unsigned long flags;
2632 int rc; 2623 int rc;
2633 2624
@@ -2639,14 +2630,16 @@ void target_sess_cmd_list_set_waiting(struct se_session *se_sess)
2639 se_sess->sess_tearing_down = 1; 2630 se_sess->sess_tearing_down = 1;
2640 list_splice_init(&se_sess->sess_cmd_list, &se_sess->sess_wait_list); 2631 list_splice_init(&se_sess->sess_cmd_list, &se_sess->sess_wait_list);
2641 2632
2642 list_for_each_entry(se_cmd, &se_sess->sess_wait_list, se_cmd_list) { 2633 list_for_each_entry_safe(se_cmd, tmp_cmd,
2634 &se_sess->sess_wait_list, se_cmd_list) {
2643 rc = kref_get_unless_zero(&se_cmd->cmd_kref); 2635 rc = kref_get_unless_zero(&se_cmd->cmd_kref);
2644 if (rc) { 2636 if (rc) {
2645 se_cmd->cmd_wait_set = 1; 2637 se_cmd->cmd_wait_set = 1;
2646 spin_lock(&se_cmd->t_state_lock); 2638 spin_lock(&se_cmd->t_state_lock);
2647 se_cmd->transport_state |= CMD_T_FABRIC_STOP; 2639 se_cmd->transport_state |= CMD_T_FABRIC_STOP;
2648 spin_unlock(&se_cmd->t_state_lock); 2640 spin_unlock(&se_cmd->t_state_lock);
2649 } 2641 } else
2642 list_del_init(&se_cmd->se_cmd_list);
2650 } 2643 }
2651 2644
2652 spin_unlock_irqrestore(&se_sess->sess_cmd_lock, flags); 2645 spin_unlock_irqrestore(&se_sess->sess_cmd_lock, flags);
@@ -2871,6 +2864,12 @@ static const struct sense_info sense_info_table[] = {
2871 .ascq = 0x03, /* LOGICAL BLOCK REFERENCE TAG CHECK FAILED */ 2864 .ascq = 0x03, /* LOGICAL BLOCK REFERENCE TAG CHECK FAILED */
2872 .add_sector_info = true, 2865 .add_sector_info = true,
2873 }, 2866 },
2867 [TCM_COPY_TARGET_DEVICE_NOT_REACHABLE] = {
2868 .key = COPY_ABORTED,
2869 .asc = 0x0d,
2870 .ascq = 0x02, /* COPY TARGET DEVICE NOT REACHABLE */
2871
2872 },
2874 [TCM_LOGICAL_UNIT_COMMUNICATION_FAILURE] = { 2873 [TCM_LOGICAL_UNIT_COMMUNICATION_FAILURE] = {
2875 /* 2874 /*
2876 * Returning ILLEGAL REQUEST would cause immediate IO errors on 2875 * Returning ILLEGAL REQUEST would cause immediate IO errors on
diff --git a/drivers/target/target_core_user.c b/drivers/target/target_core_user.c
index 62bf4fe5704a..47562509b489 100644
--- a/drivers/target/target_core_user.c
+++ b/drivers/target/target_core_user.c
@@ -96,7 +96,7 @@ struct tcmu_dev {
96 size_t dev_size; 96 size_t dev_size;
97 u32 cmdr_size; 97 u32 cmdr_size;
98 u32 cmdr_last_cleaned; 98 u32 cmdr_last_cleaned;
99 /* Offset of data ring from start of mb */ 99 /* Offset of data area from start of mb */
100 /* Must add data_off and mb_addr to get the address */ 100 /* Must add data_off and mb_addr to get the address */
101 size_t data_off; 101 size_t data_off;
102 size_t data_size; 102 size_t data_size;
@@ -349,7 +349,7 @@ static inline size_t spc_bitmap_free(unsigned long *bitmap)
349 349
350/* 350/*
351 * We can't queue a command until we have space available on the cmd ring *and* 351 * We can't queue a command until we have space available on the cmd ring *and*
352 * space available on the data ring. 352 * space available on the data area.
353 * 353 *
354 * Called with ring lock held. 354 * Called with ring lock held.
355 */ 355 */
@@ -389,7 +389,8 @@ static bool is_ring_space_avail(struct tcmu_dev *udev, size_t cmd_size, size_t d
389 return true; 389 return true;
390} 390}
391 391
392static int tcmu_queue_cmd_ring(struct tcmu_cmd *tcmu_cmd) 392static sense_reason_t
393tcmu_queue_cmd_ring(struct tcmu_cmd *tcmu_cmd)
393{ 394{
394 struct tcmu_dev *udev = tcmu_cmd->tcmu_dev; 395 struct tcmu_dev *udev = tcmu_cmd->tcmu_dev;
395 struct se_cmd *se_cmd = tcmu_cmd->se_cmd; 396 struct se_cmd *se_cmd = tcmu_cmd->se_cmd;
@@ -405,7 +406,7 @@ static int tcmu_queue_cmd_ring(struct tcmu_cmd *tcmu_cmd)
405 DECLARE_BITMAP(old_bitmap, DATA_BLOCK_BITS); 406 DECLARE_BITMAP(old_bitmap, DATA_BLOCK_BITS);
406 407
407 if (test_bit(TCMU_DEV_BIT_BROKEN, &udev->flags)) 408 if (test_bit(TCMU_DEV_BIT_BROKEN, &udev->flags))
408 return -EINVAL; 409 return TCM_LOGICAL_UNIT_COMMUNICATION_FAILURE;
409 410
410 /* 411 /*
411 * Must be a certain minimum size for response sense info, but 412 * Must be a certain minimum size for response sense info, but
@@ -432,11 +433,14 @@ static int tcmu_queue_cmd_ring(struct tcmu_cmd *tcmu_cmd)
432 BUG_ON(!(se_cmd->t_bidi_data_sg && se_cmd->t_bidi_data_nents)); 433 BUG_ON(!(se_cmd->t_bidi_data_sg && se_cmd->t_bidi_data_nents));
433 data_length += se_cmd->t_bidi_data_sg->length; 434 data_length += se_cmd->t_bidi_data_sg->length;
434 } 435 }
435 if ((command_size > (udev->cmdr_size / 2)) 436 if ((command_size > (udev->cmdr_size / 2)) ||
436 || data_length > udev->data_size) 437 data_length > udev->data_size) {
437 pr_warn("TCMU: Request of size %zu/%zu may be too big for %u/%zu " 438 pr_warn("TCMU: Request of size %zu/%zu is too big for %u/%zu "
438 "cmd/data ring buffers\n", command_size, data_length, 439 "cmd ring/data area\n", command_size, data_length,
439 udev->cmdr_size, udev->data_size); 440 udev->cmdr_size, udev->data_size);
441 spin_unlock_irq(&udev->cmdr_lock);
442 return TCM_INVALID_CDB_FIELD;
443 }
440 444
441 while (!is_ring_space_avail(udev, command_size, data_length)) { 445 while (!is_ring_space_avail(udev, command_size, data_length)) {
442 int ret; 446 int ret;
@@ -450,7 +454,7 @@ static int tcmu_queue_cmd_ring(struct tcmu_cmd *tcmu_cmd)
450 finish_wait(&udev->wait_cmdr, &__wait); 454 finish_wait(&udev->wait_cmdr, &__wait);
451 if (!ret) { 455 if (!ret) {
452 pr_warn("tcmu: command timed out\n"); 456 pr_warn("tcmu: command timed out\n");
453 return -ETIMEDOUT; 457 return TCM_LOGICAL_UNIT_COMMUNICATION_FAILURE;
454 } 458 }
455 459
456 spin_lock_irq(&udev->cmdr_lock); 460 spin_lock_irq(&udev->cmdr_lock);
@@ -487,9 +491,7 @@ static int tcmu_queue_cmd_ring(struct tcmu_cmd *tcmu_cmd)
487 491
488 bitmap_copy(old_bitmap, udev->data_bitmap, DATA_BLOCK_BITS); 492 bitmap_copy(old_bitmap, udev->data_bitmap, DATA_BLOCK_BITS);
489 493
490 /* 494 /* Handle allocating space from the data area */
491 * Fix up iovecs, and handle if allocation in data ring wrapped.
492 */
493 iov = &entry->req.iov[0]; 495 iov = &entry->req.iov[0];
494 iov_cnt = 0; 496 iov_cnt = 0;
495 copy_to_data_area = (se_cmd->data_direction == DMA_TO_DEVICE 497 copy_to_data_area = (se_cmd->data_direction == DMA_TO_DEVICE
@@ -526,10 +528,11 @@ static int tcmu_queue_cmd_ring(struct tcmu_cmd *tcmu_cmd)
526 mod_timer(&udev->timeout, 528 mod_timer(&udev->timeout,
527 round_jiffies_up(jiffies + msecs_to_jiffies(TCMU_TIME_OUT))); 529 round_jiffies_up(jiffies + msecs_to_jiffies(TCMU_TIME_OUT)));
528 530
529 return 0; 531 return TCM_NO_SENSE;
530} 532}
531 533
532static int tcmu_queue_cmd(struct se_cmd *se_cmd) 534static sense_reason_t
535tcmu_queue_cmd(struct se_cmd *se_cmd)
533{ 536{
534 struct se_device *se_dev = se_cmd->se_dev; 537 struct se_device *se_dev = se_cmd->se_dev;
535 struct tcmu_dev *udev = TCMU_DEV(se_dev); 538 struct tcmu_dev *udev = TCMU_DEV(se_dev);
@@ -538,10 +541,10 @@ static int tcmu_queue_cmd(struct se_cmd *se_cmd)
538 541
539 tcmu_cmd = tcmu_alloc_cmd(se_cmd); 542 tcmu_cmd = tcmu_alloc_cmd(se_cmd);
540 if (!tcmu_cmd) 543 if (!tcmu_cmd)
541 return -ENOMEM; 544 return TCM_LOGICAL_UNIT_COMMUNICATION_FAILURE;
542 545
543 ret = tcmu_queue_cmd_ring(tcmu_cmd); 546 ret = tcmu_queue_cmd_ring(tcmu_cmd);
544 if (ret < 0) { 547 if (ret != TCM_NO_SENSE) {
545 pr_err("TCMU: Could not queue command\n"); 548 pr_err("TCMU: Could not queue command\n");
546 spin_lock_irq(&udev->commands_lock); 549 spin_lock_irq(&udev->commands_lock);
547 idr_remove(&udev->commands, tcmu_cmd->cmd_id); 550 idr_remove(&udev->commands, tcmu_cmd->cmd_id);
@@ -561,7 +564,7 @@ static void tcmu_handle_completion(struct tcmu_cmd *cmd, struct tcmu_cmd_entry *
561 if (test_bit(TCMU_CMD_BIT_EXPIRED, &cmd->flags)) { 564 if (test_bit(TCMU_CMD_BIT_EXPIRED, &cmd->flags)) {
562 /* 565 /*
563 * cmd has been completed already from timeout, just reclaim 566 * cmd has been completed already from timeout, just reclaim
564 * data ring space and free cmd 567 * data area space and free cmd
565 */ 568 */
566 free_data_area(udev, cmd); 569 free_data_area(udev, cmd);
567 570
@@ -1129,20 +1132,9 @@ static sector_t tcmu_get_blocks(struct se_device *dev)
1129} 1132}
1130 1133
1131static sense_reason_t 1134static sense_reason_t
1132tcmu_pass_op(struct se_cmd *se_cmd)
1133{
1134 int ret = tcmu_queue_cmd(se_cmd);
1135
1136 if (ret != 0)
1137 return TCM_LOGICAL_UNIT_COMMUNICATION_FAILURE;
1138 else
1139 return TCM_NO_SENSE;
1140}
1141
1142static sense_reason_t
1143tcmu_parse_cdb(struct se_cmd *cmd) 1135tcmu_parse_cdb(struct se_cmd *cmd)
1144{ 1136{
1145 return passthrough_parse_cdb(cmd, tcmu_pass_op); 1137 return passthrough_parse_cdb(cmd, tcmu_queue_cmd);
1146} 1138}
1147 1139
1148static const struct target_backend_ops tcmu_ops = { 1140static const struct target_backend_ops tcmu_ops = {
diff --git a/drivers/target/target_core_xcopy.c b/drivers/target/target_core_xcopy.c
index 75cd85426ae3..094a1440eacb 100644
--- a/drivers/target/target_core_xcopy.c
+++ b/drivers/target/target_core_xcopy.c
@@ -104,7 +104,7 @@ static int target_xcopy_locate_se_dev_e4(struct se_cmd *se_cmd, struct xcopy_op
104 } 104 }
105 mutex_unlock(&g_device_mutex); 105 mutex_unlock(&g_device_mutex);
106 106
107 pr_err("Unable to locate 0xe4 descriptor for EXTENDED_COPY\n"); 107 pr_debug_ratelimited("Unable to locate 0xe4 descriptor for EXTENDED_COPY\n");
108 return -EINVAL; 108 return -EINVAL;
109} 109}
110 110
@@ -185,7 +185,7 @@ static int target_xcopy_parse_tiddesc_e4(struct se_cmd *se_cmd, struct xcopy_op
185 185
186static int target_xcopy_parse_target_descriptors(struct se_cmd *se_cmd, 186static int target_xcopy_parse_target_descriptors(struct se_cmd *se_cmd,
187 struct xcopy_op *xop, unsigned char *p, 187 struct xcopy_op *xop, unsigned char *p,
188 unsigned short tdll) 188 unsigned short tdll, sense_reason_t *sense_ret)
189{ 189{
190 struct se_device *local_dev = se_cmd->se_dev; 190 struct se_device *local_dev = se_cmd->se_dev;
191 unsigned char *desc = p; 191 unsigned char *desc = p;
@@ -193,6 +193,8 @@ static int target_xcopy_parse_target_descriptors(struct se_cmd *se_cmd,
193 unsigned short start = 0; 193 unsigned short start = 0;
194 bool src = true; 194 bool src = true;
195 195
196 *sense_ret = TCM_INVALID_PARAMETER_LIST;
197
196 if (offset != 0) { 198 if (offset != 0) {
197 pr_err("XCOPY target descriptor list length is not" 199 pr_err("XCOPY target descriptor list length is not"
198 " multiple of %d\n", XCOPY_TARGET_DESC_LEN); 200 " multiple of %d\n", XCOPY_TARGET_DESC_LEN);
@@ -243,9 +245,16 @@ static int target_xcopy_parse_target_descriptors(struct se_cmd *se_cmd,
243 rc = target_xcopy_locate_se_dev_e4(se_cmd, xop, true); 245 rc = target_xcopy_locate_se_dev_e4(se_cmd, xop, true);
244 else 246 else
245 rc = target_xcopy_locate_se_dev_e4(se_cmd, xop, false); 247 rc = target_xcopy_locate_se_dev_e4(se_cmd, xop, false);
246 248 /*
247 if (rc < 0) 249 * If a matching IEEE NAA 0x83 descriptor for the requested device
250 * is not located on this node, return COPY_ABORTED with ASQ/ASQC
251 * 0x0d/0x02 - COPY_TARGET_DEVICE_NOT_REACHABLE to request the
252 * initiator to fall back to normal copy method.
253 */
254 if (rc < 0) {
255 *sense_ret = TCM_COPY_TARGET_DEVICE_NOT_REACHABLE;
248 goto out; 256 goto out;
257 }
249 258
250 pr_debug("XCOPY TGT desc: Source dev: %p NAA IEEE WWN: 0x%16phN\n", 259 pr_debug("XCOPY TGT desc: Source dev: %p NAA IEEE WWN: 0x%16phN\n",
251 xop->src_dev, &xop->src_tid_wwn[0]); 260 xop->src_dev, &xop->src_tid_wwn[0]);
@@ -653,6 +662,7 @@ static int target_xcopy_read_source(
653 rc = target_xcopy_setup_pt_cmd(xpt_cmd, xop, src_dev, &cdb[0], 662 rc = target_xcopy_setup_pt_cmd(xpt_cmd, xop, src_dev, &cdb[0],
654 remote_port, true); 663 remote_port, true);
655 if (rc < 0) { 664 if (rc < 0) {
665 ec_cmd->scsi_status = xpt_cmd->se_cmd.scsi_status;
656 transport_generic_free_cmd(se_cmd, 0); 666 transport_generic_free_cmd(se_cmd, 0);
657 return rc; 667 return rc;
658 } 668 }
@@ -664,6 +674,7 @@ static int target_xcopy_read_source(
664 674
665 rc = target_xcopy_issue_pt_cmd(xpt_cmd); 675 rc = target_xcopy_issue_pt_cmd(xpt_cmd);
666 if (rc < 0) { 676 if (rc < 0) {
677 ec_cmd->scsi_status = xpt_cmd->se_cmd.scsi_status;
667 transport_generic_free_cmd(se_cmd, 0); 678 transport_generic_free_cmd(se_cmd, 0);
668 return rc; 679 return rc;
669 } 680 }
@@ -714,6 +725,7 @@ static int target_xcopy_write_destination(
714 remote_port, false); 725 remote_port, false);
715 if (rc < 0) { 726 if (rc < 0) {
716 struct se_cmd *src_cmd = &xop->src_pt_cmd->se_cmd; 727 struct se_cmd *src_cmd = &xop->src_pt_cmd->se_cmd;
728 ec_cmd->scsi_status = xpt_cmd->se_cmd.scsi_status;
717 /* 729 /*
718 * If the failure happened before the t_mem_list hand-off in 730 * If the failure happened before the t_mem_list hand-off in
719 * target_xcopy_setup_pt_cmd(), Reset memory + clear flag so that 731 * target_xcopy_setup_pt_cmd(), Reset memory + clear flag so that
@@ -729,6 +741,7 @@ static int target_xcopy_write_destination(
729 741
730 rc = target_xcopy_issue_pt_cmd(xpt_cmd); 742 rc = target_xcopy_issue_pt_cmd(xpt_cmd);
731 if (rc < 0) { 743 if (rc < 0) {
744 ec_cmd->scsi_status = xpt_cmd->se_cmd.scsi_status;
732 se_cmd->se_cmd_flags &= ~SCF_PASSTHROUGH_SG_TO_MEM_NOALLOC; 745 se_cmd->se_cmd_flags &= ~SCF_PASSTHROUGH_SG_TO_MEM_NOALLOC;
733 transport_generic_free_cmd(se_cmd, 0); 746 transport_generic_free_cmd(se_cmd, 0);
734 return rc; 747 return rc;
@@ -815,9 +828,14 @@ static void target_xcopy_do_work(struct work_struct *work)
815out: 828out:
816 xcopy_pt_undepend_remotedev(xop); 829 xcopy_pt_undepend_remotedev(xop);
817 kfree(xop); 830 kfree(xop);
818 831 /*
819 pr_warn("target_xcopy_do_work: Setting X-COPY CHECK_CONDITION -> sending response\n"); 832 * Don't override an error scsi status if it has already been set
820 ec_cmd->scsi_status = SAM_STAT_CHECK_CONDITION; 833 */
834 if (ec_cmd->scsi_status == SAM_STAT_GOOD) {
835 pr_warn_ratelimited("target_xcopy_do_work: rc: %d, Setting X-COPY"
836 " CHECK_CONDITION -> sending response\n", rc);
837 ec_cmd->scsi_status = SAM_STAT_CHECK_CONDITION;
838 }
821 target_complete_cmd(ec_cmd, SAM_STAT_CHECK_CONDITION); 839 target_complete_cmd(ec_cmd, SAM_STAT_CHECK_CONDITION);
822} 840}
823 841
@@ -875,7 +893,7 @@ sense_reason_t target_do_xcopy(struct se_cmd *se_cmd)
875 " tdll: %hu sdll: %u inline_dl: %u\n", list_id, list_id_usage, 893 " tdll: %hu sdll: %u inline_dl: %u\n", list_id, list_id_usage,
876 tdll, sdll, inline_dl); 894 tdll, sdll, inline_dl);
877 895
878 rc = target_xcopy_parse_target_descriptors(se_cmd, xop, &p[16], tdll); 896 rc = target_xcopy_parse_target_descriptors(se_cmd, xop, &p[16], tdll, &ret);
879 if (rc <= 0) 897 if (rc <= 0)
880 goto out; 898 goto out;
881 899
diff --git a/drivers/target/tcm_fc/tfc_cmd.c b/drivers/target/tcm_fc/tfc_cmd.c
index 216e18cc9133..ff5de9a96643 100644
--- a/drivers/target/tcm_fc/tfc_cmd.c
+++ b/drivers/target/tcm_fc/tfc_cmd.c
@@ -572,10 +572,10 @@ static void ft_send_work(struct work_struct *work)
572 if (target_submit_cmd(&cmd->se_cmd, cmd->sess->se_sess, fcp->fc_cdb, 572 if (target_submit_cmd(&cmd->se_cmd, cmd->sess->se_sess, fcp->fc_cdb,
573 &cmd->ft_sense_buffer[0], scsilun_to_int(&fcp->fc_lun), 573 &cmd->ft_sense_buffer[0], scsilun_to_int(&fcp->fc_lun),
574 ntohl(fcp->fc_dl), task_attr, data_dir, 574 ntohl(fcp->fc_dl), task_attr, data_dir,
575 TARGET_SCF_ACK_KREF)) 575 TARGET_SCF_ACK_KREF | TARGET_SCF_USE_CPUID))
576 goto err; 576 goto err;
577 577
578 pr_debug("r_ctl %x alloc target_submit_cmd\n", fh->fh_r_ctl); 578 pr_debug("r_ctl %x target_submit_cmd %p\n", fh->fh_r_ctl, cmd);
579 return; 579 return;
580 580
581err: 581err:
diff --git a/drivers/target/tcm_fc/tfc_sess.c b/drivers/target/tcm_fc/tfc_sess.c
index 6ffbb603d912..fd5c3de79470 100644
--- a/drivers/target/tcm_fc/tfc_sess.c
+++ b/drivers/target/tcm_fc/tfc_sess.c
@@ -39,6 +39,11 @@
39 39
40#include "tcm_fc.h" 40#include "tcm_fc.h"
41 41
42#define TFC_SESS_DBG(lport, fmt, args...) \
43 pr_debug("host%u: rport %6.6x: " fmt, \
44 (lport)->host->host_no, \
45 (lport)->port_id, ##args )
46
42static void ft_sess_delete_all(struct ft_tport *); 47static void ft_sess_delete_all(struct ft_tport *);
43 48
44/* 49/*
@@ -167,24 +172,29 @@ static struct ft_sess *ft_sess_get(struct fc_lport *lport, u32 port_id)
167 struct ft_tport *tport; 172 struct ft_tport *tport;
168 struct hlist_head *head; 173 struct hlist_head *head;
169 struct ft_sess *sess; 174 struct ft_sess *sess;
175 char *reason = "no session created";
170 176
171 rcu_read_lock(); 177 rcu_read_lock();
172 tport = rcu_dereference(lport->prov[FC_TYPE_FCP]); 178 tport = rcu_dereference(lport->prov[FC_TYPE_FCP]);
173 if (!tport) 179 if (!tport) {
180 reason = "not an FCP port";
174 goto out; 181 goto out;
182 }
175 183
176 head = &tport->hash[ft_sess_hash(port_id)]; 184 head = &tport->hash[ft_sess_hash(port_id)];
177 hlist_for_each_entry_rcu(sess, head, hash) { 185 hlist_for_each_entry_rcu(sess, head, hash) {
178 if (sess->port_id == port_id) { 186 if (sess->port_id == port_id) {
179 kref_get(&sess->kref); 187 kref_get(&sess->kref);
180 rcu_read_unlock(); 188 rcu_read_unlock();
181 pr_debug("port_id %x found %p\n", port_id, sess); 189 TFC_SESS_DBG(lport, "port_id %x found %p\n",
190 port_id, sess);
182 return sess; 191 return sess;
183 } 192 }
184 } 193 }
185out: 194out:
186 rcu_read_unlock(); 195 rcu_read_unlock();
187 pr_debug("port_id %x not found\n", port_id); 196 TFC_SESS_DBG(lport, "port_id %x not found, %s\n",
197 port_id, reason);
188 return NULL; 198 return NULL;
189} 199}
190 200
@@ -195,7 +205,7 @@ static int ft_sess_alloc_cb(struct se_portal_group *se_tpg,
195 struct ft_tport *tport = sess->tport; 205 struct ft_tport *tport = sess->tport;
196 struct hlist_head *head = &tport->hash[ft_sess_hash(sess->port_id)]; 206 struct hlist_head *head = &tport->hash[ft_sess_hash(sess->port_id)];
197 207
198 pr_debug("port_id %x sess %p\n", sess->port_id, sess); 208 TFC_SESS_DBG(tport->lport, "port_id %x sess %p\n", sess->port_id, sess);
199 hlist_add_head_rcu(&sess->hash, head); 209 hlist_add_head_rcu(&sess->hash, head);
200 tport->sess_count++; 210 tport->sess_count++;
201 211
@@ -223,7 +233,7 @@ static struct ft_sess *ft_sess_create(struct ft_tport *tport, u32 port_id,
223 233
224 sess = kzalloc(sizeof(*sess), GFP_KERNEL); 234 sess = kzalloc(sizeof(*sess), GFP_KERNEL);
225 if (!sess) 235 if (!sess)
226 return NULL; 236 return ERR_PTR(-ENOMEM);
227 237
228 kref_init(&sess->kref); /* ref for table entry */ 238 kref_init(&sess->kref); /* ref for table entry */
229 sess->tport = tport; 239 sess->tport = tport;
@@ -234,8 +244,9 @@ static struct ft_sess *ft_sess_create(struct ft_tport *tport, u32 port_id,
234 TARGET_PROT_NORMAL, &initiatorname[0], 244 TARGET_PROT_NORMAL, &initiatorname[0],
235 sess, ft_sess_alloc_cb); 245 sess, ft_sess_alloc_cb);
236 if (IS_ERR(sess->se_sess)) { 246 if (IS_ERR(sess->se_sess)) {
247 int rc = PTR_ERR(sess->se_sess);
237 kfree(sess); 248 kfree(sess);
238 return NULL; 249 sess = ERR_PTR(rc);
239 } 250 }
240 return sess; 251 return sess;
241} 252}
@@ -319,7 +330,7 @@ void ft_sess_close(struct se_session *se_sess)
319 mutex_unlock(&ft_lport_lock); 330 mutex_unlock(&ft_lport_lock);
320 return; 331 return;
321 } 332 }
322 pr_debug("port_id %x\n", port_id); 333 TFC_SESS_DBG(sess->tport->lport, "port_id %x close session\n", port_id);
323 ft_sess_unhash(sess); 334 ft_sess_unhash(sess);
324 mutex_unlock(&ft_lport_lock); 335 mutex_unlock(&ft_lport_lock);
325 ft_close_sess(sess); 336 ft_close_sess(sess);
@@ -379,8 +390,13 @@ static int ft_prli_locked(struct fc_rport_priv *rdata, u32 spp_len,
379 if (!(fcp_parm & FCP_SPPF_INIT_FCN)) 390 if (!(fcp_parm & FCP_SPPF_INIT_FCN))
380 return FC_SPP_RESP_CONF; 391 return FC_SPP_RESP_CONF;
381 sess = ft_sess_create(tport, rdata->ids.port_id, rdata); 392 sess = ft_sess_create(tport, rdata->ids.port_id, rdata);
382 if (!sess) 393 if (IS_ERR(sess)) {
383 return FC_SPP_RESP_RES; 394 if (PTR_ERR(sess) == -EACCES) {
395 spp->spp_flags &= ~FC_SPP_EST_IMG_PAIR;
396 return FC_SPP_RESP_CONF;
397 } else
398 return FC_SPP_RESP_RES;
399 }
384 if (!sess->params) 400 if (!sess->params)
385 rdata->prli_count++; 401 rdata->prli_count++;
386 sess->params = fcp_parm; 402 sess->params = fcp_parm;
@@ -423,8 +439,8 @@ static int ft_prli(struct fc_rport_priv *rdata, u32 spp_len,
423 mutex_lock(&ft_lport_lock); 439 mutex_lock(&ft_lport_lock);
424 ret = ft_prli_locked(rdata, spp_len, rspp, spp); 440 ret = ft_prli_locked(rdata, spp_len, rspp, spp);
425 mutex_unlock(&ft_lport_lock); 441 mutex_unlock(&ft_lport_lock);
426 pr_debug("port_id %x flags %x ret %x\n", 442 TFC_SESS_DBG(rdata->local_port, "port_id %x flags %x ret %x\n",
427 rdata->ids.port_id, rspp ? rspp->spp_flags : 0, ret); 443 rdata->ids.port_id, rspp ? rspp->spp_flags : 0, ret);
428 return ret; 444 return ret;
429} 445}
430 446
@@ -477,11 +493,11 @@ static void ft_recv(struct fc_lport *lport, struct fc_frame *fp)
477 struct ft_sess *sess; 493 struct ft_sess *sess;
478 u32 sid = fc_frame_sid(fp); 494 u32 sid = fc_frame_sid(fp);
479 495
480 pr_debug("sid %x\n", sid); 496 TFC_SESS_DBG(lport, "recv sid %x\n", sid);
481 497
482 sess = ft_sess_get(lport, sid); 498 sess = ft_sess_get(lport, sid);
483 if (!sess) { 499 if (!sess) {
484 pr_debug("sid %x sess lookup failed\n", sid); 500 TFC_SESS_DBG(lport, "sid %x sess lookup failed\n", sid);
485 /* TBD XXX - if FCP_CMND, send PRLO */ 501 /* TBD XXX - if FCP_CMND, send PRLO */
486 fc_frame_free(fp); 502 fc_frame_free(fp);
487 return; 503 return;
diff --git a/drivers/video/fbdev/pvr2fb.c b/drivers/video/fbdev/pvr2fb.c
index 3b1ca4411073..a2564ab91e62 100644
--- a/drivers/video/fbdev/pvr2fb.c
+++ b/drivers/video/fbdev/pvr2fb.c
@@ -686,8 +686,8 @@ static ssize_t pvr2fb_write(struct fb_info *info, const char *buf,
686 if (!pages) 686 if (!pages)
687 return -ENOMEM; 687 return -ENOMEM;
688 688
689 ret = get_user_pages_unlocked((unsigned long)buf, nr_pages, WRITE, 689 ret = get_user_pages_unlocked((unsigned long)buf, nr_pages, pages,
690 0, pages); 690 FOLL_WRITE);
691 691
692 if (ret < nr_pages) { 692 if (ret < nr_pages) {
693 nr_pages = ret; 693 nr_pages = ret;
diff --git a/drivers/virt/fsl_hypervisor.c b/drivers/virt/fsl_hypervisor.c
index 60bdad3a689b..150ce2abf6c8 100644
--- a/drivers/virt/fsl_hypervisor.c
+++ b/drivers/virt/fsl_hypervisor.c
@@ -245,8 +245,8 @@ static long ioctl_memcpy(struct fsl_hv_ioctl_memcpy __user *p)
245 /* Get the physical addresses of the source buffer */ 245 /* Get the physical addresses of the source buffer */
246 down_read(&current->mm->mmap_sem); 246 down_read(&current->mm->mmap_sem);
247 num_pinned = get_user_pages(param.local_vaddr - lb_offset, 247 num_pinned = get_user_pages(param.local_vaddr - lb_offset,
248 num_pages, (param.source == -1) ? READ : WRITE, 248 num_pages, (param.source == -1) ? 0 : FOLL_WRITE,
249 0, pages, NULL); 249 pages, NULL);
250 up_read(&current->mm->mmap_sem); 250 up_read(&current->mm->mmap_sem);
251 251
252 if (num_pinned != num_pages) { 252 if (num_pinned != num_pages) {
diff --git a/drivers/watchdog/sa1100_wdt.c b/drivers/watchdog/sa1100_wdt.c
index e1d39a1e9628..8965e3f536c3 100644
--- a/drivers/watchdog/sa1100_wdt.c
+++ b/drivers/watchdog/sa1100_wdt.c
@@ -22,6 +22,7 @@
22 22
23#include <linux/module.h> 23#include <linux/module.h>
24#include <linux/moduleparam.h> 24#include <linux/moduleparam.h>
25#include <linux/clk.h>
25#include <linux/types.h> 26#include <linux/types.h>
26#include <linux/kernel.h> 27#include <linux/kernel.h>
27#include <linux/fs.h> 28#include <linux/fs.h>
@@ -155,12 +156,27 @@ static struct miscdevice sa1100dog_miscdev = {
155}; 156};
156 157
157static int margin __initdata = 60; /* (secs) Default is 1 minute */ 158static int margin __initdata = 60; /* (secs) Default is 1 minute */
159static struct clk *clk;
158 160
159static int __init sa1100dog_init(void) 161static int __init sa1100dog_init(void)
160{ 162{
161 int ret; 163 int ret;
162 164
163 oscr_freq = get_clock_tick_rate(); 165 clk = clk_get(NULL, "OSTIMER0");
166 if (IS_ERR(clk)) {
167 pr_err("SA1100/PXA2xx Watchdog Timer: clock not found: %d\n",
168 (int) PTR_ERR(clk));
169 return PTR_ERR(clk);
170 }
171
172 ret = clk_prepare_enable(clk);
173 if (ret) {
174 pr_err("SA1100/PXA2xx Watchdog Timer: clock failed to prepare+enable: %d\n",
175 ret);
176 goto err;
177 }
178
179 oscr_freq = clk_get_rate(clk);
164 180
165 /* 181 /*
166 * Read the reset status, and save it for later. If 182 * Read the reset status, and save it for later. If
@@ -176,11 +192,17 @@ static int __init sa1100dog_init(void)
176 pr_info("SA1100/PXA2xx Watchdog Timer: timer margin %d sec\n", 192 pr_info("SA1100/PXA2xx Watchdog Timer: timer margin %d sec\n",
177 margin); 193 margin);
178 return ret; 194 return ret;
195err:
196 clk_disable_unprepare(clk);
197 clk_put(clk);
198 return ret;
179} 199}
180 200
181static void __exit sa1100dog_exit(void) 201static void __exit sa1100dog_exit(void)
182{ 202{
183 misc_deregister(&sa1100dog_miscdev); 203 misc_deregister(&sa1100dog_miscdev);
204 clk_disable_unprepare(clk);
205 clk_put(clk);
184} 206}
185 207
186module_init(sa1100dog_init); 208module_init(sa1100dog_init);
diff --git a/drivers/watchdog/wdat_wdt.c b/drivers/watchdog/wdat_wdt.c
index e473e3b23720..6d1fbda0f461 100644
--- a/drivers/watchdog/wdat_wdt.c
+++ b/drivers/watchdog/wdat_wdt.c
@@ -499,6 +499,10 @@ static int wdat_wdt_resume_noirq(struct device *dev)
499 ret = wdat_wdt_enable_reboot(wdat); 499 ret = wdat_wdt_enable_reboot(wdat);
500 if (ret) 500 if (ret)
501 return ret; 501 return ret;
502
503 ret = wdat_wdt_ping(&wdat->wdd);
504 if (ret)
505 return ret;
502 } 506 }
503 507
504 return wdat_wdt_start(&wdat->wdd); 508 return wdat_wdt_start(&wdat->wdd);
diff --git a/fs/btrfs/compression.c b/fs/btrfs/compression.c
index ccc70d96958d..d4d8b7e36b2f 100644
--- a/fs/btrfs/compression.c
+++ b/fs/btrfs/compression.c
@@ -698,7 +698,7 @@ int btrfs_submit_compressed_read(struct inode *inode, struct bio *bio,
698 698
699 ret = btrfs_map_bio(root, comp_bio, mirror_num, 0); 699 ret = btrfs_map_bio(root, comp_bio, mirror_num, 0);
700 if (ret) { 700 if (ret) {
701 bio->bi_error = ret; 701 comp_bio->bi_error = ret;
702 bio_endio(comp_bio); 702 bio_endio(comp_bio);
703 } 703 }
704 704
@@ -728,7 +728,7 @@ int btrfs_submit_compressed_read(struct inode *inode, struct bio *bio,
728 728
729 ret = btrfs_map_bio(root, comp_bio, mirror_num, 0); 729 ret = btrfs_map_bio(root, comp_bio, mirror_num, 0);
730 if (ret) { 730 if (ret) {
731 bio->bi_error = ret; 731 comp_bio->bi_error = ret;
732 bio_endio(comp_bio); 732 bio_endio(comp_bio);
733 } 733 }
734 734
diff --git a/fs/ceph/file.c b/fs/ceph/file.c
index 7bf08825cc11..18630e800208 100644
--- a/fs/ceph/file.c
+++ b/fs/ceph/file.c
@@ -1272,7 +1272,8 @@ again:
1272 statret = __ceph_do_getattr(inode, page, 1272 statret = __ceph_do_getattr(inode, page,
1273 CEPH_STAT_CAP_INLINE_DATA, !!page); 1273 CEPH_STAT_CAP_INLINE_DATA, !!page);
1274 if (statret < 0) { 1274 if (statret < 0) {
1275 __free_page(page); 1275 if (page)
1276 __free_page(page);
1276 if (statret == -ENODATA) { 1277 if (statret == -ENODATA) {
1277 BUG_ON(retry_op != READ_INLINE); 1278 BUG_ON(retry_op != READ_INLINE);
1278 goto again; 1279 goto again;
diff --git a/fs/ceph/inode.c b/fs/ceph/inode.c
index bca1b49c1c4b..ef4d04647325 100644
--- a/fs/ceph/inode.c
+++ b/fs/ceph/inode.c
@@ -1511,7 +1511,8 @@ int ceph_readdir_prepopulate(struct ceph_mds_request *req,
1511 ceph_fill_dirfrag(d_inode(parent), rinfo->dir_dir); 1511 ceph_fill_dirfrag(d_inode(parent), rinfo->dir_dir);
1512 } 1512 }
1513 1513
1514 if (ceph_frag_is_leftmost(frag) && req->r_readdir_offset == 2) { 1514 if (ceph_frag_is_leftmost(frag) && req->r_readdir_offset == 2 &&
1515 !(rinfo->hash_order && req->r_path2)) {
1515 /* note dir version at start of readdir so we can tell 1516 /* note dir version at start of readdir so we can tell
1516 * if any dentries get dropped */ 1517 * if any dentries get dropped */
1517 req->r_dir_release_cnt = atomic64_read(&ci->i_release_count); 1518 req->r_dir_release_cnt = atomic64_read(&ci->i_release_count);
diff --git a/fs/ceph/super.c b/fs/ceph/super.c
index a29ffce98187..b382e5910eea 100644
--- a/fs/ceph/super.c
+++ b/fs/ceph/super.c
@@ -845,6 +845,8 @@ static struct dentry *ceph_real_mount(struct ceph_fs_client *fsc)
845 err = ceph_fs_debugfs_init(fsc); 845 err = ceph_fs_debugfs_init(fsc);
846 if (err < 0) 846 if (err < 0)
847 goto fail; 847 goto fail;
848 } else {
849 root = dget(fsc->sb->s_root);
848 } 850 }
849 851
850 fsc->mount_state = CEPH_MOUNT_MOUNTED; 852 fsc->mount_state = CEPH_MOUNT_MOUNTED;
diff --git a/fs/ceph/xattr.c b/fs/ceph/xattr.c
index 40b703217977..febc28f9e2c2 100644
--- a/fs/ceph/xattr.c
+++ b/fs/ceph/xattr.c
@@ -16,7 +16,7 @@
16static int __remove_xattr(struct ceph_inode_info *ci, 16static int __remove_xattr(struct ceph_inode_info *ci,
17 struct ceph_inode_xattr *xattr); 17 struct ceph_inode_xattr *xattr);
18 18
19const struct xattr_handler ceph_other_xattr_handler; 19static const struct xattr_handler ceph_other_xattr_handler;
20 20
21/* 21/*
22 * List of handlers for synthetic system.* attributes. Other 22 * List of handlers for synthetic system.* attributes. Other
@@ -1086,7 +1086,7 @@ static int ceph_set_xattr_handler(const struct xattr_handler *handler,
1086 return __ceph_setxattr(inode, name, value, size, flags); 1086 return __ceph_setxattr(inode, name, value, size, flags);
1087} 1087}
1088 1088
1089const struct xattr_handler ceph_other_xattr_handler = { 1089static const struct xattr_handler ceph_other_xattr_handler = {
1090 .prefix = "", /* match any name => handlers called with full name */ 1090 .prefix = "", /* match any name => handlers called with full name */
1091 .get = ceph_get_xattr_handler, 1091 .get = ceph_get_xattr_handler,
1092 .set = ceph_set_xattr_handler, 1092 .set = ceph_set_xattr_handler,
diff --git a/fs/crypto/crypto.c b/fs/crypto/crypto.c
index 61057b7dbddb..98f87fe8f186 100644
--- a/fs/crypto/crypto.c
+++ b/fs/crypto/crypto.c
@@ -151,7 +151,10 @@ static int do_page_crypto(struct inode *inode,
151 struct page *src_page, struct page *dest_page, 151 struct page *src_page, struct page *dest_page,
152 gfp_t gfp_flags) 152 gfp_t gfp_flags)
153{ 153{
154 u8 xts_tweak[FS_XTS_TWEAK_SIZE]; 154 struct {
155 __le64 index;
156 u8 padding[FS_XTS_TWEAK_SIZE - sizeof(__le64)];
157 } xts_tweak;
155 struct skcipher_request *req = NULL; 158 struct skcipher_request *req = NULL;
156 DECLARE_FS_COMPLETION_RESULT(ecr); 159 DECLARE_FS_COMPLETION_RESULT(ecr);
157 struct scatterlist dst, src; 160 struct scatterlist dst, src;
@@ -171,17 +174,15 @@ static int do_page_crypto(struct inode *inode,
171 req, CRYPTO_TFM_REQ_MAY_BACKLOG | CRYPTO_TFM_REQ_MAY_SLEEP, 174 req, CRYPTO_TFM_REQ_MAY_BACKLOG | CRYPTO_TFM_REQ_MAY_SLEEP,
172 page_crypt_complete, &ecr); 175 page_crypt_complete, &ecr);
173 176
174 BUILD_BUG_ON(FS_XTS_TWEAK_SIZE < sizeof(index)); 177 BUILD_BUG_ON(sizeof(xts_tweak) != FS_XTS_TWEAK_SIZE);
175 memcpy(xts_tweak, &index, sizeof(index)); 178 xts_tweak.index = cpu_to_le64(index);
176 memset(&xts_tweak[sizeof(index)], 0, 179 memset(xts_tweak.padding, 0, sizeof(xts_tweak.padding));
177 FS_XTS_TWEAK_SIZE - sizeof(index));
178 180
179 sg_init_table(&dst, 1); 181 sg_init_table(&dst, 1);
180 sg_set_page(&dst, dest_page, PAGE_SIZE, 0); 182 sg_set_page(&dst, dest_page, PAGE_SIZE, 0);
181 sg_init_table(&src, 1); 183 sg_init_table(&src, 1);
182 sg_set_page(&src, src_page, PAGE_SIZE, 0); 184 sg_set_page(&src, src_page, PAGE_SIZE, 0);
183 skcipher_request_set_crypt(req, &src, &dst, PAGE_SIZE, 185 skcipher_request_set_crypt(req, &src, &dst, PAGE_SIZE, &xts_tweak);
184 xts_tweak);
185 if (rw == FS_DECRYPT) 186 if (rw == FS_DECRYPT)
186 res = crypto_skcipher_decrypt(req); 187 res = crypto_skcipher_decrypt(req);
187 else 188 else
diff --git a/fs/crypto/policy.c b/fs/crypto/policy.c
index ed115acb5dee..6865663aac69 100644
--- a/fs/crypto/policy.c
+++ b/fs/crypto/policy.c
@@ -109,6 +109,8 @@ int fscrypt_process_policy(struct file *filp,
109 if (ret) 109 if (ret)
110 return ret; 110 return ret;
111 111
112 inode_lock(inode);
113
112 if (!inode_has_encryption_context(inode)) { 114 if (!inode_has_encryption_context(inode)) {
113 if (!S_ISDIR(inode->i_mode)) 115 if (!S_ISDIR(inode->i_mode))
114 ret = -EINVAL; 116 ret = -EINVAL;
@@ -127,6 +129,8 @@ int fscrypt_process_policy(struct file *filp,
127 ret = -EINVAL; 129 ret = -EINVAL;
128 } 130 }
129 131
132 inode_unlock(inode);
133
130 mnt_drop_write_file(filp); 134 mnt_drop_write_file(filp);
131 return ret; 135 return ret;
132} 136}
diff --git a/fs/exec.c b/fs/exec.c
index 6fcfb3f7b137..4e497b9ee71e 100644
--- a/fs/exec.c
+++ b/fs/exec.c
@@ -191,6 +191,7 @@ static struct page *get_arg_page(struct linux_binprm *bprm, unsigned long pos,
191{ 191{
192 struct page *page; 192 struct page *page;
193 int ret; 193 int ret;
194 unsigned int gup_flags = FOLL_FORCE;
194 195
195#ifdef CONFIG_STACK_GROWSUP 196#ifdef CONFIG_STACK_GROWSUP
196 if (write) { 197 if (write) {
@@ -199,12 +200,16 @@ static struct page *get_arg_page(struct linux_binprm *bprm, unsigned long pos,
199 return NULL; 200 return NULL;
200 } 201 }
201#endif 202#endif
203
204 if (write)
205 gup_flags |= FOLL_WRITE;
206
202 /* 207 /*
203 * We are doing an exec(). 'current' is the process 208 * We are doing an exec(). 'current' is the process
204 * doing the exec and bprm->mm is the new process's mm. 209 * doing the exec and bprm->mm is the new process's mm.
205 */ 210 */
206 ret = get_user_pages_remote(current, bprm->mm, pos, 1, write, 211 ret = get_user_pages_remote(current, bprm->mm, pos, 1, gup_flags,
207 1, &page, NULL); 212 &page, NULL);
208 if (ret <= 0) 213 if (ret <= 0)
209 return NULL; 214 return NULL;
210 215
diff --git a/fs/ext2/inode.c b/fs/ext2/inode.c
index d831e24dc885..41b8b44a391c 100644
--- a/fs/ext2/inode.c
+++ b/fs/ext2/inode.c
@@ -622,7 +622,7 @@ static int ext2_get_blocks(struct inode *inode,
622 u32 *bno, bool *new, bool *boundary, 622 u32 *bno, bool *new, bool *boundary,
623 int create) 623 int create)
624{ 624{
625 int err = -EIO; 625 int err;
626 int offsets[4]; 626 int offsets[4];
627 Indirect chain[4]; 627 Indirect chain[4];
628 Indirect *partial; 628 Indirect *partial;
@@ -639,7 +639,7 @@ static int ext2_get_blocks(struct inode *inode,
639 depth = ext2_block_to_path(inode,iblock,offsets,&blocks_to_boundary); 639 depth = ext2_block_to_path(inode,iblock,offsets,&blocks_to_boundary);
640 640
641 if (depth == 0) 641 if (depth == 0)
642 return (err); 642 return -EIO;
643 643
644 partial = ext2_get_branch(inode, depth, offsets, chain, &err); 644 partial = ext2_get_branch(inode, depth, offsets, chain, &err);
645 /* Simplest case - block found, no allocation needed */ 645 /* Simplest case - block found, no allocation needed */
@@ -761,7 +761,6 @@ static int ext2_get_blocks(struct inode *inode,
761 ext2_splice_branch(inode, iblock, partial, indirect_blks, count); 761 ext2_splice_branch(inode, iblock, partial, indirect_blks, count);
762 mutex_unlock(&ei->truncate_mutex); 762 mutex_unlock(&ei->truncate_mutex);
763got_it: 763got_it:
764 *bno = le32_to_cpu(chain[depth-1].key);
765 if (count > blocks_to_boundary) 764 if (count > blocks_to_boundary)
766 *boundary = true; 765 *boundary = true;
767 err = count; 766 err = count;
@@ -772,6 +771,8 @@ cleanup:
772 brelse(partial->bh); 771 brelse(partial->bh);
773 partial--; 772 partial--;
774 } 773 }
774 if (err > 0)
775 *bno = le32_to_cpu(chain[depth-1].key);
775 return err; 776 return err;
776} 777}
777 778
diff --git a/fs/ext4/block_validity.c b/fs/ext4/block_validity.c
index 02ddec6d8a7d..fdb19543af1e 100644
--- a/fs/ext4/block_validity.c
+++ b/fs/ext4/block_validity.c
@@ -128,12 +128,12 @@ static void debug_print_tree(struct ext4_sb_info *sbi)
128 node = rb_first(&sbi->system_blks); 128 node = rb_first(&sbi->system_blks);
129 while (node) { 129 while (node) {
130 entry = rb_entry(node, struct ext4_system_zone, node); 130 entry = rb_entry(node, struct ext4_system_zone, node);
131 printk("%s%llu-%llu", first ? "" : ", ", 131 printk(KERN_CONT "%s%llu-%llu", first ? "" : ", ",
132 entry->start_blk, entry->start_blk + entry->count - 1); 132 entry->start_blk, entry->start_blk + entry->count - 1);
133 first = 0; 133 first = 0;
134 node = rb_next(node); 134 node = rb_next(node);
135 } 135 }
136 printk("\n"); 136 printk(KERN_CONT "\n");
137} 137}
138 138
139int ext4_setup_system_zone(struct super_block *sb) 139int ext4_setup_system_zone(struct super_block *sb)
diff --git a/fs/ext4/mballoc.h b/fs/ext4/mballoc.h
index 3ef1df6ae9ec..1aba469f8220 100644
--- a/fs/ext4/mballoc.h
+++ b/fs/ext4/mballoc.h
@@ -27,16 +27,15 @@
27#ifdef CONFIG_EXT4_DEBUG 27#ifdef CONFIG_EXT4_DEBUG
28extern ushort ext4_mballoc_debug; 28extern ushort ext4_mballoc_debug;
29 29
30#define mb_debug(n, fmt, a...) \ 30#define mb_debug(n, fmt, ...) \
31 do { \ 31do { \
32 if ((n) <= ext4_mballoc_debug) { \ 32 if ((n) <= ext4_mballoc_debug) { \
33 printk(KERN_DEBUG "(%s, %d): %s: ", \ 33 printk(KERN_DEBUG "(%s, %d): %s: " fmt, \
34 __FILE__, __LINE__, __func__); \ 34 __FILE__, __LINE__, __func__, ##__VA_ARGS__); \
35 printk(fmt, ## a); \ 35 } \
36 } \ 36} while (0)
37 } while (0)
38#else 37#else
39#define mb_debug(n, fmt, a...) no_printk(fmt, ## a) 38#define mb_debug(n, fmt, ...) no_printk(fmt, ##__VA_ARGS__)
40#endif 39#endif
41 40
42#define EXT4_MB_HISTORY_ALLOC 1 /* allocation */ 41#define EXT4_MB_HISTORY_ALLOC 1 /* allocation */
diff --git a/fs/ext4/namei.c b/fs/ext4/namei.c
index f92f10d4f66a..104f8bfba718 100644
--- a/fs/ext4/namei.c
+++ b/fs/ext4/namei.c
@@ -577,12 +577,13 @@ static inline unsigned dx_node_limit(struct inode *dir)
577static void dx_show_index(char * label, struct dx_entry *entries) 577static void dx_show_index(char * label, struct dx_entry *entries)
578{ 578{
579 int i, n = dx_get_count (entries); 579 int i, n = dx_get_count (entries);
580 printk(KERN_DEBUG "%s index ", label); 580 printk(KERN_DEBUG "%s index", label);
581 for (i = 0; i < n; i++) { 581 for (i = 0; i < n; i++) {
582 printk("%x->%lu ", i ? dx_get_hash(entries + i) : 582 printk(KERN_CONT " %x->%lu",
583 0, (unsigned long)dx_get_block(entries + i)); 583 i ? dx_get_hash(entries + i) : 0,
584 (unsigned long)dx_get_block(entries + i));
584 } 585 }
585 printk("\n"); 586 printk(KERN_CONT "\n");
586} 587}
587 588
588struct stats 589struct stats
@@ -679,7 +680,7 @@ static struct stats dx_show_leaf(struct inode *dir,
679 } 680 }
680 de = ext4_next_entry(de, size); 681 de = ext4_next_entry(de, size);
681 } 682 }
682 printk("(%i)\n", names); 683 printk(KERN_CONT "(%i)\n", names);
683 return (struct stats) { names, space, 1 }; 684 return (struct stats) { names, space, 1 };
684} 685}
685 686
@@ -798,7 +799,7 @@ dx_probe(struct ext4_filename *fname, struct inode *dir,
798 q = entries + count - 1; 799 q = entries + count - 1;
799 while (p <= q) { 800 while (p <= q) {
800 m = p + (q - p) / 2; 801 m = p + (q - p) / 2;
801 dxtrace(printk(".")); 802 dxtrace(printk(KERN_CONT "."));
802 if (dx_get_hash(m) > hash) 803 if (dx_get_hash(m) > hash)
803 q = m - 1; 804 q = m - 1;
804 else 805 else
@@ -810,7 +811,7 @@ dx_probe(struct ext4_filename *fname, struct inode *dir,
810 at = entries; 811 at = entries;
811 while (n--) 812 while (n--)
812 { 813 {
813 dxtrace(printk(",")); 814 dxtrace(printk(KERN_CONT ","));
814 if (dx_get_hash(++at) > hash) 815 if (dx_get_hash(++at) > hash)
815 { 816 {
816 at--; 817 at--;
@@ -821,7 +822,8 @@ dx_probe(struct ext4_filename *fname, struct inode *dir,
821 } 822 }
822 823
823 at = p - 1; 824 at = p - 1;
824 dxtrace(printk(" %x->%u\n", at == entries ? 0 : dx_get_hash(at), 825 dxtrace(printk(KERN_CONT " %x->%u\n",
826 at == entries ? 0 : dx_get_hash(at),
825 dx_get_block(at))); 827 dx_get_block(at)));
826 frame->entries = entries; 828 frame->entries = entries;
827 frame->at = at; 829 frame->at = at;
diff --git a/fs/ext4/super.c b/fs/ext4/super.c
index 6db81fbcbaa6..20da99da0a34 100644
--- a/fs/ext4/super.c
+++ b/fs/ext4/super.c
@@ -597,14 +597,15 @@ void __ext4_std_error(struct super_block *sb, const char *function,
597void __ext4_abort(struct super_block *sb, const char *function, 597void __ext4_abort(struct super_block *sb, const char *function,
598 unsigned int line, const char *fmt, ...) 598 unsigned int line, const char *fmt, ...)
599{ 599{
600 struct va_format vaf;
600 va_list args; 601 va_list args;
601 602
602 save_error_info(sb, function, line); 603 save_error_info(sb, function, line);
603 va_start(args, fmt); 604 va_start(args, fmt);
604 printk(KERN_CRIT "EXT4-fs error (device %s): %s:%d: ", sb->s_id, 605 vaf.fmt = fmt;
605 function, line); 606 vaf.va = &args;
606 vprintk(fmt, args); 607 printk(KERN_CRIT "EXT4-fs error (device %s): %s:%d: %pV\n",
607 printk("\n"); 608 sb->s_id, function, line, &vaf);
608 va_end(args); 609 va_end(args);
609 610
610 if ((sb->s_flags & MS_RDONLY) == 0) { 611 if ((sb->s_flags & MS_RDONLY) == 0) {
@@ -2715,12 +2716,12 @@ static void print_daily_error_info(unsigned long arg)
2715 es->s_first_error_func, 2716 es->s_first_error_func,
2716 le32_to_cpu(es->s_first_error_line)); 2717 le32_to_cpu(es->s_first_error_line));
2717 if (es->s_first_error_ino) 2718 if (es->s_first_error_ino)
2718 printk(": inode %u", 2719 printk(KERN_CONT ": inode %u",
2719 le32_to_cpu(es->s_first_error_ino)); 2720 le32_to_cpu(es->s_first_error_ino));
2720 if (es->s_first_error_block) 2721 if (es->s_first_error_block)
2721 printk(": block %llu", (unsigned long long) 2722 printk(KERN_CONT ": block %llu", (unsigned long long)
2722 le64_to_cpu(es->s_first_error_block)); 2723 le64_to_cpu(es->s_first_error_block));
2723 printk("\n"); 2724 printk(KERN_CONT "\n");
2724 } 2725 }
2725 if (es->s_last_error_time) { 2726 if (es->s_last_error_time) {
2726 printk(KERN_NOTICE "EXT4-fs (%s): last error at time %u: %.*s:%d", 2727 printk(KERN_NOTICE "EXT4-fs (%s): last error at time %u: %.*s:%d",
@@ -2729,12 +2730,12 @@ static void print_daily_error_info(unsigned long arg)
2729 es->s_last_error_func, 2730 es->s_last_error_func,
2730 le32_to_cpu(es->s_last_error_line)); 2731 le32_to_cpu(es->s_last_error_line));
2731 if (es->s_last_error_ino) 2732 if (es->s_last_error_ino)
2732 printk(": inode %u", 2733 printk(KERN_CONT ": inode %u",
2733 le32_to_cpu(es->s_last_error_ino)); 2734 le32_to_cpu(es->s_last_error_ino));
2734 if (es->s_last_error_block) 2735 if (es->s_last_error_block)
2735 printk(": block %llu", (unsigned long long) 2736 printk(KERN_CONT ": block %llu", (unsigned long long)
2736 le64_to_cpu(es->s_last_error_block)); 2737 le64_to_cpu(es->s_last_error_block));
2737 printk("\n"); 2738 printk(KERN_CONT "\n");
2738 } 2739 }
2739 mod_timer(&sbi->s_err_report, jiffies + 24*60*60*HZ); /* Once a day */ 2740 mod_timer(&sbi->s_err_report, jiffies + 24*60*60*HZ); /* Once a day */
2740} 2741}
diff --git a/fs/ext4/sysfs.c b/fs/ext4/sysfs.c
index 73bcfd41f5f2..42145be5c6b4 100644
--- a/fs/ext4/sysfs.c
+++ b/fs/ext4/sysfs.c
@@ -223,14 +223,18 @@ static struct attribute *ext4_attrs[] = {
223EXT4_ATTR_FEATURE(lazy_itable_init); 223EXT4_ATTR_FEATURE(lazy_itable_init);
224EXT4_ATTR_FEATURE(batched_discard); 224EXT4_ATTR_FEATURE(batched_discard);
225EXT4_ATTR_FEATURE(meta_bg_resize); 225EXT4_ATTR_FEATURE(meta_bg_resize);
226#ifdef CONFIG_EXT4_FS_ENCRYPTION
226EXT4_ATTR_FEATURE(encryption); 227EXT4_ATTR_FEATURE(encryption);
228#endif
227EXT4_ATTR_FEATURE(metadata_csum_seed); 229EXT4_ATTR_FEATURE(metadata_csum_seed);
228 230
229static struct attribute *ext4_feat_attrs[] = { 231static struct attribute *ext4_feat_attrs[] = {
230 ATTR_LIST(lazy_itable_init), 232 ATTR_LIST(lazy_itable_init),
231 ATTR_LIST(batched_discard), 233 ATTR_LIST(batched_discard),
232 ATTR_LIST(meta_bg_resize), 234 ATTR_LIST(meta_bg_resize),
235#ifdef CONFIG_EXT4_FS_ENCRYPTION
233 ATTR_LIST(encryption), 236 ATTR_LIST(encryption),
237#endif
234 ATTR_LIST(metadata_csum_seed), 238 ATTR_LIST(metadata_csum_seed),
235 NULL, 239 NULL,
236}; 240};
diff --git a/fs/ext4/xattr.c b/fs/ext4/xattr.c
index c15d63389957..d77be9e9f535 100644
--- a/fs/ext4/xattr.c
+++ b/fs/ext4/xattr.c
@@ -61,18 +61,12 @@
61#include "acl.h" 61#include "acl.h"
62 62
63#ifdef EXT4_XATTR_DEBUG 63#ifdef EXT4_XATTR_DEBUG
64# define ea_idebug(inode, f...) do { \ 64# define ea_idebug(inode, fmt, ...) \
65 printk(KERN_DEBUG "inode %s:%lu: ", \ 65 printk(KERN_DEBUG "inode %s:%lu: " fmt "\n", \
66 inode->i_sb->s_id, inode->i_ino); \ 66 inode->i_sb->s_id, inode->i_ino, ##__VA_ARGS__)
67 printk(f); \ 67# define ea_bdebug(bh, fmt, ...) \
68 printk("\n"); \ 68 printk(KERN_DEBUG "block %pg:%lu: " fmt "\n", \
69 } while (0) 69 bh->b_bdev, (unsigned long)bh->b_blocknr, ##__VA_ARGS__)
70# define ea_bdebug(bh, f...) do { \
71 printk(KERN_DEBUG "block %pg:%lu: ", \
72 bh->b_bdev, (unsigned long) bh->b_blocknr); \
73 printk(f); \
74 printk("\n"); \
75 } while (0)
76#else 70#else
77# define ea_idebug(inode, fmt, ...) no_printk(fmt, ##__VA_ARGS__) 71# define ea_idebug(inode, fmt, ...) no_printk(fmt, ##__VA_ARGS__)
78# define ea_bdebug(bh, fmt, ...) no_printk(fmt, ##__VA_ARGS__) 72# define ea_bdebug(bh, fmt, ...) no_printk(fmt, ##__VA_ARGS__)
@@ -241,7 +235,7 @@ __xattr_check_inode(struct inode *inode, struct ext4_xattr_ibody_header *header,
241 int error = -EFSCORRUPTED; 235 int error = -EFSCORRUPTED;
242 236
243 if (((void *) header >= end) || 237 if (((void *) header >= end) ||
244 (header->h_magic != le32_to_cpu(EXT4_XATTR_MAGIC))) 238 (header->h_magic != cpu_to_le32(EXT4_XATTR_MAGIC)))
245 goto errout; 239 goto errout;
246 error = ext4_xattr_check_names(entry, end, entry); 240 error = ext4_xattr_check_names(entry, end, entry);
247errout: 241errout:
diff --git a/fs/f2fs/gc.c b/fs/f2fs/gc.c
index 93985c64d8a8..6f14ee923acd 100644
--- a/fs/f2fs/gc.c
+++ b/fs/f2fs/gc.c
@@ -852,16 +852,16 @@ static int do_garbage_collect(struct f2fs_sb_info *sbi,
852 852
853 for (segno = start_segno; segno < end_segno; segno++) { 853 for (segno = start_segno; segno < end_segno; segno++) {
854 854
855 if (get_valid_blocks(sbi, segno, 1) == 0 ||
856 unlikely(f2fs_cp_error(sbi)))
857 goto next;
858
859 /* find segment summary of victim */ 855 /* find segment summary of victim */
860 sum_page = find_get_page(META_MAPPING(sbi), 856 sum_page = find_get_page(META_MAPPING(sbi),
861 GET_SUM_BLOCK(sbi, segno)); 857 GET_SUM_BLOCK(sbi, segno));
862 f2fs_bug_on(sbi, !PageUptodate(sum_page));
863 f2fs_put_page(sum_page, 0); 858 f2fs_put_page(sum_page, 0);
864 859
860 if (get_valid_blocks(sbi, segno, 1) == 0 ||
861 !PageUptodate(sum_page) ||
862 unlikely(f2fs_cp_error(sbi)))
863 goto next;
864
865 sum = page_address(sum_page); 865 sum = page_address(sum_page);
866 f2fs_bug_on(sbi, type != GET_SUM_TYPE((&sum->footer))); 866 f2fs_bug_on(sbi, type != GET_SUM_TYPE((&sum->footer)));
867 867
diff --git a/fs/isofs/inode.c b/fs/isofs/inode.c
index ad0c745ebad7..871c8b392099 100644
--- a/fs/isofs/inode.c
+++ b/fs/isofs/inode.c
@@ -687,6 +687,11 @@ static int isofs_fill_super(struct super_block *s, void *data, int silent)
687 pri_bh = NULL; 687 pri_bh = NULL;
688 688
689root_found: 689root_found:
690 /* We don't support read-write mounts */
691 if (!(s->s_flags & MS_RDONLY)) {
692 error = -EACCES;
693 goto out_freebh;
694 }
690 695
691 if (joliet_level && (pri == NULL || !opt.rock)) { 696 if (joliet_level && (pri == NULL || !opt.rock)) {
692 /* This is the case of Joliet with the norock mount flag. 697 /* This is the case of Joliet with the norock mount flag.
@@ -1501,9 +1506,6 @@ struct inode *__isofs_iget(struct super_block *sb,
1501static struct dentry *isofs_mount(struct file_system_type *fs_type, 1506static struct dentry *isofs_mount(struct file_system_type *fs_type,
1502 int flags, const char *dev_name, void *data) 1507 int flags, const char *dev_name, void *data)
1503{ 1508{
1504 /* We don't support read-write mounts */
1505 if (!(flags & MS_RDONLY))
1506 return ERR_PTR(-EACCES);
1507 return mount_bdev(fs_type, flags, dev_name, data, isofs_fill_super); 1509 return mount_bdev(fs_type, flags, dev_name, data, isofs_fill_super);
1508} 1510}
1509 1511
diff --git a/fs/jbd2/transaction.c b/fs/jbd2/transaction.c
index 3d8246a9faa4..e1652665bd93 100644
--- a/fs/jbd2/transaction.c
+++ b/fs/jbd2/transaction.c
@@ -1149,6 +1149,7 @@ int jbd2_journal_get_create_access(handle_t *handle, struct buffer_head *bh)
1149 JBUFFER_TRACE(jh, "file as BJ_Reserved"); 1149 JBUFFER_TRACE(jh, "file as BJ_Reserved");
1150 spin_lock(&journal->j_list_lock); 1150 spin_lock(&journal->j_list_lock);
1151 __jbd2_journal_file_buffer(jh, transaction, BJ_Reserved); 1151 __jbd2_journal_file_buffer(jh, transaction, BJ_Reserved);
1152 spin_unlock(&journal->j_list_lock);
1152 } else if (jh->b_transaction == journal->j_committing_transaction) { 1153 } else if (jh->b_transaction == journal->j_committing_transaction) {
1153 /* first access by this transaction */ 1154 /* first access by this transaction */
1154 jh->b_modified = 0; 1155 jh->b_modified = 0;
@@ -1156,8 +1157,8 @@ int jbd2_journal_get_create_access(handle_t *handle, struct buffer_head *bh)
1156 JBUFFER_TRACE(jh, "set next transaction"); 1157 JBUFFER_TRACE(jh, "set next transaction");
1157 spin_lock(&journal->j_list_lock); 1158 spin_lock(&journal->j_list_lock);
1158 jh->b_next_transaction = transaction; 1159 jh->b_next_transaction = transaction;
1160 spin_unlock(&journal->j_list_lock);
1159 } 1161 }
1160 spin_unlock(&journal->j_list_lock);
1161 jbd_unlock_bh_state(bh); 1162 jbd_unlock_bh_state(bh);
1162 1163
1163 /* 1164 /*
diff --git a/fs/locks.c b/fs/locks.c
index ce93b416b490..22c5b4aa4961 100644
--- a/fs/locks.c
+++ b/fs/locks.c
@@ -1609,6 +1609,7 @@ int fcntl_getlease(struct file *filp)
1609 1609
1610 ctx = smp_load_acquire(&inode->i_flctx); 1610 ctx = smp_load_acquire(&inode->i_flctx);
1611 if (ctx && !list_empty_careful(&ctx->flc_lease)) { 1611 if (ctx && !list_empty_careful(&ctx->flc_lease)) {
1612 percpu_down_read_preempt_disable(&file_rwsem);
1612 spin_lock(&ctx->flc_lock); 1613 spin_lock(&ctx->flc_lock);
1613 time_out_leases(inode, &dispose); 1614 time_out_leases(inode, &dispose);
1614 list_for_each_entry(fl, &ctx->flc_lease, fl_list) { 1615 list_for_each_entry(fl, &ctx->flc_lease, fl_list) {
@@ -1618,6 +1619,8 @@ int fcntl_getlease(struct file *filp)
1618 break; 1619 break;
1619 } 1620 }
1620 spin_unlock(&ctx->flc_lock); 1621 spin_unlock(&ctx->flc_lock);
1622 percpu_up_read_preempt_enable(&file_rwsem);
1623
1621 locks_dispose_list(&dispose); 1624 locks_dispose_list(&dispose);
1622 } 1625 }
1623 return type; 1626 return type;
@@ -2529,11 +2532,14 @@ locks_remove_lease(struct file *filp, struct file_lock_context *ctx)
2529 if (list_empty(&ctx->flc_lease)) 2532 if (list_empty(&ctx->flc_lease))
2530 return; 2533 return;
2531 2534
2535 percpu_down_read_preempt_disable(&file_rwsem);
2532 spin_lock(&ctx->flc_lock); 2536 spin_lock(&ctx->flc_lock);
2533 list_for_each_entry_safe(fl, tmp, &ctx->flc_lease, fl_list) 2537 list_for_each_entry_safe(fl, tmp, &ctx->flc_lease, fl_list)
2534 if (filp == fl->fl_file) 2538 if (filp == fl->fl_file)
2535 lease_modify(fl, F_UNLCK, &dispose); 2539 lease_modify(fl, F_UNLCK, &dispose);
2536 spin_unlock(&ctx->flc_lock); 2540 spin_unlock(&ctx->flc_lock);
2541 percpu_up_read_preempt_enable(&file_rwsem);
2542
2537 locks_dispose_list(&dispose); 2543 locks_dispose_list(&dispose);
2538} 2544}
2539 2545
diff --git a/fs/nfs/blocklayout/blocklayout.c b/fs/nfs/blocklayout/blocklayout.c
index 217847679f0e..2905479f214a 100644
--- a/fs/nfs/blocklayout/blocklayout.c
+++ b/fs/nfs/blocklayout/blocklayout.c
@@ -344,9 +344,10 @@ static void bl_write_cleanup(struct work_struct *work)
344 u64 start = hdr->args.offset & (loff_t)PAGE_MASK; 344 u64 start = hdr->args.offset & (loff_t)PAGE_MASK;
345 u64 end = (hdr->args.offset + hdr->args.count + 345 u64 end = (hdr->args.offset + hdr->args.count +
346 PAGE_SIZE - 1) & (loff_t)PAGE_MASK; 346 PAGE_SIZE - 1) & (loff_t)PAGE_MASK;
347 u64 lwb = hdr->args.offset + hdr->args.count;
347 348
348 ext_tree_mark_written(bl, start >> SECTOR_SHIFT, 349 ext_tree_mark_written(bl, start >> SECTOR_SHIFT,
349 (end - start) >> SECTOR_SHIFT, end); 350 (end - start) >> SECTOR_SHIFT, lwb);
350 } 351 }
351 352
352 pnfs_ld_write_done(hdr); 353 pnfs_ld_write_done(hdr);
diff --git a/fs/nfs/nfs4proc.c b/fs/nfs/nfs4proc.c
index ad917bd72b38..7897826d7c51 100644
--- a/fs/nfs/nfs4proc.c
+++ b/fs/nfs/nfs4proc.c
@@ -1545,7 +1545,7 @@ static int update_open_stateid(struct nfs4_state *state,
1545 struct nfs_client *clp = server->nfs_client; 1545 struct nfs_client *clp = server->nfs_client;
1546 struct nfs_inode *nfsi = NFS_I(state->inode); 1546 struct nfs_inode *nfsi = NFS_I(state->inode);
1547 struct nfs_delegation *deleg_cur; 1547 struct nfs_delegation *deleg_cur;
1548 nfs4_stateid freeme = {0}; 1548 nfs4_stateid freeme = { };
1549 int ret = 0; 1549 int ret = 0;
1550 1550
1551 fmode &= (FMODE_READ|FMODE_WRITE); 1551 fmode &= (FMODE_READ|FMODE_WRITE);
diff --git a/fs/proc/array.c b/fs/proc/array.c
index 89600fd5963d..81818adb8e9e 100644
--- a/fs/proc/array.c
+++ b/fs/proc/array.c
@@ -412,10 +412,11 @@ static int do_task_stat(struct seq_file *m, struct pid_namespace *ns,
412 mm = get_task_mm(task); 412 mm = get_task_mm(task);
413 if (mm) { 413 if (mm) {
414 vsize = task_vsize(mm); 414 vsize = task_vsize(mm);
415 if (permitted) { 415 /*
416 eip = KSTK_EIP(task); 416 * esp and eip are intentionally zeroed out. There is no
417 esp = KSTK_ESP(task); 417 * non-racy way to read them without freezing the task.
418 } 418 * Programs that need reliable values can use ptrace(2).
419 */
419 } 420 }
420 421
421 get_task_comm(tcomm, task); 422 get_task_comm(tcomm, task);
diff --git a/fs/proc/base.c b/fs/proc/base.c
index c2964d890c9a..8e654468ab67 100644
--- a/fs/proc/base.c
+++ b/fs/proc/base.c
@@ -252,7 +252,7 @@ static ssize_t proc_pid_cmdline_read(struct file *file, char __user *buf,
252 * Inherently racy -- command line shares address space 252 * Inherently racy -- command line shares address space
253 * with code and data. 253 * with code and data.
254 */ 254 */
255 rv = access_remote_vm(mm, arg_end - 1, &c, 1, 0); 255 rv = access_remote_vm(mm, arg_end - 1, &c, 1, FOLL_FORCE);
256 if (rv <= 0) 256 if (rv <= 0)
257 goto out_free_page; 257 goto out_free_page;
258 258
@@ -270,7 +270,8 @@ static ssize_t proc_pid_cmdline_read(struct file *file, char __user *buf,
270 int nr_read; 270 int nr_read;
271 271
272 _count = min3(count, len, PAGE_SIZE); 272 _count = min3(count, len, PAGE_SIZE);
273 nr_read = access_remote_vm(mm, p, page, _count, 0); 273 nr_read = access_remote_vm(mm, p, page, _count,
274 FOLL_FORCE);
274 if (nr_read < 0) 275 if (nr_read < 0)
275 rv = nr_read; 276 rv = nr_read;
276 if (nr_read <= 0) 277 if (nr_read <= 0)
@@ -305,7 +306,8 @@ static ssize_t proc_pid_cmdline_read(struct file *file, char __user *buf,
305 bool final; 306 bool final;
306 307
307 _count = min3(count, len, PAGE_SIZE); 308 _count = min3(count, len, PAGE_SIZE);
308 nr_read = access_remote_vm(mm, p, page, _count, 0); 309 nr_read = access_remote_vm(mm, p, page, _count,
310 FOLL_FORCE);
309 if (nr_read < 0) 311 if (nr_read < 0)
310 rv = nr_read; 312 rv = nr_read;
311 if (nr_read <= 0) 313 if (nr_read <= 0)
@@ -354,7 +356,8 @@ skip_argv:
354 bool final; 356 bool final;
355 357
356 _count = min3(count, len, PAGE_SIZE); 358 _count = min3(count, len, PAGE_SIZE);
357 nr_read = access_remote_vm(mm, p, page, _count, 0); 359 nr_read = access_remote_vm(mm, p, page, _count,
360 FOLL_FORCE);
358 if (nr_read < 0) 361 if (nr_read < 0)
359 rv = nr_read; 362 rv = nr_read;
360 if (nr_read <= 0) 363 if (nr_read <= 0)
@@ -832,6 +835,7 @@ static ssize_t mem_rw(struct file *file, char __user *buf,
832 unsigned long addr = *ppos; 835 unsigned long addr = *ppos;
833 ssize_t copied; 836 ssize_t copied;
834 char *page; 837 char *page;
838 unsigned int flags = FOLL_FORCE;
835 839
836 if (!mm) 840 if (!mm)
837 return 0; 841 return 0;
@@ -844,6 +848,9 @@ static ssize_t mem_rw(struct file *file, char __user *buf,
844 if (!atomic_inc_not_zero(&mm->mm_users)) 848 if (!atomic_inc_not_zero(&mm->mm_users))
845 goto free; 849 goto free;
846 850
851 if (write)
852 flags |= FOLL_WRITE;
853
847 while (count > 0) { 854 while (count > 0) {
848 int this_len = min_t(int, count, PAGE_SIZE); 855 int this_len = min_t(int, count, PAGE_SIZE);
849 856
@@ -852,7 +859,7 @@ static ssize_t mem_rw(struct file *file, char __user *buf,
852 break; 859 break;
853 } 860 }
854 861
855 this_len = access_remote_vm(mm, addr, page, this_len, write); 862 this_len = access_remote_vm(mm, addr, page, this_len, flags);
856 if (!this_len) { 863 if (!this_len) {
857 if (!copied) 864 if (!copied)
858 copied = -EIO; 865 copied = -EIO;
@@ -965,7 +972,7 @@ static ssize_t environ_read(struct file *file, char __user *buf,
965 this_len = min(max_len, this_len); 972 this_len = min(max_len, this_len);
966 973
967 retval = access_remote_vm(mm, (env_start + src), 974 retval = access_remote_vm(mm, (env_start + src),
968 page, this_len, 0); 975 page, this_len, FOLL_FORCE);
969 976
970 if (retval <= 0) { 977 if (retval <= 0) {
971 ret = retval; 978 ret = retval;
diff --git a/fs/proc/task_mmu.c b/fs/proc/task_mmu.c
index 6909582ce5e5..35b92d81692f 100644
--- a/fs/proc/task_mmu.c
+++ b/fs/proc/task_mmu.c
@@ -266,24 +266,15 @@ static int do_maps_open(struct inode *inode, struct file *file,
266 * /proc/PID/maps that is the stack of the main task. 266 * /proc/PID/maps that is the stack of the main task.
267 */ 267 */
268static int is_stack(struct proc_maps_private *priv, 268static int is_stack(struct proc_maps_private *priv,
269 struct vm_area_struct *vma, int is_pid) 269 struct vm_area_struct *vma)
270{ 270{
271 int stack = 0; 271 /*
272 272 * We make no effort to guess what a given thread considers to be
273 if (is_pid) { 273 * its "stack". It's not even well-defined for programs written
274 stack = vma->vm_start <= vma->vm_mm->start_stack && 274 * languages like Go.
275 vma->vm_end >= vma->vm_mm->start_stack; 275 */
276 } else { 276 return vma->vm_start <= vma->vm_mm->start_stack &&
277 struct inode *inode = priv->inode; 277 vma->vm_end >= vma->vm_mm->start_stack;
278 struct task_struct *task;
279
280 rcu_read_lock();
281 task = pid_task(proc_pid(inode), PIDTYPE_PID);
282 if (task)
283 stack = vma_is_stack_for_task(vma, task);
284 rcu_read_unlock();
285 }
286 return stack;
287} 278}
288 279
289static void 280static void
@@ -354,7 +345,7 @@ show_map_vma(struct seq_file *m, struct vm_area_struct *vma, int is_pid)
354 goto done; 345 goto done;
355 } 346 }
356 347
357 if (is_stack(priv, vma, is_pid)) 348 if (is_stack(priv, vma))
358 name = "[stack]"; 349 name = "[stack]";
359 } 350 }
360 351
@@ -1669,7 +1660,7 @@ static int show_numa_map(struct seq_file *m, void *v, int is_pid)
1669 seq_file_path(m, file, "\n\t= "); 1660 seq_file_path(m, file, "\n\t= ");
1670 } else if (vma->vm_start <= mm->brk && vma->vm_end >= mm->start_brk) { 1661 } else if (vma->vm_start <= mm->brk && vma->vm_end >= mm->start_brk) {
1671 seq_puts(m, " heap"); 1662 seq_puts(m, " heap");
1672 } else if (is_stack(proc_priv, vma, is_pid)) { 1663 } else if (is_stack(proc_priv, vma)) {
1673 seq_puts(m, " stack"); 1664 seq_puts(m, " stack");
1674 } 1665 }
1675 1666
diff --git a/fs/proc/task_nommu.c b/fs/proc/task_nommu.c
index faacb0c0d857..37175621e890 100644
--- a/fs/proc/task_nommu.c
+++ b/fs/proc/task_nommu.c
@@ -124,25 +124,17 @@ unsigned long task_statm(struct mm_struct *mm,
124} 124}
125 125
126static int is_stack(struct proc_maps_private *priv, 126static int is_stack(struct proc_maps_private *priv,
127 struct vm_area_struct *vma, int is_pid) 127 struct vm_area_struct *vma)
128{ 128{
129 struct mm_struct *mm = vma->vm_mm; 129 struct mm_struct *mm = vma->vm_mm;
130 int stack = 0; 130
131 131 /*
132 if (is_pid) { 132 * We make no effort to guess what a given thread considers to be
133 stack = vma->vm_start <= mm->start_stack && 133 * its "stack". It's not even well-defined for programs written
134 vma->vm_end >= mm->start_stack; 134 * languages like Go.
135 } else { 135 */
136 struct inode *inode = priv->inode; 136 return vma->vm_start <= mm->start_stack &&
137 struct task_struct *task; 137 vma->vm_end >= mm->start_stack;
138
139 rcu_read_lock();
140 task = pid_task(proc_pid(inode), PIDTYPE_PID);
141 if (task)
142 stack = vma_is_stack_for_task(vma, task);
143 rcu_read_unlock();
144 }
145 return stack;
146} 138}
147 139
148/* 140/*
@@ -184,7 +176,7 @@ static int nommu_vma_show(struct seq_file *m, struct vm_area_struct *vma,
184 if (file) { 176 if (file) {
185 seq_pad(m, ' '); 177 seq_pad(m, ' ');
186 seq_file_path(m, file, ""); 178 seq_file_path(m, file, "");
187 } else if (mm && is_stack(priv, vma, is_pid)) { 179 } else if (mm && is_stack(priv, vma)) {
188 seq_pad(m, ' '); 180 seq_pad(m, ' ');
189 seq_printf(m, "[stack]"); 181 seq_printf(m, "[stack]");
190 } 182 }
diff --git a/fs/ubifs/dir.c b/fs/ubifs/dir.c
index c8f60df2733e..bd4a5e8ce441 100644
--- a/fs/ubifs/dir.c
+++ b/fs/ubifs/dir.c
@@ -439,7 +439,7 @@ static unsigned int vfs_dent_type(uint8_t type)
439 */ 439 */
440static int ubifs_readdir(struct file *file, struct dir_context *ctx) 440static int ubifs_readdir(struct file *file, struct dir_context *ctx)
441{ 441{
442 int err; 442 int err = 0;
443 struct qstr nm; 443 struct qstr nm;
444 union ubifs_key key; 444 union ubifs_key key;
445 struct ubifs_dent_node *dent; 445 struct ubifs_dent_node *dent;
@@ -541,14 +541,12 @@ out:
541 kfree(file->private_data); 541 kfree(file->private_data);
542 file->private_data = NULL; 542 file->private_data = NULL;
543 543
544 if (err != -ENOENT) { 544 if (err != -ENOENT)
545 ubifs_err(c, "cannot find next direntry, error %d", err); 545 ubifs_err(c, "cannot find next direntry, error %d", err);
546 return err;
547 }
548 546
549 /* 2 is a special value indicating that there are no more direntries */ 547 /* 2 is a special value indicating that there are no more direntries */
550 ctx->pos = 2; 548 ctx->pos = 2;
551 return 0; 549 return err;
552} 550}
553 551
554/* Free saved readdir() state when the directory is closed */ 552/* Free saved readdir() state when the directory is closed */
@@ -1060,9 +1058,9 @@ static void unlock_4_inodes(struct inode *inode1, struct inode *inode2,
1060 mutex_unlock(&ubifs_inode(inode1)->ui_mutex); 1058 mutex_unlock(&ubifs_inode(inode1)->ui_mutex);
1061} 1059}
1062 1060
1063static int ubifs_rename(struct inode *old_dir, struct dentry *old_dentry, 1061static int do_rename(struct inode *old_dir, struct dentry *old_dentry,
1064 struct inode *new_dir, struct dentry *new_dentry, 1062 struct inode *new_dir, struct dentry *new_dentry,
1065 unsigned int flags) 1063 unsigned int flags)
1066{ 1064{
1067 struct ubifs_info *c = old_dir->i_sb->s_fs_info; 1065 struct ubifs_info *c = old_dir->i_sb->s_fs_info;
1068 struct inode *old_inode = d_inode(old_dentry); 1066 struct inode *old_inode = d_inode(old_dentry);
@@ -1323,7 +1321,7 @@ static int ubifs_xrename(struct inode *old_dir, struct dentry *old_dentry,
1323 return err; 1321 return err;
1324} 1322}
1325 1323
1326static int ubifs_rename2(struct inode *old_dir, struct dentry *old_dentry, 1324static int ubifs_rename(struct inode *old_dir, struct dentry *old_dentry,
1327 struct inode *new_dir, struct dentry *new_dentry, 1325 struct inode *new_dir, struct dentry *new_dentry,
1328 unsigned int flags) 1326 unsigned int flags)
1329{ 1327{
@@ -1336,7 +1334,7 @@ static int ubifs_rename2(struct inode *old_dir, struct dentry *old_dentry,
1336 if (flags & RENAME_EXCHANGE) 1334 if (flags & RENAME_EXCHANGE)
1337 return ubifs_xrename(old_dir, old_dentry, new_dir, new_dentry); 1335 return ubifs_xrename(old_dir, old_dentry, new_dir, new_dentry);
1338 1336
1339 return ubifs_rename(old_dir, old_dentry, new_dir, new_dentry, flags); 1337 return do_rename(old_dir, old_dentry, new_dir, new_dentry, flags);
1340} 1338}
1341 1339
1342int ubifs_getattr(struct vfsmount *mnt, struct dentry *dentry, 1340int ubifs_getattr(struct vfsmount *mnt, struct dentry *dentry,
@@ -1387,7 +1385,7 @@ const struct inode_operations ubifs_dir_inode_operations = {
1387 .mkdir = ubifs_mkdir, 1385 .mkdir = ubifs_mkdir,
1388 .rmdir = ubifs_rmdir, 1386 .rmdir = ubifs_rmdir,
1389 .mknod = ubifs_mknod, 1387 .mknod = ubifs_mknod,
1390 .rename = ubifs_rename2, 1388 .rename = ubifs_rename,
1391 .setattr = ubifs_setattr, 1389 .setattr = ubifs_setattr,
1392 .getattr = ubifs_getattr, 1390 .getattr = ubifs_getattr,
1393 .listxattr = ubifs_listxattr, 1391 .listxattr = ubifs_listxattr,
diff --git a/fs/ubifs/xattr.c b/fs/ubifs/xattr.c
index 6c2f4d41ed73..d9f9615bfd71 100644
--- a/fs/ubifs/xattr.c
+++ b/fs/ubifs/xattr.c
@@ -172,6 +172,7 @@ out_cancel:
172 host_ui->xattr_cnt -= 1; 172 host_ui->xattr_cnt -= 1;
173 host_ui->xattr_size -= CALC_DENT_SIZE(nm->len); 173 host_ui->xattr_size -= CALC_DENT_SIZE(nm->len);
174 host_ui->xattr_size -= CALC_XATTR_BYTES(size); 174 host_ui->xattr_size -= CALC_XATTR_BYTES(size);
175 host_ui->xattr_names -= nm->len;
175 mutex_unlock(&host_ui->ui_mutex); 176 mutex_unlock(&host_ui->ui_mutex);
176out_free: 177out_free:
177 make_bad_inode(inode); 178 make_bad_inode(inode);
@@ -478,6 +479,7 @@ out_cancel:
478 host_ui->xattr_cnt += 1; 479 host_ui->xattr_cnt += 1;
479 host_ui->xattr_size += CALC_DENT_SIZE(nm->len); 480 host_ui->xattr_size += CALC_DENT_SIZE(nm->len);
480 host_ui->xattr_size += CALC_XATTR_BYTES(ui->data_len); 481 host_ui->xattr_size += CALC_XATTR_BYTES(ui->data_len);
482 host_ui->xattr_names += nm->len;
481 mutex_unlock(&host_ui->ui_mutex); 483 mutex_unlock(&host_ui->ui_mutex);
482 ubifs_release_budget(c, &req); 484 ubifs_release_budget(c, &req);
483 make_bad_inode(inode); 485 make_bad_inode(inode);
diff --git a/include/acpi/pcc.h b/include/acpi/pcc.h
index 17a940a14477..8caa79c61703 100644
--- a/include/acpi/pcc.h
+++ b/include/acpi/pcc.h
@@ -21,7 +21,7 @@ extern void pcc_mbox_free_channel(struct mbox_chan *chan);
21static inline struct mbox_chan *pcc_mbox_request_channel(struct mbox_client *cl, 21static inline struct mbox_chan *pcc_mbox_request_channel(struct mbox_client *cl,
22 int subspace_id) 22 int subspace_id)
23{ 23{
24 return NULL; 24 return ERR_PTR(-ENODEV);
25} 25}
26static inline void pcc_mbox_free_channel(struct mbox_chan *chan) { } 26static inline void pcc_mbox_free_channel(struct mbox_chan *chan) { }
27#endif 27#endif
diff --git a/include/clocksource/pxa.h b/include/clocksource/pxa.h
index 1efbe5a66958..a9a0f03024a4 100644
--- a/include/clocksource/pxa.h
+++ b/include/clocksource/pxa.h
@@ -12,7 +12,6 @@
12#ifndef _CLOCKSOURCE_PXA_H 12#ifndef _CLOCKSOURCE_PXA_H
13#define _CLOCKSOURCE_PXA_H 13#define _CLOCKSOURCE_PXA_H
14 14
15extern void pxa_timer_nodt_init(int irq, void __iomem *base, 15extern void pxa_timer_nodt_init(int irq, void __iomem *base);
16 unsigned long clock_tick_rate);
17 16
18#endif 17#endif
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index 5fa55fc56e18..32dc0cbd51ca 100644
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -677,10 +677,10 @@ static inline int cpufreq_table_find_index_dl(struct cpufreq_policy *policy,
677 if (best == table - 1) 677 if (best == table - 1)
678 return pos - table; 678 return pos - table;
679 679
680 return best - pos; 680 return best - table;
681 } 681 }
682 682
683 return best - pos; 683 return best - table;
684} 684}
685 685
686/* Works only on sorted freq-tables */ 686/* Works only on sorted freq-tables */
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 9b207a8c5af3..afe641c02dca 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -81,6 +81,7 @@ enum cpuhp_state {
81 CPUHP_AP_ARM_ARCH_TIMER_STARTING, 81 CPUHP_AP_ARM_ARCH_TIMER_STARTING,
82 CPUHP_AP_ARM_GLOBAL_TIMER_STARTING, 82 CPUHP_AP_ARM_GLOBAL_TIMER_STARTING,
83 CPUHP_AP_DUMMY_TIMER_STARTING, 83 CPUHP_AP_DUMMY_TIMER_STARTING,
84 CPUHP_AP_JCORE_TIMER_STARTING,
84 CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING, 85 CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
85 CPUHP_AP_ARM_TWD_STARTING, 86 CPUHP_AP_ARM_TWD_STARTING,
86 CPUHP_AP_METAG_TIMER_STARTING, 87 CPUHP_AP_METAG_TIMER_STARTING,
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 8361c8d3edd1..b7e34313cdfe 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -290,7 +290,7 @@
290#define GITS_BASER_TYPE_SHIFT (56) 290#define GITS_BASER_TYPE_SHIFT (56)
291#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7) 291#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
292#define GITS_BASER_ENTRY_SIZE_SHIFT (48) 292#define GITS_BASER_ENTRY_SIZE_SHIFT (48)
293#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0xff) + 1) 293#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
294#define GITS_BASER_SHAREABILITY_SHIFT (10) 294#define GITS_BASER_SHAREABILITY_SHIFT (10)
295#define GITS_BASER_InnerShareable \ 295#define GITS_BASER_InnerShareable \
296 GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) 296 GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
diff --git a/include/linux/kasan.h b/include/linux/kasan.h
index d600303306eb..820c0ad54a01 100644
--- a/include/linux/kasan.h
+++ b/include/linux/kasan.h
@@ -44,6 +44,7 @@ static inline void kasan_disable_current(void)
44void kasan_unpoison_shadow(const void *address, size_t size); 44void kasan_unpoison_shadow(const void *address, size_t size);
45 45
46void kasan_unpoison_task_stack(struct task_struct *task); 46void kasan_unpoison_task_stack(struct task_struct *task);
47void kasan_unpoison_stack_above_sp_to(const void *watermark);
47 48
48void kasan_alloc_pages(struct page *page, unsigned int order); 49void kasan_alloc_pages(struct page *page, unsigned int order);
49void kasan_free_pages(struct page *page, unsigned int order); 50void kasan_free_pages(struct page *page, unsigned int order);
@@ -85,6 +86,7 @@ size_t kasan_metadata_size(struct kmem_cache *cache);
85static inline void kasan_unpoison_shadow(const void *address, size_t size) {} 86static inline void kasan_unpoison_shadow(const void *address, size_t size) {}
86 87
87static inline void kasan_unpoison_task_stack(struct task_struct *task) {} 88static inline void kasan_unpoison_task_stack(struct task_struct *task) {}
89static inline void kasan_unpoison_stack_above_sp_to(const void *watermark) {}
88 90
89static inline void kasan_enable_current(void) {} 91static inline void kasan_enable_current(void) {}
90static inline void kasan_disable_current(void) {} 92static inline void kasan_disable_current(void) {}
diff --git a/include/linux/mm.h b/include/linux/mm.h
index e9caec6a51e9..3a191853faaa 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -1266,9 +1266,10 @@ static inline int fixup_user_fault(struct task_struct *tsk,
1266} 1266}
1267#endif 1267#endif
1268 1268
1269extern int access_process_vm(struct task_struct *tsk, unsigned long addr, void *buf, int len, int write); 1269extern int access_process_vm(struct task_struct *tsk, unsigned long addr, void *buf, int len,
1270 unsigned int gup_flags);
1270extern int access_remote_vm(struct mm_struct *mm, unsigned long addr, 1271extern int access_remote_vm(struct mm_struct *mm, unsigned long addr,
1271 void *buf, int len, int write); 1272 void *buf, int len, unsigned int gup_flags);
1272 1273
1273long __get_user_pages(struct task_struct *tsk, struct mm_struct *mm, 1274long __get_user_pages(struct task_struct *tsk, struct mm_struct *mm,
1274 unsigned long start, unsigned long nr_pages, 1275 unsigned long start, unsigned long nr_pages,
@@ -1276,19 +1277,18 @@ long __get_user_pages(struct task_struct *tsk, struct mm_struct *mm,
1276 struct vm_area_struct **vmas, int *nonblocking); 1277 struct vm_area_struct **vmas, int *nonblocking);
1277long get_user_pages_remote(struct task_struct *tsk, struct mm_struct *mm, 1278long get_user_pages_remote(struct task_struct *tsk, struct mm_struct *mm,
1278 unsigned long start, unsigned long nr_pages, 1279 unsigned long start, unsigned long nr_pages,
1279 int write, int force, struct page **pages, 1280 unsigned int gup_flags, struct page **pages,
1280 struct vm_area_struct **vmas); 1281 struct vm_area_struct **vmas);
1281long get_user_pages(unsigned long start, unsigned long nr_pages, 1282long get_user_pages(unsigned long start, unsigned long nr_pages,
1282 int write, int force, struct page **pages, 1283 unsigned int gup_flags, struct page **pages,
1283 struct vm_area_struct **vmas); 1284 struct vm_area_struct **vmas);
1284long get_user_pages_locked(unsigned long start, unsigned long nr_pages, 1285long get_user_pages_locked(unsigned long start, unsigned long nr_pages,
1285 int write, int force, struct page **pages, int *locked); 1286 unsigned int gup_flags, struct page **pages, int *locked);
1286long __get_user_pages_unlocked(struct task_struct *tsk, struct mm_struct *mm, 1287long __get_user_pages_unlocked(struct task_struct *tsk, struct mm_struct *mm,
1287 unsigned long start, unsigned long nr_pages, 1288 unsigned long start, unsigned long nr_pages,
1288 int write, int force, struct page **pages, 1289 struct page **pages, unsigned int gup_flags);
1289 unsigned int gup_flags);
1290long get_user_pages_unlocked(unsigned long start, unsigned long nr_pages, 1290long get_user_pages_unlocked(unsigned long start, unsigned long nr_pages,
1291 int write, int force, struct page **pages); 1291 struct page **pages, unsigned int gup_flags);
1292int get_user_pages_fast(unsigned long start, int nr_pages, int write, 1292int get_user_pages_fast(unsigned long start, int nr_pages, int write,
1293 struct page **pages); 1293 struct page **pages);
1294 1294
@@ -1306,7 +1306,7 @@ struct frame_vector {
1306struct frame_vector *frame_vector_create(unsigned int nr_frames); 1306struct frame_vector *frame_vector_create(unsigned int nr_frames);
1307void frame_vector_destroy(struct frame_vector *vec); 1307void frame_vector_destroy(struct frame_vector *vec);
1308int get_vaddr_frames(unsigned long start, unsigned int nr_pfns, 1308int get_vaddr_frames(unsigned long start, unsigned int nr_pfns,
1309 bool write, bool force, struct frame_vector *vec); 1309 unsigned int gup_flags, struct frame_vector *vec);
1310void put_vaddr_frames(struct frame_vector *vec); 1310void put_vaddr_frames(struct frame_vector *vec);
1311int frame_vector_to_pages(struct frame_vector *vec); 1311int frame_vector_to_pages(struct frame_vector *vec);
1312void frame_vector_to_pfns(struct frame_vector *vec); 1312void frame_vector_to_pfns(struct frame_vector *vec);
@@ -1391,7 +1391,7 @@ static inline int stack_guard_page_end(struct vm_area_struct *vma,
1391 !vma_growsup(vma->vm_next, addr); 1391 !vma_growsup(vma->vm_next, addr);
1392} 1392}
1393 1393
1394int vma_is_stack_for_task(struct vm_area_struct *vma, struct task_struct *t); 1394int vma_is_stack_for_current(struct vm_area_struct *vma);
1395 1395
1396extern unsigned long move_page_tables(struct vm_area_struct *vma, 1396extern unsigned long move_page_tables(struct vm_area_struct *vma,
1397 unsigned long old_addr, struct vm_area_struct *new_vma, 1397 unsigned long old_addr, struct vm_area_struct *new_vma,
@@ -2232,6 +2232,7 @@ static inline struct page *follow_page(struct vm_area_struct *vma,
2232#define FOLL_TRIED 0x800 /* a retry, previous pass started an IO */ 2232#define FOLL_TRIED 0x800 /* a retry, previous pass started an IO */
2233#define FOLL_MLOCK 0x1000 /* lock present pages */ 2233#define FOLL_MLOCK 0x1000 /* lock present pages */
2234#define FOLL_REMOTE 0x2000 /* we are working on non-current tsk/mm */ 2234#define FOLL_REMOTE 0x2000 /* we are working on non-current tsk/mm */
2235#define FOLL_COW 0x4000 /* internal GUP flag */
2235 2236
2236typedef int (*pte_fn_t)(pte_t *pte, pgtable_t token, unsigned long addr, 2237typedef int (*pte_fn_t)(pte_t *pte, pgtable_t token, unsigned long addr,
2237 void *data); 2238 void *data);
diff --git a/include/linux/nvme.h b/include/linux/nvme.h
index 7676557ce357..fc3c24206593 100644
--- a/include/linux/nvme.h
+++ b/include/linux/nvme.h
@@ -16,7 +16,6 @@
16#define _LINUX_NVME_H 16#define _LINUX_NVME_H
17 17
18#include <linux/types.h> 18#include <linux/types.h>
19#include <linux/uuid.h>
20 19
21/* NQN names in commands fields specified one size */ 20/* NQN names in commands fields specified one size */
22#define NVMF_NQN_FIELD_LEN 256 21#define NVMF_NQN_FIELD_LEN 256
@@ -182,7 +181,7 @@ struct nvme_id_ctrl {
182 char fr[8]; 181 char fr[8];
183 __u8 rab; 182 __u8 rab;
184 __u8 ieee[3]; 183 __u8 ieee[3];
185 __u8 mic; 184 __u8 cmic;
186 __u8 mdts; 185 __u8 mdts;
187 __le16 cntlid; 186 __le16 cntlid;
188 __le32 ver; 187 __le32 ver;
@@ -202,7 +201,13 @@ struct nvme_id_ctrl {
202 __u8 apsta; 201 __u8 apsta;
203 __le16 wctemp; 202 __le16 wctemp;
204 __le16 cctemp; 203 __le16 cctemp;
205 __u8 rsvd270[50]; 204 __le16 mtfa;
205 __le32 hmpre;
206 __le32 hmmin;
207 __u8 tnvmcap[16];
208 __u8 unvmcap[16];
209 __le32 rpmbs;
210 __u8 rsvd316[4];
206 __le16 kas; 211 __le16 kas;
207 __u8 rsvd322[190]; 212 __u8 rsvd322[190];
208 __u8 sqes; 213 __u8 sqes;
@@ -267,7 +272,7 @@ struct nvme_id_ns {
267 __le16 nabo; 272 __le16 nabo;
268 __le16 nabspf; 273 __le16 nabspf;
269 __u16 rsvd46; 274 __u16 rsvd46;
270 __le64 nvmcap[2]; 275 __u8 nvmcap[16];
271 __u8 rsvd64[40]; 276 __u8 rsvd64[40];
272 __u8 nguid[16]; 277 __u8 nguid[16];
273 __u8 eui64[8]; 278 __u8 eui64[8];
@@ -277,6 +282,16 @@ struct nvme_id_ns {
277}; 282};
278 283
279enum { 284enum {
285 NVME_ID_CNS_NS = 0x00,
286 NVME_ID_CNS_CTRL = 0x01,
287 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
288 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
289 NVME_ID_CNS_NS_PRESENT = 0x11,
290 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
291 NVME_ID_CNS_CTRL_LIST = 0x13,
292};
293
294enum {
280 NVME_NS_FEAT_THIN = 1 << 0, 295 NVME_NS_FEAT_THIN = 1 << 0,
281 NVME_NS_FLBAS_LBA_MASK = 0xf, 296 NVME_NS_FLBAS_LBA_MASK = 0xf,
282 NVME_NS_FLBAS_META_EXT = 0x10, 297 NVME_NS_FLBAS_META_EXT = 0x10,
@@ -556,8 +571,10 @@ enum nvme_admin_opcode {
556 nvme_admin_set_features = 0x09, 571 nvme_admin_set_features = 0x09,
557 nvme_admin_get_features = 0x0a, 572 nvme_admin_get_features = 0x0a,
558 nvme_admin_async_event = 0x0c, 573 nvme_admin_async_event = 0x0c,
574 nvme_admin_ns_mgmt = 0x0d,
559 nvme_admin_activate_fw = 0x10, 575 nvme_admin_activate_fw = 0x10,
560 nvme_admin_download_fw = 0x11, 576 nvme_admin_download_fw = 0x11,
577 nvme_admin_ns_attach = 0x15,
561 nvme_admin_keep_alive = 0x18, 578 nvme_admin_keep_alive = 0x18,
562 nvme_admin_format_nvm = 0x80, 579 nvme_admin_format_nvm = 0x80,
563 nvme_admin_security_send = 0x81, 580 nvme_admin_security_send = 0x81,
@@ -583,6 +600,7 @@ enum {
583 NVME_FEAT_WRITE_ATOMIC = 0x0a, 600 NVME_FEAT_WRITE_ATOMIC = 0x0a,
584 NVME_FEAT_ASYNC_EVENT = 0x0b, 601 NVME_FEAT_ASYNC_EVENT = 0x0b,
585 NVME_FEAT_AUTO_PST = 0x0c, 602 NVME_FEAT_AUTO_PST = 0x0c,
603 NVME_FEAT_HOST_MEM_BUF = 0x0d,
586 NVME_FEAT_KATO = 0x0f, 604 NVME_FEAT_KATO = 0x0f,
587 NVME_FEAT_SW_PROGRESS = 0x80, 605 NVME_FEAT_SW_PROGRESS = 0x80,
588 NVME_FEAT_HOST_ID = 0x81, 606 NVME_FEAT_HOST_ID = 0x81,
@@ -745,7 +763,7 @@ struct nvmf_common_command {
745struct nvmf_disc_rsp_page_entry { 763struct nvmf_disc_rsp_page_entry {
746 __u8 trtype; 764 __u8 trtype;
747 __u8 adrfam; 765 __u8 adrfam;
748 __u8 nqntype; 766 __u8 subtype;
749 __u8 treq; 767 __u8 treq;
750 __le16 portid; 768 __le16 portid;
751 __le16 cntlid; 769 __le16 cntlid;
@@ -794,7 +812,7 @@ struct nvmf_connect_command {
794}; 812};
795 813
796struct nvmf_connect_data { 814struct nvmf_connect_data {
797 uuid_be hostid; 815 __u8 hostid[16];
798 __le16 cntlid; 816 __le16 cntlid;
799 char resv4[238]; 817 char resv4[238];
800 char subsysnqn[NVMF_NQN_FIELD_LEN]; 818 char subsysnqn[NVMF_NQN_FIELD_LEN];
@@ -905,12 +923,23 @@ enum {
905 NVME_SC_INVALID_VECTOR = 0x108, 923 NVME_SC_INVALID_VECTOR = 0x108,
906 NVME_SC_INVALID_LOG_PAGE = 0x109, 924 NVME_SC_INVALID_LOG_PAGE = 0x109,
907 NVME_SC_INVALID_FORMAT = 0x10a, 925 NVME_SC_INVALID_FORMAT = 0x10a,
908 NVME_SC_FIRMWARE_NEEDS_RESET = 0x10b, 926 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
909 NVME_SC_INVALID_QUEUE = 0x10c, 927 NVME_SC_INVALID_QUEUE = 0x10c,
910 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, 928 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
911 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, 929 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
912 NVME_SC_FEATURE_NOT_PER_NS = 0x10f, 930 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
913 NVME_SC_FW_NEEDS_RESET_SUBSYS = 0x110, 931 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
932 NVME_SC_FW_NEEDS_RESET = 0x111,
933 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
934 NVME_SC_FW_ACIVATE_PROHIBITED = 0x113,
935 NVME_SC_OVERLAPPING_RANGE = 0x114,
936 NVME_SC_NS_INSUFFICENT_CAP = 0x115,
937 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
938 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
939 NVME_SC_NS_IS_PRIVATE = 0x119,
940 NVME_SC_NS_NOT_ATTACHED = 0x11a,
941 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
942 NVME_SC_CTRL_LIST_INVALID = 0x11c,
914 943
915 /* 944 /*
916 * I/O Command Set Specific - NVM commands: 945 * I/O Command Set Specific - NVM commands:
@@ -941,6 +970,7 @@ enum {
941 NVME_SC_REFTAG_CHECK = 0x284, 970 NVME_SC_REFTAG_CHECK = 0x284,
942 NVME_SC_COMPARE_FAILED = 0x285, 971 NVME_SC_COMPARE_FAILED = 0x285,
943 NVME_SC_ACCESS_DENIED = 0x286, 972 NVME_SC_ACCESS_DENIED = 0x286,
973 NVME_SC_UNWRITTEN_BLOCK = 0x287,
944 974
945 NVME_SC_DNR = 0x4000, 975 NVME_SC_DNR = 0x4000,
946}; 976};
@@ -960,6 +990,7 @@ struct nvme_completion {
960 __le16 status; /* did the command fail, and if so, why? */ 990 __le16 status; /* did the command fail, and if so, why? */
961}; 991};
962 992
963#define NVME_VS(major, minor) (((major) << 16) | ((minor) << 8)) 993#define NVME_VS(major, minor, tertiary) \
994 (((major) << 16) | ((minor) << 8) | (tertiary))
964 995
965#endif /* _LINUX_NVME_H */ 996#endif /* _LINUX_NVME_H */
diff --git a/include/linux/platform_data/usb-davinci.h b/include/linux/platform_data/usb-davinci.h
index e0bc4abe69c2..0926e99f2e8f 100644
--- a/include/linux/platform_data/usb-davinci.h
+++ b/include/linux/platform_data/usb-davinci.h
@@ -11,29 +11,6 @@
11#ifndef __ASM_ARCH_USB_H 11#ifndef __ASM_ARCH_USB_H
12#define __ASM_ARCH_USB_H 12#define __ASM_ARCH_USB_H
13 13
14/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */
15#define CFGCHIP2_PHYCLKGD (1 << 17)
16#define CFGCHIP2_VBUSSENSE (1 << 16)
17#define CFGCHIP2_RESET (1 << 15)
18#define CFGCHIP2_OTGMODE (3 << 13)
19#define CFGCHIP2_NO_OVERRIDE (0 << 13)
20#define CFGCHIP2_FORCE_HOST (1 << 13)
21#define CFGCHIP2_FORCE_DEVICE (2 << 13)
22#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
23#define CFGCHIP2_USB1PHYCLKMUX (1 << 12)
24#define CFGCHIP2_USB2PHYCLKMUX (1 << 11)
25#define CFGCHIP2_PHYPWRDN (1 << 10)
26#define CFGCHIP2_OTGPWRDN (1 << 9)
27#define CFGCHIP2_DATPOL (1 << 8)
28#define CFGCHIP2_USB1SUSPENDM (1 << 7)
29#define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */
30#define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */
31#define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */
32#define CFGCHIP2_REFFREQ (0xf << 0)
33#define CFGCHIP2_REFFREQ_12MHZ (1 << 0)
34#define CFGCHIP2_REFFREQ_24MHZ (2 << 0)
35#define CFGCHIP2_REFFREQ_48MHZ (3 << 0)
36
37struct da8xx_ohci_root_hub; 14struct da8xx_ohci_root_hub;
38 15
39typedef void (*da8xx_ocic_handler_t)(struct da8xx_ohci_root_hub *hub, 16typedef void (*da8xx_ocic_handler_t)(struct da8xx_ohci_root_hub *hub,
diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h
index 0d7abb8b7315..91a740f6b884 100644
--- a/include/linux/syscalls.h
+++ b/include/linux/syscalls.h
@@ -902,8 +902,5 @@ asmlinkage long sys_pkey_mprotect(unsigned long start, size_t len,
902 unsigned long prot, int pkey); 902 unsigned long prot, int pkey);
903asmlinkage long sys_pkey_alloc(unsigned long flags, unsigned long init_val); 903asmlinkage long sys_pkey_alloc(unsigned long flags, unsigned long init_val);
904asmlinkage long sys_pkey_free(int pkey); 904asmlinkage long sys_pkey_free(int pkey);
905//asmlinkage long sys_pkey_get(int pkey, unsigned long flags);
906//asmlinkage long sys_pkey_set(int pkey, unsigned long access_rights,
907// unsigned long flags);
908 905
909#endif 906#endif
diff --git a/include/linux/thread_info.h b/include/linux/thread_info.h
index 45f004e9cc59..2873baf5372a 100644
--- a/include/linux/thread_info.h
+++ b/include/linux/thread_info.h
@@ -14,17 +14,6 @@ struct timespec;
14struct compat_timespec; 14struct compat_timespec;
15 15
16#ifdef CONFIG_THREAD_INFO_IN_TASK 16#ifdef CONFIG_THREAD_INFO_IN_TASK
17struct thread_info {
18 unsigned long flags; /* low level flags */
19};
20
21#define INIT_THREAD_INFO(tsk) \
22{ \
23 .flags = 0, \
24}
25#endif
26
27#ifdef CONFIG_THREAD_INFO_IN_TASK
28#define current_thread_info() ((struct thread_info *)current) 17#define current_thread_info() ((struct thread_info *)current)
29#endif 18#endif
30 19
diff --git a/include/target/target_core_base.h b/include/target/target_core_base.h
index fb8e3b6febdf..c2119008990a 100644
--- a/include/target/target_core_base.h
+++ b/include/target/target_core_base.h
@@ -177,6 +177,7 @@ enum tcm_sense_reason_table {
177 TCM_LOGICAL_BLOCK_GUARD_CHECK_FAILED = R(0x15), 177 TCM_LOGICAL_BLOCK_GUARD_CHECK_FAILED = R(0x15),
178 TCM_LOGICAL_BLOCK_APP_TAG_CHECK_FAILED = R(0x16), 178 TCM_LOGICAL_BLOCK_APP_TAG_CHECK_FAILED = R(0x16),
179 TCM_LOGICAL_BLOCK_REF_TAG_CHECK_FAILED = R(0x17), 179 TCM_LOGICAL_BLOCK_REF_TAG_CHECK_FAILED = R(0x17),
180 TCM_COPY_TARGET_DEVICE_NOT_REACHABLE = R(0x18),
180#undef R 181#undef R
181}; 182};
182 183
diff --git a/include/uapi/asm-generic/unistd.h b/include/uapi/asm-generic/unistd.h
index dbfee7e86ba6..9b1462e38b82 100644
--- a/include/uapi/asm-generic/unistd.h
+++ b/include/uapi/asm-generic/unistd.h
@@ -730,10 +730,6 @@ __SYSCALL(__NR_pkey_mprotect, sys_pkey_mprotect)
730__SYSCALL(__NR_pkey_alloc, sys_pkey_alloc) 730__SYSCALL(__NR_pkey_alloc, sys_pkey_alloc)
731#define __NR_pkey_free 290 731#define __NR_pkey_free 290
732__SYSCALL(__NR_pkey_free, sys_pkey_free) 732__SYSCALL(__NR_pkey_free, sys_pkey_free)
733#define __NR_pkey_get 291
734//__SYSCALL(__NR_pkey_get, sys_pkey_get)
735#define __NR_pkey_set 292
736//__SYSCALL(__NR_pkey_set, sys_pkey_set)
737 733
738#undef __NR_syscalls 734#undef __NR_syscalls
739#define __NR_syscalls 291 735#define __NR_syscalls 291
diff --git a/include/uapi/linux/Kbuild b/include/uapi/linux/Kbuild
index 6965d0909554..cd2be1c8e9fb 100644
--- a/include/uapi/linux/Kbuild
+++ b/include/uapi/linux/Kbuild
@@ -75,6 +75,7 @@ header-y += bpf_perf_event.h
75header-y += bpf.h 75header-y += bpf.h
76header-y += bpqether.h 76header-y += bpqether.h
77header-y += bsg.h 77header-y += bsg.h
78header-y += bt-bmc.h
78header-y += btrfs.h 79header-y += btrfs.h
79header-y += can.h 80header-y += can.h
80header-y += capability.h 81header-y += capability.h
diff --git a/include/uapi/linux/bt-bmc.h b/include/uapi/linux/bt-bmc.h
new file mode 100644
index 000000000000..d9ec766a63d0
--- /dev/null
+++ b/include/uapi/linux/bt-bmc.h
@@ -0,0 +1,18 @@
1/*
2 * Copyright (c) 2015-2016, IBM Corporation.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#ifndef _UAPI_LINUX_BT_BMC_H
11#define _UAPI_LINUX_BT_BMC_H
12
13#include <linux/ioctl.h>
14
15#define __BT_BMC_IOCTL_MAGIC 0xb1
16#define BT_BMC_IOCTL_SMS_ATN _IO(__BT_BMC_IOCTL_MAGIC, 0x00)
17
18#endif /* _UAPI_LINUX_BT_BMC_H */
diff --git a/kernel/cpu.c b/kernel/cpu.c
index 5df20d6d1520..29de1a9352c0 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -228,7 +228,7 @@ static struct {
228 .wq = __WAIT_QUEUE_HEAD_INITIALIZER(cpu_hotplug.wq), 228 .wq = __WAIT_QUEUE_HEAD_INITIALIZER(cpu_hotplug.wq),
229 .lock = __MUTEX_INITIALIZER(cpu_hotplug.lock), 229 .lock = __MUTEX_INITIALIZER(cpu_hotplug.lock),
230#ifdef CONFIG_DEBUG_LOCK_ALLOC 230#ifdef CONFIG_DEBUG_LOCK_ALLOC
231 .dep_map = {.name = "cpu_hotplug.lock" }, 231 .dep_map = STATIC_LOCKDEP_MAP_INIT("cpu_hotplug.dep_map", &cpu_hotplug.dep_map),
232#endif 232#endif
233}; 233};
234 234
diff --git a/kernel/events/uprobes.c b/kernel/events/uprobes.c
index d4129bb05e5d..f9ec9add2164 100644
--- a/kernel/events/uprobes.c
+++ b/kernel/events/uprobes.c
@@ -300,7 +300,8 @@ int uprobe_write_opcode(struct mm_struct *mm, unsigned long vaddr,
300 300
301retry: 301retry:
302 /* Read the page with vaddr into memory */ 302 /* Read the page with vaddr into memory */
303 ret = get_user_pages_remote(NULL, mm, vaddr, 1, 0, 1, &old_page, &vma); 303 ret = get_user_pages_remote(NULL, mm, vaddr, 1, FOLL_FORCE, &old_page,
304 &vma);
304 if (ret <= 0) 305 if (ret <= 0)
305 return ret; 306 return ret;
306 307
@@ -1710,7 +1711,8 @@ static int is_trap_at_addr(struct mm_struct *mm, unsigned long vaddr)
1710 * but we treat this as a 'remote' access since it is 1711 * but we treat this as a 'remote' access since it is
1711 * essentially a kernel access to the memory. 1712 * essentially a kernel access to the memory.
1712 */ 1713 */
1713 result = get_user_pages_remote(NULL, mm, vaddr, 1, 0, 1, &page, NULL); 1714 result = get_user_pages_remote(NULL, mm, vaddr, 1, FOLL_FORCE, &page,
1715 NULL);
1714 if (result < 0) 1716 if (result < 0)
1715 return result; 1717 return result;
1716 1718
diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c
index 0c5f1a5db654..9c4d30483264 100644
--- a/kernel/irq/manage.c
+++ b/kernel/irq/manage.c
@@ -721,6 +721,7 @@ int irq_set_parent(int irq, int parent_irq)
721 irq_put_desc_unlock(desc, flags); 721 irq_put_desc_unlock(desc, flags);
722 return 0; 722 return 0;
723} 723}
724EXPORT_SYMBOL_GPL(irq_set_parent);
724#endif 725#endif
725 726
726/* 727/*
diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c
index d5e397315473..de08fc90baaf 100644
--- a/kernel/printk/printk.c
+++ b/kernel/printk/printk.c
@@ -1769,6 +1769,10 @@ static size_t log_output(int facility, int level, enum log_flags lflags, const c
1769 cont_flush(); 1769 cont_flush();
1770 } 1770 }
1771 1771
1772 /* Skip empty continuation lines that couldn't be added - they just flush */
1773 if (!text_len && (lflags & LOG_CONT))
1774 return 0;
1775
1772 /* If it doesn't end in a newline, try to buffer the current line */ 1776 /* If it doesn't end in a newline, try to buffer the current line */
1773 if (!(lflags & LOG_NEWLINE)) { 1777 if (!(lflags & LOG_NEWLINE)) {
1774 if (cont_add(facility, level, lflags, text, text_len)) 1778 if (cont_add(facility, level, lflags, text, text_len))
diff --git a/kernel/ptrace.c b/kernel/ptrace.c
index 2a99027312a6..e6474f7272ec 100644
--- a/kernel/ptrace.c
+++ b/kernel/ptrace.c
@@ -537,7 +537,7 @@ int ptrace_readdata(struct task_struct *tsk, unsigned long src, char __user *dst
537 int this_len, retval; 537 int this_len, retval;
538 538
539 this_len = (len > sizeof(buf)) ? sizeof(buf) : len; 539 this_len = (len > sizeof(buf)) ? sizeof(buf) : len;
540 retval = access_process_vm(tsk, src, buf, this_len, 0); 540 retval = access_process_vm(tsk, src, buf, this_len, FOLL_FORCE);
541 if (!retval) { 541 if (!retval) {
542 if (copied) 542 if (copied)
543 break; 543 break;
@@ -564,7 +564,8 @@ int ptrace_writedata(struct task_struct *tsk, char __user *src, unsigned long ds
564 this_len = (len > sizeof(buf)) ? sizeof(buf) : len; 564 this_len = (len > sizeof(buf)) ? sizeof(buf) : len;
565 if (copy_from_user(buf, src, this_len)) 565 if (copy_from_user(buf, src, this_len))
566 return -EFAULT; 566 return -EFAULT;
567 retval = access_process_vm(tsk, dst, buf, this_len, 1); 567 retval = access_process_vm(tsk, dst, buf, this_len,
568 FOLL_FORCE | FOLL_WRITE);
568 if (!retval) { 569 if (!retval) {
569 if (copied) 570 if (copied)
570 break; 571 break;
@@ -1127,7 +1128,7 @@ int generic_ptrace_peekdata(struct task_struct *tsk, unsigned long addr,
1127 unsigned long tmp; 1128 unsigned long tmp;
1128 int copied; 1129 int copied;
1129 1130
1130 copied = access_process_vm(tsk, addr, &tmp, sizeof(tmp), 0); 1131 copied = access_process_vm(tsk, addr, &tmp, sizeof(tmp), FOLL_FORCE);
1131 if (copied != sizeof(tmp)) 1132 if (copied != sizeof(tmp))
1132 return -EIO; 1133 return -EIO;
1133 return put_user(tmp, (unsigned long __user *)data); 1134 return put_user(tmp, (unsigned long __user *)data);
@@ -1138,7 +1139,8 @@ int generic_ptrace_pokedata(struct task_struct *tsk, unsigned long addr,
1138{ 1139{
1139 int copied; 1140 int copied;
1140 1141
1141 copied = access_process_vm(tsk, addr, &data, sizeof(data), 1); 1142 copied = access_process_vm(tsk, addr, &data, sizeof(data),
1143 FOLL_FORCE | FOLL_WRITE);
1142 return (copied == sizeof(data)) ? 0 : -EIO; 1144 return (copied == sizeof(data)) ? 0 : -EIO;
1143} 1145}
1144 1146
@@ -1155,7 +1157,8 @@ int compat_ptrace_request(struct task_struct *child, compat_long_t request,
1155 switch (request) { 1157 switch (request) {
1156 case PTRACE_PEEKTEXT: 1158 case PTRACE_PEEKTEXT:
1157 case PTRACE_PEEKDATA: 1159 case PTRACE_PEEKDATA:
1158 ret = access_process_vm(child, addr, &word, sizeof(word), 0); 1160 ret = access_process_vm(child, addr, &word, sizeof(word),
1161 FOLL_FORCE);
1159 if (ret != sizeof(word)) 1162 if (ret != sizeof(word))
1160 ret = -EIO; 1163 ret = -EIO;
1161 else 1164 else
@@ -1164,7 +1167,8 @@ int compat_ptrace_request(struct task_struct *child, compat_long_t request,
1164 1167
1165 case PTRACE_POKETEXT: 1168 case PTRACE_POKETEXT:
1166 case PTRACE_POKEDATA: 1169 case PTRACE_POKEDATA:
1167 ret = access_process_vm(child, addr, &data, sizeof(data), 1); 1170 ret = access_process_vm(child, addr, &data, sizeof(data),
1171 FOLL_FORCE | FOLL_WRITE);
1168 ret = (ret != sizeof(data) ? -EIO : 0); 1172 ret = (ret != sizeof(data) ? -EIO : 0);
1169 break; 1173 break;
1170 1174
diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
index 2d4ad72f8f3c..d941c97dfbc3 100644
--- a/kernel/sched/fair.c
+++ b/kernel/sched/fair.c
@@ -690,7 +690,14 @@ void init_entity_runnable_average(struct sched_entity *se)
690 * will definitely be update (after enqueue). 690 * will definitely be update (after enqueue).
691 */ 691 */
692 sa->period_contrib = 1023; 692 sa->period_contrib = 1023;
693 sa->load_avg = scale_load_down(se->load.weight); 693 /*
694 * Tasks are intialized with full load to be seen as heavy tasks until
695 * they get a chance to stabilize to their real load level.
696 * Group entities are intialized with zero load to reflect the fact that
697 * nothing has been attached to the task group yet.
698 */
699 if (entity_is_task(se))
700 sa->load_avg = scale_load_down(se->load.weight);
694 sa->load_sum = sa->load_avg * LOAD_AVG_MAX; 701 sa->load_sum = sa->load_avg * LOAD_AVG_MAX;
695 /* 702 /*
696 * At this point, util_avg won't be used in select_task_rq_fair anyway 703 * At this point, util_avg won't be used in select_task_rq_fair anyway
@@ -5471,13 +5478,18 @@ static inline int select_idle_smt(struct task_struct *p, struct sched_domain *sd
5471 */ 5478 */
5472static int select_idle_cpu(struct task_struct *p, struct sched_domain *sd, int target) 5479static int select_idle_cpu(struct task_struct *p, struct sched_domain *sd, int target)
5473{ 5480{
5474 struct sched_domain *this_sd = rcu_dereference(*this_cpu_ptr(&sd_llc)); 5481 struct sched_domain *this_sd;
5475 u64 avg_idle = this_rq()->avg_idle; 5482 u64 avg_cost, avg_idle = this_rq()->avg_idle;
5476 u64 avg_cost = this_sd->avg_scan_cost;
5477 u64 time, cost; 5483 u64 time, cost;
5478 s64 delta; 5484 s64 delta;
5479 int cpu, wrap; 5485 int cpu, wrap;
5480 5486
5487 this_sd = rcu_dereference(*this_cpu_ptr(&sd_llc));
5488 if (!this_sd)
5489 return -1;
5490
5491 avg_cost = this_sd->avg_scan_cost;
5492
5481 /* 5493 /*
5482 * Due to large variance we need a large fuzz factor; hackbench in 5494 * Due to large variance we need a large fuzz factor; hackbench in
5483 * particularly is sensitive here. 5495 * particularly is sensitive here.
diff --git a/kernel/time/alarmtimer.c b/kernel/time/alarmtimer.c
index c3aad685bbc0..12dd190634ab 100644
--- a/kernel/time/alarmtimer.c
+++ b/kernel/time/alarmtimer.c
@@ -542,7 +542,6 @@ static int alarm_clock_get(clockid_t which_clock, struct timespec *tp)
542static int alarm_timer_create(struct k_itimer *new_timer) 542static int alarm_timer_create(struct k_itimer *new_timer)
543{ 543{
544 enum alarmtimer_type type; 544 enum alarmtimer_type type;
545 struct alarm_base *base;
546 545
547 if (!alarmtimer_get_rtcdev()) 546 if (!alarmtimer_get_rtcdev())
548 return -ENOTSUPP; 547 return -ENOTSUPP;
@@ -551,7 +550,6 @@ static int alarm_timer_create(struct k_itimer *new_timer)
551 return -EPERM; 550 return -EPERM;
552 551
553 type = clock2alarm(new_timer->it_clock); 552 type = clock2alarm(new_timer->it_clock);
554 base = &alarm_bases[type];
555 alarm_init(&new_timer->it.alarm.alarmtimer, type, alarm_handle_timer); 553 alarm_init(&new_timer->it.alarm.alarmtimer, type, alarm_handle_timer);
556 return 0; 554 return 0;
557} 555}
diff --git a/mm/frame_vector.c b/mm/frame_vector.c
index 381bb07ed14f..db77dcb38afd 100644
--- a/mm/frame_vector.c
+++ b/mm/frame_vector.c
@@ -11,10 +11,7 @@
11 * get_vaddr_frames() - map virtual addresses to pfns 11 * get_vaddr_frames() - map virtual addresses to pfns
12 * @start: starting user address 12 * @start: starting user address
13 * @nr_frames: number of pages / pfns from start to map 13 * @nr_frames: number of pages / pfns from start to map
14 * @write: whether pages will be written to by the caller 14 * @gup_flags: flags modifying lookup behaviour
15 * @force: whether to force write access even if user mapping is
16 * readonly. See description of the same argument of
17 get_user_pages().
18 * @vec: structure which receives pages / pfns of the addresses mapped. 15 * @vec: structure which receives pages / pfns of the addresses mapped.
19 * It should have space for at least nr_frames entries. 16 * It should have space for at least nr_frames entries.
20 * 17 *
@@ -34,7 +31,7 @@
34 * This function takes care of grabbing mmap_sem as necessary. 31 * This function takes care of grabbing mmap_sem as necessary.
35 */ 32 */
36int get_vaddr_frames(unsigned long start, unsigned int nr_frames, 33int get_vaddr_frames(unsigned long start, unsigned int nr_frames,
37 bool write, bool force, struct frame_vector *vec) 34 unsigned int gup_flags, struct frame_vector *vec)
38{ 35{
39 struct mm_struct *mm = current->mm; 36 struct mm_struct *mm = current->mm;
40 struct vm_area_struct *vma; 37 struct vm_area_struct *vma;
@@ -59,7 +56,7 @@ int get_vaddr_frames(unsigned long start, unsigned int nr_frames,
59 vec->got_ref = true; 56 vec->got_ref = true;
60 vec->is_pfns = false; 57 vec->is_pfns = false;
61 ret = get_user_pages_locked(start, nr_frames, 58 ret = get_user_pages_locked(start, nr_frames,
62 write, force, (struct page **)(vec->ptrs), &locked); 59 gup_flags, (struct page **)(vec->ptrs), &locked);
63 goto out; 60 goto out;
64 } 61 }
65 62
diff --git a/mm/gup.c b/mm/gup.c
index 96b2b2fd0fbd..7aa113c2d373 100644
--- a/mm/gup.c
+++ b/mm/gup.c
@@ -60,6 +60,16 @@ static int follow_pfn_pte(struct vm_area_struct *vma, unsigned long address,
60 return -EEXIST; 60 return -EEXIST;
61} 61}
62 62
63/*
64 * FOLL_FORCE can write to even unwritable pte's, but only
65 * after we've gone through a COW cycle and they are dirty.
66 */
67static inline bool can_follow_write_pte(pte_t pte, unsigned int flags)
68{
69 return pte_write(pte) ||
70 ((flags & FOLL_FORCE) && (flags & FOLL_COW) && pte_dirty(pte));
71}
72
63static struct page *follow_page_pte(struct vm_area_struct *vma, 73static struct page *follow_page_pte(struct vm_area_struct *vma,
64 unsigned long address, pmd_t *pmd, unsigned int flags) 74 unsigned long address, pmd_t *pmd, unsigned int flags)
65{ 75{
@@ -95,7 +105,7 @@ retry:
95 } 105 }
96 if ((flags & FOLL_NUMA) && pte_protnone(pte)) 106 if ((flags & FOLL_NUMA) && pte_protnone(pte))
97 goto no_page; 107 goto no_page;
98 if ((flags & FOLL_WRITE) && !pte_write(pte)) { 108 if ((flags & FOLL_WRITE) && !can_follow_write_pte(pte, flags)) {
99 pte_unmap_unlock(ptep, ptl); 109 pte_unmap_unlock(ptep, ptl);
100 return NULL; 110 return NULL;
101 } 111 }
@@ -412,7 +422,7 @@ static int faultin_page(struct task_struct *tsk, struct vm_area_struct *vma,
412 * reCOWed by userspace write). 422 * reCOWed by userspace write).
413 */ 423 */
414 if ((ret & VM_FAULT_WRITE) && !(vma->vm_flags & VM_WRITE)) 424 if ((ret & VM_FAULT_WRITE) && !(vma->vm_flags & VM_WRITE))
415 *flags &= ~FOLL_WRITE; 425 *flags |= FOLL_COW;
416 return 0; 426 return 0;
417} 427}
418 428
@@ -729,7 +739,6 @@ static __always_inline long __get_user_pages_locked(struct task_struct *tsk,
729 struct mm_struct *mm, 739 struct mm_struct *mm,
730 unsigned long start, 740 unsigned long start,
731 unsigned long nr_pages, 741 unsigned long nr_pages,
732 int write, int force,
733 struct page **pages, 742 struct page **pages,
734 struct vm_area_struct **vmas, 743 struct vm_area_struct **vmas,
735 int *locked, bool notify_drop, 744 int *locked, bool notify_drop,
@@ -747,10 +756,6 @@ static __always_inline long __get_user_pages_locked(struct task_struct *tsk,
747 756
748 if (pages) 757 if (pages)
749 flags |= FOLL_GET; 758 flags |= FOLL_GET;
750 if (write)
751 flags |= FOLL_WRITE;
752 if (force)
753 flags |= FOLL_FORCE;
754 759
755 pages_done = 0; 760 pages_done = 0;
756 lock_dropped = false; 761 lock_dropped = false;
@@ -843,12 +848,12 @@ static __always_inline long __get_user_pages_locked(struct task_struct *tsk,
843 * up_read(&mm->mmap_sem); 848 * up_read(&mm->mmap_sem);
844 */ 849 */
845long get_user_pages_locked(unsigned long start, unsigned long nr_pages, 850long get_user_pages_locked(unsigned long start, unsigned long nr_pages,
846 int write, int force, struct page **pages, 851 unsigned int gup_flags, struct page **pages,
847 int *locked) 852 int *locked)
848{ 853{
849 return __get_user_pages_locked(current, current->mm, start, nr_pages, 854 return __get_user_pages_locked(current, current->mm, start, nr_pages,
850 write, force, pages, NULL, locked, true, 855 pages, NULL, locked, true,
851 FOLL_TOUCH); 856 gup_flags | FOLL_TOUCH);
852} 857}
853EXPORT_SYMBOL(get_user_pages_locked); 858EXPORT_SYMBOL(get_user_pages_locked);
854 859
@@ -864,14 +869,14 @@ EXPORT_SYMBOL(get_user_pages_locked);
864 */ 869 */
865__always_inline long __get_user_pages_unlocked(struct task_struct *tsk, struct mm_struct *mm, 870__always_inline long __get_user_pages_unlocked(struct task_struct *tsk, struct mm_struct *mm,
866 unsigned long start, unsigned long nr_pages, 871 unsigned long start, unsigned long nr_pages,
867 int write, int force, struct page **pages, 872 struct page **pages, unsigned int gup_flags)
868 unsigned int gup_flags)
869{ 873{
870 long ret; 874 long ret;
871 int locked = 1; 875 int locked = 1;
876
872 down_read(&mm->mmap_sem); 877 down_read(&mm->mmap_sem);
873 ret = __get_user_pages_locked(tsk, mm, start, nr_pages, write, force, 878 ret = __get_user_pages_locked(tsk, mm, start, nr_pages, pages, NULL,
874 pages, NULL, &locked, false, gup_flags); 879 &locked, false, gup_flags);
875 if (locked) 880 if (locked)
876 up_read(&mm->mmap_sem); 881 up_read(&mm->mmap_sem);
877 return ret; 882 return ret;
@@ -896,10 +901,10 @@ EXPORT_SYMBOL(__get_user_pages_unlocked);
896 * "force" parameter). 901 * "force" parameter).
897 */ 902 */
898long get_user_pages_unlocked(unsigned long start, unsigned long nr_pages, 903long get_user_pages_unlocked(unsigned long start, unsigned long nr_pages,
899 int write, int force, struct page **pages) 904 struct page **pages, unsigned int gup_flags)
900{ 905{
901 return __get_user_pages_unlocked(current, current->mm, start, nr_pages, 906 return __get_user_pages_unlocked(current, current->mm, start, nr_pages,
902 write, force, pages, FOLL_TOUCH); 907 pages, gup_flags | FOLL_TOUCH);
903} 908}
904EXPORT_SYMBOL(get_user_pages_unlocked); 909EXPORT_SYMBOL(get_user_pages_unlocked);
905 910
@@ -910,9 +915,7 @@ EXPORT_SYMBOL(get_user_pages_unlocked);
910 * @mm: mm_struct of target mm 915 * @mm: mm_struct of target mm
911 * @start: starting user address 916 * @start: starting user address
912 * @nr_pages: number of pages from start to pin 917 * @nr_pages: number of pages from start to pin
913 * @write: whether pages will be written to by the caller 918 * @gup_flags: flags modifying lookup behaviour
914 * @force: whether to force access even when user mapping is currently
915 * protected (but never forces write access to shared mapping).
916 * @pages: array that receives pointers to the pages pinned. 919 * @pages: array that receives pointers to the pages pinned.
917 * Should be at least nr_pages long. Or NULL, if caller 920 * Should be at least nr_pages long. Or NULL, if caller
918 * only intends to ensure the pages are faulted in. 921 * only intends to ensure the pages are faulted in.
@@ -941,9 +944,9 @@ EXPORT_SYMBOL(get_user_pages_unlocked);
941 * or similar operation cannot guarantee anything stronger anyway because 944 * or similar operation cannot guarantee anything stronger anyway because
942 * locks can't be held over the syscall boundary. 945 * locks can't be held over the syscall boundary.
943 * 946 *
944 * If write=0, the page must not be written to. If the page is written to, 947 * If gup_flags & FOLL_WRITE == 0, the page must not be written to. If the page
945 * set_page_dirty (or set_page_dirty_lock, as appropriate) must be called 948 * is written to, set_page_dirty (or set_page_dirty_lock, as appropriate) must
946 * after the page is finished with, and before put_page is called. 949 * be called after the page is finished with, and before put_page is called.
947 * 950 *
948 * get_user_pages is typically used for fewer-copy IO operations, to get a 951 * get_user_pages is typically used for fewer-copy IO operations, to get a
949 * handle on the memory by some means other than accesses via the user virtual 952 * handle on the memory by some means other than accesses via the user virtual
@@ -960,12 +963,12 @@ EXPORT_SYMBOL(get_user_pages_unlocked);
960 */ 963 */
961long get_user_pages_remote(struct task_struct *tsk, struct mm_struct *mm, 964long get_user_pages_remote(struct task_struct *tsk, struct mm_struct *mm,
962 unsigned long start, unsigned long nr_pages, 965 unsigned long start, unsigned long nr_pages,
963 int write, int force, struct page **pages, 966 unsigned int gup_flags, struct page **pages,
964 struct vm_area_struct **vmas) 967 struct vm_area_struct **vmas)
965{ 968{
966 return __get_user_pages_locked(tsk, mm, start, nr_pages, write, force, 969 return __get_user_pages_locked(tsk, mm, start, nr_pages, pages, vmas,
967 pages, vmas, NULL, false, 970 NULL, false,
968 FOLL_TOUCH | FOLL_REMOTE); 971 gup_flags | FOLL_TOUCH | FOLL_REMOTE);
969} 972}
970EXPORT_SYMBOL(get_user_pages_remote); 973EXPORT_SYMBOL(get_user_pages_remote);
971 974
@@ -976,12 +979,12 @@ EXPORT_SYMBOL(get_user_pages_remote);
976 * obviously don't pass FOLL_REMOTE in here. 979 * obviously don't pass FOLL_REMOTE in here.
977 */ 980 */
978long get_user_pages(unsigned long start, unsigned long nr_pages, 981long get_user_pages(unsigned long start, unsigned long nr_pages,
979 int write, int force, struct page **pages, 982 unsigned int gup_flags, struct page **pages,
980 struct vm_area_struct **vmas) 983 struct vm_area_struct **vmas)
981{ 984{
982 return __get_user_pages_locked(current, current->mm, start, nr_pages, 985 return __get_user_pages_locked(current, current->mm, start, nr_pages,
983 write, force, pages, vmas, NULL, false, 986 pages, vmas, NULL, false,
984 FOLL_TOUCH); 987 gup_flags | FOLL_TOUCH);
985} 988}
986EXPORT_SYMBOL(get_user_pages); 989EXPORT_SYMBOL(get_user_pages);
987 990
@@ -1505,7 +1508,8 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write,
1505 start += nr << PAGE_SHIFT; 1508 start += nr << PAGE_SHIFT;
1506 pages += nr; 1509 pages += nr;
1507 1510
1508 ret = get_user_pages_unlocked(start, nr_pages - nr, write, 0, pages); 1511 ret = get_user_pages_unlocked(start, nr_pages - nr, pages,
1512 write ? FOLL_WRITE : 0);
1509 1513
1510 /* Have to be a bit careful with return values */ 1514 /* Have to be a bit careful with return values */
1511 if (nr > 0) { 1515 if (nr > 0) {
diff --git a/mm/kasan/kasan.c b/mm/kasan/kasan.c
index 88af13c00d3c..70c009741aab 100644
--- a/mm/kasan/kasan.c
+++ b/mm/kasan/kasan.c
@@ -34,6 +34,7 @@
34#include <linux/string.h> 34#include <linux/string.h>
35#include <linux/types.h> 35#include <linux/types.h>
36#include <linux/vmalloc.h> 36#include <linux/vmalloc.h>
37#include <linux/bug.h>
37 38
38#include "kasan.h" 39#include "kasan.h"
39#include "../slab.h" 40#include "../slab.h"
@@ -62,7 +63,7 @@ void kasan_unpoison_shadow(const void *address, size_t size)
62 } 63 }
63} 64}
64 65
65static void __kasan_unpoison_stack(struct task_struct *task, void *sp) 66static void __kasan_unpoison_stack(struct task_struct *task, const void *sp)
66{ 67{
67 void *base = task_stack_page(task); 68 void *base = task_stack_page(task);
68 size_t size = sp - base; 69 size_t size = sp - base;
@@ -77,9 +78,24 @@ void kasan_unpoison_task_stack(struct task_struct *task)
77} 78}
78 79
79/* Unpoison the stack for the current task beyond a watermark sp value. */ 80/* Unpoison the stack for the current task beyond a watermark sp value. */
80asmlinkage void kasan_unpoison_remaining_stack(void *sp) 81asmlinkage void kasan_unpoison_task_stack_below(const void *watermark)
81{ 82{
82 __kasan_unpoison_stack(current, sp); 83 __kasan_unpoison_stack(current, watermark);
84}
85
86/*
87 * Clear all poison for the region between the current SP and a provided
88 * watermark value, as is sometimes required prior to hand-crafted asm function
89 * returns in the middle of functions.
90 */
91void kasan_unpoison_stack_above_sp_to(const void *watermark)
92{
93 const void *sp = __builtin_frame_address(0);
94 size_t size = watermark - sp;
95
96 if (WARN_ON(sp > watermark))
97 return;
98 kasan_unpoison_shadow(sp, size);
83} 99}
84 100
85/* 101/*
diff --git a/mm/memory.c b/mm/memory.c
index fc1987dfd8cc..e18c57bdc75c 100644
--- a/mm/memory.c
+++ b/mm/memory.c
@@ -3869,10 +3869,11 @@ EXPORT_SYMBOL_GPL(generic_access_phys);
3869 * given task for page fault accounting. 3869 * given task for page fault accounting.
3870 */ 3870 */
3871static int __access_remote_vm(struct task_struct *tsk, struct mm_struct *mm, 3871static int __access_remote_vm(struct task_struct *tsk, struct mm_struct *mm,
3872 unsigned long addr, void *buf, int len, int write) 3872 unsigned long addr, void *buf, int len, unsigned int gup_flags)
3873{ 3873{
3874 struct vm_area_struct *vma; 3874 struct vm_area_struct *vma;
3875 void *old_buf = buf; 3875 void *old_buf = buf;
3876 int write = gup_flags & FOLL_WRITE;
3876 3877
3877 down_read(&mm->mmap_sem); 3878 down_read(&mm->mmap_sem);
3878 /* ignore errors, just check how much was successfully transferred */ 3879 /* ignore errors, just check how much was successfully transferred */
@@ -3882,7 +3883,7 @@ static int __access_remote_vm(struct task_struct *tsk, struct mm_struct *mm,
3882 struct page *page = NULL; 3883 struct page *page = NULL;
3883 3884
3884 ret = get_user_pages_remote(tsk, mm, addr, 1, 3885 ret = get_user_pages_remote(tsk, mm, addr, 1,
3885 write, 1, &page, &vma); 3886 gup_flags, &page, &vma);
3886 if (ret <= 0) { 3887 if (ret <= 0) {
3887#ifndef CONFIG_HAVE_IOREMAP_PROT 3888#ifndef CONFIG_HAVE_IOREMAP_PROT
3888 break; 3889 break;
@@ -3934,14 +3935,14 @@ static int __access_remote_vm(struct task_struct *tsk, struct mm_struct *mm,
3934 * @addr: start address to access 3935 * @addr: start address to access
3935 * @buf: source or destination buffer 3936 * @buf: source or destination buffer
3936 * @len: number of bytes to transfer 3937 * @len: number of bytes to transfer
3937 * @write: whether the access is a write 3938 * @gup_flags: flags modifying lookup behaviour
3938 * 3939 *
3939 * The caller must hold a reference on @mm. 3940 * The caller must hold a reference on @mm.
3940 */ 3941 */
3941int access_remote_vm(struct mm_struct *mm, unsigned long addr, 3942int access_remote_vm(struct mm_struct *mm, unsigned long addr,
3942 void *buf, int len, int write) 3943 void *buf, int len, unsigned int gup_flags)
3943{ 3944{
3944 return __access_remote_vm(NULL, mm, addr, buf, len, write); 3945 return __access_remote_vm(NULL, mm, addr, buf, len, gup_flags);
3945} 3946}
3946 3947
3947/* 3948/*
@@ -3950,7 +3951,7 @@ int access_remote_vm(struct mm_struct *mm, unsigned long addr,
3950 * Do not walk the page table directly, use get_user_pages 3951 * Do not walk the page table directly, use get_user_pages
3951 */ 3952 */
3952int access_process_vm(struct task_struct *tsk, unsigned long addr, 3953int access_process_vm(struct task_struct *tsk, unsigned long addr,
3953 void *buf, int len, int write) 3954 void *buf, int len, unsigned int gup_flags)
3954{ 3955{
3955 struct mm_struct *mm; 3956 struct mm_struct *mm;
3956 int ret; 3957 int ret;
@@ -3959,7 +3960,8 @@ int access_process_vm(struct task_struct *tsk, unsigned long addr,
3959 if (!mm) 3960 if (!mm)
3960 return 0; 3961 return 0;
3961 3962
3962 ret = __access_remote_vm(tsk, mm, addr, buf, len, write); 3963 ret = __access_remote_vm(tsk, mm, addr, buf, len, gup_flags);
3964
3963 mmput(mm); 3965 mmput(mm);
3964 3966
3965 return ret; 3967 return ret;
diff --git a/mm/mempolicy.c b/mm/mempolicy.c
index ad1c96ac313c..0b859af06b87 100644
--- a/mm/mempolicy.c
+++ b/mm/mempolicy.c
@@ -850,7 +850,7 @@ static int lookup_node(unsigned long addr)
850 struct page *p; 850 struct page *p;
851 int err; 851 int err;
852 852
853 err = get_user_pages(addr & PAGE_MASK, 1, 0, 0, &p, NULL); 853 err = get_user_pages(addr & PAGE_MASK, 1, 0, &p, NULL);
854 if (err >= 0) { 854 if (err >= 0) {
855 err = page_to_nid(p); 855 err = page_to_nid(p);
856 put_page(p); 856 put_page(p);
diff --git a/mm/mprotect.c b/mm/mprotect.c
index bcdbe62f3e6d..11936526b08b 100644
--- a/mm/mprotect.c
+++ b/mm/mprotect.c
@@ -25,7 +25,6 @@
25#include <linux/perf_event.h> 25#include <linux/perf_event.h>
26#include <linux/pkeys.h> 26#include <linux/pkeys.h>
27#include <linux/ksm.h> 27#include <linux/ksm.h>
28#include <linux/pkeys.h>
29#include <asm/uaccess.h> 28#include <asm/uaccess.h>
30#include <asm/pgtable.h> 29#include <asm/pgtable.h>
31#include <asm/cacheflush.h> 30#include <asm/cacheflush.h>
diff --git a/mm/nommu.c b/mm/nommu.c
index 95daf81a4855..db5fd1795298 100644
--- a/mm/nommu.c
+++ b/mm/nommu.c
@@ -160,33 +160,25 @@ finish_or_fault:
160 * - don't permit access to VMAs that don't support it, such as I/O mappings 160 * - don't permit access to VMAs that don't support it, such as I/O mappings
161 */ 161 */
162long get_user_pages(unsigned long start, unsigned long nr_pages, 162long get_user_pages(unsigned long start, unsigned long nr_pages,
163 int write, int force, struct page **pages, 163 unsigned int gup_flags, struct page **pages,
164 struct vm_area_struct **vmas) 164 struct vm_area_struct **vmas)
165{ 165{
166 int flags = 0; 166 return __get_user_pages(current, current->mm, start, nr_pages,
167 167 gup_flags, pages, vmas, NULL);
168 if (write)
169 flags |= FOLL_WRITE;
170 if (force)
171 flags |= FOLL_FORCE;
172
173 return __get_user_pages(current, current->mm, start, nr_pages, flags,
174 pages, vmas, NULL);
175} 168}
176EXPORT_SYMBOL(get_user_pages); 169EXPORT_SYMBOL(get_user_pages);
177 170
178long get_user_pages_locked(unsigned long start, unsigned long nr_pages, 171long get_user_pages_locked(unsigned long start, unsigned long nr_pages,
179 int write, int force, struct page **pages, 172 unsigned int gup_flags, struct page **pages,
180 int *locked) 173 int *locked)
181{ 174{
182 return get_user_pages(start, nr_pages, write, force, pages, NULL); 175 return get_user_pages(start, nr_pages, gup_flags, pages, NULL);
183} 176}
184EXPORT_SYMBOL(get_user_pages_locked); 177EXPORT_SYMBOL(get_user_pages_locked);
185 178
186long __get_user_pages_unlocked(struct task_struct *tsk, struct mm_struct *mm, 179long __get_user_pages_unlocked(struct task_struct *tsk, struct mm_struct *mm,
187 unsigned long start, unsigned long nr_pages, 180 unsigned long start, unsigned long nr_pages,
188 int write, int force, struct page **pages, 181 struct page **pages, unsigned int gup_flags)
189 unsigned int gup_flags)
190{ 182{
191 long ret; 183 long ret;
192 down_read(&mm->mmap_sem); 184 down_read(&mm->mmap_sem);
@@ -198,10 +190,10 @@ long __get_user_pages_unlocked(struct task_struct *tsk, struct mm_struct *mm,
198EXPORT_SYMBOL(__get_user_pages_unlocked); 190EXPORT_SYMBOL(__get_user_pages_unlocked);
199 191
200long get_user_pages_unlocked(unsigned long start, unsigned long nr_pages, 192long get_user_pages_unlocked(unsigned long start, unsigned long nr_pages,
201 int write, int force, struct page **pages) 193 struct page **pages, unsigned int gup_flags)
202{ 194{
203 return __get_user_pages_unlocked(current, current->mm, start, nr_pages, 195 return __get_user_pages_unlocked(current, current->mm, start, nr_pages,
204 write, force, pages, 0); 196 pages, gup_flags);
205} 197}
206EXPORT_SYMBOL(get_user_pages_unlocked); 198EXPORT_SYMBOL(get_user_pages_unlocked);
207 199
@@ -1817,9 +1809,10 @@ void filemap_map_pages(struct fault_env *fe,
1817EXPORT_SYMBOL(filemap_map_pages); 1809EXPORT_SYMBOL(filemap_map_pages);
1818 1810
1819static int __access_remote_vm(struct task_struct *tsk, struct mm_struct *mm, 1811static int __access_remote_vm(struct task_struct *tsk, struct mm_struct *mm,
1820 unsigned long addr, void *buf, int len, int write) 1812 unsigned long addr, void *buf, int len, unsigned int gup_flags)
1821{ 1813{
1822 struct vm_area_struct *vma; 1814 struct vm_area_struct *vma;
1815 int write = gup_flags & FOLL_WRITE;
1823 1816
1824 down_read(&mm->mmap_sem); 1817 down_read(&mm->mmap_sem);
1825 1818
@@ -1854,21 +1847,22 @@ static int __access_remote_vm(struct task_struct *tsk, struct mm_struct *mm,
1854 * @addr: start address to access 1847 * @addr: start address to access
1855 * @buf: source or destination buffer 1848 * @buf: source or destination buffer
1856 * @len: number of bytes to transfer 1849 * @len: number of bytes to transfer
1857 * @write: whether the access is a write 1850 * @gup_flags: flags modifying lookup behaviour
1858 * 1851 *
1859 * The caller must hold a reference on @mm. 1852 * The caller must hold a reference on @mm.
1860 */ 1853 */
1861int access_remote_vm(struct mm_struct *mm, unsigned long addr, 1854int access_remote_vm(struct mm_struct *mm, unsigned long addr,
1862 void *buf, int len, int write) 1855 void *buf, int len, unsigned int gup_flags)
1863{ 1856{
1864 return __access_remote_vm(NULL, mm, addr, buf, len, write); 1857 return __access_remote_vm(NULL, mm, addr, buf, len, gup_flags);
1865} 1858}
1866 1859
1867/* 1860/*
1868 * Access another process' address space. 1861 * Access another process' address space.
1869 * - source/target buffer must be kernel space 1862 * - source/target buffer must be kernel space
1870 */ 1863 */
1871int access_process_vm(struct task_struct *tsk, unsigned long addr, void *buf, int len, int write) 1864int access_process_vm(struct task_struct *tsk, unsigned long addr, void *buf, int len,
1865 unsigned int gup_flags)
1872{ 1866{
1873 struct mm_struct *mm; 1867 struct mm_struct *mm;
1874 1868
@@ -1879,7 +1873,7 @@ int access_process_vm(struct task_struct *tsk, unsigned long addr, void *buf, in
1879 if (!mm) 1873 if (!mm)
1880 return 0; 1874 return 0;
1881 1875
1882 len = __access_remote_vm(tsk, mm, addr, buf, len, write); 1876 len = __access_remote_vm(tsk, mm, addr, buf, len, gup_flags);
1883 1877
1884 mmput(mm); 1878 mmput(mm);
1885 return len; 1879 return len;
diff --git a/mm/process_vm_access.c b/mm/process_vm_access.c
index 07514d41ebcc..be8dc8d1edb9 100644
--- a/mm/process_vm_access.c
+++ b/mm/process_vm_access.c
@@ -88,12 +88,16 @@ static int process_vm_rw_single_vec(unsigned long addr,
88 ssize_t rc = 0; 88 ssize_t rc = 0;
89 unsigned long max_pages_per_loop = PVM_MAX_KMALLOC_PAGES 89 unsigned long max_pages_per_loop = PVM_MAX_KMALLOC_PAGES
90 / sizeof(struct pages *); 90 / sizeof(struct pages *);
91 unsigned int flags = FOLL_REMOTE;
91 92
92 /* Work out address and page range required */ 93 /* Work out address and page range required */
93 if (len == 0) 94 if (len == 0)
94 return 0; 95 return 0;
95 nr_pages = (addr + len - 1) / PAGE_SIZE - addr / PAGE_SIZE + 1; 96 nr_pages = (addr + len - 1) / PAGE_SIZE - addr / PAGE_SIZE + 1;
96 97
98 if (vm_write)
99 flags |= FOLL_WRITE;
100
97 while (!rc && nr_pages && iov_iter_count(iter)) { 101 while (!rc && nr_pages && iov_iter_count(iter)) {
98 int pages = min(nr_pages, max_pages_per_loop); 102 int pages = min(nr_pages, max_pages_per_loop);
99 size_t bytes; 103 size_t bytes;
@@ -104,8 +108,7 @@ static int process_vm_rw_single_vec(unsigned long addr,
104 * current/current->mm 108 * current/current->mm
105 */ 109 */
106 pages = __get_user_pages_unlocked(task, mm, pa, pages, 110 pages = __get_user_pages_unlocked(task, mm, pa, pages,
107 vm_write, 0, process_pages, 111 process_pages, flags);
108 FOLL_REMOTE);
109 if (pages <= 0) 112 if (pages <= 0)
110 return -EFAULT; 113 return -EFAULT;
111 114
diff --git a/mm/util.c b/mm/util.c
index 662cddf914af..1a41553db866 100644
--- a/mm/util.c
+++ b/mm/util.c
@@ -230,8 +230,10 @@ void __vma_link_list(struct mm_struct *mm, struct vm_area_struct *vma,
230} 230}
231 231
232/* Check if the vma is being used as a stack by this task */ 232/* Check if the vma is being used as a stack by this task */
233int vma_is_stack_for_task(struct vm_area_struct *vma, struct task_struct *t) 233int vma_is_stack_for_current(struct vm_area_struct *vma)
234{ 234{
235 struct task_struct * __maybe_unused t = current;
236
235 return (vma->vm_start <= KSTK_ESP(t) && vma->vm_end >= KSTK_ESP(t)); 237 return (vma->vm_start <= KSTK_ESP(t) && vma->vm_end >= KSTK_ESP(t));
236} 238}
237 239
@@ -283,7 +285,8 @@ EXPORT_SYMBOL_GPL(__get_user_pages_fast);
283int __weak get_user_pages_fast(unsigned long start, 285int __weak get_user_pages_fast(unsigned long start,
284 int nr_pages, int write, struct page **pages) 286 int nr_pages, int write, struct page **pages)
285{ 287{
286 return get_user_pages_unlocked(start, nr_pages, write, 0, pages); 288 return get_user_pages_unlocked(start, nr_pages, pages,
289 write ? FOLL_WRITE : 0);
287} 290}
288EXPORT_SYMBOL_GPL(get_user_pages_fast); 291EXPORT_SYMBOL_GPL(get_user_pages_fast);
289 292
@@ -623,7 +626,7 @@ int get_cmdline(struct task_struct *task, char *buffer, int buflen)
623 if (len > buflen) 626 if (len > buflen)
624 len = buflen; 627 len = buflen;
625 628
626 res = access_process_vm(task, arg_start, buffer, len, 0); 629 res = access_process_vm(task, arg_start, buffer, len, FOLL_FORCE);
627 630
628 /* 631 /*
629 * If the nul at the end of args has been overwritten, then 632 * If the nul at the end of args has been overwritten, then
@@ -638,7 +641,8 @@ int get_cmdline(struct task_struct *task, char *buffer, int buflen)
638 if (len > buflen - res) 641 if (len > buflen - res)
639 len = buflen - res; 642 len = buflen - res;
640 res += access_process_vm(task, env_start, 643 res += access_process_vm(task, env_start,
641 buffer+res, len, 0); 644 buffer+res, len,
645 FOLL_FORCE);
642 res = strnlen(buffer, res); 646 res = strnlen(buffer, res);
643 } 647 }
644 } 648 }
diff --git a/net/ceph/pagevec.c b/net/ceph/pagevec.c
index 00d2601407c5..1a7c9a79a53c 100644
--- a/net/ceph/pagevec.c
+++ b/net/ceph/pagevec.c
@@ -26,7 +26,7 @@ struct page **ceph_get_direct_page_vector(const void __user *data,
26 while (got < num_pages) { 26 while (got < num_pages) {
27 rc = get_user_pages_unlocked( 27 rc = get_user_pages_unlocked(
28 (unsigned long)data + ((unsigned long)got * PAGE_SIZE), 28 (unsigned long)data + ((unsigned long)got * PAGE_SIZE),
29 num_pages - got, write_page, 0, pages + got); 29 num_pages - got, pages + got, write_page ? FOLL_WRITE : 0);
30 if (rc < 0) 30 if (rc < 0)
31 break; 31 break;
32 BUG_ON(rc == 0); 32 BUG_ON(rc == 0);
diff --git a/security/selinux/hooks.c b/security/selinux/hooks.c
index 085057936287..09fd6108e421 100644
--- a/security/selinux/hooks.c
+++ b/security/selinux/hooks.c
@@ -3557,7 +3557,7 @@ static int selinux_file_mprotect(struct vm_area_struct *vma,
3557 } else if (!vma->vm_file && 3557 } else if (!vma->vm_file &&
3558 ((vma->vm_start <= vma->vm_mm->start_stack && 3558 ((vma->vm_start <= vma->vm_mm->start_stack &&
3559 vma->vm_end >= vma->vm_mm->start_stack) || 3559 vma->vm_end >= vma->vm_mm->start_stack) ||
3560 vma_is_stack_for_task(vma, current))) { 3560 vma_is_stack_for_current(vma))) {
3561 rc = current_has_perm(current, PROCESS__EXECSTACK); 3561 rc = current_has_perm(current, PROCESS__EXECSTACK);
3562 } else if (vma->vm_file && vma->anon_vma) { 3562 } else if (vma->vm_file && vma->anon_vma) {
3563 /* 3563 /*
diff --git a/security/tomoyo/domain.c b/security/tomoyo/domain.c
index ade7c6cad172..682b73af7766 100644
--- a/security/tomoyo/domain.c
+++ b/security/tomoyo/domain.c
@@ -881,7 +881,7 @@ bool tomoyo_dump_page(struct linux_binprm *bprm, unsigned long pos,
881 * the execve(). 881 * the execve().
882 */ 882 */
883 if (get_user_pages_remote(current, bprm->mm, pos, 1, 883 if (get_user_pages_remote(current, bprm->mm, pos, 1,
884 0, 1, &page, NULL) <= 0) 884 FOLL_FORCE, &page, NULL) <= 0)
885 return false; 885 return false;
886#else 886#else
887 page = bprm->page[pos / PAGE_SIZE]; 887 page = bprm->page[pos / PAGE_SIZE];
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index 1188bc849ee3..a39629206864 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -194,6 +194,8 @@
194#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ 194#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
195 195
196#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ 196#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
197#define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */
198#define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */
197 199
198/* Virtualization flags: Linux defined, word 8 */ 200/* Virtualization flags: Linux defined, word 8 */
199#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ 201#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
diff --git a/tools/objtool/arch/x86/decode.c b/tools/objtool/arch/x86/decode.c
index c0c0b265e88e..b63a31be1218 100644
--- a/tools/objtool/arch/x86/decode.c
+++ b/tools/objtool/arch/x86/decode.c
@@ -98,6 +98,15 @@ int arch_decode_instruction(struct elf *elf, struct section *sec,
98 *type = INSN_FP_SETUP; 98 *type = INSN_FP_SETUP;
99 break; 99 break;
100 100
101 case 0x8d:
102 if (insn.rex_prefix.bytes &&
103 insn.rex_prefix.bytes[0] == 0x48 &&
104 insn.modrm.nbytes && insn.modrm.bytes[0] == 0x2c &&
105 insn.sib.nbytes && insn.sib.bytes[0] == 0x24)
106 /* lea %(rsp), %rbp */
107 *type = INSN_FP_SETUP;
108 break;
109
101 case 0x90: 110 case 0x90:
102 *type = INSN_NOP; 111 *type = INSN_NOP;
103 break; 112 break;
diff --git a/tools/objtool/builtin-check.c b/tools/objtool/builtin-check.c
index 143b6cdd7f06..4490601a9235 100644
--- a/tools/objtool/builtin-check.c
+++ b/tools/objtool/builtin-check.c
@@ -97,6 +97,19 @@ static struct instruction *next_insn_same_sec(struct objtool_file *file,
97 return next; 97 return next;
98} 98}
99 99
100static bool gcov_enabled(struct objtool_file *file)
101{
102 struct section *sec;
103 struct symbol *sym;
104
105 list_for_each_entry(sec, &file->elf->sections, list)
106 list_for_each_entry(sym, &sec->symbol_list, list)
107 if (!strncmp(sym->name, "__gcov_.", 8))
108 return true;
109
110 return false;
111}
112
100#define for_each_insn(file, insn) \ 113#define for_each_insn(file, insn) \
101 list_for_each_entry(insn, &file->insn_list, list) 114 list_for_each_entry(insn, &file->insn_list, list)
102 115
@@ -713,6 +726,7 @@ static struct rela *find_switch_table(struct objtool_file *file,
713 struct instruction *insn) 726 struct instruction *insn)
714{ 727{
715 struct rela *text_rela, *rodata_rela; 728 struct rela *text_rela, *rodata_rela;
729 struct instruction *orig_insn = insn;
716 730
717 text_rela = find_rela_by_dest_range(insn->sec, insn->offset, insn->len); 731 text_rela = find_rela_by_dest_range(insn->sec, insn->offset, insn->len);
718 if (text_rela && text_rela->sym == file->rodata->sym) { 732 if (text_rela && text_rela->sym == file->rodata->sym) {
@@ -733,10 +747,16 @@ static struct rela *find_switch_table(struct objtool_file *file,
733 747
734 /* case 3 */ 748 /* case 3 */
735 func_for_each_insn_continue_reverse(file, func, insn) { 749 func_for_each_insn_continue_reverse(file, func, insn) {
736 if (insn->type == INSN_JUMP_UNCONDITIONAL || 750 if (insn->type == INSN_JUMP_DYNAMIC)
737 insn->type == INSN_JUMP_DYNAMIC)
738 break; 751 break;
739 752
753 /* allow small jumps within the range */
754 if (insn->type == INSN_JUMP_UNCONDITIONAL &&
755 insn->jump_dest &&
756 (insn->jump_dest->offset <= insn->offset ||
757 insn->jump_dest->offset >= orig_insn->offset))
758 break;
759
740 text_rela = find_rela_by_dest_range(insn->sec, insn->offset, 760 text_rela = find_rela_by_dest_range(insn->sec, insn->offset,
741 insn->len); 761 insn->len);
742 if (text_rela && text_rela->sym == file->rodata->sym) 762 if (text_rela && text_rela->sym == file->rodata->sym)
@@ -1034,34 +1054,6 @@ static int validate_branch(struct objtool_file *file,
1034 return 0; 1054 return 0;
1035} 1055}
1036 1056
1037static bool is_gcov_insn(struct instruction *insn)
1038{
1039 struct rela *rela;
1040 struct section *sec;
1041 struct symbol *sym;
1042 unsigned long offset;
1043
1044 rela = find_rela_by_dest_range(insn->sec, insn->offset, insn->len);
1045 if (!rela)
1046 return false;
1047
1048 if (rela->sym->type != STT_SECTION)
1049 return false;
1050
1051 sec = rela->sym->sec;
1052 offset = rela->addend + insn->offset + insn->len - rela->offset;
1053
1054 list_for_each_entry(sym, &sec->symbol_list, list) {
1055 if (sym->type != STT_OBJECT)
1056 continue;
1057
1058 if (offset >= sym->offset && offset < sym->offset + sym->len)
1059 return (!memcmp(sym->name, "__gcov0.", 8));
1060 }
1061
1062 return false;
1063}
1064
1065static bool is_kasan_insn(struct instruction *insn) 1057static bool is_kasan_insn(struct instruction *insn)
1066{ 1058{
1067 return (insn->type == INSN_CALL && 1059 return (insn->type == INSN_CALL &&
@@ -1083,9 +1075,6 @@ static bool ignore_unreachable_insn(struct symbol *func,
1083 if (insn->type == INSN_NOP) 1075 if (insn->type == INSN_NOP)
1084 return true; 1076 return true;
1085 1077
1086 if (is_gcov_insn(insn))
1087 return true;
1088
1089 /* 1078 /*
1090 * Check if this (or a subsequent) instruction is related to 1079 * Check if this (or a subsequent) instruction is related to
1091 * CONFIG_UBSAN or CONFIG_KASAN. 1080 * CONFIG_UBSAN or CONFIG_KASAN.
@@ -1146,6 +1135,19 @@ static int validate_functions(struct objtool_file *file)
1146 ignore_unreachable_insn(func, insn)) 1135 ignore_unreachable_insn(func, insn))
1147 continue; 1136 continue;
1148 1137
1138 /*
1139 * gcov produces a lot of unreachable
1140 * instructions. If we get an unreachable
1141 * warning and the file has gcov enabled, just
1142 * ignore it, and all other such warnings for
1143 * the file.
1144 */
1145 if (!file->ignore_unreachables &&
1146 gcov_enabled(file)) {
1147 file->ignore_unreachables = true;
1148 continue;
1149 }
1150
1149 WARN_FUNC("function has unreachable instruction", insn->sec, insn->offset); 1151 WARN_FUNC("function has unreachable instruction", insn->sec, insn->offset);
1150 warnings++; 1152 warnings++;
1151 } 1153 }
diff --git a/tools/perf/jvmti/Makefile b/tools/perf/jvmti/Makefile
index 5ce61a1bda9c..df14e6b67b63 100644
--- a/tools/perf/jvmti/Makefile
+++ b/tools/perf/jvmti/Makefile
@@ -36,7 +36,7 @@ SOLIBEXT=so
36# The following works at least on fedora 23, you may need the next 36# The following works at least on fedora 23, you may need the next
37# line for other distros. 37# line for other distros.
38ifneq (,$(wildcard /usr/sbin/update-java-alternatives)) 38ifneq (,$(wildcard /usr/sbin/update-java-alternatives))
39JDIR=$(shell /usr/sbin/update-java-alternatives -l | head -1 | cut -d ' ' -f 3) 39JDIR=$(shell /usr/sbin/update-java-alternatives -l | head -1 | awk '{print $$3}')
40else 40else
41 ifneq (,$(wildcard /usr/sbin/alternatives)) 41 ifneq (,$(wildcard /usr/sbin/alternatives))
42 JDIR=$(shell alternatives --display java | tail -1 | cut -d' ' -f 5 | sed 's%/jre/bin/java.%%g') 42 JDIR=$(shell alternatives --display java | tail -1 | cut -d' ' -f 5 | sed 's%/jre/bin/java.%%g')
diff --git a/tools/perf/ui/browsers/hists.c b/tools/perf/ui/browsers/hists.c
index fb8e42c7507a..4ffff7be9299 100644
--- a/tools/perf/ui/browsers/hists.c
+++ b/tools/perf/ui/browsers/hists.c
@@ -601,7 +601,8 @@ int hist_browser__run(struct hist_browser *browser, const char *help)
601 u64 nr_entries; 601 u64 nr_entries;
602 hbt->timer(hbt->arg); 602 hbt->timer(hbt->arg);
603 603
604 if (hist_browser__has_filter(browser)) 604 if (hist_browser__has_filter(browser) ||
605 symbol_conf.report_hierarchy)
605 hist_browser__update_nr_entries(browser); 606 hist_browser__update_nr_entries(browser);
606 607
607 nr_entries = hist_browser__nr_entries(browser); 608 nr_entries = hist_browser__nr_entries(browser);
diff --git a/tools/perf/util/header.c b/tools/perf/util/header.c
index 85dd0db0a127..2f3eded54b0c 100644
--- a/tools/perf/util/header.c
+++ b/tools/perf/util/header.c
@@ -1895,7 +1895,6 @@ static int process_numa_topology(struct perf_file_section *section __maybe_unuse
1895 if (ph->needs_swap) 1895 if (ph->needs_swap)
1896 nr = bswap_32(nr); 1896 nr = bswap_32(nr);
1897 1897
1898 ph->env.nr_numa_nodes = nr;
1899 nodes = zalloc(sizeof(*nodes) * nr); 1898 nodes = zalloc(sizeof(*nodes) * nr);
1900 if (!nodes) 1899 if (!nodes)
1901 return -ENOMEM; 1900 return -ENOMEM;
@@ -1932,6 +1931,7 @@ static int process_numa_topology(struct perf_file_section *section __maybe_unuse
1932 1931
1933 free(str); 1932 free(str);
1934 } 1933 }
1934 ph->env.nr_numa_nodes = nr;
1935 ph->env.numa_nodes = nodes; 1935 ph->env.numa_nodes = nodes;
1936 return 0; 1936 return 0;
1937 1937
diff --git a/tools/perf/util/parse-events.l b/tools/perf/util/parse-events.l
index 9f43fda2570f..660fca05bc93 100644
--- a/tools/perf/util/parse-events.l
+++ b/tools/perf/util/parse-events.l
@@ -136,8 +136,8 @@ do { \
136group [^,{}/]*[{][^}]*[}][^,{}/]* 136group [^,{}/]*[{][^}]*[}][^,{}/]*
137event_pmu [^,{}/]+[/][^/]*[/][^,{}/]* 137event_pmu [^,{}/]+[/][^/]*[/][^,{}/]*
138event [^,{}/]+ 138event [^,{}/]+
139bpf_object .*\.(o|bpf) 139bpf_object [^,{}]+\.(o|bpf)
140bpf_source .*\.c 140bpf_source [^,{}]+\.c
141 141
142num_dec [0-9]+ 142num_dec [0-9]+
143num_hex 0x[a-fA-F0-9]+ 143num_hex 0x[a-fA-F0-9]+
diff --git a/virt/kvm/async_pf.c b/virt/kvm/async_pf.c
index db9668869f6f..8035cc1eb955 100644
--- a/virt/kvm/async_pf.c
+++ b/virt/kvm/async_pf.c
@@ -84,7 +84,8 @@ static void async_pf_execute(struct work_struct *work)
84 * mm and might be done in another context, so we must 84 * mm and might be done in another context, so we must
85 * use FOLL_REMOTE. 85 * use FOLL_REMOTE.
86 */ 86 */
87 __get_user_pages_unlocked(NULL, mm, addr, 1, 1, 0, NULL, FOLL_REMOTE); 87 __get_user_pages_unlocked(NULL, mm, addr, 1, NULL,
88 FOLL_WRITE | FOLL_REMOTE);
88 89
89 kvm_async_page_present_sync(vcpu, apf); 90 kvm_async_page_present_sync(vcpu, apf);
90 91
diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c
index 81dfc73d3df3..28510e72618a 100644
--- a/virt/kvm/kvm_main.c
+++ b/virt/kvm/kvm_main.c
@@ -1416,10 +1416,15 @@ static int hva_to_pfn_slow(unsigned long addr, bool *async, bool write_fault,
1416 down_read(&current->mm->mmap_sem); 1416 down_read(&current->mm->mmap_sem);
1417 npages = get_user_page_nowait(addr, write_fault, page); 1417 npages = get_user_page_nowait(addr, write_fault, page);
1418 up_read(&current->mm->mmap_sem); 1418 up_read(&current->mm->mmap_sem);
1419 } else 1419 } else {
1420 unsigned int flags = FOLL_TOUCH | FOLL_HWPOISON;
1421
1422 if (write_fault)
1423 flags |= FOLL_WRITE;
1424
1420 npages = __get_user_pages_unlocked(current, current->mm, addr, 1, 1425 npages = __get_user_pages_unlocked(current, current->mm, addr, 1,
1421 write_fault, 0, page, 1426 page, flags);
1422 FOLL_TOUCH|FOLL_HWPOISON); 1427 }
1423 if (npages != 1) 1428 if (npages != 1)
1424 return npages; 1429 return npages;
1425 1430