1 files changed, 181 insertions, 73 deletions

diff --git a/tools/include/uapi/drm/i915_drm.h b/tools/include/uapi/drm/i915_drm.h
index 397810fa2d33..3a73f5316766 100644
--- a/tools/include/uapi/drm/i915_drm.h
+++ b/tools/include/uapi/drm/i915_drm.h
@@ -63,6 +63,28 @@ extern "C" {
 #define I915_RESET_UEVENT               "RESET"
 
 /*
+ * i915_user_extension: Base class for defining a chain of extensions
+ *
+ * Many interfaces need to grow over time. In most cases we can simply
+ * extend the struct and have userspace pass in more data. Another option,
+ * as demonstrated by Vulkan's approach to providing extensions for forward
+ * and backward compatibility, is to use a list of optional structs to
+ * provide those extra details.
+ *
+ * The key advantage to using an extension chain is that it allows us to
+ * redefine the interface more easily than an ever growing struct of
+ * increasing complexity, and for large parts of that interface to be
+ * entirely optional. The downside is more pointer chasing; chasing across
+ * the __user boundary with pointers encapsulated inside u64.
+ */
+struct i915_user_extension {
+        __u64 next_extension;
+        __u32 name;
+        __u32 flags; /* All undefined bits must be zero. */
+        __u32 rsvd[4]; /* Reserved for future use; must be zero. */
+};
+
+/*
  * MOCS indexes used for GPU surfaces, defining the cacheability of the
  * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
  */
@@ -99,9 +121,23 @@ enum drm_i915_gem_engine_class {
         I915_ENGINE_CLASS_VIDEO         = 2,
         I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
 
+        /* should be kept compact */
+
         I915_ENGINE_CLASS_INVALID       = -1
 };
 
+/*
+ * There may be more than one engine fulfilling any role within the system.
+ * Each engine of a class is given a unique instance number and therefore
+ * any engine can be specified by its class:instance tuplet. APIs that allow
+ * access to any engine in the system will use struct i915_engine_class_instance
+ * for this identification.
+ */
+struct i915_engine_class_instance {
+        __u16 engine_class; /* see enum drm_i915_gem_engine_class */
+        __u16 engine_instance;
+};
+
 /**
  * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
  *
@@ -319,6 +355,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_PERF_ADD_CONFIG        0x37
 #define DRM_I915_PERF_REMOVE_CONFIG     0x38
 #define DRM_I915_QUERY                  0x39
+/* Must be kept compact -- no holes */
 
 #define DRM_IOCTL_I915_INIT             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH            DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -367,6 +404,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
 #define DRM_IOCTL_I915_GEM_WAIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE       DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
+#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY      DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
 #define DRM_IOCTL_I915_REG_READ                 DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
 #define DRM_IOCTL_I915_GET_RESET_STATS          DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
@@ -476,6 +514,7 @@ typedef struct drm_i915_irq_wait {
 #define   I915_SCHEDULER_CAP_ENABLED    (1ul << 0)
 #define   I915_SCHEDULER_CAP_PRIORITY   (1ul << 1)
 #define   I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
+#define   I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
 
 #define I915_PARAM_HUC_STATUS            42
 
@@ -559,6 +598,8 @@ typedef struct drm_i915_irq_wait {
  */
 #define I915_PARAM_MMAP_GTT_COHERENT    52
 
+/* Must be kept compact -- no holes and well documented */
+
 typedef struct drm_i915_getparam {
         __s32 param;
         /*
@@ -574,6 +615,7 @@ typedef struct drm_i915_getparam {
 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
 #define I915_SETPARAM_ALLOW_BATCHBUFFER                   3
 #define I915_SETPARAM_NUM_USED_FENCES                     4
+/* Must be kept compact -- no holes */
 
 typedef struct drm_i915_setparam {
         int param;
@@ -972,7 +1014,7 @@ struct drm_i915_gem_execbuffer2 {
          * struct drm_i915_gem_exec_fence *fences.
          */
         __u64 cliprects_ptr;
-#define I915_EXEC_RING_MASK              (7<<0)
+#define I915_EXEC_RING_MASK              (0x3f)
 #define I915_EXEC_DEFAULT                (0<<0)
 #define I915_EXEC_RENDER                 (1<<0)
 #define I915_EXEC_BSD                    (2<<0)
@@ -1120,32 +1162,34 @@ struct drm_i915_gem_busy {
          * as busy may become idle before the ioctl is completed.
          *
          * Furthermore, if the object is busy, which engine is busy is only
-         * provided as a guide. There are race conditions which prevent the
-         * report of which engines are busy from being always accurate.
-         * However, the converse is not true. If the object is idle, the
-         * result of the ioctl, that all engines are idle, is accurate.
+         * provided as a guide and only indirectly by reporting its class
+         * (there may be more than one engine in each class). There are race
+         * conditions which prevent the report of which engines are busy from
+         * being always accurate.  However, the converse is not true. If the
+         * object is idle, the result of the ioctl, that all engines are idle,
+         * is accurate.
          *
          * The returned dword is split into two fields to indicate both
-         * the engines on which the object is being read, and the
-         * engine on which it is currently being written (if any).
+         * the engine classess on which the object is being read, and the
+         * engine class on which it is currently being written (if any).
          *
          * The low word (bits 0:15) indicate if the object is being written
          * to by any engine (there can only be one, as the GEM implicit
          * synchronisation rules force writes to be serialised). Only the
-         * engine for the last write is reported.
+         * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
+         * 1 not 0 etc) for the last write is reported.
          *
-         * The high word (bits 16:31) are a bitmask of which engines are
-         * currently reading from the object. Multiple engines may be
+         * The high word (bits 16:31) are a bitmask of which engines classes
+         * are currently reading from the object. Multiple engines may be
          * reading from the object simultaneously.
          *
-         * The value of each engine is the same as specified in the
-         * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc.
-         * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to
-         * the I915_EXEC_RENDER engine for execution, and so it is never
+         * The value of each engine class is the same as specified in the
+         * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
+         * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
          * reported as active itself. Some hardware may have parallel
          * execution engines, e.g. multiple media engines, which are
-         * mapped to the same identifier in the EXECBUFFER2 ioctl and
-         * so are not separately reported for busyness.
+         * mapped to the same class identifier and so are not separately
+         * reported for busyness.
          *
          * Caveat emptor:
          * Only the boolean result of this query is reliable; that is whether
@@ -1412,65 +1456,17 @@ struct drm_i915_gem_wait {
 };
 
 struct drm_i915_gem_context_create {
-        /*  output: id of new context*/
-        __u32 ctx_id;
-        __u32 pad;
-};
-
-struct drm_i915_gem_context_destroy {
-        __u32 ctx_id;
+        __u32 ctx_id; /* output: id of new context*/
         __u32 pad;
 };
 
-struct drm_i915_reg_read {
-        /*
-         * Register offset.
-         * For 64bit wide registers where the upper 32bits don't immediately
-         * follow the lower 32bits, the offset of the lower 32bits must
-         * be specified
-         */
-        __u64 offset;
-#define I915_REG_READ_8B_WA (1ul << 0)
-
-        __u64 val; /* Return value */
-};
-/* Known registers:
- *
- * Render engine timestamp - 0x2358 + 64bit - gen7+
- * - Note this register returns an invalid value if using the default
- *   single instruction 8byte read, in order to workaround that pass
- *   flag I915_REG_READ_8B_WA in offset field.
- *
- */
-
-struct drm_i915_reset_stats {
-        __u32 ctx_id;
-        __u32 flags;
-
-        /* All resets since boot/module reload, for all contexts */
-        __u32 reset_count;
-
-        /* Number of batches lost when active in GPU, for this context */
-        __u32 batch_active;
-
-        /* Number of batches lost pending for execution, for this context */
-        __u32 batch_pending;
-
-        __u32 pad;
-};
-
-struct drm_i915_gem_userptr {
-        __u64 user_ptr;
-        __u64 user_size;
+struct drm_i915_gem_context_create_ext {
+        __u32 ctx_id; /* output: id of new context*/
         __u32 flags;
-#define I915_USERPTR_READ_ONLY 0x1
-#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
-        /**
-         * Returned handle for the object.
-         *
-         * Object handles are nonzero.
-         */
-        __u32 handle;
+#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS        (1u << 0)
+#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
+        (-(I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS << 1))
+        __u64 extensions;
 };
 
 struct drm_i915_gem_context_param {
@@ -1491,6 +1487,28 @@ struct drm_i915_gem_context_param {
          * drm_i915_gem_context_param_sseu.
          */
 #define I915_CONTEXT_PARAM_SSEU         0x7
+
+/*
+ * Not all clients may want to attempt automatic recover of a context after
+ * a hang (for example, some clients may only submit very small incremental
+ * batches relying on known logical state of previous batches which will never
+ * recover correctly and each attempt will hang), and so would prefer that
+ * the context is forever banned instead.
+ *
+ * If set to false (0), after a reset, subsequent (and in flight) rendering
+ * from this context is discarded, and the client will need to create a new
+ * context to use instead.
+ *
+ * If set to true (1), the kernel will automatically attempt to recover the
+ * context by skipping the hanging batch and executing the next batch starting
+ * from the default context state (discarding the incomplete logical context
+ * state lost due to the reset).
+ *
+ * On creation, all new contexts are marked as recoverable.
+ */
+#define I915_CONTEXT_PARAM_RECOVERABLE  0x8
+/* Must be kept compact -- no holes and well documented */
+
         __u64 value;
 };
 
@@ -1519,8 +1537,7 @@ struct drm_i915_gem_context_param_sseu {
         /*
          * Engine class & instance to be configured or queried.
          */
-        __u16 engine_class;
-        __u16 engine_instance;
+        struct i915_engine_class_instance engine;
 
         /*
          * Unused for now. Must be cleared to zero.
@@ -1553,6 +1570,96 @@ struct drm_i915_gem_context_param_sseu {
         __u32 rsvd;
 };
 
+struct drm_i915_gem_context_create_ext_setparam {
+#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
+        struct i915_user_extension base;
+        struct drm_i915_gem_context_param param;
+};
+
+struct drm_i915_gem_context_destroy {
+        __u32 ctx_id;
+        __u32 pad;
+};
+
+/*
+ * DRM_I915_GEM_VM_CREATE -
+ *
+ * Create a new virtual memory address space (ppGTT) for use within a context
+ * on the same file. Extensions can be provided to configure exactly how the
+ * address space is setup upon creation.
+ *
+ * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
+ * returned in the outparam @id.
+ *
+ * No flags are defined, with all bits reserved and must be zero.
+ *
+ * An extension chain maybe provided, starting with @extensions, and terminated
+ * by the @next_extension being 0. Currently, no extensions are defined.
+ *
+ * DRM_I915_GEM_VM_DESTROY -
+ *
+ * Destroys a previously created VM id, specified in @id.
+ *
+ * No extensions or flags are allowed currently, and so must be zero.
+ */
+struct drm_i915_gem_vm_control {
+        __u64 extensions;
+        __u32 flags;
+        __u32 vm_id;
+};
+
+struct drm_i915_reg_read {
+        /*
+         * Register offset.
+         * For 64bit wide registers where the upper 32bits don't immediately
+         * follow the lower 32bits, the offset of the lower 32bits must
+         * be specified
+         */
+        __u64 offset;
+#define I915_REG_READ_8B_WA (1ul << 0)
+
+        __u64 val; /* Return value */
+};
+
+/* Known registers:
+ *
+ * Render engine timestamp - 0x2358 + 64bit - gen7+
+ * - Note this register returns an invalid value if using the default
+ *   single instruction 8byte read, in order to workaround that pass
+ *   flag I915_REG_READ_8B_WA in offset field.
+ *
+ */
+
+struct drm_i915_reset_stats {
+        __u32 ctx_id;
+        __u32 flags;
+
+        /* All resets since boot/module reload, for all contexts */
+        __u32 reset_count;
+
+        /* Number of batches lost when active in GPU, for this context */
+        __u32 batch_active;
+
+        /* Number of batches lost pending for execution, for this context */
+        __u32 batch_pending;
+
+        __u32 pad;
+};
+
+struct drm_i915_gem_userptr {
+        __u64 user_ptr;
+        __u64 user_size;
+        __u32 flags;
+#define I915_USERPTR_READ_ONLY 0x1
+#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
+        /**
+         * Returned handle for the object.
+         *
+         * Object handles are nonzero.
+         */
+        __u32 handle;
+};
+
 enum drm_i915_oa_format {
         I915_OA_FORMAT_A13 = 1,     /* HSW only */
         I915_OA_FORMAT_A29,         /* HSW only */
@@ -1714,6 +1821,7 @@ struct drm_i915_perf_oa_config {
 struct drm_i915_query_item {
         __u64 query_id;
 #define DRM_I915_QUERY_TOPOLOGY_INFO    1
+/* Must be kept compact -- no holes and well documented */
 
         /*
          * When set to zero by userspace, this is filled with the size of the