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-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-tm2.dts11
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433.dtsi22
2 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index 8eb59adc2bc4..6f506dd11714 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -196,6 +196,17 @@
196 <&cmu_top CLK_ACLK_GSCL_333>; 196 <&cmu_top CLK_ACLK_GSCL_333>;
197}; 197};
198 198
199&cmu_mscl {
200 assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
201 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
202 <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
203 <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
204 assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
205 <&cmu_top CLK_SCLK_JPEG_MSCL>,
206 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
207 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
208};
209
199&cpu0 { 210&cpu0 {
200 cpu-supply = <&buck3_reg>; 211 cpu-supply = <&buck3_reg>;
201}; 212};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 945b2502a4ca..1d47480f4104 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -844,6 +844,18 @@
844 iommus = <&sysmmu_gscl2>; 844 iommus = <&sysmmu_gscl2>;
845 }; 845 };
846 846
847 jpeg: codec@15020000 {
848 compatible = "samsung,exynos5433-jpeg";
849 reg = <0x15020000 0x10000>;
850 interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
851 clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
852 clocks = <&cmu_mscl CLK_PCLK_JPEG>,
853 <&cmu_mscl CLK_ACLK_JPEG>,
854 <&cmu_mscl CLK_ACLK_XIU_MSCLX>,
855 <&cmu_mscl CLK_SCLK_JPEG>;
856 iommus = <&sysmmu_jpeg>;
857 };
858
847 sysmmu_decon0x: sysmmu@0x13a00000 { 859 sysmmu_decon0x: sysmmu@0x13a00000 {
848 compatible = "samsung,exynos-sysmmu"; 860 compatible = "samsung,exynos-sysmmu";
849 reg = <0x13a00000 0x1000>; 861 reg = <0x13a00000 0x1000>;
@@ -894,6 +906,16 @@
894 #iommu-cells = <0>; 906 #iommu-cells = <0>;
895 }; 907 };
896 908
909 sysmmu_jpeg: sysmmu@0x15060000 {
910 compatible = "samsung,exynos-sysmmu";
911 reg = <0x15060000 0x1000>;
912 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
913 clock-names = "pclk", "aclk";
914 clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>,
915 <&cmu_mscl CLK_ACLK_SMMU_JPEG>;
916 #iommu-cells = <0>;
917 };
918
897 serial_0: serial@14c10000 { 919 serial_0: serial@14c10000 {
898 compatible = "samsung,exynos5433-uart"; 920 compatible = "samsung,exynos5433-uart";
899 reg = <0x14c10000 0x100>; 921 reg = <0x14c10000 0x100>;