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-rw-r--r--drivers/staging/Kconfig2
-rw-r--r--drivers/staging/Makefile1
-rw-r--r--drivers/staging/sm7xxfb/Kconfig13
-rw-r--r--drivers/staging/sm7xxfb/Makefile1
-rw-r--r--drivers/staging/sm7xxfb/TODO9
-rw-r--r--drivers/staging/sm7xxfb/sm7xx.h779
-rw-r--r--drivers/staging/sm7xxfb/sm7xxfb.c1026
7 files changed, 0 insertions, 1831 deletions
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index babb1cf67ce7..40e5ca971a9c 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -82,8 +82,6 @@ source "drivers/staging/wlags49_h2/Kconfig"
82 82
83source "drivers/staging/wlags49_h25/Kconfig" 83source "drivers/staging/wlags49_h25/Kconfig"
84 84
85source "drivers/staging/sm7xxfb/Kconfig"
86
87source "drivers/staging/crystalhd/Kconfig" 85source "drivers/staging/crystalhd/Kconfig"
88 86
89source "drivers/staging/cxt1e1/Kconfig" 87source "drivers/staging/cxt1e1/Kconfig"
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index 2c4949a9bd9b..00735bbbd0fd 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -35,7 +35,6 @@ obj-$(CONFIG_DX_SEP) += sep/
35obj-$(CONFIG_IIO) += iio/ 35obj-$(CONFIG_IIO) += iio/
36obj-$(CONFIG_WLAGS49_H2) += wlags49_h2/ 36obj-$(CONFIG_WLAGS49_H2) += wlags49_h2/
37obj-$(CONFIG_WLAGS49_H25) += wlags49_h25/ 37obj-$(CONFIG_WLAGS49_H25) += wlags49_h25/
38obj-$(CONFIG_FB_SM7XX) += sm7xxfb/
39obj-$(CONFIG_CRYSTALHD) += crystalhd/ 38obj-$(CONFIG_CRYSTALHD) += crystalhd/
40obj-$(CONFIG_CXT1E1) += cxt1e1/ 39obj-$(CONFIG_CXT1E1) += cxt1e1/
41obj-$(CONFIG_FB_XGI) += xgifb/ 40obj-$(CONFIG_FB_XGI) += xgifb/
diff --git a/drivers/staging/sm7xxfb/Kconfig b/drivers/staging/sm7xxfb/Kconfig
deleted file mode 100644
index e2922ae3a3ee..000000000000
--- a/drivers/staging/sm7xxfb/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
1config FB_SM7XX
2 tristate "Silicon Motion SM7XX framebuffer support"
3 depends on FB && PCI
4 select FB_CFB_FILLRECT
5 select FB_CFB_COPYAREA
6 select FB_CFB_IMAGEBLIT
7 help
8 Frame buffer driver for the Silicon Motion SM710, SM712, SM721
9 and SM722 chips.
10
11 This driver is also available as a module. The module will be
12 called sm7xxfb. If you want to compile it as a module, say M
13 here and read <file:Documentation/kbuild/modules.txt>.
diff --git a/drivers/staging/sm7xxfb/Makefile b/drivers/staging/sm7xxfb/Makefile
deleted file mode 100644
index 48f471cf9f36..000000000000
--- a/drivers/staging/sm7xxfb/Makefile
+++ /dev/null
@@ -1 +0,0 @@
1obj-$(CONFIG_FB_SM7XX) += sm7xxfb.o
diff --git a/drivers/staging/sm7xxfb/TODO b/drivers/staging/sm7xxfb/TODO
deleted file mode 100644
index 1fcead591c16..000000000000
--- a/drivers/staging/sm7xxfb/TODO
+++ /dev/null
@@ -1,9 +0,0 @@
1TODO:
2- Dual head support
3- 2D acceleration support
4- use kernel coding style
5- refine the code and remove unused code
6- move it to drivers/video/sm7xxfb.c
7
8Please send any patches to Greg Kroah-Hartman <greg@kroah.com> and
9Teddy Wang <teddy.wang@siliconmotion.com.cn>.
diff --git a/drivers/staging/sm7xxfb/sm7xx.h b/drivers/staging/sm7xxfb/sm7xx.h
deleted file mode 100644
index 85998615b801..000000000000
--- a/drivers/staging/sm7xxfb/sm7xx.h
+++ /dev/null
@@ -1,779 +0,0 @@
1/*
2 * Silicon Motion SM712 frame buffer device
3 *
4 * Copyright (C) 2006 Silicon Motion Technology Corp.
5 * Authors: Ge Wang, gewang@siliconmotion.com
6 * Boyod boyod.yang@siliconmotion.com.cn
7 *
8 * Copyright (C) 2009 Lemote, Inc.
9 * Author: Wu Zhangjin, wuzhangjin@gmail.com
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main directory of this archive for
13 * more details.
14 */
15
16#define NR_PALETTE 256
17
18#define FB_ACCEL_SMI_LYNX 88
19
20#define SCREEN_X_RES 1024
21#define SCREEN_Y_RES 600
22#define SCREEN_BPP 16
23
24/*Assume SM712 graphics chip has 4MB VRAM */
25#define SM712_VIDEOMEMORYSIZE 0x00400000
26/*Assume SM722 graphics chip has 8MB VRAM */
27#define SM722_VIDEOMEMORYSIZE 0x00800000
28
29#define dac_reg (0x3c8)
30#define dac_val (0x3c9)
31
32extern void __iomem *smtc_RegBaseAddress;
33#define smtc_mmiowb(dat, reg) writeb(dat, smtc_RegBaseAddress + reg)
34#define smtc_mmioww(dat, reg) writew(dat, smtc_RegBaseAddress + reg)
35#define smtc_mmiowl(dat, reg) writel(dat, smtc_RegBaseAddress + reg)
36
37#define smtc_mmiorb(reg) readb(smtc_RegBaseAddress + reg)
38#define smtc_mmiorw(reg) readw(smtc_RegBaseAddress + reg)
39#define smtc_mmiorl(reg) readl(smtc_RegBaseAddress + reg)
40
41#define SIZE_SR00_SR04 (0x04 - 0x00 + 1)
42#define SIZE_SR10_SR24 (0x24 - 0x10 + 1)
43#define SIZE_SR30_SR75 (0x75 - 0x30 + 1)
44#define SIZE_SR80_SR93 (0x93 - 0x80 + 1)
45#define SIZE_SRA0_SRAF (0xAF - 0xA0 + 1)
46#define SIZE_GR00_GR08 (0x08 - 0x00 + 1)
47#define SIZE_AR00_AR14 (0x14 - 0x00 + 1)
48#define SIZE_CR00_CR18 (0x18 - 0x00 + 1)
49#define SIZE_CR30_CR4D (0x4D - 0x30 + 1)
50#define SIZE_CR90_CRA7 (0xA7 - 0x90 + 1)
51#define SIZE_VPR (0x6C + 1)
52#define SIZE_DPR (0x44 + 1)
53
54static inline void smtc_crtcw(int reg, int val)
55{
56 smtc_mmiowb(reg, 0x3d4);
57 smtc_mmiowb(val, 0x3d5);
58}
59
60static inline unsigned int smtc_crtcr(int reg)
61{
62 smtc_mmiowb(reg, 0x3d4);
63 return smtc_mmiorb(0x3d5);
64}
65
66static inline void smtc_grphw(int reg, int val)
67{
68 smtc_mmiowb(reg, 0x3ce);
69 smtc_mmiowb(val, 0x3cf);
70}
71
72static inline unsigned int smtc_grphr(int reg)
73{
74 smtc_mmiowb(reg, 0x3ce);
75 return smtc_mmiorb(0x3cf);
76}
77
78static inline void smtc_attrw(int reg, int val)
79{
80 smtc_mmiorb(0x3da);
81 smtc_mmiowb(reg, 0x3c0);
82 smtc_mmiorb(0x3c1);
83 smtc_mmiowb(val, 0x3c0);
84}
85
86static inline void smtc_seqw(int reg, int val)
87{
88 smtc_mmiowb(reg, 0x3c4);
89 smtc_mmiowb(val, 0x3c5);
90}
91
92static inline unsigned int smtc_seqr(int reg)
93{
94 smtc_mmiowb(reg, 0x3c4);
95 return smtc_mmiorb(0x3c5);
96}
97
98/* The next structure holds all information relevant for a specific video mode.
99 */
100
101struct ModeInit {
102 int mmSizeX;
103 int mmSizeY;
104 int bpp;
105 int hz;
106 unsigned char Init_MISC;
107 unsigned char Init_SR00_SR04[SIZE_SR00_SR04];
108 unsigned char Init_SR10_SR24[SIZE_SR10_SR24];
109 unsigned char Init_SR30_SR75[SIZE_SR30_SR75];
110 unsigned char Init_SR80_SR93[SIZE_SR80_SR93];
111 unsigned char Init_SRA0_SRAF[SIZE_SRA0_SRAF];
112 unsigned char Init_GR00_GR08[SIZE_GR00_GR08];
113 unsigned char Init_AR00_AR14[SIZE_AR00_AR14];
114 unsigned char Init_CR00_CR18[SIZE_CR00_CR18];
115 unsigned char Init_CR30_CR4D[SIZE_CR30_CR4D];
116 unsigned char Init_CR90_CRA7[SIZE_CR90_CRA7];
117};
118
119/**********************************************************************
120 SM712 Mode table.
121 **********************************************************************/
122struct ModeInit VGAMode[] = {
123 {
124 /* mode#0: 640 x 480 16Bpp 60Hz */
125 640, 480, 16, 60,
126 /* Init_MISC */
127 0xE3,
128 { /* Init_SR0_SR4 */
129 0x03, 0x01, 0x0F, 0x00, 0x0E,
130 },
131 { /* Init_SR10_SR24 */
132 0xFF, 0xBE, 0xEF, 0xFF, 0x00, 0x0E, 0x17, 0x2C,
133 0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
134 0xC4, 0x30, 0x02, 0x01, 0x01,
135 },
136 { /* Init_SR30_SR75 */
137 0x32, 0x03, 0xA0, 0x09, 0xC0, 0x32, 0x32, 0x32,
138 0x32, 0x32, 0x32, 0x32, 0x00, 0x00, 0x03, 0xFF,
139 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
140 0x20, 0x0C, 0x44, 0x20, 0x00, 0x32, 0x32, 0x32,
141 0x04, 0x24, 0x63, 0x4F, 0x52, 0x0B, 0xDF, 0xEA,
142 0x04, 0x50, 0x19, 0x32, 0x32, 0x00, 0x00, 0x32,
143 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
144 0x50, 0x03, 0x74, 0x14, 0x07, 0x82, 0x07, 0x04,
145 0x00, 0x45, 0x30, 0x30, 0x40, 0x30,
146 },
147 { /* Init_SR80_SR93 */
148 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x32,
149 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x32, 0x32,
150 0x00, 0x00, 0x00, 0x00,
151 },
152 { /* Init_SRA0_SRAF */
153 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED,
154 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xFF, 0xDF,
155 },
156 { /* Init_GR00_GR08 */
157 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
158 0xFF,
159 },
160 { /* Init_AR00_AR14 */
161 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
162 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
163 0x41, 0x00, 0x0F, 0x00, 0x00,
164 },
165 { /* Init_CR00_CR18 */
166 0x5F, 0x4F, 0x4F, 0x00, 0x53, 0x1F, 0x0B, 0x3E,
167 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
168 0xEA, 0x0C, 0xDF, 0x50, 0x40, 0xDF, 0x00, 0xE3,
169 0xFF,
170 },
171 { /* Init_CR30_CR4D */
172 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x03, 0x20,
173 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xFF, 0xFD,
174 0x5F, 0x4F, 0x00, 0x54, 0x00, 0x0B, 0xDF, 0x00,
175 0xEA, 0x0C, 0x2E, 0x00, 0x4F, 0xDF,
176 },
177 { /* Init_CR90_CRA7 */
178 0x56, 0xDD, 0x5E, 0xEA, 0x87, 0x44, 0x8F, 0x55,
179 0x0A, 0x8F, 0x55, 0x0A, 0x00, 0x00, 0x18, 0x00,
180 0x11, 0x10, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x00,
181 },
182 },
183 {
184 /* mode#1: 640 x 480 24Bpp 60Hz */
185 640, 480, 24, 60,
186 /* Init_MISC */
187 0xE3,
188 { /* Init_SR0_SR4 */
189 0x03, 0x01, 0x0F, 0x00, 0x0E,
190 },
191 { /* Init_SR10_SR24 */
192 0xFF, 0xBE, 0xEF, 0xFF, 0x00, 0x0E, 0x17, 0x2C,
193 0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
194 0xC4, 0x30, 0x02, 0x01, 0x01,
195 },
196 { /* Init_SR30_SR75 */
197 0x32, 0x03, 0xA0, 0x09, 0xC0, 0x32, 0x32, 0x32,
198 0x32, 0x32, 0x32, 0x32, 0x00, 0x00, 0x03, 0xFF,
199 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
200 0x20, 0x0C, 0x44, 0x20, 0x00, 0x32, 0x32, 0x32,
201 0x04, 0x24, 0x63, 0x4F, 0x52, 0x0B, 0xDF, 0xEA,
202 0x04, 0x50, 0x19, 0x32, 0x32, 0x00, 0x00, 0x32,
203 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
204 0x50, 0x03, 0x74, 0x14, 0x07, 0x82, 0x07, 0x04,
205 0x00, 0x45, 0x30, 0x30, 0x40, 0x30,
206 },
207 { /* Init_SR80_SR93 */
208 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x32,
209 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x32, 0x32,
210 0x00, 0x00, 0x00, 0x00,
211 },
212 { /* Init_SRA0_SRAF */
213 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED,
214 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xFF, 0xDF,
215 },
216 { /* Init_GR00_GR08 */
217 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
218 0xFF,
219 },
220 { /* Init_AR00_AR14 */
221 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
222 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
223 0x41, 0x00, 0x0F, 0x00, 0x00,
224 },
225 { /* Init_CR00_CR18 */
226 0x5F, 0x4F, 0x4F, 0x00, 0x53, 0x1F, 0x0B, 0x3E,
227 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
228 0xEA, 0x0C, 0xDF, 0x50, 0x40, 0xDF, 0x00, 0xE3,
229 0xFF,
230 },
231 { /* Init_CR30_CR4D */
232 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x03, 0x20,
233 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xFF, 0xFD,
234 0x5F, 0x4F, 0x00, 0x54, 0x00, 0x0B, 0xDF, 0x00,
235 0xEA, 0x0C, 0x2E, 0x00, 0x4F, 0xDF,
236 },
237 { /* Init_CR90_CRA7 */
238 0x56, 0xDD, 0x5E, 0xEA, 0x87, 0x44, 0x8F, 0x55,
239 0x0A, 0x8F, 0x55, 0x0A, 0x00, 0x00, 0x18, 0x00,
240 0x11, 0x10, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x00,
241 },
242 },
243 {
244 /* mode#0: 640 x 480 32Bpp 60Hz */
245 640, 480, 32, 60,
246 /* Init_MISC */
247 0xE3,
248 { /* Init_SR0_SR4 */
249 0x03, 0x01, 0x0F, 0x00, 0x0E,
250 },
251 { /* Init_SR10_SR24 */
252 0xFF, 0xBE, 0xEF, 0xFF, 0x00, 0x0E, 0x17, 0x2C,
253 0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
254 0xC4, 0x30, 0x02, 0x01, 0x01,
255 },
256 { /* Init_SR30_SR75 */
257 0x32, 0x03, 0xA0, 0x09, 0xC0, 0x32, 0x32, 0x32,
258 0x32, 0x32, 0x32, 0x32, 0x00, 0x00, 0x03, 0xFF,
259 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
260 0x20, 0x0C, 0x44, 0x20, 0x00, 0x32, 0x32, 0x32,
261 0x04, 0x24, 0x63, 0x4F, 0x52, 0x0B, 0xDF, 0xEA,
262 0x04, 0x50, 0x19, 0x32, 0x32, 0x00, 0x00, 0x32,
263 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
264 0x50, 0x03, 0x74, 0x14, 0x07, 0x82, 0x07, 0x04,
265 0x00, 0x45, 0x30, 0x30, 0x40, 0x30,
266 },
267 { /* Init_SR80_SR93 */
268 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x32,
269 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x32, 0x32,
270 0x00, 0x00, 0x00, 0x00,
271 },
272 { /* Init_SRA0_SRAF */
273 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED,
274 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xFF, 0xDF,
275 },
276 { /* Init_GR00_GR08 */
277 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
278 0xFF,
279 },
280 { /* Init_AR00_AR14 */
281 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
282 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
283 0x41, 0x00, 0x0F, 0x00, 0x00,
284 },
285 { /* Init_CR00_CR18 */
286 0x5F, 0x4F, 0x4F, 0x00, 0x53, 0x1F, 0x0B, 0x3E,
287 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
288 0xEA, 0x0C, 0xDF, 0x50, 0x40, 0xDF, 0x00, 0xE3,
289 0xFF,
290 },
291 { /* Init_CR30_CR4D */
292 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x03, 0x20,
293 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xFF, 0xFD,
294 0x5F, 0x4F, 0x00, 0x54, 0x00, 0x0B, 0xDF, 0x00,
295 0xEA, 0x0C, 0x2E, 0x00, 0x4F, 0xDF,
296 },
297 { /* Init_CR90_CRA7 */
298 0x56, 0xDD, 0x5E, 0xEA, 0x87, 0x44, 0x8F, 0x55,
299 0x0A, 0x8F, 0x55, 0x0A, 0x00, 0x00, 0x18, 0x00,
300 0x11, 0x10, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x00,
301 },
302 },
303
304 { /* mode#2: 800 x 600 16Bpp 60Hz */
305 800, 600, 16, 60,
306 /* Init_MISC */
307 0x2B,
308 { /* Init_SR0_SR4 */
309 0x03, 0x01, 0x0F, 0x03, 0x0E,
310 },
311 { /* Init_SR10_SR24 */
312 0xFF, 0xBE, 0xEE, 0xFF, 0x00, 0x0E, 0x17, 0x2C,
313 0x99, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
314 0xC4, 0x30, 0x02, 0x01, 0x01,
315 },
316 { /* Init_SR30_SR75 */
317 0x34, 0x03, 0x20, 0x09, 0xC0, 0x24, 0x24, 0x24,
318 0x24, 0x24, 0x24, 0x24, 0x00, 0x00, 0x03, 0xFF,
319 0x00, 0xFC, 0x00, 0x00, 0x20, 0x38, 0x00, 0xFC,
320 0x20, 0x0C, 0x44, 0x20, 0x00, 0x24, 0x24, 0x24,
321 0x04, 0x48, 0x83, 0x63, 0x68, 0x72, 0x57, 0x58,
322 0x04, 0x55, 0x59, 0x24, 0x24, 0x00, 0x00, 0x24,
323 0x01, 0x80, 0x7A, 0x1A, 0x1A, 0x00, 0x00, 0x00,
324 0x50, 0x03, 0x74, 0x14, 0x1C, 0x85, 0x35, 0x13,
325 0x02, 0x45, 0x30, 0x35, 0x40, 0x20,
326 },
327 { /* Init_SR80_SR93 */
328 0x00, 0x00, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x24,
329 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x24, 0x24,
330 0x00, 0x00, 0x00, 0x00,
331 },
332 { /* Init_SRA0_SRAF */
333 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED,
334 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF,
335 },
336 { /* Init_GR00_GR08 */
337 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
338 0xFF,
339 },
340 { /* Init_AR00_AR14 */
341 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
342 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
343 0x41, 0x00, 0x0F, 0x00, 0x00,
344 },
345 { /* Init_CR00_CR18 */
346 0x7F, 0x63, 0x63, 0x00, 0x68, 0x18, 0x72, 0xF0,
347 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
348 0x58, 0x0C, 0x57, 0x64, 0x40, 0x57, 0x00, 0xE3,
349 0xFF,
350 },
351 { /* Init_CR30_CR4D */
352 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x20,
353 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xBF, 0xFD,
354 0x7F, 0x63, 0x00, 0x69, 0x18, 0x72, 0x57, 0x00,
355 0x58, 0x0C, 0xE0, 0x20, 0x63, 0x57,
356 },
357 { /* Init_CR90_CRA7 */
358 0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA,
359 0xDB, 0x2A, 0xDF, 0x33, 0x00, 0x00, 0x18, 0x00,
360 0x20, 0x1F, 0x1A, 0x19, 0x0F, 0x0F, 0x0F, 0x00,
361 },
362 },
363 { /* mode#3: 800 x 600 24Bpp 60Hz */
364 800, 600, 24, 60,
365 0x2B,
366 { /* Init_SR0_SR4 */
367 0x03, 0x01, 0x0F, 0x03, 0x0E,
368 },
369 { /* Init_SR10_SR24 */
370 0xFF, 0xBE, 0xEE, 0xFF, 0x00, 0x0E, 0x17, 0x2C,
371 0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
372 0xC4, 0x30, 0x02, 0x01, 0x01,
373 },
374 { /* Init_SR30_SR75 */
375 0x36, 0x03, 0x20, 0x09, 0xC0, 0x36, 0x36, 0x36,
376 0x36, 0x36, 0x36, 0x36, 0x00, 0x00, 0x03, 0xFF,
377 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
378 0x20, 0x0C, 0x44, 0x20, 0x00, 0x36, 0x36, 0x36,
379 0x04, 0x48, 0x83, 0x63, 0x68, 0x72, 0x57, 0x58,
380 0x04, 0x55, 0x59, 0x36, 0x36, 0x00, 0x00, 0x36,
381 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
382 0x50, 0x03, 0x74, 0x14, 0x1C, 0x85, 0x35, 0x13,
383 0x02, 0x45, 0x30, 0x30, 0x40, 0x20,
384 },
385 { /* Init_SR80_SR93 */
386 0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x36,
387 0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x36, 0x36,
388 0x00, 0x00, 0x00, 0x00,
389 },
390 { /* Init_SRA0_SRAF */
391 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED,
392 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF,
393 },
394 { /* Init_GR00_GR08 */
395 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
396 0xFF,
397 },
398 { /* Init_AR00_AR14 */
399 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
400 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
401 0x41, 0x00, 0x0F, 0x00, 0x00,
402 },
403 { /* Init_CR00_CR18 */
404 0x7F, 0x63, 0x63, 0x00, 0x68, 0x18, 0x72, 0xF0,
405 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
406 0x58, 0x0C, 0x57, 0x64, 0x40, 0x57, 0x00, 0xE3,
407 0xFF,
408 },
409 { /* Init_CR30_CR4D */
410 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x20,
411 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xBF, 0xFD,
412 0x7F, 0x63, 0x00, 0x69, 0x18, 0x72, 0x57, 0x00,
413 0x58, 0x0C, 0xE0, 0x20, 0x63, 0x57,
414 },
415 { /* Init_CR90_CRA7 */
416 0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA,
417 0xDB, 0x2A, 0xDF, 0x33, 0x00, 0x00, 0x18, 0x00,
418 0x20, 0x1F, 0x1A, 0x19, 0x0F, 0x0F, 0x0F, 0x00,
419 },
420 },
421 { /* mode#7: 800 x 600 32Bpp 60Hz */
422 800, 600, 32, 60,
423 /* Init_MISC */
424 0x2B,
425 { /* Init_SR0_SR4 */
426 0x03, 0x01, 0x0F, 0x03, 0x0E,
427 },
428 { /* Init_SR10_SR24 */
429 0xFF, 0xBE, 0xEE, 0xFF, 0x00, 0x0E, 0x17, 0x2C,
430 0x99, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
431 0xC4, 0x30, 0x02, 0x01, 0x01,
432 },
433 { /* Init_SR30_SR75 */
434 0x34, 0x03, 0x20, 0x09, 0xC0, 0x24, 0x24, 0x24,
435 0x24, 0x24, 0x24, 0x24, 0x00, 0x00, 0x03, 0xFF,
436 0x00, 0xFC, 0x00, 0x00, 0x20, 0x38, 0x00, 0xFC,
437 0x20, 0x0C, 0x44, 0x20, 0x00, 0x24, 0x24, 0x24,
438 0x04, 0x48, 0x83, 0x63, 0x68, 0x72, 0x57, 0x58,
439 0x04, 0x55, 0x59, 0x24, 0x24, 0x00, 0x00, 0x24,
440 0x01, 0x80, 0x7A, 0x1A, 0x1A, 0x00, 0x00, 0x00,
441 0x50, 0x03, 0x74, 0x14, 0x1C, 0x85, 0x35, 0x13,
442 0x02, 0x45, 0x30, 0x35, 0x40, 0x20,
443 },
444 { /* Init_SR80_SR93 */
445 0x00, 0x00, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x24,
446 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x24, 0x24,
447 0x00, 0x00, 0x00, 0x00,
448 },
449 { /* Init_SRA0_SRAF */
450 0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED,
451 0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF,
452 },
453 { /* Init_GR00_GR08 */
454 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
455 0xFF,
456 },
457 { /* Init_AR00_AR14 */
458 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
459 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
460 0x41, 0x00, 0x0F, 0x00, 0x00,
461 },
462 { /* Init_CR00_CR18 */
463 0x7F, 0x63, 0x63, 0x00, 0x68, 0x18, 0x72, 0xF0,
464 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
465 0x58, 0x0C, 0x57, 0x64, 0x40, 0x57, 0x00, 0xE3,
466 0xFF,
467 },
468 { /* Init_CR30_CR4D */
469 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x20,
470 0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xBF, 0xFD,
471 0x7F, 0x63, 0x00, 0x69, 0x18, 0x72, 0x57, 0x00,
472 0x58, 0x0C, 0xE0, 0x20, 0x63, 0x57,
473 },
474 { /* Init_CR90_CRA7 */
475 0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA,
476 0xDB, 0x2A, 0xDF, 0x33, 0x00, 0x00, 0x18, 0x00,
477 0x20, 0x1F, 0x1A, 0x19, 0x0F, 0x0F, 0x0F, 0x00,
478 },
479 },
480 /* We use 1024x768 table to light 1024x600 panel for lemote */
481 { /* mode#4: 1024 x 600 16Bpp 60Hz */
482 1024, 600, 16, 60,
483 /* Init_MISC */
484 0xEB,
485 { /* Init_SR0_SR4 */
486 0x03, 0x01, 0x0F, 0x00, 0x0E,
487 },
488 { /* Init_SR10_SR24 */
489 0xC8, 0x40, 0x14, 0x60, 0x00, 0x0A, 0x17, 0x20,
490 0x51, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
491 0xC4, 0x30, 0x02, 0x00, 0x01,
492 },
493 { /* Init_SR30_SR75 */
494 0x22, 0x03, 0x24, 0x09, 0xC0, 0x22, 0x22, 0x22,
495 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x03, 0xFF,
496 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
497 0x20, 0x0C, 0x44, 0x20, 0x00, 0x22, 0x22, 0x22,
498 0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03,
499 0x00, 0x60, 0x59, 0x22, 0x22, 0x00, 0x00, 0x22,
500 0x01, 0x80, 0x7A, 0x1A, 0x1A, 0x00, 0x00, 0x00,
501 0x50, 0x03, 0x16, 0x02, 0x0D, 0x82, 0x09, 0x02,
502 0x04, 0x45, 0x3F, 0x30, 0x40, 0x20,
503 },
504 { /* Init_SR80_SR93 */
505 0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A,
506 0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A,
507 0x00, 0x00, 0x00, 0x00,
508 },
509 { /* Init_SRA0_SRAF */
510 0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED,
511 0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF,
512 },
513 { /* Init_GR00_GR08 */
514 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
515 0xFF,
516 },
517 { /* Init_AR00_AR14 */
518 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
519 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
520 0x41, 0x00, 0x0F, 0x00, 0x00,
521 },
522 { /* Init_CR00_CR18 */
523 0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5,
524 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
525 0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3,
526 0xFF,
527 },
528 { /* Init_CR30_CR4D */
529 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20,
530 0x00, 0x00, 0x00, 0x40, 0x00, 0xFF, 0xBF, 0xFF,
531 0xA3, 0x7F, 0x00, 0x82, 0x0b, 0x6f, 0x57, 0x00,
532 0x5c, 0x0f, 0xE0, 0xe0, 0x7F, 0x57,
533 },
534 { /* Init_CR90_CRA7 */
535 0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26,
536 0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00,
537 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03,
538 },
539 },
540 { /* mode#5: 1024 x 768 24Bpp 60Hz */
541 1024, 768, 24, 60,
542 /* Init_MISC */
543 0xEB,
544 { /* Init_SR0_SR4 */
545 0x03, 0x01, 0x0F, 0x03, 0x0E,
546 },
547 { /* Init_SR10_SR24 */
548 0xF3, 0xB6, 0xC0, 0xDD, 0x00, 0x0E, 0x17, 0x2C,
549 0x99, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
550 0xC4, 0x30, 0x02, 0x01, 0x01,
551 },
552 { /* Init_SR30_SR75 */
553 0x38, 0x03, 0x20, 0x09, 0xC0, 0x3A, 0x3A, 0x3A,
554 0x3A, 0x3A, 0x3A, 0x3A, 0x00, 0x00, 0x03, 0xFF,
555 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
556 0x20, 0x0C, 0x44, 0x20, 0x00, 0x00, 0x00, 0x3A,
557 0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03,
558 0x00, 0x60, 0x59, 0x3A, 0x3A, 0x00, 0x00, 0x3A,
559 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
560 0x50, 0x03, 0x74, 0x14, 0x3B, 0x0D, 0x09, 0x02,
561 0x04, 0x45, 0x30, 0x30, 0x40, 0x20,
562 },
563 { /* Init_SR80_SR93 */
564 0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A,
565 0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A,
566 0x00, 0x00, 0x00, 0x00,
567 },
568 { /* Init_SRA0_SRAF */
569 0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED,
570 0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF,
571 },
572 { /* Init_GR00_GR08 */
573 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
574 0xFF,
575 },
576 { /* Init_AR00_AR14 */
577 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
578 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
579 0x41, 0x00, 0x0F, 0x00, 0x00,
580 },
581 { /* Init_CR00_CR18 */
582 0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5,
583 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
584 0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3,
585 0xFF,
586 },
587 { /* Init_CR30_CR4D */
588 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20,
589 0x00, 0x00, 0x00, 0x40, 0x00, 0xFF, 0xBF, 0xFF,
590 0xA3, 0x7F, 0x00, 0x86, 0x15, 0x24, 0xFF, 0x00,
591 0x01, 0x07, 0xE5, 0x20, 0x7F, 0xFF,
592 },
593 { /* Init_CR90_CRA7 */
594 0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26,
595 0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00,
596 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03,
597 },
598 },
599 { /* mode#4: 1024 x 768 32Bpp 60Hz */
600 1024, 768, 32, 60,
601 /* Init_MISC */
602 0xEB,
603 { /* Init_SR0_SR4 */
604 0x03, 0x01, 0x0F, 0x03, 0x0E,
605 },
606 { /* Init_SR10_SR24 */
607 0xF3, 0xB6, 0xC0, 0xDD, 0x00, 0x0E, 0x17, 0x2C,
608 0x99, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
609 0xC4, 0x32, 0x02, 0x01, 0x01,
610 },
611 { /* Init_SR30_SR75 */
612 0x38, 0x03, 0x20, 0x09, 0xC0, 0x3A, 0x3A, 0x3A,
613 0x3A, 0x3A, 0x3A, 0x3A, 0x00, 0x00, 0x03, 0xFF,
614 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
615 0x20, 0x0C, 0x44, 0x20, 0x00, 0x00, 0x00, 0x3A,
616 0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03,
617 0x00, 0x60, 0x59, 0x3A, 0x3A, 0x00, 0x00, 0x3A,
618 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
619 0x50, 0x03, 0x74, 0x14, 0x3B, 0x0D, 0x09, 0x02,
620 0x04, 0x45, 0x30, 0x30, 0x40, 0x20,
621 },
622 { /* Init_SR80_SR93 */
623 0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A,
624 0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A,
625 0x00, 0x00, 0x00, 0x00,
626 },
627 { /* Init_SRA0_SRAF */
628 0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED,
629 0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF,
630 },
631 { /* Init_GR00_GR08 */
632 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
633 0xFF,
634 },
635 { /* Init_AR00_AR14 */
636 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
637 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
638 0x41, 0x00, 0x0F, 0x00, 0x00,
639 },
640 { /* Init_CR00_CR18 */
641 0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5,
642 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
643 0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3,
644 0xFF,
645 },
646 { /* Init_CR30_CR4D */
647 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20,
648 0x00, 0x00, 0x00, 0x40, 0x00, 0xFF, 0xBF, 0xFF,
649 0xA3, 0x7F, 0x00, 0x86, 0x15, 0x24, 0xFF, 0x00,
650 0x01, 0x07, 0xE5, 0x20, 0x7F, 0xFF,
651 },
652 { /* Init_CR90_CRA7 */
653 0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26,
654 0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00,
655 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03,
656 },
657 },
658 { /* mode#6: 320 x 240 16Bpp 60Hz */
659 320, 240, 16, 60,
660 /* Init_MISC */
661 0xEB,
662 { /* Init_SR0_SR4 */
663 0x03, 0x01, 0x0F, 0x03, 0x0E,
664 },
665 { /* Init_SR10_SR24 */
666 0xF3, 0xB6, 0xC0, 0xDD, 0x00, 0x0E, 0x17, 0x2C,
667 0x99, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
668 0xC4, 0x32, 0x02, 0x01, 0x01,
669 },
670 { /* Init_SR30_SR75 */
671 0x38, 0x03, 0x20, 0x09, 0xC0, 0x3A, 0x3A, 0x3A,
672 0x3A, 0x3A, 0x3A, 0x3A, 0x00, 0x00, 0x03, 0xFF,
673 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
674 0x20, 0x0C, 0x44, 0x20, 0x00, 0x00, 0x00, 0x3A,
675 0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03,
676 0x00, 0x60, 0x59, 0x3A, 0x3A, 0x00, 0x00, 0x3A,
677 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
678 0x50, 0x03, 0x74, 0x14, 0x08, 0x43, 0x08, 0x43,
679 0x04, 0x45, 0x30, 0x30, 0x40, 0x20,
680 },
681 { /* Init_SR80_SR93 */
682 0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A,
683 0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A,
684 0x00, 0x00, 0x00, 0x00,
685 },
686 { /* Init_SRA0_SRAF */
687 0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED,
688 0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF,
689 },
690 { /* Init_GR00_GR08 */
691 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
692 0xFF,
693 },
694 { /* Init_AR00_AR14 */
695 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
696 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
697 0x41, 0x00, 0x0F, 0x00, 0x00,
698 },
699 { /* Init_CR00_CR18 */
700 0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5,
701 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
702 0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3,
703 0xFF,
704 },
705 { /* Init_CR30_CR4D */
706 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20,
707 0x00, 0x00, 0x30, 0x40, 0x00, 0xFF, 0xBF, 0xFF,
708 0x2E, 0x27, 0x00, 0x2b, 0x0c, 0x0F, 0xEF, 0x00,
709 0xFe, 0x0f, 0x01, 0xC0, 0x27, 0xEF,
710 },
711 { /* Init_CR90_CRA7 */
712 0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26,
713 0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00,
714 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03,
715 },
716 },
717
718 { /* mode#8: 320 x 240 32Bpp 60Hz */
719 320, 240, 32, 60,
720 /* Init_MISC */
721 0xEB,
722 { /* Init_SR0_SR4 */
723 0x03, 0x01, 0x0F, 0x03, 0x0E,
724 },
725 { /* Init_SR10_SR24 */
726 0xF3, 0xB6, 0xC0, 0xDD, 0x00, 0x0E, 0x17, 0x2C,
727 0x99, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
728 0xC4, 0x32, 0x02, 0x01, 0x01,
729 },
730 { /* Init_SR30_SR75 */
731 0x38, 0x03, 0x20, 0x09, 0xC0, 0x3A, 0x3A, 0x3A,
732 0x3A, 0x3A, 0x3A, 0x3A, 0x00, 0x00, 0x03, 0xFF,
733 0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
734 0x20, 0x0C, 0x44, 0x20, 0x00, 0x00, 0x00, 0x3A,
735 0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03,
736 0x00, 0x60, 0x59, 0x3A, 0x3A, 0x00, 0x00, 0x3A,
737 0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
738 0x50, 0x03, 0x74, 0x14, 0x08, 0x43, 0x08, 0x43,
739 0x04, 0x45, 0x30, 0x30, 0x40, 0x20,
740 },
741 { /* Init_SR80_SR93 */
742 0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A,
743 0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A,
744 0x00, 0x00, 0x00, 0x00,
745 },
746 { /* Init_SRA0_SRAF */
747 0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED,
748 0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF,
749 },
750 { /* Init_GR00_GR08 */
751 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
752 0xFF,
753 },
754 { /* Init_AR00_AR14 */
755 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
756 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
757 0x41, 0x00, 0x0F, 0x00, 0x00,
758 },
759 { /* Init_CR00_CR18 */
760 0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5,
761 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
762 0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3,
763 0xFF,
764 },
765 { /* Init_CR30_CR4D */
766 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20,
767 0x00, 0x00, 0x30, 0x40, 0x00, 0xFF, 0xBF, 0xFF,
768 0x2E, 0x27, 0x00, 0x2b, 0x0c, 0x0F, 0xEF, 0x00,
769 0xFe, 0x0f, 0x01, 0xC0, 0x27, 0xEF,
770 },
771 { /* Init_CR90_CRA7 */
772 0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26,
773 0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00,
774 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03,
775 },
776 },
777};
778
779#define numVGAModes ARRAY_SIZE(VGAMode)
diff --git a/drivers/staging/sm7xxfb/sm7xxfb.c b/drivers/staging/sm7xxfb/sm7xxfb.c
deleted file mode 100644
index c550b719978e..000000000000
--- a/drivers/staging/sm7xxfb/sm7xxfb.c
+++ /dev/null
@@ -1,1026 +0,0 @@
1/*
2 * Silicon Motion SM7XX frame buffer device
3 *
4 * Copyright (C) 2006 Silicon Motion Technology Corp.
5 * Authors: Ge Wang, gewang@siliconmotion.com
6 * Boyod boyod.yang@siliconmotion.com.cn
7 *
8 * Copyright (C) 2009 Lemote, Inc.
9 * Author: Wu Zhangjin, wuzhangjin@gmail.com
10 *
11 * Copyright (C) 2011 Igalia, S.L.
12 * Author: Javier M. Mellid <jmunhoz@igalia.com>
13 *
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file COPYING in the main directory of this archive for
16 * more details.
17 *
18 * Framebuffer driver for Silicon Motion SM710, SM712, SM721 and SM722 chips
19 */
20
21#include <linux/io.h>
22#include <linux/fb.h>
23#include <linux/pci.h>
24#include <linux/init.h>
25#include <linux/slab.h>
26#include <linux/uaccess.h>
27#include <linux/module.h>
28#include <linux/console.h>
29#include <linux/screen_info.h>
30
31#ifdef CONFIG_PM
32#include <linux/pm.h>
33#endif
34
35#include "sm7xx.h"
36
37/*
38* Private structure
39*/
40struct smtcfb_info {
41 struct pci_dev *pdev;
42 struct fb_info fb;
43 u16 chip_id;
44 u8 chip_rev_id;
45
46 void __iomem *lfb; /* linear frame buffer */
47 void __iomem *dp_regs; /* drawing processor control regs */
48 void __iomem *vp_regs; /* video processor control regs */
49 void __iomem *cp_regs; /* capture processor control regs */
50 void __iomem *mmio; /* memory map IO port */
51
52 u_int width;
53 u_int height;
54 u_int hz;
55
56 u32 colreg[17];
57};
58
59void __iomem *smtc_RegBaseAddress; /* Memory Map IO starting address */
60
61static struct fb_var_screeninfo smtcfb_var = {
62 .xres = 1024,
63 .yres = 600,
64 .xres_virtual = 1024,
65 .yres_virtual = 600,
66 .bits_per_pixel = 16,
67 .red = {16, 8, 0},
68 .green = {8, 8, 0},
69 .blue = {0, 8, 0},
70 .activate = FB_ACTIVATE_NOW,
71 .height = -1,
72 .width = -1,
73 .vmode = FB_VMODE_NONINTERLACED,
74 .nonstd = 0,
75 .accel_flags = FB_ACCELF_TEXT,
76};
77
78static struct fb_fix_screeninfo smtcfb_fix = {
79 .id = "smXXXfb",
80 .type = FB_TYPE_PACKED_PIXELS,
81 .visual = FB_VISUAL_TRUECOLOR,
82 .line_length = 800 * 3,
83 .accel = FB_ACCEL_SMI_LYNX,
84 .type_aux = 0,
85 .xpanstep = 0,
86 .ypanstep = 0,
87 .ywrapstep = 0,
88};
89
90struct vesa_mode {
91 char index[6];
92 u16 lfb_width;
93 u16 lfb_height;
94 u16 lfb_depth;
95};
96
97static struct vesa_mode vesa_mode_table[] = {
98 {"0x301", 640, 480, 8},
99 {"0x303", 800, 600, 8},
100 {"0x305", 1024, 768, 8},
101 {"0x307", 1280, 1024, 8},
102
103 {"0x311", 640, 480, 16},
104 {"0x314", 800, 600, 16},
105 {"0x317", 1024, 768, 16},
106 {"0x31A", 1280, 1024, 16},
107
108 {"0x312", 640, 480, 24},
109 {"0x315", 800, 600, 24},
110 {"0x318", 1024, 768, 24},
111 {"0x31B", 1280, 1024, 24},
112};
113
114struct screen_info smtc_scr_info;
115
116/* process command line options, get vga parameter */
117static int __init sm7xx_vga_setup(char *options)
118{
119 int i;
120
121 if (!options || !*options)
122 return -EINVAL;
123
124 smtc_scr_info.lfb_width = 0;
125 smtc_scr_info.lfb_height = 0;
126 smtc_scr_info.lfb_depth = 0;
127
128 pr_debug("sm7xx_vga_setup = %s\n", options);
129
130 for (i = 0; i < ARRAY_SIZE(vesa_mode_table); i++) {
131 if (strstr(options, vesa_mode_table[i].index)) {
132 smtc_scr_info.lfb_width = vesa_mode_table[i].lfb_width;
133 smtc_scr_info.lfb_height =
134 vesa_mode_table[i].lfb_height;
135 smtc_scr_info.lfb_depth = vesa_mode_table[i].lfb_depth;
136 return 0;
137 }
138 }
139
140 return -1;
141}
142__setup("vga=", sm7xx_vga_setup);
143
144static void sm712_setpalette(int regno, unsigned red, unsigned green,
145 unsigned blue, struct fb_info *info)
146{
147 /* set bit 5:4 = 01 (write LCD RAM only) */
148 smtc_seqw(0x66, (smtc_seqr(0x66) & 0xC3) | 0x10);
149
150 smtc_mmiowb(regno, dac_reg);
151 smtc_mmiowb(red >> 10, dac_val);
152 smtc_mmiowb(green >> 10, dac_val);
153 smtc_mmiowb(blue >> 10, dac_val);
154}
155
156/* chan_to_field
157 *
158 * convert a colour value into a field position
159 *
160 * from pxafb.c
161 */
162
163static inline unsigned int chan_to_field(unsigned int chan,
164 struct fb_bitfield *bf)
165{
166 chan &= 0xffff;
167 chan >>= 16 - bf->length;
168 return chan << bf->offset;
169}
170
171static int smtc_blank(int blank_mode, struct fb_info *info)
172{
173 /* clear DPMS setting */
174 switch (blank_mode) {
175 case FB_BLANK_UNBLANK:
176 /* Screen On: HSync: On, VSync : On */
177 smtc_seqw(0x01, (smtc_seqr(0x01) & (~0x20)));
178 smtc_seqw(0x6a, 0x16);
179 smtc_seqw(0x6b, 0x02);
180 smtc_seqw(0x21, (smtc_seqr(0x21) & 0x77));
181 smtc_seqw(0x22, (smtc_seqr(0x22) & (~0x30)));
182 smtc_seqw(0x23, (smtc_seqr(0x23) & (~0xc0)));
183 smtc_seqw(0x24, (smtc_seqr(0x24) | 0x01));
184 smtc_seqw(0x31, (smtc_seqr(0x31) | 0x03));
185 break;
186 case FB_BLANK_NORMAL:
187 /* Screen Off: HSync: On, VSync : On Soft blank */
188 smtc_seqw(0x01, (smtc_seqr(0x01) & (~0x20)));
189 smtc_seqw(0x6a, 0x16);
190 smtc_seqw(0x6b, 0x02);
191 smtc_seqw(0x22, (smtc_seqr(0x22) & (~0x30)));
192 smtc_seqw(0x23, (smtc_seqr(0x23) & (~0xc0)));
193 smtc_seqw(0x24, (smtc_seqr(0x24) | 0x01));
194 smtc_seqw(0x31, ((smtc_seqr(0x31) & (~0x07)) | 0x00));
195 break;
196 case FB_BLANK_VSYNC_SUSPEND:
197 /* Screen On: HSync: On, VSync : Off */
198 smtc_seqw(0x01, (smtc_seqr(0x01) | 0x20));
199 smtc_seqw(0x20, (smtc_seqr(0x20) & (~0xB0)));
200 smtc_seqw(0x6a, 0x0c);
201 smtc_seqw(0x6b, 0x02);
202 smtc_seqw(0x21, (smtc_seqr(0x21) | 0x88));
203 smtc_seqw(0x22, ((smtc_seqr(0x22) & (~0x30)) | 0x20));
204 smtc_seqw(0x23, ((smtc_seqr(0x23) & (~0xc0)) | 0x20));
205 smtc_seqw(0x24, (smtc_seqr(0x24) & (~0x01)));
206 smtc_seqw(0x31, ((smtc_seqr(0x31) & (~0x07)) | 0x00));
207 smtc_seqw(0x34, (smtc_seqr(0x34) | 0x80));
208 break;
209 case FB_BLANK_HSYNC_SUSPEND:
210 /* Screen On: HSync: Off, VSync : On */
211 smtc_seqw(0x01, (smtc_seqr(0x01) | 0x20));
212 smtc_seqw(0x20, (smtc_seqr(0x20) & (~0xB0)));
213 smtc_seqw(0x6a, 0x0c);
214 smtc_seqw(0x6b, 0x02);
215 smtc_seqw(0x21, (smtc_seqr(0x21) | 0x88));
216 smtc_seqw(0x22, ((smtc_seqr(0x22) & (~0x30)) | 0x10));
217 smtc_seqw(0x23, ((smtc_seqr(0x23) & (~0xc0)) | 0xD8));
218 smtc_seqw(0x24, (smtc_seqr(0x24) & (~0x01)));
219 smtc_seqw(0x31, ((smtc_seqr(0x31) & (~0x07)) | 0x00));
220 smtc_seqw(0x34, (smtc_seqr(0x34) | 0x80));
221 break;
222 case FB_BLANK_POWERDOWN:
223 /* Screen On: HSync: Off, VSync : Off */
224 smtc_seqw(0x01, (smtc_seqr(0x01) | 0x20));
225 smtc_seqw(0x20, (smtc_seqr(0x20) & (~0xB0)));
226 smtc_seqw(0x6a, 0x0c);
227 smtc_seqw(0x6b, 0x02);
228 smtc_seqw(0x21, (smtc_seqr(0x21) | 0x88));
229 smtc_seqw(0x22, ((smtc_seqr(0x22) & (~0x30)) | 0x30));
230 smtc_seqw(0x23, ((smtc_seqr(0x23) & (~0xc0)) | 0xD8));
231 smtc_seqw(0x24, (smtc_seqr(0x24) & (~0x01)));
232 smtc_seqw(0x31, ((smtc_seqr(0x31) & (~0x07)) | 0x00));
233 smtc_seqw(0x34, (smtc_seqr(0x34) | 0x80));
234 break;
235 default:
236 return -EINVAL;
237 }
238
239 return 0;
240}
241
242static int smtc_setcolreg(unsigned regno, unsigned red, unsigned green,
243 unsigned blue, unsigned trans, struct fb_info *info)
244{
245 struct smtcfb_info *sfb;
246 u32 val;
247
248 sfb = info->par;
249
250 if (regno > 255)
251 return 1;
252
253 switch (sfb->fb.fix.visual) {
254 case FB_VISUAL_DIRECTCOLOR:
255 case FB_VISUAL_TRUECOLOR:
256 /*
257 * 16/32 bit true-colour, use pseudo-palette for 16 base color
258 */
259 if (regno < 16) {
260 if (sfb->fb.var.bits_per_pixel == 16) {
261 u32 *pal = sfb->fb.pseudo_palette;
262 val = chan_to_field(red, &sfb->fb.var.red);
263 val |= chan_to_field(green, &sfb->fb.var.green);
264 val |= chan_to_field(blue, &sfb->fb.var.blue);
265#ifdef __BIG_ENDIAN
266 pal[regno] =
267 ((red & 0xf800) >> 8) |
268 ((green & 0xe000) >> 13) |
269 ((green & 0x1c00) << 3) |
270 ((blue & 0xf800) >> 3);
271#else
272 pal[regno] = val;
273#endif
274 } else {
275 u32 *pal = sfb->fb.pseudo_palette;
276 val = chan_to_field(red, &sfb->fb.var.red);
277 val |= chan_to_field(green, &sfb->fb.var.green);
278 val |= chan_to_field(blue, &sfb->fb.var.blue);
279#ifdef __BIG_ENDIAN
280 val =
281 (val & 0xff00ff00 >> 8) |
282 (val & 0x00ff00ff << 8);
283#endif
284 pal[regno] = val;
285 }
286 }
287 break;
288
289 case FB_VISUAL_PSEUDOCOLOR:
290 /* color depth 8 bit */
291 sm712_setpalette(regno, red, green, blue, info);
292 break;
293
294 default:
295 return 1; /* unknown type */
296 }
297
298 return 0;
299
300}
301
302#ifdef __BIG_ENDIAN
303static ssize_t smtcfb_read(struct fb_info *info, char __user *buf, size_t
304 count, loff_t *ppos)
305{
306 unsigned long p = *ppos;
307
308 u32 *buffer, *dst;
309 u32 __iomem *src;
310 int c, i, cnt = 0, err = 0;
311 unsigned long total_size;
312
313 if (!info || !info->screen_base)
314 return -ENODEV;
315
316 if (info->state != FBINFO_STATE_RUNNING)
317 return -EPERM;
318
319 total_size = info->screen_size;
320
321 if (total_size == 0)
322 total_size = info->fix.smem_len;
323
324 if (p >= total_size)
325 return 0;
326
327 if (count >= total_size)
328 count = total_size;
329
330 if (count + p > total_size)
331 count = total_size - p;
332
333 buffer = kmalloc((count > PAGE_SIZE) ? PAGE_SIZE : count, GFP_KERNEL);
334 if (!buffer)
335 return -ENOMEM;
336
337 src = (u32 __iomem *) (info->screen_base + p);
338
339 if (info->fbops->fb_sync)
340 info->fbops->fb_sync(info);
341
342 while (count) {
343 c = (count > PAGE_SIZE) ? PAGE_SIZE : count;
344 dst = buffer;
345 for (i = c >> 2; i--;) {
346 *dst = fb_readl(src++);
347 *dst =
348 (*dst & 0xff00ff00 >> 8) |
349 (*dst & 0x00ff00ff << 8);
350 dst++;
351 }
352 if (c & 3) {
353 u8 *dst8 = (u8 *) dst;
354 u8 __iomem *src8 = (u8 __iomem *) src;
355
356 for (i = c & 3; i--;) {
357 if (i & 1) {
358 *dst8++ = fb_readb(++src8);
359 } else {
360 *dst8++ = fb_readb(--src8);
361 src8 += 2;
362 }
363 }
364 src = (u32 __iomem *) src8;
365 }
366
367 if (copy_to_user(buf, buffer, c)) {
368 err = -EFAULT;
369 break;
370 }
371 *ppos += c;
372 buf += c;
373 cnt += c;
374 count -= c;
375 }
376
377 kfree(buffer);
378
379 return (err) ? err : cnt;
380}
381
382static ssize_t
383smtcfb_write(struct fb_info *info, const char __user *buf, size_t count,
384 loff_t *ppos)
385{
386 unsigned long p = *ppos;
387
388 u32 *buffer, *src;
389 u32 __iomem *dst;
390 int c, i, cnt = 0, err = 0;
391 unsigned long total_size;
392
393 if (!info || !info->screen_base)
394 return -ENODEV;
395
396 if (info->state != FBINFO_STATE_RUNNING)
397 return -EPERM;
398
399 total_size = info->screen_size;
400
401 if (total_size == 0)
402 total_size = info->fix.smem_len;
403
404 if (p > total_size)
405 return -EFBIG;
406
407 if (count > total_size) {
408 err = -EFBIG;
409 count = total_size;
410 }
411
412 if (count + p > total_size) {
413 if (!err)
414 err = -ENOSPC;
415
416 count = total_size - p;
417 }
418
419 buffer = kmalloc((count > PAGE_SIZE) ? PAGE_SIZE : count, GFP_KERNEL);
420 if (!buffer)
421 return -ENOMEM;
422
423 dst = (u32 __iomem *) (info->screen_base + p);
424
425 if (info->fbops->fb_sync)
426 info->fbops->fb_sync(info);
427
428 while (count) {
429 c = (count > PAGE_SIZE) ? PAGE_SIZE : count;
430 src = buffer;
431
432 if (copy_from_user(src, buf, c)) {
433 err = -EFAULT;
434 break;
435 }
436
437 for (i = c >> 2; i--;) {
438 fb_writel((*src & 0xff00ff00 >> 8) |
439 (*src & 0x00ff00ff << 8), dst++);
440 src++;
441 }
442 if (c & 3) {
443 u8 *src8 = (u8 *) src;
444 u8 __iomem *dst8 = (u8 __iomem *) dst;
445
446 for (i = c & 3; i--;) {
447 if (i & 1) {
448 fb_writeb(*src8++, ++dst8);
449 } else {
450 fb_writeb(*src8++, --dst8);
451 dst8 += 2;
452 }
453 }
454 dst = (u32 __iomem *) dst8;
455 }
456
457 *ppos += c;
458 buf += c;
459 cnt += c;
460 count -= c;
461 }
462
463 kfree(buffer);
464
465 return (cnt) ? cnt : err;
466}
467#endif /* ! __BIG_ENDIAN */
468
469static void sm7xx_set_timing(struct smtcfb_info *sfb)
470{
471 int i = 0, j = 0;
472 u32 m_nScreenStride;
473
474 dev_dbg(&sfb->pdev->dev,
475 "sfb->width=%d sfb->height=%d sfb->fb.var.bits_per_pixel=%d sfb->hz=%d\n",
476 sfb->width, sfb->height, sfb->fb.var.bits_per_pixel, sfb->hz);
477
478 for (j = 0; j < numVGAModes; j++) {
479 if (VGAMode[j].mmSizeX == sfb->width &&
480 VGAMode[j].mmSizeY == sfb->height &&
481 VGAMode[j].bpp == sfb->fb.var.bits_per_pixel &&
482 VGAMode[j].hz == sfb->hz) {
483
484 dev_dbg(&sfb->pdev->dev,
485 "VGAMode[j].mmSizeX=%d VGAMode[j].mmSizeY=%d VGAMode[j].bpp=%d VGAMode[j].hz=%d\n",
486 VGAMode[j].mmSizeX, VGAMode[j].mmSizeY,
487 VGAMode[j].bpp, VGAMode[j].hz);
488
489 dev_dbg(&sfb->pdev->dev, "VGAMode index=%d\n", j);
490
491 smtc_mmiowb(0x0, 0x3c6);
492
493 smtc_seqw(0, 0x1);
494
495 smtc_mmiowb(VGAMode[j].Init_MISC, 0x3c2);
496
497 /* init SEQ register SR00 - SR04 */
498 for (i = 0; i < SIZE_SR00_SR04; i++)
499 smtc_seqw(i, VGAMode[j].Init_SR00_SR04[i]);
500
501 /* init SEQ register SR10 - SR24 */
502 for (i = 0; i < SIZE_SR10_SR24; i++)
503 smtc_seqw(i + 0x10,
504 VGAMode[j].Init_SR10_SR24[i]);
505
506 /* init SEQ register SR30 - SR75 */
507 for (i = 0; i < SIZE_SR30_SR75; i++)
508 if ((i + 0x30) != 0x62 &&
509 (i + 0x30) != 0x6a &&
510 (i + 0x30) != 0x6b)
511 smtc_seqw(i + 0x30,
512 VGAMode[j].Init_SR30_SR75[i]);
513
514 /* init SEQ register SR80 - SR93 */
515 for (i = 0; i < SIZE_SR80_SR93; i++)
516 smtc_seqw(i + 0x80,
517 VGAMode[j].Init_SR80_SR93[i]);
518
519 /* init SEQ register SRA0 - SRAF */
520 for (i = 0; i < SIZE_SRA0_SRAF; i++)
521 smtc_seqw(i + 0xa0,
522 VGAMode[j].Init_SRA0_SRAF[i]);
523
524 /* init Graphic register GR00 - GR08 */
525 for (i = 0; i < SIZE_GR00_GR08; i++)
526 smtc_grphw(i, VGAMode[j].Init_GR00_GR08[i]);
527
528 /* init Attribute register AR00 - AR14 */
529 for (i = 0; i < SIZE_AR00_AR14; i++)
530 smtc_attrw(i, VGAMode[j].Init_AR00_AR14[i]);
531
532 /* init CRTC register CR00 - CR18 */
533 for (i = 0; i < SIZE_CR00_CR18; i++)
534 smtc_crtcw(i, VGAMode[j].Init_CR00_CR18[i]);
535
536 /* init CRTC register CR30 - CR4D */
537 for (i = 0; i < SIZE_CR30_CR4D; i++)
538 smtc_crtcw(i + 0x30,
539 VGAMode[j].Init_CR30_CR4D[i]);
540
541 /* init CRTC register CR90 - CRA7 */
542 for (i = 0; i < SIZE_CR90_CRA7; i++)
543 smtc_crtcw(i + 0x90,
544 VGAMode[j].Init_CR90_CRA7[i]);
545 }
546 }
547 smtc_mmiowb(0x67, 0x3c2);
548
549 /* set VPR registers */
550 writel(0x0, sfb->vp_regs + 0x0C);
551 writel(0x0, sfb->vp_regs + 0x40);
552
553 /* set data width */
554 m_nScreenStride =
555 (sfb->width * sfb->fb.var.bits_per_pixel) / 64;
556 switch (sfb->fb.var.bits_per_pixel) {
557 case 8:
558 writel(0x0, sfb->vp_regs + 0x0);
559 break;
560 case 16:
561 writel(0x00020000, sfb->vp_regs + 0x0);
562 break;
563 case 24:
564 writel(0x00040000, sfb->vp_regs + 0x0);
565 break;
566 case 32:
567 writel(0x00030000, sfb->vp_regs + 0x0);
568 break;
569 }
570 writel((u32) (((m_nScreenStride + 2) << 16) | m_nScreenStride),
571 sfb->vp_regs + 0x10);
572
573}
574
575static void smtc_set_timing(struct smtcfb_info *sfb)
576{
577 switch (sfb->chip_id) {
578 case 0x710:
579 case 0x712:
580 case 0x720:
581 sm7xx_set_timing(sfb);
582 break;
583 }
584}
585
586static void smtcfb_setmode(struct smtcfb_info *sfb)
587{
588 switch (sfb->fb.var.bits_per_pixel) {
589 case 32:
590 sfb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
591 sfb->fb.fix.line_length = sfb->fb.var.xres * 4;
592 sfb->fb.var.red.length = 8;
593 sfb->fb.var.green.length = 8;
594 sfb->fb.var.blue.length = 8;
595 sfb->fb.var.red.offset = 16;
596 sfb->fb.var.green.offset = 8;
597 sfb->fb.var.blue.offset = 0;
598 break;
599 case 24:
600 sfb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
601 sfb->fb.fix.line_length = sfb->fb.var.xres * 3;
602 sfb->fb.var.red.length = 8;
603 sfb->fb.var.green.length = 8;
604 sfb->fb.var.blue.length = 8;
605 sfb->fb.var.red.offset = 16;
606 sfb->fb.var.green.offset = 8;
607 sfb->fb.var.blue.offset = 0;
608 break;
609 case 8:
610 sfb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
611 sfb->fb.fix.line_length = sfb->fb.var.xres;
612 sfb->fb.var.red.length = 3;
613 sfb->fb.var.green.length = 3;
614 sfb->fb.var.blue.length = 2;
615 sfb->fb.var.red.offset = 5;
616 sfb->fb.var.green.offset = 2;
617 sfb->fb.var.blue.offset = 0;
618 break;
619 case 16:
620 default:
621 sfb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
622 sfb->fb.fix.line_length = sfb->fb.var.xres * 2;
623 sfb->fb.var.red.length = 5;
624 sfb->fb.var.green.length = 6;
625 sfb->fb.var.blue.length = 5;
626 sfb->fb.var.red.offset = 11;
627 sfb->fb.var.green.offset = 5;
628 sfb->fb.var.blue.offset = 0;
629 break;
630 }
631
632 sfb->width = sfb->fb.var.xres;
633 sfb->height = sfb->fb.var.yres;
634 sfb->hz = 60;
635 smtc_set_timing(sfb);
636}
637
638static int smtc_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
639{
640 /* sanity checks */
641 if (var->xres_virtual < var->xres)
642 var->xres_virtual = var->xres;
643
644 if (var->yres_virtual < var->yres)
645 var->yres_virtual = var->yres;
646
647 /* set valid default bpp */
648 if ((var->bits_per_pixel != 8) && (var->bits_per_pixel != 16) &&
649 (var->bits_per_pixel != 24) && (var->bits_per_pixel != 32))
650 var->bits_per_pixel = 16;
651
652 return 0;
653}
654
655static int smtc_set_par(struct fb_info *info)
656{
657 smtcfb_setmode(info->par);
658
659 return 0;
660}
661
662static struct fb_ops smtcfb_ops = {
663 .owner = THIS_MODULE,
664 .fb_check_var = smtc_check_var,
665 .fb_set_par = smtc_set_par,
666 .fb_setcolreg = smtc_setcolreg,
667 .fb_blank = smtc_blank,
668 .fb_fillrect = cfb_fillrect,
669 .fb_imageblit = cfb_imageblit,
670 .fb_copyarea = cfb_copyarea,
671#ifdef __BIG_ENDIAN
672 .fb_read = smtcfb_read,
673 .fb_write = smtcfb_write,
674#endif
675};
676
677/*
678 * alloc struct smtcfb_info and assign default values
679 */
680static struct smtcfb_info *smtc_alloc_fb_info(struct pci_dev *pdev)
681{
682 struct smtcfb_info *sfb;
683
684 sfb = kzalloc(sizeof(*sfb), GFP_KERNEL);
685
686 if (!sfb)
687 return NULL;
688
689 sfb->pdev = pdev;
690
691 sfb->fb.flags = FBINFO_FLAG_DEFAULT;
692 sfb->fb.fbops = &smtcfb_ops;
693 sfb->fb.fix = smtcfb_fix;
694 sfb->fb.var = smtcfb_var;
695 sfb->fb.pseudo_palette = sfb->colreg;
696 sfb->fb.par = sfb;
697
698 return sfb;
699}
700
701/*
702 * free struct smtcfb_info
703 */
704static void smtc_free_fb_info(struct smtcfb_info *sfb)
705{
706 kfree(sfb);
707}
708
709/*
710 * Unmap in the memory mapped IO registers
711 */
712
713static void smtc_unmap_mmio(struct smtcfb_info *sfb)
714{
715 if (sfb && smtc_RegBaseAddress)
716 smtc_RegBaseAddress = NULL;
717}
718
719/*
720 * Map in the screen memory
721 */
722
723static int smtc_map_smem(struct smtcfb_info *sfb,
724 struct pci_dev *pdev, u_long smem_len)
725{
726
727 sfb->fb.fix.smem_start = pci_resource_start(pdev, 0);
728
729#ifdef __BIG_ENDIAN
730 if (sfb->fb.var.bits_per_pixel == 32)
731 sfb->fb.fix.smem_start += 0x800000;
732#endif
733
734 sfb->fb.fix.smem_len = smem_len;
735
736 sfb->fb.screen_base = sfb->lfb;
737
738 if (!sfb->fb.screen_base) {
739 dev_err(&pdev->dev,
740 "%s: unable to map screen memory\n", sfb->fb.fix.id);
741 return -ENOMEM;
742 }
743
744 return 0;
745}
746
747/*
748 * Unmap in the screen memory
749 *
750 */
751static void smtc_unmap_smem(struct smtcfb_info *sfb)
752{
753 if (sfb && sfb->fb.screen_base) {
754 iounmap(sfb->fb.screen_base);
755 sfb->fb.screen_base = NULL;
756 }
757}
758
759/*
760 * We need to wake up the device and make sure its in linear memory mode.
761 */
762static inline void sm7xx_init_hw(void)
763{
764 outb_p(0x18, 0x3c4);
765 outb_p(0x11, 0x3c5);
766}
767
768static int smtcfb_pci_probe(struct pci_dev *pdev,
769 const struct pci_device_id *ent)
770{
771 struct smtcfb_info *sfb;
772 u_long smem_size = 0x00800000; /* default 8MB */
773 int err;
774 unsigned long mmio_base;
775
776 dev_info(&pdev->dev, "Silicon Motion display driver.");
777
778 err = pci_enable_device(pdev); /* enable SMTC chip */
779 if (err)
780 return err;
781
782 sprintf(smtcfb_fix.id, "sm%Xfb", ent->device);
783
784 sfb = smtc_alloc_fb_info(pdev);
785
786 if (!sfb) {
787 err = -ENOMEM;
788 goto failed_free;
789 }
790
791 sfb->chip_id = ent->device;
792
793 pci_set_drvdata(pdev, sfb);
794
795 sm7xx_init_hw();
796
797 /* get mode parameter from smtc_scr_info */
798 if (smtc_scr_info.lfb_width != 0) {
799 sfb->fb.var.xres = smtc_scr_info.lfb_width;
800 sfb->fb.var.yres = smtc_scr_info.lfb_height;
801 sfb->fb.var.bits_per_pixel = smtc_scr_info.lfb_depth;
802 } else {
803 /* default resolution 1024x600 16bit mode */
804 sfb->fb.var.xres = SCREEN_X_RES;
805 sfb->fb.var.yres = SCREEN_Y_RES;
806 sfb->fb.var.bits_per_pixel = SCREEN_BPP;
807 }
808
809#ifdef __BIG_ENDIAN
810 if (sfb->fb.var.bits_per_pixel == 24)
811 sfb->fb.var.bits_per_pixel = (smtc_scr_info.lfb_depth = 32);
812#endif
813 /* Map address and memory detection */
814 mmio_base = pci_resource_start(pdev, 0);
815 pci_read_config_byte(pdev, PCI_REVISION_ID, &sfb->chip_rev_id);
816
817 switch (sfb->chip_id) {
818 case 0x710:
819 case 0x712:
820 sfb->fb.fix.mmio_start = mmio_base + 0x00400000;
821 sfb->fb.fix.mmio_len = 0x00400000;
822 smem_size = SM712_VIDEOMEMORYSIZE;
823#ifdef __BIG_ENDIAN
824 sfb->lfb = ioremap(mmio_base, 0x00c00000);
825#else
826 sfb->lfb = ioremap(mmio_base, 0x00800000);
827#endif
828 sfb->mmio = (smtc_RegBaseAddress =
829 sfb->lfb + 0x00700000);
830 sfb->dp_regs = sfb->lfb + 0x00408000;
831 sfb->vp_regs = sfb->lfb + 0x0040c000;
832#ifdef __BIG_ENDIAN
833 if (sfb->fb.var.bits_per_pixel == 32) {
834 sfb->lfb += 0x800000;
835 dev_info(&pdev->dev, "sfb->lfb=%p", sfb->lfb);
836 }
837#endif
838 if (!smtc_RegBaseAddress) {
839 dev_err(&pdev->dev,
840 "%s: unable to map memory mapped IO!",
841 sfb->fb.fix.id);
842 err = -ENOMEM;
843 goto failed_fb;
844 }
845
846 /* set MCLK = 14.31818 * (0x16 / 0x2) */
847 smtc_seqw(0x6a, 0x16);
848 smtc_seqw(0x6b, 0x02);
849 smtc_seqw(0x62, 0x3e);
850 /* enable PCI burst */
851 smtc_seqw(0x17, 0x20);
852 /* enable word swap */
853#ifdef __BIG_ENDIAN
854 if (sfb->fb.var.bits_per_pixel == 32)
855 smtc_seqw(0x17, 0x30);
856#endif
857 break;
858 case 0x720:
859 sfb->fb.fix.mmio_start = mmio_base;
860 sfb->fb.fix.mmio_len = 0x00200000;
861 smem_size = SM722_VIDEOMEMORYSIZE;
862 sfb->dp_regs = ioremap(mmio_base, 0x00a00000);
863 sfb->lfb = sfb->dp_regs + 0x00200000;
864 sfb->mmio = (smtc_RegBaseAddress =
865 sfb->dp_regs + 0x000c0000);
866 sfb->vp_regs = sfb->dp_regs + 0x800;
867
868 smtc_seqw(0x62, 0xff);
869 smtc_seqw(0x6a, 0x0d);
870 smtc_seqw(0x6b, 0x02);
871 break;
872 default:
873 dev_err(&pdev->dev,
874 "No valid Silicon Motion display chip was detected!");
875
876 goto failed_fb;
877 }
878
879 /* can support 32 bpp */
880 if (15 == sfb->fb.var.bits_per_pixel)
881 sfb->fb.var.bits_per_pixel = 16;
882
883 sfb->fb.var.xres_virtual = sfb->fb.var.xres;
884 sfb->fb.var.yres_virtual = sfb->fb.var.yres;
885 err = smtc_map_smem(sfb, pdev, smem_size);
886 if (err)
887 goto failed;
888
889 smtcfb_setmode(sfb);
890
891 err = register_framebuffer(&sfb->fb);
892 if (err < 0)
893 goto failed;
894
895 dev_info(&pdev->dev,
896 "Silicon Motion SM%X Rev%X primary display mode %dx%d-%d Init Complete.",
897 sfb->chip_id, sfb->chip_rev_id, sfb->fb.var.xres,
898 sfb->fb.var.yres, sfb->fb.var.bits_per_pixel);
899
900 return 0;
901
902failed:
903 dev_err(&pdev->dev, "Silicon Motion, Inc. primary display init fail.");
904
905 smtc_unmap_smem(sfb);
906 smtc_unmap_mmio(sfb);
907failed_fb:
908 smtc_free_fb_info(sfb);
909
910failed_free:
911 pci_disable_device(pdev);
912
913 return err;
914}
915
916/*
917 * 0x710 (LynxEM)
918 * 0x712 (LynxEM+)
919 * 0x720 (Lynx3DM, Lynx3DM+)
920 */
921static const struct pci_device_id smtcfb_pci_table[] = {
922 { PCI_DEVICE(0x126f, 0x710), },
923 { PCI_DEVICE(0x126f, 0x712), },
924 { PCI_DEVICE(0x126f, 0x720), },
925 {0,}
926};
927
928static void smtcfb_pci_remove(struct pci_dev *pdev)
929{
930 struct smtcfb_info *sfb;
931
932 sfb = pci_get_drvdata(pdev);
933 smtc_unmap_smem(sfb);
934 smtc_unmap_mmio(sfb);
935 unregister_framebuffer(&sfb->fb);
936 smtc_free_fb_info(sfb);
937}
938
939#ifdef CONFIG_PM
940static int smtcfb_pci_suspend(struct device *device)
941{
942 struct pci_dev *pdev = to_pci_dev(device);
943 struct smtcfb_info *sfb;
944
945 sfb = pci_get_drvdata(pdev);
946
947 /* set the hw in sleep mode use external clock and self memory refresh
948 * so that we can turn off internal PLLs later on
949 */
950 smtc_seqw(0x20, (smtc_seqr(0x20) | 0xc0));
951 smtc_seqw(0x69, (smtc_seqr(0x69) & 0xf7));
952
953 console_lock();
954 fb_set_suspend(&sfb->fb, 1);
955 console_unlock();
956
957 /* additionally turn off all function blocks including internal PLLs */
958 smtc_seqw(0x21, 0xff);
959
960 return 0;
961}
962
963static int smtcfb_pci_resume(struct device *device)
964{
965 struct pci_dev *pdev = to_pci_dev(device);
966 struct smtcfb_info *sfb;
967
968 sfb = pci_get_drvdata(pdev);
969
970 /* reinit hardware */
971 sm7xx_init_hw();
972 switch (sfb->chip_id) {
973 case 0x710:
974 case 0x712:
975 /* set MCLK = 14.31818 * (0x16 / 0x2) */
976 smtc_seqw(0x6a, 0x16);
977 smtc_seqw(0x6b, 0x02);
978 smtc_seqw(0x62, 0x3e);
979 /* enable PCI burst */
980 smtc_seqw(0x17, 0x20);
981#ifdef __BIG_ENDIAN
982 if (sfb->fb.var.bits_per_pixel == 32)
983 smtc_seqw(0x17, 0x30);
984#endif
985 break;
986 case 0x720:
987 smtc_seqw(0x62, 0xff);
988 smtc_seqw(0x6a, 0x0d);
989 smtc_seqw(0x6b, 0x02);
990 break;
991 }
992
993 smtc_seqw(0x34, (smtc_seqr(0x34) | 0xc0));
994 smtc_seqw(0x33, ((smtc_seqr(0x33) | 0x08) & 0xfb));
995
996 smtcfb_setmode(sfb);
997
998 console_lock();
999 fb_set_suspend(&sfb->fb, 0);
1000 console_unlock();
1001
1002 return 0;
1003}
1004
1005static SIMPLE_DEV_PM_OPS(sm7xx_pm_ops, smtcfb_pci_suspend, smtcfb_pci_resume);
1006#define SM7XX_PM_OPS (&sm7xx_pm_ops)
1007
1008#else /* !CONFIG_PM */
1009
1010#define SM7XX_PM_OPS NULL
1011
1012#endif /* !CONFIG_PM */
1013
1014static struct pci_driver smtcfb_driver = {
1015 .name = "smtcfb",
1016 .id_table = smtcfb_pci_table,
1017 .probe = smtcfb_pci_probe,
1018 .remove = smtcfb_pci_remove,
1019 .driver.pm = SM7XX_PM_OPS,
1020};
1021
1022module_pci_driver(smtcfb_driver);
1023
1024MODULE_AUTHOR("Siliconmotion ");
1025MODULE_DESCRIPTION("Framebuffer driver for SMI Graphic Cards");
1026MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-09 08:08:06 -0400