10 files changed, 72 insertions, 83 deletions

diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 2deb05f618fb..7cb0818a13de 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -323,27 +323,27 @@ void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt)
 {
         struct intel_gvt_irq *irq = &gvt->irq;
         struct intel_vgpu *vgpu;
-        bool have_enabled_pipe = false;
         int pipe, id;
 
         if (WARN_ON(!mutex_is_locked(&gvt->lock)))
                 return;
 
-        hrtimer_cancel(&irq->vblank_timer.timer);
-
         for_each_active_vgpu(gvt, vgpu, id) {
                 for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {
-                        have_enabled_pipe =
-                                pipe_is_enabled(vgpu, pipe);
-                        if (have_enabled_pipe)
-                                break;
+                        if (pipe_is_enabled(vgpu, pipe))
+                                goto out;
                 }
         }
 
-        if (have_enabled_pipe)
-                hrtimer_start(&irq->vblank_timer.timer,
-                        ktime_add_ns(ktime_get(), irq->vblank_timer.period),
-                        HRTIMER_MODE_ABS);
+        /* all the pipes are disabled */
+        hrtimer_cancel(&irq->vblank_timer.timer);
+        return;
+
+out:
+        hrtimer_start(&irq->vblank_timer.timer,
+                ktime_add_ns(ktime_get(), irq->vblank_timer.period),
+                HRTIMER_MODE_ABS);
+
 }
 
 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
diff --git a/drivers/gpu/drm/i915/i915_gem_clflush.c b/drivers/gpu/drm/i915/i915_gem_clflush.c
index 152f16c11878..348b29a845c9 100644
--- a/drivers/gpu/drm/i915/i915_gem_clflush.c
+++ b/drivers/gpu/drm/i915/i915_gem_clflush.c
@@ -114,7 +114,7 @@ i915_clflush_notify(struct i915_sw_fence *fence,
         return NOTIFY_DONE;
 }
 
-void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
+bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
                              unsigned int flags)
 {
         struct clflush *clflush;
@@ -128,7 +128,7 @@ void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
          */
         if (!i915_gem_object_has_struct_page(obj)) {
                 obj->cache_dirty = false;
-                return;
+                return false;
         }
 
         /* If the GPU is snooping the contents of the CPU cache,
@@ -140,7 +140,7 @@ void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
          * tracking.
          */
         if (!(flags & I915_CLFLUSH_FORCE) && obj->cache_coherent)
-                return;
+                return false;
 
         trace_i915_gem_object_clflush(obj);
 
@@ -179,4 +179,5 @@ void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
         }
 
         obj->cache_dirty = false;
+        return true;
 }
diff --git a/drivers/gpu/drm/i915/i915_gem_clflush.h b/drivers/gpu/drm/i915/i915_gem_clflush.h
index 2455a7820937..f390247561b3 100644
--- a/drivers/gpu/drm/i915/i915_gem_clflush.h
+++ b/drivers/gpu/drm/i915/i915_gem_clflush.h
@@ -28,7 +28,7 @@
 struct drm_i915_private;
 struct drm_i915_gem_object;
 
-void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
+bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
                              unsigned int flags);
 #define I915_CLFLUSH_FORCE BIT(0)
 #define I915_CLFLUSH_SYNC BIT(1)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 054b2e54cdaf..e9503f6d1100 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -560,9 +560,6 @@ static int eb_reserve_vma(const struct i915_execbuffer *eb,
                 eb->args->flags |= __EXEC_HAS_RELOC;
         }
 
-        entry->flags |= __EXEC_OBJECT_HAS_PIN;
-        GEM_BUG_ON(eb_vma_misplaced(entry, vma));
-
         if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_FENCE)) {
                 err = i915_vma_get_fence(vma);
                 if (unlikely(err)) {
@@ -574,6 +571,9 @@ static int eb_reserve_vma(const struct i915_execbuffer *eb,
                         entry->flags |= __EXEC_OBJECT_HAS_FENCE;
         }
 
+        entry->flags |= __EXEC_OBJECT_HAS_PIN;
+        GEM_BUG_ON(eb_vma_misplaced(entry, vma));
+
         return 0;
 }
 
@@ -1458,7 +1458,7 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct i915_vma *vma)
          * to read. However, if the array is not writable the user loses
          * the updated relocation values.
          */
-        if (unlikely(!access_ok(VERIFY_READ, urelocs, remain*sizeof(urelocs))))
+        if (unlikely(!access_ok(VERIFY_READ, urelocs, remain*sizeof(*urelocs))))
                 return -EFAULT;
 
         do {
@@ -1775,7 +1775,7 @@ out:
                 }
         }
 
-        return err ?: have_copy;
+        return err;
 }
 
 static int eb_relocate(struct i915_execbuffer *eb)
@@ -1825,7 +1825,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
         int err;
 
         for (i = 0; i < count; i++) {
-                const struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
+                struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
                 struct i915_vma *vma = exec_to_vma(entry);
                 struct drm_i915_gem_object *obj = vma->obj;
 
@@ -1841,12 +1841,14 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
                         eb->request->capture_list = capture;
                 }
 
+                if (unlikely(obj->cache_dirty && !obj->cache_coherent)) {
+                        if (i915_gem_clflush_object(obj, 0))
+                                entry->flags &= ~EXEC_OBJECT_ASYNC;
+                }
+
                 if (entry->flags & EXEC_OBJECT_ASYNC)
                         goto skip_flushes;
 
-                if (unlikely(obj->cache_dirty && !obj->cache_coherent))
-                        i915_gem_clflush_object(obj, 0);
-
                 err = i915_gem_request_await_object
                         (eb->request, obj, entry->flags & EXEC_OBJECT_WRITE);
                 if (err)
@@ -2209,7 +2211,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
                 goto err_unlock;
 
         err = eb_relocate(&eb);
-        if (err)
+        if (err) {
                 /*
                  * If the user expects the execobject.offset and
                  * reloc.presumed_offset to be an exact match,
@@ -2218,8 +2220,8 @@ i915_gem_do_execbuffer(struct drm_device *dev,
                  * relocation.
                  */
                 args->flags &= ~__EXEC_HAS_RELOC;
-        if (err < 0)
                 goto err_vma;
+        }
 
         if (unlikely(eb.batch->exec_entry->flags & EXEC_OBJECT_WRITE)) {
                 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 4a673fc1a432..20cf272c97b1 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -284,12 +284,12 @@ static inline void __i915_vma_pin(struct i915_vma *vma)
 
 static inline void __i915_vma_unpin(struct i915_vma *vma)
 {
-        GEM_BUG_ON(!i915_vma_is_pinned(vma));
         vma->flags--;
 }
 
 static inline void i915_vma_unpin(struct i915_vma *vma)
 {
+        GEM_BUG_ON(!i915_vma_is_pinned(vma));
         GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
         __i915_vma_unpin(vma);
 }
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 80e96f1f49d2..9edeaaef77ad 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1896,8 +1896,8 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
                 val &= ~LOADGEN_SELECT;
 
-                if (((rate < 600000) && (width == 4) && (ln >= 1))  ||
-                    ((rate < 600000) && (width < 4) && ((ln == 1) || (ln == 2)))) {
+                if ((rate <= 600000 && width == 4 && ln >= 1)  ||
+                    (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
                         val |= LOADGEN_SELECT;
                 }
                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dec9e58545a1..9471c88d449e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3427,26 +3427,6 @@ static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
 }
 
-static void intel_update_primary_planes(struct drm_device *dev)
-{
-        struct drm_crtc *crtc;
-
-        for_each_crtc(dev, crtc) {
-                struct intel_plane *plane = to_intel_plane(crtc->primary);
-                struct intel_plane_state *plane_state =
-                        to_intel_plane_state(plane->base.state);
-
-                if (plane_state->base.visible) {
-                        trace_intel_update_plane(&plane->base,
-                                                 to_intel_crtc(crtc));
-
-                        plane->update_plane(plane,
-                                            to_intel_crtc_state(crtc->state),
-                                            plane_state);
-                }
-        }
-}
-
 static int
 __intel_display_resume(struct drm_device *dev,
                        struct drm_atomic_state *state,
@@ -3499,6 +3479,12 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv)
         struct drm_atomic_state *state;
         int ret;
 
+
+        /* reset doesn't touch the display */
+        if (!i915.force_reset_modeset_test &&
+            !gpu_reset_clobbers_display(dev_priv))
+                return;
+
         /*
          * Need mode_config.mutex so that we don't
          * trample ongoing ->detect() and whatnot.
@@ -3512,12 +3498,6 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv)
 
                 drm_modeset_backoff(ctx);
         }
-
-        /* reset doesn't touch the display, but flips might get nuked anyway, */
-        if (!i915.force_reset_modeset_test &&
-            !gpu_reset_clobbers_display(dev_priv))
-                return;
-
         /*
          * Disabling the crtcs gracefully seems nicer. Also the
          * g33 docs say we should at least disable all the planes.
@@ -3547,6 +3527,14 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
         int ret;
 
+        /* reset doesn't touch the display */
+        if (!i915.force_reset_modeset_test &&
+            !gpu_reset_clobbers_display(dev_priv))
+                return;
+
+        if (!state)
+                goto unlock;
+
         /*
          * Flips in the rings will be nuked by the reset,
          * so complete all pending flips so that user space
@@ -3558,22 +3546,10 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
 
         /* reset doesn't touch the display */
         if (!gpu_reset_clobbers_display(dev_priv)) {
-                if (!state) {
-                        /*
-                         * Flips in the rings have been nuked by the reset,
-                         * so update the base address of all primary
-                         * planes to the the last fb to make sure we're
-                         * showing the correct fb after a reset.
-                         *
-                         * FIXME: Atomic will make this obsolete since we won't schedule
-                         * CS-based flips (which might get lost in gpu resets) any more.
-                         */
-                        intel_update_primary_planes(dev);
-                } else {
-                        ret = __intel_display_resume(dev, state, ctx);
+                /* for testing only restore the display */
+                ret = __intel_display_resume(dev, state, ctx);
                         if (ret)
                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
-                }
         } else {
                 /*
                  * The display has been reset as well,
@@ -3597,8 +3573,8 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
                 intel_hpd_init(dev_priv);
         }
 
-        if (state)
-                drm_atomic_state_put(state);
+        drm_atomic_state_put(state);
+unlock:
         drm_modeset_drop_locks(ctx);
         drm_modeset_acquire_fini(ctx);
         mutex_unlock(&dev->mode_config.mutex);
@@ -9117,6 +9093,13 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
         u64 power_domain_mask;
         bool active;
 
+        if (INTEL_GEN(dev_priv) >= 9) {
+                intel_crtc_init_scalers(crtc, pipe_config);
+
+                pipe_config->scaler_state.scaler_id = -1;
+                pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
+        }
+
         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
                 return false;
@@ -9145,13 +9128,6 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
         pipe_config->gamma_mode =
                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
 
-        if (INTEL_GEN(dev_priv) >= 9) {
-                intel_crtc_init_scalers(crtc, pipe_config);
-
-                pipe_config->scaler_state.scaler_id = -1;
-                pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
-        }
-
         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
                 power_domain_mask |= BIT_ULL(power_domain);
@@ -9540,7 +9516,16 @@ static void i9xx_update_cursor(struct intel_plane *plane,
          * On some platforms writing CURCNTR first will also
          * cause CURPOS to be armed by the CURBASE write.
          * Without the CURCNTR write the CURPOS write would
-         * arm itself.
+         * arm itself. Thus we always start the full update
+         * with a CURCNTR write.
+         *
+         * On other platforms CURPOS always requires the
+         * CURBASE write to arm the update. Additonally
+         * a write to any of the cursor register will cancel
+         * an already armed cursor update. Thus leaving out
+         * the CURBASE write after CURPOS could lead to a
+         * cursor that doesn't appear to move, or even change
+         * shape. Thus we always write CURBASE.
          *
          * CURCNTR and CUR_FBC_CTL are always
          * armed by the CURBASE write only.
@@ -9559,6 +9544,7 @@ static void i9xx_update_cursor(struct intel_plane *plane,
                 plane->cursor.cntl = cntl;
         } else {
                 I915_WRITE_FW(CURPOS(pipe), pos);
+                I915_WRITE_FW(CURBASE(pipe), base);
         }
 
         POSTING_READ_FW(CURBASE(pipe));
diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index 52d5b82790d9..c17ed0e62b67 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -45,7 +45,7 @@ static bool is_supported_device(struct drm_i915_private *dev_priv)
                 return true;
         if (IS_SKYLAKE(dev_priv))
                 return true;
-        if (IS_KABYLAKE(dev_priv) && INTEL_DEVID(dev_priv) == 0x591D)
+        if (IS_KABYLAKE(dev_priv))
                 return true;
         return false;
 }
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 48ea0fca1f72..40b224b44d1b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4463,8 +4463,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
                 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
                     (plane_bytes_per_line / 512 < 1))
                         selected_result = method2;
-                else if ((ddb_allocation && ddb_allocation /
-                        fixed_16_16_to_u32_round_up(plane_blocks_per_line)) >= 1)
+                else if (ddb_allocation >=
+                         fixed_16_16_to_u32_round_up(plane_blocks_per_line))
                         selected_result = min_fixed_16_16(method1, method2);
                 else if (latency >= linetime_us)
                         selected_result = min_fixed_16_16(method1, method2);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 627e2aa09766..8cdec455cf7d 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -206,7 +206,7 @@ struct drm_i915_private *mock_gem_device(void)
         mkwrite_device_info(i915)->ring_mask = BIT(0);
         i915->engine[RCS] = mock_engine(i915, "mock");
         if (!i915->engine[RCS])
-                goto err_dependencies;
+                goto err_priorities;
 
         i915->kernel_context = mock_context(i915, NULL);
         if (!i915->kernel_context)