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-rw-r--r--Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt6
-rw-r--r--arch/arm64/boot/dts/allwinner/Makefile2
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts3
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts3
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts3
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts3
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts8
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts265
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi99
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts29
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi175
11 files changed, 584 insertions, 12 deletions
diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
index 62dd5baad70e..04fc368d828f 100644
--- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
@@ -2,8 +2,10 @@ Allwinner SoCs Watchdog timer
2 2
3Required properties: 3Required properties:
4 4
5- compatible : should be either "allwinner,sun4i-a10-wdt" or 5- compatible : should be one of
6 "allwinner,sun6i-a31-wdt" 6 "allwinner,sun4i-a10-wdt"
7 "allwinner,sun6i-a31-wdt"
8 "allwinner,sun50i-a64-wdt","allwinner,sun6i-a31-wdt"
7- reg : Specifies base physical address and size of the registers. 9- reg : Specifies base physical address and size of the registers.
8 10
9Example: 11Example:
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index f505227b0250..d19ba8b2f5b6 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -5,8 +5,10 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb
5dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb 5dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
6dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb 6dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
7dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb 7dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
8dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
8dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb 9dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
9dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb 10dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
10dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb 11dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
11dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb 12dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
12dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb 13dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
14dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index a6975670cd1c..2250dec9974c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -120,8 +120,7 @@
120 pinctrl-names = "default"; 120 pinctrl-names = "default";
121 pinctrl-0 = <&mmc0_pins>; 121 pinctrl-0 = <&mmc0_pins>;
122 vmmc-supply = <&reg_dcdc1>; 122 vmmc-supply = <&reg_dcdc1>;
123 cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; 123 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
124 cd-inverted;
125 disable-wp; 124 disable-wp;
126 bus-width = <4>; 125 bus-width = <4>;
127 status = "okay"; 126 status = "okay";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
index 2beef9e6cb88..e2dce48fa29a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
@@ -82,8 +82,7 @@
82 pinctrl-names = "default"; 82 pinctrl-names = "default";
83 pinctrl-0 = <&mmc0_pins>; 83 pinctrl-0 = <&mmc0_pins>;
84 vmmc-supply = <&reg_dcdc1>; 84 vmmc-supply = <&reg_dcdc1>;
85 cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; 85 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
86 cd-inverted;
87 disable-wp; 86 disable-wp;
88 bus-width = <4>; 87 bus-width = <4>;
89 status = "okay"; 88 status = "okay";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
index 8807664f363a..3b3081b10ecb 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
@@ -68,8 +68,7 @@
68 pinctrl-names = "default"; 68 pinctrl-names = "default";
69 pinctrl-0 = <&mmc0_pins>; 69 pinctrl-0 = <&mmc0_pins>;
70 vmmc-supply = <&reg_dcdc1>; 70 vmmc-supply = <&reg_dcdc1>;
71 cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; 71 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
72 cd-inverted;
73 disable-wp; 72 disable-wp;
74 bus-width = <4>; 73 bus-width = <4>;
75 status = "okay"; 74 status = "okay";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
index 240d35731d10..bf42690a3361 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
@@ -67,8 +67,7 @@
67 pinctrl-names = "default"; 67 pinctrl-names = "default";
68 pinctrl-0 = <&mmc0_pins>; 68 pinctrl-0 = <&mmc0_pins>;
69 vmmc-supply = <&reg_dcdc1>; 69 vmmc-supply = <&reg_dcdc1>;
70 cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; 70 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
71 cd-inverted;
72 status = "okay"; 71 status = "okay";
73}; 72};
74 73
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index 604cdaedac38..a75825798a71 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -103,8 +103,7 @@
103 pinctrl-names = "default"; 103 pinctrl-names = "default";
104 pinctrl-0 = <&mmc0_pins>; 104 pinctrl-0 = <&mmc0_pins>;
105 vmmc-supply = <&reg_dcdc1>; 105 vmmc-supply = <&reg_dcdc1>;
106 cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; 106 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
107 cd-inverted;
108 disable-wp; 107 disable-wp;
109 bus-width = <4>; 108 bus-width = <4>;
110 status = "okay"; 109 status = "okay";
@@ -230,6 +229,11 @@
230 regulator-name = "vcc-rtc"; 229 regulator-name = "vcc-rtc";
231}; 230};
232 231
232/* On Euler connector */
233&spdif {
234 status = "disabled";
235};
236
233/* On Exp and Euler connectors */ 237/* On Exp and Euler connectors */
234&uart0 { 238&uart0 {
235 pinctrl-names = "default"; 239 pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
new file mode 100644
index 000000000000..d9baab3dc96b
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
@@ -0,0 +1,265 @@
1/*
2 * Copyright (C) Harald Geyer <harald@ccbib.org>
3 * based on sun50i-a64-olinuxino.dts by Jagan Teki <jteki@openedev.com>
4 *
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 */
7
8/dts-v1/;
9
10#include "sun50i-a64.dtsi"
11
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/input/input.h>
14#include <dt-bindings/pwm/pwm.h>
15
16/ {
17 model = "Olimex A64 Teres-I";
18 compatible = "olimex,a64-teres-i", "allwinner,sun50i-a64";
19
20 aliases {
21 serial0 = &uart0;
22 };
23
24 chosen {
25 stdout-path = "serial0:115200n8";
26
27 framebuffer-lcd {
28 eDP25-supply = <&reg_dldo2>;
29 eDP12-supply = <&reg_dldo3>;
30 };
31 };
32
33 gpio-keys {
34 compatible = "gpio-keys";
35
36 lid-switch {
37 label = "Lid Switch";
38 gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */
39 linux,input-type = <EV_SW>;
40 linux,code = <SW_LID>;
41 };
42 };
43
44 leds {
45 compatible = "gpio-leds";
46
47 capslock {
48 label = "teres-i:green:capslock";
49 gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */
50 };
51
52 numlock {
53 label = "teres-i:green:numlock";
54 gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
55 };
56 };
57
58 reg_usb1_vbus: usb1-vbus {
59 compatible = "regulator-fixed";
60 regulator-name = "usb1-vbus";
61 regulator-min-microvolt = <5000000>;
62 regulator-max-microvolt = <5000000>;
63 enable-active-high;
64 gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
65 status = "okay";
66 };
67
68 wifi_pwrseq: wifi_pwrseq {
69 compatible = "mmc-pwrseq-simple";
70 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
71 };
72};
73
74&ehci1 {
75 status = "okay";
76};
77
78
79/* The ANX6345 eDP-bridge is on i2c0. There is no linux (mainline)
80 * driver for this chip at the moment, the bootloader initializes it.
81 * However it can be accessed with the i2c-dev driver from user space.
82 */
83&i2c0 {
84 clock-frequency = <100000>;
85 pinctrl-names = "default";
86 pinctrl-0 = <&i2c0_pins>;
87 status = "okay";
88};
89
90&mmc0 {
91 pinctrl-names = "default";
92 pinctrl-0 = <&mmc0_pins>;
93 vmmc-supply = <&reg_dcdc1>;
94 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
95 disable-wp;
96 bus-width = <4>;
97 status = "okay";
98};
99
100&mmc1 {
101 pinctrl-names = "default";
102 pinctrl-0 = <&mmc1_pins>;
103 vmmc-supply = <&reg_aldo2>;
104 vqmmc-supply = <&reg_dldo4>;
105 mmc-pwrseq = <&wifi_pwrseq>;
106 bus-width = <4>;
107 non-removable;
108 status = "okay";
109
110 rtl8723bs: wifi@1 {
111 reg = <1>;
112 interrupt-parent = <&r_pio>;
113 interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
114 interrupt-names = "host-wake";
115 };
116};
117
118&mmc2 {
119 pinctrl-names = "default";
120 pinctrl-0 = <&mmc2_pins>;
121 vmmc-supply = <&reg_dcdc1>;
122 vqmmc-supply = <&reg_dcdc1>;
123 bus-width = <8>;
124 non-removable;
125 cap-mmc-hw-reset;
126 status = "okay";
127};
128
129&ohci1 {
130 status = "okay";
131};
132
133&r_rsb {
134 status = "okay";
135
136 axp803: pmic@3a3 {
137 compatible = "x-powers,axp803";
138 reg = <0x3a3>;
139 interrupt-parent = <&r_intc>;
140 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
141 wakeup-source;
142 };
143};
144
145#include "axp803.dtsi"
146
147&reg_aldo1 {
148 regulator-always-on;
149 regulator-min-microvolt = <2800000>;
150 regulator-max-microvolt = <2800000>;
151 regulator-name = "vcc-pe";
152};
153
154&reg_aldo2 {
155 regulator-always-on;
156 regulator-min-microvolt = <3300000>;
157 regulator-max-microvolt = <3300000>;
158 regulator-name = "vcc-pl";
159};
160
161&reg_aldo3 {
162 regulator-always-on;
163 regulator-min-microvolt = <3000000>;
164 regulator-max-microvolt = <3000000>;
165 regulator-name = "vcc-pll-avcc";
166};
167
168&reg_dcdc1 {
169 regulator-always-on;
170 regulator-min-microvolt = <3300000>;
171 regulator-max-microvolt = <3300000>;
172 regulator-name = "vcc-3v3";
173};
174
175&reg_dcdc2 {
176 regulator-always-on;
177 regulator-min-microvolt = <1040000>;
178 regulator-max-microvolt = <1300000>;
179 regulator-name = "vdd-cpux";
180};
181
182/* DCDC3 is polyphased with DCDC2 */
183
184&reg_dcdc5 {
185 regulator-always-on;
186 regulator-min-microvolt = <1500000>;
187 regulator-max-microvolt = <1500000>;
188 regulator-name = "vcc-ddr3";
189};
190
191&reg_dcdc6 {
192 regulator-always-on;
193 regulator-min-microvolt = <1100000>;
194 regulator-max-microvolt = <1100000>;
195 regulator-name = "vdd-sys";
196};
197
198&reg_dldo1 {
199 regulator-min-microvolt = <3300000>;
200 regulator-max-microvolt = <3300000>;
201 regulator-name = "vcc-hdmi";
202};
203
204&reg_dldo2 {
205 regulator-min-microvolt = <2500000>;
206 regulator-max-microvolt = <2500000>;
207 regulator-name = "vcc-pd";
208};
209
210&reg_dldo3 {
211 regulator-min-microvolt = <1200000>;
212 regulator-max-microvolt = <1200000>;
213 regulator-name = "eDP12";
214};
215
216&reg_dldo4 {
217 regulator-min-microvolt = <3300000>;
218 regulator-max-microvolt = <3300000>;
219 regulator-name = "vcc-wifi-io";
220};
221
222&reg_eldo1 {
223 regulator-min-microvolt = <1800000>;
224 regulator-max-microvolt = <1800000>;
225 regulator-name = "cpvdd";
226};
227
228&reg_eldo2 {
229 regulator-min-microvolt = <1800000>;
230 regulator-max-microvolt = <1800000>;
231 regulator-name = "vcc-dvdd-csi";
232};
233
234&reg_fldo1 {
235 regulator-min-microvolt = <1200000>;
236 regulator-max-microvolt = <1200000>;
237 regulator-name = "vcc-1v2-hsic";
238};
239
240/*
241 * The A64 chip cannot work without this regulator off, although
242 * it seems to be only driving the AR100 core.
243 * Maybe we don't still know well about CPUs domain.
244 */
245&reg_fldo2 {
246 regulator-always-on;
247 regulator-min-microvolt = <1100000>;
248 regulator-max-microvolt = <1100000>;
249 regulator-name = "vdd-cpus";
250};
251
252&reg_rtc_ldo {
253 regulator-name = "vcc-rtc";
254};
255
256&uart0 {
257 pinctrl-names = "default";
258 pinctrl-0 = <&uart0_pins_a>;
259 status = "okay";
260};
261
262&usbphy {
263 usb1_vbus-supply = <&reg_usb1_vbus>;
264 status = "okay";
265};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index d783d164b9c3..1b2ef28c42bd 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -52,6 +52,26 @@
52 #address-cells = <1>; 52 #address-cells = <1>;
53 #size-cells = <1>; 53 #size-cells = <1>;
54 54
55 chosen {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 ranges;
59
60/*
61 * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU.
62 * However there is no support for this clock on A64 yet, so we depend
63 * on the upstream clocks here to keep them (and thus CLK_MIXER0) up.
64 */
65 simplefb_lcd: framebuffer-lcd {
66 compatible = "allwinner,simple-framebuffer",
67 "simple-framebuffer";
68 allwinner,pipeline = "mixer0-lcd0";
69 clocks = <&ccu CLK_TCON0>,
70 <&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
71 status = "disabled";
72 };
73 };
74
55 cpus { 75 cpus {
56 #address-cells = <1>; 76 #address-cells = <1>;
57 #size-cells = <0>; 77 #size-cells = <0>;
@@ -112,6 +132,24 @@
112 method = "smc"; 132 method = "smc";
113 }; 133 };
114 134
135 sound_spdif {
136 compatible = "simple-audio-card";
137 simple-audio-card,name = "On-board SPDIF";
138
139 simple-audio-card,cpu {
140 sound-dai = <&spdif>;
141 };
142
143 simple-audio-card,codec {
144 sound-dai = <&spdif_out>;
145 };
146 };
147
148 spdif_out: spdif-out {
149 #sound-dai-cells = <0>;
150 compatible = "linux,spdif-dit";
151 };
152
115 timer { 153 timer {
116 compatible = "arm,armv8-timer"; 154 compatible = "arm,armv8-timer";
117 interrupts = <GIC_PPI 13 155 interrupts = <GIC_PPI 13
@@ -291,6 +329,11 @@
291 interrupt-controller; 329 interrupt-controller;
292 #interrupt-cells = <3>; 330 #interrupt-cells = <3>;
293 331
332 i2c0_pins: i2c0_pins {
333 pins = "PH0", "PH1";
334 function = "i2c0";
335 };
336
294 i2c1_pins: i2c1_pins { 337 i2c1_pins: i2c1_pins {
295 pins = "PH2", "PH3"; 338 pins = "PH2", "PH3";
296 function = "i2c1"; 339 function = "i2c1";
@@ -336,6 +379,11 @@
336 drive-strength = <40>; 379 drive-strength = <40>;
337 }; 380 };
338 381
382 spdif_tx_pin: spdif {
383 pins = "PH8";
384 function = "spdif";
385 };
386
339 spi0_pins: spi0 { 387 spi0_pins: spi0 {
340 pins = "PC0", "PC1", "PC2", "PC3"; 388 pins = "PC0", "PC1", "PC2", "PC3";
341 function = "spi0"; 389 function = "spi0";
@@ -382,6 +430,50 @@
382 }; 430 };
383 }; 431 };
384 432
433 spdif: spdif@1c21000 {
434 #sound-dai-cells = <0>;
435 compatible = "allwinner,sun50i-a64-spdif",
436 "allwinner,sun8i-h3-spdif";
437 reg = <0x01c21000 0x400>;
438 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
440 resets = <&ccu RST_BUS_SPDIF>;
441 clock-names = "apb", "spdif";
442 dmas = <&dma 2>;
443 dma-names = "tx";
444 pinctrl-names = "default";
445 pinctrl-0 = <&spdif_tx_pin>;
446 status = "disabled";
447 };
448
449 i2s0: i2s@1c22000 {
450 #sound-dai-cells = <0>;
451 compatible = "allwinner,sun50i-a64-i2s",
452 "allwinner,sun8i-h3-i2s";
453 reg = <0x01c22000 0x400>;
454 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
456 clock-names = "apb", "mod";
457 resets = <&ccu RST_BUS_I2S0>;
458 dma-names = "rx", "tx";
459 dmas = <&dma 3>, <&dma 3>;
460 status = "disabled";
461 };
462
463 i2s1: i2s@1c22400 {
464 #sound-dai-cells = <0>;
465 compatible = "allwinner,sun50i-a64-i2s",
466 "allwinner,sun8i-h3-i2s";
467 reg = <0x01c22400 0x400>;
468 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
470 clock-names = "apb", "mod";
471 resets = <&ccu RST_BUS_I2S1>;
472 dma-names = "rx", "tx";
473 dmas = <&dma 4>, <&dma 4>;
474 status = "disabled";
475 };
476
385 uart0: serial@1c28000 { 477 uart0: serial@1c28000 {
386 compatible = "snps,dw-apb-uart"; 478 compatible = "snps,dw-apb-uart";
387 reg = <0x01c28000 0x400>; 479 reg = <0x01c28000 0x400>;
@@ -593,5 +685,12 @@
593 #address-cells = <1>; 685 #address-cells = <1>;
594 #size-cells = <0>; 686 #size-cells = <0>;
595 }; 687 };
688
689 wdt0: watchdog@1c20ca0 {
690 compatible = "allwinner,sun50i-a64-wdt",
691 "allwinner,sun6i-a31-wdt";
692 reg = <0x01c20ca0 0x20>;
693 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
694 };
596 }; 695 };
597}; 696};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
new file mode 100644
index 000000000000..d36de5eb81f3
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -0,0 +1,29 @@
1// SPDX-License-Identifier: (GPL-2.0+ or MIT)
2/*
3 * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
4 */
5
6/dts-v1/;
7
8#include "sun50i-h6.dtsi"
9
10#include <dt-bindings/gpio/gpio.h>
11
12/ {
13 model = "Pine H64";
14 compatible = "pine64,pine-h64", "allwinner,sun50i-h6";
15
16 aliases {
17 serial0 = &uart0;
18 };
19
20 chosen {
21 stdout-path = "serial0:115200n8";
22 };
23};
24
25&uart0 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&uart0_ph_pins>;
28 status = "okay";
29};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
new file mode 100644
index 000000000000..56563150d61a
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -0,0 +1,175 @@
1// SPDX-License-Identifier: (GPL-2.0+ or MIT)
2/*
3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7
8/ {
9 interrupt-parent = <&gic>;
10 #address-cells = <1>;
11 #size-cells = <1>;
12
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16
17 cpu0: cpu@0 {
18 compatible = "arm,cortex-a53", "arm,armv8";
19 device_type = "cpu";
20 reg = <0>;
21 enable-method = "psci";
22 };
23
24 cpu1: cpu@1 {
25 compatible = "arm,cortex-a53", "arm,armv8";
26 device_type = "cpu";
27 reg = <1>;
28 enable-method = "psci";
29 };
30
31 cpu2: cpu@2 {
32 compatible = "arm,cortex-a53", "arm,armv8";
33 device_type = "cpu";
34 reg = <2>;
35 enable-method = "psci";
36 };
37
38 cpu3: cpu@3 {
39 compatible = "arm,cortex-a53", "arm,armv8";
40 device_type = "cpu";
41 reg = <3>;
42 enable-method = "psci";
43 };
44 };
45
46 iosc: internal-osc-clk {
47 #clock-cells = <0>;
48 compatible = "fixed-clock";
49 clock-frequency = <16000000>;
50 clock-accuracy = <300000000>;
51 clock-output-names = "iosc";
52 };
53
54 osc24M: osc24M_clk {
55 #clock-cells = <0>;
56 compatible = "fixed-clock";
57 clock-frequency = <24000000>;
58 clock-output-names = "osc24M";
59 };
60
61 osc32k: osc32k_clk {
62 #clock-cells = <0>;
63 compatible = "fixed-clock";
64 clock-frequency = <32768>;
65 clock-output-names = "osc32k";
66 };
67
68 psci {
69 compatible = "arm,psci-0.2";
70 method = "smc";
71 };
72
73 timer {
74 compatible = "arm,armv8-timer";
75 interrupts = <GIC_PPI 13
76 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
77 <GIC_PPI 14
78 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
79 <GIC_PPI 11
80 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
81 <GIC_PPI 10
82 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
83 };
84
85 soc {
86 compatible = "simple-bus";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 ranges;
90
91 ccu: clock@3001000 {
92 compatible = "allwinner,sun50i-h6-ccu";
93 reg = <0x03001000 0x1000>;
94 clocks = <&osc24M>, <&osc32k>, <&iosc>;
95 clock-names = "hosc", "losc", "iosc";
96 #clock-cells = <1>;
97 #reset-cells = <1>;
98 };
99
100 gic: interrupt-controller@3021000 {
101 compatible = "arm,gic-400";
102 reg = <0x03021000 0x1000>,
103 <0x03022000 0x2000>,
104 <0x03024000 0x2000>,
105 <0x03026000 0x2000>;
106 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
107 interrupt-controller;
108 #interrupt-cells = <3>;
109 };
110
111 pio: pinctrl@300b000 {
112 compatible = "allwinner,sun50i-h6-pinctrl";
113 reg = <0x0300b000 0x400>;
114 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
116 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
118 clocks = <&ccu 26>, <&osc24M>, <&osc32k>;
119 clock-names = "apb", "hosc", "losc";
120 gpio-controller;
121 #gpio-cells = <3>;
122 interrupt-controller;
123 #interrupt-cells = <3>;
124
125 uart0_ph_pins: uart0-ph {
126 pins = "PH0", "PH1";
127 function = "uart0";
128 };
129 };
130
131 uart0: serial@5000000 {
132 compatible = "snps,dw-apb-uart";
133 reg = <0x05000000 0x400>;
134 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
135 reg-shift = <2>;
136 reg-io-width = <4>;
137 clocks = <&ccu 70>;
138 resets = <&ccu 21>;
139 status = "disabled";
140 };
141
142 uart1: serial@5000400 {
143 compatible = "snps,dw-apb-uart";
144 reg = <0x05000400 0x400>;
145 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
146 reg-shift = <2>;
147 reg-io-width = <4>;
148 clocks = <&ccu 71>;
149 resets = <&ccu 22>;
150 status = "disabled";
151 };
152
153 uart2: serial@5000800 {
154 compatible = "snps,dw-apb-uart";
155 reg = <0x05000800 0x400>;
156 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
157 reg-shift = <2>;
158 reg-io-width = <4>;
159 clocks = <&ccu 72>;
160 resets = <&ccu 23>;
161 status = "disabled";
162 };
163
164 uart3: serial@5000c00 {
165 compatible = "snps,dw-apb-uart";
166 reg = <0x05000c00 0x400>;
167 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
168 reg-shift = <2>;
169 reg-io-width = <4>;
170 clocks = <&ccu 73>;
171 resets = <&ccu 24>;
172 status = "disabled";
173 };
174 };
175};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 19:15:10 -0400