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-rw-r--r--arch/arm/mach-lpc32xx/phy3250.c84
-rw-r--r--arch/arm/mach-lpc32xx/pm.c13
2 files changed, 3 insertions, 94 deletions
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index e48cc06c2aec..b3be60a8e467 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -45,73 +45,6 @@
45#include <mach/board.h> 45#include <mach/board.h>
46#include "common.h" 46#include "common.h"
47 47
48/*
49 * AMBA LCD controller
50 */
51static struct clcd_panel conn_lcd_panel = {
52 .mode = {
53 .name = "QVGA portrait",
54 .refresh = 60,
55 .xres = 240,
56 .yres = 320,
57 .pixclock = 191828,
58 .left_margin = 22,
59 .right_margin = 11,
60 .upper_margin = 2,
61 .lower_margin = 1,
62 .hsync_len = 5,
63 .vsync_len = 2,
64 .sync = 0,
65 .vmode = FB_VMODE_NONINTERLACED,
66 },
67 .width = -1,
68 .height = -1,
69 .tim2 = (TIM2_IVS | TIM2_IHS),
70 .cntl = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
71 CNTL_LCDBPP16_565),
72 .bpp = 16,
73};
74#define PANEL_SIZE (3 * SZ_64K)
75
76static int lpc32xx_clcd_setup(struct clcd_fb *fb)
77{
78 dma_addr_t dma;
79
80 fb->fb.screen_base = dma_alloc_wc(&fb->dev->dev, PANEL_SIZE, &dma,
81 GFP_KERNEL);
82 if (!fb->fb.screen_base) {
83 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
84 return -ENOMEM;
85 }
86
87 fb->fb.fix.smem_start = dma;
88 fb->fb.fix.smem_len = PANEL_SIZE;
89 fb->panel = &conn_lcd_panel;
90
91 return 0;
92}
93
94static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
95{
96 return dma_mmap_wc(&fb->dev->dev, vma, fb->fb.screen_base,
97 fb->fb.fix.smem_start, fb->fb.fix.smem_len);
98}
99
100static void lpc32xx_clcd_remove(struct clcd_fb *fb)
101{
102 dma_free_wc(&fb->dev->dev, fb->fb.fix.smem_len, fb->fb.screen_base,
103 fb->fb.fix.smem_start);
104}
105
106static struct clcd_board lpc32xx_clcd_data = {
107 .name = "Phytec LCD",
108 .check = clcdfb_check,
109 .decode = clcdfb_decode,
110 .setup = lpc32xx_clcd_setup,
111 .mmap = lpc32xx_clcd_mmap,
112 .remove = lpc32xx_clcd_remove,
113};
114
115static struct pl08x_channel_data pl08x_slave_channels[] = { 48static struct pl08x_channel_data pl08x_slave_channels[] = {
116 { 49 {
117 .bus_id = "nand-slc", 50 .bus_id = "nand-slc",
@@ -148,11 +81,6 @@ static struct pl08x_platform_data pl08x_pd = {
148 .mem_buses = PL08X_AHB1, 81 .mem_buses = PL08X_AHB1,
149}; 82};
150 83
151static struct mmci_platform_data lpc32xx_mmci_data = {
152 .ocr_mask = MMC_VDD_30_31 | MMC_VDD_31_32 |
153 MMC_VDD_32_33 | MMC_VDD_33_34,
154};
155
156static struct lpc32xx_slc_platform_data lpc32xx_slc_data = { 84static struct lpc32xx_slc_platform_data lpc32xx_slc_data = {
157 .dma_filter = pl08x_filter_id, 85 .dma_filter = pl08x_filter_id,
158}; 86};
@@ -164,10 +92,7 @@ static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = {
164static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { 92static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
165 OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", NULL), 93 OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", NULL),
166 OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", NULL), 94 OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", NULL),
167 OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
168 OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd), 95 OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
169 OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd",
170 &lpc32xx_mmci_data),
171 OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash", 96 OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash",
172 &lpc32xx_slc_data), 97 &lpc32xx_slc_data),
173 OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash", 98 OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
@@ -177,15 +102,6 @@ static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
177 102
178static void __init lpc3250_machine_init(void) 103static void __init lpc3250_machine_init(void)
179{ 104{
180 u32 tmp;
181
182 /* Setup LCD muxing to RGB565 */
183 tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
184 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
185 LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
186 tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
187 __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
188
189 lpc32xx_serial_init(); 105 lpc32xx_serial_init();
190 106
191 /* Test clock needed for UDA1380 initial init */ 107 /* Test clock needed for UDA1380 initial init */
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
index 62471570d586..32bca351a73b 100644
--- a/arch/arm/mach-lpc32xx/pm.c
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -86,17 +86,10 @@ static int lpc32xx_pm_enter(suspend_state_t state)
86 void *iram_swap_area; 86 void *iram_swap_area;
87 87
88 /* Allocate some space for temporary IRAM storage */ 88 /* Allocate some space for temporary IRAM storage */
89 iram_swap_area = kmalloc(lpc32xx_sys_suspend_sz, GFP_KERNEL); 89 iram_swap_area = kmemdup((void *)TEMP_IRAM_AREA,
90 if (!iram_swap_area) { 90 lpc32xx_sys_suspend_sz, GFP_KERNEL);
91 printk(KERN_ERR 91 if (!iram_swap_area)
92 "PM Suspend: cannot allocate memory to save portion "
93 "of SRAM\n");
94 return -ENOMEM; 92 return -ENOMEM;
95 }
96
97 /* Backup a small area of IRAM used for the suspend code */
98 memcpy(iram_swap_area, (void *) TEMP_IRAM_AREA,
99 lpc32xx_sys_suspend_sz);
100 93
101 /* 94 /*
102 * Copy code to suspend system into IRAM. The suspend code 95 * Copy code to suspend system into IRAM. The suspend code