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-rw-r--r--Documentation/devicetree/bindings/thermal/armada-thermal.txt12
-rw-r--r--Documentation/devicetree/bindings/thermal/exynos-thermal.txt50
-rw-r--r--drivers/thermal/Kconfig14
-rw-r--r--drivers/thermal/Makefile1
-rw-r--r--drivers/thermal/armada_thermal.c158
-rw-r--r--drivers/thermal/int3403_thermal.c8
-rw-r--r--drivers/thermal/intel_powerclamp.c2
-rw-r--r--drivers/thermal/intel_soc_dts_thermal.c479
-rw-r--r--drivers/thermal/rcar_thermal.c9
-rw-r--r--drivers/thermal/samsung/exynos_tmu.c86
-rw-r--r--drivers/thermal/samsung/exynos_tmu.h23
-rw-r--r--drivers/thermal/samsung/exynos_tmu_data.c211
-rw-r--r--drivers/thermal/samsung/exynos_tmu_data.h31
-rw-r--r--drivers/thermal/spear_thermal.c4
-rw-r--r--drivers/thermal/ti-soc-thermal/ti-bandgap.c2
15 files changed, 1015 insertions, 75 deletions
diff --git a/Documentation/devicetree/bindings/thermal/armada-thermal.txt b/Documentation/devicetree/bindings/thermal/armada-thermal.txt
index fff93d5f92de..4cf024929a3f 100644
--- a/Documentation/devicetree/bindings/thermal/armada-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/armada-thermal.txt
@@ -1,11 +1,21 @@
1* Marvell Armada 370/XP thermal management 1* Marvell Armada 370/375/380/XP thermal management
2 2
3Required properties: 3Required properties:
4 4
5- compatible: Should be set to one of the following: 5- compatible: Should be set to one of the following:
6 marvell,armada370-thermal 6 marvell,armada370-thermal
7 marvell,armada375-thermal
8 marvell,armada375-z1-thermal
9 marvell,armada380-thermal
7 marvell,armadaxp-thermal 10 marvell,armadaxp-thermal
8 11
12 Note: As the name suggests, "marvell,armada375-z1-thermal"
13 applies for the SoC Z1 stepping only. On such stepping
14 some quirks need to be done and the register offset differs
15 from the one in the A0 stepping.
16 The operating system may auto-detect the SoC stepping and
17 update the compatible and register offsets at runtime.
18
9- reg: Device's register space. 19- reg: Device's register space.
10 Two entries are expected, see the examples below. 20 Two entries are expected, see the examples below.
11 The first one is required for the sensor register; 21 The first one is required for the sensor register;
diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index 284f5300fd8b..c94909215c07 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -6,16 +6,35 @@
6 "samsung,exynos4412-tmu" 6 "samsung,exynos4412-tmu"
7 "samsung,exynos4210-tmu" 7 "samsung,exynos4210-tmu"
8 "samsung,exynos5250-tmu" 8 "samsung,exynos5250-tmu"
9 "samsung,exynos5260-tmu"
10 "samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420
11 "samsung,exynos5420-tmu-ext-triminfo" for TMU channels 2, 3 and 4
12 Exynos5420 (Must pass triminfo base and triminfo clock)
9 "samsung,exynos5440-tmu" 13 "samsung,exynos5440-tmu"
10- interrupt-parent : The phandle for the interrupt controller 14- interrupt-parent : The phandle for the interrupt controller
11- reg : Address range of the thermal registers. For soc's which has multiple 15- reg : Address range of the thermal registers. For soc's which has multiple
12 instances of TMU and some registers are shared across all TMU's like 16 instances of TMU and some registers are shared across all TMU's like
13 interrupt related then 2 set of register has to supplied. First set 17 interrupt related then 2 set of register has to supplied. First set
14 belongs to each instance of TMU and second set belongs to common TMU 18 belongs to register set of TMU instance and second set belongs to
15 registers. 19 registers shared with the TMU instance.
20
21 NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
22 channels 2, 3 and 4
23 Use "samsung,exynos5420-tmu-ext-triminfo" in cases, there is a misplaced
24 register, also provide clock to access that base.
25
26 TRIMINFO at 0x1006c000 contains data for TMU channel 3
27 TRIMINFO at 0x100a0000 contains data for TMU channel 4
28 TRIMINFO at 0x10068000 contains data for TMU channel 2
29
16- interrupts : Should contain interrupt for thermal system 30- interrupts : Should contain interrupt for thermal system
17- clocks : The main clock for TMU device 31- clocks : The main clocks for TMU device
32 -- 1. operational clock for TMU channel
33 -- 2. optional clock to access the shared registers of TMU channel
18- clock-names : Thermal system clock name 34- clock-names : Thermal system clock name
35 -- "tmu_apbif" operational clock for current TMU channel
36 -- "tmu_triminfo_apbif" clock to access the shared triminfo register
37 for current TMU channel
19- vtmu-supply: This entry is optional and provides the regulator node supplying 38- vtmu-supply: This entry is optional and provides the regulator node supplying
20 voltage to TMU. If needed this entry can be placed inside 39 voltage to TMU. If needed this entry can be placed inside
21 board/platform specific dts file. 40 board/platform specific dts file.
@@ -43,6 +62,31 @@ Example 2):
43 clock-names = "tmu_apbif"; 62 clock-names = "tmu_apbif";
44 }; 63 };
45 64
65Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register")
66 tmu_cpu2: tmu@10068000 {
67 compatible = "samsung,exynos5420-tmu-ext-triminfo";
68 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
69 interrupts = <0 184 0>;
70 clocks = <&clock 318>, <&clock 318>;
71 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
72 };
73
74 tmu_cpu3: tmu@1006c000 {
75 compatible = "samsung,exynos5420-tmu-ext-triminfo";
76 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
77 interrupts = <0 185 0>;
78 clocks = <&clock 318>, <&clock 319>;
79 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
80 };
81
82 tmu_gpu: tmu@100a0000 {
83 compatible = "samsung,exynos5420-tmu-ext-triminfo";
84 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
85 interrupts = <0 215 0>;
86 clocks = <&clock 319>, <&clock 318>;
87 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
88 };
89
46Note: For multi-instance tmu each instance should have an alias correctly 90Note: For multi-instance tmu each instance should have an alias correctly
47numbered in "aliases" node. 91numbered in "aliases" node.
48 92
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 2d51912a6e40..f9a13867cb70 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -222,12 +222,24 @@ config ACPI_INT3403_THERMAL
222 the Intel Thermal Daemon can use this information to allow the user 222 the Intel Thermal Daemon can use this information to allow the user
223 to select his laptop to run without turning on the fans. 223 to select his laptop to run without turning on the fans.
224 224
225config INTEL_SOC_DTS_THERMAL
226 tristate "Intel SoCs DTS thermal driver"
227 depends on X86 && IOSF_MBI
228 help
229 Enable this to register Intel SoCs (e.g. Bay Trail) platform digital
230 temperature sensor (DTS). These SoCs have two additional DTSs in
231 addition to DTSs on CPU cores. Each DTS will be registered as a
232 thermal zone. There are two trip points. One of the trip point can
233 be set by user mode programs to get notifications via Linux thermal
234 notification methods.The other trip is a critical trip point, which
235 was set by the driver based on the TJ MAX temperature.
236
225menu "Texas Instruments thermal drivers" 237menu "Texas Instruments thermal drivers"
226source "drivers/thermal/ti-soc-thermal/Kconfig" 238source "drivers/thermal/ti-soc-thermal/Kconfig"
227endmenu 239endmenu
228 240
229menu "Samsung thermal drivers" 241menu "Samsung thermal drivers"
230depends on PLAT_SAMSUNG 242depends on ARCH_EXYNOS
231source "drivers/thermal/samsung/Kconfig" 243source "drivers/thermal/samsung/Kconfig"
232endmenu 244endmenu
233 245
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 54e4ec9eb5df..de0636a57a64 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -29,5 +29,6 @@ obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
29obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o 29obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o
30obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o 30obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o
31obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o 31obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o
32obj-$(CONFIG_INTEL_SOC_DTS_THERMAL) += intel_soc_dts_thermal.o
32obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal/ 33obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal/
33obj-$(CONFIG_ACPI_INT3403_THERMAL) += int3403_thermal.o 34obj-$(CONFIG_ACPI_INT3403_THERMAL) += int3403_thermal.o
diff --git a/drivers/thermal/armada_thermal.c b/drivers/thermal/armada_thermal.c
index 5e53212b984f..9d1420acb391 100644
--- a/drivers/thermal/armada_thermal.c
+++ b/drivers/thermal/armada_thermal.c
@@ -24,10 +24,7 @@
24#include <linux/of_device.h> 24#include <linux/of_device.h>
25#include <linux/thermal.h> 25#include <linux/thermal.h>
26 26
27#define THERMAL_VALID_OFFSET 9
28#define THERMAL_VALID_MASK 0x1 27#define THERMAL_VALID_MASK 0x1
29#define THERMAL_TEMP_OFFSET 10
30#define THERMAL_TEMP_MASK 0x1ff
31 28
32/* Thermal Manager Control and Status Register */ 29/* Thermal Manager Control and Status Register */
33#define PMU_TDC0_SW_RST_MASK (0x1 << 1) 30#define PMU_TDC0_SW_RST_MASK (0x1 << 1)
@@ -38,24 +35,47 @@
38#define PMU_TDC0_OTF_CAL_MASK (0x1 << 30) 35#define PMU_TDC0_OTF_CAL_MASK (0x1 << 30)
39#define PMU_TDC0_START_CAL_MASK (0x1 << 25) 36#define PMU_TDC0_START_CAL_MASK (0x1 << 25)
40 37
41struct armada_thermal_ops; 38#define A375_Z1_CAL_RESET_LSB 0x8011e214
39#define A375_Z1_CAL_RESET_MSB 0x30a88019
40#define A375_Z1_WORKAROUND_BIT BIT(9)
41
42#define A375_UNIT_CONTROL_SHIFT 27
43#define A375_UNIT_CONTROL_MASK 0x7
44#define A375_READOUT_INVERT BIT(15)
45#define A375_HW_RESETn BIT(8)
46#define A380_HW_RESET BIT(8)
47
48struct armada_thermal_data;
42 49
43/* Marvell EBU Thermal Sensor Dev Structure */ 50/* Marvell EBU Thermal Sensor Dev Structure */
44struct armada_thermal_priv { 51struct armada_thermal_priv {
45 void __iomem *sensor; 52 void __iomem *sensor;
46 void __iomem *control; 53 void __iomem *control;
47 struct armada_thermal_ops *ops; 54 struct armada_thermal_data *data;
48}; 55};
49 56
50struct armada_thermal_ops { 57struct armada_thermal_data {
51 /* Initialize the sensor */ 58 /* Initialize the sensor */
52 void (*init_sensor)(struct armada_thermal_priv *); 59 void (*init_sensor)(struct platform_device *pdev,
60 struct armada_thermal_priv *);
53 61
54 /* Test for a valid sensor value (optional) */ 62 /* Test for a valid sensor value (optional) */
55 bool (*is_valid)(struct armada_thermal_priv *); 63 bool (*is_valid)(struct armada_thermal_priv *);
64
65 /* Formula coeficients: temp = (b + m * reg) / div */
66 unsigned long coef_b;
67 unsigned long coef_m;
68 unsigned long coef_div;
69 bool inverted;
70
71 /* Register shift and mask to access the sensor temperature */
72 unsigned int temp_shift;
73 unsigned int temp_mask;
74 unsigned int is_valid_shift;
56}; 75};
57 76
58static void armadaxp_init_sensor(struct armada_thermal_priv *priv) 77static void armadaxp_init_sensor(struct platform_device *pdev,
78 struct armada_thermal_priv *priv)
59{ 79{
60 unsigned long reg; 80 unsigned long reg;
61 81
@@ -80,7 +100,8 @@ static void armadaxp_init_sensor(struct armada_thermal_priv *priv)
80 writel(reg, priv->sensor); 100 writel(reg, priv->sensor);
81} 101}
82 102
83static void armada370_init_sensor(struct armada_thermal_priv *priv) 103static void armada370_init_sensor(struct platform_device *pdev,
104 struct armada_thermal_priv *priv)
84{ 105{
85 unsigned long reg; 106 unsigned long reg;
86 107
@@ -99,11 +120,54 @@ static void armada370_init_sensor(struct armada_thermal_priv *priv)
99 mdelay(10); 120 mdelay(10);
100} 121}
101 122
123static void armada375_init_sensor(struct platform_device *pdev,
124 struct armada_thermal_priv *priv)
125{
126 unsigned long reg;
127 bool quirk_needed =
128 !!of_device_is_compatible(pdev->dev.of_node,
129 "marvell,armada375-z1-thermal");
130
131 if (quirk_needed) {
132 /* Ensure these registers have the default (reset) values */
133 writel(A375_Z1_CAL_RESET_LSB, priv->control);
134 writel(A375_Z1_CAL_RESET_MSB, priv->control + 0x4);
135 }
136
137 reg = readl(priv->control + 4);
138 reg &= ~(A375_UNIT_CONTROL_MASK << A375_UNIT_CONTROL_SHIFT);
139 reg &= ~A375_READOUT_INVERT;
140 reg &= ~A375_HW_RESETn;
141
142 if (quirk_needed)
143 reg |= A375_Z1_WORKAROUND_BIT;
144
145 writel(reg, priv->control + 4);
146 mdelay(20);
147
148 reg |= A375_HW_RESETn;
149 writel(reg, priv->control + 4);
150 mdelay(50);
151}
152
153static void armada380_init_sensor(struct platform_device *pdev,
154 struct armada_thermal_priv *priv)
155{
156 unsigned long reg = readl_relaxed(priv->control);
157
158 /* Reset hardware once */
159 if (!(reg & A380_HW_RESET)) {
160 reg |= A380_HW_RESET;
161 writel(reg, priv->control);
162 mdelay(10);
163 }
164}
165
102static bool armada_is_valid(struct armada_thermal_priv *priv) 166static bool armada_is_valid(struct armada_thermal_priv *priv)
103{ 167{
104 unsigned long reg = readl_relaxed(priv->sensor); 168 unsigned long reg = readl_relaxed(priv->sensor);
105 169
106 return (reg >> THERMAL_VALID_OFFSET) & THERMAL_VALID_MASK; 170 return (reg >> priv->data->is_valid_shift) & THERMAL_VALID_MASK;
107} 171}
108 172
109static int armada_get_temp(struct thermal_zone_device *thermal, 173static int armada_get_temp(struct thermal_zone_device *thermal,
@@ -111,17 +175,27 @@ static int armada_get_temp(struct thermal_zone_device *thermal,
111{ 175{
112 struct armada_thermal_priv *priv = thermal->devdata; 176 struct armada_thermal_priv *priv = thermal->devdata;
113 unsigned long reg; 177 unsigned long reg;
178 unsigned long m, b, div;
114 179
115 /* Valid check */ 180 /* Valid check */
116 if (priv->ops->is_valid && !priv->ops->is_valid(priv)) { 181 if (priv->data->is_valid && !priv->data->is_valid(priv)) {
117 dev_err(&thermal->device, 182 dev_err(&thermal->device,
118 "Temperature sensor reading not valid\n"); 183 "Temperature sensor reading not valid\n");
119 return -EIO; 184 return -EIO;
120 } 185 }
121 186
122 reg = readl_relaxed(priv->sensor); 187 reg = readl_relaxed(priv->sensor);
123 reg = (reg >> THERMAL_TEMP_OFFSET) & THERMAL_TEMP_MASK; 188 reg = (reg >> priv->data->temp_shift) & priv->data->temp_mask;
124 *temp = (3153000000UL - (10000000UL*reg)) / 13825; 189
190 /* Get formula coeficients */
191 b = priv->data->coef_b;
192 m = priv->data->coef_m;
193 div = priv->data->coef_div;
194
195 if (priv->data->inverted)
196 *temp = ((m * reg) - b) / div;
197 else
198 *temp = (b - (m * reg)) / div;
125 return 0; 199 return 0;
126} 200}
127 201
@@ -129,23 +203,69 @@ static struct thermal_zone_device_ops ops = {
129 .get_temp = armada_get_temp, 203 .get_temp = armada_get_temp,
130}; 204};
131 205
132static const struct armada_thermal_ops armadaxp_ops = { 206static const struct armada_thermal_data armadaxp_data = {
133 .init_sensor = armadaxp_init_sensor, 207 .init_sensor = armadaxp_init_sensor,
208 .temp_shift = 10,
209 .temp_mask = 0x1ff,
210 .coef_b = 3153000000UL,
211 .coef_m = 10000000UL,
212 .coef_div = 13825,
134}; 213};
135 214
136static const struct armada_thermal_ops armada370_ops = { 215static const struct armada_thermal_data armada370_data = {
137 .is_valid = armada_is_valid, 216 .is_valid = armada_is_valid,
138 .init_sensor = armada370_init_sensor, 217 .init_sensor = armada370_init_sensor,
218 .is_valid_shift = 9,
219 .temp_shift = 10,
220 .temp_mask = 0x1ff,
221 .coef_b = 3153000000UL,
222 .coef_m = 10000000UL,
223 .coef_div = 13825,
224};
225
226static const struct armada_thermal_data armada375_data = {
227 .is_valid = armada_is_valid,
228 .init_sensor = armada375_init_sensor,
229 .is_valid_shift = 10,
230 .temp_shift = 0,
231 .temp_mask = 0x1ff,
232 .coef_b = 3171900000UL,
233 .coef_m = 10000000UL,
234 .coef_div = 13616,
235};
236
237static const struct armada_thermal_data armada380_data = {
238 .is_valid = armada_is_valid,
239 .init_sensor = armada380_init_sensor,
240 .is_valid_shift = 10,
241 .temp_shift = 0,
242 .temp_mask = 0x3ff,
243 .coef_b = 1169498786UL,
244 .coef_m = 2000000UL,
245 .coef_div = 4289,
246 .inverted = true,
139}; 247};
140 248
141static const struct of_device_id armada_thermal_id_table[] = { 249static const struct of_device_id armada_thermal_id_table[] = {
142 { 250 {
143 .compatible = "marvell,armadaxp-thermal", 251 .compatible = "marvell,armadaxp-thermal",
144 .data = &armadaxp_ops, 252 .data = &armadaxp_data,
145 }, 253 },
146 { 254 {
147 .compatible = "marvell,armada370-thermal", 255 .compatible = "marvell,armada370-thermal",
148 .data = &armada370_ops, 256 .data = &armada370_data,
257 },
258 {
259 .compatible = "marvell,armada375-thermal",
260 .data = &armada375_data,
261 },
262 {
263 .compatible = "marvell,armada375-z1-thermal",
264 .data = &armada375_data,
265 },
266 {
267 .compatible = "marvell,armada380-thermal",
268 .data = &armada380_data,
149 }, 269 },
150 { 270 {
151 /* sentinel */ 271 /* sentinel */
@@ -178,8 +298,8 @@ static int armada_thermal_probe(struct platform_device *pdev)
178 if (IS_ERR(priv->control)) 298 if (IS_ERR(priv->control))
179 return PTR_ERR(priv->control); 299 return PTR_ERR(priv->control);
180 300
181 priv->ops = (struct armada_thermal_ops *)match->data; 301 priv->data = (struct armada_thermal_data *)match->data;
182 priv->ops->init_sensor(priv); 302 priv->data->init_sensor(pdev, priv);
183 303
184 thermal = thermal_zone_device_register("armada_thermal", 0, 0, 304 thermal = thermal_zone_device_register("armada_thermal", 0, 0,
185 priv, &ops, NULL, 0, 0); 305 priv, &ops, NULL, 0, 0);
diff --git a/drivers/thermal/int3403_thermal.c b/drivers/thermal/int3403_thermal.c
index 1301681d9a77..e93f0253f6ed 100644
--- a/drivers/thermal/int3403_thermal.c
+++ b/drivers/thermal/int3403_thermal.c
@@ -62,7 +62,13 @@ static int sys_get_trip_hyst(struct thermal_zone_device *tzone,
62 if (ACPI_FAILURE(status)) 62 if (ACPI_FAILURE(status))
63 return -EIO; 63 return -EIO;
64 64
65 *temp = DECI_KELVIN_TO_MILLI_CELSIUS(hyst, KELVIN_OFFSET); 65 /*
66 * Thermal hysteresis represents a temperature difference.
67 * Kelvin and Celsius have same degree size. So the
68 * conversion here between tenths of degree Kelvin unit
69 * and Milli-Celsius unit is just to multiply 100.
70 */
71 *temp = hyst * 100;
66 72
67 return 0; 73 return 0;
68} 74}
diff --git a/drivers/thermal/intel_powerclamp.c b/drivers/thermal/intel_powerclamp.c
index a084325f1386..95cb7fc20e17 100644
--- a/drivers/thermal/intel_powerclamp.c
+++ b/drivers/thermal/intel_powerclamp.c
@@ -681,8 +681,10 @@ static const struct x86_cpu_id intel_powerclamp_ids[] = {
681 { X86_VENDOR_INTEL, 6, 0x2d}, 681 { X86_VENDOR_INTEL, 6, 0x2d},
682 { X86_VENDOR_INTEL, 6, 0x2e}, 682 { X86_VENDOR_INTEL, 6, 0x2e},
683 { X86_VENDOR_INTEL, 6, 0x2f}, 683 { X86_VENDOR_INTEL, 6, 0x2f},
684 { X86_VENDOR_INTEL, 6, 0x37},
684 { X86_VENDOR_INTEL, 6, 0x3a}, 685 { X86_VENDOR_INTEL, 6, 0x3a},
685 { X86_VENDOR_INTEL, 6, 0x3c}, 686 { X86_VENDOR_INTEL, 6, 0x3c},
687 { X86_VENDOR_INTEL, 6, 0x3d},
686 { X86_VENDOR_INTEL, 6, 0x3e}, 688 { X86_VENDOR_INTEL, 6, 0x3e},
687 { X86_VENDOR_INTEL, 6, 0x3f}, 689 { X86_VENDOR_INTEL, 6, 0x3f},
688 { X86_VENDOR_INTEL, 6, 0x45}, 690 { X86_VENDOR_INTEL, 6, 0x45},
diff --git a/drivers/thermal/intel_soc_dts_thermal.c b/drivers/thermal/intel_soc_dts_thermal.c
new file mode 100644
index 000000000000..a6a0a18ec0aa
--- /dev/null
+++ b/drivers/thermal/intel_soc_dts_thermal.c
@@ -0,0 +1,479 @@
1/*
2 * intel_soc_dts_thermal.c
3 * Copyright (c) 2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 */
15
16#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17
18#include <linux/module.h>
19#include <linux/slab.h>
20#include <linux/interrupt.h>
21#include <linux/thermal.h>
22#include <asm/cpu_device_id.h>
23#include <asm/iosf_mbi.h>
24
25#define SOC_DTS_OFFSET_ENABLE 0xB0
26#define SOC_DTS_OFFSET_TEMP 0xB1
27
28#define SOC_DTS_OFFSET_PTPS 0xB2
29#define SOC_DTS_OFFSET_PTTS 0xB3
30#define SOC_DTS_OFFSET_PTTSS 0xB4
31#define SOC_DTS_OFFSET_PTMC 0x80
32#define SOC_DTS_TE_AUX0 0xB5
33#define SOC_DTS_TE_AUX1 0xB6
34
35#define SOC_DTS_AUX0_ENABLE_BIT BIT(0)
36#define SOC_DTS_AUX1_ENABLE_BIT BIT(1)
37#define SOC_DTS_CPU_MODULE0_ENABLE_BIT BIT(16)
38#define SOC_DTS_CPU_MODULE1_ENABLE_BIT BIT(17)
39#define SOC_DTS_TE_SCI_ENABLE BIT(9)
40#define SOC_DTS_TE_SMI_ENABLE BIT(10)
41#define SOC_DTS_TE_MSI_ENABLE BIT(11)
42#define SOC_DTS_TE_APICA_ENABLE BIT(14)
43#define SOC_DTS_PTMC_APIC_DEASSERT_BIT BIT(4)
44
45/* DTS encoding for TJ MAX temperature */
46#define SOC_DTS_TJMAX_ENCODING 0x7F
47
48/* IRQ 86 is a fixed APIC interrupt for BYT DTS Aux threshold notifications */
49#define BYT_SOC_DTS_APIC_IRQ 86
50
51/* Only 2 out of 4 is allowed for OSPM */
52#define SOC_MAX_DTS_TRIPS 2
53
54/* Mask for two trips in status bits */
55#define SOC_DTS_TRIP_MASK 0x03
56
57/* DTS0 and DTS 1 */
58#define SOC_MAX_DTS_SENSORS 2
59
60#define CRITICAL_OFFSET_FROM_TJ_MAX 5000
61
62struct soc_sensor_entry {
63 int id;
64 u32 tj_max;
65 u32 temp_mask;
66 u32 temp_shift;
67 u32 store_status;
68 struct thermal_zone_device *tzone;
69};
70
71static struct soc_sensor_entry *soc_dts[SOC_MAX_DTS_SENSORS];
72
73static int crit_offset = CRITICAL_OFFSET_FROM_TJ_MAX;
74module_param(crit_offset, int, 0644);
75MODULE_PARM_DESC(crit_offset,
76 "Critical Temperature offset from tj max in millidegree Celsius.");
77
78static DEFINE_MUTEX(aux_update_mutex);
79static spinlock_t intr_notify_lock;
80static int soc_dts_thres_irq;
81
82static int get_tj_max(u32 *tj_max)
83{
84 u32 eax, edx;
85 u32 val;
86 int err;
87
88 err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
89 if (err)
90 goto err_ret;
91 else {
92 val = (eax >> 16) & 0xff;
93 if (val)
94 *tj_max = val * 1000;
95 else {
96 err = -EINVAL;
97 goto err_ret;
98 }
99 }
100
101 return 0;
102err_ret:
103 *tj_max = 0;
104
105 return err;
106}
107
108static int sys_get_trip_temp(struct thermal_zone_device *tzd,
109 int trip, unsigned long *temp)
110{
111 int status;
112 u32 out;
113 struct soc_sensor_entry *aux_entry;
114
115 aux_entry = tzd->devdata;
116
117 if (!trip) {
118 /* Just return the critical temp */
119 *temp = aux_entry->tj_max - crit_offset;
120 return 0;
121 }
122
123 mutex_lock(&aux_update_mutex);
124 status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
125 SOC_DTS_OFFSET_PTPS, &out);
126 mutex_unlock(&aux_update_mutex);
127 if (status)
128 return status;
129
130 out = (out >> (trip * 8)) & SOC_DTS_TJMAX_ENCODING;
131
132 if (!out)
133 *temp = 0;
134 else
135 *temp = aux_entry->tj_max - out * 1000;
136
137 return 0;
138}
139
140static int update_trip_temp(struct soc_sensor_entry *aux_entry,
141 int thres_index, unsigned long temp)
142{
143 int status;
144 u32 temp_out;
145 u32 out;
146 u32 store_ptps;
147 u32 store_ptmc;
148 u32 store_te_out;
149 u32 te_out;
150
151 u32 int_enable_bit = SOC_DTS_TE_APICA_ENABLE |
152 SOC_DTS_TE_MSI_ENABLE;
153
154 temp_out = (aux_entry->tj_max - temp) / 1000;
155
156 status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
157 SOC_DTS_OFFSET_PTPS, &store_ptps);
158 if (status)
159 return status;
160
161 out = (store_ptps & ~(0xFF << (thres_index * 8)));
162 out |= (temp_out & 0xFF) << (thres_index * 8);
163 status = iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
164 SOC_DTS_OFFSET_PTPS, out);
165 if (status)
166 return status;
167 pr_debug("update_trip_temp PTPS = %x\n", out);
168 status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
169 SOC_DTS_OFFSET_PTMC, &out);
170 if (status)
171 goto err_restore_ptps;
172
173 store_ptmc = out;
174
175 status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
176 SOC_DTS_TE_AUX0 + thres_index,
177 &te_out);
178 if (status)
179 goto err_restore_ptmc;
180
181 store_te_out = te_out;
182
183 /* Enable for CPU module 0 and module 1 */
184 out |= (SOC_DTS_CPU_MODULE0_ENABLE_BIT |
185 SOC_DTS_CPU_MODULE1_ENABLE_BIT);
186 if (temp) {
187 if (thres_index)
188 out |= SOC_DTS_AUX1_ENABLE_BIT;
189 else
190 out |= SOC_DTS_AUX0_ENABLE_BIT;
191 te_out |= int_enable_bit;
192 } else {
193 if (thres_index)
194 out &= ~SOC_DTS_AUX1_ENABLE_BIT;
195 else
196 out &= ~SOC_DTS_AUX0_ENABLE_BIT;
197 te_out &= ~int_enable_bit;
198 }
199 status = iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
200 SOC_DTS_OFFSET_PTMC, out);
201 if (status)
202 goto err_restore_te_out;
203
204 status = iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
205 SOC_DTS_TE_AUX0 + thres_index,
206 te_out);
207 if (status)
208 goto err_restore_te_out;
209
210 return 0;
211
212err_restore_te_out:
213 iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
214 SOC_DTS_OFFSET_PTMC, store_te_out);
215err_restore_ptmc:
216 iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
217 SOC_DTS_OFFSET_PTMC, store_ptmc);
218err_restore_ptps:
219 iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
220 SOC_DTS_OFFSET_PTPS, store_ptps);
221 /* Nothing we can do if restore fails */
222
223 return status;
224}
225
226static int sys_set_trip_temp(struct thermal_zone_device *tzd, int trip,
227 unsigned long temp)
228{
229 struct soc_sensor_entry *aux_entry = tzd->devdata;
230 int status;
231
232 if (temp > (aux_entry->tj_max - crit_offset))
233 return -EINVAL;
234
235 mutex_lock(&aux_update_mutex);
236 status = update_trip_temp(tzd->devdata, trip, temp);
237 mutex_unlock(&aux_update_mutex);
238
239 return status;
240}
241
242static int sys_get_trip_type(struct thermal_zone_device *thermal,
243 int trip, enum thermal_trip_type *type)
244{
245 if (trip)
246 *type = THERMAL_TRIP_PASSIVE;
247 else
248 *type = THERMAL_TRIP_CRITICAL;
249
250 return 0;
251}
252
253static int sys_get_curr_temp(struct thermal_zone_device *tzd,
254 unsigned long *temp)
255{
256 int status;
257 u32 out;
258 struct soc_sensor_entry *aux_entry;
259
260 aux_entry = tzd->devdata;
261
262 status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
263 SOC_DTS_OFFSET_TEMP, &out);
264 if (status)
265 return status;
266
267 out = (out & aux_entry->temp_mask) >> aux_entry->temp_shift;
268 out -= SOC_DTS_TJMAX_ENCODING;
269 *temp = aux_entry->tj_max - out * 1000;
270
271 return 0;
272}
273
274static struct thermal_zone_device_ops tzone_ops = {
275 .get_temp = sys_get_curr_temp,
276 .get_trip_temp = sys_get_trip_temp,
277 .get_trip_type = sys_get_trip_type,
278 .set_trip_temp = sys_set_trip_temp,
279};
280
281static void free_soc_dts(struct soc_sensor_entry *aux_entry)
282{
283 if (aux_entry) {
284 iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
285 SOC_DTS_OFFSET_ENABLE, aux_entry->store_status);
286 thermal_zone_device_unregister(aux_entry->tzone);
287 kfree(aux_entry);
288 }
289}
290
291static int soc_dts_enable(int id)
292{
293 u32 out;
294 int ret;
295
296 ret = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
297 SOC_DTS_OFFSET_ENABLE, &out);
298 if (ret)
299 return ret;
300
301 if (!(out & BIT(id))) {
302 out |= BIT(id);
303 ret = iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
304 SOC_DTS_OFFSET_ENABLE, out);
305 if (ret)
306 return ret;
307 }
308
309 return ret;
310}
311
312static struct soc_sensor_entry *alloc_soc_dts(int id, u32 tj_max)
313{
314 struct soc_sensor_entry *aux_entry;
315 char name[10];
316 int err;
317
318 aux_entry = kzalloc(sizeof(*aux_entry), GFP_KERNEL);
319 if (!aux_entry) {
320 err = -ENOMEM;
321 return ERR_PTR(-ENOMEM);
322 }
323
324 /* Store status to restor on exit */
325 err = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
326 SOC_DTS_OFFSET_ENABLE,
327 &aux_entry->store_status);
328 if (err)
329 goto err_ret;
330
331 aux_entry->id = id;
332 aux_entry->tj_max = tj_max;
333 aux_entry->temp_mask = 0x00FF << (id * 8);
334 aux_entry->temp_shift = id * 8;
335 snprintf(name, sizeof(name), "soc_dts%d", id);
336 aux_entry->tzone = thermal_zone_device_register(name,
337 SOC_MAX_DTS_TRIPS,
338 0x02,
339 aux_entry, &tzone_ops, NULL, 0, 0);
340 if (IS_ERR(aux_entry->tzone)) {
341 err = PTR_ERR(aux_entry->tzone);
342 goto err_ret;
343 }
344
345 err = soc_dts_enable(id);
346 if (err)
347 goto err_aux_status;
348
349 return aux_entry;
350
351err_aux_status:
352 thermal_zone_device_unregister(aux_entry->tzone);
353err_ret:
354 kfree(aux_entry);
355 return ERR_PTR(err);
356}
357
358static void proc_thermal_interrupt(void)
359{
360 u32 sticky_out;
361 int status;
362 u32 ptmc_out;
363
364 /* Clear APIC interrupt */
365 status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
366 SOC_DTS_OFFSET_PTMC, &ptmc_out);
367
368 ptmc_out |= SOC_DTS_PTMC_APIC_DEASSERT_BIT;
369 status = iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
370 SOC_DTS_OFFSET_PTMC, ptmc_out);
371
372 /* Read status here */
373 status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
374 SOC_DTS_OFFSET_PTTSS, &sticky_out);
375 pr_debug("status %d PTTSS %x\n", status, sticky_out);
376 if (sticky_out & SOC_DTS_TRIP_MASK) {
377 int i;
378 /* reset sticky bit */
379 status = iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
380 SOC_DTS_OFFSET_PTTSS, sticky_out);
381 for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i) {
382 pr_debug("TZD update for zone %d\n", i);
383 thermal_zone_device_update(soc_dts[i]->tzone);
384 }
385 }
386
387}
388
389static irqreturn_t soc_irq_thread_fn(int irq, void *dev_data)
390{
391 unsigned long flags;
392
393 spin_lock_irqsave(&intr_notify_lock, flags);
394 proc_thermal_interrupt();
395 spin_unlock_irqrestore(&intr_notify_lock, flags);
396 pr_debug("proc_thermal_interrupt\n");
397
398 return IRQ_HANDLED;
399}
400
401static const struct x86_cpu_id soc_thermal_ids[] = {
402 { X86_VENDOR_INTEL, X86_FAMILY_ANY, 0x37, 0, BYT_SOC_DTS_APIC_IRQ},
403 {}
404};
405MODULE_DEVICE_TABLE(x86cpu, soc_thermal_ids);
406
407static int __init intel_soc_thermal_init(void)
408{
409 u32 tj_max;
410 int err = 0;
411 int i;
412 const struct x86_cpu_id *match_cpu;
413
414 match_cpu = x86_match_cpu(soc_thermal_ids);
415 if (!match_cpu)
416 return -ENODEV;
417
418 if (get_tj_max(&tj_max))
419 return -EINVAL;
420
421 for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i) {
422 soc_dts[i] = alloc_soc_dts(i, tj_max);
423 if (IS_ERR(soc_dts[i])) {
424 err = PTR_ERR(soc_dts[i]);
425 goto err_free;
426 }
427 }
428
429 spin_lock_init(&intr_notify_lock);
430
431 soc_dts_thres_irq = (int)match_cpu->driver_data;
432
433 err = request_threaded_irq(soc_dts_thres_irq, NULL,
434 soc_irq_thread_fn,
435 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
436 "soc_dts", soc_dts);
437 if (err) {
438 pr_err("request_threaded_irq ret %d\n", err);
439 goto err_free;
440 }
441
442 for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i) {
443 err = update_trip_temp(soc_dts[i], 0, tj_max - crit_offset);
444 if (err)
445 goto err_trip_temp;
446 }
447
448 return 0;
449
450err_trip_temp:
451 i = SOC_MAX_DTS_SENSORS;
452 free_irq(soc_dts_thres_irq, soc_dts);
453err_free:
454 while (--i >= 0)
455 free_soc_dts(soc_dts[i]);
456
457 return err;
458}
459
460static void __exit intel_soc_thermal_exit(void)
461{
462 int i;
463
464 for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i)
465 update_trip_temp(soc_dts[i], 0, 0);
466
467 free_irq(soc_dts_thres_irq, soc_dts);
468
469 for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i)
470 free_soc_dts(soc_dts[i]);
471
472}
473
474module_init(intel_soc_thermal_init)
475module_exit(intel_soc_thermal_exit)
476
477MODULE_DESCRIPTION("Intel SoC DTS Thermal Driver");
478MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
479MODULE_LICENSE("GPL v2");
diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c
index 5a37940b02c9..8803e693fe68 100644
--- a/drivers/thermal/rcar_thermal.c
+++ b/drivers/thermal/rcar_thermal.c
@@ -374,10 +374,8 @@ static int rcar_thermal_probe(struct platform_device *pdev)
374 int idle = IDLE_INTERVAL; 374 int idle = IDLE_INTERVAL;
375 375
376 common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL); 376 common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
377 if (!common) { 377 if (!common)
378 dev_err(dev, "Could not allocate common\n");
379 return -ENOMEM; 378 return -ENOMEM;
380 }
381 379
382 INIT_LIST_HEAD(&common->head); 380 INIT_LIST_HEAD(&common->head);
383 spin_lock_init(&common->lock); 381 spin_lock_init(&common->lock);
@@ -423,7 +421,6 @@ static int rcar_thermal_probe(struct platform_device *pdev)
423 421
424 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 422 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
425 if (!priv) { 423 if (!priv) {
426 dev_err(dev, "Could not allocate priv\n");
427 ret = -ENOMEM; 424 ret = -ENOMEM;
428 goto error_unregister; 425 goto error_unregister;
429 } 426 }
@@ -470,7 +467,7 @@ error_unregister:
470 rcar_thermal_irq_disable(priv); 467 rcar_thermal_irq_disable(priv);
471 } 468 }
472 469
473 pm_runtime_put_sync(dev); 470 pm_runtime_put(dev);
474 pm_runtime_disable(dev); 471 pm_runtime_disable(dev);
475 472
476 return ret; 473 return ret;
@@ -488,7 +485,7 @@ static int rcar_thermal_remove(struct platform_device *pdev)
488 rcar_thermal_irq_disable(priv); 485 rcar_thermal_irq_disable(priv);
489 } 486 }
490 487
491 pm_runtime_put_sync(dev); 488 pm_runtime_put(dev);
492 pm_runtime_disable(dev); 489 pm_runtime_disable(dev);
493 490
494 return 0; 491 return 0;
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index 0d96a510389f..d7ca9f49c9cb 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -41,12 +41,13 @@
41 * @id: identifier of the one instance of the TMU controller. 41 * @id: identifier of the one instance of the TMU controller.
42 * @pdata: pointer to the tmu platform/configuration data 42 * @pdata: pointer to the tmu platform/configuration data
43 * @base: base address of the single instance of the TMU controller. 43 * @base: base address of the single instance of the TMU controller.
44 * @base_common: base address of the common registers of the TMU controller. 44 * @base_second: base address of the common registers of the TMU controller.
45 * @irq: irq number of the TMU controller. 45 * @irq: irq number of the TMU controller.
46 * @soc: id of the SOC type. 46 * @soc: id of the SOC type.
47 * @irq_work: pointer to the irq work structure. 47 * @irq_work: pointer to the irq work structure.
48 * @lock: lock to implement synchronization. 48 * @lock: lock to implement synchronization.
49 * @clk: pointer to the clock structure. 49 * @clk: pointer to the clock structure.
50 * @clk_sec: pointer to the clock structure for accessing the base_second.
50 * @temp_error1: fused value of the first point trim. 51 * @temp_error1: fused value of the first point trim.
51 * @temp_error2: fused value of the second point trim. 52 * @temp_error2: fused value of the second point trim.
52 * @regulator: pointer to the TMU regulator structure. 53 * @regulator: pointer to the TMU regulator structure.
@@ -56,12 +57,12 @@ struct exynos_tmu_data {
56 int id; 57 int id;
57 struct exynos_tmu_platform_data *pdata; 58 struct exynos_tmu_platform_data *pdata;
58 void __iomem *base; 59 void __iomem *base;
59 void __iomem *base_common; 60 void __iomem *base_second;
60 int irq; 61 int irq;
61 enum soc_type soc; 62 enum soc_type soc;
62 struct work_struct irq_work; 63 struct work_struct irq_work;
63 struct mutex lock; 64 struct mutex lock;
64 struct clk *clk; 65 struct clk *clk, *clk_sec;
65 u8 temp_error1, temp_error2; 66 u8 temp_error1, temp_error2;
66 struct regulator *regulator; 67 struct regulator *regulator;
67 struct thermal_sensor_conf *reg_conf; 68 struct thermal_sensor_conf *reg_conf;
@@ -152,6 +153,8 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
152 153
153 mutex_lock(&data->lock); 154 mutex_lock(&data->lock);
154 clk_enable(data->clk); 155 clk_enable(data->clk);
156 if (!IS_ERR(data->clk_sec))
157 clk_enable(data->clk_sec);
155 158
156 if (TMU_SUPPORTS(pdata, READY_STATUS)) { 159 if (TMU_SUPPORTS(pdata, READY_STATUS)) {
157 status = readb(data->base + reg->tmu_status); 160 status = readb(data->base + reg->tmu_status);
@@ -186,7 +189,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
186 EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data); 189 EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
187 } 190 }
188 } else { 191 } else {
189 trim_info = readl(data->base + reg->triminfo_data); 192 /* On exynos5420 the triminfo register is in the shared space */
193 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
194 trim_info = readl(data->base_second +
195 reg->triminfo_data);
196 else
197 trim_info = readl(data->base + reg->triminfo_data);
190 } 198 }
191 data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK; 199 data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
192 data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) & 200 data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
@@ -225,6 +233,8 @@ skip_calib_data:
225 trigger_levs++; 233 trigger_levs++;
226 } 234 }
227 235
236 rising_threshold = readl(data->base + reg->threshold_th0);
237
228 if (data->soc == SOC_ARCH_EXYNOS4210) { 238 if (data->soc == SOC_ARCH_EXYNOS4210) {
229 /* Write temperature code for threshold */ 239 /* Write temperature code for threshold */
230 threshold_code = temp_to_code(data, pdata->threshold); 240 threshold_code = temp_to_code(data, pdata->threshold);
@@ -238,7 +248,7 @@ skip_calib_data:
238 writeb(pdata->trigger_levels[i], data->base + 248 writeb(pdata->trigger_levels[i], data->base +
239 reg->threshold_th0 + i * sizeof(reg->threshold_th0)); 249 reg->threshold_th0 + i * sizeof(reg->threshold_th0));
240 250
241 writel(reg->inten_rise_mask, data->base + reg->tmu_intclear); 251 writel(reg->intclr_rise_mask, data->base + reg->tmu_intclear);
242 } else { 252 } else {
243 /* Write temperature code for rising and falling threshold */ 253 /* Write temperature code for rising and falling threshold */
244 for (i = 0; 254 for (i = 0;
@@ -249,6 +259,7 @@ skip_calib_data:
249 ret = threshold_code; 259 ret = threshold_code;
250 goto out; 260 goto out;
251 } 261 }
262 rising_threshold &= ~(0xff << 8 * i);
252 rising_threshold |= threshold_code << 8 * i; 263 rising_threshold |= threshold_code << 8 * i;
253 if (pdata->threshold_falling) { 264 if (pdata->threshold_falling) {
254 threshold_code = temp_to_code(data, 265 threshold_code = temp_to_code(data,
@@ -265,8 +276,8 @@ skip_calib_data:
265 writel(falling_threshold, 276 writel(falling_threshold,
266 data->base + reg->threshold_th1); 277 data->base + reg->threshold_th1);
267 278
268 writel((reg->inten_rise_mask << reg->inten_rise_shift) | 279 writel((reg->intclr_rise_mask << reg->intclr_rise_shift) |
269 (reg->inten_fall_mask << reg->inten_fall_shift), 280 (reg->intclr_fall_mask << reg->intclr_fall_shift),
270 data->base + reg->tmu_intclear); 281 data->base + reg->tmu_intclear);
271 282
272 /* if last threshold limit is also present */ 283 /* if last threshold limit is also present */
@@ -281,6 +292,7 @@ skip_calib_data:
281 } 292 }
282 if (i == EXYNOS_MAX_TRIGGER_PER_REG - 1) { 293 if (i == EXYNOS_MAX_TRIGGER_PER_REG - 1) {
283 /* 1-4 level to be assigned in th0 reg */ 294 /* 1-4 level to be assigned in th0 reg */
295 rising_threshold &= ~(0xff << 8 * i);
284 rising_threshold |= threshold_code << 8 * i; 296 rising_threshold |= threshold_code << 8 * i;
285 writel(rising_threshold, 297 writel(rising_threshold,
286 data->base + reg->threshold_th0); 298 data->base + reg->threshold_th0);
@@ -298,10 +310,12 @@ skip_calib_data:
298 } 310 }
299 /*Clear the PMIN in the common TMU register*/ 311 /*Clear the PMIN in the common TMU register*/
300 if (reg->tmu_pmin && !data->id) 312 if (reg->tmu_pmin && !data->id)
301 writel(0, data->base_common + reg->tmu_pmin); 313 writel(0, data->base_second + reg->tmu_pmin);
302out: 314out:
303 clk_disable(data->clk); 315 clk_disable(data->clk);
304 mutex_unlock(&data->lock); 316 mutex_unlock(&data->lock);
317 if (!IS_ERR(data->clk_sec))
318 clk_disable(data->clk_sec);
305 319
306 return ret; 320 return ret;
307} 321}
@@ -453,12 +467,16 @@ static void exynos_tmu_work(struct work_struct *work)
453 const struct exynos_tmu_registers *reg = pdata->registers; 467 const struct exynos_tmu_registers *reg = pdata->registers;
454 unsigned int val_irq, val_type; 468 unsigned int val_irq, val_type;
455 469
470 if (!IS_ERR(data->clk_sec))
471 clk_enable(data->clk_sec);
456 /* Find which sensor generated this interrupt */ 472 /* Find which sensor generated this interrupt */
457 if (reg->tmu_irqstatus) { 473 if (reg->tmu_irqstatus) {
458 val_type = readl(data->base_common + reg->tmu_irqstatus); 474 val_type = readl(data->base_second + reg->tmu_irqstatus);
459 if (!((val_type >> data->id) & 0x1)) 475 if (!((val_type >> data->id) & 0x1))
460 goto out; 476 goto out;
461 } 477 }
478 if (!IS_ERR(data->clk_sec))
479 clk_disable(data->clk_sec);
462 480
463 exynos_report_trigger(data->reg_conf); 481 exynos_report_trigger(data->reg_conf);
464 mutex_lock(&data->lock); 482 mutex_lock(&data->lock);
@@ -499,6 +517,18 @@ static const struct of_device_id exynos_tmu_match[] = {
499 .data = (void *)EXYNOS5250_TMU_DRV_DATA, 517 .data = (void *)EXYNOS5250_TMU_DRV_DATA,
500 }, 518 },
501 { 519 {
520 .compatible = "samsung,exynos5260-tmu",
521 .data = (void *)EXYNOS5260_TMU_DRV_DATA,
522 },
523 {
524 .compatible = "samsung,exynos5420-tmu",
525 .data = (void *)EXYNOS5420_TMU_DRV_DATA,
526 },
527 {
528 .compatible = "samsung,exynos5420-tmu-ext-triminfo",
529 .data = (void *)EXYNOS5420_TMU_DRV_DATA,
530 },
531 {
502 .compatible = "samsung,exynos5440-tmu", 532 .compatible = "samsung,exynos5440-tmu",
503 .data = (void *)EXYNOS5440_TMU_DRV_DATA, 533 .data = (void *)EXYNOS5440_TMU_DRV_DATA,
504 }, 534 },
@@ -580,7 +610,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
580 * Check if the TMU shares some registers and then try to map the 610 * Check if the TMU shares some registers and then try to map the
581 * memory of common registers. 611 * memory of common registers.
582 */ 612 */
583 if (!TMU_SUPPORTS(pdata, SHARED_MEMORY)) 613 if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
584 return 0; 614 return 0;
585 615
586 if (of_address_to_resource(pdev->dev.of_node, 1, &res)) { 616 if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
@@ -588,9 +618,9 @@ static int exynos_map_dt_data(struct platform_device *pdev)
588 return -ENODEV; 618 return -ENODEV;
589 } 619 }
590 620
591 data->base_common = devm_ioremap(&pdev->dev, res.start, 621 data->base_second = devm_ioremap(&pdev->dev, res.start,
592 resource_size(&res)); 622 resource_size(&res));
593 if (!data->base_common) { 623 if (!data->base_second) {
594 dev_err(&pdev->dev, "Failed to ioremap memory\n"); 624 dev_err(&pdev->dev, "Failed to ioremap memory\n");
595 return -ENOMEM; 625 return -ENOMEM;
596 } 626 }
@@ -607,10 +637,8 @@ static int exynos_tmu_probe(struct platform_device *pdev)
607 637
608 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data), 638 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
609 GFP_KERNEL); 639 GFP_KERNEL);
610 if (!data) { 640 if (!data)
611 dev_err(&pdev->dev, "Failed to allocate driver structure\n");
612 return -ENOMEM; 641 return -ENOMEM;
613 }
614 642
615 platform_set_drvdata(pdev, data); 643 platform_set_drvdata(pdev, data);
616 mutex_init(&data->lock); 644 mutex_init(&data->lock);
@@ -629,13 +657,31 @@ static int exynos_tmu_probe(struct platform_device *pdev)
629 return PTR_ERR(data->clk); 657 return PTR_ERR(data->clk);
630 } 658 }
631 659
660 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
661 if (IS_ERR(data->clk_sec)) {
662 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
663 dev_err(&pdev->dev, "Failed to get triminfo clock\n");
664 return PTR_ERR(data->clk_sec);
665 }
666 } else {
667 ret = clk_prepare(data->clk_sec);
668 if (ret) {
669 dev_err(&pdev->dev, "Failed to get clock\n");
670 return ret;
671 }
672 }
673
632 ret = clk_prepare(data->clk); 674 ret = clk_prepare(data->clk);
633 if (ret) 675 if (ret) {
634 return ret; 676 dev_err(&pdev->dev, "Failed to get clock\n");
677 goto err_clk_sec;
678 }
635 679
636 if (pdata->type == SOC_ARCH_EXYNOS4210 || 680 if (pdata->type == SOC_ARCH_EXYNOS4210 ||
637 pdata->type == SOC_ARCH_EXYNOS4412 || 681 pdata->type == SOC_ARCH_EXYNOS4412 ||
638 pdata->type == SOC_ARCH_EXYNOS5250 || 682 pdata->type == SOC_ARCH_EXYNOS5250 ||
683 pdata->type == SOC_ARCH_EXYNOS5260 ||
684 pdata->type == SOC_ARCH_EXYNOS5420_TRIMINFO ||
639 pdata->type == SOC_ARCH_EXYNOS5440) 685 pdata->type == SOC_ARCH_EXYNOS5440)
640 data->soc = pdata->type; 686 data->soc = pdata->type;
641 else { 687 else {
@@ -656,7 +702,6 @@ static int exynos_tmu_probe(struct platform_device *pdev)
656 sensor_conf = devm_kzalloc(&pdev->dev, 702 sensor_conf = devm_kzalloc(&pdev->dev,
657 sizeof(struct thermal_sensor_conf), GFP_KERNEL); 703 sizeof(struct thermal_sensor_conf), GFP_KERNEL);
658 if (!sensor_conf) { 704 if (!sensor_conf) {
659 dev_err(&pdev->dev, "Failed to allocate registration struct\n");
660 ret = -ENOMEM; 705 ret = -ENOMEM;
661 goto err_clk; 706 goto err_clk;
662 } 707 }
@@ -704,6 +749,9 @@ static int exynos_tmu_probe(struct platform_device *pdev)
704 return 0; 749 return 0;
705err_clk: 750err_clk:
706 clk_unprepare(data->clk); 751 clk_unprepare(data->clk);
752err_clk_sec:
753 if (!IS_ERR(data->clk_sec))
754 clk_unprepare(data->clk_sec);
707 return ret; 755 return ret;
708} 756}
709 757
@@ -716,6 +764,8 @@ static int exynos_tmu_remove(struct platform_device *pdev)
716 exynos_unregister_thermal(data->reg_conf); 764 exynos_unregister_thermal(data->reg_conf);
717 765
718 clk_unprepare(data->clk); 766 clk_unprepare(data->clk);
767 if (!IS_ERR(data->clk_sec))
768 clk_unprepare(data->clk_sec);
719 769
720 if (!IS_ERR(data->regulator)) 770 if (!IS_ERR(data->regulator))
721 regulator_disable(data->regulator); 771 regulator_disable(data->regulator);
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 3fb65547e64c..edd08cf76729 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -43,6 +43,8 @@ enum soc_type {
43 SOC_ARCH_EXYNOS4210 = 1, 43 SOC_ARCH_EXYNOS4210 = 1,
44 SOC_ARCH_EXYNOS4412, 44 SOC_ARCH_EXYNOS4412,
45 SOC_ARCH_EXYNOS5250, 45 SOC_ARCH_EXYNOS5250,
46 SOC_ARCH_EXYNOS5260,
47 SOC_ARCH_EXYNOS5420_TRIMINFO,
46 SOC_ARCH_EXYNOS5440, 48 SOC_ARCH_EXYNOS5440,
47}; 49};
48 50
@@ -60,7 +62,7 @@ enum soc_type {
60 * state(active/idle) can be checked. 62 * state(active/idle) can be checked.
61 * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation 63 * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
62 * sample time. 64 * sample time.
63 * TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU 65 * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
64 * sensors shares some common registers. 66 * sensors shares some common registers.
65 * TMU_SUPPORT - macro to compare the above features with the supplied. 67 * TMU_SUPPORT - macro to compare the above features with the supplied.
66 */ 68 */
@@ -70,7 +72,7 @@ enum soc_type {
70#define TMU_SUPPORT_FALLING_TRIP BIT(3) 72#define TMU_SUPPORT_FALLING_TRIP BIT(3)
71#define TMU_SUPPORT_READY_STATUS BIT(4) 73#define TMU_SUPPORT_READY_STATUS BIT(4)
72#define TMU_SUPPORT_EMUL_TIME BIT(5) 74#define TMU_SUPPORT_EMUL_TIME BIT(5)
73#define TMU_SUPPORT_SHARED_MEMORY BIT(6) 75#define TMU_SUPPORT_ADDRESS_MULTIPLE BIT(6)
74 76
75#define TMU_SUPPORTS(a, b) (a->features & TMU_SUPPORT_ ## b) 77#define TMU_SUPPORTS(a, b) (a->features & TMU_SUPPORT_ ## b)
76 78
@@ -122,10 +124,6 @@ enum soc_type {
122 * @threshold_th3_l0_shift: shift bits of level0 threshold temperature. 124 * @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
123 * @tmu_inten: register containing the different threshold interrupt 125 * @tmu_inten: register containing the different threshold interrupt
124 enable bits. 126 enable bits.
125 * @inten_rise_shift: shift bits of all rising interrupt bits.
126 * @inten_rise_mask: mask bits of all rising interrupt bits.
127 * @inten_fall_shift: shift bits of all rising interrupt bits.
128 * @inten_fall_mask: mask bits of all rising interrupt bits.
129 * @inten_rise0_shift: shift bits of rising 0 interrupt bits. 127 * @inten_rise0_shift: shift bits of rising 0 interrupt bits.
130 * @inten_rise1_shift: shift bits of rising 1 interrupt bits. 128 * @inten_rise1_shift: shift bits of rising 1 interrupt bits.
131 * @inten_rise2_shift: shift bits of rising 2 interrupt bits. 129 * @inten_rise2_shift: shift bits of rising 2 interrupt bits.
@@ -136,6 +134,10 @@ enum soc_type {
136 * @inten_fall3_shift: shift bits of falling 3 interrupt bits. 134 * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
137 * @tmu_intstat: Register containing the interrupt status values. 135 * @tmu_intstat: Register containing the interrupt status values.
138 * @tmu_intclear: Register for clearing the raised interrupt status. 136 * @tmu_intclear: Register for clearing the raised interrupt status.
137 * @intclr_fall_shift: shift bits for interrupt clear fall 0
138 * @intclr_rise_shift: shift bits of all rising interrupt bits.
139 * @intclr_rise_mask: mask bits of all rising interrupt bits.
140 * @intclr_fall_mask: mask bits of all rising interrupt bits.
139 * @emul_con: TMU emulation controller register. 141 * @emul_con: TMU emulation controller register.
140 * @emul_temp_shift: shift bits of emulation temperature. 142 * @emul_temp_shift: shift bits of emulation temperature.
141 * @emul_time_shift: shift bits of emulation time. 143 * @emul_time_shift: shift bits of emulation time.
@@ -149,6 +151,7 @@ struct exynos_tmu_registers {
149 u32 triminfo_85_shift; 151 u32 triminfo_85_shift;
150 152
151 u32 triminfo_ctrl; 153 u32 triminfo_ctrl;
154 u32 triminfo_ctrl1;
152 u32 triminfo_reload_shift; 155 u32 triminfo_reload_shift;
153 156
154 u32 tmu_ctrl; 157 u32 tmu_ctrl;
@@ -191,10 +194,6 @@ struct exynos_tmu_registers {
191 u32 threshold_th3_l0_shift; 194 u32 threshold_th3_l0_shift;
192 195
193 u32 tmu_inten; 196 u32 tmu_inten;
194 u32 inten_rise_shift;
195 u32 inten_rise_mask;
196 u32 inten_fall_shift;
197 u32 inten_fall_mask;
198 u32 inten_rise0_shift; 197 u32 inten_rise0_shift;
199 u32 inten_rise1_shift; 198 u32 inten_rise1_shift;
200 u32 inten_rise2_shift; 199 u32 inten_rise2_shift;
@@ -207,6 +206,10 @@ struct exynos_tmu_registers {
207 u32 tmu_intstat; 206 u32 tmu_intstat;
208 207
209 u32 tmu_intclear; 208 u32 tmu_intclear;
209 u32 intclr_fall_shift;
210 u32 intclr_rise_shift;
211 u32 intclr_fall_mask;
212 u32 intclr_rise_mask;
210 213
211 u32 emul_con; 214 u32 emul_con;
212 u32 emul_temp_shift; 215 u32 emul_temp_shift;
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 476b768c633e..c1d81dcd7819 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -40,13 +40,13 @@ static const struct exynos_tmu_registers exynos4210_tmu_registers = {
40 .threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP, 40 .threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
41 .threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0, 41 .threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
42 .tmu_inten = EXYNOS_TMU_REG_INTEN, 42 .tmu_inten = EXYNOS_TMU_REG_INTEN,
43 .inten_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
44 .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT, 43 .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
45 .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT, 44 .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
46 .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT, 45 .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
47 .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT, 46 .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
48 .tmu_intstat = EXYNOS_TMU_REG_INTSTAT, 47 .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
49 .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR, 48 .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
49 .intclr_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
50}; 50};
51 51
52struct exynos_tmu_init_data const exynos4210_default_tmu_data = { 52struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
@@ -112,10 +112,6 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
112 .threshold_th0 = EXYNOS_THD_TEMP_RISE, 112 .threshold_th0 = EXYNOS_THD_TEMP_RISE,
113 .threshold_th1 = EXYNOS_THD_TEMP_FALL, 113 .threshold_th1 = EXYNOS_THD_TEMP_FALL,
114 .tmu_inten = EXYNOS_TMU_REG_INTEN, 114 .tmu_inten = EXYNOS_TMU_REG_INTEN,
115 .inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
116 .inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
117 .inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
118 .inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
119 .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT, 115 .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
120 .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT, 116 .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
121 .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT, 117 .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
@@ -123,6 +119,10 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
123 .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT, 119 .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
124 .tmu_intstat = EXYNOS_TMU_REG_INTSTAT, 120 .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
125 .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR, 121 .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
122 .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
123 .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
124 .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
125 .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
126 .emul_con = EXYNOS_EMUL_CON, 126 .emul_con = EXYNOS_EMUL_CON,
127 .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT, 127 .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
128 .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT, 128 .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
@@ -194,6 +194,197 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
194}; 194};
195#endif 195#endif
196 196
197#if defined(CONFIG_SOC_EXYNOS5260)
198static const struct exynos_tmu_registers exynos5260_tmu_registers = {
199 .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
200 .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
201 .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
202 .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
203 .tmu_ctrl = EXYNOS_TMU_REG_CONTROL1,
204 .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
205 .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
206 .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
207 .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
208 .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
209 .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
210 .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
211 .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
212 .tmu_status = EXYNOS_TMU_REG_STATUS,
213 .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
214 .threshold_th0 = EXYNOS_THD_TEMP_RISE,
215 .threshold_th1 = EXYNOS_THD_TEMP_FALL,
216 .tmu_inten = EXYNOS5260_TMU_REG_INTEN,
217 .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
218 .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
219 .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
220 .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
221 .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
222 .tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT,
223 .tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR,
224 .intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
225 .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
226 .intclr_rise_mask = EXYNOS5260_TMU_RISE_INT_MASK,
227 .intclr_fall_mask = EXYNOS5260_TMU_FALL_INT_MASK,
228 .emul_con = EXYNOS5260_EMUL_CON,
229 .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
230 .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
231 .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
232};
233
234#define __EXYNOS5260_TMU_DATA \
235 .threshold_falling = 10, \
236 .trigger_levels[0] = 85, \
237 .trigger_levels[1] = 103, \
238 .trigger_levels[2] = 110, \
239 .trigger_levels[3] = 120, \
240 .trigger_enable[0] = true, \
241 .trigger_enable[1] = true, \
242 .trigger_enable[2] = true, \
243 .trigger_enable[3] = false, \
244 .trigger_type[0] = THROTTLE_ACTIVE, \
245 .trigger_type[1] = THROTTLE_ACTIVE, \
246 .trigger_type[2] = SW_TRIP, \
247 .trigger_type[3] = HW_TRIP, \
248 .max_trigger_level = 4, \
249 .gain = 8, \
250 .reference_voltage = 16, \
251 .noise_cancel_mode = 4, \
252 .cal_type = TYPE_ONE_POINT_TRIMMING, \
253 .efuse_value = 55, \
254 .min_efuse_value = 40, \
255 .max_efuse_value = 100, \
256 .first_point_trim = 25, \
257 .second_point_trim = 85, \
258 .default_temp_offset = 50, \
259 .freq_tab[0] = { \
260 .freq_clip_max = 800 * 1000, \
261 .temp_level = 85, \
262 }, \
263 .freq_tab[1] = { \
264 .freq_clip_max = 200 * 1000, \
265 .temp_level = 103, \
266 }, \
267 .freq_tab_count = 2, \
268 .registers = &exynos5260_tmu_registers, \
269
270#define EXYNOS5260_TMU_DATA \
271 __EXYNOS5260_TMU_DATA \
272 .type = SOC_ARCH_EXYNOS5260, \
273 .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
274 TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
275 TMU_SUPPORT_EMUL_TIME)
276
277struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
278 .tmu_data = {
279 { EXYNOS5260_TMU_DATA },
280 { EXYNOS5260_TMU_DATA },
281 { EXYNOS5260_TMU_DATA },
282 { EXYNOS5260_TMU_DATA },
283 { EXYNOS5260_TMU_DATA },
284 },
285 .tmu_count = 5,
286};
287#endif
288
289#if defined(CONFIG_SOC_EXYNOS5420)
290static const struct exynos_tmu_registers exynos5420_tmu_registers = {
291 .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
292 .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
293 .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
294 .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
295 .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
296 .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
297 .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
298 .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
299 .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
300 .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
301 .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
302 .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
303 .tmu_status = EXYNOS_TMU_REG_STATUS,
304 .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
305 .threshold_th0 = EXYNOS_THD_TEMP_RISE,
306 .threshold_th1 = EXYNOS_THD_TEMP_FALL,
307 .tmu_inten = EXYNOS_TMU_REG_INTEN,
308 .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
309 .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
310 .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
311 /* INTEN_RISE3 Not availble in exynos5420 */
312 .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
313 .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
314 .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
315 .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
316 .intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
317 .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
318 .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
319 .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
320 .emul_con = EXYNOS_EMUL_CON,
321 .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
322 .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
323 .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
324};
325
326#define __EXYNOS5420_TMU_DATA \
327 .threshold_falling = 10, \
328 .trigger_levels[0] = 85, \
329 .trigger_levels[1] = 103, \
330 .trigger_levels[2] = 110, \
331 .trigger_levels[3] = 120, \
332 .trigger_enable[0] = true, \
333 .trigger_enable[1] = true, \
334 .trigger_enable[2] = true, \
335 .trigger_enable[3] = false, \
336 .trigger_type[0] = THROTTLE_ACTIVE, \
337 .trigger_type[1] = THROTTLE_ACTIVE, \
338 .trigger_type[2] = SW_TRIP, \
339 .trigger_type[3] = HW_TRIP, \
340 .max_trigger_level = 4, \
341 .gain = 8, \
342 .reference_voltage = 16, \
343 .noise_cancel_mode = 4, \
344 .cal_type = TYPE_ONE_POINT_TRIMMING, \
345 .efuse_value = 55, \
346 .min_efuse_value = 40, \
347 .max_efuse_value = 100, \
348 .first_point_trim = 25, \
349 .second_point_trim = 85, \
350 .default_temp_offset = 50, \
351 .freq_tab[0] = { \
352 .freq_clip_max = 800 * 1000, \
353 .temp_level = 85, \
354 }, \
355 .freq_tab[1] = { \
356 .freq_clip_max = 200 * 1000, \
357 .temp_level = 103, \
358 }, \
359 .freq_tab_count = 2, \
360 .registers = &exynos5420_tmu_registers, \
361
362#define EXYNOS5420_TMU_DATA \
363 __EXYNOS5420_TMU_DATA \
364 .type = SOC_ARCH_EXYNOS5250, \
365 .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
366 TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
367 TMU_SUPPORT_EMUL_TIME)
368
369#define EXYNOS5420_TMU_DATA_SHARED \
370 __EXYNOS5420_TMU_DATA \
371 .type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
372 .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
373 TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
374 TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
375
376struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
377 .tmu_data = {
378 { EXYNOS5420_TMU_DATA },
379 { EXYNOS5420_TMU_DATA },
380 { EXYNOS5420_TMU_DATA_SHARED },
381 { EXYNOS5420_TMU_DATA_SHARED },
382 { EXYNOS5420_TMU_DATA_SHARED },
383 },
384 .tmu_count = 5,
385};
386#endif
387
197#if defined(CONFIG_SOC_EXYNOS5440) 388#if defined(CONFIG_SOC_EXYNOS5440)
198static const struct exynos_tmu_registers exynos5440_tmu_registers = { 389static const struct exynos_tmu_registers exynos5440_tmu_registers = {
199 .triminfo_data = EXYNOS5440_TMU_S0_7_TRIM, 390 .triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
@@ -217,10 +408,6 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
217 .threshold_th2 = EXYNOS5440_TMU_S0_7_TH2, 408 .threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
218 .threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT, 409 .threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
219 .tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN, 410 .tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
220 .inten_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
221 .inten_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
222 .inten_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
223 .inten_fall_shift = EXYNOS5440_TMU_FALL_INT_SHIFT,
224 .inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT, 411 .inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
225 .inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT, 412 .inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
226 .inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT, 413 .inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
@@ -228,6 +415,10 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
228 .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT, 415 .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
229 .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ, 416 .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
230 .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ, 417 .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
418 .intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
419 .intclr_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
420 .intclr_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
421 .intclr_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
231 .tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS, 422 .tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
232 .emul_con = EXYNOS5440_TMU_S0_7_DEBUG, 423 .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
233 .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT, 424 .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
@@ -255,7 +446,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
255 .type = SOC_ARCH_EXYNOS5440, \ 446 .type = SOC_ARCH_EXYNOS5440, \
256 .registers = &exynos5440_tmu_registers, \ 447 .registers = &exynos5440_tmu_registers, \
257 .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \ 448 .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
258 TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY), 449 TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
259 450
260struct exynos_tmu_init_data const exynos5440_default_tmu_data = { 451struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
261 .tmu_data = { 452 .tmu_data = {
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index a1ea19d9e0a6..d268981b65e5 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -69,9 +69,11 @@
69#define EXYNOS_TMU_RISE_INT_MASK 0x111 69#define EXYNOS_TMU_RISE_INT_MASK 0x111
70#define EXYNOS_TMU_RISE_INT_SHIFT 0 70#define EXYNOS_TMU_RISE_INT_SHIFT 0
71#define EXYNOS_TMU_FALL_INT_MASK 0x111 71#define EXYNOS_TMU_FALL_INT_MASK 0x111
72#define EXYNOS_TMU_FALL_INT_SHIFT 12
73#define EXYNOS_TMU_CLEAR_RISE_INT 0x111 72#define EXYNOS_TMU_CLEAR_RISE_INT 0x111
74#define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 12) 73#define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 12)
74#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT 12
75#define EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT 16
76#define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT 4
75#define EXYNOS_TMU_TRIP_MODE_SHIFT 13 77#define EXYNOS_TMU_TRIP_MODE_SHIFT 13
76#define EXYNOS_TMU_TRIP_MODE_MASK 0x7 78#define EXYNOS_TMU_TRIP_MODE_MASK 0x7
77#define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12 79#define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
@@ -85,6 +87,7 @@
85#define EXYNOS_TMU_INTEN_FALL0_SHIFT 16 87#define EXYNOS_TMU_INTEN_FALL0_SHIFT 16
86#define EXYNOS_TMU_INTEN_FALL1_SHIFT 20 88#define EXYNOS_TMU_INTEN_FALL1_SHIFT 20
87#define EXYNOS_TMU_INTEN_FALL2_SHIFT 24 89#define EXYNOS_TMU_INTEN_FALL2_SHIFT 24
90#define EXYNOS_TMU_INTEN_FALL3_SHIFT 28
88 91
89#define EXYNOS_EMUL_TIME 0x57F0 92#define EXYNOS_EMUL_TIME 0x57F0
90#define EXYNOS_EMUL_TIME_MASK 0xffff 93#define EXYNOS_EMUL_TIME_MASK 0xffff
@@ -95,6 +98,17 @@
95 98
96#define EXYNOS_MAX_TRIGGER_PER_REG 4 99#define EXYNOS_MAX_TRIGGER_PER_REG 4
97 100
101/* Exynos5260 specific */
102#define EXYNOS_TMU_REG_CONTROL1 0x24
103#define EXYNOS5260_TMU_REG_INTEN 0xC0
104#define EXYNOS5260_TMU_REG_INTSTAT 0xC4
105#define EXYNOS5260_TMU_REG_INTCLEAR 0xC8
106#define EXYNOS5260_TMU_CLEAR_RISE_INT 0x1111
107#define EXYNOS5260_TMU_CLEAR_FALL_INT (0x1111 << 16)
108#define EXYNOS5260_TMU_RISE_INT_MASK 0x1111
109#define EXYNOS5260_TMU_FALL_INT_MASK 0x1111
110#define EXYNOS5260_EMUL_CON 0x100
111
98/* Exynos4412 specific */ 112/* Exynos4412 specific */
99#define EXYNOS4412_MUX_ADDR_VALUE 6 113#define EXYNOS4412_MUX_ADDR_VALUE 6
100#define EXYNOS4412_MUX_ADDR_SHIFT 20 114#define EXYNOS4412_MUX_ADDR_SHIFT 20
@@ -119,7 +133,6 @@
119#define EXYNOS5440_TMU_RISE_INT_MASK 0xf 133#define EXYNOS5440_TMU_RISE_INT_MASK 0xf
120#define EXYNOS5440_TMU_RISE_INT_SHIFT 0 134#define EXYNOS5440_TMU_RISE_INT_SHIFT 0
121#define EXYNOS5440_TMU_FALL_INT_MASK 0xf 135#define EXYNOS5440_TMU_FALL_INT_MASK 0xf
122#define EXYNOS5440_TMU_FALL_INT_SHIFT 4
123#define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0 136#define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0
124#define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1 137#define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1
125#define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2 138#define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2
@@ -156,6 +169,20 @@ extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
156#define EXYNOS5250_TMU_DRV_DATA (NULL) 169#define EXYNOS5250_TMU_DRV_DATA (NULL)
157#endif 170#endif
158 171
172#if defined(CONFIG_SOC_EXYNOS5260)
173extern struct exynos_tmu_init_data const exynos5260_default_tmu_data;
174#define EXYNOS5260_TMU_DRV_DATA (&exynos5260_default_tmu_data)
175#else
176#define EXYNOS5260_TMU_DRV_DATA (NULL)
177#endif
178
179#if defined(CONFIG_SOC_EXYNOS5420)
180extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
181#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
182#else
183#define EXYNOS5420_TMU_DRV_DATA (NULL)
184#endif
185
159#if defined(CONFIG_SOC_EXYNOS5440) 186#if defined(CONFIG_SOC_EXYNOS5440)
160extern struct exynos_tmu_init_data const exynos5440_default_tmu_data; 187extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
161#define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data) 188#define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data)
diff --git a/drivers/thermal/spear_thermal.c b/drivers/thermal/spear_thermal.c
index ab79ea4701d9..1e2193fc3241 100644
--- a/drivers/thermal/spear_thermal.c
+++ b/drivers/thermal/spear_thermal.c
@@ -113,10 +113,8 @@ static int spear_thermal_probe(struct platform_device *pdev)
113 } 113 }
114 114
115 stdev = devm_kzalloc(&pdev->dev, sizeof(*stdev), GFP_KERNEL); 115 stdev = devm_kzalloc(&pdev->dev, sizeof(*stdev), GFP_KERNEL);
116 if (!stdev) { 116 if (!stdev)
117 dev_err(&pdev->dev, "kzalloc fail\n");
118 return -ENOMEM; 117 return -ENOMEM;
119 }
120 118
121 /* Enable thermal sensor */ 119 /* Enable thermal sensor */
122 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 120 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
diff --git a/drivers/thermal/ti-soc-thermal/ti-bandgap.c b/drivers/thermal/ti-soc-thermal/ti-bandgap.c
index 3ab12ee359b7..a1271b55103a 100644
--- a/drivers/thermal/ti-soc-thermal/ti-bandgap.c
+++ b/drivers/thermal/ti-soc-thermal/ti-bandgap.c
@@ -1248,7 +1248,7 @@ int ti_bandgap_probe(struct platform_device *pdev)
1248 clk_rate = clk_round_rate(bgp->div_clk, 1248 clk_rate = clk_round_rate(bgp->div_clk,
1249 bgp->conf->sensors[0].ts_data->max_freq); 1249 bgp->conf->sensors[0].ts_data->max_freq);
1250 if (clk_rate < bgp->conf->sensors[0].ts_data->min_freq || 1250 if (clk_rate < bgp->conf->sensors[0].ts_data->min_freq ||
1251 clk_rate == 0xffffffff) { 1251 clk_rate <= 0) {
1252 ret = -ENODEV; 1252 ret = -ENODEV;
1253 dev_err(&pdev->dev, "wrong clock rate (%d)\n", clk_rate); 1253 dev_err(&pdev->dev, "wrong clock rate (%d)\n", clk_rate);
1254 goto put_clks; 1254 goto put_clks;
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-24 17:37:43 -0500