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-rw-r--r--drivers/spi/spi-dw-mid.c4
-rw-r--r--drivers/spi/spi-dw.c183
-rw-r--r--drivers/spi/spi-dw.h26
3 files changed, 49 insertions, 164 deletions
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index a0197fd4e95c..8f68e8277a3b 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -110,7 +110,7 @@ static void dw_spi_dma_tx_done(void *arg)
110 110
111 if (test_and_clear_bit(TX_BUSY, &dws->dma_chan_busy) & BIT(RX_BUSY)) 111 if (test_and_clear_bit(TX_BUSY, &dws->dma_chan_busy) & BIT(RX_BUSY))
112 return; 112 return;
113 dw_spi_xfer_done(dws); 113 spi_finalize_current_transfer(dws->master);
114} 114}
115 115
116static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws) 116static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws)
@@ -155,7 +155,7 @@ static void dw_spi_dma_rx_done(void *arg)
155 155
156 if (test_and_clear_bit(RX_BUSY, &dws->dma_chan_busy) & BIT(TX_BUSY)) 156 if (test_and_clear_bit(RX_BUSY, &dws->dma_chan_busy) & BIT(TX_BUSY))
157 return; 157 return;
158 dw_spi_xfer_done(dws); 158 spi_finalize_current_transfer(dws->master);
159} 159}
160 160
161static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws) 161static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws)
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index 9a855bb00694..7d3ee82e10be 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -28,11 +28,6 @@
28#include <linux/debugfs.h> 28#include <linux/debugfs.h>
29#endif 29#endif
30 30
31#define START_STATE ((void *)0)
32#define RUNNING_STATE ((void *)1)
33#define DONE_STATE ((void *)2)
34#define ERROR_STATE ((void *)-1)
35
36/* Slave spi_dev related */ 31/* Slave spi_dev related */
37struct chip_data { 32struct chip_data {
38 u16 cr0; 33 u16 cr0;
@@ -143,6 +138,19 @@ static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
143} 138}
144#endif /* CONFIG_DEBUG_FS */ 139#endif /* CONFIG_DEBUG_FS */
145 140
141static void dw_spi_set_cs(struct spi_device *spi, bool enable)
142{
143 struct dw_spi *dws = spi_master_get_devdata(spi->master);
144 struct chip_data *chip = spi_get_ctldata(spi);
145
146 /* Chip select logic is inverted from spi_set_cs() */
147 if (chip->cs_control)
148 chip->cs_control(!enable);
149
150 if (!enable)
151 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
152}
153
146/* Return the max entries we can fill into tx fifo */ 154/* Return the max entries we can fill into tx fifo */
147static inline u32 tx_max(struct dw_spi *dws) 155static inline u32 tx_max(struct dw_spi *dws)
148{ 156{
@@ -209,93 +217,41 @@ static void dw_reader(struct dw_spi *dws)
209 } 217 }
210} 218}
211 219
212static void *next_transfer(struct dw_spi *dws)
213{
214 struct spi_message *msg = dws->cur_msg;
215 struct spi_transfer *trans = dws->cur_transfer;
216
217 /* Move to next transfer */
218 if (trans->transfer_list.next != &msg->transfers) {
219 dws->cur_transfer =
220 list_entry(trans->transfer_list.next,
221 struct spi_transfer,
222 transfer_list);
223 return RUNNING_STATE;
224 }
225
226 return DONE_STATE;
227}
228
229/* 220/*
230 * Note: first step is the protocol driver prepares 221 * Note: first step is the protocol driver prepares
231 * a dma-capable memory, and this func just need translate 222 * a dma-capable memory, and this func just need translate
232 * the virt addr to physical 223 * the virt addr to physical
233 */ 224 */
234static int map_dma_buffers(struct dw_spi *dws) 225static int map_dma_buffers(struct spi_master *master,
226 struct spi_device *spi, struct spi_transfer *transfer)
235{ 227{
236 if (!dws->cur_msg->is_dma_mapped 228 struct dw_spi *dws = spi_master_get_devdata(master);
229 struct chip_data *chip = spi_get_ctldata(spi);
230
231 if (!master->cur_msg->is_dma_mapped
237 || !dws->dma_inited 232 || !dws->dma_inited
238 || !dws->cur_chip->enable_dma 233 || !chip->enable_dma
239 || !dws->dma_ops) 234 || !dws->dma_ops)
240 return 0; 235 return 0;
241 236
242 if (dws->cur_transfer->tx_dma) 237 if (transfer->tx_dma)
243 dws->tx_dma = dws->cur_transfer->tx_dma; 238 dws->tx_dma = transfer->tx_dma;
244 239
245 if (dws->cur_transfer->rx_dma) 240 if (transfer->rx_dma)
246 dws->rx_dma = dws->cur_transfer->rx_dma; 241 dws->rx_dma = transfer->rx_dma;
247 242
248 return 1; 243 return 1;
249} 244}
250 245
251/* Caller already set message->status; dma and pio irqs are blocked */
252static void giveback(struct dw_spi *dws)
253{
254 struct spi_transfer *last_transfer;
255 struct spi_message *msg;
256
257 msg = dws->cur_msg;
258 dws->cur_msg = NULL;
259 dws->cur_transfer = NULL;
260 dws->prev_chip = dws->cur_chip;
261 dws->cur_chip = NULL;
262 dws->dma_mapped = 0;
263
264 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
265 transfer_list);
266
267 if (!last_transfer->cs_change)
268 spi_chip_sel(dws, msg->spi, 0);
269
270 spi_finalize_current_message(dws->master);
271}
272
273static void int_error_stop(struct dw_spi *dws, const char *msg) 246static void int_error_stop(struct dw_spi *dws, const char *msg)
274{ 247{
275 spi_reset_chip(dws); 248 spi_reset_chip(dws);
276 249
277 dev_err(&dws->master->dev, "%s\n", msg); 250 dev_err(&dws->master->dev, "%s\n", msg);
278 dws->cur_msg->state = ERROR_STATE; 251 dws->master->cur_msg->status = -EIO;
279 tasklet_schedule(&dws->pump_transfers); 252 spi_finalize_current_transfer(dws->master);
280} 253}
281 254
282void dw_spi_xfer_done(struct dw_spi *dws)
283{
284 /* Update total byte transferred return count actual bytes read */
285 dws->cur_msg->actual_length += dws->len;
286
287 /* Move to next transfer */
288 dws->cur_msg->state = next_transfer(dws);
289
290 /* Handle end of message */
291 if (dws->cur_msg->state == DONE_STATE) {
292 dws->cur_msg->status = 0;
293 giveback(dws);
294 } else
295 tasklet_schedule(&dws->pump_transfers);
296}
297EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
298
299static irqreturn_t interrupt_transfer(struct dw_spi *dws) 255static irqreturn_t interrupt_transfer(struct dw_spi *dws)
300{ 256{
301 u16 irq_status = dw_readw(dws, DW_SPI_ISR); 257 u16 irq_status = dw_readw(dws, DW_SPI_ISR);
@@ -312,7 +268,7 @@ static irqreturn_t interrupt_transfer(struct dw_spi *dws)
312 dw_reader(dws); 268 dw_reader(dws);
313 if (dws->rx_end == dws->rx) { 269 if (dws->rx_end == dws->rx) {
314 spi_mask_intr(dws, SPI_INT_TXEI); 270 spi_mask_intr(dws, SPI_INT_TXEI);
315 dw_spi_xfer_done(dws); 271 spi_finalize_current_transfer(dws->master);
316 return IRQ_HANDLED; 272 return IRQ_HANDLED;
317 } 273 }
318 if (irq_status & SPI_INT_TXEI) { 274 if (irq_status & SPI_INT_TXEI) {
@@ -327,13 +283,14 @@ static irqreturn_t interrupt_transfer(struct dw_spi *dws)
327 283
328static irqreturn_t dw_spi_irq(int irq, void *dev_id) 284static irqreturn_t dw_spi_irq(int irq, void *dev_id)
329{ 285{
330 struct dw_spi *dws = dev_id; 286 struct spi_master *master = dev_id;
287 struct dw_spi *dws = spi_master_get_devdata(master);
331 u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f; 288 u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f;
332 289
333 if (!irq_status) 290 if (!irq_status)
334 return IRQ_NONE; 291 return IRQ_NONE;
335 292
336 if (!dws->cur_msg) { 293 if (!master->cur_msg) {
337 spi_mask_intr(dws, SPI_INT_TXEI); 294 spi_mask_intr(dws, SPI_INT_TXEI);
338 return IRQ_HANDLED; 295 return IRQ_HANDLED;
339 } 296 }
@@ -342,7 +299,7 @@ static irqreturn_t dw_spi_irq(int irq, void *dev_id)
342} 299}
343 300
344/* Must be called inside pump_transfers() */ 301/* Must be called inside pump_transfers() */
345static void poll_transfer(struct dw_spi *dws) 302static int poll_transfer(struct dw_spi *dws)
346{ 303{
347 do { 304 do {
348 dw_writer(dws); 305 dw_writer(dws);
@@ -350,17 +307,14 @@ static void poll_transfer(struct dw_spi *dws)
350 cpu_relax(); 307 cpu_relax();
351 } while (dws->rx_end > dws->rx); 308 } while (dws->rx_end > dws->rx);
352 309
353 dw_spi_xfer_done(dws); 310 return 0;
354} 311}
355 312
356static void pump_transfers(unsigned long data) 313static int dw_spi_transfer_one(struct spi_master *master,
314 struct spi_device *spi, struct spi_transfer *transfer)
357{ 315{
358 struct dw_spi *dws = (struct dw_spi *)data; 316 struct dw_spi *dws = spi_master_get_devdata(master);
359 struct spi_message *message = NULL; 317 struct chip_data *chip = spi_get_ctldata(spi);
360 struct spi_transfer *transfer = NULL;
361 struct spi_transfer *previous = NULL;
362 struct spi_device *spi = NULL;
363 struct chip_data *chip = NULL;
364 u8 bits = 0; 318 u8 bits = 0;
365 u8 imask = 0; 319 u8 imask = 0;
366 u8 cs_change = 0; 320 u8 cs_change = 0;
@@ -369,35 +323,8 @@ static void pump_transfers(unsigned long data)
369 u32 speed = 0; 323 u32 speed = 0;
370 u32 cr0 = 0; 324 u32 cr0 = 0;
371 325
372 /* Get current state information */
373 message = dws->cur_msg;
374 transfer = dws->cur_transfer;
375 chip = dws->cur_chip;
376 spi = message->spi;
377
378 if (message->state == ERROR_STATE) {
379 message->status = -EIO;
380 goto early_exit;
381 }
382
383 /* Handle end of message */
384 if (message->state == DONE_STATE) {
385 message->status = 0;
386 goto early_exit;
387 }
388
389 /* Delay if requested at end of transfer */
390 if (message->state == RUNNING_STATE) {
391 previous = list_entry(transfer->transfer_list.prev,
392 struct spi_transfer,
393 transfer_list);
394 if (previous->delay_usecs)
395 udelay(previous->delay_usecs);
396 }
397
398 dws->n_bytes = chip->n_bytes; 326 dws->n_bytes = chip->n_bytes;
399 dws->dma_width = chip->dma_width; 327 dws->dma_width = chip->dma_width;
400 dws->cs_control = chip->cs_control;
401 328
402 dws->rx_dma = transfer->rx_dma; 329 dws->rx_dma = transfer->rx_dma;
403 dws->tx_dma = transfer->tx_dma; 330 dws->tx_dma = transfer->tx_dma;
@@ -405,7 +332,7 @@ static void pump_transfers(unsigned long data)
405 dws->tx_end = dws->tx + transfer->len; 332 dws->tx_end = dws->tx + transfer->len;
406 dws->rx = transfer->rx_buf; 333 dws->rx = transfer->rx_buf;
407 dws->rx_end = dws->rx + transfer->len; 334 dws->rx_end = dws->rx + transfer->len;
408 dws->len = dws->cur_transfer->len; 335 dws->len = transfer->len;
409 if (chip != dws->prev_chip) 336 if (chip != dws->prev_chip)
410 cs_change = 1; 337 cs_change = 1;
411 338
@@ -437,13 +364,12 @@ static void pump_transfers(unsigned long data)
437 | (spi->mode << SPI_MODE_OFFSET) 364 | (spi->mode << SPI_MODE_OFFSET)
438 | (chip->tmode << SPI_TMOD_OFFSET); 365 | (chip->tmode << SPI_TMOD_OFFSET);
439 } 366 }
440 message->state = RUNNING_STATE;
441 367
442 /* 368 /*
443 * Adjust transfer mode if necessary. Requires platform dependent 369 * Adjust transfer mode if necessary. Requires platform dependent
444 * chipselect mechanism. 370 * chipselect mechanism.
445 */ 371 */
446 if (dws->cs_control) { 372 if (chip->cs_control) {
447 if (dws->rx && dws->tx) 373 if (dws->rx && dws->tx)
448 chip->tmode = SPI_TMOD_TR; 374 chip->tmode = SPI_TMOD_TR;
449 else if (dws->rx) 375 else if (dws->rx)
@@ -456,10 +382,9 @@ static void pump_transfers(unsigned long data)
456 } 382 }
457 383
458 dw_writew(dws, DW_SPI_CTRL0, cr0); 384 dw_writew(dws, DW_SPI_CTRL0, cr0);
459 spi_chip_sel(dws, spi, 1);
460 385
461 /* Check if current transfer is a DMA transaction */ 386 /* Check if current transfer is a DMA transaction */
462 dws->dma_mapped = map_dma_buffers(dws); 387 dws->dma_mapped = map_dma_buffers(master, spi, transfer);
463 388
464 /* For poll mode just disable all interrupts */ 389 /* For poll mode just disable all interrupts */
465 spi_mask_intr(dws, 0xff); 390 spi_mask_intr(dws, 0xff);
@@ -489,31 +414,17 @@ static void pump_transfers(unsigned long data)
489 dws->dma_ops->dma_transfer(dws, cs_change); 414 dws->dma_ops->dma_transfer(dws, cs_change);
490 415
491 if (chip->poll_mode) 416 if (chip->poll_mode)
492 poll_transfer(dws); 417 return poll_transfer(dws);
493 418
494 return; 419 return 1;
495
496early_exit:
497 giveback(dws);
498} 420}
499 421
500static int dw_spi_transfer_one_message(struct spi_master *master, 422static void dw_spi_handle_err(struct spi_master *master,
501 struct spi_message *msg) 423 struct spi_message *msg)
502{ 424{
503 struct dw_spi *dws = spi_master_get_devdata(master); 425 struct dw_spi *dws = spi_master_get_devdata(master);
504 426
505 dws->cur_msg = msg; 427 spi_reset_chip(dws);
506 /* Initial message state */
507 dws->cur_msg->state = START_STATE;
508 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
509 struct spi_transfer,
510 transfer_list);
511 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
512
513 /* Launch transfers */
514 tasklet_schedule(&dws->pump_transfers);
515
516 return 0;
517} 428}
518 429
519/* This may be called twice for each spi dev */ 430/* This may be called twice for each spi dev */
@@ -637,7 +548,7 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
637 snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num); 548 snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num);
638 549
639 ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED, 550 ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED,
640 dws->name, dws); 551 dws->name, master);
641 if (ret < 0) { 552 if (ret < 0) {
642 dev_err(&master->dev, "can not get IRQ\n"); 553 dev_err(&master->dev, "can not get IRQ\n");
643 goto err_free_master; 554 goto err_free_master;
@@ -649,7 +560,9 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
649 master->num_chipselect = dws->num_cs; 560 master->num_chipselect = dws->num_cs;
650 master->setup = dw_spi_setup; 561 master->setup = dw_spi_setup;
651 master->cleanup = dw_spi_cleanup; 562 master->cleanup = dw_spi_cleanup;
652 master->transfer_one_message = dw_spi_transfer_one_message; 563 master->set_cs = dw_spi_set_cs;
564 master->transfer_one = dw_spi_transfer_one;
565 master->handle_err = dw_spi_handle_err;
653 master->max_speed_hz = dws->max_freq; 566 master->max_speed_hz = dws->max_freq;
654 master->dev.of_node = dev->of_node; 567 master->dev.of_node = dev->of_node;
655 568
@@ -664,8 +577,6 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
664 } 577 }
665 } 578 }
666 579
667 tasklet_init(&dws->pump_transfers, pump_transfers, (unsigned long)dws);
668
669 spi_master_set_devdata(master, dws); 580 spi_master_set_devdata(master, dws);
670 ret = devm_spi_register_master(dev, master); 581 ret = devm_spi_register_master(dev, master);
671 if (ret) { 582 if (ret) {
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 1a7f083c2217..855bfdd7b433 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -96,7 +96,6 @@ struct dw_spi_dma_ops {
96 96
97struct dw_spi { 97struct dw_spi {
98 struct spi_master *master; 98 struct spi_master *master;
99 struct spi_device *cur_dev;
100 enum dw_ssi_type type; 99 enum dw_ssi_type type;
101 char name[16]; 100 char name[16];
102 101
@@ -109,13 +108,7 @@ struct dw_spi {
109 u16 bus_num; 108 u16 bus_num;
110 u16 num_cs; /* supported slave numbers */ 109 u16 num_cs; /* supported slave numbers */
111 110
112 /* Message Transfer pump */
113 struct tasklet_struct pump_transfers;
114
115 /* Current message transfer state info */ 111 /* Current message transfer state info */
116 struct spi_message *cur_msg;
117 struct spi_transfer *cur_transfer;
118 struct chip_data *cur_chip;
119 struct chip_data *prev_chip; 112 struct chip_data *prev_chip;
120 size_t len; 113 size_t len;
121 void *tx; 114 void *tx;
@@ -128,10 +121,8 @@ struct dw_spi {
128 size_t rx_map_len; 121 size_t rx_map_len;
129 size_t tx_map_len; 122 size_t tx_map_len;
130 u8 n_bytes; /* current is a 1/2 bytes op */ 123 u8 n_bytes; /* current is a 1/2 bytes op */
131 u8 max_bits_per_word; /* maxim is 16b */
132 u32 dma_width; 124 u32 dma_width;
133 irqreturn_t (*transfer_handler)(struct dw_spi *dws); 125 irqreturn_t (*transfer_handler)(struct dw_spi *dws);
134 void (*cs_control)(u32 command);
135 126
136 /* Dma info */ 127 /* Dma info */
137 int dma_inited; 128 int dma_inited;
@@ -182,22 +173,6 @@ static inline void spi_set_clk(struct dw_spi *dws, u16 div)
182 dw_writel(dws, DW_SPI_BAUDR, div); 173 dw_writel(dws, DW_SPI_BAUDR, div);
183} 174}
184 175
185static inline void spi_chip_sel(struct dw_spi *dws, struct spi_device *spi,
186 int active)
187{
188 u16 cs = spi->chip_select;
189 int gpio_val = active ? (spi->mode & SPI_CS_HIGH) :
190 !(spi->mode & SPI_CS_HIGH);
191
192 if (dws->cs_control)
193 dws->cs_control(active);
194 if (gpio_is_valid(spi->cs_gpio))
195 gpio_set_value(spi->cs_gpio, gpio_val);
196
197 if (active)
198 dw_writel(dws, DW_SPI_SER, 1 << cs);
199}
200
201/* Disable IRQ bits */ 176/* Disable IRQ bits */
202static inline void spi_mask_intr(struct dw_spi *dws, u32 mask) 177static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
203{ 178{
@@ -245,7 +220,6 @@ extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
245extern void dw_spi_remove_host(struct dw_spi *dws); 220extern void dw_spi_remove_host(struct dw_spi *dws);
246extern int dw_spi_suspend_host(struct dw_spi *dws); 221extern int dw_spi_suspend_host(struct dw_spi *dws);
247extern int dw_spi_resume_host(struct dw_spi *dws); 222extern int dw_spi_resume_host(struct dw_spi *dws);
248extern void dw_spi_xfer_done(struct dw_spi *dws);
249 223
250/* platform related setup */ 224/* platform related setup */
251extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */ 225extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */