1138 files changed, 42128 insertions, 22215 deletions

diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index 87a1e8fb6242..e3f93fb9224e 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -3,17 +3,26 @@ ARM Allwinner SoCs
 
 This document lists all the ARM Allwinner SoCs that are currently
 supported in mainline by the Linux kernel. This document will also
-provide links to documentation and or datasheet for these SoCs.
+provide links to documentation and/or datasheet for these SoCs.
 
 SunXi family
 ------------
+  Linux kernel mach directory: arch/arm/mach-sunxi
 
   Flavors:
-        Allwinner A10 (sun4i)
-                Datasheet       : http://dl.linux-sunxi.org/A10/A10%20Datasheet%20-%20v1.21%20%282012-04-06%29.pdf
+    * ARM Cortex-A8 based SoCs
+      - Allwinner A10 (sun4i)
+        + Datasheet
+          http://dl.linux-sunxi.org/A10/A10%20Datasheet%20-%20v1.21%20%282012-04-06%29.pdf
+        + User Manual
+          http://dl.linux-sunxi.org/A10/A10%20User%20Manual%20-%20v1.20%20%282012-04-09%2c%20DECRYPTED%29.pdf
 
-        Allwinner A13 (sun5i)
-                Datasheet       : http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf
+      - Allwinner A10s (sun5i)
+        + Datasheet
+          http://dl.linux-sunxi.org/A10s/A10s%20Datasheet%20-%20v1.20%20%282012-03-27%29.pdf
 
-  Core: Cortex A8
-  Linux kernel mach directory: arch/arm/mach-sunxi
\ No newline at end of file
+      - Allwinner A13 (sun5i)
+        + Datasheet
+          http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf
+        + User Manual
+          http://dl.linux-sunxi.org/A13/A13%20User%20Manual%20-%20v1.2%20%282013-08-08%29.pdf
diff --git a/Documentation/bcache.txt b/Documentation/bcache.txt
index 77db8809bd96..b3a7e7d384f6 100644
--- a/Documentation/bcache.txt
+++ b/Documentation/bcache.txt
@@ -319,7 +319,10 @@ cache<0..n>
   Symlink to each of the cache devices comprising this cache set. 
 
 cache_available_percent
-  Percentage of cache device free.
+  Percentage of cache device which doesn't contain dirty data, and could
+  potentially be used for writeback.  This doesn't mean this space isn't used
+  for clean cached data; the unused statistic (in priority_stats) is typically
+  much lower.
 
 clear_stats
   Clears the statistics associated with this cache
@@ -423,8 +426,11 @@ nbuckets
   Total buckets in this cache
 
 priority_stats
-  Statistics about how recently data in the cache has been accessed.  This can
-  reveal your working set size.
+  Statistics about how recently data in the cache has been accessed.
+  This can reveal your working set size.  Unused is the percentage of
+  the cache that doesn't contain any data.  Metadata is bcache's
+  metadata overhead.  Average is the average priority of cache buckets.
+  Next is a list of quantiles with the priority threshold of each.
 
 written
   Sum of all data that has been written to the cache; comparison with
diff --git a/Documentation/devices.txt b/Documentation/devices.txt
index 08f01e79c41a..b9015912bca6 100644
--- a/Documentation/devices.txt
+++ b/Documentation/devices.txt
@@ -498,12 +498,8 @@ Your cooperation is appreciated.
 
                 Each device type has 5 bits (32 minors).
 
- 13 block       8-bit MFM/RLL/IDE controller
-                  0 = /dev/xda          First XT disk whole disk
-                 64 = /dev/xdb          Second XT disk whole disk
-
-                Partitions are handled in the same way as IDE disks
-                (see major number 3).
+ 13 block       Previously used for the XT disk (/dev/xdN)
+                Deleted in kernel v3.9.
 
  14 char        Open Sound System (OSS)
                   0 = /dev/mixer        Mixer control
diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt
new file mode 100644
index 000000000000..92d36e2aa877
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cci.txt
@@ -0,0 +1,172 @@
+=======================================================
+ARM CCI cache coherent interconnect binding description
+=======================================================
+
+ARM multi-cluster systems maintain intra-cluster coherency through a
+cache coherent interconnect (CCI) that is capable of monitoring bus
+transactions and manage coherency, TLB invalidations and memory barriers.
+
+It allows snooping and distributed virtual memory message broadcast across
+clusters, through memory mapped interface, with a global control register
+space and multiple sets of interface control registers, one per slave
+interface.
+
+Bindings for the CCI node follow the ePAPR standard, available from:
+
+www.power.org/documentation/epapr-version-1-1/
+
+with the addition of the bindings described in this document which are
+specific to ARM.
+
+* CCI interconnect node
+
+        Description: Describes a CCI cache coherent Interconnect component
+
+        Node name must be "cci".
+        Node's parent must be the root node /, and the address space visible
+        through the CCI interconnect is the same as the one seen from the
+        root node (ie from CPUs perspective as per DT standard).
+        Every CCI node has to define the following properties:
+
+        - compatible
+                Usage: required
+                Value type: <string>
+                Definition: must be set to
+                            "arm,cci-400"
+
+        - reg
+                Usage: required
+                Value type: <prop-encoded-array>
+                Definition: A standard property. Specifies base physical
+                            address of CCI control registers common to all
+                            interfaces.
+
+        - ranges:
+                Usage: required
+                Value type: <prop-encoded-array>
+                Definition: A standard property. Follow rules in the ePAPR for
+                            hierarchical bus addressing. CCI interfaces
+                            addresses refer to the parent node addressing
+                            scheme to declare their register bases.
+
+        CCI interconnect node can define the following child nodes:
+
+        - CCI control interface nodes
+
+                Node name must be "slave-if".
+                Parent node must be CCI interconnect node.
+
+                A CCI control interface node must contain the following
+                properties:
+
+                - compatible
+                        Usage: required
+                        Value type: <string>
+                        Definition: must be set to
+                                    "arm,cci-400-ctrl-if"
+
+                - interface-type:
+                        Usage: required
+                        Value type: <string>
+                        Definition: must be set to one of {"ace", "ace-lite"}
+                                    depending on the interface type the node
+                                    represents.
+
+                - reg:
+                        Usage: required
+                        Value type: <prop-encoded-array>
+                        Definition: the base address and size of the
+                                    corresponding interface programming
+                                    registers.
+
+* CCI interconnect bus masters
+
+        Description: masters in the device tree connected to a CCI port
+                     (inclusive of CPUs and their cpu nodes).
+
+        A CCI interconnect bus master node must contain the following
+        properties:
+
+        - cci-control-port:
+                Usage: required
+                Value type: <phandle>
+                Definition: a phandle containing the CCI control interface node
+                            the master is connected to.
+
+Example:
+
+        cpus {
+                #size-cells = <0>;
+                #address-cells = <1>;
+
+                CPU0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        cci-control-port = <&cci_control1>;
+                        reg = <0x0>;
+                };
+
+                CPU1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        cci-control-port = <&cci_control1>;
+                        reg = <0x1>;
+                };
+
+                CPU2: cpu@100 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        cci-control-port = <&cci_control2>;
+                        reg = <0x100>;
+                };
+
+                CPU3: cpu@101 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        cci-control-port = <&cci_control2>;
+                        reg = <0x101>;
+                };
+
+        };
+
+        dma0: dma@3000000 {
+                compatible = "arm,pl330", "arm,primecell";
+                cci-control-port = <&cci_control0>;
+                reg = <0x0 0x3000000 0x0 0x1000>;
+                interrupts = <10>;
+                #dma-cells = <1>;
+                #dma-channels = <8>;
+                #dma-requests = <32>;
+        };
+
+        cci@2c090000 {
+                compatible = "arm,cci-400";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x0 0x2c090000 0 0x1000>;
+                ranges = <0x0 0x0 0x2c090000 0x6000>;
+
+                cci_control0: slave-if@1000 {
+                        compatible = "arm,cci-400-ctrl-if";
+                        interface-type = "ace-lite";
+                        reg = <0x1000 0x1000>;
+                };
+
+                cci_control1: slave-if@4000 {
+                        compatible = "arm,cci-400-ctrl-if";
+                        interface-type = "ace";
+                        reg = <0x4000 0x1000>;
+                };
+
+                cci_control2: slave-if@5000 {
+                        compatible = "arm,cci-400-ctrl-if";
+                        interface-type = "ace";
+                        reg = <0x5000 0x1000>;
+                };
+        };
+
+This CCI node corresponds to a CCI component whose control registers sits
+at address 0x000000002c090000.
+CCI slave interface @0x000000002c091000 is connected to dma controller dma0.
+CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};
+CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};
diff --git a/Documentation/devicetree/bindings/arm/keystone/keystone.txt b/Documentation/devicetree/bindings/arm/keystone/keystone.txt
new file mode 100644
index 000000000000..63c0e6ae5cf7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/keystone/keystone.txt
@@ -0,0 +1,10 @@
+TI Keystone Platforms Device Tree Bindings
+-----------------------------------------------
+
+Boards with Keystone2 based devices (TCI66xxK2H) SOC shall have the
+following properties.
+
+Required properties:
+ - compatible: All TI specific devices present in Keystone SOC should be in
+   the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550
+   type UART should use the specified compatible for those devices.
diff --git a/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt b/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt
new file mode 100644
index 000000000000..3b8fbf3c00c5
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt
@@ -0,0 +1,19 @@
+ARM Dual Cluster System Configuration Block
+-------------------------------------------
+
+The Dual Cluster System Configuration Block (DCSCB) provides basic
+functionality for controlling clocks, resets and configuration pins in
+the Dual Cluster System implemented by the Real-Time System Model (RTSM).
+
+Required properties:
+
+- compatible : should be "arm,rtsm,dcscb"
+
+- reg : physical base address and the size of the registers window
+
+Example:
+
+        dcscb@60000000 {
+                compatible = "arm,rtsm,dcscb";
+                reg = <0x60000000 0x1000>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/ste-u300.txt b/Documentation/devicetree/bindings/arm/ste-u300.txt
new file mode 100644
index 000000000000..69b5ab0b5f4b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/ste-u300.txt
@@ -0,0 +1,46 @@
+ST-Ericsson U300 Device Tree Bindings
+
+For various board the "board" node may contain specific properties
+that pertain to this particular board, such as board-specific GPIOs
+or board power regulator supplies.
+
+Required root node property:
+
+compatible="stericsson,u300";
+
+Required node: syscon
+This contains the system controller.
+- compatible: must be "stericsson,u300-syscon".
+- reg: the base address and size of the system controller.
+
+Boards with the U300 SoC include:
+
+S365 "Small Board U365":
+
+Required node: s365
+This contains the board-specific information.
+- compatible: must be "stericsson,s365".
+- vana15-supply: the regulator supplying the 1.5V to drive the
+  board.
+- syscon: a pointer to the syscon node so we can acccess the
+  syscon registers to set the board as self-powered.
+
+Example:
+
+/ {
+        model = "ST-Ericsson U300";
+        compatible = "stericsson,u300";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        s365 {
+                compatible = "stericsson,s365";
+                vana15-supply = <&ab3100_ldo_d_reg>;
+                syscon = <&syscon>;
+        };
+
+        syscon: syscon@c0011000 {
+                compatible = "stericsson,u300-syscon";
+                reg = <0xc0011000 0x1000>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
index d71b4b2c077d..f46f5625d8ad 100644
--- a/Documentation/devicetree/bindings/clock/imx5-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -184,6 +184,19 @@ clocks and IDs.
         cko2                    170
         srtc_gate               171
         pata_gate               172
+        sata_gate               173
+        spdif_xtal_sel          174
+        spdif0_sel              175
+        spdif1_sel              176
+        spdif0_pred             177
+        spdif0_podf             178
+        spdif1_pred             179
+        spdif1_podf             180
+        spdif0_com_sel          181
+        spdif1_com_sel          182
+        spdif0_gate             183
+        spdif1_gate             184
+        spdif_ipg_gate          185
 
 Examples (for mx53):
 
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index 6deb6fd1c7cd..a0e104f0527e 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -208,6 +208,7 @@ clocks and IDs.
         pll4_post_div           193
         pll5_post_div           194
         pll5_video_div          195
+        eim_slow                196
 
 Examples:
 
diff --git a/Documentation/devicetree/bindings/clock/imx6sl-clock.txt b/Documentation/devicetree/bindings/clock/imx6sl-clock.txt
new file mode 100644
index 000000000000..15e40bdf147d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx6sl-clock.txt
@@ -0,0 +1,10 @@
+* Clock bindings for Freescale i.MX6 SoloLite
+
+Required properties:
+- compatible: Should be "fsl,imx6sl-ccm"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.  See include/dt-bindings/clock/imx6sl-clock.h
+for the full list of i.MX6 SoloLite clock IDs.
diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
new file mode 100644
index 000000000000..7cafcb98ead7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
@@ -0,0 +1,80 @@
+Clock bindings for ST-Ericsson U300 System Controller Clocks
+
+Bindings for the gated system controller clocks:
+
+Required properties:
+- compatible: must be "stericsson,u300-syscon-clk"
+- #clock-cells: must be <0>
+- clock-type: specifies the type of clock:
+  0 = slow clock
+  1 = fast clock
+  2 = rest/remaining clock
+- clock-id: specifies the clock in the type range
+
+Optional properties:
+- clocks: parent clock(s)
+
+The available clocks per type are as follows:
+
+Type:  ID:   Clock:
+-------------------
+0      0     Slow peripheral bridge clock
+0      1     UART0 clock
+0      4     GPIO clock
+0      6     RTC clock
+0      7     Application timer clock
+0      8     Access timer clock
+
+1      0     Fast peripheral bridge clock
+1      1     I2C bus 0 clock
+1      2     I2C bus 1 clock
+1      5     MMC interface peripheral (silicon) clock
+1      6     SPI clock
+
+2      3     CPU clock
+2      4     DMA controller clock
+2      5     External Memory Interface (EMIF) clock
+2      6     NAND flask interface clock
+2      8     XGAM graphics engine clock
+2      9     Shared External Memory Interface (SEMI) clock
+2      10    AHB Subsystem Bridge clock
+2      12    Interrupt controller clock
+
+Example:
+
+gpio_clk: gpio_clk@13M {
+        #clock-cells = <0>;
+        compatible = "stericsson,u300-syscon-clk";
+        clock-type = <0>; /* Slow */
+        clock-id = <4>;
+        clocks = <&slow_clk>;
+};
+
+gpio: gpio@c0016000 {
+        compatible = "stericsson,gpio-coh901";
+        (...)
+        clocks = <&gpio_clk>;
+};
+
+
+Bindings for the MMC/SD card clock:
+
+Required properties:
+- compatible: must be "stericsson,u300-syscon-mclk"
+- #clock-cells: must be <0>
+
+Optional properties:
+- clocks: parent clock(s)
+
+mmc_mclk: mmc_mclk {
+        #clock-cells = <0>;
+        compatible = "stericsson,u300-syscon-mclk";
+        clocks = <&mmc_pclk>;
+};
+
+mmcsd: mmcsd@c0001000 {
+        compatible = "arm,pl18x", "arm,primecell";
+        clocks = <&mmc_pclk>, <&mmc_mclk>;
+        clock-names = "apb_pclk", "mclk";
+        (...)
+};
diff --git a/Documentation/devicetree/bindings/clock/vf610-clock.txt b/Documentation/devicetree/bindings/clock/vf610-clock.txt
new file mode 100644
index 000000000000..c80863d344ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/vf610-clock.txt
@@ -0,0 +1,26 @@
+* Clock bindings for Freescale Vybrid VF610 SOC
+
+Required properties:
+- compatible: Should be "fsl,vf610-ccm"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
+for the full list of VF610 clock IDs.
+
+Examples:
+
+clks: ccm@4006b000 {
+        compatible = "fsl,vf610-ccm";
+        reg = <0x4006b000 0x1000>;
+        #clock-cells = <1>;
+};
+
+uart1: serial@40028000 {
+        compatible = "fsl,vf610-uart";
+        reg = <0x40028000 0x1000>;
+        interrupts = <0 62 0x04>;
+        clocks = <&clks VF610_CLK_UART1>;
+        clock-names = "ipg";
+};
diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt
index 23ae1db1bc13..d99af878f5d7 100644
--- a/Documentation/devicetree/bindings/clock/zynq-7000.txt
+++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt
@@ -6,50 +6,99 @@ The purpose of this document is to document their usage.
 See clock_bindings.txt for more information on the generic clock bindings.
 See Chapter 25 of Zynq TRM for more information about Zynq clocks.
 
-== PLLs ==
-
-Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.
+== Clock Controller ==
+The clock controller is a logical abstraction of Zynq's clock tree. It reads
+required input clock frequencies from the devicetree and acts as clock provider
+for all clock consumers of PS clocks.
 
 Required properties:
-- #clock-cells : shall be 0 (only one clock is output from this node)
-- compatible : "xlnx,zynq-pll"
-- reg : pair of u32 values, which are the address offsets within the SLCR
-        of the relevant PLL_CTRL register and PLL_CFG register respectively
-- clocks : phandle for parent clock.  should be the phandle for ps_clk
+ - #clock-cells : Must be 1
+ - compatible : "xlnx,ps7-clkc"
+ - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
+                      (usually 33 MHz oscillators are used for Zynq platforms)
+ - clock-output-names : List of strings used to name the clock outputs. Shall be
+                        a list of the outputs given below.
 
 Optional properties:
-- clock-output-names : name of the output clock
-
-Example:
-        armpll: armpll {
-                #clock-cells = <0>;
-                compatible = "xlnx,zynq-pll";
-                clocks = <&ps_clk>;
-                reg = <0x100 0x110>;
-                clock-output-names = "armpll";
-        };
-
-== Peripheral clocks ==
+ - clocks : as described in the clock bindings
+ - clock-names : as described in the clock bindings
 
-Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks.
+Clock inputs:
+The following strings are optional parameters to the 'clock-names' property in
+order to provide an optional (E)MIO clock source.
+ - swdt_ext_clk
+ - gem0_emio_clk
+ - gem1_emio_clk
+ - mio_clk_XX           # with XX = 00..53
+...
 
-Required properties:
-- #clock-cells : shall be 1
-- compatible : "xlnx,zynq-periph-clock"
-- reg : a single u32 value, describing the offset within the SLCR where
-        the CLK_CTRL register is found for this peripheral
-- clocks : phandle for parent clocks.  should hold phandles for
-           the IO_PLL, ARM_PLL, and DDR_PLL in order
-- clock-output-names : names of the output clock(s).  For peripherals that have
-                       two output clocks (for example, the UART), two clocks
-                       should be listed.
+Clock outputs:
+ 0:  armpll
+ 1:  ddrpll
+ 2:  iopll
+ 3:  cpu_6or4x
+ 4:  cpu_3or2x
+ 5:  cpu_2x
+ 6:  cpu_1x
+ 7:  ddr2x
+ 8:  ddr3x
+ 9:  dci
+ 10: lqspi
+ 11: smc
+ 12: pcap
+ 13: gem0
+ 14: gem1
+ 15: fclk0
+ 16: fclk1
+ 17: fclk2
+ 18: fclk3
+ 19: can0
+ 20: can1
+ 21: sdio0
+ 22: sdio1
+ 23: uart0
+ 24: uart1
+ 25: spi0
+ 26: spi1
+ 27: dma
+ 28: usb0_aper
+ 29: usb1_aper
+ 30: gem0_aper
+ 31: gem1_aper
+ 32: sdio0_aper
+ 33: sdio1_aper
+ 34: spi0_aper
+ 35: spi1_aper
+ 36: can0_aper
+ 37: can1_aper
+ 38: i2c0_aper
+ 39: i2c1_aper
+ 40: uart0_aper
+ 41: uart1_aper
+ 42: gpio_aper
+ 43: lqspi_aper
+ 44: smc_aper
+ 45: swdt
+ 46: dbg_trc
+ 47: dbg_apb
 
 Example:
-        uart_clk: uart_clk {
+        clkc: clkc {
                 #clock-cells = <1>;
-                compatible = "xlnx,zynq-periph-clock";
-                clocks = <&iopll &armpll &ddrpll>;
-                reg = <0x154>;
-                clock-output-names = "uart0_ref_clk",
-                                     "uart1_ref_clk";
+                compatible = "xlnx,ps7-clkc";
+                ps-clk-frequency = <33333333>;
+                clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
+                                "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
+                                "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
+                                "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+                                "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
+                                "dma", "usb0_aper", "usb1_aper", "gem0_aper",
+                                "gem1_aper", "sdio0_aper", "sdio1_aper",
+                                "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
+                                "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
+                                "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
+                                "dbg_trc", "dbg_apb";
+                # optional props
+                clocks = <&clkc 16>, <&clk_foo>;
+                clock-names = "gem1_emio_clk", "can_mio_clk_23";
         };
diff --git a/Documentation/devicetree/bindings/dma/ste-coh901318.txt b/Documentation/devicetree/bindings/dma/ste-coh901318.txt
new file mode 100644
index 000000000000..091ad057e9cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/ste-coh901318.txt
@@ -0,0 +1,32 @@
+ST-Ericsson COH 901 318 DMA Controller
+
+This is a DMA controller which has begun as a fork of the
+ARM PL08x PrimeCell VHDL code.
+
+Required properties:
+- compatible: should be "stericsson,coh901318"
+- reg: register locations and length
+- interrupts: the single DMA IRQ
+- #dma-cells: must be set to <1>, as the channels on the
+  COH 901 318 are simple and identified by a single number
+- dma-channels: the number of DMA channels handled
+
+Example:
+
+dmac: dma-controller@c00020000 {
+        compatible = "stericsson,coh901318";
+        reg = <0xc0020000 0x1000>;
+        interrupt-parent = <&vica>;
+        interrupts = <2>;
+        #dma-cells = <1>;
+        dma-channels = <40>;
+};
+
+Consumers example:
+
+uart0: serial@c0013000 {
+        compatible = "...";
+        (...)
+        dmas = <&dmac 17 &dmac 18>;
+        dma-names = "tx", "rx";
+};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-clps711x.txt b/Documentation/devicetree/bindings/gpio/gpio-clps711x.txt
new file mode 100644
index 000000000000..e0d0446a6b78
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-clps711x.txt
@@ -0,0 +1,28 @@
+Cirrus Logic CLPS711X GPIO controller
+
+Required properties:
+- compatible: Should be "cirrus,clps711x-gpio"
+- reg: Physical base GPIO controller registers location and length.
+  There should be two registers, first is DATA register, the second
+  is DIRECTION.
+- gpio-controller: Marks the device node as a gpio controller.
+- #gpio-cells: Should be two. The first cell is the pin number and
+  the second cell is used to specify the gpio polarity:
+    0 = active high
+    1 = active low
+
+Note: Each GPIO port should have an alias correctly numbered in "aliases"
+node.
+
+Example:
+
+aliases {
+        gpio0 = &porta;
+};
+
+porta: gpio@80000000 {
+        compatible = "cirrus,clps711x-gpio";
+        reg = <0x80000000 0x1>, <0x80000040 0x1>;
+        gpio-controller;
+        #gpio-cells = <2>;
+};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt b/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt
new file mode 100644
index 000000000000..fd665b44d767
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt
@@ -0,0 +1,7 @@
+ST-Ericsson COH 901 571/3 GPIO controller
+
+Required properties:
+- compatible: Compatible property value should be "stericsson,gpio-coh901"
+- reg: Physical base address of the controller and length of memory mapped
+  region.
+- interrupts: the 0...n interrupts assigned to the different GPIO ports/banks.
diff --git a/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt b/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt
new file mode 100644
index 000000000000..bd81a482634f
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt
@@ -0,0 +1,15 @@
+ST Microelectronics DDC I2C
+
+Required properties :
+- compatible : Must be "st,ddci2c"
+- reg: physical base address of the controller and length of memory mapped
+     region.
+- interrupts: interrupt number to the cpu.
+- #address-cells = <1>;
+- #size-cells = <0>;
+
+Optional properties:
+- Child nodes conforming to i2c bus binding
+
+Examples :
+
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
index e7f4dc14eff2..57edb30dbbca 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
@@ -8,91 +8,8 @@ Required properties:
 - #interrupt-cells : Specifies the number of cells needed to encode an
   interrupt source. The value shall be 1.
 
-The interrupt sources are as follows:
-
-0: ENMI
-1: UART0
-2: UART1
-3: UART2
-4: UART3
-5: IR0
-6: IR1
-7: I2C0
-8: I2C1
-9: I2C2
-10: SPI0
-11: SPI1
-12: SPI2
-13: SPDIF
-14: AC97
-15: TS
-16: I2S
-17: UART4
-18: UART5
-19: UART6
-20: UART7
-21: KEYPAD
-22: TIMER0
-23: TIMER1
-24: TIMER2
-25: TIMER3
-26: CAN
-27: DMA
-28: PIO
-29: TOUCH_PANEL
-30: AUDIO_CODEC
-31: LRADC
-32: SDMC0
-33: SDMC1
-34: SDMC2
-35: SDMC3
-36: MEMSTICK
-37: NAND
-38: USB0
-39: USB1
-40: USB2
-41: SCR
-42: CSI0
-43: CSI1
-44: LCDCTRL0
-45: LCDCTRL1
-46: MP
-47: DEFEBE0
-48: DEFEBE1
-49: PMU
-50: SPI3
-51: TZASC
-52: PATA
-53: VE
-54: SS
-55: EMAC
-56: SATA
-57: GPS
-58: HDMI
-59: TVE
-60: ACE
-61: TVD
-62: PS2_0
-63: PS2_1
-64: USB3
-65: USB4
-66: PLE_PFM
-67: TIMER4
-68: TIMER5
-69: GPU_GP
-70: GPU_GPMMU
-71: GPU_PP0
-72: GPU_PPMMU0
-73: GPU_PMU
-74: GPU_RSV0
-75: GPU_RSV1
-76: GPU_RSV2
-77: GPU_RSV3
-78: GPU_RSV4
-79: GPU_RSV5
-80: GPU_RSV6
-82: SYNC_TIMER0
-83: SYNC_TIMER1
+For the valid interrupt sources for your SoC, see the documentation in
+sunxi/<soc>.txt
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt b/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt
new file mode 100644
index 000000000000..76b98c834499
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt
@@ -0,0 +1,89 @@
+Allwinner A10 (sun4i) interrupt sources
+---------------------------------------
+
+The interrupt sources available for the Allwinner A10 SoC are the
+following one:
+
+0: ENMI
+1: UART0
+2: UART1
+3: UART2
+4: UART3
+5: IR0
+6: IR1
+7: I2C0
+8: I2C1
+9: I2C2
+10: SPI0
+11: SPI1
+12: SPI2
+13: SPDIF
+14: AC97
+15: TS
+16: I2S
+17: UART4
+18: UART5
+19: UART6
+20: UART7
+21: KEYPAD
+22: TIMER0
+23: TIMER1
+24: TIMER2
+25: TIMER3
+26: CAN
+27: DMA
+28: PIO
+29: TOUCH_PANEL
+30: AUDIO_CODEC
+31: LRADC
+32: MMC0
+33: MMC1
+34: MMC2
+35: MMC3
+36: MEMSTICK
+37: NAND
+38: USB0
+39: USB1
+40: USB2
+41: SCR
+42: CSI0
+43: CSI1
+44: LCDCTRL0
+45: LCDCTRL1
+46: MP
+47: DEFEBE0
+48: DEFEBE1
+49: PMU
+50: SPI3
+51: TZASC
+52: PATA
+53: VE
+54: SS
+55: EMAC
+56: SATA
+57: GPS
+58: HDMI
+59: TVE
+60: ACE
+61: TVD
+62: PS2_0
+63: PS2_1
+64: USB3
+65: USB4
+66: PLE_PFM
+67: TIMER4
+68: TIMER5
+69: GPU_GP
+70: GPU_GPMMU
+71: GPU_PP0
+72: GPU_PPMMU0
+73: GPU_PMU
+74: GPU_RSV0
+75: GPU_RSV1
+76: GPU_RSV2
+77: GPU_RSV3
+78: GPU_RSV4
+79: GPU_RSV5
+80: GPU_RSV6
+82: SYNC_TIMER0
+83: SYNC_TIMER1
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt b/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt
new file mode 100644
index 000000000000..2ec3b5ce1a0b
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt
@@ -0,0 +1,55 @@
+Allwinner A13 (sun5i) interrupt sources
+---------------------------------------
+
+The interrupt sources available for the Allwinner A13 SoC are the
+following one:
+
+0: ENMI
+2: UART1
+4: UART3
+5: IR
+7: I2C0
+8: I2C1
+9: I2C2
+10: SPI0
+11: SPI1
+12: SPI2
+22: TIMER0
+23: TIMER1
+24: TIMER2
+25: TIMER3
+27: DMA
+28: PIO
+29: TOUCH_PANEL
+30: AUDIO_CODEC
+31: LRADC
+32: MMC0
+33: MMC1
+34: MMC2
+37: NAND
+38: USB OTG
+39: USB EHCI
+40: USB OHCI
+42: CSI
+44: LCDCTRL
+47: DEFEBE
+49: PMU
+53: VE
+54: SS
+66: PLE_PFM
+67: TIMER4
+68: TIMER5
+69: GPU_GP
+70: GPU_GPMMU
+71: GPU_PP0
+72: GPU_PPMMU0
+73: GPU_PMU
+74: GPU_RSV0
+75: GPU_RSV1
+76: GPU_RSV2
+77: GPU_RSV3
+78: GPU_RSV4
+79: GPU_RSV5
+80: GPU_RSV6
+82: SYNC_TIMER0
+83: SYNC_TIMER1
diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
new file mode 100644
index 000000000000..f8d405897a94
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
@@ -0,0 +1,221 @@
+* Marvell EBU PCIe interfaces
+
+Mandatory properties:
+- compatible: one of the following values:
+    marvell,armada-370-pcie
+    marvell,armada-xp-pcie
+    marvell,kirkwood-pcie
+- #address-cells, set to <3>
+- #size-cells, set to <2>
+- #interrupt-cells, set to <1>
+- bus-range: PCI bus numbers covered
+- device_type, set to "pci"
+- ranges: ranges for the PCI memory and I/O regions, as well as the
+  MMIO registers to control the PCIe interfaces.
+
+In addition, the Device Tree node must have sub-nodes describing each
+PCIe interface, having the following mandatory properties:
+- reg: used only for interrupt mapping, so only the first four bytes
+  are used to refer to the correct bus number and device number.
+- assigned-addresses: reference to the MMIO registers used to control
+  this PCIe interface.
+- clocks: the clock associated to this PCIe interface
+- marvell,pcie-port: the physical PCIe port number
+- status: either "disabled" or "okay"
+- device_type, set to "pci"
+- #address-cells, set to <3>
+- #size-cells, set to <2>
+- #interrupt-cells, set to <1>
+- ranges, empty property.
+- interrupt-map-mask and interrupt-map, standard PCI properties to
+  define the mapping of the PCIe interface to interrupt numbers.
+
+and the following optional properties:
+- marvell,pcie-lane: the physical PCIe lane number, for ports having
+  multiple lanes. If this property is not found, we assume that the
+  value is 0.
+
+Example:
+
+pcie-controller {
+        compatible = "marvell,armada-xp-pcie";
+        status = "disabled";
+        device_type = "pci";
+
+        #address-cells = <3>;
+        #size-cells = <2>;
+
+        bus-range = <0x00 0xff>;
+
+        ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */
+                  0x82000000 0 0xd0042000 0xd0042000 0 0x00002000   /* Port 2.0 registers */
+                  0x82000000 0 0xd0044000 0xd0044000 0 0x00002000   /* Port 0.1 registers */
+                  0x82000000 0 0xd0048000 0xd0048000 0 0x00002000   /* Port 0.2 registers */
+                  0x82000000 0 0xd004c000 0xd004c000 0 0x00002000   /* Port 0.3 registers */
+                  0x82000000 0 0xd0080000 0xd0080000 0 0x00002000   /* Port 1.0 registers */
+                  0x82000000 0 0xd0082000 0xd0082000 0 0x00002000   /* Port 3.0 registers */
+                  0x82000000 0 0xd0084000 0xd0084000 0 0x00002000   /* Port 1.1 registers */
+                  0x82000000 0 0xd0088000 0xd0088000 0 0x00002000   /* Port 1.2 registers */
+                  0x82000000 0 0xd008c000 0xd008c000 0 0x00002000   /* Port 1.3 registers */
+                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+
+        pcie@1,0 {
+                device_type = "pci";
+                assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
+                reg = <0x0800 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                ranges;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &mpic 58>;
+                marvell,pcie-port = <0>;
+                marvell,pcie-lane = <0>;
+                clocks = <&gateclk 5>;
+                status = "disabled";
+        };
+
+        pcie@2,0 {
+                device_type = "pci";
+                assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
+                reg = <0x1000 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                ranges;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &mpic 59>;
+                marvell,pcie-port = <0>;
+                marvell,pcie-lane = <1>;
+                clocks = <&gateclk 6>;
+                status = "disabled";
+        };
+
+        pcie@3,0 {
+                device_type = "pci";
+                assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
+                reg = <0x1800 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                ranges;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &mpic 60>;
+                marvell,pcie-port = <0>;
+                marvell,pcie-lane = <2>;
+                clocks = <&gateclk 7>;
+                status = "disabled";
+        };
+
+        pcie@4,0 {
+                device_type = "pci";
+                assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
+                reg = <0x2000 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                ranges;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &mpic 61>;
+                marvell,pcie-port = <0>;
+                marvell,pcie-lane = <3>;
+                clocks = <&gateclk 8>;
+                status = "disabled";
+        };
+
+        pcie@5,0 {
+                device_type = "pci";
+                assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
+                reg = <0x2800 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                ranges;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &mpic 62>;
+                marvell,pcie-port = <1>;
+                marvell,pcie-lane = <0>;
+                clocks = <&gateclk 9>;
+                status = "disabled";
+        };
+
+        pcie@6,0 {
+                device_type = "pci";
+                assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
+                reg = <0x3000 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                ranges;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &mpic 63>;
+                marvell,pcie-port = <1>;
+                marvell,pcie-lane = <1>;
+                clocks = <&gateclk 10>;
+                status = "disabled";
+        };
+
+        pcie@7,0 {
+                device_type = "pci";
+                assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
+                reg = <0x3800 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                ranges;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &mpic 64>;
+                marvell,pcie-port = <1>;
+                marvell,pcie-lane = <2>;
+                clocks = <&gateclk 11>;
+                status = "disabled";
+        };
+
+        pcie@8,0 {
+                device_type = "pci";
+                assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
+                reg = <0x4000 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                ranges;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &mpic 65>;
+                marvell,pcie-port = <1>;
+                marvell,pcie-lane = <3>;
+                clocks = <&gateclk 12>;
+                status = "disabled";
+        };
+        pcie@9,0 {
+                device_type = "pci";
+                assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
+                reg = <0x4800 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                ranges;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &mpic 99>;
+                marvell,pcie-port = <2>;
+                marvell,pcie-lane = <0>;
+                clocks = <&gateclk 26>;
+                status = "disabled";
+        };
+
+        pcie@10,0 {
+                device_type = "pci";
+                assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
+                reg = <0x5000 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                ranges;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &mpic 103>;
+                marvell,pcie-port = <3>;
+                marvell,pcie-lane = <0>;
+                clocks = <&gateclk 27>;
+                status = "disabled";
+        };
+};
diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt
new file mode 100644
index 000000000000..41aeed38926d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/pci.txt
@@ -0,0 +1,9 @@
+PCI bus bridges have standardized Device Tree bindings:
+
+PCI Bus Binding to: IEEE Std 1275-1994
+http://www.openfirmware.org/ofwg/bindings/pci/pci2_1.pdf
+
+And for the interrupt mapping part:
+
+Open Firmware Recommended Practice: Interrupt Mapping
+http://www.openfirmware.org/1275/practice/imap/imap0_9d.pdf
diff --git a/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt b/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt
new file mode 100644
index 000000000000..30b364e504ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt
@@ -0,0 +1,15 @@
+V3 Semiconductor V360 EPC PCI bridge
+
+This bridge is found in the ARM Integrator/AP (Application Platform)
+
+Integrator-specific notes:
+
+- syscon: should contain a link to the syscon device node (since
+  on the Integrator, some registers in the syscon are required to
+  operate the V3).
+
+V360 EPC specific notes:
+
+- reg: should contain the base address of the V3 adapter.
+- interrupts: should contain a reference to the V3 error interrupt
+  as routed on the system.
diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
index 2a3feabd3b22..34c1505774bf 100644
--- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
@@ -1,7 +1,7 @@
 Atmel AT91RM9200 Real Time Clock
 
 Required properties:
-- compatible: should be: "atmel,at91rm9200-rtc"
+- compatible: should be: "atmel,at91rm9200-rtc" or "atmel,at91sam9x5-rtc"
 - reg: physical base address of the controller and length of memory mapped
   region.
 - interrupts: rtc alarm/event interrupt
diff --git a/Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt b/Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt
new file mode 100644
index 000000000000..9499bc8ee9e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt
@@ -0,0 +1,18 @@
+ST-Ericsson U300 apptimer
+
+Required properties:
+
+- compatible : should be "stericsson,u300-apptimer"
+- reg : Specifies base physical address and size of the registers.
+- interrupts : A list of 4 interrupts; one for each subtimer. These
+  are, in order: OS (operating system), DD (device driver) both
+  adopted for EPOC/Symbian with two specific IRQs for these tasks,
+  then GP1 and GP2, which are general-purpose timers.
+
+Example:
+
+timer {
+        compatible = "stericsson,u300-apptimer";
+        reg = <0xc0014000 0x1000>;
+        interrupts = <24 25 26 27>;
+};
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 6931c4348d24..d247d1003987 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -59,6 +59,7 @@ ste	ST-Ericsson
 stericsson      ST-Ericsson
 ti      Texas Instruments
 toshiba Toshiba Corporation
+v3      V3 Semiconductor
 via     VIA Technologies, Inc.
 wlf     Wolfson Microelectronics
 wm      Wondermedia Technologies, Inc.
diff --git a/Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt b/Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt
new file mode 100644
index 000000000000..8ffb88e39e76
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt
@@ -0,0 +1,19 @@
+ST-Ericsson COH 901 327 Watchdog timer
+
+Required properties:
+- compatible: must be "stericsson,coh901327".
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- interrupts: the interrupt used for the watchdog timeout warning.
+
+Optional properties:
+- timeout-sec: contains the watchdog timeout in seconds.
+
+Example:
+
+watchdog: watchdog@c0012000 {
+        compatible = "stericsson,coh901327";
+        reg = <0xc0012000 0x1000>;
+        interrupts = <3>;
+        timeout-sec = <60>;
+};
diff --git a/Documentation/dmatest.txt b/Documentation/dmatest.txt
index 279ac0a8c5b1..132a094c7bc3 100644
--- a/Documentation/dmatest.txt
+++ b/Documentation/dmatest.txt
@@ -34,7 +34,7 @@ command:
 After a while you will start to get messages about current status or error like
 in the original code.
 
-Note that running a new test will stop any in progress test.
+Note that running a new test will not stop any in progress test.
 
 The following command should return actual state of the test.
         % cat /sys/kernel/debug/dmatest/run
@@ -52,8 +52,8 @@ To wait for test done the user may perform a busy loop that checks the state.
 
 The module parameters that is supplied to the kernel command line will be used
 for the first performed test. After user gets a control, the test could be
-interrupted or re-run with same or different parameters. For the details see
-the above section "Part 2 - When dmatest is built as a module..."
+re-run with the same or different parameters. For the details see the above
+section "Part 2 - When dmatest is built as a module..."
 
 In both cases the module parameters are used as initial values for the test case.
 You always could check them at run-time by running
diff --git a/Documentation/filesystems/xfs.txt b/Documentation/filesystems/xfs.txt
index 3e4b3dd1e046..83577f0232a0 100644
--- a/Documentation/filesystems/xfs.txt
+++ b/Documentation/filesystems/xfs.txt
@@ -33,6 +33,9 @@ When mounting an XFS filesystem, the following options are accepted.
         removing extended attributes) the on-disk superblock feature
         bit field will be updated to reflect this format being in use.
 
+        CRC enabled filesystems always use the attr2 format, and so
+        will reject the noattr2 mount option if it is set.
+
   barrier
         Enables the use of block layer write barriers for writes into
         the journal and unwritten extent conversion.  This allows for
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 6e3b18a8afc6..2fe6e767b3d6 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -3351,9 +3351,6 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
                         plus one apbt timer for broadcast timer.
                         x86_mrst_timer=apbt_only | lapic_and_apbt
 
-        xd=             [HW,XT] Original XT pre-IDE (RLL encoded) disks.
-        xd_geo=         See header of drivers/block/xd.c.
-
         xen_emul_unplug=                [HW,X86,XEN]
                         Unplug Xen emulated devices
                         Format: [unplug0,][unplug1]
diff --git a/Documentation/m68k/kernel-options.txt b/Documentation/m68k/kernel-options.txt
index 97d45f276fe6..eaf32a1fd0b1 100644
--- a/Documentation/m68k/kernel-options.txt
+++ b/Documentation/m68k/kernel-options.txt
@@ -80,8 +80,6 @@ Valid names are:
   /dev/sdd: -> 0x0830 (forth SCSI disk)
   /dev/sde: -> 0x0840 (fifth SCSI disk)
   /dev/fd : -> 0x0200 (floppy disk)
-  /dev/xda: -> 0x0c00 (first XT disk, unused in Linux/m68k)
-  /dev/xdb: -> 0x0c40 (second XT disk, unused in Linux/m68k)
 
   The name must be followed by a decimal number, that stands for the
 partition number. Internally, the value of the number is just
diff --git a/Documentation/powerpc/transactional_memory.txt b/Documentation/powerpc/transactional_memory.txt
index c907be41d60f..dc23e58ae264 100644
--- a/Documentation/powerpc/transactional_memory.txt
+++ b/Documentation/powerpc/transactional_memory.txt
@@ -147,6 +147,25 @@ Example signal handler:
       fix_the_problem(ucp->dar);
     }
 
+When in an active transaction that takes a signal, we need to be careful with
+the stack.  It's possible that the stack has moved back up after the tbegin.
+The obvious case here is when the tbegin is called inside a function that
+returns before a tend.  In this case, the stack is part of the checkpointed
+transactional memory state.  If we write over this non transactionally or in
+suspend, we are in trouble because if we get a tm abort, the program counter and
+stack pointer will be back at the tbegin but our in memory stack won't be valid
+anymore.
+
+To avoid this, when taking a signal in an active transaction, we need to use
+the stack pointer from the checkpointed state, rather than the speculated
+state.  This ensures that the signal context (written tm suspended) will be
+written below the stack required for the rollback.  The transaction is aborted
+becuase of the treclaim, so any memory written between the tbegin and the
+signal will be rolled back anyway.
+
+For signals taken in non-TM or suspended mode, we use the
+normal/non-checkpointed stack pointer.
+
 
 Failure cause codes used by kernel
 ==================================
@@ -155,14 +174,18 @@ These are defined in <asm/reg.h>, and distinguish different reasons why the
 kernel aborted a transaction:
 
  TM_CAUSE_RESCHED       Thread was rescheduled.
+ TM_CAUSE_TLBI          Software TLB invalide.
  TM_CAUSE_FAC_UNAV      FP/VEC/VSX unavailable trap.
  TM_CAUSE_SYSCALL       Currently unused; future syscalls that must abort
                         transactions for consistency will use this.
  TM_CAUSE_SIGNAL        Signal delivered.
  TM_CAUSE_MISC          Currently unused.
+ TM_CAUSE_ALIGNMENT     Alignment fault.
+ TM_CAUSE_EMULATE       Emulation that touched memory.
 
-These can be checked by the user program's abort handler as TEXASR[0:7].
-
+These can be checked by the user program's abort handler as TEXASR[0:7].  If
+bit 7 is set, it indicates that the error is consider persistent.  For example
+a TM_CAUSE_ALIGNMENT will be persistent while a TM_CAUSE_RESCHED will not.q
 
 GDB
 ===
diff --git a/MAINTAINERS b/MAINTAINERS
index fd3a495a0005..5be702cc8449 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2890,8 +2890,8 @@ F:	drivers/media/dvb-frontends/ec100*
 
 ECRYPT FILE SYSTEM
 M:      Tyler Hicks <tyhicks@canonical.com>
-M:      Dustin Kirkland <dustin.kirkland@gazzang.com>
 L:      ecryptfs@vger.kernel.org
+W:      http://ecryptfs.org
 W:      https://launchpad.net/ecryptfs
 S:      Supported
 F:      Documentation/filesystems/ecryptfs.txt
@@ -3322,11 +3322,12 @@ F:	drivers/net/wan/dlci.c
 F:      drivers/net/wan/sdla.c
 
 FRAMEBUFFER LAYER
-M:      Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
+M:      Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
+M:      Tomi Valkeinen <tomi.valkeinen@ti.com>
 L:      linux-fbdev@vger.kernel.org
 W:      http://linux-fbdev.sourceforge.net/
 Q:      http://patchwork.kernel.org/project/linux-fbdev/list/
-T:      git git://github.com/schandinat/linux-2.6.git fbdev-next
+T:      git git://git.kernel.org/pub/scm/linux/kernel/git/plagnioj/linux-fbdev.git
 S:      Maintained
 F:      Documentation/fb/
 F:      Documentation/devicetree/bindings/fb/
@@ -4447,6 +4448,16 @@ S:	Maintained
 F:      drivers/scsi/*iscsi*
 F:      include/scsi/*iscsi*
 
+ISCSI EXTENSIONS FOR RDMA (ISER) INITIATOR
+M:      Or Gerlitz <ogerlitz@mellanox.com>
+M:      Roi Dayan <roid@mellanox.com>
+L:      linux-rdma@vger.kernel.org
+S:      Supported
+W:      http://www.openfabrics.org
+W:      www.open-iscsi.org
+Q:      http://patchwork.kernel.org/project/linux-rdma/list/
+F:      drivers/infiniband/ulp/iser
+
 ISDN SUBSYSTEM
 M:      Karsten Keil <isdn@linux-pingi.de>
 L:      isdn4linux@listserv.isdn4linux.de (subscribers-only)
@@ -5755,7 +5766,7 @@ M:	Matthew Wilcox <willy@linux.intel.com>
 L:      linux-nvme@lists.infradead.org
 T:      git git://git.infradead.org/users/willy/linux-nvme.git
 S:      Supported
-F:      drivers/block/nvme.c
+F:      drivers/block/nvme*
 F:      include/linux/nvme.h
 
 OMAP SUPPORT
@@ -6087,7 +6098,15 @@ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/jejb/parisc-2.6.git
 T:      git git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux.git
 S:      Maintained
 F:      arch/parisc/
+F:      Documentation/parisc/
 F:      drivers/parisc/
+F:      drivers/char/agp/parisc-agp.c
+F:      drivers/input/serio/gscps2.c
+F:      drivers/parport/parport_gsc.*
+F:      drivers/tty/serial/8250/8250_gsc.c
+F:      drivers/video/sti*
+F:      drivers/video/console/sti*
+F:      drivers/video/logo/logo_parisc*
 
 PC87360 HARDWARE MONITORING DRIVER
 M:      Jim Cromie <jim.cromie@gmail.com>
@@ -7605,7 +7624,7 @@ F:	drivers/clk/spear/
 SPI SUBSYSTEM
 M:      Mark Brown <broonie@kernel.org>
 M:      Grant Likely <grant.likely@linaro.org>
-L:      spi-devel-general@lists.sourceforge.net
+L:      linux-spi@vger.kernel.org
 T:      git git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git
 Q:      http://patchwork.kernel.org/project/spi-devel-general/list/
 S:      Maintained
@@ -8985,7 +9004,7 @@ S:	Maintained
 F:      drivers/net/wireless/wl3501*
 
 WM97XX TOUCHSCREEN DRIVERS
-M:      Mark Brown <broonie@opensource.wolfsonmicro.com>
+M:      Mark Brown <broonie@kernel.org>
 M:      Liam Girdwood <lrg@slimlogic.co.uk>
 L:      linux-input@vger.kernel.org
 T:      git git://opensource.wolfsonmicro.com/linux-2.6-touch
@@ -8995,7 +9014,6 @@ F:	drivers/input/touchscreen/*wm97*
 F:      include/linux/wm97xx.h
 
 WOLFSON MICROELECTRONICS DRIVERS
-M:      Mark Brown <broonie@opensource.wolfsonmicro.com>
 L:      patches@opensource.wolfsonmicro.com
 T:      git git://opensource.wolfsonmicro.com/linux-2.6-asoc
 T:      git git://opensource.wolfsonmicro.com/linux-2.6-audioplus
diff --git a/Makefile b/Makefile
index 73e20dba55c1..c6863b55f7c7 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 VERSION = 3
 PATCHLEVEL = 10
 SUBLEVEL = 0
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc6
 NAME = Unicycling Gorilla
 
 # *DOCUMENTATION*
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 94d3491ae40a..ccd78c912cbf 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -9,7 +9,7 @@ config ARM
         select BUILDTIME_EXTABLE_SORT if MMU
         select CPU_PM if (SUSPEND || CPU_IDLE)
         select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
-        select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
+        select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
         select GENERIC_IRQ_PROBE
         select GENERIC_IRQ_SHOW
@@ -366,11 +366,12 @@ config ARCH_CLPS711X
         select ARCH_REQUIRE_GPIOLIB
         select AUTO_ZRELADDR
         select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
         select COMMON_CLK
         select CPU_ARM720T
         select GENERIC_CLOCKEVENTS
+        select MFD_SYSCON
         select MULTI_IRQ_HANDLER
-        select NEED_MACH_MEMORY_H
         select SPARSE_IRQ
         help
           Support for Cirrus Logic 711x/721x/731x based boards.
@@ -502,6 +503,7 @@ config ARCH_DOVE
 
 config ARCH_KIRKWOOD
         bool "Marvell Kirkwood"
+        select ARCH_HAS_CPUFREQ
         select ARCH_REQUIRE_GPIOLIB
         select CPU_FEROCEON
         select GENERIC_CLOCKEVENTS
@@ -645,7 +647,7 @@ config ARCH_SHMOBILE
         select MULTI_IRQ_HANDLER
         select NEED_MACH_MEMORY_H
         select NO_IOPORT
-        select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
+        select PINCTRL
         select PM_GENERIC_DOMAINS if PM
         select SPARSE_IRQ
         help
@@ -695,6 +697,7 @@ config ARCH_S3C24XX
         select CLKDEV_LOOKUP
         select CLKSRC_MMIO
         select GENERIC_CLOCKEVENTS
+        select GPIO_SAMSUNG
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -702,6 +705,7 @@ config ARCH_S3C24XX
         select MULTI_IRQ_HANDLER
         select NEED_MACH_GPIO_H
         select NEED_MACH_IO_H
+        select SAMSUNG_ATAGS
         help
           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
@@ -717,6 +721,7 @@ config ARCH_S3C64XX
         select CLKSRC_MMIO
         select CPU_V6
         select GENERIC_CLOCKEVENTS
+        select GPIO_SAMSUNG
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -726,6 +731,7 @@ config ARCH_S3C64XX
         select PLAT_SAMSUNG
         select S3C_DEV_NAND
         select S3C_GPIO_TRACK
+        select SAMSUNG_ATAGS
         select SAMSUNG_CLKSRC
         select SAMSUNG_GPIOLIB_4BIT
         select SAMSUNG_IRQ_VIC_TIMER
@@ -739,11 +745,13 @@ config ARCH_S5P64X0
         select CLKSRC_MMIO
         select CPU_V6
         select GENERIC_CLOCKEVENTS
+        select GPIO_SAMSUNG
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
         select HAVE_S3C_RTC if RTC_CLASS
         select NEED_MACH_GPIO_H
+        select SAMSUNG_ATAGS
         help
           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
           SMDK6450.
@@ -755,11 +763,13 @@ config ARCH_S5PC100
         select CLKSRC_MMIO
         select CPU_V7
         select GENERIC_CLOCKEVENTS
+        select GPIO_SAMSUNG
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
         select HAVE_S3C_RTC if RTC_CLASS
         select NEED_MACH_GPIO_H
+        select SAMSUNG_ATAGS
         help
           Samsung S5PC100 series based systems
 
@@ -772,12 +782,14 @@ config ARCH_S5PV210
         select CLKSRC_MMIO
         select CPU_V7
         select GENERIC_CLOCKEVENTS
+        select GPIO_SAMSUNG
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
         select HAVE_S3C_RTC if RTC_CLASS
         select NEED_MACH_GPIO_H
         select NEED_MACH_MEMORY_H
+        select SAMSUNG_ATAGS
         help
           Samsung S5PV210/S5PC110 series based systems
 
@@ -785,7 +797,9 @@ config ARCH_EXYNOS
         bool "Samsung EXYNOS"
         select ARCH_HAS_CPUFREQ
         select ARCH_HAS_HOLES_MEMORYMODEL
+        select ARCH_REQUIRE_GPIOLIB
         select ARCH_SPARSEMEM_ENABLE
+        select ARM_GIC
         select CLKDEV_LOOKUP
         select COMMON_CLK
         select CPU_V7
@@ -794,8 +808,9 @@ config ARCH_EXYNOS
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
         select HAVE_S3C_RTC if RTC_CLASS
-        select NEED_MACH_GPIO_H
         select NEED_MACH_MEMORY_H
+        select SPARSE_IRQ
+        select USE_OF
         help
           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 
@@ -813,23 +828,6 @@ config ARCH_SHARK
           Support for the StrongARM based Digital DNARD machine, also known
           as "Shark" (<http://www.shark-linux.de/shark.html>).
 
-config ARCH_U300
-        bool "ST-Ericsson U300 Series"
-        depends on MMU
-        select ARCH_REQUIRE_GPIOLIB
-        select ARM_AMBA
-        select ARM_PATCH_PHYS_VIRT
-        select ARM_VIC
-        select CLKDEV_LOOKUP
-        select CLKSRC_MMIO
-        select COMMON_CLK
-        select CPU_ARM926T
-        select GENERIC_CLOCKEVENTS
-        select HAVE_TCM
-        select SPARSE_IRQ
-        help
-          Support for ST-Ericsson U300 series mobile platforms.
-
 config ARCH_DAVINCI
         bool "TI DaVinci"
         select ARCH_HAS_HOLES_MEMORYMODEL
@@ -840,6 +838,7 @@ config ARCH_DAVINCI
         select GENERIC_IRQ_CHIP
         select HAVE_IDE
         select NEED_MACH_GPIO_H
+        select TI_PRIV_EDMA
         select USE_OF
         select ZONE_DMA
         help
@@ -948,6 +947,8 @@ source "arch/arm/mach-iop13xx/Kconfig"
 
 source "arch/arm/mach-ixp4xx/Kconfig"
 
+source "arch/arm/mach-keystone/Kconfig"
+
 source "arch/arm/mach-kirkwood/Kconfig"
 
 source "arch/arm/mach-ks8695/Kconfig"
@@ -1562,6 +1563,7 @@ config ARCH_NR_GPIO
         int
         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
         default 512 if SOC_OMAP5
+        default 512 if ARCH_KEYSTONE
         default 392 if ARCH_U8500
         default 352 if ARCH_VT8500
         default 288 if ARCH_SUNXI
@@ -1587,7 +1589,7 @@ config SCHED_HRTICK
 
 config THUMB2_KERNEL
         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
-        depends on CPU_V7 && !CPU_V6 && !CPU_V6K
+        depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
         default y if CPU_THUMBONLY
         select AEABI
         select ARM_ASM_UNIFIED
@@ -2042,7 +2044,7 @@ config CRASH_DUMP
 
 config AUTO_ZRELADDR
         bool "Auto calculation of the decompressed kernel image address"
-        depends on !ZBOOT_ROM && !ARCH_U300
+        depends on !ZBOOT_ROM
         help
           ZRELADDR is the physical address where the decompressed kernel
           image will be placed. If AUTO_ZRELADDR is selected, the address
diff --git a/arch/arm/Kconfig-nommu b/arch/arm/Kconfig-nommu
index 2cef8e13f9f8..c859495da480 100644
--- a/arch/arm/Kconfig-nommu
+++ b/arch/arm/Kconfig-nommu
@@ -28,7 +28,7 @@ config FLASH_SIZE
 config PROCESSOR_ID
         hex 'Hard wire the processor ID'
         default 0x00007700
-        depends on !CPU_CP15
+        depends on !(CPU_CP15 || CPU_V7M)
         help
           If processor has no CP15 register, this processor ID is
           used instead of the auto-probing which utilizes the register.
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 5cd90bfdddfe..ab95f07e1541 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -251,6 +251,27 @@ choice
                   Say Y here if you want kernel low-level debugging support
                   on i.MX6Q/DL.
 
+        config DEBUG_IMX6SL_UART
+                bool "i.MX6SL Debug UART"
+                depends on SOC_IMX6SL
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on i.MX6SL.
+
+        config DEBUG_KEYSTONE_UART0
+                bool "Kernel low-level debugging on KEYSTONE2 using UART0"
+                depends on ARCH_KEYSTONE
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to UART0 serial port on KEYSTONE2 devices.
+
+        config DEBUG_KEYSTONE_UART1
+                bool "Kernel low-level debugging on KEYSTONE2 using UART1"
+                depends on ARCH_KEYSTONE
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to UART1 serial port on KEYSTONE2 devices.
+
         config DEBUG_MMP_UART2
                 bool "Kernel low-level debugging message via MMP UART2"
                 depends on ARCH_MMP
@@ -303,12 +324,37 @@ choice
                   their output to the serial port on MSM 8960 devices.
 
         config DEBUG_MVEBU_UART
-                bool "Kernel low-level debugging messages via MVEBU UART"
+                bool "Kernel low-level debugging messages via MVEBU UART (old bootloaders)"
                 depends on ARCH_MVEBU
                 help
                   Say Y here if you want kernel low-level debugging support
                   on MVEBU based platforms.
 
+                  This option should be used with the old bootloaders
+                  that left the internal registers mapped at
+                  0xd0000000. As of today, this is the case on
+                  platforms such as the Globalscale Mirabox or the
+                  Plathome OpenBlocks AX3, when using the original
+                  bootloader.
+
+                  If the wrong DEBUG_MVEBU_UART* option is selected,
+                  when u-boot hands over to the kernel, the system
+                  silently crashes, with no serial output at all.
+
+        config DEBUG_MVEBU_UART_ALTERNATE
+                bool "Kernel low-level debugging messages via MVEBU UART (new bootloaders)"
+                depends on ARCH_MVEBU
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on MVEBU based platforms.
+
+                  This option should be used with the new bootloaders
+                  that remap the internal registers at 0xf1000000.
+
+                  If the wrong DEBUG_MVEBU_UART* option is selected,
+                  when u-boot hands over to the kernel, the system
+                  silently crashes, with no serial output at all.
+
         config DEBUG_NOMADIK_UART
                 bool "Kernel low-level debugging messages via NOMADIK UART"
                 depends on ARCH_NOMADIK
@@ -450,6 +496,13 @@ choice
                   Say Y here if you want the debug print routines to direct
                   their output to the uart1 port on SiRFmarco devices.
 
+        config DEBUG_U300_UART
+                bool "Kernel low-level debugging messages via U300 UART0"
+                depends on ARCH_U300
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the uart port on U300 devices.
+
         config DEBUG_UX500_UART
                 depends on ARCH_U8500
                 bool "Use Ux500 UART for low-level debug"
@@ -539,7 +592,8 @@ config DEBUG_IMX_UART_PORT
                                                 DEBUG_IMX35_UART || \
                                                 DEBUG_IMX51_UART || \
                                                 DEBUG_IMX53_UART || \
-                                                DEBUG_IMX6Q_UART
+                                                DEBUG_IMX6Q_UART || \
+                                                DEBUG_IMX6SL_UART
         default 1
         depends on ARCH_MXC
         help
@@ -664,8 +718,12 @@ config DEBUG_LL_INCLUDE
                                  DEBUG_IMX35_UART || \
                                  DEBUG_IMX51_UART || \
                                  DEBUG_IMX53_UART ||\
-                                 DEBUG_IMX6Q_UART
-        default "debug/mvebu.S" if DEBUG_MVEBU_UART
+                                 DEBUG_IMX6Q_UART || \
+                                 DEBUG_IMX6SL_UART
+        default "debug/keystone.S" if DEBUG_KEYSTONE_UART0 || \
+                                      DEBUG_KEYSTONE_UART1
+        default "debug/mvebu.S" if DEBUG_MVEBU_UART || \
+                                   DEBUG_MVEBU_UART_ALTERNATE
         default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART
         default "debug/nomadik.S" if DEBUG_NOMADIK_UART
         default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
@@ -677,6 +735,7 @@ config DEBUG_LL_INCLUDE
         default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
         default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
         default "debug/tegra.S" if DEBUG_TEGRA_UART
+        default "debug/u300.S" if DEBUG_U300_UART
         default "debug/ux500.S" if DEBUG_UX500_UART
         default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
                 DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 126313fcc594..daf19a86b8eb 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -59,6 +59,7 @@ comma = ,
 # Note that GCC does not numerically define an architecture version
 # macro, but instead defines a whole series of macros which makes
 # testing for a specific architecture or later rather impossible.
+arch-$(CONFIG_CPU_32v7M)        :=-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m
 arch-$(CONFIG_CPU_32v7)         :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
 arch-$(CONFIG_CPU_32v6)         :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
 # Only override the compiler option if ARMv6. The ARMv6K extensions are
@@ -195,9 +196,11 @@ machine-$(CONFIG_PLAT_SPEAR)		+= spear
 machine-$(CONFIG_ARCH_VIRT)             += virt
 machine-$(CONFIG_ARCH_ZYNQ)             += zynq
 machine-$(CONFIG_ARCH_SUNXI)            += sunxi
+machine-$(CONFIG_ARCH_KEYSTONE)         += keystone
 
 # Platform directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
+plat-$(CONFIG_ARCH_EXYNOS)      += samsung
 plat-$(CONFIG_ARCH_OMAP)        += omap
 plat-$(CONFIG_ARCH_S3C64XX)     += samsung
 plat-$(CONFIG_PLAT_IOP)         += iop
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 3580d57ea218..79e9bdbfc491 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -124,7 +124,7 @@ KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
 endif
 
 ccflags-y := -fpic -mno-single-pic-base -fno-builtin -I$(obj)
-asflags-y := -Wa,-march=all -DZIMAGE
+asflags-y := -DZIMAGE
 
 # Supply kernel BSS size to the decompressor via a linker symbol.
 KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \
diff --git a/arch/arm/boot/compressed/debug.S b/arch/arm/boot/compressed/debug.S
index 6e8382d5b7a4..5392ee63338f 100644
--- a/arch/arm/boot/compressed/debug.S
+++ b/arch/arm/boot/compressed/debug.S
@@ -1,6 +1,8 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
+#ifndef CONFIG_DEBUG_SEMIHOSTING
+
 #include CONFIG_DEBUG_LL_INCLUDE
 
 ENTRY(putc)
@@ -10,3 +12,29 @@ ENTRY(putc)
         busyuart r3, r1
         mov      pc, lr
 ENDPROC(putc)
+
+#else
+
+ENTRY(putc)
+        adr     r1, 1f
+        ldmia   r1, {r2, r3}
+        add     r2, r2, r1
+        ldr     r1, [r2, r3]
+        strb    r0, [r1]
+        mov     r0, #0x03               @ SYS_WRITEC
+   ARM( svc     #0x123456       )
+ THUMB( svc     #0xab           )
+        mov     pc, lr
+        .align  2
+1:      .word   _GLOBAL_OFFSET_TABLE_ - .
+        .word   semi_writec_buf(GOT)
+ENDPROC(putc)
+
+        .bss
+        .global semi_writec_buf
+        .type   semi_writec_buf, %object
+semi_writec_buf:
+        .space  4
+        .size   semi_writec_buf, 4
+
+#endif
diff --git a/arch/arm/boot/compressed/head-sa1100.S b/arch/arm/boot/compressed/head-sa1100.S
index 6179d94dd5c6..3115e313d9f6 100644
--- a/arch/arm/boot/compressed/head-sa1100.S
+++ b/arch/arm/boot/compressed/head-sa1100.S
@@ -11,6 +11,7 @@
 #include <asm/mach-types.h>
 
                 .section        ".start", "ax"
+                .arch   armv4
 
 __SA1100_start:
 
diff --git a/arch/arm/boot/compressed/head-shark.S b/arch/arm/boot/compressed/head-shark.S
index 089c560e07f1..92b56897ed64 100644
--- a/arch/arm/boot/compressed/head-shark.S
+++ b/arch/arm/boot/compressed/head-shark.S
@@ -18,6 +18,7 @@
         
                 .section        ".start", "ax"
 
+                .arch armv4
                 b       __beginning
         
 __ofw_data:     .long   0                               @ the number of memory blocks
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index fe4d9c3ad761..032a8d987148 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -11,6 +11,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
+        .arch   armv7-a
 /*
  * Debugging stuff
  *
@@ -805,8 +806,8 @@ call_cache_fn:	adr	r12, proc_types
                 .align  2
                 .type   proc_types,#object
 proc_types:
-                .word   0x00000000              @ old ARM ID
-                .word   0x0000f000
+                .word   0x41000000              @ old ARM ID
+                .word   0xff00f000
                 mov     pc, lr
  THUMB(         nop                             )
                 mov     pc, lr
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f0895c581a89..f9eae2f0ae5d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -64,6 +64,8 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
         integratorcp.dtb
 dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
 dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
+        kirkwood-db-88f6281.dtb \
+        kirkwood-db-88f6282.dtb \
         kirkwood-dns320.dtb \
         kirkwood-dns325.dtb \
         kirkwood-dockstar.dtb \
@@ -199,6 +201,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
         tegra114-pluto.dtb
 dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \
         versatile-pb.dtb
+dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
         vexpress-v2p-ca9.dtb \
         vexpress-v2p-ca15-tc1.dtb \
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 1460d9b88adf..8e1248f01fab 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -409,8 +409,8 @@
                         ti,hwmods = "gpmc";
                         reg = <0x50000000 0x2000>;
                         interrupts = <100>;
-                        num-cs = <7>;
-                        num-waitpins = <2>;
+                        gpmc,num-cs = <7>;
+                        gpmc,num-waitpins = <2>;
                         #address-cells = <2>;
                         #size-cells = <1>;
                         status = "disabled";
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 550eb772c30e..52a1f5efc086 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -80,7 +80,7 @@
 
                         sata@a0000 {
                                 compatible = "marvell,orion-sata";
-                                reg = <0xa0000 0x2400>;
+                                reg = <0xa0000 0x5000>;
                                 interrupts = <55>;
                                 clocks = <&gateclk 15>, <&gateclk 30>;
                                 clock-names = "0", "1";
@@ -96,7 +96,7 @@
 
                         ethernet@70000 {
                                 compatible = "marvell,armada-370-neta";
-                                reg = <0x70000 0x2500>;
+                                reg = <0x70000 0x4000>;
                                 interrupts = <8>;
                                 clocks = <&gateclk 4>;
                                 status = "disabled";
@@ -104,7 +104,7 @@
 
                         ethernet@74000 {
                                 compatible = "marvell,armada-370-neta";
-                                reg = <0x74000 0x2500>;
+                                reg = <0x74000 0x4000>;
                                 interrupts = <10>;
                                 clocks = <&gateclk 3>;
                                 status = "disabled";
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 3ee63d128e27..76db557adbe7 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -39,8 +39,9 @@
         };
 
         soc {
-                ranges = <0          0 0xd0000000 0x100000
-                          0xf0000000 0 0xf0000000 0x1000000>;
+                ranges = <0          0 0xd0000000 0x100000  /* Internal registers 1MiB */
+                          0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
+                          0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB  */>;
 
                 internal-regs {
                         serial@12000 {
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 6ab56bd35de9..488ca5eb9a55 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -107,7 +107,7 @@
 
                         ethernet@34000 {
                                 compatible = "marvell,armada-370-neta";
-                                reg = <0x34000 0x2500>;
+                                reg = <0x34000 0x4000>;
                                 interrupts = <14>;
                                 clocks = <&gateclk 1>;
                                 status = "disabled";
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 46b785064dd8..fdea75c73411 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -27,8 +27,9 @@
         };
 
         soc {
-                ranges = <0          0 0xd0000000 0x100000
-                          0xf0000000 0 0xf0000000 0x8000000>;
+                ranges = <0          0 0xd0000000 0x100000      /* Internal registers 1MiB */
+                          0xe0000000 0 0xe0000000 0x8100000     /* PCIe */
+                          0xf0000000 0 0xf0000000 0x8000000     /* Device Bus, NOR 128MiB   */>;
 
                 internal-regs {
                         serial@12000 {
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 5b902f9a3af2..1ee8540b0eba 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -88,7 +88,7 @@
 
                         ethernet@30000 {
                                 compatible = "marvell,armada-370-neta";
-                                reg = <0x30000 0x2500>;
+                                reg = <0x30000 0x4000>;
                                 interrupts = <12>;
                                 clocks = <&gateclk 2>;
                                 status = "disabled";
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index f0052dccf9a8..1e12aeff403b 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -44,6 +44,7 @@
                         reg = <0x7e201000 0x1000>;
                         interrupts = <2 25>;
                         clock-frequency = <3000000>;
+                        arm,primecell-periphid = <0x00241011>;
                 };
 
                 gpio: gpio {
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 98dfc3ea5c0b..0673524238a6 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -497,6 +497,21 @@
                 clock-names = "usbhost";
         };
 
+        usbphy@12130000 {
+                compatible = "samsung,exynos5250-usb2phy";
+                reg = <0x12130000 0x100>;
+                clocks = <&clock 1>, <&clock 285>;
+                clock-names = "ext_xtal", "usbhost";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                usbphy-sys {
+                        reg = <0x10040704 0x8>,
+                              <0x10050230 0x4>;
+                };
+        };
+
         amba {
                 #address-cells = <1>;
                 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index d2550e0bca24..701153992c69 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -141,8 +141,8 @@
                                 #size-cells = <0>;
                                 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
                                 reg = <0x43fa4000 0x4000>;
-                                clocks = <&clks 62>;
-                                clock-names = "ipg";
+                                clocks = <&clks 62>, <&clks 62>;
+                                clock-names = "ipg", "per";
                                 interrupts = <14>;
                                 status = "disabled";
                         };
@@ -182,8 +182,8 @@
                                 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
                                 reg = <0x50004000 0x4000>;
                                 interrupts = <0>;
-                                clocks = <&clks 80>;
-                                clock-names = "ipg";
+                                clocks = <&clks 80>, <&clks 80>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -210,8 +210,8 @@
                                 #size-cells = <0>;
                                 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
                                 reg = <0x50010000 0x4000>;
-                                clocks = <&clks 79>;
-                                clock-names = "ipg";
+                                clocks = <&clks 79>, <&clks 79>;
+                                clock-names = "ipg", "per";
                                 interrupts = <13>;
                                 status = "disabled";
                         };
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index ff4bd4873edf..75bd11386516 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -131,7 +131,7 @@
                                 compatible = "fsl,imx27-cspi";
                                 reg = <0x1000e000 0x1000>;
                                 interrupts = <16>;
-                                clocks = <&clks 53>, <&clks 0>;
+                                clocks = <&clks 53>, <&clks 53>;
                                 clock-names = "ipg", "per";
                                 status = "disabled";
                         };
@@ -142,7 +142,7 @@
                                 compatible = "fsl,imx27-cspi";
                                 reg = <0x1000f000 0x1000>;
                                 interrupts = <15>;
-                                clocks = <&clks 52>, <&clks 0>;
+                                clocks = <&clks 52>, <&clks 52>;
                                 clock-names = "ipg", "per";
                                 status = "disabled";
                         };
@@ -223,7 +223,7 @@
                                 compatible = "fsl,imx27-cspi";
                                 reg = <0x10017000 0x1000>;
                                 interrupts = <6>;
-                                clocks = <&clks 51>, <&clks 0>;
+                                clocks = <&clks 51>, <&clks 51>;
                                 clock-names = "ipg", "per";
                                 status = "disabled";
                         };
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 21bb786c5b31..53fdde69bbf4 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -631,7 +631,7 @@
                                 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
                                 reg = <0x83fc0000 0x4000>;
                                 interrupts = <38>;
-                                clocks = <&clks 55>, <&clks 0>;
+                                clocks = <&clks 55>, <&clks 55>;
                                 clock-names = "ipg", "per";
                                 status = "disabled";
                         };
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 845982eaac22..eb83aa039b8b 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -714,7 +714,7 @@
                                 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
                                 reg = <0x63fc0000 0x4000>;
                                 interrupts = <38>;
-                                clocks = <&clks 55>, <&clks 0>;
+                                clocks = <&clks 55>, <&clks 55>;
                                 clock-names = "ipg", "per";
                                 status = "disabled";
                         };
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
index c9c3fa344647..03f23b7a0ab5 100644
--- a/arch/arm/boot/dts/integratorap.dts
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -39,6 +39,47 @@
                 valid-mask = <0x003fffff>;
         };
 
+        pci: pciv3@62000000 {
+                compatible = "v3,v360epc-pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0x62000000 0x10000>;
+                interrupt-parent = <&pic>;
+                interrupts = <17>; /* Bus error IRQ */
+                ranges = <0x00000000 0 0x61000000 /* config space */
+                        0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */
+                        0x01000000 0 0x60000000 /* I/O space */
+                        0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */
+                        0x02000000 0 0x40000000 /* non-prefectable memory */
+                        0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */
+                        0x42000000 0 0x50000000 /* prefetchable memory */
+                        0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */
+                interrupt-map-mask = <0xf800 0 0 0x7>;
+                interrupt-map = <
+                /* IDSEL 9 */
+                0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
+                0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
+                0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
+                0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
+                /* IDSEL 10 */
+                0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
+                0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
+                0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
+                0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
+                /* IDSEL 11 */
+                0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
+                0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
+                0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
+                0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
+                /* IDSEL 12 */
+                0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
+                0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
+                0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
+                0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
+                >;
+        };
+
         fpga {
                 /*
                  * The Integator/AP predates the idea to have magic numbers
diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dts
new file mode 100644
index 000000000000..1334b42c6b77
--- /dev/null
+++ b/arch/arm/boot/dts/keystone.dts
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/include/ "skeleton.dtsi"
+
+/ {
+        model = "Texas Instruments Keystone 2 SoC";
+        compatible =  "ti,keystone-evm";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&gic>;
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        memory {
+                reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                interrupt-parent = <&gic>;
+
+                cpu@0 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+
+                cpu@2 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <2>;
+                };
+
+                cpu@3 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <3>;
+                };
+        };
+
+        gic: interrupt-controller {
+                compatible = "arm,cortex-a15-gic";
+                #interrupt-cells = <3>;
+                #size-cells = <0>;
+                #address-cells = <1>;
+                interrupt-controller;
+                reg = <0x0 0x02561000 0x0 0x1000>,
+                      <0x0 0x02562000 0x0 0x2000>;
+        };
+
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <1 13 0xf08>,
+                             <1 14 0xf08>,
+                             <1 11 0xf08>,
+                             <1 10 0x308>;
+        };
+
+        pmu {
+                compatible = "arm,cortex-a15-pmu";
+                interrupts = <0 20 0xf01>,
+                             <0 21 0xf01>,
+                             <0 22 0xf01>,
+                             <0 23 0xf01>;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "ti,keystone","simple-bus";
+                interrupt-parent = <&gic>;
+                ranges = <0x0 0x0 0x0 0xc0000000>;
+
+                rstctrl: reset-controller {
+                        compatible = "ti,keystone-reset";
+                        reg = <0x023100e8 4>;   /* pll reset control reg */
+                };
+
+                uart0: serial@02530c00 {
+                        compatible = "ns16550a";
+                        current-speed = <115200>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        reg = <0x02530c00 0x100>;
+                        clock-frequency = <133120000>;
+                        interrupts = <0 277 0xf01>;
+                };
+
+                uart1:  serial@02531000 {
+                        compatible = "ns16550a";
+                        current-speed = <115200>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        reg = <0x02531000 0x100>;
+                        clock-frequency = <133120000>;
+                        interrupts = <0 280 0xf01>;
+                };
+
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
index d6c9d65cbaeb..51376683dbcd 100644
--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -40,5 +40,36 @@
                                 marvell,function = "sdio";
                         };
                 };
+
+                pcie-controller {
+                        compatible = "marvell,kirkwood-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */
+                                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &intc 9>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gate_clk 2>;
+                                status = "disabled";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index 23991e45bc55..66a751ab5516 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -65,5 +65,53 @@
                         clocks = <&gate_clk 7>;
                         status = "disabled";
                 };
+
+                pcie-controller {
+                        compatible = "marvell,kirkwood-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */
+                                  0x82000000 0 0x00044000 0x00044000 0 0x00002000   /* Port 1.0 registers */
+                                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &intc 9>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gate_clk 2>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &intc 10>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gate_clk 18>;
+                                status = "disabled";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
new file mode 100644
index 000000000000..9d777edd1f36
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
@@ -0,0 +1,30 @@
+/*
+ * Marvell DB-88F6281-BP Development Board Setup
+ *
+ * Saeed Bishara <saeed@marvell.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/include/ "kirkwood-db.dtsi"
+/include/ "kirkwood-6281.dtsi"
+
+/ {
+        model = "Marvell DB-88F6281-BP Development Board";
+        compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+        ocp@f1000000 {
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
new file mode 100644
index 000000000000..f4c852886d23
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
@@ -0,0 +1,34 @@
+/*
+ * Marvell DB-88F6282-BP Development Board Setup
+ *
+ * Saeed Bishara <saeed@marvell.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/include/ "kirkwood-db.dtsi"
+/include/ "kirkwood-6282.dtsi"
+
+/ {
+        model = "Marvell DB-88F6282-BP Development Board";
+        compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood";
+
+        ocp@f1000000 {
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+
+                        pcie@2,0 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi
new file mode 100644
index 000000000000..c87cfb816120
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-db.dtsi
@@ -0,0 +1,89 @@
+/*
+ * Marvell DB-{88F6281,88F6282}-BP Development Board Setup
+ *
+ * Saeed Bishara <saeed@marvell.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file contains the definitions that are common between the 6281
+ * and 6282 variants of the Marvell Kirkwood Development Board.
+ */
+
+/include/ "kirkwood.dtsi"
+
+/ {
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>; /* 512 MB */
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        ocp@f1000000 {
+                pinctrl@10000 {
+                        pmx_sdio_gpios: pmx-sdio-gpios {
+                                marvell,pins = "mpp37", "mpp38";
+                                marvell,function = "gpio";
+                        };
+                };
+
+                serial@12000 {
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+
+                nand@3000000 {
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
+                        chip-delay = <25>;
+                        status = "okay";
+
+                        partition@0 {
+                                label = "uboot";
+                                reg = <0x0 0x100000>;
+                        };
+
+                        partition@100000 {
+                                label = "uImage";
+                                reg = <0x100000 0x400000>;
+                        };
+
+                        partition@500000 {
+                                label = "root";
+                                reg = <0x500000 0x1fb00000>;
+                        };
+                };
+
+                sata@80000 {
+                        nr-ports = <2>;
+                        status = "okay";
+                };
+
+                ehci@50000 {
+                        status = "okay";
+                };
+
+                mvsdio@90000 {
+                        pinctrl-0 = <&pmx_sdio_gpios>;
+                        pinctrl-names = "default";
+                        wp-gpios = <&gpio1 5 0>;
+                        cd-gpios = <&gpio1 6 0>;
+                        status = "okay";
+                };
+
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 12ccf74ac3c4..e591d5df769f 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -109,6 +109,14 @@
                                 reg = <0x980000 0x1f400000>;
                         };
                 };
+
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
         };
 
         gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index 758824118a9a..90501cf129bb 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -139,6 +139,14 @@
                         cd-gpios = <&gpio1 15 0>;
                         /* No WP GPIO */
                 };
+
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
         };
 
         gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
index 1ca66ab83ad6..0f852b40f5c1 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -111,6 +111,14 @@
                         status = "okay";
                         nr-ports = <2>;
                 };
+
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
         };
 
         gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
index a7412b937a8a..9ddf218f2cbd 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
@@ -176,6 +176,14 @@
                                 reg = <0x5040000 0x2fc0000>;
                         };
                 };
+
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
         };
 
         gpio_keys {
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index 8295c833887f..42648ab77c61 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -1,7 +1,8 @@
 /dts-v1/;
 
-/include/ "kirkwood-ts219.dtsi"
+/include/ "kirkwood.dtsi"
 /include/ "kirkwood-6281.dtsi"
+/include/ "kirkwood-ts219.dtsi"
 
 / {
         ocp@f1000000 {
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index df3f95dfba33..95ceeb93ba5a 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -1,7 +1,8 @@
 /dts-v1/;
 
-/include/ "kirkwood-ts219.dtsi"
+/include/ "kirkwood.dtsi"
 /include/ "kirkwood-6282.dtsi"
+/include/ "kirkwood-ts219.dtsi"
 
 / {
         ocp@f1000000 {
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
index 64ea27cb3298..7c022fd4aef7 100644
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -1,5 +1,3 @@
-/include/ "kirkwood.dtsi"
-
 / {
         model = "QNAP TS219 family";
         compatible = "qnap,ts219", "marvell,kirkwood";
@@ -74,5 +72,12 @@
                         status = "okay";
                         nr-ports = <2>;
                 };
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index fada7e6d24d8..7eef88f00fea 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -19,6 +19,7 @@
         ocp@f1000000 {
                 compatible = "simple-bus";
                 ranges = <0x00000000 0xf1000000 0x4000000
+                          0xe0000000 0xe0000000 0x8100000 /* PCIE */
                           0xf5000000 0xf5000000 0x0000400>;
                 #address-cells = <1>;
                 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 03bd60deb52b..eeb734e25709 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -56,9 +56,23 @@
         };
 };
 
+&omap4_pmx_wkup {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &twl6030_wkup_pins
+        >;
+
+        twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
+                pinctrl-single,pins = <
+                        0x14 0x2        /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */
+                >;
+        };
+};
+
 &omap4_pmx_core {
         pinctrl-names = "default";
         pinctrl-0 = <
+                        &twl6030_pins
                         &twl6040_pins
                         &mcpdm_pins
                         &mcbsp1_pins
@@ -66,6 +80,12 @@
                         &tpd12s015_pins
         >;
 
+        twl6030_pins: pinmux_twl6030_pins {
+                pinctrl-single,pins = <
+                        0x15e 0x4118    /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
+                >;
+        };
+
         twl6040_pins: pinmux_twl6040_pins {
                 pinctrl-single,pins = <
                         0xe0 0x3        /* hdq_sio.gpio_127 OUTPUT | MODE3 */
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index a35d9cd58063..98505a2ef162 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -142,9 +142,23 @@
         };
 };
 
+&omap4_pmx_wkup {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &twl6030_wkup_pins
+        >;
+
+        twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
+                pinctrl-single,pins = <
+                        0x14 0x2        /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */
+                >;
+        };
+};
+
 &omap4_pmx_core {
         pinctrl-names = "default";
         pinctrl-0 = <
+                        &twl6030_pins
                         &twl6040_pins
                         &mcpdm_pins
                         &dmic_pins
@@ -179,6 +193,12 @@
                 >;
         };
 
+        twl6030_pins: pinmux_twl6030_pins {
+                pinctrl-single,pins = <
+                        0x15e 0x4118    /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
+                >;
+        };
+
         twl6040_pins: pinmux_twl6040_pins {
                 pinctrl-single,pins = <
                         0xe0 0x3        /* hdq_sio.gpio_127 OUTPUT | MODE3 */
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 3dd7ff825828..635cae283011 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -538,6 +538,7 @@
                         interrupts = <0 41 0x4>;
                         ti,hwmods = "timer5";
                         ti,timer-dsp;
+                        ti,timer-pwm;
                 };
 
                 timer6: timer@4013a000 {
@@ -574,6 +575,7 @@
                         reg = <0x4803e000 0x80>;
                         interrupts = <0 45 0x4>;
                         ti,hwmods = "timer9";
+                        ti,timer-pwm;
                 };
 
                 timer10: timer@48086000 {
@@ -581,6 +583,7 @@
                         reg = <0x48086000 0x80>;
                         interrupts = <0 46 0x4>;
                         ti,hwmods = "timer10";
+                        ti,timer-pwm;
                 };
 
                 timer11: timer@48088000 {
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
new file mode 100644
index 000000000000..8a1032c1ffc9
--- /dev/null
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -0,0 +1,473 @@
+/*
+ * Device Tree for the ST-Ericsson U300 Machine and SoC
+ */
+
+/dts-v1/;
+/include/ "skeleton.dtsi"
+
+/ {
+        model = "ST-Ericsson U300";
+        compatible = "stericsson,u300";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        chosen {
+                bootargs = "root=/dev/ram0 console=ttyAMA0,115200n8 earlyprintk";
+        };
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
+        memory {
+                reg = <0x48000000 0x03c00000>;
+        };
+
+        s365 {
+                compatible = "stericsson,s365";
+                vana15-supply = <&ab3100_ldo_d_reg>;
+                syscon = <&syscon>;
+        };
+
+        syscon: syscon@c0011000 {
+                compatible = "stericsson,u300-syscon", "syscon";
+                reg = <0xc0011000 0x1000>;
+                clk32: app_32_clk@32k {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+                pll13: pll13@13M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                };
+                /* Slow bridge clocks under PLL13 */
+                slow_clk: slow_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <0>;
+                        clocks = <&pll13>;
+                };
+                uart0_clk: uart0_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <1>;
+                        clocks = <&slow_clk>;
+                };
+                gpio_clk: gpio_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <4>;
+                        clocks = <&slow_clk>;
+                };
+                rtc_clk: rtc_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <6>;
+                        clocks = <&slow_clk>;
+                };
+                apptimer_clk: app_tmr_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <7>;
+                        clocks = <&slow_clk>;
+                };
+                acc_tmr_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <8>;
+                        clocks = <&slow_clk>;
+                };
+                pll208: pll208@208M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <208000000>;
+                };
+                app208: app_208_clk@208M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <1>;
+                        clock-mult = <1>;
+                        clocks = <&pll208>;
+                };
+                cpu_clk@208M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <3>;
+                        clocks = <&app208>;
+                };
+                app104: app_104_clk@104M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clocks = <&pll208>;
+                };
+                semi_clk@104M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <9>;
+                        clocks = <&app104>;
+                };
+                app52: app_52_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clocks = <&pll208>;
+                };
+                /* AHB subsystem clocks */
+                ahb_clk: ahb_subsys_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <10>;
+                        clocks = <&app52>;
+                };
+                intcon_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <12>;
+                        clocks = <&ahb_clk>;
+                };
+                emif_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <5>;
+                        clocks = <&ahb_clk>;
+                };
+                dmac_clk: dmac_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <4>;
+                        clocks = <&app52>;
+                };
+                fsmc_clk: fsmc_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <6>;
+                        clocks = <&app52>;
+                };
+                xgam_clk: xgam_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <8>;
+                        clocks = <&app52>;
+                };
+                app26: app_26_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clocks = <&app52>;
+                };
+                /* Fast bridge  clocks */
+                fast_clk: fast_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <1>; /* Fast */
+                        clock-id = <0>;
+                        clocks = <&app26>;
+                };
+                i2c0_clk: i2c0_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <1>; /* Fast */
+                        clock-id = <1>;
+                        clocks = <&fast_clk>;
+                };
+                i2c1_clk: i2c1_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <1>; /* Fast */
+                        clock-id = <2>;
+                        clocks = <&fast_clk>;
+                };
+                mmc_pclk: mmc_p_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <1>; /* Fast */
+                        clock-id = <5>;
+                        clocks = <&fast_clk>;
+                };
+                mmc_mclk: mmc_mclk {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-mclk";
+                        clocks = <&mmc_pclk>;
+                };
+                spi_clk: spi_p_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <1>; /* Fast */
+                        clock-id = <6>;
+                        clocks = <&fast_clk>;
+                };
+        };
+
+        timer: timer@c0014000 {
+                compatible = "stericsson,u300-apptimer";
+                reg = <0xc0014000 0x1000>;
+                interrupt-parent = <&vica>;
+                interrupts = <24 25 26 27>;
+                clocks = <&apptimer_clk>;
+        };
+
+        gpio: gpio@c0016000 {
+                compatible = "stericsson,gpio-coh901";
+                reg = <0xc0016000 0x1000>;
+                interrupt-parent = <&vicb>;
+                interrupts = <0 1 2 18 21 22 23>;
+                clocks = <&gpio_clk>;
+                interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
+                                "gpio4", "gpio5", "gpio6";
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        pinctrl: pinctrl@c0011000 {
+                compatible = "stericsson,pinctrl-u300";
+                reg = <0xc0011000 0x1000>;
+        };
+
+        watchdog: watchdog@c0012000 {
+                compatible = "stericsson,coh901327";
+                reg = <0xc0012000 0x1000>;
+                interrupt-parent = <&vicb>;
+                interrupts = <3>;
+                clocks = <&clk32>;
+        };
+
+        rtc: rtc@c0017000 {
+                compatible = "stericsson,coh901331";
+                reg = <0xc0017000 0x1000>;
+                interrupt-parent = <&vicb>;
+                interrupts = <10>;
+                clocks = <&rtc_clk>;
+        };
+
+        dmac: dma-controller@c00020000 {
+                compatible = "stericsson,coh901318";
+                reg = <0xc0020000 0x1000>;
+                interrupt-parent = <&vica>;
+                interrupts = <2>;
+                #dma-cells = <1>;
+                dma-channels = <40>;
+                clocks = <&dmac_clk>;
+        };
+
+        /* A NAND flash of 128 MiB */
+        fsmc: flash@40000000 {
+                compatible = "stericsson,fsmc-nand";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x9f800000 0x1000>,      /* FSMC Register*/
+                        <0x80000000 0x4000>,    /* NAND Base DATA */
+                        <0x80020000 0x4000>,    /* NAND Base ADDR */
+                        <0x80010000 0x4000>;    /* NAND Base CMD */
+                reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
+                nand-skip-bbtscan;
+                clocks = <&fsmc_clk>;
+
+                partition@0 {
+                label = "boot records";
+                        reg = <0x0 0x20000>;
+                };
+                partition@20000 {
+                        label = "free";
+                        reg = <0x20000 0x7e0000>;
+                };
+                partition@800000 {
+                        label = "platform";
+                        reg = <0x800000 0xf800000>;
+                };
+        };
+
+        i2c0: i2c@c0004000 {
+                compatible = "st,ddci2c";
+                reg = <0xc0004000 0x1000>;
+                interrupt-parent = <&vicb>;
+                interrupts = <8>;
+                clocks = <&i2c0_clk>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                ab3100: ab3100@0x48 {
+                        compatible = "stericsson,ab3100";
+                        reg = <0x48>;
+                        interrupt-parent = <&vica>;
+                        interrupts = <0>; /* EXT0 IRQ */
+                        ab3100-regulators {
+                                compatible = "stericsson,ab3100-regulators";
+                                ab3100_ldo_a_reg: ab3100_ldo_a {
+                                        regulator-compatible = "ab3100_ldo_a";
+                                        startup-delay-us = <200>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ab3100_ldo_c_reg: ab3100_ldo_c {
+                                        regulator-compatible = "ab3100_ldo_c";
+                                        startup-delay-us = <200>;
+                                };
+                                ab3100_ldo_d_reg: ab3100_ldo_d {
+                                        regulator-compatible = "ab3100_ldo_d";
+                                        startup-delay-us = <200>;
+                                };
+                                ab3100_ldo_e_reg: ab3100_ldo_e {
+                                        regulator-compatible = "ab3100_ldo_e";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        startup-delay-us = <200>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ab3100_ldo_f_reg: ab3100_ldo_f {
+                                        regulator-compatible = "ab3100_ldo_f";
+                                        regulator-min-microvolt = <2500000>;
+                                        regulator-max-microvolt = <2500000>;
+                                        startup-delay-us = <600>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ab3100_ldo_g_reg: ab3100_ldo_g {
+                                        regulator-compatible = "ab3100_ldo_g";
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        startup-delay-us = <400>;
+                                };
+                                ab3100_ldo_h_reg: ab3100_ldo_h {
+                                        regulator-compatible = "ab3100_ldo_h";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <2750000>;
+                                        startup-delay-us = <200>;
+                                };
+                                ab3100_ldo_k_reg: ab3100_ldo_k {
+                                        regulator-compatible = "ab3100_ldo_k";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <2750000>;
+                                        startup-delay-us = <200>;
+                                };
+                                ab3100_ext_reg: ab3100_ext {
+                                        regulator-compatible = "ab3100_ext";
+                                };
+                                ab3100_buck_reg: ab3100_buck {
+                                        regulator-compatible = "ab3100_buck";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        startup-delay-us = <1000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                        };
+                };
+        };
+
+        i2c1: i2c@c0005000 {
+                compatible = "st,ddci2c";
+                reg = <0xc0005000 0x1000>;
+                interrupt-parent = <&vicb>;
+                interrupts = <9>;
+                clocks = <&i2c1_clk>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                fwcam0: fwcam@0x10 {
+                        reg = <0x10>;
+                };
+                fwcam1: fwcam@0x5d {
+                        reg = <0x5d>;
+                };
+        };
+
+        amba {
+                compatible = "arm,amba-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                vica: interrupt-controller@a0001000 {
+                        compatible = "arm,versatile-vic";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0xa0001000 0x20>;
+                };
+
+                vicb: interrupt-controller@a0002000 {
+                        compatible = "arm,versatile-vic";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0xa0002000 0x20>;
+                };
+
+                uart0: serial@c0013000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0xc0013000 0x1000>;
+                        interrupt-parent = <&vica>;
+                        interrupts = <22>;
+                        clocks = <&uart0_clk>, <&uart0_clk>;
+                        clock-names = "apb_pclk", "uart0_clk";
+                        dmas = <&dmac 17 &dmac 18>;
+                        dma-names = "tx", "rx";
+                };
+
+                uart1: serial@c0007000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0xc0007000 0x1000>;
+                        interrupt-parent = <&vicb>;
+                        interrupts = <20>;
+                        dmas = <&dmac 38 &dmac 39>;
+                        dma-names = "tx", "rx";
+                };
+
+                mmcsd: mmcsd@c0001000 {
+                        compatible = "arm,pl18x", "arm,primecell";
+                        reg = <0xc0001000 0x1000>;
+                        interrupt-parent = <&vicb>;
+                        interrupts = <6 7>;
+                        clocks = <&mmc_pclk>, <&mmc_mclk>;
+                        clock-names = "apb_pclk", "mclk";
+                        max-frequency = <24000000>;
+                        bus-width = <4>; // SD-card slot
+                        mmc-cap-mmc-highspeed;
+                        mmc-cap-sd-highspeed;
+                        cd-gpios = <&gpio 12 0x4>;
+                        cd-inverted;
+                        vmmc-supply = <&ab3100_ldo_g_reg>;
+                        dmas = <&dmac 14>;
+                        dma-names = "rx";
+                };
+
+                spi: ssp@c0006000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0xc0006000 0x1000>;
+                        interrupt-parent = <&vica>;
+                        interrupts = <23>;
+                        clocks = <&spi_clk>, <&spi_clk>;
+                        clock-names = "apb_pclk", "spi_clk";
+                        dmas = <&dmac 27 &dmac 28>;
+                        dma-names = "tx", "rx";
+                        num-cs = <3>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        spi-dummy@1 {
+                                compatible = "arm,pl022-dummy";
+                                reg = <1>;
+                                spi-max-frequency = <20000000>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 14fb2e609bab..0dbee2c23905 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -49,16 +49,18 @@
 
                 uart0: uart@e0000000 {
                         compatible = "xlnx,xuartps";
+                        clocks = <&clkc 23>, <&clkc 40>;
+                        clock-names = "ref_clk", "aper_clk";
                         reg = <0xE0000000 0x1000>;
                         interrupts = <0 27 4>;
-                        clocks = <&uart_clk 0>;
                 };
 
                 uart1: uart@e0001000 {
                         compatible = "xlnx,xuartps";
+                        clocks = <&clkc 24>, <&clkc 41>;
+                        clock-names = "ref_clk", "aper_clk";
                         reg = <0xE0001000 0x1000>;
                         interrupts = <0 50 4>;
-                        clocks = <&uart_clk 1>;
                 };
 
                 slcr: slcr@f8000000 {
@@ -69,50 +71,21 @@
                                 #address-cells = <1>;
                                 #size-cells = <0>;
 
-                                ps_clk: ps_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "fixed-clock";
-                                        /* clock-frequency set in board-specific file */
-                                        clock-output-names = "ps_clk";
-                                };
-                                armpll: armpll {
-                                        #clock-cells = <0>;
-                                        compatible = "xlnx,zynq-pll";
-                                        clocks = <&ps_clk>;
-                                        reg = <0x100 0x110>;
-                                        clock-output-names = "armpll";
-                                };
-                                ddrpll: ddrpll {
-                                        #clock-cells = <0>;
-                                        compatible = "xlnx,zynq-pll";
-                                        clocks = <&ps_clk>;
-                                        reg = <0x104 0x114>;
-                                        clock-output-names = "ddrpll";
-                                };
-                                iopll: iopll {
-                                        #clock-cells = <0>;
-                                        compatible = "xlnx,zynq-pll";
-                                        clocks = <&ps_clk>;
-                                        reg = <0x108 0x118>;
-                                        clock-output-names = "iopll";
-                                };
-                                uart_clk: uart_clk {
-                                        #clock-cells = <1>;
-                                        compatible = "xlnx,zynq-periph-clock";
-                                        clocks = <&iopll &armpll &ddrpll>;
-                                        reg = <0x154>;
-                                        clock-output-names = "uart0_ref_clk",
-                                                             "uart1_ref_clk";
-                                };
-                                cpu_clk: cpu_clk {
+                                clkc: clkc {
                                         #clock-cells = <1>;
-                                        compatible = "xlnx,zynq-cpu-clock";
-                                        clocks = <&iopll &armpll &ddrpll>;
-                                        reg = <0x120 0x1C4>;
-                                        clock-output-names = "cpu_6x4x",
-                                                             "cpu_3x2x",
-                                                             "cpu_2x",
-                                                             "cpu_1x";
+                                        compatible = "xlnx,ps7-clkc";
+                                        ps-clk-frequency = <33333333>;
+                                        clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
+                                                        "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
+                                                        "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
+                                                        "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+                                                        "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
+                                                        "dma", "usb0_aper", "usb1_aper", "gem0_aper",
+                                                        "gem1_aper", "sdio0_aper", "sdio1_aper",
+                                                        "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
+                                                        "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
+                                                        "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
+                                                        "dbg_trc", "dbg_apb";
                                 };
                         };
                 };
@@ -121,9 +94,8 @@
                         interrupt-parent = <&intc>;
                         interrupts = < 0 10 4 0 11 4 0 12 4 >;
                         compatible = "cdns,ttc";
+                        clocks = <&clkc 6>;
                         reg = <0xF8001000 0x1000>;
-                        clocks = <&cpu_clk 3>;
-                        clock-names = "cpu_1x";
                         clock-ranges;
                 };
 
@@ -131,9 +103,8 @@
                         interrupt-parent = <&intc>;
                         interrupts = < 0 37 4 0 38 4 0 39 4 >;
                         compatible = "cdns,ttc";
+                        clocks = <&clkc 6>;
                         reg = <0xF8002000 0x1000>;
-                        clocks = <&cpu_clk 3>;
-                        clock-names = "cpu_1x";
                         clock-ranges;
                 };
                 scutimer: scutimer@f8f00600 {
@@ -141,7 +112,7 @@
                         interrupts = < 1 13 0x301 >;
                         compatible = "arm,cortex-a9-twd-timer";
                         reg = < 0xf8f00600 0x20 >;
-                        clocks = <&cpu_clk 1>;
+                        clocks = <&clkc 4>;
                 } ;
         };
 };
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 86f44d5b0265..e25a307438ad 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -28,7 +28,3 @@
         };
 
 };
-
-&ps_clk {
-        clock-frequency = <33333330>;
-};
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 9353184d730d..c3a4e9ceba34 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -17,3 +17,6 @@ config SHARP_PARAM
 
 config SHARP_SCOOP
         bool
+
+config TI_PRIV_EDMA
+        bool
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 48434cbe3e89..8c60f473e976 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -16,3 +16,4 @@ obj-$(CONFIG_ARM_TIMER_SP804)	+= timer-sp.o
 obj-$(CONFIG_MCPM)              += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
 AFLAGS_mcpm_head.o              := -march=armv7-a
 AFLAGS_vlock.o                  := -march=armv7-a
+obj-$(CONFIG_TI_PRIV_EDMA)      += edma.o
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/common/edma.c
index 45b7c71d9cc1..a1db6cd8cf79 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/common/edma.c
@@ -25,7 +25,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <mach/edma.h>
+#include <linux/platform_data/edma.h>
 
 /* Offsets matching "struct edmacc_param" */
 #define PARM_OPT                0x00
@@ -494,26 +494,6 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
         return IRQ_HANDLED;
 }
 
-/******************************************************************************
- *
- * Transfer controller error interrupt handlers
- *
- *****************************************************************************/
-
-#define tc_errs_handled false   /* disabled as long as they're NOPs */
-
-static irqreturn_t dma_tc0err_handler(int irq, void *data)
-{
-        dev_dbg(data, "dma_tc0err_handler\n");
-        return IRQ_HANDLED;
-}
-
-static irqreturn_t dma_tc1err_handler(int irq, void *data)
-{
-        dev_dbg(data, "dma_tc1err_handler\n");
-        return IRQ_HANDLED;
-}
-
 static int reserve_contiguous_slots(int ctlr, unsigned int id,
                                      unsigned int num_slots,
                                      unsigned int start_slot)
@@ -1541,23 +1521,6 @@ static int __init edma_probe(struct platform_device *pdev)
                 arch_num_cc++;
         }
 
-        if (tc_errs_handled) {
-                status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0,
-                                        "edma_tc0", &pdev->dev);
-                if (status < 0) {
-                        dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
-                                IRQ_TCERRINT0, status);
-                        return status;
-                }
-                status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0,
-                                        "edma_tc1", &pdev->dev);
-                if (status < 0) {
-                        dev_dbg(&pdev->dev, "request_irq %d --> %d\n",
-                                IRQ_TCERRINT, status);
-                        return status;
-                }
-        }
-
         return 0;
 
 fail:
diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig
index 1cd94c36321f..9e8c8316d6b0 100644
--- a/arch/arm/configs/clps711x_defconfig
+++ b/arch/arm/configs/clps711x_defconfig
@@ -31,21 +31,18 @@ CONFIG_EP7211_DONGLE=y
 # CONFIG_WIRELESS is not set
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_JEDECPROBE=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_AUTCPU12=y
 CONFIG_MTD_PLATRAM=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_GPIO=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_CADENCE is not set
 # CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
 CONFIG_CS89x0=y
 CONFIG_CS89x0_PLATFORM=y
 # CONFIG_NET_VENDOR_FARADAY is not set
@@ -63,7 +60,11 @@ CONFIG_CS89x0_PLATFORM=y
 # CONFIG_VT is not set
 CONFIG_SERIAL_CLPS711X_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
+CONFIG_SPI_CLPS711X=y
+CONFIG_GPIO_CLPS711X=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
@@ -87,4 +88,3 @@ CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 # CONFIG_CRYPTO_HW is not set
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index e40b435d204e..ad7dfbbafa45 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -1,4 +1,4 @@
-CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_BLK_DEV_INITRD=y
@@ -7,17 +7,18 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
 CONFIG_ARCH_EXYNOS=y
-CONFIG_S3C_LOWLEVEL_UART_PORT=1
+CONFIG_S3C_LOWLEVEL_UART_PORT=3
 CONFIG_S3C24XX_PWM=y
 CONFIG_ARCH_EXYNOS5=y
 CONFIG_MACH_EXYNOS4_DT=y
-CONFIG_MACH_EXYNOS5_DT=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
@@ -30,35 +31,59 @@ CONFIG_NET_KEY=y
 CONFIG_INET=y
 CONFIG_RFKILL_REGULATOR=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_SG=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_CRYPT=m
 CONFIG_NETDEVICES=y
 CONFIG_SMSC911X=y
 CONFIG_USB_USBNET=y
 CONFIG_USB_NET_SMSC75XX=y
 CONFIG_USB_NET_SMSC95XX=y
 CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_CROS_EC=y
+# CONFIG_MOUSE_PS2 is not set
+CONFIG_MOUSE_CYAPA=y
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_SAMSUNG=y
 CONFIG_SERIAL_SAMSUNG_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_HW_RANDOM=y
+CONFIG_TCG_TPM=y
+CONFIG_TCG_TIS_I2C_INFINEON=y
 CONFIG_I2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_ARB_GPIO_CHALLENGE=y
+CONFIG_I2C_S3C2410=y
+CONFIG_DEBUG_GPIO=y
 # CONFIG_HWMON is not set
+CONFIG_MFD_CROS_EC=y
+CONFIG_MFD_CROS_EC_I2C=y
+CONFIG_MFD_MAX77686=y
+CONFIG_MFD_MAX8997=y
+CONFIG_MFD_SEC_CORE=y
 CONFIG_MFD_TPS65090=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_MAX8997=y
+CONFIG_REGULATOR_MAX77686=y
+CONFIG_REGULATOR_S5M8767=y
 CONFIG_REGULATOR_TPS65090=y
 CONFIG_FB=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_SIMPLE=y
 CONFIG_EXYNOS_VIDEO=y
 CONFIG_EXYNOS_MIPI_DSI=y
 CONFIG_EXYNOS_DP=y
@@ -67,6 +92,22 @@ CONFIG_FONTS=y
 CONFIG_FONT_7x14=y
 CONFIG_LOGO=y
 CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_S5P=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_PHY=y
+CONFIG_SAMSUNG_USB2PHY=y
+CONFIG_SAMSUNG_USB3PHY=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_S3C=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_IDMAC=y
+CONFIG_MMC_DW_EXYNOS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_S3C=y
+CONFIG_COMMON_CLK_MAX77686=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS=y
@@ -79,6 +120,7 @@ CONFIG_ROMFS_FS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_HUNG_TASK=y
@@ -87,6 +129,5 @@ CONFIG_DEBUG_SPINLOCK=y
 CONFIG_DEBUG_MUTEXES=y
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-CONFIG_EARLY_PRINTK=y
+CONFIG_CRYPTO_SHA256=y
 CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 6ec010f248b5..06686e7303a9 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -37,6 +37,8 @@ CONFIG_MACH_IMX51_DT=y
 CONFIG_MACH_EUKREA_CPUIMX51SD=y
 CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
+CONFIG_SOC_IMX6SL=y
+CONFIG_SOC_VF610=y
 CONFIG_MXC_PWM=y
 CONFIG_SMP=y
 CONFIG_VMSPLIT_2G=y
@@ -47,6 +49,7 @@ CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
 CONFIG_VFP=y
 CONFIG_NEON=y
 CONFIG_BINFMT_MISC=m
+CONFIG_PM_RUNTIME=y
 CONFIG_PM_DEBUG=y
 CONFIG_PM_TEST_SUSPEND=y
 CONFIG_NET=y
@@ -170,6 +173,7 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_LCD_L4F00242T03=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 CONFIG_FONTS=y
@@ -182,6 +186,7 @@ CONFIG_SND_SOC=y
 CONFIG_SND_IMX_SOC=y
 CONFIG_SND_SOC_PHYCORE_AC97=y
 CONFIG_SND_SOC_EUKREA_TLV320=y
+CONFIG_SND_SOC_IMX_WM8962=y
 CONFIG_SND_SOC_IMX_SGTL5000=y
 CONFIG_SND_SOC_IMX_MC13783=y
 CONFIG_USB=y
@@ -208,10 +213,15 @@ CONFIG_IMX_SDMA=y
 CONFIG_MXS_DMA=y
 CONFIG_STAGING=y
 CONFIG_DRM_IMX=y
+CONFIG_DRM_IMX_TVE=y
+CONFIG_DRM_IMX_FB_HELPER=y
+CONFIG_DRM_IMX_PARALLEL_DISPLAY=y
 CONFIG_DRM_IMX_IPUV3_CORE=y
 CONFIG_DRM_IMX_IPUV3=y
 CONFIG_COMMON_CLK_DEBUG=y
 # CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PWM=y
+CONFIG_PWM_IMX=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
new file mode 100644
index 000000000000..62e968cac9dc
--- /dev/null
+++ b/arch/arm/configs/keystone_defconfig
@@ -0,0 +1,157 @@
+# CONFIG_SWAP is not set
+CONFIG_POSIX_MQUEUE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_ELF_CORE is not set
+# CONFIG_BASE_FULL is not set
+CONFIG_EMBEDDED=y
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_ARCH_KEYSTONE=y
+CONFIG_ARM_LPAE=y
+CONFIG_SMP=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_SUSPEND is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=y
+CONFIG_XFRM_USER=y
+CONFIG_XFRM_SUB_POLICY=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_NET_IPIP=y
+CONFIG_NET_IPGRE_DEMUX=y
+CONFIG_NET_IPGRE=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_INET_AH=y
+CONFIG_INET_IPCOMP=y
+CONFIG_IPV6=y
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_IPV6_PIMSM_V2=y
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_CPU=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP_SCTP=y
+CONFIG_VLAN_8021Q=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_CMA=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_PLATRAM=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_EEPROM_AT24=y
+CONFIG_NETDEVICES=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_SPI=y
+CONFIG_SPI_SPIDEV=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_DMADEVICES=y
+CONFIG_COMMON_CLK_DEBUG=y
+CONFIG_MEMORY=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_UBIFS_FS=y
+CONFIG_CRAMFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_USER=y
+CONFIG_CRYPTO_USER=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_XCBC=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_SKCIPHER=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index a1d8252e9ec7..0f2aa61911a3 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
@@ -31,6 +30,7 @@ CONFIG_MACH_T5325=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
 CONFIG_MACH_CLOUDBOX_DT=y
+CONFIG_MACH_DB88F628X_BP_DT=y
 CONFIG_MACH_DLINK_KIRKWOOD_DT=y
 CONFIG_MACH_DOCKSTAR_DT=y
 CONFIG_MACH_DREAMPLUG_DT=y
@@ -50,14 +50,19 @@ CONFIG_MACH_NETSPACE_V2_DT=y
 CONFIG_MACH_NSA310_DT=y
 CONFIG_MACH_OPENBLOCKS_A6_DT=y
 CONFIG_MACH_READYNAS_DT=y
+CONFIG_MACH_SHEEVAPLUG_DT=y
 CONFIG_MACH_TOPKICK_DT=y
 CONFIG_MACH_TS219_DT=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
+CONFIG_PCI_MVEBU=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_IDLE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -68,14 +73,12 @@ CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IPV6 is not set
-CONFIG_NET_DSA=y
 CONFIG_NET_PKTGEN=m
 CONFIG_CFG80211=y
 CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_JEDECPROBE=y
@@ -140,6 +143,7 @@ CONFIG_HID_TOPSEED=y
 CONFIG_HID_THRUSTMASTER=y
 CONFIG_HID_ZEROPLUS=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_USB_PRINTER=m
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 2e67a272df70..4aa640106611 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -31,10 +31,12 @@ CONFIG_SATA_HIGHBANK=y
 CONFIG_SATA_MV=y
 CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_NETDEVICES=y
+CONFIG_SUN4I_EMAC=y
 CONFIG_NET_CALXEDA_XGMAC=y
 CONFIG_SMSC911X=y
 CONFIG_STMMAC_ETH=y
 CONFIG_SERIO_AMBAKMI=y
+CONFIG_MDIO_SUN4I=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_DW=y
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index f3e8ae001ff1..731814e2c189 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -13,6 +13,8 @@ CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_XP=y
 # CONFIG_CACHE_L2X0 is not set
 # CONFIG_SWP_EMULATE is not set
+CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
 CONFIG_SMP=y
 CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
@@ -60,6 +62,8 @@ CONFIG_USB_SUPPORT=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_MMC=y
 CONFIG_MMC_MVSDIO=y
 CONFIG_NEW_LEDS=y
@@ -96,5 +100,3 @@ CONFIG_TIMER_STATS=y
 # CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig
index 374000ec4e4e..fd81a1b99cce 100644
--- a/arch/arm/configs/u300_defconfig
+++ b/arch/arm/configs/u300_defconfig
@@ -1,7 +1,8 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_EXPERT=y
 # CONFIG_AIO is not set
@@ -11,12 +12,9 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_CFQ is not set
+# CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_U300=y
-CONFIG_MACH_U300=y
-CONFIG_MACH_U300_BS335=y
 CONFIG_MACH_U300_SPIDUMMY=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -44,14 +42,15 @@ CONFIG_I2C=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_FB=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 # CONFIG_LCD_CLASS_DEVICE is not set
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
-CONFIG_MMC_CLKGATE=y
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ARMMMCI=y
 CONFIG_RTC_CLASS=y
 # CONFIG_RTC_HCTOSYS is not set
@@ -70,4 +69,3 @@ CONFIG_DEBUG_FS=y
 CONFIG_TIMER_STATS=y
 # CONFIG_DEBUG_PREEMPT is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 05ee9eebad6b..a5fef710af32 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -136,7 +136,11 @@
  * assumes FIQs are enabled, and that the processor is in SVC mode.
  */
         .macro  save_and_disable_irqs, oldcpsr
+#ifdef CONFIG_CPU_V7M
+        mrs     \oldcpsr, primask
+#else
         mrs     \oldcpsr, cpsr
+#endif
         disable_irq
         .endm
 
@@ -150,7 +154,11 @@
  * guarantee that this will preserve the flags.
  */
         .macro  restore_irqs_notrace, oldcpsr
+#ifdef CONFIG_CPU_V7M
+        msr     primask, \oldcpsr
+#else
         msr     cpsr_c, \oldcpsr
+#endif
         .endm
 
         .macro restore_irqs, oldcpsr
@@ -229,7 +237,14 @@
 #endif
         .endm
 
-#ifdef CONFIG_THUMB2_KERNEL
+#if defined(CONFIG_CPU_V7M)
+        /*
+         * setmode is used to assert to be in svc mode during boot. For v7-M
+         * this is done in __v7m_setup, so setmode can be empty here.
+         */
+        .macro  setmode, mode, reg
+        .endm
+#elif defined(CONFIG_THUMB2_KERNEL)
         .macro  setmode, mode, reg
         mov     \reg, #\mode
         msr     cpsr_c, \reg
diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
index 1f3262e99d81..cedd3721318b 100644
--- a/arch/arm/include/asm/cp15.h
+++ b/arch/arm/include/asm/cp15.h
@@ -61,6 +61,20 @@ static inline void set_cr(unsigned int val)
         isb();
 }
 
+static inline unsigned int get_auxcr(void)
+{
+        unsigned int val;
+        asm("mrc p15, 0, %0, c1, c0, 1  @ get AUXCR" : "=r" (val));
+        return val;
+}
+
+static inline void set_auxcr(unsigned int val)
+{
+        asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR"
+          : : "r" (val));
+        isb();
+}
+
 #ifndef CONFIG_SMP
 extern void adjust_cr(unsigned long mask, unsigned long set);
 #endif
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 7652712d1d14..ec635ff32f49 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -10,6 +10,22 @@
 #define CPUID_TLBTYPE   3
 #define CPUID_MPIDR     5
 
+#ifdef CONFIG_CPU_V7M
+#define CPUID_EXT_PFR0  0x40
+#define CPUID_EXT_PFR1  0x44
+#define CPUID_EXT_DFR0  0x48
+#define CPUID_EXT_AFR0  0x4c
+#define CPUID_EXT_MMFR0 0x50
+#define CPUID_EXT_MMFR1 0x54
+#define CPUID_EXT_MMFR2 0x58
+#define CPUID_EXT_MMFR3 0x5c
+#define CPUID_EXT_ISAR0 0x60
+#define CPUID_EXT_ISAR1 0x64
+#define CPUID_EXT_ISAR2 0x68
+#define CPUID_EXT_ISAR3 0x6c
+#define CPUID_EXT_ISAR4 0x70
+#define CPUID_EXT_ISAR5 0x74
+#else
 #define CPUID_EXT_PFR0  "c1, 0"
 #define CPUID_EXT_PFR1  "c1, 1"
 #define CPUID_EXT_DFR0  "c1, 2"
@@ -24,6 +40,7 @@
 #define CPUID_EXT_ISAR3 "c2, 3"
 #define CPUID_EXT_ISAR4 "c2, 4"
 #define CPUID_EXT_ISAR5 "c2, 5"
+#endif
 
 #define MPIDR_SMP_BITMASK (0x3 << 30)
 #define MPIDR_SMP_VALUE (0x2 << 30)
@@ -79,7 +96,23 @@ extern unsigned int processor_id;
                 __val;                                                  \
         })
 
-#else /* ifdef CONFIG_CPU_CP15 */
+#elif defined(CONFIG_CPU_V7M)
+
+#include <asm/io.h>
+#include <asm/v7m.h>
+
+#define read_cpuid(reg)                                                 \
+        ({                                                              \
+                WARN_ON_ONCE(1);                                        \
+                0;                                                      \
+        })
+
+static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
+{
+        return readl(BASEADDR_V7M_SCB + offset);
+}
+
+#else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
 
 /*
  * read_cpuid and read_cpuid_ext should only ever be called on machines that
@@ -106,7 +139,14 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
         return read_cpuid(CPUID_ID);
 }
 
-#else /* ifdef CONFIG_CPU_CP15 */
+#elif defined(CONFIG_CPU_V7M)
+
+static inline unsigned int __attribute_const__ read_cpuid_id(void)
+{
+        return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
+}
+
+#else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
 
 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 {
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index ea289e1435e7..c81adc08b3fb 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -117,10 +117,37 @@
 # endif
 #endif
 
+#if defined(CONFIG_CPU_V7M)
+# ifdef _CACHE
+#  define MULTI_CACHE 1
+# else
+#  define _CACHE nop
+# endif
+#endif
+
 #if !defined(_CACHE) && !defined(MULTI_CACHE)
 #error Unknown cache maintenance model
 #endif
 
+#ifndef __ASSEMBLER__
+extern inline void nop_flush_icache_all(void) { }
+extern inline void nop_flush_kern_cache_all(void) { }
+extern inline void nop_flush_kern_cache_louis(void) { }
+extern inline void nop_flush_user_cache_all(void) { }
+extern inline void nop_flush_user_cache_range(unsigned long a,
+                unsigned long b, unsigned int c) { }
+
+extern inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }
+extern inline int nop_coherent_user_range(unsigned long a,
+                unsigned long b) { return 0; }
+extern inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
+
+extern inline void nop_dma_flush_range(const void *a, const void *b) { }
+
+extern inline void nop_dma_map_area(const void *s, size_t l, int f) { }
+extern inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
+#endif
+
 #ifndef MULTI_CACHE
 #define __cpuc_flush_icache_all         __glue(_CACHE,_flush_icache_all)
 #define __cpuc_flush_kern_all           __glue(_CACHE,_flush_kern_cache_all)
diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h
index b6e9f2c108b5..6b70f1b46a6e 100644
--- a/arch/arm/include/asm/glue-df.h
+++ b/arch/arm/include/asm/glue-df.h
@@ -95,6 +95,14 @@
 # endif
 #endif
 
+#ifdef CONFIG_CPU_ABRT_NOMMU
+# ifdef CPU_DABORT_HANDLER
+#  define MULTI_DABORT 1
+# else
+#  define CPU_DABORT_HANDLER nommu_early_abort
+# endif
+#endif
+
 #ifndef CPU_DABORT_HANDLER
 #error Unknown data abort handler type
 #endif
diff --git a/arch/arm/include/asm/glue-proc.h b/arch/arm/include/asm/glue-proc.h
index ac1dd54724b6..f2f39bcf7945 100644
--- a/arch/arm/include/asm/glue-proc.h
+++ b/arch/arm/include/asm/glue-proc.h
@@ -230,6 +230,15 @@
 # endif
 #endif
 
+#ifdef CONFIG_CPU_V7M
+# ifdef CPU_NAME
+#  undef  MULTI_CPU
+#  define MULTI_CPU
+# else
+#  define CPU_NAME cpu_v7m
+# endif
+#endif
+
 #ifndef MULTI_CPU
 #define cpu_proc_init                   __glue(CPU_NAME,_proc_init)
 #define cpu_proc_fin                    __glue(CPU_NAME,_proc_fin)
diff --git a/arch/arm/include/asm/hardware/pci_v3.h b/arch/arm/include/asm/hardware/pci_v3.h
deleted file mode 100644
index 2811c7e2cfdf..000000000000
--- a/arch/arm/include/asm/hardware/pci_v3.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- *  arch/arm/include/asm/hardware/pci_v3.h
- *
- *  Internal header file PCI V3 chip
- *
- *  Copyright (C) ARM Limited
- *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef ASM_ARM_HARDWARE_PCI_V3_H
-#define ASM_ARM_HARDWARE_PCI_V3_H
-
-/* -------------------------------------------------------------------------------
- *  V3 Local Bus to PCI Bridge definitions
- * -------------------------------------------------------------------------------
- *  Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
- *  All V3 register names are prefaced by V3_ to avoid clashing with any other
- *  PCI definitions.  Their names match the user's manual.
- * 
- *  I'm assuming that I20 is disabled.
- * 
- */
-#define V3_PCI_VENDOR                   0x00000000
-#define V3_PCI_DEVICE                   0x00000002
-#define V3_PCI_CMD                      0x00000004
-#define V3_PCI_STAT                     0x00000006
-#define V3_PCI_CC_REV                   0x00000008
-#define V3_PCI_HDR_CFG                  0x0000000C
-#define V3_PCI_IO_BASE                  0x00000010
-#define V3_PCI_BASE0                    0x00000014
-#define V3_PCI_BASE1                    0x00000018
-#define V3_PCI_SUB_VENDOR               0x0000002C
-#define V3_PCI_SUB_ID                   0x0000002E
-#define V3_PCI_ROM                      0x00000030
-#define V3_PCI_BPARAM                   0x0000003C
-#define V3_PCI_MAP0                     0x00000040
-#define V3_PCI_MAP1                     0x00000044
-#define V3_PCI_INT_STAT                 0x00000048
-#define V3_PCI_INT_CFG                  0x0000004C 
-#define V3_LB_BASE0                     0x00000054
-#define V3_LB_BASE1                     0x00000058
-#define V3_LB_MAP0                      0x0000005E
-#define V3_LB_MAP1                      0x00000062
-#define V3_LB_BASE2                     0x00000064
-#define V3_LB_MAP2                      0x00000066
-#define V3_LB_SIZE                      0x00000068
-#define V3_LB_IO_BASE                   0x0000006E
-#define V3_FIFO_CFG                     0x00000070
-#define V3_FIFO_PRIORITY                0x00000072
-#define V3_FIFO_STAT                    0x00000074
-#define V3_LB_ISTAT                     0x00000076
-#define V3_LB_IMASK                     0x00000077
-#define V3_SYSTEM                       0x00000078
-#define V3_LB_CFG                       0x0000007A
-#define V3_PCI_CFG                      0x0000007C
-#define V3_DMA_PCI_ADR0                 0x00000080
-#define V3_DMA_PCI_ADR1                 0x00000090
-#define V3_DMA_LOCAL_ADR0               0x00000084
-#define V3_DMA_LOCAL_ADR1               0x00000094
-#define V3_DMA_LENGTH0                  0x00000088
-#define V3_DMA_LENGTH1                  0x00000098
-#define V3_DMA_CSR0                     0x0000008B
-#define V3_DMA_CSR1                     0x0000009B
-#define V3_DMA_CTLB_ADR0                0x0000008C
-#define V3_DMA_CTLB_ADR1                0x0000009C
-#define V3_DMA_DELAY                    0x000000E0
-#define V3_MAIL_DATA                    0x000000C0
-#define V3_PCI_MAIL_IEWR                0x000000D0
-#define V3_PCI_MAIL_IERD                0x000000D2
-#define V3_LB_MAIL_IEWR                 0x000000D4
-#define V3_LB_MAIL_IERD                 0x000000D6
-#define V3_MAIL_WR_STAT                 0x000000D8
-#define V3_MAIL_RD_STAT                 0x000000DA
-#define V3_QBA_MAP                      0x000000DC
-
-/*  PCI COMMAND REGISTER bits
- */
-#define V3_COMMAND_M_FBB_EN             (1 << 9)
-#define V3_COMMAND_M_SERR_EN            (1 << 8)
-#define V3_COMMAND_M_PAR_EN             (1 << 6)
-#define V3_COMMAND_M_MASTER_EN          (1 << 2)
-#define V3_COMMAND_M_MEM_EN             (1 << 1)
-#define V3_COMMAND_M_IO_EN              (1 << 0)
-
-/*  SYSTEM REGISTER bits
- */
-#define V3_SYSTEM_M_RST_OUT             (1 << 15)
-#define V3_SYSTEM_M_LOCK                (1 << 14)
-
-/*  PCI_CFG bits
- */
-#define V3_PCI_CFG_M_I2O_EN             (1 << 15)
-#define V3_PCI_CFG_M_IO_REG_DIS         (1 << 14)
-#define V3_PCI_CFG_M_IO_DIS             (1 << 13)
-#define V3_PCI_CFG_M_EN3V               (1 << 12)
-#define V3_PCI_CFG_M_RETRY_EN           (1 << 10)
-#define V3_PCI_CFG_M_AD_LOW1            (1 << 9)
-#define V3_PCI_CFG_M_AD_LOW0            (1 << 8)
-
-/*  PCI_BASE register bits (PCI -> Local Bus)
- */
-#define V3_PCI_BASE_M_ADR_BASE          0xFFF00000
-#define V3_PCI_BASE_M_ADR_BASEL         0x000FFF00
-#define V3_PCI_BASE_M_PREFETCH          (1 << 3)
-#define V3_PCI_BASE_M_TYPE              (3 << 1)
-#define V3_PCI_BASE_M_IO                (1 << 0)
-
-/*  PCI MAP register bits (PCI -> Local bus)
- */
-#define V3_PCI_MAP_M_MAP_ADR            0xFFF00000
-#define V3_PCI_MAP_M_RD_POST_INH        (1 << 15)
-#define V3_PCI_MAP_M_ROM_SIZE           (3 << 10)
-#define V3_PCI_MAP_M_SWAP               (3 << 8)
-#define V3_PCI_MAP_M_ADR_SIZE           0x000000F0
-#define V3_PCI_MAP_M_REG_EN             (1 << 1)
-#define V3_PCI_MAP_M_ENABLE             (1 << 0)
-
-/*
- *  LB_BASE0,1 register bits (Local bus -> PCI)
- */
-#define V3_LB_BASE_ADR_BASE             0xfff00000
-#define V3_LB_BASE_SWAP                 (3 << 8)
-#define V3_LB_BASE_ADR_SIZE             (15 << 4)
-#define V3_LB_BASE_PREFETCH             (1 << 3)
-#define V3_LB_BASE_ENABLE               (1 << 0)
-
-#define V3_LB_BASE_ADR_SIZE_1MB         (0 << 4)
-#define V3_LB_BASE_ADR_SIZE_2MB         (1 << 4)
-#define V3_LB_BASE_ADR_SIZE_4MB         (2 << 4)
-#define V3_LB_BASE_ADR_SIZE_8MB         (3 << 4)
-#define V3_LB_BASE_ADR_SIZE_16MB        (4 << 4)
-#define V3_LB_BASE_ADR_SIZE_32MB        (5 << 4)
-#define V3_LB_BASE_ADR_SIZE_64MB        (6 << 4)
-#define V3_LB_BASE_ADR_SIZE_128MB       (7 << 4)
-#define V3_LB_BASE_ADR_SIZE_256MB       (8 << 4)
-#define V3_LB_BASE_ADR_SIZE_512MB       (9 << 4)
-#define V3_LB_BASE_ADR_SIZE_1GB         (10 << 4)
-#define V3_LB_BASE_ADR_SIZE_2GB         (11 << 4)
-
-#define v3_addr_to_lb_base(a)   ((a) & V3_LB_BASE_ADR_BASE)
-
-/*
- *  LB_MAP0,1 register bits (Local bus -> PCI)
- */
-#define V3_LB_MAP_MAP_ADR               0xfff0
-#define V3_LB_MAP_TYPE                  (7 << 1)
-#define V3_LB_MAP_AD_LOW_EN             (1 << 0)
-
-#define V3_LB_MAP_TYPE_IACK             (0 << 1)
-#define V3_LB_MAP_TYPE_IO               (1 << 1)
-#define V3_LB_MAP_TYPE_MEM              (3 << 1)
-#define V3_LB_MAP_TYPE_CONFIG           (5 << 1)
-#define V3_LB_MAP_TYPE_MEM_MULTIPLE     (6 << 1)
-
-#define v3_addr_to_lb_map(a)    (((a) >> 16) & V3_LB_MAP_MAP_ADR)
-
-/*
- *  LB_BASE2 register bits (Local bus -> PCI IO)
- */
-#define V3_LB_BASE2_ADR_BASE            0xff00
-#define V3_LB_BASE2_SWAP                (3 << 6)
-#define V3_LB_BASE2_ENABLE              (1 << 0)
-
-#define v3_addr_to_lb_base2(a)  (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
-
-/*
- *  LB_MAP2 register bits (Local bus -> PCI IO)
- */
-#define V3_LB_MAP2_MAP_ADR              0xff00
-
-#define v3_addr_to_lb_map2(a)   (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
-
-#endif
diff --git a/arch/arm/include/asm/irqflags.h b/arch/arm/include/asm/irqflags.h
index 1e6cca55c750..3b763d6652a0 100644
--- a/arch/arm/include/asm/irqflags.h
+++ b/arch/arm/include/asm/irqflags.h
@@ -8,6 +8,16 @@
 /*
  * CPU interrupt mask handling.
  */
+#ifdef CONFIG_CPU_V7M
+#define IRQMASK_REG_NAME_R "primask"
+#define IRQMASK_REG_NAME_W "primask"
+#define IRQMASK_I_BIT   1
+#else
+#define IRQMASK_REG_NAME_R "cpsr"
+#define IRQMASK_REG_NAME_W "cpsr_c"
+#define IRQMASK_I_BIT   PSR_I_BIT
+#endif
+
 #if __LINUX_ARM_ARCH__ >= 6
 
 static inline unsigned long arch_local_irq_save(void)
@@ -15,7 +25,7 @@ static inline unsigned long arch_local_irq_save(void)
         unsigned long flags;
 
         asm volatile(
-                "       mrs     %0, cpsr        @ arch_local_irq_save\n"
+                "       mrs     %0, " IRQMASK_REG_NAME_R "      @ arch_local_irq_save\n"
                 "       cpsid   i"
                 : "=r" (flags) : : "memory", "cc");
         return flags;
@@ -129,7 +139,7 @@ static inline unsigned long arch_local_save_flags(void)
 {
         unsigned long flags;
         asm volatile(
-                "       mrs     %0, cpsr        @ local_save_flags"
+                "       mrs     %0, " IRQMASK_REG_NAME_R "      @ local_save_flags"
                 : "=r" (flags) : : "memory", "cc");
         return flags;
 }
@@ -140,7 +150,7 @@ static inline unsigned long arch_local_save_flags(void)
 static inline void arch_local_irq_restore(unsigned long flags)
 {
         asm volatile(
-                "       msr     cpsr_c, %0      @ local_irq_restore"
+                "       msr     " IRQMASK_REG_NAME_W ", %0      @ local_irq_restore"
                 :
                 : "r" (flags)
                 : "memory", "cc");
@@ -148,8 +158,8 @@ static inline void arch_local_irq_restore(unsigned long flags)
 
 static inline int arch_irqs_disabled_flags(unsigned long flags)
 {
-        return flags & PSR_I_BIT;
+        return flags & IRQMASK_I_BIT;
 }
 
-#endif
-#endif
+#endif /* ifdef __KERNEL__ */
+#endif /* ifndef __ASM_ARM_IRQFLAGS_H */
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 308ad7d6f98b..75bf07910b81 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -8,6 +8,8 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/types.h>
+
 #ifndef __ASSEMBLY__
 
 struct tag;
@@ -16,8 +18,10 @@ struct pt_regs;
 struct smp_operations;
 #ifdef CONFIG_SMP
 #define smp_ops(ops) (&(ops))
+#define smp_init_ops(ops) (&(ops))
 #else
 #define smp_ops(ops) (struct smp_operations *)NULL
+#define smp_init_ops(ops) (bool (*)(void))NULL
 #endif
 
 struct machine_desc {
@@ -41,6 +45,7 @@ struct machine_desc {
         unsigned char           reserve_lp2 :1; /* never has lp2        */
         char                    restart_mode;   /* default restart mode */
         struct smp_operations   *smp;           /* SMP operations       */
+        bool                    (*smp_init)(void);
         void                    (*fixup)(struct tag *, char **,
                                          struct meminfo *);
         void                    (*reserve)(void);/* reserve mem blocks  */
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 7d2c3c843801..a1c90d7feb0e 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -16,6 +16,7 @@
 struct pci_sys_data;
 struct pci_ops;
 struct pci_bus;
+struct device;
 
 struct hw_pci {
 #ifdef CONFIG_PCI_DOMAINS
@@ -68,7 +69,16 @@ struct pci_sys_data {
 /*
  * Call this with your hw_pci struct to initialise the PCI system.
  */
-void pci_common_init(struct hw_pci *);
+void pci_common_init_dev(struct device *, struct hw_pci *);
+
+/*
+ * Compatibility wrapper for older platforms that do not care about
+ * passing the parent device.
+ */
+static inline void pci_common_init(struct hw_pci *hw)
+{
+        pci_common_init_dev(NULL, hw);
+}
 
 /*
  * Setup early fixed I/O mapping.
@@ -96,9 +106,4 @@ extern struct pci_ops via82c505_ops;
 extern int via82c505_setup(int nr, struct pci_sys_data *);
 extern void via82c505_init(void *sysdata);
 
-extern struct pci_ops pci_v3_ops;
-extern int pci_v3_setup(int nr, struct pci_sys_data *);
-extern void pci_v3_preinit(void);
-extern void pci_v3_postinit(void);
-
 #endif /* __ASM_MACH_PCI_H */
diff --git a/arch/arm/include/asm/percpu.h b/arch/arm/include/asm/percpu.h
index 968c0a14e0a3..209e6504922e 100644
--- a/arch/arm/include/asm/percpu.h
+++ b/arch/arm/include/asm/percpu.h
@@ -30,8 +30,15 @@ static inline void set_my_cpu_offset(unsigned long off)
 static inline unsigned long __my_cpu_offset(void)
 {
         unsigned long off;
-        /* Read TPIDRPRW */
-        asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) : : "memory");
+        register unsigned long *sp asm ("sp");
+
+        /*
+         * Read TPIDRPRW.
+         * We want to allow caching the value, so avoid using volatile and
+         * instead use a fake stack read to hazard against barrier().
+         */
+        asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) : "Q" (*sp));
+
         return off;
 }
 #define __my_cpu_offset __my_cpu_offset()
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index ce0dbe7c1625..c4ae171850f8 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -32,5 +32,14 @@ struct psci_operations {
 };
 
 extern struct psci_operations psci_ops;
+extern struct smp_operations psci_smp_ops;
+
+#ifdef CONFIG_ARM_PSCI
+void psci_init(void);
+bool psci_smp_available(void);
+#else
+static inline void psci_init(void) { }
+static inline bool psci_smp_available(void) { return false; }
+#endif
 
 #endif /* __ASM_ARM_PSCI_H */
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 3d52ee1bfb31..04c99f36ff7f 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -45,6 +45,7 @@ struct pt_regs {
  */
 static inline int valid_user_regs(struct pt_regs *regs)
 {
+#ifndef CONFIG_CPU_V7M
         unsigned long mode = regs->ARM_cpsr & MODE_MASK;
 
         /*
@@ -67,6 +68,9 @@ static inline int valid_user_regs(struct pt_regs *regs)
                 regs->ARM_cpsr |= USR_MODE;
 
         return 0;
+#else /* ifndef CONFIG_CPU_V7M */
+        return 1;
+#endif
 }
 
 static inline long regs_return_value(struct pt_regs *regs)
diff --git a/arch/arm/include/asm/system_info.h b/arch/arm/include/asm/system_info.h
index dfd386d0c022..720ea0320a6d 100644
--- a/arch/arm/include/asm/system_info.h
+++ b/arch/arm/include/asm/system_info.h
@@ -11,6 +11,7 @@
 #define CPU_ARCH_ARMv5TEJ       7
 #define CPU_ARCH_ARMv6          8
 #define CPU_ARCH_ARMv7          9
+#define CPU_ARCH_ARMv7M         10
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index 99a19512ee26..bdf2b8458ec1 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -33,18 +33,6 @@
 #include <asm/pgalloc.h>
 #include <asm/tlbflush.h>
 
-/*
- * We need to delay page freeing for SMP as other CPUs can access pages
- * which have been removed but not yet had their TLB entries invalidated.
- * Also, as ARMv7 speculative prefetch can drag new entries into the TLB,
- * we need to apply this same delaying tactic to ensure correct operation.
- */
-#if defined(CONFIG_SMP) || defined(CONFIG_CPU_32v7)
-#define tlb_fast_mode(tlb)      0
-#else
-#define tlb_fast_mode(tlb)      1
-#endif
-
 #define MMU_GATHER_BUNDLE       8
 
 /*
@@ -112,12 +100,10 @@ static inline void __tlb_alloc_page(struct mmu_gather *tlb)
 static inline void tlb_flush_mmu(struct mmu_gather *tlb)
 {
         tlb_flush(tlb);
-        if (!tlb_fast_mode(tlb)) {
-                free_pages_and_swap_cache(tlb->pages, tlb->nr);
-                tlb->nr = 0;
-                if (tlb->pages == tlb->local)
-                        __tlb_alloc_page(tlb);
-        }
+        free_pages_and_swap_cache(tlb->pages, tlb->nr);
+        tlb->nr = 0;
+        if (tlb->pages == tlb->local)
+                __tlb_alloc_page(tlb);
 }
 
 static inline void
@@ -178,11 +164,6 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
 
 static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
 {
-        if (tlb_fast_mode(tlb)) {
-                free_page_and_swap_cache(page);
-                return 1; /* avoid calling tlb_flush_mmu */
-        }
-
         tlb->pages[tlb->nr++] = page;
         VM_BUG_ON(tlb->nr > tlb->max);
         return tlb->max - tlb->nr;
diff --git a/arch/arm/include/asm/v7m.h b/arch/arm/include/asm/v7m.h
new file mode 100644
index 000000000000..fa88d09fa3d9
--- /dev/null
+++ b/arch/arm/include/asm/v7m.h
@@ -0,0 +1,44 @@
+/*
+ * Common defines for v7m cpus
+ */
+#define V7M_SCS_ICTR                    IOMEM(0xe000e004)
+#define V7M_SCS_ICTR_INTLINESNUM_MASK           0x0000000f
+
+#define BASEADDR_V7M_SCB                IOMEM(0xe000ed00)
+
+#define V7M_SCB_CPUID                   0x00
+
+#define V7M_SCB_ICSR                    0x04
+#define V7M_SCB_ICSR_PENDSVSET                  (1 << 28)
+#define V7M_SCB_ICSR_PENDSVCLR                  (1 << 27)
+#define V7M_SCB_ICSR_RETTOBASE                  (1 << 11)
+
+#define V7M_SCB_VTOR                    0x08
+
+#define V7M_SCB_SCR                     0x10
+#define V7M_SCB_SCR_SLEEPDEEP                   (1 << 2)
+
+#define V7M_SCB_CCR                     0x14
+#define V7M_SCB_CCR_STKALIGN                    (1 << 9)
+
+#define V7M_SCB_SHPR2                   0x1c
+#define V7M_SCB_SHPR3                   0x20
+
+#define V7M_SCB_SHCSR                   0x24
+#define V7M_SCB_SHCSR_USGFAULTENA               (1 << 18)
+#define V7M_SCB_SHCSR_BUSFAULTENA               (1 << 17)
+#define V7M_SCB_SHCSR_MEMFAULTENA               (1 << 16)
+
+#define V7M_xPSR_FRAMEPTRALIGN                  0x00000200
+#define V7M_xPSR_EXCEPTIONNO                    0x000001ff
+
+/*
+ * When branching to an address that has bits [31:28] == 0xf an exception return
+ * occurs. Bits [27:5] are reserved (SBOP). If the processor implements the FP
+ * extension Bit [4] defines if the exception frame has space allocated for FP
+ * state information, SBOP otherwise. Bit [3] defines the mode that is returned
+ * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
+ * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
+ */
+#define EXC_RET_STACK_MASK                      0x00000004
+#define EXC_RET_THREADMODE_PROCESSSTACK         0xfffffffd
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
index 91d38e38a0b4..29da84e183f4 100644
--- a/arch/arm/include/debug/imx-uart.h
+++ b/arch/arm/include/debug/imx-uart.h
@@ -65,6 +65,14 @@
 #define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
 #define IMX6Q_UART_BASE(n)      IMX6Q_UART_BASE_ADDR(n)
 
+#define IMX6SL_UART1_BASE_ADDR  0x02020000
+#define IMX6SL_UART2_BASE_ADDR  0x02024000
+#define IMX6SL_UART3_BASE_ADDR  0x02034000
+#define IMX6SL_UART4_BASE_ADDR  0x02038000
+#define IMX6SL_UART5_BASE_ADDR  0x02018000
+#define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR
+#define IMX6SL_UART_BASE(n)     IMX6SL_UART_BASE_ADDR(n)
+
 #define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT)
 
 #ifdef CONFIG_DEBUG_IMX1_UART
@@ -83,6 +91,8 @@
 #define UART_PADDR      IMX_DEBUG_UART_BASE(IMX53)
 #elif defined(CONFIG_DEBUG_IMX6Q_UART)
 #define UART_PADDR      IMX_DEBUG_UART_BASE(IMX6Q)
+#elif defined(CONFIG_DEBUG_IMX6SL_UART)
+#define UART_PADDR      IMX_DEBUG_UART_BASE(IMX6SL)
 #endif
 
 #endif /* __DEBUG_IMX_UART_H */
diff --git a/arch/arm/include/debug/keystone.S b/arch/arm/include/debug/keystone.S
new file mode 100644
index 000000000000..9aef9ba3f4f0
--- /dev/null
+++ b/arch/arm/include/debug/keystone.S
@@ -0,0 +1,43 @@
+/*
+ * Early serial debug output macro for Keystone SOCs
+ *
+ * Copyright 2013 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * Based on RMKs low level debug code.
+ *  Copyright (C) 1994-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/serial_reg.h>
+
+#define UART_SHIFT 2
+#if defined(CONFIG_DEBUG_KEYSTONE_UART0)
+#define UART_PHYS               0x02530c00
+#define UART_VIRT               0xfeb30c00
+#elif defined(CONFIG_DEBUG_KEYSTONE_UART1)
+#define UART_PHYS               0x02531000
+#define UART_VIRT               0xfeb31000
+#endif
+
+        .macro  addruart, rp, rv, tmp
+        ldr     \rv, =UART_VIRT                 @ physical base address
+        ldr     \rp, =UART_PHYS                 @ virtual base address
+        .endm
+
+        .macro  senduart,rd,rx
+        str     \rd, [\rx, #UART_TX << UART_SHIFT]
+        .endm
+
+        .macro  busyuart,rd,rx
+1002:   ldr     \rd, [\rx, #UART_LSR << UART_SHIFT]
+        and     \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
+        teq     \rd, #UART_LSR_TEMT | UART_LSR_THRE
+        bne     1002b
+        .endm
+
+        .macro  waituart,rd,rx
+        .endm
diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S
index df191afa3be1..6517311a1c91 100644
--- a/arch/arm/include/debug/mvebu.S
+++ b/arch/arm/include/debug/mvebu.S
@@ -11,7 +11,12 @@
  * published by the Free Software Foundation.
 */
 
+#ifdef CONFIG_DEBUG_MVEBU_UART_ALTERNATE
+#define ARMADA_370_XP_REGS_PHYS_BASE    0xf1000000
+#else
 #define ARMADA_370_XP_REGS_PHYS_BASE    0xd0000000
+#endif
+
 #define ARMADA_370_XP_REGS_VIRT_BASE    0xfec00000
 
         .macro  addruart, rp, rv, tmp
diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/include/debug/u300.S
index 8ae8e4ab34b0..6f04f08a203c 100644
--- a/arch/arm/mach-u300/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/u300.S
@@ -1,14 +1,11 @@
 /*
- *
- * arch-arm/mach-u300/include/mach/debug-macro.S
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
+ * Copyright (C) 2006-2013 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
  * Debugging macro include header.
  * Author: Linus Walleij <linus.walleij@stericsson.com>
  */
-#include <mach/hardware.h>
+#define U300_SLOW_PER_PHYS_BASE         0xc0010000
+#define U300_SLOW_PER_VIRT_BASE         0xff000000
 
         .macro  addruart, rp, rv, tmp
         /* If we move the address using MMU, use this. */
diff --git a/arch/arm/include/uapi/asm/ptrace.h b/arch/arm/include/uapi/asm/ptrace.h
index 96ee0929790f..5af0ed1b825a 100644
--- a/arch/arm/include/uapi/asm/ptrace.h
+++ b/arch/arm/include/uapi/asm/ptrace.h
@@ -34,28 +34,47 @@
 
 /*
  * PSR bits
+ * Note on V7M there is no mode contained in the PSR
  */
 #define USR26_MODE      0x00000000
 #define FIQ26_MODE      0x00000001
 #define IRQ26_MODE      0x00000002
 #define SVC26_MODE      0x00000003
+#if defined(__KERNEL__) && defined(CONFIG_CPU_V7M)
+/*
+ * Use 0 here to get code right that creates a userspace
+ * or kernel space thread.
+ */
+#define USR_MODE        0x00000000
+#define SVC_MODE        0x00000000
+#else
 #define USR_MODE        0x00000010
+#define SVC_MODE        0x00000013
+#endif
 #define FIQ_MODE        0x00000011
 #define IRQ_MODE        0x00000012
-#define SVC_MODE        0x00000013
 #define ABT_MODE        0x00000017
 #define HYP_MODE        0x0000001a
 #define UND_MODE        0x0000001b
 #define SYSTEM_MODE     0x0000001f
 #define MODE32_BIT      0x00000010
 #define MODE_MASK       0x0000001f
-#define PSR_T_BIT       0x00000020
-#define PSR_F_BIT       0x00000040
-#define PSR_I_BIT       0x00000080
-#define PSR_A_BIT       0x00000100
-#define PSR_E_BIT       0x00000200
-#define PSR_J_BIT       0x01000000
-#define PSR_Q_BIT       0x08000000
+
+#define V4_PSR_T_BIT    0x00000020      /* >= V4T, but not V7M */
+#define V7M_PSR_T_BIT   0x01000000
+#if defined(__KERNEL__) && defined(CONFIG_CPU_V7M)
+#define PSR_T_BIT       V7M_PSR_T_BIT
+#else
+/* for compatibility */
+#define PSR_T_BIT       V4_PSR_T_BIT
+#endif
+
+#define PSR_F_BIT       0x00000040      /* >= V4, but not V7M */
+#define PSR_I_BIT       0x00000080      /* >= V4, but not V7M */
+#define PSR_A_BIT       0x00000100      /* >= V6, but not V7M */
+#define PSR_E_BIT       0x00000200      /* >= V6, but not V7M */
+#define PSR_J_BIT       0x01000000      /* >= V5J, but not V7M */
+#define PSR_Q_BIT       0x08000000      /* >= V5E, including V7M */
 #define PSR_V_BIT       0x10000000
 #define PSR_C_BIT       0x20000000
 #define PSR_Z_BIT       0x40000000
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 5f3338eacad2..f4285b5ffb05 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -15,7 +15,7 @@ CFLAGS_REMOVE_return_address.o = -pg
 
 # Object file lists.
 
-obj-y           := elf.o entry-armv.o entry-common.o irq.o opcodes.o \
+obj-y           := elf.o entry-common.o irq.o opcodes.o \
                    process.o ptrace.o return_address.o sched_clock.o \
                    setup.o signal.o stacktrace.o sys_arm.o time.o traps.o
 
@@ -23,6 +23,12 @@ obj-$(CONFIG_ATAGS)		+= atags_parse.o
 obj-$(CONFIG_ATAGS_PROC)        += atags_proc.o
 obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += atags_compat.o
 
+ifeq ($(CONFIG_CPU_V7M),y)
+obj-y           += entry-v7m.o
+else
+obj-y           += entry-armv.o
+endif
+
 obj-$(CONFIG_OC_ETM)            += etm.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 obj-$(CONFIG_ISA_DMA_API)       += dma.o
@@ -82,6 +88,9 @@ obj-$(CONFIG_DEBUG_LL)	+= debug.o
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
 
 obj-$(CONFIG_ARM_VIRT_EXT)      += hyp-stub.o
-obj-$(CONFIG_ARM_PSCI)          += psci.o
+ifeq ($(CONFIG_ARM_PSCI),y)
+obj-y                           += psci.o
+obj-$(CONFIG_SMP)               += psci_smp.o
+endif
 
 extra-y := $(head-y) vmlinux.lds
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index b2ed73c45489..261fcc826169 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -445,7 +445,8 @@ static int pcibios_init_resources(int busnr, struct pci_sys_data *sys)
         return 0;
 }
 
-static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
+static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
+                            struct list_head *head)
 {
         struct pci_sys_data *sys = NULL;
         int ret;
@@ -480,7 +481,7 @@ static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
                         if (hw->scan)
                                 sys->bus = hw->scan(nr, sys);
                         else
-                                sys->bus = pci_scan_root_bus(NULL, sys->busnr,
+                                sys->bus = pci_scan_root_bus(parent, sys->busnr,
                                                 hw->ops, sys, &sys->resources);
 
                         if (!sys->bus)
@@ -497,7 +498,7 @@ static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
         }
 }
 
-void pci_common_init(struct hw_pci *hw)
+void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
 {
         struct pci_sys_data *sys;
         LIST_HEAD(head);
@@ -505,7 +506,7 @@ void pci_common_init(struct hw_pci *hw)
         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
         if (hw->preinit)
                 hw->preinit();
-        pcibios_init_hw(hw, &head);
+        pcibios_init_hw(parent, hw, &head);
         if (hw->postinit)
                 hw->postinit();
 
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index bc5bc0a97131..85a72b0809ca 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -350,6 +350,9 @@ ENDPROC(ftrace_stub)
 
         .align  5
 ENTRY(vector_swi)
+#ifdef CONFIG_CPU_V7M
+        v7m_exception_entry
+#else
         sub     sp, sp, #S_FRAME_SIZE
         stmia   sp, {r0 - r12}                  @ Calling r0 - r12
  ARM(   add     r8, sp, #S_PC           )
@@ -360,6 +363,7 @@ ENTRY(vector_swi)
         str     lr, [sp, #S_PC]                 @ Save calling PC
         str     r8, [sp, #S_PSR]                @ Save CPSR
         str     r0, [sp, #S_OLD_R0]             @ Save OLD_R0
+#endif
         zero_fp
 
         /*
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 160f3376ba6d..de23a9beed13 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -5,6 +5,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/errno.h>
 #include <asm/thread_info.h>
+#include <asm/v7m.h>
 
 @ Bad Abort numbers
 @ -----------------
@@ -44,6 +45,116 @@
 #endif
         .endm
 
+#ifdef CONFIG_CPU_V7M
+/*
+ * ARMv7-M exception entry/exit macros.
+ *
+ * xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are
+ * automatically saved on the current stack (32 words) before
+ * switching to the exception stack (SP_main).
+ *
+ * If exception is taken while in user mode, SP_main is
+ * empty. Otherwise, SP_main is aligned to 64 bit automatically
+ * (CCR.STKALIGN set).
+ *
+ * Linux assumes that the interrupts are disabled when entering an
+ * exception handler and it may BUG if this is not the case. Interrupts
+ * are disabled during entry and reenabled in the exit macro.
+ *
+ * v7m_exception_slow_exit is used when returning from SVC or PendSV.
+ * When returning to kernel mode, we don't return from exception.
+ */
+        .macro  v7m_exception_entry
+        @ determine the location of the registers saved by the core during
+        @ exception entry. Depending on the mode the cpu was in when the
+        @ exception happend that is either on the main or the process stack.
+        @ Bit 2 of EXC_RETURN stored in the lr register specifies which stack
+        @ was used.
+        tst     lr, #EXC_RET_STACK_MASK
+        mrsne   r12, psp
+        moveq   r12, sp
+
+        @ we cannot rely on r0-r3 and r12 matching the value saved in the
+        @ exception frame because of tail-chaining. So these have to be
+        @ reloaded.
+        ldmia   r12!, {r0-r3}
+
+        @ Linux expects to have irqs off. Do it here before taking stack space
+        cpsid   i
+
+        sub     sp, #S_FRAME_SIZE-S_IP
+        stmdb   sp!, {r0-r11}
+
+        @ load saved r12, lr, return address and xPSR.
+        @ r0-r7 are used for signals and never touched from now on. Clobbering
+        @ r8-r12 is OK.
+        mov     r9, r12
+        ldmia   r9!, {r8, r10-r12}
+
+        @ calculate the original stack pointer value.
+        @ r9 currently points to the memory location just above the auto saved
+        @ xPSR.
+        @ The cpu might automatically 8-byte align the stack. Bit 9
+        @ of the saved xPSR specifies if stack aligning took place. In this case
+        @ another 32-bit value is included in the stack.
+
+        tst     r12, V7M_xPSR_FRAMEPTRALIGN
+        addne   r9, r9, #4
+
+        @ store saved r12 using str to have a register to hold the base for stm
+        str     r8, [sp, #S_IP]
+        add     r8, sp, #S_SP
+        @ store r13-r15, xPSR
+        stmia   r8!, {r9-r12}
+        @ store old_r0
+        str     r0, [r8]
+        .endm
+
+        /*
+         * PENDSV and SVCALL are configured to have the same exception
+         * priorities. As a kernel thread runs at SVCALL execution priority it
+         * can never be preempted and so we will never have to return to a
+         * kernel thread here.
+         */
+        .macro  v7m_exception_slow_exit ret_r0
+        cpsid   i
+        ldr     lr, =EXC_RET_THREADMODE_PROCESSSTACK
+
+        @ read original r12, sp, lr, pc and xPSR
+        add     r12, sp, #S_IP
+        ldmia   r12, {r1-r5}
+
+        @ an exception frame is always 8-byte aligned. To tell the hardware if
+        @ the sp to be restored is aligned or not set bit 9 of the saved xPSR
+        @ accordingly.
+        tst     r2, #4
+        subne   r2, r2, #4
+        orrne   r5, V7M_xPSR_FRAMEPTRALIGN
+        biceq   r5, V7M_xPSR_FRAMEPTRALIGN
+
+        @ write basic exception frame
+        stmdb   r2!, {r1, r3-r5}
+        ldmia   sp, {r1, r3-r5}
+        .if     \ret_r0
+        stmdb   r2!, {r0, r3-r5}
+        .else
+        stmdb   r2!, {r1, r3-r5}
+        .endif
+
+        @ restore process sp
+        msr     psp, r2
+
+        @ restore original r4-r11
+        ldmia   sp!, {r0-r11}
+
+        @ restore main sp
+        add     sp, sp, #S_FRAME_SIZE-S_IP
+
+        cpsie   i
+        bx      lr
+        .endm
+#endif  /* CONFIG_CPU_V7M */
+
         @
         @ Store/load the USER SP and LR registers by switching to the SYS
         @ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not
@@ -165,6 +276,18 @@
         rfeia   sp!
         .endm
 
+#ifdef CONFIG_CPU_V7M
+        /*
+         * Note we don't need to do clrex here as clearing the local monitor is
+         * part of each exception entry and exit sequence.
+         */
+        .macro  restore_user_regs, fast = 0, offset = 0
+        .if     \offset
+        add     sp, #\offset
+        .endif
+        v7m_exception_slow_exit ret_r0 = \fast
+        .endm
+#else   /* ifdef CONFIG_CPU_V7M */
         .macro  restore_user_regs, fast = 0, offset = 0
         clrex                                   @ clear the exclusive monitor
         mov     r2, sp
@@ -181,6 +304,7 @@
         add     sp, sp, #S_FRAME_SIZE - S_SP
         movs    pc, lr                          @ return & move spsr_svc into cpsr
         .endm
+#endif  /* ifdef CONFIG_CPU_V7M / else */
 
         .macro  get_thread_info, rd
         mov     \rd, sp
diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S
new file mode 100644
index 000000000000..e00621f1403f
--- /dev/null
+++ b/arch/arm/kernel/entry-v7m.S
@@ -0,0 +1,143 @@
+/*
+ * linux/arch/arm/kernel/entry-v7m.S
+ *
+ * Copyright (C) 2008 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Low-level vector interface routines for the ARMv7-M architecture
+ */
+#include <asm/memory.h>
+#include <asm/glue.h>
+#include <asm/thread_notify.h>
+#include <asm/v7m.h>
+
+#include <mach/entry-macro.S>
+
+#include "entry-header.S"
+
+#ifdef CONFIG_TRACE_IRQFLAGS
+#error "CONFIG_TRACE_IRQFLAGS not supported on the current ARMv7M implementation"
+#endif
+
+__invalid_entry:
+        v7m_exception_entry
+        adr     r0, strerr
+        mrs     r1, ipsr
+        mov     r2, lr
+        bl      printk
+        mov     r0, sp
+        bl      show_regs
+1:      b       1b
+ENDPROC(__invalid_entry)
+
+strerr: .asciz  "\nUnhandled exception: IPSR = %08lx LR = %08lx\n"
+
+        .align  2
+__irq_entry:
+        v7m_exception_entry
+
+        @
+        @ Invoke the IRQ handler
+        @
+        mrs     r0, ipsr
+        ldr     r1, =V7M_xPSR_EXCEPTIONNO
+        and     r0, r1
+        sub     r0, #16
+        mov     r1, sp
+        stmdb   sp!, {lr}
+        @ routine called with r0 = irq number, r1 = struct pt_regs *
+        bl      nvic_do_IRQ
+
+        pop     {lr}
+        @
+        @ Check for any pending work if returning to user
+        @
+        ldr     r1, =BASEADDR_V7M_SCB
+        ldr     r0, [r1, V7M_SCB_ICSR]
+        tst     r0, V7M_SCB_ICSR_RETTOBASE
+        beq     2f
+
+        get_thread_info tsk
+        ldr     r2, [tsk, #TI_FLAGS]
+        tst     r2, #_TIF_WORK_MASK
+        beq     2f                      @ no work pending
+        mov     r0, #V7M_SCB_ICSR_PENDSVSET
+        str     r0, [r1, V7M_SCB_ICSR]  @ raise PendSV
+
+2:
+        @ registers r0-r3 and r12 are automatically restored on exception
+        @ return. r4-r7 were not clobbered in v7m_exception_entry so for
+        @ correctness they don't need to be restored. So only r8-r11 must be
+        @ restored here. The easiest way to do so is to restore r0-r7, too.
+        ldmia   sp!, {r0-r11}
+        add     sp, #S_FRAME_SIZE-S_IP
+        cpsie   i
+        bx      lr
+ENDPROC(__irq_entry)
+
+__pendsv_entry:
+        v7m_exception_entry
+
+        ldr     r1, =BASEADDR_V7M_SCB
+        mov     r0, #V7M_SCB_ICSR_PENDSVCLR
+        str     r0, [r1, V7M_SCB_ICSR]  @ clear PendSV
+
+        @ execute the pending work, including reschedule
+        get_thread_info tsk
+        mov     why, #0
+        b       ret_to_user
+ENDPROC(__pendsv_entry)
+
+/*
+ * Register switch for ARMv7-M processors.
+ * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
+ * previous and next are guaranteed not to be the same.
+ */
+ENTRY(__switch_to)
+        .fnstart
+        .cantunwind
+        add     ip, r1, #TI_CPU_SAVE
+        stmia   ip!, {r4 - r11}         @ Store most regs on stack
+        str     sp, [ip], #4
+        str     lr, [ip], #4
+        mov     r5, r0
+        add     r4, r2, #TI_CPU_SAVE
+        ldr     r0, =thread_notify_head
+        mov     r1, #THREAD_NOTIFY_SWITCH
+        bl      atomic_notifier_call_chain
+        mov     ip, r4
+        mov     r0, r5
+        ldmia   ip!, {r4 - r11}         @ Load all regs saved previously
+        ldr     sp, [ip]
+        ldr     pc, [ip, #4]!
+        .fnend
+ENDPROC(__switch_to)
+
+        .data
+        .align  8
+/*
+ * Vector table (64 words => 256 bytes natural alignment)
+ */
+ENTRY(vector_table)
+        .long   0                       @ 0 - Reset stack pointer
+        .long   __invalid_entry         @ 1 - Reset
+        .long   __invalid_entry         @ 2 - NMI
+        .long   __invalid_entry         @ 3 - HardFault
+        .long   __invalid_entry         @ 4 - MemManage
+        .long   __invalid_entry         @ 5 - BusFault
+        .long   __invalid_entry         @ 6 - UsageFault
+        .long   __invalid_entry         @ 7 - Reserved
+        .long   __invalid_entry         @ 8 - Reserved
+        .long   __invalid_entry         @ 9 - Reserved
+        .long   __invalid_entry         @ 10 - Reserved
+        .long   vector_swi              @ 11 - SVCall
+        .long   __invalid_entry         @ 12 - Debug Monitor
+        .long   __invalid_entry         @ 13 - Reserved
+        .long   __pendsv_entry          @ 14 - PendSV
+        .long   __invalid_entry         @ 15 - SysTick
+        .rept   64 - 16
+        .long   __irq_entry             @ 16..64 - External Interrupts
+        .endr
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 6a2e09c952c7..8812ce88f7a1 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -19,6 +19,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/cp15.h>
 #include <asm/thread_info.h>
+#include <asm/v7m.h>
 
 /*
  * Kernel startup entry point.
@@ -50,10 +51,13 @@ ENTRY(stext)
 
         setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
                                                 @ and irqs disabled
-#ifndef CONFIG_CPU_CP15
-        ldr     r9, =CONFIG_PROCESSOR_ID
-#else
+#if defined(CONFIG_CPU_CP15)
         mrc     p15, 0, r9, c0, c0              @ get processor id
+#elif defined(CONFIG_CPU_V7M)
+        ldr     r9, =BASEADDR_V7M_SCB
+        ldr     r9, [r9, V7M_SCB_CPUID]
+#else
+        ldr     r9, =CONFIG_PROCESSOR_ID
 #endif
         bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
         movs    r10, r5                         @ invalid processor (r5=0)?
diff --git a/arch/arm/kernel/psci.c b/arch/arm/kernel/psci.c
index 36531643cc2c..46931880093d 100644
--- a/arch/arm/kernel/psci.c
+++ b/arch/arm/kernel/psci.c
@@ -158,7 +158,7 @@ static const struct of_device_id psci_of_match[] __initconst = {
         {},
 };
 
-static int __init psci_init(void)
+void __init psci_init(void)
 {
         struct device_node *np;
         const char *method;
@@ -166,7 +166,7 @@ static int __init psci_init(void)
 
         np = of_find_matching_node(NULL, psci_of_match);
         if (!np)
-                return 0;
+                return;
 
         pr_info("probing function IDs from device-tree\n");
 
@@ -206,6 +206,5 @@ static int __init psci_init(void)
 
 out_put_node:
         of_node_put(np);
-        return 0;
+        return;
 }
-early_initcall(psci_init);
diff --git a/arch/arm/kernel/psci_smp.c b/arch/arm/kernel/psci_smp.c
new file mode 100644
index 000000000000..23a11424c568
--- /dev/null
+++ b/arch/arm/kernel/psci_smp.c
@@ -0,0 +1,84 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * Author: Will Deacon <will.deacon@arm.com>
+ */
+
+#include <linux/init.h>
+#include <linux/irqchip/arm-gic.h>
+#include <linux/smp.h>
+#include <linux/of.h>
+
+#include <asm/psci.h>
+#include <asm/smp_plat.h>
+
+/*
+ * psci_smp assumes that the following is true about PSCI:
+ *
+ * cpu_suspend   Suspend the execution on a CPU
+ * @state        we don't currently describe affinity levels, so just pass 0.
+ * @entry_point  the first instruction to be executed on return
+ * returns 0  success, < 0 on failure
+ *
+ * cpu_off       Power down a CPU
+ * @state        we don't currently describe affinity levels, so just pass 0.
+ * no return on successful call
+ *
+ * cpu_on        Power up a CPU
+ * @cpuid        cpuid of target CPU, as from MPIDR
+ * @entry_point  the first instruction to be executed on return
+ * returns 0  success, < 0 on failure
+ *
+ * migrate       Migrate the context to a different CPU
+ * @cpuid        cpuid of target CPU, as from MPIDR
+ * returns 0  success, < 0 on failure
+ *
+ */
+
+extern void secondary_startup(void);
+
+static int __cpuinit psci_boot_secondary(unsigned int cpu,
+                                         struct task_struct *idle)
+{
+        if (psci_ops.cpu_on)
+                return psci_ops.cpu_on(cpu_logical_map(cpu),
+                                       __pa(secondary_startup));
+        return -ENODEV;
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+void __ref psci_cpu_die(unsigned int cpu)
+{
+       const struct psci_power_state ps = {
+               .type = PSCI_POWER_STATE_TYPE_POWER_DOWN,
+       };
+
+       if (psci_ops.cpu_off)
+               psci_ops.cpu_off(ps);
+
+       /* We should never return */
+       panic("psci: cpu %d failed to shutdown\n", cpu);
+}
+#else
+#define psci_cpu_die NULL
+#endif
+
+bool __init psci_smp_available(void)
+{
+        /* is cpu_on available at least? */
+        return (psci_ops.cpu_on != NULL);
+}
+
+struct smp_operations __initdata psci_smp_ops = {
+        .smp_boot_secondary     = psci_boot_secondary,
+        .cpu_die                = psci_cpu_die,
+};
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 1522c7ae31b0..a1a2fbaaa31c 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -37,6 +37,7 @@
 #include <asm/cputype.h>
 #include <asm/elf.h>
 #include <asm/procinfo.h>
+#include <asm/psci.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
 #include <asm/smp_plat.h>
@@ -128,7 +129,9 @@ struct stack {
         u32 und[3];
 } ____cacheline_aligned;
 
+#ifndef CONFIG_CPU_V7M
 static struct stack stacks[NR_CPUS];
+#endif
 
 char elf_platform[ELF_PLATFORM_SIZE];
 EXPORT_SYMBOL(elf_platform);
@@ -207,7 +210,7 @@ static const char *proc_arch[] = {
         "5TEJ",
         "6TEJ",
         "7",
-        "?(11)",
+        "7M",
         "?(12)",
         "?(13)",
         "?(14)",
@@ -216,6 +219,12 @@ static const char *proc_arch[] = {
         "?(17)",
 };
 
+#ifdef CONFIG_CPU_V7M
+static int __get_cpu_architecture(void)
+{
+        return CPU_ARCH_ARMv7M;
+}
+#else
 static int __get_cpu_architecture(void)
 {
         int cpu_arch;
@@ -248,6 +257,7 @@ static int __get_cpu_architecture(void)
 
         return cpu_arch;
 }
+#endif
 
 int __pure cpu_architecture(void)
 {
@@ -293,7 +303,9 @@ static void __init cacheid_init(void)
 {
         unsigned int arch = cpu_architecture();
 
-        if (arch >= CPU_ARCH_ARMv6) {
+        if (arch == CPU_ARCH_ARMv7M) {
+                cacheid = 0;
+        } else if (arch >= CPU_ARCH_ARMv6) {
                 unsigned int cachetype = read_cpuid_cachetype();
                 if ((cachetype & (7 << 29)) == 4 << 29) {
                         /* ARMv7 register format */
@@ -392,6 +404,7 @@ static void __init feat_v6_fixup(void)
  */
 void notrace cpu_init(void)
 {
+#ifndef CONFIG_CPU_V7M
         unsigned int cpu = smp_processor_id();
         struct stack *stk = &stacks[cpu];
 
@@ -442,6 +455,7 @@ void notrace cpu_init(void)
               "I" (offsetof(struct stack, und[0])),
               PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
             : "r14");
+#endif
 }
 
 int __cpu_logical_map[NR_CPUS];
@@ -796,9 +810,15 @@ void __init setup_arch(char **cmdline_p)
         unflatten_device_tree();
 
         arm_dt_init_cpu_maps();
+        psci_init();
 #ifdef CONFIG_SMP
         if (is_smp()) {
-                smp_set_ops(mdesc->smp);
+                if (!mdesc->smp_init || !mdesc->smp_init()) {
+                        if (psci_smp_available())
+                                smp_set_ops(&psci_smp_ops);
+                        else if (mdesc->smp)
+                                smp_set_ops(mdesc->smp);
+                }
                 smp_init_cpus();
         }
 #endif
diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c
index f10316b4ecdc..c5a59546a256 100644
--- a/arch/arm/kernel/topology.c
+++ b/arch/arm/kernel/topology.c
@@ -13,6 +13,7 @@
 
 #include <linux/cpu.h>
 #include <linux/cpumask.h>
+#include <linux/export.h>
 #include <linux/init.h>
 #include <linux/percpu.h>
 #include <linux/node.h>
@@ -200,6 +201,7 @@ static inline void update_cpu_power(unsigned int cpuid, unsigned int mpidr) {}
  * cpu topology table
  */
 struct cputopo_arm cpu_topology[NR_CPUS];
+EXPORT_SYMBOL_GPL(cpu_topology);
 
 const struct cpumask *cpu_coregroup_mask(int cpu)
 {
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 18b32e8e4497..486e12a0f26a 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -812,6 +812,7 @@ static void __init kuser_get_tls_init(unsigned long vectors)
 
 void __init early_trap_init(void *vectors_base)
 {
+#ifndef CONFIG_CPU_V7M
         unsigned long vectors = (unsigned long)vectors_base;
         extern char __stubs_start[], __stubs_end[];
         extern char __vectors_start[], __vectors_end[];
@@ -843,4 +844,11 @@ void __init early_trap_init(void *vectors_base)
 
         flush_icache_range(vectors, vectors + PAGE_SIZE);
         modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
+#else /* ifndef CONFIG_CPU_V7M */
+        /*
+         * on V7-M there is no need to copy the vector table to a dedicated
+         * memory area. The address is configurable and so a table in the kernel
+         * image can be used.
+         */
+#endif
 }
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index 37d216d814cd..ef1703b9587b 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -492,6 +492,11 @@ static void vcpu_pause(struct kvm_vcpu *vcpu)
         wait_event_interruptible(*wq, !vcpu->arch.pause);
 }
 
+static int kvm_vcpu_initialized(struct kvm_vcpu *vcpu)
+{
+        return vcpu->arch.target >= 0;
+}
+
 /**
  * kvm_arch_vcpu_ioctl_run - the main VCPU run function to execute guest code
  * @vcpu:       The VCPU pointer
@@ -508,8 +513,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
         int ret;
         sigset_t sigsaved;
 
-        /* Make sure they initialize the vcpu with KVM_ARM_VCPU_INIT */
-        if (unlikely(vcpu->arch.target < 0))
+        if (unlikely(!kvm_vcpu_initialized(vcpu)))
                 return -ENOEXEC;
 
         ret = kvm_vcpu_first_run_init(vcpu);
@@ -710,6 +714,10 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
         case KVM_SET_ONE_REG:
         case KVM_GET_ONE_REG: {
                 struct kvm_one_reg reg;
+
+                if (unlikely(!kvm_vcpu_initialized(vcpu)))
+                        return -ENOEXEC;
+
                 if (copy_from_user(&reg, argp, sizeof(reg)))
                         return -EFAULT;
                 if (ioctl == KVM_SET_ONE_REG)
@@ -722,6 +730,9 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
                 struct kvm_reg_list reg_list;
                 unsigned n;
 
+                if (unlikely(!kvm_vcpu_initialized(vcpu)))
+                        return -ENOEXEC;
+
                 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
                         return -EFAULT;
                 n = reg_list.n;
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 965706578f13..84ba67b982c0 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -43,7 +43,14 @@ static phys_addr_t hyp_idmap_vector;
 
 static void kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
 {
-        kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, kvm, ipa);
+        /*
+         * This function also gets called when dealing with HYP page
+         * tables. As HYP doesn't have an associated struct kvm (and
+         * the HYP page tables are fairly static), we don't do
+         * anything there.
+         */
+        if (kvm)
+                kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, kvm, ipa);
 }
 
 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
@@ -78,18 +85,20 @@ static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
         return p;
 }
 
-static void clear_pud_entry(pud_t *pud)
+static void clear_pud_entry(struct kvm *kvm, pud_t *pud, phys_addr_t addr)
 {
         pmd_t *pmd_table = pmd_offset(pud, 0);
         pud_clear(pud);
+        kvm_tlb_flush_vmid_ipa(kvm, addr);
         pmd_free(NULL, pmd_table);
         put_page(virt_to_page(pud));
 }
 
-static void clear_pmd_entry(pmd_t *pmd)
+static void clear_pmd_entry(struct kvm *kvm, pmd_t *pmd, phys_addr_t addr)
 {
         pte_t *pte_table = pte_offset_kernel(pmd, 0);
         pmd_clear(pmd);
+        kvm_tlb_flush_vmid_ipa(kvm, addr);
         pte_free_kernel(NULL, pte_table);
         put_page(virt_to_page(pmd));
 }
@@ -100,11 +109,12 @@ static bool pmd_empty(pmd_t *pmd)
         return page_count(pmd_page) == 1;
 }
 
-static void clear_pte_entry(pte_t *pte)
+static void clear_pte_entry(struct kvm *kvm, pte_t *pte, phys_addr_t addr)
 {
         if (pte_present(*pte)) {
                 kvm_set_pte(pte, __pte(0));
                 put_page(virt_to_page(pte));
+                kvm_tlb_flush_vmid_ipa(kvm, addr);
         }
 }
 
@@ -114,7 +124,8 @@ static bool pte_empty(pte_t *pte)
         return page_count(pte_page) == 1;
 }
 
-static void unmap_range(pgd_t *pgdp, unsigned long long start, u64 size)
+static void unmap_range(struct kvm *kvm, pgd_t *pgdp,
+                        unsigned long long start, u64 size)
 {
         pgd_t *pgd;
         pud_t *pud;
@@ -138,15 +149,15 @@ static void unmap_range(pgd_t *pgdp, unsigned long long start, u64 size)
                 }
 
                 pte = pte_offset_kernel(pmd, addr);
-                clear_pte_entry(pte);
+                clear_pte_entry(kvm, pte, addr);
                 range = PAGE_SIZE;
 
                 /* If we emptied the pte, walk back up the ladder */
                 if (pte_empty(pte)) {
-                        clear_pmd_entry(pmd);
+                        clear_pmd_entry(kvm, pmd, addr);
                         range = PMD_SIZE;
                         if (pmd_empty(pmd)) {
-                                clear_pud_entry(pud);
+                                clear_pud_entry(kvm, pud, addr);
                                 range = PUD_SIZE;
                         }
                 }
@@ -165,14 +176,14 @@ void free_boot_hyp_pgd(void)
         mutex_lock(&kvm_hyp_pgd_mutex);
 
         if (boot_hyp_pgd) {
-                unmap_range(boot_hyp_pgd, hyp_idmap_start, PAGE_SIZE);
-                unmap_range(boot_hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
+                unmap_range(NULL, boot_hyp_pgd, hyp_idmap_start, PAGE_SIZE);
+                unmap_range(NULL, boot_hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
                 kfree(boot_hyp_pgd);
                 boot_hyp_pgd = NULL;
         }
 
         if (hyp_pgd)
-                unmap_range(hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
+                unmap_range(NULL, hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
 
         kfree(init_bounce_page);
         init_bounce_page = NULL;
@@ -200,9 +211,10 @@ void free_hyp_pgds(void)
 
         if (hyp_pgd) {
                 for (addr = PAGE_OFFSET; virt_addr_valid(addr); addr += PGDIR_SIZE)
-                        unmap_range(hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE);
+                        unmap_range(NULL, hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE);
                 for (addr = VMALLOC_START; is_vmalloc_addr((void*)addr); addr += PGDIR_SIZE)
-                        unmap_range(hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE);
+                        unmap_range(NULL, hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE);
+
                 kfree(hyp_pgd);
                 hyp_pgd = NULL;
         }
@@ -393,7 +405,7 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm)
  */
 static void unmap_stage2_range(struct kvm *kvm, phys_addr_t start, u64 size)
 {
-        unmap_range(kvm->arch.pgd, start, size);
+        unmap_range(kvm, kvm->arch.pgd, start, size);
 }
 
 /**
@@ -675,7 +687,6 @@ static void handle_hva_to_gpa(struct kvm *kvm,
 static void kvm_unmap_hva_handler(struct kvm *kvm, gpa_t gpa, void *data)
 {
         unmap_stage2_range(kvm, gpa, PAGE_SIZE);
-        kvm_tlb_flush_vmid_ipa(kvm, gpa);
 }
 
 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index 2d00165e85ec..01ad4d41e728 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -22,8 +22,7 @@ config ARCH_CLEP7312
 
 config ARCH_EDB7211
         bool "EDB7211"
-        select ARCH_SELECT_MEMORY_MODEL
-        select ARCH_SPARSEMEM_ENABLE
+        select ARCH_HAS_HOLES_MEMORYMODEL
         help
           Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211
           evaluation board.
diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
index 992995af666a..f30ed2b496fb 100644
--- a/arch/arm/mach-clps711x/Makefile
+++ b/arch/arm/mach-clps711x/Makefile
@@ -4,10 +4,7 @@
 
 # Object file lists.
 
-obj-y                   := common.o
-obj-m                   :=
-obj-n                   :=
-obj-                    :=
+obj-y                           := common.o devices.o
 
 obj-$(CONFIG_ARCH_AUTCPU12)     += board-autcpu12.o
 obj-$(CONFIG_ARCH_CDB89712)     += board-cdb89712.o
diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c
index f38584709df7..5867aebd8d0c 100644
--- a/arch/arm/mach-clps711x/board-autcpu12.c
+++ b/arch/arm/mach-clps711x/board-autcpu12.c
@@ -26,6 +26,8 @@
 #include <linux/gpio.h>
 #include <linux/ioport.h>
 #include <linux/interrupt.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/plat-ram.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand-gpio.h>
 #include <linux/platform_device.h>
@@ -40,38 +42,49 @@
 #include <asm/page.h>
 
 #include <asm/mach/map.h>
-#include <mach/autcpu12.h>
 
 #include "common.h"
+#include "devices.h"
 
-#define AUTCPU12_CS8900_BASE    (CS2_PHYS_BASE + 0x300)
-#define AUTCPU12_CS8900_IRQ     (IRQ_EINT3)
+/* NOR flash */
+#define AUTCPU12_FLASH_BASE     (CS0_PHYS_BASE)
+
+/* Board specific hardware definitions */
+#define AUTCPU12_CHAR_LCD_BASE  (CS1_PHYS_BASE + 0x00000000)
+#define AUTCPU12_CSAUX1_BASE    (CS1_PHYS_BASE + 0x04000000)
+#define AUTCPU12_CAN_BASE       (CS1_PHYS_BASE + 0x08000000)
+#define AUTCPU12_TOUCH_BASE     (CS1_PHYS_BASE + 0x0a000000)
+#define AUTCPU12_IO_BASE        (CS1_PHYS_BASE + 0x0c000000)
+#define AUTCPU12_LPT_BASE       (CS1_PHYS_BASE + 0x0e000000)
+
+/* NVRAM */
+#define AUTCPU12_NVRAM_BASE     (CS1_PHYS_BASE + 0x02000000)
 
+/* SmartMedia flash */
 #define AUTCPU12_SMC_BASE       (CS1_PHYS_BASE + 0x06000000)
 #define AUTCPU12_SMC_SEL_BASE   (AUTCPU12_SMC_BASE + 0x10)
 
+/* Ethernet */
+#define AUTCPU12_CS8900_BASE    (CS2_PHYS_BASE + 0x300)
+#define AUTCPU12_CS8900_IRQ     (IRQ_EINT3)
+
+/* NAND flash */
 #define AUTCPU12_MMGPIO_BASE    (CLPS711X_NR_GPIO)
 #define AUTCPU12_SMC_NCE        (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */
 #define AUTCPU12_SMC_RDY        CLPS711X_GPIO(1, 2)
 #define AUTCPU12_SMC_ALE        CLPS711X_GPIO(1, 3)
 #define AUTCPU12_SMC_CLE        CLPS711X_GPIO(1, 3)
 
+/* LCD contrast digital potentiometer */
+#define AUTCPU12_DPOT_CS        CLPS711X_GPIO(4, 0)
+#define AUTCPU12_DPOT_CLK       CLPS711X_GPIO(4, 1)
+#define AUTCPU12_DPOT_UD        CLPS711X_GPIO(4, 2)
+
 static struct resource autcpu12_cs8900_resource[] __initdata = {
         DEFINE_RES_MEM(AUTCPU12_CS8900_BASE, SZ_1K),
         DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ),
 };
 
-static struct resource autcpu12_nvram_resource[] __initdata = {
-        DEFINE_RES_MEM_NAMED(AUTCPU12_PHYS_NVRAM, SZ_128K, "SRAM"),
-};
-
-static struct platform_device autcpu12_nvram_pdev __initdata = {
-        .name           = "autcpu12_nvram",
-        .id             = -1,
-        .resource       = autcpu12_nvram_resource,
-        .num_resources  = ARRAY_SIZE(autcpu12_nvram_resource),
-};
-
 static struct resource autcpu12_nand_resource[] __initdata = {
         DEFINE_RES_MEM(AUTCPU12_SMC_BASE, SZ_16),
 };
@@ -147,17 +160,106 @@ static struct platform_device autcpu12_mmgpio_pdev __initdata = {
         },
 };
 
+static const struct gpio autcpu12_gpios[] __initconst = {
+        { AUTCPU12_DPOT_CS,     GPIOF_OUT_INIT_HIGH,    "DPOT CS" },
+        { AUTCPU12_DPOT_CLK,    GPIOF_OUT_INIT_LOW,     "DPOT CLK" },
+        { AUTCPU12_DPOT_UD,     GPIOF_OUT_INIT_LOW,     "DPOT UD" },
+};
+
+static struct mtd_partition autcpu12_flash_partitions[] = {
+        {
+                .name   = "NOR.0",
+                .offset = 0,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct physmap_flash_data autcpu12_flash_pdata = {
+        .width          = 4,
+        .parts          = autcpu12_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(autcpu12_flash_partitions),
+};
+
+static struct resource autcpu12_flash_resources[] __initdata = {
+        DEFINE_RES_MEM(AUTCPU12_FLASH_BASE, SZ_8M),
+};
+
+static struct platform_device autcpu12_flash_pdev __initdata = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .resource       = autcpu12_flash_resources,
+        .num_resources  = ARRAY_SIZE(autcpu12_flash_resources),
+        .dev            = {
+                .platform_data  = &autcpu12_flash_pdata,
+        },
+};
+
+static struct resource autcpu12_nvram_resource[] __initdata = {
+        DEFINE_RES_MEM(AUTCPU12_NVRAM_BASE, 0),
+};
+
+static struct platdata_mtd_ram autcpu12_nvram_pdata = {
+        .bankwidth      = 4,
+};
+
+static struct platform_device autcpu12_nvram_pdev __initdata = {
+        .name           = "mtd-ram",
+        .id             = 0,
+        .resource       = autcpu12_nvram_resource,
+        .num_resources  = ARRAY_SIZE(autcpu12_nvram_resource),
+        .dev            = {
+                .platform_data  = &autcpu12_nvram_pdata,
+        },
+};
+
+static void __init autcpu12_nvram_init(void)
+{
+        void __iomem *nvram;
+        unsigned int save[2];
+        resource_size_t nvram_size = SZ_128K;
+
+        /*
+         * Check for 32K/128K
+         * Read ofs 0K
+         * Read ofs 64K
+         * Write complement to ofs 64K
+         * Read and check result on ofs 0K
+         * Restore contents
+         */
+        nvram = ioremap(autcpu12_nvram_resource[0].start, SZ_128K);
+        if (nvram) {
+                save[0] = readl(nvram + 0);
+                save[1] = readl(nvram + SZ_64K);
+                writel(~save[0], nvram + SZ_64K);
+                if (readl(nvram + 0) != save[0]) {
+                        writel(save[0], nvram + 0);
+                        nvram_size = SZ_32K;
+                } else
+                        writel(save[1], nvram + SZ_64K);
+                iounmap(nvram);
+
+                autcpu12_nvram_resource[0].end =
+                        autcpu12_nvram_resource[0].start + nvram_size - 1;
+                platform_device_register(&autcpu12_nvram_pdev);
+        } else
+                pr_err("Failed to remap NVRAM resource\n");
+}
+
 static void __init autcpu12_init(void)
 {
+        clps711x_devices_init();
+        platform_device_register(&autcpu12_flash_pdev);
         platform_device_register_simple("video-clps711x", 0, NULL, 0);
         platform_device_register_simple("cs89x0", 0, autcpu12_cs8900_resource,
                                         ARRAY_SIZE(autcpu12_cs8900_resource));
         platform_device_register(&autcpu12_mmgpio_pdev);
-        platform_device_register(&autcpu12_nvram_pdev);
+        autcpu12_nvram_init();
 }
 
 static void __init autcpu12_init_late(void)
 {
+        gpio_request_array(autcpu12_gpios, ARRAY_SIZE(autcpu12_gpios));
+
         if (IS_ENABLED(MTD_NAND_GPIO) && IS_ENABLED(GPIO_GENERIC_PLATFORM)) {
                 /* We are need both drivers to handle NAND */
                 platform_device_register(&autcpu12_nand_pdev);
@@ -169,6 +271,7 @@ MACHINE_START(AUTCPU12, "autronix autcpu12")
         .atag_offset    = 0x20000,
         .nr_irqs        = CLPS711X_NR_IRQS,
         .map_io         = clps711x_map_io,
+        .init_early     = clps711x_init_early,
         .init_irq       = clps711x_init_irq,
         .init_time      = clps711x_timer_init,
         .init_machine   = autcpu12_init,
diff --git a/arch/arm/mach-clps711x/board-cdb89712.c b/arch/arm/mach-clps711x/board-cdb89712.c
index baab7da33c9b..a9e38c6bcfb4 100644
--- a/arch/arm/mach-clps711x/board-cdb89712.c
+++ b/arch/arm/mach-clps711x/board-cdb89712.c
@@ -39,6 +39,7 @@
 #include <asm/mach/map.h>
 
 #include "common.h"
+#include "devices.h"
 
 #define CDB89712_CS8900_BASE    (CS2_PHYS_BASE + 0x300)
 #define CDB89712_CS8900_IRQ     (IRQ_EINT3)
@@ -127,6 +128,7 @@ static struct platform_device cdb89712_sram_pdev __initdata = {
 
 static void __init cdb89712_init(void)
 {
+        clps711x_devices_init();
         platform_device_register(&cdb89712_flash_pdev);
         platform_device_register(&cdb89712_bootrom_pdev);
         platform_device_register(&cdb89712_sram_pdev);
@@ -139,6 +141,7 @@ MACHINE_START(CDB89712, "Cirrus-CDB89712")
         .atag_offset    = 0x100,
         .nr_irqs        = CLPS711X_NR_IRQS,
         .map_io         = clps711x_map_io,
+        .init_early     = clps711x_init_early,
         .init_irq       = clps711x_init_irq,
         .init_time      = clps711x_timer_init,
         .init_machine   = cdb89712_init,
diff --git a/arch/arm/mach-clps711x/board-clep7312.c b/arch/arm/mach-clps711x/board-clep7312.c
index 014aa3c19a03..b4764246d0f8 100644
--- a/arch/arm/mach-clps711x/board-clep7312.c
+++ b/arch/arm/mach-clps711x/board-clep7312.c
@@ -39,6 +39,7 @@ MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
         .nr_irqs        = CLPS711X_NR_IRQS,
         .fixup          = fixup_clep7312,
         .map_io         = clps711x_map_io,
+        .init_early     = clps711x_init_early,
         .init_irq       = clps711x_init_irq,
         .init_time      = clps711x_timer_init,
         .handle_irq     = clps711x_handle_irq,
diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c
index 5f928e9ed2ef..9dfb990f0801 100644
--- a/arch/arm/mach-clps711x/board-edb7211.c
+++ b/arch/arm/mach-clps711x/board-edb7211.c
@@ -12,6 +12,7 @@
 #include <linux/delay.h>
 #include <linux/memblock.h>
 #include <linux/types.h>
+#include <linux/i2c-gpio.h>
 #include <linux/interrupt.h>
 #include <linux/backlight.h>
 #include <linux/platform_device.h>
@@ -29,6 +30,7 @@
 #include <mach/hardware.h>
 
 #include "common.h"
+#include "devices.h"
 
 #define VIDEORAM_SIZE           SZ_128K
 
@@ -36,11 +38,24 @@
 #define EDB7211_LCDEN           CLPS711X_GPIO(3, 2)
 #define EDB7211_LCDBL           CLPS711X_GPIO(3, 3)
 
+#define EDB7211_I2C_SDA         CLPS711X_GPIO(3, 4)
+#define EDB7211_I2C_SCL         CLPS711X_GPIO(3, 5)
+
 #define EDB7211_FLASH0_BASE     (CS0_PHYS_BASE)
 #define EDB7211_FLASH1_BASE     (CS1_PHYS_BASE)
+
 #define EDB7211_CS8900_BASE     (CS2_PHYS_BASE + 0x300)
 #define EDB7211_CS8900_IRQ      (IRQ_EINT3)
 
+/* The extra 8 lines of the keyboard matrix */
+#define EDB7211_EXTKBD_BASE     (CS3_PHYS_BASE)
+
+static struct i2c_gpio_platform_data edb7211_i2c_pdata __initdata = {
+        .sda_pin        = EDB7211_I2C_SDA,
+        .scl_pin        = EDB7211_I2C_SCL,
+        .scl_is_output_only = 1,
+};
+
 static struct resource edb7211_cs8900_resource[] __initdata = {
         DEFINE_RES_MEM(EDB7211_CS8900_BASE, SZ_1K),
         DEFINE_RES_IRQ(EDB7211_CS8900_IRQ),
@@ -94,13 +109,14 @@ static struct plat_lcd_data edb7211_lcd_power_pdata = {
 
 static void edb7211_lcd_backlight_set_intensity(int intensity)
 {
-        gpio_set_value(EDB7211_LCDBL, intensity);
+        gpio_set_value(EDB7211_LCDBL, !!intensity);
+        clps_writel((clps_readl(PMPCON) & 0xf0ff) | (intensity << 8), PMPCON);
 }
 
 static struct generic_bl_info edb7211_lcd_backlight_pdata = {
         .name                   = "lcd-backlight.0",
         .default_intensity      = 0x01,
-        .max_intensity          = 0x01,
+        .max_intensity          = 0x0f,
         .set_bl_intensity       = edb7211_lcd_backlight_set_intensity,
 };
 
@@ -112,8 +128,8 @@ static struct gpio edb7211_gpios[] __initconst = {
 
 static struct map_desc edb7211_io_desc[] __initdata = {
         {       /* Memory-mapped extra keyboard row */
-                .virtual        = IO_ADDRESS(EP7211_PHYS_EXTKBD),
-                .pfn            = __phys_to_pfn(EP7211_PHYS_EXTKBD),
+                .virtual        = IO_ADDRESS(EDB7211_EXTKBD_BASE),
+                .pfn            = __phys_to_pfn(EDB7211_EXTKBD_BASE),
                 .length         = SZ_1M,
                 .type           = MT_DEVICE,
         },
@@ -151,6 +167,11 @@ fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi)
 
 static void __init edb7211_init(void)
 {
+        clps711x_devices_init();
+}
+
+static void __init edb7211_init_late(void)
+{
         gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios));
 
         platform_device_register(&edb7211_flash_pdev);
@@ -163,6 +184,9 @@ static void __init edb7211_init(void)
         platform_device_register_simple("video-clps711x", 0, NULL, 0);
         platform_device_register_simple("cs89x0", 0, edb7211_cs8900_resource,
                                         ARRAY_SIZE(edb7211_cs8900_resource));
+        platform_device_register_data(&platform_bus, "i2c-gpio", 0,
+                                      &edb7211_i2c_pdata,
+                                      sizeof(edb7211_i2c_pdata));
 }
 
 MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
@@ -172,9 +196,11 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
         .fixup          = fixup_edb7211,
         .reserve        = edb7211_reserve,
         .map_io         = edb7211_map_io,
+        .init_early     = clps711x_init_early,
         .init_irq       = clps711x_init_irq,
         .init_time      = clps711x_timer_init,
         .init_machine   = edb7211_init,
+        .init_late      = edb7211_init_late,
         .handle_irq     = clps711x_handle_irq,
         .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-fortunet.c b/arch/arm/mach-clps711x/board-fortunet.c
index c5675efc8c6a..b1561e3d7c5c 100644
--- a/arch/arm/mach-clps711x/board-fortunet.c
+++ b/arch/arm/mach-clps711x/board-fortunet.c
@@ -77,6 +77,7 @@ MACHINE_START(FORTUNET, "ARM-FortuNet")
         .nr_irqs        = CLPS711X_NR_IRQS,
         .fixup          = fortunet_fixup,
         .map_io         = clps711x_map_io,
+        .init_early     = clps711x_init_early,
         .init_irq       = clps711x_init_irq,
         .init_time      = clps711x_timer_init,
         .handle_irq     = clps711x_handle_irq,
diff --git a/arch/arm/mach-clps711x/board-p720t.c b/arch/arm/mach-clps711x/board-p720t.c
index 8d3ee6771135..dd81b06f68fe 100644
--- a/arch/arm/mach-clps711x/board-p720t.c
+++ b/arch/arm/mach-clps711x/board-p720t.c
@@ -23,10 +23,12 @@
 #include <linux/string.h>
 #include <linux/mm.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
 #include <linux/slab.h>
 #include <linux/leds.h>
 #include <linux/sizes.h>
 #include <linux/backlight.h>
+#include <linux/basic_mmio_gpio.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand-gpio.h>
@@ -38,11 +40,11 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/syspld.h>
 
 #include <video/platform_lcd.h>
 
 #include "common.h"
+#include "devices.h"
 
 #define P720T_USERLED           CLPS711X_GPIO(3, 0)
 #define P720T_NAND_CLE          CLPS711X_GPIO(4, 0)
@@ -51,6 +53,178 @@
 
 #define P720T_NAND_BASE         (CLPS711X_SDRAM1_BASE)
 
+#define P720T_MMGPIO_BASE       (CLPS711X_NR_GPIO)
+
+#define SYSPLD_PHYS_BASE        IOMEM(CS1_PHYS_BASE)
+
+#define PLD_INT                 (SYSPLD_PHYS_BASE + 0x000000)
+#define PLD_INT_MMGPIO_BASE     (P720T_MMGPIO_BASE + 0)
+#define PLD_INT_PENIRQ          (PLD_INT_MMGPIO_BASE + 5)
+#define PLD_INT_UCB_IRQ         (PLD_INT_MMGPIO_BASE + 1)
+#define PLD_INT_KBD_ATN         (PLD_INT_MMGPIO_BASE + 0) /* EINT1 */
+
+#define PLD_PWR                 (SYSPLD_PHYS_BASE + 0x000004)
+#define PLD_PWR_MMGPIO_BASE     (P720T_MMGPIO_BASE + 8)
+#define PLD_PWR_EXT             (PLD_PWR_MMGPIO_BASE + 5)
+#define PLD_PWR_MODE            (PLD_PWR_MMGPIO_BASE + 4) /* 1 = PWM, 0 = PFM */
+#define PLD_S4_ON               (PLD_PWR_MMGPIO_BASE + 3) /* LCD bias voltage enable */
+#define PLD_S3_ON               (PLD_PWR_MMGPIO_BASE + 2) /* LCD backlight enable */
+#define PLD_S2_ON               (PLD_PWR_MMGPIO_BASE + 1) /* LCD 3V3 supply enable */
+#define PLD_S1_ON               (PLD_PWR_MMGPIO_BASE + 0) /* LCD 3V supply enable */
+
+#define PLD_KBD                 (SYSPLD_PHYS_BASE + 0x000008)
+#define PLD_KBD_MMGPIO_BASE     (P720T_MMGPIO_BASE + 16)
+#define PLD_KBD_WAKE            (PLD_KBD_MMGPIO_BASE + 1)
+#define PLD_KBD_EN              (PLD_KBD_MMGPIO_BASE + 0)
+
+#define PLD_SPI                 (SYSPLD_PHYS_BASE + 0x00000c)
+#define PLD_SPI_MMGPIO_BASE     (P720T_MMGPIO_BASE + 24)
+#define PLD_SPI_EN              (PLD_SPI_MMGPIO_BASE + 0)
+
+#define PLD_IO                  (SYSPLD_PHYS_BASE + 0x000010)
+#define PLD_IO_MMGPIO_BASE      (P720T_MMGPIO_BASE + 32)
+#define PLD_IO_BOOTSEL          (PLD_IO_MMGPIO_BASE + 6) /* Boot sel switch */
+#define PLD_IO_USER             (PLD_IO_MMGPIO_BASE + 5) /* User defined switch */
+#define PLD_IO_LED3             (PLD_IO_MMGPIO_BASE + 4)
+#define PLD_IO_LED2             (PLD_IO_MMGPIO_BASE + 3)
+#define PLD_IO_LED1             (PLD_IO_MMGPIO_BASE + 2)
+#define PLD_IO_LED0             (PLD_IO_MMGPIO_BASE + 1)
+#define PLD_IO_LEDEN            (PLD_IO_MMGPIO_BASE + 0)
+
+#define PLD_IRDA                (SYSPLD_PHYS_BASE + 0x000014)
+#define PLD_IRDA_MMGPIO_BASE    (P720T_MMGPIO_BASE + 40)
+#define PLD_IRDA_EN             (PLD_IRDA_MMGPIO_BASE + 0)
+
+#define PLD_COM2                (SYSPLD_PHYS_BASE + 0x000018)
+#define PLD_COM2_MMGPIO_BASE    (P720T_MMGPIO_BASE + 48)
+#define PLD_COM2_EN             (PLD_COM2_MMGPIO_BASE + 0)
+
+#define PLD_COM1                (SYSPLD_PHYS_BASE + 0x00001c)
+#define PLD_COM1_MMGPIO_BASE    (P720T_MMGPIO_BASE + 56)
+#define PLD_COM1_EN             (PLD_COM1_MMGPIO_BASE + 0)
+
+#define PLD_AUD                 (SYSPLD_PHYS_BASE + 0x000020)
+#define PLD_AUD_MMGPIO_BASE     (P720T_MMGPIO_BASE + 64)
+#define PLD_AUD_DIV1            (PLD_AUD_MMGPIO_BASE + 6)
+#define PLD_AUD_DIV0            (PLD_AUD_MMGPIO_BASE + 5)
+#define PLD_AUD_CLK_SEL1        (PLD_AUD_MMGPIO_BASE + 4)
+#define PLD_AUD_CLK_SEL0        (PLD_AUD_MMGPIO_BASE + 3)
+#define PLD_AUD_MIC_PWR         (PLD_AUD_MMGPIO_BASE + 2)
+#define PLD_AUD_MIC_GAIN        (PLD_AUD_MMGPIO_BASE + 1)
+#define PLD_AUD_CODEC_EN        (PLD_AUD_MMGPIO_BASE + 0)
+
+#define PLD_CF                  (SYSPLD_PHYS_BASE + 0x000024)
+#define PLD_CF_MMGPIO_BASE      (P720T_MMGPIO_BASE + 72)
+#define PLD_CF2_SLEEP           (PLD_CF_MMGPIO_BASE + 5)
+#define PLD_CF1_SLEEP           (PLD_CF_MMGPIO_BASE + 4)
+#define PLD_CF2_nPDREQ          (PLD_CF_MMGPIO_BASE + 3)
+#define PLD_CF1_nPDREQ          (PLD_CF_MMGPIO_BASE + 2)
+#define PLD_CF2_nIRQ            (PLD_CF_MMGPIO_BASE + 1)
+#define PLD_CF1_nIRQ            (PLD_CF_MMGPIO_BASE + 0)
+
+#define PLD_SDC                 (SYSPLD_PHYS_BASE + 0x000028)
+#define PLD_SDC_MMGPIO_BASE     (P720T_MMGPIO_BASE + 80)
+#define PLD_SDC_INT_EN          (PLD_SDC_MMGPIO_BASE + 2)
+#define PLD_SDC_WP              (PLD_SDC_MMGPIO_BASE + 1)
+#define PLD_SDC_CD              (PLD_SDC_MMGPIO_BASE + 0)
+
+#define PLD_CODEC               (SYSPLD_PHYS_BASE + 0x400000)
+#define PLD_CODEC_MMGPIO_BASE   (P720T_MMGPIO_BASE + 88)
+#define PLD_CODEC_IRQ3          (PLD_CODEC_MMGPIO_BASE + 4)
+#define PLD_CODEC_IRQ2          (PLD_CODEC_MMGPIO_BASE + 3)
+#define PLD_CODEC_IRQ1          (PLD_CODEC_MMGPIO_BASE + 2)
+#define PLD_CODEC_EN            (PLD_CODEC_MMGPIO_BASE + 0)
+
+#define PLD_BRITE               (SYSPLD_PHYS_BASE + 0x400004)
+#define PLD_BRITE_MMGPIO_BASE   (P720T_MMGPIO_BASE + 96)
+#define PLD_BRITE_UP            (PLD_BRITE_MMGPIO_BASE + 1)
+#define PLD_BRITE_DN            (PLD_BRITE_MMGPIO_BASE + 0)
+
+#define PLD_LCDEN               (SYSPLD_PHYS_BASE + 0x400008)
+#define PLD_LCDEN_MMGPIO_BASE   (P720T_MMGPIO_BASE + 104)
+#define PLD_LCDEN_EN            (PLD_LCDEN_MMGPIO_BASE + 0)
+
+#define PLD_TCH                 (SYSPLD_PHYS_BASE + 0x400010)
+#define PLD_TCH_MMGPIO_BASE     (P720T_MMGPIO_BASE + 112)
+#define PLD_TCH_PENIRQ          (PLD_TCH_MMGPIO_BASE + 1)
+#define PLD_TCH_EN              (PLD_TCH_MMGPIO_BASE + 0)
+
+#define PLD_GPIO                (SYSPLD_PHYS_BASE + 0x400014)
+#define PLD_GPIO_MMGPIO_BASE    (P720T_MMGPIO_BASE + 120)
+#define PLD_GPIO2               (PLD_GPIO_MMGPIO_BASE + 2)
+#define PLD_GPIO1               (PLD_GPIO_MMGPIO_BASE + 1)
+#define PLD_GPIO0               (PLD_GPIO_MMGPIO_BASE + 0)
+
+static struct gpio p720t_gpios[] __initconst = {
+        { PLD_S1_ON,    GPIOF_OUT_INIT_LOW,     "PLD_S1_ON" },
+        { PLD_S2_ON,    GPIOF_OUT_INIT_LOW,     "PLD_S2_ON" },
+        { PLD_S3_ON,    GPIOF_OUT_INIT_LOW,     "PLD_S3_ON" },
+        { PLD_S4_ON,    GPIOF_OUT_INIT_LOW,     "PLD_S4_ON" },
+        { PLD_KBD_EN,   GPIOF_OUT_INIT_LOW,     "PLD_KBD_EN" },
+        { PLD_SPI_EN,   GPIOF_OUT_INIT_LOW,     "PLD_SPI_EN" },
+        { PLD_IO_USER,  GPIOF_OUT_INIT_LOW,     "PLD_IO_USER" },
+        { PLD_IO_LED0,  GPIOF_OUT_INIT_LOW,     "PLD_IO_LED0" },
+        { PLD_IO_LED1,  GPIOF_OUT_INIT_LOW,     "PLD_IO_LED1" },
+        { PLD_IO_LED2,  GPIOF_OUT_INIT_LOW,     "PLD_IO_LED2" },
+        { PLD_IO_LED3,  GPIOF_OUT_INIT_LOW,     "PLD_IO_LED3" },
+        { PLD_IO_LEDEN, GPIOF_OUT_INIT_LOW,     "PLD_IO_LEDEN" },
+        { PLD_IRDA_EN,  GPIOF_OUT_INIT_LOW,     "PLD_IRDA_EN" },
+        { PLD_COM1_EN,  GPIOF_OUT_INIT_HIGH,    "PLD_COM1_EN" },
+        { PLD_COM2_EN,  GPIOF_OUT_INIT_HIGH,    "PLD_COM2_EN" },
+        { PLD_CODEC_EN, GPIOF_OUT_INIT_LOW,     "PLD_CODEC_EN" },
+        { PLD_LCDEN_EN, GPIOF_OUT_INIT_LOW,     "PLD_LCDEN_EN" },
+        { PLD_TCH_EN,   GPIOF_OUT_INIT_LOW,     "PLD_TCH_EN" },
+        { P720T_USERLED,GPIOF_OUT_INIT_LOW,     "USER_LED" },
+};
+
+static struct resource p720t_mmgpio_resource[] __initdata = {
+        DEFINE_RES_MEM_NAMED(0, 4, "dat"),
+};
+
+static struct bgpio_pdata p720t_mmgpio_pdata = {
+        .ngpio  = 8,
+};
+
+static struct platform_device p720t_mmgpio __initdata = {
+        .name           = "basic-mmio-gpio",
+        .id             = -1,
+        .resource       = p720t_mmgpio_resource,
+        .num_resources  = ARRAY_SIZE(p720t_mmgpio_resource),
+        .dev            = {
+                .platform_data  = &p720t_mmgpio_pdata,
+        },
+};
+
+static void __init p720t_mmgpio_init(void __iomem *addrbase, int gpiobase)
+{
+        p720t_mmgpio_resource[0].start = (unsigned long)addrbase;
+        p720t_mmgpio_pdata.base = gpiobase;
+
+        platform_device_register(&p720t_mmgpio);
+}
+
+static struct {
+        void __iomem    *addrbase;
+        int             gpiobase;
+} mmgpios[] __initconst = {
+        { PLD_INT,      PLD_INT_MMGPIO_BASE },
+        { PLD_PWR,      PLD_PWR_MMGPIO_BASE },
+        { PLD_KBD,      PLD_KBD_MMGPIO_BASE },
+        { PLD_SPI,      PLD_SPI_MMGPIO_BASE },
+        { PLD_IO,       PLD_IO_MMGPIO_BASE },
+        { PLD_IRDA,     PLD_IRDA_MMGPIO_BASE },
+        { PLD_COM2,     PLD_COM2_MMGPIO_BASE },
+        { PLD_COM1,     PLD_COM1_MMGPIO_BASE },
+        { PLD_AUD,      PLD_AUD_MMGPIO_BASE },
+        { PLD_CF,       PLD_CF_MMGPIO_BASE },
+        { PLD_SDC,      PLD_SDC_MMGPIO_BASE },
+        { PLD_CODEC,    PLD_CODEC_MMGPIO_BASE },
+        { PLD_BRITE,    PLD_BRITE_MMGPIO_BASE },
+        { PLD_LCDEN,    PLD_LCDEN_MMGPIO_BASE },
+        { PLD_TCH,      PLD_TCH_MMGPIO_BASE },
+        { PLD_GPIO,     PLD_GPIO_MMGPIO_BASE },
+};
+
 static struct resource p720t_nand_resource[] __initdata = {
         DEFINE_RES_MEM(P720T_NAND_BASE, SZ_4),
 };
@@ -92,11 +266,15 @@ static struct platform_device p720t_nand_pdev __initdata = {
 static void p720t_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
 {
         if (power) {
-                PLD_LCDEN = PLD_LCDEN_EN;
-                PLD_PWR |= PLD_S4_ON | PLD_S2_ON | PLD_S1_ON;
+                gpio_set_value(PLD_LCDEN_EN, 1);
+                gpio_set_value(PLD_S1_ON, 1);
+                gpio_set_value(PLD_S2_ON, 1);
+                gpio_set_value(PLD_S4_ON, 1);
         } else {
-                PLD_PWR &= ~(PLD_S4_ON | PLD_S2_ON | PLD_S1_ON);
-                PLD_LCDEN = 0;
+                gpio_set_value(PLD_S1_ON, 0);
+                gpio_set_value(PLD_S2_ON, 0);
+                gpio_set_value(PLD_S4_ON, 0);
+                gpio_set_value(PLD_LCDEN_EN, 0);
         }
 }
 
@@ -106,10 +284,7 @@ static struct plat_lcd_data p720t_lcd_power_pdata = {
 
 static void p720t_lcd_backlight_set_intensity(int intensity)
 {
-        if (intensity)
-                PLD_PWR |= PLD_S3_ON;
-        else
-                PLD_PWR = 0;
+        gpio_set_value(PLD_S3_ON, intensity);
 }
 
 static struct generic_bl_info p720t_lcd_backlight_pdata = {
@@ -119,19 +294,6 @@ static struct generic_bl_info p720t_lcd_backlight_pdata = {
         .set_bl_intensity       = p720t_lcd_backlight_set_intensity,
 };
 
-/*
- * Map the P720T system PLD. It occupies two address spaces:
- * 0x10000000 and 0x10400000. We map both regions as one.
- */
-static struct map_desc p720t_io_desc[] __initdata = {
-        {
-                .virtual        = SYSPLD_VIRT_BASE,
-                .pfn            = __phys_to_pfn(SYSPLD_PHYS_BASE),
-                .length         = SZ_8M,
-                .type           = MT_DEVICE,
-        },
-};
-
 static void __init
 fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi)
 {
@@ -157,33 +319,6 @@ fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi)
         }
 }
 
-static void __init p720t_map_io(void)
-{
-        clps711x_map_io();
-        iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc));
-}
-
-static void __init p720t_init_early(void)
-{
-        /*
-         * Power down as much as possible in case we don't
-         * have the drivers loaded.
-         */
-        PLD_LCDEN = 0;
-        PLD_PWR  &= ~(PLD_S4_ON|PLD_S3_ON|PLD_S2_ON|PLD_S1_ON);
-
-        PLD_KBD   = 0;
-        PLD_IO    = 0;
-        PLD_IRDA  = 0;
-        PLD_CODEC = 0;
-        PLD_TCH   = 0;
-        PLD_SPI   = 0;
-        if (!IS_ENABLED(CONFIG_DEBUG_LL)) {
-                PLD_COM2 = 0;
-                PLD_COM1 = 0;
-        }
-}
-
 static struct gpio_led p720t_gpio_leds[] = {
         {
                 .name                   = "User LED",
@@ -199,7 +334,20 @@ static struct gpio_led_platform_data p720t_gpio_led_pdata __initdata = {
 
 static void __init p720t_init(void)
 {
+        int i;
+
+        clps711x_devices_init();
+
+        for (i = 0; i < ARRAY_SIZE(mmgpios); i++)
+                p720t_mmgpio_init(mmgpios[i].addrbase, mmgpios[i].gpiobase);
+
         platform_device_register(&p720t_nand_pdev);
+}
+
+static void __init p720t_init_late(void)
+{
+        WARN_ON(gpio_request_array(p720t_gpios, ARRAY_SIZE(p720t_gpios)));
+
         platform_device_register_data(&platform_bus, "platform-lcd", 0,
                                       &p720t_lcd_power_pdata,
                                       sizeof(p720t_lcd_power_pdata));
@@ -207,10 +355,6 @@ static void __init p720t_init(void)
                                       &p720t_lcd_backlight_pdata,
                                       sizeof(p720t_lcd_backlight_pdata));
         platform_device_register_simple("video-clps711x", 0, NULL, 0);
-}
-
-static void __init p720t_init_late(void)
-{
         platform_device_register_data(&platform_bus, "leds-gpio", 0,
                                       &p720t_gpio_led_pdata,
                                       sizeof(p720t_gpio_led_pdata));
@@ -221,8 +365,8 @@ MACHINE_START(P720T, "ARM-Prospector720T")
         .atag_offset    = 0x100,
         .nr_irqs        = CLPS711X_NR_IRQS,
         .fixup          = fixup_p720t,
-        .map_io         = p720t_map_io,
-        .init_early     = p720t_init_early,
+        .map_io         = clps711x_map_io,
+        .init_early     = clps711x_init_early,
         .init_irq       = clps711x_init_irq,
         .init_time      = clps711x_timer_init,
         .init_machine   = p720t_init,
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 20ff50f3ccf0..f6d1746366d4 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -27,12 +27,14 @@
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/clockchips.h>
+#include <linux/clocksource.h>
 #include <linux/clk-provider.h>
 
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
+#include <asm/sched_clock.h>
 #include <asm/system_misc.h>
 
 #include <mach/hardware.h>
@@ -213,7 +215,7 @@ void __init clps711x_init_irq(void)
         }
 }
 
-inline u32 fls16(u32 x)
+static inline u32 fls16(u32 x)
 {
         u32 r = 15;
 
@@ -237,27 +239,52 @@ inline u32 fls16(u32 x)
 
 asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs)
 {
-        u32 irqstat;
-        void __iomem *base = CLPS711X_VIRT_BASE;
-
-        irqstat = readl_relaxed(base + INTSR1) & readl_relaxed(base + INTMR1);
-        if (irqstat) {
-                handle_IRQ(fls16(irqstat), regs);
-                return;
-        }
+        do {
+                u32 irqstat;
+                void __iomem *base = CLPS711X_VIRT_BASE;
+
+                irqstat = readw_relaxed(base + INTSR1) &
+                          readw_relaxed(base + INTMR1);
+                if (irqstat)
+                        handle_IRQ(fls16(irqstat), regs);
+
+                irqstat = readw_relaxed(base + INTSR2) &
+                          readw_relaxed(base + INTMR2);
+                if (irqstat) {
+                        handle_IRQ(fls16(irqstat) + 16, regs);
+                        continue;
+                }
+
+                break;
+        } while (1);
+}
 
-        irqstat = readl_relaxed(base + INTSR2) & readl_relaxed(base + INTMR2);
-        if (likely(irqstat))
-                handle_IRQ(fls16(irqstat) + 16, regs);
+static u32 notrace clps711x_sched_clock_read(void)
+{
+        return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D);
 }
 
 static void clps711x_clockevent_set_mode(enum clock_event_mode mode,
                                          struct clock_event_device *evt)
 {
+        disable_irq(IRQ_TC2OI);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                enable_irq(IRQ_TC2OI);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                /* Not supported */
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_RESUME:
+                /* Left event sources disabled, no more interrupts appear */
+                break;
+        }
 }
 
 static struct clock_event_device clockevent_clps711x = {
-        .name           = "CLPS711x Clockevents",
+        .name           = "clps711x-clockevent",
         .rating         = 300,
         .features       = CLOCK_EVT_FEAT_PERIODIC,
         .set_mode       = clps711x_clockevent_set_mode,
@@ -271,8 +298,8 @@ static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id)
 }
 
 static struct irqaction clps711x_timer_irq = {
-        .name           = "CLPS711x Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .name           = "clps711x-timer",
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
         .handler        = clps711x_timer_interrupt,
 };
 
@@ -301,6 +328,7 @@ void __init clps711x_timer_init(void)
                 cpu = ext;
                 bus = cpu;
                 spi = 135400;
+                pll = 0;
         } else {
                 cpu = pll;
                 if (cpu >= 36864000)
@@ -319,9 +347,9 @@ void __init clps711x_timer_init(void)
                 else
                         timh = 541440;
         } else
-                timh = cpu / 144;
+                timh = DIV_ROUND_CLOSEST(cpu, 144);
 
-        timl = timh / 256;
+        timl = DIV_ROUND_CLOSEST(timh, 256);
 
         /* All clocks are fixed */
         add_fixed_clk(clk_pll, "pll", pll);
@@ -334,13 +362,24 @@ void __init clps711x_timer_init(void)
 
         pr_info("CPU frequency set at %i Hz.\n", cpu);
 
+        /* Start Timer1 in free running mode (Low frequency) */
+        tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M);
+        clps_writel(tmp, SYSCON1);
+
+        setup_sched_clock(clps711x_sched_clock_read, 16, timl);
+
+        clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D,
+                              "clps711x_clocksource", timl, 300, 16,
+                              clocksource_mmio_readw_down);
+
+        /* Set Timer2 prescaler */
         clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D);
 
-        tmp = clps_readl(SYSCON1);
-        tmp |= SYSCON1_TC2S | SYSCON1_TC2M;
+        /* Start Timer2 in prescale mode (High frequency)*/
+        tmp = clps_readl(SYSCON1) | SYSCON1_TC2M | SYSCON1_TC2S;
         clps_writel(tmp, SYSCON1);
 
-        clockevents_config_and_register(&clockevent_clps711x, timh, 1, 0xffff);
+        clockevents_config_and_register(&clockevent_clps711x, timh, 0, 0);
 
         setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
 }
@@ -353,15 +392,11 @@ void clps711x_restart(char mode, const char *cmd)
 static void clps711x_idle(void)
 {
         clps_writel(1, HALT);
-        __asm__ __volatile__(
-        "mov    r0, r0\n\
-        mov     r0, r0");
+        asm("mov r0, r0");
+        asm("mov r0, r0");
 }
 
-static int __init clps711x_idle_init(void)
+void __init clps711x_init_early(void)
 {
         arm_pm_idle = clps711x_idle;
-        return 0;
 }
-
-arch_initcall(clps711x_idle_init);
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index f84a7292c70e..2a22f4c6cc75 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -13,3 +13,4 @@ extern void clps711x_init_irq(void);
 extern void clps711x_timer_init(void);
 extern void clps711x_handle_irq(struct pt_regs *regs);
 extern void clps711x_restart(char mode, const char *cmd);
+extern void clps711x_init_early(void);
diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c
new file mode 100644
index 000000000000..856b81cf2f8a
--- /dev/null
+++ b/arch/arm/mach-clps711x/devices.c
@@ -0,0 +1,68 @@
+/*
+ *  CLPS711X common devices definitions
+ *
+ *  Author: Alexander Shiyan <shc_work@mail.ru>, 2013
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/sizes.h>
+
+#include <mach/hardware.h>
+
+static const phys_addr_t clps711x_gpios[][2] __initconst = {
+        { PADR, PADDR },
+        { PBDR, PBDDR },
+        { PCDR, PCDDR },
+        { PDDR, PDDDR },
+        { PEDR, PEDDR },
+};
+
+static void __init clps711x_add_gpio(void)
+{
+        unsigned i;
+        struct resource gpio_res[2];
+
+        memset(gpio_res, 0, sizeof(gpio_res));
+
+        gpio_res[0].flags = IORESOURCE_MEM;
+        gpio_res[1].flags = IORESOURCE_MEM;
+
+        for (i = 0; i < ARRAY_SIZE(clps711x_gpios); i++) {
+                gpio_res[0].start = CLPS711X_PHYS_BASE + clps711x_gpios[i][0];
+                gpio_res[0].end = gpio_res[0].start;
+                gpio_res[1].start = CLPS711X_PHYS_BASE + clps711x_gpios[i][1];
+                gpio_res[1].end = gpio_res[1].start;
+
+                platform_device_register_simple("clps711x-gpio", i,
+                                                gpio_res, ARRAY_SIZE(gpio_res));
+        }
+}
+
+const struct resource clps711x_syscon_res[] __initconst = {
+        /* SYSCON1, SYSFLG1 */
+        DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON1, SZ_128),
+        /* SYSCON2, SYSFLG2 */
+        DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON2, SZ_128),
+        /* SYSCON3 */
+        DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON3, SZ_64),
+};
+
+static void __init clps711x_add_syscon(void)
+{
+        unsigned i;
+
+        for (i = 0; i < ARRAY_SIZE(clps711x_syscon_res); i++)
+                platform_device_register_simple("clps711x-syscon", i + 1,
+                                                &clps711x_syscon_res[i], 1);
+}
+
+void __init clps711x_devices_init(void)
+{
+        clps711x_add_gpio();
+        clps711x_add_syscon();
+}
diff --git a/arch/arm/mach-clps711x/devices.h b/arch/arm/mach-clps711x/devices.h
new file mode 100644
index 000000000000..a5efc1744b84
--- /dev/null
+++ b/arch/arm/mach-clps711x/devices.h
@@ -0,0 +1,12 @@
+/*
+ *  CLPS711X common devices definitions
+ *
+ *  Copyright (C) 2013 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+void clps711x_devices_init(void);
diff --git a/arch/arm/mach-clps711x/include/mach/autcpu12.h b/arch/arm/mach-clps711x/include/mach/autcpu12.h
deleted file mode 100644
index 0452f5f3f034..000000000000
--- a/arch/arm/mach-clps711x/include/mach/autcpu12.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * AUTCPU12 specific defines
- *
- * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_AUTCPU12_H
-#define __ASM_ARCH_AUTCPU12_H
-
-/*
- * The flash bank is wired to chip select 0
- */
-#define AUTCPU12_PHYS_FLASH             CS0_PHYS_BASE           /* physical */
-
-/* offset for device specific information structure */
-#define AUTCPU12_LCDINFO_OFFS           (0x00010000)    
-
-/* Videomemory in the internal SRAM (CS 6) */
-#define AUTCPU12_PHYS_VIDEO             CS6_PHYS_BASE
-
-/*
-* All special IO's are tied to CS1
-*/
-#define AUTCPU12_PHYS_CHAR_LCD          CS1_PHYS_BASE +0x00000000  /* physical */
-
-#define AUTCPU12_PHYS_NVRAM             CS1_PHYS_BASE +0x02000000  /* physical */
-
-#define AUTCPU12_PHYS_CSAUX1            CS1_PHYS_BASE +0x04000000  /* physical */
-
-#define AUTCPU12_PHYS_CAN               CS1_PHYS_BASE +0x08000000  /* physical */
-
-#define AUTCPU12_PHYS_TOUCH             CS1_PHYS_BASE +0x0A000000  /* physical */
-
-#define AUTCPU12_PHYS_IO                CS1_PHYS_BASE +0x0C000000  /* physical */
-
-#define AUTCPU12_PHYS_LPT               CS1_PHYS_BASE +0x0E000000  /* physical */
-
-/*
-* defines for lcd contrast 
-*/
-#define AUTCPU12_DPOT_PORT_OFFSET       PEDR
-#define AUTCPU12_DPOT_CS                (1<<0)
-#define AUTCPU12_DPOT_CLK               (1<<1)
-#define AUTCPU12_DPOT_UD                (1<<2)
-
-#endif
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
index 01d1b9559710..0286f4bf9945 100644
--- a/arch/arm/mach-clps711x/include/mach/clps711x.h
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -21,6 +21,8 @@
 #ifndef __MACH_CLPS711X_H
 #define __MACH_CLPS711X_H
 
+#include <linux/mfd/syscon/clps711x.h>
+
 #define CLPS711X_PHYS_BASE      (0x80000000)
 
 #define PADR            (0x0000)
@@ -96,83 +98,9 @@
 #define RANDID2         (0x2708)
 #define RANDID3         (0x270c)
 
-/* common bits: SYSCON1 / SYSCON2 */
-#define SYSCON_UARTEN           (1 << 8)
-
-#define SYSCON1_KBDSCAN(x)      ((x) & 15)
-#define SYSCON1_KBDSCANMASK     (15)
-#define SYSCON1_TC1M            (1 << 4)
-#define SYSCON1_TC1S            (1 << 5)
-#define SYSCON1_TC2M            (1 << 6)
-#define SYSCON1_TC2S            (1 << 7)
-#define SYSCON1_UART1EN         SYSCON_UARTEN
-#define SYSCON1_BZTOG           (1 << 9)
-#define SYSCON1_BZMOD           (1 << 10)
-#define SYSCON1_DBGEN           (1 << 11)
-#define SYSCON1_LCDEN           (1 << 12)
-#define SYSCON1_CDENTX          (1 << 13)
-#define SYSCON1_CDENRX          (1 << 14)
-#define SYSCON1_SIREN           (1 << 15)
-#define SYSCON1_ADCKSEL(x)      (((x) & 3) << 16)
-#define SYSCON1_ADCKSEL_MASK    (3 << 16)
-#define SYSCON1_EXCKEN          (1 << 18)
-#define SYSCON1_WAKEDIS         (1 << 19)
-#define SYSCON1_IRTXM           (1 << 20)
-
-/* common bits: SYSFLG1 / SYSFLG2 */
-#define SYSFLG_UBUSY            (1 << 11)
-#define SYSFLG_URXFE            (1 << 22)
-#define SYSFLG_UTXFF            (1 << 23)
-
-#define SYSFLG1_MCDR            (1 << 0)
-#define SYSFLG1_DCDET           (1 << 1)
-#define SYSFLG1_WUDR            (1 << 2)
-#define SYSFLG1_WUON            (1 << 3)
-#define SYSFLG1_CTS             (1 << 8)
-#define SYSFLG1_DSR             (1 << 9)
-#define SYSFLG1_DCD             (1 << 10)
-#define SYSFLG1_UBUSY           SYSFLG_UBUSY
-#define SYSFLG1_NBFLG           (1 << 12)
-#define SYSFLG1_RSTFLG          (1 << 13)
-#define SYSFLG1_PFFLG           (1 << 14)
-#define SYSFLG1_CLDFLG          (1 << 15)
-#define SYSFLG1_URXFE           SYSFLG_URXFE
-#define SYSFLG1_UTXFF           SYSFLG_UTXFF
-#define SYSFLG1_CRXFE           (1 << 24)
-#define SYSFLG1_CTXFF           (1 << 25)
-#define SYSFLG1_SSIBUSY         (1 << 26)
-#define SYSFLG1_ID              (1 << 29)
-#define SYSFLG1_VERID(x)        (((x) >> 30) & 3)
-#define SYSFLG1_VERID_MASK      (3 << 30)
-
-#define SYSFLG2_SSRXOF          (1 << 0)
-#define SYSFLG2_RESVAL          (1 << 1)
-#define SYSFLG2_RESFRM          (1 << 2)
-#define SYSFLG2_SS2RXFE         (1 << 3)
-#define SYSFLG2_SS2TXFF         (1 << 4)
-#define SYSFLG2_SS2TXUF         (1 << 5)
-#define SYSFLG2_CKMODE          (1 << 6)
-#define SYSFLG2_UBUSY           SYSFLG_UBUSY
-#define SYSFLG2_URXFE           SYSFLG_URXFE
-#define SYSFLG2_UTXFF           SYSFLG_UTXFF
-
 #define LCDCON_GSEN             (1 << 30)
 #define LCDCON_GSMD             (1 << 31)
 
-#define SYSCON2_SERSEL          (1 << 0)
-#define SYSCON2_KBD6            (1 << 1)
-#define SYSCON2_DRAMZ           (1 << 2)
-#define SYSCON2_KBWEN           (1 << 3)
-#define SYSCON2_SS2TXEN         (1 << 4)
-#define SYSCON2_PCCARD1         (1 << 5)
-#define SYSCON2_PCCARD2         (1 << 6)
-#define SYSCON2_SS2RXEN         (1 << 7)
-#define SYSCON2_UART2EN         SYSCON_UARTEN
-#define SYSCON2_SS2MAEN         (1 << 9)
-#define SYSCON2_OSTB            (1 << 12)
-#define SYSCON2_CLKENSL         (1 << 13)
-#define SYSCON2_BUZFREQ         (1 << 14)
-
 /* common bits: UARTDR1 / UARTDR2 */
 #define UARTDR_FRMERR           (1 << 8)
 #define UARTDR_PARERR           (1 << 9)
@@ -228,18 +156,6 @@
 #define DAI64FS_MCLK256EN       (1 << 3)
 #define DAI64FS_LOOPBACK        (1 << 5)
 
-#define SYSCON3_ADCCON          (1 << 0)
-#define SYSCON3_CLKCTL0         (1 << 1)
-#define SYSCON3_CLKCTL1         (1 << 2)
-#define SYSCON3_DAISEL          (1 << 3)
-#define SYSCON3_ADCCKNSEN       (1 << 4)
-#define SYSCON3_VERSN(x)        (((x) >> 5) & 7)
-#define SYSCON3_VERSN_MASK      (7 << 5)
-#define SYSCON3_FASTWAKE        (1 << 8)
-#define SYSCON3_DAIEN           (1 << 9)
-#define SYSCON3_128FS           SYSCON3_DAIEN
-#define SYSCON3_ENPD67          (1 << 10)
-
 #define SDCONF_ACTIVE           (1 << 10)
 #define SDCONF_CLKCTL           (1 << 9)
 #define SDCONF_WIDTH_4          (0 << 7)
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
index 2f23dd5d73e4..c5a8ea6839ef 100644
--- a/arch/arm/mach-clps711x/include/mach/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -70,11 +70,4 @@
 #define CLPS711X_SDRAM0_BASE    (0xc0000000)
 #define CLPS711X_SDRAM1_BASE    (0xd0000000)
 
-#if defined (CONFIG_ARCH_EDB7211)
-
-/* The extra 8 lines of the keyboard matrix are wired to chip select 3 */
-#define EP7211_PHYS_EXTKBD      CS3_PHYS_BASE
-
-#endif /* CONFIG_ARCH_EDB7211 */
-
 #endif
diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h
deleted file mode 100644
index fc0e028d9405..000000000000
--- a/arch/arm/mach-clps711x/include/mach/memory.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- *  arch/arm/mach-clps711x/include/mach/memory.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Physical DRAM offset.
- */
-#define PLAT_PHYS_OFFSET        UL(0xc0000000)
-
-/*
- * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
- * uses only one of the two banks (bank #1).  However, even within
- * bank #1, memory is discontiguous.
- *
- * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
- * them, so we use 24 for the node max shift to get 16MB node sizes.
- */
-
-#define SECTION_SIZE_BITS       24
-#define MAX_PHYSMEM_BITS        32
-
-#endif
-
diff --git a/arch/arm/mach-clps711x/include/mach/syspld.h b/arch/arm/mach-clps711x/include/mach/syspld.h
deleted file mode 100644
index 9a433155bf58..000000000000
--- a/arch/arm/mach-clps711x/include/mach/syspld.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- *  arch/arm/mach-clps711x/include/mach/syspld.h
- *
- *  System Control PLD register definitions.
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSPLD_H
-#define __ASM_ARCH_SYSPLD_H
-
-#define SYSPLD_PHYS_BASE        (0x10000000)
-#define SYSPLD_VIRT_BASE        IO_ADDRESS(SYSPLD_PHYS_BASE)
-
-#define SYSPLD_REG(type, off)   (*(volatile type *)(SYSPLD_VIRT_BASE + (off)))
-
-#define PLD_INT         SYSPLD_REG(u32, 0x000000)
-#define PLD_INT_PENIRQ          (1 << 5)
-#define PLD_INT_UCB_IRQ         (1 << 1)
-#define PLD_INT_KBD_ATN         (1 << 0)        /* EINT1 */
-
-#define PLD_PWR         SYSPLD_REG(u32, 0x000004)
-#define PLD_PWR_EXT             (1 << 5)
-#define PLD_PWR_MODE            (1 << 4)        /* 1 = PWM, 0 = PFM */
-#define PLD_S4_ON               (1 << 3)        /* LCD bias voltage enable */
-#define PLD_S3_ON               (1 << 2)        /* LCD backlight enable */
-#define PLD_S2_ON               (1 << 1)        /* LCD 3V3 supply enable */
-#define PLD_S1_ON               (1 << 0)        /* LCD 3V supply enable */
-
-#define PLD_KBD         SYSPLD_REG(u32, 0x000008)
-#define PLD_KBD_WAKE            (1 << 1)
-#define PLD_KBD_EN              (1 << 0)
-
-#define PLD_SPI         SYSPLD_REG(u32, 0x00000c)
-#define PLD_SPI_EN              (1 << 0)
-
-#define PLD_IO          SYSPLD_REG(u32, 0x000010)
-#define PLD_IO_BOOTSEL          (1 << 6)        /* boot sel switch */
-#define PLD_IO_USER             (1 << 5)        /* user defined switch */
-#define PLD_IO_LED3             (1 << 4)
-#define PLD_IO_LED2             (1 << 3)
-#define PLD_IO_LED1             (1 << 2)
-#define PLD_IO_LED0             (1 << 1)
-#define PLD_IO_LEDEN            (1 << 0)
-
-#define PLD_IRDA        SYSPLD_REG(u32, 0x000014)
-#define PLD_IRDA_EN             (1 << 0)
-
-#define PLD_COM2        SYSPLD_REG(u32, 0x000018)
-#define PLD_COM2_EN             (1 << 0)
-
-#define PLD_COM1        SYSPLD_REG(u32, 0x00001c)
-#define PLD_COM1_EN             (1 << 0)
-
-#define PLD_AUD         SYSPLD_REG(u32, 0x000020)
-#define PLD_AUD_DIV1            (1 << 6)
-#define PLD_AUD_DIV0            (1 << 5)
-#define PLD_AUD_CLK_SEL1        (1 << 4)
-#define PLD_AUD_CLK_SEL0        (1 << 3)
-#define PLD_AUD_MIC_PWR         (1 << 2)
-#define PLD_AUD_MIC_GAIN        (1 << 1)
-#define PLD_AUD_CODEC_EN        (1 << 0)
-
-#define PLD_CF          SYSPLD_REG(u32, 0x000024)
-#define PLD_CF2_SLEEP           (1 << 5)
-#define PLD_CF1_SLEEP           (1 << 4)
-#define PLD_CF2_nPDREQ          (1 << 3)
-#define PLD_CF1_nPDREQ          (1 << 2)
-#define PLD_CF2_nIRQ            (1 << 1)
-#define PLD_CF1_nIRQ            (1 << 0)
-
-#define PLD_SDC         SYSPLD_REG(u32, 0x000028)
-#define PLD_SDC_INT_EN          (1 << 2)
-#define PLD_SDC_WP              (1 << 1)
-#define PLD_SDC_CD              (1 << 0)
-
-#define PLD_FPGA        SYSPLD_REG(u32, 0x00002c)
-
-#define PLD_CODEC       SYSPLD_REG(u32, 0x400000)
-#define PLD_CODEC_IRQ3          (1 << 4)
-#define PLD_CODEC_IRQ2          (1 << 3)
-#define PLD_CODEC_IRQ1          (1 << 2)
-#define PLD_CODEC_EN            (1 << 0)
-
-#define PLD_BRITE       SYSPLD_REG(u32, 0x400004)
-#define PLD_BRITE_UP            (1 << 1)
-#define PLD_BRITE_DN            (1 << 0)
-
-#define PLD_LCDEN       SYSPLD_REG(u32, 0x400008)
-#define PLD_LCDEN_EN            (1 << 0)
-
-#define PLD_ID          SYSPLD_REG(u32, 0x40000c)
-
-#define PLD_TCH         SYSPLD_REG(u32, 0x400010)
-#define PLD_TCH_PENIRQ          (1 << 1)
-#define PLD_TCH_EN              (1 << 0)
-
-#define PLD_GPIO        SYSPLD_REG(u32, 0x400014)
-#define PLD_GPIO2               (1 << 2)
-#define PLD_GPIO1               (1 << 1)
-#define PLD_GPIO0               (1 << 0)
-
-#endif
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index dd1ffccc75e9..63997a1128e6 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -5,7 +5,7 @@
 
 # Common objects
 obj-y                   := time.o clock.o serial.o psc.o \
-                           dma.o usb.o common.o sram.o aemif.o
+                           usb.o common.o sram.o aemif.o
 
 obj-$(CONFIG_DAVINCI_MUX)               += mux.o
 
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index ba798370fc96..78ea395d2aca 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -26,12 +26,12 @@
 #include <linux/input.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
+#include <linux/platform_data/edma.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
 #include <mach/irqs.h>
-#include <mach/edma.h>
 #include <mach/mux.h>
 #include <mach/cp_intc.h>
 #include <mach/tnetv107x.h>
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index 1ab3df423dac..a883043d0820 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -23,9 +23,9 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/platform_data/davinci_asp.h>
+#include <linux/platform_data/edma.h>
 #include <linux/platform_data/keyscan-davinci.h>
 #include <mach/hardware.h>
-#include <mach/edma.h>
 
 #include <media/davinci/vpfe_capture.h>
 #include <media/davinci/vpif_types.h>
@@ -77,32 +77,32 @@ void davinci_map_sysmod(void);
 #define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
 
 /* DM355 function declarations */
-void __init dm355_init(void);
+void dm355_init(void);
 void dm355_init_spi0(unsigned chipselect_mask,
                 const struct spi_board_info *info, unsigned len);
-void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata);
+void dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata);
 int dm355_init_video(struct vpfe_config *, struct vpbe_config *);
 
 /* DM365 function declarations */
-void __init dm365_init(void);
-void __init dm365_init_asp(struct snd_platform_data *pdata);
-void __init dm365_init_vc(struct snd_platform_data *pdata);
-void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
-void __init dm365_init_rtc(void);
+void dm365_init(void);
+void dm365_init_asp(struct snd_platform_data *pdata);
+void dm365_init_vc(struct snd_platform_data *pdata);
+void dm365_init_ks(struct davinci_ks_platform_data *pdata);
+void dm365_init_rtc(void);
 void dm365_init_spi0(unsigned chipselect_mask,
                         const struct spi_board_info *info, unsigned len);
 int dm365_init_video(struct vpfe_config *, struct vpbe_config *);
 
 /* DM644x function declarations */
-void __init dm644x_init(void);
-void __init dm644x_init_asp(struct snd_platform_data *pdata);
-int __init dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
+void dm644x_init(void);
+void dm644x_init_asp(struct snd_platform_data *pdata);
+int dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
 
 /* DM646x function declarations */
-void __init dm646x_init(void);
-void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
-void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
-int __init dm646x_init_edma(struct edma_rsv_info *rsv);
+void dm646x_init(void);
+void dm646x_init_mcasp0(struct snd_platform_data *pdata);
+void dm646x_init_mcasp1(struct snd_platform_data *pdata);
+int dm646x_init_edma(struct edma_rsv_info *rsv);
 void dm646x_video_init(void);
 void dm646x_setup_vpif(struct vpif_display_config *,
                        struct vpif_capture_config *);
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index cfb194df18ed..612a0856e9c5 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -18,10 +18,10 @@
 #include <linux/dma-mapping.h>
 #include <linux/clk.h>
 #include <linux/slab.h>
+#include <linux/platform_data/edma.h>
 
 #include <mach/common.h>
 #include <mach/irqs.h>
-#include <mach/edma.h>
 #include <mach/tnetv107x.h>
 
 #include "clock.h"
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index a7068a3aa9d3..90b83d00fe2b 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -19,9 +19,10 @@
 #include <mach/irqs.h>
 #include <mach/cputype.h>
 #include <mach/mux.h>
-#include <mach/edma.h>
 #include <linux/platform_data/mmc-davinci.h>
 #include <mach/time.h>
+#include <linux/platform_data/edma.h>
+
 
 #include "davinci.h"
 #include "clock.h"
@@ -34,6 +35,9 @@
 #define DM365_MMCSD0_BASE            0x01D11000
 #define DM365_MMCSD1_BASE            0x01D00000
 
+#define DAVINCI_DMA_MMCRXEVT    26
+#define DAVINCI_DMA_MMCTXEVT    27
+
 void __iomem  *davinci_sysmod_base;
 
 void davinci_map_sysmod(void)
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index a11034a358f1..526cf7d06d0e 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -19,7 +19,6 @@
 #include <asm/mach/map.h>
 
 #include <mach/cputype.h>
-#include <mach/edma.h>
 #include <mach/psc.h>
 #include <mach/mux.h>
 #include <mach/irqs.h>
@@ -28,6 +27,7 @@
 #include <mach/common.h>
 #include <linux/platform_data/spi-davinci.h>
 #include <mach/gpio-davinci.h>
+#include <linux/platform_data/edma.h>
 
 #include "davinci.h"
 #include "clock.h"
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 40fa4fee9331..c4b741173c06 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -18,11 +18,11 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/spi/spi.h>
+#include <linux/platform_data/edma.h>
 
 #include <asm/mach/map.h>
 
 #include <mach/cputype.h>
-#include <mach/edma.h>
 #include <mach/psc.h>
 #include <mach/mux.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 4d37d3e2a193..dd156d58fe64 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -12,11 +12,11 @@
 #include <linux/clk.h>
 #include <linux/serial_8250.h>
 #include <linux/platform_device.h>
+#include <linux/platform_data/edma.h>
 
 #include <asm/mach/map.h>
 
 #include <mach/cputype.h>
-#include <mach/edma.h>
 #include <mach/irqs.h>
 #include <mach/psc.h>
 #include <mach/mux.h>
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index ac7b431c4c8e..6d52a321a8cf 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -13,11 +13,11 @@
 #include <linux/clk.h>
 #include <linux/serial_8250.h>
 #include <linux/platform_device.h>
+#include <linux/platform_data/edma.h>
 
 #include <asm/mach/map.h>
 
 #include <mach/cputype.h>
-#include <mach/edma.h>
 #include <mach/irqs.h>
 #include <mach/psc.h>
 #include <mach/mux.h>
diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h
index d13d8dfa2b0d..827bbe9baed4 100644
--- a/arch/arm/mach-davinci/include/mach/cp_intc.h
+++ b/arch/arm/mach-davinci/include/mach/cp_intc.h
@@ -51,7 +51,7 @@
 #define CP_INTC_HOST_PRIO_VECTOR(n)     (0x1600 + (n << 2))
 #define CP_INTC_VECTOR_ADDR(n)          (0x2000 + (n << 2))
 
-void __init cp_intc_init(void);
-int __init cp_intc_of_init(struct device_node *, struct device_node *);
+void cp_intc_init(void);
+int cp_intc_of_init(struct device_node *, struct device_node *);
 
 #endif  /* __ASM_HARDWARE_CP_INTC_H */
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 2e1c9eae0a58..3c797e2272f8 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -20,8 +20,8 @@
 #include <linux/videodev2.h>
 
 #include <mach/serial.h>
-#include <mach/edma.h>
 #include <mach/pm.h>
+#include <linux/platform_data/edma.h>
 #include <linux/platform_data/i2c-davinci.h>
 #include <linux/platform_data/mmc-davinci.h>
 #include <linux/platform_data/usb-davinci.h>
@@ -79,8 +79,8 @@ extern unsigned int da850_max_speed;
 #define DA8XX_SHARED_RAM_BASE   0x80000000
 #define DA8XX_ARM_RAM_BASE      0xffff0000
 
-void __init da830_init(void);
-void __init da850_init(void);
+void da830_init(void);
+void da850_init(void);
 
 int da830_register_edma(struct edma_rsv_info *rsv);
 int da850_register_edma(struct edma_rsv_info *rsv[2]);
@@ -94,17 +94,17 @@ int da8xx_register_uio_pruss(void);
 int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
 int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
 int da850_register_mmcsd1(struct davinci_mmc_config *config);
-void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
+void da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
 int da8xx_register_rtc(void);
 int da850_register_cpufreq(char *async_clk);
 int da8xx_register_cpuidle(void);
-void __iomem * __init da8xx_get_mem_ctlr(void);
+void __iomem *da8xx_get_mem_ctlr(void);
 int da850_register_pm(struct platform_device *pdev);
-int __init da850_register_sata(unsigned long refclkpn);
-int __init da850_register_vpif(void);
-int __init da850_register_vpif_display
+int da850_register_sata(unsigned long refclkpn);
+int da850_register_vpif(void);
+int da850_register_vpif_display
                         (struct vpif_display_config *display_config);
-int __init da850_register_vpif_capture
+int da850_register_vpif_capture
                         (struct vpif_capture_config *capture_config);
 void da8xx_restart(char mode, const char *cmd);
 void da8xx_rproc_reserve_cma(void);
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index 1656a02e3eda..366e975effa8 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -51,9 +51,9 @@ struct tnetv107x_device_info {
 extern struct platform_device tnetv107x_wdt_device;
 extern struct platform_device tnetv107x_serial_device;
 
-extern void __init tnetv107x_init(void);
-extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *);
-extern void __init tnetv107x_irq_init(void);
+extern void tnetv107x_init(void);
+extern void tnetv107x_devices_init(struct tnetv107x_device_info *);
+extern void tnetv107x_irq_init(void);
 void tnetv107x_restart(char mode, const char *cmd);
 
 #endif
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index 36469d813951..dff7b2fd4e20 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -22,8 +22,7 @@ config MACH_CM_A510
 
 config MACH_DOVE_DT
         bool "Marvell Dove Flattened Device Tree"
-        select MVEBU_CLK_CORE
-        select MVEBU_CLK_GATING
+        select DOVE_CLK
         select REGULATOR
         select REGULATOR_FIXED_VOLTAGE
         select USE_OF
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index 0b142803b2e1..f3755ac81148 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -10,7 +10,6 @@
 
 #include <linux/init.h>
 #include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/platform_data/usb-ehci-orion.h>
@@ -49,7 +48,7 @@ static void __init dove_legacy_clk_init(void)
 
 static void __init dove_of_clk_init(void)
 {
-        mvebu_clocks_init();
+        of_clk_init(NULL);
         dove_legacy_clk_init();
 }
 
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index e2b5da031f96..2a9443d04d92 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -9,7 +9,6 @@
  */
 
 #include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
 #include <linux/dma-mapping.h>
 #include <linux/init.h>
 #include <linux/of.h>
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index d19edff0ea6e..1e0e3999c17a 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -14,9 +14,11 @@ menu "SAMSUNG EXYNOS SoCs Support"
 config ARCH_EXYNOS4
         bool "SAMSUNG EXYNOS4"
         default y
+        select GIC_NON_BANKED
         select HAVE_ARM_SCU if SMP
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
+        select PINCTRL
         help
           Samsung EXYNOS4 SoCs based systems
 
@@ -24,6 +26,7 @@ config ARCH_EXYNOS5
         bool "SAMSUNG EXYNOS5"
         select HAVE_ARM_SCU if SMP
         select HAVE_SMP
+        select PINCTRL
         help
           Samsung EXYNOS5 (Cortex-A15) SoC based systems
 
@@ -34,6 +37,7 @@ config CPU_EXYNOS4210
         default y
         depends on ARCH_EXYNOS4
         select ARM_CPU_SUSPEND if PM
+        select PINCTRL_EXYNOS
         select PM_GENERIC_DOMAINS
         select S5P_PM if PM
         select S5P_SLEEP if PM
@@ -45,6 +49,7 @@ config SOC_EXYNOS4212
         bool "SAMSUNG EXYNOS4212"
         default y
         depends on ARCH_EXYNOS4
+        select PINCTRL_EXYNOS
         select S5P_PM if PM
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
@@ -55,6 +60,7 @@ config SOC_EXYNOS4412
         bool "SAMSUNG EXYNOS4412"
         default y
         depends on ARCH_EXYNOS4
+        select PINCTRL_EXYNOS
         select SAMSUNG_DMADEV
         help
           Enable EXYNOS4412 SoC support
@@ -63,6 +69,7 @@ config SOC_EXYNOS5250
         bool "SAMSUNG EXYNOS5250"
         default y
         depends on ARCH_EXYNOS5
+        select PINCTRL_EXYNOS
         select PM_GENERIC_DOMAINS if PM
         select S5P_PM if PM
         select S5P_SLEEP if PM
@@ -78,344 +85,23 @@ config SOC_EXYNOS5440
         select ARCH_HAS_OPP
         select ARM_ARCH_TIMER
         select AUTO_ZRELADDR
-        select PINCTRL
         select PINCTRL_EXYNOS5440
         select PM_OPP
         help
           Enable EXYNOS5440 SoC support
 
-config EXYNOS_ATAGS
-        bool "ATAGS based boot for EXYNOS (deprecated)"
-        depends on !ARCH_MULTIPLATFORM
-        depends on ATAGS
-        default y
-        help
-          The EXYNOS platform is moving towards being completely probed
-          through device tree. This enables support for board files using
-          the traditional ATAGS boot format.
-          Note that this option is not available for multiplatform builds.
-
-if EXYNOS_ATAGS
-
-config EXYNOS_DEV_DMA
-        bool
-        help
-          Compile in amba device definitions for DMA controller
-
-config EXYNOS4_DEV_AHCI
-        bool
-        help
-          Compile in platform device definitions for AHCI
-
-config EXYNOS4_SETUP_FIMD0
-        bool
-        help
-          Common setup code for FIMD0.
-
-config EXYNOS4_DEV_USB_OHCI
-        bool
-        help
-          Compile in platform device definition for USB OHCI
-
-config EXYNOS4_SETUP_I2C1
-        bool
-        help
-          Common setup code for i2c bus 1.
-
-config EXYNOS4_SETUP_I2C2
-        bool
-        help
-          Common setup code for i2c bus 2.
-
-config EXYNOS4_SETUP_I2C3
-        bool
-        help
-          Common setup code for i2c bus 3.
-
-config EXYNOS4_SETUP_I2C4
-        bool
-        help
-          Common setup code for i2c bus 4.
-
-config EXYNOS4_SETUP_I2C5
-        bool
-        help
-          Common setup code for i2c bus 5.
-
-config EXYNOS4_SETUP_I2C6
-        bool
-        help
-          Common setup code for i2c bus 6.
-
-config EXYNOS4_SETUP_I2C7
-        bool
-        help
-          Common setup code for i2c bus 7.
-
-config EXYNOS4_SETUP_KEYPAD
-        bool
-        help
-          Common setup code for keypad.
-
-config EXYNOS4_SETUP_SDHCI
-        bool
-        select EXYNOS4_SETUP_SDHCI_GPIO
-        help
-          Internal helper functions for EXYNOS4 based SDHCI systems.
-
-config EXYNOS4_SETUP_SDHCI_GPIO
-        bool
-        help
-          Common setup code for SDHCI gpio.
-
-config EXYNOS4_SETUP_FIMC
-        bool
-        help
-          Common setup code for the camera interfaces.
-
-config EXYNOS4_SETUP_USB_PHY
-        bool
-        help
-          Common setup code for USB PHY controller
-
-config EXYNOS_SETUP_SPI
-        bool
-        help
-          Common setup code for SPI GPIO configurations.
-
-# machine support
-
-if ARCH_EXYNOS4
-
-comment "EXYNOS4210 Boards"
-
-config MACH_SMDKC210
-        bool "SMDKC210"
-        select MACH_SMDKV310
-        help
-          Machine support for Samsung SMDKC210
-
-config MACH_SMDKV310
-        bool "SMDKV310"
-        select CPU_EXYNOS4210
-        select EXYNOS4_DEV_AHCI
-        select EXYNOS4_DEV_USB_OHCI
-        select EXYNOS4_SETUP_FIMD0
-        select EXYNOS4_SETUP_I2C1
-        select EXYNOS4_SETUP_KEYPAD
-        select EXYNOS4_SETUP_SDHCI
-        select EXYNOS4_SETUP_USB_PHY
-        select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_SYSMMU
-        select S3C24XX_PWM
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC1
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select S3C_DEV_I2C1
-        select S3C_DEV_RTC
-        select S3C_DEV_USB_HSOTG
-        select S3C_DEV_WDT
-        select S5P_DEV_FIMC0
-        select S5P_DEV_FIMC1
-        select S5P_DEV_FIMC2
-        select S5P_DEV_FIMC3
-        select S5P_DEV_FIMD0
-        select S5P_DEV_G2D
-        select S5P_DEV_I2C_HDMIPHY
-        select S5P_DEV_JPEG
-        select S5P_DEV_MFC
-        select S5P_DEV_TV
-        select S5P_DEV_USB_EHCI
-        select SAMSUNG_DEV_BACKLIGHT
-        select SAMSUNG_DEV_KEYPAD
-        select SAMSUNG_DEV_PWM
-        help
-          Machine support for Samsung SMDKV310
-
-config MACH_ARMLEX4210
-        bool "ARMLEX4210"
-        select CPU_EXYNOS4210
-        select EXYNOS4_DEV_AHCI
-        select EXYNOS4_SETUP_SDHCI
-        select EXYNOS_DEV_DMA
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select S3C_DEV_RTC
-        select S3C_DEV_WDT
-        help
-          Machine support for Samsung ARMLEX4210 based on EXYNOS4210
-
-config MACH_UNIVERSAL_C210
-        bool "Mobile UNIVERSAL_C210 Board"
-        select CLKSRC_MMIO
-        select CPU_EXYNOS4210
-        select EXYNOS4_SETUP_FIMC
-        select EXYNOS4_SETUP_FIMD0
-        select EXYNOS4_SETUP_I2C1
-        select EXYNOS4_SETUP_I2C3
-        select EXYNOS4_SETUP_I2C5
-        select EXYNOS4_SETUP_SDHCI
-        select EXYNOS4_SETUP_USB_PHY
-        select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_SYSMMU
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select S3C_DEV_I2C1
-        select S3C_DEV_I2C3
-        select S3C_DEV_I2C5
-        select S3C_DEV_USB_HSOTG
-        select S5P_DEV_CSIS0
-        select S5P_DEV_FIMC0
-        select S5P_DEV_FIMC1
-        select S5P_DEV_FIMC2
-        select S5P_DEV_FIMC3
-        select S5P_DEV_FIMD0
-        select S5P_DEV_G2D
-        select S5P_DEV_I2C_HDMIPHY
-        select S5P_DEV_JPEG
-        select S5P_DEV_MFC
-        select S5P_DEV_ONENAND
-        select S5P_DEV_TV
-        select S5P_GPIO_INT
-        select S5P_SETUP_MIPIPHY
-        select SAMSUNG_HRT
-        help
-          Machine support for Samsung Mobile Universal S5PC210 Reference
-          Board.
-
-config MACH_NURI
-        bool "Mobile NURI Board"
-        select CPU_EXYNOS4210
-        select EXYNOS4_SETUP_FIMC
-        select EXYNOS4_SETUP_FIMD0
-        select EXYNOS4_SETUP_I2C1
-        select EXYNOS4_SETUP_I2C3
-        select EXYNOS4_SETUP_I2C5
-        select EXYNOS4_SETUP_I2C6
-        select EXYNOS4_SETUP_SDHCI
-        select EXYNOS4_SETUP_USB_PHY
-        select EXYNOS_DEV_DMA
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select S3C_DEV_I2C1
-        select S3C_DEV_I2C3
-        select S3C_DEV_I2C5
-        select S3C_DEV_I2C6
-        select S3C_DEV_RTC
-        select S3C_DEV_USB_HSOTG
-        select S3C_DEV_WDT
-        select S5P_DEV_CSIS0
-        select S5P_DEV_FIMC0
-        select S5P_DEV_FIMC1
-        select S5P_DEV_FIMC2
-        select S5P_DEV_FIMC3
-        select S5P_DEV_FIMD0
-        select S5P_DEV_G2D
-        select S5P_DEV_JPEG
-        select S5P_DEV_MFC
-        select S5P_DEV_USB_EHCI
-        select S5P_GPIO_INT
-        select S5P_SETUP_MIPIPHY
-        select SAMSUNG_DEV_ADC
-        select SAMSUNG_DEV_PWM
-        help
-          Machine support for Samsung Mobile NURI Board.
-
-config MACH_ORIGEN
-        bool "ORIGEN"
-        select CPU_EXYNOS4210
-        select EXYNOS4_DEV_USB_OHCI
-        select EXYNOS4_SETUP_FIMD0
-        select EXYNOS4_SETUP_SDHCI
-        select EXYNOS4_SETUP_USB_PHY
-        select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_SYSMMU
-        select S3C24XX_PWM
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_RTC
-        select S3C_DEV_USB_HSOTG
-        select S3C_DEV_WDT
-        select S5P_DEV_FIMC0
-        select S5P_DEV_FIMC1
-        select S5P_DEV_FIMC2
-        select S5P_DEV_FIMC3
-        select S5P_DEV_FIMD0
-        select S5P_DEV_G2D
-        select S5P_DEV_I2C_HDMIPHY
-        select S5P_DEV_JPEG
-        select S5P_DEV_MFC
-        select S5P_DEV_TV
-        select S5P_DEV_USB_EHCI
-        select SAMSUNG_DEV_BACKLIGHT
-        select SAMSUNG_DEV_PWM
-        help
-          Machine support for ORIGEN based on Samsung EXYNOS4210
-
-comment "EXYNOS4212 Boards"
-
-config MACH_SMDK4212
-        bool "SMDK4212"
-        select EXYNOS4_SETUP_FIMD0
-        select EXYNOS4_SETUP_I2C1
-        select EXYNOS4_SETUP_I2C3
-        select EXYNOS4_SETUP_I2C7
-        select EXYNOS4_SETUP_KEYPAD
-        select EXYNOS4_SETUP_SDHCI
-        select EXYNOS4_SETUP_USB_PHY
-        select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_SYSMMU
-        select S3C24XX_PWM
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select S3C_DEV_I2C1
-        select S3C_DEV_I2C3
-        select S3C_DEV_I2C7
-        select S3C_DEV_RTC
-        select S3C_DEV_USB_HSOTG
-        select S3C_DEV_WDT
-        select S5P_DEV_FIMC0
-        select S5P_DEV_FIMC1
-        select S5P_DEV_FIMC2
-        select S5P_DEV_FIMC3
-        select S5P_DEV_FIMD0
-        select S5P_DEV_MFC
-        select SAMSUNG_DEV_BACKLIGHT
-        select SAMSUNG_DEV_KEYPAD
-        select SAMSUNG_DEV_PWM
-        select SOC_EXYNOS4212
-        help
-          Machine support for Samsung SMDK4212
-
-comment "EXYNOS4412 Boards"
-
-config MACH_SMDK4412
-        bool "SMDK4412"
-        select MACH_SMDK4212
-        select SOC_EXYNOS4412
-        help
-          Machine support for Samsung SMDK4412
-endif
-
-endif
-
 comment "Flattened Device Tree based board for EXYNOS SoCs"
 
 config MACH_EXYNOS4_DT
         bool "Samsung Exynos4 Machine using device tree"
+        default y
         depends on ARCH_EXYNOS4
         select ARM_AMBA
         select CLKSRC_OF
+        select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210
         select CPU_EXYNOS4210
         select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
-        select PINCTRL
-        select PINCTRL_EXYNOS
         select S5P_DEV_MFC
-        select USE_OF
         help
           Machine support for Samsung Exynos4 machine with device tree enabled.
           Select this if a fdt blob is available for the Exynos4 SoC based board.
@@ -428,28 +114,11 @@ config MACH_EXYNOS5_DT
         depends on ARCH_EXYNOS5
         select ARM_AMBA
         select CLKSRC_OF
-        select USE_OF
+        select USB_ARCH_HAS_XHCI
         help
           Machine support for Samsung EXYNOS5 machine with device tree enabled.
           Select this if a fdt blob is available for the EXYNOS5 SoC based board.
 
-if ARCH_EXYNOS4
-
-comment "Configuration for HSMMC 8-bit bus width"
-
-config EXYNOS4_SDHCI_CH0_8BIT
-        bool "Channel 0 with 8-bit bus"
-        help
-          Support HSMMC Channel 0 8-bit bus.
-          If selected, Channel 1 is disabled.
-
-config EXYNOS4_SDHCI_CH2_8BIT
-        bool "Channel 2 with 8-bit bus"
-        help
-          Support HSMMC Channel 2 8-bit bus.
-          If selected, Channel 3 is disabled.
-endif
-
 endmenu
 
 endif
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index b09b027178f3..e970a7a4e278 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -32,38 +32,5 @@ AFLAGS_exynos-smc.o		:=-Wa,-march=armv7-a$(plus_sec)
 
 # machine support
 
-obj-$(CONFIG_MACH_SMDKC210)             += mach-smdkv310.o
-obj-$(CONFIG_MACH_SMDKV310)             += mach-smdkv310.o
-obj-$(CONFIG_MACH_ARMLEX4210)           += mach-armlex4210.o
-obj-$(CONFIG_MACH_UNIVERSAL_C210)       += mach-universal_c210.o
-obj-$(CONFIG_MACH_NURI)                 += mach-nuri.o
-obj-$(CONFIG_MACH_ORIGEN)               += mach-origen.o
-
-obj-$(CONFIG_MACH_SMDK4212)             += mach-smdk4x12.o
-obj-$(CONFIG_MACH_SMDK4412)             += mach-smdk4x12.o
-
 obj-$(CONFIG_MACH_EXYNOS4_DT)           += mach-exynos4-dt.o
 obj-$(CONFIG_MACH_EXYNOS5_DT)           += mach-exynos5-dt.o
-
-# device support
-
-obj-y                                   += dev-uart.o
-obj-$(CONFIG_ARCH_EXYNOS4)              += dev-audio.o
-obj-$(CONFIG_EXYNOS4_DEV_AHCI)          += dev-ahci.o
-obj-$(CONFIG_EXYNOS_DEV_DMA)            += dma.o
-obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)      += dev-ohci.o
-
-obj-$(CONFIG_ARCH_EXYNOS)               += setup-i2c0.o
-obj-$(CONFIG_EXYNOS4_SETUP_FIMC)        += setup-fimc.o
-obj-$(CONFIG_EXYNOS4_SETUP_FIMD0)       += setup-fimd0.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C1)        += setup-i2c1.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C2)        += setup-i2c2.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C3)        += setup-i2c3.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C4)        += setup-i2c4.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C5)        += setup-i2c5.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C6)        += setup-i2c6.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C7)        += setup-i2c7.o
-obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD)      += setup-keypad.o
-obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
-obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY)     += setup-usb-phy.o
-obj-$(CONFIG_EXYNOS_SETUP_SPI)          += setup-spi.o
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 745e304ad0de..81e6320ca091 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -10,12 +10,14 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/bitops.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/irqchip.h>
 #include <linux/io.h>
 #include <linux/device.h>
 #include <linux/gpio.h>
+#include <clocksource/samsung_pwm.h>
 #include <linux/sched.h>
 #include <linux/serial_core.h>
 #include <linux/of.h>
@@ -38,20 +40,9 @@
 
 #include <mach/regs-irq.h>
 #include <mach/regs-pmu.h>
-#include <mach/regs-gpio.h>
-#include <mach/irqs.h>
 
 #include <plat/cpu.h>
-#include <plat/devs.h>
 #include <plat/pm.h>
-#include <plat/sdhci.h>
-#include <plat/gpio-cfg.h>
-#include <plat/adc-core.h>
-#include <plat/fb-core.h>
-#include <plat/fimc-core.h>
-#include <plat/iic-core.h>
-#include <plat/tv-core.h>
-#include <plat/spi-core.h>
 #include <plat/regs-serial.h>
 
 #include "common.h"
@@ -67,31 +58,25 @@ static const char name_exynos5440[] = "EXYNOS5440";
 static void exynos4_map_io(void);
 static void exynos5_map_io(void);
 static void exynos5440_map_io(void);
-static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 static int exynos_init(void);
 
-unsigned long xxti_f = 0, xusbxti_f = 0;
-
 static struct cpu_table cpu_ids[] __initdata = {
         {
                 .idcode         = EXYNOS4210_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4210,
         }, {
                 .idcode         = EXYNOS4212_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4212,
         }, {
                 .idcode         = EXYNOS4412_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4412,
         }, {
@@ -111,15 +96,6 @@ static struct cpu_table cpu_ids[] __initdata = {
 
 /* Initial IO mappings */
 
-static struct map_desc exynos_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S5P_VA_CHIPID,
-                .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        },
-};
-
 static struct map_desc exynos4_iodesc[] __initdata = {
         {
                 .virtual        = (unsigned long)S3C_VA_SYS,
@@ -317,9 +293,16 @@ void exynos5_restart(char mode, const char *cmd)
                 val = 0x1;
                 addr = EXYNOS_SWRESET;
         } else if (of_machine_is_compatible("samsung,exynos5440")) {
+                u32 status;
                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
+
+                addr = of_iomap(np, 0) + 0xbc;
+                status = __raw_readl(addr);
+
                 addr = of_iomap(np, 0) + 0xcc;
-                val = (0xfff << 20) | (0x1 << 16);
+                val = __raw_readl(addr);
+
+                val = (val & 0xffff0000) | (status & 0xffff);
         } else {
                 pr_err("%s: cannot support non-DT\n", __func__);
                 return;
@@ -337,8 +320,7 @@ void __init exynos_init_late(void)
         exynos_pm_late_initcall();
 }
 
-#ifdef CONFIG_OF
-int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
+static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
                                         int depth, void *data)
 {
         struct map_desc iodesc;
@@ -360,7 +342,6 @@ int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
         iotable_init(&iodesc, 1);
         return 1;
 }
-#endif
 
 /*
  * exynos_map_io
@@ -368,17 +349,11 @@ int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
  * register the standard cpu IO areas
  */
 
-void __init exynos_init_io(struct map_desc *mach_desc, int size)
+void __init exynos_init_io(void)
 {
-#ifdef CONFIG_OF
-        if (initial_boot_params)
-                of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
-        else
-#endif
-                iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
+        debug_ll_io_init();
 
-        if (mach_desc)
-                iotable_init(mach_desc, size);
+        of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
 
         /* detect cpu id and rev. */
         s5p_init_cpu(S5P_VA_CHIPID);
@@ -399,34 +374,6 @@ static void __init exynos4_map_io(void)
                 iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
         if (soc_is_exynos4212() || soc_is_exynos4412())
                 iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
-
-        /* initialize device information early */
-        exynos4_default_sdhci0();
-        exynos4_default_sdhci1();
-        exynos4_default_sdhci2();
-        exynos4_default_sdhci3();
-
-        s3c_adc_setname("samsung-adc-v3");
-
-        s3c_fimc_setname(0, "exynos4-fimc");
-        s3c_fimc_setname(1, "exynos4-fimc");
-        s3c_fimc_setname(2, "exynos4-fimc");
-        s3c_fimc_setname(3, "exynos4-fimc");
-
-        s3c_sdhci_setname(0, "exynos4-sdhci");
-        s3c_sdhci_setname(1, "exynos4-sdhci");
-        s3c_sdhci_setname(2, "exynos4-sdhci");
-        s3c_sdhci_setname(3, "exynos4-sdhci");
-
-        /* The I2C bus controllers are directly compatible with s3c2440 */
-        s3c_i2c0_setname("s3c2440-i2c");
-        s3c_i2c1_setname("s3c2440-i2c");
-        s3c_i2c2_setname("s3c2440-i2c");
-
-        s5p_fb_setname(0, "exynos4-fb");
-        s5p_hdmi_setname("exynos4-hdmi");
-
-        s3c64xx_spi_setname("exynos4210-spi");
 }
 
 static void __init exynos5_map_io(void)
@@ -444,60 +391,8 @@ static void __init exynos5440_map_io(void)
 
 void __init exynos_init_time(void)
 {
-        if (of_have_populated_dt()) {
-#ifdef CONFIG_OF
-                of_clk_init(NULL);
-                clocksource_of_init();
-#endif
-        } else {
-                /* todo: remove after migrating legacy E4 platforms to dt */
-#ifdef CONFIG_ARCH_EXYNOS4
-                exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1);
-                exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
-#endif
-                mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0, EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1);
-        }
-}
-
-static unsigned int max_combiner_nr(void)
-{
-        if (soc_is_exynos5250())
-                return EXYNOS5_MAX_COMBINER_NR;
-        else if (soc_is_exynos4412())
-                return EXYNOS4412_MAX_COMBINER_NR;
-        else if (soc_is_exynos4212())
-                return EXYNOS4212_MAX_COMBINER_NR;
-        else
-                return EXYNOS4210_MAX_COMBINER_NR;
-}
-
-
-void __init exynos4_init_irq(void)
-{
-        unsigned int gic_bank_offset;
-
-        gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
-
-        if (!of_have_populated_dt())
-                gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
-#ifdef CONFIG_OF
-        else
-                irqchip_init();
-#endif
-
-        if (!of_have_populated_dt())
-                combiner_init(S5P_VA_COMBINER_BASE, NULL,
-                              max_combiner_nr(), COMBINER_IRQ(0, 0));
-
-        gic_arch_extn.irq_set_wake = s3c_irq_wake;
-}
-
-void __init exynos5_init_irq(void)
-{
-#ifdef CONFIG_OF
-        irqchip_init();
-#endif
-        gic_arch_extn.irq_set_wake = s3c_irq_wake;
+        of_clk_init(NULL);
+        clocksource_of_init();
 }
 
 struct bus_type exynos_subsys = {
@@ -515,59 +410,19 @@ static int __init exynos_core_init(void)
 }
 core_initcall(exynos_core_init);
 
-#ifdef CONFIG_CACHE_L2X0
 static int __init exynos4_l2x0_cache_init(void)
 {
         int ret;
 
-        if (soc_is_exynos5250() || soc_is_exynos5440())
-                return 0;
-
         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
-        if (!ret) {
-                l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
-                clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
-                return 0;
-        }
-
-        if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
-                l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
-                /* TAG, Data Latency Control: 2 cycles */
-                l2x0_saved_regs.tag_latency = 0x110;
-
-                if (soc_is_exynos4212() || soc_is_exynos4412())
-                        l2x0_saved_regs.data_latency = 0x120;
-                else
-                        l2x0_saved_regs.data_latency = 0x110;
-
-                l2x0_saved_regs.prefetch_ctrl = 0x30000007;
-                l2x0_saved_regs.pwr_ctrl =
-                        (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
-
-                l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
-
-                __raw_writel(l2x0_saved_regs.tag_latency,
-                                S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
-                __raw_writel(l2x0_saved_regs.data_latency,
-                                S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
-
-                /* L2X0 Prefetch Control */
-                __raw_writel(l2x0_saved_regs.prefetch_ctrl,
-                                S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
+        if (ret)
+                return ret;
 
-                /* L2X0 Power Control */
-                __raw_writel(l2x0_saved_regs.pwr_ctrl,
-                                S5P_VA_L2CC + L2X0_POWER_CTRL);
-
-                clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
-                clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
-        }
-
-        l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
+        l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
+        clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
         return 0;
 }
 early_initcall(exynos4_l2x0_cache_init);
-#endif
 
 static int __init exynos_init(void)
 {
@@ -575,350 +430,3 @@ static int __init exynos_init(void)
 
         return device_register(&exynos4_dev);
 }
-
-/* uart registration process */
-
-static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-        struct s3c2410_uartcfg *tcfg = cfg;
-        u32 ucnt;
-
-        for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
-                tcfg->has_fracval = 1;
-
-        s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
-}
-
-static void __iomem *exynos_eint_base;
-
-static DEFINE_SPINLOCK(eint_lock);
-
-static unsigned int eint0_15_data[16];
-
-static inline int exynos4_irq_to_gpio(unsigned int irq)
-{
-        if (irq < IRQ_EINT(0))
-                return -EINVAL;
-
-        irq -= IRQ_EINT(0);
-        if (irq < 8)
-                return EXYNOS4_GPX0(irq);
-
-        irq -= 8;
-        if (irq < 8)
-                return EXYNOS4_GPX1(irq);
-
-        irq -= 8;
-        if (irq < 8)
-                return EXYNOS4_GPX2(irq);
-
-        irq -= 8;
-        if (irq < 8)
-                return EXYNOS4_GPX3(irq);
-
-        return -EINVAL;
-}
-
-static inline int exynos5_irq_to_gpio(unsigned int irq)
-{
-        if (irq < IRQ_EINT(0))
-                return -EINVAL;
-
-        irq -= IRQ_EINT(0);
-        if (irq < 8)
-                return EXYNOS5_GPX0(irq);
-
-        irq -= 8;
-        if (irq < 8)
-                return EXYNOS5_GPX1(irq);
-
-        irq -= 8;
-        if (irq < 8)
-                return EXYNOS5_GPX2(irq);
-
-        irq -= 8;
-        if (irq < 8)
-                return EXYNOS5_GPX3(irq);
-
-        return -EINVAL;
-}
-
-static unsigned int exynos4_eint0_15_src_int[16] = {
-        EXYNOS4_IRQ_EINT0,
-        EXYNOS4_IRQ_EINT1,
-        EXYNOS4_IRQ_EINT2,
-        EXYNOS4_IRQ_EINT3,
-        EXYNOS4_IRQ_EINT4,
-        EXYNOS4_IRQ_EINT5,
-        EXYNOS4_IRQ_EINT6,
-        EXYNOS4_IRQ_EINT7,
-        EXYNOS4_IRQ_EINT8,
-        EXYNOS4_IRQ_EINT9,
-        EXYNOS4_IRQ_EINT10,
-        EXYNOS4_IRQ_EINT11,
-        EXYNOS4_IRQ_EINT12,
-        EXYNOS4_IRQ_EINT13,
-        EXYNOS4_IRQ_EINT14,
-        EXYNOS4_IRQ_EINT15,
-};
-
-static unsigned int exynos5_eint0_15_src_int[16] = {
-        EXYNOS5_IRQ_EINT0,
-        EXYNOS5_IRQ_EINT1,
-        EXYNOS5_IRQ_EINT2,
-        EXYNOS5_IRQ_EINT3,
-        EXYNOS5_IRQ_EINT4,
-        EXYNOS5_IRQ_EINT5,
-        EXYNOS5_IRQ_EINT6,
-        EXYNOS5_IRQ_EINT7,
-        EXYNOS5_IRQ_EINT8,
-        EXYNOS5_IRQ_EINT9,
-        EXYNOS5_IRQ_EINT10,
-        EXYNOS5_IRQ_EINT11,
-        EXYNOS5_IRQ_EINT12,
-        EXYNOS5_IRQ_EINT13,
-        EXYNOS5_IRQ_EINT14,
-        EXYNOS5_IRQ_EINT15,
-};
-static inline void exynos_irq_eint_mask(struct irq_data *data)
-{
-        u32 mask;
-
-        spin_lock(&eint_lock);
-        mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
-        mask |= EINT_OFFSET_BIT(data->irq);
-        __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
-        spin_unlock(&eint_lock);
-}
-
-static void exynos_irq_eint_unmask(struct irq_data *data)
-{
-        u32 mask;
-
-        spin_lock(&eint_lock);
-        mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
-        mask &= ~(EINT_OFFSET_BIT(data->irq));
-        __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
-        spin_unlock(&eint_lock);
-}
-
-static inline void exynos_irq_eint_ack(struct irq_data *data)
-{
-        __raw_writel(EINT_OFFSET_BIT(data->irq),
-                     EINT_PEND(exynos_eint_base, data->irq));
-}
-
-static void exynos_irq_eint_maskack(struct irq_data *data)
-{
-        exynos_irq_eint_mask(data);
-        exynos_irq_eint_ack(data);
-}
-
-static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
-{
-        int offs = EINT_OFFSET(data->irq);
-        int shift;
-        u32 ctrl, mask;
-        u32 newvalue = 0;
-
-        switch (type) {
-        case IRQ_TYPE_EDGE_RISING:
-                newvalue = S5P_IRQ_TYPE_EDGE_RISING;
-                break;
-
-        case IRQ_TYPE_EDGE_FALLING:
-                newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
-                break;
-
-        case IRQ_TYPE_EDGE_BOTH:
-                newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
-                break;
-
-        case IRQ_TYPE_LEVEL_LOW:
-                newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
-                break;
-
-        case IRQ_TYPE_LEVEL_HIGH:
-                newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
-                break;
-
-        default:
-                printk(KERN_ERR "No such irq type %d", type);
-                return -EINVAL;
-        }
-
-        shift = (offs & 0x7) * 4;
-        mask = 0x7 << shift;
-
-        spin_lock(&eint_lock);
-        ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
-        ctrl &= ~mask;
-        ctrl |= newvalue << shift;
-        __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
-        spin_unlock(&eint_lock);
-
-        if (soc_is_exynos5250())
-                s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
-        else
-                s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
-
-        return 0;
-}
-
-static struct irq_chip exynos_irq_eint = {
-        .name           = "exynos-eint",
-        .irq_mask       = exynos_irq_eint_mask,
-        .irq_unmask     = exynos_irq_eint_unmask,
-        .irq_mask_ack   = exynos_irq_eint_maskack,
-        .irq_ack        = exynos_irq_eint_ack,
-        .irq_set_type   = exynos_irq_eint_set_type,
-#ifdef CONFIG_PM
-        .irq_set_wake   = s3c_irqext_wake,
-#endif
-};
-
-/*
- * exynos4_irq_demux_eint
- *
- * This function demuxes the IRQ from from EINTs 16 to 31.
- * It is designed to be inlined into the specific handler
- * s5p_irq_demux_eintX_Y.
- *
- * Each EINT pend/mask registers handle eight of them.
- */
-static inline void exynos_irq_demux_eint(unsigned int start)
-{
-        unsigned int irq;
-
-        u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
-        u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
-
-        status &= ~mask;
-        status &= 0xff;
-
-        while (status) {
-                irq = fls(status) - 1;
-                generic_handle_irq(irq + start);
-                status &= ~(1 << irq);
-        }
-}
-
-static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
-{
-        struct irq_chip *chip = irq_get_chip(irq);
-        chained_irq_enter(chip, desc);
-        exynos_irq_demux_eint(IRQ_EINT(16));
-        exynos_irq_demux_eint(IRQ_EINT(24));
-        chained_irq_exit(chip, desc);
-}
-
-static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
-{
-        u32 *irq_data = irq_get_handler_data(irq);
-        struct irq_chip *chip = irq_get_chip(irq);
-
-        chained_irq_enter(chip, desc);
-        generic_handle_irq(*irq_data);
-        chained_irq_exit(chip, desc);
-}
-
-static int __init exynos_init_irq_eint(void)
-{
-        int irq;
-
-#ifdef CONFIG_PINCTRL_SAMSUNG
-        /*
-         * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
-         * functionality along with support for external gpio and wakeup
-         * interrupts. If the samsung pinctrl driver is enabled and includes
-         * the wakeup interrupt support, then the setting up external wakeup
-         * interrupts here can be skipped. This check here is temporary to
-         * allow exynos4 platforms that do not use Samsung pinctrl driver to
-         * co-exist with platforms that do. When all of the Samsung Exynos4
-         * platforms switch over to using the pinctrl driver, the wakeup
-         * interrupt support code here can be completely removed.
-         */
-        static const struct of_device_id exynos_pinctrl_ids[] = {
-                { .compatible = "samsung,exynos4210-pinctrl", },
-                { .compatible = "samsung,exynos4x12-pinctrl", },
-                { .compatible = "samsung,exynos5250-pinctrl", },
-        };
-        struct device_node *pctrl_np, *wkup_np;
-        const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
-
-        for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
-                if (of_device_is_available(pctrl_np)) {
-                        wkup_np = of_find_compatible_node(pctrl_np, NULL,
-                                                        wkup_compat);
-                        if (wkup_np)
-                                return -ENODEV;
-                }
-        }
-#endif
-        if (soc_is_exynos5440())
-                return 0;
-
-        if (soc_is_exynos5250())
-                exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
-        else
-                exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
-
-        if (exynos_eint_base == NULL) {
-                pr_err("unable to ioremap for EINT base address\n");
-                return -ENOMEM;
-        }
-
-        for (irq = 0 ; irq <= 31 ; irq++) {
-                irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
-                                         handle_level_irq);
-                set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
-        }
-
-        irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
-
-        for (irq = 0 ; irq <= 15 ; irq++) {
-                eint0_15_data[irq] = IRQ_EINT(irq);
-
-                if (soc_is_exynos5250()) {
-                        irq_set_handler_data(exynos5_eint0_15_src_int[irq],
-                                             &eint0_15_data[irq]);
-                        irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
-                                                exynos_irq_eint0_15);
-                } else {
-                        irq_set_handler_data(exynos4_eint0_15_src_int[irq],
-                                             &eint0_15_data[irq]);
-                        irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
-                                                exynos_irq_eint0_15);
-                }
-        }
-
-        return 0;
-}
-arch_initcall(exynos_init_irq_eint);
-
-static struct resource exynos4_pmu_resource[] = {
-        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
-        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
-#if defined(CONFIG_SOC_EXYNOS4412)
-        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
-        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
-#endif
-};
-
-static struct platform_device exynos4_device_pmu = {
-        .name           = "arm-pmu",
-        .num_resources  = ARRAY_SIZE(exynos4_pmu_resource),
-        .resource       = exynos4_pmu_resource,
-};
-
-static int __init exynos_armpmu_init(void)
-{
-        if (!of_have_populated_dt()) {
-                if (soc_is_exynos4210() || soc_is_exynos4212())
-                        exynos4_device_pmu.num_resources = 2;
-                platform_device_register(&exynos4_device_pmu);
-        }
-
-        return 0;
-}
-arch_initcall(exynos_armpmu_init);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 60dd35cc01a6..38d45fd23be4 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -19,9 +19,7 @@ void exynos_init_time(void);
 extern unsigned long xxti_f, xusbxti_f;
 
 struct map_desc;
-void exynos_init_io(struct map_desc *mach_desc, int size);
-void exynos4_init_irq(void);
-void exynos5_init_irq(void);
+void exynos_init_io(void);
 void exynos4_restart(char mode, const char *cmd);
 void exynos5_restart(char mode, const char *cmd);
 void exynos_init_late(void);
@@ -32,6 +30,8 @@ void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
 
 void exynos_firmware_init(void);
 
+void exynos_set_timer_source(u8 channels);
+
 #ifdef CONFIG_PM_GENERIC_DOMAINS
 int exynos_pm_late_initcall(void);
 #else
diff --git a/arch/arm/mach-exynos/dev-ahci.c b/arch/arm/mach-exynos/dev-ahci.c
deleted file mode 100644
index ce1aad3eeeb9..000000000000
--- a/arch/arm/mach-exynos/dev-ahci.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/* linux/arch/arm/mach-exynos4/dev-ahci.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - AHCI support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/ahci_platform.h>
-
-#include <plat/cpu.h>
-
-#include <mach/irqs.h>
-#include <mach/map.h>
-#include <mach/regs-pmu.h>
-
-/* PHY Control Register */
-#define SATA_CTRL0              0x0
-/* PHY Link Control Register */
-#define SATA_CTRL1              0x4
-/* PHY Status Register */
-#define SATA_PHY_STATUS         0x8
-
-#define SATA_CTRL0_RX_DATA_VALID(x)     (x << 27)
-#define SATA_CTRL0_SPEED_MODE           (1 << 26)
-#define SATA_CTRL0_M_PHY_CAL            (1 << 19)
-#define SATA_CTRL0_PHY_CMU_RST_N        (1 << 10)
-#define SATA_CTRL0_M_PHY_LN_RST_N       (1 << 9)
-#define SATA_CTRL0_PHY_POR_N            (1 << 8)
-
-#define SATA_CTRL1_RST_PMALIVE_N        (1 << 8)
-#define SATA_CTRL1_RST_RXOOB_N          (1 << 7)
-#define SATA_CTRL1_RST_RX_N             (1 << 6)
-#define SATA_CTRL1_RST_TX_N             (1 << 5)
-
-#define SATA_PHY_STATUS_CMU_OK          (1 << 18)
-#define SATA_PHY_STATUS_LANE_OK         (1 << 16)
-
-#define LANE0           0x200
-#define COM_LANE        0xA00
-
-#define HOST_PORTS_IMPL 0xC
-#define SCLK_SATA_FREQ  (67 * MHZ)
-
-static void __iomem *phy_base, *phy_ctrl;
-
-struct phy_reg {
-        u8      reg;
-        u8      val;
-};
-
-/* SATA PHY setup */
-static const struct phy_reg exynos4_sataphy_cmu[] = {
-        { 0x00, 0x06 }, { 0x02, 0x80 }, { 0x22, 0xa0 }, { 0x23, 0x42 },
-        { 0x2e, 0x04 }, { 0x2f, 0x50 }, { 0x30, 0x70 }, { 0x31, 0x02 },
-        { 0x32, 0x25 }, { 0x33, 0x40 }, { 0x34, 0x01 }, { 0x35, 0x40 },
-        { 0x61, 0x2e }, { 0x63, 0x5e }, { 0x65, 0x42 }, { 0x66, 0xd1 },
-        { 0x67, 0x20 }, { 0x68, 0x28 }, { 0x69, 0x78 }, { 0x6a, 0x04 },
-        { 0x6b, 0xc8 }, { 0x6c, 0x06 },
-};
-
-static const struct phy_reg exynos4_sataphy_lane[] = {
-        { 0x00, 0x02 }, { 0x05, 0x10 }, { 0x06, 0x84 }, { 0x07, 0x04 },
-        { 0x08, 0xe0 }, { 0x10, 0x23 }, { 0x13, 0x05 }, { 0x14, 0x30 },
-        { 0x15, 0x00 }, { 0x17, 0x70 }, { 0x18, 0xf2 }, { 0x19, 0x1e },
-        { 0x1a, 0x18 }, { 0x1b, 0x0d }, { 0x1c, 0x08 }, { 0x50, 0x60 },
-        { 0x51, 0x0f },
-};
-
-static const struct phy_reg exynos4_sataphy_comlane[] = {
-        { 0x01, 0x20 }, { 0x03, 0x40 }, { 0x04, 0x3c }, { 0x05, 0x7d },
-        { 0x06, 0x1d }, { 0x07, 0xcf }, { 0x08, 0x05 }, { 0x09, 0x63 },
-        { 0x0a, 0x29 }, { 0x0b, 0xc4 }, { 0x0c, 0x01 }, { 0x0d, 0x03 },
-        { 0x0e, 0x28 }, { 0x0f, 0x98 }, { 0x10, 0x19 }, { 0x13, 0x80 },
-        { 0x14, 0xf0 }, { 0x15, 0xd0 }, { 0x39, 0xa0 }, { 0x3a, 0xa0 },
-        { 0x3b, 0xa0 }, { 0x3c, 0xa0 }, { 0x3d, 0xa0 }, { 0x3e, 0xa0 },
-        { 0x3f, 0xa0 }, { 0x40, 0x42 }, { 0x42, 0x80 }, { 0x43, 0x58 },
-        { 0x45, 0x44 }, { 0x46, 0x5c }, { 0x47, 0x86 }, { 0x48, 0x8d },
-        { 0x49, 0xd0 }, { 0x4a, 0x09 }, { 0x4b, 0x90 }, { 0x4c, 0x07 },
-        { 0x4d, 0x40 }, { 0x51, 0x20 }, { 0x52, 0x32 }, { 0x7f, 0xd8 },
-        { 0x80, 0x1a }, { 0x81, 0xff }, { 0x82, 0x11 }, { 0x83, 0x00 },
-        { 0x87, 0xf0 }, { 0x87, 0xff }, { 0x87, 0xff }, { 0x87, 0xff },
-        { 0x87, 0xff }, { 0x8c, 0x1c }, { 0x8d, 0xc2 }, { 0x8e, 0xc3 },
-        { 0x8f, 0x3f }, { 0x90, 0x0a }, { 0x96, 0xf8 },
-};
-
-static int wait_for_phy_ready(void __iomem *reg, unsigned long bit)
-{
-        unsigned long timeout;
-
-        /* wait for maximum of 3 sec */
-        timeout = jiffies + msecs_to_jiffies(3000);
-        while (!(__raw_readl(reg) & bit)) {
-                if (time_after(jiffies, timeout))
-                        return -1;
-                cpu_relax();
-        }
-        return 0;
-}
-
-static int ahci_phy_init(void __iomem *mmio)
-{
-        int i, ctrl0;
-
-        for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++)
-                __raw_writeb(exynos4_sataphy_cmu[i].val,
-                phy_base + (exynos4_sataphy_cmu[i].reg * 4));
-
-        for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++)
-                __raw_writeb(exynos4_sataphy_lane[i].val,
-                phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4);
-
-        for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++)
-                __raw_writeb(exynos4_sataphy_comlane[i].val,
-                phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4);
-
-        __raw_writeb(0x07, phy_base);
-
-        ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
-        ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N;
-        __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
-
-        if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
-                                SATA_PHY_STATUS_CMU_OK) < 0) {
-                printk(KERN_ERR "PHY CMU not ready\n");
-                return -EBUSY;
-        }
-
-        __raw_writeb(0x03, phy_base + (COM_LANE * 4));
-
-        ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
-        ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N;
-        __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
-
-        if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
-                                SATA_PHY_STATUS_LANE_OK) < 0) {
-                printk(KERN_ERR "PHY LANE not ready\n");
-                return -EBUSY;
-        }
-
-        ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
-        ctrl0 |= SATA_CTRL0_M_PHY_CAL;
-        __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
-
-        return 0;
-}
-
-static int exynos4_ahci_init(struct device *dev, void __iomem *mmio)
-{
-        struct clk *clk_sata, *clk_sataphy, *clk_sclk_sata;
-        int val, ret;
-
-        phy_base = ioremap(EXYNOS4_PA_SATAPHY, SZ_64K);
-        if (!phy_base) {
-                dev_err(dev, "failed to allocate memory for SATA PHY\n");
-                return -ENOMEM;
-        }
-
-        phy_ctrl = ioremap(EXYNOS4_PA_SATAPHY_CTRL, SZ_16);
-        if (!phy_ctrl) {
-                dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n");
-                ret = -ENOMEM;
-                goto err1;
-        }
-
-        clk_sata = clk_get(dev, "sata");
-        if (IS_ERR(clk_sata)) {
-                dev_err(dev, "failed to get sata clock\n");
-                ret = PTR_ERR(clk_sata);
-                clk_sata = NULL;
-                goto err2;
-
-        }
-        clk_enable(clk_sata);
-
-        clk_sataphy = clk_get(dev, "sataphy");
-        if (IS_ERR(clk_sataphy)) {
-                dev_err(dev, "failed to get sataphy clock\n");
-                ret = PTR_ERR(clk_sataphy);
-                clk_sataphy = NULL;
-                goto err3;
-        }
-        clk_enable(clk_sataphy);
-
-        clk_sclk_sata = clk_get(dev, "sclk_sata");
-        if (IS_ERR(clk_sclk_sata)) {
-                dev_err(dev, "failed to get sclk_sata\n");
-                ret = PTR_ERR(clk_sclk_sata);
-                clk_sclk_sata = NULL;
-                goto err4;
-        }
-        clk_enable(clk_sclk_sata);
-        clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ);
-
-        __raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, S5P_PMU_SATA_PHY_CONTROL);
-
-        /* Enable PHY link control */
-        val = SATA_CTRL1_RST_PMALIVE_N | SATA_CTRL1_RST_RXOOB_N |
-                        SATA_CTRL1_RST_RX_N | SATA_CTRL1_RST_TX_N;
-        __raw_writel(val, phy_ctrl + SATA_CTRL1);
-
-        /* Set communication speed as 3Gbps and enable PHY power */
-        val = SATA_CTRL0_RX_DATA_VALID(3) | SATA_CTRL0_SPEED_MODE |
-                        SATA_CTRL0_PHY_POR_N;
-        __raw_writel(val, phy_ctrl + SATA_CTRL0);
-
-        /* Port0 is available */
-        __raw_writel(0x1, mmio + HOST_PORTS_IMPL);
-
-        return ahci_phy_init(mmio);
-
-err4:
-        clk_disable(clk_sataphy);
-        clk_put(clk_sataphy);
-err3:
-        clk_disable(clk_sata);
-        clk_put(clk_sata);
-err2:
-        iounmap(phy_ctrl);
-err1:
-        iounmap(phy_base);
-
-        return ret;
-}
-
-static struct ahci_platform_data exynos4_ahci_pdata = {
-        .init = exynos4_ahci_init,
-};
-
-static struct resource exynos4_ahci_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_SATA, SZ_64K),
-        [1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_SATA),
-};
-
-static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device exynos4_device_ahci = {
-        .name           = "ahci",
-        .id             = -1,
-        .resource       = exynos4_ahci_resource,
-        .num_resources  = ARRAY_SIZE(exynos4_ahci_resource),
-        .dev            = {
-                .platform_data          = &exynos4_ahci_pdata,
-                .dma_mask               = &exynos4_ahci_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
deleted file mode 100644
index c662c89794b2..000000000000
--- a/arch/arm/mach-exynos/dev-audio.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/* linux/arch/arm/mach-exynos4/dev-audio.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright (c) 2010 Samsung Electronics Co. Ltd
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <linux/platform_data/asoc-s3c.h>
-
-#include <plat/gpio-cfg.h>
-
-#include <mach/map.h>
-#include <mach/dma.h>
-#include <mach/irqs.h>
-
-#define EXYNOS4_AUDSS_INT_MEM   (0x03000000)
-
-static int exynos4_cfg_i2s(struct platform_device *pdev)
-{
-        /* configure GPIO for i2s port */
-        switch (pdev->id) {
-        case 0:
-                s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2));
-                break;
-        case 1:
-                s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2));
-                break;
-        case 2:
-                s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4));
-                break;
-        default:
-                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static struct s3c_audio_pdata i2sv5_pdata = {
-        .cfg_gpio = exynos4_cfg_i2s,
-        .type = {
-                .i2s = {
-                        .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
-                                         | QUIRK_NEED_RSTCLR,
-                        .idma_addr = EXYNOS4_AUDSS_INT_MEM,
-                },
-        },
-};
-
-static struct resource exynos4_i2s0_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S0, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
-        [2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
-        [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX),
-};
-
-struct platform_device exynos4_device_i2s0 = {
-        .name = "samsung-i2s",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(exynos4_i2s0_resource),
-        .resource = exynos4_i2s0_resource,
-        .dev = {
-                .platform_data = &i2sv5_pdata,
-        },
-};
-
-static struct s3c_audio_pdata i2sv3_pdata = {
-        .cfg_gpio = exynos4_cfg_i2s,
-        .type = {
-                .i2s = {
-                        .quirks = QUIRK_NO_MUXPSR,
-                },
-        },
-};
-
-static struct resource exynos4_i2s1_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S1, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_I2S1_TX),
-        [2] = DEFINE_RES_DMA(DMACH_I2S1_RX),
-};
-
-struct platform_device exynos4_device_i2s1 = {
-        .name = "samsung-i2s",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(exynos4_i2s1_resource),
-        .resource = exynos4_i2s1_resource,
-        .dev = {
-                .platform_data = &i2sv3_pdata,
-        },
-};
-
-static struct resource exynos4_i2s2_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S2, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_I2S2_TX),
-        [2] = DEFINE_RES_DMA(DMACH_I2S2_RX),
-};
-
-struct platform_device exynos4_device_i2s2 = {
-        .name = "samsung-i2s",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(exynos4_i2s2_resource),
-        .resource = exynos4_i2s2_resource,
-        .dev = {
-                .platform_data = &i2sv3_pdata,
-        },
-};
-
-/* PCM Controller platform_devices */
-
-static int exynos4_pcm_cfg_gpio(struct platform_device *pdev)
-{
-        switch (pdev->id) {
-        case 0:
-                s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3));
-                break;
-        case 1:
-                s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3));
-                break;
-        case 2:
-                s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3));
-                break;
-        default:
-                printk(KERN_DEBUG "Invalid PCM Controller number!");
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static struct s3c_audio_pdata s3c_pcm_pdata = {
-        .cfg_gpio = exynos4_pcm_cfg_gpio,
-};
-
-static struct resource exynos4_pcm0_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM0, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
-        [2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
-};
-
-struct platform_device exynos4_device_pcm0 = {
-        .name = "samsung-pcm",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(exynos4_pcm0_resource),
-        .resource = exynos4_pcm0_resource,
-        .dev = {
-                .platform_data = &s3c_pcm_pdata,
-        },
-};
-
-static struct resource exynos4_pcm1_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM1, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_PCM1_TX),
-        [2] = DEFINE_RES_DMA(DMACH_PCM1_RX),
-};
-
-struct platform_device exynos4_device_pcm1 = {
-        .name = "samsung-pcm",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(exynos4_pcm1_resource),
-        .resource = exynos4_pcm1_resource,
-        .dev = {
-                .platform_data = &s3c_pcm_pdata,
-        },
-};
-
-static struct resource exynos4_pcm2_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM2, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_PCM2_TX),
-        [2] = DEFINE_RES_DMA(DMACH_PCM2_RX),
-};
-
-struct platform_device exynos4_device_pcm2 = {
-        .name = "samsung-pcm",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(exynos4_pcm2_resource),
-        .resource = exynos4_pcm2_resource,
-        .dev = {
-                .platform_data = &s3c_pcm_pdata,
-        },
-};
-
-/* AC97 Controller platform devices */
-
-static int exynos4_ac97_cfg_gpio(struct platform_device *pdev)
-{
-        return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4));
-}
-
-static struct resource exynos4_ac97_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_AC97, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT),
-        [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN),
-        [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN),
-        [4] = DEFINE_RES_IRQ(EXYNOS4_IRQ_AC97),
-};
-
-static struct s3c_audio_pdata s3c_ac97_pdata = {
-        .cfg_gpio = exynos4_ac97_cfg_gpio,
-};
-
-static u64 exynos4_ac97_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device exynos4_device_ac97 = {
-        .name = "samsung-ac97",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(exynos4_ac97_resource),
-        .resource = exynos4_ac97_resource,
-        .dev = {
-                .platform_data = &s3c_ac97_pdata,
-                .dma_mask = &exynos4_ac97_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-
-/* S/PDIF Controller platform_device */
-
-static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
-{
-        s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
-
-        return 0;
-}
-
-static struct resource exynos4_spdif_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_SPDIF, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_SPDIF),
-};
-
-static struct s3c_audio_pdata samsung_spdif_pdata = {
-        .cfg_gpio = exynos4_spdif_cfg_gpio,
-};
-
-static u64 exynos4_spdif_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device exynos4_device_spdif = {
-        .name = "samsung-spdif",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(exynos4_spdif_resource),
-        .resource = exynos4_spdif_resource,
-        .dev = {
-                .platform_data = &samsung_spdif_pdata,
-                .dma_mask = &exynos4_spdif_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
diff --git a/arch/arm/mach-exynos/dev-ohci.c b/arch/arm/mach-exynos/dev-ohci.c
deleted file mode 100644
index d5bc129e6bb7..000000000000
--- a/arch/arm/mach-exynos/dev-ohci.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* linux/arch/arm/mach-exynos/dev-ohci.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS - OHCI support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/usb-ohci-exynos.h>
-
-#include <mach/irqs.h>
-#include <mach/map.h>
-
-#include <plat/devs.h>
-#include <plat/usb-phy.h>
-
-static struct resource exynos4_ohci_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_OHCI, SZ_256),
-        [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
-};
-
-static u64 exynos4_ohci_dma_mask = DMA_BIT_MASK(32);
-
-struct platform_device exynos4_device_ohci = {
-        .name           = "exynos-ohci",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(exynos4_ohci_resource),
-        .resource       = exynos4_ohci_resource,
-        .dev            = {
-                .dma_mask               = &exynos4_ohci_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        }
-};
-
-void __init exynos4_ohci_set_platdata(struct exynos4_ohci_platdata *pd)
-{
-        struct exynos4_ohci_platdata *npd;
-
-        npd = s3c_set_platdata(pd, sizeof(struct exynos4_ohci_platdata),
-                        &exynos4_device_ohci);
-
-        if (!npd->phy_init)
-                npd->phy_init = s5p_usb_phy_init;
-        if (!npd->phy_exit)
-                npd->phy_exit = s5p_usb_phy_exit;
-}
diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c
deleted file mode 100644
index c48aff02c786..000000000000
--- a/arch/arm/mach-exynos/dev-uart.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Base EXYNOS UART resource and device definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/ioport.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/irqs.h>
-
-#include <plat/devs.h>
-
-#define EXYNOS_UART_RESOURCE(_series, _nr)      \
-static struct resource exynos##_series##_uart##_nr##_resource[] = {     \
-        [0] = DEFINE_RES_MEM(EXYNOS##_series##_PA_UART##_nr, EXYNOS##_series##_SZ_UART),        \
-        [1] = DEFINE_RES_IRQ(EXYNOS##_series##_IRQ_UART##_nr),  \
-};
-
-EXYNOS_UART_RESOURCE(4, 0)
-EXYNOS_UART_RESOURCE(4, 1)
-EXYNOS_UART_RESOURCE(4, 2)
-EXYNOS_UART_RESOURCE(4, 3)
-
-struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
-        [0] = {
-                .resources      = exynos4_uart0_resource,
-                .nr_resources   = ARRAY_SIZE(exynos4_uart0_resource),
-        },
-        [1] = {
-                .resources      = exynos4_uart1_resource,
-                .nr_resources   = ARRAY_SIZE(exynos4_uart1_resource),
-        },
-        [2] = {
-                .resources      = exynos4_uart2_resource,
-                .nr_resources   = ARRAY_SIZE(exynos4_uart2_resource),
-        },
-        [3] = {
-                .resources      = exynos4_uart3_resource,
-                .nr_resources   = ARRAY_SIZE(exynos4_uart3_resource),
-        },
-};
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
deleted file mode 100644
index 87e07d6fc615..000000000000
--- a/arch/arm/mach-exynos/dma.c
+++ /dev/null
@@ -1,322 +0,0 @@
-/* linux/arch/arm/mach-exynos4/dma.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/dma-mapping.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/pl330.h>
-#include <linux/of.h>
-
-#include <asm/irq.h>
-#include <plat/devs.h>
-#include <plat/irqs.h>
-#include <plat/cpu.h>
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/dma.h>
-
-static u8 exynos4210_pdma0_peri[] = {
-        DMACH_PCM0_RX,
-        DMACH_PCM0_TX,
-        DMACH_PCM2_RX,
-        DMACH_PCM2_TX,
-        DMACH_MSM_REQ0,
-        DMACH_MSM_REQ2,
-        DMACH_SPI0_RX,
-        DMACH_SPI0_TX,
-        DMACH_SPI2_RX,
-        DMACH_SPI2_TX,
-        DMACH_I2S0S_TX,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S2_RX,
-        DMACH_I2S2_TX,
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART2_RX,
-        DMACH_UART2_TX,
-        DMACH_UART4_RX,
-        DMACH_UART4_TX,
-        DMACH_SLIMBUS0_RX,
-        DMACH_SLIMBUS0_TX,
-        DMACH_SLIMBUS2_RX,
-        DMACH_SLIMBUS2_TX,
-        DMACH_SLIMBUS4_RX,
-        DMACH_SLIMBUS4_TX,
-        DMACH_AC97_MICIN,
-        DMACH_AC97_PCMIN,
-        DMACH_AC97_PCMOUT,
-};
-
-static u8 exynos4212_pdma0_peri[] = {
-        DMACH_PCM0_RX,
-        DMACH_PCM0_TX,
-        DMACH_PCM2_RX,
-        DMACH_PCM2_TX,
-        DMACH_MIPI_HSI0,
-        DMACH_MIPI_HSI1,
-        DMACH_SPI0_RX,
-        DMACH_SPI0_TX,
-        DMACH_SPI2_RX,
-        DMACH_SPI2_TX,
-        DMACH_I2S0S_TX,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S2_RX,
-        DMACH_I2S2_TX,
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART2_RX,
-        DMACH_UART2_TX,
-        DMACH_UART4_RX,
-        DMACH_UART4_TX,
-        DMACH_SLIMBUS0_RX,
-        DMACH_SLIMBUS0_TX,
-        DMACH_SLIMBUS2_RX,
-        DMACH_SLIMBUS2_TX,
-        DMACH_SLIMBUS4_RX,
-        DMACH_SLIMBUS4_TX,
-        DMACH_AC97_MICIN,
-        DMACH_AC97_PCMIN,
-        DMACH_AC97_PCMOUT,
-        DMACH_MIPI_HSI4,
-        DMACH_MIPI_HSI5,
-};
-
-static u8 exynos5250_pdma0_peri[] = {
-        DMACH_PCM0_RX,
-        DMACH_PCM0_TX,
-        DMACH_PCM2_RX,
-        DMACH_PCM2_TX,
-        DMACH_SPI0_RX,
-        DMACH_SPI0_TX,
-        DMACH_SPI2_RX,
-        DMACH_SPI2_TX,
-        DMACH_I2S0S_TX,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S2_RX,
-        DMACH_I2S2_TX,
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART2_RX,
-        DMACH_UART2_TX,
-        DMACH_UART4_RX,
-        DMACH_UART4_TX,
-        DMACH_SLIMBUS0_RX,
-        DMACH_SLIMBUS0_TX,
-        DMACH_SLIMBUS2_RX,
-        DMACH_SLIMBUS2_TX,
-        DMACH_SLIMBUS4_RX,
-        DMACH_SLIMBUS4_TX,
-        DMACH_AC97_MICIN,
-        DMACH_AC97_PCMIN,
-        DMACH_AC97_PCMOUT,
-        DMACH_MIPI_HSI0,
-        DMACH_MIPI_HSI2,
-        DMACH_MIPI_HSI4,
-        DMACH_MIPI_HSI6,
-};
-
-static struct dma_pl330_platdata exynos_pdma0_pdata;
-
-static AMBA_AHB_DEVICE(exynos_pdma0, "dma-pl330.0", 0x00041330,
-        EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata);
-
-static u8 exynos4210_pdma1_peri[] = {
-        DMACH_PCM0_RX,
-        DMACH_PCM0_TX,
-        DMACH_PCM1_RX,
-        DMACH_PCM1_TX,
-        DMACH_MSM_REQ1,
-        DMACH_MSM_REQ3,
-        DMACH_SPI1_RX,
-        DMACH_SPI1_TX,
-        DMACH_I2S0S_TX,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S1_RX,
-        DMACH_I2S1_TX,
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART1_RX,
-        DMACH_UART1_TX,
-        DMACH_UART3_RX,
-        DMACH_UART3_TX,
-        DMACH_SLIMBUS1_RX,
-        DMACH_SLIMBUS1_TX,
-        DMACH_SLIMBUS3_RX,
-        DMACH_SLIMBUS3_TX,
-        DMACH_SLIMBUS5_RX,
-        DMACH_SLIMBUS5_TX,
-};
-
-static u8 exynos4212_pdma1_peri[] = {
-        DMACH_PCM0_RX,
-        DMACH_PCM0_TX,
-        DMACH_PCM1_RX,
-        DMACH_PCM1_TX,
-        DMACH_MIPI_HSI2,
-        DMACH_MIPI_HSI3,
-        DMACH_SPI1_RX,
-        DMACH_SPI1_TX,
-        DMACH_I2S0S_TX,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S1_RX,
-        DMACH_I2S1_TX,
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART1_RX,
-        DMACH_UART1_TX,
-        DMACH_UART3_RX,
-        DMACH_UART3_TX,
-        DMACH_SLIMBUS1_RX,
-        DMACH_SLIMBUS1_TX,
-        DMACH_SLIMBUS3_RX,
-        DMACH_SLIMBUS3_TX,
-        DMACH_SLIMBUS5_RX,
-        DMACH_SLIMBUS5_TX,
-        DMACH_SLIMBUS0AUX_RX,
-        DMACH_SLIMBUS0AUX_TX,
-        DMACH_SPDIF,
-        DMACH_MIPI_HSI6,
-        DMACH_MIPI_HSI7,
-};
-
-static u8 exynos5250_pdma1_peri[] = {
-        DMACH_PCM0_RX,
-        DMACH_PCM0_TX,
-        DMACH_PCM1_RX,
-        DMACH_PCM1_TX,
-        DMACH_SPI1_RX,
-        DMACH_SPI1_TX,
-        DMACH_PWM,
-        DMACH_SPDIF,
-        DMACH_I2S0S_TX,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S1_RX,
-        DMACH_I2S1_TX,
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART1_RX,
-        DMACH_UART1_TX,
-        DMACH_UART3_RX,
-        DMACH_UART3_TX,
-        DMACH_SLIMBUS1_RX,
-        DMACH_SLIMBUS1_TX,
-        DMACH_SLIMBUS3_RX,
-        DMACH_SLIMBUS3_TX,
-        DMACH_SLIMBUS5_RX,
-        DMACH_SLIMBUS5_TX,
-        DMACH_SLIMBUS0AUX_RX,
-        DMACH_SLIMBUS0AUX_TX,
-        DMACH_DISP1,
-        DMACH_MIPI_HSI1,
-        DMACH_MIPI_HSI3,
-        DMACH_MIPI_HSI5,
-        DMACH_MIPI_HSI7,
-};
-
-static struct dma_pl330_platdata exynos_pdma1_pdata;
-
-static AMBA_AHB_DEVICE(exynos_pdma1,  "dma-pl330.1", 0x00041330,
-        EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata);
-
-static u8 mdma_peri[] = {
-        DMACH_MTOM_0,
-        DMACH_MTOM_1,
-        DMACH_MTOM_2,
-        DMACH_MTOM_3,
-        DMACH_MTOM_4,
-        DMACH_MTOM_5,
-        DMACH_MTOM_6,
-        DMACH_MTOM_7,
-};
-
-static struct dma_pl330_platdata exynos_mdma1_pdata = {
-        .nr_valid_peri = ARRAY_SIZE(mdma_peri),
-        .peri_id = mdma_peri,
-};
-
-static AMBA_AHB_DEVICE(exynos_mdma1,  "dma-pl330.2", 0x00041330,
-        EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata);
-
-static int __init exynos_dma_init(void)
-{
-        if (of_have_populated_dt())
-                return 0;
-
-        if (soc_is_exynos4210()) {
-                exynos_pdma0_pdata.nr_valid_peri =
-                        ARRAY_SIZE(exynos4210_pdma0_peri);
-                exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
-                exynos_pdma1_pdata.nr_valid_peri =
-                        ARRAY_SIZE(exynos4210_pdma1_peri);
-                exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
-
-                if (samsung_rev() == EXYNOS4210_REV_0)
-                        exynos_mdma1_device.res.start = EXYNOS4_PA_S_MDMA1;
-        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-                exynos_pdma0_pdata.nr_valid_peri =
-                        ARRAY_SIZE(exynos4212_pdma0_peri);
-                exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
-                exynos_pdma1_pdata.nr_valid_peri =
-                        ARRAY_SIZE(exynos4212_pdma1_peri);
-                exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
-        } else if (soc_is_exynos5250()) {
-                exynos_pdma0_pdata.nr_valid_peri =
-                        ARRAY_SIZE(exynos5250_pdma0_peri);
-                exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;
-                exynos_pdma1_pdata.nr_valid_peri =
-                        ARRAY_SIZE(exynos5250_pdma1_peri);
-                exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;
-
-                exynos_pdma0_device.res.start = EXYNOS5_PA_PDMA0;
-                exynos_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K;
-                exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0;
-                exynos_pdma1_device.res.start = EXYNOS5_PA_PDMA1;
-                exynos_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K;
-                exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1;
-                exynos_mdma1_device.res.start = EXYNOS5_PA_MDMA1;
-                exynos_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K;
-                exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1;
-        }
-
-        dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
-        dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
-        dma_cap_set(DMA_PRIVATE, exynos_pdma0_pdata.cap_mask);
-        amba_device_register(&exynos_pdma0_device, &iomem_resource);
-
-        dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
-        dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
-        dma_cap_set(DMA_PRIVATE, exynos_pdma1_pdata.cap_mask);
-        amba_device_register(&exynos_pdma1_device, &iomem_resource);
-
-        dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask);
-        amba_device_register(&exynos_mdma1_device, &iomem_resource);
-
-        return 0;
-}
-arch_initcall(exynos_dma_init);
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index ed11f100d479..932129ef26c6 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -48,20 +48,18 @@ static const struct firmware_ops exynos_firmware_ops = {
 
 void __init exynos_firmware_init(void)
 {
-        if (of_have_populated_dt()) {
-                struct device_node *nd;
-                const __be32 *addr;
+        struct device_node *nd;
+        const __be32 *addr;
 
-                nd = of_find_compatible_node(NULL, NULL,
-                                                "samsung,secure-firmware");
-                if (!nd)
-                        return;
+        nd = of_find_compatible_node(NULL, NULL,
+                                        "samsung,secure-firmware");
+        if (!nd)
+                return;
 
-                addr = of_get_address(nd, 0, NULL, NULL);
-                if (!addr) {
-                        pr_err("%s: No address specified.\n", __func__);
-                        return;
-                }
+        addr = of_get_address(nd, 0, NULL, NULL);
+        if (!addr) {
+                pr_err("%s: No address specified.\n", __func__);
+                return;
         }
 
         pr_info("Running under secure firmware.\n");
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
deleted file mode 100644
index eb24f1eb8e3b..000000000000
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ /dev/null
@@ -1,289 +0,0 @@
-/*
- * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS - GPIO lib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H __FILE__
-
-/* Macro for EXYNOS GPIO numbering */
-
-#define EXYNOS_GPIO_NEXT(__gpio) \
-        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
-
-/* EXYNOS4 GPIO bank sizes */
-
-#define EXYNOS4_GPIO_A0_NR      (8)
-#define EXYNOS4_GPIO_A1_NR      (6)
-#define EXYNOS4_GPIO_B_NR       (8)
-#define EXYNOS4_GPIO_C0_NR      (5)
-#define EXYNOS4_GPIO_C1_NR      (5)
-#define EXYNOS4_GPIO_D0_NR      (4)
-#define EXYNOS4_GPIO_D1_NR      (4)
-#define EXYNOS4_GPIO_E0_NR      (5)
-#define EXYNOS4_GPIO_E1_NR      (8)
-#define EXYNOS4_GPIO_E2_NR      (6)
-#define EXYNOS4_GPIO_E3_NR      (8)
-#define EXYNOS4_GPIO_E4_NR      (8)
-#define EXYNOS4_GPIO_F0_NR      (8)
-#define EXYNOS4_GPIO_F1_NR      (8)
-#define EXYNOS4_GPIO_F2_NR      (8)
-#define EXYNOS4_GPIO_F3_NR      (6)
-#define EXYNOS4_GPIO_J0_NR      (8)
-#define EXYNOS4_GPIO_J1_NR      (5)
-#define EXYNOS4_GPIO_K0_NR      (7)
-#define EXYNOS4_GPIO_K1_NR      (7)
-#define EXYNOS4_GPIO_K2_NR      (7)
-#define EXYNOS4_GPIO_K3_NR      (7)
-#define EXYNOS4_GPIO_L0_NR      (8)
-#define EXYNOS4_GPIO_L1_NR      (3)
-#define EXYNOS4_GPIO_L2_NR      (8)
-#define EXYNOS4_GPIO_X0_NR      (8)
-#define EXYNOS4_GPIO_X1_NR      (8)
-#define EXYNOS4_GPIO_X2_NR      (8)
-#define EXYNOS4_GPIO_X3_NR      (8)
-#define EXYNOS4_GPIO_Y0_NR      (6)
-#define EXYNOS4_GPIO_Y1_NR      (4)
-#define EXYNOS4_GPIO_Y2_NR      (6)
-#define EXYNOS4_GPIO_Y3_NR      (8)
-#define EXYNOS4_GPIO_Y4_NR      (8)
-#define EXYNOS4_GPIO_Y5_NR      (8)
-#define EXYNOS4_GPIO_Y6_NR      (8)
-#define EXYNOS4_GPIO_Z_NR       (7)
-
-/* EXYNOS4 GPIO bank numbers */
-
-enum exynos4_gpio_number {
-        EXYNOS4_GPIO_A0_START   = 0,
-        EXYNOS4_GPIO_A1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A0),
-        EXYNOS4_GPIO_B_START    = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A1),
-        EXYNOS4_GPIO_C0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_B),
-        EXYNOS4_GPIO_C1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
-        EXYNOS4_GPIO_D0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
-        EXYNOS4_GPIO_D1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
-        EXYNOS4_GPIO_E0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
-        EXYNOS4_GPIO_E1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E0),
-        EXYNOS4_GPIO_E2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E1),
-        EXYNOS4_GPIO_E3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E2),
-        EXYNOS4_GPIO_E4_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E3),
-        EXYNOS4_GPIO_F0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4),
-        EXYNOS4_GPIO_F1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
-        EXYNOS4_GPIO_F2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
-        EXYNOS4_GPIO_F3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
-        EXYNOS4_GPIO_J0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F3),
-        EXYNOS4_GPIO_J1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J0),
-        EXYNOS4_GPIO_K0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J1),
-        EXYNOS4_GPIO_K1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K0),
-        EXYNOS4_GPIO_K2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K1),
-        EXYNOS4_GPIO_K3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K2),
-        EXYNOS4_GPIO_L0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K3),
-        EXYNOS4_GPIO_L1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L0),
-        EXYNOS4_GPIO_L2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L1),
-        EXYNOS4_GPIO_X0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L2),
-        EXYNOS4_GPIO_X1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X0),
-        EXYNOS4_GPIO_X2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X1),
-        EXYNOS4_GPIO_X3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X2),
-        EXYNOS4_GPIO_Y0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X3),
-        EXYNOS4_GPIO_Y1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y0),
-        EXYNOS4_GPIO_Y2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y1),
-        EXYNOS4_GPIO_Y3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y2),
-        EXYNOS4_GPIO_Y4_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y3),
-        EXYNOS4_GPIO_Y5_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y4),
-        EXYNOS4_GPIO_Y6_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y5),
-        EXYNOS4_GPIO_Z_START    = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y6),
-};
-
-/* EXYNOS4 GPIO number definitions */
-
-#define EXYNOS4_GPA0(_nr)       (EXYNOS4_GPIO_A0_START + (_nr))
-#define EXYNOS4_GPA1(_nr)       (EXYNOS4_GPIO_A1_START + (_nr))
-#define EXYNOS4_GPB(_nr)        (EXYNOS4_GPIO_B_START + (_nr))
-#define EXYNOS4_GPC0(_nr)       (EXYNOS4_GPIO_C0_START + (_nr))
-#define EXYNOS4_GPC1(_nr)       (EXYNOS4_GPIO_C1_START + (_nr))
-#define EXYNOS4_GPD0(_nr)       (EXYNOS4_GPIO_D0_START + (_nr))
-#define EXYNOS4_GPD1(_nr)       (EXYNOS4_GPIO_D1_START + (_nr))
-#define EXYNOS4_GPE0(_nr)       (EXYNOS4_GPIO_E0_START + (_nr))
-#define EXYNOS4_GPE1(_nr)       (EXYNOS4_GPIO_E1_START + (_nr))
-#define EXYNOS4_GPE2(_nr)       (EXYNOS4_GPIO_E2_START + (_nr))
-#define EXYNOS4_GPE3(_nr)       (EXYNOS4_GPIO_E3_START + (_nr))
-#define EXYNOS4_GPE4(_nr)       (EXYNOS4_GPIO_E4_START + (_nr))
-#define EXYNOS4_GPF0(_nr)       (EXYNOS4_GPIO_F0_START + (_nr))
-#define EXYNOS4_GPF1(_nr)       (EXYNOS4_GPIO_F1_START + (_nr))
-#define EXYNOS4_GPF2(_nr)       (EXYNOS4_GPIO_F2_START + (_nr))
-#define EXYNOS4_GPF3(_nr)       (EXYNOS4_GPIO_F3_START + (_nr))
-#define EXYNOS4_GPJ0(_nr)       (EXYNOS4_GPIO_J0_START + (_nr))
-#define EXYNOS4_GPJ1(_nr)       (EXYNOS4_GPIO_J1_START + (_nr))
-#define EXYNOS4_GPK0(_nr)       (EXYNOS4_GPIO_K0_START + (_nr))
-#define EXYNOS4_GPK1(_nr)       (EXYNOS4_GPIO_K1_START + (_nr))
-#define EXYNOS4_GPK2(_nr)       (EXYNOS4_GPIO_K2_START + (_nr))
-#define EXYNOS4_GPK3(_nr)       (EXYNOS4_GPIO_K3_START + (_nr))
-#define EXYNOS4_GPL0(_nr)       (EXYNOS4_GPIO_L0_START + (_nr))
-#define EXYNOS4_GPL1(_nr)       (EXYNOS4_GPIO_L1_START + (_nr))
-#define EXYNOS4_GPL2(_nr)       (EXYNOS4_GPIO_L2_START + (_nr))
-#define EXYNOS4_GPX0(_nr)       (EXYNOS4_GPIO_X0_START + (_nr))
-#define EXYNOS4_GPX1(_nr)       (EXYNOS4_GPIO_X1_START + (_nr))
-#define EXYNOS4_GPX2(_nr)       (EXYNOS4_GPIO_X2_START + (_nr))
-#define EXYNOS4_GPX3(_nr)       (EXYNOS4_GPIO_X3_START + (_nr))
-#define EXYNOS4_GPY0(_nr)       (EXYNOS4_GPIO_Y0_START + (_nr))
-#define EXYNOS4_GPY1(_nr)       (EXYNOS4_GPIO_Y1_START + (_nr))
-#define EXYNOS4_GPY2(_nr)       (EXYNOS4_GPIO_Y2_START + (_nr))
-#define EXYNOS4_GPY3(_nr)       (EXYNOS4_GPIO_Y3_START + (_nr))
-#define EXYNOS4_GPY4(_nr)       (EXYNOS4_GPIO_Y4_START + (_nr))
-#define EXYNOS4_GPY5(_nr)       (EXYNOS4_GPIO_Y5_START + (_nr))
-#define EXYNOS4_GPY6(_nr)       (EXYNOS4_GPIO_Y6_START + (_nr))
-#define EXYNOS4_GPZ(_nr)        (EXYNOS4_GPIO_Z_START + (_nr))
-
-/* the end of the EXYNOS4 specific gpios */
-
-#define EXYNOS4_GPIO_END        (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
-
-/* EXYNOS5 GPIO bank sizes */
-
-#define EXYNOS5_GPIO_A0_NR      (8)
-#define EXYNOS5_GPIO_A1_NR      (6)
-#define EXYNOS5_GPIO_A2_NR      (8)
-#define EXYNOS5_GPIO_B0_NR      (5)
-#define EXYNOS5_GPIO_B1_NR      (5)
-#define EXYNOS5_GPIO_B2_NR      (4)
-#define EXYNOS5_GPIO_B3_NR      (4)
-#define EXYNOS5_GPIO_C0_NR      (7)
-#define EXYNOS5_GPIO_C1_NR      (4)
-#define EXYNOS5_GPIO_C2_NR      (7)
-#define EXYNOS5_GPIO_C3_NR      (7)
-#define EXYNOS5_GPIO_C4_NR      (7)
-#define EXYNOS5_GPIO_D0_NR      (4)
-#define EXYNOS5_GPIO_D1_NR      (8)
-#define EXYNOS5_GPIO_Y0_NR      (6)
-#define EXYNOS5_GPIO_Y1_NR      (4)
-#define EXYNOS5_GPIO_Y2_NR      (6)
-#define EXYNOS5_GPIO_Y3_NR      (8)
-#define EXYNOS5_GPIO_Y4_NR      (8)
-#define EXYNOS5_GPIO_Y5_NR      (8)
-#define EXYNOS5_GPIO_Y6_NR      (8)
-#define EXYNOS5_GPIO_X0_NR      (8)
-#define EXYNOS5_GPIO_X1_NR      (8)
-#define EXYNOS5_GPIO_X2_NR      (8)
-#define EXYNOS5_GPIO_X3_NR      (8)
-#define EXYNOS5_GPIO_E0_NR      (8)
-#define EXYNOS5_GPIO_E1_NR      (2)
-#define EXYNOS5_GPIO_F0_NR      (4)
-#define EXYNOS5_GPIO_F1_NR      (4)
-#define EXYNOS5_GPIO_G0_NR      (8)
-#define EXYNOS5_GPIO_G1_NR      (8)
-#define EXYNOS5_GPIO_G2_NR      (2)
-#define EXYNOS5_GPIO_H0_NR      (4)
-#define EXYNOS5_GPIO_H1_NR      (8)
-#define EXYNOS5_GPIO_V0_NR      (8)
-#define EXYNOS5_GPIO_V1_NR      (8)
-#define EXYNOS5_GPIO_V2_NR      (8)
-#define EXYNOS5_GPIO_V3_NR      (8)
-#define EXYNOS5_GPIO_V4_NR      (2)
-#define EXYNOS5_GPIO_Z_NR       (7)
-
-/* EXYNOS5 GPIO bank numbers */
-
-enum exynos5_gpio_number {
-        EXYNOS5_GPIO_A0_START           = 0,
-        EXYNOS5_GPIO_A1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A0),
-        EXYNOS5_GPIO_A2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A1),
-        EXYNOS5_GPIO_B0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A2),
-        EXYNOS5_GPIO_B1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B0),
-        EXYNOS5_GPIO_B2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B1),
-        EXYNOS5_GPIO_B3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B2),
-        EXYNOS5_GPIO_C0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B3),
-        EXYNOS5_GPIO_C1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
-        EXYNOS5_GPIO_C2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
-        EXYNOS5_GPIO_C3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
-        EXYNOS5_GPIO_C4_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
-        EXYNOS5_GPIO_D0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
-        EXYNOS5_GPIO_D1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
-        EXYNOS5_GPIO_Y0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
-        EXYNOS5_GPIO_Y1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
-        EXYNOS5_GPIO_Y2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y1),
-        EXYNOS5_GPIO_Y3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y2),
-        EXYNOS5_GPIO_Y4_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y3),
-        EXYNOS5_GPIO_Y5_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y4),
-        EXYNOS5_GPIO_Y6_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y5),
-        EXYNOS5_GPIO_X0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y6),
-        EXYNOS5_GPIO_X1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X0),
-        EXYNOS5_GPIO_X2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X1),
-        EXYNOS5_GPIO_X3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X2),
-        EXYNOS5_GPIO_E0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X3),
-        EXYNOS5_GPIO_E1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E0),
-        EXYNOS5_GPIO_F0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E1),
-        EXYNOS5_GPIO_F1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F0),
-        EXYNOS5_GPIO_G0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F1),
-        EXYNOS5_GPIO_G1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G0),
-        EXYNOS5_GPIO_G2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G1),
-        EXYNOS5_GPIO_H0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G2),
-        EXYNOS5_GPIO_H1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H0),
-        EXYNOS5_GPIO_V0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H1),
-        EXYNOS5_GPIO_V1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V0),
-        EXYNOS5_GPIO_V2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V1),
-        EXYNOS5_GPIO_V3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V2),
-        EXYNOS5_GPIO_V4_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V3),
-        EXYNOS5_GPIO_Z_START            = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V4),
-};
-
-/* EXYNOS5 GPIO number definitions */
-
-#define EXYNOS5_GPA0(_nr)       (EXYNOS5_GPIO_A0_START + (_nr))
-#define EXYNOS5_GPA1(_nr)       (EXYNOS5_GPIO_A1_START + (_nr))
-#define EXYNOS5_GPA2(_nr)       (EXYNOS5_GPIO_A2_START + (_nr))
-#define EXYNOS5_GPB0(_nr)       (EXYNOS5_GPIO_B0_START + (_nr))
-#define EXYNOS5_GPB1(_nr)       (EXYNOS5_GPIO_B1_START + (_nr))
-#define EXYNOS5_GPB2(_nr)       (EXYNOS5_GPIO_B2_START + (_nr))
-#define EXYNOS5_GPB3(_nr)       (EXYNOS5_GPIO_B3_START + (_nr))
-#define EXYNOS5_GPC0(_nr)       (EXYNOS5_GPIO_C0_START + (_nr))
-#define EXYNOS5_GPC1(_nr)       (EXYNOS5_GPIO_C1_START + (_nr))
-#define EXYNOS5_GPC2(_nr)       (EXYNOS5_GPIO_C2_START + (_nr))
-#define EXYNOS5_GPC3(_nr)       (EXYNOS5_GPIO_C3_START + (_nr))
-#define EXYNOS5_GPC4(_nr)       (EXYNOS5_GPIO_C4_START + (_nr))
-#define EXYNOS5_GPD0(_nr)       (EXYNOS5_GPIO_D0_START + (_nr))
-#define EXYNOS5_GPD1(_nr)       (EXYNOS5_GPIO_D1_START + (_nr))
-#define EXYNOS5_GPY0(_nr)       (EXYNOS5_GPIO_Y0_START + (_nr))
-#define EXYNOS5_GPY1(_nr)       (EXYNOS5_GPIO_Y1_START + (_nr))
-#define EXYNOS5_GPY2(_nr)       (EXYNOS5_GPIO_Y2_START + (_nr))
-#define EXYNOS5_GPY3(_nr)       (EXYNOS5_GPIO_Y3_START + (_nr))
-#define EXYNOS5_GPY4(_nr)       (EXYNOS5_GPIO_Y4_START + (_nr))
-#define EXYNOS5_GPY5(_nr)       (EXYNOS5_GPIO_Y5_START + (_nr))
-#define EXYNOS5_GPY6(_nr)       (EXYNOS5_GPIO_Y6_START + (_nr))
-#define EXYNOS5_GPX0(_nr)       (EXYNOS5_GPIO_X0_START + (_nr))
-#define EXYNOS5_GPX1(_nr)       (EXYNOS5_GPIO_X1_START + (_nr))
-#define EXYNOS5_GPX2(_nr)       (EXYNOS5_GPIO_X2_START + (_nr))
-#define EXYNOS5_GPX3(_nr)       (EXYNOS5_GPIO_X3_START + (_nr))
-#define EXYNOS5_GPE0(_nr)       (EXYNOS5_GPIO_E0_START + (_nr))
-#define EXYNOS5_GPE1(_nr)       (EXYNOS5_GPIO_E1_START + (_nr))
-#define EXYNOS5_GPF0(_nr)       (EXYNOS5_GPIO_F0_START + (_nr))
-#define EXYNOS5_GPF1(_nr)       (EXYNOS5_GPIO_F1_START + (_nr))
-#define EXYNOS5_GPG0(_nr)       (EXYNOS5_GPIO_G0_START + (_nr))
-#define EXYNOS5_GPG1(_nr)       (EXYNOS5_GPIO_G1_START + (_nr))
-#define EXYNOS5_GPG2(_nr)       (EXYNOS5_GPIO_G2_START + (_nr))
-#define EXYNOS5_GPH0(_nr)       (EXYNOS5_GPIO_H0_START + (_nr))
-#define EXYNOS5_GPH1(_nr)       (EXYNOS5_GPIO_H1_START + (_nr))
-#define EXYNOS5_GPV0(_nr)       (EXYNOS5_GPIO_V0_START + (_nr))
-#define EXYNOS5_GPV1(_nr)       (EXYNOS5_GPIO_V1_START + (_nr))
-#define EXYNOS5_GPV2(_nr)       (EXYNOS5_GPIO_V2_START + (_nr))
-#define EXYNOS5_GPV3(_nr)       (EXYNOS5_GPIO_V3_START + (_nr))
-#define EXYNOS5_GPV4(_nr)       (EXYNOS5_GPIO_V4_START + (_nr))
-#define EXYNOS5_GPZ(_nr)        (EXYNOS5_GPIO_Z_START + (_nr))
-
-/* the end of the EXYNOS5 specific gpios */
-
-#define EXYNOS5_GPIO_END        (EXYNOS5_GPZ(EXYNOS5_GPIO_Z_NR) + 1)
-
-/* actually, EXYNOS5_GPIO_END is bigger than EXYNOS4 */
-
-#define S3C_GPIO_END            (EXYNOS5_GPIO_END)
-
-/* define the number of gpios */
-
-#define ARCH_NR_GPIOS           (CONFIG_SAMSUNG_GPIO_EXTRA + S3C_GPIO_END)
-
-#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
deleted file mode 100644
index c72f59d91fce..000000000000
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ /dev/null
@@ -1,476 +0,0 @@
-/*
- * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS - IRQ definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H __FILE__
-
-#include <plat/irqs.h>
-
-/* PPI: Private Peripheral Interrupt */
-
-#define IRQ_PPI(x)                      (x + 16)
-
-/* SPI: Shared Peripheral Interrupt */
-
-#define IRQ_SPI(x)                      (x + 32)
-
-/* COMBINER */
-
-#define MAX_IRQ_IN_COMBINER             8
-#define COMBINER_GROUP(x)               ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
-#define COMBINER_IRQ(x, y)              (COMBINER_GROUP(x) + y)
-
-/* For EXYNOS4 and EXYNOS5 */
-
-#define EXYNOS_IRQ_EINT16_31            IRQ_SPI(32)
-
-/* For EXYNOS4 SoCs */
-
-#define EXYNOS4_IRQ_EINT0               IRQ_SPI(16)
-#define EXYNOS4_IRQ_EINT1               IRQ_SPI(17)
-#define EXYNOS4_IRQ_EINT2               IRQ_SPI(18)
-#define EXYNOS4_IRQ_EINT3               IRQ_SPI(19)
-#define EXYNOS4_IRQ_EINT4               IRQ_SPI(20)
-#define EXYNOS4_IRQ_EINT5               IRQ_SPI(21)
-#define EXYNOS4_IRQ_EINT6               IRQ_SPI(22)
-#define EXYNOS4_IRQ_EINT7               IRQ_SPI(23)
-#define EXYNOS4_IRQ_EINT8               IRQ_SPI(24)
-#define EXYNOS4_IRQ_EINT9               IRQ_SPI(25)
-#define EXYNOS4_IRQ_EINT10              IRQ_SPI(26)
-#define EXYNOS4_IRQ_EINT11              IRQ_SPI(27)
-#define EXYNOS4_IRQ_EINT12              IRQ_SPI(28)
-#define EXYNOS4_IRQ_EINT13              IRQ_SPI(29)
-#define EXYNOS4_IRQ_EINT14              IRQ_SPI(30)
-#define EXYNOS4_IRQ_EINT15              IRQ_SPI(31)
-
-#define EXYNOS4_IRQ_MDMA0               IRQ_SPI(33)
-#define EXYNOS4_IRQ_MDMA1               IRQ_SPI(34)
-#define EXYNOS4_IRQ_PDMA0               IRQ_SPI(35)
-#define EXYNOS4_IRQ_PDMA1               IRQ_SPI(36)
-#define EXYNOS4_IRQ_TIMER0_VIC          IRQ_SPI(37)
-#define EXYNOS4_IRQ_TIMER1_VIC          IRQ_SPI(38)
-#define EXYNOS4_IRQ_TIMER2_VIC          IRQ_SPI(39)
-#define EXYNOS4_IRQ_TIMER3_VIC          IRQ_SPI(40)
-#define EXYNOS4_IRQ_TIMER4_VIC          IRQ_SPI(41)
-#define EXYNOS4_IRQ_MCT_L0              IRQ_SPI(42)
-#define EXYNOS4_IRQ_WDT                 IRQ_SPI(43)
-#define EXYNOS4_IRQ_RTC_ALARM           IRQ_SPI(44)
-#define EXYNOS4_IRQ_RTC_TIC             IRQ_SPI(45)
-#define EXYNOS4_IRQ_GPIO_XB             IRQ_SPI(46)
-#define EXYNOS4_IRQ_GPIO_XA             IRQ_SPI(47)
-#define EXYNOS4_IRQ_MCT_L1              IRQ_SPI(48)
-
-#define EXYNOS4_IRQ_UART0               IRQ_SPI(52)
-#define EXYNOS4_IRQ_UART1               IRQ_SPI(53)
-#define EXYNOS4_IRQ_UART2               IRQ_SPI(54)
-#define EXYNOS4_IRQ_UART3               IRQ_SPI(55)
-#define EXYNOS4_IRQ_UART4               IRQ_SPI(56)
-#define EXYNOS4_IRQ_MCT_G0              IRQ_SPI(57)
-#define EXYNOS4_IRQ_IIC                 IRQ_SPI(58)
-#define EXYNOS4_IRQ_IIC1                IRQ_SPI(59)
-#define EXYNOS4_IRQ_IIC2                IRQ_SPI(60)
-#define EXYNOS4_IRQ_IIC3                IRQ_SPI(61)
-#define EXYNOS4_IRQ_IIC4                IRQ_SPI(62)
-#define EXYNOS4_IRQ_IIC5                IRQ_SPI(63)
-#define EXYNOS4_IRQ_IIC6                IRQ_SPI(64)
-#define EXYNOS4_IRQ_IIC7                IRQ_SPI(65)
-#define EXYNOS4_IRQ_SPI0                IRQ_SPI(66)
-#define EXYNOS4_IRQ_SPI1                IRQ_SPI(67)
-#define EXYNOS4_IRQ_SPI2                IRQ_SPI(68)
-
-#define EXYNOS4_IRQ_USB_HOST            IRQ_SPI(70)
-#define EXYNOS4_IRQ_USB_HSOTG           IRQ_SPI(71)
-#define EXYNOS4_IRQ_MODEM_IF            IRQ_SPI(72)
-#define EXYNOS4_IRQ_HSMMC0              IRQ_SPI(73)
-#define EXYNOS4_IRQ_HSMMC1              IRQ_SPI(74)
-#define EXYNOS4_IRQ_HSMMC2              IRQ_SPI(75)
-#define EXYNOS4_IRQ_HSMMC3              IRQ_SPI(76)
-#define EXYNOS4_IRQ_DWMCI               IRQ_SPI(77)
-
-#define EXYNOS4_IRQ_MIPI_CSIS0          IRQ_SPI(78)
-#define EXYNOS4_IRQ_MIPI_CSIS1          IRQ_SPI(80)
-
-#define EXYNOS4_IRQ_ONENAND_AUDI        IRQ_SPI(82)
-#define EXYNOS4_IRQ_ROTATOR             IRQ_SPI(83)
-#define EXYNOS4_IRQ_FIMC0               IRQ_SPI(84)
-#define EXYNOS4_IRQ_FIMC1               IRQ_SPI(85)
-#define EXYNOS4_IRQ_FIMC2               IRQ_SPI(86)
-#define EXYNOS4_IRQ_FIMC3               IRQ_SPI(87)
-#define EXYNOS4_IRQ_JPEG                IRQ_SPI(88)
-#define EXYNOS4_IRQ_2D                  IRQ_SPI(89)
-#define EXYNOS4_IRQ_PCIE                IRQ_SPI(90)
-
-#define EXYNOS4_IRQ_MIXER               IRQ_SPI(91)
-#define EXYNOS4_IRQ_HDMI                IRQ_SPI(92)
-#define EXYNOS4_IRQ_IIC_HDMIPHY         IRQ_SPI(93)
-#define EXYNOS4_IRQ_MFC                 IRQ_SPI(94)
-#define EXYNOS4_IRQ_SDO                 IRQ_SPI(95)
-
-#define EXYNOS4_IRQ_AUDIO_SS            IRQ_SPI(96)
-#define EXYNOS4_IRQ_I2S0                IRQ_SPI(97)
-#define EXYNOS4_IRQ_I2S1                IRQ_SPI(98)
-#define EXYNOS4_IRQ_I2S2                IRQ_SPI(99)
-#define EXYNOS4_IRQ_AC97                IRQ_SPI(100)
-
-#define EXYNOS4_IRQ_SPDIF               IRQ_SPI(104)
-#define EXYNOS4_IRQ_ADC0                IRQ_SPI(105)
-#define EXYNOS4_IRQ_PEN0                IRQ_SPI(106)
-#define EXYNOS4_IRQ_ADC1                IRQ_SPI(107)
-#define EXYNOS4_IRQ_PEN1                IRQ_SPI(108)
-#define EXYNOS4_IRQ_KEYPAD              IRQ_SPI(109)
-#define EXYNOS4_IRQ_POWER_PMU           IRQ_SPI(110)
-#define EXYNOS4_IRQ_GPS                 IRQ_SPI(111)
-#define EXYNOS4_IRQ_INTFEEDCTRL_SSS     IRQ_SPI(112)
-#define EXYNOS4_IRQ_SLIMBUS             IRQ_SPI(113)
-
-#define EXYNOS4_IRQ_TSI                 IRQ_SPI(115)
-#define EXYNOS4_IRQ_SATA                IRQ_SPI(116)
-
-#define EXYNOS4_IRQ_PMU                 COMBINER_IRQ(2, 2)
-#define EXYNOS4_IRQ_PMU_CPU1            COMBINER_IRQ(3, 2)
-#define EXYNOS4_IRQ_PMU_CPU2            COMBINER_IRQ(18, 2)
-#define EXYNOS4_IRQ_PMU_CPU3            COMBINER_IRQ(19, 2)
-
-#define EXYNOS4_IRQ_TMU_TRIG0           COMBINER_IRQ(2, 4)
-#define EXYNOS4_IRQ_TMU_TRIG1           COMBINER_IRQ(3, 4)
-
-#define EXYNOS4_IRQ_SYSMMU_MDMA0_0      COMBINER_IRQ(4, 0)
-#define EXYNOS4_IRQ_SYSMMU_SSS_0        COMBINER_IRQ(4, 1)
-#define EXYNOS4_IRQ_SYSMMU_FIMC0_0      COMBINER_IRQ(4, 2)
-#define EXYNOS4_IRQ_SYSMMU_FIMC1_0      COMBINER_IRQ(4, 3)
-#define EXYNOS4_IRQ_SYSMMU_FIMC2_0      COMBINER_IRQ(4, 4)
-#define EXYNOS4_IRQ_SYSMMU_FIMC3_0      COMBINER_IRQ(4, 5)
-#define EXYNOS4_IRQ_SYSMMU_JPEG_0       COMBINER_IRQ(4, 6)
-#define EXYNOS4_IRQ_SYSMMU_2D_0         COMBINER_IRQ(4, 7)
-
-#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0    COMBINER_IRQ(5, 0)
-#define EXYNOS4_IRQ_SYSMMU_MDMA1_0      COMBINER_IRQ(5, 1)
-#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0    COMBINER_IRQ(5, 2)
-#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0    COMBINER_IRQ(5, 3)
-#define EXYNOS4_IRQ_SYSMMU_TV_M0_0      COMBINER_IRQ(5, 4)
-#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0     COMBINER_IRQ(5, 5)
-#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0     COMBINER_IRQ(5, 6)
-#define EXYNOS4_IRQ_SYSMMU_PCIE_0       COMBINER_IRQ(5, 7)
-
-#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0 COMBINER_IRQ(16, 0)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0 COMBINER_IRQ(16, 1)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0   COMBINER_IRQ(16, 2)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0   COMBINER_IRQ(16, 3)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0    COMBINER_IRQ(16, 4)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0    COMBINER_IRQ(16, 5)
-
-#define EXYNOS4_IRQ_FIMD0_FIFO          COMBINER_IRQ(11, 0)
-#define EXYNOS4_IRQ_FIMD0_VSYNC         COMBINER_IRQ(11, 1)
-#define EXYNOS4_IRQ_FIMD0_SYSTEM        COMBINER_IRQ(11, 2)
-
-#define EXYNOS4210_MAX_COMBINER_NR      16
-#define EXYNOS4212_MAX_COMBINER_NR      18
-#define EXYNOS4412_MAX_COMBINER_NR      20
-#define EXYNOS4_MAX_COMBINER_NR         EXYNOS4412_MAX_COMBINER_NR
-
-#define EXYNOS4_IRQ_GPIO1_NR_GROUPS     16
-#define EXYNOS4_IRQ_GPIO2_NR_GROUPS     9
-
-/*
- * For Compatibility:
- * the default is for EXYNOS4, and
- * for exynos5, should be re-mapped at function
- */
-
-#define IRQ_TIMER0_VIC                  EXYNOS4_IRQ_TIMER0_VIC
-#define IRQ_TIMER1_VIC                  EXYNOS4_IRQ_TIMER1_VIC
-#define IRQ_TIMER2_VIC                  EXYNOS4_IRQ_TIMER2_VIC
-#define IRQ_TIMER3_VIC                  EXYNOS4_IRQ_TIMER3_VIC
-#define IRQ_TIMER4_VIC                  EXYNOS4_IRQ_TIMER4_VIC
-
-#define IRQ_WDT                         EXYNOS4_IRQ_WDT
-#define IRQ_RTC_ALARM                   EXYNOS4_IRQ_RTC_ALARM
-#define IRQ_RTC_TIC                     EXYNOS4_IRQ_RTC_TIC
-#define IRQ_GPIO_XB                     EXYNOS4_IRQ_GPIO_XB
-#define IRQ_GPIO_XA                     EXYNOS4_IRQ_GPIO_XA
-
-#define IRQ_IIC                         EXYNOS4_IRQ_IIC
-#define IRQ_IIC1                        EXYNOS4_IRQ_IIC1
-#define IRQ_IIC3                        EXYNOS4_IRQ_IIC3
-#define IRQ_IIC5                        EXYNOS4_IRQ_IIC5
-#define IRQ_IIC6                        EXYNOS4_IRQ_IIC6
-#define IRQ_IIC7                        EXYNOS4_IRQ_IIC7
-
-#define IRQ_SPI0                        EXYNOS4_IRQ_SPI0
-#define IRQ_SPI1                        EXYNOS4_IRQ_SPI1
-#define IRQ_SPI2                        EXYNOS4_IRQ_SPI2
-
-#define IRQ_USB_HOST                    EXYNOS4_IRQ_USB_HOST
-#define IRQ_OTG                         EXYNOS4_IRQ_USB_HSOTG
-
-#define IRQ_HSMMC0                      EXYNOS4_IRQ_HSMMC0
-#define IRQ_HSMMC1                      EXYNOS4_IRQ_HSMMC1
-#define IRQ_HSMMC2                      EXYNOS4_IRQ_HSMMC2
-#define IRQ_HSMMC3                      EXYNOS4_IRQ_HSMMC3
-
-#define IRQ_MIPI_CSIS0                  EXYNOS4_IRQ_MIPI_CSIS0
-
-#define IRQ_ONENAND_AUDI                EXYNOS4_IRQ_ONENAND_AUDI
-
-#define IRQ_FIMC0                       EXYNOS4_IRQ_FIMC0
-#define IRQ_FIMC1                       EXYNOS4_IRQ_FIMC1
-#define IRQ_FIMC2                       EXYNOS4_IRQ_FIMC2
-#define IRQ_FIMC3                       EXYNOS4_IRQ_FIMC3
-#define IRQ_JPEG                        EXYNOS4_IRQ_JPEG
-#define IRQ_2D                          EXYNOS4_IRQ_2D
-
-#define IRQ_MIXER                       EXYNOS4_IRQ_MIXER
-#define IRQ_HDMI                        EXYNOS4_IRQ_HDMI
-#define IRQ_IIC_HDMIPHY                 EXYNOS4_IRQ_IIC_HDMIPHY
-#define IRQ_MFC                         EXYNOS4_IRQ_MFC
-#define IRQ_SDO                         EXYNOS4_IRQ_SDO
-
-#define IRQ_I2S0                        EXYNOS4_IRQ_I2S0
-
-#define IRQ_ADC                         EXYNOS4_IRQ_ADC0
-#define IRQ_TC                          EXYNOS4_IRQ_PEN0
-
-#define IRQ_KEYPAD                      EXYNOS4_IRQ_KEYPAD
-
-#define IRQ_FIMD0_FIFO                  EXYNOS4_IRQ_FIMD0_FIFO
-#define IRQ_FIMD0_VSYNC                 EXYNOS4_IRQ_FIMD0_VSYNC
-#define IRQ_FIMD0_SYSTEM                EXYNOS4_IRQ_FIMD0_SYSTEM
-
-#define IRQ_GPIO1_NR_GROUPS             EXYNOS4_IRQ_GPIO1_NR_GROUPS
-#define IRQ_GPIO2_NR_GROUPS             EXYNOS4_IRQ_GPIO2_NR_GROUPS
-
-/* For EXYNOS5 SoCs */
-
-#define EXYNOS5_IRQ_MDMA0               IRQ_SPI(33)
-#define EXYNOS5_IRQ_PDMA0               IRQ_SPI(34)
-#define EXYNOS5_IRQ_PDMA1               IRQ_SPI(35)
-#define EXYNOS5_IRQ_TIMER0_VIC          IRQ_SPI(36)
-#define EXYNOS5_IRQ_TIMER1_VIC          IRQ_SPI(37)
-#define EXYNOS5_IRQ_TIMER2_VIC          IRQ_SPI(38)
-#define EXYNOS5_IRQ_TIMER3_VIC          IRQ_SPI(39)
-#define EXYNOS5_IRQ_TIMER4_VIC          IRQ_SPI(40)
-#define EXYNOS5_IRQ_RTIC                IRQ_SPI(41)
-#define EXYNOS5_IRQ_WDT                 IRQ_SPI(42)
-#define EXYNOS5_IRQ_RTC_ALARM           IRQ_SPI(43)
-#define EXYNOS5_IRQ_RTC_TIC             IRQ_SPI(44)
-#define EXYNOS5_IRQ_GPIO_XB             IRQ_SPI(45)
-#define EXYNOS5_IRQ_GPIO_XA             IRQ_SPI(46)
-#define EXYNOS5_IRQ_GPIO                IRQ_SPI(47)
-#define EXYNOS5_IRQ_IEM_IEC             IRQ_SPI(48)
-#define EXYNOS5_IRQ_IEM_APC             IRQ_SPI(49)
-#define EXYNOS5_IRQ_GPIO_C2C            IRQ_SPI(50)
-#define EXYNOS5_IRQ_IIC                 IRQ_SPI(56)
-#define EXYNOS5_IRQ_IIC1                IRQ_SPI(57)
-#define EXYNOS5_IRQ_IIC2                IRQ_SPI(58)
-#define EXYNOS5_IRQ_IIC3                IRQ_SPI(59)
-#define EXYNOS5_IRQ_IIC4                IRQ_SPI(60)
-#define EXYNOS5_IRQ_IIC5                IRQ_SPI(61)
-#define EXYNOS5_IRQ_IIC6                IRQ_SPI(62)
-#define EXYNOS5_IRQ_IIC7                IRQ_SPI(63)
-#define EXYNOS5_IRQ_IIC_HDMIPHY         IRQ_SPI(64)
-#define EXYNOS5_IRQ_TMU                 IRQ_SPI(65)
-#define EXYNOS5_IRQ_FIQ_0               IRQ_SPI(66)
-#define EXYNOS5_IRQ_FIQ_1               IRQ_SPI(67)
-#define EXYNOS5_IRQ_SPI0                IRQ_SPI(68)
-#define EXYNOS5_IRQ_SPI1                IRQ_SPI(69)
-#define EXYNOS5_IRQ_SPI2                IRQ_SPI(70)
-#define EXYNOS5_IRQ_USB_HOST            IRQ_SPI(71)
-#define EXYNOS5_IRQ_USB3_DRD            IRQ_SPI(72)
-#define EXYNOS5_IRQ_MIPI_HSI            IRQ_SPI(73)
-#define EXYNOS5_IRQ_USB_HSOTG           IRQ_SPI(74)
-#define EXYNOS5_IRQ_HSMMC0              IRQ_SPI(75)
-#define EXYNOS5_IRQ_HSMMC1              IRQ_SPI(76)
-#define EXYNOS5_IRQ_HSMMC2              IRQ_SPI(77)
-#define EXYNOS5_IRQ_HSMMC3              IRQ_SPI(78)
-#define EXYNOS5_IRQ_MIPICSI0            IRQ_SPI(79)
-#define EXYNOS5_IRQ_MIPICSI1            IRQ_SPI(80)
-#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT   IRQ_SPI(81)
-#define EXYNOS5_IRQ_MIPIDSI0            IRQ_SPI(82)
-#define EXYNOS5_IRQ_WDT_IOP             IRQ_SPI(83)
-#define EXYNOS5_IRQ_ROTATOR             IRQ_SPI(84)
-#define EXYNOS5_IRQ_GSC0                IRQ_SPI(85)
-#define EXYNOS5_IRQ_GSC1                IRQ_SPI(86)
-#define EXYNOS5_IRQ_GSC2                IRQ_SPI(87)
-#define EXYNOS5_IRQ_GSC3                IRQ_SPI(88)
-#define EXYNOS5_IRQ_JPEG                IRQ_SPI(89)
-#define EXYNOS5_IRQ_EFNFCON_DMA         IRQ_SPI(90)
-#define EXYNOS5_IRQ_2D                  IRQ_SPI(91)
-#define EXYNOS5_IRQ_EFNFCON_0           IRQ_SPI(92)
-#define EXYNOS5_IRQ_EFNFCON_1           IRQ_SPI(93)
-#define EXYNOS5_IRQ_MIXER               IRQ_SPI(94)
-#define EXYNOS5_IRQ_HDMI                IRQ_SPI(95)
-#define EXYNOS5_IRQ_MFC                 IRQ_SPI(96)
-#define EXYNOS5_IRQ_AUDIO_SS            IRQ_SPI(97)
-#define EXYNOS5_IRQ_I2S0                IRQ_SPI(98)
-#define EXYNOS5_IRQ_I2S1                IRQ_SPI(99)
-#define EXYNOS5_IRQ_I2S2                IRQ_SPI(100)
-#define EXYNOS5_IRQ_AC97                IRQ_SPI(101)
-#define EXYNOS5_IRQ_PCM0                IRQ_SPI(102)
-#define EXYNOS5_IRQ_PCM1                IRQ_SPI(103)
-#define EXYNOS5_IRQ_PCM2                IRQ_SPI(104)
-#define EXYNOS5_IRQ_SPDIF               IRQ_SPI(105)
-#define EXYNOS5_IRQ_ADC0                IRQ_SPI(106)
-#define EXYNOS5_IRQ_ADC1                IRQ_SPI(107)
-#define EXYNOS5_IRQ_SATA_PHY            IRQ_SPI(108)
-#define EXYNOS5_IRQ_SATA_PMEMREQ        IRQ_SPI(109)
-#define EXYNOS5_IRQ_CAM_C               IRQ_SPI(110)
-#define EXYNOS5_IRQ_EAGLE_PMU           IRQ_SPI(111)
-#define EXYNOS5_IRQ_INTFEEDCTRL_SSS     IRQ_SPI(112)
-#define EXYNOS5_IRQ_DP1_INTP1           IRQ_SPI(113)
-#define EXYNOS5_IRQ_CEC                 IRQ_SPI(114)
-#define EXYNOS5_IRQ_SATA                IRQ_SPI(115)
-
-#define EXYNOS5_IRQ_MMC44               IRQ_SPI(123)
-#define EXYNOS5_IRQ_MDMA1               IRQ_SPI(124)
-#define EXYNOS5_IRQ_FIMC_LITE0          IRQ_SPI(125)
-#define EXYNOS5_IRQ_FIMC_LITE1          IRQ_SPI(126)
-#define EXYNOS5_IRQ_RP_TIMER            IRQ_SPI(127)
-
-/* EXYNOS5440 */
-
-#define EXYNOS5440_IRQ_UART0            IRQ_SPI(2)
-#define EXYNOS5440_IRQ_UART1            IRQ_SPI(3)
-
-#define EXYNOS5_IRQ_PMU                 COMBINER_IRQ(1, 2)
-
-#define EXYNOS5_IRQ_SYSMMU_GSC0_0       COMBINER_IRQ(2, 0)
-#define EXYNOS5_IRQ_SYSMMU_GSC0_1       COMBINER_IRQ(2, 1)
-#define EXYNOS5_IRQ_SYSMMU_GSC1_0       COMBINER_IRQ(2, 2)
-#define EXYNOS5_IRQ_SYSMMU_GSC1_1       COMBINER_IRQ(2, 3)
-#define EXYNOS5_IRQ_SYSMMU_GSC2_0       COMBINER_IRQ(2, 4)
-#define EXYNOS5_IRQ_SYSMMU_GSC2_1       COMBINER_IRQ(2, 5)
-#define EXYNOS5_IRQ_SYSMMU_GSC3_0       COMBINER_IRQ(2, 6)
-#define EXYNOS5_IRQ_SYSMMU_GSC3_1       COMBINER_IRQ(2, 7)
-
-#define EXYNOS5_IRQ_SYSMMU_LITE2_0      COMBINER_IRQ(3, 0)
-#define EXYNOS5_IRQ_SYSMMU_LITE2_1      COMBINER_IRQ(3, 1)
-#define EXYNOS5_IRQ_SYSMMU_FIMD1_0      COMBINER_IRQ(3, 2)
-#define EXYNOS5_IRQ_SYSMMU_FIMD1_1      COMBINER_IRQ(3, 3)
-#define EXYNOS5_IRQ_SYSMMU_LITE0_0      COMBINER_IRQ(3, 4)
-#define EXYNOS5_IRQ_SYSMMU_LITE0_1      COMBINER_IRQ(3, 5)
-#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6)
-#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7)
-
-#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0    COMBINER_IRQ(4, 0)
-#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1    COMBINER_IRQ(4, 1)
-#define EXYNOS5_IRQ_SYSMMU_JPEG_0       COMBINER_IRQ(4, 2)
-#define EXYNOS5_IRQ_SYSMMU_JPEG_1       COMBINER_IRQ(4, 3)
-
-#define EXYNOS5_IRQ_SYSMMU_FD_0         COMBINER_IRQ(5, 0)
-#define EXYNOS5_IRQ_SYSMMU_FD_1         COMBINER_IRQ(5, 1)
-#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2)
-#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3)
-#define EXYNOS5_IRQ_SYSMMU_MCUISP_0     COMBINER_IRQ(5, 4)
-#define EXYNOS5_IRQ_SYSMMU_MCUISP_1     COMBINER_IRQ(5, 5)
-#define EXYNOS5_IRQ_SYSMMU_3DNR_0       COMBINER_IRQ(5, 6)
-#define EXYNOS5_IRQ_SYSMMU_3DNR_1       COMBINER_IRQ(5, 7)
-
-#define EXYNOS5_IRQ_SYSMMU_ARM_0        COMBINER_IRQ(6, 0)
-#define EXYNOS5_IRQ_SYSMMU_ARM_1        COMBINER_IRQ(6, 1)
-#define EXYNOS5_IRQ_SYSMMU_MFC_R_0      COMBINER_IRQ(6, 2)
-#define EXYNOS5_IRQ_SYSMMU_MFC_R_1      COMBINER_IRQ(6, 3)
-#define EXYNOS5_IRQ_SYSMMU_RTIC_0       COMBINER_IRQ(6, 4)
-#define EXYNOS5_IRQ_SYSMMU_RTIC_1       COMBINER_IRQ(6, 5)
-#define EXYNOS5_IRQ_SYSMMU_SSS_0        COMBINER_IRQ(6, 6)
-#define EXYNOS5_IRQ_SYSMMU_SSS_1        COMBINER_IRQ(6, 7)
-
-#define EXYNOS5_IRQ_SYSMMU_MDMA0_0      COMBINER_IRQ(7, 0)
-#define EXYNOS5_IRQ_SYSMMU_MDMA0_1      COMBINER_IRQ(7, 1)
-#define EXYNOS5_IRQ_SYSMMU_MDMA1_0      COMBINER_IRQ(7, 2)
-#define EXYNOS5_IRQ_SYSMMU_MDMA1_1      COMBINER_IRQ(7, 3)
-#define EXYNOS5_IRQ_SYSMMU_TV_0         COMBINER_IRQ(7, 4)
-#define EXYNOS5_IRQ_SYSMMU_TV_1         COMBINER_IRQ(7, 5)
-
-#define EXYNOS5_IRQ_SYSMMU_MFC_L_0      COMBINER_IRQ(8, 5)
-#define EXYNOS5_IRQ_SYSMMU_MFC_L_1      COMBINER_IRQ(8, 6)
-
-#define EXYNOS5_IRQ_SYSMMU_DIS1_0       COMBINER_IRQ(9, 4)
-#define EXYNOS5_IRQ_SYSMMU_DIS1_1       COMBINER_IRQ(9, 5)
-
-#define EXYNOS5_IRQ_DP                  COMBINER_IRQ(10, 3)
-#define EXYNOS5_IRQ_SYSMMU_DIS0_0       COMBINER_IRQ(10, 4)
-#define EXYNOS5_IRQ_SYSMMU_DIS0_1       COMBINER_IRQ(10, 5)
-#define EXYNOS5_IRQ_SYSMMU_ISP_0        COMBINER_IRQ(10, 6)
-#define EXYNOS5_IRQ_SYSMMU_ISP_1        COMBINER_IRQ(10, 7)
-
-#define EXYNOS5_IRQ_SYSMMU_ODC_0        COMBINER_IRQ(11, 0)
-#define EXYNOS5_IRQ_SYSMMU_ODC_1        COMBINER_IRQ(11, 1)
-#define EXYNOS5_IRQ_SYSMMU_DRC_0        COMBINER_IRQ(11, 6)
-#define EXYNOS5_IRQ_SYSMMU_DRC_1        COMBINER_IRQ(11, 7)
-
-#define EXYNOS5_IRQ_MDMA1_ABORT         COMBINER_IRQ(13, 1)
-
-#define EXYNOS5_IRQ_MDMA0_ABORT         COMBINER_IRQ(15, 3)
-
-#define EXYNOS5_IRQ_FIMD1_FIFO          COMBINER_IRQ(18, 4)
-#define EXYNOS5_IRQ_FIMD1_VSYNC         COMBINER_IRQ(18, 5)
-#define EXYNOS5_IRQ_FIMD1_SYSTEM        COMBINER_IRQ(18, 6)
-
-#define EXYNOS5_IRQ_ARMIOP_GIC          COMBINER_IRQ(19, 0)
-#define EXYNOS5_IRQ_ARMISP_GIC          COMBINER_IRQ(19, 1)
-#define EXYNOS5_IRQ_IOP_GIC             COMBINER_IRQ(19, 3)
-#define EXYNOS5_IRQ_ISP_GIC             COMBINER_IRQ(19, 4)
-
-#define EXYNOS5_IRQ_PMU_CPU1            COMBINER_IRQ(22, 4)
-
-#define EXYNOS5_IRQ_EINT0               COMBINER_IRQ(23, 0)
-
-#define EXYNOS5_IRQ_EINT1               COMBINER_IRQ(24, 0)
-#define EXYNOS5_IRQ_SYSMMU_LITE1_0      COMBINER_IRQ(24, 1)
-#define EXYNOS5_IRQ_SYSMMU_LITE1_1      COMBINER_IRQ(24, 2)
-#define EXYNOS5_IRQ_SYSMMU_2D_0         COMBINER_IRQ(24, 5)
-#define EXYNOS5_IRQ_SYSMMU_2D_1         COMBINER_IRQ(24, 6)
-
-#define EXYNOS5_IRQ_EINT2               COMBINER_IRQ(25, 0)
-#define EXYNOS5_IRQ_EINT3               COMBINER_IRQ(25, 1)
-
-#define EXYNOS5_IRQ_EINT4               COMBINER_IRQ(26, 0)
-#define EXYNOS5_IRQ_EINT5               COMBINER_IRQ(26, 1)
-
-#define EXYNOS5_IRQ_EINT6               COMBINER_IRQ(27, 0)
-#define EXYNOS5_IRQ_EINT7               COMBINER_IRQ(27, 1)
-
-#define EXYNOS5_IRQ_EINT8               COMBINER_IRQ(28, 0)
-#define EXYNOS5_IRQ_EINT9               COMBINER_IRQ(28, 1)
-
-#define EXYNOS5_IRQ_EINT10              COMBINER_IRQ(29, 0)
-#define EXYNOS5_IRQ_EINT11              COMBINER_IRQ(29, 1)
-
-#define EXYNOS5_IRQ_EINT12              COMBINER_IRQ(30, 0)
-#define EXYNOS5_IRQ_EINT13              COMBINER_IRQ(30, 1)
-
-#define EXYNOS5_IRQ_EINT14              COMBINER_IRQ(31, 0)
-#define EXYNOS5_IRQ_EINT15              COMBINER_IRQ(31, 1)
-
-#define EXYNOS5_MAX_COMBINER_NR         32
-
-#define EXYNOS5_IRQ_GPIO1_NR_GROUPS     14
-#define EXYNOS5_IRQ_GPIO2_NR_GROUPS     9
-#define EXYNOS5_IRQ_GPIO3_NR_GROUPS     5
-#define EXYNOS5_IRQ_GPIO4_NR_GROUPS     1
-
-#define MAX_COMBINER_NR                 (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \
-                                        EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR)
-
-#define S5P_EINT_BASE1                  COMBINER_IRQ(MAX_COMBINER_NR, 0)
-#define S5P_EINT_BASE2                  (S5P_EINT_BASE1 + 16)
-#define S5P_GPIOINT_BASE                (S5P_EINT_BASE1 + 32)
-#define IRQ_GPIO_END                    (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
-#define IRQ_TIMER_BASE                  (IRQ_GPIO_END + 64)
-
-/* Set the default NR_IRQS */
-#define EXYNOS_NR_IRQS                  (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
-
-#ifndef CONFIG_SPARSE_IRQ
-#define NR_IRQS                         EXYNOS_NR_IRQS
-#endif
-
-#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 92b29bb583cb..7b046b59d9ec 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -30,31 +30,6 @@
 #define EXYNOS4x12_PA_SYSRAM_NS         0x0204F000
 #define EXYNOS5250_PA_SYSRAM_NS         0x0204F000
 
-#define EXYNOS4_PA_FIMC0                0x11800000
-#define EXYNOS4_PA_FIMC1                0x11810000
-#define EXYNOS4_PA_FIMC2                0x11820000
-#define EXYNOS4_PA_FIMC3                0x11830000
-
-#define EXYNOS4_PA_JPEG                 0x11840000
-
-/* x = 0...1 */
-#define EXYNOS4_PA_FIMC_LITE(x)         (0x12390000 + ((x) * 0x10000))
-
-#define EXYNOS4_PA_G2D                  0x12800000
-
-#define EXYNOS4_PA_I2S0                 0x03830000
-#define EXYNOS4_PA_I2S1                 0xE3100000
-#define EXYNOS4_PA_I2S2                 0xE2A00000
-
-#define EXYNOS4_PA_PCM0                 0x03840000
-#define EXYNOS4_PA_PCM1                 0x13980000
-#define EXYNOS4_PA_PCM2                 0x13990000
-
-#define EXYNOS4_PA_SROM_BANK(x)         (0x04000000 + ((x) * 0x01000000))
-
-#define EXYNOS4_PA_ONENAND              0x0C000000
-#define EXYNOS4_PA_ONENAND_DMA          0x0C600000
-
 #define EXYNOS_PA_CHIPID                0x10000000
 
 #define EXYNOS4_PA_SYSCON               0x10010000
@@ -71,10 +46,6 @@
 #define EXYNOS4_PA_WATCHDOG             0x10060000
 #define EXYNOS5_PA_WATCHDOG             0x101D0000
 
-#define EXYNOS4_PA_RTC                  0x10070000
-
-#define EXYNOS4_PA_KEYPAD               0x100A0000
-
 #define EXYNOS4_PA_DMC0                 0x10400000
 #define EXYNOS4_PA_DMC1                 0x10410000
 
@@ -87,207 +58,22 @@
 #define EXYNOS5_PA_GIC_DIST             0x10481000
 
 #define EXYNOS4_PA_COREPERI             0x10500000
-#define EXYNOS4_PA_TWD                  0x10500600
 #define EXYNOS4_PA_L2CC                 0x10502000
 
-#define EXYNOS4_PA_TMU                  0x100C0000
-
-#define EXYNOS4_PA_MDMA0                0x10810000
-#define EXYNOS4_PA_MDMA1                0x12850000
-#define EXYNOS4_PA_S_MDMA1              0x12840000
-#define EXYNOS4_PA_PDMA0                0x12680000
-#define EXYNOS4_PA_PDMA1                0x12690000
-#define EXYNOS5_PA_MDMA0                0x10800000
-#define EXYNOS5_PA_MDMA1                0x11C10000
-#define EXYNOS5_PA_PDMA0                0x121A0000
-#define EXYNOS5_PA_PDMA1                0x121B0000
-
-#define EXYNOS4_PA_SYSMMU_MDMA          0x10A40000
-#define EXYNOS4_PA_SYSMMU_2D_ACP        0x10A40000
-#define EXYNOS4_PA_SYSMMU_SSS           0x10A50000
-#define EXYNOS4_PA_SYSMMU_FIMC0         0x11A20000
-#define EXYNOS4_PA_SYSMMU_FIMC1         0x11A30000
-#define EXYNOS4_PA_SYSMMU_FIMC2         0x11A40000
-#define EXYNOS4_PA_SYSMMU_FIMC3         0x11A50000
-#define EXYNOS4_PA_SYSMMU_JPEG          0x11A60000
-#define EXYNOS4_PA_SYSMMU_FIMD0         0x11E20000
-#define EXYNOS4_PA_SYSMMU_FIMD1         0x12220000
-#define EXYNOS4_PA_SYSMMU_FIMC_ISP      0x12260000
-#define EXYNOS4_PA_SYSMMU_FIMC_DRC      0x12270000
-#define EXYNOS4_PA_SYSMMU_FIMC_FD       0x122A0000
-#define EXYNOS4_PA_SYSMMU_ISPCPU        0x122B0000
-#define EXYNOS4_PA_SYSMMU_FIMC_LITE0    0x123B0000
-#define EXYNOS4_PA_SYSMMU_FIMC_LITE1    0x123C0000
-#define EXYNOS4_PA_SYSMMU_PCIe          0x12620000
-#define EXYNOS4_PA_SYSMMU_G2D           0x12A20000
-#define EXYNOS4_PA_SYSMMU_ROTATOR       0x12A30000
-#define EXYNOS4_PA_SYSMMU_MDMA2         0x12A40000
-#define EXYNOS4_PA_SYSMMU_TV            0x12E20000
-#define EXYNOS4_PA_SYSMMU_MFC_L         0x13620000
-#define EXYNOS4_PA_SYSMMU_MFC_R         0x13630000
-
-#define EXYNOS5_PA_GSC0                 0x13E00000
-#define EXYNOS5_PA_GSC1                 0x13E10000
-#define EXYNOS5_PA_GSC2                 0x13E20000
-#define EXYNOS5_PA_GSC3                 0x13E30000
-
-#define EXYNOS5_PA_SYSMMU_MDMA1         0x10A40000
-#define EXYNOS5_PA_SYSMMU_SSS           0x10A50000
-#define EXYNOS5_PA_SYSMMU_2D            0x10A60000
-#define EXYNOS5_PA_SYSMMU_MFC_L         0x11200000
-#define EXYNOS5_PA_SYSMMU_MFC_R         0x11210000
-#define EXYNOS5_PA_SYSMMU_ROTATOR       0x11D40000
-#define EXYNOS5_PA_SYSMMU_MDMA2         0x11D50000
-#define EXYNOS5_PA_SYSMMU_JPEG          0x11F20000
-#define EXYNOS5_PA_SYSMMU_IOP           0x12360000
-#define EXYNOS5_PA_SYSMMU_RTIC          0x12370000
-#define EXYNOS5_PA_SYSMMU_ISP           0x13260000
-#define EXYNOS5_PA_SYSMMU_DRC           0x12370000
-#define EXYNOS5_PA_SYSMMU_SCALERC       0x13280000
-#define EXYNOS5_PA_SYSMMU_SCALERP       0x13290000
-#define EXYNOS5_PA_SYSMMU_FD            0x132A0000
-#define EXYNOS5_PA_SYSMMU_ISPCPU        0x132B0000
-#define EXYNOS5_PA_SYSMMU_ODC           0x132C0000
-#define EXYNOS5_PA_SYSMMU_DIS0          0x132D0000
-#define EXYNOS5_PA_SYSMMU_DIS1          0x132E0000
-#define EXYNOS5_PA_SYSMMU_3DNR          0x132F0000
-#define EXYNOS5_PA_SYSMMU_LITE0         0x13C40000
-#define EXYNOS5_PA_SYSMMU_LITE1         0x13C50000
-#define EXYNOS5_PA_SYSMMU_GSC0          0x13E80000
-#define EXYNOS5_PA_SYSMMU_GSC1          0x13E90000
-#define EXYNOS5_PA_SYSMMU_GSC2          0x13EA0000
-#define EXYNOS5_PA_SYSMMU_GSC3          0x13EB0000
-#define EXYNOS5_PA_SYSMMU_FIMD1         0x14640000
-#define EXYNOS5_PA_SYSMMU_TV            0x14650000
-
-#define EXYNOS4_PA_SPI0                 0x13920000
-#define EXYNOS4_PA_SPI1                 0x13930000
-#define EXYNOS4_PA_SPI2                 0x13940000
-#define EXYNOS5_PA_SPI0                 0x12D20000
-#define EXYNOS5_PA_SPI1                 0x12D30000
-#define EXYNOS5_PA_SPI2                 0x12D40000
-
-#define EXYNOS4_PA_GPIO1                0x11400000
-#define EXYNOS4_PA_GPIO2                0x11000000
-#define EXYNOS4_PA_GPIO3                0x03860000
-#define EXYNOS5_PA_GPIO1                0x11400000
-#define EXYNOS5_PA_GPIO2                0x13400000
-#define EXYNOS5_PA_GPIO3                0x10D10000
-#define EXYNOS5_PA_GPIO4                0x03860000
-
-#define EXYNOS4_PA_MIPI_CSIS0           0x11880000
-#define EXYNOS4_PA_MIPI_CSIS1           0x11890000
-
-#define EXYNOS4_PA_FIMD0                0x11C00000
-
-#define EXYNOS4_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
-#define EXYNOS4_PA_DWMCI                0x12550000
-#define EXYNOS5_PA_DWMCI0               0x12200000
-#define EXYNOS5_PA_DWMCI1               0x12210000
-#define EXYNOS5_PA_DWMCI2               0x12220000
-#define EXYNOS5_PA_DWMCI3               0x12230000
-
-#define EXYNOS4_PA_HSOTG                0x12480000
-#define EXYNOS4_PA_USB_HSPHY            0x125B0000
-
-#define EXYNOS4_PA_SATA                 0x12560000
-#define EXYNOS4_PA_SATAPHY              0x125D0000
-#define EXYNOS4_PA_SATAPHY_CTRL         0x126B0000
-
 #define EXYNOS4_PA_SROMC                0x12570000
 #define EXYNOS5_PA_SROMC                0x12250000
 
-#define EXYNOS4_PA_EHCI                 0x12580000
-#define EXYNOS4_PA_OHCI                 0x12590000
 #define EXYNOS4_PA_HSPHY                0x125B0000
-#define EXYNOS4_PA_MFC                  0x13400000
 
 #define EXYNOS4_PA_UART                 0x13800000
 #define EXYNOS5_PA_UART                 0x12C00000
 
-#define EXYNOS4_PA_VP                   0x12C00000
-#define EXYNOS4_PA_MIXER                0x12C10000
-#define EXYNOS4_PA_SDO                  0x12C20000
-#define EXYNOS4_PA_HDMI                 0x12D00000
-#define EXYNOS4_PA_IIC_HDMIPHY          0x138E0000
-
-#define EXYNOS4_PA_IIC(x)               (0x13860000 + ((x) * 0x10000))
-#define EXYNOS5_PA_IIC(x)               (0x12C60000 + ((x) * 0x10000))
-
-#define EXYNOS4_PA_ADC                  0x13910000
-#define EXYNOS4_PA_ADC1                 0x13911000
-
-#define EXYNOS4_PA_AC97                 0x139A0000
-
-#define EXYNOS4_PA_SPDIF                0x139B0000
-
 #define EXYNOS4_PA_TIMER                0x139D0000
 #define EXYNOS5_PA_TIMER                0x12DD0000
 
-#define EXYNOS4_PA_SDRAM                0x40000000
-#define EXYNOS5_PA_SDRAM                0x40000000
-
-/* Compatibiltiy Defines */
-
-#define S3C_PA_HSMMC0                   EXYNOS4_PA_HSMMC(0)
-#define S3C_PA_HSMMC1                   EXYNOS4_PA_HSMMC(1)
-#define S3C_PA_HSMMC2                   EXYNOS4_PA_HSMMC(2)
-#define S3C_PA_HSMMC3                   EXYNOS4_PA_HSMMC(3)
-#define S3C_PA_IIC                      EXYNOS4_PA_IIC(0)
-#define S3C_PA_IIC1                     EXYNOS4_PA_IIC(1)
-#define S3C_PA_IIC2                     EXYNOS4_PA_IIC(2)
-#define S3C_PA_IIC3                     EXYNOS4_PA_IIC(3)
-#define S3C_PA_IIC4                     EXYNOS4_PA_IIC(4)
-#define S3C_PA_IIC5                     EXYNOS4_PA_IIC(5)
-#define S3C_PA_IIC6                     EXYNOS4_PA_IIC(6)
-#define S3C_PA_IIC7                     EXYNOS4_PA_IIC(7)
-#define S3C_PA_RTC                      EXYNOS4_PA_RTC
-#define S3C_PA_WDT                      EXYNOS4_PA_WATCHDOG
-#define S3C_PA_SPI0                     EXYNOS4_PA_SPI0
-#define S3C_PA_SPI1                     EXYNOS4_PA_SPI1
-#define S3C_PA_SPI2                     EXYNOS4_PA_SPI2
-#define S3C_PA_USB_HSOTG                EXYNOS4_PA_HSOTG
-
-#define S5P_PA_EHCI                     EXYNOS4_PA_EHCI
-#define S5P_PA_FIMC0                    EXYNOS4_PA_FIMC0
-#define S5P_PA_FIMC1                    EXYNOS4_PA_FIMC1
-#define S5P_PA_FIMC2                    EXYNOS4_PA_FIMC2
-#define S5P_PA_FIMC3                    EXYNOS4_PA_FIMC3
-#define S5P_PA_JPEG                     EXYNOS4_PA_JPEG
-#define S5P_PA_G2D                      EXYNOS4_PA_G2D
-#define S5P_PA_FIMD0                    EXYNOS4_PA_FIMD0
-#define S5P_PA_HDMI                     EXYNOS4_PA_HDMI
-#define S5P_PA_IIC_HDMIPHY              EXYNOS4_PA_IIC_HDMIPHY
-#define S5P_PA_MFC                      EXYNOS4_PA_MFC
-#define S5P_PA_MIPI_CSIS0               EXYNOS4_PA_MIPI_CSIS0
-#define S5P_PA_MIPI_CSIS1               EXYNOS4_PA_MIPI_CSIS1
-#define S5P_PA_MIXER                    EXYNOS4_PA_MIXER
-#define S5P_PA_ONENAND                  EXYNOS4_PA_ONENAND
-#define S5P_PA_ONENAND_DMA              EXYNOS4_PA_ONENAND_DMA
-#define S5P_PA_SDO                      EXYNOS4_PA_SDO
-#define S5P_PA_SDRAM                    EXYNOS4_PA_SDRAM
-#define S5P_PA_VP                       EXYNOS4_PA_VP
-
-#define SAMSUNG_PA_ADC                  EXYNOS4_PA_ADC
-#define SAMSUNG_PA_ADC1                 EXYNOS4_PA_ADC1
-#define SAMSUNG_PA_KEYPAD               EXYNOS4_PA_KEYPAD
-
 /* Compatibility UART */
 
-#define EXYNOS4_PA_UART0                0x13800000
-#define EXYNOS4_PA_UART1                0x13810000
-#define EXYNOS4_PA_UART2                0x13820000
-#define EXYNOS4_PA_UART3                0x13830000
-#define EXYNOS4_SZ_UART                 SZ_256
-
-#define EXYNOS5_PA_UART0                0x12C00000
-#define EXYNOS5_PA_UART1                0x12C10000
-#define EXYNOS5_PA_UART2                0x12C20000
-#define EXYNOS5_PA_UART3                0x12C30000
-
 #define EXYNOS5440_PA_UART0             0x000B0000
-#define EXYNOS5440_PA_UART1             0x000C0000
-#define EXYNOS5440_SZ_UART              SZ_256
 
 #define S3C_VA_UARTx(x)                 (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
index 7dbbfec13ea5..2b00833b6641 100644
--- a/arch/arm/mach-exynos/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos/include/mach/pm-core.h
@@ -18,8 +18,15 @@
 #ifndef __ASM_ARCH_PM_CORE_H
 #define __ASM_ARCH_PM_CORE_H __FILE__
 
+#include <linux/of.h>
 #include <mach/regs-pmu.h>
 
+#ifdef CONFIG_PINCTRL_EXYNOS
+extern u32 exynos_get_eint_wake_mask(void);
+#else
+static inline u32 exynos_get_eint_wake_mask(void) { return 0xffffffff; }
+#endif
+
 static inline void s3c_pm_debug_init_uart(void)
 {
         /* nothing here yet */
@@ -27,7 +34,7 @@ static inline void s3c_pm_debug_init_uart(void)
 
 static inline void s3c_pm_arch_prepare_irqs(void)
 {
-        __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
+        __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
         __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
 }
 
@@ -57,4 +64,9 @@ static inline void samsung_pm_saved_gpios(void)
         /* nothing here yet */
 }
 
+/* Compatibility definitions to make plat-samsung/pm.c compile */
+#define IRQ_EINT_BIT(x)         1
+#define s3c_irqwake_intallow    0
+#define s3c_irqwake_eintallow   0
+
 #endif /* __ASM_ARCH_PM_CORE_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
deleted file mode 100644
index e4b5b60dcb85..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - GPIO (including EINT) register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_GPIO_H
-#define __ASM_ARCH_REGS_GPIO_H __FILE__
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-
-#define EINT_REG_NR(x)                  (EINT_OFFSET(x) >> 3)
-#define EINT_CON(b, x)                  (b + 0xE00 + (EINT_REG_NR(x) * 4))
-#define EINT_FLTCON(b, x)               (b + 0xE80 + (EINT_REG_NR(x) * 4))
-#define EINT_MASK(b, x)                 (b + 0xF00 + (EINT_REG_NR(x) * 4))
-#define EINT_PEND(b, x)                 (b + 0xF40 + (EINT_REG_NR(x) * 4))
-
-#define EINT_OFFSET_BIT(x)              (1 << (EINT_OFFSET(x) & 0x7))
-
-/* compatibility for plat-s5p/irq-pm.c */
-#define EXYNOS4_EINT40CON               (S5P_VA_GPIO2 + 0xE00)
-#define S5P_EINT_CON(x)                 (EXYNOS4_EINT40CON + ((x) * 0x4))
-
-#define EXYNOS4_EINT40FLTCON0           (S5P_VA_GPIO2 + 0xE80)
-#define S5P_EINT_FLTCON(x)              (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4))
-
-#define EXYNOS4_EINT40MASK              (S5P_VA_GPIO2 + 0xF00)
-#define S5P_EINT_MASK(x)                (EXYNOS4_EINT40MASK + ((x) * 0x4))
-
-#define EXYNOS4_EINT40PEND              (S5P_VA_GPIO2 + 0xF40)
-#define S5P_EINT_PEND(x)                (EXYNOS4_EINT40PEND + ((x) * 0x4))
-
-#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
deleted file mode 100644
index 07277735252e..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics Co.Ltd
- * Author: Joonyoung Shim <jy0922.shim@samsung.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifndef __PLAT_S5P_REGS_USB_PHY_H
-#define __PLAT_S5P_REGS_USB_PHY_H
-
-#define EXYNOS4_HSOTG_PHYREG(x)         ((x) + S3C_VA_USB_HSPHY)
-
-#define EXYNOS4_PHYPWR                  EXYNOS4_HSOTG_PHYREG(0x00)
-#define PHY1_HSIC_NORMAL_MASK           (0xf << 9)
-#define PHY1_HSIC1_SLEEP                (1 << 12)
-#define PHY1_HSIC1_FORCE_SUSPEND        (1 << 11)
-#define PHY1_HSIC0_SLEEP                (1 << 10)
-#define PHY1_HSIC0_FORCE_SUSPEND        (1 << 9)
-
-#define PHY1_STD_NORMAL_MASK            (0x7 << 6)
-#define PHY1_STD_SLEEP                  (1 << 8)
-#define PHY1_STD_ANALOG_POWERDOWN       (1 << 7)
-#define PHY1_STD_FORCE_SUSPEND          (1 << 6)
-
-#define PHY0_NORMAL_MASK                (0x39 << 0)
-#define PHY0_SLEEP                      (1 << 5)
-#define PHY0_OTG_DISABLE                (1 << 4)
-#define PHY0_ANALOG_POWERDOWN           (1 << 3)
-#define PHY0_FORCE_SUSPEND              (1 << 0)
-
-#define EXYNOS4_PHYCLK                  EXYNOS4_HSOTG_PHYREG(0x04)
-#define PHY1_COMMON_ON_N                (1 << 7)
-#define PHY0_COMMON_ON_N                (1 << 4)
-#define PHY0_ID_PULLUP                  (1 << 2)
-
-#define EXYNOS4_CLKSEL_SHIFT            (0)
-
-#define EXYNOS4210_CLKSEL_MASK          (0x3 << 0)
-#define EXYNOS4210_CLKSEL_48M           (0x0 << 0)
-#define EXYNOS4210_CLKSEL_12M           (0x2 << 0)
-#define EXYNOS4210_CLKSEL_24M           (0x3 << 0)
-
-#define EXYNOS4X12_CLKSEL_MASK          (0x7 << 0)
-#define EXYNOS4X12_CLKSEL_9600K         (0x0 << 0)
-#define EXYNOS4X12_CLKSEL_10M           (0x1 << 0)
-#define EXYNOS4X12_CLKSEL_12M           (0x2 << 0)
-#define EXYNOS4X12_CLKSEL_19200K        (0x3 << 0)
-#define EXYNOS4X12_CLKSEL_20M           (0x4 << 0)
-#define EXYNOS4X12_CLKSEL_24M           (0x5 << 0)
-
-#define EXYNOS4_RSTCON                  EXYNOS4_HSOTG_PHYREG(0x08)
-#define HOST_LINK_PORT_SWRST_MASK       (0xf << 6)
-#define HOST_LINK_PORT2_SWRST           (1 << 9)
-#define HOST_LINK_PORT1_SWRST           (1 << 8)
-#define HOST_LINK_PORT0_SWRST           (1 << 7)
-#define HOST_LINK_ALL_SWRST             (1 << 6)
-
-#define PHY1_SWRST_MASK                 (0x7 << 3)
-#define PHY1_HSIC_SWRST                 (1 << 5)
-#define PHY1_STD_SWRST                  (1 << 4)
-#define PHY1_ALL_SWRST                  (1 << 3)
-
-#define PHY0_SWRST_MASK                 (0x7 << 0)
-#define PHY0_PHYLINK_SWRST              (1 << 2)
-#define PHY0_HLINK_SWRST                (1 << 1)
-#define PHY0_SWRST                      (1 << 0)
-
-#define EXYNOS4_PHY1CON                 EXYNOS4_HSOTG_PHYREG(0x34)
-#define FPENABLEN                       (1 << 0)
-
-#endif /* __PLAT_S5P_REGS_USB_PHY_H */
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
deleted file mode 100644
index 5f0f55701374..000000000000
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mach-armlex4210.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/gpio.h>
-#include <linux/io.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/serial_core.h>
-#include <linux/smsc911x.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/gpio-cfg.h>
-#include <plat/regs-serial.h>
-#include <plat/regs-srom.h>
-#include <plat/sdhci.h>
-
-#include <mach/irqs.h>
-#include <mach/map.h>
-
-#include "common.h"
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define ARMLEX4210_ULCON_DEFAULT        S3C2410_LCON_CS8
-
-#define ARMLEX4210_UFCON_DEFAULT        (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-
-static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = ARMLEX4210_UCON_DEFAULT,
-                .ulcon          = ARMLEX4210_ULCON_DEFAULT,
-                .ufcon          = ARMLEX4210_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = ARMLEX4210_UCON_DEFAULT,
-                .ulcon          = ARMLEX4210_ULCON_DEFAULT,
-                .ufcon          = ARMLEX4210_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = ARMLEX4210_UCON_DEFAULT,
-                .ulcon          = ARMLEX4210_ULCON_DEFAULT,
-                .ufcon          = ARMLEX4210_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = ARMLEX4210_UCON_DEFAULT,
-                .ulcon          = ARMLEX4210_ULCON_DEFAULT,
-                .ufcon          = ARMLEX4210_UFCON_DEFAULT,
-        },
-};
-
-static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_PERMANENT,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
-        .max_width              = 8,
-        .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-
-static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPX2(5),
-        .ext_cd_gpio_invert     = 1,
-        .max_width              = 4,
-};
-
-static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_PERMANENT,
-        .max_width              = 4,
-};
-
-static void __init armlex4210_sdhci_init(void)
-{
-        s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata);
-        s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata);
-        s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata);
-}
-
-static void __init armlex4210_wlan_init(void)
-{
-        /* enable */
-        s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP);
-
-        /* reset */
-        s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP);
-
-        /* wakeup */
-        s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP);
-}
-
-static struct resource armlex4210_smsc911x_resources[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(3), SZ_64K),
-        [1] = DEFINE_RES_NAMED(IRQ_EINT(27), 1, NULL, IORESOURCE_IRQ \
-                                        | IRQF_TRIGGER_HIGH),
-};
-
-static struct smsc911x_platform_config smsc9215_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
-        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-        .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-        .mac            = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
-};
-
-static struct platform_device armlex4210_smsc911x = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(armlex4210_smsc911x_resources),
-        .resource       = armlex4210_smsc911x_resources,
-        .dev            = {
-                .platform_data  = &smsc9215_config,
-        },
-};
-
-static struct platform_device *armlex4210_devices[] __initdata = {
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-        &s3c_device_rtc,
-        &s3c_device_wdt,
-        &armlex4210_smsc911x,
-        &exynos4_device_ahci,
-};
-
-static void __init armlex4210_smsc911x_init(void)
-{
-        u32 cs1;
-
-        /* configure nCS1 width to 16 bits */
-        cs1 = __raw_readl(S5P_SROM_BW) &
-                ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
-        cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
-                (0 << S5P_SROM_BW__WAITENABLE__SHIFT) |
-                (1 << S5P_SROM_BW__ADDRMODE__SHIFT) |
-                (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
-                S5P_SROM_BW__NCS1__SHIFT;
-        __raw_writel(cs1, S5P_SROM_BW);
-
-        /* set timing for nCS1 suitable for ethernet chip */
-        __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
-                     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
-                     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
-                     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
-}
-
-static void __init armlex4210_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-        s3c24xx_init_uarts(armlex4210_uartcfgs,
-                           ARRAY_SIZE(armlex4210_uartcfgs));
-}
-
-static void __init armlex4210_machine_init(void)
-{
-        armlex4210_smsc911x_init();
-
-        armlex4210_sdhci_init();
-
-        armlex4210_wlan_init();
-
-        platform_add_devices(armlex4210_devices,
-                             ARRAY_SIZE(armlex4210_devices));
-}
-
-MACHINE_START(ARMLEX4210, "ARMLEX4210")
-        /* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = armlex4210_map_io,
-        .init_machine   = armlex4210_machine_init,
-        .init_late      = exynos_init_late,
-        .init_time      = exynos_init_time,
-        .restart        = exynos4_restart,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index b9ed834a7eee..0099c6c13bba 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -23,11 +23,6 @@
 
 #include "common.h"
 
-static void __init exynos4_dt_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-}
-
 static void __init exynos4_dt_machine_init(void)
 {
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
@@ -55,8 +50,7 @@ static void __init exynos4_reserve(void)
 DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
         /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
         .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = exynos4_dt_map_io,
+        .map_io         = exynos_init_io,
         .init_early     = exynos_firmware_init,
         .init_machine   = exynos4_dt_machine_init,
         .init_late      = exynos_init_late,
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 753b94f3fca7..d5c8afdeaa39 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -23,11 +23,6 @@
 
 #include "common.h"
 
-static void __init exynos5_dt_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-}
-
 static void __init exynos5_dt_machine_init(void)
 {
         struct device_node *i2c_np;
@@ -76,9 +71,8 @@ static void __init exynos5_reserve(void)
 
 DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .init_irq       = exynos5_init_irq,
         .smp            = smp_ops(exynos_smp_ops),
-        .map_io         = exynos5_dt_map_io,
+        .map_io         = exynos_init_io,
         .init_machine   = exynos5_dt_machine_init,
         .init_late      = exynos_init_late,
         .init_time      = exynos_init_time,
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
deleted file mode 100644
index 5c8b2878dbbd..000000000000
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ /dev/null
@@ -1,1388 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/mach-nuri.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/serial_core.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/i2c/atmel_mxt_ts.h>
-#include <linux/i2c-gpio.h>
-#include <linux/gpio_keys.h>
-#include <linux/gpio.h>
-#include <linux/power/max8903_charger.h>
-#include <linux/power/max17042_battery.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/mfd/max8997.h>
-#include <linux/mfd/max8997-private.h>
-#include <linux/mmc/host.h>
-#include <linux/fb.h>
-#include <linux/pwm_backlight.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/mipi-csis.h>
-#include <linux/platform_data/s3c-hsotg.h>
-#include <linux/platform_data/usb-ehci-s5p.h>
-#include <drm/exynos_drm.h>
-
-#include <video/platform_lcd.h>
-#include <video/samsung_fimd.h>
-#include <media/m5mols.h>
-#include <media/s5k6aa.h>
-#include <media/s5p_fimc.h>
-#include <media/v4l2-mediabus.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <plat/adc.h>
-#include <plat/regs-serial.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/fb.h>
-#include <plat/sdhci.h>
-#include <plat/clock.h>
-#include <plat/gpio-cfg.h>
-#include <plat/mfc.h>
-#include <plat/fimc-core.h>
-#include <plat/camport.h>
-
-#include <mach/irqs.h>
-#include <mach/map.h>
-
-#include "common.h"
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define NURI_UCON_DEFAULT       (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define NURI_ULCON_DEFAULT      S3C2410_LCON_CS8
-
-#define NURI_UFCON_DEFAULT      (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG256 |      \
-                                 S5PV210_UFCON_RXTRIG256)
-
-enum fixed_regulator_id {
-        FIXED_REG_ID_MMC = 0,
-        FIXED_REG_ID_MAX8903,
-        FIXED_REG_ID_CAM_A28V,
-        FIXED_REG_ID_CAM_12V,
-        FIXED_REG_ID_CAM_VT_15V,
-};
-
-static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
-        {
-                .hwport         = 0,
-                .ucon           = NURI_UCON_DEFAULT,
-                .ulcon          = NURI_ULCON_DEFAULT,
-                .ufcon          = NURI_UFCON_DEFAULT,
-        },
-        {
-                .hwport         = 1,
-                .ucon           = NURI_UCON_DEFAULT,
-                .ulcon          = NURI_ULCON_DEFAULT,
-                .ufcon          = NURI_UFCON_DEFAULT,
-        },
-        {
-                .hwport         = 2,
-                .ucon           = NURI_UCON_DEFAULT,
-                .ulcon          = NURI_ULCON_DEFAULT,
-                .ufcon          = NURI_UFCON_DEFAULT,
-        },
-        {
-                .hwport         = 3,
-                .ucon           = NURI_UCON_DEFAULT,
-                .ulcon          = NURI_ULCON_DEFAULT,
-                .ufcon          = NURI_UFCON_DEFAULT,
-        },
-};
-
-/* eMMC */
-static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
-        .max_width              = 8,
-        .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
-                                MMC_CAP_ERASE),
-        .cd_type                = S3C_SDHCI_CD_PERMANENT,
-};
-
-static struct regulator_consumer_supply emmc_supplies[] = {
-        REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
-        REGULATOR_SUPPLY("vmmc", "dw_mmc"),
-};
-
-static struct regulator_init_data emmc_fixed_voltage_init_data = {
-        .constraints            = {
-                .name           = "VMEM_VDD_2.8V",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(emmc_supplies),
-        .consumer_supplies      = emmc_supplies,
-};
-
-static struct fixed_voltage_config emmc_fixed_voltage_config = {
-        .supply_name            = "MASSMEMORY_EN (inverted)",
-        .microvolts             = 2800000,
-        .gpio                   = EXYNOS4_GPL1(1),
-        .enable_high            = false,
-        .init_data              = &emmc_fixed_voltage_init_data,
-};
-
-static struct platform_device emmc_fixed_voltage = {
-        .name                   = "reg-fixed-voltage",
-        .id                     = FIXED_REG_ID_MMC,
-        .dev                    = {
-                .platform_data  = &emmc_fixed_voltage_config,
-        },
-};
-
-/* SD */
-static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
-        .max_width              = 4,
-        .host_caps              = MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .ext_cd_gpio            = EXYNOS4_GPX3(3),      /* XEINT_27 */
-        .ext_cd_gpio_invert     = 1,
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-};
-
-/* WLAN */
-static struct s3c_sdhci_platdata nuri_hsmmc3_data __initdata = {
-        .max_width              = 4,
-        .host_caps              = MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .cd_type                = S3C_SDHCI_CD_EXTERNAL,
-};
-
-static void __init nuri_sdhci_init(void)
-{
-        s3c_sdhci0_set_platdata(&nuri_hsmmc0_data);
-        s3c_sdhci2_set_platdata(&nuri_hsmmc2_data);
-        s3c_sdhci3_set_platdata(&nuri_hsmmc3_data);
-}
-
-/* GPIO KEYS */
-static struct gpio_keys_button nuri_gpio_keys_tables[] = {
-        {
-                .code                   = KEY_VOLUMEUP,
-                .gpio                   = EXYNOS4_GPX2(0),      /* XEINT16 */
-                .desc                   = "gpio-keys: KEY_VOLUMEUP",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_VOLUMEDOWN,
-                .gpio                   = EXYNOS4_GPX2(1),      /* XEINT17 */
-                .desc                   = "gpio-keys: KEY_VOLUMEDOWN",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_POWER,
-                .gpio                   = EXYNOS4_GPX2(7),      /* XEINT23 */
-                .desc                   = "gpio-keys: KEY_POWER",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .wakeup                 = 1,
-                .debounce_interval      = 1,
-        },
-};
-
-static struct gpio_keys_platform_data nuri_gpio_keys_data = {
-        .buttons                = nuri_gpio_keys_tables,
-        .nbuttons               = ARRAY_SIZE(nuri_gpio_keys_tables),
-};
-
-static struct platform_device nuri_gpio_keys = {
-        .name                   = "gpio-keys",
-        .dev                    = {
-                .platform_data  = &nuri_gpio_keys_data,
-        },
-};
-
-#ifdef CONFIG_DRM_EXYNOS
-static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
-        .panel = {
-                .timing = {
-                        .xres           = 1024,
-                        .yres           = 600,
-                        .hsync_len      = 40,
-                        .left_margin    = 79,
-                        .right_margin   = 200,
-                        .vsync_len      = 10,
-                        .upper_margin   = 10,
-                        .lower_margin   = 11,
-                        .refresh        = 60,
-                },
-        },
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
-                          VIDCON0_CLKSEL_LCD,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .default_win    = 3,
-        .bpp            = 32,
-};
-
-#else
-/* Frame Buffer */
-static struct s3c_fb_pd_win nuri_fb_win0 = {
-        .max_bpp        = 24,
-        .default_bpp    = 16,
-        .xres           = 1024,
-        .yres           = 600,
-        .virtual_x      = 1024,
-        .virtual_y      = 2 * 600,
-};
-
-static struct fb_videomode nuri_lcd_timing = {
-        .left_margin    = 64,
-        .right_margin   = 16,
-        .upper_margin   = 64,
-        .lower_margin   = 1,
-        .hsync_len      = 48,
-        .vsync_len      = 3,
-        .xres           = 1024,
-        .yres           = 600,
-        .refresh        = 60,
-};
-
-static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
-        .win[0]         = &nuri_fb_win0,
-        .vtiming        = &nuri_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
-                          VIDCON0_CLKSEL_LCD,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-#endif
-
-static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
-{
-        int gpio = EXYNOS4_GPE1(5);
-
-        gpio_request(gpio, "LVDS_nSHDN");
-        gpio_direction_output(gpio, power);
-        gpio_free(gpio);
-}
-
-static int nuri_bl_init(struct device *dev)
-{
-        return gpio_request_one(EXYNOS4_GPE2(3), GPIOF_OUT_INIT_LOW,
-                                "LCD_LD0_EN");
-}
-
-static int nuri_bl_notify(struct device *dev, int brightness)
-{
-        if (brightness < 1)
-                brightness = 0;
-
-        gpio_set_value(EXYNOS4_GPE2(3), 1);
-
-        return brightness;
-}
-
-static void nuri_bl_exit(struct device *dev)
-{
-        gpio_free(EXYNOS4_GPE2(3));
-}
-
-/* nuri pwm backlight */
-static struct platform_pwm_backlight_data nuri_backlight_data = {
-        .pwm_id                 = 0,
-        .pwm_period_ns          = 30000,
-        .max_brightness         = 100,
-        .dft_brightness         = 50,
-        .init                   = nuri_bl_init,
-        .notify                 = nuri_bl_notify,
-        .exit                   = nuri_bl_exit,
-};
-
-static struct platform_device nuri_backlight_device = {
-        .name                   = "pwm-backlight",
-        .id                     = -1,
-        .dev                    = {
-                .parent         = &s3c_device_timer[0].dev,
-                .platform_data  = &nuri_backlight_data,
-        },
-};
-
-static struct plat_lcd_data nuri_lcd_platform_data = {
-        .set_power              = nuri_lcd_power_on,
-};
-
-static struct platform_device nuri_lcd_device = {
-        .name                   = "platform-lcd",
-        .id                     = -1,
-        .dev                    = {
-                .platform_data  = &nuri_lcd_platform_data,
-        },
-};
-
-/* I2C1 */
-static struct i2c_board_info i2c1_devs[] __initdata = {
-        /* Gyro, To be updated */
-};
-
-/* TSP */
-static struct mxt_platform_data mxt_platform_data = {
-        .x_line                 = 18,
-        .y_line                 = 11,
-        .x_size                 = 1024,
-        .y_size                 = 600,
-        .blen                   = 0x1,
-        .threshold              = 0x28,
-        .voltage                = 2800000,              /* 2.8V */
-        .orient                 = MXT_DIAGONAL_COUNTER,
-        .irqflags               = IRQF_TRIGGER_FALLING,
-};
-
-static struct s3c2410_platform_i2c i2c3_data __initdata = {
-        .flags          = 0,
-        .bus_num        = 3,
-        .slave_addr     = 0x10,
-        .frequency      = 400 * 1000,
-        .sda_delay      = 100,
-};
-
-static struct i2c_board_info i2c3_devs[] __initdata = {
-        {
-                I2C_BOARD_INFO("atmel_mxt_ts", 0x4a),
-                .platform_data  = &mxt_platform_data,
-                .irq            = IRQ_EINT(4),
-        },
-};
-
-static void __init nuri_tsp_init(void)
-{
-        int gpio;
-
-        /* TOUCH_INT: XEINT_4 */
-        gpio = EXYNOS4_GPX0(4);
-        gpio_request(gpio, "TOUCH_INT");
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-}
-
-static struct regulator_consumer_supply __initdata max8997_ldo1_[] = {
-        REGULATOR_SUPPLY("vdd", "s5p-adc"), /* Used by CPU's ADC drv */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo3_[] = {
-        REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* USB */
-        REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
-        REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo5_[] = {
-        REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */
-};
-static struct regulator_consumer_supply nuri_max8997_ldo6_consumer[] = {
-        REGULATOR_SUPPLY("vdd_reg", "6-003c"), /* S5K6AA camera */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo7_[] = {
-        REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo8_[] = {
-        REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), /* USB */
-        REGULATOR_SUPPLY("vdac", NULL), /* Used by CPU */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo11_[] = {
-        REGULATOR_SUPPLY("vcc", "platform-lcd"), /* U804 LVDS */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo12_[] = {
-        REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
-        REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.2"), /* TFLASH */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
-        REGULATOR_SUPPLY("inmotor", "max8997-haptic"),
-};
-static struct regulator_consumer_supply __initdata max8997_ldo15_[] = {
-        REGULATOR_SUPPLY("avdd", "3-004a"), /* Touch Screen */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo16_[] = {
-        REGULATOR_SUPPLY("d_sensor", "0-001f"), /* HDC803 */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo18_[] = {
-        REGULATOR_SUPPLY("vdd", "3-004a"), /* Touch Screen */
-};
-static struct regulator_consumer_supply __initdata max8997_buck1_[] = {
-        REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
-};
-static struct regulator_consumer_supply __initdata max8997_buck2_[] = {
-        REGULATOR_SUPPLY("vdd_int", "exynos4210-busfreq.0"), /* CPUFREQ */
-};
-static struct regulator_consumer_supply __initdata max8997_buck3_[] = {
-        REGULATOR_SUPPLY("vdd", "mali_dev.0"), /* G3D of Exynos 4 */
-};
-static struct regulator_consumer_supply __initdata max8997_buck4_[] = {
-        REGULATOR_SUPPLY("core", "0-001f"), /* HDC803 */
-};
-static struct regulator_consumer_supply __initdata max8997_buck6_[] = {
-        REGULATOR_SUPPLY("dig_28", "0-001f"), /* pin "7" of HDC803 */
-};
-static struct regulator_consumer_supply __initdata max8997_esafeout1_[] = {
-        REGULATOR_SUPPLY("usb_vbus", NULL), /* CPU's USB OTG */
-};
-static struct regulator_consumer_supply __initdata max8997_esafeout2_[] = {
-        REGULATOR_SUPPLY("usb_vbus", "modemctl"), /* VBUS of Modem */
-};
-
-static struct regulator_consumer_supply __initdata max8997_charger_[] = {
-        REGULATOR_SUPPLY("vinchg1", "charger-manager.0"),
-};
-static struct regulator_consumer_supply __initdata max8997_chg_toff_[] = {
-        REGULATOR_SUPPLY("vinchg_stop", NULL), /* for jack interrupt handlers */
-};
-
-static struct regulator_consumer_supply __initdata max8997_32khz_ap_[] = {
-        REGULATOR_SUPPLY("gps_clk", "bcm4751"),
-        REGULATOR_SUPPLY("bt_clk", "bcm4330-b1"),
-        REGULATOR_SUPPLY("wifi_clk", "bcm433-b1"),
-};
-
-static struct regulator_init_data __initdata max8997_ldo1_data = {
-        .constraints    = {
-                .name           = "VADC_3.3V_C210",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo1_),
-        .consumer_supplies      = max8997_ldo1_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo2_data = {
-        .constraints    = {
-                .name           = "VALIVE_1.1V_C210",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_ldo3_data = {
-        .constraints    = {
-                .name           = "VUSB_1.1V_C210",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo3_),
-        .consumer_supplies      = max8997_ldo3_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo4_data = {
-        .constraints    = {
-                .name           = "VMIPI_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo4_),
-        .consumer_supplies      = max8997_ldo4_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo5_data = {
-        .constraints    = {
-                .name           = "VHSIC_1.2V_C210",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo5_),
-        .consumer_supplies      = max8997_ldo5_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo6_data = {
-        .constraints    = {
-                .name           = "VCC_1.8V_PDA",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(nuri_max8997_ldo6_consumer),
-        .consumer_supplies      = nuri_max8997_ldo6_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo7_data = {
-        .constraints    = {
-                .name           = "CAM_ISP_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo7_),
-        .consumer_supplies      = max8997_ldo7_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo8_data = {
-        .constraints    = {
-                .name           = "VUSB+VDAC_3.3V_C210",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo8_),
-        .consumer_supplies      = max8997_ldo8_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo9_data = {
-        .constraints    = {
-                .name           = "VCC_2.8V_PDA",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_ldo10_data = {
-        .constraints    = {
-                .name           = "VPLL_1.1V_C210",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_ldo11_data = {
-        .constraints    = {
-                .name           = "LVDS_VDD3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .boot_on        = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo11_),
-        .consumer_supplies      = max8997_ldo11_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo12_data = {
-        .constraints    = {
-                .name           = "VT_CAM_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo12_),
-        .consumer_supplies      = max8997_ldo12_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo13_data = {
-        .constraints    = {
-                .name           = "VTF_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo13_),
-        .consumer_supplies      = max8997_ldo13_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo14_data = {
-        .constraints    = {
-                .name           = "VCC_3.0V_MOTOR",
-                .min_uV         = 3000000,
-                .max_uV         = 3000000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo14_),
-        .consumer_supplies      = max8997_ldo14_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo15_data = {
-        .constraints    = {
-                .name           = "VTOUCH_ADVV2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo15_),
-        .consumer_supplies      = max8997_ldo15_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo16_data = {
-        .constraints    = {
-                .name           = "CAM_SENSOR_IO_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo16_),
-        .consumer_supplies      = max8997_ldo16_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo18_data = {
-        .constraints    = {
-                .name           = "VTOUCH_VDD2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo18_),
-        .consumer_supplies      = max8997_ldo18_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo21_data = {
-        .constraints    = {
-                .name           = "VDDQ_M1M2_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_buck1_data = {
-        .constraints    = {
-                .name           = "VARM_1.2V_C210",
-                .min_uV         = 900000,
-                .max_uV         = 1350000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(max8997_buck1_),
-        .consumer_supplies = max8997_buck1_,
-};
-
-static struct regulator_init_data __initdata max8997_buck2_data = {
-        .constraints    = {
-                .name           = "VINT_1.1V_C210",
-                .min_uV         = 900000,
-                .max_uV         = 1200000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(max8997_buck2_),
-        .consumer_supplies = max8997_buck2_,
-};
-
-static struct regulator_init_data __initdata max8997_buck3_data = {
-        .constraints    = {
-                .name           = "VG3D_1.1V_C210",
-                .min_uV         = 900000,
-                .max_uV         = 1100000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                                  REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(max8997_buck3_),
-        .consumer_supplies = max8997_buck3_,
-};
-
-static struct regulator_init_data __initdata max8997_buck4_data = {
-        .constraints    = {
-                .name           = "CAM_ISP_CORE_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(max8997_buck4_),
-        .consumer_supplies = max8997_buck4_,
-};
-
-static struct regulator_init_data __initdata max8997_buck5_data = {
-        .constraints    = {
-                .name           = "VMEM_1.2V_C210",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_buck6_data = {
-        .constraints    = {
-                .name           = "CAM_AF_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(max8997_buck6_),
-        .consumer_supplies = max8997_buck6_,
-};
-
-static struct regulator_init_data __initdata max8997_buck7_data = {
-        .constraints    = {
-                .name           = "VCC_SUB_2.0V",
-                .min_uV         = 2000000,
-                .max_uV         = 2000000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_32khz_ap_data = {
-        .constraints    = {
-                .name           = "32KHz AP",
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(max8997_32khz_ap_),
-        .consumer_supplies = max8997_32khz_ap_,
-};
-
-static struct regulator_init_data __initdata max8997_32khz_cp_data = {
-        .constraints    = {
-                .name           = "32KHz CP",
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_vichg_data = {
-        .constraints    = {
-                .name           = "VICHG",
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_esafeout1_data = {
-        .constraints    = {
-                .name           = "SAFEOUT1",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_esafeout1_),
-        .consumer_supplies      = max8997_esafeout1_,
-};
-
-static struct regulator_init_data __initdata max8997_esafeout2_data = {
-        .constraints    = {
-                .name           = "SAFEOUT2",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_esafeout2_),
-        .consumer_supplies      = max8997_esafeout2_,
-};
-
-static struct regulator_init_data __initdata max8997_charger_cv_data = {
-        .constraints    = {
-                .name           = "CHARGER_CV",
-                .min_uV         = 4200000,
-                .max_uV         = 4200000,
-                .apply_uV       = 1,
-        },
-};
-
-static struct regulator_init_data __initdata max8997_charger_data = {
-        .constraints    = {
-                .name           = "CHARGER",
-                .min_uA         = 200000,
-                .max_uA         = 950000,
-                .boot_on        = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS |
-                                REGULATOR_CHANGE_CURRENT,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_charger_),
-        .consumer_supplies      = max8997_charger_,
-};
-
-static struct regulator_init_data __initdata max8997_charger_topoff_data = {
-        .constraints    = {
-                .name           = "CHARGER TOPOFF",
-                .min_uA         = 50000,
-                .max_uA         = 200000,
-                .valid_ops_mask = REGULATOR_CHANGE_CURRENT,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_chg_toff_),
-        .consumer_supplies      = max8997_chg_toff_,
-};
-
-static struct max8997_regulator_data __initdata nuri_max8997_regulators[] = {
-        { MAX8997_LDO1, &max8997_ldo1_data },
-        { MAX8997_LDO2, &max8997_ldo2_data },
-        { MAX8997_LDO3, &max8997_ldo3_data },
-        { MAX8997_LDO4, &max8997_ldo4_data },
-        { MAX8997_LDO5, &max8997_ldo5_data },
-        { MAX8997_LDO6, &max8997_ldo6_data },
-        { MAX8997_LDO7, &max8997_ldo7_data },
-        { MAX8997_LDO8, &max8997_ldo8_data },
-        { MAX8997_LDO9, &max8997_ldo9_data },
-        { MAX8997_LDO10, &max8997_ldo10_data },
-        { MAX8997_LDO11, &max8997_ldo11_data },
-        { MAX8997_LDO12, &max8997_ldo12_data },
-        { MAX8997_LDO13, &max8997_ldo13_data },
-        { MAX8997_LDO14, &max8997_ldo14_data },
-        { MAX8997_LDO15, &max8997_ldo15_data },
-        { MAX8997_LDO16, &max8997_ldo16_data },
-
-        { MAX8997_LDO18, &max8997_ldo18_data },
-        { MAX8997_LDO21, &max8997_ldo21_data },
-
-        { MAX8997_BUCK1, &max8997_buck1_data },
-        { MAX8997_BUCK2, &max8997_buck2_data },
-        { MAX8997_BUCK3, &max8997_buck3_data },
-        { MAX8997_BUCK4, &max8997_buck4_data },
-        { MAX8997_BUCK5, &max8997_buck5_data },
-        { MAX8997_BUCK6, &max8997_buck6_data },
-        { MAX8997_BUCK7, &max8997_buck7_data },
-
-        { MAX8997_EN32KHZ_AP, &max8997_32khz_ap_data },
-        { MAX8997_EN32KHZ_CP, &max8997_32khz_cp_data },
-
-        { MAX8997_ENVICHG, &max8997_vichg_data },
-        { MAX8997_ESAFEOUT1, &max8997_esafeout1_data },
-        { MAX8997_ESAFEOUT2, &max8997_esafeout2_data },
-        { MAX8997_CHARGER_CV, &max8997_charger_cv_data },
-        { MAX8997_CHARGER, &max8997_charger_data },
-        { MAX8997_CHARGER_TOPOFF, &max8997_charger_topoff_data },
-};
-
-static struct max8997_platform_data __initdata nuri_max8997_pdata = {
-        .wakeup                 = 1,
-
-        .num_regulators         = ARRAY_SIZE(nuri_max8997_regulators),
-        .regulators             = nuri_max8997_regulators,
-
-        .buck125_gpios = { EXYNOS4_GPX0(5), EXYNOS4_GPX0(6), EXYNOS4_GPL0(0) },
-
-        .buck1_voltage[0] = 1350000, /* 1.35V */
-        .buck1_voltage[1] = 1300000, /* 1.3V */
-        .buck1_voltage[2] = 1250000, /* 1.25V */
-        .buck1_voltage[3] = 1200000, /* 1.2V */
-        .buck1_voltage[4] = 1150000, /* 1.15V */
-        .buck1_voltage[5] = 1100000, /* 1.1V */
-        .buck1_voltage[6] = 1000000, /* 1.0V */
-        .buck1_voltage[7] = 950000, /* 0.95V */
-
-        .buck2_voltage[0] = 1100000, /* 1.1V */
-        .buck2_voltage[1] = 1000000, /* 1.0V */
-        .buck2_voltage[2] = 950000, /* 0.95V */
-        .buck2_voltage[3] = 900000, /* 0.9V */
-        .buck2_voltage[4] = 1100000, /* 1.1V */
-        .buck2_voltage[5] = 1000000, /* 1.0V */
-        .buck2_voltage[6] = 950000, /* 0.95V */
-        .buck2_voltage[7] = 900000, /* 0.9V */
-
-        .buck5_voltage[0] = 1200000, /* 1.2V */
-        .buck5_voltage[1] = 1200000, /* 1.2V */
-        .buck5_voltage[2] = 1200000, /* 1.2V */
-        .buck5_voltage[3] = 1200000, /* 1.2V */
-        .buck5_voltage[4] = 1200000, /* 1.2V */
-        .buck5_voltage[5] = 1200000, /* 1.2V */
-        .buck5_voltage[6] = 1200000, /* 1.2V */
-        .buck5_voltage[7] = 1200000, /* 1.2V */
-};
-
-/* GPIO I2C 5 (PMIC) */
-enum { I2C5_MAX8997 };
-static struct i2c_board_info i2c5_devs[] __initdata = {
-        [I2C5_MAX8997] = {
-                I2C_BOARD_INFO("max8997", 0xCC >> 1),
-                .platform_data  = &nuri_max8997_pdata,
-        },
-};
-
-static struct max17042_platform_data nuri_battery_platform_data = {
-};
-
-/* GPIO I2C 9 (Fuel Gauge) */
-static struct i2c_gpio_platform_data i2c9_gpio_data = {
-        .sda_pin                = EXYNOS4_GPY4(0),      /* XM0ADDR_8 */
-        .scl_pin                = EXYNOS4_GPY4(1),      /* XM0ADDR_9 */
-};
-static struct platform_device i2c9_gpio = {
-        .name                   = "i2c-gpio",
-        .id                     = 9,
-        .dev                    = {
-                .platform_data  = &i2c9_gpio_data,
-        },
-};
-enum { I2C9_MAX17042};
-static struct i2c_board_info i2c9_devs[] __initdata = {
-        [I2C9_MAX17042] = {
-                I2C_BOARD_INFO("max17042", 0x36),
-                .platform_data = &nuri_battery_platform_data,
-        },
-};
-
-/* MAX8903 Secondary Charger */
-static struct regulator_consumer_supply supplies_max8903[] = {
-        REGULATOR_SUPPLY("vinchg2", "charger-manager.0"),
-};
-
-static struct regulator_init_data max8903_charger_en_data = {
-        .constraints = {
-                .name           = "VOUT_CHARGER",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .boot_on        = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(supplies_max8903),
-        .consumer_supplies = supplies_max8903,
-};
-
-static struct fixed_voltage_config max8903_charger_en = {
-        .supply_name = "VOUT_CHARGER",
-        .microvolts = 5000000, /* Assume 5VDC */
-        .gpio = EXYNOS4_GPY4(5), /* TA_EN negaged */
-        .enable_high = 0, /* Enable = Low */
-        .enabled_at_boot = 1,
-        .init_data = &max8903_charger_en_data,
-};
-
-static struct platform_device max8903_fixed_reg_dev = {
-        .name = "reg-fixed-voltage",
-        .id = FIXED_REG_ID_MAX8903,
-        .dev = { .platform_data = &max8903_charger_en },
-};
-
-static struct max8903_pdata nuri_max8903 = {
-        /*
-         * cen: don't control with the driver, let it be
-         * controlled by regulator above
-         */
-        .dok = EXYNOS4_GPX1(4), /* TA_nCONNECTED */
-        /* uok, usus: not connected */
-        .chg = EXYNOS4_GPE2(0), /* TA_nCHG */
-        /* flt: vcc_1.8V_pda */
-        .dcm = EXYNOS4_GPL0(1), /* CURR_ADJ */
-
-        .dc_valid = true,
-        .usb_valid = false, /* USB is not wired to MAX8903 */
-};
-
-static struct platform_device nuri_max8903_device = {
-        .name                   = "max8903-charger",
-        .dev                    = {
-                .platform_data  = &nuri_max8903,
-        },
-};
-
-static void __init nuri_power_init(void)
-{
-        int gpio;
-        int ta_en = 0;
-
-        gpio = EXYNOS4_GPX0(7);
-        gpio_request(gpio, "AP_PMIC_IRQ");
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-
-        gpio = EXYNOS4_GPX2(3);
-        gpio_request(gpio, "FUEL_ALERT");
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-
-        gpio = nuri_max8903.dok;
-        gpio_request(gpio, "TA_nCONNECTED");
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        ta_en = gpio_get_value(gpio) ? 0 : 1;
-
-        gpio = nuri_max8903.chg;
-        gpio_request(gpio, "TA_nCHG");
-        gpio_direction_input(gpio);
-
-        gpio = nuri_max8903.dcm;
-        gpio_request(gpio, "CURR_ADJ");
-        gpio_direction_output(gpio, ta_en);
-}
-
-/* USB EHCI */
-static struct s5p_ehci_platdata nuri_ehci_pdata;
-
-static void __init nuri_ehci_init(void)
-{
-        struct s5p_ehci_platdata *pdata = &nuri_ehci_pdata;
-
-        s5p_ehci_set_platdata(pdata);
-}
-
-/* USB OTG */
-static struct s3c_hsotg_plat nuri_hsotg_pdata;
-
-/* CAMERA */
-static struct regulator_consumer_supply cam_vt_cam15_supply =
-        REGULATOR_SUPPLY("vdd_core", "6-003c");
-
-static struct regulator_init_data cam_vt_cam15_reg_init_data = {
-        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &cam_vt_cam15_supply,
-};
-
-static struct fixed_voltage_config cam_vt_cam15_fixed_voltage_cfg = {
-        .supply_name    = "VT_CAM_1.5V",
-        .microvolts     = 1500000,
-        .gpio           = EXYNOS4_GPE2(2), /* VT_CAM_1.5V_EN */
-        .enable_high    = 1,
-        .init_data      = &cam_vt_cam15_reg_init_data,
-};
-
-static struct platform_device cam_vt_cam15_fixed_rdev = {
-        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_15V,
-        .dev = { .platform_data = &cam_vt_cam15_fixed_voltage_cfg },
-};
-
-static struct regulator_consumer_supply cam_vdda_supply[] = {
-        REGULATOR_SUPPLY("vdda", "6-003c"),
-        REGULATOR_SUPPLY("a_sensor", "0-001f"),
-};
-
-static struct regulator_init_data cam_vdda_reg_init_data = {
-        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
-        .num_consumer_supplies = ARRAY_SIZE(cam_vdda_supply),
-        .consumer_supplies = cam_vdda_supply,
-};
-
-static struct fixed_voltage_config cam_vdda_fixed_voltage_cfg = {
-        .supply_name    = "CAM_IO_EN",
-        .microvolts     = 2800000,
-        .gpio           = EXYNOS4_GPE2(1), /* CAM_IO_EN */
-        .enable_high    = 1,
-        .init_data      = &cam_vdda_reg_init_data,
-};
-
-static struct platform_device cam_vdda_fixed_rdev = {
-        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_A28V,
-        .dev = { .platform_data = &cam_vdda_fixed_voltage_cfg },
-};
-
-static struct regulator_consumer_supply camera_8m_12v_supply =
-        REGULATOR_SUPPLY("dig_12", "0-001f");
-
-static struct regulator_init_data cam_8m_12v_reg_init_data = {
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &camera_8m_12v_supply,
-        .constraints = {
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS
-        },
-};
-
-static struct fixed_voltage_config cam_8m_12v_fixed_voltage_cfg = {
-        .supply_name    = "8M_1.2V",
-        .microvolts     = 1200000,
-        .gpio           = EXYNOS4_GPE2(5), /* 8M_1.2V_EN */
-        .enable_high    = 1,
-        .init_data      = &cam_8m_12v_reg_init_data,
-};
-
-static struct platform_device cam_8m_12v_fixed_rdev = {
-        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_12V,
-        .dev = { .platform_data = &cam_8m_12v_fixed_voltage_cfg },
-};
-
-static struct s5p_platform_mipi_csis mipi_csis_platdata = {
-        .clk_rate       = 166000000UL,
-        .lanes          = 2,
-        .hs_settle      = 12,
-};
-
-#define GPIO_CAM_MEGA_RST       EXYNOS4_GPY3(7) /* ISP_RESET */
-#define GPIO_CAM_8M_ISP_INT     EXYNOS4_GPL2(5)
-#define GPIO_CAM_VT_NSTBY       EXYNOS4_GPL2(0)
-#define GPIO_CAM_VT_NRST        EXYNOS4_GPL2(1)
-
-static struct s5k6aa_platform_data s5k6aa_pldata = {
-        .mclk_frequency = 24000000UL,
-        .gpio_reset     = { GPIO_CAM_VT_NRST, 0 },
-        .gpio_stby      = { GPIO_CAM_VT_NSTBY, 0 },
-        .bus_type       = V4L2_MBUS_PARALLEL,
-        .horiz_flip     = 1,
-};
-
-static struct i2c_board_info s5k6aa_board_info = {
-        I2C_BOARD_INFO("S5K6AA", 0x3c),
-        .platform_data = &s5k6aa_pldata,
-};
-
-static struct m5mols_platform_data m5mols_platdata = {
-        .gpio_reset = GPIO_CAM_MEGA_RST,
-};
-
-static struct i2c_board_info m5mols_board_info = {
-        I2C_BOARD_INFO("M5MOLS", 0x1F),
-        .platform_data  = &m5mols_platdata,
-};
-
-static struct fimc_source_info nuri_camera_sensors[] = {
-        {
-                .flags          = V4L2_MBUS_PCLK_SAMPLE_RISING |
-                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
-                .fimc_bus_type  = FIMC_BUS_TYPE_ITU_601,
-                .board_info     = &s5k6aa_board_info,
-                .clk_frequency  = 24000000UL,
-                .i2c_bus_num    = 6,
-        }, {
-                .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
-                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
-                .fimc_bus_type  = FIMC_BUS_TYPE_MIPI_CSI2,
-                .board_info     = &m5mols_board_info,
-                .clk_frequency  = 24000000UL,
-        },
-};
-
-static struct s5p_platform_fimc fimc_md_platdata = {
-        .source_info    = nuri_camera_sensors,
-        .num_clients    = ARRAY_SIZE(nuri_camera_sensors),
-};
-
-static struct gpio nuri_camera_gpios[] = {
-        { GPIO_CAM_VT_NSTBY,    GPIOF_OUT_INIT_LOW, "CAM_VGA_NSTBY" },
-        { GPIO_CAM_VT_NRST,     GPIOF_OUT_INIT_LOW, "CAM_VGA_NRST"  },
-        { GPIO_CAM_8M_ISP_INT,  GPIOF_IN,           "8M_ISP_INT"  },
-        { GPIO_CAM_MEGA_RST,    GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
-};
-
-static void __init nuri_camera_init(void)
-{
-        s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
-                         &s5p_device_mipi_csis0);
-        s3c_set_platdata(&fimc_md_platdata,  sizeof(fimc_md_platdata),
-                         &s5p_device_fimc_md);
-
-        if (gpio_request_array(nuri_camera_gpios,
-                               ARRAY_SIZE(nuri_camera_gpios))) {
-                pr_err("%s: GPIO request failed\n", __func__);
-                return;
-        }
-
-        m5mols_board_info.irq = s5p_register_gpio_interrupt(GPIO_CAM_8M_ISP_INT);
-        if (m5mols_board_info.irq >= 0)
-                s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xF));
-        else
-                pr_err("%s: Failed to configure 8M_ISP_INT GPIO\n", __func__);
-
-        /* Free GPIOs controlled directly by the sensor drivers. */
-        gpio_free(GPIO_CAM_VT_NRST);
-        gpio_free(GPIO_CAM_VT_NSTBY);
-        gpio_free(GPIO_CAM_MEGA_RST);
-
-        if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) {
-                pr_err("%s: Camera port A setup failed\n", __func__);
-                return;
-        }
-        /* Increase drive strength of the sensor clock output */
-        s5p_gpio_set_drvstr(EXYNOS4_GPJ1(3), S5P_GPIO_DRVSTR_LV4);
-}
-
-static struct s3c2410_platform_i2c nuri_i2c6_platdata __initdata = {
-        .frequency      = 400000U,
-        .sda_delay      = 200,
-        .bus_num        = 6,
-};
-
-static struct s3c2410_platform_i2c nuri_i2c0_platdata __initdata = {
-        .frequency      = 400000U,
-        .sda_delay      = 200,
-};
-
-/* DEVFREQ controlling memory/bus */
-static struct platform_device exynos4_bus_devfreq = {
-        .name                   = "exynos4210-busfreq",
-};
-
-static struct platform_device *nuri_devices[] __initdata = {
-        /* Samsung Platform Devices */
-        &s3c_device_i2c5, /* PMIC should initialize first */
-        &s3c_device_i2c0,
-        &s3c_device_i2c6,
-        &emmc_fixed_voltage,
-        &s5p_device_mipi_csis0,
-        &s5p_device_fimc0,
-        &s5p_device_fimc1,
-        &s5p_device_fimc2,
-        &s5p_device_fimc3,
-        &s5p_device_fimd0,
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-        &s3c_device_wdt,
-        &s3c_device_timer[0],
-        &s5p_device_ehci,
-        &s3c_device_i2c3,
-        &i2c9_gpio,
-        &s3c_device_adc,
-        &s5p_device_g2d,
-        &s5p_device_jpeg,
-        &s3c_device_rtc,
-        &s5p_device_mfc,
-        &s5p_device_mfc_l,
-        &s5p_device_mfc_r,
-        &s5p_device_fimc_md,
-        &s3c_device_usb_hsotg,
-
-        /* NURI Devices */
-        &nuri_gpio_keys,
-        &nuri_lcd_device,
-        &nuri_backlight_device,
-        &max8903_fixed_reg_dev,
-        &nuri_max8903_device,
-        &cam_vt_cam15_fixed_rdev,
-        &cam_vdda_fixed_rdev,
-        &cam_8m_12v_fixed_rdev,
-        &exynos4_bus_devfreq,
-};
-
-static void __init nuri_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-        s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
-        xxti_f = 0;
-        xusbxti_f = 24000000;
-}
-
-static void __init nuri_reserve(void)
-{
-        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-
-static void __init nuri_machine_init(void)
-{
-        nuri_sdhci_init();
-        nuri_tsp_init();
-        nuri_power_init();
-
-        s3c_i2c0_set_platdata(&nuri_i2c0_platdata);
-        i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
-        s3c_i2c3_set_platdata(&i2c3_data);
-        i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
-        s3c_i2c5_set_platdata(NULL);
-        i2c5_devs[I2C5_MAX8997].irq = gpio_to_irq(EXYNOS4_GPX0(7));
-        i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
-        i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
-        i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
-        s3c_i2c6_set_platdata(&nuri_i2c6_platdata);
-
-#ifdef CONFIG_DRM_EXYNOS
-        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
-        exynos4_fimd0_gpio_setup_24bpp();
-#else
-        s5p_fimd0_set_platdata(&nuri_fb_pdata);
-#endif
-
-        nuri_camera_init();
-
-        nuri_ehci_init();
-        s3c_hsotg_set_platdata(&nuri_hsotg_pdata);
-
-        /* Last */
-        platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
-}
-
-MACHINE_START(NURI, "NURI")
-        /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = nuri_map_io,
-        .init_machine   = nuri_machine_init,
-        .init_late      = exynos_init_late,
-        .init_time      = exynos_init_time,
-        .reserve        = &nuri_reserve,
-        .restart        = exynos4_restart,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
deleted file mode 100644
index 27f03ed5d067..000000000000
--- a/arch/arm/mach-exynos/mach-origen.c
+++ /dev/null
@@ -1,823 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mach-origen.c
- *
- * Copyright (c) 2011 Insignal Co., Ltd.
- *              http://www.insignal.co.kr/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/serial_core.h>
-#include <linux/leds.h>
-#include <linux/gpio.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/input.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/gpio_keys.h>
-#include <linux/i2c.h>
-#include <linux/regulator/machine.h>
-#include <linux/mfd/max8997.h>
-#include <linux/lcd.h>
-#include <linux/rfkill-gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/s3c-hsotg.h>
-#include <linux/platform_data/usb-ehci-s5p.h>
-#include <linux/platform_data/usb-ohci-exynos.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <video/platform_lcd.h>
-#include <video/samsung_fimd.h>
-
-#include <plat/regs-serial.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/sdhci.h>
-#include <plat/clock.h>
-#include <plat/gpio-cfg.h>
-#include <plat/backlight.h>
-#include <plat/fb.h>
-#include <plat/mfc.h>
-#include <plat/hdmi.h>
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-
-#include <drm/exynos_drm.h>
-#include "common.h"
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define ORIGEN_UCON_DEFAULT     (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define ORIGEN_ULCON_DEFAULT    S3C2410_LCON_CS8
-
-#define ORIGEN_UFCON_DEFAULT    (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-
-static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = ORIGEN_UCON_DEFAULT,
-                .ulcon          = ORIGEN_ULCON_DEFAULT,
-                .ufcon          = ORIGEN_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = ORIGEN_UCON_DEFAULT,
-                .ulcon          = ORIGEN_ULCON_DEFAULT,
-                .ufcon          = ORIGEN_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = ORIGEN_UCON_DEFAULT,
-                .ulcon          = ORIGEN_ULCON_DEFAULT,
-                .ufcon          = ORIGEN_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = ORIGEN_UCON_DEFAULT,
-                .ulcon          = ORIGEN_ULCON_DEFAULT,
-                .ufcon          = ORIGEN_UFCON_DEFAULT,
-        },
-};
-
-static struct regulator_consumer_supply __initdata ldo3_consumer[] = {
-        REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */
-        REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */
-        REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */
-        REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), /* OTG */
-};
-static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
-        REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */
-};
-static struct regulator_consumer_supply __initdata ldo7_consumer[] = {
-        REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */
-};
-static struct regulator_consumer_supply __initdata ldo8_consumer[] = {
-        REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */
-        REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), /* HDMI */
-        REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* OTG */
-};
-static struct regulator_consumer_supply __initdata ldo9_consumer[] = {
-        REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
-};
-static struct regulator_consumer_supply __initdata ldo11_consumer[] = {
-        REGULATOR_SUPPLY("dvdd", "alc5625"), /* Realtek ALC5625 */
-};
-static struct regulator_consumer_supply __initdata ldo14_consumer[] = {
-        REGULATOR_SUPPLY("avdd18", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
-};
-static struct regulator_consumer_supply __initdata ldo17_consumer[] = {
-        REGULATOR_SUPPLY("vdd33", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
-};
-static struct regulator_consumer_supply __initdata buck1_consumer[] = {
-        REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
-};
-static struct regulator_consumer_supply __initdata buck2_consumer[] = {
-        REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
-};
-static struct regulator_consumer_supply __initdata buck3_consumer[] = {
-        REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */
-};
-static struct regulator_consumer_supply __initdata buck7_consumer[] = {
-        REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */
-};
-
-static struct regulator_init_data __initdata max8997_ldo1_data = {
-        .constraints    = {
-                .name           = "VDD_ABB_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_ldo2_data  = {
-        .constraints    = {
-                .name           = "VDD_ALIVE_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_ldo3_data = {
-        .constraints    = {
-                .name           = "VMIPI_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo3_consumer),
-        .consumer_supplies      = ldo3_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo4_data = {
-        .constraints    = {
-                .name           = "VDD_RTC_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_ldo6_data = {
-        .constraints    = {
-                .name           = "VMIPI_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo6_consumer),
-        .consumer_supplies      = ldo6_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo7_data = {
-        .constraints    = {
-                .name           = "VDD_AUD_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo7_consumer),
-        .consumer_supplies      = ldo7_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo8_data = {
-        .constraints    = {
-                .name           = "VADC_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo8_consumer),
-        .consumer_supplies      = ldo8_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo9_data = {
-        .constraints    = {
-                .name           = "DVDD_SWB_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo9_consumer),
-        .consumer_supplies      = ldo9_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo10_data = {
-        .constraints    = {
-                .name           = "VDD_PLL_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_ldo11_data = {
-        .constraints    = {
-                .name           = "VDD_AUD_3V",
-                .min_uV         = 3000000,
-                .max_uV         = 3000000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo11_consumer),
-        .consumer_supplies      = ldo11_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo14_data = {
-        .constraints    = {
-                .name           = "AVDD18_SWB_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo14_consumer),
-        .consumer_supplies      = ldo14_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo17_data = {
-        .constraints    = {
-                .name           = "VDD_SWB_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo17_consumer),
-        .consumer_supplies      = ldo17_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo21_data = {
-        .constraints    = {
-                .name           = "VDD_MIF_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_buck1_data = {
-        .constraints    = {
-                .name           = "VDD_ARM_1.2V",
-                .min_uV         = 950000,
-                .max_uV         = 1350000,
-                .always_on      = 1,
-                .boot_on        = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(buck1_consumer),
-        .consumer_supplies      = buck1_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_buck2_data = {
-        .constraints    = {
-                .name           = "VDD_INT_1.1V",
-                .min_uV         = 900000,
-                .max_uV         = 1100000,
-                .always_on      = 1,
-                .boot_on        = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(buck2_consumer),
-        .consumer_supplies      = buck2_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_buck3_data = {
-        .constraints    = {
-                .name           = "VDD_G3D_1.1V",
-                .min_uV         = 900000,
-                .max_uV         = 1100000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                                        REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(buck3_consumer),
-        .consumer_supplies      = buck3_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_buck5_data = {
-        .constraints    = {
-                .name           = "VDDQ_M1M2_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_buck7_data = {
-        .constraints    = {
-                .name           = "VDD_LCD_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .boot_on        = 1,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(buck7_consumer),
-        .consumer_supplies      = buck7_consumer,
-};
-
-static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
-        { MAX8997_LDO1,         &max8997_ldo1_data },
-        { MAX8997_LDO2,         &max8997_ldo2_data },
-        { MAX8997_LDO3,         &max8997_ldo3_data },
-        { MAX8997_LDO4,         &max8997_ldo4_data },
-        { MAX8997_LDO6,         &max8997_ldo6_data },
-        { MAX8997_LDO7,         &max8997_ldo7_data },
-        { MAX8997_LDO8,         &max8997_ldo8_data },
-        { MAX8997_LDO9,         &max8997_ldo9_data },
-        { MAX8997_LDO10,        &max8997_ldo10_data },
-        { MAX8997_LDO11,        &max8997_ldo11_data },
-        { MAX8997_LDO14,        &max8997_ldo14_data },
-        { MAX8997_LDO17,        &max8997_ldo17_data },
-        { MAX8997_LDO21,        &max8997_ldo21_data },
-        { MAX8997_BUCK1,        &max8997_buck1_data },
-        { MAX8997_BUCK2,        &max8997_buck2_data },
-        { MAX8997_BUCK3,        &max8997_buck3_data },
-        { MAX8997_BUCK5,        &max8997_buck5_data },
-        { MAX8997_BUCK7,        &max8997_buck7_data },
-};
-
-static struct max8997_platform_data __initdata origen_max8997_pdata = {
-        .num_regulators = ARRAY_SIZE(origen_max8997_regulators),
-        .regulators     = origen_max8997_regulators,
-
-        .wakeup = true,
-        .buck1_gpiodvs  = false,
-        .buck2_gpiodvs  = false,
-        .buck5_gpiodvs  = false,
-
-        .ignore_gpiodvs_side_effect = true,
-        .buck125_default_idx = 0x0,
-
-        .buck125_gpios[0]       = EXYNOS4_GPX0(0),
-        .buck125_gpios[1]       = EXYNOS4_GPX0(1),
-        .buck125_gpios[2]       = EXYNOS4_GPX0(2),
-
-        .buck1_voltage[0]       = 1350000,
-        .buck1_voltage[1]       = 1300000,
-        .buck1_voltage[2]       = 1250000,
-        .buck1_voltage[3]       = 1200000,
-        .buck1_voltage[4]       = 1150000,
-        .buck1_voltage[5]       = 1100000,
-        .buck1_voltage[6]       = 1000000,
-        .buck1_voltage[7]       = 950000,
-
-        .buck2_voltage[0]       = 1100000,
-        .buck2_voltage[1]       = 1100000,
-        .buck2_voltage[2]       = 1100000,
-        .buck2_voltage[3]       = 1100000,
-        .buck2_voltage[4]       = 1000000,
-        .buck2_voltage[5]       = 1000000,
-        .buck2_voltage[6]       = 1000000,
-        .buck2_voltage[7]       = 1000000,
-
-        .buck5_voltage[0]       = 1200000,
-        .buck5_voltage[1]       = 1200000,
-        .buck5_voltage[2]       = 1200000,
-        .buck5_voltage[3]       = 1200000,
-        .buck5_voltage[4]       = 1200000,
-        .buck5_voltage[5]       = 1200000,
-        .buck5_voltage[6]       = 1200000,
-        .buck5_voltage[7]       = 1200000,
-};
-
-/* I2C0 */
-static struct i2c_board_info i2c0_devs[] __initdata = {
-        {
-                I2C_BOARD_INFO("max8997", (0xCC >> 1)),
-                .platform_data  = &origen_max8997_pdata,
-                .irq            = IRQ_EINT(4),
-        },
-};
-
-static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-};
-
-static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-};
-
-/* USB EHCI */
-static struct s5p_ehci_platdata origen_ehci_pdata;
-
-static void __init origen_ehci_init(void)
-{
-        struct s5p_ehci_platdata *pdata = &origen_ehci_pdata;
-
-        s5p_ehci_set_platdata(pdata);
-}
-
-/* USB OHCI */
-static struct exynos4_ohci_platdata origen_ohci_pdata;
-
-static void __init origen_ohci_init(void)
-{
-        struct exynos4_ohci_platdata *pdata = &origen_ohci_pdata;
-
-        exynos4_ohci_set_platdata(pdata);
-}
-
-/* USB OTG */
-static struct s3c_hsotg_plat origen_hsotg_pdata;
-
-static struct gpio_led origen_gpio_leds[] = {
-        {
-                .name                   = "origen::status1",
-                .default_trigger        = "heartbeat",
-                .gpio                   = EXYNOS4_GPX1(3),
-                .active_low             = 1,
-        },
-        {
-                .name                   = "origen::status2",
-                .default_trigger        = "mmc0",
-                .gpio                   = EXYNOS4_GPX1(4),
-                .active_low             = 1,
-        },
-};
-
-static struct gpio_led_platform_data origen_gpio_led_info = {
-        .leds           = origen_gpio_leds,
-        .num_leds       = ARRAY_SIZE(origen_gpio_leds),
-};
-
-static struct platform_device origen_leds_gpio = {
-        .name   = "leds-gpio",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &origen_gpio_led_info,
-        },
-};
-
-static struct gpio_keys_button origen_gpio_keys_table[] = {
-        {
-                .code                   = KEY_MENU,
-                .gpio                   = EXYNOS4_GPX1(5),
-                .desc                   = "gpio-keys: KEY_MENU",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .wakeup                 = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_HOME,
-                .gpio                   = EXYNOS4_GPX1(6),
-                .desc                   = "gpio-keys: KEY_HOME",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .wakeup                 = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_BACK,
-                .gpio                   = EXYNOS4_GPX1(7),
-                .desc                   = "gpio-keys: KEY_BACK",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .wakeup                 = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_UP,
-                .gpio                   = EXYNOS4_GPX2(0),
-                .desc                   = "gpio-keys: KEY_UP",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .wakeup                 = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_DOWN,
-                .gpio                   = EXYNOS4_GPX2(1),
-                .desc                   = "gpio-keys: KEY_DOWN",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .wakeup                 = 1,
-                .debounce_interval      = 1,
-        },
-};
-
-static struct gpio_keys_platform_data origen_gpio_keys_data = {
-        .buttons        = origen_gpio_keys_table,
-        .nbuttons       = ARRAY_SIZE(origen_gpio_keys_table),
-};
-
-static struct platform_device origen_device_gpiokeys = {
-        .name           = "gpio-keys",
-        .dev            = {
-                .platform_data  = &origen_gpio_keys_data,
-        },
-};
-
-static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power)
-{
-        int ret;
-
-        if (power)
-                ret = gpio_request_one(EXYNOS4_GPE3(4),
-                                        GPIOF_OUT_INIT_HIGH, "GPE3_4");
-        else
-                ret = gpio_request_one(EXYNOS4_GPE3(4),
-                                        GPIOF_OUT_INIT_LOW, "GPE3_4");
-
-        gpio_free(EXYNOS4_GPE3(4));
-
-        if (ret)
-                pr_err("failed to request gpio for LCD power: %d\n", ret);
-}
-
-static struct plat_lcd_data origen_lcd_hv070wsa_data = {
-        .set_power = lcd_hv070wsa_set_power,
-};
-
-static struct platform_device origen_lcd_hv070wsa = {
-        .name                   = "platform-lcd",
-        .dev.parent             = &s5p_device_fimd0.dev,
-        .dev.platform_data      = &origen_lcd_hv070wsa_data,
-};
-
-static struct pwm_lookup origen_pwm_lookup[] = {
-        PWM_LOOKUP("s3c24xx-pwm.0", 0, "pwm-backlight.0", NULL),
-};
-
-#ifdef CONFIG_DRM_EXYNOS_FIMD
-static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
-        .panel  = {
-                .timing = {
-                        .left_margin    = 64,
-                        .right_margin   = 16,
-                        .upper_margin   = 64,
-                        .lower_margin   = 16,
-                        .hsync_len      = 48,
-                        .vsync_len      = 3,
-                        .xres           = 1024,
-                        .yres           = 600,
-                },
-        },
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
-                                VIDCON1_INV_VCLK,
-        .default_win    = 0,
-        .bpp            = 32,
-};
-#else
-static struct s3c_fb_pd_win origen_fb_win0 = {
-        .xres                   = 1024,
-        .yres                   = 600,
-        .max_bpp                = 32,
-        .default_bpp            = 24,
-        .virtual_x              = 1024,
-        .virtual_y              = 2 * 600,
-};
-
-static struct fb_videomode origen_lcd_timing = {
-        .left_margin    = 64,
-        .right_margin   = 16,
-        .upper_margin   = 64,
-        .lower_margin   = 16,
-        .hsync_len      = 48,
-        .vsync_len      = 3,
-        .xres           = 1024,
-        .yres           = 600,
-};
-
-static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
-        .win[0]         = &origen_fb_win0,
-        .vtiming        = &origen_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
-                                VIDCON1_INV_VCLK,
-        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-#endif
-
-/* Bluetooth rfkill gpio platform data */
-static struct rfkill_gpio_platform_data origen_bt_pdata = {
-        .reset_gpio     = EXYNOS4_GPX2(2),
-        .shutdown_gpio  = -1,
-        .type           = RFKILL_TYPE_BLUETOOTH,
-        .name           = "origen-bt",
-};
-
-/* Bluetooth Platform device */
-static struct platform_device origen_device_bluetooth = {
-        .name           = "rfkill_gpio",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &origen_bt_pdata,
-        },
-};
-
-static struct platform_device *origen_devices[] __initdata = {
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc0,
-        &s3c_device_i2c0,
-        &s3c_device_rtc,
-        &s3c_device_usb_hsotg,
-        &s3c_device_wdt,
-        &s5p_device_ehci,
-        &s5p_device_fimc0,
-        &s5p_device_fimc1,
-        &s5p_device_fimc2,
-        &s5p_device_fimc3,
-        &s5p_device_fimc_md,
-        &s5p_device_fimd0,
-        &s5p_device_g2d,
-        &s5p_device_hdmi,
-        &s5p_device_i2c_hdmiphy,
-        &s5p_device_jpeg,
-        &s5p_device_mfc,
-        &s5p_device_mfc_l,
-        &s5p_device_mfc_r,
-        &s5p_device_mixer,
-        &exynos4_device_ohci,
-        &origen_device_gpiokeys,
-        &origen_lcd_hv070wsa,
-        &origen_leds_gpio,
-        &origen_device_bluetooth,
-};
-
-/* LCD Backlight data */
-static struct samsung_bl_gpio_info origen_bl_gpio_info = {
-        .no             = EXYNOS4_GPD0(0),
-        .func           = S3C_GPIO_SFN(2),
-};
-
-static struct platform_pwm_backlight_data origen_bl_data = {
-        .pwm_id         = 0,
-        .pwm_period_ns  = 1000,
-};
-
-static void __init origen_bt_setup(void)
-{
-        gpio_request(EXYNOS4_GPA0(0), "GPIO BT_UART");
-        /* 4 UART Pins configuration */
-        s3c_gpio_cfgrange_nopull(EXYNOS4_GPA0(0), 4, S3C_GPIO_SFN(2));
-        /* Setup BT Reset, this gpio will be requesed by rfkill-gpio */
-        s3c_gpio_cfgpin(EXYNOS4_GPX2(2), S3C_GPIO_OUTPUT);
-        s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE);
-}
-
-/* I2C module and id for HDMIPHY */
-static struct i2c_board_info hdmiphy_info = {
-        I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38),
-};
-
-static void s5p_tv_setup(void)
-{
-        /* Direct HPD to HDMI chip */
-        gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
-        s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
-        s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
-}
-
-static void __init origen_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-        s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
-        xxti_f = 0;
-        xusbxti_f = 24000000;
-}
-
-static void __init origen_power_init(void)
-{
-        gpio_request(EXYNOS4_GPX0(4), "PMIC_IRQ");
-        s3c_gpio_cfgpin(EXYNOS4_GPX0(4), S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE);
-}
-
-static void __init origen_reserve(void)
-{
-        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-
-static void __init origen_machine_init(void)
-{
-        origen_power_init();
-
-        s3c_i2c0_set_platdata(NULL);
-        i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
-
-        /*
-         * Since sdhci instance 2 can contain a bootable media,
-         * sdhci instance 0 is registered after instance 2.
-         */
-        s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata);
-        s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata);
-
-        origen_ehci_init();
-        origen_ohci_init();
-        s3c_hsotg_set_platdata(&origen_hsotg_pdata);
-
-        s5p_tv_setup();
-        s5p_i2c_hdmiphy_set_platdata(NULL);
-        s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0);
-
-#ifdef CONFIG_DRM_EXYNOS_FIMD
-        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
-        exynos4_fimd0_gpio_setup_24bpp();
-#else
-        s5p_fimd0_set_platdata(&origen_lcd_pdata);
-#endif
-
-        platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
-
-        pwm_add_table(origen_pwm_lookup, ARRAY_SIZE(origen_pwm_lookup));
-        samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
-
-        origen_bt_setup();
-}
-
-MACHINE_START(ORIGEN, "ORIGEN")
-        /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = origen_map_io,
-        .init_machine   = origen_machine_init,
-        .init_late      = exynos_init_late,
-        .init_time      = exynos_init_time,
-        .reserve        = &origen_reserve,
-        .restart        = exynos4_restart,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
deleted file mode 100644
index 2c8af9617920..000000000000
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ /dev/null
@@ -1,396 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/mach-smdk4x12.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/lcd.h>
-#include <linux/mfd/max8997.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/regulator/machine.h>
-#include <linux/serial_core.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/s3c-hsotg.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <video/samsung_fimd.h>
-#include <plat/backlight.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/fb.h>
-#include <plat/gpio-cfg.h>
-#include <plat/keypad.h>
-#include <plat/mfc.h>
-#include <plat/regs-serial.h>
-#include <plat/sdhci.h>
-
-#include <mach/irqs.h>
-#include <mach/map.h>
-
-#include <drm/exynos_drm.h>
-#include "common.h"
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define SMDK4X12_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define SMDK4X12_ULCON_DEFAULT  S3C2410_LCON_CS8
-
-#define SMDK4X12_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-
-static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = SMDK4X12_UCON_DEFAULT,
-                .ulcon          = SMDK4X12_ULCON_DEFAULT,
-                .ufcon          = SMDK4X12_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = SMDK4X12_UCON_DEFAULT,
-                .ulcon          = SMDK4X12_ULCON_DEFAULT,
-                .ufcon          = SMDK4X12_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = SMDK4X12_UCON_DEFAULT,
-                .ulcon          = SMDK4X12_ULCON_DEFAULT,
-                .ufcon          = SMDK4X12_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = SMDK4X12_UCON_DEFAULT,
-                .ulcon          = SMDK4X12_ULCON_DEFAULT,
-                .ufcon          = SMDK4X12_UFCON_DEFAULT,
-        },
-};
-
-static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
-        .max_width              = 8,
-        .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-
-static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-};
-
-static struct regulator_consumer_supply max8997_buck1 =
-        REGULATOR_SUPPLY("vdd_arm", NULL);
-
-static struct regulator_consumer_supply max8997_buck2 =
-        REGULATOR_SUPPLY("vdd_int", NULL);
-
-static struct regulator_consumer_supply max8997_buck3 =
-        REGULATOR_SUPPLY("vdd_g3d", NULL);
-
-static struct regulator_init_data max8997_buck1_data = {
-        .constraints    = {
-                .name           = "VDD_ARM_SMDK4X12",
-                .min_uV         = 925000,
-                .max_uV         = 1350000,
-                .always_on      = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &max8997_buck1,
-};
-
-static struct regulator_init_data max8997_buck2_data = {
-        .constraints    = {
-                .name           = "VDD_INT_SMDK4X12",
-                .min_uV         = 950000,
-                .max_uV         = 1150000,
-                .always_on      = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &max8997_buck2,
-};
-
-static struct regulator_init_data max8997_buck3_data = {
-        .constraints    = {
-                .name           = "VDD_G3D_SMDK4X12",
-                .min_uV         = 950000,
-                .max_uV         = 1150000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                                  REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &max8997_buck3,
-};
-
-static struct max8997_regulator_data smdk4x12_max8997_regulators[] = {
-        { MAX8997_BUCK1, &max8997_buck1_data },
-        { MAX8997_BUCK2, &max8997_buck2_data },
-        { MAX8997_BUCK3, &max8997_buck3_data },
-};
-
-static struct max8997_platform_data smdk4x12_max8997_pdata = {
-        .num_regulators = ARRAY_SIZE(smdk4x12_max8997_regulators),
-        .regulators     = smdk4x12_max8997_regulators,
-
-        .buck1_voltage[0] = 1100000,    /* 1.1V */
-        .buck1_voltage[1] = 1100000,    /* 1.1V */
-        .buck1_voltage[2] = 1100000,    /* 1.1V */
-        .buck1_voltage[3] = 1100000,    /* 1.1V */
-        .buck1_voltage[4] = 1100000,    /* 1.1V */
-        .buck1_voltage[5] = 1100000,    /* 1.1V */
-        .buck1_voltage[6] = 1000000,    /* 1.0V */
-        .buck1_voltage[7] = 950000,     /* 0.95V */
-
-        .buck2_voltage[0] = 1100000,    /* 1.1V */
-        .buck2_voltage[1] = 1000000,    /* 1.0V */
-        .buck2_voltage[2] = 950000,     /* 0.95V */
-        .buck2_voltage[3] = 900000,     /* 0.9V */
-        .buck2_voltage[4] = 1100000,    /* 1.1V */
-        .buck2_voltage[5] = 1000000,    /* 1.0V */
-        .buck2_voltage[6] = 950000,     /* 0.95V */
-        .buck2_voltage[7] = 900000,     /* 0.9V */
-
-        .buck5_voltage[0] = 1100000,    /* 1.1V */
-        .buck5_voltage[1] = 1100000,    /* 1.1V */
-        .buck5_voltage[2] = 1100000,    /* 1.1V */
-        .buck5_voltage[3] = 1100000,    /* 1.1V */
-        .buck5_voltage[4] = 1100000,    /* 1.1V */
-        .buck5_voltage[5] = 1100000,    /* 1.1V */
-        .buck5_voltage[6] = 1100000,    /* 1.1V */
-        .buck5_voltage[7] = 1100000,    /* 1.1V */
-};
-
-static struct i2c_board_info smdk4x12_i2c_devs0[] __initdata = {
-        {
-                I2C_BOARD_INFO("max8997", 0x66),
-                .platform_data  = &smdk4x12_max8997_pdata,
-        }
-};
-
-static struct i2c_board_info smdk4x12_i2c_devs1[] __initdata = {
-        { I2C_BOARD_INFO("wm8994", 0x1a), }
-};
-
-static struct i2c_board_info smdk4x12_i2c_devs3[] __initdata = {
-        /* nothing here yet */
-};
-
-static struct i2c_board_info smdk4x12_i2c_devs7[] __initdata = {
-        /* nothing here yet */
-};
-
-static struct samsung_bl_gpio_info smdk4x12_bl_gpio_info = {
-        .no = EXYNOS4_GPD0(1),
-        .func = S3C_GPIO_SFN(2),
-};
-
-static struct platform_pwm_backlight_data smdk4x12_bl_data = {
-        .pwm_id = 1,
-        .pwm_period_ns  = 1000,
-};
-
-static struct pwm_lookup smdk4x12_pwm_lookup[] = {
-        PWM_LOOKUP("s3c24xx-pwm.1", 0, "pwm-backlight.0", NULL),
-};
-
-static uint32_t smdk4x12_keymap[] __initdata = {
-        /* KEY(row, col, keycode) */
-        KEY(1, 3, KEY_1), KEY(1, 4, KEY_2), KEY(1, 5, KEY_3),
-        KEY(1, 6, KEY_4), KEY(1, 7, KEY_5),
-        KEY(2, 5, KEY_D), KEY(2, 6, KEY_A), KEY(2, 7, KEY_B),
-        KEY(0, 7, KEY_E), KEY(0, 5, KEY_C)
-};
-
-static struct matrix_keymap_data smdk4x12_keymap_data __initdata = {
-        .keymap         = smdk4x12_keymap,
-        .keymap_size    = ARRAY_SIZE(smdk4x12_keymap),
-};
-
-static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = {
-        .keymap_data    = &smdk4x12_keymap_data,
-        .rows           = 3,
-        .cols           = 8,
-};
-
-#ifdef CONFIG_DRM_EXYNOS_FIMD
-static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
-        .panel  = {
-                .timing = {
-                        .left_margin    = 8,
-                        .right_margin   = 8,
-                        .upper_margin   = 6,
-                        .lower_margin   = 6,
-                        .hsync_len      = 6,
-                        .vsync_len      = 4,
-                        .xres           = 480,
-                        .yres           = 800,
-                },
-        },
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .default_win    = 0,
-        .bpp            = 32,
-};
-#else
-static struct s3c_fb_pd_win smdk4x12_fb_win0 = {
-        .xres           = 480,
-        .yres           = 800,
-        .virtual_x      = 480,
-        .virtual_y      = 800 * 2,
-        .max_bpp        = 32,
-        .default_bpp    = 24,
-};
-
-static struct fb_videomode smdk4x12_lcd_timing = {
-        .left_margin    = 8,
-        .right_margin   = 8,
-        .upper_margin   = 6,
-        .lower_margin   = 6,
-        .hsync_len      = 6,
-        .vsync_len      = 4,
-        .xres           = 480,
-        .yres           = 800,
-};
-
-static struct s3c_fb_platdata smdk4x12_lcd_pdata __initdata = {
-        .win[0]         = &smdk4x12_fb_win0,
-        .vtiming        = &smdk4x12_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-#endif
-
-/* USB OTG */
-static struct s3c_hsotg_plat smdk4x12_hsotg_pdata;
-
-static struct platform_device *smdk4x12_devices[] __initdata = {
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-        &s3c_device_i2c0,
-        &s3c_device_i2c1,
-        &s3c_device_i2c3,
-        &s3c_device_i2c7,
-        &s3c_device_rtc,
-        &s3c_device_usb_hsotg,
-        &s3c_device_wdt,
-        &s5p_device_fimc0,
-        &s5p_device_fimc1,
-        &s5p_device_fimc2,
-        &s5p_device_fimc3,
-        &s5p_device_fimc_md,
-        &s5p_device_fimd0,
-        &s5p_device_mfc,
-        &s5p_device_mfc_l,
-        &s5p_device_mfc_r,
-        &samsung_device_keypad,
-};
-
-static void __init smdk4x12_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-        s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
-}
-
-static void __init smdk4x12_reserve(void)
-{
-        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-
-static void __init smdk4x12_machine_init(void)
-{
-        s3c_i2c0_set_platdata(NULL);
-        i2c_register_board_info(0, smdk4x12_i2c_devs0,
-                                ARRAY_SIZE(smdk4x12_i2c_devs0));
-
-        s3c_i2c1_set_platdata(NULL);
-        i2c_register_board_info(1, smdk4x12_i2c_devs1,
-                                ARRAY_SIZE(smdk4x12_i2c_devs1));
-
-        s3c_i2c3_set_platdata(NULL);
-        i2c_register_board_info(3, smdk4x12_i2c_devs3,
-                                ARRAY_SIZE(smdk4x12_i2c_devs3));
-
-        s3c_i2c7_set_platdata(NULL);
-        i2c_register_board_info(7, smdk4x12_i2c_devs7,
-                                ARRAY_SIZE(smdk4x12_i2c_devs7));
-
-        samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data);
-        pwm_add_table(smdk4x12_pwm_lookup, ARRAY_SIZE(smdk4x12_pwm_lookup));
-
-        samsung_keypad_set_platdata(&smdk4x12_keypad_data);
-
-        s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata);
-        s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata);
-
-        s3c_hsotg_set_platdata(&smdk4x12_hsotg_pdata);
-
-#ifdef CONFIG_DRM_EXYNOS_FIMD
-        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
-        exynos4_fimd0_gpio_setup_24bpp();
-#else
-        s5p_fimd0_set_platdata(&smdk4x12_lcd_pdata);
-#endif
-
-        platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices));
-}
-
-MACHINE_START(SMDK4212, "SMDK4212")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = smdk4x12_map_io,
-        .init_machine   = smdk4x12_machine_init,
-        .init_time      = exynos_init_time,
-        .restart        = exynos4_restart,
-        .reserve        = &smdk4x12_reserve,
-MACHINE_END
-
-MACHINE_START(SMDK4412, "SMDK4412")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = smdk4x12_map_io,
-        .init_machine   = smdk4x12_machine_init,
-        .init_late      = exynos_init_late,
-        .init_time      = exynos_init_time,
-        .restart        = exynos4_restart,
-        .reserve        = &smdk4x12_reserve,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
deleted file mode 100644
index d95b8cf85253..000000000000
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ /dev/null
@@ -1,444 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mach-smdkv310.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/serial_core.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/lcd.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/smsc911x.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/input.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/s3c-hsotg.h>
-#include <linux/platform_data/usb-ehci-s5p.h>
-#include <linux/platform_data/usb-ohci-exynos.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <video/platform_lcd.h>
-#include <video/samsung_fimd.h>
-#include <plat/regs-serial.h>
-#include <plat/regs-srom.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/fb.h>
-#include <plat/keypad.h>
-#include <plat/sdhci.h>
-#include <plat/gpio-cfg.h>
-#include <plat/backlight.h>
-#include <plat/mfc.h>
-#include <plat/clock.h>
-#include <plat/hdmi.h>
-
-#include <mach/irqs.h>
-#include <mach/map.h>
-
-#include <drm/exynos_drm.h>
-#include "common.h"
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define SMDKV310_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define SMDKV310_ULCON_DEFAULT  S3C2410_LCON_CS8
-
-#define SMDKV310_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-
-static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = SMDKV310_UCON_DEFAULT,
-                .ulcon          = SMDKV310_ULCON_DEFAULT,
-                .ufcon          = SMDKV310_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = SMDKV310_UCON_DEFAULT,
-                .ulcon          = SMDKV310_ULCON_DEFAULT,
-                .ufcon          = SMDKV310_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = SMDKV310_UCON_DEFAULT,
-                .ulcon          = SMDKV310_ULCON_DEFAULT,
-                .ufcon          = SMDKV310_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = SMDKV310_UCON_DEFAULT,
-                .ulcon          = SMDKV310_ULCON_DEFAULT,
-                .ufcon          = SMDKV310_UFCON_DEFAULT,
-        },
-};
-
-static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
-        .max_width              = 8,
-        .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-
-static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPK0(2),
-        .ext_cd_gpio_invert     = 1,
-};
-
-static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
-        .max_width              = 8,
-        .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-
-static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPK2(2),
-        .ext_cd_gpio_invert     = 1,
-};
-
-static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
-                                   unsigned int power)
-{
-        if (power) {
-#if !defined(CONFIG_BACKLIGHT_PWM)
-                gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
-                gpio_free(EXYNOS4_GPD0(1));
-#endif
-                /* fire nRESET on power up */
-                gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
-                mdelay(100);
-
-                gpio_set_value(EXYNOS4_GPX0(6), 0);
-                mdelay(10);
-
-                gpio_set_value(EXYNOS4_GPX0(6), 1);
-                mdelay(10);
-
-                gpio_free(EXYNOS4_GPX0(6));
-        } else {
-#if !defined(CONFIG_BACKLIGHT_PWM)
-                gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
-                gpio_free(EXYNOS4_GPD0(1));
-#endif
-        }
-}
-
-static struct plat_lcd_data smdkv310_lcd_lte480wv_data = {
-        .set_power              = lcd_lte480wv_set_power,
-};
-
-static struct platform_device smdkv310_lcd_lte480wv = {
-        .name                   = "platform-lcd",
-        .dev.parent             = &s5p_device_fimd0.dev,
-        .dev.platform_data      = &smdkv310_lcd_lte480wv_data,
-};
-
-#ifdef CONFIG_DRM_EXYNOS_FIMD
-static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
-        .panel  = {
-                .timing = {
-                        .left_margin    = 13,
-                        .right_margin   = 8,
-                        .upper_margin   = 7,
-                        .lower_margin   = 5,
-                        .hsync_len      = 3,
-                        .vsync_len      = 1,
-                        .xres           = 800,
-                        .yres           = 480,
-                },
-        },
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .default_win    = 0,
-        .bpp            = 32,
-};
-#else
-static struct s3c_fb_pd_win smdkv310_fb_win0 = {
-        .max_bpp        = 32,
-        .default_bpp    = 24,
-        .xres           = 800,
-        .yres           = 480,
-};
-
-static struct fb_videomode smdkv310_lcd_timing = {
-        .left_margin    = 13,
-        .right_margin   = 8,
-        .upper_margin   = 7,
-        .lower_margin   = 5,
-        .hsync_len      = 3,
-        .vsync_len      = 1,
-        .xres           = 800,
-        .yres           = 480,
-};
-
-static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
-        .win[0]         = &smdkv310_fb_win0,
-        .vtiming        = &smdkv310_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-#endif
-
-static struct resource smdkv310_smsc911x_resources[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(1), SZ_64K),
-        [1] = DEFINE_RES_NAMED(IRQ_EINT(5), 1, NULL, IORESOURCE_IRQ \
-                                                | IRQF_TRIGGER_LOW),
-};
-
-static struct smsc911x_platform_config smsc9215_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-        .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-        .mac            = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
-};
-
-static struct platform_device smdkv310_smsc911x = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(smdkv310_smsc911x_resources),
-        .resource       = smdkv310_smsc911x_resources,
-        .dev            = {
-                .platform_data  = &smsc9215_config,
-        },
-};
-
-static uint32_t smdkv310_keymap[] __initdata = {
-        /* KEY(row, col, keycode) */
-        KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
-        KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
-        KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
-        KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
-};
-
-static struct matrix_keymap_data smdkv310_keymap_data __initdata = {
-        .keymap         = smdkv310_keymap,
-        .keymap_size    = ARRAY_SIZE(smdkv310_keymap),
-};
-
-static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = {
-        .keymap_data    = &smdkv310_keymap_data,
-        .rows           = 2,
-        .cols           = 8,
-};
-
-static struct i2c_board_info i2c_devs1[] __initdata = {
-        {I2C_BOARD_INFO("wm8994", 0x1a),},
-};
-
-/* USB EHCI */
-static struct s5p_ehci_platdata smdkv310_ehci_pdata;
-
-static void __init smdkv310_ehci_init(void)
-{
-        struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata;
-
-        s5p_ehci_set_platdata(pdata);
-}
-
-/* USB OHCI */
-static struct exynos4_ohci_platdata smdkv310_ohci_pdata;
-
-static void __init smdkv310_ohci_init(void)
-{
-        struct exynos4_ohci_platdata *pdata = &smdkv310_ohci_pdata;
-
-        exynos4_ohci_set_platdata(pdata);
-}
-
-/* USB OTG */
-static struct s3c_hsotg_plat smdkv310_hsotg_pdata;
-
-/* Audio device */
-static struct platform_device smdkv310_device_audio = {
-        .name = "smdk-audio",
-        .id = -1,
-};
-
-static struct platform_device *smdkv310_devices[] __initdata = {
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc1,
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-        &s3c_device_i2c1,
-        &s5p_device_i2c_hdmiphy,
-        &s3c_device_rtc,
-        &s3c_device_usb_hsotg,
-        &s3c_device_wdt,
-        &s5p_device_ehci,
-        &s5p_device_fimc0,
-        &s5p_device_fimc1,
-        &s5p_device_fimc2,
-        &s5p_device_fimc3,
-        &s5p_device_fimc_md,
-        &s5p_device_g2d,
-        &s5p_device_jpeg,
-        &exynos4_device_ac97,
-        &exynos4_device_i2s0,
-        &exynos4_device_ohci,
-        &samsung_device_keypad,
-        &s5p_device_mfc,
-        &s5p_device_mfc_l,
-        &s5p_device_mfc_r,
-        &exynos4_device_spdif,
-        &samsung_asoc_idma,
-        &s5p_device_fimd0,
-        &smdkv310_device_audio,
-        &smdkv310_lcd_lte480wv,
-        &smdkv310_smsc911x,
-        &exynos4_device_ahci,
-        &s5p_device_hdmi,
-        &s5p_device_mixer,
-};
-
-static void __init smdkv310_smsc911x_init(void)
-{
-        u32 cs1;
-
-        /* configure nCS1 width to 16 bits */
-        cs1 = __raw_readl(S5P_SROM_BW) &
-                ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
-        cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
-                (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
-                (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
-                S5P_SROM_BW__NCS1__SHIFT;
-        __raw_writel(cs1, S5P_SROM_BW);
-
-        /* set timing for nCS1 suitable for ethernet chip */
-        __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
-                     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
-                     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
-                     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
-}
-
-/* LCD Backlight data */
-static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = {
-        .no = EXYNOS4_GPD0(1),
-        .func = S3C_GPIO_SFN(2),
-};
-
-static struct platform_pwm_backlight_data smdkv310_bl_data = {
-        .pwm_id = 1,
-        .pwm_period_ns  = 1000,
-};
-
-/* I2C module and id for HDMIPHY */
-static struct i2c_board_info hdmiphy_info = {
-        I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38),
-};
-
-static struct pwm_lookup smdkv310_pwm_lookup[] = {
-        PWM_LOOKUP("s3c24xx-pwm.1", 0, "pwm-backlight.0", NULL),
-};
-
-static void s5p_tv_setup(void)
-{
-        /* direct HPD to HDMI chip */
-        WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
-        s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
-        s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
-}
-
-static void __init smdkv310_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-        s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
-        xxti_f = 12000000;
-        xusbxti_f = 24000000;
-}
-
-static void __init smdkv310_reserve(void)
-{
-        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-
-static void __init smdkv310_machine_init(void)
-{
-        s3c_i2c1_set_platdata(NULL);
-        i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
-
-        smdkv310_smsc911x_init();
-
-        s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
-        s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
-        s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
-        s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
-
-        s5p_tv_setup();
-        s5p_i2c_hdmiphy_set_platdata(NULL);
-        s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0);
-
-        samsung_keypad_set_platdata(&smdkv310_keypad_data);
-
-        samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
-        pwm_add_table(smdkv310_pwm_lookup, ARRAY_SIZE(smdkv310_pwm_lookup));
-
-#ifdef CONFIG_DRM_EXYNOS_FIMD
-        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
-        exynos4_fimd0_gpio_setup_24bpp();
-#else
-        s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
-#endif
-
-        smdkv310_ehci_init();
-        smdkv310_ohci_init();
-        s3c_hsotg_set_platdata(&smdkv310_hsotg_pdata);
-
-        platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
-}
-
-MACHINE_START(SMDKV310, "SMDKV310")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = smdkv310_map_io,
-        .init_machine   = smdkv310_machine_init,
-        .init_time      = exynos_init_time,
-        .reserve        = &smdkv310_reserve,
-        .restart        = exynos4_restart,
-MACHINE_END
-
-MACHINE_START(SMDKC210, "SMDKC210")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = smdkv310_map_io,
-        .init_machine   = smdkv310_machine_init,
-        .init_late      = exynos_init_late,
-        .init_time      = exynos_init_time,
-        .reserve        = &smdkv310_reserve,
-        .restart        = exynos4_restart,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
deleted file mode 100644
index 327d50d4681d..000000000000
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ /dev/null
@@ -1,1160 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mach-universal_c210.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/platform_device.h>
-#include <linux/serial_core.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/gpio_keys.h>
-#include <linux/gpio.h>
-#include <linux/interrupt.h>
-#include <linux/fb.h>
-#include <linux/mfd/max8998.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/max8952.h>
-#include <linux/mmc/host.h>
-#include <linux/i2c-gpio.h>
-#include <linux/i2c/mcs.h>
-#include <linux/i2c/atmel_mxt_ts.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/mipi-csis.h>
-#include <linux/platform_data/s3c-hsotg.h>
-#include <drm/exynos_drm.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <video/samsung_fimd.h>
-#include <plat/regs-serial.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/gpio-cfg.h>
-#include <plat/fb.h>
-#include <plat/mfc.h>
-#include <plat/sdhci.h>
-#include <plat/fimc-core.h>
-#include <plat/samsung-time.h>
-#include <plat/camport.h>
-
-#include <mach/map.h>
-
-#include <media/v4l2-mediabus.h>
-#include <media/s5p_fimc.h>
-#include <media/m5mols.h>
-#include <media/s5k6aa.h>
-
-#include "common.h"
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define UNIVERSAL_UCON_DEFAULT  (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8
-
-#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG256 |      \
-                                 S5PV210_UFCON_RXTRIG256)
-
-static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .ucon           = UNIVERSAL_UCON_DEFAULT,
-                .ulcon          = UNIVERSAL_ULCON_DEFAULT,
-                .ufcon          = UNIVERSAL_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .ucon           = UNIVERSAL_UCON_DEFAULT,
-                .ulcon          = UNIVERSAL_ULCON_DEFAULT,
-                .ufcon          = UNIVERSAL_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .ucon           = UNIVERSAL_UCON_DEFAULT,
-                .ulcon          = UNIVERSAL_ULCON_DEFAULT,
-                .ufcon          = UNIVERSAL_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .ucon           = UNIVERSAL_UCON_DEFAULT,
-                .ulcon          = UNIVERSAL_ULCON_DEFAULT,
-                .ufcon          = UNIVERSAL_UFCON_DEFAULT,
-        },
-};
-
-static struct regulator_consumer_supply max8952_consumer =
-        REGULATOR_SUPPLY("vdd_arm", NULL);
-
-static struct regulator_init_data universal_max8952_reg_data = {
-        .constraints    = {
-                .name           = "VARM_1.2V",
-                .min_uV         = 770000,
-                .max_uV         = 1400000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .always_on      = 1,
-                .boot_on        = 1,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &max8952_consumer,
-};
-
-static struct max8952_platform_data universal_max8952_pdata __initdata = {
-        .gpio_vid0      = EXYNOS4_GPX0(3),
-        .gpio_vid1      = EXYNOS4_GPX0(4),
-        .gpio_en        = -1, /* Not controllable, set "Always High" */
-        .default_mode   = 0, /* vid0 = 0, vid1 = 0 */
-        .dvs_mode       = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */
-        .sync_freq      = 0, /* default: fastest */
-        .ramp_speed     = 0, /* default: fastest */
-        .reg_data       = &universal_max8952_reg_data,
-};
-
-static struct regulator_consumer_supply lp3974_buck1_consumer =
-        REGULATOR_SUPPLY("vdd_int", NULL);
-
-static struct regulator_consumer_supply lp3974_buck2_consumer =
-        REGULATOR_SUPPLY("vddg3d", NULL);
-
-static struct regulator_consumer_supply lp3974_buck3_consumer[] = {
-        REGULATOR_SUPPLY("vdet", "s5p-sdo"),
-        REGULATOR_SUPPLY("vdd_reg", "0-003c"),
-};
-
-static struct regulator_init_data lp3974_buck1_data = {
-        .constraints    = {
-                .name           = "VINT_1.1V",
-                .min_uV         = 750000,
-                .max_uV         = 1500000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                        REGULATOR_CHANGE_STATUS,
-                .boot_on        = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &lp3974_buck1_consumer,
-};
-
-static struct regulator_init_data lp3974_buck2_data = {
-        .constraints    = {
-                .name           = "VG3D_1.1V",
-                .min_uV         = 750000,
-                .max_uV         = 1500000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                        REGULATOR_CHANGE_STATUS,
-                .boot_on        = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &lp3974_buck2_consumer,
-};
-
-static struct regulator_init_data lp3974_buck3_data = {
-        .constraints    = {
-                .name           = "VCC_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(lp3974_buck3_consumer),
-        .consumer_supplies = lp3974_buck3_consumer,
-};
-
-static struct regulator_init_data lp3974_buck4_data = {
-        .constraints    = {
-                .name           = "VMEM_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data lp3974_ldo2_data = {
-        .constraints    = {
-                .name           = "VALIVE_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-
-static struct regulator_consumer_supply lp3974_ldo3_consumer[] = {
-        REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"),
-        REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
-        REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
-        REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"),
-};
-
-static struct regulator_init_data lp3974_ldo3_data = {
-        .constraints    = {
-                .name           = "VUSB+MIPI_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo3_consumer),
-        .consumer_supplies = lp3974_ldo3_consumer,
-};
-
-static struct regulator_consumer_supply lp3974_ldo4_consumer[] = {
-        REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"),
-};
-
-static struct regulator_init_data lp3974_ldo4_data = {
-        .constraints    = {
-                .name           = "VADC_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo4_consumer),
-        .consumer_supplies = lp3974_ldo4_consumer,
-};
-
-static struct regulator_init_data lp3974_ldo5_data = {
-        .constraints    = {
-                .name           = "VTF_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data lp3974_ldo6_data = {
-        .constraints    = {
-                .name           = "LDO6",
-                .min_uV         = 2000000,
-                .max_uV         = 2000000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_consumer_supply lp3974_ldo7_consumer[] = {
-        REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"),
-};
-
-static struct regulator_init_data lp3974_ldo7_data = {
-        .constraints    = {
-                .name           = "VLCD+VMIPI_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(lp3974_ldo7_consumer),
-        .consumer_supplies      = lp3974_ldo7_consumer,
-};
-
-static struct regulator_consumer_supply lp3974_ldo8_consumer[] = {
-        REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"),
-        REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
-};
-
-static struct regulator_init_data lp3974_ldo8_data = {
-        .constraints    = {
-                .name           = "VUSB+VDAC_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo8_consumer),
-        .consumer_supplies = lp3974_ldo8_consumer,
-};
-
-static struct regulator_consumer_supply lp3974_ldo9_consumer =
-        REGULATOR_SUPPLY("vddio", "0-003c");
-
-static struct regulator_init_data lp3974_ldo9_data = {
-        .constraints    = {
-                .name           = "VCC_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &lp3974_ldo9_consumer,
-};
-
-static struct regulator_init_data lp3974_ldo10_data = {
-        .constraints    = {
-                .name           = "VPLL_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .boot_on        = 1,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_consumer_supply lp3974_ldo11_consumer =
-        REGULATOR_SUPPLY("dig_28", "0-001f");
-
-static struct regulator_init_data lp3974_ldo11_data = {
-        .constraints    = {
-                .name           = "CAM_AF_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &lp3974_ldo11_consumer,
-};
-
-static struct regulator_init_data lp3974_ldo12_data = {
-        .constraints    = {
-                .name           = "PS_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data lp3974_ldo13_data = {
-        .constraints    = {
-                .name           = "VHIC_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_consumer_supply lp3974_ldo14_consumer =
-        REGULATOR_SUPPLY("dig_18", "0-001f");
-
-static struct regulator_init_data lp3974_ldo14_data = {
-        .constraints    = {
-                .name           = "CAM_I_HOST_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &lp3974_ldo14_consumer,
-};
-
-
-static struct regulator_consumer_supply lp3974_ldo15_consumer =
-        REGULATOR_SUPPLY("dig_12", "0-001f");
-
-static struct regulator_init_data lp3974_ldo15_data = {
-        .constraints    = {
-                .name           = "CAM_S_DIG+FM33_CORE_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &lp3974_ldo15_consumer,
-};
-
-static struct regulator_consumer_supply lp3974_ldo16_consumer[] = {
-        REGULATOR_SUPPLY("vdda", "0-003c"),
-        REGULATOR_SUPPLY("a_sensor", "0-001f"),
-};
-
-static struct regulator_init_data lp3974_ldo16_data = {
-        .constraints    = {
-                .name           = "CAM_S_ANA_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(lp3974_ldo16_consumer),
-        .consumer_supplies      = lp3974_ldo16_consumer,
-};
-
-static struct regulator_init_data lp3974_ldo17_data = {
-        .constraints    = {
-                .name           = "VCC_3.0V_LCD",
-                .min_uV         = 3000000,
-                .max_uV         = 3000000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .boot_on        = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data lp3974_32khz_ap_data = {
-        .constraints    = {
-                .name           = "32KHz AP",
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-
-static struct regulator_init_data lp3974_32khz_cp_data = {
-        .constraints    = {
-                .name           = "32KHz CP",
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data lp3974_vichg_data = {
-        .constraints    = {
-                .name           = "VICHG",
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data lp3974_esafeout1_data = {
-        .constraints    = {
-                .name           = "SAFEOUT1",
-                .min_uV         = 4800000,
-                .max_uV         = 4800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-
-static struct regulator_init_data lp3974_esafeout2_data = {
-        .constraints    = {
-                .name           = "SAFEOUT2",
-                .boot_on        = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-
-static struct max8998_regulator_data lp3974_regulators[] = {
-        { MAX8998_LDO2,  &lp3974_ldo2_data },
-        { MAX8998_LDO3,  &lp3974_ldo3_data },
-        { MAX8998_LDO4,  &lp3974_ldo4_data },
-        { MAX8998_LDO5,  &lp3974_ldo5_data },
-        { MAX8998_LDO6,  &lp3974_ldo6_data },
-        { MAX8998_LDO7,  &lp3974_ldo7_data },
-        { MAX8998_LDO8,  &lp3974_ldo8_data },
-        { MAX8998_LDO9,  &lp3974_ldo9_data },
-        { MAX8998_LDO10, &lp3974_ldo10_data },
-        { MAX8998_LDO11, &lp3974_ldo11_data },
-        { MAX8998_LDO12, &lp3974_ldo12_data },
-        { MAX8998_LDO13, &lp3974_ldo13_data },
-        { MAX8998_LDO14, &lp3974_ldo14_data },
-        { MAX8998_LDO15, &lp3974_ldo15_data },
-        { MAX8998_LDO16, &lp3974_ldo16_data },
-        { MAX8998_LDO17, &lp3974_ldo17_data },
-        { MAX8998_BUCK1, &lp3974_buck1_data },
-        { MAX8998_BUCK2, &lp3974_buck2_data },
-        { MAX8998_BUCK3, &lp3974_buck3_data },
-        { MAX8998_BUCK4, &lp3974_buck4_data },
-        { MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data },
-        { MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data },
-        { MAX8998_ENVICHG, &lp3974_vichg_data },
-        { MAX8998_ESAFEOUT1, &lp3974_esafeout1_data },
-        { MAX8998_ESAFEOUT2, &lp3974_esafeout2_data },
-};
-
-static struct max8998_platform_data universal_lp3974_pdata = {
-        .num_regulators         = ARRAY_SIZE(lp3974_regulators),
-        .regulators             = lp3974_regulators,
-        .buck1_voltage1         = 1100000,      /* INT */
-        .buck1_voltage2         = 1000000,
-        .buck1_voltage3         = 1100000,
-        .buck1_voltage4         = 1000000,
-        .buck1_set1             = EXYNOS4_GPX0(5),
-        .buck1_set2             = EXYNOS4_GPX0(6),
-        .buck2_voltage1         = 1200000,      /* G3D */
-        .buck2_voltage2         = 1100000,
-        .buck1_default_idx      = 0,
-        .buck2_set3             = EXYNOS4_GPE2(0),
-        .buck2_default_idx      = 0,
-        .wakeup                 = true,
-};
-
-
-enum fixed_regulator_id {
-        FIXED_REG_ID_MMC0,
-        FIXED_REG_ID_HDMI_5V,
-        FIXED_REG_ID_CAM_S_IF,
-        FIXED_REG_ID_CAM_I_CORE,
-        FIXED_REG_ID_CAM_VT_DIO,
-};
-
-static struct regulator_consumer_supply hdmi_fixed_consumer =
-        REGULATOR_SUPPLY("hdmi-en", "exynos4-hdmi");
-
-static struct regulator_init_data hdmi_fixed_voltage_init_data = {
-        .constraints            = {
-                .name           = "HDMI_5V",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &hdmi_fixed_consumer,
-};
-
-static struct fixed_voltage_config hdmi_fixed_voltage_config = {
-        .supply_name            = "HDMI_EN1",
-        .microvolts             = 5000000,
-        .gpio                   = EXYNOS4_GPE0(1),
-        .enable_high            = true,
-        .init_data              = &hdmi_fixed_voltage_init_data,
-};
-
-static struct platform_device hdmi_fixed_voltage = {
-        .name                   = "reg-fixed-voltage",
-        .id                     = FIXED_REG_ID_HDMI_5V,
-        .dev                    = {
-                .platform_data  = &hdmi_fixed_voltage_config,
-        },
-};
-
-/* GPIO I2C 5 (PMIC) */
-static struct i2c_board_info i2c5_devs[] __initdata = {
-        {
-                I2C_BOARD_INFO("max8952", 0xC0 >> 1),
-                .platform_data  = &universal_max8952_pdata,
-        }, {
-                I2C_BOARD_INFO("lp3974", 0xCC >> 1),
-                .platform_data  = &universal_lp3974_pdata,
-        },
-};
-
-/* I2C3 (TSP) */
-static struct mxt_platform_data qt602240_platform_data = {
-        .x_line         = 19,
-        .y_line         = 11,
-        .x_size         = 800,
-        .y_size         = 480,
-        .blen           = 0x11,
-        .threshold      = 0x28,
-        .voltage        = 2800000,              /* 2.8V */
-        .orient         = MXT_DIAGONAL,
-        .irqflags       = IRQF_TRIGGER_FALLING,
-};
-
-static struct i2c_board_info i2c3_devs[] __initdata = {
-        {
-                I2C_BOARD_INFO("qt602240_ts", 0x4a),
-                .platform_data = &qt602240_platform_data,
-        },
-};
-
-static void __init universal_tsp_init(void)
-{
-        int gpio;
-
-        /* TSP_LDO_ON: XMDMADDR_11 */
-        gpio = EXYNOS4_GPE2(3);
-        gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON");
-        gpio_export(gpio, 0);
-
-        /* TSP_INT: XMDMADDR_7 */
-        gpio = EXYNOS4_GPE1(7);
-        gpio_request(gpio, "TSP_INT");
-
-        s5p_register_gpio_interrupt(gpio);
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-        i2c3_devs[0].irq = gpio_to_irq(gpio);
-}
-
-
-/* GPIO I2C 12 (3 Touchkey) */
-static uint32_t touchkey_keymap[] = {
-        /* MCS_KEY_MAP(value, keycode) */
-        MCS_KEY_MAP(0, KEY_MENU),               /* KEY_SEND */
-        MCS_KEY_MAP(1, KEY_BACK),               /* KEY_END */
-};
-
-static struct mcs_platform_data touchkey_data = {
-        .keymap         = touchkey_keymap,
-        .keymap_size    = ARRAY_SIZE(touchkey_keymap),
-        .key_maxval     = 2,
-};
-
-/* GPIO I2C 3_TOUCH 2.8V */
-#define I2C_GPIO_BUS_12         12
-static struct i2c_gpio_platform_data i2c_gpio12_data = {
-        .sda_pin        = EXYNOS4_GPE4(0),      /* XMDMDATA_8 */
-        .scl_pin        = EXYNOS4_GPE4(1),      /* XMDMDATA_9 */
-};
-
-static struct platform_device i2c_gpio12 = {
-        .name           = "i2c-gpio",
-        .id             = I2C_GPIO_BUS_12,
-        .dev            = {
-                .platform_data  = &i2c_gpio12_data,
-        },
-};
-
-static struct i2c_board_info i2c_gpio12_devs[] __initdata = {
-        {
-                I2C_BOARD_INFO("mcs5080_touchkey", 0x20),
-                .platform_data = &touchkey_data,
-        },
-};
-
-static void __init universal_touchkey_init(void)
-{
-        int gpio;
-
-        gpio = EXYNOS4_GPE3(7);                 /* XMDMDATA_7 */
-        gpio_request(gpio, "3_TOUCH_INT");
-        s5p_register_gpio_interrupt(gpio);
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-        i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
-
-        gpio = EXYNOS4_GPE3(3);                 /* XMDMDATA_3 */
-        gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "3_TOUCH_EN");
-}
-
-static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = {
-        .frequency      = 300 * 1000,
-        .sda_delay      = 200,
-};
-
-/* GPIO KEYS */
-static struct gpio_keys_button universal_gpio_keys_tables[] = {
-        {
-                .code                   = KEY_VOLUMEUP,
-                .gpio                   = EXYNOS4_GPX2(0),      /* XEINT16 */
-                .desc                   = "gpio-keys: KEY_VOLUMEUP",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_VOLUMEDOWN,
-                .gpio                   = EXYNOS4_GPX2(1),      /* XEINT17 */
-                .desc                   = "gpio-keys: KEY_VOLUMEDOWN",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_CONFIG,
-                .gpio                   = EXYNOS4_GPX2(2),      /* XEINT18 */
-                .desc                   = "gpio-keys: KEY_CONFIG",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_CAMERA,
-                .gpio                   = EXYNOS4_GPX2(3),      /* XEINT19 */
-                .desc                   = "gpio-keys: KEY_CAMERA",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_OK,
-                .gpio                   = EXYNOS4_GPX3(5),      /* XEINT29 */
-                .desc                   = "gpio-keys: KEY_OK",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        },
-};
-
-static struct gpio_keys_platform_data universal_gpio_keys_data = {
-        .buttons        = universal_gpio_keys_tables,
-        .nbuttons       = ARRAY_SIZE(universal_gpio_keys_tables),
-};
-
-static struct platform_device universal_gpio_keys = {
-        .name                   = "gpio-keys",
-        .dev                    = {
-                .platform_data  = &universal_gpio_keys_data,
-        },
-};
-
-/* eMMC */
-static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
-        .max_width              = 8,
-        .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-        .cd_type                = S3C_SDHCI_CD_PERMANENT,
-};
-
-static struct regulator_consumer_supply mmc0_supplies[] = {
-        REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
-};
-
-static struct regulator_init_data mmc0_fixed_voltage_init_data = {
-        .constraints            = {
-                .name           = "VMEM_VDD_2.8V",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(mmc0_supplies),
-        .consumer_supplies      = mmc0_supplies,
-};
-
-static struct fixed_voltage_config mmc0_fixed_voltage_config = {
-        .supply_name            = "MASSMEMORY_EN",
-        .microvolts             = 2800000,
-        .gpio                   = EXYNOS4_GPE1(3),
-        .enable_high            = true,
-        .init_data              = &mmc0_fixed_voltage_init_data,
-};
-
-static struct platform_device mmc0_fixed_voltage = {
-        .name                   = "reg-fixed-voltage",
-        .id                     = FIXED_REG_ID_MMC0,
-        .dev                    = {
-                .platform_data  = &mmc0_fixed_voltage_config,
-        },
-};
-
-/* SD */
-static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
-        .max_width              = 4,
-        .host_caps              = MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .ext_cd_gpio            = EXYNOS4_GPX3(4),      /* XEINT_28 */
-        .ext_cd_gpio_invert     = 1,
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-};
-
-/* WiFi */
-static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
-        .max_width              = 4,
-        .host_caps              = MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .cd_type                = S3C_SDHCI_CD_EXTERNAL,
-};
-
-static void __init universal_sdhci_init(void)
-{
-        s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
-        s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
-        s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
-}
-
-/* I2C1 */
-static struct i2c_board_info i2c1_devs[] __initdata = {
-        /* Gyro, To be updated */
-};
-
-#ifdef CONFIG_DRM_EXYNOS
-static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
-        .panel = {
-                .timing = {
-                        .left_margin    = 16,
-                        .right_margin   = 16,
-                        .upper_margin   = 2,
-                        .lower_margin   = 28,
-                        .hsync_len      = 2,
-                        .vsync_len      = 1,
-                        .xres           = 480,
-                        .yres           = 800,
-                        .refresh        = 55,
-                },
-        },
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
-                          VIDCON0_CLKSEL_LCD,
-        .vidcon1        = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
-                          | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .default_win    = 3,
-        .bpp            = 32,
-};
-#else
-/* Frame Buffer */
-static struct s3c_fb_pd_win universal_fb_win0 = {
-        .max_bpp        = 32,
-        .default_bpp    = 16,
-        .xres           = 480,
-        .yres           = 800,
-        .virtual_x      = 480,
-        .virtual_y      = 2 * 800,
-};
-
-static struct fb_videomode universal_lcd_timing = {
-        .left_margin    = 16,
-        .right_margin   = 16,
-        .upper_margin   = 2,
-        .lower_margin   = 28,
-        .hsync_len      = 2,
-        .vsync_len      = 1,
-        .xres           = 480,
-        .yres           = 800,
-        .refresh        = 55,
-};
-
-static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
-        .win[0]         = &universal_fb_win0,
-        .vtiming        = &universal_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
-                          VIDCON0_CLKSEL_LCD,
-        .vidcon1        = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
-                          | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-#endif
-
-static struct regulator_consumer_supply cam_vt_dio_supply =
-        REGULATOR_SUPPLY("vdd_core", "0-003c");
-
-static struct regulator_init_data cam_vt_dio_reg_init_data = {
-        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &cam_vt_dio_supply,
-};
-
-static struct fixed_voltage_config cam_vt_dio_fixed_voltage_cfg = {
-        .supply_name    = "CAM_VT_D_IO",
-        .microvolts     = 2800000,
-        .gpio           = EXYNOS4_GPE2(1), /* CAM_PWR_EN2 */
-        .enable_high    = 1,
-        .init_data      = &cam_vt_dio_reg_init_data,
-};
-
-static struct platform_device cam_vt_dio_fixed_reg_dev = {
-        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_DIO,
-        .dev = { .platform_data = &cam_vt_dio_fixed_voltage_cfg },
-};
-
-static struct regulator_consumer_supply cam_i_core_supply =
-        REGULATOR_SUPPLY("core", "0-001f");
-
-static struct regulator_init_data cam_i_core_reg_init_data = {
-        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &cam_i_core_supply,
-};
-
-static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = {
-        .supply_name    = "CAM_I_CORE_1.2V",
-        .microvolts     = 1200000,
-        .gpio           = EXYNOS4_GPE2(2),      /* CAM_8M_CORE_EN */
-        .enable_high    = 1,
-        .init_data      = &cam_i_core_reg_init_data,
-};
-
-static struct platform_device cam_i_core_fixed_reg_dev = {
-        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_I_CORE,
-        .dev = { .platform_data = &cam_i_core_fixed_voltage_cfg },
-};
-
-static struct regulator_consumer_supply cam_s_if_supply =
-        REGULATOR_SUPPLY("d_sensor", "0-001f");
-
-static struct regulator_init_data cam_s_if_reg_init_data = {
-        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &cam_s_if_supply,
-};
-
-static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = {
-        .supply_name    = "CAM_S_IF_1.8V",
-        .microvolts     = 1800000,
-        .gpio           = EXYNOS4_GPE3(0),      /* CAM_PWR_EN1 */
-        .enable_high    = 1,
-        .init_data      = &cam_s_if_reg_init_data,
-};
-
-static struct platform_device cam_s_if_fixed_reg_dev = {
-        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_S_IF,
-        .dev = { .platform_data = &cam_s_if_fixed_voltage_cfg },
-};
-
-static struct s5p_platform_mipi_csis mipi_csis_platdata = {
-        .clk_rate       = 166000000UL,
-        .lanes          = 2,
-        .hs_settle      = 12,
-};
-
-#define GPIO_CAM_LEVEL_EN(n)    EXYNOS4_GPE4(n + 3)
-#define GPIO_CAM_8M_ISP_INT     EXYNOS4_GPX1(5) /* XEINT_13 */
-#define GPIO_CAM_MEGA_nRST      EXYNOS4_GPE2(5)
-#define GPIO_CAM_VGA_NRST       EXYNOS4_GPE4(7)
-#define GPIO_CAM_VGA_NSTBY      EXYNOS4_GPE4(6)
-
-static int s5k6aa_set_power(int on)
-{
-        gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
-        return 0;
-}
-
-static struct s5k6aa_platform_data s5k6aa_platdata = {
-        .mclk_frequency = 21600000UL,
-        .gpio_reset     = { GPIO_CAM_VGA_NRST, 0 },
-        .gpio_stby      = { GPIO_CAM_VGA_NSTBY, 0 },
-        .bus_type       = V4L2_MBUS_PARALLEL,
-        .horiz_flip     = 1,
-        .set_power      = s5k6aa_set_power,
-};
-
-static struct i2c_board_info s5k6aa_board_info = {
-        I2C_BOARD_INFO("S5K6AA", 0x3C),
-        .platform_data = &s5k6aa_platdata,
-};
-
-static int m5mols_set_power(struct device *dev, int on)
-{
-        gpio_set_value(GPIO_CAM_LEVEL_EN(1), !on);
-        gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
-        return 0;
-}
-
-static struct m5mols_platform_data m5mols_platdata = {
-        .gpio_reset     = GPIO_CAM_MEGA_nRST,
-        .reset_polarity = 0,
-        .set_power      = m5mols_set_power,
-};
-
-static struct i2c_board_info m5mols_board_info = {
-        I2C_BOARD_INFO("M5MOLS", 0x1F),
-        .platform_data = &m5mols_platdata,
-};
-
-static struct fimc_source_info universal_camera_sensors[] = {
-        {
-                .mux_id         = 0,
-                .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
-                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
-                .fimc_bus_type  = FIMC_BUS_TYPE_ITU_601,
-                .board_info     = &s5k6aa_board_info,
-                .i2c_bus_num    = 0,
-                .clk_frequency  = 24000000UL,
-        }, {
-                .mux_id         = 0,
-                .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
-                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
-                .fimc_bus_type  = FIMC_BUS_TYPE_MIPI_CSI2,
-                .board_info     = &m5mols_board_info,
-                .i2c_bus_num    = 0,
-                .clk_frequency  = 24000000UL,
-        },
-};
-
-static struct s5p_platform_fimc fimc_md_platdata = {
-        .source_info    = universal_camera_sensors,
-        .num_clients    = ARRAY_SIZE(universal_camera_sensors),
-};
-
-static struct gpio universal_camera_gpios[] = {
-        { GPIO_CAM_LEVEL_EN(1), GPIOF_OUT_INIT_HIGH, "CAM_LVL_EN1" },
-        { GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW,  "CAM_LVL_EN2" },
-        { GPIO_CAM_8M_ISP_INT,  GPIOF_IN,            "8M_ISP_INT"  },
-        { GPIO_CAM_MEGA_nRST,   GPIOF_OUT_INIT_LOW,  "CAM_8M_NRST" },
-        { GPIO_CAM_VGA_NRST,    GPIOF_OUT_INIT_LOW,  "CAM_VGA_NRST"  },
-        { GPIO_CAM_VGA_NSTBY,   GPIOF_OUT_INIT_LOW,  "CAM_VGA_NSTBY" },
-};
-
-/* USB OTG */
-static struct s3c_hsotg_plat universal_hsotg_pdata;
-
-static void __init universal_camera_init(void)
-{
-        s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
-                         &s5p_device_mipi_csis0);
-        s3c_set_platdata(&fimc_md_platdata,  sizeof(fimc_md_platdata),
-                         &s5p_device_fimc_md);
-
-        if (gpio_request_array(universal_camera_gpios,
-                               ARRAY_SIZE(universal_camera_gpios))) {
-                pr_err("%s: GPIO request failed\n", __func__);
-                return;
-        }
-
-        if (!s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xf)))
-                m5mols_board_info.irq = gpio_to_irq(GPIO_CAM_8M_ISP_INT);
-        else
-                pr_err("Failed to configure 8M_ISP_INT GPIO\n");
-
-        /* Free GPIOs controlled directly by the sensor drivers. */
-        gpio_free(GPIO_CAM_MEGA_nRST);
-        gpio_free(GPIO_CAM_8M_ISP_INT);
-        gpio_free(GPIO_CAM_VGA_NRST);
-        gpio_free(GPIO_CAM_VGA_NSTBY);
-
-        if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A))
-                pr_err("Camera port A setup failed\n");
-}
-
-static struct platform_device *universal_devices[] __initdata = {
-        /* Samsung Platform Devices */
-        &s5p_device_mipi_csis0,
-        &s5p_device_fimc0,
-        &s5p_device_fimc1,
-        &s5p_device_fimc2,
-        &s5p_device_fimc3,
-        &s5p_device_g2d,
-        &mmc0_fixed_voltage,
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-        &s3c_device_i2c0,
-        &s3c_device_i2c3,
-        &s3c_device_i2c5,
-        &s5p_device_i2c_hdmiphy,
-        &hdmi_fixed_voltage,
-        &s5p_device_hdmi,
-        &s5p_device_sdo,
-        &s5p_device_mixer,
-
-        /* Universal Devices */
-        &i2c_gpio12,
-        &universal_gpio_keys,
-        &s5p_device_onenand,
-        &s5p_device_fimd0,
-        &s5p_device_jpeg,
-        &s3c_device_usb_hsotg,
-        &s5p_device_mfc,
-        &s5p_device_mfc_l,
-        &s5p_device_mfc_r,
-        &cam_vt_dio_fixed_reg_dev,
-        &cam_i_core_fixed_reg_dev,
-        &cam_s_if_fixed_reg_dev,
-        &s5p_device_fimc_md,
-};
-
-static void __init universal_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-        s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
-        samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
-        xxti_f = 0;
-        xusbxti_f = 24000000;
-}
-
-static void s5p_tv_setup(void)
-{
-        /* direct HPD to HDMI chip */
-        gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
-        s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
-        s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
-}
-
-static void __init universal_reserve(void)
-{
-        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-
-static void __init universal_machine_init(void)
-{
-        universal_sdhci_init();
-        s5p_tv_setup();
-
-        s3c_i2c0_set_platdata(&universal_i2c0_platdata);
-        i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
-
-        universal_tsp_init();
-        s3c_i2c3_set_platdata(NULL);
-        i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
-
-        s3c_i2c5_set_platdata(NULL);
-        s5p_i2c_hdmiphy_set_platdata(NULL);
-        i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
-
-#ifdef CONFIG_DRM_EXYNOS
-        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
-        exynos4_fimd0_gpio_setup_24bpp();
-#else
-        s5p_fimd0_set_platdata(&universal_lcd_pdata);
-#endif
-
-        universal_touchkey_init();
-        i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
-                        ARRAY_SIZE(i2c_gpio12_devs));
-
-        s3c_hsotg_set_platdata(&universal_hsotg_pdata);
-        universal_camera_init();
-
-        /* Last */
-        platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
-}
-
-MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
-        /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = universal_map_io,
-        .init_machine   = universal_machine_init,
-        .init_late      = exynos_init_late,
-        .init_time      = samsung_timer_init,
-        .reserve        = &universal_reserve,
-        .restart        = exynos4_restart,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index a0e8ff7758a4..d9c6d0ab6a0c 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -200,7 +200,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
 {
         int i;
 
-        if (!(soc_is_exynos5250() || soc_is_exynos5440()))
+        if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
                 scu_enable(scu_base_addr());
 
         /*
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index e3faaa812016..41c20692a13f 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -30,7 +30,6 @@
 #include <plat/regs-srom.h>
 
 #include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-pmu.h>
 #include <mach/pm-core.h>
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 9f1351de52f7..1703593e366c 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -74,17 +74,6 @@ static int exynos_pd_power_off(struct generic_pm_domain *domain)
         return exynos_pd_power(domain, false);
 }
 
-#define EXYNOS_GPD(PD, BASE, NAME)                      \
-static struct exynos_pm_domain PD = {                   \
-        .base = (void __iomem *)BASE,                   \
-        .name = NAME,                                   \
-        .pd = {                                         \
-                .power_off = exynos_pd_power_off,       \
-                .power_on = exynos_pd_power_on, \
-        },                                              \
-}
-
-#ifdef CONFIG_OF
 static void exynos_add_device_to_domain(struct exynos_pm_domain *pd,
                                          struct device *dev)
 {
@@ -157,7 +146,7 @@ static struct notifier_block platform_nb = {
         .notifier_call = exynos_pm_notifier_call,
 };
 
-static __init int exynos_pm_dt_parse_domains(void)
+static __init int exynos4_pm_init_power_domain(void)
 {
         struct platform_device *pdev;
         struct device_node *np;
@@ -193,94 +182,6 @@ static __init int exynos_pm_dt_parse_domains(void)
 
         return 0;
 }
-#else
-static __init int exynos_pm_dt_parse_domains(void)
-{
-        return 0;
-}
-#endif /* CONFIG_OF */
-
-static __init __maybe_unused void exynos_pm_add_dev_to_genpd(struct platform_device *pdev,
-                                                struct exynos_pm_domain *pd)
-{
-        if (pdev->dev.bus) {
-                if (!pm_genpd_add_device(&pd->pd, &pdev->dev))
-                        pm_genpd_dev_need_restore(&pdev->dev, true);
-                else
-                        pr_info("%s: error in adding %s device to %s power"
-                                "domain\n", __func__, dev_name(&pdev->dev),
-                                pd->name);
-        }
-}
-
-EXYNOS_GPD(exynos4_pd_mfc, S5P_PMU_MFC_CONF, "pd-mfc");
-EXYNOS_GPD(exynos4_pd_g3d, S5P_PMU_G3D_CONF, "pd-g3d");
-EXYNOS_GPD(exynos4_pd_lcd0, S5P_PMU_LCD0_CONF, "pd-lcd0");
-EXYNOS_GPD(exynos4_pd_lcd1, S5P_PMU_LCD1_CONF, "pd-lcd1");
-EXYNOS_GPD(exynos4_pd_tv, S5P_PMU_TV_CONF, "pd-tv");
-EXYNOS_GPD(exynos4_pd_cam, S5P_PMU_CAM_CONF, "pd-cam");
-EXYNOS_GPD(exynos4_pd_gps, S5P_PMU_GPS_CONF, "pd-gps");
-
-static struct exynos_pm_domain *exynos4_pm_domains[] = {
-        &exynos4_pd_mfc,
-        &exynos4_pd_g3d,
-        &exynos4_pd_lcd0,
-        &exynos4_pd_lcd1,
-        &exynos4_pd_tv,
-        &exynos4_pd_cam,
-        &exynos4_pd_gps,
-};
-
-static __init int exynos4_pm_init_power_domain(void)
-{
-        int idx;
-
-        if (of_have_populated_dt())
-                return exynos_pm_dt_parse_domains();
-
-        for (idx = 0; idx < ARRAY_SIZE(exynos4_pm_domains); idx++) {
-                struct exynos_pm_domain *pd = exynos4_pm_domains[idx];
-                int on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN;
-
-                pm_genpd_init(&pd->pd, NULL, !on);
-        }
-
-#ifdef CONFIG_S5P_DEV_FIMD0
-        exynos_pm_add_dev_to_genpd(&s5p_device_fimd0, &exynos4_pd_lcd0);
-#endif
-#ifdef CONFIG_S5P_DEV_TV
-        exynos_pm_add_dev_to_genpd(&s5p_device_hdmi, &exynos4_pd_tv);
-        exynos_pm_add_dev_to_genpd(&s5p_device_mixer, &exynos4_pd_tv);
-#endif
-#ifdef CONFIG_S5P_DEV_MFC
-        exynos_pm_add_dev_to_genpd(&s5p_device_mfc, &exynos4_pd_mfc);
-#endif
-#ifdef CONFIG_S5P_DEV_FIMC0
-        exynos_pm_add_dev_to_genpd(&s5p_device_fimc0, &exynos4_pd_cam);
-#endif
-#ifdef CONFIG_S5P_DEV_FIMC1
-        exynos_pm_add_dev_to_genpd(&s5p_device_fimc1, &exynos4_pd_cam);
-#endif
-#ifdef CONFIG_S5P_DEV_FIMC2
-        exynos_pm_add_dev_to_genpd(&s5p_device_fimc2, &exynos4_pd_cam);
-#endif
-#ifdef CONFIG_S5P_DEV_FIMC3
-        exynos_pm_add_dev_to_genpd(&s5p_device_fimc3, &exynos4_pd_cam);
-#endif
-#ifdef CONFIG_S5P_DEV_CSIS0
-        exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis0, &exynos4_pd_cam);
-#endif
-#ifdef CONFIG_S5P_DEV_CSIS1
-        exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis1, &exynos4_pd_cam);
-#endif
-#ifdef CONFIG_S5P_DEV_G2D
-        exynos_pm_add_dev_to_genpd(&s5p_device_g2d, &exynos4_pd_lcd0);
-#endif
-#ifdef CONFIG_S5P_DEV_JPEG
-        exynos_pm_add_dev_to_genpd(&s5p_device_jpeg, &exynos4_pd_cam);
-#endif
-        return 0;
-}
 arch_initcall(exynos4_pm_init_power_domain);
 
 int __init exynos_pm_late_initcall(void)
diff --git a/arch/arm/mach-exynos/setup-fimc.c b/arch/arm/mach-exynos/setup-fimc.c
deleted file mode 100644
index 6a45078d9d12..000000000000
--- a/arch/arm/mach-exynos/setup-fimc.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics Co., Ltd.
- *
- * Exynos4 camera interface GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/gpio.h>
-#include <plat/gpio-cfg.h>
-#include <plat/camport.h>
-
-int exynos4_fimc_setup_gpio(enum s5p_camport_id id)
-{
-        u32 gpio8, gpio5;
-        u32 sfn;
-        int ret;
-
-        switch (id) {
-        case S5P_CAMPORT_A:
-                gpio8 = EXYNOS4_GPJ0(0); /* PCLK, VSYNC, HREF, DATA[0:4] */
-                gpio5 = EXYNOS4_GPJ1(0); /* DATA[5:7], CLKOUT, FIELD */
-                sfn = S3C_GPIO_SFN(2);
-                break;
-
-        case S5P_CAMPORT_B:
-                gpio8 = EXYNOS4_GPE0(0); /* DATA[0:7] */
-                gpio5 = EXYNOS4_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD */
-                sfn = S3C_GPIO_SFN(3);
-                break;
-
-        default:
-                WARN(1, "Wrong camport id: %d\n", id);
-                return -EINVAL;
-        }
-
-        ret = s3c_gpio_cfgall_range(gpio8, 8, sfn, S3C_GPIO_PULL_UP);
-        if (ret)
-                return ret;
-
-        return s3c_gpio_cfgall_range(gpio5, 5, sfn, S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-fimd0.c b/arch/arm/mach-exynos/setup-fimd0.c
deleted file mode 100644
index 5665bb4e980b..000000000000
--- a/arch/arm/mach-exynos/setup-fimd0.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-fimd0.c
- *
- * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * Base Exynos4 FIMD 0 configuration
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/fb.h>
-#include <linux/gpio.h>
-
-#include <video/samsung_fimd.h>
-#include <plat/gpio-cfg.h>
-
-#include <mach/map.h>
-
-void exynos4_fimd0_gpio_setup_24bpp(void)
-{
-        unsigned int reg;
-
-        s3c_gpio_cfgrange_nopull(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2));
-        s3c_gpio_cfgrange_nopull(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2));
-        s3c_gpio_cfgrange_nopull(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2));
-        s3c_gpio_cfgrange_nopull(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2));
-
-        /*
-         * Set DISPLAY_CONTROL register for Display path selection.
-         *
-         * DISPLAY_CONTROL[1:0]
-         * ---------------------
-         *  00 | MIE
-         *  01 | MDINE
-         *  10 | FIMD : selected
-         *  11 | FIMD
-         */
-        reg = __raw_readl(S3C_VA_SYS + 0x0210);
-        reg |= (1 << 1);
-        __raw_writel(reg, S3C_VA_SYS + 0x0210);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
deleted file mode 100644
index e2d9dfbf102c..000000000000
--- a/arch/arm/mach-exynos/setup-i2c0.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (c) 2009-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * I2C0 GPIO configuration.
- *
- * Based on plat-s3c64xx/setup-i2c0.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-#include <plat/cpu.h>
-
-void s3c_i2c0_cfg_gpio(struct platform_device *dev)
-{
-        if (soc_is_exynos5250() || soc_is_exynos5440())
-                /* will be implemented with gpio function */
-                return;
-
-        s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c1.c b/arch/arm/mach-exynos/setup-i2c1.c
deleted file mode 100644
index 8d2279cc85dc..000000000000
--- a/arch/arm/mach-exynos/setup-i2c1.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c1.c
- *
- * Copyright (C) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C1 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c1_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPD1(2), 2,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c2.c b/arch/arm/mach-exynos/setup-i2c2.c
deleted file mode 100644
index 0ed62fc42a77..000000000000
--- a/arch/arm/mach-exynos/setup-i2c2.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c2.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *
- * I2C2 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c2_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPA0(6), 2,
-                              S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c3.c b/arch/arm/mach-exynos/setup-i2c3.c
deleted file mode 100644
index 7787fd26076b..000000000000
--- a/arch/arm/mach-exynos/setup-i2c3.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c3.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C3 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c3_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPA1(2), 2,
-                              S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c4.c b/arch/arm/mach-exynos/setup-i2c4.c
deleted file mode 100644
index edc847f89826..000000000000
--- a/arch/arm/mach-exynos/setup-i2c4.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c4.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C4 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c4_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
-                              S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c5.c b/arch/arm/mach-exynos/setup-i2c5.c
deleted file mode 100644
index d88af7f75954..000000000000
--- a/arch/arm/mach-exynos/setup-i2c5.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c5.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C5 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c5_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
-                              S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c6.c b/arch/arm/mach-exynos/setup-i2c6.c
deleted file mode 100644
index c590286c9d3a..000000000000
--- a/arch/arm/mach-exynos/setup-i2c6.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c6.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C6 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c6_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
-                              S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c7.c b/arch/arm/mach-exynos/setup-i2c7.c
deleted file mode 100644
index 1bba75568a5f..000000000000
--- a/arch/arm/mach-exynos/setup-i2c7.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c7.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C7 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c7_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPD0(2), 2,
-                              S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-keypad.c b/arch/arm/mach-exynos/setup-keypad.c
deleted file mode 100644
index 7862bfb5933d..000000000000
--- a/arch/arm/mach-exynos/setup-keypad.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-keypad.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * GPIO configuration for Exynos4 KeyPad device
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/gpio.h>
-#include <plat/gpio-cfg.h>
-
-void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
-{
-        /* Keypads can be of various combinations, Just making sure */
-
-        if (rows > 8) {
-                /* Set all the necessary GPX2 pins: KP_ROW[0~7] */
-                s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3),
-                                        S3C_GPIO_PULL_UP);
-
-                /* Set all the necessary GPX3 pins: KP_ROW[8~] */
-                s3c_gpio_cfgall_range(EXYNOS4_GPX3(0), (rows - 8),
-                                         S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-        } else {
-                /* Set all the necessary GPX2 pins: KP_ROW[x] */
-                s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), rows, S3C_GPIO_SFN(3),
-                                        S3C_GPIO_PULL_UP);
-        }
-
-        /* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */
-        s3c_gpio_cfgrange_nopull(EXYNOS4_GPX1(0), cols, S3C_GPIO_SFN(3));
-}
diff --git a/arch/arm/mach-exynos/setup-sdhci-gpio.c b/arch/arm/mach-exynos/setup-sdhci-gpio.c
deleted file mode 100644
index d5b98c866738..000000000000
--- a/arch/arm/mach-exynos/setup-sdhci-gpio.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-sdhci-gpio.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/mmc/host.h>
-#include <linux/mmc/card.h>
-
-#include <mach/gpio.h>
-#include <plat/gpio-cfg.h>
-#include <plat/sdhci.h>
-
-void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
-
-        /* Set all the necessary GPK0[0:1] pins to special-function 2 */
-        for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-
-        switch (width) {
-        case 8:
-                for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
-                        /* Data pin GPK1[3:6] to special-function 3 */
-                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
-                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                        s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-                }
-        case 4:
-                for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) {
-                        /* Data pin GPK0[3:6] to special-function 2 */
-                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                        s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-                }
-        default:
-                break;
-        }
-
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_cfgpin(EXYNOS4_GPK0(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(EXYNOS4_GPK0(2), S3C_GPIO_PULL_UP);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-}
-
-void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
-
-        /* Set all the necessary GPK1[0:1] pins to special-function 2 */
-        for (gpio = EXYNOS4_GPK1(0); gpio < EXYNOS4_GPK1(2); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-
-        for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
-                /* Data pin GPK1[3:6] to special-function 2 */
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_cfgpin(EXYNOS4_GPK1(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(EXYNOS4_GPK1(2), S3C_GPIO_PULL_UP);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-}
-
-void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
-
-        /* Set all the necessary GPK2[0:1] pins to special-function 2 */
-        for (gpio = EXYNOS4_GPK2(0); gpio < EXYNOS4_GPK2(2); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-
-        switch (width) {
-        case 8:
-                for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
-                        /* Data pin GPK3[3:6] to special-function 3 */
-                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
-                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                        s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-                }
-        case 4:
-                for (gpio = EXYNOS4_GPK2(3); gpio <= EXYNOS4_GPK2(6); gpio++) {
-                        /* Data pin GPK2[3:6] to special-function 2 */
-                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                        s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-                }
-        default:
-                break;
-        }
-
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_cfgpin(EXYNOS4_GPK2(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(EXYNOS4_GPK2(2), S3C_GPIO_PULL_UP);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-}
-
-void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
-
-        /* Set all the necessary GPK3[0:1] pins to special-function 2 */
-        for (gpio = EXYNOS4_GPK3(0); gpio < EXYNOS4_GPK3(2); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-
-        for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
-                /* Data pin GPK3[3:6] to special-function 2 */
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_cfgpin(EXYNOS4_GPK3(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(EXYNOS4_GPK3(2), S3C_GPIO_PULL_UP);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-}
diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c
deleted file mode 100644
index 4999829d1c6e..000000000000
--- a/arch/arm/mach-exynos/setup-spi.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-spi.c
- *
- * Copyright (C) 2011 Samsung Electronics Ltd.
- *             http://www.samsung.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/gpio.h>
-#include <plat/gpio-cfg.h>
-
-#ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(void)
-{
-        s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-        return 0;
-}
-#endif
-
-#ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(void)
-{
-        s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-        return 0;
-}
-#endif
-
-#ifdef CONFIG_S3C64XX_DEV_SPI2
-int s3c64xx_spi2_cfg_gpio(void)
-{
-        s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));
-        s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
-                              S3C_GPIO_SFN(5), S3C_GPIO_PULL_UP);
-        return 0;
-}
-#endif
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
deleted file mode 100644
index 6af40662a449..000000000000
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics Co.Ltd
- * Author: Joonyoung Shim <jy0922.shim@samsung.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- */
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <mach/regs-pmu.h>
-#include <mach/regs-usb-phy.h>
-#include <plat/cpu.h>
-#include <plat/usb-phy.h>
-
-static atomic_t host_usage;
-
-static int exynos4_usb_host_phy_is_on(void)
-{
-        return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
-}
-
-static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
-{
-        struct clk *xusbxti_clk;
-        u32 phyclk;
-
-        xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
-        if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
-                if (soc_is_exynos4210()) {
-                        /* set clock frequency for PLL */
-                        phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK;
-
-                        switch (clk_get_rate(xusbxti_clk)) {
-                        case 12 * MHZ:
-                                phyclk |= EXYNOS4210_CLKSEL_12M;
-                                break;
-                        case 48 * MHZ:
-                                phyclk |= EXYNOS4210_CLKSEL_48M;
-                                break;
-                        default:
-                        case 24 * MHZ:
-                                phyclk |= EXYNOS4210_CLKSEL_24M;
-                                break;
-                        }
-                        writel(phyclk, EXYNOS4_PHYCLK);
-                } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-                        /* set clock frequency for PLL */
-                        phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK;
-
-                        switch (clk_get_rate(xusbxti_clk)) {
-                        case 9600 * KHZ:
-                                phyclk |= EXYNOS4X12_CLKSEL_9600K;
-                                break;
-                        case 10 * MHZ:
-                                phyclk |= EXYNOS4X12_CLKSEL_10M;
-                                break;
-                        case 12 * MHZ:
-                                phyclk |= EXYNOS4X12_CLKSEL_12M;
-                                break;
-                        case 19200 * KHZ:
-                                phyclk |= EXYNOS4X12_CLKSEL_19200K;
-                                break;
-                        case 20 * MHZ:
-                                phyclk |= EXYNOS4X12_CLKSEL_20M;
-                                break;
-                        default:
-                        case 24 * MHZ:
-                                /* default reference clock */
-                                phyclk |= EXYNOS4X12_CLKSEL_24M;
-                                break;
-                        }
-                        writel(phyclk, EXYNOS4_PHYCLK);
-                }
-                clk_put(xusbxti_clk);
-        }
-}
-
-static int exynos4210_usb_phy0_init(struct platform_device *pdev)
-{
-        u32 rstcon;
-
-        writel(readl(S5P_USBDEVICE_PHY_CONTROL) | S5P_USBDEVICE_PHY_ENABLE,
-                        S5P_USBDEVICE_PHY_CONTROL);
-
-        exynos4210_usb_phy_clkset(pdev);
-
-        /* set to normal PHY0 */
-        writel((readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK), EXYNOS4_PHYPWR);
-
-        /* reset PHY0 and Link */
-        rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
-        writel(rstcon, EXYNOS4_RSTCON);
-        udelay(10);
-
-        rstcon &= ~PHY0_SWRST_MASK;
-        writel(rstcon, EXYNOS4_RSTCON);
-
-        return 0;
-}
-
-static int exynos4210_usb_phy0_exit(struct platform_device *pdev)
-{
-        writel((readl(EXYNOS4_PHYPWR) | PHY0_ANALOG_POWERDOWN |
-                                PHY0_OTG_DISABLE), EXYNOS4_PHYPWR);
-
-        writel(readl(S5P_USBDEVICE_PHY_CONTROL) & ~S5P_USBDEVICE_PHY_ENABLE,
-                        S5P_USBDEVICE_PHY_CONTROL);
-
-        return 0;
-}
-
-static int exynos4210_usb_phy1_init(struct platform_device *pdev)
-{
-        struct clk *otg_clk;
-        u32 rstcon;
-        int err;
-
-        atomic_inc(&host_usage);
-
-        otg_clk = clk_get(&pdev->dev, "otg");
-        if (IS_ERR(otg_clk)) {
-                dev_err(&pdev->dev, "Failed to get otg clock\n");
-                return PTR_ERR(otg_clk);
-        }
-
-        err = clk_enable(otg_clk);
-        if (err) {
-                clk_put(otg_clk);
-                return err;
-        }
-
-        if (exynos4_usb_host_phy_is_on())
-                return 0;
-
-        writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
-                        S5P_USBHOST_PHY_CONTROL);
-
-        exynos4210_usb_phy_clkset(pdev);
-
-        /* floating prevention logic: disable */
-        writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
-
-        /* set to normal HSIC 0 and 1 of PHY1 */
-        writel((readl(EXYNOS4_PHYPWR) & ~PHY1_HSIC_NORMAL_MASK),
-                        EXYNOS4_PHYPWR);
-
-        /* set to normal standard USB of PHY1 */
-        writel((readl(EXYNOS4_PHYPWR) & ~PHY1_STD_NORMAL_MASK), EXYNOS4_PHYPWR);
-
-        /* reset all ports of both PHY and Link */
-        rstcon = readl(EXYNOS4_RSTCON) | HOST_LINK_PORT_SWRST_MASK |
-                PHY1_SWRST_MASK;
-        writel(rstcon, EXYNOS4_RSTCON);
-        udelay(10);
-
-        rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK);
-        writel(rstcon, EXYNOS4_RSTCON);
-        udelay(80);
-
-        clk_disable(otg_clk);
-        clk_put(otg_clk);
-
-        return 0;
-}
-
-static int exynos4210_usb_phy1_exit(struct platform_device *pdev)
-{
-        struct clk *otg_clk;
-        int err;
-
-        if (atomic_dec_return(&host_usage) > 0)
-                return 0;
-
-        otg_clk = clk_get(&pdev->dev, "otg");
-        if (IS_ERR(otg_clk)) {
-                dev_err(&pdev->dev, "Failed to get otg clock\n");
-                return PTR_ERR(otg_clk);
-        }
-
-        err = clk_enable(otg_clk);
-        if (err) {
-                clk_put(otg_clk);
-                return err;
-        }
-
-        writel((readl(EXYNOS4_PHYPWR) | PHY1_STD_ANALOG_POWERDOWN),
-                        EXYNOS4_PHYPWR);
-
-        writel(readl(S5P_USBHOST_PHY_CONTROL) & ~S5P_USBHOST_PHY_ENABLE,
-                        S5P_USBHOST_PHY_CONTROL);
-
-        clk_disable(otg_clk);
-        clk_put(otg_clk);
-
-        return 0;
-}
-
-int s5p_usb_phy_init(struct platform_device *pdev, int type)
-{
-        if (type == USB_PHY_TYPE_DEVICE)
-                return exynos4210_usb_phy0_init(pdev);
-        else if (type == USB_PHY_TYPE_HOST)
-                return exynos4210_usb_phy1_init(pdev);
-
-        return -EINVAL;
-}
-
-int s5p_usb_phy_exit(struct platform_device *pdev, int type)
-{
-        if (type == USB_PHY_TYPE_DEVICE)
-                return exynos4210_usb_phy0_exit(pdev);
-        else if (type == USB_PHY_TYPE_HOST)
-                return exynos4210_usb_phy1_exit(pdev);
-
-        return -EINVAL;
-}
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index ba44328464f3..f25cf888f3d4 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -56,9 +56,6 @@ config MXC_USE_EPIT
           uses the same clocks as the GPT. Anyway, on some systems the GPT
           may be in use for other purposes.
 
-config MXC_ULPI
-        bool
-
 config ARCH_HAS_RNGA
         bool
 
@@ -233,7 +230,7 @@ config MACH_EUKREA_CPUIMX25SD
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX25
 
 choice
@@ -284,7 +281,7 @@ config MACH_PCM038
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_MXC_W1
         select IMX_HAVE_PLATFORM_SPI_IMX
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX27
         help
           Include support for phyCORE-i.MX27 (aka pcm038) platform. This
@@ -314,7 +311,7 @@ config MACH_CPUIMX27
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_MXC_W1
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX27
         help
           Include support for Eukrea CPUIMX27 platform. This includes
@@ -369,7 +366,7 @@ config MACH_MX27_3DS
         select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_DEBUG_BOARD
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX27
         help
           Include support for MX27PDK platform. This includes specific
@@ -414,7 +411,7 @@ config MACH_PCA100
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_MXC_W1
         select IMX_HAVE_PLATFORM_SPI_IMX
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX27
         help
           Include support for phyCARD-s (aka pca100) platform. This
@@ -481,7 +478,7 @@ config MACH_MX31LILLY
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_SPI_IMX
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX31
         help
           Include support for mx31 based LILLY1131 modules. This includes
@@ -497,7 +494,7 @@ config MACH_MX31LITE
         select IMX_HAVE_PLATFORM_MXC_RTC
         select IMX_HAVE_PLATFORM_SPI_IMX
         select LEDS_GPIO_REGISTER
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX31
         help
           Include support for MX31 LITEKIT platform. This includes specific
@@ -514,7 +511,7 @@ config MACH_PCM037
         select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_MXC_W1
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX31
         help
           Include support for Phytec pcm037 platform. This includes
@@ -544,7 +541,7 @@ config MACH_MX31_3DS
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_DEBUG_BOARD
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX31
         help
           Include support for MX31PDK (3DS) platform. This includes specific
@@ -571,7 +568,7 @@ config MACH_MX31MOBOARD
         select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_SPI_IMX
         select LEDS_GPIO_REGISTER
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX31
         help
           Include support for mx31moboard platform. This includes specific
@@ -595,7 +592,7 @@ config MACH_ARMADILLO5X0
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_MXC_NAND
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX31
         help
           Include support for Atmark Armadillo-500 platform. This includes
@@ -639,7 +636,7 @@ config MACH_PCM043
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX35
         help
           Include support for Phytec pcm043 platform. This includes
@@ -673,7 +670,7 @@ config MACH_EUKREA_CPUIMX35SD
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX35
         help
           Include support for Eukrea CPUIMX35 platform. This includes
@@ -816,6 +813,40 @@ config SOC_IMX6Q
         help
           This enables support for Freescale i.MX6 Quad processor.
 
+config SOC_IMX6SL
+        bool "i.MX6 SoloLite support"
+        select ARM_ERRATA_754322
+        select ARM_ERRATA_775420
+        select ARM_GIC
+        select CPU_V7
+        select HAVE_IMX_ANATOP
+        select HAVE_IMX_GPC
+        select HAVE_IMX_MMDC
+        select HAVE_IMX_SRC
+        select PINCTRL
+        select PINCTRL_IMX6SL
+        select PL310_ERRATA_588369 if CACHE_PL310
+        select PL310_ERRATA_727915 if CACHE_PL310
+        select PL310_ERRATA_769419 if CACHE_PL310
+
+        help
+          This enables support for Freescale i.MX6 SoloLite processor.
+
+config SOC_VF610
+        bool "Vybrid Family VF610 support"
+        select CPU_V7
+        select ARM_GIC
+        select CLKSRC_OF
+        select PINCTRL
+        select PINCTRL_VF610
+        select VF_PIT_TIMER
+        select PL310_ERRATA_588369 if CACHE_PL310
+        select PL310_ERRATA_727915 if CACHE_PL310
+        select PL310_ERRATA_769419 if CACHE_PL310
+
+        help
+          This enable support for Freescale Vybrid VF610 processor.
+
 endif
 
 source "arch/arm/mach-imx/devices/Kconfig"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 70ae7c490ac0..e20f22d58fd8 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 obj-$(CONFIG_MXC_AVIC) += avic.o
 
-obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 
@@ -98,6 +97,7 @@ AFLAGS_headsmp.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SMP) += headsmp.o platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
 obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
+obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
 
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
@@ -111,4 +111,6 @@ obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
 obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
 obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
 
+obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
+
 obj-y += devices/
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 6fc486b6a3c6..04b1bad68350 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -73,6 +73,12 @@ static const char *mx53_cko2_sel[] = {
         "tve_sel", "lp_apm",
         "uart_root", "dummy"/* spdif0_clk_root */,
         "dummy", "dummy", };
+static const char *mx51_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", };
+static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw", };
+static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", };
+static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
+static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
+
 
 enum imx5_clks {
         dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
@@ -110,7 +116,9 @@ enum imx5_clks {
         owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate,
         cko1_sel, cko1_podf, cko1,
         cko2_sel, cko2_podf, cko2,
-        srtc_gate, pata_gate,
+        srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel,
+        spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf,
+        spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate,
         clk_max
 };
 
@@ -123,11 +131,13 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
 {
         int i;
 
+        of_clk_init(NULL);
+
         clk[dummy] = imx_clk_fixed("dummy", 0);
-        clk[ckil] = imx_clk_fixed("ckil", rate_ckil);
-        clk[osc] = imx_clk_fixed("osc", rate_osc);
-        clk[ckih1] = imx_clk_fixed("ckih1", rate_ckih1);
-        clk[ckih2] = imx_clk_fixed("ckih2", rate_ckih2);
+        clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil);
+        clk[osc] = imx_obtain_fixed_clock("osc", rate_osc);
+        clk[ckih1] = imx_obtain_fixed_clock("ckih1", rate_ckih1);
+        clk[ckih2] = imx_obtain_fixed_clock("ckih2", rate_ckih2);
 
         clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
                                 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
@@ -267,6 +277,13 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
         clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
         clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
+        clk[spdif0_sel] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
+        clk[spdif0_pred] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
+        clk[spdif0_podf] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
+        clk[spdif0_com_s] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
+                                spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
+        clk[spdif0_gate] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
+        clk[spdif_ipg_gate] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
 
         for (i = 0; i < ARRAY_SIZE(clk); i++)
                 if (IS_ERR(clk[i]))
@@ -378,6 +395,15 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
         clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
         clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
+        clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
+                                mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
+        clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
+                                spdif_sel, ARRAY_SIZE(spdif_sel));
+        clk[spdif1_pred] = imx_clk_divider("spdif1_podf", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
+        clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
+        clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
+                                mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
+        clk[spdif1_gate] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
 
         for (i = 0; i < ARRAY_SIZE(clk); i++)
                 if (IS_ERR(clk[i]))
@@ -485,6 +511,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
         clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
         clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
+        clk[sata_gate] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
 
         clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
                                 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
@@ -495,6 +522,8 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                                 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
         clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
         clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
+        clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
+                                mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
 
         for (i = 0; i < ARRAY_SIZE(clk); i++)
                 if (IS_ERR(clk[i]))
@@ -542,42 +571,12 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         return 0;
 }
 
-#ifdef CONFIG_OF
-static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
-                                   unsigned long *ckih1, unsigned long *ckih2)
-{
-        struct device_node *np;
-
-        /* retrieve the freqency of fixed clocks from device tree */
-        for_each_compatible_node(np, NULL, "fixed-clock") {
-                u32 rate;
-                if (of_property_read_u32(np, "clock-frequency", &rate))
-                        continue;
-
-                if (of_device_is_compatible(np, "fsl,imx-ckil"))
-                        *ckil = rate;
-                else if (of_device_is_compatible(np, "fsl,imx-osc"))
-                        *osc = rate;
-                else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
-                        *ckih1 = rate;
-                else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
-                        *ckih2 = rate;
-        }
-}
-
 int __init mx51_clocks_init_dt(void)
 {
-        unsigned long ckil, osc, ckih1, ckih2;
-
-        clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
-        return mx51_clocks_init(ckil, osc, ckih1, ckih2);
+        return mx51_clocks_init(0, 0, 0, 0);
 }
 
 int __init mx53_clocks_init_dt(void)
 {
-        unsigned long ckil, osc, ckih1, ckih2;
-
-        clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
-        return mx53_clocks_init(ckil, osc, ckih1, ckih2);
+        return mx53_clocks_init(0, 0, 0, 0);
 }
-#endif
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index dda9a2bd3acb..4282e99f5ca1 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -181,14 +181,14 @@ static const char *periph_clk2_sels[]	= { "pll3_usb_otg", "osc", "osc", "dummy",
 static const char *periph2_clk2_sels[]  = { "pll3_usb_otg", "pll2_bus", };
 static const char *periph_sels[]        = { "periph_pre", "periph_clk2", };
 static const char *periph2_sels[]       = { "periph2_pre", "periph2_clk2", };
-static const char *axi_sels[]           = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", };
+static const char *axi_sels[]           = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
 static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
 static const char *gpu_axi_sels[]       = { "axi", "ahb", };
 static const char *gpu2d_core_sels[]    = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
 static const char *gpu3d_core_sels[]    = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
 static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", };
 static const char *ipu_sels[]           = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
-static const char *ldb_di_sels[]        = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
+static const char *ldb_di_sels[]        = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
 static const char *ipu_di_pre_sels[]    = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
 static const char *ipu1_di0_sels[]      = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
 static const char *ipu1_di1_sels[]      = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
@@ -238,7 +238,7 @@ enum mx6q_clks {
         pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
         ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
         sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
-        usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max
+        usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, clk_max
 };
 
 static struct clk *clk[clk_max];
@@ -270,27 +270,16 @@ static struct clk_div_table video_div_table[] = {
         { }
 };
 
-int __init mx6q_clocks_init(void)
+static void __init imx6q_clocks_init(struct device_node *ccm_node)
 {
         struct device_node *np;
         void __iomem *base;
         int i, irq;
 
         clk[dummy] = imx_clk_fixed("dummy", 0);
-
-        /* retrieve the freqency of fixed clocks from device tree */
-        for_each_compatible_node(np, NULL, "fixed-clock") {
-                u32 rate;
-                if (of_property_read_u32(np, "clock-frequency", &rate))
-                        continue;
-
-                if (of_device_is_compatible(np, "fsl,imx-ckil"))
-                        clk[ckil] = imx_clk_fixed("ckil", rate);
-                else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
-                        clk[ckih] = imx_clk_fixed("ckih", rate);
-                else if (of_device_is_compatible(np, "fsl,imx-osc"))
-                        clk[osc] = imx_clk_fixed("osc", rate);
-        }
+        clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
+        clk[ckih] = imx_obtain_fixed_clock("ckih1", 0);
+        clk[osc] = imx_obtain_fixed_clock("osc", 0);
 
         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
         base = of_iomap(np, 0);
@@ -312,7 +301,6 @@ int __init mx6q_clocks_init(void)
         clk[pll5_video]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll5_video",   "osc", base + 0xa0, 0x7f);
         clk[pll6_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,      "pll6_enet",    "osc", base + 0xe0, 0x3);
         clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,       "pll7_usb_host","osc", base + 0x20, 0x3);
-        clk[pll8_mlb]      = imx_clk_pllv3(IMX_PLLV3_MLB,       "pll8_mlb",     "osc", base + 0xd0, 0x0);
 
         /*
          * Bit 20 is the reserved and read-only bit, we do this only for:
@@ -360,7 +348,7 @@ int __init mx6q_clocks_init(void)
         clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
         clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
 
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm");
+        np = ccm_node;
         base = of_iomap(np, 0);
         WARN_ON(!base);
         ccm_base = base;
@@ -481,7 +469,14 @@ int __init mx6q_clocks_init(void)
         clk[esai]         = imx_clk_gate2("esai",          "esai_podf",         base + 0x6c, 16);
         clk[gpt_ipg]      = imx_clk_gate2("gpt_ipg",       "ipg",               base + 0x6c, 20);
         clk[gpt_ipg_per]  = imx_clk_gate2("gpt_ipg_per",   "ipg_per",           base + 0x6c, 22);
-        clk[gpu2d_core]   = imx_clk_gate2("gpu2d_core",    "gpu2d_core_podf",   base + 0x6c, 24);
+        if (cpu_is_imx6dl())
+                /*
+                 * The multiplexer and divider of imx6q clock gpu3d_shader get
+                 * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl.
+                 */
+                clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
+        else
+                clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
         clk[gpu3d_core]   = imx_clk_gate2("gpu3d_core",    "gpu3d_core_podf",   base + 0x6c, 26);
         clk[hdmi_iahb]    = imx_clk_gate2("hdmi_iahb",     "ahb",               base + 0x70, 0);
         clk[hdmi_isfr]    = imx_clk_gate2("hdmi_isfr",     "pll3_pfd1_540m",    base + 0x70, 4);
@@ -499,7 +494,14 @@ int __init mx6q_clocks_init(void)
         clk[ldb_di1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);
         clk[ipu2_di1]     = imx_clk_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);
         clk[hsi_tx]       = imx_clk_gate2("hsi_tx",        "hsi_tx_podf",       base + 0x74, 16);
-        clk[mlb]          = imx_clk_gate2("mlb",           "axi",               base + 0x74, 18);
+        if (cpu_is_imx6dl())
+                /*
+                 * The multiplexer and divider of the imx6q clock gpu2d get
+                 * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
+                 */
+                clk[mlb] = imx_clk_gate2("mlb",            "gpu2d_core_podf",   base + 0x74, 18);
+        else
+                clk[mlb] = imx_clk_gate2("mlb",            "axi",               base + 0x74, 18);
         clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20);
         clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);
         clk[ocram]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);
@@ -528,6 +530,7 @@ int __init mx6q_clocks_init(void)
         clk[usdhc2]       = imx_clk_gate2("usdhc2",        "usdhc2_podf",       base + 0x80, 4);
         clk[usdhc3]       = imx_clk_gate2("usdhc3",        "usdhc3_podf",       base + 0x80, 6);
         clk[usdhc4]       = imx_clk_gate2("usdhc4",        "usdhc4_podf",       base + 0x80, 8);
+        clk[eim_slow]     = imx_clk_gate2("eim_slow",      "emi_slow_podf",     base + 0x80, 10);
         clk[vdo_axi]      = imx_clk_gate2("vdo_axi",       "vdo_axi_sel",       base + 0x80, 12);
         clk[vpu_axi]      = imx_clk_gate2("vpu_axi",       "vpu_axi_podf",      base + 0x80, 14);
         clk[cko1]         = imx_clk_gate("cko1",           "cko1_podf",         base + 0x60, 7);
@@ -547,6 +550,8 @@ int __init mx6q_clocks_init(void)
         clk_register_clkdev(clk[ahb], "ahb", NULL);
         clk_register_clkdev(clk[cko1], "cko1", NULL);
         clk_register_clkdev(clk[arm], NULL, "cpu0");
+        clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);
+        clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);
 
         if (imx6q_revision() != IMX_CHIP_REVISION_1_0) {
                 clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
@@ -576,6 +581,5 @@ int __init mx6q_clocks_init(void)
         WARN_ON(!base);
         irq = irq_of_parse_and_map(np, 0);
         mxc_timer_init(base, irq);
-
-        return 0;
 }
+CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
new file mode 100644
index 000000000000..a307ac22dffe
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -0,0 +1,267 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <dt-bindings/clock/imx6sl-clock.h>
+
+#include "clk.h"
+#include "common.h"
+
+static const char const *step_sels[]            = { "osc", "pll2_pfd2", };
+static const char const *pll1_sw_sels[]         = { "pll1_sys", "step", };
+static const char const *ocram_alt_sels[]       = { "pll2_pfd2", "pll3_pfd1", };
+static const char const *ocram_sels[]           = { "periph", "ocram_alt_sels", };
+static const char const *pre_periph_sels[]      = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", };
+static const char const *periph_clk2_sels[]     = { "pll3_usb_otg", "osc", "osc", "dummy", };
+static const char const *periph2_clk2_sels[]    = { "pll3_usb_otg", "pll2_bus", };
+static const char const *periph_sels[]          = { "pre_periph_sel", "periph_clk2_podf", };
+static const char const *periph2_sels[]         = { "pre_periph2_sel", "periph2_clk2_podf", };
+static const char const *csi_lcdif_sels[]       = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
+static const char const *usdhc_sels[]           = { "pll2_pfd2", "pll2_pfd0", };
+static const char const *ssi_sels[]             = { "pll3_pfd2", "pll3_pfd3", "pll4_post_div", "dummy", };
+static const char const *perclk_sels[]          = { "ipg", "osc", };
+static const char const *epdc_pxp_sels[]        = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
+static const char const *gpu2d_ovg_sels[]       = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
+static const char const *gpu2d_sels[]           = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
+static const char const *lcdif_pix_sels[]       = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
+static const char const *epdc_pix_sels[]        = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
+static const char const *audio_sels[]           = { "pll4_post_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
+static const char const *ecspi_sels[]           = { "pll3_60m", "osc", };
+static const char const *uart_sels[]            = { "pll3_80m", "osc", };
+
+static struct clk_div_table clk_enet_ref_table[] = {
+        { .val = 0, .div = 20, },
+        { .val = 1, .div = 10, },
+        { .val = 2, .div = 5, },
+        { .val = 3, .div = 4, },
+        { }
+};
+
+static struct clk_div_table post_div_table[] = {
+        { .val = 2, .div = 1, },
+        { .val = 1, .div = 2, },
+        { .val = 0, .div = 4, },
+        { }
+};
+
+static struct clk_div_table video_div_table[] = {
+        { .val = 0, .div = 1, },
+        { .val = 1, .div = 2, },
+        { .val = 2, .div = 1, },
+        { .val = 3, .div = 4, },
+        { }
+};
+
+static struct clk *clks[IMX6SL_CLK_CLK_END];
+static struct clk_onecell_data clk_data;
+
+static void __init imx6sl_clocks_init(struct device_node *ccm_node)
+{
+        struct device_node *np;
+        void __iomem *base;
+        int irq;
+        int i;
+
+        clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
+        clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
+        clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+
+        /*                                             type               name            parent  base         div_mask */
+        clks[IMX6SL_CLK_PLL1_SYS]      = imx_clk_pllv3(IMX_PLLV3_SYS,     "pll1_sys",      "osc", base,        0x7f);
+        clks[IMX6SL_CLK_PLL2_BUS]      = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus",      "osc", base + 0x30, 0x1);
+        clks[IMX6SL_CLK_PLL3_USB_OTG]  = imx_clk_pllv3(IMX_PLLV3_USB,     "pll3_usb_otg",  "osc", base + 0x10, 0x3);
+        clks[IMX6SL_CLK_PLL4_AUDIO]    = imx_clk_pllv3(IMX_PLLV3_AV,      "pll4_audio",    "osc", base + 0x70, 0x7f);
+        clks[IMX6SL_CLK_PLL5_VIDEO]    = imx_clk_pllv3(IMX_PLLV3_AV,      "pll5_video",    "osc", base + 0xa0, 0x7f);
+        clks[IMX6SL_CLK_PLL6_ENET]     = imx_clk_pllv3(IMX_PLLV3_ENET,    "pll6_enet",     "osc", base + 0xe0, 0x3);
+        clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll7_usb_host", "osc", base + 0x20, 0x3);
+
+        /*
+         * usbphy1 and usbphy2 are implemented as dummy gates using reserve
+         * bit 20.  They are used by phy driver to keep the refcount of
+         * parent PLL correct. usbphy1_gate and usbphy2_gate only needs to be
+         * turned on during boot, and software will not need to control it
+         * anymore after that.
+         */
+        clks[IMX6SL_CLK_USBPHY1]      = imx_clk_gate("usbphy1",      "pll3_usb_otg",  base + 0x10, 20);
+        clks[IMX6SL_CLK_USBPHY2]      = imx_clk_gate("usbphy2",      "pll7_usb_host", base + 0x20, 20);
+        clks[IMX6SL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy",         base + 0x10, 6);
+        clks[IMX6SL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy",         base + 0x20, 6);
+
+        /*                                                           dev   name              parent_name      flags                reg        shift width div: flags, div_table lock */
+        clks[IMX6SL_CLK_PLL4_POST_DIV]  = clk_register_divider_table(NULL, "pll4_post_div",  "pll4_audio",    CLK_SET_RATE_PARENT, base + 0x70,  19, 2,   0, post_div_table, &imx_ccm_lock);
+        clks[IMX6SL_CLK_PLL5_POST_DIV]  = clk_register_divider_table(NULL, "pll5_post_div",  "pll5_video",    CLK_SET_RATE_PARENT, base + 0xa0,  19, 2,   0, post_div_table, &imx_ccm_lock);
+        clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2,   0, video_div_table, &imx_ccm_lock);
+        clks[IMX6SL_CLK_ENET_REF]       = clk_register_divider_table(NULL, "enet_ref",       "pll6_enet",     0,                   base + 0xe0,  0,  2,   0, clk_enet_ref_table, &imx_ccm_lock);
+
+        /*                                       name         parent_name     reg           idx */
+        clks[IMX6SL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0", "pll2_bus",     base + 0x100, 0);
+        clks[IMX6SL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus",     base + 0x100, 1);
+        clks[IMX6SL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus",     base + 0x100, 2);
+        clks[IMX6SL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0", "pll3_usb_otg", base + 0xf0,  0);
+        clks[IMX6SL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", base + 0xf0,  1);
+        clks[IMX6SL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", base + 0xf0,  2);
+        clks[IMX6SL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", base + 0xf0,  3);
+
+        /*                                                name         parent_name     mult div */
+        clks[IMX6SL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2",      1, 2);
+        clks[IMX6SL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg",   1, 4);
+        clks[IMX6SL_CLK_PLL3_80M]  = imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6);
+        clks[IMX6SL_CLK_PLL3_60M]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
+
+        np = ccm_node;
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+
+        /*                                              name                reg       shift width parent_names     num_parents */
+        clks[IMX6SL_CLK_STEP]             = imx_clk_mux("step",             base + 0xc,  8,  1, step_sels,         ARRAY_SIZE(step_sels));
+        clks[IMX6SL_CLK_PLL1_SW]          = imx_clk_mux("pll1_sw",          base + 0xc,  2,  1, pll1_sw_sels,      ARRAY_SIZE(pll1_sw_sels));
+        clks[IMX6SL_CLK_OCRAM_ALT_SEL]    = imx_clk_mux("ocram_alt_sel",    base + 0x14, 7,  1, ocram_alt_sels,    ARRAY_SIZE(ocram_alt_sels));
+        clks[IMX6SL_CLK_OCRAM_SEL]        = imx_clk_mux("ocram_sel",        base + 0x14, 6,  1, ocram_sels,        ARRAY_SIZE(ocram_sels));
+        clks[IMX6SL_CLK_PRE_PERIPH2_SEL]  = imx_clk_mux("pre_periph2_sel",  base + 0x18, 21, 2, pre_periph_sels,   ARRAY_SIZE(pre_periph_sels));
+        clks[IMX6SL_CLK_PRE_PERIPH_SEL]   = imx_clk_mux("pre_periph_sel",   base + 0x18, 18, 2, pre_periph_sels,   ARRAY_SIZE(pre_periph_sels));
+        clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
+        clks[IMX6SL_CLK_PERIPH_CLK2_SEL]  = imx_clk_mux("periph_clk2_sel",  base + 0x18, 12, 2, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
+        clks[IMX6SL_CLK_CSI_SEL]          = imx_clk_mux("csi_sel",          base + 0x3c, 9,  2, csi_lcdif_sels,    ARRAY_SIZE(csi_lcdif_sels));
+        clks[IMX6SL_CLK_LCDIF_AXI_SEL]    = imx_clk_mux("lcdif_axi_sel",    base + 0x3c, 14, 2, csi_lcdif_sels,    ARRAY_SIZE(csi_lcdif_sels));
+        clks[IMX6SL_CLK_USDHC1_SEL]       = imx_clk_mux("usdhc1_sel",       base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clks[IMX6SL_CLK_USDHC2_SEL]       = imx_clk_mux("usdhc2_sel",       base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clks[IMX6SL_CLK_USDHC3_SEL]       = imx_clk_mux("usdhc3_sel",       base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clks[IMX6SL_CLK_USDHC4_SEL]       = imx_clk_mux("usdhc4_sel",       base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clks[IMX6SL_CLK_SSI1_SEL]         = imx_clk_mux("ssi1_sel",         base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+        clks[IMX6SL_CLK_SSI2_SEL]         = imx_clk_mux("ssi2_sel",         base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+        clks[IMX6SL_CLK_SSI3_SEL]         = imx_clk_mux("ssi3_sel",         base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+        clks[IMX6SL_CLK_PERCLK_SEL]       = imx_clk_mux("perclk_sel",       base + 0x1c, 6,  1, perclk_sels,       ARRAY_SIZE(perclk_sels));
+        clks[IMX6SL_CLK_PXP_AXI_SEL]      = imx_clk_mux("pxp_axi_sel",      base + 0x34, 6,  3, epdc_pxp_sels,     ARRAY_SIZE(epdc_pxp_sels));
+        clks[IMX6SL_CLK_EPDC_AXI_SEL]     = imx_clk_mux("epdc_axi_sel",     base + 0x34, 15, 3, epdc_pxp_sels,     ARRAY_SIZE(epdc_pxp_sels));
+        clks[IMX6SL_CLK_GPU2D_OVG_SEL]    = imx_clk_mux("gpu2d_ovg_sel",    base + 0x18, 4,  2, gpu2d_ovg_sels,    ARRAY_SIZE(gpu2d_ovg_sels));
+        clks[IMX6SL_CLK_GPU2D_SEL]        = imx_clk_mux("gpu2d_sel",        base + 0x18, 8,  2, gpu2d_sels,        ARRAY_SIZE(gpu2d_sels));
+        clks[IMX6SL_CLK_LCDIF_PIX_SEL]    = imx_clk_mux("lcdif_pix_sel",    base + 0x38, 6,  3, lcdif_pix_sels,    ARRAY_SIZE(lcdif_pix_sels));
+        clks[IMX6SL_CLK_EPDC_PIX_SEL]     = imx_clk_mux("epdc_pix_sel",     base + 0x38, 15, 3, epdc_pix_sels,     ARRAY_SIZE(epdc_pix_sels));
+        clks[IMX6SL_CLK_SPDIF0_SEL]       = imx_clk_mux("spdif0_sel",       base + 0x30, 20, 2, audio_sels,        ARRAY_SIZE(audio_sels));
+        clks[IMX6SL_CLK_SPDIF1_SEL]       = imx_clk_mux("spdif1_sel",       base + 0x30, 7,  2, audio_sels,        ARRAY_SIZE(audio_sels));
+        clks[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x20, 19, 2, audio_sels,        ARRAY_SIZE(audio_sels));
+        clks[IMX6SL_CLK_ECSPI_SEL]        = imx_clk_mux("ecspi_sel",        base + 0x38, 18, 1, ecspi_sels,        ARRAY_SIZE(ecspi_sels));
+        clks[IMX6SL_CLK_UART_SEL]         = imx_clk_mux("uart_sel",         base + 0x24, 6,  1, uart_sels,         ARRAY_SIZE(uart_sels));
+
+        /*                                          name       reg        shift width busy: reg, shift parent_names  num_parents */
+        clks[IMX6SL_CLK_PERIPH]  = imx_clk_busy_mux("periph",  base + 0x14, 25,  1,   base + 0x48, 5,  periph_sels,  ARRAY_SIZE(periph_sels));
+        clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26,  1,   base + 0x48, 3,  periph2_sels, ARRAY_SIZE(periph2_sels));
+
+        /*                                                   name                 parent_name          reg       shift width */
+        clks[IMX6SL_CLK_OCRAM_PODF]        = imx_clk_divider("ocram_podf",        "ocram_sel",         base + 0x14, 16, 3);
+        clks[IMX6SL_CLK_PERIPH_CLK2_PODF]  = imx_clk_divider("periph_clk2_podf",  "periph_clk2_sel",   base + 0x14, 27, 3);
+        clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel",  base + 0x14, 0,  3);
+        clks[IMX6SL_CLK_IPG]               = imx_clk_divider("ipg",               "ahb",               base + 0x14, 8,  2);
+        clks[IMX6SL_CLK_CSI_PODF]          = imx_clk_divider("csi_podf",          "csi_sel",           base + 0x3c, 11, 3);
+        clks[IMX6SL_CLK_LCDIF_AXI_PODF]    = imx_clk_divider("lcdif_axi_podf",    "lcdif_axi_sel",     base + 0x3c, 16, 3);
+        clks[IMX6SL_CLK_USDHC1_PODF]       = imx_clk_divider("usdhc1_podf",       "usdhc1_sel",        base + 0x24, 11, 3);
+        clks[IMX6SL_CLK_USDHC2_PODF]       = imx_clk_divider("usdhc2_podf",       "usdhc2_sel",        base + 0x24, 16, 3);
+        clks[IMX6SL_CLK_USDHC3_PODF]       = imx_clk_divider("usdhc3_podf",       "usdhc3_sel",        base + 0x24, 19, 3);
+        clks[IMX6SL_CLK_USDHC4_PODF]       = imx_clk_divider("usdhc4_podf",       "usdhc4_sel",        base + 0x24, 22, 3);
+        clks[IMX6SL_CLK_SSI1_PRED]         = imx_clk_divider("ssi1_pred",         "ssi1_sel",          base + 0x28, 6,  3);
+        clks[IMX6SL_CLK_SSI1_PODF]         = imx_clk_divider("ssi1_podf",         "ssi1_pred",         base + 0x28, 0,  6);
+        clks[IMX6SL_CLK_SSI2_PRED]         = imx_clk_divider("ssi2_pred",         "ssi2_sel",          base + 0x2c, 6,  3);
+        clks[IMX6SL_CLK_SSI2_PODF]         = imx_clk_divider("ssi2_podf",         "ssi2_pred",         base + 0x2c, 0,  6);
+        clks[IMX6SL_CLK_SSI3_PRED]         = imx_clk_divider("ssi3_pred",         "ssi3_sel",          base + 0x28, 22, 3);
+        clks[IMX6SL_CLK_SSI3_PODF]         = imx_clk_divider("ssi3_podf",         "ssi3_pred",         base + 0x28, 16, 6);
+        clks[IMX6SL_CLK_PERCLK]            = imx_clk_divider("perclk",            "perclk_sel",        base + 0x1c, 0,  6);
+        clks[IMX6SL_CLK_PXP_AXI_PODF]      = imx_clk_divider("pxp_axi_podf",      "pxp_axi_sel",       base + 0x34, 3,  3);
+        clks[IMX6SL_CLK_EPDC_AXI_PODF]     = imx_clk_divider("epdc_axi_podf",     "epdc_axi_sel",      base + 0x34, 12, 3);
+        clks[IMX6SL_CLK_GPU2D_OVG_PODF]    = imx_clk_divider("gpu2d_ovg_podf",    "gpu2d_ovg_sel",     base + 0x18, 26, 3);
+        clks[IMX6SL_CLK_GPU2D_PODF]        = imx_clk_divider("gpu2d_podf",        "gpu2d_sel",         base + 0x18, 29, 3);
+        clks[IMX6SL_CLK_LCDIF_PIX_PRED]    = imx_clk_divider("lcdif_pix_pred",    "lcdif_pix_sel",     base + 0x38, 3,  3);
+        clks[IMX6SL_CLK_EPDC_PIX_PRED]     = imx_clk_divider("epdc_pix_pred",     "epdc_pix_sel",      base + 0x38, 12, 3);
+        clks[IMX6SL_CLK_LCDIF_PIX_PODF]    = imx_clk_divider("lcdif_pix_podf",    "lcdif_pix_pred",    base + 0x1c, 20, 3);
+        clks[IMX6SL_CLK_EPDC_PIX_PODF]     = imx_clk_divider("epdc_pix_podf",     "epdc_pix_pred",     base + 0x18, 23, 3);
+        clks[IMX6SL_CLK_SPDIF0_PRED]       = imx_clk_divider("spdif0_pred",       "spdif0_sel",        base + 0x30, 25, 3);
+        clks[IMX6SL_CLK_SPDIF0_PODF]       = imx_clk_divider("spdif0_podf",       "spdif0_pred",       base + 0x30, 22, 3);
+        clks[IMX6SL_CLK_SPDIF1_PRED]       = imx_clk_divider("spdif1_pred",       "spdif1_sel",        base + 0x30, 12, 3);
+        clks[IMX6SL_CLK_SPDIF1_PODF]       = imx_clk_divider("spdif1_podf",       "spdif1_pred",       base + 0x30, 9,  3);
+        clks[IMX6SL_CLK_EXTERN_AUDIO_PRED] = imx_clk_divider("extern_audio_pred", "extern_audio_sel",  base + 0x28, 9,  3);
+        clks[IMX6SL_CLK_EXTERN_AUDIO_PODF] = imx_clk_divider("extern_audio_podf", "extern_audio_pred", base + 0x28, 25, 3);
+        clks[IMX6SL_CLK_ECSPI_ROOT]        = imx_clk_divider("ecspi_root",        "ecspi_sel",         base + 0x38, 19, 6);
+        clks[IMX6SL_CLK_UART_ROOT]         = imx_clk_divider("uart_root",         "uart_sel",          base + 0x24, 0,  6);
+
+        /*                                                name         parent_name reg       shift width busy: reg, shift */
+        clks[IMX6SL_CLK_AHB]       = imx_clk_busy_divider("ahb",       "periph",  base + 0x14, 10, 3,    base + 0x48, 1);
+        clks[IMX6SL_CLK_MMDC_ROOT] = imx_clk_busy_divider("mmdc",      "periph2", base + 0x14, 3,  3,    base + 0x48, 2);
+        clks[IMX6SL_CLK_ARM]       = imx_clk_busy_divider("arm",       "pll1_sw", base + 0x10, 0,  3,    base + 0x48, 16);
+
+        /*                                            name            parent_name          reg         shift */
+        clks[IMX6SL_CLK_ECSPI1]       = imx_clk_gate2("ecspi1",       "ecspi_root",        base + 0x6c, 0);
+        clks[IMX6SL_CLK_ECSPI2]       = imx_clk_gate2("ecspi2",       "ecspi_root",        base + 0x6c, 2);
+        clks[IMX6SL_CLK_ECSPI3]       = imx_clk_gate2("ecspi3",       "ecspi_root",        base + 0x6c, 4);
+        clks[IMX6SL_CLK_ECSPI4]       = imx_clk_gate2("ecspi4",       "ecspi_root",        base + 0x6c, 6);
+        clks[IMX6SL_CLK_EPIT1]        = imx_clk_gate2("epit1",        "perclk",            base + 0x6c, 12);
+        clks[IMX6SL_CLK_EPIT2]        = imx_clk_gate2("epit2",        "perclk",            base + 0x6c, 14);
+        clks[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16);
+        clks[IMX6SL_CLK_GPT]          = imx_clk_gate2("gpt",          "perclk",            base + 0x6c, 20);
+        clks[IMX6SL_CLK_GPT_SERIAL]   = imx_clk_gate2("gpt_serial",   "perclk",            base + 0x6c, 22);
+        clks[IMX6SL_CLK_GPU2D_OVG]    = imx_clk_gate2("gpu2d_ovg",    "gpu2d_ovg_podf",    base + 0x6c, 26);
+        clks[IMX6SL_CLK_I2C1]         = imx_clk_gate2("i2c1",         "perclk",            base + 0x70, 6);
+        clks[IMX6SL_CLK_I2C2]         = imx_clk_gate2("i2c2",         "perclk",            base + 0x70, 8);
+        clks[IMX6SL_CLK_I2C3]         = imx_clk_gate2("i2c3",         "perclk",            base + 0x70, 10);
+        clks[IMX6SL_CLK_OCOTP]        = imx_clk_gate2("ocotp",        "ipg",               base + 0x70, 12);
+        clks[IMX6SL_CLK_CSI]          = imx_clk_gate2("csi",          "csi_podf",          base + 0x74, 0);
+        clks[IMX6SL_CLK_PXP_AXI]      = imx_clk_gate2("pxp_axi",      "pxp_axi_podf",      base + 0x74, 2);
+        clks[IMX6SL_CLK_EPDC_AXI]     = imx_clk_gate2("epdc_axi",     "epdc_axi_podf",     base + 0x74, 4);
+        clks[IMX6SL_CLK_LCDIF_AXI]    = imx_clk_gate2("lcdif_axi",    "lcdif_axi_podf",    base + 0x74, 6);
+        clks[IMX6SL_CLK_LCDIF_PIX]    = imx_clk_gate2("lcdif_pix",    "lcdif_pix_podf",    base + 0x74, 8);
+        clks[IMX6SL_CLK_EPDC_PIX]     = imx_clk_gate2("epdc_pix",     "epdc_pix_podf",     base + 0x74, 10);
+        clks[IMX6SL_CLK_OCRAM]        = imx_clk_gate2("ocram",        "ocram_podf",        base + 0x74, 28);
+        clks[IMX6SL_CLK_PWM1]         = imx_clk_gate2("pwm1",         "perclk",            base + 0x78, 16);
+        clks[IMX6SL_CLK_PWM2]         = imx_clk_gate2("pwm2",         "perclk",            base + 0x78, 18);
+        clks[IMX6SL_CLK_PWM3]         = imx_clk_gate2("pwm3",         "perclk",            base + 0x78, 20);
+        clks[IMX6SL_CLK_PWM4]         = imx_clk_gate2("pwm4",         "perclk",            base + 0x78, 22);
+        clks[IMX6SL_CLK_SDMA]         = imx_clk_gate2("sdma",         "ipg",               base + 0x7c, 6);
+        clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2("spdif",        "spdif0_podf",       base + 0x7c, 14);
+        clks[IMX6SL_CLK_SSI1]         = imx_clk_gate2("ssi1",         "ssi1_podf",         base + 0x7c, 18);
+        clks[IMX6SL_CLK_SSI2]         = imx_clk_gate2("ssi2",         "ssi2_podf",         base + 0x7c, 20);
+        clks[IMX6SL_CLK_SSI3]         = imx_clk_gate2("ssi3",         "ssi3_podf",         base + 0x7c, 22);
+        clks[IMX6SL_CLK_UART]         = imx_clk_gate2("uart",         "ipg",               base + 0x7c, 24);
+        clks[IMX6SL_CLK_UART_SERIAL]  = imx_clk_gate2("uart_serial",  "uart_root",         base + 0x7c, 26);
+        clks[IMX6SL_CLK_USBOH3]       = imx_clk_gate2("usboh3",       "ipg",               base + 0x80, 0);
+        clks[IMX6SL_CLK_USDHC1]       = imx_clk_gate2("usdhc1",       "usdhc1_podf",       base + 0x80, 2);
+        clks[IMX6SL_CLK_USDHC2]       = imx_clk_gate2("usdhc2",       "usdhc2_podf",       base + 0x80, 4);
+        clks[IMX6SL_CLK_USDHC3]       = imx_clk_gate2("usdhc3",       "usdhc3_podf",       base + 0x80, 6);
+        clks[IMX6SL_CLK_USDHC4]       = imx_clk_gate2("usdhc4",       "usdhc4_podf",       base + 0x80, 8);
+
+        for (i = 0; i < ARRAY_SIZE(clks); i++)
+                if (IS_ERR(clks[i]))
+                        pr_err("i.MX6SL clk %d: register failed with %ld\n",
+                                i, PTR_ERR(clks[i]));
+
+        clk_data.clks = clks;
+        clk_data.clk_num = ARRAY_SIZE(clks);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+        clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
+
+        if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
+                clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
+                clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
+        }
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+        irq = irq_of_parse_and_map(np, 0);
+        mxc_timer_init(base, irq);
+}
+CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index d09bc3df9a7a..a9fad5f8d340 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -296,13 +296,6 @@ static const struct clk_ops clk_pllv3_enet_ops = {
         .recalc_rate    = clk_pllv3_enet_recalc_rate,
 };
 
-static const struct clk_ops clk_pllv3_mlb_ops = {
-        .prepare        = clk_pllv3_prepare,
-        .unprepare      = clk_pllv3_unprepare,
-        .enable         = clk_pllv3_enable,
-        .disable        = clk_pllv3_disable,
-};
-
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
                           const char *parent_name, void __iomem *base,
                           u32 div_mask)
@@ -330,9 +323,6 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
         case IMX_PLLV3_ENET:
                 ops = &clk_pllv3_enet_ops;
                 break;
-        case IMX_PLLV3_MLB:
-                ops = &clk_pllv3_mlb_ops;
-                break;
         default:
                 ops = &clk_pllv3_ops;
         }
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
new file mode 100644
index 000000000000..d617c0b7c809
--- /dev/null
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -0,0 +1,319 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/of_address.h>
+#include <linux/clk.h>
+#include <dt-bindings/clock/vf610-clock.h>
+
+#include "clk.h"
+
+#define CCM_CCR                 (ccm_base + 0x00)
+#define CCM_CSR                 (ccm_base + 0x04)
+#define CCM_CCSR                (ccm_base + 0x08)
+#define CCM_CACRR               (ccm_base + 0x0c)
+#define CCM_CSCMR1              (ccm_base + 0x10)
+#define CCM_CSCDR1              (ccm_base + 0x14)
+#define CCM_CSCDR2              (ccm_base + 0x18)
+#define CCM_CSCDR3              (ccm_base + 0x1c)
+#define CCM_CSCMR2              (ccm_base + 0x20)
+#define CCM_CSCDR4              (ccm_base + 0x24)
+#define CCM_CLPCR               (ccm_base + 0x2c)
+#define CCM_CISR                (ccm_base + 0x30)
+#define CCM_CIMR                (ccm_base + 0x34)
+#define CCM_CGPR                (ccm_base + 0x3c)
+#define CCM_CCGR0               (ccm_base + 0x40)
+#define CCM_CCGR1               (ccm_base + 0x44)
+#define CCM_CCGR2               (ccm_base + 0x48)
+#define CCM_CCGR3               (ccm_base + 0x4c)
+#define CCM_CCGR4               (ccm_base + 0x50)
+#define CCM_CCGR5               (ccm_base + 0x54)
+#define CCM_CCGR6               (ccm_base + 0x58)
+#define CCM_CCGR7               (ccm_base + 0x5c)
+#define CCM_CCGR8               (ccm_base + 0x60)
+#define CCM_CCGR9               (ccm_base + 0x64)
+#define CCM_CCGR10              (ccm_base + 0x68)
+#define CCM_CCGR11              (ccm_base + 0x6c)
+#define CCM_CMEOR0              (ccm_base + 0x70)
+#define CCM_CMEOR1              (ccm_base + 0x74)
+#define CCM_CMEOR2              (ccm_base + 0x78)
+#define CCM_CMEOR3              (ccm_base + 0x7c)
+#define CCM_CMEOR4              (ccm_base + 0x80)
+#define CCM_CMEOR5              (ccm_base + 0x84)
+#define CCM_CPPDSR              (ccm_base + 0x88)
+#define CCM_CCOWR               (ccm_base + 0x8c)
+#define CCM_CCPGR0              (ccm_base + 0x90)
+#define CCM_CCPGR1              (ccm_base + 0x94)
+#define CCM_CCPGR2              (ccm_base + 0x98)
+#define CCM_CCPGR3              (ccm_base + 0x9c)
+
+#define CCM_CCGRx_CGn(n)        ((n) * 2)
+
+#define PFD_PLL1_BASE           (anatop_base + 0x2b0)
+#define PFD_PLL2_BASE           (anatop_base + 0x100)
+#define PFD_PLL3_BASE           (anatop_base + 0xf0)
+
+static void __iomem *anatop_base;
+static void __iomem *ccm_base;
+
+/* sources for multiplexer clocks, this is used multiple times */
+static const char const *fast_sels[]    = { "firc", "fxosc", };
+static const char const *slow_sels[]    = { "sirc_32k", "sxosc", };
+static const char const *pll1_sels[]    = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
+static const char const *pll2_sels[]    = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
+static const char const *sys_sels[]     = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", };
+static const char const *ddr_sels[]     = { "pll2_pfd2", "sys_sel", };
+static const char const *rmii_sels[]    = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", };
+static const char const *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", };
+static const char const *esai_sels[]    = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
+static const char const *sai_sels[]     = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
+static const char const *nfc_sels[]     = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", };
+static const char const *qspi_sels[]    = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
+static const char const *esdhc_sels[]   = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
+static const char const *dcu_sels[]     = { "pll1_pfd2", "pll3_main", };
+static const char const *gpu_sels[]     = { "pll2_pfd2", "pll3_pfd2", };
+static const char const *vadc_sels[]    = { "pll6_main_div", "pll3_main_div", "pll3_main", };
+/* FTM counter clock source, not module clock */
+static const char const *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
+static const char const *ftm_fix_sels[] = { "sxosc", "ipg_bus", };
+
+static struct clk_div_table pll4_main_div_table[] = {
+        { .val = 0, .div = 1 },
+        { .val = 1, .div = 2 },
+        { .val = 2, .div = 6 },
+        { .val = 3, .div = 8 },
+        { .val = 4, .div = 10 },
+        { .val = 5, .div = 12 },
+        { .val = 6, .div = 14 },
+        { .val = 7, .div = 16 },
+        { }
+};
+
+static struct clk *clk[VF610_CLK_END];
+static struct clk_onecell_data clk_data;
+
+static void __init vf610_clocks_init(struct device_node *ccm_node)
+{
+        struct device_node *np;
+
+        clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
+        clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000);
+        clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000);
+        clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000);
+
+        clk[VF610_CLK_SXOSC] = imx_obtain_fixed_clock("sxosc", 0);
+        clk[VF610_CLK_FXOSC] = imx_obtain_fixed_clock("fxosc", 0);
+        clk[VF610_CLK_AUDIO_EXT] = imx_obtain_fixed_clock("audio_ext", 0);
+        clk[VF610_CLK_ENET_EXT] = imx_obtain_fixed_clock("enet_ext", 0);
+
+        clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2);
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,vf610-anatop");
+        anatop_base = of_iomap(np, 0);
+        BUG_ON(!anatop_base);
+
+        np = ccm_node;
+        ccm_base = of_iomap(np, 0);
+        BUG_ON(!ccm_base);
+
+        clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels));
+        clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels));
+
+        clk[VF610_CLK_PLL1_MAIN] = imx_clk_fixed_factor("pll1_main", "fast_clk_sel", 22, 1);
+        clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_main", PFD_PLL1_BASE, 0);
+        clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_main", PFD_PLL1_BASE, 1);
+        clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_main", PFD_PLL1_BASE, 2);
+        clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_main", PFD_PLL1_BASE, 3);
+
+        clk[VF610_CLK_PLL2_MAIN] = imx_clk_fixed_factor("pll2_main", "fast_clk_sel", 22, 1);
+        clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_main", PFD_PLL2_BASE, 0);
+        clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_main", PFD_PLL2_BASE, 1);
+        clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_main", PFD_PLL2_BASE, 2);
+        clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_main", PFD_PLL2_BASE, 3);
+
+        clk[VF610_CLK_PLL3_MAIN] = imx_clk_fixed_factor("pll3_main", "fast_clk_sel", 20, 1);
+        clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_main", PFD_PLL3_BASE, 0);
+        clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_main", PFD_PLL3_BASE, 1);
+        clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_main", PFD_PLL3_BASE, 2);
+        clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_main", PFD_PLL3_BASE, 3);
+
+        clk[VF610_CLK_PLL4_MAIN] = imx_clk_fixed_factor("pll4_main", "fast_clk_sel", 25, 1);
+        /* Enet pll: fixed 50Mhz */
+        clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6);
+        /* pll6: default 960Mhz */
+        clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1);
+        clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5);
+        clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5);
+        clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels));
+        clk[VF610_CLK_DDR_SEL] = imx_clk_mux("ddr_sel", CCM_CCSR, 6, 1, ddr_sels, ARRAY_SIZE(ddr_sels));
+        clk[VF610_CLK_SYS_BUS] = imx_clk_divider("sys_bus", "sys_sel", CCM_CACRR, 0, 3);
+        clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3);
+        clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2);
+
+        clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_main_div", "pll3_main", CCM_CACRR, 20, 1);
+        clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock);
+        clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1);
+
+        clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4));
+        clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4));
+
+        clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4);
+        clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4);
+        clk[VF610_CLK_QSPI0_X4_DIV] = imx_clk_divider("qspi0_x4", "qspi0_en", CCM_CSCDR3, 0, 2);
+        clk[VF610_CLK_QSPI0_X2_DIV] = imx_clk_divider("qspi0_x2", "qspi0_x4", CCM_CSCDR3, 2, 1);
+        clk[VF610_CLK_QSPI0_X1_DIV] = imx_clk_divider("qspi0_x1", "qspi0_x2", CCM_CSCDR3, 3, 1);
+        clk[VF610_CLK_QSPI0] = imx_clk_gate2("qspi0", "qspi0_x1", CCM_CCGR2, CCM_CCGRx_CGn(4));
+
+        clk[VF610_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", CCM_CSCMR1, 24, 2, qspi_sels, 4);
+        clk[VF610_CLK_QSPI1_EN] = imx_clk_gate("qspi1_en", "qspi1_sel", CCM_CSCDR3, 12);
+        clk[VF610_CLK_QSPI1_X4_DIV] = imx_clk_divider("qspi1_x4", "qspi1_en", CCM_CSCDR3, 8, 2);
+        clk[VF610_CLK_QSPI1_X2_DIV] = imx_clk_divider("qspi1_x2", "qspi1_x4", CCM_CSCDR3, 10, 1);
+        clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1);
+        clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4));
+
+        clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_main", 1, 10);
+        clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_main", 1, 20);
+        clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4);
+        clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7);
+        clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24);
+        clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);
+
+        clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
+
+        clk[VF610_CLK_UART0] = imx_clk_gate2("uart0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7));
+        clk[VF610_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8));
+        clk[VF610_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9));
+        clk[VF610_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10));
+
+        clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6));
+        clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7));
+
+        clk[VF610_CLK_DSPI0] = imx_clk_gate2("dspi0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(12));
+        clk[VF610_CLK_DSPI1] = imx_clk_gate2("dspi1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(13));
+        clk[VF610_CLK_DSPI2] = imx_clk_gate2("dspi2", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(12));
+        clk[VF610_CLK_DSPI3] = imx_clk_gate2("dspi3", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(13));
+
+        clk[VF610_CLK_WDT] = imx_clk_gate2("wdt", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(14));
+
+        clk[VF610_CLK_ESDHC0_SEL] = imx_clk_mux("esdhc0_sel", CCM_CSCMR1, 16, 2, esdhc_sels, 4);
+        clk[VF610_CLK_ESDHC0_EN] = imx_clk_gate("esdhc0_en", "esdhc0_sel", CCM_CSCDR2, 28);
+        clk[VF610_CLK_ESDHC0_DIV] = imx_clk_divider("esdhc0_div", "esdhc0_en", CCM_CSCDR2, 16, 4);
+        clk[VF610_CLK_ESDHC0] = imx_clk_gate2("eshc0", "esdhc0_div", CCM_CCGR7, CCM_CCGRx_CGn(1));
+
+        clk[VF610_CLK_ESDHC1_SEL] = imx_clk_mux("esdhc1_sel", CCM_CSCMR1, 18, 2, esdhc_sels, 4);
+        clk[VF610_CLK_ESDHC1_EN] = imx_clk_gate("esdhc1_en", "esdhc1_sel", CCM_CSCDR2, 29);
+        clk[VF610_CLK_ESDHC1_DIV] = imx_clk_divider("esdhc1_div", "esdhc1_en", CCM_CSCDR2, 20, 4);
+        clk[VF610_CLK_ESDHC1] = imx_clk_gate2("eshc1", "esdhc1_div", CCM_CCGR7, CCM_CCGRx_CGn(2));
+
+        /*
+         * ftm_ext_clk and ftm_fix_clk are FTM timer counter's
+         * selectable clock sources, both use a common enable bit
+         * in CCM_CSCDR1, selecting "dummy" clock as parent of
+         * "ftm0_ext_fix" make it serve only for enable/disable.
+         */
+        clk[VF610_CLK_FTM0_EXT_SEL] = imx_clk_mux("ftm0_ext_sel", CCM_CSCMR2, 6, 2, ftm_ext_sels, 4);
+        clk[VF610_CLK_FTM0_FIX_SEL] = imx_clk_mux("ftm0_fix_sel", CCM_CSCMR2, 14, 1, ftm_fix_sels, 2);
+        clk[VF610_CLK_FTM0_EXT_FIX_EN] = imx_clk_gate("ftm0_ext_fix_en", "dummy", CCM_CSCDR1, 25);
+        clk[VF610_CLK_FTM1_EXT_SEL] = imx_clk_mux("ftm1_ext_sel", CCM_CSCMR2, 8, 2, ftm_ext_sels, 4);
+        clk[VF610_CLK_FTM1_FIX_SEL] = imx_clk_mux("ftm1_fix_sel", CCM_CSCMR2, 15, 1, ftm_fix_sels, 2);
+        clk[VF610_CLK_FTM1_EXT_FIX_EN] = imx_clk_gate("ftm1_ext_fix_en", "dummy", CCM_CSCDR1, 26);
+        clk[VF610_CLK_FTM2_EXT_SEL] = imx_clk_mux("ftm2_ext_sel", CCM_CSCMR2, 10, 2, ftm_ext_sels, 4);
+        clk[VF610_CLK_FTM2_FIX_SEL] = imx_clk_mux("ftm2_fix_sel", CCM_CSCMR2, 16, 1, ftm_fix_sels, 2);
+        clk[VF610_CLK_FTM2_EXT_FIX_EN] = imx_clk_gate("ftm2_ext_fix_en", "dummy", CCM_CSCDR1, 27);
+        clk[VF610_CLK_FTM3_EXT_SEL] = imx_clk_mux("ftm3_ext_sel", CCM_CSCMR2, 12, 2, ftm_ext_sels, 4);
+        clk[VF610_CLK_FTM3_FIX_SEL] = imx_clk_mux("ftm3_fix_sel", CCM_CSCMR2, 17, 1, ftm_fix_sels, 2);
+        clk[VF610_CLK_FTM3_EXT_FIX_EN] = imx_clk_gate("ftm3_ext_fix_en", "dummy", CCM_CSCDR1, 28);
+
+        /* ftm(n)_clk are FTM module operation clock */
+        clk[VF610_CLK_FTM0] = imx_clk_gate2("ftm0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(8));
+        clk[VF610_CLK_FTM1] = imx_clk_gate2("ftm1", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(9));
+        clk[VF610_CLK_FTM2] = imx_clk_gate2("ftm2", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(8));
+        clk[VF610_CLK_FTM3] = imx_clk_gate2("ftm3", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(9));
+
+        clk[VF610_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2);
+        clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19);
+        clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3);
+        clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8));
+        clk[VF610_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2);
+        clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23);
+        clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3);
+        clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8));
+
+        clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4);
+        clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30);
+        clk[VF610_CLK_ESAI_DIV] = imx_clk_divider("esai_div", "esai_en", CCM_CSCDR2, 24, 4);
+        clk[VF610_CLK_ESAI] = imx_clk_gate2("esai", "esai_div", CCM_CCGR4, CCM_CCGRx_CGn(2));
+
+        clk[VF610_CLK_SAI0_SEL] = imx_clk_mux("sai0_sel", CCM_CSCMR1, 0, 2, sai_sels, 4);
+        clk[VF610_CLK_SAI0_EN] = imx_clk_gate("sai0_en", "sai0_sel", CCM_CSCDR1, 16);
+        clk[VF610_CLK_SAI0_DIV] = imx_clk_divider("sai0_div", "sai0_en", CCM_CSCDR1, 0, 4);
+        clk[VF610_CLK_SAI0] = imx_clk_gate2("sai0", "sai0_div", CCM_CCGR0, CCM_CCGRx_CGn(15));
+
+        clk[VF610_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel", CCM_CSCMR1, 2, 2, sai_sels, 4);
+        clk[VF610_CLK_SAI1_EN] = imx_clk_gate("sai1_en", "sai1_sel", CCM_CSCDR1, 17);
+        clk[VF610_CLK_SAI1_DIV] = imx_clk_divider("sai1_div", "sai1_en", CCM_CSCDR1, 4, 4);
+        clk[VF610_CLK_SAI1] = imx_clk_gate2("sai1", "sai1_div", CCM_CCGR1, CCM_CCGRx_CGn(0));
+
+        clk[VF610_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel", CCM_CSCMR1, 4, 2, sai_sels, 4);
+        clk[VF610_CLK_SAI2_EN] = imx_clk_gate("sai2_en", "sai2_sel", CCM_CSCDR1, 18);
+        clk[VF610_CLK_SAI2_DIV] = imx_clk_divider("sai2_div", "sai2_en", CCM_CSCDR1, 8, 4);
+        clk[VF610_CLK_SAI2] = imx_clk_gate2("sai2", "sai2_div", CCM_CCGR1, CCM_CCGRx_CGn(1));
+
+        clk[VF610_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel", CCM_CSCMR1, 6, 2, sai_sels, 4);
+        clk[VF610_CLK_SAI3_EN] = imx_clk_gate("sai3_en", "sai3_sel", CCM_CSCDR1, 19);
+        clk[VF610_CLK_SAI3_DIV] = imx_clk_divider("sai3_div", "sai3_en", CCM_CSCDR1, 12, 4);
+        clk[VF610_CLK_SAI3] = imx_clk_gate2("sai3", "sai3_div", CCM_CCGR1, CCM_CCGRx_CGn(2));
+
+        clk[VF610_CLK_NFC_SEL] = imx_clk_mux("nfc_sel", CCM_CSCMR1, 12, 2, nfc_sels, 4);
+        clk[VF610_CLK_NFC_EN] = imx_clk_gate("nfc_en", "nfc_sel", CCM_CSCDR2, 9);
+        clk[VF610_CLK_NFC_PRE_DIV] = imx_clk_divider("nfc_pre_div", "nfc_en", CCM_CSCDR3, 13, 3);
+        clk[VF610_CLK_NFC_FRAC_DIV] = imx_clk_divider("nfc_frac_div", "nfc_pre_div", CCM_CSCDR2, 4, 4);
+        clk[VF610_CLK_NFC] = imx_clk_gate2("nfc", "nfc_frac_div", CCM_CCGR10, CCM_CCGRx_CGn(0));
+
+        clk[VF610_CLK_GPU_SEL] = imx_clk_mux("gpu_sel", CCM_CSCMR1, 14, 1, gpu_sels, 2);
+        clk[VF610_CLK_GPU_EN] = imx_clk_gate("gpu_en", "gpu_sel", CCM_CSCDR2, 10);
+        clk[VF610_CLK_GPU2D] = imx_clk_gate2("gpu", "gpu_en", CCM_CCGR8, CCM_CCGRx_CGn(15));
+
+        clk[VF610_CLK_VADC_SEL] = imx_clk_mux("vadc_sel", CCM_CSCMR1, 8, 2, vadc_sels, 3);
+        clk[VF610_CLK_VADC_EN] = imx_clk_gate("vadc_en", "vadc_sel", CCM_CSCDR1, 22);
+        clk[VF610_CLK_VADC_DIV] = imx_clk_divider("vadc_div", "vadc_en", CCM_CSCDR1, 20, 2);
+        clk[VF610_CLK_VADC_DIV_HALF] = imx_clk_fixed_factor("vadc_div_half", "vadc_div", 1, 2);
+        clk[VF610_CLK_VADC] = imx_clk_gate2("vadc", "vadc_div", CCM_CCGR8, CCM_CCGRx_CGn(7));
+
+        clk[VF610_CLK_ADC0] = imx_clk_gate2("adc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(11));
+        clk[VF610_CLK_ADC1] = imx_clk_gate2("adc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(11));
+        clk[VF610_CLK_DAC0] = imx_clk_gate2("dac0", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(12));
+        clk[VF610_CLK_DAC1] = imx_clk_gate2("dac1", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(13));
+
+        clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1));
+
+        clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));
+        clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));
+
+        clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
+        clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2);
+        clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2);
+        clk_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2);
+
+        clk_set_parent(clk[VF610_CLK_QSPI1_SEL], clk[VF610_CLK_PLL1_PFD4]);
+        clk_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2);
+        clk_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2);
+        clk_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2);
+
+        clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]);
+        clk_set_parent(clk[VF610_CLK_SAI1_SEL], clk[VF610_CLK_AUDIO_EXT]);
+        clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]);
+        clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]);
+
+        /* Add the clocks to provider list */
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+CLK_OF_DECLARE(vf610, "fsl,vf610-ccm", vf610_clocks_init);
diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c
index 37e884ed1cd4..55bc80a00666 100644
--- a/arch/arm/mach-imx/clk.c
+++ b/arch/arm/mach-imx/clk.c
@@ -1,4 +1,39 @@
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/slab.h>
 #include <linux/spinlock.h>
 #include "clk.h"
 
 DEFINE_SPINLOCK(imx_ccm_lock);
+
+static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
+{
+        struct of_phandle_args phandle;
+        struct clk *clk = ERR_PTR(-ENODEV);
+        char *path;
+
+        path = kasprintf(GFP_KERNEL, "/clocks/%s", name);
+        if (!path)
+                return ERR_PTR(-ENOMEM);
+
+        phandle.np = of_find_node_by_path(path);
+        kfree(path);
+
+        if (phandle.np) {
+                clk = of_clk_get_from_provider(&phandle);
+                of_node_put(phandle.np);
+        }
+        return clk;
+}
+
+struct clk * __init imx_obtain_fixed_clock(
+                        const char *name, unsigned long rate)
+{
+        struct clk *clk;
+
+        clk = imx_obtain_fixed_clock_from_dt(name);
+        if (IS_ERR(clk))
+                clk = imx_clk_fixed(name, rate);
+        return clk;
+}
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index d9d9d9c66dff..0e4e8bb261b9 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -18,7 +18,6 @@ enum imx_pllv3_type {
         IMX_PLLV3_USB,
         IMX_PLLV3_AV,
         IMX_PLLV3_ENET,
-        IMX_PLLV3_MLB,
 };
 
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
@@ -29,6 +28,9 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
                 void __iomem *reg, u8 bit_idx,
                 u8 clk_gate_flags, spinlock_t *lock);
 
+struct clk * imx_obtain_fixed_clock(
+                        const char *name, unsigned long rate);
+
 static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
                 void __iomem *reg, u8 shift)
 {
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index c08ae3f99cee..ee78847abf47 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -68,12 +68,12 @@ extern int mx27_clocks_init_dt(void);
 extern int mx31_clocks_init_dt(void);
 extern int mx51_clocks_init_dt(void);
 extern int mx53_clocks_init_dt(void);
-extern int mx6q_clocks_init(void);
 extern struct platform_device *mxc_register_gpio(char *name, int id,
         resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
 extern void mxc_set_cpu_type(unsigned int type);
 extern void mxc_restart(char, const char *);
 extern void mxc_arch_reset_init(void __iomem *);
+extern void mxc_arch_reset_init_dt(void);
 extern int mx53_revision(void);
 extern int imx6q_revision(void);
 extern int mx53_display_revision(void);
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index 356131f7b591..a3b0b04b45c9 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -20,6 +20,7 @@
 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
 #define __ASM_ARCH_MXC_HARDWARE_H__
 
+#include <asm/io.h>
 #include <asm/sizes.h>
 
 #define addr_in_module(addr, mod) \
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
index 82348391582a..3e1ec5ffe630 100644
--- a/arch/arm/mach-imx/imx25-dt.c
+++ b/arch/arm/mach-imx/imx25-dt.c
@@ -19,6 +19,8 @@
 
 static void __init imx25_dt_init(void)
 {
+        mxc_arch_reset_init_dt();
+
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index 4aaead0a77ff..4e235ecb4021 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -22,6 +22,8 @@ static void __init imx27_dt_init(void)
 {
         struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
 
+        mxc_arch_reset_init_dt();
+
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
         platform_device_register_full(&devinfo);
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index 67de611e29ab..818a1cc2fe45 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -20,6 +20,8 @@
 
 static void __init imx31_dt_init(void)
 {
+        mxc_arch_reset_init_dt();
+
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index ab24cc322111..53e43e579dd7 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -23,6 +23,8 @@ static void __init imx51_dt_init(void)
 {
         struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
 
+        mxc_arch_reset_init_dt();
+
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
         platform_device_register_full(&devinfo);
 }
diff --git a/arch/arm/mach-imx/irq-common.c b/arch/arm/mach-imx/irq-common.c
index 4b34f52dc46b..0a920d184867 100644
--- a/arch/arm/mach-imx/irq-common.c
+++ b/arch/arm/mach-imx/irq-common.c
@@ -18,6 +18,7 @@
 
 #include <linux/module.h>
 #include <linux/irq.h>
+#include <linux/platform_data/asoc-imx-ssi.h>
 
 #include "irq-common.h"
 
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index f579c616feed..74e7b94c22e7 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -21,6 +21,7 @@
 #include <asm/mach/time.h>
 
 #include "common.h"
+#include "hardware.h"
 #include "mx53.h"
 
 static void __init imx53_qsb_init(void)
@@ -38,6 +39,8 @@ static void __init imx53_qsb_init(void)
 
 static void __init imx53_dt_init(void)
 {
+        mxc_arch_reset_init_dt();
+
         if (of_machine_is_compatible("fsl,imx53-qsb"))
                 imx53_qsb_init();
 
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5536fd81379a..f5965220a4d8 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/clkdev.h>
 #include <linux/clocksource.h>
 #include <linux/cpu.h>
@@ -145,6 +146,45 @@ static void __init imx6q_sabrelite_init(void)
         imx6q_sabrelite_cko1_setup();
 }
 
+static void __init imx6q_sabresd_cko1_setup(void)
+{
+        struct clk *cko1_sel, *pll4, *pll4_post, *cko1;
+        unsigned long rate;
+
+        cko1_sel = clk_get_sys(NULL, "cko1_sel");
+        pll4 = clk_get_sys(NULL, "pll4_audio");
+        pll4_post = clk_get_sys(NULL, "pll4_post_div");
+        cko1 = clk_get_sys(NULL, "cko1");
+        if (IS_ERR(cko1_sel) || IS_ERR(pll4)
+                        || IS_ERR(pll4_post) || IS_ERR(cko1)) {
+                pr_err("cko1 setup failed!\n");
+                goto put_clk;
+        }
+        /*
+         * Setting pll4 at 768MHz (24MHz * 32)
+         * So its child clock can get 24MHz easily
+         */
+        clk_set_rate(pll4, 768000000);
+
+        clk_set_parent(cko1_sel, pll4_post);
+        rate = clk_round_rate(cko1, 24000000);
+        clk_set_rate(cko1, rate);
+put_clk:
+        if (!IS_ERR(cko1_sel))
+                clk_put(cko1_sel);
+        if (!IS_ERR(pll4_post))
+                clk_put(pll4_post);
+        if (!IS_ERR(pll4))
+                clk_put(pll4);
+        if (!IS_ERR(cko1))
+                clk_put(cko1);
+}
+
+static void __init imx6q_sabresd_init(void)
+{
+        imx6q_sabresd_cko1_setup();
+}
+
 static void __init imx6q_1588_init(void)
 {
         struct regmap *gpr;
@@ -165,6 +205,9 @@ static void __init imx6q_init_machine(void)
 {
         if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
                 imx6q_sabrelite_init();
+        else if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
+                        of_machine_is_compatible("fsl,imx6dl-sabresd"))
+                imx6q_sabresd_init();
 
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
@@ -253,10 +296,44 @@ static void __init imx6q_map_io(void)
         imx_scu_map_io();
 }
 
+#ifdef CONFIG_CACHE_L2X0
+static void __init imx6q_init_l2cache(void)
+{
+        void __iomem *l2x0_base;
+        struct device_node *np;
+        unsigned int val;
+
+        np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
+        if (!np)
+                goto out;
+
+        l2x0_base = of_iomap(np, 0);
+        if (!l2x0_base) {
+                of_node_put(np);
+                goto out;
+        }
+
+        /* Configure the L2 PREFETCH and POWER registers */
+        val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
+        val |= 0x70800000;
+        writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
+        val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
+        writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
+
+        iounmap(l2x0_base);
+        of_node_put(np);
+
+out:
+        l2x0_of_init(0, ~0UL);
+}
+#else
+static inline void imx6q_init_l2cache(void) {}
+#endif
+
 static void __init imx6q_init_irq(void)
 {
         imx6q_init_revision();
-        l2x0_of_init(0, ~0UL);
+        imx6q_init_l2cache();
         imx_src_init();
         imx_gpc_init();
         irqchip_init();
@@ -264,7 +341,7 @@ static void __init imx6q_init_irq(void)
 
 static void __init imx6q_timer_init(void)
 {
-        mx6q_clocks_init();
+        of_clk_init(NULL);
         clocksource_of_init();
         imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
                               imx6q_revision());
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
new file mode 100644
index 000000000000..132db2609507
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/irqchip.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include "common.h"
+
+static void __init imx6sl_init_machine(void)
+{
+        mxc_arch_reset_init_dt();
+
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static void __init imx6sl_init_irq(void)
+{
+        l2x0_of_init(0, ~0UL);
+        imx_src_init();
+        imx_gpc_init();
+        irqchip_init();
+}
+
+static void __init imx6sl_timer_init(void)
+{
+        of_clk_init(NULL);
+}
+
+static const char *imx6sl_dt_compat[] __initdata = {
+        "fsl,imx6sl",
+        NULL,
+};
+
+DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)")
+        .map_io         = debug_ll_io_init,
+        .init_irq       = imx6sl_init_irq,
+        .init_time      = imx6sl_timer_init,
+        .init_machine   = imx6sl_init_machine,
+        .dt_compat      = imx6sl_dt_compat,
+        .restart        = mxc_restart,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index b8b15bb1ffdf..19bb6441a7d4 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -398,8 +398,8 @@ static void __init pca100_init(void)
                 imx27_add_fsl_usb2_udc(&otg_device_pdata);
         }
 
-        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+        usbh2_pdata.otg = imx_otg_ulpi_create(
+                        ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
 
         if (usbh2_pdata.otg)
                 imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
new file mode 100644
index 000000000000..816991deb9b8
--- /dev/null
+++ b/arch/arm/mach-imx/mach-vf610.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/of_platform.h>
+#include <linux/clocksource.h>
+#include <linux/irqchip.h>
+#include <linux/clk-provider.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include "common.h"
+
+static void __init vf610_init_machine(void)
+{
+        mxc_arch_reset_init_dt();
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static void __init vf610_init_irq(void)
+{
+        l2x0_of_init(0, ~0UL);
+        irqchip_init();
+}
+
+static void __init vf610_init_time(void)
+{
+        of_clk_init(NULL);
+        clocksource_of_init();
+}
+
+static const char *vf610_dt_compat[] __initdata = {
+        "fsl,vf610",
+        NULL,
+};
+
+DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF610 (Device Tree)")
+        .init_irq       = vf610_init_irq,
+        .init_time      = vf610_init_time,
+        .init_machine   = vf610_init_machine,
+        .dt_compat      = vf610_dt_compat,
+        .restart        = mxc_restart,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 3c609c52d3eb..e065fedb3ad4 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -39,7 +39,6 @@ void __init mx1_map_io(void)
 void __init imx1_init_early(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX1);
-        mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
         imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
                         MX1_NUM_GPIO_PORT);
 }
@@ -51,6 +50,7 @@ void __init mx1_init_irq(void)
 
 void __init imx1_soc_init(void)
 {
+        mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
         mxc_device_init();
 
         mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256,
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index d8ccd3a8ec53..2e91ab2ca378 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -66,7 +66,6 @@ void __init mx21_map_io(void)
 void __init imx21_init_early(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX21);
-        mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
         imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR),
                         MX21_NUM_GPIO_PORT);
 }
@@ -82,6 +81,7 @@ static const struct resource imx21_audmux_res[] __initconst = {
 
 void __init imx21_soc_init(void)
 {
+        mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
         mxc_device_init();
 
         mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 9357707bb7af..e065c117f5a6 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -54,7 +54,6 @@ void __init imx25_init_early(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX25);
         mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
 }
 
 void __init mx25_init_irq(void)
@@ -89,6 +88,7 @@ static const struct resource imx25_audmux_res[] __initconst = {
 
 void __init imx25_soc_init(void)
 {
+        mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
         mxc_device_init();
 
         /* i.mx25 has the i.mx35 type gpio */
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 4f1be65a7b5f..7d82a5a5b16b 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -66,7 +66,6 @@ void __init mx27_map_io(void)
 void __init imx27_init_early(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX27);
-        mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
         imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR),
                         MX27_NUM_GPIO_PORT);
 }
@@ -82,6 +81,7 @@ static const struct resource imx27_audmux_res[] __initconst = {
 
 void __init imx27_soc_init(void)
 {
+        mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
         mxc_device_init();
 
         /* i.mx27 has the i.mx21 type gpio */
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index e0e69a682174..8f0f60697f55 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -138,7 +138,6 @@ void __init mx31_map_io(void)
 void __init imx31_init_early(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX31);
-        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
         arch_ioremap_caller = imx3_ioremap_caller;
         arm_pm_idle = imx3_idle;
         mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
@@ -174,6 +173,7 @@ void __init imx31_soc_init(void)
 
         imx3_init_l2x0();
 
+        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
         mxc_device_init();
 
         mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
@@ -216,7 +216,6 @@ void __init imx35_init_early(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX35);
         mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
         arm_pm_idle = imx3_idle;
         arch_ioremap_caller = imx3_ioremap_caller;
         mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
@@ -272,6 +271,7 @@ void __init imx35_soc_init(void)
 
         imx3_init_l2x0();
 
+        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
         mxc_device_init();
 
         mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index b7c4e70e5081..cf193d87274a 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -83,7 +83,6 @@ void __init imx51_init_early(void)
         imx51_ipu_mipi_setup();
         mxc_set_cpu_type(MXC_CPU_MX51);
         mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
         imx_src_init();
 }
 
@@ -91,7 +90,6 @@ void __init imx53_init_early(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX53);
         mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
         imx_src_init();
 }
 
@@ -129,6 +127,7 @@ static const struct resource imx51_audmux_res[] __initconst = {
 
 void __init imx51_soc_init(void)
 {
+        mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
         mxc_device_init();
 
         /* i.mx51 has the i.mx35 type gpio */
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 695e0d73bf85..7cdc79a9657c 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -21,6 +21,8 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <asm/system_misc.h>
 #include <asm/proc-fns.h>
@@ -30,6 +32,7 @@
 #include "hardware.h"
 
 static void __iomem *wdog_base;
+static struct clk *wdog_clk;
 
 /*
  * Reset the system. It is called by machine_restart().
@@ -38,16 +41,13 @@ void mxc_restart(char mode, const char *cmd)
 {
         unsigned int wcr_enable;
 
-        if (cpu_is_mx1()) {
-                wcr_enable = (1 << 0);
-        } else {
-                struct clk *clk;
+        if (wdog_clk)
+                clk_enable(wdog_clk);
 
-                clk = clk_get_sys("imx2-wdt.0", NULL);
-                if (!IS_ERR(clk))
-                        clk_prepare_enable(clk);
+        if (cpu_is_mx1())
+                wcr_enable = (1 << 0);
+        else
                 wcr_enable = (1 << 2);
-        }
 
         /* Assert SRS signal */
         __raw_writew(wcr_enable, wdog_base);
@@ -55,7 +55,7 @@ void mxc_restart(char mode, const char *cmd)
         /* wait for reset to assert... */
         mdelay(500);
 
-        printk(KERN_ERR "Watchdog reset failed to assert reset\n");
+        pr_err("%s: Watchdog reset failed to assert reset\n", __func__);
 
         /* delay to allow the serial port to show the message */
         mdelay(50);
@@ -64,7 +64,34 @@ void mxc_restart(char mode, const char *cmd)
         soft_restart(0);
 }
 
-void mxc_arch_reset_init(void __iomem *base)
+void __init mxc_arch_reset_init(void __iomem *base)
 {
         wdog_base = base;
+
+        wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
+        if (IS_ERR(wdog_clk)) {
+                pr_warn("%s: failed to get wdog clock\n", __func__);
+                wdog_clk = NULL;
+                return;
+        }
+
+        clk_prepare(wdog_clk);
+}
+
+void __init mxc_arch_reset_init_dt(void)
+{
+        struct device_node *np;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt");
+        wdog_base = of_iomap(np, 0);
+        WARN_ON(!wdog_base);
+
+        wdog_clk = of_clk_get(np, 0);
+        if (IS_ERR(wdog_clk)) {
+                pr_warn("%s: failed to get wdog clock\n", __func__);
+                wdog_clk = NULL;
+                return;
+        }
+
+        clk_prepare(wdog_clk);
 }
diff --git a/arch/arm/mach-imx/ulpi.c b/arch/arm/mach-imx/ulpi.c
deleted file mode 100644
index 0f051957d10c..000000000000
--- a/arch/arm/mach-imx/ulpi.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
- * Copyright 2009 Daniel Mack <daniel@caiaq.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-
-#include "ulpi.h"
-
-/* ULPIVIEW register bits */
-#define ULPIVW_WU               (1 << 31)       /* Wakeup */
-#define ULPIVW_RUN              (1 << 30)       /* read/write run */
-#define ULPIVW_WRITE            (1 << 29)       /* 0 = read  1 = write */
-#define ULPIVW_SS               (1 << 27)       /* SyncState */
-#define ULPIVW_PORT_MASK        0x07    /* Port field */
-#define ULPIVW_PORT_SHIFT       24
-#define ULPIVW_ADDR_MASK        0xff    /* data address field */
-#define ULPIVW_ADDR_SHIFT       16
-#define ULPIVW_RDATA_MASK       0xff    /* read data field */
-#define ULPIVW_RDATA_SHIFT      8
-#define ULPIVW_WDATA_MASK       0xff    /* write data field */
-#define ULPIVW_WDATA_SHIFT      0
-
-static int ulpi_poll(void __iomem *view, u32 bit)
-{
-        int timeout = 10000;
-
-        while (timeout--) {
-                u32 data = __raw_readl(view);
-
-                if (!(data & bit))
-                        return 0;
-
-                cpu_relax();
-        };
-
-        printk(KERN_WARNING "timeout polling for ULPI device\n");
-
-        return -ETIMEDOUT;
-}
-
-static int ulpi_read(struct usb_phy *otg, u32 reg)
-{
-        int ret;
-        void __iomem *view = otg->io_priv;
-
-        /* make sure interface is running */
-        if (!(__raw_readl(view) & ULPIVW_SS)) {
-                __raw_writel(ULPIVW_WU, view);
-
-                /* wait for wakeup */
-                ret = ulpi_poll(view, ULPIVW_WU);
-                if (ret)
-                        return ret;
-        }
-
-        /* read the register */
-        __raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view);
-
-        /* wait for completion */
-        ret = ulpi_poll(view, ULPIVW_RUN);
-        if (ret)
-                return ret;
-
-        return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK;
-}
-
-static int ulpi_write(struct usb_phy *otg, u32 val, u32 reg)
-{
-        int ret;
-        void __iomem *view = otg->io_priv;
-
-        /* make sure the interface is running */
-        if (!(__raw_readl(view) & ULPIVW_SS)) {
-                __raw_writel(ULPIVW_WU, view);
-                /* wait for wakeup */
-                ret = ulpi_poll(view, ULPIVW_WU);
-                if (ret)
-                        return ret;
-        }
-
-        __raw_writel((ULPIVW_RUN | ULPIVW_WRITE |
-                      (reg << ULPIVW_ADDR_SHIFT) |
-                      ((val & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), view);
-
-        /* wait for completion */
-        return ulpi_poll(view, ULPIVW_RUN);
-}
-
-struct usb_phy_io_ops mxc_ulpi_access_ops = {
-        .read   = ulpi_read,
-        .write  = ulpi_write,
-};
-EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops);
-
-struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
-{
-        return otg_ulpi_create(&mxc_ulpi_access_ops, flags);
-}
diff --git a/arch/arm/mach-imx/ulpi.h b/arch/arm/mach-imx/ulpi.h
index 42bdaca6d7d9..23f5c0349e80 100644
--- a/arch/arm/mach-imx/ulpi.h
+++ b/arch/arm/mach-imx/ulpi.h
@@ -1,8 +1,13 @@
 #ifndef __MACH_ULPI_H
 #define __MACH_ULPI_H
 
-#ifdef CONFIG_USB_ULPI
-struct usb_phy *imx_otg_ulpi_create(unsigned int flags);
+#include <linux/usb/ulpi.h>
+
+#ifdef CONFIG_USB_ULPI_VIEWPORT
+static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
+{
+        return otg_ulpi_create(&ulpi_viewport_access_ops, flags);
+}
 #else
 static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
 {
@@ -10,7 +15,5 @@ static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
 }
 #endif
 
-extern struct usb_phy_io_ops mxc_ulpi_access_ops;
-
 #endif /* __MACH_ULPI_H */
 
diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
index d14d6b76f4c2..ec759ded7b60 100644
--- a/arch/arm/mach-integrator/Makefile
+++ b/arch/arm/mach-integrator/Makefile
@@ -8,5 +8,5 @@ obj-y					:= core.o lm.o leds.o
 obj-$(CONFIG_ARCH_INTEGRATOR_AP)        += integrator_ap.o
 obj-$(CONFIG_ARCH_INTEGRATOR_CP)        += integrator_cp.o
 
-obj-$(CONFIG_PCI)                       += pci_v3.o pci.o
+obj-$(CONFIG_PCI)                       += pci_v3.o
 obj-$(CONFIG_INTEGRATOR_IMPD1)          += impd1.o
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h
index be5859efe10e..306d025d9730 100644
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ b/arch/arm/mach-integrator/include/mach/platform.h
@@ -305,29 +305,6 @@
 /* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */
 
 /* ------------------------------------------------------------------------
- *  Where in the memory map does PCI live?
- * ------------------------------------------------------------------------
- *  This represents a fairly liberal usage of address space.  Even though
- *  the V3 only has two windows (therefore we need to map stuff on the fly),
- *  we maintain the same addresses, even if they're not mapped.
- *
- */
-#define PHYS_PCI_MEM_BASE               0x40000000   /* 512M to xxx */
-/*  unused 256M from A0000000-AFFFFFFF might be used for I2O ???
- */
-#define PHYS_PCI_IO_BASE                0x60000000   /* 16M to xxx */
-/*  unused (128-16)M from B1000000-B7FFFFFF
- */
-#define PHYS_PCI_CONFIG_BASE            0x61000000   /* 16M to xxx */
-/*  unused ((128-16)M - 64K) from XXX
- */
-#define PHYS_PCI_V3_BASE                0x62000000
-
-#define PCI_MEMORY_VADDR                IOMEM(0xe8000000)
-#define PCI_CONFIG_VADDR                IOMEM(0xec000000)
-#define PCI_V3_VADDR                    IOMEM(0xed000000)
-
-/* ------------------------------------------------------------------------
  *  Integrator Interrupt Controllers
  * ------------------------------------------------------------------------
  *
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index b23c8e4f28e8..a5b15c4e8def 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -41,7 +41,6 @@
 #include <linux/stat.h>
 #include <linux/sys_soc.h>
 #include <linux/termios.h>
-#include <video/vga.h>
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -57,10 +56,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
-#include <asm/mach/pci.h>
 #include <asm/mach/time.h>
 
 #include "common.h"
+#include "pci_v3.h"
 
 /* Base address to the AP system controller */
 void __iomem *ap_syscon_base;
@@ -78,10 +77,6 @@ void __iomem *ap_syscon_base;
 
 /*
  * Logical      Physical
- * e8000000     40000000        PCI memory              PHYS_PCI_MEM_BASE       (max 512M)
- * ec000000     61000000        PCI config space        PHYS_PCI_CONFIG_BASE    (max 16M)
- * ed000000     62000000        PCI V3 regs             PHYS_PCI_V3_BASE        (max 64k)
- * fee00000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
  * ef000000                     Cache flush
  * f1000000     10000000        Core module registers
  * f1100000     11000000        System controller registers
@@ -130,29 +125,13 @@ static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
                 .pfn            = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE
-        }, {
-                .virtual        = (unsigned long)PCI_MEMORY_VADDR,
-                .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
-                .length         = SZ_16M,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = (unsigned long)PCI_CONFIG_VADDR,
-                .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
-                .length         = SZ_16M,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = (unsigned long)PCI_V3_VADDR,
-                .pfn            = __phys_to_pfn(PHYS_PCI_V3_BASE),
-                .length         = SZ_64K,
-                .type           = MT_DEVICE
         }
 };
 
 static void __init ap_map_io(void)
 {
         iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
-        vga_base = (unsigned long)PCI_MEMORY_VADDR;
-        pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
+        pci_v3_early_init();
 }
 
 #ifdef CONFIG_PM
@@ -615,6 +594,11 @@ static void __init ap_map_io_atag(void)
  * for eventual deletion.
  */
 
+static struct platform_device pci_v3_device = {
+        .name           = "pci-v3",
+        .id             = 0,
+};
+
 static struct resource cfi_flash_resource = {
         .start          = INTEGRATOR_FLASH_BASE,
         .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
@@ -672,6 +656,7 @@ static void __init ap_init(void)
         unsigned long sc_dec;
         int i;
 
+        platform_device_register(&pci_v3_device);
         platform_device_register(&cfi_flash_device);
 
         ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
diff --git a/arch/arm/mach-integrator/pci.c b/arch/arm/mach-integrator/pci.c
deleted file mode 100644
index 6c1667e728f5..000000000000
--- a/arch/arm/mach-integrator/pci.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- *  linux/arch/arm/mach-integrator/pci-integrator.c
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- *
- *  PCI functions for Integrator
- */
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-
-#include <asm/mach/pci.h>
-#include <asm/mach-types.h>
-
-#include <mach/irqs.h>
-
-/* 
- * A small note about bridges and interrupts.  The DECchip 21050 (and
- * later) adheres to the PCI-PCI bridge specification.  This says that
- * the interrupts on the other side of a bridge are swizzled in the
- * following manner:
- *
- * Dev    Interrupt   Interrupt 
- *        Pin on      Pin on 
- *        Device      Connector
- *
- *   4    A           A
- *        B           B
- *        C           C
- *        D           D
- * 
- *   5    A           B
- *        B           C
- *        C           D
- *        D           A
- *
- *   6    A           C
- *        B           D
- *        C           A
- *        D           B
- *
- *   7    A           D
- *        B           A
- *        C           B
- *        D           C
- *
- * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
- * Thus, each swizzle is ((pin-1) + (device#-4)) % 4
- */
-
-/*
- * This routine handles multiple bridges.
- */
-static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp)
-{
-        if (*pinp == 0)
-                *pinp = 1;
-
-        return pci_common_swizzle(dev, pinp);
-}
-
-static int irq_tab[4] __initdata = {
-        IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3
-};
-
-/*
- * map the specified device/slot/pin to an IRQ.  This works out such
- * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
- */
-static int __init integrator_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-        int intnr = ((slot - 9) + (pin - 1)) & 3;
-
-        return irq_tab[intnr];
-}
-
-extern void pci_v3_init(void *);
-
-static struct hw_pci integrator_pci __initdata = {
-        .swizzle                = integrator_swizzle,
-        .map_irq                = integrator_map_irq,
-        .setup                  = pci_v3_setup,
-        .nr_controllers         = 1,
-        .ops                    = &pci_v3_ops,
-        .preinit                = pci_v3_preinit,
-        .postinit               = pci_v3_postinit,
-};
-
-static int __init integrator_pci_init(void)
-{
-        if (machine_is_integrator())
-                pci_common_init(&integrator_pci);
-        return 0;
-}
-
-subsys_initcall(integrator_pci_init);
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index e7fcea7f3300..a0e069d37e14 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -27,16 +27,198 @@
 #include <linux/spinlock.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <video/vga.h>
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
 #include <mach/irqs.h>
 
+#include <asm/mach/map.h>
 #include <asm/signal.h>
 #include <asm/mach/pci.h>
 #include <asm/irq_regs.h>
 
-#include <asm/hardware/pci_v3.h>
+#include "pci_v3.h"
+
+/*
+ * Where in the memory map does PCI live?
+ *
+ * This represents a fairly liberal usage of address space.  Even though
+ * the V3 only has two windows (therefore we need to map stuff on the fly),
+ * we maintain the same addresses, even if they're not mapped.
+ */
+#define PHYS_PCI_MEM_BASE               0x40000000 /* 512M */
+#define PHYS_PCI_IO_BASE                0x60000000 /* 16M */
+#define PHYS_PCI_CONFIG_BASE            0x61000000 /* 16M */
+#define PHYS_PCI_V3_BASE                0x62000000 /* 64K */
+
+#define PCI_MEMORY_VADDR               IOMEM(0xe8000000)
+#define PCI_CONFIG_VADDR               IOMEM(0xec000000)
+
+/*
+ * V3 Local Bus to PCI Bridge definitions
+ *
+ * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
+ * All V3 register names are prefaced by V3_ to avoid clashing with any other
+ * PCI definitions.  Their names match the user's manual.
+ *
+ * I'm assuming that I20 is disabled.
+ *
+ */
+#define V3_PCI_VENDOR                   0x00000000
+#define V3_PCI_DEVICE                   0x00000002
+#define V3_PCI_CMD                      0x00000004
+#define V3_PCI_STAT                     0x00000006
+#define V3_PCI_CC_REV                   0x00000008
+#define V3_PCI_HDR_CFG                  0x0000000C
+#define V3_PCI_IO_BASE                  0x00000010
+#define V3_PCI_BASE0                    0x00000014
+#define V3_PCI_BASE1                    0x00000018
+#define V3_PCI_SUB_VENDOR               0x0000002C
+#define V3_PCI_SUB_ID                   0x0000002E
+#define V3_PCI_ROM                      0x00000030
+#define V3_PCI_BPARAM                   0x0000003C
+#define V3_PCI_MAP0                     0x00000040
+#define V3_PCI_MAP1                     0x00000044
+#define V3_PCI_INT_STAT                 0x00000048
+#define V3_PCI_INT_CFG                  0x0000004C
+#define V3_LB_BASE0                     0x00000054
+#define V3_LB_BASE1                     0x00000058
+#define V3_LB_MAP0                      0x0000005E
+#define V3_LB_MAP1                      0x00000062
+#define V3_LB_BASE2                     0x00000064
+#define V3_LB_MAP2                      0x00000066
+#define V3_LB_SIZE                      0x00000068
+#define V3_LB_IO_BASE                   0x0000006E
+#define V3_FIFO_CFG                     0x00000070
+#define V3_FIFO_PRIORITY                0x00000072
+#define V3_FIFO_STAT                    0x00000074
+#define V3_LB_ISTAT                     0x00000076
+#define V3_LB_IMASK                     0x00000077
+#define V3_SYSTEM                       0x00000078
+#define V3_LB_CFG                       0x0000007A
+#define V3_PCI_CFG                      0x0000007C
+#define V3_DMA_PCI_ADR0                 0x00000080
+#define V3_DMA_PCI_ADR1                 0x00000090
+#define V3_DMA_LOCAL_ADR0               0x00000084
+#define V3_DMA_LOCAL_ADR1               0x00000094
+#define V3_DMA_LENGTH0                  0x00000088
+#define V3_DMA_LENGTH1                  0x00000098
+#define V3_DMA_CSR0                     0x0000008B
+#define V3_DMA_CSR1                     0x0000009B
+#define V3_DMA_CTLB_ADR0                0x0000008C
+#define V3_DMA_CTLB_ADR1                0x0000009C
+#define V3_DMA_DELAY                    0x000000E0
+#define V3_MAIL_DATA                    0x000000C0
+#define V3_PCI_MAIL_IEWR                0x000000D0
+#define V3_PCI_MAIL_IERD                0x000000D2
+#define V3_LB_MAIL_IEWR                 0x000000D4
+#define V3_LB_MAIL_IERD                 0x000000D6
+#define V3_MAIL_WR_STAT                 0x000000D8
+#define V3_MAIL_RD_STAT                 0x000000DA
+#define V3_QBA_MAP                      0x000000DC
+
+/*  PCI COMMAND REGISTER bits
+ */
+#define V3_COMMAND_M_FBB_EN             (1 << 9)
+#define V3_COMMAND_M_SERR_EN            (1 << 8)
+#define V3_COMMAND_M_PAR_EN             (1 << 6)
+#define V3_COMMAND_M_MASTER_EN          (1 << 2)
+#define V3_COMMAND_M_MEM_EN             (1 << 1)
+#define V3_COMMAND_M_IO_EN              (1 << 0)
+
+/*  SYSTEM REGISTER bits
+ */
+#define V3_SYSTEM_M_RST_OUT             (1 << 15)
+#define V3_SYSTEM_M_LOCK                (1 << 14)
+
+/*  PCI_CFG bits
+ */
+#define V3_PCI_CFG_M_I2O_EN             (1 << 15)
+#define V3_PCI_CFG_M_IO_REG_DIS         (1 << 14)
+#define V3_PCI_CFG_M_IO_DIS             (1 << 13)
+#define V3_PCI_CFG_M_EN3V               (1 << 12)
+#define V3_PCI_CFG_M_RETRY_EN           (1 << 10)
+#define V3_PCI_CFG_M_AD_LOW1            (1 << 9)
+#define V3_PCI_CFG_M_AD_LOW0            (1 << 8)
+
+/*  PCI_BASE register bits (PCI -> Local Bus)
+ */
+#define V3_PCI_BASE_M_ADR_BASE          0xFFF00000
+#define V3_PCI_BASE_M_ADR_BASEL         0x000FFF00
+#define V3_PCI_BASE_M_PREFETCH          (1 << 3)
+#define V3_PCI_BASE_M_TYPE              (3 << 1)
+#define V3_PCI_BASE_M_IO                (1 << 0)
+
+/*  PCI MAP register bits (PCI -> Local bus)
+ */
+#define V3_PCI_MAP_M_MAP_ADR            0xFFF00000
+#define V3_PCI_MAP_M_RD_POST_INH        (1 << 15)
+#define V3_PCI_MAP_M_ROM_SIZE           (3 << 10)
+#define V3_PCI_MAP_M_SWAP               (3 << 8)
+#define V3_PCI_MAP_M_ADR_SIZE           0x000000F0
+#define V3_PCI_MAP_M_REG_EN             (1 << 1)
+#define V3_PCI_MAP_M_ENABLE             (1 << 0)
+
+/*
+ *  LB_BASE0,1 register bits (Local bus -> PCI)
+ */
+#define V3_LB_BASE_ADR_BASE             0xfff00000
+#define V3_LB_BASE_SWAP                 (3 << 8)
+#define V3_LB_BASE_ADR_SIZE             (15 << 4)
+#define V3_LB_BASE_PREFETCH             (1 << 3)
+#define V3_LB_BASE_ENABLE               (1 << 0)
+
+#define V3_LB_BASE_ADR_SIZE_1MB         (0 << 4)
+#define V3_LB_BASE_ADR_SIZE_2MB         (1 << 4)
+#define V3_LB_BASE_ADR_SIZE_4MB         (2 << 4)
+#define V3_LB_BASE_ADR_SIZE_8MB         (3 << 4)
+#define V3_LB_BASE_ADR_SIZE_16MB        (4 << 4)
+#define V3_LB_BASE_ADR_SIZE_32MB        (5 << 4)
+#define V3_LB_BASE_ADR_SIZE_64MB        (6 << 4)
+#define V3_LB_BASE_ADR_SIZE_128MB       (7 << 4)
+#define V3_LB_BASE_ADR_SIZE_256MB       (8 << 4)
+#define V3_LB_BASE_ADR_SIZE_512MB       (9 << 4)
+#define V3_LB_BASE_ADR_SIZE_1GB         (10 << 4)
+#define V3_LB_BASE_ADR_SIZE_2GB         (11 << 4)
+
+#define v3_addr_to_lb_base(a)   ((a) & V3_LB_BASE_ADR_BASE)
+
+/*
+ *  LB_MAP0,1 register bits (Local bus -> PCI)
+ */
+#define V3_LB_MAP_MAP_ADR               0xfff0
+#define V3_LB_MAP_TYPE                  (7 << 1)
+#define V3_LB_MAP_AD_LOW_EN             (1 << 0)
+
+#define V3_LB_MAP_TYPE_IACK             (0 << 1)
+#define V3_LB_MAP_TYPE_IO               (1 << 1)
+#define V3_LB_MAP_TYPE_MEM              (3 << 1)
+#define V3_LB_MAP_TYPE_CONFIG           (5 << 1)
+#define V3_LB_MAP_TYPE_MEM_MULTIPLE     (6 << 1)
+
+#define v3_addr_to_lb_map(a)    (((a) >> 16) & V3_LB_MAP_MAP_ADR)
+
+/*
+ *  LB_BASE2 register bits (Local bus -> PCI IO)
+ */
+#define V3_LB_BASE2_ADR_BASE            0xff00
+#define V3_LB_BASE2_SWAP                (3 << 6)
+#define V3_LB_BASE2_ENABLE              (1 << 0)
+
+#define v3_addr_to_lb_base2(a)  (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
+
+/*
+ *  LB_MAP2 register bits (Local bus -> PCI IO)
+ */
+#define V3_LB_MAP2_MAP_ADR              0xff00
+
+#define v3_addr_to_lb_map2(a)   (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
 
 /*
  * The V3 PCI interface chip in Integrator provides several windows from
@@ -101,15 +283,22 @@
  * the mappings into PCI memory.
  */
 
+/* Filled in by probe */
+static void __iomem *pci_v3_base;
+static struct resource conf_mem; /* FIXME: remap this instead of static map */
+static struct resource io_mem;
+static struct resource non_mem;
+static struct resource pre_mem;
+
 // V3 access routines
-#define v3_writeb(o,v) __raw_writeb(v, PCI_V3_VADDR + (unsigned int)(o))
-#define v3_readb(o)    (__raw_readb(PCI_V3_VADDR + (unsigned int)(o)))
+#define v3_writeb(o,v) __raw_writeb(v, pci_v3_base + (unsigned int)(o))
+#define v3_readb(o)    (__raw_readb(pci_v3_base + (unsigned int)(o)))
 
-#define v3_writew(o,v) __raw_writew(v, PCI_V3_VADDR + (unsigned int)(o))
-#define v3_readw(o)    (__raw_readw(PCI_V3_VADDR + (unsigned int)(o)))
+#define v3_writew(o,v) __raw_writew(v, pci_v3_base + (unsigned int)(o))
+#define v3_readw(o)    (__raw_readw(pci_v3_base + (unsigned int)(o)))
 
-#define v3_writel(o,v) __raw_writel(v, PCI_V3_VADDR + (unsigned int)(o))
-#define v3_readl(o)    (__raw_readl(PCI_V3_VADDR + (unsigned int)(o)))
+#define v3_writel(o,v) __raw_writel(v, pci_v3_base + (unsigned int)(o))
+#define v3_readl(o)    (__raw_readl(pci_v3_base + (unsigned int)(o)))
 
 /*============================================================================
  *
@@ -243,13 +432,13 @@ static void __iomem *v3_open_config_window(struct pci_bus *bus,
          * prefetchable), this frees up base1 for re-use by
          * configuration memory
          */
-        v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
+        v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
                         V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
 
         /*
          * Set up base1/map1 to point into configuration space.
          */
-        v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
+        v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(conf_mem.start) |
                         V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
         v3_writew(V3_LB_MAP1, mapaddress);
 
@@ -261,7 +450,7 @@ static void v3_close_config_window(void)
         /*
          * Reassign base1 for use by prefetchable PCI memory
          */
-        v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
+        v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) |
                         V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
                         V3_LB_BASE_ENABLE);
         v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
@@ -270,7 +459,7 @@ static void v3_close_config_window(void)
         /*
          * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
          */
-        v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
+        v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
                         V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
 }
 
@@ -337,25 +526,11 @@ static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
         return PCIBIOS_SUCCESSFUL;
 }
 
-struct pci_ops pci_v3_ops = {
+static struct pci_ops pci_v3_ops = {
         .read   = v3_read_config,
         .write  = v3_write_config,
 };
 
-static struct resource non_mem = {
-        .name   = "PCI non-prefetchable",
-        .start  = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START,
-        .end    = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE - 1,
-        .flags  = IORESOURCE_MEM,
-};
-
-static struct resource pre_mem = {
-        .name   = "PCI prefetchable",
-        .start  = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START,
-        .end    = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START + PCI_BUS_PREMEM_SIZE - 1,
-        .flags  = IORESOURCE_MEM | IORESOURCE_PREFETCH,
-};
-
 static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
 {
         if (request_resource(&iomem_resource, &non_mem)) {
@@ -471,7 +646,7 @@ static irqreturn_t v3_irq(int dummy, void *devid)
         return IRQ_HANDLED;
 }
 
-int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
+static int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
 {
         int ret = 0;
 
@@ -479,7 +654,7 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
                 return -EINVAL;
 
         if (nr == 0) {
-                sys->mem_offset = PHYS_PCI_MEM_BASE;
+                sys->mem_offset = non_mem.start;
                 ret = pci_v3_setup_resources(sys);
         }
 
@@ -490,18 +665,10 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
  * V3_LB_BASE? - local bus address
  * V3_LB_MAP?  - pci bus address
  */
-void __init pci_v3_preinit(void)
+static void __init pci_v3_preinit(void)
 {
         unsigned long flags;
         unsigned int temp;
-        int ret;
-
-        /* Remap the Integrator system controller */
-        ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
-        if (!ap_syscon_base) {
-                pr_err("unable to remap the AP syscon for PCIv3\n");
-                return;
-        }
 
         pcibios_min_mem = 0x00100000;
 
@@ -525,7 +692,7 @@ void __init pci_v3_preinit(void)
          * Setup window 0 - PCI non-prefetchable memory
          *  Local: 0x40000000 Bus: 0x00000000 Size: 256MB
          */
-        v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
+        v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
                         V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
         v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(PCI_BUS_NONMEM_START) |
                         V3_LB_MAP_TYPE_MEM);
@@ -534,7 +701,7 @@ void __init pci_v3_preinit(void)
          * Setup window 1 - PCI prefetchable memory
          *  Local: 0x50000000 Bus: 0x10000000 Size: 256MB
          */
-        v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
+        v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) |
                         V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
                         V3_LB_BASE_ENABLE);
         v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
@@ -543,7 +710,7 @@ void __init pci_v3_preinit(void)
         /*
          * Setup window 2 - PCI IO
          */
-        v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(PHYS_PCI_IO_BASE) |
+        v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_mem.start) |
                         V3_LB_BASE_ENABLE);
         v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
 
@@ -578,18 +745,10 @@ void __init pci_v3_preinit(void)
         v3_writeb(V3_LB_IMASK, 0x28);
         __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
 
-        /*
-         * Grab the PCI error interrupt.
-         */
-        ret = request_irq(IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
-        if (ret)
-                printk(KERN_ERR "PCI: unable to grab PCI error "
-                       "interrupt: %d\n", ret);
-
         raw_spin_unlock_irqrestore(&v3_lock, flags);
 }
 
-void __init pci_v3_postinit(void)
+static void __init pci_v3_postinit(void)
 {
         unsigned int pci_cmd;
 
@@ -608,5 +767,278 @@ void __init pci_v3_postinit(void)
                        "interrupt: %d\n", ret);
 #endif
 
-        register_isa_ports(PHYS_PCI_MEM_BASE, PHYS_PCI_IO_BASE, 0);
+        register_isa_ports(non_mem.start, io_mem.start, 0);
+}
+
+/*
+ * A small note about bridges and interrupts.  The DECchip 21050 (and
+ * later) adheres to the PCI-PCI bridge specification.  This says that
+ * the interrupts on the other side of a bridge are swizzled in the
+ * following manner:
+ *
+ * Dev    Interrupt   Interrupt
+ *        Pin on      Pin on
+ *        Device      Connector
+ *
+ *   4    A           A
+ *        B           B
+ *        C           C
+ *        D           D
+ *
+ *   5    A           B
+ *        B           C
+ *        C           D
+ *        D           A
+ *
+ *   6    A           C
+ *        B           D
+ *        C           A
+ *        D           B
+ *
+ *   7    A           D
+ *        B           A
+ *        C           B
+ *        D           C
+ *
+ * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
+ * Thus, each swizzle is ((pin-1) + (device#-4)) % 4
+ */
+
+/*
+ * This routine handles multiple bridges.
+ */
+static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp)
+{
+        if (*pinp == 0)
+                *pinp = 1;
+
+        return pci_common_swizzle(dev, pinp);
+}
+
+static int irq_tab[4] __initdata = {
+        IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3
+};
+
+/*
+ * map the specified device/slot/pin to an IRQ.  This works out such
+ * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
+ */
+static int __init pci_v3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int intnr = ((slot - 9) + (pin - 1)) & 3;
+
+        return irq_tab[intnr];
+}
+
+static struct hw_pci pci_v3 __initdata = {
+        .swizzle                = pci_v3_swizzle,
+        .setup                  = pci_v3_setup,
+        .nr_controllers         = 1,
+        .ops                    = &pci_v3_ops,
+        .preinit                = pci_v3_preinit,
+        .postinit               = pci_v3_postinit,
+};
+
+#ifdef CONFIG_OF
+
+static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        struct of_irq oirq;
+        int ret;
+
+        ret = of_irq_map_pci(dev, &oirq);
+        if (ret) {
+                dev_err(&dev->dev, "of_irq_map_pci() %d\n", ret);
+                /* Proper return code 0 == NO_IRQ */
+                return 0;
+        }
+
+        return irq_create_of_mapping(oirq.controller, oirq.specifier,
+                                     oirq.size);
+}
+
+static int __init pci_v3_dtprobe(struct platform_device *pdev,
+                                struct device_node *np)
+{
+        struct of_pci_range_parser parser;
+        struct of_pci_range range;
+        struct resource *res;
+        int irq, ret;
+
+        if (of_pci_range_parser_init(&parser, np))
+                return -EINVAL;
+
+        /* Get base for bridge registers */
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "unable to obtain PCIv3 base\n");
+                return -ENODEV;
+        }
+        pci_v3_base = devm_ioremap(&pdev->dev, res->start,
+                                   resource_size(res));
+        if (!pci_v3_base) {
+                dev_err(&pdev->dev, "unable to remap PCIv3 base\n");
+                return -ENODEV;
+        }
+
+        /* Get and request error IRQ resource */
+        irq = platform_get_irq(pdev, 0);
+        if (irq <= 0) {
+                dev_err(&pdev->dev, "unable to obtain PCIv3 error IRQ\n");
+                return -ENODEV;
+        }
+        ret = devm_request_irq(&pdev->dev, irq, v3_irq, 0,
+                        "PCIv3 error", NULL);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "unable to request PCIv3 error IRQ %d (%d)\n", irq, ret);
+                return ret;
+        }
+
+        for_each_of_pci_range(&parser, &range) {
+                if (!range.flags) {
+                        of_pci_range_to_resource(&range, np, &conf_mem);
+                        conf_mem.name = "PCIv3 config";
+                }
+                if (range.flags & IORESOURCE_IO) {
+                        of_pci_range_to_resource(&range, np, &io_mem);
+                        io_mem.name = "PCIv3 I/O";
+                }
+                if ((range.flags & IORESOURCE_MEM) &&
+                        !(range.flags & IORESOURCE_PREFETCH)) {
+                        of_pci_range_to_resource(&range, np, &non_mem);
+                        non_mem.name = "PCIv3 non-prefetched mem";
+                }
+                if ((range.flags & IORESOURCE_MEM) &&
+                        (range.flags & IORESOURCE_PREFETCH)) {
+                        of_pci_range_to_resource(&range, np, &pre_mem);
+                        pre_mem.name = "PCIv3 prefetched mem";
+                }
+        }
+
+        if (!conf_mem.start || !io_mem.start ||
+            !non_mem.start || !pre_mem.start) {
+                dev_err(&pdev->dev, "missing ranges in device node\n");
+                return -EINVAL;
+        }
+
+        pci_v3.map_irq = pci_v3_map_irq_dt;
+        pci_common_init_dev(&pdev->dev, &pci_v3);
+
+        return 0;
+}
+
+#else
+
+static inline int pci_v3_dtprobe(struct platform_device *pdev,
+                                  struct device_node *np)
+{
+        return -EINVAL;
+}
+
+#endif
+
+static int __init pci_v3_probe(struct platform_device *pdev)
+{
+        struct device_node *np = pdev->dev.of_node;
+        int ret;
+
+        /* Remap the Integrator system controller */
+        ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
+        if (!ap_syscon_base) {
+                dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n");
+                return -ENODEV;
+        }
+
+        /* Device tree probe path */
+        if (np)
+                return pci_v3_dtprobe(pdev, np);
+
+        pci_v3_base = devm_ioremap(&pdev->dev, PHYS_PCI_V3_BASE, SZ_64K);
+        if (!pci_v3_base) {
+                dev_err(&pdev->dev, "unable to remap PCIv3 base\n");
+                return -ENODEV;
+        }
+
+        ret = devm_request_irq(&pdev->dev, IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
+        if (ret) {
+                dev_err(&pdev->dev, "unable to grab PCI error interrupt: %d\n",
+                        ret);
+                return -ENODEV;
+        }
+
+        conf_mem.name = "PCIv3 config";
+        conf_mem.start = PHYS_PCI_CONFIG_BASE;
+        conf_mem.end = PHYS_PCI_CONFIG_BASE + SZ_16M - 1;
+        conf_mem.flags = IORESOURCE_MEM;
+
+        io_mem.name = "PCIv3 I/O";
+        io_mem.start = PHYS_PCI_IO_BASE;
+        io_mem.end = PHYS_PCI_IO_BASE + SZ_16M - 1;
+        io_mem.flags = IORESOURCE_MEM;
+
+        non_mem.name = "PCIv3 non-prefetched mem";
+        non_mem.start = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START;
+        non_mem.end = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START +
+                PCI_BUS_NONMEM_SIZE - 1;
+        non_mem.flags = IORESOURCE_MEM;
+
+        pre_mem.name = "PCIv3 prefetched mem";
+        pre_mem.start = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START;
+        pre_mem.end = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START +
+                PCI_BUS_PREMEM_SIZE - 1;
+        pre_mem.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+
+        pci_v3.map_irq = pci_v3_map_irq;
+
+        pci_common_init_dev(&pdev->dev, &pci_v3);
+
+        return 0;
+}
+
+static const struct of_device_id pci_ids[] = {
+        { .compatible = "v3,v360epc-pci", },
+        {},
+};
+
+static struct platform_driver pci_v3_driver = {
+        .driver = {
+                .name = "pci-v3",
+                .of_match_table = pci_ids,
+        },
+};
+
+static int __init pci_v3_init(void)
+{
+        return platform_driver_probe(&pci_v3_driver, pci_v3_probe);
+}
+
+subsys_initcall(pci_v3_init);
+
+/*
+ * Static mappings for the PCIv3 bridge
+ *
+ * e8000000     40000000        PCI memory              PHYS_PCI_MEM_BASE       (max 512M)
+ * ec000000     61000000        PCI config space        PHYS_PCI_CONFIG_BASE    (max 16M)
+ * fee00000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
+ */
+static struct map_desc pci_v3_io_desc[] __initdata __maybe_unused = {
+        {
+                .virtual        = (unsigned long)PCI_MEMORY_VADDR,
+                .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE
+        }, {
+                .virtual        = (unsigned long)PCI_CONFIG_VADDR,
+                .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE
+        }
+};
+
+int __init pci_v3_early_init(void)
+{
+        iotable_init(pci_v3_io_desc, ARRAY_SIZE(pci_v3_io_desc));
+        vga_base = (unsigned long)PCI_MEMORY_VADDR;
+        pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
+        return 0;
 }
diff --git a/arch/arm/mach-integrator/pci_v3.h b/arch/arm/mach-integrator/pci_v3.h
new file mode 100644
index 000000000000..755fd29fed4a
--- /dev/null
+++ b/arch/arm/mach-integrator/pci_v3.h
@@ -0,0 +1,2 @@
+/* Simple oneliner include to the PCIv3 early init */
+extern int pci_v3_early_init(void);
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
new file mode 100644
index 000000000000..2dbd4ce3653c
--- /dev/null
+++ b/arch/arm/mach-keystone/Kconfig
@@ -0,0 +1,15 @@
+config ARCH_KEYSTONE
+        bool "Texas Instruments Keystone Devices"
+        depends on ARCH_MULTI_V7
+        select CPU_V7
+        select ARM_GIC
+        select HAVE_ARM_ARCH_TIMER
+        select HAVE_SMP
+        select CLKSRC_MMIO
+        select GENERIC_CLOCKEVENTS
+        select HAVE_SCHED_CLOCK
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARM_ERRATA_798181
+        help
+          Support for boards based on the Texas Instruments Keystone family of
+          SoCs.
diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile
new file mode 100644
index 000000000000..3f6b8ab82235
--- /dev/null
+++ b/arch/arm/mach-keystone/Makefile
@@ -0,0 +1,2 @@
+obj-y                                   := keystone.o
+obj-$(CONFIG_SMP)                       += platsmp.o
diff --git a/arch/arm/mach-keystone/Makefile.boot b/arch/arm/mach-keystone/Makefile.boot
new file mode 100644
index 000000000000..f3835c43af61
--- /dev/null
+++ b/arch/arm/mach-keystone/Makefile.boot
@@ -0,0 +1 @@
+zreladdr-y      := 0x80008000
diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c
new file mode 100644
index 000000000000..fe4d9ff93a7e
--- /dev/null
+++ b/arch/arm/mach-keystone/keystone.c
@@ -0,0 +1,75 @@
+/*
+ * Keystone2 based boards and SOC related code.
+ *
+ * Copyright 2013 Texas Instruments, Inc.
+ *      Cyril Chemparathy <cyril@ti.com>
+ *      Santosh Shilimkar <santosh.shillimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/init.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+
+#include <asm/setup.h>
+#include <asm/mach/map.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/smp_plat.h>
+
+#include "keystone.h"
+
+#define PLL_RESET_WRITE_KEY_MASK                0xffff0000
+#define PLL_RESET_WRITE_KEY                     0x5a69
+#define PLL_RESET                               BIT(16)
+
+static void __iomem *keystone_rstctrl;
+
+static void __init keystone_init(void)
+{
+        struct device_node *node;
+
+        node = of_find_compatible_node(NULL, NULL, "ti,keystone-reset");
+        if (WARN_ON(!node))
+                pr_warn("ti,keystone-reset node undefined\n");
+
+        keystone_rstctrl = of_iomap(node, 0);
+        if (WARN_ON(!keystone_rstctrl))
+                pr_warn("ti,keystone-reset iomap error\n");
+
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char *keystone_match[] __initconst = {
+        "ti,keystone-evm",
+        NULL,
+};
+
+void keystone_restart(char mode, const char *cmd)
+{
+        u32 val;
+
+        BUG_ON(!keystone_rstctrl);
+
+        /* Enable write access to RSTCTRL */
+        val = readl(keystone_rstctrl);
+        val &= PLL_RESET_WRITE_KEY_MASK;
+        val |= PLL_RESET_WRITE_KEY;
+        writel(val, keystone_rstctrl);
+
+        /* Reset the SOC */
+        val = readl(keystone_rstctrl);
+        val &= ~PLL_RESET;
+        writel(val, keystone_rstctrl);
+}
+
+DT_MACHINE_START(KEYSTONE, "Keystone")
+        .smp            = smp_ops(keystone_smp_ops),
+        .init_machine   = keystone_init,
+        .dt_compat      = keystone_match,
+        .restart        = keystone_restart,
+MACHINE_END
diff --git a/arch/arm/mach-keystone/keystone.h b/arch/arm/mach-keystone/keystone.h
new file mode 100644
index 000000000000..43a1b4789a6e
--- /dev/null
+++ b/arch/arm/mach-keystone/keystone.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2013 Texas Instruments, Inc.
+ *      Cyril Chemparathy <cyril@ti.com>
+ *      Santosh Shilimkar <santosh.shillimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#ifndef __KEYSTONE_H__
+#define __KEYSTONE_H__
+
+extern struct smp_operations keystone_smp_ops;
+extern void secondary_startup(void);
+
+#endif /* __KEYSTONE_H__ */
diff --git a/arch/arm/mach-keystone/platsmp.c b/arch/arm/mach-keystone/platsmp.c
new file mode 100644
index 000000000000..630ab3bd5f78
--- /dev/null
+++ b/arch/arm/mach-keystone/platsmp.c
@@ -0,0 +1,52 @@
+/*
+ * Keystone SOC SMP platform code
+ *
+ * Copyright 2013 Texas Instruments, Inc.
+ *      Cyril Chemparathy <cyril@ti.com>
+ *      Santosh Shilimkar <santosh.shillimkar@ti.com>
+ *
+ * Based on platsmp.c, Copyright (C) 2002 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+
+#include <asm/smp_plat.h>
+#include <asm/prom.h>
+
+#include "keystone.h"
+
+static int __cpuinit keystone_smp_boot_secondary(unsigned int cpu,
+                                                struct task_struct *idle)
+{
+        unsigned long start = virt_to_phys(&secondary_startup);
+        int error;
+
+        pr_debug("keystone-smp: booting cpu %d, vector %08lx\n",
+                 cpu, start);
+
+        asm volatile (
+                "mov    r0, #0\n"       /* power on cmd */
+                "mov    r1, %1\n"       /* cpu          */
+                "mov    r2, %2\n"       /* start        */
+                ".inst  0xe1600070\n"   /* smc #0       */
+                "mov    %0, r0\n"
+                : "=r" (error)
+                : "r"(cpu), "r"(start)
+                : "cc", "r0", "r1", "r2", "memory"
+        );
+
+        pr_debug("keystone-smp: monitor returned %d\n", error);
+
+        return error;
+}
+
+struct smp_operations keystone_smp_ops __initdata = {
+        .smp_init_cpus          = arm_dt_init_cpu_maps,
+        .smp_boot_secondary     = keystone_smp_boot_secondary,
+};
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 7509a89af967..e610e137aa36 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -8,12 +8,6 @@ config MACH_D2NET_V2
           Say 'Y' here if you want your kernel to support the
           LaCie d2 Network v2 NAS.
 
-config MACH_DB88F6281_BP
-        bool "Marvell DB-88F6281-BP Development Board"
-        help
-          Say 'Y' here if you want your kernel to support the
-          Marvell DB-88F6281-BP Development Board.
-
 config MACH_DOCKSTAR
         bool "Seagate FreeAgent DockStar"
         help
@@ -134,13 +128,12 @@ comment "Device tree entries"
 
 config ARCH_KIRKWOOD_DT
         bool "Marvell Kirkwood Flattened Device Tree"
+        select KIRKWOOD_CLK
         select POWER_SUPPLY
         select POWER_RESET
         select POWER_RESET_GPIO
         select REGULATOR
         select REGULATOR_FIXED_VOLTAGE
-        select MVEBU_CLK_CORE
-        select MVEBU_CLK_GATING
         select USE_OF
         help
           Say 'Y' here if you want your kernel to support the
@@ -153,6 +146,13 @@ config MACH_CLOUDBOX_DT
           Say 'Y' here if you want your kernel to support the LaCie
           CloudBox NAS, using Flattened Device Tree.
 
+config MACH_DB88F628X_BP_DT
+        bool "Marvell DB-88F628x-BP Development Board (Flattened Device Tree)"
+        help
+          Say 'Y' here if you want your kernel to support the Marvell
+          DB-88F6281-BP and DB-88F6282-BP Development Board (Flattened
+          Device Tree).
+
 config MACH_DLINK_KIRKWOOD_DT
         bool "D-Link Kirkwood-based NAS (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
@@ -272,14 +272,6 @@ config MACH_NETSPACE_V2_DT
           Say 'Y' here if you want your kernel to support the LaCie
           Network Space v2 NAS, using Flattened Device Tree.
 
-config MACH_NSA310_DT
-        bool "ZyXEL NSA-310 (Flattened Device Tree)"
-        select ARCH_KIRKWOOD_DT
-        select ARM_ATAG_DTB_COMPAT
-        help
-          Say 'Y' here if you want your kernel to support the
-          ZyXEL NSA-310 board (Flattened Device Tree).
-
 config MACH_OPENBLOCKS_A6_DT
         bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index e1f3735d3415..2fdc3a7ad226 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -1,7 +1,6 @@
 obj-y                           += common.o irq.o pcie.o mpp.o
 
 obj-$(CONFIG_MACH_D2NET_V2)             += d2net_v2-setup.o lacie_v2-common.o
-obj-$(CONFIG_MACH_DB88F6281_BP)         += db88f6281-bp-setup.o
 obj-$(CONFIG_MACH_DOCKSTAR)             += dockstar-setup.o
 obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG)     += sheevaplug-setup.o
 obj-$(CONFIG_MACH_GURUPLUG)             += guruplug-setup.o
@@ -21,6 +20,7 @@ obj-$(CONFIG_MACH_TS41X)		+= ts41x-setup.o tsx1x-common.o
 
 obj-$(CONFIG_ARCH_KIRKWOOD_DT)          += board-dt.o
 obj-$(CONFIG_MACH_CLOUDBOX_DT)          += board-ns2.o
+obj-$(CONFIG_MACH_DB88F628X_BP_DT)      += board-db88f628x-bp.o
 obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT)    += board-dnskw.o
 obj-$(CONFIG_MACH_DOCKSTAR_DT)          += board-dockstar.o
 obj-$(CONFIG_MACH_DREAMPLUG_DT)         += board-dreamplug.o
@@ -37,7 +37,6 @@ obj-$(CONFIG_MACH_NETSPACE_LITE_V2_DT)	+= board-ns2.o
 obj-$(CONFIG_MACH_NETSPACE_MAX_V2_DT)   += board-ns2.o
 obj-$(CONFIG_MACH_NETSPACE_MINI_V2_DT)  += board-ns2.o
 obj-$(CONFIG_MACH_NETSPACE_V2_DT)       += board-ns2.o
-obj-$(CONFIG_MACH_NSA310_DT)            += board-nsa310.o
 obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT)     += board-openblocks_a6.o
 obj-$(CONFIG_MACH_READYNAS_DT)          += board-readynas.o
 obj-$(CONFIG_MACH_TOPKICK_DT)           += board-usi_topkick.o
diff --git a/arch/arm/mach-kirkwood/board-db88f628x-bp.c b/arch/arm/mach-kirkwood/board-db88f628x-bp.c
new file mode 100644
index 000000000000..2f574bc8ed40
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-db88f628x-bp.c
@@ -0,0 +1,24 @@
+/*
+ * Saeed Bishara <saeed@marvell.com>
+ *
+ * Marvell DB-88F628{1,2}-BP Development Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/mv643xx_eth.h>
+#include "common.h"
+
+static struct mv643xx_eth_platform_data db88f628x_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+
+void __init db88f628x_init(void)
+{
+        kirkwood_ge00_init(&db88f628x_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e9647b80cb59..cee5dc71cb60 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -15,7 +15,6 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
 #include <linux/kexec.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -25,11 +24,6 @@
 #include <plat/common.h>
 #include "common.h"
 
-static struct of_device_id kirkwood_dt_match_table[] __initdata = {
-        { .compatible = "simple-bus", },
-        { }
-};
-
 /*
  * There are still devices that doesn't know about DT yet.  Get clock
  * gates here and add a clock lookup alias, so that old platform
@@ -77,7 +71,7 @@ static void __init kirkwood_legacy_clk_init(void)
 
 static void __init kirkwood_of_clk_init(void)
 {
-        mvebu_clocks_init();
+        of_clk_init(NULL);
         kirkwood_legacy_clk_init();
 }
 
@@ -97,6 +91,8 @@ static void __init kirkwood_dt_init(void)
 
         kirkwood_l2_init();
 
+        kirkwood_cpufreq_init();
+
         /* Setup root of clk tree */
         kirkwood_of_clk_init();
 
@@ -147,6 +143,10 @@ static void __init kirkwood_dt_init(void)
             of_machine_is_compatible("lacie,netspace_v2"))
                 ns2_init();
 
+        if (of_machine_is_compatible("marvell,db-88f6281-bp") ||
+            of_machine_is_compatible("marvell,db-88f6282-bp"))
+                db88f628x_init();
+
         if (of_machine_is_compatible("mpl,cec4"))
                 mplcec4_init();
 
@@ -159,7 +159,7 @@ static void __init kirkwood_dt_init(void)
         if (of_machine_is_compatible("usi,topkick"))
                 usi_topkick_init();
 
-        of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static const char * const kirkwood_dt_board_compat[] = {
@@ -181,6 +181,8 @@ static const char * const kirkwood_dt_board_compat[] = {
         "lacie,netspace_max_v2",
         "lacie,netspace_mini_v2",
         "lacie,netspace_v2",
+        "marvell,db-88f6281-bp",
+        "marvell,db-88f6282-bp",
         "mpl,cec4",
         "netgear,readynas-duo-v2",
         "plathome,openblocks-a6",
diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c
index c8ebde4919e2..98b5ad1bba90 100644
--- a/arch/arm/mach-kirkwood/board-iconnect.c
+++ b/arch/arm/mach-kirkwood/board-iconnect.c
@@ -22,11 +22,3 @@ void __init iconnect_init(void)
 {
         kirkwood_ge00_init(&iconnect_ge00_data);
 }
-
-static int __init iconnect_pci_init(void)
-{
-        if (of_machine_is_compatible("iom,iconnect"))
-                kirkwood_pcie_init(KW_PCIE0);
-        return 0;
-}
-subsys_initcall(iconnect_pci_init);
diff --git a/arch/arm/mach-kirkwood/board-mplcec4.c b/arch/arm/mach-kirkwood/board-mplcec4.c
index 7d6dc669e17f..938712e248f1 100644
--- a/arch/arm/mach-kirkwood/board-mplcec4.c
+++ b/arch/arm/mach-kirkwood/board-mplcec4.c
@@ -29,7 +29,6 @@ void __init mplcec4_init(void)
          */
         kirkwood_ge00_init(&mplcec4_ge00_data);
         kirkwood_ge01_init(&mplcec4_ge01_data);
-        kirkwood_pcie_init(KW_PCIE0);
 }
 
 
diff --git a/arch/arm/mach-kirkwood/board-nsa310.c b/arch/arm/mach-kirkwood/board-nsa310.c
deleted file mode 100644
index 55ade93b93bf..000000000000
--- a/arch/arm/mach-kirkwood/board-nsa310.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/nsa-310-setup.c
- *
- * ZyXEL NSA-310 Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <mach/kirkwood.h>
-#include <linux/of.h>
-#include "common.h"
-
-static int __init nsa310_pci_init(void)
-{
-        if (of_machine_is_compatible("zyxel,nsa310"))
-                kirkwood_pcie_init(KW_PCIE0);
-
-        return 0;
-}
-
-subsys_initcall(nsa310_pci_init);
diff --git a/arch/arm/mach-kirkwood/board-readynas.c b/arch/arm/mach-kirkwood/board-readynas.c
index fb42c20e273f..341b82d9cadb 100644
--- a/arch/arm/mach-kirkwood/board-readynas.c
+++ b/arch/arm/mach-kirkwood/board-readynas.c
@@ -24,5 +24,4 @@ static struct mv643xx_eth_platform_data netgear_readynas_ge00_data = {
 void __init netgear_readynas_init(void)
 {
         kirkwood_ge00_init(&netgear_readynas_ge00_data);
-        kirkwood_pcie_init(KW_PCIE0);
 }
diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c
index acb0187c7ee1..4695d5f35fc9 100644
--- a/arch/arm/mach-kirkwood/board-ts219.c
+++ b/arch/arm/mach-kirkwood/board-ts219.c
@@ -41,13 +41,3 @@ void __init qnap_dt_ts219_init(void)
 
         pm_power_off = qnap_tsx1x_power_off;
 }
-
-/* FIXME: Will not work with DT. Maybe use MPP40_GPIO? */
-static int __init ts219_pci_init(void)
-{
-        if (machine_is_ts219())
-                kirkwood_pcie_init(KW_PCIE0);
-
-        return 0;
-}
-subsys_initcall(ts219_pci_init);
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index f38922897563..7c72c725b711 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -598,6 +598,29 @@ void __init kirkwood_audio_init(void)
 }
 
 /*****************************************************************************
+ * CPU Frequency
+ ****************************************************************************/
+static struct resource kirkwood_cpufreq_resources[] = {
+        [0] = {
+                .start  = CPU_CONTROL_PHYS,
+                .end    = CPU_CONTROL_PHYS + 3,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device kirkwood_cpufreq_device = {
+        .name           = "kirkwood-cpufreq",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(kirkwood_cpufreq_resources),
+        .resource       = kirkwood_cpufreq_resources,
+};
+
+void __init kirkwood_cpufreq_init(void)
+{
+        platform_device_register(&kirkwood_cpufreq_device);
+}
+
+/*****************************************************************************
  * General
  ****************************************************************************/
 /*
@@ -648,30 +671,6 @@ char * __init kirkwood_id(void)
 
 void __init kirkwood_setup_wins(void)
 {
-        /*
-         * The PCIe windows will no longer be statically allocated
-         * here once Kirkwood is migrated to the pci-mvebu driver.
-         */
-        mvebu_mbus_add_window_remap_flags("pcie0.0",
-                                          KIRKWOOD_PCIE_IO_PHYS_BASE,
-                                          KIRKWOOD_PCIE_IO_SIZE,
-                                          KIRKWOOD_PCIE_IO_BUS_BASE,
-                                          MVEBU_MBUS_PCI_IO);
-        mvebu_mbus_add_window_remap_flags("pcie0.0",
-                                          KIRKWOOD_PCIE_MEM_PHYS_BASE,
-                                          KIRKWOOD_PCIE_MEM_SIZE,
-                                          MVEBU_MBUS_NO_REMAP,
-                                          MVEBU_MBUS_PCI_MEM);
-        mvebu_mbus_add_window_remap_flags("pcie1.0",
-                                          KIRKWOOD_PCIE1_IO_PHYS_BASE,
-                                          KIRKWOOD_PCIE1_IO_SIZE,
-                                          KIRKWOOD_PCIE1_IO_BUS_BASE,
-                                          MVEBU_MBUS_PCI_IO);
-        mvebu_mbus_add_window_remap_flags("pcie1.0",
-                                          KIRKWOOD_PCIE1_MEM_PHYS_BASE,
-                                          KIRKWOOD_PCIE1_MEM_SIZE,
-                                          MVEBU_MBUS_NO_REMAP,
-                                          MVEBU_MBUS_PCI_MEM);
         mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE,
                               KIRKWOOD_NAND_MEM_SIZE);
         mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE,
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 21da3b1ebd7b..e2e19b302c28 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -51,6 +51,8 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
                             int (*dev_ready)(struct mtd_info *));
 void kirkwood_audio_init(void);
 void kirkwood_cpuidle_init(void);
+void kirkwood_cpufreq_init(void);
+
 void kirkwood_restart(char, const char *);
 void kirkwood_clk_init(void);
 
@@ -119,6 +121,12 @@ void km_kirkwood_init(void);
 static inline void km_kirkwood_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_DB88F628X_BP_DT
+void db88f628x_init(void);
+#else
+static inline void db88f628x_init(void) {};
+#endif
+
 #ifdef CONFIG_MACH_MPLCEC4_DT
 void mplcec4_init(void);
 #else
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
deleted file mode 100644
index 5a369fe74754..000000000000
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/db88f6281-bp-setup.c
- *
- * Marvell DB-88F6281-BP Development Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/sizes.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/partitions.h>
-#include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/kirkwood.h>
-#include <linux/platform_data/mmc-mvsdio.h>
-#include "common.h"
-#include "mpp.h"
-
-static struct mtd_partition db88f6281_nand_parts[] = {
-        {
-                .name = "u-boot",
-                .offset = 0,
-                .size = SZ_1M
-        }, {
-                .name = "uImage",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size = SZ_4M
-        }, {
-                .name = "root",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size = MTDPART_SIZ_FULL
-        },
-};
-
-static struct mv643xx_eth_platform_data db88f6281_ge00_data = {
-        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
-};
-
-static struct mv_sata_platform_data db88f6281_sata_data = {
-        .n_ports        = 2,
-};
-
-static struct mvsdio_platform_data db88f6281_mvsdio_data = {
-        .gpio_write_protect     = 37,
-        .gpio_card_detect       = 38,
-};
-
-static unsigned int db88f6281_mpp_config[] __initdata = {
-        MPP0_NF_IO2,
-        MPP1_NF_IO3,
-        MPP2_NF_IO4,
-        MPP3_NF_IO5,
-        MPP4_NF_IO6,
-        MPP5_NF_IO7,
-        MPP18_NF_IO0,
-        MPP19_NF_IO1,
-        MPP37_GPIO,
-        MPP38_GPIO,
-        0
-};
-
-static void __init db88f6281_init(void)
-{
-        /*
-         * Basic setup. Needs to be called early.
-         */
-        kirkwood_init();
-        kirkwood_mpp_conf(db88f6281_mpp_config);
-
-        kirkwood_nand_init(ARRAY_AND_SIZE(db88f6281_nand_parts), 25);
-        kirkwood_ehci_init();
-        kirkwood_ge00_init(&db88f6281_ge00_data);
-        kirkwood_sata_init(&db88f6281_sata_data);
-        kirkwood_uart0_init();
-        kirkwood_sdio_init(&db88f6281_mvsdio_data);
-}
-
-static int __init db88f6281_pci_init(void)
-{
-        if (machine_is_db88f6281_bp()) {
-                u32 dev, rev;
-
-                kirkwood_pcie_id(&dev, &rev);
-                if (dev == MV88F6282_DEV_ID)
-                        kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
-                else
-                        kirkwood_pcie_init(KW_PCIE0);
-        }
-        return 0;
-}
-subsys_initcall(db88f6281_pci_init);
-
-MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
-        /* Maintainer: Saeed Bishara <saeed@marvell.com> */
-        .atag_offset    = 0x100,
-        .init_machine   = db88f6281_init,
-        .map_io         = kirkwood_map_io,
-        .init_early     = kirkwood_init_early,
-        .init_irq       = kirkwood_init_irq,
-        .init_time      = kirkwood_timer_init,
-        .restart        = kirkwood_restart,
-MACHINE_END
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 5c82b7dce4e2..d4cbe5e81bb4 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -17,6 +17,7 @@
 #define CPU_CONFIG_ERROR_PROP   0x00000004
 
 #define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
+#define CPU_CONTROL_PHYS        (BRIDGE_PHYS_BASE + 0x0104)
 #define CPU_RESET               0x00000002
 
 #define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
@@ -69,6 +70,7 @@
 #define CGC_RUNIT               (1 << 7)
 #define CGC_XOR0                (1 << 8)
 #define CGC_AUDIO               (1 << 9)
+#define CGC_POWERSAVE           (1 << 11)
 #define CGC_SATA0               (1 << 14)
 #define CGC_SATA1               (1 << 15)
 #define CGC_XOR1                (1 << 16)
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index 827cde42414f..e96fd71abd76 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -22,9 +22,10 @@ static unsigned int __init kirkwood_variant(void)
 
         kirkwood_pcie_id(&dev, &rev);
 
-        if ((dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) ||
-            (dev == MV88F6282_DEV_ID))
+        if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0)
                 return MPP_F6281_MASK;
+        if (dev == MV88F6282_DEV_ID)
+                return MPP_F6282_MASK;
         if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0)
                 return MPP_F6192_MASK;
         if (dev == MV88F6180_DEV_ID)
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 7f43e6c2f8c0..ddcb09f5bdd3 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -12,6 +12,7 @@
 #include <linux/pci.h>
 #include <linux/slab.h>
 #include <linux/clk.h>
+#include <linux/mbus.h>
 #include <video/vga.h>
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
@@ -253,6 +254,27 @@ static void __init add_pcie_port(int index, void __iomem *base)
 
 void __init kirkwood_pcie_init(unsigned int portmask)
 {
+        mvebu_mbus_add_window_remap_flags("pcie0.0",
+                                          KIRKWOOD_PCIE_IO_PHYS_BASE,
+                                          KIRKWOOD_PCIE_IO_SIZE,
+                                          KIRKWOOD_PCIE_IO_BUS_BASE,
+                                          MVEBU_MBUS_PCI_IO);
+        mvebu_mbus_add_window_remap_flags("pcie0.0",
+                                          KIRKWOOD_PCIE_MEM_PHYS_BASE,
+                                          KIRKWOOD_PCIE_MEM_SIZE,
+                                          MVEBU_MBUS_NO_REMAP,
+                                          MVEBU_MBUS_PCI_MEM);
+        mvebu_mbus_add_window_remap_flags("pcie1.0",
+                                          KIRKWOOD_PCIE1_IO_PHYS_BASE,
+                                          KIRKWOOD_PCIE1_IO_SIZE,
+                                          KIRKWOOD_PCIE1_IO_BUS_BASE,
+                                          MVEBU_MBUS_PCI_IO);
+        mvebu_mbus_add_window_remap_flags("pcie1.0",
+                                          KIRKWOOD_PCIE1_MEM_PHYS_BASE,
+                                          KIRKWOOD_PCIE1_MEM_SIZE,
+                                          MVEBU_MBUS_NO_REMAP,
+                                          MVEBU_MBUS_PCI_MEM);
+
         vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
 
         if (portmask & KW_PCIE0)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 80a8bcacd9d5..9eb63d724602 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -10,12 +10,11 @@ config ARCH_MVEBU
         select PLAT_ORION
         select SPARSE_IRQ
         select CLKDEV_LOOKUP
-        select MVEBU_CLK_CORE
-        select MVEBU_CLK_CPU
-        select MVEBU_CLK_GATING
         select MVEBU_MBUS
         select ZONE_DMA if ARM_LPAE
         select ARCH_REQUIRE_GPIOLIB
+        select MIGHT_HAVE_PCI
+        select PCI_QUIRKS if PCI
 
 if ARCH_MVEBU
 
@@ -30,6 +29,7 @@ config MACH_ARMADA_370_XP
 
 config MACH_ARMADA_370
         bool "Marvell Armada 370 boards"
+        select ARMADA_370_CLK
         select MACH_ARMADA_370_XP
         select PINCTRL_ARMADA_370
         help
@@ -38,6 +38,7 @@ config MACH_ARMADA_370
 
 config MACH_ARMADA_XP
         bool "Marvell Armada XP boards"
+        select ARMADA_XP_CLK
         select MACH_ARMADA_370_XP
         select PINCTRL_ARMADA_XP
         help
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 1c48890bb72b..97cbb8021919 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -14,13 +14,13 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/io.h>
 #include <linux/time-armada-370-xp.h>
-#include <linux/clk/mvebu.h>
 #include <linux/dma-mapping.h>
 #include <linux/mbus.h>
-#include <linux/irqchip.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -29,45 +29,49 @@
 #include "common.h"
 #include "coherency.h"
 
-static struct map_desc armada_370_xp_io_desc[] __initdata = {
-        {
-                .virtual        = (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE,
-                .pfn            = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
-                .length         = ARMADA_370_XP_REGS_SIZE,
-                .type           = MT_DEVICE,
-        },
-};
-
-void __init armada_370_xp_map_io(void)
+static void __init armada_370_xp_map_io(void)
 {
-        iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc));
+        debug_ll_io_init();
 }
 
-void __init armada_370_xp_timer_and_clk_init(void)
-{
-        mvebu_clocks_init();
-        armada_370_xp_timer_init();
-}
+/*
+ * This initialization will be replaced by a DT-based
+ * initialization once the mvebu-mbus driver gains DT support.
+ */
 
-void __init armada_370_xp_init_early(void)
+#define ARMADA_370_XP_MBUS_WINS_OFFS   0x20000
+#define ARMADA_370_XP_MBUS_WINS_SIZE   0x100
+#define ARMADA_370_XP_SDRAM_WINS_OFFS  0x20180
+#define ARMADA_370_XP_SDRAM_WINS_SIZE  0x20
+
+static void __init armada_370_xp_mbus_init(void)
 {
         char *mbus_soc_name;
+        struct device_node *dn;
+        const __be32 mbus_wins_offs = cpu_to_be32(ARMADA_370_XP_MBUS_WINS_OFFS);
+        const __be32 sdram_wins_offs = cpu_to_be32(ARMADA_370_XP_SDRAM_WINS_OFFS);
 
-        /*
-         * This initialization will be replaced by a DT-based
-         * initialization once the mvebu-mbus driver gains DT support.
-         */
         if (of_machine_is_compatible("marvell,armada370"))
                 mbus_soc_name = "marvell,armada370-mbus";
         else
                 mbus_soc_name = "marvell,armadaxp-mbus";
 
+        dn = of_find_node_by_name(NULL, "internal-regs");
+        BUG_ON(!dn);
+
         mvebu_mbus_init(mbus_soc_name,
-                        ARMADA_370_XP_MBUS_WINS_BASE,
+                        of_translate_address(dn, &mbus_wins_offs),
                         ARMADA_370_XP_MBUS_WINS_SIZE,
-                        ARMADA_370_XP_SDRAM_WINS_BASE,
+                        of_translate_address(dn, &sdram_wins_offs),
                         ARMADA_370_XP_SDRAM_WINS_SIZE);
+}
 
+static void __init armada_370_xp_timer_and_clk_init(void)
+{
+        of_clk_init(NULL);
+        armada_370_xp_timer_init();
+        coherency_init();
+        armada_370_xp_mbus_init();
 #ifdef CONFIG_CACHE_L2X0
         l2x0_of_init(0, ~0UL);
 #endif
@@ -76,7 +80,6 @@ void __init armada_370_xp_init_early(void)
 static void __init armada_370_xp_dt_init(void)
 {
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-        coherency_init();
 }
 
 static const char * const armada_370_xp_dt_compat[] = {
@@ -88,8 +91,6 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)")
         .smp            = smp_ops(armada_xp_smp_ops),
         .init_machine   = armada_370_xp_dt_init,
         .map_io         = armada_370_xp_map_io,
-        .init_early     = armada_370_xp_init_early,
-        .init_irq       = irqchip_init,
         .init_time      = armada_370_xp_timer_and_clk_init,
         .restart        = mvebu_restart,
         .dt_compat      = armada_370_xp_dt_compat,
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index 2070e1b4f342..c612b2c4ed6c 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -15,16 +15,6 @@
 #ifndef __MACH_ARMADA_370_XP_H
 #define __MACH_ARMADA_370_XP_H
 
-#define ARMADA_370_XP_REGS_PHYS_BASE    0xd0000000
-#define ARMADA_370_XP_REGS_VIRT_BASE    IOMEM(0xfec00000)
-#define ARMADA_370_XP_REGS_SIZE         SZ_1M
-
-/* These defines can go away once mvebu-mbus has a DT binding */
-#define ARMADA_370_XP_MBUS_WINS_BASE    (ARMADA_370_XP_REGS_PHYS_BASE + 0x20000)
-#define ARMADA_370_XP_MBUS_WINS_SIZE    0x100
-#define ARMADA_370_XP_SDRAM_WINS_BASE   (ARMADA_370_XP_REGS_PHYS_BASE + 0x20180)
-#define ARMADA_370_XP_SDRAM_WINS_SIZE   0x20
-
 #ifdef CONFIG_SMP
 #include <linux/cpumask.h>
 
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 8278960066c3..32fcf69f4202 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -25,16 +25,11 @@
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <asm/smp_plat.h>
+#include <asm/cacheflush.h>
 #include "armada-370-xp.h"
 
-/*
- * Some functions in this file are called very early during SMP
- * initialization. At that time the device tree framework is not yet
- * ready, and it is not possible to get the register address to
- * ioremap it. That's why the pointer below is given with an initial
- * value matching its virtual mapping
- */
-static void __iomem *coherency_base = ARMADA_370_XP_REGS_VIRT_BASE + 0x20200;
+unsigned long __cpuinitdata coherency_phys_base;
+static void __iomem *coherency_base;
 static void __iomem *coherency_cpu_base;
 
 /* Coherency fabric registers */
@@ -47,18 +42,6 @@ static struct of_device_id of_coherency_table[] = {
         { /* end of list */ },
 };
 
-#ifdef CONFIG_SMP
-int coherency_get_cpu_count(void)
-{
-        int reg, cnt;
-
-        reg = readl(coherency_base + COHERENCY_FABRIC_CFG_OFFSET);
-        cnt = (reg & 0xF) + 1;
-
-        return cnt;
-}
-#endif
-
 /* Function defined in coherency_ll.S */
 int ll_set_cpu_coherent(void __iomem *base_addr, unsigned int hw_cpu_id);
 
@@ -143,13 +126,30 @@ int __init coherency_init(void)
 
         np = of_find_matching_node(NULL, of_coherency_table);
         if (np) {
+                struct resource res;
                 pr_info("Initializing Coherency fabric\n");
+                of_address_to_resource(np, 0, &res);
+                coherency_phys_base = res.start;
+                /*
+                 * Ensure secondary CPUs will see the updated value,
+                 * which they read before they join the coherency
+                 * fabric, and therefore before they are coherent with
+                 * the boot CPU cache.
+                 */
+                sync_cache_w(&coherency_phys_base);
                 coherency_base = of_iomap(np, 0);
                 coherency_cpu_base = of_iomap(np, 1);
                 set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
-                bus_register_notifier(&platform_bus_type,
-                                        &mvebu_hwcc_platform_nb);
         }
 
         return 0;
 }
+
+static int __init coherency_late_init(void)
+{
+        bus_register_notifier(&platform_bus_type,
+                              &mvebu_hwcc_platform_nb);
+        return 0;
+}
+
+postcore_initcall(coherency_late_init);
diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h
index 2f428137f6fe..df33ad8a6c08 100644
--- a/arch/arm/mach-mvebu/coherency.h
+++ b/arch/arm/mach-mvebu/coherency.h
@@ -14,10 +14,6 @@
 #ifndef __MACH_370_XP_COHERENCY_H
 #define __MACH_370_XP_COHERENCY_H
 
-#ifdef CONFIG_SMP
-int coherency_get_cpu_count(void);
-#endif
-
 int set_cpu_coherent(int cpu_id, int smp_group_id);
 int coherency_init(void);
 
diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index 53e8391192cd..5476669ba905 100644
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -32,15 +32,21 @@ ENTRY(ll_set_cpu_coherent)
 
         /* Add CPU to SMP group - Atomic */
         add     r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET
-        ldr     r2, [r3]
+1:
+        ldrex   r2, [r3]
         orr     r2, r2, r1
-        str     r2, [r3]
+        strex   r0, r2, [r3]
+        cmp     r0, #0
+        bne 1b
 
         /* Enable coherency on CPU - Atomic */
-        add     r3, r0, #ARMADA_XP_CFB_CFG_REG_OFFSET
-        ldr     r2, [r3]
+        add     r3, r3, #ARMADA_XP_CFB_CFG_REG_OFFSET
+1:
+        ldrex   r2, [r3]
         orr     r2, r2, r1
-        str     r2, [r3]
+        strex   r0, r2, [r3]
+        cmp     r0, #0
+        bne 1b
 
         dsb
 
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index aa27bc2ffb60..98defd5e92cd 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -15,6 +15,8 @@
 #ifndef __ARCH_MVEBU_COMMON_H
 #define __ARCH_MVEBU_COMMON_H
 
+#define ARMADA_XP_MAX_CPUS 4
+
 void mvebu_restart(char mode, const char *cmd);
 
 void armada_370_xp_init_irq(void);
diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S
index a06e0ede8c08..7147300c8af2 100644
--- a/arch/arm/mach-mvebu/headsmp.S
+++ b/arch/arm/mach-mvebu/headsmp.S
@@ -21,12 +21,6 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
-/*
- * At this stage the secondary CPUs don't have acces yet to the MMU, so
- * we have to provide physical addresses
- */
-#define ARMADA_XP_CFB_BASE           0xD0020200
-
         __CPUINIT
 
 /*
@@ -35,15 +29,21 @@
  * startup
  */
 ENTRY(armada_xp_secondary_startup)
+        /* Get coherency fabric base physical address */
+        adr     r0, 1f
+        ldr     r1, [r0]
+        ldr     r0, [r0, r1]
 
         /* Read CPU id */
         mrc     p15, 0, r1, c0, c0, 5
         and     r1, r1, #0xF
 
         /* Add CPU to coherency fabric */
-        ldr     r0, =ARMADA_XP_CFB_BASE
-
         bl      ll_set_cpu_coherent
         b       secondary_startup
 
 ENDPROC(armada_xp_secondary_startup)
+
+        .align 2
+1:
+        .long   coherency_phys_base - .
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index 875ea748391c..93f2f3ab45f1 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -88,8 +88,16 @@ static int __cpuinit armada_xp_boot_secondary(unsigned int cpu,
 
 static void __init armada_xp_smp_init_cpus(void)
 {
+        struct device_node *np;
         unsigned int i, ncores;
-        ncores = coherency_get_cpu_count();
+
+        np = of_find_node_by_name(NULL, "cpus");
+        if (!np)
+                panic("No 'cpus' node found\n");
+
+        ncores = of_get_child_count(np);
+        if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
+                panic("Invalid number of CPUs in DT\n");
 
         /* Limit possible CPUs to defconfig */
         if (ncores > nr_cpu_ids) {
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f49cd51e162a..1bfe9ee0331b 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -149,6 +149,14 @@ config SOC_AM33XX
         select MULTI_IRQ_HANDLER
         select COMMON_CLK
 
+config SOC_AM43XX
+        bool "TI AM43x"
+        select CPU_V7
+        select MULTI_IRQ_HANDLER
+        select ARM_GIC
+        select COMMON_CLK
+        select MACH_OMAP_GENERIC
+
 config OMAP_PACKAGE_ZAF
        bool
 
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 55a9d6777683..ec2e128074d8 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
 obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
 obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
 obj-$(CONFIG_SOC_OMAP5)  += prm44xx.o $(hwmod-common) $(secure-common)
+obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
 
 ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
 obj-y += mcbsp.o
@@ -38,6 +39,7 @@ omap-4-5-common				=  omap4-common.o omap-wakeupgen.o \
                                            sleep44xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(omap-4-5-common) $(smp-y)
 obj-$(CONFIG_SOC_OMAP5)                 += $(omap-4-5-common) $(smp-y)
+obj-$(CONFIG_SOC_AM43XX)                += $(omap-4-5-common)
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o                   :=-Wa,-march=armv7-a$(plus_sec)
@@ -58,6 +60,8 @@ obj-$(CONFIG_SOC_OMAP2420)		+= omap2-restart.o
 obj-$(CONFIG_SOC_OMAP2430)              += omap2-restart.o
 obj-$(CONFIG_SOC_AM33XX)                += am33xx-restart.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap3-restart.o
+obj-$(CONFIG_ARCH_OMAP4)                += omap4-restart.o
+obj-$(CONFIG_SOC_OMAP5)                 += omap4-restart.o
 
 # Pin multiplexing
 obj-$(CONFIG_SOC_OMAP2420)              += mux2420.o
@@ -110,6 +114,7 @@ obj-$(CONFIG_ARCH_OMAP2)		+= prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += vc3xxx_data.o vp3xxx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += prm33xx.o cm33xx.o
+obj-$(CONFIG_SOC_AM43XX)                += prm33xx.o cm33xx.o
 omap-prcm-4-5-common                    =  cminst44xx.o cm44xx.o prm44xx.o \
                                            prcm_mpu44xx.o prminst44xx.o \
                                            vc44xx_data.o vp44xx_data.o
@@ -125,8 +130,9 @@ obj-$(CONFIG_ARCH_OMAP3)		+= voltagedomains3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += voltagedomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += $(voltagedomain-common)
-obj-$(CONFIG_SOC_AM33XX)                += voltagedomains33xx_data.o
+obj-$(CONFIG_SOC_AM43XX)                += $(voltagedomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(voltagedomain-common)
+obj-$(CONFIG_SOC_OMAP5)                += voltagedomains54xx_data.o
 
 # OMAP powerdomain framework
 powerdomain-common                      += powerdomain.o powerdomain-common.o
@@ -140,7 +146,9 @@ obj-$(CONFIG_ARCH_OMAP4)		+= $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += powerdomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += $(powerdomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += powerdomains33xx_data.o
+obj-$(CONFIG_SOC_AM43XX)                += $(powerdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(powerdomain-common)
+obj-$(CONFIG_SOC_OMAP5)                 += powerdomains54xx_data.o
 
 # PRCM clockdomain control
 clockdomain-common                      += clockdomain.o
@@ -155,7 +163,9 @@ obj-$(CONFIG_ARCH_OMAP4)		+= $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += clockdomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += $(clockdomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += clockdomains33xx_data.o
+obj-$(CONFIG_SOC_AM43XX)                += $(clockdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(clockdomain-common)
+obj-$(CONFIG_SOC_OMAP5)                 += clockdomains54xx_data.o
 
 # Clock framework
 obj-$(CONFIG_ARCH_OMAP2)                += $(clock-common) clock2xxx.o
@@ -198,6 +208,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= omap_hwmod_2xxx_3xxx_interconnect_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_3xxx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += omap_hwmod_33xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap_hwmod_44xx_data.o
+obj-$(CONFIG_SOC_OMAP5)                 += omap_hwmod_54xx_data.o
 
 # EMU peripherals
 obj-$(CONFIG_OMAP3_EMU)                 += emu.o
diff --git a/arch/arm/mach-omap2/am33xx.h b/arch/arm/mach-omap2/am33xx.h
index 43296c1af9ee..5eef093e6738 100644
--- a/arch/arm/mach-omap2/am33xx.h
+++ b/arch/arm/mach-omap2/am33xx.h
@@ -21,6 +21,7 @@
 #define AM33XX_SCM_BASE         0x44E10000
 #define AM33XX_CTRL_BASE        AM33XX_SCM_BASE
 #define AM33XX_PRCM_BASE        0x44E00000
+#define AM43XX_PRCM_BASE        0x44DF0000
 #define AM33XX_TAP_BASE         (AM33XX_CTRL_BASE + 0x3FC)
 
 #endif /* __ASM_ARCH_AM33XX_H */
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 88aa6b1835c3..e5fbfed69aa2 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -185,3 +185,19 @@ DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
         .restart        = omap44xx_restart,
 MACHINE_END
 #endif
+
+#ifdef CONFIG_SOC_AM43XX
+static const char *am43_boards_compat[] __initdata = {
+        "ti,am43",
+        NULL,
+};
+
+DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
+        .map_io         = am33xx_map_io,
+        .init_early     = am43xx_init_early,
+        .init_irq       = omap_gic_of_init,
+        .init_machine   = omap_generic_init,
+        .init_time      = omap3_sync32k_timer_init,
+        .dt_compat      = am43_boards_compat,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index af3544ce4f02..0346de56436c 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -862,6 +862,33 @@ static struct clk_hw_omap wdt1_fck_hw = {
 
 DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
 
+static const char *pwmss_clk_parents[] = {
+        "dpll_per_m2_ck",
+};
+
+static const struct clk_ops ehrpwm_tbclk_ops = {
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
+                         NULL, NULL, 0,
+                         AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
+                         AM33XX_PWMSS0_TBCLKEN_SHIFT,
+                         NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
+                         NULL, NULL, 0,
+                         AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
+                         AM33XX_PWMSS1_TBCLKEN_SHIFT,
+                         NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
+                         NULL, NULL, 0,
+                         AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
+                         AM33XX_PWMSS2_TBCLKEN_SHIFT,
+                         NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
+
 /*
  * clkdev
  */
@@ -942,6 +969,9 @@ static struct omap_clk am33xx_clks[] = {
         CLK(NULL,       "clkout2_div_ck",       &clkout2_div_ck),
         CLK(NULL,       "timer_32k_ck",         &clkdiv32k_ick),
         CLK(NULL,       "timer_sys_ck",         &sys_clkin_ck),
+        CLK("48300200.ehrpwm",  "tbclk",        &ehrpwm0_tbclk),
+        CLK("48302200.ehrpwm",  "tbclk",        &ehrpwm1_tbclk),
+        CLK("48304200.ehrpwm",  "tbclk",        &ehrpwm2_tbclk),
 };
 
 
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 45cd26430d1f..334b76745900 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -3329,11 +3329,7 @@ static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
         CLK(NULL,       "cpefuse_fck",  &cpefuse_fck),
         CLK(NULL,       "ts_fck",       &ts_fck),
         CLK(NULL,       "usbtll_fck",   &usbtll_fck),
-        CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck),
-        CLK("usbhs_tll",        "usbtll_fck",   &usbtll_fck),
         CLK(NULL,       "usbtll_ick",   &usbtll_ick),
-        CLK("usbhs_omap",       "usbtll_ick",   &usbtll_ick),
-        CLK("usbhs_tll",        "usbtll_ick",   &usbtll_ick),
         CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick),
         CLK(NULL,       "mmchs3_ick",   &mmchs3_ick),
         CLK(NULL,       "mmchs3_fck",   &mmchs3_fck),
@@ -3343,7 +3339,6 @@ static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
         CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck),
         CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck),
         CLK(NULL,       "usbhost_ick",  &usbhost_ick),
-        CLK("usbhs_omap",       "usbhost_ick",  &usbhost_ick),
 };
 
 /*
@@ -3463,12 +3458,6 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "utmi_p2_gfclk",        &dummy_ck),
         CLK(NULL,       "xclk60mhsp1_ck",       &dummy_ck),
         CLK(NULL,       "xclk60mhsp2_ck",       &dummy_ck),
-        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &dummy_ck),
-        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &dummy_ck),
-        CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck),
-        CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck),
-        CLK("usbhs_tll",        "usb_tll_hs_usb_ch0_clk",       &dummy_ck),
-        CLK("usbhs_tll",        "usb_tll_hs_usb_ch1_clk",       &dummy_ck),
         CLK(NULL,       "init_60m_fclk",        &dummy_ck),
         CLK(NULL,       "gpt1_fck",     &gpt1_fck),
         CLK(NULL,       "aes2_ick",     &aes2_ick),
diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c
index 8f3bf4e50908..bbd6a3f717e6 100644
--- a/arch/arm/mach-omap2/clock36xx.c
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -20,11 +20,12 @@
 
 #include <linux/kernel.h>
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/io.h>
 
 #include "clock.h"
 #include "clock36xx.h"
-
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
 
 /**
  * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
@@ -39,29 +40,28 @@
  */
 int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
 {
-        struct clk_hw_omap *parent;
+        struct clk_divider *parent;
         struct clk_hw *parent_hw;
-        u32 dummy_v, orig_v, clksel_shift;
+        u32 dummy_v, orig_v;
         int ret;
 
         /* Clear PWRDN bit of HSDIVIDER */
         ret = omap2_dflt_clk_enable(clk);
 
         parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
-        parent = to_clk_hw_omap(parent_hw);
+        parent = to_clk_divider(parent_hw);
 
         /* Restore the dividers */
         if (!ret) {
-                clksel_shift = __ffs(parent->clksel_mask);
-                orig_v = __raw_readl(parent->clksel_reg);
+                orig_v = __raw_readl(parent->reg);
                 dummy_v = orig_v;
 
                 /* Write any other value different from the Read value */
-                dummy_v ^= (1 << clksel_shift);
-                __raw_writel(dummy_v, parent->clksel_reg);
+                dummy_v ^= (1 << parent->shift);
+                __raw_writel(dummy_v, parent->reg);
 
                 /* Write the original divider */
-                __raw_writel(orig_v, parent->clksel_reg);
+                __raw_writel(orig_v, parent->reg);
         }
 
         return ret;
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 2da37656a693..daeecf1b89fa 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -216,6 +216,7 @@ extern void __init omap243x_clockdomains_init(void);
 extern void __init omap3xxx_clockdomains_init(void);
 extern void __init am33xx_clockdomains_init(void);
 extern void __init omap44xx_clockdomains_init(void);
+extern void __init omap54xx_clockdomains_init(void);
 
 extern void clkdm_add_autodeps(struct clockdomain *clkdm);
 extern void clkdm_del_autodeps(struct clockdomain *clkdm);
diff --git a/arch/arm/mach-omap2/clockdomains54xx_data.c b/arch/arm/mach-omap2/clockdomains54xx_data.c
new file mode 100644
index 000000000000..1a3c69d2e14c
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains54xx_data.c
@@ -0,0 +1,464 @@
+/*
+ * OMAP54XX Clock domains framework
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Abhijit Pagare (abhijitpagare@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Paul Walmsley (paul@pwsan.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+#include "cm1_54xx.h"
+#include "cm2_54xx.h"
+
+#include "cm-regbits-54xx.h"
+#include "prm54xx.h"
+#include "prcm44xx.h"
+#include "prcm_mpu54xx.h"
+
+/* Static Dependencies for OMAP4 Clock Domains */
+
+static struct clkdm_dep c2c_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l3main2_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep cam_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep dma_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "ipu_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "l4sec_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep dsp_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l3main2_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep dss_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3main2_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep gpu_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep ipu_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "dsp_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "gpu_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l3main2_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "l4sec_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep iva_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep l3init_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "l4sec_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep mipiext_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l3main2_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep mpu_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "dsp_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "gpu_clkdm" },
+        { .clkdm_name = "ipu_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l3main2_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "l4sec_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+
+static struct clockdomain l4sec_54xx_clkdm = {
+        .name             = "l4sec_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS,
+        .dep_bit          = OMAP54XX_L4SEC_STATDEP_SHIFT,
+        .wkdep_srcs       = l4sec_wkup_sleep_deps,
+        .sleepdep_srcs    = l4sec_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain iva_54xx_clkdm = {
+        .name             = "iva_clkdm",
+        .pwrdm            = { .name = "iva_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_IVA_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_IVA_IVA_CDOFFS,
+        .dep_bit          = OMAP54XX_IVA_STATDEP_SHIFT,
+        .wkdep_srcs       = iva_wkup_sleep_deps,
+        .sleepdep_srcs    = iva_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain mipiext_54xx_clkdm = {
+        .name             = "mipiext_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS,
+        .wkdep_srcs       = mipiext_wkup_sleep_deps,
+        .sleepdep_srcs    = mipiext_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l3main2_54xx_clkdm = {
+        .name             = "l3main2_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS,
+        .dep_bit          = OMAP54XX_L3MAIN2_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l3main1_54xx_clkdm = {
+        .name             = "l3main1_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
+        .dep_bit          = OMAP54XX_L3MAIN1_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain custefuse_54xx_clkdm = {
+        .name             = "custefuse_clkdm",
+        .pwrdm            = { .name = "custefuse_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CUSTEFUSE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain ipu_54xx_clkdm = {
+        .name             = "ipu_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_IPU_CDOFFS,
+        .dep_bit          = OMAP54XX_IPU_STATDEP_SHIFT,
+        .wkdep_srcs       = ipu_wkup_sleep_deps,
+        .sleepdep_srcs    = ipu_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l4cfg_54xx_clkdm = {
+        .name             = "l4cfg_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS,
+        .dep_bit          = OMAP54XX_L4CFG_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain abe_54xx_clkdm = {
+        .name             = "abe_clkdm",
+        .pwrdm            = { .name = "abe_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_AON_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_AON_ABE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS,
+        .dep_bit          = OMAP54XX_ABE_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain dss_54xx_clkdm = {
+        .name             = "dss_clkdm",
+        .pwrdm            = { .name = "dss_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_DSS_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_DSS_DSS_CDOFFS,
+        .dep_bit          = OMAP54XX_DSS_STATDEP_SHIFT,
+        .wkdep_srcs       = dss_wkup_sleep_deps,
+        .sleepdep_srcs    = dss_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain dsp_54xx_clkdm = {
+        .name             = "dsp_clkdm",
+        .pwrdm            = { .name = "dsp_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_AON_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_AON_DSP_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS,
+        .dep_bit          = OMAP54XX_DSP_STATDEP_SHIFT,
+        .wkdep_srcs       = dsp_wkup_sleep_deps,
+        .sleepdep_srcs    = dsp_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain c2c_54xx_clkdm = {
+        .name             = "c2c_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_C2C_CDOFFS,
+        .wkdep_srcs       = c2c_wkup_sleep_deps,
+        .sleepdep_srcs    = c2c_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l4per_54xx_clkdm = {
+        .name             = "l4per_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS,
+        .dep_bit          = OMAP54XX_L4PER_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain gpu_54xx_clkdm = {
+        .name             = "gpu_clkdm",
+        .pwrdm            = { .name = "gpu_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_GPU_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_GPU_GPU_CDOFFS,
+        .dep_bit          = OMAP54XX_GPU_STATDEP_SHIFT,
+        .wkdep_srcs       = gpu_wkup_sleep_deps,
+        .sleepdep_srcs    = gpu_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain wkupaon_54xx_clkdm = {
+        .name             = "wkupaon_clkdm",
+        .pwrdm            = { .name = "wkupaon_pwrdm" },
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .cm_inst          = OMAP54XX_PRM_WKUPAON_CM_INST,
+        .clkdm_offs       = OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
+        .dep_bit          = OMAP54XX_WKUPAON_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain mpu0_54xx_clkdm = {
+        .name             = "mpu0_clkdm",
+        .pwrdm            = { .name = "cpu0_pwrdm" },
+        .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
+        .cm_inst          = OMAP54XX_PRCM_MPU_CM_C0_INST,
+        .clkdm_offs       = OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain mpu1_54xx_clkdm = {
+        .name             = "mpu1_clkdm",
+        .pwrdm            = { .name = "cpu1_pwrdm" },
+        .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
+        .cm_inst          = OMAP54XX_PRCM_MPU_CM_C1_INST,
+        .clkdm_offs       = OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain coreaon_54xx_clkdm = {
+        .name             = "coreaon_clkdm",
+        .pwrdm            = { .name = "coreaon_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_COREAON_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain mpu_54xx_clkdm = {
+        .name             = "mpu_clkdm",
+        .pwrdm            = { .name = "mpu_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_AON_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_AON_MPU_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS,
+        .wkdep_srcs       = mpu_wkup_sleep_deps,
+        .sleepdep_srcs    = mpu_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l3init_54xx_clkdm = {
+        .name             = "l3init_clkdm",
+        .pwrdm            = { .name = "l3init_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_L3INIT_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
+        .dep_bit          = OMAP54XX_L3INIT_STATDEP_SHIFT,
+        .wkdep_srcs       = l3init_wkup_sleep_deps,
+        .sleepdep_srcs    = l3init_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain dma_54xx_clkdm = {
+        .name             = "dma_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_DMA_CDOFFS,
+        .wkdep_srcs       = dma_wkup_sleep_deps,
+        .sleepdep_srcs    = dma_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l3instr_54xx_clkdm = {
+        .name             = "l3instr_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS,
+};
+
+static struct clockdomain emif_54xx_clkdm = {
+        .name             = "emif_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS,
+        .dep_bit          = OMAP54XX_EMIF_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain emu_54xx_clkdm = {
+        .name             = "emu_clkdm",
+        .pwrdm            = { .name = "emu_pwrdm" },
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .cm_inst          = OMAP54XX_PRM_EMU_CM_INST,
+        .clkdm_offs       = OMAP54XX_PRM_EMU_CM_EMU_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain cam_54xx_clkdm = {
+        .name             = "cam_clkdm",
+        .pwrdm            = { .name = "cam_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CAM_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CAM_CAM_CDOFFS,
+        .wkdep_srcs       = cam_wkup_sleep_deps,
+        .sleepdep_srcs    = cam_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+/* As clockdomains are added or removed above, this list must also be changed */
+static struct clockdomain *clockdomains_omap54xx[] __initdata = {
+        &l4sec_54xx_clkdm,
+        &iva_54xx_clkdm,
+        &mipiext_54xx_clkdm,
+        &l3main2_54xx_clkdm,
+        &l3main1_54xx_clkdm,
+        &custefuse_54xx_clkdm,
+        &ipu_54xx_clkdm,
+        &l4cfg_54xx_clkdm,
+        &abe_54xx_clkdm,
+        &dss_54xx_clkdm,
+        &dsp_54xx_clkdm,
+        &c2c_54xx_clkdm,
+        &l4per_54xx_clkdm,
+        &gpu_54xx_clkdm,
+        &wkupaon_54xx_clkdm,
+        &mpu0_54xx_clkdm,
+        &mpu1_54xx_clkdm,
+        &coreaon_54xx_clkdm,
+        &mpu_54xx_clkdm,
+        &l3init_54xx_clkdm,
+        &dma_54xx_clkdm,
+        &l3instr_54xx_clkdm,
+        &emif_54xx_clkdm,
+        &emu_54xx_clkdm,
+        &cam_54xx_clkdm,
+        NULL
+};
+
+void __init omap54xx_clockdomains_init(void)
+{
+        clkdm_register_platform_funcs(&omap4_clkdm_operations);
+        clkdm_register_clkdms(clockdomains_omap54xx);
+        clkdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/cm-regbits-54xx.h b/arch/arm/mach-omap2/cm-regbits-54xx.h
new file mode 100644
index 000000000000..e83b8e352b6e
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-54xx.h
@@ -0,0 +1,1737 @@
+/*
+ * OMAP54xx Clock Management register bits
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
+
+/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_MPU_DYNAMICDEP */
+#define OMAP54XX_ABE_DYNDEP_SHIFT                                       3
+#define OMAP54XX_ABE_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_ABE_DYNDEP_MASK                                        (1 << 3)
+
+/*
+ * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
+ * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_ABE_STATDEP_SHIFT                                      3
+#define OMAP54XX_ABE_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_ABE_STATDEP_MASK                                       (1 << 3)
+
+/*
+ * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_IVA,
+ * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO1,
+ * CM_AUTOIDLE_DPLL_UNIPRO2, CM_AUTOIDLE_DPLL_USB
+ */
+#define OMAP54XX_AUTO_DPLL_MODE_SHIFT                                   0
+#define OMAP54XX_AUTO_DPLL_MODE_WIDTH                                   0x3
+#define OMAP54XX_AUTO_DPLL_MODE_MASK                                    (0x7 << 0)
+
+/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_C2C_DYNDEP_SHIFT                                       18
+#define OMAP54XX_C2C_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_C2C_DYNDEP_MASK                                        (1 << 18)
+
+/* Used by CM_MPU_STATICDEP */
+#define OMAP54XX_C2C_STATDEP_SHIFT                                      18
+#define OMAP54XX_C2C_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_C2C_STATDEP_MASK                                       (1 << 18)
+
+/* Used by CM_IPU_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_CAM_DYNDEP_SHIFT                                       9
+#define OMAP54XX_CAM_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_CAM_DYNDEP_MASK                                        (1 << 9)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP,
+ * CM_MPU_STATICDEP
+ */
+#define OMAP54XX_CAM_STATDEP_SHIFT                                      9
+#define OMAP54XX_CAM_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_CAM_STATDEP_MASK                                       (1 << 9)
+
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_SHIFT                        13
+#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_MASK                         (1 << 13)
+
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_SHIFT                          12
+#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_WIDTH                          0x1
+#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_MASK                           (1 << 12)
+
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_ABE_GICLK_SHIFT                            9
+#define OMAP54XX_CLKACTIVITY_ABE_GICLK_WIDTH                            0x1
+#define OMAP54XX_CLKACTIVITY_ABE_GICLK_MASK                             (1 << 9)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_SHIFT                           9
+#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_WIDTH                           0x1
+#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_MASK                            (1 << 9)
+
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_SHIFT                          11
+#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_WIDTH                          0x1
+#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_MASK                           (1 << 11)
+
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_SHIFT                           8
+#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_WIDTH                           0x1
+#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_MASK                            (1 << 8)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_SHIFT                           13
+#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_WIDTH                           0x1
+#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_MASK                            (1 << 13)
+
+/* Used by CM_C2C_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_SHIFT                            9
+#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_WIDTH                            0x1
+#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_MASK                             (1 << 9)
+
+/* Used by CM_C2C_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_C2C_GICLK_SHIFT                            10
+#define OMAP54XX_CLKACTIVITY_C2C_GICLK_WIDTH                            0x1
+#define OMAP54XX_CLKACTIVITY_C2C_GICLK_MASK                             (1 << 10)
+
+/* Used by CM_C2C_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_SHIFT                         8
+#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_MASK                          (1 << 8)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_SHIFT                       11
+#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_MASK                        (1 << 11)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_CAM_GCLK_SHIFT                             8
+#define OMAP54XX_CLKACTIVITY_CAM_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_CAM_GCLK_MASK                              (1 << 8)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_SHIFT                         12
+#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_MASK                          (1 << 12)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_SHIFT                    12
+#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_WIDTH                    0x1
+#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_MASK                     (1 << 12)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_SHIFT              14
+#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_WIDTH              0x1
+#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_MASK               (1 << 14)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_SHIFT                     8
+#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_MASK                      (1 << 8)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_SHIFT                        9
+#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_MASK                         (1 << 9)
+
+/* Used by CM_CUSTEFUSE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_SHIFT                   8
+#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_WIDTH                   0x1
+#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_MASK                    (1 << 8)
+
+/* Used by CM_CUSTEFUSE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_SHIFT                  9
+#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_WIDTH                  0x1
+#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_MASK                   (1 << 9)
+
+/* Used by CM_EMIF_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_DLL_GCLK_SHIFT                             9
+#define OMAP54XX_CLKACTIVITY_DLL_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_DLL_GCLK_MASK                              (1 << 9)
+
+/* Used by CM_DMA_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_SHIFT                         8
+#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_MASK                          (1 << 8)
+
+/* Used by CM_DSP_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_DSP_GCLK_SHIFT                             8
+#define OMAP54XX_CLKACTIVITY_DSP_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_DSP_GCLK_MASK                              (1 << 8)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_SHIFT                            9
+#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_WIDTH                            0x1
+#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_MASK                             (1 << 9)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_SHIFT                         8
+#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_MASK                          (1 << 8)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_SHIFT                        10
+#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_MASK                         (1 << 10)
+
+/* Used by CM_EMIF_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_SHIFT                        8
+#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_MASK                         (1 << 8)
+
+/* Used by CM_EMIF_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_SHIFT                         11
+#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_MASK                          (1 << 11)
+
+/* Used by CM_EMIF_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_SHIFT                        10
+#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_MASK                         (1 << 10)
+
+/* Used by CM_EMU_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_SHIFT                         8
+#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_MASK                          (1 << 8)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_SHIFT                            10
+#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_WIDTH                            0x1
+#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_MASK                             (1 << 10)
+
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT                       10
+#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_MASK                        (1 << 10)
+
+/* Used by CM_GPU_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_SHIFT                        9
+#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_MASK                         (1 << 9)
+
+/* Used by CM_GPU_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_SHIFT                         10
+#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_MASK                          (1 << 10)
+
+/* Used by CM_GPU_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_SHIFT                         8
+#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_MASK                          (1 << 8)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_SHIFT                       12
+#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_MASK                        (1 << 12)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_SHIFT                       11
+#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_MASK                        (1 << 11)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT                   20
+#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH                   0x1
+#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK                    (1 << 20)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT                        26
+#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_MASK                         (1 << 26)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT                   21
+#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH                   0x1
+#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK                    (1 << 21)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT                        27
+#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_MASK                         (1 << 27)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_SHIFT                   6
+#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_WIDTH                   0x1
+#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_MASK                    (1 << 6)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_SHIFT                        7
+#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_MASK                         (1 << 7)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_SHIFT                            16
+#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_WIDTH                            0x1
+#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_MASK                             (1 << 16)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_IPU_GCLK_SHIFT                             8
+#define OMAP54XX_CLKACTIVITY_IPU_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_IPU_GCLK_MASK                              (1 << 8)
+
+/* Used by CM_IVA_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_IVA_GCLK_SHIFT                             8
+#define OMAP54XX_CLKACTIVITY_IVA_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_IVA_GCLK_MASK                              (1 << 8)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_SHIFT                     12
+#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_MASK                      (1 << 12)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_SHIFT                  28
+#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_WIDTH                  0x1
+#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_MASK                   (1 << 28)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_SHIFT                  29
+#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_WIDTH                  0x1
+#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_MASK                   (1 << 29)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_SHIFT                      8
+#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_MASK                       (1 << 8)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_SHIFT                      9
+#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_MASK                       (1 << 9)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_SHIFT      11
+#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_WIDTH      0x1
+#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_MASK       (1 << 11)
+
+/* Used by CM_L3INSTR_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_SHIFT               9
+#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_WIDTH               0x1
+#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_MASK                (1 << 9)
+
+/* Used by CM_L3INSTR_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_SHIFT                     8
+#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_MASK                      (1 << 8)
+
+/* Used by CM_L3INSTR_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_SHIFT                      10
+#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_MASK                       (1 << 10)
+
+/* Used by CM_L3MAIN1_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_SHIFT                     8
+#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_MASK                      (1 << 8)
+
+/* Used by CM_L3MAIN2_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_SHIFT                     8
+#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_MASK                      (1 << 8)
+
+/* Used by CM_L4CFG_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_SHIFT                       8
+#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_MASK                        (1 << 8)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_SHIFT                       8
+#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_MASK                        (1 << 8)
+
+/* Used by CM_L4SEC_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_SHIFT                       8
+#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_MASK                        (1 << 8)
+
+/* Used by CM_L4SEC_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_SHIFT                       9
+#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_MASK                        (1 << 9)
+
+/* Used by CM_MIPIEXT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_SHIFT                     8
+#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_MASK                      (1 << 8)
+
+/* Used by CM_MIPIEXT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_SHIFT                11
+#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_WIDTH                0x1
+#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_MASK                 (1 << 11)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_SHIFT                       2
+#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_MASK                        (1 << 2)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_SHIFT                           17
+#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_WIDTH                           0x1
+#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_MASK                            (1 << 17)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_SHIFT                           18
+#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_WIDTH                           0x1
+#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_MASK                            (1 << 18)
+
+/* Used by CM_MPU_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_MPU_GCLK_SHIFT                             8
+#define OMAP54XX_CLKACTIVITY_MPU_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_MPU_GCLK_MASK                              (1 << 8)
+
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PAD_CLKS_SHIFT                             14
+#define OMAP54XX_CLKACTIVITY_PAD_CLKS_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_PAD_CLKS_MASK                              (1 << 14)
+
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_SHIFT                     15
+#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_MASK                      (1 << 15)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_SHIFT                      3
+#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_MASK                       (1 << 3)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_SHIFT                      4
+#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_MASK                       (1 << 4)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_SHIFT                        15
+#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_MASK                         (1 << 15)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_SHIFT                        17
+#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_MASK                         (1 << 17)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_SHIFT                        18
+#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_MASK                         (1 << 18)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_SHIFT                        19
+#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_MASK                         (1 << 19)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_SHIFT                       19
+#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_MASK                        (1 << 19)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_SHIFT                    11
+#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_WIDTH                    0x1
+#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_MASK                     (1 << 11)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_SHIFT                      10
+#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_MASK                       (1 << 10)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_SHIFT                     9
+#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_MASK                      (1 << 9)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_SHIFT                              8
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_WIDTH                              0x1
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_MASK                               (1 << 8)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_SHIFT                          15
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_WIDTH                          0x1
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_MASK                           (1 << 15)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_SHIFT                         14
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_MASK                          (1 << 14)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_SHIFT                        9
+#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_MASK                         (1 << 9)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_SHIFT                        10
+#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_MASK                         (1 << 10)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_SHIFT                         11
+#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_MASK                          (1 << 11)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_SHIFT                         12
+#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_MASK                          (1 << 12)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_SHIFT                         13
+#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_MASK                          (1 << 13)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_SHIFT                         14
+#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_MASK                          (1 << 14)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT                        22
+#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_MASK                         (1 << 22)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT                        23
+#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_MASK                         (1 << 23)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT                        24
+#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_MASK                         (1 << 24)
+
+/* Used by CM_MIPIEXT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_SHIFT                     10
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_MASK                      (1 << 10)
+
+/* Used by CM_MIPIEXT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_SHIFT                    13
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_WIDTH                    0x1
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_MASK                     (1 << 13)
+
+/* Used by CM_MIPIEXT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_SHIFT               12
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_WIDTH               0x1
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_MASK                (1 << 12)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_SHIFT                     10
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_MASK                      (1 << 10)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_SHIFT                    13
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_WIDTH                    0x1
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_MASK                     (1 << 13)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_SHIFT                5
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_WIDTH                0x1
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_MASK                 (1 << 5)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_SHIFT                         14
+#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_MASK                          (1 << 14)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT                      15
+#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_MASK                       (1 << 15)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_SHIFT                   31
+#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_WIDTH                   0x1
+#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_MASK                    (1 << 31)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT                        30
+#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_MASK                         (1 << 30)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT                      25
+#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK                       (1 << 25)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_SHIFT                    11
+#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_WIDTH                    0x1
+#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_MASK                     (1 << 11)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_SHIFT                        12
+#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_MASK                         (1 << 12)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_SHIFT              13
+#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_WIDTH              0x1
+#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_MASK               (1 << 13)
+
+/* Used by CM_COREAON_IO_SRCOMP_CLKCTRL, CM_WKUPAON_IO_SRCOMP_CLKCTRL */
+#define OMAP54XX_CLKEN_SRCOMP_FCLK_SHIFT                                8
+#define OMAP54XX_CLKEN_SRCOMP_FCLK_WIDTH                                0x1
+#define OMAP54XX_CLKEN_SRCOMP_FCLK_MASK                                 (1 << 8)
+
+/*
+ * Used by CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
+ * CM_ABE_TIMER8_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
+ * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
+ * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL
+ */
+#define OMAP54XX_CLKSEL_SHIFT                                           24
+#define OMAP54XX_CLKSEL_WIDTH                                           0x1
+#define OMAP54XX_CLKSEL_MASK                                            (1 << 24)
+
+/*
+ * Renamed from CLKSEL Used by CM_CLKSEL_ABE_DSS_SYS, CM_CLKSEL_ABE_PLL_REF,
+ * CM_CLKSEL_USB_60MHZ, CM_CLKSEL_WKUPAON
+ */
+#define OMAP54XX_CLKSEL_0_0_SHIFT                                       0
+#define OMAP54XX_CLKSEL_0_0_WIDTH                                       0x1
+#define OMAP54XX_CLKSEL_0_0_MASK                                        (1 << 0)
+
+/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
+#define OMAP54XX_CLKSEL_0_1_SHIFT                                       0
+#define OMAP54XX_CLKSEL_0_1_WIDTH                                       0x2
+#define OMAP54XX_CLKSEL_0_1_MASK                                        (0x3 << 0)
+
+/* Renamed from CLKSEL Used by CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL */
+#define OMAP54XX_CLKSEL_24_25_SHIFT                                     24
+#define OMAP54XX_CLKSEL_24_25_WIDTH                                     0x2
+#define OMAP54XX_CLKSEL_24_25_MASK                                      (0x3 << 24)
+
+/* Used by CM_MPU_MPU_CLKCTRL */
+#define OMAP54XX_CLKSEL_ABE_DIV_MODE_SHIFT                              26
+#define OMAP54XX_CLKSEL_ABE_DIV_MODE_WIDTH                              0x1
+#define OMAP54XX_CLKSEL_ABE_DIV_MODE_MASK                               (1 << 26)
+
+/* Used by CM_ABE_AESS_CLKCTRL */
+#define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT                                 24
+#define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH                                 0x1
+#define OMAP54XX_CLKSEL_AESS_FCLK_MASK                                  (1 << 24)
+
+/* Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL */
+#define OMAP54XX_CLKSEL_DIV_SHIFT                                       25
+#define OMAP54XX_CLKSEL_DIV_WIDTH                                       0x1
+#define OMAP54XX_CLKSEL_DIV_MASK                                        (1 << 25)
+
+/* Used by CM_MPU_MPU_CLKCTRL */
+#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_SHIFT                             24
+#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_WIDTH                             0x2
+#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_MASK                              (0x3 << 24)
+
+/* Used by CM_CAM_FDIF_CLKCTRL */
+#define OMAP54XX_CLKSEL_FCLK_SHIFT                                      24
+#define OMAP54XX_CLKSEL_FCLK_WIDTH                                      0x1
+#define OMAP54XX_CLKSEL_FCLK_MASK                                       (1 << 24)
+
+/* Used by CM_GPU_GPU_CLKCTRL */
+#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT                             24
+#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_MASK                              (1 << 24)
+
+/* Used by CM_GPU_GPU_CLKCTRL */
+#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT                              25
+#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH                              0x1
+#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_MASK                               (1 << 25)
+
+/* Used by CM_GPU_GPU_CLKCTRL */
+#define OMAP54XX_CLKSEL_GPU_SYS_CLK_SHIFT                               26
+#define OMAP54XX_CLKSEL_GPU_SYS_CLK_WIDTH                               0x1
+#define OMAP54XX_CLKSEL_GPU_SYS_CLK_MASK                                (1 << 26)
+
+/*
+ * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL,
+ * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL
+ */
+#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT                           26
+#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH                           0x2
+#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_MASK                            (0x3 << 26)
+
+/* Used by CM_CLKSEL_CORE */
+#define OMAP54XX_CLKSEL_L3_SHIFT                                        4
+#define OMAP54XX_CLKSEL_L3_WIDTH                                        0x1
+#define OMAP54XX_CLKSEL_L3_MASK                                         (1 << 4)
+
+/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
+#define OMAP54XX_CLKSEL_L3_1_1_SHIFT                                    1
+#define OMAP54XX_CLKSEL_L3_1_1_WIDTH                                    0x1
+#define OMAP54XX_CLKSEL_L3_1_1_MASK                                     (1 << 1)
+
+/* Used by CM_CLKSEL_CORE */
+#define OMAP54XX_CLKSEL_L4_SHIFT                                        8
+#define OMAP54XX_CLKSEL_L4_WIDTH                                        0x1
+#define OMAP54XX_CLKSEL_L4_MASK                                         (1 << 8)
+
+/* Used by CM_EMIF_EMIF1_CLKCTRL */
+#define OMAP54XX_CLKSEL_LL_SHIFT                                        24
+#define OMAP54XX_CLKSEL_LL_WIDTH                                        0x1
+#define OMAP54XX_CLKSEL_LL_MASK                                         (1 << 24)
+
+/* Used by CM_CLKSEL_ABE */
+#define OMAP54XX_CLKSEL_OPP_SHIFT                                       0
+#define OMAP54XX_CLKSEL_OPP_WIDTH                                       0x2
+#define OMAP54XX_CLKSEL_OPP_MASK                                        (0x3 << 0)
+
+/* Renamed from CLKSEL_OPP Used by CM_L3INIT_UNIPRO2_CLKCTRL */
+#define OMAP54XX_CLKSEL_OPP_24_24_SHIFT                                 24
+#define OMAP54XX_CLKSEL_OPP_24_24_WIDTH                                 0x1
+#define OMAP54XX_CLKSEL_OPP_24_24_MASK                                  (1 << 24)
+
+/*
+ * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL,
+ * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL
+ */
+#define OMAP54XX_CLKSEL_SOURCE_SHIFT                                    24
+#define OMAP54XX_CLKSEL_SOURCE_WIDTH                                    0x2
+#define OMAP54XX_CLKSEL_SOURCE_MASK                                     (0x3 << 24)
+
+/*
+ * Renamed from CLKSEL_SOURCE Used by CM_L3INIT_MMC1_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL
+ */
+#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT                        24
+#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH                        0x1
+#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_MASK                         (1 << 24)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_CLKSEL_UTMI_P1_SHIFT                                   24
+#define OMAP54XX_CLKSEL_UTMI_P1_WIDTH                                   0x1
+#define OMAP54XX_CLKSEL_UTMI_P1_MASK                                    (1 << 24)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_CLKSEL_UTMI_P2_SHIFT                                   25
+#define OMAP54XX_CLKSEL_UTMI_P2_WIDTH                                   0x1
+#define OMAP54XX_CLKSEL_UTMI_P2_MASK                                    (1 << 25)
+
+/*
+ * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER,
+ * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER,
+ * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
+ * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE,
+ * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE, CM_DIV_M2_DPLL_ABE,
+ * CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER,
+ * CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, CM_DIV_M2_DPLL_USB,
+ * CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER
+ */
+#define OMAP54XX_CLKST_SHIFT                                            9
+#define OMAP54XX_CLKST_WIDTH                                            0x1
+#define OMAP54XX_CLKST_MASK                                             (1 << 9)
+
+/*
+ * Used by CM_ABE_CLKSTCTRL, CM_C2C_CLKSTCTRL, CM_CAM_CLKSTCTRL,
+ * CM_COREAON_CLKSTCTRL, CM_CUSTEFUSE_CLKSTCTRL, CM_DMA_CLKSTCTRL,
+ * CM_DSP_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_EMIF_CLKSTCTRL, CM_EMU_CLKSTCTRL,
+ * CM_GPU_CLKSTCTRL, CM_IPU_CLKSTCTRL, CM_IVA_CLKSTCTRL, CM_L3INIT_CLKSTCTRL,
+ * CM_L3INSTR_CLKSTCTRL, CM_L3MAIN1_CLKSTCTRL, CM_L3MAIN2_CLKSTCTRL,
+ * CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL,
+ * CM_MIPIEXT_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_WKUPAON_CLKSTCTRL
+ */
+#define OMAP54XX_CLKTRCTRL_SHIFT                                        0
+#define OMAP54XX_CLKTRCTRL_WIDTH                                        0x2
+#define OMAP54XX_CLKTRCTRL_MASK                                         (0x3 << 0)
+
+/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER */
+#define OMAP54XX_CLKX2ST_SHIFT                                          11
+#define OMAP54XX_CLKX2ST_WIDTH                                          0x1
+#define OMAP54XX_CLKX2ST_MASK                                           (1 << 11)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_COREAON_DYNDEP_SHIFT                                   16
+#define OMAP54XX_COREAON_DYNDEP_WIDTH                                   0x1
+#define OMAP54XX_COREAON_DYNDEP_MASK                                    (1 << 16)
+
+/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_COREAON_STATDEP_SHIFT                                  16
+#define OMAP54XX_COREAON_STATDEP_WIDTH                                  0x1
+#define OMAP54XX_COREAON_STATDEP_MASK                                   (1 << 16)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_CUSTEFUSE_DYNDEP_SHIFT                                 17
+#define OMAP54XX_CUSTEFUSE_DYNDEP_WIDTH                                 0x1
+#define OMAP54XX_CUSTEFUSE_DYNDEP_MASK                                  (1 << 17)
+
+/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_CUSTEFUSE_STATDEP_SHIFT                                17
+#define OMAP54XX_CUSTEFUSE_STATDEP_WIDTH                                0x1
+#define OMAP54XX_CUSTEFUSE_STATDEP_MASK                                 (1 << 17)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define OMAP54XX_CUSTOM_SHIFT                                           6
+#define OMAP54XX_CUSTOM_WIDTH                                           0x2
+#define OMAP54XX_CUSTOM_MASK                                            (0x3 << 6)
+
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1,
+ * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
+ */
+#define OMAP54XX_DCC_EN_SHIFT                                           22
+#define OMAP54XX_DCC_EN_WIDTH                                           0x1
+#define OMAP54XX_DCC_EN_MASK                                            (1 << 22)
+
+/*
+ * Used by CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS,
+ * CM_CORE_AON_DEBUG_DSS_FD_TRANS, CM_CORE_AON_DEBUG_EMIF_FD_TRANS,
+ * CM_CORE_AON_DEBUG_L4SEC_FD_TRANS
+ */
+#define OMAP54XX_CM_DEBUG_OUT_SHIFT                                     0
+#define OMAP54XX_CM_DEBUG_OUT_WIDTH                                     0xd
+#define OMAP54XX_CM_DEBUG_OUT_MASK                                      (0x1fff << 0)
+
+/*
+ * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS,
+ * CM_CORE_AON_DEBUG_L3INIT_FD_TRANS, CM_CORE_AON_DEBUG_L4PER_FD_TRANS
+ */
+#define OMAP54XX_DEBUG_OUT_0_31_SHIFT                                   0
+#define OMAP54XX_DEBUG_OUT_0_31_WIDTH                                   0x20
+#define OMAP54XX_DEBUG_OUT_0_31_MASK                                    (0xffffffff << 0)
+
+/*
+ * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_C2C_FD_TRANS,
+ * CM_CORE_AON_DEBUG_COREAON_FD_TRANS, CM_CORE_AON_DEBUG_L4CFG_FD_TRANS
+ */
+#define OMAP54XX_DEBUG_OUT_0_8_SHIFT                                    0
+#define OMAP54XX_DEBUG_OUT_0_8_WIDTH                                    0x9
+#define OMAP54XX_DEBUG_OUT_0_8_MASK                                     (0x1ff << 0)
+
+/*
+ * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS,
+ * CM_CORE_AON_DEBUG_DMA_FD_TRANS, CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS
+ */
+#define OMAP54XX_DEBUG_OUT_0_4_SHIFT                                    0
+#define OMAP54XX_DEBUG_OUT_0_4_WIDTH                                    0x5
+#define OMAP54XX_DEBUG_OUT_0_4_MASK                                     (0x1f << 0)
+
+/*
+ * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_DSP_FD_TRANS,
+ * CM_CORE_AON_DEBUG_IPU_FD_TRANS, CM_CORE_AON_DEBUG_MPU_FD_TRANS
+ */
+#define OMAP54XX_DEBUG_OUT_0_5_SHIFT                                    0
+#define OMAP54XX_DEBUG_OUT_0_5_WIDTH                                    0x6
+#define OMAP54XX_DEBUG_OUT_0_5_MASK                                     (0x3f << 0)
+
+/*
+ * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CAM_FD_TRANS,
+ * CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS
+ */
+#define OMAP54XX_DEBUG_OUT_0_10_SHIFT                                   0
+#define OMAP54XX_DEBUG_OUT_0_10_WIDTH                                   0xb
+#define OMAP54XX_DEBUG_OUT_0_10_MASK                                    (0x7ff << 0)
+
+/*
+ * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_IVA_FD_TRANS,
+ * CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS
+ */
+#define OMAP54XX_DEBUG_OUT_0_6_SHIFT                                    0
+#define OMAP54XX_DEBUG_OUT_0_6_WIDTH                                    0x7
+#define OMAP54XX_DEBUG_OUT_0_6_MASK                                     (0x7f << 0)
+
+/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS2 */
+#define OMAP54XX_DEBUG_OUT_0_19_SHIFT                                   0
+#define OMAP54XX_DEBUG_OUT_0_19_WIDTH                                   0x14
+#define OMAP54XX_DEBUG_OUT_0_19_MASK                                    (0xfffff << 0)
+
+/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_GPU_FD_TRANS */
+#define OMAP54XX_DEBUG_OUT_0_9_SHIFT                                    0
+#define OMAP54XX_DEBUG_OUT_0_9_WIDTH                                    0xa
+#define OMAP54XX_DEBUG_OUT_0_9_MASK                                     (0x3ff << 0)
+
+/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2 */
+#define OMAP54XX_DEBUG_OUT_0_26_SHIFT                                   0
+#define OMAP54XX_DEBUG_OUT_0_26_WIDTH                                   0x1b
+#define OMAP54XX_DEBUG_OUT_0_26_MASK                                    (0x7ffffff << 0)
+
+/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS */
+#define OMAP54XX_DEBUG_OUT_0_13_SHIFT                                   0
+#define OMAP54XX_DEBUG_OUT_0_13_WIDTH                                   0xe
+#define OMAP54XX_DEBUG_OUT_0_13_MASK                                    (0x3fff << 0)
+
+/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L4PER_FD_TRANS2 */
+#define OMAP54XX_DEBUG_OUT_0_21_SHIFT                                   0
+#define OMAP54XX_DEBUG_OUT_0_21_WIDTH                                   0x16
+#define OMAP54XX_DEBUG_OUT_0_21_MASK                                    (0x3fffff << 0)
+
+/*
+ * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
+ * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
+ * CM_SSC_DELTAMSTEP_DPLL_PER
+ */
+#define OMAP54XX_DELTAMSTEP_SHIFT                                       0
+#define OMAP54XX_DELTAMSTEP_WIDTH                                       0x14
+#define OMAP54XX_DELTAMSTEP_MASK                                        (0xfffff << 0)
+
+/*
+ * Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_UNIPRO1,
+ * CM_SSC_DELTAMSTEP_DPLL_UNIPRO2, CM_SSC_DELTAMSTEP_DPLL_USB
+ */
+#define OMAP54XX_DELTAMSTEP_0_20_SHIFT                                  0
+#define OMAP54XX_DELTAMSTEP_0_20_WIDTH                                  0x15
+#define OMAP54XX_DELTAMSTEP_0_20_MASK                                   (0x1fffff << 0)
+
+/*
+ * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER,
+ * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER,
+ * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
+ * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE,
+ * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE
+ */
+#define OMAP54XX_DIVHS_SHIFT                                            0
+#define OMAP54XX_DIVHS_WIDTH                                            0x6
+#define OMAP54XX_DIVHS_MASK                                             (0x3f << 0)
+
+/*
+ * Renamed from DIVHS Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M3_DPLL_ABE,
+ * CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER
+ */
+#define OMAP54XX_DIVHS_0_4_SHIFT                                        0
+#define OMAP54XX_DIVHS_0_4_WIDTH                                        0x5
+#define OMAP54XX_DIVHS_0_4_MASK                                         (0x1f << 0)
+
+/*
+ * Renamed from DIVHS Used by CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2,
+ * CM_DIV_M2_DPLL_USB
+ */
+#define OMAP54XX_DIVHS_0_6_SHIFT                                        0
+#define OMAP54XX_DIVHS_0_6_WIDTH                                        0x7
+#define OMAP54XX_DIVHS_0_6_MASK                                         (0x7f << 0)
+
+/* Used by CM_DLL_CTRL */
+#define OMAP54XX_DLL_OVERRIDE_SHIFT                                     0
+#define OMAP54XX_DLL_OVERRIDE_WIDTH                                     0x1
+#define OMAP54XX_DLL_OVERRIDE_MASK                                      (1 << 0)
+
+/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP54XX_DLL_OVERRIDE_2_2_SHIFT                                 2
+#define OMAP54XX_DLL_OVERRIDE_2_2_WIDTH                                 0x1
+#define OMAP54XX_DLL_OVERRIDE_2_2_MASK                                  (1 << 2)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP54XX_DLL_RESET_SHIFT                                        3
+#define OMAP54XX_DLL_RESET_WIDTH                                        0x1
+#define OMAP54XX_DLL_RESET_MASK                                         (1 << 3)
+
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1,
+ * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
+ */
+#define OMAP54XX_DPLL_BYP_CLKSEL_SHIFT                                  23
+#define OMAP54XX_DPLL_BYP_CLKSEL_WIDTH                                  0x1
+#define OMAP54XX_DPLL_BYP_CLKSEL_MASK                                   (1 << 23)
+
+/* Used by CM_CLKSEL_DPLL_CORE */
+#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_SHIFT                            20
+#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_WIDTH                            0x1
+#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_MASK                             (1 << 20)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP54XX_DPLL_CORE_DPLL_EN_SHIFT                                8
+#define OMAP54XX_DPLL_CORE_DPLL_EN_WIDTH                                0x3
+#define OMAP54XX_DPLL_CORE_DPLL_EN_MASK                                 (0x7 << 8)
+
+/* Used by CM_SHADOW_FREQ_CONFIG2 */
+#define OMAP54XX_DPLL_CORE_H12_DIV_SHIFT                                2
+#define OMAP54XX_DPLL_CORE_H12_DIV_WIDTH                                0x6
+#define OMAP54XX_DPLL_CORE_H12_DIV_MASK                                 (0x3f << 2)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP54XX_DPLL_CORE_M2_DIV_SHIFT                                 11
+#define OMAP54XX_DPLL_CORE_M2_DIV_WIDTH                                 0x5
+#define OMAP54XX_DPLL_CORE_M2_DIV_MASK                                  (0x1f << 11)
+
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER
+ */
+#define OMAP54XX_DPLL_DIV_SHIFT                                         0
+#define OMAP54XX_DPLL_DIV_WIDTH                                         0x7
+#define OMAP54XX_DPLL_DIV_MASK                                          (0x7f << 0)
+
+/*
+ * Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_UNIPRO1,
+ * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
+ */
+#define OMAP54XX_DPLL_DIV_0_7_SHIFT                                     0
+#define OMAP54XX_DPLL_DIV_0_7_WIDTH                                     0x8
+#define OMAP54XX_DPLL_DIV_0_7_MASK                                      (0xff << 0)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define OMAP54XX_DPLL_DRIFTGUARD_EN_SHIFT                               8
+#define OMAP54XX_DPLL_DRIFTGUARD_EN_WIDTH                               0x1
+#define OMAP54XX_DPLL_DRIFTGUARD_EN_MASK                                (1 << 8)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
+ * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
+ */
+#define OMAP54XX_DPLL_EN_SHIFT                                          0
+#define OMAP54XX_DPLL_EN_WIDTH                                          0x3
+#define OMAP54XX_DPLL_EN_MASK                                           (0x7 << 0)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define OMAP54XX_DPLL_LPMODE_EN_SHIFT                                   10
+#define OMAP54XX_DPLL_LPMODE_EN_WIDTH                                   0x1
+#define OMAP54XX_DPLL_LPMODE_EN_MASK                                    (1 << 10)
+
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER
+ */
+#define OMAP54XX_DPLL_MULT_SHIFT                                        8
+#define OMAP54XX_DPLL_MULT_WIDTH                                        0xb
+#define OMAP54XX_DPLL_MULT_MASK                                         (0x7ff << 8)
+
+/*
+ * Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_UNIPRO1,
+ * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
+ */
+#define OMAP54XX_DPLL_MULT_UNIPRO1_SHIFT                                8
+#define OMAP54XX_DPLL_MULT_UNIPRO1_WIDTH                                0xc
+#define OMAP54XX_DPLL_MULT_UNIPRO1_MASK                                 (0xfff << 8)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define OMAP54XX_DPLL_REGM4XEN_SHIFT                                    11
+#define OMAP54XX_DPLL_REGM4XEN_WIDTH                                    0x1
+#define OMAP54XX_DPLL_REGM4XEN_MASK                                     (1 << 11)
+
+/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */
+#define OMAP54XX_DPLL_SD_DIV_SHIFT                                      24
+#define OMAP54XX_DPLL_SD_DIV_WIDTH                                      0x8
+#define OMAP54XX_DPLL_SD_DIV_MASK                                       (0xff << 24)
+
+/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */
+#define OMAP54XX_DPLL_SELFREQDCO_SHIFT                                  21
+#define OMAP54XX_DPLL_SELFREQDCO_WIDTH                                  0x1
+#define OMAP54XX_DPLL_SELFREQDCO_MASK                                   (1 << 21)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
+ * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
+ */
+#define OMAP54XX_DPLL_SSC_ACK_SHIFT                                     13
+#define OMAP54XX_DPLL_SSC_ACK_WIDTH                                     0x1
+#define OMAP54XX_DPLL_SSC_ACK_MASK                                      (1 << 13)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
+ * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
+ */
+#define OMAP54XX_DPLL_SSC_DOWNSPREAD_SHIFT                              14
+#define OMAP54XX_DPLL_SSC_DOWNSPREAD_WIDTH                              0x1
+#define OMAP54XX_DPLL_SSC_DOWNSPREAD_MASK                               (1 << 14)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
+ * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
+ */
+#define OMAP54XX_DPLL_SSC_EN_SHIFT                                      12
+#define OMAP54XX_DPLL_SSC_EN_WIDTH                                      0x1
+#define OMAP54XX_DPLL_SSC_EN_MASK                                       (1 << 12)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_DSP_DYNDEP_SHIFT                                       1
+#define OMAP54XX_DSP_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_DSP_DYNDEP_MASK                                        (1 << 1)
+
+/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_DSP_STATDEP_SHIFT                                      1
+#define OMAP54XX_DSP_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_DSP_STATDEP_MASK                                       (1 << 1)
+
+/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+#define OMAP54XX_DSS_DYNDEP_SHIFT                                       8
+#define OMAP54XX_DSS_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_DSS_DYNDEP_MASK                                        (1 << 8)
+
+/* Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_DSS_STATDEP_SHIFT                                      8
+#define OMAP54XX_DSS_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_DSS_STATDEP_MASK                                       (1 << 8)
+
+/*
+ * Used by CM_C2C_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
+ * CM_MIPIEXT_DYNAMICDEP, CM_MPU_DYNAMICDEP
+ */
+#define OMAP54XX_EMIF_DYNDEP_SHIFT                                      4
+#define OMAP54XX_EMIF_DYNDEP_WIDTH                                      0x1
+#define OMAP54XX_EMIF_DYNDEP_MASK                                       (1 << 4)
+
+/*
+ * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
+ * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
+ * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
+ * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_EMIF_STATDEP_SHIFT                                     4
+#define OMAP54XX_EMIF_STATDEP_WIDTH                                     0x1
+#define OMAP54XX_EMIF_STATDEP_MASK                                      (1 << 4)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP54XX_FREQ_UPDATE_SHIFT                                      0
+#define OMAP54XX_FREQ_UPDATE_WIDTH                                      0x1
+#define OMAP54XX_FREQ_UPDATE_MASK                                       (1 << 0)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define OMAP54XX_FUNC_SHIFT                                             16
+#define OMAP54XX_FUNC_WIDTH                                             0xc
+#define OMAP54XX_FUNC_MASK                                              (0xfff << 16)
+
+/* Used by CM_SHADOW_FREQ_CONFIG2 */
+#define OMAP54XX_GPMC_FREQ_UPDATE_SHIFT                                 0
+#define OMAP54XX_GPMC_FREQ_UPDATE_WIDTH                                 0x1
+#define OMAP54XX_GPMC_FREQ_UPDATE_MASK                                  (1 << 0)
+
+/* Used by CM_L3MAIN2_DYNAMICDEP */
+#define OMAP54XX_GPU_DYNDEP_SHIFT                                       10
+#define OMAP54XX_GPU_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_GPU_DYNDEP_MASK                                        (1 << 10)
+
+/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_GPU_STATDEP_SHIFT                                      10
+#define OMAP54XX_GPU_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_GPU_STATDEP_MASK                                       (1 << 10)
+
+/*
+ * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL,
+ * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL,
+ * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL,
+ * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
+ * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL,
+ * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL,
+ * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
+ * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
+ * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
+ * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
+ * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL,
+ * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL,
+ * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
+ * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL,
+ * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL,
+ * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL,
+ * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL,
+ * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL,
+ * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
+ * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
+ * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
+ * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL,
+ * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL,
+ * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL,
+ * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
+ * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
+ * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
+ * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
+ * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
+ * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL,
+ * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
+ * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
+ * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
+ * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
+ * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
+ * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
+ * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL,
+ * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL,
+ * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
+ * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
+ * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
+ * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
+ * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL
+ */
+#define OMAP54XX_IDLEST_SHIFT                                           16
+#define OMAP54XX_IDLEST_WIDTH                                           0x2
+#define OMAP54XX_IDLEST_MASK                                            (0x3 << 16)
+
+/* Used by CM_L3MAIN2_DYNAMICDEP */
+#define OMAP54XX_IPU_DYNDEP_SHIFT                                       0
+#define OMAP54XX_IPU_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_IPU_DYNDEP_MASK                                        (1 << 0)
+
+/* Used by CM_DMA_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_IPU_STATDEP_SHIFT                                      0
+#define OMAP54XX_IPU_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_IPU_STATDEP_MASK                                       (1 << 0)
+
+/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP */
+#define OMAP54XX_IVA_DYNDEP_SHIFT                                       2
+#define OMAP54XX_IVA_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_IVA_DYNDEP_MASK                                        (1 << 2)
+
+/*
+ * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
+ * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_IVA_STATDEP_SHIFT                                      2
+#define OMAP54XX_IVA_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_IVA_STATDEP_MASK                                       (1 << 2)
+
+/* Used by CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+#define OMAP54XX_L3INIT_DYNDEP_SHIFT                                    7
+#define OMAP54XX_L3INIT_DYNDEP_WIDTH                                    0x1
+#define OMAP54XX_L3INIT_DYNDEP_MASK                                     (1 << 7)
+
+/*
+ * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
+ * CM_IPU_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_L3INIT_STATDEP_SHIFT                                   7
+#define OMAP54XX_L3INIT_STATDEP_WIDTH                                   0x1
+#define OMAP54XX_L3INIT_STATDEP_MASK                                    (1 << 7)
+
+/*
+ * Used by CM_DSP_DYNAMICDEP, CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
+ * CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP
+ */
+#define OMAP54XX_L3MAIN1_DYNDEP_SHIFT                                   5
+#define OMAP54XX_L3MAIN1_DYNDEP_WIDTH                                   0x1
+#define OMAP54XX_L3MAIN1_DYNDEP_MASK                                    (1 << 5)
+
+/*
+ * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
+ * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
+ * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
+ * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_L3MAIN1_STATDEP_SHIFT                                  5
+#define OMAP54XX_L3MAIN1_STATDEP_WIDTH                                  0x1
+#define OMAP54XX_L3MAIN1_STATDEP_MASK                                   (1 << 5)
+
+/*
+ * Used by CM_C2C_DYNAMICDEP, CM_CAM_DYNAMICDEP, CM_DMA_DYNAMICDEP,
+ * CM_DSS_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GPU_DYNAMICDEP, CM_IPU_DYNAMICDEP,
+ * CM_IVA_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP
+ */
+#define OMAP54XX_L3MAIN2_DYNDEP_SHIFT                                   6
+#define OMAP54XX_L3MAIN2_DYNDEP_WIDTH                                   0x1
+#define OMAP54XX_L3MAIN2_DYNDEP_MASK                                    (1 << 6)
+
+/*
+ * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
+ * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
+ * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
+ * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_L3MAIN2_STATDEP_SHIFT                                  6
+#define OMAP54XX_L3MAIN2_STATDEP_WIDTH                                  0x1
+#define OMAP54XX_L3MAIN2_STATDEP_MASK                                   (1 << 6)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define OMAP54XX_L4CFG_DYNDEP_SHIFT                                     12
+#define OMAP54XX_L4CFG_DYNDEP_WIDTH                                     0x1
+#define OMAP54XX_L4CFG_DYNDEP_MASK                                      (1 << 12)
+
+/*
+ * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
+ * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_L4CFG_STATDEP_SHIFT                                    12
+#define OMAP54XX_L4CFG_STATDEP_WIDTH                                    0x1
+#define OMAP54XX_L4CFG_STATDEP_MASK                                     (1 << 12)
+
+/* Used by CM_L3MAIN2_DYNAMICDEP */
+#define OMAP54XX_L4PER_DYNDEP_SHIFT                                     13
+#define OMAP54XX_L4PER_DYNDEP_WIDTH                                     0x1
+#define OMAP54XX_L4PER_DYNDEP_MASK                                      (1 << 13)
+
+/*
+ * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
+ * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
+ * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_L4PER_STATDEP_SHIFT                                    13
+#define OMAP54XX_L4PER_STATDEP_WIDTH                                    0x1
+#define OMAP54XX_L4PER_STATDEP_MASK                                     (1 << 13)
+
+/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+#define OMAP54XX_L4SEC_DYNDEP_SHIFT                                     14
+#define OMAP54XX_L4SEC_DYNDEP_WIDTH                                     0x1
+#define OMAP54XX_L4SEC_DYNDEP_MASK                                      (1 << 14)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_MPU_STATICDEP
+ */
+#define OMAP54XX_L4SEC_STATDEP_SHIFT                                    14
+#define OMAP54XX_L4SEC_STATDEP_WIDTH                                    0x1
+#define OMAP54XX_L4SEC_STATDEP_MASK                                     (1 << 14)
+
+/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_MIPIEXT_DYNDEP_SHIFT                                   21
+#define OMAP54XX_MIPIEXT_DYNDEP_WIDTH                                   0x1
+#define OMAP54XX_MIPIEXT_DYNDEP_MASK                                    (1 << 21)
+
+/* Used by CM_MPU_STATICDEP */
+#define OMAP54XX_MIPIEXT_STATDEP_SHIFT                                  21
+#define OMAP54XX_MIPIEXT_STATDEP_WIDTH                                  0x1
+#define OMAP54XX_MIPIEXT_STATDEP_MASK                                   (1 << 21)
+
+/*
+ * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
+ * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1,
+ * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB
+ */
+#define OMAP54XX_MODFREQDIV_EXPONENT_SHIFT                              8
+#define OMAP54XX_MODFREQDIV_EXPONENT_WIDTH                              0x3
+#define OMAP54XX_MODFREQDIV_EXPONENT_MASK                               (0x7 << 8)
+
+/*
+ * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
+ * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1,
+ * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB
+ */
+#define OMAP54XX_MODFREQDIV_MANTISSA_SHIFT                              0
+#define OMAP54XX_MODFREQDIV_MANTISSA_WIDTH                              0x7
+#define OMAP54XX_MODFREQDIV_MANTISSA_MASK                               (0x7f << 0)
+
+/*
+ * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL,
+ * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL,
+ * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL,
+ * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
+ * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL,
+ * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL,
+ * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
+ * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
+ * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
+ * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
+ * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL,
+ * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL,
+ * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
+ * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL,
+ * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL,
+ * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL,
+ * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL,
+ * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL,
+ * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
+ * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
+ * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
+ * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL,
+ * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL,
+ * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL,
+ * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
+ * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
+ * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
+ * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
+ * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
+ * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL,
+ * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
+ * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
+ * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
+ * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
+ * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
+ * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
+ * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL,
+ * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL,
+ * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
+ * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
+ * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
+ * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
+ * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL
+ */
+#define OMAP54XX_MODULEMODE_SHIFT                                       0
+#define OMAP54XX_MODULEMODE_WIDTH                                       0x2
+#define OMAP54XX_MODULEMODE_MASK                                        (0x3 << 0)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_MPU_DYNDEP_SHIFT                                       19
+#define OMAP54XX_MPU_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_MPU_DYNDEP_MASK                                        (1 << 19)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT                              11
+#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_WIDTH                              0x1
+#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_MASK                               (1 << 11)
+
+/* Renamed from OPTFCLKEN_32KHZ_CLK Used by CM_L3INIT_MMC1_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT                          8
+#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_WIDTH                          0x1
+#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_MASK                           (1 << 8)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT                              9
+#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_WIDTH                              0x1
+#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_MASK                               (1 << 9)
+
+/* Used by CM_COREAON_USB_PHY_CORE_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT                                 8
+#define OMAP54XX_OPTFCLKEN_CLK32K_WIDTH                                 0x1
+#define OMAP54XX_OPTFCLKEN_CLK32K_MASK                                  (1 << 8)
+
+/* Used by CM_CAM_ISS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT                                8
+#define OMAP54XX_OPTFCLKEN_CTRLCLK_WIDTH                                0x1
+#define OMAP54XX_OPTFCLKEN_CTRLCLK_MASK                                 (1 << 8)
+
+/*
+ * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
+ * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
+ * CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL
+ */
+#define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT                                  8
+#define OMAP54XX_OPTFCLKEN_DBCLK_WIDTH                                  0x1
+#define OMAP54XX_OPTFCLKEN_DBCLK_MASK                                   (1 << 8)
+
+/* Used by CM_EMIF_EMIF_DLL_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_DLL_CLK_SHIFT                                8
+#define OMAP54XX_OPTFCLKEN_DLL_CLK_WIDTH                                0x1
+#define OMAP54XX_OPTFCLKEN_DLL_CLK_MASK                                 (1 << 8)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT                                 8
+#define OMAP54XX_OPTFCLKEN_DSSCLK_WIDTH                                 0x1
+#define OMAP54XX_OPTFCLKEN_DSSCLK_MASK                                  (1 << 8)
+
+/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_FCLK0_SHIFT                                  8
+#define OMAP54XX_OPTFCLKEN_FCLK0_WIDTH                                  0x1
+#define OMAP54XX_OPTFCLKEN_FCLK0_MASK                                   (1 << 8)
+
+/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_FCLK1_SHIFT                                  9
+#define OMAP54XX_OPTFCLKEN_FCLK1_WIDTH                                  0x1
+#define OMAP54XX_OPTFCLKEN_FCLK1_MASK                                   (1 << 9)
+
+/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_FCLK2_SHIFT                                  10
+#define OMAP54XX_OPTFCLKEN_FCLK2_WIDTH                                  0x1
+#define OMAP54XX_OPTFCLKEN_FCLK2_MASK                                   (1 << 10)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_SHIFT                            15
+#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_MASK                             (1 << 15)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT                        13
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH                        0x1
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_MASK                         (1 << 13)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT                        14
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH                        0x1
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_MASK                         (1 << 14)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT                        7
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_WIDTH                        0x1
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_MASK                         (1 << 7)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                         11
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH                         0x1
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_MASK                          (1 << 11)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                         12
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH                         0x1
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_MASK                          (1 << 12)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT                         6
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_WIDTH                         0x1
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_MASK                          (1 << 6)
+
+/* Used by CM_L3INIT_USB_OTG_SS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT                             8
+#define OMAP54XX_OPTFCLKEN_REFCLK960M_WIDTH                             0x1
+#define OMAP54XX_OPTFCLKEN_REFCLK960M_MASK                              (1 << 8)
+
+/* Used by CM_L3INIT_SATA_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT                                8
+#define OMAP54XX_OPTFCLKEN_REF_CLK_WIDTH                                0x1
+#define OMAP54XX_OPTFCLKEN_REF_CLK_MASK                                 (1 << 8)
+
+/* Used by CM_WKUPAON_SCRM_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_SCRM_CORE_SHIFT                              8
+#define OMAP54XX_OPTFCLKEN_SCRM_CORE_WIDTH                              0x1
+#define OMAP54XX_OPTFCLKEN_SCRM_CORE_MASK                               (1 << 8)
+
+/* Used by CM_WKUPAON_SCRM_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_SCRM_PER_SHIFT                               9
+#define OMAP54XX_OPTFCLKEN_SCRM_PER_WIDTH                               0x1
+#define OMAP54XX_OPTFCLKEN_SCRM_PER_MASK                                (1 << 9)
+
+/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT                            11
+#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_MASK                             (1 << 11)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT                                10
+#define OMAP54XX_OPTFCLKEN_SYS_CLK_WIDTH                                0x1
+#define OMAP54XX_OPTFCLKEN_SYS_CLK_MASK                                 (1 << 10)
+
+/* Used by CM_MIPIEXT_LLI_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT                              8
+#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_WIDTH                              0x1
+#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_MASK                               (1 << 8)
+
+/* Used by CM_MIPIEXT_LLI_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT                           9
+#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_WIDTH                           0x1
+#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_MASK                            (1 << 9)
+
+/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT                            8
+#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_MASK                             (1 << 8)
+
+/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT                            9
+#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_MASK                             (1 << 9)
+
+/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT                            10
+#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_MASK                             (1 << 10)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT                            8
+#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_MASK                             (1 << 8)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT                            9
+#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_MASK                             (1 << 9)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT                            10
+#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_MASK                             (1 << 10)
+
+/* Used by CM_CORE_AON_DEBUG_OUT, CM_CORE_DEBUG_OUT */
+#define OMAP54XX_OUTPUT_SHIFT                                           0
+#define OMAP54XX_OUTPUT_WIDTH                                           0x20
+#define OMAP54XX_OUTPUT_MASK                                            (0xffffffff << 0)
+
+/* Used by CM_CLKSEL_ABE */
+#define OMAP54XX_PAD_CLKS_GATE_SHIFT                                    8
+#define OMAP54XX_PAD_CLKS_GATE_WIDTH                                    0x1
+#define OMAP54XX_PAD_CLKS_GATE_MASK                                     (1 << 8)
+
+/* Used by CM_RESTORE_ST */
+#define OMAP54XX_PHASE1_COMPLETED_SHIFT                                 0
+#define OMAP54XX_PHASE1_COMPLETED_WIDTH                                 0x1
+#define OMAP54XX_PHASE1_COMPLETED_MASK                                  (1 << 0)
+
+/* Used by CM_RESTORE_ST */
+#define OMAP54XX_PHASE2A_COMPLETED_SHIFT                                1
+#define OMAP54XX_PHASE2A_COMPLETED_WIDTH                                0x1
+#define OMAP54XX_PHASE2A_COMPLETED_MASK                                 (1 << 1)
+
+/* Used by CM_RESTORE_ST */
+#define OMAP54XX_PHASE2B_COMPLETED_SHIFT                                2
+#define OMAP54XX_PHASE2B_COMPLETED_WIDTH                                0x1
+#define OMAP54XX_PHASE2B_COMPLETED_MASK                                 (1 << 2)
+
+/* Used by CM_DYN_DEP_PRESCAL */
+#define OMAP54XX_PRESCAL_SHIFT                                          0
+#define OMAP54XX_PRESCAL_WIDTH                                          0x6
+#define OMAP54XX_PRESCAL_MASK                                           (0x3f << 0)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define OMAP54XX_R_RTL_SHIFT                                            11
+#define OMAP54XX_R_RTL_WIDTH                                            0x5
+#define OMAP54XX_R_RTL_MASK                                             (0x1f << 11)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_TLL_HS_CLKCTRL */
+#define OMAP54XX_SAR_MODE_SHIFT                                         4
+#define OMAP54XX_SAR_MODE_WIDTH                                         0x1
+#define OMAP54XX_SAR_MODE_MASK                                          (1 << 4)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define OMAP54XX_SCHEME_SHIFT                                           30
+#define OMAP54XX_SCHEME_WIDTH                                           0x2
+#define OMAP54XX_SCHEME_MASK                                            (0x3 << 30)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_SDMA_DYNDEP_SHIFT                                      11
+#define OMAP54XX_SDMA_DYNDEP_WIDTH                                      0x1
+#define OMAP54XX_SDMA_DYNDEP_MASK                                       (1 << 11)
+
+/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_SDMA_STATDEP_SHIFT                                     11
+#define OMAP54XX_SDMA_STATDEP_WIDTH                                     0x1
+#define OMAP54XX_SDMA_STATDEP_MASK                                      (1 << 11)
+
+/* Used by CM_CORE_AON_DEBUG_CFG */
+#define OMAP54XX_SEL0_SHIFT                                             0
+#define OMAP54XX_SEL0_WIDTH                                             0x7
+#define OMAP54XX_SEL0_MASK                                              (0x7f << 0)
+
+/* Renamed from SEL0 Used by CM_CORE_DEBUG_CFG */
+#define OMAP54XX_SEL0_0_7_SHIFT                                         0
+#define OMAP54XX_SEL0_0_7_WIDTH                                         0x8
+#define OMAP54XX_SEL0_0_7_MASK                                          (0xff << 0)
+
+/* Used by CM_CORE_AON_DEBUG_CFG */
+#define OMAP54XX_SEL1_SHIFT                                             8
+#define OMAP54XX_SEL1_WIDTH                                             0x7
+#define OMAP54XX_SEL1_MASK                                              (0x7f << 8)
+
+/* Renamed from SEL1 Used by CM_CORE_DEBUG_CFG */
+#define OMAP54XX_SEL1_CORE_DEBUG_CFG_SHIFT                              8
+#define OMAP54XX_SEL1_CORE_DEBUG_CFG_WIDTH                              0x8
+#define OMAP54XX_SEL1_CORE_DEBUG_CFG_MASK                               (0xff << 8)
+
+/* Used by CM_CORE_AON_DEBUG_CFG */
+#define OMAP54XX_SEL2_SHIFT                                             16
+#define OMAP54XX_SEL2_WIDTH                                             0x7
+#define OMAP54XX_SEL2_MASK                                              (0x7f << 16)
+
+/* Renamed from SEL2 Used by CM_CORE_DEBUG_CFG */
+#define OMAP54XX_SEL2_CORE_DEBUG_CFG_SHIFT                              16
+#define OMAP54XX_SEL2_CORE_DEBUG_CFG_WIDTH                              0x8
+#define OMAP54XX_SEL2_CORE_DEBUG_CFG_MASK                               (0xff << 16)
+
+/* Used by CM_CORE_AON_DEBUG_CFG */
+#define OMAP54XX_SEL3_SHIFT                                             24
+#define OMAP54XX_SEL3_WIDTH                                             0x7
+#define OMAP54XX_SEL3_MASK                                              (0x7f << 24)
+
+/* Renamed from SEL3 Used by CM_CORE_DEBUG_CFG */
+#define OMAP54XX_SEL3_CORE_DEBUG_CFG_SHIFT                              24
+#define OMAP54XX_SEL3_CORE_DEBUG_CFG_WIDTH                              0x8
+#define OMAP54XX_SEL3_CORE_DEBUG_CFG_MASK                               (0xff << 24)
+
+/* Used by CM_CLKSEL_ABE */
+#define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT                                10
+#define OMAP54XX_SLIMBUS1_CLK_GATE_WIDTH                                0x1
+#define OMAP54XX_SLIMBUS1_CLK_GATE_MASK                                 (1 << 10)
+
+/*
+ * Used by CM_ABE_AESS_CLKCTRL, CM_C2C_C2C_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
+ * CM_CAM_ISS_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, CM_DSP_DSP_CLKCTRL,
+ * CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
+ * CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, CM_IVA_IVA_CLKCTRL,
+ * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,
+ * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_SATA_CLKCTRL,
+ * CM_L3INIT_UNIPRO2_CLKCTRL, CM_L3INIT_USB_HOST_HS_CLKCTRL,
+ * CM_L3INIT_USB_OTG_SS_CLKCTRL, CM_L4SEC_DMA_CRYPTO_CLKCTRL,
+ * CM_MIPIEXT_LLI_CLKCTRL, CM_MPU_MPU_CLKCTRL
+ */
+#define OMAP54XX_STBYST_SHIFT                                           18
+#define OMAP54XX_STBYST_WIDTH                                           0x1
+#define OMAP54XX_STBYST_MASK                                            (1 << 18)
+
+/*
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
+ * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
+ * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
+ */
+#define OMAP54XX_ST_DPLL_CLK_SHIFT                                      0
+#define OMAP54XX_ST_DPLL_CLK_WIDTH                                      0x1
+#define OMAP54XX_ST_DPLL_CLK_MASK                                       (1 << 0)
+
+/*
+ * Used by CM_CLKDCOLDO_DPLL_UNIPRO1, CM_CLKDCOLDO_DPLL_UNIPRO2,
+ * CM_CLKDCOLDO_DPLL_USB
+ */
+#define OMAP54XX_ST_DPLL_CLKDCOLDO_SHIFT                                9
+#define OMAP54XX_ST_DPLL_CLKDCOLDO_WIDTH                                0x1
+#define OMAP54XX_ST_DPLL_CLKDCOLDO_MASK                                 (1 << 9)
+
+/*
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
+ * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
+ * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
+ */
+#define OMAP54XX_ST_DPLL_INIT_SHIFT                                     4
+#define OMAP54XX_ST_DPLL_INIT_WIDTH                                     0x1
+#define OMAP54XX_ST_DPLL_INIT_MASK                                      (1 << 4)
+
+/*
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
+ * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
+ * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
+ */
+#define OMAP54XX_ST_DPLL_MODE_SHIFT                                     1
+#define OMAP54XX_ST_DPLL_MODE_WIDTH                                     0x3
+#define OMAP54XX_ST_DPLL_MODE_MASK                                      (0x7 << 1)
+
+/* Used by CM_CLKSEL_SYS */
+#define OMAP54XX_SYS_CLKSEL_SHIFT                                       0
+#define OMAP54XX_SYS_CLKSEL_WIDTH                                       0x3
+#define OMAP54XX_SYS_CLKSEL_MASK                                        (0x7 << 0)
+
+/*
+ * Used by CM_C2C_DYNAMICDEP, CM_DSP_DYNAMICDEP, CM_EMU_DYNAMICDEP,
+ * CM_IPU_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP,
+ * CM_MPU_DYNAMICDEP
+ */
+#define OMAP54XX_WINDOWSIZE_SHIFT                                       24
+#define OMAP54XX_WINDOWSIZE_WIDTH                                       0x4
+#define OMAP54XX_WINDOWSIZE_MASK                                        (0xf << 24)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define OMAP54XX_WKUPAON_DYNDEP_SHIFT                                   15
+#define OMAP54XX_WKUPAON_DYNDEP_WIDTH                                   0x1
+#define OMAP54XX_WKUPAON_DYNDEP_MASK                                    (1 << 15)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_WKUPAON_STATDEP_SHIFT                                  15
+#define OMAP54XX_WKUPAON_STATDEP_WIDTH                                  0x1
+#define OMAP54XX_WKUPAON_STATDEP_MASK                                   (1 << 15)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define OMAP54XX_X_MAJOR_SHIFT                                          8
+#define OMAP54XX_X_MAJOR_WIDTH                                          0x3
+#define OMAP54XX_X_MAJOR_MASK                                           (0x7 << 8)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define OMAP54XX_Y_MINOR_SHIFT                                          0
+#define OMAP54XX_Y_MINOR_WIDTH                                          0x6
+#define OMAP54XX_Y_MINOR_MASK                                           (0x3f << 0)
+#endif
diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
index 1bc00dc4876c..5ae8fe39d6ee 100644
--- a/arch/arm/mach-omap2/cm1_44xx.h
+++ b/arch/arm/mach-omap2/cm1_44xx.h
@@ -25,6 +25,8 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
 
+#include "cm_44xx_54xx.h"
+
 /* CM1 base address */
 #define OMAP4430_CM1_BASE               0x4a004000
 
@@ -217,9 +219,4 @@
 #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET               0x0088
 #define OMAP4430_CM1_ABE_WDT3_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
 
-/* Function prototypes */
-extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-
 #endif
diff --git a/arch/arm/mach-omap2/cm1_54xx.h b/arch/arm/mach-omap2/cm1_54xx.h
new file mode 100644
index 000000000000..90b3348e6672
--- /dev/null
+++ b/arch/arm/mach-omap2/cm1_54xx.h
@@ -0,0 +1,213 @@
+/*
+ * OMAP54xx CM1 instance offset macros
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
+
+#include "cm_44xx_54xx.h"
+
+/* CM1 base address */
+#define OMAP54XX_CM_CORE_AON_BASE               0x4a004000
+
+#define OMAP54XX_CM_CORE_AON_REGADDR(inst, reg)                         \
+        OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE + (inst) + (reg))
+
+/* CM_CORE_AON instances */
+#define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST    0x0000
+#define OMAP54XX_CM_CORE_AON_CKGEN_INST         0x0100
+#define OMAP54XX_CM_CORE_AON_MPU_INST           0x0300
+#define OMAP54XX_CM_CORE_AON_DSP_INST           0x0400
+#define OMAP54XX_CM_CORE_AON_ABE_INST           0x0500
+#define OMAP54XX_CM_CORE_AON_RESTORE_INST       0x0e00
+#define OMAP54XX_CM_CORE_AON_INSTR_INST         0x0f00
+
+/* CM_CORE_AON clockdomain register offsets (from instance start) */
+#define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS     0x0000
+#define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS     0x0000
+#define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS     0x0000
+
+/* CM_CORE_AON */
+
+/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
+#define OMAP54XX_REVISION_CM_CORE_AON_OFFSET                    0x0000
+#define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET        0x0040
+#define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL               OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
+#define OMAP54XX_CM_CORE_AON_DEBUG_CFG_OFFSET                   0x0080
+#define OMAP54XX_CM_CORE_AON_DEBUG_OUT_OFFSET                   0x0084
+#define OMAP54XX_CM_CORE_AON_DEBUG_MPU_FD_TRANS_OFFSET          0x0090
+#define OMAP54XX_CM_CORE_AON_DEBUG_DSP_FD_TRANS_OFFSET          0x0094
+#define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS_OFFSET          0x0098
+#define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS2_OFFSET         0x009c
+#define OMAP54XX_CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS_OFFSET  0x00a0
+#define OMAP54XX_CM_CORE_AON_DEBUG_C2C_FD_TRANS_OFFSET          0x00a4
+#define OMAP54XX_CM_CORE_AON_DEBUG_CAM_FD_TRANS_OFFSET          0x00a8
+#define OMAP54XX_CM_CORE_AON_DEBUG_COREAON_FD_TRANS_OFFSET      0x00ac
+#define OMAP54XX_CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS_OFFSET    0x00b0
+#define OMAP54XX_CM_CORE_AON_DEBUG_DMA_FD_TRANS_OFFSET          0x00b4
+#define OMAP54XX_CM_CORE_AON_DEBUG_DSS_FD_TRANS_OFFSET          0x00b8
+#define OMAP54XX_CM_CORE_AON_DEBUG_EMIF_FD_TRANS_OFFSET         0x00bc
+#define OMAP54XX_CM_CORE_AON_DEBUG_GPU_FD_TRANS_OFFSET          0x00c0
+#define OMAP54XX_CM_CORE_AON_DEBUG_IPU_FD_TRANS_OFFSET          0x00c4
+#define OMAP54XX_CM_CORE_AON_DEBUG_IVA_FD_TRANS_OFFSET          0x00c8
+#define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS_OFFSET       0x00cc
+#define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2_OFFSET      0x00d0
+#define OMAP54XX_CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS_OFFSET      0x00d4
+#define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS_OFFSET      0x00d8
+#define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS_OFFSET      0x00dc
+#define OMAP54XX_CM_CORE_AON_DEBUG_L4CFG_FD_TRANS_OFFSET        0x00e0
+#define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS_OFFSET        0x00e4
+#define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS2_OFFSET       0x00e8
+#define OMAP54XX_CM_CORE_AON_DEBUG_L4SEC_FD_TRANS_OFFSET        0x00ec
+#define OMAP54XX_CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS_OFFSET      0x00f0
+
+/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
+#define OMAP54XX_CM_CLKSEL_CORE_OFFSET                          0x0000
+#define OMAP54XX_CM_CLKSEL_CORE                                 OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0000)
+#define OMAP54XX_CM_CLKSEL_ABE_OFFSET                           0x0008
+#define OMAP54XX_CM_CLKSEL_ABE                                  OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0008)
+#define OMAP54XX_CM_DLL_CTRL_OFFSET                             0x0010
+#define OMAP54XX_CM_CLKMODE_DPLL_CORE_OFFSET                    0x0020
+#define OMAP54XX_CM_CLKMODE_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0020)
+#define OMAP54XX_CM_IDLEST_DPLL_CORE_OFFSET                     0x0024
+#define OMAP54XX_CM_IDLEST_DPLL_CORE                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0024)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_CORE_OFFSET                   0x0028
+#define OMAP54XX_CM_AUTOIDLE_DPLL_CORE                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0028)
+#define OMAP54XX_CM_CLKSEL_DPLL_CORE_OFFSET                     0x002c
+#define OMAP54XX_CM_CLKSEL_DPLL_CORE                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x002c)
+#define OMAP54XX_CM_DIV_M2_DPLL_CORE_OFFSET                     0x0030
+#define OMAP54XX_CM_DIV_M2_DPLL_CORE                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0030)
+#define OMAP54XX_CM_DIV_M3_DPLL_CORE_OFFSET                     0x0034
+#define OMAP54XX_CM_DIV_M3_DPLL_CORE                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0034)
+#define OMAP54XX_CM_DIV_H11_DPLL_CORE_OFFSET                    0x0038
+#define OMAP54XX_CM_DIV_H11_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0038)
+#define OMAP54XX_CM_DIV_H12_DPLL_CORE_OFFSET                    0x003c
+#define OMAP54XX_CM_DIV_H12_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x003c)
+#define OMAP54XX_CM_DIV_H13_DPLL_CORE_OFFSET                    0x0040
+#define OMAP54XX_CM_DIV_H13_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0040)
+#define OMAP54XX_CM_DIV_H14_DPLL_CORE_OFFSET                    0x0044
+#define OMAP54XX_CM_DIV_H14_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0044)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET             0x0048
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET             0x004c
+#define OMAP54XX_CM_DIV_H21_DPLL_CORE_OFFSET                    0x0050
+#define OMAP54XX_CM_DIV_H21_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0050)
+#define OMAP54XX_CM_DIV_H22_DPLL_CORE_OFFSET                    0x0054
+#define OMAP54XX_CM_DIV_H22_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0054)
+#define OMAP54XX_CM_DIV_H23_DPLL_CORE_OFFSET                    0x0058
+#define OMAP54XX_CM_DIV_H23_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0058)
+#define OMAP54XX_CM_DIV_H24_DPLL_CORE_OFFSET                    0x005c
+#define OMAP54XX_CM_DIV_H24_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x005c)
+#define OMAP54XX_CM_CLKMODE_DPLL_MPU_OFFSET                     0x0060
+#define OMAP54XX_CM_CLKMODE_DPLL_MPU                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0060)
+#define OMAP54XX_CM_IDLEST_DPLL_MPU_OFFSET                      0x0064
+#define OMAP54XX_CM_IDLEST_DPLL_MPU                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0064)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_MPU_OFFSET                    0x0068
+#define OMAP54XX_CM_AUTOIDLE_DPLL_MPU                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0068)
+#define OMAP54XX_CM_CLKSEL_DPLL_MPU_OFFSET                      0x006c
+#define OMAP54XX_CM_CLKSEL_DPLL_MPU                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x006c)
+#define OMAP54XX_CM_DIV_M2_DPLL_MPU_OFFSET                      0x0070
+#define OMAP54XX_CM_DIV_M2_DPLL_MPU                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0070)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET              0x0088
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET              0x008c
+#define OMAP54XX_CM_BYPCLK_DPLL_MPU_OFFSET                      0x009c
+#define OMAP54XX_CM_BYPCLK_DPLL_MPU                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x009c)
+#define OMAP54XX_CM_CLKMODE_DPLL_IVA_OFFSET                     0x00a0
+#define OMAP54XX_CM_CLKMODE_DPLL_IVA                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
+#define OMAP54XX_CM_IDLEST_DPLL_IVA_OFFSET                      0x00a4
+#define OMAP54XX_CM_IDLEST_DPLL_IVA                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_IVA_OFFSET                    0x00a8
+#define OMAP54XX_CM_AUTOIDLE_DPLL_IVA                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
+#define OMAP54XX_CM_CLKSEL_DPLL_IVA_OFFSET                      0x00ac
+#define OMAP54XX_CM_CLKSEL_DPLL_IVA                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
+#define OMAP54XX_CM_DIV_H11_DPLL_IVA_OFFSET                     0x00b8
+#define OMAP54XX_CM_DIV_H11_DPLL_IVA                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00b8)
+#define OMAP54XX_CM_DIV_H12_DPLL_IVA_OFFSET                     0x00bc
+#define OMAP54XX_CM_DIV_H12_DPLL_IVA                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00bc)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET              0x00c8
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET              0x00cc
+#define OMAP54XX_CM_BYPCLK_DPLL_IVA_OFFSET                      0x00dc
+#define OMAP54XX_CM_BYPCLK_DPLL_IVA                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
+#define OMAP54XX_CM_CLKMODE_DPLL_ABE_OFFSET                     0x00e0
+#define OMAP54XX_CM_CLKMODE_DPLL_ABE                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
+#define OMAP54XX_CM_IDLEST_DPLL_ABE_OFFSET                      0x00e4
+#define OMAP54XX_CM_IDLEST_DPLL_ABE                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_ABE_OFFSET                    0x00e8
+#define OMAP54XX_CM_AUTOIDLE_DPLL_ABE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
+#define OMAP54XX_CM_CLKSEL_DPLL_ABE_OFFSET                      0x00ec
+#define OMAP54XX_CM_CLKSEL_DPLL_ABE                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
+#define OMAP54XX_CM_DIV_M2_DPLL_ABE_OFFSET                      0x00f0
+#define OMAP54XX_CM_DIV_M2_DPLL_ABE                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
+#define OMAP54XX_CM_DIV_M3_DPLL_ABE_OFFSET                      0x00f4
+#define OMAP54XX_CM_DIV_M3_DPLL_ABE                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET              0x0108
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET              0x010c
+#define OMAP54XX_CM_SHADOW_FREQ_CONFIG1_OFFSET                  0x0160
+#define OMAP54XX_CM_SHADOW_FREQ_CONFIG2_OFFSET                  0x0164
+#define OMAP54XX_CM_DYN_DEP_PRESCAL_OFFSET                      0x0170
+#define OMAP54XX_CM_RESTORE_ST_OFFSET                           0x0180
+
+/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
+#define OMAP54XX_CM_MPU_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_MPU_STATICDEP_OFFSET                        0x0004
+#define OMAP54XX_CM_MPU_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET                      0x0020
+#define OMAP54XX_CM_MPU_MPU_CLKCTRL                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0020)
+#define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET              0x0028
+#define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL                     OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0028)
+
+/* CM_CORE_AON.DSP_CM_CORE_AON register offsets */
+#define OMAP54XX_CM_DSP_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_DSP_STATICDEP_OFFSET                        0x0004
+#define OMAP54XX_CM_DSP_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET                      0x0020
+#define OMAP54XX_CM_DSP_DSP_CLKCTRL                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_DSP_INST, 0x0020)
+
+/* CM_CORE_AON.ABE_CM_CORE_AON register offsets */
+#define OMAP54XX_CM_ABE_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET                   0x0020
+#define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0020)
+#define OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET                     0x0028
+#define OMAP54XX_CM_ABE_AESS_CLKCTRL                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0028)
+#define OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET                    0x0030
+#define OMAP54XX_CM_ABE_MCPDM_CLKCTRL                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0030)
+#define OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET                     0x0038
+#define OMAP54XX_CM_ABE_DMIC_CLKCTRL                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0038)
+#define OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET                    0x0040
+#define OMAP54XX_CM_ABE_MCASP_CLKCTRL                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0040)
+#define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET                   0x0048
+#define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0048)
+#define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET                   0x0050
+#define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0050)
+#define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET                   0x0058
+#define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0058)
+#define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET                 0x0060
+#define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL                        OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0060)
+#define OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET                   0x0068
+#define OMAP54XX_CM_ABE_TIMER5_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0068)
+#define OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET                   0x0070
+#define OMAP54XX_CM_ABE_TIMER6_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0070)
+#define OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET                   0x0078
+#define OMAP54XX_CM_ABE_TIMER7_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0078)
+#define OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET                   0x0080
+#define OMAP54XX_CM_ABE_TIMER8_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0080)
+#define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL_OFFSET                0x0088
+#define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL                       OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0088)
+
+#endif
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
index b9de72da1a8e..ee5136d7cdda 100644
--- a/arch/arm/mach-omap2/cm2_44xx.h
+++ b/arch/arm/mach-omap2/cm2_44xx.h
@@ -25,6 +25,8 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
 
+#include "cm_44xx_54xx.h"
+
 /* CM2 base address */
 #define OMAP4430_CM2_BASE               0x4a008000
 
@@ -449,9 +451,4 @@
 #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET           0x0020
 #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
 
-/* Function prototypes */
-extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-
 #endif
diff --git a/arch/arm/mach-omap2/cm2_54xx.h b/arch/arm/mach-omap2/cm2_54xx.h
new file mode 100644
index 000000000000..2683231b299b
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2_54xx.h
@@ -0,0 +1,389 @@
+/*
+ * OMAP54xx CM2 instance offset macros
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
+
+#include "cm_44xx_54xx.h"
+
+/* CM2 base address */
+#define OMAP54XX_CM_CORE_BASE           0x4a008000
+
+#define OMAP54XX_CM_CORE_REGADDR(inst, reg)                             \
+        OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE + (inst) + (reg))
+
+/* CM_CORE instances */
+#define OMAP54XX_CM_CORE_OCP_SOCKET_INST        0x0000
+#define OMAP54XX_CM_CORE_CKGEN_INST             0x0100
+#define OMAP54XX_CM_CORE_COREAON_INST           0x0600
+#define OMAP54XX_CM_CORE_CORE_INST              0x0700
+#define OMAP54XX_CM_CORE_IVA_INST               0x1200
+#define OMAP54XX_CM_CORE_CAM_INST               0x1300
+#define OMAP54XX_CM_CORE_DSS_INST               0x1400
+#define OMAP54XX_CM_CORE_GPU_INST               0x1500
+#define OMAP54XX_CM_CORE_L3INIT_INST            0x1600
+#define OMAP54XX_CM_CORE_CUSTEFUSE_INST         0x1700
+#define OMAP54XX_CM_CORE_RESTORE_INST           0x1e00
+#define OMAP54XX_CM_CORE_INSTR_INST             0x1f00
+
+/* CM_CORE clockdomain register offsets (from instance start) */
+#define OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS         0x0000
+#define OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS            0x0000
+#define OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS            0x0100
+#define OMAP54XX_CM_CORE_CORE_IPU_CDOFFS                0x0200
+#define OMAP54XX_CM_CORE_CORE_DMA_CDOFFS                0x0300
+#define OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS               0x0400
+#define OMAP54XX_CM_CORE_CORE_C2C_CDOFFS                0x0500
+#define OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS              0x0600
+#define OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS            0x0700
+#define OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS            0x0800
+#define OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS              0x0900
+#define OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS              0x0a80
+#define OMAP54XX_CM_CORE_IVA_IVA_CDOFFS                 0x0000
+#define OMAP54XX_CM_CORE_CAM_CAM_CDOFFS                 0x0000
+#define OMAP54XX_CM_CORE_DSS_DSS_CDOFFS                 0x0000
+#define OMAP54XX_CM_CORE_GPU_GPU_CDOFFS                 0x0000
+#define OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS           0x0000
+#define OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS     0x0000
+
+/* CM_CORE */
+
+/* CM_CORE.OCP_SOCKET_CM_CORE register offsets */
+#define OMAP54XX_REVISION_CM_CORE_OFFSET                        0x0000
+#define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET            0x0040
+#define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_OCP_SOCKET_INST, 0x0040)
+#define OMAP54XX_CM_CORE_DEBUG_CFG_OFFSET                       0x0080
+#define OMAP54XX_CM_CORE_DEBUG_OUT_OFFSET                       0x0084
+
+/* CM_CORE.CKGEN_CM_CORE register offsets */
+#define OMAP54XX_CM_CLKSEL_USB_60MHZ_OFFSET                     0x0004
+#define OMAP54XX_CM_CLKSEL_USB_60MHZ                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0004)
+#define OMAP54XX_CM_CLKMODE_DPLL_PER_OFFSET                     0x0040
+#define OMAP54XX_CM_CLKMODE_DPLL_PER                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0040)
+#define OMAP54XX_CM_IDLEST_DPLL_PER_OFFSET                      0x0044
+#define OMAP54XX_CM_IDLEST_DPLL_PER                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0044)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_PER_OFFSET                    0x0048
+#define OMAP54XX_CM_AUTOIDLE_DPLL_PER                           OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0048)
+#define OMAP54XX_CM_CLKSEL_DPLL_PER_OFFSET                      0x004c
+#define OMAP54XX_CM_CLKSEL_DPLL_PER                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x004c)
+#define OMAP54XX_CM_DIV_M2_DPLL_PER_OFFSET                      0x0050
+#define OMAP54XX_CM_DIV_M2_DPLL_PER                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0050)
+#define OMAP54XX_CM_DIV_M3_DPLL_PER_OFFSET                      0x0054
+#define OMAP54XX_CM_DIV_M3_DPLL_PER                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0054)
+#define OMAP54XX_CM_DIV_H11_DPLL_PER_OFFSET                     0x0058
+#define OMAP54XX_CM_DIV_H11_DPLL_PER                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0058)
+#define OMAP54XX_CM_DIV_H12_DPLL_PER_OFFSET                     0x005c
+#define OMAP54XX_CM_DIV_H12_DPLL_PER                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x005c)
+#define OMAP54XX_CM_DIV_H13_DPLL_PER_OFFSET                     0x0060
+#define OMAP54XX_CM_DIV_H13_DPLL_PER                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0060)
+#define OMAP54XX_CM_DIV_H14_DPLL_PER_OFFSET                     0x0064
+#define OMAP54XX_CM_DIV_H14_DPLL_PER                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0064)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET              0x0068
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET              0x006c
+#define OMAP54XX_CM_CLKMODE_DPLL_USB_OFFSET                     0x0080
+#define OMAP54XX_CM_CLKMODE_DPLL_USB                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0080)
+#define OMAP54XX_CM_IDLEST_DPLL_USB_OFFSET                      0x0084
+#define OMAP54XX_CM_IDLEST_DPLL_USB                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0084)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_USB_OFFSET                    0x0088
+#define OMAP54XX_CM_AUTOIDLE_DPLL_USB                           OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0088)
+#define OMAP54XX_CM_CLKSEL_DPLL_USB_OFFSET                      0x008c
+#define OMAP54XX_CM_CLKSEL_DPLL_USB                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x008c)
+#define OMAP54XX_CM_DIV_M2_DPLL_USB_OFFSET                      0x0090
+#define OMAP54XX_CM_DIV_M2_DPLL_USB                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0090)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET              0x00a8
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET              0x00ac
+#define OMAP54XX_CM_CLKDCOLDO_DPLL_USB_OFFSET                   0x00b4
+#define OMAP54XX_CM_CLKDCOLDO_DPLL_USB                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00b4)
+#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2_OFFSET                 0x00c0
+#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c0)
+#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2_OFFSET                  0x00c4
+#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c4)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2_OFFSET                0x00c8
+#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c8)
+#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2_OFFSET                  0x00cc
+#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00cc)
+#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2_OFFSET                  0x00d0
+#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00d0)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO2_OFFSET          0x00e8
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO2_OFFSET          0x00ec
+#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2_OFFSET               0x00f4
+#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00f4)
+#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1_OFFSET                 0x0100
+#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0100)
+#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1_OFFSET                  0x0104
+#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0104)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1_OFFSET                0x0108
+#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0108)
+#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1_OFFSET                  0x010c
+#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x010c)
+#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1_OFFSET                  0x0110
+#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0110)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO1_OFFSET          0x0128
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO1_OFFSET          0x012c
+#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1_OFFSET               0x0134
+#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0134)
+
+/* CM_CORE.COREAON_CM_CORE register offsets */
+#define OMAP54XX_CM_COREAON_CLKSTCTRL_OFFSET                    0x0000
+#define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET      0x0028
+#define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0028)
+#define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL_OFFSET       0x0030
+#define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL              OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0030)
+#define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET     0x0038
+#define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0038)
+#define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL_OFFSET         0x0040
+#define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL                OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0040)
+#define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET            0x0050
+#define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0050)
+
+/* CM_CORE.CORE_CM_CORE register offsets */
+#define OMAP54XX_CM_L3MAIN1_CLKSTCTRL_OFFSET                    0x0000
+#define OMAP54XX_CM_L3MAIN1_DYNAMICDEP_OFFSET                   0x0008
+#define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET            0x0020
+#define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0020)
+#define OMAP54XX_CM_L3MAIN2_CLKSTCTRL_OFFSET                    0x0100
+#define OMAP54XX_CM_L3MAIN2_DYNAMICDEP_OFFSET                   0x0108
+#define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET            0x0120
+#define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0120)
+#define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL_OFFSET                 0x0128
+#define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0128)
+#define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL_OFFSET             0x0130
+#define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL                    OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0130)
+#define OMAP54XX_CM_IPU_CLKSTCTRL_OFFSET                        0x0200
+#define OMAP54XX_CM_IPU_STATICDEP_OFFSET                        0x0204
+#define OMAP54XX_CM_IPU_DYNAMICDEP_OFFSET                       0x0208
+#define OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET                      0x0220
+#define OMAP54XX_CM_IPU_IPU_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0220)
+#define OMAP54XX_CM_DMA_CLKSTCTRL_OFFSET                        0x0300
+#define OMAP54XX_CM_DMA_STATICDEP_OFFSET                        0x0304
+#define OMAP54XX_CM_DMA_DYNAMICDEP_OFFSET                       0x0308
+#define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET               0x0320
+#define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0320)
+#define OMAP54XX_CM_EMIF_CLKSTCTRL_OFFSET                       0x0400
+#define OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET                     0x0420
+#define OMAP54XX_CM_EMIF_DMM_CLKCTRL                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0420)
+#define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET             0x0428
+#define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL                    OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0428)
+#define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET                   0x0430
+#define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0430)
+#define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET                   0x0438
+#define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0438)
+#define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET                0x0440
+#define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0440)
+#define OMAP54XX_CM_C2C_CLKSTCTRL_OFFSET                        0x0500
+#define OMAP54XX_CM_C2C_STATICDEP_OFFSET                        0x0504
+#define OMAP54XX_CM_C2C_DYNAMICDEP_OFFSET                       0x0508
+#define OMAP54XX_CM_C2C_C2C_CLKCTRL_OFFSET                      0x0520
+#define OMAP54XX_CM_C2C_C2C_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0520)
+#define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL_OFFSET                0x0528
+#define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0528)
+#define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL_OFFSET               0x0530
+#define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0530)
+#define OMAP54XX_CM_L4CFG_CLKSTCTRL_OFFSET                      0x0600
+#define OMAP54XX_CM_L4CFG_DYNAMICDEP_OFFSET                     0x0608
+#define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET                 0x0620
+#define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0620)
+#define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET               0x0628
+#define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0628)
+#define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET                0x0630
+#define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0630)
+#define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET                0x0638
+#define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0638)
+#define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET               0x0640
+#define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0640)
+#define OMAP54XX_CM_L3INSTR_CLKSTCTRL_OFFSET                    0x0700
+#define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET            0x0720
+#define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0720)
+#define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET             0x0728
+#define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL                    OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0728)
+#define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET           0x0740
+#define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL                  OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0740)
+#define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET            0x0748
+#define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0748)
+#define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET  0x0750
+#define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0750)
+#define OMAP54XX_CM_MIPIEXT_CLKSTCTRL_OFFSET                    0x0800
+#define OMAP54XX_CM_MIPIEXT_STATICDEP_OFFSET                    0x0804
+#define OMAP54XX_CM_MIPIEXT_DYNAMICDEP_OFFSET                   0x0808
+#define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL_OFFSET                  0x0820
+#define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0820)
+#define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL_OFFSET           0x0828
+#define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL                  OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0828)
+#define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL_OFFSET                 0x0830
+#define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0830)
+#define OMAP54XX_CM_L4PER_CLKSTCTRL_OFFSET                      0x0900
+#define OMAP54XX_CM_L4PER_DYNAMICDEP_OFFSET                     0x0908
+#define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET                0x0928
+#define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0928)
+#define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET                0x0930
+#define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0930)
+#define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET                 0x0938
+#define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0938)
+#define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET                 0x0940
+#define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0940)
+#define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET                 0x0948
+#define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0948)
+#define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET                 0x0950
+#define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0950)
+#define OMAP54XX_CM_L4PER_ELM_CLKCTRL_OFFSET                    0x0958
+#define OMAP54XX_CM_L4PER_ELM_CLKCTRL                           OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0958)
+#define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET                  0x0960
+#define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0960)
+#define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET                  0x0968
+#define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0968)
+#define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET                  0x0970
+#define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0970)
+#define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET                  0x0978
+#define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0978)
+#define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET                  0x0980
+#define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0980)
+#define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET                  0x0988
+#define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0988)
+#define OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET                   0x09a0
+#define OMAP54XX_CM_L4PER_I2C1_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a0)
+#define OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET                   0x09a8
+#define OMAP54XX_CM_L4PER_I2C2_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a8)
+#define OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET                   0x09b0
+#define OMAP54XX_CM_L4PER_I2C3_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b0)
+#define OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET                   0x09b8
+#define OMAP54XX_CM_L4PER_I2C4_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b8)
+#define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET                 0x09c0
+#define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09c0)
+#define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET                 0x09f0
+#define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f0)
+#define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET                 0x09f8
+#define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f8)
+#define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET                 0x0a00
+#define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a00)
+#define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET                 0x0a08
+#define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a08)
+#define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET                  0x0a10
+#define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a10)
+#define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET                  0x0a18
+#define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a18)
+#define OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET                   0x0a20
+#define OMAP54XX_CM_L4PER_MMC3_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a20)
+#define OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET                   0x0a28
+#define OMAP54XX_CM_L4PER_MMC4_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a28)
+#define OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET                  0x0a40
+#define OMAP54XX_CM_L4PER_UART1_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a40)
+#define OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET                  0x0a48
+#define OMAP54XX_CM_L4PER_UART2_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a48)
+#define OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET                  0x0a50
+#define OMAP54XX_CM_L4PER_UART3_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a50)
+#define OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET                  0x0a58
+#define OMAP54XX_CM_L4PER_UART4_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a58)
+#define OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET                   0x0a60
+#define OMAP54XX_CM_L4PER_MMC5_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a60)
+#define OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET                   0x0a68
+#define OMAP54XX_CM_L4PER_I2C5_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a68)
+#define OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET                  0x0a70
+#define OMAP54XX_CM_L4PER_UART5_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a70)
+#define OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET                  0x0a78
+#define OMAP54XX_CM_L4PER_UART6_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a78)
+#define OMAP54XX_CM_L4SEC_CLKSTCTRL_OFFSET                      0x0a80
+#define OMAP54XX_CM_L4SEC_STATICDEP_OFFSET                      0x0a84
+#define OMAP54XX_CM_L4SEC_DYNAMICDEP_OFFSET                     0x0a88
+#define OMAP54XX_CM_L4SEC_AES1_CLKCTRL_OFFSET                   0x0aa0
+#define OMAP54XX_CM_L4SEC_AES1_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa0)
+#define OMAP54XX_CM_L4SEC_AES2_CLKCTRL_OFFSET                   0x0aa8
+#define OMAP54XX_CM_L4SEC_AES2_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa8)
+#define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET                0x0ab0
+#define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab0)
+#define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET                   0x0ab8
+#define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab8)
+#define OMAP54XX_CM_L4SEC_RNG_CLKCTRL_OFFSET                    0x0ac0
+#define OMAP54XX_CM_L4SEC_RNG_CLKCTRL                           OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac0)
+#define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL_OFFSET                0x0ac8
+#define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac8)
+#define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET             0x0ad8
+#define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL                    OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ad8)
+
+/* CM_CORE.IVA_CM_CORE register offsets */
+#define OMAP54XX_CM_IVA_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_IVA_STATICDEP_OFFSET                        0x0004
+#define OMAP54XX_CM_IVA_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_IVA_IVA_CLKCTRL_OFFSET                      0x0020
+#define OMAP54XX_CM_IVA_IVA_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0020)
+#define OMAP54XX_CM_IVA_SL2_CLKCTRL_OFFSET                      0x0028
+#define OMAP54XX_CM_IVA_SL2_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0028)
+
+/* CM_CORE.CAM_CM_CORE register offsets */
+#define OMAP54XX_CM_CAM_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_CAM_STATICDEP_OFFSET                        0x0004
+#define OMAP54XX_CM_CAM_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_CAM_ISS_CLKCTRL_OFFSET                      0x0020
+#define OMAP54XX_CM_CAM_ISS_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0020)
+#define OMAP54XX_CM_CAM_FDIF_CLKCTRL_OFFSET                     0x0028
+#define OMAP54XX_CM_CAM_FDIF_CLKCTRL                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0028)
+#define OMAP54XX_CM_CAM_CAL_CLKCTRL_OFFSET                      0x0030
+#define OMAP54XX_CM_CAM_CAL_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0030)
+
+/* CM_CORE.DSS_CM_CORE register offsets */
+#define OMAP54XX_CM_DSS_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_DSS_STATICDEP_OFFSET                        0x0004
+#define OMAP54XX_CM_DSS_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET                      0x0020
+#define OMAP54XX_CM_DSS_DSS_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0020)
+#define OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET                     0x0030
+#define OMAP54XX_CM_DSS_BB2D_CLKCTRL                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0030)
+
+/* CM_CORE.GPU_CM_CORE register offsets */
+#define OMAP54XX_CM_GPU_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_GPU_STATICDEP_OFFSET                        0x0004
+#define OMAP54XX_CM_GPU_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_GPU_GPU_CLKCTRL_OFFSET                      0x0020
+#define OMAP54XX_CM_GPU_GPU_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_GPU_INST, 0x0020)
+
+/* CM_CORE.L3INIT_CM_CORE register offsets */
+#define OMAP54XX_CM_L3INIT_CLKSTCTRL_OFFSET                     0x0000
+#define OMAP54XX_CM_L3INIT_STATICDEP_OFFSET                     0x0004
+#define OMAP54XX_CM_L3INIT_DYNAMICDEP_OFFSET                    0x0008
+#define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET                  0x0028
+#define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0028)
+#define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET                  0x0030
+#define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0030)
+#define OMAP54XX_CM_L3INIT_HSI_CLKCTRL_OFFSET                   0x0038
+#define OMAP54XX_CM_L3INIT_HSI_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0038)
+#define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL_OFFSET               0x0040
+#define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0040)
+#define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL_OFFSET          0x0048
+#define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL                 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0048)
+#define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET           0x0058
+#define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL                  OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0058)
+#define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET            0x0068
+#define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0068)
+#define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET        0x0078
+#define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL               OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0078)
+#define OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET                  0x0088
+#define OMAP54XX_CM_L3INIT_SATA_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0088)
+#define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET              0x00e0
+#define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL                     OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e0)
+#define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET              0x00e8
+#define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL                     OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e8)
+#define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET            0x00f0
+#define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00f0)
+
+/* CM_CORE.CUSTEFUSE_CM_CORE register offsets */
+#define OMAP54XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET                  0x0000
+#define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET    0x0020
+#define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL           OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CUSTEFUSE_INST, 0x0020)
+
+#endif
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 64f4bafe7bd9..9d1f4fcdebbb 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -383,7 +383,7 @@ extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
 extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs);
 extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs);
 
-#ifdef CONFIG_SOC_AM33XX
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
                                         u16 clkctrl_offs);
 extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
diff --git a/arch/arm/mach-omap2/cm_44xx_54xx.h b/arch/arm/mach-omap2/cm_44xx_54xx.h
new file mode 100644
index 000000000000..cbb211690321
--- /dev/null
+++ b/arch/arm/mach-omap2/cm_44xx_54xx.h
@@ -0,0 +1,36 @@
+/*
+ * OMAP44xx and OMAP54xx CM1/CM2 function prototypes
+ *
+ * Copyright (C) 2009-2013 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_44XX_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_44XX_55XX_H
+
+/* CM1 Function prototypes */
+extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+/* CM2 Function prototypes */
+extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+#endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index d555cf2459e1..72cab3f4f16d 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -96,6 +96,7 @@ void am33xx_init_early(void);
 void am35xx_init_early(void);
 void ti81xx_init_early(void);
 void am33xx_init_early(void);
+void am43xx_init_early(void);
 void omap4430_init_early(void);
 void omap5_init_early(void);
 void omap3_init_late(void);     /* Do not use this one */
@@ -237,8 +238,8 @@ extern void omap_do_wfi(void);
 
 #ifdef CONFIG_SMP
 /* Needed for secondary core boot */
-extern void omap_secondary_startup(void);
-extern void omap_secondary_startup_4460(void);
+extern void omap4_secondary_startup(void);
+extern void omap4460_secondary_startup(void);
 extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
 extern void omap_auxcoreboot_addr(u32 cpu_addr);
 extern u32 omap_read_auxcoreboot0(void);
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index e6c328128a0a..f7d7c2ef1b40 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -358,6 +358,18 @@
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH            0x2
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK             (0x3 << 22)
 
+/* AM33XX PWMSS Control register */
+#define AM33XX_PWMSS_TBCLK_CLKCTRL                      0x664
+
+/* AM33XX  PWMSS Control bitfields */
+#define AM33XX_PWMSS0_TBCLKEN_SHIFT                     0
+#define AM33XX_PWMSS1_TBCLKEN_SHIFT                     1
+#define AM33XX_PWMSS2_TBCLKEN_SHIFT                     2
+
+/* DEV Feature register to identify AM33XX features */
+#define AM33XX_DEV_FEATURE              0x604
+#define AM33XX_SGX_MASK                 BIT(29)
+
 /* CONTROL OMAP STATUS register to identify OMAP3 features */
 #define OMAP3_CONTROL_OMAP_STATUS       0x044c
 
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 1272c41d4749..7335eb2bf3fa 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -55,7 +55,7 @@ int omap_type(void)
 
         if (cpu_is_omap24xx()) {
                 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
-        } else if (soc_is_am33xx()) {
+        } else if (soc_is_am33xx() || soc_is_am43xx()) {
                 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
         } else if (cpu_is_omap34xx()) {
                 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
@@ -209,6 +209,8 @@ static void __init omap3_cpuinfo(void)
                 cpu_name = "TI816X";
         } else if (soc_is_am335x()) {
                 cpu_name =  "AM335X";
+        } else if (soc_is_am437x()) {
+                cpu_name =  "AM437x";
         } else if (cpu_is_ti814x()) {
                 cpu_name = "TI814X";
         } else if (omap3_has_iva() && omap3_has_sgx()) {
@@ -302,6 +304,19 @@ void __init ti81xx_check_features(void)
         omap3_cpuinfo();
 }
 
+void __init am33xx_check_features(void)
+{
+        u32 status;
+
+        omap_features = OMAP3_HAS_NEON;
+
+        status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
+        if (status & AM33XX_SGX_MASK)
+                omap_features |= OMAP3_HAS_SGX;
+
+        omap3_cpuinfo();
+}
+
 void __init omap3xxx_check_revision(void)
 {
         const char *cpu_rev;
@@ -405,11 +420,18 @@ void __init omap3xxx_check_revision(void)
                         cpu_rev = "1.0";
                         break;
                 case 1:
-                /* FALLTHROUGH */
-                default:
                         omap_revision = TI8168_REV_ES1_1;
                         cpu_rev = "1.1";
                         break;
+                case 2:
+                        omap_revision = TI8168_REV_ES2_0;
+                        cpu_rev = "2.0";
+                        break;
+                case 3:
+                        /* FALLTHROUGH */
+                default:
+                        omap_revision = TI8168_REV_ES2_1;
+                        cpu_rev = "2.1";
                 }
                 break;
         case 0xb944:
@@ -430,6 +452,10 @@ void __init omap3xxx_check_revision(void)
                         break;
                 }
                 break;
+        case 0xb98c:
+                omap_revision = AM437X_REV_ES1_0;
+                cpu_rev = "1.0";
+                break;
         case 0xb8f2:
                 switch (rev) {
                 case 0:
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 09abf99e9e57..fe3253a100e7 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -202,7 +202,7 @@ static struct map_desc omapti81xx_io_desc[] __initdata = {
 };
 #endif
 
-#ifdef CONFIG_SOC_AM33XX
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 static struct map_desc omapam33xx_io_desc[] __initdata = {
         {
                 .virtual        = L4_34XX_VIRT,
@@ -318,7 +318,7 @@ void __init ti81xx_map_io(void)
 }
 #endif
 
-#ifdef CONFIG_SOC_AM33XX
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 void __init am33xx_map_io(void)
 {
         iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
@@ -576,8 +576,7 @@ void __init am33xx_init_early(void)
         omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
         omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
         omap3xxx_check_revision();
-        ti81xx_check_features();
-        am33xx_voltagedomains_init();
+        am33xx_check_features();
         am33xx_powerdomains_init();
         am33xx_clockdomains_init();
         am33xx_hwmod_init();
@@ -586,6 +585,19 @@ void __init am33xx_init_early(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_AM43XX
+void __init am43xx_init_early(void)
+{
+        omap2_set_globals_tap(AM335X_CLASS,
+                              AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
+        omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
+                                  NULL);
+        omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
+        omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
+        omap3xxx_check_revision();
+}
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 void __init omap4430_init_early(void)
 {
@@ -631,7 +643,13 @@ void __init omap5_init_early(void)
         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
         omap_prm_base_init();
         omap_cm_base_init();
+        omap44xx_prm_init();
         omap5xxx_check_revision();
+        omap54xx_voltagedomains_init();
+        omap54xx_powerdomains_init();
+        omap54xx_clockdomains_init();
+        omap54xx_hwmod_init();
+        omap_hwmod_init_postsetup();
 }
 #endif
 
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 0ea09faf327b..4ea308114165 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -49,7 +49,7 @@ END(omap5_secondary_startup)
  * The primary core will update this flag using a hardware
  * register AuxCoreBoot0.
  */
-ENTRY(omap_secondary_startup)
+ENTRY(omap4_secondary_startup)
 hold:   ldr     r12,=0x103
         dsb
         smc     #0                      @ read from AuxCoreBoot0
@@ -64,9 +64,9 @@ hold:	ldr	r12,=0x103
          * should now contain the SVC stack for this core
          */
         b       secondary_startup
-ENDPROC(omap_secondary_startup)
+ENDPROC(omap4_secondary_startup)
 
-ENTRY(omap_secondary_startup_4460)
+ENTRY(omap4460_secondary_startup)
 hold_2: ldr     r12,=0x103
         dsb
         smc     #0                      @ read from AuxCoreBoot0
@@ -101,4 +101,4 @@ hold_2:	ldr	r12,=0x103
          * should now contain the SVC stack for this core
          */
         b       secondary_startup
-ENDPROC(omap_secondary_startup_4460)
+ENDPROC(omap4460_secondary_startup)
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index e80327b6c81f..f993a4188701 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -71,10 +71,43 @@ struct omap4_cpu_pm_info {
         void (*secondary_startup)(void);
 };
 
+/**
+ * struct cpu_pm_ops - CPU pm operations
+ * @finish_suspend:     CPU suspend finisher function pointer
+ * @resume:             CPU resume function pointer
+ * @scu_prepare:        CPU Snoop Control program function pointer
+ *
+ * Structure holds functions pointer for CPU low power operations like
+ * suspend, resume and scu programming.
+ */
+struct cpu_pm_ops {
+        int (*finish_suspend)(unsigned long cpu_state);
+        void (*resume)(void);
+        void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
+};
+
 static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
 static struct powerdomain *mpuss_pd;
 static void __iomem *sar_base;
 
+static int default_finish_suspend(unsigned long cpu_state)
+{
+        omap_do_wfi();
+        return 0;
+}
+
+static void dummy_cpu_resume(void)
+{}
+
+static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state)
+{}
+
+struct cpu_pm_ops omap_pm_ops = {
+        .finish_suspend         = default_finish_suspend,
+        .resume                 = dummy_cpu_resume,
+        .scu_prepare            = dummy_scu_prepare,
+};
+
 /*
  * Program the wakeup routine address for the CPU0 and CPU1
  * used for OFF or DORMANT wakeup.
@@ -158,11 +191,12 @@ static void save_l2x0_context(void)
 {
         u32 val;
         void __iomem *l2x0_base = omap4_get_l2cache_base();
-
-        val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
-        __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
-        val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
-        __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
+        if (l2x0_base) {
+                val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
+                __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
+                val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
+                __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
+        }
 }
 #else
 static void save_l2x0_context(void)
@@ -225,14 +259,17 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 
         cpu_clear_prev_logic_pwrst(cpu);
         pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
-        set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
-        scu_pwrst_prepare(cpu, power_state);
+        set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
+        omap_pm_ops.scu_prepare(cpu, power_state);
         l2x0_pwrst_prepare(cpu, save_state);
 
         /*
          * Call low level function  with targeted low power state.
          */
-        cpu_suspend(save_state, omap4_finish_suspend);
+        if (save_state)
+                cpu_suspend(save_state, omap_pm_ops.finish_suspend);
+        else
+                omap_pm_ops.finish_suspend(save_state);
 
         /*
          * Restore the CPUx power state to ON otherwise CPUx
@@ -268,14 +305,14 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
         pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
         pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
         set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup));
-        scu_pwrst_prepare(cpu, power_state);
+        omap_pm_ops.scu_prepare(cpu, power_state);
 
         /*
          * CPU never retuns back if targeted power state is OFF mode.
          * CPU ONLINE follows normal CPU ONLINE ptah via
-         * omap_secondary_startup().
+         * omap4_secondary_startup().
          */
-        omap4_finish_suspend(cpu_state);
+        omap_pm_ops.finish_suspend(cpu_state);
 
         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
         return 0;
@@ -319,9 +356,9 @@ int __init omap4_mpuss_init(void)
         pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
         pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
         if (cpu_is_omap446x())
-                pm_info->secondary_startup = omap_secondary_startup_4460;
+                pm_info->secondary_startup = omap4460_secondary_startup;
         else
-                pm_info->secondary_startup = omap_secondary_startup;
+                pm_info->secondary_startup = omap4_secondary_startup;
 
         pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
         if (!pm_info->pwrdm) {
@@ -352,6 +389,12 @@ int __init omap4_mpuss_init(void)
 
         save_l2x0_context();
 
+        if (cpu_is_omap44xx()) {
+                omap_pm_ops.finish_suspend = omap4_finish_suspend;
+                omap_pm_ops.resume = omap4_cpu_resume;
+                omap_pm_ops.scu_prepare = scu_pwrst_prepare;
+        }
+
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 2a551f997aea..98a11463a843 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -87,7 +87,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
 
         /*
          * Update the AuxCoreBoot0 with boot state for secondary core.
-         * omap_secondary_startup() routine will hold the secondary core till
+         * omap4_secondary_startup() routine will hold the secondary core till
          * the AuxCoreBoot1 register is updated with cpu state
          * A barrier is added to ensure that write buffer is drained
          */
@@ -200,7 +200,7 @@ static void __init omap4_smp_init_cpus(void)
 
 static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
 {
-        void *startup_addr = omap_secondary_startup;
+        void *startup_addr = omap4_secondary_startup;
         void __iomem *base = omap_get_wakeupgen_base();
 
         /*
@@ -211,7 +211,7 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
                 scu_enable(scu_base);
 
         if (cpu_is_omap446x()) {
-                startup_addr = omap_secondary_startup_4460;
+                startup_addr = omap4460_secondary_startup;
                 pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
         }
 
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 13b27ffaf45e..38cd3a69cff3 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -339,19 +339,3 @@ int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
         return 0;
 }
 #endif
-
-/**
- * omap44xx_restart - trigger a software restart of the SoC
- * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
- * @cmd: passed from the userspace program rebooting the system (if provided)
- *
- * Resets the SoC.  For @cmd, see the 'reboot' syscall in
- * kernel/sys.c.  No return value.
- */
-void omap44xx_restart(char mode, const char *cmd)
-{
-        /* XXX Should save 'cmd' into scratchpad for use after reboot */
-        omap4_prminst_global_warm_sw_reset(); /* never returns */
-        while (1);
-}
-
diff --git a/arch/arm/mach-omap2/omap4-restart.c b/arch/arm/mach-omap2/omap4-restart.c
new file mode 100644
index 000000000000..f90e02e11898
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4-restart.c
@@ -0,0 +1,27 @@
+/*
+ * omap4-restart.c - Common to OMAP4 and OMAP5
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/types.h>
+#include "prminst44xx.h"
+
+/**
+ * omap44xx_restart - trigger a software restart of the SoC
+ * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
+ * @cmd: passed from the userspace program rebooting the system (if provided)
+ *
+ * Resets the SoC.  For @cmd, see the 'reboot' syscall in
+ * kernel/sys.c.  No return value.
+ */
+void omap44xx_restart(char mode, const char *cmd)
+{
+        /* XXX Should save 'cmd' into scratchpad for use after reboot */
+        omap4_prminst_global_warm_sw_reset(); /* never returns */
+        while (1)
+                ;
+}
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 0c898f58ac9b..aab33fd814c0 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -699,6 +699,7 @@ extern int omap2420_hwmod_init(void);
 extern int omap2430_hwmod_init(void);
 extern int omap3xxx_hwmod_init(void);
 extern int omap44xx_hwmod_init(void);
+extern int omap54xx_hwmod_init(void);
 extern int am33xx_hwmod_init(void);
 
 extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 075f7cc51026..0c9a183131e2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -329,7 +329,7 @@ static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 };
 
 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
-        { .name = "gfx", .rst_shift = 0 },
+        { .name = "gfx", .rst_shift = 0, .st_shift = 0},
 };
 
 static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
@@ -347,6 +347,7 @@ static struct omap_hwmod am33xx_gfx_hwmod = {
                 .omap4  = {
                         .clkctrl_offs   = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
                         .rstctrl_offs   = AM33XX_RM_GFX_RSTCTRL_OFFSET,
+                        .rstst_offs     = AM33XX_RM_GFX_RSTST_OFFSET,
                         .modulemode     = MODULEMODE_SWCTRL,
                 },
         },
@@ -2007,6 +2008,13 @@ static struct omap_hwmod am33xx_uart1_hwmod = {
         },
 };
 
+/* uart2 */
+static struct omap_hwmod_dma_info uart2_edma_reqs[] = {
+        { .name = "tx", .dma_req = 28, },
+        { .name = "rx", .dma_req = 29, },
+        { .dma_req = -1 }
+};
+
 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
         { .irq = 73 + OMAP_INTC_START, },
         { .irq = -1 },
@@ -2018,7 +2026,7 @@ static struct omap_hwmod am33xx_uart2_hwmod = {
         .clkdm_name     = "l4ls_clkdm",
         .flags          = HWMOD_SWSUP_SIDLE_ACT,
         .mpu_irqs       = am33xx_uart2_irqs,
-        .sdma_reqs      = uart1_edma_reqs,
+        .sdma_reqs      = uart2_edma_reqs,
         .main_clk       = "dpll_per_m2_div4_ck",
         .prcm           = {
                 .omap4  = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
new file mode 100644
index 000000000000..f37ae96b70a1
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -0,0 +1,2150 @@
+/*
+ * Hardware modules present on the OMAP54xx chips
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley
+ * Benoit Cousson
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/power/smartreflex.h>
+#include <linux/i2c-omap.h>
+
+#include <linux/omap-dma.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
+#include <plat/dmtimer.h>
+
+#include "omap_hwmod.h"
+#include "omap_hwmod_common_data.h"
+#include "cm1_54xx.h"
+#include "cm2_54xx.h"
+#include "prm54xx.h"
+#include "prm-regbits-54xx.h"
+#include "i2c.h"
+#include "mmc.h"
+#include "wd_timer.h"
+
+/* Base offset for all OMAP5 interrupts external to MPUSS */
+#define OMAP54XX_IRQ_GIC_START  32
+
+/* Base offset for all OMAP5 dma requests */
+#define OMAP54XX_DMA_REQ_START  1
+
+
+/*
+ * IP blocks
+ */
+
+/*
+ * 'dmm' class
+ * instance(s): dmm
+ */
+static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
+        .name   = "dmm",
+};
+
+/* dmm */
+static struct omap_hwmod omap54xx_dmm_hwmod = {
+        .name           = "dmm",
+        .class          = &omap54xx_dmm_hwmod_class,
+        .clkdm_name     = "emif_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/*
+ * 'l3' class
+ * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
+ */
+static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
+        .name   = "l3",
+};
+
+/* l3_instr */
+static struct omap_hwmod omap54xx_l3_instr_hwmod = {
+        .name           = "l3_instr",
+        .class          = &omap54xx_l3_hwmod_class,
+        .clkdm_name     = "l3instr_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/* l3_main_1 */
+static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
+        .name           = "l3_main_1",
+        .class          = &omap54xx_l3_hwmod_class,
+        .clkdm_name     = "l3main1_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* l3_main_2 */
+static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
+        .name           = "l3_main_2",
+        .class          = &omap54xx_l3_hwmod_class,
+        .clkdm_name     = "l3main2_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* l3_main_3 */
+static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
+        .name           = "l3_main_3",
+        .class          = &omap54xx_l3_hwmod_class,
+        .clkdm_name     = "l3instr_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/*
+ * 'l4' class
+ * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
+ */
+static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
+        .name   = "l4",
+};
+
+/* l4_abe */
+static struct omap_hwmod omap54xx_l4_abe_hwmod = {
+        .name           = "l4_abe",
+        .class          = &omap54xx_l4_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
+};
+
+/* l4_cfg */
+static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
+        .name           = "l4_cfg",
+        .class          = &omap54xx_l4_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* l4_per */
+static struct omap_hwmod omap54xx_l4_per_hwmod = {
+        .name           = "l4_per",
+        .class          = &omap54xx_l4_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* l4_wkup */
+static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
+        .name           = "l4_wkup",
+        .class          = &omap54xx_l4_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/*
+ * 'mpu_bus' class
+ * instance(s): mpu_private
+ */
+static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
+        .name   = "mpu_bus",
+};
+
+/* mpu_private */
+static struct omap_hwmod omap54xx_mpu_private_hwmod = {
+        .name           = "mpu_private",
+        .class          = &omap54xx_mpu_bus_hwmod_class,
+        .clkdm_name     = "mpu_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
+};
+
+/*
+ * 'counter' class
+ * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
+        .name   = "counter",
+        .sysc   = &omap54xx_counter_sysc,
+};
+
+/* counter_32k */
+static struct omap_hwmod omap54xx_counter_32k_hwmod = {
+        .name           = "counter_32k",
+        .class          = &omap54xx_counter_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE,
+        .main_clk       = "wkupaon_iclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/*
+ * 'dma' class
+ * dma controller for data exchange between memory to memory (i.e. internal or
+ * external memory) and gp peripherals to memory or memory to gp peripherals
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x002c,
+        .syss_offs      = 0x0028,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
+        .name   = "dma",
+        .sysc   = &omap54xx_dma_sysc,
+};
+
+/* dma dev_attr */
+static struct omap_dma_dev_attr dma_dev_attr = {
+        .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+                          IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
+        .lch_count      = 32,
+};
+
+/* dma_system */
+static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
+        { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
+        { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
+        { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
+        { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod omap54xx_dma_system_hwmod = {
+        .name           = "dma_system",
+        .class          = &omap54xx_dma_hwmod_class,
+        .clkdm_name     = "dma_clkdm",
+        .mpu_irqs       = omap54xx_dma_system_irqs,
+        .main_clk       = "l3_iclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
+                },
+        },
+        .dev_attr       = &dma_dev_attr,
+};
+
+/*
+ * 'dmic' class
+ * digital microphone controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
+        .name   = "dmic",
+        .sysc   = &omap54xx_dmic_sysc,
+};
+
+/* dmic */
+static struct omap_hwmod omap54xx_dmic_hwmod = {
+        .name           = "dmic",
+        .class          = &omap54xx_dmic_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "dmic_gfclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'emif' class
+ * external memory interface no1 (wrapper)
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
+        .rev_offs       = 0x0000,
+};
+
+static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
+        .name   = "emif",
+        .sysc   = &omap54xx_emif_sysc,
+};
+
+/* emif1 */
+static struct omap_hwmod omap54xx_emif1_hwmod = {
+        .name           = "emif1",
+        .class          = &omap54xx_emif_hwmod_class,
+        .clkdm_name     = "emif_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .main_clk       = "dpll_core_h11x2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/* emif2 */
+static struct omap_hwmod omap54xx_emif2_hwmod = {
+        .name           = "emif2",
+        .class          = &omap54xx_emif_hwmod_class,
+        .clkdm_name     = "emif_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .main_clk       = "dpll_core_h11x2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/*
+ * 'gpio' class
+ * general purpose io module
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0114,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
+        .name   = "gpio",
+        .sysc   = &omap54xx_gpio_sysc,
+        .rev    = 2,
+};
+
+/* gpio dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+        .bank_width     = 32,
+        .dbck_flag      = true,
+};
+
+/* gpio1 */
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio1_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio1_hwmod = {
+        .name           = "gpio1",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .main_clk       = "wkupaon_iclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio2 */
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio2_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio2_hwmod = {
+        .name           = "gpio2",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio3 */
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio3_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio3_hwmod = {
+        .name           = "gpio3",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio3_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio4 */
+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio4_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio4_hwmod = {
+        .name           = "gpio4",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio4_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio5 */
+static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio5_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio5_hwmod = {
+        .name           = "gpio5",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio5_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio6 */
+static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio6_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio6_hwmod = {
+        .name           = "gpio6",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio6_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio7 */
+static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio7_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio7_hwmod = {
+        .name           = "gpio7",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio7_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio8 */
+static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio8_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio8_hwmod = {
+        .name           = "gpio8",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio8_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/*
+ * 'i2c' class
+ * multimaster high-speed i2c controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0090,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .clockact       = CLOCKACT_TEST_ICLK,
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
+        .name   = "i2c",
+        .sysc   = &omap54xx_i2c_sysc,
+        .reset  = &omap_i2c_reset,
+        .rev    = OMAP_I2C_IP_VERSION_2,
+};
+
+/* i2c dev_attr */
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+        .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
+};
+
+/* i2c1 */
+static struct omap_hwmod omap54xx_i2c1_hwmod = {
+        .name           = "i2c1",
+        .class          = &omap54xx_i2c_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/* i2c2 */
+static struct omap_hwmod omap54xx_i2c2_hwmod = {
+        .name           = "i2c2",
+        .class          = &omap54xx_i2c_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/* i2c3 */
+static struct omap_hwmod omap54xx_i2c3_hwmod = {
+        .name           = "i2c3",
+        .class          = &omap54xx_i2c_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/* i2c4 */
+static struct omap_hwmod omap54xx_i2c4_hwmod = {
+        .name           = "i2c4",
+        .class          = &omap54xx_i2c_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/* i2c5 */
+static struct omap_hwmod omap54xx_i2c5_hwmod = {
+        .name           = "i2c5",
+        .class          = &omap54xx_i2c_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/*
+ * 'kbd' class
+ * keyboard controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
+        .name   = "kbd",
+        .sysc   = &omap54xx_kbd_sysc,
+};
+
+/* kbd */
+static struct omap_hwmod omap54xx_kbd_hwmod = {
+        .name           = "kbd",
+        .class          = &omap54xx_kbd_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .main_clk       = "sys_32k_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'mcbsp' class
+ * multi channel buffered serial port controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
+        .sysc_offs      = 0x008c,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
+        .name   = "mcbsp",
+        .sysc   = &omap54xx_mcbsp_sysc,
+        .rev    = MCBSP_CONFIG_TYPE4,
+};
+
+/* mcbsp1 */
+static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
+        { .role = "pad_fck", .clk = "pad_clks_ck" },
+        { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
+};
+
+static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
+        .name           = "mcbsp1",
+        .class          = &omap54xx_mcbsp_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "mcbsp1_gfclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = mcbsp1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
+};
+
+/* mcbsp2 */
+static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
+        { .role = "pad_fck", .clk = "pad_clks_ck" },
+        { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
+};
+
+static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
+        .name           = "mcbsp2",
+        .class          = &omap54xx_mcbsp_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "mcbsp2_gfclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = mcbsp2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
+};
+
+/* mcbsp3 */
+static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
+        { .role = "pad_fck", .clk = "pad_clks_ck" },
+        { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
+};
+
+static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
+        .name           = "mcbsp3",
+        .class          = &omap54xx_mcbsp_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "mcbsp3_gfclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = mcbsp3_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
+};
+
+/*
+ * 'mcpdm' class
+ * multi channel pdm controller (proprietary interface with phoenix power
+ * ic)
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
+        .name   = "mcpdm",
+        .sysc   = &omap54xx_mcpdm_sysc,
+};
+
+/* mcpdm */
+static struct omap_hwmod omap54xx_mcpdm_hwmod = {
+        .name           = "mcpdm",
+        .class          = &omap54xx_mcpdm_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        /*
+         * It's suspected that the McPDM requires an off-chip main
+         * functional clock, controlled via I2C.  This IP block is
+         * currently reset very early during boot, before I2C is
+         * available, so it doesn't seem that we have any choice in
+         * the kernel other than to avoid resetting it.  XXX This is
+         * really a hardware issue workaround: every IP block should
+         * be able to source its main functional clock from either
+         * on-chip or off-chip sources.  McPDM seems to be the only
+         * current exception.
+         */
+
+        .flags          = HWMOD_EXT_OPT_MAIN_CLK,
+        .main_clk       = "pad_clks_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
+        .name   = "mcspi",
+        .sysc   = &omap54xx_mcspi_sysc,
+        .rev    = OMAP4_MCSPI_REV,
+};
+
+/* mcspi1 */
+/* mcspi1 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
+        .num_chipselect = 4,
+};
+
+static struct omap_hwmod omap54xx_mcspi1_hwmod = {
+        .name           = "mcspi1",
+        .class          = &omap54xx_mcspi_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi1_dev_attr,
+};
+
+/* mcspi2 */
+/* mcspi2 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
+        .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap54xx_mcspi2_hwmod = {
+        .name           = "mcspi2",
+        .class          = &omap54xx_mcspi_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi2_dev_attr,
+};
+
+/* mcspi3 */
+/* mcspi3 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
+        .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap54xx_mcspi3_hwmod = {
+        .name           = "mcspi3",
+        .class          = &omap54xx_mcspi_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi3_dev_attr,
+};
+
+/* mcspi4 */
+/* mcspi4 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
+        .num_chipselect = 1,
+};
+
+static struct omap_hwmod omap54xx_mcspi4_hwmod = {
+        .name           = "mcspi4",
+        .class          = &omap54xx_mcspi_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi4_dev_attr,
+};
+
+/*
+ * 'mmc' class
+ * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
+        .name   = "mmc",
+        .sysc   = &omap54xx_mmc_sysc,
+};
+
+/* mmc1 */
+static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
+        { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
+};
+
+/* mmc1 dev_attr */
+static struct omap_mmc_dev_attr mmc1_dev_attr = {
+        .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod omap54xx_mmc1_hwmod = {
+        .name           = "mmc1",
+        .class          = &omap54xx_mmc_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "mmc1_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = mmc1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
+        .dev_attr       = &mmc1_dev_attr,
+};
+
+/* mmc2 */
+static struct omap_hwmod omap54xx_mmc2_hwmod = {
+        .name           = "mmc2",
+        .class          = &omap54xx_mmc_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "mmc2_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* mmc3 */
+static struct omap_hwmod omap54xx_mmc3_hwmod = {
+        .name           = "mmc3",
+        .class          = &omap54xx_mmc_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* mmc4 */
+static struct omap_hwmod omap54xx_mmc4_hwmod = {
+        .name           = "mmc4",
+        .class          = &omap54xx_mmc_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* mmc5 */
+static struct omap_hwmod omap54xx_mmc5_hwmod = {
+        .name           = "mmc5",
+        .class          = &omap54xx_mmc_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'mpu' class
+ * mpu sub-system
+ */
+
+static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
+        .name   = "mpu",
+};
+
+/* mpu */
+static struct omap_hwmod omap54xx_mpu_hwmod = {
+        .name           = "mpu",
+        .class          = &omap54xx_mpu_hwmod_class,
+        .clkdm_name     = "mpu_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .main_clk       = "dpll_mpu_m2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/*
+ * 'timer' class
+ * general purpose timer module with accurate 1ms tick
+ * This class contains several variants: ['timer_1ms', 'timer']
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+        .clockact       = CLOCKACT_TEST_ICLK,
+};
+
+static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
+        .name   = "timer",
+        .sysc   = &omap54xx_timer_1ms_sysc,
+};
+
+static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
+        .name   = "timer",
+        .sysc   = &omap54xx_timer_sysc,
+};
+
+/* timer1 */
+static struct omap_hwmod omap54xx_timer1_hwmod = {
+        .name           = "timer1",
+        .class          = &omap54xx_timer_1ms_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .main_clk       = "timer1_gfclk_mux",
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer2 */
+static struct omap_hwmod omap54xx_timer2_hwmod = {
+        .name           = "timer2",
+        .class          = &omap54xx_timer_1ms_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer2_gfclk_mux",
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer3 */
+static struct omap_hwmod omap54xx_timer3_hwmod = {
+        .name           = "timer3",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer3_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer4 */
+static struct omap_hwmod omap54xx_timer4_hwmod = {
+        .name           = "timer4",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer4_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer5 */
+static struct omap_hwmod omap54xx_timer5_hwmod = {
+        .name           = "timer5",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "timer5_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer6 */
+static struct omap_hwmod omap54xx_timer6_hwmod = {
+        .name           = "timer6",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "timer6_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer7 */
+static struct omap_hwmod omap54xx_timer7_hwmod = {
+        .name           = "timer7",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "timer7_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer8 */
+static struct omap_hwmod omap54xx_timer8_hwmod = {
+        .name           = "timer8",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "timer8_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer9 */
+static struct omap_hwmod omap54xx_timer9_hwmod = {
+        .name           = "timer9",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer9_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer10 */
+static struct omap_hwmod omap54xx_timer10_hwmod = {
+        .name           = "timer10",
+        .class          = &omap54xx_timer_1ms_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer10_gfclk_mux",
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer11 */
+static struct omap_hwmod omap54xx_timer11_hwmod = {
+        .name           = "timer11",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer11_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'uart' class
+ * universal asynchronous receiver/transmitter (uart)
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
+        .rev_offs       = 0x0050,
+        .sysc_offs      = 0x0054,
+        .syss_offs      = 0x0058,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
+        .name   = "uart",
+        .sysc   = &omap54xx_uart_sysc,
+};
+
+/* uart1 */
+static struct omap_hwmod omap54xx_uart1_hwmod = {
+        .name           = "uart1",
+        .class          = &omap54xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* uart2 */
+static struct omap_hwmod omap54xx_uart2_hwmod = {
+        .name           = "uart2",
+        .class          = &omap54xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* uart3 */
+static struct omap_hwmod omap54xx_uart3_hwmod = {
+        .name           = "uart3",
+        .class          = &omap54xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* uart4 */
+static struct omap_hwmod omap54xx_uart4_hwmod = {
+        .name           = "uart4",
+        .class          = &omap54xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* uart5 */
+static struct omap_hwmod omap54xx_uart5_hwmod = {
+        .name           = "uart5",
+        .class          = &omap54xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* uart6 */
+static struct omap_hwmod omap54xx_uart6_hwmod = {
+        .name           = "uart6",
+        .class          = &omap54xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'usb_otg_ss' class
+ * 2.0 super speed (usb_otg_ss) controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_SIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
+        .name   = "usb_otg_ss",
+        .sysc   = &omap54xx_usb_otg_ss_sysc,
+};
+
+/* usb_otg_ss */
+static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
+        { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
+};
+
+static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
+        .name           = "usb_otg_ss",
+        .class          = &omap54xx_usb_otg_ss_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE,
+        .main_clk       = "dpll_core_h13x2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = usb_otg_ss_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss_opt_clks),
+};
+
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
+        .name           = "wd_timer",
+        .sysc           = &omap54xx_wd_timer_sysc,
+        .pre_shutdown   = &omap2_wd_timer_disable,
+};
+
+/* wd_timer2 */
+static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &omap54xx_wd_timer_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .main_clk       = "sys_32k_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+
+/*
+ * Interfaces
+ */
+
+/* l3_main_1 -> dmm */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
+        .master         = &omap54xx_l3_main_1_hwmod,
+        .slave          = &omap54xx_dmm_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_SDMA,
+};
+
+/* l3_main_3 -> l3_instr */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
+        .master         = &omap54xx_l3_main_3_hwmod,
+        .slave          = &omap54xx_l3_instr_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
+        .master         = &omap54xx_l3_main_2_hwmod,
+        .slave          = &omap54xx_l3_main_1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_l3_main_1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
+        .master         = &omap54xx_mpu_hwmod,
+        .slave          = &omap54xx_l3_main_1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU,
+};
+
+/* l3_main_1 -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
+        .master         = &omap54xx_l3_main_1_hwmod,
+        .slave          = &omap54xx_l3_main_2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_cfg -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_l3_main_2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
+        .master         = &omap54xx_l3_main_1_hwmod,
+        .slave          = &omap54xx_l3_main_3_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU,
+};
+
+/* l3_main_2 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
+        .master         = &omap54xx_l3_main_2_hwmod,
+        .slave          = &omap54xx_l3_main_3_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_l3_main_3_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_abe */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
+        .master         = &omap54xx_l3_main_1_hwmod,
+        .slave          = &omap54xx_l4_abe_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l4_abe */
+static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
+        .master         = &omap54xx_mpu_hwmod,
+        .slave          = &omap54xx_l4_abe_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_cfg */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
+        .master         = &omap54xx_l3_main_1_hwmod,
+        .slave          = &omap54xx_l4_cfg_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> l4_per */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
+        .master         = &omap54xx_l3_main_2_hwmod,
+        .slave          = &omap54xx_l4_per_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_wkup */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
+        .master         = &omap54xx_l3_main_1_hwmod,
+        .slave          = &omap54xx_l4_wkup_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> mpu_private */
+static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
+        .master         = &omap54xx_mpu_hwmod,
+        .slave          = &omap54xx_mpu_private_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> counter_32k */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
+        .master         = &omap54xx_l4_wkup_hwmod,
+        .slave          = &omap54xx_counter_32k_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
+        {
+                .pa_start       = 0x4a056000,
+                .pa_end         = 0x4a056fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> dma_system */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_dma_system_hwmod,
+        .clk            = "l4_root_clk_div",
+        .addr           = omap54xx_dma_system_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_abe -> dmic */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_dmic_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* mpu -> emif1 */
+static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
+        .master         = &omap54xx_mpu_hwmod,
+        .slave          = &omap54xx_emif1_hwmod,
+        .clk            = "dpll_core_h11x2_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> emif2 */
+static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
+        .master         = &omap54xx_mpu_hwmod,
+        .slave          = &omap54xx_emif2_hwmod,
+        .clk            = "dpll_core_h11x2_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
+        .master         = &omap54xx_l4_wkup_hwmod,
+        .slave          = &omap54xx_gpio1_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio2_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio3_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio4_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio5_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio6 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio6_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio7 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio7_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio8 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio8_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> i2c1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_i2c1_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> i2c2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_i2c2_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> i2c3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_i2c3_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> i2c4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_i2c4_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> i2c5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_i2c5_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> kbd */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
+        .master         = &omap54xx_l4_wkup_hwmod,
+        .slave          = &omap54xx_kbd_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_abe -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_mcbsp1_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_abe -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_mcbsp2_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_abe -> mcbsp3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_mcbsp3_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_abe -> mcpdm */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_mcpdm_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_per -> mcspi1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mcspi1_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mcspi2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mcspi2_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mcspi3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mcspi3_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mcspi4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mcspi4_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mmc1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mmc1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mmc2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mmc2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mmc3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mmc3_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mmc4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mmc4_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mmc5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mmc5_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> mpu */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_mpu_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
+        .master         = &omap54xx_l4_wkup_hwmod,
+        .slave          = &omap54xx_timer1_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> timer2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_timer2_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> timer3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_timer3_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> timer4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_timer4_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_abe -> timer5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_timer5_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_abe -> timer6 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_timer6_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_abe -> timer7 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_timer7_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_abe -> timer8 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_timer8_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_per -> timer9 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_timer9_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> timer10 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_timer10_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> timer11 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_timer11_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_uart1_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_uart2_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_uart3_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_uart4_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_uart5_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart6 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_uart6_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> usb_otg_ss */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_usb_otg_ss_hwmod,
+        .clk            = "dpll_core_h13x2_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
+        .master         = &omap54xx_l4_wkup_hwmod,
+        .slave          = &omap54xx_wd_timer2_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
+        &omap54xx_l3_main_1__dmm,
+        &omap54xx_l3_main_3__l3_instr,
+        &omap54xx_l3_main_2__l3_main_1,
+        &omap54xx_l4_cfg__l3_main_1,
+        &omap54xx_mpu__l3_main_1,
+        &omap54xx_l3_main_1__l3_main_2,
+        &omap54xx_l4_cfg__l3_main_2,
+        &omap54xx_l3_main_1__l3_main_3,
+        &omap54xx_l3_main_2__l3_main_3,
+        &omap54xx_l4_cfg__l3_main_3,
+        &omap54xx_l3_main_1__l4_abe,
+        &omap54xx_mpu__l4_abe,
+        &omap54xx_l3_main_1__l4_cfg,
+        &omap54xx_l3_main_2__l4_per,
+        &omap54xx_l3_main_1__l4_wkup,
+        &omap54xx_mpu__mpu_private,
+        &omap54xx_l4_wkup__counter_32k,
+        &omap54xx_l4_cfg__dma_system,
+        &omap54xx_l4_abe__dmic,
+        &omap54xx_mpu__emif1,
+        &omap54xx_mpu__emif2,
+        &omap54xx_l4_wkup__gpio1,
+        &omap54xx_l4_per__gpio2,
+        &omap54xx_l4_per__gpio3,
+        &omap54xx_l4_per__gpio4,
+        &omap54xx_l4_per__gpio5,
+        &omap54xx_l4_per__gpio6,
+        &omap54xx_l4_per__gpio7,
+        &omap54xx_l4_per__gpio8,
+        &omap54xx_l4_per__i2c1,
+        &omap54xx_l4_per__i2c2,
+        &omap54xx_l4_per__i2c3,
+        &omap54xx_l4_per__i2c4,
+        &omap54xx_l4_per__i2c5,
+        &omap54xx_l4_wkup__kbd,
+        &omap54xx_l4_abe__mcbsp1,
+        &omap54xx_l4_abe__mcbsp2,
+        &omap54xx_l4_abe__mcbsp3,
+        &omap54xx_l4_abe__mcpdm,
+        &omap54xx_l4_per__mcspi1,
+        &omap54xx_l4_per__mcspi2,
+        &omap54xx_l4_per__mcspi3,
+        &omap54xx_l4_per__mcspi4,
+        &omap54xx_l4_per__mmc1,
+        &omap54xx_l4_per__mmc2,
+        &omap54xx_l4_per__mmc3,
+        &omap54xx_l4_per__mmc4,
+        &omap54xx_l4_per__mmc5,
+        &omap54xx_l4_cfg__mpu,
+        &omap54xx_l4_wkup__timer1,
+        &omap54xx_l4_per__timer2,
+        &omap54xx_l4_per__timer3,
+        &omap54xx_l4_per__timer4,
+        &omap54xx_l4_abe__timer5,
+        &omap54xx_l4_abe__timer6,
+        &omap54xx_l4_abe__timer7,
+        &omap54xx_l4_abe__timer8,
+        &omap54xx_l4_per__timer9,
+        &omap54xx_l4_per__timer10,
+        &omap54xx_l4_per__timer11,
+        &omap54xx_l4_per__uart1,
+        &omap54xx_l4_per__uart2,
+        &omap54xx_l4_per__uart3,
+        &omap54xx_l4_per__uart4,
+        &omap54xx_l4_per__uart5,
+        &omap54xx_l4_per__uart6,
+        &omap54xx_l4_cfg__usb_otg_ss,
+        &omap54xx_l4_wkup__wd_timer2,
+        NULL,
+};
+
+int __init omap54xx_hwmod_init(void)
+{
+        omap_hwmod_init();
+        return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
+}
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index c01859398b54..5a2d8034c8de 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -546,8 +546,10 @@ static void __init prcm_setup_regs(void)
         /* Clear any pending PRCM interrupts */
         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 
-        if (omap3_has_iva())
-                omap3_iva_idle();
+        /*
+         * We need to idle iva2_pwrdm even on am3703 with no iva2.
+         */
+        omap3_iva_idle();
 
         omap3_d2d_idle();
 }
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index a251f87fa2a2..82f0698933d8 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -1,7 +1,7 @@
 /*
- * OMAP4 Power Management Routines
+ * OMAP4+ Power Management Routines
  *
- * Copyright (C) 2010-2011 Texas Instruments, Inc.
+ * Copyright (C) 2010-2013 Texas Instruments, Inc.
  * Rajendra Nayak <rnayak@ti.com>
  * Santosh Shilimkar <santosh.shilimkar@ti.com>
  *
@@ -135,16 +135,16 @@ static void omap_default_idle(void)
 }
 
 /**
- * omap4_pm_init - Init routine for OMAP4 PM
+ * omap4_init_static_deps - Add OMAP4 static dependencies
  *
- * Initializes all powerdomain and clockdomain target states
- * and all PRCM settings.
+ * Add needed static clockdomain dependencies on OMAP4 devices.
+ * Return: 0 on success or 'err' on failures
  */
-int __init omap4_pm_init(void)
+static inline int omap4_init_static_deps(void)
 {
-        int ret;
         struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
         struct clockdomain *ducati_clkdm, *l3_2_clkdm;
+        int ret = 0;
 
         if (omap_rev() == OMAP4430_REV_ES1_0) {
                 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
@@ -163,7 +163,7 @@ int __init omap4_pm_init(void)
         ret = pwrdm_for_each(pwrdms_setup, NULL);
         if (ret) {
                 pr_err("Failed to setup powerdomains\n");
-                goto err2;
+                return ret;
         }
 
         /*
@@ -171,6 +171,10 @@ int __init omap4_pm_init(void)
          * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
          * expected. The hardware recommendation is to enable static
          * dependencies for these to avoid system lock ups or random crashes.
+         * The L4 wakeup depedency is added to workaround the OCP sync hardware
+         * BUG with 32K synctimer which lead to incorrect timer value read
+         * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
+         * are part of L4 wakeup clockdomain.
          */
         mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
         emif_clkdm = clkdm_lookup("l3_emif_clkdm");
@@ -179,7 +183,7 @@ int __init omap4_pm_init(void)
         ducati_clkdm = clkdm_lookup("ducati_clkdm");
         if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
                 (!l3_2_clkdm) || (!ducati_clkdm))
-                goto err2;
+                return -EINVAL;
 
         ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
         ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
@@ -188,9 +192,42 @@ int __init omap4_pm_init(void)
         ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
         if (ret) {
                 pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
+                return -EINVAL;
+        }
+
+        return ret;
+}
+
+/**
+ * omap4_pm_init - Init routine for OMAP4+ devices
+ *
+ * Initializes all powerdomain and clockdomain target states
+ * and all PRCM settings.
+ * Return: Returns the error code returned by called functions.
+ */
+int __init omap4_pm_init(void)
+{
+        int ret = 0;
+
+        if (omap_rev() == OMAP4430_REV_ES1_0) {
+                WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
+                return -ENODEV;
+        }
+
+        pr_info("Power Management for TI OMAP4+ devices.\n");
+
+        ret = pwrdm_for_each(pwrdms_setup, NULL);
+        if (ret) {
+                pr_err("Failed to setup powerdomains.\n");
                 goto err2;
         }
 
+        if (cpu_is_omap44xx()) {
+                ret = omap4_init_static_deps();
+                if (ret)
+                        goto err2;
+        }
+
         ret = omap4_mpuss_init();
         if (ret) {
                 pr_err("Failed to initialise OMAP4 MPUSS\n");
@@ -206,7 +243,8 @@ int __init omap4_pm_init(void)
         /* Overwrite the default cpu_do_idle() */
         arm_pm_idle = omap_default_idle;
 
-        omap4_idle_init();
+        if (cpu_is_omap44xx())
+                omap4_idle_init();
 
 err2:
         return ret;
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 86babd740d41..e233dfcbc186 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -102,6 +102,10 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
         if (_pwrdm_lookup(pwrdm->name))
                 return -EEXIST;
 
+        if (arch_pwrdm && arch_pwrdm->pwrdm_has_voltdm)
+                if (!arch_pwrdm->pwrdm_has_voltdm())
+                        goto skip_voltdm;
+
         voltdm = voltdm_lookup(pwrdm->voltdm.name);
         if (!voltdm) {
                 pr_err("powerdomain: %s: voltagedomain %s does not exist\n",
@@ -111,6 +115,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
         pwrdm->voltdm.ptr = voltdm;
         INIT_LIST_HEAD(&pwrdm->voltdm_node);
         voltdm_add_pwrdm(voltdm, pwrdm);
+skip_voltdm:
         spin_lock_init(&pwrdm->_lock);
 
         list_add(&pwrdm->node, &pwrdm_list);
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 140c36074fed..e4d7bd6f94b8 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -166,6 +166,7 @@ struct powerdomain {
  * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
  * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
  * @pwrdm_wait_transition: Wait for a pd state transition to complete
+ * @pwrdm_has_voltdm: Check if a voltdm association is needed
  *
  * Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family
  * chips, a powerdomain's power state is not allowed to directly
@@ -196,6 +197,7 @@ struct pwrdm_ops {
         int     (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
         int     (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
         int     (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
+        int     (*pwrdm_has_voltdm)(void);
 };
 
 int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
@@ -253,6 +255,7 @@ extern void omap243x_powerdomains_init(void);
 extern void omap3xxx_powerdomains_init(void);
 extern void am33xx_powerdomains_init(void);
 extern void omap44xx_powerdomains_init(void);
+extern void omap54xx_powerdomains_init(void);
 
 extern struct pwrdm_ops omap2_pwrdm_operations;
 extern struct pwrdm_ops omap3_pwrdm_operations;
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index f0e14e9efe5a..e2d4bd804523 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -336,6 +336,54 @@ static struct powerdomain dpll5_pwrdm = {
         .voltdm           = { .name = "core" },
 };
 
+static struct powerdomain device_81xx_pwrdm = {
+        .name             = "device_pwrdm",
+        .prcm_offs        = TI81XX_PRM_DEVICE_MOD,
+        .voltdm           = { .name = "core" },
+};
+
+static struct powerdomain active_816x_pwrdm = {
+        .name             = "active_pwrdm",
+        .prcm_offs        = TI816X_PRM_ACTIVE_MOD,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .voltdm           = { .name = "core" },
+};
+
+static struct powerdomain default_816x_pwrdm = {
+        .name             = "default_pwrdm",
+        .prcm_offs        = TI81XX_PRM_DEFAULT_MOD,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .voltdm           = { .name = "core" },
+};
+
+static struct powerdomain ivahd0_816x_pwrdm = {
+        .name             = "ivahd0_pwrdm",
+        .prcm_offs        = TI816X_PRM_IVAHD0_MOD,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .voltdm           = { .name = "mpu_iva" },
+};
+
+static struct powerdomain ivahd1_816x_pwrdm = {
+        .name             = "ivahd1_pwrdm",
+        .prcm_offs        = TI816X_PRM_IVAHD1_MOD,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .voltdm           = { .name = "mpu_iva" },
+};
+
+static struct powerdomain ivahd2_816x_pwrdm = {
+        .name             = "ivahd2_pwrdm",
+        .prcm_offs        = TI816X_PRM_IVAHD2_MOD,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .voltdm           = { .name = "mpu_iva" },
+};
+
+static struct powerdomain sgx_816x_pwrdm = {
+        .name             = "sgx_pwrdm",
+        .prcm_offs        = TI816X_PRM_SGX_MOD,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .voltdm           = { .name = "core" },
+};
+
 /* As powerdomains are added or removed above, this list must also be changed */
 static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
         &wkup_omap2_pwrdm,
@@ -393,6 +441,17 @@ static struct powerdomain *powerdomains_am35x[] __initdata = {
         NULL
 };
 
+static struct powerdomain *powerdomains_ti81xx[] __initdata = {
+        &device_81xx_pwrdm,
+        &active_816x_pwrdm,
+        &default_816x_pwrdm,
+        &ivahd0_816x_pwrdm,
+        &ivahd1_816x_pwrdm,
+        &ivahd2_816x_pwrdm,
+        &sgx_816x_pwrdm,
+        NULL
+};
+
 void __init omap3xxx_powerdomains_init(void)
 {
         unsigned int rev;
@@ -406,6 +465,9 @@ void __init omap3xxx_powerdomains_init(void)
 
         if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
                 pwrdm_register_pwrdms(powerdomains_am35x);
+        } else if (rev == TI8168_REV_ES1_0 || rev == TI8168_REV_ES1_1
+                        || rev == TI8168_REV_ES2_0 || rev == TI8168_REV_ES2_1) {
+                pwrdm_register_pwrdms(powerdomains_ti81xx);
         } else {
                 pwrdm_register_pwrdms(powerdomains_omap3430_common);
 
diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c
new file mode 100644
index 000000000000..81f8a7cc26ee
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains54xx_data.c
@@ -0,0 +1,331 @@
+/*
+ * OMAP54XX Power domains framework
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Abhijit Pagare (abhijitpagare@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Paul Walmsley (paul@pwsan.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "powerdomain.h"
+
+#include "prcm-common.h"
+#include "prcm44xx.h"
+#include "prm-regbits-54xx.h"
+#include "prm54xx.h"
+#include "prcm_mpu54xx.h"
+
+/* core_54xx_pwrdm: CORE power domain */
+static struct powerdomain core_54xx_pwrdm = {
+        .name             = "core_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_CORE_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 5,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* core_nret_bank */
+                [1] = PWRSTS_OFF_RET,   /* core_ocmram */
+                [2] = PWRSTS_OFF_RET,   /* core_other_bank */
+                [3] = PWRSTS_OFF_RET,   /* ipu_l2ram */
+                [4] = PWRSTS_OFF_RET,   /* ipu_unicache */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* core_nret_bank */
+                [1] = PWRSTS_OFF_RET,   /* core_ocmram */
+                [2] = PWRSTS_OFF_RET,   /* core_other_bank */
+                [3] = PWRSTS_OFF_RET,   /* ipu_l2ram */
+                [4] = PWRSTS_OFF_RET,   /* ipu_unicache */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* abe_54xx_pwrdm: Audio back end power domain */
+static struct powerdomain abe_54xx_pwrdm = {
+        .name             = "abe_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_ABE_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF,
+        .banks            = 2,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* aessmem */
+                [1] = PWRSTS_OFF_RET,   /* periphmem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* aessmem */
+                [1] = PWRSTS_OFF_RET,   /* periphmem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
+static struct powerdomain coreaon_54xx_pwrdm = {
+        .name             = "coreaon_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_COREAON_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_ON,
+};
+
+/* dss_54xx_pwrdm: Display subsystem power domain */
+static struct powerdomain dss_54xx_pwrdm = {
+        .name             = "dss_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_DSS_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* dss_mem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* dss_mem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
+static struct powerdomain cpu0_54xx_pwrdm = {
+        .name             = "cpu0_pwrdm",
+        .voltdm           = { .name = "mpu" },
+        .prcm_offs        = OMAP54XX_PRCM_MPU_PRM_C0_INST,
+        .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* cpu0_l1 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_ON,        /* cpu0_l1 */
+        },
+};
+
+/* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
+static struct powerdomain cpu1_54xx_pwrdm = {
+        .name             = "cpu1_pwrdm",
+        .voltdm           = { .name = "mpu" },
+        .prcm_offs        = OMAP54XX_PRCM_MPU_PRM_C1_INST,
+        .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* cpu1_l1 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_ON,        /* cpu1_l1 */
+        },
+};
+
+/* emu_54xx_pwrdm: Emulation power domain */
+static struct powerdomain emu_54xx_pwrdm = {
+        .name             = "emu_pwrdm",
+        .voltdm           = { .name = "wkup" },
+        .prcm_offs        = OMAP54XX_PRM_EMU_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* emu_bank */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* emu_bank */
+        },
+};
+
+/* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */
+static struct powerdomain mpu_54xx_pwrdm = {
+        .name             = "mpu_pwrdm",
+        .voltdm           = { .name = "mpu" },
+        .prcm_offs        = OMAP54XX_PRM_MPU_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 2,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* mpu_l2 */
+                [1] = PWRSTS_RET,       /* mpu_ram */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* mpu_l2 */
+                [1] = PWRSTS_OFF_RET,   /* mpu_ram */
+        },
+};
+
+/* custefuse_54xx_pwrdm: Customer efuse controller power domain */
+static struct powerdomain custefuse_54xx_pwrdm = {
+        .name             = "custefuse_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_CUSTEFUSE_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* dsp_54xx_pwrdm: Tesla processor power domain */
+static struct powerdomain dsp_54xx_pwrdm = {
+        .name             = "dsp_pwrdm",
+        .voltdm           = { .name = "mm" },
+        .prcm_offs        = OMAP54XX_PRM_DSP_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 3,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* dsp_edma */
+                [1] = PWRSTS_OFF_RET,   /* dsp_l1 */
+                [2] = PWRSTS_OFF_RET,   /* dsp_l2 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* dsp_edma */
+                [1] = PWRSTS_OFF_RET,   /* dsp_l1 */
+                [2] = PWRSTS_OFF_RET,   /* dsp_l2 */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* cam_54xx_pwrdm: Camera subsystem power domain */
+static struct powerdomain cam_54xx_pwrdm = {
+        .name             = "cam_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_CAM_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* cam_mem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* cam_mem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* l3init_54xx_pwrdm: L3 initators pheripherals power domain  */
+static struct powerdomain l3init_54xx_pwrdm = {
+        .name             = "l3init_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_L3INIT_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 2,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* l3init_bank1 */
+                [1] = PWRSTS_OFF_RET,   /* l3init_bank2 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* l3init_bank1 */
+                [1] = PWRSTS_OFF_RET,   /* l3init_bank2 */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* gpu_54xx_pwrdm: 3D accelerator power domain */
+static struct powerdomain gpu_54xx_pwrdm = {
+        .name             = "gpu_pwrdm",
+        .voltdm           = { .name = "mm" },
+        .prcm_offs        = OMAP54XX_PRM_GPU_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* gpu_mem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* gpu_mem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* wkupaon_54xx_pwrdm: Wake-up power domain */
+static struct powerdomain wkupaon_54xx_pwrdm = {
+        .name             = "wkupaon_pwrdm",
+        .voltdm           = { .name = "wkup" },
+        .prcm_offs        = OMAP54XX_PRM_WKUPAON_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_ON,        /* wkup_bank */
+        },
+};
+
+/* iva_54xx_pwrdm: IVA-HD power domain */
+static struct powerdomain iva_54xx_pwrdm = {
+        .name             = "iva_pwrdm",
+        .voltdm           = { .name = "mm" },
+        .prcm_offs        = OMAP54XX_PRM_IVA_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF,
+        .banks            = 4,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* hwa_mem */
+                [1] = PWRSTS_OFF_RET,   /* sl2_mem */
+                [2] = PWRSTS_OFF_RET,   /* tcm1_mem */
+                [3] = PWRSTS_OFF_RET,   /* tcm2_mem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* hwa_mem */
+                [1] = PWRSTS_OFF_RET,   /* sl2_mem */
+                [2] = PWRSTS_OFF_RET,   /* tcm1_mem */
+                [3] = PWRSTS_OFF_RET,   /* tcm2_mem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/*
+ * The following power domains are not under SW control
+ *
+ * mpuaon
+ * mmaon
+ */
+
+/* As powerdomains are added or removed above, this list must also be changed */
+static struct powerdomain *powerdomains_omap54xx[] __initdata = {
+        &core_54xx_pwrdm,
+        &abe_54xx_pwrdm,
+        &coreaon_54xx_pwrdm,
+        &dss_54xx_pwrdm,
+        &cpu0_54xx_pwrdm,
+        &cpu1_54xx_pwrdm,
+        &emu_54xx_pwrdm,
+        &mpu_54xx_pwrdm,
+        &custefuse_54xx_pwrdm,
+        &dsp_54xx_pwrdm,
+        &cam_54xx_pwrdm,
+        &l3init_54xx_pwrdm,
+        &gpu_54xx_pwrdm,
+        &wkupaon_54xx_pwrdm,
+        &iva_54xx_pwrdm,
+        NULL
+};
+
+void __init omap54xx_powerdomains_init(void)
+{
+        pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
+        pwrdm_register_pwrdms(powerdomains_omap54xx);
+        pwrdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index c7d355fafd24..ff1ac4a82a04 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -48,6 +48,17 @@
 #define OMAP3430_NEON_MOD                               0xb00
 #define OMAP3430ES2_USBHOST_MOD                         0xc00
 
+/*
+ * TI81XX PRM module offsets
+ */
+#define TI81XX_PRM_DEVICE_MOD                   0x0000
+#define TI816X_PRM_ACTIVE_MOD                   0x0a00
+#define TI81XX_PRM_DEFAULT_MOD                  0x0b00
+#define TI816X_PRM_IVAHD0_MOD                   0x0c00
+#define TI816X_PRM_IVAHD1_MOD                   0x0d00
+#define TI816X_PRM_IVAHD2_MOD                   0x0e00
+#define TI816X_PRM_SGX_MOD                              0x0f00
+
 /* 24XX register bits shared between CM & PRM registers */
 
 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
diff --git a/arch/arm/mach-omap2/prcm44xx.h b/arch/arm/mach-omap2/prcm44xx.h
index 7334ffb9d2c1..f429cdd5a118 100644
--- a/arch/arm/mach-omap2/prcm44xx.h
+++ b/arch/arm/mach-omap2/prcm44xx.h
@@ -32,6 +32,12 @@
 #define OMAP4430_SCRM_PARTITION                 4
 #define OMAP4430_PRCM_MPU_PARTITION             5
 
+#define OMAP54XX_PRM_PARTITION                  1
+#define OMAP54XX_CM_CORE_AON_PARTITION          2
+#define OMAP54XX_CM_CORE_PARTITION              3
+#define OMAP54XX_SCRM_PARTITION                 4
+#define OMAP54XX_PRCM_MPU_PARTITION             5
+
 /*
  * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
  * IDs, plus one
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index 884af7bb4afd..059bd4f49035 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -25,12 +25,9 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
 
+#include "prcm_mpu_44xx_54xx.h"
 #include "common.h"
 
-# ifndef __ASSEMBLER__
-extern void __iomem *prcm_mpu_base;
-# endif
-
 #define OMAP4430_PRCM_MPU_BASE                  0x48243000
 
 #define OMAP44XX_PRCM_MPU_REGADDR(inst, reg)                            \
@@ -98,13 +95,4 @@ extern void __iomem *prcm_mpu_base;
 #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET          0x0018
 #define OMAP4430_CM_CPU1_CLKSTCTRL              OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
 
-/* Function prototypes */
-# ifndef __ASSEMBLER__
-extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
-                                            s16 idx);
-extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
-# endif
-
 #endif
diff --git a/arch/arm/mach-omap2/prcm_mpu54xx.h b/arch/arm/mach-omap2/prcm_mpu54xx.h
new file mode 100644
index 000000000000..bc2ce3288315
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu54xx.h
@@ -0,0 +1,87 @@
+/*
+ * OMAP54xx PRCM MPU instance offset macros
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
+
+#include "prcm_mpu_44xx_54xx.h"
+#include "common.h"
+
+#define OMAP54XX_PRCM_MPU_BASE                  0x48243000
+
+#define OMAP54XX_PRCM_MPU_REGADDR(inst, reg)                            \
+        OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg))
+
+/* PRCM_MPU instances */
+#define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST       0x0000
+#define OMAP54XX_PRCM_MPU_DEVICE_INST           0x0200
+#define OMAP54XX_PRCM_MPU_PRM_C0_INST           0x0400
+#define OMAP54XX_PRCM_MPU_CM_C0_INST            0x0600
+#define OMAP54XX_PRCM_MPU_PRM_C1_INST           0x0800
+#define OMAP54XX_PRCM_MPU_CM_C1_INST            0x0a00
+
+/* PRCM_MPU clockdomain register offsets (from instance start) */
+#define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS     0x0000
+#define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS     0x0000
+
+
+/*
+ * PRCM_MPU
+ *
+ * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
+ * point of view the PRCM_MPU is a single entity. It shares the same
+ * programming model as the global PRCM and thus can be assimilate as two new
+ * MOD inside the PRCM
+ */
+
+/* PRCM_MPU.PRCM_MPU_OCP_SOCKET register offsets */
+#define OMAP54XX_REVISION_PRCM_MPU_OFFSET                       0x0000
+
+/* PRCM_MPU.PRCM_MPU_DEVICE register offsets */
+#define OMAP54XX_PRCM_MPU_PRM_RSTST_OFFSET                      0x0000
+#define OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET                0x0004
+#define OMAP54XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET          0x0010
+#define OMAP54XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
+
+/* PRCM_MPU.PRCM_MPU_PRM_C0 register offsets */
+#define OMAP54XX_PM_CPU0_PWRSTCTRL_OFFSET                       0x0000
+#define OMAP54XX_PM_CPU0_PWRSTST_OFFSET                         0x0004
+#define OMAP54XX_RM_CPU0_CPU0_RSTCTRL_OFFSET                    0x0010
+#define OMAP54XX_RM_CPU0_CPU0_RSTST_OFFSET                      0x0014
+#define OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET                    0x0024
+
+/* PRCM_MPU.PRCM_MPU_CM_C0 register offsets */
+#define OMAP54XX_CM_CPU0_CLKSTCTRL_OFFSET                       0x0000
+#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL_OFFSET                    0x0020
+#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL                           OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C0_INST, 0x0020)
+
+/* PRCM_MPU.PRCM_MPU_PRM_C1 register offsets */
+#define OMAP54XX_PM_CPU1_PWRSTCTRL_OFFSET                       0x0000
+#define OMAP54XX_PM_CPU1_PWRSTST_OFFSET                         0x0004
+#define OMAP54XX_RM_CPU1_CPU1_RSTCTRL_OFFSET                    0x0010
+#define OMAP54XX_RM_CPU1_CPU1_RSTST_OFFSET                      0x0014
+#define OMAP54XX_RM_CPU1_CPU1_CONTEXT_OFFSET                    0x0024
+
+/* PRCM_MPU.PRCM_MPU_CM_C1 register offsets */
+#define OMAP54XX_CM_CPU1_CLKSTCTRL_OFFSET                       0x0000
+#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL_OFFSET                    0x0020
+#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL                           OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C1_INST, 0x0020)
+
+#endif
diff --git a/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
new file mode 100644
index 000000000000..ca149e70bed0
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
@@ -0,0 +1,36 @@
+/*
+ * OMAP44xx and OMAP54xx PRCM MPU function prototypes
+ *
+ * Copyright (C) 2010, 2013 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
+
+#ifndef __ASSEMBLER__
+extern void __iomem *prcm_mpu_base;
+
+extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
+                                            s16 idx);
+extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
+#endif
+
+#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-54xx.h b/arch/arm/mach-omap2/prm-regbits-54xx.h
new file mode 100644
index 000000000000..be31b21aa9c6
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-54xx.h
@@ -0,0 +1,2701 @@
+/*
+ * OMAP54xx Power Management register bits
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H
+
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ABBOFF_ACT_SHIFT                                               1
+#define OMAP54XX_ABBOFF_ACT_WIDTH                                               0x1
+#define OMAP54XX_ABBOFF_ACT_MASK                                                (1 << 1)
+
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ABBOFF_SLEEP_SHIFT                                             2
+#define OMAP54XX_ABBOFF_SLEEP_WIDTH                                             0x1
+#define OMAP54XX_ABBOFF_SLEEP_MASK                                              (1 << 2)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_ABB_MM_DONE_EN_SHIFT                                           31
+#define OMAP54XX_ABB_MM_DONE_EN_WIDTH                                           0x1
+#define OMAP54XX_ABB_MM_DONE_EN_MASK                                            (1 << 31)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_ABB_MM_DONE_ST_SHIFT                                           31
+#define OMAP54XX_ABB_MM_DONE_ST_WIDTH                                           0x1
+#define OMAP54XX_ABB_MM_DONE_ST_MASK                                            (1 << 31)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_ABB_MPU_DONE_EN_SHIFT                                          7
+#define OMAP54XX_ABB_MPU_DONE_EN_WIDTH                                          0x1
+#define OMAP54XX_ABB_MPU_DONE_EN_MASK                                           (1 << 7)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_ABB_MPU_DONE_ST_SHIFT                                          7
+#define OMAP54XX_ABB_MPU_DONE_ST_WIDTH                                          0x1
+#define OMAP54XX_ABB_MPU_DONE_ST_MASK                                           (1 << 7)
+
+/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
+#define OMAP54XX_ACTIVE_FBB_SEL_SHIFT                                           2
+#define OMAP54XX_ACTIVE_FBB_SEL_WIDTH                                           0x1
+#define OMAP54XX_ACTIVE_FBB_SEL_MASK                                            (1 << 2)
+
+/* Used by PM_ABE_PWRSTCTRL */
+#define OMAP54XX_AESSMEM_ONSTATE_SHIFT                                          16
+#define OMAP54XX_AESSMEM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_AESSMEM_ONSTATE_MASK                                           (0x3 << 16)
+
+/* Used by PM_ABE_PWRSTCTRL */
+#define OMAP54XX_AESSMEM_RETSTATE_SHIFT                                         8
+#define OMAP54XX_AESSMEM_RETSTATE_WIDTH                                         0x1
+#define OMAP54XX_AESSMEM_RETSTATE_MASK                                          (1 << 8)
+
+/* Used by PM_ABE_PWRSTST */
+#define OMAP54XX_AESSMEM_STATEST_SHIFT                                          4
+#define OMAP54XX_AESSMEM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_AESSMEM_STATEST_MASK                                           (0x3 << 4)
+
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_AIPOFF_SHIFT                                                   8
+#define OMAP54XX_AIPOFF_WIDTH                                                   0x1
+#define OMAP54XX_AIPOFF_MASK                                                    (1 << 8)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_SHIFT                                     0
+#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_WIDTH                                     0x2
+#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_MASK                                      (0x3 << 0)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_AUTO_CTRL_VDD_MM_L_SHIFT                                       4
+#define OMAP54XX_AUTO_CTRL_VDD_MM_L_WIDTH                                       0x2
+#define OMAP54XX_AUTO_CTRL_VDD_MM_L_MASK                                        (0x3 << 4)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_SHIFT                                      2
+#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_WIDTH                                      0x2
+#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_MASK                                       (0x3 << 2)
+
+/* Used by PRM_VC_BYPASS_ERRST */
+#define OMAP54XX_BYPS_RA_ERR_SHIFT                                              1
+#define OMAP54XX_BYPS_RA_ERR_WIDTH                                              0x1
+#define OMAP54XX_BYPS_RA_ERR_MASK                                               (1 << 1)
+
+/* Used by PRM_VC_BYPASS_ERRST */
+#define OMAP54XX_BYPS_SA_ERR_SHIFT                                              0
+#define OMAP54XX_BYPS_SA_ERR_WIDTH                                              0x1
+#define OMAP54XX_BYPS_SA_ERR_MASK                                               (1 << 0)
+
+/* Used by PRM_VC_BYPASS_ERRST */
+#define OMAP54XX_BYPS_TIMEOUT_ERR_SHIFT                                         2
+#define OMAP54XX_BYPS_TIMEOUT_ERR_WIDTH                                         0x1
+#define OMAP54XX_BYPS_TIMEOUT_ERR_MASK                                          (1 << 2)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_C2C_RST_SHIFT                                                  10
+#define OMAP54XX_C2C_RST_WIDTH                                                  0x1
+#define OMAP54XX_C2C_RST_MASK                                                   (1 << 10)
+
+/* Used by PM_CAM_PWRSTCTRL */
+#define OMAP54XX_CAM_MEM_ONSTATE_SHIFT                                          16
+#define OMAP54XX_CAM_MEM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_CAM_MEM_ONSTATE_MASK                                           (0x3 << 16)
+
+/* Used by PM_CAM_PWRSTST */
+#define OMAP54XX_CAM_MEM_STATEST_SHIFT                                          4
+#define OMAP54XX_CAM_MEM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_CAM_MEM_STATEST_MASK                                           (0x3 << 4)
+
+/* Used by PRM_CLKREQCTRL */
+#define OMAP54XX_CLKREQ_COND_SHIFT                                              0
+#define OMAP54XX_CLKREQ_COND_WIDTH                                              0x3
+#define OMAP54XX_CLKREQ_COND_MASK                                               (0x7 << 0)
+
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_CMDRA_VDD_CORE_L_SHIFT                                         16
+#define OMAP54XX_CMDRA_VDD_CORE_L_WIDTH                                         0x8
+#define OMAP54XX_CMDRA_VDD_CORE_L_MASK                                          (0xff << 16)
+
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_CMDRA_VDD_MM_L_SHIFT                                           16
+#define OMAP54XX_CMDRA_VDD_MM_L_WIDTH                                           0x8
+#define OMAP54XX_CMDRA_VDD_MM_L_MASK                                            (0xff << 16)
+
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_CMDRA_VDD_MPU_L_SHIFT                                          16
+#define OMAP54XX_CMDRA_VDD_MPU_L_WIDTH                                          0x8
+#define OMAP54XX_CMDRA_VDD_MPU_L_MASK                                           (0xff << 16)
+
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_CMD_VDD_CORE_L_SHIFT                                           28
+#define OMAP54XX_CMD_VDD_CORE_L_WIDTH                                           0x1
+#define OMAP54XX_CMD_VDD_CORE_L_MASK                                            (1 << 28)
+
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_CMD_VDD_MM_L_SHIFT                                             28
+#define OMAP54XX_CMD_VDD_MM_L_WIDTH                                             0x1
+#define OMAP54XX_CMD_VDD_MM_L_MASK                                              (1 << 28)
+
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_CMD_VDD_MPU_L_SHIFT                                            28
+#define OMAP54XX_CMD_VDD_MPU_L_WIDTH                                            0x1
+#define OMAP54XX_CMD_VDD_MPU_L_MASK                                             (1 << 28)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_CORE_OCMRAM_ONSTATE_SHIFT                                      18
+#define OMAP54XX_CORE_OCMRAM_ONSTATE_WIDTH                                      0x2
+#define OMAP54XX_CORE_OCMRAM_ONSTATE_MASK                                       (0x3 << 18)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_CORE_OCMRAM_RETSTATE_SHIFT                                     9
+#define OMAP54XX_CORE_OCMRAM_RETSTATE_WIDTH                                     0x1
+#define OMAP54XX_CORE_OCMRAM_RETSTATE_MASK                                      (1 << 9)
+
+/* Used by PM_CORE_PWRSTST */
+#define OMAP54XX_CORE_OCMRAM_STATEST_SHIFT                                      6
+#define OMAP54XX_CORE_OCMRAM_STATEST_WIDTH                                      0x2
+#define OMAP54XX_CORE_OCMRAM_STATEST_MASK                                       (0x3 << 6)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_SHIFT                                  16
+#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_WIDTH                                  0x2
+#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_MASK                                   (0x3 << 16)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_SHIFT                                 8
+#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_WIDTH                                 0x1
+#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_MASK                                  (1 << 8)
+
+/* Used by PM_CORE_PWRSTST */
+#define OMAP54XX_CORE_OTHER_BANK_STATEST_SHIFT                                  4
+#define OMAP54XX_CORE_OTHER_BANK_STATEST_WIDTH                                  0x2
+#define OMAP54XX_CORE_OTHER_BANK_STATEST_MASK                                   (0x3 << 4)
+
+/* Used by REVISION_PRM */
+#define OMAP54XX_CUSTOM_SHIFT                                                   6
+#define OMAP54XX_CUSTOM_WIDTH                                                   0x2
+#define OMAP54XX_CUSTOM_MASK                                                    (0x3 << 6)
+
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP54XX_DATA_SHIFT                                                     16
+#define OMAP54XX_DATA_WIDTH                                                     0x8
+#define OMAP54XX_DATA_MASK                                                      (0xff << 16)
+
+/* Used by PRM_DEBUG_CORE_RET_TRANS */
+#define OMAP54XX_PRM_DEBUG_OUT_SHIFT                                            0
+#define OMAP54XX_PRM_DEBUG_OUT_WIDTH                                            0x1c
+#define OMAP54XX_PRM_DEBUG_OUT_MASK                                             (0xfffffff << 0)
+
+/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MM_RET_TRANS */
+#define OMAP54XX_DEBUG_OUT_0_9_SHIFT                                            0
+#define OMAP54XX_DEBUG_OUT_0_9_WIDTH                                            0xa
+#define OMAP54XX_DEBUG_OUT_0_9_MASK                                             (0x3ff << 0)
+
+/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MPU_RET_TRANS */
+#define OMAP54XX_DEBUG_OUT_0_6_SHIFT                                            0
+#define OMAP54XX_DEBUG_OUT_0_6_WIDTH                                            0x7
+#define OMAP54XX_DEBUG_OUT_0_6_MASK                                             (0x7f << 0)
+
+/* Renamed from DEBUG_OUT Used by PRM_DEBUG_OFF_TRANS */
+#define OMAP54XX_DEBUG_OUT_0_31_SHIFT                                           0
+#define OMAP54XX_DEBUG_OUT_0_31_WIDTH                                           0x20
+#define OMAP54XX_DEBUG_OUT_0_31_MASK                                            (0xffffffff << 0)
+
+/* Renamed from DEBUG_OUT Used by PRM_DEBUG_WKUPAON_FD_TRANS */
+#define OMAP54XX_DEBUG_OUT_0_11_SHIFT                                           0
+#define OMAP54XX_DEBUG_OUT_0_11_WIDTH                                           0xc
+#define OMAP54XX_DEBUG_OUT_0_11_MASK                                            (0xfff << 0)
+
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define OMAP54XX_DEVICE_OFF_ENABLE_SHIFT                                        0
+#define OMAP54XX_DEVICE_OFF_ENABLE_WIDTH                                        0x1
+#define OMAP54XX_DEVICE_OFF_ENABLE_MASK                                         (1 << 0)
+
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP54XX_DFILTEREN_SHIFT                                                6
+#define OMAP54XX_DFILTEREN_WIDTH                                                0x1
+#define OMAP54XX_DFILTEREN_MASK                                                 (1 << 6)
+
+/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_DPLL_ABE_RECAL_EN_SHIFT                                        4
+#define OMAP54XX_DPLL_ABE_RECAL_EN_WIDTH                                        0x1
+#define OMAP54XX_DPLL_ABE_RECAL_EN_MASK                                         (1 << 4)
+
+/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_DPLL_ABE_RECAL_ST_SHIFT                                        4
+#define OMAP54XX_DPLL_ABE_RECAL_ST_WIDTH                                        0x1
+#define OMAP54XX_DPLL_ABE_RECAL_ST_MASK                                         (1 << 4)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_DPLL_CORE_RECAL_EN_SHIFT                                       0
+#define OMAP54XX_DPLL_CORE_RECAL_EN_WIDTH                                       0x1
+#define OMAP54XX_DPLL_CORE_RECAL_EN_MASK                                        (1 << 0)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_DPLL_CORE_RECAL_ST_SHIFT                                       0
+#define OMAP54XX_DPLL_CORE_RECAL_ST_WIDTH                                       0x1
+#define OMAP54XX_DPLL_CORE_RECAL_ST_MASK                                        (1 << 0)
+
+/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_DPLL_IVA_RECAL_EN_SHIFT                                        2
+#define OMAP54XX_DPLL_IVA_RECAL_EN_WIDTH                                        0x1
+#define OMAP54XX_DPLL_IVA_RECAL_EN_MASK                                         (1 << 2)
+
+/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_DPLL_IVA_RECAL_ST_SHIFT                                        2
+#define OMAP54XX_DPLL_IVA_RECAL_ST_WIDTH                                        0x1
+#define OMAP54XX_DPLL_IVA_RECAL_ST_MASK                                         (1 << 2)
+
+/* Used by PRM_IRQENABLE_MPU */
+#define OMAP54XX_DPLL_MPU_RECAL_EN_SHIFT                                        1
+#define OMAP54XX_DPLL_MPU_RECAL_EN_WIDTH                                        0x1
+#define OMAP54XX_DPLL_MPU_RECAL_EN_MASK                                         (1 << 1)
+
+/* Used by PRM_IRQSTATUS_MPU */
+#define OMAP54XX_DPLL_MPU_RECAL_ST_SHIFT                                        1
+#define OMAP54XX_DPLL_MPU_RECAL_ST_WIDTH                                        0x1
+#define OMAP54XX_DPLL_MPU_RECAL_ST_MASK                                         (1 << 1)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_DPLL_PER_RECAL_EN_SHIFT                                        3
+#define OMAP54XX_DPLL_PER_RECAL_EN_WIDTH                                        0x1
+#define OMAP54XX_DPLL_PER_RECAL_EN_MASK                                         (1 << 3)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_DPLL_PER_RECAL_ST_SHIFT                                        3
+#define OMAP54XX_DPLL_PER_RECAL_ST_WIDTH                                        0x1
+#define OMAP54XX_DPLL_PER_RECAL_ST_MASK                                         (1 << 3)
+
+/* Used by PM_DSP_PWRSTCTRL */
+#define OMAP54XX_DSP_EDMA_ONSTATE_SHIFT                                         20
+#define OMAP54XX_DSP_EDMA_ONSTATE_WIDTH                                         0x2
+#define OMAP54XX_DSP_EDMA_ONSTATE_MASK                                          (0x3 << 20)
+
+/* Used by PM_DSP_PWRSTCTRL */
+#define OMAP54XX_DSP_EDMA_RETSTATE_SHIFT                                        10
+#define OMAP54XX_DSP_EDMA_RETSTATE_WIDTH                                        0x1
+#define OMAP54XX_DSP_EDMA_RETSTATE_MASK                                         (1 << 10)
+
+/* Used by PM_DSP_PWRSTST */
+#define OMAP54XX_DSP_EDMA_STATEST_SHIFT                                         8
+#define OMAP54XX_DSP_EDMA_STATEST_WIDTH                                         0x2
+#define OMAP54XX_DSP_EDMA_STATEST_MASK                                          (0x3 << 8)
+
+/* Used by PM_DSP_PWRSTCTRL */
+#define OMAP54XX_DSP_L1_ONSTATE_SHIFT                                           16
+#define OMAP54XX_DSP_L1_ONSTATE_WIDTH                                           0x2
+#define OMAP54XX_DSP_L1_ONSTATE_MASK                                            (0x3 << 16)
+
+/* Used by PM_DSP_PWRSTCTRL */
+#define OMAP54XX_DSP_L1_RETSTATE_SHIFT                                          8
+#define OMAP54XX_DSP_L1_RETSTATE_WIDTH                                          0x1
+#define OMAP54XX_DSP_L1_RETSTATE_MASK                                           (1 << 8)
+
+/* Used by PM_DSP_PWRSTST */
+#define OMAP54XX_DSP_L1_STATEST_SHIFT                                           4
+#define OMAP54XX_DSP_L1_STATEST_WIDTH                                           0x2
+#define OMAP54XX_DSP_L1_STATEST_MASK                                            (0x3 << 4)
+
+/* Used by PM_DSP_PWRSTCTRL */
+#define OMAP54XX_DSP_L2_ONSTATE_SHIFT                                           18
+#define OMAP54XX_DSP_L2_ONSTATE_WIDTH                                           0x2
+#define OMAP54XX_DSP_L2_ONSTATE_MASK                                            (0x3 << 18)
+
+/* Used by PM_DSP_PWRSTCTRL */
+#define OMAP54XX_DSP_L2_RETSTATE_SHIFT                                          9
+#define OMAP54XX_DSP_L2_RETSTATE_WIDTH                                          0x1
+#define OMAP54XX_DSP_L2_RETSTATE_MASK                                           (1 << 9)
+
+/* Used by PM_DSP_PWRSTST */
+#define OMAP54XX_DSP_L2_STATEST_SHIFT                                           6
+#define OMAP54XX_DSP_L2_STATEST_WIDTH                                           0x2
+#define OMAP54XX_DSP_L2_STATEST_MASK                                            (0x3 << 6)
+
+/* Used by PM_DSS_PWRSTCTRL */
+#define OMAP54XX_DSS_MEM_ONSTATE_SHIFT                                          16
+#define OMAP54XX_DSS_MEM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_DSS_MEM_ONSTATE_MASK                                           (0x3 << 16)
+
+/* Used by PM_DSS_PWRSTCTRL */
+#define OMAP54XX_DSS_MEM_RETSTATE_SHIFT                                         8
+#define OMAP54XX_DSS_MEM_RETSTATE_WIDTH                                         0x1
+#define OMAP54XX_DSS_MEM_RETSTATE_MASK                                          (1 << 8)
+
+/* Used by PM_DSS_PWRSTST */
+#define OMAP54XX_DSS_MEM_STATEST_SHIFT                                          4
+#define OMAP54XX_DSS_MEM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_DSS_MEM_STATEST_MASK                                           (0x3 << 4)
+
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_SHIFT                                    8
+#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_WIDTH                                    0x1
+#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_MASK                                     (1 << 8)
+
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_SHIFT                                    9
+#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_WIDTH                                    0x1
+#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_MASK                                     (1 << 9)
+
+/* Used by PM_EMU_PWRSTCTRL */
+#define OMAP54XX_EMU_BANK_ONSTATE_SHIFT                                         16
+#define OMAP54XX_EMU_BANK_ONSTATE_WIDTH                                         0x2
+#define OMAP54XX_EMU_BANK_ONSTATE_MASK                                          (0x3 << 16)
+
+/* Used by PM_EMU_PWRSTST */
+#define OMAP54XX_EMU_BANK_STATEST_SHIFT                                         4
+#define OMAP54XX_EMU_BANK_STATEST_WIDTH                                         0x2
+#define OMAP54XX_EMU_BANK_STATEST_MASK                                          (0x3 << 4)
+
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP,
+ * PRM_SRAM_WKUP_SETUP
+ */
+#define OMAP54XX_ENABLE_RTA_SHIFT                                               0
+#define OMAP54XX_ENABLE_RTA_WIDTH                                               0x1
+#define OMAP54XX_ENABLE_RTA_MASK                                                (1 << 0)
+
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ENFUNC1_SHIFT                                                  3
+#define OMAP54XX_ENFUNC1_WIDTH                                                  0x1
+#define OMAP54XX_ENFUNC1_MASK                                                   (1 << 3)
+
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ENFUNC2_SHIFT                                                  4
+#define OMAP54XX_ENFUNC2_WIDTH                                                  0x1
+#define OMAP54XX_ENFUNC2_MASK                                                   (1 << 4)
+
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ENFUNC3_SHIFT                                                  5
+#define OMAP54XX_ENFUNC3_WIDTH                                                  0x1
+#define OMAP54XX_ENFUNC3_MASK                                                   (1 << 5)
+
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ENFUNC4_SHIFT                                                  6
+#define OMAP54XX_ENFUNC4_WIDTH                                                  0x1
+#define OMAP54XX_ENFUNC4_MASK                                                   (1 << 6)
+
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ENFUNC5_SHIFT                                                  7
+#define OMAP54XX_ENFUNC5_WIDTH                                                  0x1
+#define OMAP54XX_ENFUNC5_MASK                                                   (1 << 7)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_ERRORGAIN_SHIFT                                                16
+#define OMAP54XX_ERRORGAIN_WIDTH                                                0x8
+#define OMAP54XX_ERRORGAIN_MASK                                                 (0xff << 16)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_ERROROFFSET_SHIFT                                              24
+#define OMAP54XX_ERROROFFSET_WIDTH                                              0x8
+#define OMAP54XX_ERROROFFSET_MASK                                               (0xff << 24)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_EXTERNAL_WARM_RST_SHIFT                                        5
+#define OMAP54XX_EXTERNAL_WARM_RST_WIDTH                                        0x1
+#define OMAP54XX_EXTERNAL_WARM_RST_MASK                                         (1 << 5)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_FORCEUPDATE_SHIFT                                              1
+#define OMAP54XX_FORCEUPDATE_WIDTH                                              0x1
+#define OMAP54XX_FORCEUPDATE_MASK                                               (1 << 1)
+
+/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */
+#define OMAP54XX_FORCEUPDATEWAIT_SHIFT                                          8
+#define OMAP54XX_FORCEUPDATEWAIT_WIDTH                                          0x18
+#define OMAP54XX_FORCEUPDATEWAIT_MASK                                           (0xffffff << 8)
+
+/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU */
+#define OMAP54XX_FORCEWKUP_EN_SHIFT                                             10
+#define OMAP54XX_FORCEWKUP_EN_WIDTH                                             0x1
+#define OMAP54XX_FORCEWKUP_EN_MASK                                              (1 << 10)
+
+/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU */
+#define OMAP54XX_FORCEWKUP_ST_SHIFT                                             10
+#define OMAP54XX_FORCEWKUP_ST_WIDTH                                             0x1
+#define OMAP54XX_FORCEWKUP_ST_MASK                                              (1 << 10)
+
+/* Used by REVISION_PRM */
+#define OMAP54XX_FUNC_SHIFT                                                     16
+#define OMAP54XX_FUNC_WIDTH                                                     0xc
+#define OMAP54XX_FUNC_MASK                                                      (0xfff << 16)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_GLOBAL_COLD_RST_SHIFT                                          0
+#define OMAP54XX_GLOBAL_COLD_RST_WIDTH                                          0x1
+#define OMAP54XX_GLOBAL_COLD_RST_MASK                                           (1 << 0)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_GLOBAL_WARM_SW_RST_SHIFT                                       1
+#define OMAP54XX_GLOBAL_WARM_SW_RST_WIDTH                                       0x1
+#define OMAP54XX_GLOBAL_WARM_SW_RST_MASK                                        (1 << 1)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_GLOBAL_WUEN_SHIFT                                              16
+#define OMAP54XX_GLOBAL_WUEN_WIDTH                                              0x1
+#define OMAP54XX_GLOBAL_WUEN_MASK                                               (1 << 16)
+
+/* Used by PM_GPU_PWRSTCTRL */
+#define OMAP54XX_GPU_MEM_ONSTATE_SHIFT                                          16
+#define OMAP54XX_GPU_MEM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_GPU_MEM_ONSTATE_MASK                                           (0x3 << 16)
+
+/* Used by PM_GPU_PWRSTST */
+#define OMAP54XX_GPU_MEM_STATEST_SHIFT                                          4
+#define OMAP54XX_GPU_MEM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_GPU_MEM_STATEST_MASK                                           (0x3 << 4)
+
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP54XX_HSMCODE_SHIFT                                                  0
+#define OMAP54XX_HSMCODE_WIDTH                                                  0x3
+#define OMAP54XX_HSMCODE_MASK                                                   (0x7 << 0)
+
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP54XX_HSMODEEN_SHIFT                                                 3
+#define OMAP54XX_HSMODEEN_WIDTH                                                 0x1
+#define OMAP54XX_HSMODEEN_MASK                                                  (1 << 3)
+
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP54XX_HSSCLH_SHIFT                                                   16
+#define OMAP54XX_HSSCLH_WIDTH                                                   0x8
+#define OMAP54XX_HSSCLH_MASK                                                    (0xff << 16)
+
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP54XX_HSSCLL_SHIFT                                                   24
+#define OMAP54XX_HSSCLL_WIDTH                                                   0x8
+#define OMAP54XX_HSSCLL_MASK                                                    (0xff << 24)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_HWA_MEM_ONSTATE_SHIFT                                          16
+#define OMAP54XX_HWA_MEM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_HWA_MEM_ONSTATE_MASK                                           (0x3 << 16)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_HWA_MEM_RETSTATE_SHIFT                                         8
+#define OMAP54XX_HWA_MEM_RETSTATE_WIDTH                                         0x1
+#define OMAP54XX_HWA_MEM_RETSTATE_MASK                                          (1 << 8)
+
+/* Used by PM_IVA_PWRSTST */
+#define OMAP54XX_HWA_MEM_STATEST_SHIFT                                          4
+#define OMAP54XX_HWA_MEM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_HWA_MEM_STATEST_MASK                                           (0x3 << 4)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_ICEPICK_RST_SHIFT                                              9
+#define OMAP54XX_ICEPICK_RST_WIDTH                                              0x1
+#define OMAP54XX_ICEPICK_RST_MASK                                               (1 << 9)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_INITVDD_SHIFT                                                  2
+#define OMAP54XX_INITVDD_WIDTH                                                  0x1
+#define OMAP54XX_INITVDD_MASK                                                   (1 << 2)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_INITVOLTAGE_SHIFT                                              8
+#define OMAP54XX_INITVOLTAGE_WIDTH                                              0x8
+#define OMAP54XX_INITVOLTAGE_MASK                                               (0xff << 8)
+
+/*
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
+ * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
+ * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST,
+ * PRM_VOLTST_MM, PRM_VOLTST_MPU
+ */
+#define OMAP54XX_INTRANSITION_SHIFT                                             20
+#define OMAP54XX_INTRANSITION_WIDTH                                             0x1
+#define OMAP54XX_INTRANSITION_MASK                                              (1 << 20)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_IO_EN_SHIFT                                                    9
+#define OMAP54XX_IO_EN_WIDTH                                                    0x1
+#define OMAP54XX_IO_EN_MASK                                                     (1 << 9)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_IO_ON_STATUS_SHIFT                                             5
+#define OMAP54XX_IO_ON_STATUS_WIDTH                                             0x1
+#define OMAP54XX_IO_ON_STATUS_MASK                                              (1 << 5)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_IO_ST_SHIFT                                                    9
+#define OMAP54XX_IO_ST_WIDTH                                                    0x1
+#define OMAP54XX_IO_ST_MASK                                                     (1 << 9)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_IPU_L2RAM_ONSTATE_SHIFT                                        20
+#define OMAP54XX_IPU_L2RAM_ONSTATE_WIDTH                                        0x2
+#define OMAP54XX_IPU_L2RAM_ONSTATE_MASK                                         (0x3 << 20)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_IPU_L2RAM_RETSTATE_SHIFT                                       10
+#define OMAP54XX_IPU_L2RAM_RETSTATE_WIDTH                                       0x1
+#define OMAP54XX_IPU_L2RAM_RETSTATE_MASK                                        (1 << 10)
+
+/* Used by PM_CORE_PWRSTST */
+#define OMAP54XX_IPU_L2RAM_STATEST_SHIFT                                        8
+#define OMAP54XX_IPU_L2RAM_STATEST_WIDTH                                        0x2
+#define OMAP54XX_IPU_L2RAM_STATEST_MASK                                         (0x3 << 8)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_IPU_UNICACHE_ONSTATE_SHIFT                                     22
+#define OMAP54XX_IPU_UNICACHE_ONSTATE_WIDTH                                     0x2
+#define OMAP54XX_IPU_UNICACHE_ONSTATE_MASK                                      (0x3 << 22)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_IPU_UNICACHE_RETSTATE_SHIFT                                    11
+#define OMAP54XX_IPU_UNICACHE_RETSTATE_WIDTH                                    0x1
+#define OMAP54XX_IPU_UNICACHE_RETSTATE_MASK                                     (1 << 11)
+
+/* Used by PM_CORE_PWRSTST */
+#define OMAP54XX_IPU_UNICACHE_STATEST_SHIFT                                     10
+#define OMAP54XX_IPU_UNICACHE_STATEST_WIDTH                                     0x2
+#define OMAP54XX_IPU_UNICACHE_STATEST_MASK                                      (0x3 << 10)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_ISOCLK_OVERRIDE_SHIFT                                          0
+#define OMAP54XX_ISOCLK_OVERRIDE_WIDTH                                          0x1
+#define OMAP54XX_ISOCLK_OVERRIDE_MASK                                           (1 << 0)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_ISOCLK_STATUS_SHIFT                                            1
+#define OMAP54XX_ISOCLK_STATUS_WIDTH                                            0x1
+#define OMAP54XX_ISOCLK_STATUS_MASK                                             (1 << 1)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_ISOOVR_EXTEND_SHIFT                                            4
+#define OMAP54XX_ISOOVR_EXTEND_WIDTH                                            0x1
+#define OMAP54XX_ISOOVR_EXTEND_MASK                                             (1 << 4)
+
+/* Used by PRM_IO_COUNT */
+#define OMAP54XX_ISO_2_ON_TIME_SHIFT                                            0
+#define OMAP54XX_ISO_2_ON_TIME_WIDTH                                            0x8
+#define OMAP54XX_ISO_2_ON_TIME_MASK                                             (0xff << 0)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define OMAP54XX_L3INIT_BANK1_ONSTATE_SHIFT                                     16
+#define OMAP54XX_L3INIT_BANK1_ONSTATE_WIDTH                                     0x2
+#define OMAP54XX_L3INIT_BANK1_ONSTATE_MASK                                      (0x3 << 16)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define OMAP54XX_L3INIT_BANK1_RETSTATE_SHIFT                                    8
+#define OMAP54XX_L3INIT_BANK1_RETSTATE_WIDTH                                    0x1
+#define OMAP54XX_L3INIT_BANK1_RETSTATE_MASK                                     (1 << 8)
+
+/* Used by PM_L3INIT_PWRSTST */
+#define OMAP54XX_L3INIT_BANK1_STATEST_SHIFT                                     4
+#define OMAP54XX_L3INIT_BANK1_STATEST_WIDTH                                     0x2
+#define OMAP54XX_L3INIT_BANK1_STATEST_MASK                                      (0x3 << 4)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define OMAP54XX_L3INIT_BANK2_ONSTATE_SHIFT                                     18
+#define OMAP54XX_L3INIT_BANK2_ONSTATE_WIDTH                                     0x2
+#define OMAP54XX_L3INIT_BANK2_ONSTATE_MASK                                      (0x3 << 18)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define OMAP54XX_L3INIT_BANK2_RETSTATE_SHIFT                                    9
+#define OMAP54XX_L3INIT_BANK2_RETSTATE_WIDTH                                    0x1
+#define OMAP54XX_L3INIT_BANK2_RETSTATE_MASK                                     (1 << 9)
+
+/* Used by PM_L3INIT_PWRSTST */
+#define OMAP54XX_L3INIT_BANK2_STATEST_SHIFT                                     6
+#define OMAP54XX_L3INIT_BANK2_STATEST_WIDTH                                     0x2
+#define OMAP54XX_L3INIT_BANK2_STATEST_MASK                                      (0x3 << 6)
+
+/*
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
+ * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
+ * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
+ */
+#define OMAP54XX_LASTPOWERSTATEENTERED_SHIFT                                    24
+#define OMAP54XX_LASTPOWERSTATEENTERED_WIDTH                                    0x2
+#define OMAP54XX_LASTPOWERSTATEENTERED_MASK                                     (0x3 << 24)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_LLI_RST_SHIFT                                                  14
+#define OMAP54XX_LLI_RST_WIDTH                                                  0x1
+#define OMAP54XX_LLI_RST_MASK                                                   (1 << 14)
+
+/*
+ * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSP_PWRSTCTRL,
+ * PM_DSS_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL
+ */
+#define OMAP54XX_LOGICRETSTATE_SHIFT                                            2
+#define OMAP54XX_LOGICRETSTATE_WIDTH                                            0x1
+#define OMAP54XX_LOGICRETSTATE_MASK                                             (1 << 2)
+
+/*
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
+ * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
+ * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
+ */
+#define OMAP54XX_LOGICSTATEST_SHIFT                                             2
+#define OMAP54XX_LOGICSTATEST_WIDTH                                             0x1
+#define OMAP54XX_LOGICSTATEST_MASK                                              (1 << 2)
+
+/*
+ * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
+ * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
+ * RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT, RM_ABE_TIMER5_CONTEXT,
+ * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
+ * RM_ABE_WD_TIMER3_CONTEXT, RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT,
+ * RM_CAM_CAL_CONTEXT, RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT,
+ * RM_COREAON_SMARTREFLEX_CORE_CONTEXT, RM_COREAON_SMARTREFLEX_MM_CONTEXT,
+ * RM_COREAON_SMARTREFLEX_MPU_CONTEXT, RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT,
+ * RM_DSP_DSP_CONTEXT, RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT,
+ * RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, RM_EMIF_EMIF2_CONTEXT,
+ * RM_EMIF_EMIF_DLL_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT,
+ * RM_EMU_DEBUGSS_CONTEXT, RM_GPU_GPU_CONTEXT, RM_IPU_IPU_CONTEXT,
+ * RM_IVA_IVA_CONTEXT, RM_IVA_SL2_CONTEXT, RM_L3INIT_IEEE1500_2_OCP_CONTEXT,
+ * RM_L3INIT_OCP2SCP1_CONTEXT, RM_L3INIT_OCP2SCP3_CONTEXT,
+ * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT,
+ * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT,
+ * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT,
+ * RM_L3MAIN2_L3_MAIN_2_CONTEXT, RM_L3MAIN2_OCMC_RAM_CONTEXT,
+ * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_OCP2SCP2_CONTEXT,
+ * RM_L4CFG_SAR_ROM_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT,
+ * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT,
+ * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCSPI1_CONTEXT,
+ * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT,
+ * RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT,
+ * RM_L4PER_TIMER10_CONTEXT, RM_L4PER_TIMER11_CONTEXT, RM_L4PER_TIMER2_CONTEXT,
+ * RM_L4PER_TIMER3_CONTEXT, RM_L4PER_TIMER4_CONTEXT, RM_L4PER_TIMER9_CONTEXT,
+ * RM_L4SEC_FPKA_CONTEXT, RM_MIPIEXT_LLI_CONTEXT,
+ * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT,
+ * RM_WKUPAON_COUNTER_32K_CONTEXT, RM_WKUPAON_GPIO1_CONTEXT,
+ * RM_WKUPAON_KBD_CONTEXT, RM_WKUPAON_L4_WKUP_CONTEXT,
+ * RM_WKUPAON_SAR_RAM_CONTEXT, RM_WKUPAON_TIMER12_CONTEXT,
+ * RM_WKUPAON_TIMER1_CONTEXT, RM_WKUPAON_WD_TIMER1_CONTEXT,
+ * RM_WKUPAON_WD_TIMER2_CONTEXT
+ */
+#define OMAP54XX_LOSTCONTEXT_DFF_SHIFT                                          0
+#define OMAP54XX_LOSTCONTEXT_DFF_WIDTH                                          0x1
+#define OMAP54XX_LOSTCONTEXT_DFF_MASK                                           (1 << 0)
+
+/*
+ * Used by RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT,
+ * RM_C2C_MODEM_ICR_CONTEXT, RM_DMA_DMA_SYSTEM_CONTEXT, RM_DSP_DSP_CONTEXT,
+ * RM_DSS_DSS_CONTEXT, RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT,
+ * RM_EMIF_EMIF2_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, RM_IPU_IPU_CONTEXT,
+ * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
+ * RM_L3INIT_USB_HOST_HS_CONTEXT, RM_L3INIT_USB_OTG_SS_CONTEXT,
+ * RM_L3INIT_USB_TLL_HS_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT,
+ * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT,
+ * RM_L3MAIN2_GPMC_CONTEXT, RM_L3MAIN2_L3_MAIN_2_CONTEXT,
+ * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_MAILBOX_CONTEXT,
+ * RM_L4CFG_SPINLOCK_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT,
+ * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT,
+ * RM_L4PER_GPIO7_CONTEXT, RM_L4PER_GPIO8_CONTEXT, RM_L4PER_I2C1_CONTEXT,
+ * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT,
+ * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT,
+ * RM_L4PER_UART6_CONTEXT, RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT,
+ * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT, RM_L4SEC_RNG_CONTEXT,
+ * RM_L4SEC_SHA2MD5_CONTEXT, RM_MIPIEXT_LLI_CONTEXT,
+ * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT
+ */
+#define OMAP54XX_LOSTCONTEXT_RFF_SHIFT                                          1
+#define OMAP54XX_LOSTCONTEXT_RFF_WIDTH                                          0x1
+#define OMAP54XX_LOSTCONTEXT_RFF_MASK                                           (1 << 1)
+
+/* Used by RM_ABE_AESS_CONTEXT */
+#define OMAP54XX_LOSTMEM_AESSMEM_SHIFT                                          8
+#define OMAP54XX_LOSTMEM_AESSMEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_AESSMEM_MASK                                           (1 << 8)
+
+/* Used by RM_CAM_CAL_CONTEXT */
+#define OMAP54XX_LOSTMEM_CAL_MEM_SHIFT                                          8
+#define OMAP54XX_LOSTMEM_CAL_MEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_CAL_MEM_MASK                                           (1 << 8)
+
+/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
+#define OMAP54XX_LOSTMEM_CAM_MEM_SHIFT                                          8
+#define OMAP54XX_LOSTMEM_CAM_MEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_CAM_MEM_MASK                                           (1 << 8)
+
+/* Used by RM_EMIF_DMM_CONTEXT */
+#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_SHIFT                                   9
+#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_WIDTH                                   0x1
+#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_MASK                                    (1 << 9)
+
+/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_L3INSTR_OCP_WP_NOC_CONTEXT */
+#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_SHIFT                               8
+#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_WIDTH                               0x1
+#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_MASK                                (1 << 8)
+
+/* Used by RM_L3MAIN2_OCMC_RAM_CONTEXT */
+#define OMAP54XX_LOSTMEM_CORE_OCMRAM_SHIFT                                      8
+#define OMAP54XX_LOSTMEM_CORE_OCMRAM_WIDTH                                      0x1
+#define OMAP54XX_LOSTMEM_CORE_OCMRAM_MASK                                       (1 << 8)
+
+/* Used by RM_DMA_DMA_SYSTEM_CONTEXT, RM_EMIF_DMM_CONTEXT */
+#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_SHIFT                                  8
+#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_WIDTH                                  0x1
+#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_MASK                                   (1 << 8)
+
+/* Used by RM_DSP_DSP_CONTEXT */
+#define OMAP54XX_LOSTMEM_DSP_EDMA_SHIFT                                         10
+#define OMAP54XX_LOSTMEM_DSP_EDMA_WIDTH                                         0x1
+#define OMAP54XX_LOSTMEM_DSP_EDMA_MASK                                          (1 << 10)
+
+/* Used by RM_DSP_DSP_CONTEXT */
+#define OMAP54XX_LOSTMEM_DSP_L1_SHIFT                                           8
+#define OMAP54XX_LOSTMEM_DSP_L1_WIDTH                                           0x1
+#define OMAP54XX_LOSTMEM_DSP_L1_MASK                                            (1 << 8)
+
+/* Used by RM_DSP_DSP_CONTEXT */
+#define OMAP54XX_LOSTMEM_DSP_L2_SHIFT                                           9
+#define OMAP54XX_LOSTMEM_DSP_L2_WIDTH                                           0x1
+#define OMAP54XX_LOSTMEM_DSP_L2_MASK                                            (1 << 9)
+
+/* Used by RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT */
+#define OMAP54XX_LOSTMEM_DSS_MEM_SHIFT                                          8
+#define OMAP54XX_LOSTMEM_DSS_MEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_DSS_MEM_MASK                                           (1 << 8)
+
+/* Used by RM_EMU_DEBUGSS_CONTEXT */
+#define OMAP54XX_LOSTMEM_EMU_BANK_SHIFT                                         8
+#define OMAP54XX_LOSTMEM_EMU_BANK_WIDTH                                         0x1
+#define OMAP54XX_LOSTMEM_EMU_BANK_MASK                                          (1 << 8)
+
+/* Used by RM_GPU_GPU_CONTEXT */
+#define OMAP54XX_LOSTMEM_GPU_MEM_SHIFT                                          8
+#define OMAP54XX_LOSTMEM_GPU_MEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_GPU_MEM_MASK                                           (1 << 8)
+
+/* Used by RM_IVA_IVA_CONTEXT */
+#define OMAP54XX_LOSTMEM_HWA_MEM_SHIFT                                          10
+#define OMAP54XX_LOSTMEM_HWA_MEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_HWA_MEM_MASK                                           (1 << 10)
+
+/* Used by RM_IPU_IPU_CONTEXT */
+#define OMAP54XX_LOSTMEM_IPU_L2RAM_SHIFT                                        9
+#define OMAP54XX_LOSTMEM_IPU_L2RAM_WIDTH                                        0x1
+#define OMAP54XX_LOSTMEM_IPU_L2RAM_MASK                                         (1 << 9)
+
+/* Used by RM_IPU_IPU_CONTEXT */
+#define OMAP54XX_LOSTMEM_IPU_UNICACHE_SHIFT                                     8
+#define OMAP54XX_LOSTMEM_IPU_UNICACHE_WIDTH                                     0x1
+#define OMAP54XX_LOSTMEM_IPU_UNICACHE_MASK                                      (1 << 8)
+
+/*
+ * Used by RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT,
+ * RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT,
+ * RM_L3INIT_USB_OTG_SS_CONTEXT
+ */
+#define OMAP54XX_LOSTMEM_L3INIT_BANK1_SHIFT                                     8
+#define OMAP54XX_LOSTMEM_L3INIT_BANK1_WIDTH                                     0x1
+#define OMAP54XX_LOSTMEM_L3INIT_BANK1_MASK                                      (1 << 8)
+
+/* Used by RM_MPU_MPU_CONTEXT */
+#define OMAP54XX_LOSTMEM_MPU_L2_SHIFT                                           9
+#define OMAP54XX_LOSTMEM_MPU_L2_WIDTH                                           0x1
+#define OMAP54XX_LOSTMEM_MPU_L2_MASK                                            (1 << 9)
+
+/* Used by RM_MPU_MPU_CONTEXT */
+#define OMAP54XX_LOSTMEM_MPU_RAM_SHIFT                                          10
+#define OMAP54XX_LOSTMEM_MPU_RAM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_MPU_RAM_MASK                                           (1 << 10)
+
+/*
+ * Used by RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT,
+ * RM_L4SEC_FPKA_CONTEXT
+ */
+#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_SHIFT                                 8
+#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_WIDTH                                 0x1
+#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_MASK                                  (1 << 8)
+
+/*
+ * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
+ * RM_ABE_MCBSP3_CONTEXT, RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT
+ */
+#define OMAP54XX_LOSTMEM_PERIHPMEM_SHIFT                                        8
+#define OMAP54XX_LOSTMEM_PERIHPMEM_WIDTH                                        0x1
+#define OMAP54XX_LOSTMEM_PERIHPMEM_MASK                                         (1 << 8)
+
+/*
+ * Used by RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT,
+ * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT,
+ * RM_L4PER_UART6_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT
+ */
+#define OMAP54XX_LOSTMEM_RETAINED_BANK_SHIFT                                    8
+#define OMAP54XX_LOSTMEM_RETAINED_BANK_WIDTH                                    0x1
+#define OMAP54XX_LOSTMEM_RETAINED_BANK_MASK                                     (1 << 8)
+
+/* Used by RM_IVA_SL2_CONTEXT */
+#define OMAP54XX_LOSTMEM_SL2_MEM_SHIFT                                          8
+#define OMAP54XX_LOSTMEM_SL2_MEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_SL2_MEM_MASK                                           (1 << 8)
+
+/* Used by RM_IVA_IVA_CONTEXT */
+#define OMAP54XX_LOSTMEM_TCM1_MEM_SHIFT                                         8
+#define OMAP54XX_LOSTMEM_TCM1_MEM_WIDTH                                         0x1
+#define OMAP54XX_LOSTMEM_TCM1_MEM_MASK                                          (1 << 8)
+
+/* Used by RM_IVA_IVA_CONTEXT */
+#define OMAP54XX_LOSTMEM_TCM2_MEM_SHIFT                                         9
+#define OMAP54XX_LOSTMEM_TCM2_MEM_WIDTH                                         0x1
+#define OMAP54XX_LOSTMEM_TCM2_MEM_MASK                                          (1 << 9)
+
+/* Used by RM_WKUPAON_SAR_RAM_CONTEXT */
+#define OMAP54XX_LOSTMEM_WKUP_BANK_SHIFT                                        8
+#define OMAP54XX_LOSTMEM_WKUP_BANK_WIDTH                                        0x1
+#define OMAP54XX_LOSTMEM_WKUP_BANK_MASK                                         (1 << 8)
+
+/*
+ * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL,
+ * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL,
+ * PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL
+ */
+#define OMAP54XX_LOWPOWERSTATECHANGE_SHIFT                                      4
+#define OMAP54XX_LOWPOWERSTATECHANGE_WIDTH                                      0x1
+#define OMAP54XX_LOWPOWERSTATECHANGE_MASK                                       (1 << 4)
+
+/* Used by PRM_DEBUG_TRANS_CFG */
+#define OMAP54XX_MODE_SHIFT                                                     0
+#define OMAP54XX_MODE_WIDTH                                                     0x2
+#define OMAP54XX_MODE_MASK                                                      (0x3 << 0)
+
+/* Used by PRM_MODEM_IF_CTRL */
+#define OMAP54XX_MODEM_SHUTDOWN_IRQ_SHIFT                                       9
+#define OMAP54XX_MODEM_SHUTDOWN_IRQ_WIDTH                                       0x1
+#define OMAP54XX_MODEM_SHUTDOWN_IRQ_MASK                                        (1 << 9)
+
+/* Used by PRM_MODEM_IF_CTRL */
+#define OMAP54XX_MODEM_WAKE_IRQ_SHIFT                                           8
+#define OMAP54XX_MODEM_WAKE_IRQ_WIDTH                                           0x1
+#define OMAP54XX_MODEM_WAKE_IRQ_MASK                                            (1 << 8)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP54XX_MPU_L2_ONSTATE_SHIFT                                           18
+#define OMAP54XX_MPU_L2_ONSTATE_WIDTH                                           0x2
+#define OMAP54XX_MPU_L2_ONSTATE_MASK                                            (0x3 << 18)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP54XX_MPU_L2_RETSTATE_SHIFT                                          9
+#define OMAP54XX_MPU_L2_RETSTATE_WIDTH                                          0x1
+#define OMAP54XX_MPU_L2_RETSTATE_MASK                                           (1 << 9)
+
+/* Used by PM_MPU_PWRSTST */
+#define OMAP54XX_MPU_L2_STATEST_SHIFT                                           6
+#define OMAP54XX_MPU_L2_STATEST_WIDTH                                           0x2
+#define OMAP54XX_MPU_L2_STATEST_MASK                                            (0x3 << 6)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP54XX_MPU_RAM_ONSTATE_SHIFT                                          20
+#define OMAP54XX_MPU_RAM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_MPU_RAM_ONSTATE_MASK                                           (0x3 << 20)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP54XX_MPU_RAM_RETSTATE_SHIFT                                         10
+#define OMAP54XX_MPU_RAM_RETSTATE_WIDTH                                         0x1
+#define OMAP54XX_MPU_RAM_RETSTATE_MASK                                          (1 << 10)
+
+/* Used by PM_MPU_PWRSTST */
+#define OMAP54XX_MPU_RAM_STATEST_SHIFT                                          8
+#define OMAP54XX_MPU_RAM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_MPU_RAM_STATEST_MASK                                           (0x3 << 8)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_MPU_SECURITY_VIOL_RST_SHIFT                                    2
+#define OMAP54XX_MPU_SECURITY_VIOL_RST_WIDTH                                    0x1
+#define OMAP54XX_MPU_SECURITY_VIOL_RST_MASK                                     (1 << 2)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_MPU_WDT_RST_SHIFT                                              3
+#define OMAP54XX_MPU_WDT_RST_WIDTH                                              0x1
+#define OMAP54XX_MPU_WDT_RST_MASK                                               (1 << 3)
+
+/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
+#define OMAP54XX_NOCAP_SHIFT                                                    4
+#define OMAP54XX_NOCAP_WIDTH                                                    0x1
+#define OMAP54XX_NOCAP_MASK                                                     (1 << 4)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_OCP_NRET_BANK_ONSTATE_SHIFT                                    24
+#define OMAP54XX_OCP_NRET_BANK_ONSTATE_WIDTH                                    0x2
+#define OMAP54XX_OCP_NRET_BANK_ONSTATE_MASK                                     (0x3 << 24)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_OCP_NRET_BANK_RETSTATE_SHIFT                                   12
+#define OMAP54XX_OCP_NRET_BANK_RETSTATE_WIDTH                                   0x1
+#define OMAP54XX_OCP_NRET_BANK_RETSTATE_MASK                                    (1 << 12)
+
+/* Used by PM_CORE_PWRSTST */
+#define OMAP54XX_OCP_NRET_BANK_STATEST_SHIFT                                    12
+#define OMAP54XX_OCP_NRET_BANK_STATEST_WIDTH                                    0x2
+#define OMAP54XX_OCP_NRET_BANK_STATEST_MASK                                     (0x3 << 12)
+
+/*
+ * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
+ * PRM_VC_VAL_CMD_VDD_MPU_L
+ */
+#define OMAP54XX_OFF_SHIFT                                                      0
+#define OMAP54XX_OFF_WIDTH                                                      0x8
+#define OMAP54XX_OFF_MASK                                                       (0xff << 0)
+
+/*
+ * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
+ * PRM_VC_VAL_CMD_VDD_MPU_L
+ */
+#define OMAP54XX_ON_SHIFT                                                       24
+#define OMAP54XX_ON_WIDTH                                                       0x8
+#define OMAP54XX_ON_MASK                                                        (0xff << 24)
+
+/*
+ * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
+ * PRM_VC_VAL_CMD_VDD_MPU_L
+ */
+#define OMAP54XX_ONLP_SHIFT                                                     16
+#define OMAP54XX_ONLP_WIDTH                                                     0x8
+#define OMAP54XX_ONLP_MASK                                                      (0xff << 16)
+
+/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
+#define OMAP54XX_OPP_CHANGE_SHIFT                                               2
+#define OMAP54XX_OPP_CHANGE_WIDTH                                               0x1
+#define OMAP54XX_OPP_CHANGE_MASK                                                (1 << 2)
+
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP54XX_OPP_CHANGE_EMIF_LVL_SHIFT                                      25
+#define OMAP54XX_OPP_CHANGE_EMIF_LVL_WIDTH                                      0x1
+#define OMAP54XX_OPP_CHANGE_EMIF_LVL_MASK                                       (1 << 25)
+
+/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
+#define OMAP54XX_OPP_SEL_SHIFT                                                  0
+#define OMAP54XX_OPP_SEL_WIDTH                                                  0x2
+#define OMAP54XX_OPP_SEL_MASK                                                   (0x3 << 0)
+
+/* Used by PRM_DEBUG_OUT */
+#define OMAP54XX_OUTPUT_SHIFT                                                   0
+#define OMAP54XX_OUTPUT_WIDTH                                                   0x20
+#define OMAP54XX_OUTPUT_MASK                                                    (0xffffffff << 0)
+
+/* Used by PRM_SRAM_COUNT */
+#define OMAP54XX_PCHARGECNT_VALUE_SHIFT                                         0
+#define OMAP54XX_PCHARGECNT_VALUE_WIDTH                                         0x6
+#define OMAP54XX_PCHARGECNT_VALUE_MASK                                          (0x3f << 0)
+
+/* Used by PRM_PSCON_COUNT */
+#define OMAP54XX_PCHARGE_TIME_SHIFT                                             0
+#define OMAP54XX_PCHARGE_TIME_WIDTH                                             0x8
+#define OMAP54XX_PCHARGE_TIME_MASK                                              (0xff << 0)
+
+/* Used by PM_ABE_PWRSTCTRL */
+#define OMAP54XX_PERIPHMEM_ONSTATE_SHIFT                                        20
+#define OMAP54XX_PERIPHMEM_ONSTATE_WIDTH                                        0x2
+#define OMAP54XX_PERIPHMEM_ONSTATE_MASK                                         (0x3 << 20)
+
+/* Used by PM_ABE_PWRSTCTRL */
+#define OMAP54XX_PERIPHMEM_RETSTATE_SHIFT                                       10
+#define OMAP54XX_PERIPHMEM_RETSTATE_WIDTH                                       0x1
+#define OMAP54XX_PERIPHMEM_RETSTATE_MASK                                        (1 << 10)
+
+/* Used by PM_ABE_PWRSTST */
+#define OMAP54XX_PERIPHMEM_STATEST_SHIFT                                        8
+#define OMAP54XX_PERIPHMEM_STATEST_WIDTH                                        0x2
+#define OMAP54XX_PERIPHMEM_STATEST_MASK                                         (0x3 << 8)
+
+/* Used by PRM_PHASE1_CNDP */
+#define OMAP54XX_PHASE1_CNDP_SHIFT                                              0
+#define OMAP54XX_PHASE1_CNDP_WIDTH                                              0x20
+#define OMAP54XX_PHASE1_CNDP_MASK                                               (0xffffffff << 0)
+
+/* Used by PRM_PHASE2A_CNDP */
+#define OMAP54XX_PHASE2A_CNDP_SHIFT                                             0
+#define OMAP54XX_PHASE2A_CNDP_WIDTH                                             0x20
+#define OMAP54XX_PHASE2A_CNDP_MASK                                              (0xffffffff << 0)
+
+/* Used by PRM_PHASE2B_CNDP */
+#define OMAP54XX_PHASE2B_CNDP_SHIFT                                             0
+#define OMAP54XX_PHASE2B_CNDP_WIDTH                                             0x20
+#define OMAP54XX_PHASE2B_CNDP_MASK                                              (0xffffffff << 0)
+
+/* Used by PRM_PSCON_COUNT */
+#define OMAP54XX_PONOUT_2_PGOODIN_TIME_SHIFT                                    8
+#define OMAP54XX_PONOUT_2_PGOODIN_TIME_WIDTH                                    0x8
+#define OMAP54XX_PONOUT_2_PGOODIN_TIME_MASK                                     (0xff << 8)
+
+/*
+ * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL,
+ * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL,
+ * PM_EMU_PWRSTCTRL, PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL
+ */
+#define OMAP54XX_POWERSTATE_SHIFT                                               0
+#define OMAP54XX_POWERSTATE_WIDTH                                               0x2
+#define OMAP54XX_POWERSTATE_MASK                                                (0x3 << 0)
+
+/*
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
+ * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
+ * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
+ */
+#define OMAP54XX_POWERSTATEST_SHIFT                                             0
+#define OMAP54XX_POWERSTATEST_WIDTH                                             0x2
+#define OMAP54XX_POWERSTATEST_MASK                                              (0x3 << 0)
+
+/* Used by PRM_PWRREQCTRL */
+#define OMAP54XX_PWRREQ_COND_SHIFT                                              0
+#define OMAP54XX_PWRREQ_COND_WIDTH                                              0x2
+#define OMAP54XX_PWRREQ_COND_MASK                                               (0x3 << 0)
+
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_RACEN_VDD_CORE_L_SHIFT                                         27
+#define OMAP54XX_RACEN_VDD_CORE_L_WIDTH                                         0x1
+#define OMAP54XX_RACEN_VDD_CORE_L_MASK                                          (1 << 27)
+
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_RACEN_VDD_MM_L_SHIFT                                           27
+#define OMAP54XX_RACEN_VDD_MM_L_WIDTH                                           0x1
+#define OMAP54XX_RACEN_VDD_MM_L_MASK                                            (1 << 27)
+
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_RACEN_VDD_MPU_L_SHIFT                                          27
+#define OMAP54XX_RACEN_VDD_MPU_L_WIDTH                                          0x1
+#define OMAP54XX_RACEN_VDD_MPU_L_MASK                                           (1 << 27)
+
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_RAC_VDD_CORE_L_SHIFT                                           26
+#define OMAP54XX_RAC_VDD_CORE_L_WIDTH                                           0x1
+#define OMAP54XX_RAC_VDD_CORE_L_MASK                                            (1 << 26)
+
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_RAC_VDD_MM_L_SHIFT                                             26
+#define OMAP54XX_RAC_VDD_MM_L_WIDTH                                             0x1
+#define OMAP54XX_RAC_VDD_MM_L_MASK                                              (1 << 26)
+
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_RAC_VDD_MPU_L_SHIFT                                            26
+#define OMAP54XX_RAC_VDD_MPU_L_WIDTH                                            0x1
+#define OMAP54XX_RAC_VDD_MPU_L_MASK                                             (1 << 26)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define OMAP54XX_RAMP_DOWN_COUNT_SHIFT                                          16
+#define OMAP54XX_RAMP_DOWN_COUNT_WIDTH                                          0x6
+#define OMAP54XX_RAMP_DOWN_COUNT_MASK                                           (0x3f << 16)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define OMAP54XX_RAMP_DOWN_PRESCAL_SHIFT                                        24
+#define OMAP54XX_RAMP_DOWN_PRESCAL_WIDTH                                        0x2
+#define OMAP54XX_RAMP_DOWN_PRESCAL_MASK                                         (0x3 << 24)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define OMAP54XX_RAMP_UP_COUNT_SHIFT                                            0
+#define OMAP54XX_RAMP_UP_COUNT_WIDTH                                            0x6
+#define OMAP54XX_RAMP_UP_COUNT_MASK                                             (0x3f << 0)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define OMAP54XX_RAMP_UP_PRESCAL_SHIFT                                          8
+#define OMAP54XX_RAMP_UP_PRESCAL_WIDTH                                          0x2
+#define OMAP54XX_RAMP_UP_PRESCAL_MASK                                           (0x3 << 8)
+
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_RAV_VDD_CORE_L_SHIFT                                           25
+#define OMAP54XX_RAV_VDD_CORE_L_WIDTH                                           0x1
+#define OMAP54XX_RAV_VDD_CORE_L_MASK                                            (1 << 25)
+
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_RAV_VDD_MM_L_SHIFT                                             25
+#define OMAP54XX_RAV_VDD_MM_L_WIDTH                                             0x1
+#define OMAP54XX_RAV_VDD_MM_L_MASK                                              (1 << 25)
+
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_RAV_VDD_MPU_L_SHIFT                                            25
+#define OMAP54XX_RAV_VDD_MPU_L_WIDTH                                            0x1
+#define OMAP54XX_RAV_VDD_MPU_L_MASK                                             (1 << 25)
+
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP54XX_REGADDR_SHIFT                                                  8
+#define OMAP54XX_REGADDR_WIDTH                                                  0x8
+#define OMAP54XX_REGADDR_MASK                                                   (0xff << 8)
+
+/*
+ * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
+ * PRM_VC_VAL_CMD_VDD_MPU_L
+ */
+#define OMAP54XX_RET_SHIFT                                                      8
+#define OMAP54XX_RET_WIDTH                                                      0x8
+#define OMAP54XX_RET_MASK                                                       (0xff << 8)
+
+/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
+#define OMAP54XX_RETMODE_ENABLE_SHIFT                                           0
+#define OMAP54XX_RETMODE_ENABLE_WIDTH                                           0x1
+#define OMAP54XX_RETMODE_ENABLE_MASK                                            (1 << 0)
+
+/* Used by PRM_RSTTIME */
+#define OMAP54XX_RSTTIME1_SHIFT                                                 0
+#define OMAP54XX_RSTTIME1_WIDTH                                                 0xa
+#define OMAP54XX_RSTTIME1_MASK                                                  (0x3ff << 0)
+
+/* Used by PRM_RSTTIME */
+#define OMAP54XX_RSTTIME2_SHIFT                                                 10
+#define OMAP54XX_RSTTIME2_WIDTH                                                 0x5
+#define OMAP54XX_RSTTIME2_MASK                                                  (0x1f << 10)
+
+/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
+#define OMAP54XX_RST_CPU0_SHIFT                                                 0
+#define OMAP54XX_RST_CPU0_WIDTH                                                 0x1
+#define OMAP54XX_RST_CPU0_MASK                                                  (1 << 0)
+
+/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
+#define OMAP54XX_RST_CPU1_SHIFT                                                 1
+#define OMAP54XX_RST_CPU1_WIDTH                                                 0x1
+#define OMAP54XX_RST_CPU1_MASK                                                  (1 << 1)
+
+/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */
+#define OMAP54XX_RST_DSP_SHIFT                                                  0
+#define OMAP54XX_RST_DSP_WIDTH                                                  0x1
+#define OMAP54XX_RST_DSP_MASK                                                   (1 << 0)
+
+/* Used by RM_DSP_RSTST */
+#define OMAP54XX_RST_DSP_EMU_SHIFT                                              2
+#define OMAP54XX_RST_DSP_EMU_WIDTH                                              0x1
+#define OMAP54XX_RST_DSP_EMU_MASK                                               (1 << 2)
+
+/* Used by RM_DSP_RSTST */
+#define OMAP54XX_RST_DSP_EMU_REQ_SHIFT                                          3
+#define OMAP54XX_RST_DSP_EMU_REQ_WIDTH                                          0x1
+#define OMAP54XX_RST_DSP_EMU_REQ_MASK                                           (1 << 3)
+
+/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */
+#define OMAP54XX_RST_DSP_MMU_CACHE_SHIFT                                        1
+#define OMAP54XX_RST_DSP_MMU_CACHE_WIDTH                                        0x1
+#define OMAP54XX_RST_DSP_MMU_CACHE_MASK                                         (1 << 1)
+
+/* Used by RM_IPU_RSTST */
+#define OMAP54XX_RST_EMULATION_CPU0_SHIFT                                       3
+#define OMAP54XX_RST_EMULATION_CPU0_WIDTH                                       0x1
+#define OMAP54XX_RST_EMULATION_CPU0_MASK                                        (1 << 3)
+
+/* Used by RM_IPU_RSTST */
+#define OMAP54XX_RST_EMULATION_CPU1_SHIFT                                       4
+#define OMAP54XX_RST_EMULATION_CPU1_WIDTH                                       0x1
+#define OMAP54XX_RST_EMULATION_CPU1_MASK                                        (1 << 4)
+
+/* Used by RM_IVA_RSTST */
+#define OMAP54XX_RST_EMULATION_SEQ1_SHIFT                                       3
+#define OMAP54XX_RST_EMULATION_SEQ1_WIDTH                                       0x1
+#define OMAP54XX_RST_EMULATION_SEQ1_MASK                                        (1 << 3)
+
+/* Used by RM_IVA_RSTST */
+#define OMAP54XX_RST_EMULATION_SEQ2_SHIFT                                       4
+#define OMAP54XX_RST_EMULATION_SEQ2_WIDTH                                       0x1
+#define OMAP54XX_RST_EMULATION_SEQ2_MASK                                        (1 << 4)
+
+/* Used by PRM_RSTCTRL */
+#define OMAP54XX_RST_GLOBAL_COLD_SW_SHIFT                                       1
+#define OMAP54XX_RST_GLOBAL_COLD_SW_WIDTH                                       0x1
+#define OMAP54XX_RST_GLOBAL_COLD_SW_MASK                                        (1 << 1)
+
+/* Used by PRM_RSTCTRL */
+#define OMAP54XX_RST_GLOBAL_WARM_SW_SHIFT                                       0
+#define OMAP54XX_RST_GLOBAL_WARM_SW_WIDTH                                       0x1
+#define OMAP54XX_RST_GLOBAL_WARM_SW_MASK                                        (1 << 0)
+
+/* Used by RM_IPU_RSTST */
+#define OMAP54XX_RST_ICECRUSHER_CPU0_SHIFT                                      5
+#define OMAP54XX_RST_ICECRUSHER_CPU0_WIDTH                                      0x1
+#define OMAP54XX_RST_ICECRUSHER_CPU0_MASK                                       (1 << 5)
+
+/* Used by RM_IPU_RSTST */
+#define OMAP54XX_RST_ICECRUSHER_CPU1_SHIFT                                      6
+#define OMAP54XX_RST_ICECRUSHER_CPU1_WIDTH                                      0x1
+#define OMAP54XX_RST_ICECRUSHER_CPU1_MASK                                       (1 << 6)
+
+/* Used by RM_IVA_RSTST */
+#define OMAP54XX_RST_ICECRUSHER_SEQ1_SHIFT                                      5
+#define OMAP54XX_RST_ICECRUSHER_SEQ1_WIDTH                                      0x1
+#define OMAP54XX_RST_ICECRUSHER_SEQ1_MASK                                       (1 << 5)
+
+/* Used by RM_IVA_RSTST */
+#define OMAP54XX_RST_ICECRUSHER_SEQ2_SHIFT                                      6
+#define OMAP54XX_RST_ICECRUSHER_SEQ2_WIDTH                                      0x1
+#define OMAP54XX_RST_ICECRUSHER_SEQ2_MASK                                       (1 << 6)
+
+/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
+#define OMAP54XX_RST_IPU_MMU_CACHE_SHIFT                                        2
+#define OMAP54XX_RST_IPU_MMU_CACHE_WIDTH                                        0x1
+#define OMAP54XX_RST_IPU_MMU_CACHE_MASK                                         (1 << 2)
+
+/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
+#define OMAP54XX_RST_LOGIC_SHIFT                                                2
+#define OMAP54XX_RST_LOGIC_WIDTH                                                0x1
+#define OMAP54XX_RST_LOGIC_MASK                                                 (1 << 2)
+
+/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
+#define OMAP54XX_RST_SEQ1_SHIFT                                                 0
+#define OMAP54XX_RST_SEQ1_WIDTH                                                 0x1
+#define OMAP54XX_RST_SEQ1_MASK                                                  (1 << 0)
+
+/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
+#define OMAP54XX_RST_SEQ2_SHIFT                                                 1
+#define OMAP54XX_RST_SEQ2_WIDTH                                                 0x1
+#define OMAP54XX_RST_SEQ2_MASK                                                  (1 << 1)
+
+/* Used by REVISION_PRM */
+#define OMAP54XX_R_RTL_SHIFT                                                    11
+#define OMAP54XX_R_RTL_WIDTH                                                    0x5
+#define OMAP54XX_R_RTL_MASK                                                     (0x1f << 11)
+
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_SA_VDD_CORE_L_SHIFT                                            0
+#define OMAP54XX_SA_VDD_CORE_L_WIDTH                                            0x7
+#define OMAP54XX_SA_VDD_CORE_L_MASK                                             (0x7f << 0)
+
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_SA_VDD_MM_L_SHIFT                                              0
+#define OMAP54XX_SA_VDD_MM_L_WIDTH                                              0x7
+#define OMAP54XX_SA_VDD_MM_L_MASK                                               (0x7f << 0)
+
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_SA_VDD_MPU_L_SHIFT                                             0
+#define OMAP54XX_SA_VDD_MPU_L_WIDTH                                             0x7
+#define OMAP54XX_SA_VDD_MPU_L_MASK                                              (0x7f << 0)
+
+/* Used by REVISION_PRM */
+#define OMAP54XX_SCHEME_SHIFT                                                   30
+#define OMAP54XX_SCHEME_WIDTH                                                   0x2
+#define OMAP54XX_SCHEME_MASK                                                    (0x3 << 30)
+
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP54XX_SCLH_SHIFT                                                     0
+#define OMAP54XX_SCLH_WIDTH                                                     0x8
+#define OMAP54XX_SCLH_MASK                                                      (0xff << 0)
+
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP54XX_SCLL_SHIFT                                                     8
+#define OMAP54XX_SCLL_WIDTH                                                     0x8
+#define OMAP54XX_SCLL_MASK                                                      (0xff << 8)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_SECURE_WDT_RST_SHIFT                                           4
+#define OMAP54XX_SECURE_WDT_RST_WIDTH                                           0x1
+#define OMAP54XX_SECURE_WDT_RST_MASK                                            (1 << 4)
+
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_SEL_SA_VDD_CORE_L_SHIFT                                        24
+#define OMAP54XX_SEL_SA_VDD_CORE_L_WIDTH                                        0x1
+#define OMAP54XX_SEL_SA_VDD_CORE_L_MASK                                         (1 << 24)
+
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_SEL_SA_VDD_MM_L_SHIFT                                          24
+#define OMAP54XX_SEL_SA_VDD_MM_L_WIDTH                                          0x1
+#define OMAP54XX_SEL_SA_VDD_MM_L_MASK                                           (1 << 24)
+
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_SEL_SA_VDD_MPU_L_SHIFT                                         24
+#define OMAP54XX_SEL_SA_VDD_MPU_L_WIDTH                                         0x1
+#define OMAP54XX_SEL_SA_VDD_MPU_L_MASK                                          (1 << 24)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_SL2_MEM_ONSTATE_SHIFT                                          18
+#define OMAP54XX_SL2_MEM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_SL2_MEM_ONSTATE_MASK                                           (0x3 << 18)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_SL2_MEM_RETSTATE_SHIFT                                         9
+#define OMAP54XX_SL2_MEM_RETSTATE_WIDTH                                         0x1
+#define OMAP54XX_SL2_MEM_RETSTATE_MASK                                          (1 << 9)
+
+/* Used by PM_IVA_PWRSTST */
+#define OMAP54XX_SL2_MEM_STATEST_SHIFT                                          6
+#define OMAP54XX_SL2_MEM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_SL2_MEM_STATEST_MASK                                           (0x3 << 6)
+
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP54XX_SLAVEADDR_SHIFT                                                0
+#define OMAP54XX_SLAVEADDR_WIDTH                                                0x7
+#define OMAP54XX_SLAVEADDR_MASK                                                 (0x7f << 0)
+
+/* Used by PRM_SRAM_COUNT */
+#define OMAP54XX_SLPCNT_VALUE_SHIFT                                             16
+#define OMAP54XX_SLPCNT_VALUE_WIDTH                                             0x8
+#define OMAP54XX_SLPCNT_VALUE_MASK                                              (0xff << 16)
+
+/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
+#define OMAP54XX_SMPSWAITTIMEMAX_SHIFT                                          8
+#define OMAP54XX_SMPSWAITTIMEMAX_WIDTH                                          0x10
+#define OMAP54XX_SMPSWAITTIMEMAX_MASK                                           (0xffff << 8)
+
+/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
+#define OMAP54XX_SMPSWAITTIMEMIN_SHIFT                                          8
+#define OMAP54XX_SMPSWAITTIMEMIN_WIDTH                                          0x10
+#define OMAP54XX_SMPSWAITTIMEMIN_MASK                                           (0xffff << 8)
+
+/* Used by PRM_VC_CORE_ERRST */
+#define OMAP54XX_SMPS_RA_ERR_CORE_SHIFT                                         1
+#define OMAP54XX_SMPS_RA_ERR_CORE_WIDTH                                         0x1
+#define OMAP54XX_SMPS_RA_ERR_CORE_MASK                                          (1 << 1)
+
+/* Used by PRM_VC_MM_ERRST */
+#define OMAP54XX_SMPS_RA_ERR_MM_SHIFT                                           1
+#define OMAP54XX_SMPS_RA_ERR_MM_WIDTH                                           0x1
+#define OMAP54XX_SMPS_RA_ERR_MM_MASK                                            (1 << 1)
+
+/* Used by PRM_VC_MPU_ERRST */
+#define OMAP54XX_SMPS_RA_ERR_MPU_SHIFT                                          1
+#define OMAP54XX_SMPS_RA_ERR_MPU_WIDTH                                          0x1
+#define OMAP54XX_SMPS_RA_ERR_MPU_MASK                                           (1 << 1)
+
+/* Used by PRM_VC_CORE_ERRST */
+#define OMAP54XX_SMPS_SA_ERR_CORE_SHIFT                                         0
+#define OMAP54XX_SMPS_SA_ERR_CORE_WIDTH                                         0x1
+#define OMAP54XX_SMPS_SA_ERR_CORE_MASK                                          (1 << 0)
+
+/* Used by PRM_VC_MM_ERRST */
+#define OMAP54XX_SMPS_SA_ERR_MM_SHIFT                                           0
+#define OMAP54XX_SMPS_SA_ERR_MM_WIDTH                                           0x1
+#define OMAP54XX_SMPS_SA_ERR_MM_MASK                                            (1 << 0)
+
+/* Used by PRM_VC_MPU_ERRST */
+#define OMAP54XX_SMPS_SA_ERR_MPU_SHIFT                                          0
+#define OMAP54XX_SMPS_SA_ERR_MPU_WIDTH                                          0x1
+#define OMAP54XX_SMPS_SA_ERR_MPU_MASK                                           (1 << 0)
+
+/* Used by PRM_VC_CORE_ERRST */
+#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_SHIFT                                    2
+#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_WIDTH                                    0x1
+#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_MASK                                     (1 << 2)
+
+/* Used by PRM_VC_MM_ERRST */
+#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_SHIFT                                      2
+#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_WIDTH                                      0x1
+#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_MASK                                       (1 << 2)
+
+/* Used by PRM_VC_MPU_ERRST */
+#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_SHIFT                                     2
+#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_WIDTH                                     0x1
+#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_MASK                                      (1 << 2)
+
+/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
+#define OMAP54XX_SR2EN_SHIFT                                                    0
+#define OMAP54XX_SR2EN_WIDTH                                                    0x1
+#define OMAP54XX_SR2EN_MASK                                                     (1 << 0)
+
+/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
+#define OMAP54XX_SR2_IN_TRANSITION_SHIFT                                        6
+#define OMAP54XX_SR2_IN_TRANSITION_WIDTH                                        0x1
+#define OMAP54XX_SR2_IN_TRANSITION_MASK                                         (1 << 6)
+
+/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
+#define OMAP54XX_SR2_STATUS_SHIFT                                               3
+#define OMAP54XX_SR2_STATUS_WIDTH                                               0x2
+#define OMAP54XX_SR2_STATUS_MASK                                                (0x3 << 3)
+
+/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
+#define OMAP54XX_SR2_WTCNT_VALUE_SHIFT                                          8
+#define OMAP54XX_SR2_WTCNT_VALUE_WIDTH                                          0x8
+#define OMAP54XX_SR2_WTCNT_VALUE_MASK                                           (0xff << 8)
+
+/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
+#define OMAP54XX_SRAMLDO_STATUS_SHIFT                                           8
+#define OMAP54XX_SRAMLDO_STATUS_WIDTH                                           0x1
+#define OMAP54XX_SRAMLDO_STATUS_MASK                                            (1 << 8)
+
+/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
+#define OMAP54XX_SRAM_IN_TRANSITION_SHIFT                                       9
+#define OMAP54XX_SRAM_IN_TRANSITION_WIDTH                                       0x1
+#define OMAP54XX_SRAM_IN_TRANSITION_MASK                                        (1 << 9)
+
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP54XX_SRMODEEN_SHIFT                                                 4
+#define OMAP54XX_SRMODEEN_WIDTH                                                 0x1
+#define OMAP54XX_SRMODEEN_MASK                                                  (1 << 4)
+
+/* Used by PRM_VOLTSETUP_WARMRESET */
+#define OMAP54XX_STABLE_COUNT_SHIFT                                             0
+#define OMAP54XX_STABLE_COUNT_WIDTH                                             0x6
+#define OMAP54XX_STABLE_COUNT_MASK                                              (0x3f << 0)
+
+/* Used by PRM_VOLTSETUP_WARMRESET */
+#define OMAP54XX_STABLE_PRESCAL_SHIFT                                           8
+#define OMAP54XX_STABLE_PRESCAL_WIDTH                                           0x2
+#define OMAP54XX_STABLE_PRESCAL_MASK                                            (0x3 << 8)
+
+/* Used by PRM_BANDGAP_SETUP */
+#define OMAP54XX_STARTUP_COUNT_SHIFT                                            0
+#define OMAP54XX_STARTUP_COUNT_WIDTH                                            0x8
+#define OMAP54XX_STARTUP_COUNT_MASK                                             (0xff << 0)
+
+/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
+#define OMAP54XX_STARTUP_COUNT_24_31_SHIFT                                      24
+#define OMAP54XX_STARTUP_COUNT_24_31_WIDTH                                      0x8
+#define OMAP54XX_STARTUP_COUNT_24_31_MASK                                       (0xff << 24)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_TCM1_MEM_ONSTATE_SHIFT                                         20
+#define OMAP54XX_TCM1_MEM_ONSTATE_WIDTH                                         0x2
+#define OMAP54XX_TCM1_MEM_ONSTATE_MASK                                          (0x3 << 20)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_TCM1_MEM_RETSTATE_SHIFT                                        10
+#define OMAP54XX_TCM1_MEM_RETSTATE_WIDTH                                        0x1
+#define OMAP54XX_TCM1_MEM_RETSTATE_MASK                                         (1 << 10)
+
+/* Used by PM_IVA_PWRSTST */
+#define OMAP54XX_TCM1_MEM_STATEST_SHIFT                                         8
+#define OMAP54XX_TCM1_MEM_STATEST_WIDTH                                         0x2
+#define OMAP54XX_TCM1_MEM_STATEST_MASK                                          (0x3 << 8)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_TCM2_MEM_ONSTATE_SHIFT                                         22
+#define OMAP54XX_TCM2_MEM_ONSTATE_WIDTH                                         0x2
+#define OMAP54XX_TCM2_MEM_ONSTATE_MASK                                          (0x3 << 22)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_TCM2_MEM_RETSTATE_SHIFT                                        11
+#define OMAP54XX_TCM2_MEM_RETSTATE_WIDTH                                        0x1
+#define OMAP54XX_TCM2_MEM_RETSTATE_MASK                                         (1 << 11)
+
+/* Used by PM_IVA_PWRSTST */
+#define OMAP54XX_TCM2_MEM_STATEST_SHIFT                                         10
+#define OMAP54XX_TCM2_MEM_STATEST_WIDTH                                         0x2
+#define OMAP54XX_TCM2_MEM_STATEST_MASK                                          (0x3 << 10)
+
+/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+#define OMAP54XX_TIMEOUT_SHIFT                                                  0
+#define OMAP54XX_TIMEOUT_WIDTH                                                  0x10
+#define OMAP54XX_TIMEOUT_MASK                                                   (0xffff << 0)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_TIMEOUTEN_SHIFT                                                3
+#define OMAP54XX_TIMEOUTEN_WIDTH                                                0x1
+#define OMAP54XX_TIMEOUTEN_MASK                                                 (1 << 3)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_TRANSITION_EN_SHIFT                                            8
+#define OMAP54XX_TRANSITION_EN_WIDTH                                            0x1
+#define OMAP54XX_TRANSITION_EN_MASK                                             (1 << 8)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_TRANSITION_ST_SHIFT                                            8
+#define OMAP54XX_TRANSITION_ST_WIDTH                                            0x1
+#define OMAP54XX_TRANSITION_ST_MASK                                             (1 << 8)
+
+/* Used by PRM_DEBUG_TRANS_CFG */
+#define OMAP54XX_TRIGGER_CLEAR_SHIFT                                            2
+#define OMAP54XX_TRIGGER_CLEAR_WIDTH                                            0x1
+#define OMAP54XX_TRIGGER_CLEAR_MASK                                             (1 << 2)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_TSHUT_CORE_RST_SHIFT                                           13
+#define OMAP54XX_TSHUT_CORE_RST_WIDTH                                           0x1
+#define OMAP54XX_TSHUT_CORE_RST_MASK                                            (1 << 13)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_TSHUT_MM_RST_SHIFT                                             12
+#define OMAP54XX_TSHUT_MM_RST_WIDTH                                             0x1
+#define OMAP54XX_TSHUT_MM_RST_MASK                                              (1 << 12)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_TSHUT_MPU_RST_SHIFT                                            11
+#define OMAP54XX_TSHUT_MPU_RST_WIDTH                                            0x1
+#define OMAP54XX_TSHUT_MPU_RST_MASK                                             (1 << 11)
+
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP54XX_VALID_SHIFT                                                    24
+#define OMAP54XX_VALID_WIDTH                                                    0x1
+#define OMAP54XX_VALID_MASK                                                     (1 << 24)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VC_BYPASSACK_EN_SHIFT                                          14
+#define OMAP54XX_VC_BYPASSACK_EN_WIDTH                                          0x1
+#define OMAP54XX_VC_BYPASSACK_EN_MASK                                           (1 << 14)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VC_BYPASSACK_ST_SHIFT                                          14
+#define OMAP54XX_VC_BYPASSACK_ST_WIDTH                                          0x1
+#define OMAP54XX_VC_BYPASSACK_ST_MASK                                           (1 << 14)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VC_CORE_VPACK_EN_SHIFT                                         22
+#define OMAP54XX_VC_CORE_VPACK_EN_WIDTH                                         0x1
+#define OMAP54XX_VC_CORE_VPACK_EN_MASK                                          (1 << 22)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VC_CORE_VPACK_ST_SHIFT                                         22
+#define OMAP54XX_VC_CORE_VPACK_ST_WIDTH                                         0x1
+#define OMAP54XX_VC_CORE_VPACK_ST_MASK                                          (1 << 22)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VC_MM_VPACK_EN_SHIFT                                           30
+#define OMAP54XX_VC_MM_VPACK_EN_WIDTH                                           0x1
+#define OMAP54XX_VC_MM_VPACK_EN_MASK                                            (1 << 30)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VC_MM_VPACK_ST_SHIFT                                           30
+#define OMAP54XX_VC_MM_VPACK_ST_WIDTH                                           0x1
+#define OMAP54XX_VC_MM_VPACK_ST_MASK                                            (1 << 30)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VC_MPU_VPACK_EN_SHIFT                                          6
+#define OMAP54XX_VC_MPU_VPACK_EN_WIDTH                                          0x1
+#define OMAP54XX_VC_MPU_VPACK_EN_MASK                                           (1 << 6)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VC_MPU_VPACK_ST_SHIFT                                          6
+#define OMAP54XX_VC_MPU_VPACK_ST_WIDTH                                          0x1
+#define OMAP54XX_VC_MPU_VPACK_ST_MASK                                           (1 << 6)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VC_RAERR_EN_SHIFT                                              12
+#define OMAP54XX_VC_RAERR_EN_WIDTH                                              0x1
+#define OMAP54XX_VC_RAERR_EN_MASK                                               (1 << 12)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VC_RAERR_ST_SHIFT                                              12
+#define OMAP54XX_VC_RAERR_ST_WIDTH                                              0x1
+#define OMAP54XX_VC_RAERR_ST_MASK                                               (1 << 12)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VC_SAERR_EN_SHIFT                                              11
+#define OMAP54XX_VC_SAERR_EN_WIDTH                                              0x1
+#define OMAP54XX_VC_SAERR_EN_MASK                                               (1 << 11)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VC_SAERR_ST_SHIFT                                              11
+#define OMAP54XX_VC_SAERR_ST_WIDTH                                              0x1
+#define OMAP54XX_VC_SAERR_ST_MASK                                               (1 << 11)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VC_TOERR_EN_SHIFT                                              13
+#define OMAP54XX_VC_TOERR_EN_WIDTH                                              0x1
+#define OMAP54XX_VC_TOERR_EN_MASK                                               (1 << 13)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VC_TOERR_ST_SHIFT                                              13
+#define OMAP54XX_VC_TOERR_ST_WIDTH                                              0x1
+#define OMAP54XX_VC_TOERR_ST_MASK                                               (1 << 13)
+
+/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+#define OMAP54XX_VDDMAX_SHIFT                                                   24
+#define OMAP54XX_VDDMAX_WIDTH                                                   0x8
+#define OMAP54XX_VDDMAX_MASK                                                    (0xff << 24)
+
+/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+#define OMAP54XX_VDDMIN_SHIFT                                                   16
+#define OMAP54XX_VDDMIN_WIDTH                                                   0x8
+#define OMAP54XX_VDDMIN_MASK                                                    (0xff << 16)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_VDD_CORE_I2C_DISABLE_SHIFT                                     12
+#define OMAP54XX_VDD_CORE_I2C_DISABLE_WIDTH                                     0x1
+#define OMAP54XX_VDD_CORE_I2C_DISABLE_MASK                                      (1 << 12)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_SHIFT                                    8
+#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_WIDTH                                    0x1
+#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_MASK                                     (1 << 8)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_VDD_MM_I2C_DISABLE_SHIFT                                       14
+#define OMAP54XX_VDD_MM_I2C_DISABLE_WIDTH                                       0x1
+#define OMAP54XX_VDD_MM_I2C_DISABLE_MASK                                        (1 << 14)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_VDD_MM_PRESENCE_SHIFT                                          9
+#define OMAP54XX_VDD_MM_PRESENCE_WIDTH                                          0x1
+#define OMAP54XX_VDD_MM_PRESENCE_MASK                                           (1 << 9)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_VDD_MM_VOLT_MGR_RST_SHIFT                                      7
+#define OMAP54XX_VDD_MM_VOLT_MGR_RST_WIDTH                                      0x1
+#define OMAP54XX_VDD_MM_VOLT_MGR_RST_MASK                                       (1 << 7)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_VDD_MPU_I2C_DISABLE_SHIFT                                      13
+#define OMAP54XX_VDD_MPU_I2C_DISABLE_WIDTH                                      0x1
+#define OMAP54XX_VDD_MPU_I2C_DISABLE_MASK                                       (1 << 13)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_VDD_MPU_PRESENCE_SHIFT                                         8
+#define OMAP54XX_VDD_MPU_PRESENCE_WIDTH                                         0x1
+#define OMAP54XX_VDD_MPU_PRESENCE_MASK                                          (1 << 8)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_SHIFT                                     6
+#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_WIDTH                                     0x1
+#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_MASK                                      (1 << 6)
+
+/* Used by PRM_VC_CORE_ERRST */
+#define OMAP54XX_VFSM_RA_ERR_CORE_SHIFT                                         4
+#define OMAP54XX_VFSM_RA_ERR_CORE_WIDTH                                         0x1
+#define OMAP54XX_VFSM_RA_ERR_CORE_MASK                                          (1 << 4)
+
+/* Used by PRM_VC_MM_ERRST */
+#define OMAP54XX_VFSM_RA_ERR_MM_SHIFT                                           4
+#define OMAP54XX_VFSM_RA_ERR_MM_WIDTH                                           0x1
+#define OMAP54XX_VFSM_RA_ERR_MM_MASK                                            (1 << 4)
+
+/* Used by PRM_VC_MPU_ERRST */
+#define OMAP54XX_VFSM_RA_ERR_MPU_SHIFT                                          4
+#define OMAP54XX_VFSM_RA_ERR_MPU_WIDTH                                          0x1
+#define OMAP54XX_VFSM_RA_ERR_MPU_MASK                                           (1 << 4)
+
+/* Used by PRM_VC_CORE_ERRST */
+#define OMAP54XX_VFSM_SA_ERR_CORE_SHIFT                                         3
+#define OMAP54XX_VFSM_SA_ERR_CORE_WIDTH                                         0x1
+#define OMAP54XX_VFSM_SA_ERR_CORE_MASK                                          (1 << 3)
+
+/* Used by PRM_VC_MM_ERRST */
+#define OMAP54XX_VFSM_SA_ERR_MM_SHIFT                                           3
+#define OMAP54XX_VFSM_SA_ERR_MM_WIDTH                                           0x1
+#define OMAP54XX_VFSM_SA_ERR_MM_MASK                                            (1 << 3)
+
+/* Used by PRM_VC_MPU_ERRST */
+#define OMAP54XX_VFSM_SA_ERR_MPU_SHIFT                                          3
+#define OMAP54XX_VFSM_SA_ERR_MPU_WIDTH                                          0x1
+#define OMAP54XX_VFSM_SA_ERR_MPU_MASK                                           (1 << 3)
+
+/* Used by PRM_VC_CORE_ERRST */
+#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_SHIFT                                    5
+#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_WIDTH                                    0x1
+#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_MASK                                     (1 << 5)
+
+/* Used by PRM_VC_MM_ERRST */
+#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_SHIFT                                      5
+#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_WIDTH                                      0x1
+#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_MASK                                       (1 << 5)
+
+/* Used by PRM_VC_MPU_ERRST */
+#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_SHIFT                                     5
+#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_WIDTH                                     0x1
+#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_MASK                                      (1 << 5)
+
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_VOLRA_VDD_CORE_L_SHIFT                                         8
+#define OMAP54XX_VOLRA_VDD_CORE_L_WIDTH                                         0x8
+#define OMAP54XX_VOLRA_VDD_CORE_L_MASK                                          (0xff << 8)
+
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_VOLRA_VDD_MM_L_SHIFT                                           8
+#define OMAP54XX_VOLRA_VDD_MM_L_WIDTH                                           0x8
+#define OMAP54XX_VOLRA_VDD_MM_L_MASK                                            (0xff << 8)
+
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_VOLRA_VDD_MPU_L_SHIFT                                          8
+#define OMAP54XX_VOLRA_VDD_MPU_L_WIDTH                                          0x8
+#define OMAP54XX_VOLRA_VDD_MPU_L_MASK                                           (0xff << 8)
+
+/* Used by PRM_VOLTST_MM, PRM_VOLTST_MPU */
+#define OMAP54XX_VOLTSTATEST_SHIFT                                              0
+#define OMAP54XX_VOLTSTATEST_WIDTH                                              0x2
+#define OMAP54XX_VOLTSTATEST_MASK                                               (0x3 << 0)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_VPENABLE_SHIFT                                                 0
+#define OMAP54XX_VPENABLE_WIDTH                                                 0x1
+#define OMAP54XX_VPENABLE_MASK                                                  (1 << 0)
+
+/* Used by PRM_VP_CORE_STATUS, PRM_VP_MM_STATUS, PRM_VP_MPU_STATUS */
+#define OMAP54XX_VPINIDLE_SHIFT                                                 0
+#define OMAP54XX_VPINIDLE_WIDTH                                                 0x1
+#define OMAP54XX_VPINIDLE_MASK                                                  (1 << 0)
+
+/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */
+#define OMAP54XX_VPVOLTAGE_SHIFT                                                0
+#define OMAP54XX_VPVOLTAGE_WIDTH                                                0x8
+#define OMAP54XX_VPVOLTAGE_MASK                                                 (0xff << 0)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_CORE_EQVALUE_EN_SHIFT                                       20
+#define OMAP54XX_VP_CORE_EQVALUE_EN_WIDTH                                       0x1
+#define OMAP54XX_VP_CORE_EQVALUE_EN_MASK                                        (1 << 20)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_CORE_EQVALUE_ST_SHIFT                                       20
+#define OMAP54XX_VP_CORE_EQVALUE_ST_WIDTH                                       0x1
+#define OMAP54XX_VP_CORE_EQVALUE_ST_MASK                                        (1 << 20)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_CORE_MAXVDD_EN_SHIFT                                        18
+#define OMAP54XX_VP_CORE_MAXVDD_EN_WIDTH                                        0x1
+#define OMAP54XX_VP_CORE_MAXVDD_EN_MASK                                         (1 << 18)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_CORE_MAXVDD_ST_SHIFT                                        18
+#define OMAP54XX_VP_CORE_MAXVDD_ST_WIDTH                                        0x1
+#define OMAP54XX_VP_CORE_MAXVDD_ST_MASK                                         (1 << 18)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_CORE_MINVDD_EN_SHIFT                                        17
+#define OMAP54XX_VP_CORE_MINVDD_EN_WIDTH                                        0x1
+#define OMAP54XX_VP_CORE_MINVDD_EN_MASK                                         (1 << 17)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_CORE_MINVDD_ST_SHIFT                                        17
+#define OMAP54XX_VP_CORE_MINVDD_ST_WIDTH                                        0x1
+#define OMAP54XX_VP_CORE_MINVDD_ST_MASK                                         (1 << 17)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_CORE_NOSMPSACK_EN_SHIFT                                     19
+#define OMAP54XX_VP_CORE_NOSMPSACK_EN_WIDTH                                     0x1
+#define OMAP54XX_VP_CORE_NOSMPSACK_EN_MASK                                      (1 << 19)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_CORE_NOSMPSACK_ST_SHIFT                                     19
+#define OMAP54XX_VP_CORE_NOSMPSACK_ST_WIDTH                                     0x1
+#define OMAP54XX_VP_CORE_NOSMPSACK_ST_MASK                                      (1 << 19)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_SHIFT                                 16
+#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_WIDTH                                 0x1
+#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_MASK                                  (1 << 16)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_SHIFT                                 16
+#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_WIDTH                                 0x1
+#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_MASK                                  (1 << 16)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_CORE_TRANXDONE_EN_SHIFT                                     21
+#define OMAP54XX_VP_CORE_TRANXDONE_EN_WIDTH                                     0x1
+#define OMAP54XX_VP_CORE_TRANXDONE_EN_MASK                                      (1 << 21)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_CORE_TRANXDONE_ST_SHIFT                                     21
+#define OMAP54XX_VP_CORE_TRANXDONE_ST_WIDTH                                     0x1
+#define OMAP54XX_VP_CORE_TRANXDONE_ST_MASK                                      (1 << 21)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_MM_EQVALUE_EN_SHIFT                                         28
+#define OMAP54XX_VP_MM_EQVALUE_EN_WIDTH                                         0x1
+#define OMAP54XX_VP_MM_EQVALUE_EN_MASK                                          (1 << 28)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_MM_EQVALUE_ST_SHIFT                                         28
+#define OMAP54XX_VP_MM_EQVALUE_ST_WIDTH                                         0x1
+#define OMAP54XX_VP_MM_EQVALUE_ST_MASK                                          (1 << 28)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_MM_MAXVDD_EN_SHIFT                                          26
+#define OMAP54XX_VP_MM_MAXVDD_EN_WIDTH                                          0x1
+#define OMAP54XX_VP_MM_MAXVDD_EN_MASK                                           (1 << 26)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_MM_MAXVDD_ST_SHIFT                                          26
+#define OMAP54XX_VP_MM_MAXVDD_ST_WIDTH                                          0x1
+#define OMAP54XX_VP_MM_MAXVDD_ST_MASK                                           (1 << 26)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_MM_MINVDD_EN_SHIFT                                          25
+#define OMAP54XX_VP_MM_MINVDD_EN_WIDTH                                          0x1
+#define OMAP54XX_VP_MM_MINVDD_EN_MASK                                           (1 << 25)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_MM_MINVDD_ST_SHIFT                                          25
+#define OMAP54XX_VP_MM_MINVDD_ST_WIDTH                                          0x1
+#define OMAP54XX_VP_MM_MINVDD_ST_MASK                                           (1 << 25)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_MM_NOSMPSACK_EN_SHIFT                                       27
+#define OMAP54XX_VP_MM_NOSMPSACK_EN_WIDTH                                       0x1
+#define OMAP54XX_VP_MM_NOSMPSACK_EN_MASK                                        (1 << 27)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_MM_NOSMPSACK_ST_SHIFT                                       27
+#define OMAP54XX_VP_MM_NOSMPSACK_ST_WIDTH                                       0x1
+#define OMAP54XX_VP_MM_NOSMPSACK_ST_MASK                                        (1 << 27)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_SHIFT                                   24
+#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_WIDTH                                   0x1
+#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_MASK                                    (1 << 24)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_SHIFT                                   24
+#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_WIDTH                                   0x1
+#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_MASK                                    (1 << 24)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_MM_TRANXDONE_EN_SHIFT                                       29
+#define OMAP54XX_VP_MM_TRANXDONE_EN_WIDTH                                       0x1
+#define OMAP54XX_VP_MM_TRANXDONE_EN_MASK                                        (1 << 29)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_MM_TRANXDONE_ST_SHIFT                                       29
+#define OMAP54XX_VP_MM_TRANXDONE_ST_WIDTH                                       0x1
+#define OMAP54XX_VP_MM_TRANXDONE_ST_MASK                                        (1 << 29)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VP_MPU_EQVALUE_EN_SHIFT                                        4
+#define OMAP54XX_VP_MPU_EQVALUE_EN_WIDTH                                        0x1
+#define OMAP54XX_VP_MPU_EQVALUE_EN_MASK                                         (1 << 4)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VP_MPU_EQVALUE_ST_SHIFT                                        4
+#define OMAP54XX_VP_MPU_EQVALUE_ST_WIDTH                                        0x1
+#define OMAP54XX_VP_MPU_EQVALUE_ST_MASK                                         (1 << 4)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VP_MPU_MAXVDD_EN_SHIFT                                         2
+#define OMAP54XX_VP_MPU_MAXVDD_EN_WIDTH                                         0x1
+#define OMAP54XX_VP_MPU_MAXVDD_EN_MASK                                          (1 << 2)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VP_MPU_MAXVDD_ST_SHIFT                                         2
+#define OMAP54XX_VP_MPU_MAXVDD_ST_WIDTH                                         0x1
+#define OMAP54XX_VP_MPU_MAXVDD_ST_MASK                                          (1 << 2)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VP_MPU_MINVDD_EN_SHIFT                                         1
+#define OMAP54XX_VP_MPU_MINVDD_EN_WIDTH                                         0x1
+#define OMAP54XX_VP_MPU_MINVDD_EN_MASK                                          (1 << 1)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VP_MPU_MINVDD_ST_SHIFT                                         1
+#define OMAP54XX_VP_MPU_MINVDD_ST_WIDTH                                         0x1
+#define OMAP54XX_VP_MPU_MINVDD_ST_MASK                                          (1 << 1)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VP_MPU_NOSMPSACK_EN_SHIFT                                      3
+#define OMAP54XX_VP_MPU_NOSMPSACK_EN_WIDTH                                      0x1
+#define OMAP54XX_VP_MPU_NOSMPSACK_EN_MASK                                       (1 << 3)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VP_MPU_NOSMPSACK_ST_SHIFT                                      3
+#define OMAP54XX_VP_MPU_NOSMPSACK_ST_WIDTH                                      0x1
+#define OMAP54XX_VP_MPU_NOSMPSACK_ST_MASK                                       (1 << 3)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_SHIFT                                  0
+#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_WIDTH                                  0x1
+#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_MASK                                   (1 << 0)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_SHIFT                                  0
+#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_WIDTH                                  0x1
+#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_MASK                                   (1 << 0)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VP_MPU_TRANXDONE_EN_SHIFT                                      5
+#define OMAP54XX_VP_MPU_TRANXDONE_EN_WIDTH                                      0x1
+#define OMAP54XX_VP_MPU_TRANXDONE_EN_MASK                                       (1 << 5)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VP_MPU_TRANXDONE_ST_SHIFT                                      5
+#define OMAP54XX_VP_MPU_TRANXDONE_ST_WIDTH                                      0x1
+#define OMAP54XX_VP_MPU_TRANXDONE_ST_MASK                                       (1 << 5)
+
+/* Used by PRM_SRAM_COUNT */
+#define OMAP54XX_VSETUPCNT_VALUE_SHIFT                                          8
+#define OMAP54XX_VSETUPCNT_VALUE_WIDTH                                          0x8
+#define OMAP54XX_VSETUPCNT_VALUE_MASK                                           (0xff << 8)
+
+/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
+#define OMAP54XX_VSTEPMAX_SHIFT                                                 0
+#define OMAP54XX_VSTEPMAX_WIDTH                                                 0x8
+#define OMAP54XX_VSTEPMAX_MASK                                                  (0xff << 0)
+
+/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
+#define OMAP54XX_VSTEPMIN_SHIFT                                                 0
+#define OMAP54XX_VSTEPMIN_WIDTH                                                 0x8
+#define OMAP54XX_VSTEPMIN_MASK                                                  (0xff << 0)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DISPC_DSP_SHIFT                                        2
+#define OMAP54XX_WKUPDEP_DISPC_DSP_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_DISPC_DSP_MASK                                         (1 << 2)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DISPC_IPU_SHIFT                                        1
+#define OMAP54XX_WKUPDEP_DISPC_IPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_DISPC_IPU_MASK                                         (1 << 1)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DISPC_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_DISPC_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_DISPC_MPU_MASK                                         (1 << 0)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DISPC_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_DISPC_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DISPC_SDMA_MASK                                        (1 << 3)
+
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_SHIFT                                     6
+#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_MASK                                      (1 << 6)
+
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_SHIFT                                    7
+#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_MASK                                     (1 << 7)
+
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_SHIFT                                     2
+#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_MASK                                      (1 << 2)
+
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_SHIFT                                     0
+#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_MASK                                      (1 << 0)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_A_DSP_SHIFT                                       6
+#define OMAP54XX_WKUPDEP_DSI1_A_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_A_DSP_MASK                                        (1 << 6)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_A_IPU_SHIFT                                       5
+#define OMAP54XX_WKUPDEP_DSI1_A_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_A_IPU_MASK                                        (1 << 5)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_A_MPU_SHIFT                                       4
+#define OMAP54XX_WKUPDEP_DSI1_A_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_A_MPU_MASK                                        (1 << 4)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_SHIFT                                      7
+#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_MASK                                       (1 << 7)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_B_DSP_SHIFT                                       10
+#define OMAP54XX_WKUPDEP_DSI1_B_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_B_DSP_MASK                                        (1 << 10)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_B_IPU_SHIFT                                       9
+#define OMAP54XX_WKUPDEP_DSI1_B_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_B_IPU_MASK                                        (1 << 9)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_B_MPU_SHIFT                                       8
+#define OMAP54XX_WKUPDEP_DSI1_B_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_B_MPU_MASK                                        (1 << 8)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_SHIFT                                      11
+#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_MASK                                       (1 << 11)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_C_DSP_SHIFT                                       17
+#define OMAP54XX_WKUPDEP_DSI1_C_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_C_DSP_MASK                                        (1 << 17)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_C_IPU_SHIFT                                       16
+#define OMAP54XX_WKUPDEP_DSI1_C_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_C_IPU_MASK                                        (1 << 16)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_C_MPU_SHIFT                                       15
+#define OMAP54XX_WKUPDEP_DSI1_C_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_C_MPU_MASK                                        (1 << 15)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_SHIFT                                      18
+#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_MASK                                       (1 << 18)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_SHIFT                                   1
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_MASK                                    (1 << 1)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_MASK                                    (1 << 0)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_SHIFT                                   6
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_MASK                                    (1 << 6)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_SHIFT                                   1
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_MASK                                    (1 << 1)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_MASK                                    (1 << 0)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_SHIFT                                   6
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_MASK                                    (1 << 6)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_MASK                                    (1 << 0)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_SHIFT                                   6
+#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_MASK                                    (1 << 6)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_MASK                                    (1 << 0)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_SHIFT                                   6
+#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_MASK                                    (1 << 6)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_MASK                                    (1 << 0)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_SHIFT                                   6
+#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_MASK                                    (1 << 6)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_MASK                                    (1 << 0)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_SHIFT                                   6
+#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_MASK                                    (1 << 6)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_MASK                                    (1 << 0)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_MASK                                    (1 << 0)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_SHIFT                                     19
+#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_MASK                                      (1 << 19)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_SHIFT                                      14
+#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_MASK                                       (1 << 14)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_SHIFT                                      13
+#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_MASK                                       (1 << 13)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_SHIFT                                      12
+#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_MASK                                       (1 << 12)
+
+/* Used by PM_L3INIT_HSI_WKDEP */
+#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_SHIFT                                      6
+#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_MASK                                       (1 << 6)
+
+/* Used by PM_L3INIT_HSI_WKDEP */
+#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_SHIFT                                      1
+#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_MASK                                       (1 << 1)
+
+/* Used by PM_L3INIT_HSI_WKDEP */
+#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_SHIFT                                      0
+#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_MASK                                       (1 << 0)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_SHIFT                                    7
+#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_MASK                                     (1 << 7)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_SHIFT                                     1
+#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_MASK                                      (1 << 1)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_SHIFT                                     0
+#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_MASK                                      (1 << 0)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_SHIFT                                    7
+#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_MASK                                     (1 << 7)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_SHIFT                                     1
+#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_MASK                                      (1 << 1)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_SHIFT                                     0
+#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_MASK                                      (1 << 0)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_SHIFT                                    7
+#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_MASK                                     (1 << 7)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_SHIFT                                     1
+#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_MASK                                      (1 << 1)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_SHIFT                                     0
+#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_MASK                                      (1 << 0)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_SHIFT                                    7
+#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_MASK                                     (1 << 7)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_SHIFT                                     1
+#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_MASK                                      (1 << 1)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_SHIFT                                     0
+#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_MASK                                      (1 << 0)
+
+/* Used by PM_L4PER_I2C5_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_SHIFT                                     0
+#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_MASK                                      (1 << 0)
+
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define OMAP54XX_WKUPDEP_KBD_MPU_SHIFT                                          0
+#define OMAP54XX_WKUPDEP_KBD_MPU_WIDTH                                          0x1
+#define OMAP54XX_WKUPDEP_KBD_MPU_MASK                                           (1 << 0)
+
+/* Used by PM_ABE_MCASP_WKDEP */
+#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_SHIFT                                    6
+#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_MASK                                     (1 << 6)
+
+/* Used by PM_ABE_MCASP_WKDEP */
+#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_SHIFT                                   7
+#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_MASK                                    (1 << 7)
+
+/* Used by PM_ABE_MCASP_WKDEP */
+#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_SHIFT                                    2
+#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_MASK                                     (1 << 2)
+
+/* Used by PM_ABE_MCASP_WKDEP */
+#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_SHIFT                                    0
+#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_MASK                                     (1 << 0)
+
+/* Used by PM_ABE_MCBSP1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP1_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_MCBSP1_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCBSP1_DSP_MASK                                        (1 << 2)
+
+/* Used by PM_ABE_MCBSP1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP1_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCBSP1_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCBSP1_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_ABE_MCBSP1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_MASK                                       (1 << 3)
+
+/* Used by PM_ABE_MCBSP2_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP2_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_MCBSP2_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCBSP2_DSP_MASK                                        (1 << 2)
+
+/* Used by PM_ABE_MCBSP2_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP2_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCBSP2_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCBSP2_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_ABE_MCBSP2_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_MASK                                       (1 << 3)
+
+/* Used by PM_ABE_MCBSP3_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP3_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_MCBSP3_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCBSP3_DSP_MASK                                        (1 << 2)
+
+/* Used by PM_ABE_MCBSP3_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP3_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCBSP3_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCBSP3_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_ABE_MCBSP3_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_MASK                                       (1 << 3)
+
+/* Used by PM_ABE_MCPDM_WKDEP */
+#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_SHIFT                                    6
+#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_MASK                                     (1 << 6)
+
+/* Used by PM_ABE_MCPDM_WKDEP */
+#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_SHIFT                                   7
+#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_MASK                                    (1 << 7)
+
+/* Used by PM_ABE_MCPDM_WKDEP */
+#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_SHIFT                                    2
+#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_MASK                                     (1 << 2)
+
+/* Used by PM_ABE_MCPDM_WKDEP */
+#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_SHIFT                                    0
+#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_MASK                                     (1 << 0)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI1_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_MCSPI1_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI1_DSP_MASK                                        (1 << 2)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI1_IPU_SHIFT                                       1
+#define OMAP54XX_WKUPDEP_MCSPI1_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI1_IPU_MASK                                        (1 << 1)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI1_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCSPI1_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI1_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_MASK                                       (1 << 3)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI2_IPU_SHIFT                                       1
+#define OMAP54XX_WKUPDEP_MCSPI2_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI2_IPU_MASK                                        (1 << 1)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI2_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCSPI2_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI2_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_MASK                                       (1 << 3)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI3_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCSPI3_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI3_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_MASK                                       (1 << 3)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI4_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCSPI4_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI4_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_MASK                                       (1 << 3)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC1_DSP_SHIFT                                         2
+#define OMAP54XX_WKUPDEP_MMC1_DSP_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC1_DSP_MASK                                          (1 << 2)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC1_IPU_SHIFT                                         1
+#define OMAP54XX_WKUPDEP_MMC1_IPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC1_IPU_MASK                                          (1 << 1)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC1_MPU_SHIFT                                         0
+#define OMAP54XX_WKUPDEP_MMC1_MPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC1_MPU_MASK                                          (1 << 0)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC1_SDMA_SHIFT                                        3
+#define OMAP54XX_WKUPDEP_MMC1_SDMA_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_MMC1_SDMA_MASK                                         (1 << 3)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC2_DSP_SHIFT                                         2
+#define OMAP54XX_WKUPDEP_MMC2_DSP_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC2_DSP_MASK                                          (1 << 2)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC2_IPU_SHIFT                                         1
+#define OMAP54XX_WKUPDEP_MMC2_IPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC2_IPU_MASK                                          (1 << 1)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC2_MPU_SHIFT                                         0
+#define OMAP54XX_WKUPDEP_MMC2_MPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC2_MPU_MASK                                          (1 << 0)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC2_SDMA_SHIFT                                        3
+#define OMAP54XX_WKUPDEP_MMC2_SDMA_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_MMC2_SDMA_MASK                                         (1 << 3)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC3_IPU_SHIFT                                         1
+#define OMAP54XX_WKUPDEP_MMC3_IPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC3_IPU_MASK                                          (1 << 1)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC3_MPU_SHIFT                                         0
+#define OMAP54XX_WKUPDEP_MMC3_MPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC3_MPU_MASK                                          (1 << 0)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC3_SDMA_SHIFT                                        3
+#define OMAP54XX_WKUPDEP_MMC3_SDMA_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_MMC3_SDMA_MASK                                         (1 << 3)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC4_MPU_SHIFT                                         0
+#define OMAP54XX_WKUPDEP_MMC4_MPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC4_MPU_MASK                                          (1 << 0)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC4_SDMA_SHIFT                                        3
+#define OMAP54XX_WKUPDEP_MMC4_SDMA_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_MMC4_SDMA_MASK                                         (1 << 3)
+
+/* Used by PM_L4PER_MMC5_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC5_MPU_SHIFT                                         0
+#define OMAP54XX_WKUPDEP_MMC5_MPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC5_MPU_MASK                                          (1 << 0)
+
+/* Used by PM_L4PER_MMC5_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC5_SDMA_SHIFT                                        3
+#define OMAP54XX_WKUPDEP_MMC5_SDMA_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_MMC5_SDMA_MASK                                         (1 << 3)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define OMAP54XX_WKUPDEP_SATA_MPU_SHIFT                                         0
+#define OMAP54XX_WKUPDEP_SATA_MPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_SATA_MPU_MASK                                          (1 << 0)
+
+/* Used by PM_ABE_SLIMBUS1_WKDEP */
+#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_SHIFT                                 6
+#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_WIDTH                                 0x1
+#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_MASK                                  (1 << 6)
+
+/* Used by PM_ABE_SLIMBUS1_WKDEP */
+#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT                                7
+#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_WIDTH                                0x1
+#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK                                 (1 << 7)
+
+/* Used by PM_ABE_SLIMBUS1_WKDEP */
+#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_SHIFT                                 2
+#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_WIDTH                                 0x1
+#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_MASK                                  (1 << 2)
+
+/* Used by PM_ABE_SLIMBUS1_WKDEP */
+#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT                                 0
+#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_WIDTH                                 0x1
+#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK                                  (1 << 0)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_SHIFT                             1
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_WIDTH                             0x1
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_MASK                              (1 << 1)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_SHIFT                             0
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_WIDTH                             0x1
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_MASK                              (1 << 0)
+
+/* Used by PM_COREAON_SMARTREFLEX_MM_WKDEP */
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_SHIFT                               0
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_WIDTH                               0x1
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_MASK                                (1 << 0)
+
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_SHIFT                              0
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_WIDTH                              0x1
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_MASK                               (1 << 0)
+
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER10_MPU_SHIFT                                      0
+#define OMAP54XX_WKUPDEP_TIMER10_MPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_TIMER10_MPU_MASK                                       (1 << 0)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER11_IPU_SHIFT                                      1
+#define OMAP54XX_WKUPDEP_TIMER11_IPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_TIMER11_IPU_MASK                                       (1 << 1)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER11_MPU_SHIFT                                      0
+#define OMAP54XX_WKUPDEP_TIMER11_MPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_TIMER11_MPU_MASK                                       (1 << 0)
+
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER12_MPU_SHIFT                                      0
+#define OMAP54XX_WKUPDEP_TIMER12_MPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_TIMER12_MPU_MASK                                       (1 << 0)
+
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER1_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER1_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER1_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER2_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER2_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER2_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER3_IPU_SHIFT                                       1
+#define OMAP54XX_WKUPDEP_TIMER3_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER3_IPU_MASK                                        (1 << 1)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER3_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER3_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER3_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER4_IPU_SHIFT                                       1
+#define OMAP54XX_WKUPDEP_TIMER4_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER4_IPU_MASK                                        (1 << 1)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER4_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER4_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER4_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_ABE_TIMER5_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER5_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_TIMER5_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER5_DSP_MASK                                        (1 << 2)
+
+/* Used by PM_ABE_TIMER5_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER5_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER5_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER5_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_ABE_TIMER6_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER6_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_TIMER6_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER6_DSP_MASK                                        (1 << 2)
+
+/* Used by PM_ABE_TIMER6_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER6_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER6_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER6_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_ABE_TIMER7_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER7_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_TIMER7_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER7_DSP_MASK                                        (1 << 2)
+
+/* Used by PM_ABE_TIMER7_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER7_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER7_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER7_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_ABE_TIMER8_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER8_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_TIMER8_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER8_DSP_MASK                                        (1 << 2)
+
+/* Used by PM_ABE_TIMER8_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER8_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER8_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER8_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER9_IPU_SHIFT                                       1
+#define OMAP54XX_WKUPDEP_TIMER9_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER9_IPU_MASK                                        (1 << 1)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER9_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER9_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER9_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define OMAP54XX_WKUPDEP_UART1_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_UART1_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART1_MPU_MASK                                         (1 << 0)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define OMAP54XX_WKUPDEP_UART1_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_UART1_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_UART1_SDMA_MASK                                        (1 << 3)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define OMAP54XX_WKUPDEP_UART2_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_UART2_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART2_MPU_MASK                                         (1 << 0)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define OMAP54XX_WKUPDEP_UART2_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_UART2_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_UART2_SDMA_MASK                                        (1 << 3)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define OMAP54XX_WKUPDEP_UART3_DSP_SHIFT                                        2
+#define OMAP54XX_WKUPDEP_UART3_DSP_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART3_DSP_MASK                                         (1 << 2)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define OMAP54XX_WKUPDEP_UART3_IPU_SHIFT                                        1
+#define OMAP54XX_WKUPDEP_UART3_IPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART3_IPU_MASK                                         (1 << 1)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define OMAP54XX_WKUPDEP_UART3_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_UART3_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART3_MPU_MASK                                         (1 << 0)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define OMAP54XX_WKUPDEP_UART3_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_UART3_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_UART3_SDMA_MASK                                        (1 << 3)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define OMAP54XX_WKUPDEP_UART4_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_UART4_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART4_MPU_MASK                                         (1 << 0)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define OMAP54XX_WKUPDEP_UART4_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_UART4_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_UART4_SDMA_MASK                                        (1 << 3)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define OMAP54XX_WKUPDEP_UART5_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_UART5_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART5_MPU_MASK                                         (1 << 0)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define OMAP54XX_WKUPDEP_UART5_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_UART5_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_UART5_SDMA_MASK                                        (1 << 3)
+
+/* Used by PM_L4PER_UART6_WKDEP */
+#define OMAP54XX_WKUPDEP_UART6_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_UART6_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART6_MPU_MASK                                         (1 << 0)
+
+/* Used by PM_L4PER_UART6_WKDEP */
+#define OMAP54XX_WKUPDEP_UART6_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_UART6_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_UART6_SDMA_MASK                                        (1 << 3)
+
+/* Used by PM_L3INIT_UNIPRO2_WKDEP */
+#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_SHIFT                                      0
+#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_MASK                                       (1 << 0)
+
+/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */
+#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_SHIFT                                  1
+#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_WIDTH                                  0x1
+#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_MASK                                   (1 << 1)
+
+/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */
+#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_SHIFT                                  0
+#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_WIDTH                                  0x1
+#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_MASK                                   (1 << 0)
+
+/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */
+#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_SHIFT                                   1
+#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_MASK                                    (1 << 1)
+
+/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */
+#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_MASK                                    (1 << 0)
+
+/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */
+#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_SHIFT                                   1
+#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_MASK                                    (1 << 1)
+
+/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */
+#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_MASK                                    (1 << 0)
+
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_SHIFT                                    0
+#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_MASK                                     (1 << 0)
+
+/* Used by PM_ABE_WD_TIMER3_WKDEP */
+#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_SHIFT                                    0
+#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_MASK                                     (1 << 0)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_WUCLK_CTRL_SHIFT                                               8
+#define OMAP54XX_WUCLK_CTRL_WIDTH                                               0x1
+#define OMAP54XX_WUCLK_CTRL_MASK                                                (1 << 8)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_WUCLK_STATUS_SHIFT                                             9
+#define OMAP54XX_WUCLK_STATUS_WIDTH                                             0x1
+#define OMAP54XX_WUCLK_STATUS_MASK                                              (1 << 9)
+
+/* Used by REVISION_PRM */
+#define OMAP54XX_X_MAJOR_SHIFT                                                  8
+#define OMAP54XX_X_MAJOR_WIDTH                                                  0x3
+#define OMAP54XX_X_MAJOR_MASK                                                   (0x7 << 8)
+
+/* Used by REVISION_PRM */
+#define OMAP54XX_Y_MINOR_SHIFT                                                  0
+#define OMAP54XX_Y_MINOR_WIDTH                                                  0x6
+#define OMAP54XX_Y_MINOR_MASK                                                   (0x3f << 0)
+#endif
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 44c0d7216aa7..720440737744 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -320,6 +320,12 @@ static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
         return 0;
 }
 
+static int am33xx_check_vcvp(void)
+{
+        /* No VC/VP on am33xx devices */
+        return 0;
+}
+
 struct pwrdm_ops am33xx_pwrdm_operations = {
         .pwrdm_set_next_pwrst           = am33xx_pwrdm_set_next_pwrst,
         .pwrdm_read_next_pwrst          = am33xx_pwrdm_read_next_pwrst,
@@ -335,4 +341,5 @@ struct pwrdm_ops am33xx_pwrdm_operations = {
         .pwrdm_set_mem_onst             = am33xx_pwrdm_set_mem_onst,
         .pwrdm_set_mem_retst            = am33xx_pwrdm_set_mem_retst,
         .pwrdm_wait_transition          = am33xx_pwrdm_wait_transition,
+        .pwrdm_has_voltdm               = am33xx_check_vcvp,
 };
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 8ee1fbdec561..7db2422faa16 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -25,6 +25,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
 
+#include "prm44xx_54xx.h"
 #include "prcm-common.h"
 #include "prm.h"
 
@@ -744,36 +745,4 @@
 #define OMAP4_PRM_VC_ERRST_OFFSET                       0x00f8
 #define OMAP4430_PRM_VC_ERRST                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
 
-/* Function prototypes */
-# ifndef __ASSEMBLER__
-
-extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-
-/* OMAP4-specific VP functions */
-u32 omap4_prm_vp_check_txdone(u8 vp_id);
-void omap4_prm_vp_clear_txdone(u8 vp_id);
-
-/*
- * OMAP4 access functions for voltage controller (VC) and
- * voltage proccessor (VP) in the PRM.
- */
-extern u32 omap4_prm_vcvp_read(u8 offset);
-extern void omap4_prm_vcvp_write(u32 val, u8 offset);
-extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
-
-extern void omap44xx_prm_reconfigure_io_chain(void);
-
-/* PRM interrupt-related functions */
-extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
-extern void omap44xx_prm_ocp_barrier(void);
-extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
-extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
-
-extern int __init omap44xx_prm_init(void);
-extern u32 omap44xx_prm_get_reset_sources(void);
-
-# endif
-
 #endif
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
new file mode 100644
index 000000000000..7cd22abb8f15
--- /dev/null
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -0,0 +1,58 @@
+/*
+ * OMAP44xx and 54xx PRM common functions
+ *
+ * Copyright (C) 2009-2013 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
+
+/* Function prototypes */
+#ifndef __ASSEMBLER__
+
+extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+/* OMAP4/OMAP5-specific VP functions */
+u32 omap4_prm_vp_check_txdone(u8 vp_id);
+void omap4_prm_vp_clear_txdone(u8 vp_id);
+
+/*
+ * OMAP4/OMAP5 access functions for voltage controller (VC) and
+ * voltage proccessor (VP) in the PRM.
+ */
+extern u32 omap4_prm_vcvp_read(u8 offset);
+extern void omap4_prm_vcvp_write(u32 val, u8 offset);
+extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
+
+extern void omap44xx_prm_reconfigure_io_chain(void);
+
+/* PRM interrupt-related functions */
+extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
+extern void omap44xx_prm_ocp_barrier(void);
+extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
+extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
+
+extern int __init omap44xx_prm_init(void);
+extern u32 omap44xx_prm_get_reset_sources(void);
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h
new file mode 100644
index 000000000000..e4411010309c
--- /dev/null
+++ b/arch/arm/mach-omap2/prm54xx.h
@@ -0,0 +1,421 @@
+/*
+ * OMAP54xx PRM instance offset macros
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM54XX_H
+
+#include "prm44xx_54xx.h"
+#include "prcm-common.h"
+#include "prm.h"
+
+#define OMAP54XX_PRM_BASE               0x4ae06000
+
+#define OMAP54XX_PRM_REGADDR(inst, reg)                         \
+        OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE + (inst) + (reg))
+
+
+/* PRM instances */
+#define OMAP54XX_PRM_OCP_SOCKET_INST    0x0000
+#define OMAP54XX_PRM_CKGEN_INST         0x0100
+#define OMAP54XX_PRM_MPU_INST           0x0300
+#define OMAP54XX_PRM_DSP_INST           0x0400
+#define OMAP54XX_PRM_ABE_INST           0x0500
+#define OMAP54XX_PRM_COREAON_INST       0x0600
+#define OMAP54XX_PRM_CORE_INST          0x0700
+#define OMAP54XX_PRM_IVA_INST           0x1200
+#define OMAP54XX_PRM_CAM_INST           0x1300
+#define OMAP54XX_PRM_DSS_INST           0x1400
+#define OMAP54XX_PRM_GPU_INST           0x1500
+#define OMAP54XX_PRM_L3INIT_INST        0x1600
+#define OMAP54XX_PRM_CUSTEFUSE_INST     0x1700
+#define OMAP54XX_PRM_WKUPAON_INST       0x1800
+#define OMAP54XX_PRM_WKUPAON_CM_INST    0x1900
+#define OMAP54XX_PRM_EMU_INST           0x1a00
+#define OMAP54XX_PRM_EMU_CM_INST        0x1b00
+#define OMAP54XX_PRM_DEVICE_INST        0x1c00
+#define OMAP54XX_PRM_INSTR_INST         0x1f00
+
+/* PRM clockdomain register offsets (from instance start) */
+#define OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS  0x0000
+#define OMAP54XX_PRM_EMU_CM_EMU_CDOFFS          0x0000
+
+/* PRM */
+
+/* PRM.OCP_SOCKET_PRM register offsets */
+#define OMAP54XX_REVISION_PRM_OFFSET                            0x0000
+#define OMAP54XX_PRM_IRQSTATUS_MPU_OFFSET                       0x0010
+#define OMAP54XX_PRM_IRQSTATUS_MPU_2_OFFSET                     0x0014
+#define OMAP54XX_PRM_IRQENABLE_MPU_OFFSET                       0x0018
+#define OMAP54XX_PRM_IRQENABLE_MPU_2_OFFSET                     0x001c
+#define OMAP54XX_PRM_IRQSTATUS_IPU_OFFSET                       0x0020
+#define OMAP54XX_PRM_IRQENABLE_IPU_OFFSET                       0x0028
+#define OMAP54XX_PRM_IRQSTATUS_DSP_OFFSET                       0x0030
+#define OMAP54XX_PRM_IRQENABLE_DSP_OFFSET                       0x0038
+#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL_OFFSET                0x0040
+#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL                       OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_OCP_SOCKET_INST, 0x0040)
+#define OMAP54XX_PRM_DEBUG_OUT_OFFSET                           0x0084
+#define OMAP54XX_PRM_DEBUG_TRANS_CFG_OFFSET                     0x0090
+#define OMAP54XX_PRM_DEBUG_OFF_TRANS_OFFSET                     0x0094
+#define OMAP54XX_PRM_DEBUG_CORE_RET_TRANS_OFFSET                0x0098
+#define OMAP54XX_PRM_DEBUG_MPU_RET_TRANS_OFFSET                 0x009c
+#define OMAP54XX_PRM_DEBUG_MM_RET_TRANS_OFFSET                  0x00a0
+#define OMAP54XX_PRM_DEBUG_WKUPAON_FD_TRANS_OFFSET              0x00a4
+
+/* PRM.CKGEN_PRM register offsets */
+#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS_OFFSET                   0x0000
+#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS                          OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0000)
+#define OMAP54XX_CM_CLKSEL_WKUPAON_OFFSET                       0x0008
+#define OMAP54XX_CM_CLKSEL_WKUPAON                              OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0008)
+#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF_OFFSET                   0x000c
+#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF                          OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x000c)
+#define OMAP54XX_CM_CLKSEL_SYS_OFFSET                           0x0010
+#define OMAP54XX_CM_CLKSEL_SYS                                  OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0010)
+
+/* PRM.MPU_PRM register offsets */
+#define OMAP54XX_PM_MPU_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_MPU_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET                      0x0024
+
+/* PRM.DSP_PRM register offsets */
+#define OMAP54XX_PM_DSP_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_DSP_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_DSP_RSTCTRL_OFFSET                          0x0010
+#define OMAP54XX_RM_DSP_RSTST_OFFSET                            0x0014
+#define OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET                      0x0024
+
+/* PRM.ABE_PRM register offsets */
+#define OMAP54XX_PM_ABE_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_ABE_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET                     0x002c
+#define OMAP54XX_PM_ABE_MCPDM_WKDEP_OFFSET                      0x0030
+#define OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET                    0x0034
+#define OMAP54XX_PM_ABE_DMIC_WKDEP_OFFSET                       0x0038
+#define OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET                     0x003c
+#define OMAP54XX_PM_ABE_MCASP_WKDEP_OFFSET                      0x0040
+#define OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET                    0x0044
+#define OMAP54XX_PM_ABE_MCBSP1_WKDEP_OFFSET                     0x0048
+#define OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET                   0x004c
+#define OMAP54XX_PM_ABE_MCBSP2_WKDEP_OFFSET                     0x0050
+#define OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET                   0x0054
+#define OMAP54XX_PM_ABE_MCBSP3_WKDEP_OFFSET                     0x0058
+#define OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET                   0x005c
+#define OMAP54XX_PM_ABE_SLIMBUS1_WKDEP_OFFSET                   0x0060
+#define OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET                 0x0064
+#define OMAP54XX_PM_ABE_TIMER5_WKDEP_OFFSET                     0x0068
+#define OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET                   0x006c
+#define OMAP54XX_PM_ABE_TIMER6_WKDEP_OFFSET                     0x0070
+#define OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET                   0x0074
+#define OMAP54XX_PM_ABE_TIMER7_WKDEP_OFFSET                     0x0078
+#define OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET                   0x007c
+#define OMAP54XX_PM_ABE_TIMER8_WKDEP_OFFSET                     0x0080
+#define OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET                   0x0084
+#define OMAP54XX_PM_ABE_WD_TIMER3_WKDEP_OFFSET                  0x0088
+#define OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET                0x008c
+
+/* PRM.COREAON_PRM register offsets */
+#define OMAP54XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET        0x0028
+#define OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET      0x002c
+#define OMAP54XX_PM_COREAON_SMARTREFLEX_MM_WKDEP_OFFSET         0x0030
+#define OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET       0x0034
+#define OMAP54XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET       0x0038
+#define OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET     0x003c
+
+/* PRM.CORE_PRM register offsets */
+#define OMAP54XX_PM_CORE_PWRSTCTRL_OFFSET                       0x0000
+#define OMAP54XX_PM_CORE_PWRSTST_OFFSET                         0x0004
+#define OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET            0x0024
+#define OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET            0x0124
+#define OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET                 0x012c
+#define OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET             0x0134
+#define OMAP54XX_RM_IPU_RSTCTRL_OFFSET                          0x0210
+#define OMAP54XX_RM_IPU_RSTST_OFFSET                            0x0214
+#define OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET                      0x0224
+#define OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET               0x0324
+#define OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET                     0x0424
+#define OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET             0x042c
+#define OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET                   0x0434
+#define OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET                   0x043c
+#define OMAP54XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET                0x0444
+#define OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET                      0x0524
+#define OMAP54XX_RM_C2C_MODEM_ICR_CONTEXT_OFFSET                0x052c
+#define OMAP54XX_RM_C2C_C2C_OCP_FW_CONTEXT_OFFSET               0x0534
+#define OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET                 0x0624
+#define OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET               0x062c
+#define OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET                0x0634
+#define OMAP54XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET                0x063c
+#define OMAP54XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET               0x0644
+#define OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET            0x0724
+#define OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET             0x072c
+#define OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET           0x0744
+#define OMAP54XX_RM_MIPIEXT_LLI_CONTEXT_OFFSET                  0x0824
+#define OMAP54XX_RM_MIPIEXT_LLI_OCP_FW_CONTEXT_OFFSET           0x082c
+#define OMAP54XX_RM_MIPIEXT_MPHY_CONTEXT_OFFSET                 0x0834
+#define OMAP54XX_PM_L4PER_TIMER10_WKDEP_OFFSET                  0x0928
+#define OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET                0x092c
+#define OMAP54XX_PM_L4PER_TIMER11_WKDEP_OFFSET                  0x0930
+#define OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET                0x0934
+#define OMAP54XX_PM_L4PER_TIMER2_WKDEP_OFFSET                   0x0938
+#define OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET                 0x093c
+#define OMAP54XX_PM_L4PER_TIMER3_WKDEP_OFFSET                   0x0940
+#define OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET                 0x0944
+#define OMAP54XX_PM_L4PER_TIMER4_WKDEP_OFFSET                   0x0948
+#define OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET                 0x094c
+#define OMAP54XX_PM_L4PER_TIMER9_WKDEP_OFFSET                   0x0950
+#define OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET                 0x0954
+#define OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET                    0x095c
+#define OMAP54XX_PM_L4PER_GPIO2_WKDEP_OFFSET                    0x0960
+#define OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET                  0x0964
+#define OMAP54XX_PM_L4PER_GPIO3_WKDEP_OFFSET                    0x0968
+#define OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET                  0x096c
+#define OMAP54XX_PM_L4PER_GPIO4_WKDEP_OFFSET                    0x0970
+#define OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET                  0x0974
+#define OMAP54XX_PM_L4PER_GPIO5_WKDEP_OFFSET                    0x0978
+#define OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET                  0x097c
+#define OMAP54XX_PM_L4PER_GPIO6_WKDEP_OFFSET                    0x0980
+#define OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET                  0x0984
+#define OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET                  0x098c
+#define OMAP54XX_PM_L4PER_I2C1_WKDEP_OFFSET                     0x09a0
+#define OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET                   0x09a4
+#define OMAP54XX_PM_L4PER_I2C2_WKDEP_OFFSET                     0x09a8
+#define OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET                   0x09ac
+#define OMAP54XX_PM_L4PER_I2C3_WKDEP_OFFSET                     0x09b0
+#define OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET                   0x09b4
+#define OMAP54XX_PM_L4PER_I2C4_WKDEP_OFFSET                     0x09b8
+#define OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET                   0x09bc
+#define OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET                 0x09c0
+#define OMAP54XX_PM_L4PER_MCSPI1_WKDEP_OFFSET                   0x09f0
+#define OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET                 0x09f4
+#define OMAP54XX_PM_L4PER_MCSPI2_WKDEP_OFFSET                   0x09f8
+#define OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET                 0x09fc
+#define OMAP54XX_PM_L4PER_MCSPI3_WKDEP_OFFSET                   0x0a00
+#define OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET                 0x0a04
+#define OMAP54XX_PM_L4PER_MCSPI4_WKDEP_OFFSET                   0x0a08
+#define OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET                 0x0a0c
+#define OMAP54XX_PM_L4PER_GPIO7_WKDEP_OFFSET                    0x0a10
+#define OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET                  0x0a14
+#define OMAP54XX_PM_L4PER_GPIO8_WKDEP_OFFSET                    0x0a18
+#define OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET                  0x0a1c
+#define OMAP54XX_PM_L4PER_MMC3_WKDEP_OFFSET                     0x0a20
+#define OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET                   0x0a24
+#define OMAP54XX_PM_L4PER_MMC4_WKDEP_OFFSET                     0x0a28
+#define OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET                   0x0a2c
+#define OMAP54XX_PM_L4PER_UART1_WKDEP_OFFSET                    0x0a40
+#define OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET                  0x0a44
+#define OMAP54XX_PM_L4PER_UART2_WKDEP_OFFSET                    0x0a48
+#define OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET                  0x0a4c
+#define OMAP54XX_PM_L4PER_UART3_WKDEP_OFFSET                    0x0a50
+#define OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET                  0x0a54
+#define OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET                  0x0a58
+#define OMAP54XX_PM_L4PER_UART4_WKDEP_OFFSET                    0x0a5c
+#define OMAP54XX_PM_L4PER_MMC5_WKDEP_OFFSET                     0x0a60
+#define OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET                   0x0a64
+#define OMAP54XX_PM_L4PER_I2C5_WKDEP_OFFSET                     0x0a68
+#define OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET                   0x0a6c
+#define OMAP54XX_PM_L4PER_UART5_WKDEP_OFFSET                    0x0a70
+#define OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET                  0x0a74
+#define OMAP54XX_PM_L4PER_UART6_WKDEP_OFFSET                    0x0a78
+#define OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET                  0x0a7c
+#define OMAP54XX_RM_L4SEC_AES1_CONTEXT_OFFSET                   0x0aa4
+#define OMAP54XX_RM_L4SEC_AES2_CONTEXT_OFFSET                   0x0aac
+#define OMAP54XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET                0x0ab4
+#define OMAP54XX_RM_L4SEC_FPKA_CONTEXT_OFFSET                   0x0abc
+#define OMAP54XX_RM_L4SEC_RNG_CONTEXT_OFFSET                    0x0ac4
+#define OMAP54XX_RM_L4SEC_SHA2MD5_CONTEXT_OFFSET                0x0acc
+#define OMAP54XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET             0x0adc
+
+/* PRM.IVA_PRM register offsets */
+#define OMAP54XX_PM_IVA_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_IVA_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_IVA_RSTCTRL_OFFSET                          0x0010
+#define OMAP54XX_RM_IVA_RSTST_OFFSET                            0x0014
+#define OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET                      0x0024
+#define OMAP54XX_RM_IVA_SL2_CONTEXT_OFFSET                      0x002c
+
+/* PRM.CAM_PRM register offsets */
+#define OMAP54XX_PM_CAM_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_CAM_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET                      0x0024
+#define OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET                     0x002c
+#define OMAP54XX_RM_CAM_CAL_CONTEXT_OFFSET                      0x0034
+
+/* PRM.DSS_PRM register offsets */
+#define OMAP54XX_PM_DSS_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_DSS_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_PM_DSS_DSS_WKDEP_OFFSET                        0x0020
+#define OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET                      0x0024
+#define OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET                     0x0034
+
+/* PRM.GPU_PRM register offsets */
+#define OMAP54XX_PM_GPU_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_GPU_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET                      0x0024
+
+/* PRM.L3INIT_PRM register offsets */
+#define OMAP54XX_PM_L3INIT_PWRSTCTRL_OFFSET                     0x0000
+#define OMAP54XX_PM_L3INIT_PWRSTST_OFFSET                       0x0004
+#define OMAP54XX_PM_L3INIT_MMC1_WKDEP_OFFSET                    0x0028
+#define OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET                  0x002c
+#define OMAP54XX_PM_L3INIT_MMC2_WKDEP_OFFSET                    0x0030
+#define OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET                  0x0034
+#define OMAP54XX_PM_L3INIT_HSI_WKDEP_OFFSET                     0x0038
+#define OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET                   0x003c
+#define OMAP54XX_PM_L3INIT_UNIPRO2_WKDEP_OFFSET                 0x0040
+#define OMAP54XX_RM_L3INIT_UNIPRO2_CONTEXT_OFFSET               0x0044
+#define OMAP54XX_PM_L3INIT_USB_HOST_HS_WKDEP_OFFSET             0x0058
+#define OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET           0x005c
+#define OMAP54XX_PM_L3INIT_USB_TLL_HS_WKDEP_OFFSET              0x0068
+#define OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET            0x006c
+#define OMAP54XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET        0x007c
+#define OMAP54XX_PM_L3INIT_SATA_WKDEP_OFFSET                    0x0088
+#define OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET                  0x008c
+#define OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET              0x00e4
+#define OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET              0x00ec
+#define OMAP54XX_PM_L3INIT_USB_OTG_SS_WKDEP_OFFSET              0x00f0
+#define OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET            0x00f4
+
+/* PRM.CUSTEFUSE_PRM register offsets */
+#define OMAP54XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET                  0x0000
+#define OMAP54XX_PM_CUSTEFUSE_PWRSTST_OFFSET                    0x0004
+#define OMAP54XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET    0x0024
+
+/* PRM.WKUPAON_PRM register offsets */
+#define OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET              0x0024
+#define OMAP54XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET            0x002c
+#define OMAP54XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET              0x0030
+#define OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET            0x0034
+#define OMAP54XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET                  0x0038
+#define OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET                0x003c
+#define OMAP54XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET                 0x0040
+#define OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET               0x0044
+#define OMAP54XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET                0x0048
+#define OMAP54XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET              0x004c
+#define OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET          0x0054
+#define OMAP54XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET              0x0064
+#define OMAP54XX_PM_WKUPAON_KBD_WKDEP_OFFSET                    0x0078
+#define OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET                  0x007c
+
+/* PRM.WKUPAON_CM register offsets */
+#define OMAP54XX_CM_WKUPAON_CLKSTCTRL_OFFSET                    0x0000
+#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET              0x0020
+#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL                     OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0020)
+#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET            0x0028
+#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL                   OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0028)
+#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET            0x0030
+#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL                   OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0030)
+#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET                0x0038
+#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL                       OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0038)
+#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET               0x0040
+#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL                      OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0040)
+#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET              0x0048
+#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL                     OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0048)
+#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET          0x0050
+#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL                 OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0050)
+#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET              0x0060
+#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL                     OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0060)
+#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET                  0x0078
+#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL                         OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0078)
+#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET                 0x0090
+#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL                        OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0090)
+#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET            0x0098
+#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL                   OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0098)
+
+/* PRM.EMU_PRM register offsets */
+#define OMAP54XX_PM_EMU_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_EMU_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET                  0x0024
+
+/* PRM.EMU_CM register offsets */
+#define OMAP54XX_CM_EMU_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_EMU_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET                  0x0020
+#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL                         OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0020)
+#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET              0x0028
+#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL                     OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0028)
+
+/* PRM.DEVICE_PRM register offsets */
+#define OMAP54XX_PRM_RSTCTRL_OFFSET                             0x0000
+#define OMAP54XX_PRM_RSTST_OFFSET                               0x0004
+#define OMAP54XX_PRM_RSTTIME_OFFSET                             0x0008
+#define OMAP54XX_PRM_CLKREQCTRL_OFFSET                          0x000c
+#define OMAP54XX_PRM_VOLTCTRL_OFFSET                            0x0010
+#define OMAP54XX_PRM_PWRREQCTRL_OFFSET                          0x0014
+#define OMAP54XX_PRM_PSCON_COUNT_OFFSET                         0x0018
+#define OMAP54XX_PRM_IO_COUNT_OFFSET                            0x001c
+#define OMAP54XX_PRM_IO_PMCTRL_OFFSET                           0x0020
+#define OMAP54XX_PRM_VOLTSETUP_WARMRESET_OFFSET                 0x0024
+#define OMAP54XX_PRM_VOLTSETUP_CORE_OFF_OFFSET                  0x0028
+#define OMAP54XX_PRM_VOLTSETUP_MPU_OFF_OFFSET                   0x002c
+#define OMAP54XX_PRM_VOLTSETUP_MM_OFF_OFFSET                    0x0030
+#define OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET            0x0034
+#define OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET             0x0038
+#define OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET              0x003c
+#define OMAP54XX_PRM_VP_CORE_CONFIG_OFFSET                      0x0040
+#define OMAP54XX_PRM_VP_CORE_STATUS_OFFSET                      0x0044
+#define OMAP54XX_PRM_VP_CORE_VLIMITTO_OFFSET                    0x0048
+#define OMAP54XX_PRM_VP_CORE_VOLTAGE_OFFSET                     0x004c
+#define OMAP54XX_PRM_VP_CORE_VSTEPMAX_OFFSET                    0x0050
+#define OMAP54XX_PRM_VP_CORE_VSTEPMIN_OFFSET                    0x0054
+#define OMAP54XX_PRM_VP_MPU_CONFIG_OFFSET                       0x0058
+#define OMAP54XX_PRM_VP_MPU_STATUS_OFFSET                       0x005c
+#define OMAP54XX_PRM_VP_MPU_VLIMITTO_OFFSET                     0x0060
+#define OMAP54XX_PRM_VP_MPU_VOLTAGE_OFFSET                      0x0064
+#define OMAP54XX_PRM_VP_MPU_VSTEPMAX_OFFSET                     0x0068
+#define OMAP54XX_PRM_VP_MPU_VSTEPMIN_OFFSET                     0x006c
+#define OMAP54XX_PRM_VP_MM_CONFIG_OFFSET                        0x0070
+#define OMAP54XX_PRM_VP_MM_STATUS_OFFSET                        0x0074
+#define OMAP54XX_PRM_VP_MM_VLIMITTO_OFFSET                      0x0078
+#define OMAP54XX_PRM_VP_MM_VOLTAGE_OFFSET                       0x007c
+#define OMAP54XX_PRM_VP_MM_VSTEPMAX_OFFSET                      0x0080
+#define OMAP54XX_PRM_VP_MM_VSTEPMIN_OFFSET                      0x0084
+#define OMAP54XX_PRM_VC_SMPS_CORE_CONFIG_OFFSET                 0x0088
+#define OMAP54XX_PRM_VC_SMPS_MM_CONFIG_OFFSET                   0x008c
+#define OMAP54XX_PRM_VC_SMPS_MPU_CONFIG_OFFSET                  0x0090
+#define OMAP54XX_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET               0x0094
+#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MM_L_OFFSET                 0x0098
+#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET                0x009c
+#define OMAP54XX_PRM_VC_VAL_BYPASS_OFFSET                       0x00a0
+#define OMAP54XX_PRM_VC_CORE_ERRST_OFFSET                       0x00a4
+#define OMAP54XX_PRM_VC_MM_ERRST_OFFSET                         0x00a8
+#define OMAP54XX_PRM_VC_MPU_ERRST_OFFSET                        0x00ac
+#define OMAP54XX_PRM_VC_BYPASS_ERRST_OFFSET                     0x00b0
+#define OMAP54XX_PRM_VC_CFG_I2C_MODE_OFFSET                     0x00b4
+#define OMAP54XX_PRM_VC_CFG_I2C_CLK_OFFSET                      0x00b8
+#define OMAP54XX_PRM_SRAM_COUNT_OFFSET                          0x00bc
+#define OMAP54XX_PRM_SRAM_WKUP_SETUP_OFFSET                     0x00c0
+#define OMAP54XX_PRM_SLDO_CORE_SETUP_OFFSET                     0x00c4
+#define OMAP54XX_PRM_SLDO_CORE_CTRL_OFFSET                      0x00c8
+#define OMAP54XX_PRM_SLDO_MPU_SETUP_OFFSET                      0x00cc
+#define OMAP54XX_PRM_SLDO_MPU_CTRL_OFFSET                       0x00d0
+#define OMAP54XX_PRM_SLDO_MM_SETUP_OFFSET                       0x00d4
+#define OMAP54XX_PRM_SLDO_MM_CTRL_OFFSET                        0x00d8
+#define OMAP54XX_PRM_ABBLDO_MPU_SETUP_OFFSET                    0x00dc
+#define OMAP54XX_PRM_ABBLDO_MPU_CTRL_OFFSET                     0x00e0
+#define OMAP54XX_PRM_ABBLDO_MM_SETUP_OFFSET                     0x00e4
+#define OMAP54XX_PRM_ABBLDO_MM_CTRL_OFFSET                      0x00e8
+#define OMAP54XX_PRM_BANDGAP_SETUP_OFFSET                       0x00ec
+#define OMAP54XX_PRM_DEVICE_OFF_CTRL_OFFSET                     0x00f0
+#define OMAP54XX_PRM_PHASE1_CNDP_OFFSET                         0x00f4
+#define OMAP54XX_PRM_PHASE2A_CNDP_OFFSET                        0x00f8
+#define OMAP54XX_PRM_PHASE2B_CNDP_OFFSET                        0x00fc
+#define OMAP54XX_PRM_MODEM_IF_CTRL_OFFSET                       0x0100
+#define OMAP54XX_PRM_VOLTST_MPU_OFFSET                          0x0110
+#define OMAP54XX_PRM_VOLTST_MM_OFFSET                           0x0114
+
+#endif
diff --git a/arch/arm/mach-omap2/scrm54xx.h b/arch/arm/mach-omap2/scrm54xx.h
new file mode 100644
index 000000000000..57e86c8f8239
--- /dev/null
+++ b/arch/arm/mach-omap2/scrm54xx.h
@@ -0,0 +1,231 @@
+/*
+ * OMAP54XX SCRM registers and bitfields
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
+
+#define OMAP5_SCRM_BASE         0x4ae0a000
+
+#define OMAP54XX_SCRM_REGADDR(reg)                              \
+        OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg))
+
+/* SCRM */
+
+/* SCRM.SCRM register offsets */
+#define OMAP5_SCRM_REVISION_SCRM_OFFSET         0x0000
+#define OMAP5_SCRM_REVISION_SCRM                OMAP54XX_SCRM_REGADDR(0x0000)
+#define OMAP5_SCRM_CLKSETUPTIME_OFFSET          0x0100
+#define OMAP5_SCRM_CLKSETUPTIME                 OMAP54XX_SCRM_REGADDR(0x0100)
+#define OMAP5_SCRM_PMICSETUPTIME_OFFSET         0x0104
+#define OMAP5_SCRM_PMICSETUPTIME                OMAP54XX_SCRM_REGADDR(0x0104)
+#define OMAP5_SCRM_ALTCLKSRC_OFFSET             0x0110
+#define OMAP5_SCRM_ALTCLKSRC                    OMAP54XX_SCRM_REGADDR(0x0110)
+#define OMAP5_SCRM_MODEMCLKM_OFFSET             0x0118
+#define OMAP5_SCRM_MODEMCLKM                    OMAP54XX_SCRM_REGADDR(0x0118)
+#define OMAP5_SCRM_D2DCLKM_OFFSET               0x011c
+#define OMAP5_SCRM_D2DCLKM                      OMAP54XX_SCRM_REGADDR(0x011c)
+#define OMAP5_SCRM_EXTCLKREQ_OFFSET             0x0200
+#define OMAP5_SCRM_EXTCLKREQ                    OMAP54XX_SCRM_REGADDR(0x0200)
+#define OMAP5_SCRM_ACCCLKREQ_OFFSET             0x0204
+#define OMAP5_SCRM_ACCCLKREQ                    OMAP54XX_SCRM_REGADDR(0x0204)
+#define OMAP5_SCRM_PWRREQ_OFFSET                0x0208
+#define OMAP5_SCRM_PWRREQ                       OMAP54XX_SCRM_REGADDR(0x0208)
+#define OMAP5_SCRM_AUXCLKREQ0_OFFSET            0x0210
+#define OMAP5_SCRM_AUXCLKREQ0                   OMAP54XX_SCRM_REGADDR(0x0210)
+#define OMAP5_SCRM_AUXCLKREQ1_OFFSET            0x0214
+#define OMAP5_SCRM_AUXCLKREQ1                   OMAP54XX_SCRM_REGADDR(0x0214)
+#define OMAP5_SCRM_AUXCLKREQ2_OFFSET            0x0218
+#define OMAP5_SCRM_AUXCLKREQ2                   OMAP54XX_SCRM_REGADDR(0x0218)
+#define OMAP5_SCRM_AUXCLKREQ3_OFFSET            0x021c
+#define OMAP5_SCRM_AUXCLKREQ3                   OMAP54XX_SCRM_REGADDR(0x021c)
+#define OMAP5_SCRM_AUXCLKREQ4_OFFSET            0x0220
+#define OMAP5_SCRM_AUXCLKREQ4                   OMAP54XX_SCRM_REGADDR(0x0220)
+#define OMAP5_SCRM_AUXCLKREQ5_OFFSET            0x0224
+#define OMAP5_SCRM_AUXCLKREQ5                   OMAP54XX_SCRM_REGADDR(0x0224)
+#define OMAP5_SCRM_D2DCLKREQ_OFFSET             0x0234
+#define OMAP5_SCRM_D2DCLKREQ                    OMAP54XX_SCRM_REGADDR(0x0234)
+#define OMAP5_SCRM_AUXCLK0_OFFSET               0x0310
+#define OMAP5_SCRM_AUXCLK0                      OMAP54XX_SCRM_REGADDR(0x0310)
+#define OMAP5_SCRM_AUXCLK1_OFFSET               0x0314
+#define OMAP5_SCRM_AUXCLK1                      OMAP54XX_SCRM_REGADDR(0x0314)
+#define OMAP5_SCRM_AUXCLK2_OFFSET               0x0318
+#define OMAP5_SCRM_AUXCLK2                      OMAP54XX_SCRM_REGADDR(0x0318)
+#define OMAP5_SCRM_AUXCLK3_OFFSET               0x031c
+#define OMAP5_SCRM_AUXCLK3                      OMAP54XX_SCRM_REGADDR(0x031c)
+#define OMAP5_SCRM_AUXCLK4_OFFSET               0x0320
+#define OMAP5_SCRM_AUXCLK4                      OMAP54XX_SCRM_REGADDR(0x0320)
+#define OMAP5_SCRM_AUXCLK5_OFFSET               0x0324
+#define OMAP5_SCRM_AUXCLK5                      OMAP54XX_SCRM_REGADDR(0x0324)
+#define OMAP5_SCRM_RSTTIME_OFFSET               0x0400
+#define OMAP5_SCRM_RSTTIME                      OMAP54XX_SCRM_REGADDR(0x0400)
+#define OMAP5_SCRM_MODEMRSTCTRL_OFFSET          0x0418
+#define OMAP5_SCRM_MODEMRSTCTRL                 OMAP54XX_SCRM_REGADDR(0x0418)
+#define OMAP5_SCRM_D2DRSTCTRL_OFFSET            0x041c
+#define OMAP5_SCRM_D2DRSTCTRL                   OMAP54XX_SCRM_REGADDR(0x041c)
+#define OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET       0x0420
+#define OMAP5_SCRM_EXTPWRONRSTCTRL              OMAP54XX_SCRM_REGADDR(0x0420)
+#define OMAP5_SCRM_EXTWARMRSTST_OFFSET          0x0510
+#define OMAP5_SCRM_EXTWARMRSTST                 OMAP54XX_SCRM_REGADDR(0x0510)
+#define OMAP5_SCRM_APEWARMRSTST_OFFSET          0x0514
+#define OMAP5_SCRM_APEWARMRSTST                 OMAP54XX_SCRM_REGADDR(0x0514)
+#define OMAP5_SCRM_MODEMWARMRSTST_OFFSET        0x0518
+#define OMAP5_SCRM_MODEMWARMRSTST               OMAP54XX_SCRM_REGADDR(0x0518)
+#define OMAP5_SCRM_D2DWARMRSTST_OFFSET          0x051c
+#define OMAP5_SCRM_D2DWARMRSTST                 OMAP54XX_SCRM_REGADDR(0x051c)
+
+/*
+ * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
+ * AUXCLKREQ5, D2DCLKREQ
+ */
+#define OMAP5_ACCURACY_SHIFT                    1
+#define OMAP5_ACCURACY_WIDTH                    0x1
+#define OMAP5_ACCURACY_MASK                     (1 << 1)
+
+/* Used by APEWARMRSTST */
+#define OMAP5_APEWARMRSTST_SHIFT                1
+#define OMAP5_APEWARMRSTST_WIDTH                0x1
+#define OMAP5_APEWARMRSTST_MASK                 (1 << 1)
+
+/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
+#define OMAP5_CLKDIV_SHIFT                      16
+#define OMAP5_CLKDIV_WIDTH                      0x4
+#define OMAP5_CLKDIV_MASK                       (0xf << 16)
+
+/* Used by D2DCLKM, MODEMCLKM */
+#define OMAP5_CLK_32KHZ_SHIFT                   0
+#define OMAP5_CLK_32KHZ_WIDTH                   0x1
+#define OMAP5_CLK_32KHZ_MASK                    (1 << 0)
+
+/* Used by D2DRSTCTRL, MODEMRSTCTRL */
+#define OMAP5_COLDRST_SHIFT                     0
+#define OMAP5_COLDRST_WIDTH                     0x1
+#define OMAP5_COLDRST_MASK                      (1 << 0)
+
+/* Used by D2DWARMRSTST */
+#define OMAP5_D2DWARMRSTST_SHIFT                3
+#define OMAP5_D2DWARMRSTST_WIDTH                0x1
+#define OMAP5_D2DWARMRSTST_MASK                 (1 << 3)
+
+/* Used by AUXCLK0 */
+#define OMAP5_DISABLECLK_SHIFT                  9
+#define OMAP5_DISABLECLK_WIDTH                  0x1
+#define OMAP5_DISABLECLK_MASK                   (1 << 9)
+
+/* Used by CLKSETUPTIME */
+#define OMAP5_DOWNTIME_SHIFT                    16
+#define OMAP5_DOWNTIME_WIDTH                    0x6
+#define OMAP5_DOWNTIME_MASK                     (0x3f << 16)
+
+/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
+#define OMAP5_ENABLE_SHIFT                      8
+#define OMAP5_ENABLE_WIDTH                      0x1
+#define OMAP5_ENABLE_MASK                       (1 << 8)
+
+/* Renamed from ENABLE Used by EXTPWRONRSTCTRL */
+#define OMAP5_ENABLE_0_0_SHIFT                  0
+#define OMAP5_ENABLE_0_0_WIDTH                  0x1
+#define OMAP5_ENABLE_0_0_MASK                   (1 << 0)
+
+/* Used by ALTCLKSRC */
+#define OMAP5_ENABLE_EXT_SHIFT                  3
+#define OMAP5_ENABLE_EXT_WIDTH                  0x1
+#define OMAP5_ENABLE_EXT_MASK                   (1 << 3)
+
+/* Used by ALTCLKSRC */
+#define OMAP5_ENABLE_INT_SHIFT                  2
+#define OMAP5_ENABLE_INT_WIDTH                  0x1
+#define OMAP5_ENABLE_INT_MASK                   (1 << 2)
+
+/* Used by EXTWARMRSTST */
+#define OMAP5_EXTWARMRSTST_SHIFT                0
+#define OMAP5_EXTWARMRSTST_WIDTH                0x1
+#define OMAP5_EXTWARMRSTST_MASK                 (1 << 0)
+
+/*
+ * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
+ * AUXCLKREQ5
+ */
+#define OMAP5_MAPPING_SHIFT                     2
+#define OMAP5_MAPPING_WIDTH                     0x3
+#define OMAP5_MAPPING_MASK                      (0x7 << 2)
+
+/* Used by ALTCLKSRC */
+#define OMAP5_MODE_SHIFT                        0
+#define OMAP5_MODE_WIDTH                        0x2
+#define OMAP5_MODE_MASK                         (0x3 << 0)
+
+/* Used by MODEMWARMRSTST */
+#define OMAP5_MODEMWARMRSTST_SHIFT              2
+#define OMAP5_MODEMWARMRSTST_WIDTH              0x1
+#define OMAP5_MODEMWARMRSTST_MASK               (1 << 2)
+
+/*
+ * Used by ACCCLKREQ, AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5,
+ * AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, AUXCLKREQ5,
+ * D2DCLKREQ, EXTCLKREQ, PWRREQ
+ */
+#define OMAP5_POLARITY_SHIFT                    0
+#define OMAP5_POLARITY_WIDTH                    0x1
+#define OMAP5_POLARITY_MASK                     (1 << 0)
+
+/* Used by EXTPWRONRSTCTRL */
+#define OMAP5_PWRONRST_SHIFT                    1
+#define OMAP5_PWRONRST_WIDTH                    0x1
+#define OMAP5_PWRONRST_MASK                     (1 << 1)
+
+/* Used by REVISION_SCRM */
+#define OMAP5_REV_SHIFT                         0
+#define OMAP5_REV_WIDTH                         0x8
+#define OMAP5_REV_MASK                          (0xff << 0)
+
+/* Used by RSTTIME */
+#define OMAP5_RSTTIME_SHIFT                     0
+#define OMAP5_RSTTIME_WIDTH                     0x4
+#define OMAP5_RSTTIME_MASK                      (0xf << 0)
+
+/* Used by CLKSETUPTIME */
+#define OMAP5_SETUPTIME_SHIFT                   0
+#define OMAP5_SETUPTIME_WIDTH                   0xc
+#define OMAP5_SETUPTIME_MASK                    (0xfff << 0)
+
+/* Used by PMICSETUPTIME */
+#define OMAP5_SLEEPTIME_SHIFT                   0
+#define OMAP5_SLEEPTIME_WIDTH                   0x6
+#define OMAP5_SLEEPTIME_MASK                    (0x3f << 0)
+
+/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
+#define OMAP5_SRCSELECT_SHIFT                   1
+#define OMAP5_SRCSELECT_WIDTH                   0x2
+#define OMAP5_SRCSELECT_MASK                    (0x3 << 1)
+
+/* Used by D2DCLKM */
+#define OMAP5_SYSCLK_SHIFT                      1
+#define OMAP5_SYSCLK_WIDTH                      0x1
+#define OMAP5_SYSCLK_MASK                       (1 << 1)
+
+/* Used by PMICSETUPTIME */
+#define OMAP5_WAKEUPTIME_SHIFT                  16
+#define OMAP5_WAKEUPTIME_WIDTH                  0x6
+#define OMAP5_WAKEUPTIME_MASK                   (0x3f << 16)
+
+/* Used by D2DRSTCTRL, MODEMRSTCTRL */
+#define OMAP5_WARMRST_SHIFT                     1
+#define OMAP5_WARMRST_WIDTH                     0x1
+#define OMAP5_WARMRST_MASK                      (1 << 1)
+
+#endif
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 197cc16870d9..8c616e436bc7 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -96,6 +96,15 @@
 # endif
 #endif
 
+#ifdef CONFIG_SOC_AM43XX
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME am43xx
+# endif
+#endif
+
 /*
  * Omap device type i.e. EMU/HS/TST/GP/BAD
  */
@@ -187,6 +196,7 @@ IS_OMAP_CLASS(44xx, 0x44)
 IS_AM_CLASS(35xx, 0x35)
 IS_OMAP_CLASS(54xx, 0x54)
 IS_AM_CLASS(33xx, 0x33)
+IS_AM_CLASS(43xx, 0x43)
 
 IS_TI_CLASS(81xx, 0x81)
 
@@ -202,6 +212,7 @@ IS_OMAP_SUBCLASS(543x, 0x543)
 IS_TI_SUBCLASS(816x, 0x816)
 IS_TI_SUBCLASS(814x, 0x814)
 IS_AM_SUBCLASS(335x, 0x335)
+IS_AM_SUBCLASS(437x, 0x437)
 
 #define cpu_is_omap24xx()               0
 #define cpu_is_omap242x()               0
@@ -214,6 +225,8 @@ IS_AM_SUBCLASS(335x, 0x335)
 #define soc_is_am35xx()                 0
 #define soc_is_am33xx()                 0
 #define soc_is_am335x()                 0
+#define soc_is_am43xx()                 0
+#define soc_is_am437x()                 0
 #define cpu_is_omap44xx()               0
 #define cpu_is_omap443x()               0
 #define cpu_is_omap446x()               0
@@ -341,6 +354,13 @@ IS_OMAP_TYPE(3430, 0x3430)
 # define soc_is_am335x()                is_am335x()
 #endif
 
+#ifdef  CONFIG_SOC_AM43XX
+# undef soc_is_am43xx
+# undef soc_is_am437x
+# define soc_is_am43xx()                is_am43xx()
+# define soc_is_am437x()                is_am437x()
+#endif
+
 # if defined(CONFIG_ARCH_OMAP4)
 # undef cpu_is_omap44xx
 # undef cpu_is_omap443x
@@ -383,6 +403,8 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define TI816X_CLASS            0x81600034
 #define TI8168_REV_ES1_0        TI816X_CLASS
 #define TI8168_REV_ES1_1        (TI816X_CLASS | (0x1 << 8))
+#define TI8168_REV_ES2_0        (TI816X_CLASS | (0x2 << 8))
+#define TI8168_REV_ES2_1        (TI816X_CLASS | (0x3 << 8))
 
 #define TI814X_CLASS            0x81400034
 #define TI8148_REV_ES1_0        TI814X_CLASS
@@ -398,6 +420,9 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define AM335X_REV_ES2_0        (AM335X_CLASS | (0x1 << 8))
 #define AM335X_REV_ES2_1        (AM335X_CLASS | (0x2 << 8))
 
+#define AM437X_CLASS            0x43700000
+#define AM437X_REV_ES1_0        AM437X_CLASS
+
 #define OMAP443X_CLASS          0x44300044
 #define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
 #define OMAP4430_REV_ES2_0      (OMAP443X_CLASS | (0x20 << 8))
@@ -424,6 +449,7 @@ void omap4xxx_check_revision(void);
 void omap5xxx_check_revision(void);
 void omap3xxx_check_features(void);
 void ti81xx_check_features(void);
+void am33xx_check_features(void);
 void omap4xxx_check_features(void);
 
 /*
diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
index 0ff0f068bea8..4bd096836235 100644
--- a/arch/arm/mach-omap2/sram.c
+++ b/arch/arm/mach-omap2/sram.c
@@ -119,6 +119,9 @@ static void __init omap_detect_sram(void)
                 if (soc_is_am33xx()) {
                         omap_sram_start = AM33XX_SRAM_PA;
                         omap_sram_size = 0x10000; /* 64K */
+                } else if (soc_is_am43xx()) {
+                        omap_sram_start = AM33XX_SRAM_PA;
+                        omap_sram_size = SZ_256K;
                 } else if (cpu_is_omap34xx()) {
                         omap_sram_start = OMAP3_SRAM_PA;
                         omap_sram_size = 0x10000; /* 64K */
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index f8b23b8040d9..3bdb0fb02028 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -582,7 +582,7 @@ OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon",
                         2, "timer_sys_ck", NULL);
 #endif /* CONFIG_ARCH_OMAP2 */
 
-#ifdef CONFIG_ARCH_OMAP3
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
 OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon",
                         2, "timer_sys_ck", NULL);
 OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure",
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index a0ce4f10ff13..f7f2879b31b0 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -169,8 +169,8 @@ int omap_voltage_late_init(void);
 
 extern void omap2xxx_voltagedomains_init(void);
 extern void omap3xxx_voltagedomains_init(void);
-extern void am33xx_voltagedomains_init(void);
 extern void omap44xx_voltagedomains_init(void);
+extern void omap54xx_voltagedomains_init(void);
 
 struct voltagedomain *voltdm_lookup(const char *name);
 void voltdm_init(struct voltagedomain **voltdm_list);
diff --git a/arch/arm/mach-omap2/voltagedomains33xx_data.c b/arch/arm/mach-omap2/voltagedomains33xx_data.c
deleted file mode 100644
index 965458dc0cb9..000000000000
--- a/arch/arm/mach-omap2/voltagedomains33xx_data.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * AM33XX voltage domain data
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include "voltage.h"
-
-static struct voltagedomain am33xx_voltdm_mpu = {
-        .name           = "mpu",
-};
-
-static struct voltagedomain am33xx_voltdm_core = {
-        .name           = "core",
-};
-
-static struct voltagedomain am33xx_voltdm_rtc = {
-        .name           = "rtc",
-};
-
-static struct voltagedomain *voltagedomains_am33xx[] __initdata = {
-        &am33xx_voltdm_mpu,
-        &am33xx_voltdm_core,
-        &am33xx_voltdm_rtc,
-        NULL,
-};
-
-void __init am33xx_voltagedomains_init(void)
-{
-        voltdm_init(voltagedomains_am33xx);
-}
diff --git a/arch/arm/mach-omap2/voltagedomains54xx_data.c b/arch/arm/mach-omap2/voltagedomains54xx_data.c
new file mode 100644
index 000000000000..72b8971b54c7
--- /dev/null
+++ b/arch/arm/mach-omap2/voltagedomains54xx_data.c
@@ -0,0 +1,102 @@
+/*
+ * OMAP5 Voltage Management Routines
+ *
+ * Based on voltagedomains44xx_data.c
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/init.h>
+
+#include "common.h"
+
+#include "prm54xx.h"
+#include "voltage.h"
+#include "omap_opp_data.h"
+#include "vc.h"
+#include "vp.h"
+
+static const struct omap_vfsm_instance omap5_vdd_mpu_vfsm = {
+        .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET,
+};
+
+static const struct omap_vfsm_instance omap5_vdd_mm_vfsm = {
+        .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET,
+};
+
+static const struct omap_vfsm_instance omap5_vdd_core_vfsm = {
+        .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
+};
+
+static struct voltagedomain omap5_voltdm_mpu = {
+        .name = "mpu",
+        .scalable = true,
+        .read = omap4_prm_vcvp_read,
+        .write = omap4_prm_vcvp_write,
+        .rmw = omap4_prm_vcvp_rmw,
+        .vc = &omap4_vc_mpu,
+        .vfsm = &omap5_vdd_mpu_vfsm,
+        .vp = &omap4_vp_mpu,
+};
+
+static struct voltagedomain omap5_voltdm_mm = {
+        .name = "mm",
+        .scalable = true,
+        .read = omap4_prm_vcvp_read,
+        .write = omap4_prm_vcvp_write,
+        .rmw = omap4_prm_vcvp_rmw,
+        .vc = &omap4_vc_iva,
+        .vfsm = &omap5_vdd_mm_vfsm,
+        .vp = &omap4_vp_iva,
+};
+
+static struct voltagedomain omap5_voltdm_core = {
+        .name = "core",
+        .scalable = true,
+        .read = omap4_prm_vcvp_read,
+        .write = omap4_prm_vcvp_write,
+        .rmw = omap4_prm_vcvp_rmw,
+        .vc = &omap4_vc_core,
+        .vfsm = &omap5_vdd_core_vfsm,
+        .vp = &omap4_vp_core,
+};
+
+static struct voltagedomain omap5_voltdm_wkup = {
+        .name = "wkup",
+};
+
+static struct voltagedomain *voltagedomains_omap5[] __initdata = {
+        &omap5_voltdm_mpu,
+        &omap5_voltdm_mm,
+        &omap5_voltdm_core,
+        &omap5_voltdm_wkup,
+        NULL,
+};
+
+static const char *sys_clk_name __initdata = "sys_clkin";
+
+void __init omap54xx_voltagedomains_init(void)
+{
+        struct voltagedomain *voltdm;
+        int i;
+
+        /*
+         * XXX Will depend on the process, validation, and binning
+         * for the currently-running IC. Use OMAP4 data for time being.
+         */
+#ifdef CONFIG_PM_OPP
+        omap5_voltdm_mpu.volt_data = omap446x_vdd_mpu_volt_data;
+        omap5_voltdm_mm.volt_data = omap446x_vdd_iva_volt_data;
+        omap5_voltdm_core.volt_data = omap446x_vdd_core_volt_data;
+#endif
+
+        for (i = 0; voltdm = voltagedomains_omap5[i], voltdm; i++)
+                voltdm->sys_clk.name = sys_clk_name;
+
+        voltdm_init(voltagedomains_omap5);
+};
diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
index 9936c180bf01..8f595c0cc8d9 100644
--- a/arch/arm/mach-prima2/pm.c
+++ b/arch/arm/mach-prima2/pm.c
@@ -101,8 +101,10 @@ static int __init sirfsoc_of_pwrc_init(void)
         struct device_node *np;
 
         np = of_find_matching_node(NULL, pwrc_ids);
-        if (!np)
-                panic("unable to find compatible pwrc node in dtb\n");
+        if (!np) {
+                pr_err("unable to find compatible sirf pwrc node in dtb\n");
+                return -ENOENT;
+        }
 
         /*
          * pwrc behind rtciobrg is not located in memory space
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 435019ca0a48..d5e0cbc934c0 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -28,8 +28,10 @@ static int __init sirfsoc_of_rstc_init(void)
         struct device_node *np;
 
         np = of_find_matching_node(NULL, rstc_ids);
-        if (!np)
-                panic("unable to find compatible rstc node in dtb\n");
+        if (!np) {
+                pr_err("unable to find compatible sirf rstc node in dtb\n");
+                return -ENOENT;
+        }
 
         sirfsoc_rstc_base = of_iomap(np, 0);
         if (!sirfsoc_rstc_base)
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c
index ab1700ec8e64..b7e094671522 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c
@@ -35,121 +35,95 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
         [DMACH_XD0] = {
                 .name           = "xdreq0",
                 .channels       = MAP(S3C2412_DMAREQSEL_XDREQ0),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_XDREQ0),
         },
         [DMACH_XD1] = {
                 .name           = "xdreq1",
                 .channels       = MAP(S3C2412_DMAREQSEL_XDREQ1),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_XDREQ1),
         },
         [DMACH_SDI] = {
                 .name           = "sdi",
                 .channels       = MAP(S3C2412_DMAREQSEL_SDI),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_SDI),
         },
-        [DMACH_SPI0] = {
-                .name           = "spi0",
+        [DMACH_SPI0_RX] = {
+                .name           = "spi0-rx",
+                .channels       = MAP(S3C2412_DMAREQSEL_SPI0RX),
+        },
+        [DMACH_SPI0_TX] = {
+                .name           = "spi0-tx",
                 .channels       = MAP(S3C2412_DMAREQSEL_SPI0TX),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_SPI0RX),
         },
-        [DMACH_SPI1] = {
-                .name           = "spi1",
+        [DMACH_SPI1_RX] = {
+                .name           = "spi1-rx",
+                .channels       = MAP(S3C2412_DMAREQSEL_SPI1RX),
+        },
+        [DMACH_SPI1_TX] = {
+                .name           = "spi1-tx",
                 .channels       = MAP(S3C2412_DMAREQSEL_SPI1TX),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_SPI1RX),
         },
         [DMACH_UART0] = {
                 .name           = "uart0",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART0_0),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART0_0),
         },
         [DMACH_UART1] = {
                 .name           = "uart1",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART1_0),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART1_0),
         },
         [DMACH_UART2] = {
                 .name           = "uart2",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART2_0),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART2_0),
         },
         [DMACH_UART0_SRC2] = {
                 .name           = "uart0",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART0_1),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART0_1),
         },
         [DMACH_UART1_SRC2] = {
                 .name           = "uart1",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART1_1),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART1_1),
         },
         [DMACH_UART2_SRC2] = {
                 .name           = "uart2",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART2_1),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART2_1),
         },
         [DMACH_TIMER] = {
                 .name           = "timer",
                 .channels       = MAP(S3C2412_DMAREQSEL_TIMER),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_TIMER),
         },
         [DMACH_I2S_IN] = {
                 .name           = "i2s-sdi",
                 .channels       = MAP(S3C2412_DMAREQSEL_I2SRX),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_I2SRX),
         },
         [DMACH_I2S_OUT] = {
                 .name           = "i2s-sdo",
                 .channels       = MAP(S3C2412_DMAREQSEL_I2STX),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_I2STX),
         },
         [DMACH_USB_EP1] = {
                 .name           = "usb-ep1",
                 .channels       = MAP(S3C2412_DMAREQSEL_USBEP1),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_USBEP1),
         },
         [DMACH_USB_EP2] = {
                 .name           = "usb-ep2",
                 .channels       = MAP(S3C2412_DMAREQSEL_USBEP2),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_USBEP2),
         },
         [DMACH_USB_EP3] = {
                 .name           = "usb-ep3",
                 .channels       = MAP(S3C2412_DMAREQSEL_USBEP3),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_USBEP3),
         },
         [DMACH_USB_EP4] = {
                 .name           = "usb-ep4",
                 .channels       = MAP(S3C2412_DMAREQSEL_USBEP4),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_USBEP4),
         },
 };
 
-static void s3c2412_dma_direction(struct s3c2410_dma_chan *chan,
-                                  struct s3c24xx_dma_map *map,
-                                  enum dma_data_direction dir)
-{
-        unsigned long chsel;
-
-        if (dir == DMA_FROM_DEVICE)
-                chsel = map->channels_rx[0];
-        else
-                chsel = map->channels[0];
-
-        chsel &= ~DMA_CH_VALID;
-        chsel |= S3C2412_DMAREQSEL_HW;
-
-        writel(chsel, chan->regs + S3C2412_DMA_DMAREQSEL);
-}
-
 static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
                                struct s3c24xx_dma_map *map)
 {
-        s3c2412_dma_direction(chan, map, chan->source);
+        unsigned long chsel = map->channels[0] & (~DMA_CH_VALID);
+        writel(chsel | S3C2412_DMAREQSEL_HW,
+               chan->regs + S3C2412_DMA_DMAREQSEL);
 }
 
 static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
         .select         = s3c2412_dma_select,
-        .direction      = s3c2412_dma_direction,
         .dcon_mask      = 0,
         .map            = s3c2412_dma_mappings,
         .map_size       = ARRAY_SIZE(s3c2412_dma_mappings),
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index 5fe3539dc2b5..95b9f759fe97 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -128,7 +128,8 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
 static void s3c2443_dma_select(struct s3c2410_dma_chan *chan,
                                struct s3c24xx_dma_map *map)
 {
-        writel(map->channels[0] | S3C2443_DMAREQSEL_HW,
+        unsigned long chsel = map->channels[0] & (~DMA_CH_VALID);
+        writel(chsel | S3C2443_DMAREQSEL_HW,
                chan->regs + S3C2443_DMA_DMAREQSEL);
 }
 
diff --git a/arch/arm/mach-s3c24xx/dma.c b/arch/arm/mach-s3c24xx/dma.c
index aab64909e9a3..4a65cba3295d 100644
--- a/arch/arm/mach-s3c24xx/dma.c
+++ b/arch/arm/mach-s3c24xx/dma.c
@@ -1159,9 +1159,6 @@ int s3c2410_dma_devconfig(enum dma_ch channel,
                 return -EINVAL;
         }
 
-        if (dma_sel.direction != NULL)
-                (dma_sel.direction)(chan, chan->map, source);
-
         return 0;
 }
 
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 1a517e2fe449..757c4e97375f 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -36,10 +36,13 @@ config ARCH_R8A7740
         select RENESAS_INTC_IRQPIN
 
 config ARCH_R8A7778
-        bool "R-Car M1 (R8A77780)"
+        bool "R-Car M1A (R8A77781)"
+        select ARCH_WANT_OPTIONAL_GPIOLIB
         select CPU_V7
         select SH_CLK_CPG
         select ARM_GIC
+        select USB_ARCH_HAS_EHCI
+        select USB_ARCH_HAS_OHCI
 
 config ARCH_R8A7779
         bool "R-Car H1 (R8A77790)"
@@ -169,6 +172,8 @@ config MACH_KZM9D
 config MACH_KZM9G
         bool "KZM-A9-GT board"
         depends on ARCH_SH73A0
+        select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_OPP
         select ARCH_REQUIRE_GPIOLIB
         select REGULATOR_FIXED_VOLTAGE if REGULATOR
         select SND_SOC_AK4642 if SND_SIMPLE_CARD
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 45f78cadec1d..297bf5eec5ab 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1026,10 +1026,8 @@ out:
 
 /* TouchScreen */
 #ifdef CONFIG_AP4EVB_QHD
-# define GPIO_TSC_IRQ   GPIO_FN_IRQ28_123
 # define GPIO_TSC_PORT  123
 #else /* WVGA */
-# define GPIO_TSC_IRQ   GPIO_FN_IRQ7_40
 # define GPIO_TSC_PORT  40
 #endif
 
@@ -1037,22 +1035,12 @@ out:
 #define IRQ7    evt2irq(0x02e0) /* IRQ7A */
 static int ts_get_pendown_state(void)
 {
-        int val;
-
-        gpio_free(GPIO_TSC_IRQ);
-
-        gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL);
-
-        val = gpio_get_value(GPIO_TSC_PORT);
-
-        gpio_request(GPIO_TSC_IRQ, NULL);
-
-        return !val;
+        return !gpio_get_value(GPIO_TSC_PORT);
 }
 
 static int ts_init(void)
 {
-        gpio_request(GPIO_TSC_IRQ, NULL);
+        gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL);
 
         return 0;
 }
@@ -1086,11 +1074,42 @@ static struct i2c_board_info i2c1_devices[] = {
 
 
 static const struct pinctrl_map ap4evb_pinctrl_map[] = {
+        /* CEU */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_clk_0", "ceu"),
+        /* FSIA (AK4643) */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_sclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_data_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_data_out", "fsia"),
+        /* FSIB (HDMI) */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372",
+                                  "fsib_mclk_in", "fsib"),
+        /* HDMI */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372",
+                                  "hdmi", "hdmi"),
+        /* KEYSC */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372",
+                                  "keysc_in04_0", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372",
+                                  "keysc_out5", "keysc"),
+#ifndef CONFIG_AP4EVB_QHD
+        /* LCDC */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
+                                  "lcd_data18", "lcd"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
+                                  "lcd_sync", "lcd"),
+#endif
         /* MMCIF */
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
                                   "mmc0_data8_0", "mmc0"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
                                   "mmc0_ctrl_0", "mmc0"),
+        /* SCIFA0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372",
+                                  "scifa0_data", "scifa0"),
         /* SDHI0 */
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
                                   "sdhi0_data4", "sdhi0"),
@@ -1105,6 +1124,26 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = {
                                   "sdhi1_data4", "sdhi1"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
                                   "sdhi1_ctrl", "sdhi1"),
+        /* SMSC911X */
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
+                                  "bsc_cs5a", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
+                                  "intc_irq6_0", "intc"),
+        /* TSC2007 */
+#ifdef CONFIG_AP4EVB_QHD
+        PIN_MAP_MUX_GROUP_DEFAULT("1-0048", "pfc-sh7372",
+                                  "intc_irq28_0", "intc"),
+#else /* WVGA */
+        PIN_MAP_MUX_GROUP_DEFAULT("1-0048", "pfc-sh7372",
+                                  "intc_irq7_0", "intc"),
+#endif
+        /* USBHS1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372",
+                                  "usb1_vbus", "usb1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372",
+                                  "usb1_otg_id_0", "usb1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372",
+                                  "usb1_otg_ctrl_0", "usb1"),
 };
 
 #define GPIO_PORT9CR    IOMEM(0xE6051009)
@@ -1137,36 +1176,16 @@ static void __init ap4evb_init(void)
                                   ARRAY_SIZE(ap4evb_pinctrl_map));
         sh7372_pinmux_init();
 
-        /* enable SCIFA0 */
-        gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
-        gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
-
-        /* enable SMSC911X */
-        gpio_request(GPIO_FN_CS5A,      NULL);
-        gpio_request(GPIO_FN_IRQ6_39,   NULL);
-
         /* enable Debug switch (S6) */
         gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL);
         gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL);
         gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL);
         gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL);
 
-        /* USB enable */
-        gpio_request(GPIO_FN_VBUS0_1,    NULL);
-        gpio_request(GPIO_FN_IDIN_1_18,  NULL);
-        gpio_request(GPIO_FN_PWEN_1_115, NULL);
-        gpio_request(GPIO_FN_OVCN_1_114, NULL);
-        gpio_request(GPIO_FN_EXTLP_1,    NULL);
-        gpio_request(GPIO_FN_OVCN2_1,    NULL);
-
         /* setup USB phy */
         __raw_writew(0x8a0a, IOMEM(0xE6058130));        /* USBCR4 */
 
-        /* enable FSI2 port A (ak4643) */
-        gpio_request(GPIO_FN_FSIAIBT,   NULL);
-        gpio_request(GPIO_FN_FSIAILR,   NULL);
-        gpio_request(GPIO_FN_FSIAISLD,  NULL);
-        gpio_request(GPIO_FN_FSIAOSLD,  NULL);
+        /* FSI2 port A (ak4643) */
         gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
 
         gpio_request(9, NULL);
@@ -1177,8 +1196,7 @@ static void __init ap4evb_init(void)
         /* card detect pin for MMC slot (CN7) */
         gpio_request_one(41, GPIOF_IN, NULL);
 
-        /* setup FSI2 port B (HDMI) */
-        gpio_request(GPIO_FN_FSIBCK, NULL);
+        /* FSI2 port B (HDMI) */
         __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
 
         /* set SPU2 clock to 119.6 MHz */
@@ -1208,18 +1226,6 @@ static void __init ap4evb_init(void)
          * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON.
          */
 
-        /* enable KEYSC */
-        gpio_request(GPIO_FN_KEYOUT0, NULL);
-        gpio_request(GPIO_FN_KEYOUT1, NULL);
-        gpio_request(GPIO_FN_KEYOUT2, NULL);
-        gpio_request(GPIO_FN_KEYOUT3, NULL);
-        gpio_request(GPIO_FN_KEYOUT4, NULL);
-        gpio_request(GPIO_FN_KEYIN0_136, NULL);
-        gpio_request(GPIO_FN_KEYIN1_135, NULL);
-        gpio_request(GPIO_FN_KEYIN2_134, NULL);
-        gpio_request(GPIO_FN_KEYIN3_133, NULL);
-        gpio_request(GPIO_FN_KEYIN4,     NULL);
-
         /* enable TouchScreen */
         irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
 
@@ -1241,28 +1247,6 @@ static void __init ap4evb_init(void)
          * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and
          * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF.
          */
-
-        gpio_request(GPIO_FN_LCDD17,   NULL);
-        gpio_request(GPIO_FN_LCDD16,   NULL);
-        gpio_request(GPIO_FN_LCDD15,   NULL);
-        gpio_request(GPIO_FN_LCDD14,   NULL);
-        gpio_request(GPIO_FN_LCDD13,   NULL);
-        gpio_request(GPIO_FN_LCDD12,   NULL);
-        gpio_request(GPIO_FN_LCDD11,   NULL);
-        gpio_request(GPIO_FN_LCDD10,   NULL);
-        gpio_request(GPIO_FN_LCDD9,    NULL);
-        gpio_request(GPIO_FN_LCDD8,    NULL);
-        gpio_request(GPIO_FN_LCDD7,    NULL);
-        gpio_request(GPIO_FN_LCDD6,    NULL);
-        gpio_request(GPIO_FN_LCDD5,    NULL);
-        gpio_request(GPIO_FN_LCDD4,    NULL);
-        gpio_request(GPIO_FN_LCDD3,    NULL);
-        gpio_request(GPIO_FN_LCDD2,    NULL);
-        gpio_request(GPIO_FN_LCDD1,    NULL);
-        gpio_request(GPIO_FN_LCDD0,    NULL);
-        gpio_request(GPIO_FN_LCDDISP,  NULL);
-        gpio_request(GPIO_FN_LCDDCK,   NULL);
-
         gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
         gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
 
@@ -1288,8 +1272,6 @@ static void __init ap4evb_init(void)
          */
 
         /* MIPI-CSI stuff */
-        gpio_request(GPIO_FN_VIO_CKO, NULL);
-
         clk = clk_get(NULL, "vck1_clk");
         if (!IS_ERR(clk)) {
                 clk_set_rate(clk, clk_round_rate(clk, 13000000));
@@ -1299,10 +1281,6 @@ static void __init ap4evb_init(void)
 
         sh7372_add_standard_devices();
 
-        /* HDMI */
-        gpio_request(GPIO_FN_HDMI_HPD, NULL);
-        gpio_request(GPIO_FN_HDMI_CEC, NULL);
-
         /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
 #define SRCR4 IOMEM(0xe61580bc)
         srcr4 = __raw_readl(SRCR4);
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index b85b2882dbd0..44a621505eeb 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -584,7 +584,7 @@ static struct regulator_init_data vcc_sdhi0_init_data = {
 static struct fixed_voltage_config vcc_sdhi0_info = {
         .supply_name = "SDHI0 Vcc",
         .microvolts = 3300000,
-        .gpio = GPIO_PORT75,
+        .gpio = 75,
         .enable_high = 1,
         .init_data = &vcc_sdhi0_init_data,
 };
@@ -615,7 +615,7 @@ static struct regulator_init_data vccq_sdhi0_init_data = {
 };
 
 static struct gpio vccq_sdhi0_gpios[] = {
-        {GPIO_PORT17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" },
+        {17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" },
 };
 
 static struct gpio_regulator_state vccq_sdhi0_states[] = {
@@ -626,7 +626,7 @@ static struct gpio_regulator_state vccq_sdhi0_states[] = {
 static struct gpio_regulator_config vccq_sdhi0_info = {
         .supply_name = "vqmmc",
 
-        .enable_gpio = GPIO_PORT74,
+        .enable_gpio = 74,
         .enable_high = 1,
         .enabled_at_boot = 0,
 
@@ -664,7 +664,7 @@ static struct regulator_init_data vcc_sdhi1_init_data = {
 static struct fixed_voltage_config vcc_sdhi1_info = {
         .supply_name = "SDHI1 Vcc",
         .microvolts = 3300000,
-        .gpio = GPIO_PORT16,
+        .gpio = 16,
         .enable_high = 1,
         .init_data = &vcc_sdhi1_init_data,
 };
@@ -693,7 +693,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
         .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
                           MMC_CAP_POWER_OFF_CARD,
         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
-        .cd_gpio        = GPIO_PORT167,
+        .cd_gpio        = 167,
 };
 
 static struct resource sdhi0_resources[] = {
@@ -736,7 +736,7 @@ static struct sh_mobile_sdhi_info sdhi1_info = {
                           MMC_CAP_POWER_OFF_CARD,
         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
         /* Port72 cannot generate IRQs, will be used in polling mode. */
-        .cd_gpio        = GPIO_PORT72,
+        .cd_gpio        = 72,
 };
 
 static struct resource sdhi1_resources[] = {
@@ -1046,6 +1046,35 @@ static struct platform_device *eva_devices[] __initdata = {
 };
 
 static const struct pinctrl_map eva_pinctrl_map[] = {
+        /* CEU0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+                                  "ceu0_data_0_7", "ceu0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+                                  "ceu0_clk_0", "ceu0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+                                  "ceu0_sync", "ceu0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+                                  "ceu0_field", "ceu0"),
+        /* FSIA */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+                                  "fsia_sclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+                                  "fsia_mclk_out", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+                                  "fsia_data_in_1", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+                                  "fsia_data_out_0", "fsia"),
+        /* FSIB */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-r8a7740",
+                                  "fsib_mclk_in", "fsib"),
+        /* GETHER */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
+                                  "gether_mii", "gether"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
+                                  "gether_int", "gether"),
+        /* HDMI */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-r8a7740",
+                                  "hdmi", "hdmi"),
         /* LCD0 */
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
                                   "lcd0_data24_0", "lcd0"),
@@ -1058,6 +1087,9 @@ static const struct pinctrl_map eva_pinctrl_map[] = {
                                   "mmc0_data8_1", "mmc0"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
                                   "mmc0_ctrl_1", "mmc0"),
+        /* SCIFA1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740",
+                                  "scifa1_data", "scifa1"),
         /* SDHI0 */
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
                                   "sdhi0_data4", "sdhi0"),
@@ -1065,6 +1097,12 @@ static const struct pinctrl_map eva_pinctrl_map[] = {
                                   "sdhi0_ctrl", "sdhi0"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
                                   "sdhi0_wp", "sdhi0"),
+        /* ST1232 */
+        PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-r8a7740",
+                                  "intc_irq10", "intc"),
+        /* USBHS */
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7740",
+                                  "intc_irq7_1", "intc"),
 };
 
 static void __init eva_clock_init(void)
@@ -1119,40 +1157,14 @@ static void __init eva_init(void)
         r8a7740_pinmux_init();
         r8a7740_meram_workaround();
 
-        /* SCIFA1 */
-        gpio_request(GPIO_FN_SCIFA1_RXD, NULL);
-        gpio_request(GPIO_FN_SCIFA1_TXD, NULL);
-
         /* LCDC0 */
-        gpio_request(GPIO_FN_LCDC0_SELECT,      NULL);
-
         gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
         gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
 
         /* Touchscreen */
-        gpio_request(GPIO_FN_IRQ10,     NULL); /* TP_INT */
+        gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
 
         /* GETHER */
-        gpio_request(GPIO_FN_ET_CRS,            NULL);
-        gpio_request(GPIO_FN_ET_MDC,            NULL);
-        gpio_request(GPIO_FN_ET_MDIO,           NULL);
-        gpio_request(GPIO_FN_ET_TX_ER,          NULL);
-        gpio_request(GPIO_FN_ET_RX_ER,          NULL);
-        gpio_request(GPIO_FN_ET_ERXD0,          NULL);
-        gpio_request(GPIO_FN_ET_ERXD1,          NULL);
-        gpio_request(GPIO_FN_ET_ERXD2,          NULL);
-        gpio_request(GPIO_FN_ET_ERXD3,          NULL);
-        gpio_request(GPIO_FN_ET_TX_CLK,         NULL);
-        gpio_request(GPIO_FN_ET_TX_EN,          NULL);
-        gpio_request(GPIO_FN_ET_ETXD0,          NULL);
-        gpio_request(GPIO_FN_ET_ETXD1,          NULL);
-        gpio_request(GPIO_FN_ET_ETXD2,          NULL);
-        gpio_request(GPIO_FN_ET_ETXD3,          NULL);
-        gpio_request(GPIO_FN_ET_PHY_INT,        NULL);
-        gpio_request(GPIO_FN_ET_COL,            NULL);
-        gpio_request(GPIO_FN_ET_RX_DV,          NULL);
-        gpio_request(GPIO_FN_ET_RX_CLK,         NULL);
-
         gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
 
         /* USB */
@@ -1163,34 +1175,17 @@ static void __init eva_init(void)
         } else {
                 /* USB Func */
                 /*
-                 * A1 chip has 2 IRQ7 pin and it was controled by MSEL register.
-                 * OTOH, usbhs interrupt needs its value (HI/LOW) to decide
-                 * USB connection/disconnection (usbhsf_get_vbus()).
-                 * This means we needs to select GPIO_FN_IRQ7_PORT209 first,
-                 * and select GPIO 209 here
+                 * The USBHS interrupt handlers needs to read the IRQ pin value
+                 * (HI/LOW) to diffentiate USB connection and disconnection
+                 * events (usbhsf_get_vbus()). We thus need to select both the
+                 * intc_irq7_1 pin group and GPIO 209 here.
                  */
-                gpio_request(GPIO_FN_IRQ7_PORT209, NULL);
                 gpio_request_one(209, GPIOF_IN, NULL);
 
                 platform_device_register(&usbhsf_device);
                 usb = &usbhsf_device;
         }
 
-        /* CEU0 */
-        gpio_request(GPIO_FN_VIO0_D7,           NULL);
-        gpio_request(GPIO_FN_VIO0_D6,           NULL);
-        gpio_request(GPIO_FN_VIO0_D5,           NULL);
-        gpio_request(GPIO_FN_VIO0_D4,           NULL);
-        gpio_request(GPIO_FN_VIO0_D3,           NULL);
-        gpio_request(GPIO_FN_VIO0_D2,           NULL);
-        gpio_request(GPIO_FN_VIO0_D1,           NULL);
-        gpio_request(GPIO_FN_VIO0_D0,           NULL);
-        gpio_request(GPIO_FN_VIO0_CLK,          NULL);
-        gpio_request(GPIO_FN_VIO0_HD,           NULL);
-        gpio_request(GPIO_FN_VIO0_VD,           NULL);
-        gpio_request(GPIO_FN_VIO0_FIELD,        NULL);
-        gpio_request(GPIO_FN_VIO_CKO,           NULL);
-
         /* CON1/CON15 Camera */
         gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL);  /* STANDBY */
         gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
@@ -1198,24 +1193,11 @@ static void __init eva_init(void)
         gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL);  /* CAM_PON */
 
         /* FSI-WM8978 */
-        gpio_request(GPIO_FN_FSIAIBT,           NULL);
-        gpio_request(GPIO_FN_FSIAILR,           NULL);
-        gpio_request(GPIO_FN_FSIAOMC,           NULL);
-        gpio_request(GPIO_FN_FSIAOSLD,          NULL);
-        gpio_request(GPIO_FN_FSIAISLD_PORT5,    NULL);
-
         gpio_request(7, NULL);
         gpio_request(8, NULL);
         gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */
         gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */
 
-        /* FSI-HDMI */
-        gpio_request(GPIO_FN_FSIBCK,            NULL);
-
-        /* HDMI */
-        gpio_request(GPIO_FN_HDMI_HPD,          NULL);
-        gpio_request(GPIO_FN_HDMI_CEC,          NULL);
-
         /*
          * CAUTION
          *
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index 38e5e50fb318..7ed2401b899c 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -18,6 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
 #include <linux/smsc911x.h>
 #include <mach/common.h>
@@ -37,6 +38,20 @@ static struct resource smsc911x_resources[] = {
         DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */
 };
 
+static struct rcar_phy_platform_data usb_phy_platform_data __initdata;
+
+static const struct pinctrl_map bockw_pinctrl_map[] = {
+        /* SCIF0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
+                                  "scif0_data_a", "scif0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
+                                  "scif0_ctrl", "scif0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
+                                  "usb0", "usb0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
+                                  "usb1", "usb1"),
+};
+
 #define IRQ0MR  0x30
 static void __init bockw_init(void)
 {
@@ -45,6 +60,11 @@ static void __init bockw_init(void)
         r8a7778_clock_init();
         r8a7778_init_irq_extpin(1);
         r8a7778_add_standard_devices();
+        r8a7778_add_usb_phy_device(&usb_phy_platform_data);
+
+        pinctrl_register_mappings(bockw_pinctrl_map,
+                                  ARRAY_SIZE(bockw_pinctrl_map));
+        r8a7778_pinmux_init();
 
         fpga = ioremap_nocache(0x18200000, SZ_1M);
         if (fpga) {
@@ -78,4 +98,5 @@ DT_MACHINE_START(BOCKW_DT, "bockw")
         .init_machine   = bockw_init,
         .init_time      = shmobile_timer_init,
         .dt_compat      = bockw_boards_compat_dt,
+        .init_late      = r8a7778_init_late,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index 70d992c540ae..b373e9ced573 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -331,12 +331,6 @@ static struct platform_device smsc_device = {
 };
 
 /*
- * core board devices
- */
-static struct platform_device *bonito_core_devices[] __initdata = {
-};
-
-/*
  * base board devices
  */
 static struct platform_device *bonito_base_devices[] __initdata = {
@@ -375,12 +369,37 @@ static void __init bonito_map_io(void)
 #define VCCQ1CR         IOMEM(0xE6058140)
 #define VCCQ1LCDCR      IOMEM(0xE6058186)
 
+/*
+ * HACK: The FPGA mappings should be associated with the FPGA device, but we
+ * don't have one at the moment. Associate them with the PFC device to make
+ * sure they will be applied.
+ */
+static const struct pinctrl_map fpga_pinctrl_map[] = {
+        /* FPGA */
+        PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
+                                  "bsc_cs5a_0", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
+                                  "bsc_cs5b", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
+                                  "bsc_cs6a", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
+                                  "intc_irq10", "intc"),
+};
+
+static const struct pinctrl_map scifa5_pinctrl_map[] = {
+        /* SCIFA5 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.5", "pfc-r8a7740",
+                                  "scifa5_data_2", "scifa5"),
+};
+
 static void __init bonito_init(void)
 {
         u16 val;
 
         regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 
+        pinctrl_register_mappings(fpga_pinctrl_map,
+                                  ARRAY_SIZE(fpga_pinctrl_map));
         r8a7740_pinmux_init();
         bonito_fpga_init();
 
@@ -397,9 +416,6 @@ static void __init bonito_init(void)
 
         r8a7740_add_standard_devices();
 
-        platform_add_devices(bonito_core_devices,
-                             ARRAY_SIZE(bonito_core_devices));
-
         /*
          * base board settings
          */
@@ -409,14 +425,6 @@ static void __init bonito_init(void)
                 u16 bsw3;
                 u16 bsw4;
 
-                /*
-                 * FPGA
-                 */
-                gpio_request(GPIO_FN_CS5B,              NULL);
-                gpio_request(GPIO_FN_CS6A,              NULL);
-                gpio_request(GPIO_FN_CS5A_PORT105,      NULL);
-                gpio_request(GPIO_FN_IRQ10,             NULL);
-
                 val = bonito_fpga_read(BVERR);
                 pr_info("bonito version: cpu %02x, base %02x\n",
                         ((val >> 8) & 0xFF),
@@ -432,8 +440,8 @@ static void __init bonito_init(void)
                 if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
                     BIT_OFF(bsw3, 9) && /* S39.6 = ON */
                     BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
-                        gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL);
-                        gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
+                        pinctrl_register_mappings(scifa5_pinctrl_map,
+                                                  ARRAY_SIZE(scifa5_pinctrl_map));
                 }
 
                 /*
@@ -443,7 +451,6 @@ static void __init bonito_init(void)
                     BIT_ON(bsw2, 2)) {  /* S38.2 = OFF */
                         pinctrl_register_mappings(lcdc0_pinctrl_map,
                                                   ARRAY_SIZE(lcdc0_pinctrl_map));
-                        gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
 
                         gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
                                          NULL); /* LCDDON */
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index aefa50d385b7..44055fe8a45c 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -79,7 +79,6 @@ static void __init kzm_init(void)
         sh73a0_pinmux_init();
 
         /* enable SD */
-        gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
         gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
 
         gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index e6b775a10aad..1fdf05cb6da1 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -663,13 +663,13 @@ static unsigned long pin_pullup_conf[] = {
 
 static const struct pinctrl_map kzm_pinctrl_map[] = {
         /* FSIA (AK4648) */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
                                   "fsia_mclk_in", "fsia"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
                                   "fsia_sclk_in", "fsia"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
                                   "fsia_data_in", "fsia"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
                                   "fsia_data_out", "fsia"),
         /* I2C3 */
         PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
@@ -788,9 +788,6 @@ static void __init kzm_init(void)
         /* Touchscreen */
         gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
 
-        /* enable SD */
-        gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
-
 #ifdef CONFIG_CACHE_L2X0
         /* Early BRESP enable, Shared attribute override enable, 64K*8way */
         l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index f587187a8603..6114edd0a977 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -21,15 +21,30 @@
 #include <linux/interrupt.h>
 #include <linux/irqchip.h>
 #include <linux/kernel.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
 #include <mach/common.h>
 #include <mach/r8a7790.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+static const struct pinctrl_map lager_pinctrl_map[] = {
+        /* SCIF0 (CN19: DEBUG SERIAL0) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
+                                  "scif0_data", "scif0"),
+        /* SCIF1 (CN20: DEBUG SERIAL1) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
+                                  "scif1_data", "scif1"),
+};
+
 static void __init lager_add_standard_devices(void)
 {
         r8a7790_clock_init();
+
+        pinctrl_register_mappings(lager_pinctrl_map,
+                                  ARRAY_SIZE(lager_pinctrl_map));
+        r8a7790_pinmux_init();
+
         r8a7790_add_standard_devices();
 }
 
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index fa3407da682a..85f51a849a50 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1309,6 +1309,49 @@ static struct i2c_board_info i2c1_devices[] = {
 };
 
 static const struct pinctrl_map mackerel_pinctrl_map[] = {
+        /* ADXL34X */
+        PIN_MAP_MUX_GROUP_DEFAULT("1-0053", "pfc-sh7372",
+                                  "intc_irq21", "intc"),
+        /* CEU */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_data_0_7", "ceu"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_clk_0", "ceu"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_sync", "ceu"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_field", "ceu"),
+        /* FLCTL */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
+                                  "flctl_data", "flctl"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
+                                  "flctl_ce0", "flctl"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
+                                  "flctl_ctrl", "flctl"),
+        /* FSIA (AK4643) */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_sclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_data_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_data_out", "fsia"),
+        /* FSIB (HDMI) */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372",
+                                  "fsib_mclk_in", "fsib"),
+        /* HDMI */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372",
+                                  "hdmi", "hdmi"),
+        /* LCDC */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
+                                  "lcd_data24", "lcd"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
+                                  "lcd_sync", "lcd"),
+        /* SCIFA0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372",
+                                  "scifa0_data", "scifa0"),
+        /* SCIFA2 (GT-720F GPS module) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh7372",
+                                  "scifa2_data", "scifa2"),
         /* SDHI0 */
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
                                   "sdhi0_data4", "sdhi0"),
@@ -1316,6 +1359,8 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
                                   "sdhi0_ctrl", "sdhi0"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
                                   "sdhi0_wp", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+                                  "intc_irq26_1", "intc"),
         /* SDHI1 */
 #if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
@@ -1334,6 +1379,25 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
                                   "sdhi2_data4", "sdhi2"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
                                   "sdhi2_ctrl", "sdhi2"),
+        /* SMSC911X */
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
+                                  "bsc_cs5a", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
+                                  "intc_irq6_0", "intc"),
+        /* ST1232 */
+        PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-sh7372",
+                                  "intc_irq7_0", "intc"),
+        /* TCA6416 */
+        PIN_MAP_MUX_GROUP_DEFAULT("0-0020", "pfc-sh7372",
+                                  "intc_irq9_0", "intc"),
+        /* USBHS0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.0", "pfc-sh7372",
+                                  "usb0_vbus", "usb0"),
+        /* USBHS1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
+                                  "usb1_vbus", "usb1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
+                                  "usb1_otg_id_0", "usb1"),
 };
 
 #define GPIO_PORT9CR    IOMEM(0xE6051009)
@@ -1377,61 +1441,18 @@ static void __init mackerel_init(void)
                                   ARRAY_SIZE(mackerel_pinctrl_map));
         sh7372_pinmux_init();
 
-        /* enable SCIFA0 */
-        gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
-        gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
-
-        /* enable SMSC911X */
-        gpio_request(GPIO_FN_CS5A,      NULL);
-        gpio_request(GPIO_FN_IRQ6_39,   NULL);
-
-        /* LCDC */
-        gpio_request(GPIO_FN_LCDD23,   NULL);
-        gpio_request(GPIO_FN_LCDD22,   NULL);
-        gpio_request(GPIO_FN_LCDD21,   NULL);
-        gpio_request(GPIO_FN_LCDD20,   NULL);
-        gpio_request(GPIO_FN_LCDD19,   NULL);
-        gpio_request(GPIO_FN_LCDD18,   NULL);
-        gpio_request(GPIO_FN_LCDD17,   NULL);
-        gpio_request(GPIO_FN_LCDD16,   NULL);
-        gpio_request(GPIO_FN_LCDD15,   NULL);
-        gpio_request(GPIO_FN_LCDD14,   NULL);
-        gpio_request(GPIO_FN_LCDD13,   NULL);
-        gpio_request(GPIO_FN_LCDD12,   NULL);
-        gpio_request(GPIO_FN_LCDD11,   NULL);
-        gpio_request(GPIO_FN_LCDD10,   NULL);
-        gpio_request(GPIO_FN_LCDD9,    NULL);
-        gpio_request(GPIO_FN_LCDD8,    NULL);
-        gpio_request(GPIO_FN_LCDD7,    NULL);
-        gpio_request(GPIO_FN_LCDD6,    NULL);
-        gpio_request(GPIO_FN_LCDD5,    NULL);
-        gpio_request(GPIO_FN_LCDD4,    NULL);
-        gpio_request(GPIO_FN_LCDD3,    NULL);
-        gpio_request(GPIO_FN_LCDD2,    NULL);
-        gpio_request(GPIO_FN_LCDD1,    NULL);
-        gpio_request(GPIO_FN_LCDD0,    NULL);
-        gpio_request(GPIO_FN_LCDDISP,  NULL);
-        gpio_request(GPIO_FN_LCDDCK,   NULL);
-
         /* backlight, off by default */
         gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL);
 
         gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
 
         /* USBHS0 */
-        gpio_request(GPIO_FN_VBUS0_0, NULL);
         gpio_request_pulldown(GPIO_PORT168CR); /* VBUS0_0 pull down */
 
         /* USBHS1 */
-        gpio_request(GPIO_FN_VBUS0_1, NULL);
         gpio_request_pulldown(GPIO_PORT167CR); /* VBUS0_1 pull down */
-        gpio_request(GPIO_FN_IDIN_1_113, NULL);
 
-        /* enable FSI2 port A (ak4643) */
-        gpio_request(GPIO_FN_FSIAIBT,   NULL);
-        gpio_request(GPIO_FN_FSIAILR,   NULL);
-        gpio_request(GPIO_FN_FSIAISLD,  NULL);
-        gpio_request(GPIO_FN_FSIAOSLD,  NULL);
+        /* FSI2 port A (ak4643) */
         gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
 
         gpio_request(9,  NULL);
@@ -1441,8 +1462,7 @@ static void __init mackerel_init(void)
 
         intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */
 
-        /* setup FSI2 port B (HDMI) */
-        gpio_request(GPIO_FN_FSIBCK, NULL);
+        /* FSI2 port B (HDMI) */
         __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
 
         /* set SPU2 clock to 119.6 MHz */
@@ -1452,68 +1472,15 @@ static void __init mackerel_init(void)
                 clk_put(clk);
         }
 
-        /* enable Keypad */
-        gpio_request(GPIO_FN_IRQ9_42,   NULL);
+        /* Keypad */
         irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
 
-        /* enable Touchscreen */
-        gpio_request(GPIO_FN_IRQ7_40,   NULL);
+        /* Touchscreen */
         irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
 
-        /* enable Accelerometer */
-        gpio_request(GPIO_FN_IRQ21,     NULL);
+        /* Accelerometer */
         irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
 
-        /* SDHI0 PORT172 card-detect IRQ26 */
-        gpio_request(GPIO_FN_IRQ26_172, NULL);
-
-        /* FLCTL */
-        gpio_request(GPIO_FN_D0_NAF0, NULL);
-        gpio_request(GPIO_FN_D1_NAF1, NULL);
-        gpio_request(GPIO_FN_D2_NAF2, NULL);
-        gpio_request(GPIO_FN_D3_NAF3, NULL);
-        gpio_request(GPIO_FN_D4_NAF4, NULL);
-        gpio_request(GPIO_FN_D5_NAF5, NULL);
-        gpio_request(GPIO_FN_D6_NAF6, NULL);
-        gpio_request(GPIO_FN_D7_NAF7, NULL);
-        gpio_request(GPIO_FN_D8_NAF8, NULL);
-        gpio_request(GPIO_FN_D9_NAF9, NULL);
-        gpio_request(GPIO_FN_D10_NAF10, NULL);
-        gpio_request(GPIO_FN_D11_NAF11, NULL);
-        gpio_request(GPIO_FN_D12_NAF12, NULL);
-        gpio_request(GPIO_FN_D13_NAF13, NULL);
-        gpio_request(GPIO_FN_D14_NAF14, NULL);
-        gpio_request(GPIO_FN_D15_NAF15, NULL);
-        gpio_request(GPIO_FN_FCE0, NULL);
-        gpio_request(GPIO_FN_WE0_FWE, NULL);
-        gpio_request(GPIO_FN_FRB, NULL);
-        gpio_request(GPIO_FN_A4_FOE, NULL);
-        gpio_request(GPIO_FN_A5_FCDE, NULL);
-        gpio_request(GPIO_FN_RD_FSC, NULL);
-
-        /* enable GPS module (GT-720F) */
-        gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
-        gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
-
-        /* CEU */
-        gpio_request(GPIO_FN_VIO_CLK, NULL);
-        gpio_request(GPIO_FN_VIO_VD, NULL);
-        gpio_request(GPIO_FN_VIO_HD, NULL);
-        gpio_request(GPIO_FN_VIO_FIELD, NULL);
-        gpio_request(GPIO_FN_VIO_CKO, NULL);
-        gpio_request(GPIO_FN_VIO_D7, NULL);
-        gpio_request(GPIO_FN_VIO_D6, NULL);
-        gpio_request(GPIO_FN_VIO_D5, NULL);
-        gpio_request(GPIO_FN_VIO_D4, NULL);
-        gpio_request(GPIO_FN_VIO_D3, NULL);
-        gpio_request(GPIO_FN_VIO_D2, NULL);
-        gpio_request(GPIO_FN_VIO_D1, NULL);
-        gpio_request(GPIO_FN_VIO_D0, NULL);
-
-        /* HDMI */
-        gpio_request(GPIO_FN_HDMI_HPD, NULL);
-        gpio_request(GPIO_FN_HDMI_CEC, NULL);
-
         /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
         srcr4 = __raw_readl(SRCR4);
         __raw_writel(srcr4 | (1 << 13), SRCR4);
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index b9594e911ce7..b1b41b199f99 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -28,6 +28,7 @@
 #include <linux/leds.h>
 #include <linux/dma-mapping.h>
 #include <linux/pinctrl/machine.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
@@ -36,10 +37,6 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ehci_pdriver.h>
-#include <linux/usb/ohci_pdriver.h>
-#include <linux/pm_runtime.h>
 #include <mach/hardware.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
@@ -60,6 +57,8 @@ static struct regulator_consumer_supply dummy_supplies[] = {
         REGULATOR_SUPPLY("vdd33a", "smsc911x"),
 };
 
+static struct rcar_phy_platform_data usb_phy_platform_data __initdata;
+
 /* SMSC LAN89218 */
 static struct resource smsc911x_resources[] = {
         [0] = {
@@ -149,39 +148,19 @@ static struct platform_device hspi_device = {
         .num_resources  = ARRAY_SIZE(hspi_resources),
 };
 
-/* USB PHY */
-static struct resource usb_phy_resources[] = {
-        [0] = {
-                .start          = 0xffe70000,
-                .end            = 0xffe70900 - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start          = 0xfff70000,
-                .end            = 0xfff70900 - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device usb_phy_device = {
-        .name           = "rcar_usb_phy",
-        .resource       = usb_phy_resources,
-        .num_resources  = ARRAY_SIZE(usb_phy_resources),
-};
-
 /* LEDS */
 static struct gpio_led marzen_leds[] = {
         {
                 .name           = "led2",
-                .gpio           = 157,
+                .gpio           = RCAR_GP_PIN(4, 29),
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         }, {
                 .name           = "led3",
-                .gpio           = 158,
+                .gpio           = RCAR_GP_PIN(4, 30),
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         }, {
                 .name           = "led4",
-                .gpio           = 159,
+                .gpio           = RCAR_GP_PIN(4, 31),
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         },
 };
@@ -204,161 +183,9 @@ static struct platform_device *marzen_devices[] __initdata = {
         &sdhi0_device,
         &thermal_device,
         &hspi_device,
-        &usb_phy_device,
         &leds_device,
 };
 
-/* USB */
-static struct usb_phy *phy;
-static int usb_power_on(struct platform_device *pdev)
-{
-        if (IS_ERR(phy))
-                return PTR_ERR(phy);
-
-        pm_runtime_enable(&pdev->dev);
-        pm_runtime_get_sync(&pdev->dev);
-
-        usb_phy_init(phy);
-
-        return 0;
-}
-
-static void usb_power_off(struct platform_device *pdev)
-{
-        if (IS_ERR(phy))
-                return;
-
-        usb_phy_shutdown(phy);
-
-        pm_runtime_put_sync(&pdev->dev);
-        pm_runtime_disable(&pdev->dev);
-}
-
-static struct usb_ehci_pdata ehcix_pdata = {
-        .power_on       = usb_power_on,
-        .power_off      = usb_power_off,
-        .power_suspend  = usb_power_off,
-};
-
-static struct resource ehci0_resources[] = {
-        [0] = {
-                .start  = 0xffe70000,
-                .end    = 0xffe70400 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = gic_iid(0x4c),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device ehci0_device = {
-        .name   = "ehci-platform",
-        .id     = 0,
-        .dev    = {
-                .dma_mask               = &ehci0_device.dev.coherent_dma_mask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &ehcix_pdata,
-        },
-        .num_resources  = ARRAY_SIZE(ehci0_resources),
-        .resource       = ehci0_resources,
-};
-
-static struct resource ehci1_resources[] = {
-        [0] = {
-                .start  = 0xfff70000,
-                .end    = 0xfff70400 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = gic_iid(0x4d),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device ehci1_device = {
-        .name   = "ehci-platform",
-        .id     = 1,
-        .dev    = {
-                .dma_mask               = &ehci1_device.dev.coherent_dma_mask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &ehcix_pdata,
-        },
-        .num_resources  = ARRAY_SIZE(ehci1_resources),
-        .resource       = ehci1_resources,
-};
-
-static struct usb_ohci_pdata ohcix_pdata = {
-        .power_on       = usb_power_on,
-        .power_off      = usb_power_off,
-        .power_suspend  = usb_power_off,
-};
-
-static struct resource ohci0_resources[] = {
-        [0] = {
-                .start  = 0xffe70400,
-                .end    = 0xffe70800 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = gic_iid(0x4c),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device ohci0_device = {
-        .name   = "ohci-platform",
-        .id     = 0,
-        .dev    = {
-                .dma_mask               = &ohci0_device.dev.coherent_dma_mask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &ohcix_pdata,
-        },
-        .num_resources  = ARRAY_SIZE(ohci0_resources),
-        .resource       = ohci0_resources,
-};
-
-static struct resource ohci1_resources[] = {
-        [0] = {
-                .start  = 0xfff70400,
-                .end    = 0xfff70800 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = gic_iid(0x4d),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device ohci1_device = {
-        .name   = "ohci-platform",
-        .id     = 1,
-        .dev    = {
-                .dma_mask               = &ohci1_device.dev.coherent_dma_mask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &ohcix_pdata,
-        },
-        .num_resources  = ARRAY_SIZE(ohci1_resources),
-        .resource       = ohci1_resources,
-};
-
-static struct platform_device *marzen_late_devices[] __initdata = {
-        &ehci0_device,
-        &ehci1_device,
-        &ohci0_device,
-        &ohci1_device,
-};
-
-void __init marzen_init_late(void)
-{
-        /* get usb phy */
-        phy = usb_get_phy(USB_PHY_TYPE_USB2);
-
-        shmobile_init_late();
-        platform_add_devices(marzen_late_devices,
-                             ARRAY_SIZE(marzen_late_devices));
-}
-
 static const struct pinctrl_map marzen_pinctrl_map[] = {
         /* HSPI0 */
         PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779",
@@ -406,6 +233,7 @@ static void __init marzen_init(void)
         r8a7779_pinmux_init();
 
         r8a7779_add_standard_devices();
+        r8a7779_add_usb_phy_device(&usb_phy_platform_data);
         platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
 }
 
@@ -416,6 +244,6 @@ MACHINE_START(MARZEN, "marzen")
         .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = r8a7779_init_irq,
         .init_machine   = marzen_init,
-        .init_late      = marzen_init_late,
+        .init_late      = r8a7779_init_late,
         .init_time      = r8a7779_earlytimer_init,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index e710c00c3822..5f7fe628b8a1 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -22,15 +22,44 @@
 #include <linux/kernel.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x270
 
-#define MPCKCR 0xe6150080
 #define SMSTPCR2 0xe6150138
+#define SMSTPCR3 0xe615013c
 #define SMSTPCR5 0xe6150144
 
+#define FRQCRA          0xE6150000
+#define FRQCRB          0xE6150004
+#define VCLKCR1         0xE6150008
+#define VCLKCR2         0xE615000C
+#define VCLKCR3         0xE615001C
+#define VCLKCR4         0xE6150014
+#define VCLKCR5         0xE6150034
+#define ZBCKCR          0xE6150010
+#define SD0CKCR         0xE6150074
+#define SD1CKCR         0xE6150078
+#define SD2CKCR         0xE615007C
+#define MMC0CKCR        0xE6150240
+#define MMC1CKCR        0xE6150244
+#define FSIACKCR        0xE6150018
+#define FSIBCKCR        0xE6150090
+#define MPCKCR          0xe6150080
+#define SPUVCKCR        0xE6150094
+#define HSICKCR         0xE615026C
+#define M4CKCR          0xE6150098
+#define PLLECR          0xE61500D0
+#define PLL1CR          0xE6150028
+#define PLL2CR          0xE615002C
+#define PLL2SCR         0xE61501F4
+#define PLL2HCR         0xE61501E4
+#define CKSCR           0xE61500C0
+
+#define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base)
+
 static struct clk_mapping cpg_mapping = {
         .phys   = CPG_BASE,
         .len    = CPG_LEN,
@@ -51,29 +80,327 @@ static struct clk extal2_clk = {
         .mapping        = &cpg_mapping,
 };
 
+static struct sh_clk_ops followparent_clk_ops = {
+        .recalc = followparent_recalc,
+};
+
+static struct clk main_clk = {
+        /* .parent will be set r8a73a4_clock_init */
+        .ops    = &followparent_clk_ops,
+};
+
+SH_CLK_RATIO(div2,      1, 2);
+SH_CLK_RATIO(div4,      1, 4);
+
+SH_FIXED_RATIO_CLK(main_div2_clk,       main_clk,               div2);
+SH_FIXED_RATIO_CLK(extal1_div2_clk,     extal1_clk,             div2);
+SH_FIXED_RATIO_CLK(extal2_div2_clk,     extal2_clk,             div2);
+SH_FIXED_RATIO_CLK(extal2_div4_clk,     extal2_clk,             div4);
+
+/* External FSIACK/FSIBCK clock */
+static struct clk fsiack_clk = {
+};
+
+static struct clk fsibck_clk = {
+};
+
+/*
+ *              PLL clocks
+ */
+static struct clk *pll_parent_main[] = {
+        [0] = &main_clk,
+        [1] = &main_div2_clk
+};
+
+static struct clk *pll_parent_main_extal[8] = {
+        [0] = &main_div2_clk,
+        [1] = &extal2_div2_clk,
+        [3] = &extal2_div4_clk,
+        [4] = &main_clk,
+        [5] = &extal2_clk,
+};
+
+static unsigned long pll_recalc(struct clk *clk)
+{
+        unsigned long mult = 1;
+
+        if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit))
+                mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1);
+
+        return clk->parent->rate * mult;
+}
+
+static int pll_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 val;
+        int i, ret;
+
+        if (!clk->parent_table || !clk->parent_num)
+                return -EINVAL;
+
+        /* Search the parent */
+        for (i = 0; i < clk->parent_num; i++)
+                if (clk->parent_table[i] == parent)
+                        break;
+
+        if (i == clk->parent_num)
+                return -ENODEV;
+
+        ret = clk_reparent(clk, parent);
+        if (ret < 0)
+                return ret;
+
+        val = ioread32(clk->mapped_reg) &
+                ~(((1 << clk->src_width) - 1) << clk->src_shift);
+
+        iowrite32(val | i << clk->src_shift, clk->mapped_reg);
+
+        return 0;
+}
+
+static struct sh_clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
+        .set_parent     = pll_set_parent,
+};
+
+#define PLL_CLOCK(name, p, pt, w, s, reg, e)            \
+        static struct clk name = {                      \
+                .ops            = &pll_clk_ops,         \
+                .flags          = CLK_ENABLE_ON_INIT,   \
+                .parent         = p,                    \
+                .parent_table   = pt,                   \
+                .parent_num     = ARRAY_SIZE(pt),       \
+                .src_width      = w,                    \
+                .src_shift      = s,                    \
+                .enable_reg     = (void __iomem *)reg,  \
+                .enable_bit     = e,                    \
+                .mapping        = &cpg_mapping,         \
+        }
+
+PLL_CLOCK(pll1_clk,  &main_clk,      pll_parent_main,       1, 7, PLL1CR,  1);
+PLL_CLOCK(pll2_clk,  &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR,  2);
+PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
+PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
+
+SH_FIXED_RATIO_CLK(pll1_div2_clk,       pll1_clk,       div2);
+
 static struct clk *main_clks[] = {
         &extalr_clk,
         &extal1_clk,
+        &extal1_div2_clk,
         &extal2_clk,
+        &extal2_div2_clk,
+        &extal2_div4_clk,
+        &main_clk,
+        &main_div2_clk,
+        &fsiack_clk,
+        &fsibck_clk,
+        &pll1_clk,
+        &pll1_div2_clk,
+        &pll2_clk,
+        &pll2s_clk,
+        &pll2h_clk,
+};
+
+/* DIV4 */
+static void div4_kick(struct clk *clk)
+{
+        unsigned long value;
+
+        /* set KICK bit in FRQCRB to update hardware setting */
+        value = ioread32(CPG_MAP(FRQCRB));
+        value |= (1 << 31);
+        iowrite32(value, CPG_MAP(FRQCRB));
+}
+
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
+
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors       = divisors,
+        .nr_divisors    = ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+        .kick           = div4_kick,
+};
+
+enum {
+        DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
+        DIV4_ZX, DIV4_ZS, DIV4_HP,
+        DIV4_NR };
+
+static struct clk div4_clks[DIV4_NR] = {
+        [DIV4_I]        = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT),
+        [DIV4_M3]       = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
+        [DIV4_B]        = SH_CLK_DIV4(&pll1_clk, FRQCRA,  8, 0x0dff, CLK_ENABLE_ON_INIT),
+        [DIV4_M1]       = SH_CLK_DIV4(&pll1_clk, FRQCRA,  4, 0x1dff, 0),
+        [DIV4_M2]       = SH_CLK_DIV4(&pll1_clk, FRQCRA,  0, 0x1dff, 0),
+        [DIV4_ZX]       = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0),
+        [DIV4_ZS]       = SH_CLK_DIV4(&pll1_clk, FRQCRB,  8, 0x0dff, 0),
+        [DIV4_HP]       = SH_CLK_DIV4(&pll1_clk, FRQCRB,  4, 0x0dff, 0),
 };
 
 enum {
+        DIV6_ZB,
+        DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
+        DIV6_MMC0, DIV6_MMC1,
+        DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VCK4, DIV6_VCK5,
+        DIV6_FSIA, DIV6_FSIB,
+        DIV6_MP, DIV6_M4, DIV6_HSI, DIV6_SPUV,
+        DIV6_NR };
+
+static struct clk *div6_parents[8] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2s_clk,
+        [3] = &extal2_clk,
+        [4] = &main_div2_clk,
+        [6] = &extalr_clk,
+};
+
+static struct clk *fsia_parents[4] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2s_clk,
+        [2] = &fsiack_clk,
+};
+
+static struct clk *fsib_parents[4] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2s_clk,
+        [2] = &fsibck_clk,
+};
+
+static struct clk *mp_parents[4] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2s_clk,
+        [2] = &extal2_clk,
+        [3] = &extal2_clk,
+};
+
+static struct clk *m4_parents[2] = {
+        [0] = &pll2s_clk,
+};
+
+static struct clk *hsi_parents[4] = {
+        [0] = &pll2h_clk,
+        [1] = &pll1_div2_clk,
+        [3] = &pll2s_clk,
+};
+
+/*** FIXME ***
+ * SH_CLK_DIV6_EXT() macro doesn't care .mapping
+ * but, it is necessary on R-Car (= ioremap() base CPG)
+ * The difference between
+ * SH_CLK_DIV6_EXT() <--> SH_CLK_MAP_DIV6_EXT()
+ * is only .mapping
+ */
+#define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents,                     \
+                            _num_parents, _src_shift, _src_width)       \
+{                                                                       \
+        .enable_reg     = (void __iomem *)_reg,                         \
+        .enable_bit     = 0, /* unused */                               \
+        .flags          = _flags | CLK_MASK_DIV_ON_DISABLE,             \
+        .div_mask       = SH_CLK_DIV6_MSK,                              \
+        .parent_table   = _parents,                                     \
+        .parent_num     = _num_parents,                                 \
+        .src_shift      = _src_shift,                                   \
+        .src_width      = _src_width,                                   \
+        .mapping        = &cpg_mapping,                                 \
+}
+
+static struct clk div6_clks[DIV6_NR] = {
+        [DIV6_ZB] = SH_CLK_MAP_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
+                                div6_parents, 2, 7, 1),
+        [DIV6_SDHI0] = SH_CLK_MAP_DIV6_EXT(SD0CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_SDHI1] = SH_CLK_MAP_DIV6_EXT(SD1CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_SDHI2] = SH_CLK_MAP_DIV6_EXT(SD2CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_MMC0] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_MMC1] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_VCK1] = SH_CLK_MAP_DIV6_EXT(VCLKCR1, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_VCK2] = SH_CLK_MAP_DIV6_EXT(VCLKCR2, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_VCK3] = SH_CLK_MAP_DIV6_EXT(VCLKCR3, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_VCK4] = SH_CLK_MAP_DIV6_EXT(VCLKCR4, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_VCK5] = SH_CLK_MAP_DIV6_EXT(VCLKCR5, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_FSIA] = SH_CLK_MAP_DIV6_EXT(FSIACKCR, 0,
+                                fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2),
+        [DIV6_FSIB] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR, 0,
+                                fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
+        [DIV6_MP] = SH_CLK_MAP_DIV6_EXT(MPCKCR, 0, /* it needs bit[9-11] control */
+                                mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
+        /* pll2s will be selected always for M4 */
+        [DIV6_M4] = SH_CLK_MAP_DIV6_EXT(M4CKCR, 0, /* it needs bit[9] control */
+                                m4_parents, ARRAY_SIZE(m4_parents), 6, 1),
+        [DIV6_HSI] = SH_CLK_MAP_DIV6_EXT(HSICKCR, 0, /* it needs bit[9] control */
+                                hsi_parents, ARRAY_SIZE(hsi_parents), 6, 2),
+        [DIV6_SPUV] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR, 0,
+                                mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
+};
+
+/* MSTP */
+enum {
         MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
+        MSTP315, MSTP314, MSTP313, MSTP312, MSTP305,
         MSTP522,
         MSTP_NR
 };
 
 static struct clk mstp_clks[MSTP_NR] = {
-        [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
-        [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
-        [MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
-        [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
-        [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
-        [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */
+        [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 4, 0), /* SCIFA0 */
+        [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 3, 0), /* SCIFA1 */
+        [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 6, 0), /* SCIFB0 */
+        [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 7, 0), /* SCIFB1 */
+        [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 16, 0), /* SCIFB2 */
+        [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 17, 0), /* SCIFB3 */
+        [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
+        [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
+        [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */
+        [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */
+        [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */
         [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
 };
 
 static struct clk_lookup lookups[] = {
+        /* main clock */
+        CLKDEV_CON_ID("extal1",                 &extal1_clk),
+        CLKDEV_CON_ID("extal1_div2",            &extal1_div2_clk),
+        CLKDEV_CON_ID("extal2",                 &extal2_clk),
+        CLKDEV_CON_ID("extal2_div2",            &extal2_div2_clk),
+        CLKDEV_CON_ID("extal2_div4",            &extal2_div4_clk),
+        CLKDEV_CON_ID("fsiack",                 &fsiack_clk),
+        CLKDEV_CON_ID("fsibck",                 &fsibck_clk),
+
+        /* pll clock */
+        CLKDEV_CON_ID("pll1",                   &pll1_clk),
+        CLKDEV_CON_ID("pll1_div2",              &pll1_div2_clk),
+        CLKDEV_CON_ID("pll2",                   &pll2_clk),
+        CLKDEV_CON_ID("pll2s",                  &pll2s_clk),
+        CLKDEV_CON_ID("pll2h",                  &pll2h_clk),
+
+        /* DIV6 */
+        CLKDEV_CON_ID("zb",                     &div6_clks[DIV6_ZB]),
+        CLKDEV_CON_ID("vck1",                   &div6_clks[DIV6_VCK1]),
+        CLKDEV_CON_ID("vck2",                   &div6_clks[DIV6_VCK2]),
+        CLKDEV_CON_ID("vck3",                   &div6_clks[DIV6_VCK3]),
+        CLKDEV_CON_ID("vck4",                   &div6_clks[DIV6_VCK4]),
+        CLKDEV_CON_ID("vck5",                   &div6_clks[DIV6_VCK5]),
+        CLKDEV_CON_ID("fsia",                   &div6_clks[DIV6_FSIA]),
+        CLKDEV_CON_ID("fsib",                   &div6_clks[DIV6_FSIB]),
+        CLKDEV_CON_ID("mp",                     &div6_clks[DIV6_MP]),
+        CLKDEV_CON_ID("m4",                     &div6_clks[DIV6_M4]),
+        CLKDEV_CON_ID("hsi",                    &div6_clks[DIV6_HSI]),
+        CLKDEV_CON_ID("spuv",                   &div6_clks[DIV6_SPUV]),
+
+        /* MSTP */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@@ -81,6 +408,16 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
         CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
+        CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
+        CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
+        CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
 
         /* for DT */
         CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
@@ -88,22 +425,40 @@ static struct clk_lookup lookups[] = {
 
 void __init r8a73a4_clock_init(void)
 {
-        void __iomem *cpg_base, *reg;
+        void __iomem *reg;
         int k, ret = 0;
+        u32 ckscr;
+
+        reg = ioremap_nocache(CKSCR, PAGE_SIZE);
+        BUG_ON(!reg);
+        ckscr = ioread32(reg);
+        iounmap(reg);
 
-        /* fix MPCLK to EXTAL2 for now.
-         * this is needed until more detailed clock topology is supported
-         */
-        cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN);
-        BUG_ON(!cpg_base);
-        reg = cpg_base + (MPCKCR - CPG_BASE);
-        iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */
-        iounmap(cpg_base);
+        switch ((ckscr >> 28) & 0x3) {
+        case 0:
+                main_clk.parent = &extal1_clk;
+                break;
+        case 1:
+                main_clk.parent = &extal1_div2_clk;
+                break;
+        case 2:
+                main_clk.parent = &extal2_clk;
+                break;
+        case 3:
+                main_clk.parent = &extal2_div2_clk;
+                break;
+        }
 
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
         if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
+
+        if (!ret)
                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index c0d39aa6de50..7fd32d604e34 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -266,7 +266,7 @@ static struct clk fsiack_clk = {
 static struct clk fsibck_clk = {
 };
 
-struct clk *main_clks[] = {
+static struct clk *main_clks[] = {
         &extalr_clk,
         &extal1_clk,
         &extal2_clk,
@@ -317,7 +317,7 @@ enum {
         DIV4_NR
 };
 
-struct clk div4_clks[DIV4_NR] = {
+static struct clk div4_clks[DIV4_NR] = {
         [DIV4_I]        = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
         [DIV4_ZG]       = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
         [DIV4_B]        = SH_CLK_DIV4(&pllc1_clk, FRQCRA,  8, 0x6fff, CLK_ENABLE_ON_INIT),
@@ -461,7 +461,7 @@ enum {
 
         MSTP329, MSTP328, MSTP323, MSTP320,
         MSTP314, MSTP313, MSTP312,
-        MSTP309,
+        MSTP309, MSTP304,
 
         MSTP416, MSTP415, MSTP407, MSTP406,
 
@@ -499,6 +499,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 13, 0), /* SDHI1 */
         [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 12, 0), /* MMC */
         [MSTP309] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3,  9, 0), /* GEther */
+        [MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_CP],  SMSTPCR3,  4, 0), /* TPU0 */
 
         [MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 16, 0), /* USBHOST */
         [MSTP415] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 15, 0), /* SDHI2 */
@@ -551,6 +552,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_tmu.4",               &mstp_clks[MSTP111]),
         CLKDEV_DEV_ID("sh_tmu.5",               &mstp_clks[MSTP111]),
         CLKDEV_DEV_ID("i2c-sh_mobile.0",        &mstp_clks[MSTP116]),
+        CLKDEV_DEV_ID("fff20000.i2c",           &mstp_clks[MSTP116]),
         CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1",    &mstp_clks[MSTP117]),
         CLKDEV_DEV_ID("sh_tmu.0",               &mstp_clks[MSTP125]),
         CLKDEV_DEV_ID("sh_tmu.1",               &mstp_clks[MSTP125]),
@@ -584,6 +586,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_cmt.10",              &mstp_clks[MSTP329]),
         CLKDEV_DEV_ID("sh_fsi2",                &mstp_clks[MSTP328]),
         CLKDEV_DEV_ID("i2c-sh_mobile.1",        &mstp_clks[MSTP323]),
+        CLKDEV_DEV_ID("e6c20000.i2c",           &mstp_clks[MSTP323]),
         CLKDEV_DEV_ID("renesas_usbhs",          &mstp_clks[MSTP320]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.0",       &mstp_clks[MSTP314]),
         CLKDEV_DEV_ID("e6850000.sdhi",          &mstp_clks[MSTP314]),
@@ -592,6 +595,8 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mmcif",               &mstp_clks[MSTP312]),
         CLKDEV_DEV_ID("e6bd0000.mmcif",         &mstp_clks[MSTP312]),
         CLKDEV_DEV_ID("sh-eth",                 &mstp_clks[MSTP309]),
+        CLKDEV_DEV_ID("e9a00000.sh-eth",        &mstp_clks[MSTP309]),
+        CLKDEV_DEV_ID("renesas_tpu_pwm",        &mstp_clks[MSTP304]),
 
         CLKDEV_DEV_ID("sh_mobile_sdhi.2",       &mstp_clks[MSTP415]),
         CLKDEV_DEV_ID("e6870000.sdhi",          &mstp_clks[MSTP415]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index cd6855290b1f..53798e5037d7 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -23,9 +23,23 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+/*
+ *     MD      MD      MD      MD       PLLA   PLLB    EXTAL   clki    clkz
+ *     19      18      12      11                      (HMz)   (MHz)   (MHz)
+ *----------------------------------------------------------------------------
+ *     1       0       0       0       x21     x21     38.00   800     800
+ *     1       0       0       1       x24     x24     33.33   800     800
+ *     1       0       1       0       x28     x28     28.50   800     800
+ *     1       0       1       1       x32     x32     25.00   800     800
+ *     1       1       0       1       x24     x21     33.33   800     700
+ *     1       1       1       0       x28     x21     28.50   800     600
+ *     1       1       1       1       x32     x24     25.00   800     600
+ */
+
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 
 #define MSTPCR0         IOMEM(0xffc80030)
@@ -37,6 +51,9 @@
 #define MSTPCR4         IOMEM(0xffc80050)
 #define MSTPCR5         IOMEM(0xffc80054)
 #define MSTPCR6         IOMEM(0xffc80058)
+#define MODEMR          0xFFCC0020
+
+#define MD(nr)  BIT(nr)
 
 /* ioremap() through clock mapping mandatory to avoid
  * collision with ARM coherent DMA virtual memory range.
@@ -47,37 +64,94 @@ static struct clk_mapping cpg_mapping = {
         .len    = 0x80,
 };
 
-static struct clk clkp = {
-        .rate   = 62500000, /* FIXME: shortcut */
-        .flags  = CLK_ENABLE_ON_INIT,
+static struct clk extal_clk = {
+        /* .rate will be updated on r8a7778_clock_init() */
         .mapping = &cpg_mapping,
 };
 
+/*
+ * clock ratio of these clock will be updated
+ * on r8a7778_clock_init()
+ */
+SH_FIXED_RATIO_CLK_SET(plla_clk,        extal_clk, 1, 1);
+SH_FIXED_RATIO_CLK_SET(pllb_clk,        extal_clk, 1, 1);
+SH_FIXED_RATIO_CLK_SET(i_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s1_clk,          plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s3_clk,          plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s4_clk,          plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(b_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(out_clk,         plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(p_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(g_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(z_clk,           pllb_clk,  1, 1);
+
 static struct clk *main_clks[] = {
-        &clkp,
+        &extal_clk,
+        &plla_clk,
+        &pllb_clk,
+        &i_clk,
+        &s_clk,
+        &s1_clk,
+        &s3_clk,
+        &s4_clk,
+        &b_clk,
+        &out_clk,
+        &p_clk,
+        &g_clk,
+        &z_clk,
 };
 
 enum {
+        MSTP331,
+        MSTP323, MSTP322, MSTP321,
         MSTP114,
-        MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
+        MSTP100,
+        MSTP030,
+        MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
         MSTP016, MSTP015,
+        MSTP007,
         MSTP_NR };
 
 static struct clk mstp_clks[MSTP_NR] = {
-        [MSTP114] = SH_CLK_MSTP32(&clkp, MSTPCR1, 14, 0), /* Ether */
-        [MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */
-        [MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */
-        [MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */
-        [MSTP023] = SH_CLK_MSTP32(&clkp, MSTPCR0, 23, 0), /* SCIF3 */
-        [MSTP022] = SH_CLK_MSTP32(&clkp, MSTPCR0, 22, 0), /* SCIF4 */
-        [MSTP021] = SH_CLK_MSTP32(&clkp, MSTPCR0, 21, 0), /* SCIF5 */
-        [MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */
-        [MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */
+        [MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */
+        [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
+        [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
+        [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */
+        [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
+        [MSTP100] = SH_CLK_MSTP32(&p_clk, MSTPCR1,  0, 0), /* USB0/1 */
+        [MSTP030] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 30, 0), /* I2C0 */
+        [MSTP029] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 29, 0), /* I2C1 */
+        [MSTP028] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 28, 0), /* I2C2 */
+        [MSTP027] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 27, 0), /* I2C3 */
+        [MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */
+        [MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */
+        [MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */
+        [MSTP023] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 23, 0), /* SCIF3 */
+        [MSTP022] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 22, 0), /* SCIF4 */
+        [MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */
+        [MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */
+        [MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */
+        [MSTP007] = SH_CLK_MSTP32(&p_clk, MSTPCR0,  7, 0), /* HSPI */
 };
 
 static struct clk_lookup lookups[] = {
+        /* main */
+        CLKDEV_CON_ID("shyway_clk",     &s_clk),
+        CLKDEV_CON_ID("peripheral_clk", &p_clk),
+
         /* MSTP32 clocks */
+        CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
         CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
+        CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
+        CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
+        CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
+        CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
+        CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
+        CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
@@ -86,12 +160,93 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
         CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
         CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */
+        CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
+        CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
+        CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
 };
 
 void __init r8a7778_clock_init(void)
 {
+        void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+        u32 mode;
         int k, ret = 0;
 
+        BUG_ON(!modemr);
+        mode = ioread32(modemr);
+        iounmap(modemr);
+
+        switch (mode & (MD(19) | MD(18) | MD(12) | MD(11))) {
+        case MD(19):
+                extal_clk.rate = 38000000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       21, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       21, 1);
+                break;
+        case MD(19) | MD(11):
+                extal_clk.rate = 33333333;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       24, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       24, 1);
+                break;
+        case MD(19) | MD(12):
+                extal_clk.rate = 28500000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       28, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       28, 1);
+                break;
+        case MD(19) | MD(12) | MD(11):
+                extal_clk.rate = 25000000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       32, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       32, 1);
+                break;
+        case MD(19) | MD(18) | MD(11):
+                extal_clk.rate = 33333333;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       24, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       21, 1);
+                break;
+        case MD(19) | MD(18) | MD(12):
+                extal_clk.rate = 28500000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       28, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       21, 1);
+                break;
+        case MD(19) | MD(18) | MD(12) | MD(11):
+                extal_clk.rate = 25000000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       32, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       24, 1);
+                break;
+        default:
+                BUG();
+        }
+
+        if (mode & MD(1)) {
+                SH_CLK_SET_RATIO(&i_clk_ratio,  1, 1);
+                SH_CLK_SET_RATIO(&s_clk_ratio,  1, 3);
+                SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 6);
+                SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
+                SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
+                SH_CLK_SET_RATIO(&p_clk_ratio,  1, 12);
+                SH_CLK_SET_RATIO(&g_clk_ratio,  1, 12);
+                if (mode & MD(2)) {
+                        SH_CLK_SET_RATIO(&b_clk_ratio,          1, 18);
+                        SH_CLK_SET_RATIO(&out_clk_ratio,        1, 18);
+                } else {
+                        SH_CLK_SET_RATIO(&b_clk_ratio,          1, 12);
+                        SH_CLK_SET_RATIO(&out_clk_ratio,        1, 12);
+                }
+        } else {
+                SH_CLK_SET_RATIO(&i_clk_ratio,  1, 1);
+                SH_CLK_SET_RATIO(&s_clk_ratio,  1, 4);
+                SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 8);
+                SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
+                SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
+                SH_CLK_SET_RATIO(&p_clk_ratio,  1, 16);
+                SH_CLK_SET_RATIO(&g_clk_ratio,  1, 12);
+                if (mode & MD(2)) {
+                        SH_CLK_SET_RATIO(&b_clk_ratio,          1, 16);
+                        SH_CLK_SET_RATIO(&out_clk_ratio,        1, 16);
+                } else {
+                        SH_CLK_SET_RATIO(&b_clk_ratio,          1, 12);
+                        SH_CLK_SET_RATIO(&out_clk_ratio,        1, 12);
+                }
+        }
+
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 31d5cd4d9787..9daeb8c37483 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -112,7 +112,7 @@ static struct clk *main_clks[] = {
 };
 
 enum { MSTP323, MSTP322, MSTP321, MSTP320,
-        MSTP115, MSTP114,
+        MSTP116, MSTP115, MSTP114,
         MSTP103, MSTP101, MSTP100,
         MSTP030,
         MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
@@ -125,6 +125,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
         [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
         [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
+        [MSTP116] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 16, 0), /* PCIe */
         [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */
         [MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */
         [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1,  3, 0), /* DU */
@@ -161,6 +162,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("peripheral_clk", &clkp_clk),
 
         /* MSTP32 clocks */
+        CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */
         CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
         CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
         CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index bad9bf2e34d6..5d71313df52d 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -22,48 +22,228 @@
 #include <linux/kernel.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 
+/*
+ *   MD         EXTAL           PLL0    PLL1    PLL3
+ * 14 13 19     (MHz)           *1      *1
+ *---------------------------------------------------
+ * 0  0  0      15 x 1          x172/2  x208/2  x106
+ * 0  0  1      15 x 1          x172/2  x208/2  x88
+ * 0  1  0      20 x 1          x130/2  x156/2  x80
+ * 0  1  1      20 x 1          x130/2  x156/2  x66
+ * 1  0  0      26 / 2          x200/2  x240/2  x122
+ * 1  0  1      26 / 2          x200/2  x240/2  x102
+ * 1  1  0      30 / 2          x172/2  x208/2  x106
+ * 1  1  1      30 / 2          x172/2  x208/2  x88
+ *
+ * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
+ *      see "p1 / 2" on R8A7790_CLOCK_ROOT() below
+ */
+
+#define MD(nr)  (1 << nr)
+
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x1000
 
 #define SMSTPCR2 0xe6150138
+#define SMSTPCR3 0xe615013c
 #define SMSTPCR7 0xe615014c
 
+#define MODEMR          0xE6160060
+#define SDCKCR          0xE6150074
+#define SD2CKCR         0xE6150078
+#define SD3CKCR         0xE615007C
+#define MMC0CKCR        0xE6150240
+#define MMC1CKCR        0xE6150244
+#define SSPCKCR         0xE6150248
+#define SSPRSCKCR       0xE615024C
+
 static struct clk_mapping cpg_mapping = {
         .phys   = CPG_BASE,
         .len    = CPG_LEN,
 };
 
-static struct clk p_clk = {
-        .rate   = 65000000, /* shortcut for now */
+static struct clk extal_clk = {
+        /* .rate will be updated on r8a7790_clock_init() */
         .mapping        = &cpg_mapping,
 };
 
-static struct clk mp_clk = {
-        .rate   = 52000000,  /* shortcut for now */
-        .mapping        = &cpg_mapping,
+static struct sh_clk_ops followparent_clk_ops = {
+        .recalc = followparent_recalc,
+};
+
+static struct clk main_clk = {
+        /* .parent will be set r8a73a4_clock_init */
+        .ops    = &followparent_clk_ops,
 };
 
+/*
+ * clock ratio of these clock will be updated
+ * on r8a7790_clock_init()
+ */
+SH_FIXED_RATIO_CLK_SET(pll1_clk,                main_clk,       1, 1);
+SH_FIXED_RATIO_CLK_SET(pll3_clk,                main_clk,       1, 1);
+SH_FIXED_RATIO_CLK_SET(lb_clk,                  pll1_clk,       1, 1);
+SH_FIXED_RATIO_CLK_SET(qspi_clk,                pll1_clk,       1, 1);
+
+/* fixed ratio clock */
+SH_FIXED_RATIO_CLK_SET(extal_div2_clk,          extal_clk,      1, 2);
+SH_FIXED_RATIO_CLK_SET(cp_clk,                  extal_clk,      1, 2);
+
+SH_FIXED_RATIO_CLK_SET(pll1_div2_clk,           pll1_clk,       1, 2);
+SH_FIXED_RATIO_CLK_SET(zg_clk,                  pll1_clk,       1, 3);
+SH_FIXED_RATIO_CLK_SET(zx_clk,                  pll1_clk,       1, 3);
+SH_FIXED_RATIO_CLK_SET(zs_clk,                  pll1_clk,       1, 6);
+SH_FIXED_RATIO_CLK_SET(hp_clk,                  pll1_clk,       1, 12);
+SH_FIXED_RATIO_CLK_SET(i_clk,                   pll1_clk,       1, 2);
+SH_FIXED_RATIO_CLK_SET(b_clk,                   pll1_clk,       1, 12);
+SH_FIXED_RATIO_CLK_SET(p_clk,                   pll1_clk,       1, 24);
+SH_FIXED_RATIO_CLK_SET(cl_clk,                  pll1_clk,       1, 48);
+SH_FIXED_RATIO_CLK_SET(m2_clk,                  pll1_clk,       1, 8);
+SH_FIXED_RATIO_CLK_SET(imp_clk,                 pll1_clk,       1, 4);
+SH_FIXED_RATIO_CLK_SET(rclk_clk,                pll1_clk,       1, (48 * 1024));
+SH_FIXED_RATIO_CLK_SET(oscclk_clk,              pll1_clk,       1, (12 * 1024));
+
+SH_FIXED_RATIO_CLK_SET(zb3_clk,                 pll3_clk,       1, 4);
+SH_FIXED_RATIO_CLK_SET(zb3d2_clk,               pll3_clk,       1, 8);
+SH_FIXED_RATIO_CLK_SET(ddr_clk,                 pll3_clk,       1, 8);
+SH_FIXED_RATIO_CLK_SET(mp_clk,                  pll1_div2_clk,  1, 15);
+
 static struct clk *main_clks[] = {
+        &extal_clk,
+        &extal_div2_clk,
+        &main_clk,
+        &pll1_clk,
+        &pll1_div2_clk,
+        &pll3_clk,
+        &lb_clk,
+        &qspi_clk,
+        &zg_clk,
+        &zx_clk,
+        &zs_clk,
+        &hp_clk,
+        &i_clk,
+        &b_clk,
         &p_clk,
+        &cl_clk,
+        &m2_clk,
+        &imp_clk,
+        &rclk_clk,
+        &oscclk_clk,
+        &zb3_clk,
+        &zb3d2_clk,
+        &ddr_clk,
         &mp_clk,
+        &cp_clk,
+};
+
+/* SDHI (DIV4) clock */
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
+
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = divisors,
+        .nr_divisors = ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
+enum {
+        DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
+};
+
+static struct clk div4_clks[DIV4_NR] = {
+        [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
+        [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
+        [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
+};
+
+/* DIV6 clocks */
+enum {
+        DIV6_SD2, DIV6_SD3,
+        DIV6_MMC0, DIV6_MMC1,
+        DIV6_SSP, DIV6_SSPRS,
+        DIV6_NR
+};
+
+static struct clk div6_clks[DIV6_NR] = {
+        [DIV6_SD2]      = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
+        [DIV6_SD3]      = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
+        [DIV6_MMC0]     = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
+        [DIV6_MMC1]     = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
+        [DIV6_SSP]      = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
+        [DIV6_SSPRS]    = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
+};
+
+/* MSTP */
+enum {
+        MSTP721, MSTP720,
+        MSTP717, MSTP716,
+        MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
+        MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
+        MSTP_NR
 };
 
-enum { MSTP721, MSTP720,
-        MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
 static struct clk mstp_clks[MSTP_NR] = {
         [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
         [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
+        [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */
+        [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */
+        [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */
+        [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SD2], SMSTPCR3, 12, 0), /* SDHI2 */
+        [MSTP311] = SH_CLK_MSTP32(&div6_clks[DIV6_SD3], SMSTPCR3, 11, 0), /* SDHI3 */
+        [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, 0), /* MMC1 */
+        [MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */
         [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
         [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
         [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
         [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
         [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
         [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
+        [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
+        [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
 };
 
 static struct clk_lookup lookups[] = {
+
+        /* main clocks */
+        CLKDEV_CON_ID("extal",          &extal_clk),
+        CLKDEV_CON_ID("extal_div2",     &extal_div2_clk),
+        CLKDEV_CON_ID("main",           &main_clk),
+        CLKDEV_CON_ID("pll1",           &pll1_clk),
+        CLKDEV_CON_ID("pll1_div2",      &pll1_div2_clk),
+        CLKDEV_CON_ID("pll3",           &pll3_clk),
+        CLKDEV_CON_ID("zg",             &zg_clk),
+        CLKDEV_CON_ID("zx",             &zx_clk),
+        CLKDEV_CON_ID("zs",             &zs_clk),
+        CLKDEV_CON_ID("hp",             &hp_clk),
+        CLKDEV_CON_ID("i",              &i_clk),
+        CLKDEV_CON_ID("b",              &b_clk),
+        CLKDEV_CON_ID("lb",             &lb_clk),
+        CLKDEV_CON_ID("p",              &p_clk),
+        CLKDEV_CON_ID("cl",             &cl_clk),
+        CLKDEV_CON_ID("m2",             &m2_clk),
+        CLKDEV_CON_ID("imp",            &imp_clk),
+        CLKDEV_CON_ID("rclk",           &rclk_clk),
+        CLKDEV_CON_ID("oscclk",         &oscclk_clk),
+        CLKDEV_CON_ID("zb3",            &zb3_clk),
+        CLKDEV_CON_ID("zb3d2",          &zb3d2_clk),
+        CLKDEV_CON_ID("ddr",            &ddr_clk),
+        CLKDEV_CON_ID("mp",             &mp_clk),
+        CLKDEV_CON_ID("qspi",           &qspi_clk),
+        CLKDEV_CON_ID("cp",             &cp_clk),
+
+        /* DIV4 */
+        CLKDEV_CON_ID("sdh",            &div4_clks[DIV4_SDH]),
+
+        /* DIV6 */
+        CLKDEV_CON_ID("ssp",            &div6_clks[DIV6_SSP]),
+        CLKDEV_CON_ID("ssprs",          &div6_clks[DIV6_SSPRS]),
+
+        /* MSTP */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@@ -72,16 +252,77 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
         CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
         CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
+        CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
+        CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
+        CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
+        CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
+        CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("ee160000.sdhi", &mstp_clks[MSTP311]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
+        CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
+        CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
 };
 
+#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)              \
+        extal_clk.rate  = e * 1000 * 1000;                      \
+        main_clk.parent = m;                                    \
+        SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1);           \
+        if (mode & MD(19))                                      \
+                SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1);      \
+        else                                                    \
+                SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
+
+
 void __init r8a7790_clock_init(void)
 {
+        void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+        u32 mode;
         int k, ret = 0;
 
+        BUG_ON(!modemr);
+        mode = ioread32(modemr);
+        iounmap(modemr);
+
+        switch (mode & (MD(14) | MD(13))) {
+        case 0:
+                R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
+                break;
+        case MD(13):
+                R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
+                break;
+        case MD(14):
+                R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
+                break;
+        case MD(13) | MD(14):
+                R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
+                break;
+        }
+
+        if (mode & (MD(18)))
+                SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
+        else
+                SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);
+
+        if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
+                SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
+        else
+                SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
+
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
         if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+
+        if (!ret)
                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 784fbaa4cc55..d9fd0336b910 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -228,6 +228,11 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
 
 static struct clk div4_clks[DIV4_NR] = {
         [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
+        /*
+         * ZG clock is dividing PLL0 frequency to supply SGX. Make sure not to
+         * exceed maximum frequencies of 201.5MHz for VDD_DVFS=1.175 and
+         * 239.2MHz for VDD_DVFS=1.315V.
+         */
         [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
         [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
         [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
@@ -252,6 +257,101 @@ static struct clk twd_clk = {
         .ops = &twd_clk_ops,
 };
 
+static struct sh_clk_ops zclk_ops, kicker_ops;
+static const struct sh_clk_ops *div4_clk_ops;
+
+static int zclk_set_rate(struct clk *clk, unsigned long rate)
+{
+        int ret;
+
+        if (!clk->parent || !__clk_get(clk->parent))
+                return -ENODEV;
+
+        if (readl(FRQCRB) & (1 << 31))
+                return -EBUSY;
+
+        if (rate == clk_get_rate(clk->parent)) {
+                /* 1:1 - switch off divider */
+                __raw_writel(__raw_readl(FRQCRB) & ~(1 << 28), FRQCRB);
+                /* nullify the divider to prepare for the next time */
+                ret = div4_clk_ops->set_rate(clk, rate / 2);
+                if (!ret)
+                        ret = frqcr_kick();
+                if (ret > 0)
+                        ret = 0;
+        } else {
+                /* Enable the divider */
+                __raw_writel(__raw_readl(FRQCRB) | (1 << 28), FRQCRB);
+
+                ret = frqcr_kick();
+                if (ret >= 0)
+                        /*
+                         * set the divider - call the DIV4 method, it will kick
+                         * FRQCRB too
+                         */
+                        ret = div4_clk_ops->set_rate(clk, rate);
+                if (ret < 0)
+                        goto esetrate;
+        }
+
+esetrate:
+        __clk_put(clk->parent);
+        return ret;
+}
+
+static long zclk_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long div_freq = div4_clk_ops->round_rate(clk, rate),
+                parent_freq = clk_get_rate(clk->parent);
+
+        if (rate > div_freq && abs(parent_freq - rate) < rate - div_freq)
+                return parent_freq;
+
+        return div_freq;
+}
+
+static unsigned long zclk_recalc(struct clk *clk)
+{
+        /*
+         * Must recalculate frequencies in case PLL0 has been changed, even if
+         * the divisor is unused ATM!
+         */
+        unsigned long div_freq = div4_clk_ops->recalc(clk);
+
+        if (__raw_readl(FRQCRB) & (1 << 28))
+                return div_freq;
+
+        return clk_get_rate(clk->parent);
+}
+
+static int kicker_set_rate(struct clk *clk, unsigned long rate)
+{
+        if (__raw_readl(FRQCRB) & (1 << 31))
+                return -EBUSY;
+
+        return div4_clk_ops->set_rate(clk, rate);
+}
+
+static void div4_clk_extend(void)
+{
+        int i;
+
+        div4_clk_ops = div4_clks[0].ops;
+
+        /* Add a kicker-busy check before changing the rate */
+        kicker_ops = *div4_clk_ops;
+        /* We extend the DIV4 clock with a 1:1 pass-through case */
+        zclk_ops = *div4_clk_ops;
+
+        kicker_ops.set_rate = kicker_set_rate;
+        zclk_ops.set_rate = zclk_set_rate;
+        zclk_ops.round_rate = zclk_round_rate;
+        zclk_ops.recalc = zclk_recalc;
+
+        for (i = 0; i < DIV4_NR; i++)
+                div4_clks[i].ops = i == DIV4_Z ? &zclk_ops : &kicker_ops;
+}
+
 enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
         DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
         DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
@@ -450,7 +550,7 @@ static struct clk *late_main_clks[] = {
 };
 
 enum { MSTP001,
-        MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
+        MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP112, MSTP100,
         MSTP219, MSTP218, MSTP217,
         MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
         MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322,
@@ -471,6 +571,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
         [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */
         [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
+        [MSTP112] = MSTP(&div4_clks[DIV4_ZG], SMSTPCR1, 12, 0), /* SGX */
         [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
         [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
         [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */
@@ -513,6 +614,9 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("r_clk", &r_clk),
         CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */
 
+        /* DIV4 clocks */
+        CLKDEV_DEV_ID("cpufreq-cpu0", &div4_clks[DIV4_Z]),
+
         /* DIV6 clocks */
         CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
         CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
@@ -604,8 +708,11 @@ void __init sh73a0_clock_init(void)
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
-        if (!ret)
+        if (!ret) {
                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+                if (!ret)
+                        div4_clk_extend();
+        }
 
         if (!ret)
                 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h
index 76ac61292e48..03e56074928c 100644
--- a/arch/arm/mach-shmobile/include/mach/clock.h
+++ b/arch/arm/mach-shmobile/include/mach/clock.h
@@ -24,16 +24,16 @@ struct clk name = {			\
 }
 
 #define SH_FIXED_RATIO_CLK(name, p, r)          \
-static SH_FIXED_RATIO_CLKg(name, p, r);
+static SH_FIXED_RATIO_CLKg(name, p, r)
 
 #define SH_FIXED_RATIO_CLK_SET(name, p, m, d)   \
         SH_CLK_RATIO(name, m, d);               \
-        SH_FIXED_RATIO_CLK(name, p, name);
+        SH_FIXED_RATIO_CLK(name, p, name)
 
 #define SH_CLK_SET_RATIO(p, m, d)       \
-{                       \
+do {                    \
         (p)->mul = m;   \
         (p)->div = d;   \
-}
+} while (0)
 
 #endif
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index b2074e2acb15..d241bfd6926d 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -16,4 +16,9 @@
 #define IRQPIN_BASE             2000
 #define irq_pin(nr)             ((nr) + IRQPIN_BASE)
 
+/* GPIO IRQ */
+#define _GPIO_IRQ_BASE          2500
+#define GPIO_IRQ_BASE(x)        (_GPIO_IRQ_BASE + (32 * x))
+#define GPIO_IRQ(x, y)          (_GPIO_IRQ_BASE + (32 * x) + y)
+
 #endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index abdc4d4efa28..9c9a66ccaf6f 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -28,494 +28,6 @@
 #define MD_CK1  (1 << 1)
 #define MD_CK0  (1 << 0)
 
-/*
- * Pin Function Controller:
- *      GPIO_FN_xx - GPIO used to select pin function
- *      GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
- */
-enum {
-        /* PORT */
-        GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
-        GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
-
-        GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
-        GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
-
-        GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
-        GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
-
-        GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
-        GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
-
-        GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
-        GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
-
-        GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
-        GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
-
-        GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
-        GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
-
-        GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
-        GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
-
-        GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
-        GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
-
-        GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
-        GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
-
-        GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
-        GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
-
-        GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
-        GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
-
-        GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
-        GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
-
-        GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
-        GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
-
-        GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
-        GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
-
-        GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
-        GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
-
-        GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
-        GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
-
-        GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
-        GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
-
-        GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
-        GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
-
-        GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
-        GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
-
-        GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
-        GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
-
-        GPIO_PORT210, GPIO_PORT211,
-
-        /* IRQ */
-        GPIO_FN_IRQ0_PORT2,     GPIO_FN_IRQ0_PORT13,
-        GPIO_FN_IRQ1,
-        GPIO_FN_IRQ2_PORT11,    GPIO_FN_IRQ2_PORT12,
-        GPIO_FN_IRQ3_PORT10,    GPIO_FN_IRQ3_PORT14,
-        GPIO_FN_IRQ4_PORT15,    GPIO_FN_IRQ4_PORT172,
-        GPIO_FN_IRQ5_PORT0,     GPIO_FN_IRQ5_PORT1,
-        GPIO_FN_IRQ6_PORT121,   GPIO_FN_IRQ6_PORT173,
-        GPIO_FN_IRQ7_PORT120,   GPIO_FN_IRQ7_PORT209,
-        GPIO_FN_IRQ8,
-        GPIO_FN_IRQ9_PORT118,   GPIO_FN_IRQ9_PORT210,
-        GPIO_FN_IRQ10,
-        GPIO_FN_IRQ11,
-        GPIO_FN_IRQ12_PORT42,   GPIO_FN_IRQ12_PORT97,
-        GPIO_FN_IRQ13_PORT64,   GPIO_FN_IRQ13_PORT98,
-        GPIO_FN_IRQ14_PORT63,   GPIO_FN_IRQ14_PORT99,
-        GPIO_FN_IRQ15_PORT62,   GPIO_FN_IRQ15_PORT100,
-        GPIO_FN_IRQ16_PORT68,   GPIO_FN_IRQ16_PORT211,
-        GPIO_FN_IRQ17,
-        GPIO_FN_IRQ18,
-        GPIO_FN_IRQ19,
-        GPIO_FN_IRQ20,
-        GPIO_FN_IRQ21,
-        GPIO_FN_IRQ22,
-        GPIO_FN_IRQ23,
-        GPIO_FN_IRQ24,
-        GPIO_FN_IRQ25,
-        GPIO_FN_IRQ26_PORT58,   GPIO_FN_IRQ26_PORT81,
-        GPIO_FN_IRQ27_PORT57,   GPIO_FN_IRQ27_PORT168,
-        GPIO_FN_IRQ28_PORT56,   GPIO_FN_IRQ28_PORT169,
-        GPIO_FN_IRQ29_PORT50,   GPIO_FN_IRQ29_PORT170,
-        GPIO_FN_IRQ30_PORT49,   GPIO_FN_IRQ30_PORT171,
-        GPIO_FN_IRQ31_PORT41,   GPIO_FN_IRQ31_PORT167,
-
-        /* Function */
-
-        /* DBGT */
-        GPIO_FN_DBGMDT2,        GPIO_FN_DBGMDT1,        GPIO_FN_DBGMDT0,
-        GPIO_FN_DBGMD10,        GPIO_FN_DBGMD11,        GPIO_FN_DBGMD20,
-        GPIO_FN_DBGMD21,
-
-        /* FSI-A */
-        GPIO_FN_FSIAISLD_PORT0,         /* FSIAISLD Port 0/5 */
-        GPIO_FN_FSIAISLD_PORT5,
-        GPIO_FN_FSIASPDIF_PORT9,        /* FSIASPDIF Port 9/18 */
-        GPIO_FN_FSIASPDIF_PORT18,
-        GPIO_FN_FSIAOSLD1,      GPIO_FN_FSIAOSLD2,
-        GPIO_FN_FSIAOLR,        GPIO_FN_FSIAOBT,
-        GPIO_FN_FSIAOSLD,       GPIO_FN_FSIAOMC,
-        GPIO_FN_FSIACK,         GPIO_FN_FSIAILR,
-        GPIO_FN_FSIAIBT,
-
-        /* FSI-B */
-        GPIO_FN_FSIBCK,
-
-        /* FMSI */
-        GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
-        GPIO_FN_FMSISLD_PORT6,
-        GPIO_FN_FMSIILR,        GPIO_FN_FMSIIBT,
-        GPIO_FN_FMSIOLR,        GPIO_FN_FMSIOBT,
-        GPIO_FN_FMSICK,         GPIO_FN_FMSOILR,
-        GPIO_FN_FMSOIBT,        GPIO_FN_FMSOOLR,
-        GPIO_FN_FMSOOBT,        GPIO_FN_FMSOSLD,
-        GPIO_FN_FMSOCK,
-
-        /* SCIFA0 */
-        GPIO_FN_SCIFA0_SCK,     GPIO_FN_SCIFA0_CTS,
-        GPIO_FN_SCIFA0_RTS,     GPIO_FN_SCIFA0_RXD,
-        GPIO_FN_SCIFA0_TXD,
-
-        /* SCIFA1 */
-        GPIO_FN_SCIFA1_CTS,     GPIO_FN_SCIFA1_SCK,
-        GPIO_FN_SCIFA1_RXD,     GPIO_FN_SCIFA1_TXD,
-        GPIO_FN_SCIFA1_RTS,
-
-        /* SCIFA2 */
-        GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
-        GPIO_FN_SCIFA2_SCK_PORT199,
-        GPIO_FN_SCIFA2_RXD,     GPIO_FN_SCIFA2_TXD,
-        GPIO_FN_SCIFA2_CTS,     GPIO_FN_SCIFA2_RTS,
-
-        /* SCIFA3 */
-        GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
-        GPIO_FN_SCIFA3_SCK_PORT116,
-        GPIO_FN_SCIFA3_CTS_PORT117,
-        GPIO_FN_SCIFA3_RXD_PORT174,
-        GPIO_FN_SCIFA3_TXD_PORT175,
-
-        GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
-        GPIO_FN_SCIFA3_SCK_PORT158,
-        GPIO_FN_SCIFA3_CTS_PORT162,
-        GPIO_FN_SCIFA3_RXD_PORT159,
-        GPIO_FN_SCIFA3_TXD_PORT160,
-
-        /* SCIFA4 */
-        GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
-        GPIO_FN_SCIFA4_TXD_PORT13,
-
-        GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
-        GPIO_FN_SCIFA4_TXD_PORT203,
-
-        GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
-        GPIO_FN_SCIFA4_TXD_PORT93,
-
-        GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
-        GPIO_FN_SCIFA4_SCK_PORT205,
-
-        /* SCIFA5 */
-        GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
-        GPIO_FN_SCIFA5_RXD_PORT10,
-
-        GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
-        GPIO_FN_SCIFA5_TXD_PORT208,
-
-        GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
-        GPIO_FN_SCIFA5_RXD_PORT92,
-
-        GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
-        GPIO_FN_SCIFA5_SCK_PORT206,
-
-        /* SCIFA6 */
-        GPIO_FN_SCIFA6_SCK,     GPIO_FN_SCIFA6_RXD,     GPIO_FN_SCIFA6_TXD,
-
-        /* SCIFA7 */
-        GPIO_FN_SCIFA7_TXD,     GPIO_FN_SCIFA7_RXD,
-
-        /* SCIFAB */
-        GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
-        GPIO_FN_SCIFB_RXD_PORT191,
-        GPIO_FN_SCIFB_TXD_PORT192,
-        GPIO_FN_SCIFB_RTS_PORT186,
-        GPIO_FN_SCIFB_CTS_PORT187,
-
-        GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
-        GPIO_FN_SCIFB_RXD_PORT3,
-        GPIO_FN_SCIFB_TXD_PORT4,
-        GPIO_FN_SCIFB_RTS_PORT172,
-        GPIO_FN_SCIFB_CTS_PORT173,
-
-        /* LCD0 */
-        GPIO_FN_LCDC0_SELECT,
-
-        /* LCD1 */
-        GPIO_FN_LCDC1_SELECT,
-
-        /* RSPI */
-        GPIO_FN_RSPI_SSL0_A,    GPIO_FN_RSPI_SSL1_A,
-        GPIO_FN_RSPI_SSL2_A,    GPIO_FN_RSPI_SSL3_A,
-        GPIO_FN_RSPI_MOSI_A,    GPIO_FN_RSPI_MISO_A,
-        GPIO_FN_RSPI_CK_A,
-
-        /* VIO CKO */
-        GPIO_FN_VIO_CKO1,
-        GPIO_FN_VIO_CKO2,
-        GPIO_FN_VIO_CKO_1,
-        GPIO_FN_VIO_CKO,
-
-        /* VIO0 */
-        GPIO_FN_VIO0_D0,        GPIO_FN_VIO0_D1,        GPIO_FN_VIO0_D2,
-        GPIO_FN_VIO0_D3,        GPIO_FN_VIO0_D4,        GPIO_FN_VIO0_D5,
-        GPIO_FN_VIO0_D6,        GPIO_FN_VIO0_D7,        GPIO_FN_VIO0_D8,
-        GPIO_FN_VIO0_D9,        GPIO_FN_VIO0_D10,       GPIO_FN_VIO0_D11,
-        GPIO_FN_VIO0_D12,       GPIO_FN_VIO0_VD,        GPIO_FN_VIO0_HD,
-        GPIO_FN_VIO0_CLK,       GPIO_FN_VIO0_FIELD,
-
-        GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
-        GPIO_FN_VIO0_D14_PORT25,
-        GPIO_FN_VIO0_D15_PORT24,
-
-        GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
-        GPIO_FN_VIO0_D14_PORT95,
-        GPIO_FN_VIO0_D15_PORT96,
-
-        /* VIO1 */
-        GPIO_FN_VIO1_D0,        GPIO_FN_VIO1_D1,        GPIO_FN_VIO1_D2,
-        GPIO_FN_VIO1_D3,        GPIO_FN_VIO1_D4,        GPIO_FN_VIO1_D5,
-        GPIO_FN_VIO1_D6,        GPIO_FN_VIO1_D7,        GPIO_FN_VIO1_VD,
-        GPIO_FN_VIO1_HD,        GPIO_FN_VIO1_CLK,       GPIO_FN_VIO1_FIELD,
-
-        /* TPU0 */
-        GPIO_FN_TPU0TO0,        GPIO_FN_TPU0TO1,
-        GPIO_FN_TPU0TO3,
-        GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
-        GPIO_FN_TPU0TO2_PORT202,
-
-        /* SSP1 0 */
-        GPIO_FN_STP0_IPD0,      GPIO_FN_STP0_IPD1,      GPIO_FN_STP0_IPD2,
-        GPIO_FN_STP0_IPD3,      GPIO_FN_STP0_IPD4,      GPIO_FN_STP0_IPD5,
-        GPIO_FN_STP0_IPD6,      GPIO_FN_STP0_IPD7,      GPIO_FN_STP0_IPEN,
-        GPIO_FN_STP0_IPCLK,     GPIO_FN_STP0_IPSYNC,
-
-        /* SSP1 1 */
-        GPIO_FN_STP1_IPD1,      GPIO_FN_STP1_IPD2,      GPIO_FN_STP1_IPD3,
-        GPIO_FN_STP1_IPD4,      GPIO_FN_STP1_IPD5,      GPIO_FN_STP1_IPD6,
-        GPIO_FN_STP1_IPD7,      GPIO_FN_STP1_IPCLK,     GPIO_FN_STP1_IPSYNC,
-
-        GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
-        GPIO_FN_STP1_IPEN_PORT187,
-
-        GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
-        GPIO_FN_STP1_IPEN_PORT193,
-
-        /* SIM */
-        GPIO_FN_SIM_RST,        GPIO_FN_SIM_CLK,
-        GPIO_FN_SIM_D_PORT22, /* SIM_D  Port 22/199 */
-        GPIO_FN_SIM_D_PORT199,
-
-        /* MSIOF2 */
-        GPIO_FN_MSIOF2_TXD,     GPIO_FN_MSIOF2_RXD,     GPIO_FN_MSIOF2_TSCK,
-        GPIO_FN_MSIOF2_SS2,     GPIO_FN_MSIOF2_TSYNC,   GPIO_FN_MSIOF2_SS1,
-        GPIO_FN_MSIOF2_MCK1,    GPIO_FN_MSIOF2_MCK0,    GPIO_FN_MSIOF2_RSYNC,
-        GPIO_FN_MSIOF2_RSCK,
-
-        /* KEYSC */
-        GPIO_FN_KEYIN4,         GPIO_FN_KEYIN5,
-        GPIO_FN_KEYIN6,         GPIO_FN_KEYIN7,
-        GPIO_FN_KEYOUT0,        GPIO_FN_KEYOUT1,        GPIO_FN_KEYOUT2,
-        GPIO_FN_KEYOUT3,        GPIO_FN_KEYOUT4,        GPIO_FN_KEYOUT5,
-        GPIO_FN_KEYOUT6,        GPIO_FN_KEYOUT7,
-
-        GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
-        GPIO_FN_KEYIN1_PORT44,
-        GPIO_FN_KEYIN2_PORT45,
-        GPIO_FN_KEYIN3_PORT46,
-
-        GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
-        GPIO_FN_KEYIN1_PORT57,
-        GPIO_FN_KEYIN2_PORT56,
-        GPIO_FN_KEYIN3_PORT55,
-
-        /* VOU */
-        GPIO_FN_DV_D0,  GPIO_FN_DV_D1,  GPIO_FN_DV_D2,  GPIO_FN_DV_D3,
-        GPIO_FN_DV_D4,  GPIO_FN_DV_D5,  GPIO_FN_DV_D6,  GPIO_FN_DV_D7,
-        GPIO_FN_DV_D8,  GPIO_FN_DV_D9,  GPIO_FN_DV_D10, GPIO_FN_DV_D11,
-        GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15,
-        GPIO_FN_DV_CLK,
-        GPIO_FN_DV_VSYNC,
-        GPIO_FN_DV_HSYNC,
-
-        /* MEMC */
-        GPIO_FN_MEMC_AD0,       GPIO_FN_MEMC_AD1,       GPIO_FN_MEMC_AD2,
-        GPIO_FN_MEMC_AD3,       GPIO_FN_MEMC_AD4,       GPIO_FN_MEMC_AD5,
-        GPIO_FN_MEMC_AD6,       GPIO_FN_MEMC_AD7,       GPIO_FN_MEMC_AD8,
-        GPIO_FN_MEMC_AD9,       GPIO_FN_MEMC_AD10,      GPIO_FN_MEMC_AD11,
-        GPIO_FN_MEMC_AD12,      GPIO_FN_MEMC_AD13,      GPIO_FN_MEMC_AD14,
-        GPIO_FN_MEMC_AD15,      GPIO_FN_MEMC_CS0,       GPIO_FN_MEMC_INT,
-        GPIO_FN_MEMC_NWE,       GPIO_FN_MEMC_NOE,
-
-        GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
-        GPIO_FN_MEMC_ADV,
-        GPIO_FN_MEMC_WAIT,
-        GPIO_FN_MEMC_BUSCLK,
-
-        GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
-        GPIO_FN_MEMC_DREQ0,
-        GPIO_FN_MEMC_DREQ1,
-        GPIO_FN_MEMC_A0,
-
-        /* MSIOF0 */
-        GPIO_FN_MSIOF0_SS1,     GPIO_FN_MSIOF0_SS2,
-        GPIO_FN_MSIOF0_RXD,     GPIO_FN_MSIOF0_TXD,
-        GPIO_FN_MSIOF0_MCK0,    GPIO_FN_MSIOF0_MCK1,
-        GPIO_FN_MSIOF0_RSYNC,   GPIO_FN_MSIOF0_RSCK,
-        GPIO_FN_MSIOF0_TSCK,    GPIO_FN_MSIOF0_TSYNC,
-
-        /* MSIOF1 */
-        GPIO_FN_MSIOF1_RSCK,    GPIO_FN_MSIOF1_RSYNC,
-        GPIO_FN_MSIOF1_MCK0,    GPIO_FN_MSIOF1_MCK1,
-
-        GPIO_FN_MSIOF1_SS2_PORT116,     GPIO_FN_MSIOF1_SS1_PORT117,
-        GPIO_FN_MSIOF1_RXD_PORT118,     GPIO_FN_MSIOF1_TXD_PORT119,
-        GPIO_FN_MSIOF1_TSYNC_PORT120,
-        GPIO_FN_MSIOF1_TSCK_PORT121,    /* MSEL4CR_10_0 */
-
-        GPIO_FN_MSIOF1_SS1_PORT67,      GPIO_FN_MSIOF1_TSCK_PORT72,
-        GPIO_FN_MSIOF1_TSYNC_PORT73,    GPIO_FN_MSIOF1_TXD_PORT74,
-        GPIO_FN_MSIOF1_RXD_PORT75,
-        GPIO_FN_MSIOF1_SS2_PORT202,     /* MSEL4CR_10_1 */
-
-        /* GPIO */
-        GPIO_FN_GPO0,   GPIO_FN_GPI0,
-        GPIO_FN_GPO1,   GPIO_FN_GPI1,
-
-        /* USB0 */
-        GPIO_FN_USB0_OCI,       GPIO_FN_USB0_PPON,      GPIO_FN_VBUS,
-
-        /* USB1 */
-        GPIO_FN_USB1_OCI,       GPIO_FN_USB1_PPON,
-
-        /* BBIF1 */
-        GPIO_FN_BBIF1_RXD,      GPIO_FN_BBIF1_TXD,      GPIO_FN_BBIF1_TSYNC,
-        GPIO_FN_BBIF1_TSCK,     GPIO_FN_BBIF1_RSCK,     GPIO_FN_BBIF1_RSYNC,
-        GPIO_FN_BBIF1_FLOW,     GPIO_FN_BBIF1_RX_FLOW_N,
-
-        /* BBIF2 */
-        GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
-        GPIO_FN_BBIF2_RXD2_PORT60,
-        GPIO_FN_BBIF2_TSYNC2_PORT6,
-        GPIO_FN_BBIF2_TSCK2_PORT59,
-
-        GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
-        GPIO_FN_BBIF2_TXD2_PORT183,
-        GPIO_FN_BBIF2_TSCK2_PORT89,
-        GPIO_FN_BBIF2_TSYNC2_PORT184,
-
-        /* BSC / FLCTL / PCMCIA */
-        GPIO_FN_CS0,    GPIO_FN_CS2,    GPIO_FN_CS4,
-        GPIO_FN_CS5B,   GPIO_FN_CS6A,
-        GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
-        GPIO_FN_CS5A_PORT19,
-        GPIO_FN_IOIS16, /* ? */
-
-        GPIO_FN_A0,     GPIO_FN_A1,     GPIO_FN_A2,     GPIO_FN_A3,
-        GPIO_FN_A4_FOE,         /* share with FLCTL */
-        GPIO_FN_A5_FCDE,        /* share with FLCTL */
-        GPIO_FN_A6,     GPIO_FN_A7,     GPIO_FN_A8,     GPIO_FN_A9,
-        GPIO_FN_A10,    GPIO_FN_A11,    GPIO_FN_A12,    GPIO_FN_A13,
-        GPIO_FN_A14,    GPIO_FN_A15,    GPIO_FN_A16,    GPIO_FN_A17,
-        GPIO_FN_A18,    GPIO_FN_A19,    GPIO_FN_A20,    GPIO_FN_A21,
-        GPIO_FN_A22,    GPIO_FN_A23,    GPIO_FN_A24,    GPIO_FN_A25,
-        GPIO_FN_A26,
-
-        GPIO_FN_D0_NAF0,        GPIO_FN_D1_NAF1,        /* share with FLCTL */
-        GPIO_FN_D2_NAF2,        GPIO_FN_D3_NAF3,        /* share with FLCTL */
-        GPIO_FN_D4_NAF4,        GPIO_FN_D5_NAF5,        /* share with FLCTL */
-        GPIO_FN_D6_NAF6,        GPIO_FN_D7_NAF7,        /* share with FLCTL */
-        GPIO_FN_D8_NAF8,        GPIO_FN_D9_NAF9,        /* share with FLCTL */
-        GPIO_FN_D10_NAF10,      GPIO_FN_D11_NAF11,      /* share with FLCTL */
-        GPIO_FN_D12_NAF12,      GPIO_FN_D13_NAF13,      /* share with FLCTL */
-        GPIO_FN_D14_NAF14,      GPIO_FN_D15_NAF15,      /* share with FLCTL */
-
-        GPIO_FN_D16,    GPIO_FN_D17,    GPIO_FN_D18,    GPIO_FN_D19,
-        GPIO_FN_D20,    GPIO_FN_D21,    GPIO_FN_D22,    GPIO_FN_D23,
-        GPIO_FN_D24,    GPIO_FN_D25,    GPIO_FN_D26,    GPIO_FN_D27,
-        GPIO_FN_D28,    GPIO_FN_D29,    GPIO_FN_D30,    GPIO_FN_D31,
-
-        GPIO_FN_WE0_FWE,        /* share with FLCTL */
-        GPIO_FN_WE1,
-        GPIO_FN_WE2_ICIORD,     /* share with PCMCIA */
-        GPIO_FN_WE3_ICIOWR,     /* share with PCMCIA */
-        GPIO_FN_CKO,    GPIO_FN_BS,     GPIO_FN_RDWR,
-        GPIO_FN_RD_FSC,         /* share with FLCTL */
-        GPIO_FN_WAIT_PORT177,   /* WAIT Port 90/177 */
-        GPIO_FN_WAIT_PORT90,
-
-        GPIO_FN_FCE0,   GPIO_FN_FCE1,   GPIO_FN_FRB, /* FLCTL */
-
-        /* IRDA */
-        GPIO_FN_IRDA_FIRSEL,    GPIO_FN_IRDA_IN,        GPIO_FN_IRDA_OUT,
-
-        /* ATAPI */
-        GPIO_FN_IDE_D0,         GPIO_FN_IDE_D1,         GPIO_FN_IDE_D2,
-        GPIO_FN_IDE_D3,         GPIO_FN_IDE_D4,         GPIO_FN_IDE_D5,
-        GPIO_FN_IDE_D6,         GPIO_FN_IDE_D7,         GPIO_FN_IDE_D8,
-        GPIO_FN_IDE_D9,         GPIO_FN_IDE_D10,        GPIO_FN_IDE_D11,
-        GPIO_FN_IDE_D12,        GPIO_FN_IDE_D13,        GPIO_FN_IDE_D14,
-        GPIO_FN_IDE_D15,        GPIO_FN_IDE_A0,         GPIO_FN_IDE_A1,
-        GPIO_FN_IDE_A2,         GPIO_FN_IDE_CS0,        GPIO_FN_IDE_CS1,
-        GPIO_FN_IDE_IOWR,       GPIO_FN_IDE_IORD,       GPIO_FN_IDE_IORDY,
-        GPIO_FN_IDE_INT,        GPIO_FN_IDE_RST,        GPIO_FN_IDE_DIRECTION,
-        GPIO_FN_IDE_EXBUF_ENB,  GPIO_FN_IDE_IODACK,     GPIO_FN_IDE_IODREQ,
-
-        /* RMII */
-        GPIO_FN_RMII_CRS_DV,    GPIO_FN_RMII_RX_ER,     GPIO_FN_RMII_RXD0,
-        GPIO_FN_RMII_RXD1,      GPIO_FN_RMII_TX_EN,     GPIO_FN_RMII_TXD0,
-        GPIO_FN_RMII_MDC,       GPIO_FN_RMII_TXD1,      GPIO_FN_RMII_MDIO,
-        GPIO_FN_RMII_REF50CK,   /* for RMII */
-        GPIO_FN_RMII_REF125CK,  /* for GMII */
-
-        /* GEther */
-        GPIO_FN_ET_TX_CLK,      GPIO_FN_ET_TX_EN,       GPIO_FN_ET_ETXD0,
-        GPIO_FN_ET_ETXD1,       GPIO_FN_ET_ETXD2,       GPIO_FN_ET_ETXD3,
-        GPIO_FN_ET_ETXD4,       GPIO_FN_ET_ETXD5, /* for GEther */
-        GPIO_FN_ET_ETXD6,       GPIO_FN_ET_ETXD7, /* for GEther */
-        GPIO_FN_ET_COL,         GPIO_FN_ET_TX_ER,
-        GPIO_FN_ET_RX_CLK,      GPIO_FN_ET_RX_DV,
-        GPIO_FN_ET_ERXD0,       GPIO_FN_ET_ERXD1,
-        GPIO_FN_ET_ERXD2,       GPIO_FN_ET_ERXD3,
-        GPIO_FN_ET_ERXD4,       GPIO_FN_ET_ERXD5, /* for GEther */
-        GPIO_FN_ET_ERXD6,       GPIO_FN_ET_ERXD7, /* for GEther */
-        GPIO_FN_ET_RX_ER,       GPIO_FN_ET_CRS,
-        GPIO_FN_ET_MDC,         GPIO_FN_ET_MDIO,
-        GPIO_FN_ET_LINK,        GPIO_FN_ET_PHY_INT,
-        GPIO_FN_ET_WOL,         GPIO_FN_ET_GTX_CLK,
-
-        /* DMA0 */
-        GPIO_FN_DREQ0,          GPIO_FN_DACK0,
-
-        /* DMA1 */
-        GPIO_FN_DREQ1,          GPIO_FN_DACK1,
-
-        /* SYSC */
-        GPIO_FN_RESETOUTS,
-        GPIO_FN_RESETP_PULLUP,
-        GPIO_FN_RESETP_PLAIN,
-
-        /* HDMI */
-        GPIO_FN_HDMI_HPD,
-        GPIO_FN_HDMI_CEC,
-
-        /* SDENC */
-        GPIO_FN_SDENC_CPG,
-        GPIO_FN_SDENC_DV_CLKI,
-
-        /* IRREM */
-        GPIO_FN_IROUT,
-
-        /* DEBUG */
-        GPIO_FN_EDEBGREQ_PULLDOWN,
-        GPIO_FN_EDEBGREQ_PULLUP,
-
-        GPIO_FN_TRACEAUD_FROM_VIO,
-        GPIO_FN_TRACEAUD_FROM_LCDC0,
-        GPIO_FN_TRACEAUD_FROM_MEMC,
-};
-
 /* DMA slave IDs */
 enum {
         SHDMA_SLAVE_INVALID,
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
index 951149e6bcca..851d027a2f06 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -18,15 +18,26 @@
 #ifndef __ASM_R8A7778_H__
 #define __ASM_R8A7778_H__
 
+#include <linux/mmc/sh_mmcif.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/sh_eth.h>
+#include <linux/platform_data/usb-rcar-phy.h>
 
 extern void r8a7778_add_standard_devices(void);
 extern void r8a7778_add_standard_devices_dt(void);
 extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata);
+extern void r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata);
+extern void r8a7778_add_i2c_device(int id);
+extern void r8a7778_add_hspi_device(int id);
+extern void r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info);
+
+extern void r8a7778_init_late(void);
 extern void r8a7778_init_delay(void);
 extern void r8a7778_init_irq(void);
 extern void r8a7778_init_irq_dt(void);
 extern void r8a7778_clock_init(void);
 extern void r8a7778_init_irq_extpin(int irlm);
+extern void r8a7778_pinmux_init(void);
+extern void r8a7778_sdhi_init(int id, struct sh_mobile_sdhi_info *info);
 
 #endif /* __ASM_R8A7778_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 188b295938a5..fc47073c7ba9 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -4,6 +4,7 @@
 #include <linux/sh_clk.h>
 #include <linux/pm_domain.h>
 #include <linux/sh_eth.h>
+#include <linux/platform_data/usb-rcar-phy.h>
 
 struct platform_device;
 
@@ -33,6 +34,8 @@ extern void r8a7779_add_early_devices(void);
 extern void r8a7779_add_standard_devices(void);
 extern void r8a7779_add_standard_devices_dt(void);
 extern void r8a7779_add_ether_device(struct sh_eth_plat_data *pdata);
+extern void r8a7779_add_usb_phy_device(struct rcar_phy_platform_data *pdata);
+extern void r8a7779_init_late(void);
 extern void r8a7779_clock_init(void);
 extern void r8a7779_pinmux_init(void);
 extern void r8a7779_pm_init(void);
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index fd7cba024c39..e882717ca97f 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -15,397 +15,6 @@
 #include <linux/pm_domain.h>
 #include <mach/pm-rmobile.h>
 
-/*
- * Pin Function Controller:
- *      GPIO_FN_xx - GPIO used to select pin function
- *      GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
- */
-enum {
-        /* PORT */
-        GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
-        GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
-
-        GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
-        GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
-
-        GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
-        GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
-
-        GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
-        GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
-
-        GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
-        GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
-
-        GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
-        GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
-
-        GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
-        GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
-
-        GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
-        GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
-
-        GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
-        GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
-
-        GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
-        GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
-
-        GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
-        GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
-
-        GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
-        GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
-
-        GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
-        GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
-
-        GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
-        GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
-
-        GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
-        GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
-
-        GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
-        GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
-
-        GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
-        GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
-
-        GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
-        GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
-
-        GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
-        GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
-
-        GPIO_PORT190,
-
-        /* IRQ */
-        GPIO_FN_IRQ0_6,         /* PORT   6 */
-        GPIO_FN_IRQ0_162,       /* PORT 162 */
-        GPIO_FN_IRQ1,           /* PORT  12 */
-        GPIO_FN_IRQ2_4,         /* PORT   4 */
-        GPIO_FN_IRQ2_5,         /* PORT   5 */
-        GPIO_FN_IRQ3_8,         /* PORT   8 */
-        GPIO_FN_IRQ3_16,        /* PORT  16 */
-        GPIO_FN_IRQ4_17,        /* PORT  17 */
-        GPIO_FN_IRQ4_163,       /* PORT 163 */
-        GPIO_FN_IRQ5,           /* PORT  18 */
-        GPIO_FN_IRQ6_39,        /* PORT  39 */
-        GPIO_FN_IRQ6_164,       /* PORT 164 */
-        GPIO_FN_IRQ7_40,        /* PORT  40 */
-        GPIO_FN_IRQ7_167,       /* PORT 167 */
-        GPIO_FN_IRQ8_41,        /* PORT  41 */
-        GPIO_FN_IRQ8_168,       /* PORT 168 */
-        GPIO_FN_IRQ9_42,        /* PORT  42 */
-        GPIO_FN_IRQ9_169,       /* PORT 169 */
-        GPIO_FN_IRQ10,          /* PORT  65 */
-        GPIO_FN_IRQ11,          /* PORT  67 */
-        GPIO_FN_IRQ12_80,       /* PORT  80 */
-        GPIO_FN_IRQ12_137,      /* PORT 137 */
-        GPIO_FN_IRQ13_81,       /* PORT  81 */
-        GPIO_FN_IRQ13_145,      /* PORT 145 */
-        GPIO_FN_IRQ14_82,       /* PORT  82 */
-        GPIO_FN_IRQ14_146,      /* PORT 146 */
-        GPIO_FN_IRQ15_83,       /* PORT  83 */
-        GPIO_FN_IRQ15_147,      /* PORT 147 */
-        GPIO_FN_IRQ16_84,       /* PORT  84 */
-        GPIO_FN_IRQ16_170,      /* PORT 170 */
-        GPIO_FN_IRQ17,          /* PORT  85 */
-        GPIO_FN_IRQ18,          /* PORT  86 */
-        GPIO_FN_IRQ19,          /* PORT  87 */
-        GPIO_FN_IRQ20,          /* PORT  92 */
-        GPIO_FN_IRQ21,          /* PORT  93 */
-        GPIO_FN_IRQ22,          /* PORT  94 */
-        GPIO_FN_IRQ23,          /* PORT  95 */
-        GPIO_FN_IRQ24,          /* PORT 112 */
-        GPIO_FN_IRQ25,          /* PORT 119 */
-        GPIO_FN_IRQ26_121,      /* PORT 121 */
-        GPIO_FN_IRQ26_172,      /* PORT 172 */
-        GPIO_FN_IRQ27_122,      /* PORT 122 */
-        GPIO_FN_IRQ27_180,      /* PORT 180 */
-        GPIO_FN_IRQ28_123,      /* PORT 123 */
-        GPIO_FN_IRQ28_181,      /* PORT 181 */
-        GPIO_FN_IRQ29_129,      /* PORT 129 */
-        GPIO_FN_IRQ29_182,      /* PORT 182 */
-        GPIO_FN_IRQ30_130,      /* PORT 130 */
-        GPIO_FN_IRQ30_183,      /* PORT 183 */
-        GPIO_FN_IRQ31_138,      /* PORT 138 */
-        GPIO_FN_IRQ31_184,      /* PORT 184 */
-
-        /*
-         * MSIOF0       (PORT 36, 37, 38, 39
-         *                    40, 41, 42, 43, 44, 45)
-         */
-        GPIO_FN_MSIOF0_TSYNC,   GPIO_FN_MSIOF0_TSCK,
-        GPIO_FN_MSIOF0_RXD,     GPIO_FN_MSIOF0_RSCK,
-        GPIO_FN_MSIOF0_RSYNC,   GPIO_FN_MSIOF0_MCK0,
-        GPIO_FN_MSIOF0_MCK1,    GPIO_FN_MSIOF0_SS1,
-        GPIO_FN_MSIOF0_SS2,     GPIO_FN_MSIOF0_TXD,
-
-        /*
-         * MSIOF1       (PORT 39, 40, 41, 42, 43, 44
-         *                    84, 85, 86, 87, 88, 89, 90, 91, 92, 93)
-         */
-        GPIO_FN_MSIOF1_TSCK_39, GPIO_FN_MSIOF1_TSYNC_40,
-        GPIO_FN_MSIOF1_TSCK_88, GPIO_FN_MSIOF1_TSYNC_89,
-        GPIO_FN_MSIOF1_TXD_41,  GPIO_FN_MSIOF1_RXD_42,
-        GPIO_FN_MSIOF1_TXD_90,  GPIO_FN_MSIOF1_RXD_91,
-        GPIO_FN_MSIOF1_SS1_43,  GPIO_FN_MSIOF1_SS2_44,
-        GPIO_FN_MSIOF1_SS1_92,  GPIO_FN_MSIOF1_SS2_93,
-        GPIO_FN_MSIOF1_RSCK,    GPIO_FN_MSIOF1_RSYNC,
-        GPIO_FN_MSIOF1_MCK0,    GPIO_FN_MSIOF1_MCK1,
-
-        /*
-         * MSIOF2       (PORT 134, 135, 136, 137, 138, 139
-         *                    148, 149, 150, 151)
-         */
-        GPIO_FN_MSIOF2_RSCK,    GPIO_FN_MSIOF2_RSYNC,
-        GPIO_FN_MSIOF2_MCK0,    GPIO_FN_MSIOF2_MCK1,
-        GPIO_FN_MSIOF2_SS1,     GPIO_FN_MSIOF2_SS2,
-        GPIO_FN_MSIOF2_TSYNC,   GPIO_FN_MSIOF2_TSCK,
-        GPIO_FN_MSIOF2_RXD,     GPIO_FN_MSIOF2_TXD,
-
-        /* MSIOF3       (PORT 76, 77, 78, 79, 80, 81, 82, 83) */
-        GPIO_FN_BBIF1_RXD,      GPIO_FN_BBIF1_TSYNC,
-        GPIO_FN_BBIF1_TSCK,     GPIO_FN_BBIF1_TXD,
-        GPIO_FN_BBIF1_RSCK,     GPIO_FN_BBIF1_RSYNC,
-        GPIO_FN_BBIF1_FLOW,     GPIO_FN_BB_RX_FLOW_N,
-
-        /* MSIOF4       (PORT 0, 1, 2, 3) */
-        GPIO_FN_BBIF2_TSCK1,    GPIO_FN_BBIF2_TSYNC1,
-        GPIO_FN_BBIF2_TXD1,     GPIO_FN_BBIF2_RXD,
-
-        /* FSI          (PORT 4, 5, 6, 7, 8, 9, 10, 11, 15) */
-        GPIO_FN_FSIACK,         GPIO_FN_FSIBCK,
-        GPIO_FN_FSIAILR,        GPIO_FN_FSIAIBT,
-        GPIO_FN_FSIAISLD,       GPIO_FN_FSIAOMC,
-        GPIO_FN_FSIAOLR,        GPIO_FN_FSIAOBT,
-        GPIO_FN_FSIAOSLD,       GPIO_FN_FSIASPDIF_11,
-        GPIO_FN_FSIASPDIF_15,
-
-        /* FMSI         (PORT 12, 13, 14, 15, 16, 17, 18, 65) */
-        GPIO_FN_FMSOCK,         GPIO_FN_FMSOOLR,
-        GPIO_FN_FMSIOLR,        GPIO_FN_FMSOOBT,
-        GPIO_FN_FMSIOBT,        GPIO_FN_FMSOSLD,
-        GPIO_FN_FMSOILR,        GPIO_FN_FMSIILR,
-        GPIO_FN_FMSOIBT,        GPIO_FN_FMSIIBT,
-        GPIO_FN_FMSISLD,        GPIO_FN_FMSICK,
-
-        /* SCIFA0       (PORT 152, 153, 156, 157, 158) */
-        GPIO_FN_SCIFA0_TXD,     GPIO_FN_SCIFA0_RXD,
-        GPIO_FN_SCIFA0_SCK,     GPIO_FN_SCIFA0_RTS,
-        GPIO_FN_SCIFA0_CTS,
-
-        /* SCIFA1       (PORT 154, 155, 159, 160, 161) */
-        GPIO_FN_SCIFA1_TXD,     GPIO_FN_SCIFA1_RXD,
-        GPIO_FN_SCIFA1_SCK,     GPIO_FN_SCIFA1_RTS,
-        GPIO_FN_SCIFA1_CTS,
-
-        /* SCIFA2       (PORT 94, 95, 96, 97, 98) */
-        GPIO_FN_SCIFA2_CTS1,    GPIO_FN_SCIFA2_RTS1,
-        GPIO_FN_SCIFA2_TXD1,    GPIO_FN_SCIFA2_RXD1,
-        GPIO_FN_SCIFA2_SCK1,
-
-        /* SCIFA3       (PORT 43, 44,
-                             140, 141, 142, 143, 144) */
-        GPIO_FN_SCIFA3_CTS_43,  GPIO_FN_SCIFA3_CTS_140,
-        GPIO_FN_SCIFA3_RTS_44,  GPIO_FN_SCIFA3_RTS_141,
-        GPIO_FN_SCIFA3_SCK,     GPIO_FN_SCIFA3_TXD,
-        GPIO_FN_SCIFA3_RXD,
-
-        /* SCIFA4       (PORT 5, 6) */
-        GPIO_FN_SCIFA4_RXD,     GPIO_FN_SCIFA4_TXD,
-
-        /* SCIFA5       (PORT 8, 12) */
-        GPIO_FN_SCIFA5_RXD,     GPIO_FN_SCIFA5_TXD,
-
-        /* SCIFB        (PORT 162, 163, 164, 165, 166) */
-        GPIO_FN_SCIFB_SCK,      GPIO_FN_SCIFB_RTS,
-        GPIO_FN_SCIFB_CTS,      GPIO_FN_SCIFB_TXD,
-        GPIO_FN_SCIFB_RXD,
-
-        /*
-         * CEU          (PORT 16, 17,
-         *                    100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
-         *                    110, 111, 112, 113, 114, 115, 116, 117, 118, 119,
-         *                    120)
-         */
-        GPIO_FN_VIO_HD,         GPIO_FN_VIO_CKO1,       GPIO_FN_VIO_CKO2,
-        GPIO_FN_VIO_VD,         GPIO_FN_VIO_CLK,        GPIO_FN_VIO_FIELD,
-        GPIO_FN_VIO_CKO,
-        GPIO_FN_VIO_D0,         GPIO_FN_VIO_D1,         GPIO_FN_VIO_D2,
-        GPIO_FN_VIO_D3,         GPIO_FN_VIO_D4,         GPIO_FN_VIO_D5,
-        GPIO_FN_VIO_D6,         GPIO_FN_VIO_D7,         GPIO_FN_VIO_D8,
-        GPIO_FN_VIO_D9,         GPIO_FN_VIO_D10,        GPIO_FN_VIO_D11,
-        GPIO_FN_VIO_D12,        GPIO_FN_VIO_D13,        GPIO_FN_VIO_D14,
-        GPIO_FN_VIO_D15,
-
-        /* USB0         (PORT 113, 114, 115, 116, 117, 167) */
-        GPIO_FN_IDIN_0,         GPIO_FN_EXTLP_0,
-        GPIO_FN_OVCN2_0,        GPIO_FN_PWEN_0,
-        GPIO_FN_OVCN_0,         GPIO_FN_VBUS0_0,
-
-        /* USB1         (PORT 18, 113, 114, 115, 116, 117, 138, 162, 168) */
-        GPIO_FN_IDIN_1_18,      GPIO_FN_IDIN_1_113,
-        GPIO_FN_PWEN_1_115,     GPIO_FN_PWEN_1_138,
-        GPIO_FN_OVCN_1_114,     GPIO_FN_OVCN_1_162,
-        GPIO_FN_EXTLP_1,        GPIO_FN_OVCN2_1,
-        GPIO_FN_VBUS0_1,
-
-        /* GPIO         (PORT 41, 42, 43, 44) */
-        GPIO_FN_GPI0,   GPIO_FN_GPI1,   GPIO_FN_GPO0,   GPIO_FN_GPO1,
-
-        /*
-         * BSC          (PORT 19,
-         *                    20, 21, 22, 25, 26, 27, 28, 29,
-         *                    30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
-         *                    40, 41, 42, 43, 44, 45,
-         *                    62, 63, 64, 65, 66, 67,
-         *                    71, 72, 74, 75)
-         */
-        GPIO_FN_BS,     GPIO_FN_WE1,
-        GPIO_FN_CKO,    GPIO_FN_WAIT,   GPIO_FN_RDWR,
-
-        GPIO_FN_A0,     GPIO_FN_A1,     GPIO_FN_A2,     GPIO_FN_A3,
-        GPIO_FN_A6,     GPIO_FN_A7,     GPIO_FN_A8,     GPIO_FN_A9,
-        GPIO_FN_A10,    GPIO_FN_A11,    GPIO_FN_A12,    GPIO_FN_A13,
-        GPIO_FN_A14,    GPIO_FN_A15,    GPIO_FN_A16,    GPIO_FN_A17,
-        GPIO_FN_A18,    GPIO_FN_A19,    GPIO_FN_A20,    GPIO_FN_A21,
-        GPIO_FN_A22,    GPIO_FN_A23,    GPIO_FN_A24,    GPIO_FN_A25,
-        GPIO_FN_A26,
-
-        GPIO_FN_CS0,    GPIO_FN_CS2,    GPIO_FN_CS4,
-        GPIO_FN_CS5A,   GPIO_FN_CS5B,   GPIO_FN_CS6A,
-
-        /*
-         * BSC/FLCTL            (PORT 23, 24,
-         *                            46, 47, 48, 49,
-         *                            50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
-         *                            60, 61, 69, 70)
-         */
-        GPIO_FN_RD_FSC,         GPIO_FN_WE0_FWE,
-        GPIO_FN_A4_FOE,         GPIO_FN_A5_FCDE,
-        GPIO_FN_D0_NAF0,        GPIO_FN_D1_NAF1,        GPIO_FN_D2_NAF2,
-        GPIO_FN_D3_NAF3,        GPIO_FN_D4_NAF4,        GPIO_FN_D5_NAF5,
-        GPIO_FN_D6_NAF6,        GPIO_FN_D7_NAF7,        GPIO_FN_D8_NAF8,
-        GPIO_FN_D9_NAF9,        GPIO_FN_D10_NAF10,      GPIO_FN_D11_NAF11,
-        GPIO_FN_D12_NAF12,      GPIO_FN_D13_NAF13,      GPIO_FN_D14_NAF14,
-        GPIO_FN_D15_NAF15,
-
-        /* SPU2         (PORT 65) */
-        GPIO_FN_VINT_I,
-
-        /* FLCTL        (PORT 66, 68, 73) */
-        GPIO_FN_FCE1,   GPIO_FN_FCE0,   GPIO_FN_FRB,
-
-        /* HSI          (PORT 76, 77, 78, 79, 80, 81, 82, 83) */
-        GPIO_FN_GP_RX_FLAG,     GPIO_FN_GP_RX_DATA,     GPIO_FN_GP_TX_READY,
-        GPIO_FN_GP_RX_WAKE,     GPIO_FN_MP_TX_FLAG,     GPIO_FN_MP_TX_DATA,
-        GPIO_FN_MP_RX_READY,    GPIO_FN_MP_TX_WAKE,
-
-        /*
-         * MFI          (PORT 76, 77, 78, 79,
-         *                    80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
-         *                    90, 91, 92, 93, 94, 95, 96, 97, 98, 99)
-         */
-        GPIO_FN_MFIv6,  /* see MSEL4CR 6 */
-        GPIO_FN_MFIv4,  /* see MSEL4CR 6 */
-
-        GPIO_FN_MEMC_CS0,               GPIO_FN_MEMC_BUSCLK_MEMC_A0,
-        GPIO_FN_MEMC_CS1_MEMC_A1,       GPIO_FN_MEMC_ADV_MEMC_DREQ0,
-        GPIO_FN_MEMC_WAIT_MEMC_DREQ1,   GPIO_FN_MEMC_NOE,
-        GPIO_FN_MEMC_NWE,               GPIO_FN_MEMC_INT,
-
-        GPIO_FN_MEMC_AD0,       GPIO_FN_MEMC_AD1,       GPIO_FN_MEMC_AD2,
-        GPIO_FN_MEMC_AD3,       GPIO_FN_MEMC_AD4,       GPIO_FN_MEMC_AD5,
-        GPIO_FN_MEMC_AD6,       GPIO_FN_MEMC_AD7,       GPIO_FN_MEMC_AD8,
-        GPIO_FN_MEMC_AD9,       GPIO_FN_MEMC_AD10,      GPIO_FN_MEMC_AD11,
-        GPIO_FN_MEMC_AD12,      GPIO_FN_MEMC_AD13,      GPIO_FN_MEMC_AD14,
-        GPIO_FN_MEMC_AD15,
-
-        /* SIM          (PORT 94, 95, 98) */
-        GPIO_FN_SIM_RST,        GPIO_FN_SIM_CLK,        GPIO_FN_SIM_D,
-
-        /* TPU          (PORT 93, 99, 112, 160, 161) */
-        GPIO_FN_TPU0TO0,        GPIO_FN_TPU0TO1,
-        GPIO_FN_TPU0TO2_93,     GPIO_FN_TPU0TO2_99,
-        GPIO_FN_TPU0TO3,
-
-        /* I2C2         (PORT 110, 111) */
-        GPIO_FN_I2C_SCL2,       GPIO_FN_I2C_SDA2,
-
-        /* I2C3(1)      (PORT 114, 115) */
-        GPIO_FN_I2C_SCL3,       GPIO_FN_I2C_SDA3,
-
-        /* I2C3(2)      (PORT 137, 145) */
-        GPIO_FN_I2C_SCL3S,      GPIO_FN_I2C_SDA3S,
-
-        /* I2C4(2)      (PORT 116, 117) */
-        GPIO_FN_I2C_SCL4,       GPIO_FN_I2C_SDA4,
-
-        /* I2C4(2)      (PORT 146, 147) */
-        GPIO_FN_I2C_SCL4S,      GPIO_FN_I2C_SDA4S,
-
-        /*
-         * KEYSC        (PORT 121, 122, 123, 124, 125, 126, 127, 128, 129,
-         *                    130, 131, 132, 133, 134, 135, 136)
-         */
-        GPIO_FN_KEYOUT0,        GPIO_FN_KEYIN0_121,     GPIO_FN_KEYIN0_136,
-        GPIO_FN_KEYOUT1,        GPIO_FN_KEYIN1_122,     GPIO_FN_KEYIN1_135,
-        GPIO_FN_KEYOUT2,        GPIO_FN_KEYIN2_123,     GPIO_FN_KEYIN2_134,
-        GPIO_FN_KEYOUT3,        GPIO_FN_KEYIN3_124,     GPIO_FN_KEYIN3_133,
-        GPIO_FN_KEYOUT4,        GPIO_FN_KEYIN4,
-        GPIO_FN_KEYOUT5,        GPIO_FN_KEYIN5,
-        GPIO_FN_KEYOUT6,        GPIO_FN_KEYIN6,
-        GPIO_FN_KEYOUT7,        GPIO_FN_KEYIN7,
-
-        /*
-         * LCDC         (PORT      121, 122, 123, 124, 125, 126, 127, 128, 129,
-         *                    130, 131, 132, 133, 134, 135, 136, 137, 138, 139,
-         *                    140, 141, 142, 143, 144, 145, 146, 147, 148, 149,
-         *                    150, 151)
-         */
-        GPIO_FN_LCDC0_SELECT, /* LCDC 0 */
-        GPIO_FN_LCDC1_SELECT, /* LCDC 1 */
-        GPIO_FN_LCDHSYN,        GPIO_FN_LCDCS,  GPIO_FN_LCDVSYN,
-        GPIO_FN_LCDDCK,         GPIO_FN_LCDWR,  GPIO_FN_LCDRD,
-        GPIO_FN_LCDDISP,        GPIO_FN_LCDRS,  GPIO_FN_LCDLCLK,
-        GPIO_FN_LCDDON,
-
-        GPIO_FN_LCDD0,  GPIO_FN_LCDD1,  GPIO_FN_LCDD2,  GPIO_FN_LCDD3,
-        GPIO_FN_LCDD4,  GPIO_FN_LCDD5,  GPIO_FN_LCDD6,  GPIO_FN_LCDD7,
-        GPIO_FN_LCDD8,  GPIO_FN_LCDD9,  GPIO_FN_LCDD10, GPIO_FN_LCDD11,
-        GPIO_FN_LCDD12, GPIO_FN_LCDD13, GPIO_FN_LCDD14, GPIO_FN_LCDD15,
-        GPIO_FN_LCDD16, GPIO_FN_LCDD17, GPIO_FN_LCDD18, GPIO_FN_LCDD19,
-        GPIO_FN_LCDD20, GPIO_FN_LCDD21, GPIO_FN_LCDD22, GPIO_FN_LCDD23,
-
-        /* IRDA         (PORT 139, 140, 141, 142) */
-        GPIO_FN_IRDA_OUT,       GPIO_FN_IRDA_IN,        GPIO_FN_IRDA_FIRSEL,
-        GPIO_FN_IROUT_139,      GPIO_FN_IROUT_140,
-
-        /* TSIF1        (PORT 156, 157, 158, 159) */
-        GPIO_FN_TS0_1SELECT, /* TSIF0 - 1 select */
-        GPIO_FN_TS0_2SELECT, /* TSIF0 - 2 select */
-        GPIO_FN_TS1_1SELECT, /* TSIF1 - 1 select */
-        GPIO_FN_TS1_2SELECT, /* TSIF1 - 2 select */
-
-        GPIO_FN_TS_SPSYNC1,     GPIO_FN_TS_SDAT1,
-        GPIO_FN_TS_SDEN1,       GPIO_FN_TS_SCK1,
-
-        /* TSIF2        (PORT 137, 145, 146, 147) */
-        GPIO_FN_TS_SPSYNC2,     GPIO_FN_TS_SDAT2,
-        GPIO_FN_TS_SDEN2,       GPIO_FN_TS_SCK2,
-
-        /* HDMI         (PORT 169, 170) */
-        GPIO_FN_HDMI_HPD,       GPIO_FN_HDMI_CEC,
-
-        /* SDENC        see MSEL4CR 19 */
-        GPIO_FN_SDENC_CPG,
-        GPIO_FN_SDENC_DV_CLKI,
-};
-
 /* DMA slave IDs */
 enum {
         SHDMA_SLAVE_INVALID,
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 326a4ab0bd5f..3a6b6fe7b6c0 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -70,29 +70,15 @@ void __init r8a7740_map_io(void)
 }
 
 /* PFC */
-static struct resource r8a7740_pfc_resources[] = {
-        [0] = {
-                .start  = 0xe6050000,
-                .end    = 0xe6057fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 0xe605800c,
-                .end    = 0xe605802b,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device r8a7740_pfc_device = {
-        .name           = "pfc-r8a7740",
-        .id             = -1,
-        .resource       = r8a7740_pfc_resources,
-        .num_resources  = ARRAY_SIZE(r8a7740_pfc_resources),
+static const struct resource pfc_resources[] = {
+        DEFINE_RES_MEM(0xe6050000, 0x8000),
+        DEFINE_RES_MEM(0xe605800c, 0x0020),
 };
 
 void __init r8a7740_pinmux_init(void)
 {
-        platform_device_register(&r8a7740_pfc_device);
+        platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
+                                        ARRAY_SIZE(pfc_resources));
 }
 
 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 30b4a336308f..80c20392ad7c 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -24,11 +24,18 @@
 #include <linux/irqchip/arm-gic.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
 #include <linux/platform_device.h>
 #include <linux/irqchip.h>
 #include <linux/serial_sci.h>
 #include <linux/sh_timer.h>
+#include <linux/pm_runtime.h>
+#include <linux/usb/phy.h>
+#include <linux/usb/hcd.h>
+#include <linux/usb/ehci_pdriver.h>
+#include <linux/usb/ohci_pdriver.h>
+#include <linux/dma-mapping.h>
 #include <mach/irqs.h>
 #include <mach/r8a7778.h>
 #include <mach/common.h>
@@ -80,12 +87,6 @@ static struct sh_timer_config sh_tmu1_platform_data = {
         .clocksource_rating     = 200,
 };
 
-/* Ether */
-static struct resource ether_resources[] = {
-        DEFINE_RES_MEM(0xfde00000, 0x400),
-        DEFINE_RES_IRQ(gic_iid(0x89)),
-};
-
 #define r8a7778_register_tmu(idx)                       \
         platform_device_register_resndata(              \
                 &platform_bus, "sh_tmu", idx,           \
@@ -94,6 +95,244 @@ static struct resource ether_resources[] = {
                 &sh_tmu##idx##_platform_data,           \
                 sizeof(sh_tmu##idx##_platform_data))
 
+/* USB PHY */
+static struct resource usb_phy_resources[] __initdata = {
+        DEFINE_RES_MEM(0xffe70800, 0x100),
+        DEFINE_RES_MEM(0xffe76000, 0x100),
+};
+
+void __init r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata)
+{
+        platform_device_register_resndata(&platform_bus, "rcar_usb_phy", -1,
+                                          usb_phy_resources,
+                                          ARRAY_SIZE(usb_phy_resources),
+                                          pdata, sizeof(*pdata));
+}
+
+/* USB */
+static struct usb_phy *phy;
+
+static int usb_power_on(struct platform_device *pdev)
+{
+        if (IS_ERR(phy))
+                return PTR_ERR(phy);
+
+        pm_runtime_enable(&pdev->dev);
+        pm_runtime_get_sync(&pdev->dev);
+
+        usb_phy_init(phy);
+
+        return 0;
+}
+
+static void usb_power_off(struct platform_device *pdev)
+{
+        if (IS_ERR(phy))
+                return;
+
+        usb_phy_shutdown(phy);
+
+        pm_runtime_put_sync(&pdev->dev);
+        pm_runtime_disable(&pdev->dev);
+}
+
+static int ehci_init_internal_buffer(struct usb_hcd *hcd)
+{
+        /*
+         * Below are recommended values from the datasheet;
+         * see [USB :: Setting of EHCI Internal Buffer].
+         */
+        /* EHCI IP internal buffer setting */
+        iowrite32(0x00ff0040, hcd->regs + 0x0094);
+        /* EHCI IP internal buffer enable */
+        iowrite32(0x00000001, hcd->regs + 0x009C);
+
+        return 0;
+}
+
+static struct usb_ehci_pdata ehci_pdata __initdata = {
+        .power_on       = usb_power_on,
+        .power_off      = usb_power_off,
+        .power_suspend  = usb_power_off,
+        .pre_setup      = ehci_init_internal_buffer,
+};
+
+static struct resource ehci_resources[] __initdata = {
+        DEFINE_RES_MEM(0xffe70000, 0x400),
+        DEFINE_RES_IRQ(gic_iid(0x4c)),
+};
+
+static struct usb_ohci_pdata ohci_pdata __initdata = {
+        .power_on       = usb_power_on,
+        .power_off      = usb_power_off,
+        .power_suspend  = usb_power_off,
+};
+
+static struct resource ohci_resources[] __initdata = {
+        DEFINE_RES_MEM(0xffe70400, 0x400),
+        DEFINE_RES_IRQ(gic_iid(0x4c)),
+};
+
+#define USB_PLATFORM_INFO(hci)                                  \
+static struct platform_device_info hci##_info __initdata = {    \
+        .parent         = &platform_bus,                        \
+        .name           = #hci "-platform",                     \
+        .id             = -1,                                   \
+        .res            = hci##_resources,                      \
+        .num_res        = ARRAY_SIZE(hci##_resources),          \
+        .data           = &hci##_pdata,                         \
+        .size_data      = sizeof(hci##_pdata),                  \
+        .dma_mask       = DMA_BIT_MASK(32),                     \
+}
+
+USB_PLATFORM_INFO(ehci);
+USB_PLATFORM_INFO(ohci);
+
+/* Ether */
+static struct resource ether_resources[] = {
+        DEFINE_RES_MEM(0xfde00000, 0x400),
+        DEFINE_RES_IRQ(gic_iid(0x89)),
+};
+
+void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
+{
+        platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1,
+                                          ether_resources,
+                                          ARRAY_SIZE(ether_resources),
+                                          pdata, sizeof(*pdata));
+}
+
+/* PFC/GPIO */
+static struct resource pfc_resources[] = {
+        DEFINE_RES_MEM(0xfffc0000, 0x118),
+};
+
+#define R8A7778_GPIO(idx)                                               \
+static struct resource r8a7778_gpio##idx##_resources[] = {              \
+        DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30),              \
+        DEFINE_RES_IRQ(gic_iid(0x87)),                                  \
+};                                                                      \
+                                                                        \
+static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data = {    \
+        .gpio_base      = 32 * (idx),                                   \
+        .irq_base       = GPIO_IRQ_BASE(idx),                           \
+        .number_of_pins = 32,                                           \
+        .pctl_name      = "pfc-r8a7778",                                \
+}
+
+R8A7778_GPIO(0);
+R8A7778_GPIO(1);
+R8A7778_GPIO(2);
+R8A7778_GPIO(3);
+R8A7778_GPIO(4);
+
+#define r8a7778_register_gpio(idx)                              \
+        platform_device_register_resndata(                      \
+                &platform_bus, "gpio_rcar", idx,                \
+                r8a7778_gpio##idx##_resources,                  \
+                ARRAY_SIZE(r8a7778_gpio##idx##_resources),      \
+                &r8a7778_gpio##idx##_platform_data,             \
+                sizeof(r8a7778_gpio##idx##_platform_data))
+
+void __init r8a7778_pinmux_init(void)
+{
+        platform_device_register_simple(
+                "pfc-r8a7778", -1,
+                pfc_resources,
+                ARRAY_SIZE(pfc_resources));
+
+        r8a7778_register_gpio(0);
+        r8a7778_register_gpio(1);
+        r8a7778_register_gpio(2);
+        r8a7778_register_gpio(3);
+        r8a7778_register_gpio(4);
+};
+
+/* SDHI */
+static struct resource sdhi_resources[] = {
+        /* SDHI0 */
+        DEFINE_RES_MEM(0xFFE4C000, 0x100),
+        DEFINE_RES_IRQ(gic_iid(0x77)),
+        /* SDHI1 */
+        DEFINE_RES_MEM(0xFFE4D000, 0x100),
+        DEFINE_RES_IRQ(gic_iid(0x78)),
+        /* SDHI2 */
+        DEFINE_RES_MEM(0xFFE4F000, 0x100),
+        DEFINE_RES_IRQ(gic_iid(0x76)),
+};
+
+void __init r8a7778_sdhi_init(int id,
+                              struct sh_mobile_sdhi_info *info)
+{
+        BUG_ON(id < 0 || id > 2);
+
+        platform_device_register_resndata(
+                &platform_bus, "sh_mobile_sdhi", id,
+                sdhi_resources + (2 * id), 2,
+                info, sizeof(*info));
+}
+
+/* I2C */
+static struct resource i2c_resources[] __initdata = {
+        /* I2C0 */
+        DEFINE_RES_MEM(0xffc70000, 0x1000),
+        DEFINE_RES_IRQ(gic_iid(0x63)),
+        /* I2C1 */
+        DEFINE_RES_MEM(0xffc71000, 0x1000),
+        DEFINE_RES_IRQ(gic_iid(0x6e)),
+        /* I2C2 */
+        DEFINE_RES_MEM(0xffc72000, 0x1000),
+        DEFINE_RES_IRQ(gic_iid(0x6c)),
+        /* I2C3 */
+        DEFINE_RES_MEM(0xffc73000, 0x1000),
+        DEFINE_RES_IRQ(gic_iid(0x6d)),
+};
+
+void __init r8a7778_add_i2c_device(int id)
+{
+        BUG_ON(id < 0 || id > 3);
+
+        platform_device_register_simple(
+                "i2c-rcar", id,
+                i2c_resources + (2 * id), 2);
+}
+
+/* HSPI */
+static struct resource hspi_resources[] __initdata = {
+        /* HSPI0 */
+        DEFINE_RES_MEM(0xfffc7000, 0x18),
+        DEFINE_RES_IRQ(gic_iid(0x5f)),
+        /* HSPI1 */
+        DEFINE_RES_MEM(0xfffc8000, 0x18),
+        DEFINE_RES_IRQ(gic_iid(0x74)),
+        /* HSPI2 */
+        DEFINE_RES_MEM(0xfffc6000, 0x18),
+        DEFINE_RES_IRQ(gic_iid(0x75)),
+};
+
+void __init r8a7778_add_hspi_device(int id)
+{
+        BUG_ON(id < 0 || id > 2);
+
+        platform_device_register_simple(
+                "sh-hspi", id,
+                hspi_resources + (2 * id), 2);
+}
+
+/* MMC */
+static struct resource mmc_resources[] __initdata = {
+        DEFINE_RES_MEM(0xffe4e000, 0x100),
+        DEFINE_RES_IRQ(gic_iid(0x5d)),
+};
+
+void __init r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info)
+{
+        platform_device_register_resndata(
+                &platform_bus, "sh_mmcif", -1,
+                mmc_resources, ARRAY_SIZE(mmc_resources),
+                info, sizeof(*info));
+}
+
 void __init r8a7778_add_standard_devices(void)
 {
         int i;
@@ -118,12 +357,12 @@ void __init r8a7778_add_standard_devices(void)
         r8a7778_register_tmu(1);
 }
 
-void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
+void __init r8a7778_init_late(void)
 {
-        platform_device_register_resndata(&platform_bus, "sh_eth", -1,
-                                          ether_resources,
-                                          ARRAY_SIZE(ether_resources),
-                                          pdata, sizeof(*pdata));
+        phy = usb_get_phy(USB_PHY_TYPE_USB2);
+
+        platform_device_register_full(&ehci_info);
+        platform_device_register_full(&ohci_info);
 }
 
 static struct renesas_intc_irqpin_config irqpin_platform_data = {
@@ -239,6 +478,7 @@ DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
         .init_machine   = r8a7778_add_standard_devices_dt,
         .init_time      = shmobile_timer_init,
         .dt_compat      = r8a7778_compat_dt,
+        .init_late      = r8a7778_init_late,
 MACHINE_END
 
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index b0b394842ea5..398687761f50 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -32,6 +32,11 @@
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
 #include <linux/dma-mapping.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/hcd.h>
+#include <linux/usb/ehci_pdriver.h>
+#include <linux/usb/ohci_pdriver.h>
+#include <linux/pm_runtime.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <mach/r8a7779.h>
@@ -65,11 +70,7 @@ void __init r8a7779_map_io(void)
 }
 
 static struct resource r8a7779_pfc_resources[] = {
-        [0] = {
-                .start  = 0xfffc0000,
-                .end    = 0xfffc023b,
-                .flags  = IORESOURCE_MEM,
-        },
+        DEFINE_RES_MEM(0xfffc0000, 0x023c),
 };
 
 static struct platform_device r8a7779_pfc_device = {
@@ -81,15 +82,8 @@ static struct platform_device r8a7779_pfc_device = {
 
 #define R8A7779_GPIO(idx, npins) \
 static struct resource r8a7779_gpio##idx##_resources[] = {              \
-        [0] = {                                                         \
-                .start  = 0xffc40000 + 0x1000 * (idx),                  \
-                .end    = 0xffc4002b + 0x1000 * (idx),                  \
-                .flags  = IORESOURCE_MEM,                               \
-        },                                                              \
-        [1] = {                                                         \
-                .start  = gic_iid(0xad + (idx)),                        \
-                .flags  = IORESOURCE_IRQ,                               \
-        }                                                               \
+        DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c),          \
+        DEFINE_RES_IRQ(gic_iid(0xad + (idx))),                          \
 };                                                                      \
                                                                         \
 static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = {    \
@@ -394,6 +388,165 @@ static struct platform_device sata_device = {
         },
 };
 
+/* USB PHY */
+static struct resource usb_phy_resources[] __initdata = {
+        [0] = {
+                .start          = 0xffe70800,
+                .end            = 0xffe70900 - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+/* USB */
+static struct usb_phy *phy;
+
+static int usb_power_on(struct platform_device *pdev)
+{
+        if (IS_ERR(phy))
+                return PTR_ERR(phy);
+
+        pm_runtime_enable(&pdev->dev);
+        pm_runtime_get_sync(&pdev->dev);
+
+        usb_phy_init(phy);
+
+        return 0;
+}
+
+static void usb_power_off(struct platform_device *pdev)
+{
+        if (IS_ERR(phy))
+                return;
+
+        usb_phy_shutdown(phy);
+
+        pm_runtime_put_sync(&pdev->dev);
+        pm_runtime_disable(&pdev->dev);
+}
+
+static int ehci_init_internal_buffer(struct usb_hcd *hcd)
+{
+        /*
+         * Below are recommended values from the datasheet;
+         * see [USB :: Setting of EHCI Internal Buffer].
+         */
+        /* EHCI IP internal buffer setting */
+        iowrite32(0x00ff0040, hcd->regs + 0x0094);
+        /* EHCI IP internal buffer enable */
+        iowrite32(0x00000001, hcd->regs + 0x009C);
+
+        return 0;
+}
+
+static struct usb_ehci_pdata ehcix_pdata = {
+        .power_on       = usb_power_on,
+        .power_off      = usb_power_off,
+        .power_suspend  = usb_power_off,
+        .pre_setup      = ehci_init_internal_buffer,
+};
+
+static struct resource ehci0_resources[] = {
+        [0] = {
+                .start  = 0xffe70000,
+                .end    = 0xffe70400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_iid(0x4c),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device ehci0_device = {
+        .name   = "ehci-platform",
+        .id     = 0,
+        .dev    = {
+                .dma_mask               = &ehci0_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &ehcix_pdata,
+        },
+        .num_resources  = ARRAY_SIZE(ehci0_resources),
+        .resource       = ehci0_resources,
+};
+
+static struct resource ehci1_resources[] = {
+        [0] = {
+                .start  = 0xfff70000,
+                .end    = 0xfff70400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_iid(0x4d),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device ehci1_device = {
+        .name   = "ehci-platform",
+        .id     = 1,
+        .dev    = {
+                .dma_mask               = &ehci1_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &ehcix_pdata,
+        },
+        .num_resources  = ARRAY_SIZE(ehci1_resources),
+        .resource       = ehci1_resources,
+};
+
+static struct usb_ohci_pdata ohcix_pdata = {
+        .power_on       = usb_power_on,
+        .power_off      = usb_power_off,
+        .power_suspend  = usb_power_off,
+};
+
+static struct resource ohci0_resources[] = {
+        [0] = {
+                .start  = 0xffe70400,
+                .end    = 0xffe70800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_iid(0x4c),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device ohci0_device = {
+        .name   = "ohci-platform",
+        .id     = 0,
+        .dev    = {
+                .dma_mask               = &ohci0_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &ohcix_pdata,
+        },
+        .num_resources  = ARRAY_SIZE(ohci0_resources),
+        .resource       = ohci0_resources,
+};
+
+static struct resource ohci1_resources[] = {
+        [0] = {
+                .start  = 0xfff70400,
+                .end    = 0xfff70800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_iid(0x4d),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device ohci1_device = {
+        .name   = "ohci-platform",
+        .id     = 1,
+        .dev    = {
+                .dma_mask               = &ohci1_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &ohcix_pdata,
+        },
+        .num_resources  = ARRAY_SIZE(ohci1_resources),
+        .resource       = ohci1_resources,
+};
+
 /* Ether */
 static struct resource ether_resources[] = {
         {
@@ -417,7 +570,7 @@ static struct platform_device *r8a7779_devices_dt[] __initdata = {
         &tmu01_device,
 };
 
-static struct platform_device *r8a7779_late_devices[] __initdata = {
+static struct platform_device *r8a7779_standard_devices[] __initdata = {
         &i2c0_device,
         &i2c1_device,
         &i2c2_device,
@@ -437,18 +590,26 @@ void __init r8a7779_add_standard_devices(void)
 
         platform_add_devices(r8a7779_devices_dt,
                             ARRAY_SIZE(r8a7779_devices_dt));
-        platform_add_devices(r8a7779_late_devices,
-                            ARRAY_SIZE(r8a7779_late_devices));
+        platform_add_devices(r8a7779_standard_devices,
+                            ARRAY_SIZE(r8a7779_standard_devices));
 }
 
 void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata)
 {
-        platform_device_register_resndata(&platform_bus, "sh_eth", -1,
+        platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1,
                                           ether_resources,
                                           ARRAY_SIZE(ether_resources),
                                           pdata, sizeof(*pdata));
 }
 
+void __init r8a7779_add_usb_phy_device(struct rcar_phy_platform_data *pdata)
+{
+        platform_device_register_resndata(&platform_bus, "rcar_usb_phy", -1,
+                                          usb_phy_resources,
+                                          ARRAY_SIZE(usb_phy_resources),
+                                          pdata, sizeof(*pdata));
+}
+
 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 void __init __weak r8a7779_register_twd(void) { }
 
@@ -481,6 +642,23 @@ void __init r8a7779_add_early_devices(void)
          */
 }
 
+static struct platform_device *r8a7779_late_devices[] __initdata = {
+        &ehci0_device,
+        &ehci1_device,
+        &ohci0_device,
+        &ohci1_device,
+};
+
+void __init r8a7779_init_late(void)
+{
+        /* get USB PHY */
+        phy = usb_get_phy(USB_PHY_TYPE_USB2);
+
+        shmobile_init_late();
+        platform_add_devices(r8a7779_late_devices,
+                             ARRAY_SIZE(r8a7779_late_devices));
+}
+
 #ifdef CONFIG_USE_OF
 void __init r8a7779_init_delay(void)
 {
@@ -514,6 +692,7 @@ DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
         .init_irq       = r8a7779_init_irq_dt,
         .init_machine   = r8a7779_add_standard_devices_dt,
         .init_time      = shmobile_timer_init,
+        .init_late      = r8a7779_init_late,
         .dt_compat      = r8a7779_compat_dt,
 MACHINE_END
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 49de2d56f86d..b461d93431ed 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -23,6 +23,7 @@
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/serial_sci.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/irq-renesas-irqc.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
@@ -31,13 +32,46 @@
 
 static const struct resource pfc_resources[] = {
         DEFINE_RES_MEM(0xe6060000, 0x250),
-        DEFINE_RES_MEM(0xe6050000, 0x5050),
 };
 
+#define R8A7790_GPIO(idx)                                               \
+static struct resource r8a7790_gpio##idx##_resources[] = {              \
+        DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50),              \
+        DEFINE_RES_IRQ(gic_spi(4 + (idx))),                             \
+};                                                                      \
+                                                                        \
+static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data = {    \
+        .gpio_base      = 32 * (idx),                                   \
+        .irq_base       = 0,                                            \
+        .number_of_pins = 32,                                           \
+        .pctl_name      = "pfc-r8a7790",                                \
+        .has_both_edge_trigger = 1,                                     \
+};                                                                      \
+
+R8A7790_GPIO(0);
+R8A7790_GPIO(1);
+R8A7790_GPIO(2);
+R8A7790_GPIO(3);
+R8A7790_GPIO(4);
+R8A7790_GPIO(5);
+
+#define r8a7790_register_gpio(idx)                                      \
+        platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
+                r8a7790_gpio##idx##_resources,                          \
+                ARRAY_SIZE(r8a7790_gpio##idx##_resources),              \
+                &r8a7790_gpio##idx##_platform_data,                     \
+                sizeof(r8a7790_gpio##idx##_platform_data))
+
 void __init r8a7790_pinmux_init(void)
 {
         platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
                                         ARRAY_SIZE(pfc_resources));
+        r8a7790_register_gpio(0);
+        r8a7790_register_gpio(1);
+        r8a7790_register_gpio(2);
+        r8a7790_register_gpio(3);
+        r8a7790_register_gpio(4);
+        r8a7790_register_gpio(5);
 }
 
 #define SCIF_COMMON(scif_type, baseaddr, irq)                   \
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index fdf3894b1cc3..96e7ca1e4e11 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -252,7 +252,7 @@ static struct sh_timer_config cmt10_platform_data = {
         .name = "CMT10",
         .channel_offset = 0x10,
         .timer_bit = 0,
-        .clockevent_rating = 125,
+        .clockevent_rating = 80,
         .clocksource_rating = 125,
 };
 
@@ -288,12 +288,7 @@ static struct sh_timer_config tmu00_platform_data = {
 };
 
 static struct resource tmu00_resources[] = {
-        [0] = {
-                .name   = "TMU00",
-                .start  = 0xfff60008,
-                .end    = 0xfff60013,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xfff60008, 0xc, "TMU00"),
         [1] = {
                 .start  = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
                 .flags  = IORESOURCE_IRQ,
@@ -318,12 +313,7 @@ static struct sh_timer_config tmu01_platform_data = {
 };
 
 static struct resource tmu01_resources[] = {
-        [0] = {
-                .name   = "TMU01",
-                .start  = 0xfff60014,
-                .end    = 0xfff6001f,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xfff60014, 0xc, "TMU00"),
         [1] = {
                 .start  = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
                 .flags  = IORESOURCE_IRQ,
@@ -341,12 +331,7 @@ static struct platform_device tmu01_device = {
 };
 
 static struct resource i2c0_resources[] = {
-        [0] = {
-                .name   = "IIC0",
-                .start  = 0xe6820000,
-                .end    = 0xe6820425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xe6820000, 0x426, "IIC0"),
         [1] = {
                 .start  = gic_spi(167),
                 .end    = gic_spi(170),
@@ -355,12 +340,7 @@ static struct resource i2c0_resources[] = {
 };
 
 static struct resource i2c1_resources[] = {
-        [0] = {
-                .name   = "IIC1",
-                .start  = 0xe6822000,
-                .end    = 0xe6822425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xe6822000, 0x426, "IIC1"),
         [1] = {
                 .start  = gic_spi(51),
                 .end    = gic_spi(54),
@@ -369,12 +349,7 @@ static struct resource i2c1_resources[] = {
 };
 
 static struct resource i2c2_resources[] = {
-        [0] = {
-                .name   = "IIC2",
-                .start  = 0xe6824000,
-                .end    = 0xe6824425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xe6824000, 0x426, "IIC2"),
         [1] = {
                 .start  = gic_spi(171),
                 .end    = gic_spi(174),
@@ -383,12 +358,7 @@ static struct resource i2c2_resources[] = {
 };
 
 static struct resource i2c3_resources[] = {
-        [0] = {
-                .name   = "IIC3",
-                .start  = 0xe6826000,
-                .end    = 0xe6826425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xe6826000, 0x426, "IIC3"),
         [1] = {
                 .start  = gic_spi(183),
                 .end    = gic_spi(186),
@@ -397,12 +367,7 @@ static struct resource i2c3_resources[] = {
 };
 
 static struct resource i2c4_resources[] = {
-        [0] = {
-                .name   = "IIC4",
-                .start  = 0xe6828000,
-                .end    = 0xe6828425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xe6828000, 0x426, "IIC4"),
         [1] = {
                 .start  = gic_spi(187),
                 .end    = gic_spi(190),
@@ -623,12 +588,7 @@ static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
 };
 
 static struct resource sh73a0_dmae_resources[] = {
-        {
-                /* Registers including DMAOR and channels including DMARSx */
-                .start  = 0xfe000020,
-                .end    = 0xfe008a00 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        DEFINE_RES_MEM(0xfe000020, 0x89e0),
         {
                 .name   = "error_irq",
                 .start  = gic_spi(129),
@@ -727,18 +687,10 @@ static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
 
 /* Resource order important! */
 static struct resource sh73a0_mpdma_resources[] = {
-        {
-                /* Channel registers and DMAOR */
-                .start  = 0xec618020,
-                .end    = 0xec61828f,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                /* DMARSx */
-                .start  = 0xec619000,
-                .end    = 0xec61900b,
-                .flags  = IORESOURCE_MEM,
-        },
+        /* Channel registers and DMAOR */
+        DEFINE_RES_MEM(0xec618020, 0x270),
+        /* DMARSx */
+        DEFINE_RES_MEM(0xec619000, 0xc),
         {
                 .name   = "error_irq",
                 .start  = gic_spi(181),
@@ -785,12 +737,7 @@ static struct platform_device pmu_device = {
 
 /* an IPMMU module for ICB */
 static struct resource ipmmu_resources[] = {
-        [0] = {
-                .name   = "IPMMU",
-                .start  = 0xfe951000,
-                .end    = 0xfe9510ff,
-                .flags  = IORESOURCE_MEM,
-        },
+        DEFINE_RES_MEM_NAMED(0xfe951000, 0x100, "IPMMU"),
 };
 
 static const char * const ipmmu_dev_names[] = {
@@ -982,11 +929,17 @@ void __init sh73a0_add_standard_devices(void)
                             ARRAY_SIZE(sh73a0_late_devices));
 }
 
+void __init sh73a0_init_delay(void)
+{
+        shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
+}
+
 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 void __init __weak sh73a0_register_twd(void) { }
 
 void __init sh73a0_earlytimer_init(void)
 {
+        sh73a0_init_delay();
         sh73a0_clock_init();
         shmobile_earlytimer_init();
         sh73a0_register_twd();
@@ -1005,17 +958,14 @@ void __init sh73a0_add_early_devices(void)
 
 #ifdef CONFIG_USE_OF
 
-void __init sh73a0_init_delay(void)
-{
-        shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
-}
-
 static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
         {},
 };
 
 void __init sh73a0_add_standard_devices_dt(void)
 {
+        struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, };
+
         /* clocks are setup late during boot in the case of DT */
         sh73a0_clock_init();
 
@@ -1023,6 +973,9 @@ void __init sh73a0_add_standard_devices_dt(void)
                              ARRAY_SIZE(sh73a0_devices_dt));
         of_platform_populate(NULL, of_default_bus_match_table,
                              sh73a0_auxdata_lookup, NULL);
+
+        /* Instantiate cpufreq-cpu0 */
+        platform_device_register_full(&devinfo);
 }
 
 static const char *sh73a0_boards_compat_dt[] __initdata = {
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index a279fb315069..dd86db467521 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -12,5 +12,6 @@ config ARCH_SOCFPGA
         select GPIO_PL061 if GPIOLIB
         select HAVE_ARM_SCU
         select HAVE_SMP
+        select MFD_SYSCON
         select SPARSE_IRQ
         select USE_OF
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 706ce35396b8..a42d8743ba7f 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -14,7 +14,6 @@
 #include <linux/delay.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/irqchip.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
@@ -110,6 +109,7 @@ static void __init sunxi_dt_init(void)
 
 static const char * const sunxi_board_dt_compat[] = {
         "allwinner,sun4i-a10",
+        "allwinner,sun5i-a10s",
         "allwinner,sun5i-a13",
         NULL,
 };
@@ -117,7 +117,6 @@ static const char * const sunxi_board_dt_compat[] = {
 DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
         .init_machine   = sunxi_dt_init,
         .map_io         = sunxi_map_io,
-        .init_irq       = irqchip_init,
         .init_time      = sunxi_timer_init,
         .dt_compat      = sunxi_board_dt_compat,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index d011f0ad49c4..98b184efc110 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
 
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += tegra114_speedo.o
+obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += sleep-tegra30.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += cpuidle-tegra114.o
 endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 9f852c6fe5b9..ec5836b1e713 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -29,6 +29,7 @@
 
 #include "board.h"
 #include "common.h"
+#include "cpuidle.h"
 #include "fuse.h"
 #include "iomap.h"
 #include "irq.h"
@@ -108,5 +109,6 @@ void __init tegra_init_early(void)
 void __init tegra_init_late(void)
 {
         tegra_init_suspend();
+        tegra_cpuidle_init();
         tegra_powergate_debugfs_init();
 }
diff --git a/arch/arm/mach-tegra/common.h b/arch/arm/mach-tegra/common.h
index 5900cc44f780..32f8eb3fe344 100644
--- a/arch/arm/mach-tegra/common.h
+++ b/arch/arm/mach-tegra/common.h
@@ -2,3 +2,4 @@ extern struct smp_operations tegra_smp_ops;
 
 extern int tegra_cpu_kill(unsigned int cpu);
 extern void tegra_cpu_die(unsigned int cpu);
+extern int tegra_cpu_disable(unsigned int cpu);
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index 0cdba8de8c77..706aa4215c36 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -177,7 +177,6 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
                                     struct cpuidle_driver *drv,
                                     int index)
 {
-        u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
         bool entered_lp2 = false;
 
         if (tegra_pending_sgi())
@@ -193,16 +192,16 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
 
         local_fiq_disable();
 
-        tegra_set_cpu_in_lp2(cpu);
+        tegra_set_cpu_in_lp2();
         cpu_pm_enter();
 
-        if (cpu == 0)
+        if (dev->cpu == 0)
                 entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index);
         else
                 entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
 
         cpu_pm_exit();
-        tegra_clear_cpu_in_lp2(cpu);
+        tegra_clear_cpu_in_lp2();
 
         local_fiq_enable();
 
@@ -214,8 +213,5 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
 
 int __init tegra20_cpuidle_init(void)
 {
-#ifdef CONFIG_PM_SLEEP
-        tegra_tear_down_cpu = tegra20_tear_down_cpu;
-#endif
         return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);
 }
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 3cf9aca5f3ea..ed2a2a7bae4d 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -114,16 +114,15 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev,
                             struct cpuidle_driver *drv,
                             int index)
 {
-        u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
         bool entered_lp2 = false;
         bool last_cpu;
 
         local_fiq_disable();
 
-        last_cpu = tegra_set_cpu_in_lp2(cpu);
+        last_cpu = tegra_set_cpu_in_lp2();
         cpu_pm_enter();
 
-        if (cpu == 0) {
+        if (dev->cpu == 0) {
                 if (last_cpu)
                         entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
                                                                      index);
@@ -134,7 +133,7 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev,
         }
 
         cpu_pm_exit();
-        tegra_clear_cpu_in_lp2(cpu);
+        tegra_clear_cpu_in_lp2();
 
         local_fiq_enable();
 
@@ -146,8 +145,5 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev,
 
 int __init tegra30_cpuidle_init(void)
 {
-#ifdef CONFIG_PM_SLEEP
-        tegra_tear_down_cpu = tegra30_tear_down_cpu;
-#endif
         return cpuidle_register(&tegra_idle_driver, NULL);
 }
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index 4b744c4661e2..e85973cef037 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -27,25 +27,20 @@
 #include "fuse.h"
 #include "cpuidle.h"
 
-static int __init tegra_cpuidle_init(void)
+void __init tegra_cpuidle_init(void)
 {
-        int ret;
-
         switch (tegra_chip_id) {
         case TEGRA20:
-                ret = tegra20_cpuidle_init();
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
+                        tegra20_cpuidle_init();
                 break;
         case TEGRA30:
-                ret = tegra30_cpuidle_init();
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))
+                        tegra30_cpuidle_init();
                 break;
         case TEGRA114:
-                ret = tegra114_cpuidle_init();
-                break;
-        default:
-                ret = -ENODEV;
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+                        tegra114_cpuidle_init();
                 break;
         }
-
-        return ret;
 }
-device_initcall(tegra_cpuidle_init);
diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h
index d733f75d0208..9ec2c1ab0fa4 100644
--- a/arch/arm/mach-tegra/cpuidle.h
+++ b/arch/arm/mach-tegra/cpuidle.h
@@ -17,22 +17,13 @@
 #ifndef __MACH_TEGRA_CPUIDLE_H
 #define __MACH_TEGRA_CPUIDLE_H
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+#ifdef CONFIG_CPU_IDLE
 int tegra20_cpuidle_init(void);
-#else
-static inline int tegra20_cpuidle_init(void) { return -ENODEV; }
-#endif
-
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
 int tegra30_cpuidle_init(void);
-#else
-static inline int tegra30_cpuidle_init(void) { return -ENODEV; }
-#endif
-
-#ifdef CONFIG_ARCH_TEGRA_114_SOC
 int tegra114_cpuidle_init(void);
+void tegra_cpuidle_init(void);
 #else
-static inline int tegra114_cpuidle_init(void) { return -ENODEV; }
+static inline void tegra_cpuidle_init(void) {}
 #endif
 
 #endif
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index 67eab56699bd..7a29bae799a7 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -25,6 +25,7 @@
 #define FLOW_CTRL_WAITEVENT             (2 << 29)
 #define FLOW_CTRL_WAIT_FOR_INTERRUPT    (4 << 29)
 #define FLOW_CTRL_JTAG_RESUME           (1 << 28)
+#define FLOW_CTRL_SCLK_RESUME           (1 << 27)
 #define FLOW_CTRL_HALT_CPU_IRQ          (1 << 10)
 #define FLOW_CTRL_HALT_CPU_FIQ          (1 << 8)
 #define FLOW_CTRL_CPU0_CSR              0x8
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index aacc00d05980..def79683bef6 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -19,16 +19,6 @@
 #ifndef __MACH_TEGRA_FUSE_H
 #define __MACH_TEGRA_FUSE_H
 
-enum tegra_revision {
-        TEGRA_REVISION_UNKNOWN = 0,
-        TEGRA_REVISION_A01,
-        TEGRA_REVISION_A02,
-        TEGRA_REVISION_A03,
-        TEGRA_REVISION_A03p,
-        TEGRA_REVISION_A04,
-        TEGRA_REVISION_MAX,
-};
-
 #define SKU_ID_T20      8
 #define SKU_ID_T25SE    20
 #define SKU_ID_AP25     23
@@ -40,6 +30,17 @@ enum tegra_revision {
 #define TEGRA30         0x30
 #define TEGRA114        0x35
 
+#ifndef __ASSEMBLY__
+enum tegra_revision {
+        TEGRA_REVISION_UNKNOWN = 0,
+        TEGRA_REVISION_A01,
+        TEGRA_REVISION_A02,
+        TEGRA_REVISION_A03,
+        TEGRA_REVISION_A03p,
+        TEGRA_REVISION_A04,
+        TEGRA_REVISION_MAX,
+};
+
 extern int tegra_sku_id;
 extern int tegra_cpu_process_id;
 extern int tegra_core_process_id;
@@ -72,5 +73,6 @@ void tegra114_init_speedo_data(void);
 #else
 static inline void tegra114_init_speedo_data(void) {}
 #endif
+#endif /* __ASSEMBLY__ */
 
 #endif
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index 184914a68d73..a52c10e0a857 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -46,6 +46,17 @@ void __ref tegra_cpu_die(unsigned int cpu)
         BUG();
 }
 
+int tegra_cpu_disable(unsigned int cpu)
+{
+        switch (tegra_chip_id) {
+        case TEGRA20:
+        case TEGRA30:
+                return cpu == 0 ? -EPERM : 0;
+        default:
+                return 0;
+        }
+}
+
 void __init tegra_hotplug_init(void)
 {
         if (!IS_ENABLED(CONFIG_HOTPLUG_CPU))
@@ -55,4 +66,6 @@ void __init tegra_hotplug_init(void)
                 tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
         if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
                 tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
+                tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
 }
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index fad4226ef710..24db4ac428ae 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -140,8 +140,31 @@ remove_clamps:
 
 static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
+        int ret = 0;
+
         cpu = cpu_logical_map(cpu);
-        return tegra_pmc_cpu_power_on(cpu);
+
+        if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
+                /*
+                 * Warm boot flow
+                 * The flow controller in charge of the power state and
+                 * control for each CPU.
+                 */
+                /* set SCLK as event trigger for flow controller */
+                flowctrl_write_cpu_csr(cpu, 1);
+                flowctrl_write_cpu_halt(cpu,
+                                FLOW_CTRL_WAITEVENT | FLOW_CTRL_SCLK_RESUME);
+        } else {
+                /*
+                 * Cold boot flow
+                 * The CPU is powered up by toggling PMC directly. It will
+                 * also initial power state in flow controller. After that,
+                 * the CPU's power state is maintained by flow controller.
+                 */
+                ret = tegra_pmc_cpu_power_on(cpu);
+        }
+
+        return ret;
 }
 
 static int __cpuinit tegra_boot_secondary(unsigned int cpu,
@@ -173,5 +196,6 @@ struct smp_operations tegra_smp_ops __initdata = {
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_kill               = tegra_cpu_kill,
         .cpu_die                = tegra_cpu_die,
+        .cpu_disable            = tegra_cpu_disable,
 #endif
 };
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 45cf52c7e528..94e69bee3da5 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -44,6 +44,20 @@
 static DEFINE_SPINLOCK(tegra_lp2_lock);
 void (*tegra_tear_down_cpu)(void);
 
+static void tegra_tear_down_cpu_init(void)
+{
+        switch (tegra_chip_id) {
+        case TEGRA20:
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
+                        tegra_tear_down_cpu = tegra20_tear_down_cpu;
+                break;
+        case TEGRA30:
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))
+                        tegra_tear_down_cpu = tegra30_tear_down_cpu;
+                break;
+        }
+}
+
 /*
  * restore_cpu_complex
  *
@@ -91,8 +105,9 @@ static void suspend_cpu_complex(void)
         flowctrl_cpu_suspend_enter(cpu);
 }
 
-void tegra_clear_cpu_in_lp2(int phy_cpu_id)
+void tegra_clear_cpu_in_lp2(void)
 {
+        int phy_cpu_id = cpu_logical_map(smp_processor_id());
         u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
 
         spin_lock(&tegra_lp2_lock);
@@ -103,8 +118,9 @@ void tegra_clear_cpu_in_lp2(int phy_cpu_id)
         spin_unlock(&tegra_lp2_lock);
 }
 
-bool tegra_set_cpu_in_lp2(int phy_cpu_id)
+bool tegra_set_cpu_in_lp2(void)
 {
+        int phy_cpu_id = cpu_logical_map(smp_processor_id());
         bool last_cpu = false;
         cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
         u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
@@ -192,7 +208,7 @@ static int __cpuinit tegra_suspend_enter(suspend_state_t state)
         suspend_cpu_complex();
         switch (mode) {
         case TEGRA_SUSPEND_LP2:
-                tegra_set_cpu_in_lp2(0);
+                tegra_set_cpu_in_lp2();
                 break;
         default:
                 break;
@@ -202,7 +218,7 @@ static int __cpuinit tegra_suspend_enter(suspend_state_t state)
 
         switch (mode) {
         case TEGRA_SUSPEND_LP2:
-                tegra_clear_cpu_in_lp2(0);
+                tegra_clear_cpu_in_lp2();
                 break;
         default:
                 break;
@@ -224,6 +240,7 @@ void __init tegra_init_suspend(void)
         if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE)
                 return;
 
+        tegra_tear_down_cpu_init();
         tegra_pmc_suspend_init();
 
         suspend_set_ops(&tegra_suspend_ops);
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index 778a4aa7c3fa..94c4b9d9077c 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -28,8 +28,8 @@ extern unsigned long l2x0_saved_regs_addr;
 void save_cpu_arch_register(void);
 void restore_cpu_arch_register(void);
 
-void tegra_clear_cpu_in_lp2(int phy_cpu_id);
-bool tegra_set_cpu_in_lp2(int phy_cpu_id);
+void tegra_clear_cpu_in_lp2(void);
+bool tegra_set_cpu_in_lp2(void);
 
 void tegra_idle_lp2_last(void);
 extern void (*tegra_tear_down_cpu)(void);
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index e6de88a2ea06..39dc9e7834f3 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -22,11 +22,11 @@
 #include <asm/hardware/cache-l2x0.h>
 
 #include "flowctrl.h"
+#include "fuse.h"
 #include "iomap.h"
 #include "reset.h"
 #include "sleep.h"
 
-#define APB_MISC_GP_HIDREV      0x804
 #define PMC_SCRATCH41   0x140
 
 #define RESET_DATA(x)   ((TEGRA_RESET_##x)*4)
@@ -38,34 +38,40 @@
  *        CPU boot vector when restarting the a CPU following
  *        an LP2 transition. Also branched to by LP0 and LP1 resume after
  *        re-enabling sdram.
+ *
+ *      r6: SoC ID
  */
 ENTRY(tegra_resume)
         bl      v7_invalidate_l1
 
         cpu_id  r0
+        tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
+        cmp     r6, #TEGRA114
+        beq     no_cpu0_chk
+
         cmp     r0, #0                          @ CPU0?
  THUMB( it      ne )
         bne     cpu_resume                      @ no
+no_cpu0_chk:
 
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
         /* Are we on Tegra20? */
-        mov32   r6, TEGRA_APB_MISC_BASE
-        ldr     r0, [r6, #APB_MISC_GP_HIDREV]
-        and     r0, r0, #0xff00
-        cmp     r0, #(0x20 << 8)
+        cmp     r6, #TEGRA20
         beq     1f                              @ Yes
         /* Clear the flow controller flags for this CPU. */
-        mov32   r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR   @ CPU0 CSR
-        ldr     r1, [r2]
+        cpu_to_csr_reg r1, r0
+        mov32   r2, TEGRA_FLOW_CTRL_BASE
+        ldr     r1, [r2, r1]
         /* Clear event & intr flag */
         orr     r1, r1, \
                 #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
-        movw    r0, #0x0FFD     @ enable, cluster_switch, immed, & bitmaps
+        movw    r0, #0x3FFD     @ enable, cluster_switch, immed, bitmaps
+                                @ & ext flags for CPU power mgnt
         bic     r1, r1, r0
         str     r1, [r2]
 1:
-#endif
 
+        check_cpu_part_num 0xc09, r8, r9
+        bne     not_ca9
 #ifdef CONFIG_HAVE_ARM_SCU
         /* enable SCU */
         mov32   r0, TEGRA_ARM_PERIF_BASE
@@ -76,6 +82,7 @@ ENTRY(tegra_resume)
 
         /* L2 cache resume & re-enable */
         l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
+not_ca9:
 
         b       cpu_resume
 ENDPROC(tegra_resume)
@@ -98,7 +105,7 @@ ENTRY(__tegra_cpu_reset_handler_start)
  * Register usage within the reset handler:
  *
  *      Others: scratch
- *      R6  = SoC ID << 8
+ *      R6  = SoC ID
  *      R7  = CPU present (to the OS) mask
  *      R8  = CPU in LP1 state mask
  *      R9  = CPU in LP2 state mask
@@ -115,12 +122,10 @@ ENTRY(__tegra_cpu_reset_handler)
 
         cpsid   aif, 0x13                       @ SVC mode, interrupts disabled
 
-        mov32   r6, TEGRA_APB_MISC_BASE
-        ldr     r6, [r6, #APB_MISC_GP_HIDREV]
-        and     r6, r6, #0xff00
+        tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 t20_check:
-        cmp     r6, #(0x20 << 8)
+        cmp     r6, #TEGRA20
         bne     after_t20_check
 t20_errata:
         # Tegra20 is a Cortex-A9 r1p1
@@ -136,7 +141,7 @@ after_t20_check:
 #endif
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 t30_check:
-        cmp     r6, #(0x30 << 8)
+        cmp     r6, #TEGRA30
         bne     after_t30_check
 t30_errata:
         # Tegra30 is a Cortex-A9 r2p9
@@ -163,7 +168,7 @@ after_errata:
 
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
         /* Are we on Tegra20? */
-        cmp     r6, #(0x20 << 8)
+        cmp     r6, #TEGRA20
         bne     1f
         /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
         mov32   r5, TEGRA_PMC_BASE
@@ -186,11 +191,14 @@ __is_not_lp2:
 
 #ifdef CONFIG_SMP
         /*
-         * Can only be secondary boot (initial or hotplug) but CPU 0
-         * cannot be here.
+         * Can only be secondary boot (initial or hotplug)
+         * CPU0 can't be here for Tegra20/30
          */
+        cmp     r6, #TEGRA114
+        beq     __no_cpu0_chk
         cmp     r10, #0
         bleq    __die                           @ CPU0 cannot be here
+__no_cpu0_chk:
         ldr     lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
         cmp     lr, #0
         bleq    __die                           @ no secondary startup handler
@@ -210,10 +218,7 @@ __die:
         mov32   r7, TEGRA_CLK_RESET_BASE
 
         /* Are we on Tegra20? */
-        mov32   r6, TEGRA_APB_MISC_BASE
-        ldr     r0, [r6, #APB_MISC_GP_HIDREV]
-        and     r0, r0, #0xff00
-        cmp     r0, #(0x20 << 8)
+        cmp     r6, #TEGRA20
         bne     1f
 
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index d29dfcce948d..ada8821b48be 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -19,6 +19,7 @@
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 
+#include "fuse.h"
 #include "sleep.h"
 #include "flowctrl.h"
 
@@ -43,14 +44,19 @@ ENDPROC(tegra30_hotplug_shutdown)
  *
  * Puts the current CPU in wait-for-event mode on the flow controller
  * and powergates it -- flags (in R0) indicate the request type.
- * Must never be called for CPU 0.
  *
- * corrupts r0-r4, r12
+ * r10 = SoC ID
+ * corrupts r0-r4, r10-r12
  */
 ENTRY(tegra30_cpu_shutdown)
         cpu_id  r3
+        tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10
+        cmp     r10, #TEGRA30
+        bne     _no_cpu0_chk    @ It's not Tegra30
+
         cmp     r3, #0
         moveq   pc, lr          @ Must never be called for CPU 0
+_no_cpu0_chk:
 
         ldr     r12, =TEGRA_FLOW_CTRL_VIRT
         cpu_to_csr_reg r1, r3
@@ -65,7 +71,9 @@ ENTRY(tegra30_cpu_shutdown)
         movw    r12, \
                 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
                 FLOW_CTRL_CSR_ENABLE
-        mov     r4, #(1 << 4)
+        cmp     r10, #TEGRA30
+        moveq   r4, #(1 << 4)                   @ wfe bitmap
+        movne   r4, #(1 << 8)                   @ wfi bitmap
  ARM(   orr     r12, r12, r4, lsl r3    )
  THUMB( lsl     r4, r4, r3              )
  THUMB( orr     r12, r12, r4            )
@@ -79,9 +87,20 @@ delay_1:
         cpsid   a                               @ disable imprecise aborts.
         ldr     r3, [r1]                        @ read CSR
         str     r3, [r1]                        @ clear CSR
+
         tst     r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+        beq     flow_ctrl_setting_for_lp2
+
+        /* flow controller set up for hotplug */
+        mov     r3, #FLOW_CTRL_WAITEVENT                @ For hotplug
+        b       flow_ctrl_done
+flow_ctrl_setting_for_lp2:
+        /* flow controller set up for LP2 */
+        cmp     r10, #TEGRA30
         moveq   r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT       @ For LP2
-        movne   r3, #FLOW_CTRL_WAITEVENT                @ For hotplug
+        movne   r3, #FLOW_CTRL_WAITEVENT
+flow_ctrl_done:
+        cmp     r10, #TEGRA30
         str     r3, [r2]
         ldr     r0, [r2]
         b       wfe_war
@@ -89,7 +108,8 @@ delay_1:
 __cpu_reset_again:
         dsb
         .align 5
-        wfe                                     @ CPU should be power gated here
+        wfeeq                                   @ CPU should be power gated here
+        wfine
 wfe_war:
         b       __cpu_reset_again
 
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 364d84523fba..9daaef26b0f6 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -106,9 +106,11 @@ ENTRY(tegra_shut_off_mmu)
         isb
 #ifdef CONFIG_CACHE_L2X0
         /* Disable L2 cache */
-        mov32   r4, TEGRA_ARM_PERIF_BASE + 0x3000
-        mov     r5, #0
-        str     r5, [r4, #L2X0_CTRL]
+        check_cpu_part_num 0xc09, r9, r10
+        movweq  r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
+        movteq  r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
+        moveq   r5, #0
+        streq   r5, [r4, #L2X0_CTRL]
 #endif
         mov     pc, r0
 ENDPROC(tegra_shut_off_mmu)
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 2080fb12ce26..98b7da698f2b 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -25,6 +25,8 @@
                                         + IO_PPSB_VIRT)
 #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
                                         + IO_PPSB_VIRT)
+#define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \
+                                        + IO_APB_VIRT)
 #define TEGRA_PMC_VIRT  (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
 
 /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
@@ -70,19 +72,40 @@
         movt    \reg, #:upper16:\val
 .endm
 
+/* Marco to check CPU part num */
+.macro check_cpu_part_num part_num, tmp1, tmp2
+        mrc     p15, 0, \tmp1, c0, c0, 0
+        ubfx    \tmp1, \tmp1, #4, #12
+        mov32   \tmp2, \part_num
+        cmp     \tmp1, \tmp2
+.endm
+
 /* Macro to exit SMP coherency. */
 .macro exit_smp, tmp1, tmp2
         mrc     p15, 0, \tmp1, c1, c0, 1        @ ACTLR
         bic     \tmp1, \tmp1, #(1<<6) | (1<<0)  @ clear ACTLR.SMP | ACTLR.FW
         mcr     p15, 0, \tmp1, c1, c0, 1        @ ACTLR
         isb
-        cpu_id  \tmp1
-        mov     \tmp1, \tmp1, lsl #2
-        mov     \tmp2, #0xf
-        mov     \tmp2, \tmp2, lsl \tmp1
-        mov32   \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC
-        str     \tmp2, [\tmp1]                  @ invalidate SCU tags for CPU
+#ifdef CONFIG_HAVE_ARM_SCU
+        check_cpu_part_num 0xc09, \tmp1, \tmp2
+        mrceq   p15, 0, \tmp1, c0, c0, 5
+        andeq   \tmp1, \tmp1, #0xF
+        moveq   \tmp1, \tmp1, lsl #2
+        moveq   \tmp2, #0xf
+        moveq   \tmp2, \tmp2, lsl \tmp1
+        ldreq   \tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC)
+        streq   \tmp2, [\tmp1]                  @ invalidate SCU tags for CPU
         dsb
+#endif
+.endm
+
+/* Macro to check Tegra revision */
+#define APB_MISC_GP_HIDREV      0x804
+.macro tegra_get_soc_id base, tmp1
+        mov32   \tmp1, \base
+        ldr     \tmp1, [\tmp1, #APB_MISC_GP_HIDREV]
+        and     \tmp1, \tmp1, #0xff00
+        mov     \tmp1, \tmp1, lsr #8
 .endm
 
 /* Macro to resume & re-enable L2 cache */
diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c
index 31e69a019bdd..3ae4a7f1a2fb 100644
--- a/arch/arm/mach-tegra/tegra2_emc.c
+++ b/arch/arm/mach-tegra/tegra2_emc.c
@@ -183,7 +183,7 @@ static struct device_node *tegra_emc_ramcode_devnode(struct device_node *np)
         u32 reg;
 
         for_each_child_of_node(np, iter) {
-                if (of_property_read_u32(np, "nvidia,ram-code", &reg))
+                if (of_property_read_u32(iter, "nvidia,ram-code", &reg))
                         continue;
                 if (reg == tegra_bct_strapping)
                         return of_node_get(iter);
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index 1f597647d431..a85adcd00882 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -1,24 +1,46 @@
-if ARCH_U300
-
 menu "ST-Ericsson AB U300/U335 Platform"
 
 comment "ST-Ericsson Mobile Platform Products"
 
-config MACH_U300
-        bool "U300"
+config ARCH_U300
+        bool "ST-Ericsson U300 Series" if ARCH_MULTI_V5
+        depends on MMU
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_AMBA
+        select ARM_PATCH_PHYS_VIRT
+        select ARM_VIC
+        select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
+        select CLKSRC_OF
+        select COMMON_CLK
+        select CPU_ARM926T
+        select GENERIC_CLOCKEVENTS
+        select HAVE_TCM
         select PINCTRL
         select PINCTRL_COH901
         select PINCTRL_U300
+        select SPARSE_IRQ
+        select MFD_SYSCON
+        select USE_OF
+        help
+          Support for ST-Ericsson U300 series mobile platforms.
 
 comment "ST-Ericsson U300/U335 Feature Selections"
 
+config MACH_U300
+        depends on ARCH_U300
+        bool "U300"
+        default y
+
 config U300_DEBUG
+        depends on ARCH_U300
         bool "Debug support for U300"
         depends on PM
         help
                 Debug support for U300 in sysfs, procfs etc.
 
 config MACH_U300_SPIDUMMY
+        depends on ARCH_U300
         bool "SSP/SPI dummy chip"
         select SPI
         select SPI_MASTER
@@ -31,5 +53,3 @@ config MACH_U300_SPIDUMMY
                 SPI framework and ARM PL022 support.
 
 endmenu
-
-endif
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index 5a86c58da396..0f362b64fb87 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -7,7 +7,5 @@ obj-m		:=
 obj-n           :=
 obj-            :=
 
-obj-$(CONFIG_SPI_PL022)           += spi.o
 obj-$(CONFIG_MACH_U300_SPIDUMMY)  += dummyspichip.o
-obj-$(CONFIG_I2C_STU300)          += i2c.o
 obj-$(CONFIG_REGULATOR_AB3100)    += regulator.o
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index a683d17b2ce4..4f7ac2a11452 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -9,46 +9,157 @@
  * Author: Linus Walleij <linus.walleij@stericsson.com>
  */
 #include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/bitops.h>
-#include <linux/device.h>
-#include <linux/mm.h>
-#include <linux/termios.h>
-#include <linux/dmaengine.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/mmci.h>
-#include <linux/amba/serial.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/fsmc.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinconf-generic.h>
-#include <linux/dma-mapping.h>
 #include <linux/platform_data/clk-u300.h>
-#include <linux/platform_data/pinctrl-coh901.h>
-#include <linux/platform_data/dma-coh901318.h>
-#include <linux/irqchip/arm-vic.h>
+#include <linux/irqchip.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/clocksource.h>
+#include <linux/clk.h>
 
-#include <asm/types.h>
-#include <asm/setup.h>
-#include <asm/memory.h>
 #include <asm/mach/map.h>
-#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/hardware.h>
-#include <mach/syscon.h>
-#include <mach/irqs.h>
+/*
+ * These are the large blocks of memory allocated for I/O.
+ * the defines are used for setting up the I/O memory mapping.
+ */
+
+/* NAND Flash CS0 */
+#define U300_NAND_CS0_PHYS_BASE         0x80000000
+/* NFIF */
+#define U300_NAND_IF_PHYS_BASE          0x9f800000
+/* ALE, CLE offset for FSMC NAND */
+#define PLAT_NAND_CLE                   (1 << 16)
+#define PLAT_NAND_ALE                   (1 << 17)
+/* AHB Peripherals */
+#define U300_AHB_PER_PHYS_BASE          0xa0000000
+#define U300_AHB_PER_VIRT_BASE          0xff010000
+/* FAST Peripherals */
+#define U300_FAST_PER_PHYS_BASE         0xc0000000
+#define U300_FAST_PER_VIRT_BASE         0xff020000
+/* SLOW Peripherals */
+#define U300_SLOW_PER_PHYS_BASE         0xc0010000
+#define U300_SLOW_PER_VIRT_BASE         0xff000000
+/* Boot ROM */
+#define U300_BOOTROM_PHYS_BASE          0xffff0000
+#define U300_BOOTROM_VIRT_BASE          0xffff0000
+/* SEMI config base */
+#define U300_SEMI_CONFIG_BASE           0x2FFE0000
+
+/*
+ * AHB peripherals
+ */
+
+/* AHB Peripherals Bridge Controller */
+#define U300_AHB_BRIDGE_BASE            (U300_AHB_PER_PHYS_BASE+0x0000)
+/* Vectored Interrupt Controller 0, servicing 32 interrupts */
+#define U300_INTCON0_BASE               (U300_AHB_PER_PHYS_BASE+0x1000)
+#define U300_INTCON0_VBASE              IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
+/* Vectored Interrupt Controller 1, servicing 32 interrupts */
+#define U300_INTCON1_BASE               (U300_AHB_PER_PHYS_BASE+0x2000)
+#define U300_INTCON1_VBASE              IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
+/* Memory Stick Pro (MSPRO) controller */
+#define U300_MSPRO_BASE                 (U300_AHB_PER_PHYS_BASE+0x3000)
+/* EMIF Configuration Area */
+#define U300_EMIF_CFG_BASE              (U300_AHB_PER_PHYS_BASE+0x4000)
+
+/*
+ * FAST peripherals
+ */
+
+/* FAST bridge control */
+#define U300_FAST_BRIDGE_BASE           (U300_FAST_PER_PHYS_BASE+0x0000)
+/* MMC/SD controller */
+#define U300_MMCSD_BASE                 (U300_FAST_PER_PHYS_BASE+0x1000)
+/* PCM I2S0 controller */
+#define U300_PCM_I2S0_BASE              (U300_FAST_PER_PHYS_BASE+0x2000)
+/* PCM I2S1 controller */
+#define U300_PCM_I2S1_BASE              (U300_FAST_PER_PHYS_BASE+0x3000)
+/* I2C0 controller */
+#define U300_I2C0_BASE                  (U300_FAST_PER_PHYS_BASE+0x4000)
+/* I2C1 controller */
+#define U300_I2C1_BASE                  (U300_FAST_PER_PHYS_BASE+0x5000)
+/* SPI controller */
+#define U300_SPI_BASE                   (U300_FAST_PER_PHYS_BASE+0x6000)
+/* Fast UART1 on U335 only */
+#define U300_UART1_BASE                 (U300_FAST_PER_PHYS_BASE+0x7000)
+
+/*
+ * SLOW peripherals
+ */
+
+/* SLOW bridge control */
+#define U300_SLOW_BRIDGE_BASE           (U300_SLOW_PER_PHYS_BASE)
+/* SYSCON */
+#define U300_SYSCON_BASE                (U300_SLOW_PER_PHYS_BASE+0x1000)
+#define U300_SYSCON_VBASE               IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
+/* Watchdog */
+#define U300_WDOG_BASE                  (U300_SLOW_PER_PHYS_BASE+0x2000)
+/* UART0 */
+#define U300_UART0_BASE                 (U300_SLOW_PER_PHYS_BASE+0x3000)
+/* APP side special timer */
+#define U300_TIMER_APP_BASE             (U300_SLOW_PER_PHYS_BASE+0x4000)
+#define U300_TIMER_APP_VBASE            IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
+/* Keypad */
+#define U300_KEYPAD_BASE                (U300_SLOW_PER_PHYS_BASE+0x5000)
+/* GPIO */
+#define U300_GPIO_BASE                  (U300_SLOW_PER_PHYS_BASE+0x6000)
+/* RTC */
+#define U300_RTC_BASE                   (U300_SLOW_PER_PHYS_BASE+0x7000)
+/* Bus tracer */
+#define U300_BUSTR_BASE                 (U300_SLOW_PER_PHYS_BASE+0x8000)
+/* Event handler (hardware queue) */
+#define U300_EVHIST_BASE                (U300_SLOW_PER_PHYS_BASE+0x9000)
+/* Genric Timer */
+#define U300_TIMER_BASE                 (U300_SLOW_PER_PHYS_BASE+0xa000)
+/* PPM */
+#define U300_PPM_BASE                   (U300_SLOW_PER_PHYS_BASE+0xb000)
+
+/*
+ * REST peripherals
+ */
+
+/* ISP (image signal processor) */
+#define U300_ISP_BASE                   (0xA0008000)
+/* DMA Controller base */
+#define U300_DMAC_BASE                  (0xC0020000)
+/* MSL Base */
+#define U300_MSL_BASE                   (0xc0022000)
+/* APEX Base */
+#define U300_APEX_BASE                  (0xc0030000)
+/* Video Encoder Base */
+#define U300_VIDEOENC_BASE              (0xc0080000)
+/* XGAM Base */
+#define U300_XGAM_BASE                  (0xd0000000)
+
+/*
+ * SYSCON addresses applicable to the core machine.
+ */
 
-#include "timer.h"
-#include "spi.h"
-#include "i2c.h"
-#include "u300-gpio.h"
+/* Chip ID register 16bit (R/-) */
+#define U300_SYSCON_CIDR                                        (0x400)
+/* SMCR */
+#define U300_SYSCON_SMCR                                        (0x4d0)
+#define U300_SYSCON_SMCR_FIELD_MASK                             (0x000e)
+#define U300_SYSCON_SMCR_SEMI_SREFACK_IND                       (0x0008)
+#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE                    (0x0004)
+#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE              (0x0002)
+/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
+#define U300_SYSCON_CSDR                                        (0x4f0)
+#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE                        (0x0001)
+/* PRINT_CONTROL Print Control 16bit (R/-) */
+#define U300_SYSCON_PCR                                         (0x4f8)
+#define U300_SYSCON_PCR_SERV_IND                                (0x0001)
+/* BOOT_CONTROL 16bit (R/-) */
+#define U300_SYSCON_BCR                                         (0x4fc)
+#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND              (0x0400)
+#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND              (0x0200)
+#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK                  (0x01FC)
+#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK                      (0x0003)
+
+static void __iomem *syscon_base;
 
 /*
  * Static I/O mappings that are needed for booting the U300 platforms. The
@@ -82,365 +193,6 @@ static void __init u300_map_io(void)
         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
 }
 
-/*
- * Declaration of devices found on the U300 board and
- * their respective memory locations.
- */
-
-static struct amba_pl011_data uart0_plat_data = {
-#ifdef CONFIG_COH901318
-        .dma_filter = coh901318_filter_id,
-        .dma_rx_param = (void *) U300_DMA_UART0_RX,
-        .dma_tx_param = (void *) U300_DMA_UART0_TX,
-#endif
-};
-
-/* Slow device at 0x3000 offset */
-static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
-        { IRQ_U300_UART0 }, &uart0_plat_data);
-
-/* The U335 have an additional UART1 on the APP CPU */
-static struct amba_pl011_data uart1_plat_data = {
-#ifdef CONFIG_COH901318
-        .dma_filter = coh901318_filter_id,
-        .dma_rx_param = (void *) U300_DMA_UART1_RX,
-        .dma_tx_param = (void *) U300_DMA_UART1_TX,
-#endif
-};
-
-/* Fast device at 0x7000 offset */
-static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
-        { IRQ_U300_UART1 }, &uart1_plat_data);
-
-/* AHB device at 0x4000 offset */
-static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
-
-/* Fast device at 0x6000 offset */
-static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE,
-        { IRQ_U300_SPI }, NULL);
-
-/* Fast device at 0x1000 offset */
-#define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }
-
-static struct mmci_platform_data mmcsd_platform_data = {
-        /*
-         * Do not set ocr_mask or voltage translation function,
-         * we have a regulator we can control instead.
-         */
-        .f_max = 24000000,
-        .gpio_wp = -1,
-        .gpio_cd = U300_GPIO_PIN_MMC_CD,
-        .cd_invert = true,
-        .capabilities = MMC_CAP_MMC_HIGHSPEED |
-        MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-#ifdef CONFIG_COH901318
-        .dma_filter = coh901318_filter_id,
-        .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
-        /* Don't specify a TX channel, this RX channel is bidirectional */
-#endif
-};
-
-static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
-        U300_MMCSD_IRQS, &mmcsd_platform_data);
-
-/*
- * The order of device declaration may be important, since some devices
- * have dependencies on other devices being initialized first.
- */
-static struct amba_device *amba_devs[] __initdata = {
-        &uart0_device,
-        &uart1_device,
-        &pl022_device,
-        &pl172_device,
-        &mmcsd_device,
-};
-
-/* Here follows a list of all hw resources that the platform devices
- * allocate. Note, clock dependencies are not included
- */
-
-static struct resource gpio_resources[] = {
-        {
-                .start = U300_GPIO_BASE,
-                .end   = (U300_GPIO_BASE + SZ_4K - 1),
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name  = "gpio0",
-                .start = IRQ_U300_GPIO_PORT0,
-                .end   = IRQ_U300_GPIO_PORT0,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "gpio1",
-                .start = IRQ_U300_GPIO_PORT1,
-                .end   = IRQ_U300_GPIO_PORT1,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "gpio2",
-                .start = IRQ_U300_GPIO_PORT2,
-                .end   = IRQ_U300_GPIO_PORT2,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "gpio3",
-                .start = IRQ_U300_GPIO_PORT3,
-                .end   = IRQ_U300_GPIO_PORT3,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "gpio4",
-                .start = IRQ_U300_GPIO_PORT4,
-                .end   = IRQ_U300_GPIO_PORT4,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "gpio5",
-                .start = IRQ_U300_GPIO_PORT5,
-                .end   = IRQ_U300_GPIO_PORT5,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "gpio6",
-                .start = IRQ_U300_GPIO_PORT6,
-                .end   = IRQ_U300_GPIO_PORT6,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource keypad_resources[] = {
-        {
-                .start = U300_KEYPAD_BASE,
-                .end   = U300_KEYPAD_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name  = "coh901461-press",
-                .start = IRQ_U300_KEYPAD_KEYBF,
-                .end   = IRQ_U300_KEYPAD_KEYBF,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "coh901461-release",
-                .start = IRQ_U300_KEYPAD_KEYBR,
-                .end   = IRQ_U300_KEYPAD_KEYBR,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource rtc_resources[] = {
-        {
-                .start = U300_RTC_BASE,
-                .end   = U300_RTC_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = IRQ_U300_RTC,
-                .end   = IRQ_U300_RTC,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-/*
- * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
- * but these are not yet used by the driver.
- */
-static struct resource fsmc_resources[] = {
-        {
-                .name  = "nand_addr",
-                .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE,
-                .end   = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name  = "nand_cmd",
-                .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE,
-                .end   = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name  = "nand_data",
-                .start = U300_NAND_CS0_PHYS_BASE,
-                .end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name  = "fsmc_regs",
-                .start = U300_NAND_IF_PHYS_BASE,
-                .end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-
-static struct resource i2c0_resources[] = {
-        {
-                .start = U300_I2C0_BASE,
-                .end   = U300_I2C0_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = IRQ_U300_I2C0,
-                .end   = IRQ_U300_I2C0,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource i2c1_resources[] = {
-        {
-                .start = U300_I2C1_BASE,
-                .end   = U300_I2C1_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = IRQ_U300_I2C1,
-                .end   = IRQ_U300_I2C1,
-                .flags = IORESOURCE_IRQ,
-        },
-
-};
-
-static struct resource wdog_resources[] = {
-        {
-                .start = U300_WDOG_BASE,
-                .end   = U300_WDOG_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = IRQ_U300_WDOG,
-                .end   = IRQ_U300_WDOG,
-                .flags = IORESOURCE_IRQ,
-        }
-};
-
-static struct resource dma_resource[] = {
-        {
-                .start = U300_DMAC_BASE,
-                .end = U300_DMAC_BASE + PAGE_SIZE - 1,
-                .flags =  IORESOURCE_MEM,
-        },
-        {
-                .start = IRQ_U300_DMA,
-                .end = IRQ_U300_DMA,
-                .flags =  IORESOURCE_IRQ,
-        }
-};
-
-
-static struct resource pinctrl_resources[] = {
-        {
-                .start = U300_SYSCON_BASE,
-                .end   = U300_SYSCON_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device wdog_device = {
-        .name = "coh901327_wdog",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(wdog_resources),
-        .resource = wdog_resources,
-};
-
-static struct platform_device i2c0_device = {
-        .name = "stu300",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(i2c0_resources),
-        .resource = i2c0_resources,
-};
-
-static struct platform_device i2c1_device = {
-        .name = "stu300",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(i2c1_resources),
-        .resource = i2c1_resources,
-};
-
-static struct platform_device pinctrl_device = {
-        .name = "pinctrl-u300",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(pinctrl_resources),
-        .resource = pinctrl_resources,
-};
-
-/*
- * The different variants have a few different versions of the
- * GPIO block, with different number of ports.
- */
-static struct u300_gpio_platform u300_gpio_plat = {
-        .ports = 7,
-        .gpio_base = 0,
-};
-
-static struct platform_device gpio_device = {
-        .name = "u300-gpio",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(gpio_resources),
-        .resource = gpio_resources,
-        .dev = {
-                .platform_data = &u300_gpio_plat,
-        },
-};
-
-static struct platform_device keypad_device = {
-        .name = "keypad",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(keypad_resources),
-        .resource = keypad_resources,
-};
-
-static struct platform_device rtc_device = {
-        .name = "rtc-coh901331",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(rtc_resources),
-        .resource = rtc_resources,
-};
-
-static struct mtd_partition u300_partitions[] = {
-        {
-                .name = "bootrecords",
-                .offset = 0,
-                .size = SZ_128K,
-        },
-        {
-                .name = "free",
-                .offset = SZ_128K,
-                .size = 8064 * SZ_1K,
-        },
-        {
-                .name = "platform",
-                .offset = 8192 * SZ_1K,
-                .size = 253952 * SZ_1K,
-        },
-};
-
-static struct fsmc_nand_platform_data nand_platform_data = {
-        .partitions = u300_partitions,
-        .nr_partitions = ARRAY_SIZE(u300_partitions),
-        .options = NAND_SKIP_BBTSCAN,
-        .width = FSMC_NAND_BW8,
-};
-
-static struct platform_device nand_device = {
-        .name = "fsmc-nand",
-        .id = -1,
-        .resource = fsmc_resources,
-        .num_resources = ARRAY_SIZE(fsmc_resources),
-        .dev = {
-                .platform_data = &nand_platform_data,
-        },
-};
-
-static struct platform_device dma_device = {
-        .name           = "coh901318",
-        .id             = -1,
-        .resource       = dma_resource,
-        .num_resources  = ARRAY_SIZE(dma_resource),
-        .dev = {
-                .coherent_dma_mask = ~0,
-        },
-};
-
 static unsigned long pin_pullup_conf[] = {
         PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
 };
@@ -467,61 +219,6 @@ static struct pinctrl_map __initdata u300_pinmux_map[] = {
                                     pin_highz_conf),
 };
 
-/*
- * Notice that AMBA devices are initialized before platform devices.
- *
- */
-static struct platform_device *platform_devs[] __initdata = {
-        &dma_device,
-        &i2c0_device,
-        &i2c1_device,
-        &keypad_device,
-        &rtc_device,
-        &pinctrl_device,
-        &gpio_device,
-        &nand_device,
-        &wdog_device,
-};
-
-/*
- * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
- * together so some interrupts are connected to the first one and some
- * to the second one.
- */
-static void __init u300_init_irq(void)
-{
-        u32 mask[2] = {0, 0};
-        struct clk *clk;
-        int i;
-
-        /* initialize clocking early, we want to clock the INTCON */
-        u300_clk_init(U300_SYSCON_VBASE);
-
-        /* Bootstrap EMIF and SEMI clocks */
-        clk = clk_get_sys("pl172", NULL);
-        BUG_ON(IS_ERR(clk));
-        clk_prepare_enable(clk);
-        clk = clk_get_sys("semi", NULL);
-        BUG_ON(IS_ERR(clk));
-        clk_prepare_enable(clk);
-
-        /* Clock the interrupt controller */
-        clk = clk_get_sys("intcon", NULL);
-        BUG_ON(IS_ERR(clk));
-        clk_prepare_enable(clk);
-
-        for (i = 0; i < U300_VIC_IRQS_END; i++)
-                set_bit(i, (unsigned long *) &mask[0]);
-        vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
-                 mask[0], mask[0]);
-        vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
-                 mask[1], mask[1]);
-}
-
-
-/*
- * U300 platforms peripheral handling
- */
 struct db_chip {
         u16 chipid;
         const char *name;
@@ -578,7 +275,7 @@ static void __init u300_init_check_chip(void)
         const char unknown[] = "UNKNOWN";
 
         /* Read out and print chip ID */
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
+        val = readw(syscon_base + U300_SYSCON_CIDR);
         /* This is in funky bigendian order... */
         val = (val & 0xFFU) << 8 | (val >> 8);
         chip = db_chips;
@@ -600,74 +297,6 @@ static void __init u300_init_check_chip(void)
         }
 }
 
-/*
- * Some devices and their resources require reserved physical memory from
- * the end of the available RAM. This function traverses the list of devices
- * and assigns actual addresses to these.
- */
-static void __init u300_assign_physmem(void)
-{
-        unsigned long curr_start = __pa(high_memory);
-        int i, j;
-
-        for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
-                for (j = 0; j < platform_devs[i]->num_resources; j++) {
-                        struct resource *const res =
-                          &platform_devs[i]->resource[j];
-
-                        if (IORESOURCE_MEM == res->flags &&
-                                     0 == res->start) {
-                                res->start  = curr_start;
-                                res->end   += curr_start;
-                                curr_start += resource_size(res);
-
-                                printk(KERN_INFO "core.c: Mapping RAM " \
-                                       "%#x-%#x to device %s:%s\n",
-                                        res->start, res->end,
-                                       platform_devs[i]->name, res->name);
-                        }
-                }
-        }
-}
-
-static void __init u300_init_machine(void)
-{
-        int i;
-        u16 val;
-
-        /* Check what platform we run and print some status information */
-        u300_init_check_chip();
-
-        /* Initialize SPI device with some board specifics */
-        u300_spi_init(&pl022_device);
-
-        /* Register the AMBA devices in the AMBA bus abstraction layer */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-                struct amba_device *d = amba_devs[i];
-                amba_device_register(d, &iomem_resource);
-        }
-
-        u300_assign_physmem();
-
-        /* Initialize pinmuxing */
-        pinctrl_register_mappings(u300_pinmux_map,
-                                  ARRAY_SIZE(u300_pinmux_map));
-
-        /* Register subdevices on the I2C buses */
-        u300_i2c_register_board_devices();
-
-        /* Register the platform devices */
-        platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
-
-        /* Register subdevices on the SPI bus */
-        u300_spi_register_board_devices();
-
-        /* Enable SEMI self refresh */
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
-                U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
-}
-
 /* Forward declare this function from the watchdog */
 void coh901327_watchdog_reset(void);
 
@@ -688,13 +317,99 @@ static void u300_restart(char mode, const char *cmd)
         while (1);
 }
 
-MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
-        /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
-        .atag_offset    = 0x100,
+/* These are mostly to get the right device names for the clock lookups */
+static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE,
+                "pinctrl-u300", NULL),
+        OF_DEV_AUXDATA("stericsson,gpio-coh901", U300_GPIO_BASE,
+                "u300-gpio", NULL),
+        OF_DEV_AUXDATA("stericsson,coh901327", U300_WDOG_BASE,
+                "coh901327_wdog", NULL),
+        OF_DEV_AUXDATA("stericsson,coh901331", U300_RTC_BASE,
+                "rtc-coh901331", NULL),
+        OF_DEV_AUXDATA("stericsson,coh901318", U300_DMAC_BASE,
+                "coh901318", NULL),
+        OF_DEV_AUXDATA("stericsson,fsmc-nand", U300_NAND_IF_PHYS_BASE,
+                "fsmc-nand", NULL),
+        OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE,
+                "uart0", NULL),
+        OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
+                "uart1", NULL),
+        OF_DEV_AUXDATA("arm,primecell", U300_SPI_BASE,
+                "pl022", NULL),
+        OF_DEV_AUXDATA("st,ddci2c", U300_I2C0_BASE,
+                "stu300.0", NULL),
+        OF_DEV_AUXDATA("st,ddci2c", U300_I2C1_BASE,
+                "stu300.1", NULL),
+        OF_DEV_AUXDATA("arm,primecell", U300_MMCSD_BASE,
+                "mmci", NULL),
+        { /* sentinel */ },
+};
+
+static void __init u300_init_irq_dt(void)
+{
+        struct device_node *syscon;
+        struct clk *clk;
+
+        syscon = of_find_node_by_path("/syscon@c0011000");
+        if (!syscon) {
+                pr_crit("could not find syscon node\n");
+                return;
+        }
+        syscon_base = of_iomap(syscon, 0);
+        if (!syscon_base) {
+                pr_crit("could not remap syscon\n");
+                return;
+        }
+        /* initialize clocking early, we want to clock the INTCON */
+        u300_clk_init(syscon_base);
+
+        /* Bootstrap EMIF and SEMI clocks */
+        clk = clk_get_sys("pl172", NULL);
+        BUG_ON(IS_ERR(clk));
+        clk_prepare_enable(clk);
+        clk = clk_get_sys("semi", NULL);
+        BUG_ON(IS_ERR(clk));
+        clk_prepare_enable(clk);
+
+        /* Clock the interrupt controller */
+        clk = clk_get_sys("intcon", NULL);
+        BUG_ON(IS_ERR(clk));
+        clk_prepare_enable(clk);
+
+        irqchip_init();
+}
+
+static void __init u300_init_machine_dt(void)
+{
+        u16 val;
+
+        /* Check what platform we run and print some status information */
+        u300_init_check_chip();
+
+        /* Initialize pinmuxing */
+        pinctrl_register_mappings(u300_pinmux_map,
+                                  ARRAY_SIZE(u300_pinmux_map));
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        u300_auxdata_lookup, NULL);
+
+        /* Enable SEMI self refresh */
+        val = readw(syscon_base + U300_SYSCON_SMCR) |
+                U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
+        writew(val, syscon_base + U300_SYSCON_SMCR);
+}
+
+static const char * u300_board_compat[] = {
+        "stericsson,u300",
+        NULL,
+};
+
+DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)")
         .map_io         = u300_map_io,
-        .nr_irqs        = 0,
-        .init_irq       = u300_init_irq,
-        .init_time      = u300_timer_init,
-        .init_machine   = u300_init_machine,
+        .init_irq       = u300_init_irq_dt,
+        .init_time      = clocksource_of_init,
+        .init_machine   = u300_init_machine_dt,
         .restart        = u300_restart,
+        .dt_compat      = u300_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-u300/dummyspichip.c b/arch/arm/mach-u300/dummyspichip.c
index 2785cb67b5e8..ec0283cf9a32 100644
--- a/arch/arm/mach-u300/dummyspichip.c
+++ b/arch/arm/mach-u300/dummyspichip.c
@@ -263,28 +263,22 @@ static int pl022_dummy_remove(struct spi_device *spi)
         return 0;
 }
 
+static const struct of_device_id pl022_dummy_dt_match[] = {
+        { .compatible = "arm,pl022-dummy" },
+        {},
+};
+
 static struct spi_driver pl022_dummy_driver = {
         .driver = {
                 .name   = "spi-dummy",
                 .owner  = THIS_MODULE,
+                .of_match_table = pl022_dummy_dt_match,
         },
         .probe  = pl022_dummy_probe,
         .remove = pl022_dummy_remove,
 };
 
-static int __init pl022_init_dummy(void)
-{
-        return spi_register_driver(&pl022_dummy_driver);
-}
-
-static void __exit pl022_exit_dummy(void)
-{
-        spi_unregister_driver(&pl022_dummy_driver);
-}
-
-module_init(pl022_init_dummy);
-module_exit(pl022_exit_dummy);
-
+module_spi_driver(pl022_dummy_driver);
 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
 MODULE_DESCRIPTION("PL022 SSP/SPI DUMMY Linux driver");
 MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
deleted file mode 100644
index 96800aa1316d..000000000000
--- a/arch/arm/mach-u300/i2c.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * arch/arm/mach-u300/i2c.c
- *
- * Copyright (C) 2009-2012 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Register board i2c devices
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#include <linux/kernel.h>
-#include <linux/i2c.h>
-#include <linux/mfd/ab3100.h>
-#include <linux/regulator/machine.h>
-#include <linux/amba/bus.h>
-#include <mach/irqs.h>
-
-/*
- * Initial settings of ab3100 registers.
- * Common for below LDO regulator settings are that
- * bit 7-5 controls voltage. Bit 4 turns regulator ON(1) or OFF(0).
- * Bit 3-2 controls sleep enable and bit 1-0 controls sleep mode.
- */
-
-/* LDO_A 0x16: 2.75V, ON, SLEEP_A, SLEEP OFF GND */
-#define LDO_A_SETTING           0x16
-/* LDO_C 0x10: 2.65V, ON, SLEEP_A or B, SLEEP full power */
-#define LDO_C_SETTING           0x10
-/* LDO_D 0x10: 2.65V, ON, sleep mode not used */
-#define LDO_D_SETTING           0x10
-/* LDO_E 0x10: 1.8V, ON, SLEEP_A or B, SLEEP full power */
-#define LDO_E_SETTING           0x10
-/* LDO_E SLEEP 0x00: 1.8V, not used, SLEEP_A or B, not used */
-#define LDO_E_SLEEP_SETTING     0x00
-/* LDO_F 0xD0: 2.5V, ON, SLEEP_A or B, SLEEP full power */
-#define LDO_F_SETTING           0xD0
-/* LDO_G 0x00: 2.85V, OFF, SLEEP_A or B, SLEEP full power */
-#define LDO_G_SETTING           0x00
-/* LDO_H 0x18: 2.75V, ON, SLEEP_B, SLEEP full power */
-#define LDO_H_SETTING           0x18
-/* LDO_K 0x00: 2.75V, OFF, SLEEP_A or B, SLEEP full power */
-#define LDO_K_SETTING           0x00
-/* LDO_EXT 0x00: Voltage not set, OFF, not used, not used */
-#define LDO_EXT_SETTING         0x00
-/* BUCK 0x7D: 1.2V, ON, SLEEP_A and B, SLEEP low power */
-#define BUCK_SETTING    0x7D
-/* BUCK SLEEP 0xAC: 1.05V, Not used, SLEEP_A and B, Not used */
-#define BUCK_SLEEP_SETTING      0xAC
-
-#ifdef CONFIG_AB3100_CORE
-static struct regulator_consumer_supply supply_ldo_c[] = {
-        {
-                .dev_name = "ab3100-codec",
-                .supply = "vaudio", /* Powers the codec */
-        },
-};
-
-/*
- * This one needs to be a supply so we can turn it off
- * in order to shut down the system.
- */
-static struct regulator_consumer_supply supply_ldo_d[] = {
-        {
-                .supply = "vana15", /* Powers the SoC (CPU etc) */
-        },
-};
-
-static struct regulator_consumer_supply supply_ldo_g[] = {
-        {
-                .dev_name = "mmci",
-                .supply = "vmmc", /* Powers MMC/SD card */
-        },
-};
-
-static struct regulator_consumer_supply supply_ldo_h[] = {
-        {
-                .dev_name = "xgam_pdi",
-                .supply = "vdisp", /* Powers camera, display etc */
-        },
-};
-
-static struct regulator_consumer_supply supply_ldo_k[] = {
-        {
-                .dev_name = "irda",
-                .supply = "vir", /* Power IrDA */
-        },
-};
-
-/*
- * This is a placeholder for whoever wish to use the
- * external power.
- */
-static struct regulator_consumer_supply supply_ldo_ext[] = {
-        {
-                .supply = "vext", /* External power */
-        },
-};
-
-/* Preset (hardware defined) voltages for these regulators */
-#define LDO_A_VOLTAGE 2750000
-#define LDO_C_VOLTAGE 2650000
-#define LDO_D_VOLTAGE 2650000
-
-static struct ab3100_platform_data ab3100_plf_data = {
-        .reg_constraints = {
-                /* LDO A routing and constraints */
-                {
-                        .constraints = {
-                                .name = "vrad",
-                                .min_uV = LDO_A_VOLTAGE,
-                                .max_uV = LDO_A_VOLTAGE,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .always_on = 1,
-                                .boot_on = 1,
-                        },
-                },
-                /* LDO C routing and constraints */
-                {
-                        .constraints = {
-                                .min_uV = LDO_C_VOLTAGE,
-                                .max_uV = LDO_C_VOLTAGE,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                        },
-                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_c),
-                        .consumer_supplies = supply_ldo_c,
-                },
-                /* LDO D routing and constraints */
-                {
-                        .constraints = {
-                                .min_uV = LDO_D_VOLTAGE,
-                                .max_uV = LDO_D_VOLTAGE,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                                /*
-                                 * Actually this is boot_on but we need
-                                 * to reference count it externally to
-                                 * be able to shut down the system.
-                                 */
-                        },
-                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_d),
-                        .consumer_supplies = supply_ldo_d,
-                },
-                /* LDO E routing and constraints */
-                {
-                        .constraints = {
-                                .name = "vio",
-                                .min_uV = 1800000,
-                                .max_uV = 1800000,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .always_on = 1,
-                                .boot_on = 1,
-                        },
-                },
-                /* LDO F routing and constraints */
-                {
-                        .constraints = {
-                                .name = "vana25",
-                                .min_uV = 2500000,
-                                .max_uV = 2500000,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .always_on = 1,
-                                .boot_on = 1,
-                        },
-                },
-                /* LDO G routing and constraints */
-                {
-                        .constraints = {
-                                .min_uV = 1500000,
-                                .max_uV = 2850000,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE |
-                                REGULATOR_CHANGE_STATUS,
-                        },
-                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_g),
-                        .consumer_supplies = supply_ldo_g,
-                },
-                /* LDO H routing and constraints */
-                {
-                        .constraints = {
-                                .min_uV = 1200000,
-                                .max_uV = 2750000,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE |
-                                REGULATOR_CHANGE_STATUS,
-                        },
-                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_h),
-                        .consumer_supplies = supply_ldo_h,
-                },
-                /* LDO K routing and constraints */
-                {
-                        .constraints = {
-                                .min_uV = 1800000,
-                                .max_uV = 2750000,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE |
-                                REGULATOR_CHANGE_STATUS,
-                        },
-                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_k),
-                        .consumer_supplies = supply_ldo_k,
-                },
-                /* External regulator interface. No fixed voltage specified.
-                 * If we knew the voltage of the external regulator and it
-                 * was connected on the board, we could add the (fixed)
-                 * voltage for it here.
-                 */
-                {
-                        .constraints = {
-                                .min_uV = 0,
-                                .max_uV = 0,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_STATUS,
-                        },
-                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_ext),
-                        .consumer_supplies = supply_ldo_ext,
-                },
-                /* Buck converter routing and constraints */
-                {
-                        .constraints = {
-                                .name = "vcore",
-                                .min_uV = 1200000,
-                                .max_uV = 1800000,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE,
-                                .always_on = 1,
-                                .boot_on = 1,
-                        },
-                },
-        },
-        .reg_initvals = {
-                LDO_A_SETTING,
-                LDO_C_SETTING,
-                LDO_E_SETTING,
-                LDO_E_SLEEP_SETTING,
-                LDO_F_SETTING,
-                LDO_G_SETTING,
-                LDO_H_SETTING,
-                LDO_K_SETTING,
-                LDO_EXT_SETTING,
-                BUCK_SETTING,
-                BUCK_SLEEP_SETTING,
-                LDO_D_SETTING,
-        },
-};
-#endif
-
-static struct i2c_board_info __initdata bus0_i2c_board_info[] = {
-#ifdef CONFIG_AB3100_CORE
-        {
-                .type = "ab3100",
-                .addr = 0x48,
-                .irq = IRQ_U300_IRQ0_EXT,
-                .platform_data = &ab3100_plf_data,
-        },
-#else
-        { },
-#endif
-};
-
-static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
-        {
-                .type = "fwcam",
-                .addr = 0x10,
-        },
-        {
-                .type = "fwcam",
-                .addr = 0x5d,
-        },
-};
-
-void __init u300_i2c_register_board_devices(void)
-{
-        i2c_register_board_info(0, bus0_i2c_board_info,
-                                ARRAY_SIZE(bus0_i2c_board_info));
-        /*
-         * This makes the core shut down all unused regulators
-         * after all the initcalls have completed.
-         */
-        regulator_has_full_constraints();
-        i2c_register_board_info(1, bus1_i2c_board_info,
-                                ARRAY_SIZE(bus1_i2c_board_info));
-}
diff --git a/arch/arm/mach-u300/i2c.h b/arch/arm/mach-u300/i2c.h
deleted file mode 100644
index 485c02e5c06d..000000000000
--- a/arch/arm/mach-u300/i2c.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * arch/arm/mach-u300/i2c.h
- *
- * Copyright (C) 2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Register board i2c devices
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-
-#ifndef MACH_U300_I2C_H
-#define MACH_U300_I2C_H
-
-#ifdef CONFIG_I2C_STU300
-void __init u300_i2c_register_board_devices(void);
-#else
-/* Compile out this stuff if no I2C adapter is available */
-static inline void __init u300_i2c_register_board_devices(void)
-{
-}
-#endif
-
-#endif
diff --git a/arch/arm/mach-u300/include/mach/hardware.h b/arch/arm/mach-u300/include/mach/hardware.h
deleted file mode 100644
index b99d4ce0ac2b..000000000000
--- a/arch/arm/mach-u300/include/mach/hardware.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-u300/include/mach/hardware.h
- */
-#include <asm/sizes.h>
-#include <mach/u300-regs.h>
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
deleted file mode 100644
index 21d5e76a6cd3..000000000000
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/irqs.h
- *
- *
- * Copyright (C) 2006-2012 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * IRQ channel definitions for the U300 platforms.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-
-#ifndef __MACH_IRQS_H
-#define __MACH_IRQS_H
-
-#define IRQ_U300_INTCON0_START          32
-#define IRQ_U300_INTCON1_START          64
-/* These are on INTCON0 - 30 lines */
-#define IRQ_U300_IRQ0_EXT               32
-#define IRQ_U300_IRQ1_EXT               33
-#define IRQ_U300_DMA                    34
-#define IRQ_U300_VIDEO_ENC_0            35
-#define IRQ_U300_VIDEO_ENC_1            36
-#define IRQ_U300_AAIF_RX                37
-#define IRQ_U300_AAIF_TX                38
-#define IRQ_U300_AAIF_VGPIO             39
-#define IRQ_U300_AAIF_WAKEUP            40
-#define IRQ_U300_PCM_I2S0_FRAME         41
-#define IRQ_U300_PCM_I2S0_FIFO          42
-#define IRQ_U300_PCM_I2S1_FRAME         43
-#define IRQ_U300_PCM_I2S1_FIFO          44
-#define IRQ_U300_XGAM_GAMCON            45
-#define IRQ_U300_XGAM_CDI               46
-#define IRQ_U300_XGAM_CDICON            47
-#define IRQ_U300_XGAM_PDI               49
-#define IRQ_U300_XGAM_PDICON            50
-#define IRQ_U300_XGAM_GAMEACC           51
-#define IRQ_U300_XGAM_MCIDCT            52
-#define IRQ_U300_APEX                   53
-#define IRQ_U300_UART0                  54
-#define IRQ_U300_SPI                    55
-#define IRQ_U300_TIMER_APP_OS           56
-#define IRQ_U300_TIMER_APP_DD           57
-#define IRQ_U300_TIMER_APP_GP1          58
-#define IRQ_U300_TIMER_APP_GP2          59
-#define IRQ_U300_TIMER_OS               60
-#define IRQ_U300_TIMER_MS               61
-#define IRQ_U300_KEYPAD_KEYBF           62
-#define IRQ_U300_KEYPAD_KEYBR           63
-/* These are on INTCON1 - 32 lines */
-#define IRQ_U300_GPIO_PORT0             64
-#define IRQ_U300_GPIO_PORT1             65
-#define IRQ_U300_GPIO_PORT2             66
-
-/* These are for DB3150, DB3200 and DB3350 */
-#define IRQ_U300_WDOG                   67
-#define IRQ_U300_EVHIST                 68
-#define IRQ_U300_MSPRO                  69
-#define IRQ_U300_MMCSD_MCIINTR0         70
-#define IRQ_U300_MMCSD_MCIINTR1         71
-#define IRQ_U300_I2C0                   72
-#define IRQ_U300_I2C1                   73
-#define IRQ_U300_RTC                    74
-#define IRQ_U300_NFIF                   75
-#define IRQ_U300_NFIF2                  76
-
-/* The DB3350-specific interrupt lines */
-#define IRQ_U300_ISP_F0                 77
-#define IRQ_U300_ISP_F1                 78
-#define IRQ_U300_ISP_F2                 79
-#define IRQ_U300_ISP_F3                 80
-#define IRQ_U300_ISP_F4                 81
-#define IRQ_U300_GPIO_PORT3             82
-#define IRQ_U300_SYSCON_PLL_LOCK        83
-#define IRQ_U300_UART1                  84
-#define IRQ_U300_GPIO_PORT4             85
-#define IRQ_U300_GPIO_PORT5             86
-#define IRQ_U300_GPIO_PORT6             87
-#define U300_VIC_IRQS_END               88
-
-#endif
diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h
deleted file mode 100644
index 10bdd0be9774..000000000000
--- a/arch/arm/mach-u300/include/mach/syscon.h
+++ /dev/null
@@ -1,592 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/syscon.h
- *
- *
- * Copyright (C) 2008-2012 ST-Ericsson AB
- *
- * Author: Rickard Andersson <rickard.andersson@stericsson.com>
- */
-
-#ifndef __MACH_SYSCON_H
-#define __MACH_SYSCON_H
-
-/*
- * All register defines for SYSCON registers that concerns individual
- * block clocks and reset lines are registered here. This is because
- * we don't want any other file to try to fool around with this stuff.
- */
-
-/* APP side SYSCON registers */
-/* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */
-/* CLK Control Register 16bit (R/W) */
-#define U300_SYSCON_CCR                                         (0x0000)
-#define U300_SYSCON_CCR_I2S1_USE_VCXO                           (0x0040)
-#define U300_SYSCON_CCR_I2S0_USE_VCXO                           (0x0020)
-#define U300_SYSCON_CCR_TURN_VCXO_ON                            (0x0008)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK                 (0x0007)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER            (0x04)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW                  (0x03)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE         (0x02)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH                 (0x01)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST                 (0x00)
-/* CLK Status Register 16bit (R/W) */
-#define U300_SYSCON_CSR                                         (0x0004)
-#define U300_SYSCON_CSR_PLL208_LOCK_IND                         (0x0002)
-#define U300_SYSCON_CSR_PLL13_LOCK_IND                          (0x0001)
-/* Reset lines for SLOW devices 16bit (R/W) */
-#define U300_SYSCON_RSR                                         (0x0014)
-#define U300_SYSCON_RSR_PPM_RESET_EN                            (0x0200)
-#define U300_SYSCON_RSR_ACC_TMR_RESET_EN                        (0x0100)
-#define U300_SYSCON_RSR_APP_TMR_RESET_EN                        (0x0080)
-#define U300_SYSCON_RSR_RTC_RESET_EN                            (0x0040)
-#define U300_SYSCON_RSR_KEYPAD_RESET_EN                         (0x0020)
-#define U300_SYSCON_RSR_GPIO_RESET_EN                           (0x0010)
-#define U300_SYSCON_RSR_EH_RESET_EN                             (0x0008)
-#define U300_SYSCON_RSR_BTR_RESET_EN                            (0x0004)
-#define U300_SYSCON_RSR_UART_RESET_EN                           (0x0002)
-#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN                    (0x0001)
-/* Reset lines for FAST devices 16bit (R/W) */
-#define U300_SYSCON_RFR                                         (0x0018)
-#define U300_SYSCON_RFR_UART1_RESET_ENABLE                      (0x0080)
-#define U300_SYSCON_RFR_SPI_RESET_ENABLE                        (0x0040)
-#define U300_SYSCON_RFR_MMC_RESET_ENABLE                        (0x0020)
-#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE                   (0x0010)
-#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE                   (0x0008)
-#define U300_SYSCON_RFR_I2C1_RESET_ENABLE                       (0x0004)
-#define U300_SYSCON_RFR_I2C0_RESET_ENABLE                       (0x0002)
-#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE                (0x0001)
-/* Reset lines for the rest of the peripherals 16bit (R/W) */
-#define U300_SYSCON_RRR                                         (0x001c)
-#define U300_SYSCON_RRR_CDS_RESET_EN                            (0x4000)
-#define U300_SYSCON_RRR_ISP_RESET_EN                            (0x2000)
-#define U300_SYSCON_RRR_INTCON_RESET_EN                         (0x1000)
-#define U300_SYSCON_RRR_MSPRO_RESET_EN                          (0x0800)
-#define U300_SYSCON_RRR_XGAM_RESET_EN                           (0x0100)
-#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN                   (0x0080)
-#define U300_SYSCON_RRR_NANDIF_RESET_EN                         (0x0040)
-#define U300_SYSCON_RRR_EMIF_RESET_EN                           (0x0020)
-#define U300_SYSCON_RRR_DMAC_RESET_EN                           (0x0010)
-#define U300_SYSCON_RRR_CPU_RESET_EN                            (0x0008)
-#define U300_SYSCON_RRR_APEX_RESET_EN                           (0x0004)
-#define U300_SYSCON_RRR_AHB_RESET_EN                            (0x0002)
-#define U300_SYSCON_RRR_AAIF_RESET_EN                           (0x0001)
-/* Clock enable for SLOW peripherals 16bit (R/W) */
-#define U300_SYSCON_CESR                                        (0x0020)
-#define U300_SYSCON_CESR_PPM_CLK_EN                             (0x0200)
-#define U300_SYSCON_CESR_ACC_TMR_CLK_EN                         (0x0100)
-#define U300_SYSCON_CESR_APP_TMR_CLK_EN                         (0x0080)
-#define U300_SYSCON_CESR_KEYPAD_CLK_EN                          (0x0040)
-#define U300_SYSCON_CESR_GPIO_CLK_EN                            (0x0010)
-#define U300_SYSCON_CESR_EH_CLK_EN                              (0x0008)
-#define U300_SYSCON_CESR_BTR_CLK_EN                             (0x0004)
-#define U300_SYSCON_CESR_UART_CLK_EN                            (0x0002)
-#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN                     (0x0001)
-/* Clock enable for FAST peripherals 16bit (R/W) */
-#define U300_SYSCON_CEFR                                        (0x0024)
-#define U300_SYSCON_CEFR_UART1_CLK_EN                           (0x0200)
-#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN                       (0x0100)
-#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN                       (0x0080)
-#define U300_SYSCON_CEFR_SPI_CLK_EN                             (0x0040)
-#define U300_SYSCON_CEFR_MMC_CLK_EN                             (0x0020)
-#define U300_SYSCON_CEFR_I2S1_CLK_EN                            (0x0010)
-#define U300_SYSCON_CEFR_I2S0_CLK_EN                            (0x0008)
-#define U300_SYSCON_CEFR_I2C1_CLK_EN                            (0x0004)
-#define U300_SYSCON_CEFR_I2C0_CLK_EN                            (0x0002)
-#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN                     (0x0001)
-/* Clock enable for the rest of the peripherals 16bit (R/W) */
-#define U300_SYSCON_CERR                                        (0x0028)
-#define U300_SYSCON_CERR_CDS_CLK_EN                             (0x2000)
-#define U300_SYSCON_CERR_ISP_CLK_EN                             (0x1000)
-#define U300_SYSCON_CERR_MSPRO_CLK_EN                           (0x0800)
-#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN               (0x0400)
-#define U300_SYSCON_CERR_SEMI_CLK_EN                            (0x0200)
-#define U300_SYSCON_CERR_XGAM_CLK_EN                            (0x0100)
-#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN                       (0x0080)
-#define U300_SYSCON_CERR_NANDIF_CLK_EN                          (0x0040)
-#define U300_SYSCON_CERR_EMIF_CLK_EN                            (0x0020)
-#define U300_SYSCON_CERR_DMAC_CLK_EN                            (0x0010)
-#define U300_SYSCON_CERR_CPU_CLK_EN                             (0x0008)
-#define U300_SYSCON_CERR_APEX_CLK_EN                            (0x0004)
-#define U300_SYSCON_CERR_AHB_CLK_EN                             (0x0002)
-#define U300_SYSCON_CERR_AAIF_CLK_EN                            (0x0001)
-/* Single block clock enable 16bit (-/W) */
-#define U300_SYSCON_SBCER                                       (0x002c)
-#define U300_SYSCON_SBCER_PPM_CLK_EN                            (0x0009)
-#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN                        (0x0008)
-#define U300_SYSCON_SBCER_APP_TMR_CLK_EN                        (0x0007)
-#define U300_SYSCON_SBCER_KEYPAD_CLK_EN                         (0x0006)
-#define U300_SYSCON_SBCER_GPIO_CLK_EN                           (0x0004)
-#define U300_SYSCON_SBCER_EH_CLK_EN                             (0x0003)
-#define U300_SYSCON_SBCER_BTR_CLK_EN                            (0x0002)
-#define U300_SYSCON_SBCER_UART_CLK_EN                           (0x0001)
-#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN                    (0x0000)
-#define U300_SYSCON_SBCER_UART1_CLK_EN                          (0x0019)
-#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN                      (0x0018)
-#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN                      (0x0017)
-#define U300_SYSCON_SBCER_SPI_CLK_EN                            (0x0016)
-#define U300_SYSCON_SBCER_MMC_CLK_EN                            (0x0015)
-#define U300_SYSCON_SBCER_I2S1_CLK_EN                           (0x0014)
-#define U300_SYSCON_SBCER_I2S0_CLK_EN                           (0x0013)
-#define U300_SYSCON_SBCER_I2C1_CLK_EN                           (0x0012)
-#define U300_SYSCON_SBCER_I2C0_CLK_EN                           (0x0011)
-#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN                    (0x0010)
-#define U300_SYSCON_SBCER_CDS_CLK_EN                            (0x002D)
-#define U300_SYSCON_SBCER_ISP_CLK_EN                            (0x002C)
-#define U300_SYSCON_SBCER_MSPRO_CLK_EN                          (0x002B)
-#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN              (0x002A)
-#define U300_SYSCON_SBCER_SEMI_CLK_EN                           (0x0029)
-#define U300_SYSCON_SBCER_XGAM_CLK_EN                           (0x0028)
-#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN                      (0x0027)
-#define U300_SYSCON_SBCER_NANDIF_CLK_EN                         (0x0026)
-#define U300_SYSCON_SBCER_EMIF_CLK_EN                           (0x0025)
-#define U300_SYSCON_SBCER_DMAC_CLK_EN                           (0x0024)
-#define U300_SYSCON_SBCER_CPU_CLK_EN                            (0x0023)
-#define U300_SYSCON_SBCER_APEX_CLK_EN                           (0x0022)
-#define U300_SYSCON_SBCER_AHB_CLK_EN                            (0x0021)
-#define U300_SYSCON_SBCER_AAIF_CLK_EN                           (0x0020)
-/* Single block clock disable 16bit (-/W) */
-#define U300_SYSCON_SBCDR                                       (0x0030)
-/* Same values as above for SBCER */
-/* Clock force SLOW peripherals 16bit (R/W) */
-#define U300_SYSCON_CFSR                                        (0x003c)
-#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN                       (0x0200)
-#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN                   (0x0100)
-#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN                   (0x0080)
-#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN                    (0x0020)
-#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN                      (0x0010)
-#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN                        (0x0008)
-#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN                       (0x0004)
-#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN                      (0x0002)
-#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN               (0x0001)
-/* Clock force FAST peripherals 16bit (R/W) */
-#define U300_SYSCON_CFFR                                        (0x40)
-/* Values not defined. Define if you want to use them. */
-/* Clock force the rest of the peripherals 16bit (R/W) */
-#define U300_SYSCON_CFRR                                        (0x44)
-#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN                       (0x2000)
-#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN                       (0x1000)
-#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN                     (0x0800)
-#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN         (0x0400)
-#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN                      (0x0200)
-#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN                      (0x0100)
-#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN                 (0x0080)
-#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN                    (0x0040)
-#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN                      (0x0020)
-#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN                      (0x0010)
-#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN                       (0x0008)
-#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN                      (0x0004)
-#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN                       (0x0002)
-#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN                      (0x0001)
-/* PLL208 Frequency Control 16bit (R/W) */
-#define U300_SYSCON_PFCR                                        (0x48)
-#define U300_SYSCON_PFCR_DPLL_MULT_NUM                          (0x000F)
-/* Power Management Control 16bit (R/W) */
-#define U300_SYSCON_PMCR                                        (0x50)
-#define U300_SYSCON_PMCR_DCON_ENABLE                            (0x0002)
-#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE                        (0x0001)
-/*
- * All other clocking registers moved to clock.c!
- */
-/* Reset Out 16bit (R/W) */
-#define U300_SYSCON_RCR                                         (0x6c)
-#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE                   (0x0001)
-/* EMIF Slew Rate Control 16bit (R/W) */
-#define U300_SYSCON_SRCLR                                       (0x70)
-#define U300_SYSCON_SRCLR_MASK                                  (0x03FF)
-#define U300_SYSCON_SRCLR_VALUE                                 (0x03FF)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B                       (0x0200)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A                       (0x0100)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B                       (0x0080)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A                       (0x0040)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B                       (0x0020)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A                       (0x0010)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B                       (0x0008)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A                       (0x0004)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B                       (0x0002)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A                       (0x0001)
-/* EMIF Clock Control Register 16bit (R/W) */
-#define U300_SYSCON_ECCR                                        (0x0078)
-#define U300_SYSCON_ECCR_MASK                                   (0x000F)
-#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE         (0x0008)
-#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE        (0x0004)
-#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE           (0x0002)
-#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE           (0x0001)
-/* Step one for killing the applications system 16bit (-/W) */
-#define U300_SYSCON_KA1R                                        (0x0080)
-#define U300_SYSCON_KA1R_MASK                                   (0xFFFF)
-#define U300_SYSCON_KA1R_VALUE                                  (0xFFFF)
-/* Step two for killing the application system 16bit (-/W) */
-#define U300_SYSCON_KA2R                                        (0x0084)
-#define U300_SYSCON_KA2R_MASK                                   (0xFFFF)
-#define U300_SYSCON_KA2R_VALUE                                  (0xFFFF)
-/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
-#define U300_SYSCON_MMF0R                                       (0x90)
-#define U300_SYSCON_MMF0R_MASK                                  (0x00FF)
-#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK                      (0x00F0)
-#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK                       (0x000F)
-/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
-#define U300_SYSCON_MMF1R                                       (0x94)
-#define U300_SYSCON_MMF1R_MASK                                  (0x00FF)
-#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK                      (0x00F0)
-#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK                       (0x000F)
-/* AAIF control register 16 bit (R/W) */
-#define U300_SYSCON_AAIFCR                                      (0x98)
-#define U300_SYSCON_AAIFCR_MASK                                 (0x0003)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_MASK                       (0x0003)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_FUNCTIONAL                 (0x0000)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_MONITORING                 (0x0001)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_ACC_TO_EXT                 (0x0002)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_APP_TO_EXT                 (0x0003)
-/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
-#define U300_SYSCON_MMCR                                        (0x9C)
-#define U300_SYSCON_MMCR_MASK                                   (0x0003)
-#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE                  (0x0002)
-#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE                   (0x0001)
-/* Pull up/down control (R/W) */
-#define U300_SYSCON_PUCR                                        (0x104)
-#define U300_SYSCON_PUCR_EMIF_1_WAIT_N_PU_ENABLE                (0x0200)
-#define U300_SYSCON_PUCR_EMIF_1_NFIF_READY_PU_ENABLE            (0x0100)
-#define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE                 (0x0080)
-#define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE                  (0x0040)
-#define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK                      (0x003F)
-/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
-#define U300_SYSCON_S0CCR                                       (0x120)
-#define U300_SYSCON_S0CCR_FIELD_MASK                            (0x43FF)
-#define U300_SYSCON_S0CCR_CLOCK_REQ                             (0x4000)
-#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR                     (0x2000)
-#define U300_SYSCON_S0CCR_CLOCK_INV                             (0x0200)
-#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK                       (0x01E0)
-#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK                     (0x001E)
-#define U300_SYSCON_S0CCR_CLOCK_ENABLE                          (0x0001)
-#define U300_SYSCON_S0CCR_SEL_MCLK                              (0x8<<1)
-#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK                       (0xA<<1)
-#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK                      (0xC<<1)
-#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK                      (0xD<<1)
-#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK                    (0xE<<1)
-#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK                     (0x0<<1)
-#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK                       (0x2<<1)
-#define U300_SYSCON_S0CCR_SEL_RTC_CLK                           (0x4<<1)
-#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK                    (0x6<<1)
-/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
-#define U300_SYSCON_S1CCR                                       (0x124)
-#define U300_SYSCON_S1CCR_FIELD_MASK                            (0x43FF)
-#define U300_SYSCON_S1CCR_CLOCK_REQ                             (0x4000)
-#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR                     (0x2000)
-#define U300_SYSCON_S1CCR_CLOCK_INV                             (0x0200)
-#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK                       (0x01E0)
-#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK                     (0x001E)
-#define U300_SYSCON_S1CCR_CLOCK_ENABLE                          (0x0001)
-#define U300_SYSCON_S1CCR_SEL_MCLK                              (0x8<<1)
-#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK                       (0xA<<1)
-#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK                      (0xC<<1)
-#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK                      (0xD<<1)
-#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK                    (0xE<<1)
-#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK                     (0x0<<1)
-#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK                       (0x2<<1)
-#define U300_SYSCON_S1CCR_SEL_RTC_CLK                           (0x4<<1)
-#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK                    (0x6<<1)
-/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
-#define U300_SYSCON_S2CCR                                       (0x128)
-#define U300_SYSCON_S2CCR_FIELD_MASK                            (0xC3FF)
-#define U300_SYSCON_S2CCR_CLK_STEAL                             (0x8000)
-#define U300_SYSCON_S2CCR_CLOCK_REQ                             (0x4000)
-#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR                     (0x2000)
-#define U300_SYSCON_S2CCR_CLOCK_INV                             (0x0200)
-#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK                       (0x01E0)
-#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK                     (0x001E)
-#define U300_SYSCON_S2CCR_CLOCK_ENABLE                          (0x0001)
-#define U300_SYSCON_S2CCR_SEL_MCLK                              (0x8<<1)
-#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK                       (0xA<<1)
-#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK                      (0xC<<1)
-#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK                      (0xD<<1)
-#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK                    (0xE<<1)
-#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK                     (0x0<<1)
-#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK                       (0x2<<1)
-#define U300_SYSCON_S2CCR_SEL_RTC_CLK                           (0x4<<1)
-#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK                    (0x6<<1)
-/* SYS_MISC_CONTROL, miscellaneous 16bit (R/W) */
-#define U300_SYSCON_MCR                                         (0x12c)
-#define U300_SYSCON_MCR_FIELD_MASK                              (0x00FF)
-#define U300_SYSCON_MCR_PMGEN_CR_4_MASK                         (0x00C0)
-#define U300_SYSCON_MCR_PMGEN_CR_4_GPIO                         (0x0000)
-#define U300_SYSCON_MCR_PMGEN_CR_4_SPI                          (0x0040)
-#define U300_SYSCON_MCR_PMGEN_CR_4_AAIF                         (0x00C0)
-#define U300_SYSCON_MCR_PMGEN_CR_2_MASK                         (0x0030)
-#define U300_SYSCON_MCR_PMGEN_CR_2_GPIO                         (0x0000)
-#define U300_SYSCON_MCR_PMGEN_CR_2_EMIF_1_STATIC                (0x0010)
-#define U300_SYSCON_MCR_PMGEN_CR_2_DSP                          (0x0020)
-#define U300_SYSCON_MCR_PMGEN_CR_2_AAIF                         (0x0030)
-#define U300_SYSCON_MCR_PMGEN_CR_0_MASK                         (0x000C)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M1              (0x0000)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M2              (0x0004)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M3              (0x0008)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_0_SDRAM                 (0x000C)
-#define U300_SYSCON_MCR_PM1G_MODE_ENABLE                        (0x0002)
-#define U300_SYSCON_MCR_PMTG5_MODE_ENABLE                       (0x0001)
-/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
-#define U300_SYSCON_PICR                                        (0x0130)
-#define U300_SYSCON_PICR_MASK                                   (0x00FF)
-#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE           (0x0080)
-#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE          (0x0040)
-#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE            (0x0020)
-#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE           (0x0010)
-#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE            (0x0008)
-#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE              (0x0004)
-#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE           (0x0002)
-#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE             (0x0001)
-/* SC_PLL_IRQ_STATUS 16 bit (R/-) */
-#define U300_SYSCON_PISR                                        (0x0134)
-#define U300_SYSCON_PISR_MASK                                   (0x000F)
-#define U300_SYSCON_PISR_PLL13_UNLOCK_IND                       (0x0008)
-#define U300_SYSCON_PISR_PLL13_LOCK_IND                         (0x0004)
-#define U300_SYSCON_PISR_PLL208_UNLOCK_IND                      (0x0002)
-#define U300_SYSCON_PISR_PLL208_LOCK_IND                        (0x0001)
-/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
-#define U300_SYSCON_PICLR                                       (0x0138)
-#define U300_SYSCON_PICLR_MASK                                  (0x000F)
-#define U300_SYSCON_PICLR_RWMASK                                (0x0000)
-#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC                       (0x0008)
-#define U300_SYSCON_PICLR_PLL13_LOCK_SC                         (0x0004)
-#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC                      (0x0002)
-#define U300_SYSCON_PICLR_PLL208_LOCK_SC                        (0x0001)
-/* CAMIF_CONTROL 16 bit (-/W) */
-#define U300_SYSCON_CICR                                        (0x013C)
-#define U300_SYSCON_CICR_MASK                                   (0x0FFF)
-#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_MASK              (0x0F00)
-#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT1             (0x0C00)
-#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT0             (0x0300)
-#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_MASK                (0x00F0)
-#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT1               (0x00C0)
-#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT0               (0x0030)
-#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_MASK             (0x000F)
-#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT1            (0x000C)
-#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT0            (0x0003)
-/* Clock activity observability register 0 */
-#define U300_SYSCON_C0OAR                                       (0x140)
-#define U300_SYSCON_C0OAR_MASK                                  (0xFFFF)
-#define U300_SYSCON_C0OAR_VALUE                                 (0xFFFF)
-#define U300_SYSCON_C0OAR_BT_H_CLK                              (0x8000)
-#define U300_SYSCON_C0OAR_ASPB_P_CLK                            (0x4000)
-#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK                        (0x2000)
-#define U300_SYSCON_C0OAR_APP_SEMI_CLK                          (0x1000)
-#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK                     (0x0800)
-#define U300_SYSCON_C0OAR_APP_I2S1_CLK                          (0x0400)
-#define U300_SYSCON_C0OAR_APP_I2S0_CLK                          (0x0200)
-#define U300_SYSCON_C0OAR_APP_CPU_CLK                           (0x0100)
-#define U300_SYSCON_C0OAR_APP_52_CLK                            (0x0080)
-#define U300_SYSCON_C0OAR_APP_208_CLK                           (0x0040)
-#define U300_SYSCON_C0OAR_APP_104_CLK                           (0x0020)
-#define U300_SYSCON_C0OAR_APEX_CLK                              (0x0010)
-#define U300_SYSCON_C0OAR_AHPB_M_H_CLK                          (0x0008)
-#define U300_SYSCON_C0OAR_AHB_CLK                               (0x0004)
-#define U300_SYSCON_C0OAR_AFPB_P_CLK                            (0x0002)
-#define U300_SYSCON_C0OAR_AAIF_CLK                              (0x0001)
-/* Clock activity observability register 1 */
-#define U300_SYSCON_C1OAR                                       (0x144)
-#define U300_SYSCON_C1OAR_MASK                                  (0x3FFE)
-#define U300_SYSCON_C1OAR_VALUE                                 (0x3FFE)
-#define U300_SYSCON_C1OAR_NFIF_F_CLK                            (0x2000)
-#define U300_SYSCON_C1OAR_MSPRO_CLK                             (0x1000)
-#define U300_SYSCON_C1OAR_MMC_P_CLK                             (0x0800)
-#define U300_SYSCON_C1OAR_MMC_CLK                               (0x0400)
-#define U300_SYSCON_C1OAR_KP_P_CLK                              (0x0200)
-#define U300_SYSCON_C1OAR_I2C1_P_CLK                            (0x0100)
-#define U300_SYSCON_C1OAR_I2C0_P_CLK                            (0x0080)
-#define U300_SYSCON_C1OAR_GPIO_CLK                              (0x0040)
-#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK                         (0x0020)
-#define U300_SYSCON_C1OAR_EMIF_H_CLK                            (0x0010)
-#define U300_SYSCON_C1OAR_EVHIST_CLK                            (0x0008)
-#define U300_SYSCON_C1OAR_PPM_CLK                               (0x0004)
-#define U300_SYSCON_C1OAR_DMA_CLK                               (0x0002)
-/* Clock activity observability register 2 */
-#define U300_SYSCON_C2OAR                                       (0x148)
-#define U300_SYSCON_C2OAR_MASK                                  (0x0FFF)
-#define U300_SYSCON_C2OAR_VALUE                                 (0x0FFF)
-#define U300_SYSCON_C2OAR_XGAM_CDI_CLK                          (0x0800)
-#define U300_SYSCON_C2OAR_XGAM_CLK                              (0x0400)
-#define U300_SYSCON_C2OAR_VC_H_CLK                              (0x0200)
-#define U300_SYSCON_C2OAR_VC_CLK                                (0x0100)
-#define U300_SYSCON_C2OAR_UA_P_CLK                              (0x0080)
-#define U300_SYSCON_C2OAR_TMR1_CLK                              (0x0040)
-#define U300_SYSCON_C2OAR_TMR0_CLK                              (0x0020)
-#define U300_SYSCON_C2OAR_SPI_P_CLK                             (0x0010)
-#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK                     (0x0008)
-#define U300_SYSCON_C2OAR_PCM_I2S1_CLK                          (0x0004)
-#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK                     (0x0002)
-#define U300_SYSCON_C2OAR_PCM_I2S0_CLK                          (0x0001)
-
-/* Chip ID register 16bit (R/-) */
-#define U300_SYSCON_CIDR                                        (0x400)
-/* Video IRQ clear 16bit (R/W) */
-#define U300_SYSCON_VICR                                        (0x404)
-#define U300_SYSCON_VICR_VIDEO1_IRQ_CLEAR_ENABLE                (0x0002)
-#define U300_SYSCON_VICR_VIDEO0_IRQ_CLEAR_ENABLE                (0x0001)
-/* SMCR */
-#define U300_SYSCON_SMCR                                        (0x4d0)
-#define U300_SYSCON_SMCR_FIELD_MASK                             (0x000e)
-#define U300_SYSCON_SMCR_SEMI_SREFACK_IND                       (0x0008)
-#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE                    (0x0004)
-#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE              (0x0002)
-/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
-#define U300_SYSCON_CSDR                                        (0x4f0)
-#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE                        (0x0001)
-/* PRINT_CONTROL Print Control 16bit (R/-) */
-#define U300_SYSCON_PCR                                         (0x4f8)
-#define U300_SYSCON_PCR_SERV_IND                                (0x0001)
-/* BOOT_CONTROL 16bit (R/-) */
-#define U300_SYSCON_BCR                                         (0x4fc)
-#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND              (0x0400)
-#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND              (0x0200)
-#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK                  (0x01FC)
-#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK                      (0x0003)
-
-
-/* CPU clock defines */
-/**
- * CPU high frequency in MHz
- */
-#define SYSCON_CPU_CLOCK_HIGH    208
-/**
- * CPU medium frequency in MHz
- */
-#define SYSCON_CPU_CLOCK_MEDIUM   52
-/**
- * CPU low frequency in MHz
- */
-#define SYSCON_CPU_CLOCK_LOW      13
-
-/* EMIF clock defines */
-/**
- * EMIF high frequency in MHz
- */
-#define SYSCON_EMIF_CLOCK_HIGH   104
-/**
- * EMIF medium frequency in MHz
- */
-#define SYSCON_EMIF_CLOCK_MEDIUM  52
-/**
- * EMIF low frequency in MHz
- */
-#define SYSCON_EMIF_CLOCK_LOW     13
-
-/* AHB clock defines */
-/**
- * AHB high frequency in MHz
- */
-#define SYSCON_AHB_CLOCK_HIGH     52
-/**
- * AHB medium frequency in MHz
- */
-#define SYSCON_AHB_CLOCK_MEDIUM   26
-/**
- * AHB low frequency in MHz
- */
-#define SYSCON_AHB_CLOCK_LOW       7  /* i.e 13/2=6.5MHz */
-
-enum syscon_busmaster {
-  SYSCON_BM_DMAC,
-  SYSCON_BM_XGAM,
-  SYSCON_BM_VIDEO_ENC
-};
-
-/* Selectr a resistor or a set of resistors */
-enum syscon_pull_up_down {
-  SYSCON_PU_KEY_IN_EN,
-  SYSCON_PU_EMIF_1_8_BIT_EN,
-  SYSCON_PU_EMIF_1_16_BIT_EN,
-  SYSCON_PU_EMIF_1_NFIF_READY_EN,
-  SYSCON_PU_EMIF_1_NFIF_WAIT_N_EN,
-};
-
-/*
- * Note that this array must match the order of the array "clk_reg"
- * in syscon.c
- */
-enum syscon_clk {
-  SYSCON_CLKCONTROL_SLOW_BRIDGE,
-  SYSCON_CLKCONTROL_UART,
-  SYSCON_CLKCONTROL_BTR,
-  SYSCON_CLKCONTROL_EH,
-  SYSCON_CLKCONTROL_GPIO,
-  SYSCON_CLKCONTROL_KEYPAD,
-  SYSCON_CLKCONTROL_APP_TIMER,
-  SYSCON_CLKCONTROL_ACC_TIMER,
-  SYSCON_CLKCONTROL_FAST_BRIDGE,
-  SYSCON_CLKCONTROL_I2C0,
-  SYSCON_CLKCONTROL_I2C1,
-  SYSCON_CLKCONTROL_I2S0,
-  SYSCON_CLKCONTROL_I2S1,
-  SYSCON_CLKCONTROL_MMC,
-  SYSCON_CLKCONTROL_SPI,
-  SYSCON_CLKCONTROL_I2S0_CORE,
-  SYSCON_CLKCONTROL_I2S1_CORE,
-  SYSCON_CLKCONTROL_UART1,
-  SYSCON_CLKCONTROL_AAIF,
-  SYSCON_CLKCONTROL_AHB,
-  SYSCON_CLKCONTROL_APEX,
-  SYSCON_CLKCONTROL_CPU,
-  SYSCON_CLKCONTROL_DMA,
-  SYSCON_CLKCONTROL_EMIF,
-  SYSCON_CLKCONTROL_NAND_IF,
-  SYSCON_CLKCONTROL_VIDEO_ENC,
-  SYSCON_CLKCONTROL_XGAM,
-  SYSCON_CLKCONTROL_SEMI,
-  SYSCON_CLKCONTROL_AHB_SUBSYS,
-  SYSCON_CLKCONTROL_MSPRO
-};
-
-enum syscon_sysclk_mode {
-  SYSCON_SYSCLK_DISABLED,
-  SYSCON_SYSCLK_M_CLK,
-  SYSCON_SYSCLK_ACC_FSM,
-  SYSCON_SYSCLK_PLL60_48,
-  SYSCON_SYSCLK_PLL60_60,
-  SYSCON_SYSCLK_ACC_PLL208,
-  SYSCON_SYSCLK_APP_PLL13,
-  SYSCON_SYSCLK_APP_FSM,
-  SYSCON_SYSCLK_RTC,
-  SYSCON_SYSCLK_APP_PLL208
-};
-
-enum syscon_sysclk_req {
-  SYSCON_SYSCLKREQ_DISABLED,
-  SYSCON_SYSCLKREQ_ACTIVE_LOW,
-  SYSCON_SYSCLKREQ_MONITOR
-};
-
-enum syscon_clk_mode {
-  SYSCON_CLKMODE_OFF,
-  SYSCON_CLKMODE_DEFAULT,
-  SYSCON_CLKMODE_LOW,
-  SYSCON_CLKMODE_MEDIUM,
-  SYSCON_CLKMODE_HIGH,
-  SYSCON_CLKMODE_PERMANENT,
-  SYSCON_CLKMODE_ON,
-};
-
-enum syscon_call_mode {
-  SYSCON_CLKCALL_NOWAIT,
-  SYSCON_CLKCALL_WAIT,
-};
-
-int syscon_dc_on(bool keep_power_on);
-int syscon_set_busmaster_active_state(enum syscon_busmaster busmaster,
-                                      bool active);
-bool syscon_get_busmaster_active_state(void);
-int syscon_set_sleep_mask(enum syscon_clk,
-                          bool sleep_ctrl);
-int syscon_config_sysclk(u32 sysclk,
-                         enum syscon_sysclk_mode sysclkmode,
-                         bool inverse,
-                         u32 divisor,
-                         enum syscon_sysclk_req sysclkreq);
-bool syscon_can_turn_off_semi_clock(void);
-
-/* This function is restricted to core.c */
-int syscon_request_normal_power(bool req);
-
-/* This function is restricted to be used by platform_speed.c */
-int syscon_speed_request(enum syscon_call_mode wait_mode,
-                         enum syscon_clk_mode req_clk_mode);
-#endif /* __MACH_SYSCON_H */
diff --git a/arch/arm/mach-u300/include/mach/timex.h b/arch/arm/mach-u300/include/mach/timex.h
deleted file mode 100644
index f233b72633f6..000000000000
--- a/arch/arm/mach-u300/include/mach/timex.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/timex.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Platform tick rate definition.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#ifndef __MACH_TIMEX_H
-#define __MACH_TIMEX_H
-
-/* This is for the APP OS GP1 (General Purpose 1) timer */
-#define CLOCK_TICK_RATE         1000000
-
-#endif
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h
deleted file mode 100644
index 0320495efc4d..000000000000
--- a/arch/arm/mach-u300/include/mach/u300-regs.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/u300-regs.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Basic register address definitions in physical memory and
- * some block definitions for core devices like the timer.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-
-#ifndef __MACH_U300_REGS_H
-#define __MACH_U300_REGS_H
-
-/*
- * These are the large blocks of memory allocated for I/O.
- * the defines are used for setting up the I/O memory mapping.
- */
-
-/* NAND Flash CS0 */
-#define U300_NAND_CS0_PHYS_BASE         0x80000000
-
-/* NFIF */
-#define U300_NAND_IF_PHYS_BASE          0x9f800000
-
-/* ALE, CLE offset for FSMC NAND */
-#define PLAT_NAND_CLE                   (1 << 16)
-#define PLAT_NAND_ALE                   (1 << 17)
-
-/* AHB Peripherals */
-#define U300_AHB_PER_PHYS_BASE          0xa0000000
-#define U300_AHB_PER_VIRT_BASE          0xff010000
-
-/* FAST Peripherals */
-#define U300_FAST_PER_PHYS_BASE         0xc0000000
-#define U300_FAST_PER_VIRT_BASE         0xff020000
-
-/* SLOW Peripherals */
-#define U300_SLOW_PER_PHYS_BASE         0xc0010000
-#define U300_SLOW_PER_VIRT_BASE         0xff000000
-
-/* Boot ROM */
-#define U300_BOOTROM_PHYS_BASE          0xffff0000
-#define U300_BOOTROM_VIRT_BASE          0xffff0000
-
-/* SEMI config base */
-#define U300_SEMI_CONFIG_BASE           0x2FFE0000
-
-/*
- * AHB peripherals
- */
-
-/* AHB Peripherals Bridge Controller */
-#define U300_AHB_BRIDGE_BASE            (U300_AHB_PER_PHYS_BASE+0x0000)
-
-/* Vectored Interrupt Controller 0, servicing 32 interrupts */
-#define U300_INTCON0_BASE               (U300_AHB_PER_PHYS_BASE+0x1000)
-#define U300_INTCON0_VBASE              IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
-
-/* Vectored Interrupt Controller 1, servicing 32 interrupts */
-#define U300_INTCON1_BASE               (U300_AHB_PER_PHYS_BASE+0x2000)
-#define U300_INTCON1_VBASE              IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
-
-/* Memory Stick Pro (MSPRO) controller */
-#define U300_MSPRO_BASE                 (U300_AHB_PER_PHYS_BASE+0x3000)
-
-/* EMIF Configuration Area */
-#define U300_EMIF_CFG_BASE              (U300_AHB_PER_PHYS_BASE+0x4000)
-
-
-/*
- * FAST peripherals
- */
-
-/* FAST bridge control */
-#define U300_FAST_BRIDGE_BASE           (U300_FAST_PER_PHYS_BASE+0x0000)
-
-/* MMC/SD controller */
-#define U300_MMCSD_BASE                 (U300_FAST_PER_PHYS_BASE+0x1000)
-
-/* PCM I2S0 controller */
-#define U300_PCM_I2S0_BASE              (U300_FAST_PER_PHYS_BASE+0x2000)
-
-/* PCM I2S1 controller */
-#define U300_PCM_I2S1_BASE              (U300_FAST_PER_PHYS_BASE+0x3000)
-
-/* I2C0 controller */
-#define U300_I2C0_BASE                  (U300_FAST_PER_PHYS_BASE+0x4000)
-
-/* I2C1 controller */
-#define U300_I2C1_BASE                  (U300_FAST_PER_PHYS_BASE+0x5000)
-
-/* SPI controller */
-#define U300_SPI_BASE                   (U300_FAST_PER_PHYS_BASE+0x6000)
-
-/* Fast UART1 on U335 only */
-#define U300_UART1_BASE                 (U300_FAST_PER_PHYS_BASE+0x7000)
-
-/*
- * SLOW peripherals
- */
-
-/* SLOW bridge control */
-#define U300_SLOW_BRIDGE_BASE           (U300_SLOW_PER_PHYS_BASE)
-
-/* SYSCON */
-#define U300_SYSCON_BASE                (U300_SLOW_PER_PHYS_BASE+0x1000)
-#define U300_SYSCON_VBASE               IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
-
-/* Watchdog */
-#define U300_WDOG_BASE                  (U300_SLOW_PER_PHYS_BASE+0x2000)
-
-/* UART0 */
-#define U300_UART0_BASE                 (U300_SLOW_PER_PHYS_BASE+0x3000)
-
-/* APP side special timer */
-#define U300_TIMER_APP_BASE             (U300_SLOW_PER_PHYS_BASE+0x4000)
-#define U300_TIMER_APP_VBASE            IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
-
-/* Keypad */
-#define U300_KEYPAD_BASE                (U300_SLOW_PER_PHYS_BASE+0x5000)
-
-/* GPIO */
-#define U300_GPIO_BASE                  (U300_SLOW_PER_PHYS_BASE+0x6000)
-
-/* RTC */
-#define U300_RTC_BASE                   (U300_SLOW_PER_PHYS_BASE+0x7000)
-
-/* Bus tracer */
-#define U300_BUSTR_BASE                 (U300_SLOW_PER_PHYS_BASE+0x8000)
-
-/* Event handler (hardware queue) */
-#define U300_EVHIST_BASE                (U300_SLOW_PER_PHYS_BASE+0x9000)
-
-/* Genric Timer */
-#define U300_TIMER_BASE                 (U300_SLOW_PER_PHYS_BASE+0xa000)
-
-/* PPM */
-#define U300_PPM_BASE                   (U300_SLOW_PER_PHYS_BASE+0xb000)
-
-
-/*
- * REST peripherals
- */
-
-/* ISP (image signal processor) */
-#define U300_ISP_BASE                   (0xA0008000)
-
-/* DMA Controller base */
-#define U300_DMAC_BASE                  (0xC0020000)
-
-/* MSL Base */
-#define U300_MSL_BASE                   (0xc0022000)
-
-/* APEX Base */
-#define U300_APEX_BASE                  (0xc0030000)
-
-/* Video Encoder Base */
-#define U300_VIDEOENC_BASE              (0xc0080000)
-
-/* XGAM Base */
-#define U300_XGAM_BASE                  (0xd0000000)
-
-#endif
diff --git a/arch/arm/mach-u300/include/mach/uncompress.h b/arch/arm/mach-u300/include/mach/uncompress.h
deleted file mode 100644
index 783e7e60101b..000000000000
--- a/arch/arm/mach-u300/include/mach/uncompress.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * arch/arm/mach-u300/include/mach/uncompress.h
- *
- * Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define AMBA_UART_DR    (*(volatile unsigned char *)0xc0013000)
-#define AMBA_UART_LCRH  (*(volatile unsigned char *)0xc001302C)
-#define AMBA_UART_CR    (*(volatile unsigned char *)0xc0013030)
-#define AMBA_UART_FR    (*(volatile unsigned char *)0xc0013018)
-
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
-        while (AMBA_UART_FR & (1 << 5))
-                barrier();
-
-        AMBA_UART_DR = c;
-}
-
-static inline void flush(void)
-{
-        while (AMBA_UART_FR & (1 << 3))
-                barrier();
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index 9c53f01c62eb..bf40cd478fe9 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -10,11 +10,18 @@
 #include <linux/device.h>
 #include <linux/signal.h>
 #include <linux/err.h>
+#include <linux/of.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/machine.h>
 #include <linux/regulator/consumer.h>
-/* Those are just for writing in syscon */
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/syscon.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+
+/* Power Management Control 16bit (R/W) */
+#define U300_SYSCON_PMCR                                        (0x50)
+#define U300_SYSCON_PMCR_DCON_ENABLE                            (0x0002)
+#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE                        (0x0001)
 
 /*
  * Regulators that power the board and chip and which are
@@ -47,13 +54,28 @@ void u300_pm_poweroff(void)
 /*
  * Hog the regulators needed to power up the board.
  */
-static int __init u300_init_boardpower(void)
+static int __init __u300_init_boardpower(struct platform_device *pdev)
 {
+        struct device_node *np = pdev->dev.of_node;
+        struct device_node *syscon_np;
+        struct regmap *regmap;
         int err;
-        u32 val;
 
         pr_info("U300: setting up board power\n");
-        main_power_15 = regulator_get(NULL, "vana15");
+
+        syscon_np = of_parse_phandle(np, "syscon", 0);
+        if (!syscon_np) {
+                pr_crit("U300: no syscon node\n");
+                return -ENODEV;
+        }
+        regmap = syscon_node_to_regmap(syscon_np);
+        if (!regmap) {
+                pr_crit("U300: could not locate syscon regmap\n");
+                return -ENODEV;
+        }
+
+        main_power_15 = regulator_get(&pdev->dev, "vana15");
+
         if (IS_ERR(main_power_15)) {
                 pr_err("could not get vana15");
                 return PTR_ERR(main_power_15);
@@ -72,9 +94,8 @@ static int __init u300_init_boardpower(void)
          * the rest of the U300 power management is implemented.
          */
         pr_info("U300: disable system controller pull-up\n");
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR);
-        val &= ~U300_SYSCON_PMCR_DCON_ENABLE;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
+        regmap_update_bits(regmap, U300_SYSCON_PMCR,
+                           U300_SYSCON_PMCR_DCON_ENABLE, 0);
 
         /* Register globally exported PM poweroff hook */
         pm_power_off = u300_pm_poweroff;
@@ -82,7 +103,31 @@ static int __init u300_init_boardpower(void)
         return 0;
 }
 
+static int __init s365_board_probe(struct platform_device *pdev)
+{
+        return __u300_init_boardpower(pdev);
+}
+
+static const struct of_device_id s365_board_match[] = {
+        { .compatible = "stericsson,s365" },
+        {},
+};
+
+static struct platform_driver s365_board_driver = {
+        .driver         = {
+                .name   = "s365-board",
+                .owner  = THIS_MODULE,
+                .of_match_table = s365_board_match,
+        },
+};
+
 /*
  * So at module init time we hog the regulator!
  */
-module_init(u300_init_boardpower);
+static int __init u300_init_boardpower(void)
+{
+        return platform_driver_probe(&s365_board_driver,
+                                     s365_board_probe);
+}
+
+device_initcall(u300_init_boardpower);
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
deleted file mode 100644
index 910698293d64..000000000000
--- a/arch/arm/mach-u300/spi.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * arch/arm/mach-u300/spi.c
- *
- * Copyright (C) 2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#include <linux/device.h>
-#include <linux/amba/bus.h>
-#include <linux/spi/spi.h>
-#include <linux/amba/pl022.h>
-#include <linux/platform_data/dma-coh901318.h>
-#include <linux/err.h>
-
-/*
- * The following is for the actual devices on the SSP/SPI bus
- */
-#ifdef CONFIG_MACH_U300_SPIDUMMY
-static void select_dummy_chip(u32 chipselect)
-{
-        pr_debug("CORE: %s called with CS=0x%x (%s)\n",
-                 __func__,
-                 chipselect,
-                 chipselect ? "unselect chip" : "select chip");
-        /*
-         * Here you would write the chip select value to the GPIO pins if
-         * this was a real chip (but this is a loopback dummy).
-         */
-}
-
-struct pl022_config_chip dummy_chip_info = {
-        /* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */
-        .com_mode = DMA_TRANSFER,
-        .iface = SSP_INTERFACE_MOTOROLA_SPI,
-        /* We can only act as master but SSP_SLAVE is possible in theory */
-        .hierarchy = SSP_MASTER,
-        /* 0 = drive TX even as slave, 1 = do not drive TX as slave */
-        .slave_tx_disable = 0,
-        .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM,
-        .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC,
-        .ctrl_len = SSP_BITS_12,
-        .wait_state = SSP_MWIRE_WAIT_ZERO,
-        .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
-        /*
-         * This is where you insert a call to a function to enable CS
-         * (usually GPIO) for a certain chip.
-         */
-        .cs_control = select_dummy_chip,
-};
-#endif
-
-static struct spi_board_info u300_spi_devices[] = {
-#ifdef CONFIG_MACH_U300_SPIDUMMY
-        {
-                /* A dummy chip used for loopback tests */
-                .modalias       = "spi-dummy",
-                /* Really dummy, pass in additional chip config here */
-                .platform_data  = NULL,
-                /* This defines how the controller shall handle the device */
-                .controller_data = &dummy_chip_info,
-                /* .irq - no external IRQ routed from this device */
-                .max_speed_hz   = 1000000,
-                .bus_num        = 0, /* Only one bus on this chip */
-                .chip_select    = 0,
-                /* Means SPI_CS_HIGH, change if e.g low CS */
-                .mode           = SPI_MODE_1 | SPI_LOOP,
-        },
-#endif
-};
-
-static struct pl022_ssp_controller ssp_platform_data = {
-        /* If you have several SPI buses this varies, we have only bus 0 */
-        .bus_id = 0,
-        /*
-         * On the APP CPU GPIO 4, 5 and 6 are connected as generic
-         * chip selects for SPI. (Same on U330, U335 and U365.)
-         * TODO: make sure the GPIO driver can select these properly
-         * and do padmuxing accordingly too.
-         */
-        .num_chipselect = 3,
-#ifdef CONFIG_COH901318
-        .enable_dma = 1,
-        .dma_filter = coh901318_filter_id,
-        .dma_rx_param = (void *) U300_DMA_SPI_RX,
-        .dma_tx_param = (void *) U300_DMA_SPI_TX,
-#else
-        .enable_dma = 0,
-#endif
-};
-
-
-void __init u300_spi_init(struct amba_device *adev)
-{
-        adev->dev.platform_data = &ssp_platform_data;
-}
-
-void __init u300_spi_register_board_devices(void)
-{
-        /* Register any SPI devices */
-        spi_register_board_info(u300_spi_devices, ARRAY_SIZE(u300_spi_devices));
-}
diff --git a/arch/arm/mach-u300/spi.h b/arch/arm/mach-u300/spi.h
deleted file mode 100644
index bd3d867e240f..000000000000
--- a/arch/arm/mach-u300/spi.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-u300/spi.h
- *
- * Copyright (C) 2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#ifndef SPI_H
-#define SPI_H
-#include <linux/amba/bus.h>
-
-#ifdef CONFIG_SPI_PL022
-void __init u300_spi_init(struct amba_device *adev);
-void __init u300_spi_register_board_devices(void);
-#else
-/* Compile out SPI support if PL022 is not selected */
-static inline void __init u300_spi_init(struct amba_device *adev)
-{
-}
-static inline void __init u300_spi_register_board_devices(void)
-{
-}
-#endif
-
-#endif
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index d9e73209c9b8..390ae5feb1d0 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -18,17 +18,15 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/irq.h>
-
-#include <mach/hardware.h>
-#include <mach/irqs.h>
+#include <linux/delay.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 /* Generic stuff */
 #include <asm/sched_clock.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 
-#include "timer.h"
-
 /*
  * APP side special timer registers
  * This timer contains four timers which can fire an interrupt each.
@@ -189,6 +187,8 @@
 #define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
 #define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
 
+static void __iomem *u300_timer_base;
+
 /*
  * The u300_set_mode() function is always called first, if we
  * have oneshot timer active, the oneshot scheduling function
@@ -201,28 +201,28 @@ static void u300_set_mode(enum clock_event_mode mode,
         case CLOCK_EVT_MODE_PERIODIC:
                 /* Disable interrupts on GPT1 */
                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+                       u300_timer_base + U300_TIMER_APP_GPT1IE);
                 /* Disable GP1 while we're reprogramming it. */
                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+                       u300_timer_base + U300_TIMER_APP_DGPT1);
                 /*
                  * Set the periodic mode to a certain number of ticks per
                  * jiffy.
                  */
                 writel(TICKS_PER_JIFFY,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+                       u300_timer_base + U300_TIMER_APP_GPT1TC);
                 /*
                  * Set continuous mode, so the timer keeps triggering
                  * interrupts.
                  */
                 writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+                       u300_timer_base + U300_TIMER_APP_SGPT1M);
                 /* Enable timer interrupts */
                 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+                       u300_timer_base + U300_TIMER_APP_GPT1IE);
                 /* Then enable the OS timer again */
                 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+                       u300_timer_base + U300_TIMER_APP_EGPT1);
                 break;
         case CLOCK_EVT_MODE_ONESHOT:
                 /* Just break; here? */
@@ -233,33 +233,33 @@ static void u300_set_mode(enum clock_event_mode mode,
                  */
                 /* Disable interrupts on GPT1 */
                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+                       u300_timer_base + U300_TIMER_APP_GPT1IE);
                 /* Disable GP1 while we're reprogramming it. */
                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+                       u300_timer_base + U300_TIMER_APP_DGPT1);
                 /*
                  * Expire far in the future, u300_set_next_event() will be
                  * called soon...
                  */
-                writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+                writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC);
                 /* We run one shot per tick here! */
                 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+                       u300_timer_base + U300_TIMER_APP_SGPT1M);
                 /* Enable interrupts for this timer */
                 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+                       u300_timer_base + U300_TIMER_APP_GPT1IE);
                 /* Enable timer */
                 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+                       u300_timer_base + U300_TIMER_APP_EGPT1);
                 break;
         case CLOCK_EVT_MODE_UNUSED:
         case CLOCK_EVT_MODE_SHUTDOWN:
                 /* Disable interrupts on GP1 */
                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+                       u300_timer_base + U300_TIMER_APP_GPT1IE);
                 /* Disable GP1 */
                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+                       u300_timer_base + U300_TIMER_APP_DGPT1);
                 break;
         case CLOCK_EVT_MODE_RESUME:
                 /* Ignore this call */
@@ -281,27 +281,27 @@ static int u300_set_next_event(unsigned long cycles,
 {
         /* Disable interrupts on GPT1 */
         writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+               u300_timer_base + U300_TIMER_APP_GPT1IE);
         /* Disable GP1 while we're reprogramming it. */
         writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+               u300_timer_base + U300_TIMER_APP_DGPT1);
         /* Reset the General Purpose timer 1. */
         writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
+               u300_timer_base + U300_TIMER_APP_RGPT1);
         /* IRQ in n * cycles */
-        writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+        writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC);
         /*
          * We run one shot per tick here! (This is necessary to reconfigure,
          * the timer will tilt if you don't!)
          */
         writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+               u300_timer_base + U300_TIMER_APP_SGPT1M);
         /* Enable timer interrupts */
         writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+               u300_timer_base + U300_TIMER_APP_GPT1IE);
         /* Then enable the OS timer again */
         writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+               u300_timer_base + U300_TIMER_APP_EGPT1);
         return 0;
 }
 
@@ -320,8 +320,9 @@ static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
 {
         struct clock_event_device *evt = &clockevent_u300_1mhz;
         /* ACK/Clear timer IRQ for the APP GPT1 Timer */
+
         writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA);
+                u300_timer_base + U300_TIMER_APP_GPT1IA);
         evt->event_handler(evt);
         return IRQ_HANDLED;
 }
@@ -342,65 +343,88 @@ static struct irqaction u300_timer_irq = {
 
 static u32 notrace u300_read_sched_clock(void)
 {
-        return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
+        return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
+}
+
+static unsigned long u300_read_current_timer(void)
+{
+        return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
 }
 
+static struct delay_timer u300_delay_timer;
 
 /*
  * This sets up the system timers, clock source and clock event.
  */
-void __init u300_timer_init(void)
+static void __init u300_timer_init_of(struct device_node *np)
 {
+        struct resource irq_res;
+        int irq;
         struct clk *clk;
         unsigned long rate;
 
+        u300_timer_base = of_iomap(np, 0);
+        if (!u300_timer_base)
+                panic("could not ioremap system timer\n");
+
+        /* Get the IRQ for the GP1 timer */
+        irq = of_irq_to_resource(np, 2, &irq_res);
+        if (irq <= 0)
+                panic("no IRQ for system timer\n");
+
+        pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
+
         /* Clock the interrupt controller */
-        clk = clk_get_sys("apptimer", NULL);
+        clk = of_clk_get(np, 0);
         BUG_ON(IS_ERR(clk));
         clk_prepare_enable(clk);
         rate = clk_get_rate(clk);
 
         setup_sched_clock(u300_read_sched_clock, 32, rate);
 
+        u300_delay_timer.read_current_timer = &u300_read_current_timer;
+        u300_delay_timer.freq = rate;
+        register_current_timer_delay(&u300_delay_timer);
+
         /*
          * Disable the "OS" and "DD" timers - these are designed for Symbian!
          * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
          */
         writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC);
+                u300_timer_base + U300_TIMER_APP_CRC);
         writel(U300_TIMER_APP_ROST_TIMER_RESET,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST);
+                u300_timer_base + U300_TIMER_APP_ROST);
         writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST);
+                u300_timer_base + U300_TIMER_APP_DOST);
         writel(U300_TIMER_APP_RDDT_TIMER_RESET,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT);
+                u300_timer_base + U300_TIMER_APP_RDDT);
         writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT);
+                u300_timer_base + U300_TIMER_APP_DDDT);
 
         /* Reset the General Purpose timer 1. */
         writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
+                u300_timer_base + U300_TIMER_APP_RGPT1);
 
         /* Set up the IRQ handler */
-        setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq);
+        setup_irq(irq, &u300_timer_irq);
 
         /* Reset the General Purpose timer 2 */
         writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2);
+                u300_timer_base + U300_TIMER_APP_RGPT2);
         /* Set this timer to run around forever */
-        writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC);
+        writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC);
         /* Set continuous mode so it wraps around */
         writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M);
+               u300_timer_base + U300_TIMER_APP_SGPT2M);
         /* Disable timer interrupts */
         writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE);
+                u300_timer_base + U300_TIMER_APP_GPT2IE);
         /* Then enable the GP2 timer to use as a free running us counter */
         writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
+                u300_timer_base + U300_TIMER_APP_EGPT2);
 
         /* Use general purpose timer 2 as clock source */
-        if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC,
+        if (clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC,
                         "GPT2", rate, 300, 32, clocksource_mmio_readl_up))
                 pr_err("timer: failed to initialize U300 clock source\n");
 
@@ -413,3 +437,6 @@ void __init u300_timer_init(void)
          * used by hrtimers!
          */
 }
+
+CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
+                       u300_timer_init_of);
diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h
deleted file mode 100644
index d34287bc34f5..000000000000
--- a/arch/arm/mach-u300/timer.h
+++ /dev/null
@@ -1 +0,0 @@
-extern void u300_timer_init(void);
diff --git a/arch/arm/mach-u300/u300-gpio.h b/arch/arm/mach-u300/u300-gpio.h
deleted file mode 100644
index 83f50772e169..000000000000
--- a/arch/arm/mach-u300/u300-gpio.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Individual pin assignments for the B335/S335.
- * Notice that the actual usage of these pins depends on the
- * PAD MUX settings, that is why the same number can potentially
- * appear several times. In the reference design each pin is only
- * used for one purpose. These were determined by inspecting the
- * S365 schematic.
- */
-#define U300_GPIO_PIN_UART_RX           0
-#define U300_GPIO_PIN_UART_TX           1
-#define U300_GPIO_PIN_UART_CTS          2
-#define U300_GPIO_PIN_UART_RTS          3
-#define U300_GPIO_PIN_CAM_MAIN_STANDBY  4 /* Camera MAIN standby */
-#define U300_GPIO_PIN_GPIO05            5 /* Unrouted */
-#define U300_GPIO_PIN_MS_CD             6 /* Memory Stick Card insertion */
-#define U300_GPIO_PIN_GPIO07            7 /* Test point TP2430 */
-
-#define U300_GPIO_PIN_GPIO08            8 /* Test point TP2437 */
-#define U300_GPIO_PIN_GPIO09            9 /* Test point TP2431 */
-#define U300_GPIO_PIN_GPIO10            10 /* Test point TP2432 */
-#define U300_GPIO_PIN_MMC_CLKRET        11 /* Clock return from MMC/SD card */
-#define U300_GPIO_PIN_MMC_CD            12 /* MMC Card insertion detection */
-#define U300_GPIO_PIN_CAM_SUB_STANDBY   13 /* Camera SUB standby */
-#define U300_GPIO_PIN_GPIO14            14 /* Test point TP2436 */
-#define U300_GPIO_PIN_GPIO15            15 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO16            16 /* Test point TP2438 */
-#define U300_GPIO_PIN_PHFSENSE          17 /* Headphone jack sensing */
-#define U300_GPIO_PIN_GPIO18            18 /* Test point TP2439 */
-#define U300_GPIO_PIN_GPIO19            19 /* Routed somewhere */
-#define U300_GPIO_PIN_GPIO20            20 /* Unrouted */
-#define U300_GPIO_PIN_GPIO21            21 /* Unrouted */
-#define U300_GPIO_PIN_GPIO22            22 /* Unrouted */
-#define U300_GPIO_PIN_GPIO23            23 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO24            24 /* Unrouted */
-#define U300_GPIO_PIN_GPIO25            25 /* Unrouted */
-#define U300_GPIO_PIN_GPIO26            26 /* Unrouted */
-#define U300_GPIO_PIN_GPIO27            27 /* Unrouted */
-#define U300_GPIO_PIN_GPIO28            28 /* Unrouted */
-#define U300_GPIO_PIN_GPIO29            29 /* Unrouted */
-#define U300_GPIO_PIN_GPIO30            30 /* Unrouted */
-#define U300_GPIO_PIN_GPIO31            31 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO32            32 /* Unrouted */
-#define U300_GPIO_PIN_GPIO33            33 /* Unrouted */
-#define U300_GPIO_PIN_GPIO34            34 /* Unrouted */
-#define U300_GPIO_PIN_GPIO35            35 /* Unrouted */
-#define U300_GPIO_PIN_GPIO36            36 /* Unrouted */
-#define U300_GPIO_PIN_GPIO37            37 /* Unrouted */
-#define U300_GPIO_PIN_GPIO38            38 /* Unrouted */
-#define U300_GPIO_PIN_GPIO39            39 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO40            40 /* Unrouted */
-#define U300_GPIO_PIN_GPIO41            41 /* Unrouted */
-#define U300_GPIO_PIN_GPIO42            42 /* Unrouted */
-#define U300_GPIO_PIN_GPIO43            43 /* Unrouted */
-#define U300_GPIO_PIN_GPIO44            44 /* Unrouted */
-#define U300_GPIO_PIN_GPIO45            45 /* Unrouted */
-#define U300_GPIO_PIN_GPIO46            46 /* Unrouted */
-#define U300_GPIO_PIN_GPIO47            47 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO48            48 /* Unrouted */
-#define U300_GPIO_PIN_GPIO49            49 /* Unrouted */
-#define U300_GPIO_PIN_GPIO50            50 /* Unrouted */
-#define U300_GPIO_PIN_GPIO51            51 /* Unrouted */
-#define U300_GPIO_PIN_GPIO52            52 /* Unrouted */
-#define U300_GPIO_PIN_GPIO53            53 /* Unrouted */
-#define U300_GPIO_PIN_GPIO54            54 /* Unrouted */
-#define U300_GPIO_PIN_GPIO55            55 /* Unrouted */
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index 33c353bc1c4a..d6b7c8556fa1 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -374,6 +374,7 @@ static struct ab8500_regulator_reg_init ab8500_reg_init[] = {
 static struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
         /* supplies to the display/camera */
         [AB8500_LDO_AUX1] = {
+                .supply_regulator = "ab8500-ext-supply3",
                 .constraints = {
                         .name = "V-DISPLAY",
                         .min_uV = 2800000,
@@ -387,6 +388,7 @@ static struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
         },
         /* supplies to the on-board eMMC */
         [AB8500_LDO_AUX2] = {
+                .supply_regulator = "ab8500-ext-supply3",
                 .constraints = {
                         .name = "V-eMMC1",
                         .min_uV = 1100000,
@@ -402,6 +404,7 @@ static struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
         },
         /* supply for VAUX3, supplies to SDcard slots */
         [AB8500_LDO_AUX3] = {
+                .supply_regulator = "ab8500-ext-supply3",
                 .constraints = {
                         .name = "V-MMC-SD",
                         .min_uV = 1100000,
diff --git a/arch/arm/mach-ux500/cpuidle.c b/arch/arm/mach-ux500/cpuidle.c
index 317a2be129fb..a45dd09daed9 100644
--- a/arch/arm/mach-ux500/cpuidle.c
+++ b/arch/arm/mach-ux500/cpuidle.c
@@ -21,6 +21,7 @@
 #include <asm/proc-fns.h>
 
 #include "db8500-regs.h"
+#include "id.h"
 
 static atomic_t master = ATOMIC_INIT(0);
 static DEFINE_SPINLOCK(master_lock);
@@ -114,6 +115,9 @@ static struct cpuidle_driver ux500_idle_driver = {
 
 int __init ux500_idle_init(void)
 {
+        if (!(cpu_is_u8500_family() || cpu_is_ux540_family()))
+                return -ENODEV;
+
         /* Configure wake up reasons */
         prcmu_enable_wakeups(PRCMU_WAKEUP(ARM) | PRCMU_WAKEUP(RTC) |
                              PRCMU_WAKEUP(ABB));
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 5907e10c37fd..b8bbabec6310 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -57,4 +57,13 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
 config ARCH_VEXPRESS_CA9X4
         bool "Versatile Express Cortex-A9x4 tile"
 
+config ARCH_VEXPRESS_DCSCB
+        bool "Dual Cluster System Control Block (DCSCB) support"
+        depends on MCPM
+        select ARM_CCI
+        help
+          Support for the Dual Cluster System Configuration Block (DCSCB).
+          This is needed to provide CPU and cluster power management
+          on RTSM implementing big.LITTLE.
+
 endmenu
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 42703e8b4d3b..48ba89a8149f 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -6,5 +6,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
 
 obj-y                                   := v2m.o
 obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)       += ct-ca9x4.o
+obj-$(CONFIG_ARCH_VEXPRESS_DCSCB)       += dcscb.o      dcscb_setup.o
 obj-$(CONFIG_SMP)                       += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index f134cd4a85f1..bde4374ab6d5 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -6,6 +6,8 @@
 
 void vexpress_dt_smp_map_io(void);
 
+bool vexpress_smp_init_ops(void);
+
 extern struct smp_operations    vexpress_smp_ops;
 
 extern void vexpress_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
new file mode 100644
index 000000000000..16d57a8a9d5a
--- /dev/null
+++ b/arch/arm/mach-vexpress/dcscb.c
@@ -0,0 +1,253 @@
+/*
+ * arch/arm/mach-vexpress/dcscb.c - Dual Cluster System Configuration Block
+ *
+ * Created by:  Nicolas Pitre, May 2012
+ * Copyright:   (C) 2012-2013  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/errno.h>
+#include <linux/of_address.h>
+#include <linux/vexpress.h>
+#include <linux/arm-cci.h>
+
+#include <asm/mcpm.h>
+#include <asm/proc-fns.h>
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
+#include <asm/cp15.h>
+
+
+#define RST_HOLD0       0x0
+#define RST_HOLD1       0x4
+#define SYS_SWRESET     0x8
+#define RST_STAT0       0xc
+#define RST_STAT1       0x10
+#define EAG_CFG_R       0x20
+#define EAG_CFG_W       0x24
+#define KFC_CFG_R       0x28
+#define KFC_CFG_W       0x2c
+#define DCS_CFG_R       0x30
+
+/*
+ * We can't use regular spinlocks. In the switcher case, it is possible
+ * for an outbound CPU to call power_down() while its inbound counterpart
+ * is already live using the same logical CPU number which trips lockdep
+ * debugging.
+ */
+static arch_spinlock_t dcscb_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+
+static void __iomem *dcscb_base;
+static int dcscb_use_count[4][2];
+static int dcscb_allcpus_mask[2];
+
+static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
+{
+        unsigned int rst_hold, cpumask = (1 << cpu);
+        unsigned int all_mask = dcscb_allcpus_mask[cluster];
+
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        if (cpu >= 4 || cluster >= 2)
+                return -EINVAL;
+
+        /*
+         * Since this is called with IRQs enabled, and no arch_spin_lock_irq
+         * variant exists, we need to disable IRQs manually here.
+         */
+        local_irq_disable();
+        arch_spin_lock(&dcscb_lock);
+
+        dcscb_use_count[cpu][cluster]++;
+        if (dcscb_use_count[cpu][cluster] == 1) {
+                rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
+                if (rst_hold & (1 << 8)) {
+                        /* remove cluster reset and add individual CPU's reset */
+                        rst_hold &= ~(1 << 8);
+                        rst_hold |= all_mask;
+                }
+                rst_hold &= ~(cpumask | (cpumask << 4));
+                writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
+        } else if (dcscb_use_count[cpu][cluster] != 2) {
+                /*
+                 * The only possible values are:
+                 * 0 = CPU down
+                 * 1 = CPU (still) up
+                 * 2 = CPU requested to be up before it had a chance
+                 *     to actually make itself down.
+                 * Any other value is a bug.
+                 */
+                BUG();
+        }
+
+        arch_spin_unlock(&dcscb_lock);
+        local_irq_enable();
+
+        return 0;
+}
+
+static void dcscb_power_down(void)
+{
+        unsigned int mpidr, cpu, cluster, rst_hold, cpumask, all_mask;
+        bool last_man = false, skip_wfi = false;
+
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+        cpumask = (1 << cpu);
+        all_mask = dcscb_allcpus_mask[cluster];
+
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        BUG_ON(cpu >= 4 || cluster >= 2);
+
+        __mcpm_cpu_going_down(cpu, cluster);
+
+        arch_spin_lock(&dcscb_lock);
+        BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+        dcscb_use_count[cpu][cluster]--;
+        if (dcscb_use_count[cpu][cluster] == 0) {
+                rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
+                rst_hold |= cpumask;
+                if (((rst_hold | (rst_hold >> 4)) & all_mask) == all_mask) {
+                        rst_hold |= (1 << 8);
+                        last_man = true;
+                }
+                writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
+        } else if (dcscb_use_count[cpu][cluster] == 1) {
+                /*
+                 * A power_up request went ahead of us.
+                 * Even if we do not want to shut this CPU down,
+                 * the caller expects a certain state as if the WFI
+                 * was aborted.  So let's continue with cache cleaning.
+                 */
+                skip_wfi = true;
+        } else
+                BUG();
+
+        if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
+                arch_spin_unlock(&dcscb_lock);
+
+                /*
+                 * Flush all cache levels for this cluster.
+                 *
+                 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
+                 * a preliminary flush here for those CPUs.  At least, that's
+                 * the theory -- without the extra flush, Linux explodes on
+                 * RTSM (to be investigated).
+                 */
+                flush_cache_all();
+                set_cr(get_cr() & ~CR_C);
+                flush_cache_all();
+
+                /*
+                 * This is a harmless no-op.  On platforms with a real
+                 * outer cache this might either be needed or not,
+                 * depending on where the outer cache sits.
+                 */
+                outer_flush_all();
+
+                /* Disable local coherency by clearing the ACTLR "SMP" bit: */
+                set_auxcr(get_auxcr() & ~(1 << 6));
+
+                /*
+                 * Disable cluster-level coherency by masking
+                 * incoming snoops and DVM messages:
+                 */
+                cci_disable_port_by_cpu(mpidr);
+
+                __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+        } else {
+                arch_spin_unlock(&dcscb_lock);
+
+                /*
+                 * Flush the local CPU cache.
+                 *
+                 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
+                 * a preliminary flush here for those CPUs.  At least, that's
+                 * the theory -- without the extra flush, Linux explodes on
+                 * RTSM (to be investigated).
+                 */
+                flush_cache_louis();
+                set_cr(get_cr() & ~CR_C);
+                flush_cache_louis();
+
+                /* Disable local coherency by clearing the ACTLR "SMP" bit: */
+                set_auxcr(get_auxcr() & ~(1 << 6));
+        }
+
+        __mcpm_cpu_down(cpu, cluster);
+
+        /* Now we are prepared for power-down, do it: */
+        dsb();
+        if (!skip_wfi)
+                wfi();
+
+        /* Not dead at this point?  Let our caller cope. */
+}
+
+static const struct mcpm_platform_ops dcscb_power_ops = {
+        .power_up       = dcscb_power_up,
+        .power_down     = dcscb_power_down,
+};
+
+static void __init dcscb_usage_count_init(void)
+{
+        unsigned int mpidr, cpu, cluster;
+
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        BUG_ON(cpu >= 4 || cluster >= 2);
+        dcscb_use_count[cpu][cluster] = 1;
+}
+
+extern void dcscb_power_up_setup(unsigned int affinity_level);
+
+static int __init dcscb_init(void)
+{
+        struct device_node *node;
+        unsigned int cfg;
+        int ret;
+
+        if (!cci_probed())
+                return -ENODEV;
+
+        node = of_find_compatible_node(NULL, NULL, "arm,rtsm,dcscb");
+        if (!node)
+                return -ENODEV;
+        dcscb_base = of_iomap(node, 0);
+        if (!dcscb_base)
+                return -EADDRNOTAVAIL;
+        cfg = readl_relaxed(dcscb_base + DCS_CFG_R);
+        dcscb_allcpus_mask[0] = (1 << (((cfg >> 16) >> (0 << 2)) & 0xf)) - 1;
+        dcscb_allcpus_mask[1] = (1 << (((cfg >> 16) >> (1 << 2)) & 0xf)) - 1;
+        dcscb_usage_count_init();
+
+        ret = mcpm_platform_register(&dcscb_power_ops);
+        if (!ret)
+                ret = mcpm_sync_init(dcscb_power_up_setup);
+        if (ret) {
+                iounmap(dcscb_base);
+                return ret;
+        }
+
+        pr_info("VExpress DCSCB support installed\n");
+
+        /*
+         * Future entries into the kernel can now go
+         * through the cluster entry vectors.
+         */
+        vexpress_flags_set(virt_to_phys(mcpm_entry_point));
+
+        return 0;
+}
+
+early_initcall(dcscb_init);
diff --git a/arch/arm/mach-vexpress/dcscb_setup.S b/arch/arm/mach-vexpress/dcscb_setup.S
new file mode 100644
index 000000000000..4bb7fbe0f621
--- /dev/null
+++ b/arch/arm/mach-vexpress/dcscb_setup.S
@@ -0,0 +1,38 @@
+/*
+ * arch/arm/include/asm/dcscb_setup.S
+ *
+ * Created by:  Dave Martin, 2012-06-22
+ * Copyright:   (C) 2012-2013  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+
+
+ENTRY(dcscb_power_up_setup)
+
+        cmp     r0, #0                  @ check affinity level
+        beq     2f
+
+/*
+ * Enable cluster-level coherency, in preparation for turning on the MMU.
+ * The ACTLR SMP bit does not need to be set here, because cpu_resume()
+ * already restores that.
+ *
+ * A15/A7 may not require explicit L2 invalidation on reset, dependent
+ * on hardware integration decisions.
+ * For now, this code assumes that L2 is either already invalidated,
+ * or invalidation is not required.
+ */
+
+        b       cci_enable_port_for_self
+
+2:      @ Implementation-specific local CPU setup operations should go here,
+        @ if any.  In this case, there is nothing to do.
+
+        bx      lr
+
+ENDPROC(dcscb_power_up_setup)
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index dc1ace55d557..993c9ae5dc5e 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -12,9 +12,11 @@
 #include <linux/errno.h>
 #include <linux/smp.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <linux/of_fdt.h>
 #include <linux/vexpress.h>
 
+#include <asm/mcpm.h>
 #include <asm/smp_scu.h>
 #include <asm/mach/map.h>
 
@@ -203,3 +205,21 @@ struct smp_operations __initdata vexpress_smp_ops = {
         .cpu_die                = vexpress_cpu_die,
 #endif
 };
+
+bool __init vexpress_smp_init_ops(void)
+{
+#ifdef CONFIG_MCPM
+        /*
+         * The best way to detect a multi-cluster configuration at the moment
+         * is to look for the presence of a CCI in the system.
+         * Override the default vexpress_smp_ops if so.
+         */
+        struct device_node *node;
+        node = of_find_compatible_node(NULL, NULL, "arm,cci-400");
+        if (node && of_device_is_available(node)) {
+                mcpm_smp_set_ops();
+                return true;
+        }
+#endif
+        return false;
+}
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 8802030df98d..b0eccf7e06ec 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -456,6 +456,7 @@ static const char * const v2m_dt_match[] __initconst = {
 DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
         .dt_compat      = v2m_dt_match,
         .smp            = smp_ops(vexpress_smp_ops),
+        .smp_init       = smp_init_ops(vexpress_smp_init_ops),
         .map_io         = v2m_dt_map_io,
         .init_early     = v2m_dt_init_early,
         .init_irq       = irqchip_init,
diff --git a/arch/arm/mach-virt/Makefile b/arch/arm/mach-virt/Makefile
index 042afc1f8c44..7ddbfa60227f 100644
--- a/arch/arm/mach-virt/Makefile
+++ b/arch/arm/mach-virt/Makefile
@@ -3,4 +3,3 @@
 #
 
 obj-y                                   := virt.o
-obj-$(CONFIG_SMP)                       += platsmp.o
diff --git a/arch/arm/mach-virt/platsmp.c b/arch/arm/mach-virt/platsmp.c
deleted file mode 100644
index f4143f5bfa5b..000000000000
--- a/arch/arm/mach-virt/platsmp.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Dummy Virtual Machine - does what it says on the tin.
- *
- * Copyright (C) 2012 ARM Ltd
- * Author: Will Deacon <will.deacon@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/of.h>
-
-#include <asm/psci.h>
-#include <asm/smp_plat.h>
-
-extern void secondary_startup(void);
-
-static void __init virt_smp_init_cpus(void)
-{
-}
-
-static void __init virt_smp_prepare_cpus(unsigned int max_cpus)
-{
-}
-
-static int __cpuinit virt_boot_secondary(unsigned int cpu,
-                                         struct task_struct *idle)
-{
-        if (psci_ops.cpu_on)
-                return psci_ops.cpu_on(cpu_logical_map(cpu),
-                                       __pa(secondary_startup));
-        return -ENODEV;
-}
-
-struct smp_operations __initdata virt_smp_ops = {
-        .smp_init_cpus          = virt_smp_init_cpus,
-        .smp_prepare_cpus       = virt_smp_prepare_cpus,
-        .smp_boot_secondary     = virt_boot_secondary,
-};
diff --git a/arch/arm/mach-virt/virt.c b/arch/arm/mach-virt/virt.c
index 061f283f579e..a67d2dd5bb60 100644
--- a/arch/arm/mach-virt/virt.c
+++ b/arch/arm/mach-virt/virt.c
@@ -36,11 +36,8 @@ static const char *virt_dt_match[] = {
         NULL
 };
 
-extern struct smp_operations virt_smp_ops;
-
 DT_MACHINE_START(VIRT, "Dummy Virtual Machine")
         .init_irq       = irqchip_init,
         .init_machine   = virt_init,
-        .smp            = smp_ops(virt_smp_ops),
         .dt_compat      = virt_dt_match,
 MACHINE_END
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index c70969b9c258..50d008d8f87f 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -117,7 +117,7 @@ int __init zynq_slcr_init(void)
 
         pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
 
-        xilinx_zynq_clocks_init(zynq_slcr_base);
+        zynq_clock_init(zynq_slcr_base);
 
         of_node_put(np);
 
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 35955b54944c..9e8101ecd63e 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -397,6 +397,15 @@ config CPU_V7
         select CPU_PABRT_V7
         select CPU_TLB_V7 if MMU
 
+# ARMv7M
+config CPU_V7M
+        bool
+        select CPU_32v7M
+        select CPU_ABRT_NOMMU
+        select CPU_CACHE_NOP
+        select CPU_PABRT_LEGACY
+        select CPU_THUMBONLY
+
 config CPU_THUMBONLY
         bool
         # There are no CPUs available with MMU that don't implement an ARM ISA:
@@ -441,6 +450,9 @@ config CPU_32v6K
 config CPU_32v7
         bool
 
+config CPU_32v7M
+        bool
+
 # The abort model
 config CPU_ABRT_NOMMU
         bool
@@ -491,6 +503,9 @@ config CPU_CACHE_V6
 config CPU_CACHE_V7
         bool
 
+config CPU_CACHE_NOP
+        bool
+
 config CPU_CACHE_VIVT
         bool
 
@@ -613,7 +628,11 @@ config ARCH_DMA_ADDR_T_64BIT
 
 config ARM_THUMB
         bool "Support Thumb user binaries" if !CPU_THUMBONLY
-        depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON
+        depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \
+                CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \
+                CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
+                CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \
+                CPU_V7 || CPU_FEROCEON || CPU_V7M
         default y
         help
           Say Y if you want to include kernel support for running user space
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 9e51be96f635..ee558a01f390 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_CPU_CACHE_V4WB)	+= cache-v4wb.o
 obj-$(CONFIG_CPU_CACHE_V6)      += cache-v6.o
 obj-$(CONFIG_CPU_CACHE_V7)      += cache-v7.o
 obj-$(CONFIG_CPU_CACHE_FA)      += cache-fa.o
+obj-$(CONFIG_CPU_CACHE_NOP)     += cache-nop.o
 
 AFLAGS_cache-v6.o       :=-Wa,-march=armv6
 AFLAGS_cache-v7.o       :=-Wa,-march=armv7-a
@@ -87,6 +88,7 @@ obj-$(CONFIG_CPU_FEROCEON)	+= proc-feroceon.o
 obj-$(CONFIG_CPU_V6)            += proc-v6.o
 obj-$(CONFIG_CPU_V6K)           += proc-v6.o
 obj-$(CONFIG_CPU_V7)            += proc-v7.o
+obj-$(CONFIG_CPU_V7M)           += proc-v7m.o
 
 AFLAGS_proc-v6.o        :=-Wa,-march=armv6
 AFLAGS_proc-v7.o        :=-Wa,-march=armv7-a
diff --git a/arch/arm/mm/cache-nop.S b/arch/arm/mm/cache-nop.S
new file mode 100644
index 000000000000..8e12ddca0031
--- /dev/null
+++ b/arch/arm/mm/cache-nop.S
@@ -0,0 +1,50 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+#include "proc-macros.S"
+
+ENTRY(nop_flush_icache_all)
+        mov     pc, lr
+ENDPROC(nop_flush_icache_all)
+
+        .globl nop_flush_kern_cache_all
+        .equ nop_flush_kern_cache_all, nop_flush_icache_all
+
+        .globl nop_flush_kern_cache_louis
+        .equ nop_flush_kern_cache_louis, nop_flush_icache_all
+
+        .globl nop_flush_user_cache_all
+        .equ nop_flush_user_cache_all, nop_flush_icache_all
+
+        .globl nop_flush_user_cache_range
+        .equ nop_flush_user_cache_range, nop_flush_icache_all
+
+        .globl nop_coherent_kern_range
+        .equ nop_coherent_kern_range, nop_flush_icache_all
+
+ENTRY(nop_coherent_user_range)
+        mov     r0, 0
+        mov     pc, lr
+ENDPROC(nop_coherent_user_range)
+
+        .globl nop_flush_kern_dcache_area
+        .equ nop_flush_kern_dcache_area, nop_flush_icache_all
+
+        .globl nop_dma_flush_range
+        .equ nop_dma_flush_range, nop_flush_icache_all
+
+        .globl nop_dma_map_area
+        .equ nop_dma_map_area, nop_flush_icache_all
+
+        .globl nop_dma_unmap_area
+        .equ nop_dma_unmap_area, nop_flush_icache_all
+
+        __INITDATA
+
+        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+        define_cache_functions nop
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index d51225f90ae2..dd3a6c670f08 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -20,12 +20,19 @@
 
 void __init arm_mm_memblock_reserve(void)
 {
+#ifndef CONFIG_CPU_V7M
         /*
          * Register the exception vector page.
          * some architectures which the DRAM is the exception vector to trap,
          * alloc_page breaks with error, although it is not NULL, but "0."
          */
         memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
+#else /* ifndef CONFIG_CPU_V7M */
+        /*
+         * There is no dedicated vector page on V7-M. So nothing needs to be
+         * reserved here.
+         */
+#endif
 }
 
 void __init sanity_check_meminfo(void)
diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
new file mode 100644
index 000000000000..0c93588fcb91
--- /dev/null
+++ b/arch/arm/mm/proc-v7m.S
@@ -0,0 +1,157 @@
+/*
+ *  linux/arch/arm/mm/proc-v7m.S
+ *
+ *  Copyright (C) 2008 ARM Ltd.
+ *  Copyright (C) 2001 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This is the "shell" of the ARMv7-M processor support.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/v7m.h>
+#include "proc-macros.S"
+
+ENTRY(cpu_v7m_proc_init)
+        mov     pc, lr
+ENDPROC(cpu_v7m_proc_init)
+
+ENTRY(cpu_v7m_proc_fin)
+        mov     pc, lr
+ENDPROC(cpu_v7m_proc_fin)
+
+/*
+ *      cpu_v7m_reset(loc)
+ *
+ *      Perform a soft reset of the system.  Put the CPU into the
+ *      same state as it would be if it had been reset, and branch
+ *      to what would be the reset vector.
+ *
+ *      - loc   - location to jump to for soft reset
+ */
+        .align  5
+ENTRY(cpu_v7m_reset)
+        mov     pc, r0
+ENDPROC(cpu_v7m_reset)
+
+/*
+ *      cpu_v7m_do_idle()
+ *
+ *      Idle the processor (eg, wait for interrupt).
+ *
+ *      IRQs are already disabled.
+ */
+ENTRY(cpu_v7m_do_idle)
+        wfi
+        mov     pc, lr
+ENDPROC(cpu_v7m_do_idle)
+
+ENTRY(cpu_v7m_dcache_clean_area)
+        mov     pc, lr
+ENDPROC(cpu_v7m_dcache_clean_area)
+
+/*
+ * There is no MMU, so here is nothing to do.
+ */
+ENTRY(cpu_v7m_switch_mm)
+        mov     pc, lr
+ENDPROC(cpu_v7m_switch_mm)
+
+.globl  cpu_v7m_suspend_size
+.equ    cpu_v7m_suspend_size, 0
+
+#ifdef CONFIG_ARM_CPU_SUSPEND
+ENTRY(cpu_v7m_do_suspend)
+        mov     pc, lr
+ENDPROC(cpu_v7m_do_suspend)
+
+ENTRY(cpu_v7m_do_resume)
+        mov     pc, lr
+ENDPROC(cpu_v7m_do_resume)
+#endif
+
+        .section ".text.init", #alloc, #execinstr
+
+/*
+ *      __v7m_setup
+ *
+ *      This should be able to cover all ARMv7-M cores.
+ */
+__v7m_setup:
+        @ Configure the vector table base address
+        ldr     r0, =BASEADDR_V7M_SCB
+        ldr     r12, =vector_table
+        str     r12, [r0, V7M_SCB_VTOR]
+
+        @ enable UsageFault, BusFault and MemManage fault.
+        ldr     r5, [r0, #V7M_SCB_SHCSR]
+        orr     r5, #(V7M_SCB_SHCSR_USGFAULTENA | V7M_SCB_SHCSR_BUSFAULTENA | V7M_SCB_SHCSR_MEMFAULTENA)
+        str     r5, [r0, #V7M_SCB_SHCSR]
+
+        @ Lower the priority of the SVC and PendSV exceptions
+        mov     r5, #0x80000000
+        str     r5, [r0, V7M_SCB_SHPR2] @ set SVC priority
+        mov     r5, #0x00800000
+        str     r5, [r0, V7M_SCB_SHPR3] @ set PendSV priority
+
+        @ SVC to run the kernel in this mode
+        adr     r1, BSYM(1f)
+        ldr     r5, [r12, #11 * 4]      @ read the SVC vector entry
+        str     r1, [r12, #11 * 4]      @ write the temporary SVC vector entry
+        mov     r6, lr                  @ save LR
+        mov     r7, sp                  @ save SP
+        ldr     sp, =__v7m_setup_stack_top
+        cpsie   i
+        svc     #0
+1:      cpsid   i
+        str     r5, [r12, #11 * 4]      @ restore the original SVC vector entry
+        mov     lr, r6                  @ restore LR
+        mov     sp, r7                  @ restore SP
+
+        @ Special-purpose control register
+        mov     r1, #1
+        msr     control, r1             @ Thread mode has unpriviledged access
+
+        @ Configure the System Control Register to ensure 8-byte stack alignment
+        @ Note the STKALIGN bit is either RW or RAO.
+        ldr     r12, [r0, V7M_SCB_CCR]  @ system control register
+        orr     r12, #V7M_SCB_CCR_STKALIGN
+        str     r12, [r0, V7M_SCB_CCR]
+        mov     pc, lr
+ENDPROC(__v7m_setup)
+
+        define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
+
+        .section ".rodata"
+        string cpu_arch_name, "armv7m"
+        string cpu_elf_name "v7m"
+        string cpu_v7m_name "ARMv7-M"
+
+        .section ".proc.info.init", #alloc, #execinstr
+
+        /*
+         * Match any ARMv7-M processor core.
+         */
+        .type   __v7m_proc_info, #object
+__v7m_proc_info:
+        .long   0x000f0000              @ Required ID value
+        .long   0x000f0000              @ Mask for ID
+        .long   0                       @ proc_info_list.__cpu_mm_mmu_flags
+        .long   0                       @ proc_info_list.__cpu_io_mmu_flags
+        b       __v7m_setup             @ proc_info_list.__cpu_flush
+        .long   cpu_arch_name
+        .long   cpu_elf_name
+        .long   HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT
+        .long   cpu_v7m_name
+        .long   v7m_processor_functions @ proc_info_list.proc
+        .long   0                       @ proc_info_list.tlb
+        .long   0                       @ proc_info_list.user
+        .long   nop_cache_fns           @ proc_info_list.cache
+        .size   __v7m_proc_info, . - __v7m_proc_info
+
+__v7m_setup_stack:
+        .space  4 * 8                           @ 8 registers
+__v7m_setup_stack_top:
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index f8ed2de0a678..ca27cc9ac4bf 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -6,7 +6,7 @@
 
 config PLAT_SAMSUNG
         bool
-        depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P
+        depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P || ARCH_EXYNOS
         default y
         select GENERIC_IRQ_CHIP
         select NO_IOPORT
@@ -15,12 +15,10 @@ config PLAT_SAMSUNG
 
 config PLAT_S5P
         bool
-        depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
+        depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
         default y
         select ARCH_REQUIRE_GPIOLIB
-        select ARM_GIC if ARCH_EXYNOS
-        select ARM_VIC if !ARCH_EXYNOS
-        select GIC_NON_BANKED if ARCH_EXYNOS4
+        select ARM_VIC
         select NO_IOPORT
         select PLAT_SAMSUNG
         select S3C_GPIO_TRACK
@@ -60,6 +58,20 @@ config S3C_LOWLEVEL_UART_PORT
           this configuration should be between zero and two. The port
           must have been initialised by the boot-loader before use.
 
+config SAMSUNG_ATAGS
+        def_bool n
+        depends on !ARCH_MULTIPLATFORM
+        depends on ATAGS
+        help
+           This option enables ATAGS based boot support code for
+           Samsung platforms, including static platform devices, legacy
+           clock, timer and interrupt initialization, etc.
+
+           Platforms that support only DT based boot need not to select
+           this option.
+
+if SAMSUNG_ATAGS
+
 # timer options
 
 config SAMSUNG_HRT
@@ -367,11 +379,6 @@ config S5P_DEV_JPEG
         help
           Compile in platform device definitions for JPEG codec
 
-config S5P_DEV_MFC
-        bool
-        help
-          Compile in setup memory (init) code for MFC
-
 config S5P_DEV_ONENAND
         bool
         help
@@ -412,6 +419,21 @@ config S3C_DMA
         help
           Internal configuration for S3C DMA core
 
+config S5P_IRQ_PM
+        bool
+        default y if S5P_PM
+        help
+          Legacy IRQ power management for S5P platforms
+
+config SAMSUNG_PM_GPIO
+        bool
+        default y if GPIO_SAMSUNG && PM
+        help
+          Include legacy GPIO power management code for platforms not using
+          pinctrl-samsung driver.
+
+endif
+
 config SAMSUNG_DMADEV
         bool
         select ARM_AMBA
@@ -421,6 +443,11 @@ config SAMSUNG_DMADEV
         help
           Use DMA device engine for PL330 DMAC.
 
+config S5P_DEV_MFC
+        bool
+        help
+          Compile in setup memory (init) code for MFC
+
 comment "Power management"
 
 config SAMSUNG_PM_DEBUG
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index a23c460299a1..6348ae2e3b46 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -31,10 +31,10 @@ obj-$(CONFIG_S3C_ADC)	+= adc.o
 
 # devices
 
-obj-y                           += platformdata.o
+obj-$(CONFIG_SAMSUNG_ATAGS)     += platformdata.o
 
-obj-y                           += devs.o
-obj-y                           += dev-uart.o
+obj-$(CONFIG_SAMSUNG_ATAGS)     += devs.o
+obj-$(CONFIG_SAMSUNG_ATAGS)     += dev-uart.o
 obj-$(CONFIG_S5P_DEV_MFC)       += s5p-dev-mfc.o
 obj-$(CONFIG_S5P_DEV_UART)      += s5p-dev-uart.o
 
@@ -52,10 +52,11 @@ obj-$(CONFIG_SAMSUNG_DMADEV)	+= dma-ops.o
 # PM support
 
 obj-$(CONFIG_PM)                += pm.o
-obj-$(CONFIG_PM)                += pm-gpio.o
+obj-$(CONFIG_SAMSUNG_PM_GPIO)   += pm-gpio.o
 obj-$(CONFIG_SAMSUNG_PM_CHECK)  += pm-check.o
 
 obj-$(CONFIG_SAMSUNG_WAKEMASK)  += wakeup-mask.o
 
-obj-$(CONFIG_S5P_PM)            += s5p-pm.o s5p-irq-pm.o
+obj-$(CONFIG_S5P_PM)            += s5p-pm.o
+obj-$(CONFIG_S5P_IRQ_PM)        += s5p-irq-pm.o
 obj-$(CONFIG_S5P_SLEEP)         += s5p-sleep.o
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 30c2fe243f76..0f9c3f431a5f 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -311,9 +311,9 @@ struct platform_device s5p_device_jpeg = {
 #ifdef CONFIG_S5P_DEV_FIMD0
 static struct resource s5p_fimd0_resource[] = {
         [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
-        [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC),
-        [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO),
-        [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM),
+        [1] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_VSYNC, "vsync"),
+        [2] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_FIFO, "fifo"),
+        [3] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_SYSTEM, "lcd_sys"),
 };
 
 struct platform_device s5p_device_fimd0 = {
diff --git a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
index d01576318b2c..bd3a6db14cbb 100644
--- a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
+++ b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
@@ -28,7 +28,6 @@ struct s3c24xx_dma_map {
         const char              *name;
 
         unsigned long            channels[S3C_DMA_CHANNELS];
-        unsigned long            channels_rx[S3C_DMA_CHANNELS];
 };
 
 struct s3c24xx_dma_selection {
@@ -38,10 +37,6 @@ struct s3c24xx_dma_selection {
 
         void    (*select)(struct s3c2410_dma_chan *chan,
                           struct s3c24xx_dma_map *map);
-
-        void    (*direction)(struct s3c2410_dma_chan *chan,
-                             struct s3c24xx_dma_map *map,
-                             enum dma_data_direction dir);
 };
 
 extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index f6fcadeee969..5d47ca35cabd 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -166,6 +166,7 @@ extern void s3c_pm_check_store(void);
  */
 extern void s3c_pm_configure_extint(void);
 
+#ifdef CONFIG_GPIO_SAMSUNG
 /**
  * samsung_pm_restore_gpios() - restore the state of the gpios after sleep.
  *
@@ -181,6 +182,10 @@ extern void samsung_pm_restore_gpios(void);
  * Save the GPIO states for resotration on resume. See samsung_pm_restore_gpios().
  */
 extern void samsung_pm_save_gpios(void);
+#else
+static inline void samsung_pm_restore_gpios(void) {}
+static inline void samsung_pm_save_gpios(void) {}
+#endif
 
 extern void s3c_pm_save_core(void);
 extern void s3c_pm_restore_core(void);
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index 438b24846e7f..02b66d723d1a 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -66,6 +66,9 @@ uart_rd(unsigned int reg)
 
 static void putc(int ch)
 {
+        if (!config_enabled(CONFIG_DEBUG_LL))
+                return;
+
         if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
                 int level;
 
@@ -118,7 +121,12 @@ static void arch_decomp_error(const char *x)
 #ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
 static inline void arch_enable_uart_fifo(void)
 {
-        u32 fifocon = uart_rd(S3C2410_UFCON);
+        u32 fifocon;
+
+        if (!config_enabled(CONFIG_DEBUG_LL))
+                return;
+
+        fifocon = uart_rd(S3C2410_UFCON);
 
         if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
                 fifocon |= S3C2410_UFCON_RESETBOTH;
diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c
index 79d10fca9090..3e5c4619caa5 100644
--- a/arch/arm/plat-samsung/init.c
+++ b/arch/arm/plat-samsung/init.c
@@ -87,7 +87,7 @@ void __init s3c24xx_init_clocks(int xtal)
 }
 
 /* uart management */
-
+#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS)
 static int nr_uarts __initdata = 0;
 
 static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS];
@@ -134,11 +134,12 @@ void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
         if (cpu == NULL)
                 return;
 
-        if (cpu->init_uarts == NULL) {
+        if (cpu->init_uarts == NULL && IS_ENABLED(CONFIG_SAMSUNG_ATAGS)) {
                 printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
         } else
                 (cpu->init_uarts)(cfg, no);
 }
+#endif
 
 static int __init s3c_arch_init(void)
 {
@@ -152,8 +153,9 @@ static int __init s3c_arch_init(void)
         ret = (cpu->init)();
         if (ret != 0)
                 return ret;
-
+#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS)
         ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
+#endif
         return ret;
 }
 
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
index c2ff92c30bdf..a8de3cfe2ee1 100644
--- a/arch/arm/plat-samsung/pm-gpio.c
+++ b/arch/arm/plat-samsung/pm-gpio.c
@@ -192,7 +192,8 @@ struct samsung_gpio_pm samsung_gpio_pm_2bit = {
         .resume = samsung_gpio_pm_2bit_resume,
 };
 
-#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P)
+#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P) \
+        || defined(CONFIG_ARCH_EXYNOS)
 static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip)
 {
         chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
@@ -302,7 +303,7 @@ struct samsung_gpio_pm samsung_gpio_pm_4bit = {
         .save   = samsung_gpio_pm_4bit_save,
         .resume = samsung_gpio_pm_4bit_resume,
 };
-#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */
+#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P || CONFIG_ARCH_EXYNOS */
 
 /**
  * samsung_pm_save_gpio() - save gpio chip data for suspend
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 53210ec4e8ec..ea3613642451 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -16,18 +16,23 @@
 #include <linux/suspend.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
+#include <linux/of.h>
 #include <linux/serial_core.h>
 #include <linux/io.h>
 
 #include <asm/cacheflush.h>
 #include <asm/suspend.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
 
 #include <plat/regs-serial.h>
+
+#ifdef CONFIG_SAMSUNG_ATAGS
+#include <mach/hardware.h>
+#include <mach/map.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-irq.h>
 #include <mach/irqs.h>
+#endif
+
 #include <asm/irq.h>
 
 #include <plat/pm.h>
@@ -261,7 +266,8 @@ static int s3c_pm_enter(suspend_state_t state)
          * require a full power-cycle)
         */
 
-        if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
+        if (!of_have_populated_dt() &&
+            !any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
             !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
                 printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
                 printk(KERN_ERR "%s: Aborting sleep\n", __func__);
@@ -270,8 +276,11 @@ static int s3c_pm_enter(suspend_state_t state)
 
         /* save all necessary core registers not covered by the drivers */
 
-        samsung_pm_save_gpios();
-        samsung_pm_saved_gpios();
+        if (!of_have_populated_dt()) {
+                samsung_pm_save_gpios();
+                samsung_pm_saved_gpios();
+        }
+
         s3c_pm_save_uarts();
         s3c_pm_save_core();
 
@@ -310,8 +319,11 @@ static int s3c_pm_enter(suspend_state_t state)
 
         s3c_pm_restore_core();
         s3c_pm_restore_uarts();
-        samsung_pm_restore_gpios();
-        s3c_pm_restored_gpios();
+
+        if (!of_have_populated_dt()) {
+                samsung_pm_restore_gpios();
+                s3c_pm_restored_gpios();
+        }
 
         s3c_pm_debug_init();
 
diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c
index a93fb6fb6606..ad51f85fbd01 100644
--- a/arch/arm/plat-samsung/s5p-dev-mfc.c
+++ b/arch/arm/plat-samsung/s5p-dev-mfc.c
@@ -17,10 +17,12 @@
 #include <linux/of_fdt.h>
 #include <linux/of.h>
 
+#include <plat/mfc.h>
+
+#ifdef CONFIG_SAMSUNG_ATAGS
 #include <mach/map.h>
 #include <mach/irqs.h>
 #include <plat/devs.h>
-#include <plat/mfc.h>
 
 static struct resource s5p_mfc_resource[] = {
         [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
@@ -61,6 +63,10 @@ struct platform_device s5p_device_mfc_r = {
                 .coherent_dma_mask      = DMA_BIT_MASK(32),
         },
 };
+#else
+static struct platform_device s5p_device_mfc_l;
+static struct platform_device s5p_device_mfc_r;
+#endif
 
 struct s5p_mfc_reserved_mem {
         phys_addr_t     base;
@@ -70,6 +76,7 @@ struct s5p_mfc_reserved_mem {
 
 static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata;
 
+
 void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
                                 phys_addr_t lbase, unsigned int lsize)
 {
@@ -93,6 +100,7 @@ void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
         }
 }
 
+#ifdef CONFIG_SAMSUNG_ATAGS
 static int __init s5p_mfc_memory_init(void)
 {
         int i;
@@ -111,6 +119,7 @@ static int __init s5p_mfc_memory_init(void)
         return 0;
 }
 device_initcall(s5p_mfc_memory_init);
+#endif
 
 #ifdef CONFIG_OF
 int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname,
diff --git a/arch/arm64/kernel/arm64ksyms.c b/arch/arm64/kernel/arm64ksyms.c
index 7df1aad29b67..41b4f626d554 100644
--- a/arch/arm64/kernel/arm64ksyms.c
+++ b/arch/arm64/kernel/arm64ksyms.c
@@ -34,6 +34,7 @@ EXPORT_SYMBOL(__strnlen_user);
 EXPORT_SYMBOL(__strncpy_from_user);
 
 EXPORT_SYMBOL(copy_page);
+EXPORT_SYMBOL(clear_page);
 
 EXPORT_SYMBOL(__copy_from_user);
 EXPORT_SYMBOL(__copy_to_user);
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index c7e047049f2c..1d1314280a03 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -390,6 +390,16 @@ el0_sync_compat:
         b.eq    el0_fpsimd_exc
         cmp     x24, #ESR_EL1_EC_UNKNOWN        // unknown exception in EL0
         b.eq    el0_undef
+        cmp     x24, #ESR_EL1_EC_CP15_32        // CP15 MRC/MCR trap
+        b.eq    el0_undef
+        cmp     x24, #ESR_EL1_EC_CP15_64        // CP15 MRRC/MCRR trap
+        b.eq    el0_undef
+        cmp     x24, #ESR_EL1_EC_CP14_MR        // CP14 MRC/MCR trap
+        b.eq    el0_undef
+        cmp     x24, #ESR_EL1_EC_CP14_LS        // CP14 LDC/STC trap
+        b.eq    el0_undef
+        cmp     x24, #ESR_EL1_EC_CP14_64        // CP14 MRRC/MCRR trap
+        b.eq    el0_undef
         cmp     x24, #ESR_EL1_EC_BREAKPT_EL0    // debug exception in EL0
         b.ge    el0_dbg
         b       el0_inv
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index 61d7dd29f756..f30852d28590 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -267,7 +267,8 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
                 return;
 #endif
 
-        if (show_unhandled_signals) {
+        if (show_unhandled_signals && unhandled_signal(current, SIGILL) &&
+            printk_ratelimit()) {
                 pr_info("%s[%d]: undefined instruction: pc=%p\n",
                         current->comm, task_pid_nr(current), pc);
                 dump_instr(KERN_INFO, regs);
@@ -294,7 +295,7 @@ asmlinkage long do_ni_syscall(struct pt_regs *regs)
         }
 #endif
 
-        if (show_unhandled_signals) {
+        if (show_unhandled_signals && printk_ratelimit()) {
                 pr_info("%s[%d]: syscall %d\n", current->comm,
                         task_pid_nr(current), (int)regs->syscallno);
                 dump_instr("", regs);
@@ -310,14 +311,20 @@ asmlinkage long do_ni_syscall(struct pt_regs *regs)
  */
 asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr)
 {
+        siginfo_t info;
+        void __user *pc = (void __user *)instruction_pointer(regs);
         console_verbose();
 
         pr_crit("Bad mode in %s handler detected, code 0x%08x\n",
                 handler[reason], esr);
+        __show_regs(regs);
+
+        info.si_signo = SIGILL;
+        info.si_errno = 0;
+        info.si_code  = ILL_ILLOPC;
+        info.si_addr  = pc;
 
-        die("Oops - bad mode", regs, 0);
-        local_irq_disable();
-        panic("bad mode");
+        arm64_notify_die("Oops - bad mode", regs, &info, 0);
 }
 
 void __pte_error(const char *file, int line, unsigned long val)
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index 98af6e760cce..1426468b77f3 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -113,7 +113,8 @@ static void __do_user_fault(struct task_struct *tsk, unsigned long addr,
 {
         struct siginfo si;
 
-        if (show_unhandled_signals) {
+        if (show_unhandled_signals && unhandled_signal(tsk, sig) &&
+            printk_ratelimit()) {
                 pr_info("%s[%d]: unhandled %s (%d) at 0x%08lx, esr 0x%03x\n",
                         tsk->comm, task_pid_nr(tsk), fault_name(esr), sig,
                         addr, esr);
diff --git a/arch/ia64/include/asm/tlb.h b/arch/ia64/include/asm/tlb.h
index c3ffe3e54edc..ef3a9de01954 100644
--- a/arch/ia64/include/asm/tlb.h
+++ b/arch/ia64/include/asm/tlb.h
@@ -46,12 +46,6 @@
 #include <asm/tlbflush.h>
 #include <asm/machvec.h>
 
-#ifdef CONFIG_SMP
-# define tlb_fast_mode(tlb)     ((tlb)->nr == ~0U)
-#else
-# define tlb_fast_mode(tlb)     (1)
-#endif
-
 /*
  * If we can't allocate a page to make a big batch of page pointers
  * to work on, then just handle a few from the on-stack structure.
@@ -60,7 +54,7 @@
 
 struct mmu_gather {
         struct mm_struct        *mm;
-        unsigned int            nr;             /* == ~0U => fast mode */
+        unsigned int            nr;
         unsigned int            max;
         unsigned char           fullmm;         /* non-zero means full mm flush */
         unsigned char           need_flush;     /* really unmapped some PTEs? */
@@ -103,6 +97,7 @@ extern struct ia64_tr_entry *ia64_idtrs[NR_CPUS];
 static inline void
 ia64_tlb_flush_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long end)
 {
+        unsigned long i;
         unsigned int nr;
 
         if (!tlb->need_flush)
@@ -141,13 +136,11 @@ ia64_tlb_flush_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long e
 
         /* lastly, release the freed pages */
         nr = tlb->nr;
-        if (!tlb_fast_mode(tlb)) {
-                unsigned long i;
-                tlb->nr = 0;
-                tlb->start_addr = ~0UL;
-                for (i = 0; i < nr; ++i)
-                        free_page_and_swap_cache(tlb->pages[i]);
-        }
+
+        tlb->nr = 0;
+        tlb->start_addr = ~0UL;
+        for (i = 0; i < nr; ++i)
+                free_page_and_swap_cache(tlb->pages[i]);
 }
 
 static inline void __tlb_alloc_page(struct mmu_gather *tlb)
@@ -167,20 +160,7 @@ tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned int full_m
         tlb->mm = mm;
         tlb->max = ARRAY_SIZE(tlb->local);
         tlb->pages = tlb->local;
-        /*
-         * Use fast mode if only 1 CPU is online.
-         *
-         * It would be tempting to turn on fast-mode for full_mm_flush as well.  But this
-         * doesn't work because of speculative accesses and software prefetching: the page
-         * table of "mm" may (and usually is) the currently active page table and even
-         * though the kernel won't do any user-space accesses during the TLB shoot down, a
-         * compiler might use speculation or lfetch.fault on what happens to be a valid
-         * user-space address.  This in turn could trigger a TLB miss fault (or a VHPT
-         * walk) and re-insert a TLB entry we just removed.  Slow mode avoids such
-         * problems.  (We could make fast-mode work by switching the current task to a
-         * different "mm" during the shootdown.) --davidm 08/02/2002
-         */
-        tlb->nr = (num_online_cpus() == 1) ? ~0U : 0;
+        tlb->nr = 0;
         tlb->fullmm = full_mm_flush;
         tlb->start_addr = ~0UL;
 }
@@ -214,11 +194,6 @@ static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
 {
         tlb->need_flush = 1;
 
-        if (tlb_fast_mode(tlb)) {
-                free_page_and_swap_cache(page);
-                return 1; /* avoid calling tlb_flush_mmu */
-        }
-
         if (!tlb->nr && tlb->pages == tlb->local)
                 __tlb_alloc_page(tlb);
 
diff --git a/arch/m68k/configs/amiga_defconfig b/arch/m68k/configs/amiga_defconfig
index 90d3109c82f4..19325e117eea 100644
--- a/arch/m68k/configs/amiga_defconfig
+++ b/arch/m68k/configs/amiga_defconfig
@@ -1,55 +1,78 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_LOCALVERSION="-amiga"
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_RELAY=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_AMIGA=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ATARI_PARTITION=y
+CONFIG_MAC_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_SUN_PARTITION=y
+# CONFIG_EFI_PARTITION is not set
+CONFIG_SYSV68_PARTITION=y
+CONFIG_IOSCHED_DEADLINE=m
 CONFIG_M68020=y
 CONFIG_M68030=y
 CONFIG_M68040=y
 CONFIG_M68060=y
-CONFIG_BINFMT_AOUT=m
-CONFIG_BINFMT_MISC=m
+CONFIG_AMIGA=y
 CONFIG_ZORRO=y
 CONFIG_AMIGA_PCMCIA=y
-CONFIG_HEARTBEAT=y
-CONFIG_PROC_HARDWARE=y
 CONFIG_ZORRO_NAMES=y
+# CONFIG_COMPACTION is not set
+CONFIG_CLEANCACHE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_MISC=m
 CONFIG_NET=y
 CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=m
 CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=m
+CONFIG_XFRM_MIGRATE=y
 CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
 CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
 CONFIG_NET_IPGRE=m
 CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=m
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=m
+CONFIG_INET_UDP_DIAG=m
 CONFIG_IPV6_PRIVACY=y
 CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_GRE=m
 CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
 CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_ZONES=y
+# CONFIG_NF_CONNTRACK_PROCFS is not set
 # CONFIG_NF_CT_PROTO_DCCP is not set
 CONFIG_NF_CT_PROTO_UDPLITE=m
 CONFIG_NF_CONNTRACK_AMANDA=m
@@ -57,25 +80,37 @@ CONFIG_NF_CONNTRACK_FTP=m
 CONFIG_NF_CONNTRACK_H323=m
 CONFIG_NF_CONNTRACK_IRC=m
 CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
 CONFIG_NF_CONNTRACK_PPTP=m
 CONFIG_NF_CONNTRACK_SANE=m
 CONFIG_NF_CONNTRACK_SIP=m
 CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NETFILTER_XT_SET=m
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
 CONFIG_NETFILTER_XT_TARGET_MARK=m
 CONFIG_NETFILTER_XT_TARGET_NFLOG=m
 CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
 CONFIG_NETFILTER_XT_TARGET_TRACE=m
 CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
 CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
 CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
 CONFIG_NETFILTER_XT_MATCH_COMMENT=m
 CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
 CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
 CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
 CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
 CONFIG_NETFILTER_XT_MATCH_DSCP=m
 CONFIG_NETFILTER_XT_MATCH_ESP=m
 CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
@@ -86,6 +121,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m
 CONFIG_NETFILTER_XT_MATCH_MAC=m
 CONFIG_NETFILTER_XT_MATCH_MARK=m
 CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
 CONFIG_NETFILTER_XT_MATCH_OWNER=m
 CONFIG_NETFILTER_XT_MATCH_POLICY=m
 CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
@@ -99,22 +136,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 CONFIG_NETFILTER_XT_MATCH_TIME=m
 CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
 CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
 CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_NF_NAT=m
+CONFIG_NF_NAT_IPV4=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_NF_NAT_SNMP_BASIC=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_TARGET_ECN=m
@@ -124,7 +170,6 @@ CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_AH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
@@ -133,18 +178,30 @@ CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_HL=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
 CONFIG_IP6_NF_RAW=m
+CONFIG_NF_NAT_IPV6=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
 CONFIG_IP_DCCP=m
 # CONFIG_IP_DCCP_CCID3 is not set
+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
+CONFIG_RDS=m
+CONFIG_RDS_TCP=m
+CONFIG_L2TP=m
 CONFIG_ATALK=m
+CONFIG_BATMAN_ADV=m
+CONFIG_BATMAN_ADV_DAT=y
+# CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
+# CONFIG_FW_LOADER_USER_HELPER is not set
 CONFIG_CONNECTOR=m
 CONFIG_PARPORT=m
 CONFIG_PARPORT_AMIGA=m
@@ -154,11 +211,13 @@ CONFIG_AMIGA_FLOPPY=y
 CONFIG_AMIGA_Z2RAM=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_DRBD=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_CDROM_PKTCDVD=m
 CONFIG_ATA_OVER_ETH=m
 CONFIG_IDE=y
+CONFIG_IDE_GD_ATAPI=y
 CONFIG_BLK_DEV_IDECD=y
 CONFIG_BLK_DEV_GAYLE=y
 CONFIG_BLK_DEV_BUDDHA=y
@@ -172,57 +231,77 @@ CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=m
 CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_SAS_LIBSAS=m
-# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
-CONFIG_SCSI_SRP_ATTRS=m
-CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=m
 CONFIG_ISCSI_TCP=m
+CONFIG_ISCSI_BOOT_SYSFS=m
 CONFIG_A3000_SCSI=y
 CONFIG_A2091_SCSI=y
 CONFIG_GVP11_SCSI=y
 CONFIG_SCSI_A4000T=y
 CONFIG_SCSI_ZORRO7XX=y
 CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
 CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID456=m
 CONFIG_BLK_DEV_DM=m
 CONFIG_DM_CRYPT=m
 CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_CACHE=m
 CONFIG_DM_MIRROR=m
+CONFIG_DM_RAID=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
 CONFIG_DM_UEVENT=y
+CONFIG_TARGET_CORE=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_PSCSI=m
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
-CONFIG_MACVLAN=m
 CONFIG_EQUALIZER=m
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_VXLAN=m
+CONFIG_NETCONSOLE=m
+CONFIG_NETCONSOLE_DYNAMIC=y
 CONFIG_VETH=m
-CONFIG_NET_ETHERNET=y
-CONFIG_ARIADNE=y
+# CONFIG_NET_VENDOR_3COM is not set
 CONFIG_A2065=y
+CONFIG_ARIADNE=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FUJITSU is not set
+# CONFIG_NET_VENDOR_HP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
 CONFIG_HYDRA=y
-CONFIG_ZORRO8390=y
 CONFIG_APNE=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+CONFIG_ZORRO8390=y
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
 CONFIG_PPP=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
 CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPTP=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_WLAN is not set
+CONFIG_INPUT_EVDEV=m
 CONFIG_KEYBOARD_AMIGA=y
 # CONFIG_KEYBOARD_ATKBD is not set
 # CONFIG_MOUSE_PS2 is not set
@@ -233,11 +312,14 @@ CONFIG_INPUT_MISC=y
 CONFIG_INPUT_M68K_BEEP=m
 # CONFIG_SERIO is not set
 CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 CONFIG_PRINTER=m
 # CONFIG_HW_RANDOM is not set
-CONFIG_GEN_RTC=m
-CONFIG_GEN_RTC_X=y
+CONFIG_NTP_PPS=y
+CONFIG_PPS_CLIENT_LDISC=m
+CONFIG_PPS_CLIENT_PARPORT=m
+CONFIG_PTP_1588_CLOCK=m
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FB_CIRRUS=y
@@ -252,48 +334,64 @@ CONFIG_SOUND=m
 CONFIG_DMASOUND_PAULA=m
 CONFIG_HID=m
 CONFIG_HIDRAW=y
+CONFIG_UHID=m
+# CONFIG_HID_GENERIC is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_MSM6242=m
+CONFIG_RTC_DRV_RP5C01=m
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_HEARTBEAT=y
+CONFIG_PROC_HARDWARE=y
 CONFIG_AMIGA_BUILTIN_SERIAL=y
 CONFIG_SERIAL_CONSOLE=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
 CONFIG_REISERFS_FS=m
 CONFIG_JFS_FS=m
 CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
-# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
+CONFIG_FANOTIFY=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
 # CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
 CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
+CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_AFFS_FS=m
+CONFIG_ECRYPT_FS=m
+CONFIG_ECRYPT_FS_MESSAGING=y
 CONFIG_HFS_FS=m
 CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 CONFIG_SQUASHFS=m
-CONFIG_MINIX_FS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_MINIX_FS=m
+CONFIG_OMFS_FS=m
 CONFIG_HPFS_FS=m
+CONFIG_QNX4FS_FS=m
+CONFIG_QNX6FS_FS=m
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V4=y
+CONFIG_NFS_SWAP=y
+CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_CIFS=m
+# CONFIG_CIFS_DEBUG is not set
 CONFIG_CODA_FS=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
@@ -332,10 +430,23 @@ CONFIG_NLS_ISO8859_14=m
 CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_MAC_ROMAN=m
+CONFIG_NLS_MAC_CELTIC=m
+CONFIG_NLS_MAC_CENTEURO=m
+CONFIG_NLS_MAC_CROATIAN=m
+CONFIG_NLS_MAC_CYRILLIC=m
+CONFIG_NLS_MAC_GAELIC=m
+CONFIG_NLS_MAC_GREEK=m
+CONFIG_NLS_MAC_ICELAND=m
+CONFIG_NLS_MAC_INUIT=m
+CONFIG_NLS_MAC_ROMANIAN=m
+CONFIG_NLS_MAC_TURKISH=m
 CONFIG_DLM=m
 CONFIG_MAGIC_SYSRQ=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_ASYNC_RAID6_TEST=m
+CONFIG_ENCRYPTED_KEYS=m
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_USER=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_TEST=m
@@ -345,19 +456,16 @@ CONFIG_CRYPTO_CTS=m
 CONFIG_CRYPTO_LRW=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_VMAC=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_RMD128=m
 CONFIG_CRYPTO_RMD160=m
 CONFIG_CRYPTO_RMD256=m
 CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_TGR192=m
 CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_ANUBIS=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_CAMELLIA=m
@@ -373,6 +481,14 @@ CONFIG_CRYPTO_TWOFISH=m
 CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
 # CONFIG_CRYPTO_HW is not set
-CONFIG_CRC16=m
 CONFIG_CRC_T10DIF=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_TEST=m
diff --git a/arch/m68k/configs/apollo_defconfig b/arch/m68k/configs/apollo_defconfig
index 8f4f657fdbc6..14dc6ccda7f4 100644
--- a/arch/m68k/configs/apollo_defconfig
+++ b/arch/m68k/configs/apollo_defconfig
@@ -1,55 +1,76 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_LOCALVERSION="-apollo"
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_RELAY=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_APOLLO=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_AMIGA_PARTITION=y
+CONFIG_ATARI_PARTITION=y
+CONFIG_MAC_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_SUN_PARTITION=y
+# CONFIG_EFI_PARTITION is not set
+CONFIG_SYSV68_PARTITION=y
+CONFIG_IOSCHED_DEADLINE=m
 CONFIG_M68020=y
 CONFIG_M68030=y
 CONFIG_M68040=y
 CONFIG_M68060=y
+CONFIG_APOLLO=y
+# CONFIG_COMPACTION is not set
+CONFIG_CLEANCACHE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
-CONFIG_HEARTBEAT=y
-CONFIG_PROC_HARDWARE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=m
 CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=m
+CONFIG_XFRM_MIGRATE=y
 CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 CONFIG_IP_PNP_RARP=y
 CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
 CONFIG_NET_IPGRE=m
 CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=m
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=m
+CONFIG_INET_UDP_DIAG=m
 CONFIG_IPV6_PRIVACY=y
 CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_GRE=m
 CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
 CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_ZONES=y
+# CONFIG_NF_CONNTRACK_PROCFS is not set
 # CONFIG_NF_CT_PROTO_DCCP is not set
 CONFIG_NF_CT_PROTO_UDPLITE=m
 CONFIG_NF_CONNTRACK_AMANDA=m
@@ -57,25 +78,37 @@ CONFIG_NF_CONNTRACK_FTP=m
 CONFIG_NF_CONNTRACK_H323=m
 CONFIG_NF_CONNTRACK_IRC=m
 CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
 CONFIG_NF_CONNTRACK_PPTP=m
 CONFIG_NF_CONNTRACK_SANE=m
 CONFIG_NF_CONNTRACK_SIP=m
 CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NETFILTER_XT_SET=m
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
 CONFIG_NETFILTER_XT_TARGET_MARK=m
 CONFIG_NETFILTER_XT_TARGET_NFLOG=m
 CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
 CONFIG_NETFILTER_XT_TARGET_TRACE=m
 CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
 CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
 CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
 CONFIG_NETFILTER_XT_MATCH_COMMENT=m
 CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
 CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
 CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
 CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
 CONFIG_NETFILTER_XT_MATCH_DSCP=m
 CONFIG_NETFILTER_XT_MATCH_ESP=m
 CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
@@ -86,6 +119,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m
 CONFIG_NETFILTER_XT_MATCH_MAC=m
 CONFIG_NETFILTER_XT_MATCH_MARK=m
 CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
 CONFIG_NETFILTER_XT_MATCH_OWNER=m
 CONFIG_NETFILTER_XT_MATCH_POLICY=m
 CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
@@ -99,22 +134,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 CONFIG_NETFILTER_XT_MATCH_TIME=m
 CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
 CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
 CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_NF_NAT=m
+CONFIG_NF_NAT_IPV4=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_NF_NAT_SNMP_BASIC=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_TARGET_ECN=m
@@ -124,7 +168,6 @@ CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_AH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
@@ -133,21 +176,34 @@ CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_HL=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
 CONFIG_IP6_NF_RAW=m
+CONFIG_NF_NAT_IPV6=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
 CONFIG_IP_DCCP=m
 # CONFIG_IP_DCCP_CCID3 is not set
+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
+CONFIG_RDS=m
+CONFIG_RDS_TCP=m
+CONFIG_L2TP=m
 CONFIG_ATALK=m
+CONFIG_BATMAN_ADV=m
+CONFIG_BATMAN_ADV_DAT=y
+# CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
+# CONFIG_FW_LOADER_USER_HELPER is not set
 CONFIG_CONNECTOR=m
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_DRBD=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_CDROM_PKTCDVD=m
@@ -162,57 +218,74 @@ CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=m
 CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_SAS_LIBSAS=m
-# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
-CONFIG_SCSI_SRP_ATTRS=m
-CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=m
 CONFIG_ISCSI_TCP=m
+CONFIG_ISCSI_BOOT_SYSFS=m
 CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
 CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID456=m
 CONFIG_BLK_DEV_DM=m
 CONFIG_DM_CRYPT=m
 CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_CACHE=m
 CONFIG_DM_MIRROR=m
+CONFIG_DM_RAID=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
 CONFIG_DM_UEVENT=y
+CONFIG_TARGET_CORE=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_PSCSI=m
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
-CONFIG_MACVLAN=m
 CONFIG_EQUALIZER=m
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_VXLAN=m
+CONFIG_NETCONSOLE=m
+CONFIG_NETCONSOLE_DYNAMIC=y
 CONFIG_VETH=m
-CONFIG_NET_ETHERNET=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
 CONFIG_PPP=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
 CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPTP=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_WLAN is not set
+CONFIG_INPUT_EVDEV=m
 # CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_MOUSE_PS2=m
+# CONFIG_MOUSE_PS2 is not set
 CONFIG_MOUSE_SERIAL=m
 CONFIG_SERIO=m
-# CONFIG_SERIO_SERPORT is not set
 CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 # CONFIG_HW_RANDOM is not set
-CONFIG_GEN_RTC=m
-CONFIG_GEN_RTC_X=y
+CONFIG_NTP_PPS=y
+CONFIG_PPS_CLIENT_LDISC=m
+CONFIG_PTP_1588_CLOCK=m
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
@@ -221,47 +294,61 @@ CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_CLUT224 is not set
 CONFIG_HID=m
 CONFIG_HIDRAW=y
+CONFIG_UHID=m
+# CONFIG_HID_GENERIC is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_HEARTBEAT=y
+CONFIG_PROC_HARDWARE=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
 CONFIG_REISERFS_FS=m
 CONFIG_JFS_FS=m
 CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
-# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
+CONFIG_FANOTIFY=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
 # CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
 CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
+CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_AFFS_FS=m
+CONFIG_ECRYPT_FS=m
+CONFIG_ECRYPT_FS_MESSAGING=y
 CONFIG_HFS_FS=m
 CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 CONFIG_SQUASHFS=m
-CONFIG_MINIX_FS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_MINIX_FS=m
+CONFIG_OMFS_FS=m
 CONFIG_HPFS_FS=m
+CONFIG_QNX4FS_FS=m
+CONFIG_QNX6FS_FS=m
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V4=y
+CONFIG_NFS_SWAP=y
 CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_CIFS=m
+# CONFIG_CIFS_DEBUG is not set
 CONFIG_CODA_FS=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
@@ -300,10 +387,23 @@ CONFIG_NLS_ISO8859_14=m
 CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_MAC_ROMAN=m
+CONFIG_NLS_MAC_CELTIC=m
+CONFIG_NLS_MAC_CENTEURO=m
+CONFIG_NLS_MAC_CROATIAN=m
+CONFIG_NLS_MAC_CYRILLIC=m
+CONFIG_NLS_MAC_GAELIC=m
+CONFIG_NLS_MAC_GREEK=m
+CONFIG_NLS_MAC_ICELAND=m
+CONFIG_NLS_MAC_INUIT=m
+CONFIG_NLS_MAC_ROMANIAN=m
+CONFIG_NLS_MAC_TURKISH=m
 CONFIG_DLM=m
 CONFIG_MAGIC_SYSRQ=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_ASYNC_RAID6_TEST=m
+CONFIG_ENCRYPTED_KEYS=m
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_USER=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_TEST=m
@@ -313,19 +413,16 @@ CONFIG_CRYPTO_CTS=m
 CONFIG_CRYPTO_LRW=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_VMAC=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_RMD128=m
 CONFIG_CRYPTO_RMD160=m
 CONFIG_CRYPTO_RMD256=m
 CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_TGR192=m
 CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_ANUBIS=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_CAMELLIA=m
@@ -341,6 +438,14 @@ CONFIG_CRYPTO_TWOFISH=m
 CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
 # CONFIG_CRYPTO_HW is not set
-CONFIG_CRC16=m
 CONFIG_CRC_T10DIF=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_TEST=m
diff --git a/arch/m68k/configs/atari_defconfig b/arch/m68k/configs/atari_defconfig
index 4571d33903fe..6d5370c914b2 100644
--- a/arch/m68k/configs/atari_defconfig
+++ b/arch/m68k/configs/atari_defconfig
@@ -1,53 +1,75 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_LOCALVERSION="-atari"
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_RELAY=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_ATARI=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_AMIGA_PARTITION=y
+CONFIG_MAC_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_SUN_PARTITION=y
+# CONFIG_EFI_PARTITION is not set
+CONFIG_SYSV68_PARTITION=y
+CONFIG_IOSCHED_DEADLINE=m
 CONFIG_M68020=y
 CONFIG_M68030=y
 CONFIG_M68040=y
 CONFIG_M68060=y
+CONFIG_ATARI=y
+# CONFIG_COMPACTION is not set
+CONFIG_CLEANCACHE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
-CONFIG_STRAM_PROC=y
-CONFIG_HEARTBEAT=y
-CONFIG_PROC_HARDWARE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=m
 CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=m
+CONFIG_XFRM_MIGRATE=y
 CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
 CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
 CONFIG_NET_IPGRE=m
 CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=m
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=m
+CONFIG_INET_UDP_DIAG=m
 CONFIG_IPV6_PRIVACY=y
 CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_GRE=m
 CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
 CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_ZONES=y
+# CONFIG_NF_CONNTRACK_PROCFS is not set
 # CONFIG_NF_CT_PROTO_DCCP is not set
 CONFIG_NF_CT_PROTO_UDPLITE=m
 CONFIG_NF_CONNTRACK_AMANDA=m
@@ -55,25 +77,37 @@ CONFIG_NF_CONNTRACK_FTP=m
 CONFIG_NF_CONNTRACK_H323=m
 CONFIG_NF_CONNTRACK_IRC=m
 CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
 CONFIG_NF_CONNTRACK_PPTP=m
 CONFIG_NF_CONNTRACK_SANE=m
 CONFIG_NF_CONNTRACK_SIP=m
 CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NETFILTER_XT_SET=m
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
 CONFIG_NETFILTER_XT_TARGET_MARK=m
 CONFIG_NETFILTER_XT_TARGET_NFLOG=m
 CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
 CONFIG_NETFILTER_XT_TARGET_TRACE=m
 CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
 CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
 CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
 CONFIG_NETFILTER_XT_MATCH_COMMENT=m
 CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
 CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
 CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
 CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
 CONFIG_NETFILTER_XT_MATCH_DSCP=m
 CONFIG_NETFILTER_XT_MATCH_ESP=m
 CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
@@ -84,6 +118,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m
 CONFIG_NETFILTER_XT_MATCH_MAC=m
 CONFIG_NETFILTER_XT_MATCH_MARK=m
 CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
 CONFIG_NETFILTER_XT_MATCH_OWNER=m
 CONFIG_NETFILTER_XT_MATCH_POLICY=m
 CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
@@ -97,22 +133,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 CONFIG_NETFILTER_XT_MATCH_TIME=m
 CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
 CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
 CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_NF_NAT=m
+CONFIG_NF_NAT_IPV4=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_NF_NAT_SNMP_BASIC=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_TARGET_ECN=m
@@ -122,7 +167,6 @@ CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_AH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
@@ -131,18 +175,30 @@ CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_HL=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
 CONFIG_IP6_NF_RAW=m
+CONFIG_NF_NAT_IPV6=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
 CONFIG_IP_DCCP=m
 # CONFIG_IP_DCCP_CCID3 is not set
+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
+CONFIG_RDS=m
+CONFIG_RDS_TCP=m
+CONFIG_L2TP=m
 CONFIG_ATALK=m
+CONFIG_BATMAN_ADV=m
+CONFIG_BATMAN_ADV_DAT=y
+# CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
+# CONFIG_FW_LOADER_USER_HELPER is not set
 CONFIG_CONNECTOR=m
 CONFIG_PARPORT=m
 CONFIG_PARPORT_ATARI=m
@@ -150,11 +206,13 @@ CONFIG_PARPORT_1284=y
 CONFIG_ATARI_FLOPPY=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_DRBD=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_CDROM_PKTCDVD=m
 CONFIG_ATA_OVER_ETH=m
 CONFIG_IDE=y
+CONFIG_IDE_GD_ATAPI=y
 CONFIG_BLK_DEV_IDECD=y
 CONFIG_BLK_DEV_FALCON_IDE=y
 CONFIG_RAID_ATTRS=m
@@ -167,63 +225,81 @@ CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=m
 CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_SAS_LIBSAS=m
-# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
-CONFIG_SCSI_SRP_ATTRS=m
-CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=m
 CONFIG_ISCSI_TCP=m
+CONFIG_ISCSI_BOOT_SYSFS=m
 CONFIG_ATARI_SCSI=y
 CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
 CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID456=m
 CONFIG_BLK_DEV_DM=m
 CONFIG_DM_CRYPT=m
 CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_CACHE=m
 CONFIG_DM_MIRROR=m
+CONFIG_DM_RAID=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
 CONFIG_DM_UEVENT=y
+CONFIG_TARGET_CORE=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_PSCSI=m
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
-CONFIG_MACVLAN=m
 CONFIG_EQUALIZER=m
-CONFIG_VETH=m
-CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_VXLAN=m
+CONFIG_NETCONSOLE=m
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_VETH=m
 CONFIG_ATARILANCE=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
 CONFIG_PPP=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
 CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPTP=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_WLAN is not set
+CONFIG_INPUT_EVDEV=m
 CONFIG_KEYBOARD_ATARI=y
 # CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_MOUSE_PS2=m
+# CONFIG_MOUSE_PS2 is not set
 CONFIG_MOUSE_ATARI=m
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_M68K_BEEP=m
-# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO is not set
 CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 CONFIG_PRINTER=m
 # CONFIG_HW_RANDOM is not set
-CONFIG_GEN_RTC=m
-CONFIG_GEN_RTC_X=y
+CONFIG_NTP_PPS=y
+CONFIG_PPS_CLIENT_LDISC=m
+CONFIG_PPS_CLIENT_PARPORT=m
+CONFIG_PTP_1588_CLOCK=m
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FB_ATARI=y
@@ -233,47 +309,64 @@ CONFIG_SOUND=m
 CONFIG_DMASOUND_ATARI=m
 CONFIG_HID=m
 CONFIG_HIDRAW=y
-# CONFIG_USB_SUPPORT is not set
+CONFIG_UHID=m
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_HEARTBEAT=y
+CONFIG_PROC_HARDWARE=y
+CONFIG_NATFEAT=y
+CONFIG_NFBLOCK=y
+CONFIG_NFCON=y
+CONFIG_NFETH=y
 CONFIG_ATARI_DSP56K=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
 CONFIG_REISERFS_FS=m
 CONFIG_JFS_FS=m
 CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
-# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
+CONFIG_FANOTIFY=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
 # CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
 CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
+CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_AFFS_FS=m
+CONFIG_ECRYPT_FS=m
+CONFIG_ECRYPT_FS_MESSAGING=y
 CONFIG_HFS_FS=m
 CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 CONFIG_SQUASHFS=m
-CONFIG_MINIX_FS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_MINIX_FS=m
+CONFIG_OMFS_FS=m
 CONFIG_HPFS_FS=m
+CONFIG_QNX4FS_FS=m
+CONFIG_QNX6FS_FS=m
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V4=y
+CONFIG_NFS_SWAP=y
+CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_CIFS=m
+# CONFIG_CIFS_DEBUG is not set
 CONFIG_CODA_FS=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
@@ -312,10 +405,23 @@ CONFIG_NLS_ISO8859_14=m
 CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_MAC_ROMAN=m
+CONFIG_NLS_MAC_CELTIC=m
+CONFIG_NLS_MAC_CENTEURO=m
+CONFIG_NLS_MAC_CROATIAN=m
+CONFIG_NLS_MAC_CYRILLIC=m
+CONFIG_NLS_MAC_GAELIC=m
+CONFIG_NLS_MAC_GREEK=m
+CONFIG_NLS_MAC_ICELAND=m
+CONFIG_NLS_MAC_INUIT=m
+CONFIG_NLS_MAC_ROMANIAN=m
+CONFIG_NLS_MAC_TURKISH=m
 CONFIG_DLM=m
 CONFIG_MAGIC_SYSRQ=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_ASYNC_RAID6_TEST=m
+CONFIG_ENCRYPTED_KEYS=m
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_USER=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_TEST=m
@@ -325,19 +431,16 @@ CONFIG_CRYPTO_CTS=m
 CONFIG_CRYPTO_LRW=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_VMAC=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_RMD128=m
 CONFIG_CRYPTO_RMD160=m
 CONFIG_CRYPTO_RMD256=m
 CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_TGR192=m
 CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_ANUBIS=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_CAMELLIA=m
@@ -353,6 +456,14 @@ CONFIG_CRYPTO_TWOFISH=m
 CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
 # CONFIG_CRYPTO_HW is not set
-CONFIG_CRC16=y
 CONFIG_CRC_T10DIF=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_TEST=m
diff --git a/arch/m68k/configs/bvme6000_defconfig b/arch/m68k/configs/bvme6000_defconfig
index 12f211733ba0..c015ddb6fd80 100644
--- a/arch/m68k/configs/bvme6000_defconfig
+++ b/arch/m68k/configs/bvme6000_defconfig
@@ -1,53 +1,74 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_LOCALVERSION="-bvme6000"
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_RELAY=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_VME=y
-CONFIG_BVME6000=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_AMIGA_PARTITION=y
+CONFIG_ATARI_PARTITION=y
+CONFIG_MAC_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_SUN_PARTITION=y
+# CONFIG_EFI_PARTITION is not set
+CONFIG_IOSCHED_DEADLINE=m
 CONFIG_M68040=y
 CONFIG_M68060=y
+CONFIG_VME=y
+CONFIG_BVME6000=y
+# CONFIG_COMPACTION is not set
+CONFIG_CLEANCACHE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
-CONFIG_PROC_HARDWARE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=m
 CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=m
+CONFIG_XFRM_MIGRATE=y
 CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 CONFIG_IP_PNP_RARP=y
 CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
 CONFIG_NET_IPGRE=m
 CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=m
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=m
+CONFIG_INET_UDP_DIAG=m
 CONFIG_IPV6_PRIVACY=y
 CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_GRE=m
 CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
 CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_ZONES=y
+# CONFIG_NF_CONNTRACK_PROCFS is not set
 # CONFIG_NF_CT_PROTO_DCCP is not set
 CONFIG_NF_CT_PROTO_UDPLITE=m
 CONFIG_NF_CONNTRACK_AMANDA=m
@@ -55,25 +76,37 @@ CONFIG_NF_CONNTRACK_FTP=m
 CONFIG_NF_CONNTRACK_H323=m
 CONFIG_NF_CONNTRACK_IRC=m
 CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
 CONFIG_NF_CONNTRACK_PPTP=m
 CONFIG_NF_CONNTRACK_SANE=m
 CONFIG_NF_CONNTRACK_SIP=m
 CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NETFILTER_XT_SET=m
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
 CONFIG_NETFILTER_XT_TARGET_MARK=m
 CONFIG_NETFILTER_XT_TARGET_NFLOG=m
 CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
 CONFIG_NETFILTER_XT_TARGET_TRACE=m
 CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
 CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
 CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
 CONFIG_NETFILTER_XT_MATCH_COMMENT=m
 CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
 CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
 CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
 CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
 CONFIG_NETFILTER_XT_MATCH_DSCP=m
 CONFIG_NETFILTER_XT_MATCH_ESP=m
 CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
@@ -84,6 +117,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m
 CONFIG_NETFILTER_XT_MATCH_MAC=m
 CONFIG_NETFILTER_XT_MATCH_MARK=m
 CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
 CONFIG_NETFILTER_XT_MATCH_OWNER=m
 CONFIG_NETFILTER_XT_MATCH_POLICY=m
 CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
@@ -97,22 +132,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 CONFIG_NETFILTER_XT_MATCH_TIME=m
 CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
 CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
 CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_NF_NAT=m
+CONFIG_NF_NAT_IPV4=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_NF_NAT_SNMP_BASIC=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_TARGET_ECN=m
@@ -122,7 +166,6 @@ CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_AH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
@@ -131,21 +174,34 @@ CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_HL=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
 CONFIG_IP6_NF_RAW=m
+CONFIG_NF_NAT_IPV6=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
 CONFIG_IP_DCCP=m
 # CONFIG_IP_DCCP_CCID3 is not set
+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
+CONFIG_RDS=m
+CONFIG_RDS_TCP=m
+CONFIG_L2TP=m
 CONFIG_ATALK=m
+CONFIG_BATMAN_ADV=m
+CONFIG_BATMAN_ADV_DAT=y
+# CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
+# CONFIG_FW_LOADER_USER_HELPER is not set
 CONFIG_CONNECTOR=m
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_DRBD=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_CDROM_PKTCDVD=m
@@ -160,103 +216,131 @@ CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=m
 CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_SAS_LIBSAS=m
-# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
-CONFIG_SCSI_SRP_ATTRS=m
-CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=m
 CONFIG_ISCSI_TCP=m
+CONFIG_ISCSI_BOOT_SYSFS=m
 CONFIG_BVME6000_SCSI=y
 CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
 CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID456=m
 CONFIG_BLK_DEV_DM=m
 CONFIG_DM_CRYPT=m
 CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_CACHE=m
 CONFIG_DM_MIRROR=m
+CONFIG_DM_RAID=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
 CONFIG_DM_UEVENT=y
+CONFIG_TARGET_CORE=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_PSCSI=m
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
-CONFIG_MACVLAN=m
 CONFIG_EQUALIZER=m
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_VXLAN=m
+CONFIG_NETCONSOLE=m
+CONFIG_NETCONSOLE_DYNAMIC=y
 CONFIG_VETH=m
-CONFIG_NET_ETHERNET=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
 CONFIG_BVME6000_NET=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
 CONFIG_PPP=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
 CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPTP=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_WLAN is not set
+CONFIG_INPUT_EVDEV=m
 # CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_MOUSE_PS2=m
-CONFIG_MOUSE_SERIAL=m
-CONFIG_SERIO=m
-# CONFIG_SERIO_SERPORT is not set
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_SERIO is not set
 CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 # CONFIG_HW_RANDOM is not set
-CONFIG_GEN_RTC=m
-CONFIG_GEN_RTC_X=y
+CONFIG_NTP_PPS=y
+CONFIG_PPS_CLIENT_LDISC=m
+CONFIG_PTP_1588_CLOCK=m
 # CONFIG_HWMON is not set
 CONFIG_HID=m
 CONFIG_HIDRAW=y
+CONFIG_UHID=m
+# CONFIG_HID_GENERIC is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PROC_HARDWARE=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
 CONFIG_REISERFS_FS=m
 CONFIG_JFS_FS=m
 CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
-# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
+CONFIG_FANOTIFY=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
 # CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
 CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
+CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_AFFS_FS=m
+CONFIG_ECRYPT_FS=m
+CONFIG_ECRYPT_FS_MESSAGING=y
 CONFIG_HFS_FS=m
 CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 CONFIG_SQUASHFS=m
-CONFIG_MINIX_FS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_MINIX_FS=m
+CONFIG_OMFS_FS=m
 CONFIG_HPFS_FS=m
+CONFIG_QNX4FS_FS=m
+CONFIG_QNX6FS_FS=m
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V4=y
+CONFIG_NFS_SWAP=y
 CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_CIFS=m
+# CONFIG_CIFS_DEBUG is not set
 CONFIG_CODA_FS=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
@@ -295,10 +379,23 @@ CONFIG_NLS_ISO8859_14=m
 CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_MAC_ROMAN=m
+CONFIG_NLS_MAC_CELTIC=m
+CONFIG_NLS_MAC_CENTEURO=m
+CONFIG_NLS_MAC_CROATIAN=m
+CONFIG_NLS_MAC_CYRILLIC=m
+CONFIG_NLS_MAC_GAELIC=m
+CONFIG_NLS_MAC_GREEK=m
+CONFIG_NLS_MAC_ICELAND=m
+CONFIG_NLS_MAC_INUIT=m
+CONFIG_NLS_MAC_ROMANIAN=m
+CONFIG_NLS_MAC_TURKISH=m
 CONFIG_DLM=m
 CONFIG_MAGIC_SYSRQ=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_ASYNC_RAID6_TEST=m
+CONFIG_ENCRYPTED_KEYS=m
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_USER=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_TEST=m
@@ -308,19 +405,16 @@ CONFIG_CRYPTO_CTS=m
 CONFIG_CRYPTO_LRW=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_VMAC=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_RMD128=m
 CONFIG_CRYPTO_RMD160=m
 CONFIG_CRYPTO_RMD256=m
 CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_TGR192=m
 CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_ANUBIS=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_CAMELLIA=m
@@ -336,7 +430,14 @@ CONFIG_CRYPTO_TWOFISH=m
 CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
 # CONFIG_CRYPTO_HW is not set
-CONFIG_CRC16=m
 CONFIG_CRC_T10DIF=y
-CONFIG_CRC32=m
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_TEST=m
diff --git a/arch/m68k/configs/hp300_defconfig b/arch/m68k/configs/hp300_defconfig
index 215389a5407f..ec7382d8afff 100644
--- a/arch/m68k/configs/hp300_defconfig
+++ b/arch/m68k/configs/hp300_defconfig
@@ -1,54 +1,76 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_LOCALVERSION="-hp300"
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_RELAY=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_HP300=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_AMIGA_PARTITION=y
+CONFIG_ATARI_PARTITION=y
+CONFIG_MAC_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_SUN_PARTITION=y
+# CONFIG_EFI_PARTITION is not set
+CONFIG_SYSV68_PARTITION=y
+CONFIG_IOSCHED_DEADLINE=m
 CONFIG_M68020=y
 CONFIG_M68030=y
 CONFIG_M68040=y
 CONFIG_M68060=y
+CONFIG_HP300=y
+# CONFIG_COMPACTION is not set
+CONFIG_CLEANCACHE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
-CONFIG_PROC_HARDWARE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=m
 CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=m
+CONFIG_XFRM_MIGRATE=y
 CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 CONFIG_IP_PNP_RARP=y
 CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
 CONFIG_NET_IPGRE=m
 CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=m
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=m
+CONFIG_INET_UDP_DIAG=m
 CONFIG_IPV6_PRIVACY=y
 CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_GRE=m
 CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
 CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_ZONES=y
+# CONFIG_NF_CONNTRACK_PROCFS is not set
 # CONFIG_NF_CT_PROTO_DCCP is not set
 CONFIG_NF_CT_PROTO_UDPLITE=m
 CONFIG_NF_CONNTRACK_AMANDA=m
@@ -56,25 +78,37 @@ CONFIG_NF_CONNTRACK_FTP=m
 CONFIG_NF_CONNTRACK_H323=m
 CONFIG_NF_CONNTRACK_IRC=m
 CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
 CONFIG_NF_CONNTRACK_PPTP=m
 CONFIG_NF_CONNTRACK_SANE=m
 CONFIG_NF_CONNTRACK_SIP=m
 CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NETFILTER_XT_SET=m
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
 CONFIG_NETFILTER_XT_TARGET_MARK=m
 CONFIG_NETFILTER_XT_TARGET_NFLOG=m
 CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
 CONFIG_NETFILTER_XT_TARGET_TRACE=m
 CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
 CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
 CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
 CONFIG_NETFILTER_XT_MATCH_COMMENT=m
 CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
 CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
 CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
 CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
 CONFIG_NETFILTER_XT_MATCH_DSCP=m
 CONFIG_NETFILTER_XT_MATCH_ESP=m
 CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
@@ -85,6 +119,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m
 CONFIG_NETFILTER_XT_MATCH_MAC=m
 CONFIG_NETFILTER_XT_MATCH_MARK=m
 CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
 CONFIG_NETFILTER_XT_MATCH_OWNER=m
 CONFIG_NETFILTER_XT_MATCH_POLICY=m
 CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
@@ -98,22 +134,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 CONFIG_NETFILTER_XT_MATCH_TIME=m
 CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
 CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
 CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_NF_NAT=m
+CONFIG_NF_NAT_IPV4=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_NF_NAT_SNMP_BASIC=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_TARGET_ECN=m
@@ -123,7 +168,6 @@ CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_AH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
@@ -132,21 +176,34 @@ CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_HL=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
 CONFIG_IP6_NF_RAW=m
+CONFIG_NF_NAT_IPV6=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
 CONFIG_IP_DCCP=m
 # CONFIG_IP_DCCP_CCID3 is not set
+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
+CONFIG_RDS=m
+CONFIG_RDS_TCP=m
+CONFIG_L2TP=m
 CONFIG_ATALK=m
+CONFIG_BATMAN_ADV=m
+CONFIG_BATMAN_ADV_DAT=y
+# CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
+# CONFIG_FW_LOADER_USER_HELPER is not set
 CONFIG_CONNECTOR=m
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_DRBD=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_CDROM_PKTCDVD=m
@@ -161,59 +218,77 @@ CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=m
 CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_SAS_LIBSAS=m
-# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
-CONFIG_SCSI_SRP_ATTRS=m
-CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=m
 CONFIG_ISCSI_TCP=m
+CONFIG_ISCSI_BOOT_SYSFS=m
 CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
 CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID456=m
 CONFIG_BLK_DEV_DM=m
 CONFIG_DM_CRYPT=m
 CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_CACHE=m
 CONFIG_DM_MIRROR=m
+CONFIG_DM_RAID=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
 CONFIG_DM_UEVENT=y
+CONFIG_TARGET_CORE=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_PSCSI=m
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
-CONFIG_MACVLAN=m
 CONFIG_EQUALIZER=m
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_VXLAN=m
+CONFIG_NETCONSOLE=m
+CONFIG_NETCONSOLE_DYNAMIC=y
 CONFIG_VETH=m
-CONFIG_NET_ETHERNET=y
 CONFIG_HPLANCE=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
 CONFIG_PPP=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
 CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPTP=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_WLAN is not set
+CONFIG_INPUT_EVDEV=m
 # CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_MOUSE_PS2=m
+# CONFIG_MOUSE_PS2 is not set
 CONFIG_MOUSE_SERIAL=m
 CONFIG_INPUT_MISC=y
 CONFIG_HP_SDC_RTC=m
-# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_SERPORT=m
 CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 # CONFIG_HW_RANDOM is not set
-CONFIG_GEN_RTC=m
-CONFIG_GEN_RTC_X=y
+CONFIG_NTP_PPS=y
+CONFIG_PPS_CLIENT_LDISC=m
+CONFIG_PTP_1588_CLOCK=m
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
@@ -222,47 +297,60 @@ CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_VGA16 is not set
 CONFIG_HID=m
 CONFIG_HIDRAW=y
+CONFIG_UHID=m
+# CONFIG_HID_GENERIC is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PROC_HARDWARE=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
 CONFIG_REISERFS_FS=m
 CONFIG_JFS_FS=m
 CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
-# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
+CONFIG_FANOTIFY=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
 # CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
 CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
+CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_AFFS_FS=m
+CONFIG_ECRYPT_FS=m
+CONFIG_ECRYPT_FS_MESSAGING=y
 CONFIG_HFS_FS=m
 CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 CONFIG_SQUASHFS=m
-CONFIG_MINIX_FS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_MINIX_FS=m
+CONFIG_OMFS_FS=m
 CONFIG_HPFS_FS=m
+CONFIG_QNX4FS_FS=m
+CONFIG_QNX6FS_FS=m
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V4=y
+CONFIG_NFS_SWAP=y
 CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_CIFS=m
+# CONFIG_CIFS_DEBUG is not set
 CONFIG_CODA_FS=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
@@ -301,10 +389,23 @@ CONFIG_NLS_ISO8859_14=m
 CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_MAC_ROMAN=m
+CONFIG_NLS_MAC_CELTIC=m
+CONFIG_NLS_MAC_CENTEURO=m
+CONFIG_NLS_MAC_CROATIAN=m
+CONFIG_NLS_MAC_CYRILLIC=m
+CONFIG_NLS_MAC_GAELIC=m
+CONFIG_NLS_MAC_GREEK=m
+CONFIG_NLS_MAC_ICELAND=m
+CONFIG_NLS_MAC_INUIT=m
+CONFIG_NLS_MAC_ROMANIAN=m
+CONFIG_NLS_MAC_TURKISH=m
 CONFIG_DLM=m
 CONFIG_MAGIC_SYSRQ=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_ASYNC_RAID6_TEST=m
+CONFIG_ENCRYPTED_KEYS=m
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_USER=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_TEST=m
@@ -314,19 +415,16 @@ CONFIG_CRYPTO_CTS=m
 CONFIG_CRYPTO_LRW=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_VMAC=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_RMD128=m
 CONFIG_CRYPTO_RMD160=m
 CONFIG_CRYPTO_RMD256=m
 CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_TGR192=m
 CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_ANUBIS=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_CAMELLIA=m
@@ -342,6 +440,14 @@ CONFIG_CRYPTO_TWOFISH=m
 CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
 # CONFIG_CRYPTO_HW is not set
-CONFIG_CRC16=m
 CONFIG_CRC_T10DIF=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_TEST=m
diff --git a/arch/m68k/configs/mac_defconfig b/arch/m68k/configs/mac_defconfig
index cb9dfb30b674..7d46fbec7042 100644
--- a/arch/m68k/configs/mac_defconfig
+++ b/arch/m68k/configs/mac_defconfig
@@ -1,49 +1,75 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_LOCALVERSION="-mac"
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_RELAY=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_MAC=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_AMIGA_PARTITION=y
+CONFIG_ATARI_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_SUN_PARTITION=y
+# CONFIG_EFI_PARTITION is not set
+CONFIG_SYSV68_PARTITION=y
+CONFIG_IOSCHED_DEADLINE=m
 CONFIG_M68020=y
 CONFIG_M68030=y
 CONFIG_M68040=y
+CONFIG_M68KFPU_EMU=y
+CONFIG_MAC=y
+# CONFIG_COMPACTION is not set
+CONFIG_CLEANCACHE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
-CONFIG_PROC_HARDWARE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=m
 CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=m
+CONFIG_XFRM_MIGRATE=y
 CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
 CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
 CONFIG_NET_IPGRE=m
 CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=m
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=m
+CONFIG_INET_UDP_DIAG=m
 CONFIG_IPV6_PRIVACY=y
 CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_GRE=m
 CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
 CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_ZONES=y
+# CONFIG_NF_CONNTRACK_PROCFS is not set
 # CONFIG_NF_CT_PROTO_DCCP is not set
 CONFIG_NF_CT_PROTO_UDPLITE=m
 CONFIG_NF_CONNTRACK_AMANDA=m
@@ -51,25 +77,37 @@ CONFIG_NF_CONNTRACK_FTP=m
 CONFIG_NF_CONNTRACK_H323=m
 CONFIG_NF_CONNTRACK_IRC=m
 CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
 CONFIG_NF_CONNTRACK_PPTP=m
 CONFIG_NF_CONNTRACK_SANE=m
 CONFIG_NF_CONNTRACK_SIP=m
 CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NETFILTER_XT_SET=m
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
 CONFIG_NETFILTER_XT_TARGET_MARK=m
 CONFIG_NETFILTER_XT_TARGET_NFLOG=m
 CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
 CONFIG_NETFILTER_XT_TARGET_TRACE=m
 CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
 CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
 CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
 CONFIG_NETFILTER_XT_MATCH_COMMENT=m
 CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
 CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
 CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
 CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
 CONFIG_NETFILTER_XT_MATCH_DSCP=m
 CONFIG_NETFILTER_XT_MATCH_ESP=m
 CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
@@ -80,6 +118,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m
 CONFIG_NETFILTER_XT_MATCH_MAC=m
 CONFIG_NETFILTER_XT_MATCH_MARK=m
 CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
 CONFIG_NETFILTER_XT_MATCH_OWNER=m
 CONFIG_NETFILTER_XT_MATCH_POLICY=m
 CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
@@ -93,22 +133,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 CONFIG_NETFILTER_XT_MATCH_TIME=m
 CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
 CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
 CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_NF_NAT=m
+CONFIG_NF_NAT_IPV4=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_NF_NAT_SNMP_BASIC=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_TARGET_ECN=m
@@ -118,7 +167,6 @@ CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_AH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
@@ -127,31 +175,45 @@ CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_HL=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
 CONFIG_IP6_NF_RAW=m
+CONFIG_NF_NAT_IPV6=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
 CONFIG_IP_DCCP=m
 # CONFIG_IP_DCCP_CCID3 is not set
+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
+CONFIG_RDS=m
+CONFIG_RDS_TCP=m
+CONFIG_L2TP=m
 CONFIG_ATALK=m
 CONFIG_DEV_APPLETALK=m
 CONFIG_IPDDP=m
 CONFIG_IPDDP_ENCAP=y
 CONFIG_IPDDP_DECAP=y
+CONFIG_BATMAN_ADV=m
+CONFIG_BATMAN_ADV_DAT=y
+# CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
+# CONFIG_FW_LOADER_USER_HELPER is not set
 CONFIG_CONNECTOR=m
-CONFIG_BLK_DEV_SWIM=y
+CONFIG_BLK_DEV_SWIM=m
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_DRBD=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_CDROM_PKTCDVD=m
 CONFIG_ATA_OVER_ETH=m
 CONFIG_IDE=y
+CONFIG_IDE_GD_ATAPI=y
 CONFIG_BLK_DEV_IDECD=y
 CONFIG_BLK_DEV_MAC_IDE=y
 CONFIG_RAID_ATTRS=m
@@ -164,29 +226,30 @@ CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=m
 CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_SAS_LIBSAS=m
-# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
-CONFIG_SCSI_SRP_ATTRS=m
-CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=m
 CONFIG_ISCSI_TCP=m
+CONFIG_ISCSI_BOOT_SYSFS=m
 CONFIG_MAC_SCSI=y
 CONFIG_SCSI_MAC_ESP=y
 CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
 CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID456=m
 CONFIG_BLK_DEV_DM=m
 CONFIG_DM_CRYPT=m
 CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_CACHE=m
 CONFIG_DM_MIRROR=m
+CONFIG_DM_RAID=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
 CONFIG_DM_UEVENT=y
+CONFIG_TARGET_CORE=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_PSCSI=m
 CONFIG_ADB=y
 CONFIG_ADB_MACII=y
-CONFIG_ADB_MACIISI=y
 CONFIG_ADB_IOP=y
 CONFIG_ADB_PMU68K=y
 CONFIG_ADB_CUDA=y
@@ -194,46 +257,61 @@ CONFIG_INPUT_ADBHID=y
 CONFIG_MAC_EMUMOUSEBTN=y
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
-CONFIG_MACVLAN=m
 CONFIG_EQUALIZER=m
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_VXLAN=m
+CONFIG_NETCONSOLE=m
+CONFIG_NETCONSOLE_DYNAMIC=y
 CONFIG_VETH=m
-CONFIG_NET_ETHERNET=y
-CONFIG_MAC8390=y
-CONFIG_MAC89x0=m
-CONFIG_MACSONIC=m
 CONFIG_MACMACE=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+CONFIG_MAC89x0=y
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+CONFIG_MACSONIC=y
+CONFIG_MAC8390=y
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
 CONFIG_PPP=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
 CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPTP=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_WLAN is not set
+CONFIG_INPUT_EVDEV=m
 # CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_MOUSE_PS2=m
+# CONFIG_MOUSE_PS2 is not set
 CONFIG_MOUSE_SERIAL=m
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_M68K_BEEP=m
 CONFIG_SERIO=m
-# CONFIG_SERIO_SERPORT is not set
 CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_PMACZILOG=y
 CONFIG_SERIAL_PMACZILOG_TTYS=y
 CONFIG_SERIAL_PMACZILOG_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
-CONFIG_GEN_RTC=m
-CONFIG_GEN_RTC_X=y
+CONFIG_NTP_PPS=y
+CONFIG_PPS_CLIENT_LDISC=m
+CONFIG_PTP_1588_CLOCK=m
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FB_VALKYRIE=y
@@ -242,46 +320,60 @@ CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
 CONFIG_HID=m
 CONFIG_HIDRAW=y
+CONFIG_UHID=m
+# CONFIG_HID_GENERIC is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PROC_HARDWARE=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
 CONFIG_REISERFS_FS=m
 CONFIG_JFS_FS=m
 CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
-# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
+CONFIG_FANOTIFY=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
 # CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
 CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
+CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_AFFS_FS=m
-CONFIG_HFS_FS=y
-CONFIG_HFSPLUS_FS=y
+CONFIG_ECRYPT_FS=m
+CONFIG_ECRYPT_FS_MESSAGING=y
+CONFIG_HFS_FS=m
+CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 CONFIG_SQUASHFS=m
-CONFIG_MINIX_FS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_MINIX_FS=m
+CONFIG_OMFS_FS=m
 CONFIG_HPFS_FS=m
+CONFIG_QNX4FS_FS=m
+CONFIG_QNX6FS_FS=m
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
+CONFIG_NFS_FS=y
 CONFIG_NFS_V4=y
+CONFIG_NFS_SWAP=y
+CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_CIFS=m
+# CONFIG_CIFS_DEBUG is not set
 CONFIG_CODA_FS=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
@@ -320,10 +412,23 @@ CONFIG_NLS_ISO8859_14=m
 CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_MAC_ROMAN=m
+CONFIG_NLS_MAC_CELTIC=m
+CONFIG_NLS_MAC_CENTEURO=m
+CONFIG_NLS_MAC_CROATIAN=m
+CONFIG_NLS_MAC_CYRILLIC=m
+CONFIG_NLS_MAC_GAELIC=m
+CONFIG_NLS_MAC_GREEK=m
+CONFIG_NLS_MAC_ICELAND=m
+CONFIG_NLS_MAC_INUIT=m
+CONFIG_NLS_MAC_ROMANIAN=m
+CONFIG_NLS_MAC_TURKISH=m
 CONFIG_DLM=m
 CONFIG_MAGIC_SYSRQ=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_ASYNC_RAID6_TEST=m
+CONFIG_ENCRYPTED_KEYS=m
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_USER=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_TEST=m
@@ -333,19 +438,16 @@ CONFIG_CRYPTO_CTS=m
 CONFIG_CRYPTO_LRW=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_VMAC=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_RMD128=m
 CONFIG_CRYPTO_RMD160=m
 CONFIG_CRYPTO_RMD256=m
 CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_TGR192=m
 CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_ANUBIS=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_CAMELLIA=m
@@ -361,6 +463,14 @@ CONFIG_CRYPTO_TWOFISH=m
 CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
 # CONFIG_CRYPTO_HW is not set
-CONFIG_CRC16=m
 CONFIG_CRC_T10DIF=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_TEST=m
diff --git a/arch/m68k/configs/multi_defconfig b/arch/m68k/configs/multi_defconfig
index 8d5def4a31e0..0f795d8e65fa 100644
--- a/arch/m68k/configs/multi_defconfig
+++ b/arch/m68k/configs/multi_defconfig
@@ -1,15 +1,29 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_LOCALVERSION="-multi"
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_RELAY=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+# CONFIG_EFI_PARTITION is not set
+CONFIG_IOSCHED_DEADLINE=m
+CONFIG_M68020=y
+CONFIG_M68040=y
+CONFIG_M68060=y
+CONFIG_M68KFPU_EMU=y
 CONFIG_AMIGA=y
 CONFIG_ATARI=y
 CONFIG_MAC=y
@@ -21,48 +35,50 @@ CONFIG_BVME6000=y
 CONFIG_HP300=y
 CONFIG_SUN3X=y
 CONFIG_Q40=y
-CONFIG_M68020=y
-CONFIG_M68040=y
-CONFIG_M68060=y
-CONFIG_BINFMT_AOUT=m
-CONFIG_BINFMT_MISC=m
 CONFIG_ZORRO=y
 CONFIG_AMIGA_PCMCIA=y
-CONFIG_STRAM_PROC=y
-CONFIG_HEARTBEAT=y
-CONFIG_PROC_HARDWARE=y
 CONFIG_ZORRO_NAMES=y
+# CONFIG_COMPACTION is not set
+CONFIG_CLEANCACHE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_MISC=m
 CONFIG_NET=y
 CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=m
 CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=m
+CONFIG_XFRM_MIGRATE=y
 CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 CONFIG_IP_PNP_RARP=y
 CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
 CONFIG_NET_IPGRE=m
 CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=m
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=m
+CONFIG_INET_UDP_DIAG=m
 CONFIG_IPV6_PRIVACY=y
 CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_GRE=m
 CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
 CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_ZONES=y
+# CONFIG_NF_CONNTRACK_PROCFS is not set
 # CONFIG_NF_CT_PROTO_DCCP is not set
 CONFIG_NF_CT_PROTO_UDPLITE=m
 CONFIG_NF_CONNTRACK_AMANDA=m
@@ -70,25 +86,37 @@ CONFIG_NF_CONNTRACK_FTP=m
 CONFIG_NF_CONNTRACK_H323=m
 CONFIG_NF_CONNTRACK_IRC=m
 CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
 CONFIG_NF_CONNTRACK_PPTP=m
 CONFIG_NF_CONNTRACK_SANE=m
 CONFIG_NF_CONNTRACK_SIP=m
 CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NETFILTER_XT_SET=m
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
 CONFIG_NETFILTER_XT_TARGET_MARK=m
 CONFIG_NETFILTER_XT_TARGET_NFLOG=m
 CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
 CONFIG_NETFILTER_XT_TARGET_TRACE=m
 CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
 CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
 CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
 CONFIG_NETFILTER_XT_MATCH_COMMENT=m
 CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
 CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
 CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
 CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
 CONFIG_NETFILTER_XT_MATCH_DSCP=m
 CONFIG_NETFILTER_XT_MATCH_ESP=m
 CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
@@ -99,6 +127,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m
 CONFIG_NETFILTER_XT_MATCH_MAC=m
 CONFIG_NETFILTER_XT_MATCH_MARK=m
 CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
 CONFIG_NETFILTER_XT_MATCH_OWNER=m
 CONFIG_NETFILTER_XT_MATCH_POLICY=m
 CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
@@ -112,22 +142,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 CONFIG_NETFILTER_XT_MATCH_TIME=m
 CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
 CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
 CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_NF_NAT=m
+CONFIG_NF_NAT_IPV4=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_NF_NAT_SNMP_BASIC=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_TARGET_ECN=m
@@ -137,7 +176,6 @@ CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_AH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
@@ -146,22 +184,34 @@ CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_HL=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
 CONFIG_IP6_NF_RAW=m
+CONFIG_NF_NAT_IPV6=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
 CONFIG_IP_DCCP=m
 # CONFIG_IP_DCCP_CCID3 is not set
+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
+CONFIG_RDS=m
+CONFIG_RDS_TCP=m
+CONFIG_L2TP=m
 CONFIG_ATALK=m
 CONFIG_DEV_APPLETALK=m
 CONFIG_IPDDP=m
 CONFIG_IPDDP_ENCAP=y
 CONFIG_IPDDP_DECAP=y
+CONFIG_BATMAN_ADV=m
+CONFIG_BATMAN_ADV_DAT=y
+# CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
+# CONFIG_FW_LOADER_USER_HELPER is not set
 CONFIG_CONNECTOR=m
 CONFIG_PARPORT=m
 CONFIG_PARPORT_AMIGA=m
@@ -170,15 +220,17 @@ CONFIG_PARPORT_ATARI=m
 CONFIG_PARPORT_1284=y
 CONFIG_AMIGA_FLOPPY=y
 CONFIG_ATARI_FLOPPY=y
-CONFIG_BLK_DEV_SWIM=y
+CONFIG_BLK_DEV_SWIM=m
 CONFIG_AMIGA_Z2RAM=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_DRBD=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_CDROM_PKTCDVD=m
 CONFIG_ATA_OVER_ETH=m
 CONFIG_IDE=y
+CONFIG_IDE_GD_ATAPI=y
 CONFIG_BLK_DEV_IDECD=y
 CONFIG_BLK_DEV_GAYLE=y
 CONFIG_BLK_DEV_BUDDHA=y
@@ -195,11 +247,9 @@ CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=m
 CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_SAS_LIBSAS=m
-# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
-CONFIG_SCSI_SRP_ATTRS=m
-CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=m
 CONFIG_ISCSI_TCP=m
+CONFIG_ISCSI_BOOT_SYSFS=m
 CONFIG_A3000_SCSI=y
 CONFIG_A2091_SCSI=y
 CONFIG_GVP11_SCSI=y
@@ -213,21 +263,24 @@ CONFIG_MVME16x_SCSI=y
 CONFIG_BVME6000_SCSI=y
 CONFIG_SUN3X_ESP=y
 CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
 CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID456=m
 CONFIG_BLK_DEV_DM=m
 CONFIG_DM_CRYPT=m
 CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_CACHE=m
 CONFIG_DM_MIRROR=m
+CONFIG_DM_RAID=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
 CONFIG_DM_UEVENT=y
+CONFIG_TARGET_CORE=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_PSCSI=m
 CONFIG_ADB=y
 CONFIG_ADB_MACII=y
-CONFIG_ADB_MACIISI=y
 CONFIG_ADB_IOP=y
 CONFIG_ADB_PMU68K=y
 CONFIG_ADB_CUDA=y
@@ -235,49 +288,64 @@ CONFIG_INPUT_ADBHID=y
 CONFIG_MAC_EMUMOUSEBTN=y
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
-CONFIG_MACVLAN=m
 CONFIG_EQUALIZER=m
-CONFIG_VETH=m
-CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
-CONFIG_ARIADNE=y
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_VXLAN=m
+CONFIG_NETCONSOLE=m
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_VETH=m
+# CONFIG_NET_VENDOR_3COM is not set
 CONFIG_A2065=y
-CONFIG_HYDRA=y
-CONFIG_ZORRO8390=y
-CONFIG_APNE=y
-CONFIG_MAC8390=y
-CONFIG_MAC89x0=y
-CONFIG_MACSONIC=y
-CONFIG_MACMACE=y
-CONFIG_MVME147_NET=y
-CONFIG_MVME16x_NET=y
-CONFIG_BVME6000_NET=y
+CONFIG_ARIADNE=y
 CONFIG_ATARILANCE=y
-CONFIG_SUN3LANCE=y
 CONFIG_HPLANCE=y
+CONFIG_MVME147_NET=y
+CONFIG_SUN3LANCE=y
+CONFIG_MACMACE=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+CONFIG_MAC89x0=y
+# CONFIG_NET_VENDOR_FUJITSU is not set
+# CONFIG_NET_VENDOR_HP is not set
+CONFIG_BVME6000_NET=y
+CONFIG_MVME16x_NET=y
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+CONFIG_MACSONIC=y
+CONFIG_HYDRA=y
+CONFIG_MAC8390=y
 CONFIG_NE2000=m
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+CONFIG_APNE=y
+CONFIG_ZORRO8390=y
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
 CONFIG_PPP=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
 CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPTP=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_WLAN is not set
+CONFIG_INPUT_EVDEV=m
 CONFIG_KEYBOARD_AMIGA=y
 CONFIG_KEYBOARD_ATARI=y
 # CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_SUNKBD=y
-CONFIG_MOUSE_PS2=m
+# CONFIG_MOUSE_PS2 is not set
 CONFIG_MOUSE_SERIAL=m
 CONFIG_MOUSE_AMIGA=m
 CONFIG_MOUSE_ATARI=m
@@ -285,18 +353,20 @@ CONFIG_INPUT_JOYSTICK=y
 CONFIG_JOYSTICK_AMIGA=m
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_M68K_BEEP=m
-CONFIG_HP_SDC_RTC=y
-# CONFIG_SERIO_SERPORT is not set
+CONFIG_HP_SDC_RTC=m
 CONFIG_SERIO_Q40KBD=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_PMACZILOG=y
 CONFIG_SERIAL_PMACZILOG_TTYS=y
 CONFIG_SERIAL_PMACZILOG_CONSOLE=y
 CONFIG_PRINTER=m
 # CONFIG_HW_RANDOM is not set
-CONFIG_GEN_RTC=y
-CONFIG_GEN_RTC_X=y
+CONFIG_NTP_PPS=y
+CONFIG_PPS_CLIENT_LDISC=m
+CONFIG_PPS_CLIENT_PARPORT=m
+CONFIG_PTP_1588_CLOCK=m
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FB_CIRRUS=y
@@ -316,7 +386,20 @@ CONFIG_DMASOUND_PAULA=m
 CONFIG_DMASOUND_Q40=m
 CONFIG_HID=m
 CONFIG_HIDRAW=y
+CONFIG_UHID=m
+# CONFIG_HID_GENERIC is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_MSM6242=m
+CONFIG_RTC_DRV_RP5C01=m
+CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_HEARTBEAT=y
+CONFIG_PROC_HARDWARE=y
+CONFIG_NATFEAT=y
+CONFIG_NFBLOCK=y
+CONFIG_NFCON=y
+CONFIG_NFETH=y
 CONFIG_ATARI_DSP56K=m
 CONFIG_AMIGA_BUILTIN_SERIAL=y
 CONFIG_SERIAL_CONSOLE=y
@@ -324,42 +407,49 @@ CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
 CONFIG_REISERFS_FS=m
 CONFIG_JFS_FS=m
 CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
-# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
+CONFIG_FANOTIFY=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
 # CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
 CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
+CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_AFFS_FS=m
-CONFIG_HFS_FS=y
-CONFIG_HFSPLUS_FS=y
+CONFIG_ECRYPT_FS=m
+CONFIG_ECRYPT_FS_MESSAGING=y
+CONFIG_HFS_FS=m
+CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 CONFIG_SQUASHFS=m
-CONFIG_MINIX_FS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_MINIX_FS=m
+CONFIG_OMFS_FS=m
 CONFIG_HPFS_FS=m
+CONFIG_QNX4FS_FS=m
+CONFIG_QNX6FS_FS=m
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V4=y
+CONFIG_NFS_SWAP=y
 CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_CIFS=m
+# CONFIG_CIFS_DEBUG is not set
 CONFIG_CODA_FS=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
@@ -398,10 +488,23 @@ CONFIG_NLS_ISO8859_14=m
 CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_MAC_ROMAN=m
+CONFIG_NLS_MAC_CELTIC=m
+CONFIG_NLS_MAC_CENTEURO=m
+CONFIG_NLS_MAC_CROATIAN=m
+CONFIG_NLS_MAC_CYRILLIC=m
+CONFIG_NLS_MAC_GAELIC=m
+CONFIG_NLS_MAC_GREEK=m
+CONFIG_NLS_MAC_ICELAND=m
+CONFIG_NLS_MAC_INUIT=m
+CONFIG_NLS_MAC_ROMANIAN=m
+CONFIG_NLS_MAC_TURKISH=m
 CONFIG_DLM=m
 CONFIG_MAGIC_SYSRQ=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_ASYNC_RAID6_TEST=m
+CONFIG_ENCRYPTED_KEYS=m
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_USER=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_TEST=m
@@ -411,19 +514,16 @@ CONFIG_CRYPTO_CTS=m
 CONFIG_CRYPTO_LRW=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_VMAC=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_RMD128=m
 CONFIG_CRYPTO_RMD160=m
 CONFIG_CRYPTO_RMD256=m
 CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_TGR192=m
 CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_ANUBIS=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_CAMELLIA=m
@@ -439,6 +539,14 @@ CONFIG_CRYPTO_TWOFISH=m
 CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
 # CONFIG_CRYPTO_HW is not set
-CONFIG_CRC16=y
 CONFIG_CRC_T10DIF=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_TEST=m
diff --git a/arch/m68k/configs/mvme147_defconfig b/arch/m68k/configs/mvme147_defconfig
index e2af46f530c1..5586c6529fce 100644
--- a/arch/m68k/configs/mvme147_defconfig
+++ b/arch/m68k/configs/mvme147_defconfig
@@ -1,52 +1,73 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_LOCALVERSION="-mvme147"
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_RELAY=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_AMIGA_PARTITION=y
+CONFIG_ATARI_PARTITION=y
+CONFIG_MAC_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_SUN_PARTITION=y
+# CONFIG_EFI_PARTITION is not set
+CONFIG_IOSCHED_DEADLINE=m
+CONFIG_M68030=y
 CONFIG_VME=y
 CONFIG_MVME147=y
-CONFIG_M68030=y
+# CONFIG_COMPACTION is not set
+CONFIG_CLEANCACHE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
-CONFIG_PROC_HARDWARE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=m
 CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=m
+CONFIG_XFRM_MIGRATE=y
 CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 CONFIG_IP_PNP_RARP=y
 CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
 CONFIG_NET_IPGRE=m
 CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=m
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=m
+CONFIG_INET_UDP_DIAG=m
 CONFIG_IPV6_PRIVACY=y
 CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_GRE=m
 CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
 CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_ZONES=y
+# CONFIG_NF_CONNTRACK_PROCFS is not set
 # CONFIG_NF_CT_PROTO_DCCP is not set
 CONFIG_NF_CT_PROTO_UDPLITE=m
 CONFIG_NF_CONNTRACK_AMANDA=m
@@ -54,25 +75,37 @@ CONFIG_NF_CONNTRACK_FTP=m
 CONFIG_NF_CONNTRACK_H323=m
 CONFIG_NF_CONNTRACK_IRC=m
 CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
 CONFIG_NF_CONNTRACK_PPTP=m
 CONFIG_NF_CONNTRACK_SANE=m
 CONFIG_NF_CONNTRACK_SIP=m
 CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NETFILTER_XT_SET=m
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
 CONFIG_NETFILTER_XT_TARGET_MARK=m
 CONFIG_NETFILTER_XT_TARGET_NFLOG=m
 CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
 CONFIG_NETFILTER_XT_TARGET_TRACE=m
 CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
 CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
 CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
 CONFIG_NETFILTER_XT_MATCH_COMMENT=m
 CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
 CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
 CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
 CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
 CONFIG_NETFILTER_XT_MATCH_DSCP=m
 CONFIG_NETFILTER_XT_MATCH_ESP=m
 CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
@@ -83,6 +116,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m
 CONFIG_NETFILTER_XT_MATCH_MAC=m
 CONFIG_NETFILTER_XT_MATCH_MARK=m
 CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
 CONFIG_NETFILTER_XT_MATCH_OWNER=m
 CONFIG_NETFILTER_XT_MATCH_POLICY=m
 CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
@@ -96,22 +131,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 CONFIG_NETFILTER_XT_MATCH_TIME=m
 CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
 CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
 CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_NF_NAT=m
+CONFIG_NF_NAT_IPV4=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_NF_NAT_SNMP_BASIC=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_TARGET_ECN=m
@@ -121,7 +165,6 @@ CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_AH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
@@ -130,21 +173,34 @@ CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_HL=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
 CONFIG_IP6_NF_RAW=m
+CONFIG_NF_NAT_IPV6=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
 CONFIG_IP_DCCP=m
 # CONFIG_IP_DCCP_CCID3 is not set
+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
+CONFIG_RDS=m
+CONFIG_RDS_TCP=m
+CONFIG_L2TP=m
 CONFIG_ATALK=m
+CONFIG_BATMAN_ADV=m
+CONFIG_BATMAN_ADV_DAT=y
+# CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
+# CONFIG_FW_LOADER_USER_HELPER is not set
 CONFIG_CONNECTOR=m
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_DRBD=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_CDROM_PKTCDVD=m
@@ -159,103 +215,132 @@ CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=m
 CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_SAS_LIBSAS=m
-# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
-CONFIG_SCSI_SRP_ATTRS=m
-CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=m
 CONFIG_ISCSI_TCP=m
+CONFIG_ISCSI_BOOT_SYSFS=m
 CONFIG_MVME147_SCSI=y
 CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
 CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID456=m
 CONFIG_BLK_DEV_DM=m
 CONFIG_DM_CRYPT=m
 CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_CACHE=m
 CONFIG_DM_MIRROR=m
+CONFIG_DM_RAID=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
 CONFIG_DM_UEVENT=y
+CONFIG_TARGET_CORE=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_PSCSI=m
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
-CONFIG_MACVLAN=m
 CONFIG_EQUALIZER=m
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_VXLAN=m
+CONFIG_NETCONSOLE=m
+CONFIG_NETCONSOLE_DYNAMIC=y
 CONFIG_VETH=m
-CONFIG_NET_ETHERNET=y
 CONFIG_MVME147_NET=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
 CONFIG_PPP=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
 CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPTP=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_WLAN is not set
+CONFIG_INPUT_EVDEV=m
 # CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_MOUSE_PS2=m
-CONFIG_MOUSE_SERIAL=m
-CONFIG_SERIO=m
-# CONFIG_SERIO_SERPORT is not set
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_SERIO is not set
 CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 # CONFIG_HW_RANDOM is not set
-CONFIG_GEN_RTC=m
-CONFIG_GEN_RTC_X=y
+CONFIG_NTP_PPS=y
+CONFIG_PPS_CLIENT_LDISC=m
+CONFIG_PTP_1588_CLOCK=m
 # CONFIG_HWMON is not set
 CONFIG_HID=m
 CONFIG_HIDRAW=y
+CONFIG_UHID=m
+# CONFIG_HID_GENERIC is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PROC_HARDWARE=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
 CONFIG_REISERFS_FS=m
 CONFIG_JFS_FS=m
 CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
-# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
+CONFIG_FANOTIFY=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
 # CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
 CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
+CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_AFFS_FS=m
+CONFIG_ECRYPT_FS=m
+CONFIG_ECRYPT_FS_MESSAGING=y
 CONFIG_HFS_FS=m
 CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 CONFIG_SQUASHFS=m
-CONFIG_MINIX_FS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_MINIX_FS=m
+CONFIG_OMFS_FS=m
 CONFIG_HPFS_FS=m
+CONFIG_QNX4FS_FS=m
+CONFIG_QNX6FS_FS=m
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V4=y
+CONFIG_NFS_SWAP=y
 CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_CIFS=m
+# CONFIG_CIFS_DEBUG is not set
 CONFIG_CODA_FS=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
@@ -294,10 +379,23 @@ CONFIG_NLS_ISO8859_14=m
 CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_MAC_ROMAN=m
+CONFIG_NLS_MAC_CELTIC=m
+CONFIG_NLS_MAC_CENTEURO=m
+CONFIG_NLS_MAC_CROATIAN=m
+CONFIG_NLS_MAC_CYRILLIC=m
+CONFIG_NLS_MAC_GAELIC=m
+CONFIG_NLS_MAC_GREEK=m
+CONFIG_NLS_MAC_ICELAND=m
+CONFIG_NLS_MAC_INUIT=m
+CONFIG_NLS_MAC_ROMANIAN=m
+CONFIG_NLS_MAC_TURKISH=m
 CONFIG_DLM=m
 CONFIG_MAGIC_SYSRQ=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_ASYNC_RAID6_TEST=m
+CONFIG_ENCRYPTED_KEYS=m
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_USER=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_TEST=m
@@ -307,19 +405,16 @@ CONFIG_CRYPTO_CTS=m
 CONFIG_CRYPTO_LRW=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_VMAC=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_RMD128=m
 CONFIG_CRYPTO_RMD160=m
 CONFIG_CRYPTO_RMD256=m
 CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_TGR192=m
 CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_ANUBIS=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_CAMELLIA=m
@@ -335,6 +430,14 @@ CONFIG_CRYPTO_TWOFISH=m
 CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
 # CONFIG_CRYPTO_HW is not set
-CONFIG_CRC16=m
 CONFIG_CRC_T10DIF=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_TEST=m
diff --git a/arch/m68k/configs/mvme16x_defconfig b/arch/m68k/configs/mvme16x_defconfig
index 7c9402b2097f..e5e8262bbacd 100644
--- a/arch/m68k/configs/mvme16x_defconfig
+++ b/arch/m68k/configs/mvme16x_defconfig
@@ -1,53 +1,74 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_LOCALVERSION="-mvme16x"
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_RELAY=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_VME=y
-CONFIG_MVME16x=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_AMIGA_PARTITION=y
+CONFIG_ATARI_PARTITION=y
+CONFIG_MAC_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_SUN_PARTITION=y
+# CONFIG_EFI_PARTITION is not set
+CONFIG_IOSCHED_DEADLINE=m
 CONFIG_M68040=y
 CONFIG_M68060=y
+CONFIG_VME=y
+CONFIG_MVME16x=y
+# CONFIG_COMPACTION is not set
+CONFIG_CLEANCACHE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
-CONFIG_PROC_HARDWARE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=m
 CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=m
+CONFIG_XFRM_MIGRATE=y
 CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 CONFIG_IP_PNP_RARP=y
 CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
 CONFIG_NET_IPGRE=m
 CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=m
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=m
+CONFIG_INET_UDP_DIAG=m
 CONFIG_IPV6_PRIVACY=y
 CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_GRE=m
 CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
 CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_ZONES=y
+# CONFIG_NF_CONNTRACK_PROCFS is not set
 # CONFIG_NF_CT_PROTO_DCCP is not set
 CONFIG_NF_CT_PROTO_UDPLITE=m
 CONFIG_NF_CONNTRACK_AMANDA=m
@@ -55,25 +76,37 @@ CONFIG_NF_CONNTRACK_FTP=m
 CONFIG_NF_CONNTRACK_H323=m
 CONFIG_NF_CONNTRACK_IRC=m
 CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
 CONFIG_NF_CONNTRACK_PPTP=m
 CONFIG_NF_CONNTRACK_SANE=m
 CONFIG_NF_CONNTRACK_SIP=m
 CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NETFILTER_XT_SET=m
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
 CONFIG_NETFILTER_XT_TARGET_MARK=m
 CONFIG_NETFILTER_XT_TARGET_NFLOG=m
 CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
 CONFIG_NETFILTER_XT_TARGET_TRACE=m
 CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
 CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
 CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
 CONFIG_NETFILTER_XT_MATCH_COMMENT=m
 CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
 CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
 CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
 CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
 CONFIG_NETFILTER_XT_MATCH_DSCP=m
 CONFIG_NETFILTER_XT_MATCH_ESP=m
 CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
@@ -84,6 +117,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m
 CONFIG_NETFILTER_XT_MATCH_MAC=m
 CONFIG_NETFILTER_XT_MATCH_MARK=m
 CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
 CONFIG_NETFILTER_XT_MATCH_OWNER=m
 CONFIG_NETFILTER_XT_MATCH_POLICY=m
 CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
@@ -97,22 +132,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 CONFIG_NETFILTER_XT_MATCH_TIME=m
 CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
 CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
 CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_NF_NAT=m
+CONFIG_NF_NAT_IPV4=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_NF_NAT_SNMP_BASIC=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_TARGET_ECN=m
@@ -122,7 +166,6 @@ CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_AH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
@@ -131,21 +174,34 @@ CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_HL=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
 CONFIG_IP6_NF_RAW=m
+CONFIG_NF_NAT_IPV6=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
 CONFIG_IP_DCCP=m
 # CONFIG_IP_DCCP_CCID3 is not set
+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
+CONFIG_RDS=m
+CONFIG_RDS_TCP=m
+CONFIG_L2TP=m
 CONFIG_ATALK=m
+CONFIG_BATMAN_ADV=m
+CONFIG_BATMAN_ADV_DAT=y
+# CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
+# CONFIG_FW_LOADER_USER_HELPER is not set
 CONFIG_CONNECTOR=m
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_DRBD=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_CDROM_PKTCDVD=m
@@ -160,103 +216,131 @@ CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=m
 CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_SAS_LIBSAS=m
-# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
-CONFIG_SCSI_SRP_ATTRS=m
-CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=m
 CONFIG_ISCSI_TCP=m
+CONFIG_ISCSI_BOOT_SYSFS=m
 CONFIG_MVME16x_SCSI=y
 CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
 CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID456=m
 CONFIG_BLK_DEV_DM=m
 CONFIG_DM_CRYPT=m
 CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_CACHE=m
 CONFIG_DM_MIRROR=m
+CONFIG_DM_RAID=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
 CONFIG_DM_UEVENT=y
+CONFIG_TARGET_CORE=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_PSCSI=m
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
-CONFIG_MACVLAN=m
 CONFIG_EQUALIZER=m
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_VXLAN=m
+CONFIG_NETCONSOLE=m
+CONFIG_NETCONSOLE_DYNAMIC=y
 CONFIG_VETH=m
-CONFIG_NET_ETHERNET=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
 CONFIG_MVME16x_NET=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
 CONFIG_PPP=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
 CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPTP=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_WLAN is not set
+CONFIG_INPUT_EVDEV=m
 # CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_MOUSE_PS2=m
-CONFIG_MOUSE_SERIAL=m
-CONFIG_SERIO=m
-# CONFIG_SERIO_SERPORT is not set
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_SERIO is not set
 CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 # CONFIG_HW_RANDOM is not set
-CONFIG_GEN_RTC=m
-CONFIG_GEN_RTC_X=y
+CONFIG_NTP_PPS=y
+CONFIG_PPS_CLIENT_LDISC=m
+CONFIG_PTP_1588_CLOCK=m
 # CONFIG_HWMON is not set
 CONFIG_HID=m
 CONFIG_HIDRAW=y
+CONFIG_UHID=m
+# CONFIG_HID_GENERIC is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PROC_HARDWARE=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
 CONFIG_REISERFS_FS=m
 CONFIG_JFS_FS=m
 CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
-# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
+CONFIG_FANOTIFY=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
 # CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
 CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
+CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_AFFS_FS=m
+CONFIG_ECRYPT_FS=m
+CONFIG_ECRYPT_FS_MESSAGING=y
 CONFIG_HFS_FS=m
 CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 CONFIG_SQUASHFS=m
-CONFIG_MINIX_FS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_MINIX_FS=m
+CONFIG_OMFS_FS=m
 CONFIG_HPFS_FS=m
+CONFIG_QNX4FS_FS=m
+CONFIG_QNX6FS_FS=m
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V4=y
+CONFIG_NFS_SWAP=y
 CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_CIFS=m
+# CONFIG_CIFS_DEBUG is not set
 CONFIG_CODA_FS=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
@@ -295,10 +379,23 @@ CONFIG_NLS_ISO8859_14=m
 CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_MAC_ROMAN=m
+CONFIG_NLS_MAC_CELTIC=m
+CONFIG_NLS_MAC_CENTEURO=m
+CONFIG_NLS_MAC_CROATIAN=m
+CONFIG_NLS_MAC_CYRILLIC=m
+CONFIG_NLS_MAC_GAELIC=m
+CONFIG_NLS_MAC_GREEK=m
+CONFIG_NLS_MAC_ICELAND=m
+CONFIG_NLS_MAC_INUIT=m
+CONFIG_NLS_MAC_ROMANIAN=m
+CONFIG_NLS_MAC_TURKISH=m
 CONFIG_DLM=m
 CONFIG_MAGIC_SYSRQ=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_ASYNC_RAID6_TEST=m
+CONFIG_ENCRYPTED_KEYS=m
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_USER=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_TEST=m
@@ -308,19 +405,16 @@ CONFIG_CRYPTO_CTS=m
 CONFIG_CRYPTO_LRW=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_VMAC=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_RMD128=m
 CONFIG_CRYPTO_RMD160=m
 CONFIG_CRYPTO_RMD256=m
 CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_TGR192=m
 CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_ANUBIS=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_CAMELLIA=m
@@ -336,6 +430,14 @@ CONFIG_CRYPTO_TWOFISH=m
 CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
 # CONFIG_CRYPTO_HW is not set
-CONFIG_CRC16=m
 CONFIG_CRC_T10DIF=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_TEST=m
diff --git a/arch/m68k/configs/q40_defconfig b/arch/m68k/configs/q40_defconfig
index 19d23db690a4..8982370e8b42 100644
--- a/arch/m68k/configs/q40_defconfig
+++ b/arch/m68k/configs/q40_defconfig
@@ -1,49 +1,74 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_LOCALVERSION="-q40"
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_RELAY=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_Q40=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_AMIGA_PARTITION=y
+CONFIG_ATARI_PARTITION=y
+CONFIG_MAC_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_SUN_PARTITION=y
+# CONFIG_EFI_PARTITION is not set
+CONFIG_SYSV68_PARTITION=y
+CONFIG_IOSCHED_DEADLINE=m
 CONFIG_M68040=y
 CONFIG_M68060=y
+CONFIG_Q40=y
+# CONFIG_COMPACTION is not set
+CONFIG_CLEANCACHE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
-CONFIG_HEARTBEAT=y
-CONFIG_PROC_HARDWARE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=m
 CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=m
+CONFIG_XFRM_MIGRATE=y
 CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
 CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
 CONFIG_NET_IPGRE=m
 CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=m
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=m
+CONFIG_INET_UDP_DIAG=m
 CONFIG_IPV6_PRIVACY=y
 CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_GRE=m
 CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
 CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_ZONES=y
+# CONFIG_NF_CONNTRACK_PROCFS is not set
 # CONFIG_NF_CT_PROTO_DCCP is not set
 CONFIG_NF_CT_PROTO_UDPLITE=m
 CONFIG_NF_CONNTRACK_AMANDA=m
@@ -51,25 +76,37 @@ CONFIG_NF_CONNTRACK_FTP=m
 CONFIG_NF_CONNTRACK_H323=m
 CONFIG_NF_CONNTRACK_IRC=m
 CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
 CONFIG_NF_CONNTRACK_PPTP=m
 CONFIG_NF_CONNTRACK_SANE=m
 CONFIG_NF_CONNTRACK_SIP=m
 CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NETFILTER_XT_SET=m
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
 CONFIG_NETFILTER_XT_TARGET_MARK=m
 CONFIG_NETFILTER_XT_TARGET_NFLOG=m
 CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
 CONFIG_NETFILTER_XT_TARGET_TRACE=m
 CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
 CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
 CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
 CONFIG_NETFILTER_XT_MATCH_COMMENT=m
 CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
 CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
 CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
 CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
 CONFIG_NETFILTER_XT_MATCH_DSCP=m
 CONFIG_NETFILTER_XT_MATCH_ESP=m
 CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
@@ -80,6 +117,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m
 CONFIG_NETFILTER_XT_MATCH_MAC=m
 CONFIG_NETFILTER_XT_MATCH_MARK=m
 CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
 CONFIG_NETFILTER_XT_MATCH_OWNER=m
 CONFIG_NETFILTER_XT_MATCH_POLICY=m
 CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
@@ -93,22 +132,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 CONFIG_NETFILTER_XT_MATCH_TIME=m
 CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
 CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
 CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_NF_NAT=m
+CONFIG_NF_NAT_IPV4=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_NF_NAT_SNMP_BASIC=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_TARGET_ECN=m
@@ -118,7 +166,6 @@ CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_AH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
@@ -127,26 +174,40 @@ CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_HL=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
 CONFIG_IP6_NF_RAW=m
+CONFIG_NF_NAT_IPV6=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
 CONFIG_IP_DCCP=m
 # CONFIG_IP_DCCP_CCID3 is not set
+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
+CONFIG_RDS=m
+CONFIG_RDS_TCP=m
+CONFIG_L2TP=m
 CONFIG_ATALK=m
+CONFIG_BATMAN_ADV=m
+CONFIG_BATMAN_ADV_DAT=y
+# CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
+# CONFIG_FW_LOADER_USER_HELPER is not set
 CONFIG_CONNECTOR=m
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_DRBD=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_CDROM_PKTCDVD=m
 CONFIG_ATA_OVER_ETH=m
 CONFIG_IDE=y
+CONFIG_IDE_GD_ATAPI=y
 CONFIG_BLK_DEV_IDECD=y
 CONFIG_BLK_DEV_Q40IDE=y
 CONFIG_RAID_ATTRS=m
@@ -159,61 +220,82 @@ CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=m
 CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_SAS_LIBSAS=m
-# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
-CONFIG_SCSI_SRP_ATTRS=m
-CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=m
 CONFIG_ISCSI_TCP=m
+CONFIG_ISCSI_BOOT_SYSFS=m
 CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
 CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID456=m
 CONFIG_BLK_DEV_DM=m
 CONFIG_DM_CRYPT=m
 CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_CACHE=m
 CONFIG_DM_MIRROR=m
+CONFIG_DM_RAID=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
 CONFIG_DM_UEVENT=y
+CONFIG_TARGET_CORE=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_PSCSI=m
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
-CONFIG_MACVLAN=m
 CONFIG_EQUALIZER=m
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_VXLAN=m
+CONFIG_NETCONSOLE=m
+CONFIG_NETCONSOLE_DYNAMIC=y
 CONFIG_VETH=m
-CONFIG_NET_ETHERNET=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FUJITSU is not set
+# CONFIG_NET_VENDOR_HP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
 CONFIG_NE2000=m
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
 CONFIG_PPP=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
 CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPTP=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_WLAN is not set
+CONFIG_INPUT_EVDEV=m
 # CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_MOUSE_PS2=m
+# CONFIG_MOUSE_PS2 is not set
 CONFIG_MOUSE_SERIAL=m
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_M68K_BEEP=m
-CONFIG_SERIO=m
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_Q40KBD=m
+CONFIG_SERIO_Q40KBD=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 # CONFIG_HW_RANDOM is not set
-CONFIG_GEN_RTC=m
-CONFIG_GEN_RTC_X=y
+CONFIG_NTP_PPS=y
+CONFIG_PPS_CLIENT_LDISC=m
+CONFIG_PTP_1588_CLOCK=m
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
@@ -222,46 +304,61 @@ CONFIG_SOUND=m
 CONFIG_DMASOUND_Q40=m
 CONFIG_HID=m
 CONFIG_HIDRAW=y
+CONFIG_UHID=m
+# CONFIG_HID_GENERIC is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_HEARTBEAT=y
+CONFIG_PROC_HARDWARE=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
 CONFIG_REISERFS_FS=m
 CONFIG_JFS_FS=m
 CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
-# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
+CONFIG_FANOTIFY=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
 # CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
 CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
+CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_AFFS_FS=m
+CONFIG_ECRYPT_FS=m
+CONFIG_ECRYPT_FS_MESSAGING=y
 CONFIG_HFS_FS=m
 CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 CONFIG_SQUASHFS=m
-CONFIG_MINIX_FS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_MINIX_FS=m
+CONFIG_OMFS_FS=m
 CONFIG_HPFS_FS=m
+CONFIG_QNX4FS_FS=m
+CONFIG_QNX6FS_FS=m
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V4=y
+CONFIG_NFS_SWAP=y
+CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_CIFS=m
+# CONFIG_CIFS_DEBUG is not set
 CONFIG_CODA_FS=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
@@ -300,10 +397,23 @@ CONFIG_NLS_ISO8859_14=m
 CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_MAC_ROMAN=m
+CONFIG_NLS_MAC_CELTIC=m
+CONFIG_NLS_MAC_CENTEURO=m
+CONFIG_NLS_MAC_CROATIAN=m
+CONFIG_NLS_MAC_CYRILLIC=m
+CONFIG_NLS_MAC_GAELIC=m
+CONFIG_NLS_MAC_GREEK=m
+CONFIG_NLS_MAC_ICELAND=m
+CONFIG_NLS_MAC_INUIT=m
+CONFIG_NLS_MAC_ROMANIAN=m
+CONFIG_NLS_MAC_TURKISH=m
 CONFIG_DLM=m
 CONFIG_MAGIC_SYSRQ=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_ASYNC_RAID6_TEST=m
+CONFIG_ENCRYPTED_KEYS=m
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_USER=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_TEST=m
@@ -313,19 +423,16 @@ CONFIG_CRYPTO_CTS=m
 CONFIG_CRYPTO_LRW=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_VMAC=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_RMD128=m
 CONFIG_CRYPTO_RMD160=m
 CONFIG_CRYPTO_RMD256=m
 CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_TGR192=m
 CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_ANUBIS=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_CAMELLIA=m
@@ -341,6 +448,14 @@ CONFIG_CRYPTO_TWOFISH=m
 CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
 # CONFIG_CRYPTO_HW is not set
-CONFIG_CRC16=m
 CONFIG_CRC_T10DIF=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_TEST=m
diff --git a/arch/m68k/configs/sun3_defconfig b/arch/m68k/configs/sun3_defconfig
index ca6c0b4cab77..54674d61e001 100644
--- a/arch/m68k/configs/sun3_defconfig
+++ b/arch/m68k/configs/sun3_defconfig
@@ -1,50 +1,71 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_LOCALVERSION="-sun3"
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_RELAY=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_AMIGA_PARTITION=y
+CONFIG_ATARI_PARTITION=y
+CONFIG_MAC_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+# CONFIG_EFI_PARTITION is not set
+CONFIG_SYSV68_PARTITION=y
+CONFIG_IOSCHED_DEADLINE=m
 CONFIG_SUN3=y
+# CONFIG_COMPACTION is not set
+CONFIG_CLEANCACHE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
-CONFIG_PROC_HARDWARE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=m
 CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=m
+CONFIG_XFRM_MIGRATE=y
 CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 CONFIG_IP_PNP_RARP=y
 CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
 CONFIG_NET_IPGRE=m
 CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=m
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=m
+CONFIG_INET_UDP_DIAG=m
 CONFIG_IPV6_PRIVACY=y
 CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_GRE=m
 CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
 CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_ZONES=y
+# CONFIG_NF_CONNTRACK_PROCFS is not set
 # CONFIG_NF_CT_PROTO_DCCP is not set
 CONFIG_NF_CT_PROTO_UDPLITE=m
 CONFIG_NF_CONNTRACK_AMANDA=m
@@ -52,25 +73,37 @@ CONFIG_NF_CONNTRACK_FTP=m
 CONFIG_NF_CONNTRACK_H323=m
 CONFIG_NF_CONNTRACK_IRC=m
 CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
 CONFIG_NF_CONNTRACK_PPTP=m
 CONFIG_NF_CONNTRACK_SANE=m
 CONFIG_NF_CONNTRACK_SIP=m
 CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NETFILTER_XT_SET=m
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
 CONFIG_NETFILTER_XT_TARGET_MARK=m
 CONFIG_NETFILTER_XT_TARGET_NFLOG=m
 CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
 CONFIG_NETFILTER_XT_TARGET_TRACE=m
 CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
 CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
 CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
 CONFIG_NETFILTER_XT_MATCH_COMMENT=m
 CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
 CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
 CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
 CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
 CONFIG_NETFILTER_XT_MATCH_DSCP=m
 CONFIG_NETFILTER_XT_MATCH_ESP=m
 CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
@@ -81,6 +114,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m
 CONFIG_NETFILTER_XT_MATCH_MAC=m
 CONFIG_NETFILTER_XT_MATCH_MARK=m
 CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
 CONFIG_NETFILTER_XT_MATCH_OWNER=m
 CONFIG_NETFILTER_XT_MATCH_POLICY=m
 CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
@@ -94,22 +129,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 CONFIG_NETFILTER_XT_MATCH_TIME=m
 CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
 CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
 CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_NF_NAT=m
+CONFIG_NF_NAT_IPV4=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_NF_NAT_SNMP_BASIC=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_TARGET_ECN=m
@@ -119,7 +163,6 @@ CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_AH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
@@ -128,21 +171,34 @@ CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_HL=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
 CONFIG_IP6_NF_RAW=m
+CONFIG_NF_NAT_IPV6=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
 CONFIG_IP_DCCP=m
 # CONFIG_IP_DCCP_CCID3 is not set
+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
+CONFIG_RDS=m
+CONFIG_RDS_TCP=m
+CONFIG_L2TP=m
 CONFIG_ATALK=m
+CONFIG_BATMAN_ADV=m
+CONFIG_BATMAN_ADV_DAT=y
+# CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
+# CONFIG_FW_LOADER_USER_HELPER is not set
 CONFIG_CONNECTOR=m
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_DRBD=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_CDROM_PKTCDVD=m
@@ -157,107 +213,136 @@ CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=m
 CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_SAS_LIBSAS=m
-# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
-CONFIG_SCSI_SRP_ATTRS=m
-CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=m
 CONFIG_ISCSI_TCP=m
+CONFIG_ISCSI_BOOT_SYSFS=m
 CONFIG_SUN3_SCSI=y
 CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
 CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID456=m
 CONFIG_BLK_DEV_DM=m
 CONFIG_DM_CRYPT=m
 CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_CACHE=m
 CONFIG_DM_MIRROR=m
+CONFIG_DM_RAID=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
 CONFIG_DM_UEVENT=y
+CONFIG_TARGET_CORE=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_PSCSI=m
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
-CONFIG_MACVLAN=m
 CONFIG_EQUALIZER=m
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_VXLAN=m
+CONFIG_NETCONSOLE=m
+CONFIG_NETCONSOLE_DYNAMIC=y
 CONFIG_VETH=m
-CONFIG_NET_ETHERNET=y
 CONFIG_SUN3LANCE=y
+# CONFIG_NET_CADENCE is not set
 CONFIG_SUN3_82586=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
 CONFIG_PPP=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
 CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPTP=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_WLAN is not set
+CONFIG_INPUT_EVDEV=m
 # CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_SUNKBD=y
-CONFIG_MOUSE_PS2=m
+# CONFIG_MOUSE_PS2 is not set
 CONFIG_MOUSE_SERIAL=m
-# CONFIG_SERIO_SERPORT is not set
 CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 # CONFIG_HW_RANDOM is not set
-CONFIG_GEN_RTC=m
-CONFIG_GEN_RTC_X=y
+CONFIG_NTP_PPS=y
+CONFIG_PPS_CLIENT_LDISC=m
+CONFIG_PTP_1588_CLOCK=m
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
 CONFIG_HID=m
 CONFIG_HIDRAW=y
+CONFIG_UHID=m
+# CONFIG_HID_GENERIC is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PROC_HARDWARE=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
 CONFIG_REISERFS_FS=m
 CONFIG_JFS_FS=m
 CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
-# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
+CONFIG_FANOTIFY=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
 # CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
 CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
+CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_AFFS_FS=m
+CONFIG_ECRYPT_FS=m
+CONFIG_ECRYPT_FS_MESSAGING=y
 CONFIG_HFS_FS=m
 CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 CONFIG_SQUASHFS=m
-CONFIG_MINIX_FS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_MINIX_FS=m
+CONFIG_OMFS_FS=m
 CONFIG_HPFS_FS=m
+CONFIG_QNX4FS_FS=m
+CONFIG_QNX6FS_FS=m
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V4=y
+CONFIG_NFS_SWAP=y
 CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_CIFS=m
+# CONFIG_CIFS_DEBUG is not set
 CONFIG_CODA_FS=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
@@ -296,10 +381,23 @@ CONFIG_NLS_ISO8859_14=m
 CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_MAC_ROMAN=m
+CONFIG_NLS_MAC_CELTIC=m
+CONFIG_NLS_MAC_CENTEURO=m
+CONFIG_NLS_MAC_CROATIAN=m
+CONFIG_NLS_MAC_CYRILLIC=m
+CONFIG_NLS_MAC_GAELIC=m
+CONFIG_NLS_MAC_GREEK=m
+CONFIG_NLS_MAC_ICELAND=m
+CONFIG_NLS_MAC_INUIT=m
+CONFIG_NLS_MAC_ROMANIAN=m
+CONFIG_NLS_MAC_TURKISH=m
 CONFIG_DLM=m
 CONFIG_MAGIC_SYSRQ=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_ASYNC_RAID6_TEST=m
+CONFIG_ENCRYPTED_KEYS=m
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_USER=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_TEST=m
@@ -309,19 +407,16 @@ CONFIG_CRYPTO_CTS=m
 CONFIG_CRYPTO_LRW=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_VMAC=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_RMD128=m
 CONFIG_CRYPTO_RMD160=m
 CONFIG_CRYPTO_RMD256=m
 CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_TGR192=m
 CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_ANUBIS=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_CAMELLIA=m
@@ -337,6 +432,14 @@ CONFIG_CRYPTO_TWOFISH=m
 CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
 # CONFIG_CRYPTO_HW is not set
-CONFIG_CRC16=m
 CONFIG_CRC_T10DIF=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_TEST=m
diff --git a/arch/m68k/configs/sun3x_defconfig b/arch/m68k/configs/sun3x_defconfig
index c80941c7759e..832d9539f441 100644
--- a/arch/m68k/configs/sun3x_defconfig
+++ b/arch/m68k/configs/sun3x_defconfig
@@ -1,50 +1,71 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_LOCALVERSION="-sun3x"
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
 CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_RELAY=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_AMIGA_PARTITION=y
+CONFIG_ATARI_PARTITION=y
+CONFIG_MAC_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+# CONFIG_EFI_PARTITION is not set
+CONFIG_SYSV68_PARTITION=y
+CONFIG_IOSCHED_DEADLINE=m
 CONFIG_SUN3X=y
+# CONFIG_COMPACTION is not set
+CONFIG_CLEANCACHE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_AOUT=m
 CONFIG_BINFMT_MISC=m
-CONFIG_PROC_HARDWARE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=m
 CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=m
+CONFIG_XFRM_MIGRATE=y
 CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 CONFIG_IP_PNP_RARP=y
 CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
 CONFIG_NET_IPGRE=m
 CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=m
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
 CONFIG_INET_XFRM_MODE_TRANSPORT=m
 CONFIG_INET_XFRM_MODE_TUNNEL=m
 CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=m
+CONFIG_INET_UDP_DIAG=m
 CONFIG_IPV6_PRIVACY=y
 CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
 CONFIG_INET6_AH=m
 CONFIG_INET6_ESP=m
 CONFIG_INET6_IPCOMP=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_GRE=m
 CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
 CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_ZONES=y
+# CONFIG_NF_CONNTRACK_PROCFS is not set
 # CONFIG_NF_CT_PROTO_DCCP is not set
 CONFIG_NF_CT_PROTO_UDPLITE=m
 CONFIG_NF_CONNTRACK_AMANDA=m
@@ -52,25 +73,37 @@ CONFIG_NF_CONNTRACK_FTP=m
 CONFIG_NF_CONNTRACK_H323=m
 CONFIG_NF_CONNTRACK_IRC=m
 CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
 CONFIG_NF_CONNTRACK_PPTP=m
 CONFIG_NF_CONNTRACK_SANE=m
 CONFIG_NF_CONNTRACK_SIP=m
 CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NETFILTER_XT_SET=m
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
 CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
 CONFIG_NETFILTER_XT_TARGET_MARK=m
 CONFIG_NETFILTER_XT_TARGET_NFLOG=m
 CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
 CONFIG_NETFILTER_XT_TARGET_TRACE=m
 CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
 CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
 CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
 CONFIG_NETFILTER_XT_MATCH_COMMENT=m
 CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
 CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
 CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
 CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
 CONFIG_NETFILTER_XT_MATCH_DSCP=m
 CONFIG_NETFILTER_XT_MATCH_ESP=m
 CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
@@ -81,6 +114,8 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=m
 CONFIG_NETFILTER_XT_MATCH_MAC=m
 CONFIG_NETFILTER_XT_MATCH_MARK=m
 CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
 CONFIG_NETFILTER_XT_MATCH_OWNER=m
 CONFIG_NETFILTER_XT_MATCH_POLICY=m
 CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
@@ -94,22 +129,31 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m
 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 CONFIG_NETFILTER_XT_MATCH_TIME=m
 CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
 CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
 CONFIG_IP_NF_MATCH_TTL=m
 CONFIG_IP_NF_FILTER=m
 CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
 CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_NF_NAT=m
+CONFIG_NF_NAT_IPV4=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_NF_NAT_SNMP_BASIC=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_TARGET_ECN=m
@@ -119,7 +163,6 @@ CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
 CONFIG_IP6_NF_IPTABLES=m
 CONFIG_IP6_NF_MATCH_AH=m
 CONFIG_IP6_NF_MATCH_EUI64=m
@@ -128,21 +171,34 @@ CONFIG_IP6_NF_MATCH_OPTS=m
 CONFIG_IP6_NF_MATCH_HL=m
 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
 CONFIG_IP6_NF_MATCH_RT=m
 CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
 CONFIG_IP6_NF_FILTER=m
 CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
 CONFIG_IP6_NF_RAW=m
+CONFIG_NF_NAT_IPV6=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
 CONFIG_IP_DCCP=m
 # CONFIG_IP_DCCP_CCID3 is not set
+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
+CONFIG_RDS=m
+CONFIG_RDS_TCP=m
+CONFIG_L2TP=m
 CONFIG_ATALK=m
+CONFIG_BATMAN_ADV=m
+CONFIG_BATMAN_ADV_DAT=y
+# CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
+# CONFIG_FW_LOADER_USER_HELPER is not set
 CONFIG_CONNECTOR=m
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_DRBD=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_CDROM_PKTCDVD=m
@@ -157,106 +213,136 @@ CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=m
 CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_SAS_LIBSAS=m
-# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
-CONFIG_SCSI_SRP_ATTRS=m
-CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_SCSI_SAS_ATTRS=m
 CONFIG_ISCSI_TCP=m
+CONFIG_ISCSI_BOOT_SYSFS=m
 CONFIG_SUN3X_ESP=y
 CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
 CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID456=m
 CONFIG_BLK_DEV_DM=m
 CONFIG_DM_CRYPT=m
 CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_CACHE=m
 CONFIG_DM_MIRROR=m
+CONFIG_DM_RAID=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
 CONFIG_DM_UEVENT=y
+CONFIG_TARGET_CORE=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_PSCSI=m
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
-CONFIG_MACVLAN=m
 CONFIG_EQUALIZER=m
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_VXLAN=m
+CONFIG_NETCONSOLE=m
+CONFIG_NETCONSOLE_DYNAMIC=y
 CONFIG_VETH=m
-CONFIG_NET_ETHERNET=y
 CONFIG_SUN3LANCE=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
 CONFIG_PPP=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
 CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
+CONFIG_PPTP=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
 CONFIG_SLIP=m
 CONFIG_SLIP_COMPRESSED=y
 CONFIG_SLIP_SMART=y
 CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_INPUT_FF_MEMLESS=m
+# CONFIG_WLAN is not set
+CONFIG_INPUT_EVDEV=m
 # CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_SUNKBD=y
-CONFIG_MOUSE_PS2=m
+# CONFIG_MOUSE_PS2 is not set
 CONFIG_MOUSE_SERIAL=m
-# CONFIG_SERIO_SERPORT is not set
 CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 # CONFIG_HW_RANDOM is not set
-CONFIG_GEN_RTC=m
-CONFIG_GEN_RTC_X=y
+CONFIG_NTP_PPS=y
+CONFIG_PPS_CLIENT_LDISC=m
+CONFIG_PTP_1588_CLOCK=m
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
 CONFIG_HID=m
 CONFIG_HIDRAW=y
+CONFIG_UHID=m
+# CONFIG_HID_GENERIC is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PROC_HARDWARE=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 # CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
 CONFIG_REISERFS_FS=m
 CONFIG_JFS_FS=m
 CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
-# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
+CONFIG_FANOTIFY=y
 CONFIG_QUOTA_NETLINK_INTERFACE=y
 # CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
 CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
+CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_AFFS_FS=m
+CONFIG_ECRYPT_FS=m
+CONFIG_ECRYPT_FS_MESSAGING=y
 CONFIG_HFS_FS=m
 CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 CONFIG_SQUASHFS=m
-CONFIG_MINIX_FS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_MINIX_FS=m
+CONFIG_OMFS_FS=m
 CONFIG_HPFS_FS=m
+CONFIG_QNX4FS_FS=m
+CONFIG_QNX6FS_FS=m
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V4=y
+CONFIG_NFS_SWAP=y
 CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_CIFS=m
+# CONFIG_CIFS_DEBUG is not set
 CONFIG_CODA_FS=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
@@ -295,10 +381,23 @@ CONFIG_NLS_ISO8859_14=m
 CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_MAC_ROMAN=m
+CONFIG_NLS_MAC_CELTIC=m
+CONFIG_NLS_MAC_CENTEURO=m
+CONFIG_NLS_MAC_CROATIAN=m
+CONFIG_NLS_MAC_CYRILLIC=m
+CONFIG_NLS_MAC_GAELIC=m
+CONFIG_NLS_MAC_GREEK=m
+CONFIG_NLS_MAC_ICELAND=m
+CONFIG_NLS_MAC_INUIT=m
+CONFIG_NLS_MAC_ROMANIAN=m
+CONFIG_NLS_MAC_TURKISH=m
 CONFIG_DLM=m
 CONFIG_MAGIC_SYSRQ=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_ASYNC_RAID6_TEST=m
+CONFIG_ENCRYPTED_KEYS=m
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_USER=m
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_TEST=m
@@ -308,19 +407,16 @@ CONFIG_CRYPTO_CTS=m
 CONFIG_CRYPTO_LRW=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_VMAC=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_RMD128=m
 CONFIG_CRYPTO_RMD160=m
 CONFIG_CRYPTO_RMD256=m
 CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
 CONFIG_CRYPTO_TGR192=m
 CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_AES=m
 CONFIG_CRYPTO_ANUBIS=m
 CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_CAMELLIA=m
@@ -336,6 +432,14 @@ CONFIG_CRYPTO_TWOFISH=m
 CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
 # CONFIG_CRYPTO_HW is not set
-CONFIG_CRC16=m
 CONFIG_CRC_T10DIF=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_TEST=m
diff --git a/arch/m68k/include/asm/Kbuild b/arch/m68k/include/asm/Kbuild
index c7933e41f10d..09d77a862da3 100644
--- a/arch/m68k/include/asm/Kbuild
+++ b/arch/m68k/include/asm/Kbuild
@@ -6,7 +6,6 @@ generic-y += device.h
 generic-y += emergency-restart.h
 generic-y += errno.h
 generic-y += exec.h
-generic-y += futex.h
 generic-y += hw_irq.h
 generic-y += ioctl.h
 generic-y += ipcbuf.h
diff --git a/arch/m68k/include/asm/futex.h b/arch/m68k/include/asm/futex.h
new file mode 100644
index 000000000000..bc868af10c96
--- /dev/null
+++ b/arch/m68k/include/asm/futex.h
@@ -0,0 +1,94 @@
+#ifndef _ASM_M68K_FUTEX_H
+#define _ASM_M68K_FUTEX_H
+
+#ifdef __KERNEL__
+#if !defined(CONFIG_MMU)
+#include <asm-generic/futex.h>
+#else   /* CONFIG_MMU */
+
+#include <linux/futex.h>
+#include <linux/uaccess.h>
+#include <asm/errno.h>
+
+static inline int
+futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
+                              u32 oldval, u32 newval)
+{
+        u32 val;
+
+        if (unlikely(get_user(val, uaddr) != 0))
+                return -EFAULT;
+
+        if (val == oldval && unlikely(put_user(newval, uaddr) != 0))
+                return -EFAULT;
+
+        *uval = val;
+
+        return 0;
+}
+
+static inline int
+futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval, ret;
+        u32 tmp;
+
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        pagefault_disable();    /* implies preempt_disable() */
+
+        ret = -EFAULT;
+        if (unlikely(get_user(oldval, uaddr) != 0))
+                goto out_pagefault_enable;
+
+        ret = 0;
+        tmp = oldval;
+
+        switch (op) {
+        case FUTEX_OP_SET:
+                tmp = oparg;
+                break;
+        case FUTEX_OP_ADD:
+                tmp += oparg;
+                break;
+        case FUTEX_OP_OR:
+                tmp |= oparg;
+                break;
+        case FUTEX_OP_ANDN:
+                tmp &= ~oparg;
+                break;
+        case FUTEX_OP_XOR:
+                tmp ^= oparg;
+                break;
+        default:
+                ret = -ENOSYS;
+        }
+
+        if (ret == 0 && unlikely(put_user(tmp, uaddr) != 0))
+                ret = -EFAULT;
+
+out_pagefault_enable:
+        pagefault_enable();     /* subsumes preempt_enable() */
+
+        if (ret == 0) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif /* CONFIG_MMU */
+#endif /* __KERNEL__ */
+#endif /* _ASM_M68K_FUTEX_H */
diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h
index 8cc83431805b..2f6eec1e34b4 100644
--- a/arch/m68k/include/asm/gpio.h
+++ b/arch/m68k/include/asm/gpio.h
@@ -86,6 +86,7 @@ static inline int gpio_cansleep(unsigned gpio)
         return gpio < MCFGPIO_PIN_MAX ? 0 : __gpio_cansleep(gpio);
 }
 
+#ifndef CONFIG_GPIOLIB
 static inline int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
 {
         int err;
@@ -105,5 +106,5 @@ static inline int gpio_request_one(unsigned gpio, unsigned long flags, const cha
 
         return err;
 }
-
+#endif /* !CONFIG_GPIOLIB */
 #endif
diff --git a/arch/m68k/kernel/head.S b/arch/m68k/kernel/head.S
index d197e7ff62c5..ac85f16534af 100644
--- a/arch/m68k/kernel/head.S
+++ b/arch/m68k/kernel/head.S
@@ -2752,11 +2752,9 @@ func_return	get_new_page
 #ifdef CONFIG_MAC
 
 L(scc_initable_mac):
-        .byte   9,12            /* Reset */
         .byte   4,0x44          /* x16, 1 stopbit, no parity */
         .byte   3,0xc0          /* receiver: 8 bpc */
         .byte   5,0xe2          /* transmitter: 8 bpc, assert dtr/rts */
-        .byte   9,0             /* no interrupts */
         .byte   10,0            /* NRZ */
         .byte   11,0x50         /* use baud rate generator */
         .byte   12,1,13,0       /* 38400 baud */
@@ -2899,6 +2897,7 @@ func_start	serial_init,%d0/%d1/%a0/%a1
         is_not_mac(L(serial_init_not_mac))
 
 #ifdef SERIAL_DEBUG
+
 /* You may define either or both of these. */
 #define MAC_USE_SCC_A /* Modem port */
 #define MAC_USE_SCC_B /* Printer port */
@@ -2908,9 +2907,21 @@ func_start	serial_init,%d0/%d1/%a0/%a1
 #define mac_scc_cha_b_data_offset       0x4
 #define mac_scc_cha_a_data_offset       0x6
 
+#if defined(MAC_USE_SCC_A) || defined(MAC_USE_SCC_B)
+        movel   %pc@(L(mac_sccbase)),%a0
+        /* Reset SCC device */
+        moveb   #9,%a0@(mac_scc_cha_a_ctrl_offset)
+        moveb   #0xc0,%a0@(mac_scc_cha_a_ctrl_offset)
+        /* Wait for 5 PCLK cycles, which is about 68 CPU cycles */
+        /* 5 / 3.6864 MHz = approx. 1.36 us = 68 / 50 MHz */
+        movel   #35,%d0
+5:
+        subq    #1,%d0
+        jne     5b
+#endif
+
 #ifdef MAC_USE_SCC_A
         /* Initialize channel A */
-        movel   %pc@(L(mac_sccbase)),%a0
         lea     %pc@(L(scc_initable_mac)),%a1
 5:      moveb   %a1@+,%d0
         jmi     6f
@@ -2922,9 +2933,6 @@ func_start	serial_init,%d0/%d1/%a0/%a1
 
 #ifdef MAC_USE_SCC_B
         /* Initialize channel B */
-#ifndef MAC_USE_SCC_A   /* Load mac_sccbase only if needed */
-        movel   %pc@(L(mac_sccbase)),%a0
-#endif  /* MAC_USE_SCC_A */
         lea     %pc@(L(scc_initable_mac)),%a1
 7:      moveb   %a1@+,%d0
         jmi     8f
@@ -2933,6 +2941,7 @@ func_start	serial_init,%d0/%d1/%a0/%a1
         jra     7b
 8:
 #endif  /* MAC_USE_SCC_B */
+
 #endif  /* SERIAL_DEBUG */
 
         jra     L(serial_init_done)
@@ -3006,17 +3015,17 @@ func_start	serial_putc,%d0/%d1/%a0/%a1
 
 #ifdef SERIAL_DEBUG
 
-#ifdef MAC_USE_SCC_A
+#if defined(MAC_USE_SCC_A) || defined(MAC_USE_SCC_B)
         movel   %pc@(L(mac_sccbase)),%a1
+#endif
+
+#ifdef MAC_USE_SCC_A
 3:      btst    #2,%a1@(mac_scc_cha_a_ctrl_offset)
         jeq     3b
         moveb   %d0,%a1@(mac_scc_cha_a_data_offset)
 #endif  /* MAC_USE_SCC_A */
 
 #ifdef MAC_USE_SCC_B
-#ifndef MAC_USE_SCC_A   /* Load mac_sccbase only if needed */
-        movel   %pc@(L(mac_sccbase)),%a1
-#endif  /* MAC_USE_SCC_A */
 4:      btst    #2,%a1@(mac_scc_cha_b_ctrl_offset)
         jeq     4b
         moveb   %d0,%a1@(mac_scc_cha_b_data_offset)
diff --git a/arch/microblaze/include/asm/cacheflush.h b/arch/microblaze/include/asm/cacheflush.h
index 0f553bc009a0..ffea82a16d2c 100644
--- a/arch/microblaze/include/asm/cacheflush.h
+++ b/arch/microblaze/include/asm/cacheflush.h
@@ -102,21 +102,23 @@ do { \
 
 #define flush_cache_range(vma, start, len) do { } while (0)
 
-#define copy_to_user_page(vma, page, vaddr, dst, src, len)              \
-do {                                                                    \
-        u32 addr = virt_to_phys(dst);                                   \
-        memcpy((dst), (src), (len));                                    \
-        if (vma->vm_flags & VM_EXEC) {                                  \
-                invalidate_icache_range((unsigned) (addr),              \
-                                        (unsigned) (addr) + PAGE_SIZE); \
-                flush_dcache_range((unsigned) (addr),                   \
-                                        (unsigned) (addr) + PAGE_SIZE); \
-        }                                                               \
-} while (0)
-
-#define copy_from_user_page(vma, page, vaddr, dst, src, len)            \
-do {                                                                    \
-        memcpy((dst), (src), (len));                                    \
-} while (0)
+static inline void copy_to_user_page(struct vm_area_struct *vma,
+                                     struct page *page, unsigned long vaddr,
+                                     void *dst, void *src, int len)
+{
+        u32 addr = virt_to_phys(dst);
+        memcpy(dst, src, len);
+        if (vma->vm_flags & VM_EXEC) {
+                invalidate_icache_range(addr, addr + PAGE_SIZE);
+                flush_dcache_range(addr, addr + PAGE_SIZE);
+        }
+}
+
+static inline void copy_from_user_page(struct vm_area_struct *vma,
+                                       struct page *page, unsigned long vaddr,
+                                       void *dst, void *src, int len)
+{
+        memcpy(dst, src, len);
+}
 
 #endif /* _ASM_MICROBLAZE_CACHEFLUSH_H */
diff --git a/arch/microblaze/include/asm/futex.h b/arch/microblaze/include/asm/futex.h
index ff8cde159d9a..01848f056f43 100644
--- a/arch/microblaze/include/asm/futex.h
+++ b/arch/microblaze/include/asm/futex.h
@@ -105,7 +105,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
 
         __asm__ __volatile__ ("1:       lwx     %1, %3, r0;             \
                                         cmp     %2, %1, %4;             \
-                                        beqi    %2, 3f;                 \
+                                        bnei    %2, 3f;                 \
                                 2:      swx     %5, %3, r0;             \
                                         addic   %2, r0, 0;              \
                                         bnei    %2, 1b;                 \
diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h
index 8cb8a8566ede..2565cb94f32f 100644
--- a/arch/microblaze/include/asm/io.h
+++ b/arch/microblaze/include/asm/io.h
@@ -123,11 +123,11 @@ static inline void writel(unsigned int v, volatile void __iomem *addr)
  * inb_p/inw_p/...
  * The macros don't do byte-swapping.
  */
-#define inb(port)               readb((u8 *)((port)))
+#define inb(port)               readb((u8 *)((unsigned long)(port)))
 #define outb(val, port)         writeb((val), (u8 *)((unsigned long)(port)))
-#define inw(port)               readw((u16 *)((port)))
+#define inw(port)               readw((u16 *)((unsigned long)(port)))
 #define outw(val, port)         writew((val), (u16 *)((unsigned long)(port)))
-#define inl(port)               readl((u32 *)((port)))
+#define inl(port)               readl((u32 *)((unsigned long)(port)))
 #define outl(val, port)         writel((val), (u32 *)((unsigned long)(port)))
 
 #define inb_p(port)             inb((port))
diff --git a/arch/microblaze/include/asm/uaccess.h b/arch/microblaze/include/asm/uaccess.h
index efe59d881789..04e49553bdf9 100644
--- a/arch/microblaze/include/asm/uaccess.h
+++ b/arch/microblaze/include/asm/uaccess.h
@@ -99,13 +99,13 @@ static inline int access_ok(int type, const void __user *addr,
         if ((get_fs().seg < ((unsigned long)addr)) ||
                         (get_fs().seg < ((unsigned long)addr + size - 1))) {
                 pr_debug("ACCESS fail: %s at 0x%08x (size 0x%x), seg 0x%08x\n",
-                        type ? "WRITE" : "READ ", (u32)addr, (u32)size,
+                        type ? "WRITE" : "READ ", (__force u32)addr, (u32)size,
                         (u32)get_fs().seg);
                 return 0;
         }
 ok:
         pr_debug("ACCESS OK: %s at 0x%08x (size 0x%x), seg 0x%08x\n",
-                        type ? "WRITE" : "READ ", (u32)addr, (u32)size,
+                        type ? "WRITE" : "READ ", (__force u32)addr, (u32)size,
                         (u32)get_fs().seg);
         return 1;
 }
diff --git a/arch/microblaze/kernel/cpu/cache.c b/arch/microblaze/kernel/cpu/cache.c
index 4254514b4c8c..a6e44410672d 100644
--- a/arch/microblaze/kernel/cpu/cache.c
+++ b/arch/microblaze/kernel/cpu/cache.c
@@ -140,7 +140,7 @@ do {									\
 /* It is used only first parameter for OP - for wic, wdc */
 #define CACHE_RANGE_LOOP_1(start, end, line_length, op)                 \
 do {                                                                    \
-        int volatile temp;                                              \
+        int volatile temp = 0;                                          \
         int align = ~(line_length - 1);                                 \
         end = ((end & align) == end) ? end - line_length : end & align; \
         WARN_ON(end - start < 0);                                       \
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index b0baa299f899..01b1b3f94feb 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -428,13 +428,16 @@ static void octeon_restart(char *command)
  */
 static void octeon_kill_core(void *arg)
 {
-        mb();
-        if (octeon_is_simulation()) {
-                /* The simulator needs the watchdog to stop for dead cores */
-                cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
+        if (octeon_is_simulation())
                 /* A break instruction causes the simulator stop a core */
-                asm volatile ("sync\nbreak");
-        }
+                asm volatile ("break" ::: "memory");
+
+        local_irq_disable();
+        /* Disable watchdog on this core. */
+        cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
+        /* Spin in a low power mode. */
+        while (true)
+                asm volatile ("wait" ::: "memory");
 }
 
 
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 143875c6c95a..4d6fa0bf1305 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -496,10 +496,6 @@ struct kvm_mips_callbacks {
                             uint32_t cause);
         int (*irq_clear) (struct kvm_vcpu *vcpu, unsigned int priority,
                           uint32_t cause);
-        int (*vcpu_ioctl_get_regs) (struct kvm_vcpu *vcpu,
-                                    struct kvm_regs *regs);
-        int (*vcpu_ioctl_set_regs) (struct kvm_vcpu *vcpu,
-                                    struct kvm_regs *regs);
 };
 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 820116067c10..516e6e9a5594 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -117,7 +117,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
         if (! ((asid += ASID_INC) & ASID_MASK) ) {
                 if (cpu_has_vtag_icache)
                         flush_icache_all();
-#ifdef CONFIG_VIRTUALIZATION
+#ifdef CONFIG_KVM
                 kvm_local_flush_tlb_all();      /* start new asid cycle */
 #else
                 local_flush_tlb_all();  /* start new asid cycle */
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index a3186f2bb8a0..5e6cd0947393 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -16,6 +16,38 @@
 #include <asm/isadep.h>
 #include <uapi/asm/ptrace.h>
 
+/*
+ * This struct defines the way the registers are stored on the stack during a
+ * system call/exception. As usual the registers k0/k1 aren't being saved.
+ */
+struct pt_regs {
+#ifdef CONFIG_32BIT
+        /* Pad bytes for argument save space on the stack. */
+        unsigned long pad0[6];
+#endif
+
+        /* Saved main processor registers. */
+        unsigned long regs[32];
+
+        /* Saved special registers. */
+        unsigned long cp0_status;
+        unsigned long hi;
+        unsigned long lo;
+#ifdef CONFIG_CPU_HAS_SMARTMIPS
+        unsigned long acx;
+#endif
+        unsigned long cp0_badvaddr;
+        unsigned long cp0_cause;
+        unsigned long cp0_epc;
+#ifdef CONFIG_MIPS_MT_SMTC
+        unsigned long cp0_tcstatus;
+#endif /* CONFIG_MIPS_MT_SMTC */
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+        unsigned long long mpl[3];        /* MTM{0,1,2} */
+        unsigned long long mtp[3];        /* MTP{0,1,2} */
+#endif
+} __aligned(8);
+
 struct task_struct;
 
 extern int ptrace_getregs(struct task_struct *child, __s64 __user *data);
diff --git a/arch/mips/include/uapi/asm/kvm.h b/arch/mips/include/uapi/asm/kvm.h
index 85789eacbf18..f09ff5ae2059 100644
--- a/arch/mips/include/uapi/asm/kvm.h
+++ b/arch/mips/include/uapi/asm/kvm.h
@@ -1,55 +1,135 @@
 /*
-* This file is subject to the terms and conditions of the GNU General Public
-* License.  See the file "COPYING" in the main directory of this archive
-* for more details.
-*
-* Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
-* Authors: Sanjay Lal <sanjayl@kymasys.com>
-*/
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2013 Cavium, Inc.
+ * Authors: Sanjay Lal <sanjayl@kymasys.com>
+ */
 
 #ifndef __LINUX_KVM_MIPS_H
 #define __LINUX_KVM_MIPS_H
 
 #include <linux/types.h>
 
-#define __KVM_MIPS
-
-#define N_MIPS_COPROC_REGS      32
-#define N_MIPS_COPROC_SEL       8
+/*
+ * KVM MIPS specific structures and definitions.
+ *
+ * Some parts derived from the x86 version of this file.
+ */
 
-/* for KVM_GET_REGS and KVM_SET_REGS */
+/*
+ * for KVM_GET_REGS and KVM_SET_REGS
+ *
+ * If Config[AT] is zero (32-bit CPU), the register contents are
+ * stored in the lower 32-bits of the struct kvm_regs fields and sign
+ * extended to 64-bits.
+ */
 struct kvm_regs {
-        __u32 gprs[32];
-        __u32 hi;
-        __u32 lo;
-        __u32 pc;
-
-        __u32 cp0reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
-};
-
-/* for KVM_GET_SREGS and KVM_SET_SREGS */
-struct kvm_sregs {
+        /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
+        __u64 gpr[32];
+        __u64 hi;
+        __u64 lo;
+        __u64 pc;
 };
 
-/* for KVM_GET_FPU and KVM_SET_FPU */
+/*
+ * for KVM_GET_FPU and KVM_SET_FPU
+ *
+ * If Status[FR] is zero (32-bit FPU), the upper 32-bits of the FPRs
+ * are zero filled.
+ */
 struct kvm_fpu {
+        __u64 fpr[32];
+        __u32 fir;
+        __u32 fccr;
+        __u32 fexr;
+        __u32 fenr;
+        __u32 fcsr;
+        __u32 pad;
 };
 
+
+/*
+ * For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access CP0
+ * registers.  The id field is broken down as follows:
+ *
+ *  bits[2..0]   - Register 'sel' index.
+ *  bits[7..3]   - Register 'rd'  index.
+ *  bits[15..8]  - Must be zero.
+ *  bits[31..16] - 1 -> CP0 registers.
+ *  bits[51..32] - Must be zero.
+ *  bits[63..52] - As per linux/kvm.h
+ *
+ * Other sets registers may be added in the future.  Each set would
+ * have its own identifier in bits[31..16].
+ *
+ * The registers defined in struct kvm_regs are also accessible, the
+ * id values for these are below.
+ */
+
+#define KVM_REG_MIPS_R0 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0)
+#define KVM_REG_MIPS_R1 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 1)
+#define KVM_REG_MIPS_R2 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 2)
+#define KVM_REG_MIPS_R3 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 3)
+#define KVM_REG_MIPS_R4 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 4)
+#define KVM_REG_MIPS_R5 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 5)
+#define KVM_REG_MIPS_R6 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 6)
+#define KVM_REG_MIPS_R7 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 7)
+#define KVM_REG_MIPS_R8 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 8)
+#define KVM_REG_MIPS_R9 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 9)
+#define KVM_REG_MIPS_R10 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 10)
+#define KVM_REG_MIPS_R11 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 11)
+#define KVM_REG_MIPS_R12 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 12)
+#define KVM_REG_MIPS_R13 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 13)
+#define KVM_REG_MIPS_R14 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 14)
+#define KVM_REG_MIPS_R15 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 15)
+#define KVM_REG_MIPS_R16 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 16)
+#define KVM_REG_MIPS_R17 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 17)
+#define KVM_REG_MIPS_R18 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 18)
+#define KVM_REG_MIPS_R19 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 19)
+#define KVM_REG_MIPS_R20 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 20)
+#define KVM_REG_MIPS_R21 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 21)
+#define KVM_REG_MIPS_R22 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 22)
+#define KVM_REG_MIPS_R23 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 23)
+#define KVM_REG_MIPS_R24 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 24)
+#define KVM_REG_MIPS_R25 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 25)
+#define KVM_REG_MIPS_R26 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 26)
+#define KVM_REG_MIPS_R27 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 27)
+#define KVM_REG_MIPS_R28 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 28)
+#define KVM_REG_MIPS_R29 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 29)
+#define KVM_REG_MIPS_R30 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 30)
+#define KVM_REG_MIPS_R31 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 31)
+
+#define KVM_REG_MIPS_HI (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 32)
+#define KVM_REG_MIPS_LO (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 33)
+#define KVM_REG_MIPS_PC (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 34)
+
+/*
+ * KVM MIPS specific structures and definitions
+ *
+ */
 struct kvm_debug_exit_arch {
+        __u64 epc;
 };
 
 /* for KVM_SET_GUEST_DEBUG */
 struct kvm_guest_debug_arch {
 };
 
+/* definition of registers in kvm_run */
+struct kvm_sync_regs {
+};
+
+/* dummy definition */
+struct kvm_sregs {
+};
+
 struct kvm_mips_interrupt {
         /* in */
         __u32 cpu;
         __u32 irq;
 };
 
-/* definition of registers in kvm_run */
-struct kvm_sync_regs {
-};
-
 #endif /* __LINUX_KVM_MIPS_H */
diff --git a/arch/mips/include/uapi/asm/ptrace.h b/arch/mips/include/uapi/asm/ptrace.h
index 4d58d8468705..b26f7e317279 100644
--- a/arch/mips/include/uapi/asm/ptrace.h
+++ b/arch/mips/include/uapi/asm/ptrace.h
@@ -22,16 +22,12 @@
 #define DSP_CONTROL     77
 #define ACX             78
 
+#ifndef __KERNEL__
 /*
  * This struct defines the way the registers are stored on the stack during a
  * system call/exception. As usual the registers k0/k1 aren't being saved.
  */
 struct pt_regs {
-#ifdef CONFIG_32BIT
-        /* Pad bytes for argument save space on the stack. */
-        unsigned long pad0[6];
-#endif
-
         /* Saved main processor registers. */
         unsigned long regs[32];
 
@@ -39,20 +35,11 @@ struct pt_regs {
         unsigned long cp0_status;
         unsigned long hi;
         unsigned long lo;
-#ifdef CONFIG_CPU_HAS_SMARTMIPS
-        unsigned long acx;
-#endif
         unsigned long cp0_badvaddr;
         unsigned long cp0_cause;
         unsigned long cp0_epc;
-#ifdef CONFIG_MIPS_MT_SMTC
-        unsigned long cp0_tcstatus;
-#endif /* CONFIG_MIPS_MT_SMTC */
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
-        unsigned long long mpl[3];        /* MTM{0,1,2} */
-        unsigned long long mtp[3];        /* MTP{0,1,2} */
-#endif
 } __attribute__ ((aligned (8)));
+#endif /* __KERNEL__ */
 
 /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
 #define PTRACE_GETREGS          12
diff --git a/arch/mips/kernel/binfmt_elfn32.c b/arch/mips/kernel/binfmt_elfn32.c
index e06f777e9c49..1188e00bb120 100644
--- a/arch/mips/kernel/binfmt_elfn32.c
+++ b/arch/mips/kernel/binfmt_elfn32.c
@@ -119,4 +119,15 @@ MODULE_AUTHOR("Ralf Baechle (ralf@linux-mips.org)");
 #undef TASK_SIZE
 #define TASK_SIZE TASK_SIZE32
 
+#undef cputime_to_timeval
+#define cputime_to_timeval cputime_to_compat_timeval
+static __inline__ void
+cputime_to_compat_timeval(const cputime_t cputime, struct compat_timeval *value)
+{
+        unsigned long jiffies = cputime_to_jiffies(cputime);
+
+        value->tv_usec = (jiffies % HZ) * (1000000L / HZ);
+        value->tv_sec = jiffies / HZ;
+}
+
 #include "../../../fs/binfmt_elf.c"
diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c
index 97c5a1668e53..202e581e6096 100644
--- a/arch/mips/kernel/binfmt_elfo32.c
+++ b/arch/mips/kernel/binfmt_elfo32.c
@@ -162,4 +162,15 @@ MODULE_AUTHOR("Ralf Baechle (ralf@linux-mips.org)");
 #undef TASK_SIZE
 #define TASK_SIZE TASK_SIZE32
 
+#undef cputime_to_timeval
+#define cputime_to_timeval cputime_to_compat_timeval
+static __inline__ void
+cputime_to_compat_timeval(const cputime_t cputime, struct compat_timeval *value)
+{
+        unsigned long jiffies = cputime_to_jiffies(cputime);
+
+        value->tv_usec = (jiffies % HZ) * (1000000L / HZ);
+        value->tv_sec = jiffies / HZ;
+}
+
 #include "../../../fs/binfmt_elf.c"
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
index cf5509f13dd5..dba90ec0dc38 100644
--- a/arch/mips/kernel/ftrace.c
+++ b/arch/mips/kernel/ftrace.c
@@ -25,12 +25,16 @@
 #define MCOUNT_OFFSET_INSNS 4
 #endif
 
+#ifdef CONFIG_DYNAMIC_FTRACE
+
 /* Arch override because MIPS doesn't need to run this from stop_machine() */
 void arch_ftrace_update_code(int command)
 {
         ftrace_modify_all_code(command);
 }
 
+#endif
+
 /*
  * Check if the address is in kernel space
  *
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 3b09b888afa9..0c655deeea4a 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -93,26 +93,27 @@ static void rm7k_wait_irqoff(void)
 }
 
 /*
- * The Au1xxx wait is available only if using 32khz counter or
- * external timer source, but specifically not CP0 Counter.
- * alchemy/common/time.c may override cpu_wait!
+ * Au1 'wait' is only useful when the 32kHz counter is used as timer,
+ * since coreclock (and the cp0 counter) stops upon executing it. Only an
+ * interrupt can wake it, so they must be enabled before entering idle modes.
  */
 static void au1k_wait(void)
 {
+        unsigned long c0status = read_c0_status() | 1;  /* irqs on */
+
         __asm__(
         "       .set    mips3                   \n"
         "       cache   0x14, 0(%0)             \n"
         "       cache   0x14, 32(%0)            \n"
         "       sync                            \n"
-        "       nop                             \n"
+        "       mtc0    %1, $12                 \n" /* wr c0status */
         "       wait                            \n"
         "       nop                             \n"
         "       nop                             \n"
         "       nop                             \n"
         "       nop                             \n"
         "       .set    mips0                   \n"
-        : : "r" (au1k_wait));
-        local_irq_enable();
+        : : "r" (au1k_wait), "r" (c0status));
 }
 
 static int __initdata nowait;
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
index 93c070b41b0d..6fa198db8999 100644
--- a/arch/mips/kernel/rtlx.c
+++ b/arch/mips/kernel/rtlx.c
@@ -40,6 +40,7 @@
 #include <asm/processor.h>
 #include <asm/vpe.h>
 #include <asm/rtlx.h>
+#include <asm/setup.h>
 
 static struct rtlx_info *rtlx;
 static int major;
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index e3be67012d78..a75ae40184aa 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -897,22 +897,24 @@ out_sigsegv:
 
 asmlinkage void do_tr(struct pt_regs *regs)
 {
-        unsigned int opcode, tcode = 0;
+        u32 opcode, tcode = 0;
         u16 instr[2];
-        unsigned long epc = exception_epc(regs);
+        unsigned long epc = msk_isa16_mode(exception_epc(regs));
 
-        if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc))) ||
-                (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2))))
+        if (get_isa16_mode(regs->cp0_epc)) {
+                if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
+                    __get_user(instr[1], (u16 __user *)(epc + 2)))
                         goto out_sigsegv;
-        opcode = (instr[0] << 16) | instr[1];
-
-        /* Immediate versions don't provide a code.  */
-        if (!(opcode & OPCODE)) {
-                if (get_isa16_mode(regs->cp0_epc))
-                        /* microMIPS */
-                        tcode = (opcode >> 12) & 0x1f;
-                else
-                        tcode = ((opcode >> 6) & ((1 << 10) - 1));
+                opcode = (instr[0] << 16) | instr[1];
+                /* Immediate versions don't provide a code.  */
+                if (!(opcode & OPCODE))
+                        tcode = (opcode >> 12) & ((1 << 4) - 1);
+        } else {
+                if (__get_user(opcode, (u32 __user *)epc))
+                        goto out_sigsegv;
+                /* Immediate versions don't provide a code.  */
+                if (!(opcode & OPCODE))
+                        tcode = (opcode >> 6) & ((1 << 10) - 1);
         }
 
         do_trap_or_bp(regs, tcode, "Trap");
diff --git a/arch/mips/kvm/kvm_mips.c b/arch/mips/kvm/kvm_mips.c
index e0dad0289797..dd203e59e6fd 100644
--- a/arch/mips/kvm/kvm_mips.c
+++ b/arch/mips/kvm/kvm_mips.c
@@ -195,7 +195,7 @@ void kvm_arch_destroy_vm(struct kvm *kvm)
 long
 kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
 {
-        return -EINVAL;
+        return -ENOIOCTLCMD;
 }
 
 void kvm_arch_free_memslot(struct kvm_memory_slot *free,
@@ -401,7 +401,7 @@ int
 kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
                                     struct kvm_guest_debug *dbg)
 {
-        return -EINVAL;
+        return -ENOIOCTLCMD;
 }
 
 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
@@ -475,14 +475,248 @@ int
 kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
                                 struct kvm_mp_state *mp_state)
 {
-        return -EINVAL;
+        return -ENOIOCTLCMD;
 }
 
 int
 kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
                                 struct kvm_mp_state *mp_state)
 {
-        return -EINVAL;
+        return -ENOIOCTLCMD;
+}
+
+#define MIPS_CP0_32(_R, _S)                                     \
+        (KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S)))
+
+#define MIPS_CP0_64(_R, _S)                                     \
+        (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S)))
+
+#define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
+#define KVM_REG_MIPS_CP0_ENTRYLO0       MIPS_CP0_64(2, 0)
+#define KVM_REG_MIPS_CP0_ENTRYLO1       MIPS_CP0_64(3, 0)
+#define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
+#define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
+#define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
+#define KVM_REG_MIPS_CP0_PAGEGRAIN      MIPS_CP0_32(5, 1)
+#define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
+#define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
+#define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
+#define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
+#define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
+#define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
+#define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
+#define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
+#define KVM_REG_MIPS_CP0_EBASE          MIPS_CP0_64(15, 1)
+#define KVM_REG_MIPS_CP0_CONFIG         MIPS_CP0_32(16, 0)
+#define KVM_REG_MIPS_CP0_CONFIG1        MIPS_CP0_32(16, 1)
+#define KVM_REG_MIPS_CP0_CONFIG2        MIPS_CP0_32(16, 2)
+#define KVM_REG_MIPS_CP0_CONFIG3        MIPS_CP0_32(16, 3)
+#define KVM_REG_MIPS_CP0_CONFIG7        MIPS_CP0_32(16, 7)
+#define KVM_REG_MIPS_CP0_XCONTEXT       MIPS_CP0_64(20, 0)
+#define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
+
+static u64 kvm_mips_get_one_regs[] = {
+        KVM_REG_MIPS_R0,
+        KVM_REG_MIPS_R1,
+        KVM_REG_MIPS_R2,
+        KVM_REG_MIPS_R3,
+        KVM_REG_MIPS_R4,
+        KVM_REG_MIPS_R5,
+        KVM_REG_MIPS_R6,
+        KVM_REG_MIPS_R7,
+        KVM_REG_MIPS_R8,
+        KVM_REG_MIPS_R9,
+        KVM_REG_MIPS_R10,
+        KVM_REG_MIPS_R11,
+        KVM_REG_MIPS_R12,
+        KVM_REG_MIPS_R13,
+        KVM_REG_MIPS_R14,
+        KVM_REG_MIPS_R15,
+        KVM_REG_MIPS_R16,
+        KVM_REG_MIPS_R17,
+        KVM_REG_MIPS_R18,
+        KVM_REG_MIPS_R19,
+        KVM_REG_MIPS_R20,
+        KVM_REG_MIPS_R21,
+        KVM_REG_MIPS_R22,
+        KVM_REG_MIPS_R23,
+        KVM_REG_MIPS_R24,
+        KVM_REG_MIPS_R25,
+        KVM_REG_MIPS_R26,
+        KVM_REG_MIPS_R27,
+        KVM_REG_MIPS_R28,
+        KVM_REG_MIPS_R29,
+        KVM_REG_MIPS_R30,
+        KVM_REG_MIPS_R31,
+
+        KVM_REG_MIPS_HI,
+        KVM_REG_MIPS_LO,
+        KVM_REG_MIPS_PC,
+
+        KVM_REG_MIPS_CP0_INDEX,
+        KVM_REG_MIPS_CP0_CONTEXT,
+        KVM_REG_MIPS_CP0_PAGEMASK,
+        KVM_REG_MIPS_CP0_WIRED,
+        KVM_REG_MIPS_CP0_BADVADDR,
+        KVM_REG_MIPS_CP0_ENTRYHI,
+        KVM_REG_MIPS_CP0_STATUS,
+        KVM_REG_MIPS_CP0_CAUSE,
+        /* EPC set via kvm_regs, et al. */
+        KVM_REG_MIPS_CP0_CONFIG,
+        KVM_REG_MIPS_CP0_CONFIG1,
+        KVM_REG_MIPS_CP0_CONFIG2,
+        KVM_REG_MIPS_CP0_CONFIG3,
+        KVM_REG_MIPS_CP0_CONFIG7,
+        KVM_REG_MIPS_CP0_ERROREPC
+};
+
+static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
+                            const struct kvm_one_reg *reg)
+{
+        struct mips_coproc *cop0 = vcpu->arch.cop0;
+        s64 v;
+
+        switch (reg->id) {
+        case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
+                v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
+                break;
+        case KVM_REG_MIPS_HI:
+                v = (long)vcpu->arch.hi;
+                break;
+        case KVM_REG_MIPS_LO:
+                v = (long)vcpu->arch.lo;
+                break;
+        case KVM_REG_MIPS_PC:
+                v = (long)vcpu->arch.pc;
+                break;
+
+        case KVM_REG_MIPS_CP0_INDEX:
+                v = (long)kvm_read_c0_guest_index(cop0);
+                break;
+        case KVM_REG_MIPS_CP0_CONTEXT:
+                v = (long)kvm_read_c0_guest_context(cop0);
+                break;
+        case KVM_REG_MIPS_CP0_PAGEMASK:
+                v = (long)kvm_read_c0_guest_pagemask(cop0);
+                break;
+        case KVM_REG_MIPS_CP0_WIRED:
+                v = (long)kvm_read_c0_guest_wired(cop0);
+                break;
+        case KVM_REG_MIPS_CP0_BADVADDR:
+                v = (long)kvm_read_c0_guest_badvaddr(cop0);
+                break;
+        case KVM_REG_MIPS_CP0_ENTRYHI:
+                v = (long)kvm_read_c0_guest_entryhi(cop0);
+                break;
+        case KVM_REG_MIPS_CP0_STATUS:
+                v = (long)kvm_read_c0_guest_status(cop0);
+                break;
+        case KVM_REG_MIPS_CP0_CAUSE:
+                v = (long)kvm_read_c0_guest_cause(cop0);
+                break;
+        case KVM_REG_MIPS_CP0_ERROREPC:
+                v = (long)kvm_read_c0_guest_errorepc(cop0);
+                break;
+        case KVM_REG_MIPS_CP0_CONFIG:
+                v = (long)kvm_read_c0_guest_config(cop0);
+                break;
+        case KVM_REG_MIPS_CP0_CONFIG1:
+                v = (long)kvm_read_c0_guest_config1(cop0);
+                break;
+        case KVM_REG_MIPS_CP0_CONFIG2:
+                v = (long)kvm_read_c0_guest_config2(cop0);
+                break;
+        case KVM_REG_MIPS_CP0_CONFIG3:
+                v = (long)kvm_read_c0_guest_config3(cop0);
+                break;
+        case KVM_REG_MIPS_CP0_CONFIG7:
+                v = (long)kvm_read_c0_guest_config7(cop0);
+                break;
+        default:
+                return -EINVAL;
+        }
+        if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
+                u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
+                return put_user(v, uaddr64);
+        } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
+                u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
+                u32 v32 = (u32)v;
+                return put_user(v32, uaddr32);
+        } else {
+                return -EINVAL;
+        }
+}
+
+static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
+                            const struct kvm_one_reg *reg)
+{
+        struct mips_coproc *cop0 = vcpu->arch.cop0;
+        u64 v;
+
+        if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
+                u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
+
+                if (get_user(v, uaddr64) != 0)
+                        return -EFAULT;
+        } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
+                u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
+                s32 v32;
+
+                if (get_user(v32, uaddr32) != 0)
+                        return -EFAULT;
+                v = (s64)v32;
+        } else {
+                return -EINVAL;
+        }
+
+        switch (reg->id) {
+        case KVM_REG_MIPS_R0:
+                /* Silently ignore requests to set $0 */
+                break;
+        case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
+                vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
+                break;
+        case KVM_REG_MIPS_HI:
+                vcpu->arch.hi = v;
+                break;
+        case KVM_REG_MIPS_LO:
+                vcpu->arch.lo = v;
+                break;
+        case KVM_REG_MIPS_PC:
+                vcpu->arch.pc = v;
+                break;
+
+        case KVM_REG_MIPS_CP0_INDEX:
+                kvm_write_c0_guest_index(cop0, v);
+                break;
+        case KVM_REG_MIPS_CP0_CONTEXT:
+                kvm_write_c0_guest_context(cop0, v);
+                break;
+        case KVM_REG_MIPS_CP0_PAGEMASK:
+                kvm_write_c0_guest_pagemask(cop0, v);
+                break;
+        case KVM_REG_MIPS_CP0_WIRED:
+                kvm_write_c0_guest_wired(cop0, v);
+                break;
+        case KVM_REG_MIPS_CP0_BADVADDR:
+                kvm_write_c0_guest_badvaddr(cop0, v);
+                break;
+        case KVM_REG_MIPS_CP0_ENTRYHI:
+                kvm_write_c0_guest_entryhi(cop0, v);
+                break;
+        case KVM_REG_MIPS_CP0_STATUS:
+                kvm_write_c0_guest_status(cop0, v);
+                break;
+        case KVM_REG_MIPS_CP0_CAUSE:
+                kvm_write_c0_guest_cause(cop0, v);
+                break;
+        case KVM_REG_MIPS_CP0_ERROREPC:
+                kvm_write_c0_guest_errorepc(cop0, v);
+                break;
+        default:
+                return -EINVAL;
+        }
+        return 0;
 }
 
 long
@@ -491,9 +725,38 @@ kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
         struct kvm_vcpu *vcpu = filp->private_data;
         void __user *argp = (void __user *)arg;
         long r;
-        int intr;
 
         switch (ioctl) {
+        case KVM_SET_ONE_REG:
+        case KVM_GET_ONE_REG: {
+                struct kvm_one_reg reg;
+                if (copy_from_user(&reg, argp, sizeof(reg)))
+                        return -EFAULT;
+                if (ioctl == KVM_SET_ONE_REG)
+                        return kvm_mips_set_reg(vcpu, &reg);
+                else
+                        return kvm_mips_get_reg(vcpu, &reg);
+        }
+        case KVM_GET_REG_LIST: {
+                struct kvm_reg_list __user *user_list = argp;
+                u64 __user *reg_dest;
+                struct kvm_reg_list reg_list;
+                unsigned n;
+
+                if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
+                        return -EFAULT;
+                n = reg_list.n;
+                reg_list.n = ARRAY_SIZE(kvm_mips_get_one_regs);
+                if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
+                        return -EFAULT;
+                if (n < reg_list.n)
+                        return -E2BIG;
+                reg_dest = user_list->reg;
+                if (copy_to_user(reg_dest, kvm_mips_get_one_regs,
+                                 sizeof(kvm_mips_get_one_regs)))
+                        return -EFAULT;
+                return 0;
+        }
         case KVM_NMI:
                 /* Treat the NMI as a CPU reset */
                 r = kvm_mips_reset_vcpu(vcpu);
@@ -505,8 +768,6 @@ kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
                         if (copy_from_user(&irq, argp, sizeof(irq)))
                                 goto out;
 
-                        intr = (int)irq.irq;
-
                         kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
                                   irq.irq);
 
@@ -514,7 +775,7 @@ kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
                         break;
                 }
         default:
-                r = -EINVAL;
+                r = -ENOIOCTLCMD;
         }
 
 out:
@@ -565,7 +826,7 @@ long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
 
         switch (ioctl) {
         default:
-                r = -EINVAL;
+                r = -ENOIOCTLCMD;
         }
 
         return r;
@@ -593,13 +854,13 @@ void kvm_arch_exit(void)
 int
 kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
 {
-        return -ENOTSUPP;
+        return -ENOIOCTLCMD;
 }
 
 int
 kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
 {
-        return -ENOTSUPP;
+        return -ENOIOCTLCMD;
 }
 
 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
@@ -609,12 +870,12 @@ int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
 
 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
 {
-        return -ENOTSUPP;
+        return -ENOIOCTLCMD;
 }
 
 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
 {
-        return -ENOTSUPP;
+        return -ENOIOCTLCMD;
 }
 
 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
@@ -627,6 +888,9 @@ int kvm_dev_ioctl_check_extension(long ext)
         int r;
 
         switch (ext) {
+        case KVM_CAP_ONE_REG:
+                r = 1;
+                break;
         case KVM_CAP_COALESCED_MMIO:
                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
                 break;
@@ -635,7 +899,6 @@ int kvm_dev_ioctl_check_extension(long ext)
                 break;
         }
         return r;
-
 }
 
 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
@@ -677,28 +940,28 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
 {
         int i;
 
-        for (i = 0; i < 32; i++)
-                vcpu->arch.gprs[i] = regs->gprs[i];
-
+        for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
+                vcpu->arch.gprs[i] = regs->gpr[i];
+        vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
         vcpu->arch.hi = regs->hi;
         vcpu->arch.lo = regs->lo;
         vcpu->arch.pc = regs->pc;
 
-        return kvm_mips_callbacks->vcpu_ioctl_set_regs(vcpu, regs);
+        return 0;
 }
 
 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
 {
         int i;
 
-        for (i = 0; i < 32; i++)
-                regs->gprs[i] = vcpu->arch.gprs[i];
+        for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
+                regs->gpr[i] = vcpu->arch.gprs[i];
 
         regs->hi = vcpu->arch.hi;
         regs->lo = vcpu->arch.lo;
         regs->pc = vcpu->arch.pc;
 
-        return kvm_mips_callbacks->vcpu_ioctl_get_regs(vcpu, regs);
+        return 0;
 }
 
 void kvm_mips_comparecount_func(unsigned long data)
diff --git a/arch/mips/kvm/kvm_trap_emul.c b/arch/mips/kvm/kvm_trap_emul.c
index 466aeef044bd..30d725321db1 100644
--- a/arch/mips/kvm/kvm_trap_emul.c
+++ b/arch/mips/kvm/kvm_trap_emul.c
@@ -345,54 +345,6 @@ static int kvm_trap_emul_handle_break(struct kvm_vcpu *vcpu)
         return ret;
 }
 
-static int
-kvm_trap_emul_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
-{
-        struct mips_coproc *cop0 = vcpu->arch.cop0;
-
-        kvm_write_c0_guest_index(cop0, regs->cp0reg[MIPS_CP0_TLB_INDEX][0]);
-        kvm_write_c0_guest_context(cop0, regs->cp0reg[MIPS_CP0_TLB_CONTEXT][0]);
-        kvm_write_c0_guest_badvaddr(cop0, regs->cp0reg[MIPS_CP0_BAD_VADDR][0]);
-        kvm_write_c0_guest_entryhi(cop0, regs->cp0reg[MIPS_CP0_TLB_HI][0]);
-        kvm_write_c0_guest_epc(cop0, regs->cp0reg[MIPS_CP0_EXC_PC][0]);
-
-        kvm_write_c0_guest_status(cop0, regs->cp0reg[MIPS_CP0_STATUS][0]);
-        kvm_write_c0_guest_cause(cop0, regs->cp0reg[MIPS_CP0_CAUSE][0]);
-        kvm_write_c0_guest_pagemask(cop0,
-                                    regs->cp0reg[MIPS_CP0_TLB_PG_MASK][0]);
-        kvm_write_c0_guest_wired(cop0, regs->cp0reg[MIPS_CP0_TLB_WIRED][0]);
-        kvm_write_c0_guest_errorepc(cop0, regs->cp0reg[MIPS_CP0_ERROR_PC][0]);
-
-        return 0;
-}
-
-static int
-kvm_trap_emul_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
-{
-        struct mips_coproc *cop0 = vcpu->arch.cop0;
-
-        regs->cp0reg[MIPS_CP0_TLB_INDEX][0] = kvm_read_c0_guest_index(cop0);
-        regs->cp0reg[MIPS_CP0_TLB_CONTEXT][0] = kvm_read_c0_guest_context(cop0);
-        regs->cp0reg[MIPS_CP0_BAD_VADDR][0] = kvm_read_c0_guest_badvaddr(cop0);
-        regs->cp0reg[MIPS_CP0_TLB_HI][0] = kvm_read_c0_guest_entryhi(cop0);
-        regs->cp0reg[MIPS_CP0_EXC_PC][0] = kvm_read_c0_guest_epc(cop0);
-
-        regs->cp0reg[MIPS_CP0_STATUS][0] = kvm_read_c0_guest_status(cop0);
-        regs->cp0reg[MIPS_CP0_CAUSE][0] = kvm_read_c0_guest_cause(cop0);
-        regs->cp0reg[MIPS_CP0_TLB_PG_MASK][0] =
-            kvm_read_c0_guest_pagemask(cop0);
-        regs->cp0reg[MIPS_CP0_TLB_WIRED][0] = kvm_read_c0_guest_wired(cop0);
-        regs->cp0reg[MIPS_CP0_ERROR_PC][0] = kvm_read_c0_guest_errorepc(cop0);
-
-        regs->cp0reg[MIPS_CP0_CONFIG][0] = kvm_read_c0_guest_config(cop0);
-        regs->cp0reg[MIPS_CP0_CONFIG][1] = kvm_read_c0_guest_config1(cop0);
-        regs->cp0reg[MIPS_CP0_CONFIG][2] = kvm_read_c0_guest_config2(cop0);
-        regs->cp0reg[MIPS_CP0_CONFIG][3] = kvm_read_c0_guest_config3(cop0);
-        regs->cp0reg[MIPS_CP0_CONFIG][7] = kvm_read_c0_guest_config7(cop0);
-
-        return 0;
-}
-
 static int kvm_trap_emul_vm_init(struct kvm *kvm)
 {
         return 0;
@@ -471,8 +423,6 @@ static struct kvm_mips_callbacks kvm_trap_emul_callbacks = {
         .dequeue_io_int = kvm_mips_dequeue_io_int_cb,
         .irq_deliver = kvm_mips_irq_deliver_cb,
         .irq_clear = kvm_mips_irq_clear_cb,
-        .vcpu_ioctl_get_regs = kvm_trap_emul_ioctl_get_regs,
-        .vcpu_ioctl_set_regs = kvm_trap_emul_ioctl_set_regs,
 };
 
 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks)
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index ce9818eef7d3..afeef93f81a7 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -301,10 +301,6 @@ static u32 tlb_handler[128] __cpuinitdata;
 static struct uasm_label labels[128] __cpuinitdata;
 static struct uasm_reloc relocs[128] __cpuinitdata;
 
-#ifdef CONFIG_64BIT
-static int check_for_high_segbits __cpuinitdata;
-#endif
-
 static int check_for_high_segbits __cpuinitdata;
 
 static unsigned int kscratch_used_mask __cpuinitdata;
diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
index fb1569580def..6b5f3406f414 100644
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -88,7 +88,7 @@ void __init plat_mem_setup(void)
         __dt_setup_arch(&__dtb_start);
 
         if (soc_info.mem_size)
-                add_memory_region(soc_info.mem_base, soc_info.mem_size,
+                add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M,
                                   BOOT_MEM_RAM);
         else
                 detect_memory_region(soc_info.mem_base,
diff --git a/arch/mn10300/include/asm/pci.h b/arch/mn10300/include/asm/pci.h
index 8137c25c4e15..6f31cc0f1a87 100644
--- a/arch/mn10300/include/asm/pci.h
+++ b/arch/mn10300/include/asm/pci.h
@@ -103,4 +103,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
         return channel ? 15 : 14;
 }
 
+#include <asm-generic/pci_iomap.h>
+
 #endif /* _ASM_PCI_H */
diff --git a/arch/mn10300/kernel/entry.S b/arch/mn10300/kernel/entry.S
index 68fcab8f8f6f..222152a3f751 100644
--- a/arch/mn10300/kernel/entry.S
+++ b/arch/mn10300/kernel/entry.S
@@ -60,6 +60,7 @@ ENTRY(ret_from_kernel_thread)
         mov     (REG_D0,fp),d0
         mov     (REG_A0,fp),a0
         calls   (a0)
+        GET_THREAD_INFO a2              # A2 must be set on return from sys_exit()
         clr     d0
         mov     d0,(REG_D0,fp)
         jmp     syscall_exit
@@ -107,10 +108,10 @@ syscall_exit_work:
         and     EPSW_nSL,d0
         beq     resume_kernel           # returning to supervisor mode
 
-        btst    _TIF_SYSCALL_TRACE,d2
-        beq     work_pending
         LOCAL_IRQ_ENABLE                # could let syscall_trace_exit() call
                                         # schedule() instead
+        btst    _TIF_SYSCALL_TRACE,d2
+        beq     work_pending
         mov     fp,d0
         call    syscall_trace_exit[],0  # do_syscall_trace(regs)
         jmp     resume_userspace
@@ -123,6 +124,7 @@ work_pending:
 work_resched:
         call    schedule[],0
 
+resume_userspace:
         # make sure we don't miss an interrupt setting need_resched or
         # sigpending between sampling and the rti
         LOCAL_IRQ_DISABLE
@@ -131,6 +133,8 @@ work_resched:
         mov     (TI_flags,a2),d2
         btst    _TIF_WORK_MASK,d2
         beq     restore_all
+
+        LOCAL_IRQ_ENABLE
         btst    _TIF_NEED_RESCHED,d2
         bne     work_resched
 
@@ -169,17 +173,6 @@ ret_from_intr:
         and     EPSW_nSL,d0
         beq     resume_kernel           # returning to supervisor mode
 
-ENTRY(resume_userspace)
-        # make sure we don't miss an interrupt setting need_resched or
-        # sigpending between sampling and the rti
-        LOCAL_IRQ_DISABLE
-
-        # is there any work to be done on int/exception return?
-        mov     (TI_flags,a2),d2
-        btst    _TIF_WORK_MASK,d2
-        bne     work_pending
-        jmp     restore_all
-
 #ifdef CONFIG_PREEMPT
 ENTRY(resume_kernel)
         LOCAL_IRQ_DISABLE
diff --git a/arch/mn10300/unit-asb2305/pci.c b/arch/mn10300/unit-asb2305/pci.c
index 1adcf024bb9a..e37fac0461f3 100644
--- a/arch/mn10300/unit-asb2305/pci.c
+++ b/arch/mn10300/unit-asb2305/pci.c
@@ -19,6 +19,7 @@
 #include <linux/delay.h>
 #include <linux/irq.h>
 #include <asm/io.h>
+#include <asm/irq.h>
 #include "pci-asb2305.h"
 
 unsigned int pci_probe = 1;
diff --git a/arch/parisc/Makefile b/arch/parisc/Makefile
index 197690068f88..96ec3982be8d 100644
--- a/arch/parisc/Makefile
+++ b/arch/parisc/Makefile
@@ -66,7 +66,7 @@ KBUILD_CFLAGS_KERNEL += -mlong-calls
 endif
 
 # select which processor to optimise for
-cflags-$(CONFIG_PA7100)         += -march=1.1 -mschedule=7100
+cflags-$(CONFIG_PA7000)         += -march=1.1 -mschedule=7100
 cflags-$(CONFIG_PA7200)         += -march=1.1 -mschedule=7200
 cflags-$(CONFIG_PA7100LC)       += -march=1.1 -mschedule=7100LC
 cflags-$(CONFIG_PA7300LC)       += -march=1.1 -mschedule=7300
diff --git a/arch/parisc/include/asm/mmzone.h b/arch/parisc/include/asm/mmzone.h
index 0e625ab9aaec..cc50d33b7b88 100644
--- a/arch/parisc/include/asm/mmzone.h
+++ b/arch/parisc/include/asm/mmzone.h
@@ -39,17 +39,14 @@ extern unsigned char pfnnid_map[PFNNID_MAP_MAX];
 static inline int pfn_to_nid(unsigned long pfn)
 {
         unsigned int i;
-        unsigned char r;
 
         if (unlikely(pfn_is_io(pfn)))
                 return 0;
 
         i = pfn >> PFNNID_SHIFT;
         BUG_ON(i >= ARRAY_SIZE(pfnnid_map));
-        r = pfnnid_map[i];
-        BUG_ON(r == 0xff);
 
-        return (int)r;
+        return (int)pfnnid_map[i];
 }
 
 static inline int pfn_valid(int pfn)
diff --git a/arch/parisc/kernel/drivers.c b/arch/parisc/kernel/drivers.c
index 5709c5e59be8..14285caec71a 100644
--- a/arch/parisc/kernel/drivers.c
+++ b/arch/parisc/kernel/drivers.c
@@ -394,7 +394,7 @@ EXPORT_SYMBOL(print_pci_hwpath);
 static void setup_bus_id(struct parisc_device *padev)
 {
         struct hardware_path path;
-        char name[20];
+        char name[28];
         char *output = name;
         int i;
 
diff --git a/arch/parisc/kernel/setup.c b/arch/parisc/kernel/setup.c
index 76b63e726a53..1e95b2000ce8 100644
--- a/arch/parisc/kernel/setup.c
+++ b/arch/parisc/kernel/setup.c
@@ -69,7 +69,8 @@ void __init setup_cmdline(char **cmdline_p)
                 /* called from hpux boot loader */
                 boot_command_line[0] = '\0';
         } else {
-                strcpy(boot_command_line, (char *)__va(boot_args[1]));
+                strlcpy(boot_command_line, (char *)__va(boot_args[1]),
+                        COMMAND_LINE_SIZE);
 
 #ifdef CONFIG_BLK_DEV_INITRD
                 if (boot_args[2] != 0) /* did palo pass us a ramdisk? */
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 26807e5aff51..6f3887d884d2 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -176,6 +176,7 @@ extern const char *powerpc_base_platform;
 #define CPU_FTR_CFAR                    LONG_ASM_CONST(0x0100000000000000)
 #define CPU_FTR_HAS_PPR                 LONG_ASM_CONST(0x0200000000000000)
 #define CPU_FTR_DAWR                    LONG_ASM_CONST(0x0400000000000000)
+#define CPU_FTR_DABRX                   LONG_ASM_CONST(0x0800000000000000)
 
 #ifndef __ASSEMBLY__
 
@@ -394,19 +395,20 @@ extern const char *powerpc_base_platform;
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
             CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
-            CPU_FTR_HVMODE)
+            CPU_FTR_HVMODE | CPU_FTR_DABRX)
 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
             CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
-            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
+            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
             CPU_FTR_COHERENT_ICACHE | \
             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
             CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
-            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR)
+            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
+            CPU_FTR_DABRX)
 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -415,7 +417,7 @@ extern const char *powerpc_base_platform;
             CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \
             CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
             CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
-            CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR)
+            CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)
 #define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -430,14 +432,15 @@ extern const char *powerpc_base_platform;
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
             CPU_FTR_PAUSE_ZERO  | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
-            CPU_FTR_UNALIGNED_LD_STD)
+            CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
-            CPU_FTR_PURR | CPU_FTR_REAL_LE)
+            CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
 #define CPU_FTRS_COMPATIBLE     (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
 
 #define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
-                     CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
+                     CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | \
+                     CPU_FTR_ICSWX | CPU_FTR_DABRX )
 
 #ifdef __powerpc64__
 #ifdef CONFIG_PPC_BOOK3E
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 8e5fae8beaf6..46793b58a761 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -513,7 +513,7 @@ label##_common:							\
  */
 #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr)             \
         EXCEPTION_COMMON(trap, label, hdlr, ret_from_except_lite, \
-                         FINISH_NAP;RUNLATCH_ON;DISABLE_INTS)
+                         FINISH_NAP;DISABLE_INTS;RUNLATCH_ON)
 
 /*
  * When the idle code in power4_idle puts the CPU into NAP mode,
diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
index cf4df8e2139a..0c7f2bfcf134 100644
--- a/arch/powerpc/include/asm/hvcall.h
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -264,6 +264,7 @@
 #define H_GET_MPP               0x2D4
 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC
 #define H_BEST_ENERGY           0x2F4
+#define H_XIRR_X                0x2FC
 #define H_RANDOM                0x300
 #define H_COP                   0x304
 #define H_GET_MPP_X             0x314
diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h
index b9dd382cb349..851bac7afa4b 100644
--- a/arch/powerpc/include/asm/kvm_asm.h
+++ b/arch/powerpc/include/asm/kvm_asm.h
@@ -54,8 +54,16 @@
 #define BOOKE_INTERRUPT_DEBUG 15
 
 /* E500 */
-#define BOOKE_INTERRUPT_SPE_UNAVAIL 32
-#define BOOKE_INTERRUPT_SPE_FP_DATA 33
+#define BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL 32
+#define BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST 33
+/*
+ * TODO: Unify 32-bit and 64-bit kernel exception handlers to use same defines
+ */
+#define BOOKE_INTERRUPT_SPE_UNAVAIL BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL
+#define BOOKE_INTERRUPT_SPE_FP_DATA BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST
+#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL
+#define BOOKE_INTERRUPT_ALTIVEC_ASSIST \
+                                BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST
 #define BOOKE_INTERRUPT_SPE_FP_ROUND 34
 #define BOOKE_INTERRUPT_PERFORMANCE_MONITOR 35
 #define BOOKE_INTERRUPT_DOORBELL 36
@@ -67,10 +75,6 @@
 #define BOOKE_INTERRUPT_HV_SYSCALL 40
 #define BOOKE_INTERRUPT_HV_PRIV 41
 
-/* altivec */
-#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL 42
-#define BOOKE_INTERRUPT_ALTIVEC_ASSIST 43
-
 /* book3s */
 
 #define BOOK3S_INTERRUPT_SYSTEM_RESET   0x100
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index cea8496091ff..2f1b6c5f8174 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -523,6 +523,17 @@ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,946)
 #define PPC440EP_ERR42
 #endif
 
+/* The following stops all load and store data streams associated with stream
+ * ID (ie. streams created explicitly).  The embedded and server mnemonics for
+ * dcbt are different so we use machine "power4" here explicitly.
+ */
+#define DCBT_STOP_ALL_STREAM_IDS(scratch)       \
+.machine push ;                                 \
+.machine "power4" ;                             \
+       lis     scratch,0x60000000@h;            \
+       dcbt    r0,scratch,0b01010;              \
+.machine pop
+
 /*
  * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
  * keep the address intact to be compatible with code shared with
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 594db6bc093c..14a658363698 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -409,21 +409,16 @@ static inline void prefetchw(const void *x)
 #endif
 
 #ifdef CONFIG_PPC64
-static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
+static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
 {
-        unsigned long sp;
-
         if (is_32)
-                sp = regs->gpr[1] & 0x0ffffffffUL;
-        else
-                sp = regs->gpr[1];
-
+                return sp & 0x0ffffffffUL;
         return sp;
 }
 #else
-static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
+static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
 {
-        return regs->gpr[1];
+        return sp;
 }
 #endif
 
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index a6136515c7f2..4a9e408644fe 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -111,17 +111,6 @@
 #define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T)
 #define MSR_TM_SUSPENDED(x)     (((x) & MSR_TS_MASK) == MSR_TS_S)
 
-/* Reason codes describing kernel causes for transaction aborts.  By
-   convention, bit0 is copied to TEXASR[56] (IBM bit 7) which is set if
-   the failure is persistent.
-*/
-#define TM_CAUSE_RESCHED        0xfe
-#define TM_CAUSE_TLBI           0xfc
-#define TM_CAUSE_FAC_UNAV       0xfa
-#define TM_CAUSE_SYSCALL        0xf9 /* Persistent */
-#define TM_CAUSE_MISC           0xf6
-#define TM_CAUSE_SIGNAL         0xf4
-
 #if defined(CONFIG_PPC_BOOK3S_64)
 #define MSR_64BIT       MSR_SF
 
diff --git a/arch/powerpc/include/asm/signal.h b/arch/powerpc/include/asm/signal.h
index fbe66c463891..9322c28aebd2 100644
--- a/arch/powerpc/include/asm/signal.h
+++ b/arch/powerpc/include/asm/signal.h
@@ -3,5 +3,8 @@
 
 #define __ARCH_HAS_SA_RESTORER
 #include <uapi/asm/signal.h>
+#include <uapi/asm/ptrace.h>
+
+extern unsigned long get_tm_stackpointer(struct pt_regs *regs);
 
 #endif /* _ASM_POWERPC_SIGNAL_H */
diff --git a/arch/powerpc/include/asm/tm.h b/arch/powerpc/include/asm/tm.h
index 4b4449abf3f8..9dfbc34bdbf5 100644
--- a/arch/powerpc/include/asm/tm.h
+++ b/arch/powerpc/include/asm/tm.h
@@ -5,6 +5,8 @@
  * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
  */
 
+#include <uapi/asm/tm.h>
+
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 extern void do_load_up_transact_fpu(struct thread_struct *thread);
 extern void do_load_up_transact_altivec(struct thread_struct *thread);
diff --git a/arch/powerpc/include/uapi/asm/Kbuild b/arch/powerpc/include/uapi/asm/Kbuild
index f7bca6370745..5182c8622b54 100644
--- a/arch/powerpc/include/uapi/asm/Kbuild
+++ b/arch/powerpc/include/uapi/asm/Kbuild
@@ -40,6 +40,7 @@ header-y += statfs.h
 header-y += swab.h
 header-y += termbits.h
 header-y += termios.h
+header-y += tm.h
 header-y += types.h
 header-y += ucontext.h
 header-y += unistd.h
diff --git a/arch/powerpc/include/uapi/asm/tm.h b/arch/powerpc/include/uapi/asm/tm.h
new file mode 100644
index 000000000000..85059a00f560
--- /dev/null
+++ b/arch/powerpc/include/uapi/asm/tm.h
@@ -0,0 +1,18 @@
+#ifndef _ASM_POWERPC_TM_H
+#define _ASM_POWERPC_TM_H
+
+/* Reason codes describing kernel causes for transaction aborts.  By
+ * convention, bit0 is copied to TEXASR[56] (IBM bit 7) which is set if
+ * the failure is persistent.  PAPR saves 0xff-0xe0 for the hypervisor.
+ */
+#define TM_CAUSE_PERSISTENT     0x01
+#define TM_CAUSE_RESCHED        0xde
+#define TM_CAUSE_TLBI           0xdc
+#define TM_CAUSE_FAC_UNAV       0xda
+#define TM_CAUSE_SYSCALL        0xd8  /* future use */
+#define TM_CAUSE_MISC           0xd6  /* future use */
+#define TM_CAUSE_SIGNAL         0xd4
+#define TM_CAUSE_ALIGNMENT      0xd2
+#define TM_CAUSE_EMULATE        0xd0
+
+#endif
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index c60bbec25c1f..2a45d0f04385 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -452,7 +452,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .mmu_features           = MMU_FTRS_POWER8,
                 .icache_bsize           = 128,
                 .dcache_bsize           = 128,
-                .oprofile_type          = PPC_OPROFILE_POWER4,
+                .oprofile_type          = PPC_OPROFILE_INVALID,
                 .oprofile_cpu_type      = "ppc64/ibm-compat-v1",
                 .cpu_setup              = __setup_cpu_power8,
                 .cpu_restore            = __restore_cpu_power8,
@@ -482,7 +482,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .cpu_name               = "POWER7+ (raw)",
                 .cpu_features           = CPU_FTRS_POWER7,
                 .cpu_user_features      = COMMON_USER_POWER7,
-                .cpu_user_features      = COMMON_USER2_POWER7,
+                .cpu_user_features2     = COMMON_USER2_POWER7,
                 .mmu_features           = MMU_FTRS_POWER7,
                 .icache_bsize           = 128,
                 .dcache_bsize           = 128,
@@ -507,7 +507,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .num_pmcs               = 6,
                 .pmc_type               = PPC_PMC_IBM,
                 .oprofile_cpu_type      = "ppc64/power8",
-                .oprofile_type          = PPC_OPROFILE_POWER4,
+                .oprofile_type          = PPC_OPROFILE_INVALID,
                 .cpu_setup              = __setup_cpu_power8,
                 .cpu_restore            = __restore_cpu_power8,
                 .platform               = "power8",
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index d22e73e4618b..22b45a4955cd 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -849,7 +849,7 @@ resume_kernel:
         /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
         CURRENT_THREAD_INFO(r9, r1)
         lwz     r8,TI_FLAGS(r9)
-        andis.  r8,r8,_TIF_EMULATE_STACK_STORE@h
+        andis.  r0,r8,_TIF_EMULATE_STACK_STORE@h
         beq+    1f
 
         addi    r8,r1,INT_FRAME_SIZE    /* Get the kprobed function entry */
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 0e9095e47b5b..8741c854e03d 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -465,20 +465,6 @@ BEGIN_FTR_SECTION
         std     r0, THREAD_EBBHR(r3)
         mfspr   r0, SPRN_EBBRR
         std     r0, THREAD_EBBRR(r3)
-
-        /* PMU registers made user read/(write) by EBB */
-        mfspr   r0, SPRN_SIAR
-        std     r0, THREAD_SIAR(r3)
-        mfspr   r0, SPRN_SDAR
-        std     r0, THREAD_SDAR(r3)
-        mfspr   r0, SPRN_SIER
-        std     r0, THREAD_SIER(r3)
-        mfspr   r0, SPRN_MMCR0
-        std     r0, THREAD_MMCR0(r3)
-        mfspr   r0, SPRN_MMCR2
-        std     r0, THREAD_MMCR2(r3)
-        mfspr   r0, SPRN_MMCRA
-        std     r0, THREAD_MMCRA(r3)
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 #endif
 
@@ -501,6 +487,13 @@ BEGIN_FTR_SECTION
         ldarx   r6,0,r1
 END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS)
 
+#ifdef CONFIG_PPC_BOOK3S
+/* Cancel all explict user streams as they will have no use after context
+ * switch and will stop the HW from creating streams itself
+ */
+        DCBT_STOP_ALL_STREAM_IDS(r6)
+#endif
+
         addi    r6,r4,-THREAD   /* Convert THREAD to 'current' */
         std     r6,PACACURRENT(r13)     /* Set new 'current' */
 
@@ -574,20 +567,6 @@ BEGIN_FTR_SECTION
         ld      r0, THREAD_EBBRR(r4)
         mtspr   SPRN_EBBRR, r0
 
-        /* PMU registers made user read/(write) by EBB */
-        ld      r0, THREAD_SIAR(r4)
-        mtspr   SPRN_SIAR, r0
-        ld      r0, THREAD_SDAR(r4)
-        mtspr   SPRN_SDAR, r0
-        ld      r0, THREAD_SIER(r4)
-        mtspr   SPRN_SIER, r0
-        ld      r0, THREAD_MMCR0(r4)
-        mtspr   SPRN_MMCR0, r0
-        ld      r0, THREAD_MMCR2(r4)
-        mtspr   SPRN_MMCR2, r0
-        ld      r0, THREAD_MMCRA(r4)
-        mtspr   SPRN_MMCRA, r0
-
         ld      r0,THREAD_TAR(r4)
         mtspr   SPRN_TAR,r0
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index e6eba1bf61ad..40e4a17c8ba0 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -454,38 +454,14 @@ BEGIN_FTR_SECTION
         xori    r10,r10,(MSR_FE0|MSR_FE1)
         mtmsrd  r10
         sync
-        fmr     0,0
-        fmr     1,1
-        fmr     2,2
-        fmr     3,3
-        fmr     4,4
-        fmr     5,5
-        fmr     6,6
-        fmr     7,7
-        fmr     8,8
-        fmr     9,9
-        fmr     10,10
-        fmr     11,11
-        fmr     12,12
-        fmr     13,13
-        fmr     14,14
-        fmr     15,15
-        fmr     16,16
-        fmr     17,17
-        fmr     18,18
-        fmr     19,19
-        fmr     20,20
-        fmr     21,21
-        fmr     22,22
-        fmr     23,23
-        fmr     24,24
-        fmr     25,25
-        fmr     26,26
-        fmr     27,27
-        fmr     28,28
-        fmr     29,29
-        fmr     30,30
-        fmr     31,31
+
+#define FMR2(n)  fmr (n), (n) ; fmr n+1, n+1
+#define FMR4(n)  FMR2(n) ; FMR2(n+2)
+#define FMR8(n)  FMR4(n) ; FMR4(n+4)
+#define FMR16(n) FMR8(n) ; FMR8(n+8)
+#define FMR32(n) FMR16(n) ; FMR16(n+16)
+        FMR32(0)
+
 FTR_SECTION_ELSE
 /*
  * To denormalise we need to move a copy of the register to itself.
@@ -495,39 +471,25 @@ FTR_SECTION_ELSE
         oris    r10,r10,MSR_VSX@h
         mtmsrd  r10
         sync
-        XVCPSGNDP(0,0,0)
-        XVCPSGNDP(1,1,1)
-        XVCPSGNDP(2,2,2)
-        XVCPSGNDP(3,3,3)
-        XVCPSGNDP(4,4,4)
-        XVCPSGNDP(5,5,5)
-        XVCPSGNDP(6,6,6)
-        XVCPSGNDP(7,7,7)
-        XVCPSGNDP(8,8,8)
-        XVCPSGNDP(9,9,9)
-        XVCPSGNDP(10,10,10)
-        XVCPSGNDP(11,11,11)
-        XVCPSGNDP(12,12,12)
-        XVCPSGNDP(13,13,13)
-        XVCPSGNDP(14,14,14)
-        XVCPSGNDP(15,15,15)
-        XVCPSGNDP(16,16,16)
-        XVCPSGNDP(17,17,17)
-        XVCPSGNDP(18,18,18)
-        XVCPSGNDP(19,19,19)
-        XVCPSGNDP(20,20,20)
-        XVCPSGNDP(21,21,21)
-        XVCPSGNDP(22,22,22)
-        XVCPSGNDP(23,23,23)
-        XVCPSGNDP(24,24,24)
-        XVCPSGNDP(25,25,25)
-        XVCPSGNDP(26,26,26)
-        XVCPSGNDP(27,27,27)
-        XVCPSGNDP(28,28,28)
-        XVCPSGNDP(29,29,29)
-        XVCPSGNDP(30,30,30)
-        XVCPSGNDP(31,31,31)
+
+#define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
+#define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
+#define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
+#define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
+#define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
+        XVCPSGNDP32(0)
+
 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
+
+BEGIN_FTR_SECTION
+        b       denorm_done
+END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
+/*
+ * To denormalise we need to move a copy of the register to itself.
+ * For POWER8 we need to do that for all 64 VSX registers
+ */
+        XVCPSGNDP32(32)
+denorm_done:
         mtspr   SPRN_HSRR0,r11
         mtcrf   0x80,r9
         ld      r9,PACA_EXGEN+EX_R9(r13)
@@ -721,7 +683,7 @@ machine_check_common:
         STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
         STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
         STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
-        STD_EXCEPTION_COMMON(0xe40, emulation_assist, .program_check_exception)
+        STD_EXCEPTION_COMMON(0xe40, emulation_assist, .emulation_assist_interrupt)
         STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception)
 #ifdef CONFIG_PPC_DOORBELL
         STD_EXCEPTION_COMMON_ASYNC(0xe80, h_doorbell, .doorbell_exception)
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 5cbcf4d5a808..ea185e0b3cae 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -162,7 +162,7 @@ notrace unsigned int __check_irq_replay(void)
          * in case we also had a rollover while hard disabled
          */
         local_paca->irq_happened &= ~PACA_IRQ_DEC;
-        if (decrementer_check_overflow())
+        if ((happened & PACA_IRQ_DEC) || decrementer_check_overflow())
                 return 0x900;
 
         /* Finally check if an external interrupt happened */
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index e9acf50dd5b2..eabeec991016 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -657,15 +657,6 @@ void pci_resource_to_user(const struct pci_dev *dev, int bar,
  *     ranges. However, some machines (thanks Apple !) tend to split their
  *     space into lots of small contiguous ranges. So we have to coalesce.
  *
- *   - We can only cope with all memory ranges having the same offset
- *     between CPU addresses and PCI addresses. Unfortunately, some bridges
- *     are setup for a large 1:1 mapping along with a small "window" which
- *     maps PCI address 0 to some arbitrary high address of the CPU space in
- *     order to give access to the ISA memory hole.
- *     The way out of here that I've chosen for now is to always set the
- *     offset based on the first resource found, then override it if we
- *     have a different offset and the previous was set by an ISA hole.
- *
  *   - Some busses have IO space not starting at 0, which causes trouble with
  *     the way we do our IO resource renumbering. The code somewhat deals with
  *     it for 64 bits but I would expect problems on 32 bits.
@@ -680,10 +671,9 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose,
         int rlen;
         int pna = of_n_addr_cells(dev);
         int np = pna + 5;
-        int memno = 0, isa_hole = -1;
+        int memno = 0;
         u32 pci_space;
         unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
-        unsigned long long isa_mb = 0;
         struct resource *res;
 
         printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
@@ -777,8 +767,6 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose,
                         }
                         /* Handles ISA memory hole space here */
                         if (pci_addr == 0) {
-                                isa_mb = cpu_addr;
-                                isa_hole = memno;
                                 if (primary || isa_mem_base == 0)
                                         isa_mem_base = cpu_addr;
                                 hose->isa_mem_phys = cpu_addr;
@@ -839,6 +827,7 @@ static void pcibios_fixup_resources(struct pci_dev *dev)
         }
         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
                 struct resource *res = dev->resource + i;
+                struct pci_bus_region reg;
                 if (!res->flags)
                         continue;
 
@@ -847,8 +836,9 @@ static void pcibios_fixup_resources(struct pci_dev *dev)
                  * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
                  * since in that case, we don't want to re-assign anything
                  */
+                pcibios_resource_to_bus(dev, &reg, res);
                 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
-                    (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
+                    (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
                         /* Only print message if not re-assigning */
                         if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
                                 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index a902723fdc69..076d1242507a 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -399,7 +399,8 @@ static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 {
         mtspr(SPRN_DABR, dabr);
-        mtspr(SPRN_DABRX, dabrx);
+        if (cpu_has_feature(CPU_FTR_DABRX))
+                mtspr(SPRN_DABRX, dabrx);
         return 0;
 }
 #else
@@ -1368,7 +1369,7 @@ void show_stack(struct task_struct *tsk, unsigned long *stack)
 
 #ifdef CONFIG_PPC64
 /* Called with hard IRQs off */
-void __ppc64_runlatch_on(void)
+void notrace __ppc64_runlatch_on(void)
 {
         struct thread_info *ti = current_thread_info();
         unsigned long ctrl;
@@ -1381,7 +1382,7 @@ void __ppc64_runlatch_on(void)
 }
 
 /* Called with hard IRQs off */
-void __ppc64_runlatch_off(void)
+void notrace __ppc64_runlatch_off(void)
 {
         struct thread_info *ti = current_thread_info();
         unsigned long ctrl;
diff --git a/arch/powerpc/kernel/signal.c b/arch/powerpc/kernel/signal.c
index 577a8aa69c6e..457e97aa2945 100644
--- a/arch/powerpc/kernel/signal.c
+++ b/arch/powerpc/kernel/signal.c
@@ -18,6 +18,7 @@
 #include <asm/uaccess.h>
 #include <asm/unistd.h>
 #include <asm/debug.h>
+#include <asm/tm.h>
 
 #include "signal.h"
 
@@ -30,13 +31,13 @@ int show_unhandled_signals = 1;
 /*
  * Allocate space for the signal frame
  */
-void __user * get_sigframe(struct k_sigaction *ka, struct pt_regs *regs,
+void __user * get_sigframe(struct k_sigaction *ka, unsigned long sp,
                            size_t frame_size, int is_32)
 {
         unsigned long oldsp, newsp;
 
         /* Default to using normal stack */
-        oldsp = get_clean_sp(regs, is_32);
+        oldsp = get_clean_sp(sp, is_32);
 
         /* Check for alt stack */
         if ((ka->sa.sa_flags & SA_ONSTACK) &&
@@ -175,3 +176,38 @@ void do_notify_resume(struct pt_regs *regs, unsigned long thread_info_flags)
 
         user_enter();
 }
+
+unsigned long get_tm_stackpointer(struct pt_regs *regs)
+{
+        /* When in an active transaction that takes a signal, we need to be
+         * careful with the stack.  It's possible that the stack has moved back
+         * up after the tbegin.  The obvious case here is when the tbegin is
+         * called inside a function that returns before a tend.  In this case,
+         * the stack is part of the checkpointed transactional memory state.
+         * If we write over this non transactionally or in suspend, we are in
+         * trouble because if we get a tm abort, the program counter and stack
+         * pointer will be back at the tbegin but our in memory stack won't be
+         * valid anymore.
+         *
+         * To avoid this, when taking a signal in an active transaction, we
+         * need to use the stack pointer from the checkpointed state, rather
+         * than the speculated state.  This ensures that the signal context
+         * (written tm suspended) will be written below the stack required for
+         * the rollback.  The transaction is aborted becuase of the treclaim,
+         * so any memory written between the tbegin and the signal will be
+         * rolled back anyway.
+         *
+         * For signals taken in non-TM or suspended mode, we use the
+         * normal/non-checkpointed stack pointer.
+         */
+
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+        if (MSR_TM_ACTIVE(regs->msr)) {
+                tm_enable();
+                tm_reclaim(&current->thread, regs->msr, TM_CAUSE_SIGNAL);
+                if (MSR_TM_TRANSACTIONAL(regs->msr))
+                        return current->thread.ckpt_regs.gpr[1];
+        }
+#endif
+        return regs->gpr[1];
+}
diff --git a/arch/powerpc/kernel/signal.h b/arch/powerpc/kernel/signal.h
index ec84c901ceab..c69b9aeb9f23 100644
--- a/arch/powerpc/kernel/signal.h
+++ b/arch/powerpc/kernel/signal.h
@@ -12,7 +12,7 @@
 
 extern void do_notify_resume(struct pt_regs *regs, unsigned long thread_info_flags);
 
-extern void __user * get_sigframe(struct k_sigaction *ka, struct pt_regs *regs,
+extern void __user * get_sigframe(struct k_sigaction *ka, unsigned long sp,
                                   size_t frame_size, int is_32);
 
 extern int handle_signal32(unsigned long sig, struct k_sigaction *ka,
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index 95068bf569ad..201385c3a1ae 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -503,12 +503,6 @@ static int save_tm_user_regs(struct pt_regs *regs,
 {
         unsigned long msr = regs->msr;
 
-        /* tm_reclaim rolls back all reg states, updating thread.ckpt_regs,
-         * thread.transact_fpr[], thread.transact_vr[], etc.
-         */
-        tm_enable();
-        tm_reclaim(&current->thread, msr, TM_CAUSE_SIGNAL);
-
         /* Make sure floating point registers are stored in regs */
         flush_fp_to_thread(current);
 
@@ -965,7 +959,7 @@ int handle_rt_signal32(unsigned long sig, struct k_sigaction *ka,
 
         /* Set up Signal Frame */
         /* Put a Real Time Context onto stack */
-        rt_sf = get_sigframe(ka, regs, sizeof(*rt_sf), 1);
+        rt_sf = get_sigframe(ka, get_tm_stackpointer(regs), sizeof(*rt_sf), 1);
         addr = rt_sf;
         if (unlikely(rt_sf == NULL))
                 goto badframe;
@@ -1403,7 +1397,7 @@ int handle_signal32(unsigned long sig, struct k_sigaction *ka,
         unsigned long tramp;
 
         /* Set up Signal Frame */
-        frame = get_sigframe(ka, regs, sizeof(*frame), 1);
+        frame = get_sigframe(ka, get_tm_stackpointer(regs), sizeof(*frame), 1);
         if (unlikely(frame == NULL))
                 goto badframe;
         sc = (struct sigcontext __user *) &frame->sctx;
diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c
index c1794286098c..345947367ec0 100644
--- a/arch/powerpc/kernel/signal_64.c
+++ b/arch/powerpc/kernel/signal_64.c
@@ -154,11 +154,12 @@ static long setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs,
  * As above, but Transactional Memory is in use, so deliver sigcontexts
  * containing checkpointed and transactional register states.
  *
- * To do this, we treclaim to gather both sets of registers and set up the
- * 'normal' sigcontext registers with rolled-back register values such that a
- * simple signal handler sees a correct checkpointed register state.
- * If interested, a TM-aware sighandler can examine the transactional registers
- * in the 2nd sigcontext to determine the real origin of the signal.
+ * To do this, we treclaim (done before entering here) to gather both sets of
+ * registers and set up the 'normal' sigcontext registers with rolled-back
+ * register values such that a simple signal handler sees a correct
+ * checkpointed register state.  If interested, a TM-aware sighandler can
+ * examine the transactional registers in the 2nd sigcontext to determine the
+ * real origin of the signal.
  */
 static long setup_tm_sigcontexts(struct sigcontext __user *sc,
                                  struct sigcontext __user *tm_sc,
@@ -184,16 +185,6 @@ static long setup_tm_sigcontexts(struct sigcontext __user *sc,
 
         BUG_ON(!MSR_TM_ACTIVE(regs->msr));
 
-        /* tm_reclaim rolls back all reg states, saving checkpointed (older)
-         * GPRs to thread.ckpt_regs and (if used) FPRs to (newer)
-         * thread.transact_fp and/or VRs to (newer) thread.transact_vr.
-         * THEN we save out FP/VRs, if necessary, to the checkpointed (older)
-         * thread.fr[]/vr[]s.  The transactional (newer) GPRs are on the
-         * stack, in *regs.
-         */
-        tm_enable();
-        tm_reclaim(&current->thread, msr, TM_CAUSE_SIGNAL);
-
         flush_fp_to_thread(current);
 
 #ifdef CONFIG_ALTIVEC
@@ -711,7 +702,7 @@ int handle_rt_signal64(int signr, struct k_sigaction *ka, siginfo_t *info,
         unsigned long newsp = 0;
         long err = 0;
 
-        frame = get_sigframe(ka, regs, sizeof(*frame), 0);
+        frame = get_sigframe(ka, get_tm_stackpointer(regs), sizeof(*frame), 0);
         if (unlikely(frame == NULL))
                 goto badframe;
 
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index a7a648f6b750..c0e5caf8ccc7 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -53,6 +53,7 @@
 #ifdef CONFIG_PPC64
 #include <asm/firmware.h>
 #include <asm/processor.h>
+#include <asm/tm.h>
 #endif
 #include <asm/kexec.h>
 #include <asm/ppc-opcode.h>
@@ -932,6 +933,28 @@ static int emulate_isel(struct pt_regs *regs, u32 instword)
         return 0;
 }
 
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+static inline bool tm_abort_check(struct pt_regs *regs, int cause)
+{
+        /* If we're emulating a load/store in an active transaction, we cannot
+         * emulate it as the kernel operates in transaction suspended context.
+         * We need to abort the transaction.  This creates a persistent TM
+         * abort so tell the user what caused it with a new code.
+         */
+        if (MSR_TM_TRANSACTIONAL(regs->msr)) {
+                tm_enable();
+                tm_abort(cause);
+                return true;
+        }
+        return false;
+}
+#else
+static inline bool tm_abort_check(struct pt_regs *regs, int reason)
+{
+        return false;
+}
+#endif
+
 static int emulate_instruction(struct pt_regs *regs)
 {
         u32 instword;
@@ -971,6 +994,9 @@ static int emulate_instruction(struct pt_regs *regs)
 
         /* Emulate load/store string insn. */
         if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
+                if (tm_abort_check(regs,
+                                   TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
+                        return -EINVAL;
                 PPC_WARN_EMULATED(string, regs);
                 return emulate_string_inst(regs, instword);
         }
@@ -1139,6 +1165,16 @@ bail:
         exception_exit(prev_state);
 }
 
+/*
+ * This occurs when running in hypervisor mode on POWER6 or later
+ * and an illegal instruction is encountered.
+ */
+void __kprobes emulation_assist_interrupt(struct pt_regs *regs)
+{
+        regs->msr |= REASON_ILLEGAL;
+        program_check_exception(regs);
+}
+
 void alignment_exception(struct pt_regs *regs)
 {
         enum ctx_state prev_state = exception_enter();
@@ -1148,6 +1184,9 @@ void alignment_exception(struct pt_regs *regs)
         if (!arch_irq_disabled_regs(regs))
                 local_irq_enable();
 
+        if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
+                goto bail;
+
         /* we don't implement logging of alignment exceptions */
         if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
                 fixed = fix_alignment(regs);
diff --git a/arch/powerpc/kvm/44x_tlb.c b/arch/powerpc/kvm/44x_tlb.c
index 5dd3ab469976..ed0385448148 100644
--- a/arch/powerpc/kvm/44x_tlb.c
+++ b/arch/powerpc/kvm/44x_tlb.c
@@ -441,6 +441,7 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
         struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
         struct kvmppc_44x_tlbe *tlbe;
         unsigned int gtlb_index;
+        int idx;
 
         gtlb_index = kvmppc_get_gpr(vcpu, ra);
         if (gtlb_index >= KVM44x_GUEST_TLB_SIZE) {
@@ -473,6 +474,8 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
                 return EMULATE_FAIL;
         }
 
+        idx = srcu_read_lock(&vcpu->kvm->srcu);
+
         if (tlbe_is_host_safe(vcpu, tlbe)) {
                 gva_t eaddr;
                 gpa_t gpaddr;
@@ -489,6 +492,8 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
                 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
         }
 
+        srcu_read_unlock(&vcpu->kvm->srcu, idx);
+
         trace_kvm_gtlb_write(gtlb_index, tlbe->tid, tlbe->word0, tlbe->word1,
                              tlbe->word2);
 
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 9de24f8e03c7..550f5928b394 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -562,6 +562,8 @@ int kvmppc_pseries_do_hcall(struct kvm_vcpu *vcpu)
         case H_CPPR:
         case H_EOI:
         case H_IPI:
+        case H_IPOLL:
+        case H_XIRR_X:
                 if (kvmppc_xics_enabled(vcpu)) {
                         ret = kvmppc_xics_hcall(vcpu, req);
                         break;
diff --git a/arch/powerpc/kvm/book3s_pr_papr.c b/arch/powerpc/kvm/book3s_pr_papr.c
index b24309c6c2d5..da0e0bc268bd 100644
--- a/arch/powerpc/kvm/book3s_pr_papr.c
+++ b/arch/powerpc/kvm/book3s_pr_papr.c
@@ -257,6 +257,8 @@ int kvmppc_h_pr(struct kvm_vcpu *vcpu, unsigned long cmd)
         case H_CPPR:
         case H_EOI:
         case H_IPI:
+        case H_IPOLL:
+        case H_XIRR_X:
                 if (kvmppc_xics_enabled(vcpu))
                         return kvmppc_h_pr_xics_hcall(vcpu, cmd);
                 break;
diff --git a/arch/powerpc/kvm/book3s_xics.c b/arch/powerpc/kvm/book3s_xics.c
index f7a103756618..94c1dd46b83d 100644
--- a/arch/powerpc/kvm/book3s_xics.c
+++ b/arch/powerpc/kvm/book3s_xics.c
@@ -650,6 +650,23 @@ static noinline int kvmppc_h_ipi(struct kvm_vcpu *vcpu, unsigned long server,
         return H_SUCCESS;
 }
 
+static int kvmppc_h_ipoll(struct kvm_vcpu *vcpu, unsigned long server)
+{
+        union kvmppc_icp_state state;
+        struct kvmppc_icp *icp;
+
+        icp = vcpu->arch.icp;
+        if (icp->server_num != server) {
+                icp = kvmppc_xics_find_server(vcpu->kvm, server);
+                if (!icp)
+                        return H_PARAMETER;
+        }
+        state = ACCESS_ONCE(icp->state);
+        kvmppc_set_gpr(vcpu, 4, ((u32)state.cppr << 24) | state.xisr);
+        kvmppc_set_gpr(vcpu, 5, state.mfrr);
+        return H_SUCCESS;
+}
+
 static noinline void kvmppc_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr)
 {
         union kvmppc_icp_state old_state, new_state;
@@ -787,6 +804,18 @@ int kvmppc_xics_hcall(struct kvm_vcpu *vcpu, u32 req)
         if (!xics || !vcpu->arch.icp)
                 return H_HARDWARE;
 
+        /* These requests don't have real-mode implementations at present */
+        switch (req) {
+        case H_XIRR_X:
+                res = kvmppc_h_xirr(vcpu);
+                kvmppc_set_gpr(vcpu, 4, res);
+                kvmppc_set_gpr(vcpu, 5, get_tb());
+                return rc;
+        case H_IPOLL:
+                rc = kvmppc_h_ipoll(vcpu, kvmppc_get_gpr(vcpu, 4));
+                return rc;
+        }
+
         /* Check for real mode returning too hard */
         if (xics->real_mode)
                 return kvmppc_xics_rm_complete(vcpu, req);
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index 1020119226db..5cd7ad0c1176 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -832,6 +832,18 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
 {
         int r = RESUME_HOST;
         int s;
+        int idx;
+
+#ifdef CONFIG_PPC64
+        WARN_ON(local_paca->irq_happened != 0);
+#endif
+
+        /*
+         * We enter with interrupts disabled in hardware, but
+         * we need to call hard_irq_disable anyway to ensure that
+         * the software state is kept in sync.
+         */
+        hard_irq_disable();
 
         /* update before a new last_exit_type is rewritten */
         kvmppc_update_timing_stats(vcpu);
@@ -1053,6 +1065,8 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
                         break;
                 }
 
+                idx = srcu_read_lock(&vcpu->kvm->srcu);
+
                 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
                 gfn = gpaddr >> PAGE_SHIFT;
 
@@ -1075,6 +1089,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
                         kvmppc_account_exit(vcpu, MMIO_EXITS);
                 }
 
+                srcu_read_unlock(&vcpu->kvm->srcu, idx);
                 break;
         }
 
@@ -1098,6 +1113,8 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
 
                 kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS);
 
+                idx = srcu_read_lock(&vcpu->kvm->srcu);
+
                 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
                 gfn = gpaddr >> PAGE_SHIFT;
 
@@ -1114,6 +1131,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
                         kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK);
                 }
 
+                srcu_read_unlock(&vcpu->kvm->srcu, idx);
                 break;
         }
 
diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc/kvm/e500_mmu.c
index c41a5a96b558..6d6f153b6c1d 100644
--- a/arch/powerpc/kvm/e500_mmu.c
+++ b/arch/powerpc/kvm/e500_mmu.c
@@ -396,6 +396,7 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
         struct kvm_book3e_206_tlb_entry *gtlbe;
         int tlbsel, esel;
         int recal = 0;
+        int idx;
 
         tlbsel = get_tlb_tlbsel(vcpu);
         esel = get_tlb_esel(vcpu, tlbsel);
@@ -430,6 +431,8 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
                         kvmppc_set_tlb1map_range(vcpu, gtlbe);
         }
 
+        idx = srcu_read_lock(&vcpu->kvm->srcu);
+
         /* Invalidate shadow mappings for the about-to-be-clobbered TLBE. */
         if (tlbe_is_host_safe(vcpu, gtlbe)) {
                 u64 eaddr = get_tlb_eaddr(gtlbe);
@@ -444,6 +447,8 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
                 kvmppc_mmu_map(vcpu, eaddr, raddr, index_of(tlbsel, esel));
         }
 
+        srcu_read_unlock(&vcpu->kvm->srcu, idx);
+
         kvmppc_set_exit_type(vcpu, EMULATED_TLBWE_EXITS);
         return EMULATE_DONE;
 }
diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index 753cc99eff2b..19c8379575f7 100644
--- a/arch/powerpc/kvm/e500mc.c
+++ b/arch/powerpc/kvm/e500mc.c
@@ -177,8 +177,6 @@ int kvmppc_core_check_processor_compat(void)
                 r = 0;
         else if (strcmp(cur_cpu_spec->cpu_name, "e5500") == 0)
                 r = 0;
-        else if (strcmp(cur_cpu_spec->cpu_name, "e6500") == 0)
-                r = 0;
         else
                 r = -ENOTSUPP;
 
diff --git a/arch/powerpc/lib/copypage_power7.S b/arch/powerpc/lib/copypage_power7.S
index 0ef75bf0695c..395c594722a2 100644
--- a/arch/powerpc/lib/copypage_power7.S
+++ b/arch/powerpc/lib/copypage_power7.S
@@ -28,13 +28,14 @@ _GLOBAL(copypage_power7)
          * aligned we don't need to clear the bottom 7 bits of either
          * address.
          */
-        ori     r9,r3,1         /* stream=1 */
+        ori     r9,r3,1         /* stream=1 => to */
 
 #ifdef CONFIG_PPC_64K_PAGES
-        lis     r7,0x0E01       /* depth=7, units=512 */
+        lis     r7,0x0E01       /* depth=7
+                                 * units/cachelines=512 */
 #else
         lis     r7,0x0E00       /* depth=7 */
-        ori     r7,r7,0x1000    /* units=32 */
+        ori     r7,r7,0x1000    /* units/cachelines=32 */
 #endif
         ori     r10,r7,1        /* stream=1 */
 
@@ -43,12 +44,14 @@ _GLOBAL(copypage_power7)
 
 .machine push
 .machine "power4"
-        dcbt    r0,r4,0b01000
-        dcbt    r0,r7,0b01010
-        dcbtst  r0,r9,0b01000
-        dcbtst  r0,r10,0b01010
+        /* setup read stream 0  */
+        dcbt    r0,r4,0b01000   /* addr from */
+        dcbt    r0,r7,0b01010   /* length and depth from */
+        /* setup write stream 1 */
+        dcbtst  r0,r9,0b01000   /* addr to */
+        dcbtst  r0,r10,0b01010  /* length and depth to */
         eieio
-        dcbt    r0,r8,0b01010   /* GO */
+        dcbt    r0,r8,0b01010   /* all streams GO */
 .machine pop
 
 #ifdef CONFIG_ALTIVEC
diff --git a/arch/powerpc/lib/copyuser_power7.S b/arch/powerpc/lib/copyuser_power7.S
index 0d24ff15f5f6..d1f11795a7ad 100644
--- a/arch/powerpc/lib/copyuser_power7.S
+++ b/arch/powerpc/lib/copyuser_power7.S
@@ -318,12 +318,14 @@ err1;	stb	r0,0(r3)
 
 .machine push
 .machine "power4"
-        dcbt    r0,r6,0b01000
-        dcbt    r0,r7,0b01010
-        dcbtst  r0,r9,0b01000
-        dcbtst  r0,r10,0b01010
+        /* setup read stream 0 */
+        dcbt    r0,r6,0b01000   /* addr from */
+        dcbt    r0,r7,0b01010   /* length and depth from */
+        /* setup write stream 1 */
+        dcbtst  r0,r9,0b01000   /* addr to */
+        dcbtst  r0,r10,0b01010  /* length and depth to */
         eieio
-        dcbt    r0,r8,0b01010   /* GO */
+        dcbt    r0,r8,0b01010   /* all streams GO */
 .machine pop
 
         beq     cr1,.Lunwind_stack_nonvmx_copy
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 6a2aead5b0e5..4c122c3f1623 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -336,11 +336,18 @@ static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
 
         hpte_v = hptep->v;
         actual_psize = hpte_actual_psize(hptep, psize);
+        /*
+         * We need to invalidate the TLB always because hpte_remove doesn't do
+         * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
+         * random entry from it. When we do that we don't invalidate the TLB
+         * (hpte_remove) because we assume the old translation is still
+         * technically "valid".
+         */
         if (actual_psize < 0) {
-                native_unlock_hpte(hptep);
-                return -1;
+                actual_psize = psize;
+                ret = -1;
+                goto err_out;
         }
-        /* Even if we miss, we need to invalidate the TLB */
         if (!HPTE_V_COMPARE(hpte_v, want_v)) {
                 DBG_LOW(" -> miss\n");
                 ret = -1;
@@ -350,6 +357,7 @@ static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
                 hptep->r = (hptep->r & ~(HPTE_R_PP | HPTE_R_N)) |
                         (newpp & (HPTE_R_PP | HPTE_R_N | HPTE_R_C));
         }
+err_out:
         native_unlock_hpte(hptep);
 
         /* Ensure it is out of the tlb too. */
@@ -409,7 +417,7 @@ static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
         hptep = htab_address + slot;
         actual_psize = hpte_actual_psize(hptep, psize);
         if (actual_psize < 0)
-                return;
+                actual_psize = psize;
 
         /* Update the HPTE */
         hptep->r = (hptep->r & ~(HPTE_R_PP | HPTE_R_N)) |
@@ -437,21 +445,27 @@ static void native_hpte_invalidate(unsigned long slot, unsigned long vpn,
         hpte_v = hptep->v;
 
         actual_psize = hpte_actual_psize(hptep, psize);
+        /*
+         * We need to invalidate the TLB always because hpte_remove doesn't do
+         * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
+         * random entry from it. When we do that we don't invalidate the TLB
+         * (hpte_remove) because we assume the old translation is still
+         * technically "valid".
+         */
         if (actual_psize < 0) {
+                actual_psize = psize;
                 native_unlock_hpte(hptep);
-                local_irq_restore(flags);
-                return;
+                goto err_out;
         }
-        /* Even if we miss, we need to invalidate the TLB */
         if (!HPTE_V_COMPARE(hpte_v, want_v))
                 native_unlock_hpte(hptep);
         else
                 /* Invalidate the hpte. NOTE: this also unlocks it */
                 hptep->v = 0;
 
+err_out:
         /* Invalidate the TLB */
         tlbie(vpn, psize, actual_psize, ssize, local);
-
         local_irq_restore(flags);
 }
 
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 426180b84978..29c6482890c8 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -110,7 +110,7 @@ static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {}
 
 static bool regs_use_siar(struct pt_regs *regs)
 {
-        return !!(regs->result & 1);
+        return !!regs->result;
 }
 
 /*
@@ -136,22 +136,30 @@ static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
  * If we're not doing instruction sampling, give them the SDAR
  * (sampled data address).  If we are doing instruction sampling, then
  * only give them the SDAR if it corresponds to the instruction
- * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC or
- * the [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA.
+ * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the
+ * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER.
  */
 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp)
 {
         unsigned long mmcra = regs->dsisr;
-        unsigned long sdsync;
+        bool sdar_valid;
 
-        if (ppmu->flags & PPMU_SIAR_VALID)
-                sdsync = POWER7P_MMCRA_SDAR_VALID;
-        else if (ppmu->flags & PPMU_ALT_SIPR)
-                sdsync = POWER6_MMCRA_SDSYNC;
-        else
-                sdsync = MMCRA_SDSYNC;
+        if (ppmu->flags & PPMU_HAS_SIER)
+                sdar_valid = regs->dar & SIER_SDAR_VALID;
+        else {
+                unsigned long sdsync;
+
+                if (ppmu->flags & PPMU_SIAR_VALID)
+                        sdsync = POWER7P_MMCRA_SDAR_VALID;
+                else if (ppmu->flags & PPMU_ALT_SIPR)
+                        sdsync = POWER6_MMCRA_SDSYNC;
+                else
+                        sdsync = MMCRA_SDSYNC;
+
+                sdar_valid = mmcra & sdsync;
+        }
 
-        if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync))
+        if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid)
                 *addrp = mfspr(SPRN_SDAR);
 }
 
@@ -181,11 +189,6 @@ static bool regs_sipr(struct pt_regs *regs)
         return !!(regs->dsisr & sipr);
 }
 
-static bool regs_no_sipr(struct pt_regs *regs)
-{
-        return !!(regs->result & 2);
-}
-
 static inline u32 perf_flags_from_msr(struct pt_regs *regs)
 {
         if (regs->msr & MSR_PR)
@@ -208,7 +211,7 @@ static inline u32 perf_get_misc_flags(struct pt_regs *regs)
          * SIAR which should give slightly more reliable
          * results
          */
-        if (regs_no_sipr(regs)) {
+        if (ppmu->flags & PPMU_NO_SIPR) {
                 unsigned long siar = mfspr(SPRN_SIAR);
                 if (siar >= PAGE_OFFSET)
                         return PERF_RECORD_MISC_KERNEL;
@@ -239,22 +242,9 @@ static inline void perf_read_regs(struct pt_regs *regs)
         int use_siar;
 
         regs->dsisr = mmcra;
-        regs->result = 0;
-
-        if (ppmu->flags & PPMU_NO_SIPR)
-                regs->result |= 2;
-
-        /*
-         * On power8 if we're in random sampling mode, the SIER is updated.
-         * If we're in continuous sampling mode, we don't have SIPR.
-         */
-        if (ppmu->flags & PPMU_HAS_SIER) {
-                if (marked)
-                        regs->dar = mfspr(SPRN_SIER);
-                else
-                        regs->result |= 2;
-        }
 
+        if (ppmu->flags & PPMU_HAS_SIER)
+                regs->dar = mfspr(SPRN_SIER);
 
         /*
          * If this isn't a PMU exception (eg a software event) the SIAR is
@@ -279,12 +269,12 @@ static inline void perf_read_regs(struct pt_regs *regs)
                 use_siar = 1;
         else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING))
                 use_siar = 0;
-        else if (!regs_no_sipr(regs) && regs_sipr(regs))
+        else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs))
                 use_siar = 0;
         else
                 use_siar = 1;
 
-        regs->result |= use_siar;
+        regs->result = use_siar;
 }
 
 /*
@@ -308,8 +298,13 @@ static inline int siar_valid(struct pt_regs *regs)
         unsigned long mmcra = regs->dsisr;
         int marked = mmcra & MMCRA_SAMPLE_ENABLE;
 
-        if ((ppmu->flags & PPMU_SIAR_VALID) && marked)
-                return mmcra & POWER7P_MMCRA_SIAR_VALID;
+        if (marked) {
+                if (ppmu->flags & PPMU_HAS_SIER)
+                        return regs->dar & SIER_SIAR_VALID;
+
+                if (ppmu->flags & PPMU_SIAR_VALID)
+                        return mmcra & POWER7P_MMCRA_SIAR_VALID;
+        }
 
         return 1;
 }
@@ -1763,7 +1758,7 @@ static void perf_event_interrupt(struct pt_regs *regs)
                         }
                 }
         }
-        if ((!found) && printk_ratelimit())
+        if (!found && !nmi && printk_ratelimit())
                 printk(KERN_WARNING "Can't find PMC that caused IRQ\n");
 
         /*
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index 023b288f895b..4459eff7a75a 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -19,6 +19,8 @@ config PPC_PSERIES
         select ZLIB_DEFLATE
         select PPC_DOORBELL
         select HAVE_CONTEXT_TRACKING
+        select HOTPLUG if SMP
+        select HOTPLUG_CPU if SMP
         default y
 
 config PPC_SPLPAR
diff --git a/arch/powerpc/platforms/pseries/eeh_pseries.c b/arch/powerpc/platforms/pseries/eeh_pseries.c
index 19506f935737..b456b157d33d 100644
--- a/arch/powerpc/platforms/pseries/eeh_pseries.c
+++ b/arch/powerpc/platforms/pseries/eeh_pseries.c
@@ -83,7 +83,11 @@ static int pseries_eeh_init(void)
         ibm_configure_pe                = rtas_token("ibm,configure-pe");
         ibm_configure_bridge            = rtas_token("ibm,configure-bridge");
 
-        /* necessary sanity check */
+        /*
+         * Necessary sanity check. We needn't check "get-config-addr-info"
+         * and its variant since the old firmware probably support address
+         * of domain/bus/slot/function for EEH RTAS operations.
+         */
         if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) {
                 pr_warning("%s: RTAS service <ibm,set-eeh-option> invalid\n",
                         __func__);
@@ -102,12 +106,6 @@ static int pseries_eeh_init(void)
                 pr_warning("%s: RTAS service <ibm,slot-error-detail> invalid\n",
                         __func__);
                 return -EINVAL;
-        } else if (ibm_get_config_addr_info2 == RTAS_UNKNOWN_SERVICE &&
-                   ibm_get_config_addr_info == RTAS_UNKNOWN_SERVICE) {
-                pr_warning("%s: RTAS service <ibm,get-config-addr-info2> and "
-                        "<ibm,get-config-addr-info> invalid\n",
-                        __func__);
-                return -EINVAL;
         } else if (ibm_configure_pe == RTAS_UNKNOWN_SERVICE &&
                    ibm_configure_bridge == RTAS_UNKNOWN_SERVICE) {
                 pr_warning("%s: RTAS service <ibm,configure-pe> and "
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 0a13ecb270c7..3cc2f9159ab1 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -54,7 +54,7 @@ static DEFINE_RAW_SPINLOCK(mpic_lock);
 
 #ifdef CONFIG_PPC32     /* XXX for now */
 #ifdef CONFIG_IRQ_ALL_CPUS
-#define distribute_irqs (!(mpic->flags & MPIC_SINGLE_DEST_CPU))
+#define distribute_irqs (1)
 #else
 #define distribute_irqs (0)
 #endif
@@ -1703,7 +1703,7 @@ void mpic_setup_this_cpu(void)
          * it differently, then we should make sure we also change the default
          * values of irq_desc[].affinity in irq.c.
          */
-        if (distribute_irqs) {
+        if (distribute_irqs && !(mpic->flags & MPIC_SINGLE_DEST_CPU)) {
                 for (i = 0; i < mpic->num_sources ; i++)
                         mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
                                 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
diff --git a/arch/s390/appldata/appldata_base.c b/arch/s390/appldata/appldata_base.c
index bae0f402bf2a..87a22092b68f 100644
--- a/arch/s390/appldata/appldata_base.c
+++ b/arch/s390/appldata/appldata_base.c
@@ -212,7 +212,9 @@ appldata_timer_handler(ctl_table *ctl, int write,
                 return 0;
         }
         if (!write) {
-                len = sprintf(buf, appldata_timer_active ? "1\n" : "0\n");
+                strncpy(buf, appldata_timer_active ? "1\n" : "0\n",
+                        ARRAY_SIZE(buf));
+                len = strnlen(buf, ARRAY_SIZE(buf));
                 if (len > *lenp)
                         len = *lenp;
                 if (copy_to_user(buffer, buf, len))
@@ -317,7 +319,8 @@ appldata_generic_handler(ctl_table *ctl, int write,
                 return 0;
         }
         if (!write) {
-                len = sprintf(buf, ops->active ? "1\n" : "0\n");
+                strncpy(buf, ops->active ? "1\n" : "0\n", ARRAY_SIZE(buf));
+                len = strnlen(buf, ARRAY_SIZE(buf));
                 if (len > *lenp)
                         len = *lenp;
                 if (copy_to_user(buffer, buf, len)) {
diff --git a/arch/s390/include/asm/dma-mapping.h b/arch/s390/include/asm/dma-mapping.h
index 9411db653bac..886ac7d4937a 100644
--- a/arch/s390/include/asm/dma-mapping.h
+++ b/arch/s390/include/asm/dma-mapping.h
@@ -71,8 +71,8 @@ static inline void dma_free_coherent(struct device *dev, size_t size,
 {
         struct dma_map_ops *dma_ops = get_dma_ops(dev);
 
-        dma_ops->free(dev, size, cpu_addr, dma_handle, NULL);
         debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
+        dma_ops->free(dev, size, cpu_addr, dma_handle, NULL);
 }
 
 #endif /* _ASM_S390_DMA_MAPPING_H */
diff --git a/arch/s390/include/asm/io.h b/arch/s390/include/asm/io.h
index 379d96e2105e..fd9be010f9b2 100644
--- a/arch/s390/include/asm/io.h
+++ b/arch/s390/include/asm/io.h
@@ -36,6 +36,7 @@ static inline void * phys_to_virt(unsigned long address)
 }
 
 void *xlate_dev_mem_ptr(unsigned long phys);
+#define xlate_dev_mem_ptr xlate_dev_mem_ptr
 void unxlate_dev_mem_ptr(unsigned long phys, void *addr);
 
 /*
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index 0f0de30e3e3f..e8b6e5b8932c 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -623,7 +623,7 @@ static inline pgste_t pgste_get_lock(pte_t *ptep)
                 "       csg     %0,%1,%2\n"
                 "       jl      0b\n"
                 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE])
-                : "Q" (ptep[PTRS_PER_PTE]) : "cc");
+                : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory");
 #endif
         return __pgste(new);
 }
@@ -635,18 +635,26 @@ static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste)
                 "       nihh    %1,0xff7f\n"    /* clear RCP_PCL_BIT */
                 "       stg     %1,%0\n"
                 : "=Q" (ptep[PTRS_PER_PTE])
-                : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) : "cc");
+                : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE])
+                : "cc", "memory");
         preempt_enable();
 #endif
 }
 
+static inline void pgste_set(pte_t *ptep, pgste_t pgste)
+{
+#ifdef CONFIG_PGSTE
+        *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste;
+#endif
+}
+
 static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste)
 {
 #ifdef CONFIG_PGSTE
         unsigned long address, bits;
         unsigned char skey;
 
-        if (!pte_present(*ptep))
+        if (pte_val(*ptep) & _PAGE_INVALID)
                 return pgste;
         address = pte_val(*ptep) & PAGE_MASK;
         skey = page_get_storage_key(address);
@@ -680,7 +688,7 @@ static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste)
 #ifdef CONFIG_PGSTE
         int young;
 
-        if (!pte_present(*ptep))
+        if (pte_val(*ptep) & _PAGE_INVALID)
                 return pgste;
         /* Get referenced bit from storage key */
         young = page_reset_referenced(pte_val(*ptep) & PAGE_MASK);
@@ -704,17 +712,19 @@ static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry)
 {
 #ifdef CONFIG_PGSTE
         unsigned long address;
-        unsigned long okey, nkey;
+        unsigned long nkey;
 
-        if (!pte_present(entry))
+        if (pte_val(entry) & _PAGE_INVALID)
                 return;
+        VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID));
         address = pte_val(entry) & PAGE_MASK;
-        okey = nkey = page_get_storage_key(address);
-        nkey &= ~(_PAGE_ACC_BITS | _PAGE_FP_BIT);
-        /* Set page access key and fetch protection bit from pgste */
-        nkey |= (pgste_val(pgste) & (RCP_ACC_BITS | RCP_FP_BIT)) >> 56;
-        if (okey != nkey)
-                page_set_storage_key(address, nkey, 0);
+        /*
+         * Set page access key and fetch protection bit from pgste.
+         * The guest C/R information is still in the PGSTE, set real
+         * key C/R to 0.
+         */
+        nkey = (pgste_val(pgste) & (RCP_ACC_BITS | RCP_FP_BIT)) >> 56;
+        page_set_storage_key(address, nkey, 0);
 #endif
 }
 
@@ -1098,6 +1108,11 @@ static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
         pte = *ptep;
         if (!mm_exclusive(mm))
                 __ptep_ipte(address, ptep);
+
+        if (mm_has_pgste(mm)) {
+                pgste = pgste_update_all(&pte, pgste);
+                pgste_set(ptep, pgste);
+        }
         return pte;
 }
 
@@ -1105,9 +1120,13 @@ static inline void ptep_modify_prot_commit(struct mm_struct *mm,
                                            unsigned long address,
                                            pte_t *ptep, pte_t pte)
 {
+        pgste_t pgste;
+
         if (mm_has_pgste(mm)) {
+                pgste = *(pgste_t *)(ptep + PTRS_PER_PTE);
+                pgste_set_key(ptep, pgste, pte);
                 pgste_set_pte(ptep, pte);
-                pgste_set_unlock(ptep, *(pgste_t *)(ptep + PTRS_PER_PTE));
+                pgste_set_unlock(ptep, pgste);
         } else
                 *ptep = pte;
 }
diff --git a/arch/s390/kernel/dumpstack.c b/arch/s390/kernel/dumpstack.c
index 298297477257..87acc38f73c6 100644
--- a/arch/s390/kernel/dumpstack.c
+++ b/arch/s390/kernel/dumpstack.c
@@ -74,6 +74,8 @@ __show_trace(unsigned long sp, unsigned long low, unsigned long high)
 
 static void show_trace(struct task_struct *task, unsigned long *stack)
 {
+        const unsigned long frame_size =
+                STACK_FRAME_OVERHEAD + sizeof(struct pt_regs);
         register unsigned long __r15 asm ("15");
         unsigned long sp;
 
@@ -82,11 +84,13 @@ static void show_trace(struct task_struct *task, unsigned long *stack)
                 sp = task ? task->thread.ksp : __r15;
         printk("Call Trace:\n");
 #ifdef CONFIG_CHECK_STACK
-        sp = __show_trace(sp, S390_lowcore.panic_stack - 4096,
-                          S390_lowcore.panic_stack);
+        sp = __show_trace(sp,
+                          S390_lowcore.panic_stack + frame_size - 4096,
+                          S390_lowcore.panic_stack + frame_size);
 #endif
-        sp = __show_trace(sp, S390_lowcore.async_stack - ASYNC_SIZE,
-                          S390_lowcore.async_stack);
+        sp = __show_trace(sp,
+                          S390_lowcore.async_stack + frame_size - ASYNC_SIZE,
+                          S390_lowcore.async_stack + frame_size);
         if (task)
                 __show_trace(sp, (unsigned long) task_stack_page(task),
                              (unsigned long) task_stack_page(task) + THREAD_SIZE);
diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c
index f7fb58903f6a..408e866ae548 100644
--- a/arch/s390/kernel/irq.c
+++ b/arch/s390/kernel/irq.c
@@ -311,3 +311,67 @@ void measurement_alert_subclass_unregister(void)
         spin_unlock(&ma_subclass_lock);
 }
 EXPORT_SYMBOL(measurement_alert_subclass_unregister);
+
+void synchronize_irq(unsigned int irq)
+{
+        /*
+         * Not needed, the handler is protected by a lock and IRQs that occur
+         * after the handler is deleted are just NOPs.
+         */
+}
+EXPORT_SYMBOL_GPL(synchronize_irq);
+
+#ifndef CONFIG_PCI
+
+/* Only PCI devices have dynamically-defined IRQ handlers */
+
+int request_irq(unsigned int irq, irq_handler_t handler,
+                unsigned long irqflags, const char *devname, void *dev_id)
+{
+        return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(request_irq);
+
+void free_irq(unsigned int irq, void *dev_id)
+{
+        WARN_ON(1);
+}
+EXPORT_SYMBOL_GPL(free_irq);
+
+void enable_irq(unsigned int irq)
+{
+        WARN_ON(1);
+}
+EXPORT_SYMBOL_GPL(enable_irq);
+
+void disable_irq(unsigned int irq)
+{
+        WARN_ON(1);
+}
+EXPORT_SYMBOL_GPL(disable_irq);
+
+#endif /* !CONFIG_PCI */
+
+void disable_irq_nosync(unsigned int irq)
+{
+        disable_irq(irq);
+}
+EXPORT_SYMBOL_GPL(disable_irq_nosync);
+
+unsigned long probe_irq_on(void)
+{
+        return 0;
+}
+EXPORT_SYMBOL_GPL(probe_irq_on);
+
+int probe_irq_off(unsigned long val)
+{
+        return 0;
+}
+EXPORT_SYMBOL_GPL(probe_irq_off);
+
+unsigned int probe_irq_mask(unsigned long val)
+{
+        return val;
+}
+EXPORT_SYMBOL_GPL(probe_irq_mask);
diff --git a/arch/s390/kernel/sclp.S b/arch/s390/kernel/sclp.S
index b6506ee32a36..29bd7bec4176 100644
--- a/arch/s390/kernel/sclp.S
+++ b/arch/s390/kernel/sclp.S
@@ -225,7 +225,7 @@ _sclp_print:
         ahi     %r2,1
         ltr     %r0,%r0                         # end of string?
         jz      .LfinalizemtoS4
-        chi     %r0,0x15                        # end of line (NL)?
+        chi     %r0,0x0a                        # end of line (NL)?
         jz      .LfinalizemtoS4
         stc     %r0,0(%r6,%r7)                  # copy to mto
         la      %r11,0(%r6,%r7)
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
index 05674b669001..4f977d0d25c2 100644
--- a/arch/s390/kernel/smp.c
+++ b/arch/s390/kernel/smp.c
@@ -428,34 +428,27 @@ void smp_stop_cpu(void)
  * This is the main routine where commands issued by other
  * cpus are handled.
  */
-static void do_ext_call_interrupt(struct ext_code ext_code,
-                                  unsigned int param32, unsigned long param64)
+static void smp_handle_ext_call(void)
 {
         unsigned long bits;
-        int cpu;
-
-        cpu = smp_processor_id();
-        if (ext_code.code == 0x1202)
-                inc_irq_stat(IRQEXT_EXC);
-        else
-                inc_irq_stat(IRQEXT_EMS);
-        /*
-         * handle bit signal external calls
-         */
-        bits = xchg(&pcpu_devices[cpu].ec_mask, 0);
 
+        /* handle bit signal external calls */
+        bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0);
         if (test_bit(ec_stop_cpu, &bits))
                 smp_stop_cpu();
-
         if (test_bit(ec_schedule, &bits))
                 scheduler_ipi();
-
         if (test_bit(ec_call_function, &bits))
                 generic_smp_call_function_interrupt();
-
         if (test_bit(ec_call_function_single, &bits))
                 generic_smp_call_function_single_interrupt();
+}
 
+static void do_ext_call_interrupt(struct ext_code ext_code,
+                                  unsigned int param32, unsigned long param64)
+{
+        inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS);
+        smp_handle_ext_call();
 }
 
 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
@@ -760,6 +753,8 @@ int __cpu_disable(void)
 {
         unsigned long cregs[16];
 
+        /* Handle possible pending IPIs */
+        smp_handle_ext_call();
         set_cpu_online(smp_processor_id(), false);
         /* Disable pseudo page faults on this cpu. */
         pfault_fini();
diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c
index 18dc417aaf79..a938b548f07e 100644
--- a/arch/s390/mm/pgtable.c
+++ b/arch/s390/mm/pgtable.c
@@ -492,7 +492,7 @@ static int gmap_connect_pgtable(unsigned long address, unsigned long segment,
         mp = (struct gmap_pgtable *) page->index;
         rmap->gmap = gmap;
         rmap->entry = segment_ptr;
-        rmap->vmaddr = address;
+        rmap->vmaddr = address & PMD_MASK;
         spin_lock(&mm->page_table_lock);
         if (*segment_ptr == segment) {
                 list_add(&rmap->list, &mp->mapper);
diff --git a/arch/s390/pci/pci.c b/arch/s390/pci/pci.c
index e6f15b5d8b7d..f1e5be85d592 100644
--- a/arch/s390/pci/pci.c
+++ b/arch/s390/pci/pci.c
@@ -302,15 +302,6 @@ static int zpci_cfg_store(struct zpci_dev *zdev, int offset, u32 val, u8 len)
         return rc;
 }
 
-void synchronize_irq(unsigned int irq)
-{
-        /*
-         * Not needed, the handler is protected by a lock and IRQs that occur
-         * after the handler is deleted are just NOPs.
-         */
-}
-EXPORT_SYMBOL_GPL(synchronize_irq);
-
 void enable_irq(unsigned int irq)
 {
         struct msi_desc *msi = irq_get_msi_desc(irq);
@@ -327,30 +318,6 @@ void disable_irq(unsigned int irq)
 }
 EXPORT_SYMBOL_GPL(disable_irq);
 
-void disable_irq_nosync(unsigned int irq)
-{
-        disable_irq(irq);
-}
-EXPORT_SYMBOL_GPL(disable_irq_nosync);
-
-unsigned long probe_irq_on(void)
-{
-        return 0;
-}
-EXPORT_SYMBOL_GPL(probe_irq_on);
-
-int probe_irq_off(unsigned long val)
-{
-        return 0;
-}
-EXPORT_SYMBOL_GPL(probe_irq_off);
-
-unsigned int probe_irq_mask(unsigned long val)
-{
-        return val;
-}
-EXPORT_SYMBOL_GPL(probe_irq_mask);
-
 void pcibios_fixup_bus(struct pci_bus *bus)
 {
 }
diff --git a/arch/sparc/kernel/prom_common.c b/arch/sparc/kernel/prom_common.c
index 9f20566b0773..79cc0d1a477d 100644
--- a/arch/sparc/kernel/prom_common.c
+++ b/arch/sparc/kernel/prom_common.c
@@ -54,6 +54,7 @@ EXPORT_SYMBOL(of_set_property_mutex);
 int of_set_property(struct device_node *dp, const char *name, void *val, int len)
 {
         struct property **prevp;
+        unsigned long flags;
         void *new_val;
         int err;
 
@@ -64,7 +65,7 @@ int of_set_property(struct device_node *dp, const char *name, void *val, int len
         err = -ENODEV;
 
         mutex_lock(&of_set_property_mutex);
-        raw_spin_lock(&devtree_lock);
+        raw_spin_lock_irqsave(&devtree_lock, flags);
         prevp = &dp->properties;
         while (*prevp) {
                 struct property *prop = *prevp;
@@ -91,7 +92,7 @@ int of_set_property(struct device_node *dp, const char *name, void *val, int len
                 }
                 prevp = &(*prevp)->next;
         }
-        raw_spin_unlock(&devtree_lock);
+        raw_spin_unlock_irqrestore(&devtree_lock, flags);
         mutex_unlock(&of_set_property_mutex);
 
         /* XXX Upate procfs if necessary... */
diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c
index 35ee62fccf98..c205035a6b96 100644
--- a/arch/x86/boot/compressed/eboot.c
+++ b/arch/x86/boot/compressed/eboot.c
@@ -251,51 +251,6 @@ static void find_bits(unsigned long mask, u8 *pos, u8 *size)
         *size = len;
 }
 
-static efi_status_t setup_efi_vars(struct boot_params *params)
-{
-        struct setup_data *data;
-        struct efi_var_bootdata *efidata;
-        u64 store_size, remaining_size, var_size;
-        efi_status_t status;
-
-        if (sys_table->runtime->hdr.revision < EFI_2_00_SYSTEM_TABLE_REVISION)
-                return EFI_UNSUPPORTED;
-
-        data = (struct setup_data *)(unsigned long)params->hdr.setup_data;
-
-        while (data && data->next)
-                data = (struct setup_data *)(unsigned long)data->next;
-
-        status = efi_call_phys4((void *)sys_table->runtime->query_variable_info,
-                                EFI_VARIABLE_NON_VOLATILE |
-                                EFI_VARIABLE_BOOTSERVICE_ACCESS |
-                                EFI_VARIABLE_RUNTIME_ACCESS, &store_size,
-                                &remaining_size, &var_size);
-
-        if (status != EFI_SUCCESS)
-                return status;
-
-        status = efi_call_phys3(sys_table->boottime->allocate_pool,
-                                EFI_LOADER_DATA, sizeof(*efidata), &efidata);
-
-        if (status != EFI_SUCCESS)
-                return status;
-
-        efidata->data.type = SETUP_EFI_VARS;
-        efidata->data.len = sizeof(struct efi_var_bootdata) -
-                sizeof(struct setup_data);
-        efidata->data.next = 0;
-        efidata->store_size = store_size;
-        efidata->remaining_size = remaining_size;
-        efidata->max_var_size = var_size;
-
-        if (data)
-                data->next = (unsigned long)efidata;
-        else
-                params->hdr.setup_data = (unsigned long)efidata;
-
-}
-
 static efi_status_t setup_efi_pci(struct boot_params *params)
 {
         efi_pci_io_protocol *pci;
@@ -1202,8 +1157,6 @@ struct boot_params *efi_main(void *handle, efi_system_table_t *_table,
 
         setup_graphics(boot_params);
 
-        setup_efi_vars(boot_params);
-
         setup_efi_pci(boot_params);
 
         status = efi_call_phys3(sys_table->boottime->allocate_pool,
diff --git a/arch/x86/crypto/crc32-pclmul_asm.S b/arch/x86/crypto/crc32-pclmul_asm.S
index 94c27df8a549..f247304299a2 100644
--- a/arch/x86/crypto/crc32-pclmul_asm.S
+++ b/arch/x86/crypto/crc32-pclmul_asm.S
@@ -240,7 +240,7 @@ fold_64:
         pand    %xmm3, %xmm1
         PCLMULQDQ 0x00, CONSTANT, %xmm1
         pxor    %xmm2, %xmm1
-        pextrd  $0x01, %xmm1, %eax
+        PEXTRD  0x01, %xmm1, %eax
 
         ret
 ENDPROC(crc32_pclmul_le_16)
diff --git a/arch/x86/crypto/sha256-avx-asm.S b/arch/x86/crypto/sha256-avx-asm.S
index 56610c4bf31b..642f15687a0a 100644
--- a/arch/x86/crypto/sha256-avx-asm.S
+++ b/arch/x86/crypto/sha256-avx-asm.S
@@ -118,7 +118,7 @@ y2 = %r15d
 
 _INP_END_SIZE = 8
 _INP_SIZE = 8
-_XFER_SIZE = 8
+_XFER_SIZE = 16
 _XMM_SAVE_SIZE = 0
 
 _INP_END = 0
diff --git a/arch/x86/crypto/sha256-ssse3-asm.S b/arch/x86/crypto/sha256-ssse3-asm.S
index 98d3c391da81..f833b74d902b 100644
--- a/arch/x86/crypto/sha256-ssse3-asm.S
+++ b/arch/x86/crypto/sha256-ssse3-asm.S
@@ -111,7 +111,7 @@ y2 = %r15d
 
 _INP_END_SIZE = 8
 _INP_SIZE = 8
-_XFER_SIZE = 8
+_XFER_SIZE = 16
 _XMM_SAVE_SIZE = 0
 
 _INP_END = 0
diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h
index 2fb5d5884e23..60c89f30c727 100644
--- a/arch/x86/include/asm/efi.h
+++ b/arch/x86/include/asm/efi.h
@@ -102,13 +102,6 @@ extern void efi_call_phys_epilog(void);
 extern void efi_unmap_memmap(void);
 extern void efi_memory_uc(u64 addr, unsigned long size);
 
-struct efi_var_bootdata {
-        struct setup_data data;
-        u64 store_size;
-        u64 remaining_size;
-        u64 max_var_size;
-};
-
 #ifdef CONFIG_EFI
 
 static inline bool efi_is_native(void)
diff --git a/arch/x86/include/asm/inst.h b/arch/x86/include/asm/inst.h
index 280bf7fb6aba..3e115273ed88 100644
--- a/arch/x86/include/asm/inst.h
+++ b/arch/x86/include/asm/inst.h
@@ -9,12 +9,68 @@
 
 #define REG_NUM_INVALID         100
 
-#define REG_TYPE_R64            0
-#define REG_TYPE_XMM            1
+#define REG_TYPE_R32            0
+#define REG_TYPE_R64            1
+#define REG_TYPE_XMM            2
 #define REG_TYPE_INVALID        100
 
+        .macro R32_NUM opd r32
+        \opd = REG_NUM_INVALID
+        .ifc \r32,%eax
+        \opd = 0
+        .endif
+        .ifc \r32,%ecx
+        \opd = 1
+        .endif
+        .ifc \r32,%edx
+        \opd = 2
+        .endif
+        .ifc \r32,%ebx
+        \opd = 3
+        .endif
+        .ifc \r32,%esp
+        \opd = 4
+        .endif
+        .ifc \r32,%ebp
+        \opd = 5
+        .endif
+        .ifc \r32,%esi
+        \opd = 6
+        .endif
+        .ifc \r32,%edi
+        \opd = 7
+        .endif
+#ifdef CONFIG_X86_64
+        .ifc \r32,%r8d
+        \opd = 8
+        .endif
+        .ifc \r32,%r9d
+        \opd = 9
+        .endif
+        .ifc \r32,%r10d
+        \opd = 10
+        .endif
+        .ifc \r32,%r11d
+        \opd = 11
+        .endif
+        .ifc \r32,%r12d
+        \opd = 12
+        .endif
+        .ifc \r32,%r13d
+        \opd = 13
+        .endif
+        .ifc \r32,%r14d
+        \opd = 14
+        .endif
+        .ifc \r32,%r15d
+        \opd = 15
+        .endif
+#endif
+        .endm
+
         .macro R64_NUM opd r64
         \opd = REG_NUM_INVALID
+#ifdef CONFIG_X86_64
         .ifc \r64,%rax
         \opd = 0
         .endif
@@ -63,6 +119,7 @@
         .ifc \r64,%r15
         \opd = 15
         .endif
+#endif
         .endm
 
         .macro XMM_NUM opd xmm
@@ -118,10 +175,13 @@
         .endm
 
         .macro REG_TYPE type reg
+        R32_NUM reg_type_r32 \reg
         R64_NUM reg_type_r64 \reg
         XMM_NUM reg_type_xmm \reg
         .if reg_type_r64 <> REG_NUM_INVALID
         \type = REG_TYPE_R64
+        .elseif reg_type_r32 <> REG_NUM_INVALID
+        \type = REG_TYPE_R32
         .elseif reg_type_xmm <> REG_NUM_INVALID
         \type = REG_TYPE_XMM
         .else
@@ -162,6 +222,16 @@
         .byte \imm8
         .endm
 
+        .macro PEXTRD imm8 xmm gpr
+        R32_NUM extrd_opd1 \gpr
+        XMM_NUM extrd_opd2 \xmm
+        PFX_OPD_SIZE
+        PFX_REX extrd_opd1 extrd_opd2
+        .byte 0x0f, 0x3a, 0x16
+        MODRM 0xc0 extrd_opd1 extrd_opd2
+        .byte \imm8
+        .endm
+
         .macro AESKEYGENASSIST rcon xmm1 xmm2
         XMM_NUM aeskeygen_opd1 \xmm1
         XMM_NUM aeskeygen_opd2 \xmm2
diff --git a/arch/x86/include/uapi/asm/bootparam.h b/arch/x86/include/uapi/asm/bootparam.h
index 08744242b8d2..c15ddaf90710 100644
--- a/arch/x86/include/uapi/asm/bootparam.h
+++ b/arch/x86/include/uapi/asm/bootparam.h
@@ -6,7 +6,6 @@
 #define SETUP_E820_EXT                  1
 #define SETUP_DTB                       2
 #define SETUP_PCI                       3
-#define SETUP_EFI_VARS                  4
 
 /* ram_size flags */
 #define RAMDISK_IMAGE_START_MASK        0x07FF
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index 08f7e8039099..321d65ebaffe 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -115,8 +115,10 @@ startup_64:
         movq    %rdi, %rax
         shrq    $PUD_SHIFT, %rax
         andl    $(PTRS_PER_PUD-1), %eax
-        movq    %rdx, (4096+0)(%rbx,%rax,8)
-        movq    %rdx, (4096+8)(%rbx,%rax,8)
+        movq    %rdx, 4096(%rbx,%rax,8)
+        incl    %eax
+        andl    $(PTRS_PER_PUD-1), %eax
+        movq    %rdx, 4096(%rbx,%rax,8)
 
         addq    $8192, %rbx
         movq    %rdi, %rax
diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c
index 245a71db401a..cb339097b9ea 100644
--- a/arch/x86/kernel/i387.c
+++ b/arch/x86/kernel/i387.c
@@ -22,23 +22,19 @@
 /*
  * Were we in an interrupt that interrupted kernel mode?
  *
- * For now, with eagerfpu we will return interrupted kernel FPU
- * state as not-idle. TBD: Ideally we can change the return value
- * to something like __thread_has_fpu(current). But we need to
- * be careful of doing __thread_clear_has_fpu() before saving
- * the FPU etc for supporting nested uses etc. For now, take
- * the simple route!
- *
  * On others, we can do a kernel_fpu_begin/end() pair *ONLY* if that
  * pair does nothing at all: the thread must not have fpu (so
  * that we don't try to save the FPU state), and TS must
  * be set (so that the clts/stts pair does nothing that is
  * visible in the interrupted kernel thread).
+ *
+ * Except for the eagerfpu case when we return 1 unless we've already
+ * been eager and saved the state in kernel_fpu_begin().
  */
 static inline bool interrupted_kernel_fpu_idle(void)
 {
         if (use_eager_fpu())
-                return 0;
+                return __thread_has_fpu(current);
 
         return !__thread_has_fpu(current) &&
                 (read_cr0() & X86_CR0_TS);
@@ -78,8 +74,8 @@ void __kernel_fpu_begin(void)
         struct task_struct *me = current;
 
         if (__thread_has_fpu(me)) {
-                __save_init_fpu(me);
                 __thread_clear_has_fpu(me);
+                __save_init_fpu(me);
                 /* We do 'stts()' in __kernel_fpu_end() */
         } else if (!use_eager_fpu()) {
                 this_cpu_write(fpu_owner_task, NULL);
diff --git a/arch/x86/kernel/relocate_kernel_64.S b/arch/x86/kernel/relocate_kernel_64.S
index 7a6f3b3be3cf..f2bb9c96720a 100644
--- a/arch/x86/kernel/relocate_kernel_64.S
+++ b/arch/x86/kernel/relocate_kernel_64.S
@@ -160,7 +160,7 @@ identity_mapped:
         xorq    %rbp, %rbp
         xorq    %r8,  %r8
         xorq    %r9,  %r9
-        xorq    %r10, %r9
+        xorq    %r10, %r10
         xorq    %r11, %r11
         xorq    %r12, %r12
         xorq    %r13, %r13
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index 8db0010ed150..5953dcea752d 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -1240,9 +1240,12 @@ static int decode_modrm(struct x86_emulate_ctxt *ctxt,
         ctxt->modrm_seg = VCPU_SREG_DS;
 
         if (ctxt->modrm_mod == 3) {
+                int highbyte_regs = ctxt->rex_prefix == 0;
+
                 op->type = OP_REG;
                 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
-                op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp);
+                op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
+                                               highbyte_regs && (ctxt->d & ByteOp));
                 if (ctxt->d & Sse) {
                         op->type = OP_XMM;
                         op->bytes = 16;
@@ -3997,7 +4000,8 @@ static const struct opcode twobyte_table[256] = {
         DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
         N, D(ImplicitOps | ModRM), N, N,
         /* 0x10 - 0x1F */
-        N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
+        N, N, N, N, N, N, N, N,
+        D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM),
         /* 0x20 - 0x2F */
         DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
         DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
@@ -4836,6 +4840,7 @@ twobyte_insn:
         case 0x08:              /* invd */
         case 0x0d:              /* GrpP (prefetch) */
         case 0x18:              /* Grp16 (prefetch/nop) */
+        case 0x1f:              /* nop */
                 break;
         case 0x20: /* mov cr, reg */
                 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index e1adbb4aca75..0eee2c8b64d1 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -1861,11 +1861,14 @@ void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
 {
         struct kvm_lapic *apic = vcpu->arch.apic;
         unsigned int sipi_vector;
+        unsigned long pe;
 
-        if (!kvm_vcpu_has_lapic(vcpu))
+        if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
                 return;
 
-        if (test_and_clear_bit(KVM_APIC_INIT, &apic->pending_events)) {
+        pe = xchg(&apic->pending_events, 0);
+
+        if (test_bit(KVM_APIC_INIT, &pe)) {
                 kvm_lapic_reset(vcpu);
                 kvm_vcpu_reset(vcpu);
                 if (kvm_vcpu_is_bsp(apic->vcpu))
@@ -1873,7 +1876,7 @@ void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
                 else
                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
         }
-        if (test_and_clear_bit(KVM_APIC_SIPI, &apic->pending_events) &&
+        if (test_bit(KVM_APIC_SIPI, &pe) &&
             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
                 /* evaluate pending_events before reading the vector */
                 smp_rmb();
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index eaac1743def7..1f34e9219775 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -277,6 +277,9 @@ static int __meminit split_mem_range(struct map_range *mr, int nr_range,
         end_pfn = limit_pfn;
         nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
 
+        if (!after_bootmem)
+                adjust_range_page_size_mask(mr, nr_range);
+
         /* try to merge same page size and continuous */
         for (i = 0; nr_range > 1 && i < nr_range - 1; i++) {
                 unsigned long old_start;
@@ -291,9 +294,6 @@ static int __meminit split_mem_range(struct map_range *mr, int nr_range,
                 nr_range--;
         }
 
-        if (!after_bootmem)
-                adjust_range_page_size_mask(mr, nr_range);
-
         for (i = 0; i < nr_range; i++)
                 printk(KERN_DEBUG " [mem %#010lx-%#010lx] page %s\n",
                                 mr[i].start, mr[i].end - 1,
diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
index 305c68b8d538..981c2dbd72cc 100644
--- a/arch/x86/pci/common.c
+++ b/arch/x86/pci/common.c
@@ -628,7 +628,9 @@ int pcibios_add_device(struct pci_dev *dev)
 
         pa_data = boot_params.hdr.setup_data;
         while (pa_data) {
-                data = phys_to_virt(pa_data);
+                data = ioremap(pa_data, sizeof(*rom));
+                if (!data)
+                        return -ENOMEM;
 
                 if (data->type == SETUP_PCI) {
                         rom = (struct pci_setup_rom *)data;
@@ -645,6 +647,7 @@ int pcibios_add_device(struct pci_dev *dev)
                         }
                 }
                 pa_data = data->next;
+                iounmap(data);
         }
         return 0;
 }
diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c
index 55856b2310d3..5ae2eb09419e 100644
--- a/arch/x86/platform/efi/efi.c
+++ b/arch/x86/platform/efi/efi.c
@@ -42,7 +42,6 @@
 #include <linux/io.h>
 #include <linux/reboot.h>
 #include <linux/bcd.h>
-#include <linux/ucs2_string.h>
 
 #include <asm/setup.h>
 #include <asm/efi.h>
@@ -54,12 +53,12 @@
 
 #define EFI_DEBUG       1
 
-/*
- * There's some additional metadata associated with each
- * variable. Intel's reference implementation is 60 bytes - bump that
- * to account for potential alignment constraints
- */
-#define VAR_METADATA_SIZE 64
+#define EFI_MIN_RESERVE 5120
+
+#define EFI_DUMMY_GUID \
+        EFI_GUID(0x4424ac57, 0xbe4b, 0x47dd, 0x9e, 0x97, 0xed, 0x50, 0xf0, 0x9f, 0x92, 0xa9)
+
+static efi_char16_t efi_dummy_name[6] = { 'D', 'U', 'M', 'M', 'Y', 0 };
 
 struct efi __read_mostly efi = {
         .mps        = EFI_INVALID_TABLE_ADDR,
@@ -79,13 +78,6 @@ struct efi_memory_map memmap;
 static struct efi efi_phys __initdata;
 static efi_system_table_t efi_systab __initdata;
 
-static u64 efi_var_store_size;
-static u64 efi_var_remaining_size;
-static u64 efi_var_max_var_size;
-static u64 boot_used_size;
-static u64 boot_var_size;
-static u64 active_size;
-
 unsigned long x86_efi_facility;
 
 /*
@@ -188,53 +180,8 @@ static efi_status_t virt_efi_get_next_variable(unsigned long *name_size,
                                                efi_char16_t *name,
                                                efi_guid_t *vendor)
 {
-        efi_status_t status;
-        static bool finished = false;
-        static u64 var_size;
-
-        status = efi_call_virt3(get_next_variable,
-                                name_size, name, vendor);
-
-        if (status == EFI_NOT_FOUND) {
-                finished = true;
-                if (var_size < boot_used_size) {
-                        boot_var_size = boot_used_size - var_size;
-                        active_size += boot_var_size;
-                } else {
-                        printk(KERN_WARNING FW_BUG  "efi: Inconsistent initial sizes\n");
-                }
-        }
-
-        if (boot_used_size && !finished) {
-                unsigned long size;
-                u32 attr;
-                efi_status_t s;
-                void *tmp;
-
-                s = virt_efi_get_variable(name, vendor, &attr, &size, NULL);
-
-                if (s != EFI_BUFFER_TOO_SMALL || !size)
-                        return status;
-
-                tmp = kmalloc(size, GFP_ATOMIC);
-
-                if (!tmp)
-                        return status;
-
-                s = virt_efi_get_variable(name, vendor, &attr, &size, tmp);
-
-                if (s == EFI_SUCCESS && (attr & EFI_VARIABLE_NON_VOLATILE)) {
-                        var_size += size;
-                        var_size += ucs2_strsize(name, 1024);
-                        active_size += size;
-                        active_size += VAR_METADATA_SIZE;
-                        active_size += ucs2_strsize(name, 1024);
-                }
-
-                kfree(tmp);
-        }
-
-        return status;
+        return efi_call_virt3(get_next_variable,
+                              name_size, name, vendor);
 }
 
 static efi_status_t virt_efi_set_variable(efi_char16_t *name,
@@ -243,34 +190,9 @@ static efi_status_t virt_efi_set_variable(efi_char16_t *name,
                                           unsigned long data_size,
                                           void *data)
 {
-        efi_status_t status;
-        u32 orig_attr = 0;
-        unsigned long orig_size = 0;
-
-        status = virt_efi_get_variable(name, vendor, &orig_attr, &orig_size,
-                                       NULL);
-
-        if (status != EFI_BUFFER_TOO_SMALL)
-                orig_size = 0;
-
-        status = efi_call_virt5(set_variable,
-                                name, vendor, attr,
-                                data_size, data);
-
-        if (status == EFI_SUCCESS) {
-                if (orig_size) {
-                        active_size -= orig_size;
-                        active_size -= ucs2_strsize(name, 1024);
-                        active_size -= VAR_METADATA_SIZE;
-                }
-                if (data_size) {
-                        active_size += data_size;
-                        active_size += ucs2_strsize(name, 1024);
-                        active_size += VAR_METADATA_SIZE;
-                }
-        }
-
-        return status;
+        return efi_call_virt5(set_variable,
+                              name, vendor, attr,
+                              data_size, data);
 }
 
 static efi_status_t virt_efi_query_variable_info(u32 attr,
@@ -786,9 +708,6 @@ void __init efi_init(void)
         char vendor[100] = "unknown";
         int i = 0;
         void *tmp;
-        struct setup_data *data;
-        struct efi_var_bootdata *efi_var_data;
-        u64 pa_data;
 
 #ifdef CONFIG_X86_32
         if (boot_params.efi_info.efi_systab_hi ||
@@ -806,22 +725,6 @@ void __init efi_init(void)
         if (efi_systab_init(efi_phys.systab))
                 return;
 
-        pa_data = boot_params.hdr.setup_data;
-        while (pa_data) {
-                data = early_ioremap(pa_data, sizeof(*efi_var_data));
-                if (data->type == SETUP_EFI_VARS) {
-                        efi_var_data = (struct efi_var_bootdata *)data;
-
-                        efi_var_store_size = efi_var_data->store_size;
-                        efi_var_remaining_size = efi_var_data->remaining_size;
-                        efi_var_max_var_size = efi_var_data->max_var_size;
-                }
-                pa_data = data->next;
-                early_iounmap(data, sizeof(*efi_var_data));
-        }
-
-        boot_used_size = efi_var_store_size - efi_var_remaining_size;
-
         set_bit(EFI_SYSTEM_TABLES, &x86_efi_facility);
 
         /*
@@ -1085,6 +988,13 @@ void __init efi_enter_virtual_mode(void)
                 runtime_code_page_mkexec();
 
         kfree(new_memmap);
+
+        /* clean DUMMY object */
+        efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID,
+                         EFI_VARIABLE_NON_VOLATILE |
+                         EFI_VARIABLE_BOOTSERVICE_ACCESS |
+                         EFI_VARIABLE_RUNTIME_ACCESS,
+                         0, NULL);
 }
 
 /*
@@ -1136,33 +1046,65 @@ efi_status_t efi_query_variable_store(u32 attributes, unsigned long size)
         efi_status_t status;
         u64 storage_size, remaining_size, max_size;
 
+        if (!(attributes & EFI_VARIABLE_NON_VOLATILE))
+                return 0;
+
         status = efi.query_variable_info(attributes, &storage_size,
                                          &remaining_size, &max_size);
         if (status != EFI_SUCCESS)
                 return status;
 
-        if (!max_size && remaining_size > size)
-                printk_once(KERN_ERR FW_BUG "Broken EFI implementation"
-                            " is returning MaxVariableSize=0\n");
         /*
          * Some firmware implementations refuse to boot if there's insufficient
          * space in the variable store. We account for that by refusing the
          * write if permitting it would reduce the available space to under
-         * 50%. However, some firmware won't reclaim variable space until
-         * after the used (not merely the actively used) space drops below
-         * a threshold. We can approximate that case with the value calculated
-         * above. If both the firmware and our calculations indicate that the
-         * available space would drop below 50%, refuse the write.
+         * 5KB. This figure was provided by Samsung, so should be safe.
          */
+        if ((remaining_size - size < EFI_MIN_RESERVE) &&
+                !efi_no_storage_paranoia) {
+
+                /*
+                 * Triggering garbage collection may require that the firmware
+                 * generate a real EFI_OUT_OF_RESOURCES error. We can force
+                 * that by attempting to use more space than is available.
+                 */
+                unsigned long dummy_size = remaining_size + 1024;
+                void *dummy = kmalloc(dummy_size, GFP_ATOMIC);
+
+                status = efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID,
+                                          EFI_VARIABLE_NON_VOLATILE |
+                                          EFI_VARIABLE_BOOTSERVICE_ACCESS |
+                                          EFI_VARIABLE_RUNTIME_ACCESS,
+                                          dummy_size, dummy);
+
+                if (status == EFI_SUCCESS) {
+                        /*
+                         * This should have failed, so if it didn't make sure
+                         * that we delete it...
+                         */
+                        efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID,
+                                         EFI_VARIABLE_NON_VOLATILE |
+                                         EFI_VARIABLE_BOOTSERVICE_ACCESS |
+                                         EFI_VARIABLE_RUNTIME_ACCESS,
+                                         0, dummy);
+                }
 
-        if (!storage_size || size > remaining_size ||
-            (max_size && size > max_size))
-                return EFI_OUT_OF_RESOURCES;
+                /*
+                 * The runtime code may now have triggered a garbage collection
+                 * run, so check the variable info again
+                 */
+                status = efi.query_variable_info(attributes, &storage_size,
+                                                 &remaining_size, &max_size);
 
-        if (!efi_no_storage_paranoia &&
-            ((active_size + size + VAR_METADATA_SIZE > storage_size / 2) &&
-             (remaining_size - size < storage_size / 2)))
-                return EFI_OUT_OF_RESOURCES;
+                if (status != EFI_SUCCESS)
+                        return status;
+
+                /*
+                 * There still isn't enough room, so return an error
+                 */
+                if (remaining_size - size < EFI_MIN_RESERVE)
+                        return EFI_OUT_OF_RESOURCES;
+        }
 
         return EFI_SUCCESS;
 }
diff --git a/arch/x86/tools/relocs.c b/arch/x86/tools/relocs.c
index 590be1090892..f7bab68a4b83 100644
--- a/arch/x86/tools/relocs.c
+++ b/arch/x86/tools/relocs.c
@@ -42,9 +42,6 @@ static const char * const sym_regex_kernel[S_NSYMTYPES] = {
         "^(xen_irq_disable_direct_reloc$|"
         "xen_save_fl_direct_reloc$|"
         "VDSO|"
-#if ELF_BITS == 64
-        "__vvar_page|"
-#endif
         "__crc_)",
 
 /*
@@ -72,6 +69,7 @@ static const char * const sym_regex_kernel[S_NSYMTYPES] = {
         "__per_cpu_load|"
         "init_per_cpu__.*|"
         "__end_rodata_hpage_align|"
+        "__vvar_page|"
 #endif
         "_end)$"
 };
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index 8ff37995d54e..d99cae8147d1 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -17,6 +17,7 @@
 #include <linux/slab.h>
 #include <linux/smp.h>
 #include <linux/irq_work.h>
+#include <linux/tick.h>
 
 #include <asm/paravirt.h>
 #include <asm/desc.h>
@@ -447,6 +448,13 @@ static void __cpuinit xen_play_dead(void) /* used only with HOTPLUG_CPU */
         play_dead_common();
         HYPERVISOR_vcpu_op(VCPUOP_down, smp_processor_id(), NULL);
         cpu_bringup();
+        /*
+         * commit 4b0c0f294 (tick: Cleanup NOHZ per cpu data on cpu down)
+         * clears certain data that the cpu_idle loop (which called us
+         * and that we return from) expects. The only way to get that
+         * data back is to call:
+         */
+        tick_nohz_idle_enter();
 }
 
 #else /* !CONFIG_HOTPLUG_CPU */
@@ -576,24 +584,22 @@ void xen_send_IPI_mask_allbutself(const struct cpumask *mask,
 {
         unsigned cpu;
         unsigned int this_cpu = smp_processor_id();
+        int xen_vector = xen_map_vector(vector);
 
-        if (!(num_online_cpus() > 1))
+        if (!(num_online_cpus() > 1) || (xen_vector < 0))
                 return;
 
         for_each_cpu_and(cpu, mask, cpu_online_mask) {
                 if (this_cpu == cpu)
                         continue;
 
-                xen_smp_send_call_function_single_ipi(cpu);
+                xen_send_IPI_one(cpu, xen_vector);
         }
 }
 
 void xen_send_IPI_allbutself(int vector)
 {
-        int xen_vector = xen_map_vector(vector);
-
-        if (xen_vector >= 0)
-                xen_send_IPI_mask_allbutself(cpu_online_mask, xen_vector);
+        xen_send_IPI_mask_allbutself(cpu_online_mask, vector);
 }
 
 static irqreturn_t xen_call_function_interrupt(int irq, void *dev_id)
diff --git a/arch/x86/xen/smp.h b/arch/x86/xen/smp.h
index 8981a76d081a..c7c2d89efd76 100644
--- a/arch/x86/xen/smp.h
+++ b/arch/x86/xen/smp.h
@@ -5,7 +5,6 @@ extern void xen_send_IPI_mask(const struct cpumask *mask,
 extern void xen_send_IPI_mask_allbutself(const struct cpumask *mask,
                                 int vector);
 extern void xen_send_IPI_allbutself(int vector);
-extern void physflat_send_IPI_allbutself(int vector);
 extern void xen_send_IPI_all(int vector);
 extern void xen_send_IPI_self(int vector);
 
diff --git a/block/blk-core.c b/block/blk-core.c
index 33c33bc99ddd..d5745b5833c9 100644
--- a/block/blk-core.c
+++ b/block/blk-core.c
@@ -3164,7 +3164,7 @@ void blk_post_runtime_resume(struct request_queue *q, int err)
                 q->rpm_status = RPM_ACTIVE;
                 __blk_run_queue(q);
                 pm_runtime_mark_last_busy(q->dev);
-                pm_runtime_autosuspend(q->dev);
+                pm_request_autosuspend(q->dev);
         } else {
                 q->rpm_status = RPM_SUSPENDED;
         }
diff --git a/crypto/Kconfig b/crypto/Kconfig
index 622d8a48cbe9..bf8148e74e73 100644
--- a/crypto/Kconfig
+++ b/crypto/Kconfig
@@ -823,6 +823,7 @@ config CRYPTO_BLOWFISH_X86_64
 config CRYPTO_BLOWFISH_AVX2_X86_64
         tristate "Blowfish cipher algorithm (x86_64/AVX2)"
         depends on X86 && 64BIT
+        depends on BROKEN
         select CRYPTO_ALGAPI
         select CRYPTO_CRYPTD
         select CRYPTO_ABLK_HELPER_X86
@@ -1299,6 +1300,7 @@ config CRYPTO_TWOFISH_AVX_X86_64
 config CRYPTO_TWOFISH_AVX2_X86_64
         tristate "Twofish cipher algorithm (x86_64/AVX2)"
         depends on X86 && 64BIT
+        depends on BROKEN
         select CRYPTO_ALGAPI
         select CRYPTO_CRYPTD
         select CRYPTO_ABLK_HELPER_X86
diff --git a/drivers/acpi/apei/cper.c b/drivers/acpi/apei/cper.c
index fefc2ca7cc3e..33dc6a004802 100644
--- a/drivers/acpi/apei/cper.c
+++ b/drivers/acpi/apei/cper.c
@@ -250,10 +250,6 @@ static const char *cper_pcie_port_type_strs[] = {
 static void cper_print_pcie(const char *pfx, const struct cper_sec_pcie *pcie,
                             const struct acpi_hest_generic_data *gdata)
 {
-#ifdef CONFIG_ACPI_APEI_PCIEAER
-        struct pci_dev *dev;
-#endif
-
         if (pcie->validation_bits & CPER_PCIE_VALID_PORT_TYPE)
                 printk("%s""port_type: %d, %s\n", pfx, pcie->port_type,
                        pcie->port_type < ARRAY_SIZE(cper_pcie_port_type_strs) ?
@@ -285,20 +281,6 @@ static void cper_print_pcie(const char *pfx, const struct cper_sec_pcie *pcie,
                 printk(
         "%s""bridge: secondary_status: 0x%04x, control: 0x%04x\n",
         pfx, pcie->bridge.secondary_status, pcie->bridge.control);
-#ifdef CONFIG_ACPI_APEI_PCIEAER
-        dev = pci_get_domain_bus_and_slot(pcie->device_id.segment,
-                        pcie->device_id.bus, pcie->device_id.function);
-        if (!dev) {
-                pr_err("PCI AER Cannot get PCI device %04x:%02x:%02x.%d\n",
-                        pcie->device_id.segment, pcie->device_id.bus,
-                        pcie->device_id.slot, pcie->device_id.function);
-                return;
-        }
-        if (pcie->validation_bits & CPER_PCIE_VALID_AER_INFO)
-                cper_print_aer(pfx, dev, gdata->error_severity,
-                                (struct aer_capability_regs *) pcie->aer_info);
-        pci_dev_put(dev);
-#endif
 }
 
 static const char *apei_estatus_section_flag_strs[] = {
diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
index d668a8ae602b..fcd7d91cec34 100644
--- a/drivers/acpi/apei/ghes.c
+++ b/drivers/acpi/apei/ghes.c
@@ -454,7 +454,9 @@ static void ghes_do_proc(struct ghes *ghes,
                                 aer_severity = cper_severity_to_aer(sev);
                                 aer_recover_queue(pcie_err->device_id.segment,
                                                   pcie_err->device_id.bus,
-                                                  devfn, aer_severity);
+                                                  devfn, aer_severity,
+                                                  (struct aer_capability_regs *)
+                                                  pcie_err->aer_info);
                         }
 
                 }
@@ -917,13 +919,14 @@ static int ghes_probe(struct platform_device *ghes_dev)
                 break;
         case ACPI_HEST_NOTIFY_EXTERNAL:
                 /* External interrupt vector is GSI */
-                if (acpi_gsi_to_irq(generic->notify.vector, &ghes->irq)) {
+                rc = acpi_gsi_to_irq(generic->notify.vector, &ghes->irq);
+                if (rc) {
                         pr_err(GHES_PFX "Failed to map GSI to IRQ for generic hardware error source: %d\n",
                                generic->header.source_id);
                         goto err_edac_unreg;
                 }
-                if (request_irq(ghes->irq, ghes_irq_func,
-                                0, "GHES IRQ", ghes)) {
+                rc = request_irq(ghes->irq, ghes_irq_func, 0, "GHES IRQ", ghes);
+                if (rc) {
                         pr_err(GHES_PFX "Failed to register IRQ for generic hardware error source: %d\n",
                                generic->header.source_id);
                         goto err_edac_unreg;
diff --git a/drivers/acpi/device_pm.c b/drivers/acpi/device_pm.c
index bc493aa3af19..318fa32a141e 100644
--- a/drivers/acpi/device_pm.c
+++ b/drivers/acpi/device_pm.c
@@ -278,11 +278,13 @@ int acpi_bus_init_power(struct acpi_device *device)
                 if (result)
                         return result;
         } else if (state == ACPI_STATE_UNKNOWN) {
-                /* No power resources and missing _PSC? Try to force D0. */
+                /*
+                 * No power resources and missing _PSC?  Cross fingers and make
+                 * it D0 in hope that this is what the BIOS put the device into.
+                 * [We tried to force D0 here by executing _PS0, but that broke
+                 * Toshiba P870-303 in a nasty way.]
+                 */
                 state = ACPI_STATE_D0;
-                result = acpi_dev_pm_explicit_set(device, state);
-                if (result)
-                        return result;
         }
         device->power.state = state;
         return 0;
diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c
index 44225cb15f3a..b14ac46948c9 100644
--- a/drivers/acpi/scan.c
+++ b/drivers/acpi/scan.c
@@ -1017,11 +1017,8 @@ acpi_bus_driver_init(struct acpi_device *device, struct acpi_driver *driver)
                 return -ENOSYS;
 
         result = driver->ops.add(device);
-        if (result) {
-                device->driver = NULL;
-                device->driver_data = NULL;
+        if (result)
                 return result;
-        }
 
         device->driver = driver;
 
diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c
index 5b32e15a65ce..440eadf2d32c 100644
--- a/drivers/acpi/video.c
+++ b/drivers/acpi/video.c
@@ -458,12 +458,28 @@ static struct dmi_system_id video_dmi_table[] __initdata = {
         },
         {
          .callback = video_ignore_initial_backlight,
+         .ident = "HP Pavilion g6 Notebook PC",
+         .matches = {
+                 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
+                 DMI_MATCH(DMI_PRODUCT_NAME, "HP Pavilion g6 Notebook PC"),
+                },
+        },
+        {
+         .callback = video_ignore_initial_backlight,
          .ident = "HP 1000 Notebook PC",
          .matches = {
                 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
                 DMI_MATCH(DMI_PRODUCT_NAME, "HP 1000 Notebook PC"),
                 },
         },
+        {
+         .callback = video_ignore_initial_backlight,
+         .ident = "HP Pavilion m4",
+         .matches = {
+                DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
+                DMI_MATCH(DMI_PRODUCT_NAME, "HP Pavilion m4 Notebook PC"),
+                },
+        },
         {}
 };
 
@@ -1706,6 +1722,9 @@ static int acpi_video_bus_add(struct acpi_device *device)
         int error;
         acpi_status status;
 
+        if (device->handler)
+                return -EINVAL;
+
         status = acpi_walk_namespace(ACPI_TYPE_DEVICE,
                                 device->parent->handle, 1,
                                 acpi_video_bus_match, NULL,
diff --git a/drivers/ata/acard-ahci.c b/drivers/ata/acard-ahci.c
index 4e94ba29cb8d..9d0cf019ce59 100644
--- a/drivers/ata/acard-ahci.c
+++ b/drivers/ata/acard-ahci.c
@@ -2,7 +2,7 @@
 /*
  *  acard-ahci.c - ACard AHCI SATA support
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 251e57d38942..2b50dfdf1cfc 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1,7 +1,7 @@
 /*
  *  ahci.c - AHCI SATA support
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
@@ -423,6 +423,8 @@ static const struct pci_device_id ahci_pci_tbl[] = {
           .driver_data = board_ahci_yes_fbs },                  /* 88se9125 */
         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
           .driver_data = board_ahci_yes_fbs },                  /* 88se9172 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
+          .driver_data = board_ahci_yes_fbs },                  /* 88se9172 */
         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
           .driver_data = board_ahci_yes_fbs },                  /* 88se9172 on some Gigabyte */
         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index b830e6c9fe49..10b14d45cfd2 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -1,7 +1,7 @@
 /*
  *  ahci.h - Common AHCI SATA definitions and declarations
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
index 2f48123d74c4..9a8a674e8fac 100644
--- a/drivers/ata/ata_piix.c
+++ b/drivers/ata/ata_piix.c
@@ -1,7 +1,7 @@
 /*
  *    ata_piix.c - Intel PATA/SATA controllers
  *
- *    Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *    Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
@@ -151,6 +151,7 @@ enum piix_controller_ids {
         piix_pata_vmw,                  /* PIIX4 for VMware, spurious DMA_ERR */
         ich8_sata_snb,
         ich8_2port_sata_snb,
+        ich8_2port_sata_byt,
 };
 
 struct piix_map_db {
@@ -334,6 +335,9 @@ static const struct pci_device_id piix_pci_tbl[] = {
         { 0x8086, 0x8d60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
         /* SATA Controller IDE (Wellsburg) */
         { 0x8086, 0x8d68, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
+        /* SATA Controller IDE (BayTrail) */
+        { 0x8086, 0x0F20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
+        { 0x8086, 0x0F21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
 
         { }     /* terminate list */
 };
@@ -441,6 +445,7 @@ static const struct piix_map_db *piix_map_db_table[] = {
         [tolapai_sata]          = &tolapai_map_db,
         [ich8_sata_snb]         = &ich8_map_db,
         [ich8_2port_sata_snb]   = &ich8_2port_map_db,
+        [ich8_2port_sata_byt]   = &ich8_2port_map_db,
 };
 
 static struct pci_bits piix_enable_bits[] = {
@@ -1254,6 +1259,16 @@ static struct ata_port_info piix_port_info[] = {
                 .udma_mask      = ATA_UDMA6,
                 .port_ops       = &piix_sata_ops,
         },
+
+        [ich8_2port_sata_byt] =
+        {
+                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
+                .pio_mask       = ATA_PIO4,
+                .mwdma_mask     = ATA_MWDMA2,
+                .udma_mask      = ATA_UDMA6,
+                .port_ops       = &piix_sata_ops,
+        },
+
 };
 
 #define AHCI_PCI_BAR 5
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
index 34c82167b962..a70ff154f586 100644
--- a/drivers/ata/libahci.c
+++ b/drivers/ata/libahci.c
@@ -1,7 +1,7 @@
 /*
  *  libahci.c - Common AHCI SATA low-level routines
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 63c743baf920..f2184276539d 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -1,7 +1,7 @@
 /*
  *  libata-core.c - helper library for ATA
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
@@ -1602,6 +1602,12 @@ unsigned ata_exec_internal_sg(struct ata_device *dev,
         qc->tf = *tf;
         if (cdb)
                 memcpy(qc->cdb, cdb, ATAPI_CDB_LEN);
+
+        /* some SATA bridges need us to indicate data xfer direction */
+        if (tf->protocol == ATAPI_PROT_DMA && (dev->flags & ATA_DFLAG_DMADIR) &&
+            dma_dir == DMA_FROM_DEVICE)
+                qc->tf.feature |= ATAPI_DMADIR;
+
         qc->flags |= ATA_QCFLAG_RESULT_TF;
         qc->dma_dir = dma_dir;
         if (dma_dir != DMA_NONE) {
diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c
index f9476fb3ac43..c69fcce505c0 100644
--- a/drivers/ata/libata-eh.c
+++ b/drivers/ata/libata-eh.c
@@ -1,7 +1,7 @@
 /*
  *  libata-eh.c - libata error handling
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c
index dd310b27b24c..0101af541436 100644
--- a/drivers/ata/libata-scsi.c
+++ b/drivers/ata/libata-scsi.c
@@ -1,7 +1,7 @@
 /*
  *  libata-scsi.c - helper library for ATA
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
diff --git a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c
index d8af325a6bda..b603720b877d 100644
--- a/drivers/ata/libata-sff.c
+++ b/drivers/ata/libata-sff.c
@@ -1,7 +1,7 @@
 /*
  *  libata-sff.c - helper library for PCI IDE BMDMA
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
diff --git a/drivers/ata/pdc_adma.c b/drivers/ata/pdc_adma.c
index 505333340ad5..8ea6e6afd041 100644
--- a/drivers/ata/pdc_adma.c
+++ b/drivers/ata/pdc_adma.c
@@ -1,7 +1,7 @@
 /*
  *  pdc_adma.c - Pacific Digital Corporation ADMA
  *
- *  Maintained by:  Mark Lord <mlord@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *
  *  Copyright 2005 Mark Lord
  *
diff --git a/drivers/ata/sata_promise.c b/drivers/ata/sata_promise.c
index fb0dd87f8893..958ba2a420c3 100644
--- a/drivers/ata/sata_promise.c
+++ b/drivers/ata/sata_promise.c
@@ -1,7 +1,7 @@
 /*
  *  sata_promise.c - Promise SATA
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Mikael Pettersson <mikpe@it.uu.se>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c
index 4799868bd733..249c8a289bfd 100644
--- a/drivers/ata/sata_rcar.c
+++ b/drivers/ata/sata_rcar.c
@@ -549,6 +549,7 @@ static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc)
 
         /* start host DMA transaction */
         dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG);
+        dmactl &= ~ATAPI_CONTROL1_STOP;
         dmactl |= ATAPI_CONTROL1_START;
         iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG);
 }
@@ -618,17 +619,16 @@ static struct ata_port_operations sata_rcar_port_ops = {
         .bmdma_status           = sata_rcar_bmdma_status,
 };
 
-static int sata_rcar_serr_interrupt(struct ata_port *ap)
+static void sata_rcar_serr_interrupt(struct ata_port *ap)
 {
         struct sata_rcar_priv *priv = ap->host->private_data;
         struct ata_eh_info *ehi = &ap->link.eh_info;
         int freeze = 0;
-        int handled = 0;
         u32 serror;
 
         serror = ioread32(priv->base + SCRSERR_REG);
         if (!serror)
-                return 0;
+                return;
 
         DPRINTK("SError @host_intr: 0x%x\n", serror);
 
@@ -641,7 +641,6 @@ static int sata_rcar_serr_interrupt(struct ata_port *ap)
                 ata_ehi_push_desc(ehi, "%s", "hotplug");
 
                 freeze = serror & SERR_COMM_WAKE ? 0 : 1;
-                handled = 1;
         }
 
         /* freeze or abort */
@@ -649,11 +648,9 @@ static int sata_rcar_serr_interrupt(struct ata_port *ap)
                 ata_port_freeze(ap);
         else
                 ata_port_abort(ap);
-
-        return handled;
 }
 
-static int sata_rcar_ata_interrupt(struct ata_port *ap)
+static void sata_rcar_ata_interrupt(struct ata_port *ap)
 {
         struct ata_queued_cmd *qc;
         int handled = 0;
@@ -662,7 +659,9 @@ static int sata_rcar_ata_interrupt(struct ata_port *ap)
         if (qc)
                 handled |= ata_bmdma_port_intr(ap, qc);
 
-        return handled;
+        /* be sure to clear ATA interrupt */
+        if (!handled)
+                sata_rcar_check_status(ap);
 }
 
 static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance)
@@ -677,20 +676,21 @@ static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance)
         spin_lock_irqsave(&host->lock, flags);
 
         sataintstat = ioread32(priv->base + SATAINTSTAT_REG);
+        sataintstat &= SATA_RCAR_INT_MASK;
         if (!sataintstat)
                 goto done;
         /* ack */
-        iowrite32(sataintstat & ~SATA_RCAR_INT_MASK,
-                 priv->base + SATAINTSTAT_REG);
+        iowrite32(~sataintstat & 0x7ff, priv->base + SATAINTSTAT_REG);
 
         ap = host->ports[0];
 
         if (sataintstat & SATAINTSTAT_ATA)
-                handled |= sata_rcar_ata_interrupt(ap);
+                sata_rcar_ata_interrupt(ap);
 
         if (sataintstat & SATAINTSTAT_SERR)
-                handled |= sata_rcar_serr_interrupt(ap);
+                sata_rcar_serr_interrupt(ap);
 
+        handled = 1;
 done:
         spin_unlock_irqrestore(&host->lock, flags);
 
diff --git a/drivers/ata/sata_sil.c b/drivers/ata/sata_sil.c
index a7b31672c4b7..0ae3ca4bf5c0 100644
--- a/drivers/ata/sata_sil.c
+++ b/drivers/ata/sata_sil.c
@@ -1,7 +1,7 @@
 /*
  *  sata_sil.c - Silicon Image SATA
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
diff --git a/drivers/ata/sata_sx4.c b/drivers/ata/sata_sx4.c
index 7b7127a58f51..9947010afc0f 100644
--- a/drivers/ata/sata_sx4.c
+++ b/drivers/ata/sata_sx4.c
@@ -1,7 +1,7 @@
 /*
  *  sata_sx4.c - Promise SATA
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
diff --git a/drivers/ata/sata_via.c b/drivers/ata/sata_via.c
index 5913ea9d57b2..87f056e54a9d 100644
--- a/drivers/ata/sata_via.c
+++ b/drivers/ata/sata_via.c
@@ -1,7 +1,7 @@
 /*
  *  sata_via.c - VIA Serial ATA controllers
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                 Please ALWAYS copy linux-ide@vger.kernel.org
  *                 on emails.
  *
diff --git a/drivers/base/regmap/regcache-rbtree.c b/drivers/base/regmap/regcache-rbtree.c
index aa0875f6f1b7..02f490bad30f 100644
--- a/drivers/base/regmap/regcache-rbtree.c
+++ b/drivers/base/regmap/regcache-rbtree.c
@@ -143,7 +143,7 @@ static int rbtree_show(struct seq_file *s, void *ignored)
         int registers = 0;
         int this_registers, average;
 
-        map->lock(map);
+        map->lock(map->lock_arg);
 
         mem_size = sizeof(*rbtree_ctx);
         mem_size += BITS_TO_LONGS(map->cache_present_nbits) * sizeof(long);
@@ -170,7 +170,7 @@ static int rbtree_show(struct seq_file *s, void *ignored)
         seq_printf(s, "%d nodes, %d registers, average %d registers, used %zu bytes\n",
                    nodes, registers, average, mem_size);
 
-        map->unlock(map);
+        map->unlock(map->lock_arg);
 
         return 0;
 }
@@ -391,8 +391,6 @@ static int regcache_rbtree_sync(struct regmap *map, unsigned int min,
         for (node = rb_first(&rbtree_ctx->root); node; node = rb_next(node)) {
                 rbnode = rb_entry(node, struct regcache_rbtree_node, node);
 
-                if (rbnode->base_reg < min)
-                        continue;
                 if (rbnode->base_reg > max)
                         break;
                 if (rbnode->base_reg + rbnode->blklen < min)
diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c
index 75923f2396bd..507ee2da0f6e 100644
--- a/drivers/base/regmap/regcache.c
+++ b/drivers/base/regmap/regcache.c
@@ -270,7 +270,7 @@ int regcache_sync(struct regmap *map)
 
         BUG_ON(!map->cache_ops || !map->cache_ops->sync);
 
-        map->lock(map);
+        map->lock(map->lock_arg);
         /* Remember the initial bypass state */
         bypass = map->cache_bypass;
         dev_dbg(map->dev, "Syncing %s cache\n",
@@ -306,7 +306,7 @@ out:
         trace_regcache_sync(map->dev, name, "stop");
         /* Restore the bypass state */
         map->cache_bypass = bypass;
-        map->unlock(map);
+        map->unlock(map->lock_arg);
 
         return ret;
 }
@@ -333,7 +333,7 @@ int regcache_sync_region(struct regmap *map, unsigned int min,
 
         BUG_ON(!map->cache_ops || !map->cache_ops->sync);
 
-        map->lock(map);
+        map->lock(map->lock_arg);
 
         /* Remember the initial bypass state */
         bypass = map->cache_bypass;
@@ -352,7 +352,7 @@ out:
         trace_regcache_sync(map->dev, name, "stop region");
         /* Restore the bypass state */
         map->cache_bypass = bypass;
-        map->unlock(map);
+        map->unlock(map->lock_arg);
 
         return ret;
 }
@@ -372,11 +372,11 @@ EXPORT_SYMBOL_GPL(regcache_sync_region);
  */
 void regcache_cache_only(struct regmap *map, bool enable)
 {
-        map->lock(map);
+        map->lock(map->lock_arg);
         WARN_ON(map->cache_bypass && enable);
         map->cache_only = enable;
         trace_regmap_cache_only(map->dev, enable);
-        map->unlock(map);
+        map->unlock(map->lock_arg);
 }
 EXPORT_SYMBOL_GPL(regcache_cache_only);
 
@@ -391,9 +391,9 @@ EXPORT_SYMBOL_GPL(regcache_cache_only);
  */
 void regcache_mark_dirty(struct regmap *map)
 {
-        map->lock(map);
+        map->lock(map->lock_arg);
         map->cache_dirty = true;
-        map->unlock(map);
+        map->unlock(map->lock_arg);
 }
 EXPORT_SYMBOL_GPL(regcache_mark_dirty);
 
@@ -410,11 +410,11 @@ EXPORT_SYMBOL_GPL(regcache_mark_dirty);
  */
 void regcache_cache_bypass(struct regmap *map, bool enable)
 {
-        map->lock(map);
+        map->lock(map->lock_arg);
         WARN_ON(map->cache_only && enable);
         map->cache_bypass = enable;
         trace_regmap_cache_bypass(map->dev, enable);
-        map->unlock(map);
+        map->unlock(map->lock_arg);
 }
 EXPORT_SYMBOL_GPL(regcache_cache_bypass);
 
diff --git a/drivers/base/regmap/regmap-debugfs.c b/drivers/base/regmap/regmap-debugfs.c
index 23b701f5fd2f..975719bc3450 100644
--- a/drivers/base/regmap/regmap-debugfs.c
+++ b/drivers/base/regmap/regmap-debugfs.c
@@ -265,6 +265,7 @@ static ssize_t regmap_map_write_file(struct file *file,
         char *start = buf;
         unsigned long reg, value;
         struct regmap *map = file->private_data;
+        int ret;
 
         buf_size = min(count, (sizeof(buf)-1));
         if (copy_from_user(buf, user_buf, buf_size))
@@ -282,7 +283,9 @@ static ssize_t regmap_map_write_file(struct file *file,
         /* Userspace has been fiddling around behind the kernel's back */
         add_taint(TAINT_USER, LOCKDEP_NOW_UNRELIABLE);
 
-        regmap_write(map, reg, value);
+        ret = regmap_write(map, reg, value);
+        if (ret < 0)
+                return ret;
         return buf_size;
 }
 #else
diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c
index 6374dc103521..62b6c2cc80b5 100644
--- a/drivers/block/cciss.c
+++ b/drivers/block/cciss.c
@@ -168,8 +168,6 @@ static irqreturn_t do_cciss_msix_intr(int irq, void *dev_id);
 static int cciss_open(struct block_device *bdev, fmode_t mode);
 static int cciss_unlocked_open(struct block_device *bdev, fmode_t mode);
 static void cciss_release(struct gendisk *disk, fmode_t mode);
-static int do_ioctl(struct block_device *bdev, fmode_t mode,
-                    unsigned int cmd, unsigned long arg);
 static int cciss_ioctl(struct block_device *bdev, fmode_t mode,
                        unsigned int cmd, unsigned long arg);
 static int cciss_getgeo(struct block_device *bdev, struct hd_geometry *geo);
@@ -235,7 +233,7 @@ static const struct block_device_operations cciss_fops = {
         .owner = THIS_MODULE,
         .open = cciss_unlocked_open,
         .release = cciss_release,
-        .ioctl = do_ioctl,
+        .ioctl = cciss_ioctl,
         .getgeo = cciss_getgeo,
 #ifdef CONFIG_COMPAT
         .compat_ioctl = cciss_compat_ioctl,
@@ -1143,16 +1141,6 @@ static void cciss_release(struct gendisk *disk, fmode_t mode)
         mutex_unlock(&cciss_mutex);
 }
 
-static int do_ioctl(struct block_device *bdev, fmode_t mode,
-                    unsigned cmd, unsigned long arg)
-{
-        int ret;
-        mutex_lock(&cciss_mutex);
-        ret = cciss_ioctl(bdev, mode, cmd, arg);
-        mutex_unlock(&cciss_mutex);
-        return ret;
-}
-
 #ifdef CONFIG_COMPAT
 
 static int cciss_ioctl32_passthru(struct block_device *bdev, fmode_t mode,
@@ -1179,7 +1167,7 @@ static int cciss_compat_ioctl(struct block_device *bdev, fmode_t mode,
         case CCISS_REGNEWD:
         case CCISS_RESCANDISK:
         case CCISS_GETLUNINFO:
-                return do_ioctl(bdev, mode, cmd, arg);
+                return cciss_ioctl(bdev, mode, cmd, arg);
 
         case CCISS_PASSTHRU32:
                 return cciss_ioctl32_passthru(bdev, mode, cmd, arg);
@@ -1219,7 +1207,7 @@ static int cciss_ioctl32_passthru(struct block_device *bdev, fmode_t mode,
         if (err)
                 return -EFAULT;
 
-        err = do_ioctl(bdev, mode, CCISS_PASSTHRU, (unsigned long)p);
+        err = cciss_ioctl(bdev, mode, CCISS_PASSTHRU, (unsigned long)p);
         if (err)
                 return err;
         err |=
@@ -1261,7 +1249,7 @@ static int cciss_ioctl32_big_passthru(struct block_device *bdev, fmode_t mode,
         if (err)
                 return -EFAULT;
 
-        err = do_ioctl(bdev, mode, CCISS_BIG_PASSTHRU, (unsigned long)p);
+        err = cciss_ioctl(bdev, mode, CCISS_BIG_PASSTHRU, (unsigned long)p);
         if (err)
                 return err;
         err |=
@@ -1311,11 +1299,14 @@ static int cciss_getpciinfo(ctlr_info_t *h, void __user *argp)
 static int cciss_getintinfo(ctlr_info_t *h, void __user *argp)
 {
         cciss_coalint_struct intinfo;
+        unsigned long flags;
 
         if (!argp)
                 return -EINVAL;
+        spin_lock_irqsave(&h->lock, flags);
         intinfo.delay = readl(&h->cfgtable->HostWrite.CoalIntDelay);
         intinfo.count = readl(&h->cfgtable->HostWrite.CoalIntCount);
+        spin_unlock_irqrestore(&h->lock, flags);
         if (copy_to_user
             (argp, &intinfo, sizeof(cciss_coalint_struct)))
                 return -EFAULT;
@@ -1356,12 +1347,15 @@ static int cciss_setintinfo(ctlr_info_t *h, void __user *argp)
 static int cciss_getnodename(ctlr_info_t *h, void __user *argp)
 {
         NodeName_type NodeName;
+        unsigned long flags;
         int i;
 
         if (!argp)
                 return -EINVAL;
+        spin_lock_irqsave(&h->lock, flags);
         for (i = 0; i < 16; i++)
                 NodeName[i] = readb(&h->cfgtable->ServerName[i]);
+        spin_unlock_irqrestore(&h->lock, flags);
         if (copy_to_user(argp, NodeName, sizeof(NodeName_type)))
                 return -EFAULT;
         return 0;
@@ -1398,10 +1392,13 @@ static int cciss_setnodename(ctlr_info_t *h, void __user *argp)
 static int cciss_getheartbeat(ctlr_info_t *h, void __user *argp)
 {
         Heartbeat_type heartbeat;
+        unsigned long flags;
 
         if (!argp)
                 return -EINVAL;
+        spin_lock_irqsave(&h->lock, flags);
         heartbeat = readl(&h->cfgtable->HeartBeat);
+        spin_unlock_irqrestore(&h->lock, flags);
         if (copy_to_user(argp, &heartbeat, sizeof(Heartbeat_type)))
                 return -EFAULT;
         return 0;
@@ -1410,10 +1407,13 @@ static int cciss_getheartbeat(ctlr_info_t *h, void __user *argp)
 static int cciss_getbustypes(ctlr_info_t *h, void __user *argp)
 {
         BusTypes_type BusTypes;
+        unsigned long flags;
 
         if (!argp)
                 return -EINVAL;
+        spin_lock_irqsave(&h->lock, flags);
         BusTypes = readl(&h->cfgtable->BusTypes);
+        spin_unlock_irqrestore(&h->lock, flags);
         if (copy_to_user(argp, &BusTypes, sizeof(BusTypes_type)))
                 return -EFAULT;
         return 0;
diff --git a/drivers/block/mtip32xx/mtip32xx.c b/drivers/block/mtip32xx/mtip32xx.c
index 847107ef0cce..20dd52a2f92f 100644
--- a/drivers/block/mtip32xx/mtip32xx.c
+++ b/drivers/block/mtip32xx/mtip32xx.c
@@ -3002,7 +3002,8 @@ static int mtip_hw_debugfs_init(struct driver_data *dd)
 
 static void mtip_hw_debugfs_exit(struct driver_data *dd)
 {
-        debugfs_remove_recursive(dd->dfs_node);
+        if (dd->dfs_node)
+                debugfs_remove_recursive(dd->dfs_node);
 }
 
 
@@ -3863,7 +3864,7 @@ static void mtip_make_request(struct request_queue *queue, struct bio *bio)
         struct driver_data *dd = queue->queuedata;
         struct scatterlist *sg;
         struct bio_vec *bvec;
-        int nents = 0;
+        int i, nents = 0;
         int tag = 0, unaligned = 0;
 
         if (unlikely(dd->dd_flag & MTIP_DDF_STOP_IO)) {
@@ -3921,11 +3922,12 @@ static void mtip_make_request(struct request_queue *queue, struct bio *bio)
                 }
 
                 /* Create the scatter list for this bio. */
-                bio_for_each_segment(bvec, bio, nents) {
+                bio_for_each_segment(bvec, bio, i) {
                         sg_set_page(&sg[nents],
                                         bvec->bv_page,
                                         bvec->bv_len,
                                         bvec->bv_offset);
+                        nents++;
                 }
 
                 /* Issue the read/write. */
diff --git a/drivers/block/nvme-core.c b/drivers/block/nvme-core.c
index 8efdfaa44a59..ce79a590b45b 100644
--- a/drivers/block/nvme-core.c
+++ b/drivers/block/nvme-core.c
@@ -629,7 +629,7 @@ static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
         struct nvme_command *cmnd;
         struct nvme_iod *iod;
         enum dma_data_direction dma_dir;
-        int cmdid, length, result = -ENOMEM;
+        int cmdid, length, result;
         u16 control;
         u32 dsmgmt;
         int psegs = bio_phys_segments(ns->queue, bio);
@@ -640,6 +640,7 @@ static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
                         return result;
         }
 
+        result = -ENOMEM;
         iod = nvme_alloc_iod(psegs, bio->bi_size, GFP_ATOMIC);
         if (!iod)
                 goto nomem;
@@ -977,6 +978,8 @@ static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
 
                 if (timeout && !time_after(now, info[cmdid].timeout))
                         continue;
+                if (info[cmdid].ctx == CMD_CTX_CANCELLED)
+                        continue;
                 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d\n", cmdid);
                 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
                 fn(nvmeq->dev, ctx, &cqe);
@@ -1206,7 +1209,7 @@ struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
 
         if (addr & 3)
                 return ERR_PTR(-EINVAL);
-        if (!length)
+        if (!length || length > INT_MAX - PAGE_SIZE)
                 return ERR_PTR(-EINVAL);
 
         offset = offset_in_page(addr);
@@ -1227,7 +1230,8 @@ struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
         sg_init_table(sg, count);
         for (i = 0; i < count; i++) {
                 sg_set_page(&sg[i], pages[i],
-                                min_t(int, length, PAGE_SIZE - offset), offset);
+                            min_t(unsigned, length, PAGE_SIZE - offset),
+                            offset);
                 length -= (PAGE_SIZE - offset);
                 offset = 0;
         }
@@ -1435,7 +1439,7 @@ static int nvme_user_admin_cmd(struct nvme_dev *dev,
                 nvme_free_iod(dev, iod);
         }
 
-        if (!status && copy_to_user(&ucmd->result, &cmd.result,
+        if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
                                                         sizeof(cmd.result)))
                 status = -EFAULT;
 
@@ -1633,7 +1637,8 @@ static int set_queue_count(struct nvme_dev *dev, int count)
 
 static int nvme_setup_io_queues(struct nvme_dev *dev)
 {
-        int result, cpu, i, nr_io_queues, db_bar_size, q_depth;
+        struct pci_dev *pdev = dev->pci_dev;
+        int result, cpu, i, nr_io_queues, db_bar_size, q_depth, q_count;
 
         nr_io_queues = num_online_cpus();
         result = set_queue_count(dev, nr_io_queues);
@@ -1642,14 +1647,14 @@ static int nvme_setup_io_queues(struct nvme_dev *dev)
         if (result < nr_io_queues)
                 nr_io_queues = result;
 
+        q_count = nr_io_queues;
         /* Deregister the admin queue's interrupt */
         free_irq(dev->entry[0].vector, dev->queues[0]);
 
         db_bar_size = 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3));
         if (db_bar_size > 8192) {
                 iounmap(dev->bar);
-                dev->bar = ioremap(pci_resource_start(dev->pci_dev, 0),
-                                                                db_bar_size);
+                dev->bar = ioremap(pci_resource_start(pdev, 0), db_bar_size);
                 dev->dbs = ((void __iomem *)dev->bar) + 4096;
                 dev->queues[0]->q_db = dev->dbs;
         }
@@ -1657,19 +1662,36 @@ static int nvme_setup_io_queues(struct nvme_dev *dev)
         for (i = 0; i < nr_io_queues; i++)
                 dev->entry[i].entry = i;
         for (;;) {
-                result = pci_enable_msix(dev->pci_dev, dev->entry,
-                                                                nr_io_queues);
+                result = pci_enable_msix(pdev, dev->entry, nr_io_queues);
                 if (result == 0) {
                         break;
                 } else if (result > 0) {
                         nr_io_queues = result;
                         continue;
                 } else {
-                        nr_io_queues = 1;
+                        nr_io_queues = 0;
                         break;
                 }
         }
 
+        if (nr_io_queues == 0) {
+                nr_io_queues = q_count;
+                for (;;) {
+                        result = pci_enable_msi_block(pdev, nr_io_queues);
+                        if (result == 0) {
+                                for (i = 0; i < nr_io_queues; i++)
+                                        dev->entry[i].vector = i + pdev->irq;
+                                break;
+                        } else if (result > 0) {
+                                nr_io_queues = result;
+                                continue;
+                        } else {
+                                nr_io_queues = 1;
+                                break;
+                        }
+                }
+        }
+
         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
         /* XXX: handle failure here */
 
@@ -1850,7 +1872,10 @@ static void nvme_free_dev(struct kref *kref)
 {
         struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
         nvme_dev_remove(dev);
-        pci_disable_msix(dev->pci_dev);
+        if (dev->pci_dev->msi_enabled)
+                pci_disable_msi(dev->pci_dev);
+        else if (dev->pci_dev->msix_enabled)
+                pci_disable_msix(dev->pci_dev);
         iounmap(dev->bar);
         nvme_release_instance(dev);
         nvme_release_prp_pools(dev);
@@ -1923,8 +1948,14 @@ static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
         INIT_LIST_HEAD(&dev->namespaces);
         dev->pci_dev = pdev;
         pci_set_drvdata(pdev, dev);
-        dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
-        dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
+
+        if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)))
+                dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
+        else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)))
+                dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
+        else
+                goto disable;
+
         result = nvme_set_instance(dev);
         if (result)
                 goto disable;
@@ -1977,7 +2008,10 @@ static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  unmap:
         iounmap(dev->bar);
  disable_msix:
-        pci_disable_msix(pdev);
+        if (dev->pci_dev->msi_enabled)
+                pci_disable_msi(dev->pci_dev);
+        else if (dev->pci_dev->msix_enabled)
+                pci_disable_msix(dev->pci_dev);
         nvme_release_instance(dev);
         nvme_release_prp_pools(dev);
  disable:
diff --git a/drivers/block/nvme-scsi.c b/drivers/block/nvme-scsi.c
index fed54b039893..102de2f52b5c 100644
--- a/drivers/block/nvme-scsi.c
+++ b/drivers/block/nvme-scsi.c
@@ -44,7 +44,6 @@
 #include <linux/sched.h>
 #include <linux/slab.h>
 #include <linux/types.h>
-#include <linux/version.h>
 #include <scsi/sg.h>
 #include <scsi/scsi.h>
 
@@ -1654,7 +1653,7 @@ static void nvme_trans_modesel_save_bd(struct nvme_ns *ns, u8 *parm_list,
         }
 }
 
-static u16 nvme_trans_modesel_get_mp(struct nvme_ns *ns, struct sg_io_hdr *hdr,
+static int nvme_trans_modesel_get_mp(struct nvme_ns *ns, struct sg_io_hdr *hdr,
                                         u8 *mode_page, u8 page_code)
 {
         int res = SNTI_TRANSLATION_SUCCESS;
diff --git a/drivers/block/pktcdvd.c b/drivers/block/pktcdvd.c
index 3c08983e600a..f5d0ea11d9fd 100644
--- a/drivers/block/pktcdvd.c
+++ b/drivers/block/pktcdvd.c
@@ -83,7 +83,8 @@
 
 #define MAX_SPEED 0xffff
 
-#define ZONE(sector, pd) (((sector) + (pd)->offset) & ~((pd)->settings.size - 1))
+#define ZONE(sector, pd) (((sector) + (pd)->offset) & \
+                        ~(sector_t)((pd)->settings.size - 1))
 
 static DEFINE_MUTEX(pktcdvd_mutex);
 static struct pktcdvd_device *pkt_devs[MAX_WRITERS];
diff --git a/drivers/block/rbd.c b/drivers/block/rbd.c
index d6d314027b5d..3063452e55da 100644
--- a/drivers/block/rbd.c
+++ b/drivers/block/rbd.c
@@ -519,8 +519,8 @@ static const struct block_device_operations rbd_bd_ops = {
 };
 
 /*
- * Initialize an rbd client instance.
- * We own *ceph_opts.
+ * Initialize an rbd client instance.  Success or not, this function
+ * consumes ceph_opts.
  */
 static struct rbd_client *rbd_client_create(struct ceph_options *ceph_opts)
 {
@@ -675,7 +675,8 @@ static int parse_rbd_opts_token(char *c, void *private)
 
 /*
  * Get a ceph client with specific addr and configuration, if one does
- * not exist create it.
+ * not exist create it.  Either way, ceph_opts is consumed by this
+ * function.
  */
 static struct rbd_client *rbd_get_client(struct ceph_options *ceph_opts)
 {
@@ -4697,8 +4698,10 @@ out:
         return ret;
 }
 
-/* Undo whatever state changes are made by v1 or v2 image probe */
-
+/*
+ * Undo whatever state changes are made by v1 or v2 header info
+ * call.
+ */
 static void rbd_dev_unprobe(struct rbd_device *rbd_dev)
 {
         struct rbd_image_header *header;
@@ -4902,9 +4905,10 @@ static int rbd_dev_image_probe(struct rbd_device *rbd_dev, bool mapping)
         int tmp;
 
         /*
-         * Get the id from the image id object.  If it's not a
-         * format 2 image, we'll get ENOENT back, and we'll assume
-         * it's a format 1 image.
+         * Get the id from the image id object.  Unless there's an
+         * error, rbd_dev->spec->image_id will be filled in with
+         * a dynamically-allocated string, and rbd_dev->image_format
+         * will be set to either 1 or 2.
          */
         ret = rbd_dev_image_id(rbd_dev);
         if (ret)
@@ -4992,7 +4996,6 @@ static ssize_t rbd_add(struct bus_type *bus,
                 rc = PTR_ERR(rbdc);
                 goto err_out_args;
         }
-        ceph_opts = NULL;       /* rbd_dev client now owns this */
 
         /* pick the pool */
         osdc = &rbdc->client->osdc;
@@ -5027,18 +5030,18 @@ static ssize_t rbd_add(struct bus_type *bus,
         rbd_dev->mapping.read_only = read_only;
 
         rc = rbd_dev_device_setup(rbd_dev);
-        if (!rc)
-                return count;
+        if (rc) {
+                rbd_dev_image_release(rbd_dev);
+                goto err_out_module;
+        }
+
+        return count;
 
-        rbd_dev_image_release(rbd_dev);
 err_out_rbd_dev:
         rbd_dev_destroy(rbd_dev);
 err_out_client:
         rbd_put_client(rbdc);
 err_out_args:
-        if (ceph_opts)
-                ceph_destroy_options(ceph_opts);
-        kfree(rbd_opts);
         rbd_spec_put(spec);
 err_out_module:
         module_put(THIS_MODULE);
diff --git a/drivers/bluetooth/Kconfig b/drivers/bluetooth/Kconfig
index fdfd61a2d523..11a6104a1e4f 100644
--- a/drivers/bluetooth/Kconfig
+++ b/drivers/bluetooth/Kconfig
@@ -201,7 +201,7 @@ config BT_MRVL
           The core driver to support Marvell Bluetooth devices.
 
           This driver is required if you want to support
-          Marvell Bluetooth devices, such as 8688/8787/8797.
+          Marvell Bluetooth devices, such as 8688/8787/8797/8897.
 
           Say Y here to compile Marvell Bluetooth driver
           into the kernel or say M to compile it as module.
@@ -214,7 +214,7 @@ config BT_MRVL_SDIO
           The driver for Marvell Bluetooth chipsets with SDIO interface.
 
           This driver is required if you want to use Marvell Bluetooth
-          devices with SDIO interface. Currently SD8688/SD8787/SD8797
+          devices with SDIO interface. Currently SD8688/SD8787/SD8797/SD8897
           chipsets are supported.
 
           Say Y here to compile support for Marvell BT-over-SDIO driver
diff --git a/drivers/bluetooth/btmrvl_sdio.c b/drivers/bluetooth/btmrvl_sdio.c
index c63488c54f4a..13693b7a0d5c 100644
--- a/drivers/bluetooth/btmrvl_sdio.c
+++ b/drivers/bluetooth/btmrvl_sdio.c
@@ -82,6 +82,23 @@ static const struct btmrvl_sdio_card_reg btmrvl_reg_87xx = {
         .io_port_2 = 0x7a,
 };
 
+static const struct btmrvl_sdio_card_reg btmrvl_reg_88xx = {
+        .cfg = 0x00,
+        .host_int_mask = 0x02,
+        .host_intstatus = 0x03,
+        .card_status = 0x50,
+        .sq_read_base_addr_a0 = 0x60,
+        .sq_read_base_addr_a1 = 0x61,
+        .card_revision = 0xbc,
+        .card_fw_status0 = 0xc0,
+        .card_fw_status1 = 0xc1,
+        .card_rx_len = 0xc2,
+        .card_rx_unit = 0xc3,
+        .io_port_0 = 0xd8,
+        .io_port_1 = 0xd9,
+        .io_port_2 = 0xda,
+};
+
 static const struct btmrvl_sdio_device btmrvl_sdio_sd8688 = {
         .helper         = "mrvl/sd8688_helper.bin",
         .firmware       = "mrvl/sd8688.bin",
@@ -103,6 +120,13 @@ static const struct btmrvl_sdio_device btmrvl_sdio_sd8797 = {
         .sd_blksz_fw_dl = 256,
 };
 
+static const struct btmrvl_sdio_device btmrvl_sdio_sd8897 = {
+        .helper         = NULL,
+        .firmware       = "mrvl/sd8897_uapsta.bin",
+        .reg            = &btmrvl_reg_88xx,
+        .sd_blksz_fw_dl = 256,
+};
+
 static const struct sdio_device_id btmrvl_sdio_ids[] = {
         /* Marvell SD8688 Bluetooth device */
         { SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, 0x9105),
@@ -116,6 +140,9 @@ static const struct sdio_device_id btmrvl_sdio_ids[] = {
         /* Marvell SD8797 Bluetooth device */
         { SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, 0x912A),
                         .driver_data = (unsigned long) &btmrvl_sdio_sd8797 },
+        /* Marvell SD8897 Bluetooth device */
+        { SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, 0x912E),
+                        .driver_data = (unsigned long) &btmrvl_sdio_sd8897 },
 
         { }     /* Terminating entry */
 };
@@ -1194,3 +1221,4 @@ MODULE_FIRMWARE("mrvl/sd8688_helper.bin");
 MODULE_FIRMWARE("mrvl/sd8688.bin");
 MODULE_FIRMWARE("mrvl/sd8787_uapsta.bin");
 MODULE_FIRMWARE("mrvl/sd8797_uapsta.bin");
+MODULE_FIRMWARE("mrvl/sd8897_uapsta.bin");
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index b05ecab915c4..5286e2d333b0 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -26,4 +26,11 @@ config OMAP_INTERCONNECT
 
         help
           Driver to enable OMAP interconnect error handling driver.
+
+config ARM_CCI
+        bool "ARM CCI driver support"
+        depends on ARM
+        help
+          Driver supporting the CCI cache coherent interconnect for ARM
+          platforms.
 endmenu
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 3c7b53c12091..670cea443802 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -7,3 +7,5 @@ obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
 
 # Interconnect bus driver for OMAP SoCs.
 obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
+# CCI cache coherent interconnect for ARM platforms
+obj-$(CONFIG_ARM_CCI)           += arm-cci.o
diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
new file mode 100644
index 000000000000..733288967d4d
--- /dev/null
+++ b/drivers/bus/arm-cci.c
@@ -0,0 +1,533 @@
+/*
+ * CCI cache coherent interconnect driver
+ *
+ * Copyright (C) 2013 ARM Ltd.
+ * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/arm-cci.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
+
+#define CCI_PORT_CTRL           0x0
+#define CCI_CTRL_STATUS         0xc
+
+#define CCI_ENABLE_SNOOP_REQ    0x1
+#define CCI_ENABLE_DVM_REQ      0x2
+#define CCI_ENABLE_REQ          (CCI_ENABLE_SNOOP_REQ | CCI_ENABLE_DVM_REQ)
+
+struct cci_nb_ports {
+        unsigned int nb_ace;
+        unsigned int nb_ace_lite;
+};
+
+enum cci_ace_port_type {
+        ACE_INVALID_PORT = 0x0,
+        ACE_PORT,
+        ACE_LITE_PORT,
+};
+
+struct cci_ace_port {
+        void __iomem *base;
+        unsigned long phys;
+        enum cci_ace_port_type type;
+        struct device_node *dn;
+};
+
+static struct cci_ace_port *ports;
+static unsigned int nb_cci_ports;
+
+static void __iomem *cci_ctrl_base;
+static unsigned long cci_ctrl_phys;
+
+struct cpu_port {
+        u64 mpidr;
+        u32 port;
+};
+
+/*
+ * Use the port MSB as valid flag, shift can be made dynamic
+ * by computing number of bits required for port indexes.
+ * Code disabling CCI cpu ports runs with D-cache invalidated
+ * and SCTLR bit clear so data accesses must be kept to a minimum
+ * to improve performance; for now shift is left static to
+ * avoid one more data access while disabling the CCI port.
+ */
+#define PORT_VALID_SHIFT        31
+#define PORT_VALID              (0x1 << PORT_VALID_SHIFT)
+
+static inline void init_cpu_port(struct cpu_port *port, u32 index, u64 mpidr)
+{
+        port->port = PORT_VALID | index;
+        port->mpidr = mpidr;
+}
+
+static inline bool cpu_port_is_valid(struct cpu_port *port)
+{
+        return !!(port->port & PORT_VALID);
+}
+
+static inline bool cpu_port_match(struct cpu_port *port, u64 mpidr)
+{
+        return port->mpidr == (mpidr & MPIDR_HWID_BITMASK);
+}
+
+static struct cpu_port cpu_port[NR_CPUS];
+
+/**
+ * __cci_ace_get_port - Function to retrieve the port index connected to
+ *                      a cpu or device.
+ *
+ * @dn: device node of the device to look-up
+ * @type: port type
+ *
+ * Return value:
+ *      - CCI port index if success
+ *      - -ENODEV if failure
+ */
+static int __cci_ace_get_port(struct device_node *dn, int type)
+{
+        int i;
+        bool ace_match;
+        struct device_node *cci_portn;
+
+        cci_portn = of_parse_phandle(dn, "cci-control-port", 0);
+        for (i = 0; i < nb_cci_ports; i++) {
+                ace_match = ports[i].type == type;
+                if (ace_match && cci_portn == ports[i].dn)
+                        return i;
+        }
+        return -ENODEV;
+}
+
+int cci_ace_get_port(struct device_node *dn)
+{
+        return __cci_ace_get_port(dn, ACE_LITE_PORT);
+}
+EXPORT_SYMBOL_GPL(cci_ace_get_port);
+
+static void __init cci_ace_init_ports(void)
+{
+        int port, ac, cpu;
+        u64 hwid;
+        const u32 *cell;
+        struct device_node *cpun, *cpus;
+
+        cpus = of_find_node_by_path("/cpus");
+        if (WARN(!cpus, "Missing cpus node, bailing out\n"))
+                return;
+
+        if (WARN_ON(of_property_read_u32(cpus, "#address-cells", &ac)))
+                ac = of_n_addr_cells(cpus);
+
+        /*
+         * Port index look-up speeds up the function disabling ports by CPU,
+         * since the logical to port index mapping is done once and does
+         * not change after system boot.
+         * The stashed index array is initialized for all possible CPUs
+         * at probe time.
+         */
+        for_each_child_of_node(cpus, cpun) {
+                if (of_node_cmp(cpun->type, "cpu"))
+                        continue;
+                cell = of_get_property(cpun, "reg", NULL);
+                if (WARN(!cell, "%s: missing reg property\n", cpun->full_name))
+                        continue;
+
+                hwid = of_read_number(cell, ac);
+                cpu = get_logical_index(hwid & MPIDR_HWID_BITMASK);
+
+                if (cpu < 0 || !cpu_possible(cpu))
+                        continue;
+                port = __cci_ace_get_port(cpun, ACE_PORT);
+                if (port < 0)
+                        continue;
+
+                init_cpu_port(&cpu_port[cpu], port, cpu_logical_map(cpu));
+        }
+
+        for_each_possible_cpu(cpu) {
+                WARN(!cpu_port_is_valid(&cpu_port[cpu]),
+                        "CPU %u does not have an associated CCI port\n",
+                        cpu);
+        }
+}
+/*
+ * Functions to enable/disable a CCI interconnect slave port
+ *
+ * They are called by low-level power management code to disable slave
+ * interfaces snoops and DVM broadcast.
+ * Since they may execute with cache data allocation disabled and
+ * after the caches have been cleaned and invalidated the functions provide
+ * no explicit locking since they may run with D-cache disabled, so normal
+ * cacheable kernel locks based on ldrex/strex may not work.
+ * Locking has to be provided by BSP implementations to ensure proper
+ * operations.
+ */
+
+/**
+ * cci_port_control() - function to control a CCI port
+ *
+ * @port: index of the port to setup
+ * @enable: if true enables the port, if false disables it
+ */
+static void notrace cci_port_control(unsigned int port, bool enable)
+{
+        void __iomem *base = ports[port].base;
+
+        writel_relaxed(enable ? CCI_ENABLE_REQ : 0, base + CCI_PORT_CTRL);
+        /*
+         * This function is called from power down procedures
+         * and must not execute any instruction that might
+         * cause the processor to be put in a quiescent state
+         * (eg wfi). Hence, cpu_relax() can not be added to this
+         * read loop to optimize power, since it might hide possibly
+         * disruptive operations.
+         */
+        while (readl_relaxed(cci_ctrl_base + CCI_CTRL_STATUS) & 0x1)
+                        ;
+}
+
+/**
+ * cci_disable_port_by_cpu() - function to disable a CCI port by CPU
+ *                             reference
+ *
+ * @mpidr: mpidr of the CPU whose CCI port should be disabled
+ *
+ * Disabling a CCI port for a CPU implies disabling the CCI port
+ * controlling that CPU cluster. Code disabling CPU CCI ports
+ * must make sure that the CPU running the code is the last active CPU
+ * in the cluster ie all other CPUs are quiescent in a low power state.
+ *
+ * Return:
+ *      0 on success
+ *      -ENODEV on port look-up failure
+ */
+int notrace cci_disable_port_by_cpu(u64 mpidr)
+{
+        int cpu;
+        bool is_valid;
+        for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
+                is_valid = cpu_port_is_valid(&cpu_port[cpu]);
+                if (is_valid && cpu_port_match(&cpu_port[cpu], mpidr)) {
+                        cci_port_control(cpu_port[cpu].port, false);
+                        return 0;
+                }
+        }
+        return -ENODEV;
+}
+EXPORT_SYMBOL_GPL(cci_disable_port_by_cpu);
+
+/**
+ * cci_enable_port_for_self() - enable a CCI port for calling CPU
+ *
+ * Enabling a CCI port for the calling CPU implies enabling the CCI
+ * port controlling that CPU's cluster. Caller must make sure that the
+ * CPU running the code is the first active CPU in the cluster and all
+ * other CPUs are quiescent in a low power state  or waiting for this CPU
+ * to complete the CCI initialization.
+ *
+ * Because this is called when the MMU is still off and with no stack,
+ * the code must be position independent and ideally rely on callee
+ * clobbered registers only.  To achieve this we must code this function
+ * entirely in assembler.
+ *
+ * On success this returns with the proper CCI port enabled.  In case of
+ * any failure this never returns as the inability to enable the CCI is
+ * fatal and there is no possible recovery at this stage.
+ */
+asmlinkage void __naked cci_enable_port_for_self(void)
+{
+        asm volatile ("\n"
+"       .arch armv7-a\n"
+"       mrc     p15, 0, r0, c0, c0, 5   @ get MPIDR value \n"
+"       and     r0, r0, #"__stringify(MPIDR_HWID_BITMASK)" \n"
+"       adr     r1, 5f \n"
+"       ldr     r2, [r1] \n"
+"       add     r1, r1, r2              @ &cpu_port \n"
+"       add     ip, r1, %[sizeof_cpu_port] \n"
+
+        /* Loop over the cpu_port array looking for a matching MPIDR */
+"1:     ldr     r2, [r1, %[offsetof_cpu_port_mpidr_lsb]] \n"
+"       cmp     r2, r0                  @ compare MPIDR \n"
+"       bne     2f \n"
+
+        /* Found a match, now test port validity */
+"       ldr     r3, [r1, %[offsetof_cpu_port_port]] \n"
+"       tst     r3, #"__stringify(PORT_VALID)" \n"
+"       bne     3f \n"
+
+        /* no match, loop with the next cpu_port entry */
+"2:     add     r1, r1, %[sizeof_struct_cpu_port] \n"
+"       cmp     r1, ip                  @ done? \n"
+"       blo     1b \n"
+
+        /* CCI port not found -- cheaply try to stall this CPU */
+"cci_port_not_found: \n"
+"       wfi \n"
+"       wfe \n"
+"       b       cci_port_not_found \n"
+
+        /* Use matched port index to look up the corresponding ports entry */
+"3:     bic     r3, r3, #"__stringify(PORT_VALID)" \n"
+"       adr     r0, 6f \n"
+"       ldmia   r0, {r1, r2} \n"
+"       sub     r1, r1, r0              @ virt - phys \n"
+"       ldr     r0, [r0, r2]            @ *(&ports) \n"
+"       mov     r2, %[sizeof_struct_ace_port] \n"
+"       mla     r0, r2, r3, r0          @ &ports[index] \n"
+"       sub     r0, r0, r1              @ virt_to_phys() \n"
+
+        /* Enable the CCI port */
+"       ldr     r0, [r0, %[offsetof_port_phys]] \n"
+"       mov     r3, #"__stringify(CCI_ENABLE_REQ)" \n"
+"       str     r3, [r0, #"__stringify(CCI_PORT_CTRL)"] \n"
+
+        /* poll the status reg for completion */
+"       adr     r1, 7f \n"
+"       ldr     r0, [r1] \n"
+"       ldr     r0, [r0, r1]            @ cci_ctrl_base \n"
+"4:     ldr     r1, [r0, #"__stringify(CCI_CTRL_STATUS)"] \n"
+"       tst     r1, #1 \n"
+"       bne     4b \n"
+
+"       mov     r0, #0 \n"
+"       bx      lr \n"
+
+"       .align  2 \n"
+"5:     .word   cpu_port - . \n"
+"6:     .word   . \n"
+"       .word   ports - 6b \n"
+"7:     .word   cci_ctrl_phys - . \n"
+        : :
+        [sizeof_cpu_port] "i" (sizeof(cpu_port)),
+#ifndef __ARMEB__
+        [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)),
+#else
+        [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)+4),
+#endif
+        [offsetof_cpu_port_port] "i" (offsetof(struct cpu_port, port)),
+        [sizeof_struct_cpu_port] "i" (sizeof(struct cpu_port)),
+        [sizeof_struct_ace_port] "i" (sizeof(struct cci_ace_port)),
+        [offsetof_port_phys] "i" (offsetof(struct cci_ace_port, phys)) );
+
+        unreachable();
+}
+
+/**
+ * __cci_control_port_by_device() - function to control a CCI port by device
+ *                                  reference
+ *
+ * @dn: device node pointer of the device whose CCI port should be
+ *      controlled
+ * @enable: if true enables the port, if false disables it
+ *
+ * Return:
+ *      0 on success
+ *      -ENODEV on port look-up failure
+ */
+int notrace __cci_control_port_by_device(struct device_node *dn, bool enable)
+{
+        int port;
+
+        if (!dn)
+                return -ENODEV;
+
+        port = __cci_ace_get_port(dn, ACE_LITE_PORT);
+        if (WARN_ONCE(port < 0, "node %s ACE lite port look-up failure\n",
+                                dn->full_name))
+                return -ENODEV;
+        cci_port_control(port, enable);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(__cci_control_port_by_device);
+
+/**
+ * __cci_control_port_by_index() - function to control a CCI port by port index
+ *
+ * @port: port index previously retrieved with cci_ace_get_port()
+ * @enable: if true enables the port, if false disables it
+ *
+ * Return:
+ *      0 on success
+ *      -ENODEV on port index out of range
+ *      -EPERM if operation carried out on an ACE PORT
+ */
+int notrace __cci_control_port_by_index(u32 port, bool enable)
+{
+        if (port >= nb_cci_ports || ports[port].type == ACE_INVALID_PORT)
+                return -ENODEV;
+        /*
+         * CCI control for ports connected to CPUS is extremely fragile
+         * and must be made to go through a specific and controlled
+         * interface (ie cci_disable_port_by_cpu(); control by general purpose
+         * indexing is therefore disabled for ACE ports.
+         */
+        if (ports[port].type == ACE_PORT)
+                return -EPERM;
+
+        cci_port_control(port, enable);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(__cci_control_port_by_index);
+
+static const struct cci_nb_ports cci400_ports = {
+        .nb_ace = 2,
+        .nb_ace_lite = 3
+};
+
+static const struct of_device_id arm_cci_matches[] = {
+        {.compatible = "arm,cci-400", .data = &cci400_ports },
+        {},
+};
+
+static const struct of_device_id arm_cci_ctrl_if_matches[] = {
+        {.compatible = "arm,cci-400-ctrl-if", },
+        {},
+};
+
+static int __init cci_probe(void)
+{
+        struct cci_nb_ports const *cci_config;
+        int ret, i, nb_ace = 0, nb_ace_lite = 0;
+        struct device_node *np, *cp;
+        struct resource res;
+        const char *match_str;
+        bool is_ace;
+
+        np = of_find_matching_node(NULL, arm_cci_matches);
+        if (!np)
+                return -ENODEV;
+
+        cci_config = of_match_node(arm_cci_matches, np)->data;
+        if (!cci_config)
+                return -ENODEV;
+
+        nb_cci_ports = cci_config->nb_ace + cci_config->nb_ace_lite;
+
+        ports = kcalloc(sizeof(*ports), nb_cci_ports, GFP_KERNEL);
+        if (!ports)
+                return -ENOMEM;
+
+        ret = of_address_to_resource(np, 0, &res);
+        if (!ret) {
+                cci_ctrl_base = ioremap(res.start, resource_size(&res));
+                cci_ctrl_phys = res.start;
+        }
+        if (ret || !cci_ctrl_base) {
+                WARN(1, "unable to ioremap CCI ctrl\n");
+                ret = -ENXIO;
+                goto memalloc_err;
+        }
+
+        for_each_child_of_node(np, cp) {
+                if (!of_match_node(arm_cci_ctrl_if_matches, cp))
+                        continue;
+
+                i = nb_ace + nb_ace_lite;
+
+                if (i >= nb_cci_ports)
+                        break;
+
+                if (of_property_read_string(cp, "interface-type",
+                                        &match_str)) {
+                        WARN(1, "node %s missing interface-type property\n",
+                                  cp->full_name);
+                        continue;
+                }
+                is_ace = strcmp(match_str, "ace") == 0;
+                if (!is_ace && strcmp(match_str, "ace-lite")) {
+                        WARN(1, "node %s containing invalid interface-type property, skipping it\n",
+                                        cp->full_name);
+                        continue;
+                }
+
+                ret = of_address_to_resource(cp, 0, &res);
+                if (!ret) {
+                        ports[i].base = ioremap(res.start, resource_size(&res));
+                        ports[i].phys = res.start;
+                }
+                if (ret || !ports[i].base) {
+                        WARN(1, "unable to ioremap CCI port %d\n", i);
+                        continue;
+                }
+
+                if (is_ace) {
+                        if (WARN_ON(nb_ace >= cci_config->nb_ace))
+                                continue;
+                        ports[i].type = ACE_PORT;
+                        ++nb_ace;
+                } else {
+                        if (WARN_ON(nb_ace_lite >= cci_config->nb_ace_lite))
+                                continue;
+                        ports[i].type = ACE_LITE_PORT;
+                        ++nb_ace_lite;
+                }
+                ports[i].dn = cp;
+        }
+
+         /* initialize a stashed array of ACE ports to speed-up look-up */
+        cci_ace_init_ports();
+
+        /*
+         * Multi-cluster systems may need this data when non-coherent, during
+         * cluster power-up/power-down. Make sure it reaches main memory.
+         */
+        sync_cache_w(&cci_ctrl_base);
+        sync_cache_w(&cci_ctrl_phys);
+        sync_cache_w(&ports);
+        sync_cache_w(&cpu_port);
+        __sync_cache_range_w(ports, sizeof(*ports) * nb_cci_ports);
+        pr_info("ARM CCI driver probed\n");
+        return 0;
+
+memalloc_err:
+
+        kfree(ports);
+        return ret;
+}
+
+static int cci_init_status = -EAGAIN;
+static DEFINE_MUTEX(cci_probing);
+
+static int __init cci_init(void)
+{
+        if (cci_init_status != -EAGAIN)
+                return cci_init_status;
+
+        mutex_lock(&cci_probing);
+        if (cci_init_status == -EAGAIN)
+                cci_init_status = cci_probe();
+        mutex_unlock(&cci_probing);
+        return cci_init_status;
+}
+
+/*
+ * To sort out early init calls ordering a helper function is provided to
+ * check if the CCI driver has beed initialized. Function check if the driver
+ * has been initialized, if not it calls the init function that probes
+ * the driver and updates the return value.
+ */
+bool __init cci_probed(void)
+{
+        return cci_init() == 0;
+}
+EXPORT_SYMBOL_GPL(cci_probed);
+
+early_initcall(cci_init);
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("ARM CCI support");
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 137d3e730f86..fa435bcf9f1a 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -27,7 +27,7 @@ obj-$(CONFIG_MACH_LOONGSON1)	+= clk-ls1x.o
 obj-$(CONFIG_ARCH_SUNXI)        += sunxi/
 obj-$(CONFIG_ARCH_U8500)        += ux500/
 obj-$(CONFIG_ARCH_VT8500)       += clk-vt8500.o
-obj-$(CONFIG_ARCH_ZYNQ)         += clk-zynq.o
+obj-$(CONFIG_ARCH_ZYNQ)         += zynq/
 obj-$(CONFIG_ARCH_TEGRA)        += tegra/
 obj-$(CONFIG_PLAT_SAMSUNG)      += samsung/
 
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index 892728412e9d..24f553673b72 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -932,7 +932,7 @@ static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
         unsigned char reg;
         unsigned char rdiv;
 
-        if (hwdata->num > 5)
+        if (hwdata->num <= 5)
                 reg = si5351_msynth_params_address(hwdata->num) + 2;
         else
                 reg = SI5351_CLK6_7_OUTPUT_DIVIDER;
@@ -1477,6 +1477,16 @@ static int si5351_i2c_probe(struct i2c_client *client,
                         return -EINVAL;
                 }
                 drvdata->onecell.clks[n] = clk;
+
+                /* set initial clkout rate */
+                if (pdata->clkout[n].rate != 0) {
+                        int ret;
+                        ret = clk_set_rate(clk, pdata->clkout[n].rate);
+                        if (ret != 0) {
+                                dev_err(&client->dev, "Cannot set rate : %d\n",
+                                        ret);
+                        }
+                }
         }
 
         ret = of_clk_add_provider(client->dev.of_node, of_clk_src_onecell_get,
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index a15f7928fb11..8774e058cb6c 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -11,7 +11,349 @@
 #include <linux/io.h>
 #include <linux/clk-provider.h>
 #include <linux/spinlock.h>
-#include <mach/syscon.h>
+#include <linux/of.h>
+
+/* APP side SYSCON registers */
+/* CLK Control Register 16bit (R/W) */
+#define U300_SYSCON_CCR                                         (0x0000)
+#define U300_SYSCON_CCR_I2S1_USE_VCXO                           (0x0040)
+#define U300_SYSCON_CCR_I2S0_USE_VCXO                           (0x0020)
+#define U300_SYSCON_CCR_TURN_VCXO_ON                            (0x0008)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK                 (0x0007)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER            (0x04)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW                  (0x03)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE         (0x02)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH                 (0x01)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST                 (0x00)
+/* CLK Status Register 16bit (R/W) */
+#define U300_SYSCON_CSR                                         (0x0004)
+#define U300_SYSCON_CSR_PLL208_LOCK_IND                         (0x0002)
+#define U300_SYSCON_CSR_PLL13_LOCK_IND                          (0x0001)
+/* Reset lines for SLOW devices 16bit (R/W) */
+#define U300_SYSCON_RSR                                         (0x0014)
+#define U300_SYSCON_RSR_PPM_RESET_EN                            (0x0200)
+#define U300_SYSCON_RSR_ACC_TMR_RESET_EN                        (0x0100)
+#define U300_SYSCON_RSR_APP_TMR_RESET_EN                        (0x0080)
+#define U300_SYSCON_RSR_RTC_RESET_EN                            (0x0040)
+#define U300_SYSCON_RSR_KEYPAD_RESET_EN                         (0x0020)
+#define U300_SYSCON_RSR_GPIO_RESET_EN                           (0x0010)
+#define U300_SYSCON_RSR_EH_RESET_EN                             (0x0008)
+#define U300_SYSCON_RSR_BTR_RESET_EN                            (0x0004)
+#define U300_SYSCON_RSR_UART_RESET_EN                           (0x0002)
+#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN                    (0x0001)
+/* Reset lines for FAST devices 16bit (R/W) */
+#define U300_SYSCON_RFR                                         (0x0018)
+#define U300_SYSCON_RFR_UART1_RESET_ENABLE                      (0x0080)
+#define U300_SYSCON_RFR_SPI_RESET_ENABLE                        (0x0040)
+#define U300_SYSCON_RFR_MMC_RESET_ENABLE                        (0x0020)
+#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE                   (0x0010)
+#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE                   (0x0008)
+#define U300_SYSCON_RFR_I2C1_RESET_ENABLE                       (0x0004)
+#define U300_SYSCON_RFR_I2C0_RESET_ENABLE                       (0x0002)
+#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE                (0x0001)
+/* Reset lines for the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_RRR                                         (0x001c)
+#define U300_SYSCON_RRR_CDS_RESET_EN                            (0x4000)
+#define U300_SYSCON_RRR_ISP_RESET_EN                            (0x2000)
+#define U300_SYSCON_RRR_INTCON_RESET_EN                         (0x1000)
+#define U300_SYSCON_RRR_MSPRO_RESET_EN                          (0x0800)
+#define U300_SYSCON_RRR_XGAM_RESET_EN                           (0x0100)
+#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN                   (0x0080)
+#define U300_SYSCON_RRR_NANDIF_RESET_EN                         (0x0040)
+#define U300_SYSCON_RRR_EMIF_RESET_EN                           (0x0020)
+#define U300_SYSCON_RRR_DMAC_RESET_EN                           (0x0010)
+#define U300_SYSCON_RRR_CPU_RESET_EN                            (0x0008)
+#define U300_SYSCON_RRR_APEX_RESET_EN                           (0x0004)
+#define U300_SYSCON_RRR_AHB_RESET_EN                            (0x0002)
+#define U300_SYSCON_RRR_AAIF_RESET_EN                           (0x0001)
+/* Clock enable for SLOW peripherals 16bit (R/W) */
+#define U300_SYSCON_CESR                                        (0x0020)
+#define U300_SYSCON_CESR_PPM_CLK_EN                             (0x0200)
+#define U300_SYSCON_CESR_ACC_TMR_CLK_EN                         (0x0100)
+#define U300_SYSCON_CESR_APP_TMR_CLK_EN                         (0x0080)
+#define U300_SYSCON_CESR_KEYPAD_CLK_EN                          (0x0040)
+#define U300_SYSCON_CESR_GPIO_CLK_EN                            (0x0010)
+#define U300_SYSCON_CESR_EH_CLK_EN                              (0x0008)
+#define U300_SYSCON_CESR_BTR_CLK_EN                             (0x0004)
+#define U300_SYSCON_CESR_UART_CLK_EN                            (0x0002)
+#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN                     (0x0001)
+/* Clock enable for FAST peripherals 16bit (R/W) */
+#define U300_SYSCON_CEFR                                        (0x0024)
+#define U300_SYSCON_CEFR_UART1_CLK_EN                           (0x0200)
+#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN                       (0x0100)
+#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN                       (0x0080)
+#define U300_SYSCON_CEFR_SPI_CLK_EN                             (0x0040)
+#define U300_SYSCON_CEFR_MMC_CLK_EN                             (0x0020)
+#define U300_SYSCON_CEFR_I2S1_CLK_EN                            (0x0010)
+#define U300_SYSCON_CEFR_I2S0_CLK_EN                            (0x0008)
+#define U300_SYSCON_CEFR_I2C1_CLK_EN                            (0x0004)
+#define U300_SYSCON_CEFR_I2C0_CLK_EN                            (0x0002)
+#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN                     (0x0001)
+/* Clock enable for the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_CERR                                        (0x0028)
+#define U300_SYSCON_CERR_CDS_CLK_EN                             (0x2000)
+#define U300_SYSCON_CERR_ISP_CLK_EN                             (0x1000)
+#define U300_SYSCON_CERR_MSPRO_CLK_EN                           (0x0800)
+#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN               (0x0400)
+#define U300_SYSCON_CERR_SEMI_CLK_EN                            (0x0200)
+#define U300_SYSCON_CERR_XGAM_CLK_EN                            (0x0100)
+#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN                       (0x0080)
+#define U300_SYSCON_CERR_NANDIF_CLK_EN                          (0x0040)
+#define U300_SYSCON_CERR_EMIF_CLK_EN                            (0x0020)
+#define U300_SYSCON_CERR_DMAC_CLK_EN                            (0x0010)
+#define U300_SYSCON_CERR_CPU_CLK_EN                             (0x0008)
+#define U300_SYSCON_CERR_APEX_CLK_EN                            (0x0004)
+#define U300_SYSCON_CERR_AHB_CLK_EN                             (0x0002)
+#define U300_SYSCON_CERR_AAIF_CLK_EN                            (0x0001)
+/* Single block clock enable 16bit (-/W) */
+#define U300_SYSCON_SBCER                                       (0x002c)
+#define U300_SYSCON_SBCER_PPM_CLK_EN                            (0x0009)
+#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN                        (0x0008)
+#define U300_SYSCON_SBCER_APP_TMR_CLK_EN                        (0x0007)
+#define U300_SYSCON_SBCER_KEYPAD_CLK_EN                         (0x0006)
+#define U300_SYSCON_SBCER_GPIO_CLK_EN                           (0x0004)
+#define U300_SYSCON_SBCER_EH_CLK_EN                             (0x0003)
+#define U300_SYSCON_SBCER_BTR_CLK_EN                            (0x0002)
+#define U300_SYSCON_SBCER_UART_CLK_EN                           (0x0001)
+#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN                    (0x0000)
+#define U300_SYSCON_SBCER_UART1_CLK_EN                          (0x0019)
+#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN                      (0x0018)
+#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN                      (0x0017)
+#define U300_SYSCON_SBCER_SPI_CLK_EN                            (0x0016)
+#define U300_SYSCON_SBCER_MMC_CLK_EN                            (0x0015)
+#define U300_SYSCON_SBCER_I2S1_CLK_EN                           (0x0014)
+#define U300_SYSCON_SBCER_I2S0_CLK_EN                           (0x0013)
+#define U300_SYSCON_SBCER_I2C1_CLK_EN                           (0x0012)
+#define U300_SYSCON_SBCER_I2C0_CLK_EN                           (0x0011)
+#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN                    (0x0010)
+#define U300_SYSCON_SBCER_CDS_CLK_EN                            (0x002D)
+#define U300_SYSCON_SBCER_ISP_CLK_EN                            (0x002C)
+#define U300_SYSCON_SBCER_MSPRO_CLK_EN                          (0x002B)
+#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN              (0x002A)
+#define U300_SYSCON_SBCER_SEMI_CLK_EN                           (0x0029)
+#define U300_SYSCON_SBCER_XGAM_CLK_EN                           (0x0028)
+#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN                      (0x0027)
+#define U300_SYSCON_SBCER_NANDIF_CLK_EN                         (0x0026)
+#define U300_SYSCON_SBCER_EMIF_CLK_EN                           (0x0025)
+#define U300_SYSCON_SBCER_DMAC_CLK_EN                           (0x0024)
+#define U300_SYSCON_SBCER_CPU_CLK_EN                            (0x0023)
+#define U300_SYSCON_SBCER_APEX_CLK_EN                           (0x0022)
+#define U300_SYSCON_SBCER_AHB_CLK_EN                            (0x0021)
+#define U300_SYSCON_SBCER_AAIF_CLK_EN                           (0x0020)
+/* Single block clock disable 16bit (-/W) */
+#define U300_SYSCON_SBCDR                                       (0x0030)
+/* Same values as above for SBCER */
+/* Clock force SLOW peripherals 16bit (R/W) */
+#define U300_SYSCON_CFSR                                        (0x003c)
+#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN                       (0x0200)
+#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN                   (0x0100)
+#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN                   (0x0080)
+#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN                    (0x0020)
+#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN                      (0x0010)
+#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN                        (0x0008)
+#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN                       (0x0004)
+#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN                      (0x0002)
+#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN               (0x0001)
+/* Clock force FAST peripherals 16bit (R/W) */
+#define U300_SYSCON_CFFR                                        (0x40)
+/* Values not defined. Define if you want to use them. */
+/* Clock force the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_CFRR                                        (0x44)
+#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN                       (0x2000)
+#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN                       (0x1000)
+#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN                     (0x0800)
+#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN         (0x0400)
+#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN                      (0x0200)
+#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN                      (0x0100)
+#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN                 (0x0080)
+#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN                    (0x0040)
+#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN                      (0x0020)
+#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN                      (0x0010)
+#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN                       (0x0008)
+#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN                      (0x0004)
+#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN                       (0x0002)
+#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN                      (0x0001)
+/* PLL208 Frequency Control 16bit (R/W) */
+#define U300_SYSCON_PFCR                                        (0x48)
+#define U300_SYSCON_PFCR_DPLL_MULT_NUM                          (0x000F)
+/* Power Management Control 16bit (R/W) */
+#define U300_SYSCON_PMCR                                        (0x50)
+#define U300_SYSCON_PMCR_DCON_ENABLE                            (0x0002)
+#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE                        (0x0001)
+/* Reset Out 16bit (R/W) */
+#define U300_SYSCON_RCR                                         (0x6c)
+#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE                   (0x0001)
+/* EMIF Slew Rate Control 16bit (R/W) */
+#define U300_SYSCON_SRCLR                                       (0x70)
+#define U300_SYSCON_SRCLR_MASK                                  (0x03FF)
+#define U300_SYSCON_SRCLR_VALUE                                 (0x03FF)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B                       (0x0200)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A                       (0x0100)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B                       (0x0080)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A                       (0x0040)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B                       (0x0020)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A                       (0x0010)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B                       (0x0008)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A                       (0x0004)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B                       (0x0002)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A                       (0x0001)
+/* EMIF Clock Control Register 16bit (R/W) */
+#define U300_SYSCON_ECCR                                        (0x0078)
+#define U300_SYSCON_ECCR_MASK                                   (0x000F)
+#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE         (0x0008)
+#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE        (0x0004)
+#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE           (0x0002)
+#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE           (0x0001)
+/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
+#define U300_SYSCON_MMF0R                                       (0x90)
+#define U300_SYSCON_MMF0R_MASK                                  (0x00FF)
+#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK                      (0x00F0)
+#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK                       (0x000F)
+/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
+#define U300_SYSCON_MMF1R                                       (0x94)
+#define U300_SYSCON_MMF1R_MASK                                  (0x00FF)
+#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK                      (0x00F0)
+#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK                       (0x000F)
+/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
+#define U300_SYSCON_MMCR                                        (0x9C)
+#define U300_SYSCON_MMCR_MASK                                   (0x0003)
+#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE                  (0x0002)
+#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE                   (0x0001)
+/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
+#define U300_SYSCON_S0CCR                                       (0x120)
+#define U300_SYSCON_S0CCR_FIELD_MASK                            (0x43FF)
+#define U300_SYSCON_S0CCR_CLOCK_REQ                             (0x4000)
+#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR                     (0x2000)
+#define U300_SYSCON_S0CCR_CLOCK_INV                             (0x0200)
+#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK                       (0x01E0)
+#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK                     (0x001E)
+#define U300_SYSCON_S0CCR_CLOCK_ENABLE                          (0x0001)
+#define U300_SYSCON_S0CCR_SEL_MCLK                              (0x8<<1)
+#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK                       (0xA<<1)
+#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK                      (0xC<<1)
+#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK                      (0xD<<1)
+#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK                    (0xE<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK                     (0x0<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK                       (0x2<<1)
+#define U300_SYSCON_S0CCR_SEL_RTC_CLK                           (0x4<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK                    (0x6<<1)
+/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
+#define U300_SYSCON_S1CCR                                       (0x124)
+#define U300_SYSCON_S1CCR_FIELD_MASK                            (0x43FF)
+#define U300_SYSCON_S1CCR_CLOCK_REQ                             (0x4000)
+#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR                     (0x2000)
+#define U300_SYSCON_S1CCR_CLOCK_INV                             (0x0200)
+#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK                       (0x01E0)
+#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK                     (0x001E)
+#define U300_SYSCON_S1CCR_CLOCK_ENABLE                          (0x0001)
+#define U300_SYSCON_S1CCR_SEL_MCLK                              (0x8<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK                       (0xA<<1)
+#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK                      (0xC<<1)
+#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK                      (0xD<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK                    (0xE<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK                     (0x0<<1)
+#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK                       (0x2<<1)
+#define U300_SYSCON_S1CCR_SEL_RTC_CLK                           (0x4<<1)
+#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK                    (0x6<<1)
+/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
+#define U300_SYSCON_S2CCR                                       (0x128)
+#define U300_SYSCON_S2CCR_FIELD_MASK                            (0xC3FF)
+#define U300_SYSCON_S2CCR_CLK_STEAL                             (0x8000)
+#define U300_SYSCON_S2CCR_CLOCK_REQ                             (0x4000)
+#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR                     (0x2000)
+#define U300_SYSCON_S2CCR_CLOCK_INV                             (0x0200)
+#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK                       (0x01E0)
+#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK                     (0x001E)
+#define U300_SYSCON_S2CCR_CLOCK_ENABLE                          (0x0001)
+#define U300_SYSCON_S2CCR_SEL_MCLK                              (0x8<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK                       (0xA<<1)
+#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK                      (0xC<<1)
+#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK                      (0xD<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK                    (0xE<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK                     (0x0<<1)
+#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK                       (0x2<<1)
+#define U300_SYSCON_S2CCR_SEL_RTC_CLK                           (0x4<<1)
+#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK                    (0x6<<1)
+/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
+#define U300_SYSCON_PICR                                        (0x0130)
+#define U300_SYSCON_PICR_MASK                                   (0x00FF)
+#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE           (0x0080)
+#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE          (0x0040)
+#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE            (0x0020)
+#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE           (0x0010)
+#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE            (0x0008)
+#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE              (0x0004)
+#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE           (0x0002)
+#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE             (0x0001)
+/* SC_PLL_IRQ_STATUS 16 bit (R/-) */
+#define U300_SYSCON_PISR                                        (0x0134)
+#define U300_SYSCON_PISR_MASK                                   (0x000F)
+#define U300_SYSCON_PISR_PLL13_UNLOCK_IND                       (0x0008)
+#define U300_SYSCON_PISR_PLL13_LOCK_IND                         (0x0004)
+#define U300_SYSCON_PISR_PLL208_UNLOCK_IND                      (0x0002)
+#define U300_SYSCON_PISR_PLL208_LOCK_IND                        (0x0001)
+/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
+#define U300_SYSCON_PICLR                                       (0x0138)
+#define U300_SYSCON_PICLR_MASK                                  (0x000F)
+#define U300_SYSCON_PICLR_RWMASK                                (0x0000)
+#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC                       (0x0008)
+#define U300_SYSCON_PICLR_PLL13_LOCK_SC                         (0x0004)
+#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC                      (0x0002)
+#define U300_SYSCON_PICLR_PLL208_LOCK_SC                        (0x0001)
+/* Clock activity observability register 0 */
+#define U300_SYSCON_C0OAR                                       (0x140)
+#define U300_SYSCON_C0OAR_MASK                                  (0xFFFF)
+#define U300_SYSCON_C0OAR_VALUE                                 (0xFFFF)
+#define U300_SYSCON_C0OAR_BT_H_CLK                              (0x8000)
+#define U300_SYSCON_C0OAR_ASPB_P_CLK                            (0x4000)
+#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK                        (0x2000)
+#define U300_SYSCON_C0OAR_APP_SEMI_CLK                          (0x1000)
+#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK                     (0x0800)
+#define U300_SYSCON_C0OAR_APP_I2S1_CLK                          (0x0400)
+#define U300_SYSCON_C0OAR_APP_I2S0_CLK                          (0x0200)
+#define U300_SYSCON_C0OAR_APP_CPU_CLK                           (0x0100)
+#define U300_SYSCON_C0OAR_APP_52_CLK                            (0x0080)
+#define U300_SYSCON_C0OAR_APP_208_CLK                           (0x0040)
+#define U300_SYSCON_C0OAR_APP_104_CLK                           (0x0020)
+#define U300_SYSCON_C0OAR_APEX_CLK                              (0x0010)
+#define U300_SYSCON_C0OAR_AHPB_M_H_CLK                          (0x0008)
+#define U300_SYSCON_C0OAR_AHB_CLK                               (0x0004)
+#define U300_SYSCON_C0OAR_AFPB_P_CLK                            (0x0002)
+#define U300_SYSCON_C0OAR_AAIF_CLK                              (0x0001)
+/* Clock activity observability register 1 */
+#define U300_SYSCON_C1OAR                                       (0x144)
+#define U300_SYSCON_C1OAR_MASK                                  (0x3FFE)
+#define U300_SYSCON_C1OAR_VALUE                                 (0x3FFE)
+#define U300_SYSCON_C1OAR_NFIF_F_CLK                            (0x2000)
+#define U300_SYSCON_C1OAR_MSPRO_CLK                             (0x1000)
+#define U300_SYSCON_C1OAR_MMC_P_CLK                             (0x0800)
+#define U300_SYSCON_C1OAR_MMC_CLK                               (0x0400)
+#define U300_SYSCON_C1OAR_KP_P_CLK                              (0x0200)
+#define U300_SYSCON_C1OAR_I2C1_P_CLK                            (0x0100)
+#define U300_SYSCON_C1OAR_I2C0_P_CLK                            (0x0080)
+#define U300_SYSCON_C1OAR_GPIO_CLK                              (0x0040)
+#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK                         (0x0020)
+#define U300_SYSCON_C1OAR_EMIF_H_CLK                            (0x0010)
+#define U300_SYSCON_C1OAR_EVHIST_CLK                            (0x0008)
+#define U300_SYSCON_C1OAR_PPM_CLK                               (0x0004)
+#define U300_SYSCON_C1OAR_DMA_CLK                               (0x0002)
+/* Clock activity observability register 2 */
+#define U300_SYSCON_C2OAR                                       (0x148)
+#define U300_SYSCON_C2OAR_MASK                                  (0x0FFF)
+#define U300_SYSCON_C2OAR_VALUE                                 (0x0FFF)
+#define U300_SYSCON_C2OAR_XGAM_CDI_CLK                          (0x0800)
+#define U300_SYSCON_C2OAR_XGAM_CLK                              (0x0400)
+#define U300_SYSCON_C2OAR_VC_H_CLK                              (0x0200)
+#define U300_SYSCON_C2OAR_VC_CLK                                (0x0100)
+#define U300_SYSCON_C2OAR_UA_P_CLK                              (0x0080)
+#define U300_SYSCON_C2OAR_TMR1_CLK                              (0x0040)
+#define U300_SYSCON_C2OAR_TMR0_CLK                              (0x0020)
+#define U300_SYSCON_C2OAR_SPI_P_CLK                             (0x0010)
+#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK                     (0x0008)
+#define U300_SYSCON_C2OAR_PCM_I2S1_CLK                          (0x0004)
+#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK                     (0x0002)
+#define U300_SYSCON_C2OAR_PCM_I2S0_CLK                          (0x0001)
+
 
 /*
  * The clocking hierarchy currently looks like this.
@@ -386,6 +728,213 @@ syscon_clk_register(struct device *dev, const char *name,
         return clk;
 }
 
+#define U300_CLK_TYPE_SLOW 0
+#define U300_CLK_TYPE_FAST 1
+#define U300_CLK_TYPE_REST 2
+
+/**
+ * struct u300_clock - defines the bits and pieces for a certain clock
+ * @type: the clock type, slow fast or rest
+ * @id: the bit in the slow/fast/rest register for this clock
+ * @hw_ctrld: whether the clock is hardware controlled
+ * @clk_val: a value to poke in the one-write enable/disable registers
+ */
+struct u300_clock {
+        u8 type;
+        u8 id;
+        bool hw_ctrld;
+        u16 clk_val;
+};
+
+struct u300_clock const __initconst u300_clk_lookup[] = {
+        {
+                .type = U300_CLK_TYPE_REST,
+                .id = 3,
+                .hw_ctrld = true,
+                .clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_REST,
+                .id = 4,
+                .hw_ctrld = true,
+                .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_REST,
+                .id = 5,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_REST,
+                .id = 6,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_REST,
+                .id = 8,
+                .hw_ctrld = true,
+                .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_REST,
+                .id = 9,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_REST,
+                .id = 10,
+                .hw_ctrld = true,
+                .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_REST,
+                .id = 12,
+                .hw_ctrld = false,
+                /* INTCON: cannot be enabled, just taken out of reset */
+                .clk_val = 0xFFFFU,
+        },
+        {
+                .type = U300_CLK_TYPE_FAST,
+                .id = 0,
+                .hw_ctrld = true,
+                .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_FAST,
+                .id = 1,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_FAST,
+                .id = 2,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_FAST,
+                .id = 5,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_FAST,
+                .id = 6,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_SLOW,
+                .id = 0,
+                .hw_ctrld = true,
+                .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_SLOW,
+                .id = 1,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_SLOW,
+                .id = 4,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_SLOW,
+                .id = 6,
+                .hw_ctrld = true,
+                /* No clock enable register bit */
+                .clk_val = 0xFFFFU,
+        },
+        {
+                .type = U300_CLK_TYPE_SLOW,
+                .id = 7,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_SLOW,
+                .id = 8,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
+        },
+};
+
+static void __init of_u300_syscon_clk_init(struct device_node *np)
+{
+        struct clk *clk = ERR_PTR(-EINVAL);
+        const char *clk_name = np->name;
+        const char *parent_name;
+        void __iomem *res_reg;
+        void __iomem *en_reg;
+        u32 clk_type;
+        u32 clk_id;
+        int i;
+
+        if (of_property_read_u32(np, "clock-type", &clk_type)) {
+                pr_err("%s: syscon clock \"%s\" missing clock-type property\n",
+                       __func__, clk_name);
+                return;
+        }
+        if (of_property_read_u32(np, "clock-id", &clk_id)) {
+                pr_err("%s: syscon clock \"%s\" missing clock-id property\n",
+                       __func__, clk_name);
+                return;
+        }
+        parent_name = of_clk_get_parent_name(np, 0);
+
+        switch (clk_type) {
+        case U300_CLK_TYPE_SLOW:
+                res_reg = syscon_vbase + U300_SYSCON_RSR;
+                en_reg = syscon_vbase + U300_SYSCON_CESR;
+                break;
+        case U300_CLK_TYPE_FAST:
+                res_reg = syscon_vbase + U300_SYSCON_RFR;
+                en_reg = syscon_vbase + U300_SYSCON_CEFR;
+                break;
+        case U300_CLK_TYPE_REST:
+                res_reg = syscon_vbase + U300_SYSCON_RRR;
+                en_reg = syscon_vbase + U300_SYSCON_CERR;
+                break;
+        default:
+                pr_err("unknown clock type %x specified\n", clk_type);
+                return;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(u300_clk_lookup); i++) {
+                const struct u300_clock *u3clk = &u300_clk_lookup[i];
+
+                if (u3clk->type == clk_type && u3clk->id == clk_id)
+                        clk = syscon_clk_register(NULL,
+                                                  clk_name, parent_name,
+                                                  0, u3clk->hw_ctrld,
+                                                  res_reg, u3clk->id,
+                                                  en_reg, u3clk->id,
+                                                  u3clk->clk_val);
+        }
+
+        if (!IS_ERR(clk)) {
+                of_clk_add_provider(np, of_clk_src_simple_get, clk);
+
+                /*
+                 * Some few system clocks - device tree does not
+                 * represent clocks without a corresponding device node.
+                 * for now we add these three clocks here.
+                 */
+                if (clk_type == U300_CLK_TYPE_REST && clk_id == 5)
+                        clk_register_clkdev(clk, NULL, "pl172");
+                if (clk_type == U300_CLK_TYPE_REST && clk_id == 9)
+                        clk_register_clkdev(clk, NULL, "semi");
+                if (clk_type == U300_CLK_TYPE_REST && clk_id == 12)
+                        clk_register_clkdev(clk, NULL, "intcon");
+        }
+}
+
 /**
  * struct clk_mclk - U300 MCLK clock (MMC/SD clock)
  * @hw: corresponding clock hardware entry
@@ -590,10 +1139,41 @@ mclk_clk_register(struct device *dev, const char *name,
         return clk;
 }
 
+static void __init of_u300_syscon_mclk_init(struct device_node *np)
+{
+        struct clk *clk = ERR_PTR(-EINVAL);
+        const char *clk_name = np->name;
+        const char *parent_name;
+
+        parent_name = of_clk_get_parent_name(np, 0);
+        clk = mclk_clk_register(NULL, clk_name, parent_name, false);
+        if (!IS_ERR(clk))
+                of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+
+static const __initconst struct of_device_id u300_clk_match[] = {
+        {
+                .compatible = "fixed-clock",
+                .data = of_fixed_clk_setup,
+        },
+        {
+                .compatible = "fixed-factor-clock",
+                .data = of_fixed_factor_clk_setup,
+        },
+        {
+                .compatible = "stericsson,u300-syscon-clk",
+                .data = of_u300_syscon_clk_init,
+        },
+        {
+                .compatible = "stericsson,u300-syscon-mclk",
+                .data = of_u300_syscon_mclk_init,
+        },
+};
+
+
 void __init u300_clk_init(void __iomem *base)
 {
         u16 val;
-        struct clk *clk;
 
         syscon_vbase = base;
 
@@ -610,137 +1190,5 @@ void __init u300_clk_init(void __iomem *base)
         val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
         writew(val, syscon_vbase + U300_SYSCON_PMCR);
 
-        /* These are always available (RTC and PLL13) */
-        clk = clk_register_fixed_rate(NULL, "app_32_clk", NULL,
-                                      CLK_IS_ROOT, 32768);
-        /* The watchdog sits directly on the 32 kHz clock */
-        clk_register_clkdev(clk, NULL, "coh901327_wdog");
-        clk = clk_register_fixed_rate(NULL, "pll13", NULL,
-                                      CLK_IS_ROOT, 13000000);
-
-        /* These derive from PLL208 */
-        clk = clk_register_fixed_rate(NULL, "pll208", NULL,
-                                      CLK_IS_ROOT, 208000000);
-        clk = clk_register_fixed_factor(NULL, "app_208_clk", "pll208",
-                                        0, 1, 1);
-        clk = clk_register_fixed_factor(NULL, "app_104_clk", "pll208",
-                                        0, 1, 2);
-        clk = clk_register_fixed_factor(NULL, "app_52_clk", "pll208",
-                                        0, 1, 4);
-        /* The 52 MHz is divided down to 26 MHz */
-        clk = clk_register_fixed_factor(NULL, "app_26_clk", "app_52_clk",
-                                        0, 1, 2);
-
-        /* Directly on the AMBA interconnect */
-        clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
-                                  syscon_vbase + U300_SYSCON_RRR, 3,
-                                  syscon_vbase + U300_SYSCON_CERR, 3,
-                                  U300_SYSCON_SBCER_CPU_CLK_EN);
-        clk = syscon_clk_register(NULL, "dmac_clk", "app_52_clk", 0, true,
-                                  syscon_vbase + U300_SYSCON_RRR, 4,
-                                  syscon_vbase + U300_SYSCON_CERR, 4,
-                                  U300_SYSCON_SBCER_DMAC_CLK_EN);
-        clk_register_clkdev(clk, NULL, "dma");
-        clk = syscon_clk_register(NULL, "fsmc_clk", "app_52_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RRR, 6,
-                                  syscon_vbase + U300_SYSCON_CERR, 6,
-                                  U300_SYSCON_SBCER_NANDIF_CLK_EN);
-        clk_register_clkdev(clk, NULL, "fsmc-nand");
-        clk = syscon_clk_register(NULL, "xgam_clk", "app_52_clk", 0, true,
-                                  syscon_vbase + U300_SYSCON_RRR, 8,
-                                  syscon_vbase + U300_SYSCON_CERR, 8,
-                                  U300_SYSCON_SBCER_XGAM_CLK_EN);
-        clk_register_clkdev(clk, NULL, "xgam");
-        clk = syscon_clk_register(NULL, "semi_clk", "app_104_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RRR, 9,
-                                  syscon_vbase + U300_SYSCON_CERR, 9,
-                                  U300_SYSCON_SBCER_SEMI_CLK_EN);
-        clk_register_clkdev(clk, NULL, "semi");
-
-        /* AHB bridge clocks */
-        clk = syscon_clk_register(NULL, "ahb_subsys_clk", "app_52_clk", 0, true,
-                                  syscon_vbase + U300_SYSCON_RRR, 10,
-                                  syscon_vbase + U300_SYSCON_CERR, 10,
-                                  U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN);
-        clk = syscon_clk_register(NULL, "intcon_clk", "ahb_subsys_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RRR, 12,
-                                  syscon_vbase + U300_SYSCON_CERR, 12,
-                                  /* Cannot be enabled, just taken out of reset */
-                                  0xFFFFU);
-        clk_register_clkdev(clk, NULL, "intcon");
-        clk = syscon_clk_register(NULL, "emif_clk", "ahb_subsys_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RRR, 5,
-                                  syscon_vbase + U300_SYSCON_CERR, 5,
-                                  U300_SYSCON_SBCER_EMIF_CLK_EN);
-        clk_register_clkdev(clk, NULL, "pl172");
-
-        /* FAST bridge clocks */
-        clk = syscon_clk_register(NULL, "fast_clk", "app_26_clk", 0, true,
-                                  syscon_vbase + U300_SYSCON_RFR, 0,
-                                  syscon_vbase + U300_SYSCON_CEFR, 0,
-                                  U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN);
-        clk = syscon_clk_register(NULL, "i2c0_p_clk", "fast_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RFR, 1,
-                                  syscon_vbase + U300_SYSCON_CEFR, 1,
-                                  U300_SYSCON_SBCER_I2C0_CLK_EN);
-        clk_register_clkdev(clk, NULL, "stu300.0");
-        clk = syscon_clk_register(NULL, "i2c1_p_clk", "fast_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RFR, 2,
-                                  syscon_vbase + U300_SYSCON_CEFR, 2,
-                                  U300_SYSCON_SBCER_I2C1_CLK_EN);
-        clk_register_clkdev(clk, NULL, "stu300.1");
-        clk = syscon_clk_register(NULL, "mmc_p_clk", "fast_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RFR, 5,
-                                  syscon_vbase + U300_SYSCON_CEFR, 5,
-                                  U300_SYSCON_SBCER_MMC_CLK_EN);
-        clk_register_clkdev(clk, "apb_pclk", "mmci");
-        clk = syscon_clk_register(NULL, "spi_p_clk", "fast_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RFR, 6,
-                                  syscon_vbase + U300_SYSCON_CEFR, 6,
-                                  U300_SYSCON_SBCER_SPI_CLK_EN);
-        /* The SPI has no external clock for the outward bus, uses the pclk */
-        clk_register_clkdev(clk, NULL, "pl022");
-        clk_register_clkdev(clk, "apb_pclk", "pl022");
-
-        /* SLOW bridge clocks */
-        clk = syscon_clk_register(NULL, "slow_clk", "pll13", 0, true,
-                                  syscon_vbase + U300_SYSCON_RSR, 0,
-                                  syscon_vbase + U300_SYSCON_CESR, 0,
-                                  U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN);
-        clk = syscon_clk_register(NULL, "uart0_clk", "slow_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RSR, 1,
-                                  syscon_vbase + U300_SYSCON_CESR, 1,
-                                  U300_SYSCON_SBCER_UART_CLK_EN);
-        /* Same clock is used for APB and outward bus */
-        clk_register_clkdev(clk, NULL, "uart0");
-        clk_register_clkdev(clk, "apb_pclk", "uart0");
-        clk = syscon_clk_register(NULL, "gpio_clk", "slow_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RSR, 4,
-                                  syscon_vbase + U300_SYSCON_CESR, 4,
-                                  U300_SYSCON_SBCER_GPIO_CLK_EN);
-        clk_register_clkdev(clk, NULL, "u300-gpio");
-        clk = syscon_clk_register(NULL, "keypad_clk", "slow_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RSR, 5,
-                                  syscon_vbase + U300_SYSCON_CESR, 6,
-                                  U300_SYSCON_SBCER_KEYPAD_CLK_EN);
-        clk_register_clkdev(clk, NULL, "coh901461-keypad");
-        clk = syscon_clk_register(NULL, "rtc_clk", "slow_clk", 0, true,
-                                  syscon_vbase + U300_SYSCON_RSR, 6,
-                                  /* No clock enable register bit */
-                                  NULL, 0, 0xFFFFU);
-        clk_register_clkdev(clk, NULL, "rtc-coh901331");
-        clk = syscon_clk_register(NULL, "app_tmr_clk", "slow_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RSR, 7,
-                                  syscon_vbase + U300_SYSCON_CESR, 7,
-                                  U300_SYSCON_SBCER_APP_TMR_CLK_EN);
-        clk_register_clkdev(clk, NULL, "apptimer");
-        clk = syscon_clk_register(NULL, "acc_tmr_clk", "slow_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RSR, 8,
-                                  syscon_vbase + U300_SYSCON_CESR, 8,
-                                  U300_SYSCON_SBCER_ACC_TMR_CLK_EN);
-        clk_register_clkdev(clk, NULL, "timer");
-
-        /* Then this special MMC/SD clock */
-        clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
-        clk_register_clkdev(clk, NULL, "mmci");
+        of_clk_init(u300_clk_match);
 }
diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index debf688afa8e..553ac35bcc91 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -183,7 +183,7 @@ static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
         writel(divisor, cdev->div_reg);
         vt8500_pmc_wait_busy();
 
-        spin_lock_irqsave(cdev->lock, flags);
+        spin_unlock_irqrestore(cdev->lock, flags);
 
         return 0;
 }
diff --git a/drivers/clk/clk-zynq.c b/drivers/clk/clk-zynq.c
deleted file mode 100644
index 32062977f453..000000000000
--- a/drivers/clk/clk-zynq.c
+++ /dev/null
@@ -1,378 +0,0 @@
-/*
- * Copyright (c) 2012 National Instruments
- *
- * Josh Cartwright <josh.cartwright@ni.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/slab.h>
-#include <linux/kernel.h>
-#include <linux/clk-provider.h>
-#include <linux/clk/zynq.h>
-
-static void __iomem *slcr_base;
-
-struct zynq_pll_clk {
-        struct clk_hw   hw;
-        void __iomem    *pll_ctrl;
-        void __iomem    *pll_cfg;
-};
-
-#define to_zynq_pll_clk(hw)     container_of(hw, struct zynq_pll_clk, hw)
-
-#define CTRL_PLL_FDIV(x)        ((x) >> 12)
-
-static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
-                                          unsigned long parent_rate)
-{
-        struct zynq_pll_clk *pll = to_zynq_pll_clk(hw);
-        return parent_rate * CTRL_PLL_FDIV(ioread32(pll->pll_ctrl));
-}
-
-static const struct clk_ops zynq_pll_clk_ops = {
-        .recalc_rate    = zynq_pll_recalc_rate,
-};
-
-static void __init zynq_pll_clk_setup(struct device_node *np)
-{
-        struct clk_init_data init;
-        struct zynq_pll_clk *pll;
-        const char *parent_name;
-        struct clk *clk;
-        u32 regs[2];
-        int ret;
-
-        ret = of_property_read_u32_array(np, "reg", regs, ARRAY_SIZE(regs));
-        if (WARN_ON(ret))
-                return;
-
-        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
-        if (WARN_ON(!pll))
-                return;
-
-        pll->pll_ctrl = slcr_base + regs[0];
-        pll->pll_cfg  = slcr_base + regs[1];
-
-        of_property_read_string(np, "clock-output-names", &init.name);
-
-        init.ops = &zynq_pll_clk_ops;
-        parent_name = of_clk_get_parent_name(np, 0);
-        init.parent_names = &parent_name;
-        init.num_parents = 1;
-
-        pll->hw.init = &init;
-
-        clk = clk_register(NULL, &pll->hw);
-        if (WARN_ON(IS_ERR(clk)))
-                return;
-
-        ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
-        if (WARN_ON(ret))
-                return;
-}
-CLK_OF_DECLARE(zynq_pll, "xlnx,zynq-pll", zynq_pll_clk_setup);
-
-struct zynq_periph_clk {
-        struct clk_hw           hw;
-        struct clk_onecell_data onecell_data;
-        struct clk              *gates[2];
-        void __iomem            *clk_ctrl;
-        spinlock_t              clkact_lock;
-};
-
-#define to_zynq_periph_clk(hw)  container_of(hw, struct zynq_periph_clk, hw)
-
-static const u8 periph_clk_parent_map[] = {
-        0, 0, 1, 2
-};
-#define PERIPH_CLK_CTRL_SRC(x)  (periph_clk_parent_map[((x) & 0x30) >> 4])
-#define PERIPH_CLK_CTRL_DIV(x)  (((x) & 0x3F00) >> 8)
-
-static unsigned long zynq_periph_recalc_rate(struct clk_hw *hw,
-                                             unsigned long parent_rate)
-{
-        struct zynq_periph_clk *periph = to_zynq_periph_clk(hw);
-        return parent_rate / PERIPH_CLK_CTRL_DIV(ioread32(periph->clk_ctrl));
-}
-
-static u8 zynq_periph_get_parent(struct clk_hw *hw)
-{
-        struct zynq_periph_clk *periph = to_zynq_periph_clk(hw);
-        return PERIPH_CLK_CTRL_SRC(ioread32(periph->clk_ctrl));
-}
-
-static const struct clk_ops zynq_periph_clk_ops = {
-        .recalc_rate    = zynq_periph_recalc_rate,
-        .get_parent     = zynq_periph_get_parent,
-};
-
-static void __init zynq_periph_clk_setup(struct device_node *np)
-{
-        struct zynq_periph_clk *periph;
-        const char *parent_names[3];
-        struct clk_init_data init;
-        int clk_num = 0, err;
-        const char *name;
-        struct clk *clk;
-        u32 reg;
-        int i;
-
-        err = of_property_read_u32(np, "reg", &reg);
-        if (WARN_ON(err))
-                return;
-
-        periph = kzalloc(sizeof(*periph), GFP_KERNEL);
-        if (WARN_ON(!periph))
-                return;
-
-        periph->clk_ctrl = slcr_base + reg;
-        spin_lock_init(&periph->clkact_lock);
-
-        init.name = np->name;
-        init.ops = &zynq_periph_clk_ops;
-        for (i = 0; i < ARRAY_SIZE(parent_names); i++)
-                parent_names[i] = of_clk_get_parent_name(np, i);
-        init.parent_names = parent_names;
-        init.num_parents = ARRAY_SIZE(parent_names);
-
-        periph->hw.init = &init;
-
-        clk = clk_register(NULL, &periph->hw);
-        if (WARN_ON(IS_ERR(clk)))
-                return;
-
-        err = of_clk_add_provider(np, of_clk_src_simple_get, clk);
-        if (WARN_ON(err))
-                return;
-
-        err = of_property_read_string_index(np, "clock-output-names", 0,
-                                            &name);
-        if (WARN_ON(err))
-                return;
-
-        periph->gates[0] = clk_register_gate(NULL, name, np->name, 0,
-                                             periph->clk_ctrl, 0, 0,
-                                             &periph->clkact_lock);
-        if (WARN_ON(IS_ERR(periph->gates[0])))
-                return;
-        clk_num++;
-
-        /* some periph clks have 2 downstream gates */
-        err = of_property_read_string_index(np, "clock-output-names", 1,
-                                            &name);
-        if (err != -ENODATA) {
-                periph->gates[1] = clk_register_gate(NULL, name, np->name, 0,
-                                                     periph->clk_ctrl, 1, 0,
-                                                     &periph->clkact_lock);
-                if (WARN_ON(IS_ERR(periph->gates[1])))
-                        return;
-                clk_num++;
-        }
-
-        periph->onecell_data.clks = periph->gates;
-        periph->onecell_data.clk_num = clk_num;
-
-        err = of_clk_add_provider(np, of_clk_src_onecell_get,
-                                  &periph->onecell_data);
-        if (WARN_ON(err))
-                return;
-}
-CLK_OF_DECLARE(zynq_periph, "xlnx,zynq-periph-clock", zynq_periph_clk_setup);
-
-/* CPU Clock domain is modelled as a mux with 4 children subclks, whose
- * derivative rates depend on CLK_621_TRUE
- */
-
-struct zynq_cpu_clk {
-        struct clk_hw           hw;
-        struct clk_onecell_data onecell_data;
-        struct clk              *subclks[4];
-        void __iomem            *clk_ctrl;
-        spinlock_t              clkact_lock;
-};
-
-#define to_zynq_cpu_clk(hw)     container_of(hw, struct zynq_cpu_clk, hw)
-
-static const u8 zynq_cpu_clk_parent_map[] = {
-        1, 1, 2, 0
-};
-#define CPU_CLK_SRCSEL(x)       (zynq_cpu_clk_parent_map[(((x) & 0x30) >> 4)])
-#define CPU_CLK_CTRL_DIV(x)     (((x) & 0x3F00) >> 8)
-
-static u8 zynq_cpu_clk_get_parent(struct clk_hw *hw)
-{
-        struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw);
-        return CPU_CLK_SRCSEL(ioread32(cpuclk->clk_ctrl));
-}
-
-static unsigned long zynq_cpu_clk_recalc_rate(struct clk_hw *hw,
-                                              unsigned long parent_rate)
-{
-        struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw);
-        return parent_rate / CPU_CLK_CTRL_DIV(ioread32(cpuclk->clk_ctrl));
-}
-
-static const struct clk_ops zynq_cpu_clk_ops = {
-        .get_parent     = zynq_cpu_clk_get_parent,
-        .recalc_rate    = zynq_cpu_clk_recalc_rate,
-};
-
-struct zynq_cpu_subclk {
-        struct clk_hw   hw;
-        void __iomem    *clk_621;
-        enum {
-                CPU_SUBCLK_6X4X,
-                CPU_SUBCLK_3X2X,
-                CPU_SUBCLK_2X,
-                CPU_SUBCLK_1X,
-        } which;
-};
-
-#define CLK_621_TRUE(x) ((x) & 1)
-
-#define to_zynq_cpu_subclk(hw)  container_of(hw, struct zynq_cpu_subclk, hw);
-
-static unsigned long zynq_cpu_subclk_recalc_rate(struct clk_hw *hw,
-                                                 unsigned long parent_rate)
-{
-        unsigned long uninitialized_var(rate);
-        struct zynq_cpu_subclk *subclk;
-        bool is_621;
-
-        subclk = to_zynq_cpu_subclk(hw)
-        is_621 = CLK_621_TRUE(ioread32(subclk->clk_621));
-
-        switch (subclk->which) {
-        case CPU_SUBCLK_6X4X:
-                rate = parent_rate;
-                break;
-        case CPU_SUBCLK_3X2X:
-                rate = parent_rate / 2;
-                break;
-        case CPU_SUBCLK_2X:
-                rate = parent_rate / (is_621 ? 3 : 2);
-                break;
-        case CPU_SUBCLK_1X:
-                rate = parent_rate / (is_621 ? 6 : 4);
-                break;
-        };
-
-        return rate;
-}
-
-static const struct clk_ops zynq_cpu_subclk_ops = {
-        .recalc_rate    = zynq_cpu_subclk_recalc_rate,
-};
-
-static struct clk *zynq_cpu_subclk_setup(struct device_node *np, u8 which,
-                                         void __iomem *clk_621)
-{
-        struct zynq_cpu_subclk *subclk;
-        struct clk_init_data init;
-        struct clk *clk;
-        int err;
-
-        err = of_property_read_string_index(np, "clock-output-names",
-                                            which, &init.name);
-        if (WARN_ON(err))
-                goto err_read_output_name;
-
-        subclk = kzalloc(sizeof(*subclk), GFP_KERNEL);
-        if (!subclk)
-                goto err_subclk_alloc;
-
-        subclk->clk_621 = clk_621;
-        subclk->which = which;
-
-        init.ops = &zynq_cpu_subclk_ops;
-        init.parent_names = &np->name;
-        init.num_parents = 1;
-
-        subclk->hw.init = &init;
-
-        clk = clk_register(NULL, &subclk->hw);
-        if (WARN_ON(IS_ERR(clk)))
-                goto err_clk_register;
-
-        return clk;
-
-err_clk_register:
-        kfree(subclk);
-err_subclk_alloc:
-err_read_output_name:
-        return ERR_PTR(-EINVAL);
-}
-
-static void __init zynq_cpu_clk_setup(struct device_node *np)
-{
-        struct zynq_cpu_clk *cpuclk;
-        const char *parent_names[3];
-        struct clk_init_data init;
-        void __iomem *clk_621;
-        struct clk *clk;
-        u32 reg[2];
-        int err;
-        int i;
-
-        err = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg));
-        if (WARN_ON(err))
-                return;
-
-        cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
-        if (WARN_ON(!cpuclk))
-                return;
-
-        cpuclk->clk_ctrl = slcr_base + reg[0];
-        clk_621 = slcr_base + reg[1];
-        spin_lock_init(&cpuclk->clkact_lock);
-
-        init.name = np->name;
-        init.ops = &zynq_cpu_clk_ops;
-        for (i = 0; i < ARRAY_SIZE(parent_names); i++)
-                parent_names[i] = of_clk_get_parent_name(np, i);
-        init.parent_names = parent_names;
-        init.num_parents = ARRAY_SIZE(parent_names);
-
-        cpuclk->hw.init = &init;
-
-        clk = clk_register(NULL, &cpuclk->hw);
-        if (WARN_ON(IS_ERR(clk)))
-                return;
-
-        err = of_clk_add_provider(np, of_clk_src_simple_get, clk);
-        if (WARN_ON(err))
-                return;
-
-        for (i = 0; i < 4; i++) {
-                cpuclk->subclks[i] = zynq_cpu_subclk_setup(np, i, clk_621);
-                if (WARN_ON(IS_ERR(cpuclk->subclks[i])))
-                        return;
-        }
-
-        cpuclk->onecell_data.clks = cpuclk->subclks;
-        cpuclk->onecell_data.clk_num = i;
-
-        err = of_clk_add_provider(np, of_clk_src_onecell_get,
-                                  &cpuclk->onecell_data);
-        if (WARN_ON(err))
-                return;
-}
-CLK_OF_DECLARE(zynq_cpu, "xlnx,zynq-cpu-clock", zynq_cpu_clk_setup);
-
-void __init xilinx_zynq_clocks_init(void __iomem *slcr)
-{
-        slcr_base = slcr;
-        of_clk_init(NULL);
-}
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 57323fd15ec9..0b0f3e729cf7 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -1,8 +1,23 @@
-config MVEBU_CLK_CORE
-       bool
+config MVEBU_CLK_COMMON
+        bool
 
 config MVEBU_CLK_CPU
-       bool
+        bool
 
-config MVEBU_CLK_GATING
-       bool
+config ARMADA_370_CLK
+        bool
+        select MVEBU_CLK_COMMON
+        select MVEBU_CLK_CPU
+
+config ARMADA_XP_CLK
+        bool
+        select MVEBU_CLK_COMMON
+        select MVEBU_CLK_CPU
+
+config DOVE_CLK
+        bool
+        select MVEBU_CLK_COMMON
+
+config KIRKWOOD_CLK
+        bool
+        select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 58df3dc49363..1c7e70c63fb2 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -1,3 +1,7 @@
-obj-$(CONFIG_MVEBU_CLK_CORE)    += clk.o clk-core.o
+obj-$(CONFIG_MVEBU_CLK_COMMON)  += common.o
 obj-$(CONFIG_MVEBU_CLK_CPU)     += clk-cpu.o
-obj-$(CONFIG_MVEBU_CLK_GATING)  += clk-gating-ctrl.o
+
+obj-$(CONFIG_ARMADA_370_CLK)    += armada-370.o
+obj-$(CONFIG_ARMADA_XP_CLK)     += armada-xp.o
+obj-$(CONFIG_DOVE_CLK)          += dove.o
+obj-$(CONFIG_KIRKWOOD_CLK)      += kirkwood.o
diff --git a/drivers/clk/mvebu/armada-370.c b/drivers/clk/mvebu/armada-370.c
new file mode 100644
index 000000000000..079960e7c304
--- /dev/null
+++ b/drivers/clk/mvebu/armada-370.c
@@ -0,0 +1,176 @@
+/*
+ * Marvell Armada 370 SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ */
+
+#define SARL                            0       /* Low part [0:31] */
+#define  SARL_A370_PCLK_FREQ_OPT        11
+#define  SARL_A370_PCLK_FREQ_OPT_MASK   0xF
+#define  SARL_A370_FAB_FREQ_OPT         15
+#define  SARL_A370_FAB_FREQ_OPT_MASK    0x1F
+#define  SARL_A370_TCLK_FREQ_OPT        20
+#define  SARL_A370_TCLK_FREQ_OPT_MASK   0x1
+
+enum { A370_CPU_TO_NBCLK, A370_CPU_TO_HCLK, A370_CPU_TO_DRAMCLK };
+
+static const struct coreclk_ratio __initconst a370_coreclk_ratios[] = {
+        { .id = A370_CPU_TO_NBCLK, .name = "nbclk" },
+        { .id = A370_CPU_TO_HCLK, .name = "hclk" },
+        { .id = A370_CPU_TO_DRAMCLK, .name = "dramclk" },
+};
+
+static const u32 __initconst a370_tclk_freqs[] = {
+        16600000,
+        20000000,
+};
+
+static u32 __init a370_get_tclk_freq(void __iomem *sar)
+{
+        u8 tclk_freq_select = 0;
+
+        tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) &
+                            SARL_A370_TCLK_FREQ_OPT_MASK);
+        return a370_tclk_freqs[tclk_freq_select];
+}
+
+static const u32 __initconst a370_cpu_freqs[] = {
+        400000000,
+        533000000,
+        667000000,
+        800000000,
+        1000000000,
+        1067000000,
+        1200000000,
+};
+
+static u32 __init a370_get_cpu_freq(void __iomem *sar)
+{
+        u32 cpu_freq;
+        u8 cpu_freq_select = 0;
+
+        cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) &
+                           SARL_A370_PCLK_FREQ_OPT_MASK);
+        if (cpu_freq_select >= ARRAY_SIZE(a370_cpu_freqs)) {
+                pr_err("CPU freq select unsupported %d\n", cpu_freq_select);
+                cpu_freq = 0;
+        } else
+                cpu_freq = a370_cpu_freqs[cpu_freq_select];
+
+        return cpu_freq;
+}
+
+static const int __initconst a370_nbclk_ratios[32][2] = {
+        {0, 1}, {1, 2}, {2, 2}, {2, 2},
+        {1, 2}, {1, 2}, {1, 1}, {2, 3},
+        {0, 1}, {1, 2}, {2, 4}, {0, 1},
+        {1, 2}, {0, 1}, {0, 1}, {2, 2},
+        {0, 1}, {0, 1}, {0, 1}, {1, 1},
+        {2, 3}, {0, 1}, {0, 1}, {0, 1},
+        {0, 1}, {0, 1}, {0, 1}, {1, 1},
+        {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst a370_hclk_ratios[32][2] = {
+        {0, 1}, {1, 2}, {2, 6}, {2, 3},
+        {1, 3}, {1, 4}, {1, 2}, {2, 6},
+        {0, 1}, {1, 6}, {2, 10}, {0, 1},
+        {1, 4}, {0, 1}, {0, 1}, {2, 5},
+        {0, 1}, {0, 1}, {0, 1}, {1, 2},
+        {2, 6}, {0, 1}, {0, 1}, {0, 1},
+        {0, 1}, {0, 1}, {0, 1}, {1, 1},
+        {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst a370_dramclk_ratios[32][2] = {
+        {0, 1}, {1, 2}, {2, 3}, {2, 3},
+        {1, 3}, {1, 2}, {1, 2}, {2, 6},
+        {0, 1}, {1, 3}, {2, 5}, {0, 1},
+        {1, 4}, {0, 1}, {0, 1}, {2, 5},
+        {0, 1}, {0, 1}, {0, 1}, {1, 1},
+        {2, 3}, {0, 1}, {0, 1}, {0, 1},
+        {0, 1}, {0, 1}, {0, 1}, {1, 1},
+        {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static void __init a370_get_clk_ratio(
+        void __iomem *sar, int id, int *mult, int *div)
+{
+        u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) &
+                SARL_A370_FAB_FREQ_OPT_MASK);
+
+        switch (id) {
+        case A370_CPU_TO_NBCLK:
+                *mult = a370_nbclk_ratios[opt][0];
+                *div = a370_nbclk_ratios[opt][1];
+                break;
+        case A370_CPU_TO_HCLK:
+                *mult = a370_hclk_ratios[opt][0];
+                *div = a370_hclk_ratios[opt][1];
+                break;
+        case A370_CPU_TO_DRAMCLK:
+                *mult = a370_dramclk_ratios[opt][0];
+                *div = a370_dramclk_ratios[opt][1];
+                break;
+        }
+}
+
+static const struct coreclk_soc_desc a370_coreclks = {
+        .get_tclk_freq = a370_get_tclk_freq,
+        .get_cpu_freq = a370_get_cpu_freq,
+        .get_clk_ratio = a370_get_clk_ratio,
+        .ratios = a370_coreclk_ratios,
+        .num_ratios = ARRAY_SIZE(a370_coreclk_ratios),
+};
+
+static void __init a370_coreclk_init(struct device_node *np)
+{
+        mvebu_coreclk_setup(np, &a370_coreclks);
+}
+CLK_OF_DECLARE(a370_core_clk, "marvell,armada-370-core-clock",
+               a370_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst a370_gating_desc[] = {
+        { "audio", NULL, 0, 0 },
+        { "pex0_en", NULL, 1, 0 },
+        { "pex1_en", NULL,  2, 0 },
+        { "ge1", NULL, 3, 0 },
+        { "ge0", NULL, 4, 0 },
+        { "pex0", "pex0_en", 5, 0 },
+        { "pex1", "pex1_en", 9, 0 },
+        { "sata0", NULL, 15, 0 },
+        { "sdio", NULL, 17, 0 },
+        { "tdm", NULL, 25, 0 },
+        { "ddr", NULL, 28, CLK_IGNORE_UNUSED },
+        { "sata1", NULL, 30, 0 },
+        { }
+};
+
+static void __init a370_clk_gating_init(struct device_node *np)
+{
+        mvebu_clk_gating_setup(np, a370_gating_desc);
+}
+CLK_OF_DECLARE(a370_clk_gating, "marvell,armada-370-gating-clock",
+               a370_clk_gating_init);
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
new file mode 100644
index 000000000000..13b62ceb3407
--- /dev/null
+++ b/drivers/clk/mvebu/armada-xp.c
@@ -0,0 +1,210 @@
+/*
+ * Marvell Armada XP SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Armada XP Sample At Reset is a 64 bit bitfiled split in two
+ * register of 32 bits
+ */
+
+#define SARL                            0       /* Low part [0:31] */
+#define  SARL_AXP_PCLK_FREQ_OPT         21
+#define  SARL_AXP_PCLK_FREQ_OPT_MASK    0x7
+#define  SARL_AXP_FAB_FREQ_OPT          24
+#define  SARL_AXP_FAB_FREQ_OPT_MASK     0xF
+#define SARH                            4       /* High part [32:63] */
+#define  SARH_AXP_PCLK_FREQ_OPT         (52-32)
+#define  SARH_AXP_PCLK_FREQ_OPT_MASK    0x1
+#define  SARH_AXP_PCLK_FREQ_OPT_SHIFT   3
+#define  SARH_AXP_FAB_FREQ_OPT          (51-32)
+#define  SARH_AXP_FAB_FREQ_OPT_MASK     0x1
+#define  SARH_AXP_FAB_FREQ_OPT_SHIFT    4
+
+enum { AXP_CPU_TO_NBCLK, AXP_CPU_TO_HCLK, AXP_CPU_TO_DRAMCLK };
+
+static const struct coreclk_ratio __initconst axp_coreclk_ratios[] = {
+        { .id = AXP_CPU_TO_NBCLK, .name = "nbclk" },
+        { .id = AXP_CPU_TO_HCLK, .name = "hclk" },
+        { .id = AXP_CPU_TO_DRAMCLK, .name = "dramclk" },
+};
+
+/* Armada XP TCLK frequency is fixed to 250MHz */
+static u32 __init axp_get_tclk_freq(void __iomem *sar)
+{
+        return 250000000;
+}
+
+static const u32 __initconst axp_cpu_freqs[] = {
+        1000000000,
+        1066000000,
+        1200000000,
+        1333000000,
+        1500000000,
+        1666000000,
+        1800000000,
+        2000000000,
+        667000000,
+        0,
+        800000000,
+        1600000000,
+};
+
+static u32 __init axp_get_cpu_freq(void __iomem *sar)
+{
+        u32 cpu_freq;
+        u8 cpu_freq_select = 0;
+
+        cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) &
+                           SARL_AXP_PCLK_FREQ_OPT_MASK);
+        /*
+         * The upper bit is not contiguous to the other ones and
+         * located in the high part of the SAR registers
+         */
+        cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) &
+             SARH_AXP_PCLK_FREQ_OPT_MASK) << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
+        if (cpu_freq_select >= ARRAY_SIZE(axp_cpu_freqs)) {
+                pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
+                cpu_freq = 0;
+        } else
+                cpu_freq = axp_cpu_freqs[cpu_freq_select];
+
+        return cpu_freq;
+}
+
+static const int __initconst axp_nbclk_ratios[32][2] = {
+        {0, 1}, {1, 2}, {2, 2}, {2, 2},
+        {1, 2}, {1, 2}, {1, 1}, {2, 3},
+        {0, 1}, {1, 2}, {2, 4}, {0, 1},
+        {1, 2}, {0, 1}, {0, 1}, {2, 2},
+        {0, 1}, {0, 1}, {0, 1}, {1, 1},
+        {2, 3}, {0, 1}, {0, 1}, {0, 1},
+        {0, 1}, {0, 1}, {0, 1}, {1, 1},
+        {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst axp_hclk_ratios[32][2] = {
+        {0, 1}, {1, 2}, {2, 6}, {2, 3},
+        {1, 3}, {1, 4}, {1, 2}, {2, 6},
+        {0, 1}, {1, 6}, {2, 10}, {0, 1},
+        {1, 4}, {0, 1}, {0, 1}, {2, 5},
+        {0, 1}, {0, 1}, {0, 1}, {1, 2},
+        {2, 6}, {0, 1}, {0, 1}, {0, 1},
+        {0, 1}, {0, 1}, {0, 1}, {1, 1},
+        {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst axp_dramclk_ratios[32][2] = {
+        {0, 1}, {1, 2}, {2, 3}, {2, 3},
+        {1, 3}, {1, 2}, {1, 2}, {2, 6},
+        {0, 1}, {1, 3}, {2, 5}, {0, 1},
+        {1, 4}, {0, 1}, {0, 1}, {2, 5},
+        {0, 1}, {0, 1}, {0, 1}, {1, 1},
+        {2, 3}, {0, 1}, {0, 1}, {0, 1},
+        {0, 1}, {0, 1}, {0, 1}, {1, 1},
+        {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static void __init axp_get_clk_ratio(
+        void __iomem *sar, int id, int *mult, int *div)
+{
+        u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) &
+              SARL_AXP_FAB_FREQ_OPT_MASK);
+        /*
+         * The upper bit is not contiguous to the other ones and
+         * located in the high part of the SAR registers
+         */
+        opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) &
+                 SARH_AXP_FAB_FREQ_OPT_MASK) << SARH_AXP_FAB_FREQ_OPT_SHIFT);
+
+        switch (id) {
+        case AXP_CPU_TO_NBCLK:
+                *mult = axp_nbclk_ratios[opt][0];
+                *div = axp_nbclk_ratios[opt][1];
+                break;
+        case AXP_CPU_TO_HCLK:
+                *mult = axp_hclk_ratios[opt][0];
+                *div = axp_hclk_ratios[opt][1];
+                break;
+        case AXP_CPU_TO_DRAMCLK:
+                *mult = axp_dramclk_ratios[opt][0];
+                *div = axp_dramclk_ratios[opt][1];
+                break;
+        }
+}
+
+static const struct coreclk_soc_desc axp_coreclks = {
+        .get_tclk_freq = axp_get_tclk_freq,
+        .get_cpu_freq = axp_get_cpu_freq,
+        .get_clk_ratio = axp_get_clk_ratio,
+        .ratios = axp_coreclk_ratios,
+        .num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
+};
+
+static void __init axp_coreclk_init(struct device_node *np)
+{
+        mvebu_coreclk_setup(np, &axp_coreclks);
+}
+CLK_OF_DECLARE(axp_core_clk, "marvell,armada-xp-core-clock",
+               axp_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst axp_gating_desc[] = {
+        { "audio", NULL, 0, 0 },
+        { "ge3", NULL, 1, 0 },
+        { "ge2", NULL,  2, 0 },
+        { "ge1", NULL, 3, 0 },
+        { "ge0", NULL, 4, 0 },
+        { "pex00", NULL, 5, 0 },
+        { "pex01", NULL, 6, 0 },
+        { "pex02", NULL, 7, 0 },
+        { "pex03", NULL, 8, 0 },
+        { "pex10", NULL, 9, 0 },
+        { "pex11", NULL, 10, 0 },
+        { "pex12", NULL, 11, 0 },
+        { "pex13", NULL, 12, 0 },
+        { "bp", NULL, 13, 0 },
+        { "sata0lnk", NULL, 14, 0 },
+        { "sata0", "sata0lnk", 15, 0 },
+        { "lcd", NULL, 16, 0 },
+        { "sdio", NULL, 17, 0 },
+        { "usb0", NULL, 18, 0 },
+        { "usb1", NULL, 19, 0 },
+        { "usb2", NULL, 20, 0 },
+        { "xor0", NULL, 22, 0 },
+        { "crypto", NULL, 23, 0 },
+        { "tdm", NULL, 25, 0 },
+        { "pex20", NULL, 26, 0 },
+        { "pex30", NULL, 27, 0 },
+        { "xor1", NULL, 28, 0 },
+        { "sata1lnk", NULL, 29, 0 },
+        { "sata1", "sata1lnk", 30, 0 },
+        { }
+};
+
+static void __init axp_clk_gating_init(struct device_node *np)
+{
+        mvebu_clk_gating_setup(np, axp_gating_desc);
+}
+CLK_OF_DECLARE(axp_clk_gating, "marvell,armada-xp-gating-clock",
+               axp_clk_gating_init);
diff --git a/drivers/clk/mvebu/clk-core.c b/drivers/clk/mvebu/clk-core.c
deleted file mode 100644
index 0a53edbae8b8..000000000000
--- a/drivers/clk/mvebu/clk-core.c
+++ /dev/null
@@ -1,675 +0,0 @@
-/*
- * Marvell EBU clock core handling defined at reset
- *
- * Copyright (C) 2012 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/of_address.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include "clk-core.h"
-
-struct core_ratio {
-        int id;
-        const char *name;
-};
-
-struct core_clocks {
-        u32 (*get_tclk_freq)(void __iomem *sar);
-        u32 (*get_cpu_freq)(void __iomem *sar);
-        void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
-        const struct core_ratio *ratios;
-        int num_ratios;
-};
-
-static struct clk_onecell_data clk_data;
-
-static void __init mvebu_clk_core_setup(struct device_node *np,
-                                 struct core_clocks *coreclk)
-{
-        const char *tclk_name = "tclk";
-        const char *cpuclk_name = "cpuclk";
-        void __iomem *base;
-        unsigned long rate;
-        int n;
-
-        base = of_iomap(np, 0);
-        if (WARN_ON(!base))
-                return;
-
-        /*
-         * Allocate struct for TCLK, cpu clk, and core ratio clocks
-         */
-        clk_data.clk_num = 2 + coreclk->num_ratios;
-        clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
-                                GFP_KERNEL);
-        if (WARN_ON(!clk_data.clks))
-                return;
-
-        /*
-         * Register TCLK
-         */
-        of_property_read_string_index(np, "clock-output-names", 0,
-                                      &tclk_name);
-        rate = coreclk->get_tclk_freq(base);
-        clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL,
-                                                   CLK_IS_ROOT, rate);
-        WARN_ON(IS_ERR(clk_data.clks[0]));
-
-        /*
-         * Register CPU clock
-         */
-        of_property_read_string_index(np, "clock-output-names", 1,
-                                      &cpuclk_name);
-        rate = coreclk->get_cpu_freq(base);
-        clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,
-                                                   CLK_IS_ROOT, rate);
-        WARN_ON(IS_ERR(clk_data.clks[1]));
-
-        /*
-         * Register fixed-factor clocks derived from CPU clock
-         */
-        for (n = 0; n < coreclk->num_ratios; n++) {
-                const char *rclk_name = coreclk->ratios[n].name;
-                int mult, div;
-
-                of_property_read_string_index(np, "clock-output-names",
-                                              2+n, &rclk_name);
-                coreclk->get_clk_ratio(base, coreclk->ratios[n].id,
-                                       &mult, &div);
-                clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
-                                       cpuclk_name, 0, mult, div);
-                WARN_ON(IS_ERR(clk_data.clks[2+n]));
-        };
-
-        /*
-         * SAR register isn't needed anymore
-         */
-        iounmap(base);
-
-        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-}
-
-#ifdef CONFIG_MACH_ARMADA_370_XP
-/*
- * Armada 370/XP Sample At Reset is a 64 bit bitfiled split in two
- * register of 32 bits
- */
-
-#define SARL                                0   /* Low part [0:31] */
-#define     SARL_AXP_PCLK_FREQ_OPT          21
-#define     SARL_AXP_PCLK_FREQ_OPT_MASK     0x7
-#define     SARL_A370_PCLK_FREQ_OPT         11
-#define     SARL_A370_PCLK_FREQ_OPT_MASK    0xF
-#define     SARL_AXP_FAB_FREQ_OPT           24
-#define     SARL_AXP_FAB_FREQ_OPT_MASK      0xF
-#define     SARL_A370_FAB_FREQ_OPT          15
-#define     SARL_A370_FAB_FREQ_OPT_MASK     0x1F
-#define     SARL_A370_TCLK_FREQ_OPT         20
-#define     SARL_A370_TCLK_FREQ_OPT_MASK    0x1
-#define SARH                                4   /* High part [32:63] */
-#define     SARH_AXP_PCLK_FREQ_OPT          (52-32)
-#define     SARH_AXP_PCLK_FREQ_OPT_MASK     0x1
-#define     SARH_AXP_PCLK_FREQ_OPT_SHIFT    3
-#define     SARH_AXP_FAB_FREQ_OPT           (51-32)
-#define     SARH_AXP_FAB_FREQ_OPT_MASK      0x1
-#define     SARH_AXP_FAB_FREQ_OPT_SHIFT     4
-
-static const u32 __initconst armada_370_tclk_frequencies[] = {
-        16600000,
-        20000000,
-};
-
-static u32 __init armada_370_get_tclk_freq(void __iomem *sar)
-{
-        u8 tclk_freq_select = 0;
-
-        tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) &
-                            SARL_A370_TCLK_FREQ_OPT_MASK);
-        return armada_370_tclk_frequencies[tclk_freq_select];
-}
-
-static const u32 __initconst armada_370_cpu_frequencies[] = {
-        400000000,
-        533000000,
-        667000000,
-        800000000,
-        1000000000,
-        1067000000,
-        1200000000,
-};
-
-static u32 __init armada_370_get_cpu_freq(void __iomem *sar)
-{
-        u32 cpu_freq;
-        u8 cpu_freq_select = 0;
-
-        cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) &
-                           SARL_A370_PCLK_FREQ_OPT_MASK);
-        if (cpu_freq_select >= ARRAY_SIZE(armada_370_cpu_frequencies)) {
-                pr_err("CPU freq select unsupported %d\n", cpu_freq_select);
-                cpu_freq = 0;
-        } else
-                cpu_freq = armada_370_cpu_frequencies[cpu_freq_select];
-
-        return cpu_freq;
-}
-
-enum { A370_XP_NBCLK, A370_XP_HCLK, A370_XP_DRAMCLK };
-
-static const struct core_ratio __initconst armada_370_xp_core_ratios[] = {
-        { .id = A370_XP_NBCLK,   .name = "nbclk" },
-        { .id = A370_XP_HCLK,    .name = "hclk" },
-        { .id = A370_XP_DRAMCLK, .name = "dramclk" },
-};
-
-static const int __initconst armada_370_xp_nbclk_ratios[32][2] = {
-        {0, 1}, {1, 2}, {2, 2}, {2, 2},
-        {1, 2}, {1, 2}, {1, 1}, {2, 3},
-        {0, 1}, {1, 2}, {2, 4}, {0, 1},
-        {1, 2}, {0, 1}, {0, 1}, {2, 2},
-        {0, 1}, {0, 1}, {0, 1}, {1, 1},
-        {2, 3}, {0, 1}, {0, 1}, {0, 1},
-        {0, 1}, {0, 1}, {0, 1}, {1, 1},
-        {0, 1}, {0, 1}, {0, 1}, {0, 1},
-};
-
-static const int __initconst armada_370_xp_hclk_ratios[32][2] = {
-        {0, 1}, {1, 2}, {2, 6}, {2, 3},
-        {1, 3}, {1, 4}, {1, 2}, {2, 6},
-        {0, 1}, {1, 6}, {2, 10}, {0, 1},
-        {1, 4}, {0, 1}, {0, 1}, {2, 5},
-        {0, 1}, {0, 1}, {0, 1}, {1, 2},
-        {2, 6}, {0, 1}, {0, 1}, {0, 1},
-        {0, 1}, {0, 1}, {0, 1}, {1, 1},
-        {0, 1}, {0, 1}, {0, 1}, {0, 1},
-};
-
-static const int __initconst armada_370_xp_dramclk_ratios[32][2] = {
-        {0, 1}, {1, 2}, {2, 3}, {2, 3},
-        {1, 3}, {1, 2}, {1, 2}, {2, 6},
-        {0, 1}, {1, 3}, {2, 5}, {0, 1},
-        {1, 4}, {0, 1}, {0, 1}, {2, 5},
-        {0, 1}, {0, 1}, {0, 1}, {1, 1},
-        {2, 3}, {0, 1}, {0, 1}, {0, 1},
-        {0, 1}, {0, 1}, {0, 1}, {1, 1},
-        {0, 1}, {0, 1}, {0, 1}, {0, 1},
-};
-
-static void __init armada_370_xp_get_clk_ratio(u32 opt,
-        void __iomem *sar, int id, int *mult, int *div)
-{
-        switch (id) {
-        case A370_XP_NBCLK:
-                *mult = armada_370_xp_nbclk_ratios[opt][0];
-                *div = armada_370_xp_nbclk_ratios[opt][1];
-                break;
-        case A370_XP_HCLK:
-                *mult = armada_370_xp_hclk_ratios[opt][0];
-                *div = armada_370_xp_hclk_ratios[opt][1];
-                break;
-        case A370_XP_DRAMCLK:
-                *mult = armada_370_xp_dramclk_ratios[opt][0];
-                *div = armada_370_xp_dramclk_ratios[opt][1];
-                break;
-        }
-}
-
-static void __init armada_370_get_clk_ratio(
-        void __iomem *sar, int id, int *mult, int *div)
-{
-        u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) &
-                SARL_A370_FAB_FREQ_OPT_MASK);
-
-        armada_370_xp_get_clk_ratio(opt, sar, id, mult, div);
-}
-
-
-static const struct core_clocks armada_370_core_clocks = {
-        .get_tclk_freq = armada_370_get_tclk_freq,
-        .get_cpu_freq = armada_370_get_cpu_freq,
-        .get_clk_ratio = armada_370_get_clk_ratio,
-        .ratios = armada_370_xp_core_ratios,
-        .num_ratios = ARRAY_SIZE(armada_370_xp_core_ratios),
-};
-
-static const u32 __initconst armada_xp_cpu_frequencies[] = {
-        1000000000,
-        1066000000,
-        1200000000,
-        1333000000,
-        1500000000,
-        1666000000,
-        1800000000,
-        2000000000,
-        667000000,
-        0,
-        800000000,
-        1600000000,
-};
-
-/* For Armada XP TCLK frequency is fix: 250MHz */
-static u32 __init armada_xp_get_tclk_freq(void __iomem *sar)
-{
-        return 250 * 1000 * 1000;
-}
-
-static u32 __init armada_xp_get_cpu_freq(void __iomem *sar)
-{
-        u32 cpu_freq;
-        u8 cpu_freq_select = 0;
-
-        cpu_freq_select = ((readl(sar) >> SARL_AXP_PCLK_FREQ_OPT) &
-                           SARL_AXP_PCLK_FREQ_OPT_MASK);
-        /*
-         * The upper bit is not contiguous to the other ones and
-         * located in the high part of the SAR registers
-         */
-        cpu_freq_select |= (((readl(sar+4) >> SARH_AXP_PCLK_FREQ_OPT) &
-                             SARH_AXP_PCLK_FREQ_OPT_MASK)
-                            << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
-        if (cpu_freq_select >= ARRAY_SIZE(armada_xp_cpu_frequencies)) {
-                pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
-                cpu_freq = 0;
-        } else
-                cpu_freq = armada_xp_cpu_frequencies[cpu_freq_select];
-
-        return cpu_freq;
-}
-
-static void __init armada_xp_get_clk_ratio(
-        void __iomem *sar, int id, int *mult, int *div)
-{
-
-        u32 opt = ((readl(sar) >> SARL_AXP_FAB_FREQ_OPT) &
-              SARL_AXP_FAB_FREQ_OPT_MASK);
-        /*
-         * The upper bit is not contiguous to the other ones and
-         * located in the high part of the SAR registers
-         */
-        opt |= (((readl(sar+4) >> SARH_AXP_FAB_FREQ_OPT) &
-                SARH_AXP_FAB_FREQ_OPT_MASK)
-               << SARH_AXP_FAB_FREQ_OPT_SHIFT);
-
-        armada_370_xp_get_clk_ratio(opt, sar, id, mult, div);
-}
-
-static const struct core_clocks armada_xp_core_clocks = {
-        .get_tclk_freq = armada_xp_get_tclk_freq,
-        .get_cpu_freq = armada_xp_get_cpu_freq,
-        .get_clk_ratio = armada_xp_get_clk_ratio,
-        .ratios = armada_370_xp_core_ratios,
-        .num_ratios = ARRAY_SIZE(armada_370_xp_core_ratios),
-};
-
-#endif /* CONFIG_MACH_ARMADA_370_XP */
-
-/*
- * Dove PLL sample-at-reset configuration
- *
- * SAR0[8:5]   : CPU frequency
- *               5  = 1000 MHz
- *               6  =  933 MHz
- *               7  =  933 MHz
- *               8  =  800 MHz
- *               9  =  800 MHz
- *               10 =  800 MHz
- *               11 = 1067 MHz
- *               12 =  667 MHz
- *               13 =  533 MHz
- *               14 =  400 MHz
- *               15 =  333 MHz
- *               others reserved.
- *
- * SAR0[11:9]  : CPU to L2 Clock divider ratio
- *               0 = (1/1) * CPU
- *               2 = (1/2) * CPU
- *               4 = (1/3) * CPU
- *               6 = (1/4) * CPU
- *               others reserved.
- *
- * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio
- *               0  = (1/1) * CPU
- *               2  = (1/2) * CPU
- *               3  = (2/5) * CPU
- *               4  = (1/3) * CPU
- *               6  = (1/4) * CPU
- *               8  = (1/5) * CPU
- *               10 = (1/6) * CPU
- *               12 = (1/7) * CPU
- *               14 = (1/8) * CPU
- *               15 = (1/10) * CPU
- *               others reserved.
- *
- * SAR0[24:23] : TCLK frequency
- *               0 = 166 MHz
- *               1 = 125 MHz
- *               others reserved.
- */
-#ifdef CONFIG_ARCH_DOVE
-#define SAR_DOVE_CPU_FREQ               5
-#define SAR_DOVE_CPU_FREQ_MASK          0xf
-#define SAR_DOVE_L2_RATIO               9
-#define SAR_DOVE_L2_RATIO_MASK          0x7
-#define SAR_DOVE_DDR_RATIO              12
-#define SAR_DOVE_DDR_RATIO_MASK         0xf
-#define SAR_DOVE_TCLK_FREQ              23
-#define SAR_DOVE_TCLK_FREQ_MASK         0x3
-
-static const u32 __initconst dove_tclk_frequencies[] = {
-        166666667,
-        125000000,
-        0, 0
-};
-
-static u32 __init dove_get_tclk_freq(void __iomem *sar)
-{
-        u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) &
-                SAR_DOVE_TCLK_FREQ_MASK;
-        return dove_tclk_frequencies[opt];
-}
-
-static const u32 __initconst dove_cpu_frequencies[] = {
-        0, 0, 0, 0, 0,
-        1000000000,
-        933333333, 933333333,
-        800000000, 800000000, 800000000,
-        1066666667,
-        666666667,
-        533333333,
-        400000000,
-        333333333
-};
-
-static u32 __init dove_get_cpu_freq(void __iomem *sar)
-{
-        u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) &
-                SAR_DOVE_CPU_FREQ_MASK;
-        return dove_cpu_frequencies[opt];
-}
-
-enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR };
-
-static const struct core_ratio __initconst dove_core_ratios[] = {
-        { .id = DOVE_CPU_TO_L2, .name = "l2clk", },
-        { .id = DOVE_CPU_TO_DDR, .name = "ddrclk", }
-};
-
-static const int __initconst dove_cpu_l2_ratios[8][2] = {
-        { 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
-        { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }
-};
-
-static const int __initconst dove_cpu_ddr_ratios[16][2] = {
-        { 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 },
-        { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 },
-        { 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 },
-        { 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 }
-};
-
-static void __init dove_get_clk_ratio(
-        void __iomem *sar, int id, int *mult, int *div)
-{
-        switch (id) {
-        case DOVE_CPU_TO_L2:
-        {
-                u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) &
-                        SAR_DOVE_L2_RATIO_MASK;
-                *mult = dove_cpu_l2_ratios[opt][0];
-                *div = dove_cpu_l2_ratios[opt][1];
-                break;
-        }
-        case DOVE_CPU_TO_DDR:
-        {
-                u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) &
-                        SAR_DOVE_DDR_RATIO_MASK;
-                *mult = dove_cpu_ddr_ratios[opt][0];
-                *div = dove_cpu_ddr_ratios[opt][1];
-                break;
-        }
-        }
-}
-
-static const struct core_clocks dove_core_clocks = {
-        .get_tclk_freq = dove_get_tclk_freq,
-        .get_cpu_freq = dove_get_cpu_freq,
-        .get_clk_ratio = dove_get_clk_ratio,
-        .ratios = dove_core_ratios,
-        .num_ratios = ARRAY_SIZE(dove_core_ratios),
-};
-#endif /* CONFIG_ARCH_DOVE */
-
-/*
- * Kirkwood PLL sample-at-reset configuration
- * (6180 has different SAR layout than other Kirkwood SoCs)
- *
- * SAR0[4:3,22,1] : CPU frequency (6281,6292,6282)
- *      4  =  600 MHz
- *      6  =  800 MHz
- *      7  = 1000 MHz
- *      9  = 1200 MHz
- *      12 = 1500 MHz
- *      13 = 1600 MHz
- *      14 = 1800 MHz
- *      15 = 2000 MHz
- *      others reserved.
- *
- * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
- *      1 = (1/2) * CPU
- *      3 = (1/3) * CPU
- *      5 = (1/4) * CPU
- *      others reserved.
- *
- * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282)
- *      2 = (1/2) * CPU
- *      4 = (1/3) * CPU
- *      6 = (1/4) * CPU
- *      7 = (2/9) * CPU
- *      8 = (1/5) * CPU
- *      9 = (1/6) * CPU
- *      others reserved.
- *
- * SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only)
- *      5 = [CPU =  600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU]
- *      6 = [CPU =  800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU]
- *      7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU]
- *      others reserved.
- *
- * SAR0[21] : TCLK frequency
- *      0 = 200 MHz
- *      1 = 166 MHz
- *      others reserved.
- */
-#ifdef CONFIG_ARCH_KIRKWOOD
-#define SAR_KIRKWOOD_CPU_FREQ(x)        \
-        (((x & (1 <<  1)) >>  1) |      \
-         ((x & (1 << 22)) >> 21) |      \
-         ((x & (3 <<  3)) >>  1))
-#define SAR_KIRKWOOD_L2_RATIO(x)        \
-        (((x & (3 <<  9)) >> 9) |       \
-         (((x & (1 << 19)) >> 17)))
-#define SAR_KIRKWOOD_DDR_RATIO          5
-#define SAR_KIRKWOOD_DDR_RATIO_MASK     0xf
-#define SAR_MV88F6180_CLK               2
-#define SAR_MV88F6180_CLK_MASK          0x7
-#define SAR_KIRKWOOD_TCLK_FREQ          21
-#define SAR_KIRKWOOD_TCLK_FREQ_MASK     0x1
-
-enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR };
-
-static const struct core_ratio __initconst kirkwood_core_ratios[] = {
-        { .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", },
-        { .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", }
-};
-
-static u32 __init kirkwood_get_tclk_freq(void __iomem *sar)
-{
-        u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) &
-                SAR_KIRKWOOD_TCLK_FREQ_MASK;
-        return (opt) ? 166666667 : 200000000;
-}
-
-static const u32 __initconst kirkwood_cpu_frequencies[] = {
-        0, 0, 0, 0,
-        600000000,
-        0,
-        800000000,
-        1000000000,
-        0,
-        1200000000,
-        0, 0,
-        1500000000,
-        1600000000,
-        1800000000,
-        2000000000
-};
-
-static u32 __init kirkwood_get_cpu_freq(void __iomem *sar)
-{
-        u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar));
-        return kirkwood_cpu_frequencies[opt];
-}
-
-static const int __initconst kirkwood_cpu_l2_ratios[8][2] = {
-        { 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 },
-        { 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 }
-};
-
-static const int __initconst kirkwood_cpu_ddr_ratios[16][2] = {
-        { 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
-        { 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 },
-        { 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 },
-        { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
-};
-
-static void __init kirkwood_get_clk_ratio(
-        void __iomem *sar, int id, int *mult, int *div)
-{
-        switch (id) {
-        case KIRKWOOD_CPU_TO_L2:
-        {
-                u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar));
-                *mult = kirkwood_cpu_l2_ratios[opt][0];
-                *div = kirkwood_cpu_l2_ratios[opt][1];
-                break;
-        }
-        case KIRKWOOD_CPU_TO_DDR:
-        {
-                u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) &
-                        SAR_KIRKWOOD_DDR_RATIO_MASK;
-                *mult = kirkwood_cpu_ddr_ratios[opt][0];
-                *div = kirkwood_cpu_ddr_ratios[opt][1];
-                break;
-        }
-        }
-}
-
-static const struct core_clocks kirkwood_core_clocks = {
-        .get_tclk_freq = kirkwood_get_tclk_freq,
-        .get_cpu_freq = kirkwood_get_cpu_freq,
-        .get_clk_ratio = kirkwood_get_clk_ratio,
-        .ratios = kirkwood_core_ratios,
-        .num_ratios = ARRAY_SIZE(kirkwood_core_ratios),
-};
-
-static const u32 __initconst mv88f6180_cpu_frequencies[] = {
-        0, 0, 0, 0, 0,
-        600000000,
-        800000000,
-        1000000000
-};
-
-static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar)
-{
-        u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK;
-        return mv88f6180_cpu_frequencies[opt];
-}
-
-static const int __initconst mv88f6180_cpu_ddr_ratios[8][2] = {
-        { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
-        { 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 }
-};
-
-static void __init mv88f6180_get_clk_ratio(
-        void __iomem *sar, int id, int *mult, int *div)
-{
-        switch (id) {
-        case KIRKWOOD_CPU_TO_L2:
-        {
-                /* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */
-                *mult = 1;
-                *div = 2;
-                break;
-        }
-        case KIRKWOOD_CPU_TO_DDR:
-        {
-                u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) &
-                        SAR_MV88F6180_CLK_MASK;
-                *mult = mv88f6180_cpu_ddr_ratios[opt][0];
-                *div = mv88f6180_cpu_ddr_ratios[opt][1];
-                break;
-        }
-        }
-}
-
-static const struct core_clocks mv88f6180_core_clocks = {
-        .get_tclk_freq = kirkwood_get_tclk_freq,
-        .get_cpu_freq = mv88f6180_get_cpu_freq,
-        .get_clk_ratio = mv88f6180_get_clk_ratio,
-        .ratios = kirkwood_core_ratios,
-        .num_ratios = ARRAY_SIZE(kirkwood_core_ratios),
-};
-#endif /* CONFIG_ARCH_KIRKWOOD */
-
-static const __initdata struct of_device_id clk_core_match[] = {
-#ifdef CONFIG_MACH_ARMADA_370_XP
-        {
-                .compatible = "marvell,armada-370-core-clock",
-                .data = &armada_370_core_clocks,
-        },
-        {
-                .compatible = "marvell,armada-xp-core-clock",
-                .data = &armada_xp_core_clocks,
-        },
-#endif
-#ifdef CONFIG_ARCH_DOVE
-        {
-                .compatible = "marvell,dove-core-clock",
-                .data = &dove_core_clocks,
-        },
-#endif
-
-#ifdef CONFIG_ARCH_KIRKWOOD
-        {
-                .compatible = "marvell,kirkwood-core-clock",
-                .data = &kirkwood_core_clocks,
-        },
-        {
-                .compatible = "marvell,mv88f6180-core-clock",
-                .data = &mv88f6180_core_clocks,
-        },
-#endif
-
-        { }
-};
-
-void __init mvebu_core_clk_init(void)
-{
-        struct device_node *np;
-
-        for_each_matching_node(np, clk_core_match) {
-                const struct of_device_id *match =
-                        of_match_node(clk_core_match, np);
-                mvebu_clk_core_setup(np, (struct core_clocks *)match->data);
-        }
-}
diff --git a/drivers/clk/mvebu/clk-core.h b/drivers/clk/mvebu/clk-core.h
deleted file mode 100644
index 28b5e02e9885..000000000000
--- a/drivers/clk/mvebu/clk-core.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- *  * Marvell EBU clock core handling defined at reset
- *
- * Copyright (C) 2012 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MVEBU_CLK_CORE_H
-#define __MVEBU_CLK_CORE_H
-
-void __init mvebu_core_clk_init(void);
-
-#endif
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
deleted file mode 100644
index ebf141d4374b..000000000000
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
- * Marvell MVEBU clock gating control.
- *
- * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- * Andrew Lunn <andrew@lunn.ch>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/bitops.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-struct mvebu_gating_ctrl {
-        spinlock_t lock;
-        struct clk **gates;
-        int num_gates;
-};
-
-struct mvebu_soc_descr {
-        const char *name;
-        const char *parent;
-        int bit_idx;
-};
-
-#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
-
-static struct clk *mvebu_clk_gating_get_src(
-        struct of_phandle_args *clkspec, void *data)
-{
-        struct mvebu_gating_ctrl *ctrl = (struct mvebu_gating_ctrl *)data;
-        int n;
-
-        if (clkspec->args_count < 1)
-                return ERR_PTR(-EINVAL);
-
-        for (n = 0; n < ctrl->num_gates; n++) {
-                struct clk_gate *gate =
-                        to_clk_gate(__clk_get_hw(ctrl->gates[n]));
-                if (clkspec->args[0] == gate->bit_idx)
-                        return ctrl->gates[n];
-        }
-        return ERR_PTR(-ENODEV);
-}
-
-static void __init mvebu_clk_gating_setup(
-        struct device_node *np, const struct mvebu_soc_descr *descr)
-{
-        struct mvebu_gating_ctrl *ctrl;
-        struct clk *clk;
-        void __iomem *base;
-        const char *default_parent = NULL;
-        int n;
-
-        base = of_iomap(np, 0);
-
-        clk = of_clk_get(np, 0);
-        if (!IS_ERR(clk)) {
-                default_parent = __clk_get_name(clk);
-                clk_put(clk);
-        }
-
-        ctrl = kzalloc(sizeof(struct mvebu_gating_ctrl), GFP_KERNEL);
-        if (WARN_ON(!ctrl))
-                return;
-
-        spin_lock_init(&ctrl->lock);
-
-        /*
-         * Count, allocate, and register clock gates
-         */
-        for (n = 0; descr[n].name;)
-                n++;
-
-        ctrl->num_gates = n;
-        ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *),
-                              GFP_KERNEL);
-        if (WARN_ON(!ctrl->gates)) {
-                kfree(ctrl);
-                return;
-        }
-
-        for (n = 0; n < ctrl->num_gates; n++) {
-                u8 flags = 0;
-                const char *parent =
-                        (descr[n].parent) ? descr[n].parent : default_parent;
-
-                /*
-                 * On Armada 370, the DDR clock is a special case: it
-                 * isn't taken by any driver, but should anyway be
-                 * kept enabled, so we mark it as IGNORE_UNUSED for
-                 * now.
-                 */
-                if (!strcmp(descr[n].name, "ddr"))
-                        flags |= CLK_IGNORE_UNUSED;
-
-                ctrl->gates[n] = clk_register_gate(NULL, descr[n].name, parent,
-                                   flags, base, descr[n].bit_idx, 0, &ctrl->lock);
-                WARN_ON(IS_ERR(ctrl->gates[n]));
-        }
-        of_clk_add_provider(np, mvebu_clk_gating_get_src, ctrl);
-}
-
-/*
- * SoC specific clock gating control
- */
-
-#ifdef CONFIG_MACH_ARMADA_370
-static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = {
-        { "audio", NULL, 0 },
-        { "pex0_en", NULL, 1 },
-        { "pex1_en", NULL,  2 },
-        { "ge1", NULL, 3 },
-        { "ge0", NULL, 4 },
-        { "pex0", NULL, 5 },
-        { "pex1", NULL, 9 },
-        { "sata0", NULL, 15 },
-        { "sdio", NULL, 17 },
-        { "tdm", NULL, 25 },
-        { "ddr", NULL, 28 },
-        { "sata1", NULL, 30 },
-        { }
-};
-#endif
-
-#ifdef CONFIG_MACH_ARMADA_XP
-static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
-        { "audio", NULL, 0 },
-        { "ge3", NULL, 1 },
-        { "ge2", NULL,  2 },
-        { "ge1", NULL, 3 },
-        { "ge0", NULL, 4 },
-        { "pex0", NULL, 5 },
-        { "pex1", NULL, 6 },
-        { "pex2", NULL, 7 },
-        { "pex3", NULL, 8 },
-        { "bp", NULL, 13 },
-        { "sata0lnk", NULL, 14 },
-        { "sata0", "sata0lnk", 15 },
-        { "lcd", NULL, 16 },
-        { "sdio", NULL, 17 },
-        { "usb0", NULL, 18 },
-        { "usb1", NULL, 19 },
-        { "usb2", NULL, 20 },
-        { "xor0", NULL, 22 },
-        { "crypto", NULL, 23 },
-        { "tdm", NULL, 25 },
-        { "xor1", NULL, 28 },
-        { "sata1lnk", NULL, 29 },
-        { "sata1", "sata1lnk", 30 },
-        { }
-};
-#endif
-
-#ifdef CONFIG_ARCH_DOVE
-static const struct mvebu_soc_descr __initconst dove_gating_descr[] = {
-        { "usb0", NULL, 0 },
-        { "usb1", NULL, 1 },
-        { "ge", "gephy", 2 },
-        { "sata", NULL, 3 },
-        { "pex0", NULL, 4 },
-        { "pex1", NULL, 5 },
-        { "sdio0", NULL, 8 },
-        { "sdio1", NULL, 9 },
-        { "nand", NULL, 10 },
-        { "camera", NULL, 11 },
-        { "i2s0", NULL, 12 },
-        { "i2s1", NULL, 13 },
-        { "crypto", NULL, 15 },
-        { "ac97", NULL, 21 },
-        { "pdma", NULL, 22 },
-        { "xor0", NULL, 23 },
-        { "xor1", NULL, 24 },
-        { "gephy", NULL, 30 },
-        { }
-};
-#endif
-
-#ifdef CONFIG_ARCH_KIRKWOOD
-static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = {
-        { "ge0", NULL, 0 },
-        { "pex0", NULL, 2 },
-        { "usb0", NULL, 3 },
-        { "sdio", NULL, 4 },
-        { "tsu", NULL, 5 },
-        { "runit", NULL, 7 },
-        { "xor0", NULL, 8 },
-        { "audio", NULL, 9 },
-        { "powersave", "cpuclk", 11 },
-        { "sata0", NULL, 14 },
-        { "sata1", NULL, 15 },
-        { "xor1", NULL, 16 },
-        { "crypto", NULL, 17 },
-        { "pex1", NULL, 18 },
-        { "ge1", NULL, 19 },
-        { "tdm", NULL, 20 },
-        { }
-};
-#endif
-
-static const __initdata struct of_device_id clk_gating_match[] = {
-#ifdef CONFIG_MACH_ARMADA_370
-        {
-                .compatible = "marvell,armada-370-gating-clock",
-                .data = armada_370_gating_descr,
-        },
-#endif
-
-#ifdef CONFIG_MACH_ARMADA_XP
-        {
-                .compatible = "marvell,armada-xp-gating-clock",
-                .data = armada_xp_gating_descr,
-        },
-#endif
-
-#ifdef CONFIG_ARCH_DOVE
-        {
-                .compatible = "marvell,dove-gating-clock",
-                .data = dove_gating_descr,
-        },
-#endif
-
-#ifdef CONFIG_ARCH_KIRKWOOD
-        {
-                .compatible = "marvell,kirkwood-gating-clock",
-                .data = kirkwood_gating_descr,
-        },
-#endif
-
-        { }
-};
-
-void __init mvebu_gating_clk_init(void)
-{
-        struct device_node *np;
-
-        for_each_matching_node(np, clk_gating_match) {
-                const struct of_device_id *match =
-                        of_match_node(clk_gating_match, np);
-                mvebu_clk_gating_setup(np,
-                       (const struct mvebu_soc_descr *)match->data);
-        }
-}
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.h b/drivers/clk/mvebu/clk-gating-ctrl.h
deleted file mode 100644
index 9275d1e51f1b..000000000000
--- a/drivers/clk/mvebu/clk-gating-ctrl.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Marvell EBU gating clock handling
- *
- * Copyright (C) 2012 Marvell
- *
- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MVEBU_CLK_GATING_H
-#define __MVEBU_CLK_GATING_H
-
-#ifdef CONFIG_MVEBU_CLK_GATING
-void __init mvebu_gating_clk_init(void);
-#else
-void mvebu_gating_clk_init(void) {}
-#endif
-
-#endif
diff --git a/drivers/clk/mvebu/clk.c b/drivers/clk/mvebu/clk.c
deleted file mode 100644
index 29f10fb3006c..000000000000
--- a/drivers/clk/mvebu/clk.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Marvell EBU SoC clock handling.
- *
- * Copyright (C) 2012 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include "clk-core.h"
-#include "clk-gating-ctrl.h"
-
-void __init mvebu_clocks_init(void)
-{
-        mvebu_core_clk_init();
-        mvebu_gating_clk_init();
-        of_clk_init(NULL);
-}
diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
new file mode 100644
index 000000000000..adaa4a1821b8
--- /dev/null
+++ b/drivers/clk/mvebu/common.c
@@ -0,0 +1,163 @@
+/*
+ * Marvell EBU SoC common clock handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "common.h"
+
+/*
+ * Core Clocks
+ */
+
+static struct clk_onecell_data clk_data;
+
+void __init mvebu_coreclk_setup(struct device_node *np,
+                                const struct coreclk_soc_desc *desc)
+{
+        const char *tclk_name = "tclk";
+        const char *cpuclk_name = "cpuclk";
+        void __iomem *base;
+        unsigned long rate;
+        int n;
+
+        base = of_iomap(np, 0);
+        if (WARN_ON(!base))
+                return;
+
+        /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
+        clk_data.clk_num = 2 + desc->num_ratios;
+        clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
+                                GFP_KERNEL);
+        if (WARN_ON(!clk_data.clks))
+                return;
+
+        /* Register TCLK */
+        of_property_read_string_index(np, "clock-output-names", 0,
+                                      &tclk_name);
+        rate = desc->get_tclk_freq(base);
+        clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL,
+                                                   CLK_IS_ROOT, rate);
+        WARN_ON(IS_ERR(clk_data.clks[0]));
+
+        /* Register CPU clock */
+        of_property_read_string_index(np, "clock-output-names", 1,
+                                      &cpuclk_name);
+        rate = desc->get_cpu_freq(base);
+        clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,
+                                                   CLK_IS_ROOT, rate);
+        WARN_ON(IS_ERR(clk_data.clks[1]));
+
+        /* Register fixed-factor clocks derived from CPU clock */
+        for (n = 0; n < desc->num_ratios; n++) {
+                const char *rclk_name = desc->ratios[n].name;
+                int mult, div;
+
+                of_property_read_string_index(np, "clock-output-names",
+                                              2+n, &rclk_name);
+                desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div);
+                clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
+                                       cpuclk_name, 0, mult, div);
+                WARN_ON(IS_ERR(clk_data.clks[2+n]));
+        };
+
+        /* SAR register isn't needed anymore */
+        iounmap(base);
+
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+/*
+ * Clock Gating Control
+ */
+
+struct clk_gating_ctrl {
+        spinlock_t lock;
+        struct clk **gates;
+        int num_gates;
+};
+
+#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
+
+static struct clk *clk_gating_get_src(
+        struct of_phandle_args *clkspec, void *data)
+{
+        struct clk_gating_ctrl *ctrl = (struct clk_gating_ctrl *)data;
+        int n;
+
+        if (clkspec->args_count < 1)
+                return ERR_PTR(-EINVAL);
+
+        for (n = 0; n < ctrl->num_gates; n++) {
+                struct clk_gate *gate =
+                        to_clk_gate(__clk_get_hw(ctrl->gates[n]));
+                if (clkspec->args[0] == gate->bit_idx)
+                        return ctrl->gates[n];
+        }
+        return ERR_PTR(-ENODEV);
+}
+
+void __init mvebu_clk_gating_setup(struct device_node *np,
+                                   const struct clk_gating_soc_desc *desc)
+{
+        struct clk_gating_ctrl *ctrl;
+        struct clk *clk;
+        void __iomem *base;
+        const char *default_parent = NULL;
+        int n;
+
+        base = of_iomap(np, 0);
+        if (WARN_ON(!base))
+                return;
+
+        clk = of_clk_get(np, 0);
+        if (!IS_ERR(clk)) {
+                default_parent = __clk_get_name(clk);
+                clk_put(clk);
+        }
+
+        ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
+        if (WARN_ON(!ctrl))
+                return;
+
+        spin_lock_init(&ctrl->lock);
+
+        /* Count, allocate, and register clock gates */
+        for (n = 0; desc[n].name;)
+                n++;
+
+        ctrl->num_gates = n;
+        ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *),
+                              GFP_KERNEL);
+        if (WARN_ON(!ctrl->gates)) {
+                kfree(ctrl);
+                return;
+        }
+
+        for (n = 0; n < ctrl->num_gates; n++) {
+                const char *parent =
+                        (desc[n].parent) ? desc[n].parent : default_parent;
+                ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent,
+                                        desc[n].flags, base, desc[n].bit_idx,
+                                        0, &ctrl->lock);
+                WARN_ON(IS_ERR(ctrl->gates[n]));
+        }
+
+        of_clk_add_provider(np, clk_gating_get_src, ctrl);
+}
diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h
new file mode 100644
index 000000000000..f968b4d9df92
--- /dev/null
+++ b/drivers/clk/mvebu/common.h
@@ -0,0 +1,48 @@
+/*
+ * Marvell EBU SoC common clock handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __CLK_MVEBU_COMMON_H_
+#define __CLK_MVEBU_COMMON_H_
+
+#include <linux/kernel.h>
+
+struct device_node;
+
+struct coreclk_ratio {
+        int id;
+        const char *name;
+};
+
+struct coreclk_soc_desc {
+        u32 (*get_tclk_freq)(void __iomem *sar);
+        u32 (*get_cpu_freq)(void __iomem *sar);
+        void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
+        const struct coreclk_ratio *ratios;
+        int num_ratios;
+};
+
+struct clk_gating_soc_desc {
+        const char *name;
+        const char *parent;
+        int bit_idx;
+        unsigned long flags;
+};
+
+void __init mvebu_coreclk_setup(struct device_node *np,
+                                const struct coreclk_soc_desc *desc);
+
+void __init mvebu_clk_gating_setup(struct device_node *np,
+                                   const struct clk_gating_soc_desc *desc);
+
+#endif
diff --git a/drivers/clk/mvebu/dove.c b/drivers/clk/mvebu/dove.c
new file mode 100644
index 000000000000..79d7aedf03fb
--- /dev/null
+++ b/drivers/clk/mvebu/dove.c
@@ -0,0 +1,194 @@
+/*
+ * Marvell Dove SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Dove PLL sample-at-reset configuration
+ *
+ * SAR0[8:5]   : CPU frequency
+ *               5  = 1000 MHz
+ *               6  =  933 MHz
+ *               7  =  933 MHz
+ *               8  =  800 MHz
+ *               9  =  800 MHz
+ *               10 =  800 MHz
+ *               11 = 1067 MHz
+ *               12 =  667 MHz
+ *               13 =  533 MHz
+ *               14 =  400 MHz
+ *               15 =  333 MHz
+ *               others reserved.
+ *
+ * SAR0[11:9]  : CPU to L2 Clock divider ratio
+ *               0 = (1/1) * CPU
+ *               2 = (1/2) * CPU
+ *               4 = (1/3) * CPU
+ *               6 = (1/4) * CPU
+ *               others reserved.
+ *
+ * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio
+ *               0  = (1/1) * CPU
+ *               2  = (1/2) * CPU
+ *               3  = (2/5) * CPU
+ *               4  = (1/3) * CPU
+ *               6  = (1/4) * CPU
+ *               8  = (1/5) * CPU
+ *               10 = (1/6) * CPU
+ *               12 = (1/7) * CPU
+ *               14 = (1/8) * CPU
+ *               15 = (1/10) * CPU
+ *               others reserved.
+ *
+ * SAR0[24:23] : TCLK frequency
+ *               0 = 166 MHz
+ *               1 = 125 MHz
+ *               others reserved.
+ */
+
+#define SAR_DOVE_CPU_FREQ               5
+#define SAR_DOVE_CPU_FREQ_MASK          0xf
+#define SAR_DOVE_L2_RATIO               9
+#define SAR_DOVE_L2_RATIO_MASK          0x7
+#define SAR_DOVE_DDR_RATIO              12
+#define SAR_DOVE_DDR_RATIO_MASK         0xf
+#define SAR_DOVE_TCLK_FREQ              23
+#define SAR_DOVE_TCLK_FREQ_MASK         0x3
+
+enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR };
+
+static const struct coreclk_ratio __initconst dove_coreclk_ratios[] = {
+        { .id = DOVE_CPU_TO_L2, .name = "l2clk", },
+        { .id = DOVE_CPU_TO_DDR, .name = "ddrclk", }
+};
+
+static const u32 __initconst dove_tclk_freqs[] = {
+        166666667,
+        125000000,
+        0, 0
+};
+
+static u32 __init dove_get_tclk_freq(void __iomem *sar)
+{
+        u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) &
+                SAR_DOVE_TCLK_FREQ_MASK;
+        return dove_tclk_freqs[opt];
+}
+
+static const u32 __initconst dove_cpu_freqs[] = {
+        0, 0, 0, 0, 0,
+        1000000000,
+        933333333, 933333333,
+        800000000, 800000000, 800000000,
+        1066666667,
+        666666667,
+        533333333,
+        400000000,
+        333333333
+};
+
+static u32 __init dove_get_cpu_freq(void __iomem *sar)
+{
+        u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) &
+                SAR_DOVE_CPU_FREQ_MASK;
+        return dove_cpu_freqs[opt];
+}
+
+static const int __initconst dove_cpu_l2_ratios[8][2] = {
+        { 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
+        { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }
+};
+
+static const int __initconst dove_cpu_ddr_ratios[16][2] = {
+        { 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 },
+        { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 },
+        { 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 },
+        { 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 }
+};
+
+static void __init dove_get_clk_ratio(
+        void __iomem *sar, int id, int *mult, int *div)
+{
+        switch (id) {
+        case DOVE_CPU_TO_L2:
+        {
+                u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) &
+                        SAR_DOVE_L2_RATIO_MASK;
+                *mult = dove_cpu_l2_ratios[opt][0];
+                *div = dove_cpu_l2_ratios[opt][1];
+                break;
+        }
+        case DOVE_CPU_TO_DDR:
+        {
+                u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) &
+                        SAR_DOVE_DDR_RATIO_MASK;
+                *mult = dove_cpu_ddr_ratios[opt][0];
+                *div = dove_cpu_ddr_ratios[opt][1];
+                break;
+        }
+        }
+}
+
+static const struct coreclk_soc_desc dove_coreclks = {
+        .get_tclk_freq = dove_get_tclk_freq,
+        .get_cpu_freq = dove_get_cpu_freq,
+        .get_clk_ratio = dove_get_clk_ratio,
+        .ratios = dove_coreclk_ratios,
+        .num_ratios = ARRAY_SIZE(dove_coreclk_ratios),
+};
+
+static void __init dove_coreclk_init(struct device_node *np)
+{
+        mvebu_coreclk_setup(np, &dove_coreclks);
+}
+CLK_OF_DECLARE(dove_core_clk, "marvell,dove-core-clock", dove_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst dove_gating_desc[] = {
+        { "usb0", NULL, 0, 0 },
+        { "usb1", NULL, 1, 0 },
+        { "ge", "gephy", 2, 0 },
+        { "sata", NULL, 3, 0 },
+        { "pex0", NULL, 4, 0 },
+        { "pex1", NULL, 5, 0 },
+        { "sdio0", NULL, 8, 0 },
+        { "sdio1", NULL, 9, 0 },
+        { "nand", NULL, 10, 0 },
+        { "camera", NULL, 11, 0 },
+        { "i2s0", NULL, 12, 0 },
+        { "i2s1", NULL, 13, 0 },
+        { "crypto", NULL, 15, 0 },
+        { "ac97", NULL, 21, 0 },
+        { "pdma", NULL, 22, 0 },
+        { "xor0", NULL, 23, 0 },
+        { "xor1", NULL, 24, 0 },
+        { "gephy", NULL, 30, 0 },
+        { }
+};
+
+static void __init dove_clk_gating_init(struct device_node *np)
+{
+        mvebu_clk_gating_setup(np, dove_gating_desc);
+}
+CLK_OF_DECLARE(dove_clk_gating, "marvell,dove-gating-clock",
+               dove_clk_gating_init);
diff --git a/drivers/clk/mvebu/kirkwood.c b/drivers/clk/mvebu/kirkwood.c
new file mode 100644
index 000000000000..71d24619ccdb
--- /dev/null
+++ b/drivers/clk/mvebu/kirkwood.c
@@ -0,0 +1,247 @@
+/*
+ * Marvell Kirkwood SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Kirkwood PLL sample-at-reset configuration
+ * (6180 has different SAR layout than other Kirkwood SoCs)
+ *
+ * SAR0[4:3,22,1] : CPU frequency (6281,6292,6282)
+ *      4  =  600 MHz
+ *      6  =  800 MHz
+ *      7  = 1000 MHz
+ *      9  = 1200 MHz
+ *      12 = 1500 MHz
+ *      13 = 1600 MHz
+ *      14 = 1800 MHz
+ *      15 = 2000 MHz
+ *      others reserved.
+ *
+ * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
+ *      1 = (1/2) * CPU
+ *      3 = (1/3) * CPU
+ *      5 = (1/4) * CPU
+ *      others reserved.
+ *
+ * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282)
+ *      2 = (1/2) * CPU
+ *      4 = (1/3) * CPU
+ *      6 = (1/4) * CPU
+ *      7 = (2/9) * CPU
+ *      8 = (1/5) * CPU
+ *      9 = (1/6) * CPU
+ *      others reserved.
+ *
+ * SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only)
+ *      5 = [CPU =  600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU]
+ *      6 = [CPU =  800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU]
+ *      7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU]
+ *      others reserved.
+ *
+ * SAR0[21] : TCLK frequency
+ *      0 = 200 MHz
+ *      1 = 166 MHz
+ *      others reserved.
+ */
+
+#define SAR_KIRKWOOD_CPU_FREQ(x)        \
+        (((x & (1 <<  1)) >>  1) |      \
+         ((x & (1 << 22)) >> 21) |      \
+         ((x & (3 <<  3)) >>  1))
+#define SAR_KIRKWOOD_L2_RATIO(x)        \
+        (((x & (3 <<  9)) >> 9) |       \
+         (((x & (1 << 19)) >> 17)))
+#define SAR_KIRKWOOD_DDR_RATIO          5
+#define SAR_KIRKWOOD_DDR_RATIO_MASK     0xf
+#define SAR_MV88F6180_CLK               2
+#define SAR_MV88F6180_CLK_MASK          0x7
+#define SAR_KIRKWOOD_TCLK_FREQ          21
+#define SAR_KIRKWOOD_TCLK_FREQ_MASK     0x1
+
+enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR };
+
+static const struct coreclk_ratio __initconst kirkwood_coreclk_ratios[] = {
+        { .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", },
+        { .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", }
+};
+
+static u32 __init kirkwood_get_tclk_freq(void __iomem *sar)
+{
+        u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) &
+                SAR_KIRKWOOD_TCLK_FREQ_MASK;
+        return (opt) ? 166666667 : 200000000;
+}
+
+static const u32 __initconst kirkwood_cpu_freqs[] = {
+        0, 0, 0, 0,
+        600000000,
+        0,
+        800000000,
+        1000000000,
+        0,
+        1200000000,
+        0, 0,
+        1500000000,
+        1600000000,
+        1800000000,
+        2000000000
+};
+
+static u32 __init kirkwood_get_cpu_freq(void __iomem *sar)
+{
+        u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar));
+        return kirkwood_cpu_freqs[opt];
+}
+
+static const int __initconst kirkwood_cpu_l2_ratios[8][2] = {
+        { 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 },
+        { 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 }
+};
+
+static const int __initconst kirkwood_cpu_ddr_ratios[16][2] = {
+        { 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
+        { 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 },
+        { 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 },
+        { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
+};
+
+static void __init kirkwood_get_clk_ratio(
+        void __iomem *sar, int id, int *mult, int *div)
+{
+        switch (id) {
+        case KIRKWOOD_CPU_TO_L2:
+        {
+                u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar));
+                *mult = kirkwood_cpu_l2_ratios[opt][0];
+                *div = kirkwood_cpu_l2_ratios[opt][1];
+                break;
+        }
+        case KIRKWOOD_CPU_TO_DDR:
+        {
+                u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) &
+                        SAR_KIRKWOOD_DDR_RATIO_MASK;
+                *mult = kirkwood_cpu_ddr_ratios[opt][0];
+                *div = kirkwood_cpu_ddr_ratios[opt][1];
+                break;
+        }
+        }
+}
+
+static const u32 __initconst mv88f6180_cpu_freqs[] = {
+        0, 0, 0, 0, 0,
+        600000000,
+        800000000,
+        1000000000
+};
+
+static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar)
+{
+        u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK;
+        return mv88f6180_cpu_freqs[opt];
+}
+
+static const int __initconst mv88f6180_cpu_ddr_ratios[8][2] = {
+        { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
+        { 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 }
+};
+
+static void __init mv88f6180_get_clk_ratio(
+        void __iomem *sar, int id, int *mult, int *div)
+{
+        switch (id) {
+        case KIRKWOOD_CPU_TO_L2:
+        {
+                /* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */
+                *mult = 1;
+                *div = 2;
+                break;
+        }
+        case KIRKWOOD_CPU_TO_DDR:
+        {
+                u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) &
+                        SAR_MV88F6180_CLK_MASK;
+                *mult = mv88f6180_cpu_ddr_ratios[opt][0];
+                *div = mv88f6180_cpu_ddr_ratios[opt][1];
+                break;
+        }
+        }
+}
+
+static const struct coreclk_soc_desc kirkwood_coreclks = {
+        .get_tclk_freq = kirkwood_get_tclk_freq,
+        .get_cpu_freq = kirkwood_get_cpu_freq,
+        .get_clk_ratio = kirkwood_get_clk_ratio,
+        .ratios = kirkwood_coreclk_ratios,
+        .num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
+};
+
+static void __init kirkwood_coreclk_init(struct device_node *np)
+{
+        mvebu_coreclk_setup(np, &kirkwood_coreclks);
+}
+CLK_OF_DECLARE(kirkwood_core_clk, "marvell,kirkwood-core-clock",
+               kirkwood_coreclk_init);
+
+static const struct coreclk_soc_desc mv88f6180_coreclks = {
+        .get_tclk_freq = kirkwood_get_tclk_freq,
+        .get_cpu_freq = mv88f6180_get_cpu_freq,
+        .get_clk_ratio = mv88f6180_get_clk_ratio,
+        .ratios = kirkwood_coreclk_ratios,
+        .num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
+};
+
+static void __init mv88f6180_coreclk_init(struct device_node *np)
+{
+        mvebu_coreclk_setup(np, &mv88f6180_coreclks);
+}
+CLK_OF_DECLARE(mv88f6180_core_clk, "marvell,mv88f6180-core-clock",
+               mv88f6180_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst kirkwood_gating_desc[] = {
+        { "ge0", NULL, 0, 0 },
+        { "pex0", NULL, 2, 0 },
+        { "usb0", NULL, 3, 0 },
+        { "sdio", NULL, 4, 0 },
+        { "tsu", NULL, 5, 0 },
+        { "runit", NULL, 7, 0 },
+        { "xor0", NULL, 8, 0 },
+        { "audio", NULL, 9, 0 },
+        { "powersave", "cpuclk", 11, 0 },
+        { "sata0", NULL, 14, 0 },
+        { "sata1", NULL, 15, 0 },
+        { "xor1", NULL, 16, 0 },
+        { "crypto", NULL, 17, 0 },
+        { "pex1", NULL, 18, 0 },
+        { "ge1", NULL, 19, 0 },
+        { "tdm", NULL, 20, 0 },
+        { }
+};
+
+static void __init kirkwood_clk_gating_init(struct device_node *np)
+{
+        mvebu_clk_gating_setup(np, kirkwood_gating_desc);
+}
+CLK_OF_DECLARE(kirkwood_clk_gating, "marvell,kirkwood-gating-clock",
+               kirkwood_clk_gating_init);
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index d0e5eed146de..4faf0afc44cd 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -10,6 +10,7 @@
  */
 
 #include <linux/clk.h>
+#include <linux/clk/mxs.h>
 #include <linux/clkdev.h>
 #include <linux/err.h>
 #include <linux/init.h>
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index d0940e69d034..3c1f88868f29 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -791,7 +791,8 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
         GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
         GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
         GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
-        GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
+        GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
+                        CLK_IGNORE_UNUSED, 0),
         GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0),
         GATE(smmu_rotator, "smmu_rotator", "aclk200",
                         E4210_GATE_IP_IMAGE, 4, 0, 0),
@@ -819,7 +820,8 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
         GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0),
         GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
         GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
-        GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 0, 0),
+        GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
+                        CLK_IGNORE_UNUSED, 0),
         GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0),
         GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0",
                         SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
index bd11315cf5ab..5bb848cac6ec 100644
--- a/drivers/clk/socfpga/clk.c
+++ b/drivers/clk/socfpga/clk.c
@@ -24,15 +24,17 @@
 #include <linux/of.h>
 
 /* Clock Manager offsets */
-#define CLKMGR_CTRL    0x0
-#define CLKMGR_BYPASS 0x4
+#define CLKMGR_CTRL     0x0
+#define CLKMGR_BYPASS   0x4
+#define CLKMGR_L4SRC    0x70
+#define CLKMGR_PERPLL_SRC       0xAC
 
 /* Clock bypass bits */
-#define MAINPLL_BYPASS (1<<0)
-#define SDRAMPLL_BYPASS (1<<1)
-#define SDRAMPLL_SRC_BYPASS (1<<2)
-#define PERPLL_BYPASS (1<<3)
-#define PERPLL_SRC_BYPASS (1<<4)
+#define MAINPLL_BYPASS          (1<<0)
+#define SDRAMPLL_BYPASS         (1<<1)
+#define SDRAMPLL_SRC_BYPASS     (1<<2)
+#define PERPLL_BYPASS           (1<<3)
+#define PERPLL_SRC_BYPASS       (1<<4)
 
 #define SOCFPGA_PLL_BG_PWRDWN           0
 #define SOCFPGA_PLL_EXT_ENA             1
@@ -41,6 +43,17 @@
 #define SOCFPGA_PLL_DIVF_SHIFT  3
 #define SOCFPGA_PLL_DIVQ_MASK           0x003F0000
 #define SOCFPGA_PLL_DIVQ_SHIFT  16
+#define SOCFGPA_MAX_PARENTS     3
+
+#define SOCFPGA_L4_MP_CLK               "l4_mp_clk"
+#define SOCFPGA_L4_SP_CLK               "l4_sp_clk"
+#define SOCFPGA_NAND_CLK                "nand_clk"
+#define SOCFPGA_NAND_X_CLK              "nand_x_clk"
+#define SOCFPGA_MMC_CLK                 "mmc_clk"
+#define SOCFPGA_DB_CLK                  "gpio_db_clk"
+
+#define div_mask(width) ((1 << (width)) - 1)
+#define streq(a, b) (strcmp((a), (b)) == 0)
 
 extern void __iomem *clk_mgr_base_addr;
 
@@ -49,6 +62,9 @@ struct socfpga_clk {
         char *parent_name;
         char *clk_name;
         u32 fixed_div;
+        void __iomem *div_reg;
+        u32 width;      /* only valid if div_reg != 0 */
+        u32 shift;      /* only valid if div_reg != 0 */
 };
 #define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw.hw)
 
@@ -132,8 +148,9 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
 
         socfpga_clk->hw.hw.init = &init;
 
-        if (strcmp(clk_name, "main_pll") || strcmp(clk_name, "periph_pll") ||
-                        strcmp(clk_name, "sdram_pll")) {
+        if (streq(clk_name, "main_pll") ||
+                streq(clk_name, "periph_pll") ||
+                streq(clk_name, "sdram_pll")) {
                 socfpga_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
                 clk_pll_ops.enable = clk_gate_ops.enable;
                 clk_pll_ops.disable = clk_gate_ops.disable;
@@ -148,6 +165,159 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
         return clk;
 }
 
+static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
+{
+        u32 l4_src;
+        u32 perpll_src;
+
+        if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
+                l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+                return l4_src &= 0x1;
+        }
+        if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
+                l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+                return !!(l4_src & 2);
+        }
+
+        perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+        if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
+                return perpll_src &= 0x3;
+        if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
+                        streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
+                        return (perpll_src >> 2) & 3;
+
+        /* QSPI clock */
+        return (perpll_src >> 4) & 3;
+
+}
+
+static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
+{
+        u32 src_reg;
+
+        if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
+                src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+                src_reg &= ~0x1;
+                src_reg |= parent;
+                writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
+        } else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
+                src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+                src_reg &= ~0x2;
+                src_reg |= (parent << 1);
+                writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
+        } else {
+                src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+                if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
+                        src_reg &= ~0x3;
+                        src_reg |= parent;
+                } else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
+                        streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
+                        src_reg &= ~0xC;
+                        src_reg |= (parent << 2);
+                } else {/* QSPI clock */
+                        src_reg &= ~0x30;
+                        src_reg |= (parent << 4);
+                }
+                writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+        }
+
+        return 0;
+}
+
+static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
+        unsigned long parent_rate)
+{
+        struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
+        u32 div = 1, val;
+
+        if (socfpgaclk->fixed_div)
+                div = socfpgaclk->fixed_div;
+        else if (socfpgaclk->div_reg) {
+                val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
+                val &= div_mask(socfpgaclk->width);
+                if (streq(hwclk->init->name, SOCFPGA_DB_CLK))
+                        div = val + 1;
+                else
+                        div = (1 << val);
+        }
+
+        return parent_rate / div;
+}
+
+static struct clk_ops gateclk_ops = {
+        .recalc_rate = socfpga_clk_recalc_rate,
+        .get_parent = socfpga_clk_get_parent,
+        .set_parent = socfpga_clk_set_parent,
+};
+
+static void __init socfpga_gate_clk_init(struct device_node *node,
+        const struct clk_ops *ops)
+{
+        u32 clk_gate[2];
+        u32 div_reg[3];
+        u32 fixed_div;
+        struct clk *clk;
+        struct socfpga_clk *socfpga_clk;
+        const char *clk_name = node->name;
+        const char *parent_name[SOCFGPA_MAX_PARENTS];
+        struct clk_init_data init;
+        int rc;
+        int i = 0;
+
+        socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
+        if (WARN_ON(!socfpga_clk))
+                return;
+
+        rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
+        if (rc)
+                clk_gate[0] = 0;
+
+        if (clk_gate[0]) {
+                socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
+                socfpga_clk->hw.bit_idx = clk_gate[1];
+
+                gateclk_ops.enable = clk_gate_ops.enable;
+                gateclk_ops.disable = clk_gate_ops.disable;
+        }
+
+        rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
+        if (rc)
+                socfpga_clk->fixed_div = 0;
+        else
+                socfpga_clk->fixed_div = fixed_div;
+
+        rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
+        if (!rc) {
+                socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
+                socfpga_clk->shift = div_reg[1];
+                socfpga_clk->width = div_reg[2];
+        } else {
+                socfpga_clk->div_reg = 0;
+        }
+
+        of_property_read_string(node, "clock-output-names", &clk_name);
+
+        init.name = clk_name;
+        init.ops = ops;
+        init.flags = 0;
+        while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
+                        of_clk_get_parent_name(node, i)) != NULL)
+                i++;
+
+        init.parent_names = parent_name;
+        init.num_parents = i;
+        socfpga_clk->hw.hw.init = &init;
+
+        clk = clk_register(NULL, &socfpga_clk->hw.hw);
+        if (WARN_ON(IS_ERR(clk))) {
+                kfree(socfpga_clk);
+                return;
+        }
+        rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+        if (WARN_ON(rc))
+                return;
+}
+
 static void __init socfpga_pll_init(struct device_node *node)
 {
         socfpga_clk_init(node, &clk_pll_ops);
@@ -160,6 +330,12 @@ static void __init socfpga_periph_init(struct device_node *node)
 }
 CLK_OF_DECLARE(socfpga_periph, "altr,socfpga-perip-clk", socfpga_periph_init);
 
+static void __init socfpga_gate_init(struct device_node *node)
+{
+        socfpga_gate_clk_init(node, &gateclk_ops);
+}
+CLK_OF_DECLARE(socfpga_gate, "altr,socfpga-gate-clk", socfpga_gate_init);
+
 void __init socfpga_init_clocks(void)
 {
         struct clk *clk;
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index d78e16ee161c..40d939d091bf 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -250,6 +250,9 @@
 #define CLK_SOURCE_XUSB_DEV_SRC 0x60c
 #define CLK_SOURCE_EMC 0x19c
 
+/* Tegra CPU clock and reset control regs */
+#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS     0x470
+
 static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
 
 static void __iomem *clk_base;
@@ -2000,7 +2003,25 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
         }
 }
 
-static struct tegra_cpu_car_ops tegra114_cpu_car_ops;
+/* Tegra114 CPU clock and reset control functions */
+static void tegra114_wait_cpu_in_reset(u32 cpu)
+{
+        unsigned int reg;
+
+        do {
+                reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+                cpu_relax();
+        } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
+}
+static void tegra114_disable_cpu_clock(u32 cpu)
+{
+        /* flow controller would take care in the power sequence. */
+}
+
+static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
+        .wait_for_reset = tegra114_wait_cpu_in_reset,
+        .disable_clock  = tegra114_disable_cpu_clock,
+};
 
 static const struct of_device_id pmc_match[] __initconst = {
         { .compatible = "nvidia,tegra114-pmc" },
diff --git a/drivers/clk/ux500/clk-sysctrl.c b/drivers/clk/ux500/clk-sysctrl.c
index bc7e9bde792b..e364c9d4aa60 100644
--- a/drivers/clk/ux500/clk-sysctrl.c
+++ b/drivers/clk/ux500/clk-sysctrl.c
@@ -145,7 +145,13 @@ static struct clk *clk_reg_sysctrl(struct device *dev,
                 return ERR_PTR(-ENOMEM);
         }
 
-        for (i = 0; i < num_parents; i++) {
+        /* set main clock registers */
+        clk->reg_sel[0] = reg_sel[0];
+        clk->reg_bits[0] = reg_bits[0];
+        clk->reg_mask[0] = reg_mask[0];
+
+        /* handle clocks with more than one parent */
+        for (i = 1; i < num_parents; i++) {
                 clk->reg_sel[i] = reg_sel[i];
                 clk->reg_bits[i] = reg_bits[i];
                 clk->reg_mask[i] = reg_mask[i];
diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
index 0b4f35a5ffc2..80069c370a47 100644
--- a/drivers/clk/ux500/u8500_clk.c
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -325,7 +325,7 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
         clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
                                 BIT(0), 0);
         clk_register_clkdev(clk, "fsmc", NULL);
-        clk_register_clkdev(clk, NULL, "smsc911x");
+        clk_register_clkdev(clk, NULL, "smsc911x.0");
 
         clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
                                 BIT(1), 0);
diff --git a/drivers/clk/zynq/Makefile b/drivers/clk/zynq/Makefile
new file mode 100644
index 000000000000..156d923f4fa9
--- /dev/null
+++ b/drivers/clk/zynq/Makefile
@@ -0,0 +1,3 @@
+# Zynq clock specific Makefile
+
+obj-$(CONFIG_ARCH_ZYNQ) += clkc.o pll.o
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
new file mode 100644
index 000000000000..5c205b60a82a
--- /dev/null
+++ b/drivers/clk/zynq/clkc.c
@@ -0,0 +1,533 @@
+/*
+ * Zynq clock controller
+ *
+ *  Copyright (C) 2012 - 2013 Xilinx
+ *
+ *  Sören Brinkmann <soren.brinkmann@xilinx.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk/zynq.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/io.h>
+
+static void __iomem *zynq_slcr_base_priv;
+
+#define SLCR_ARMPLL_CTRL                (zynq_slcr_base_priv + 0x100)
+#define SLCR_DDRPLL_CTRL                (zynq_slcr_base_priv + 0x104)
+#define SLCR_IOPLL_CTRL                 (zynq_slcr_base_priv + 0x108)
+#define SLCR_PLL_STATUS                 (zynq_slcr_base_priv + 0x10c)
+#define SLCR_ARM_CLK_CTRL               (zynq_slcr_base_priv + 0x120)
+#define SLCR_DDR_CLK_CTRL               (zynq_slcr_base_priv + 0x124)
+#define SLCR_DCI_CLK_CTRL               (zynq_slcr_base_priv + 0x128)
+#define SLCR_APER_CLK_CTRL              (zynq_slcr_base_priv + 0x12c)
+#define SLCR_GEM0_CLK_CTRL              (zynq_slcr_base_priv + 0x140)
+#define SLCR_GEM1_CLK_CTRL              (zynq_slcr_base_priv + 0x144)
+#define SLCR_SMC_CLK_CTRL               (zynq_slcr_base_priv + 0x148)
+#define SLCR_LQSPI_CLK_CTRL             (zynq_slcr_base_priv + 0x14c)
+#define SLCR_SDIO_CLK_CTRL              (zynq_slcr_base_priv + 0x150)
+#define SLCR_UART_CLK_CTRL              (zynq_slcr_base_priv + 0x154)
+#define SLCR_SPI_CLK_CTRL               (zynq_slcr_base_priv + 0x158)
+#define SLCR_CAN_CLK_CTRL               (zynq_slcr_base_priv + 0x15c)
+#define SLCR_CAN_MIOCLK_CTRL            (zynq_slcr_base_priv + 0x160)
+#define SLCR_DBG_CLK_CTRL               (zynq_slcr_base_priv + 0x164)
+#define SLCR_PCAP_CLK_CTRL              (zynq_slcr_base_priv + 0x168)
+#define SLCR_FPGA0_CLK_CTRL             (zynq_slcr_base_priv + 0x170)
+#define SLCR_621_TRUE                   (zynq_slcr_base_priv + 0x1c4)
+#define SLCR_SWDT_CLK_SEL               (zynq_slcr_base_priv + 0x304)
+
+#define NUM_MIO_PINS    54
+
+enum zynq_clk {
+        armpll, ddrpll, iopll,
+        cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
+        ddr2x, ddr3x, dci,
+        lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1,
+        sdio0, sdio1, uart0, uart1, spi0, spi1, dma,
+        usb0_aper, usb1_aper, gem0_aper, gem1_aper,
+        sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper,
+        i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper,
+        smc_aper, swdt, dbg_trc, dbg_apb, clk_max};
+
+static struct clk *ps_clk;
+static struct clk *clks[clk_max];
+static struct clk_onecell_data clk_data;
+
+static DEFINE_SPINLOCK(armpll_lock);
+static DEFINE_SPINLOCK(ddrpll_lock);
+static DEFINE_SPINLOCK(iopll_lock);
+static DEFINE_SPINLOCK(armclk_lock);
+static DEFINE_SPINLOCK(ddrclk_lock);
+static DEFINE_SPINLOCK(dciclk_lock);
+static DEFINE_SPINLOCK(gem0clk_lock);
+static DEFINE_SPINLOCK(gem1clk_lock);
+static DEFINE_SPINLOCK(canclk_lock);
+static DEFINE_SPINLOCK(canmioclk_lock);
+static DEFINE_SPINLOCK(dbgclk_lock);
+static DEFINE_SPINLOCK(aperclk_lock);
+
+static const char dummy_nm[] __initconst = "dummy_name";
+
+static const char *armpll_parents[] __initdata = {"armpll_int", "ps_clk"};
+static const char *ddrpll_parents[] __initdata = {"ddrpll_int", "ps_clk"};
+static const char *iopll_parents[] __initdata = {"iopll_int", "ps_clk"};
+static const char *gem0_mux_parents[] __initdata = {"gem0_div1", dummy_nm};
+static const char *gem1_mux_parents[] __initdata = {"gem1_div1", dummy_nm};
+static const char *can0_mio_mux2_parents[] __initdata = {"can0_gate",
+        "can0_mio_mux"};
+static const char *can1_mio_mux2_parents[] __initdata = {"can1_gate",
+        "can1_mio_mux"};
+static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div",
+        dummy_nm};
+
+static const char *dbgtrc_emio_input_names[] __initdata = {"trace_emio_clk"};
+static const char *gem0_emio_input_names[] __initdata = {"gem0_emio_clk"};
+static const char *gem1_emio_input_names[] __initdata = {"gem1_emio_clk"};
+static const char *swdt_ext_clk_input_names[] __initdata = {"swdt_ext_clk"};
+
+static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
+                const char *clk_name, void __iomem *fclk_ctrl_reg,
+                const char **parents)
+{
+        struct clk *clk;
+        char *mux_name;
+        char *div0_name;
+        char *div1_name;
+        spinlock_t *fclk_lock;
+        spinlock_t *fclk_gate_lock;
+        void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8;
+
+        fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL);
+        if (!fclk_lock)
+                goto err;
+        fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL);
+        if (!fclk_gate_lock)
+                goto err;
+        spin_lock_init(fclk_lock);
+        spin_lock_init(fclk_gate_lock);
+
+        mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name);
+        div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name);
+        div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name);
+
+        clk = clk_register_mux(NULL, mux_name, parents, 4, 0,
+                        fclk_ctrl_reg, 4, 2, 0, fclk_lock);
+
+        clk = clk_register_divider(NULL, div0_name, mux_name,
+                        0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
+                        CLK_DIVIDER_ALLOW_ZERO, fclk_lock);
+
+        clk = clk_register_divider(NULL, div1_name, div0_name,
+                        CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,
+                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+                        fclk_lock);
+
+        clks[fclk] = clk_register_gate(NULL, clk_name,
+                        div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
+                        0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
+        kfree(mux_name);
+        kfree(div0_name);
+        kfree(div1_name);
+
+        return;
+
+err:
+        clks[fclk] = ERR_PTR(-ENOMEM);
+}
+
+static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
+                enum zynq_clk clk1, const char *clk_name0,
+                const char *clk_name1, void __iomem *clk_ctrl,
+                const char **parents, unsigned int two_gates)
+{
+        struct clk *clk;
+        char *mux_name;
+        char *div_name;
+        spinlock_t *lock;
+
+        lock = kmalloc(sizeof(*lock), GFP_KERNEL);
+        if (!lock)
+                goto err;
+        spin_lock_init(lock);
+
+        mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
+        div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
+
+        clk = clk_register_mux(NULL, mux_name, parents, 4, 0,
+                        clk_ctrl, 4, 2, 0, lock);
+
+        clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
+                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
+
+        clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
+                        CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock);
+        if (two_gates)
+                clks[clk1] = clk_register_gate(NULL, clk_name1, div_name,
+                                CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock);
+
+        kfree(mux_name);
+        kfree(div_name);
+
+        return;
+
+err:
+        clks[clk0] = ERR_PTR(-ENOMEM);
+        if (two_gates)
+                clks[clk1] = ERR_PTR(-ENOMEM);
+}
+
+static void __init zynq_clk_setup(struct device_node *np)
+{
+        int i;
+        u32 tmp;
+        int ret;
+        struct clk *clk;
+        char *clk_name;
+        const char *clk_output_name[clk_max];
+        const char *cpu_parents[4];
+        const char *periph_parents[4];
+        const char *swdt_ext_clk_mux_parents[2];
+        const char *can_mio_mux_parents[NUM_MIO_PINS];
+
+        pr_info("Zynq clock init\n");
+
+        /* get clock output names from DT */
+        for (i = 0; i < clk_max; i++) {
+                if (of_property_read_string_index(np, "clock-output-names",
+                                  i, &clk_output_name[i])) {
+                        pr_err("%s: clock output name not in DT\n", __func__);
+                        BUG();
+                }
+        }
+        cpu_parents[0] = clk_output_name[armpll];
+        cpu_parents[1] = clk_output_name[armpll];
+        cpu_parents[2] = clk_output_name[ddrpll];
+        cpu_parents[3] = clk_output_name[iopll];
+        periph_parents[0] = clk_output_name[iopll];
+        periph_parents[1] = clk_output_name[iopll];
+        periph_parents[2] = clk_output_name[armpll];
+        periph_parents[3] = clk_output_name[ddrpll];
+
+        /* ps_clk */
+        ret = of_property_read_u32(np, "ps-clk-frequency", &tmp);
+        if (ret) {
+                pr_warn("ps_clk frequency not specified, using 33 MHz.\n");
+                tmp = 33333333;
+        }
+        ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT,
+                        tmp);
+
+        /* PLLs */
+        clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
+                        SLCR_PLL_STATUS, 0, &armpll_lock);
+        clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
+                        armpll_parents, 2, 0, SLCR_ARMPLL_CTRL, 4, 1, 0,
+                        &armpll_lock);
+
+        clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
+                        SLCR_PLL_STATUS, 1, &ddrpll_lock);
+        clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
+                        ddrpll_parents, 2, 0, SLCR_DDRPLL_CTRL, 4, 1, 0,
+                        &ddrpll_lock);
+
+        clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
+                        SLCR_PLL_STATUS, 2, &iopll_lock);
+        clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
+                        iopll_parents, 2, 0, SLCR_IOPLL_CTRL, 4, 1, 0,
+                        &iopll_lock);
+
+        /* CPU clocks */
+        tmp = readl(SLCR_621_TRUE) & 1;
+        clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, 0,
+                        SLCR_ARM_CLK_CTRL, 4, 2, 0, &armclk_lock);
+        clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
+                        SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+                        CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
+
+        clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x],
+                        "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+                        SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock);
+
+        clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
+                        1, 2);
+        clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],
+                        "cpu_3or2x_div", CLK_IGNORE_UNUSED,
+                        SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock);
+
+        clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
+                        2 + tmp);
+        clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
+                        "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
+                        26, 0, &armclk_lock);
+
+        clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
+                        4 + 2 * tmp);
+        clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],
+                        "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27,
+                        0, &armclk_lock);
+
+        /* Timers */
+        swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x];
+        for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) {
+                int idx = of_property_match_string(np, "clock-names",
+                                swdt_ext_clk_input_names[i]);
+                if (idx >= 0)
+                        swdt_ext_clk_mux_parents[i + 1] =
+                                of_clk_get_parent_name(np, idx);
+                else
+                        swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
+        }
+        clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
+                        swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT,
+                        SLCR_SWDT_CLK_SEL, 0, 1, 0, &gem0clk_lock);
+
+        /* DDR clocks */
+        clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
+                        SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
+                        CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
+        clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],
+                        "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock);
+        clk_prepare_enable(clks[ddr2x]);
+        clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
+                        SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
+                        CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
+        clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],
+                        "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock);
+        clk_prepare_enable(clks[ddr3x]);
+
+        clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
+                        SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+                        CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock);
+        clk = clk_register_divider(NULL, "dci_div1", "dci_div0",
+                        CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,
+                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+                        &dciclk_lock);
+        clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1",
+                        CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0,
+                        &dciclk_lock);
+        clk_prepare_enable(clks[dci]);
+
+        /* Peripheral clocks */
+        for (i = fclk0; i <= fclk3; i++)
+                zynq_clk_register_fclk(i, clk_output_name[i],
+                                SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
+                                periph_parents);
+
+        zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,
+                        SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
+
+        zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL,
+                        SLCR_SMC_CLK_CTRL, periph_parents, 0);
+
+        zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL,
+                        SLCR_PCAP_CLK_CTRL, periph_parents, 0);
+
+        zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0],
+                        clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL,
+                        periph_parents, 1);
+
+        zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0],
+                        clk_output_name[uart1], SLCR_UART_CLK_CTRL,
+                        periph_parents, 1);
+
+        zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0],
+                        clk_output_name[spi1], SLCR_SPI_CLK_CTRL,
+                        periph_parents, 1);
+
+        for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) {
+                int idx = of_property_match_string(np, "clock-names",
+                                gem0_emio_input_names[i]);
+                if (idx >= 0)
+                        gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
+                                        idx);
+        }
+        clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4, 0,
+                        SLCR_GEM0_CLK_CTRL, 4, 2, 0, &gem0clk_lock);
+        clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
+                        SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+                        CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
+        clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",
+                        CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
+                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+                        &gem0clk_lock);
+        clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 0,
+                        SLCR_GEM0_CLK_CTRL, 6, 1, 0, &gem0clk_lock);
+        clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
+                        "gem0_emio_mux", CLK_SET_RATE_PARENT,
+                        SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
+
+        for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) {
+                int idx = of_property_match_string(np, "clock-names",
+                                gem1_emio_input_names[i]);
+                if (idx >= 0)
+                        gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
+                                        idx);
+        }
+        clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4, 0,
+                        SLCR_GEM1_CLK_CTRL, 4, 2, 0, &gem1clk_lock);
+        clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
+                        SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+                        CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
+        clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",
+                        CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
+                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+                        &gem1clk_lock);
+        clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 0,
+                        SLCR_GEM1_CLK_CTRL, 6, 1, 0, &gem1clk_lock);
+        clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
+                        "gem1_emio_mux", CLK_SET_RATE_PARENT,
+                        SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);
+
+        tmp = strlen("mio_clk_00x");
+        clk_name = kmalloc(tmp, GFP_KERNEL);
+        for (i = 0; i < NUM_MIO_PINS; i++) {
+                int idx;
+
+                snprintf(clk_name, tmp, "mio_clk_%2.2d", i);
+                idx = of_property_match_string(np, "clock-names", clk_name);
+                if (idx >= 0)
+                        can_mio_mux_parents[i] = of_clk_get_parent_name(np,
+                                                idx);
+                else
+                        can_mio_mux_parents[i] = dummy_nm;
+        }
+        kfree(clk_name);
+        clk = clk_register_mux(NULL, "can_mux", periph_parents, 4, 0,
+                        SLCR_CAN_CLK_CTRL, 4, 2, 0, &canclk_lock);
+        clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
+                        SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+                        CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
+        clk = clk_register_divider(NULL, "can_div1", "can_div0",
+                        CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,
+                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+                        &canclk_lock);
+        clk = clk_register_gate(NULL, "can0_gate", "can_div1",
+                        CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,
+                        &canclk_lock);
+        clk = clk_register_gate(NULL, "can1_gate", "can_div1",
+                        CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
+                        &canclk_lock);
+        clk = clk_register_mux(NULL, "can0_mio_mux",
+                        can_mio_mux_parents, 54, CLK_SET_RATE_PARENT,
+                        SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, &canmioclk_lock);
+        clk = clk_register_mux(NULL, "can1_mio_mux",
+                        can_mio_mux_parents, 54, CLK_SET_RATE_PARENT,
+                        SLCR_CAN_MIOCLK_CTRL, 16, 6, 0, &canmioclk_lock);
+        clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
+                        can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT,
+                        SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, &canmioclk_lock);
+        clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
+                        can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT,
+                        SLCR_CAN_MIOCLK_CTRL, 22, 1, 0, &canmioclk_lock);
+
+        for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) {
+                int idx = of_property_match_string(np, "clock-names",
+                                dbgtrc_emio_input_names[i]);
+                if (idx >= 0)
+                        dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
+                                        idx);
+        }
+        clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4, 0,
+                        SLCR_DBG_CLK_CTRL, 4, 2, 0, &dbgclk_lock);
+        clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
+                        SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+                        CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
+        clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, 0,
+                        SLCR_DBG_CLK_CTRL, 6, 1, 0, &dbgclk_lock);
+        clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
+                        "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,
+                        0, 0, &dbgclk_lock);
+        clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb],
+                        clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0,
+                        &dbgclk_lock);
+
+        /* One gated clock for all APER clocks. */
+        clks[dma] = clk_register_gate(NULL, clk_output_name[dma],
+                        clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0,
+                        &aperclk_lock);
+        clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0,
+                        &aperclk_lock);
+        clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0,
+                        &aperclk_lock);
+        clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0,
+                        &aperclk_lock);
+        clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0,
+                        &aperclk_lock);
+        clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0,
+                        &aperclk_lock);
+        clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0,
+                        &aperclk_lock);
+        clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0,
+                        &aperclk_lock);
+        clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0,
+                        &aperclk_lock);
+        clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0,
+                        &aperclk_lock);
+        clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0,
+                        &aperclk_lock);
+        clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0,
+                        &aperclk_lock);
+        clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0,
+                        &aperclk_lock);
+        clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0,
+                        &aperclk_lock);
+        clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0,
+                        &aperclk_lock);
+        clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0,
+                        &aperclk_lock);
+        clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0,
+                        &aperclk_lock);
+        clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0,
+                        &aperclk_lock);
+
+        for (i = 0; i < ARRAY_SIZE(clks); i++) {
+                if (IS_ERR(clks[i])) {
+                        pr_err("Zynq clk %d: register failed with %ld\n",
+                               i, PTR_ERR(clks[i]));
+                        BUG();
+                }
+        }
+
+        clk_data.clks = clks;
+        clk_data.clk_num = ARRAY_SIZE(clks);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
+
+void __init zynq_clock_init(void __iomem *slcr_base)
+{
+        zynq_slcr_base_priv = slcr_base;
+        of_clk_init(NULL);
+}
diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c
new file mode 100644
index 000000000000..47e307c25a7b
--- /dev/null
+++ b/drivers/clk/zynq/pll.c
@@ -0,0 +1,235 @@
+/*
+ * Zynq PLL driver
+ *
+ *  Copyright (C) 2013 Xilinx
+ *
+ *  Sören Brinkmann <soren.brinkmann@xilinx.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#include <linux/clk/zynq.h>
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+
+/**
+ * struct zynq_pll
+ * @hw:         Handle between common and hardware-specific interfaces
+ * @pll_ctrl:   PLL control register
+ * @pll_status: PLL status register
+ * @lock:       Register lock
+ * @lockbit:    Indicates the associated PLL_LOCKED bit in the PLL status
+ *              register.
+ */
+struct zynq_pll {
+        struct clk_hw   hw;
+        void __iomem    *pll_ctrl;
+        void __iomem    *pll_status;
+        spinlock_t      *lock;
+        u8              lockbit;
+};
+#define to_zynq_pll(_hw)        container_of(_hw, struct zynq_pll, hw)
+
+/* Register bitfield defines */
+#define PLLCTRL_FBDIV_MASK      0x7f000
+#define PLLCTRL_FBDIV_SHIFT     12
+#define PLLCTRL_BPQUAL_MASK     (1 << 3)
+#define PLLCTRL_PWRDWN_MASK     2
+#define PLLCTRL_PWRDWN_SHIFT    1
+#define PLLCTRL_RESET_MASK      1
+#define PLLCTRL_RESET_SHIFT     0
+
+/**
+ * zynq_pll_round_rate() - Round a clock frequency
+ * @hw:         Handle between common and hardware-specific interfaces
+ * @rate:       Desired clock frequency
+ * @prate:      Clock frequency of parent clock
+ * Returns frequency closest to @rate the hardware can generate.
+ */
+static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long *prate)
+{
+        u32 fbdiv;
+
+        fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
+        if (fbdiv < 13)
+                fbdiv = 13;
+        else if (fbdiv > 66)
+                fbdiv = 66;
+
+        return *prate * fbdiv;
+}
+
+/**
+ * zynq_pll_recalc_rate() - Recalculate clock frequency
+ * @hw:                 Handle between common and hardware-specific interfaces
+ * @parent_rate:        Clock frequency of parent clock
+ * Returns current clock frequency.
+ */
+static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct zynq_pll *clk = to_zynq_pll(hw);
+        u32 fbdiv;
+
+        /*
+         * makes probably sense to redundantly save fbdiv in the struct
+         * zynq_pll to save the IO access.
+         */
+        fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
+                        PLLCTRL_FBDIV_SHIFT;
+
+        return parent_rate * fbdiv;
+}
+
+/**
+ * zynq_pll_is_enabled - Check if a clock is enabled
+ * @hw:         Handle between common and hardware-specific interfaces
+ * Returns 1 if the clock is enabled, 0 otherwise.
+ *
+ * Not sure this is a good idea, but since disabled means bypassed for
+ * this clock implementation we say we are always enabled.
+ */
+static int zynq_pll_is_enabled(struct clk_hw *hw)
+{
+        unsigned long flags = 0;
+        u32 reg;
+        struct zynq_pll *clk = to_zynq_pll(hw);
+
+        spin_lock_irqsave(clk->lock, flags);
+
+        reg = readl(clk->pll_ctrl);
+
+        spin_unlock_irqrestore(clk->lock, flags);
+
+        return !(reg & (PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK));
+}
+
+/**
+ * zynq_pll_enable - Enable clock
+ * @hw:         Handle between common and hardware-specific interfaces
+ * Returns 0 on success
+ */
+static int zynq_pll_enable(struct clk_hw *hw)
+{
+        unsigned long flags = 0;
+        u32 reg;
+        struct zynq_pll *clk = to_zynq_pll(hw);
+
+        if (zynq_pll_is_enabled(hw))
+                return 0;
+
+        pr_info("PLL: enable\n");
+
+        /* Power up PLL and wait for lock */
+        spin_lock_irqsave(clk->lock, flags);
+
+        reg = readl(clk->pll_ctrl);
+        reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK);
+        writel(reg, clk->pll_ctrl);
+        while (!(readl(clk->pll_status) & (1 << clk->lockbit)))
+                ;
+
+        spin_unlock_irqrestore(clk->lock, flags);
+
+        return 0;
+}
+
+/**
+ * zynq_pll_disable - Disable clock
+ * @hw:         Handle between common and hardware-specific interfaces
+ * Returns 0 on success
+ */
+static void zynq_pll_disable(struct clk_hw *hw)
+{
+        unsigned long flags = 0;
+        u32 reg;
+        struct zynq_pll *clk = to_zynq_pll(hw);
+
+        if (!zynq_pll_is_enabled(hw))
+                return;
+
+        pr_info("PLL: shutdown\n");
+
+        /* shut down PLL */
+        spin_lock_irqsave(clk->lock, flags);
+
+        reg = readl(clk->pll_ctrl);
+        reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK;
+        writel(reg, clk->pll_ctrl);
+
+        spin_unlock_irqrestore(clk->lock, flags);
+}
+
+static const struct clk_ops zynq_pll_ops = {
+        .enable = zynq_pll_enable,
+        .disable = zynq_pll_disable,
+        .is_enabled = zynq_pll_is_enabled,
+        .round_rate = zynq_pll_round_rate,
+        .recalc_rate = zynq_pll_recalc_rate
+};
+
+/**
+ * clk_register_zynq_pll() - Register PLL with the clock framework
+ * @np  Pointer to the DT device node
+ */
+struct clk *clk_register_zynq_pll(const char *name, const char *parent,
+                void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
+                spinlock_t *lock)
+{
+        struct zynq_pll *pll;
+        struct clk *clk;
+        u32 reg;
+        const char *parent_arr[1] = {parent};
+        unsigned long flags = 0;
+        struct clk_init_data initd = {
+                .name = name,
+                .parent_names = parent_arr,
+                .ops = &zynq_pll_ops,
+                .num_parents = 1,
+                .flags = 0
+        };
+
+        pll = kmalloc(sizeof(*pll), GFP_KERNEL);
+        if (!pll) {
+                pr_err("%s: Could not allocate Zynq PLL clk.\n", __func__);
+                return ERR_PTR(-ENOMEM);
+        }
+
+        /* Populate the struct */
+        pll->hw.init = &initd;
+        pll->pll_ctrl = pll_ctrl;
+        pll->pll_status = pll_status;
+        pll->lockbit = lock_index;
+        pll->lock = lock;
+
+        spin_lock_irqsave(pll->lock, flags);
+
+        reg = readl(pll->pll_ctrl);
+        reg &= ~PLLCTRL_BPQUAL_MASK;
+        writel(reg, pll->pll_ctrl);
+
+        spin_unlock_irqrestore(pll->lock, flags);
+
+        clk = clk_register(NULL, &pll->hw);
+        if (WARN_ON(IS_ERR(clk)))
+                goto free_pll;
+
+        return clk;
+
+free_pll:
+        kfree(pll);
+
+        return clk;
+}
diff --git a/drivers/clocksource/cadence_ttc_timer.c b/drivers/clocksource/cadence_ttc_timer.c
index 685bc60e210a..4cbe28c74631 100644
--- a/drivers/clocksource/cadence_ttc_timer.c
+++ b/drivers/clocksource/cadence_ttc_timer.c
@@ -51,6 +51,8 @@
 
 #define TTC_CNT_CNTRL_DISABLE_MASK      0x1
 
+#define TTC_CLK_CNTRL_CSRC_MASK         (1 << 5)        /* clock source */
+
 /*
  * Setup the timers to use pre-scaling, using a fixed value for now that will
  * work across most input frequency, but it may need to be more dynamic
@@ -396,8 +398,9 @@ static void __init ttc_timer_init(struct device_node *timer)
 {
         unsigned int irq;
         void __iomem *timer_baseaddr;
-        struct clk *clk;
+        struct clk *clk_cs, *clk_ce;
         static int initialized;
+        int clksel;
 
         if (initialized)
                 return;
@@ -421,14 +424,24 @@ static void __init ttc_timer_init(struct device_node *timer)
                 BUG();
         }
 
-        clk = of_clk_get_by_name(timer, "cpu_1x");
-        if (IS_ERR(clk)) {
+        clksel = __raw_readl(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
+        clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
+        clk_cs = of_clk_get(timer, clksel);
+        if (IS_ERR(clk_cs)) {
+                pr_err("ERROR: timer input clock not found\n");
+                BUG();
+        }
+
+        clksel = __raw_readl(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
+        clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
+        clk_ce = of_clk_get(timer, clksel);
+        if (IS_ERR(clk_ce)) {
                 pr_err("ERROR: timer input clock not found\n");
                 BUG();
         }
 
-        ttc_setup_clocksource(clk, timer_baseaddr);
-        ttc_setup_clockevent(clk, timer_baseaddr + 4, irq);
+        ttc_setup_clocksource(clk_cs, timer_baseaddr);
+        ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
 
         pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
 }
diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
index 11b8b4b54ceb..edc089e9d0c4 100644
--- a/drivers/cpufreq/acpi-cpufreq.c
+++ b/drivers/cpufreq/acpi-cpufreq.c
@@ -347,11 +347,11 @@ static u32 get_cur_val(const struct cpumask *mask)
         switch (per_cpu(acfreq_data, cpumask_first(mask))->cpu_feature) {
         case SYSTEM_INTEL_MSR_CAPABLE:
                 cmd.type = SYSTEM_INTEL_MSR_CAPABLE;
-                cmd.addr.msr.reg = MSR_IA32_PERF_STATUS;
+                cmd.addr.msr.reg = MSR_IA32_PERF_CTL;
                 break;
         case SYSTEM_AMD_MSR_CAPABLE:
                 cmd.type = SYSTEM_AMD_MSR_CAPABLE;
-                cmd.addr.msr.reg = MSR_AMD_PERF_STATUS;
+                cmd.addr.msr.reg = MSR_AMD_PERF_CTL;
                 break;
         case SYSTEM_IO_CAPABLE:
                 cmd.type = SYSTEM_IO_CAPABLE;
diff --git a/drivers/cpufreq/cpufreq-cpu0.c b/drivers/cpufreq/cpufreq-cpu0.c
index a64eb8b70444..ad1fde277661 100644
--- a/drivers/cpufreq/cpufreq-cpu0.c
+++ b/drivers/cpufreq/cpufreq-cpu0.c
@@ -45,7 +45,7 @@ static int cpu0_set_target(struct cpufreq_policy *policy,
         struct cpufreq_freqs freqs;
         struct opp *opp;
         unsigned long volt = 0, volt_old = 0, tol = 0;
-        long freq_Hz;
+        long freq_Hz, freq_exact;
         unsigned int index;
         int ret;
 
@@ -60,6 +60,7 @@ static int cpu0_set_target(struct cpufreq_policy *policy,
         freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
         if (freq_Hz < 0)
                 freq_Hz = freq_table[index].frequency * 1000;
+        freq_exact = freq_Hz;
         freqs.new = freq_Hz / 1000;
         freqs.old = clk_get_rate(cpu_clk) / 1000;
 
@@ -98,7 +99,7 @@ static int cpu0_set_target(struct cpufreq_policy *policy,
                 }
         }
 
-        ret = clk_set_rate(cpu_clk, freqs.new * 1000);
+        ret = clk_set_rate(cpu_clk, freq_exact);
         if (ret) {
                 pr_err("failed to set clock rate: %d\n", ret);
                 if (cpu_reg)
diff --git a/drivers/cpufreq/cpufreq_governor.c b/drivers/cpufreq/cpufreq_governor.c
index 5af40ad82d23..dc9b72e25c1a 100644
--- a/drivers/cpufreq/cpufreq_governor.c
+++ b/drivers/cpufreq/cpufreq_governor.c
@@ -26,6 +26,7 @@
 #include <linux/tick.h>
 #include <linux/types.h>
 #include <linux/workqueue.h>
+#include <linux/cpu.h>
 
 #include "cpufreq_governor.h"
 
@@ -180,8 +181,10 @@ void gov_queue_work(struct dbs_data *dbs_data, struct cpufreq_policy *policy,
         if (!all_cpus) {
                 __gov_queue_work(smp_processor_id(), dbs_data, delay);
         } else {
+                get_online_cpus();
                 for_each_cpu(i, policy->cpus)
                         __gov_queue_work(i, dbs_data, delay);
+                put_online_cpus();
         }
 }
 EXPORT_SYMBOL_GPL(gov_queue_work);
diff --git a/drivers/cpuidle/cpuidle-calxeda.c b/drivers/cpuidle/cpuidle-calxeda.c
index 223379169cb0..0e6e408c0a63 100644
--- a/drivers/cpuidle/cpuidle-calxeda.c
+++ b/drivers/cpuidle/cpuidle-calxeda.c
@@ -37,20 +37,6 @@
 extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
 extern void *scu_base_addr;
 
-static inline unsigned int get_auxcr(void)
-{
-        unsigned int val;
-        asm("mrc p15, 0, %0, c1, c0, 1  @ get AUXCR" : "=r" (val) : : "cc");
-        return val;
-}
-
-static inline void set_auxcr(unsigned int val)
-{
-        asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR"
-          : : "r" (val) : "cc");
-        isb();
-}
-
 static noinline void calxeda_idle_restore(void)
 {
         set_cr(get_cr() | CR_C);
diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
index 765fdf5ce579..bf416a8391a7 100644
--- a/drivers/crypto/caam/caamalg.c
+++ b/drivers/crypto/caam/caamalg.c
@@ -1154,7 +1154,7 @@ static struct aead_edesc *aead_edesc_alloc(struct aead_request *req,
                 dst_nents = sg_count(req->dst, req->cryptlen, &dst_chained);
 
         sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1,
-                                 DMA_BIDIRECTIONAL, assoc_chained);
+                                 DMA_TO_DEVICE, assoc_chained);
         if (likely(req->src == req->dst)) {
                 sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
                                          DMA_BIDIRECTIONAL, src_chained);
@@ -1336,7 +1336,7 @@ static struct aead_edesc *aead_giv_edesc_alloc(struct aead_givcrypt_request
                 dst_nents = sg_count(req->dst, req->cryptlen, &dst_chained);
 
         sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1,
-                                 DMA_BIDIRECTIONAL, assoc_chained);
+                                 DMA_TO_DEVICE, assoc_chained);
         if (likely(req->src == req->dst)) {
                 sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
                                          DMA_BIDIRECTIONAL, src_chained);
diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c
index a97bb6c1596c..c3dc1c04a5df 100644
--- a/drivers/crypto/sahara.c
+++ b/drivers/crypto/sahara.c
@@ -863,7 +863,7 @@ static struct of_device_id sahara_dt_ids[] = {
         { .compatible = "fsl,imx27-sahara" },
         { /* sentinel */ }
 };
-MODULE_DEVICE_TABLE(platform, sahara_dt_ids);
+MODULE_DEVICE_TABLE(of, sahara_dt_ids);
 
 static int sahara_probe(struct platform_device *pdev)
 {
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index 3b23061cdb41..9bfaddd57ef1 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -22,6 +22,7 @@
 #include <linux/uaccess.h>
 #include <linux/debugfs.h>
 #include <linux/platform_data/dma-coh901318.h>
+#include <linux/of_dma.h>
 
 #include "coh901318.h"
 #include "dmaengine.h"
@@ -1788,6 +1789,35 @@ bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
 }
 EXPORT_SYMBOL(coh901318_filter_id);
 
+struct coh901318_filter_args {
+        struct coh901318_base *base;
+        unsigned int ch_nr;
+};
+
+static bool coh901318_filter_base_and_id(struct dma_chan *chan, void *data)
+{
+        struct coh901318_filter_args *args = data;
+
+        if (&args->base->dma_slave == chan->device &&
+            args->ch_nr == to_coh901318_chan(chan)->id)
+                return true;
+
+        return false;
+}
+
+static struct dma_chan *coh901318_xlate(struct of_phandle_args *dma_spec,
+                                        struct of_dma *ofdma)
+{
+        struct coh901318_filter_args args = {
+                .base = ofdma->of_dma_data,
+                .ch_nr = dma_spec->args[0],
+        };
+        dma_cap_mask_t cap;
+        dma_cap_zero(cap);
+        dma_cap_set(DMA_SLAVE, cap);
+
+        return dma_request_channel(cap, coh901318_filter_base_and_id, &args);
+}
 /*
  * DMA channel allocation
  */
@@ -2735,12 +2765,19 @@ static int __init coh901318_probe(struct platform_device *pdev)
         if (err)
                 goto err_register_memcpy;
 
+        err = of_dma_controller_register(pdev->dev.of_node, coh901318_xlate,
+                                         base);
+        if (err)
+                goto err_register_of_dma;
+
         platform_set_drvdata(pdev, base);
         dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
                 (u32) base->virtbase);
 
         return err;
 
+ err_register_of_dma:
+        dma_async_device_unregister(&base->dma_memcpy);
  err_register_memcpy:
         dma_async_device_unregister(&base->dma_slave);
  err_register_slave:
@@ -2752,17 +2789,23 @@ static int coh901318_remove(struct platform_device *pdev)
 {
         struct coh901318_base *base = platform_get_drvdata(pdev);
 
+        of_dma_controller_free(pdev->dev.of_node);
         dma_async_device_unregister(&base->dma_memcpy);
         dma_async_device_unregister(&base->dma_slave);
         coh901318_pool_destroy(&base->pool);
         return 0;
 }
 
+static const struct of_device_id coh901318_dt_match[] = {
+        { .compatible = "stericsson,coh901318" },
+        {},
+};
 
 static struct platform_driver coh901318_driver = {
         .remove = coh901318_remove,
         .driver = {
                 .name   = "coh901318",
+                .of_match_table = coh901318_dt_match,
         },
 };
 
diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c
index d8ce4ecfef18..e88ded2c8d2f 100644
--- a/drivers/dma/dmatest.c
+++ b/drivers/dma/dmatest.c
@@ -716,8 +716,7 @@ static int dmatest_func(void *data)
                 }
                 dma_async_issue_pending(chan);
 
-                wait_event_freezable_timeout(done_wait,
-                                             done.done || kthread_should_stop(),
+                wait_event_freezable_timeout(done_wait, done.done,
                                              msecs_to_jiffies(params->timeout));
 
                 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
@@ -997,7 +996,6 @@ static void stop_threaded_test(struct dmatest_info *info)
 static int __restart_threaded_test(struct dmatest_info *info, bool run)
 {
         struct dmatest_params *params = &info->params;
-        int ret;
 
         /* Stop any running test first */
         __stop_threaded_test(info);
@@ -1012,13 +1010,23 @@ static int __restart_threaded_test(struct dmatest_info *info, bool run)
         memcpy(params, &info->dbgfs_params, sizeof(*params));
 
         /* Run test with new parameters */
-        ret = __run_threaded_test(info);
-        if (ret) {
-                __stop_threaded_test(info);
-                pr_err("dmatest: Can't run test\n");
+        return __run_threaded_test(info);
+}
+
+static bool __is_threaded_test_run(struct dmatest_info *info)
+{
+        struct dmatest_chan *dtc;
+
+        list_for_each_entry(dtc, &info->channels, node) {
+                struct dmatest_thread *thread;
+
+                list_for_each_entry(thread, &dtc->threads, node) {
+                        if (!thread->done)
+                                return true;
+                }
         }
 
-        return ret;
+        return false;
 }
 
 static ssize_t dtf_write_string(void *to, size_t available, loff_t *ppos,
@@ -1091,22 +1099,10 @@ static ssize_t dtf_read_run(struct file *file, char __user *user_buf,
 {
         struct dmatest_info *info = file->private_data;
         char buf[3];
-        struct dmatest_chan *dtc;
-        bool alive = false;
 
         mutex_lock(&info->lock);
-        list_for_each_entry(dtc, &info->channels, node) {
-                struct dmatest_thread *thread;
-
-                list_for_each_entry(thread, &dtc->threads, node) {
-                        if (!thread->done) {
-                                alive = true;
-                                break;
-                        }
-                }
-        }
 
-        if (alive) {
+        if (__is_threaded_test_run(info)) {
                 buf[0] = 'Y';
         } else {
                 __stop_threaded_test(info);
@@ -1132,7 +1128,12 @@ static ssize_t dtf_write_run(struct file *file, const char __user *user_buf,
 
         if (strtobool(buf, &bv) == 0) {
                 mutex_lock(&info->lock);
-                ret = __restart_threaded_test(info, bv);
+
+                if (__is_threaded_test_run(info))
+                        ret = -EBUSY;
+                else
+                        ret = __restart_threaded_test(info, bv);
+
                 mutex_unlock(&info->lock);
         }
 
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index cd7e3280fadd..5f3e532436ee 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -24,7 +24,7 @@
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 
-#include <mach/edma.h>
+#include <linux/platform_data/edma.h>
 
 #include "dmaengine.h"
 #include "virt-dma.h"
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 1734feec47b1..71bf4ec300ea 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -1566,10 +1566,12 @@ static void dma_tc_handle(struct d40_chan *d40c)
                         return;
                 }
 
-                if (d40_queue_start(d40c) == NULL)
+                if (d40_queue_start(d40c) == NULL) {
                         d40c->busy = false;
-                pm_runtime_mark_last_busy(d40c->base->dev);
-                pm_runtime_put_autosuspend(d40c->base->dev);
+
+                        pm_runtime_mark_last_busy(d40c->base->dev);
+                        pm_runtime_put_autosuspend(d40c->base->dev);
+                }
 
                 d40_desc_remove(d40d);
                 d40_desc_done(d40c, d40d);
diff --git a/drivers/firmware/efi/efivars.c b/drivers/firmware/efi/efivars.c
index b623c599e572..8bd1bb6dbe47 100644
--- a/drivers/firmware/efi/efivars.c
+++ b/drivers/firmware/efi/efivars.c
@@ -523,13 +523,11 @@ static void efivar_update_sysfs_entries(struct work_struct *work)
         struct efivar_entry *entry;
         int err;
 
-        entry = kzalloc(sizeof(*entry), GFP_KERNEL);
-        if (!entry)
-                return;
-
         /* Add new sysfs entries */
         while (1) {
-                memset(entry, 0, sizeof(*entry));
+                entry = kzalloc(sizeof(*entry), GFP_KERNEL);
+                if (!entry)
+                        return;
 
                 err = efivar_init(efivar_update_sysfs_entry, entry,
                                   true, false, &efivar_sysfs_list);
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 573c449c49b9..ec1dcdca5b8a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -109,8 +109,11 @@ config GPIO_MAX730X
 comment "Memory mapped GPIO drivers:"
 
 config GPIO_CLPS711X
-        def_bool y
+        tristate "CLPS711X GPIO support"
         depends on ARCH_CLPS711X
+        select GPIO_GENERIC
+        help
+          Say yes here to support GPIO on CLPS711X SoCs.
 
 config GPIO_GENERIC_PLATFORM
         tristate "Generic memory-mapped GPIO controller support (MMIO platform device)"
@@ -209,6 +212,13 @@ config GPIO_RCAR
         help
           Say yes here to support GPIO on Renesas R-Car SoCs.
 
+config GPIO_SAMSUNG
+        bool
+        depends on PLAT_SAMSUNG
+        help
+          Legacy GPIO support. Use only for platforms without support for
+          pinctrl.
+
 config GPIO_SPEAR_SPICS
         bool "ST SPEAr13xx SPI Chip Select as GPIO support"
         depends on PLAT_SPEAR
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 0cb2d656ad16..ef3e983a2f1e 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -59,7 +59,7 @@ obj-$(CONFIG_GPIO_PXA)		+= gpio-pxa.o
 obj-$(CONFIG_GPIO_RC5T583)      += gpio-rc5t583.o
 obj-$(CONFIG_GPIO_RDC321X)      += gpio-rdc321x.o
 obj-$(CONFIG_GPIO_RCAR)         += gpio-rcar.o
-obj-$(CONFIG_PLAT_SAMSUNG)      += gpio-samsung.o
+obj-$(CONFIG_GPIO_SAMSUNG)      += gpio-samsung.o
 obj-$(CONFIG_ARCH_SA1100)       += gpio-sa1100.o
 obj-$(CONFIG_GPIO_SCH)          += gpio-sch.o
 obj-$(CONFIG_GPIO_SODAVILLE)    += gpio-sodaville.o
diff --git a/drivers/gpio/gpio-clps711x.c b/drivers/gpio/gpio-clps711x.c
index ce63b75b13f5..0edaf2ce9266 100644
--- a/drivers/gpio/gpio-clps711x.c
+++ b/drivers/gpio/gpio-clps711x.c
@@ -1,7 +1,7 @@
 /*
  *  CLPS711X GPIO driver
  *
- *  Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
+ *  Copyright (C) 2012,2013 Alexander Shiyan <shc_work@mail.ru>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -9,191 +9,91 @@
  * (at your option) any later version.
  */
 
-#include <linux/io.h>
-#include <linux/slab.h>
+#include <linux/err.h>
 #include <linux/gpio.h>
 #include <linux/module.h>
-#include <linux/spinlock.h>
+#include <linux/basic_mmio_gpio.h>
 #include <linux/platform_device.h>
 
-#include <mach/hardware.h>
-
-#define CLPS711X_GPIO_PORTS     5
-#define CLPS711X_GPIO_NAME      "gpio-clps711x"
-
-struct clps711x_gpio {
-        struct gpio_chip        chip[CLPS711X_GPIO_PORTS];
-        spinlock_t              lock;
-};
-
-static void __iomem *clps711x_ports[] = {
-        CLPS711X_VIRT_BASE + PADR,
-        CLPS711X_VIRT_BASE + PBDR,
-        CLPS711X_VIRT_BASE + PCDR,
-        CLPS711X_VIRT_BASE + PDDR,
-        CLPS711X_VIRT_BASE + PEDR,
-};
-
-static void __iomem *clps711x_pdirs[] = {
-        CLPS711X_VIRT_BASE + PADDR,
-        CLPS711X_VIRT_BASE + PBDDR,
-        CLPS711X_VIRT_BASE + PCDDR,
-        CLPS711X_VIRT_BASE + PDDDR,
-        CLPS711X_VIRT_BASE + PEDDR,
-};
-
-#define clps711x_port(x)        clps711x_ports[x->base / 8]
-#define clps711x_pdir(x)        clps711x_pdirs[x->base / 8]
-
-static int gpio_clps711x_get(struct gpio_chip *chip, unsigned offset)
+static int clps711x_gpio_probe(struct platform_device *pdev)
 {
-        return !!(readb(clps711x_port(chip)) & (1 << offset));
-}
+        struct device_node *np = pdev->dev.of_node;
+        void __iomem *dat, *dir;
+        struct bgpio_chip *bgc;
+        struct resource *res;
+        int err, id = np ? of_alias_get_id(np, "gpio") : pdev->id;
 
-static void gpio_clps711x_set(struct gpio_chip *chip, unsigned offset,
-                              int value)
-{
-        int tmp;
-        unsigned long flags;
-        struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
-
-        spin_lock_irqsave(&gpio->lock, flags);
-        tmp = readb(clps711x_port(chip)) & ~(1 << offset);
-        if (value)
-                tmp |= 1 << offset;
-        writeb(tmp, clps711x_port(chip));
-        spin_unlock_irqrestore(&gpio->lock, flags);
-}
-
-static int gpio_clps711x_dir_in(struct gpio_chip *chip, unsigned offset)
-{
-        int tmp;
-        unsigned long flags;
-        struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
+        if ((id < 0) || (id > 4))
+                return -ENODEV;
 
-        spin_lock_irqsave(&gpio->lock, flags);
-        tmp = readb(clps711x_pdir(chip)) & ~(1 << offset);
-        writeb(tmp, clps711x_pdir(chip));
-        spin_unlock_irqrestore(&gpio->lock, flags);
+        bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
+        if (!bgc)
+                return -ENOMEM;
 
-        return 0;
-}
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        dat = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(dat))
+                return PTR_ERR(dat);
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+        dir = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(dir))
+                return PTR_ERR(dir);
+
+        switch (id) {
+        case 3:
+                /* PORTD is inverted logic for direction register */
+                err = bgpio_init(bgc, &pdev->dev, 1, dat, NULL, NULL,
+                                 NULL, dir, 0);
+                break;
+        default:
+                err = bgpio_init(bgc, &pdev->dev, 1, dat, NULL, NULL,
+                                 dir, NULL, 0);
+                break;
+        }
 
-static int gpio_clps711x_dir_out(struct gpio_chip *chip, unsigned offset,
-                                 int value)
-{
-        int tmp;
-        unsigned long flags;
-        struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
-
-        spin_lock_irqsave(&gpio->lock, flags);
-        tmp = readb(clps711x_pdir(chip)) | (1 << offset);
-        writeb(tmp, clps711x_pdir(chip));
-        tmp = readb(clps711x_port(chip)) & ~(1 << offset);
-        if (value)
-                tmp |= 1 << offset;
-        writeb(tmp, clps711x_port(chip));
-        spin_unlock_irqrestore(&gpio->lock, flags);
-
-        return 0;
-}
+        if (err)
+                return err;
 
-static int gpio_clps711x_dir_in_inv(struct gpio_chip *chip, unsigned offset)
-{
-        int tmp;
-        unsigned long flags;
-        struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
+        switch (id) {
+        case 4:
+                /* PORTE is 3 lines only */
+                bgc->gc.ngpio = 3;
+                break;
+        default:
+                break;
+        }
 
-        spin_lock_irqsave(&gpio->lock, flags);
-        tmp = readb(clps711x_pdir(chip)) | (1 << offset);
-        writeb(tmp, clps711x_pdir(chip));
-        spin_unlock_irqrestore(&gpio->lock, flags);
+        bgc->gc.base = id * 8;
+        platform_set_drvdata(pdev, bgc);
 
-        return 0;
+        return gpiochip_add(&bgc->gc);
 }
 
-static int gpio_clps711x_dir_out_inv(struct gpio_chip *chip, unsigned offset,
-                                     int value)
+static int clps711x_gpio_remove(struct platform_device *pdev)
 {
-        int tmp;
-        unsigned long flags;
-        struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
-
-        spin_lock_irqsave(&gpio->lock, flags);
-        tmp = readb(clps711x_pdir(chip)) & ~(1 << offset);
-        writeb(tmp, clps711x_pdir(chip));
-        tmp = readb(clps711x_port(chip)) & ~(1 << offset);
-        if (value)
-                tmp |= 1 << offset;
-        writeb(tmp, clps711x_port(chip));
-        spin_unlock_irqrestore(&gpio->lock, flags);
-
-        return 0;
+        struct bgpio_chip *bgc = platform_get_drvdata(pdev);
+
+        return bgpio_remove(bgc);
 }
 
-static struct {
-        char    *name;
-        int     nr;
-        int     inv_dir;
-} clps711x_gpio_ports[] __initconst = {
-        { "PORTA", 8, 0, },
-        { "PORTB", 8, 0, },
-        { "PORTC", 8, 0, },
-        { "PORTD", 8, 1, },
-        { "PORTE", 3, 0, },
+static const struct of_device_id clps711x_gpio_ids[] = {
+        { .compatible = "cirrus,clps711x-gpio" },
+        { }
 };
+MODULE_DEVICE_TABLE(of, clps711x_gpio_ids);
+
+static struct platform_driver clps711x_gpio_driver = {
+        .driver = {
+                .name           = "clps711x-gpio",
+                .owner          = THIS_MODULE,
+                .of_match_table = of_match_ptr(clps711x_gpio_ids),
+        },
+        .probe  = clps711x_gpio_probe,
+        .remove = clps711x_gpio_remove,
+};
+module_platform_driver(clps711x_gpio_driver);
 
-static int __init gpio_clps711x_init(void)
-{
-        int i;
-        struct platform_device *pdev;
-        struct clps711x_gpio *gpio;
-
-        pdev = platform_device_alloc(CLPS711X_GPIO_NAME, 0);
-        if (!pdev) {
-                pr_err("Cannot create platform device: %s\n",
-                       CLPS711X_GPIO_NAME);
-                return -ENOMEM;
-        }
-
-        platform_device_add(pdev);
-
-        gpio = devm_kzalloc(&pdev->dev, sizeof(struct clps711x_gpio),
-                            GFP_KERNEL);
-        if (!gpio) {
-                dev_err(&pdev->dev, "GPIO allocating memory error\n");
-                platform_device_unregister(pdev);
-                return -ENOMEM;
-        }
-
-        platform_set_drvdata(pdev, gpio);
-
-        spin_lock_init(&gpio->lock);
-
-        for (i = 0; i < CLPS711X_GPIO_PORTS; i++) {
-                gpio->chip[i].owner             = THIS_MODULE;
-                gpio->chip[i].dev               = &pdev->dev;
-                gpio->chip[i].label             = clps711x_gpio_ports[i].name;
-                gpio->chip[i].base              = i * 8;
-                gpio->chip[i].ngpio             = clps711x_gpio_ports[i].nr;
-                gpio->chip[i].get               = gpio_clps711x_get;
-                gpio->chip[i].set               = gpio_clps711x_set;
-                if (!clps711x_gpio_ports[i].inv_dir) {
-                        gpio->chip[i].direction_input = gpio_clps711x_dir_in;
-                        gpio->chip[i].direction_output = gpio_clps711x_dir_out;
-                } else {
-                        gpio->chip[i].direction_input = gpio_clps711x_dir_in_inv;
-                        gpio->chip[i].direction_output = gpio_clps711x_dir_out_inv;
-                }
-                WARN_ON(gpiochip_add(&gpio->chip[i]));
-        }
-
-        dev_info(&pdev->dev, "GPIO driver initialized\n");
-
-        return 0;
-}
-arch_initcall(gpio_clps711x_init);
-
-MODULE_LICENSE("GPL v2");
+MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
 MODULE_DESCRIPTION("CLPS711X GPIO driver");
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index b4ca450947b8..d173d56dbb8c 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -49,6 +49,7 @@ struct gpio_rcar_priv {
 #define POSNEG 0x20
 #define EDGLEVEL 0x24
 #define FILONOFF 0x28
+#define BOTHEDGE 0x4c
 
 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
 {
@@ -91,7 +92,8 @@ static void gpio_rcar_irq_enable(struct irq_data *d)
 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
                                                   unsigned int hwirq,
                                                   bool active_high_rising_edge,
-                                                  bool level_trigger)
+                                                  bool level_trigger,
+                                                  bool both)
 {
         unsigned long flags;
 
@@ -108,6 +110,10 @@ static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
         /* Configure edge or level trigger in EDGLEVEL */
         gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
 
+        /* Select one edge or both edges in BOTHEDGE */
+        if (p->config.has_both_edge_trigger)
+                gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
+
         /* Select "Interrupt Input Mode" in IOINTSEL */
         gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
 
@@ -127,16 +133,26 @@ static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
 
         switch (type & IRQ_TYPE_SENSE_MASK) {
         case IRQ_TYPE_LEVEL_HIGH:
-                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true);
+                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
+                                                      false);
                 break;
         case IRQ_TYPE_LEVEL_LOW:
-                gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true);
+                gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
+                                                      false);
                 break;
         case IRQ_TYPE_EDGE_RISING:
-                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false);
+                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
+                                                      false);
                 break;
         case IRQ_TYPE_EDGE_FALLING:
-                gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false);
+                gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
+                                                      false);
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                if (!p->config.has_both_edge_trigger)
+                        return -EINVAL;
+                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
+                                                      true);
                 break;
         default:
                 return -EINVAL;
@@ -333,7 +349,7 @@ static int gpio_rcar_probe(struct platform_device *pdev)
         }
 
         if (devm_request_irq(&pdev->dev, irq->start,
-                             gpio_rcar_irq_handler, 0, name, p)) {
+                             gpio_rcar_irq_handler, IRQF_SHARED, name, p)) {
                 dev_err(&pdev->dev, "failed to request IRQ\n");
                 ret = -ENOENT;
                 goto err1;
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index a6a8643a6a77..8bcce7866d36 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -1054,7 +1054,7 @@ EXPORT_SYMBOL(drm_vblank_off);
  */
 void drm_vblank_pre_modeset(struct drm_device *dev, int crtc)
 {
-        /* vblank is not initialized (IRQ not installed ?) */
+        /* vblank is not initialized (IRQ not installed ?), or has been freed */
         if (!dev->num_crtcs)
                 return;
         /*
@@ -1076,6 +1076,10 @@ void drm_vblank_post_modeset(struct drm_device *dev, int crtc)
 {
         unsigned long irqflags;
 
+        /* vblank is not initialized (IRQ not installed ?), or has been freed */
+        if (!dev->num_crtcs)
+                return;
+
         if (dev->vblank_inmodeset[crtc]) {
                 spin_lock_irqsave(&dev->vbl_lock, irqflags);
                 dev->vblank_disable_allowed = 1;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index e8894bc9e6d5..c200e4d71e3d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -48,6 +48,8 @@ struct exynos_drm_crtc {
         unsigned int                    pipe;
         unsigned int                    dpms;
         enum exynos_crtc_mode           mode;
+        wait_queue_head_t               pending_flip_queue;
+        atomic_t                        pending_flip;
 };
 
 static void exynos_drm_crtc_dpms(struct drm_crtc *crtc, int mode)
@@ -61,6 +63,13 @@ static void exynos_drm_crtc_dpms(struct drm_crtc *crtc, int mode)
                 return;
         }
 
+        if (mode > DRM_MODE_DPMS_ON) {
+                /* wait for the completion of page flip. */
+                wait_event(exynos_crtc->pending_flip_queue,
+                                atomic_read(&exynos_crtc->pending_flip) == 0);
+                drm_vblank_off(crtc->dev, exynos_crtc->pipe);
+        }
+
         exynos_drm_fn_encoder(crtc, &mode, exynos_drm_encoder_crtc_dpms);
         exynos_crtc->dpms = mode;
 }
@@ -217,7 +226,6 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
                 ret = drm_vblank_get(dev, exynos_crtc->pipe);
                 if (ret) {
                         DRM_DEBUG("failed to acquire vblank counter\n");
-                        list_del(&event->base.link);
 
                         goto out;
                 }
@@ -225,6 +233,7 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
                 spin_lock_irq(&dev->event_lock);
                 list_add_tail(&event->base.link,
                                 &dev_priv->pageflip_event_list);
+                atomic_set(&exynos_crtc->pending_flip, 1);
                 spin_unlock_irq(&dev->event_lock);
 
                 crtc->fb = fb;
@@ -344,6 +353,8 @@ int exynos_drm_crtc_create(struct drm_device *dev, unsigned int nr)
 
         exynos_crtc->pipe = nr;
         exynos_crtc->dpms = DRM_MODE_DPMS_OFF;
+        init_waitqueue_head(&exynos_crtc->pending_flip_queue);
+        atomic_set(&exynos_crtc->pending_flip, 0);
         exynos_crtc->plane = exynos_plane_init(dev, 1 << nr, true);
         if (!exynos_crtc->plane) {
                 kfree(exynos_crtc);
@@ -398,7 +409,8 @@ void exynos_drm_crtc_finish_pageflip(struct drm_device *dev, int crtc)
 {
         struct exynos_drm_private *dev_priv = dev->dev_private;
         struct drm_pending_vblank_event *e, *t;
-        struct timeval now;
+        struct drm_crtc *drm_crtc = dev_priv->crtc[crtc];
+        struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(drm_crtc);
         unsigned long flags;
 
         DRM_DEBUG_KMS("%s\n", __FILE__);
@@ -411,14 +423,11 @@ void exynos_drm_crtc_finish_pageflip(struct drm_device *dev, int crtc)
                 if (crtc != e->pipe)
                         continue;
 
-                do_gettimeofday(&now);
-                e->event.sequence = 0;
-                e->event.tv_sec = now.tv_sec;
-                e->event.tv_usec = now.tv_usec;
-
-                list_move_tail(&e->base.link, &e->base.file_priv->event_list);
-                wake_up_interruptible(&e->base.file_priv->event_wait);
+                list_del(&e->base.link);
+                drm_send_vblank_event(dev, -1, e);
                 drm_vblank_put(dev, crtc);
+                atomic_set(&exynos_crtc->pending_flip, 0);
+                wake_up(&exynos_crtc->pending_flip_queue);
         }
 
         spin_unlock_irqrestore(&dev->event_lock, flags);
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
index 68f0045f86b8..8f007aaeffc3 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
@@ -182,7 +182,7 @@ static int exynos_drm_fbdev_create(struct drm_fb_helper *helper,
 
         helper->fb = exynos_drm_framebuffer_init(dev, &mode_cmd,
                         &exynos_gem_obj->base);
-        if (IS_ERR_OR_NULL(helper->fb)) {
+        if (IS_ERR(helper->fb)) {
                 DRM_ERROR("failed to create drm framebuffer.\n");
                 ret = PTR_ERR(helper->fb);
                 goto err_destroy_gem;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
index 773f583fa964..4a1616a18ab7 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
@@ -12,9 +12,9 @@
  *
  */
 #include <linux/kernel.h>
-#include <linux/mfd/syscon.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/mfd/syscon.h>
 #include <linux/regmap.h>
 #include <linux/clk.h>
 #include <linux/pm_runtime.h>
@@ -1845,7 +1845,7 @@ static int fimc_probe(struct platform_device *pdev)
         }
 
         ctx->irq = res->start;
-        ret = request_threaded_irq(ctx->irq, NULL, fimc_irq_handler,
+        ret = devm_request_threaded_irq(dev, ctx->irq, NULL, fimc_irq_handler,
                 IRQF_ONESHOT, "drm_fimc", ctx);
         if (ret < 0) {
                 dev_err(dev, "failed to request irq.\n");
@@ -1854,7 +1854,7 @@ static int fimc_probe(struct platform_device *pdev)
 
         ret = fimc_setup_clocks(ctx);
         if (ret < 0)
-                goto err_free_irq;
+                return ret;
 
         ippdrv = &ctx->ippdrv;
         ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &fimc_src_ops;
@@ -1884,7 +1884,7 @@ static int fimc_probe(struct platform_device *pdev)
                 goto err_pm_dis;
         }
 
-        dev_info(&pdev->dev, "drm fimc registered successfully.\n");
+        dev_info(dev, "drm fimc registered successfully.\n");
 
         return 0;
 
@@ -1892,8 +1892,6 @@ err_pm_dis:
         pm_runtime_disable(dev);
 err_put_clk:
         fimc_put_clocks(ctx);
-err_free_irq:
-        free_irq(ctx->irq, ctx);
 
         return ret;
 }
@@ -1911,8 +1909,6 @@ static int fimc_remove(struct platform_device *pdev)
         pm_runtime_set_suspended(dev);
         pm_runtime_disable(dev);
 
-        free_irq(ctx->irq, ctx);
-
         return 0;
 }
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 746b282b343a..97c61dbffd82 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -885,7 +885,7 @@ static int fimd_probe(struct platform_device *pdev)
 
         DRM_DEBUG_KMS("%s\n", __FILE__);
 
-        if (pdev->dev.of_node) {
+        if (dev->of_node) {
                 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
                 if (!pdata) {
                         DRM_ERROR("memory allocation for pdata failed\n");
@@ -899,7 +899,7 @@ static int fimd_probe(struct platform_device *pdev)
                         return ret;
                 }
         } else {
-                pdata = pdev->dev.platform_data;
+                pdata = dev->platform_data;
                 if (!pdata) {
                         DRM_ERROR("no platform data specified\n");
                         return -EINVAL;
@@ -912,7 +912,7 @@ static int fimd_probe(struct platform_device *pdev)
                 return -EINVAL;
         }
 
-        ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
+        ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
         if (!ctx)
                 return -ENOMEM;
 
@@ -930,7 +930,7 @@ static int fimd_probe(struct platform_device *pdev)
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 
-        ctx->regs = devm_ioremap_resource(&pdev->dev, res);
+        ctx->regs = devm_ioremap_resource(dev, res);
         if (IS_ERR(ctx->regs))
                 return PTR_ERR(ctx->regs);
 
@@ -942,7 +942,7 @@ static int fimd_probe(struct platform_device *pdev)
 
         ctx->irq = res->start;
 
-        ret = devm_request_irq(&pdev->dev, ctx->irq, fimd_irq_handler,
+        ret = devm_request_irq(dev, ctx->irq, fimd_irq_handler,
                                                         0, "drm_fimd", ctx);
         if (ret) {
                 dev_err(dev, "irq request failed.\n");
diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
index 47a493c8a71f..af75434ee4d7 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
@@ -1379,7 +1379,7 @@ static int g2d_probe(struct platform_device *pdev)
         struct exynos_drm_subdrv *subdrv;
         int ret;
 
-        g2d = devm_kzalloc(&pdev->dev, sizeof(*g2d), GFP_KERNEL);
+        g2d = devm_kzalloc(dev, sizeof(*g2d), GFP_KERNEL);
         if (!g2d) {
                 dev_err(dev, "failed to allocate driver data\n");
                 return -ENOMEM;
@@ -1417,7 +1417,7 @@ static int g2d_probe(struct platform_device *pdev)
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 
-        g2d->regs = devm_ioremap_resource(&pdev->dev, res);
+        g2d->regs = devm_ioremap_resource(dev, res);
         if (IS_ERR(g2d->regs)) {
                 ret = PTR_ERR(g2d->regs);
                 goto err_put_clk;
@@ -1430,7 +1430,7 @@ static int g2d_probe(struct platform_device *pdev)
                 goto err_put_clk;
         }
 
-        ret = devm_request_irq(&pdev->dev, g2d->irq, g2d_irq_handler, 0,
+        ret = devm_request_irq(dev, g2d->irq, g2d_irq_handler, 0,
                                                                 "drm_g2d", g2d);
         if (ret < 0) {
                 dev_err(dev, "irq request failed\n");
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c b/drivers/gpu/drm/exynos/exynos_drm_gsc.c
index 7841c3b8a20e..762f40d548b7 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gsc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.c
@@ -1704,7 +1704,7 @@ static int gsc_probe(struct platform_device *pdev)
         }
 
         ctx->irq = res->start;
-        ret = request_threaded_irq(ctx->irq, NULL, gsc_irq_handler,
+        ret = devm_request_threaded_irq(dev, ctx->irq, NULL, gsc_irq_handler,
                 IRQF_ONESHOT, "drm_gsc", ctx);
         if (ret < 0) {
                 dev_err(dev, "failed to request irq.\n");
@@ -1725,7 +1725,7 @@ static int gsc_probe(struct platform_device *pdev)
         ret = gsc_init_prop_list(ippdrv);
         if (ret < 0) {
                 dev_err(dev, "failed to init property list.\n");
-                goto err_get_irq;
+                return ret;
         }
 
         DRM_DEBUG_KMS("%s:id[%d]ippdrv[0x%x]\n", __func__, ctx->id,
@@ -1743,15 +1743,12 @@ static int gsc_probe(struct platform_device *pdev)
                 goto err_ippdrv_register;
         }
 
-        dev_info(&pdev->dev, "drm gsc registered successfully.\n");
+        dev_info(dev, "drm gsc registered successfully.\n");
 
         return 0;
 
 err_ippdrv_register:
-        devm_kfree(dev, ippdrv->prop_list);
         pm_runtime_disable(dev);
-err_get_irq:
-        free_irq(ctx->irq, ctx);
         return ret;
 }
 
@@ -1761,15 +1758,12 @@ static int gsc_remove(struct platform_device *pdev)
         struct gsc_context *ctx = get_gsc_context(dev);
         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 
-        devm_kfree(dev, ippdrv->prop_list);
         exynos_drm_ippdrv_unregister(ippdrv);
         mutex_destroy(&ctx->lock);
 
         pm_runtime_set_suspended(dev);
         pm_runtime_disable(dev);
 
-        free_irq(ctx->irq, ctx);
-
         return 0;
 }
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_hdmi.c b/drivers/gpu/drm/exynos/exynos_drm_hdmi.c
index ba2f0f1aa05f..437fb947e46d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_hdmi.c
@@ -442,7 +442,7 @@ static int exynos_drm_hdmi_probe(struct platform_device *pdev)
 
         DRM_DEBUG_KMS("%s\n", __FILE__);
 
-        ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
+        ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
         if (!ctx) {
                 DRM_LOG_KMS("failed to alloc common hdmi context.\n");
                 return -ENOMEM;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.c b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
index 29d2ad314490..be1e88463466 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_ipp.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
@@ -222,7 +222,7 @@ static struct exynos_drm_ippdrv *ipp_find_driver(struct ipp_context *ctx,
                 /* find ipp driver using idr */
                 ippdrv = ipp_find_obj(&ctx->ipp_idr, &ctx->ipp_lock,
                         ipp_id);
-                if (IS_ERR_OR_NULL(ippdrv)) {
+                if (IS_ERR(ippdrv)) {
                         DRM_ERROR("not found ipp%d driver.\n", ipp_id);
                         return ippdrv;
                 }
@@ -388,7 +388,7 @@ static int ipp_find_and_set_property(struct drm_exynos_ipp_property *property)
         DRM_DEBUG_KMS("%s:prop_id[%d]\n", __func__, prop_id);
 
         ippdrv = ipp_find_drv_by_handle(prop_id);
-        if (IS_ERR_OR_NULL(ippdrv)) {
+        if (IS_ERR(ippdrv)) {
                 DRM_ERROR("failed to get ipp driver.\n");
                 return -EINVAL;
         }
@@ -492,7 +492,7 @@ int exynos_drm_ipp_set_property(struct drm_device *drm_dev, void *data,
 
         /* find ipp driver using ipp id */
         ippdrv = ipp_find_driver(ctx, property);
-        if (IS_ERR_OR_NULL(ippdrv)) {
+        if (IS_ERR(ippdrv)) {
                 DRM_ERROR("failed to get ipp driver.\n");
                 return -EINVAL;
         }
@@ -521,19 +521,19 @@ int exynos_drm_ipp_set_property(struct drm_device *drm_dev, void *data,
         c_node->state = IPP_STATE_IDLE;
 
         c_node->start_work = ipp_create_cmd_work();
-        if (IS_ERR_OR_NULL(c_node->start_work)) {
+        if (IS_ERR(c_node->start_work)) {
                 DRM_ERROR("failed to create start work.\n");
                 goto err_clear;
         }
 
         c_node->stop_work = ipp_create_cmd_work();
-        if (IS_ERR_OR_NULL(c_node->stop_work)) {
+        if (IS_ERR(c_node->stop_work)) {
                 DRM_ERROR("failed to create stop work.\n");
                 goto err_free_start;
         }
 
         c_node->event_work = ipp_create_event_work();
-        if (IS_ERR_OR_NULL(c_node->event_work)) {
+        if (IS_ERR(c_node->event_work)) {
                 DRM_ERROR("failed to create event work.\n");
                 goto err_free_stop;
         }
@@ -915,7 +915,7 @@ static int ipp_queue_buf_with_run(struct device *dev,
         DRM_DEBUG_KMS("%s\n", __func__);
 
         ippdrv = ipp_find_drv_by_handle(qbuf->prop_id);
-        if (IS_ERR_OR_NULL(ippdrv)) {
+        if (IS_ERR(ippdrv)) {
                 DRM_ERROR("failed to get ipp driver.\n");
                 return -EFAULT;
         }
@@ -1909,7 +1909,7 @@ static int ipp_probe(struct platform_device *pdev)
         struct exynos_drm_subdrv *subdrv;
         int ret;
 
-        ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
+        ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
         if (!ctx)
                 return -ENOMEM;
 
@@ -1963,7 +1963,7 @@ static int ipp_probe(struct platform_device *pdev)
                 goto err_cmd_workq;
         }
 
-        dev_info(&pdev->dev, "drm ipp registered successfully.\n");
+        dev_info(dev, "drm ipp registered successfully.\n");
 
         return 0;
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_rotator.c b/drivers/gpu/drm/exynos/exynos_drm_rotator.c
index 947f09f15ad1..9b6c70964d71 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_rotator.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_rotator.c
@@ -666,8 +666,8 @@ static int rotator_probe(struct platform_device *pdev)
                 return rot->irq;
         }
 
-        ret = request_threaded_irq(rot->irq, NULL, rotator_irq_handler,
-                        IRQF_ONESHOT, "drm_rotator", rot);
+        ret = devm_request_threaded_irq(dev, rot->irq, NULL,
+                        rotator_irq_handler, IRQF_ONESHOT, "drm_rotator", rot);
         if (ret < 0) {
                 dev_err(dev, "failed to request irq\n");
                 return ret;
@@ -676,8 +676,7 @@ static int rotator_probe(struct platform_device *pdev)
         rot->clock = devm_clk_get(dev, "rotator");
         if (IS_ERR(rot->clock)) {
                 dev_err(dev, "failed to get clock\n");
-                ret = PTR_ERR(rot->clock);
-                goto err_clk_get;
+                return PTR_ERR(rot->clock);
         }
 
         pm_runtime_enable(dev);
@@ -709,10 +708,7 @@ static int rotator_probe(struct platform_device *pdev)
         return 0;
 
 err_ippdrv_register:
-        devm_kfree(dev, ippdrv->prop_list);
         pm_runtime_disable(dev);
-err_clk_get:
-        free_irq(rot->irq, rot);
         return ret;
 }
 
@@ -722,13 +718,10 @@ static int rotator_remove(struct platform_device *pdev)
         struct rot_context *rot = dev_get_drvdata(dev);
         struct exynos_drm_ippdrv *ippdrv = &rot->ippdrv;
 
-        devm_kfree(dev, ippdrv->prop_list);
         exynos_drm_ippdrv_unregister(ippdrv);
 
         pm_runtime_disable(dev);
 
-        free_irq(rot->irq, rot);
-
         return 0;
 }
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
index 9504b0cd825a..24376c194a5e 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
@@ -594,7 +594,7 @@ static int vidi_probe(struct platform_device *pdev)
 
         DRM_DEBUG_KMS("%s\n", __FILE__);
 
-        ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
+        ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
         if (!ctx)
                 return -ENOMEM;
 
@@ -612,7 +612,7 @@ static int vidi_probe(struct platform_device *pdev)
 
         platform_set_drvdata(pdev, ctx);
 
-        ret = device_create_file(&pdev->dev, &dev_attr_connection);
+        ret = device_create_file(dev, &dev_attr_connection);
         if (ret < 0)
                 DRM_INFO("failed to create connection sysfs.\n");
 
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 6652597586a1..fd1426dca882 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -1946,14 +1946,14 @@ static int hdmi_probe(struct platform_device *pdev)
 
         DRM_DEBUG_KMS("[%d]\n", __LINE__);
 
-        if (pdev->dev.of_node) {
+        if (dev->of_node) {
                 pdata = drm_hdmi_dt_parse_pdata(dev);
                 if (IS_ERR(pdata)) {
                         DRM_ERROR("failed to parse dt\n");
                         return PTR_ERR(pdata);
                 }
         } else {
-                pdata = pdev->dev.platform_data;
+                pdata = dev->platform_data;
         }
 
         if (!pdata) {
@@ -1961,14 +1961,14 @@ static int hdmi_probe(struct platform_device *pdev)
                 return -EINVAL;
         }
 
-        drm_hdmi_ctx = devm_kzalloc(&pdev->dev, sizeof(*drm_hdmi_ctx),
+        drm_hdmi_ctx = devm_kzalloc(dev, sizeof(*drm_hdmi_ctx),
                                                                 GFP_KERNEL);
         if (!drm_hdmi_ctx) {
                 DRM_ERROR("failed to allocate common hdmi context.\n");
                 return -ENOMEM;
         }
 
-        hdata = devm_kzalloc(&pdev->dev, sizeof(struct hdmi_context),
+        hdata = devm_kzalloc(dev, sizeof(struct hdmi_context),
                                                                 GFP_KERNEL);
         if (!hdata) {
                 DRM_ERROR("out of memory\n");
@@ -1985,7 +1985,7 @@ static int hdmi_probe(struct platform_device *pdev)
         if (dev->of_node) {
                 const struct of_device_id *match;
                 match = of_match_node(of_match_ptr(hdmi_match_types),
-                                        pdev->dev.of_node);
+                                        dev->of_node);
                 if (match == NULL)
                         return -ENODEV;
                 hdata->type = (enum hdmi_type)match->data;
@@ -2005,11 +2005,11 @@ static int hdmi_probe(struct platform_device *pdev)
         }
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        hdata->regs = devm_ioremap_resource(&pdev->dev, res);
+        hdata->regs = devm_ioremap_resource(dev, res);
         if (IS_ERR(hdata->regs))
                 return PTR_ERR(hdata->regs);
 
-        ret = devm_gpio_request(&pdev->dev, hdata->hpd_gpio, "HPD");
+        ret = devm_gpio_request(dev, hdata->hpd_gpio, "HPD");
         if (ret) {
                 DRM_ERROR("failed to request HPD gpio\n");
                 return ret;
@@ -2041,7 +2041,7 @@ static int hdmi_probe(struct platform_device *pdev)
 
         hdata->hpd = gpio_get_value(hdata->hpd_gpio);
 
-        ret = request_threaded_irq(hdata->irq, NULL,
+        ret = devm_request_threaded_irq(dev, hdata->irq, NULL,
                         hdmi_irq_thread, IRQF_TRIGGER_RISING |
                         IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
                         "hdmi", drm_hdmi_ctx);
@@ -2070,16 +2070,11 @@ err_ddc:
 static int hdmi_remove(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
-        struct exynos_drm_hdmi_context *ctx = platform_get_drvdata(pdev);
-        struct hdmi_context *hdata = ctx->ctx;
 
         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
 
         pm_runtime_disable(dev);
 
-        free_irq(hdata->irq, hdata);
-
-
         /* hdmiphy i2c driver */
         i2c_del_driver(&hdmiphy_driver);
         /* DDC i2c driver */
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index ec3e376b7e01..7c197d3820c5 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -1061,7 +1061,7 @@ static int mixer_resources_init(struct exynos_drm_hdmi_context *ctx,
                 return -ENXIO;
         }
 
-        mixer_res->mixer_regs = devm_ioremap(&pdev->dev, res->start,
+        mixer_res->mixer_regs = devm_ioremap(dev, res->start,
                                                         resource_size(res));
         if (mixer_res->mixer_regs == NULL) {
                 dev_err(dev, "register mapping failed.\n");
@@ -1074,7 +1074,7 @@ static int mixer_resources_init(struct exynos_drm_hdmi_context *ctx,
                 return -ENXIO;
         }
 
-        ret = devm_request_irq(&pdev->dev, res->start, mixer_irq_handler,
+        ret = devm_request_irq(dev, res->start, mixer_irq_handler,
                                                         0, "drm_mixer", ctx);
         if (ret) {
                 dev_err(dev, "request interrupt failed.\n");
@@ -1118,7 +1118,7 @@ static int vp_resources_init(struct exynos_drm_hdmi_context *ctx,
                 return -ENXIO;
         }
 
-        mixer_res->vp_regs = devm_ioremap(&pdev->dev, res->start,
+        mixer_res->vp_regs = devm_ioremap(dev, res->start,
                                                         resource_size(res));
         if (mixer_res->vp_regs == NULL) {
                 dev_err(dev, "register mapping failed.\n");
@@ -1169,14 +1169,14 @@ static int mixer_probe(struct platform_device *pdev)
 
         dev_info(dev, "probe start\n");
 
-        drm_hdmi_ctx = devm_kzalloc(&pdev->dev, sizeof(*drm_hdmi_ctx),
+        drm_hdmi_ctx = devm_kzalloc(dev, sizeof(*drm_hdmi_ctx),
                                                                 GFP_KERNEL);
         if (!drm_hdmi_ctx) {
                 DRM_ERROR("failed to allocate common hdmi context.\n");
                 return -ENOMEM;
         }
 
-        ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
+        ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
         if (!ctx) {
                 DRM_ERROR("failed to alloc mixer context.\n");
                 return -ENOMEM;
@@ -1187,14 +1187,14 @@ static int mixer_probe(struct platform_device *pdev)
         if (dev->of_node) {
                 const struct of_device_id *match;
                 match = of_match_node(of_match_ptr(mixer_match_types),
-                                                          pdev->dev.of_node);
+                                                          dev->of_node);
                 drv = (struct mixer_drv_data *)match->data;
         } else {
                 drv = (struct mixer_drv_data *)
                         platform_get_device_id(pdev)->driver_data;
         }
 
-        ctx->dev = &pdev->dev;
+        ctx->dev = dev;
         ctx->parent_ctx = (void *)drm_hdmi_ctx;
         drm_hdmi_ctx->ctx = (void *)ctx;
         ctx->vp_enabled = drv->is_vp_enabled;
diff --git a/drivers/gpu/drm/gma500/cdv_intel_display.c b/drivers/gpu/drm/gma500/cdv_intel_display.c
index 3cfd0931fbfb..82430ad8ba62 100644
--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
@@ -1462,7 +1462,7 @@ static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc,
         size_t addr = 0;
         struct gtt_range *gt;
         struct drm_gem_object *obj;
-        int ret;
+        int ret = 0;
 
         /* if we want to turn of the cursor ignore width and height */
         if (!handle) {
@@ -1499,7 +1499,8 @@ static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc,
 
         if (obj->size < width * height * 4) {
                 dev_dbg(dev->dev, "buffer is to small\n");
-                return -ENOMEM;
+                ret = -ENOMEM;
+                goto unref_cursor;
         }
 
         gt = container_of(obj, struct gtt_range, gem);
@@ -1508,7 +1509,7 @@ static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc,
         ret = psb_gtt_pin(gt);
         if (ret) {
                 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
-                return ret;
+                goto unref_cursor;
         }
 
         addr = gt->offset;      /* Or resource.start ??? */
@@ -1532,9 +1533,14 @@ static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc,
                                                         struct gtt_range, gem);
                 psb_gtt_unpin(gt);
                 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
-                psb_intel_crtc->cursor_obj = obj;
         }
-        return 0;
+
+        psb_intel_crtc->cursor_obj = obj;
+        return ret;
+
+unref_cursor:
+        drm_gem_object_unreference(obj);
+        return ret;
 }
 
 static int cdv_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
@@ -1750,6 +1756,19 @@ static void cdv_intel_crtc_destroy(struct drm_crtc *crtc)
         kfree(psb_intel_crtc);
 }
 
+static void cdv_intel_crtc_disable(struct drm_crtc *crtc)
+{
+        struct gtt_range *gt;
+        struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+
+        crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
+
+        if (crtc->fb) {
+                gt = to_psb_fb(crtc->fb)->gtt;
+                psb_gtt_unpin(gt);
+        }
+}
+
 const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
         .dpms = cdv_intel_crtc_dpms,
         .mode_fixup = cdv_intel_crtc_mode_fixup,
@@ -1757,6 +1776,7 @@ const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
         .mode_set_base = cdv_intel_pipe_set_base,
         .prepare = cdv_intel_crtc_prepare,
         .commit = cdv_intel_crtc_commit,
+        .disable = cdv_intel_crtc_disable,
 };
 
 const struct drm_crtc_funcs cdv_intel_crtc_funcs = {
diff --git a/drivers/gpu/drm/gma500/framebuffer.c b/drivers/gpu/drm/gma500/framebuffer.c
index 1534e220097a..8b1b6d923abe 100644
--- a/drivers/gpu/drm/gma500/framebuffer.c
+++ b/drivers/gpu/drm/gma500/framebuffer.c
@@ -121,8 +121,8 @@ static int psbfb_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
         unsigned long address;
         int ret;
         unsigned long pfn;
-        /* FIXME: assumes fb at stolen base which may not be true */
-        unsigned long phys_addr = (unsigned long)dev_priv->stolen_base;
+        unsigned long phys_addr = (unsigned long)dev_priv->stolen_base +
+                                  psbfb->gtt->offset;
 
         page_num = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
         address = (unsigned long)vmf->virtual_address - (vmf->pgoff << PAGE_SHIFT);
diff --git a/drivers/gpu/drm/gma500/psb_intel_display.c b/drivers/gpu/drm/gma500/psb_intel_display.c
index 6e8f42b61ff6..6666493789d1 100644
--- a/drivers/gpu/drm/gma500/psb_intel_display.c
+++ b/drivers/gpu/drm/gma500/psb_intel_display.c
@@ -843,7 +843,7 @@ static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc,
         struct gtt_range *cursor_gt = psb_intel_crtc->cursor_gt;
         struct drm_gem_object *obj;
         void *tmp_dst, *tmp_src;
-        int ret, i, cursor_pages;
+        int ret = 0, i, cursor_pages;
 
         /* if we want to turn of the cursor ignore width and height */
         if (!handle) {
@@ -880,7 +880,8 @@ static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc,
 
         if (obj->size < width * height * 4) {
                 dev_dbg(dev->dev, "buffer is to small\n");
-                return -ENOMEM;
+                ret = -ENOMEM;
+                goto unref_cursor;
         }
 
         gt = container_of(obj, struct gtt_range, gem);
@@ -889,13 +890,14 @@ static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc,
         ret = psb_gtt_pin(gt);
         if (ret) {
                 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
-                return ret;
+                goto unref_cursor;
         }
 
         if (dev_priv->ops->cursor_needs_phys) {
                 if (cursor_gt == NULL) {
                         dev_err(dev->dev, "No hardware cursor mem available");
-                        return -ENOMEM;
+                        ret = -ENOMEM;
+                        goto unref_cursor;
                 }
 
                 /* Prevent overflow */
@@ -936,9 +938,14 @@ static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc,
                                                         struct gtt_range, gem);
                 psb_gtt_unpin(gt);
                 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
-                psb_intel_crtc->cursor_obj = obj;
         }
-        return 0;
+
+        psb_intel_crtc->cursor_obj = obj;
+        return ret;
+
+unref_cursor:
+        drm_gem_object_unreference(obj);
+        return ret;
 }
 
 static int psb_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
@@ -1150,6 +1157,19 @@ static void psb_intel_crtc_destroy(struct drm_crtc *crtc)
         kfree(psb_intel_crtc);
 }
 
+static void psb_intel_crtc_disable(struct drm_crtc *crtc)
+{
+        struct gtt_range *gt;
+        struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+
+        crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
+
+        if (crtc->fb) {
+                gt = to_psb_fb(crtc->fb)->gtt;
+                psb_gtt_unpin(gt);
+        }
+}
+
 const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
         .dpms = psb_intel_crtc_dpms,
         .mode_fixup = psb_intel_crtc_mode_fixup,
@@ -1157,6 +1177,7 @@ const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
         .mode_set_base = psb_intel_pipe_set_base,
         .prepare = psb_intel_crtc_prepare,
         .commit = psb_intel_crtc_commit,
+        .disable = psb_intel_crtc_disable,
 };
 
 const struct drm_crtc_funcs psb_intel_crtc_funcs = {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9ebe895c17d6..a2e4953b8e8d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -364,40 +364,64 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
-        INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
+        INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT3 desktop */
         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
-        INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
+        INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT3 server */
         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
         INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
+        INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info), /* GT1 reserved */
+        INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info), /* GT2 reserved */
+        INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info), /* GT3 reserved */
+        INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info), /* GT1 reserved */
+        INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info), /* GT2 reserved */
+        INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info), /* GT3 reserved */
         INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
         INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
-        INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
+        INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT3 desktop */
         INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
         INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
-        INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
+        INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT3 server */
         INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
         INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
-        INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
+        INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT3 mobile */
+        INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info), /* SDV GT1 reserved */
+        INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info), /* SDV GT2 reserved */
+        INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info), /* SDV GT3 reserved */
+        INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info), /* SDV GT1 reserved */
+        INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info), /* SDV GT2 reserved */
+        INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info), /* SDV GT3 reserved */
         INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
         INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
-        INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
+        INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT3 desktop */
         INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
         INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
-        INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
+        INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT3 server */
         INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
         INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
-        INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
+        INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT3 mobile */
+        INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info), /* ULT GT1 reserved */
+        INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info), /* ULT GT2 reserved */
+        INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info), /* ULT GT3 reserved */
+        INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info), /* ULT GT1 reserved */
+        INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info), /* ULT GT2 reserved */
+        INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info), /* ULT GT3 reserved */
         INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
         INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
-        INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
+        INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT3 desktop */
         INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
         INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
-        INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
+        INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT3 server */
         INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
         INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
-        INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
+        INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT3 mobile */
+        INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info), /* CRW GT1 reserved */
+        INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info), /* CRW GT2 reserved */
+        INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info), /* CRW GT3 reserved */
+        INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info), /* CRW GT1 reserved */
+        INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info), /* CRW GT2 reserved */
+        INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info), /* CRW GT3 reserved */
         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
         INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
         INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d5dcf7fe1ee9..b9d00dcf9a2d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1943,4 +1943,19 @@ static inline void __user *to_user_ptr(u64 address)
         return (void __user *)(uintptr_t)address;
 }
 
+static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
+{
+        unsigned long j = msecs_to_jiffies(m);
+
+        return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
+}
+
+static inline unsigned long
+timespec_to_jiffies_timeout(const struct timespec *value)
+{
+        unsigned long j = timespec_to_jiffies(value);
+
+        return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
+}
+
 #endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6165535d15f0..970ad17c99ab 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -91,14 +91,11 @@ i915_gem_wait_for_error(struct i915_gpu_error *error)
 {
         int ret;
 
-#define EXIT_COND (!i915_reset_in_progress(error))
+#define EXIT_COND (!i915_reset_in_progress(error) || \
+                   i915_terminally_wedged(error))
         if (EXIT_COND)
                 return 0;
 
-        /* GPU is already declared terminally dead, give up. */
-        if (i915_terminally_wedged(error))
-                return -EIO;
-
         /*
          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
          * userspace. If it takes that long something really bad is going on and
@@ -1003,7 +1000,7 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
                 wait_forever = false;
         }
 
-        timeout_jiffies = timespec_to_jiffies(&wait_time);
+        timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
 
         if (WARN_ON(!ring->irq_get(ring)))
                 return -ENODEV;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index efe829919755..56746dcac40f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7937,6 +7937,11 @@ intel_modeset_check_state(struct drm_device *dev)
                 memset(&pipe_config, 0, sizeof(pipe_config));
                 active = dev_priv->display.get_pipe_config(crtc,
                                                            &pipe_config);
+
+                /* hw state is inconsistent with the pipe A quirk */
+                if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
+                        active = crtc->active;
+
                 WARN(crtc->active != active,
                      "crtc active state doesn't match with hw state "
                      "(expected %i, found %i)\n", crtc->active, active);
@@ -8140,6 +8145,21 @@ static void intel_set_config_restore_state(struct drm_device *dev,
         }
 }
 
+static bool
+is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
+                      int num_connectors)
+{
+        int i;
+
+        for (i = 0; i < num_connectors; i++)
+                if (connectors[i].encoder &&
+                    connectors[i].encoder->crtc == crtc &&
+                    connectors[i].dpms != DRM_MODE_DPMS_ON)
+                        return true;
+
+        return false;
+}
+
 static void
 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
                                       struct intel_set_config *config)
@@ -8147,7 +8167,11 @@ intel_set_config_compute_mode_changes(struct drm_mode_set *set,
 
         /* We should be able to check here if the fb has the same properties
          * and then just flip_or_move it */
-        if (set->crtc->fb != set->fb) {
+        if (set->connectors != NULL &&
+            is_crtc_connector_off(set->crtc, *set->connectors,
+                                  set->num_connectors)) {
+                        config->mode_changed = true;
+        } else if (set->crtc->fb != set->fb) {
                 /* If we have no fb then treat it as a full mode set */
                 if (set->crtc->fb == NULL) {
                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
@@ -8157,8 +8181,9 @@ intel_set_config_compute_mode_changes(struct drm_mode_set *set,
                 } else if (set->fb->pixel_format !=
                            set->crtc->fb->pixel_format) {
                         config->mode_changed = true;
-                } else
+                } else {
                         config->fb_changed = true;
+                }
         }
 
         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
@@ -8332,11 +8357,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
 
                 ret = intel_set_mode(set->crtc, set->mode,
                                      set->x, set->y, set->fb);
-                if (ret) {
-                        DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
-                                  set->crtc->base.id, ret);
-                        goto fail;
-                }
         } else if (config->fb_changed) {
                 intel_crtc_wait_for_pending_flips(set->crtc);
 
@@ -8344,18 +8364,18 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
                                           set->x, set->y, set->fb);
         }
 
-        intel_set_config_free(config);
-
-        return 0;
-
+        if (ret) {
+                DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
+                          set->crtc->base.id, ret);
 fail:
-        intel_set_config_restore_state(dev, config);
+                intel_set_config_restore_state(dev, config);
 
-        /* Try to restore the config */
-        if (config->mode_changed &&
-            intel_set_mode(save_set.crtc, save_set.mode,
-                           save_set.x, save_set.y, save_set.fb))
-                DRM_ERROR("failed to restore config after modeset failure\n");
+                /* Try to restore the config */
+                if (config->mode_changed &&
+                    intel_set_mode(save_set.crtc, save_set.mode,
+                                   save_set.x, save_set.y, save_set.fb))
+                        DRM_ERROR("failed to restore config after modeset failure\n");
+        }
 
 out_config:
         intel_set_config_free(config);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3d704b706a8d..70789b1b5642 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -303,7 +303,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
         if (has_aux_irq)
                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
-                                          msecs_to_jiffies(10));
+                                          msecs_to_jiffies_timeout(10));
         else
                 done = wait_for_atomic(C, 10) == 0;
         if (!done)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 5d245031e391..639fe192997c 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -228,7 +228,7 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
          * need to wake up periodically and check that ourselves. */
         I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
 
-        for (i = 0; i < msecs_to_jiffies(50) + 1; i++) {
+        for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
                 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
                                 TASK_UNINTERRUPTIBLE);
 
@@ -263,7 +263,8 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
         /* Important: The hw handles only the first bit, so set only one! */
         I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
 
-        ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10);
+        ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
+                                 msecs_to_jiffies_timeout(10));
 
         I915_WRITE(GMBUS4 + reg_offset, 0);
 
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index f36f1baabd5a..29412cc89c7a 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -815,10 +815,10 @@ static const struct dmi_system_id intel_no_lvds[] = {
         },
         {
                 .callback = intel_no_lvds_dmi_callback,
-                .ident = "Hewlett-Packard HP t5740e Thin Client",
+                .ident = "Hewlett-Packard HP t5740",
                 .matches = {
                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"),
+                        DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
                 },
         },
         {
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index d15428404b9a..d4ea6c265ce1 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1776,11 +1776,14 @@ static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
          * Assume that the preferred modes are
          * arranged in priority order.
          */
-        intel_ddc_get_modes(connector, intel_sdvo->i2c);
-        if (list_empty(&connector->probed_modes) == false)
-                goto end;
+        intel_ddc_get_modes(connector, &intel_sdvo->ddc);
 
-        /* Fetch modes from VBT */
+        /*
+         * Fetch modes from VBT. For SDVO prefer the VBT mode since some
+         * SDVO->LVDS transcoders can't cope with the EDID mode. Since
+         * drm_mode_probed_add adds the mode at the head of the list we add it
+         * last.
+         */
         if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
                 newmode = drm_mode_duplicate(connector->dev,
                                              dev_priv->sdvo_lvds_vbt_mode);
@@ -1792,7 +1795,6 @@ static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
                 }
         }
 
-end:
         list_for_each_entry(newmode, &connector->probed_modes, head) {
                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
                         intel_sdvo->sdvo_lvds_fixed_mode =
@@ -2790,12 +2792,6 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
                         SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
         }
 
-        /* Only enable the hotplug irq if we need it, to work around noisy
-         * hotplug lines.
-         */
-        if (intel_sdvo->hotplug_active)
-                intel_encoder->hpd_pin = HPD_SDVO_B ? HPD_SDVO_B : HPD_SDVO_C;
-
         intel_encoder->compute_config = intel_sdvo_compute_config;
         intel_encoder->disable = intel_disable_sdvo;
         intel_encoder->mode_set = intel_sdvo_mode_set;
@@ -2814,6 +2810,14 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
                 goto err_output;
         }
 
+        /* Only enable the hotplug irq if we need it, to work around noisy
+         * hotplug lines.
+         */
+        if (intel_sdvo->hotplug_active) {
+                intel_encoder->hpd_pin =
+                        intel_sdvo->is_sdvob ?  HPD_SDVO_B : HPD_SDVO_C;
+        }
+
         /*
          * Cloning SDVO with anything is often impossible, since the SDVO
          * encoder can request a special input timing mode. And even if that's
diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c b/drivers/gpu/drm/mgag200/mgag200_mode.c
index 77b8a45fb10a..ee66badc8bb6 100644
--- a/drivers/gpu/drm/mgag200/mgag200_mode.c
+++ b/drivers/gpu/drm/mgag200/mgag200_mode.c
@@ -1034,13 +1034,14 @@ static int mga_crtc_mode_set(struct drm_crtc *crtc,
                         else
                                 hi_pri_lvl = 5;
 
-                        WREG8(0x1fde, 0x06);
-                        WREG8(0x1fdf, hi_pri_lvl);
+                        WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
+                        WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl);
                 } else {
+                        WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
                         if (mdev->reg_1e24 >= 0x01)
-                                WREG8(0x1fdf, 0x03);
+                                WREG8(MGAREG_CRTCEXT_DATA, 0x03);
                         else
-                                WREG8(0x1fdf, 0x04);
+                                WREG8(MGAREG_CRTCEXT_DATA, 0x04);
                 }
         }
         return 0;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
index d0817d94454c..f02fd9f443ff 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
@@ -50,11 +50,16 @@ nv50_dac_sense(struct nv50_disp_priv *priv, int or, u32 loadval)
 {
         const u32 doff = (or * 0x800);
         int load = -EINVAL;
+        nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80150000);
+        nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
         nv_wr32(priv, 0x61a00c + doff, 0x00100000 | loadval);
-        udelay(9500);
+        mdelay(9);
+        udelay(500);
         nv_wr32(priv, 0x61a00c + doff, 0x80000000);
         load = (nv_rd32(priv, 0x61a00c + doff) & 0x38000000) >> 27;
         nv_wr32(priv, 0x61a00c + doff, 0x00000000);
+        nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80550000);
+        nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
         return load;
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c
index 0d36bdc51417..7fdade6e604d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c
@@ -55,6 +55,10 @@ nv84_hdmi_ctrl(struct nv50_disp_priv *priv, int head, int or, u32 data)
         nv_wr32(priv, 0x616510 + hoff, 0x00000000);
         nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000001);
 
+        nv_mask(priv, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
+        nv_mask(priv, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
+        nv_mask(priv, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
+
         /* ??? */
         nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
         nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
index 89bf459d584b..e9b8217d0075 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
@@ -40,14 +40,13 @@
  * FIFO channel objects
  ******************************************************************************/
 
-void
-nv50_fifo_playlist_update(struct nv50_fifo_priv *priv)
+static void
+nv50_fifo_playlist_update_locked(struct nv50_fifo_priv *priv)
 {
         struct nouveau_bar *bar = nouveau_bar(priv);
         struct nouveau_gpuobj *cur;
         int i, p;
 
-        mutex_lock(&nv_subdev(priv)->mutex);
         cur = priv->playlist[priv->cur_playlist];
         priv->cur_playlist = !priv->cur_playlist;
 
@@ -61,6 +60,13 @@ nv50_fifo_playlist_update(struct nv50_fifo_priv *priv)
         nv_wr32(priv, 0x0032f4, cur->addr >> 12);
         nv_wr32(priv, 0x0032ec, p);
         nv_wr32(priv, 0x002500, 0x00000101);
+}
+
+void
+nv50_fifo_playlist_update(struct nv50_fifo_priv *priv)
+{
+        mutex_lock(&nv_subdev(priv)->mutex);
+        nv50_fifo_playlist_update_locked(priv);
         mutex_unlock(&nv_subdev(priv)->mutex);
 }
 
@@ -489,7 +495,7 @@ nv50_fifo_init(struct nouveau_object *object)
 
         for (i = 0; i < 128; i++)
                 nv_wr32(priv, 0x002600 + (i * 4), 0x00000000);
-        nv50_fifo_playlist_update(priv);
+        nv50_fifo_playlist_update_locked(priv);
 
         nv_wr32(priv, 0x003200, 0x00000001);
         nv_wr32(priv, 0x003250, 0x00000001);
diff --git a/drivers/gpu/drm/nouveau/core/include/core/class.h b/drivers/gpu/drm/nouveau/core/include/core/class.h
index 0a393f7f055f..5a5961b6a6a3 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/class.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/class.h
@@ -218,7 +218,7 @@ struct nv04_display_class {
 #define NV50_DISP_DAC_PWR_STATE                                      0x00000040
 #define NV50_DISP_DAC_PWR_STATE_ON                                   0x00000000
 #define NV50_DISP_DAC_PWR_STATE_OFF                                  0x00000040
-#define NV50_DISP_DAC_LOAD                                           0x0002000c
+#define NV50_DISP_DAC_LOAD                                           0x00020100
 #define NV50_DISP_DAC_LOAD_VALUE                                     0x00000007
 
 #define NV50_DISP_PIOR_MTHD                                          0x00030000
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index 7bf22d4a3d96..f17dc2ab03ec 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -638,17 +638,8 @@ nouveau_finish_page_flip(struct nouveau_channel *chan,
         }
 
         s = list_first_entry(&fctx->flip, struct nouveau_page_flip_state, head);
-        if (s->event) {
-                struct drm_pending_vblank_event *e = s->event;
-                struct timeval now;
-
-                do_gettimeofday(&now);
-                e->event.sequence = 0;
-                e->event.tv_sec = now.tv_sec;
-                e->event.tv_usec = now.tv_usec;
-                list_add_tail(&e->base.link, &e->base.file_priv->event_list);
-                wake_up_interruptible(&e->base.file_priv->event_wait);
-        }
+        if (s->event)
+                drm_send_vblank_event(dev, -1, s->event);
 
         list_del(&s->head);
         if (ps)
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index ebf0a683305e..dd5e01f89f28 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -1554,7 +1554,9 @@ nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 {
         struct nv50_disp *disp = nv50_disp(encoder->dev);
         int ret, or = nouveau_encoder(encoder)->or;
-        u32 load = 0;
+        u32 load = nouveau_drm(encoder->dev)->vbios.dactestval;
+        if (load == 0)
+                load = 340;
 
         ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load));
         if (ret || load != 7)
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c
index 9c53c25e5201..826586ffbe83 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.c
+++ b/drivers/gpu/drm/omapdrm/omap_drv.c
@@ -649,6 +649,9 @@ static void pdev_shutdown(struct platform_device *device)
 
 static int pdev_probe(struct platform_device *device)
 {
+        if (omapdss_is_initialized() == false)
+                return -EPROBE_DEFER;
+
         DBG("%s", device->name);
         return drm_platform_init(&omap_drm_driver, device);
 }
diff --git a/drivers/gpu/drm/qxl/Kconfig b/drivers/gpu/drm/qxl/Kconfig
index 2f1a57e11140..d6c12796023c 100644
--- a/drivers/gpu/drm/qxl/Kconfig
+++ b/drivers/gpu/drm/qxl/Kconfig
@@ -4,6 +4,7 @@ config DRM_QXL
         select FB_SYS_FILLRECT
         select FB_SYS_COPYAREA
         select FB_SYS_IMAGEBLIT
+        select FB_DEFERRED_IO
         select DRM_KMS_HELPER
         select DRM_TTM
         help
diff --git a/drivers/gpu/drm/qxl/qxl_ioctl.c b/drivers/gpu/drm/qxl/qxl_ioctl.c
index 6db7370373ea..a4b71b25fa53 100644
--- a/drivers/gpu/drm/qxl/qxl_ioctl.c
+++ b/drivers/gpu/drm/qxl/qxl_ioctl.c
@@ -151,7 +151,7 @@ static int qxl_execbuffer_ioctl(struct drm_device *dev, void *data,
                 struct qxl_bo *cmd_bo;
                 int release_type;
                 struct drm_qxl_command *commands =
-                        (struct drm_qxl_command *)execbuffer->commands;
+                        (struct drm_qxl_command *)(uintptr_t)execbuffer->commands;
 
                 if (DRM_COPY_FROM_USER(&user_cmd, &commands[cmd_num],
                                        sizeof(user_cmd)))
@@ -193,7 +193,7 @@ static int qxl_execbuffer_ioctl(struct drm_device *dev, void *data,
 
                 for (i = 0 ; i < user_cmd.relocs_num; ++i) {
                         if (DRM_COPY_FROM_USER(&reloc,
-                                               &((struct drm_qxl_reloc *)user_cmd.relocs)[i],
+                                               &((struct drm_qxl_reloc *)(uintptr_t)user_cmd.relocs)[i],
                                                sizeof(reloc))) {
                                 qxl_bo_list_unreserve(&reloc_list, true);
                                 qxl_release_unreserve(qdev, release);
diff --git a/drivers/gpu/drm/qxl/qxl_kms.c b/drivers/gpu/drm/qxl/qxl_kms.c
index 85127ed24cfd..e27ce2a907cf 100644
--- a/drivers/gpu/drm/qxl/qxl_kms.c
+++ b/drivers/gpu/drm/qxl/qxl_kms.c
@@ -128,12 +128,13 @@ int qxl_device_init(struct qxl_device *qdev,
 
         qdev->vram_mapping = io_mapping_create_wc(qdev->vram_base, pci_resource_len(pdev, 0));
         qdev->surface_mapping = io_mapping_create_wc(qdev->surfaceram_base, qdev->surfaceram_size);
-        DRM_DEBUG_KMS("qxl: vram %p-%p(%dM %dk), surface %p-%p(%dM %dk)\n",
-                 (void *)qdev->vram_base, (void *)pci_resource_end(pdev, 0),
+        DRM_DEBUG_KMS("qxl: vram %llx-%llx(%dM %dk), surface %llx-%llx(%dM %dk)\n",
+                 (unsigned long long)qdev->vram_base,
+                 (unsigned long long)pci_resource_end(pdev, 0),
                  (int)pci_resource_len(pdev, 0) / 1024 / 1024,
                  (int)pci_resource_len(pdev, 0) / 1024,
-                 (void *)qdev->surfaceram_base,
-                 (void *)pci_resource_end(pdev, 1),
+                 (unsigned long long)qdev->surfaceram_base,
+                 (unsigned long long)pci_resource_end(pdev, 1),
                  (int)qdev->surfaceram_size / 1024 / 1024,
                  (int)qdev->surfaceram_size / 1024);
 
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index 44a7da66e081..8406c8251fbf 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -667,6 +667,8 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
 int
 atombios_get_encoder_mode(struct drm_encoder *encoder)
 {
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
         struct drm_connector *connector;
         struct radeon_connector *radeon_connector;
@@ -693,7 +695,8 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
         case DRM_MODE_CONNECTOR_DVII:
         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
                 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
-                    radeon_audio)
+                    radeon_audio &&
+                    !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
                         return ATOM_ENCODER_MODE_HDMI;
                 else if (radeon_connector->use_digital)
                         return ATOM_ENCODER_MODE_DVI;
@@ -704,7 +707,8 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
         case DRM_MODE_CONNECTOR_HDMIA:
         default:
                 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
-                    radeon_audio)
+                    radeon_audio &&
+                    !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
                         return ATOM_ENCODER_MODE_HDMI;
                 else
                         return ATOM_ENCODER_MODE_DVI;
@@ -718,7 +722,8 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
                         return ATOM_ENCODER_MODE_DP;
                 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
-                         radeon_audio)
+                         radeon_audio &&
+                         !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
                         return ATOM_ENCODER_MODE_HDMI;
                 else
                         return ATOM_ENCODER_MODE_DVI;
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 8f9e2d31b255..0f89ce3d02b9 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -4754,6 +4754,12 @@ static int evergreen_startup(struct radeon_device *rdev)
                 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         r = r600_irq_init(rdev);
         if (r) {
                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
@@ -4923,10 +4929,6 @@ int evergreen_init(struct radeon_device *rdev)
         if (r)
                 return r;
 
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
-
         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
 
@@ -4999,8 +5001,7 @@ void evergreen_fini(struct radeon_device *rdev)
 
 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
 {
-        u32 link_width_cntl, speed_cntl, mask;
-        int ret;
+        u32 link_width_cntl, speed_cntl;
 
         if (radeon_pcie_gen2 == 0)
                 return;
@@ -5015,11 +5016,8 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
         if (ASIC_IS_X2(rdev))
                 return;
 
-        ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
-        if (ret != 0)
-                return;
-
-        if (!(mask & DRM_PCIE_SPEED_50))
+        if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
+                (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
                 return;
 
         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 7969c0c8ec20..84583302b081 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -2025,6 +2025,12 @@ static int cayman_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         r = r600_irq_init(rdev);
         if (r) {
                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
@@ -2190,10 +2196,6 @@ int cayman_init(struct radeon_device *rdev)
         if (r)
                 return r;
 
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
-
         ring->ring_obj = NULL;
         r600_ring_init(rdev, ring, 1024 * 1024);
 
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 4973bff37fec..d0314ecbd7c1 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -3869,6 +3869,12 @@ static int r100_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         r100_irq_set(rdev);
         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
@@ -4024,9 +4030,6 @@ int r100_init(struct radeon_device *rdev)
         r = radeon_fence_driver_init(rdev);
         if (r)
                 return r;
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
         /* Memory manager */
         r = radeon_bo_init(rdev);
         if (r)
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index c60350e6872d..b9b776f1e582 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -1382,6 +1382,12 @@ static int r300_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         r100_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
@@ -1516,9 +1522,6 @@ int r300_init(struct radeon_device *rdev)
         r = radeon_fence_driver_init(rdev);
         if (r)
                 return r;
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
         /* Memory manager */
         r = radeon_bo_init(rdev);
         if (r)
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 6fce2eb4dd16..4e796ecf9ea4 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -265,6 +265,12 @@ static int r420_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         r100_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
@@ -411,10 +417,6 @@ int r420_init(struct radeon_device *rdev)
         if (r) {
                 return r;
         }
-        r = radeon_irq_kms_init(rdev);
-        if (r) {
-                return r;
-        }
         /* Memory manager */
         r = radeon_bo_init(rdev);
         if (r) {
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index f795a4e092cb..e1aece73b370 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -194,6 +194,12 @@ static int r520_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         rs600_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
@@ -297,9 +303,6 @@ int r520_init(struct radeon_device *rdev)
         r = radeon_fence_driver_init(rdev);
         if (r)
                 return r;
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
         /* Memory manager */
         r = radeon_bo_init(rdev);
         if (r)
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 1a08008c978b..0e5341695922 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1046,6 +1046,24 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev)
         return -1;
 }
 
+uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
+{
+        uint32_t r;
+
+        WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
+        r = RREG32(R_0028FC_MC_DATA);
+        WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
+        return r;
+}
+
+void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
+{
+        WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
+                S_0028F8_MC_IND_WR_EN(1));
+        WREG32(R_0028FC_MC_DATA, v);
+        WREG32(R_0028F8_MC_INDEX, 0x7F);
+}
+
 static void r600_mc_program(struct radeon_device *rdev)
 {
         struct rv515_mc_save save;
@@ -1181,6 +1199,8 @@ static int r600_mc_init(struct radeon_device *rdev)
 {
         u32 tmp;
         int chansize, numchan;
+        uint32_t h_addr, l_addr;
+        unsigned long long k8_addr;
 
         /* Get VRAM informations */
         rdev->mc.vram_is_ddr = true;
@@ -1221,7 +1241,30 @@ static int r600_mc_init(struct radeon_device *rdev)
         if (rdev->flags & RADEON_IS_IGP) {
                 rs690_pm_info(rdev);
                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
+
+                if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
+                        /* Use K8 direct mapping for fast fb access. */
+                        rdev->fastfb_working = false;
+                        h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
+                        l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
+                        k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
+#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
+                        if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
+#endif
+                        {
+                                /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
+                                * memory is present.
+                                */
+                                if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
+                                        DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
+                                                (unsigned long long)rdev->mc.aper_base, k8_addr);
+                                        rdev->mc.aper_base = (resource_size_t)k8_addr;
+                                        rdev->fastfb_working = true;
+                                }
+                        }
+                }
         }
+
         radeon_update_bandwidth_info(rdev);
         return 0;
 }
@@ -3202,6 +3245,12 @@ static int r600_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         r = r600_irq_init(rdev);
         if (r) {
                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
@@ -3356,10 +3405,6 @@ int r600_init(struct radeon_device *rdev)
         if (r)
                 return r;
 
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
-
         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
 
@@ -4631,8 +4676,6 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
 {
         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
         u16 link_cntl2;
-        u32 mask;
-        int ret;
 
         if (radeon_pcie_gen2 == 0)
                 return;
@@ -4651,11 +4694,8 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
         if (rdev->family <= CHIP_R600)
                 return;
 
-        ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
-        if (ret != 0)
-                return;
-
-        if (!(mask & DRM_PCIE_SPEED_50))
+        if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
+                (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
                 return;
 
         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index acb146c06973..79df558f8c40 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -1342,6 +1342,14 @@
 #define PACKET3_STRMOUT_BASE_UPDATE                     0x72 /* r7xx */
 #define PACKET3_SURFACE_BASE_UPDATE                     0x73
 
+#define R_000011_K8_FB_LOCATION                 0x11
+#define R_000012_MC_MISC_UMA_CNTL               0x12
+#define   G_000012_K8_ADDR_EXT(x)               (((x) >> 0) & 0xFF)
+#define R_0028F8_MC_INDEX                       0x28F8
+#define         S_0028F8_MC_IND_ADDR(x)                 (((x) & 0x1FF) << 0)
+#define         C_0028F8_MC_IND_ADDR                    0xFFFFFE00
+#define         S_0028F8_MC_IND_WR_EN(x)                (((x) & 0x1) << 9)
+#define R_0028FC_MC_DATA                        0x28FC
 
 #define R_008020_GRBM_SOFT_RESET                0x8020
 #define         S_008020_SOFT_RESET_CP(x)               (((x) & 1) << 0)
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 06b8c19ab19e..a2802b47ee95 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -122,6 +122,10 @@ static void radeon_register_accessor_init(struct radeon_device *rdev)
                 rdev->mc_rreg = &rs600_mc_rreg;
                 rdev->mc_wreg = &rs600_mc_wreg;
         }
+        if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
+                rdev->mc_rreg = &rs780_mc_rreg;
+                rdev->mc_wreg = &rs780_mc_wreg;
+        }
         if (rdev->family >= CHIP_R600) {
                 rdev->pciep_rreg = &r600_pciep_rreg;
                 rdev->pciep_wreg = &r600_pciep_wreg;
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 2c87365d345f..a72759ede753 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -347,6 +347,8 @@ extern bool r600_gui_idle(struct radeon_device *rdev);
 extern void r600_pm_misc(struct radeon_device *rdev);
 extern void r600_pm_init_profile(struct radeon_device *rdev);
 extern void rs780_pm_init_profile(struct radeon_device *rdev);
+extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
+extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
 extern int r600_get_pcie_lanes(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index c2c59fb1ea01..189973836cff 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -467,23 +467,27 @@ bool radeon_card_posted(struct radeon_device *rdev)
 {
         uint32_t reg;
 
+        /* required for EFI mode on macbook2,1 which uses an r5xx asic */
         if (efi_enabled(EFI_BOOT) &&
-            rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE)
+            (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
+            (rdev->family < CHIP_R600))
                 return false;
 
+        if (ASIC_IS_NODCE(rdev))
+                goto check_memsize;
+
         /* first check CRTCs */
-        if (ASIC_IS_DCE41(rdev)) {
+        if (ASIC_IS_DCE4(rdev)) {
                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
-                if (reg & EVERGREEN_CRTC_MASTER_EN)
-                        return true;
-        } else if (ASIC_IS_DCE4(rdev)) {
-                reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
-                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
-                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
-                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
-                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
-                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
+                        if (rdev->num_crtc >= 4) {
+                                reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
+                                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
+                        }
+                        if (rdev->num_crtc >= 6) {
+                                reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
+                                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
+                        }
                 if (reg & EVERGREEN_CRTC_MASTER_EN)
                         return true;
         } else if (ASIC_IS_AVIVO(rdev)) {
@@ -500,6 +504,7 @@ bool radeon_card_posted(struct radeon_device *rdev)
                 }
         }
 
+check_memsize:
         /* then check MEM_SIZE, in case the crtcs are off */
         if (rdev->family >= CHIP_R600)
                 reg = RREG32(R600_CONFIG_MEMSIZE);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index e38fd559f1ab..eb18bb7af1cc 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -271,8 +271,6 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 {
         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
         struct radeon_unpin_work *work;
-        struct drm_pending_vblank_event *e;
-        struct timeval now;
         unsigned long flags;
         u32 update_pending;
         int vpos, hpos;
@@ -328,14 +326,9 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
         radeon_crtc->unpin_work = NULL;
 
         /* wakeup userspace */
-        if (work->event) {
-                e = work->event;
-                e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);
-                e->event.tv_sec = now.tv_sec;
-                e->event.tv_usec = now.tv_usec;
-                list_add_tail(&e->base.link, &e->base.file_priv->event_list);
-                wake_up_interruptible(&e->base.file_priv->event_wait);
-        }
+        if (work->event)
+                drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
+
         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 
         drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index 73051ce3121e..233a9b9fa1f7 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -417,6 +417,12 @@ static int rs400_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         r100_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
@@ -535,9 +541,6 @@ int rs400_init(struct radeon_device *rdev)
         r = radeon_fence_driver_init(rdev);
         if (r)
                 return r;
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
         /* Memory manager */
         r = radeon_bo_init(rdev);
         if (r)
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 46fa1b07c560..670b555d2ca2 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -923,6 +923,12 @@ static int rs600_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         rs600_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
@@ -1047,9 +1053,6 @@ int rs600_init(struct radeon_device *rdev)
         r = radeon_fence_driver_init(rdev);
         if (r)
                 return r;
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
         /* Memory manager */
         r = radeon_bo_init(rdev);
         if (r)
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index ab4c86cfd552..55880d5962c3 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -651,6 +651,12 @@ static int rs690_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         rs600_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
@@ -776,9 +782,6 @@ int rs690_init(struct radeon_device *rdev)
         r = radeon_fence_driver_init(rdev);
         if (r)
                 return r;
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
         /* Memory manager */
         r = radeon_bo_init(rdev);
         if (r)
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index ffcba730c57c..21c7d7b26e55 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -532,6 +532,12 @@ static int rv515_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         rs600_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
@@ -662,9 +668,6 @@ int rv515_init(struct radeon_device *rdev)
         r = radeon_fence_driver_init(rdev);
         if (r)
                 return r;
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
         /* Memory manager */
         r = radeon_bo_init(rdev);
         if (r)
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 83f612a9500b..4a62ad2e5399 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -862,10 +862,8 @@ int rv770_uvd_resume(struct radeon_device *rdev)
                 chip_id = 0x0100000b;
                 break;
         case CHIP_SUMO:
-                chip_id = 0x0100000c;
-                break;
         case CHIP_SUMO2:
-                chip_id = 0x0100000d;
+                chip_id = 0x0100000c;
                 break;
         case CHIP_PALM:
                 chip_id = 0x0100000e;
@@ -1889,6 +1887,12 @@ static int rv770_startup(struct radeon_device *rdev)
                 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         r = r600_irq_init(rdev);
         if (r) {
                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
@@ -2047,10 +2051,6 @@ int rv770_init(struct radeon_device *rdev)
         if (r)
                 return r;
 
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
-
         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
 
@@ -2113,8 +2113,6 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
 {
         u32 link_width_cntl, lanes, speed_cntl, tmp;
         u16 link_cntl2;
-        u32 mask;
-        int ret;
 
         if (radeon_pcie_gen2 == 0)
                 return;
@@ -2129,11 +2127,8 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
         if (ASIC_IS_X2(rdev))
                 return;
 
-        ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
-        if (ret != 0)
-                return;
-
-        if (!(mask & DRM_PCIE_SPEED_50))
+        if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
+                (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
                 return;
 
         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 5ffade69af25..a1b0da6b5808 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2616,7 +2616,7 @@ static void si_gpu_init(struct radeon_device *rdev)
         default:
                 rdev->config.si.max_shader_engines = 1;
                 rdev->config.si.max_tile_pipes = 4;
-                rdev->config.si.max_cu_per_sh = 2;
+                rdev->config.si.max_cu_per_sh = 5;
                 rdev->config.si.max_sh_per_se = 2;
                 rdev->config.si.max_backends_per_se = 4;
                 rdev->config.si.max_texture_channel_caches = 4;
@@ -5350,6 +5350,12 @@ static int si_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         r = si_irq_init(rdev);
         if (r) {
                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
@@ -5533,10 +5539,6 @@ int si_init(struct radeon_device *rdev)
         if (r)
                 return r;
 
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
-
         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
         ring->ring_obj = NULL;
         r600_ring_init(rdev, ring, 1024 * 1024);
diff --git a/drivers/gpu/drm/shmobile/shmob_drm_crtc.c b/drivers/gpu/drm/shmobile/shmob_drm_crtc.c
index 7dff49ed66e7..99e2034e49cc 100644
--- a/drivers/gpu/drm/shmobile/shmob_drm_crtc.c
+++ b/drivers/gpu/drm/shmobile/shmob_drm_crtc.c
@@ -451,27 +451,16 @@ void shmob_drm_crtc_finish_page_flip(struct shmob_drm_crtc *scrtc)
 {
         struct drm_pending_vblank_event *event;
         struct drm_device *dev = scrtc->crtc.dev;
-        struct timeval vblanktime;
         unsigned long flags;
 
         spin_lock_irqsave(&dev->event_lock, flags);
         event = scrtc->event;
         scrtc->event = NULL;
+        if (event) {
+                drm_send_vblank_event(dev, 0, event);
+                drm_vblank_put(dev, 0);
+        }
         spin_unlock_irqrestore(&dev->event_lock, flags);
-
-        if (event == NULL)
-                return;
-
-        event->event.sequence = drm_vblank_count_and_time(dev, 0, &vblanktime);
-        event->event.tv_sec = vblanktime.tv_sec;
-        event->event.tv_usec = vblanktime.tv_usec;
-
-        spin_lock_irqsave(&dev->event_lock, flags);
-        list_add_tail(&event->base.link, &event->base.file_priv->event_list);
-        wake_up_interruptible(&event->base.file_priv->event_wait);
-        spin_unlock_irqrestore(&dev->event_lock, flags);
-
-        drm_vblank_put(dev, 0);
 }
 
 static int shmob_drm_crtc_page_flip(struct drm_crtc *crtc,
diff --git a/drivers/gpu/drm/tilcdc/Kconfig b/drivers/gpu/drm/tilcdc/Kconfig
index e461e9972455..7a4d10106906 100644
--- a/drivers/gpu/drm/tilcdc/Kconfig
+++ b/drivers/gpu/drm/tilcdc/Kconfig
@@ -6,6 +6,7 @@ config DRM_TILCDC
         select DRM_GEM_CMA_HELPER
         select VIDEOMODE_HELPERS
         select BACKLIGHT_CLASS_DEVICE
+        select BACKLIGHT_LCD_SUPPORT
         help
           Choose this option if you have an TI SoC with LCDC display
           controller, for example AM33xx in beagle-bone, DA8xx, or
diff --git a/drivers/hid/hid-multitouch.c b/drivers/hid/hid-multitouch.c
index dc3ae5c56f56..d39a5cede0b0 100644
--- a/drivers/hid/hid-multitouch.c
+++ b/drivers/hid/hid-multitouch.c
@@ -264,9 +264,12 @@ static struct mt_class mt_classes[] = {
 static void mt_free_input_name(struct hid_input *hi)
 {
         struct hid_device *hdev = hi->report->device;
+        const char *name = hi->input->name;
 
-        if (hi->input->name != hdev->name)
-                kfree(hi->input->name);
+        if (name != hdev->name) {
+                hi->input->name = hdev->name;
+                kfree(name);
+        }
 }
 
 static ssize_t mt_show_quirks(struct device *dev,
@@ -1040,11 +1043,11 @@ static void mt_remove(struct hid_device *hdev)
         struct hid_input *hi;
 
         sysfs_remove_group(&hdev->dev.kobj, &mt_attribute_group);
-        hid_hw_stop(hdev);
-
         list_for_each_entry(hi, &hdev->inputs, list)
                 mt_free_input_name(hi);
 
+        hid_hw_stop(hdev);
+
         kfree(td);
         hid_set_drvdata(hdev, NULL);
 }
diff --git a/drivers/hwmon/adm1021.c b/drivers/hwmon/adm1021.c
index 7e76922a4ba9..f920619cd6da 100644
--- a/drivers/hwmon/adm1021.c
+++ b/drivers/hwmon/adm1021.c
@@ -331,26 +331,68 @@ static int adm1021_detect(struct i2c_client *client,
         man_id = i2c_smbus_read_byte_data(client, ADM1021_REG_MAN_ID);
         dev_id = i2c_smbus_read_byte_data(client, ADM1021_REG_DEV_ID);
 
+        if (man_id < 0 || dev_id < 0)
+                return -ENODEV;
+
         if (man_id == 0x4d && dev_id == 0x01)
                 type_name = "max1617a";
         else if (man_id == 0x41) {
                 if ((dev_id & 0xF0) == 0x30)
                         type_name = "adm1023";
-                else
+                else if ((dev_id & 0xF0) == 0x00)
                         type_name = "adm1021";
+                else
+                        return -ENODEV;
         } else if (man_id == 0x49)
                 type_name = "thmc10";
         else if (man_id == 0x23)
                 type_name = "gl523sm";
         else if (man_id == 0x54)
                 type_name = "mc1066";
-        /* LM84 Mfr ID in a different place, and it has more unused bits */
-        else if (conv_rate == 0x00
-                 && (config & 0x7F) == 0x00
-                 && (status & 0xAB) == 0x00)
-                type_name = "lm84";
-        else
-                type_name = "max1617";
+        else {
+                int lte, rte, lhi, rhi, llo, rlo;
+
+                /* extra checks for LM84 and MAX1617 to avoid misdetections */
+
+                llo = i2c_smbus_read_byte_data(client, ADM1021_REG_THYST_R(0));
+                rlo = i2c_smbus_read_byte_data(client, ADM1021_REG_THYST_R(1));
+
+                /* fail if any of the additional register reads failed */
+                if (llo < 0 || rlo < 0)
+                        return -ENODEV;
+
+                lte = i2c_smbus_read_byte_data(client, ADM1021_REG_TEMP(0));
+                rte = i2c_smbus_read_byte_data(client, ADM1021_REG_TEMP(1));
+                lhi = i2c_smbus_read_byte_data(client, ADM1021_REG_TOS_R(0));
+                rhi = i2c_smbus_read_byte_data(client, ADM1021_REG_TOS_R(1));
+
+                /*
+                 * Fail for negative temperatures and negative high limits.
+                 * This check also catches read errors on the tested registers.
+                 */
+                if ((s8)lte < 0 || (s8)rte < 0 || (s8)lhi < 0 || (s8)rhi < 0)
+                        return -ENODEV;
+
+                /* fail if all registers hold the same value */
+                if (lte == rte && lte == lhi && lte == rhi && lte == llo
+                    && lte == rlo)
+                        return -ENODEV;
+
+                /*
+                 * LM84 Mfr ID is in a different place,
+                 * and it has more unused bits.
+                 */
+                if (conv_rate == 0x00
+                    && (config & 0x7F) == 0x00
+                    && (status & 0xAB) == 0x00) {
+                        type_name = "lm84";
+                } else {
+                        /* fail if low limits are larger than high limits */
+                        if ((s8)llo > lhi || (s8)rlo > rhi)
+                                return -ENODEV;
+                        type_name = "max1617";
+                }
+        }
 
         pr_debug("Detected chip %s at adapter %d, address 0x%02x.\n",
                  type_name, i2c_adapter_id(adapter), client->addr);
diff --git a/drivers/i2c/busses/i2c-stu300.c b/drivers/i2c/busses/i2c-stu300.c
index 0a6f941133f6..d1a6b204af00 100644
--- a/drivers/i2c/busses/i2c-stu300.c
+++ b/drivers/i2c/busses/i2c-stu300.c
@@ -17,6 +17,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/of_i2c.h>
 
 /* the name of this kernel module */
 #define NAME "stu300"
@@ -867,7 +868,6 @@ stu300_probe(struct platform_device *pdev)
         struct resource *res;
         int bus_nr;
         int ret = 0;
-        char clk_name[] = "I2C0";
 
         dev = devm_kzalloc(&pdev->dev, sizeof(struct stu300_dev), GFP_KERNEL);
         if (!dev) {
@@ -876,8 +876,7 @@ stu300_probe(struct platform_device *pdev)
         }
 
         bus_nr = pdev->id;
-        clk_name[3] += (char)bus_nr;
-        dev->clk = devm_clk_get(&pdev->dev, clk_name);
+        dev->clk = devm_clk_get(&pdev->dev, NULL);
         if (IS_ERR(dev->clk)) {
                 dev_err(&pdev->dev, "could not retrieve i2c bus clock\n");
                 return PTR_ERR(dev->clk);
@@ -923,6 +922,7 @@ stu300_probe(struct platform_device *pdev)
         adap->nr = bus_nr;
         adap->algo = &stu300_algo;
         adap->dev.parent = &pdev->dev;
+        adap->dev.of_node = pdev->dev.of_node;
         i2c_set_adapdata(adap, dev);
 
         /* i2c device drivers may be active on return from add_adapter() */
@@ -934,6 +934,10 @@ stu300_probe(struct platform_device *pdev)
         }
 
         platform_set_drvdata(pdev, dev);
+        dev_info(&pdev->dev, "ST DDC I2C @ %p, irq %d\n",
+                 dev->virtbase, dev->irq);
+        of_i2c_register_devices(adap);
+
         return 0;
 }
 
@@ -978,11 +982,17 @@ stu300_remove(struct platform_device *pdev)
         return 0;
 }
 
+static const struct of_device_id stu300_dt_match[] = {
+        { .compatible = "st,ddci2c" },
+        {},
+};
+
 static struct platform_driver stu300_i2c_driver = {
         .driver = {
                 .name   = NAME,
                 .owner  = THIS_MODULE,
                 .pm     = STU300_I2C_PM,
+                .of_match_table = stu300_dt_match,
         },
         .remove         = __exit_p(stu300_remove),
 
diff --git a/drivers/iio/buffer_cb.c b/drivers/iio/buffer_cb.c
index 9201022945e9..9d19ba74f22b 100644
--- a/drivers/iio/buffer_cb.c
+++ b/drivers/iio/buffer_cb.c
@@ -64,7 +64,7 @@ struct iio_cb_buffer *iio_channel_get_all_cb(struct device *dev,
         while (chan->indio_dev) {
                 if (chan->indio_dev != indio_dev) {
                         ret = -EINVAL;
-                        goto error_release_channels;
+                        goto error_free_scan_mask;
                 }
                 set_bit(chan->channel->scan_index,
                         cb_buff->buffer.scan_mask);
@@ -73,6 +73,8 @@ struct iio_cb_buffer *iio_channel_get_all_cb(struct device *dev,
 
         return cb_buff;
 
+error_free_scan_mask:
+        kfree(cb_buff->buffer.scan_mask);
 error_release_channels:
         iio_channel_release_all(cb_buff->channels);
 error_free_cb_buff:
@@ -100,6 +102,7 @@ EXPORT_SYMBOL_GPL(iio_channel_stop_all_cb);
 
 void iio_channel_release_all_cb(struct iio_cb_buffer *cb_buff)
 {
+        kfree(cb_buff->buffer.scan_mask);
         iio_channel_release_all(cb_buff->channels);
         kfree(cb_buff);
 }
diff --git a/drivers/iio/frequency/adf4350.c b/drivers/iio/frequency/adf4350.c
index a884252ac66b..e76d4ace53ff 100644
--- a/drivers/iio/frequency/adf4350.c
+++ b/drivers/iio/frequency/adf4350.c
@@ -212,7 +212,7 @@ static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq)
                 (pdata->r2_user_settings & (ADF4350_REG2_PD_POLARITY_POS |
                 ADF4350_REG2_LDP_6ns | ADF4350_REG2_LDF_INT_N |
                 ADF4350_REG2_CHARGE_PUMP_CURR_uA(5000) |
-                ADF4350_REG2_MUXOUT(0x7) | ADF4350_REG2_NOISE_MODE(0x9)));
+                ADF4350_REG2_MUXOUT(0x7) | ADF4350_REG2_NOISE_MODE(0x3)));
 
         st->regs[ADF4350_REG3] = pdata->r3_user_settings &
                                  (ADF4350_REG3_12BIT_CLKDIV(0xFFF) |
diff --git a/drivers/iio/inkern.c b/drivers/iio/inkern.c
index 795d100b4c36..98ddc323add0 100644
--- a/drivers/iio/inkern.c
+++ b/drivers/iio/inkern.c
@@ -124,7 +124,7 @@ static int __of_iio_channel_get(struct iio_channel *channel,
         channel->indio_dev = indio_dev;
         index = iiospec.args_count ? iiospec.args[0] : 0;
         if (index >= indio_dev->num_channels) {
-                return -EINVAL;
+                err = -EINVAL;
                 goto err_put;
         }
         channel->channel = &indio_dev->channels[index];
@@ -450,7 +450,7 @@ static int iio_convert_raw_to_processed_unlocked(struct iio_channel *chan,
         s64 raw64 = raw;
         int ret;
 
-        ret = iio_channel_read(chan, &offset, NULL, IIO_CHAN_INFO_SCALE);
+        ret = iio_channel_read(chan, &offset, NULL, IIO_CHAN_INFO_OFFSET);
         if (ret == 0)
                 raw64 += offset;
 
diff --git a/drivers/infiniband/hw/qib/qib_keys.c b/drivers/infiniband/hw/qib/qib_keys.c
index 81c7b73695d2..3b9afccaaade 100644
--- a/drivers/infiniband/hw/qib/qib_keys.c
+++ b/drivers/infiniband/hw/qib/qib_keys.c
@@ -61,7 +61,7 @@ int qib_alloc_lkey(struct qib_mregion *mr, int dma_region)
         if (dma_region) {
                 struct qib_mregion *tmr;
 
-                tmr = rcu_dereference(dev->dma_mr);
+                tmr = rcu_access_pointer(dev->dma_mr);
                 if (!tmr) {
                         qib_get_mr(mr);
                         rcu_assign_pointer(dev->dma_mr, mr);
diff --git a/drivers/infiniband/ulp/iser/iscsi_iser.c b/drivers/infiniband/ulp/iser/iscsi_iser.c
index f19b0998a53c..2e84ef859c5b 100644
--- a/drivers/infiniband/ulp/iser/iscsi_iser.c
+++ b/drivers/infiniband/ulp/iser/iscsi_iser.c
@@ -5,6 +5,7 @@
  * Copyright (C) 2004 Alex Aizman
  * Copyright (C) 2005 Mike Christie
  * Copyright (c) 2005, 2006 Voltaire, Inc. All rights reserved.
+ * Copyright (c) 2013 Mellanox Technologies. All rights reserved.
  * maintained by openib-general@openib.org
  *
  * This software is available to you under a choice of one of two
diff --git a/drivers/infiniband/ulp/iser/iscsi_iser.h b/drivers/infiniband/ulp/iser/iscsi_iser.h
index 06f578cde75b..4f069c0d4c04 100644
--- a/drivers/infiniband/ulp/iser/iscsi_iser.h
+++ b/drivers/infiniband/ulp/iser/iscsi_iser.h
@@ -8,6 +8,7 @@
  *
  * Copyright (c) 2004, 2005, 2006 Voltaire, Inc. All rights reserved.
  * Copyright (c) 2005, 2006 Cisco Systems.  All rights reserved.
+ * Copyright (c) 2013 Mellanox Technologies. All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
diff --git a/drivers/infiniband/ulp/iser/iser_initiator.c b/drivers/infiniband/ulp/iser/iser_initiator.c
index a00ccd1ca333..b6d81a86c976 100644
--- a/drivers/infiniband/ulp/iser/iser_initiator.c
+++ b/drivers/infiniband/ulp/iser/iser_initiator.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2004, 2005, 2006 Voltaire, Inc. All rights reserved.
+ * Copyright (c) 2013 Mellanox Technologies. All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
diff --git a/drivers/infiniband/ulp/iser/iser_memory.c b/drivers/infiniband/ulp/iser/iser_memory.c
index 68ebb7fe072a..7827baf455a1 100644
--- a/drivers/infiniband/ulp/iser/iser_memory.c
+++ b/drivers/infiniband/ulp/iser/iser_memory.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2004, 2005, 2006 Voltaire, Inc. All rights reserved.
+ * Copyright (c) 2013 Mellanox Technologies. All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
diff --git a/drivers/infiniband/ulp/iser/iser_verbs.c b/drivers/infiniband/ulp/iser/iser_verbs.c
index 5278916c3103..2c4941d0656b 100644
--- a/drivers/infiniband/ulp/iser/iser_verbs.c
+++ b/drivers/infiniband/ulp/iser/iser_verbs.c
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2004, 2005, 2006 Voltaire, Inc. All rights reserved.
  * Copyright (c) 2005, 2006 Cisco Systems.  All rights reserved.
+ * Copyright (c) 2013 Mellanox Technologies. All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
@@ -292,10 +293,10 @@ out_err:
 }
 
 /**
- * releases the FMR pool, QP and CMA ID objects, returns 0 on success,
+ * releases the FMR pool and QP objects, returns 0 on success,
  * -1 on failure
  */
-static int iser_free_ib_conn_res(struct iser_conn *ib_conn, int can_destroy_id)
+static int iser_free_ib_conn_res(struct iser_conn *ib_conn)
 {
         int cq_index;
         BUG_ON(ib_conn == NULL);
@@ -314,13 +315,9 @@ static int iser_free_ib_conn_res(struct iser_conn *ib_conn, int can_destroy_id)
 
                 rdma_destroy_qp(ib_conn->cma_id);
         }
-        /* if cma handler context, the caller acts s.t the cma destroy the id */
-        if (ib_conn->cma_id != NULL && can_destroy_id)
-                rdma_destroy_id(ib_conn->cma_id);
 
         ib_conn->fmr_pool = NULL;
         ib_conn->qp       = NULL;
-        ib_conn->cma_id   = NULL;
         kfree(ib_conn->page_vec);
 
         if (ib_conn->login_buf) {
@@ -415,11 +412,16 @@ static void iser_conn_release(struct iser_conn *ib_conn, int can_destroy_id)
         list_del(&ib_conn->conn_list);
         mutex_unlock(&ig.connlist_mutex);
         iser_free_rx_descriptors(ib_conn);
-        iser_free_ib_conn_res(ib_conn, can_destroy_id);
+        iser_free_ib_conn_res(ib_conn);
         ib_conn->device = NULL;
         /* on EVENT_ADDR_ERROR there's no device yet for this conn */
         if (device != NULL)
                 iser_device_try_release(device);
+        /* if cma handler context, the caller actually destroy the id */
+        if (ib_conn->cma_id != NULL && can_destroy_id) {
+                rdma_destroy_id(ib_conn->cma_id);
+                ib_conn->cma_id = NULL;
+        }
         iscsi_destroy_endpoint(ib_conn->ep);
 }
 
diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.c b/drivers/infiniband/ulp/srpt/ib_srpt.c
index b08ca7a9f76b..3f3f0416fbdd 100644
--- a/drivers/infiniband/ulp/srpt/ib_srpt.c
+++ b/drivers/infiniband/ulp/srpt/ib_srpt.c
@@ -2227,6 +2227,27 @@ static void srpt_close_ch(struct srpt_rdma_ch *ch)
 }
 
 /**
+ * srpt_shutdown_session() - Whether or not a session may be shut down.
+ */
+static int srpt_shutdown_session(struct se_session *se_sess)
+{
+        struct srpt_rdma_ch *ch = se_sess->fabric_sess_ptr;
+        unsigned long flags;
+
+        spin_lock_irqsave(&ch->spinlock, flags);
+        if (ch->in_shutdown) {
+                spin_unlock_irqrestore(&ch->spinlock, flags);
+                return true;
+        }
+
+        ch->in_shutdown = true;
+        target_sess_cmd_list_set_waiting(se_sess);
+        spin_unlock_irqrestore(&ch->spinlock, flags);
+
+        return true;
+}
+
+/**
  * srpt_drain_channel() - Drain a channel by resetting the IB queue pair.
  * @cm_id: Pointer to the CM ID of the channel to be drained.
  *
@@ -2264,6 +2285,9 @@ static void srpt_drain_channel(struct ib_cm_id *cm_id)
         spin_unlock_irq(&sdev->spinlock);
 
         if (do_reset) {
+                if (ch->sess)
+                        srpt_shutdown_session(ch->sess);
+
                 ret = srpt_ch_qp_err(ch);
                 if (ret < 0)
                         printk(KERN_ERR "Setting queue pair in error state"
@@ -2328,7 +2352,7 @@ static void srpt_release_channel_work(struct work_struct *w)
         se_sess = ch->sess;
         BUG_ON(!se_sess);
 
-        target_wait_for_sess_cmds(se_sess, 0);
+        target_wait_for_sess_cmds(se_sess);
 
         transport_deregister_session_configfs(se_sess);
         transport_deregister_session(se_sess);
@@ -3467,14 +3491,6 @@ static void srpt_release_cmd(struct se_cmd *se_cmd)
 }
 
 /**
- * srpt_shutdown_session() - Whether or not a session may be shut down.
- */
-static int srpt_shutdown_session(struct se_session *se_sess)
-{
-        return true;
-}
-
-/**
  * srpt_close_session() - Forcibly close a session.
  *
  * Callback function invoked by the TCM core to clean up sessions associated
diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.h b/drivers/infiniband/ulp/srpt/ib_srpt.h
index 4caf55cda7b1..3dae156905de 100644
--- a/drivers/infiniband/ulp/srpt/ib_srpt.h
+++ b/drivers/infiniband/ulp/srpt/ib_srpt.h
@@ -325,6 +325,7 @@ struct srpt_rdma_ch {
         u8                      sess_name[36];
         struct work_struct      release_work;
         struct completion       *release_done;
+        bool                    in_shutdown;
 };
 
 /**
diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c
index 2f78538e09d0..b2420ae19e14 100644
--- a/drivers/input/mouse/synaptics.c
+++ b/drivers/input/mouse/synaptics.c
@@ -1379,6 +1379,7 @@ static int synaptics_reconnect(struct psmouse *psmouse)
 {
         struct synaptics_data *priv = psmouse->private;
         struct synaptics_data old_priv = *priv;
+        unsigned char param[2];
         int retry = 0;
         int error;
 
@@ -1394,6 +1395,7 @@ static int synaptics_reconnect(struct psmouse *psmouse)
                          */
                         ssleep(1);
                 }
+                ps2_command(&psmouse->ps2dev, param, PSMOUSE_CMD_GETID);
                 error = synaptics_detect(psmouse, 0);
         } while (error && ++retry < 3);
 
diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c
index 5c68e4486845..518282da6d85 100644
--- a/drivers/input/tablet/wacom_wac.c
+++ b/drivers/input/tablet/wacom_wac.c
@@ -1966,7 +1966,8 @@ static const struct wacom_features wacom_features_0xF4 =
           63, WACOM_24HD, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES };
 static const struct wacom_features wacom_features_0xF8 =
         { "Wacom Cintiq 24HD touch", WACOM_PKGLEN_INTUOS,   104480, 65600, 2047, /* Pen */
-          63, WACOM_24HD, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES, .oVid = USB_VENDOR_ID_WACOM, .oPid = 0xf6 };
+          63, WACOM_24HD, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES,
+          .oVid = USB_VENDOR_ID_WACOM, .oPid = 0xf6 };
 static const struct wacom_features wacom_features_0xF6 =
         { "Wacom Cintiq 24HD touch", .type = WACOM_24HDT, /* Touch */
           .oVid = USB_VENDOR_ID_WACOM, .oPid = 0xf8, .touch_max = 10 };
@@ -2009,7 +2010,8 @@ static const struct wacom_features wacom_features_0xFA =
           63, WACOM_22HD, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES };
 static const struct wacom_features wacom_features_0x5B =
         { "Wacom Cintiq 22HDT", WACOM_PKGLEN_INTUOS,      95840, 54260, 2047,
-          63, WACOM_24HD, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES, .oVid = USB_VENDOR_ID_WACOM, .oPid = 0x5e };
+          63, WACOM_22HD, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES,
+          .oVid = USB_VENDOR_ID_WACOM, .oPid = 0x5e };
 static const struct wacom_features wacom_features_0x5E =
         { "Wacom Cintiq 22HDT", .type = WACOM_24HDT,
           .oVid = USB_VENDOR_ID_WACOM, .oPid = 0x5b, .touch_max = 10 };
@@ -2042,7 +2044,7 @@ static const struct wacom_features wacom_features_0xE5 =
 static const struct wacom_features wacom_features_0xE6 =
         { "Wacom ISDv4 E6",       WACOM_PKGLEN_TPC2FG,    27760, 15694,  255,
           0, TABLETPC2FG, WACOM_INTUOS_RES, WACOM_INTUOS_RES,
-        .touch_max = 2 };
+          .touch_max = 2 };
 static const struct wacom_features wacom_features_0xEC =
         { "Wacom ISDv4 EC",       WACOM_PKGLEN_GRAPHIRE,  25710, 14500,  255,
           0, TABLETPC,    WACOM_INTUOS_RES, WACOM_INTUOS_RES };
diff --git a/drivers/irqchip/irq-mxs.c b/drivers/irqchip/irq-mxs.c
index 29889bbdcc6d..63b3d4eb0ef7 100644
--- a/drivers/irqchip/irq-mxs.c
+++ b/drivers/irqchip/irq-mxs.c
@@ -76,16 +76,10 @@ asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
 {
         u32 irqnr;
 
-        do {
-                irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET);
-                if (irqnr != 0x7f) {
-                        __raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR);
-                        irqnr = irq_find_mapping(icoll_domain, irqnr);
-                        handle_IRQ(irqnr, regs);
-                        continue;
-                }
-                break;
-        } while (1);
+        irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET);
+        __raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR);
+        irqnr = irq_find_mapping(icoll_domain, irqnr);
+        handle_IRQ(irqnr, regs);
 }
 
 static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
diff --git a/drivers/irqchip/irq-versatile-fpga.c b/drivers/irqchip/irq-versatile-fpga.c
index 065b7a31a478..47a52ab580d8 100644
--- a/drivers/irqchip/irq-versatile-fpga.c
+++ b/drivers/irqchip/irq-versatile-fpga.c
@@ -119,7 +119,7 @@ static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
 
         /* Skip invalid IRQs, only register handlers for the real ones */
         if (!(f->valid & BIT(hwirq)))
-                return -ENOTSUPP;
+                return -EPERM;
         irq_set_chip_data(irq, f);
         irq_set_chip_and_handler(irq, &f->chip,
                                 handle_level_irq);
diff --git a/drivers/irqchip/irq-vic.c b/drivers/irqchip/irq-vic.c
index 884d11c7355f..2bbb00404cf5 100644
--- a/drivers/irqchip/irq-vic.c
+++ b/drivers/irqchip/irq-vic.c
@@ -197,7 +197,7 @@ static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq,
 
         /* Skip invalid IRQs, only register handlers for the real ones */
         if (!(v->valid_sources & (1 << hwirq)))
-                return -ENOTSUPP;
+                return -EPERM;
         irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
         irq_set_chip_data(irq, v->base);
         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
diff --git a/drivers/md/bcache/Kconfig b/drivers/md/bcache/Kconfig
index 05c220d05e23..f950c9d29f3e 100644
--- a/drivers/md/bcache/Kconfig
+++ b/drivers/md/bcache/Kconfig
@@ -1,7 +1,6 @@
 
 config BCACHE
         tristate "Block device as cache"
-        select CLOSURES
         ---help---
         Allows a block device to be used as cache for other devices; uses
         a btree for indexing and the layout is optimized for SSDs.
diff --git a/drivers/md/bcache/bcache.h b/drivers/md/bcache/bcache.h
index 340146d7c17f..d3e15b42a4ab 100644
--- a/drivers/md/bcache/bcache.h
+++ b/drivers/md/bcache/bcache.h
@@ -1241,7 +1241,7 @@ void bch_cache_set_stop(struct cache_set *);
 struct cache_set *bch_cache_set_alloc(struct cache_sb *);
 void bch_btree_cache_free(struct cache_set *);
 int bch_btree_cache_alloc(struct cache_set *);
-void bch_writeback_init_cached_dev(struct cached_dev *);
+void bch_cached_dev_writeback_init(struct cached_dev *);
 void bch_moving_init_cache_set(struct cache_set *);
 
 void bch_cache_allocator_exit(struct cache *ca);
diff --git a/drivers/md/bcache/stats.c b/drivers/md/bcache/stats.c
index 64e679449c2a..b8730e714d69 100644
--- a/drivers/md/bcache/stats.c
+++ b/drivers/md/bcache/stats.c
@@ -93,24 +93,6 @@ static struct attribute *bch_stats_files[] = {
 };
 static KTYPE(bch_stats);
 
-static void scale_accounting(unsigned long data);
-
-void bch_cache_accounting_init(struct cache_accounting *acc,
-                               struct closure *parent)
-{
-        kobject_init(&acc->total.kobj,          &bch_stats_ktype);
-        kobject_init(&acc->five_minute.kobj,    &bch_stats_ktype);
-        kobject_init(&acc->hour.kobj,           &bch_stats_ktype);
-        kobject_init(&acc->day.kobj,            &bch_stats_ktype);
-
-        closure_init(&acc->cl, parent);
-        init_timer(&acc->timer);
-        acc->timer.expires      = jiffies + accounting_delay;
-        acc->timer.data         = (unsigned long) acc;
-        acc->timer.function     = scale_accounting;
-        add_timer(&acc->timer);
-}
-
 int bch_cache_accounting_add_kobjs(struct cache_accounting *acc,
                                    struct kobject *parent)
 {
@@ -244,3 +226,19 @@ void bch_mark_sectors_bypassed(struct search *s, int sectors)
         atomic_add(sectors, &dc->accounting.collector.sectors_bypassed);
         atomic_add(sectors, &s->op.c->accounting.collector.sectors_bypassed);
 }
+
+void bch_cache_accounting_init(struct cache_accounting *acc,
+                               struct closure *parent)
+{
+        kobject_init(&acc->total.kobj,          &bch_stats_ktype);
+        kobject_init(&acc->five_minute.kobj,    &bch_stats_ktype);
+        kobject_init(&acc->hour.kobj,           &bch_stats_ktype);
+        kobject_init(&acc->day.kobj,            &bch_stats_ktype);
+
+        closure_init(&acc->cl, parent);
+        init_timer(&acc->timer);
+        acc->timer.expires      = jiffies + accounting_delay;
+        acc->timer.data         = (unsigned long) acc;
+        acc->timer.function     = scale_accounting;
+        add_timer(&acc->timer);
+}
diff --git a/drivers/md/bcache/super.c b/drivers/md/bcache/super.c
index c8046bc4aa57..f88e2b653a3f 100644
--- a/drivers/md/bcache/super.c
+++ b/drivers/md/bcache/super.c
@@ -634,11 +634,10 @@ static int open_dev(struct block_device *b, fmode_t mode)
         return 0;
 }
 
-static int release_dev(struct gendisk *b, fmode_t mode)
+static void release_dev(struct gendisk *b, fmode_t mode)
 {
         struct bcache_device *d = b->private_data;
         closure_put(&d->cl);
-        return 0;
 }
 
 static int ioctl_dev(struct block_device *b, fmode_t mode,
@@ -732,8 +731,7 @@ static void bcache_device_free(struct bcache_device *d)
 
         if (d->c)
                 bcache_device_detach(d);
-
-        if (d->disk)
+        if (d->disk && d->disk->flags & GENHD_FL_UP)
                 del_gendisk(d->disk);
         if (d->disk && d->disk->queue)
                 blk_cleanup_queue(d->disk->queue);
@@ -756,12 +754,9 @@ static int bcache_device_init(struct bcache_device *d, unsigned block_size)
         if (!(d->bio_split = bioset_create(4, offsetof(struct bbio, bio))) ||
             !(d->unaligned_bvec = mempool_create_kmalloc_pool(1,
                                 sizeof(struct bio_vec) * BIO_MAX_PAGES)) ||
-            bio_split_pool_init(&d->bio_split_hook))
-
-                return -ENOMEM;
-
-        d->disk = alloc_disk(1);
-        if (!d->disk)
+            bio_split_pool_init(&d->bio_split_hook) ||
+            !(d->disk = alloc_disk(1)) ||
+            !(q = blk_alloc_queue(GFP_KERNEL)))
                 return -ENOMEM;
 
         snprintf(d->disk->disk_name, DISK_NAME_LEN, "bcache%i", bcache_minor);
@@ -771,10 +766,6 @@ static int bcache_device_init(struct bcache_device *d, unsigned block_size)
         d->disk->fops           = &bcache_ops;
         d->disk->private_data   = d;
 
-        q = blk_alloc_queue(GFP_KERNEL);
-        if (!q)
-                return -ENOMEM;
-
         blk_queue_make_request(q, NULL);
         d->disk->queue                  = q;
         q->queuedata                    = d;
@@ -999,14 +990,17 @@ static void cached_dev_free(struct closure *cl)
 
         mutex_lock(&bch_register_lock);
 
-        bd_unlink_disk_holder(dc->bdev, dc->disk.disk);
+        if (atomic_read(&dc->running))
+                bd_unlink_disk_holder(dc->bdev, dc->disk.disk);
         bcache_device_free(&dc->disk);
         list_del(&dc->list);
 
         mutex_unlock(&bch_register_lock);
 
         if (!IS_ERR_OR_NULL(dc->bdev)) {
-                blk_sync_queue(bdev_get_queue(dc->bdev));
+                if (dc->bdev->bd_disk)
+                        blk_sync_queue(bdev_get_queue(dc->bdev));
+
                 blkdev_put(dc->bdev, FMODE_READ|FMODE_WRITE|FMODE_EXCL);
         }
 
@@ -1028,73 +1022,67 @@ static void cached_dev_flush(struct closure *cl)
 
 static int cached_dev_init(struct cached_dev *dc, unsigned block_size)
 {
-        int err;
+        int ret;
         struct io *io;
-
-        closure_init(&dc->disk.cl, NULL);
-        set_closure_fn(&dc->disk.cl, cached_dev_flush, system_wq);
+        struct request_queue *q = bdev_get_queue(dc->bdev);
 
         __module_get(THIS_MODULE);
         INIT_LIST_HEAD(&dc->list);
+        closure_init(&dc->disk.cl, NULL);
+        set_closure_fn(&dc->disk.cl, cached_dev_flush, system_wq);
         kobject_init(&dc->disk.kobj, &bch_cached_dev_ktype);
-
-        bch_cache_accounting_init(&dc->accounting, &dc->disk.cl);
-
-        err = bcache_device_init(&dc->disk, block_size);
-        if (err)
-                goto err;
-
-        spin_lock_init(&dc->io_lock);
-        closure_init_unlocked(&dc->sb_write);
         INIT_WORK(&dc->detach, cached_dev_detach_finish);
+        closure_init_unlocked(&dc->sb_write);
+        INIT_LIST_HEAD(&dc->io_lru);
+        spin_lock_init(&dc->io_lock);
+        bch_cache_accounting_init(&dc->accounting, &dc->disk.cl);
 
         dc->sequential_merge            = true;
         dc->sequential_cutoff           = 4 << 20;
 
-        INIT_LIST_HEAD(&dc->io_lru);
-        dc->sb_bio.bi_max_vecs  = 1;
-        dc->sb_bio.bi_io_vec    = dc->sb_bio.bi_inline_vecs;
-
         for (io = dc->io; io < dc->io + RECENT_IO; io++) {
                 list_add(&io->lru, &dc->io_lru);
                 hlist_add_head(&io->hash, dc->io_hash + RECENT_IO);
         }
 
-        bch_writeback_init_cached_dev(dc);
+        ret = bcache_device_init(&dc->disk, block_size);
+        if (ret)
+                return ret;
+
+        set_capacity(dc->disk.disk,
+                     dc->bdev->bd_part->nr_sects - dc->sb.data_offset);
+
+        dc->disk.disk->queue->backing_dev_info.ra_pages =
+                max(dc->disk.disk->queue->backing_dev_info.ra_pages,
+                    q->backing_dev_info.ra_pages);
+
+        bch_cached_dev_request_init(dc);
+        bch_cached_dev_writeback_init(dc);
         return 0;
-err:
-        bcache_device_stop(&dc->disk);
-        return err;
 }
 
 /* Cached device - bcache superblock */
 
-static const char *register_bdev(struct cache_sb *sb, struct page *sb_page,
+static void register_bdev(struct cache_sb *sb, struct page *sb_page,
                                  struct block_device *bdev,
                                  struct cached_dev *dc)
 {
         char name[BDEVNAME_SIZE];
         const char *err = "cannot allocate memory";
-        struct gendisk *g;
         struct cache_set *c;
 
-        if (!dc || cached_dev_init(dc, sb->block_size << 9) != 0)
-                return err;
-
         memcpy(&dc->sb, sb, sizeof(struct cache_sb));
-        dc->sb_bio.bi_io_vec[0].bv_page = sb_page;
         dc->bdev = bdev;
         dc->bdev->bd_holder = dc;
 
-        g = dc->disk.disk;
-
-        set_capacity(g, dc->bdev->bd_part->nr_sects - dc->sb.data_offset);
-
-        g->queue->backing_dev_info.ra_pages =
-                max(g->queue->backing_dev_info.ra_pages,
-                    bdev->bd_queue->backing_dev_info.ra_pages);
+        bio_init(&dc->sb_bio);
+        dc->sb_bio.bi_max_vecs  = 1;
+        dc->sb_bio.bi_io_vec    = dc->sb_bio.bi_inline_vecs;
+        dc->sb_bio.bi_io_vec[0].bv_page = sb_page;
+        get_page(sb_page);
 
-        bch_cached_dev_request_init(dc);
+        if (cached_dev_init(dc, sb->block_size << 9))
+                goto err;
 
         err = "error creating kobject";
         if (kobject_add(&dc->disk.kobj, &part_to_dev(bdev->bd_part)->kobj,
@@ -1103,6 +1091,8 @@ static const char *register_bdev(struct cache_sb *sb, struct page *sb_page,
         if (bch_cache_accounting_add_kobjs(&dc->accounting, &dc->disk.kobj))
                 goto err;
 
+        pr_info("registered backing device %s", bdevname(bdev, name));
+
         list_add(&dc->list, &uncached_devices);
         list_for_each_entry(c, &bch_cache_sets, list)
                 bch_cached_dev_attach(dc, c);
@@ -1111,15 +1101,10 @@ static const char *register_bdev(struct cache_sb *sb, struct page *sb_page,
             BDEV_STATE(&dc->sb) == BDEV_STATE_STALE)
                 bch_cached_dev_run(dc);
 
-        return NULL;
+        return;
 err:
-        kobject_put(&dc->disk.kobj);
         pr_notice("error opening %s: %s", bdevname(bdev, name), err);
-        /*
-         * Return NULL instead of an error because kobject_put() cleans
-         * everything up
-         */
-        return NULL;
+        bcache_device_stop(&dc->disk);
 }
 
 /* Flash only volumes */
@@ -1717,20 +1702,11 @@ static int cache_alloc(struct cache_sb *sb, struct cache *ca)
         size_t free;
         struct bucket *b;
 
-        if (!ca)
-                return -ENOMEM;
-
         __module_get(THIS_MODULE);
         kobject_init(&ca->kobj, &bch_cache_ktype);
 
-        memcpy(&ca->sb, sb, sizeof(struct cache_sb));
-
         INIT_LIST_HEAD(&ca->discards);
 
-        bio_init(&ca->sb_bio);
-        ca->sb_bio.bi_max_vecs  = 1;
-        ca->sb_bio.bi_io_vec    = ca->sb_bio.bi_inline_vecs;
-
         bio_init(&ca->journal.bio);
         ca->journal.bio.bi_max_vecs = 8;
         ca->journal.bio.bi_io_vec = ca->journal.bio.bi_inline_vecs;
@@ -1742,18 +1718,17 @@ static int cache_alloc(struct cache_sb *sb, struct cache *ca)
             !init_fifo(&ca->free_inc,   free << 2, GFP_KERNEL) ||
             !init_fifo(&ca->unused,     free << 2, GFP_KERNEL) ||
             !init_heap(&ca->heap,       free << 3, GFP_KERNEL) ||
-            !(ca->buckets       = vmalloc(sizeof(struct bucket) *
+            !(ca->buckets       = vzalloc(sizeof(struct bucket) *
                                           ca->sb.nbuckets)) ||
             !(ca->prio_buckets  = kzalloc(sizeof(uint64_t) * prio_buckets(ca) *
                                           2, GFP_KERNEL)) ||
             !(ca->disk_buckets  = alloc_bucket_pages(GFP_KERNEL, ca)) ||
             !(ca->alloc_workqueue = alloc_workqueue("bch_allocator", 0, 1)) ||
             bio_split_pool_init(&ca->bio_split_hook))
-                goto err;
+                return -ENOMEM;
 
         ca->prio_last_buckets = ca->prio_buckets + prio_buckets(ca);
 
-        memset(ca->buckets, 0, ca->sb.nbuckets * sizeof(struct bucket));
         for_each_bucket(b, ca)
                 atomic_set(&b->pin, 0);
 
@@ -1766,22 +1741,28 @@ err:
         return -ENOMEM;
 }
 
-static const char *register_cache(struct cache_sb *sb, struct page *sb_page,
+static void register_cache(struct cache_sb *sb, struct page *sb_page,
                                   struct block_device *bdev, struct cache *ca)
 {
         char name[BDEVNAME_SIZE];
         const char *err = "cannot allocate memory";
 
-        if (cache_alloc(sb, ca) != 0)
-                return err;
-
-        ca->sb_bio.bi_io_vec[0].bv_page = sb_page;
+        memcpy(&ca->sb, sb, sizeof(struct cache_sb));
         ca->bdev = bdev;
         ca->bdev->bd_holder = ca;
 
+        bio_init(&ca->sb_bio);
+        ca->sb_bio.bi_max_vecs  = 1;
+        ca->sb_bio.bi_io_vec    = ca->sb_bio.bi_inline_vecs;
+        ca->sb_bio.bi_io_vec[0].bv_page = sb_page;
+        get_page(sb_page);
+
         if (blk_queue_discard(bdev_get_queue(ca->bdev)))
                 ca->discard = CACHE_DISCARD(&ca->sb);
 
+        if (cache_alloc(sb, ca) != 0)
+                goto err;
+
         err = "error creating kobject";
         if (kobject_add(&ca->kobj, &part_to_dev(bdev->bd_part)->kobj, "bcache"))
                 goto err;
@@ -1791,15 +1772,10 @@ static const char *register_cache(struct cache_sb *sb, struct page *sb_page,
                 goto err;
 
         pr_info("registered cache device %s", bdevname(bdev, name));
-
-        return NULL;
+        return;
 err:
+        pr_notice("error opening %s: %s", bdevname(bdev, name), err);
         kobject_put(&ca->kobj);
-        pr_info("error opening %s: %s", bdevname(bdev, name), err);
-        /* Return NULL instead of an error because kobject_put() cleans
-         * everything up
-         */
-        return NULL;
 }
 
 /* Global interfaces/init */
@@ -1833,12 +1809,15 @@ static ssize_t register_bcache(struct kobject *k, struct kobj_attribute *attr,
         bdev = blkdev_get_by_path(strim(path),
                                   FMODE_READ|FMODE_WRITE|FMODE_EXCL,
                                   sb);
-        if (bdev == ERR_PTR(-EBUSY))
-                err = "device busy";
-
-        if (IS_ERR(bdev) ||
-            set_blocksize(bdev, 4096))
+        if (IS_ERR(bdev)) {
+                if (bdev == ERR_PTR(-EBUSY))
+                        err = "device busy";
                 goto err;
+        }
+
+        err = "failed to set blocksize";
+        if (set_blocksize(bdev, 4096))
+                goto err_close;
 
         err = read_super(sb, bdev, &sb_page);
         if (err)
@@ -1846,33 +1825,33 @@ static ssize_t register_bcache(struct kobject *k, struct kobj_attribute *attr,
 
         if (SB_IS_BDEV(sb)) {
                 struct cached_dev *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
+                if (!dc)
+                        goto err_close;
 
-                err = register_bdev(sb, sb_page, bdev, dc);
+                register_bdev(sb, sb_page, bdev, dc);
         } else {
                 struct cache *ca = kzalloc(sizeof(*ca), GFP_KERNEL);
+                if (!ca)
+                        goto err_close;
 
-                err = register_cache(sb, sb_page, bdev, ca);
+                register_cache(sb, sb_page, bdev, ca);
         }
-
-        if (err) {
-                /* register_(bdev|cache) will only return an error if they
-                 * didn't get far enough to create the kobject - if they did,
-                 * the kobject destructor will do this cleanup.
-                 */
+out:
+        if (sb_page)
                 put_page(sb_page);
-err_close:
-                blkdev_put(bdev, FMODE_READ|FMODE_WRITE|FMODE_EXCL);
-err:
-                if (attr != &ksysfs_register_quiet)
-                        pr_info("error opening %s: %s", path, err);
-                ret = -EINVAL;
-        }
-
         kfree(sb);
         kfree(path);
         mutex_unlock(&bch_register_lock);
         module_put(THIS_MODULE);
         return ret;
+
+err_close:
+        blkdev_put(bdev, FMODE_READ|FMODE_WRITE|FMODE_EXCL);
+err:
+        if (attr != &ksysfs_register_quiet)
+                pr_info("error opening %s: %s", path, err);
+        ret = -EINVAL;
+        goto out;
 }
 
 static int bcache_reboot(struct notifier_block *n, unsigned long code, void *x)
diff --git a/drivers/md/bcache/writeback.c b/drivers/md/bcache/writeback.c
index 93e7e31a4bd3..2714ed3991d1 100644
--- a/drivers/md/bcache/writeback.c
+++ b/drivers/md/bcache/writeback.c
@@ -375,7 +375,7 @@ err:
         refill_dirty(cl);
 }
 
-void bch_writeback_init_cached_dev(struct cached_dev *dc)
+void bch_cached_dev_writeback_init(struct cached_dev *dc)
 {
         closure_init_unlocked(&dc->writeback);
         init_rwsem(&dc->writeback_lock);
diff --git a/drivers/md/md.c b/drivers/md/md.c
index 681d1099a2d5..9b82377a833b 100644
--- a/drivers/md/md.c
+++ b/drivers/md/md.c
@@ -5268,8 +5268,8 @@ static void md_clean(struct mddev *mddev)
 
 static void __md_stop_writes(struct mddev *mddev)
 {
+        set_bit(MD_RECOVERY_FROZEN, &mddev->recovery);
         if (mddev->sync_thread) {
-                set_bit(MD_RECOVERY_FROZEN, &mddev->recovery);
                 set_bit(MD_RECOVERY_INTR, &mddev->recovery);
                 md_reap_sync_thread(mddev);
         }
diff --git a/drivers/md/raid1.c b/drivers/md/raid1.c
index 55951182af73..6e17f8181c4b 100644
--- a/drivers/md/raid1.c
+++ b/drivers/md/raid1.c
@@ -417,7 +417,17 @@ static void raid1_end_write_request(struct bio *bio, int error)
 
                 r1_bio->bios[mirror] = NULL;
                 to_put = bio;
-                set_bit(R1BIO_Uptodate, &r1_bio->state);
+                /*
+                 * Do not set R1BIO_Uptodate if the current device is
+                 * rebuilding or Faulty. This is because we cannot use
+                 * such device for properly reading the data back (we could
+                 * potentially use it, if the current write would have felt
+                 * before rdev->recovery_offset, but for simplicity we don't
+                 * check this here.
+                 */
+                if (test_bit(In_sync, &conf->mirrors[mirror].rdev->flags) &&
+                    !test_bit(Faulty, &conf->mirrors[mirror].rdev->flags))
+                        set_bit(R1BIO_Uptodate, &r1_bio->state);
 
                 /* Maybe we can clear some bad blocks. */
                 if (is_badblock(conf->mirrors[mirror].rdev,
@@ -870,17 +880,17 @@ static void allow_barrier(struct r1conf *conf)
         wake_up(&conf->wait_barrier);
 }
 
-static void freeze_array(struct r1conf *conf)
+static void freeze_array(struct r1conf *conf, int extra)
 {
         /* stop syncio and normal IO and wait for everything to
          * go quite.
          * We increment barrier and nr_waiting, and then
-         * wait until nr_pending match nr_queued+1
+         * wait until nr_pending match nr_queued+extra
          * This is called in the context of one normal IO request
          * that has failed. Thus any sync request that might be pending
          * will be blocked by nr_pending, and we need to wait for
          * pending IO requests to complete or be queued for re-try.
-         * Thus the number queued (nr_queued) plus this request (1)
+         * Thus the number queued (nr_queued) plus this request (extra)
          * must match the number of pending IOs (nr_pending) before
          * we continue.
          */
@@ -888,7 +898,7 @@ static void freeze_array(struct r1conf *conf)
         conf->barrier++;
         conf->nr_waiting++;
         wait_event_lock_irq_cmd(conf->wait_barrier,
-                                conf->nr_pending == conf->nr_queued+1,
+                                conf->nr_pending == conf->nr_queued+extra,
                                 conf->resync_lock,
                                 flush_pending_writes(conf));
         spin_unlock_irq(&conf->resync_lock);
@@ -1544,8 +1554,8 @@ static int raid1_add_disk(struct mddev *mddev, struct md_rdev *rdev)
                  * we wait for all outstanding requests to complete.
                  */
                 synchronize_sched();
-                raise_barrier(conf);
-                lower_barrier(conf);
+                freeze_array(conf, 0);
+                unfreeze_array(conf);
                 clear_bit(Unmerged, &rdev->flags);
         }
         md_integrity_add_rdev(rdev, mddev);
@@ -1595,11 +1605,11 @@ static int raid1_remove_disk(struct mddev *mddev, struct md_rdev *rdev)
                          */
                         struct md_rdev *repl =
                                 conf->mirrors[conf->raid_disks + number].rdev;
-                        raise_barrier(conf);
+                        freeze_array(conf, 0);
                         clear_bit(Replacement, &repl->flags);
                         p->rdev = repl;
                         conf->mirrors[conf->raid_disks + number].rdev = NULL;
-                        lower_barrier(conf);
+                        unfreeze_array(conf);
                         clear_bit(WantReplacement, &rdev->flags);
                 } else
                         clear_bit(WantReplacement, &rdev->flags);
@@ -2195,7 +2205,7 @@ static void handle_read_error(struct r1conf *conf, struct r1bio *r1_bio)
          * frozen
          */
         if (mddev->ro == 0) {
-                freeze_array(conf);
+                freeze_array(conf, 1);
                 fix_read_error(conf, r1_bio->read_disk,
                                r1_bio->sector, r1_bio->sectors);
                 unfreeze_array(conf);
@@ -2780,8 +2790,8 @@ static int run(struct mddev *mddev)
                 return PTR_ERR(conf);
 
         if (mddev->queue)
-                blk_queue_max_write_same_sectors(mddev->queue,
-                                                 mddev->chunk_sectors);
+                blk_queue_max_write_same_sectors(mddev->queue, 0);
+
         rdev_for_each(rdev, mddev) {
                 if (!mddev->gendisk)
                         continue;
@@ -2963,7 +2973,7 @@ static int raid1_reshape(struct mddev *mddev)
                 return -ENOMEM;
         }
 
-        raise_barrier(conf);
+        freeze_array(conf, 0);
 
         /* ok, everything is stopped */
         oldpool = conf->r1bio_pool;
@@ -2994,7 +3004,7 @@ static int raid1_reshape(struct mddev *mddev)
         conf->raid_disks = mddev->raid_disks = raid_disks;
         mddev->delta_disks = 0;
 
-        lower_barrier(conf);
+        unfreeze_array(conf);
 
         set_bit(MD_RECOVERY_NEEDED, &mddev->recovery);
         md_wakeup_thread(mddev->thread);
diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c
index 59d4daa5f4c7..6ddae2501b9a 100644
--- a/drivers/md/raid10.c
+++ b/drivers/md/raid10.c
@@ -490,7 +490,17 @@ static void raid10_end_write_request(struct bio *bio, int error)
                 sector_t first_bad;
                 int bad_sectors;
 
-                set_bit(R10BIO_Uptodate, &r10_bio->state);
+                /*
+                 * Do not set R10BIO_Uptodate if the current device is
+                 * rebuilding or Faulty. This is because we cannot use
+                 * such device for properly reading the data back (we could
+                 * potentially use it, if the current write would have felt
+                 * before rdev->recovery_offset, but for simplicity we don't
+                 * check this here.
+                 */
+                if (test_bit(In_sync, &rdev->flags) &&
+                    !test_bit(Faulty, &rdev->flags))
+                        set_bit(R10BIO_Uptodate, &r10_bio->state);
 
                 /* Maybe we can clear some bad blocks. */
                 if (is_badblock(rdev,
@@ -1055,17 +1065,17 @@ static void allow_barrier(struct r10conf *conf)
         wake_up(&conf->wait_barrier);
 }
 
-static void freeze_array(struct r10conf *conf)
+static void freeze_array(struct r10conf *conf, int extra)
 {
         /* stop syncio and normal IO and wait for everything to
          * go quiet.
          * We increment barrier and nr_waiting, and then
-         * wait until nr_pending match nr_queued+1
+         * wait until nr_pending match nr_queued+extra
          * This is called in the context of one normal IO request
          * that has failed. Thus any sync request that might be pending
          * will be blocked by nr_pending, and we need to wait for
          * pending IO requests to complete or be queued for re-try.
-         * Thus the number queued (nr_queued) plus this request (1)
+         * Thus the number queued (nr_queued) plus this request (extra)
          * must match the number of pending IOs (nr_pending) before
          * we continue.
          */
@@ -1073,7 +1083,7 @@ static void freeze_array(struct r10conf *conf)
         conf->barrier++;
         conf->nr_waiting++;
         wait_event_lock_irq_cmd(conf->wait_barrier,
-                                conf->nr_pending == conf->nr_queued+1,
+                                conf->nr_pending == conf->nr_queued+extra,
                                 conf->resync_lock,
                                 flush_pending_writes(conf));
 
@@ -1837,8 +1847,8 @@ static int raid10_add_disk(struct mddev *mddev, struct md_rdev *rdev)
                  * we wait for all outstanding requests to complete.
                  */
                 synchronize_sched();
-                raise_barrier(conf, 0);
-                lower_barrier(conf);
+                freeze_array(conf, 0);
+                unfreeze_array(conf);
                 clear_bit(Unmerged, &rdev->flags);
         }
         md_integrity_add_rdev(rdev, mddev);
@@ -2612,7 +2622,7 @@ static void handle_read_error(struct mddev *mddev, struct r10bio *r10_bio)
         r10_bio->devs[slot].bio = NULL;
 
         if (mddev->ro == 0) {
-                freeze_array(conf);
+                freeze_array(conf, 1);
                 fix_read_error(conf, mddev, r10_bio);
                 unfreeze_array(conf);
         } else
@@ -3609,8 +3619,7 @@ static int run(struct mddev *mddev)
         if (mddev->queue) {
                 blk_queue_max_discard_sectors(mddev->queue,
                                               mddev->chunk_sectors);
-                blk_queue_max_write_same_sectors(mddev->queue,
-                                                 mddev->chunk_sectors);
+                blk_queue_max_write_same_sectors(mddev->queue, 0);
                 blk_queue_io_min(mddev->queue, chunk_size);
                 if (conf->geo.raid_disks % conf->geo.near_copies)
                         blk_queue_io_opt(mddev->queue, chunk_size * conf->geo.raid_disks);
diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
index 9359828ffe26..05e4a105b9c7 100644
--- a/drivers/md/raid5.c
+++ b/drivers/md/raid5.c
@@ -664,6 +664,7 @@ static void ops_run_io(struct stripe_head *sh, struct stripe_head_state *s)
                         if (test_bit(R5_ReadNoMerge, &sh->dev[i].flags))
                                 bi->bi_rw |= REQ_FLUSH;
 
+                        bi->bi_vcnt = 1;
                         bi->bi_io_vec[0].bv_len = STRIPE_SIZE;
                         bi->bi_io_vec[0].bv_offset = 0;
                         bi->bi_size = STRIPE_SIZE;
@@ -701,6 +702,7 @@ static void ops_run_io(struct stripe_head *sh, struct stripe_head_state *s)
                         else
                                 rbi->bi_sector = (sh->sector
                                                   + rrdev->data_offset);
+                        rbi->bi_vcnt = 1;
                         rbi->bi_io_vec[0].bv_len = STRIPE_SIZE;
                         rbi->bi_io_vec[0].bv_offset = 0;
                         rbi->bi_size = STRIPE_SIZE;
@@ -5464,7 +5466,7 @@ static int run(struct mddev *mddev)
                 if (mddev->major_version == 0 &&
                     mddev->minor_version > 90)
                         rdev->recovery_offset = reshape_offset;
-                        
+
                 if (rdev->recovery_offset < reshape_offset) {
                         /* We need to check old and new layout */
                         if (!only_parity(rdev->raid_disk,
@@ -5587,6 +5589,8 @@ static int run(struct mddev *mddev)
                  */
                 mddev->queue->limits.discard_zeroes_data = 0;
 
+                blk_queue_max_write_same_sectors(mddev->queue, 0);
+
                 rdev_for_each(rdev, mddev) {
                         disk_stack_limits(mddev->gendisk, rdev->bdev,
                                           rdev->data_offset << 9);
diff --git a/drivers/media/pci/zoran/zoran.h b/drivers/media/pci/zoran/zoran.h
index ca2754a3cd63..5e040085c2ff 100644
--- a/drivers/media/pci/zoran/zoran.h
+++ b/drivers/media/pci/zoran/zoran.h
@@ -176,7 +176,7 @@ struct zoran_fh;
 
 struct zoran_mapping {
         struct zoran_fh *fh;
-        int count;
+        atomic_t count;
 };
 
 struct zoran_buffer {
diff --git a/drivers/media/pci/zoran/zoran_driver.c b/drivers/media/pci/zoran/zoran_driver.c
index 1168a84a737d..d133c30c3fdc 100644
--- a/drivers/media/pci/zoran/zoran_driver.c
+++ b/drivers/media/pci/zoran/zoran_driver.c
@@ -2803,8 +2803,7 @@ static void
 zoran_vm_open (struct vm_area_struct *vma)
 {
         struct zoran_mapping *map = vma->vm_private_data;
-
-        map->count++;
+        atomic_inc(&map->count);
 }
 
 static void
@@ -2815,7 +2814,7 @@ zoran_vm_close (struct vm_area_struct *vma)
         struct zoran *zr = fh->zr;
         int i;
 
-        if (--map->count > 0)
+        if (!atomic_dec_and_mutex_lock(&map->count, &zr->resource_lock))
                 return;
 
         dprintk(3, KERN_INFO "%s: %s - munmap(%s)\n", ZR_DEVNAME(zr),
@@ -2828,14 +2827,16 @@ zoran_vm_close (struct vm_area_struct *vma)
         kfree(map);
 
         /* Any buffers still mapped? */
-        for (i = 0; i < fh->buffers.num_buffers; i++)
-                if (fh->buffers.buffer[i].map)
+        for (i = 0; i < fh->buffers.num_buffers; i++) {
+                if (fh->buffers.buffer[i].map) {
+                        mutex_unlock(&zr->resource_lock);
                         return;
+                }
+        }
 
         dprintk(3, KERN_INFO "%s: %s - free %s buffers\n", ZR_DEVNAME(zr),
                 __func__, mode_name(fh->map_mode));
 
-        mutex_lock(&zr->resource_lock);
 
         if (fh->map_mode == ZORAN_MAP_MODE_RAW) {
                 if (fh->buffers.active != ZORAN_FREE) {
@@ -2939,7 +2940,7 @@ zoran_mmap (struct file           *file,
                 goto mmap_unlock_and_return;
         }
         map->fh = fh;
-        map->count = 1;
+        atomic_set(&map->count, 1);
 
         vma->vm_ops = &zoran_vm_ops;
         vma->vm_flags |= VM_DONTEXPAND;
diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index 0494d2769fd7..bce695d42f10 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -159,7 +159,7 @@ config VIDEO_MEM2MEM_DEINTERLACE
 
 config VIDEO_SAMSUNG_S5P_G2D
         tristate "Samsung S5P and EXYNOS4 G2D 2d graphics accelerator driver"
-        depends on VIDEO_DEV && VIDEO_V4L2 && PLAT_S5P
+        depends on VIDEO_DEV && VIDEO_V4L2 && (PLAT_S5P || ARCH_EXYNOS)
         select VIDEOBUF2_DMA_CONTIG
         select V4L2_MEM2MEM_DEV
         default n
@@ -169,7 +169,7 @@ config VIDEO_SAMSUNG_S5P_G2D
 
 config VIDEO_SAMSUNG_S5P_JPEG
         tristate "Samsung S5P/Exynos4 JPEG codec driver"
-        depends on VIDEO_DEV && VIDEO_V4L2 && PLAT_S5P
+        depends on VIDEO_DEV && VIDEO_V4L2 && (PLAT_S5P || ARCH_EXYNOS)
         select VIDEOBUF2_DMA_CONTIG
         select V4L2_MEM2MEM_DEV
         ---help---
@@ -177,7 +177,7 @@ config VIDEO_SAMSUNG_S5P_JPEG
 
 config VIDEO_SAMSUNG_S5P_MFC
         tristate "Samsung S5P MFC Video Codec"
-        depends on VIDEO_DEV && VIDEO_V4L2 && PLAT_S5P
+        depends on VIDEO_DEV && VIDEO_V4L2 && (PLAT_S5P || ARCH_EXYNOS)
         select VIDEOBUF2_DMA_CONTIG
         default n
         help
diff --git a/drivers/media/platform/exynos4-is/Kconfig b/drivers/media/platform/exynos4-is/Kconfig
index 6ff99b5849f9..004fd0b4e9df 100644
--- a/drivers/media/platform/exynos4-is/Kconfig
+++ b/drivers/media/platform/exynos4-is/Kconfig
@@ -1,7 +1,8 @@
 
 config VIDEO_SAMSUNG_EXYNOS4_IS
         bool "Samsung S5P/EXYNOS4 SoC series Camera Subsystem driver"
-        depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && PLAT_S5P && PM_RUNTIME
+        depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && PM_RUNTIME
+        depends on (PLAT_S5P || ARCH_EXYNOS)
         help
           Say Y here to enable camera host interface devices for
           Samsung S5P and EXYNOS SoC series.
diff --git a/drivers/media/platform/omap/omap_vout.c b/drivers/media/platform/omap/omap_vout.c
index 477268a2415f..d338b19da544 100644
--- a/drivers/media/platform/omap/omap_vout.c
+++ b/drivers/media/platform/omap/omap_vout.c
@@ -2150,6 +2150,9 @@ static int __init omap_vout_probe(struct platform_device *pdev)
         struct omap_dss_device *def_display;
         struct omap2video_device *vid_dev = NULL;
 
+        if (omapdss_is_initialized() == false)
+                return -EPROBE_DEFER;
+
         ret = omapdss_compat_init();
         if (ret) {
                 dev_err(&pdev->dev, "failed to init dss\n");
diff --git a/drivers/media/platform/s5p-tv/Kconfig b/drivers/media/platform/s5p-tv/Kconfig
index 7b659bd09bfd..369a4c191e18 100644
--- a/drivers/media/platform/s5p-tv/Kconfig
+++ b/drivers/media/platform/s5p-tv/Kconfig
@@ -8,7 +8,7 @@
 
 config VIDEO_SAMSUNG_S5P_TV
         bool "Samsung TV driver for S5P platform"
-        depends on PLAT_S5P && PM_RUNTIME
+        depends on (PLAT_S5P || ARCH_EXYNOS) && PM_RUNTIME
         default n
         ---help---
           Say Y here to enable selecting the TV output devices for
diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c
index 962a6e17a01a..1a31512369f9 100644
--- a/drivers/mfd/syscon.c
+++ b/drivers/mfd/syscon.c
@@ -159,6 +159,9 @@ static int syscon_probe(struct platform_device *pdev)
 
 static const struct platform_device_id syscon_ids[] = {
         { "syscon", },
+#ifdef CONFIG_ARCH_CLPS711X
+        { "clps711x-syscon", },
+#endif
         { }
 };
 
diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c
index 713d89fedc46..f580d30bb784 100644
--- a/drivers/misc/mei/init.c
+++ b/drivers/misc/mei/init.c
@@ -197,6 +197,8 @@ void mei_stop(struct mei_device *dev)
 {
         dev_dbg(&dev->pdev->dev, "stopping the device.\n");
 
+        flush_scheduled_work();
+
         mutex_lock(&dev->device_lock);
 
         cancel_delayed_work(&dev->timer_work);
@@ -210,8 +212,6 @@ void mei_stop(struct mei_device *dev)
 
         mutex_unlock(&dev->device_lock);
 
-        flush_scheduled_work();
-
         mei_watchdog_unregister(dev);
 }
 EXPORT_SYMBOL_GPL(mei_stop);
diff --git a/drivers/misc/mei/nfc.c b/drivers/misc/mei/nfc.c
index 3adf8a70f26e..d0c6907dfd92 100644
--- a/drivers/misc/mei/nfc.c
+++ b/drivers/misc/mei/nfc.c
@@ -142,6 +142,8 @@ static void mei_nfc_free(struct mei_nfc_dev *ndev)
                 mei_cl_unlink(ndev->cl_info);
                 kfree(ndev->cl_info);
         }
+
+        memset(ndev, 0, sizeof(struct mei_nfc_dev));
 }
 
 static int mei_nfc_build_bus_name(struct mei_nfc_dev *ndev)
diff --git a/drivers/misc/mei/pci-me.c b/drivers/misc/mei/pci-me.c
index a727464e9c3f..0f268329bd3a 100644
--- a/drivers/misc/mei/pci-me.c
+++ b/drivers/misc/mei/pci-me.c
@@ -325,6 +325,7 @@ static int mei_me_pci_resume(struct device *device)
 
         mutex_lock(&dev->device_lock);
         dev->dev_state = MEI_DEV_POWER_UP;
+        mei_clear_interrupts(dev);
         mei_reset(dev, 1);
         mutex_unlock(&dev->device_lock);
 
diff --git a/drivers/misc/sgi-gru/grufile.c b/drivers/misc/sgi-gru/grufile.c
index 44d273c5e19d..0535d1e0bc78 100644
--- a/drivers/misc/sgi-gru/grufile.c
+++ b/drivers/misc/sgi-gru/grufile.c
@@ -172,6 +172,7 @@ static long gru_get_config_info(unsigned long arg)
                 nodesperblade = 2;
         else
                 nodesperblade = 1;
+        memset(&info, 0, sizeof(info));
         info.cpus = num_online_cpus();
         info.nodes = num_online_nodes();
         info.blades = info.nodes / nodesperblade;
diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index e75774f72606..aca59d93d5a9 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -2230,10 +2230,15 @@ static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
         mmc_free_host(slot->mmc);
 }
 
-static bool atmci_filter(struct dma_chan *chan, void *slave)
+static bool atmci_filter(struct dma_chan *chan, void *pdata)
 {
-        struct mci_dma_data     *sl = slave;
+        struct mci_platform_data *sl_pdata = pdata;
+        struct mci_dma_data *sl;
 
+        if (!sl_pdata)
+                return false;
+
+        sl = sl_pdata->dma_slave;
         if (sl && find_slave_dev(sl) == chan->device->dev) {
                 chan->private = slave_data_ptr(sl);
                 return true;
@@ -2245,24 +2250,18 @@ static bool atmci_filter(struct dma_chan *chan, void *slave)
 static bool atmci_configure_dma(struct atmel_mci *host)
 {
         struct mci_platform_data        *pdata;
+        dma_cap_mask_t mask;
 
         if (host == NULL)
                 return false;
 
         pdata = host->pdev->dev.platform_data;
 
-        if (!pdata)
-                return false;
+        dma_cap_zero(mask);
+        dma_cap_set(DMA_SLAVE, mask);
 
-        if (pdata->dma_slave && find_slave_dev(pdata->dma_slave)) {
-                dma_cap_mask_t mask;
-
-                /* Try to grab a DMA channel */
-                dma_cap_zero(mask);
-                dma_cap_set(DMA_SLAVE, mask);
-                host->dma.chan =
-                        dma_request_channel(mask, atmci_filter, pdata->dma_slave);
-        }
+        host->dma.chan = dma_request_slave_channel_compat(mask, atmci_filter, pdata,
+                                                          &host->pdev->dev, "rxtx");
         if (!host->dma.chan) {
                 dev_warn(&host->pdev->dev, "no DMA channel available\n");
                 return false;
diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c
index 3946a0eb3a03..5dfb70c669dc 100644
--- a/drivers/mmc/host/davinci_mmc.c
+++ b/drivers/mmc/host/davinci_mmc.c
@@ -37,6 +37,7 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 
+#include <linux/platform_data/edma.h>
 #include <linux/platform_data/mmc-davinci.h>
 
 /*
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 6e44025acf01..eccedc7d06a4 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -161,6 +161,7 @@ struct omap_hsmmc_host {
          */
         struct  regulator       *vcc;
         struct  regulator       *vcc_aux;
+        int                     pbias_disable;
         void    __iomem         *base;
         resource_size_t         mapbase;
         spinlock_t              irq_lock; /* Prevent races with irq handler */
@@ -255,11 +256,11 @@ static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
         if (!host->vcc)
                 return 0;
         /*
-         * With DT, never turn OFF the regulator. This is because
+         * With DT, never turn OFF the regulator for MMC1. This is because
          * the pbias cell programming support is still missing when
          * booting with Device tree
          */
-        if (dev->of_node && !vdd)
+        if (host->pbias_disable && !vdd)
                 return 0;
 
         if (mmc_slot(host).before_set_reg)
@@ -1520,10 +1521,10 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
                         (ios->vdd == DUAL_VOLT_OCR_BIT) &&
                         /*
                          * With pbias cell programming missing, this
-                         * can't be allowed when booting with device
+                         * can't be allowed on MMC1 when booting with device
                          * tree.
                          */
-                        !host->dev->of_node) {
+                        !host->pbias_disable) {
                                 /*
                                  * The mmc_select_voltage fn of the core does
                                  * not seem to set the power_mode to
@@ -1871,6 +1872,10 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
 
         omap_hsmmc_context_save(host);
 
+        /* This can be removed once we support PBIAS with DT */
+        if (host->dev->of_node && host->mapbase == 0x4809c000)
+                host->pbias_disable = 1;
+
         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
         /*
          * MMC can still work without debounce clock.
@@ -1906,33 +1911,41 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
 
         omap_hsmmc_conf_bus_power(host);
 
-        res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
-        if (!res) {
-                dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
-                ret = -ENXIO;
-                goto err_irq;
-        }
-        tx_req = res->start;
+        if (!pdev->dev.of_node) {
+                res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
+                if (!res) {
+                        dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
+                        ret = -ENXIO;
+                        goto err_irq;
+                }
+                tx_req = res->start;
 
-        res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
-        if (!res) {
-                dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
-                ret = -ENXIO;
-                goto err_irq;
+                res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
+                if (!res) {
+                        dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
+                        ret = -ENXIO;
+                        goto err_irq;
+                }
+                rx_req = res->start;
         }
-        rx_req = res->start;
 
         dma_cap_zero(mask);
         dma_cap_set(DMA_SLAVE, mask);
 
-        host->rx_chan = dma_request_channel(mask, omap_dma_filter_fn, &rx_req);
+        host->rx_chan =
+                dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
+                                                 &rx_req, &pdev->dev, "rx");
+
         if (!host->rx_chan) {
                 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
                 ret = -ENXIO;
                 goto err_irq;
         }
 
-        host->tx_chan = dma_request_channel(mask, omap_dma_filter_fn, &tx_req);
+        host->tx_chan =
+                dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
+                                                 &tx_req, &pdev->dev, "tx");
+
         if (!host->tx_chan) {
                 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
                 ret = -ENXIO;
diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c
index 7bcf74b1a5cd..706d9cb1a49e 100644
--- a/drivers/mmc/host/sdhci-acpi.c
+++ b/drivers/mmc/host/sdhci-acpi.c
@@ -87,6 +87,12 @@ static const struct sdhci_ops sdhci_acpi_ops_dflt = {
         .enable_dma = sdhci_acpi_enable_dma,
 };
 
+static const struct sdhci_acpi_slot sdhci_acpi_slot_int_emmc = {
+        .caps    = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
+        .caps2   = MMC_CAP2_HC_ERASE_SZ,
+        .flags   = SDHCI_ACPI_RUNTIME_PM,
+};
+
 static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = {
         .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
         .caps    = MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD,
@@ -94,23 +100,67 @@ static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = {
         .pm_caps = MMC_PM_KEEP_POWER,
 };
 
+static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sd = {
+};
+
+struct sdhci_acpi_uid_slot {
+        const char *hid;
+        const char *uid;
+        const struct sdhci_acpi_slot *slot;
+};
+
+static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = {
+        { "80860F14" , "1" , &sdhci_acpi_slot_int_emmc },
+        { "80860F14" , "3" , &sdhci_acpi_slot_int_sd   },
+        { "INT33BB"  , "2" , &sdhci_acpi_slot_int_sdio },
+        { "INT33C6"  , NULL, &sdhci_acpi_slot_int_sdio },
+        { "PNP0D40"  },
+        { },
+};
+
 static const struct acpi_device_id sdhci_acpi_ids[] = {
-        { "INT33C6", (kernel_ulong_t)&sdhci_acpi_slot_int_sdio },
-        { "PNP0D40" },
+        { "80860F14" },
+        { "INT33BB"  },
+        { "INT33C6"  },
+        { "PNP0D40"  },
         { },
 };
 MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);
 
-static const struct sdhci_acpi_slot *sdhci_acpi_get_slot(const char *hid)
+static const struct sdhci_acpi_slot *sdhci_acpi_get_slot_by_ids(const char *hid,
+                                                                const char *uid)
 {
-        const struct acpi_device_id *id;
-
-        for (id = sdhci_acpi_ids; id->id[0]; id++)
-                if (!strcmp(id->id, hid))
-                        return (const struct sdhci_acpi_slot *)id->driver_data;
+        const struct sdhci_acpi_uid_slot *u;
+
+        for (u = sdhci_acpi_uids; u->hid; u++) {
+                if (strcmp(u->hid, hid))
+                        continue;
+                if (!u->uid)
+                        return u->slot;
+                if (uid && !strcmp(u->uid, uid))
+                        return u->slot;
+        }
         return NULL;
 }
 
+static const struct sdhci_acpi_slot *sdhci_acpi_get_slot(acpi_handle handle,
+                                                         const char *hid)
+{
+        const struct sdhci_acpi_slot *slot;
+        struct acpi_device_info *info;
+        const char *uid = NULL;
+        acpi_status status;
+
+        status = acpi_get_object_info(handle, &info);
+        if (!ACPI_FAILURE(status) && (info->valid & ACPI_VALID_UID))
+                uid = info->unique_id.string;
+
+        slot = sdhci_acpi_get_slot_by_ids(hid, uid);
+
+        kfree(info);
+        return slot;
+}
+
 static int sdhci_acpi_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
@@ -148,7 +198,7 @@ static int sdhci_acpi_probe(struct platform_device *pdev)
 
         c = sdhci_priv(host);
         c->host = host;
-        c->slot = sdhci_acpi_get_slot(hid);
+        c->slot = sdhci_acpi_get_slot(handle, hid);
         c->pdev = pdev;
         c->use_runtime_pm = sdhci_acpi_flag(c, SDHCI_ACPI_RUNTIME_PM);
 
@@ -202,6 +252,7 @@ static int sdhci_acpi_probe(struct platform_device *pdev)
                 goto err_free;
 
         if (c->use_runtime_pm) {
+                pm_runtime_set_active(dev);
                 pm_suspend_ignore_children(dev, 1);
                 pm_runtime_set_autosuspend_delay(dev, 50);
                 pm_runtime_use_autosuspend(dev);
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 67d6dde2ff19..d5f0d59e1310 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -85,6 +85,12 @@ struct pltfm_imx_data {
         struct clk *clk_ipg;
         struct clk *clk_ahb;
         struct clk *clk_per;
+        enum {
+                NO_CMD_PENDING,      /* no multiblock command pending*/
+                MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
+                WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
+        } multiblock_status;
+
 };
 
 static struct platform_device_id imx_esdhc_devtype[] = {
@@ -154,6 +160,8 @@ static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, i
 
 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
 {
+        struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+        struct pltfm_imx_data *imx_data = pltfm_host->priv;
         u32 val = readl(host->ioaddr + reg);
 
         if (unlikely(reg == SDHCI_CAPABILITIES)) {
@@ -175,6 +183,18 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
                         val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
                         val |= SDHCI_INT_ADMA_ERROR;
                 }
+
+                /*
+                 * mask off the interrupt we get in response to the manually
+                 * sent CMD12
+                 */
+                if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
+                    ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
+                        val &= ~SDHCI_INT_RESPONSE;
+                        writel(SDHCI_INT_RESPONSE, host->ioaddr +
+                                                   SDHCI_INT_STATUS);
+                        imx_data->multiblock_status = NO_CMD_PENDING;
+                }
         }
 
         return val;
@@ -211,6 +231,15 @@ static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
                         v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
+
+                        if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
+                        {
+                                /* send a manual CMD12 with RESPTYP=none */
+                                data = MMC_STOP_TRANSMISSION << 24 |
+                                       SDHCI_CMD_ABORTCMD << 16;
+                                writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
+                                imx_data->multiblock_status = WAIT_FOR_INT;
+                        }
         }
 
         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
@@ -277,11 +306,13 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
                 }
                 return;
         case SDHCI_COMMAND:
-                if ((host->cmd->opcode == MMC_STOP_TRANSMISSION ||
-                     host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
-                    (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
+                if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
                         val |= SDHCI_CMD_ABORTCMD;
 
+                if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
+                    (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
+                        imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
+
                 if (is_imx6q_usdhc(imx_data))
                         writel(val << 16,
                                host->ioaddr + SDHCI_TRANSFER_MODE);
@@ -324,8 +355,10 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
                 /*
                  * Do not touch buswidth bits here. This is done in
                  * esdhc_pltfm_bus_width.
+                 * Do not touch the D3CD bit either which is used for the
+                 * SDIO interrupt errata workaround.
                  */
-                mask = 0xffff & ~ESDHC_CTRL_BUSWIDTH_MASK;
+                mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
 
                 esdhc_clrset_le(host, mask, new_val, reg);
                 return;
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
index 0012d3fdc999..701d06d0e1fb 100644
--- a/drivers/mmc/host/sdhci-pci.c
+++ b/drivers/mmc/host/sdhci-pci.c
@@ -33,6 +33,9 @@
  */
 #define PCI_DEVICE_ID_INTEL_PCH_SDIO0   0x8809
 #define PCI_DEVICE_ID_INTEL_PCH_SDIO1   0x880a
+#define PCI_DEVICE_ID_INTEL_BYT_EMMC    0x0f14
+#define PCI_DEVICE_ID_INTEL_BYT_SDIO    0x0f15
+#define PCI_DEVICE_ID_INTEL_BYT_SD      0x0f16
 
 /*
  * PCI registers
@@ -304,6 +307,33 @@ static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
         .probe_slot     = pch_hc_probe_slot,
 };
 
+static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
+{
+        slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
+        slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
+        return 0;
+}
+
+static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
+{
+        slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
+        return 0;
+}
+
+static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
+        .allow_runtime_pm = true,
+        .probe_slot     = byt_emmc_probe_slot,
+};
+
+static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
+        .quirks2        = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
+        .allow_runtime_pm = true,
+        .probe_slot     = byt_sdio_probe_slot,
+};
+
+static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
+};
+
 /* O2Micro extra registers */
 #define O2_SD_LOCK_WP           0xD3
 #define O2_SD_MULTI_VCC3V       0xEE
@@ -856,6 +886,30 @@ static const struct pci_device_id pci_ids[] = {
         },
 
         {
+                .vendor         = PCI_VENDOR_ID_INTEL,
+                .device         = PCI_DEVICE_ID_INTEL_BYT_EMMC,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_emmc,
+        },
+
+        {
+                .vendor         = PCI_VENDOR_ID_INTEL,
+                .device         = PCI_DEVICE_ID_INTEL_BYT_SDIO,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sdio,
+        },
+
+        {
+                .vendor         = PCI_VENDOR_ID_INTEL,
+                .device         = PCI_DEVICE_ID_INTEL_BYT_SD,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sd,
+        },
+
+        {
                 .vendor         = PCI_VENDOR_ID_O2,
                 .device         = PCI_DEVICE_ID_O2_8120,
                 .subvendor      = PCI_ANY_ID,
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index bed9d58d5741..8b27ca054c59 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -297,13 +297,6 @@ config MTD_IXP4XX
           IXDP425 and Coyote. If you have an IXP4xx based board and
           would like to use the flash chips on it, say 'Y'.
 
-config MTD_AUTCPU12
-        bool "NV-RAM mapping AUTCPU12 board"
-        depends on ARCH_AUTCPU12
-        help
-          This enables access to the NV-RAM on autronix autcpu12 board.
-          If you have such a board, say 'Y'.
-
 config MTD_IMPA7
         tristate "JEDEC Flash device mapped on impA7"
         depends on ARM && MTD_JEDECPROBE
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
index 395a12444048..9fdbd4ba6441 100644
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -32,7 +32,6 @@ obj-$(CONFIG_MTD_VMAX)		+= vmax301.o
 obj-$(CONFIG_MTD_SCx200_DOCFLASH)+= scx200_docflash.o
 obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o
 obj-$(CONFIG_MTD_PCI)           += pci.o
-obj-$(CONFIG_MTD_AUTCPU12)      += autcpu12-nvram.o
 obj-$(CONFIG_MTD_IMPA7)         += impa7.o
 obj-$(CONFIG_MTD_UCLINUX)       += uclinux.o
 obj-$(CONFIG_MTD_NETtel)        += nettel.o
diff --git a/drivers/mtd/maps/autcpu12-nvram.c b/drivers/mtd/maps/autcpu12-nvram.c
deleted file mode 100644
index c3525d2a2fa8..000000000000
--- a/drivers/mtd/maps/autcpu12-nvram.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * NV-RAM memory access on autcpu12
- * (C) 2002 Thomas Gleixner (gleixner@autronix.de)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/err.h>
-#include <linux/sizes.h>
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-
-struct autcpu12_nvram_priv {
-        struct mtd_info *mtd;
-        struct map_info map;
-};
-
-static int autcpu12_nvram_probe(struct platform_device *pdev)
-{
-        map_word tmp, save0, save1;
-        struct resource *res;
-        struct autcpu12_nvram_priv *priv;
-
-        priv = devm_kzalloc(&pdev->dev,
-                            sizeof(struct autcpu12_nvram_priv), GFP_KERNEL);
-        if (!priv)
-                return -ENOMEM;
-
-        platform_set_drvdata(pdev, priv);
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res) {
-                dev_err(&pdev->dev, "failed to get memory resource\n");
-                return -ENOENT;
-        }
-
-        priv->map.bankwidth     = 4;
-        priv->map.phys          = res->start;
-        priv->map.size          = resource_size(res);
-        priv->map.virt = devm_ioremap_resource(&pdev->dev, res);
-        strcpy((char *)priv->map.name, res->name);
-        if (IS_ERR(priv->map.virt))
-                return PTR_ERR(priv->map.virt);
-
-        simple_map_init(&priv->map);
-
-        /*
-         * Check for 32K/128K
-         * read ofs 0
-         * read ofs 0x10000
-         * Write complement to ofs 0x100000
-         * Read and check result on ofs 0x0
-         * Restore contents
-         */
-        save0 = map_read(&priv->map, 0);
-        save1 = map_read(&priv->map, 0x10000);
-        tmp.x[0] = ~save0.x[0];
-        map_write(&priv->map, tmp, 0x10000);
-        tmp = map_read(&priv->map, 0);
-        /* if we find this pattern on 0x0, we have 32K size */
-        if (!map_word_equal(&priv->map, tmp, save0)) {
-                map_write(&priv->map, save0, 0x0);
-                priv->map.size = SZ_32K;
-        } else
-                map_write(&priv->map, save1, 0x10000);
-
-        priv->mtd = do_map_probe("map_ram", &priv->map);
-        if (!priv->mtd) {
-                dev_err(&pdev->dev, "probing failed\n");
-                return -ENXIO;
-        }
-
-        priv->mtd->owner        = THIS_MODULE;
-        priv->mtd->erasesize    = 16;
-        priv->mtd->dev.parent   = &pdev->dev;
-        if (!mtd_device_register(priv->mtd, NULL, 0)) {
-                dev_info(&pdev->dev,
-                         "NV-RAM device size %ldKiB registered on AUTCPU12\n",
-                         priv->map.size / SZ_1K);
-                return 0;
-        }
-
-        map_destroy(priv->mtd);
-        dev_err(&pdev->dev, "NV-RAM device addition failed\n");
-        return -ENOMEM;
-}
-
-static int autcpu12_nvram_remove(struct platform_device *pdev)
-{
-        struct autcpu12_nvram_priv *priv = platform_get_drvdata(pdev);
-
-        mtd_device_unregister(priv->mtd);
-        map_destroy(priv->mtd);
-
-        return 0;
-}
-
-static struct platform_driver autcpu12_nvram_driver = {
-        .driver         = {
-                .name   = "autcpu12_nvram",
-                .owner  = THIS_MODULE,
-        },
-        .probe          = autcpu12_nvram_probe,
-        .remove         = autcpu12_nvram_remove,
-};
-module_platform_driver(autcpu12_nvram_driver);
-
-MODULE_AUTHOR("Thomas Gleixner");
-MODULE_DESCRIPTION("autcpu12 NVRAM map driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index 29b846cbfb48..02d9ae7d527e 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/drivers/net/bonding/bond_main.c
@@ -764,8 +764,8 @@ static void bond_resend_igmp_join_requests(struct bonding *bond)
         struct net_device *bond_dev, *vlan_dev, *upper_dev;
         struct vlan_entry *vlan;
 
-        rcu_read_lock();
         read_lock(&bond->lock);
+        rcu_read_lock();
 
         bond_dev = bond->dev;
 
@@ -787,12 +787,19 @@ static void bond_resend_igmp_join_requests(struct bonding *bond)
                 if (vlan_dev)
                         __bond_resend_igmp_join_requests(vlan_dev);
         }
+        rcu_read_unlock();
 
-        if (--bond->igmp_retrans > 0)
+        /* We use curr_slave_lock to protect against concurrent access to
+         * igmp_retrans from multiple running instances of this function and
+         * bond_change_active_slave
+         */
+        write_lock_bh(&bond->curr_slave_lock);
+        if (bond->igmp_retrans > 1) {
+                bond->igmp_retrans--;
                 queue_delayed_work(bond->wq, &bond->mcast_work, HZ/5);
-
+        }
+        write_unlock_bh(&bond->curr_slave_lock);
         read_unlock(&bond->lock);
-        rcu_read_unlock();
 }
 
 static void bond_resend_igmp_join_requests_delayed(struct work_struct *work)
@@ -1957,6 +1964,10 @@ err_free:
 
 err_undo_flags:
         bond_compute_features(bond);
+        /* Enslave of first slave has failed and we need to fix master's mac */
+        if (bond->slave_cnt == 0 &&
+            ether_addr_equal(bond_dev->dev_addr, slave_dev->dev_addr))
+                eth_hw_addr_random(bond_dev);
 
         return res;
 }
diff --git a/drivers/net/bonding/bonding.h b/drivers/net/bonding/bonding.h
index 2baec24388b1..f989e1529a29 100644
--- a/drivers/net/bonding/bonding.h
+++ b/drivers/net/bonding/bonding.h
@@ -225,7 +225,7 @@ struct bonding {
         rwlock_t curr_slave_lock;
         u8       send_peer_notif;
         s8       setup_by_slave;
-        s8       igmp_retrans;
+        u8       igmp_retrans;
 #ifdef CONFIG_PROC_FS
         struct   proc_dir_entry *proc_entry;
         char     proc_file_name[IFNAMSIZ];
diff --git a/drivers/net/can/usb/esd_usb2.c b/drivers/net/can/usb/esd_usb2.c
index 9b74d1e3ad44..6aa7b3266c80 100644
--- a/drivers/net/can/usb/esd_usb2.c
+++ b/drivers/net/can/usb/esd_usb2.c
@@ -612,9 +612,15 @@ static int esd_usb2_start(struct esd_usb2_net_priv *priv)
 {
         struct esd_usb2 *dev = priv->usb2;
         struct net_device *netdev = priv->netdev;
-        struct esd_usb2_msg msg;
+        struct esd_usb2_msg *msg;
         int err, i;
 
+        msg = kmalloc(sizeof(*msg), GFP_KERNEL);
+        if (!msg) {
+                err = -ENOMEM;
+                goto out;
+        }
+
         /*
          * Enable all IDs
          * The IDADD message takes up to 64 32 bit bitmasks (2048 bits).
@@ -628,33 +634,32 @@ static int esd_usb2_start(struct esd_usb2_net_priv *priv)
          * the number of the starting bitmask (0..64) to the filter.option
          * field followed by only some bitmasks.
          */
-        msg.msg.hdr.cmd = CMD_IDADD;
-        msg.msg.hdr.len = 2 + ESD_MAX_ID_SEGMENT;
-        msg.msg.filter.net = priv->index;
-        msg.msg.filter.option = ESD_ID_ENABLE; /* start with segment 0 */
+        msg->msg.hdr.cmd = CMD_IDADD;
+        msg->msg.hdr.len = 2 + ESD_MAX_ID_SEGMENT;
+        msg->msg.filter.net = priv->index;
+        msg->msg.filter.option = ESD_ID_ENABLE; /* start with segment 0 */
         for (i = 0; i < ESD_MAX_ID_SEGMENT; i++)
-                msg.msg.filter.mask[i] = cpu_to_le32(0xffffffff);
+                msg->msg.filter.mask[i] = cpu_to_le32(0xffffffff);
         /* enable 29bit extended IDs */
-        msg.msg.filter.mask[ESD_MAX_ID_SEGMENT] = cpu_to_le32(0x00000001);
+        msg->msg.filter.mask[ESD_MAX_ID_SEGMENT] = cpu_to_le32(0x00000001);
 
-        err = esd_usb2_send_msg(dev, &msg);
+        err = esd_usb2_send_msg(dev, msg);
         if (err)
-                goto failed;
+                goto out;
 
         err = esd_usb2_setup_rx_urbs(dev);
         if (err)
-                goto failed;
+                goto out;
 
         priv->can.state = CAN_STATE_ERROR_ACTIVE;
 
-        return 0;
-
-failed:
+out:
         if (err == -ENODEV)
                 netif_device_detach(netdev);
+        if (err)
+                netdev_err(netdev, "couldn't start device: %d\n", err);
 
-        netdev_err(netdev, "couldn't start device: %d\n", err);
-
+        kfree(msg);
         return err;
 }
 
@@ -833,26 +838,30 @@ nourbmem:
 static int esd_usb2_close(struct net_device *netdev)
 {
         struct esd_usb2_net_priv *priv = netdev_priv(netdev);
-        struct esd_usb2_msg msg;
+        struct esd_usb2_msg *msg;
         int i;
 
+        msg = kmalloc(sizeof(*msg), GFP_KERNEL);
+        if (!msg)
+                return -ENOMEM;
+
         /* Disable all IDs (see esd_usb2_start()) */
-        msg.msg.hdr.cmd = CMD_IDADD;
-        msg.msg.hdr.len = 2 + ESD_MAX_ID_SEGMENT;
-        msg.msg.filter.net = priv->index;
-        msg.msg.filter.option = ESD_ID_ENABLE; /* start with segment 0 */
+        msg->msg.hdr.cmd = CMD_IDADD;
+        msg->msg.hdr.len = 2 + ESD_MAX_ID_SEGMENT;
+        msg->msg.filter.net = priv->index;
+        msg->msg.filter.option = ESD_ID_ENABLE; /* start with segment 0 */
         for (i = 0; i <= ESD_MAX_ID_SEGMENT; i++)
-                msg.msg.filter.mask[i] = 0;
-        if (esd_usb2_send_msg(priv->usb2, &msg) < 0)
+                msg->msg.filter.mask[i] = 0;
+        if (esd_usb2_send_msg(priv->usb2, msg) < 0)
                 netdev_err(netdev, "sending idadd message failed\n");
 
         /* set CAN controller to reset mode */
-        msg.msg.hdr.len = 2;
-        msg.msg.hdr.cmd = CMD_SETBAUD;
-        msg.msg.setbaud.net = priv->index;
-        msg.msg.setbaud.rsvd = 0;
-        msg.msg.setbaud.baud = cpu_to_le32(ESD_USB2_NO_BAUDRATE);
-        if (esd_usb2_send_msg(priv->usb2, &msg) < 0)
+        msg->msg.hdr.len = 2;
+        msg->msg.hdr.cmd = CMD_SETBAUD;
+        msg->msg.setbaud.net = priv->index;
+        msg->msg.setbaud.rsvd = 0;
+        msg->msg.setbaud.baud = cpu_to_le32(ESD_USB2_NO_BAUDRATE);
+        if (esd_usb2_send_msg(priv->usb2, msg) < 0)
                 netdev_err(netdev, "sending setbaud message failed\n");
 
         priv->can.state = CAN_STATE_STOPPED;
@@ -861,6 +870,8 @@ static int esd_usb2_close(struct net_device *netdev)
 
         close_candev(netdev);
 
+        kfree(msg);
+
         return 0;
 }
 
@@ -886,7 +897,8 @@ static int esd_usb2_set_bittiming(struct net_device *netdev)
 {
         struct esd_usb2_net_priv *priv = netdev_priv(netdev);
         struct can_bittiming *bt = &priv->can.bittiming;
-        struct esd_usb2_msg msg;
+        struct esd_usb2_msg *msg;
+        int err;
         u32 canbtr;
         int sjw_shift;
 
@@ -912,15 +924,22 @@ static int esd_usb2_set_bittiming(struct net_device *netdev)
         if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
                 canbtr |= ESD_USB2_3_SAMPLES;
 
-        msg.msg.hdr.len = 2;
-        msg.msg.hdr.cmd = CMD_SETBAUD;
-        msg.msg.setbaud.net = priv->index;
-        msg.msg.setbaud.rsvd = 0;
-        msg.msg.setbaud.baud = cpu_to_le32(canbtr);
+        msg = kmalloc(sizeof(*msg), GFP_KERNEL);
+        if (!msg)
+                return -ENOMEM;
+
+        msg->msg.hdr.len = 2;
+        msg->msg.hdr.cmd = CMD_SETBAUD;
+        msg->msg.setbaud.net = priv->index;
+        msg->msg.setbaud.rsvd = 0;
+        msg->msg.setbaud.baud = cpu_to_le32(canbtr);
 
         netdev_info(netdev, "setting BTR=%#x\n", canbtr);
 
-        return esd_usb2_send_msg(priv->usb2, &msg);
+        err = esd_usb2_send_msg(priv->usb2, msg);
+
+        kfree(msg);
+        return err;
 }
 
 static int esd_usb2_get_berr_counter(const struct net_device *netdev,
@@ -1022,7 +1041,7 @@ static int esd_usb2_probe(struct usb_interface *intf,
                          const struct usb_device_id *id)
 {
         struct esd_usb2 *dev;
-        struct esd_usb2_msg msg;
+        struct esd_usb2_msg *msg;
         int i, err;
 
         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
@@ -1037,27 +1056,33 @@ static int esd_usb2_probe(struct usb_interface *intf,
 
         usb_set_intfdata(intf, dev);
 
+        msg = kmalloc(sizeof(*msg), GFP_KERNEL);
+        if (!msg) {
+                err = -ENOMEM;
+                goto free_msg;
+        }
+
         /* query number of CAN interfaces (nets) */
-        msg.msg.hdr.cmd = CMD_VERSION;
-        msg.msg.hdr.len = 2;
-        msg.msg.version.rsvd = 0;
-        msg.msg.version.flags = 0;
-        msg.msg.version.drv_version = 0;
+        msg->msg.hdr.cmd = CMD_VERSION;
+        msg->msg.hdr.len = 2;
+        msg->msg.version.rsvd = 0;
+        msg->msg.version.flags = 0;
+        msg->msg.version.drv_version = 0;
 
-        err = esd_usb2_send_msg(dev, &msg);
+        err = esd_usb2_send_msg(dev, msg);
         if (err < 0) {
                 dev_err(&intf->dev, "sending version message failed\n");
-                goto free_dev;
+                goto free_msg;
         }
 
-        err = esd_usb2_wait_msg(dev, &msg);
+        err = esd_usb2_wait_msg(dev, msg);
         if (err < 0) {
                 dev_err(&intf->dev, "no version message answer\n");
-                goto free_dev;
+                goto free_msg;
         }
 
-        dev->net_count = (int)msg.msg.version_reply.nets;
-        dev->version = le32_to_cpu(msg.msg.version_reply.version);
+        dev->net_count = (int)msg->msg.version_reply.nets;
+        dev->version = le32_to_cpu(msg->msg.version_reply.version);
 
         if (device_create_file(&intf->dev, &dev_attr_firmware))
                 dev_err(&intf->dev,
@@ -1075,10 +1100,10 @@ static int esd_usb2_probe(struct usb_interface *intf,
         for (i = 0; i < dev->net_count; i++)
                 esd_usb2_probe_one_net(intf, i);
 
-        return 0;
-
-free_dev:
-        kfree(dev);
+free_msg:
+        kfree(msg);
+        if (err)
+                kfree(dev);
 done:
         return err;
 }
diff --git a/drivers/net/can/usb/kvaser_usb.c b/drivers/net/can/usb/kvaser_usb.c
index 45cb9f3c1324..3b9546588240 100644
--- a/drivers/net/can/usb/kvaser_usb.c
+++ b/drivers/net/can/usb/kvaser_usb.c
@@ -136,6 +136,9 @@
 #define KVASER_CTRL_MODE_SELFRECEPTION  3
 #define KVASER_CTRL_MODE_OFF            4
 
+/* log message */
+#define KVASER_EXTENDED_FRAME           BIT(31)
+
 struct kvaser_msg_simple {
         u8 tid;
         u8 channel;
@@ -817,8 +820,13 @@ static void kvaser_usb_rx_can_msg(const struct kvaser_usb *dev,
         priv = dev->nets[channel];
         stats = &priv->netdev->stats;
 
-        if (msg->u.rx_can.flag & (MSG_FLAG_ERROR_FRAME | MSG_FLAG_NERR |
-                                  MSG_FLAG_OVERRUN)) {
+        if ((msg->u.rx_can.flag & MSG_FLAG_ERROR_FRAME) &&
+            (msg->id == CMD_LOG_MESSAGE)) {
+                kvaser_usb_rx_error(dev, msg);
+                return;
+        } else if (msg->u.rx_can.flag & (MSG_FLAG_ERROR_FRAME |
+                                         MSG_FLAG_NERR |
+                                         MSG_FLAG_OVERRUN)) {
                 kvaser_usb_rx_can_err(priv, msg);
                 return;
         } else if (msg->u.rx_can.flag & ~MSG_FLAG_REMOTE_FRAME) {
@@ -834,22 +842,40 @@ static void kvaser_usb_rx_can_msg(const struct kvaser_usb *dev,
                 return;
         }
 
-        cf->can_id = ((msg->u.rx_can.msg[0] & 0x1f) << 6) |
-                     (msg->u.rx_can.msg[1] & 0x3f);
-        cf->can_dlc = get_can_dlc(msg->u.rx_can.msg[5]);
+        if (msg->id == CMD_LOG_MESSAGE) {
+                cf->can_id = le32_to_cpu(msg->u.log_message.id);
+                if (cf->can_id & KVASER_EXTENDED_FRAME)
+                        cf->can_id &= CAN_EFF_MASK | CAN_EFF_FLAG;
+                else
+                        cf->can_id &= CAN_SFF_MASK;
 
-        if (msg->id == CMD_RX_EXT_MESSAGE) {
-                cf->can_id <<= 18;
-                cf->can_id |= ((msg->u.rx_can.msg[2] & 0x0f) << 14) |
-                              ((msg->u.rx_can.msg[3] & 0xff) << 6) |
-                              (msg->u.rx_can.msg[4] & 0x3f);
-                cf->can_id |= CAN_EFF_FLAG;
-        }
+                cf->can_dlc = get_can_dlc(msg->u.log_message.dlc);
 
-        if (msg->u.rx_can.flag & MSG_FLAG_REMOTE_FRAME)
-                cf->can_id |= CAN_RTR_FLAG;
-        else
-                memcpy(cf->data, &msg->u.rx_can.msg[6], cf->can_dlc);
+                if (msg->u.log_message.flags & MSG_FLAG_REMOTE_FRAME)
+                        cf->can_id |= CAN_RTR_FLAG;
+                else
+                        memcpy(cf->data, &msg->u.log_message.data,
+                               cf->can_dlc);
+        } else {
+                cf->can_id = ((msg->u.rx_can.msg[0] & 0x1f) << 6) |
+                             (msg->u.rx_can.msg[1] & 0x3f);
+
+                if (msg->id == CMD_RX_EXT_MESSAGE) {
+                        cf->can_id <<= 18;
+                        cf->can_id |= ((msg->u.rx_can.msg[2] & 0x0f) << 14) |
+                                      ((msg->u.rx_can.msg[3] & 0xff) << 6) |
+                                      (msg->u.rx_can.msg[4] & 0x3f);
+                        cf->can_id |= CAN_EFF_FLAG;
+                }
+
+                cf->can_dlc = get_can_dlc(msg->u.rx_can.msg[5]);
+
+                if (msg->u.rx_can.flag & MSG_FLAG_REMOTE_FRAME)
+                        cf->can_id |= CAN_RTR_FLAG;
+                else
+                        memcpy(cf->data, &msg->u.rx_can.msg[6],
+                               cf->can_dlc);
+        }
 
         netif_rx(skb);
 
@@ -911,6 +937,7 @@ static void kvaser_usb_handle_message(const struct kvaser_usb *dev,
 
         case CMD_RX_STD_MESSAGE:
         case CMD_RX_EXT_MESSAGE:
+        case CMD_LOG_MESSAGE:
                 kvaser_usb_rx_can_msg(dev, msg);
                 break;
 
@@ -919,11 +946,6 @@ static void kvaser_usb_handle_message(const struct kvaser_usb *dev,
                 kvaser_usb_rx_error(dev, msg);
                 break;
 
-        case CMD_LOG_MESSAGE:
-                if (msg->u.log_message.flags & MSG_FLAG_ERROR_FRAME)
-                        kvaser_usb_rx_error(dev, msg);
-                break;
-
         case CMD_TX_ACKNOWLEDGE:
                 kvaser_usb_tx_acknowledge(dev, msg);
                 break;
diff --git a/drivers/net/can/usb/peak_usb/pcan_usb_pro.c b/drivers/net/can/usb/peak_usb/pcan_usb_pro.c
index 30d79bfa5b10..8ee9d1556e6e 100644
--- a/drivers/net/can/usb/peak_usb/pcan_usb_pro.c
+++ b/drivers/net/can/usb/peak_usb/pcan_usb_pro.c
@@ -504,15 +504,24 @@ static int pcan_usb_pro_restart_async(struct peak_usb_device *dev,
         return usb_submit_urb(urb, GFP_ATOMIC);
 }
 
-static void pcan_usb_pro_drv_loaded(struct peak_usb_device *dev, int loaded)
+static int pcan_usb_pro_drv_loaded(struct peak_usb_device *dev, int loaded)
 {
-        u8 buffer[16];
+        u8 *buffer;
+        int err;
+
+        buffer = kmalloc(PCAN_USBPRO_FCT_DRVLD_REQ_LEN, GFP_KERNEL);
+        if (!buffer)
+                return -ENOMEM;
 
         buffer[0] = 0;
         buffer[1] = !!loaded;
 
-        pcan_usb_pro_send_req(dev, PCAN_USBPRO_REQ_FCT,
-                              PCAN_USBPRO_FCT_DRVLD, buffer, sizeof(buffer));
+        err = pcan_usb_pro_send_req(dev, PCAN_USBPRO_REQ_FCT,
+                                    PCAN_USBPRO_FCT_DRVLD, buffer,
+                                    PCAN_USBPRO_FCT_DRVLD_REQ_LEN);
+        kfree(buffer);
+
+        return err;
 }
 
 static inline
@@ -851,21 +860,24 @@ static int pcan_usb_pro_stop(struct peak_usb_device *dev)
  */
 static int pcan_usb_pro_init(struct peak_usb_device *dev)
 {
-        struct pcan_usb_pro_interface *usb_if;
         struct pcan_usb_pro_device *pdev =
                         container_of(dev, struct pcan_usb_pro_device, dev);
+        struct pcan_usb_pro_interface *usb_if = NULL;
+        struct pcan_usb_pro_fwinfo *fi = NULL;
+        struct pcan_usb_pro_blinfo *bi = NULL;
+        int err;
 
         /* do this for 1st channel only */
         if (!dev->prev_siblings) {
-                struct pcan_usb_pro_fwinfo fi;
-                struct pcan_usb_pro_blinfo bi;
-                int err;
-
                 /* allocate netdevices common structure attached to first one */
                 usb_if = kzalloc(sizeof(struct pcan_usb_pro_interface),
                                  GFP_KERNEL);
-                if (!usb_if)
-                        return -ENOMEM;
+                fi = kmalloc(sizeof(struct pcan_usb_pro_fwinfo), GFP_KERNEL);
+                bi = kmalloc(sizeof(struct pcan_usb_pro_blinfo), GFP_KERNEL);
+                if (!usb_if || !fi || !bi) {
+                        err = -ENOMEM;
+                        goto err_out;
+                }
 
                 /* number of ts msgs to ignore before taking one into account */
                 usb_if->cm_ignore_count = 5;
@@ -877,34 +889,34 @@ static int pcan_usb_pro_init(struct peak_usb_device *dev)
                  */
                 err = pcan_usb_pro_send_req(dev, PCAN_USBPRO_REQ_INFO,
                                             PCAN_USBPRO_INFO_FW,
-                                            &fi, sizeof(fi));
+                                            fi, sizeof(*fi));
                 if (err) {
-                        kfree(usb_if);
                         dev_err(dev->netdev->dev.parent,
                                 "unable to read %s firmware info (err %d)\n",
                                 pcan_usb_pro.name, err);
-                        return err;
+                        goto err_out;
                 }
 
                 err = pcan_usb_pro_send_req(dev, PCAN_USBPRO_REQ_INFO,
                                             PCAN_USBPRO_INFO_BL,
-                                            &bi, sizeof(bi));
+                                            bi, sizeof(*bi));
                 if (err) {
-                        kfree(usb_if);
                         dev_err(dev->netdev->dev.parent,
                                 "unable to read %s bootloader info (err %d)\n",
                                 pcan_usb_pro.name, err);
-                        return err;
+                        goto err_out;
                 }
 
+                /* tell the device the can driver is running */
+                err = pcan_usb_pro_drv_loaded(dev, 1);
+                if (err)
+                        goto err_out;
+
                 dev_info(dev->netdev->dev.parent,
                      "PEAK-System %s hwrev %u serial %08X.%08X (%u channels)\n",
                      pcan_usb_pro.name,
-                     bi.hw_rev, bi.serial_num_hi, bi.serial_num_lo,
+                     bi->hw_rev, bi->serial_num_hi, bi->serial_num_lo,
                      pcan_usb_pro.ctrl_count);
-
-                /* tell the device the can driver is running */
-                pcan_usb_pro_drv_loaded(dev, 1);
         } else {
                 usb_if = pcan_usb_pro_dev_if(dev->prev_siblings);
         }
@@ -916,6 +928,13 @@ static int pcan_usb_pro_init(struct peak_usb_device *dev)
         pcan_usb_pro_set_led(dev, 0, 1);
 
         return 0;
+
+ err_out:
+        kfree(bi);
+        kfree(fi);
+        kfree(usb_if);
+
+        return err;
 }
 
 static void pcan_usb_pro_exit(struct peak_usb_device *dev)
diff --git a/drivers/net/can/usb/peak_usb/pcan_usb_pro.h b/drivers/net/can/usb/peak_usb/pcan_usb_pro.h
index a869918c5620..32275af547e0 100644
--- a/drivers/net/can/usb/peak_usb/pcan_usb_pro.h
+++ b/drivers/net/can/usb/peak_usb/pcan_usb_pro.h
@@ -29,6 +29,7 @@
 
 /* Vendor Request value for XXX_FCT */
 #define PCAN_USBPRO_FCT_DRVLD           5 /* tell device driver is loaded */
+#define PCAN_USBPRO_FCT_DRVLD_REQ_LEN   16
 
 /* PCAN_USBPRO_INFO_BL vendor request record type */
 struct __packed pcan_usb_pro_blinfo {
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
index be59ec4b2c30..638e55435b04 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
@@ -3192,11 +3192,11 @@ static u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
                 rc |= XMIT_CSUM_TCP;
 
         if (skb_is_gso_v6(skb)) {
-                rc |= (XMIT_GSO_V6 | XMIT_CSUM_TCP | XMIT_CSUM_V6);
+                rc |= (XMIT_GSO_V6 | XMIT_CSUM_TCP);
                 if (rc & XMIT_CSUM_ENC)
                         rc |= XMIT_GSO_ENC_V6;
         } else if (skb_is_gso(skb)) {
-                rc |= (XMIT_GSO_V4 | XMIT_CSUM_V4 | XMIT_CSUM_TCP);
+                rc |= (XMIT_GSO_V4 | XMIT_CSUM_TCP);
                 if (rc & XMIT_CSUM_ENC)
                         rc |= XMIT_GSO_ENC_V4;
         }
@@ -3483,19 +3483,18 @@ static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb,
 {
         u16 hlen_w = 0;
         u8 outerip_off, outerip_len = 0;
+
         /* from outer IP to transport */
         hlen_w = (skb_inner_transport_header(skb) -
                   skb_network_header(skb)) >> 1;
 
         /* transport len */
-        if (xmit_type & XMIT_CSUM_TCP)
-                hlen_w += inner_tcp_hdrlen(skb) >> 1;
-        else
-                hlen_w += sizeof(struct udphdr) >> 1;
+        hlen_w += inner_tcp_hdrlen(skb) >> 1;
 
         pbd2->fw_ip_hdr_to_payload_w = hlen_w;
 
-        if (xmit_type & XMIT_CSUM_ENC_V4) {
+        /* outer IP header info */
+        if (xmit_type & XMIT_CSUM_V4) {
                 struct iphdr *iph = ip_hdr(skb);
                 pbd2->fw_ip_csum_wo_len_flags_frag =
                         bswab16(csum_fold((~iph->check) -
@@ -3818,8 +3817,7 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
                         bnx2x_set_pbd_gso_e2(skb, &pbd_e2_parsing_data,
                                              xmit_type);
                 else
-                        bnx2x_set_pbd_gso(skb, pbd_e1x, tx_start_bd,
-                                          xmit_type);
+                        bnx2x_set_pbd_gso(skb, pbd_e1x, first_bd, xmit_type);
         }
 
         /* Set the PBD's parsing_data field if not zero
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 1f2dd928888a..c777b9013164 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -1800,6 +1800,9 @@ static int tg3_poll_fw(struct tg3 *tp)
         int i;
         u32 val;
 
+        if (tg3_flag(tp, NO_FWARE_REPORTED))
+                return 0;
+
         if (tg3_flag(tp, IS_SSB_CORE)) {
                 /* We don't use firmware. */
                 return 0;
@@ -9468,6 +9471,14 @@ static void tg3_rss_write_indir_tbl(struct tg3 *tp)
         }
 }
 
+static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
+{
+        if (tg3_asic_rev(tp) == ASIC_REV_5719)
+                return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
+        else
+                return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
+}
+
 /* tp->lock is held. */
 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
 {
@@ -10153,16 +10164,17 @@ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
         tw32_f(RDMAC_MODE, rdmac_mode);
         udelay(40);
 
-        if (tg3_asic_rev(tp) == ASIC_REV_5719) {
+        if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
+            tg3_asic_rev(tp) == ASIC_REV_5720) {
                 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
                         if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
                                 break;
                 }
                 if (i < TG3_NUM_RDMA_CHANNELS) {
                         val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
-                        val |= TG3_LSO_RD_DMA_TX_LENGTH_WA;
+                        val |= tg3_lso_rd_dma_workaround_bit(tp);
                         tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
-                        tg3_flag_set(tp, 5719_RDMA_BUG);
+                        tg3_flag_set(tp, 5719_5720_RDMA_BUG);
                 }
         }
 
@@ -10395,6 +10407,13 @@ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
  */
 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
 {
+        /* Chip may have been just powered on. If so, the boot code may still
+         * be running initialization. Wait for it to finish to avoid races in
+         * accessing the hardware.
+         */
+        tg3_enable_register_access(tp);
+        tg3_poll_fw(tp);
+
         tg3_switch_clocks(tp);
 
         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
@@ -10526,15 +10545,15 @@ static void tg3_periodic_fetch_stats(struct tg3 *tp)
         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
-        if (unlikely(tg3_flag(tp, 5719_RDMA_BUG) &&
+        if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
                      (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
                       sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
                 u32 val;
 
                 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
-                val &= ~TG3_LSO_RD_DMA_TX_LENGTH_WA;
+                val &= ~tg3_lso_rd_dma_workaround_bit(tp);
                 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
-                tg3_flag_clear(tp, 5719_RDMA_BUG);
+                tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
         }
 
         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h
index 9b2d3ac2474a..ff6e30eeae35 100644
--- a/drivers/net/ethernet/broadcom/tg3.h
+++ b/drivers/net/ethernet/broadcom/tg3.h
@@ -1422,7 +1422,8 @@
 #define TG3_LSO_RD_DMA_CRPTEN_CTRL      0x00004910
 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K    0x00030000
 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K   0x000c0000
-#define TG3_LSO_RD_DMA_TX_LENGTH_WA      0x02000000
+#define TG3_LSO_RD_DMA_TX_LENGTH_WA_5719         0x02000000
+#define TG3_LSO_RD_DMA_TX_LENGTH_WA_5720         0x00200000
 /* 0x4914 --> 0x4be0 unused */
 
 #define TG3_NUM_RDMA_CHANNELS           4
@@ -3059,7 +3060,7 @@ enum TG3_FLAGS {
         TG3_FLAG_APE_HAS_NCSI,
         TG3_FLAG_TX_TSTAMP_EN,
         TG3_FLAG_4K_FIFO_LIMIT,
-        TG3_FLAG_5719_RDMA_BUG,
+        TG3_FLAG_5719_5720_RDMA_BUG,
         TG3_FLAG_RESET_TASK_PENDING,
         TG3_FLAG_PTP_CAPABLE,
         TG3_FLAG_5705_PLUS,
diff --git a/drivers/net/ethernet/dec/tulip/interrupt.c b/drivers/net/ethernet/dec/tulip/interrupt.c
index 28a5e425fecf..92306b320840 100644
--- a/drivers/net/ethernet/dec/tulip/interrupt.c
+++ b/drivers/net/ethernet/dec/tulip/interrupt.c
@@ -76,6 +76,12 @@ int tulip_refill_rx(struct net_device *dev)
 
                         mapping = pci_map_single(tp->pdev, skb->data, PKT_BUF_SZ,
                                                  PCI_DMA_FROMDEVICE);
+                        if (dma_mapping_error(&tp->pdev->dev, mapping)) {
+                                dev_kfree_skb(skb);
+                                tp->rx_buffers[entry].skb = NULL;
+                                break;
+                        }
+
                         tp->rx_buffers[entry].mapping = mapping;
 
                         tp->rx_ring[entry].buffer1 = cpu_to_le32(mapping);
diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h
index f544b297c9ab..0a510684e468 100644
--- a/drivers/net/ethernet/emulex/benet/be.h
+++ b/drivers/net/ethernet/emulex/benet/be.h
@@ -262,6 +262,7 @@ struct be_rx_compl_info {
         u8 ipv6;
         u8 vtm;
         u8 pkt_type;
+        u8 ip_frag;
 };
 
 struct be_rx_obj {
diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c
index a236ecd27cf3..1db2df61b8af 100644
--- a/drivers/net/ethernet/emulex/benet/be_cmds.c
+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c
@@ -562,7 +562,7 @@ int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
 
         resource_error = lancer_provisioning_error(adapter);
         if (resource_error)
-                return -1;
+                return -EAGAIN;
 
         status = lancer_wait_ready(adapter);
         if (!status) {
@@ -590,8 +590,8 @@ int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
          * when PF provisions resources.
          */
         resource_error = lancer_provisioning_error(adapter);
-        if (status == -1 && !resource_error)
-                adapter->eeh_error = true;
+        if (resource_error)
+                status = -EAGAIN;
 
         return status;
 }
diff --git a/drivers/net/ethernet/emulex/benet/be_hw.h b/drivers/net/ethernet/emulex/benet/be_hw.h
index 3c1099b47f2a..8780183c6d1c 100644
--- a/drivers/net/ethernet/emulex/benet/be_hw.h
+++ b/drivers/net/ethernet/emulex/benet/be_hw.h
@@ -356,7 +356,7 @@ struct amap_eth_rx_compl_v0 {
         u8 ip_version;          /* dword 1 */
         u8 macdst[6];           /* dword 1 */
         u8 vtp;                 /* dword 1 */
-        u8 rsvd0;               /* dword 1 */
+        u8 ip_frag;             /* dword 1 */
         u8 fragndx[10];         /* dword 1 */
         u8 ct[2];               /* dword 1 */
         u8 sw;                  /* dword 1 */
diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c
index ca2967b0f18b..a0b4be51f0d1 100644
--- a/drivers/net/ethernet/emulex/benet/be_main.c
+++ b/drivers/net/ethernet/emulex/benet/be_main.c
@@ -1599,6 +1599,8 @@ static void be_parse_rx_compl_v0(struct be_eth_rx_compl *compl,
                                                compl);
         }
         rxcp->port = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, port, compl);
+        rxcp->ip_frag = AMAP_GET_BITS(struct amap_eth_rx_compl_v0,
+                                      ip_frag, compl);
 }
 
 static struct be_rx_compl_info *be_rx_compl_get(struct be_rx_obj *rxo)
@@ -1620,6 +1622,9 @@ static struct be_rx_compl_info *be_rx_compl_get(struct be_rx_obj *rxo)
         else
                 be_parse_rx_compl_v0(compl, rxcp);
 
+        if (rxcp->ip_frag)
+                rxcp->l4_csum = 0;
+
         if (rxcp->vlanf) {
                 /* vlanf could be wrongly set in some cards.
                  * ignore if vtm is not set */
@@ -2168,7 +2173,7 @@ static irqreturn_t be_msix(int irq, void *dev)
 
 static inline bool do_gro(struct be_rx_compl_info *rxcp)
 {
-        return (rxcp->tcpf && !rxcp->err) ? true : false;
+        return (rxcp->tcpf && !rxcp->err && rxcp->l4_csum) ? true : false;
 }
 
 static int be_process_rx(struct be_rx_obj *rxo, struct napi_struct *napi,
@@ -4093,6 +4098,7 @@ static int be_get_initial_config(struct be_adapter *adapter)
 
 static int lancer_recover_func(struct be_adapter *adapter)
 {
+        struct device *dev = &adapter->pdev->dev;
         int status;
 
         status = lancer_test_and_set_rdy_state(adapter);
@@ -4104,8 +4110,7 @@ static int lancer_recover_func(struct be_adapter *adapter)
 
         be_clear(adapter);
 
-        adapter->hw_error = false;
-        adapter->fw_timeout = false;
+        be_clear_all_error(adapter);
 
         status = be_setup(adapter);
         if (status)
@@ -4117,13 +4122,13 @@ static int lancer_recover_func(struct be_adapter *adapter)
                         goto err;
         }
 
-        dev_err(&adapter->pdev->dev,
-                "Adapter SLIPORT recovery succeeded\n");
+        dev_err(dev, "Error recovery successful\n");
         return 0;
 err:
-        if (adapter->eeh_error)
-                dev_err(&adapter->pdev->dev,
-                        "Adapter SLIPORT recovery failed\n");
+        if (status == -EAGAIN)
+                dev_err(dev, "Waiting for resource provisioning\n");
+        else
+                dev_err(dev, "Error recovery failed\n");
 
         return status;
 }
@@ -4132,28 +4137,27 @@ static void be_func_recovery_task(struct work_struct *work)
 {
         struct be_adapter *adapter =
                 container_of(work, struct be_adapter,  func_recovery_work.work);
-        int status;
+        int status = 0;
 
         be_detect_error(adapter);
 
         if (adapter->hw_error && lancer_chip(adapter)) {
 
-                if (adapter->eeh_error)
-                        goto out;
-
                 rtnl_lock();
                 netif_device_detach(adapter->netdev);
                 rtnl_unlock();
 
                 status = lancer_recover_func(adapter);
-
                 if (!status)
                         netif_device_attach(adapter->netdev);
         }
 
-out:
-        schedule_delayed_work(&adapter->func_recovery_work,
-                              msecs_to_jiffies(1000));
+        /* In Lancer, for all errors other than provisioning error (-EAGAIN),
+         * no need to attempt further recovery.
+         */
+        if (!status || status == -EAGAIN)
+                schedule_delayed_work(&adapter->func_recovery_work,
+                                      msecs_to_jiffies(1000));
 }
 
 static void be_worker(struct work_struct *work)
@@ -4258,6 +4262,9 @@ static int be_probe(struct pci_dev *pdev, const struct pci_device_id *pdev_id)
                 netdev->features |= NETIF_F_HIGHDMA;
         } else {
                 status = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
+                if (!status)
+                        status = dma_set_coherent_mask(&pdev->dev,
+                                                       DMA_BIT_MASK(32));
                 if (status) {
                         dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
                         goto free_netdev;
@@ -4436,20 +4443,19 @@ static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
 
         dev_err(&adapter->pdev->dev, "EEH error detected\n");
 
-        adapter->eeh_error = true;
+        if (!adapter->eeh_error) {
+                adapter->eeh_error = true;
 
-        cancel_delayed_work_sync(&adapter->func_recovery_work);
-
-        rtnl_lock();
-        netif_device_detach(netdev);
-        rtnl_unlock();
+                cancel_delayed_work_sync(&adapter->func_recovery_work);
 
-        if (netif_running(netdev)) {
                 rtnl_lock();
-                be_close(netdev);
+                netif_device_detach(netdev);
+                if (netif_running(netdev))
+                        be_close(netdev);
                 rtnl_unlock();
+
+                be_clear(adapter);
         }
-        be_clear(adapter);
 
         if (state == pci_channel_io_perm_failure)
                 return PCI_ERS_RESULT_DISCONNECT;
@@ -4474,7 +4480,6 @@ static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
         int status;
 
         dev_info(&adapter->pdev->dev, "EEH reset\n");
-        be_clear_all_error(adapter);
 
         status = pci_enable_device(pdev);
         if (status)
@@ -4492,6 +4497,7 @@ static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
                 return PCI_ERS_RESULT_DISCONNECT;
 
         pci_cleanup_aer_uncorrect_error_status(pdev);
+        be_clear_all_error(adapter);
         return PCI_ERS_RESULT_RECOVERED;
 }
 
diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c
index 85a06037b242..a667015be22a 100644
--- a/drivers/net/ethernet/freescale/fec_main.c
+++ b/drivers/net/ethernet/freescale/fec_main.c
@@ -1038,6 +1038,18 @@ static void fec_get_mac(struct net_device *ndev)
                 iap = &tmpaddr[0];
         }
 
+        /*
+         * 5) random mac address
+         */
+        if (!is_valid_ether_addr(iap)) {
+                /* Report it and use a random ethernet address instead */
+                netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
+                eth_hw_addr_random(ndev);
+                netdev_info(ndev, "Using random MAC address: %pM\n",
+                            ndev->dev_addr);
+                return;
+        }
+
         memcpy(ndev->dev_addr, iap, ETH_ALEN);
 
         /* Adjust MAC if using macaddr */
diff --git a/drivers/net/ethernet/mellanox/mlx4/cmd.c b/drivers/net/ethernet/mellanox/mlx4/cmd.c
index 1df56cc50ee9..0e572a527154 100644
--- a/drivers/net/ethernet/mellanox/mlx4/cmd.c
+++ b/drivers/net/ethernet/mellanox/mlx4/cmd.c
@@ -222,8 +222,6 @@ static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
                  * FLR process. The only non-zero result in the RESET command
                  * is MLX4_DELAY_RESET_SLAVE*/
                 if ((MLX4_COMM_CMD_RESET == cmd)) {
-                        mlx4_warn(dev, "Got slave FLRed from Communication"
-                                  " channel (ret:0x%x)\n", ret_from_pending);
                         err = MLX4_DELAY_RESET_SLAVE;
                 } else {
                         mlx4_warn(dev, "Communication channel timed out\n");
diff --git a/drivers/net/ethernet/mellanox/mlx4/en_netdev.c b/drivers/net/ethernet/mellanox/mlx4/en_netdev.c
index b35f94700093..89c47ea84b50 100644
--- a/drivers/net/ethernet/mellanox/mlx4/en_netdev.c
+++ b/drivers/net/ethernet/mellanox/mlx4/en_netdev.c
@@ -1323,6 +1323,7 @@ static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv)
                         priv->last_moder_time[ring] = moder_time;
                         cq = &priv->rx_cq[ring];
                         cq->moder_time = moder_time;
+                        cq->moder_cnt = priv->rx_frames;
                         err = mlx4_en_set_cq_moder(priv, cq);
                         if (err)
                                 en_err(priv, "Failed modifying moderation for cq:%d\n",
@@ -2118,6 +2119,7 @@ int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
         struct mlx4_en_priv *priv;
         int i;
         int err;
+        u64 mac_u64;
 
         dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),
                                  MAX_TX_RINGS, MAX_RX_RINGS);
@@ -2191,10 +2193,17 @@ int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
         dev->addr_len = ETH_ALEN;
         mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);
         if (!is_valid_ether_addr(dev->dev_addr)) {
-                en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",
-                       priv->port, dev->dev_addr);
-                err = -EINVAL;
-                goto out;
+                if (mlx4_is_slave(priv->mdev->dev)) {
+                        eth_hw_addr_random(dev);
+                        en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr);
+                        mac_u64 = mlx4_en_mac_to_u64(dev->dev_addr);
+                        mdev->dev->caps.def_mac[priv->port] = mac_u64;
+                } else {
+                        en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",
+                               priv->port, dev->dev_addr);
+                        err = -EINVAL;
+                        goto out;
+                }
         }
 
         memcpy(priv->prev_mac, dev->dev_addr, sizeof(priv->prev_mac));
diff --git a/drivers/net/ethernet/mellanox/mlx4/fw.c b/drivers/net/ethernet/mellanox/mlx4/fw.c
index 58a8e535d698..2c97901c6a6d 100644
--- a/drivers/net/ethernet/mellanox/mlx4/fw.c
+++ b/drivers/net/ethernet/mellanox/mlx4/fw.c
@@ -840,12 +840,16 @@ int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
                            MLX4_CMD_NATIVE);
 
         if (!err && dev->caps.function != slave) {
-                /* set slave default_mac address */
-                MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET);
-                def_mac += slave << 8;
                 /* if config MAC in DB use it */
                 if (priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac)
                         def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
+                else {
+                        /* set slave default_mac address */
+                        MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET);
+                        def_mac += slave << 8;
+                        priv->mfunc.master.vf_admin[slave].vport[vhcr->in_modifier].mac = def_mac;
+                }
+
                 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
 
                 /* get port type - currently only eth is enabled */
diff --git a/drivers/net/ethernet/mellanox/mlx4/main.c b/drivers/net/ethernet/mellanox/mlx4/main.c
index 0d32a82458bf..2f4a26039e80 100644
--- a/drivers/net/ethernet/mellanox/mlx4/main.c
+++ b/drivers/net/ethernet/mellanox/mlx4/main.c
@@ -1290,7 +1290,6 @@ static int mlx4_init_slave(struct mlx4_dev *dev)
 {
         struct mlx4_priv *priv = mlx4_priv(dev);
         u64 dma = (u64) priv->mfunc.vhcr_dma;
-        int num_of_reset_retries = NUM_OF_RESET_RETRIES;
         int ret_from_reset = 0;
         u32 slave_read;
         u32 cmd_channel_ver;
@@ -1304,18 +1303,10 @@ static int mlx4_init_slave(struct mlx4_dev *dev)
          * NUM_OF_RESET_RETRIES times before leaving.*/
         if (ret_from_reset) {
                 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
-                        msleep(SLEEP_TIME_IN_RESET);
-                        while (ret_from_reset && num_of_reset_retries) {
-                                mlx4_warn(dev, "slave is currently in the"
-                                          "middle of FLR. retrying..."
-                                          "(try num:%d)\n",
-                                          (NUM_OF_RESET_RETRIES -
-                                           num_of_reset_retries  + 1));
-                                ret_from_reset =
-                                        mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET,
-                                                      0, MLX4_COMM_TIME);
-                                num_of_reset_retries = num_of_reset_retries - 1;
-                        }
+                        mlx4_warn(dev, "slave is currently in the "
+                                  "middle of FLR. Deferring probe.\n");
+                        mutex_unlock(&priv->cmd.slave_cmd_mutex);
+                        return -EPROBE_DEFER;
                 } else
                         goto err;
         }
@@ -1526,7 +1517,8 @@ static int mlx4_init_hca(struct mlx4_dev *dev)
         } else {
                 err = mlx4_init_slave(dev);
                 if (err) {
-                        mlx4_err(dev, "Failed to initialize slave\n");
+                        if (err != -EPROBE_DEFER)
+                                mlx4_err(dev, "Failed to initialize slave\n");
                         return err;
                 }
 
diff --git a/drivers/net/ethernet/qlogic/qlge/qlge_main.c b/drivers/net/ethernet/qlogic/qlge/qlge_main.c
index 50235d201592..f87cc216045b 100644
--- a/drivers/net/ethernet/qlogic/qlge/qlge_main.c
+++ b/drivers/net/ethernet/qlogic/qlge/qlge_main.c
@@ -4717,6 +4717,7 @@ static int qlge_probe(struct pci_dev *pdev,
                 dev_err(&pdev->dev, "net device registration failed.\n");
                 ql_release_all(pdev);
                 pci_disable_device(pdev);
+                free_netdev(ndev);
                 return err;
         }
         /* Start up the timer to trigger EEH if
diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
index 42e9dd05c936..5e3982fc5398 100644
--- a/drivers/net/ethernet/renesas/sh_eth.c
+++ b/drivers/net/ethernet/renesas/sh_eth.c
@@ -897,8 +897,8 @@ static int sh_eth_check_reset(struct net_device *ndev)
                 mdelay(1);
                 cnt--;
         }
-        if (cnt < 0) {
-                pr_err("Device reset fail\n");
+        if (cnt <= 0) {
+                pr_err("Device reset failed\n");
                 ret = -ETIMEDOUT;
         }
         return ret;
@@ -1401,16 +1401,23 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status)
                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
                 pkt_len = rxdesc->frame_length;
 
-#if defined(CONFIG_ARCH_R8A7740)
-                desc_status >>= 16;
-#endif
-
                 if (--boguscnt < 0)
                         break;
 
                 if (!(desc_status & RDFEND))
                         ndev->stats.rx_length_errors++;
 
+#if defined(CONFIG_ARCH_R8A7740)
+                /*
+                 * In case of almost all GETHER/ETHERs, the Receive Frame State
+                 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
+                 * bit 0. However, in case of the R8A7740's GETHER, the RFS
+                 * bits are from bit 25 to bit 16. So, the driver needs right
+                 * shifting by 16.
+                 */
+                desc_status >>= 16;
+#endif
+
                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
                         ndev->stats.rx_errors++;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 618446ae1ec1..ee919ca8b8a0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1899,7 +1899,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
 
 #ifdef STMMAC_XMIT_DEBUG
         if (netif_msg_pktdata(priv)) {
-                pr_info("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d"
+                pr_info("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
                         __func__, (priv->cur_tx % txsize),
                         (priv->dirty_tx % txsize), entry, first, nfrags);
                 if (priv->extend_desc)
diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
index 12aec173564c..c47f0dbcebb5 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -449,10 +449,9 @@ static int davinci_mdio_suspend(struct device *dev)
         __raw_writel(ctrl, &data->regs->control);
         wait_for_idle(data);
 
-        pm_runtime_put_sync(data->dev);
-
         data->suspended = true;
         spin_unlock(&data->lock);
+        pm_runtime_put_sync(data->dev);
 
         return 0;
 }
@@ -460,15 +459,12 @@ static int davinci_mdio_suspend(struct device *dev)
 static int davinci_mdio_resume(struct device *dev)
 {
         struct davinci_mdio_data *data = dev_get_drvdata(dev);
-        u32 ctrl;
 
-        spin_lock(&data->lock);
         pm_runtime_get_sync(data->dev);
 
+        spin_lock(&data->lock);
         /* restart the scan state machine */
-        ctrl = __raw_readl(&data->regs->control);
-        ctrl |= CONTROL_ENABLE;
-        __raw_writel(ctrl, &data->regs->control);
+        __davinci_mdio_reset(data);
 
         data->suspended = false;
         spin_unlock(&data->lock);
@@ -477,8 +473,8 @@ static int davinci_mdio_resume(struct device *dev)
 }
 
 static const struct dev_pm_ops davinci_mdio_pm_ops = {
-        .suspend        = davinci_mdio_suspend,
-        .resume         = davinci_mdio_resume,
+        .suspend_late   = davinci_mdio_suspend,
+        .resume_early   = davinci_mdio_resume,
 };
 
 static const struct of_device_id davinci_mdio_of_mtable[] = {
diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
index 919b983114e9..b7268b3dae77 100644
--- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
+++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
@@ -946,7 +946,8 @@ static int xemaclite_open(struct net_device *dev)
                 phy_write(lp->phy_dev, MII_CTRL1000, 0);
 
                 /* Advertise only 10 and 100mbps full/half duplex speeds */
-                phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL);
+                phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL |
+                          ADVERTISE_CSMA);
 
                 /* Restart auto negotiation */
                 bmcr = phy_read(lp->phy_dev, MII_BMCR);
diff --git a/drivers/net/hyperv/netvsc_drv.c b/drivers/net/hyperv/netvsc_drv.c
index 088c55496191..ab2307b5d9a7 100644
--- a/drivers/net/hyperv/netvsc_drv.c
+++ b/drivers/net/hyperv/netvsc_drv.c
@@ -31,6 +31,7 @@
 #include <linux/inetdevice.h>
 #include <linux/etherdevice.h>
 #include <linux/skbuff.h>
+#include <linux/if_vlan.h>
 #include <linux/in.h>
 #include <linux/slab.h>
 #include <net/arp.h>
@@ -284,7 +285,7 @@ int netvsc_recv_callback(struct hv_device *device_obj,
 
         skb->protocol = eth_type_trans(skb, net);
         skb->ip_summed = CHECKSUM_NONE;
-        skb->vlan_tci = packet->vlan_tci;
+        __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), packet->vlan_tci);
 
         net->stats.rx_packets++;
         net->stats.rx_bytes += packet->total_data_buflen;
diff --git a/drivers/net/macvlan.c b/drivers/net/macvlan.c
index 1c502bb0c916..6e91931a1c2c 100644
--- a/drivers/net/macvlan.c
+++ b/drivers/net/macvlan.c
@@ -853,18 +853,24 @@ static int macvlan_changelink(struct net_device *dev,
                 struct nlattr *tb[], struct nlattr *data[])
 {
         struct macvlan_dev *vlan = netdev_priv(dev);
-        if (data && data[IFLA_MACVLAN_MODE])
-                vlan->mode = nla_get_u32(data[IFLA_MACVLAN_MODE]);
+
         if (data && data[IFLA_MACVLAN_FLAGS]) {
                 __u16 flags = nla_get_u16(data[IFLA_MACVLAN_FLAGS]);
                 bool promisc = (flags ^ vlan->flags) & MACVLAN_FLAG_NOPROMISC;
-
-                if (promisc && (flags & MACVLAN_FLAG_NOPROMISC))
-                        dev_set_promiscuity(vlan->lowerdev, -1);
-                else if (promisc && !(flags & MACVLAN_FLAG_NOPROMISC))
-                        dev_set_promiscuity(vlan->lowerdev, 1);
+                if (vlan->port->passthru && promisc) {
+                        int err;
+
+                        if (flags & MACVLAN_FLAG_NOPROMISC)
+                                err = dev_set_promiscuity(vlan->lowerdev, -1);
+                        else
+                                err = dev_set_promiscuity(vlan->lowerdev, 1);
+                        if (err < 0)
+                                return err;
+                }
                 vlan->flags = flags;
         }
+        if (data && data[IFLA_MACVLAN_MODE])
+                vlan->mode = nla_get_u32(data[IFLA_MACVLAN_MODE]);
         return 0;
 }
 
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index c14f14741b3f..38f0b312ff85 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -1044,7 +1044,7 @@ int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable)
                 adv = mmd_eee_adv_to_ethtool_adv_t(eee_adv);
                 lp = mmd_eee_adv_to_ethtool_adv_t(eee_lp);
                 idx = phy_find_setting(phydev->speed, phydev->duplex);
-                if ((lp & adv & settings[idx].setting))
+                if (!(lp & adv & settings[idx].setting))
                         goto eee_exit;
 
                 if (clk_stop_enable) {
diff --git a/drivers/net/team/team.c b/drivers/net/team/team.c
index 7c43261975bd..b3051052f3ad 100644
--- a/drivers/net/team/team.c
+++ b/drivers/net/team/team.c
@@ -1092,8 +1092,8 @@ static int team_port_add(struct team *team, struct net_device *port_dev)
         }
 
         port->index = -1;
-        team_port_enable(team, port);
         list_add_tail_rcu(&port->list, &team->port_list);
+        team_port_enable(team, port);
         __team_compute_features(team);
         __team_port_change_port_added(port, !!netif_carrier_ok(port_dev));
         __team_options_change_check(team);
@@ -2374,7 +2374,8 @@ static int team_nl_send_port_list_get(struct team *team, u32 portid, u32 seq,
         bool incomplete;
         int i;
 
-        port = list_first_entry(&team->port_list, struct team_port, list);
+        port = list_first_entry_or_null(&team->port_list,
+                                        struct team_port, list);
 
 start_again:
         err = __send_and_alloc_skb(&skb, team, portid, send_func);
@@ -2402,8 +2403,8 @@ start_again:
                 err = team_nl_fill_one_port_get(skb, one_port);
                 if (err)
                         goto errout;
-        } else {
-                list_for_each_entry(port, &team->port_list, list) {
+        } else if (port) {
+                list_for_each_entry_from(port, &team->port_list, list) {
                         err = team_nl_fill_one_port_get(skb, port);
                         if (err) {
                                 if (err == -EMSGSIZE) {
diff --git a/drivers/net/team/team_mode_random.c b/drivers/net/team/team_mode_random.c
index 5ca14d463ba7..7f032e211343 100644
--- a/drivers/net/team/team_mode_random.c
+++ b/drivers/net/team/team_mode_random.c
@@ -28,6 +28,8 @@ static bool rnd_transmit(struct team *team, struct sk_buff *skb)
 
         port_index = random_N(team->en_port_count);
         port = team_get_port_by_index_rcu(team, port_index);
+        if (unlikely(!port))
+                goto drop;
         port = team_get_first_port_txable_rcu(team, port);
         if (unlikely(!port))
                 goto drop;
diff --git a/drivers/net/team/team_mode_roundrobin.c b/drivers/net/team/team_mode_roundrobin.c
index d268e4de781b..472623f8ce3d 100644
--- a/drivers/net/team/team_mode_roundrobin.c
+++ b/drivers/net/team/team_mode_roundrobin.c
@@ -32,6 +32,8 @@ static bool rr_transmit(struct team *team, struct sk_buff *skb)
 
         port_index = rr_priv(team)->sent_packets++ % team->en_port_count;
         port = team_get_port_by_index_rcu(team, port_index);
+        if (unlikely(!port))
+                goto drop;
         port = team_get_first_port_txable_rcu(team, port);
         if (unlikely(!port))
                 goto drop;
diff --git a/drivers/net/tun.c b/drivers/net/tun.c
index f042b0373e5d..bfa9bb48e42d 100644
--- a/drivers/net/tun.c
+++ b/drivers/net/tun.c
@@ -352,7 +352,7 @@ static u16 tun_select_queue(struct net_device *dev, struct sk_buff *skb)
         u32 numqueues = 0;
 
         rcu_read_lock();
-        numqueues = tun->numqueues;
+        numqueues = ACCESS_ONCE(tun->numqueues);
 
         txq = skb_get_rxhash(skb);
         if (txq) {
@@ -1585,6 +1585,10 @@ static int tun_set_iff(struct net *net, struct file *file, struct ifreq *ifr)
                 else
                         return -EINVAL;
 
+                if (!!(ifr->ifr_flags & IFF_MULTI_QUEUE) !=
+                    !!(tun->flags & TUN_TAP_MQ))
+                        return -EINVAL;
+
                 if (tun_not_capable(tun))
                         return -EPERM;
                 err = security_tun_dev_open(tun->security);
@@ -2155,6 +2159,8 @@ static int tun_chr_open(struct inode *inode, struct file * file)
         set_bit(SOCK_EXTERNALLY_ALLOCATED, &tfile->socket.flags);
         INIT_LIST_HEAD(&tfile->next);
 
+        sock_set_flag(&tfile->sk, SOCK_ZEROCOPY);
+
         return 0;
 }
 
diff --git a/drivers/net/usb/cdc_ether.c b/drivers/net/usb/cdc_ether.c
index 078795fe6e31..04ee044dde51 100644
--- a/drivers/net/usb/cdc_ether.c
+++ b/drivers/net/usb/cdc_ether.c
@@ -627,6 +627,12 @@ static const struct usb_device_id	products [] = {
         .driver_info = 0,
 },
 
+/* Huawei E1820 - handled by qmi_wwan */
+{
+        USB_DEVICE_INTERFACE_NUMBER(HUAWEI_VENDOR_ID, 0x14ac, 1),
+        .driver_info = 0,
+},
+
 /* Realtek RTL8152 Based USB 2.0 Ethernet Adapters */
 #if defined(CONFIG_USB_RTL8152) || defined(CONFIG_USB_RTL8152_MODULE)
 {
diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c
index 86adfa0a912e..d095d0d3056b 100644
--- a/drivers/net/usb/qmi_wwan.c
+++ b/drivers/net/usb/qmi_wwan.c
@@ -519,6 +519,7 @@ static const struct usb_device_id products[] = {
         /* 3. Combined interface devices matching on interface number */
         {QMI_FIXED_INTF(0x0408, 0xea42, 4)},    /* Yota / Megafon M100-1 */
         {QMI_FIXED_INTF(0x12d1, 0x140c, 1)},    /* Huawei E173 */
+        {QMI_FIXED_INTF(0x12d1, 0x14ac, 1)},    /* Huawei E1820 */
         {QMI_FIXED_INTF(0x19d2, 0x0002, 1)},
         {QMI_FIXED_INTF(0x19d2, 0x0012, 1)},
         {QMI_FIXED_INTF(0x19d2, 0x0017, 3)},
diff --git a/drivers/net/wireless/ath/ath9k/Kconfig b/drivers/net/wireless/ath/ath9k/Kconfig
index f3dc124c60c7..3c2cbc9d6295 100644
--- a/drivers/net/wireless/ath/ath9k/Kconfig
+++ b/drivers/net/wireless/ath/ath9k/Kconfig
@@ -92,13 +92,17 @@ config ATH9K_MAC_DEBUG
           This option enables collection of statistics for Rx/Tx status
           data and some other MAC related statistics
 
-config ATH9K_RATE_CONTROL
+config ATH9K_LEGACY_RATE_CONTROL
         bool "Atheros ath9k rate control"
         depends on ATH9K
-        default y
+        default n
         ---help---
           Say Y, if you want to use the ath9k specific rate control
-          module instead of minstrel_ht.
+          module instead of minstrel_ht. Be warned that there are various
+          issues with the ath9k RC and minstrel is a more robust algorithm.
+          Note that even if this option is selected, "ath9k_rate_control"
+          has to be passed to mac80211 using the module parameter,
+          ieee80211_default_rc_algo.
 
 config ATH9K_HTC
        tristate "Atheros HTC based wireless cards support"
diff --git a/drivers/net/wireless/ath/ath9k/Makefile b/drivers/net/wireless/ath/ath9k/Makefile
index 2ad8f9474ba1..75ee9e7704ce 100644
--- a/drivers/net/wireless/ath/ath9k/Makefile
+++ b/drivers/net/wireless/ath/ath9k/Makefile
@@ -8,7 +8,7 @@ ath9k-y +=	beacon.o \
                 antenna.o
 
 ath9k-$(CONFIG_ATH9K_BTCOEX_SUPPORT) += mci.o
-ath9k-$(CONFIG_ATH9K_RATE_CONTROL) += rc.o
+ath9k-$(CONFIG_ATH9K_LEGACY_RATE_CONTROL) += rc.o
 ath9k-$(CONFIG_ATH9K_PCI) += pci.o
 ath9k-$(CONFIG_ATH9K_AHB) += ahb.o
 ath9k-$(CONFIG_ATH9K_DEBUGFS) += debug.o
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
index db5ffada2217..7546b9a7dcbf 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
@@ -958,11 +958,11 @@ static const u32 ar9300Common_rx_gain_table_2p2[][2] = {
         {0x0000a074, 0x00000000},
         {0x0000a078, 0x00000000},
         {0x0000a07c, 0x00000000},
-        {0x0000a080, 0x1a1a1a1a},
-        {0x0000a084, 0x1a1a1a1a},
-        {0x0000a088, 0x1a1a1a1a},
-        {0x0000a08c, 0x1a1a1a1a},
-        {0x0000a090, 0x171a1a1a},
+        {0x0000a080, 0x22222229},
+        {0x0000a084, 0x1d1d1d1d},
+        {0x0000a088, 0x1d1d1d1d},
+        {0x0000a08c, 0x1d1d1d1d},
+        {0x0000a090, 0x171d1d1d},
         {0x0000a094, 0x11111717},
         {0x0000a098, 0x00030311},
         {0x0000a09c, 0x00000000},
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
index 54ba42f4108a..874f6570bd1c 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
@@ -68,13 +68,16 @@
 #define AR9300_BASE_ADDR 0x3ff
 #define AR9300_BASE_ADDR_512 0x1ff
 
-#define AR9300_OTP_BASE                 (AR_SREV_9340(ah) ? 0x30000 : 0x14000)
-#define AR9300_OTP_STATUS               (AR_SREV_9340(ah) ? 0x30018 : 0x15f18)
+#define AR9300_OTP_BASE \
+                ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x30000 : 0x14000)
+#define AR9300_OTP_STATUS \
+                ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x30018 : 0x15f18)
 #define AR9300_OTP_STATUS_TYPE          0x7
 #define AR9300_OTP_STATUS_VALID         0x4
 #define AR9300_OTP_STATUS_ACCESS_BUSY   0x2
 #define AR9300_OTP_STATUS_SM_BUSY       0x1
-#define AR9300_OTP_READ_DATA            (AR_SREV_9340(ah) ? 0x3001c : 0x15f1c)
+#define AR9300_OTP_READ_DATA \
+                ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x3001c : 0x15f1c)
 
 enum targetPowerHTRates {
         HT_TARGET_RATE_0_8_16,
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index 2bf6548dd143..e1714d7c9eeb 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -334,7 +334,8 @@ static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
 
-        if (REG_READ_FIELD(ah, AR_PHY_MODE,
+        if (!AR_SREV_9340(ah) &&
+            REG_READ_FIELD(ah, AR_PHY_MODE,
                            AR_PHY_MODE_DYNAMIC) == 0x1)
                 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
                               AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index 366002f266f8..42b03dc39d14 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -251,10 +251,9 @@ struct ath_atx_tid {
         int tidno;
         int baw_head;   /* first un-acked tx buffer */
         int baw_tail;   /* next unused tx buffer slot */
-        int sched;
-        int paused;
-        u8 state;
-        bool stop_cb;
+        bool sched;
+        bool paused;
+        bool active;
 };
 
 struct ath_node {
@@ -275,10 +274,6 @@ struct ath_node {
 #endif
 };
 
-#define AGGR_CLEANUP         BIT(1)
-#define AGGR_ADDBA_COMPLETE  BIT(2)
-#define AGGR_ADDBA_PROGRESS  BIT(3)
-
 struct ath_tx_control {
         struct ath_txq *txq;
         struct ath_node *an;
@@ -352,8 +347,7 @@ void ath_tx_tasklet(struct ath_softc *sc);
 void ath_tx_edma_tasklet(struct ath_softc *sc);
 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
                       u16 tid, u16 *ssn);
-bool ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid,
-                      bool flush);
+void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 
 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 7f25da8444fe..15dfefcf2d0f 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -1172,6 +1172,7 @@ u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
 {
         struct ath_common *common = ath9k_hw_common(ah);
+        int txbuf_size;
 
         ENABLE_REGWRITE_BUFFER(ah);
 
@@ -1225,13 +1226,17 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
                  * So set the usable tx buf size also to half to
                  * avoid data/delimiter underruns
                  */
-                REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
-                          AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
-        } else if (!AR_SREV_9271(ah)) {
-                REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
-                          AR_PCU_TXBUF_CTRL_USABLE_SIZE);
+                txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
+        } else if (AR_SREV_9340_13_OR_LATER(ah)) {
+                /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
+                txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
+        } else {
+                txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
         }
 
+        if (!AR_SREV_9271(ah))
+                REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
+
         REGWRITE_BUFFER_FLUSH(ah);
 
         if (AR_SREV_9300_20_OR_LATER(ah))
@@ -1306,9 +1311,13 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
         } else {
                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
-                if (tmpReg &
-                    (AR_INTR_SYNC_LOCAL_TIMEOUT |
-                     AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
+                if (AR_SREV_9340(ah))
+                        tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
+                else
+                        tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
+                                  AR_INTR_SYNC_RADM_CPL_TIMEOUT;
+
+                if (tmpReg) {
                         u32 val;
                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
 
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index aba415103f94..2ba494567777 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -787,8 +787,7 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
         hw->wiphy->iface_combinations = if_comb;
         hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
 
-        if (AR_SREV_5416(sc->sc_ah))
-                hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
+        hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
 
         hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
         hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
@@ -830,10 +829,6 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
         sc->ant_rx = hw->wiphy->available_antennas_rx;
         sc->ant_tx = hw->wiphy->available_antennas_tx;
 
-#ifdef CONFIG_ATH9K_RATE_CONTROL
-        hw->rate_control_algorithm = "ath9k_rate_control";
-#endif
-
         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
                         &sc->sbands[IEEE80211_BAND_2GHZ];
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index 498fee04afa0..566109a40fb3 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -410,7 +410,7 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
 
         REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
 
-        if (AR_SREV_9340(ah))
+        if (AR_SREV_9340(ah) && !AR_SREV_9340_13_OR_LATER(ah))
                 REG_WRITE(ah, AR_DMISC(q),
                           AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1);
         else
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index 2382d1262e7f..5092ecae7706 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -1709,7 +1709,8 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
                 flush = true;
         case IEEE80211_AMPDU_TX_STOP_CONT:
                 ath9k_ps_wakeup(sc);
-                if (ath_tx_aggr_stop(sc, sta, tid, flush))
+                ath_tx_aggr_stop(sc, sta, tid);
+                if (!flush)
                         ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
                 ath9k_ps_restore(sc);
                 break;
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
index aa4d368d8d3d..7eb1f4b458e4 100644
--- a/drivers/net/wireless/ath/ath9k/rc.c
+++ b/drivers/net/wireless/ath/ath9k/rc.c
@@ -1227,10 +1227,7 @@ static bool ath_tx_aggr_check(struct ath_softc *sc, struct ieee80211_sta *sta,
                 return false;
 
         txtid = ATH_AN_2_TID(an, tidno);
-
-        if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS)))
-                        return true;
-        return false;
+        return !txtid->active;
 }
 
 
diff --git a/drivers/net/wireless/ath/ath9k/rc.h b/drivers/net/wireless/ath/ath9k/rc.h
index 267dbfcfaa96..b9a87383cb43 100644
--- a/drivers/net/wireless/ath/ath9k/rc.h
+++ b/drivers/net/wireless/ath/ath9k/rc.h
@@ -231,7 +231,7 @@ static inline void ath_debug_stat_retries(struct ath_rate_priv *rc, int rix,
 }
 #endif
 
-#ifdef CONFIG_ATH9K_RATE_CONTROL
+#ifdef CONFIG_ATH9K_LEGACY_RATE_CONTROL
 int ath_rate_control_register(void);
 void ath_rate_control_unregister(void);
 #else
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index 5c4ab5026dca..f7c90cc58d56 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -798,6 +798,10 @@
 #define AR_SREV_REVISION_9485_10        0
 #define AR_SREV_REVISION_9485_11        1
 #define AR_SREV_VERSION_9340            0x300
+#define AR_SREV_REVISION_9340_10        0
+#define AR_SREV_REVISION_9340_11        1
+#define AR_SREV_REVISION_9340_12        2
+#define AR_SREV_REVISION_9340_13        3
 #define AR_SREV_VERSION_9580            0x1C0
 #define AR_SREV_REVISION_9580_10        4 /* AR9580 1.0 */
 #define AR_SREV_VERSION_9462            0x280
@@ -897,6 +901,10 @@
 #define AR_SREV_9340(_ah) \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9340))
 
+#define AR_SREV_9340_13_OR_LATER(_ah) \
+        (AR_SREV_9340((_ah)) && \
+         ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9340_13))
+
 #define AR_SREV_9285E_20(_ah) \
     (AR_SREV_9285_12_OR_LATER(_ah) && \
      ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))
@@ -1007,6 +1015,8 @@ enum {
                                 AR_INTR_SYNC_LOCAL_TIMEOUT |
                                 AR_INTR_SYNC_MAC_SLEEP_ACCESS),
 
+        AR9340_INTR_SYNC_LOCAL_TIMEOUT = 0x00000010,
+
         AR_INTR_SYNC_SPURIOUS = 0xFFFFFFFF,
 
 };
@@ -1881,6 +1891,7 @@ enum {
 #define AR_PCU_TXBUF_CTRL_SIZE_MASK     0x7FF
 #define AR_PCU_TXBUF_CTRL_USABLE_SIZE   0x700
 #define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE   0x380
+#define AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE   0x500
 
 #define AR_PCU_MISC_MODE2               0x8344
 #define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE           0x00000002
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 14bb3354ea64..1c9b1bac8b0d 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -125,24 +125,6 @@ static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
         list_add_tail(&ac->list, &txq->axq_acq);
 }
 
-static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
-{
-        struct ath_txq *txq = tid->ac->txq;
-
-        WARN_ON(!tid->paused);
-
-        ath_txq_lock(sc, txq);
-        tid->paused = false;
-
-        if (skb_queue_empty(&tid->buf_q))
-                goto unlock;
-
-        ath_tx_queue_tid(txq, tid);
-        ath_txq_schedule(sc, txq);
-unlock:
-        ath_txq_unlock_complete(sc, txq);
-}
-
 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
 {
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
@@ -164,20 +146,7 @@ static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
                                ARRAY_SIZE(bf->rates));
 }
 
-static void ath_tx_clear_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
-{
-        tid->state &= ~AGGR_ADDBA_COMPLETE;
-        tid->state &= ~AGGR_CLEANUP;
-        if (!tid->stop_cb)
-                return;
-
-        ieee80211_start_tx_ba_cb_irqsafe(tid->an->vif, tid->an->sta->addr,
-                                         tid->tidno);
-        tid->stop_cb = false;
-}
-
-static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid,
-                             bool flush_packets)
+static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
 {
         struct ath_txq *txq = tid->ac->txq;
         struct sk_buff *skb;
@@ -194,15 +163,16 @@ static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid,
         while ((skb = __skb_dequeue(&tid->buf_q))) {
                 fi = get_frame_info(skb);
                 bf = fi->bf;
-                if (!bf && !flush_packets)
-                        bf = ath_tx_setup_buffer(sc, txq, tid, skb);
 
                 if (!bf) {
-                        ieee80211_free_txskb(sc->hw, skb);
-                        continue;
+                        bf = ath_tx_setup_buffer(sc, txq, tid, skb);
+                        if (!bf) {
+                                ieee80211_free_txskb(sc->hw, skb);
+                                continue;
+                        }
                 }
 
-                if (fi->retries || flush_packets) {
+                if (fi->retries) {
                         list_add_tail(&bf->list, &bf_head);
                         ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
                         ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
@@ -213,10 +183,7 @@ static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid,
                 }
         }
 
-        if (tid->baw_head == tid->baw_tail)
-                ath_tx_clear_tid(sc, tid);
-
-        if (sendbar && !flush_packets) {
+        if (sendbar) {
                 ath_txq_unlock(sc, txq);
                 ath_send_bar(tid, tid->seq_start);
                 ath_txq_lock(sc, txq);
@@ -499,19 +466,19 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                 tx_info = IEEE80211_SKB_CB(skb);
                 fi = get_frame_info(skb);
 
-                if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
+                if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
+                        /*
+                         * Outside of the current BlockAck window,
+                         * maybe part of a previous session
+                         */
+                        txfail = 1;
+                } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
                         /* transmit completion, subframe is
                          * acked by block ack */
                         acked_cnt++;
                 } else if (!isaggr && txok) {
                         /* transmit completion */
                         acked_cnt++;
-                } else if (tid->state & AGGR_CLEANUP) {
-                        /*
-                         * cleanup in progress, just fail
-                         * the un-acked sub-frames
-                         */
-                        txfail = 1;
                 } else if (flush) {
                         txpending = 1;
                 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
@@ -535,7 +502,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                 if (bf_next != NULL || !bf_last->bf_stale)
                         list_move_tail(&bf->list, &bf_head);
 
-                if (!txpending || (tid->state & AGGR_CLEANUP)) {
+                if (!txpending) {
                         /*
                          * complete the acked-ones/xretried ones; update
                          * block-ack window
@@ -609,9 +576,6 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                 ath_txq_lock(sc, txq);
         }
 
-        if (tid->state & AGGR_CLEANUP)
-                ath_tx_flush_tid(sc, tid, false);
-
         rcu_read_unlock();
 
         if (needreset)
@@ -1244,9 +1208,6 @@ int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
         an = (struct ath_node *)sta->drv_priv;
         txtid = ATH_AN_2_TID(an, tid);
 
-        if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
-                return -EAGAIN;
-
         /* update ampdu factor/density, they may have changed. This may happen
          * in HT IBSS when a beacon with HT-info is received after the station
          * has already been added.
@@ -1258,7 +1219,7 @@ int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
                 an->mpdudensity = density;
         }
 
-        txtid->state |= AGGR_ADDBA_PROGRESS;
+        txtid->active = true;
         txtid->paused = true;
         *ssn = txtid->seq_start = txtid->seq_next;
         txtid->bar_index = -1;
@@ -1269,45 +1230,17 @@ int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
         return 0;
 }
 
-bool ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid,
-                      bool flush)
+void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
 {
         struct ath_node *an = (struct ath_node *)sta->drv_priv;
         struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
         struct ath_txq *txq = txtid->ac->txq;
-        bool ret = !flush;
-
-        if (flush)
-                txtid->stop_cb = false;
-
-        if (txtid->state & AGGR_CLEANUP)
-                return false;
-
-        if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
-                txtid->state &= ~AGGR_ADDBA_PROGRESS;
-                return ret;
-        }
 
         ath_txq_lock(sc, txq);
+        txtid->active = false;
         txtid->paused = true;
-
-        /*
-         * If frames are still being transmitted for this TID, they will be
-         * cleaned up during tx completion. To prevent race conditions, this
-         * TID can only be reused after all in-progress subframes have been
-         * completed.
-         */
-        if (txtid->baw_head != txtid->baw_tail) {
-                txtid->state |= AGGR_CLEANUP;
-                ret = false;
-                txtid->stop_cb = !flush;
-        } else {
-                txtid->state &= ~AGGR_ADDBA_COMPLETE;
-        }
-
-        ath_tx_flush_tid(sc, txtid, flush);
+        ath_tx_flush_tid(sc, txtid);
         ath_txq_unlock_complete(sc, txq);
-        return ret;
 }
 
 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
@@ -1371,18 +1304,28 @@ void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
         }
 }
 
-void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
+void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
+                        u16 tidno)
 {
-        struct ath_atx_tid *txtid;
+        struct ath_atx_tid *tid;
         struct ath_node *an;
+        struct ath_txq *txq;
 
         an = (struct ath_node *)sta->drv_priv;
+        tid = ATH_AN_2_TID(an, tidno);
+        txq = tid->ac->txq;
 
-        txtid = ATH_AN_2_TID(an, tid);
-        txtid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
-        txtid->state |= AGGR_ADDBA_COMPLETE;
-        txtid->state &= ~AGGR_ADDBA_PROGRESS;
-        ath_tx_resume_tid(sc, txtid);
+        ath_txq_lock(sc, txq);
+
+        tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
+        tid->paused = false;
+
+        if (!skb_queue_empty(&tid->buf_q)) {
+                ath_tx_queue_tid(txq, tid);
+                ath_txq_schedule(sc, txq);
+        }
+
+        ath_txq_unlock_complete(sc, txq);
 }
 
 /********************/
@@ -2431,13 +2374,10 @@ void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
                 tid->baw_head  = tid->baw_tail = 0;
                 tid->sched     = false;
                 tid->paused    = false;
-                tid->state &= ~AGGR_CLEANUP;
+                tid->active        = false;
                 __skb_queue_head_init(&tid->buf_q);
                 acno = TID_TO_WME_AC(tidno);
                 tid->ac = &an->ac[acno];
-                tid->state &= ~AGGR_ADDBA_COMPLETE;
-                tid->state &= ~AGGR_ADDBA_PROGRESS;
-                tid->stop_cb = false;
         }
 
         for (acno = 0, ac = &an->ac[acno];
@@ -2474,7 +2414,7 @@ void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
                 }
 
                 ath_tid_drain(sc, txq, tid);
-                ath_tx_clear_tid(sc, tid);
+                tid->active = false;
 
                 ath_txq_unlock(sc, txq);
         }
diff --git a/drivers/net/wireless/atmel.c b/drivers/net/wireless/atmel.c
index 830bb1d1f957..b827d51c30a3 100644
--- a/drivers/net/wireless/atmel.c
+++ b/drivers/net/wireless/atmel.c
@@ -1624,7 +1624,7 @@ struct net_device *init_atmel_card(unsigned short irq, unsigned long port,
 
         netif_carrier_off(dev);
 
-        if (!proc_create_data("driver/atmel", 0, NULL, &atmel_proc_fops, priv));
+        if (!proc_create_data("driver/atmel", 0, NULL, &atmel_proc_fops, priv))
                 printk(KERN_WARNING "atmel: unable to create /proc entry.\n");
 
         printk(KERN_INFO "%s: Atmel at76c50x. Version %d.%d. MAC %pM\n",
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c
index 6dd07e2ec595..a95b77ab360e 100644
--- a/drivers/net/wireless/b43/main.c
+++ b/drivers/net/wireless/b43/main.c
@@ -2458,7 +2458,7 @@ static void b43_request_firmware(struct work_struct *work)
         for (i = 0; i < B43_NR_FWTYPES; i++) {
                 errmsg = ctx->errors[i];
                 if (strlen(errmsg))
-                        b43err(dev->wl, errmsg);
+                        b43err(dev->wl, "%s", errmsg);
         }
         b43_print_fw_helptext(dev->wl, 1);
         goto out;
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c b/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c
index be0787cab24f..9431af2465f3 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c
@@ -27,7 +27,6 @@
 #include "tracepoint.h"
 
 #define PKTFILTER_BUF_SIZE              128
-#define BRCMF_ARPOL_MODE                0xb     /* agent|snoop|peer_autoreply */
 #define BRCMF_DEFAULT_BCN_TIMEOUT       3
 #define BRCMF_DEFAULT_SCAN_CHANNEL_TIME 40
 #define BRCMF_DEFAULT_SCAN_UNASSOC_TIME 40
@@ -338,23 +337,6 @@ int brcmf_c_preinit_dcmds(struct brcmf_if *ifp)
                 goto done;
         }
 
-        /* Try to set and enable ARP offload feature, this may fail */
-        err = brcmf_fil_iovar_int_set(ifp, "arp_ol", BRCMF_ARPOL_MODE);
-        if (err) {
-                brcmf_dbg(TRACE, "failed to set ARP offload mode to 0x%x, err = %d\n",
-                          BRCMF_ARPOL_MODE, err);
-                err = 0;
-        } else {
-                err = brcmf_fil_iovar_int_set(ifp, "arpoe", 1);
-                if (err) {
-                        brcmf_dbg(TRACE, "failed to enable ARP offload err = %d\n",
-                                  err);
-                        err = 0;
-                } else
-                        brcmf_dbg(TRACE, "successfully enabled ARP offload to 0x%x\n",
-                                  BRCMF_ARPOL_MODE);
-        }
-
         /* Setup packet filter */
         brcmf_c_pktfilter_offload_set(ifp, BRCMF_DEFAULT_PACKET_FILTER);
         brcmf_c_pktfilter_offload_enable(ifp, BRCMF_DEFAULT_PACKET_FILTER,
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c b/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
index 59c25463e428..b98f2235978e 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
@@ -653,10 +653,13 @@ int brcmf_net_attach(struct brcmf_if *ifp, bool rtnl_locked)
 
         brcmf_dbg(INFO, "%s: Broadcom Dongle Host Driver\n", ndev->name);
 
+        ndev->destructor = free_netdev;
         return 0;
 
 fail:
+        drvr->iflist[ifp->bssidx] = NULL;
         ndev->netdev_ops = NULL;
+        free_netdev(ndev);
         return -EBADE;
 }
 
@@ -720,6 +723,9 @@ static int brcmf_net_p2p_attach(struct brcmf_if *ifp)
         return 0;
 
 fail:
+        ifp->drvr->iflist[ifp->bssidx] = NULL;
+        ndev->netdev_ops = NULL;
+        free_netdev(ndev);
         return -EBADE;
 }
 
@@ -788,6 +794,7 @@ void brcmf_del_if(struct brcmf_pub *drvr, s32 bssidx)
         struct brcmf_if *ifp;
 
         ifp = drvr->iflist[bssidx];
+        drvr->iflist[bssidx] = NULL;
         if (!ifp) {
                 brcmf_err("Null interface, idx=%d\n", bssidx);
                 return;
@@ -808,15 +815,13 @@ void brcmf_del_if(struct brcmf_pub *drvr, s32 bssidx)
                         cancel_work_sync(&ifp->setmacaddr_work);
                         cancel_work_sync(&ifp->multicast_work);
                 }
-
+                /* unregister will take care of freeing it */
                 unregister_netdev(ifp->ndev);
                 if (bssidx == 0)
                         brcmf_cfg80211_detach(drvr->config);
-                free_netdev(ifp->ndev);
         } else {
                 kfree(ifp);
         }
-        drvr->iflist[bssidx] = NULL;
 }
 
 int brcmf_attach(uint bus_hdrlen, struct device *dev)
@@ -925,8 +930,6 @@ fail:
                         brcmf_fws_del_interface(ifp);
                         brcmf_fws_deinit(drvr);
                 }
-                free_netdev(ifp->ndev);
-                drvr->iflist[0] = NULL;
                 if (p2p_ifp) {
                         free_netdev(p2p_ifp->ndev);
                         drvr->iflist[1] = NULL;
@@ -934,7 +937,8 @@ fail:
                 return ret;
         }
         if ((brcmf_p2p_enable) && (p2p_ifp))
-                brcmf_net_p2p_attach(p2p_ifp);
+                if (brcmf_net_p2p_attach(p2p_ifp) < 0)
+                        brcmf_p2p_enable = 0;
 
         return 0;
 }
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/fweh.c b/drivers/net/wireless/brcm80211/brcmfmac/fweh.c
index 5a64280e6485..83ee53a7c76e 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/fweh.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/fweh.c
@@ -202,7 +202,8 @@ static void brcmf_fweh_handle_if_event(struct brcmf_pub *drvr,
                         return;
                 brcmf_fws_add_interface(ifp);
                 if (!drvr->fweh.evt_handler[BRCMF_E_IF])
-                        err = brcmf_net_attach(ifp, false);
+                        if (brcmf_net_attach(ifp, false) < 0)
+                                return;
         }
 
         if (ifevent->action == BRCMF_E_IF_CHANGE)
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/fwil_types.h b/drivers/net/wireless/brcm80211/brcmfmac/fwil_types.h
index 0f2c83bc95dc..665ef69e974b 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/fwil_types.h
+++ b/drivers/net/wireless/brcm80211/brcmfmac/fwil_types.h
@@ -23,6 +23,12 @@
 
 #define BRCMF_FIL_ACTION_FRAME_SIZE     1800
 
+/* ARP Offload feature flags for arp_ol iovar */
+#define BRCMF_ARP_OL_AGENT              0x00000001
+#define BRCMF_ARP_OL_SNOOP              0x00000002
+#define BRCMF_ARP_OL_HOST_AUTO_REPLY    0x00000004
+#define BRCMF_ARP_OL_PEER_AUTO_REPLY    0x00000008
+
 
 enum brcmf_fil_p2p_if_types {
         BRCMF_FIL_P2P_IF_CLIENT,
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/p2p.c b/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
index e7a1a4770996..79555f006d53 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
@@ -47,6 +47,7 @@
 #define IS_P2P_SOCIAL_CHANNEL(channel) ((channel == SOCIAL_CHAN_1) || \
                                          (channel == SOCIAL_CHAN_2) || \
                                          (channel == SOCIAL_CHAN_3))
+#define BRCMF_P2P_TEMP_CHAN     SOCIAL_CHAN_3
 #define SOCIAL_CHAN_CNT         3
 #define AF_PEER_SEARCH_CNT      2
 
@@ -1954,21 +1955,21 @@ s32 brcmf_p2p_attach(struct brcmf_cfg80211_info *cfg)
                 err = brcmf_fil_iovar_int_set(pri_ifp, "p2p_disc", 1);
                 if (err < 0) {
                         brcmf_err("set p2p_disc error\n");
-                        brcmf_free_vif(p2p_vif);
+                        brcmf_free_vif(cfg, p2p_vif);
                         goto exit;
                 }
                 /* obtain bsscfg index for P2P discovery */
                 err = brcmf_fil_iovar_int_get(pri_ifp, "p2p_dev", &bssidx);
                 if (err < 0) {
                         brcmf_err("retrieving discover bsscfg index failed\n");
-                        brcmf_free_vif(p2p_vif);
+                        brcmf_free_vif(cfg, p2p_vif);
                         goto exit;
                 }
                 /* Verify that firmware uses same bssidx as driver !! */
                 if (p2p_ifp->bssidx != bssidx) {
                         brcmf_err("Incorrect bssidx=%d, compared to p2p_ifp->bssidx=%d\n",
                                   bssidx, p2p_ifp->bssidx);
-                        brcmf_free_vif(p2p_vif);
+                        brcmf_free_vif(cfg, p2p_vif);
                         goto exit;
                 }
 
@@ -1996,7 +1997,7 @@ void brcmf_p2p_detach(struct brcmf_p2p_info *p2p)
                 brcmf_p2p_cancel_remain_on_channel(vif->ifp);
                 brcmf_p2p_deinit_discovery(p2p);
                 /* remove discovery interface */
-                brcmf_free_vif(vif);
+                brcmf_free_vif(p2p->cfg, vif);
                 p2p->bss_idx[P2PAPI_BSSCFG_DEVICE].vif = NULL;
         }
         /* just set it all to zero */
@@ -2013,17 +2014,30 @@ static void brcmf_p2p_get_current_chanspec(struct brcmf_p2p_info *p2p,
                                            u16 *chanspec)
 {
         struct brcmf_if *ifp;
-        struct brcmf_fil_chan_info_le ci;
+        u8 mac_addr[ETH_ALEN];
         struct brcmu_chan ch;
-        s32 err;
+        struct brcmf_bss_info_le *bi;
+        u8 *buf;
 
         ifp = p2p->bss_idx[P2PAPI_BSSCFG_PRIMARY].vif->ifp;
 
-        ch.chnum = 11;
-
-        err = brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_CHANNEL, &ci, sizeof(ci));
-        if (!err)
-                ch.chnum = le32_to_cpu(ci.hw_channel);
+        if (brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_BSSID, mac_addr,
+                                   ETH_ALEN) == 0) {
+                buf = kzalloc(WL_BSS_INFO_MAX, GFP_KERNEL);
+                if (buf != NULL) {
+                        *(__le32 *)buf = cpu_to_le32(WL_BSS_INFO_MAX);
+                        if (brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_BSS_INFO,
+                                                   buf, WL_BSS_INFO_MAX) == 0) {
+                                bi = (struct brcmf_bss_info_le *)(buf + 4);
+                                *chanspec = le16_to_cpu(bi->chanspec);
+                                kfree(buf);
+                                return;
+                        }
+                        kfree(buf);
+                }
+        }
+        /* Use default channel for P2P */
+        ch.chnum = BRCMF_P2P_TEMP_CHAN;
         ch.bw = BRCMU_CHAN_BW_20;
         p2p->cfg->d11inf.encchspec(&ch);
         *chanspec = ch.chspec;
@@ -2208,7 +2222,7 @@ static struct wireless_dev *brcmf_p2p_create_p2pdev(struct brcmf_p2p_info *p2p,
         return &p2p_vif->wdev;
 
 fail:
-        brcmf_free_vif(p2p_vif);
+        brcmf_free_vif(p2p->cfg, p2p_vif);
         return ERR_PTR(err);
 }
 
@@ -2217,13 +2231,31 @@ fail:
  *
  * @vif: virtual interface object to delete.
  */
-static void brcmf_p2p_delete_p2pdev(struct brcmf_cfg80211_vif *vif)
+static void brcmf_p2p_delete_p2pdev(struct brcmf_cfg80211_info *cfg,
+                                    struct brcmf_cfg80211_vif *vif)
 {
-        struct brcmf_p2p_info *p2p = &vif->ifp->drvr->config->p2p;
-
         cfg80211_unregister_wdev(&vif->wdev);
-        p2p->bss_idx[P2PAPI_BSSCFG_DEVICE].vif = NULL;
-        brcmf_free_vif(vif);
+        cfg->p2p.bss_idx[P2PAPI_BSSCFG_DEVICE].vif = NULL;
+        brcmf_free_vif(cfg, vif);
+}
+
+/**
+ * brcmf_p2p_free_p2p_if() - free up net device related data.
+ *
+ * @ndev: net device that needs to be freed.
+ */
+static void brcmf_p2p_free_p2p_if(struct net_device *ndev)
+{
+        struct brcmf_cfg80211_info *cfg;
+        struct brcmf_cfg80211_vif *vif;
+        struct brcmf_if *ifp;
+
+        ifp = netdev_priv(ndev);
+        cfg = ifp->drvr->config;
+        vif = ifp->vif;
+
+        brcmf_free_vif(cfg, vif);
+        free_netdev(ifp->ndev);
 }
 
 /**
@@ -2303,6 +2335,9 @@ struct wireless_dev *brcmf_p2p_add_vif(struct wiphy *wiphy, const char *name,
                 brcmf_err("Registering netdevice failed\n");
                 goto fail;
         }
+        /* override destructor */
+        ifp->ndev->destructor = brcmf_p2p_free_p2p_if;
+
         cfg->p2p.bss_idx[P2PAPI_BSSCFG_CONNECTION].vif = vif;
         /* Disable firmware roaming for P2P interface  */
         brcmf_fil_iovar_int_set(ifp, "roam_off", 1);
@@ -2314,7 +2349,7 @@ struct wireless_dev *brcmf_p2p_add_vif(struct wiphy *wiphy, const char *name,
         return &ifp->vif->wdev;
 
 fail:
-        brcmf_free_vif(vif);
+        brcmf_free_vif(cfg, vif);
         return ERR_PTR(err);
 }
 
@@ -2350,7 +2385,7 @@ int brcmf_p2p_del_vif(struct wiphy *wiphy, struct wireless_dev *wdev)
                 break;
 
         case NL80211_IFTYPE_P2P_DEVICE:
-                brcmf_p2p_delete_p2pdev(vif);
+                brcmf_p2p_delete_p2pdev(cfg, vif);
                 return 0;
         default:
                 return -ENOTSUPP;
@@ -2378,7 +2413,6 @@ int brcmf_p2p_del_vif(struct wiphy *wiphy, struct wireless_dev *wdev)
                         err = 0;
         }
         brcmf_cfg80211_arm_vif_event(cfg, NULL);
-        brcmf_free_vif(vif);
         p2p->bss_idx[P2PAPI_BSSCFG_CONNECTION].vif = NULL;
 
         return err;
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
index 761f501959a9..301e572e8923 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
@@ -459,6 +459,38 @@ send_key_to_dongle(struct net_device *ndev, struct brcmf_wsec_key *key)
         return err;
 }
 
+static s32
+brcmf_configure_arp_offload(struct brcmf_if *ifp, bool enable)
+{
+        s32 err;
+        u32 mode;
+
+        if (enable)
+                mode = BRCMF_ARP_OL_AGENT | BRCMF_ARP_OL_PEER_AUTO_REPLY;
+        else
+                mode = 0;
+
+        /* Try to set and enable ARP offload feature, this may fail, then it  */
+        /* is simply not supported and err 0 will be returned                 */
+        err = brcmf_fil_iovar_int_set(ifp, "arp_ol", mode);
+        if (err) {
+                brcmf_dbg(TRACE, "failed to set ARP offload mode to 0x%x, err = %d\n",
+                          mode, err);
+                err = 0;
+        } else {
+                err = brcmf_fil_iovar_int_set(ifp, "arpoe", enable);
+                if (err) {
+                        brcmf_dbg(TRACE, "failed to configure (%d) ARP offload err = %d\n",
+                                  enable, err);
+                        err = 0;
+                } else
+                        brcmf_dbg(TRACE, "successfully configured (%d) ARP offload to 0x%x\n",
+                                  enable, mode);
+        }
+
+        return err;
+}
+
 static struct wireless_dev *brcmf_cfg80211_add_iface(struct wiphy *wiphy,
                                                      const char *name,
                                                      enum nl80211_iftype type,
@@ -2216,6 +2248,11 @@ brcmf_cfg80211_set_power_mgmt(struct wiphy *wiphy, struct net_device *ndev,
         }
 
         pm = enabled ? PM_FAST : PM_OFF;
+        /* Do not enable the power save after assoc if it is a p2p interface */
+        if (ifp->vif->wdev.iftype == NL80211_IFTYPE_P2P_CLIENT) {
+                brcmf_dbg(INFO, "Do not enable power save for P2P clients\n");
+                pm = PM_OFF;
+        }
         brcmf_dbg(INFO, "power save %s\n", (pm ? "enabled" : "disabled"));
 
         err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_PM, pm);
@@ -3640,10 +3677,28 @@ brcmf_config_ap_mgmt_ie(struct brcmf_cfg80211_vif *vif,
 }
 
 static s32
+brcmf_cfg80211_set_channel(struct brcmf_cfg80211_info *cfg,
+                           struct brcmf_if *ifp,
+                           struct ieee80211_channel *channel)
+{
+        u16 chanspec;
+        s32 err;
+
+        brcmf_dbg(TRACE, "band=%d, center_freq=%d\n", channel->band,
+                  channel->center_freq);
+
+        chanspec = channel_to_chanspec(&cfg->d11inf, channel);
+        err = brcmf_fil_iovar_int_set(ifp, "chanspec", chanspec);
+
+        return err;
+}
+
+static s32
 brcmf_cfg80211_start_ap(struct wiphy *wiphy, struct net_device *ndev,
                         struct cfg80211_ap_settings *settings)
 {
         s32 ie_offset;
+        struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
         struct brcmf_if *ifp = netdev_priv(ndev);
         struct brcmf_tlv *ssid_ie;
         struct brcmf_ssid_le ssid_le;
@@ -3683,6 +3738,7 @@ brcmf_cfg80211_start_ap(struct wiphy *wiphy, struct net_device *ndev,
         }
 
         brcmf_set_mpc(ifp, 0);
+        brcmf_configure_arp_offload(ifp, false);
 
         /* find the RSN_IE */
         rsn_ie = brcmf_parse_tlvs((u8 *)settings->beacon.tail,
@@ -3713,6 +3769,12 @@ brcmf_cfg80211_start_ap(struct wiphy *wiphy, struct net_device *ndev,
 
         brcmf_config_ap_mgmt_ie(ifp->vif, &settings->beacon);
 
+        err = brcmf_cfg80211_set_channel(cfg, ifp, settings->chandef.chan);
+        if (err < 0) {
+                brcmf_err("Set Channel failed, %d\n", err);
+                goto exit;
+        }
+
         if (settings->beacon_interval) {
                 err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_BCNPRD,
                                             settings->beacon_interval);
@@ -3789,8 +3851,10 @@ brcmf_cfg80211_start_ap(struct wiphy *wiphy, struct net_device *ndev,
         set_bit(BRCMF_VIF_STATUS_AP_CREATED, &ifp->vif->sme_state);
 
 exit:
-        if (err)
+        if (err) {
                 brcmf_set_mpc(ifp, 1);
+                brcmf_configure_arp_offload(ifp, true);
+        }
         return err;
 }
 
@@ -3831,6 +3895,7 @@ static int brcmf_cfg80211_stop_ap(struct wiphy *wiphy, struct net_device *ndev)
                         brcmf_err("bss_enable config failed %d\n", err);
         }
         brcmf_set_mpc(ifp, 1);
+        brcmf_configure_arp_offload(ifp, true);
         set_bit(BRCMF_VIF_STATUS_AP_CREATING, &ifp->vif->sme_state);
         clear_bit(BRCMF_VIF_STATUS_AP_CREATED, &ifp->vif->sme_state);
 
@@ -4148,7 +4213,7 @@ static const struct ieee80211_iface_limit brcmf_iface_limits[] = {
 static const struct ieee80211_iface_combination brcmf_iface_combos[] = {
         {
                  .max_interfaces = BRCMF_IFACE_MAX_CNT,
-                 .num_different_channels = 1, /* no multi-channel for now */
+                 .num_different_channels = 2,
                  .n_limits = ARRAY_SIZE(brcmf_iface_limits),
                  .limits = brcmf_iface_limits
         }
@@ -4256,20 +4321,16 @@ struct brcmf_cfg80211_vif *brcmf_alloc_vif(struct brcmf_cfg80211_info *cfg,
         return vif;
 }
 
-void brcmf_free_vif(struct brcmf_cfg80211_vif *vif)
+void brcmf_free_vif(struct brcmf_cfg80211_info *cfg,
+                    struct brcmf_cfg80211_vif *vif)
 {
-        struct brcmf_cfg80211_info *cfg;
-        struct wiphy *wiphy;
-
-        wiphy = vif->wdev.wiphy;
-        cfg = wiphy_priv(wiphy);
         list_del(&vif->list);
         cfg->vif_cnt--;
 
         kfree(vif);
         if (!cfg->vif_cnt) {
-                wiphy_unregister(wiphy);
-                wiphy_free(wiphy);
+                wiphy_unregister(cfg->wiphy);
+                wiphy_free(cfg->wiphy);
         }
 }
 
@@ -4646,7 +4707,6 @@ static s32 brcmf_notify_vif_event(struct brcmf_if *ifp,
                 return 0;
 
         case BRCMF_E_IF_DEL:
-                ifp->vif = NULL;
                 mutex_unlock(&event->vif_event_lock);
                 /* event may not be upon user request */
                 if (brcmf_cfg80211_vif_event_armed(cfg))
@@ -4852,8 +4912,7 @@ cfg80211_p2p_attach_out:
         wl_deinit_priv(cfg);
 
 cfg80211_attach_out:
-        brcmf_free_vif(vif);
-        wiphy_free(wiphy);
+        brcmf_free_vif(cfg, vif);
         return NULL;
 }
 
@@ -4865,7 +4924,7 @@ void brcmf_cfg80211_detach(struct brcmf_cfg80211_info *cfg)
         wl_deinit_priv(cfg);
         brcmf_btcoex_detach(cfg);
         list_for_each_entry_safe(vif, tmp, &cfg->vif_list, list) {
-                brcmf_free_vif(vif);
+                brcmf_free_vif(cfg, vif);
         }
 }
 
@@ -5229,6 +5288,8 @@ static s32 brcmf_config_dongle(struct brcmf_cfg80211_info *cfg)
         if (err)
                 goto default_conf_out;
 
+        brcmf_configure_arp_offload(ifp, true);
+
         cfg->dongle_up = true;
 default_conf_out:
 
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h
index a71cff84cdcf..d9bdaf9a72d0 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h
+++ b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h
@@ -487,7 +487,8 @@ enum nl80211_iftype brcmf_cfg80211_get_iftype(struct brcmf_if *ifp);
 struct brcmf_cfg80211_vif *brcmf_alloc_vif(struct brcmf_cfg80211_info *cfg,
                                            enum nl80211_iftype type,
                                            bool pm_block);
-void brcmf_free_vif(struct brcmf_cfg80211_vif *vif);
+void brcmf_free_vif(struct brcmf_cfg80211_info *cfg,
+                    struct brcmf_cfg80211_vif *vif);
 
 s32 brcmf_vif_set_mgmt_ie(struct brcmf_cfg80211_vif *vif, s32 pktflag,
                           const u8 *vndr_ie_buf, u32 vndr_ie_len);
diff --git a/drivers/net/wireless/iwlegacy/common.h b/drivers/net/wireless/iwlegacy/common.h
index f8246f2d88f9..4caaf52986a4 100644
--- a/drivers/net/wireless/iwlegacy/common.h
+++ b/drivers/net/wireless/iwlegacy/common.h
@@ -1832,16 +1832,16 @@ u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
 __le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
                           u32 beacon_interval);
 
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
 extern const struct dev_pm_ops il_pm_ops;
 
 #define IL_LEGACY_PM_OPS        (&il_pm_ops)
 
-#else /* !CONFIG_PM */
+#else /* !CONFIG_PM_SLEEP */
 
 #define IL_LEGACY_PM_OPS        NULL
 
-#endif /* !CONFIG_PM */
+#endif /* !CONFIG_PM_SLEEP */
 
 /*****************************************************
 *  Error Handling Debugging
diff --git a/drivers/net/wireless/iwlwifi/dvm/sta.c b/drivers/net/wireless/iwlwifi/dvm/sta.c
index db183b44e038..c3c13ce96eb0 100644
--- a/drivers/net/wireless/iwlwifi/dvm/sta.c
+++ b/drivers/net/wireless/iwlwifi/dvm/sta.c
@@ -735,7 +735,7 @@ void iwl_restore_stations(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
                                         memcpy(&lq, priv->stations[i].lq,
                                                sizeof(struct iwl_link_quality_cmd));
 
-                                if (!memcmp(&lq, &zero_lq, sizeof(lq)))
+                                if (memcmp(&lq, &zero_lq, sizeof(lq)))
                                         send_lq = true;
                         }
                         spin_unlock_bh(&priv->sta_lock);
diff --git a/drivers/net/wireless/mwifiex/debugfs.c b/drivers/net/wireless/mwifiex/debugfs.c
index 753b5682d53f..a5f9875cfd6e 100644
--- a/drivers/net/wireless/mwifiex/debugfs.c
+++ b/drivers/net/wireless/mwifiex/debugfs.c
@@ -26,10 +26,17 @@
 static struct dentry *mwifiex_dfs_dir;
 
 static char *bss_modes[] = {
-        "Unknown",
-        "Ad-hoc",
-        "Managed",
-        "Auto"
+        "UNSPECIFIED",
+        "ADHOC",
+        "STATION",
+        "AP",
+        "AP_VLAN",
+        "WDS",
+        "MONITOR",
+        "MESH_POINT",
+        "P2P_CLIENT",
+        "P2P_GO",
+        "P2P_DEVICE",
 };
 
 /* size/addr for mwifiex_debug_info */
@@ -200,7 +207,12 @@ mwifiex_info_read(struct file *file, char __user *ubuf,
         p += sprintf(p, "driver_version = %s", fmt);
         p += sprintf(p, "\nverext = %s", priv->version_str);
         p += sprintf(p, "\ninterface_name=\"%s\"\n", netdev->name);
-        p += sprintf(p, "bss_mode=\"%s\"\n", bss_modes[info.bss_mode]);
+
+        if (info.bss_mode >= ARRAY_SIZE(bss_modes))
+                p += sprintf(p, "bss_mode=\"%d\"\n", info.bss_mode);
+        else
+                p += sprintf(p, "bss_mode=\"%s\"\n", bss_modes[info.bss_mode]);
+
         p += sprintf(p, "media_state=\"%s\"\n",
                      (!priv->media_connected ? "Disconnected" : "Connected"));
         p += sprintf(p, "mac_address=\"%pM\"\n", netdev->dev_addr);
diff --git a/drivers/net/wireless/rtlwifi/pci.c b/drivers/net/wireless/rtlwifi/pci.c
index 999ffc12578b..c97e9d327331 100644
--- a/drivers/net/wireless/rtlwifi/pci.c
+++ b/drivers/net/wireless/rtlwifi/pci.c
@@ -764,6 +764,7 @@ static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
                                  "can't alloc skb for rx\n");
                         goto done;
                 }
+                kmemleak_not_leak(new_skb);
 
                 pci_unmap_single(rtlpci->pdev,
                                  *((dma_addr_t *) skb->cb),
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
index 3d0498e69c8c..189ba124a8c6 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
@@ -1973,26 +1973,35 @@ void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
         }
 }
 
-void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
-                                   struct ieee80211_sta *sta,
-                                   u8 rssi_level)
+static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
+                                          struct ieee80211_sta *sta)
 {
         struct rtl_priv *rtlpriv = rtl_priv(hw);
         struct rtl_phy *rtlphy = &(rtlpriv->phy);
         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
-        u32 ratr_value = (u32) mac->basic_rates;
-        u8 *mcsrate = mac->mcs;
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        u32 ratr_value;
         u8 ratr_index = 0;
         u8 nmode = mac->ht_enable;
-        u8 mimo_ps = 1;
-        u16 shortgi_rate = 0;
-        u32 tmp_ratr_value = 0;
+        u8 mimo_ps = IEEE80211_SMPS_OFF;
+        u16 shortgi_rate;
+        u32 tmp_ratr_value;
         u8 curtxbw_40mhz = mac->bw_40;
-        u8 curshortgi_40mhz = mac->sgi_40;
-        u8 curshortgi_20mhz = mac->sgi_20;
+        u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
+                               1 : 0;
+        u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
+                               1 : 0;
         enum wireless_mode wirelessmode = mac->mode;
 
-        ratr_value |= ((*(u16 *) (mcsrate))) << 12;
+        if (rtlhal->current_bandtype == BAND_ON_5G)
+                ratr_value = sta->supp_rates[1] << 4;
+        else
+                ratr_value = sta->supp_rates[0];
+        if (mac->opmode == NL80211_IFTYPE_ADHOC)
+                ratr_value = 0xfff;
+
+        ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
+                        sta->ht_cap.mcs.rx_mask[0] << 12);
         switch (wirelessmode) {
         case WIRELESS_MODE_B:
                 if (ratr_value & 0x0000000c)
@@ -2006,7 +2015,7 @@ void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
         case WIRELESS_MODE_N_24G:
         case WIRELESS_MODE_N_5G:
                 nmode = 1;
-                if (mimo_ps == 0) {
+                if (mimo_ps == IEEE80211_SMPS_STATIC) {
                         ratr_value &= 0x0007F005;
                 } else {
                         u32 ratr_mask;
@@ -2016,8 +2025,7 @@ void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
                                 ratr_mask = 0x000ff005;
                         else
                                 ratr_mask = 0x0f0ff005;
-                        if (curtxbw_40mhz)
-                                ratr_mask |= 0x00000010;
+
                         ratr_value &= ratr_mask;
                 }
                 break;
@@ -2026,41 +2034,74 @@ void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
                         ratr_value &= 0x000ff0ff;
                 else
                         ratr_value &= 0x0f0ff0ff;
+
                 break;
         }
+
         ratr_value &= 0x0FFFFFFF;
-        if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
-            (!curtxbw_40mhz && curshortgi_20mhz))) {
+
+        if (nmode && ((curtxbw_40mhz &&
+                         curshortgi_40mhz) || (!curtxbw_40mhz &&
+                                               curshortgi_20mhz))) {
+
                 ratr_value |= 0x10000000;
                 tmp_ratr_value = (ratr_value >> 12);
+
                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
                         if ((1 << shortgi_rate) & tmp_ratr_value)
                                 break;
                 }
+
                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
-                               (shortgi_rate << 4) | (shortgi_rate);
+                    (shortgi_rate << 4) | (shortgi_rate);
         }
+
         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
+
+        RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
+                 rtl_read_dword(rtlpriv, REG_ARFR0));
 }
 
-void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
+static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw,
+                                         struct ieee80211_sta *sta,
+                                         u8 rssi_level)
 {
         struct rtl_priv *rtlpriv = rtl_priv(hw);
         struct rtl_phy *rtlphy = &(rtlpriv->phy);
         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
-        u32 ratr_bitmap = (u32) mac->basic_rates;
-        u8 *p_mcsrate = mac->mcs;
-        u8 ratr_index = 0;
-        u8 curtxbw_40mhz = mac->bw_40;
-        u8 curshortgi_40mhz = mac->sgi_40;
-        u8 curshortgi_20mhz = mac->sgi_20;
-        enum wireless_mode wirelessmode = mac->mode;
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        struct rtl_sta_info *sta_entry = NULL;
+        u32 ratr_bitmap;
+        u8 ratr_index;
+        u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
+        u8 curshortgi_40mhz = curtxbw_40mhz &&
+                              (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
+                                1 : 0;
+        u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
+                                1 : 0;
+        enum wireless_mode wirelessmode = 0;
         bool shortgi = false;
         u8 rate_mask[5];
         u8 macid = 0;
-        u8 mimops = 1;
-
-        ratr_bitmap |= (p_mcsrate[1] << 20) | (p_mcsrate[0] << 12);
+        u8 mimo_ps = IEEE80211_SMPS_OFF;
+
+        sta_entry = (struct rtl_sta_info *) sta->drv_priv;
+        wirelessmode = sta_entry->wireless_mode;
+        if (mac->opmode == NL80211_IFTYPE_STATION ||
+            mac->opmode == NL80211_IFTYPE_MESH_POINT)
+                curtxbw_40mhz = mac->bw_40;
+        else if (mac->opmode == NL80211_IFTYPE_AP ||
+                mac->opmode == NL80211_IFTYPE_ADHOC)
+                macid = sta->aid + 1;
+
+        if (rtlhal->current_bandtype == BAND_ON_5G)
+                ratr_bitmap = sta->supp_rates[1] << 4;
+        else
+                ratr_bitmap = sta->supp_rates[0];
+        if (mac->opmode == NL80211_IFTYPE_ADHOC)
+                ratr_bitmap = 0xfff;
+        ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
+                        sta->ht_cap.mcs.rx_mask[0] << 12);
         switch (wirelessmode) {
         case WIRELESS_MODE_B:
                 ratr_index = RATR_INX_WIRELESS_B;
@@ -2071,6 +2112,7 @@ void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
                 break;
         case WIRELESS_MODE_G:
                 ratr_index = RATR_INX_WIRELESS_GB;
+
                 if (rssi_level == 1)
                         ratr_bitmap &= 0x00000f00;
                 else if (rssi_level == 2)
@@ -2085,7 +2127,8 @@ void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
         case WIRELESS_MODE_N_24G:
         case WIRELESS_MODE_N_5G:
                 ratr_index = RATR_INX_WIRELESS_NGB;
-                if (mimops == 0) {
+
+                if (mimo_ps == IEEE80211_SMPS_STATIC) {
                         if (rssi_level == 1)
                                 ratr_bitmap &= 0x00070000;
                         else if (rssi_level == 2)
@@ -2128,8 +2171,10 @@ void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
                                 }
                         }
                 }
+
                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
                     (!curtxbw_40mhz && curshortgi_20mhz)) {
+
                         if (macid == 0)
                                 shortgi = true;
                         else if (macid == 1)
@@ -2138,21 +2183,42 @@ void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
                 break;
         default:
                 ratr_index = RATR_INX_WIRELESS_NGB;
+
                 if (rtlphy->rf_type == RF_1T2R)
                         ratr_bitmap &= 0x000ff0ff;
                 else
                         ratr_bitmap &= 0x0f0ff0ff;
                 break;
         }
-        RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "ratr_bitmap :%x\n",
-                 ratr_bitmap);
-        *(u32 *)&rate_mask = ((ratr_bitmap & 0x0fffffff) |
-                                      ratr_index << 28);
+        sta_entry->ratr_index = ratr_index;
+
+        RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
+                 "ratr_bitmap :%x\n", ratr_bitmap);
+        *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
+                                     (ratr_index << 28);
         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
                  "Rate_index:%x, ratr_val:%x, %5phC\n",
                  ratr_index, ratr_bitmap, rate_mask);
-        rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
+        memcpy(rtlpriv->rate_mask, rate_mask, 5);
+        /* rtl92c_fill_h2c_cmd() does USB I/O and will result in a
+         * "scheduled while atomic" if called directly */
+        schedule_work(&rtlpriv->works.fill_h2c_cmd);
+
+        if (macid != 0)
+                sta_entry->ratr_index = ratr_index;
+}
+
+void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw,
+                                 struct ieee80211_sta *sta,
+                                 u8 rssi_level)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        if (rtlpriv->dm.useramask)
+                rtl92cu_update_hal_rate_mask(hw, sta, rssi_level);
+        else
+                rtl92cu_update_hal_rate_table(hw, sta);
 }
 
 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h
index f41a3aa4a26f..8e3ec1e25644 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h
@@ -98,10 +98,6 @@ void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
                                    u32 add_msr, u32 rm_msr);
 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
-void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
-                                   struct ieee80211_sta *sta,
-                                   u8 rssi_level);
-void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level);
 
 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw);
 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
index 85b6bdb163c0..da4f587199ee 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
@@ -289,14 +289,30 @@ void rtl92c_set_key(struct ieee80211_hw *hw, u32 key_index,
                                 macaddr = cam_const_broad;
                                 entry_id = key_index;
                         } else {
+                                if (mac->opmode == NL80211_IFTYPE_AP ||
+                                    mac->opmode == NL80211_IFTYPE_MESH_POINT) {
+                                        entry_id = rtl_cam_get_free_entry(hw,
+                                                                 p_macaddr);
+                                        if (entry_id >=  TOTAL_CAM_ENTRY) {
+                                                RT_TRACE(rtlpriv, COMP_SEC,
+                                                         DBG_EMERG,
+                                                         "Can not find free hw security cam entry\n");
+                                                return;
+                                        }
+                                } else {
+                                        entry_id = CAM_PAIRWISE_KEY_POSITION;
+                                }
+
                                 key_index = PAIRWISE_KEYIDX;
-                                entry_id = CAM_PAIRWISE_KEY_POSITION;
                                 is_pairwise = true;
                         }
                 }
                 if (rtlpriv->sec.key_len[key_index] == 0) {
                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
                                  "delete one entry\n");
+                        if (mac->opmode == NL80211_IFTYPE_AP ||
+                            mac->opmode == NL80211_IFTYPE_MESH_POINT)
+                                rtl_cam_del_entry(hw, p_macaddr);
                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
                 } else {
                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
index 938b1e670b93..826f085c29dd 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
@@ -106,8 +106,7 @@ static struct rtl_hal_ops rtl8192cu_hal_ops = {
         .update_interrupt_mask = rtl92cu_update_interrupt_mask,
         .get_hw_reg = rtl92cu_get_hw_reg,
         .set_hw_reg = rtl92cu_set_hw_reg,
-        .update_rate_tbl = rtl92cu_update_hal_rate_table,
-        .update_rate_mask = rtl92cu_update_hal_rate_mask,
+        .update_rate_tbl = rtl92cu_update_hal_rate_tbl,
         .fill_tx_desc = rtl92cu_tx_fill_desc,
         .fill_fake_txdesc = rtl92cu_fill_fake_txdesc,
         .fill_tx_cmddesc = rtl92cu_tx_fill_cmddesc,
@@ -137,6 +136,7 @@ static struct rtl_hal_ops rtl8192cu_hal_ops = {
         .phy_lc_calibrate = _rtl92cu_phy_lc_calibrate,
         .phy_set_bw_mode_callback = rtl92cu_phy_set_bw_mode_callback,
         .dm_dynamic_txpower = rtl92cu_dm_dynamic_txpower,
+        .fill_h2c_cmd = rtl92c_fill_h2c_cmd,
 };
 
 static struct rtl_mod_params rtl92cu_mod_params = {
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h
index a1310abd0d54..262e1e4c6e5b 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h
@@ -49,5 +49,8 @@ bool rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
 u32 rtl92cu_phy_query_rf_reg(struct ieee80211_hw *hw,
                             enum radio_path rfpath, u32 regaddr, u32 bitmask);
 void rtl92cu_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
+void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw,
+                                 struct ieee80211_sta *sta,
+                                 u8 rssi_level);
 
 #endif
diff --git a/drivers/net/wireless/rtlwifi/usb.c b/drivers/net/wireless/rtlwifi/usb.c
index 76732b0cd221..a3532e077871 100644
--- a/drivers/net/wireless/rtlwifi/usb.c
+++ b/drivers/net/wireless/rtlwifi/usb.c
@@ -824,6 +824,7 @@ static void rtl_usb_stop(struct ieee80211_hw *hw)
 
         /* should after adapter start and interrupt enable. */
         set_hal_stop(rtlhal);
+        cancel_work_sync(&rtlpriv->works.fill_h2c_cmd);
         /* Enable software */
         SET_USB_STOP(rtlusb);
         rtl_usb_deinit(hw);
@@ -1026,6 +1027,16 @@ static bool rtl_usb_tx_chk_waitq_insert(struct ieee80211_hw *hw,
         return false;
 }
 
+static void rtl_fill_h2c_cmd_work_callback(struct work_struct *work)
+{
+        struct rtl_works *rtlworks =
+            container_of(work, struct rtl_works, fill_h2c_cmd);
+        struct ieee80211_hw *hw = rtlworks->hw;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        rtlpriv->cfg->ops->fill_h2c_cmd(hw, H2C_RA_MASK, 5, rtlpriv->rate_mask);
+}
+
 static struct rtl_intf_ops rtl_usb_ops = {
         .adapter_start = rtl_usb_start,
         .adapter_stop = rtl_usb_stop,
@@ -1057,6 +1068,8 @@ int rtl_usb_probe(struct usb_interface *intf,
 
         /* this spin lock must be initialized early */
         spin_lock_init(&rtlpriv->locks.usb_lock);
+        INIT_WORK(&rtlpriv->works.fill_h2c_cmd,
+                  rtl_fill_h2c_cmd_work_callback);
 
         rtlpriv->usb_data_index = 0;
         init_completion(&rtlpriv->firmware_loading_complete);
diff --git a/drivers/net/wireless/rtlwifi/wifi.h b/drivers/net/wireless/rtlwifi/wifi.h
index 44328baa6389..cc03e7c87cbe 100644
--- a/drivers/net/wireless/rtlwifi/wifi.h
+++ b/drivers/net/wireless/rtlwifi/wifi.h
@@ -1736,6 +1736,8 @@ struct rtl_hal_ops {
         void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
                                              bool mstate);
         void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
+        void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
+                              u32 cmd_len, u8 *p_cmdbuffer);
 };
 
 struct rtl_intf_ops {
@@ -1869,6 +1871,7 @@ struct rtl_works {
         struct delayed_work fwevt_wq;
 
         struct work_struct lps_change_work;
+        struct work_struct fill_h2c_cmd;
 };
 
 struct rtl_debug {
@@ -2048,6 +2051,7 @@ struct rtl_priv {
                 };
         };
         bool enter_ps;  /* true when entering PS */
+        u8 rate_mask[5];
 
         /*This must be the last item so
            that it points to the data allocated
diff --git a/drivers/net/wireless/ti/wl12xx/scan.c b/drivers/net/wireless/ti/wl12xx/scan.c
index affdb3ec6225..4a0bbb13806b 100644
--- a/drivers/net/wireless/ti/wl12xx/scan.c
+++ b/drivers/net/wireless/ti/wl12xx/scan.c
@@ -310,7 +310,7 @@ static void wl12xx_adjust_channels(struct wl1271_cmd_sched_scan_config *cmd,
         memcpy(cmd->channels_2, cmd_channels->channels_2,
                sizeof(cmd->channels_2));
         memcpy(cmd->channels_5, cmd_channels->channels_5,
-               sizeof(cmd->channels_2));
+               sizeof(cmd->channels_5));
         /* channels_4 are not supported, so no need to copy them */
 }
 
diff --git a/drivers/net/wireless/ti/wl12xx/wl12xx.h b/drivers/net/wireless/ti/wl12xx/wl12xx.h
index 222d03540200..9e5484a73667 100644
--- a/drivers/net/wireless/ti/wl12xx/wl12xx.h
+++ b/drivers/net/wireless/ti/wl12xx/wl12xx.h
@@ -36,12 +36,12 @@
 #define WL127X_IFTYPE_SR_VER    3
 #define WL127X_MAJOR_SR_VER     10
 #define WL127X_SUBTYPE_SR_VER   WLCORE_FW_VER_IGNORE
-#define WL127X_MINOR_SR_VER     115
+#define WL127X_MINOR_SR_VER     133
 /* minimum multi-role FW version for wl127x */
 #define WL127X_IFTYPE_MR_VER    5
 #define WL127X_MAJOR_MR_VER     7
 #define WL127X_SUBTYPE_MR_VER   WLCORE_FW_VER_IGNORE
-#define WL127X_MINOR_MR_VER     115
+#define WL127X_MINOR_MR_VER     42
 
 /* FW chip version for wl128x */
 #define WL128X_CHIP_VER         7
@@ -49,7 +49,7 @@
 #define WL128X_IFTYPE_SR_VER    3
 #define WL128X_MAJOR_SR_VER     10
 #define WL128X_SUBTYPE_SR_VER   WLCORE_FW_VER_IGNORE
-#define WL128X_MINOR_SR_VER     115
+#define WL128X_MINOR_SR_VER     133
 /* minimum multi-role FW version for wl128x */
 #define WL128X_IFTYPE_MR_VER    5
 #define WL128X_MAJOR_MR_VER     7
diff --git a/drivers/net/wireless/ti/wl18xx/scan.c b/drivers/net/wireless/ti/wl18xx/scan.c
index 09d944505ac0..2b642f8c9266 100644
--- a/drivers/net/wireless/ti/wl18xx/scan.c
+++ b/drivers/net/wireless/ti/wl18xx/scan.c
@@ -34,7 +34,7 @@ static void wl18xx_adjust_channels(struct wl18xx_cmd_scan_params *cmd,
         memcpy(cmd->channels_2, cmd_channels->channels_2,
                sizeof(cmd->channels_2));
         memcpy(cmd->channels_5, cmd_channels->channels_5,
-               sizeof(cmd->channels_2));
+               sizeof(cmd->channels_5));
         /* channels_4 are not supported, so no need to copy them */
 }
 
diff --git a/drivers/net/xen-netback/netback.c b/drivers/net/xen-netback/netback.c
index 37984e6d4e99..8c20935d72c9 100644
--- a/drivers/net/xen-netback/netback.c
+++ b/drivers/net/xen-netback/netback.c
@@ -662,7 +662,7 @@ static void xen_netbk_rx_action(struct xen_netbk *netbk)
 {
         struct xenvif *vif = NULL, *tmp;
         s8 status;
-        u16 irq, flags;
+        u16 flags;
         struct xen_netif_rx_response *resp;
         struct sk_buff_head rxq;
         struct sk_buff *skb;
@@ -771,13 +771,13 @@ static void xen_netbk_rx_action(struct xen_netbk *netbk)
                                          sco->meta_slots_used);
 
                 RING_PUSH_RESPONSES_AND_CHECK_NOTIFY(&vif->rx, ret);
-                irq = vif->irq;
-                if (ret && list_empty(&vif->notify_list))
-                        list_add_tail(&vif->notify_list, &notify);
 
                 xenvif_notify_tx_completion(vif);
 
-                xenvif_put(vif);
+                if (ret && list_empty(&vif->notify_list))
+                        list_add_tail(&vif->notify_list, &notify);
+                else
+                        xenvif_put(vif);
                 npo.meta_cons += sco->meta_slots_used;
                 dev_kfree_skb(skb);
         }
@@ -785,6 +785,7 @@ static void xen_netbk_rx_action(struct xen_netbk *netbk)
         list_for_each_entry_safe(vif, tmp, &notify, notify_list) {
                 notify_remote_via_irq(vif->irq);
                 list_del_init(&vif->notify_list);
+                xenvif_put(vif);
         }
 
         /* More work to do? */
diff --git a/drivers/nfc/Kconfig b/drivers/nfc/Kconfig
index 4775d4e61b88..74a852e4e41f 100644
--- a/drivers/nfc/Kconfig
+++ b/drivers/nfc/Kconfig
@@ -28,7 +28,7 @@ config NFC_WILINK
 
 config NFC_MEI_PHY
         tristate "MEI bus NFC device support"
-        depends on INTEL_MEI_BUS_NFC && NFC_HCI
+        depends on INTEL_MEI && NFC_HCI
         help
           This adds support to use an mei bus nfc device. Select this if you
           will use an HCI NFC driver for an NFC chip connected behind an
diff --git a/drivers/nfc/mei_phy.c b/drivers/nfc/mei_phy.c
index b8f8abc422f0..1201bdbfb791 100644
--- a/drivers/nfc/mei_phy.c
+++ b/drivers/nfc/mei_phy.c
@@ -64,6 +64,15 @@ int nfc_mei_phy_enable(void *phy_id)
                 return r;
         }
 
+        r = mei_cl_register_event_cb(phy->device, nfc_mei_event_cb, phy);
+        if (r) {
+                pr_err("MEY_PHY: Event cb registration failed\n");
+                mei_cl_disable_device(phy->device);
+                phy->powered = 0;
+
+                return r;
+        }
+
         phy->powered = 1;
 
         return 0;
diff --git a/drivers/nfc/microread/mei.c b/drivers/nfc/microread/mei.c
index 1ad044dce7b6..cdf1bc53b257 100644
--- a/drivers/nfc/microread/mei.c
+++ b/drivers/nfc/microread/mei.c
@@ -43,24 +43,16 @@ static int microread_mei_probe(struct mei_cl_device *device,
                 return -ENOMEM;
         }
 
-        r = mei_cl_register_event_cb(device, nfc_mei_event_cb, phy);
-        if (r) {
-                pr_err(MICROREAD_DRIVER_NAME ": event cb registration failed\n");
-                goto err_out;
-        }
-
         r = microread_probe(phy, &mei_phy_ops, LLC_NOP_NAME,
                             MEI_NFC_HEADER_SIZE, 0, MEI_NFC_MAX_HCI_PAYLOAD,
                             &phy->hdev);
-        if (r < 0)
-                goto err_out;
-
-        return 0;
+        if (r < 0) {
+                nfc_mei_phy_free(phy);
 
-err_out:
-        nfc_mei_phy_free(phy);
+                return r;
+        }
 
-        return r;
+        return 0;
 }
 
 static int microread_mei_remove(struct mei_cl_device *device)
@@ -71,8 +63,6 @@ static int microread_mei_remove(struct mei_cl_device *device)
 
         microread_remove(phy->hdev);
 
-        nfc_mei_phy_disable(phy);
-
         nfc_mei_phy_free(phy);
 
         return 0;
diff --git a/drivers/nfc/pn544/mei.c b/drivers/nfc/pn544/mei.c
index 1eb48848a35a..b5d3d18179eb 100644
--- a/drivers/nfc/pn544/mei.c
+++ b/drivers/nfc/pn544/mei.c
@@ -43,24 +43,16 @@ static int pn544_mei_probe(struct mei_cl_device *device,
                 return -ENOMEM;
         }
 
-        r = mei_cl_register_event_cb(device, nfc_mei_event_cb, phy);
-        if (r) {
-                pr_err(PN544_DRIVER_NAME ": event cb registration failed\n");
-                goto err_out;
-        }
-
         r = pn544_hci_probe(phy, &mei_phy_ops, LLC_NOP_NAME,
                             MEI_NFC_HEADER_SIZE, 0, MEI_NFC_MAX_HCI_PAYLOAD,
                             &phy->hdev);
-        if (r < 0)
-                goto err_out;
-
-        return 0;
+        if (r < 0) {
+                nfc_mei_phy_free(phy);
 
-err_out:
-        nfc_mei_phy_free(phy);
+                return r;
+        }
 
-        return r;
+        return 0;
 }
 
 static int pn544_mei_remove(struct mei_cl_device *device)
@@ -71,8 +63,6 @@ static int pn544_mei_remove(struct mei_cl_device *device)
 
         pn544_hci_remove(phy->hdev);
 
-        nfc_mei_phy_disable(phy);
-
         nfc_mei_phy_free(phy);
 
         return 0;
diff --git a/drivers/of/address.c b/drivers/of/address.c
index 04da786c84d2..fdd0636a987d 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -227,6 +227,73 @@ int of_pci_address_to_resource(struct device_node *dev, int bar,
         return __of_address_to_resource(dev, addrp, size, flags, NULL, r);
 }
 EXPORT_SYMBOL_GPL(of_pci_address_to_resource);
+
+int of_pci_range_parser_init(struct of_pci_range_parser *parser,
+                                struct device_node *node)
+{
+        const int na = 3, ns = 2;
+        int rlen;
+
+        parser->node = node;
+        parser->pna = of_n_addr_cells(node);
+        parser->np = parser->pna + na + ns;
+
+        parser->range = of_get_property(node, "ranges", &rlen);
+        if (parser->range == NULL)
+                return -ENOENT;
+
+        parser->end = parser->range + rlen / sizeof(__be32);
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(of_pci_range_parser_init);
+
+struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser,
+                                                struct of_pci_range *range)
+{
+        const int na = 3, ns = 2;
+
+        if (!range)
+                return NULL;
+
+        if (!parser->range || parser->range + parser->np > parser->end)
+                return NULL;
+
+        range->pci_space = parser->range[0];
+        range->flags = of_bus_pci_get_flags(parser->range);
+        range->pci_addr = of_read_number(parser->range + 1, ns);
+        range->cpu_addr = of_translate_address(parser->node,
+                                parser->range + na);
+        range->size = of_read_number(parser->range + parser->pna + na, ns);
+
+        parser->range += parser->np;
+
+        /* Now consume following elements while they are contiguous */
+        while (parser->range + parser->np <= parser->end) {
+                u32 flags, pci_space;
+                u64 pci_addr, cpu_addr, size;
+
+                pci_space = be32_to_cpup(parser->range);
+                flags = of_bus_pci_get_flags(parser->range);
+                pci_addr = of_read_number(parser->range + 1, ns);
+                cpu_addr = of_translate_address(parser->node,
+                                parser->range + na);
+                size = of_read_number(parser->range + parser->pna + na, ns);
+
+                if (flags != range->flags)
+                        break;
+                if (pci_addr != range->pci_addr + range->size ||
+                    cpu_addr != range->cpu_addr + range->size)
+                        break;
+
+                range->size += size;
+                parser->range += parser->np;
+        }
+
+        return range;
+}
+EXPORT_SYMBOL_GPL(of_pci_range_parser_one);
+
 #endif /* CONFIG_PCI */
 
 /*
diff --git a/drivers/of/base.c b/drivers/of/base.c
index f53b992f060a..a6f584a7f4a1 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -192,14 +192,15 @@ EXPORT_SYMBOL(of_find_property);
 struct device_node *of_find_all_nodes(struct device_node *prev)
 {
         struct device_node *np;
+        unsigned long flags;
 
-        raw_spin_lock(&devtree_lock);
+        raw_spin_lock_irqsave(&devtree_lock, flags);
         np = prev ? prev->allnext : of_allnodes;
         for (; np != NULL; np = np->allnext)
                 if (of_node_get(np))
                         break;
         of_node_put(prev);
-        raw_spin_unlock(&devtree_lock);
+        raw_spin_unlock_irqrestore(&devtree_lock, flags);
         return np;
 }
 EXPORT_SYMBOL(of_find_all_nodes);
@@ -421,8 +422,9 @@ struct device_node *of_get_next_available_child(const struct device_node *node,
         struct device_node *prev)
 {
         struct device_node *next;
+        unsigned long flags;
 
-        raw_spin_lock(&devtree_lock);
+        raw_spin_lock_irqsave(&devtree_lock, flags);
         next = prev ? prev->sibling : node->child;
         for (; next; next = next->sibling) {
                 if (!__of_device_is_available(next))
@@ -431,7 +433,7 @@ struct device_node *of_get_next_available_child(const struct device_node *node,
                         break;
         }
         of_node_put(prev);
-        raw_spin_unlock(&devtree_lock);
+        raw_spin_unlock_irqrestore(&devtree_lock, flags);
         return next;
 }
 EXPORT_SYMBOL(of_get_next_available_child);
@@ -735,13 +737,14 @@ EXPORT_SYMBOL_GPL(of_modalias_node);
 struct device_node *of_find_node_by_phandle(phandle handle)
 {
         struct device_node *np;
+        unsigned long flags;
 
-        raw_spin_lock(&devtree_lock);
+        raw_spin_lock_irqsave(&devtree_lock, flags);
         for (np = of_allnodes; np; np = np->allnext)
                 if (np->phandle == handle)
                         break;
         of_node_get(np);
-        raw_spin_unlock(&devtree_lock);
+        raw_spin_unlock_irqrestore(&devtree_lock, flags);
         return np;
 }
 EXPORT_SYMBOL(of_find_node_by_phandle);
diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c
index 13e37e2d8ec1..42c687a820ac 100644
--- a/drivers/of/of_pci.c
+++ b/drivers/of/of_pci.c
@@ -5,14 +5,15 @@
 #include <asm/prom.h>
 
 static inline int __of_pci_pci_compare(struct device_node *node,
-                                       unsigned int devfn)
+                                       unsigned int data)
 {
-        unsigned int size;
-        const __be32 *reg = of_get_property(node, "reg", &size);
+        int devfn;
 
-        if (!reg || size < 5 * sizeof(__be32))
+        devfn = of_pci_get_devfn(node);
+        if (devfn < 0)
                 return 0;
-        return ((be32_to_cpup(&reg[0]) >> 8) & 0xff) == devfn;
+
+        return devfn == data;
 }
 
 struct device_node *of_pci_find_child_device(struct device_node *parent,
@@ -40,3 +41,51 @@ struct device_node *of_pci_find_child_device(struct device_node *parent,
         return NULL;
 }
 EXPORT_SYMBOL_GPL(of_pci_find_child_device);
+
+/**
+ * of_pci_get_devfn() - Get device and function numbers for a device node
+ * @np: device node
+ *
+ * Parses a standard 5-cell PCI resource and returns an 8-bit value that can
+ * be passed to the PCI_SLOT() and PCI_FUNC() macros to extract the device
+ * and function numbers respectively. On error a negative error code is
+ * returned.
+ */
+int of_pci_get_devfn(struct device_node *np)
+{
+        unsigned int size;
+        const __be32 *reg;
+
+        reg = of_get_property(np, "reg", &size);
+
+        if (!reg || size < 5 * sizeof(__be32))
+                return -EINVAL;
+
+        return (be32_to_cpup(reg) >> 8) & 0xff;
+}
+EXPORT_SYMBOL_GPL(of_pci_get_devfn);
+
+/**
+ * of_pci_parse_bus_range() - parse the bus-range property of a PCI device
+ * @node: device node
+ * @res: address to a struct resource to return the bus-range
+ *
+ * Returns 0 on success or a negative error-code on failure.
+ */
+int of_pci_parse_bus_range(struct device_node *node, struct resource *res)
+{
+        const __be32 *values;
+        int len;
+
+        values = of_get_property(node, "bus-range", &len);
+        if (!values || len < sizeof(*values) * 2)
+                return -EINVAL;
+
+        res->name = node->name;
+        res->start = be32_to_cpup(values++);
+        res->end = be32_to_cpup(values);
+        res->flags = IORESOURCE_BUS;
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(of_pci_parse_bus_range);
diff --git a/drivers/parisc/lba_pci.c b/drivers/parisc/lba_pci.c
index 2ef7103270bb..1f05913ae677 100644
--- a/drivers/parisc/lba_pci.c
+++ b/drivers/parisc/lba_pci.c
@@ -668,7 +668,7 @@ lba_fixup_bus(struct pci_bus *bus)
                         BUG();
                 }
 
-                if (ldev->hba.elmmio_space.start) {
+                if (ldev->hba.elmmio_space.flags) {
                         err = request_resource(&iomem_resource,
                                         &(ldev->hba.elmmio_space));
                         if (err < 0) {
@@ -993,7 +993,7 @@ lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
 
                 case PAT_LMMIO:
                         /* used to fix up pre-initialized MEM BARs */
-                        if (!lba_dev->hba.lmmio_space.start) {
+                        if (!lba_dev->hba.lmmio_space.flags) {
                                 sprintf(lba_dev->hba.lmmio_name,
                                                 "PCI%02x LMMIO",
                                                 (int)lba_dev->hba.bus_num.start);
@@ -1001,7 +1001,7 @@ lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
                                         io->start;
                                 r = &lba_dev->hba.lmmio_space;
                                 r->name = lba_dev->hba.lmmio_name;
-                        } else if (!lba_dev->hba.elmmio_space.start) {
+                        } else if (!lba_dev->hba.elmmio_space.flags) {
                                 sprintf(lba_dev->hba.elmmio_name,
                                                 "PCI%02x ELMMIO",
                                                 (int)lba_dev->hba.bus_num.start);
@@ -1096,6 +1096,7 @@ lba_legacy_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
         r->name = "LBA PCI Busses";
         r->start = lba_num & 0xff;
         r->end = (lba_num>>8) & 0xff;
+        r->flags = IORESOURCE_BUS;
 
         /* Set up local PCI Bus resources - we don't need them for
         ** Legacy boxes but it's nice to see in /proc/iomem.
@@ -1494,7 +1495,7 @@ lba_driver_probe(struct parisc_device *dev)
 
         pci_add_resource_offset(&resources, &lba_dev->hba.io_space,
                                 HBA_PORT_BASE(lba_dev->hba.hba_num));
-        if (lba_dev->hba.elmmio_space.start)
+        if (lba_dev->hba.elmmio_space.flags)
                 pci_add_resource_offset(&resources, &lba_dev->hba.elmmio_space,
                                         lba_dev->hba.lmmio_space_offset);
         if (lba_dev->hba.lmmio_space.flags)
diff --git a/drivers/parport/Kconfig b/drivers/parport/Kconfig
index 24e12d4d1769..a50576081b34 100644
--- a/drivers/parport/Kconfig
+++ b/drivers/parport/Kconfig
@@ -71,7 +71,7 @@ config PARPORT_PC_FIFO
 
 config PARPORT_PC_SUPERIO
         bool "SuperIO chipset support"
-        depends on PARPORT_PC
+        depends on PARPORT_PC && !PARISC
         help
           Saying Y here enables some probes for Super-IO chipsets in order to
           find out things like base addresses, IRQ lines and DMA channels.  It
diff --git a/drivers/parport/parport_gsc.c b/drivers/parport/parport_gsc.c
index a5251cb5fb0c..6e3a60c78873 100644
--- a/drivers/parport/parport_gsc.c
+++ b/drivers/parport/parport_gsc.c
@@ -234,7 +234,7 @@ static int parport_PS2_supported(struct parport *pb)
 
 struct parport *parport_gsc_probe_port(unsigned long base,
                                        unsigned long base_hi, int irq,
-                                       int dma, struct pci_dev *dev)
+                                       int dma, struct parisc_device *padev)
 {
         struct parport_gsc_private *priv;
         struct parport_operations *ops;
@@ -258,7 +258,6 @@ struct parport *parport_gsc_probe_port(unsigned long base,
         priv->ctr_writable = 0xff;
         priv->dma_buf = 0;
         priv->dma_handle = 0;
-        priv->dev = dev;
         p->base = base;
         p->base_hi = base_hi;
         p->irq = irq;
@@ -282,6 +281,7 @@ struct parport *parport_gsc_probe_port(unsigned long base,
                 return NULL;
         }
 
+        p->dev = &padev->dev;
         p->base_hi = base_hi;
         p->modes = tmp.modes;
         p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
@@ -373,7 +373,7 @@ static int parport_init_chip(struct parisc_device *dev)
         }
         
         p = parport_gsc_probe_port(port, 0, dev->irq,
-                        /* PARPORT_IRQ_NONE */ PARPORT_DMA_NONE, NULL);
+                        /* PARPORT_IRQ_NONE */ PARPORT_DMA_NONE, dev);
         if (p)
                 parport_count++;
         dev_set_drvdata(&dev->dev, p);
diff --git a/drivers/parport/parport_gsc.h b/drivers/parport/parport_gsc.h
index fc9c37c54022..812214768d27 100644
--- a/drivers/parport/parport_gsc.h
+++ b/drivers/parport/parport_gsc.h
@@ -217,6 +217,6 @@ extern void parport_gsc_dec_use_count(void);
 extern struct parport *parport_gsc_probe_port(unsigned long base,
                                                 unsigned long base_hi,
                                                 int irq, int dma,
-                                                struct pci_dev *dev);
+                                                struct parisc_device *padev);
 
 #endif  /* __DRIVERS_PARPORT_PARPORT_GSC_H */
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 6d51aa68ec7a..ac45398ebb8e 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -119,3 +119,5 @@ config PCI_IOAPIC
 config PCI_LABEL
         def_bool y if (DMI || ACPI)
         select NLS
+
+source "drivers/pci/host/Kconfig"
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 0c3efcffa83b..6ebf5bf8e7a7 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -67,3 +67,6 @@ obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen-pcifront.o
 obj-$(CONFIG_OF) += of.o
 
 ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG
+
+# PCI host controller drivers
+obj-y += host/
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
new file mode 100644
index 000000000000..1f1d67fec8b2
--- /dev/null
+++ b/drivers/pci/host/Kconfig
@@ -0,0 +1,8 @@
+menu "PCI host controller drivers"
+        depends on PCI
+
+config PCI_MVEBU
+        bool "Marvell EBU PCIe controller"
+        depends on ARCH_MVEBU || ARCH_KIRKWOOD
+
+endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
new file mode 100644
index 000000000000..5ea2d8bf013a
--- /dev/null
+++ b/drivers/pci/host/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
new file mode 100644
index 000000000000..13a633b1612e
--- /dev/null
+++ b/drivers/pci/host/pci-mvebu.c
@@ -0,0 +1,914 @@
+/*
+ * PCIe driver for Marvell Armada 370 and Armada XP SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/mbus.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/of_address.h>
+#include <linux/of_pci.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+/*
+ * PCIe unit register offsets.
+ */
+#define PCIE_DEV_ID_OFF         0x0000
+#define PCIE_CMD_OFF            0x0004
+#define PCIE_DEV_REV_OFF        0x0008
+#define PCIE_BAR_LO_OFF(n)      (0x0010 + ((n) << 3))
+#define PCIE_BAR_HI_OFF(n)      (0x0014 + ((n) << 3))
+#define PCIE_HEADER_LOG_4_OFF   0x0128
+#define PCIE_BAR_CTRL_OFF(n)    (0x1804 + (((n) - 1) * 4))
+#define PCIE_WIN04_CTRL_OFF(n)  (0x1820 + ((n) << 4))
+#define PCIE_WIN04_BASE_OFF(n)  (0x1824 + ((n) << 4))
+#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
+#define PCIE_WIN5_CTRL_OFF      0x1880
+#define PCIE_WIN5_BASE_OFF      0x1884
+#define PCIE_WIN5_REMAP_OFF     0x188c
+#define PCIE_CONF_ADDR_OFF      0x18f8
+#define  PCIE_CONF_ADDR_EN              0x80000000
+#define  PCIE_CONF_REG(r)               ((((r) & 0xf00) << 16) | ((r) & 0xfc))
+#define  PCIE_CONF_BUS(b)               (((b) & 0xff) << 16)
+#define  PCIE_CONF_DEV(d)               (((d) & 0x1f) << 11)
+#define  PCIE_CONF_FUNC(f)              (((f) & 0x7) << 8)
+#define  PCIE_CONF_ADDR(bus, devfn, where) \
+        (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn))    | \
+         PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
+         PCIE_CONF_ADDR_EN)
+#define PCIE_CONF_DATA_OFF      0x18fc
+#define PCIE_MASK_OFF           0x1910
+#define  PCIE_MASK_ENABLE_INTS          0x0f000000
+#define PCIE_CTRL_OFF           0x1a00
+#define  PCIE_CTRL_X1_MODE              0x0001
+#define PCIE_STAT_OFF           0x1a04
+#define  PCIE_STAT_BUS                  0xff00
+#define  PCIE_STAT_DEV                  0x1f0000
+#define  PCIE_STAT_LINK_DOWN            BIT(0)
+#define PCIE_DEBUG_CTRL         0x1a60
+#define  PCIE_DEBUG_SOFT_RESET          BIT(20)
+
+/*
+ * This product ID is registered by Marvell, and used when the Marvell
+ * SoC is not the root complex, but an endpoint on the PCIe bus. It is
+ * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
+ * bridge.
+ */
+#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
+
+/* PCI configuration space of a PCI-to-PCI bridge */
+struct mvebu_sw_pci_bridge {
+        u16 vendor;
+        u16 device;
+        u16 command;
+        u16 class;
+        u8 interface;
+        u8 revision;
+        u8 bist;
+        u8 header_type;
+        u8 latency_timer;
+        u8 cache_line_size;
+        u32 bar[2];
+        u8 primary_bus;
+        u8 secondary_bus;
+        u8 subordinate_bus;
+        u8 secondary_latency_timer;
+        u8 iobase;
+        u8 iolimit;
+        u16 secondary_status;
+        u16 membase;
+        u16 memlimit;
+        u16 prefmembase;
+        u16 prefmemlimit;
+        u32 prefbaseupper;
+        u32 preflimitupper;
+        u16 iobaseupper;
+        u16 iolimitupper;
+        u8 cappointer;
+        u8 reserved1;
+        u16 reserved2;
+        u32 romaddr;
+        u8 intline;
+        u8 intpin;
+        u16 bridgectrl;
+};
+
+struct mvebu_pcie_port;
+
+/* Structure representing all PCIe interfaces */
+struct mvebu_pcie {
+        struct platform_device *pdev;
+        struct mvebu_pcie_port *ports;
+        struct resource io;
+        struct resource realio;
+        struct resource mem;
+        struct resource busn;
+        int nports;
+};
+
+/* Structure representing one PCIe interface */
+struct mvebu_pcie_port {
+        char *name;
+        void __iomem *base;
+        spinlock_t conf_lock;
+        int haslink;
+        u32 port;
+        u32 lane;
+        int devfn;
+        struct clk *clk;
+        struct mvebu_sw_pci_bridge bridge;
+        struct device_node *dn;
+        struct mvebu_pcie *pcie;
+        phys_addr_t memwin_base;
+        size_t memwin_size;
+        phys_addr_t iowin_base;
+        size_t iowin_size;
+};
+
+static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
+{
+        return !(readl(port->base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
+}
+
+static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
+{
+        u32 stat;
+
+        stat = readl(port->base + PCIE_STAT_OFF);
+        stat &= ~PCIE_STAT_BUS;
+        stat |= nr << 8;
+        writel(stat, port->base + PCIE_STAT_OFF);
+}
+
+static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
+{
+        u32 stat;
+
+        stat = readl(port->base + PCIE_STAT_OFF);
+        stat &= ~PCIE_STAT_DEV;
+        stat |= nr << 16;
+        writel(stat, port->base + PCIE_STAT_OFF);
+}
+
+/*
+ * Setup PCIE BARs and Address Decode Wins:
+ * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
+ * WIN[0-3] -> DRAM bank[0-3]
+ */
+static void __init mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
+{
+        const struct mbus_dram_target_info *dram;
+        u32 size;
+        int i;
+
+        dram = mv_mbus_dram_info();
+
+        /* First, disable and clear BARs and windows. */
+        for (i = 1; i < 3; i++) {
+                writel(0, port->base + PCIE_BAR_CTRL_OFF(i));
+                writel(0, port->base + PCIE_BAR_LO_OFF(i));
+                writel(0, port->base + PCIE_BAR_HI_OFF(i));
+        }
+
+        for (i = 0; i < 5; i++) {
+                writel(0, port->base + PCIE_WIN04_CTRL_OFF(i));
+                writel(0, port->base + PCIE_WIN04_BASE_OFF(i));
+                writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
+        }
+
+        writel(0, port->base + PCIE_WIN5_CTRL_OFF);
+        writel(0, port->base + PCIE_WIN5_BASE_OFF);
+        writel(0, port->base + PCIE_WIN5_REMAP_OFF);
+
+        /* Setup windows for DDR banks.  Count total DDR size on the fly. */
+        size = 0;
+        for (i = 0; i < dram->num_cs; i++) {
+                const struct mbus_dram_window *cs = dram->cs + i;
+
+                writel(cs->base & 0xffff0000,
+                       port->base + PCIE_WIN04_BASE_OFF(i));
+                writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
+                writel(((cs->size - 1) & 0xffff0000) |
+                        (cs->mbus_attr << 8) |
+                        (dram->mbus_dram_target_id << 4) | 1,
+                       port->base + PCIE_WIN04_CTRL_OFF(i));
+
+                size += cs->size;
+        }
+
+        /* Round up 'size' to the nearest power of two. */
+        if ((size & (size - 1)) != 0)
+                size = 1 << fls(size);
+
+        /* Setup BAR[1] to all DRAM banks. */
+        writel(dram->cs[0].base, port->base + PCIE_BAR_LO_OFF(1));
+        writel(0, port->base + PCIE_BAR_HI_OFF(1));
+        writel(((size - 1) & 0xffff0000) | 1,
+               port->base + PCIE_BAR_CTRL_OFF(1));
+}
+
+static void __init mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
+{
+        u16 cmd;
+        u32 mask;
+
+        /* Point PCIe unit MBUS decode windows to DRAM space. */
+        mvebu_pcie_setup_wins(port);
+
+        /* Master + slave enable. */
+        cmd = readw(port->base + PCIE_CMD_OFF);
+        cmd |= PCI_COMMAND_IO;
+        cmd |= PCI_COMMAND_MEMORY;
+        cmd |= PCI_COMMAND_MASTER;
+        writew(cmd, port->base + PCIE_CMD_OFF);
+
+        /* Enable interrupt lines A-D. */
+        mask = readl(port->base + PCIE_MASK_OFF);
+        mask |= PCIE_MASK_ENABLE_INTS;
+        writel(mask, port->base + PCIE_MASK_OFF);
+}
+
+static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
+                                 struct pci_bus *bus,
+                                 u32 devfn, int where, int size, u32 *val)
+{
+        writel(PCIE_CONF_ADDR(bus->number, devfn, where),
+               port->base + PCIE_CONF_ADDR_OFF);
+
+        *val = readl(port->base + PCIE_CONF_DATA_OFF);
+
+        if (size == 1)
+                *val = (*val >> (8 * (where & 3))) & 0xff;
+        else if (size == 2)
+                *val = (*val >> (8 * (where & 3))) & 0xffff;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
+                                 struct pci_bus *bus,
+                                 u32 devfn, int where, int size, u32 val)
+{
+        int ret = PCIBIOS_SUCCESSFUL;
+
+        writel(PCIE_CONF_ADDR(bus->number, devfn, where),
+               port->base + PCIE_CONF_ADDR_OFF);
+
+        if (size == 4)
+                writel(val, port->base + PCIE_CONF_DATA_OFF);
+        else if (size == 2)
+                writew(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
+        else if (size == 1)
+                writeb(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
+        else
+                ret = PCIBIOS_BAD_REGISTER_NUMBER;
+
+        return ret;
+}
+
+static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
+{
+        phys_addr_t iobase;
+
+        /* Are the new iobase/iolimit values invalid? */
+        if (port->bridge.iolimit < port->bridge.iobase ||
+            port->bridge.iolimitupper < port->bridge.iobaseupper) {
+
+                /* If a window was configured, remove it */
+                if (port->iowin_base) {
+                        mvebu_mbus_del_window(port->iowin_base,
+                                              port->iowin_size);
+                        port->iowin_base = 0;
+                        port->iowin_size = 0;
+                }
+
+                return;
+        }
+
+        /*
+         * We read the PCI-to-PCI bridge emulated registers, and
+         * calculate the base address and size of the address decoding
+         * window to setup, according to the PCI-to-PCI bridge
+         * specifications. iobase is the bus address, port->iowin_base
+         * is the CPU address.
+         */
+        iobase = ((port->bridge.iobase & 0xF0) << 8) |
+                (port->bridge.iobaseupper << 16);
+        port->iowin_base = port->pcie->io.start + iobase;
+        port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
+                            (port->bridge.iolimitupper << 16)) -
+                            iobase);
+
+        mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base,
+                                          port->iowin_size,
+                                          iobase,
+                                          MVEBU_MBUS_PCI_IO);
+
+        pci_ioremap_io(iobase, port->iowin_base);
+}
+
+static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
+{
+        /* Are the new membase/memlimit values invalid? */
+        if (port->bridge.memlimit < port->bridge.membase) {
+
+                /* If a window was configured, remove it */
+                if (port->memwin_base) {
+                        mvebu_mbus_del_window(port->memwin_base,
+                                              port->memwin_size);
+                        port->memwin_base = 0;
+                        port->memwin_size = 0;
+                }
+
+                return;
+        }
+
+        /*
+         * We read the PCI-to-PCI bridge emulated registers, and
+         * calculate the base address and size of the address decoding
+         * window to setup, according to the PCI-to-PCI bridge
+         * specifications.
+         */
+        port->memwin_base  = ((port->bridge.membase & 0xFFF0) << 16);
+        port->memwin_size  =
+                (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
+                port->memwin_base;
+
+        mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base,
+                                          port->memwin_size,
+                                          MVEBU_MBUS_NO_REMAP,
+                                          MVEBU_MBUS_PCI_MEM);
+}
+
+/*
+ * Initialize the configuration space of the PCI-to-PCI bridge
+ * associated with the given PCIe interface.
+ */
+static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
+{
+        struct mvebu_sw_pci_bridge *bridge = &port->bridge;
+
+        memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
+
+        bridge->class = PCI_CLASS_BRIDGE_PCI;
+        bridge->vendor = PCI_VENDOR_ID_MARVELL;
+        bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
+        bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
+        bridge->cache_line_size = 0x10;
+
+        /* We support 32 bits I/O addressing */
+        bridge->iobase = PCI_IO_RANGE_TYPE_32;
+        bridge->iolimit = PCI_IO_RANGE_TYPE_32;
+}
+
+/*
+ * Read the configuration space of the PCI-to-PCI bridge associated to
+ * the given PCIe interface.
+ */
+static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
+                                  unsigned int where, int size, u32 *value)
+{
+        struct mvebu_sw_pci_bridge *bridge = &port->bridge;
+
+        switch (where & ~3) {
+        case PCI_VENDOR_ID:
+                *value = bridge->device << 16 | bridge->vendor;
+                break;
+
+        case PCI_COMMAND:
+                *value = bridge->command;
+                break;
+
+        case PCI_CLASS_REVISION:
+                *value = bridge->class << 16 | bridge->interface << 8 |
+                         bridge->revision;
+                break;
+
+        case PCI_CACHE_LINE_SIZE:
+                *value = bridge->bist << 24 | bridge->header_type << 16 |
+                         bridge->latency_timer << 8 | bridge->cache_line_size;
+                break;
+
+        case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
+                *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
+                break;
+
+        case PCI_PRIMARY_BUS:
+                *value = (bridge->secondary_latency_timer << 24 |
+                          bridge->subordinate_bus         << 16 |
+                          bridge->secondary_bus           <<  8 |
+                          bridge->primary_bus);
+                break;
+
+        case PCI_IO_BASE:
+                *value = (bridge->secondary_status << 16 |
+                          bridge->iolimit          <<  8 |
+                          bridge->iobase);
+                break;
+
+        case PCI_MEMORY_BASE:
+                *value = (bridge->memlimit << 16 | bridge->membase);
+                break;
+
+        case PCI_PREF_MEMORY_BASE:
+                *value = (bridge->prefmemlimit << 16 | bridge->prefmembase);
+                break;
+
+        case PCI_PREF_BASE_UPPER32:
+                *value = bridge->prefbaseupper;
+                break;
+
+        case PCI_PREF_LIMIT_UPPER32:
+                *value = bridge->preflimitupper;
+                break;
+
+        case PCI_IO_BASE_UPPER16:
+                *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
+                break;
+
+        case PCI_ROM_ADDRESS1:
+                *value = 0;
+                break;
+
+        default:
+                *value = 0xffffffff;
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+        }
+
+        if (size == 2)
+                *value = (*value >> (8 * (where & 3))) & 0xffff;
+        else if (size == 1)
+                *value = (*value >> (8 * (where & 3))) & 0xff;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+/* Write to the PCI-to-PCI bridge configuration space */
+static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
+                                     unsigned int where, int size, u32 value)
+{
+        struct mvebu_sw_pci_bridge *bridge = &port->bridge;
+        u32 mask, reg;
+        int err;
+
+        if (size == 4)
+                mask = 0x0;
+        else if (size == 2)
+                mask = ~(0xffff << ((where & 3) * 8));
+        else if (size == 1)
+                mask = ~(0xff << ((where & 3) * 8));
+        else
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+
+        err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, &reg);
+        if (err)
+                return err;
+
+        value = (reg & mask) | value << ((where & 3) * 8);
+
+        switch (where & ~3) {
+        case PCI_COMMAND:
+                bridge->command = value & 0xffff;
+                break;
+
+        case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
+                bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
+                break;
+
+        case PCI_IO_BASE:
+                /*
+                 * We also keep bit 1 set, it is a read-only bit that
+                 * indicates we support 32 bits addressing for the
+                 * I/O
+                 */
+                bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
+                bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
+                bridge->secondary_status = value >> 16;
+                mvebu_pcie_handle_iobase_change(port);
+                break;
+
+        case PCI_MEMORY_BASE:
+                bridge->membase = value & 0xffff;
+                bridge->memlimit = value >> 16;
+                mvebu_pcie_handle_membase_change(port);
+                break;
+
+        case PCI_PREF_MEMORY_BASE:
+                bridge->prefmembase = value & 0xffff;
+                bridge->prefmemlimit = value >> 16;
+                break;
+
+        case PCI_PREF_BASE_UPPER32:
+                bridge->prefbaseupper = value;
+                break;
+
+        case PCI_PREF_LIMIT_UPPER32:
+                bridge->preflimitupper = value;
+                break;
+
+        case PCI_IO_BASE_UPPER16:
+                bridge->iobaseupper = value & 0xffff;
+                bridge->iolimitupper = value >> 16;
+                mvebu_pcie_handle_iobase_change(port);
+                break;
+
+        case PCI_PRIMARY_BUS:
+                bridge->primary_bus             = value & 0xff;
+                bridge->secondary_bus           = (value >> 8) & 0xff;
+                bridge->subordinate_bus         = (value >> 16) & 0xff;
+                bridge->secondary_latency_timer = (value >> 24) & 0xff;
+                mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
+                break;
+
+        default:
+                break;
+        }
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
+{
+        return sys->private_data;
+}
+
+static struct mvebu_pcie_port *
+mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
+                     int devfn)
+{
+        int i;
+
+        for (i = 0; i < pcie->nports; i++) {
+                struct mvebu_pcie_port *port = &pcie->ports[i];
+                if (bus->number == 0 && port->devfn == devfn)
+                        return port;
+                if (bus->number != 0 &&
+                    bus->number >= port->bridge.secondary_bus &&
+                    bus->number <= port->bridge.subordinate_bus)
+                        return port;
+        }
+
+        return NULL;
+}
+
+/* PCI configuration space write function */
+static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
+                              int where, int size, u32 val)
+{
+        struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
+        struct mvebu_pcie_port *port;
+        unsigned long flags;
+        int ret;
+
+        port = mvebu_pcie_find_port(pcie, bus, devfn);
+        if (!port)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        /* Access the emulated PCI-to-PCI bridge */
+        if (bus->number == 0)
+                return mvebu_sw_pci_bridge_write(port, where, size, val);
+
+        if (!port->haslink)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        /*
+         * On the secondary bus, we don't want to expose any other
+         * device than the device physically connected in the PCIe
+         * slot, visible in slot 0. In slot 1, there's a special
+         * Marvell device that only makes sense when the Armada is
+         * used as a PCIe endpoint.
+         */
+        if (bus->number == port->bridge.secondary_bus &&
+            PCI_SLOT(devfn) != 0)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        /* Access the real PCIe interface */
+        spin_lock_irqsave(&port->conf_lock, flags);
+        ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
+                                    where, size, val);
+        spin_unlock_irqrestore(&port->conf_lock, flags);
+
+        return ret;
+}
+
+/* PCI configuration space read function */
+static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+                              int size, u32 *val)
+{
+        struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
+        struct mvebu_pcie_port *port;
+        unsigned long flags;
+        int ret;
+
+        port = mvebu_pcie_find_port(pcie, bus, devfn);
+        if (!port) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        /* Access the emulated PCI-to-PCI bridge */
+        if (bus->number == 0)
+                return mvebu_sw_pci_bridge_read(port, where, size, val);
+
+        if (!port->haslink) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        /*
+         * On the secondary bus, we don't want to expose any other
+         * device than the device physically connected in the PCIe
+         * slot, visible in slot 0. In slot 1, there's a special
+         * Marvell device that only makes sense when the Armada is
+         * used as a PCIe endpoint.
+         */
+        if (bus->number == port->bridge.secondary_bus &&
+            PCI_SLOT(devfn) != 0) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        /* Access the real PCIe interface */
+        spin_lock_irqsave(&port->conf_lock, flags);
+        ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
+                                    where, size, val);
+        spin_unlock_irqrestore(&port->conf_lock, flags);
+
+        return ret;
+}
+
+static struct pci_ops mvebu_pcie_ops = {
+        .read = mvebu_pcie_rd_conf,
+        .write = mvebu_pcie_wr_conf,
+};
+
+static int __init mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+        struct mvebu_pcie *pcie = sys_to_pcie(sys);
+        int i;
+
+        pci_add_resource_offset(&sys->resources, &pcie->realio, sys->io_offset);
+        pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
+        pci_add_resource(&sys->resources, &pcie->busn);
+
+        for (i = 0; i < pcie->nports; i++) {
+                struct mvebu_pcie_port *port = &pcie->ports[i];
+                mvebu_pcie_setup_hw(port);
+        }
+
+        return 1;
+}
+
+static int __init mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        struct of_irq oirq;
+        int ret;
+
+        ret = of_irq_map_pci(dev, &oirq);
+        if (ret)
+                return ret;
+
+        return irq_create_of_mapping(oirq.controller, oirq.specifier,
+                                     oirq.size);
+}
+
+static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        struct mvebu_pcie *pcie = sys_to_pcie(sys);
+        struct pci_bus *bus;
+
+        bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
+                                  &mvebu_pcie_ops, sys, &sys->resources);
+        if (!bus)
+                return NULL;
+
+        pci_scan_child_bus(bus);
+
+        return bus;
+}
+
+resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
+                                          const struct resource *res,
+                                          resource_size_t start,
+                                          resource_size_t size,
+                                          resource_size_t align)
+{
+        if (dev->bus->number != 0)
+                return start;
+
+        /*
+         * On the PCI-to-PCI bridge side, the I/O windows must have at
+         * least a 64 KB size and be aligned on their size, and the
+         * memory windows must have at least a 1 MB size and be
+         * aligned on their size
+         */
+        if (res->flags & IORESOURCE_IO)
+                return round_up(start, max((resource_size_t)SZ_64K, size));
+        else if (res->flags & IORESOURCE_MEM)
+                return round_up(start, max((resource_size_t)SZ_1M, size));
+        else
+                return start;
+}
+
+static void __init mvebu_pcie_enable(struct mvebu_pcie *pcie)
+{
+        struct hw_pci hw;
+
+        memset(&hw, 0, sizeof(hw));
+
+        hw.nr_controllers = 1;
+        hw.private_data   = (void **)&pcie;
+        hw.setup          = mvebu_pcie_setup;
+        hw.scan           = mvebu_pcie_scan_bus;
+        hw.map_irq        = mvebu_pcie_map_irq;
+        hw.ops            = &mvebu_pcie_ops;
+        hw.align_resource = mvebu_pcie_align_resource;
+
+        pci_common_init(&hw);
+}
+
+/*
+ * Looks up the list of register addresses encoded into the reg =
+ * <...> property for one that matches the given port/lane. Once
+ * found, maps it.
+ */
+static void __iomem * __init
+mvebu_pcie_map_registers(struct platform_device *pdev,
+                         struct device_node *np,
+                         struct mvebu_pcie_port *port)
+{
+        struct resource regs;
+        int ret = 0;
+
+        ret = of_address_to_resource(np, 0, &regs);
+        if (ret)
+                return NULL;
+
+        return devm_request_and_ioremap(&pdev->dev, &regs);
+}
+
+static int __init mvebu_pcie_probe(struct platform_device *pdev)
+{
+        struct mvebu_pcie *pcie;
+        struct device_node *np = pdev->dev.of_node;
+        struct of_pci_range range;
+        struct of_pci_range_parser parser;
+        struct device_node *child;
+        int i, ret;
+
+        pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
+                            GFP_KERNEL);
+        if (!pcie)
+                return -ENOMEM;
+
+        pcie->pdev = pdev;
+
+        if (of_pci_range_parser_init(&parser, np))
+                return -EINVAL;
+
+        /* Get the I/O and memory ranges from DT */
+        for_each_of_pci_range(&parser, &range) {
+                unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
+                if (restype == IORESOURCE_IO) {
+                        of_pci_range_to_resource(&range, np, &pcie->io);
+                        of_pci_range_to_resource(&range, np, &pcie->realio);
+                        pcie->io.name = "I/O";
+                        pcie->realio.start = max_t(resource_size_t,
+                                                   PCIBIOS_MIN_IO,
+                                                   range.pci_addr);
+                        pcie->realio.end = min_t(resource_size_t,
+                                                 IO_SPACE_LIMIT,
+                                                 range.pci_addr + range.size);
+                }
+                if (restype == IORESOURCE_MEM) {
+                        of_pci_range_to_resource(&range, np, &pcie->mem);
+                        pcie->mem.name = "MEM";
+                }
+        }
+
+        /* Get the bus range */
+        ret = of_pci_parse_bus_range(np, &pcie->busn);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
+                        ret);
+                return ret;
+        }
+
+        for_each_child_of_node(pdev->dev.of_node, child) {
+                if (!of_device_is_available(child))
+                        continue;
+                pcie->nports++;
+        }
+
+        pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports *
+                                   sizeof(struct mvebu_pcie_port),
+                                   GFP_KERNEL);
+        if (!pcie->ports)
+                return -ENOMEM;
+
+        i = 0;
+        for_each_child_of_node(pdev->dev.of_node, child) {
+                struct mvebu_pcie_port *port = &pcie->ports[i];
+
+                if (!of_device_is_available(child))
+                        continue;
+
+                port->pcie = pcie;
+
+                if (of_property_read_u32(child, "marvell,pcie-port",
+                                         &port->port)) {
+                        dev_warn(&pdev->dev,
+                                 "ignoring PCIe DT node, missing pcie-port property\n");
+                        continue;
+                }
+
+                if (of_property_read_u32(child, "marvell,pcie-lane",
+                                         &port->lane))
+                        port->lane = 0;
+
+                port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
+                                       port->port, port->lane);
+
+                port->devfn = of_pci_get_devfn(child);
+                if (port->devfn < 0)
+                        continue;
+
+                port->base = mvebu_pcie_map_registers(pdev, child, port);
+                if (!port->base) {
+                        dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
+                                port->port, port->lane);
+                        continue;
+                }
+
+                mvebu_pcie_set_local_dev_nr(port, 1);
+
+                if (mvebu_pcie_link_up(port)) {
+                        port->haslink = 1;
+                        dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
+                                 port->port, port->lane);
+                } else {
+                        port->haslink = 0;
+                        dev_info(&pdev->dev, "PCIe%d.%d: link down\n",
+                                 port->port, port->lane);
+                }
+
+                port->clk = of_clk_get_by_name(child, NULL);
+                if (IS_ERR(port->clk)) {
+                        dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
+                               port->port, port->lane);
+                        iounmap(port->base);
+                        port->haslink = 0;
+                        continue;
+                }
+
+                port->dn = child;
+
+                clk_prepare_enable(port->clk);
+                spin_lock_init(&port->conf_lock);
+
+                mvebu_sw_pci_bridge_init(port);
+
+                i++;
+        }
+
+        mvebu_pcie_enable(pcie);
+
+        return 0;
+}
+
+static const struct of_device_id mvebu_pcie_of_match_table[] = {
+        { .compatible = "marvell,armada-xp-pcie", },
+        { .compatible = "marvell,armada-370-pcie", },
+        { .compatible = "marvell,kirkwood-pcie", },
+        {},
+};
+MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
+
+static struct platform_driver mvebu_pcie_driver = {
+        .driver = {
+                .owner = THIS_MODULE,
+                .name = "mvebu-pcie",
+                .of_match_table =
+                   of_match_ptr(mvebu_pcie_of_match_table),
+        },
+};
+
+static int __init mvebu_pcie_init(void)
+{
+        return platform_driver_probe(&mvebu_pcie_driver,
+                                     mvebu_pcie_probe);
+}
+
+subsys_initcall(mvebu_pcie_init);
+
+MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
+MODULE_DESCRIPTION("Marvell EBU PCIe driver");
+MODULE_LICENSE("GPLv2");
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c
index 8ec8b4f48560..0f4554e48cc5 100644
--- a/drivers/pci/pcie/aer/aerdrv_core.c
+++ b/drivers/pci/pcie/aer/aerdrv_core.c
@@ -580,6 +580,7 @@ struct aer_recover_entry
         u8      devfn;
         u16     domain;
         int     severity;
+        struct aer_capability_regs *regs;
 };
 
 static DEFINE_KFIFO(aer_recover_ring, struct aer_recover_entry,
@@ -593,7 +594,7 @@ static DEFINE_SPINLOCK(aer_recover_ring_lock);
 static DECLARE_WORK(aer_recover_work, aer_recover_work_func);
 
 void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
-                       int severity)
+                       int severity, struct aer_capability_regs *aer_regs)
 {
         unsigned long flags;
         struct aer_recover_entry entry = {
@@ -601,6 +602,7 @@ void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
                 .devfn          = devfn,
                 .domain         = domain,
                 .severity       = severity,
+                .regs           = aer_regs,
         };
 
         spin_lock_irqsave(&aer_recover_ring_lock, flags);
@@ -627,6 +629,7 @@ static void aer_recover_work_func(struct work_struct *work)
                                PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn));
                         continue;
                 }
+                cper_print_aer(pdev, entry.severity, entry.regs);
                 do_recovery(pdev, entry.severity);
                 pci_dev_put(pdev);
         }
diff --git a/drivers/pci/pcie/aer/aerdrv_errprint.c b/drivers/pci/pcie/aer/aerdrv_errprint.c
index 5ab14251839d..2c7c9f5f592c 100644
--- a/drivers/pci/pcie/aer/aerdrv_errprint.c
+++ b/drivers/pci/pcie/aer/aerdrv_errprint.c
@@ -220,7 +220,7 @@ int cper_severity_to_aer(int cper_severity)
 }
 EXPORT_SYMBOL_GPL(cper_severity_to_aer);
 
-void cper_print_aer(const char *prefix, struct pci_dev *dev, int cper_severity,
+void cper_print_aer(struct pci_dev *dev, int cper_severity,
                     struct aer_capability_regs *aer)
 {
         int aer_severity, layer, agent, status_strs_size, tlp_header_valid = 0;
@@ -244,7 +244,7 @@ void cper_print_aer(const char *prefix, struct pci_dev *dev, int cper_severity,
         agent = AER_GET_AGENT(aer_severity, status);
         dev_err(&dev->dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n",
                status, mask);
-        cper_print_bits(prefix, status, status_strs, status_strs_size);
+        cper_print_bits("", status, status_strs, status_strs_size);
         dev_err(&dev->dev, "aer_layer=%s, aer_agent=%s\n",
                aer_error_layer[layer], aer_agent_string[agent]);
         if (aer_severity != AER_CORRECTABLE)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 8f6692438149..a1c6dd32e14b 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -207,12 +207,13 @@ config PINCTRL_SAMSUNG
         select PINCONF
 
 config PINCTRL_EXYNOS
-        bool "Pinctrl driver data for Samsung EXYNOS SoCs"
-        depends on OF && GPIOLIB
+        bool "Pinctrl driver data for Samsung EXYNOS SoCs other than 5440"
+        depends on OF && GPIOLIB && ARCH_EXYNOS
         select PINCTRL_SAMSUNG
 
 config PINCTRL_EXYNOS5440
         bool "Samsung EXYNOS5440 SoC pinctrl driver"
+        depends on SOC_EXYNOS5440
         select PINMUX
         select PINCONF
 
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index c67c37e23dd7..694c3ace4520 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -610,7 +610,7 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
         bool found = false;
         unsigned long config;
 
-        mutex_lock(&pctldev->mutex);
+        mutex_lock(&pinctrl_maps_mutex);
 
         /* Parse the pinctrl map and look for the elected pin/state */
         for_each_maps(maps_node, i, map) {
@@ -659,7 +659,7 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
                 confops->pin_config_config_dbg_show(pctldev, s, config);
 
 exit:
-        mutex_unlock(&pctldev->mutex);
+        mutex_unlock(&pinctrl_maps_mutex);
 
         return 0;
 }
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index a67af419f531..eeff7f7fc920 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -22,7 +22,6 @@
 #include <linux/slab.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/pinctrl/pinconf-generic.h>
-#include <linux/platform_data/pinctrl-coh901.h>
 #include "pinctrl-coh901.h"
 
 #define U300_GPIO_PORT_STRIDE                           (0x30)
@@ -58,8 +57,9 @@
 #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE          (0x00000001UL)
 
 /* 8 bits per port, no version has more than 7 ports */
+#define U300_GPIO_NUM_PORTS 7
 #define U300_GPIO_PINS_PER_PORT 8
-#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7)
+#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS)
 
 struct u300_gpio {
         struct gpio_chip chip;
@@ -111,9 +111,6 @@ struct u300_gpio_confdata {
         int outval;
 };
 
-/* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
-#define BS335_GPIO_NUM_PORTS 7
-
 #define U300_FLOATING_INPUT { \
         .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
         .output = false, \
@@ -136,7 +133,7 @@ struct u300_gpio_confdata {
 
 /* Initial configuration */
 static const struct __initconst u300_gpio_confdata
-bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
+bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
         /* Port 0, pins 0-7 */
         {
                 U300_FLOATING_INPUT,
@@ -630,13 +627,12 @@ static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
         }
 }
 
-static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
-                                     struct u300_gpio_platform *plat)
+static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio)
 {
         int i, j;
 
         /* Write default config and values to all pins */
-        for (i = 0; i < plat->ports; i++) {
+        for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
                 for (j = 0; j < 8; j++) {
                         const struct u300_gpio_confdata *conf;
                         int offset = (i*8) + j;
@@ -693,7 +689,6 @@ static struct coh901_pinpair coh901_pintable[] = {
 
 static int __init u300_gpio_probe(struct platform_device *pdev)
 {
-        struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
         struct u300_gpio *gpio;
         struct resource *memres;
         int err = 0;
@@ -707,9 +702,9 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
                 return -ENOMEM;
 
         gpio->chip = u300_gpio_chip;
-        gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT;
+        gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT;
         gpio->chip.dev = &pdev->dev;
-        gpio->chip.base = plat->gpio_base;
+        gpio->chip.base = 0;
         gpio->dev = &pdev->dev;
 
         memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -750,11 +745,11 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
                  ((val & 0x0000FE00) >> 9) * 8);
         writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
                gpio->base + U300_GPIO_CR);
-        u300_gpio_init_coh901571(gpio, plat);
+        u300_gpio_init_coh901571(gpio);
 
         /* Add each port with its IRQ separately */
         INIT_LIST_HEAD(&gpio->port_list);
-        for (portno = 0 ; portno < plat->ports; portno++) {
+        for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) {
                 struct u300_gpio_port *port =
                         kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL);
 
@@ -768,8 +763,7 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
                 port->number = portno;
                 port->gpio = gpio;
 
-                port->irq = platform_get_irq_byname(pdev,
-                                                    port->name);
+                port->irq = platform_get_irq(pdev, portno);
 
                 dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq,
                         port->name);
@@ -806,6 +800,9 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
         }
         dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
 
+#ifdef CONFIG_OF_GPIO
+        gpio->chip.of_node = pdev->dev.of_node;
+#endif
         err = gpiochip_add(&gpio->chip);
         if (err) {
                 dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
@@ -830,7 +827,8 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
         return 0;
 
 err_no_range:
-        err = gpiochip_remove(&gpio->chip);
+        if (gpiochip_remove(&gpio->chip))
+                dev_err(&pdev->dev, "failed to remove gpio chip\n");
 err_no_chip:
 err_no_domain:
 err_no_port:
@@ -859,9 +857,15 @@ static int __exit u300_gpio_remove(struct platform_device *pdev)
         return 0;
 }
 
+static const struct of_device_id u300_gpio_match[] = {
+        { .compatible = "stericsson,gpio-coh901" },
+        {},
+};
+
 static struct platform_driver u300_gpio_driver = {
         .driver         = {
                 .name   = "u300-gpio",
+                .of_match_table = u300_gpio_match,
         },
         .remove         = __exit_p(u300_gpio_remove),
 };
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index ac742817ebce..2d76f66a2e0b 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -196,6 +196,12 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
         return IRQ_HANDLED;
 }
 
+struct exynos_eint_gpio_save {
+        u32 eint_con;
+        u32 eint_fltcon0;
+        u32 eint_fltcon1;
+};
+
 /*
  * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
  * @d: driver data of samsung pinctrl driver.
@@ -204,8 +210,8 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
 {
         struct samsung_pin_bank *bank;
         struct device *dev = d->dev;
-        unsigned int ret;
-        unsigned int i;
+        int ret;
+        int i;
 
         if (!d->irq) {
                 dev_err(dev, "irq number not available\n");
@@ -227,11 +233,29 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
                                 bank->nr_pins, &exynos_gpio_irqd_ops, bank);
                 if (!bank->irq_domain) {
                         dev_err(dev, "gpio irq domain add failed\n");
-                        return -ENXIO;
+                        ret = -ENXIO;
+                        goto err_domains;
+                }
+
+                bank->soc_priv = devm_kzalloc(d->dev,
+                        sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
+                if (!bank->soc_priv) {
+                        irq_domain_remove(bank->irq_domain);
+                        ret = -ENOMEM;
+                        goto err_domains;
                 }
         }
 
         return 0;
+
+err_domains:
+        for (--i, --bank; i >= 0; --i, --bank) {
+                if (bank->eint_type != EINT_TYPE_GPIO)
+                        continue;
+                irq_domain_remove(bank->irq_domain);
+        }
+
+        return ret;
 }
 
 static void exynos_wkup_irq_unmask(struct irq_data *irqd)
@@ -326,6 +350,28 @@ static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
         return 0;
 }
 
+static u32 exynos_eint_wake_mask = 0xffffffff;
+
+u32 exynos_get_eint_wake_mask(void)
+{
+        return exynos_eint_wake_mask;
+}
+
+static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
+{
+        struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
+        unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
+
+        pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq);
+
+        if (!on)
+                exynos_eint_wake_mask |= bit;
+        else
+                exynos_eint_wake_mask &= ~bit;
+
+        return 0;
+}
+
 /*
  * irq_chip for wakeup interrupts
  */
@@ -335,6 +381,7 @@ static struct irq_chip exynos_wkup_irq_chip = {
         .irq_mask       = exynos_wkup_irq_mask,
         .irq_ack        = exynos_wkup_irq_ack,
         .irq_set_type   = exynos_wkup_irq_set_type,
+        .irq_set_wake   = exynos_wkup_irq_set_wake,
 };
 
 /* interrupt handler for wakeup interrupts 0..15 */
@@ -505,6 +552,72 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
         return 0;
 }
 
+static void exynos_pinctrl_suspend_bank(
+                                struct samsung_pinctrl_drv_data *drvdata,
+                                struct samsung_pin_bank *bank)
+{
+        struct exynos_eint_gpio_save *save = bank->soc_priv;
+        void __iomem *regs = drvdata->virt_base;
+
+        save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
+                                                + bank->eint_offset);
+        save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+                                                + 2 * bank->eint_offset);
+        save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+                                                + 2 * bank->eint_offset + 4);
+
+        pr_debug("%s: save     con %#010x\n", bank->name, save->eint_con);
+        pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
+        pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
+}
+
+static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
+{
+        struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
+        struct samsung_pin_bank *bank = ctrl->pin_banks;
+        int i;
+
+        for (i = 0; i < ctrl->nr_banks; ++i, ++bank)
+                if (bank->eint_type == EINT_TYPE_GPIO)
+                        exynos_pinctrl_suspend_bank(drvdata, bank);
+}
+
+static void exynos_pinctrl_resume_bank(
+                                struct samsung_pinctrl_drv_data *drvdata,
+                                struct samsung_pin_bank *bank)
+{
+        struct exynos_eint_gpio_save *save = bank->soc_priv;
+        void __iomem *regs = drvdata->virt_base;
+
+        pr_debug("%s:     con %#010x => %#010x\n", bank->name,
+                        readl(regs + EXYNOS_GPIO_ECON_OFFSET
+                        + bank->eint_offset), save->eint_con);
+        pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
+                        readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+                        + 2 * bank->eint_offset), save->eint_fltcon0);
+        pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
+                        readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+                        + 2 * bank->eint_offset + 4), save->eint_fltcon1);
+
+        writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
+                                                + bank->eint_offset);
+        writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
+                                                + 2 * bank->eint_offset);
+        writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
+                                                + 2 * bank->eint_offset + 4);
+}
+
+static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
+{
+        struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
+        struct samsung_pin_bank *bank = ctrl->pin_banks;
+        int i;
+
+        for (i = 0; i < ctrl->nr_banks; ++i, ++bank)
+                if (bank->eint_type == EINT_TYPE_GPIO)
+                        exynos_pinctrl_resume_bank(drvdata, bank);
+}
+
 /* pin banks of exynos4210 pin-controller 0 */
 static struct samsung_pin_bank exynos4210_pin_banks0[] = {
         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
@@ -568,6 +681,8 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
                 .svc            = EXYNOS_SVC_OFFSET,
                 .eint_gpio_init = exynos_eint_gpio_init,
+                .suspend        = exynos_pinctrl_suspend,
+                .resume         = exynos_pinctrl_resume,
                 .label          = "exynos4210-gpio-ctrl0",
         }, {
                 /* pin-controller instance 1 data */
@@ -582,6 +697,8 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
                 .svc            = EXYNOS_SVC_OFFSET,
                 .eint_gpio_init = exynos_eint_gpio_init,
                 .eint_wkup_init = exynos_eint_wkup_init,
+                .suspend        = exynos_pinctrl_suspend,
+                .resume         = exynos_pinctrl_resume,
                 .label          = "exynos4210-gpio-ctrl1",
         }, {
                 /* pin-controller instance 2 data */
@@ -663,6 +780,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
                 .svc            = EXYNOS_SVC_OFFSET,
                 .eint_gpio_init = exynos_eint_gpio_init,
+                .suspend        = exynos_pinctrl_suspend,
+                .resume         = exynos_pinctrl_resume,
                 .label          = "exynos4x12-gpio-ctrl0",
         }, {
                 /* pin-controller instance 1 data */
@@ -677,6 +796,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
                 .svc            = EXYNOS_SVC_OFFSET,
                 .eint_gpio_init = exynos_eint_gpio_init,
                 .eint_wkup_init = exynos_eint_wkup_init,
+                .suspend        = exynos_pinctrl_suspend,
+                .resume         = exynos_pinctrl_resume,
                 .label          = "exynos4x12-gpio-ctrl1",
         }, {
                 /* pin-controller instance 2 data */
@@ -687,6 +808,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
                 .svc            = EXYNOS_SVC_OFFSET,
                 .eint_gpio_init = exynos_eint_gpio_init,
+                .suspend        = exynos_pinctrl_suspend,
+                .resume         = exynos_pinctrl_resume,
                 .label          = "exynos4x12-gpio-ctrl2",
         }, {
                 /* pin-controller instance 3 data */
@@ -697,6 +820,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
                 .svc            = EXYNOS_SVC_OFFSET,
                 .eint_gpio_init = exynos_eint_gpio_init,
+                .suspend        = exynos_pinctrl_suspend,
+                .resume         = exynos_pinctrl_resume,
                 .label          = "exynos4x12-gpio-ctrl3",
         },
 };
@@ -775,6 +900,8 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
                 .svc            = EXYNOS_SVC_OFFSET,
                 .eint_gpio_init = exynos_eint_gpio_init,
                 .eint_wkup_init = exynos_eint_wkup_init,
+                .suspend        = exynos_pinctrl_suspend,
+                .resume         = exynos_pinctrl_resume,
                 .label          = "exynos5250-gpio-ctrl0",
         }, {
                 /* pin-controller instance 1 data */
@@ -785,6 +912,8 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
                 .svc            = EXYNOS_SVC_OFFSET,
                 .eint_gpio_init = exynos_eint_gpio_init,
+                .suspend        = exynos_pinctrl_suspend,
+                .resume         = exynos_pinctrl_resume,
                 .label          = "exynos5250-gpio-ctrl1",
         }, {
                 /* pin-controller instance 2 data */
@@ -795,6 +924,8 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
                 .svc            = EXYNOS_SVC_OFFSET,
                 .eint_gpio_init = exynos_eint_gpio_init,
+                .suspend        = exynos_pinctrl_suspend,
+                .resume         = exynos_pinctrl_resume,
                 .label          = "exynos5250-gpio-ctrl2",
         }, {
                 /* pin-controller instance 3 data */
@@ -805,6 +936,8 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
                 .svc            = EXYNOS_SVC_OFFSET,
                 .eint_gpio_init = exynos_eint_gpio_init,
+                .suspend        = exynos_pinctrl_suspend,
+                .resume         = exynos_pinctrl_resume,
                 .label          = "exynos5250-gpio-ctrl3",
         },
 };
diff --git a/drivers/pinctrl/pinctrl-exynos.h b/drivers/pinctrl/pinctrl-exynos.h
index 9b1f77a5bf0f..3c91c357792f 100644
--- a/drivers/pinctrl/pinctrl-exynos.h
+++ b/drivers/pinctrl/pinctrl-exynos.h
@@ -19,6 +19,7 @@
 
 /* External GPIO and wakeup interrupt related definitions */
 #define EXYNOS_GPIO_ECON_OFFSET         0x700
+#define EXYNOS_GPIO_EFLTCON_OFFSET      0x800
 #define EXYNOS_GPIO_EMASK_OFFSET        0x900
 #define EXYNOS_GPIO_EPEND_OFFSET        0xA00
 #define EXYNOS_WKUP_ECON_OFFSET         0xE00
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index 055d0162098b..63ac22e89678 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -28,6 +28,7 @@
 #include <linux/gpio.h>
 #include <linux/irqdomain.h>
 #include <linux/spinlock.h>
+#include <linux/syscore_ops.h>
 
 #include "core.h"
 #include "pinctrl-samsung.h"
@@ -48,6 +49,9 @@ static struct pin_config {
         { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
 };
 
+/* Global list of devices (struct samsung_pinctrl_drv_data) */
+LIST_HEAD(drvdata_list);
+
 static unsigned int pin_base;
 
 static inline struct samsung_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
@@ -956,9 +960,151 @@ static int samsung_pinctrl_probe(struct platform_device *pdev)
                 ctrl->eint_wkup_init(drvdata);
 
         platform_set_drvdata(pdev, drvdata);
+
+        /* Add to the global list */
+        list_add_tail(&drvdata->node, &drvdata_list);
+
         return 0;
 }
 
+#ifdef CONFIG_PM
+
+/**
+ * samsung_pinctrl_suspend_dev - save pinctrl state for suspend for a device
+ *
+ * Save data for all banks handled by this device.
+ */
+static void samsung_pinctrl_suspend_dev(
+        struct samsung_pinctrl_drv_data *drvdata)
+{
+        struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
+        void __iomem *virt_base = drvdata->virt_base;
+        int i;
+
+        for (i = 0; i < ctrl->nr_banks; i++) {
+                struct samsung_pin_bank *bank = &ctrl->pin_banks[i];
+                void __iomem *reg = virt_base + bank->pctl_offset;
+
+                u8 *offs = bank->type->reg_offset;
+                u8 *widths = bank->type->fld_width;
+                enum pincfg_type type;
+
+                /* Registers without a powerdown config aren't lost */
+                if (!widths[PINCFG_TYPE_CON_PDN])
+                        continue;
+
+                for (type = 0; type < PINCFG_TYPE_NUM; type++)
+                        if (widths[type])
+                                bank->pm_save[type] = readl(reg + offs[type]);
+
+                if (widths[PINCFG_TYPE_FUNC] * bank->nr_pins > 32) {
+                        /* Some banks have two config registers */
+                        bank->pm_save[PINCFG_TYPE_NUM] =
+                                readl(reg + offs[PINCFG_TYPE_FUNC] + 4);
+                        pr_debug("Save %s @ %p (con %#010x %08x)\n",
+                                 bank->name, reg,
+                                 bank->pm_save[PINCFG_TYPE_FUNC],
+                                 bank->pm_save[PINCFG_TYPE_NUM]);
+                } else {
+                        pr_debug("Save %s @ %p (con %#010x)\n", bank->name,
+                                 reg, bank->pm_save[PINCFG_TYPE_FUNC]);
+                }
+        }
+
+        if (ctrl->suspend)
+                ctrl->suspend(drvdata);
+}
+
+/**
+ * samsung_pinctrl_resume_dev - restore pinctrl state from suspend for a device
+ *
+ * Restore one of the banks that was saved during suspend.
+ *
+ * We don't bother doing anything complicated to avoid glitching lines since
+ * we're called before pad retention is turned off.
+ */
+static void samsung_pinctrl_resume_dev(struct samsung_pinctrl_drv_data *drvdata)
+{
+        struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
+        void __iomem *virt_base = drvdata->virt_base;
+        int i;
+
+        if (ctrl->resume)
+                ctrl->resume(drvdata);
+
+        for (i = 0; i < ctrl->nr_banks; i++) {
+                struct samsung_pin_bank *bank = &ctrl->pin_banks[i];
+                void __iomem *reg = virt_base + bank->pctl_offset;
+
+                u8 *offs = bank->type->reg_offset;
+                u8 *widths = bank->type->fld_width;
+                enum pincfg_type type;
+
+                /* Registers without a powerdown config aren't lost */
+                if (!widths[PINCFG_TYPE_CON_PDN])
+                        continue;
+
+                if (widths[PINCFG_TYPE_FUNC] * bank->nr_pins > 32) {
+                        /* Some banks have two config registers */
+                        pr_debug("%s @ %p (con %#010x %08x => %#010x %08x)\n",
+                                 bank->name, reg,
+                                 readl(reg + offs[PINCFG_TYPE_FUNC]),
+                                 readl(reg + offs[PINCFG_TYPE_FUNC] + 4),
+                                 bank->pm_save[PINCFG_TYPE_FUNC],
+                                 bank->pm_save[PINCFG_TYPE_NUM]);
+                        writel(bank->pm_save[PINCFG_TYPE_NUM],
+                               reg + offs[PINCFG_TYPE_FUNC] + 4);
+                } else {
+                        pr_debug("%s @ %p (con %#010x => %#010x)\n", bank->name,
+                                 reg, readl(reg + offs[PINCFG_TYPE_FUNC]),
+                                 bank->pm_save[PINCFG_TYPE_FUNC]);
+                }
+                for (type = 0; type < PINCFG_TYPE_NUM; type++)
+                        if (widths[type])
+                                writel(bank->pm_save[type], reg + offs[type]);
+        }
+}
+
+/**
+ * samsung_pinctrl_suspend - save pinctrl state for suspend
+ *
+ * Save data for all banks across all devices.
+ */
+static int samsung_pinctrl_suspend(void)
+{
+        struct samsung_pinctrl_drv_data *drvdata;
+
+        list_for_each_entry(drvdata, &drvdata_list, node) {
+                samsung_pinctrl_suspend_dev(drvdata);
+        }
+
+        return 0;
+}
+
+/**
+ * samsung_pinctrl_resume - restore pinctrl state for suspend
+ *
+ * Restore data for all banks across all devices.
+ */
+static void samsung_pinctrl_resume(void)
+{
+        struct samsung_pinctrl_drv_data *drvdata;
+
+        list_for_each_entry_reverse(drvdata, &drvdata_list, node) {
+                samsung_pinctrl_resume_dev(drvdata);
+        }
+}
+
+#else
+#define samsung_pinctrl_suspend         NULL
+#define samsung_pinctrl_resume          NULL
+#endif
+
+static struct syscore_ops samsung_pinctrl_syscore_ops = {
+        .suspend        = samsung_pinctrl_suspend,
+        .resume         = samsung_pinctrl_resume,
+};
+
 static const struct of_device_id samsung_pinctrl_dt_match[] = {
 #ifdef CONFIG_PINCTRL_EXYNOS
         { .compatible = "samsung,exynos4210-pinctrl",
@@ -987,6 +1133,14 @@ static struct platform_driver samsung_pinctrl_driver = {
 
 static int __init samsung_pinctrl_drv_register(void)
 {
+        /*
+         * Register syscore ops for save/restore of registers across suspend.
+         * It's important to ensure that this driver is running at an earlier
+         * initcall level than any arch-specific init calls that install syscore
+         * ops that turn off pad retention (like exynos_pm_resume).
+         */
+        register_syscore_ops(&samsung_pinctrl_syscore_ops);
+
         return platform_driver_register(&samsung_pinctrl_driver);
 }
 postcore_initcall(samsung_pinctrl_drv_register);
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index 7c7f9ebcd05b..26d3519240c9 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -127,6 +127,7 @@ struct samsung_pin_bank_type {
  * @gpio_chip: GPIO chip of the bank.
  * @grange: linux gpio pin range supported by this bank.
  * @slock: spinlock protecting bank registers
+ * @pm_save: saved register values during suspend
  */
 struct samsung_pin_bank {
         struct samsung_pin_bank_type *type;
@@ -138,12 +139,15 @@ struct samsung_pin_bank {
         u32             eint_mask;
         u32             eint_offset;
         char            *name;
+        void            *soc_priv;
         struct device_node *of_node;
         struct samsung_pinctrl_drv_data *drvdata;
         struct irq_domain *irq_domain;
         struct gpio_chip gpio_chip;
         struct pinctrl_gpio_range grange;
         spinlock_t slock;
+
+        u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
 };
 
 /**
@@ -184,11 +188,15 @@ struct samsung_pin_ctrl {
 
         int             (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
         int             (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
+        void            (*suspend)(struct samsung_pinctrl_drv_data *);
+        void            (*resume)(struct samsung_pinctrl_drv_data *);
+
         char            *label;
 };
 
 /**
  * struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
+ * @node: global list node
  * @virt_base: register base address of the controller.
  * @dev: device instance representing the controller.
  * @irq: interrpt number used by the controller to notify gpio interrupts.
@@ -201,6 +209,7 @@ struct samsung_pin_ctrl {
  * @nr_function: number of such pin functions.
  */
 struct samsung_pinctrl_drv_data {
+        struct list_head                node;
         void __iomem                    *virt_base;
         struct device                   *dev;
         int                             irq;
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index c52fc2c08732..b7d8c890514c 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -1990,8 +1990,10 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
         }
 
         clk = devm_clk_get(&pdev->dev, NULL);
-        if (IS_ERR(clk))
+        if (IS_ERR(clk)) {
+                ret = PTR_ERR(clk);
                 goto gpiochip_error;
+        }
 
         clk_prepare_enable(clk);
 
@@ -2000,7 +2002,8 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
         return 0;
 
 gpiochip_error:
-        ret = gpiochip_remove(pctl->chip);
+        if (gpiochip_remove(pctl->chip))
+                dev_err(&pdev->dev, "failed to remove gpio chip\n");
 pinctrl_error:
         pinctrl_unregister(pctl->pctl_dev);
         return ret;
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index 6a3a7503e6a0..06bfa09bb15c 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -1105,10 +1105,17 @@ static int u300_pmx_remove(struct platform_device *pdev)
         return 0;
 }
 
+static const struct of_device_id u300_pinctrl_match[] = {
+        { .compatible = "stericsson,pinctrl-u300" },
+        {},
+};
+
+
 static struct platform_driver u300_pmx_driver = {
         .driver = {
                 .name = DRIVER_NAME,
                 .owner = THIS_MODULE,
+                .of_match_table = u300_pinctrl_match,
         },
         .probe = u300_pmx_probe,
         .remove = u300_pmx_remove,
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index f8a2ae413c7f..636a882b406e 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -5,8 +5,6 @@
 if ARCH_SHMOBILE || SUPERH
 
 config PINCTRL_SH_PFC
-        # XXX move off the gpio dependency
-        depends on GPIOLIB
         select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB
         select PINMUX
         select PINCONF
@@ -32,11 +30,21 @@ config PINCTRL_PFC_R8A7740
         depends on ARCH_R8A7740
         select PINCTRL_SH_PFC
 
+config PINCTRL_PFC_R8A7778
+        def_bool y
+        depends on ARCH_R8A7778
+        select PINCTRL_SH_PFC
+
 config PINCTRL_PFC_R8A7779
         def_bool y
         depends on ARCH_R8A7779
         select PINCTRL_SH_PFC
 
+config PINCTRL_PFC_R8A7790
+        def_bool y
+        depends on ARCH_R8A7790
+        select PINCTRL_SH_PFC
+
 config PINCTRL_PFC_SH7203
         def_bool y
         depends on CPU_SUBTYPE_SH7203
@@ -64,6 +72,7 @@ config PINCTRL_PFC_SH73A0
         def_bool y
         depends on ARCH_SH73A0
         select PINCTRL_SH_PFC
+        select REGULATOR
 
 config PINCTRL_PFC_SH7720
         def_bool y
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 211cd8e98a8a..5e0c222c12d7 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -5,7 +5,9 @@ endif
 obj-$(CONFIG_PINCTRL_SH_PFC)    += sh-pfc.o
 obj-$(CONFIG_PINCTRL_PFC_R8A73A4)       += pfc-r8a73a4.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7740)       += pfc-r8a7740.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7778)       += pfc-r8a7778.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7779)       += pfc-r8a7779.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7790)       += pfc-r8a7790.o
 obj-$(CONFIG_PINCTRL_PFC_SH7203)        += pfc-sh7203.o
 obj-$(CONFIG_PINCTRL_PFC_SH7264)        += pfc-sh7264.o
 obj-$(CONFIG_PINCTRL_PFC_SH7269)        += pfc-sh7269.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index b551336924a5..3b2fd43ff294 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -372,6 +372,12 @@ static int sh_pfc_probe(struct platform_device *pdev)
 
         spin_lock_init(&pfc->lock);
 
+        if (info->ops && info->ops->init) {
+                ret = info->ops->init(pfc);
+                if (ret < 0)
+                        return ret;
+        }
+
         pinctrl_provide_dummies();
 
         /*
@@ -379,7 +385,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
          */
         ret = sh_pfc_register_pinctrl(pfc);
         if (unlikely(ret != 0))
-                return ret;
+                goto error;
 
 #ifdef CONFIG_GPIO_SH_PFC
         /*
@@ -401,6 +407,11 @@ static int sh_pfc_probe(struct platform_device *pdev)
         dev_info(pfc->dev, "%s support registered\n", info->name);
 
         return 0;
+
+error:
+        if (info->ops && info->ops->exit)
+                info->ops->exit(pfc);
+        return ret;
 }
 
 static int sh_pfc_remove(struct platform_device *pdev)
@@ -412,6 +423,9 @@ static int sh_pfc_remove(struct platform_device *pdev)
 #endif
         sh_pfc_unregister_pinctrl(pfc);
 
+        if (pfc->info->ops && pfc->info->ops->exit)
+                pfc->info->ops->exit(pfc);
+
         platform_set_drvdata(pdev, NULL);
 
         return 0;
@@ -424,9 +438,15 @@ static const struct platform_device_id sh_pfc_id_table[] = {
 #ifdef CONFIG_PINCTRL_PFC_R8A7740
         { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
 #endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7778
+        { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
+#endif
 #ifdef CONFIG_PINCTRL_PFC_R8A7779
         { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
 #endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
+        { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
+#endif
 #ifdef CONFIG_PINCTRL_PFC_SH7203
         { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
 #endif
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 89cb4289d761..f02ba1dde3a0 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -11,6 +11,7 @@
 #define __SH_PFC_CORE_H__
 
 #include <linux/compiler.h>
+#include <linux/spinlock.h>
 #include <linux/types.h>
 
 #include "sh_pfc.h"
@@ -27,6 +28,7 @@ struct sh_pfc_pinctrl;
 struct sh_pfc {
         struct device *dev;
         const struct sh_pfc_soc_info *info;
+        void *soc_data;
         spinlock_t lock;
 
         unsigned int num_windows;
@@ -56,7 +58,9 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
 
 extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
 extern const struct sh_pfc_soc_info sh7203_pinmux_info;
 extern const struct sh_pfc_soc_info sh7264_pinmux_info;
 extern const struct sh_pfc_soc_info sh7269_pinmux_info;
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index bbd87d29bfd0..f6ea47c433b3 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -18,10 +18,14 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
+#include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/pinctrl/pinconf-generic.h>
+
 #include <mach/r8a7740.h>
 #include <mach/irqs.h>
 
+#include "core.h"
 #include "sh_pfc.h"
 
 #define CPU_ALL_PORT(fn, pfx, sfx)                                      \
@@ -30,6 +34,29 @@
         PORT_10(fn, pfx##20, sfx),                                      \
         PORT_1(fn, pfx##210, sfx),      PORT_1(fn, pfx##211, sfx)
 
+#undef _GPIO_PORT
+#define _GPIO_PORT(gpio, sfx)                                           \
+        [gpio] = {                                                      \
+                .name = __stringify(PORT##gpio),                        \
+                .enum_id = PORT##gpio##_DATA,                           \
+        }
+
+#define IRQC_PIN_MUX(irq, pin)                                          \
+static const unsigned int intc_irq##irq##_pins[] = {                    \
+        pin,                                                            \
+};                                                                      \
+static const unsigned int intc_irq##irq##_mux[] = {                     \
+        IRQ##irq##_MARK,                                                \
+}
+
+#define IRQC_PINS_MUX(irq, idx, pin)                                    \
+static const unsigned int intc_irq##irq##_##idx##_pins[] = {            \
+        pin,                                                            \
+};                                                                      \
+static const unsigned int intc_irq##irq##_##idx##_mux[] = {             \
+        IRQ##irq##_PORT##pin##_MARK,                                    \
+}
+
 enum {
         PINMUX_RESERVED = 0,
 
@@ -43,16 +70,6 @@ enum {
         PORT_ALL(IN),
         PINMUX_INPUT_END,
 
-        /* PORT0_IN_PU -> PORT211_IN_PU */
-        PINMUX_INPUT_PULLUP_BEGIN,
-        PORT_ALL(IN_PU),
-        PINMUX_INPUT_PULLUP_END,
-
-        /* PORT0_IN_PD -> PORT211_IN_PD */
-        PINMUX_INPUT_PULLDOWN_BEGIN,
-        PORT_ALL(IN_PD),
-        PINMUX_INPUT_PULLDOWN_END,
-
         /* PORT0_OUT -> PORT211_OUT */
         PINMUX_OUTPUT_BEGIN,
         PORT_ALL(OUT),
@@ -261,8 +278,6 @@ enum {
         SCIFB_CTS_PORT173_MARK,
 
         /* LCD0 */
-        LCDC0_SELECT_MARK,
-
         LCD0_D0_MARK,   LCD0_D1_MARK,   LCD0_D2_MARK,   LCD0_D3_MARK,
         LCD0_D4_MARK,   LCD0_D5_MARK,   LCD0_D6_MARK,   LCD0_D7_MARK,
         LCD0_D8_MARK,   LCD0_D9_MARK,   LCD0_D10_MARK,  LCD0_D11_MARK,
@@ -285,8 +300,6 @@ enum {
         LCD0_LCLK_PORT102_MARK,
 
         /* LCD1 */
-        LCDC1_SELECT_MARK,
-
         LCD1_D0_MARK,   LCD1_D1_MARK,   LCD1_D2_MARK,   LCD1_D3_MARK,
         LCD1_D4_MARK,   LCD1_D5_MARK,   LCD1_D6_MARK,   LCD1_D7_MARK,
         LCD1_D8_MARK,   LCD1_D9_MARK,   LCD1_D10_MARK,  LCD1_D11_MARK,
@@ -577,137 +590,11 @@ enum {
         PINMUX_MARK_END,
 };
 
+#define _PORT_DATA(pfx, sfx)    PORT_DATA_IO(pfx)
+#define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_PORT_DATA, , unused)
+
 static const pinmux_enum_t pinmux_data[] = {
-        /* specify valid pin states for each pin in GPIO mode */
-
-        /* I/O and Pull U/D */
-        PORT_DATA_IO_PD(0),             PORT_DATA_IO_PD(1),
-        PORT_DATA_IO_PD(2),             PORT_DATA_IO_PD(3),
-        PORT_DATA_IO_PD(4),             PORT_DATA_IO_PD(5),
-        PORT_DATA_IO_PD(6),             PORT_DATA_IO(7),
-        PORT_DATA_IO(8),                PORT_DATA_IO(9),
-
-        PORT_DATA_IO_PD(10),            PORT_DATA_IO_PD(11),
-        PORT_DATA_IO_PD(12),            PORT_DATA_IO_PU_PD(13),
-        PORT_DATA_IO_PD(14),            PORT_DATA_IO_PD(15),
-        PORT_DATA_IO_PD(16),            PORT_DATA_IO_PD(17),
-        PORT_DATA_IO(18),               PORT_DATA_IO_PU(19),
-
-        PORT_DATA_IO_PU_PD(20),         PORT_DATA_IO_PD(21),
-        PORT_DATA_IO_PU_PD(22),         PORT_DATA_IO(23),
-        PORT_DATA_IO_PU(24),            PORT_DATA_IO_PU(25),
-        PORT_DATA_IO_PU(26),            PORT_DATA_IO_PU(27),
-        PORT_DATA_IO_PU(28),            PORT_DATA_IO_PU(29),
-
-        PORT_DATA_IO_PU(30),            PORT_DATA_IO_PD(31),
-        PORT_DATA_IO_PD(32),            PORT_DATA_IO_PD(33),
-        PORT_DATA_IO_PD(34),            PORT_DATA_IO_PU(35),
-        PORT_DATA_IO_PU(36),            PORT_DATA_IO_PD(37),
-        PORT_DATA_IO_PU(38),            PORT_DATA_IO_PD(39),
-
-        PORT_DATA_IO_PU_PD(40),         PORT_DATA_IO_PD(41),
-        PORT_DATA_IO_PD(42),            PORT_DATA_IO_PU_PD(43),
-        PORT_DATA_IO_PU_PD(44),         PORT_DATA_IO_PU_PD(45),
-        PORT_DATA_IO_PU_PD(46),         PORT_DATA_IO_PU_PD(47),
-        PORT_DATA_IO_PU_PD(48),         PORT_DATA_IO_PU_PD(49),
-
-        PORT_DATA_IO_PU_PD(50),         PORT_DATA_IO_PD(51),
-        PORT_DATA_IO_PD(52),            PORT_DATA_IO_PD(53),
-        PORT_DATA_IO_PD(54),            PORT_DATA_IO_PU_PD(55),
-        PORT_DATA_IO_PU_PD(56),         PORT_DATA_IO_PU_PD(57),
-        PORT_DATA_IO_PU_PD(58),         PORT_DATA_IO_PU_PD(59),
-
-        PORT_DATA_IO_PU_PD(60),         PORT_DATA_IO_PD(61),
-        PORT_DATA_IO_PD(62),            PORT_DATA_IO_PD(63),
-        PORT_DATA_IO_PD(64),            PORT_DATA_IO_PD(65),
-        PORT_DATA_IO_PU_PD(66),         PORT_DATA_IO_PU_PD(67),
-        PORT_DATA_IO_PU_PD(68),         PORT_DATA_IO_PU_PD(69),
-
-        PORT_DATA_IO_PU_PD(70),         PORT_DATA_IO_PU_PD(71),
-        PORT_DATA_IO_PU_PD(72),         PORT_DATA_IO_PU_PD(73),
-        PORT_DATA_IO_PU_PD(74),         PORT_DATA_IO_PU_PD(75),
-        PORT_DATA_IO_PU_PD(76),         PORT_DATA_IO_PU_PD(77),
-        PORT_DATA_IO_PU_PD(78),         PORT_DATA_IO_PU_PD(79),
-
-        PORT_DATA_IO_PU_PD(80),         PORT_DATA_IO_PU_PD(81),
-        PORT_DATA_IO(82),               PORT_DATA_IO_PU_PD(83),
-        PORT_DATA_IO(84),               PORT_DATA_IO_PD(85),
-        PORT_DATA_IO_PD(86),            PORT_DATA_IO_PD(87),
-        PORT_DATA_IO_PD(88),            PORT_DATA_IO_PD(89),
-
-        PORT_DATA_IO_PD(90),            PORT_DATA_IO_PU_PD(91),
-        PORT_DATA_IO_PU_PD(92),         PORT_DATA_IO_PU_PD(93),
-        PORT_DATA_IO_PU_PD(94),         PORT_DATA_IO_PU_PD(95),
-        PORT_DATA_IO_PU_PD(96),         PORT_DATA_IO_PU_PD(97),
-        PORT_DATA_IO_PU_PD(98),         PORT_DATA_IO_PU_PD(99),
-
-        PORT_DATA_IO_PU_PD(100),        PORT_DATA_IO(101),
-        PORT_DATA_IO_PU(102),           PORT_DATA_IO_PU_PD(103),
-        PORT_DATA_IO_PU(104),           PORT_DATA_IO_PU(105),
-        PORT_DATA_IO_PU_PD(106),        PORT_DATA_IO(107),
-        PORT_DATA_IO(108),              PORT_DATA_IO(109),
-
-        PORT_DATA_IO(110),              PORT_DATA_IO(111),
-        PORT_DATA_IO(112),              PORT_DATA_IO(113),
-        PORT_DATA_IO_PU_PD(114),        PORT_DATA_IO(115),
-        PORT_DATA_IO_PD(116),           PORT_DATA_IO_PD(117),
-        PORT_DATA_IO_PD(118),           PORT_DATA_IO_PD(119),
-
-        PORT_DATA_IO_PD(120),           PORT_DATA_IO_PD(121),
-        PORT_DATA_IO_PD(122),           PORT_DATA_IO_PD(123),
-        PORT_DATA_IO_PD(124),           PORT_DATA_IO(125),
-        PORT_DATA_IO(126),              PORT_DATA_IO(127),
-        PORT_DATA_IO(128),              PORT_DATA_IO(129),
-
-        PORT_DATA_IO(130),              PORT_DATA_IO(131),
-        PORT_DATA_IO(132),              PORT_DATA_IO(133),
-        PORT_DATA_IO(134),              PORT_DATA_IO(135),
-        PORT_DATA_IO(136),              PORT_DATA_IO(137),
-        PORT_DATA_IO(138),              PORT_DATA_IO(139),
-
-        PORT_DATA_IO(140),              PORT_DATA_IO(141),
-        PORT_DATA_IO_PU(142),           PORT_DATA_IO_PU(143),
-        PORT_DATA_IO_PU(144),           PORT_DATA_IO_PU(145),
-        PORT_DATA_IO_PU(146),           PORT_DATA_IO_PU(147),
-        PORT_DATA_IO_PU(148),           PORT_DATA_IO_PU(149),
-
-        PORT_DATA_IO_PU(150),           PORT_DATA_IO_PU(151),
-        PORT_DATA_IO_PU(152),           PORT_DATA_IO_PU(153),
-        PORT_DATA_IO_PU(154),           PORT_DATA_IO_PU(155),
-        PORT_DATA_IO_PU(156),           PORT_DATA_IO_PU(157),
-        PORT_DATA_IO_PD(158),           PORT_DATA_IO_PD(159),
-
-        PORT_DATA_IO_PU_PD(160),        PORT_DATA_IO_PD(161),
-        PORT_DATA_IO_PD(162),           PORT_DATA_IO_PD(163),
-        PORT_DATA_IO_PD(164),           PORT_DATA_IO_PD(165),
-        PORT_DATA_IO_PU(166),           PORT_DATA_IO_PU(167),
-        PORT_DATA_IO_PU(168),           PORT_DATA_IO_PU(169),
-
-        PORT_DATA_IO_PU(170),           PORT_DATA_IO_PU(171),
-        PORT_DATA_IO_PD(172),           PORT_DATA_IO_PD(173),
-        PORT_DATA_IO_PD(174),           PORT_DATA_IO_PD(175),
-        PORT_DATA_IO_PU(176),           PORT_DATA_IO_PU_PD(177),
-        PORT_DATA_IO_PU(178),           PORT_DATA_IO_PD(179),
-
-        PORT_DATA_IO_PD(180),           PORT_DATA_IO_PU(181),
-        PORT_DATA_IO_PU(182),           PORT_DATA_IO(183),
-        PORT_DATA_IO_PD(184),           PORT_DATA_IO_PD(185),
-        PORT_DATA_IO_PD(186),           PORT_DATA_IO_PD(187),
-        PORT_DATA_IO_PD(188),           PORT_DATA_IO_PD(189),
-
-        PORT_DATA_IO_PD(190),           PORT_DATA_IO_PD(191),
-        PORT_DATA_IO_PD(192),           PORT_DATA_IO_PU_PD(193),
-        PORT_DATA_IO_PU_PD(194),        PORT_DATA_IO_PD(195),
-        PORT_DATA_IO_PU_PD(196),        PORT_DATA_IO_PD(197),
-        PORT_DATA_IO_PU_PD(198),        PORT_DATA_IO_PU_PD(199),
-
-        PORT_DATA_IO_PU_PD(200),        PORT_DATA_IO_PU(201),
-        PORT_DATA_IO_PU_PD(202),        PORT_DATA_IO(203),
-        PORT_DATA_IO_PU_PD(204),        PORT_DATA_IO_PU_PD(205),
-        PORT_DATA_IO_PU_PD(206),        PORT_DATA_IO_PU_PD(207),
-        PORT_DATA_IO_PU_PD(208),        PORT_DATA_IO_PD(209),
-
-        PORT_DATA_IO_PD(210),           PORT_DATA_IO_PD(211),
+        PINMUX_DATA_GP_ALL(),
 
         /* Port0 */
         PINMUX_DATA(DBGMDT2_MARK,               PORT0_FN1),
@@ -986,7 +873,7 @@ static const pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(IRQ27_PORT57_MARK,          PORT57_FN0,     MSEL1CR_27_1),
 
         /* Port58 */
-        PINMUX_DATA(LCD0_D0_MARK,               PORT58_FN1),
+        PINMUX_DATA(LCD0_D0_MARK,               PORT58_FN1,     MSEL3CR_6_0),
         PINMUX_DATA(KEYOUT7_MARK,               PORT58_FN3),
         PINMUX_DATA(KEYIN0_PORT58_MARK,         PORT58_FN4,     MSEL4CR_18_1),
         PINMUX_DATA(DV_D0_MARK,                 PORT58_FN6),
@@ -1633,10 +1520,6 @@ static const pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(IRQ16_PORT211_MARK,         PORT211_FN0,    MSEL1CR_16_1),
         PINMUX_DATA(HDMI_CEC_MARK,              PORT211_FN1),
 
-        /* LCDC select */
-        PINMUX_DATA(LCDC0_SELECT_MARK,                          MSEL3CR_6_0),
-        PINMUX_DATA(LCDC1_SELECT_MARK,                          MSEL3CR_6_1),
-
         /* SDENC */
         PINMUX_DATA(SDENC_CPG_MARK,                             MSEL4CR_19_0),
         PINMUX_DATA(SDENC_DV_CLKI_MARK,                         MSEL4CR_19_1),
@@ -1654,9 +1537,565 @@ static const pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK,                    MSEL5CR_30_1,   MSEL5CR_29_0),
 };
 
+#define R8A7740_PIN(pin, cfgs)                                          \
+        {                                                               \
+                .name = __stringify(PORT##pin),                         \
+                .enum_id = PORT##pin##_DATA,                            \
+                .configs = cfgs,                                        \
+        }
+
+#define __I             (SH_PFC_PIN_CFG_INPUT)
+#define __O             (SH_PFC_PIN_CFG_OUTPUT)
+#define __IO            (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
+#define __PD            (SH_PFC_PIN_CFG_PULL_DOWN)
+#define __PU            (SH_PFC_PIN_CFG_PULL_UP)
+#define __PUD           (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
+
+#define R8A7740_PIN_I_PD(pin)           R8A7740_PIN(pin, __I | __PD)
+#define R8A7740_PIN_I_PU(pin)           R8A7740_PIN(pin, __I | __PU)
+#define R8A7740_PIN_I_PU_PD(pin)                R8A7740_PIN(pin, __I | __PUD)
+#define R8A7740_PIN_IO(pin)             R8A7740_PIN(pin, __IO)
+#define R8A7740_PIN_IO_PD(pin)          R8A7740_PIN(pin, __IO | __PD)
+#define R8A7740_PIN_IO_PU(pin)          R8A7740_PIN(pin, __IO | __PU)
+#define R8A7740_PIN_IO_PU_PD(pin)       R8A7740_PIN(pin, __IO | __PUD)
+#define R8A7740_PIN_O(pin)              R8A7740_PIN(pin, __O)
+#define R8A7740_PIN_O_PU_PD(pin)                R8A7740_PIN(pin, __O | __PUD)
+
 static struct sh_pfc_pin pinmux_pins[] = {
-        GPIO_PORT_ALL(),
+        /* Table 56-1 (I/O and Pull U/D) */
+        R8A7740_PIN_IO_PD(0),           R8A7740_PIN_IO_PD(1),
+        R8A7740_PIN_IO_PD(2),           R8A7740_PIN_IO_PD(3),
+        R8A7740_PIN_IO_PD(4),           R8A7740_PIN_IO_PD(5),
+        R8A7740_PIN_IO_PD(6),           R8A7740_PIN_IO(7),
+        R8A7740_PIN_IO(8),              R8A7740_PIN_IO(9),
+        R8A7740_PIN_IO_PD(10),          R8A7740_PIN_IO_PD(11),
+        R8A7740_PIN_IO_PD(12),          R8A7740_PIN_IO_PU_PD(13),
+        R8A7740_PIN_IO_PD(14),          R8A7740_PIN_IO_PD(15),
+        R8A7740_PIN_IO_PD(16),          R8A7740_PIN_IO_PD(17),
+        R8A7740_PIN_IO(18),             R8A7740_PIN_IO_PU(19),
+        R8A7740_PIN_IO_PU_PD(20),       R8A7740_PIN_IO_PD(21),
+        R8A7740_PIN_IO_PU_PD(22),       R8A7740_PIN_IO(23),
+        R8A7740_PIN_IO_PU(24),          R8A7740_PIN_IO_PU(25),
+        R8A7740_PIN_IO_PU(26),          R8A7740_PIN_IO_PU(27),
+        R8A7740_PIN_IO_PU(28),          R8A7740_PIN_IO_PU(29),
+        R8A7740_PIN_IO_PU(30),          R8A7740_PIN_IO_PD(31),
+        R8A7740_PIN_IO_PD(32),          R8A7740_PIN_IO_PD(33),
+        R8A7740_PIN_IO_PD(34),          R8A7740_PIN_IO_PU(35),
+        R8A7740_PIN_IO_PU(36),          R8A7740_PIN_IO_PD(37),
+        R8A7740_PIN_IO_PU(38),          R8A7740_PIN_IO_PD(39),
+        R8A7740_PIN_IO_PU_PD(40),       R8A7740_PIN_IO_PD(41),
+        R8A7740_PIN_IO_PD(42),          R8A7740_PIN_IO_PU_PD(43),
+        R8A7740_PIN_IO_PU_PD(44),       R8A7740_PIN_IO_PU_PD(45),
+        R8A7740_PIN_IO_PU_PD(46),       R8A7740_PIN_IO_PU_PD(47),
+        R8A7740_PIN_IO_PU_PD(48),       R8A7740_PIN_IO_PU_PD(49),
+        R8A7740_PIN_IO_PU_PD(50),       R8A7740_PIN_IO_PD(51),
+        R8A7740_PIN_IO_PD(52),          R8A7740_PIN_IO_PD(53),
+        R8A7740_PIN_IO_PD(54),          R8A7740_PIN_IO_PU_PD(55),
+        R8A7740_PIN_IO_PU_PD(56),       R8A7740_PIN_IO_PU_PD(57),
+        R8A7740_PIN_IO_PU_PD(58),       R8A7740_PIN_IO_PU_PD(59),
+        R8A7740_PIN_IO_PU_PD(60),       R8A7740_PIN_IO_PD(61),
+        R8A7740_PIN_IO_PD(62),          R8A7740_PIN_IO_PD(63),
+        R8A7740_PIN_IO_PD(64),          R8A7740_PIN_IO_PD(65),
+        R8A7740_PIN_IO_PU_PD(66),       R8A7740_PIN_IO_PU_PD(67),
+        R8A7740_PIN_IO_PU_PD(68),       R8A7740_PIN_IO_PU_PD(69),
+        R8A7740_PIN_IO_PU_PD(70),       R8A7740_PIN_IO_PU_PD(71),
+        R8A7740_PIN_IO_PU_PD(72),       R8A7740_PIN_IO_PU_PD(73),
+        R8A7740_PIN_IO_PU_PD(74),       R8A7740_PIN_IO_PU_PD(75),
+        R8A7740_PIN_IO_PU_PD(76),       R8A7740_PIN_IO_PU_PD(77),
+        R8A7740_PIN_IO_PU_PD(78),       R8A7740_PIN_IO_PU_PD(79),
+        R8A7740_PIN_IO_PU_PD(80),       R8A7740_PIN_IO_PU_PD(81),
+        R8A7740_PIN_IO(82),             R8A7740_PIN_IO_PU_PD(83),
+        R8A7740_PIN_IO(84),             R8A7740_PIN_IO_PD(85),
+        R8A7740_PIN_IO_PD(86),          R8A7740_PIN_IO_PD(87),
+        R8A7740_PIN_IO_PD(88),          R8A7740_PIN_IO_PD(89),
+        R8A7740_PIN_IO_PD(90),          R8A7740_PIN_IO_PU_PD(91),
+        R8A7740_PIN_IO_PU_PD(92),       R8A7740_PIN_IO_PU_PD(93),
+        R8A7740_PIN_IO_PU_PD(94),       R8A7740_PIN_IO_PU_PD(95),
+        R8A7740_PIN_IO_PU_PD(96),       R8A7740_PIN_IO_PU_PD(97),
+        R8A7740_PIN_IO_PU_PD(98),       R8A7740_PIN_IO_PU_PD(99),
+        R8A7740_PIN_IO_PU_PD(100),      R8A7740_PIN_IO(101),
+        R8A7740_PIN_IO_PU(102),         R8A7740_PIN_IO_PU_PD(103),
+        R8A7740_PIN_IO_PU(104),         R8A7740_PIN_IO_PU(105),
+        R8A7740_PIN_IO_PU_PD(106),      R8A7740_PIN_IO(107),
+        R8A7740_PIN_IO(108),            R8A7740_PIN_IO(109),
+        R8A7740_PIN_IO(110),            R8A7740_PIN_IO(111),
+        R8A7740_PIN_IO(112),            R8A7740_PIN_IO(113),
+        R8A7740_PIN_IO_PU_PD(114),      R8A7740_PIN_IO(115),
+        R8A7740_PIN_IO_PD(116),         R8A7740_PIN_IO_PD(117),
+        R8A7740_PIN_IO_PD(118),         R8A7740_PIN_IO_PD(119),
+        R8A7740_PIN_IO_PD(120),         R8A7740_PIN_IO_PD(121),
+        R8A7740_PIN_IO_PD(122),         R8A7740_PIN_IO_PD(123),
+        R8A7740_PIN_IO_PD(124),         R8A7740_PIN_IO(125),
+        R8A7740_PIN_IO(126),            R8A7740_PIN_IO(127),
+        R8A7740_PIN_IO(128),            R8A7740_PIN_IO(129),
+        R8A7740_PIN_IO(130),            R8A7740_PIN_IO(131),
+        R8A7740_PIN_IO(132),            R8A7740_PIN_IO(133),
+        R8A7740_PIN_IO(134),            R8A7740_PIN_IO(135),
+        R8A7740_PIN_IO(136),            R8A7740_PIN_IO(137),
+        R8A7740_PIN_IO(138),            R8A7740_PIN_IO(139),
+        R8A7740_PIN_IO(140),            R8A7740_PIN_IO(141),
+        R8A7740_PIN_IO_PU(142),         R8A7740_PIN_IO_PU(143),
+        R8A7740_PIN_IO_PU(144),         R8A7740_PIN_IO_PU(145),
+        R8A7740_PIN_IO_PU(146),         R8A7740_PIN_IO_PU(147),
+        R8A7740_PIN_IO_PU(148),         R8A7740_PIN_IO_PU(149),
+        R8A7740_PIN_IO_PU(150),         R8A7740_PIN_IO_PU(151),
+        R8A7740_PIN_IO_PU(152),         R8A7740_PIN_IO_PU(153),
+        R8A7740_PIN_IO_PU(154),         R8A7740_PIN_IO_PU(155),
+        R8A7740_PIN_IO_PU(156),         R8A7740_PIN_IO_PU(157),
+        R8A7740_PIN_IO_PD(158),         R8A7740_PIN_IO_PD(159),
+        R8A7740_PIN_IO_PU_PD(160),      R8A7740_PIN_IO_PD(161),
+        R8A7740_PIN_IO_PD(162),         R8A7740_PIN_IO_PD(163),
+        R8A7740_PIN_IO_PD(164),         R8A7740_PIN_IO_PD(165),
+        R8A7740_PIN_IO_PU(166),         R8A7740_PIN_IO_PU(167),
+        R8A7740_PIN_IO_PU(168),         R8A7740_PIN_IO_PU(169),
+        R8A7740_PIN_IO_PU(170),         R8A7740_PIN_IO_PU(171),
+        R8A7740_PIN_IO_PD(172),         R8A7740_PIN_IO_PD(173),
+        R8A7740_PIN_IO_PD(174),         R8A7740_PIN_IO_PD(175),
+        R8A7740_PIN_IO_PU(176),         R8A7740_PIN_IO_PU_PD(177),
+        R8A7740_PIN_IO_PU(178),         R8A7740_PIN_IO_PD(179),
+        R8A7740_PIN_IO_PD(180),         R8A7740_PIN_IO_PU(181),
+        R8A7740_PIN_IO_PU(182),         R8A7740_PIN_IO(183),
+        R8A7740_PIN_IO_PD(184),         R8A7740_PIN_IO_PD(185),
+        R8A7740_PIN_IO_PD(186),         R8A7740_PIN_IO_PD(187),
+        R8A7740_PIN_IO_PD(188),         R8A7740_PIN_IO_PD(189),
+        R8A7740_PIN_IO_PD(190),         R8A7740_PIN_IO_PD(191),
+        R8A7740_PIN_IO_PD(192),         R8A7740_PIN_IO_PU_PD(193),
+        R8A7740_PIN_IO_PU_PD(194),      R8A7740_PIN_IO_PD(195),
+        R8A7740_PIN_IO_PU_PD(196),      R8A7740_PIN_IO_PD(197),
+        R8A7740_PIN_IO_PU_PD(198),      R8A7740_PIN_IO_PU_PD(199),
+        R8A7740_PIN_IO_PU_PD(200),      R8A7740_PIN_IO_PU(201),
+        R8A7740_PIN_IO_PU_PD(202),      R8A7740_PIN_IO(203),
+        R8A7740_PIN_IO_PU_PD(204),      R8A7740_PIN_IO_PU_PD(205),
+        R8A7740_PIN_IO_PU_PD(206),      R8A7740_PIN_IO_PU_PD(207),
+        R8A7740_PIN_IO_PU_PD(208),      R8A7740_PIN_IO_PD(209),
+        R8A7740_PIN_IO_PD(210),         R8A7740_PIN_IO_PD(211),
+};
+
+/* - BSC -------------------------------------------------------------------- */
+static const unsigned int bsc_data8_pins[] = {
+        /* D[0:7] */
+        157, 156, 155, 154, 153, 152, 151, 150,
+};
+static const unsigned int bsc_data8_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+};
+static const unsigned int bsc_data16_pins[] = {
+        /* D[0:15] */
+        157, 156, 155, 154, 153, 152, 151, 150,
+        149, 148, 147, 146, 145, 144, 143, 142,
+};
+static const unsigned int bsc_data16_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+        D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+};
+static const unsigned int bsc_data32_pins[] = {
+        /* D[0:31] */
+        157, 156, 155, 154, 153, 152, 151, 150,
+        149, 148, 147, 146, 145, 144, 143, 142,
+        171, 170, 169, 168, 167, 166, 173, 172,
+        165, 164, 163, 162, 161, 160, 159, 158,
+};
+static const unsigned int bsc_data32_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+        D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+        D16_MARK, D17_MARK, D18_MARK, D19_MARK,
+        D20_MARK, D21_MARK, D22_MARK, D23_MARK,
+        D24_MARK, D25_MARK, D26_MARK, D27_MARK,
+        D28_MARK, D29_MARK, D30_MARK, D31_MARK,
+};
+static const unsigned int bsc_cs0_pins[] = {
+        /* CS */
+        109,
+};
+static const unsigned int bsc_cs0_mux[] = {
+        CS0_MARK,
+};
+static const unsigned int bsc_cs2_pins[] = {
+        /* CS */
+        110,
+};
+static const unsigned int bsc_cs2_mux[] = {
+        CS2_MARK,
+};
+static const unsigned int bsc_cs4_pins[] = {
+        /* CS */
+        111,
+};
+static const unsigned int bsc_cs4_mux[] = {
+        CS4_MARK,
+};
+static const unsigned int bsc_cs5a_0_pins[] = {
+        /* CS */
+        105,
+};
+static const unsigned int bsc_cs5a_0_mux[] = {
+        CS5A_PORT105_MARK,
+};
+static const unsigned int bsc_cs5a_1_pins[] = {
+        /* CS */
+        19,
+};
+static const unsigned int bsc_cs5a_1_mux[] = {
+        CS5A_PORT19_MARK,
+};
+static const unsigned int bsc_cs5b_pins[] = {
+        /* CS */
+        103,
+};
+static const unsigned int bsc_cs5b_mux[] = {
+        CS5B_MARK,
+};
+static const unsigned int bsc_cs6a_pins[] = {
+        /* CS */
+        104,
+};
+static const unsigned int bsc_cs6a_mux[] = {
+        CS6A_MARK,
+};
+static const unsigned int bsc_rd_we8_pins[] = {
+        /* RD, WE[0] */
+        115, 113,
+};
+static const unsigned int bsc_rd_we8_mux[] = {
+        RD_FSC_MARK, WE0_FWE_MARK,
+};
+static const unsigned int bsc_rd_we16_pins[] = {
+        /* RD, WE[0:1] */
+        115, 113, 112,
+};
+static const unsigned int bsc_rd_we16_mux[] = {
+        RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
+};
+static const unsigned int bsc_rd_we32_pins[] = {
+        /* RD, WE[0:3] */
+        115, 113, 112, 108, 107,
+};
+static const unsigned int bsc_rd_we32_mux[] = {
+        RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
+};
+static const unsigned int bsc_bs_pins[] = {
+        /* BS */
+        175,
+};
+static const unsigned int bsc_bs_mux[] = {
+        BS_MARK,
+};
+static const unsigned int bsc_rdwr_pins[] = {
+        /* RDWR */
+        114,
+};
+static const unsigned int bsc_rdwr_mux[] = {
+        RDWR_MARK,
+};
+/* - CEU0 ------------------------------------------------------------------- */
+static const unsigned int ceu0_data_0_7_pins[] = {
+        /* D[0:7] */
+        34, 33, 32, 31, 30, 29, 28, 27,
+};
+static const unsigned int ceu0_data_0_7_mux[] = {
+        VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
+        VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
+};
+static const unsigned int ceu0_data_8_15_0_pins[] = {
+        /* D[8:15] */
+        182, 181, 180, 179, 178, 26, 25, 24,
+};
+static const unsigned int ceu0_data_8_15_0_mux[] = {
+        VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
+        VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK,
+        VIO0_D15_PORT24_MARK,
+};
+static const unsigned int ceu0_data_8_15_1_pins[] = {
+        /* D[8:15] */
+        182, 181, 180, 179, 178, 22, 95, 96,
+};
+static const unsigned int ceu0_data_8_15_1_mux[] = {
+        VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
+        VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK,
+        VIO0_D15_PORT96_MARK,
+};
+static const unsigned int ceu0_clk_0_pins[] = {
+        /* CKO */
+        36,
+};
+static const unsigned int ceu0_clk_0_mux[] = {
+        VIO_CKO_MARK,
+};
+static const unsigned int ceu0_clk_1_pins[] = {
+        /* CKO */
+        14,
+};
+static const unsigned int ceu0_clk_1_mux[] = {
+        VIO_CKO1_MARK,
+};
+static const unsigned int ceu0_clk_2_pins[] = {
+        /* CKO */
+        15,
+};
+static const unsigned int ceu0_clk_2_mux[] = {
+        VIO_CKO2_MARK,
+};
+static const unsigned int ceu0_sync_pins[] = {
+        /* CLK, VD, HD */
+        35, 39, 37,
+};
+static const unsigned int ceu0_sync_mux[] = {
+        VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK,
+};
+static const unsigned int ceu0_field_pins[] = {
+        /* FIELD */
+        38,
+};
+static const unsigned int ceu0_field_mux[] = {
+        VIO0_FIELD_MARK,
+};
+/* - CEU1 ------------------------------------------------------------------- */
+static const unsigned int ceu1_data_pins[] = {
+        /* D[0:7] */
+        182, 181, 180, 179, 178, 26, 25, 24,
+};
+static const unsigned int ceu1_data_mux[] = {
+        VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
+        VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
+};
+static const unsigned int ceu1_clk_pins[] = {
+        /* CKO */
+        23,
+};
+static const unsigned int ceu1_clk_mux[] = {
+        VIO_CKO_1_MARK,
+};
+static const unsigned int ceu1_sync_pins[] = {
+        /* CLK, VD, HD */
+        197, 198, 160,
+};
+static const unsigned int ceu1_sync_mux[] = {
+        VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK,
+};
+static const unsigned int ceu1_field_pins[] = {
+        /* FIELD */
+        21,
+};
+static const unsigned int ceu1_field_mux[] = {
+        VIO1_FIELD_MARK,
+};
+/* - FSIA ------------------------------------------------------------------- */
+static const unsigned int fsia_mclk_in_pins[] = {
+        /* CK */
+        11,
+};
+static const unsigned int fsia_mclk_in_mux[] = {
+        FSIACK_MARK,
+};
+static const unsigned int fsia_mclk_out_pins[] = {
+        /* OMC */
+        10,
+};
+static const unsigned int fsia_mclk_out_mux[] = {
+        FSIAOMC_MARK,
+};
+static const unsigned int fsia_sclk_in_pins[] = {
+        /* ILR, IBT */
+        12, 13,
+};
+static const unsigned int fsia_sclk_in_mux[] = {
+        FSIAILR_MARK, FSIAIBT_MARK,
+};
+static const unsigned int fsia_sclk_out_pins[] = {
+        /* OLR, OBT */
+        7, 8,
+};
+static const unsigned int fsia_sclk_out_mux[] = {
+        FSIAOLR_MARK, FSIAOBT_MARK,
+};
+static const unsigned int fsia_data_in_0_pins[] = {
+        /* ISLD */
+        0,
 };
+static const unsigned int fsia_data_in_0_mux[] = {
+        FSIAISLD_PORT0_MARK,
+};
+static const unsigned int fsia_data_in_1_pins[] = {
+        /* ISLD */
+        5,
+};
+static const unsigned int fsia_data_in_1_mux[] = {
+        FSIAISLD_PORT5_MARK,
+};
+static const unsigned int fsia_data_out_0_pins[] = {
+        /* OSLD */
+        9,
+};
+static const unsigned int fsia_data_out_0_mux[] = {
+        FSIAOSLD_MARK,
+};
+static const unsigned int fsia_data_out_1_pins[] = {
+        /* OSLD */
+        0,
+};
+static const unsigned int fsia_data_out_1_mux[] = {
+        FSIAOSLD1_MARK,
+};
+static const unsigned int fsia_data_out_2_pins[] = {
+        /* OSLD */
+        1,
+};
+static const unsigned int fsia_data_out_2_mux[] = {
+        FSIAOSLD2_MARK,
+};
+static const unsigned int fsia_spdif_0_pins[] = {
+        /* SPDIF */
+        9,
+};
+static const unsigned int fsia_spdif_0_mux[] = {
+        FSIASPDIF_PORT9_MARK,
+};
+static const unsigned int fsia_spdif_1_pins[] = {
+        /* SPDIF */
+        18,
+};
+static const unsigned int fsia_spdif_1_mux[] = {
+        FSIASPDIF_PORT18_MARK,
+};
+/* - FSIB ------------------------------------------------------------------- */
+static const unsigned int fsib_mclk_in_pins[] = {
+        /* CK */
+        11,
+};
+static const unsigned int fsib_mclk_in_mux[] = {
+        FSIBCK_MARK,
+};
+/* - GETHER ----------------------------------------------------------------- */
+static const unsigned int gether_rmii_pins[] = {
+        /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
+        195, 196, 194, 193, 200, 201, 199, 159, 202, 208,
+};
+static const unsigned int gether_rmii_mux[] = {
+        RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK,
+        RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK,
+        RMII_MDC_MARK, RMII_MDIO_MARK,
+};
+static const unsigned int gether_mii_pins[] = {
+        /* RXD[0:3], RX_CLK, RX_DV, RX_ER
+         * TXD[0:3], TX_CLK, TX_EN, TX_ER
+         * CRS, COL, MDC, MDIO,
+         */
+        185, 186, 187, 188, 174, 161, 204,
+        171, 170, 169, 168, 184, 183, 203,
+        205, 163, 206, 207,
+};
+static const unsigned int gether_mii_mux[] = {
+        ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
+        ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
+        ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
+        ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
+        ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
+};
+static const unsigned int gether_gmii_pins[] = {
+        /* RXD[0:7], RX_CLK, RX_DV, RX_ER
+         * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
+         * CRS, COL, MDC, MDIO, REF125CK_MARK,
+         */
+        185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
+        171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
+        205, 163, 206, 207,
+};
+static const unsigned int gether_gmii_mux[] = {
+        ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
+        ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK,
+        ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
+        ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
+        ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK,
+        ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
+        ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
+        RMII_REF125CK_MARK,
+};
+static const unsigned int gether_int_pins[] = {
+        /* PHY_INT */
+        164,
+};
+static const unsigned int gether_int_mux[] = {
+        ET_PHY_INT_MARK,
+};
+static const unsigned int gether_link_pins[] = {
+        /* LINK */
+        177,
+};
+static const unsigned int gether_link_mux[] = {
+        ET_LINK_MARK,
+};
+static const unsigned int gether_wol_pins[] = {
+        /* WOL */
+        175,
+};
+static const unsigned int gether_wol_mux[] = {
+        ET_WOL_MARK,
+};
+/* - HDMI ------------------------------------------------------------------- */
+static const unsigned int hdmi_pins[] = {
+        /* HPD, CEC */
+        210, 211,
+};
+static const unsigned int hdmi_mux[] = {
+        HDMI_HPD_MARK, HDMI_CEC_MARK,
+};
+/* - INTC ------------------------------------------------------------------- */
+IRQC_PINS_MUX(0, 0, 2);
+IRQC_PINS_MUX(0, 1, 13);
+IRQC_PIN_MUX(1, 20);
+IRQC_PINS_MUX(2, 0, 11);
+IRQC_PINS_MUX(2, 1, 12);
+IRQC_PINS_MUX(3, 0, 10);
+IRQC_PINS_MUX(3, 1, 14);
+IRQC_PINS_MUX(4, 0, 15);
+IRQC_PINS_MUX(4, 1, 172);
+IRQC_PINS_MUX(5, 0, 0);
+IRQC_PINS_MUX(5, 1, 1);
+IRQC_PINS_MUX(6, 0, 121);
+IRQC_PINS_MUX(6, 1, 173);
+IRQC_PINS_MUX(7, 0, 120);
+IRQC_PINS_MUX(7, 1, 209);
+IRQC_PIN_MUX(8, 119);
+IRQC_PINS_MUX(9, 0, 118);
+IRQC_PINS_MUX(9, 1, 210);
+IRQC_PIN_MUX(10, 19);
+IRQC_PIN_MUX(11, 104);
+IRQC_PINS_MUX(12, 0, 42);
+IRQC_PINS_MUX(12, 1, 97);
+IRQC_PINS_MUX(13, 0, 64);
+IRQC_PINS_MUX(13, 1, 98);
+IRQC_PINS_MUX(14, 0, 63);
+IRQC_PINS_MUX(14, 1, 99);
+IRQC_PINS_MUX(15, 0, 62);
+IRQC_PINS_MUX(15, 1, 100);
+IRQC_PINS_MUX(16, 0, 68);
+IRQC_PINS_MUX(16, 1, 211);
+IRQC_PIN_MUX(17, 69);
+IRQC_PIN_MUX(18, 70);
+IRQC_PIN_MUX(19, 71);
+IRQC_PIN_MUX(20, 67);
+IRQC_PIN_MUX(21, 202);
+IRQC_PIN_MUX(22, 95);
+IRQC_PIN_MUX(23, 96);
+IRQC_PIN_MUX(24, 180);
+IRQC_PIN_MUX(25, 38);
+IRQC_PINS_MUX(26, 0, 58);
+IRQC_PINS_MUX(26, 1, 81);
+IRQC_PINS_MUX(27, 0, 57);
+IRQC_PINS_MUX(27, 1, 168);
+IRQC_PINS_MUX(28, 0, 56);
+IRQC_PINS_MUX(28, 1, 169);
+IRQC_PINS_MUX(29, 0, 50);
+IRQC_PINS_MUX(29, 1, 170);
+IRQC_PINS_MUX(30, 0, 49);
+IRQC_PINS_MUX(30, 1, 171);
+IRQC_PINS_MUX(31, 0, 41);
+IRQC_PINS_MUX(31, 1, 167);
 
 /* - LCD0 ------------------------------------------------------------------- */
 static const unsigned int lcd0_data8_pins[] = {
@@ -1930,6 +2369,260 @@ static const unsigned int mmc0_ctrl_1_pins[] = {
 static const unsigned int mmc0_ctrl_1_mux[] = {
         MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
 };
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+        /* RXD, TXD */
+        197, 198,
+};
+static const unsigned int scifa0_data_mux[] = {
+        SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+        /* SCK */
+        188,
+};
+static const unsigned int scifa0_clk_mux[] = {
+        SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+        /* RTS, CTS */
+        194, 193,
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+        SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+        /* RXD, TXD */
+        195, 196,
+};
+static const unsigned int scifa1_data_mux[] = {
+        SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+        /* SCK */
+        185,
+};
+static const unsigned int scifa1_clk_mux[] = {
+        SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+        /* RTS, CTS */
+        23, 21,
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+        SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_pins[] = {
+        /* RXD, TXD */
+        200, 201,
+};
+static const unsigned int scifa2_data_mux[] = {
+        SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
+};
+static const unsigned int scifa2_clk_0_pins[] = {
+        /* SCK */
+        22,
+};
+static const unsigned int scifa2_clk_0_mux[] = {
+        SCIFA2_SCK_PORT22_MARK,
+};
+static const unsigned int scifa2_clk_1_pins[] = {
+        /* SCK */
+        199,
+};
+static const unsigned int scifa2_clk_1_mux[] = {
+        SCIFA2_SCK_PORT199_MARK,
+};
+static const unsigned int scifa2_ctrl_pins[] = {
+        /* RTS, CTS */
+        96, 95,
+};
+static const unsigned int scifa2_ctrl_mux[] = {
+        SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
+};
+/* - SCIFA3 ----------------------------------------------------------------- */
+static const unsigned int scifa3_data_0_pins[] = {
+        /* RXD, TXD */
+        174, 175,
+};
+static const unsigned int scifa3_data_0_mux[] = {
+        SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
+};
+static const unsigned int scifa3_clk_0_pins[] = {
+        /* SCK */
+        116,
+};
+static const unsigned int scifa3_clk_0_mux[] = {
+        SCIFA3_SCK_PORT116_MARK,
+};
+static const unsigned int scifa3_ctrl_0_pins[] = {
+        /* RTS, CTS */
+        105, 117,
+};
+static const unsigned int scifa3_ctrl_0_mux[] = {
+        SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
+};
+static const unsigned int scifa3_data_1_pins[] = {
+        /* RXD, TXD */
+        159, 160,
+};
+static const unsigned int scifa3_data_1_mux[] = {
+        SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
+};
+static const unsigned int scifa3_clk_1_pins[] = {
+        /* SCK */
+        158,
+};
+static const unsigned int scifa3_clk_1_mux[] = {
+        SCIFA3_SCK_PORT158_MARK,
+};
+static const unsigned int scifa3_ctrl_1_pins[] = {
+        /* RTS, CTS */
+        161, 162,
+};
+static const unsigned int scifa3_ctrl_1_mux[] = {
+        SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
+};
+/* - SCIFA4 ----------------------------------------------------------------- */
+static const unsigned int scifa4_data_0_pins[] = {
+        /* RXD, TXD */
+        12, 13,
+};
+static const unsigned int scifa4_data_0_mux[] = {
+        SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
+};
+static const unsigned int scifa4_data_1_pins[] = {
+        /* RXD, TXD */
+        204, 203,
+};
+static const unsigned int scifa4_data_1_mux[] = {
+        SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
+};
+static const unsigned int scifa4_data_2_pins[] = {
+        /* RXD, TXD */
+        94, 93,
+};
+static const unsigned int scifa4_data_2_mux[] = {
+        SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
+};
+static const unsigned int scifa4_clk_0_pins[] = {
+        /* SCK */
+        21,
+};
+static const unsigned int scifa4_clk_0_mux[] = {
+        SCIFA4_SCK_PORT21_MARK,
+};
+static const unsigned int scifa4_clk_1_pins[] = {
+        /* SCK */
+        205,
+};
+static const unsigned int scifa4_clk_1_mux[] = {
+        SCIFA4_SCK_PORT205_MARK,
+};
+/* - SCIFA5 ----------------------------------------------------------------- */
+static const unsigned int scifa5_data_0_pins[] = {
+        /* RXD, TXD */
+        10, 20,
+};
+static const unsigned int scifa5_data_0_mux[] = {
+        SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
+};
+static const unsigned int scifa5_data_1_pins[] = {
+        /* RXD, TXD */
+        207, 208,
+};
+static const unsigned int scifa5_data_1_mux[] = {
+        SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
+};
+static const unsigned int scifa5_data_2_pins[] = {
+        /* RXD, TXD */
+        92, 91,
+};
+static const unsigned int scifa5_data_2_mux[] = {
+        SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
+};
+static const unsigned int scifa5_clk_0_pins[] = {
+        /* SCK */
+        23,
+};
+static const unsigned int scifa5_clk_0_mux[] = {
+        SCIFA5_SCK_PORT23_MARK,
+};
+static const unsigned int scifa5_clk_1_pins[] = {
+        /* SCK */
+        206,
+};
+static const unsigned int scifa5_clk_1_mux[] = {
+        SCIFA5_SCK_PORT206_MARK,
+};
+/* - SCIFA6 ----------------------------------------------------------------- */
+static const unsigned int scifa6_data_pins[] = {
+        /* RXD, TXD */
+        25, 26,
+};
+static const unsigned int scifa6_data_mux[] = {
+        SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
+};
+static const unsigned int scifa6_clk_pins[] = {
+        /* SCK */
+        24,
+};
+static const unsigned int scifa6_clk_mux[] = {
+        SCIFA6_SCK_MARK,
+};
+/* - SCIFA7 ----------------------------------------------------------------- */
+static const unsigned int scifa7_data_pins[] = {
+        /* RXD, TXD */
+        0, 1,
+};
+static const unsigned int scifa7_data_mux[] = {
+        SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
+};
+/* - SCIFB ------------------------------------------------------------------ */
+static const unsigned int scifb_data_0_pins[] = {
+        /* RXD, TXD */
+        191, 192,
+};
+static const unsigned int scifb_data_0_mux[] = {
+        SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
+};
+static const unsigned int scifb_clk_0_pins[] = {
+        /* SCK */
+        190,
+};
+static const unsigned int scifb_clk_0_mux[] = {
+        SCIFB_SCK_PORT190_MARK,
+};
+static const unsigned int scifb_ctrl_0_pins[] = {
+        /* RTS, CTS */
+        186, 187,
+};
+static const unsigned int scifb_ctrl_0_mux[] = {
+        SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
+};
+static const unsigned int scifb_data_1_pins[] = {
+        /* RXD, TXD */
+        3, 4,
+};
+static const unsigned int scifb_data_1_mux[] = {
+        SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
+};
+static const unsigned int scifb_clk_1_pins[] = {
+        /* SCK */
+        2,
+};
+static const unsigned int scifb_clk_1_mux[] = {
+        SCIFB_SCK_PORT2_MARK,
+};
+static const unsigned int scifb_ctrl_1_pins[] = {
+        /* RTS, CTS */
+        172, 173,
+};
+static const unsigned int scifb_ctrl_1_mux[] = {
+        SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
+};
 /* - SDHI0 ------------------------------------------------------------------ */
 static const unsigned int sdhi0_data1_pins[] = {
         /* D0 */
@@ -2052,8 +2745,141 @@ static const unsigned int sdhi2_wp_1_pins[] = {
 static const unsigned int sdhi2_wp_1_mux[] = {
         SDHI2_WP_PORT25_MARK,
 };
+/* - TPU0 ------------------------------------------------------------------- */
+static const unsigned int tpu0_to0_pins[] = {
+        /* TO */
+        23,
+};
+static const unsigned int tpu0_to0_mux[] = {
+        TPU0TO0_MARK,
+};
+static const unsigned int tpu0_to1_pins[] = {
+        /* TO */
+        21,
+};
+static const unsigned int tpu0_to1_mux[] = {
+        TPU0TO1_MARK,
+};
+static const unsigned int tpu0_to2_0_pins[] = {
+        /* TO */
+        66,
+};
+static const unsigned int tpu0_to2_0_mux[] = {
+        TPU0TO2_PORT66_MARK,
+};
+static const unsigned int tpu0_to2_1_pins[] = {
+        /* TO */
+        202,
+};
+static const unsigned int tpu0_to2_1_mux[] = {
+        TPU0TO2_PORT202_MARK,
+};
+static const unsigned int tpu0_to3_pins[] = {
+        /* TO */
+        180,
+};
+static const unsigned int tpu0_to3_mux[] = {
+        TPU0TO3_MARK,
+};
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(bsc_data8),
+        SH_PFC_PIN_GROUP(bsc_data16),
+        SH_PFC_PIN_GROUP(bsc_data32),
+        SH_PFC_PIN_GROUP(bsc_cs0),
+        SH_PFC_PIN_GROUP(bsc_cs2),
+        SH_PFC_PIN_GROUP(bsc_cs4),
+        SH_PFC_PIN_GROUP(bsc_cs5a_0),
+        SH_PFC_PIN_GROUP(bsc_cs5a_1),
+        SH_PFC_PIN_GROUP(bsc_cs5b),
+        SH_PFC_PIN_GROUP(bsc_cs6a),
+        SH_PFC_PIN_GROUP(bsc_rd_we8),
+        SH_PFC_PIN_GROUP(bsc_rd_we16),
+        SH_PFC_PIN_GROUP(bsc_rd_we32),
+        SH_PFC_PIN_GROUP(bsc_bs),
+        SH_PFC_PIN_GROUP(bsc_rdwr),
+        SH_PFC_PIN_GROUP(ceu0_data_0_7),
+        SH_PFC_PIN_GROUP(ceu0_data_8_15_0),
+        SH_PFC_PIN_GROUP(ceu0_data_8_15_1),
+        SH_PFC_PIN_GROUP(ceu0_clk_0),
+        SH_PFC_PIN_GROUP(ceu0_clk_1),
+        SH_PFC_PIN_GROUP(ceu0_clk_2),
+        SH_PFC_PIN_GROUP(ceu0_sync),
+        SH_PFC_PIN_GROUP(ceu0_field),
+        SH_PFC_PIN_GROUP(ceu1_data),
+        SH_PFC_PIN_GROUP(ceu1_clk),
+        SH_PFC_PIN_GROUP(ceu1_sync),
+        SH_PFC_PIN_GROUP(ceu1_field),
+        SH_PFC_PIN_GROUP(fsia_mclk_in),
+        SH_PFC_PIN_GROUP(fsia_mclk_out),
+        SH_PFC_PIN_GROUP(fsia_sclk_in),
+        SH_PFC_PIN_GROUP(fsia_sclk_out),
+        SH_PFC_PIN_GROUP(fsia_data_in_0),
+        SH_PFC_PIN_GROUP(fsia_data_in_1),
+        SH_PFC_PIN_GROUP(fsia_data_out_0),
+        SH_PFC_PIN_GROUP(fsia_data_out_1),
+        SH_PFC_PIN_GROUP(fsia_data_out_2),
+        SH_PFC_PIN_GROUP(fsia_spdif_0),
+        SH_PFC_PIN_GROUP(fsia_spdif_1),
+        SH_PFC_PIN_GROUP(fsib_mclk_in),
+        SH_PFC_PIN_GROUP(gether_rmii),
+        SH_PFC_PIN_GROUP(gether_mii),
+        SH_PFC_PIN_GROUP(gether_gmii),
+        SH_PFC_PIN_GROUP(gether_int),
+        SH_PFC_PIN_GROUP(gether_link),
+        SH_PFC_PIN_GROUP(gether_wol),
+        SH_PFC_PIN_GROUP(hdmi),
+        SH_PFC_PIN_GROUP(intc_irq0_0),
+        SH_PFC_PIN_GROUP(intc_irq0_1),
+        SH_PFC_PIN_GROUP(intc_irq1),
+        SH_PFC_PIN_GROUP(intc_irq2_0),
+        SH_PFC_PIN_GROUP(intc_irq2_1),
+        SH_PFC_PIN_GROUP(intc_irq3_0),
+        SH_PFC_PIN_GROUP(intc_irq3_1),
+        SH_PFC_PIN_GROUP(intc_irq4_0),
+        SH_PFC_PIN_GROUP(intc_irq4_1),
+        SH_PFC_PIN_GROUP(intc_irq5_0),
+        SH_PFC_PIN_GROUP(intc_irq5_1),
+        SH_PFC_PIN_GROUP(intc_irq6_0),
+        SH_PFC_PIN_GROUP(intc_irq6_1),
+        SH_PFC_PIN_GROUP(intc_irq7_0),
+        SH_PFC_PIN_GROUP(intc_irq7_1),
+        SH_PFC_PIN_GROUP(intc_irq8),
+        SH_PFC_PIN_GROUP(intc_irq9_0),
+        SH_PFC_PIN_GROUP(intc_irq9_1),
+        SH_PFC_PIN_GROUP(intc_irq10),
+        SH_PFC_PIN_GROUP(intc_irq11),
+        SH_PFC_PIN_GROUP(intc_irq12_0),
+        SH_PFC_PIN_GROUP(intc_irq12_1),
+        SH_PFC_PIN_GROUP(intc_irq13_0),
+        SH_PFC_PIN_GROUP(intc_irq13_1),
+        SH_PFC_PIN_GROUP(intc_irq14_0),
+        SH_PFC_PIN_GROUP(intc_irq14_1),
+        SH_PFC_PIN_GROUP(intc_irq15_0),
+        SH_PFC_PIN_GROUP(intc_irq15_1),
+        SH_PFC_PIN_GROUP(intc_irq16_0),
+        SH_PFC_PIN_GROUP(intc_irq16_1),
+        SH_PFC_PIN_GROUP(intc_irq17),
+        SH_PFC_PIN_GROUP(intc_irq18),
+        SH_PFC_PIN_GROUP(intc_irq19),
+        SH_PFC_PIN_GROUP(intc_irq20),
+        SH_PFC_PIN_GROUP(intc_irq21),
+        SH_PFC_PIN_GROUP(intc_irq22),
+        SH_PFC_PIN_GROUP(intc_irq23),
+        SH_PFC_PIN_GROUP(intc_irq24),
+        SH_PFC_PIN_GROUP(intc_irq25),
+        SH_PFC_PIN_GROUP(intc_irq26_0),
+        SH_PFC_PIN_GROUP(intc_irq26_1),
+        SH_PFC_PIN_GROUP(intc_irq27_0),
+        SH_PFC_PIN_GROUP(intc_irq27_1),
+        SH_PFC_PIN_GROUP(intc_irq28_0),
+        SH_PFC_PIN_GROUP(intc_irq28_1),
+        SH_PFC_PIN_GROUP(intc_irq29_0),
+        SH_PFC_PIN_GROUP(intc_irq29_1),
+        SH_PFC_PIN_GROUP(intc_irq30_0),
+        SH_PFC_PIN_GROUP(intc_irq30_1),
+        SH_PFC_PIN_GROUP(intc_irq31_0),
+        SH_PFC_PIN_GROUP(intc_irq31_1),
         SH_PFC_PIN_GROUP(lcd0_data8),
         SH_PFC_PIN_GROUP(lcd0_data9),
         SH_PFC_PIN_GROUP(lcd0_data12),
@@ -2084,6 +2910,41 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(mmc0_data4_1),
         SH_PFC_PIN_GROUP(mmc0_data8_1),
         SH_PFC_PIN_GROUP(mmc0_ctrl_1),
+        SH_PFC_PIN_GROUP(scifa0_data),
+        SH_PFC_PIN_GROUP(scifa0_clk),
+        SH_PFC_PIN_GROUP(scifa0_ctrl),
+        SH_PFC_PIN_GROUP(scifa1_data),
+        SH_PFC_PIN_GROUP(scifa1_clk),
+        SH_PFC_PIN_GROUP(scifa1_ctrl),
+        SH_PFC_PIN_GROUP(scifa2_data),
+        SH_PFC_PIN_GROUP(scifa2_clk_0),
+        SH_PFC_PIN_GROUP(scifa2_clk_1),
+        SH_PFC_PIN_GROUP(scifa2_ctrl),
+        SH_PFC_PIN_GROUP(scifa3_data_0),
+        SH_PFC_PIN_GROUP(scifa3_clk_0),
+        SH_PFC_PIN_GROUP(scifa3_ctrl_0),
+        SH_PFC_PIN_GROUP(scifa3_data_1),
+        SH_PFC_PIN_GROUP(scifa3_clk_1),
+        SH_PFC_PIN_GROUP(scifa3_ctrl_1),
+        SH_PFC_PIN_GROUP(scifa4_data_0),
+        SH_PFC_PIN_GROUP(scifa4_data_1),
+        SH_PFC_PIN_GROUP(scifa4_data_2),
+        SH_PFC_PIN_GROUP(scifa4_clk_0),
+        SH_PFC_PIN_GROUP(scifa4_clk_1),
+        SH_PFC_PIN_GROUP(scifa5_data_0),
+        SH_PFC_PIN_GROUP(scifa5_data_1),
+        SH_PFC_PIN_GROUP(scifa5_data_2),
+        SH_PFC_PIN_GROUP(scifa5_clk_0),
+        SH_PFC_PIN_GROUP(scifa5_clk_1),
+        SH_PFC_PIN_GROUP(scifa6_data),
+        SH_PFC_PIN_GROUP(scifa6_clk),
+        SH_PFC_PIN_GROUP(scifa7_data),
+        SH_PFC_PIN_GROUP(scifb_data_0),
+        SH_PFC_PIN_GROUP(scifb_clk_0),
+        SH_PFC_PIN_GROUP(scifb_ctrl_0),
+        SH_PFC_PIN_GROUP(scifb_data_1),
+        SH_PFC_PIN_GROUP(scifb_clk_1),
+        SH_PFC_PIN_GROUP(scifb_ctrl_1),
         SH_PFC_PIN_GROUP(sdhi0_data1),
         SH_PFC_PIN_GROUP(sdhi0_data4),
         SH_PFC_PIN_GROUP(sdhi0_ctrl),
@@ -2101,6 +2962,132 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(sdhi2_wp_0),
         SH_PFC_PIN_GROUP(sdhi2_cd_1),
         SH_PFC_PIN_GROUP(sdhi2_wp_1),
+        SH_PFC_PIN_GROUP(tpu0_to0),
+        SH_PFC_PIN_GROUP(tpu0_to1),
+        SH_PFC_PIN_GROUP(tpu0_to2_0),
+        SH_PFC_PIN_GROUP(tpu0_to2_1),
+        SH_PFC_PIN_GROUP(tpu0_to3),
+};
+
+static const char * const bsc_groups[] = {
+        "bsc_data8",
+        "bsc_data16",
+        "bsc_data32",
+        "bsc_cs0",
+        "bsc_cs2",
+        "bsc_cs4",
+        "bsc_cs5a_0",
+        "bsc_cs5a_1",
+        "bsc_cs5b",
+        "bsc_cs6a",
+        "bsc_rd_we8",
+        "bsc_rd_we16",
+        "bsc_rd_we32",
+        "bsc_bs",
+        "bsc_rdwr",
+};
+
+static const char * const ceu0_groups[] = {
+        "ceu0_data_0_7",
+        "ceu0_data_8_15_0",
+        "ceu0_data_8_15_1",
+        "ceu0_clk_0",
+        "ceu0_clk_1",
+        "ceu0_clk_2",
+        "ceu0_sync",
+        "ceu0_field",
+};
+
+static const char * const ceu1_groups[] = {
+        "ceu1_data",
+        "ceu1_clk",
+        "ceu1_sync",
+        "ceu1_field",
+};
+
+static const char * const fsia_groups[] = {
+        "fsia_mclk_in",
+        "fsia_mclk_out",
+        "fsia_sclk_in",
+        "fsia_sclk_out",
+        "fsia_data_in_0",
+        "fsia_data_in_1",
+        "fsia_data_out_0",
+        "fsia_data_out_1",
+        "fsia_data_out_2",
+        "fsia_spdif_0",
+        "fsia_spdif_1",
+};
+
+static const char * const fsib_groups[] = {
+        "fsib_mclk_in",
+};
+
+static const char * const gether_groups[] = {
+        "gether_rmii",
+        "gether_mii",
+        "gether_gmii",
+        "gether_int",
+        "gether_link",
+        "gether_wol",
+};
+
+static const char * const hdmi_groups[] = {
+        "hdmi",
+};
+
+static const char * const intc_groups[] = {
+        "intc_irq0_0",
+        "intc_irq0_1",
+        "intc_irq1",
+        "intc_irq2_0",
+        "intc_irq2_1",
+        "intc_irq3_0",
+        "intc_irq3_1",
+        "intc_irq4_0",
+        "intc_irq4_1",
+        "intc_irq5_0",
+        "intc_irq5_1",
+        "intc_irq6_0",
+        "intc_irq6_1",
+        "intc_irq7_0",
+        "intc_irq7_1",
+        "intc_irq8",
+        "intc_irq9_0",
+        "intc_irq9_1",
+        "intc_irq10",
+        "intc_irq11",
+        "intc_irq12_0",
+        "intc_irq12_1",
+        "intc_irq13_0",
+        "intc_irq13_1",
+        "intc_irq14_0",
+        "intc_irq14_1",
+        "intc_irq15_0",
+        "intc_irq15_1",
+        "intc_irq16_0",
+        "intc_irq16_1",
+        "intc_irq17",
+        "intc_irq18",
+        "intc_irq19",
+        "intc_irq20",
+        "intc_irq21",
+        "intc_irq22",
+        "intc_irq23",
+        "intc_irq24",
+        "intc_irq25",
+        "intc_irq26_0",
+        "intc_irq26_1",
+        "intc_irq27_0",
+        "intc_irq27_1",
+        "intc_irq28_0",
+        "intc_irq28_1",
+        "intc_irq29_0",
+        "intc_irq29_1",
+        "intc_irq30_0",
+        "intc_irq30_1",
+        "intc_irq31_0",
+        "intc_irq31_1",
 };
 
 static const char * const lcd0_groups[] = {
@@ -2142,6 +3129,68 @@ static const char * const mmc0_groups[] = {
         "mmc0_ctrl_1",
 };
 
+static const char * const scifa0_groups[] = {
+        "scifa0_data",
+        "scifa0_clk",
+        "scifa0_ctrl",
+};
+
+static const char * const scifa1_groups[] = {
+        "scifa1_data",
+        "scifa1_clk",
+        "scifa1_ctrl",
+};
+
+static const char * const scifa2_groups[] = {
+        "scifa2_data",
+        "scifa2_clk_0",
+        "scifa2_clk_1",
+        "scifa2_ctrl",
+};
+
+static const char * const scifa3_groups[] = {
+        "scifa3_data_0",
+        "scifa3_clk_0",
+        "scifa3_ctrl_0",
+        "scifa3_data_1",
+        "scifa3_clk_1",
+        "scifa3_ctrl_1",
+};
+
+static const char * const scifa4_groups[] = {
+        "scifa4_data_0",
+        "scifa4_data_1",
+        "scifa4_data_2",
+        "scifa4_clk_0",
+        "scifa4_clk_1",
+};
+
+static const char * const scifa5_groups[] = {
+        "scifa5_data_0",
+        "scifa5_data_1",
+        "scifa5_data_2",
+        "scifa5_clk_0",
+        "scifa5_clk_1",
+};
+
+static const char * const scifa6_groups[] = {
+        "scifa6_data",
+        "scifa6_clk",
+};
+
+static const char * const scifa7_groups[] = {
+        "scifa7_data",
+};
+
+static const char * const scifb_groups[] = {
+        "scifb_data_0",
+        "scifb_clk_0",
+        "scifb_ctrl_0",
+        "scifb_data_1",
+        "scifb_clk_1",
+        "scifb_ctrl_1",
+};
+
 static const char * const sdhi0_groups[] = {
         "sdhi0_data1",
         "sdhi0_data4",
@@ -2168,412 +3217,51 @@ static const char * const sdhi2_groups[] = {
         "sdhi2_wp_1",
 };
 
+static const char * const tpu0_groups[] = {
+        "tpu0_to0",
+        "tpu0_to1",
+        "tpu0_to2_0",
+        "tpu0_to2_1",
+        "tpu0_to3",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(bsc),
+        SH_PFC_FUNCTION(ceu0),
+        SH_PFC_FUNCTION(ceu1),
+        SH_PFC_FUNCTION(fsia),
+        SH_PFC_FUNCTION(fsib),
+        SH_PFC_FUNCTION(gether),
+        SH_PFC_FUNCTION(hdmi),
+        SH_PFC_FUNCTION(intc),
         SH_PFC_FUNCTION(lcd0),
         SH_PFC_FUNCTION(lcd1),
         SH_PFC_FUNCTION(mmc0),
+        SH_PFC_FUNCTION(scifa0),
+        SH_PFC_FUNCTION(scifa1),
+        SH_PFC_FUNCTION(scifa2),
+        SH_PFC_FUNCTION(scifa3),
+        SH_PFC_FUNCTION(scifa4),
+        SH_PFC_FUNCTION(scifa5),
+        SH_PFC_FUNCTION(scifa6),
+        SH_PFC_FUNCTION(scifa7),
+        SH_PFC_FUNCTION(scifb),
         SH_PFC_FUNCTION(sdhi0),
         SH_PFC_FUNCTION(sdhi1),
         SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(tpu0),
 };
 
-#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-        /* IRQ */
-        GPIO_FN(IRQ0_PORT2),    GPIO_FN(IRQ0_PORT13),
-        GPIO_FN(IRQ1),
-        GPIO_FN(IRQ2_PORT11),   GPIO_FN(IRQ2_PORT12),
-        GPIO_FN(IRQ3_PORT10),   GPIO_FN(IRQ3_PORT14),
-        GPIO_FN(IRQ4_PORT15),   GPIO_FN(IRQ4_PORT172),
-        GPIO_FN(IRQ5_PORT0),    GPIO_FN(IRQ5_PORT1),
-        GPIO_FN(IRQ6_PORT121),  GPIO_FN(IRQ6_PORT173),
-        GPIO_FN(IRQ7_PORT120),  GPIO_FN(IRQ7_PORT209),
-        GPIO_FN(IRQ8),
-        GPIO_FN(IRQ9_PORT118),  GPIO_FN(IRQ9_PORT210),
-        GPIO_FN(IRQ10),
-        GPIO_FN(IRQ11),
-        GPIO_FN(IRQ12_PORT42),  GPIO_FN(IRQ12_PORT97),
-        GPIO_FN(IRQ13_PORT64),  GPIO_FN(IRQ13_PORT98),
-        GPIO_FN(IRQ14_PORT63),  GPIO_FN(IRQ14_PORT99),
-        GPIO_FN(IRQ15_PORT62),  GPIO_FN(IRQ15_PORT100),
-        GPIO_FN(IRQ16_PORT68),  GPIO_FN(IRQ16_PORT211),
-        GPIO_FN(IRQ17),
-        GPIO_FN(IRQ18),
-        GPIO_FN(IRQ19),
-        GPIO_FN(IRQ20),
-        GPIO_FN(IRQ21),
-        GPIO_FN(IRQ22),
-        GPIO_FN(IRQ23),
-        GPIO_FN(IRQ24),
-        GPIO_FN(IRQ25),
-        GPIO_FN(IRQ26_PORT58),  GPIO_FN(IRQ26_PORT81),
-        GPIO_FN(IRQ27_PORT57),  GPIO_FN(IRQ27_PORT168),
-        GPIO_FN(IRQ28_PORT56),  GPIO_FN(IRQ28_PORT169),
-        GPIO_FN(IRQ29_PORT50),  GPIO_FN(IRQ29_PORT170),
-        GPIO_FN(IRQ30_PORT49),  GPIO_FN(IRQ30_PORT171),
-        GPIO_FN(IRQ31_PORT41),  GPIO_FN(IRQ31_PORT167),
-
-        /* Function */
-
-        /* DBGT */
-        GPIO_FN(DBGMDT2),       GPIO_FN(DBGMDT1),       GPIO_FN(DBGMDT0),
-        GPIO_FN(DBGMD10),       GPIO_FN(DBGMD11),       GPIO_FN(DBGMD20),
-        GPIO_FN(DBGMD21),
-
-        /* FSI-A */
-        GPIO_FN(FSIAISLD_PORT0),        /* FSIAISLD Port 0/5 */
-        GPIO_FN(FSIAISLD_PORT5),
-        GPIO_FN(FSIASPDIF_PORT9),       /* FSIASPDIF Port 9/18 */
-        GPIO_FN(FSIASPDIF_PORT18),
-        GPIO_FN(FSIAOSLD1),     GPIO_FN(FSIAOSLD2),     GPIO_FN(FSIAOLR),
-        GPIO_FN(FSIAOBT),       GPIO_FN(FSIAOSLD),      GPIO_FN(FSIAOMC),
-        GPIO_FN(FSIACK),        GPIO_FN(FSIAILR),       GPIO_FN(FSIAIBT),
-
-        /* FSI-B */
-        GPIO_FN(FSIBCK),
-
-        /* FMSI */
-        GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
-        GPIO_FN(FMSISLD_PORT6),
-        GPIO_FN(FMSIILR),       GPIO_FN(FMSIIBT),       GPIO_FN(FMSIOLR),
-        GPIO_FN(FMSIOBT),       GPIO_FN(FMSICK),        GPIO_FN(FMSOILR),
-        GPIO_FN(FMSOIBT),       GPIO_FN(FMSOOLR),       GPIO_FN(FMSOOBT),
-        GPIO_FN(FMSOSLD),       GPIO_FN(FMSOCK),
-
-        /* SCIFA0 */
-        GPIO_FN(SCIFA0_SCK),    GPIO_FN(SCIFA0_CTS),    GPIO_FN(SCIFA0_RTS),
-        GPIO_FN(SCIFA0_RXD),    GPIO_FN(SCIFA0_TXD),
-
-        /* SCIFA1 */
-        GPIO_FN(SCIFA1_CTS),    GPIO_FN(SCIFA1_SCK),
-        GPIO_FN(SCIFA1_RXD),    GPIO_FN(SCIFA1_TXD),    GPIO_FN(SCIFA1_RTS),
-
-        /* SCIFA2 */
-        GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */
-        GPIO_FN(SCIFA2_SCK_PORT199),
-        GPIO_FN(SCIFA2_RXD),    GPIO_FN(SCIFA2_TXD),
-        GPIO_FN(SCIFA2_CTS),    GPIO_FN(SCIFA2_RTS),
-
-        /* SCIFA3 */
-        GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */
-        GPIO_FN(SCIFA3_SCK_PORT116),
-        GPIO_FN(SCIFA3_CTS_PORT117),
-        GPIO_FN(SCIFA3_RXD_PORT174),
-        GPIO_FN(SCIFA3_TXD_PORT175),
-
-        GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */
-        GPIO_FN(SCIFA3_SCK_PORT158),
-        GPIO_FN(SCIFA3_CTS_PORT162),
-        GPIO_FN(SCIFA3_RXD_PORT159),
-        GPIO_FN(SCIFA3_TXD_PORT160),
-
-        /* SCIFA4 */
-        GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */
-        GPIO_FN(SCIFA4_TXD_PORT13),
-
-        GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */
-        GPIO_FN(SCIFA4_TXD_PORT203),
-
-        GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */
-        GPIO_FN(SCIFA4_TXD_PORT93),
-
-        GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */
-        GPIO_FN(SCIFA4_SCK_PORT205),
-
-        /* SCIFA5 */
-        GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */
-        GPIO_FN(SCIFA5_RXD_PORT10),
-
-        GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */
-        GPIO_FN(SCIFA5_TXD_PORT208),
-
-        GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */
-        GPIO_FN(SCIFA5_RXD_PORT92),
-
-        GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */
-        GPIO_FN(SCIFA5_SCK_PORT206),
-
-        /* SCIFA6 */
-        GPIO_FN(SCIFA6_SCK),    GPIO_FN(SCIFA6_RXD),    GPIO_FN(SCIFA6_TXD),
-
-        /* SCIFA7 */
-        GPIO_FN(SCIFA7_TXD),    GPIO_FN(SCIFA7_RXD),
-
-        /* SCIFAB */
-        GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */
-        GPIO_FN(SCIFB_RXD_PORT191),
-        GPIO_FN(SCIFB_TXD_PORT192),
-        GPIO_FN(SCIFB_RTS_PORT186),
-        GPIO_FN(SCIFB_CTS_PORT187),
-
-        GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */
-        GPIO_FN(SCIFB_RXD_PORT3),
-        GPIO_FN(SCIFB_TXD_PORT4),
-        GPIO_FN(SCIFB_RTS_PORT172),
-        GPIO_FN(SCIFB_CTS_PORT173),
-
-        /* RSPI */
-        GPIO_FN(RSPI_SSL0_A),   GPIO_FN(RSPI_SSL1_A),   GPIO_FN(RSPI_SSL2_A),
-        GPIO_FN(RSPI_SSL3_A),   GPIO_FN(RSPI_CK_A),     GPIO_FN(RSPI_MOSI_A),
-        GPIO_FN(RSPI_MISO_A),
-
-        /* VIO CKO */
-        GPIO_FN(VIO_CKO1),
-        GPIO_FN(VIO_CKO2),
-        GPIO_FN(VIO_CKO_1),
-        GPIO_FN(VIO_CKO),
-
-        /* VIO0 */
-        GPIO_FN(VIO0_D0),       GPIO_FN(VIO0_D1),       GPIO_FN(VIO0_D2),
-        GPIO_FN(VIO0_D3),       GPIO_FN(VIO0_D4),       GPIO_FN(VIO0_D5),
-        GPIO_FN(VIO0_D6),       GPIO_FN(VIO0_D7),       GPIO_FN(VIO0_D8),
-        GPIO_FN(VIO0_D9),       GPIO_FN(VIO0_D10),      GPIO_FN(VIO0_D11),
-        GPIO_FN(VIO0_D12),      GPIO_FN(VIO0_VD),       GPIO_FN(VIO0_HD),
-        GPIO_FN(VIO0_CLK),      GPIO_FN(VIO0_FIELD),
-
-        GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */
-        GPIO_FN(VIO0_D14_PORT25),
-        GPIO_FN(VIO0_D15_PORT24),
-
-        GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */
-        GPIO_FN(VIO0_D14_PORT95),
-        GPIO_FN(VIO0_D15_PORT96),
-
-        /* VIO1 */
-        GPIO_FN(VIO1_D0),       GPIO_FN(VIO1_D1),       GPIO_FN(VIO1_D2),
-        GPIO_FN(VIO1_D3),       GPIO_FN(VIO1_D4),       GPIO_FN(VIO1_D5),
-        GPIO_FN(VIO1_D6),       GPIO_FN(VIO1_D7),       GPIO_FN(VIO1_VD),
-        GPIO_FN(VIO1_HD),       GPIO_FN(VIO1_CLK),      GPIO_FN(VIO1_FIELD),
-
-        /* TPU0 */
-        GPIO_FN(TPU0TO0),       GPIO_FN(TPU0TO1),       GPIO_FN(TPU0TO3),
-        GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
-        GPIO_FN(TPU0TO2_PORT202),
-
-        /* SSP1 0 */
-        GPIO_FN(STP0_IPD0),     GPIO_FN(STP0_IPD1),     GPIO_FN(STP0_IPD2),
-        GPIO_FN(STP0_IPD3),     GPIO_FN(STP0_IPD4),     GPIO_FN(STP0_IPD5),
-        GPIO_FN(STP0_IPD6),     GPIO_FN(STP0_IPD7),     GPIO_FN(STP0_IPEN),
-        GPIO_FN(STP0_IPCLK),    GPIO_FN(STP0_IPSYNC),
-
-        /* SSP1 1 */
-        GPIO_FN(STP1_IPD1),     GPIO_FN(STP1_IPD2),     GPIO_FN(STP1_IPD3),
-        GPIO_FN(STP1_IPD4),     GPIO_FN(STP1_IPD5),     GPIO_FN(STP1_IPD6),
-        GPIO_FN(STP1_IPD7),     GPIO_FN(STP1_IPCLK),    GPIO_FN(STP1_IPSYNC),
-
-        GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */
-        GPIO_FN(STP1_IPEN_PORT187),
-
-        GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */
-        GPIO_FN(STP1_IPEN_PORT193),
-
-        /* SIM */
-        GPIO_FN(SIM_RST),       GPIO_FN(SIM_CLK),
-        GPIO_FN(SIM_D_PORT22), /* SIM_D  Port 22/199 */
-        GPIO_FN(SIM_D_PORT199),
-
-        /* MSIOF2 */
-        GPIO_FN(MSIOF2_TXD),    GPIO_FN(MSIOF2_RXD),    GPIO_FN(MSIOF2_TSCK),
-        GPIO_FN(MSIOF2_SS2),    GPIO_FN(MSIOF2_TSYNC),  GPIO_FN(MSIOF2_SS1),
-        GPIO_FN(MSIOF2_MCK1),   GPIO_FN(MSIOF2_MCK0),   GPIO_FN(MSIOF2_RSYNC),
-        GPIO_FN(MSIOF2_RSCK),
-
-        /* KEYSC */
-        GPIO_FN(KEYIN4),        GPIO_FN(KEYIN5),
-        GPIO_FN(KEYIN6),        GPIO_FN(KEYIN7),
-        GPIO_FN(KEYOUT0),       GPIO_FN(KEYOUT1),       GPIO_FN(KEYOUT2),
-        GPIO_FN(KEYOUT3),       GPIO_FN(KEYOUT4),       GPIO_FN(KEYOUT5),
-        GPIO_FN(KEYOUT6),       GPIO_FN(KEYOUT7),
-
-        GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */
-        GPIO_FN(KEYIN1_PORT44),
-        GPIO_FN(KEYIN2_PORT45),
-        GPIO_FN(KEYIN3_PORT46),
-
-        GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */
-        GPIO_FN(KEYIN1_PORT57),
-        GPIO_FN(KEYIN2_PORT56),
-        GPIO_FN(KEYIN3_PORT55),
-
-        /* VOU */
-        GPIO_FN(DV_D0),         GPIO_FN(DV_D1),         GPIO_FN(DV_D2),
-        GPIO_FN(DV_D3),         GPIO_FN(DV_D4),         GPIO_FN(DV_D5),
-        GPIO_FN(DV_D6),         GPIO_FN(DV_D7),         GPIO_FN(DV_D8),
-        GPIO_FN(DV_D9),         GPIO_FN(DV_D10),        GPIO_FN(DV_D11),
-        GPIO_FN(DV_D12),        GPIO_FN(DV_D13),        GPIO_FN(DV_D14),
-        GPIO_FN(DV_D15),        GPIO_FN(DV_CLK),
-        GPIO_FN(DV_VSYNC),      GPIO_FN(DV_HSYNC),
-
-        /* MEMC */
-        GPIO_FN(MEMC_AD0),      GPIO_FN(MEMC_AD1),      GPIO_FN(MEMC_AD2),
-        GPIO_FN(MEMC_AD3),      GPIO_FN(MEMC_AD4),      GPIO_FN(MEMC_AD5),
-        GPIO_FN(MEMC_AD6),      GPIO_FN(MEMC_AD7),      GPIO_FN(MEMC_AD8),
-        GPIO_FN(MEMC_AD9),      GPIO_FN(MEMC_AD10),     GPIO_FN(MEMC_AD11),
-        GPIO_FN(MEMC_AD12),     GPIO_FN(MEMC_AD13),     GPIO_FN(MEMC_AD14),
-        GPIO_FN(MEMC_AD15),     GPIO_FN(MEMC_CS0),      GPIO_FN(MEMC_INT),
-        GPIO_FN(MEMC_NWE),      GPIO_FN(MEMC_NOE),      GPIO_FN(MEMC_CS1),
-        GPIO_FN(MEMC_A1),       GPIO_FN(MEMC_ADV),      GPIO_FN(MEMC_DREQ0),
-        GPIO_FN(MEMC_WAIT),     GPIO_FN(MEMC_DREQ1),    GPIO_FN(MEMC_BUSCLK),
-        GPIO_FN(MEMC_A0),
-
-        /* MSIOF0 */
-        GPIO_FN(MSIOF0_SS1),    GPIO_FN(MSIOF0_SS2),    GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(MSIOF0_TXD),    GPIO_FN(MSIOF0_MCK0),   GPIO_FN(MSIOF0_MCK1),
-        GPIO_FN(MSIOF0_RSYNC),  GPIO_FN(MSIOF0_RSCK),   GPIO_FN(MSIOF0_TSCK),
-        GPIO_FN(MSIOF0_TSYNC),
-
-        /* MSIOF1 */
-        GPIO_FN(MSIOF1_RSCK),   GPIO_FN(MSIOF1_RSYNC),
-        GPIO_FN(MSIOF1_MCK0),   GPIO_FN(MSIOF1_MCK1),
-
-        GPIO_FN(MSIOF1_SS2_PORT116),    GPIO_FN(MSIOF1_SS1_PORT117),
-        GPIO_FN(MSIOF1_RXD_PORT118),    GPIO_FN(MSIOF1_TXD_PORT119),
-        GPIO_FN(MSIOF1_TSYNC_PORT120),
-        GPIO_FN(MSIOF1_TSCK_PORT121),   /* MSEL4CR_10_0 */
-
-        GPIO_FN(MSIOF1_SS1_PORT67),     GPIO_FN(MSIOF1_TSCK_PORT72),
-        GPIO_FN(MSIOF1_TSYNC_PORT73),   GPIO_FN(MSIOF1_TXD_PORT74),
-        GPIO_FN(MSIOF1_RXD_PORT75),
-        GPIO_FN(MSIOF1_SS2_PORT202),    /* MSEL4CR_10_1 */
-
-        /* GPIO */
-        GPIO_FN(GPO0),  GPIO_FN(GPI0),
-        GPIO_FN(GPO1),  GPIO_FN(GPI1),
-
-        /* USB0 */
-        GPIO_FN(USB0_OCI),      GPIO_FN(USB0_PPON),     GPIO_FN(VBUS),
-
-        /* USB1 */
-        GPIO_FN(USB1_OCI),      GPIO_FN(USB1_PPON),
-
-        /* BBIF1 */
-        GPIO_FN(BBIF1_RXD),     GPIO_FN(BBIF1_TXD),     GPIO_FN(BBIF1_TSYNC),
-        GPIO_FN(BBIF1_TSCK),    GPIO_FN(BBIF1_RSCK),    GPIO_FN(BBIF1_RSYNC),
-        GPIO_FN(BBIF1_FLOW),    GPIO_FN(BBIF1_RX_FLOW_N),
-
-        /* BBIF2 */
-        GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */
-        GPIO_FN(BBIF2_RXD2_PORT60),
-        GPIO_FN(BBIF2_TSYNC2_PORT6),
-        GPIO_FN(BBIF2_TSCK2_PORT59),
-
-        GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */
-        GPIO_FN(BBIF2_TXD2_PORT183),
-        GPIO_FN(BBIF2_TSCK2_PORT89),
-        GPIO_FN(BBIF2_TSYNC2_PORT184),
-
-        /* BSC / FLCTL / PCMCIA */
-        GPIO_FN(CS0),   GPIO_FN(CS2),   GPIO_FN(CS4),
-        GPIO_FN(CS5B),  GPIO_FN(CS6A),
-        GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */
-        GPIO_FN(CS5A_PORT19),
-        GPIO_FN(IOIS16), /* ? */
-
-        GPIO_FN(A0),    GPIO_FN(A1),    GPIO_FN(A2),    GPIO_FN(A3),
-        GPIO_FN(A4_FOE),        GPIO_FN(A5_FCDE),       /* share with FLCTL */
-        GPIO_FN(A6),    GPIO_FN(A7),    GPIO_FN(A8),    GPIO_FN(A9),
-        GPIO_FN(A10),   GPIO_FN(A11),   GPIO_FN(A12),   GPIO_FN(A13),
-        GPIO_FN(A14),   GPIO_FN(A15),   GPIO_FN(A16),   GPIO_FN(A17),
-        GPIO_FN(A18),   GPIO_FN(A19),   GPIO_FN(A20),   GPIO_FN(A21),
-        GPIO_FN(A22),   GPIO_FN(A23),   GPIO_FN(A24),   GPIO_FN(A25),
-        GPIO_FN(A26),
-
-        GPIO_FN(D0_NAF0),       GPIO_FN(D1_NAF1),       /* share with FLCTL */
-        GPIO_FN(D2_NAF2),       GPIO_FN(D3_NAF3),       /* share with FLCTL */
-        GPIO_FN(D4_NAF4),       GPIO_FN(D5_NAF5),       /* share with FLCTL */
-        GPIO_FN(D6_NAF6),       GPIO_FN(D7_NAF7),       /* share with FLCTL */
-        GPIO_FN(D8_NAF8),       GPIO_FN(D9_NAF9),       /* share with FLCTL */
-        GPIO_FN(D10_NAF10),     GPIO_FN(D11_NAF11),     /* share with FLCTL */
-        GPIO_FN(D12_NAF12),     GPIO_FN(D13_NAF13),     /* share with FLCTL */
-        GPIO_FN(D14_NAF14),     GPIO_FN(D15_NAF15),     /* share with FLCTL */
-        GPIO_FN(D16),   GPIO_FN(D17),   GPIO_FN(D18),   GPIO_FN(D19),
-        GPIO_FN(D20),   GPIO_FN(D21),   GPIO_FN(D22),   GPIO_FN(D23),
-        GPIO_FN(D24),   GPIO_FN(D25),   GPIO_FN(D26),   GPIO_FN(D27),
-        GPIO_FN(D28),   GPIO_FN(D29),   GPIO_FN(D30),   GPIO_FN(D31),
-
-        GPIO_FN(WE0_FWE),       /* share with FLCTL */
-        GPIO_FN(WE1),
-        GPIO_FN(WE2_ICIORD),    /* share with PCMCIA */
-        GPIO_FN(WE3_ICIOWR),    /* share with PCMCIA */
-        GPIO_FN(CKO),   GPIO_FN(BS),    GPIO_FN(RDWR),
-        GPIO_FN(RD_FSC),        /* share with FLCTL */
-        GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
-        GPIO_FN(WAIT_PORT90),
-
-        GPIO_FN(FCE0),  GPIO_FN(FCE1),  GPIO_FN(FRB), /* FLCTL */
-
-        /* IRDA */
-        GPIO_FN(IRDA_FIRSEL),   GPIO_FN(IRDA_IN),       GPIO_FN(IRDA_OUT),
-
-        /* ATAPI */
-        GPIO_FN(IDE_D0),        GPIO_FN(IDE_D1),        GPIO_FN(IDE_D2),
-        GPIO_FN(IDE_D3),        GPIO_FN(IDE_D4),        GPIO_FN(IDE_D5),
-        GPIO_FN(IDE_D6),        GPIO_FN(IDE_D7),        GPIO_FN(IDE_D8),
-        GPIO_FN(IDE_D9),        GPIO_FN(IDE_D10),       GPIO_FN(IDE_D11),
-        GPIO_FN(IDE_D12),       GPIO_FN(IDE_D13),       GPIO_FN(IDE_D14),
-        GPIO_FN(IDE_D15),       GPIO_FN(IDE_A0),        GPIO_FN(IDE_A1),
-        GPIO_FN(IDE_A2),        GPIO_FN(IDE_CS0),       GPIO_FN(IDE_CS1),
-        GPIO_FN(IDE_IOWR),      GPIO_FN(IDE_IORD),      GPIO_FN(IDE_IORDY),
-        GPIO_FN(IDE_INT),       GPIO_FN(IDE_RST),       GPIO_FN(IDE_DIRECTION),
-        GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK),    GPIO_FN(IDE_IODREQ),
-
-        /* RMII */
-        GPIO_FN(RMII_CRS_DV),   GPIO_FN(RMII_RX_ER),    GPIO_FN(RMII_RXD0),
-        GPIO_FN(RMII_RXD1),     GPIO_FN(RMII_TX_EN),    GPIO_FN(RMII_TXD0),
-        GPIO_FN(RMII_MDC),      GPIO_FN(RMII_TXD1),     GPIO_FN(RMII_MDIO),
-        GPIO_FN(RMII_REF50CK),  GPIO_FN(RMII_REF125CK), /* for GMII */
-
-        /* GEther */
-        GPIO_FN(ET_TX_CLK),     GPIO_FN(ET_TX_EN),      GPIO_FN(ET_ETXD0),
-        GPIO_FN(ET_ETXD1),      GPIO_FN(ET_ETXD2),      GPIO_FN(ET_ETXD3),
-        GPIO_FN(ET_ETXD4),      GPIO_FN(ET_ETXD5), /* for GEther */
-        GPIO_FN(ET_ETXD6),      GPIO_FN(ET_ETXD7), /* for GEther */
-        GPIO_FN(ET_COL),        GPIO_FN(ET_TX_ER),      GPIO_FN(ET_RX_CLK),
-        GPIO_FN(ET_RX_DV),      GPIO_FN(ET_ERXD0),      GPIO_FN(ET_ERXD1),
-        GPIO_FN(ET_ERXD2),      GPIO_FN(ET_ERXD3),
-        GPIO_FN(ET_ERXD4),      GPIO_FN(ET_ERXD5), /* for GEther */
-        GPIO_FN(ET_ERXD6),      GPIO_FN(ET_ERXD7), /* for GEther */
-        GPIO_FN(ET_RX_ER),      GPIO_FN(ET_CRS),        GPIO_FN(ET_MDC),
-        GPIO_FN(ET_MDIO),       GPIO_FN(ET_LINK),       GPIO_FN(ET_PHY_INT),
-        GPIO_FN(ET_WOL),        GPIO_FN(ET_GTX_CLK),
-
-        /* DMA0 */
-        GPIO_FN(DREQ0), GPIO_FN(DACK0),
-
-        /* DMA1 */
-        GPIO_FN(DREQ1), GPIO_FN(DACK1),
-
-        /* SYSC */
-        GPIO_FN(RESETOUTS),
-
-        /* IRREM */
-        GPIO_FN(IROUT),
-
-        /* LCDC */
-        GPIO_FN(LCDC0_SELECT),
-        GPIO_FN(LCDC1_SELECT),
-
-        /* SDENC */
-        GPIO_FN(SDENC_CPG),
-        GPIO_FN(SDENC_DV_CLKI),
-
-        /* HDMI */
-        GPIO_FN(HDMI_HPD),
-        GPIO_FN(HDMI_CEC),
-
-        /* SYSC */
-        GPIO_FN(RESETP_PULLUP),
-        GPIO_FN(RESETP_PLAIN),
-
-        /* DEBUG */
-        GPIO_FN(EDEBGREQ_PULLDOWN),
-        GPIO_FN(EDEBGREQ_PULLUP),
-
-        GPIO_FN(TRACEAUD_FROM_VIO),
-        GPIO_FN(TRACEAUD_FROM_LCDC0),
-        GPIO_FN(TRACEAUD_FROM_MEMC),
-};
+#undef PORTCR
+#define PORTCR(nr, reg)                                                 \
+        {                                                               \
+                PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {             \
+                        _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT),     \
+                                PORT##nr##_FN0, PORT##nr##_FN1,         \
+                                PORT##nr##_FN2, PORT##nr##_FN3,         \
+                                PORT##nr##_FN4, PORT##nr##_FN5,         \
+                                PORT##nr##_FN6, PORT##nr##_FN7 }        \
+        }
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         PORTCR(0,       0xe6050000), /* PORT0CR */
@@ -2994,48 +3682,114 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
 };
 
 static const struct pinmux_irq pinmux_irqs[] = {
-        PINMUX_IRQ(irq_pin(0), GPIO_PORT2,   GPIO_PORT13),      /* IRQ0A */
-        PINMUX_IRQ(irq_pin(1), GPIO_PORT20),            /* IRQ1A */
-        PINMUX_IRQ(irq_pin(2), GPIO_PORT11,  GPIO_PORT12),      /* IRQ2A */
-        PINMUX_IRQ(irq_pin(3), GPIO_PORT10,  GPIO_PORT14),      /* IRQ3A */
-        PINMUX_IRQ(irq_pin(4), GPIO_PORT15,  GPIO_PORT172),/* IRQ4A */
-        PINMUX_IRQ(irq_pin(5), GPIO_PORT0,   GPIO_PORT1),       /* IRQ5A */
-        PINMUX_IRQ(irq_pin(6), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */
-        PINMUX_IRQ(irq_pin(7), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */
-        PINMUX_IRQ(irq_pin(8), GPIO_PORT119),           /* IRQ8A */
-        PINMUX_IRQ(irq_pin(9), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */
-        PINMUX_IRQ(irq_pin(10), GPIO_PORT19),           /* IRQ10A */
-        PINMUX_IRQ(irq_pin(11), GPIO_PORT104),          /* IRQ11A */
-        PINMUX_IRQ(irq_pin(12), GPIO_PORT42,  GPIO_PORT97),     /* IRQ12A */
-        PINMUX_IRQ(irq_pin(13), GPIO_PORT64,  GPIO_PORT98),     /* IRQ13A */
-        PINMUX_IRQ(irq_pin(14), GPIO_PORT63,  GPIO_PORT99),     /* IRQ14A */
-        PINMUX_IRQ(irq_pin(15), GPIO_PORT62,  GPIO_PORT100),/* IRQ15A */
-        PINMUX_IRQ(irq_pin(16), GPIO_PORT68,  GPIO_PORT211),/* IRQ16A */
-        PINMUX_IRQ(irq_pin(17), GPIO_PORT69),           /* IRQ17A */
-        PINMUX_IRQ(irq_pin(18), GPIO_PORT70),           /* IRQ18A */
-        PINMUX_IRQ(irq_pin(19), GPIO_PORT71),           /* IRQ19A */
-        PINMUX_IRQ(irq_pin(20), GPIO_PORT67),           /* IRQ20A */
-        PINMUX_IRQ(irq_pin(21), GPIO_PORT202),          /* IRQ21A */
-        PINMUX_IRQ(irq_pin(22), GPIO_PORT95),           /* IRQ22A */
-        PINMUX_IRQ(irq_pin(23), GPIO_PORT96),           /* IRQ23A */
-        PINMUX_IRQ(irq_pin(24), GPIO_PORT180),          /* IRQ24A */
-        PINMUX_IRQ(irq_pin(25), GPIO_PORT38),           /* IRQ25A */
-        PINMUX_IRQ(irq_pin(26), GPIO_PORT58,  GPIO_PORT81),     /* IRQ26A */
-        PINMUX_IRQ(irq_pin(27), GPIO_PORT57,  GPIO_PORT168),/* IRQ27A */
-        PINMUX_IRQ(irq_pin(28), GPIO_PORT56,  GPIO_PORT169),/* IRQ28A */
-        PINMUX_IRQ(irq_pin(29), GPIO_PORT50,  GPIO_PORT170),/* IRQ29A */
-        PINMUX_IRQ(irq_pin(30), GPIO_PORT49,  GPIO_PORT171),/* IRQ30A */
-        PINMUX_IRQ(irq_pin(31), GPIO_PORT41,  GPIO_PORT167),/* IRQ31A */
+        PINMUX_IRQ(irq_pin(0), 2,   13),        /* IRQ0A */
+        PINMUX_IRQ(irq_pin(1), 20),             /* IRQ1A */
+        PINMUX_IRQ(irq_pin(2), 11,  12),        /* IRQ2A */
+        PINMUX_IRQ(irq_pin(3), 10,  14),        /* IRQ3A */
+        PINMUX_IRQ(irq_pin(4), 15,  172),       /* IRQ4A */
+        PINMUX_IRQ(irq_pin(5), 0,   1),         /* IRQ5A */
+        PINMUX_IRQ(irq_pin(6), 121, 173),       /* IRQ6A */
+        PINMUX_IRQ(irq_pin(7), 120, 209),       /* IRQ7A */
+        PINMUX_IRQ(irq_pin(8), 119),            /* IRQ8A */
+        PINMUX_IRQ(irq_pin(9), 118, 210),       /* IRQ9A */
+        PINMUX_IRQ(irq_pin(10), 19),            /* IRQ10A */
+        PINMUX_IRQ(irq_pin(11), 104),           /* IRQ11A */
+        PINMUX_IRQ(irq_pin(12), 42,  97),       /* IRQ12A */
+        PINMUX_IRQ(irq_pin(13), 64,  98),       /* IRQ13A */
+        PINMUX_IRQ(irq_pin(14), 63,  99),       /* IRQ14A */
+        PINMUX_IRQ(irq_pin(15), 62,  100),      /* IRQ15A */
+        PINMUX_IRQ(irq_pin(16), 68,  211),      /* IRQ16A */
+        PINMUX_IRQ(irq_pin(17), 69),            /* IRQ17A */
+        PINMUX_IRQ(irq_pin(18), 70),            /* IRQ18A */
+        PINMUX_IRQ(irq_pin(19), 71),            /* IRQ19A */
+        PINMUX_IRQ(irq_pin(20), 67),            /* IRQ20A */
+        PINMUX_IRQ(irq_pin(21), 202),           /* IRQ21A */
+        PINMUX_IRQ(irq_pin(22), 95),            /* IRQ22A */
+        PINMUX_IRQ(irq_pin(23), 96),            /* IRQ23A */
+        PINMUX_IRQ(irq_pin(24), 180),           /* IRQ24A */
+        PINMUX_IRQ(irq_pin(25), 38),            /* IRQ25A */
+        PINMUX_IRQ(irq_pin(26), 58,  81),       /* IRQ26A */
+        PINMUX_IRQ(irq_pin(27), 57,  168),      /* IRQ27A */
+        PINMUX_IRQ(irq_pin(28), 56,  169),      /* IRQ28A */
+        PINMUX_IRQ(irq_pin(29), 50,  170),      /* IRQ29A */
+        PINMUX_IRQ(irq_pin(30), 49,  171),      /* IRQ30A */
+        PINMUX_IRQ(irq_pin(31), 41,  167),      /* IRQ31A */
+};
+
+#define PORTnCR_PULMD_OFF       (0 << 6)
+#define PORTnCR_PULMD_DOWN      (2 << 6)
+#define PORTnCR_PULMD_UP        (3 << 6)
+#define PORTnCR_PULMD_MASK      (3 << 6)
+
+struct r8a7740_portcr_group {
+        unsigned int end_pin;
+        unsigned int offset;
+};
+
+static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
+        { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
+};
+
+static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
+{
+        unsigned int i;
+
+        for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) {
+                const struct r8a7740_portcr_group *group =
+                        &r8a7740_portcr_offsets[i];
+
+                if (i <= group->end_pin)
+                        return pfc->window->virt + group->offset + pin;
+        }
+
+        return NULL;
+}
+
+static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
+{
+        void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
+        u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
+
+        switch (value) {
+        case PORTnCR_PULMD_UP:
+                return PIN_CONFIG_BIAS_PULL_UP;
+        case PORTnCR_PULMD_DOWN:
+                return PIN_CONFIG_BIAS_PULL_DOWN;
+        case PORTnCR_PULMD_OFF:
+        default:
+                return PIN_CONFIG_BIAS_DISABLE;
+        }
+}
+
+static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+                                   unsigned int bias)
+{
+        void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
+        u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
+
+        switch (bias) {
+        case PIN_CONFIG_BIAS_PULL_UP:
+                value |= PORTnCR_PULMD_UP;
+                break;
+        case PIN_CONFIG_BIAS_PULL_DOWN:
+                value |= PORTnCR_PULMD_DOWN;
+                break;
+        }
+
+        iowrite8(value, addr);
+}
+
+static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = {
+        .get_bias = r8a7740_pinmux_get_bias,
+        .set_bias = r8a7740_pinmux_set_bias,
 };
 
 const struct sh_pfc_soc_info r8a7740_pinmux_info = {
         .name           = "r8a7740_pfc",
+        .ops            = &r8a7740_pinmux_ops,
+
         .input          = { PINMUX_INPUT_BEGIN,
                             PINMUX_INPUT_END },
-        .input_pu       = { PINMUX_INPUT_PULLUP_BEGIN,
-                            PINMUX_INPUT_PULLUP_END },
-        .input_pd       = { PINMUX_INPUT_PULLDOWN_BEGIN,
-                            PINMUX_INPUT_PULLDOWN_END },
         .output         = { PINMUX_OUTPUT_BEGIN,
                             PINMUX_OUTPUT_END },
         .function       = { PINMUX_FUNCTION_BEGIN,
@@ -3048,9 +3802,6 @@ const struct sh_pfc_soc_info r8a7740_pinmux_info = {
         .functions      = pinmux_functions,
         .nr_functions   = ARRAY_SIZE(pinmux_functions),
 
-        .func_gpios     = pinmux_func_gpios,
-        .nr_func_gpios  = ARRAY_SIZE(pinmux_func_gpios),
-
         .cfg_regs       = pinmux_config_regs,
         .data_regs      = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
new file mode 100644
index 000000000000..1dcbabcd7b3c
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -0,0 +1,2783 @@
+/*
+ * r8a7778 processor support - PFC hardware block
+ *
+ * Copyright (C) 2013  Renesas Solutions Corp.
+ * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ * Copyright (C) 2013  Cogent Embedded, Inc.
+ *
+ * based on
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/platform_data/gpio-rcar.h>
+#include <linux/kernel.h>
+#include "sh_pfc.h"
+
+#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
+
+#define PORT_GP_32(bank, fn, sfx)                                       \
+        PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),     \
+        PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),     \
+        PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),     \
+        PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),     \
+        PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),     \
+        PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),     \
+        PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),     \
+        PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),     \
+        PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),     \
+        PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),     \
+        PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),     \
+        PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),     \
+        PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),     \
+        PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx),     \
+        PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx),     \
+        PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
+
+#define PORT_GP_27(bank, fn, sfx)                                       \
+        PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),     \
+        PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),     \
+        PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),     \
+        PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),     \
+        PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),     \
+        PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),     \
+        PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),     \
+        PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),     \
+        PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),     \
+        PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),     \
+        PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),     \
+        PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),     \
+        PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),     \
+        PORT_GP_1(bank, 26, fn, sfx)
+
+#define CPU_ALL_PORT(fn, sfx)           \
+        PORT_GP_32(0, fn, sfx),         \
+        PORT_GP_32(1, fn, sfx),         \
+        PORT_GP_32(2, fn, sfx),         \
+        PORT_GP_32(3, fn, sfx),         \
+        PORT_GP_27(4, fn, sfx)
+
+#define _GP_PORT_ALL(bank, pin, name, sfx)      name##_##sfx
+
+#define _GP_GPIO(bank, pin, _name, sfx)         \
+        [RCAR_GP_PIN(bank, pin)] = {            \
+                .name = __stringify(_name),     \
+                .enum_id = _name##_DATA,        \
+        }
+
+#define _GP_DATA(bank, pin, name, sfx)          \
+        PINMUX_DATA(name##_DATA, name##_FN)
+
+#define GP_ALL(str)             CPU_ALL_PORT(_GP_PORT_ALL, str)
+#define PINMUX_GPIO_GP_ALL()    CPU_ALL_PORT(_GP_GPIO, unused)
+#define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_GP_DATA, unused)
+
+#define PINMUX_IPSR_NOGP(ispr, fn)      PINMUX_DATA(fn##_MARK, FN_##fn)
+#define PINMUX_IPSR_DATA(ipsr, fn)      PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
+#define PINMUX_IPSR_MSEL(ipsr, fn, ms)  PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms)
+#define PINMUX_IPSR_NOGM(ispr, fn, ms)  PINMUX_DATA(fn##_MARK, FN_##fn,            FN_##ms)
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */
+        PINMUX_DATA_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */
+
+        /* GPSR0 */
+        FN_IP0_1_0,     FN_PENC0,       FN_PENC1,       FN_IP0_4_2,
+        FN_IP0_7_5,     FN_IP0_11_8,    FN_IP0_14_12,   FN_A1,
+        FN_A2,          FN_A3,          FN_IP0_15,      FN_IP0_16,
+        FN_IP0_17,      FN_IP0_18,      FN_IP0_19,      FN_IP0_20,
+        FN_IP0_21,      FN_IP0_22,      FN_IP0_23,      FN_IP0_24,
+        FN_IP0_25,      FN_IP0_26,      FN_IP0_27,      FN_IP0_28,
+        FN_IP0_29,      FN_IP0_30,      FN_IP1_0,       FN_IP1_1,
+        FN_IP1_4_2,     FN_IP1_7_5,     FN_IP1_10_8,    FN_IP1_14_11,
+
+        /* GPSR1 */
+        FN_IP1_23_21,   FN_WE0,         FN_IP1_24,      FN_IP1_27_25,
+        FN_IP1_29_28,   FN_IP2_2_0,     FN_IP2_5_3,     FN_IP2_8_6,
+        FN_IP2_11_9,    FN_IP2_13_12,   FN_IP2_16_14,   FN_IP2_17,
+        FN_IP2_30,      FN_IP2_31,      FN_IP3_1_0,     FN_IP3_4_2,
+        FN_IP3_7_5,     FN_IP3_9_8,     FN_IP3_12_10,   FN_IP3_15_13,
+        FN_IP3_18_16,   FN_IP3_20_19,   FN_IP3_23_21,   FN_IP3_26_24,
+        FN_IP3_27,      FN_IP3_28,      FN_IP3_29,      FN_IP3_30,
+        FN_IP3_31,      FN_IP4_0,       FN_IP4_3_1,     FN_IP4_6_4,
+
+        /* GPSR2 */
+        FN_IP4_7,       FN_IP4_8,       FN_IP4_10_9,    FN_IP4_12_11,
+        FN_IP4_14_13,   FN_IP4_16_15,   FN_IP4_20_17,   FN_IP4_24_21,
+        FN_IP4_26_25,   FN_IP4_28_27,   FN_IP4_30_29,   FN_IP5_1_0,
+        FN_IP5_3_2,     FN_IP5_5_4,     FN_IP5_6,       FN_IP5_7,
+        FN_IP5_9_8,     FN_IP5_11_10,   FN_IP5_12,      FN_IP5_14_13,
+        FN_IP5_17_15,   FN_IP5_20_18,   FN_AUDIO_CLKA,  FN_AUDIO_CLKB,
+        FN_IP5_22_21,   FN_IP5_25_23,   FN_IP5_28_26,   FN_IP5_30_29,
+        FN_IP6_1_0,     FN_IP6_4_2,     FN_IP6_6_5,     FN_IP6_7,
+
+        /* GPSR3 */
+        FN_IP6_8,       FN_IP6_9,       FN_SSI_SCK34,   FN_IP6_10,
+        FN_IP6_12_11,   FN_IP6_13,      FN_IP6_15_14,   FN_IP6_16,
+        FN_IP6_18_17,   FN_IP6_20_19,   FN_IP6_21,      FN_IP6_23_22,
+        FN_IP6_25_24,   FN_IP6_27_26,   FN_IP6_29_28,   FN_IP6_31_30,
+        FN_IP7_1_0,     FN_IP7_3_2,     FN_IP7_5_4,     FN_IP7_8_6,
+        FN_IP7_11_9,    FN_IP7_14_12,   FN_IP7_17_15,   FN_IP7_20_18,
+        FN_IP7_21,      FN_IP7_24_22,   FN_IP7_28_25,   FN_IP7_31_29,
+        FN_IP8_2_0,     FN_IP8_5_3,     FN_IP8_8_6,     FN_IP8_10_9,
+
+        /* GPSR4 */
+        FN_IP8_13_11,   FN_IP8_15_14,   FN_IP8_18_16,   FN_IP8_21_19,
+        FN_IP8_23_22,   FN_IP8_26_24,   FN_IP8_29_27,   FN_IP9_2_0,
+        FN_IP9_5_3,     FN_IP9_8_6,     FN_IP9_11_9,    FN_IP9_14_12,
+        FN_IP9_17_15,   FN_IP9_20_18,   FN_IP9_23_21,   FN_IP9_26_24,
+        FN_IP9_29_27,   FN_IP10_2_0,    FN_IP10_5_3,    FN_IP10_8_6,
+        FN_IP10_12_9,   FN_IP10_15_13,  FN_IP10_18_16,  FN_IP10_21_19,
+        FN_IP10_24_22,  FN_AVS1,        FN_AVS2,
+
+        /* IPSR0 */
+        FN_PRESETOUT,   FN_PWM1,        FN_AUDATA0,     FN_ARM_TRACEDATA_0,
+        FN_GPSCLK_C,    FN_USB_OVC0,    FN_TX2_E,       FN_SDA2_B,
+        FN_AUDATA1,     FN_ARM_TRACEDATA_1,             FN_GPSIN_C,
+        FN_USB_OVC1,    FN_RX2_E,       FN_SCL2_B,      FN_SD1_DAT2_A,
+        FN_MMC_D2,      FN_BS,          FN_ATADIR0_A,   FN_SDSELF_A,
+        FN_PWM4_B,      FN_SD1_DAT3_A,  FN_MMC_D3,      FN_A0,
+        FN_ATAG0_A,     FN_REMOCON_B,   FN_A4,          FN_A5,
+        FN_A6,          FN_A7,          FN_A8,          FN_A9,
+        FN_A10,         FN_A11,         FN_A12,         FN_A13,
+        FN_A14,         FN_A15,         FN_A16,         FN_A17,
+        FN_A18,         FN_A19,
+
+        /* IPSR1 */
+        FN_A20,         FN_HSPI_CS1_B,  FN_A21,         FN_HSPI_CLK1_B,
+        FN_A22,         FN_HRTS0_B,     FN_RX2_B,       FN_DREQ2_A,
+        FN_A23,         FN_HTX0_B,      FN_TX2_B,       FN_DACK2_A,
+        FN_TS_SDEN0_A,  FN_SD1_CD_A,    FN_MMC_D6,      FN_A24,
+        FN_DREQ1_A,     FN_HRX0_B,      FN_TS_SPSYNC0_A,
+        FN_SD1_WP_A,    FN_MMC_D7,      FN_A25, FN_DACK1_A,
+        FN_HCTS0_B,     FN_RX3_C,       FN_TS_SDAT0_A,  FN_CLKOUT,
+        FN_HSPI_TX1_B,  FN_PWM0_B,      FN_CS0,         FN_HSPI_RX1_B,
+        FN_SSI_SCK1_B,  FN_ATAG0_B,     FN_CS1_A26,     FN_SDA2_A,
+        FN_SCK2_B,      FN_MMC_D5,      FN_ATADIR0_B,   FN_RD_WR,
+        FN_WE1,         FN_ATAWR0_B,    FN_SSI_WS1_B,   FN_EX_CS0,
+        FN_SCL2_A,      FN_TX3_C,       FN_TS_SCK0_A,   FN_EX_CS1,
+        FN_MMC_D4,
+
+        /* IPSR2 */
+        FN_SD1_CLK_A,   FN_MMC_CLK,     FN_ATACS00,     FN_EX_CS2,
+        FN_SD1_CMD_A,   FN_MMC_CMD,     FN_ATACS10,     FN_EX_CS3,
+        FN_SD1_DAT0_A,  FN_MMC_D0,      FN_ATARD0,      FN_EX_CS4,
+        FN_EX_WAIT1_A,  FN_SD1_DAT1_A,  FN_MMC_D1,      FN_ATAWR0_A,
+        FN_EX_CS5,      FN_EX_WAIT2_A,  FN_DREQ0_A,     FN_RX3_A,
+        FN_DACK0,       FN_TX3_A,       FN_DRACK0,      FN_EX_WAIT0,
+        FN_PWM0_C,      FN_D0,          FN_D1,          FN_D2,
+        FN_D3,          FN_D4,          FN_D5,          FN_D6,
+        FN_D7,          FN_D8,          FN_D9,          FN_D10,
+        FN_D11,         FN_RD_WR_B,     FN_IRQ0,        FN_MLB_CLK,
+        FN_IRQ1_A,
+
+        /* IPSR3 */
+        FN_MLB_SIG,     FN_RX5_B,       FN_SDA3_A,      FN_IRQ2_A,
+        FN_MLB_DAT,     FN_TX5_B,       FN_SCL3_A,      FN_IRQ3_A,
+        FN_SDSELF_B,    FN_SD1_CMD_B,   FN_SCIF_CLK,    FN_AUDIO_CLKOUT_B,
+        FN_CAN_CLK_B,   FN_SDA3_B,      FN_SD1_CLK_B,   FN_HTX0_A,
+        FN_TX0_A,       FN_SD1_DAT0_B,  FN_HRX0_A,      FN_RX0_A,
+        FN_SD1_DAT1_B,  FN_HSCK0,       FN_SCK0,        FN_SCL3_B,
+        FN_SD1_DAT2_B,  FN_HCTS0_A,     FN_CTS0,        FN_SD1_DAT3_B,
+        FN_HRTS0_A,     FN_RTS0,        FN_SSI_SCK4,    FN_DU0_DR0,
+        FN_LCDOUT0,     FN_AUDATA2,     FN_ARM_TRACEDATA_2,
+        FN_SDA3_C,      FN_ADICHS1,     FN_TS_SDEN0_B,  FN_SSI_WS4,
+        FN_DU0_DR1,     FN_LCDOUT1,     FN_AUDATA3,     FN_ARM_TRACEDATA_3,
+        FN_SCL3_C,      FN_ADICHS2,     FN_TS_SPSYNC0_B,
+        FN_DU0_DR2,     FN_LCDOUT2,     FN_DU0_DR3,     FN_LCDOUT3,
+        FN_DU0_DR4,     FN_LCDOUT4,     FN_DU0_DR5,     FN_LCDOUT5,
+        FN_DU0_DR6,     FN_LCDOUT6,
+
+        /* IPSR4 */
+        FN_DU0_DR7,     FN_LCDOUT7,     FN_DU0_DG0,     FN_LCDOUT8,
+        FN_AUDATA4,     FN_ARM_TRACEDATA_4,             FN_TX1_D,
+        FN_CAN0_TX_A,   FN_ADICHS0,     FN_DU0_DG1,     FN_LCDOUT9,
+        FN_AUDATA5,     FN_ARM_TRACEDATA_5,             FN_RX1_D,
+        FN_CAN0_RX_A,   FN_ADIDATA,     FN_DU0_DG2,     FN_LCDOUT10,
+        FN_DU0_DG3,     FN_LCDOUT11,    FN_DU0_DG4,     FN_LCDOUT12,
+        FN_RX0_B,       FN_DU0_DG5,     FN_LCDOUT13,    FN_TX0_B,
+        FN_DU0_DG6,     FN_LCDOUT14,    FN_RX4_A,       FN_DU0_DG7,
+        FN_LCDOUT15,    FN_TX4_A,       FN_SSI_SCK2_B,  FN_VI0_R0_B,
+        FN_DU0_DB0,     FN_LCDOUT16,    FN_AUDATA6,     FN_ARM_TRACEDATA_6,
+        FN_GPSCLK_A,    FN_PWM0_A,      FN_ADICLK,      FN_TS_SDAT0_B,
+        FN_AUDIO_CLKC,  FN_VI0_R1_B,    FN_DU0_DB1,     FN_LCDOUT17,
+        FN_AUDATA7,     FN_ARM_TRACEDATA_7,             FN_GPSIN_A,
+        FN_ADICS_SAMP,  FN_TS_SCK0_B,   FN_VI0_R2_B,    FN_DU0_DB2,
+        FN_LCDOUT18,    FN_VI0_R3_B,    FN_DU0_DB3,     FN_LCDOUT19,
+        FN_VI0_R4_B,    FN_DU0_DB4,     FN_LCDOUT20,
+
+        /* IPSR5 */
+        FN_VI0_R5_B,    FN_DU0_DB5,     FN_LCDOUT21,    FN_VI1_DATA10_B,
+        FN_DU0_DB6,     FN_LCDOUT22,    FN_VI1_DATA11_B,
+        FN_DU0_DB7,     FN_LCDOUT23,    FN_DU0_DOTCLKIN,
+        FN_QSTVA_QVS,   FN_DU0_DOTCLKO_UT0,             FN_QCLK,
+        FN_DU0_DOTCLKO_UT1,             FN_QSTVB_QVE,   FN_AUDIO_CLKOUT_A,
+        FN_REMOCON_C,   FN_SSI_WS2_B,   FN_DU0_EXHSYNC_DU0_HSYNC,
+        FN_QSTH_QHS,    FN_DU0_EXVSYNC_DU0_VSYNC,       FN_QSTB_QHE,
+        FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,
+        FN_QCPV_QDE,    FN_FMCLK_D,     FN_SSI_SCK1_A,  FN_DU0_DISP,
+        FN_QPOLA,       FN_AUDCK,       FN_ARM_TRACECLK,
+        FN_BPFCLK_D,    FN_SSI_WS1_A,   FN_DU0_CDE,     FN_QPOLB,
+        FN_AUDSYNC,     FN_ARM_TRACECTL,                FN_FMIN_D,
+        FN_SD1_CD_B,    FN_SSI_SCK78,   FN_HSPI_RX0_B,  FN_TX1_B,
+        FN_SD1_WP_B,    FN_SSI_WS78,    FN_HSPI_CLK0_B, FN_RX1_B,
+        FN_CAN_CLK_D,   FN_SSI_SDATA8,  FN_SSI_SCK2_A,  FN_HSPI_CS0_B,
+        FN_TX2_A,       FN_CAN0_TX_B,   FN_SSI_SDATA7,  FN_HSPI_TX0_B,
+        FN_RX2_A,       FN_CAN0_RX_B,
+
+        /* IPSR6 */
+        FN_SSI_SCK6,    FN_HSPI_RX2_A,  FN_FMCLK_B,     FN_CAN1_TX_B,
+        FN_SSI_WS6,     FN_HSPI_CLK2_A, FN_BPFCLK_B,    FN_CAN1_RX_B,
+        FN_SSI_SDATA6,  FN_HSPI_TX2_A,  FN_FMIN_B,      FN_SSI_SCK5,
+        FN_RX4_C,       FN_SSI_WS5,     FN_TX4_C,       FN_SSI_SDATA5,
+        FN_RX0_D,       FN_SSI_WS34,    FN_ARM_TRACEDATA_8,
+        FN_SSI_SDATA4,  FN_SSI_WS2_A,   FN_ARM_TRACEDATA_9,
+        FN_SSI_SDATA3,  FN_ARM_TRACEDATA_10,
+        FN_SSI_SCK012,  FN_ARM_TRACEDATA_11,
+        FN_TX0_D,       FN_SSI_WS012,   FN_ARM_TRACEDATA_12,
+        FN_SSI_SDATA2,  FN_HSPI_CS2_A,  FN_ARM_TRACEDATA_13,
+        FN_SDA1_A,      FN_SSI_SDATA1,  FN_ARM_TRACEDATA_14,
+        FN_SCL1_A,      FN_SCK2_A,      FN_SSI_SDATA0,
+        FN_ARM_TRACEDATA_15,
+        FN_SD0_CLK,     FN_SUB_TDO,     FN_SD0_CMD,     FN_SUB_TRST,
+        FN_SD0_DAT0,    FN_SUB_TMS,     FN_SD0_DAT1,    FN_SUB_TCK,
+        FN_SD0_DAT2,    FN_SUB_TDI,
+
+        /* IPSR7 */
+        FN_SD0_DAT3,    FN_IRQ1_B,      FN_SD0_CD,      FN_TX5_A,
+        FN_SD0_WP,      FN_RX5_A,       FN_VI1_CLKENB,  FN_HSPI_CLK0_A,
+        FN_HTX1_A,      FN_RTS1_C,      FN_VI1_FIELD,   FN_HSPI_CS0_A,
+        FN_HRX1_A,      FN_SCK1_C,      FN_VI1_HSYNC,   FN_HSPI_RX0_A,
+        FN_HRTS1_A,     FN_FMCLK_A,     FN_RX1_C,       FN_VI1_VSYNC,
+        FN_HSPI_TX0,    FN_HCTS1_A,     FN_BPFCLK_A,    FN_TX1_C,
+        FN_TCLK0,       FN_HSCK1_A,     FN_FMIN_A,      FN_IRQ2_C,
+        FN_CTS1_C,      FN_SPEEDIN,     FN_VI0_CLK,     FN_CAN_CLK_A,
+        FN_VI0_CLKENB,  FN_SD2_DAT2_B,  FN_VI1_DATA0,   FN_DU1_DG6,
+        FN_HSPI_RX1_A,  FN_RX4_B,       FN_VI0_FIELD,   FN_SD2_DAT3_B,
+        FN_VI0_R3_C,    FN_VI1_DATA1,   FN_DU1_DG7,     FN_HSPI_CLK1_A,
+        FN_TX4_B,       FN_VI0_HSYNC,   FN_SD2_CD_B,    FN_VI1_DATA2,
+        FN_DU1_DR2,     FN_HSPI_CS1_A,  FN_RX3_B,
+
+        /* IPSR8 */
+        FN_VI0_VSYNC,   FN_SD2_WP_B,    FN_VI1_DATA3,   FN_DU1_DR3,
+        FN_HSPI_TX1_A,  FN_TX3_B,       FN_VI0_DATA0_VI0_B0,
+        FN_DU1_DG2,     FN_IRQ2_B,      FN_RX3_D,       FN_VI0_DATA1_VI0_B1,
+        FN_DU1_DG3,     FN_IRQ3_B,      FN_TX3_D,       FN_VI0_DATA2_VI0_B2,
+        FN_DU1_DG4,     FN_RX0_C,       FN_VI0_DATA3_VI0_B3,
+        FN_DU1_DG5,     FN_TX1_A,       FN_TX0_C,       FN_VI0_DATA4_VI0_B4,
+        FN_DU1_DB2,     FN_RX1_A,       FN_VI0_DATA5_VI0_B5,
+        FN_DU1_DB3,     FN_SCK1_A,      FN_PWM4,        FN_HSCK1_B,
+        FN_VI0_DATA6_VI0_G0,            FN_DU1_DB4,     FN_CTS1_A,
+        FN_PWM5,        FN_VI0_DATA7_VI0_G1,            FN_DU1_DB5,
+        FN_RTS1_A,      FN_VI0_G2,      FN_SD2_CLK_B,   FN_VI1_DATA4,
+        FN_DU1_DR4,     FN_HTX1_B,      FN_VI0_G3,      FN_SD2_CMD_B,
+        FN_VI1_DATA5,   FN_DU1_DR5,     FN_HRX1_B,
+
+        /* IPSR9 */
+        FN_VI0_G4,      FN_SD2_DAT0_B,  FN_VI1_DATA6,   FN_DU1_DR6,
+        FN_HRTS1_B,     FN_VI0_G5,      FN_SD2_DAT1_B,  FN_VI1_DATA7,
+        FN_DU1_DR7,     FN_HCTS1_B,     FN_VI0_R0_A,    FN_VI1_CLK,
+        FN_ETH_REF_CLK, FN_DU1_DOTCLKIN,                FN_VI0_R1_A,
+        FN_VI1_DATA8,   FN_DU1_DB6,     FN_ETH_TXD0,    FN_PWM2,
+        FN_TCLK1,       FN_VI0_R2_A,    FN_VI1_DATA9,   FN_DU1_DB7,
+        FN_ETH_TXD1,    FN_PWM3,        FN_VI0_R3_A,    FN_ETH_CRS_DV,
+        FN_IECLK,       FN_SCK2_C,      FN_VI0_R4_A,    FN_ETH_TX_EN,
+        FN_IETX,        FN_TX2_C,       FN_VI0_R5_A,    FN_ETH_RX_ER,
+        FN_FMCLK_C,     FN_IERX,        FN_RX2_C,       FN_VI1_DATA10_A,
+        FN_DU1_DOTCLKOUT,               FN_ETH_RXD0,    FN_BPFCLK_C,
+        FN_TX2_D,       FN_SDA2_C,      FN_VI1_DATA11_A,
+        FN_DU1_EXHSYNC_DU1_HSYNC,       FN_ETH_RXD1,    FN_FMIN_C,
+        FN_RX2_D,       FN_SCL2_C,
+
+        /* IPSR10 */
+        FN_SD2_CLK_A,   FN_DU1_EXVSYNC_DU1_VSYNC,       FN_ATARD1,
+        FN_ETH_MDC,     FN_SDA1_B,      FN_SD2_CMD_A,
+        FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,                FN_ATAWR1,
+        FN_ETH_MDIO,    FN_SCL1_B,      FN_SD2_DAT0_A,  FN_DU1_DISP,
+        FN_ATACS01,     FN_DREQ1_B,     FN_ETH_LINK,    FN_CAN1_RX_A,
+        FN_SD2_DAT1_A,  FN_DU1_CDE,     FN_ATACS11,     FN_DACK1_B,
+        FN_ETH_MAGIC,   FN_CAN1_TX_A,   FN_PWM6,        FN_SD2_DAT2_A,
+        FN_VI1_DATA12,  FN_DREQ2_B,     FN_ATADIR1,     FN_HSPI_CLK2_B,
+        FN_GPSCLK_B,    FN_SD2_DAT3_A,  FN_VI1_DATA13,  FN_DACK2_B,
+        FN_ATAG1,       FN_HSPI_CS2_B,  FN_GPSIN_B,     FN_SD2_CD_A,
+        FN_VI1_DATA14,  FN_EX_WAIT1_B,  FN_DREQ0_B,     FN_HSPI_RX2_B,
+        FN_REMOCON_A,   FN_SD2_WP_A,    FN_VI1_DATA15,  FN_EX_WAIT2_B,
+        FN_DACK0_B,     FN_HSPI_TX2_B,  FN_CAN_CLK_C,
+
+        /* SEL */
+        FN_SEL_SCIF5_A, FN_SEL_SCIF5_B,
+        FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, FN_SEL_SCIF4_C,
+        FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, FN_SEL_SCIF3_C, FN_SEL_SCIF3_D,
+        FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, FN_SEL_SCIF2_E,
+        FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, FN_SEL_SCIF1_C, FN_SEL_SCIF1_D,
+        FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, FN_SEL_SCIF0_C, FN_SEL_SCIF0_D,
+        FN_SEL_SSI2_A,  FN_SEL_SSI2_B,
+        FN_SEL_SSI1_A,  FN_SEL_SSI1_B,
+        FN_SEL_VI1_A,   FN_SEL_VI1_B,
+        FN_SEL_VI0_A,   FN_SEL_VI0_B,   FN_SEL_VI0_C,   FN_SEL_VI0_D,
+        FN_SEL_SD2_A,   FN_SEL_SD2_B,
+        FN_SEL_SD1_A,   FN_SEL_SD1_B,
+        FN_SEL_IRQ3_A,  FN_SEL_IRQ3_B,
+        FN_SEL_IRQ2_A,  FN_SEL_IRQ2_B,  FN_SEL_IRQ2_C,
+        FN_SEL_IRQ1_A,  FN_SEL_IRQ1_B,
+        FN_SEL_DREQ2_A, FN_SEL_DREQ2_B,
+        FN_SEL_DREQ1_A, FN_SEL_DREQ1_B,
+        FN_SEL_DREQ0_A, FN_SEL_DREQ0_B,
+        FN_SEL_WAIT2_A, FN_SEL_WAIT2_B,
+        FN_SEL_WAIT1_A, FN_SEL_WAIT1_B,
+        FN_SEL_CAN1_A,  FN_SEL_CAN1_B,
+        FN_SEL_CAN0_A,  FN_SEL_CAN0_B,
+        FN_SEL_CANCLK_A,        FN_SEL_CANCLK_B,
+        FN_SEL_CANCLK_C,        FN_SEL_CANCLK_D,
+        FN_SEL_HSCIF1_A,        FN_SEL_HSCIF1_B,
+        FN_SEL_HSCIF0_A,        FN_SEL_HSCIF0_B,
+        FN_SEL_REMOCON_A,       FN_SEL_REMOCON_B,       FN_SEL_REMOCON_C,
+        FN_SEL_FM_A,    FN_SEL_FM_B,    FN_SEL_FM_C,    FN_SEL_FM_D,
+        FN_SEL_GPS_A,   FN_SEL_GPS_B,   FN_SEL_GPS_C,
+        FN_SEL_TSIF0_A, FN_SEL_TSIF0_B,
+        FN_SEL_HSPI2_A, FN_SEL_HSPI2_B,
+        FN_SEL_HSPI1_A, FN_SEL_HSPI1_B,
+        FN_SEL_HSPI0_A, FN_SEL_HSPI0_B,
+        FN_SEL_I2C3_A,  FN_SEL_I2C3_B,  FN_SEL_I2C3_C,
+        FN_SEL_I2C2_A,  FN_SEL_I2C2_B,  FN_SEL_I2C2_C,
+        FN_SEL_I2C1_A,  FN_SEL_I2C1_B,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+
+        /* GPSR0 */
+        PENC0_MARK,     PENC1_MARK,     A1_MARK,        A2_MARK,        A3_MARK,
+
+        /* GPSR1 */
+        WE0_MARK,
+
+        /* GPSR2 */
+        AUDIO_CLKA_MARK,
+        AUDIO_CLKB_MARK,
+
+        /* GPSR3 */
+        SSI_SCK34_MARK,
+
+        /* GPSR4 */
+        AVS1_MARK,
+        AVS2_MARK,
+
+        VI0_R0_C_MARK,          /* see sel_vi0 */
+        VI0_R1_C_MARK,          /* see sel_vi0 */
+        VI0_R2_C_MARK,          /* see sel_vi0 */
+        /* VI0_R3_C_MARK, */
+        VI0_R4_C_MARK,          /* see sel_vi0 */
+        VI0_R5_C_MARK,          /* see sel_vi0 */
+
+        VI0_R0_D_MARK,          /* see sel_vi0 */
+        VI0_R1_D_MARK,          /* see sel_vi0 */
+        VI0_R2_D_MARK,          /* see sel_vi0 */
+        VI0_R3_D_MARK,          /* see sel_vi0 */
+        VI0_R4_D_MARK,          /* see sel_vi0 */
+        VI0_R5_D_MARK,          /* see sel_vi0 */
+
+        /* IPSR0 */
+        PRESETOUT_MARK, PWM1_MARK,      AUDATA0_MARK,
+        ARM_TRACEDATA_0_MARK,           GPSCLK_C_MARK,  USB_OVC0_MARK,
+        TX2_E_MARK,     SDA2_B_MARK,    AUDATA1_MARK,   ARM_TRACEDATA_1_MARK,
+        GPSIN_C_MARK,   USB_OVC1_MARK,  RX2_E_MARK,     SCL2_B_MARK,
+        SD1_DAT2_A_MARK,                MMC_D2_MARK,    BS_MARK,
+        ATADIR0_A_MARK, SDSELF_A_MARK,  PWM4_B_MARK,    SD1_DAT3_A_MARK,
+        MMC_D3_MARK,    A0_MARK,        ATAG0_A_MARK,   REMOCON_B_MARK,
+        A4_MARK,        A5_MARK,        A6_MARK,        A7_MARK,
+        A8_MARK,        A9_MARK,        A10_MARK,       A11_MARK,
+        A12_MARK,       A13_MARK,       A14_MARK,       A15_MARK,
+        A16_MARK,       A17_MARK,       A18_MARK,       A19_MARK,
+
+        /* IPSR1 */
+        A20_MARK,       HSPI_CS1_B_MARK,                A21_MARK,
+        HSPI_CLK1_B_MARK,               A22_MARK,       HRTS0_B_MARK,
+        RX2_B_MARK,     DREQ2_A_MARK,   A23_MARK,       HTX0_B_MARK,
+        TX2_B_MARK,     DACK2_A_MARK,   TS_SDEN0_A_MARK,
+        SD1_CD_A_MARK,  MMC_D6_MARK,    A24_MARK,       DREQ1_A_MARK,
+        HRX0_B_MARK,    TS_SPSYNC0_A_MARK,              SD1_WP_A_MARK,
+        MMC_D7_MARK,    A25_MARK,       DACK1_A_MARK,   HCTS0_B_MARK,
+        RX3_C_MARK,     TS_SDAT0_A_MARK,                CLKOUT_MARK,
+        HSPI_TX1_B_MARK,                PWM0_B_MARK,    CS0_MARK,
+        HSPI_RX1_B_MARK,                SSI_SCK1_B_MARK,
+        ATAG0_B_MARK,   CS1_A26_MARK,   SDA2_A_MARK,    SCK2_B_MARK,
+        MMC_D5_MARK,    ATADIR0_B_MARK, RD_WR_MARK,     WE1_MARK,
+        ATAWR0_B_MARK,  SSI_WS1_B_MARK, EX_CS0_MARK,    SCL2_A_MARK,
+        TX3_C_MARK,     TS_SCK0_A_MARK, EX_CS1_MARK,    MMC_D4_MARK,
+
+        /* IPSR2 */
+        SD1_CLK_A_MARK, MMC_CLK_MARK,   ATACS00_MARK,   EX_CS2_MARK,
+        SD1_CMD_A_MARK, MMC_CMD_MARK,   ATACS10_MARK,   EX_CS3_MARK,
+        SD1_DAT0_A_MARK,                MMC_D0_MARK,    ATARD0_MARK,
+        EX_CS4_MARK,    EX_WAIT1_A_MARK,                SD1_DAT1_A_MARK,
+        MMC_D1_MARK,    ATAWR0_A_MARK,  EX_CS5_MARK,    EX_WAIT2_A_MARK,
+        DREQ0_A_MARK,   RX3_A_MARK,     DACK0_MARK,     TX3_A_MARK,
+        DRACK0_MARK,    EX_WAIT0_MARK,  PWM0_C_MARK,    D0_MARK,
+        D1_MARK,        D2_MARK,        D3_MARK,        D4_MARK,
+        D5_MARK,        D6_MARK,        D7_MARK,        D8_MARK,
+        D9_MARK,        D10_MARK,       D11_MARK,       RD_WR_B_MARK,
+        IRQ0_MARK,      MLB_CLK_MARK,   IRQ1_A_MARK,
+
+        /* IPSR3 */
+        MLB_SIG_MARK,   RX5_B_MARK,     SDA3_A_MARK,    IRQ2_A_MARK,
+        MLB_DAT_MARK,   TX5_B_MARK,     SCL3_A_MARK,    IRQ3_A_MARK,
+        SDSELF_B_MARK,  SD1_CMD_B_MARK, SCIF_CLK_MARK,  AUDIO_CLKOUT_B_MARK,
+        CAN_CLK_B_MARK, SDA3_B_MARK,    SD1_CLK_B_MARK, HTX0_A_MARK,
+        TX0_A_MARK,     SD1_DAT0_B_MARK,                HRX0_A_MARK,
+        RX0_A_MARK,     SD1_DAT1_B_MARK,                HSCK0_MARK,
+        SCK0_MARK,      SCL3_B_MARK,    SD1_DAT2_B_MARK,
+        HCTS0_A_MARK,   CTS0_MARK,      SD1_DAT3_B_MARK,
+        HRTS0_A_MARK,   RTS0_MARK,      SSI_SCK4_MARK,
+        DU0_DR0_MARK,   LCDOUT0_MARK,   AUDATA2_MARK,   ARM_TRACEDATA_2_MARK,
+        SDA3_C_MARK,    ADICHS1_MARK,   TS_SDEN0_B_MARK,
+        SSI_WS4_MARK,   DU0_DR1_MARK,   LCDOUT1_MARK,   AUDATA3_MARK,
+        ARM_TRACEDATA_3_MARK,           SCL3_C_MARK,    ADICHS2_MARK,
+        TS_SPSYNC0_B_MARK,              DU0_DR2_MARK,   LCDOUT2_MARK,
+        DU0_DR3_MARK,   LCDOUT3_MARK,   DU0_DR4_MARK,   LCDOUT4_MARK,
+        DU0_DR5_MARK,   LCDOUT5_MARK,   DU0_DR6_MARK,   LCDOUT6_MARK,
+
+        /* IPSR4 */
+        DU0_DR7_MARK,   LCDOUT7_MARK,   DU0_DG0_MARK,   LCDOUT8_MARK,
+        AUDATA4_MARK,   ARM_TRACEDATA_4_MARK,
+        TX1_D_MARK,     CAN0_TX_A_MARK, ADICHS0_MARK,   DU0_DG1_MARK,
+        LCDOUT9_MARK,   AUDATA5_MARK,   ARM_TRACEDATA_5_MARK,
+        RX1_D_MARK,     CAN0_RX_A_MARK, ADIDATA_MARK,   DU0_DG2_MARK,
+        LCDOUT10_MARK,  DU0_DG3_MARK,   LCDOUT11_MARK,  DU0_DG4_MARK,
+        LCDOUT12_MARK,  RX0_B_MARK,     DU0_DG5_MARK,   LCDOUT13_MARK,
+        TX0_B_MARK,     DU0_DG6_MARK,   LCDOUT14_MARK,  RX4_A_MARK,
+        DU0_DG7_MARK,   LCDOUT15_MARK,  TX4_A_MARK,     SSI_SCK2_B_MARK,
+        VI0_R0_B_MARK,  DU0_DB0_MARK,   LCDOUT16_MARK,  AUDATA6_MARK,
+        ARM_TRACEDATA_6_MARK,           GPSCLK_A_MARK,  PWM0_A_MARK,
+        ADICLK_MARK,    TS_SDAT0_B_MARK,                AUDIO_CLKC_MARK,
+        VI0_R1_B_MARK,  DU0_DB1_MARK,   LCDOUT17_MARK,  AUDATA7_MARK,
+        ARM_TRACEDATA_7_MARK,           GPSIN_A_MARK,   ADICS_SAMP_MARK,
+        TS_SCK0_B_MARK, VI0_R2_B_MARK,  DU0_DB2_MARK,   LCDOUT18_MARK,
+        VI0_R3_B_MARK,  DU0_DB3_MARK,   LCDOUT19_MARK,  VI0_R4_B_MARK,
+        DU0_DB4_MARK,   LCDOUT20_MARK,
+
+        /* IPSR5 */
+        VI0_R5_B_MARK,  DU0_DB5_MARK,   LCDOUT21_MARK,  VI1_DATA10_B_MARK,
+        DU0_DB6_MARK,   LCDOUT22_MARK,  VI1_DATA11_B_MARK,
+        DU0_DB7_MARK,   LCDOUT23_MARK,  DU0_DOTCLKIN_MARK,
+        QSTVA_QVS_MARK, DU0_DOTCLKO_UT0_MARK,
+        QCLK_MARK,      DU0_DOTCLKO_UT1_MARK,           QSTVB_QVE_MARK,
+        AUDIO_CLKOUT_A_MARK,            REMOCON_C_MARK, SSI_WS2_B_MARK,
+        DU0_EXHSYNC_DU0_HSYNC_MARK,     QSTH_QHS_MARK,
+        DU0_EXVSYNC_DU0_VSYNC_MARK,     QSTB_QHE_MARK,
+        DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
+        QCPV_QDE_MARK,  FMCLK_D_MARK,   SSI_SCK1_A_MARK,
+        DU0_DISP_MARK,  QPOLA_MARK,     AUDCK_MARK,     ARM_TRACECLK_MARK,
+        BPFCLK_D_MARK,  SSI_WS1_A_MARK, DU0_CDE_MARK,   QPOLB_MARK,
+        AUDSYNC_MARK,   ARM_TRACECTL_MARK,              FMIN_D_MARK,
+        SD1_CD_B_MARK,  SSI_SCK78_MARK, HSPI_RX0_B_MARK,
+        TX1_B_MARK,     SD1_WP_B_MARK,  SSI_WS78_MARK,  HSPI_CLK0_B_MARK,
+        RX1_B_MARK,     CAN_CLK_D_MARK, SSI_SDATA8_MARK,
+        SSI_SCK2_A_MARK,                HSPI_CS0_B_MARK,
+        TX2_A_MARK,     CAN0_TX_B_MARK, SSI_SDATA7_MARK,
+        HSPI_TX0_B_MARK,                RX2_A_MARK,     CAN0_RX_B_MARK,
+
+        /* IPSR6 */
+        SSI_SCK6_MARK,  HSPI_RX2_A_MARK,                FMCLK_B_MARK,
+        CAN1_TX_B_MARK, SSI_WS6_MARK,   HSPI_CLK2_A_MARK,
+        BPFCLK_B_MARK,  CAN1_RX_B_MARK, SSI_SDATA6_MARK,
+        HSPI_TX2_A_MARK,                FMIN_B_MARK,    SSI_SCK5_MARK,
+        RX4_C_MARK,     SSI_WS5_MARK,   TX4_C_MARK,     SSI_SDATA5_MARK,
+        RX0_D_MARK,     SSI_WS34_MARK,  ARM_TRACEDATA_8_MARK,
+        SSI_SDATA4_MARK,                SSI_WS2_A_MARK, ARM_TRACEDATA_9_MARK,
+        SSI_SDATA3_MARK,                ARM_TRACEDATA_10_MARK,
+        SSI_SCK012_MARK,                ARM_TRACEDATA_11_MARK,
+        TX0_D_MARK,     SSI_WS012_MARK, ARM_TRACEDATA_12_MARK,
+        SSI_SDATA2_MARK,                HSPI_CS2_A_MARK,
+        ARM_TRACEDATA_13_MARK,          SDA1_A_MARK,    SSI_SDATA1_MARK,
+        ARM_TRACEDATA_14_MARK,          SCL1_A_MARK,    SCK2_A_MARK,
+        SSI_SDATA0_MARK,                ARM_TRACEDATA_15_MARK,
+        SD0_CLK_MARK,   SUB_TDO_MARK,   SD0_CMD_MARK,   SUB_TRST_MARK,
+        SD0_DAT0_MARK,  SUB_TMS_MARK,   SD0_DAT1_MARK,  SUB_TCK_MARK,
+        SD0_DAT2_MARK,  SUB_TDI_MARK,
+
+        /* IPSR7 */
+        SD0_DAT3_MARK,  IRQ1_B_MARK,    SD0_CD_MARK,    TX5_A_MARK,
+        SD0_WP_MARK,    RX5_A_MARK,     VI1_CLKENB_MARK,
+        HSPI_CLK0_A_MARK,       HTX1_A_MARK,    RTS1_C_MARK,    VI1_FIELD_MARK,
+        HSPI_CS0_A_MARK,        HRX1_A_MARK,    SCK1_C_MARK,    VI1_HSYNC_MARK,
+        HSPI_RX0_A_MARK,        HRTS1_A_MARK,   FMCLK_A_MARK,   RX1_C_MARK,
+        VI1_VSYNC_MARK, HSPI_TX0_MARK,  HCTS1_A_MARK,   BPFCLK_A_MARK,
+        TX1_C_MARK,     TCLK0_MARK,     HSCK1_A_MARK,   FMIN_A_MARK,
+        IRQ2_C_MARK,    CTS1_C_MARK,    SPEEDIN_MARK,   VI0_CLK_MARK,
+        CAN_CLK_A_MARK, VI0_CLKENB_MARK,                SD2_DAT2_B_MARK,
+        VI1_DATA0_MARK, DU1_DG6_MARK,   HSPI_RX1_A_MARK,
+        RX4_B_MARK,     VI0_FIELD_MARK, SD2_DAT3_B_MARK,
+        VI0_R3_C_MARK,  VI1_DATA1_MARK, DU1_DG7_MARK,   HSPI_CLK1_A_MARK,
+        TX4_B_MARK,     VI0_HSYNC_MARK, SD2_CD_B_MARK,  VI1_DATA2_MARK,
+        DU1_DR2_MARK,   HSPI_CS1_A_MARK,                RX3_B_MARK,
+
+        /* IPSR8 */
+        VI0_VSYNC_MARK, SD2_WP_B_MARK,  VI1_DATA3_MARK, DU1_DR3_MARK,
+        HSPI_TX1_A_MARK,                TX3_B_MARK,     VI0_DATA0_VI0_B0_MARK,
+        DU1_DG2_MARK,   IRQ2_B_MARK,    RX3_D_MARK,     VI0_DATA1_VI0_B1_MARK,
+        DU1_DG3_MARK,   IRQ3_B_MARK,    TX3_D_MARK,     VI0_DATA2_VI0_B2_MARK,
+        DU1_DG4_MARK,   RX0_C_MARK,     VI0_DATA3_VI0_B3_MARK,
+        DU1_DG5_MARK,   TX1_A_MARK,     TX0_C_MARK,     VI0_DATA4_VI0_B4_MARK,
+        DU1_DB2_MARK,   RX1_A_MARK,     VI0_DATA5_VI0_B5_MARK,
+        DU1_DB3_MARK,   SCK1_A_MARK,    PWM4_MARK,      HSCK1_B_MARK,
+        VI0_DATA6_VI0_G0_MARK,          DU1_DB4_MARK,   CTS1_A_MARK,
+        PWM5_MARK,      VI0_DATA7_VI0_G1_MARK,          DU1_DB5_MARK,
+        RTS1_A_MARK,    VI0_G2_MARK,    SD2_CLK_B_MARK, VI1_DATA4_MARK,
+        DU1_DR4_MARK,   HTX1_B_MARK,    VI0_G3_MARK,    SD2_CMD_B_MARK,
+        VI1_DATA5_MARK, DU1_DR5_MARK,   HRX1_B_MARK,
+
+        /* IPSR9 */
+        VI0_G4_MARK,    SD2_DAT0_B_MARK,                VI1_DATA6_MARK,
+        DU1_DR6_MARK,   HRTS1_B_MARK,   VI0_G5_MARK,    SD2_DAT1_B_MARK,
+        VI1_DATA7_MARK, DU1_DR7_MARK,   HCTS1_B_MARK,   VI0_R0_A_MARK,
+        VI1_CLK_MARK,   ETH_REF_CLK_MARK,               DU1_DOTCLKIN_MARK,
+        VI0_R1_A_MARK,  VI1_DATA8_MARK, DU1_DB6_MARK,   ETH_TXD0_MARK,
+        PWM2_MARK,      TCLK1_MARK,     VI0_R2_A_MARK,  VI1_DATA9_MARK,
+        DU1_DB7_MARK,   ETH_TXD1_MARK,  PWM3_MARK,      VI0_R3_A_MARK,
+        ETH_CRS_DV_MARK,                IECLK_MARK,     SCK2_C_MARK,
+        VI0_R4_A_MARK,                  ETH_TX_EN_MARK, IETX_MARK,
+        TX2_C_MARK,     VI0_R5_A_MARK,  ETH_RX_ER_MARK, FMCLK_C_MARK,
+        IERX_MARK,      RX2_C_MARK,     VI1_DATA10_A_MARK,
+        DU1_DOTCLKOUT_MARK,             ETH_RXD0_MARK,
+        BPFCLK_C_MARK,  TX2_D_MARK,     SDA2_C_MARK,    VI1_DATA11_A_MARK,
+        DU1_EXHSYNC_DU1_HSYNC_MARK,     ETH_RXD1_MARK,  FMIN_C_MARK,
+        RX2_D_MARK,     SCL2_C_MARK,
+
+        /* IPSR10 */
+        SD2_CLK_A_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK,     ATARD1_MARK,
+        ETH_MDC_MARK,   SDA1_B_MARK,    SD2_CMD_A_MARK,
+        DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,              ATAWR1_MARK,
+        ETH_MDIO_MARK,  SCL1_B_MARK,    SD2_DAT0_A_MARK,
+        DU1_DISP_MARK,  ATACS01_MARK,   DREQ1_B_MARK,   ETH_LINK_MARK,
+        CAN1_RX_A_MARK, SD2_DAT1_A_MARK,                DU1_CDE_MARK,
+        ATACS11_MARK,   DACK1_B_MARK,   ETH_MAGIC_MARK, CAN1_TX_A_MARK,
+        PWM6_MARK,      SD2_DAT2_A_MARK,                VI1_DATA12_MARK,
+        DREQ2_B_MARK,   ATADIR1_MARK,   HSPI_CLK2_B_MARK,
+        GPSCLK_B_MARK,  SD2_DAT3_A_MARK,                VI1_DATA13_MARK,
+        DACK2_B_MARK,   ATAG1_MARK,     HSPI_CS2_B_MARK,
+        GPSIN_B_MARK,   SD2_CD_A_MARK,  VI1_DATA14_MARK,
+        EX_WAIT1_B_MARK,                DREQ0_B_MARK,   HSPI_RX2_B_MARK,
+        REMOCON_A_MARK, SD2_WP_A_MARK,  VI1_DATA15_MARK,
+        EX_WAIT2_B_MARK,                DACK0_B_MARK,
+        HSPI_TX2_B_MARK,                CAN_CLK_C_MARK,
+
+        PINMUX_MARK_END,
+};
+
+static const pinmux_enum_t pinmux_data[] = {
+        PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+        PINMUX_DATA(PENC0_MARK,         FN_PENC0),
+        PINMUX_DATA(PENC1_MARK,         FN_PENC1),
+        PINMUX_DATA(A1_MARK,            FN_A1),
+        PINMUX_DATA(A2_MARK,            FN_A2),
+        PINMUX_DATA(A3_MARK,            FN_A3),
+        PINMUX_DATA(WE0_MARK,           FN_WE0),
+        PINMUX_DATA(AUDIO_CLKA_MARK,    FN_AUDIO_CLKA),
+        PINMUX_DATA(AUDIO_CLKB_MARK,    FN_AUDIO_CLKB),
+        PINMUX_DATA(SSI_SCK34_MARK,     FN_SSI_SCK34),
+        PINMUX_DATA(AVS1_MARK,          FN_AVS1),
+        PINMUX_DATA(AVS2_MARK,          FN_AVS2),
+
+        /* IPSR0 */
+        PINMUX_IPSR_DATA(IP0_1_0,       PRESETOUT),
+        PINMUX_IPSR_DATA(IP0_1_0,       PWM1),
+
+        PINMUX_IPSR_DATA(IP0_4_2,       AUDATA0),
+        PINMUX_IPSR_DATA(IP0_4_2,       ARM_TRACEDATA_0),
+        PINMUX_IPSR_MSEL(IP0_4_2,       GPSCLK_C,       SEL_GPS_C),
+        PINMUX_IPSR_DATA(IP0_4_2,       USB_OVC0),
+        PINMUX_IPSR_DATA(IP0_4_2,       TX2_E),
+        PINMUX_IPSR_MSEL(IP0_4_2,       SDA2_B,         SEL_I2C2_B),
+
+        PINMUX_IPSR_DATA(IP0_7_5,       AUDATA1),
+        PINMUX_IPSR_DATA(IP0_7_5,       ARM_TRACEDATA_1),
+        PINMUX_IPSR_MSEL(IP0_7_5,       GPSIN_C,        SEL_GPS_C),
+        PINMUX_IPSR_DATA(IP0_7_5,       USB_OVC1),
+        PINMUX_IPSR_MSEL(IP0_7_5,       RX2_E,          SEL_SCIF2_E),
+        PINMUX_IPSR_MSEL(IP0_7_5,       SCL2_B,         SEL_I2C2_B),
+
+        PINMUX_IPSR_MSEL(IP0_11_8,      SD1_DAT2_A,     SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP0_11_8,      MMC_D2),
+        PINMUX_IPSR_DATA(IP0_11_8,      BS),
+        PINMUX_IPSR_DATA(IP0_11_8,      ATADIR0_A),
+        PINMUX_IPSR_DATA(IP0_11_8,      SDSELF_A),
+        PINMUX_IPSR_DATA(IP0_11_8,      PWM4_B),
+
+        PINMUX_IPSR_MSEL(IP0_14_12,     SD1_DAT3_A,     SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP0_14_12,     MMC_D3),
+        PINMUX_IPSR_DATA(IP0_14_12,     A0),
+        PINMUX_IPSR_DATA(IP0_14_12,     ATAG0_A),
+        PINMUX_IPSR_MSEL(IP0_14_12,     REMOCON_B,      SEL_REMOCON_B),
+
+        PINMUX_IPSR_DATA(IP0_15,        A4),
+        PINMUX_IPSR_DATA(IP0_16,        A5),
+        PINMUX_IPSR_DATA(IP0_17,        A6),
+        PINMUX_IPSR_DATA(IP0_18,        A7),
+        PINMUX_IPSR_DATA(IP0_19,        A8),
+        PINMUX_IPSR_DATA(IP0_20,        A9),
+        PINMUX_IPSR_DATA(IP0_21,        A10),
+        PINMUX_IPSR_DATA(IP0_22,        A11),
+        PINMUX_IPSR_DATA(IP0_23,        A12),
+        PINMUX_IPSR_DATA(IP0_24,        A13),
+        PINMUX_IPSR_DATA(IP0_25,        A14),
+        PINMUX_IPSR_DATA(IP0_26,        A15),
+        PINMUX_IPSR_DATA(IP0_27,        A16),
+        PINMUX_IPSR_DATA(IP0_28,        A17),
+        PINMUX_IPSR_DATA(IP0_29,        A18),
+        PINMUX_IPSR_DATA(IP0_30,        A19),
+
+        /* IPSR1 */
+        PINMUX_IPSR_DATA(IP1_0,         A20),
+        PINMUX_IPSR_MSEL(IP1_0,         HSPI_CS1_B,     SEL_HSPI1_B),
+
+        PINMUX_IPSR_DATA(IP1_1,         A21),
+        PINMUX_IPSR_MSEL(IP1_1,         HSPI_CLK1_B,    SEL_HSPI1_B),
+
+        PINMUX_IPSR_DATA(IP1_4_2,       A22),
+        PINMUX_IPSR_MSEL(IP1_4_2,       HRTS0_B,        SEL_HSCIF0_B),
+        PINMUX_IPSR_MSEL(IP1_4_2,       RX2_B,          SEL_SCIF2_B),
+        PINMUX_IPSR_MSEL(IP1_4_2,       DREQ2_A,        SEL_DREQ2_A),
+
+        PINMUX_IPSR_DATA(IP1_7_5,       A23),
+        PINMUX_IPSR_DATA(IP1_7_5,       HTX0_B),
+        PINMUX_IPSR_DATA(IP1_7_5,       TX2_B),
+        PINMUX_IPSR_DATA(IP1_7_5,       DACK2_A),
+        PINMUX_IPSR_MSEL(IP1_7_5,       TS_SDEN0_A,     SEL_TSIF0_A),
+
+        PINMUX_IPSR_MSEL(IP1_10_8,      SD1_CD_A,       SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP1_10_8,      MMC_D6),
+        PINMUX_IPSR_DATA(IP1_10_8,      A24),
+        PINMUX_IPSR_MSEL(IP1_10_8,      DREQ1_A,        SEL_DREQ1_A),
+        PINMUX_IPSR_MSEL(IP1_10_8,      HRX0_B,         SEL_HSCIF0_B),
+        PINMUX_IPSR_MSEL(IP1_10_8,      TS_SPSYNC0_A,   SEL_TSIF0_A),
+
+        PINMUX_IPSR_MSEL(IP1_14_11,     SD1_WP_A,       SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP1_14_11,     MMC_D7),
+        PINMUX_IPSR_DATA(IP1_14_11,     A25),
+        PINMUX_IPSR_DATA(IP1_14_11,     DACK1_A),
+        PINMUX_IPSR_MSEL(IP1_14_11,     HCTS0_B,        SEL_HSCIF0_B),
+        PINMUX_IPSR_MSEL(IP1_14_11,     RX3_C,          SEL_SCIF3_C),
+        PINMUX_IPSR_MSEL(IP1_14_11,     TS_SDAT0_A,     SEL_TSIF0_A),
+
+        PINMUX_IPSR_NOGP(IP1_16_15,     CLKOUT),
+        PINMUX_IPSR_NOGP(IP1_16_15,     HSPI_TX1_B),
+        PINMUX_IPSR_NOGP(IP1_16_15,     PWM0_B),
+
+        PINMUX_IPSR_NOGP(IP1_17,        CS0),
+        PINMUX_IPSR_NOGM(IP1_17,        HSPI_RX1_B,     SEL_HSPI1_B),
+
+        PINMUX_IPSR_NOGM(IP1_20_18,     SSI_SCK1_B,     SEL_SSI1_B),
+        PINMUX_IPSR_NOGP(IP1_20_18,     ATAG0_B),
+        PINMUX_IPSR_NOGP(IP1_20_18,     CS1_A26),
+        PINMUX_IPSR_NOGM(IP1_20_18,     SDA2_A,         SEL_I2C2_A),
+        PINMUX_IPSR_NOGM(IP1_20_18,     SCK2_B,         SEL_SCIF2_B),
+
+        PINMUX_IPSR_DATA(IP1_23_21,     MMC_D5),
+        PINMUX_IPSR_DATA(IP1_23_21,     ATADIR0_B),
+        PINMUX_IPSR_DATA(IP1_23_21,     RD_WR),
+
+        PINMUX_IPSR_DATA(IP1_24,        WE1),
+        PINMUX_IPSR_DATA(IP1_24,        ATAWR0_B),
+
+        PINMUX_IPSR_MSEL(IP1_27_25,     SSI_WS1_B,      SEL_SSI1_B),
+        PINMUX_IPSR_DATA(IP1_27_25,     EX_CS0),
+        PINMUX_IPSR_MSEL(IP1_27_25,     SCL2_A,         SEL_I2C2_A),
+        PINMUX_IPSR_DATA(IP1_27_25,     TX3_C),
+        PINMUX_IPSR_MSEL(IP1_27_25,     TS_SCK0_A,      SEL_TSIF0_A),
+
+        PINMUX_IPSR_DATA(IP1_29_28,     EX_CS1),
+        PINMUX_IPSR_DATA(IP1_29_28,     MMC_D4),
+
+        /* IPSR2 */
+        PINMUX_IPSR_DATA(IP2_2_0,       SD1_CLK_A),
+        PINMUX_IPSR_DATA(IP2_2_0,       MMC_CLK),
+        PINMUX_IPSR_DATA(IP2_2_0,       ATACS00),
+        PINMUX_IPSR_DATA(IP2_2_0,       EX_CS2),
+
+        PINMUX_IPSR_MSEL(IP2_5_3,       SD1_CMD_A,      SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP2_5_3,       MMC_CMD),
+        PINMUX_IPSR_DATA(IP2_5_3,       ATACS10),
+        PINMUX_IPSR_DATA(IP2_5_3,       EX_CS3),
+
+        PINMUX_IPSR_MSEL(IP2_8_6,       SD1_DAT0_A,     SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP2_8_6,       MMC_D0),
+        PINMUX_IPSR_DATA(IP2_8_6,       ATARD0),
+        PINMUX_IPSR_DATA(IP2_8_6,       EX_CS4),
+        PINMUX_IPSR_MSEL(IP2_8_6,       EX_WAIT1_A,     SEL_WAIT1_A),
+
+        PINMUX_IPSR_MSEL(IP2_11_9,      SD1_DAT1_A,     SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP2_11_9,      MMC_D1),
+        PINMUX_IPSR_DATA(IP2_11_9,      ATAWR0_A),
+        PINMUX_IPSR_DATA(IP2_11_9,      EX_CS5),
+        PINMUX_IPSR_MSEL(IP2_11_9,      EX_WAIT2_A,     SEL_WAIT2_A),
+
+        PINMUX_IPSR_MSEL(IP2_13_12,     DREQ0_A,        SEL_DREQ0_A),
+        PINMUX_IPSR_MSEL(IP2_13_12,     RX3_A,          SEL_SCIF3_A),
+
+        PINMUX_IPSR_DATA(IP2_16_14,     DACK0),
+        PINMUX_IPSR_DATA(IP2_16_14,     TX3_A),
+        PINMUX_IPSR_DATA(IP2_16_14,     DRACK0),
+
+        PINMUX_IPSR_DATA(IP2_17,        EX_WAIT0),
+        PINMUX_IPSR_DATA(IP2_17,        PWM0_C),
+
+        PINMUX_IPSR_NOGP(IP2_18,        D0),
+        PINMUX_IPSR_NOGP(IP2_19,        D1),
+        PINMUX_IPSR_NOGP(IP2_20,        D2),
+        PINMUX_IPSR_NOGP(IP2_21,        D3),
+        PINMUX_IPSR_NOGP(IP2_22,        D4),
+        PINMUX_IPSR_NOGP(IP2_23,        D5),
+        PINMUX_IPSR_NOGP(IP2_24,        D6),
+        PINMUX_IPSR_NOGP(IP2_25,        D7),
+        PINMUX_IPSR_NOGP(IP2_26,        D8),
+        PINMUX_IPSR_NOGP(IP2_27,        D9),
+        PINMUX_IPSR_NOGP(IP2_28,        D10),
+        PINMUX_IPSR_NOGP(IP2_29,        D11),
+
+        PINMUX_IPSR_DATA(IP2_30,        RD_WR_B),
+        PINMUX_IPSR_DATA(IP2_30,        IRQ0),
+
+        PINMUX_IPSR_DATA(IP2_31,        MLB_CLK),
+        PINMUX_IPSR_MSEL(IP2_31,        IRQ1_A,         SEL_IRQ1_A),
+
+        /* IPSR3 */
+        PINMUX_IPSR_DATA(IP3_1_0,       MLB_SIG),
+        PINMUX_IPSR_MSEL(IP3_1_0,       RX5_B,          SEL_SCIF5_B),
+        PINMUX_IPSR_MSEL(IP3_1_0,       SDA3_A,         SEL_I2C3_A),
+        PINMUX_IPSR_MSEL(IP3_1_0,       IRQ2_A,         SEL_IRQ2_A),
+
+        PINMUX_IPSR_DATA(IP3_4_2,       MLB_DAT),
+        PINMUX_IPSR_DATA(IP3_4_2,       TX5_B),
+        PINMUX_IPSR_MSEL(IP3_4_2,       SCL3_A,         SEL_I2C3_A),
+        PINMUX_IPSR_MSEL(IP3_4_2,       IRQ3_A,         SEL_IRQ3_A),
+        PINMUX_IPSR_DATA(IP3_4_2,       SDSELF_B),
+
+        PINMUX_IPSR_MSEL(IP3_7_5,       SD1_CMD_B,      SEL_SD1_B),
+        PINMUX_IPSR_DATA(IP3_7_5,       SCIF_CLK),
+        PINMUX_IPSR_DATA(IP3_7_5,       AUDIO_CLKOUT_B),
+        PINMUX_IPSR_MSEL(IP3_7_5,       CAN_CLK_B,      SEL_CANCLK_B),
+        PINMUX_IPSR_MSEL(IP3_7_5,       SDA3_B,         SEL_I2C3_B),
+
+        PINMUX_IPSR_DATA(IP3_9_8,       SD1_CLK_B),
+        PINMUX_IPSR_DATA(IP3_9_8,       HTX0_A),
+        PINMUX_IPSR_DATA(IP3_9_8,       TX0_A),
+
+        PINMUX_IPSR_MSEL(IP3_12_10,     SD1_DAT0_B,     SEL_SD1_B),
+        PINMUX_IPSR_MSEL(IP3_12_10,     HRX0_A,         SEL_HSCIF0_A),
+        PINMUX_IPSR_MSEL(IP3_12_10,     RX0_A,          SEL_SCIF0_A),
+
+        PINMUX_IPSR_MSEL(IP3_15_13,     SD1_DAT1_B,     SEL_SD1_B),
+        PINMUX_IPSR_MSEL(IP3_15_13,     HSCK0,          SEL_HSCIF0_A),
+        PINMUX_IPSR_DATA(IP3_15_13,     SCK0),
+        PINMUX_IPSR_MSEL(IP3_15_13,     SCL3_B,         SEL_I2C3_B),
+
+        PINMUX_IPSR_MSEL(IP3_18_16,     SD1_DAT2_B,     SEL_SD1_B),
+        PINMUX_IPSR_MSEL(IP3_18_16,     HCTS0_A,        SEL_HSCIF0_A),
+        PINMUX_IPSR_DATA(IP3_18_16,     CTS0),
+
+        PINMUX_IPSR_MSEL(IP3_20_19,     SD1_DAT3_B,     SEL_SD1_B),
+        PINMUX_IPSR_MSEL(IP3_20_19,     HRTS0_A,        SEL_HSCIF0_A),
+        PINMUX_IPSR_DATA(IP3_20_19,     RTS0),
+
+        PINMUX_IPSR_DATA(IP3_23_21,     SSI_SCK4),
+        PINMUX_IPSR_DATA(IP3_23_21,     DU0_DR0),
+        PINMUX_IPSR_DATA(IP3_23_21,     LCDOUT0),
+        PINMUX_IPSR_DATA(IP3_23_21,     AUDATA2),
+        PINMUX_IPSR_DATA(IP3_23_21,     ARM_TRACEDATA_2),
+        PINMUX_IPSR_MSEL(IP3_23_21,     SDA3_C,         SEL_I2C3_C),
+        PINMUX_IPSR_DATA(IP3_23_21,     ADICHS1),
+        PINMUX_IPSR_MSEL(IP3_23_21,     TS_SDEN0_B,     SEL_TSIF0_B),
+
+        PINMUX_IPSR_DATA(IP3_26_24,     SSI_WS4),
+        PINMUX_IPSR_DATA(IP3_26_24,     DU0_DR1),
+        PINMUX_IPSR_DATA(IP3_26_24,     LCDOUT1),
+        PINMUX_IPSR_DATA(IP3_26_24,     AUDATA3),
+        PINMUX_IPSR_DATA(IP3_26_24,     ARM_TRACEDATA_3),
+        PINMUX_IPSR_MSEL(IP3_26_24,     SCL3_C,         SEL_I2C3_C),
+        PINMUX_IPSR_DATA(IP3_26_24,     ADICHS2),
+        PINMUX_IPSR_MSEL(IP3_26_24,     TS_SPSYNC0_B,   SEL_TSIF0_B),
+
+        PINMUX_IPSR_DATA(IP3_27,        DU0_DR2),
+        PINMUX_IPSR_DATA(IP3_27,        LCDOUT2),
+
+        PINMUX_IPSR_DATA(IP3_28,        DU0_DR3),
+        PINMUX_IPSR_DATA(IP3_28,        LCDOUT3),
+
+        PINMUX_IPSR_DATA(IP3_29,        DU0_DR4),
+        PINMUX_IPSR_DATA(IP3_29,        LCDOUT4),
+
+        PINMUX_IPSR_DATA(IP3_30,        DU0_DR5),
+        PINMUX_IPSR_DATA(IP3_30,        LCDOUT5),
+
+        PINMUX_IPSR_DATA(IP3_31,        DU0_DR6),
+        PINMUX_IPSR_DATA(IP3_31,        LCDOUT6),
+
+        /* IPSR4 */
+        PINMUX_IPSR_DATA(IP4_0,         DU0_DR7),
+        PINMUX_IPSR_DATA(IP4_0,         LCDOUT7),
+
+        PINMUX_IPSR_DATA(IP4_3_1,       DU0_DG0),
+        PINMUX_IPSR_DATA(IP4_3_1,       LCDOUT8),
+        PINMUX_IPSR_DATA(IP4_3_1,       AUDATA4),
+        PINMUX_IPSR_DATA(IP4_3_1,       ARM_TRACEDATA_4),
+        PINMUX_IPSR_DATA(IP4_3_1,       TX1_D),
+        PINMUX_IPSR_DATA(IP4_3_1,       CAN0_TX_A),
+        PINMUX_IPSR_DATA(IP4_3_1,       ADICHS0),
+
+        PINMUX_IPSR_DATA(IP4_6_4,       DU0_DG1),
+        PINMUX_IPSR_DATA(IP4_6_4,       LCDOUT9),
+        PINMUX_IPSR_DATA(IP4_6_4,       AUDATA5),
+        PINMUX_IPSR_DATA(IP4_6_4,       ARM_TRACEDATA_5),
+        PINMUX_IPSR_MSEL(IP4_6_4,       RX1_D,          SEL_SCIF1_D),
+        PINMUX_IPSR_MSEL(IP4_6_4,       CAN0_RX_A,      SEL_CAN0_A),
+        PINMUX_IPSR_DATA(IP4_6_4,       ADIDATA),
+
+        PINMUX_IPSR_DATA(IP4_7,         DU0_DG2),
+        PINMUX_IPSR_DATA(IP4_7,         LCDOUT10),
+
+        PINMUX_IPSR_DATA(IP4_8,         DU0_DG3),
+        PINMUX_IPSR_DATA(IP4_8,         LCDOUT11),
+
+        PINMUX_IPSR_DATA(IP4_10_9,      DU0_DG4),
+        PINMUX_IPSR_DATA(IP4_10_9,      LCDOUT12),
+        PINMUX_IPSR_MSEL(IP4_10_9,      RX0_B,          SEL_SCIF0_B),
+
+        PINMUX_IPSR_DATA(IP4_12_11,     DU0_DG5),
+        PINMUX_IPSR_DATA(IP4_12_11,     LCDOUT13),
+        PINMUX_IPSR_DATA(IP4_12_11,     TX0_B),
+
+        PINMUX_IPSR_DATA(IP4_14_13,     DU0_DG6),
+        PINMUX_IPSR_DATA(IP4_14_13,     LCDOUT14),
+        PINMUX_IPSR_MSEL(IP4_14_13,     RX4_A,          SEL_SCIF4_A),
+
+        PINMUX_IPSR_DATA(IP4_16_15,     DU0_DG7),
+        PINMUX_IPSR_DATA(IP4_16_15,     LCDOUT15),
+        PINMUX_IPSR_DATA(IP4_16_15,     TX4_A),
+
+        PINMUX_IPSR_MSEL(IP4_20_17,     SSI_SCK2_B,     SEL_SSI2_B),
+        PINMUX_DATA(VI0_R0_B_MARK,      FN_IP4_20_17,   FN_VI0_R0_B,    FN_SEL_VI0_B), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R0_D_MARK,      FN_IP4_20_17,   FN_VI0_R0_B,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP4_20_17,     DU0_DB0),
+        PINMUX_IPSR_DATA(IP4_20_17,     LCDOUT16),
+        PINMUX_IPSR_DATA(IP4_20_17,     AUDATA6),
+        PINMUX_IPSR_DATA(IP4_20_17,     ARM_TRACEDATA_6),
+        PINMUX_IPSR_MSEL(IP4_20_17,     GPSCLK_A,       SEL_GPS_A),
+        PINMUX_IPSR_DATA(IP4_20_17,     PWM0_A),
+        PINMUX_IPSR_DATA(IP4_20_17,     ADICLK),
+        PINMUX_IPSR_MSEL(IP4_20_17,     TS_SDAT0_B,     SEL_TSIF0_B),
+
+        PINMUX_IPSR_DATA(IP4_24_21,     AUDIO_CLKC),
+        PINMUX_DATA(VI0_R1_B_MARK,      FN_IP4_24_21,   FN_VI0_R1_B,    FN_SEL_VI0_B), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R1_D_MARK,      FN_IP4_24_21,   FN_VI0_R1_B,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP4_24_21,     DU0_DB1),
+        PINMUX_IPSR_DATA(IP4_24_21,     LCDOUT17),
+        PINMUX_IPSR_DATA(IP4_24_21,     AUDATA7),
+        PINMUX_IPSR_DATA(IP4_24_21,     ARM_TRACEDATA_7),
+        PINMUX_IPSR_MSEL(IP4_24_21,     GPSIN_A,        SEL_GPS_A),
+        PINMUX_IPSR_DATA(IP4_24_21,     ADICS_SAMP),
+        PINMUX_IPSR_MSEL(IP4_24_21,     TS_SCK0_B,      SEL_TSIF0_B),
+
+        PINMUX_DATA(VI0_R2_B_MARK,      FN_IP4_26_25,   FN_VI0_R2_B,    FN_SEL_VI0_B), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R2_D_MARK,      FN_IP4_26_25,   FN_VI0_R2_B,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP4_26_25,     DU0_DB2),
+        PINMUX_IPSR_DATA(IP4_26_25,     LCDOUT18),
+
+        PINMUX_IPSR_MSEL(IP4_28_27,     VI0_R3_B,       SEL_VI0_B),
+        PINMUX_IPSR_DATA(IP4_28_27,     DU0_DB3),
+        PINMUX_IPSR_DATA(IP4_28_27,     LCDOUT19),
+
+        PINMUX_DATA(VI0_R4_B_MARK,      FN_IP4_30_29,   FN_VI0_R4_B,    FN_SEL_VI0_B), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R4_D_MARK,      FN_IP4_30_29,   FN_VI0_R4_B,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP4_30_29,     DU0_DB4),
+        PINMUX_IPSR_DATA(IP4_30_29,     LCDOUT20),
+
+        /* IPSR5 */
+        PINMUX_DATA(VI0_R5_B_MARK,      FN_IP5_1_0,     FN_VI0_R5_B,    FN_SEL_VI0_B), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R5_D_MARK,      FN_IP5_1_0,     FN_VI0_R5_B,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP5_1_0,       DU0_DB5),
+        PINMUX_IPSR_DATA(IP5_1_0,       LCDOUT21),
+
+        PINMUX_IPSR_MSEL(IP5_3_2,       VI1_DATA10_B,   SEL_VI1_B),
+        PINMUX_IPSR_DATA(IP5_3_2,       DU0_DB6),
+        PINMUX_IPSR_DATA(IP5_3_2,       LCDOUT22),
+
+        PINMUX_IPSR_MSEL(IP5_5_4,       VI1_DATA11_B,   SEL_VI1_B),
+        PINMUX_IPSR_DATA(IP5_5_4,       DU0_DB7),
+        PINMUX_IPSR_DATA(IP5_5_4,       LCDOUT23),
+
+        PINMUX_IPSR_DATA(IP5_6,         DU0_DOTCLKIN),
+        PINMUX_IPSR_DATA(IP5_6,         QSTVA_QVS),
+
+        PINMUX_IPSR_DATA(IP5_7,         DU0_DOTCLKO_UT0),
+        PINMUX_IPSR_DATA(IP5_7,         QCLK),
+
+        PINMUX_IPSR_DATA(IP5_9_8,       DU0_DOTCLKO_UT1),
+        PINMUX_IPSR_DATA(IP5_9_8,       QSTVB_QVE),
+        PINMUX_IPSR_DATA(IP5_9_8,       AUDIO_CLKOUT_A),
+        PINMUX_IPSR_MSEL(IP5_9_8,       REMOCON_C,      SEL_REMOCON_C),
+
+        PINMUX_IPSR_MSEL(IP5_11_10,     SSI_WS2_B,      SEL_SSI2_B),
+        PINMUX_IPSR_DATA(IP5_11_10,     DU0_EXHSYNC_DU0_HSYNC),
+        PINMUX_IPSR_DATA(IP5_11_10,     QSTH_QHS),
+
+        PINMUX_IPSR_DATA(IP5_12,        DU0_EXVSYNC_DU0_VSYNC),
+        PINMUX_IPSR_DATA(IP5_12,        QSTB_QHE),
+
+        PINMUX_IPSR_DATA(IP5_14_13,     DU0_EXODDF_DU0_ODDF_DISP_CDE),
+        PINMUX_IPSR_DATA(IP5_14_13,     QCPV_QDE),
+        PINMUX_IPSR_MSEL(IP5_14_13,     FMCLK_D,        SEL_FM_D),
+
+        PINMUX_IPSR_MSEL(IP5_17_15,     SSI_SCK1_A,     SEL_SSI1_A),
+        PINMUX_IPSR_DATA(IP5_17_15,     DU0_DISP),
+        PINMUX_IPSR_DATA(IP5_17_15,     QPOLA),
+        PINMUX_IPSR_DATA(IP5_17_15,     AUDCK),
+        PINMUX_IPSR_DATA(IP5_17_15,     ARM_TRACECLK),
+        PINMUX_IPSR_DATA(IP5_17_15,     BPFCLK_D),
+
+        PINMUX_IPSR_MSEL(IP5_20_18,     SSI_WS1_A,      SEL_SSI1_A),
+        PINMUX_IPSR_DATA(IP5_20_18,     DU0_CDE),
+        PINMUX_IPSR_DATA(IP5_20_18,     QPOLB),
+        PINMUX_IPSR_DATA(IP5_20_18,     AUDSYNC),
+        PINMUX_IPSR_DATA(IP5_20_18,     ARM_TRACECTL),
+        PINMUX_IPSR_MSEL(IP5_20_18,     FMIN_D,         SEL_FM_D),
+
+        PINMUX_IPSR_MSEL(IP5_22_21,     SD1_CD_B,       SEL_SD1_B),
+        PINMUX_IPSR_DATA(IP5_22_21,     SSI_SCK78),
+        PINMUX_IPSR_MSEL(IP5_22_21,     HSPI_RX0_B,     SEL_HSPI0_B),
+        PINMUX_IPSR_DATA(IP5_22_21,     TX1_B),
+
+        PINMUX_IPSR_MSEL(IP5_25_23,     SD1_WP_B,       SEL_SD1_B),
+        PINMUX_IPSR_DATA(IP5_25_23,     SSI_WS78),
+        PINMUX_IPSR_MSEL(IP5_25_23,     HSPI_CLK0_B,    SEL_HSPI0_B),
+        PINMUX_IPSR_MSEL(IP5_25_23,     RX1_B,          SEL_SCIF1_B),
+        PINMUX_IPSR_MSEL(IP5_25_23,     CAN_CLK_D,      SEL_CANCLK_D),
+
+        PINMUX_IPSR_DATA(IP5_28_26,     SSI_SDATA8),
+        PINMUX_IPSR_MSEL(IP5_28_26,     SSI_SCK2_A,     SEL_SSI2_A),
+        PINMUX_IPSR_MSEL(IP5_28_26,     HSPI_CS0_B,     SEL_HSPI0_B),
+        PINMUX_IPSR_DATA(IP5_28_26,     TX2_A),
+        PINMUX_IPSR_DATA(IP5_28_26,     CAN0_TX_B),
+
+        PINMUX_IPSR_DATA(IP5_30_29,     SSI_SDATA7),
+        PINMUX_IPSR_DATA(IP5_30_29,     HSPI_TX0_B),
+        PINMUX_IPSR_MSEL(IP5_30_29,     RX2_A,          SEL_SCIF2_A),
+        PINMUX_IPSR_MSEL(IP5_30_29,     CAN0_RX_B,      SEL_CAN0_B),
+
+        /* IPSR6 */
+        PINMUX_IPSR_DATA(IP6_1_0,       SSI_SCK6),
+        PINMUX_IPSR_MSEL(IP6_1_0,       HSPI_RX2_A,     SEL_HSPI2_A),
+        PINMUX_IPSR_MSEL(IP6_1_0,       FMCLK_B,        SEL_FM_B),
+        PINMUX_IPSR_DATA(IP6_1_0,       CAN1_TX_B),
+
+        PINMUX_IPSR_DATA(IP6_4_2,       SSI_WS6),
+        PINMUX_IPSR_MSEL(IP6_4_2,       HSPI_CLK2_A,    SEL_HSPI2_A),
+        PINMUX_IPSR_DATA(IP6_4_2,       BPFCLK_B),
+        PINMUX_IPSR_MSEL(IP6_4_2,       CAN1_RX_B,      SEL_CAN1_B),
+
+        PINMUX_IPSR_DATA(IP6_6_5,       SSI_SDATA6),
+        PINMUX_IPSR_DATA(IP6_6_5,       HSPI_TX2_A),
+        PINMUX_IPSR_MSEL(IP6_6_5,       FMIN_B,         SEL_FM_B),
+
+        PINMUX_IPSR_DATA(IP6_7,         SSI_SCK5),
+        PINMUX_IPSR_MSEL(IP6_7,         RX4_C,          SEL_SCIF4_C),
+
+        PINMUX_IPSR_DATA(IP6_8,         SSI_WS5),
+        PINMUX_IPSR_DATA(IP6_8,         TX4_C),
+
+        PINMUX_IPSR_DATA(IP6_9,         SSI_SDATA5),
+        PINMUX_IPSR_MSEL(IP6_9,         RX0_D,          SEL_SCIF0_D),
+
+        PINMUX_IPSR_DATA(IP6_10,        SSI_WS34),
+        PINMUX_IPSR_DATA(IP6_10,        ARM_TRACEDATA_8),
+
+        PINMUX_IPSR_DATA(IP6_12_11,     SSI_SDATA4),
+        PINMUX_IPSR_MSEL(IP6_12_11,     SSI_WS2_A,      SEL_SSI2_A),
+        PINMUX_IPSR_DATA(IP6_12_11,     ARM_TRACEDATA_9),
+
+        PINMUX_IPSR_DATA(IP6_13,        SSI_SDATA3),
+        PINMUX_IPSR_DATA(IP6_13,        ARM_TRACEDATA_10),
+
+        PINMUX_IPSR_DATA(IP6_15_14,     SSI_SCK012),
+        PINMUX_IPSR_DATA(IP6_15_14,     ARM_TRACEDATA_11),
+        PINMUX_IPSR_DATA(IP6_15_14,     TX0_D),
+
+        PINMUX_IPSR_DATA(IP6_16,        SSI_WS012),
+        PINMUX_IPSR_DATA(IP6_16,        ARM_TRACEDATA_12),
+
+        PINMUX_IPSR_DATA(IP6_18_17,     SSI_SDATA2),
+        PINMUX_IPSR_MSEL(IP6_18_17,     HSPI_CS2_A,     SEL_HSPI2_A),
+        PINMUX_IPSR_DATA(IP6_18_17,     ARM_TRACEDATA_13),
+        PINMUX_IPSR_MSEL(IP6_18_17,     SDA1_A,         SEL_I2C1_A),
+
+        PINMUX_IPSR_DATA(IP6_20_19,     SSI_SDATA1),
+        PINMUX_IPSR_DATA(IP6_20_19,     ARM_TRACEDATA_14),
+        PINMUX_IPSR_MSEL(IP6_20_19,     SCL1_A,         SEL_I2C1_A),
+        PINMUX_IPSR_MSEL(IP6_20_19,     SCK2_A,         SEL_SCIF2_A),
+
+        PINMUX_IPSR_DATA(IP6_21,        SSI_SDATA0),
+        PINMUX_IPSR_DATA(IP6_21,        ARM_TRACEDATA_15),
+
+        PINMUX_IPSR_DATA(IP6_23_22,     SD0_CLK),
+        PINMUX_IPSR_DATA(IP6_23_22,     SUB_TDO),
+
+        PINMUX_IPSR_DATA(IP6_25_24,     SD0_CMD),
+        PINMUX_IPSR_DATA(IP6_25_24,     SUB_TRST),
+
+        PINMUX_IPSR_DATA(IP6_27_26,     SD0_DAT0),
+        PINMUX_IPSR_DATA(IP6_27_26,     SUB_TMS),
+
+        PINMUX_IPSR_DATA(IP6_29_28,     SD0_DAT1),
+        PINMUX_IPSR_DATA(IP6_29_28,     SUB_TCK),
+
+        PINMUX_IPSR_DATA(IP6_31_30,     SD0_DAT2),
+        PINMUX_IPSR_DATA(IP6_31_30,     SUB_TDI),
+
+        /* IPSR7 */
+        PINMUX_IPSR_DATA(IP7_1_0,       SD0_DAT3),
+        PINMUX_IPSR_MSEL(IP7_1_0,       IRQ1_B,         SEL_IRQ1_B),
+
+        PINMUX_IPSR_DATA(IP7_3_2,       SD0_CD),
+        PINMUX_IPSR_DATA(IP7_3_2,       TX5_A),
+
+        PINMUX_IPSR_DATA(IP7_5_4,       SD0_WP),
+        PINMUX_IPSR_MSEL(IP7_5_4,       RX5_A,          SEL_SCIF5_A),
+
+        PINMUX_IPSR_DATA(IP7_8_6,       VI1_CLKENB),
+        PINMUX_IPSR_MSEL(IP7_8_6,       HSPI_CLK0_A,    SEL_HSPI0_A),
+        PINMUX_IPSR_DATA(IP7_8_6,       HTX1_A),
+        PINMUX_IPSR_MSEL(IP7_8_6,       RTS1_C,         SEL_SCIF1_C),
+
+        PINMUX_IPSR_DATA(IP7_11_9,      VI1_FIELD),
+        PINMUX_IPSR_MSEL(IP7_11_9,      HSPI_CS0_A,     SEL_HSPI0_A),
+        PINMUX_IPSR_MSEL(IP7_11_9,      HRX1_A,         SEL_HSCIF1_A),
+        PINMUX_IPSR_MSEL(IP7_11_9,      SCK1_C,         SEL_SCIF1_C),
+
+        PINMUX_IPSR_DATA(IP7_14_12,     VI1_HSYNC),
+        PINMUX_IPSR_MSEL(IP7_14_12,     HSPI_RX0_A,     SEL_HSPI0_A),
+        PINMUX_IPSR_MSEL(IP7_14_12,     HRTS1_A,        SEL_HSCIF1_A),
+        PINMUX_IPSR_MSEL(IP7_14_12,     FMCLK_A,        SEL_FM_A),
+        PINMUX_IPSR_MSEL(IP7_14_12,     RX1_C,          SEL_SCIF1_C),
+
+        PINMUX_IPSR_DATA(IP7_17_15,     VI1_VSYNC),
+        PINMUX_IPSR_DATA(IP7_17_15,     HSPI_TX0),
+        PINMUX_IPSR_MSEL(IP7_17_15,     HCTS1_A,        SEL_HSCIF1_A),
+        PINMUX_IPSR_DATA(IP7_17_15,     BPFCLK_A),
+        PINMUX_IPSR_DATA(IP7_17_15,     TX1_C),
+
+        PINMUX_IPSR_DATA(IP7_20_18,     TCLK0),
+        PINMUX_IPSR_MSEL(IP7_20_18,     HSCK1_A,        SEL_HSCIF1_A),
+        PINMUX_IPSR_MSEL(IP7_20_18,     FMIN_A,         SEL_FM_A),
+        PINMUX_IPSR_MSEL(IP7_20_18,     IRQ2_C,         SEL_IRQ2_C),
+        PINMUX_IPSR_MSEL(IP7_20_18,     CTS1_C,         SEL_SCIF1_C),
+        PINMUX_IPSR_DATA(IP7_20_18,     SPEEDIN),
+
+        PINMUX_IPSR_DATA(IP7_21,        VI0_CLK),
+        PINMUX_IPSR_MSEL(IP7_21,        CAN_CLK_A,      SEL_CANCLK_A),
+
+        PINMUX_IPSR_DATA(IP7_24_22,     VI0_CLKENB),
+        PINMUX_IPSR_MSEL(IP7_24_22,     SD2_DAT2_B,     SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP7_24_22,     VI1_DATA0),
+        PINMUX_IPSR_DATA(IP7_24_22,     DU1_DG6),
+        PINMUX_IPSR_MSEL(IP7_24_22,     HSPI_RX1_A,     SEL_HSPI1_A),
+        PINMUX_IPSR_MSEL(IP7_24_22,     RX4_B,          SEL_SCIF4_B),
+
+        PINMUX_IPSR_DATA(IP7_28_25,     VI0_FIELD),
+        PINMUX_IPSR_MSEL(IP7_28_25,     SD2_DAT3_B,     SEL_SD2_B),
+        PINMUX_DATA(VI0_R3_C_MARK,      FN_IP7_28_25,   FN_VI0_R3_C,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R3_D_MARK,      FN_IP7_28_25,   FN_VI0_R3_C,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP7_28_25,     VI1_DATA1),
+        PINMUX_IPSR_DATA(IP7_28_25,     DU1_DG7),
+        PINMUX_IPSR_MSEL(IP7_28_25,     HSPI_CLK1_A,    SEL_HSPI1_A),
+        PINMUX_IPSR_DATA(IP7_28_25,     TX4_B),
+
+        PINMUX_IPSR_DATA(IP7_31_29,     VI0_HSYNC),
+        PINMUX_IPSR_MSEL(IP7_31_29,     SD2_CD_B,       SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP7_31_29,     VI1_DATA2),
+        PINMUX_IPSR_DATA(IP7_31_29,     DU1_DR2),
+        PINMUX_IPSR_MSEL(IP7_31_29,     HSPI_CS1_A,     SEL_HSPI1_A),
+        PINMUX_IPSR_MSEL(IP7_31_29,     RX3_B,          SEL_SCIF3_B),
+
+        /* IPSR8 */
+        PINMUX_IPSR_DATA(IP8_2_0,       VI0_VSYNC),
+        PINMUX_IPSR_MSEL(IP8_2_0,       SD2_WP_B,       SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP8_2_0,       VI1_DATA3),
+        PINMUX_IPSR_DATA(IP8_2_0,       DU1_DR3),
+        PINMUX_IPSR_DATA(IP8_2_0,       HSPI_TX1_A),
+        PINMUX_IPSR_DATA(IP8_2_0,       TX3_B),
+
+        PINMUX_IPSR_DATA(IP8_5_3,       VI0_DATA0_VI0_B0),
+        PINMUX_IPSR_DATA(IP8_5_3,       DU1_DG2),
+        PINMUX_IPSR_MSEL(IP8_5_3,       IRQ2_B,         SEL_IRQ2_B),
+        PINMUX_IPSR_MSEL(IP8_5_3,       RX3_D,          SEL_SCIF3_D),
+
+        PINMUX_IPSR_DATA(IP8_8_6,       VI0_DATA1_VI0_B1),
+        PINMUX_IPSR_DATA(IP8_8_6,       DU1_DG3),
+        PINMUX_IPSR_MSEL(IP8_8_6,       IRQ3_B,         SEL_IRQ3_B),
+        PINMUX_IPSR_DATA(IP8_8_6,       TX3_D),
+
+        PINMUX_IPSR_DATA(IP8_10_9,      VI0_DATA2_VI0_B2),
+        PINMUX_IPSR_DATA(IP8_10_9,      DU1_DG4),
+        PINMUX_IPSR_MSEL(IP8_10_9,      RX0_C,          SEL_SCIF0_C),
+
+        PINMUX_IPSR_DATA(IP8_13_11,     VI0_DATA3_VI0_B3),
+        PINMUX_IPSR_DATA(IP8_13_11,     DU1_DG5),
+        PINMUX_IPSR_DATA(IP8_13_11,     TX1_A),
+        PINMUX_IPSR_DATA(IP8_13_11,     TX0_C),
+
+        PINMUX_IPSR_DATA(IP8_15_14,     VI0_DATA4_VI0_B4),
+        PINMUX_IPSR_DATA(IP8_15_14,     DU1_DB2),
+        PINMUX_IPSR_MSEL(IP8_15_14,     RX1_A,          SEL_SCIF1_A),
+
+        PINMUX_IPSR_DATA(IP8_18_16,     VI0_DATA5_VI0_B5),
+        PINMUX_IPSR_DATA(IP8_18_16,     DU1_DB3),
+        PINMUX_IPSR_MSEL(IP8_18_16,     SCK1_A,         SEL_SCIF1_A),
+        PINMUX_IPSR_DATA(IP8_18_16,     PWM4),
+        PINMUX_IPSR_MSEL(IP8_18_16,     HSCK1_B,        SEL_HSCIF1_B),
+
+        PINMUX_IPSR_DATA(IP8_21_19,     VI0_DATA6_VI0_G0),
+        PINMUX_IPSR_DATA(IP8_21_19,     DU1_DB4),
+        PINMUX_IPSR_MSEL(IP8_21_19,     CTS1_A,         SEL_SCIF1_A),
+        PINMUX_IPSR_DATA(IP8_21_19,     PWM5),
+
+        PINMUX_IPSR_DATA(IP8_23_22,     VI0_DATA7_VI0_G1),
+        PINMUX_IPSR_DATA(IP8_23_22,     DU1_DB5),
+        PINMUX_IPSR_MSEL(IP8_23_22,     RTS1_A,         SEL_SCIF1_A),
+
+        PINMUX_IPSR_DATA(IP8_26_24,     VI0_G2),
+        PINMUX_IPSR_DATA(IP8_26_24,     SD2_CLK_B),
+        PINMUX_IPSR_DATA(IP8_26_24,     VI1_DATA4),
+        PINMUX_IPSR_DATA(IP8_26_24,     DU1_DR4),
+        PINMUX_IPSR_DATA(IP8_26_24,     HTX1_B),
+
+        PINMUX_IPSR_DATA(IP8_29_27,     VI0_G3),
+        PINMUX_IPSR_MSEL(IP8_29_27,     SD2_CMD_B,      SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP8_29_27,     VI1_DATA5),
+        PINMUX_IPSR_DATA(IP8_29_27,     DU1_DR5),
+        PINMUX_IPSR_MSEL(IP8_29_27,     HRX1_B,         SEL_HSCIF1_B),
+
+        /* IPSR9 */
+        PINMUX_IPSR_DATA(IP9_2_0,       VI0_G4),
+        PINMUX_IPSR_MSEL(IP9_2_0,       SD2_DAT0_B,     SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP9_2_0,       VI1_DATA6),
+        PINMUX_IPSR_DATA(IP9_2_0,       DU1_DR6),
+        PINMUX_IPSR_MSEL(IP9_2_0,       HRTS1_B,        SEL_HSCIF1_B),
+
+        PINMUX_IPSR_DATA(IP9_5_3,       VI0_G5),
+        PINMUX_IPSR_MSEL(IP9_5_3,       SD2_DAT1_B,     SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP9_5_3,       VI1_DATA7),
+        PINMUX_IPSR_DATA(IP9_5_3,       DU1_DR7),
+        PINMUX_IPSR_MSEL(IP9_5_3,       HCTS1_B,        SEL_HSCIF1_B),
+
+        PINMUX_DATA(VI0_R0_A_MARK,      FN_IP9_8_6,     FN_VI0_R0_A,    FN_SEL_VI0_A), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R0_C_MARK,      FN_IP9_8_6,     FN_VI0_R0_A,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP9_8_6,       VI1_CLK),
+        PINMUX_IPSR_DATA(IP9_8_6,       ETH_REF_CLK),
+        PINMUX_IPSR_DATA(IP9_8_6,       DU1_DOTCLKIN),
+
+        PINMUX_DATA(VI0_R1_A_MARK,      FN_IP9_11_9,    FN_VI0_R1_A,    FN_SEL_VI0_A), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R1_C_MARK,      FN_IP9_11_9,    FN_VI0_R1_A,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP9_11_9,      VI1_DATA8),
+        PINMUX_IPSR_DATA(IP9_11_9,      DU1_DB6),
+        PINMUX_IPSR_DATA(IP9_11_9,      ETH_TXD0),
+        PINMUX_IPSR_DATA(IP9_11_9,      PWM2),
+        PINMUX_IPSR_DATA(IP9_11_9,      TCLK1),
+
+        PINMUX_DATA(VI0_R2_A_MARK,      FN_IP9_14_12,   FN_VI0_R2_A,    FN_SEL_VI0_A), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R2_C_MARK,      FN_IP9_14_12,   FN_VI0_R2_A,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP9_14_12,     VI1_DATA9),
+        PINMUX_IPSR_DATA(IP9_14_12,     DU1_DB7),
+        PINMUX_IPSR_DATA(IP9_14_12,     ETH_TXD1),
+        PINMUX_IPSR_DATA(IP9_14_12,     PWM3),
+
+        PINMUX_IPSR_MSEL(IP9_17_15,     VI0_R3_A,       SEL_VI0_A),
+        PINMUX_IPSR_DATA(IP9_17_15,     ETH_CRS_DV),
+        PINMUX_IPSR_DATA(IP9_17_15,     IECLK),
+        PINMUX_IPSR_MSEL(IP9_17_15,     SCK2_C,         SEL_SCIF2_C),
+
+        PINMUX_DATA(VI0_R4_A_MARK,      FN_IP9_20_18,   FN_VI0_R4_A,    FN_SEL_VI0_A), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R3_C_MARK,      FN_IP9_20_18,   FN_VI0_R4_A,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP9_20_18,     ETH_TX_EN),
+        PINMUX_IPSR_DATA(IP9_20_18,     IETX),
+        PINMUX_IPSR_DATA(IP9_20_18,     TX2_C),
+
+        PINMUX_DATA(VI0_R5_A_MARK,      FN_IP9_23_21,   FN_VI0_R5_A,    FN_SEL_VI0_A), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R5_C_MARK,      FN_IP9_23_21,   FN_VI0_R5_A,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP9_23_21,     ETH_RX_ER),
+        PINMUX_IPSR_MSEL(IP9_23_21,     FMCLK_C,        SEL_FM_C),
+        PINMUX_IPSR_DATA(IP9_23_21,     IERX),
+        PINMUX_IPSR_MSEL(IP9_23_21,     RX2_C,          SEL_SCIF2_C),
+
+        PINMUX_IPSR_MSEL(IP9_26_24,     VI1_DATA10_A,   SEL_VI1_A),
+        PINMUX_IPSR_DATA(IP9_26_24,     DU1_DOTCLKOUT),
+        PINMUX_IPSR_DATA(IP9_26_24,     ETH_RXD0),
+        PINMUX_IPSR_DATA(IP9_26_24,     BPFCLK_C),
+        PINMUX_IPSR_DATA(IP9_26_24,     TX2_D),
+        PINMUX_IPSR_MSEL(IP9_26_24,     SDA2_C,         SEL_I2C2_C),
+
+        PINMUX_IPSR_MSEL(IP9_29_27,     VI1_DATA11_A,   SEL_VI1_A),
+        PINMUX_IPSR_DATA(IP9_29_27,     DU1_EXHSYNC_DU1_HSYNC),
+        PINMUX_IPSR_DATA(IP9_29_27,     ETH_RXD1),
+        PINMUX_IPSR_MSEL(IP9_29_27,     FMIN_C,         SEL_FM_C),
+        PINMUX_IPSR_MSEL(IP9_29_27,     RX2_D,          SEL_SCIF2_D),
+        PINMUX_IPSR_MSEL(IP9_29_27,     SCL2_C,         SEL_I2C2_C),
+
+        /* IPSR10 */
+        PINMUX_IPSR_DATA(IP10_2_0,      SD2_CLK_A),
+        PINMUX_IPSR_DATA(IP10_2_0,      DU1_EXVSYNC_DU1_VSYNC),
+        PINMUX_IPSR_DATA(IP10_2_0,      ATARD1),
+        PINMUX_IPSR_DATA(IP10_2_0,      ETH_MDC),
+        PINMUX_IPSR_MSEL(IP10_2_0,      SDA1_B,         SEL_I2C1_B),
+
+        PINMUX_IPSR_MSEL(IP10_5_3,      SD2_CMD_A,      SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_5_3,      DU1_EXODDF_DU1_ODDF_DISP_CDE),
+        PINMUX_IPSR_DATA(IP10_5_3,      ATAWR1),
+        PINMUX_IPSR_DATA(IP10_5_3,      ETH_MDIO),
+        PINMUX_IPSR_MSEL(IP10_5_3,      SCL1_B,         SEL_I2C1_B),
+
+        PINMUX_IPSR_MSEL(IP10_8_6,      SD2_DAT0_A,     SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_8_6,      DU1_DISP),
+        PINMUX_IPSR_DATA(IP10_8_6,      ATACS01),
+        PINMUX_IPSR_MSEL(IP10_8_6,      DREQ1_B,        SEL_DREQ1_B),
+        PINMUX_IPSR_DATA(IP10_8_6,      ETH_LINK),
+        PINMUX_IPSR_MSEL(IP10_8_6,      CAN1_RX_A,      SEL_CAN1_A),
+
+        PINMUX_IPSR_MSEL(IP10_12_9,     SD2_DAT1_A,     SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_12_9,     DU1_CDE),
+        PINMUX_IPSR_DATA(IP10_12_9,     ATACS11),
+        PINMUX_IPSR_DATA(IP10_12_9,     DACK1_B),
+        PINMUX_IPSR_DATA(IP10_12_9,     ETH_MAGIC),
+        PINMUX_IPSR_DATA(IP10_12_9,     CAN1_TX_A),
+        PINMUX_IPSR_DATA(IP10_12_9,     PWM6),
+
+        PINMUX_IPSR_MSEL(IP10_15_13,    SD2_DAT2_A,     SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_15_13,    VI1_DATA12),
+        PINMUX_IPSR_MSEL(IP10_15_13,    DREQ2_B,        SEL_DREQ2_B),
+        PINMUX_IPSR_DATA(IP10_15_13,    ATADIR1),
+        PINMUX_IPSR_MSEL(IP10_15_13,    HSPI_CLK2_B,    SEL_HSPI2_B),
+        PINMUX_IPSR_MSEL(IP10_15_13,    GPSCLK_B,       SEL_GPS_B),
+
+        PINMUX_IPSR_MSEL(IP10_18_16,    SD2_DAT3_A,     SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_18_16,    VI1_DATA13),
+        PINMUX_IPSR_DATA(IP10_18_16,    DACK2_B),
+        PINMUX_IPSR_DATA(IP10_18_16,    ATAG1),
+        PINMUX_IPSR_MSEL(IP10_18_16,    HSPI_CS2_B,     SEL_HSPI2_B),
+        PINMUX_IPSR_MSEL(IP10_18_16,    GPSIN_B,        SEL_GPS_B),
+
+        PINMUX_IPSR_MSEL(IP10_21_19,    SD2_CD_A,       SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_21_19,    VI1_DATA14),
+        PINMUX_IPSR_MSEL(IP10_21_19,    EX_WAIT1_B,     SEL_WAIT1_B),
+        PINMUX_IPSR_MSEL(IP10_21_19,    DREQ0_B,        SEL_DREQ0_B),
+        PINMUX_IPSR_MSEL(IP10_21_19,    HSPI_RX2_B,     SEL_HSPI2_B),
+        PINMUX_IPSR_MSEL(IP10_21_19,    REMOCON_A,      SEL_REMOCON_A),
+
+        PINMUX_IPSR_MSEL(IP10_24_22,    SD2_WP_A,       SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_24_22,    VI1_DATA15),
+        PINMUX_IPSR_MSEL(IP10_24_22,    EX_WAIT2_B,     SEL_WAIT2_B),
+        PINMUX_IPSR_DATA(IP10_24_22,    DACK0_B),
+        PINMUX_IPSR_DATA(IP10_24_22,    HSPI_TX2_B),
+        PINMUX_IPSR_MSEL(IP10_24_22,    CAN_CLK_C,      SEL_CANCLK_C),
+};
+
+static struct sh_pfc_pin pinmux_pins[] = {
+        PINMUX_GPIO_GP_ALL(),
+};
+
+/* Pin numbers for pins without a corresponding GPIO port number are computed
+ * from the row and column numbers with a 1000 offset to avoid collisions with
+ * GPIO port numbers.
+ */
+#define PIN_NUMBER(row, col)            (1000+((row)-1)*25+(col)-1)
+
+/* - macro */
+#define SH_PFC_PINS(name, args...) \
+        static const unsigned int name ##_pins[] = { args }
+#define SH_PFC_MUX1(name, arg1)                                 \
+        static const unsigned int name ##_mux[]  = { arg1##_MARK }
+#define SH_PFC_MUX2(name, arg1, arg2)                                   \
+        static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, }
+#define SH_PFC_MUX3(name, arg1, arg2, arg3)                                     \
+        static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK,  \
+                                                     arg3##_MARK }
+#define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4)                       \
+        static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
+                                                     arg3##_MARK, arg4##_MARK }
+#define SH_PFC_MUX8(name, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) \
+        static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
+                                                     arg3##_MARK, arg4##_MARK, \
+                                                     arg5##_MARK, arg6##_MARK, \
+                                                     arg7##_MARK, arg8##_MARK, }
+
+/* - Ether ------------------------------------------------------------------ */
+SH_PFC_PINS(ether_rmii,         RCAR_GP_PIN(4, 10),     RCAR_GP_PIN(4, 11),
+                                RCAR_GP_PIN(4, 13),     RCAR_GP_PIN(4, 9),
+                                RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16),
+                                RCAR_GP_PIN(4, 12),     RCAR_GP_PIN(4, 14),
+                                RCAR_GP_PIN(4, 18),     RCAR_GP_PIN(4, 17));
+static const unsigned int ether_rmii_mux[] = {
+        ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REF_CLK_MARK,
+        ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
+        ETH_MDIO_MARK, ETH_MDC_MARK,
+};
+SH_PFC_PINS(ether_link,         RCAR_GP_PIN(4, 19));
+SH_PFC_MUX1(ether_link,         ETH_LINK);
+SH_PFC_PINS(ether_magic,        RCAR_GP_PIN(4, 20));
+SH_PFC_MUX1(ether_magic,        ETH_MAGIC);
+
+/* - SCIF macro ------------------------------------------------------------- */
+#define SCIF_PFC_PIN(name, args...)     SH_PFC_PINS(name, args)
+#define SCIF_PFC_DAT(name, tx, rx)      SH_PFC_MUX2(name, tx, rx)
+#define SCIF_PFC_CTR(name, cts, rts)    SH_PFC_MUX2(name, cts, rts)
+#define SCIF_PFC_CLK(name, sck)         SH_PFC_MUX1(name, sck)
+
+/* - HSCIF0 ----------------------------------------------------------------- */
+SCIF_PFC_PIN(hscif0_data_a,     RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 18));
+SCIF_PFC_DAT(hscif0_data_a,     HTX0_A,                 HRX0_A);
+SCIF_PFC_PIN(hscif0_data_b,     RCAR_GP_PIN(0, 29),     RCAR_GP_PIN(0, 30));
+SCIF_PFC_DAT(hscif0_data_b,     HTX0_B,                 HRX0_B);
+SCIF_PFC_PIN(hscif0_ctrl_a,     RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
+SCIF_PFC_CTR(hscif0_ctrl_a,     HCTS0_A,                HRTS0_A);
+SCIF_PFC_PIN(hscif0_ctrl_b,     RCAR_GP_PIN(0, 31),     RCAR_GP_PIN(0, 28));
+SCIF_PFC_CTR(hscif0_ctrl_b,     HCTS0_B,                HRTS0_B);
+SCIF_PFC_PIN(hscif0_clk,        RCAR_GP_PIN(1, 19));
+SCIF_PFC_CLK(hscif0_clk,        HSCK0);
+
+/* - HSCIF1 ----------------------------------------------------------------- */
+SCIF_PFC_PIN(hscif1_data_a,     RCAR_GP_PIN(3, 19),     RCAR_GP_PIN(3, 20));
+SCIF_PFC_DAT(hscif1_data_a,     HTX1_A,                 HRX1_A);
+SCIF_PFC_PIN(hscif1_data_b,     RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6));
+SCIF_PFC_DAT(hscif1_data_b,     HTX1_B,                 HRX1_B);
+SCIF_PFC_PIN(hscif1_ctrl_a,     RCAR_GP_PIN(3, 22),     RCAR_GP_PIN(3, 21));
+SCIF_PFC_CTR(hscif1_ctrl_a,     HCTS1_A,                HRTS1_A);
+SCIF_PFC_PIN(hscif1_ctrl_b,     RCAR_GP_PIN(4, 8),      RCAR_GP_PIN(4, 7));
+SCIF_PFC_CTR(hscif1_ctrl_b,     HCTS1_B,                HRTS1_B);
+SCIF_PFC_PIN(hscif1_clk_a,      RCAR_GP_PIN(3, 23));
+SCIF_PFC_CLK(hscif1_clk_a,      HSCK1_A);
+SCIF_PFC_PIN(hscif1_clk_b,      RCAR_GP_PIN(4, 2));
+SCIF_PFC_CLK(hscif1_clk_b,      HSCK1_B);
+
+/* - HSPI macro --------------------------------------------------------------*/
+#define HSPI_PFC_PIN(name, args...)             SH_PFC_PINS(name, args)
+#define HSPI_PFC_DAT(name, clk, cs, rx, tx)     SH_PFC_MUX4(name, clk, cs, rx, tx)
+
+/* - HSPI0 -------------------------------------------------------------------*/
+HSPI_PFC_PIN(hspi0_a,   RCAR_GP_PIN(3, 19),     RCAR_GP_PIN(3, 20),
+                        RCAR_GP_PIN(3, 21),     RCAR_GP_PIN(3, 22));
+HSPI_PFC_DAT(hspi0_a,   HSPI_CLK0_A,            HSPI_CS0_A,
+                        HSPI_RX0_A,             HSPI_TX0);
+
+HSPI_PFC_PIN(hspi0_b,   RCAR_GP_PIN(2, 25),     RCAR_GP_PIN(2, 26),
+                        RCAR_GP_PIN(2, 24),     RCAR_GP_PIN(2, 27));
+HSPI_PFC_DAT(hspi0_b,   HSPI_CLK0_B,            HSPI_CS0_B,
+                        HSPI_RX0_B,             HSPI_TX0_B);
+
+/* - HSPI1 -------------------------------------------------------------------*/
+HSPI_PFC_PIN(hspi1_a,   RCAR_GP_PIN(3, 26),     RCAR_GP_PIN(3, 27),
+                        RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 28));
+HSPI_PFC_DAT(hspi1_a,   HSPI_CLK1_A,            HSPI_CS1_A,
+                        HSPI_RX1_A,             HSPI_TX1_A);
+
+HSPI_PFC_PIN(hspi1_b,   RCAR_GP_PIN(0, 27),     RCAR_GP_PIN(0, 26),
+                        PIN_NUMBER(20, 1),      PIN_NUMBER(25, 2));
+HSPI_PFC_DAT(hspi1_b,   HSPI_CLK1_B,            HSPI_CS1_B,
+                        HSPI_RX1_B,             HSPI_TX1_B);
+
+/* - HSPI2 -------------------------------------------------------------------*/
+HSPI_PFC_PIN(hspi2_a,   RCAR_GP_PIN(2, 29),     RCAR_GP_PIN(3, 8),
+                        RCAR_GP_PIN(2, 28),     RCAR_GP_PIN(2, 30));
+HSPI_PFC_DAT(hspi2_a,   HSPI_CLK2_A,            HSPI_CS2_A,
+                        HSPI_RX2_A,             HSPI_TX2_A);
+
+HSPI_PFC_PIN(hspi2_b,   RCAR_GP_PIN(4, 21),     RCAR_GP_PIN(4, 22),
+                        RCAR_GP_PIN(4, 23),     RCAR_GP_PIN(4, 24));
+HSPI_PFC_DAT(hspi2_b,   HSPI_CLK2_B,            HSPI_CS2_B,
+                        HSPI_RX2_B,             HSPI_TX2_B);
+
+/* - I2C macro ------------------------------------------------------------- */
+#define I2C_PFC_PIN(name, args...)      SH_PFC_PINS(name, args)
+#define I2C_PFC_MUX(name, sda, scl)     SH_PFC_MUX2(name, sda, scl)
+
+/* - I2C1 ------------------------------------------------------------------ */
+I2C_PFC_PIN(i2c1_a,     RCAR_GP_PIN(3, 8),      RCAR_GP_PIN(3, 9));
+I2C_PFC_MUX(i2c1_a,     SDA1_A,                 SCL1_A);
+I2C_PFC_PIN(i2c1_b,     RCAR_GP_PIN(4, 17),     RCAR_GP_PIN(4, 18));
+I2C_PFC_MUX(i2c1_b,     SDA1_B,                 SCL1_B);
+
+/* - I2C2 ------------------------------------------------------------------ */
+I2C_PFC_PIN(i2c2_a,     PIN_NUMBER(3, 20),      RCAR_GP_PIN(1, 3));
+I2C_PFC_MUX(i2c2_a,     SDA2_A,                 SCL2_A);
+I2C_PFC_PIN(i2c2_b,     RCAR_GP_PIN(0, 3),      RCAR_GP_PIN(0, 4));
+I2C_PFC_MUX(i2c2_b,     SDA2_B,                 SCL2_B);
+I2C_PFC_PIN(i2c2_c,     RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16));
+I2C_PFC_MUX(i2c2_c,     SDA2_C,                 SCL2_C);
+
+/* - I2C3 ------------------------------------------------------------------ */
+I2C_PFC_PIN(i2c3_a,     RCAR_GP_PIN(1, 14),     RCAR_GP_PIN(1, 15));
+I2C_PFC_MUX(i2c3_a,     SDA3_A,                 SCL3_A);
+I2C_PFC_PIN(i2c3_b,     RCAR_GP_PIN(1, 16),     RCAR_GP_PIN(1, 19));
+I2C_PFC_MUX(i2c3_b,     SDA3_B,                 SCL3_B);
+I2C_PFC_PIN(i2c3_c,     RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 23));
+I2C_PFC_MUX(i2c3_c,     SDA3_C,                 SCL3_C);
+
+/* - MMC macro -------------------------------------------------------------- */
+#define MMC_PFC_PINS(name, args...)             SH_PFC_PINS(name, args)
+#define MMC_PFC_CTRL(name, clk, cmd)            SH_PFC_MUX2(name, clk, cmd)
+#define MMC_PFC_DAT1(name, d0)                  SH_PFC_MUX1(name, d0)
+#define MMC_PFC_DAT4(name, d0, d1, d2, d3)      SH_PFC_MUX4(name, d0, d1, d2, d3)
+#define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)      \
+                        SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
+
+/* - MMC -------------------------------------------------------------------- */
+MMC_PFC_PINS(mmc_ctrl,          RCAR_GP_PIN(1, 5),      RCAR_GP_PIN(1, 6));
+MMC_PFC_CTRL(mmc_ctrl,          MMC_CLK,                MMC_CMD);
+MMC_PFC_PINS(mmc_data1,         RCAR_GP_PIN(1, 7));
+MMC_PFC_DAT1(mmc_data1,         MMC_D0);
+MMC_PFC_PINS(mmc_data4,         RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(2, 8),
+                                RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6));
+MMC_PFC_DAT4(mmc_data4,         MMC_D0,                 MMC_D1,
+                                MMC_D2,                 MMC_D3);
+MMC_PFC_PINS(mmc_data8,         RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(2, 8),
+                                RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6),
+                                RCAR_GP_PIN(1, 4),      RCAR_GP_PIN(1, 0),
+                                RCAR_GP_PIN(0, 30),     RCAR_GP_PIN(0, 31));
+MMC_PFC_DAT8(mmc_data8,         MMC_D0,                 MMC_D1,
+                                MMC_D2,                 MMC_D3,
+                                MMC_D4,                 MMC_D5,
+                                MMC_D6,                 MMC_D7);
+
+/* - SCIF CLOCK ------------------------------------------------------------- */
+SCIF_PFC_PIN(scif_clk,          RCAR_GP_PIN(1, 16));
+SCIF_PFC_CLK(scif_clk,          SCIF_CLK);
+
+/* - SCIF0 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif0_data_a,      RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 18));
+SCIF_PFC_DAT(scif0_data_a,      TX0_A,                  RX0_A);
+SCIF_PFC_PIN(scif0_data_b,      RCAR_GP_PIN(2, 3),      RCAR_GP_PIN(2, 2));
+SCIF_PFC_DAT(scif0_data_b,      TX0_B,                  RX0_B);
+SCIF_PFC_PIN(scif0_data_c,      RCAR_GP_PIN(4, 0),      RCAR_GP_PIN(3, 31));
+SCIF_PFC_DAT(scif0_data_c,      TX0_C,                  RX0_C);
+SCIF_PFC_PIN(scif0_data_d,      RCAR_GP_PIN(3, 6),      RCAR_GP_PIN(3, 1));
+SCIF_PFC_DAT(scif0_data_d,      TX0_D,                  RX0_D);
+SCIF_PFC_PIN(scif0_ctrl,        RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
+SCIF_PFC_CTR(scif0_ctrl,        CTS0,                   RTS0);
+SCIF_PFC_PIN(scif0_clk,         RCAR_GP_PIN(1, 19));
+SCIF_PFC_CLK(scif0_clk,         SCK0);
+
+/* - SCIF1 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif1_data_a,      RCAR_GP_PIN(4, 0),      RCAR_GP_PIN(4, 1));
+SCIF_PFC_DAT(scif1_data_a,      TX1_A,                  RX1_A);
+SCIF_PFC_PIN(scif1_data_b,      RCAR_GP_PIN(2, 24),     RCAR_GP_PIN(2, 25));
+SCIF_PFC_DAT(scif1_data_b,      TX1_B,                  RX1_B);
+SCIF_PFC_PIN(scif1_data_c,      RCAR_GP_PIN(3, 22),     RCAR_GP_PIN(3, 21));
+SCIF_PFC_DAT(scif1_data_c,      TX1_C,                  RX1_C);
+SCIF_PFC_PIN(scif1_data_d,      RCAR_GP_PIN(1, 30),     RCAR_GP_PIN(1, 31));
+SCIF_PFC_DAT(scif1_data_d,      TX1_D,                  RX1_D);
+SCIF_PFC_PIN(scif1_ctrl_a,      RCAR_GP_PIN(4, 3),      RCAR_GP_PIN(4, 4));
+SCIF_PFC_CTR(scif1_ctrl_a,      CTS1_A,                 RTS1_A);
+SCIF_PFC_PIN(scif1_ctrl_c,      RCAR_GP_PIN(3, 23),     RCAR_GP_PIN(3, 19));
+SCIF_PFC_CTR(scif1_ctrl_c,      CTS1_C,                 RTS1_C);
+SCIF_PFC_PIN(scif1_clk_a,       RCAR_GP_PIN(4, 2));
+SCIF_PFC_CLK(scif1_clk_a,       SCK1_A);
+SCIF_PFC_PIN(scif1_clk_c,       RCAR_GP_PIN(3, 20));
+SCIF_PFC_CLK(scif1_clk_c,       SCK1_C);
+
+/* - SCIF2 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif2_data_a,      RCAR_GP_PIN(2, 26),     RCAR_GP_PIN(2, 27));
+SCIF_PFC_DAT(scif2_data_a,      TX2_A,                  RX2_A);
+SCIF_PFC_PIN(scif2_data_b,      RCAR_GP_PIN(0, 29),     RCAR_GP_PIN(0, 28));
+SCIF_PFC_DAT(scif2_data_b,      TX2_B,                  RX2_B);
+SCIF_PFC_PIN(scif2_data_c,      RCAR_GP_PIN(4, 13),     RCAR_GP_PIN(4, 14));
+SCIF_PFC_DAT(scif2_data_c,      TX2_C,                  RX2_C);
+SCIF_PFC_PIN(scif2_data_d,      RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16));
+SCIF_PFC_DAT(scif2_data_d,      TX2_D,                  RX2_D);
+SCIF_PFC_PIN(scif2_data_e,      RCAR_GP_PIN(0, 3),      RCAR_GP_PIN(0, 4));
+SCIF_PFC_DAT(scif2_data_e,      TX2_E,                  RX2_E);
+SCIF_PFC_PIN(scif2_clk_a,       RCAR_GP_PIN(3, 9));
+SCIF_PFC_CLK(scif2_clk_a,       SCK2_A);
+SCIF_PFC_PIN(scif2_clk_b,       PIN_NUMBER(3, 20));
+SCIF_PFC_CLK(scif2_clk_b,       SCK2_B);
+SCIF_PFC_PIN(scif2_clk_c,       RCAR_GP_PIN(4, 12));
+SCIF_PFC_CLK(scif2_clk_c,       SCK2_C);
+
+/* - SCIF3 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif3_data_a,      RCAR_GP_PIN(1, 10),     RCAR_GP_PIN(1, 9));
+SCIF_PFC_DAT(scif3_data_a,      TX3_A,                  RX3_A);
+SCIF_PFC_PIN(scif3_data_b,      RCAR_GP_PIN(3, 28),     RCAR_GP_PIN(3, 27));
+SCIF_PFC_DAT(scif3_data_b,      TX3_B,                  RX3_B);
+SCIF_PFC_PIN(scif3_data_c,      RCAR_GP_PIN(1, 3),      RCAR_GP_PIN(0, 31));
+SCIF_PFC_DAT(scif3_data_c,      TX3_C,                  RX3_C);
+SCIF_PFC_PIN(scif3_data_d,      RCAR_GP_PIN(3, 30),     RCAR_GP_PIN(3, 29));
+SCIF_PFC_DAT(scif3_data_d,      TX3_D,                  RX3_D);
+
+/* - SCIF4 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif4_data_a,      RCAR_GP_PIN(2, 5),      RCAR_GP_PIN(2, 4));
+SCIF_PFC_DAT(scif4_data_a,      TX4_A,                  RX4_A);
+SCIF_PFC_PIN(scif4_data_b,      RCAR_GP_PIN(3, 26),     RCAR_GP_PIN(3, 25));
+SCIF_PFC_DAT(scif4_data_b,      TX4_B,                  RX4_B);
+SCIF_PFC_PIN(scif4_data_c,      RCAR_GP_PIN(3, 0),      RCAR_GP_PIN(2, 31));
+SCIF_PFC_DAT(scif4_data_c,      TX4_C,                  RX4_C);
+
+/* - SCIF5 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif5_data_a,      RCAR_GP_PIN(3, 17),     RCAR_GP_PIN(3, 18));
+SCIF_PFC_DAT(scif5_data_a,      TX5_A,                  RX5_A);
+SCIF_PFC_PIN(scif5_data_b,      RCAR_GP_PIN(1, 15),     RCAR_GP_PIN(1, 14));
+SCIF_PFC_DAT(scif5_data_b,      TX5_B,                  RX5_B);
+
+/* - SDHI macro ------------------------------------------------------------- */
+#define SDHI_PFC_PINS(name, args...)            SH_PFC_PINS(name, args)
+#define SDHI_PFC_DAT1(name, d0)                 SH_PFC_MUX1(name, d0)
+#define SDHI_PFC_DAT4(name, d0, d1, d2, d3)     SH_PFC_MUX4(name, d0, d1, d2, d3)
+#define SDHI_PFC_CTRL(name, clk, cmd)           SH_PFC_MUX2(name, clk, cmd)
+#define SDHI_PFC_CDPN(name, cd)                 SH_PFC_MUX1(name, cd)
+#define SDHI_PFC_WPPN(name, wp)                 SH_PFC_MUX1(name, wp)
+
+/* - SDHI0 ------------------------------------------------------------------ */
+SDHI_PFC_PINS(sdhi0_cd,         RCAR_GP_PIN(3, 17));
+SDHI_PFC_CDPN(sdhi0_cd,         SD0_CD);
+SDHI_PFC_PINS(sdhi0_ctrl,       RCAR_GP_PIN(3, 11),     RCAR_GP_PIN(3, 12));
+SDHI_PFC_CTRL(sdhi0_ctrl,       SD0_CLK,                SD0_CMD);
+SDHI_PFC_PINS(sdhi0_data1,      RCAR_GP_PIN(3, 13));
+SDHI_PFC_DAT1(sdhi0_data1,      SD0_DAT0);
+SDHI_PFC_PINS(sdhi0_data4,      RCAR_GP_PIN(3, 13),     RCAR_GP_PIN(3, 14),
+                                RCAR_GP_PIN(3, 15),     RCAR_GP_PIN(3, 16));
+SDHI_PFC_DAT4(sdhi0_data4,      SD0_DAT0,               SD0_DAT1,
+                                SD0_DAT2,               SD0_DAT3);
+SDHI_PFC_PINS(sdhi0_wp,         RCAR_GP_PIN(3, 18));
+SDHI_PFC_WPPN(sdhi0_wp,         SD0_WP);
+
+/* - SDHI1 ------------------------------------------------------------------ */
+SDHI_PFC_PINS(sdhi1_cd_a,       RCAR_GP_PIN(0, 30));
+SDHI_PFC_CDPN(sdhi1_cd_a,       SD1_CD_A);
+SDHI_PFC_PINS(sdhi1_cd_b,       RCAR_GP_PIN(2, 24));
+SDHI_PFC_CDPN(sdhi1_cd_b,       SD1_CD_B);
+SDHI_PFC_PINS(sdhi1_ctrl_a,     RCAR_GP_PIN(1, 5),      RCAR_GP_PIN(1, 6));
+SDHI_PFC_CTRL(sdhi1_ctrl_a,     SD1_CLK_A,              SD1_CMD_A);
+SDHI_PFC_PINS(sdhi1_ctrl_b,     RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 16));
+SDHI_PFC_CTRL(sdhi1_ctrl_b,     SD1_CLK_B,              SD1_CMD_B);
+SDHI_PFC_PINS(sdhi1_data1_a,    RCAR_GP_PIN(1, 7));
+SDHI_PFC_DAT1(sdhi1_data1_a,    SD1_DAT0_A);
+SDHI_PFC_PINS(sdhi1_data1_b,    RCAR_GP_PIN(1, 18));
+SDHI_PFC_DAT1(sdhi1_data1_b,    SD1_DAT0_B);
+SDHI_PFC_PINS(sdhi1_data4_a,    RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(1, 8),
+                                RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6));
+SDHI_PFC_DAT4(sdhi1_data4_a,    SD1_DAT0_A,             SD1_DAT1_A,
+                                SD1_DAT2_A,             SD1_DAT3_A);
+SDHI_PFC_PINS(sdhi1_data4_b,    RCAR_GP_PIN(1, 18),     RCAR_GP_PIN(1, 19),
+                                RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
+SDHI_PFC_DAT4(sdhi1_data4_b,    SD1_DAT0_B,             SD1_DAT1_B,
+                                SD1_DAT2_B,             SD1_DAT3_B);
+SDHI_PFC_PINS(sdhi1_wp_a,       RCAR_GP_PIN(0, 31));
+SDHI_PFC_WPPN(sdhi1_wp_a,       SD1_WP_A);
+SDHI_PFC_PINS(sdhi1_wp_b,       RCAR_GP_PIN(2, 25));
+SDHI_PFC_WPPN(sdhi1_wp_b,       SD1_WP_B);
+
+/* - SDH2 ------------------------------------------------------------------- */
+SDHI_PFC_PINS(sdhi2_cd_a,       RCAR_GP_PIN(4, 23));
+SDHI_PFC_CDPN(sdhi2_cd_a,       SD2_CD_A);
+SDHI_PFC_PINS(sdhi2_cd_b,       RCAR_GP_PIN(3, 27));
+SDHI_PFC_CDPN(sdhi2_cd_b,       SD2_CD_B);
+SDHI_PFC_PINS(sdhi2_ctrl_a,     RCAR_GP_PIN(4, 17),     RCAR_GP_PIN(4, 18));
+SDHI_PFC_CTRL(sdhi2_ctrl_a,     SD2_CLK_A,              SD2_CMD_A);
+SDHI_PFC_PINS(sdhi2_ctrl_b,     RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6));
+SDHI_PFC_CTRL(sdhi2_ctrl_b,     SD2_CLK_B,              SD2_CMD_B);
+SDHI_PFC_PINS(sdhi2_data1_a,    RCAR_GP_PIN(4, 19));
+SDHI_PFC_DAT1(sdhi2_data1_a,    SD2_DAT0_A);
+SDHI_PFC_PINS(sdhi2_data1_b,    RCAR_GP_PIN(4, 7));
+SDHI_PFC_DAT1(sdhi2_data1_b,    SD2_DAT0_B);
+SDHI_PFC_PINS(sdhi2_data4_a,    RCAR_GP_PIN(4, 19),     RCAR_GP_PIN(4, 20),
+                                RCAR_GP_PIN(4, 21),     RCAR_GP_PIN(4, 22));
+SDHI_PFC_DAT4(sdhi2_data4_a,    SD2_DAT0_A,             SD2_DAT1_A,
+                                SD2_DAT2_A,             SD2_DAT3_A);
+SDHI_PFC_PINS(sdhi2_data4_b,    RCAR_GP_PIN(4, 7),      RCAR_GP_PIN(4, 8),
+                                RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 26));
+SDHI_PFC_DAT4(sdhi2_data4_b,    SD2_DAT0_B,             SD2_DAT1_B,
+                                SD2_DAT2_B,             SD2_DAT3_B);
+SDHI_PFC_PINS(sdhi2_wp_a,       RCAR_GP_PIN(4, 24));
+SDHI_PFC_WPPN(sdhi2_wp_a,       SD2_WP_A);
+SDHI_PFC_PINS(sdhi2_wp_b,       RCAR_GP_PIN(3, 28));
+SDHI_PFC_WPPN(sdhi2_wp_b,       SD2_WP_B);
+
+/* - USB0 ------------------------------------------------------------------- */
+SH_PFC_PINS(usb0,               RCAR_GP_PIN(0, 1));
+SH_PFC_MUX1(usb0,               PENC0);
+SH_PFC_PINS(usb0_ovc,           RCAR_GP_PIN(0, 3));
+SH_PFC_MUX1(usb0_ovc,           USB_OVC0);
+
+/* - USB1 ------------------------------------------------------------------- */
+SH_PFC_PINS(usb1,               RCAR_GP_PIN(0, 2));
+SH_PFC_MUX1(usb1,               PENC1);
+SH_PFC_PINS(usb1_ovc,           RCAR_GP_PIN(0, 4));
+SH_PFC_MUX1(usb1_ovc,           USB_OVC1);
+
+/* - VIN macros ------------------------------------------------------------- */
+#define VIN_PFC_PINS(name, args...)             SH_PFC_PINS(name, args)
+#define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)      \
+        SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
+#define VIN_PFC_CLK(name, clk)                  SH_PFC_MUX1(name, clk)
+#define VIN_PFC_SYNC(name, hsync, vsync)        SH_PFC_MUX2(name, hsync, vsync)
+
+/* - VIN0 ------------------------------------------------------------------- */
+VIN_PFC_PINS(vin0_data8,        RCAR_GP_PIN(3, 29),     RCAR_GP_PIN(3, 30),
+                                RCAR_GP_PIN(3, 31),     RCAR_GP_PIN(4, 0),
+                                RCAR_GP_PIN(4, 1),      RCAR_GP_PIN(4, 2),
+                                RCAR_GP_PIN(4, 3),      RCAR_GP_PIN(4, 4));
+VIN_PFC_DAT8(vin0_data8,        VI0_DATA0_VI0_B0,       VI0_DATA1_VI0_B1,
+                                VI0_DATA2_VI0_B2,       VI0_DATA3_VI0_B3,
+                                VI0_DATA4_VI0_B4,       VI0_DATA5_VI0_B5,
+                                VI0_DATA6_VI0_G0,       VI0_DATA7_VI0_G1);
+VIN_PFC_PINS(vin0_clk,          RCAR_GP_PIN(3, 24));
+VIN_PFC_CLK(vin0_clk,           VI0_CLK);
+VIN_PFC_PINS(vin0_sync,         RCAR_GP_PIN(3, 27),     RCAR_GP_PIN(3, 28));
+VIN_PFC_SYNC(vin0_sync,         VI0_HSYNC,              VI0_VSYNC);
+/* - VIN1 ------------------------------------------------------------------- */
+VIN_PFC_PINS(vin1_data8,        RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 26),
+                                RCAR_GP_PIN(3, 27),     RCAR_GP_PIN(3, 28),
+                                RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6),
+                                RCAR_GP_PIN(4, 7),      RCAR_GP_PIN(4, 8));
+VIN_PFC_DAT8(vin1_data8,        VI1_DATA0,              VI1_DATA1,
+                                VI1_DATA2,              VI1_DATA3,
+                                VI1_DATA4,              VI1_DATA5,
+                                VI1_DATA6,              VI1_DATA7);
+VIN_PFC_PINS(vin1_clk,          RCAR_GP_PIN(4, 9));
+VIN_PFC_CLK(vin1_clk,           VI1_CLK);
+VIN_PFC_PINS(vin1_sync,         RCAR_GP_PIN(3, 21),     RCAR_GP_PIN(3, 22));
+VIN_PFC_SYNC(vin1_sync,         VI1_HSYNC,              VI1_VSYNC);
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(ether_rmii),
+        SH_PFC_PIN_GROUP(ether_link),
+        SH_PFC_PIN_GROUP(ether_magic),
+        SH_PFC_PIN_GROUP(hscif0_data_a),
+        SH_PFC_PIN_GROUP(hscif0_data_b),
+        SH_PFC_PIN_GROUP(hscif0_ctrl_a),
+        SH_PFC_PIN_GROUP(hscif0_ctrl_b),
+        SH_PFC_PIN_GROUP(hscif0_clk),
+        SH_PFC_PIN_GROUP(hscif1_data_a),
+        SH_PFC_PIN_GROUP(hscif1_data_b),
+        SH_PFC_PIN_GROUP(hscif1_ctrl_a),
+        SH_PFC_PIN_GROUP(hscif1_ctrl_b),
+        SH_PFC_PIN_GROUP(hscif1_clk_a),
+        SH_PFC_PIN_GROUP(hscif1_clk_b),
+        SH_PFC_PIN_GROUP(hspi0_a),
+        SH_PFC_PIN_GROUP(hspi0_b),
+        SH_PFC_PIN_GROUP(hspi1_a),
+        SH_PFC_PIN_GROUP(hspi1_b),
+        SH_PFC_PIN_GROUP(hspi2_a),
+        SH_PFC_PIN_GROUP(hspi2_b),
+        SH_PFC_PIN_GROUP(i2c1_a),
+        SH_PFC_PIN_GROUP(i2c1_b),
+        SH_PFC_PIN_GROUP(i2c2_a),
+        SH_PFC_PIN_GROUP(i2c2_b),
+        SH_PFC_PIN_GROUP(i2c2_c),
+        SH_PFC_PIN_GROUP(i2c3_a),
+        SH_PFC_PIN_GROUP(i2c3_b),
+        SH_PFC_PIN_GROUP(i2c3_c),
+        SH_PFC_PIN_GROUP(mmc_ctrl),
+        SH_PFC_PIN_GROUP(mmc_data1),
+        SH_PFC_PIN_GROUP(mmc_data4),
+        SH_PFC_PIN_GROUP(mmc_data8),
+        SH_PFC_PIN_GROUP(scif_clk),
+        SH_PFC_PIN_GROUP(scif0_data_a),
+        SH_PFC_PIN_GROUP(scif0_data_b),
+        SH_PFC_PIN_GROUP(scif0_data_c),
+        SH_PFC_PIN_GROUP(scif0_data_d),
+        SH_PFC_PIN_GROUP(scif0_ctrl),
+        SH_PFC_PIN_GROUP(scif0_clk),
+        SH_PFC_PIN_GROUP(scif1_data_a),
+        SH_PFC_PIN_GROUP(scif1_data_b),
+        SH_PFC_PIN_GROUP(scif1_data_c),
+        SH_PFC_PIN_GROUP(scif1_data_d),
+        SH_PFC_PIN_GROUP(scif1_ctrl_a),
+        SH_PFC_PIN_GROUP(scif1_ctrl_c),
+        SH_PFC_PIN_GROUP(scif1_clk_a),
+        SH_PFC_PIN_GROUP(scif1_clk_c),
+        SH_PFC_PIN_GROUP(scif2_data_a),
+        SH_PFC_PIN_GROUP(scif2_data_b),
+        SH_PFC_PIN_GROUP(scif2_data_c),
+        SH_PFC_PIN_GROUP(scif2_data_d),
+        SH_PFC_PIN_GROUP(scif2_data_e),
+        SH_PFC_PIN_GROUP(scif2_clk_a),
+        SH_PFC_PIN_GROUP(scif2_clk_b),
+        SH_PFC_PIN_GROUP(scif2_clk_c),
+        SH_PFC_PIN_GROUP(scif3_data_a),
+        SH_PFC_PIN_GROUP(scif3_data_b),
+        SH_PFC_PIN_GROUP(scif3_data_c),
+        SH_PFC_PIN_GROUP(scif3_data_d),
+        SH_PFC_PIN_GROUP(scif4_data_a),
+        SH_PFC_PIN_GROUP(scif4_data_b),
+        SH_PFC_PIN_GROUP(scif4_data_c),
+        SH_PFC_PIN_GROUP(scif5_data_a),
+        SH_PFC_PIN_GROUP(scif5_data_b),
+        SH_PFC_PIN_GROUP(sdhi0_cd),
+        SH_PFC_PIN_GROUP(sdhi0_ctrl),
+        SH_PFC_PIN_GROUP(sdhi0_data1),
+        SH_PFC_PIN_GROUP(sdhi0_data4),
+        SH_PFC_PIN_GROUP(sdhi0_wp),
+        SH_PFC_PIN_GROUP(sdhi1_cd_a),
+        SH_PFC_PIN_GROUP(sdhi1_cd_b),
+        SH_PFC_PIN_GROUP(sdhi1_ctrl_a),
+        SH_PFC_PIN_GROUP(sdhi1_ctrl_b),
+        SH_PFC_PIN_GROUP(sdhi1_data1_a),
+        SH_PFC_PIN_GROUP(sdhi1_data1_b),
+        SH_PFC_PIN_GROUP(sdhi1_data4_a),
+        SH_PFC_PIN_GROUP(sdhi1_data4_b),
+        SH_PFC_PIN_GROUP(sdhi1_wp_a),
+        SH_PFC_PIN_GROUP(sdhi1_wp_b),
+        SH_PFC_PIN_GROUP(sdhi2_cd_a),
+        SH_PFC_PIN_GROUP(sdhi2_cd_b),
+        SH_PFC_PIN_GROUP(sdhi2_ctrl_a),
+        SH_PFC_PIN_GROUP(sdhi2_ctrl_b),
+        SH_PFC_PIN_GROUP(sdhi2_data1_a),
+        SH_PFC_PIN_GROUP(sdhi2_data1_b),
+        SH_PFC_PIN_GROUP(sdhi2_data4_a),
+        SH_PFC_PIN_GROUP(sdhi2_data4_b),
+        SH_PFC_PIN_GROUP(sdhi2_wp_a),
+        SH_PFC_PIN_GROUP(sdhi2_wp_b),
+        SH_PFC_PIN_GROUP(usb0),
+        SH_PFC_PIN_GROUP(usb0_ovc),
+        SH_PFC_PIN_GROUP(usb1),
+        SH_PFC_PIN_GROUP(usb1_ovc),
+        SH_PFC_PIN_GROUP(vin0_data8),
+        SH_PFC_PIN_GROUP(vin0_clk),
+        SH_PFC_PIN_GROUP(vin0_sync),
+        SH_PFC_PIN_GROUP(vin1_data8),
+        SH_PFC_PIN_GROUP(vin1_clk),
+        SH_PFC_PIN_GROUP(vin1_sync),
+};
+
+static const char * const ether_groups[] = {
+        "ether_rmii",
+        "ether_link",
+        "ether_magic",
+};
+
+static const char * const hscif0_groups[] = {
+        "hscif0_data_a",
+        "hscif0_data_b",
+        "hscif0_ctrl_a",
+        "hscif0_ctrl_b",
+        "hscif0_clk",
+};
+
+static const char * const hscif1_groups[] = {
+        "hscif1_data_a",
+        "hscif1_data_b",
+        "hscif1_ctrl_a",
+        "hscif1_ctrl_b",
+        "hscif1_clk_a",
+        "hscif1_clk_b",
+};
+
+static const char * const hspi0_groups[] = {
+        "hspi0_a",
+        "hspi0_b",
+};
+
+static const char * const hspi1_groups[] = {
+        "hspi1_a",
+        "hspi1_b",
+};
+
+static const char * const hspi2_groups[] = {
+        "hspi2_a",
+        "hspi2_b",
+};
+
+static const char * const i2c1_groups[] = {
+        "i2c1_a",
+        "i2c1_b",
+};
+
+static const char * const i2c2_groups[] = {
+        "i2c2_a",
+        "i2c2_b",
+        "i2c2_c",
+};
+
+static const char * const i2c3_groups[] = {
+        "i2c3_a",
+        "i2c3_b",
+        "i2c3_c",
+};
+
+static const char * const mmc_groups[] = {
+        "mmc_ctrl",
+        "mmc_data1",
+        "mmc_data4",
+        "mmc_data8",
+};
+
+static const char * const scif_clk_groups[] = {
+        "scif_clk",
+};
+
+static const char * const scif0_groups[] = {
+        "scif0_data_a",
+        "scif0_data_b",
+        "scif0_data_c",
+        "scif0_data_d",
+        "scif0_ctrl",
+        "scif0_clk",
+};
+
+static const char * const scif1_groups[] = {
+        "scif1_data_a",
+        "scif1_data_b",
+        "scif1_data_c",
+        "scif1_data_d",
+        "scif1_ctrl_a",
+        "scif1_ctrl_c",
+        "scif1_clk_a",
+        "scif1_clk_c",
+};
+
+static const char * const scif2_groups[] = {
+        "scif2_data_a",
+        "scif2_data_b",
+        "scif2_data_c",
+        "scif2_data_d",
+        "scif2_data_e",
+        "scif2_clk_a",
+        "scif2_clk_b",
+        "scif2_clk_c",
+};
+
+static const char * const scif3_groups[] = {
+        "scif3_data_a",
+        "scif3_data_b",
+        "scif3_data_c",
+        "scif3_data_d",
+};
+
+static const char * const scif4_groups[] = {
+        "scif4_data_a",
+        "scif4_data_b",
+        "scif4_data_c",
+};
+
+static const char * const scif5_groups[] = {
+        "scif5_data_a",
+        "scif5_data_b",
+};
+
+
+static const char * const sdhi0_groups[] = {
+        "sdhi0_cd",
+        "sdhi0_ctrl",
+        "sdhi0_data1",
+        "sdhi0_data4",
+        "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+        "sdhi1_cd_a",
+        "sdhi1_cd_b",
+        "sdhi1_ctrl_a",
+        "sdhi1_ctrl_b",
+        "sdhi1_data1_a",
+        "sdhi1_data1_b",
+        "sdhi1_data4_a",
+        "sdhi1_data4_b",
+        "sdhi1_wp_a",
+        "sdhi1_wp_b",
+};
+
+static const char * const sdhi2_groups[] = {
+        "sdhi2_cd_a",
+        "sdhi2_cd_b",
+        "sdhi2_ctrl_a",
+        "sdhi2_ctrl_b",
+        "sdhi2_data1_a",
+        "sdhi2_data1_b",
+        "sdhi2_data4_a",
+        "sdhi2_data4_b",
+        "sdhi2_wp_a",
+        "sdhi2_wp_b",
+};
+
+static const char * const usb0_groups[] = {
+        "usb0",
+        "usb0_ovc",
+};
+
+static const char * const usb1_groups[] = {
+        "usb1",
+        "usb1_ovc",
+};
+
+static const char * const vin0_groups[] = {
+        "vin0_data8",
+        "vin0_clk",
+        "vin0_sync",
+};
+
+static const char * const vin1_groups[] = {
+        "vin1_data8",
+        "vin1_clk",
+        "vin1_sync",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(ether),
+        SH_PFC_FUNCTION(hscif0),
+        SH_PFC_FUNCTION(hscif1),
+        SH_PFC_FUNCTION(hspi0),
+        SH_PFC_FUNCTION(hspi1),
+        SH_PFC_FUNCTION(hspi2),
+        SH_PFC_FUNCTION(i2c1),
+        SH_PFC_FUNCTION(i2c2),
+        SH_PFC_FUNCTION(i2c3),
+        SH_PFC_FUNCTION(mmc),
+        SH_PFC_FUNCTION(scif_clk),
+        SH_PFC_FUNCTION(scif0),
+        SH_PFC_FUNCTION(scif1),
+        SH_PFC_FUNCTION(scif2),
+        SH_PFC_FUNCTION(scif3),
+        SH_PFC_FUNCTION(scif4),
+        SH_PFC_FUNCTION(scif5),
+        SH_PFC_FUNCTION(sdhi0),
+        SH_PFC_FUNCTION(sdhi1),
+        SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(usb0),
+        SH_PFC_FUNCTION(usb1),
+        SH_PFC_FUNCTION(vin0),
+        SH_PFC_FUNCTION(vin1),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
+                GP_0_31_FN,     FN_IP1_14_11,
+                GP_0_30_FN,     FN_IP1_10_8,
+                GP_0_29_FN,     FN_IP1_7_5,
+                GP_0_28_FN,     FN_IP1_4_2,
+                GP_0_27_FN,     FN_IP1_1,
+                GP_0_26_FN,     FN_IP1_0,
+                GP_0_25_FN,     FN_IP0_30,
+                GP_0_24_FN,     FN_IP0_29,
+                GP_0_23_FN,     FN_IP0_28,
+                GP_0_22_FN,     FN_IP0_27,
+                GP_0_21_FN,     FN_IP0_26,
+                GP_0_20_FN,     FN_IP0_25,
+                GP_0_19_FN,     FN_IP0_24,
+                GP_0_18_FN,     FN_IP0_23,
+                GP_0_17_FN,     FN_IP0_22,
+                GP_0_16_FN,     FN_IP0_21,
+                GP_0_15_FN,     FN_IP0_20,
+                GP_0_14_FN,     FN_IP0_19,
+                GP_0_13_FN,     FN_IP0_18,
+                GP_0_12_FN,     FN_IP0_17,
+                GP_0_11_FN,     FN_IP0_16,
+                GP_0_10_FN,     FN_IP0_15,
+                GP_0_9_FN,      FN_A3,
+                GP_0_8_FN,      FN_A2,
+                GP_0_7_FN,      FN_A1,
+                GP_0_6_FN,      FN_IP0_14_12,
+                GP_0_5_FN,      FN_IP0_11_8,
+                GP_0_4_FN,      FN_IP0_7_5,
+                GP_0_3_FN,      FN_IP0_4_2,
+                GP_0_2_FN,      FN_PENC1,
+                GP_0_1_FN,      FN_PENC0,
+                GP_0_0_FN,      FN_IP0_1_0 }
+        },
+        { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
+                GP_1_31_FN,     FN_IP4_6_4,
+                GP_1_30_FN,     FN_IP4_3_1,
+                GP_1_29_FN,     FN_IP4_0,
+                GP_1_28_FN,     FN_IP3_31,
+                GP_1_27_FN,     FN_IP3_30,
+                GP_1_26_FN,     FN_IP3_29,
+                GP_1_25_FN,     FN_IP3_28,
+                GP_1_24_FN,     FN_IP3_27,
+                GP_1_23_FN,     FN_IP3_26_24,
+                GP_1_22_FN,     FN_IP3_23_21,
+                GP_1_21_FN,     FN_IP3_20_19,
+                GP_1_20_FN,     FN_IP3_18_16,
+                GP_1_19_FN,     FN_IP3_15_13,
+                GP_1_18_FN,     FN_IP3_12_10,
+                GP_1_17_FN,     FN_IP3_9_8,
+                GP_1_16_FN,     FN_IP3_7_5,
+                GP_1_15_FN,     FN_IP3_4_2,
+                GP_1_14_FN,     FN_IP3_1_0,
+                GP_1_13_FN,     FN_IP2_31,
+                GP_1_12_FN,     FN_IP2_30,
+                GP_1_11_FN,     FN_IP2_17,
+                GP_1_10_FN,     FN_IP2_16_14,
+                GP_1_9_FN,      FN_IP2_13_12,
+                GP_1_8_FN,      FN_IP2_11_9,
+                GP_1_7_FN,      FN_IP2_8_6,
+                GP_1_6_FN,      FN_IP2_5_3,
+                GP_1_5_FN,      FN_IP2_2_0,
+                GP_1_4_FN,      FN_IP1_29_28,
+                GP_1_3_FN,      FN_IP1_27_25,
+                GP_1_2_FN,      FN_IP1_24,
+                GP_1_1_FN,      FN_WE0,
+                GP_1_0_FN,      FN_IP1_23_21 }
+        },
+        { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
+                GP_2_31_FN,     FN_IP6_7,
+                GP_2_30_FN,     FN_IP6_6_5,
+                GP_2_29_FN,     FN_IP6_4_2,
+                GP_2_28_FN,     FN_IP6_1_0,
+                GP_2_27_FN,     FN_IP5_30_29,
+                GP_2_26_FN,     FN_IP5_28_26,
+                GP_2_25_FN,     FN_IP5_25_23,
+                GP_2_24_FN,     FN_IP5_22_21,
+                GP_2_23_FN,     FN_AUDIO_CLKB,
+                GP_2_22_FN,     FN_AUDIO_CLKA,
+                GP_2_21_FN,     FN_IP5_20_18,
+                GP_2_20_FN,     FN_IP5_17_15,
+                GP_2_19_FN,     FN_IP5_14_13,
+                GP_2_18_FN,     FN_IP5_12,
+                GP_2_17_FN,     FN_IP5_11_10,
+                GP_2_16_FN,     FN_IP5_9_8,
+                GP_2_15_FN,     FN_IP5_7,
+                GP_2_14_FN,     FN_IP5_6,
+                GP_2_13_FN,     FN_IP5_5_4,
+                GP_2_12_FN,     FN_IP5_3_2,
+                GP_2_11_FN,     FN_IP5_1_0,
+                GP_2_10_FN,     FN_IP4_30_29,
+                GP_2_9_FN,      FN_IP4_28_27,
+                GP_2_8_FN,      FN_IP4_26_25,
+                GP_2_7_FN,      FN_IP4_24_21,
+                GP_2_6_FN,      FN_IP4_20_17,
+                GP_2_5_FN,      FN_IP4_16_15,
+                GP_2_4_FN,      FN_IP4_14_13,
+                GP_2_3_FN,      FN_IP4_12_11,
+                GP_2_2_FN,      FN_IP4_10_9,
+                GP_2_1_FN,      FN_IP4_8,
+                GP_2_0_FN,      FN_IP4_7 }
+        },
+        { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
+                GP_3_31_FN,     FN_IP8_10_9,
+                GP_3_30_FN,     FN_IP8_8_6,
+                GP_3_29_FN,     FN_IP8_5_3,
+                GP_3_28_FN,     FN_IP8_2_0,
+                GP_3_27_FN,     FN_IP7_31_29,
+                GP_3_26_FN,     FN_IP7_28_25,
+                GP_3_25_FN,     FN_IP7_24_22,
+                GP_3_24_FN,     FN_IP7_21,
+                GP_3_23_FN,     FN_IP7_20_18,
+                GP_3_22_FN,     FN_IP7_17_15,
+                GP_3_21_FN,     FN_IP7_14_12,
+                GP_3_20_FN,     FN_IP7_11_9,
+                GP_3_19_FN,     FN_IP7_8_6,
+                GP_3_18_FN,     FN_IP7_5_4,
+                GP_3_17_FN,     FN_IP7_3_2,
+                GP_3_16_FN,     FN_IP7_1_0,
+                GP_3_15_FN,     FN_IP6_31_30,
+                GP_3_14_FN,     FN_IP6_29_28,
+                GP_3_13_FN,     FN_IP6_27_26,
+                GP_3_12_FN,     FN_IP6_25_24,
+                GP_3_11_FN,     FN_IP6_23_22,
+                GP_3_10_FN,     FN_IP6_21,
+                GP_3_9_FN,      FN_IP6_20_19,
+                GP_3_8_FN,      FN_IP6_18_17,
+                GP_3_7_FN,      FN_IP6_16,
+                GP_3_6_FN,      FN_IP6_15_14,
+                GP_3_5_FN,      FN_IP6_13,
+                GP_3_4_FN,      FN_IP6_12_11,
+                GP_3_3_FN,      FN_IP6_10,
+                GP_3_2_FN,      FN_SSI_SCK34,
+                GP_3_1_FN,      FN_IP6_9,
+                GP_3_0_FN,      FN_IP6_8 }
+        },
+        { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                GP_4_26_FN,     FN_AVS2,
+                GP_4_25_FN,     FN_AVS1,
+                GP_4_24_FN,     FN_IP10_24_22,
+                GP_4_23_FN,     FN_IP10_21_19,
+                GP_4_22_FN,     FN_IP10_18_16,
+                GP_4_21_FN,     FN_IP10_15_13,
+                GP_4_20_FN,     FN_IP10_12_9,
+                GP_4_19_FN,     FN_IP10_8_6,
+                GP_4_18_FN,     FN_IP10_5_3,
+                GP_4_17_FN,     FN_IP10_2_0,
+                GP_4_16_FN,     FN_IP9_29_27,
+                GP_4_15_FN,     FN_IP9_26_24,
+                GP_4_14_FN,     FN_IP9_23_21,
+                GP_4_13_FN,     FN_IP9_20_18,
+                GP_4_12_FN,     FN_IP9_17_15,
+                GP_4_11_FN,     FN_IP9_14_12,
+                GP_4_10_FN,     FN_IP9_11_9,
+                GP_4_9_FN,      FN_IP9_8_6,
+                GP_4_8_FN,      FN_IP9_5_3,
+                GP_4_7_FN,      FN_IP9_2_0,
+                GP_4_6_FN,      FN_IP8_29_27,
+                GP_4_5_FN,      FN_IP8_26_24,
+                GP_4_4_FN,      FN_IP8_23_22,
+                GP_4_3_FN,      FN_IP8_21_19,
+                GP_4_2_FN,      FN_IP8_18_16,
+                GP_4_1_FN,      FN_IP8_15_14,
+                GP_4_0_FN,      FN_IP8_13_11 }
+        },
+
+        { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
+                             1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                             1, 1, 1, 1, 1, 1, 3, 4, 3, 3, 2) {
+                /* IP0_31 [1] */
+                0,      0,
+                /* IP0_30 [1] */
+                FN_A19, 0,
+                /* IP0_29 [1] */
+                FN_A18, 0,
+                /* IP0_28 [1] */
+                FN_A17, 0,
+                /* IP0_27 [1] */
+                FN_A16, 0,
+                /* IP0_26 [1] */
+                FN_A15, 0,
+                /* IP0_25 [1] */
+                FN_A14, 0,
+                /* IP0_24 [1] */
+                FN_A13, 0,
+                /* IP0_23 [1] */
+                FN_A12, 0,
+                /* IP0_22 [1] */
+                FN_A11, 0,
+                /* IP0_21 [1] */
+                FN_A10, 0,
+                /* IP0_20 [1] */
+                FN_A9,  0,
+                /* IP0_19 [1] */
+                FN_A8,  0,
+                /* IP0_18 [1] */
+                FN_A7,  0,
+                /* IP0_17 [1] */
+                FN_A6,  0,
+                /* IP0_16 [1] */
+                FN_A5,  0,
+                /* IP0_15 [1] */
+                FN_A4,  0,
+                /* IP0_14_12 [3] */
+                FN_SD1_DAT3_A,  FN_MMC_D3,      0,              FN_A0,
+                FN_ATAG0_A,     0,              FN_REMOCON_B,   0,
+                /* IP0_11_8 [4] */
+                FN_SD1_DAT2_A,  FN_MMC_D2,      0,              FN_BS,
+                FN_ATADIR0_A,   0,              FN_SDSELF_B,    0,
+                FN_PWM4_B,      0,              0,              0,
+                0,              0,              0,              0,
+                /* IP0_7_5 [3] */
+                FN_AUDATA1,     FN_ARM_TRACEDATA_1,     FN_GPSIN_C,     FN_USB_OVC1,
+                FN_RX2_E,       FN_SCL2_B,              0,              0,
+                /* IP0_4_2 [3] */
+                FN_AUDATA0,     FN_ARM_TRACEDATA_0,     FN_GPSCLK_C,    FN_USB_OVC0,
+                FN_TX2_E,       FN_SDA2_B,              0,              0,
+                /* IP0_1_0 [2] */
+                FN_PRESETOUT,   0,      FN_PWM1,        0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
+                             1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3, 3, 1, 1) {
+                /* IP1_31 [1] */
+                0,      0,
+                /* IP1_30 [1] */
+                0,      0,
+                /* IP1_29_28 [2] */
+                FN_EX_CS1,      FN_MMC_D4,      0,      0,
+                /* IP1_27_25 [3] */
+                FN_SSI_WS1_B,   FN_EX_CS0,      FN_SCL2_A,      FN_TX3_C,
+                FN_TS_SCK0_A,   0,              0,              0,
+                /* IP1_24 [1] */
+                FN_WE1,         FN_ATAWR0_B,
+                /* IP1_23_21 [3] */
+                FN_MMC_D5,      FN_ATADIR0_B,   0,              FN_RD_WR,
+                0,              0,              0,              0,
+                /* IP1_20_18 [3] */
+                FN_SSI_SCK1_B,  FN_ATAG0_B,     FN_CS1_A26,     FN_SDA2_A,
+                FN_SCK2_B,      0,              0,              0,
+                /* IP1_17 [1] */
+                FN_CS0,         FN_HSPI_RX1_B,
+                /* IP1_16_15 [2] */
+                FN_CLKOUT,      FN_HSPI_TX1_B,  FN_PWM0_B,      0,
+                /* IP1_14_11 [4] */
+                FN_SD1_WP_A,    FN_MMC_D7,      0,              FN_A25,
+                FN_DACK1_A,     0,              FN_HCTS0_B,     FN_RX3_C,
+                FN_TS_SDAT0_A,  0,              0,              0,
+                0,              0,              0,              0,
+                /* IP1_10_8 [3] */
+                FN_SD1_CLK_B,   FN_MMC_D6,      0,              FN_A24,
+                FN_DREQ1_A,     0,              FN_HRX0_B,      FN_TS_SPSYNC0_A,
+                /* IP1_7_5 [3] */
+                FN_A23,         FN_HTX0_B,      FN_TX2_B,       FN_DACK2_A,
+                FN_TS_SDEN0_A,  0,              0,              0,
+                /* IP1_4_2 [3] */
+                FN_A22,         FN_HRTS0_B,     FN_RX2_B,       FN_DREQ2_A,
+                0,              0,              0,              0,
+                /* IP1_1 [1] */
+                FN_A21,         FN_HSPI_CLK1_B,
+                /* IP1_0 [1] */
+                FN_A20,         FN_HSPI_CS1_B,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
+                             1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                             1, 1, 1, 1, 3, 2, 3, 3, 3, 3) {
+                /* IP2_31 [1] */
+                FN_MLB_CLK,     FN_IRQ1_A,
+                /* IP2_30 [1] */
+                FN_RD_WR_B,     FN_IRQ0,
+                /* IP2_29 [1] */
+                FN_D11,         0,
+                /* IP2_28 [1] */
+                FN_D10,         0,
+                /* IP2_27 [1] */
+                FN_D9,          0,
+                /* IP2_26 [1] */
+                FN_D8,          0,
+                /* IP2_25 [1] */
+                FN_D7,          0,
+                /* IP2_24 [1] */
+                FN_D6,          0,
+                /* IP2_23 [1] */
+                FN_D5,          0,
+                /* IP2_22 [1] */
+                FN_D4,          0,
+                /* IP2_21 [1] */
+                FN_D3,          0,
+                /* IP2_20 [1] */
+                FN_D2,          0,
+                /* IP2_19 [1] */
+                FN_D1,          0,
+                /* IP2_18 [1] */
+                FN_D0,          0,
+                /* IP2_17 [1] */
+                FN_EX_WAIT0,    FN_PWM0_C,
+                /* IP2_16_14 [3] */
+                FN_DACK0,       0,      0,      FN_TX3_A,
+                FN_DRACK0,      0,      0,      0,
+                /* IP2_13_12 [2] */
+                FN_DREQ0_A,     0,      0,      FN_RX3_A,
+                /* IP2_11_9 [3] */
+                FN_SD1_DAT1_A,  FN_MMC_D1,      0,      FN_ATAWR0_A,
+                FN_EX_CS5,      FN_EX_WAIT2_A,  0,      0,
+                /* IP2_8_6 [3] */
+                FN_SD1_DAT0_A,  FN_MMC_D0,      0,      FN_ATARD0,
+                FN_EX_CS4,      FN_EX_WAIT1_A,  0,      0,
+                /* IP2_5_3 [3] */
+                FN_SD1_CMD_A,   FN_MMC_CMD,     0,      FN_ATACS10,
+                FN_EX_CS3,      0,              0,      0,
+                /* IP2_2_0 [3] */
+                FN_SD1_CLK_A,   FN_MMC_CLK,     0,      FN_ATACS00,
+                FN_EX_CS2,      0,              0,      0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
+                             1, 1, 1, 1, 1, 3, 3, 2,
+                             3, 3, 3, 2, 3, 3, 2) {
+                /* IP3_31 [1] */
+                FN_DU0_DR6,     FN_LCDOUT6,
+                /* IP3_30 [1] */
+                FN_DU0_DR5,     FN_LCDOUT5,
+                /* IP3_29 [1] */
+                FN_DU0_DR4,     FN_LCDOUT4,
+                /* IP3_28 [1] */
+                FN_DU0_DR3,     FN_LCDOUT3,
+                /* IP3_27 [1] */
+                FN_DU0_DR2,     FN_LCDOUT2,
+                /* IP3_26_24 [3] */
+                FN_SSI_WS4,             FN_DU0_DR1,     FN_LCDOUT1,     FN_AUDATA3,
+                FN_ARM_TRACEDATA_3,     FN_SCL3_C,      FN_ADICHS2,     FN_TS_SPSYNC0_B,
+                /* IP3_23_21 [3] */
+                FN_SSI_SCK4,            FN_DU0_DR0,     FN_LCDOUT0,     FN_AUDATA2,
+                FN_ARM_TRACEDATA_2,     FN_SDA3_C,      FN_ADICHS1,     FN_TS_SDEN0_B,
+                /* IP3_20_19 [2] */
+                FN_SD1_DAT3_B,  FN_HRTS0_A,     FN_RTS0,        0,
+                /* IP3_18_16 [3] */
+                FN_SD1_DAT2_B,  FN_HCTS0_A,     FN_CTS0,        0,
+                0,              0,              0,              0,
+                /* IP3_15_13 [3] */
+                FN_SD1_DAT1_B,  FN_HSCK0,       FN_SCK0,        FN_SCL3_B,
+                0,              0,              0,              0,
+                /* IP3_12_10 [3] */
+                FN_SD1_DAT0_B,  FN_HRX0_A,      FN_RX0_A,       0,
+                0,              0,              0,              0,
+                /* IP3_9_8 [2] */
+                FN_SD1_CLK_B,   FN_HTX0_A,      FN_TX0_A,       0,
+                /* IP3_7_5 [3] */
+                FN_SD1_CMD_B,   FN_SCIF_CLK,    FN_AUDIO_CLKOUT_B,      FN_CAN_CLK_B,
+                FN_SDA3_B,      0,              0,                      0,
+                /* IP3_4_2 [3] */
+                FN_MLB_DAT,     FN_TX5_B,       FN_SCL3_A,      FN_IRQ3_A,
+                FN_SDSELF_B,    0,              0,              0,
+                /* IP3_1_0 [2] */
+                FN_MLB_SIG,     FN_RX5_B,       FN_SDA3_A,      FN_IRQ2_A,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
+                             1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1, 3, 3, 1) {
+                /* IP4_31 [1] */
+                0,      0,
+                /* IP4_30_29 [2] */
+                FN_VI0_R4_B,    FN_DU0_DB4,     FN_LCDOUT20,    0,
+                /* IP4_28_27 [2] */
+                FN_VI0_R3_B,    FN_DU0_DB3,     FN_LCDOUT19,    0,
+                /* IP4_26_25 [2] */
+                FN_VI0_R2_B,    FN_DU0_DB2,     FN_LCDOUT18,    0,
+                /* IP4_24_21 [4] */
+                FN_AUDIO_CLKC,  FN_VI0_R1_B,            FN_DU0_DB1,     FN_LCDOUT17,
+                FN_AUDATA7,     FN_ARM_TRACEDATA_7,     FN_GPSIN_A,     0,
+                FN_ADICS_SAMP,  FN_TS_SCK0_B,           0,              0,
+                0,              0,                      0,              0,
+                /* IP4_20_17 [4] */
+                FN_SSI_SCK2_B,  FN_VI0_R0_B,            FN_DU0_DB0,     FN_LCDOUT16,
+                FN_AUDATA6,     FN_ARM_TRACEDATA_6,     FN_GPSCLK_A,    FN_PWM0_A,
+                FN_ADICLK,      FN_TS_SDAT0_B,          0,              0,
+                0,              0,                      0,              0,
+                /* IP4_16_15 [2] */
+                FN_DU0_DG7,     FN_LCDOUT15,    FN_TX4_A,       0,
+                /* IP4_14_13 [2] */
+                FN_DU0_DG6,     FN_LCDOUT14,    FN_RX4_A,       0,
+                /* IP4_12_11 [2] */
+                FN_DU0_DG5,     FN_LCDOUT13,    FN_TX0_B,       0,
+                /* IP4_10_9 [2] */
+                FN_DU0_DG4,     FN_LCDOUT12,    FN_RX0_B,       0,
+                /* IP4_8 [1] */
+                FN_DU0_DG3,     FN_LCDOUT11,
+                /* IP4_7 [1] */
+                FN_DU0_DG2,     FN_LCDOUT10,
+                /* IP4_6_4 [3] */
+                FN_DU0_DG1,     FN_LCDOUT9,     FN_AUDATA5,     FN_ARM_TRACEDATA_5,
+                FN_RX1_D,       FN_CAN0_RX_A,   FN_ADIDATA,     0,
+                /* IP4_3_1 [3] */
+                FN_DU0_DG0,     FN_LCDOUT8,     FN_AUDATA4,     FN_ARM_TRACEDATA_4,
+                FN_TX1_D,       FN_CAN0_TX_A,   FN_ADICHS0,     0,
+                /* IP4_0 [1] */
+                FN_DU0_DR7,     FN_LCDOUT7,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
+                             1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1, 1, 2, 2, 2) {
+
+                /* IP5_31 [1] */
+                0, 0,
+                /* IP5_30_29 [2] */
+                FN_SSI_SDATA7,  FN_HSPI_TX0_B,  FN_RX2_A,       FN_CAN0_RX_B,
+                /* IP5_28_26 [3] */
+                FN_SSI_SDATA8,  FN_SSI_SCK2_A,  FN_HSPI_CS0_B,  FN_TX2_A,
+                FN_CAN0_TX_B,   0,              0,              0,
+                /* IP5_25_23 [3] */
+                FN_SD1_WP_B,    FN_SSI_WS78,    FN_HSPI_CLK0_B, FN_RX1_B,
+                FN_CAN_CLK_D,   0,              0,              0,
+                /* IP5_22_21 [2] */
+                FN_SD1_CD_B,    FN_SSI_SCK78,   FN_HSPI_RX0_B,  FN_TX1_B,
+                /* IP5_20_18 [3] */
+                FN_SSI_WS1_A,           FN_DU0_CDE,     FN_QPOLB,       FN_AUDSYNC,
+                FN_ARM_TRACECTL,        FN_FMIN_D,      0,              0,
+                /* IP5_17_15 [3] */
+                FN_SSI_SCK1_A,          FN_DU0_DISP,    FN_QPOLA,       FN_AUDCK,
+                FN_ARM_TRACECLK,        FN_BPFCLK_D,    0,              0,
+                /* IP5_14_13 [2] */
+                FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,        FN_QCPV_QDE,
+                FN_FMCLK_D,                             0,
+                /* IP5_12 [1] */
+                FN_DU0_EXVSYNC_DU0_VSYNC,       FN_QSTB_QHE,
+                /* IP5_11_10 [2] */
+                FN_SSI_WS2_B,   FN_DU0_EXHSYNC_DU0_HSYNC,
+                FN_QSTH_QHS,    0,
+                /* IP5_9_8 [2] */
+                FN_DU0_DOTCLKO_UT1,     FN_QSTVB_QVE,
+                FN_AUDIO_CLKOUT_A,      FN_REMOCON_C,
+                /* IP5_7 [1] */
+                FN_DU0_DOTCLKO_UT0,     FN_QCLK,
+                /* IP5_6 [1] */
+                FN_DU0_DOTCLKIN,        FN_QSTVA_QVS,
+                /* IP5_5_4 [2] */
+                FN_VI1_DATA11_B,        FN_DU0_DB7,     FN_LCDOUT23,    0,
+                /* IP5_3_2 [2] */
+                FN_VI1_DATA10_B,        FN_DU0_DB6,     FN_LCDOUT22,    0,
+                /* IP5_1_0 [2] */
+                FN_VI0_R5_B,            FN_DU0_DB5,     FN_LCDOUT21,    0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
+                             2, 2, 2, 2, 2, 1, 2, 2, 1, 2,
+                             1, 2, 1, 1, 1, 1, 2, 3, 2) {
+                /* IP6_31_30 [2] */
+                FN_SD0_DAT2,    0,      FN_SUB_TDI,     0,
+                /* IP6_29_28 [2] */
+                FN_SD0_DAT1,    0,      FN_SUB_TCK,     0,
+                /* IP6_27_26 [2] */
+                FN_SD0_DAT0,    0,      FN_SUB_TMS,     0,
+                /* IP6_25_24 [2] */
+                FN_SD0_CMD,     0,      FN_SUB_TRST,    0,
+                /* IP6_23_22 [2] */
+                FN_SD0_CLK,     0,      FN_SUB_TDO,     0,
+                /* IP6_21 [1] */
+                FN_SSI_SDATA0,          FN_ARM_TRACEDATA_15,
+                /* IP6_20_19 [2] */
+                FN_SSI_SDATA1,          FN_ARM_TRACEDATA_14,
+                FN_SCL1_A,              FN_SCK2_A,
+                /* IP6_18_17 [2] */
+                FN_SSI_SDATA2,          FN_HSPI_CS2_A,
+                FN_ARM_TRACEDATA_13,    FN_SDA1_A,
+                /* IP6_16 [1] */
+                FN_SSI_WS012,           FN_ARM_TRACEDATA_12,
+                /* IP6_15_14 [2] */
+                FN_SSI_SCK012,          FN_ARM_TRACEDATA_11,
+                FN_TX0_D,               0,
+                /* IP6_13 [1] */
+                FN_SSI_SDATA3,          FN_ARM_TRACEDATA_10,
+                /* IP6_12_11 [2] */
+                FN_SSI_SDATA4,          FN_SSI_WS2_A,
+                FN_ARM_TRACEDATA_9,     0,
+                /* IP6_10 [1] */
+                FN_SSI_WS34,            FN_ARM_TRACEDATA_8,
+                /* IP6_9 [1] */
+                FN_SSI_SDATA5,          FN_RX0_D,
+                /* IP6_8 [1] */
+                FN_SSI_WS5,             FN_TX4_C,
+                /* IP6_7 [1] */
+                FN_SSI_SCK5,            FN_RX4_C,
+                /* IP6_6_5 [2] */
+                FN_SSI_SDATA6,          FN_HSPI_TX2_A,
+                FN_FMIN_B,              0,
+                /* IP6_4_2 [3] */
+                FN_SSI_WS6,             FN_HSPI_CLK2_A,
+                FN_BPFCLK_B,            FN_CAN1_RX_B,
+                0,      0,      0,      0,
+                /* IP6_1_0 [2] */
+                FN_SSI_SCK6,            FN_HSPI_RX2_A,
+                FN_FMCLK_B,             FN_CAN1_TX_B,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
+                             3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2) {
+
+                /* IP7_31_29 [3] */
+                FN_VI0_HSYNC,   FN_SD2_CD_B,    FN_VI1_DATA2,   FN_DU1_DR2,
+                0,              FN_HSPI_CS1_A,  FN_RX3_B,       0,
+                /* IP7_28_25 [4] */
+                FN_VI0_FIELD,   FN_SD2_DAT3_B,  FN_VI0_R3_C,    FN_VI1_DATA1,
+                FN_DU1_DG7,     0,              FN_HSPI_CLK1_A, FN_TX4_B,
+                0,      0,      0,      0,
+                0,      0,      0,      0,
+                /* IP7_24_22 [3] */
+                FN_VI0_CLKENB,  FN_SD2_DAT2_B,  FN_VI1_DATA0,   FN_DU1_DG6,
+                0,              FN_HSPI_RX1_A,  FN_RX4_B,       0,
+                /* IP7_21 [1] */
+                FN_VI0_CLK,     FN_CAN_CLK_A,
+                /* IP7_20_18 [3] */
+                FN_TCLK0,       FN_HSCK1_A,     FN_FMIN_A,      0,
+                FN_IRQ2_C,      FN_CTS1_C,      FN_SPEEDIN,     0,
+                /* IP7_17_15 [3] */
+                FN_VI1_VSYNC,   FN_HSPI_TX0,    FN_HCTS1_A,     FN_BPFCLK_A,
+                0,              FN_TX1_C,       0,              0,
+                /* IP7_14_12 [3] */
+                FN_VI1_HSYNC,   FN_HSPI_RX0_A,  FN_HRTS1_A,     FN_FMCLK_A,
+                0,              FN_RX1_C,       0,              0,
+                /* IP7_11_9 [3] */
+                FN_VI1_FIELD,   FN_HSPI_CS0_A,  FN_HRX1_A,      0,
+                FN_SCK1_C,      0,              0,              0,
+                /* IP7_8_6 [3] */
+                FN_VI1_CLKENB,  FN_HSPI_CLK0_A, FN_HTX1_A,      0,
+                FN_RTS1_C,      0,              0,              0,
+                /* IP7_5_4 [2] */
+                FN_SD0_WP,      0,              FN_RX5_A,       0,
+                /* IP7_3_2 [2] */
+                FN_SD0_CD,      0,              FN_TX5_A,       0,
+                /* IP7_1_0 [2] */
+                FN_SD0_DAT3,    0,              FN_IRQ1_B,      0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
+                             1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3) {
+                /* IP8_31 [1] */
+                0, 0,
+                /* IP8_30 [1] */
+                0, 0,
+                /* IP8_29_27 [3] */
+                FN_VI0_G3,      FN_SD2_CMD_B,   FN_VI1_DATA5,   FN_DU1_DR5,
+                0,              FN_HRX1_B,      0,              0,
+                /* IP8_26_24 [3] */
+                FN_VI0_G2,      FN_SD2_CLK_B,   FN_VI1_DATA4,   FN_DU1_DR4,
+                0,              FN_HTX1_B,      0,              0,
+                /* IP8_23_22 [2] */
+                FN_VI0_DATA7_VI0_G1,    FN_DU1_DB5,
+                FN_RTS1_A,              0,
+                /* IP8_21_19 [3] */
+                FN_VI0_DATA6_VI0_G0,    FN_DU1_DB4,
+                FN_CTS1_A,              FN_PWM5,
+                0,      0,      0,      0,
+                /* IP8_18_16 [3] */
+                FN_VI0_DATA5_VI0_B5,    FN_DU1_DB3,     FN_SCK1_A,      FN_PWM4,
+                0,                      FN_HSCK1_B,     0,              0,
+                /* IP8_15_14 [2] */
+                FN_VI0_DATA4_VI0_B4,    FN_DU1_DB2,     FN_RX1_A,       0,
+                /* IP8_13_11 [3] */
+                FN_VI0_DATA3_VI0_B3,    FN_DU1_DG5,     FN_TX1_A,       FN_TX0_C,
+                0,                       0,             0,              0,
+                /* IP8_10_9 [2] */
+                FN_VI0_DATA2_VI0_B2,    FN_DU1_DG4,     FN_RX0_C,       0,
+                /* IP8_8_6 [3] */
+                FN_VI0_DATA1_VI0_B1,    FN_DU1_DG3,     FN_IRQ3_B,      FN_TX3_D,
+                0,                       0,             0,              0,
+                /* IP8_5_3 [3] */
+                FN_VI0_DATA0_VI0_B0,    FN_DU1_DG2,     FN_IRQ2_B,      FN_RX3_D,
+                0,                       0,             0,              0,
+                /* IP8_2_0 [3] */
+                FN_VI0_VSYNC,           FN_SD2_WP_B,    FN_VI1_DATA3,   FN_DU1_DR3,
+                0,                      FN_HSPI_TX1_A,  FN_TX3_B,       0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
+                             1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+                /* IP9_31 [1] */
+                0, 0,
+                /* IP9_30 [1] */
+                0, 0,
+                /* IP9_29_27 [3] */
+                FN_VI1_DATA11_A,        FN_DU1_EXHSYNC_DU1_HSYNC,
+                FN_ETH_RXD1,            FN_FMIN_C,
+                0,                      FN_RX2_D,
+                FN_SCL2_C,              0,
+                /* IP9_26_24 [3] */
+                FN_VI1_DATA10_A,        FN_DU1_DOTCLKOUT,
+                FN_ETH_RXD0,            FN_BPFCLK_C,
+                0,                      FN_TX2_D,
+                FN_SDA2_C,              0,
+                /* IP9_23_21 [3] */
+                FN_VI0_R5_A,    0,              FN_ETH_RX_ER,   FN_FMCLK_C,
+                FN_IERX,        FN_RX2_C,       0,              0,
+                /* IP9_20_18 [3] */
+                FN_VI0_R4_A,    FN_ETH_TX_EN,   0,              0,
+                FN_IETX,        FN_TX2_C,       0,              0,
+                /* IP9_17_15 [3] */
+                FN_VI0_R3_A,    FN_ETH_CRS_DV,  0,              FN_IECLK,
+                FN_SCK2_C,      0,              0,              0,
+                /* IP9_14_12 [3] */
+                FN_VI0_R2_A,    FN_VI1_DATA9,   FN_DU1_DB7,     FN_ETH_TXD1,
+                0,              FN_PWM3,        0,              0,
+                /* IP9_11_9 [3] */
+                FN_VI0_R1_A,    FN_VI1_DATA8,   FN_DU1_DB6,     FN_ETH_TXD0,
+                0,              FN_PWM2,        FN_TCLK1,       0,
+                /* IP9_8_6 [3] */
+                FN_VI0_R0_A,    FN_VI1_CLK,     FN_ETH_REF_CLK, FN_DU1_DOTCLKIN,
+                0,              0,              0,              0,
+                /* IP9_5_3 [3] */
+                FN_VI0_G5,      FN_SD2_DAT1_B,  FN_VI1_DATA7,   FN_DU1_DR7,
+                0,              FN_HCTS1_B,     0,              0,
+                /* IP9_2_0 [3] */
+                FN_VI0_G4,      FN_SD2_DAT0_B,  FN_VI1_DATA6,   FN_DU1_DR6,
+                0,              FN_HRTS1_B,     0,              0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
+                             1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4, 3, 3, 3) {
+
+                /* IP10_31 [1] */
+                0, 0,
+                /* IP10_30 [1] */
+                0, 0,
+                /* IP10_29 [1] */
+                0, 0,
+                /* IP10_28 [1] */
+                0, 0,
+                /* IP10_27 [1] */
+                0, 0,
+                /* IP10_26 [1] */
+                0, 0,
+                /* IP10_25 [1] */
+                0, 0,
+                /* IP10_24_22 [3] */
+                FN_SD2_WP_A,    FN_VI1_DATA15,  FN_EX_WAIT2_B,  FN_DACK0_B,
+                FN_HSPI_TX2_B,  FN_CAN_CLK_C,   0,              0,
+                /* IP10_21_19 [3] */
+                FN_SD2_CD_A,    FN_VI1_DATA14,  FN_EX_WAIT1_B,  FN_DREQ0_B,
+                FN_HSPI_RX2_B,  FN_REMOCON_A,   0,              0,
+                /* IP10_18_16 [3] */
+                FN_SD2_DAT3_A,  FN_VI1_DATA13,  FN_DACK2_B,     FN_ATAG1,
+                FN_HSPI_CS2_B,  FN_GPSIN_B,     0,              0,
+                /* IP10_15_13 [3] */
+                FN_SD2_DAT2_A,  FN_VI1_DATA12,  FN_DREQ2_B,     FN_ATADIR1,
+                FN_HSPI_CLK2_B, FN_GPSCLK_B,    0,              0,
+                /* IP10_12_9 [4] */
+                FN_SD2_DAT1_A,  FN_DU1_CDE,     FN_ATACS11,     FN_DACK1_B,
+                FN_ETH_MAGIC,   FN_CAN1_TX_A,   0,              FN_PWM6,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                /* IP10_8_6 [3] */
+                FN_SD2_DAT0_A,  FN_DU1_DISP,    FN_ATACS01,     FN_DREQ1_B,
+                FN_ETH_LINK,    FN_CAN1_RX_A,   0,              0,
+                /* IP10_5_3 [3] */
+                FN_SD2_CMD_A,   FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
+                FN_ATAWR1,      FN_ETH_MDIO,
+                FN_SCL1_B,      0,
+                0,              0,
+                /* IP10_2_0 [3] */
+                FN_SD2_CLK_A,   FN_DU1_EXVSYNC_DU1_VSYNC,
+                FN_ATARD1,      FN_ETH_MDC,
+                FN_SDA1_B,      0,
+                0,              0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,
+                             1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
+                             1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
+
+                /* SEL 31  [1] */
+                0, 0,
+                /* SEL_30 (SCIF5) [1] */
+                FN_SEL_SCIF5_A,         FN_SEL_SCIF5_B,
+                /* SEL_29_28 (SCIF4) [2] */
+                FN_SEL_SCIF4_A,         FN_SEL_SCIF4_B,
+                FN_SEL_SCIF4_C,         0,
+                /* SEL_27_26 (SCIF3) [2] */
+                FN_SEL_SCIF3_A,         FN_SEL_SCIF3_B,
+                FN_SEL_SCIF3_C,         FN_SEL_SCIF3_D,
+                /* SEL_25_23 (SCIF2) [3] */
+                FN_SEL_SCIF2_A,         FN_SEL_SCIF2_B,
+                FN_SEL_SCIF2_C,         FN_SEL_SCIF2_D,
+                FN_SEL_SCIF2_E,         0,
+                0,                      0,
+                /* SEL_22_21 (SCIF1) [2] */
+                FN_SEL_SCIF1_A,         FN_SEL_SCIF1_B,
+                FN_SEL_SCIF1_C,         FN_SEL_SCIF1_D,
+                /* SEL_20_19 (SCIF0) [2] */
+                FN_SEL_SCIF0_A,         FN_SEL_SCIF0_B,
+                FN_SEL_SCIF0_C,         FN_SEL_SCIF0_D,
+                /* SEL_18 [1] */
+                0, 0,
+                /* SEL_17 (SSI2) [1] */
+                FN_SEL_SSI2_A,          FN_SEL_SSI2_B,
+                /* SEL_16 (SSI1) [1] */
+                FN_SEL_SSI1_A,          FN_SEL_SSI1_B,
+                /* SEL_15 (VI1) [1] */
+                FN_SEL_VI1_A,           FN_SEL_VI1_B,
+                /* SEL_14_13 (VI0) [2] */
+                FN_SEL_VI0_A,           FN_SEL_VI0_B,
+                FN_SEL_VI0_C,           FN_SEL_VI0_D,
+                /* SEL_12 [1] */
+                0, 0,
+                /* SEL_11 (SD2) [1] */
+                FN_SEL_SD2_A,           FN_SEL_SD2_B,
+                /* SEL_10 (SD1) [1] */
+                FN_SEL_SD1_A,           FN_SEL_SD1_B,
+                /* SEL_9 (IRQ3) [1] */
+                FN_SEL_IRQ3_A,          FN_SEL_IRQ3_B,
+                /* SEL_8_7 (IRQ2) [2] */
+                FN_SEL_IRQ2_A,          FN_SEL_IRQ2_B,
+                FN_SEL_IRQ2_C,          0,
+                /* SEL_6 (IRQ1) [1] */
+                FN_SEL_IRQ1_A,          FN_SEL_IRQ1_B,
+                /* SEL_5 [1] */
+                0, 0,
+                /* SEL_4 (DREQ2) [1] */
+                FN_SEL_DREQ2_A,         FN_SEL_DREQ2_B,
+                /* SEL_3 (DREQ1) [1] */
+                FN_SEL_DREQ1_A,         FN_SEL_DREQ1_B,
+                /* SEL_2 (DREQ0) [1] */
+                FN_SEL_DREQ0_A,         FN_SEL_DREQ0_B,
+                /* SEL_1 (WAIT2) [1] */
+                FN_SEL_WAIT2_A,         FN_SEL_WAIT2_B,
+                /* SEL_0 (WAIT1) [1] */
+                FN_SEL_WAIT1_A,         FN_SEL_WAIT1_B,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,
+                             1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1,
+                             1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1) {
+
+                /* SEL_31 [1] */
+                0, 0,
+                /* SEL_30 [1] */
+                0, 0,
+                /* SEL_29 [1] */
+                0, 0,
+                /* SEL_28 [1] */
+                0, 0,
+                /* SEL_27 (CAN1) [1] */
+                FN_SEL_CAN1_A,          FN_SEL_CAN1_B,
+                /* SEL_26 (CAN0) [1] */
+                FN_SEL_CAN0_A,          FN_SEL_CAN0_B,
+                /* SEL_25_24 (CANCLK) [2] */
+                FN_SEL_CANCLK_A,        FN_SEL_CANCLK_B,
+                FN_SEL_CANCLK_C,        FN_SEL_CANCLK_D,
+                /* SEL_23 (HSCIF1) [1] */
+                FN_SEL_HSCIF1_A,        FN_SEL_HSCIF1_B,
+                /* SEL_22 (HSCIF0) [1] */
+                FN_SEL_HSCIF0_A,        FN_SEL_HSCIF0_B,
+                /* SEL_21 [1] */
+                0, 0,
+                /* SEL_20 [1] */
+                0, 0,
+                /* SEL_19 [1] */
+                0, 0,
+                /* SEL_18 [1] */
+                0, 0,
+                /* SEL_17 [1] */
+                0, 0,
+                /* SEL_16 [1] */
+                0, 0,
+                /* SEL_15 [1] */
+                0, 0,
+                /* SEL_14_13 (REMOCON) [2] */
+                FN_SEL_REMOCON_A,       FN_SEL_REMOCON_B,
+                FN_SEL_REMOCON_C,       0,
+                /* SEL_12_11 (FM) [2] */
+                FN_SEL_FM_A,            FN_SEL_FM_B,
+                FN_SEL_FM_C,            FN_SEL_FM_D,
+                /* SEL_10_9 (GPS) [2] */
+                FN_SEL_GPS_A,           FN_SEL_GPS_B,
+                FN_SEL_GPS_C,           0,
+                /* SEL_8 (TSIF0) [1] */
+                FN_SEL_TSIF0_A,         FN_SEL_TSIF0_B,
+                /* SEL_7 (HSPI2) [1] */
+                FN_SEL_HSPI2_A,         FN_SEL_HSPI2_B,
+                /* SEL_6 (HSPI1) [1] */
+                FN_SEL_HSPI1_A,         FN_SEL_HSPI1_B,
+                /* SEL_5 (HSPI0) [1] */
+                FN_SEL_HSPI0_A,         FN_SEL_HSPI0_B,
+                /* SEL_4_3 (I2C3) [2] */
+                FN_SEL_I2C3_A,          FN_SEL_I2C3_B,
+                FN_SEL_I2C3_C,          0,
+                /* SEL_2_1 (I2C2) [2] */
+                FN_SEL_I2C2_A,          FN_SEL_I2C2_B,
+                FN_SEL_I2C2_C,          0,
+                /* SEL_0 (I2C1) [1] */
+                FN_SEL_I2C1_A,          FN_SEL_I2C1_B,
+                }
+        },
+        { },
+};
+
+const struct sh_pfc_soc_info r8a7778_pinmux_info = {
+        .name = "r8a7778_pfc",
+
+        .unlock_reg = 0xfffc0000, /* PMMR */
+
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+
+        .groups = pinmux_groups,
+        .nr_groups = ARRAY_SIZE(pinmux_groups),
+
+        .functions = pinmux_functions,
+        .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+        .cfg_regs = pinmux_config_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 791a6719d8a9..8e22ca6c1044 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1,8 +1,9 @@
 /*
  * r8a7779 processor support - PFC hardware block
  *
- * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011, 2013  Renesas Solutions Corp.
  * Copyright (C) 2011  Magnus Damm
+ * Copyright (C) 2013  Cogent Embedded, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -19,6 +20,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/platform_data/gpio-rcar.h>
 
 #include "sh_pfc.h"
 
@@ -79,7 +81,7 @@
 #define _GP_PORT_ALL(bank, pin, name, sfx)      name##_##sfx
 
 #define _GP_GPIO(bank, pin, _name, sfx)                                 \
-        [(bank * 32) + pin] = {                                         \
+        [RCAR_GP_PIN(bank, pin)] = {                                    \
                 .name = __stringify(_name),                             \
                 .enum_id = _name##_DATA,                                \
         }
@@ -1472,9 +1474,12 @@ static struct sh_pfc_pin pinmux_pins[] = {
 /* - DU0 -------------------------------------------------------------------- */
 static const unsigned int du0_rgb666_pins[] = {
         /* R[7:2], G[7:2], B[7:2] */
-        188, 187, 186, 185, 184, 183,
-        194, 193, 192, 191, 190, 189,
-        200, 199, 198, 197, 196, 195,
+        RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
+        RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
+        RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),
+        RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29),
+        RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),  RCAR_GP_PIN(6, 6),
+        RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),  RCAR_GP_PIN(6, 3),
 };
 static const unsigned int du0_rgb666_mux[] = {
         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
@@ -1486,9 +1491,14 @@ static const unsigned int du0_rgb666_mux[] = {
 };
 static const unsigned int du0_rgb888_pins[] = {
         /* R[7:0], G[7:0], B[7:0] */
-        188, 187, 186, 185, 184, 183, 24, 23,
-        194, 193, 192, 191, 190, 189, 26, 25,
-        200, 199, 198, 197, 196, 195, 28, 27,
+        RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
+        RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
+        RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), RCAR_GP_PIN(6, 2),
+        RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),  RCAR_GP_PIN(5, 31),
+        RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), RCAR_GP_PIN(0, 26),
+        RCAR_GP_PIN(0, 25), RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),
+        RCAR_GP_PIN(6, 6),  RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),
+        RCAR_GP_PIN(6, 3),  RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 27),
 };
 static const unsigned int du0_rgb888_mux[] = {
         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
@@ -1500,28 +1510,28 @@ static const unsigned int du0_rgb888_mux[] = {
 };
 static const unsigned int du0_clk_in_pins[] = {
         /* CLKIN */
-        29,
+        RCAR_GP_PIN(0, 29),
 };
 static const unsigned int du0_clk_in_mux[] = {
         DU0_DOTCLKIN_MARK,
 };
 static const unsigned int du0_clk_out_0_pins[] = {
         /* CLKOUT */
-        180,
+        RCAR_GP_PIN(5, 20),
 };
 static const unsigned int du0_clk_out_0_mux[] = {
         DU0_DOTCLKOUT0_MARK,
 };
 static const unsigned int du0_clk_out_1_pins[] = {
         /* CLKOUT */
-        30,
+        RCAR_GP_PIN(0, 30),
 };
 static const unsigned int du0_clk_out_1_mux[] = {
         DU0_DOTCLKOUT1_MARK,
 };
 static const unsigned int du0_sync_0_pins[] = {
         /* VSYNC, HSYNC, DISP */
-        182, 181, 31,
+        RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(0, 31),
 };
 static const unsigned int du0_sync_0_mux[] = {
         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
@@ -1529,7 +1539,7 @@ static const unsigned int du0_sync_0_mux[] = {
 };
 static const unsigned int du0_sync_1_pins[] = {
         /* VSYNC, HSYNC, DISP */
-        182, 181, 32,
+        RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(1, 0),
 };
 static const unsigned int du0_sync_1_mux[] = {
         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
@@ -1537,14 +1547,14 @@ static const unsigned int du0_sync_1_mux[] = {
 };
 static const unsigned int du0_oddf_pins[] = {
         /* ODDF */
-        31,
+        RCAR_GP_PIN(0, 31),
 };
 static const unsigned int du0_oddf_mux[] = {
         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
 };
 static const unsigned int du0_cde_pins[] = {
         /* CDE */
-        33,
+        RCAR_GP_PIN(1, 1),
 };
 static const unsigned int du0_cde_mux[] = {
         DU0_CDE_MARK
@@ -1552,9 +1562,12 @@ static const unsigned int du0_cde_mux[] = {
 /* - DU1 -------------------------------------------------------------------- */
 static const unsigned int du1_rgb666_pins[] = {
         /* R[7:2], G[7:2], B[7:2] */
-        41, 40, 39, 38, 37, 36,
-        49, 48, 47, 46, 45, 44,
-        57, 56, 55, 54, 53, 52,
+        RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
+        RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
+        RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
+        RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
+        RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
+        RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 20),
 };
 static const unsigned int du1_rgb666_mux[] = {
         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
@@ -1566,9 +1579,14 @@ static const unsigned int du1_rgb666_mux[] = {
 };
 static const unsigned int du1_rgb888_pins[] = {
         /* R[7:0], G[7:0], B[7:0] */
-        41, 40, 39, 38, 37, 36, 35, 34,
-        49, 48, 47, 46, 45, 44, 43, 32,
-        57, 56, 55, 54, 53, 52, 51, 50,
+        RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
+        RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
+        RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 17),
+        RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
+        RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11),
+        RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24),
+        RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
+        RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
 };
 static const unsigned int du1_rgb888_mux[] = {
         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
@@ -1580,21 +1598,21 @@ static const unsigned int du1_rgb888_mux[] = {
 };
 static const unsigned int du1_clk_in_pins[] = {
         /* CLKIN */
-        58,
+        RCAR_GP_PIN(1, 26),
 };
 static const unsigned int du1_clk_in_mux[] = {
         DU1_DOTCLKIN_MARK,
 };
 static const unsigned int du1_clk_out_pins[] = {
         /* CLKOUT */
-        59,
+        RCAR_GP_PIN(1, 27),
 };
 static const unsigned int du1_clk_out_mux[] = {
         DU1_DOTCLKOUT_MARK,
 };
 static const unsigned int du1_sync_0_pins[] = {
         /* VSYNC, HSYNC, DISP */
-        61, 60, 62,
+        RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 30),
 };
 static const unsigned int du1_sync_0_mux[] = {
         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
@@ -1602,7 +1620,7 @@ static const unsigned int du1_sync_0_mux[] = {
 };
 static const unsigned int du1_sync_1_pins[] = {
         /* VSYNC, HSYNC, DISP */
-        61, 60, 63,
+        RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 31),
 };
 static const unsigned int du1_sync_1_mux[] = {
         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
@@ -1610,22 +1628,55 @@ static const unsigned int du1_sync_1_mux[] = {
 };
 static const unsigned int du1_oddf_pins[] = {
         /* ODDF */
-        62,
+        RCAR_GP_PIN(1, 30),
 };
 static const unsigned int du1_oddf_mux[] = {
         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
 };
 static const unsigned int du1_cde_pins[] = {
         /* CDE */
-        64,
+        RCAR_GP_PIN(2, 0),
 };
 static const unsigned int du1_cde_mux[] = {
         DU1_CDE_MARK
 };
+/* - Ether ------------------------------------------------------------------ */
+static const unsigned int ether_rmii_pins[] = {
+        /*
+         * ETH_TXD0, ETH_TXD1, ETH_TX_EN,  ETH_REFCLK,
+         * ETH_RXD0, ETH_RXD1, ETH_CRS_DV, ETH_RX_ER,
+         * ETH_MDIO, ETH_MDC
+         */
+        RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 18),
+        RCAR_GP_PIN(2, 26),
+        RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 17),
+        RCAR_GP_PIN(2, 19),
+        RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 28),
+};
+static const unsigned int ether_rmii_mux[] = {
+        ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REFCLK_MARK,
+        ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
+        ETH_MDIO_MARK, ETH_MDC_MARK,
+};
+static const unsigned int ether_link_pins[] = {
+        /* ETH_LINK */
+        RCAR_GP_PIN(2, 24),
+};
+static const unsigned int ether_link_mux[] = {
+        ETH_LINK_MARK,
+};
+static const unsigned int ether_magic_pins[] = {
+        /* ETH_MAGIC */
+        RCAR_GP_PIN(2, 25),
+};
+static const unsigned int ether_magic_mux[] = {
+        ETH_MAGIC_MARK,
+};
 /* - HSPI0 ------------------------------------------------------------------ */
 static const unsigned int hspi0_pins[] = {
         /* CLK, CS, RX, TX */
-        150, 151, 153, 152,
+        RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 25),
+        RCAR_GP_PIN(4, 24),
 };
 static const unsigned int hspi0_mux[] = {
         HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK,
@@ -1633,28 +1684,32 @@ static const unsigned int hspi0_mux[] = {
 /* - HSPI1 ------------------------------------------------------------------ */
 static const unsigned int hspi1_pins[] = {
         /* CLK, CS, RX, TX */
-        63, 58, 64, 62,
+        RCAR_GP_PIN(1, 31), RCAR_GP_PIN(1, 26), RCAR_GP_PIN(2, 0),
+        RCAR_GP_PIN(1, 30),
 };
 static const unsigned int hspi1_mux[] = {
         HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK,
 };
 static const unsigned int hspi1_b_pins[] = {
         /* CLK, CS, RX, TX */
-        90, 91, 93, 92,
+        RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 29),
+        RCAR_GP_PIN(2, 28),
 };
 static const unsigned int hspi1_b_mux[] = {
         HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK,
 };
 static const unsigned int hspi1_c_pins[] = {
         /* CLK, CS, RX, TX */
-        141, 142, 144, 143,
+        RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 16),
+        RCAR_GP_PIN(4, 15),
 };
 static const unsigned int hspi1_c_mux[] = {
         HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK,
 };
 static const unsigned int hspi1_d_pins[] = {
         /* CLK, CS, RX, TX */
-        101, 102, 104, 103,
+        RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 8),
+        RCAR_GP_PIN(3, 7),
 };
 static const unsigned int hspi1_d_mux[] = {
         HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK,
@@ -1662,14 +1717,16 @@ static const unsigned int hspi1_d_mux[] = {
 /* - HSPI2 ------------------------------------------------------------------ */
 static const unsigned int hspi2_pins[] = {
         /* CLK, CS, RX, TX */
-        9, 10, 11, 14,
+        RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+        RCAR_GP_PIN(0, 14),
 };
 static const unsigned int hspi2_mux[] = {
         HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK,
 };
 static const unsigned int hspi2_b_pins[] = {
         /* CLK, CS, RX, TX */
-        7, 13, 8, 6,
+        RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 8),
+        RCAR_GP_PIN(0, 6),
 };
 static const unsigned int hspi2_b_mux[] = {
         HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
@@ -1677,56 +1734,56 @@ static const unsigned int hspi2_b_mux[] = {
 /* - INTC ------------------------------------------------------------------- */
 static const unsigned int intc_irq0_pins[] = {
         /* IRQ */
-        78,
+        RCAR_GP_PIN(2, 14),
 };
 static const unsigned int intc_irq0_mux[] = {
         IRQ0_MARK,
 };
 static const unsigned int intc_irq0_b_pins[] = {
         /* IRQ */
-        141,
+        RCAR_GP_PIN(4, 13),
 };
 static const unsigned int intc_irq0_b_mux[] = {
         IRQ0_B_MARK,
 };
 static const unsigned int intc_irq1_pins[] = {
         /* IRQ */
-        79,
+        RCAR_GP_PIN(2, 15),
 };
 static const unsigned int intc_irq1_mux[] = {
         IRQ1_MARK,
 };
 static const unsigned int intc_irq1_b_pins[] = {
         /* IRQ */
-        142,
+        RCAR_GP_PIN(4, 14),
 };
 static const unsigned int intc_irq1_b_mux[] = {
         IRQ1_B_MARK,
 };
 static const unsigned int intc_irq2_pins[] = {
         /* IRQ */
-        88,
+        RCAR_GP_PIN(2, 24),
 };
 static const unsigned int intc_irq2_mux[] = {
         IRQ2_MARK,
 };
 static const unsigned int intc_irq2_b_pins[] = {
         /* IRQ */
-        143,
+        RCAR_GP_PIN(4, 15),
 };
 static const unsigned int intc_irq2_b_mux[] = {
         IRQ2_B_MARK,
 };
 static const unsigned int intc_irq3_pins[] = {
         /* IRQ */
-        89,
+        RCAR_GP_PIN(2, 25),
 };
 static const unsigned int intc_irq3_mux[] = {
         IRQ3_MARK,
 };
 static const unsigned int intc_irq3_b_pins[] = {
         /* IRQ */
-        144,
+        RCAR_GP_PIN(4, 16),
 };
 static const unsigned int intc_irq3_b_mux[] = {
         IRQ3_B_MARK,
@@ -1734,56 +1791,56 @@ static const unsigned int intc_irq3_b_mux[] = {
 /* - LSBC ------------------------------------------------------------------- */
 static const unsigned int lbsc_cs0_pins[] = {
         /* CS */
-        13,
+        RCAR_GP_PIN(0, 13),
 };
 static const unsigned int lbsc_cs0_mux[] = {
         CS0_MARK,
 };
 static const unsigned int lbsc_cs1_pins[] = {
         /* CS */
-        14,
+        RCAR_GP_PIN(0, 14),
 };
 static const unsigned int lbsc_cs1_mux[] = {
         CS1_A26_MARK,
 };
 static const unsigned int lbsc_ex_cs0_pins[] = {
         /* CS */
-        15,
+        RCAR_GP_PIN(0, 15),
 };
 static const unsigned int lbsc_ex_cs0_mux[] = {
         EX_CS0_MARK,
 };
 static const unsigned int lbsc_ex_cs1_pins[] = {
         /* CS */
-        16,
+        RCAR_GP_PIN(0, 16),
 };
 static const unsigned int lbsc_ex_cs1_mux[] = {
         EX_CS1_MARK,
 };
 static const unsigned int lbsc_ex_cs2_pins[] = {
         /* CS */
-        17,
+        RCAR_GP_PIN(0, 17),
 };
 static const unsigned int lbsc_ex_cs2_mux[] = {
         EX_CS2_MARK,
 };
 static const unsigned int lbsc_ex_cs3_pins[] = {
         /* CS */
-        18,
+        RCAR_GP_PIN(0, 18),
 };
 static const unsigned int lbsc_ex_cs3_mux[] = {
         EX_CS3_MARK,
 };
 static const unsigned int lbsc_ex_cs4_pins[] = {
         /* CS */
-        19,
+        RCAR_GP_PIN(0, 19),
 };
 static const unsigned int lbsc_ex_cs4_mux[] = {
         EX_CS4_MARK,
 };
 static const unsigned int lbsc_ex_cs5_pins[] = {
         /* CS */
-        20,
+        RCAR_GP_PIN(0, 20),
 };
 static const unsigned int lbsc_ex_cs5_mux[] = {
         EX_CS5_MARK,
@@ -1791,21 +1848,24 @@ static const unsigned int lbsc_ex_cs5_mux[] = {
 /* - MMCIF ------------------------------------------------------------------ */
 static const unsigned int mmc0_data1_pins[] = {
         /* D[0] */
-        19,
+        RCAR_GP_PIN(0, 19),
 };
 static const unsigned int mmc0_data1_mux[] = {
         MMC0_D0_MARK,
 };
 static const unsigned int mmc0_data4_pins[] = {
         /* D[0:3] */
-        19, 20, 21, 2,
+        RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
+        RCAR_GP_PIN(0, 2),
 };
 static const unsigned int mmc0_data4_mux[] = {
         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
 };
 static const unsigned int mmc0_data8_pins[] = {
         /* D[0:7] */
-        19, 20, 21, 2, 10, 11, 15, 16,
+        RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
+        RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+        RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
 };
 static const unsigned int mmc0_data8_mux[] = {
         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
@@ -1813,28 +1873,31 @@ static const unsigned int mmc0_data8_mux[] = {
 };
 static const unsigned int mmc0_ctrl_pins[] = {
         /* CMD, CLK */
-        18, 17,
+        RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
 };
 static const unsigned int mmc0_ctrl_mux[] = {
         MMC0_CMD_MARK, MMC0_CLK_MARK,
 };
 static const unsigned int mmc1_data1_pins[] = {
         /* D[0] */
-        72,
+        RCAR_GP_PIN(2, 8),
 };
 static const unsigned int mmc1_data1_mux[] = {
         MMC1_D0_MARK,
 };
 static const unsigned int mmc1_data4_pins[] = {
         /* D[0:3] */
-        72, 73, 74, 75,
+        RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+        RCAR_GP_PIN(2, 11),
 };
 static const unsigned int mmc1_data4_mux[] = {
         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
 };
 static const unsigned int mmc1_data8_pins[] = {
         /* D[0:7] */
-        72, 73, 74, 75, 76, 77, 80, 81,
+        RCAR_GP_PIN(2, 8),  RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10),
+        RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+        RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
 };
 static const unsigned int mmc1_data8_mux[] = {
         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
@@ -1842,7 +1905,7 @@ static const unsigned int mmc1_data8_mux[] = {
 };
 static const unsigned int mmc1_ctrl_pins[] = {
         /* CMD, CLK */
-        68, 65,
+        RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 1),
 };
 static const unsigned int mmc1_ctrl_mux[] = {
         MMC1_CMD_MARK, MMC1_CLK_MARK,
@@ -1850,84 +1913,84 @@ static const unsigned int mmc1_ctrl_mux[] = {
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
         /* RXD, TXD */
-        153, 152,
+        RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
 };
 static const unsigned int scif0_data_mux[] = {
         RX0_MARK, TX0_MARK,
 };
 static const unsigned int scif0_clk_pins[] = {
         /* SCK */
-        156,
+        RCAR_GP_PIN(4, 28),
 };
 static const unsigned int scif0_clk_mux[] = {
         SCK0_MARK,
 };
 static const unsigned int scif0_ctrl_pins[] = {
         /* RTS, CTS */
-        151, 150,
+        RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22),
 };
 static const unsigned int scif0_ctrl_mux[] = {
         RTS0_TANS_MARK, CTS0_MARK,
 };
 static const unsigned int scif0_data_b_pins[] = {
         /* RXD, TXD */
-        20, 19,
+        RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
 };
 static const unsigned int scif0_data_b_mux[] = {
         RX0_B_MARK, TX0_B_MARK,
 };
 static const unsigned int scif0_clk_b_pins[] = {
         /* SCK */
-        33,
+        RCAR_GP_PIN(1, 1),
 };
 static const unsigned int scif0_clk_b_mux[] = {
         SCK0_B_MARK,
 };
 static const unsigned int scif0_ctrl_b_pins[] = {
         /* RTS, CTS */
-        18, 11,
+        RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
 };
 static const unsigned int scif0_ctrl_b_mux[] = {
         RTS0_B_TANS_B_MARK, CTS0_B_MARK,
 };
 static const unsigned int scif0_data_c_pins[] = {
         /* RXD, TXD */
-        146, 147,
+        RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
 };
 static const unsigned int scif0_data_c_mux[] = {
         RX0_C_MARK, TX0_C_MARK,
 };
 static const unsigned int scif0_clk_c_pins[] = {
         /* SCK */
-        145,
+        RCAR_GP_PIN(4, 17),
 };
 static const unsigned int scif0_clk_c_mux[] = {
         SCK0_C_MARK,
 };
 static const unsigned int scif0_ctrl_c_pins[] = {
         /* RTS, CTS */
-        149, 148,
+        RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
 };
 static const unsigned int scif0_ctrl_c_mux[] = {
         RTS0_C_TANS_C_MARK, CTS0_C_MARK,
 };
 static const unsigned int scif0_data_d_pins[] = {
         /* RXD, TXD */
-        43, 42,
+        RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
 };
 static const unsigned int scif0_data_d_mux[] = {
         RX0_D_MARK, TX0_D_MARK,
 };
 static const unsigned int scif0_clk_d_pins[] = {
         /* SCK */
-        50,
+        RCAR_GP_PIN(1, 18),
 };
 static const unsigned int scif0_clk_d_mux[] = {
         SCK0_D_MARK,
 };
 static const unsigned int scif0_ctrl_d_pins[] = {
         /* RTS, CTS */
-        51, 35,
+        RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 3),
 };
 static const unsigned int scif0_ctrl_d_mux[] = {
         RTS0_D_TANS_D_MARK, CTS0_D_MARK,
@@ -1935,63 +1998,63 @@ static const unsigned int scif0_ctrl_d_mux[] = {
 /* - SCIF1 ------------------------------------------------------------------ */
 static const unsigned int scif1_data_pins[] = {
         /* RXD, TXD */
-        149, 148,
+        RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
 };
 static const unsigned int scif1_data_mux[] = {
         RX1_MARK, TX1_MARK,
 };
 static const unsigned int scif1_clk_pins[] = {
         /* SCK */
-        145,
+        RCAR_GP_PIN(4, 17),
 };
 static const unsigned int scif1_clk_mux[] = {
         SCK1_MARK,
 };
 static const unsigned int scif1_ctrl_pins[] = {
         /* RTS, CTS */
-        147, 146,
+        RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
 };
 static const unsigned int scif1_ctrl_mux[] = {
         RTS1_TANS_MARK, CTS1_MARK,
 };
 static const unsigned int scif1_data_b_pins[] = {
         /* RXD, TXD */
-        117, 114,
+        RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 18),
 };
 static const unsigned int scif1_data_b_mux[] = {
         RX1_B_MARK, TX1_B_MARK,
 };
 static const unsigned int scif1_clk_b_pins[] = {
         /* SCK */
-        113,
+        RCAR_GP_PIN(3, 17),
 };
 static const unsigned int scif1_clk_b_mux[] = {
         SCK1_B_MARK,
 };
 static const unsigned int scif1_ctrl_b_pins[] = {
         /* RTS, CTS */
-        115, 116,
+        RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
 };
 static const unsigned int scif1_ctrl_b_mux[] = {
         RTS1_B_TANS_B_MARK, CTS1_B_MARK,
 };
 static const unsigned int scif1_data_c_pins[] = {
         /* RXD, TXD */
-        67, 66,
+        RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
 };
 static const unsigned int scif1_data_c_mux[] = {
         RX1_C_MARK, TX1_C_MARK,
 };
 static const unsigned int scif1_clk_c_pins[] = {
         /* SCK */
-        86,
+        RCAR_GP_PIN(2, 22),
 };
 static const unsigned int scif1_clk_c_mux[] = {
         SCK1_C_MARK,
 };
 static const unsigned int scif1_ctrl_c_pins[] = {
         /* RTS, CTS */
-        69, 68,
+        RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
 };
 static const unsigned int scif1_ctrl_c_mux[] = {
         RTS1_C_TANS_C_MARK, CTS1_C_MARK,
@@ -1999,63 +2062,63 @@ static const unsigned int scif1_ctrl_c_mux[] = {
 /* - SCIF2 ------------------------------------------------------------------ */
 static const unsigned int scif2_data_pins[] = {
         /* RXD, TXD */
-        106, 105,
+        RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 9),
 };
 static const unsigned int scif2_data_mux[] = {
         RX2_MARK, TX2_MARK,
 };
 static const unsigned int scif2_clk_pins[] = {
         /* SCK */
-        107,
+        RCAR_GP_PIN(3, 11),
 };
 static const unsigned int scif2_clk_mux[] = {
         SCK2_MARK,
 };
 static const unsigned int scif2_data_b_pins[] = {
         /* RXD, TXD */
-        120, 119,
+        RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 23),
 };
 static const unsigned int scif2_data_b_mux[] = {
         RX2_B_MARK, TX2_B_MARK,
 };
 static const unsigned int scif2_clk_b_pins[] = {
         /* SCK */
-        118,
+        RCAR_GP_PIN(3, 22),
 };
 static const unsigned int scif2_clk_b_mux[] = {
         SCK2_B_MARK,
 };
 static const unsigned int scif2_data_c_pins[] = {
         /* RXD, TXD */
-        33, 31,
+        RCAR_GP_PIN(1, 1), RCAR_GP_PIN(0, 31),
 };
 static const unsigned int scif2_data_c_mux[] = {
         RX2_C_MARK, TX2_C_MARK,
 };
 static const unsigned int scif2_clk_c_pins[] = {
         /* SCK */
-        32,
+        RCAR_GP_PIN(1, 0),
 };
 static const unsigned int scif2_clk_c_mux[] = {
         SCK2_C_MARK,
 };
 static const unsigned int scif2_data_d_pins[] = {
         /* RXD, TXD */
-        64, 62,
+        RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
 };
 static const unsigned int scif2_data_d_mux[] = {
         RX2_D_MARK, TX2_D_MARK,
 };
 static const unsigned int scif2_clk_d_pins[] = {
         /* SCK */
-        63,
+        RCAR_GP_PIN(1, 31),
 };
 static const unsigned int scif2_clk_d_mux[] = {
         SCK2_D_MARK,
 };
 static const unsigned int scif2_data_e_pins[] = {
         /* RXD, TXD */
-        20, 19,
+        RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
 };
 static const unsigned int scif2_data_e_mux[] = {
         RX2_E_MARK, TX2_E_MARK,
@@ -2063,14 +2126,14 @@ static const unsigned int scif2_data_e_mux[] = {
 /* - SCIF3 ------------------------------------------------------------------ */
 static const unsigned int scif3_data_pins[] = {
         /* RXD, TXD */
-        137, 136,
+        RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8),
 };
 static const unsigned int scif3_data_mux[] = {
         RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK,
 };
 static const unsigned int scif3_clk_pins[] = {
         /* SCK */
-        135,
+        RCAR_GP_PIN(4, 7),
 };
 static const unsigned int scif3_clk_mux[] = {
         SCK3_MARK,
@@ -2078,35 +2141,35 @@ static const unsigned int scif3_clk_mux[] = {
 
 static const unsigned int scif3_data_b_pins[] = {
         /* RXD, TXD */
-        64, 62,
+        RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
 };
 static const unsigned int scif3_data_b_mux[] = {
         RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK,
 };
 static const unsigned int scif3_data_c_pins[] = {
         /* RXD, TXD */
-        15, 12,
+        RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 12),
 };
 static const unsigned int scif3_data_c_mux[] = {
         RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK,
 };
 static const unsigned int scif3_data_d_pins[] = {
         /* RXD, TXD */
-        30, 29,
+        RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 29),
 };
 static const unsigned int scif3_data_d_mux[] = {
         RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK,
 };
 static const unsigned int scif3_data_e_pins[] = {
         /* RXD, TXD */
-        35, 34,
+        RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
 };
 static const unsigned int scif3_data_e_mux[] = {
         RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK,
 };
 static const unsigned int scif3_clk_e_pins[] = {
         /* SCK */
-        42,
+        RCAR_GP_PIN(1, 10),
 };
 static const unsigned int scif3_clk_e_mux[] = {
         SCK3_E_MARK,
@@ -2114,42 +2177,42 @@ static const unsigned int scif3_clk_e_mux[] = {
 /* - SCIF4 ------------------------------------------------------------------ */
 static const unsigned int scif4_data_pins[] = {
         /* RXD, TXD */
-        123, 122,
+        RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 26),
 };
 static const unsigned int scif4_data_mux[] = {
         RX4_MARK, TX4_MARK,
 };
 static const unsigned int scif4_clk_pins[] = {
         /* SCK */
-        121,
+        RCAR_GP_PIN(3, 25),
 };
 static const unsigned int scif4_clk_mux[] = {
         SCK4_MARK,
 };
 static const unsigned int scif4_data_b_pins[] = {
         /* RXD, TXD */
-        111, 110,
+        RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
 };
 static const unsigned int scif4_data_b_mux[] = {
         RX4_B_MARK, TX4_B_MARK,
 };
 static const unsigned int scif4_clk_b_pins[] = {
         /* SCK */
-        112,
+        RCAR_GP_PIN(3, 16),
 };
 static const unsigned int scif4_clk_b_mux[] = {
         SCK4_B_MARK,
 };
 static const unsigned int scif4_data_c_pins[] = {
         /* RXD, TXD */
-        22, 21,
+        RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
 };
 static const unsigned int scif4_data_c_mux[] = {
         RX4_C_MARK, TX4_C_MARK,
 };
 static const unsigned int scif4_data_d_pins[] = {
         /* RXD, TXD */
-        69, 68,
+        RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
 };
 static const unsigned int scif4_data_d_mux[] = {
         RX4_D_MARK, TX4_D_MARK,
@@ -2157,56 +2220,56 @@ static const unsigned int scif4_data_d_mux[] = {
 /* - SCIF5 ------------------------------------------------------------------ */
 static const unsigned int scif5_data_pins[] = {
         /* RXD, TXD */
-        51, 50,
+        RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
 };
 static const unsigned int scif5_data_mux[] = {
         RX5_MARK, TX5_MARK,
 };
 static const unsigned int scif5_clk_pins[] = {
         /* SCK */
-        43,
+        RCAR_GP_PIN(1, 11),
 };
 static const unsigned int scif5_clk_mux[] = {
         SCK5_MARK,
 };
 static const unsigned int scif5_data_b_pins[] = {
         /* RXD, TXD */
-        18, 11,
+        RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
 };
 static const unsigned int scif5_data_b_mux[] = {
         RX5_B_MARK, TX5_B_MARK,
 };
 static const unsigned int scif5_clk_b_pins[] = {
         /* SCK */
-        19,
+        RCAR_GP_PIN(0, 19),
 };
 static const unsigned int scif5_clk_b_mux[] = {
         SCK5_B_MARK,
 };
 static const unsigned int scif5_data_c_pins[] = {
         /* RXD, TXD */
-        24, 23,
+        RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23),
 };
 static const unsigned int scif5_data_c_mux[] = {
         RX5_C_MARK, TX5_C_MARK,
 };
 static const unsigned int scif5_clk_c_pins[] = {
         /* SCK */
-        28,
+        RCAR_GP_PIN(0, 28),
 };
 static const unsigned int scif5_clk_c_mux[] = {
         SCK5_C_MARK,
 };
 static const unsigned int scif5_data_d_pins[] = {
         /* RXD, TXD */
-        8, 6,
+        RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6),
 };
 static const unsigned int scif5_data_d_mux[] = {
         RX5_D_MARK, TX5_D_MARK,
 };
 static const unsigned int scif5_clk_d_pins[] = {
         /* SCK */
-        7,
+        RCAR_GP_PIN(0, 7),
 };
 static const unsigned int scif5_clk_d_mux[] = {
         SCK5_D_MARK,
@@ -2214,35 +2277,36 @@ static const unsigned int scif5_clk_d_mux[] = {
 /* - SDHI0 ------------------------------------------------------------------ */
 static const unsigned int sdhi0_data1_pins[] = {
         /* D0 */
-        117,
+        RCAR_GP_PIN(3, 21),
 };
 static const unsigned int sdhi0_data1_mux[] = {
         SD0_DAT0_MARK,
 };
 static const unsigned int sdhi0_data4_pins[] = {
         /* D[0:3] */
-        117, 118, 119, 120,
+        RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
+        RCAR_GP_PIN(3, 24),
 };
 static const unsigned int sdhi0_data4_mux[] = {
         SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
 };
 static const unsigned int sdhi0_ctrl_pins[] = {
         /* CMD, CLK */
-        114, 113,
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 17),
 };
 static const unsigned int sdhi0_ctrl_mux[] = {
         SD0_CMD_MARK, SD0_CLK_MARK,
 };
 static const unsigned int sdhi0_cd_pins[] = {
         /* CD */
-        115,
+        RCAR_GP_PIN(3, 19),
 };
 static const unsigned int sdhi0_cd_mux[] = {
         SD0_CD_MARK,
 };
 static const unsigned int sdhi0_wp_pins[] = {
         /* WP */
-        116,
+        RCAR_GP_PIN(3, 20),
 };
 static const unsigned int sdhi0_wp_mux[] = {
         SD0_WP_MARK,
@@ -2250,35 +2314,36 @@ static const unsigned int sdhi0_wp_mux[] = {
 /* - SDHI1 ------------------------------------------------------------------ */
 static const unsigned int sdhi1_data1_pins[] = {
         /* D0 */
-        19,
+        RCAR_GP_PIN(0, 19),
 };
 static const unsigned int sdhi1_data1_mux[] = {
         SD1_DAT0_MARK,
 };
 static const unsigned int sdhi1_data4_pins[] = {
         /* D[0:3] */
-        19, 20, 21, 2,
+        RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
+        RCAR_GP_PIN(0, 2),
 };
 static const unsigned int sdhi1_data4_mux[] = {
         SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
 };
 static const unsigned int sdhi1_ctrl_pins[] = {
         /* CMD, CLK */
-        18, 17,
+        RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
 };
 static const unsigned int sdhi1_ctrl_mux[] = {
         SD1_CMD_MARK, SD1_CLK_MARK,
 };
 static const unsigned int sdhi1_cd_pins[] = {
         /* CD */
-        10,
+        RCAR_GP_PIN(0, 10),
 };
 static const unsigned int sdhi1_cd_mux[] = {
         SD1_CD_MARK,
 };
 static const unsigned int sdhi1_wp_pins[] = {
         /* WP */
-        11,
+        RCAR_GP_PIN(0, 11),
 };
 static const unsigned int sdhi1_wp_mux[] = {
         SD1_WP_MARK,
@@ -2286,35 +2351,36 @@ static const unsigned int sdhi1_wp_mux[] = {
 /* - SDHI2 ------------------------------------------------------------------ */
 static const unsigned int sdhi2_data1_pins[] = {
         /* D0 */
-        97,
+        RCAR_GP_PIN(3, 1),
 };
 static const unsigned int sdhi2_data1_mux[] = {
         SD2_DAT0_MARK,
 };
 static const unsigned int sdhi2_data4_pins[] = {
         /* D[0:3] */
-        97, 98, 99, 100,
+        RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+        RCAR_GP_PIN(3, 4),
 };
 static const unsigned int sdhi2_data4_mux[] = {
         SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
 };
 static const unsigned int sdhi2_ctrl_pins[] = {
         /* CMD, CLK */
-        102, 101,
+        RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
 };
 static const unsigned int sdhi2_ctrl_mux[] = {
         SD2_CMD_MARK, SD2_CLK_MARK,
 };
 static const unsigned int sdhi2_cd_pins[] = {
         /* CD */
-        103,
+        RCAR_GP_PIN(3, 7),
 };
 static const unsigned int sdhi2_cd_mux[] = {
         SD2_CD_MARK,
 };
 static const unsigned int sdhi2_wp_pins[] = {
         /* WP */
-        104,
+        RCAR_GP_PIN(3, 8),
 };
 static const unsigned int sdhi2_wp_mux[] = {
         SD2_WP_MARK,
@@ -2322,62 +2388,188 @@ static const unsigned int sdhi2_wp_mux[] = {
 /* - SDHI3 ------------------------------------------------------------------ */
 static const unsigned int sdhi3_data1_pins[] = {
         /* D0 */
-        50,
+        RCAR_GP_PIN(1, 18),
 };
 static const unsigned int sdhi3_data1_mux[] = {
         SD3_DAT0_MARK,
 };
 static const unsigned int sdhi3_data4_pins[] = {
         /* D[0:3] */
-        50, 51, 52, 53,
+        RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20),
+        RCAR_GP_PIN(1, 21),
 };
 static const unsigned int sdhi3_data4_mux[] = {
         SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
 };
 static const unsigned int sdhi3_ctrl_pins[] = {
         /* CMD, CLK */
-        35, 34,
+        RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
 };
 static const unsigned int sdhi3_ctrl_mux[] = {
         SD3_CMD_MARK, SD3_CLK_MARK,
 };
 static const unsigned int sdhi3_cd_pins[] = {
         /* CD */
-        62,
+        RCAR_GP_PIN(1, 30),
 };
 static const unsigned int sdhi3_cd_mux[] = {
         SD3_CD_MARK,
 };
 static const unsigned int sdhi3_wp_pins[] = {
         /* WP */
-        64,
+        RCAR_GP_PIN(2, 0),
 };
 static const unsigned int sdhi3_wp_mux[] = {
         SD3_WP_MARK,
 };
 /* - USB0 ------------------------------------------------------------------- */
 static const unsigned int usb0_pins[] = {
-        /* OVC */
-        150, 154,
+        /* PENC */
+        RCAR_GP_PIN(4, 26),
 };
 static const unsigned int usb0_mux[] = {
-        USB_OVC0_MARK, USB_PENC0_MARK,
+        USB_PENC0_MARK,
+};
+static const unsigned int usb0_ovc_pins[] = {
+        /* USB_OVC */
+        RCAR_GP_PIN(4, 22),
+};
+static const unsigned int usb0_ovc_mux[] = {
+        USB_OVC0_MARK,
 };
 /* - USB1 ------------------------------------------------------------------- */
 static const unsigned int usb1_pins[] = {
-        /* OVC */
-        152, 155,
+        /* PENC */
+        RCAR_GP_PIN(4, 27),
 };
 static const unsigned int usb1_mux[] = {
-        USB_OVC1_MARK, USB_PENC1_MARK,
+        USB_PENC1_MARK,
+};
+static const unsigned int usb1_ovc_pins[] = {
+        /* USB_OVC */
+        RCAR_GP_PIN(4, 24),
+};
+static const unsigned int usb1_ovc_mux[] = {
+        USB_OVC1_MARK,
 };
 /* - USB2 ------------------------------------------------------------------- */
 static const unsigned int usb2_pins[] = {
-        /* OVC, PENC */
-        125, 156,
+        /* PENC */
+        RCAR_GP_PIN(4, 28),
 };
 static const unsigned int usb2_mux[] = {
-        USB_OVC2_MARK, USB_PENC2_MARK,
+        USB_PENC2_MARK,
+};
+static const unsigned int usb2_ovc_pins[] = {
+        /* USB_OVC */
+        RCAR_GP_PIN(3, 29),
+};
+static const unsigned int usb2_ovc_mux[] = {
+        USB_OVC2_MARK,
+};
+/* - VIN0 ------------------------------------------------------------------- */
+static const unsigned int vin0_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 8),
+        RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+        RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int vin0_data8_mux[] = {
+        VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK,
+        VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
+        VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
+};
+static const unsigned int vin0_clk_pins[] = {
+        /* CLK */
+        RCAR_GP_PIN(2, 1),
+};
+static const unsigned int vin0_clk_mux[] = {
+        VI0_CLK_MARK,
+};
+static const unsigned int vin0_sync_pins[] = {
+        /* HSYNC, VSYNC */
+        RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+};
+static const unsigned int vin0_sync_mux[] = {
+        VI0_HSYNC_MARK, VI0_VSYNC_MARK,
+};
+/* - VIN1 ------------------------------------------------------------------- */
+static const unsigned int vin1_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+        RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
+        RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
+};
+static const unsigned int vin1_data8_mux[] = {
+        VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK,
+        VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
+        VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
+};
+static const unsigned int vin1_clk_pins[] = {
+        /* CLK */
+        RCAR_GP_PIN(2, 30),
+};
+static const unsigned int vin1_clk_mux[] = {
+        VI1_CLK_MARK,
+};
+static const unsigned int vin1_sync_pins[] = {
+        /* HSYNC, VSYNC */
+        RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0),
+};
+static const unsigned int vin1_sync_mux[] = {
+        VI1_HSYNC_MARK, VI1_VSYNC_MARK,
+};
+/* - VIN2 ------------------------------------------------------------------- */
+static const unsigned int vin2_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
+        RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
+        RCAR_GP_PIN(1, 31), RCAR_GP_PIN(2, 0),
+};
+static const unsigned int vin2_data8_mux[] = {
+        VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, VI2_DATA2_VI2_B2_MARK,
+        VI2_DATA3_VI2_B3_MARK, VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
+        VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
+};
+static const unsigned int vin2_clk_pins[] = {
+        /* CLK */
+        RCAR_GP_PIN(1, 30),
+};
+static const unsigned int vin2_clk_mux[] = {
+        VI2_CLK_MARK,
+};
+static const unsigned int vin2_sync_pins[] = {
+        /* HSYNC, VSYNC */
+        RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
+};
+static const unsigned int vin2_sync_mux[] = {
+        VI2_HSYNC_MARK, VI2_VSYNC_MARK,
+};
+/* - VIN3 ------------------------------------------------------------------- */
+static const unsigned int vin3_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+        RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+        RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
+};
+static const unsigned int vin3_data8_mux[] = {
+        VI3_DATA0_MARK, VI3_DATA1_MARK, VI3_DATA2_MARK,
+        VI3_DATA3_MARK, VI3_DATA4_MARK, VI3_DATA5_MARK,
+        VI3_DATA6_MARK, VI3_DATA7_MARK,
+};
+static const unsigned int vin3_clk_pins[] = {
+        /* CLK */
+        RCAR_GP_PIN(2, 31),
+};
+static const unsigned int vin3_clk_mux[] = {
+        VI3_CLK_MARK,
+};
+static const unsigned int vin3_sync_pins[] = {
+        /* HSYNC, VSYNC */
+        RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
+};
+static const unsigned int vin3_sync_mux[] = {
+        VI3_HSYNC_MARK, VI3_VSYNC_MARK,
 };
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
@@ -2398,6 +2590,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(du1_sync_1),
         SH_PFC_PIN_GROUP(du1_oddf),
         SH_PFC_PIN_GROUP(du1_cde),
+        SH_PFC_PIN_GROUP(ether_rmii),
+        SH_PFC_PIN_GROUP(ether_link),
+        SH_PFC_PIN_GROUP(ether_magic),
         SH_PFC_PIN_GROUP(hspi0),
         SH_PFC_PIN_GROUP(hspi1),
         SH_PFC_PIN_GROUP(hspi1_b),
@@ -2501,8 +2696,23 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(sdhi3_cd),
         SH_PFC_PIN_GROUP(sdhi3_wp),
         SH_PFC_PIN_GROUP(usb0),
+        SH_PFC_PIN_GROUP(usb0_ovc),
         SH_PFC_PIN_GROUP(usb1),
+        SH_PFC_PIN_GROUP(usb1_ovc),
         SH_PFC_PIN_GROUP(usb2),
+        SH_PFC_PIN_GROUP(usb2_ovc),
+        SH_PFC_PIN_GROUP(vin0_data8),
+        SH_PFC_PIN_GROUP(vin0_clk),
+        SH_PFC_PIN_GROUP(vin0_sync),
+        SH_PFC_PIN_GROUP(vin1_data8),
+        SH_PFC_PIN_GROUP(vin1_clk),
+        SH_PFC_PIN_GROUP(vin1_sync),
+        SH_PFC_PIN_GROUP(vin2_data8),
+        SH_PFC_PIN_GROUP(vin2_clk),
+        SH_PFC_PIN_GROUP(vin2_sync),
+        SH_PFC_PIN_GROUP(vin3_data8),
+        SH_PFC_PIN_GROUP(vin3_clk),
+        SH_PFC_PIN_GROUP(vin3_sync),
 };
 
 static const char * const du0_groups[] = {
@@ -2528,6 +2738,12 @@ static const char * const du1_groups[] = {
         "du1_cde",
 };
 
+static const char * const ether_groups[] = {
+        "ether_rmii",
+        "ether_link",
+        "ether_magic",
+};
+
 static const char * const hspi0_groups[] = {
         "hspi0",
 };
@@ -2683,19 +2899,47 @@ static const char * const sdhi3_groups[] = {
 
 static const char * const usb0_groups[] = {
         "usb0",
+        "usb0_ovc",
 };
 
 static const char * const usb1_groups[] = {
         "usb1",
+        "usb1_ovc",
 };
 
 static const char * const usb2_groups[] = {
         "usb2",
+        "usb2_ovc",
+};
+
+static const char * const vin0_groups[] = {
+        "vin0_data8",
+        "vin0_clk",
+        "vin0_sync",
+};
+
+static const char * const vin1_groups[] = {
+        "vin1_data8",
+        "vin1_clk",
+        "vin1_sync",
+};
+
+static const char * const vin2_groups[] = {
+        "vin2_data8",
+        "vin2_clk",
+        "vin2_sync",
+};
+
+static const char * const vin3_groups[] = {
+        "vin3_data8",
+        "vin3_clk",
+        "vin3_sync",
 };
 
 static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(du0),
         SH_PFC_FUNCTION(du1),
+        SH_PFC_FUNCTION(ether),
         SH_PFC_FUNCTION(hspi0),
         SH_PFC_FUNCTION(hspi1),
         SH_PFC_FUNCTION(hspi2),
@@ -2716,6 +2960,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(usb0),
         SH_PFC_FUNCTION(usb1),
         SH_PFC_FUNCTION(usb2),
+        SH_PFC_FUNCTION(vin0),
+        SH_PFC_FUNCTION(vin1),
+        SH_PFC_FUNCTION(vin2),
+        SH_PFC_FUNCTION(vin3),
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -3520,7 +3768,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
             /* SEL_SCIF [2] */
             FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
             /* SEL_CANCLK [2] */
-            FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
+            FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 0,
             /* SEL_CAN0 [1] */
             FN_SEL_CAN0_0, FN_SEL_CAN0_1,
             /* SEL_HSCIF1 [1] */
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
new file mode 100644
index 000000000000..85d77a417c0e
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -0,0 +1,3835 @@
+/*
+ * R8A7790 processor support
+ *
+ * Copyright (C) 2013  Renesas Electronics Corporation
+ * Copyright (C) 2013  Magnus Damm
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_data/gpio-rcar.h>
+
+#include "core.h"
+#include "sh_pfc.h"
+
+#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
+
+#define PORT_GP_32(bank, fn, sfx)                                       \
+        PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),     \
+        PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),     \
+        PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),     \
+        PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),     \
+        PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),     \
+        PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),     \
+        PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),     \
+        PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),     \
+        PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),     \
+        PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),     \
+        PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),     \
+        PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),     \
+        PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),     \
+        PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx),     \
+        PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx),     \
+        PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
+
+#define PORT_GP_32_REV(bank, fn, sfx)                                   \
+        PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),     \
+        PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),     \
+        PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),     \
+        PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),     \
+        PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),     \
+        PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),     \
+        PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),     \
+        PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),     \
+        PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),     \
+        PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),     \
+        PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),     \
+        PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),     \
+        PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),     \
+        PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),     \
+        PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),     \
+        PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)
+
+#define CPU_ALL_PORT(fn, sfx)                                           \
+        PORT_GP_32(0, fn, sfx),                                         \
+        PORT_GP_32(1, fn, sfx),                                         \
+        PORT_GP_32(2, fn, sfx),                                         \
+        PORT_GP_32(3, fn, sfx),                                         \
+        PORT_GP_32(4, fn, sfx),                                         \
+        PORT_GP_32(5, fn, sfx)
+
+#define _GP_PORT_ALL(bank, pin, name, sfx)      name##_##sfx
+
+#define _GP_GPIO(bank, pin, _name, sfx)                                 \
+        [(bank * 32) + pin] = {                                         \
+                .name = __stringify(_name),                             \
+                .enum_id = _name##_DATA,                                \
+        }
+
+#define _GP_DATA(bank, pin, name, sfx)                                  \
+        PINMUX_DATA(name##_DATA, name##_FN)
+
+#define GP_ALL(str)             CPU_ALL_PORT(_GP_PORT_ALL, str)
+#define PINMUX_GPIO_GP_ALL()    CPU_ALL_PORT(_GP_GPIO, unused)
+#define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_GP_DATA, unused)
+
+#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
+#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
+                                                          FN_##ipsr, FN_##fn)
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        GP_ALL(DATA),
+        PINMUX_DATA_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        GP_ALL(FN),
+
+        /* GPSR0 */
+        FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
+        FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
+        FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
+        FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
+        FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
+        FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
+        FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
+        FN_IP3_14_12, FN_IP3_17_15,
+
+        /* GPSR1 */
+        FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
+        FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
+        FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
+        FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
+        FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
+        FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
+        FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
+
+        /* GPSR2 */
+        FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
+        FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
+        FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
+        FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
+        FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
+        FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
+        FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
+
+        /* GPSR3 */
+        FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
+        FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
+        FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
+        FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
+        FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
+        FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
+        FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
+
+        /* GPSR4 */
+        FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
+        FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
+        FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
+        FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
+        FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
+        FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
+        FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
+        FN_IP14_15_12, FN_IP14_18_16,
+
+        /* GPSR5 */
+        FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
+        FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
+        FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
+        FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
+        FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
+        FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
+        FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
+
+        /* IPSR0 */
+        FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
+        FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
+        FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
+        FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
+        FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
+        FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
+        FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
+        FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
+        FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
+        FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
+        FN_SCL2_CIS_C, FN_D7, FN_AD_DI_B, FN_SDA2_C,
+        FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C,
+        FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0,
+        FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
+
+        /* IPSR1 */
+        FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1,
+        FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
+        FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2,
+        FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
+        FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3,
+        FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
+        FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
+        FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
+        FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
+        FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
+        FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
+        FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
+        FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
+        FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
+        FN_A0, FN_PWM3, FN_A1, FN_PWM4,
+
+        /* IPSR2 */
+        FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
+        FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
+        FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
+        FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
+        FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
+        FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
+        FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_VI2_DATA0_VI2_B0_B,
+        FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
+        FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_VI2_DATA1_VI2_B1_B,
+        FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
+        FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
+
+        /* IPSR3 */
+        FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
+        FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
+        FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
+        FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
+        FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
+        FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
+        FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
+        FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
+        FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
+        FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
+        FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
+        FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
+        FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
+
+        /* IPSR4 */
+        FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
+        FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
+        FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
+        FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
+        FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
+        FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
+        FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
+        FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
+        FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
+        FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
+        FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
+        FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
+        FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
+        FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
+        FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
+
+        /* IPSR5 */
+        FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
+        FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
+        FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B,
+        FN_INTC_EN0_N, FN_SCL1_CIS, FN_EX_CS5_N, FN_CAN0_RX,
+        FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
+        FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N,
+        FN_SDA1_CIS, FN_BS_N, FN_IETX, FN_HTX1_B,
+        FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
+        FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
+        FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
+        FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
+        FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
+        FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
+        FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
+        FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
+        FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
+        FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
+        FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
+        FN_SSI_WS78_B,
+
+        /* IPSR6 */
+        FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
+        FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
+        FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
+        FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
+        FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
+        FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
+        FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
+        FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
+        FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
+        FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
+        FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER,
+        FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
+        FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0,
+        FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
+        FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
+        FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
+        FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
+        FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
+        FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
+        FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
+        FN_STP_IVCXO27_1_B, FN_HRX0_F,
+
+        /* IPSR7 */
+        FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
+        FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
+        FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
+        FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C,
+        FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC,
+        FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0,
+        FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
+        FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
+        FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
+        FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
+        FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
+        FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
+        FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
+        FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN,
+        FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
+        FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
+        FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
+        FN_MII_RXD2,
+
+        /* IPSR8 */
+        FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
+        FN_MII_RXD3, FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
+        FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
+        FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
+        FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
+        FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
+        FN_MII_RX_ER, FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
+        FN_MII_RX_CLK, FN_VI1_CLK, FN_AVB_RX_DV,
+        FN_MII_RX_DV, FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
+        FN_AVB_CRS, FN_MII_CRS, FN_VI1_DATA1_VI1_B1,
+        FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,
+        FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
+        FN_MII_MDIO, FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
+        FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
+        FN_AVB_MAGIC, FN_MII_MAGIC, FN_VI1_DATA5_VI1_B5,
+        FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
+        FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
+        FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
+
+        /* IPSR9 */
+        FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
+        FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
+        FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
+        FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
+        FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
+        FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B,
+        FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
+        FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
+        FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B,
+        FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
+        FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD,
+        FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,
+        FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK,
+        FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
+        FN_MII_LINK, FN_SCIFB0_TXD_B, FN_SD1_DAT2,
+        FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,
+        FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0,
+        FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
+        FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
+        FN_SCL2_D, FN_SCL2_CIS_D, FN_SIM0_CLK_B,
+        FN_VI3_CLK_B,
+
+        /* IPSR10 */
+        FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
+        FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D,
+        FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
+        FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
+        FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
+        FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
+        FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
+        FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
+        FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
+        FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
+        FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
+        FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
+        FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
+        FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
+        FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
+        FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
+        FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
+        FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
+        FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
+        FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
+        FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
+        FN_GLO_I0_B, FN_VI3_DATA6_B,
+
+        /* IPSR11 */
+        FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
+        FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
+        FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
+        FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
+        FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
+        FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
+        FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
+        FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
+        FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
+        FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
+        FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
+        FN_RDS_DATA_E, FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B,
+        FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B,
+        FN_SDA2_CIS_B, FN_MLB_DAT, FN_SPV_EVEN,
+        FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
+        FN_RDS_CLK_B, FN_SSI_SCK0129, FN_CAN_CLK_B,
+        FN_MOUT0,
+
+        /* IPSR12 */
+        FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
+        FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
+        FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
+        FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
+        FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
+        FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
+        FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
+        FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
+        FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
+        FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
+        FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
+        FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
+        FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
+        FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
+        FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
+        FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
+        FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
+        FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
+        FN_CAN_DEBUGOUT4,
+
+        /* IPSR13 */
+        FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
+        FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
+        FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C,
+        FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
+        FN_BPFCLK_F, FN_RDS_CLK_E, FN_SSI_WS6,
+        FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
+        FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
+        FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5,
+        FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
+        FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
+        FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
+        FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
+        FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
+        FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
+        FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
+        FN_BPFCLK_E, FN_RDS_CLK_D, FN_SSI_SDATA7_B,
+        FN_FMIN_G, FN_RDS_DATA_F, FN_SSI_SDATA8,
+        FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
+        FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
+        FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
+        FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
+        FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
+
+        /* IPSR14 */
+        FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
+        FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
+        FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
+        FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_SDA1_C,
+        FN_SDA1_CIS_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
+        FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
+        FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
+        FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
+        FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C,
+        FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS,
+        FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
+        FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
+        FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
+        FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
+        FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
+        FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
+        FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS,
+        FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
+        FN_HRTS0_N_C,
+
+        /* IPSR15 */
+        FN_SCIFA2_SCK, FN_FMCLK, FN_MSIOF3_SCK, FN_DU2_DG7,
+        FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
+        FN_DU2_DB0, FN_LCDOUT16, FN_SCL2, FN_SCL2_CIS,
+        FN_SCIFA2_TXD, FN_BPFCLK, FN_DU2_DB1, FN_LCDOUT17,
+        FN_SDA2, FN_SDA2_CIS, FN_HSCK0, FN_TS_SDEN0,
+        FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
+        FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
+        FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
+        FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
+        FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
+        FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
+        FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
+        FN_SCIFA2_RXD_B, FN_MSIOF0_SS1, FN_ADICHS0,
+        FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
+        FN_DU2_DG6, FN_LCDOUT14,
+
+        /* IPSR16 */
+        FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
+        FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
+        FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
+        FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C,
+        FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
+        FN_TCLK1_B,
+
+        FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+        FN_SEL_SCIF1_4,
+        FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
+        FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
+        FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
+        FN_SEL_SCIFB1_4,
+        FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
+        FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
+        FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
+        FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+        FN_SEL_SOF1_0, FN_SEL_SOF1_1,
+        FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
+        FN_SEL_SSI6_0, FN_SEL_SSI6_1,
+        FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
+        FN_SEL_VI3_0, FN_SEL_VI3_1,
+        FN_SEL_VI2_0, FN_SEL_VI2_1,
+        FN_SEL_VI1_0, FN_SEL_VI1_1,
+        FN_SEL_VI0_0, FN_SEL_VI0_1,
+        FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
+        FN_SEL_LBS_0, FN_SEL_LBS_1,
+        FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+        FN_SEL_SOF3_0, FN_SEL_SOF3_1,
+        FN_SEL_SOF0_0, FN_SEL_SOF0_1,
+
+        FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+        FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+        FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
+        FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+        FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
+        FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
+        FN_SEL_CAN1_0, FN_SEL_CAN1_1,
+        FN_SEL_ADI_0, FN_SEL_ADI_1,
+        FN_SEL_SSP_0, FN_SEL_SSP_1,
+        FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
+        FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
+        FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
+        FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
+        FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
+        FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
+        FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5,
+        FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
+        FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
+
+        FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
+        FN_SEL_IIC0_0, FN_SEL_IIC0_1,
+        FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+        FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+        FN_SEL_IIC2_4,
+        FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
+        FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
+        FN_SEL_I2C2_4,
+        FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+
+        VI1_DATA7_VI1_B7_MARK,
+
+        USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
+        USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
+        DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
+
+        D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
+        D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
+        VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
+        VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
+        VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
+        SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
+        VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
+        SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
+        VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
+        SCL2_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
+        SCL2_CIS_C_MARK, D7_MARK, AD_DI_B_MARK, SDA2_C_MARK,
+        VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, SDA2_CIS_C_MARK,
+        D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK,
+        VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
+
+        D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, MII_TXD1_MARK,
+        VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
+        SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, MII_TXD2_MARK,
+        VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
+        SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, MII_TXD3_MARK,
+        VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
+        D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
+        VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
+        D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
+        VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
+        SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
+        VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
+        D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
+        VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
+        A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
+
+        A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
+        PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
+        TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
+        A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
+        SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
+        A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
+        VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, VI2_DATA0_VI2_B0_B_MARK,
+        A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
+        VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, VI2_DATA1_VI2_B1_B_MARK,
+        A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
+        VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
+
+        A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
+        VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
+        A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
+        VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
+        A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
+        MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
+        VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
+        ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
+        ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
+        A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
+        AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
+        ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
+        VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
+
+        A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
+        A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
+        VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
+        VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
+        VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
+        VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
+        VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
+        VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
+        CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
+        VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
+        VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
+        MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
+        HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
+        VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
+        VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
+
+        EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
+        VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
+        EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
+        VI2_HSYNC_N_MARK, SCL1_MARK, VI2_HSYNC_N_B_MARK,
+        INTC_EN0_N_MARK, SCL1_CIS_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
+        MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
+        VI1_G2_B_MARK, VI2_R4_MARK, SDA1_MARK, INTC_EN1_N_MARK,
+        SDA1_CIS_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
+        CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
+        CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
+        VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
+        INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
+        VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
+        WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
+        VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
+        IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
+        VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
+        MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
+        VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
+        SSI_WS78_B_MARK,
+
+        DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
+        VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
+        DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
+        SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
+        INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
+        DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
+        MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
+        SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
+        ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
+        TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK,
+        SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK,
+        STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
+        SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK,
+        STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
+        SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
+        RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
+        TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
+        RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK,
+        STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
+        ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK,
+        STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
+
+        ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK,
+        SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
+        RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK,
+        ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK,
+        HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK,
+        SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK,
+        STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
+        ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK,
+        TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
+        SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
+        GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
+        STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
+        PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
+        PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK,
+        AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
+        ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK,
+        VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
+        MII_RXD2_MARK,
+
+        VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
+        MII_RXD3_MARK, VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
+        AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
+        AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
+        AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
+        AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
+        MII_RX_ER_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
+        MII_RX_CLK_MARK, VI1_CLK_MARK, AVB_RX_DV_MARK,
+        MII_RX_DV_MARK, VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
+        AVB_CRS_MARK, MII_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
+        SCIFA1_RXD_D_MARK, AVB_MDC_MARK, MII_MDC_MARK,
+        VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
+        MII_MDIO_MARK, VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
+        AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
+        AVB_MAGIC_MARK, MII_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
+        AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
+        SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
+        SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
+
+        SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
+        SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
+        SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
+        SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
+        SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
+        GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, SCL1_B_MARK,
+        SCL1_CIS_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
+        MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
+        GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, SDA1_B_MARK,
+        SDA1_CIS_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
+        AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK,
+        AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK,
+        SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK,
+        SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
+        MII_LINK_MARK, SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
+        AVB_COL_MARK, MII_COL_MARK, SCIFB0_CTS_N_B_MARK,
+        SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK,
+        SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
+        TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
+        SCL2_D_MARK, SCL2_CIS_D_MARK, SIM0_CLK_B_MARK,
+        VI3_CLK_B_MARK,
+
+        SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
+        GLO_RFON_MARK, VI1_CLK_B_MARK, SDA2_D_MARK, SDA2_CIS_D_MARK,
+        SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
+        VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
+        VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
+        VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
+        TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
+        SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
+        VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
+        TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
+        SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, RDS_DATA_MARK,
+        VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
+        TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
+        SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, RDS_CLK_MARK,
+        VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
+        GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
+        MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
+        HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
+        VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
+        TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
+        VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
+        GLO_I0_B_MARK, VI3_DATA6_B_MARK,
+
+        SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
+        GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
+        TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
+        SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
+        MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
+        SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
+        MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
+        SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
+        VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
+        MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
+        RDS_DATA_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, FMIN_F_MARK,
+        RDS_DATA_E_MARK, MLB_CLK_MARK, SCL2_B_MARK, SCL2_CIS_B_MARK,
+        MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, SDA2_B_MARK,
+        SDA2_CIS_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK,
+        SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
+        RDS_CLK_B_MARK, SSI_SCK0129_MARK, CAN_CLK_B_MARK,
+        MOUT0_MARK,
+
+        SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
+        SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
+        SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
+        SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
+        SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
+        MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
+        STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
+        CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
+        SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
+        SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
+        MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
+        SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
+        MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
+        SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
+        CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
+        IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
+        CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
+        IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
+        CAN_DEBUGOUT4_MARK,
+
+        SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
+        LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
+        SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, RDS_CLK_C_MARK,
+        DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
+        BPFCLK_F_MARK, RDS_CLK_E_MARK, SSI_WS6_MARK,
+        SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
+        LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
+        FMIN_D_MARK, RDS_DATA_C_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
+        CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
+        SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
+        CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
+        SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
+        LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
+        STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
+        TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
+        BPFCLK_E_MARK, RDS_CLK_D_MARK, SSI_SDATA7_B_MARK,
+        FMIN_G_MARK, RDS_DATA_F_MARK, SSI_SDATA8_MARK,
+        STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
+        CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
+        STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
+        SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
+        SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
+
+        AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
+        DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
+        REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
+        MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, SDA1_C_MARK,
+        SDA1_CIS_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
+        DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
+        TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
+        HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
+        LCDOUT11_MARK, PWM0_B_MARK, SCL1_C_MARK, SCL1_CIS_C_MARK,
+        SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_TANS_MARK,
+        MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
+        SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
+        DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
+        SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
+        LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
+        CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
+        SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_TANS_MARK,
+        MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
+        HRTS0_N_C_MARK,
+
+        SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
+        LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
+        DU2_DB0_MARK, LCDOUT16_MARK, SCL2_MARK, SCL2_CIS_MARK,
+        SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
+        SDA2_MARK, SDA2_CIS_MARK, HSCK0_MARK, TS_SDEN0_MARK,
+        DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
+        DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
+        LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
+        LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
+        LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
+        DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
+        SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
+        SCIFA2_RXD_B_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
+        DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
+        DU2_DG6_MARK, LCDOUT14_MARK,
+
+        MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
+        DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
+        MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
+        ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, HRX0_C_MARK,
+        USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
+        TCLK1_B_MARK,
+        PINMUX_MARK_END,
+};
+
+static const pinmux_enum_t pinmux_data[] = {
+        PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+        PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
+        PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
+        PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS),
+        PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN),
+        PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC),
+        PINMUX_DATA(AVS1_MARK, FN_AVS1),
+        PINMUX_DATA(AVS2_MARK, FN_AVS2),
+        PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0),
+        PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
+
+        PINMUX_IPSR_DATA(IP0_2_0, D0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1),
+        PINMUX_IPSR_DATA(IP0_5_3, D1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1),
+        PINMUX_IPSR_DATA(IP0_8_6, D2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1),
+        PINMUX_IPSR_DATA(IP0_11_9, D3),
+        PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1),
+        PINMUX_IPSR_DATA(IP0_15_12, D4),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1),
+        PINMUX_IPSR_DATA(IP0_19_16, D5),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1),
+        PINMUX_IPSR_DATA(IP0_22_20, D6),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_C, SEL_IIC2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_CIS_C, SEL_I2C2_2),
+        PINMUX_IPSR_DATA(IP0_26_23, D7),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_C, SEL_IIC2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_CIS_C, SEL_I2C2_2),
+        PINMUX_IPSR_DATA(IP0_30_27, D8),
+        PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
+        PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),
+        PINMUX_IPSR_DATA(IP0_30_27, MII_TXD0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
+
+        PINMUX_IPSR_DATA(IP1_3_0, D9),
+        PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
+        PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),
+        PINMUX_IPSR_DATA(IP1_3_0, MII_TXD1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_7_4, D10),
+        PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
+        PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),
+        PINMUX_IPSR_DATA(IP1_7_4, MII_TXD2),
+        PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_11_8, D11),
+        PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
+        PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),
+        PINMUX_IPSR_DATA(IP1_11_8, MII_TXD3),
+        PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_14_12, D12),
+        PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
+        PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4),
+        PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_17_15, D13),
+        PINMUX_IPSR_MODSEL_DATA(IP1_17_15, AVB_TXD5, SEL_SCIFA1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_21_18, D14),
+        PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
+        PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6),
+        PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_25_22, D15),
+        PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
+        PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7),
+        PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_27_26, A0),
+        PINMUX_IPSR_DATA(IP1_27_26, PWM3),
+        PINMUX_IPSR_DATA(IP1_29_28, A1),
+        PINMUX_IPSR_DATA(IP1_29_28, PWM4),
+
+        PINMUX_IPSR_DATA(IP2_2_0, A2),
+        PINMUX_IPSR_DATA(IP2_2_0, PWM5),
+        PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
+        PINMUX_IPSR_DATA(IP2_5_3, A3),
+        PINMUX_IPSR_DATA(IP2_5_3, PWM6),
+        PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
+        PINMUX_IPSR_DATA(IP2_8_6, A4),
+        PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
+        PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0),
+        PINMUX_IPSR_DATA(IP2_11_9, A5),
+        PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
+        PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1),
+        PINMUX_IPSR_DATA(IP2_14_12, A6),
+        PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
+        PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2),
+        PINMUX_IPSR_DATA(IP2_17_15, A7),
+        PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
+        PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B),
+        PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3),
+        PINMUX_IPSR_DATA(IP2_21_18, A8),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP2_25_22, A9),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP2_28_26, A10),
+        PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
+        PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC),
+        PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
+
+        PINMUX_IPSR_DATA(IP3_3_0, A11),
+        PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
+        PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK),
+        PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP3_3_0, VI2_G0),
+        PINMUX_IPSR_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B),
+        PINMUX_IPSR_DATA(IP3_7_4, A12),
+        PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
+        PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD),
+        PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP3_7_4, VI2_G1),
+        PINMUX_IPSR_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B),
+        PINMUX_IPSR_DATA(IP3_11_8, A13),
+        PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
+        PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2),
+        PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD),
+        PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP3_11_8, VI2_G2),
+        PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP3_14_12, A14),
+        PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
+        PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N),
+        PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1),
+        PINMUX_IPSR_DATA(IP3_17_15, A15),
+        PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
+        PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N),
+        PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2),
+        PINMUX_IPSR_DATA(IP3_19_18, A16),
+        PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N),
+        PINMUX_IPSR_DATA(IP3_22_20, A17),
+        PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1),
+        PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N),
+        PINMUX_IPSR_DATA(IP3_25_23, A18),
+        PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1),
+        PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N),
+        PINMUX_IPSR_DATA(IP3_28_26, A19),
+        PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
+        PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N),
+        PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
+        PINMUX_IPSR_DATA(IP3_31_29, A20),
+        PINMUX_IPSR_DATA(IP3_31_29, SPCLK),
+        PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP3_31_29, VI2_G4),
+
+        PINMUX_IPSR_DATA(IP4_2_0, A21),
+        PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_2_0, VI2_G5),
+        PINMUX_IPSR_DATA(IP4_5_3, A22),
+        PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_5_3, VI2_G6),
+        PINMUX_IPSR_DATA(IP4_8_6, A23),
+        PINMUX_IPSR_DATA(IP4_8_6, IO2),
+        PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_8_6, VI2_G7),
+        PINMUX_IPSR_DATA(IP4_11_9, A24),
+        PINMUX_IPSR_DATA(IP4_11_9, IO3),
+        PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP4_14_12, A25),
+        PINMUX_IPSR_DATA(IP4_14_12, SSL),
+        PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP4_17_15, CS0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_17_15, VI2_G3),
+        PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
+        PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26),
+        PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN),
+        PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_23_21, VI2_R0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
+        PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N),
+        PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_26_24, VI2_R1),
+        PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N),
+        PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN),
+        PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB),
+        PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_29_27, VI2_R2),
+
+        PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N),
+        PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG),
+        PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD),
+        PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP5_2_0, VI2_R3),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, EX_CS4_N, SEL_I2C1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
+        PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1, SEL_IIC1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1_CIS, SEL_I2C1_0),
+        PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
+        PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP5_9_6, VI2_R4),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1, SEL_IIC1_0),
+        PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1_CIS, SEL_I2C1_0),
+        PINMUX_IPSR_DATA(IP5_12_10, BS_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0),
+        PINMUX_IPSR_DATA(IP5_12_10, DRACK0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2),
+        PINMUX_IPSR_DATA(IP5_14_13, RD_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
+        PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP5_17_15, VI2_R5),
+        PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
+        PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N),
+        PINMUX_IPSR_DATA(IP5_20_18, WE0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP5_23_21, WE1_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP5_23_21, VI2_R6),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2),
+        PINMUX_IPSR_DATA(IP5_26_24, EX_WAIT0),
+        PINMUX_IPSR_DATA(IP5_26_24, IRQ3),
+        PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
+        PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP5_29_27, VI2_R7),
+        PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
+        PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
+
+        PINMUX_IPSR_DATA(IP6_2_0, DACK0),
+        PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
+        PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
+        PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
+        PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
+        PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
+        PINMUX_IPSR_DATA(IP6_8_6, DACK1),
+        PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
+        PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
+        PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
+        PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
+        PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
+        PINMUX_IPSR_DATA(IP6_13_11, DACK2),
+        PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
+        PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
+        PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
+        PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
+        PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV),
+        PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
+        PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4),
+        PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4),
+        PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
+        PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4),
+        PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
+        PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
+        PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
+        PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
+        PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
+        PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK),
+        PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
+        PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
+        PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
+        PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
+        PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
+        PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
+
+        PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
+        PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO),
+        PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
+        PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
+        PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
+        PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4),
+        PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5),
+        PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
+        PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN),
+        PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
+        PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
+        PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC),
+        PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
+        PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
+        PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0),
+        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
+        PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
+        PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC),
+        PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
+        PINMUX_IPSR_DATA(IP7_18_16, PWM0),
+        PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
+        PINMUX_IPSR_DATA(IP7_21_19, PWM1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
+        PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
+        PINMUX_IPSR_DATA(IP7_24_22, PWM2),
+        PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
+        PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
+        PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
+        PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
+        PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN),
+        PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
+        PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
+        PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
+        PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
+        PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
+        PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
+        PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2),
+
+        PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
+        PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
+        PINMUX_IPSR_DATA(IP8_1_0, MII_RXD3),
+        PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
+        PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
+        PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N),
+        PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5),
+        PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N),
+        PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6),
+        PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1),
+        PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
+        PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
+        PINMUX_IPSR_DATA(IP8_11_10, MII_RX_ER),
+        PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
+        PINMUX_IPSR_DATA(IP8_13_12, MII_RX_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),
+        PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
+        PINMUX_IPSR_DATA(IP8_15_14, MII_RX_DV),
+        PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
+        PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
+        PINMUX_IPSR_DATA(IP8_17_16, MII_CRS),
+        PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
+        PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
+        PINMUX_IPSR_DATA(IP8_19_18, MII_MDC),
+        PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
+        PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
+        PINMUX_IPSR_DATA(IP8_21_20, MII_MDIO),
+        PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
+        PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
+        PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
+        PINMUX_IPSR_DATA(IP8_25_24, MII_MAGIC),
+        PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
+        PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
+        PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD),
+        PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
+
+        PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2),
+        PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3),
+        PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP9_11_8, SD0_CD),
+        PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
+        PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_B, SEL_IIC1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_CIS_B, SEL_I2C1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
+        PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
+        PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_B, SEL_IIC1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_CIS_B, SEL_I2C1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
+        PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
+        PINMUX_IPSR_DATA(IP9_17_16, MII_TX_EN),
+        PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
+        PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
+        PINMUX_IPSR_DATA(IP9_19_18, MII_TX_ER),
+        PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
+        PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
+        PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
+        PINMUX_IPSR_DATA(IP9_21_20, MII_TX_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
+        PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
+        PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
+        PINMUX_IPSR_DATA(IP9_23_22, MII_LINK),
+        PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
+        PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
+        PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
+        PINMUX_IPSR_DATA(IP9_25_24, MII_COL),
+        PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
+        PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
+        PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
+        PINMUX_IPSR_DATA(IP9_27_26, MII_RXD0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
+        PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
+        PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
+        PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_D, SEL_IIC2_3),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_CIS_D, SEL_I2C2_3),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
+
+        PINMUX_IPSR_DATA(IP10_3_0, SD1_WP),
+        PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
+        PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_D, SEL_IIC2_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_CIS_D, SEL_I2C2_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1),
+        PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
+        PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD),
+        PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0),
+        PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
+        PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, RDS_DATA, SEL_RDS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
+        PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, RDS_CLK, SEL_RDS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3),
+        PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_29_26, SD2_CD),
+        PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
+        PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
+
+        PINMUX_IPSR_DATA(IP11_3_0, SD2_WP),
+        PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
+        PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP11_4, SD3_CLK),
+        PINMUX_IPSR_DATA(IP11_4, MMC1_CLK),
+        PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD),
+        PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD),
+        PINMUX_IPSR_DATA(IP11_6_5, MTS_N),
+        PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0),
+        PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0),
+        PINMUX_IPSR_DATA(IP11_8_7, STM_N),
+        PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1),
+        PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1),
+        PINMUX_IPSR_DATA(IP11_10_9, MDATA),
+        PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2),
+        PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2),
+        PINMUX_IPSR_DATA(IP11_12_11, SDATA),
+        PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3),
+        PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3),
+        PINMUX_IPSR_DATA(IP11_14_13, SCKZ),
+        PINMUX_IPSR_DATA(IP11_17_15, SD3_CD),
+        PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4),
+        PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
+        PINMUX_IPSR_DATA(IP11_17_15, VSP),
+        PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
+        PINMUX_IPSR_DATA(IP11_21_18, SD3_WP),
+        PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_B, SEL_RDS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_D, SEL_RDS_3),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_E, SEL_RDS_4),
+        PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_B, SEL_IIC2_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_CIS_B, SEL_I2C2_1),
+        PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
+        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_B, SEL_IIC2_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_CIS_B, SEL_I2C2_1),
+        PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
+        PINMUX_IPSR_DATA(IP11_29_27, SPV_EVEN),
+        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2),
+        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RDS_CLK_B, SEL_RDS_1),
+        PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
+        PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
+        PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
+
+        PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129),
+        PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
+        PINMUX_IPSR_DATA(IP12_1_0, MOUT1),
+        PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
+        PINMUX_IPSR_DATA(IP12_3_2, MOUT2),
+        PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1),
+        PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
+        PINMUX_IPSR_DATA(IP12_5_4, MOUT5),
+        PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2),
+        PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_TX_B, SEL_CAN1_1),
+        PINMUX_IPSR_DATA(IP12_7_6, MOUT6),
+        PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34),
+        PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
+        PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
+        PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34),
+        PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
+        PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC),
+        PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0),
+        PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3),
+        PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
+        PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK),
+        PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4),
+        PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
+        PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0),
+        PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4),
+        PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
+        PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1),
+        PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4),
+        PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
+        PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2),
+        PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1),
+        PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
+        PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS),
+        PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3),
+        PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1),
+        PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
+        PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE),
+        PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4),
+
+        PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1),
+        PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2),
+        PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2),
+        PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_C, SEL_RDS_2),
+        PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3),
+        PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3),
+        PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_E, SEL_RDS_4),
+        PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
+        PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4),
+        PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4),
+        PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7),
+        PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3),
+        PINMUX_IPSR_MODSEL_DATA(IP13_12_10, RDS_DATA_C, SEL_RDS_2),
+        PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5),
+        PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5),
+        PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8),
+        PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
+        PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6),
+        PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6),
+        PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9),
+        PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
+        PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N),
+        PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7),
+        PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7),
+        PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
+        PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N),
+        PINMUX_IPSR_DATA(IP13_22_19, TCLK2),
+        PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS),
+        PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_CLK_D, SEL_RDS_3),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_DATA_F, SEL_RDS_5),
+        PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
+        PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12),
+        PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
+        PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9),
+        PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
+        PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1),
+        PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
+        PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13),
+        PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA),
+        PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
+        PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14),
+
+        PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB),
+        PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
+        PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE),
+        PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
+        PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15),
+        PINMUX_IPSR_DATA(IP14_2_0, REMOCON),
+        PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0),
+        PINMUX_IPSR_DATA(IP14_5_3, SCK0),
+        PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2),
+        PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2),
+        PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10),
+        PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_C, SEL_IIC1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_CIS_C, SEL_I2C1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0),
+        PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0),
+        PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0),
+        PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1),
+        PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, CTS0_N, SEL_SCIF0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
+        PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, LCDOUT11, SEL_HSCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, PWM0_B, SEL_SCIF0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_C, SEL_IIC1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_CIS_C, SEL_I2C1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
+        PINMUX_IPSR_DATA(IP14_18_16, RTS0_N_TANS),
+        PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1),
+        PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0),
+        PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8),
+        PINMUX_IPSR_DATA(IP14_18_16, PWM1_B),
+        PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0),
+        PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
+        PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE),
+        PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0),
+        PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1),
+        PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9),
+        PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0),
+        PINMUX_IPSR_DATA(IP14_27_25, CTS1_N),
+        PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
+        PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT),
+        PINMUX_IPSR_DATA(IP14_27_25, QCLK),
+        PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0),
+        PINMUX_IPSR_DATA(IP14_30_28, RTS1_N_TANS),
+        PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
+        PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT),
+        PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE),
+        PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
+
+        PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
+        PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7),
+        PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15),
+        PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0),
+        PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0),
+        PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16),
+        PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2, SEL_IIC2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2_CIS, SEL_I2C2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0),
+        PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1),
+        PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17),
+        PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2, SEL_IIC2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2_CIS, SEL_I2C2_0),
+        PINMUX_IPSR_DATA(IP15_11_9, HSCK0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
+        PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4),
+        PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12),
+        PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_IIC2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SDA2_CIS, SEL_I2C2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0),
+        PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2),
+        PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18),
+        PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0),
+        PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3),
+        PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19),
+        PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
+        PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9),
+        PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4),
+        PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20),
+        PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
+        PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9),
+        PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5),
+        PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21),
+        PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
+        PINMUX_IPSR_DATA(IP15_22_20, ADICLK),
+        PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6),
+        PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22),
+        PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC),
+        PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
+        PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2),
+        PINMUX_IPSR_DATA(IP15_25_23, ADIDATA),
+        PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7),
+        PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23),
+        PINMUX_IPSR_MODSEL_DATA(IP15_25_23, SCIFA2_RXD_B, SEL_SCIFA2_1),
+        PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
+        PINMUX_IPSR_DATA(IP15_27_26, ADICHS0),
+        PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5),
+        PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13),
+        PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
+        PINMUX_IPSR_DATA(IP15_29_28, ADICHS1),
+        PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6),
+        PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14),
+
+        PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
+        PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT),
+        PINMUX_IPSR_DATA(IP16_2_0, ADICHS2),
+        PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP),
+        PINMUX_IPSR_DATA(IP16_2_0, QPOLA),
+        PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
+        PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
+        PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2),
+        PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP),
+        PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE),
+        PINMUX_IPSR_DATA(IP16_5_3, QPOLB),
+        PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HRX0_C, SEL_HSCIF0_2),
+        PINMUX_IPSR_DATA(IP16_6, USB1_PWEN),
+        PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
+        PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
+        PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
+};
+
+static struct sh_pfc_pin pinmux_pins[] = {
+        PINMUX_GPIO_GP_ALL(),
+};
+
+/* - ETH -------------------------------------------------------------------- */
+static const unsigned int eth_link_pins[] = {
+        /* LINK */
+        RCAR_GP_PIN(2, 22),
+};
+static const unsigned int eth_link_mux[] = {
+        ETH_LINK_MARK,
+};
+static const unsigned int eth_magic_pins[] = {
+        /* MAGIC */
+        RCAR_GP_PIN(2, 27),
+};
+static const unsigned int eth_magic_mux[] = {
+        ETH_MAGIC_MARK,
+};
+static const unsigned int eth_mdio_pins[] = {
+        /* MDC, MDIO */
+        RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
+};
+static const unsigned int eth_mdio_mux[] = {
+        ETH_MDC_MARK, ETH_MDIO_MARK,
+};
+static const unsigned int eth_rmii_pins[] = {
+        /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
+        RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
+        RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
+        RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
+};
+static const unsigned int eth_rmii_mux[] = {
+        ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
+        ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
+};
+/* - INTC ------------------------------------------------------------------- */
+static const unsigned int intc_irq0_pins[] = {
+        /* IRQ */
+        RCAR_GP_PIN(1, 25),
+};
+static const unsigned int intc_irq0_mux[] = {
+        IRQ0_MARK,
+};
+static const unsigned int intc_irq1_pins[] = {
+        /* IRQ */
+        RCAR_GP_PIN(1, 27),
+};
+static const unsigned int intc_irq1_mux[] = {
+        IRQ1_MARK,
+};
+static const unsigned int intc_irq2_pins[] = {
+        /* IRQ */
+        RCAR_GP_PIN(1, 29),
+};
+static const unsigned int intc_irq2_mux[] = {
+        IRQ2_MARK,
+};
+static const unsigned int intc_irq3_pins[] = {
+        /* IRQ */
+        RCAR_GP_PIN(1, 23),
+};
+static const unsigned int intc_irq3_mux[] = {
+        IRQ3_MARK,
+};
+/* - SCIF0 ----------------------------------------------------------------- */
+static const unsigned int scif0_data_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
+};
+static const unsigned int scif0_data_mux[] = {
+        RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 27),
+};
+static const unsigned int scif0_clk_mux[] = {
+        SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+        RTS0_N_TANS_MARK, CTS0_N_MARK,
+};
+static const unsigned int scif0_data_b_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int scif0_data_b_mux[] = {
+        RX0_B_MARK, TX0_B_MARK,
+};
+/* - SCIF1 ----------------------------------------------------------------- */
+static const unsigned int scif1_data_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
+};
+static const unsigned int scif1_data_mux[] = {
+        RX1_MARK, TX1_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 20),
+};
+static const unsigned int scif1_clk_mux[] = {
+        SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+        RTS1_N_TANS_MARK, CTS1_N_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+static const unsigned int scif1_data_b_mux[] = {
+        RX1_B_MARK, TX1_B_MARK,
+};
+static const unsigned int scif1_data_c_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int scif1_data_c_mux[] = {
+        RX1_C_MARK, TX1_C_MARK,
+};
+static const unsigned int scif1_data_d_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+};
+static const unsigned int scif1_data_d_mux[] = {
+        RX1_D_MARK, TX1_D_MARK,
+};
+static const unsigned int scif1_clk_d_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(3, 17),
+};
+static const unsigned int scif1_clk_d_mux[] = {
+        SCK1_D_MARK,
+};
+static const unsigned int scif1_data_e_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+};
+static const unsigned int scif1_data_e_mux[] = {
+        RX1_E_MARK, TX1_E_MARK,
+};
+static const unsigned int scif1_clk_e_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(2, 20),
+};
+static const unsigned int scif1_clk_e_mux[] = {
+        SCK1_E_MARK,
+};
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
+};
+static const unsigned int scifa0_data_mux[] = {
+        SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 27),
+};
+static const unsigned int scifa0_clk_mux[] = {
+        SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+        SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
+};
+static const unsigned int scifa0_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
+};
+static const unsigned int scifa0_data_b_mux[] = {
+        SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
+};
+static const unsigned int scifa0_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(1, 19),
+};
+static const unsigned int scifa0_clk_b_mux[] = {
+        SCIFA0_SCK_B_MARK,
+};
+static const unsigned int scifa0_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
+};
+static const unsigned int scifa0_ctrl_b_mux[] = {
+        SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
+};
+static const unsigned int scifa1_data_mux[] = {
+        SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 20),
+};
+static const unsigned int scifa1_clk_mux[] = {
+        SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+        SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
+};
+static const unsigned int scifa1_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
+};
+static const unsigned int scifa1_data_b_mux[] = {
+        SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
+};
+static const unsigned int scifa1_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(0, 23),
+};
+static const unsigned int scifa1_clk_b_mux[] = {
+        SCIFA1_SCK_B_MARK,
+};
+static const unsigned int scifa1_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
+};
+static const unsigned int scifa1_ctrl_b_mux[] = {
+        SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
+};
+static const unsigned int scifa1_data_c_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+};
+static const unsigned int scifa1_data_c_mux[] = {
+        SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
+};
+static const unsigned int scifa1_clk_c_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(0, 8),
+};
+static const unsigned int scifa1_clk_c_mux[] = {
+        SCIFA1_SCK_C_MARK,
+};
+static const unsigned int scifa1_ctrl_c_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
+};
+static const unsigned int scifa1_ctrl_c_mux[] = {
+        SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
+};
+static const unsigned int scifa1_data_d_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+};
+static const unsigned int scifa1_data_d_mux[] = {
+        SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
+};
+static const unsigned int scifa1_clk_d_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(2, 10),
+};
+static const unsigned int scifa1_clk_d_mux[] = {
+        SCIFA1_SCK_D_MARK,
+};
+static const unsigned int scifa1_ctrl_d_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int scifa1_ctrl_d_mux[] = {
+        SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+static const unsigned int scifa2_data_mux[] = {
+        SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
+};
+static const unsigned int scifa2_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(5, 4),
+};
+static const unsigned int scifa2_clk_mux[] = {
+        SCIFA2_SCK_MARK,
+};
+static const unsigned int scifa2_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
+};
+static const unsigned int scifa2_ctrl_mux[] = {
+        SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
+};
+static const unsigned int scifa2_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
+};
+static const unsigned int scifa2_data_b_mux[] = {
+        SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
+};
+static const unsigned int scifa2_data_c_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
+};
+static const unsigned int scifa2_data_c_mux[] = {
+        SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
+};
+static const unsigned int scifa2_clk_c_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(5, 29),
+};
+static const unsigned int scifa2_clk_c_mux[] = {
+        SCIFA2_SCK_C_MARK,
+};
+/* - SCIFB0 ----------------------------------------------------------------- */
+static const unsigned int scifb0_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
+};
+static const unsigned int scifb0_data_mux[] = {
+        SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
+};
+static const unsigned int scifb0_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 8),
+};
+static const unsigned int scifb0_clk_mux[] = {
+        SCIFB0_SCK_MARK,
+};
+static const unsigned int scifb0_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
+};
+static const unsigned int scifb0_ctrl_mux[] = {
+        SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
+};
+static const unsigned int scifb0_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+static const unsigned int scifb0_data_b_mux[] = {
+        SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
+};
+static const unsigned int scifb0_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(3, 9),
+};
+static const unsigned int scifb0_clk_b_mux[] = {
+        SCIFB0_SCK_B_MARK,
+};
+static const unsigned int scifb0_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
+};
+static const unsigned int scifb0_ctrl_b_mux[] = {
+        SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
+};
+static const unsigned int scifb0_data_c_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int scifb0_data_c_mux[] = {
+        SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
+};
+/* - SCIFB1 ----------------------------------------------------------------- */
+static const unsigned int scifb1_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
+};
+static const unsigned int scifb1_data_mux[] = {
+        SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
+};
+static const unsigned int scifb1_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 14),
+};
+static const unsigned int scifb1_clk_mux[] = {
+        SCIFB1_SCK_MARK,
+};
+static const unsigned int scifb1_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
+};
+static const unsigned int scifb1_ctrl_mux[] = {
+        SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
+};
+static const unsigned int scifb1_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+};
+static const unsigned int scifb1_data_b_mux[] = {
+        SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
+};
+static const unsigned int scifb1_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(3, 1),
+};
+static const unsigned int scifb1_clk_b_mux[] = {
+        SCIFB1_SCK_B_MARK,
+};
+static const unsigned int scifb1_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
+};
+static const unsigned int scifb1_ctrl_b_mux[] = {
+        SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
+};
+static const unsigned int scifb1_data_c_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+static const unsigned int scifb1_data_c_mux[] = {
+        SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
+};
+static const unsigned int scifb1_data_d_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int scifb1_data_d_mux[] = {
+        SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
+};
+static const unsigned int scifb1_data_e_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+};
+static const unsigned int scifb1_data_e_mux[] = {
+        SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
+};
+static const unsigned int scifb1_clk_e_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(3, 17),
+};
+static const unsigned int scifb1_clk_e_mux[] = {
+        SCIFB1_SCK_E_MARK,
+};
+static const unsigned int scifb1_data_f_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int scifb1_data_f_mux[] = {
+        SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
+};
+static const unsigned int scifb1_data_g_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+};
+static const unsigned int scifb1_data_g_mux[] = {
+        SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
+};
+static const unsigned int scifb1_clk_g_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(2, 20),
+};
+static const unsigned int scifb1_clk_g_mux[] = {
+        SCIFB1_SCK_G_MARK,
+};
+/* - SCIFB2 ----------------------------------------------------------------- */
+static const unsigned int scifb2_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
+};
+static const unsigned int scifb2_data_mux[] = {
+        SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
+};
+static const unsigned int scifb2_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 21),
+};
+static const unsigned int scifb2_clk_mux[] = {
+        SCIFB2_SCK_MARK,
+};
+static const unsigned int scifb2_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
+};
+static const unsigned int scifb2_ctrl_mux[] = {
+        SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
+};
+static const unsigned int scifb2_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
+};
+static const unsigned int scifb2_data_b_mux[] = {
+        SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
+};
+static const unsigned int scifb2_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(0, 31),
+};
+static const unsigned int scifb2_clk_b_mux[] = {
+        SCIFB2_SCK_B_MARK,
+};
+static const unsigned int scifb2_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
+};
+static const unsigned int scifb2_ctrl_b_mux[] = {
+        SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
+};
+static const unsigned int scifb2_data_c_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
+};
+static const unsigned int scifb2_data_c_mux[] = {
+        SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
+};
+/* - TPU0 ------------------------------------------------------------------- */
+static const unsigned int tpu0_to0_pins[] = {
+        /* TO */
+        RCAR_GP_PIN(0, 20),
+};
+static const unsigned int tpu0_to0_mux[] = {
+        TPU0TO0_MARK,
+};
+static const unsigned int tpu0_to1_pins[] = {
+        /* TO */
+        RCAR_GP_PIN(0, 21),
+};
+static const unsigned int tpu0_to1_mux[] = {
+        TPU0TO1_MARK,
+};
+static const unsigned int tpu0_to2_pins[] = {
+        /* TO */
+        RCAR_GP_PIN(0, 22),
+};
+static const unsigned int tpu0_to2_mux[] = {
+        TPU0TO2_MARK,
+};
+static const unsigned int tpu0_to3_pins[] = {
+        /* TO */
+        RCAR_GP_PIN(0, 23),
+};
+static const unsigned int tpu0_to3_mux[] = {
+        TPU0TO3_MARK,
+};
+
+/* - MMCIF ------------------------------------------------------------------ */
+static const unsigned int mmc0_data1_pins[] = {
+        /* D[0] */
+        RCAR_GP_PIN(3, 18),
+};
+static const unsigned int mmc0_data1_mux[] = {
+        MMC0_D0_MARK,
+};
+static const unsigned int mmc0_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+        RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+};
+static const unsigned int mmc0_data4_mux[] = {
+        MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
+};
+static const unsigned int mmc0_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+        RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+        RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
+        RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+static const unsigned int mmc0_data8_mux[] = {
+        MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
+        MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
+};
+static const unsigned int mmc0_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
+};
+static const unsigned int mmc0_ctrl_mux[] = {
+        MMC0_CLK_MARK, MMC0_CMD_MARK,
+};
+
+static const unsigned int mmc1_data1_pins[] = {
+        /* D[0] */
+        RCAR_GP_PIN(3, 26),
+};
+static const unsigned int mmc1_data1_mux[] = {
+        MMC1_D0_MARK,
+};
+static const unsigned int mmc1_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
+        RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
+};
+static const unsigned int mmc1_data4_mux[] = {
+        MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
+};
+static const unsigned int mmc1_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
+        RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
+        RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
+        RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+};
+static const unsigned int mmc1_data8_mux[] = {
+        MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
+        MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
+};
+static const unsigned int mmc1_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
+};
+static const unsigned int mmc1_ctrl_mux[] = {
+        MMC1_CLK_MARK, MMC1_CMD_MARK,
+};
+
+/* - SDHI ------------------------------------------------------------------- */
+static const unsigned int sdhi0_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(3, 2),
+};
+static const unsigned int sdhi0_data1_mux[] = {
+        SD0_DAT0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+};
+static const unsigned int sdhi0_data4_mux[] = {
+        SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+        SD0_CLK_MARK, SD0_CMD_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(3, 6),
+};
+static const unsigned int sdhi0_cd_mux[] = {
+        SD0_CD_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(3, 7),
+};
+static const unsigned int sdhi0_wp_mux[] = {
+        SD0_WP_MARK,
+};
+
+static const unsigned int sdhi1_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(3, 10),
+};
+static const unsigned int sdhi1_data1_mux[] = {
+        SD1_DAT0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+};
+static const unsigned int sdhi1_data4_mux[] = {
+        SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+        SD1_CLK_MARK, SD1_CMD_MARK,
+};
+static const unsigned int sdhi1_cd_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(3, 14),
+};
+static const unsigned int sdhi1_cd_mux[] = {
+        SD1_CD_MARK,
+};
+static const unsigned int sdhi1_wp_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(3, 15),
+};
+static const unsigned int sdhi1_wp_mux[] = {
+        SD1_WP_MARK,
+};
+
+static const unsigned int sdhi2_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(3, 18),
+};
+static const unsigned int sdhi2_data1_mux[] = {
+        SD2_DAT0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+};
+static const unsigned int sdhi2_data4_mux[] = {
+        SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+        SD2_CLK_MARK, SD2_CMD_MARK,
+};
+static const unsigned int sdhi2_cd_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(3, 22),
+};
+static const unsigned int sdhi2_cd_mux[] = {
+        SD2_CD_MARK,
+};
+static const unsigned int sdhi2_wp_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(3, 23),
+};
+static const unsigned int sdhi2_wp_mux[] = {
+        SD2_WP_MARK,
+};
+
+static const unsigned int sdhi3_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(3, 26),
+};
+static const unsigned int sdhi3_data1_mux[] = {
+        SD3_DAT0_MARK,
+};
+static const unsigned int sdhi3_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
+};
+static const unsigned int sdhi3_data4_mux[] = {
+        SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
+};
+static const unsigned int sdhi3_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
+};
+static const unsigned int sdhi3_ctrl_mux[] = {
+        SD3_CLK_MARK, SD3_CMD_MARK,
+};
+static const unsigned int sdhi3_cd_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(3, 30),
+};
+static const unsigned int sdhi3_cd_mux[] = {
+        SD3_CD_MARK,
+};
+static const unsigned int sdhi3_wp_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(3, 31),
+};
+static const unsigned int sdhi3_wp_mux[] = {
+        SD3_WP_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(eth_link),
+        SH_PFC_PIN_GROUP(eth_magic),
+        SH_PFC_PIN_GROUP(eth_mdio),
+        SH_PFC_PIN_GROUP(eth_rmii),
+        SH_PFC_PIN_GROUP(intc_irq0),
+        SH_PFC_PIN_GROUP(intc_irq1),
+        SH_PFC_PIN_GROUP(intc_irq2),
+        SH_PFC_PIN_GROUP(intc_irq3),
+        SH_PFC_PIN_GROUP(scif0_data),
+        SH_PFC_PIN_GROUP(scif0_clk),
+        SH_PFC_PIN_GROUP(scif0_ctrl),
+        SH_PFC_PIN_GROUP(scif0_data_b),
+        SH_PFC_PIN_GROUP(scif1_data),
+        SH_PFC_PIN_GROUP(scif1_clk),
+        SH_PFC_PIN_GROUP(scif1_ctrl),
+        SH_PFC_PIN_GROUP(scif1_data_b),
+        SH_PFC_PIN_GROUP(scif1_data_c),
+        SH_PFC_PIN_GROUP(scif1_data_d),
+        SH_PFC_PIN_GROUP(scif1_clk_d),
+        SH_PFC_PIN_GROUP(scif1_data_e),
+        SH_PFC_PIN_GROUP(scif1_clk_e),
+        SH_PFC_PIN_GROUP(scifa0_data),
+        SH_PFC_PIN_GROUP(scifa0_clk),
+        SH_PFC_PIN_GROUP(scifa0_ctrl),
+        SH_PFC_PIN_GROUP(scifa0_data_b),
+        SH_PFC_PIN_GROUP(scifa0_clk_b),
+        SH_PFC_PIN_GROUP(scifa0_ctrl_b),
+        SH_PFC_PIN_GROUP(scifa1_data),
+        SH_PFC_PIN_GROUP(scifa1_clk),
+        SH_PFC_PIN_GROUP(scifa1_ctrl),
+        SH_PFC_PIN_GROUP(scifa1_data_b),
+        SH_PFC_PIN_GROUP(scifa1_clk_b),
+        SH_PFC_PIN_GROUP(scifa1_ctrl_b),
+        SH_PFC_PIN_GROUP(scifa1_data_c),
+        SH_PFC_PIN_GROUP(scifa1_clk_c),
+        SH_PFC_PIN_GROUP(scifa1_ctrl_c),
+        SH_PFC_PIN_GROUP(scifa1_data_d),
+        SH_PFC_PIN_GROUP(scifa1_clk_d),
+        SH_PFC_PIN_GROUP(scifa1_ctrl_d),
+        SH_PFC_PIN_GROUP(scifa2_data),
+        SH_PFC_PIN_GROUP(scifa2_clk),
+        SH_PFC_PIN_GROUP(scifa2_ctrl),
+        SH_PFC_PIN_GROUP(scifa2_data_b),
+        SH_PFC_PIN_GROUP(scifa2_data_c),
+        SH_PFC_PIN_GROUP(scifa2_clk_c),
+        SH_PFC_PIN_GROUP(scifb0_data),
+        SH_PFC_PIN_GROUP(scifb0_clk),
+        SH_PFC_PIN_GROUP(scifb0_ctrl),
+        SH_PFC_PIN_GROUP(scifb0_data_b),
+        SH_PFC_PIN_GROUP(scifb0_clk_b),
+        SH_PFC_PIN_GROUP(scifb0_ctrl_b),
+        SH_PFC_PIN_GROUP(scifb0_data_c),
+        SH_PFC_PIN_GROUP(scifb1_data),
+        SH_PFC_PIN_GROUP(scifb1_clk),
+        SH_PFC_PIN_GROUP(scifb1_ctrl),
+        SH_PFC_PIN_GROUP(scifb1_data_b),
+        SH_PFC_PIN_GROUP(scifb1_clk_b),
+        SH_PFC_PIN_GROUP(scifb1_ctrl_b),
+        SH_PFC_PIN_GROUP(scifb1_data_c),
+        SH_PFC_PIN_GROUP(scifb1_data_d),
+        SH_PFC_PIN_GROUP(scifb1_data_e),
+        SH_PFC_PIN_GROUP(scifb1_clk_e),
+        SH_PFC_PIN_GROUP(scifb1_data_f),
+        SH_PFC_PIN_GROUP(scifb1_data_g),
+        SH_PFC_PIN_GROUP(scifb1_clk_g),
+        SH_PFC_PIN_GROUP(scifb2_data),
+        SH_PFC_PIN_GROUP(scifb2_clk),
+        SH_PFC_PIN_GROUP(scifb2_ctrl),
+        SH_PFC_PIN_GROUP(scifb2_data_b),
+        SH_PFC_PIN_GROUP(scifb2_clk_b),
+        SH_PFC_PIN_GROUP(scifb2_ctrl_b),
+        SH_PFC_PIN_GROUP(scifb2_data_c),
+        SH_PFC_PIN_GROUP(tpu0_to0),
+        SH_PFC_PIN_GROUP(tpu0_to1),
+        SH_PFC_PIN_GROUP(tpu0_to2),
+        SH_PFC_PIN_GROUP(tpu0_to3),
+        SH_PFC_PIN_GROUP(mmc0_data1),
+        SH_PFC_PIN_GROUP(mmc0_data4),
+        SH_PFC_PIN_GROUP(mmc0_data8),
+        SH_PFC_PIN_GROUP(mmc0_ctrl),
+        SH_PFC_PIN_GROUP(mmc1_data1),
+        SH_PFC_PIN_GROUP(mmc1_data4),
+        SH_PFC_PIN_GROUP(mmc1_data8),
+        SH_PFC_PIN_GROUP(mmc1_ctrl),
+        SH_PFC_PIN_GROUP(sdhi0_data1),
+        SH_PFC_PIN_GROUP(sdhi0_data4),
+        SH_PFC_PIN_GROUP(sdhi0_ctrl),
+        SH_PFC_PIN_GROUP(sdhi0_cd),
+        SH_PFC_PIN_GROUP(sdhi0_wp),
+        SH_PFC_PIN_GROUP(sdhi1_data1),
+        SH_PFC_PIN_GROUP(sdhi1_data4),
+        SH_PFC_PIN_GROUP(sdhi1_ctrl),
+        SH_PFC_PIN_GROUP(sdhi1_cd),
+        SH_PFC_PIN_GROUP(sdhi1_wp),
+        SH_PFC_PIN_GROUP(sdhi2_data1),
+        SH_PFC_PIN_GROUP(sdhi2_data4),
+        SH_PFC_PIN_GROUP(sdhi2_ctrl),
+        SH_PFC_PIN_GROUP(sdhi2_cd),
+        SH_PFC_PIN_GROUP(sdhi2_wp),
+        SH_PFC_PIN_GROUP(sdhi3_data1),
+        SH_PFC_PIN_GROUP(sdhi3_data4),
+        SH_PFC_PIN_GROUP(sdhi3_ctrl),
+        SH_PFC_PIN_GROUP(sdhi3_cd),
+        SH_PFC_PIN_GROUP(sdhi3_wp),
+};
+
+static const char * const eth_groups[] = {
+        "eth_link",
+        "eth_magic",
+        "eth_mdio",
+        "eth_rmii",
+};
+
+static const char * const intc_groups[] = {
+        "intc_irq0",
+        "intc_irq1",
+        "intc_irq2",
+        "intc_irq3",
+};
+
+static const char * const scif0_groups[] = {
+        "scif0_data",
+        "scif0_clk",
+        "scif0_ctrl",
+        "scif0_data_b",
+};
+
+static const char * const scif1_groups[] = {
+        "scif1_data",
+        "scif1_clk",
+        "scif1_ctrl",
+        "scif1_data_b",
+        "scif1_data_c",
+        "scif1_data_d",
+        "scif1_clk_d",
+        "scif1_data_e",
+        "scif1_clk_e",
+};
+
+static const char * const scifa0_groups[] = {
+        "scifa0_data",
+        "scifa0_clk",
+        "scifa0_ctrl",
+        "scifa0_data_b",
+        "scifa0_clk_b",
+        "scifa0_ctrl_b",
+};
+
+static const char * const scifa1_groups[] = {
+        "scifa1_data",
+        "scifa1_clk",
+        "scifa1_ctrl",
+        "scifa1_data_b",
+        "scifa1_clk_b",
+        "scifa1_ctrl_b",
+        "scifa1_data_c",
+        "scifa1_clk_c",
+        "scifa1_ctrl_c",
+        "scifa1_data_d",
+        "scifa1_clk_d",
+        "scifa1_ctrl_d",
+};
+
+static const char * const scifa2_groups[] = {
+        "scifa2_data",
+        "scifa2_clk",
+        "scifa2_ctrl",
+        "scifa2_data_b",
+        "scifa2_data_c",
+        "scifa2_clk_c",
+};
+
+static const char * const scifb0_groups[] = {
+        "scifb0_data",
+        "scifb0_clk",
+        "scifb0_ctrl",
+        "scifb0_data_b",
+        "scifb0_clk_b",
+        "scifb0_ctrl_b",
+        "scifb0_data_c",
+};
+
+static const char * const scifb1_groups[] = {
+        "scifb1_data",
+        "scifb1_clk",
+        "scifb1_ctrl",
+        "scifb1_data_b",
+        "scifb1_clk_b",
+        "scifb1_ctrl_b",
+        "scifb1_data_c",
+        "scifb1_data_d",
+        "scifb1_data_e",
+        "scifb1_clk_e",
+        "scifb1_data_f",
+        "scifb1_data_g",
+        "scifb1_clk_g",
+};
+
+static const char * const scifb2_groups[] = {
+        "scifb2_data",
+        "scifb2_clk",
+        "scifb2_ctrl",
+        "scifb2_data_b",
+        "scifb2_clk_b",
+        "scifb2_ctrl_b",
+        "scifb2_data_c",
+};
+
+static const char * const tpu0_groups[] = {
+        "tpu0_to0",
+        "tpu0_to1",
+        "tpu0_to2",
+        "tpu0_to3",
+};
+
+static const char * const mmc0_groups[] = {
+        "mmc0_data1",
+        "mmc0_data4",
+        "mmc0_data8",
+        "mmc0_ctrl",
+};
+
+static const char * const mmc1_groups[] = {
+        "mmc1_data1",
+        "mmc1_data4",
+        "mmc1_data8",
+        "mmc1_ctrl",
+};
+
+static const char * const sdhi0_groups[] = {
+        "sdhi0_data1",
+        "sdhi0_data4",
+        "sdhi0_ctrl",
+        "sdhi0_cd",
+        "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+        "sdhi1_data1",
+        "sdhi1_data4",
+        "sdhi1_ctrl",
+        "sdhi1_cd",
+        "sdhi1_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+        "sdhi2_data1",
+        "sdhi2_data4",
+        "sdhi2_ctrl",
+        "sdhi2_cd",
+        "sdhi2_wp",
+};
+
+static const char * const sdhi3_groups[] = {
+        "sdhi3_data1",
+        "sdhi3_data4",
+        "sdhi3_ctrl",
+        "sdhi3_cd",
+        "sdhi3_wp",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(eth),
+        SH_PFC_FUNCTION(intc),
+        SH_PFC_FUNCTION(scif0),
+        SH_PFC_FUNCTION(scif1),
+        SH_PFC_FUNCTION(scifa0),
+        SH_PFC_FUNCTION(scifa1),
+        SH_PFC_FUNCTION(scifa2),
+        SH_PFC_FUNCTION(scifb0),
+        SH_PFC_FUNCTION(scifb1),
+        SH_PFC_FUNCTION(scifb2),
+        SH_PFC_FUNCTION(tpu0),
+        SH_PFC_FUNCTION(mmc0),
+        SH_PFC_FUNCTION(mmc1),
+        SH_PFC_FUNCTION(sdhi0),
+        SH_PFC_FUNCTION(sdhi1),
+        SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(sdhi3),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+                GP_0_31_FN, FN_IP3_17_15,
+                GP_0_30_FN, FN_IP3_14_12,
+                GP_0_29_FN, FN_IP3_11_8,
+                GP_0_28_FN, FN_IP3_7_4,
+                GP_0_27_FN, FN_IP3_3_0,
+                GP_0_26_FN, FN_IP2_28_26,
+                GP_0_25_FN, FN_IP2_25_22,
+                GP_0_24_FN, FN_IP2_21_18,
+                GP_0_23_FN, FN_IP2_17_15,
+                GP_0_22_FN, FN_IP2_14_12,
+                GP_0_21_FN, FN_IP2_11_9,
+                GP_0_20_FN, FN_IP2_8_6,
+                GP_0_19_FN, FN_IP2_5_3,
+                GP_0_18_FN, FN_IP2_2_0,
+                GP_0_17_FN, FN_IP1_29_28,
+                GP_0_16_FN, FN_IP1_27_26,
+                GP_0_15_FN, FN_IP1_25_22,
+                GP_0_14_FN, FN_IP1_21_18,
+                GP_0_13_FN, FN_IP1_17_15,
+                GP_0_12_FN, FN_IP1_14_12,
+                GP_0_11_FN, FN_IP1_11_8,
+                GP_0_10_FN, FN_IP1_7_4,
+                GP_0_9_FN, FN_IP1_3_0,
+                GP_0_8_FN, FN_IP0_30_27,
+                GP_0_7_FN, FN_IP0_26_23,
+                GP_0_6_FN, FN_IP0_22_20,
+                GP_0_5_FN, FN_IP0_19_16,
+                GP_0_4_FN, FN_IP0_15_12,
+                GP_0_3_FN, FN_IP0_11_9,
+                GP_0_2_FN, FN_IP0_8_6,
+                GP_0_1_FN, FN_IP0_5_3,
+                GP_0_0_FN, FN_IP0_2_0 }
+        },
+        { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+                0, 0,
+                0, 0,
+                GP_1_29_FN, FN_IP6_13_11,
+                GP_1_28_FN, FN_IP6_10_9,
+                GP_1_27_FN, FN_IP6_8_6,
+                GP_1_26_FN, FN_IP6_5_3,
+                GP_1_25_FN, FN_IP6_2_0,
+                GP_1_24_FN, FN_IP5_29_27,
+                GP_1_23_FN, FN_IP5_26_24,
+                GP_1_22_FN, FN_IP5_23_21,
+                GP_1_21_FN, FN_IP5_20_18,
+                GP_1_20_FN, FN_IP5_17_15,
+                GP_1_19_FN, FN_IP5_14_13,
+                GP_1_18_FN, FN_IP5_12_10,
+                GP_1_17_FN, FN_IP5_9_6,
+                GP_1_16_FN, FN_IP5_5_3,
+                GP_1_15_FN, FN_IP5_2_0,
+                GP_1_14_FN, FN_IP4_29_27,
+                GP_1_13_FN, FN_IP4_26_24,
+                GP_1_12_FN, FN_IP4_23_21,
+                GP_1_11_FN, FN_IP4_20_18,
+                GP_1_10_FN, FN_IP4_17_15,
+                GP_1_9_FN, FN_IP4_14_12,
+                GP_1_8_FN, FN_IP4_11_9,
+                GP_1_7_FN, FN_IP4_8_6,
+                GP_1_6_FN, FN_IP4_5_3,
+                GP_1_5_FN, FN_IP4_2_0,
+                GP_1_4_FN, FN_IP3_31_29,
+                GP_1_3_FN, FN_IP3_28_26,
+                GP_1_2_FN, FN_IP3_25_23,
+                GP_1_1_FN, FN_IP3_22_20,
+                GP_1_0_FN, FN_IP3_19_18, }
+        },
+        { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+                0, 0,
+                0, 0,
+                GP_2_29_FN, FN_IP7_15_13,
+                GP_2_28_FN, FN_IP7_12_10,
+                GP_2_27_FN, FN_IP7_9_8,
+                GP_2_26_FN, FN_IP7_7_6,
+                GP_2_25_FN, FN_IP7_5_3,
+                GP_2_24_FN, FN_IP7_2_0,
+                GP_2_23_FN, FN_IP6_31_29,
+                GP_2_22_FN, FN_IP6_28_26,
+                GP_2_21_FN, FN_IP6_25_23,
+                GP_2_20_FN, FN_IP6_22_20,
+                GP_2_19_FN, FN_IP6_19_17,
+                GP_2_18_FN, FN_IP6_16_14,
+                GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
+                GP_2_16_FN, FN_IP8_27,
+                GP_2_15_FN, FN_IP8_26,
+                GP_2_14_FN, FN_IP8_25_24,
+                GP_2_13_FN, FN_IP8_23_22,
+                GP_2_12_FN, FN_IP8_21_20,
+                GP_2_11_FN, FN_IP8_19_18,
+                GP_2_10_FN, FN_IP8_17_16,
+                GP_2_9_FN, FN_IP8_15_14,
+                GP_2_8_FN, FN_IP8_13_12,
+                GP_2_7_FN, FN_IP8_11_10,
+                GP_2_6_FN, FN_IP8_9_8,
+                GP_2_5_FN, FN_IP8_7_6,
+                GP_2_4_FN, FN_IP8_5_4,
+                GP_2_3_FN, FN_IP8_3_2,
+                GP_2_2_FN, FN_IP8_1_0,
+                GP_2_1_FN, FN_IP7_30_29,
+                GP_2_0_FN, FN_IP7_28_27 }
+        },
+        { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+                GP_3_31_FN, FN_IP11_21_18,
+                GP_3_30_FN, FN_IP11_17_15,
+                GP_3_29_FN, FN_IP11_14_13,
+                GP_3_28_FN, FN_IP11_12_11,
+                GP_3_27_FN, FN_IP11_10_9,
+                GP_3_26_FN, FN_IP11_8_7,
+                GP_3_25_FN, FN_IP11_6_5,
+                GP_3_24_FN, FN_IP11_4,
+                GP_3_23_FN, FN_IP11_3_0,
+                GP_3_22_FN, FN_IP10_29_26,
+                GP_3_21_FN, FN_IP10_25_23,
+                GP_3_20_FN, FN_IP10_22_19,
+                GP_3_19_FN, FN_IP10_18_15,
+                GP_3_18_FN, FN_IP10_14_11,
+                GP_3_17_FN, FN_IP10_10_7,
+                GP_3_16_FN, FN_IP10_6_4,
+                GP_3_15_FN, FN_IP10_3_0,
+                GP_3_14_FN, FN_IP9_31_28,
+                GP_3_13_FN, FN_IP9_27_26,
+                GP_3_12_FN, FN_IP9_25_24,
+                GP_3_11_FN, FN_IP9_23_22,
+                GP_3_10_FN, FN_IP9_21_20,
+                GP_3_9_FN, FN_IP9_19_18,
+                GP_3_8_FN, FN_IP9_17_16,
+                GP_3_7_FN, FN_IP9_15_12,
+                GP_3_6_FN, FN_IP9_11_8,
+                GP_3_5_FN, FN_IP9_7_6,
+                GP_3_4_FN, FN_IP9_5_4,
+                GP_3_3_FN, FN_IP9_3_2,
+                GP_3_2_FN, FN_IP9_1_0,
+                GP_3_1_FN, FN_IP8_30_29,
+                GP_3_0_FN, FN_IP8_28 }
+        },
+        { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+                GP_4_31_FN, FN_IP14_18_16,
+                GP_4_30_FN, FN_IP14_15_12,
+                GP_4_29_FN, FN_IP14_11_9,
+                GP_4_28_FN, FN_IP14_8_6,
+                GP_4_27_FN, FN_IP14_5_3,
+                GP_4_26_FN, FN_IP14_2_0,
+                GP_4_25_FN, FN_IP13_30_29,
+                GP_4_24_FN, FN_IP13_28_26,
+                GP_4_23_FN, FN_IP13_25_23,
+                GP_4_22_FN, FN_IP13_22_19,
+                GP_4_21_FN, FN_IP13_18_16,
+                GP_4_20_FN, FN_IP13_15_13,
+                GP_4_19_FN, FN_IP13_12_10,
+                GP_4_18_FN, FN_IP13_9_7,
+                GP_4_17_FN, FN_IP13_6_3,
+                GP_4_16_FN, FN_IP13_2_0,
+                GP_4_15_FN, FN_IP12_30_28,
+                GP_4_14_FN, FN_IP12_27_25,
+                GP_4_13_FN, FN_IP12_24_23,
+                GP_4_12_FN, FN_IP12_22_20,
+                GP_4_11_FN, FN_IP12_19_17,
+                GP_4_10_FN, FN_IP12_16_14,
+                GP_4_9_FN, FN_IP12_13_11,
+                GP_4_8_FN, FN_IP12_10_8,
+                GP_4_7_FN, FN_IP12_7_6,
+                GP_4_6_FN, FN_IP12_5_4,
+                GP_4_5_FN, FN_IP12_3_2,
+                GP_4_4_FN, FN_IP12_1_0,
+                GP_4_3_FN, FN_IP11_31_30,
+                GP_4_2_FN, FN_IP11_29_27,
+                GP_4_1_FN, FN_IP11_26_24,
+                GP_4_0_FN, FN_IP11_23_22 }
+        },
+        { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+                GP_5_31_FN, FN_IP7_24_22,
+                GP_5_30_FN, FN_IP7_21_19,
+                GP_5_29_FN, FN_IP7_18_16,
+                GP_5_28_FN, FN_DU_DOTCLKIN2,
+                GP_5_27_FN, FN_IP7_26_25,
+                GP_5_26_FN, FN_DU_DOTCLKIN0,
+                GP_5_25_FN, FN_AVS2,
+                GP_5_24_FN, FN_AVS1,
+                GP_5_23_FN, FN_USB2_OVC,
+                GP_5_22_FN, FN_USB2_PWEN,
+                GP_5_21_FN, FN_IP16_7,
+                GP_5_20_FN, FN_IP16_6,
+                GP_5_19_FN, FN_USB0_OVC_VBUS,
+                GP_5_18_FN, FN_USB0_PWEN,
+                GP_5_17_FN, FN_IP16_5_3,
+                GP_5_16_FN, FN_IP16_2_0,
+                GP_5_15_FN, FN_IP15_29_28,
+                GP_5_14_FN, FN_IP15_27_26,
+                GP_5_13_FN, FN_IP15_25_23,
+                GP_5_12_FN, FN_IP15_22_20,
+                GP_5_11_FN, FN_IP15_19_18,
+                GP_5_10_FN, FN_IP15_17_16,
+                GP_5_9_FN, FN_IP15_15_14,
+                GP_5_8_FN, FN_IP15_13_12,
+                GP_5_7_FN, FN_IP15_11_9,
+                GP_5_6_FN, FN_IP15_8_6,
+                GP_5_5_FN, FN_IP15_5_3,
+                GP_5_4_FN, FN_IP15_2_0,
+                GP_5_3_FN, FN_IP14_30_28,
+                GP_5_2_FN, FN_IP14_27_25,
+                GP_5_1_FN, FN_IP14_24_22,
+                GP_5_0_FN, FN_IP14_21_19 }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
+                             1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
+                /* IP0_31 [1] */
+                0, 0,
+                /* IP0_30_27 [4] */
+                FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0,
+                FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_26_23 [4] */
+                FN_D7, FN_AD_DI_B, FN_SDA2_C,
+                FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_22_20 [3] */
+                FN_D6, FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
+                FN_SCL2_CIS_C, 0, 0,
+                /* IP0_19_16 [4] */
+                FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
+                FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_15_12 [4] */
+                FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
+                FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_11_9 [3] */
+                FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
+                0, 0, 0,
+                /* IP0_8_6 [3] */
+                FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
+                0, 0, 0,
+                /* IP0_5_3 [3] */
+                FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
+                0, 0, 0,
+                /* IP0_2_0 [3] */
+                FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
+                0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
+                             2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
+                /* IP1_31_30 [2] */
+                0, 0, 0, 0,
+                /* IP1_29_28 [2] */
+                FN_A1, FN_PWM4, 0, 0,
+                /* IP1_27_26 [2] */
+                FN_A0, FN_PWM3, 0, 0,
+                /* IP1_25_22 [4] */
+                FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
+                FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_21_18 [4] */
+                FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
+                FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_17_15 [3] */
+                FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
+                FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
+                0, 0, 0,
+                /* IP1_14_12 [3] */
+                FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
+                FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
+                0, 0,
+                /* IP1_11_8 [4] */
+                FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3,
+                FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_7_4 [4] */
+                FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2,
+                FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_3_0 [4] */
+                FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1,
+                FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
+                             3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
+                /* IP2_31_29 [3] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP2_28_26 [3] */
+                FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
+                FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
+                /* IP2_25_22 [4] */
+                FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
+                FN_VI0_R5_B, FN_SCIFB2_TXD_C, 0, FN_VI2_DATA1_VI2_B1_B,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP2_21_18 [4] */
+                FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
+                FN_VI0_R4_B, FN_SCIFB2_RXD_C, 0, FN_VI2_DATA0_VI2_B0_B,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP2_17_15 [3] */
+                FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
+                0, 0, 0, 0,
+                /* IP2_14_12 [3] */
+                FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
+                /* IP2_11_9 [3] */
+                FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
+                /* IP2_8_6 [3] */
+                FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
+                /* IP2_5_3 [3] */
+                FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
+                /* IP2_2_0 [3] */
+                FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
+                             3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
+                /* IP3_31_29 [3] */
+                FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
+                0, 0, 0,
+                /* IP3_28_26 [3] */
+                FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
+                0, 0, 0, 0,
+                /* IP3_25_23 [3] */
+                FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
+                /* IP3_22_20 [3] */
+                FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
+                /* IP3_19_18 [2] */
+                FN_A16, FN_ATAWR1_N, 0, 0,
+                /* IP3_17_15 [3] */
+                FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
+                0, 0, 0, 0,
+                /* IP3_14_12 [3] */
+                FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
+                0, 0, 0, 0,
+                /* IP3_11_8 [4] */
+                FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
+                FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
+                FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP3_7_4 [4] */
+                FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
+                FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP3_3_0 [4] */
+                FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
+                FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
+                             2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+                /* IP4_31_30 [2] */
+                0, 0, 0, 0,
+                /* IP4_29_27 [3] */
+                FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
+                FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
+                /* IP4_26_24 [3] */
+                FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
+                FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
+                /* IP4_23_21 [3] */
+                FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
+                FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
+                /* IP4_20_18 [3] */
+                FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
+                FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
+                /* IP4_17_15 [3] */
+                FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
+                0, 0, 0,
+                /* IP4_14_12 [3] */
+                FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
+                FN_VI2_FIELD_B, 0, 0,
+                /* IP4_11_9 [3] */
+                FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
+                FN_VI2_CLKENB_B, 0, 0,
+                /* IP4_8_6 [3] */
+                FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
+                /* IP4_5_3 [3] */
+                FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
+                /* IP4_2_0 [3] */
+                FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
+                             2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
+                /* IP5_31_30 [2] */
+                0, 0, 0, 0,
+                /* IP5_29_27 [3] */
+                FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
+                FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
+                /* IP5_26_24 [3] */
+                FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
+                FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
+                FN_MSIOF0_SCK_B, 0,
+                /* IP5_23_21 [3] */
+                FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
+                FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
+                FN_IERX_C, 0,
+                /* IP5_20_18 [3] */
+                FN_WE0_N, FN_IECLK, FN_CAN_CLK,
+                FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
+                /* IP5_17_15 [3] */
+                FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
+                FN_INTC_IRQ4_N, 0, 0,
+                /* IP5_14_13 [2] */
+                FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
+                /* IP5_12_10 [3] */
+                FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
+                0, 0,
+                /* IP5_9_6 [4] */
+                FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
+                FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N,
+                FN_SDA1_CIS, 0, 0, 0, 0, 0, 0,
+                /* IP5_5_3 [3] */
+                FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
+                FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B,
+                FN_INTC_EN0_N, FN_SCL1_CIS,
+                /* IP5_2_0 [3] */
+                FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
+                FN_VI2_R3, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
+                             3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
+                /* IP6_31_29 [3] */
+                FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
+                FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
+                /* IP6_28_26 [3] */
+                FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
+                FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
+                /* IP6_25_23 [3] */
+                FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
+                FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
+                /* IP6_22_20 [3] */
+                FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
+                FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
+                /* IP6_19_17 [3] */
+                FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B,
+                FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0,
+                /* IP6_16_14 [3] */
+                FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
+                FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
+                FN_SCL2_CIS_E, 0,
+                /* IP6_13_11 [3] */
+                FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
+                FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
+                /* IP6_10_9 [2] */
+                FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
+                /* IP6_8_6 [3] */
+                FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
+                FN_SSI_SDATA8_C, 0, 0, 0,
+                /* IP6_5_3 [3] */
+                FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
+                FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
+                /* IP6_2_0 [3] */
+                FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
+                FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
+                             1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
+                /* IP7_31 [1] */
+                0, 0,
+                /* IP7_30_29 [2] */
+                FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
+                FN_MII_RXD2,
+                /* IP7_28_27 [2] */
+                FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
+                /* IP7_26_25 [2] */
+                FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
+                /* IP7_24_22 [3] */
+                FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
+                0, 0, 0,
+                /* IP7_21_19 [3] */
+                FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
+                FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
+                /* IP7_18_16 [3] */
+                FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
+                FN_GLO_SS_C, 0, 0, 0,
+                /* IP7_15_13 [3] */
+                FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
+                FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
+                /* IP7_12_10 [3] */
+                FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
+                FN_GLO_SCLK_C, 0, 0, 0,
+                /* IP7_9_8 [2] */
+                FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0,
+                /* IP7_7_6 [2] */
+                FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F,
+                /* IP7_5_3 [3] */
+                FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
+                0, 0, 0,
+                /* IP7_2_0 [3] */
+                FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
+                FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
+                             1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
+                             2, 2, 2, 2, 2, 2, 2) {
+                /* IP8_31 [1] */
+                0, 0,
+                /* IP8_30_29 [2] */
+                FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
+                /* IP8_28 [1] */
+                FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
+                /* IP8_27 [1] */
+                FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
+                /* IP8_26 [1] */
+                FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
+                /* IP8_25_24 [2] */
+                FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
+                FN_AVB_MAGIC, FN_MII_MAGIC,
+                /* IP8_23_22 [2] */
+                FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
+                /* IP8_21_20 [2] */
+                FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
+                FN_MII_MDIO,
+                /* IP8_19_18 [2] */
+                FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,
+                /* IP8_17_16 [2] */
+                FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, FN_MII_CRS,
+                /* IP8_15_14 [2] */
+                FN_VI1_CLK, FN_AVB_RX_DV, FN_MII_RX_DV, 0,
+                /* IP8_13_12 [2] */
+                FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, FN_MII_RX_CLK, 0,
+                /* IP8_11_10 [2] */
+                FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, FN_MII_RX_ER, 0,
+                /* IP8_9_8 [2] */
+                FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
+                /* IP8_7_6 [2] */
+                FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
+                /* IP8_5_4 [2] */
+                FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
+                /* IP8_3_2 [2] */
+                FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
+                /* IP8_1_0 [2] */
+                FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, FN_MII_RXD3, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
+                             4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
+                /* IP9_31_28 [4] */
+                FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
+                FN_GLO_SS, FN_VI0_CLK_B, FN_SCL2_D, FN_SCL2_CIS_D,
+                FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
+                /* IP9_27_26 [2] */
+                FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B,
+                /* IP9_25_24 [2] */
+                FN_SD1_DAT2, FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,
+                /* IP9_23_22 [2] */
+                FN_SD1_DAT1, FN_AVB_LINK, FN_MII_LINK, FN_SCIFB0_TXD_B,
+                /* IP9_21_20 [2] */
+                FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, FN_SCIFB0_RXD_B,
+                /* IP9_19_18 [2] */
+                FN_SD1_CMD, FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,
+                /* IP9_17_16 [2] */
+                FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0,
+                /* IP9_15_12 [4] */
+                FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
+                FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B,
+                FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
+                /* IP9_11_8 [4] */
+                FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
+                FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B,
+                FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
+                /* IP9_7_6 [2] */
+                FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
+                /* IP9_5_4 [2] */
+                FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
+                /* IP9_3_2 [2] */
+                FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
+                /* IP9_1_0 [2] */
+                FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
+                             2, 4, 3, 4, 4, 4, 4, 3, 4) {
+                /* IP10_31_30 [2] */
+                0, 0, 0, 0,
+                /* IP10_29_26 [4] */
+                FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
+                FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
+                FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
+                /* IP10_25_23 [3] */
+                FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
+                FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
+                /* IP10_22_19 [4] */
+                FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
+                FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
+                FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
+                /* IP10_18_15 [4] */
+                FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
+                FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
+                FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
+                0, 0, 0, 0, 0, 0,
+                /* IP10_14_11 [4] */
+                FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
+                FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
+                FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
+                0, 0, 0, 0, 0, 0, 0,
+                /* IP10_10_7 [4] */
+                FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
+                FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
+                FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
+                0, 0, 0, 0, 0, 0, 0,
+                /* IP10_6_4 [3] */
+                FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
+                FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
+                FN_VI3_DATA0_B, 0,
+                /* IP10_3_0 [4] */
+                FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
+                FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D,
+                FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
+                             2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
+                /* IP11_31_30 [2] */
+                FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
+                /* IP11_29_27 [3] */
+                FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
+                FN_RDS_CLK_B, 0, 0,
+                /* IP11_26_24 [3] */
+                FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, FN_SDA2_CIS_B,
+                0, 0, 0,
+                /* IP11_23_22 [2] */
+                FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, 0,
+                /* IP11_21_18 [4] */
+                FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
+                FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
+                FN_RDS_DATA_E, 0, 0, 0, 0, 0, 0,
+                /* IP11_17_15 [3] */
+                FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
+                FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
+                /* IP11_14_13 [2] */
+                FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
+                /* IP11_12_11 [2] */
+                FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
+                /* IP11_10_9 [2] */
+                FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
+                /* IP11_8_7 [2] */
+                FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
+                /* IP11_6_5 [2] */
+                FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
+                /* IP11_4 [1] */
+                FN_SD3_CLK, FN_MMC1_CLK,
+                /* IP11_3_0 [4] */
+                FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
+                FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
+                FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
+                             1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
+                /* IP12_31 [1] */
+                0, 0,
+                /* IP12_30_28 [3] */
+                FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
+                FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
+                FN_CAN_DEBUGOUT4, 0, 0,
+                /* IP12_27_25 [3] */
+                FN_SSI_SCK5, FN_SCIFB1_SCK,
+                FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
+                FN_CAN_DEBUGOUT3, 0, 0,
+                /* IP12_24_23 [2] */
+                FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
+                FN_CAN_DEBUGOUT2,
+                /* IP12_22_20 [3] */
+                FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
+                FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
+                /* IP12_19_17 [3] */
+                FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
+                FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
+                /* IP12_16_14 [3] */
+                FN_SSI_SDATA3, FN_STP_ISCLK_0,
+                FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
+                /* IP12_13_11 [3] */
+                FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
+                FN_CAN_STEP0, 0, 0, 0,
+                /* IP12_10_8 [3] */
+                FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
+                FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
+                /* IP12_7_6 [2] */
+                FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
+                /* IP12_5_4 [2] */
+                FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
+                /* IP12_3_2 [2] */
+                FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
+                /* IP12_1_0 [2] */
+                FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
+                             1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
+                /* IP13_31 [1] */
+                0, 0,
+                /* IP13_30_29 [2] */
+                FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
+                /* IP13_28_26 [3] */
+                FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
+                FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
+                /* IP13_25_23 [3] */
+                FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
+                FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
+                /* IP13_22_19 [4] */
+                FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
+                FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
+                FN_RDS_CLK_D, FN_SSI_SDATA7_B, FN_FMIN_G, FN_RDS_DATA_F,
+                0, 0, 0, 0,
+                /* IP13_18_16 [3] */
+                FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
+                FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
+                /* IP13_15_13 [3] */
+                FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
+                FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
+                /* IP13_12_10 [3] */
+                FN_SSI_SDATA6, FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5,
+                FN_CAN_DEBUGOUT8, 0, 0,
+                /* IP13_9_7 [3] */
+                FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
+                FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
+                /* IP13_6_3 [4] */
+                FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C,
+                FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
+                FN_BPFCLK_F, FN_RDS_CLK_E, 0, 0, 0, 0, 0, 0, 0,
+                /* IP13_2_0 [3] */
+                FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
+                FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
+                             1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
+                /* IP14_30 [1] */
+                0, 0,
+                /* IP14_30_28 [3] */
+                FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS,
+                FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
+                FN_HRTS0_N_C, 0,
+                /* IP14_27_25 [3] */
+                FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
+                FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
+                /* IP14_24_22 [3] */
+                FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
+                FN_LCDOUT9, 0, 0, 0,
+                /* IP14_21_19 [3] */
+                FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
+                FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
+                /* IP14_18_16 [3] */
+                FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS,
+                FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
+                /* IP14_15_12 [4] */
+                FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
+                FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C,
+                0, 0, 0, 0, 0, 0, 0,
+                /* IP14_11_9 [3] */
+                FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
+                0, 0, 0,
+                /* IP14_8_6 [3] */
+                FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
+                0, 0, 0,
+                /* IP14_5_3 [3] */
+                FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
+                FN_LCDOUT10, FN_SDA1_C, FN_SDA1_CIS_C,
+                /* IP14_2_0 [3] */
+                FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
+                FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
+                FN_REMOCON, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
+                             2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
+                /* IP15_31_30 [2] */
+                0, 0, 0, 0,
+                /* IP15_29_28 [2] */
+                FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
+                /* IP15_27_26 [2] */
+                FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
+                /* IP15_25_23 [3] */
+                FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
+                FN_DU2_DB7, FN_LCDOUT23, FN_SCIFA2_RXD_B, 0,
+                /* IP15_22_20 [3] */
+                FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
+                FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
+                /* IP15_19_18 [2] */
+                FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
+                /* IP15_17_16 [2] */
+                FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
+                /* IP15_15_14 [2] */
+                FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
+                /* IP15_13_12 [2] */
+                FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
+                /* IP15_11_9 [3] */
+                FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
+                0, 0, 0,
+                /* IP15_8_6 [3] */
+                FN_SCIFA2_TXD, FN_BPFCLK, 0, FN_DU2_DB1, FN_LCDOUT17,
+                FN_SDA2, FN_SDA2_CIS, 0,
+                /* IP15_5_3 [3] */
+                FN_SCIFA2_RXD, FN_FMIN, 0, FN_DU2_DB0, FN_LCDOUT16,
+                FN_SCL2, FN_SCL2_CIS, 0,
+                /* IP15_2_0 [3] */
+                FN_SCIFA2_SCK, FN_FMCLK, 0, FN_MSIOF3_SCK, FN_DU2_DG7,
+                FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
+                             4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
+                /* IP16_31_28 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_27_24 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_23_20 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_19_16 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_15_12 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_11_8 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_7 [1] */
+                FN_USB1_OVC, FN_TCLK1_B,
+                /* IP16_6 [1] */
+                FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
+                /* IP16_5_3 [3] */
+                FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
+                FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C, 0,
+                /* IP16_2_0 [3] */
+                FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
+                FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
+                             3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
+                             2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
+                /* SEL_SCIF1 [3] */
+                FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+                FN_SEL_SCIF1_4, 0, 0, 0,
+                /* SEL_SCIFB [2] */
+                FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
+                /* SEL_SCIFB2 [2] */
+                FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
+                /* SEL_SCIFB1 [3] */
+                FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
+                FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
+                FN_SEL_SCIFB1_6, 0,
+                /* SEL_SCIFA1 [2] */
+                FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
+                FN_SEL_SCIFA1_3,
+                /* SEL_SCIF0 [1] */
+                FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
+                /* SEL_SCIFA [1] */
+                FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+                /* SEL_SOF1 [1] */
+                FN_SEL_SOF1_0, FN_SEL_SOF1_1,
+                /* SEL_SSI7 [2] */
+                FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
+                /* SEL_SSI6 [1] */
+                FN_SEL_SSI6_0, FN_SEL_SSI6_1,
+                /* SEL_SSI5 [2] */
+                FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
+                /* SEL_VI3 [1] */
+                FN_SEL_VI3_0, FN_SEL_VI3_1,
+                /* SEL_VI2 [1] */
+                FN_SEL_VI2_0, FN_SEL_VI2_1,
+                /* SEL_VI1 [1] */
+                FN_SEL_VI1_0, FN_SEL_VI1_1,
+                /* SEL_VI0 [1] */
+                FN_SEL_VI0_0, FN_SEL_VI0_1,
+                /* SEL_TSIF1 [2] */
+                FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
+                /* RESERVED [1] */
+                0, 0,
+                /* SEL_LBS [1] */
+                FN_SEL_LBS_0, FN_SEL_LBS_1,
+                /* SEL_TSIF0 [2] */
+                FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+                /* SEL_SOF3 [1] */
+                FN_SEL_SOF3_0, FN_SEL_SOF3_1,
+                /* SEL_SOF0 [1] */
+                FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
+                             3, 1, 1, 1, 2, 1, 2, 1, 2,
+                             1, 1, 1, 3, 3, 2, 3, 2, 2) {
+                /* RESERVED [3] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* SEL_TMU1 [1] */
+                FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+                /* SEL_HSCIF1 [1] */
+                FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+                /* SEL_SCIFCLK [1] */
+                FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
+                /* SEL_CAN0 [2] */
+                FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+                /* SEL_CANCLK [1] */
+                FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
+                /* SEL_SCIFA2 [2] */
+                FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
+                /* SEL_CAN1 [1] */
+                FN_SEL_CAN1_0, FN_SEL_CAN1_1,
+                /* RESERVED [2] */
+                0, 0, 0, 0,
+                /* RESERVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */
+                0, 0,
+                /* SEL_ADI [1] */
+                FN_SEL_ADI_0, FN_SEL_ADI_1,
+                /* SEL_SSP [1] */
+                FN_SEL_SSP_0, FN_SEL_SSP_1,
+                /* SEL_FM [3] */
+                FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
+                FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
+                /* SEL_HSCIF0 [3] */
+                FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
+                FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
+                /* SEL_GPS [2] */
+                FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
+                /* SEL_RDS [3] */
+                FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
+                FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, 0, 0,
+                /* SEL_SIM [2] */
+                FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
+                /* SEL_SSI8 [2] */
+                FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
+                             1, 1, 2, 4, 4, 2, 2,
+                             4, 2, 3, 2, 3, 2) {
+                /* SEL_IICDVFS [1] */
+                FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
+                /* SEL_IIC0 [1] */
+                FN_SEL_IIC0_0, FN_SEL_IIC0_1,
+                /* RESERVED [2] */
+                0, 0, 0, 0,
+                /* RESERVED [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* RESERVED [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* RESERVED [2] */
+                0, 0, 0, 0,
+                /* SEL_IEB [2] */
+                FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
+                /* RESERVED [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* RESERVED [2] */
+                0, 0, 0, 0,
+                /* SEL_IIC2 [3] */
+                FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+                FN_SEL_IIC2_4, 0, 0, 0,
+                /* SEL_IIC1 [2] */
+                FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
+                /* SEL_I2C2 [3] */
+                FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
+                FN_SEL_I2C2_4, 0, 0, 0,
+                /* SEL_I2C1 [2] */
+                FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
+        },
+        { },
+};
+
+const struct sh_pfc_soc_info r8a7790_pinmux_info = {
+        .name = "r8a77900_pfc",
+        .unlock_reg = 0xe6060000, /* PMMR */
+
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+        .groups = pinmux_groups,
+        .nr_groups = ARRAY_SIZE(pinmux_groups),
+        .functions = pinmux_functions,
+        .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+        .cfg_regs = pinmux_config_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index df0ae21a5ac8..6dfb18772574 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -20,10 +20,14 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
+#include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/pinctrl/pinconf-generic.h>
+
 #include <mach/irqs.h>
 #include <mach/sh7372.h>
 
+#include "core.h"
 #include "sh_pfc.h"
 
 #define CPU_ALL_PORT(fn, pfx, sfx) \
@@ -34,6 +38,35 @@
         PORT_10(fn, pfx##16, sfx),      PORT_10(fn, pfx##17, sfx), \
         PORT_10(fn, pfx##18, sfx),      PORT_1(fn, pfx##190, sfx)
 
+#undef _GPIO_PORT
+#define _GPIO_PORT(gpio, sfx)                                           \
+        [gpio] = {                                                      \
+                .name = __stringify(PORT##gpio),                        \
+                .enum_id = PORT##gpio##_DATA,                           \
+        }
+
+#define IRQC_PIN_MUX(irq, pin)                                          \
+static const unsigned int intc_irq##irq##_pins[] = {                    \
+        pin,                                                            \
+};                                                                      \
+static const unsigned int intc_irq##irq##_mux[] = {                     \
+        IRQ##irq##_MARK,                                                \
+}
+
+#define IRQC_PINS_MUX(irq, pin0, pin1)                                  \
+static const unsigned int intc_irq##irq##_0_pins[] = {                  \
+        pin0,                                                           \
+};                                                                      \
+static const unsigned int intc_irq##irq##_0_mux[] = {                   \
+        IRQ##irq##_##pin0##_MARK,                                       \
+};                                                                      \
+static const unsigned int intc_irq##irq##_1_pins[] = {                  \
+        pin1,                                                           \
+};                                                                      \
+static const unsigned int intc_irq##irq##_1_mux[] = {                   \
+        IRQ##irq##_##pin1##_MARK,                                       \
+}
+
 enum {
         PINMUX_RESERVED = 0,
 
@@ -47,16 +80,6 @@ enum {
         PORT_ALL(IN),
         PINMUX_INPUT_END,
 
-        /* PORT0_IN_PU -> PORT190_IN_PU */
-        PINMUX_INPUT_PULLUP_BEGIN,
-        PORT_ALL(IN_PU),
-        PINMUX_INPUT_PULLUP_END,
-
-        /* PORT0_IN_PD -> PORT190_IN_PD */
-        PINMUX_INPUT_PULLDOWN_BEGIN,
-        PORT_ALL(IN_PD),
-        PINMUX_INPUT_PULLDOWN_END,
-
         /* PORT0_OUT -> PORT190_OUT */
         PINMUX_OUTPUT_BEGIN,
         PORT_ALL(OUT),
@@ -368,124 +391,11 @@ enum {
         PINMUX_MARK_END,
 };
 
-static const pinmux_enum_t pinmux_data[] = {
+#define _PORT_DATA(pfx, sfx)    PORT_DATA_IO(pfx)
+#define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_PORT_DATA, , unused)
 
-        /* specify valid pin states for each pin in GPIO mode */
-        PORT_DATA_IO_PD(0),             PORT_DATA_IO_PD(1),
-        PORT_DATA_O(2),                 PORT_DATA_I_PD(3),
-        PORT_DATA_I_PD(4),              PORT_DATA_I_PD(5),
-        PORT_DATA_IO_PU_PD(6),          PORT_DATA_I_PD(7),
-        PORT_DATA_IO_PD(8),             PORT_DATA_O(9),
-
-        PORT_DATA_O(10),                PORT_DATA_O(11),
-        PORT_DATA_IO_PU_PD(12),         PORT_DATA_IO_PD(13),
-        PORT_DATA_IO_PD(14),            PORT_DATA_O(15),
-        PORT_DATA_IO_PD(16),            PORT_DATA_IO_PD(17),
-        PORT_DATA_I_PD(18),             PORT_DATA_IO(19),
-
-        PORT_DATA_IO(20),               PORT_DATA_IO(21),
-        PORT_DATA_IO(22),               PORT_DATA_IO(23),
-        PORT_DATA_IO(24),               PORT_DATA_IO(25),
-        PORT_DATA_IO(26),               PORT_DATA_IO(27),
-        PORT_DATA_IO(28),               PORT_DATA_IO(29),
-
-        PORT_DATA_IO(30),               PORT_DATA_IO(31),
-        PORT_DATA_IO(32),               PORT_DATA_IO(33),
-        PORT_DATA_IO(34),               PORT_DATA_IO(35),
-        PORT_DATA_IO(36),               PORT_DATA_IO(37),
-        PORT_DATA_IO(38),               PORT_DATA_IO(39),
-
-        PORT_DATA_IO(40),               PORT_DATA_IO(41),
-        PORT_DATA_IO(42),               PORT_DATA_IO(43),
-        PORT_DATA_IO(44),               PORT_DATA_IO(45),
-        PORT_DATA_IO_PU(46),            PORT_DATA_IO_PU(47),
-        PORT_DATA_IO_PU(48),            PORT_DATA_IO_PU(49),
-
-        PORT_DATA_IO_PU(50),            PORT_DATA_IO_PU(51),
-        PORT_DATA_IO_PU(52),            PORT_DATA_IO_PU(53),
-        PORT_DATA_IO_PU(54),            PORT_DATA_IO_PU(55),
-        PORT_DATA_IO_PU(56),            PORT_DATA_IO_PU(57),
-        PORT_DATA_IO_PU(58),            PORT_DATA_IO_PU(59),
-
-        PORT_DATA_IO_PU(60),            PORT_DATA_IO_PU(61),
-        PORT_DATA_IO(62),               PORT_DATA_O(63),
-        PORT_DATA_O(64),                PORT_DATA_IO_PU(65),
-        PORT_DATA_O(66),                PORT_DATA_IO_PU(67),  /*66?*/
-        PORT_DATA_O(68),                PORT_DATA_IO(69),
-
-        PORT_DATA_IO(70),               PORT_DATA_IO(71),
-        PORT_DATA_O(72),                PORT_DATA_I_PU(73),
-        PORT_DATA_I_PU_PD(74),          PORT_DATA_IO_PU_PD(75),
-        PORT_DATA_IO_PU_PD(76),         PORT_DATA_IO_PU_PD(77),
-        PORT_DATA_IO_PU_PD(78),         PORT_DATA_IO_PU_PD(79),
-
-        PORT_DATA_IO_PU_PD(80),         PORT_DATA_IO_PU_PD(81),
-        PORT_DATA_IO_PU_PD(82),         PORT_DATA_IO_PU_PD(83),
-        PORT_DATA_IO_PU_PD(84),         PORT_DATA_IO_PU_PD(85),
-        PORT_DATA_IO_PU_PD(86),         PORT_DATA_IO_PU_PD(87),
-        PORT_DATA_IO_PU_PD(88),         PORT_DATA_IO_PU_PD(89),
-
-        PORT_DATA_IO_PU_PD(90),         PORT_DATA_IO_PU_PD(91),
-        PORT_DATA_IO_PU_PD(92),         PORT_DATA_IO_PU_PD(93),
-        PORT_DATA_IO_PU_PD(94),         PORT_DATA_IO_PU_PD(95),
-        PORT_DATA_IO_PU(96),            PORT_DATA_IO_PU_PD(97),
-        PORT_DATA_IO_PU_PD(98),         PORT_DATA_O(99), /*99?*/
-
-        PORT_DATA_IO_PD(100),           PORT_DATA_IO_PD(101),
-        PORT_DATA_IO_PD(102),           PORT_DATA_IO_PD(103),
-        PORT_DATA_IO_PD(104),           PORT_DATA_IO_PD(105),
-        PORT_DATA_IO_PU(106),           PORT_DATA_IO_PU(107),
-        PORT_DATA_IO_PU(108),           PORT_DATA_IO_PU(109),
-
-        PORT_DATA_IO_PU(110),           PORT_DATA_IO_PU(111),
-        PORT_DATA_IO_PD(112),           PORT_DATA_IO_PD(113),
-        PORT_DATA_IO_PU(114),           PORT_DATA_IO_PU(115),
-        PORT_DATA_IO_PU(116),           PORT_DATA_IO_PU(117),
-        PORT_DATA_IO_PU(118),           PORT_DATA_IO_PU(119),
-
-        PORT_DATA_IO_PU(120),           PORT_DATA_IO_PD(121),
-        PORT_DATA_IO_PD(122),           PORT_DATA_IO_PD(123),
-        PORT_DATA_IO_PD(124),           PORT_DATA_IO_PD(125),
-        PORT_DATA_IO_PD(126),           PORT_DATA_IO_PD(127),
-        PORT_DATA_IO_PD(128),           PORT_DATA_IO_PU_PD(129),
-
-        PORT_DATA_IO_PU_PD(130),        PORT_DATA_IO_PU_PD(131),
-        PORT_DATA_IO_PU_PD(132),        PORT_DATA_IO_PU_PD(133),
-        PORT_DATA_IO_PU_PD(134),        PORT_DATA_IO_PU_PD(135),
-        PORT_DATA_IO_PD(136),           PORT_DATA_IO_PD(137),
-        PORT_DATA_IO_PD(138),           PORT_DATA_IO_PD(139),
-
-        PORT_DATA_IO_PD(140),           PORT_DATA_IO_PD(141),
-        PORT_DATA_IO_PD(142),           PORT_DATA_IO_PU_PD(143),
-        PORT_DATA_IO_PD(144),           PORT_DATA_IO_PD(145),
-        PORT_DATA_IO_PD(146),           PORT_DATA_IO_PD(147),
-        PORT_DATA_IO_PD(148),           PORT_DATA_IO_PD(149),
-
-        PORT_DATA_IO_PD(150),           PORT_DATA_IO_PD(151),
-        PORT_DATA_IO_PU_PD(152),        PORT_DATA_I_PD(153),
-        PORT_DATA_IO_PU_PD(154),        PORT_DATA_I_PD(155),
-        PORT_DATA_IO_PD(156),           PORT_DATA_IO_PD(157),
-        PORT_DATA_I_PD(158),            PORT_DATA_IO_PD(159),
-
-        PORT_DATA_O(160),               PORT_DATA_IO_PD(161),
-        PORT_DATA_IO_PD(162),           PORT_DATA_IO_PD(163),
-        PORT_DATA_I_PD(164),            PORT_DATA_IO_PD(165),
-        PORT_DATA_I_PD(166),            PORT_DATA_I_PD(167),
-        PORT_DATA_I_PD(168),            PORT_DATA_I_PD(169),
-
-        PORT_DATA_I_PD(170),            PORT_DATA_O(171),
-        PORT_DATA_IO_PU_PD(172),        PORT_DATA_IO_PU_PD(173),
-        PORT_DATA_IO_PU_PD(174),        PORT_DATA_IO_PU_PD(175),
-        PORT_DATA_IO_PU_PD(176),        PORT_DATA_IO_PU_PD(177),
-        PORT_DATA_IO_PU_PD(178),        PORT_DATA_O(179),
-
-        PORT_DATA_IO_PU_PD(180),        PORT_DATA_IO_PU_PD(181),
-        PORT_DATA_IO_PU_PD(182),        PORT_DATA_IO_PU_PD(183),
-        PORT_DATA_IO_PU_PD(184),        PORT_DATA_O(185),
-        PORT_DATA_IO_PU_PD(186),        PORT_DATA_IO_PU_PD(187),
-        PORT_DATA_IO_PU_PD(188),        PORT_DATA_IO_PU_PD(189),
-
-        PORT_DATA_IO_PU_PD(190),
+static const pinmux_enum_t pinmux_data[] = {
+        PINMUX_DATA_GP_ALL(),
 
         /* IRQ */
         PINMUX_DATA(IRQ0_6_MARK,        PORT6_FN0,      MSEL1CR_0_0),
@@ -929,10 +839,582 @@ static const pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(MFIv4_MARK,         MSEL4CR_6_1),
 };
 
+#define SH7372_PIN(pin, cfgs)                                           \
+        {                                                               \
+                .name = __stringify(PORT##pin),                         \
+                .enum_id = PORT##pin##_DATA,                            \
+                .configs = cfgs,                                        \
+        }
+
+#define __I             (SH_PFC_PIN_CFG_INPUT)
+#define __O             (SH_PFC_PIN_CFG_OUTPUT)
+#define __IO            (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
+#define __PD            (SH_PFC_PIN_CFG_PULL_DOWN)
+#define __PU            (SH_PFC_PIN_CFG_PULL_UP)
+#define __PUD           (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
+
+#define SH7372_PIN_I_PD(pin)            SH7372_PIN(pin, __I | __PD)
+#define SH7372_PIN_I_PU(pin)            SH7372_PIN(pin, __I | __PU)
+#define SH7372_PIN_I_PU_PD(pin)         SH7372_PIN(pin, __I | __PUD)
+#define SH7372_PIN_IO(pin)              SH7372_PIN(pin, __IO)
+#define SH7372_PIN_IO_PD(pin)           SH7372_PIN(pin, __IO | __PD)
+#define SH7372_PIN_IO_PU(pin)           SH7372_PIN(pin, __IO | __PU)
+#define SH7372_PIN_IO_PU_PD(pin)        SH7372_PIN(pin, __IO | __PUD)
+#define SH7372_PIN_O(pin)               SH7372_PIN(pin, __O)
+#define SH7372_PIN_O_PU_PD(pin)         SH7372_PIN(pin, __O | __PUD)
+
 static struct sh_pfc_pin pinmux_pins[] = {
-        GPIO_PORT_ALL(),
+        /* Table 57-1 (I/O and Pull U/D) */
+        SH7372_PIN_IO_PD(0),            SH7372_PIN_IO_PD(1),
+        SH7372_PIN_O(2),                SH7372_PIN_I_PD(3),
+        SH7372_PIN_I_PD(4),             SH7372_PIN_I_PD(5),
+        SH7372_PIN_IO_PU_PD(6),         SH7372_PIN_I_PD(7),
+        SH7372_PIN_IO_PD(8),            SH7372_PIN_O(9),
+        SH7372_PIN_O(10),               SH7372_PIN_O(11),
+        SH7372_PIN_IO_PU_PD(12),        SH7372_PIN_IO_PD(13),
+        SH7372_PIN_IO_PD(14),           SH7372_PIN_O(15),
+        SH7372_PIN_IO_PD(16),           SH7372_PIN_IO_PD(17),
+        SH7372_PIN_I_PD(18),            SH7372_PIN_IO(19),
+        SH7372_PIN_IO(20),              SH7372_PIN_IO(21),
+        SH7372_PIN_IO(22),              SH7372_PIN_IO(23),
+        SH7372_PIN_IO(24),              SH7372_PIN_IO(25),
+        SH7372_PIN_IO(26),              SH7372_PIN_IO(27),
+        SH7372_PIN_IO(28),              SH7372_PIN_IO(29),
+        SH7372_PIN_IO(30),              SH7372_PIN_IO(31),
+        SH7372_PIN_IO(32),              SH7372_PIN_IO(33),
+        SH7372_PIN_IO(34),              SH7372_PIN_IO(35),
+        SH7372_PIN_IO(36),              SH7372_PIN_IO(37),
+        SH7372_PIN_IO(38),              SH7372_PIN_IO(39),
+        SH7372_PIN_IO(40),              SH7372_PIN_IO(41),
+        SH7372_PIN_IO(42),              SH7372_PIN_IO(43),
+        SH7372_PIN_IO(44),              SH7372_PIN_IO(45),
+        SH7372_PIN_IO_PU(46),           SH7372_PIN_IO_PU(47),
+        SH7372_PIN_IO_PU(48),           SH7372_PIN_IO_PU(49),
+        SH7372_PIN_IO_PU(50),           SH7372_PIN_IO_PU(51),
+        SH7372_PIN_IO_PU(52),           SH7372_PIN_IO_PU(53),
+        SH7372_PIN_IO_PU(54),           SH7372_PIN_IO_PU(55),
+        SH7372_PIN_IO_PU(56),           SH7372_PIN_IO_PU(57),
+        SH7372_PIN_IO_PU(58),           SH7372_PIN_IO_PU(59),
+        SH7372_PIN_IO_PU(60),           SH7372_PIN_IO_PU(61),
+        SH7372_PIN_IO(62),              SH7372_PIN_O(63),
+        SH7372_PIN_O(64),               SH7372_PIN_IO_PU(65),
+        SH7372_PIN_O_PU_PD(66),         SH7372_PIN_IO_PU(67),
+        SH7372_PIN_O(68),               SH7372_PIN_IO(69),
+        SH7372_PIN_IO(70),              SH7372_PIN_IO(71),
+        SH7372_PIN_O(72),               SH7372_PIN_I_PU(73),
+        SH7372_PIN_I_PU_PD(74),         SH7372_PIN_IO_PU_PD(75),
+        SH7372_PIN_IO_PU_PD(76),        SH7372_PIN_IO_PU_PD(77),
+        SH7372_PIN_IO_PU_PD(78),        SH7372_PIN_IO_PU_PD(79),
+        SH7372_PIN_IO_PU_PD(80),        SH7372_PIN_IO_PU_PD(81),
+        SH7372_PIN_IO_PU_PD(82),        SH7372_PIN_IO_PU_PD(83),
+        SH7372_PIN_IO_PU_PD(84),        SH7372_PIN_IO_PU_PD(85),
+        SH7372_PIN_IO_PU_PD(86),        SH7372_PIN_IO_PU_PD(87),
+        SH7372_PIN_IO_PU_PD(88),        SH7372_PIN_IO_PU_PD(89),
+        SH7372_PIN_IO_PU_PD(90),        SH7372_PIN_IO_PU_PD(91),
+        SH7372_PIN_IO_PU_PD(92),        SH7372_PIN_IO_PU_PD(93),
+        SH7372_PIN_IO_PU_PD(94),        SH7372_PIN_IO_PU_PD(95),
+        SH7372_PIN_IO_PU(96),           SH7372_PIN_IO_PU_PD(97),
+        SH7372_PIN_IO_PU_PD(98),        SH7372_PIN_O_PU_PD(99),
+        SH7372_PIN_IO_PD(100),          SH7372_PIN_IO_PD(101),
+        SH7372_PIN_IO_PD(102),          SH7372_PIN_IO_PD(103),
+        SH7372_PIN_IO_PD(104),          SH7372_PIN_IO_PD(105),
+        SH7372_PIN_IO_PU(106),          SH7372_PIN_IO_PU(107),
+        SH7372_PIN_IO_PU(108),          SH7372_PIN_IO_PU(109),
+        SH7372_PIN_IO_PU(110),          SH7372_PIN_IO_PU(111),
+        SH7372_PIN_IO_PD(112),          SH7372_PIN_IO_PD(113),
+        SH7372_PIN_IO_PU(114),          SH7372_PIN_IO_PU(115),
+        SH7372_PIN_IO_PU(116),          SH7372_PIN_IO_PU(117),
+        SH7372_PIN_IO_PU(118),          SH7372_PIN_IO_PU(119),
+        SH7372_PIN_IO_PU(120),          SH7372_PIN_IO_PD(121),
+        SH7372_PIN_IO_PD(122),          SH7372_PIN_IO_PD(123),
+        SH7372_PIN_IO_PD(124),          SH7372_PIN_IO_PD(125),
+        SH7372_PIN_IO_PD(126),          SH7372_PIN_IO_PD(127),
+        SH7372_PIN_IO_PD(128),          SH7372_PIN_IO_PU_PD(129),
+        SH7372_PIN_IO_PU_PD(130),       SH7372_PIN_IO_PU_PD(131),
+        SH7372_PIN_IO_PU_PD(132),       SH7372_PIN_IO_PU_PD(133),
+        SH7372_PIN_IO_PU_PD(134),       SH7372_PIN_IO_PU_PD(135),
+        SH7372_PIN_IO_PD(136),          SH7372_PIN_IO_PD(137),
+        SH7372_PIN_IO_PD(138),          SH7372_PIN_IO_PD(139),
+        SH7372_PIN_IO_PD(140),          SH7372_PIN_IO_PD(141),
+        SH7372_PIN_IO_PD(142),          SH7372_PIN_IO_PU_PD(143),
+        SH7372_PIN_IO_PD(144),          SH7372_PIN_IO_PD(145),
+        SH7372_PIN_IO_PD(146),          SH7372_PIN_IO_PD(147),
+        SH7372_PIN_IO_PD(148),          SH7372_PIN_IO_PD(149),
+        SH7372_PIN_IO_PD(150),          SH7372_PIN_IO_PD(151),
+        SH7372_PIN_IO_PU_PD(152),       SH7372_PIN_I_PD(153),
+        SH7372_PIN_IO_PU_PD(154),       SH7372_PIN_I_PD(155),
+        SH7372_PIN_IO_PD(156),          SH7372_PIN_IO_PD(157),
+        SH7372_PIN_I_PD(158),           SH7372_PIN_IO_PD(159),
+        SH7372_PIN_O(160),              SH7372_PIN_IO_PD(161),
+        SH7372_PIN_IO_PD(162),          SH7372_PIN_IO_PD(163),
+        SH7372_PIN_I_PD(164),           SH7372_PIN_IO_PD(165),
+        SH7372_PIN_I_PD(166),           SH7372_PIN_I_PD(167),
+        SH7372_PIN_I_PD(168),           SH7372_PIN_I_PD(169),
+        SH7372_PIN_I_PD(170),           SH7372_PIN_O(171),
+        SH7372_PIN_IO_PU_PD(172),       SH7372_PIN_IO_PU_PD(173),
+        SH7372_PIN_IO_PU_PD(174),       SH7372_PIN_IO_PU_PD(175),
+        SH7372_PIN_IO_PU_PD(176),       SH7372_PIN_IO_PU_PD(177),
+        SH7372_PIN_IO_PU_PD(178),       SH7372_PIN_O(179),
+        SH7372_PIN_IO_PU_PD(180),       SH7372_PIN_IO_PU_PD(181),
+        SH7372_PIN_IO_PU_PD(182),       SH7372_PIN_IO_PU_PD(183),
+        SH7372_PIN_IO_PU_PD(184),       SH7372_PIN_O(185),
+        SH7372_PIN_IO_PU_PD(186),       SH7372_PIN_IO_PU_PD(187),
+        SH7372_PIN_IO_PU_PD(188),       SH7372_PIN_IO_PU_PD(189),
+        SH7372_PIN_IO_PU_PD(190),
 };
 
+/* - BSC -------------------------------------------------------------------- */
+static const unsigned int bsc_data8_pins[] = {
+        /* D[0:7] */
+        46, 47, 48, 49, 50, 51, 52, 53,
+};
+static const unsigned int bsc_data8_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+};
+static const unsigned int bsc_data16_pins[] = {
+        /* D[0:15] */
+        46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
+};
+static const unsigned int bsc_data16_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+        D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+};
+static const unsigned int bsc_cs0_pins[] = {
+        /* CS */
+        62,
+};
+static const unsigned int bsc_cs0_mux[] = {
+        CS0_MARK,
+};
+static const unsigned int bsc_cs2_pins[] = {
+        /* CS */
+        63,
+};
+static const unsigned int bsc_cs2_mux[] = {
+        CS2_MARK,
+};
+static const unsigned int bsc_cs4_pins[] = {
+        /* CS */
+        64,
+};
+static const unsigned int bsc_cs4_mux[] = {
+        CS4_MARK,
+};
+static const unsigned int bsc_cs5a_pins[] = {
+        /* CS */
+        65,
+};
+static const unsigned int bsc_cs5a_mux[] = {
+        CS5A_MARK,
+};
+static const unsigned int bsc_cs5b_pins[] = {
+        /* CS */
+        66,
+};
+static const unsigned int bsc_cs5b_mux[] = {
+        CS5B_MARK,
+};
+static const unsigned int bsc_cs6a_pins[] = {
+        /* CS */
+        67,
+};
+static const unsigned int bsc_cs6a_mux[] = {
+        CS6A_MARK,
+};
+static const unsigned int bsc_rd_we8_pins[] = {
+        /* RD, WE[0] */
+        69, 70,
+};
+static const unsigned int bsc_rd_we8_mux[] = {
+        RD_FSC_MARK, WE0_FWE_MARK,
+};
+static const unsigned int bsc_rd_we16_pins[] = {
+        /* RD, WE[0:1] */
+        69, 70, 71,
+};
+static const unsigned int bsc_rd_we16_mux[] = {
+        RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
+};
+static const unsigned int bsc_bs_pins[] = {
+        /* BS */
+        19,
+};
+static const unsigned int bsc_bs_mux[] = {
+        BS_MARK,
+};
+static const unsigned int bsc_rdwr_pins[] = {
+        /* RDWR */
+        75,
+};
+static const unsigned int bsc_rdwr_mux[] = {
+        RDWR_MARK,
+};
+static const unsigned int bsc_wait_pins[] = {
+        /* WAIT */
+        74,
+};
+static const unsigned int bsc_wait_mux[] = {
+        WAIT_MARK,
+};
+/* - CEU -------------------------------------------------------------------- */
+static const unsigned int ceu_data_0_7_pins[] = {
+        /* D[0:7] */
+        102, 103, 104, 105, 106, 107, 108, 109,
+};
+static const unsigned int ceu_data_0_7_mux[] = {
+        VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK,
+        VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK,
+};
+static const unsigned int ceu_data_8_15_pins[] = {
+        /* D[8:15] */
+        110, 111, 112, 113, 114, 115, 116, 117,
+};
+static const unsigned int ceu_data_8_15_mux[] = {
+        VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
+        VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK,
+};
+static const unsigned int ceu_clk_0_pins[] = {
+        /* CKO */
+        120,
+};
+static const unsigned int ceu_clk_0_mux[] = {
+        VIO_CKO_MARK,
+};
+static const unsigned int ceu_clk_1_pins[] = {
+        /* CKO */
+        16,
+};
+static const unsigned int ceu_clk_1_mux[] = {
+        VIO_CKO1_MARK,
+};
+static const unsigned int ceu_clk_2_pins[] = {
+        /* CKO */
+        17,
+};
+static const unsigned int ceu_clk_2_mux[] = {
+        VIO_CKO2_MARK,
+};
+static const unsigned int ceu_sync_pins[] = {
+        /* CLK, VD, HD */
+        118, 100, 101,
+};
+static const unsigned int ceu_sync_mux[] = {
+        VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK,
+};
+static const unsigned int ceu_field_pins[] = {
+        /* FIELD */
+        119,
+};
+static const unsigned int ceu_field_mux[] = {
+        VIO_FIELD_MARK,
+};
+/* - FLCTL ------------------------------------------------------------------ */
+static const unsigned int flctl_data_pins[] = {
+        /* NAF[0:15] */
+        46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
+};
+static const unsigned int flctl_data_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+        D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+};
+static const unsigned int flctl_ce0_pins[] = {
+        /* CE */
+        68,
+};
+static const unsigned int flctl_ce0_mux[] = {
+        FCE0_MARK,
+};
+static const unsigned int flctl_ce1_pins[] = {
+        /* CE */
+        66,
+};
+static const unsigned int flctl_ce1_mux[] = {
+        FCE1_MARK,
+};
+static const unsigned int flctl_ctrl_pins[] = {
+        /* FCDE, FOE, FSC, FWE, FRB */
+        24, 23, 69, 70, 73,
+};
+static const unsigned int flctl_ctrl_mux[] = {
+        A5_FCDE_MARK, A4_FOE_MARK, RD_FSC_MARK, WE0_FWE_MARK, FRB_MARK,
+};
+/* - FSIA ------------------------------------------------------------------- */
+static const unsigned int fsia_mclk_in_pins[] = {
+        /* CK */
+        4,
+};
+static const unsigned int fsia_mclk_in_mux[] = {
+        FSIACK_MARK,
+};
+static const unsigned int fsia_mclk_out_pins[] = {
+        /* OMC */
+        8,
+};
+static const unsigned int fsia_mclk_out_mux[] = {
+        FSIAOMC_MARK,
+};
+static const unsigned int fsia_sclk_in_pins[] = {
+        /* ILR, IBT */
+        5, 6,
+};
+static const unsigned int fsia_sclk_in_mux[] = {
+        FSIAILR_MARK, FSIAIBT_MARK,
+};
+static const unsigned int fsia_sclk_out_pins[] = {
+        /* OLR, OBT */
+        9, 10,
+};
+static const unsigned int fsia_sclk_out_mux[] = {
+        FSIAOLR_MARK, FSIAOBT_MARK,
+};
+static const unsigned int fsia_data_in_pins[] = {
+        /* ISLD */
+        7,
+};
+static const unsigned int fsia_data_in_mux[] = {
+        FSIAISLD_MARK,
+};
+static const unsigned int fsia_data_out_pins[] = {
+        /* OSLD */
+        11,
+};
+static const unsigned int fsia_data_out_mux[] = {
+        FSIAOSLD_MARK,
+};
+static const unsigned int fsia_spdif_0_pins[] = {
+        /* SPDIF */
+        11,
+};
+static const unsigned int fsia_spdif_0_mux[] = {
+        FSIASPDIF_11_MARK,
+};
+static const unsigned int fsia_spdif_1_pins[] = {
+        /* SPDIF */
+        15,
+};
+static const unsigned int fsia_spdif_1_mux[] = {
+        FSIASPDIF_15_MARK,
+};
+/* - FSIB ------------------------------------------------------------------- */
+static const unsigned int fsib_mclk_in_pins[] = {
+        /* CK */
+        4,
+};
+static const unsigned int fsib_mclk_in_mux[] = {
+        FSIBCK_MARK,
+};
+/* - HDMI ------------------------------------------------------------------- */
+static const unsigned int hdmi_pins[] = {
+        /* HPD, CEC */
+        169, 170,
+};
+static const unsigned int hdmi_mux[] = {
+        HDMI_HPD_MARK, HDMI_CEC_MARK,
+};
+/* - INTC ------------------------------------------------------------------- */
+IRQC_PINS_MUX(0, 6, 162);
+IRQC_PIN_MUX(1, 12);
+IRQC_PINS_MUX(2, 4, 5);
+IRQC_PINS_MUX(3, 8, 16);
+IRQC_PINS_MUX(4, 17, 163);
+IRQC_PIN_MUX(5, 18);
+IRQC_PINS_MUX(6, 39, 164);
+IRQC_PINS_MUX(7, 40, 167);
+IRQC_PINS_MUX(8, 41, 168);
+IRQC_PINS_MUX(9, 42, 169);
+IRQC_PIN_MUX(10, 65);
+IRQC_PIN_MUX(11, 67);
+IRQC_PINS_MUX(12, 80, 137);
+IRQC_PINS_MUX(13, 81, 145);
+IRQC_PINS_MUX(14, 82, 146);
+IRQC_PINS_MUX(15, 83, 147);
+IRQC_PINS_MUX(16, 84, 170);
+IRQC_PIN_MUX(17, 85);
+IRQC_PIN_MUX(18, 86);
+IRQC_PIN_MUX(19, 87);
+IRQC_PIN_MUX(20, 92);
+IRQC_PIN_MUX(21, 93);
+IRQC_PIN_MUX(22, 94);
+IRQC_PIN_MUX(23, 95);
+IRQC_PIN_MUX(24, 112);
+IRQC_PIN_MUX(25, 119);
+IRQC_PINS_MUX(26, 121, 172);
+IRQC_PINS_MUX(27, 122, 180);
+IRQC_PINS_MUX(28, 123, 181);
+IRQC_PINS_MUX(29, 129, 182);
+IRQC_PINS_MUX(30, 130, 183);
+IRQC_PINS_MUX(31, 138, 184);
+/* - KEYSC ------------------------------------------------------------------ */
+static const unsigned int keysc_in04_0_pins[] = {
+        /* KEYIN[0:4] */
+        136, 135, 134, 133, 132,
+};
+static const unsigned int keysc_in04_0_mux[] = {
+        KEYIN0_136_MARK, KEYIN1_135_MARK, KEYIN2_134_MARK, KEYIN3_133_MARK,
+        KEYIN4_MARK,
+};
+static const unsigned int keysc_in04_1_pins[] = {
+        /* KEYIN[0:4] */
+        121, 122, 123, 124, 132,
+};
+static const unsigned int keysc_in04_1_mux[] = {
+        KEYIN0_121_MARK, KEYIN1_122_MARK, KEYIN2_123_MARK, KEYIN3_124_MARK,
+        KEYIN4_MARK,
+};
+static const unsigned int keysc_in5_pins[] = {
+        /* KEYIN5 */
+        131,
+};
+static const unsigned int keysc_in5_mux[] = {
+        KEYIN5_MARK,
+};
+static const unsigned int keysc_in6_pins[] = {
+        /* KEYIN6 */
+        130,
+};
+static const unsigned int keysc_in6_mux[] = {
+        KEYIN6_MARK,
+};
+static const unsigned int keysc_in7_pins[] = {
+        /* KEYIN7 */
+        129,
+};
+static const unsigned int keysc_in7_mux[] = {
+        KEYIN7_MARK,
+};
+static const unsigned int keysc_out4_pins[] = {
+        /* KEYOUT[0:3] */
+        128, 127, 126, 125,
+};
+static const unsigned int keysc_out4_mux[] = {
+        KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+};
+static const unsigned int keysc_out5_pins[] = {
+        /* KEYOUT[0:4] */
+        128, 127, 126, 125, 124,
+};
+static const unsigned int keysc_out5_mux[] = {
+        KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+        KEYOUT4_MARK,
+};
+static const unsigned int keysc_out6_pins[] = {
+        /* KEYOUT[0:5] */
+        128, 127, 126, 125, 124, 123,
+};
+static const unsigned int keysc_out6_mux[] = {
+        KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+        KEYOUT4_MARK, KEYOUT5_MARK,
+};
+static const unsigned int keysc_out8_pins[] = {
+        /* KEYOUT[0:7] */
+        128, 127, 126, 125, 124, 123, 122, 121,
+};
+static const unsigned int keysc_out8_mux[] = {
+        KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+        KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
+};
+/* - LCD -------------------------------------------------------------------- */
+static const unsigned int lcd_data8_pins[] = {
+        /* D[0:7] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+};
+static const unsigned int lcd_data8_mux[] = {
+        /* LCDC */
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+};
+static const unsigned int lcd_data9_pins[] = {
+        /* D[0:8] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+        129,
+        137, 138, 139, 140, 141, 142, 143, 144,
+};
+static const unsigned int lcd_data9_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK,
+};
+static const unsigned int lcd_data12_pins[] = {
+        /* D[0:11] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+        129, 130, 131, 132,
+};
+static const unsigned int lcd_data12_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+};
+static const unsigned int lcd_data16_pins[] = {
+        /* D[0:15] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+        129, 130, 131, 132, 133, 134, 135, 136,
+};
+static const unsigned int lcd_data16_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+        LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+};
+static const unsigned int lcd_data18_pins[] = {
+        /* D[0:17] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+        129, 130, 131, 132, 133, 134, 135, 136,
+        137, 138,
+};
+static const unsigned int lcd_data18_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+        LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+        LCDD16_MARK, LCDD17_MARK,
+};
+static const unsigned int lcd_data24_pins[] = {
+        /* D[0:23] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+        129, 130, 131, 132, 133, 134, 135, 136,
+        137, 138, 139, 140, 141, 142, 143, 144,
+};
+static const unsigned int lcd_data24_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+        LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+        LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
+        LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
+};
+static const unsigned int lcd_display_pins[] = {
+        /* DON */
+        151,
+};
+static const unsigned int lcd_display_mux[] = {
+        LCDDON_MARK,
+};
+static const unsigned int lcd_lclk_pins[] = {
+        /* LCLK */
+        150,
+};
+static const unsigned int lcd_lclk_mux[] = {
+        LCDLCLK_MARK,
+};
+static const unsigned int lcd_sync_pins[] = {
+        /* VSYN, HSYN, DCK, DISP */
+        146, 145, 147, 149,
+};
+static const unsigned int lcd_sync_mux[] = {
+        LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
+};
+static const unsigned int lcd_sys_pins[] = {
+        /* CS, WR, RD, RS */
+        145, 147, 148, 149,
+};
+static const unsigned int lcd_sys_mux[] = {
+        LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, LCDRS_MARK,
+};
 /* - MMCIF ------------------------------------------------------------------ */
 static const unsigned int mmc0_data1_0_pins[] = {
         /* D[0] */
@@ -993,6 +1475,139 @@ static const unsigned int mmc0_ctrl_1_pins[] = {
 static const unsigned int mmc0_ctrl_1_mux[] = {
         MMCCMD1_MARK, MMCCLK1_MARK,
 };
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+        /* RXD, TXD */
+        153, 152,
+};
+static const unsigned int scifa0_data_mux[] = {
+        SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+        /* SCK */
+        156,
+};
+static const unsigned int scifa0_clk_mux[] = {
+        SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+        /* RTS, CTS */
+        157, 158,
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+        SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+        /* RXD, TXD */
+        155, 154,
+};
+static const unsigned int scifa1_data_mux[] = {
+        SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+        /* SCK */
+        159,
+};
+static const unsigned int scifa1_clk_mux[] = {
+        SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+        /* RTS, CTS */
+        160, 161,
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+        SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_pins[] = {
+        /* RXD, TXD */
+        97, 96,
+};
+static const unsigned int scifa2_data_mux[] = {
+        SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
+};
+static const unsigned int scifa2_clk_pins[] = {
+        /* SCK */
+        98,
+};
+static const unsigned int scifa2_clk_mux[] = {
+        SCIFA2_SCK1_MARK,
+};
+static const unsigned int scifa2_ctrl_pins[] = {
+        /* RTS, CTS */
+        95, 94,
+};
+static const unsigned int scifa2_ctrl_mux[] = {
+        SCIFA2_RTS1_MARK, SCIFA2_CTS1_MARK,
+};
+/* - SCIFA3 ----------------------------------------------------------------- */
+static const unsigned int scifa3_data_pins[] = {
+        /* RXD, TXD */
+        144, 143,
+};
+static const unsigned int scifa3_data_mux[] = {
+        SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
+};
+static const unsigned int scifa3_clk_pins[] = {
+        /* SCK */
+        142,
+};
+static const unsigned int scifa3_clk_mux[] = {
+        SCIFA3_SCK_MARK,
+};
+static const unsigned int scifa3_ctrl_0_pins[] = {
+        /* RTS, CTS */
+        44, 43,
+};
+static const unsigned int scifa3_ctrl_0_mux[] = {
+        SCIFA3_RTS_44_MARK, SCIFA3_CTS_43_MARK,
+};
+static const unsigned int scifa3_ctrl_1_pins[] = {
+        /* RTS, CTS */
+        141, 140,
+};
+static const unsigned int scifa3_ctrl_1_mux[] = {
+        SCIFA3_RTS_141_MARK, SCIFA3_CTS_140_MARK,
+};
+/* - SCIFA4 ----------------------------------------------------------------- */
+static const unsigned int scifa4_data_pins[] = {
+        /* RXD, TXD */
+        5, 6,
+};
+static const unsigned int scifa4_data_mux[] = {
+        SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
+};
+/* - SCIFA5 ----------------------------------------------------------------- */
+static const unsigned int scifa5_data_pins[] = {
+        /* RXD, TXD */
+        8, 12,
+};
+static const unsigned int scifa5_data_mux[] = {
+        SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
+};
+/* - SCIFB ------------------------------------------------------------------ */
+static const unsigned int scifb_data_pins[] = {
+        /* RXD, TXD */
+        166, 165,
+};
+static const unsigned int scifb_data_mux[] = {
+        SCIFB_RXD_MARK, SCIFB_TXD_MARK,
+};
+static const unsigned int scifb_clk_pins[] = {
+        /* SCK */
+        162,
+};
+static const unsigned int scifb_clk_mux[] = {
+        SCIFB_SCK_MARK,
+};
+static const unsigned int scifb_ctrl_pins[] = {
+        /* RTS, CTS */
+        163, 164,
+};
+static const unsigned int scifb_ctrl_mux[] = {
+        SCIFB_RTS_MARK, SCIFB_CTS_MARK,
+};
 /* - SDHI0 ------------------------------------------------------------------ */
 static const unsigned int sdhi0_data1_pins[] = {
         /* D0 */
@@ -1073,8 +1688,169 @@ static const unsigned int sdhi2_ctrl_pins[] = {
 static const unsigned int sdhi2_ctrl_mux[] = {
         SDHICMD2_MARK, SDHICLK2_MARK,
 };
+/* - USB0 ------------------------------------------------------------------- */
+static const unsigned int usb0_vbus_pins[] = {
+        /* VBUS */
+        167,
+};
+static const unsigned int usb0_vbus_mux[] = {
+        VBUS0_0_MARK,
+};
+static const unsigned int usb0_otg_id_pins[] = {
+        /* IDIN */
+        113,
+};
+static const unsigned int usb0_otg_id_mux[] = {
+        IDIN_0_MARK,
+};
+static const unsigned int usb0_otg_ctrl_pins[] = {
+        /* PWEN, EXTLP, OVCN, OVCN2 */
+        116, 114, 117, 115,
+};
+static const unsigned int usb0_otg_ctrl_mux[] = {
+        PWEN_0_MARK, EXTLP_0_MARK, OVCN_0_MARK, OVCN2_0_MARK,
+};
+/* - USB1 ------------------------------------------------------------------- */
+static const unsigned int usb1_vbus_pins[] = {
+        /* VBUS */
+        168,
+};
+static const unsigned int usb1_vbus_mux[] = {
+        VBUS0_1_MARK,
+};
+static const unsigned int usb1_otg_id_0_pins[] = {
+        /* IDIN */
+        113,
+};
+static const unsigned int usb1_otg_id_0_mux[] = {
+        IDIN_1_113_MARK,
+};
+static const unsigned int usb1_otg_id_1_pins[] = {
+        /* IDIN */
+        18,
+};
+static const unsigned int usb1_otg_id_1_mux[] = {
+        IDIN_1_18_MARK,
+};
+static const unsigned int usb1_otg_ctrl_0_pins[] = {
+        /* PWEN, EXTLP, OVCN, OVCN2 */
+        115, 116, 114, 117, 113,
+};
+static const unsigned int usb1_otg_ctrl_0_mux[] = {
+        PWEN_1_115_MARK, EXTLP_1_MARK, OVCN_1_114_MARK, OVCN2_1_MARK,
+};
+static const unsigned int usb1_otg_ctrl_1_pins[] = {
+        /* PWEN, EXTLP, OVCN, OVCN2 */
+        138, 116, 162, 117, 18,
+};
+static const unsigned int usb1_otg_ctrl_1_mux[] = {
+        PWEN_1_138_MARK, EXTLP_1_MARK, OVCN_1_162_MARK, OVCN2_1_MARK,
+};
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(bsc_data8),
+        SH_PFC_PIN_GROUP(bsc_data16),
+        SH_PFC_PIN_GROUP(bsc_cs0),
+        SH_PFC_PIN_GROUP(bsc_cs2),
+        SH_PFC_PIN_GROUP(bsc_cs4),
+        SH_PFC_PIN_GROUP(bsc_cs5a),
+        SH_PFC_PIN_GROUP(bsc_cs5b),
+        SH_PFC_PIN_GROUP(bsc_cs6a),
+        SH_PFC_PIN_GROUP(bsc_rd_we8),
+        SH_PFC_PIN_GROUP(bsc_rd_we16),
+        SH_PFC_PIN_GROUP(bsc_bs),
+        SH_PFC_PIN_GROUP(bsc_rdwr),
+        SH_PFC_PIN_GROUP(ceu_data_0_7),
+        SH_PFC_PIN_GROUP(ceu_data_8_15),
+        SH_PFC_PIN_GROUP(ceu_clk_0),
+        SH_PFC_PIN_GROUP(ceu_clk_1),
+        SH_PFC_PIN_GROUP(ceu_clk_2),
+        SH_PFC_PIN_GROUP(ceu_sync),
+        SH_PFC_PIN_GROUP(ceu_field),
+        SH_PFC_PIN_GROUP(flctl_data),
+        SH_PFC_PIN_GROUP(flctl_ce0),
+        SH_PFC_PIN_GROUP(flctl_ce1),
+        SH_PFC_PIN_GROUP(flctl_ctrl),
+        SH_PFC_PIN_GROUP(fsia_mclk_in),
+        SH_PFC_PIN_GROUP(fsia_mclk_out),
+        SH_PFC_PIN_GROUP(fsia_sclk_in),
+        SH_PFC_PIN_GROUP(fsia_sclk_out),
+        SH_PFC_PIN_GROUP(fsia_data_in),
+        SH_PFC_PIN_GROUP(fsia_data_out),
+        SH_PFC_PIN_GROUP(fsia_spdif_0),
+        SH_PFC_PIN_GROUP(fsia_spdif_1),
+        SH_PFC_PIN_GROUP(fsib_mclk_in),
+        SH_PFC_PIN_GROUP(hdmi),
+        SH_PFC_PIN_GROUP(intc_irq0_0),
+        SH_PFC_PIN_GROUP(intc_irq0_1),
+        SH_PFC_PIN_GROUP(intc_irq1),
+        SH_PFC_PIN_GROUP(intc_irq2_0),
+        SH_PFC_PIN_GROUP(intc_irq2_1),
+        SH_PFC_PIN_GROUP(intc_irq3_0),
+        SH_PFC_PIN_GROUP(intc_irq3_1),
+        SH_PFC_PIN_GROUP(intc_irq4_0),
+        SH_PFC_PIN_GROUP(intc_irq4_1),
+        SH_PFC_PIN_GROUP(intc_irq5),
+        SH_PFC_PIN_GROUP(intc_irq6_0),
+        SH_PFC_PIN_GROUP(intc_irq6_1),
+        SH_PFC_PIN_GROUP(intc_irq7_0),
+        SH_PFC_PIN_GROUP(intc_irq7_1),
+        SH_PFC_PIN_GROUP(intc_irq8_0),
+        SH_PFC_PIN_GROUP(intc_irq8_1),
+        SH_PFC_PIN_GROUP(intc_irq9_0),
+        SH_PFC_PIN_GROUP(intc_irq9_1),
+        SH_PFC_PIN_GROUP(intc_irq10),
+        SH_PFC_PIN_GROUP(intc_irq11),
+        SH_PFC_PIN_GROUP(intc_irq12_0),
+        SH_PFC_PIN_GROUP(intc_irq12_1),
+        SH_PFC_PIN_GROUP(intc_irq13_0),
+        SH_PFC_PIN_GROUP(intc_irq13_1),
+        SH_PFC_PIN_GROUP(intc_irq14_0),
+        SH_PFC_PIN_GROUP(intc_irq14_1),
+        SH_PFC_PIN_GROUP(intc_irq15_0),
+        SH_PFC_PIN_GROUP(intc_irq15_1),
+        SH_PFC_PIN_GROUP(intc_irq16_0),
+        SH_PFC_PIN_GROUP(intc_irq16_1),
+        SH_PFC_PIN_GROUP(intc_irq17),
+        SH_PFC_PIN_GROUP(intc_irq18),
+        SH_PFC_PIN_GROUP(intc_irq19),
+        SH_PFC_PIN_GROUP(intc_irq20),
+        SH_PFC_PIN_GROUP(intc_irq21),
+        SH_PFC_PIN_GROUP(intc_irq22),
+        SH_PFC_PIN_GROUP(intc_irq23),
+        SH_PFC_PIN_GROUP(intc_irq24),
+        SH_PFC_PIN_GROUP(intc_irq25),
+        SH_PFC_PIN_GROUP(intc_irq26_0),
+        SH_PFC_PIN_GROUP(intc_irq26_1),
+        SH_PFC_PIN_GROUP(intc_irq27_0),
+        SH_PFC_PIN_GROUP(intc_irq27_1),
+        SH_PFC_PIN_GROUP(intc_irq28_0),
+        SH_PFC_PIN_GROUP(intc_irq28_1),
+        SH_PFC_PIN_GROUP(intc_irq29_0),
+        SH_PFC_PIN_GROUP(intc_irq29_1),
+        SH_PFC_PIN_GROUP(intc_irq30_0),
+        SH_PFC_PIN_GROUP(intc_irq30_1),
+        SH_PFC_PIN_GROUP(intc_irq31_0),
+        SH_PFC_PIN_GROUP(intc_irq31_1),
+        SH_PFC_PIN_GROUP(keysc_in04_0),
+        SH_PFC_PIN_GROUP(keysc_in04_1),
+        SH_PFC_PIN_GROUP(keysc_in5),
+        SH_PFC_PIN_GROUP(keysc_in6),
+        SH_PFC_PIN_GROUP(keysc_in7),
+        SH_PFC_PIN_GROUP(keysc_out4),
+        SH_PFC_PIN_GROUP(keysc_out5),
+        SH_PFC_PIN_GROUP(keysc_out6),
+        SH_PFC_PIN_GROUP(keysc_out8),
+        SH_PFC_PIN_GROUP(lcd_data8),
+        SH_PFC_PIN_GROUP(lcd_data9),
+        SH_PFC_PIN_GROUP(lcd_data12),
+        SH_PFC_PIN_GROUP(lcd_data16),
+        SH_PFC_PIN_GROUP(lcd_data18),
+        SH_PFC_PIN_GROUP(lcd_data24),
+        SH_PFC_PIN_GROUP(lcd_display),
+        SH_PFC_PIN_GROUP(lcd_lclk),
+        SH_PFC_PIN_GROUP(lcd_sync),
+        SH_PFC_PIN_GROUP(lcd_sys),
         SH_PFC_PIN_GROUP(mmc0_data1_0),
         SH_PFC_PIN_GROUP(mmc0_data4_0),
         SH_PFC_PIN_GROUP(mmc0_data8_0),
@@ -1083,6 +1859,24 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(mmc0_data4_1),
         SH_PFC_PIN_GROUP(mmc0_data8_1),
         SH_PFC_PIN_GROUP(mmc0_ctrl_1),
+        SH_PFC_PIN_GROUP(scifa0_data),
+        SH_PFC_PIN_GROUP(scifa0_clk),
+        SH_PFC_PIN_GROUP(scifa0_ctrl),
+        SH_PFC_PIN_GROUP(scifa1_data),
+        SH_PFC_PIN_GROUP(scifa1_clk),
+        SH_PFC_PIN_GROUP(scifa1_ctrl),
+        SH_PFC_PIN_GROUP(scifa2_data),
+        SH_PFC_PIN_GROUP(scifa2_clk),
+        SH_PFC_PIN_GROUP(scifa2_ctrl),
+        SH_PFC_PIN_GROUP(scifa3_data),
+        SH_PFC_PIN_GROUP(scifa3_clk),
+        SH_PFC_PIN_GROUP(scifa3_ctrl_0),
+        SH_PFC_PIN_GROUP(scifa3_ctrl_1),
+        SH_PFC_PIN_GROUP(scifa4_data),
+        SH_PFC_PIN_GROUP(scifa5_data),
+        SH_PFC_PIN_GROUP(scifb_data),
+        SH_PFC_PIN_GROUP(scifb_clk),
+        SH_PFC_PIN_GROUP(scifb_ctrl),
         SH_PFC_PIN_GROUP(sdhi0_data1),
         SH_PFC_PIN_GROUP(sdhi0_data4),
         SH_PFC_PIN_GROUP(sdhi0_ctrl),
@@ -1094,6 +1888,144 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(sdhi2_data1),
         SH_PFC_PIN_GROUP(sdhi2_data4),
         SH_PFC_PIN_GROUP(sdhi2_ctrl),
+        SH_PFC_PIN_GROUP(usb0_vbus),
+        SH_PFC_PIN_GROUP(usb0_otg_id),
+        SH_PFC_PIN_GROUP(usb0_otg_ctrl),
+        SH_PFC_PIN_GROUP(usb1_vbus),
+        SH_PFC_PIN_GROUP(usb1_otg_id_0),
+        SH_PFC_PIN_GROUP(usb1_otg_id_1),
+        SH_PFC_PIN_GROUP(usb1_otg_ctrl_0),
+        SH_PFC_PIN_GROUP(usb1_otg_ctrl_1),
+};
+
+static const char * const bsc_groups[] = {
+        "bsc_data8",
+        "bsc_data16",
+        "bsc_cs0",
+        "bsc_cs2",
+        "bsc_cs4",
+        "bsc_cs5a",
+        "bsc_cs5b",
+        "bsc_cs6a",
+        "bsc_rd_we8",
+        "bsc_rd_we16",
+        "bsc_bs",
+        "bsc_rdwr",
+};
+
+static const char * const ceu_groups[] = {
+        "ceu_data_0_7",
+        "ceu_data_8_15",
+        "ceu_clk_0",
+        "ceu_clk_1",
+        "ceu_clk_2",
+        "ceu_sync",
+        "ceu_field",
+};
+
+static const char * const flctl_groups[] = {
+        "flctl_data",
+        "flctl_ce0",
+        "flctl_ce1",
+        "flctl_ctrl",
+};
+
+static const char * const fsia_groups[] = {
+        "fsia_mclk_in",
+        "fsia_mclk_out",
+        "fsia_sclk_in",
+        "fsia_sclk_out",
+        "fsia_data_in",
+        "fsia_data_out",
+        "fsia_spdif_0",
+        "fsia_spdif_1",
+};
+
+static const char * const fsib_groups[] = {
+        "fsib_mclk_in",
+};
+
+static const char * const hdmi_groups[] = {
+        "hdmi",
+};
+
+static const char * const intc_groups[] = {
+        "intc_irq0_0",
+        "intc_irq0_1",
+        "intc_irq1",
+        "intc_irq2_0",
+        "intc_irq2_1",
+        "intc_irq3_0",
+        "intc_irq3_1",
+        "intc_irq4_0",
+        "intc_irq4_1",
+        "intc_irq5",
+        "intc_irq6_0",
+        "intc_irq6_1",
+        "intc_irq7_0",
+        "intc_irq7_1",
+        "intc_irq8_0",
+        "intc_irq8_1",
+        "intc_irq9_0",
+        "intc_irq9_1",
+        "intc_irq10",
+        "intc_irq11",
+        "intc_irq12_0",
+        "intc_irq12_1",
+        "intc_irq13_0",
+        "intc_irq13_1",
+        "intc_irq14_0",
+        "intc_irq14_1",
+        "intc_irq15_0",
+        "intc_irq15_1",
+        "intc_irq16_0",
+        "intc_irq16_1",
+        "intc_irq17",
+        "intc_irq18",
+        "intc_irq19",
+        "intc_irq20",
+        "intc_irq21",
+        "intc_irq22",
+        "intc_irq23",
+        "intc_irq24",
+        "intc_irq25",
+        "intc_irq26_0",
+        "intc_irq26_1",
+        "intc_irq27_0",
+        "intc_irq27_1",
+        "intc_irq28_0",
+        "intc_irq28_1",
+        "intc_irq29_0",
+        "intc_irq29_1",
+        "intc_irq30_0",
+        "intc_irq30_1",
+        "intc_irq31_0",
+        "intc_irq31_1",
+};
+
+static const char * const keysc_groups[] = {
+        "keysc_in04_0",
+        "keysc_in04_1",
+        "keysc_in5",
+        "keysc_in6",
+        "keysc_in7",
+        "keysc_out4",
+        "keysc_out5",
+        "keysc_out6",
+        "keysc_out8",
+};
+
+static const char * const lcd_groups[] = {
+        "lcd_data8",
+        "lcd_data9",
+        "lcd_data12",
+        "lcd_data16",
+        "lcd_data18",
+        "lcd_data24",
+        "lcd_display",
+        "lcd_lclk",
+        "lcd_sync",
+        "lcd_sys",
 };
 
 static const char * const mmc0_groups[] = {
@@ -1107,6 +2039,45 @@ static const char * const mmc0_groups[] = {
         "mmc0_ctrl_1",
 };
 
+static const char * const scifa0_groups[] = {
+        "scifa0_data",
+        "scifa0_clk",
+        "scifa0_ctrl",
+};
+
+static const char * const scifa1_groups[] = {
+        "scifa1_data",
+        "scifa1_clk",
+        "scifa1_ctrl",
+};
+
+static const char * const scifa2_groups[] = {
+        "scifa2_data",
+        "scifa2_clk",
+        "scifa2_ctrl",
+};
+
+static const char * const scifa3_groups[] = {
+        "scifa3_data",
+        "scifa3_clk",
+        "scifa3_ctrl_0",
+        "scifa3_ctrl_1",
+};
+
+static const char * const scifa4_groups[] = {
+        "scifa4_data",
+};
+
+static const char * const scifa5_groups[] = {
+        "scifa5_data",
+};
+
+static const char * const scifb_groups[] = {
+        "scifb_data",
+        "scifb_clk",
+        "scifb_ctrl",
+};
+
 static const char * const sdhi0_groups[] = {
         "sdhi0_data1",
         "sdhi0_data4",
@@ -1127,256 +2098,55 @@ static const char * const sdhi2_groups[] = {
         "sdhi2_ctrl",
 };
 
+static const char * const usb0_groups[] = {
+        "usb0_vbus",
+        "usb0_otg_id",
+        "usb0_otg_ctrl",
+};
+
+static const char * const usb1_groups[] = {
+        "usb1_vbus",
+        "usb1_otg_id_0",
+        "usb1_otg_id_1",
+        "usb1_otg_ctrl_0",
+        "usb1_otg_ctrl_1",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(bsc),
+        SH_PFC_FUNCTION(ceu),
+        SH_PFC_FUNCTION(flctl),
+        SH_PFC_FUNCTION(fsia),
+        SH_PFC_FUNCTION(fsib),
+        SH_PFC_FUNCTION(hdmi),
+        SH_PFC_FUNCTION(intc),
+        SH_PFC_FUNCTION(keysc),
+        SH_PFC_FUNCTION(lcd),
         SH_PFC_FUNCTION(mmc0),
+        SH_PFC_FUNCTION(scifa0),
+        SH_PFC_FUNCTION(scifa1),
+        SH_PFC_FUNCTION(scifa2),
+        SH_PFC_FUNCTION(scifa3),
+        SH_PFC_FUNCTION(scifa4),
+        SH_PFC_FUNCTION(scifa5),
+        SH_PFC_FUNCTION(scifb),
         SH_PFC_FUNCTION(sdhi0),
         SH_PFC_FUNCTION(sdhi1),
         SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(usb0),
+        SH_PFC_FUNCTION(usb1),
 };
 
-#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-        /* IRQ */
-        GPIO_FN(IRQ0_6),        GPIO_FN(IRQ0_162),      GPIO_FN(IRQ1),
-        GPIO_FN(IRQ2_4),        GPIO_FN(IRQ2_5),        GPIO_FN(IRQ3_8),
-        GPIO_FN(IRQ3_16),       GPIO_FN(IRQ4_17),       GPIO_FN(IRQ4_163),
-        GPIO_FN(IRQ5),          GPIO_FN(IRQ6_39),       GPIO_FN(IRQ6_164),
-        GPIO_FN(IRQ7_40),       GPIO_FN(IRQ7_167),      GPIO_FN(IRQ8_41),
-        GPIO_FN(IRQ8_168),      GPIO_FN(IRQ9_42),       GPIO_FN(IRQ9_169),
-        GPIO_FN(IRQ10),         GPIO_FN(IRQ11),         GPIO_FN(IRQ12_80),
-        GPIO_FN(IRQ12_137),     GPIO_FN(IRQ13_81),      GPIO_FN(IRQ13_145),
-        GPIO_FN(IRQ14_82),      GPIO_FN(IRQ14_146),     GPIO_FN(IRQ15_83),
-        GPIO_FN(IRQ15_147),     GPIO_FN(IRQ16_84),      GPIO_FN(IRQ16_170),
-        GPIO_FN(IRQ17),         GPIO_FN(IRQ18),         GPIO_FN(IRQ19),
-        GPIO_FN(IRQ20),         GPIO_FN(IRQ21),         GPIO_FN(IRQ22),
-        GPIO_FN(IRQ23),         GPIO_FN(IRQ24),         GPIO_FN(IRQ25),
-        GPIO_FN(IRQ26_121),     GPIO_FN(IRQ26_172),     GPIO_FN(IRQ27_122),
-        GPIO_FN(IRQ27_180),     GPIO_FN(IRQ28_123),     GPIO_FN(IRQ28_181),
-        GPIO_FN(IRQ29_129),     GPIO_FN(IRQ29_182),     GPIO_FN(IRQ30_130),
-        GPIO_FN(IRQ30_183),     GPIO_FN(IRQ31_138),     GPIO_FN(IRQ31_184),
-
-        /* MSIOF0 */
-        GPIO_FN(MSIOF0_TSYNC),  GPIO_FN(MSIOF0_TSCK),   GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(MSIOF0_RSCK),   GPIO_FN(MSIOF0_RSYNC),  GPIO_FN(MSIOF0_MCK0),
-        GPIO_FN(MSIOF0_MCK1),   GPIO_FN(MSIOF0_SS1),    GPIO_FN(MSIOF0_SS2),
-        GPIO_FN(MSIOF0_TXD),
-
-        /* MSIOF1 */
-        GPIO_FN(MSIOF1_TSCK_39),        GPIO_FN(MSIOF1_TSCK_88),
-        GPIO_FN(MSIOF1_TSYNC_40),       GPIO_FN(MSIOF1_TSYNC_89),
-        GPIO_FN(MSIOF1_TXD_41),         GPIO_FN(MSIOF1_TXD_90),
-        GPIO_FN(MSIOF1_RXD_42),         GPIO_FN(MSIOF1_RXD_91),
-        GPIO_FN(MSIOF1_SS1_43),         GPIO_FN(MSIOF1_SS1_92),
-        GPIO_FN(MSIOF1_SS2_44),         GPIO_FN(MSIOF1_SS2_93),
-        GPIO_FN(MSIOF1_RSCK),           GPIO_FN(MSIOF1_RSYNC),
-        GPIO_FN(MSIOF1_MCK0),           GPIO_FN(MSIOF1_MCK1),
-
-        /* MSIOF2 */
-        GPIO_FN(MSIOF2_RSCK),   GPIO_FN(MSIOF2_RSYNC),  GPIO_FN(MSIOF2_MCK0),
-        GPIO_FN(MSIOF2_MCK1),   GPIO_FN(MSIOF2_SS1),    GPIO_FN(MSIOF2_SS2),
-        GPIO_FN(MSIOF2_TSYNC),  GPIO_FN(MSIOF2_TSCK),   GPIO_FN(MSIOF2_RXD),
-        GPIO_FN(MSIOF2_TXD),
-
-        /* BBIF1 */
-        GPIO_FN(BBIF1_RXD),     GPIO_FN(BBIF1_TSYNC),   GPIO_FN(BBIF1_TSCK),
-        GPIO_FN(BBIF1_TXD),     GPIO_FN(BBIF1_RSCK),    GPIO_FN(BBIF1_RSYNC),
-        GPIO_FN(BBIF1_FLOW),    GPIO_FN(BB_RX_FLOW_N),
-
-        /* BBIF2 */
-        GPIO_FN(BBIF2_TSCK1),   GPIO_FN(BBIF2_TSYNC1),
-        GPIO_FN(BBIF2_TXD1),    GPIO_FN(BBIF2_RXD),
-
-        /* FSI */
-        GPIO_FN(FSIACK),        GPIO_FN(FSIBCK),        GPIO_FN(FSIAILR),
-        GPIO_FN(FSIAIBT),       GPIO_FN(FSIAISLD),      GPIO_FN(FSIAOMC),
-        GPIO_FN(FSIAOLR),       GPIO_FN(FSIAOBT),       GPIO_FN(FSIAOSLD),
-        GPIO_FN(FSIASPDIF_11),  GPIO_FN(FSIASPDIF_15),
-
-        /* FMSI */
-        GPIO_FN(FMSOCK),        GPIO_FN(FMSOOLR),       GPIO_FN(FMSIOLR),
-        GPIO_FN(FMSOOBT),       GPIO_FN(FMSIOBT),       GPIO_FN(FMSOSLD),
-        GPIO_FN(FMSOILR),       GPIO_FN(FMSIILR),       GPIO_FN(FMSOIBT),
-        GPIO_FN(FMSIIBT),       GPIO_FN(FMSISLD),       GPIO_FN(FMSICK),
-
-        /* SCIFA0 */
-        GPIO_FN(SCIFA0_TXD),    GPIO_FN(SCIFA0_RXD),    GPIO_FN(SCIFA0_SCK),
-        GPIO_FN(SCIFA0_RTS),    GPIO_FN(SCIFA0_CTS),
-
-        /* SCIFA1 */
-        GPIO_FN(SCIFA1_TXD),    GPIO_FN(SCIFA1_RXD),    GPIO_FN(SCIFA1_SCK),
-        GPIO_FN(SCIFA1_RTS),    GPIO_FN(SCIFA1_CTS),
-
-        /* SCIFA2 */
-        GPIO_FN(SCIFA2_CTS1),   GPIO_FN(SCIFA2_RTS1),   GPIO_FN(SCIFA2_TXD1),
-        GPIO_FN(SCIFA2_RXD1),   GPIO_FN(SCIFA2_SCK1),
-
-        /* SCIFA3 */
-        GPIO_FN(SCIFA3_CTS_43),         GPIO_FN(SCIFA3_CTS_140),
-        GPIO_FN(SCIFA3_RTS_44),         GPIO_FN(SCIFA3_RTS_141),
-        GPIO_FN(SCIFA3_SCK),            GPIO_FN(SCIFA3_TXD),
-        GPIO_FN(SCIFA3_RXD),
-
-        /* SCIFA4 */
-        GPIO_FN(SCIFA4_RXD),    GPIO_FN(SCIFA4_TXD),
-
-        /* SCIFA5 */
-        GPIO_FN(SCIFA5_RXD),    GPIO_FN(SCIFA5_TXD),
-
-        /* SCIFB */
-        GPIO_FN(SCIFB_SCK),     GPIO_FN(SCIFB_RTS),     GPIO_FN(SCIFB_CTS),
-        GPIO_FN(SCIFB_TXD),     GPIO_FN(SCIFB_RXD),
-
-        /* CEU */
-        GPIO_FN(VIO_HD),        GPIO_FN(VIO_CKO1),      GPIO_FN(VIO_CKO2),
-        GPIO_FN(VIO_VD),        GPIO_FN(VIO_CLK),       GPIO_FN(VIO_FIELD),
-        GPIO_FN(VIO_CKO),       GPIO_FN(VIO_D0),        GPIO_FN(VIO_D1),
-        GPIO_FN(VIO_D2),        GPIO_FN(VIO_D3),        GPIO_FN(VIO_D4),
-        GPIO_FN(VIO_D5),        GPIO_FN(VIO_D6),        GPIO_FN(VIO_D7),
-        GPIO_FN(VIO_D8),        GPIO_FN(VIO_D9),        GPIO_FN(VIO_D10),
-        GPIO_FN(VIO_D11),       GPIO_FN(VIO_D12),       GPIO_FN(VIO_D13),
-        GPIO_FN(VIO_D14),       GPIO_FN(VIO_D15),
-
-        /* USB0 */
-        GPIO_FN(IDIN_0),        GPIO_FN(EXTLP_0),       GPIO_FN(OVCN2_0),
-        GPIO_FN(PWEN_0),        GPIO_FN(OVCN_0),        GPIO_FN(VBUS0_0),
-
-        /* USB1 */
-        GPIO_FN(IDIN_1_18),     GPIO_FN(IDIN_1_113),
-        GPIO_FN(OVCN_1_114),    GPIO_FN(OVCN_1_162),
-        GPIO_FN(PWEN_1_115),    GPIO_FN(PWEN_1_138),
-        GPIO_FN(EXTLP_1),       GPIO_FN(OVCN2_1),
-        GPIO_FN(VBUS0_1),
-
-        /* GPIO */
-        GPIO_FN(GPI0),  GPIO_FN(GPI1),  GPIO_FN(GPO0),  GPIO_FN(GPO1),
-
-        /* BSC */
-        GPIO_FN(BS),    GPIO_FN(WE1),   GPIO_FN(CKO),
-        GPIO_FN(WAIT),  GPIO_FN(RDWR),
-
-        GPIO_FN(A0),    GPIO_FN(A1),    GPIO_FN(A2),
-        GPIO_FN(A3),    GPIO_FN(A6),    GPIO_FN(A7),
-        GPIO_FN(A8),    GPIO_FN(A9),    GPIO_FN(A10),
-        GPIO_FN(A11),   GPIO_FN(A12),   GPIO_FN(A13),
-        GPIO_FN(A14),   GPIO_FN(A15),   GPIO_FN(A16),
-        GPIO_FN(A17),   GPIO_FN(A18),   GPIO_FN(A19),
-        GPIO_FN(A20),   GPIO_FN(A21),   GPIO_FN(A22),
-        GPIO_FN(A23),   GPIO_FN(A24),   GPIO_FN(A25),
-        GPIO_FN(A26),
-
-        GPIO_FN(CS0),   GPIO_FN(CS2),   GPIO_FN(CS4),
-        GPIO_FN(CS5A),  GPIO_FN(CS5B),  GPIO_FN(CS6A),
-
-        /* BSC/FLCTL */
-        GPIO_FN(RD_FSC),        GPIO_FN(WE0_FWE),       GPIO_FN(A4_FOE),
-        GPIO_FN(A5_FCDE),       GPIO_FN(D0_NAF0),       GPIO_FN(D1_NAF1),
-        GPIO_FN(D2_NAF2),       GPIO_FN(D3_NAF3),       GPIO_FN(D4_NAF4),
-        GPIO_FN(D5_NAF5),       GPIO_FN(D6_NAF6),       GPIO_FN(D7_NAF7),
-        GPIO_FN(D8_NAF8),       GPIO_FN(D9_NAF9),       GPIO_FN(D10_NAF10),
-        GPIO_FN(D11_NAF11),     GPIO_FN(D12_NAF12),     GPIO_FN(D13_NAF13),
-        GPIO_FN(D14_NAF14),     GPIO_FN(D15_NAF15),
-
-        /* SPU2 */
-        GPIO_FN(VINT_I),
-
-        /* FLCTL */
-        GPIO_FN(FCE1),  GPIO_FN(FCE0),  GPIO_FN(FRB),
-
-        /* HSI */
-        GPIO_FN(GP_RX_FLAG),    GPIO_FN(GP_RX_DATA),    GPIO_FN(GP_TX_READY),
-        GPIO_FN(GP_RX_WAKE),    GPIO_FN(MP_TX_FLAG),    GPIO_FN(MP_TX_DATA),
-        GPIO_FN(MP_RX_READY),   GPIO_FN(MP_TX_WAKE),
-
-        /* MFI */
-        GPIO_FN(MFIv6),
-        GPIO_FN(MFIv4),
-
-        GPIO_FN(MEMC_BUSCLK_MEMC_A0),   GPIO_FN(MEMC_ADV_MEMC_DREQ0),
-        GPIO_FN(MEMC_WAIT_MEMC_DREQ1),  GPIO_FN(MEMC_CS1_MEMC_A1),
-        GPIO_FN(MEMC_CS0),      GPIO_FN(MEMC_NOE),
-        GPIO_FN(MEMC_NWE),      GPIO_FN(MEMC_INT),
-
-        GPIO_FN(MEMC_AD0),      GPIO_FN(MEMC_AD1),      GPIO_FN(MEMC_AD2),
-        GPIO_FN(MEMC_AD3),      GPIO_FN(MEMC_AD4),      GPIO_FN(MEMC_AD5),
-        GPIO_FN(MEMC_AD6),      GPIO_FN(MEMC_AD7),      GPIO_FN(MEMC_AD8),
-        GPIO_FN(MEMC_AD9),      GPIO_FN(MEMC_AD10),     GPIO_FN(MEMC_AD11),
-        GPIO_FN(MEMC_AD12),     GPIO_FN(MEMC_AD13),     GPIO_FN(MEMC_AD14),
-        GPIO_FN(MEMC_AD15),
-
-        /* SIM */
-        GPIO_FN(SIM_RST),       GPIO_FN(SIM_CLK),       GPIO_FN(SIM_D),
-
-        /* TPU */
-        GPIO_FN(TPU0TO0),       GPIO_FN(TPU0TO1),       GPIO_FN(TPU0TO2_93),
-        GPIO_FN(TPU0TO2_99),    GPIO_FN(TPU0TO3),
-
-        /* I2C2 */
-        GPIO_FN(I2C_SCL2),      GPIO_FN(I2C_SDA2),
-
-        /* I2C3(1) */
-        GPIO_FN(I2C_SCL3),      GPIO_FN(I2C_SDA3),
-
-        /* I2C3(2) */
-        GPIO_FN(I2C_SCL3S),     GPIO_FN(I2C_SDA3S),
-
-        /* I2C4(2) */
-        GPIO_FN(I2C_SCL4),      GPIO_FN(I2C_SDA4),
-
-        /* I2C4(2) */
-        GPIO_FN(I2C_SCL4S),     GPIO_FN(I2C_SDA4S),
-
-        /* KEYSC */
-        GPIO_FN(KEYOUT0),       GPIO_FN(KEYIN0_121),    GPIO_FN(KEYIN0_136),
-        GPIO_FN(KEYOUT1),       GPIO_FN(KEYIN1_122),    GPIO_FN(KEYIN1_135),
-        GPIO_FN(KEYOUT2),       GPIO_FN(KEYIN2_123),    GPIO_FN(KEYIN2_134),
-        GPIO_FN(KEYOUT3),       GPIO_FN(KEYIN3_124),    GPIO_FN(KEYIN3_133),
-        GPIO_FN(KEYOUT4),       GPIO_FN(KEYIN4),        GPIO_FN(KEYOUT5),
-        GPIO_FN(KEYIN5),        GPIO_FN(KEYOUT6),       GPIO_FN(KEYIN6),
-        GPIO_FN(KEYOUT7),       GPIO_FN(KEYIN7),
-
-        /* LCDC */
-        GPIO_FN(LCDHSYN),       GPIO_FN(LCDCS), GPIO_FN(LCDVSYN),
-        GPIO_FN(LCDDCK),        GPIO_FN(LCDWR), GPIO_FN(LCDRD),
-        GPIO_FN(LCDDISP),       GPIO_FN(LCDRS), GPIO_FN(LCDLCLK),
-        GPIO_FN(LCDDON),
-
-        GPIO_FN(LCDD0),         GPIO_FN(LCDD1),         GPIO_FN(LCDD2),
-        GPIO_FN(LCDD3),         GPIO_FN(LCDD4),         GPIO_FN(LCDD5),
-        GPIO_FN(LCDD6),         GPIO_FN(LCDD7),         GPIO_FN(LCDD8),
-        GPIO_FN(LCDD9),         GPIO_FN(LCDD10),        GPIO_FN(LCDD11),
-        GPIO_FN(LCDD12),        GPIO_FN(LCDD13),        GPIO_FN(LCDD14),
-        GPIO_FN(LCDD15),        GPIO_FN(LCDD16),        GPIO_FN(LCDD17),
-        GPIO_FN(LCDD18),        GPIO_FN(LCDD19),        GPIO_FN(LCDD20),
-        GPIO_FN(LCDD21),        GPIO_FN(LCDD22),        GPIO_FN(LCDD23),
-
-        GPIO_FN(LCDC0_SELECT),
-        GPIO_FN(LCDC1_SELECT),
-
-        /* IRDA */
-        GPIO_FN(IRDA_OUT),      GPIO_FN(IRDA_IN),       GPIO_FN(IRDA_FIRSEL),
-        GPIO_FN(IROUT_139),     GPIO_FN(IROUT_140),
-
-        /* TSIF1 */
-        GPIO_FN(TS0_1SELECT),
-        GPIO_FN(TS0_2SELECT),
-        GPIO_FN(TS1_1SELECT),
-        GPIO_FN(TS1_2SELECT),
-
-        GPIO_FN(TS_SPSYNC1),    GPIO_FN(TS_SDAT1),
-        GPIO_FN(TS_SDEN1),      GPIO_FN(TS_SCK1),
-
-        /* TSIF2 */
-        GPIO_FN(TS_SPSYNC2),    GPIO_FN(TS_SDAT2),
-        GPIO_FN(TS_SDEN2),      GPIO_FN(TS_SCK2),
-
-        /* HDMI */
-        GPIO_FN(HDMI_HPD),      GPIO_FN(HDMI_CEC),
-
-        /* SDENC */
-        GPIO_FN(SDENC_CPG),
-        GPIO_FN(SDENC_DV_CLKI),
-};
+#undef PORTCR
+#define PORTCR(nr, reg)                                                 \
+        {                                                               \
+                PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {             \
+                        _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT),     \
+                                PORT##nr##_FN0, PORT##nr##_FN1,         \
+                                PORT##nr##_FN2, PORT##nr##_FN3,         \
+                                PORT##nr##_FN4, PORT##nr##_FN5,         \
+                                PORT##nr##_FN6, PORT##nr##_FN7 }        \
+        }
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         PORTCR(0,       0xE6051000), /* PORT0CR */
@@ -1776,45 +2546,114 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
 #define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
 #define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
 static const struct pinmux_irq pinmux_irqs[] = {
-        PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT6, GPIO_PORT162),
-        PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT12),
-        PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT4, GPIO_PORT5),
-        PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT8, GPIO_PORT16),
-        PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT17, GPIO_PORT163),
-        PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT18),
-        PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT39, GPIO_PORT164),
-        PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT40, GPIO_PORT167),
-        PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT41, GPIO_PORT168),
-        PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT42, GPIO_PORT169),
-        PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT65),
-        PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT67),
-        PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT80, GPIO_PORT137),
-        PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT81, GPIO_PORT145),
-        PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT82, GPIO_PORT146),
-        PINMUX_IRQ(EXT_IRQ16L(15), GPIO_PORT83, GPIO_PORT147),
-        PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT84, GPIO_PORT170),
-        PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT85),
-        PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT86),
-        PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT87),
-        PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT92),
-        PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT93),
-        PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT94),
-        PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT95),
-        PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT112),
-        PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT119),
-        PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT121, GPIO_PORT172),
-        PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT122, GPIO_PORT180),
-        PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT123, GPIO_PORT181),
-        PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT129, GPIO_PORT182),
-        PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT130, GPIO_PORT183),
-        PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT138, GPIO_PORT184),
+        PINMUX_IRQ(EXT_IRQ16L(0), 6, 162),
+        PINMUX_IRQ(EXT_IRQ16L(1), 12),
+        PINMUX_IRQ(EXT_IRQ16L(2), 4, 5),
+        PINMUX_IRQ(EXT_IRQ16L(3), 8, 16),
+        PINMUX_IRQ(EXT_IRQ16L(4), 17, 163),
+        PINMUX_IRQ(EXT_IRQ16L(5), 18),
+        PINMUX_IRQ(EXT_IRQ16L(6), 39, 164),
+        PINMUX_IRQ(EXT_IRQ16L(7), 40, 167),
+        PINMUX_IRQ(EXT_IRQ16L(8), 41, 168),
+        PINMUX_IRQ(EXT_IRQ16L(9), 42, 169),
+        PINMUX_IRQ(EXT_IRQ16L(10), 65),
+        PINMUX_IRQ(EXT_IRQ16L(11), 67),
+        PINMUX_IRQ(EXT_IRQ16L(12), 80, 137),
+        PINMUX_IRQ(EXT_IRQ16L(13), 81, 145),
+        PINMUX_IRQ(EXT_IRQ16L(14), 82, 146),
+        PINMUX_IRQ(EXT_IRQ16L(15), 83, 147),
+        PINMUX_IRQ(EXT_IRQ16H(16), 84, 170),
+        PINMUX_IRQ(EXT_IRQ16H(17), 85),
+        PINMUX_IRQ(EXT_IRQ16H(18), 86),
+        PINMUX_IRQ(EXT_IRQ16H(19), 87),
+        PINMUX_IRQ(EXT_IRQ16H(20), 92),
+        PINMUX_IRQ(EXT_IRQ16H(21), 93),
+        PINMUX_IRQ(EXT_IRQ16H(22), 94),
+        PINMUX_IRQ(EXT_IRQ16H(23), 95),
+        PINMUX_IRQ(EXT_IRQ16H(24), 112),
+        PINMUX_IRQ(EXT_IRQ16H(25), 119),
+        PINMUX_IRQ(EXT_IRQ16H(26), 121, 172),
+        PINMUX_IRQ(EXT_IRQ16H(27), 122, 180),
+        PINMUX_IRQ(EXT_IRQ16H(28), 123, 181),
+        PINMUX_IRQ(EXT_IRQ16H(29), 129, 182),
+        PINMUX_IRQ(EXT_IRQ16H(30), 130, 183),
+        PINMUX_IRQ(EXT_IRQ16H(31), 138, 184),
+};
+
+#define PORTnCR_PULMD_OFF       (0 << 6)
+#define PORTnCR_PULMD_DOWN      (2 << 6)
+#define PORTnCR_PULMD_UP        (3 << 6)
+#define PORTnCR_PULMD_MASK      (3 << 6)
+
+struct sh7372_portcr_group {
+        unsigned int end_pin;
+        unsigned int offset;
+};
+
+static const struct sh7372_portcr_group sh7372_portcr_offsets[] = {
+        { 45,  0x1000 }, { 75,  0x2000 }, { 99,  0x0000 }, { 120, 0x3000 },
+        { 151, 0x0000 }, { 155, 0x3000 }, { 166, 0x0000 }, { 190, 0x2000 },
+};
+
+static void __iomem *sh7372_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
+{
+        unsigned int i;
+
+        for (i = 0; i < ARRAY_SIZE(sh7372_portcr_offsets); ++i) {
+                const struct sh7372_portcr_group *group =
+                        &sh7372_portcr_offsets[i];
+
+                if (i <= group->end_pin)
+                        return pfc->window->virt + group->offset + pin;
+        }
+
+        return NULL;
+}
+
+static unsigned int sh7372_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
+{
+        void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
+        u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
+
+        switch (value) {
+        case PORTnCR_PULMD_UP:
+                return PIN_CONFIG_BIAS_PULL_UP;
+        case PORTnCR_PULMD_DOWN:
+                return PIN_CONFIG_BIAS_PULL_DOWN;
+        case PORTnCR_PULMD_OFF:
+        default:
+                return PIN_CONFIG_BIAS_DISABLE;
+        }
+}
+
+static void sh7372_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+                                   unsigned int bias)
+{
+        void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
+        u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
+
+        switch (bias) {
+        case PIN_CONFIG_BIAS_PULL_UP:
+                value |= PORTnCR_PULMD_UP;
+                break;
+        case PIN_CONFIG_BIAS_PULL_DOWN:
+                value |= PORTnCR_PULMD_DOWN;
+                break;
+        }
+
+        iowrite8(value, addr);
+}
+
+static const struct sh_pfc_soc_operations sh7372_pinmux_ops = {
+        .get_bias = sh7372_pinmux_get_bias,
+        .set_bias = sh7372_pinmux_set_bias,
 };
 
 const struct sh_pfc_soc_info sh7372_pinmux_info = {
         .name = "sh7372_pfc",
+        .ops = &sh7372_pinmux_ops,
+
         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
-        .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
@@ -1825,9 +2664,6 @@ const struct sh_pfc_soc_info sh7372_pinmux_info = {
         .functions = pinmux_functions,
         .nr_functions = ARRAY_SIZE(pinmux_functions),
 
-        .func_gpios = pinmux_func_gpios,
-        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 587f7772abf2..7956df58d751 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -20,9 +20,12 @@
  */
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/pinctrl/pinconf-generic.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/slab.h>
 
-#include <mach/sh73a0.h>
 #include <mach/irqs.h>
 
 #include "core.h"
@@ -2538,6 +2541,157 @@ static const unsigned int sdhi2_ctrl_pins[] = {
 static const unsigned int sdhi2_ctrl_mux[] = {
         SDHICMD2_MARK, SDHICLK2_MARK,
 };
+/* - TPU0 ------------------------------------------------------------------- */
+static const unsigned int tpu0_to0_pins[] = {
+        /* TO */
+        55,
+};
+static const unsigned int tpu0_to0_mux[] = {
+        TPU0TO0_MARK,
+};
+static const unsigned int tpu0_to1_pins[] = {
+        /* TO */
+        59,
+};
+static const unsigned int tpu0_to1_mux[] = {
+        TPU0TO1_MARK,
+};
+static const unsigned int tpu0_to2_pins[] = {
+        /* TO */
+        140,
+};
+static const unsigned int tpu0_to2_mux[] = {
+        TPU0TO2_MARK,
+};
+static const unsigned int tpu0_to3_pins[] = {
+        /* TO */
+        141,
+};
+static const unsigned int tpu0_to3_mux[] = {
+        TPU0TO3_MARK,
+};
+/* - TPU1 ------------------------------------------------------------------- */
+static const unsigned int tpu1_to0_pins[] = {
+        /* TO */
+        246,
+};
+static const unsigned int tpu1_to0_mux[] = {
+        TPU1TO0_MARK,
+};
+static const unsigned int tpu1_to1_0_pins[] = {
+        /* TO */
+        28,
+};
+static const unsigned int tpu1_to1_0_mux[] = {
+        PORT28_TPU1TO1_MARK,
+};
+static const unsigned int tpu1_to1_1_pins[] = {
+        /* TO */
+        29,
+};
+static const unsigned int tpu1_to1_1_mux[] = {
+        PORT29_TPU1TO1_MARK,
+};
+static const unsigned int tpu1_to2_pins[] = {
+        /* TO */
+        153,
+};
+static const unsigned int tpu1_to2_mux[] = {
+        TPU1TO2_MARK,
+};
+static const unsigned int tpu1_to3_pins[] = {
+        /* TO */
+        145,
+};
+static const unsigned int tpu1_to3_mux[] = {
+        TPU1TO3_MARK,
+};
+/* - TPU2 ------------------------------------------------------------------- */
+static const unsigned int tpu2_to0_pins[] = {
+        /* TO */
+        248,
+};
+static const unsigned int tpu2_to0_mux[] = {
+        TPU2TO0_MARK,
+};
+static const unsigned int tpu2_to1_pins[] = {
+        /* TO */
+        197,
+};
+static const unsigned int tpu2_to1_mux[] = {
+        TPU2TO1_MARK,
+};
+static const unsigned int tpu2_to2_pins[] = {
+        /* TO */
+        50,
+};
+static const unsigned int tpu2_to2_mux[] = {
+        TPU2TO2_MARK,
+};
+static const unsigned int tpu2_to3_pins[] = {
+        /* TO */
+        51,
+};
+static const unsigned int tpu2_to3_mux[] = {
+        TPU2TO3_MARK,
+};
+/* - TPU3 ------------------------------------------------------------------- */
+static const unsigned int tpu3_to0_pins[] = {
+        /* TO */
+        163,
+};
+static const unsigned int tpu3_to0_mux[] = {
+        TPU3TO0_MARK,
+};
+static const unsigned int tpu3_to1_pins[] = {
+        /* TO */
+        247,
+};
+static const unsigned int tpu3_to1_mux[] = {
+        TPU3TO1_MARK,
+};
+static const unsigned int tpu3_to2_pins[] = {
+        /* TO */
+        54,
+};
+static const unsigned int tpu3_to2_mux[] = {
+        TPU3TO2_MARK,
+};
+static const unsigned int tpu3_to3_pins[] = {
+        /* TO */
+        53,
+};
+static const unsigned int tpu3_to3_mux[] = {
+        TPU3TO3_MARK,
+};
+/* - TPU4 ------------------------------------------------------------------- */
+static const unsigned int tpu4_to0_pins[] = {
+        /* TO */
+        241,
+};
+static const unsigned int tpu4_to0_mux[] = {
+        TPU4TO0_MARK,
+};
+static const unsigned int tpu4_to1_pins[] = {
+        /* TO */
+        199,
+};
+static const unsigned int tpu4_to1_mux[] = {
+        TPU4TO1_MARK,
+};
+static const unsigned int tpu4_to2_pins[] = {
+        /* TO */
+        58,
+};
+static const unsigned int tpu4_to2_mux[] = {
+        TPU4TO2_MARK,
+};
+static const unsigned int tpu4_to3_pins[] = {
+        /* TO */
+};
+static const unsigned int tpu4_to3_mux[] = {
+        TPU4TO3_MARK,
+};
 /* - USB -------------------------------------------------------------------- */
 static const unsigned int usb_vbus_pins[] = {
         /* VBUS */
@@ -2689,6 +2843,27 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(sdhi2_data1),
         SH_PFC_PIN_GROUP(sdhi2_data4),
         SH_PFC_PIN_GROUP(sdhi2_ctrl),
+        SH_PFC_PIN_GROUP(tpu0_to0),
+        SH_PFC_PIN_GROUP(tpu0_to1),
+        SH_PFC_PIN_GROUP(tpu0_to2),
+        SH_PFC_PIN_GROUP(tpu0_to3),
+        SH_PFC_PIN_GROUP(tpu1_to0),
+        SH_PFC_PIN_GROUP(tpu1_to1_0),
+        SH_PFC_PIN_GROUP(tpu1_to1_1),
+        SH_PFC_PIN_GROUP(tpu1_to2),
+        SH_PFC_PIN_GROUP(tpu1_to3),
+        SH_PFC_PIN_GROUP(tpu2_to0),
+        SH_PFC_PIN_GROUP(tpu2_to1),
+        SH_PFC_PIN_GROUP(tpu2_to2),
+        SH_PFC_PIN_GROUP(tpu2_to3),
+        SH_PFC_PIN_GROUP(tpu3_to0),
+        SH_PFC_PIN_GROUP(tpu3_to1),
+        SH_PFC_PIN_GROUP(tpu3_to2),
+        SH_PFC_PIN_GROUP(tpu3_to3),
+        SH_PFC_PIN_GROUP(tpu4_to0),
+        SH_PFC_PIN_GROUP(tpu4_to1),
+        SH_PFC_PIN_GROUP(tpu4_to2),
+        SH_PFC_PIN_GROUP(tpu4_to3),
         SH_PFC_PIN_GROUP(usb_vbus),
 };
 
@@ -2908,6 +3083,42 @@ static const char * const usb_groups[] = {
         "usb_vbus",
 };
 
+static const char * const tpu0_groups[] = {
+        "tpu0_to0",
+        "tpu0_to1",
+        "tpu0_to2",
+        "tpu0_to3",
+};
+
+static const char * const tpu1_groups[] = {
+        "tpu1_to0",
+        "tpu1_to1_0",
+        "tpu1_to1_1",
+        "tpu1_to2",
+        "tpu1_to3",
+};
+
+static const char * const tpu2_groups[] = {
+        "tpu2_to0",
+        "tpu2_to1",
+        "tpu2_to2",
+        "tpu2_to3",
+};
+
+static const char * const tpu3_groups[] = {
+        "tpu3_to0",
+        "tpu3_to1",
+        "tpu3_to2",
+        "tpu3_to3",
+};
+
+static const char * const tpu4_groups[] = {
+        "tpu4_to0",
+        "tpu4_to1",
+        "tpu4_to2",
+        "tpu4_to3",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(bsc),
         SH_PFC_FUNCTION(fsia),
@@ -2933,400 +3144,14 @@ static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(sdhi0),
         SH_PFC_FUNCTION(sdhi1),
         SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(tpu0),
+        SH_PFC_FUNCTION(tpu1),
+        SH_PFC_FUNCTION(tpu2),
+        SH_PFC_FUNCTION(tpu3),
+        SH_PFC_FUNCTION(tpu4),
         SH_PFC_FUNCTION(usb),
 };
 
-#define PINMUX_FN_BASE  GPIO_FN_GPI0
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-        /* Table 25-1 (Functions 0-7) */
-        GPIO_FN(GPI0),
-        GPIO_FN(GPI1),
-        GPIO_FN(GPI2),
-        GPIO_FN(GPI3),
-        GPIO_FN(GPI4),
-        GPIO_FN(GPI5),
-        GPIO_FN(GPI6),
-        GPIO_FN(GPI7),
-        GPIO_FN(GPO7), \
-        GPIO_FN(MFG0_OUT2),
-        GPIO_FN(GPO6), \
-        GPIO_FN(MFG1_OUT2),
-        GPIO_FN(GPO5), \
-        GPIO_FN(PORT16_VIO_CKOR),
-        GPIO_FN(PORT19_VIO_CKO2),
-        GPIO_FN(GPO0),
-        GPIO_FN(GPO1),
-        GPIO_FN(GPO2), \
-        GPIO_FN(STATUS0),
-        GPIO_FN(GPO3), \
-        GPIO_FN(STATUS1),
-        GPIO_FN(GPO4), \
-        GPIO_FN(STATUS2),
-        GPIO_FN(VINT),
-        GPIO_FN(TCKON),
-        GPIO_FN(XDVFS1), \
-        GPIO_FN(MFG0_OUT1), \
-        GPIO_FN(PORT27_IROUT),
-        GPIO_FN(XDVFS2), \
-        GPIO_FN(PORT28_TPU1TO1),
-        GPIO_FN(SIM_RST), \
-        GPIO_FN(PORT29_TPU1TO1),
-        GPIO_FN(SIM_CLK), \
-        GPIO_FN(PORT30_VIO_CKOR),
-        GPIO_FN(SIM_D), \
-        GPIO_FN(PORT31_IROUT),
-        GPIO_FN(XWUP),
-        GPIO_FN(VACK),
-        GPIO_FN(XTAL1L),
-        GPIO_FN(PORT49_IROUT), \
-        GPIO_FN(BBIF2_TSYNC2), \
-        GPIO_FN(TPU2TO2), \
-
-        GPIO_FN(BBIF2_TSCK2), \
-        GPIO_FN(TPU2TO3), \
-        GPIO_FN(BBIF2_TXD2),
-        GPIO_FN(TPU3TO3), \
-        GPIO_FN(TPU3TO2), \
-        GPIO_FN(TPU0TO0),
-        GPIO_FN(A0), \
-        GPIO_FN(BS_),
-        GPIO_FN(A12), \
-        GPIO_FN(TPU4TO2),
-        GPIO_FN(A13), \
-        GPIO_FN(TPU0TO1),
-        GPIO_FN(A14), \
-        GPIO_FN(A15), \
-        GPIO_FN(A16), \
-        GPIO_FN(MSIOF0_SS1),
-        GPIO_FN(A17), \
-        GPIO_FN(MSIOF0_TSYNC),
-        GPIO_FN(A18), \
-        GPIO_FN(MSIOF0_TSCK),
-        GPIO_FN(A19), \
-        GPIO_FN(MSIOF0_TXD),
-        GPIO_FN(A20), \
-        GPIO_FN(MSIOF0_RSCK),
-        GPIO_FN(A21), \
-        GPIO_FN(MSIOF0_RSYNC),
-        GPIO_FN(A22), \
-        GPIO_FN(MSIOF0_MCK0),
-        GPIO_FN(A23), \
-        GPIO_FN(MSIOF0_MCK1),
-        GPIO_FN(A24), \
-        GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(A25), \
-        GPIO_FN(MSIOF0_SS2),
-        GPIO_FN(A26), \
-        GPIO_FN(FCE1_),
-        GPIO_FN(DACK0),
-        GPIO_FN(FCE0_), \
-        GPIO_FN(WAIT_), \
-        GPIO_FN(DREQ0),
-        GPIO_FN(FRB),
-        GPIO_FN(CKO),
-        GPIO_FN(NBRSTOUT_),
-        GPIO_FN(NBRST_),
-        GPIO_FN(BBIF2_TXD),
-        GPIO_FN(BBIF2_RXD),
-        GPIO_FN(BBIF2_SYNC),
-        GPIO_FN(BBIF2_SCK),
-        GPIO_FN(MFG3_IN2),
-        GPIO_FN(MFG3_IN1),
-        GPIO_FN(BBIF1_SS2), \
-        GPIO_FN(MFG3_OUT1),
-        GPIO_FN(HSI_RX_DATA), \
-        GPIO_FN(BBIF1_RXD),
-        GPIO_FN(HSI_TX_WAKE), \
-        GPIO_FN(BBIF1_TSCK),
-        GPIO_FN(HSI_TX_DATA), \
-        GPIO_FN(BBIF1_TSYNC),
-        GPIO_FN(HSI_TX_READY), \
-        GPIO_FN(BBIF1_TXD),
-        GPIO_FN(HSI_RX_READY), \
-        GPIO_FN(BBIF1_RSCK), \
-        GPIO_FN(HSI_RX_WAKE), \
-        GPIO_FN(BBIF1_RSYNC), \
-        GPIO_FN(HSI_RX_FLAG), \
-        GPIO_FN(BBIF1_SS1), \
-        GPIO_FN(BBIF1_FLOW),
-        GPIO_FN(HSI_TX_FLAG),
-        GPIO_FN(VIO_VD), \
-        GPIO_FN(VIO2_VD), \
-
-        GPIO_FN(VIO_HD), \
-        GPIO_FN(VIO2_HD), \
-        GPIO_FN(VIO_D0), \
-        GPIO_FN(PORT130_MSIOF2_RXD), \
-        GPIO_FN(VIO_D1), \
-        GPIO_FN(PORT131_MSIOF2_SS1), \
-        GPIO_FN(VIO_D2), \
-        GPIO_FN(PORT132_MSIOF2_SS2), \
-        GPIO_FN(VIO_D3), \
-        GPIO_FN(MSIOF2_TSYNC), \
-        GPIO_FN(VIO_D4), \
-        GPIO_FN(MSIOF2_TXD), \
-        GPIO_FN(VIO_D5), \
-        GPIO_FN(MSIOF2_TSCK), \
-        GPIO_FN(VIO_D6), \
-        GPIO_FN(VIO_D7), \
-        GPIO_FN(VIO_D8), \
-        GPIO_FN(VIO2_D0), \
-        GPIO_FN(VIO_D9), \
-        GPIO_FN(VIO2_D1), \
-        GPIO_FN(VIO_D10), \
-        GPIO_FN(TPU0TO2), \
-        GPIO_FN(VIO2_D2), \
-        GPIO_FN(VIO_D11), \
-        GPIO_FN(TPU0TO3), \
-        GPIO_FN(VIO2_D3), \
-        GPIO_FN(VIO_D12), \
-        GPIO_FN(VIO2_D4), \
-        GPIO_FN(VIO_D13), \
-        GPIO_FN(VIO2_D5), \
-        GPIO_FN(VIO_D14), \
-        GPIO_FN(VIO2_D6), \
-        GPIO_FN(VIO_D15), \
-        GPIO_FN(TPU1TO3), \
-        GPIO_FN(VIO2_D7), \
-        GPIO_FN(VIO_CLK), \
-        GPIO_FN(VIO2_CLK), \
-        GPIO_FN(VIO_FIELD), \
-        GPIO_FN(VIO2_FIELD), \
-        GPIO_FN(VIO_CKO),
-        GPIO_FN(A27), \
-        GPIO_FN(MFG0_IN1), \
-        GPIO_FN(MFG0_IN2),
-        GPIO_FN(TS_SPSYNC3), \
-        GPIO_FN(MSIOF2_RSCK),
-        GPIO_FN(TS_SDAT3), \
-        GPIO_FN(MSIOF2_RSYNC),
-        GPIO_FN(TPU1TO2), \
-        GPIO_FN(TS_SDEN3), \
-        GPIO_FN(PORT153_MSIOF2_SS1),
-        GPIO_FN(MSIOF2_MCK0),
-        GPIO_FN(MSIOF2_MCK1),
-        GPIO_FN(PORT156_MSIOF2_SS2),
-        GPIO_FN(PORT157_MSIOF2_RXD),
-        GPIO_FN(DINT_), \
-        GPIO_FN(TS_SCK3),
-        GPIO_FN(NMI),
-        GPIO_FN(TPU3TO0),
-        GPIO_FN(BBIF2_TSYNC1),
-        GPIO_FN(BBIF2_TSCK1),
-        GPIO_FN(BBIF2_TXD1),
-        GPIO_FN(MFG2_OUT2), \
-        GPIO_FN(TPU2TO1),
-        GPIO_FN(TPU4TO1), \
-        GPIO_FN(MFG4_OUT2),
-        GPIO_FN(D16),
-        GPIO_FN(D17),
-        GPIO_FN(D18),
-        GPIO_FN(D19),
-        GPIO_FN(D20),
-        GPIO_FN(D21),
-        GPIO_FN(D22),
-        GPIO_FN(PORT207_MSIOF0L_SS1), \
-        GPIO_FN(D23),
-        GPIO_FN(PORT208_MSIOF0L_SS2), \
-        GPIO_FN(D24),
-        GPIO_FN(D25),
-        GPIO_FN(DREQ2), \
-        GPIO_FN(PORT210_MSIOF0L_SS1), \
-        GPIO_FN(D26),
-        GPIO_FN(PORT211_MSIOF0L_SS2), \
-        GPIO_FN(D27),
-        GPIO_FN(TS_SPSYNC1), \
-        GPIO_FN(MSIOF0L_MCK0), \
-        GPIO_FN(D28),
-        GPIO_FN(TS_SDAT1), \
-        GPIO_FN(MSIOF0L_MCK1), \
-        GPIO_FN(D29),
-        GPIO_FN(TS_SDEN1), \
-        GPIO_FN(MSIOF0L_RSCK), \
-        GPIO_FN(D30),
-        GPIO_FN(TS_SCK1), \
-        GPIO_FN(MSIOF0L_RSYNC), \
-        GPIO_FN(D31),
-        GPIO_FN(DACK2), \
-        GPIO_FN(MSIOF0L_TSYNC), \
-        GPIO_FN(VIO2_FIELD3), \
-        GPIO_FN(DACK3), \
-        GPIO_FN(PORT218_VIO_CKOR),
-        GPIO_FN(DREQ3), \
-        GPIO_FN(MSIOF0L_TSCK), \
-        GPIO_FN(VIO2_CLK3), \
-        GPIO_FN(DREQ1), \
-        GPIO_FN(PWEN), \
-        GPIO_FN(MSIOF0L_RXD), \
-        GPIO_FN(VIO2_HD3), \
-        GPIO_FN(DACK1), \
-        GPIO_FN(OVCN), \
-        GPIO_FN(MSIOF0L_TXD), \
-        GPIO_FN(VIO2_VD3), \
-
-        GPIO_FN(OVCN2),
-        GPIO_FN(EXTLP), \
-        GPIO_FN(PORT226_VIO_CKO2),
-        GPIO_FN(IDIN),
-        GPIO_FN(MFG1_IN1),
-        GPIO_FN(MSIOF1_TXD), \
-        GPIO_FN(MSIOF1_TSYNC), \
-        GPIO_FN(MSIOF1_TSCK), \
-        GPIO_FN(MSIOF1_RXD), \
-        GPIO_FN(MSIOF1_RSCK), \
-        GPIO_FN(VIO2_CLK2), \
-        GPIO_FN(MSIOF1_RSYNC), \
-        GPIO_FN(MFG1_IN2), \
-        GPIO_FN(VIO2_VD2), \
-        GPIO_FN(MSIOF1_MCK0), \
-        GPIO_FN(MSIOF1_MCK1), \
-        GPIO_FN(MSIOF1_SS1), \
-        GPIO_FN(VIO2_FIELD2), \
-        GPIO_FN(MSIOF1_SS2), \
-        GPIO_FN(VIO2_HD2), \
-        GPIO_FN(PORT241_IROUT), \
-        GPIO_FN(MFG4_OUT1), \
-        GPIO_FN(TPU4TO0),
-        GPIO_FN(MFG4_IN2),
-        GPIO_FN(PORT243_VIO_CKO2),
-        GPIO_FN(MFG2_IN1), \
-        GPIO_FN(MSIOF2R_RXD),
-        GPIO_FN(MFG2_IN2), \
-        GPIO_FN(MSIOF2R_TXD),
-        GPIO_FN(MFG1_OUT1), \
-        GPIO_FN(TPU1TO0),
-        GPIO_FN(MFG3_OUT2), \
-        GPIO_FN(TPU3TO1),
-        GPIO_FN(MFG2_OUT1), \
-        GPIO_FN(TPU2TO0), \
-        GPIO_FN(MSIOF2R_TSCK),
-        GPIO_FN(PORT249_IROUT), \
-        GPIO_FN(MFG4_IN1), \
-        GPIO_FN(MSIOF2R_TSYNC),
-        GPIO_FN(SDHICLK0),
-        GPIO_FN(SDHICD0),
-        GPIO_FN(SDHID0_0),
-        GPIO_FN(SDHID0_1),
-        GPIO_FN(SDHID0_2),
-        GPIO_FN(SDHID0_3),
-        GPIO_FN(SDHICMD0),
-        GPIO_FN(SDHIWP0),
-        GPIO_FN(SDHICLK1),
-        GPIO_FN(SDHID1_0), \
-        GPIO_FN(TS_SPSYNC2),
-        GPIO_FN(SDHID1_1), \
-        GPIO_FN(TS_SDAT2),
-        GPIO_FN(SDHID1_2), \
-        GPIO_FN(TS_SDEN2),
-        GPIO_FN(SDHID1_3), \
-        GPIO_FN(TS_SCK2),
-        GPIO_FN(SDHICMD1),
-        GPIO_FN(SDHICLK2),
-        GPIO_FN(SDHID2_0), \
-        GPIO_FN(TS_SPSYNC4),
-        GPIO_FN(SDHID2_1), \
-        GPIO_FN(TS_SDAT4),
-        GPIO_FN(SDHID2_2), \
-        GPIO_FN(TS_SDEN4),
-        GPIO_FN(SDHID2_3), \
-        GPIO_FN(TS_SCK4),
-        GPIO_FN(SDHICMD2),
-        GPIO_FN(MMCCLK0),
-        GPIO_FN(MMCD0_0),
-        GPIO_FN(MMCD0_1),
-        GPIO_FN(MMCD0_2),
-        GPIO_FN(MMCD0_3),
-        GPIO_FN(MMCD0_4), \
-        GPIO_FN(TS_SPSYNC5),
-        GPIO_FN(MMCD0_5), \
-        GPIO_FN(TS_SDAT5),
-        GPIO_FN(MMCD0_6), \
-        GPIO_FN(TS_SDEN5),
-        GPIO_FN(MMCD0_7), \
-        GPIO_FN(TS_SCK5),
-        GPIO_FN(MMCCMD0),
-        GPIO_FN(RESETOUTS_), \
-        GPIO_FN(EXTAL2OUT),
-        GPIO_FN(MCP_WAIT__MCP_FRB),
-        GPIO_FN(MCP_CKO), \
-        GPIO_FN(MMCCLK1),
-        GPIO_FN(MCP_D15_MCP_NAF15),
-        GPIO_FN(MCP_D14_MCP_NAF14),
-        GPIO_FN(MCP_D13_MCP_NAF13),
-        GPIO_FN(MCP_D12_MCP_NAF12),
-        GPIO_FN(MCP_D11_MCP_NAF11),
-        GPIO_FN(MCP_D10_MCP_NAF10),
-        GPIO_FN(MCP_D9_MCP_NAF9),
-        GPIO_FN(MCP_D8_MCP_NAF8), \
-        GPIO_FN(MMCCMD1),
-        GPIO_FN(MCP_D7_MCP_NAF7), \
-        GPIO_FN(MMCD1_7),
-
-        GPIO_FN(MCP_D6_MCP_NAF6), \
-        GPIO_FN(MMCD1_6),
-        GPIO_FN(MCP_D5_MCP_NAF5), \
-        GPIO_FN(MMCD1_5),
-        GPIO_FN(MCP_D4_MCP_NAF4), \
-        GPIO_FN(MMCD1_4),
-        GPIO_FN(MCP_D3_MCP_NAF3), \
-        GPIO_FN(MMCD1_3),
-        GPIO_FN(MCP_D2_MCP_NAF2), \
-        GPIO_FN(MMCD1_2),
-        GPIO_FN(MCP_D1_MCP_NAF1), \
-        GPIO_FN(MMCD1_1),
-        GPIO_FN(MCP_D0_MCP_NAF0), \
-        GPIO_FN(MMCD1_0),
-        GPIO_FN(MCP_NBRSTOUT_),
-        GPIO_FN(MCP_WE0__MCP_FWE), \
-        GPIO_FN(MCP_RDWR_MCP_FWE),
-
-        /* MSEL2 special cases */
-        GPIO_FN(TSIF2_TS_XX1),
-        GPIO_FN(TSIF2_TS_XX2),
-        GPIO_FN(TSIF2_TS_XX3),
-        GPIO_FN(TSIF2_TS_XX4),
-        GPIO_FN(TSIF2_TS_XX5),
-        GPIO_FN(TSIF1_TS_XX1),
-        GPIO_FN(TSIF1_TS_XX2),
-        GPIO_FN(TSIF1_TS_XX3),
-        GPIO_FN(TSIF1_TS_XX4),
-        GPIO_FN(TSIF1_TS_XX5),
-        GPIO_FN(TSIF0_TS_XX1),
-        GPIO_FN(TSIF0_TS_XX2),
-        GPIO_FN(TSIF0_TS_XX3),
-        GPIO_FN(TSIF0_TS_XX4),
-        GPIO_FN(TSIF0_TS_XX5),
-        GPIO_FN(MST1_TS_XX1),
-        GPIO_FN(MST1_TS_XX2),
-        GPIO_FN(MST1_TS_XX3),
-        GPIO_FN(MST1_TS_XX4),
-        GPIO_FN(MST1_TS_XX5),
-        GPIO_FN(MST0_TS_XX1),
-        GPIO_FN(MST0_TS_XX2),
-        GPIO_FN(MST0_TS_XX3),
-        GPIO_FN(MST0_TS_XX4),
-        GPIO_FN(MST0_TS_XX5),
-
-        /* MSEL3 special cases */
-        GPIO_FN(SDHI0_VCCQ_MC0_ON),
-        GPIO_FN(SDHI0_VCCQ_MC0_OFF),
-        GPIO_FN(DEBUG_MON_VIO),
-        GPIO_FN(DEBUG_MON_LCDD),
-        GPIO_FN(LCDC_LCDC0),
-        GPIO_FN(LCDC_LCDC1),
-
-        /* MSEL4 special cases */
-        GPIO_FN(IRQ9_MEM_INT),
-        GPIO_FN(IRQ9_MCP_INT),
-        GPIO_FN(A11),
-        GPIO_FN(TPU4TO3),
-        GPIO_FN(RESETA_N_PU_ON),
-        GPIO_FN(RESETA_N_PU_OFF),
-        GPIO_FN(EDBGREQ_PD),
-        GPIO_FN(EDBGREQ_PU),
-};
-
 #undef PORTCR
 #define PORTCR(nr, reg)                                                 \
         {                                                               \
@@ -3888,6 +3713,92 @@ static const struct pinmux_irq pinmux_irqs[] = {
         PINMUX_IRQ(EXT_IRQ16L(9), 308),
 };
 
+/* -----------------------------------------------------------------------------
+ * VCCQ MC0 regulator
+ */
+
+static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
+{
+        struct sh_pfc *pfc = reg->reg_data;
+        void __iomem *addr = pfc->window[1].virt + 4;
+        unsigned long flags;
+        u32 value;
+
+        spin_lock_irqsave(&pfc->lock, flags);
+
+        value = ioread32(addr);
+
+        if (enable)
+                value |= BIT(28);
+        else
+                value &= ~BIT(28);
+
+        iowrite32(value, addr);
+
+        spin_unlock_irqrestore(&pfc->lock, flags);
+}
+
+static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg)
+{
+        sh73a0_vccq_mc0_endisable(reg, true);
+        return 0;
+}
+
+static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
+{
+        sh73a0_vccq_mc0_endisable(reg, false);
+        return 0;
+}
+
+static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
+{
+        struct sh_pfc *pfc = reg->reg_data;
+        void __iomem *addr = pfc->window[1].virt + 4;
+        unsigned long flags;
+        u32 value;
+
+        spin_lock_irqsave(&pfc->lock, flags);
+        value = ioread32(addr);
+        spin_unlock_irqrestore(&pfc->lock, flags);
+
+        return !!(value & BIT(28));
+}
+
+static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg)
+{
+        return 3300000;
+}
+
+static struct regulator_ops sh73a0_vccq_mc0_ops = {
+        .enable = sh73a0_vccq_mc0_enable,
+        .disable = sh73a0_vccq_mc0_disable,
+        .is_enabled = sh73a0_vccq_mc0_is_enabled,
+        .get_voltage = sh73a0_vccq_mc0_get_voltage,
+};
+
+static const struct regulator_desc sh73a0_vccq_mc0_desc = {
+        .owner = THIS_MODULE,
+        .name = "vccq_mc0",
+        .type = REGULATOR_VOLTAGE,
+        .ops = &sh73a0_vccq_mc0_ops,
+};
+
+static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = {
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+};
+
+static const struct regulator_init_data sh73a0_vccq_mc0_init_data = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers),
+        .consumer_supplies = sh73a0_vccq_mc0_consumers,
+};
+
+/* -----------------------------------------------------------------------------
+ * Pin bias
+ */
+
 #define PORTnCR_PULMD_OFF       (0 << 6)
 #define PORTnCR_PULMD_DOWN      (2 << 6)
 #define PORTnCR_PULMD_UP        (3 << 6)
@@ -3934,7 +3845,51 @@ static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
         iowrite8(value, addr);
 }
 
+/* -----------------------------------------------------------------------------
+ * SoC information
+ */
+
+struct sh73a0_pinmux_data {
+        struct regulator_dev *vccq_mc0;
+};
+
+static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
+{
+        struct sh73a0_pinmux_data *data;
+        struct regulator_config cfg = { };
+        int ret;
+
+        data = devm_kzalloc(pfc->dev, sizeof(*data), GFP_KERNEL);
+        if (data == NULL)
+                return -ENOMEM;
+
+        cfg.dev = pfc->dev;
+        cfg.init_data = &sh73a0_vccq_mc0_init_data;
+        cfg.driver_data = pfc;
+
+        data->vccq_mc0 = regulator_register(&sh73a0_vccq_mc0_desc, &cfg);
+        if (IS_ERR(data->vccq_mc0)) {
+                ret = PTR_ERR(data->vccq_mc0);
+                dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
+                        ret);
+                return ret;
+        }
+
+        pfc->soc_data = data;
+
+        return 0;
+}
+
+static void sh73a0_pinmux_soc_exit(struct sh_pfc *pfc)
+{
+        struct sh73a0_pinmux_data *data = pfc->soc_data;
+
+        regulator_unregister(data->vccq_mc0);
+}
+
 static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
+        .init = sh73a0_pinmux_soc_init,
+        .exit = sh73a0_pinmux_soc_exit,
         .get_bias = sh73a0_pinmux_get_bias,
         .set_bias = sh73a0_pinmux_set_bias,
 };
@@ -3956,9 +3911,6 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = {
         .functions = pinmux_functions,
         .nr_functions = ARRAY_SIZE(pinmux_functions),
 
-        .func_gpios = pinmux_func_gpios,
-        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 3b785fc428d5..830ae1ffd0b5 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -11,8 +11,8 @@
 #ifndef __SH_PFC_H
 #define __SH_PFC_H
 
+#include <linux/bug.h>
 #include <linux/stringify.h>
-#include <asm-generic/gpio.h>
 
 typedef unsigned short pinmux_enum_t;
 
@@ -129,6 +129,8 @@ struct pinmux_range {
 struct sh_pfc;
 
 struct sh_pfc_soc_operations {
+        int (*init)(struct sh_pfc *pfc);
+        void (*exit)(struct sh_pfc *pfc);
         unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
         void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
                          unsigned int bias);
diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c
index ab63104e8dc9..70d986e04afb 100644
--- a/drivers/pinctrl/vt8500/pinctrl-wmt.c
+++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c
@@ -609,8 +609,7 @@ int wmt_pinctrl_probe(struct platform_device *pdev,
         return 0;
 
 fail_range:
-        err = gpiochip_remove(&data->gpio_chip);
-        if (err)
+        if (gpiochip_remove(&data->gpio_chip))
                 dev_err(&pdev->dev, "failed to remove gpio chip\n");
 fail_gpio:
         pinctrl_unregister(data->pctl_dev);
diff --git a/drivers/platform/x86/hp-wmi.c b/drivers/platform/x86/hp-wmi.c
index 8df0c5a21be2..d111c8687f9b 100644
--- a/drivers/platform/x86/hp-wmi.c
+++ b/drivers/platform/x86/hp-wmi.c
@@ -703,7 +703,7 @@ static int hp_wmi_rfkill_setup(struct platform_device *device)
                 }
                 rfkill_init_sw_state(gps_rfkill,
                                      hp_wmi_get_sw_state(HPWMI_GPS));
-                rfkill_set_hw_state(bluetooth_rfkill,
+                rfkill_set_hw_state(gps_rfkill,
                                     hp_wmi_get_hw_state(HPWMI_GPS));
                 err = rfkill_register(gps_rfkill);
                 if (err)
diff --git a/drivers/ptp/ptp_pch.c b/drivers/ptp/ptp_pch.c
index bea94510ad2d..71a2559278d7 100644
--- a/drivers/ptp/ptp_pch.c
+++ b/drivers/ptp/ptp_pch.c
@@ -628,9 +628,10 @@ pch_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 
         chip->caps = ptp_pch_caps;
         chip->ptp_clock = ptp_clock_register(&chip->caps, &pdev->dev);
-
-        if (IS_ERR(chip->ptp_clock))
-                return PTR_ERR(chip->ptp_clock);
+        if (IS_ERR(chip->ptp_clock)) {
+                ret = PTR_ERR(chip->ptp_clock);
+                goto err_ptp_clock_reg;
+        }
 
         spin_lock_init(&chip->register_lock);
 
@@ -669,6 +670,7 @@ pch_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 
 err_req_irq:
         ptp_clock_unregister(chip->ptp_clock);
+err_ptp_clock_reg:
         iounmap(chip->regs);
         chip->regs = NULL;
 
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index 6e5017841582..815d6df8bd5f 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -1539,7 +1539,10 @@ static void regulator_ena_gpio_free(struct regulator_dev *rdev)
 }
 
 /**
- * Balance enable_count of each GPIO and actual GPIO pin control.
+ * regulator_ena_gpio_ctrl - balance enable_count of each GPIO and actual GPIO pin control
+ * @rdev: regulator_dev structure
+ * @enable: enable GPIO at initial use?
+ *
  * GPIO is enabled in case of initial use. (enable_count is 0)
  * GPIO is disabled when it is not shared any more. (enable_count <= 1)
  */
@@ -2702,7 +2705,7 @@ EXPORT_SYMBOL_GPL(regulator_get_voltage);
 /**
  * regulator_set_current_limit - set regulator output current limit
  * @regulator: regulator source
- * @min_uA: Minimuum supported current in uA
+ * @min_uA: Minimum supported current in uA
  * @max_uA: Maximum supported current in uA
  *
  * Sets current sink to the desired output current. This can be set during
diff --git a/drivers/regulator/dbx500-prcmu.c b/drivers/regulator/dbx500-prcmu.c
index 89bd2faaef8c..ce89f7848a57 100644
--- a/drivers/regulator/dbx500-prcmu.c
+++ b/drivers/regulator/dbx500-prcmu.c
@@ -24,18 +24,6 @@
 static int power_state_active_cnt; /* will initialize to zero */
 static DEFINE_SPINLOCK(power_state_active_lock);
 
-int power_state_active_get(void)
-{
-        unsigned long flags;
-        int cnt;
-
-        spin_lock_irqsave(&power_state_active_lock, flags);
-        cnt = power_state_active_cnt;
-        spin_unlock_irqrestore(&power_state_active_lock, flags);
-
-        return cnt;
-}
-
 void power_state_active_enable(void)
 {
         unsigned long flags;
@@ -65,6 +53,18 @@ out:
 
 #ifdef CONFIG_REGULATOR_DEBUG
 
+static int power_state_active_get(void)
+{
+        unsigned long flags;
+        int cnt;
+
+        spin_lock_irqsave(&power_state_active_lock, flags);
+        cnt = power_state_active_cnt;
+        spin_unlock_irqrestore(&power_state_active_lock, flags);
+
+        return cnt;
+}
+
 static struct ux500_regulator_debug {
         struct dentry *dir;
         struct dentry *status_file;
diff --git a/drivers/regulator/palmas-regulator.c b/drivers/regulator/palmas-regulator.c
index 92ceed0fc65e..3ae44ac12a94 100644
--- a/drivers/regulator/palmas-regulator.c
+++ b/drivers/regulator/palmas-regulator.c
@@ -840,7 +840,7 @@ static int palmas_regulators_probe(struct platform_device *pdev)
                         break;
                 }
 
-                if ((id == PALMAS_REG_SMPS6) && (id == PALMAS_REG_SMPS8))
+                if ((id == PALMAS_REG_SMPS6) || (id == PALMAS_REG_SMPS8))
                         ramp_delay_support = true;
 
                 if (ramp_delay_support) {
@@ -878,7 +878,7 @@ static int palmas_regulators_probe(struct platform_device *pdev)
                         pmic->desc[id].vsel_mask = SMPS10_VSEL;
                         pmic->desc[id].enable_reg =
                                         PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
-                                                        PALMAS_SMPS10_STATUS);
+                                                        PALMAS_SMPS10_CTRL);
                         pmic->desc[id].enable_mask = SMPS10_BOOST_EN;
                         pmic->desc[id].min_uV = 3750000;
                         pmic->desc[id].uV_step = 1250000;
diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c
index 0eab77b22340..f296f3f7db9b 100644
--- a/drivers/rtc/rtc-at91rm9200.c
+++ b/drivers/rtc/rtc-at91rm9200.c
@@ -25,6 +25,7 @@
 #include <linux/rtc.h>
 #include <linux/bcd.h>
 #include <linux/interrupt.h>
+#include <linux/spinlock.h>
 #include <linux/ioctl.h>
 #include <linux/completion.h>
 #include <linux/io.h>
@@ -42,10 +43,65 @@
 
 #define AT91_RTC_EPOCH          1900UL  /* just like arch/arm/common/rtctime.c */
 
+struct at91_rtc_config {
+        bool use_shadow_imr;
+};
+
+static const struct at91_rtc_config *at91_rtc_config;
 static DECLARE_COMPLETION(at91_rtc_updated);
 static unsigned int at91_alarm_year = AT91_RTC_EPOCH;
 static void __iomem *at91_rtc_regs;
 static int irq;
+static DEFINE_SPINLOCK(at91_rtc_lock);
+static u32 at91_rtc_shadow_imr;
+
+static void at91_rtc_write_ier(u32 mask)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&at91_rtc_lock, flags);
+        at91_rtc_shadow_imr |= mask;
+        at91_rtc_write(AT91_RTC_IER, mask);
+        spin_unlock_irqrestore(&at91_rtc_lock, flags);
+}
+
+static void at91_rtc_write_idr(u32 mask)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&at91_rtc_lock, flags);
+        at91_rtc_write(AT91_RTC_IDR, mask);
+        /*
+         * Register read back (of any RTC-register) needed to make sure
+         * IDR-register write has reached the peripheral before updating
+         * shadow mask.
+         *
+         * Note that there is still a possibility that the mask is updated
+         * before interrupts have actually been disabled in hardware. The only
+         * way to be certain would be to poll the IMR-register, which is is
+         * the very register we are trying to emulate. The register read back
+         * is a reasonable heuristic.
+         */
+        at91_rtc_read(AT91_RTC_SR);
+        at91_rtc_shadow_imr &= ~mask;
+        spin_unlock_irqrestore(&at91_rtc_lock, flags);
+}
+
+static u32 at91_rtc_read_imr(void)
+{
+        unsigned long flags;
+        u32 mask;
+
+        if (at91_rtc_config->use_shadow_imr) {
+                spin_lock_irqsave(&at91_rtc_lock, flags);
+                mask = at91_rtc_shadow_imr;
+                spin_unlock_irqrestore(&at91_rtc_lock, flags);
+        } else {
+                mask = at91_rtc_read(AT91_RTC_IMR);
+        }
+
+        return mask;
+}
 
 /*
  * Decode time/date into rtc_time structure
@@ -110,9 +166,9 @@ static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
         cr = at91_rtc_read(AT91_RTC_CR);
         at91_rtc_write(AT91_RTC_CR, cr | AT91_RTC_UPDCAL | AT91_RTC_UPDTIM);
 
-        at91_rtc_write(AT91_RTC_IER, AT91_RTC_ACKUPD);
+        at91_rtc_write_ier(AT91_RTC_ACKUPD);
         wait_for_completion(&at91_rtc_updated); /* wait for ACKUPD interrupt */
-        at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD);
+        at91_rtc_write_idr(AT91_RTC_ACKUPD);
 
         at91_rtc_write(AT91_RTC_TIMR,
                           bin2bcd(tm->tm_sec) << 0
@@ -144,7 +200,7 @@ static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
         tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
         tm->tm_year = at91_alarm_year - 1900;
 
-        alrm->enabled = (at91_rtc_read(AT91_RTC_IMR) & AT91_RTC_ALARM)
+        alrm->enabled = (at91_rtc_read_imr() & AT91_RTC_ALARM)
                         ? 1 : 0;
 
         dev_dbg(dev, "%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __func__,
@@ -169,7 +225,7 @@ static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
         tm.tm_min = alrm->time.tm_min;
         tm.tm_sec = alrm->time.tm_sec;
 
-        at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ALARM);
+        at91_rtc_write_idr(AT91_RTC_ALARM);
         at91_rtc_write(AT91_RTC_TIMALR,
                   bin2bcd(tm.tm_sec) << 0
                 | bin2bcd(tm.tm_min) << 8
@@ -182,7 +238,7 @@ static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
 
         if (alrm->enabled) {
                 at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
-                at91_rtc_write(AT91_RTC_IER, AT91_RTC_ALARM);
+                at91_rtc_write_ier(AT91_RTC_ALARM);
         }
 
         dev_dbg(dev, "%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __func__,
@@ -198,9 +254,9 @@ static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 
         if (enabled) {
                 at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
-                at91_rtc_write(AT91_RTC_IER, AT91_RTC_ALARM);
+                at91_rtc_write_ier(AT91_RTC_ALARM);
         } else
-                at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ALARM);
+                at91_rtc_write_idr(AT91_RTC_ALARM);
 
         return 0;
 }
@@ -209,7 +265,7 @@ static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  */
 static int at91_rtc_proc(struct device *dev, struct seq_file *seq)
 {
-        unsigned long imr = at91_rtc_read(AT91_RTC_IMR);
+        unsigned long imr = at91_rtc_read_imr();
 
         seq_printf(seq, "update_IRQ\t: %s\n",
                         (imr & AT91_RTC_ACKUPD) ? "yes" : "no");
@@ -229,7 +285,7 @@ static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
         unsigned int rtsr;
         unsigned long events = 0;
 
-        rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read(AT91_RTC_IMR);
+        rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read_imr();
         if (rtsr) {             /* this interrupt is shared!  Is it ours? */
                 if (rtsr & AT91_RTC_ALARM)
                         events |= (RTC_AF | RTC_IRQF);
@@ -250,6 +306,43 @@ static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
         return IRQ_NONE;                /* not handled */
 }
 
+static const struct at91_rtc_config at91rm9200_config = {
+};
+
+static const struct at91_rtc_config at91sam9x5_config = {
+        .use_shadow_imr = true,
+};
+
+#ifdef CONFIG_OF
+static const struct of_device_id at91_rtc_dt_ids[] = {
+        {
+                .compatible = "atmel,at91rm9200-rtc",
+                .data = &at91rm9200_config,
+        }, {
+                .compatible = "atmel,at91sam9x5-rtc",
+                .data = &at91sam9x5_config,
+        }, {
+                /* sentinel */
+        }
+};
+MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
+#endif
+
+static const struct at91_rtc_config *
+at91_rtc_get_config(struct platform_device *pdev)
+{
+        const struct of_device_id *match;
+
+        if (pdev->dev.of_node) {
+                match = of_match_node(at91_rtc_dt_ids, pdev->dev.of_node);
+                if (!match)
+                        return NULL;
+                return (const struct at91_rtc_config *)match->data;
+        }
+
+        return &at91rm9200_config;
+}
+
 static const struct rtc_class_ops at91_rtc_ops = {
         .read_time      = at91_rtc_readtime,
         .set_time       = at91_rtc_settime,
@@ -268,6 +361,10 @@ static int __init at91_rtc_probe(struct platform_device *pdev)
         struct resource *regs;
         int ret = 0;
 
+        at91_rtc_config = at91_rtc_get_config(pdev);
+        if (!at91_rtc_config)
+                return -ENODEV;
+
         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         if (!regs) {
                 dev_err(&pdev->dev, "no mmio resource defined\n");
@@ -290,7 +387,7 @@ static int __init at91_rtc_probe(struct platform_device *pdev)
         at91_rtc_write(AT91_RTC_MR, 0);         /* 24 hour mode */
 
         /* Disable all interrupts */
-        at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
+        at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM |
                                         AT91_RTC_SECEV | AT91_RTC_TIMEV |
                                         AT91_RTC_CALEV);
 
@@ -335,7 +432,7 @@ static int __exit at91_rtc_remove(struct platform_device *pdev)
         struct rtc_device *rtc = platform_get_drvdata(pdev);
 
         /* Disable all interrupts */
-        at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
+        at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM |
                                         AT91_RTC_SECEV | AT91_RTC_TIMEV |
                                         AT91_RTC_CALEV);
         free_irq(irq, pdev);
@@ -358,13 +455,13 @@ static int at91_rtc_suspend(struct device *dev)
         /* this IRQ is shared with DBGU and other hardware which isn't
          * necessarily doing PM like we are...
          */
-        at91_rtc_imr = at91_rtc_read(AT91_RTC_IMR)
+        at91_rtc_imr = at91_rtc_read_imr()
                         & (AT91_RTC_ALARM|AT91_RTC_SECEV);
         if (at91_rtc_imr) {
                 if (device_may_wakeup(dev))
                         enable_irq_wake(irq);
                 else
-                        at91_rtc_write(AT91_RTC_IDR, at91_rtc_imr);
+                        at91_rtc_write_idr(at91_rtc_imr);
         }
         return 0;
 }
@@ -375,7 +472,7 @@ static int at91_rtc_resume(struct device *dev)
                 if (device_may_wakeup(dev))
                         disable_irq_wake(irq);
                 else
-                        at91_rtc_write(AT91_RTC_IER, at91_rtc_imr);
+                        at91_rtc_write_ier(at91_rtc_imr);
         }
         return 0;
 }
@@ -383,12 +480,6 @@ static int at91_rtc_resume(struct device *dev)
 
 static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume);
 
-static const struct of_device_id at91_rtc_dt_ids[] = {
-        { .compatible = "atmel,at91rm9200-rtc" },
-        { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
-
 static struct platform_driver at91_rtc_driver = {
         .remove         = __exit_p(at91_rtc_remove),
         .driver         = {
diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c
index cc5bea9c4b1c..f1cb706445c7 100644
--- a/drivers/rtc/rtc-cmos.c
+++ b/drivers/rtc/rtc-cmos.c
@@ -854,6 +854,9 @@ static int cmos_resume(struct device *dev)
                 }
 
                 spin_lock_irq(&rtc_lock);
+                if (device_may_wakeup(dev))
+                        hpet_rtc_timer_init();
+
                 do {
                         CMOS_WRITE(tmp, RTC_CONTROL);
                         hpet_set_rtc_irq_bit(tmp & RTC_IRQMASK);
@@ -869,7 +872,6 @@ static int cmos_resume(struct device *dev)
                         rtc_update_irq(cmos->rtc, 1, mask);
                         tmp &= ~RTC_AIE;
                         hpet_mask_rtc_irq_bit(RTC_AIE);
-                        hpet_rtc_timer_init();
                 } while (mask & RTC_AIE);
                 spin_unlock_irq(&rtc_lock);
         }
diff --git a/drivers/rtc/rtc-coh901331.c b/drivers/rtc/rtc-coh901331.c
index 93c06588ddca..ad6863a76af9 100644
--- a/drivers/rtc/rtc-coh901331.c
+++ b/drivers/rtc/rtc-coh901331.c
@@ -274,11 +274,17 @@ static void coh901331_shutdown(struct platform_device *pdev)
         clk_disable_unprepare(rtap->clk);
 }
 
+static const struct of_device_id coh901331_dt_match[] = {
+        { .compatible = "stericsson,coh901331" },
+        {},
+};
+
 static struct platform_driver coh901331_driver = {
         .driver = {
                 .name = "rtc-coh901331",
                 .owner = THIS_MODULE,
                 .pm = &coh901331_pm_ops,
+                .of_match_table = coh901331_dt_match,
         },
         .remove = __exit_p(coh901331_remove),
         .shutdown = coh901331_shutdown,
diff --git a/drivers/rtc/rtc-tps6586x.c b/drivers/rtc/rtc-tps6586x.c
index 459c2ffc95a6..426901cef14f 100644
--- a/drivers/rtc/rtc-tps6586x.c
+++ b/drivers/rtc/rtc-tps6586x.c
@@ -273,6 +273,8 @@ static int tps6586x_rtc_probe(struct platform_device *pdev)
                 return ret;
         }
 
+        device_init_wakeup(&pdev->dev, 1);
+
         platform_set_drvdata(pdev, rtc);
         rtc->rtc = devm_rtc_device_register(&pdev->dev, dev_name(&pdev->dev),
                                        &tps6586x_rtc_ops, THIS_MODULE);
@@ -292,7 +294,6 @@ static int tps6586x_rtc_probe(struct platform_device *pdev)
                 goto fail_rtc_register;
         }
         disable_irq(rtc->irq);
-        device_set_wakeup_capable(&pdev->dev, 1);
         return 0;
 
 fail_rtc_register:
diff --git a/drivers/rtc/rtc-twl.c b/drivers/rtc/rtc-twl.c
index 8751a5240c99..b2eab34f38d9 100644
--- a/drivers/rtc/rtc-twl.c
+++ b/drivers/rtc/rtc-twl.c
@@ -524,6 +524,7 @@ static int twl_rtc_probe(struct platform_device *pdev)
         }
 
         platform_set_drvdata(pdev, rtc);
+        device_init_wakeup(&pdev->dev, 1);
         return 0;
 
 out2:
diff --git a/drivers/s390/block/dasd.c b/drivers/s390/block/dasd.c
index 4361d9772c42..d72a9216ee2e 100644
--- a/drivers/s390/block/dasd.c
+++ b/drivers/s390/block/dasd.c
@@ -3440,8 +3440,16 @@ void dasd_generic_path_event(struct ccw_device *cdev, int *path_event)
                         device->path_data.opm &= ~eventlpm;
                         device->path_data.ppm &= ~eventlpm;
                         device->path_data.npm &= ~eventlpm;
-                        if (oldopm && !device->path_data.opm)
-                                dasd_generic_last_path_gone(device);
+                        if (oldopm && !device->path_data.opm) {
+                                dev_warn(&device->cdev->dev,
+                                         "No verified channel paths remain "
+                                         "for the device\n");
+                                DBF_DEV_EVENT(DBF_WARNING, device,
+                                              "%s", "last verified path gone");
+                                dasd_eer_write(device, NULL, DASD_EER_NOPATH);
+                                dasd_device_set_stop_bits(device,
+                                                          DASD_STOPPED_DC_WAIT);
+                        }
                 }
                 if (path_event[chp] & PE_PATH_AVAILABLE) {
                         device->path_data.opm &= ~eventlpm;
diff --git a/drivers/s390/net/netiucv.c b/drivers/s390/net/netiucv.c
index 4ffa66c87ea5..9ca3996f65b2 100644
--- a/drivers/s390/net/netiucv.c
+++ b/drivers/s390/net/netiucv.c
@@ -2040,6 +2040,7 @@ static struct net_device *netiucv_init_netdevice(char *username, char *userdata)
                            netiucv_setup_netdevice);
         if (!dev)
                 return NULL;
+        rtnl_lock();
         if (dev_alloc_name(dev, dev->name) < 0)
                 goto out_netdev;
 
@@ -2061,6 +2062,7 @@ static struct net_device *netiucv_init_netdevice(char *username, char *userdata)
 out_fsm:
         kfree_fsm(privptr->fsm);
 out_netdev:
+        rtnl_unlock();
         free_netdev(dev);
         return NULL;
 }
@@ -2100,6 +2102,7 @@ static ssize_t conn_write(struct device_driver *drv,
 
         rc = netiucv_register_device(dev);
         if (rc) {
+                rtnl_unlock();
                 IUCV_DBF_TEXT_(setup, 2,
                         "ret %d from netiucv_register_device\n", rc);
                 goto out_free_ndev;
@@ -2109,7 +2112,8 @@ static ssize_t conn_write(struct device_driver *drv,
         priv = netdev_priv(dev);
         SET_NETDEV_DEV(dev, priv->dev);
 
-        rc = register_netdev(dev);
+        rc = register_netdevice(dev);
+        rtnl_unlock();
         if (rc)
                 goto out_unreg;
 
diff --git a/drivers/scsi/qla2xxx/tcm_qla2xxx.c b/drivers/scsi/qla2xxx/tcm_qla2xxx.c
index d182c96e17ea..7a3870f385f6 100644
--- a/drivers/scsi/qla2xxx/tcm_qla2xxx.c
+++ b/drivers/scsi/qla2xxx/tcm_qla2xxx.c
@@ -1370,7 +1370,7 @@ static void tcm_qla2xxx_free_session(struct qla_tgt_sess *sess)
                 dump_stack();
                 return;
         }
-        target_wait_for_sess_cmds(se_sess, 0);
+        target_wait_for_sess_cmds(se_sess);
 
         transport_deregister_session_configfs(sess->se_sess);
         transport_deregister_session(sess->se_sess);
diff --git a/drivers/scsi/scsi_proc.c b/drivers/scsi/scsi_proc.c
index db66357211ed..86f0c5d5c116 100644
--- a/drivers/scsi/scsi_proc.c
+++ b/drivers/scsi/scsi_proc.c
@@ -84,6 +84,7 @@ static int proc_scsi_host_open(struct inode *inode, struct file *file)
 
 static const struct file_operations proc_scsi_fops = {
         .open = proc_scsi_host_open,
+        .release = single_release,
         .read = seq_read,
         .llseek = seq_lseek,
         .write = proc_scsi_host_write
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index 371cc66f1a0e..3b246543282f 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -2083,6 +2083,7 @@ pl022_platform_data_dt_get(struct device *dev)
         }
 
         pd->bus_id = -1;
+        pd->enable_dma = 1;
         of_property_read_u32(np, "num-cs", &tmp);
         pd->num_chipselect = tmp;
         of_property_read_u32(np, "pl022,autosuspend-delay",
diff --git a/drivers/spi/spi-sh-hspi.c b/drivers/spi/spi-sh-hspi.c
index 60cfae51c713..eab593eaaafa 100644
--- a/drivers/spi/spi-sh-hspi.c
+++ b/drivers/spi/spi-sh-hspi.c
@@ -89,7 +89,7 @@ static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 val)
                 if ((mask & hspi_read(hspi, SPSR)) == val)
                         return 0;
 
-                msleep(20);
+                udelay(10);
         }
 
         dev_err(hspi->dev, "timeout\n");
diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
index 35f60bd252dd..637d728fbeb5 100644
--- a/drivers/spi/spi-topcliff-pch.c
+++ b/drivers/spi/spi-topcliff-pch.c
@@ -1487,7 +1487,7 @@ static int pch_spi_pd_probe(struct platform_device *plat_dev)
         return 0;
 
 err_spi_register_master:
-        free_irq(board_dat->pdev->irq, board_dat);
+        free_irq(board_dat->pdev->irq, data);
 err_request_irq:
         pch_spi_free_resources(board_dat, data);
 err_spi_get_resources:
@@ -1667,6 +1667,7 @@ static int pch_spi_probe(struct pci_dev *pdev,
                 pd_dev = platform_device_alloc("pch-spi", i);
                 if (!pd_dev) {
                         dev_err(&pdev->dev, "platform_device_alloc failed\n");
+                        retval = -ENOMEM;
                         goto err_platform_device;
                 }
                 pd_dev_save->pd_save[i] = pd_dev;
diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c
index e1d769607425..34d18dcfa0db 100644
--- a/drivers/spi/spi-xilinx.c
+++ b/drivers/spi/spi-xilinx.c
@@ -267,7 +267,6 @@ static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
 {
         struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
         u32 ipif_ier;
-        u16 cr;
 
         /* We get here with transmitter inhibited */
 
@@ -276,7 +275,6 @@ static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
         xspi->remaining_bytes = t->len;
         INIT_COMPLETION(xspi->done);
 
-        xilinx_spi_fill_tx_fifo(xspi);
 
         /* Enable the transmit empty interrupt, which we use to determine
          * progress on the transmission.
@@ -285,12 +283,41 @@ static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
         xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY,
                 xspi->regs + XIPIF_V123B_IIER_OFFSET);
 
-        /* Start the transfer by not inhibiting the transmitter any longer */
-        cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
-                ~XSPI_CR_TRANS_INHIBIT;
-        xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
+        for (;;) {
+                u16 cr;
+                u8 sr;
+
+                xilinx_spi_fill_tx_fifo(xspi);
+
+                /* Start the transfer by not inhibiting the transmitter any
+                 * longer
+                 */
+                cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
+                                                        ~XSPI_CR_TRANS_INHIBIT;
+                xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
+
+                wait_for_completion(&xspi->done);
+
+                /* A transmit has just completed. Process received data and
+                 * check for more data to transmit. Always inhibit the
+                 * transmitter while the Isr refills the transmit register/FIFO,
+                 * or make sure it is stopped if we're done.
+                 */
+                cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
+                xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
+                               xspi->regs + XSPI_CR_OFFSET);
+
+                /* Read out all the data from the Rx FIFO */
+                sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
+                while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
+                        xspi->rx_fn(xspi);
+                        sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
+                }
 
-        wait_for_completion(&xspi->done);
+                /* See if there is more data to send */
+                if (!xspi->remaining_bytes > 0)
+                        break;
+        }
 
         /* Disable the transmit empty interrupt */
         xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET);
@@ -314,38 +341,7 @@ static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
         xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
 
         if (ipif_isr & XSPI_INTR_TX_EMPTY) {    /* Transmission completed */
-                u16 cr;
-                u8 sr;
-
-                /* A transmit has just completed. Process received data and
-                 * check for more data to transmit. Always inhibit the
-                 * transmitter while the Isr refills the transmit register/FIFO,
-                 * or make sure it is stopped if we're done.
-                 */
-                cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
-                xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
-                        xspi->regs + XSPI_CR_OFFSET);
-
-                /* Read out all the data from the Rx FIFO */
-                sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
-                while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
-                        xspi->rx_fn(xspi);
-                        sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
-                }
-
-                /* See if there is more data to send */
-                if (xspi->remaining_bytes > 0) {
-                        xilinx_spi_fill_tx_fifo(xspi);
-                        /* Start the transfer by not inhibiting the
-                         * transmitter any longer
-                         */
-                        xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
-                } else {
-                        /* No more data to send.
-                         * Indicate the transfer is completed.
-                         */
-                        complete(&xspi->done);
-                }
+                complete(&xspi->done);
         }
 
         return IRQ_HANDLED;
diff --git a/drivers/staging/android/alarm-dev.c b/drivers/staging/android/alarm-dev.c
index ceb1c643753d..6dc27dac679d 100644
--- a/drivers/staging/android/alarm-dev.c
+++ b/drivers/staging/android/alarm-dev.c
@@ -264,6 +264,8 @@ static long alarm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
         }
 
         rv = alarm_do_ioctl(file, cmd, &ts);
+        if (rv)
+                return rv;
 
         switch (ANDROID_ALARM_BASE_CMD(cmd)) {
         case ANDROID_ALARM_GET_TIME(0):
@@ -272,7 +274,7 @@ static long alarm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
                 break;
         }
 
-        return rv;
+        return 0;
 }
 #ifdef CONFIG_COMPAT
 static long alarm_compat_ioctl(struct file *file, unsigned int cmd,
@@ -295,6 +297,8 @@ static long alarm_compat_ioctl(struct file *file, unsigned int cmd,
         }
 
         rv = alarm_do_ioctl(file, cmd, &ts);
+        if (rv)
+                return rv;
 
         switch (ANDROID_ALARM_BASE_CMD(cmd)) {
         case ANDROID_ALARM_GET_TIME(0): /* NOTE: we modified cmd above */
@@ -303,7 +307,7 @@ static long alarm_compat_ioctl(struct file *file, unsigned int cmd,
                 break;
         }
 
-        return rv;
+        return 0;
 }
 #endif
 
diff --git a/drivers/staging/dwc2/hcd.c b/drivers/staging/dwc2/hcd.c
index 827ab781ae9b..8551ccedf037 100644
--- a/drivers/staging/dwc2/hcd.c
+++ b/drivers/staging/dwc2/hcd.c
@@ -2804,9 +2804,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq,
 
         /* Set device flags indicating whether the HCD supports DMA */
         if (hsotg->core_params->dma_enable > 0) {
-                if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(31)) < 0)
-                        dev_warn(hsotg->dev,
-                                 "can't enable workaround for >2GB RAM\n");
+                if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
+                        dev_warn(hsotg->dev, "can't set DMA mask\n");
                 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(31)) < 0)
                         dev_warn(hsotg->dev,
                                  "can't enable workaround for >2GB RAM\n");
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index ea61c869110f..ff5c63350932 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -316,31 +316,14 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
 
 static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc)
 {
-        struct drm_pending_vblank_event *e;
-        struct timeval now;
         unsigned long flags;
         struct drm_device *drm = ipu_crtc->base.dev;
 
         spin_lock_irqsave(&drm->event_lock, flags);
-
-        e = ipu_crtc->page_flip_event;
-        if (!e) {
-                spin_unlock_irqrestore(&drm->event_lock, flags);
-                return;
-        }
-
-        do_gettimeofday(&now);
-        e->event.sequence = 0;
-        e->event.tv_sec = now.tv_sec;
-        e->event.tv_usec = now.tv_usec;
+        if (ipu_crtc->page_flip_event)
+                drm_send_vblank_event(drm, -1, ipu_crtc->page_flip_event);
         ipu_crtc->page_flip_event = NULL;
-
         imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc);
-
-        list_add_tail(&e->base.link, &e->base.file_priv->event_list);
-
-        wake_up_interruptible(&e->base.file_priv->event_wait);
-
         spin_unlock_irqrestore(&drm->event_lock, flags);
 }
 
diff --git a/drivers/staging/zcache/ramster.h b/drivers/staging/zcache/ramster.h
index e1f91d5a0f6a..a858666eae68 100644
--- a/drivers/staging/zcache/ramster.h
+++ b/drivers/staging/zcache/ramster.h
@@ -11,10 +11,6 @@
 #ifndef _ZCACHE_RAMSTER_H_
 #define _ZCACHE_RAMSTER_H_
 
-#ifdef CONFIG_RAMSTER_MODULE
-#define CONFIG_RAMSTER
-#endif
-
 #ifdef CONFIG_RAMSTER
 #include "ramster/ramster.h"
 #else
diff --git a/drivers/staging/zcache/ramster/debug.c b/drivers/staging/zcache/ramster/debug.c
index 327e4f0d98e1..5b26ee977c2f 100644
--- a/drivers/staging/zcache/ramster/debug.c
+++ b/drivers/staging/zcache/ramster/debug.c
@@ -1,6 +1,8 @@
 #include <linux/atomic.h>
 #include "debug.h"
 
+ssize_t ramster_foreign_eph_pages;
+ssize_t ramster_foreign_pers_pages;
 #ifdef CONFIG_DEBUG_FS
 #include <linux/debugfs.h>
 
diff --git a/drivers/staging/zcache/ramster/ramster.c b/drivers/staging/zcache/ramster/ramster.c
index b18b887db79f..a937ce1fa27a 100644
--- a/drivers/staging/zcache/ramster/ramster.c
+++ b/drivers/staging/zcache/ramster/ramster.c
@@ -66,8 +66,6 @@ static int ramster_remote_target_nodenum __read_mostly = -1;
 
 /* Used by this code. */
 long ramster_flnodes;
-ssize_t ramster_foreign_eph_pages;
-ssize_t ramster_foreign_pers_pages;
 /* FIXME frontswap selfshrinking knobs in debugfs? */
 
 static LIST_HEAD(ramster_rem_op_list);
@@ -399,14 +397,18 @@ void ramster_count_foreign_pages(bool eph, int count)
                         inc_ramster_foreign_eph_pages();
                 } else {
                         dec_ramster_foreign_eph_pages();
+#ifdef CONFIG_RAMSTER_DEBUG
                         WARN_ON_ONCE(ramster_foreign_eph_pages < 0);
+#endif
                 }
         } else {
                 if (count > 0) {
                         inc_ramster_foreign_pers_pages();
                 } else {
                         dec_ramster_foreign_pers_pages();
+#ifdef CONFIG_RAMSTER_DEBUG
                         WARN_ON_ONCE(ramster_foreign_pers_pages < 0);
+#endif
                 }
         }
 }
diff --git a/drivers/target/iscsi/iscsi_target.c b/drivers/target/iscsi/iscsi_target.c
index 262ef1f23b38..d7705e5824fb 100644
--- a/drivers/target/iscsi/iscsi_target.c
+++ b/drivers/target/iscsi/iscsi_target.c
@@ -651,7 +651,7 @@ static int iscsit_add_reject(
         cmd->buf_ptr = kmemdup(buf, ISCSI_HDR_LEN, GFP_KERNEL);
         if (!cmd->buf_ptr) {
                 pr_err("Unable to allocate memory for cmd->buf_ptr\n");
-                iscsit_release_cmd(cmd);
+                iscsit_free_cmd(cmd, false);
                 return -1;
         }
 
@@ -697,7 +697,7 @@ int iscsit_add_reject_from_cmd(
         cmd->buf_ptr = kmemdup(buf, ISCSI_HDR_LEN, GFP_KERNEL);
         if (!cmd->buf_ptr) {
                 pr_err("Unable to allocate memory for cmd->buf_ptr\n");
-                iscsit_release_cmd(cmd);
+                iscsit_free_cmd(cmd, false);
                 return -1;
         }
 
@@ -1743,7 +1743,7 @@ int iscsit_handle_nop_out(struct iscsi_conn *conn, struct iscsi_cmd *cmd,
         return 0;
 out:
         if (cmd)
-                iscsit_release_cmd(cmd);
+                iscsit_free_cmd(cmd, false);
 ping_out:
         kfree(ping_data);
         return ret;
@@ -2251,7 +2251,7 @@ iscsit_handle_logout_cmd(struct iscsi_conn *conn, struct iscsi_cmd *cmd,
         if (conn->conn_state != TARG_CONN_STATE_LOGGED_IN) {
                 pr_err("Received logout request on connection that"
                         " is not in logged in state, ignoring request.\n");
-                iscsit_release_cmd(cmd);
+                iscsit_free_cmd(cmd, false);
                 return 0;
         }
 
@@ -3665,7 +3665,7 @@ iscsit_immediate_queue(struct iscsi_conn *conn, struct iscsi_cmd *cmd, int state
                 list_del(&cmd->i_conn_node);
                 spin_unlock_bh(&conn->cmd_lock);
 
-                iscsit_free_cmd(cmd);
+                iscsit_free_cmd(cmd, false);
                 break;
         case ISTATE_SEND_NOPIN_WANT_RESPONSE:
                 iscsit_mod_nopin_response_timer(conn);
@@ -4122,7 +4122,7 @@ static void iscsit_release_commands_from_conn(struct iscsi_conn *conn)
 
                 iscsit_increment_maxcmdsn(cmd, sess);
 
-                iscsit_free_cmd(cmd);
+                iscsit_free_cmd(cmd, true);
 
                 spin_lock_bh(&conn->cmd_lock);
         }
diff --git a/drivers/target/iscsi/iscsi_target_erl2.c b/drivers/target/iscsi/iscsi_target_erl2.c
index ba6091bf93fc..45a5afd5ea13 100644
--- a/drivers/target/iscsi/iscsi_target_erl2.c
+++ b/drivers/target/iscsi/iscsi_target_erl2.c
@@ -143,7 +143,7 @@ void iscsit_free_connection_recovery_entires(struct iscsi_session *sess)
                         list_del(&cmd->i_conn_node);
                         cmd->conn = NULL;
                         spin_unlock(&cr->conn_recovery_cmd_lock);
-                        iscsit_free_cmd(cmd);
+                        iscsit_free_cmd(cmd, true);
                         spin_lock(&cr->conn_recovery_cmd_lock);
                 }
                 spin_unlock(&cr->conn_recovery_cmd_lock);
@@ -165,7 +165,7 @@ void iscsit_free_connection_recovery_entires(struct iscsi_session *sess)
                         list_del(&cmd->i_conn_node);
                         cmd->conn = NULL;
                         spin_unlock(&cr->conn_recovery_cmd_lock);
-                        iscsit_free_cmd(cmd);
+                        iscsit_free_cmd(cmd, true);
                         spin_lock(&cr->conn_recovery_cmd_lock);
                 }
                 spin_unlock(&cr->conn_recovery_cmd_lock);
@@ -248,7 +248,7 @@ void iscsit_discard_cr_cmds_by_expstatsn(
                 iscsit_remove_cmd_from_connection_recovery(cmd, sess);
 
                 spin_unlock(&cr->conn_recovery_cmd_lock);
-                iscsit_free_cmd(cmd);
+                iscsit_free_cmd(cmd, true);
                 spin_lock(&cr->conn_recovery_cmd_lock);
         }
         spin_unlock(&cr->conn_recovery_cmd_lock);
@@ -302,7 +302,7 @@ int iscsit_discard_unacknowledged_ooo_cmdsns_for_conn(struct iscsi_conn *conn)
                 list_del(&cmd->i_conn_node);
 
                 spin_unlock_bh(&conn->cmd_lock);
-                iscsit_free_cmd(cmd);
+                iscsit_free_cmd(cmd, true);
                 spin_lock_bh(&conn->cmd_lock);
         }
         spin_unlock_bh(&conn->cmd_lock);
@@ -355,7 +355,7 @@ int iscsit_prepare_cmds_for_realligance(struct iscsi_conn *conn)
 
                         list_del(&cmd->i_conn_node);
                         spin_unlock_bh(&conn->cmd_lock);
-                        iscsit_free_cmd(cmd);
+                        iscsit_free_cmd(cmd, true);
                         spin_lock_bh(&conn->cmd_lock);
                         continue;
                 }
@@ -375,7 +375,7 @@ int iscsit_prepare_cmds_for_realligance(struct iscsi_conn *conn)
                      iscsi_sna_gte(cmd->cmd_sn, conn->sess->exp_cmd_sn)) {
                         list_del(&cmd->i_conn_node);
                         spin_unlock_bh(&conn->cmd_lock);
-                        iscsit_free_cmd(cmd);
+                        iscsit_free_cmd(cmd, true);
                         spin_lock_bh(&conn->cmd_lock);
                         continue;
                 }
diff --git a/drivers/target/iscsi/iscsi_target_parameters.c b/drivers/target/iscsi/iscsi_target_parameters.c
index c2185fc31136..e38222191a33 100644
--- a/drivers/target/iscsi/iscsi_target_parameters.c
+++ b/drivers/target/iscsi/iscsi_target_parameters.c
@@ -758,9 +758,9 @@ static int iscsi_add_notunderstood_response(
         }
         INIT_LIST_HEAD(&extra_response->er_list);
 
-        strncpy(extra_response->key, key, strlen(key) + 1);
-        strncpy(extra_response->value, NOTUNDERSTOOD,
-                        strlen(NOTUNDERSTOOD) + 1);
+        strlcpy(extra_response->key, key, sizeof(extra_response->key));
+        strlcpy(extra_response->value, NOTUNDERSTOOD,
+                sizeof(extra_response->value));
 
         list_add_tail(&extra_response->er_list,
                         &param_list->extra_response_list);
@@ -1629,8 +1629,6 @@ int iscsi_decode_text_input(
 
                 if (phase & PHASE_SECURITY) {
                         if (iscsi_check_for_auth_key(key) > 0) {
-                                char *tmpptr = key + strlen(key);
-                                *tmpptr = '=';
                                 kfree(tmpbuf);
                                 return 1;
                         }
diff --git a/drivers/target/iscsi/iscsi_target_parameters.h b/drivers/target/iscsi/iscsi_target_parameters.h
index 915b06798505..a47046a752aa 100644
--- a/drivers/target/iscsi/iscsi_target_parameters.h
+++ b/drivers/target/iscsi/iscsi_target_parameters.h
@@ -1,8 +1,10 @@
 #ifndef ISCSI_PARAMETERS_H
 #define ISCSI_PARAMETERS_H
 
+#include <scsi/iscsi_proto.h>
+
 struct iscsi_extra_response {
-        char key[64];
+        char key[KEY_MAXLEN];
         char value[32];
         struct list_head er_list;
 } ____cacheline_aligned;
diff --git a/drivers/target/iscsi/iscsi_target_util.c b/drivers/target/iscsi/iscsi_target_util.c
index 2cc6c9a3ffb8..08a3bacef0c5 100644
--- a/drivers/target/iscsi/iscsi_target_util.c
+++ b/drivers/target/iscsi/iscsi_target_util.c
@@ -676,40 +676,56 @@ void iscsit_free_queue_reqs_for_conn(struct iscsi_conn *conn)
 
 void iscsit_release_cmd(struct iscsi_cmd *cmd)
 {
-        struct iscsi_conn *conn = cmd->conn;
-
-        iscsit_free_r2ts_from_list(cmd);
-        iscsit_free_all_datain_reqs(cmd);
-
         kfree(cmd->buf_ptr);
         kfree(cmd->pdu_list);
         kfree(cmd->seq_list);
         kfree(cmd->tmr_req);
         kfree(cmd->iov_data);
 
-        if (conn) {
+        kmem_cache_free(lio_cmd_cache, cmd);
+}
+
+static void __iscsit_free_cmd(struct iscsi_cmd *cmd, bool scsi_cmd,
+                              bool check_queues)
+{
+        struct iscsi_conn *conn = cmd->conn;
+
+        if (scsi_cmd) {
+                if (cmd->data_direction == DMA_TO_DEVICE) {
+                        iscsit_stop_dataout_timer(cmd);
+                        iscsit_free_r2ts_from_list(cmd);
+                }
+                if (cmd->data_direction == DMA_FROM_DEVICE)
+                        iscsit_free_all_datain_reqs(cmd);
+        }
+
+        if (conn && check_queues) {
                 iscsit_remove_cmd_from_immediate_queue(cmd, conn);
                 iscsit_remove_cmd_from_response_queue(cmd, conn);
         }
-
-        kmem_cache_free(lio_cmd_cache, cmd);
 }
 
-void iscsit_free_cmd(struct iscsi_cmd *cmd)
+void iscsit_free_cmd(struct iscsi_cmd *cmd, bool shutdown)
 {
+        struct se_cmd *se_cmd = NULL;
+        int rc;
         /*
          * Determine if a struct se_cmd is associated with
          * this struct iscsi_cmd.
          */
         switch (cmd->iscsi_opcode) {
         case ISCSI_OP_SCSI_CMD:
-                if (cmd->data_direction == DMA_TO_DEVICE)
-                        iscsit_stop_dataout_timer(cmd);
+                se_cmd = &cmd->se_cmd;
+                __iscsit_free_cmd(cmd, true, shutdown);
                 /*
                  * Fallthrough
                  */
         case ISCSI_OP_SCSI_TMFUNC:
-                transport_generic_free_cmd(&cmd->se_cmd, 1);
+                rc = transport_generic_free_cmd(&cmd->se_cmd, 1);
+                if (!rc && shutdown && se_cmd && se_cmd->se_sess) {
+                        __iscsit_free_cmd(cmd, true, shutdown);
+                        target_put_sess_cmd(se_cmd->se_sess, se_cmd);
+                }
                 break;
         case ISCSI_OP_REJECT:
                 /*
@@ -718,11 +734,19 @@ void iscsit_free_cmd(struct iscsi_cmd *cmd)
                  * associated cmd->se_cmd needs to be released.
                  */
                 if (cmd->se_cmd.se_tfo != NULL) {
-                        transport_generic_free_cmd(&cmd->se_cmd, 1);
+                        se_cmd = &cmd->se_cmd;
+                        __iscsit_free_cmd(cmd, true, shutdown);
+
+                        rc = transport_generic_free_cmd(&cmd->se_cmd, 1);
+                        if (!rc && shutdown && se_cmd->se_sess) {
+                                __iscsit_free_cmd(cmd, true, shutdown);
+                                target_put_sess_cmd(se_cmd->se_sess, se_cmd);
+                        }
                         break;
                 }
                 /* Fall-through */
         default:
+                __iscsit_free_cmd(cmd, false, shutdown);
                 cmd->release_cmd(cmd);
                 break;
         }
diff --git a/drivers/target/iscsi/iscsi_target_util.h b/drivers/target/iscsi/iscsi_target_util.h
index 4f8e01a47081..a4422659d049 100644
--- a/drivers/target/iscsi/iscsi_target_util.h
+++ b/drivers/target/iscsi/iscsi_target_util.h
@@ -29,7 +29,7 @@ extern void iscsit_remove_cmd_from_tx_queues(struct iscsi_cmd *, struct iscsi_co
 extern bool iscsit_conn_all_queues_empty(struct iscsi_conn *);
 extern void iscsit_free_queue_reqs_for_conn(struct iscsi_conn *);
 extern void iscsit_release_cmd(struct iscsi_cmd *);
-extern void iscsit_free_cmd(struct iscsi_cmd *);
+extern void iscsit_free_cmd(struct iscsi_cmd *, bool);
 extern int iscsit_check_session_usage_count(struct iscsi_session *);
 extern void iscsit_dec_session_usage_count(struct iscsi_session *);
 extern void iscsit_inc_session_usage_count(struct iscsi_session *);
diff --git a/drivers/target/target_core_file.c b/drivers/target/target_core_file.c
index 1b1d544e927a..b11890d85120 100644
--- a/drivers/target/target_core_file.c
+++ b/drivers/target/target_core_file.c
@@ -153,6 +153,7 @@ static int fd_configure_device(struct se_device *dev)
                 struct request_queue *q = bdev_get_queue(inode->i_bdev);
                 unsigned long long dev_size;
 
+                fd_dev->fd_block_size = bdev_logical_block_size(inode->i_bdev);
                 /*
                  * Determine the number of bytes from i_size_read() minus
                  * one (1) logical sector from underlying struct block_device
@@ -199,6 +200,7 @@ static int fd_configure_device(struct se_device *dev)
                         goto fail;
                 }
 
+                fd_dev->fd_block_size = FD_BLOCKSIZE;
                 /*
                  * Limit UNMAP emulation to 8k Number of LBAs (NoLB)
                  */
@@ -217,9 +219,7 @@ static int fd_configure_device(struct se_device *dev)
                 dev->dev_attrib.max_write_same_len = 0x1000;
         }
 
-        fd_dev->fd_block_size = dev->dev_attrib.hw_block_size;
-
-        dev->dev_attrib.hw_block_size = FD_BLOCKSIZE;
+        dev->dev_attrib.hw_block_size = fd_dev->fd_block_size;
         dev->dev_attrib.hw_max_sectors = FD_MAX_SECTORS;
         dev->dev_attrib.hw_queue_depth = FD_MAX_DEVICE_QUEUE_DEPTH;
 
@@ -694,11 +694,12 @@ static sector_t fd_get_blocks(struct se_device *dev)
          * to handle underlying block_device resize operations.
          */
         if (S_ISBLK(i->i_mode))
-                dev_size = (i_size_read(i) - fd_dev->fd_block_size);
+                dev_size = i_size_read(i);
         else
                 dev_size = fd_dev->fd_dev_size;
 
-        return div_u64(dev_size, dev->dev_attrib.block_size);
+        return div_u64(dev_size - dev->dev_attrib.block_size,
+                       dev->dev_attrib.block_size);
 }
 
 static struct sbc_ops fd_sbc_ops = {
diff --git a/drivers/target/target_core_transport.c b/drivers/target/target_core_transport.c
index 4a793362309d..21e315874a54 100644
--- a/drivers/target/target_core_transport.c
+++ b/drivers/target/target_core_transport.c
@@ -65,7 +65,7 @@ static void transport_complete_task_attr(struct se_cmd *cmd);
 static void transport_handle_queue_full(struct se_cmd *cmd,
                 struct se_device *dev);
 static int transport_generic_get_mem(struct se_cmd *cmd);
-static void transport_put_cmd(struct se_cmd *cmd);
+static int transport_put_cmd(struct se_cmd *cmd);
 static void target_complete_ok_work(struct work_struct *work);
 
 int init_se_kmem_caches(void)
@@ -221,6 +221,7 @@ struct se_session *transport_init_session(void)
         INIT_LIST_HEAD(&se_sess->sess_list);
         INIT_LIST_HEAD(&se_sess->sess_acl_list);
         INIT_LIST_HEAD(&se_sess->sess_cmd_list);
+        INIT_LIST_HEAD(&se_sess->sess_wait_list);
         spin_lock_init(&se_sess->sess_cmd_lock);
         kref_init(&se_sess->sess_kref);
 
@@ -1943,7 +1944,7 @@ static inline void transport_free_pages(struct se_cmd *cmd)
  * This routine unconditionally frees a command, and reference counting
  * or list removal must be done in the caller.
  */
-static void transport_release_cmd(struct se_cmd *cmd)
+static int transport_release_cmd(struct se_cmd *cmd)
 {
         BUG_ON(!cmd->se_tfo);
 
@@ -1955,11 +1956,11 @@ static void transport_release_cmd(struct se_cmd *cmd)
          * If this cmd has been setup with target_get_sess_cmd(), drop
          * the kref and call ->release_cmd() in kref callback.
          */
-         if (cmd->check_release != 0) {
-                target_put_sess_cmd(cmd->se_sess, cmd);
-                return;
-        }
+         if (cmd->check_release != 0)
+                return target_put_sess_cmd(cmd->se_sess, cmd);
+
         cmd->se_tfo->release_cmd(cmd);
+        return 1;
 }
 
 /**
@@ -1968,7 +1969,7 @@ static void transport_release_cmd(struct se_cmd *cmd)
  *
  * This routine releases our reference to the command and frees it if possible.
  */
-static void transport_put_cmd(struct se_cmd *cmd)
+static int transport_put_cmd(struct se_cmd *cmd)
 {
         unsigned long flags;
 
@@ -1976,7 +1977,7 @@ static void transport_put_cmd(struct se_cmd *cmd)
         if (atomic_read(&cmd->t_fe_count) &&
             !atomic_dec_and_test(&cmd->t_fe_count)) {
                 spin_unlock_irqrestore(&cmd->t_state_lock, flags);
-                return;
+                return 0;
         }
 
         if (cmd->transport_state & CMD_T_DEV_ACTIVE) {
@@ -1986,8 +1987,7 @@ static void transport_put_cmd(struct se_cmd *cmd)
         spin_unlock_irqrestore(&cmd->t_state_lock, flags);
 
         transport_free_pages(cmd);
-        transport_release_cmd(cmd);
-        return;
+        return transport_release_cmd(cmd);
 }
 
 void *transport_kmap_data_sg(struct se_cmd *cmd)
@@ -2152,13 +2152,15 @@ static void transport_write_pending_qf(struct se_cmd *cmd)
         }
 }
 
-void transport_generic_free_cmd(struct se_cmd *cmd, int wait_for_tasks)
+int transport_generic_free_cmd(struct se_cmd *cmd, int wait_for_tasks)
 {
+        int ret = 0;
+
         if (!(cmd->se_cmd_flags & SCF_SE_LUN_CMD)) {
                 if (wait_for_tasks && (cmd->se_cmd_flags & SCF_SCSI_TMR_CDB))
                          transport_wait_for_tasks(cmd);
 
-                transport_release_cmd(cmd);
+                ret = transport_release_cmd(cmd);
         } else {
                 if (wait_for_tasks)
                         transport_wait_for_tasks(cmd);
@@ -2166,8 +2168,9 @@ void transport_generic_free_cmd(struct se_cmd *cmd, int wait_for_tasks)
                 if (cmd->se_lun)
                         transport_lun_remove_cmd(cmd);
 
-                transport_put_cmd(cmd);
+                ret = transport_put_cmd(cmd);
         }
+        return ret;
 }
 EXPORT_SYMBOL(transport_generic_free_cmd);
 
@@ -2250,11 +2253,14 @@ void target_sess_cmd_list_set_waiting(struct se_session *se_sess)
         unsigned long flags;
 
         spin_lock_irqsave(&se_sess->sess_cmd_lock, flags);
-
-        WARN_ON(se_sess->sess_tearing_down);
+        if (se_sess->sess_tearing_down) {
+                spin_unlock_irqrestore(&se_sess->sess_cmd_lock, flags);
+                return;
+        }
         se_sess->sess_tearing_down = 1;
+        list_splice_init(&se_sess->sess_cmd_list, &se_sess->sess_wait_list);
 
-        list_for_each_entry(se_cmd, &se_sess->sess_cmd_list, se_cmd_list)
+        list_for_each_entry(se_cmd, &se_sess->sess_wait_list, se_cmd_list)
                 se_cmd->cmd_wait_set = 1;
 
         spin_unlock_irqrestore(&se_sess->sess_cmd_lock, flags);
@@ -2263,44 +2269,32 @@ EXPORT_SYMBOL(target_sess_cmd_list_set_waiting);
 
 /* target_wait_for_sess_cmds - Wait for outstanding descriptors
  * @se_sess:    session to wait for active I/O
- * @wait_for_tasks:     Make extra transport_wait_for_tasks call
  */
-void target_wait_for_sess_cmds(
-        struct se_session *se_sess,
-        int wait_for_tasks)
+void target_wait_for_sess_cmds(struct se_session *se_sess)
 {
         struct se_cmd *se_cmd, *tmp_cmd;
-        bool rc = false;
+        unsigned long flags;
 
         list_for_each_entry_safe(se_cmd, tmp_cmd,
-                                &se_sess->sess_cmd_list, se_cmd_list) {
+                                &se_sess->sess_wait_list, se_cmd_list) {
                 list_del(&se_cmd->se_cmd_list);
 
                 pr_debug("Waiting for se_cmd: %p t_state: %d, fabric state:"
                         " %d\n", se_cmd, se_cmd->t_state,
                         se_cmd->se_tfo->get_cmd_state(se_cmd));
 
-                if (wait_for_tasks) {
-                        pr_debug("Calling transport_wait_for_tasks se_cmd: %p t_state: %d,"
-                                " fabric state: %d\n", se_cmd, se_cmd->t_state,
-                                se_cmd->se_tfo->get_cmd_state(se_cmd));
-
-                        rc = transport_wait_for_tasks(se_cmd);
-
-                        pr_debug("After transport_wait_for_tasks se_cmd: %p t_state: %d,"
-                                " fabric state: %d\n", se_cmd, se_cmd->t_state,
-                                se_cmd->se_tfo->get_cmd_state(se_cmd));
-                }
-
-                if (!rc) {
-                        wait_for_completion(&se_cmd->cmd_wait_comp);
-                        pr_debug("After cmd_wait_comp: se_cmd: %p t_state: %d"
-                                " fabric state: %d\n", se_cmd, se_cmd->t_state,
-                                se_cmd->se_tfo->get_cmd_state(se_cmd));
-                }
+                wait_for_completion(&se_cmd->cmd_wait_comp);
+                pr_debug("After cmd_wait_comp: se_cmd: %p t_state: %d"
+                        " fabric state: %d\n", se_cmd, se_cmd->t_state,
+                        se_cmd->se_tfo->get_cmd_state(se_cmd));
 
                 se_cmd->se_tfo->release_cmd(se_cmd);
         }
+
+        spin_lock_irqsave(&se_sess->sess_cmd_lock, flags);
+        WARN_ON(!list_empty(&se_sess->sess_cmd_list));
+        spin_unlock_irqrestore(&se_sess->sess_cmd_lock, flags);
+
 }
 EXPORT_SYMBOL(target_wait_for_sess_cmds);
 
diff --git a/drivers/thermal/exynos_thermal.c b/drivers/thermal/exynos_thermal.c
index 788b1ddcac6c..4cbe3eea6deb 100644
--- a/drivers/thermal/exynos_thermal.c
+++ b/drivers/thermal/exynos_thermal.c
@@ -817,7 +817,8 @@ static struct exynos_tmu_platform_data const exynos4210_default_tmu_data = {
 #define EXYNOS4210_TMU_DRV_DATA (NULL)
 #endif
 
-#if defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412)
+#if defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412) || \
+        defined(CONFIG_SOC_EXYNOS4212)
 static struct exynos_tmu_platform_data const exynos_default_tmu_data = {
         .threshold_falling = 10,
         .trigger_levels[0] = 85,
diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c
index 46528d57be72..86c00b1c5583 100644
--- a/drivers/tty/serial/8250/8250_core.c
+++ b/drivers/tty/serial/8250/8250_core.c
@@ -2755,7 +2755,7 @@ static void __init serial8250_isa_init_ports(void)
         if (nr_uarts > UART_NR)
                 nr_uarts = UART_NR;
 
-        for (i = 0; i < UART_NR; i++) {
+        for (i = 0; i < nr_uarts; i++) {
                 struct uart_8250_port *up = &serial8250_ports[i];
                 struct uart_port *port = &up->port;
 
@@ -2916,7 +2916,7 @@ static int __init serial8250_console_setup(struct console *co, char *options)
          * if so, search for the first available port that does have
          * console support.
          */
-        if (co->index >= UART_NR)
+        if (co->index >= nr_uarts)
                 co->index = 0;
         port = &serial8250_ports[co->index].port;
         if (!port->iobase && !port->membase)
@@ -2957,7 +2957,7 @@ int serial8250_find_port(struct uart_port *p)
         int line;
         struct uart_port *port;
 
-        for (line = 0; line < UART_NR; line++) {
+        for (line = 0; line < nr_uarts; line++) {
                 port = &serial8250_ports[line].port;
                 if (uart_match_port(p, port))
                         return line;
@@ -3110,7 +3110,7 @@ static int serial8250_remove(struct platform_device *dev)
 {
         int i;
 
-        for (i = 0; i < UART_NR; i++) {
+        for (i = 0; i < nr_uarts; i++) {
                 struct uart_8250_port *up = &serial8250_ports[i];
 
                 if (up->port.dev == &dev->dev)
@@ -3178,7 +3178,7 @@ static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *
         /*
          * First, find a port entry which matches.
          */
-        for (i = 0; i < UART_NR; i++)
+        for (i = 0; i < nr_uarts; i++)
                 if (uart_match_port(&serial8250_ports[i].port, port))
                         return &serial8250_ports[i];
 
@@ -3187,7 +3187,7 @@ static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *
          * free entry.  We look for one which hasn't been previously
          * used (indicated by zero iobase).
          */
-        for (i = 0; i < UART_NR; i++)
+        for (i = 0; i < nr_uarts; i++)
                 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
                     serial8250_ports[i].port.iobase == 0)
                         return &serial8250_ports[i];
@@ -3196,7 +3196,7 @@ static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *
          * That also failed.  Last resort is to find any entry which
          * doesn't have a real port associated with it.
          */
-        for (i = 0; i < UART_NR; i++)
+        for (i = 0; i < nr_uarts; i++)
                 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
                         return &serial8250_ports[i];
 
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 147c9e193595..8cdfbd365892 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -761,6 +761,8 @@ static int imx_startup(struct uart_port *port)
 
         temp = readl(sport->port.membase + UCR2);
         temp |= (UCR2_RXEN | UCR2_TXEN);
+        if (!sport->have_rtscts)
+                temp |= UCR2_IRTS;
         writel(temp, sport->port.membase + UCR2);
 
         if (USE_IRDA(sport)) {
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 89429410a245..0c8a9fa2be6c 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1166,6 +1166,18 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
                 ourport->tx_irq = ret;
 
         ourport->clk    = clk_get(&platdev->dev, "uart");
+        if (IS_ERR(ourport->clk)) {
+                pr_err("%s: Controller clock not found\n",
+                                dev_name(&platdev->dev));
+                return PTR_ERR(ourport->clk);
+        }
+
+        ret = clk_prepare_enable(ourport->clk);
+        if (ret) {
+                pr_err("uart: clock failed to prepare+enable: %d\n", ret);
+                clk_put(ourport->clk);
+                return ret;
+        }
 
         /* Keep all interrupts masked and cleared */
         if (s3c24xx_serial_has_interrupt_mask(port)) {
@@ -1180,6 +1192,7 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
 
         /* reset the fifos (and setup the uart) */
         s3c24xx_serial_resetport(port, cfg);
+        clk_disable_unprepare(ourport->clk);
         return 0;
 }
 
diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c
index 4e5c77834c50..a4a3028103e3 100644
--- a/drivers/tty/serial/xilinx_uartps.c
+++ b/drivers/tty/serial/xilinx_uartps.c
@@ -14,6 +14,7 @@
 #include <linux/platform_device.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
+#include <linux/slab.h>
 #include <linux/tty.h>
 #include <linux/tty_flip.h>
 #include <linux/console.h>
@@ -139,6 +140,16 @@
 #define XUARTPS_SR_RXTRIG       0x00000001 /* Rx Trigger */
 
 /**
+ * struct xuartps - device data
+ * @refclk      Reference clock
+ * @aperclk     APB clock
+ */
+struct xuartps {
+        struct clk              *refclk;
+        struct clk              *aperclk;
+};
+
+/**
  * xuartps_isr - Interrupt handler
  * @irq: Irq number
  * @dev_id: Id of the port
@@ -936,34 +947,55 @@ static int xuartps_probe(struct platform_device *pdev)
         int rc;
         struct uart_port *port;
         struct resource *res, *res2;
-        struct clk *clk;
+        struct xuartps *xuartps_data;
 
-        clk = of_clk_get(pdev->dev.of_node, 0);
-        if (IS_ERR(clk)) {
-                dev_err(&pdev->dev, "no clock specified\n");
-                return PTR_ERR(clk);
+        xuartps_data = kzalloc(sizeof(*xuartps_data), GFP_KERNEL);
+        if (!xuartps_data)
+                return -ENOMEM;
+
+        xuartps_data->aperclk = clk_get(&pdev->dev, "aper_clk");
+        if (IS_ERR(xuartps_data->aperclk)) {
+                dev_err(&pdev->dev, "aper_clk clock not found.\n");
+                rc = PTR_ERR(xuartps_data->aperclk);
+                goto err_out_free;
+        }
+        xuartps_data->refclk = clk_get(&pdev->dev, "ref_clk");
+        if (IS_ERR(xuartps_data->refclk)) {
+                dev_err(&pdev->dev, "ref_clk clock not found.\n");
+                rc = PTR_ERR(xuartps_data->refclk);
+                goto err_out_clk_put_aper;
         }
 
-        rc = clk_prepare_enable(clk);
+        rc = clk_prepare_enable(xuartps_data->aperclk);
+        if (rc) {
+                dev_err(&pdev->dev, "Unable to enable APER clock.\n");
+                goto err_out_clk_put;
+        }
+        rc = clk_prepare_enable(xuartps_data->refclk);
         if (rc) {
-                dev_err(&pdev->dev, "could not enable clock\n");
-                return -EBUSY;
+                dev_err(&pdev->dev, "Unable to enable device clock.\n");
+                goto err_out_clk_dis_aper;
         }
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res)
-                return -ENODEV;
+        if (!res) {
+                rc = -ENODEV;
+                goto err_out_clk_disable;
+        }
 
         res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-        if (!res2)
-                return -ENODEV;
+        if (!res2) {
+                rc = -ENODEV;
+                goto err_out_clk_disable;
+        }
 
         /* Initialize the port structure */
         port = xuartps_get_port();
 
         if (!port) {
                 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
-                return -ENODEV;
+                rc = -ENODEV;
+                goto err_out_clk_disable;
         } else {
                 /* Register the port.
                  * This function also registers this device with the tty layer
@@ -972,18 +1004,31 @@ static int xuartps_probe(struct platform_device *pdev)
                 port->mapbase = res->start;
                 port->irq = res2->start;
                 port->dev = &pdev->dev;
-                port->uartclk = clk_get_rate(clk);
-                port->private_data = clk;
+                port->uartclk = clk_get_rate(xuartps_data->refclk);
+                port->private_data = xuartps_data;
                 dev_set_drvdata(&pdev->dev, port);
                 rc = uart_add_one_port(&xuartps_uart_driver, port);
                 if (rc) {
                         dev_err(&pdev->dev,
                                 "uart_add_one_port() failed; err=%i\n", rc);
                         dev_set_drvdata(&pdev->dev, NULL);
-                        return rc;
+                        goto err_out_clk_disable;
                 }
                 return 0;
         }
+
+err_out_clk_disable:
+        clk_disable_unprepare(xuartps_data->refclk);
+err_out_clk_dis_aper:
+        clk_disable_unprepare(xuartps_data->aperclk);
+err_out_clk_put:
+        clk_put(xuartps_data->refclk);
+err_out_clk_put_aper:
+        clk_put(xuartps_data->aperclk);
+err_out_free:
+        kfree(xuartps_data);
+
+        return rc;
 }
 
 /**
@@ -995,14 +1040,18 @@ static int xuartps_probe(struct platform_device *pdev)
 static int xuartps_remove(struct platform_device *pdev)
 {
         struct uart_port *port = dev_get_drvdata(&pdev->dev);
-        struct clk *clk = port->private_data;
+        struct xuartps *xuartps_data = port->private_data;
         int rc;
 
         /* Remove the xuartps port from the serial core */
         rc = uart_remove_one_port(&xuartps_uart_driver, port);
         dev_set_drvdata(&pdev->dev, NULL);
         port->mapbase = 0;
-        clk_disable_unprepare(clk);
+        clk_disable_unprepare(xuartps_data->refclk);
+        clk_disable_unprepare(xuartps_data->aperclk);
+        clk_put(xuartps_data->refclk);
+        clk_put(xuartps_data->aperclk);
+        kfree(xuartps_data);
         return rc;
 }
 
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 92e1dc94ecc8..a3b48b5ea8d3 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -43,6 +43,7 @@ config USB_ARCH_HAS_EHCI
         default y if ARCH_VT8500
         default y if PLAT_SPEAR
         default y if PLAT_S5P
+        default y if ARCH_EXYNOS
         default y if ARCH_MSM
         default y if MICROBLAZE
         default y if SPARC_LEON
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index 49b098bedf9b..475c9c114689 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -276,8 +276,9 @@ static void ci_role_work(struct work_struct *work)
 
                 ci_role_stop(ci);
                 ci_role_start(ci, role);
-                enable_irq(ci->irq);
         }
+
+        enable_irq(ci->irq);
 }
 
 static irqreturn_t ci_irq(int irq, void *data)
diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
index 519ead2443c5..b501346484ae 100644
--- a/drivers/usb/chipidea/udc.c
+++ b/drivers/usb/chipidea/udc.c
@@ -1678,8 +1678,11 @@ static int udc_start(struct ci13xxx *ci)
 
         ci->gadget.ep0 = &ci->ep0in->ep;
 
-        if (ci->global_phy)
+        if (ci->global_phy) {
                 ci->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
+                if (IS_ERR(ci->transceiver))
+                        ci->transceiver = NULL;
+        }
 
         if (ci->platdata->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
                 if (ci->transceiver == NULL) {
@@ -1694,7 +1697,7 @@ static int udc_start(struct ci13xxx *ci)
                         goto put_transceiver;
         }
 
-        if (!IS_ERR_OR_NULL(ci->transceiver)) {
+        if (ci->transceiver) {
                 retval = otg_set_peripheral(ci->transceiver->otg,
                                                 &ci->gadget);
                 if (retval)
@@ -1711,7 +1714,7 @@ static int udc_start(struct ci13xxx *ci)
         return retval;
 
 remove_trans:
-        if (!IS_ERR_OR_NULL(ci->transceiver)) {
+        if (ci->transceiver) {
                 otg_set_peripheral(ci->transceiver->otg, NULL);
                 if (ci->global_phy)
                         usb_put_phy(ci->transceiver);
@@ -1719,7 +1722,7 @@ remove_trans:
 
         dev_err(dev, "error = %i\n", retval);
 put_transceiver:
-        if (!IS_ERR_OR_NULL(ci->transceiver) && ci->global_phy)
+        if (ci->transceiver && ci->global_phy)
                 usb_put_phy(ci->transceiver);
 destroy_eps:
         destroy_eps(ci);
@@ -1747,7 +1750,7 @@ static void udc_stop(struct ci13xxx *ci)
         dma_pool_destroy(ci->td_pool);
         dma_pool_destroy(ci->qh_pool);
 
-        if (!IS_ERR_OR_NULL(ci->transceiver)) {
+        if (ci->transceiver) {
                 otg_set_peripheral(ci->transceiver->otg, NULL);
                 if (ci->global_phy)
                         usb_put_phy(ci->transceiver);
diff --git a/drivers/usb/core/devio.c b/drivers/usb/core/devio.c
index caefc800f298..c88c4fb9459d 100644
--- a/drivers/usb/core/devio.c
+++ b/drivers/usb/core/devio.c
@@ -1287,9 +1287,13 @@ static int proc_do_submiturb(struct dev_state *ps, struct usbdevfs_urb *uurb,
                         goto error;
                 }
                 for (totlen = u = 0; u < uurb->number_of_packets; u++) {
-                        /* arbitrary limit,
-                         * sufficient for USB 2.0 high-bandwidth iso */
-                        if (isopkt[u].length > 8192) {
+                        /*
+                         * arbitrary limit need for USB 3.0
+                         * bMaxBurst (0~15 allowed, 1~16 packets)
+                         * bmAttributes (bit 1:0, mult 0~2, 1~3 packets)
+                         * sizemax: 1024 * 16 * 3 = 49152
+                         */
+                        if (isopkt[u].length > 49152) {
                                 ret = -EINVAL;
                                 goto error;
                         }
diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
index 929e7dd6e58b..8ce9d7fd6cfc 100644
--- a/drivers/usb/dwc3/dwc3-exynos.c
+++ b/drivers/usb/dwc3/dwc3-exynos.c
@@ -164,9 +164,9 @@ static int dwc3_exynos_remove(struct platform_device *pdev)
 {
         struct dwc3_exynos      *exynos = platform_get_drvdata(pdev);
 
+        device_for_each_child(&pdev->dev, NULL, dwc3_exynos_remove_child);
         platform_device_unregister(exynos->usb2_phy);
         platform_device_unregister(exynos->usb3_phy);
-        device_for_each_child(&pdev->dev, NULL, dwc3_exynos_remove_child);
 
         clk_disable_unprepare(exynos->clk);
 
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index 227d4a7acad7..eba9e2baf32b 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -196,9 +196,9 @@ static void dwc3_pci_remove(struct pci_dev *pci)
 {
         struct dwc3_pci *glue = pci_get_drvdata(pci);
 
+        platform_device_unregister(glue->dwc3);
         platform_device_unregister(glue->usb2_phy);
         platform_device_unregister(glue->usb3_phy);
-        platform_device_unregister(glue->dwc3);
         pci_set_drvdata(pci, NULL);
         pci_disable_device(pci);
 }
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 2b6e7e001207..b5e5b35df49c 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -1706,11 +1706,19 @@ static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
                 dep = dwc->eps[epnum];
                 if (!dep)
                         continue;
-
-                dwc3_free_trb_pool(dep);
-
-                if (epnum != 0 && epnum != 1)
+                /*
+                 * Physical endpoints 0 and 1 are special; they form the
+                 * bi-directional USB endpoint 0.
+                 *
+                 * For those two physical endpoints, we don't allocate a TRB
+                 * pool nor do we add them the endpoints list. Due to that, we
+                 * shouldn't do these two operations otherwise we would end up
+                 * with all sorts of bugs when removing dwc3.ko.
+                 */
+                if (epnum != 0 && epnum != 1) {
+                        dwc3_free_trb_pool(dep);
                         list_del(&dep->endpoint.ep_list);
+                }
 
                 kfree(dep);
         }
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 344d5e2f87d7..922a65d361c8 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -225,7 +225,7 @@ config USB_EHCI_SH
 
 config USB_EHCI_S5P
        tristate "EHCI support for Samsung S5P/EXYNOS SoC Series"
-       depends on PLAT_S5P
+       depends on PLAT_S5P || ARCH_EXYNOS
        help
         Enable support for the Samsung S5Pxxxx and Exynos3/4/5 SOC's
         on-chip EHCI controller.
diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
index f47f2594c9d4..d1f5cea435aa 100644
--- a/drivers/usb/host/ehci-platform.c
+++ b/drivers/usb/host/ehci-platform.c
@@ -48,6 +48,12 @@ static int ehci_platform_reset(struct usb_hcd *hcd)
         ehci->big_endian_desc = pdata->big_endian_desc;
         ehci->big_endian_mmio = pdata->big_endian_mmio;
 
+        if (pdata->pre_setup) {
+                retval = pdata->pre_setup(hcd);
+                if (retval < 0)
+                        return retval;
+        }
+
         ehci->caps = hcd->regs + pdata->caps_offset;
         retval = ehci_setup(hcd);
         if (retval)
diff --git a/drivers/usb/host/ehci-sched.c b/drivers/usb/host/ehci-sched.c
index acff5b8f6e89..f80d0330d548 100644
--- a/drivers/usb/host/ehci-sched.c
+++ b/drivers/usb/host/ehci-sched.c
@@ -213,7 +213,7 @@ static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
 }
 
 static const unsigned char
-max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 125, 25 };
+max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 };
 
 /* carryover low/fullspeed bandwidth that crosses uframe boundries */
 static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8])
@@ -646,6 +646,10 @@ static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh)
         /* reschedule QH iff another request is queued */
         if (!list_empty(&qh->qtd_list) && ehci->rh_state == EHCI_RH_RUNNING) {
                 rc = qh_schedule(ehci, qh);
+                if (rc == 0) {
+                        qh_refresh(ehci, qh);
+                        qh_link_periodic(ehci, qh);
+                }
 
                 /* An error here likely indicates handshake failure
                  * or no space left in the schedule.  Neither fault
@@ -653,9 +657,10 @@ static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh)
                  *
                  * FIXME kill the now-dysfunctional queued urbs
                  */
-                if (rc != 0)
+                else {
                         ehci_err(ehci, "can't reschedule qh %p, err %d\n",
                                         qh, rc);
+                }
         }
 
         /* maybe turn off periodic schedule */
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 2cfc465925bd..fbf75e57628b 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -1827,6 +1827,9 @@ void xhci_mem_cleanup(struct xhci_hcd *xhci)
         }
         spin_unlock_irqrestore(&xhci->lock, flags);
 
+        if (!xhci->rh_bw)
+                goto no_bw;
+
         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
         for (i = 0; i < num_ports; i++) {
                 struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
@@ -1845,6 +1848,7 @@ void xhci_mem_cleanup(struct xhci_hcd *xhci)
                 }
         }
 
+no_bw:
         xhci->num_usb2_ports = 0;
         xhci->num_usb3_ports = 0;
         xhci->num_active_eps = 0;
@@ -2256,6 +2260,9 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
         u32 page_size, temp;
         int i;
 
+        INIT_LIST_HEAD(&xhci->lpm_failed_devs);
+        INIT_LIST_HEAD(&xhci->cancel_cmd_list);
+
         page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
         xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
         for (i = 0; i < 16; i++) {
@@ -2334,7 +2341,6 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
         xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, flags);
         if (!xhci->cmd_ring)
                 goto fail;
-        INIT_LIST_HEAD(&xhci->cancel_cmd_list);
         xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
         xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
                         (unsigned long long)xhci->cmd_ring->first_seg->dma);
@@ -2445,8 +2451,6 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
         if (xhci_setup_port_arrays(xhci, flags))
                 goto fail;
 
-        INIT_LIST_HEAD(&xhci->lpm_failed_devs);
-
         /* Enable USB 3.0 device notifications for function remote wake, which
          * is necessary for allowing USB 3.0 devices to do remote wakeup from
          * U3 (device suspend).
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index 1a30c380043c..cc24e39b97d5 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -221,6 +221,14 @@ static void xhci_pci_remove(struct pci_dev *dev)
 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 {
         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+        struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
+
+        /*
+         * Systems with the TI redriver that loses port status change events
+         * need to have the registers polled during D3, so avoid D3cold.
+         */
+        if (xhci_compliance_mode_recovery_timer_quirk_check())
+                pdev->no_d3cold = true;
 
         return xhci_suspend(xhci);
 }
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index b4aa79d154b2..d8f640b12dd9 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -466,7 +466,7 @@ static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
  * Systems:
  * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
  */
-static bool compliance_mode_recovery_timer_quirk_check(void)
+bool xhci_compliance_mode_recovery_timer_quirk_check(void)
 {
         const char *dmi_product_name, *dmi_sys_vendor;
 
@@ -517,7 +517,7 @@ int xhci_init(struct usb_hcd *hcd)
         xhci_dbg(xhci, "Finished xhci_init\n");
 
         /* Initializing Compliance Mode Recovery Data If Needed */
-        if (compliance_mode_recovery_timer_quirk_check()) {
+        if (xhci_compliance_mode_recovery_timer_quirk_check()) {
                 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
                 compliance_mode_recovery_timer_init(xhci);
         }
@@ -956,6 +956,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
         struct usb_hcd          *hcd = xhci_to_hcd(xhci);
         struct usb_hcd          *secondary_hcd;
         int                     retval = 0;
+        bool                    comp_timer_running = false;
 
         /* Wait a bit if either of the roothubs need to settle from the
          * transition into bus suspend.
@@ -993,6 +994,13 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
 
         /* If restore operation fails, re-initialize the HC during resume */
         if ((temp & STS_SRE) || hibernated) {
+
+                if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
+                                !(xhci_all_ports_seen_u0(xhci))) {
+                        del_timer_sync(&xhci->comp_mode_recovery_timer);
+                        xhci_dbg(xhci, "Compliance Mode Recovery Timer deleted!\n");
+                }
+
                 /* Let the USB core know _both_ roothubs lost power. */
                 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
                 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
@@ -1035,6 +1043,8 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
                 retval = xhci_init(hcd->primary_hcd);
                 if (retval)
                         return retval;
+                comp_timer_running = true;
+
                 xhci_dbg(xhci, "Start the primary HCD\n");
                 retval = xhci_run(hcd->primary_hcd);
                 if (!retval) {
@@ -1076,7 +1086,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
          * to suffer the Compliance Mode issue again. It doesn't matter if
          * ports have entered previously to U0 before system's suspension.
          */
-        if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
+        if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
                 compliance_mode_recovery_timer_init(xhci);
 
         /* Re-enable port polling. */
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 29c978e37135..77600cefcaf1 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1853,4 +1853,7 @@ struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
 
+/* xHCI quirks */
+bool xhci_compliance_mode_recovery_timer_quirk_check(void);
+
 #endif /* __LINUX_XHCI_HCD_H */
diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
index 8914dec49f01..9d3044bdebe5 100644
--- a/drivers/usb/musb/musb_host.c
+++ b/drivers/usb/musb/musb_host.c
@@ -1232,7 +1232,6 @@ void musb_host_tx(struct musb *musb, u8 epnum)
         void __iomem            *mbase = musb->mregs;
         struct dma_channel      *dma;
         bool                    transfer_pending = false;
-        static bool use_sg;
 
         musb_ep_select(mbase, epnum);
         tx_csr = musb_readw(epio, MUSB_TXCSR);
@@ -1463,9 +1462,9 @@ done:
          * NULL.
          */
         if (!urb->transfer_buffer)
-                use_sg = true;
+                qh->use_sg = true;
 
-        if (use_sg) {
+        if (qh->use_sg) {
                 /* sg_miter_start is already done in musb_ep_program */
                 if (!sg_miter_next(&qh->sg_miter)) {
                         dev_err(musb->controller, "error: sg list empty\n");
@@ -1484,9 +1483,9 @@ done:
 
         qh->segsize = length;
 
-        if (use_sg) {
+        if (qh->use_sg) {
                 if (offset + length >= urb->transfer_buffer_length)
-                        use_sg = false;
+                        qh->use_sg = false;
         }
 
         musb_ep_select(mbase, epnum);
@@ -1552,7 +1551,6 @@ void musb_host_rx(struct musb *musb, u8 epnum)
         bool                    done = false;
         u32                     status;
         struct dma_channel      *dma;
-        static bool use_sg;
         unsigned int sg_flags = SG_MITER_ATOMIC | SG_MITER_TO_SG;
 
         musb_ep_select(mbase, epnum);
@@ -1878,12 +1876,12 @@ void musb_host_rx(struct musb *musb, u8 epnum)
                          * NULL.
                          */
                         if (!urb->transfer_buffer) {
-                                use_sg = true;
+                                qh->use_sg = true;
                                 sg_miter_start(&qh->sg_miter, urb->sg, 1,
                                                 sg_flags);
                         }
 
-                        if (use_sg) {
+                        if (qh->use_sg) {
                                 if (!sg_miter_next(&qh->sg_miter)) {
                                         dev_err(musb->controller, "error: sg list empty\n");
                                         sg_miter_stop(&qh->sg_miter);
@@ -1913,8 +1911,8 @@ finish:
         urb->actual_length += xfer_len;
         qh->offset += xfer_len;
         if (done) {
-                if (use_sg)
-                        use_sg = false;
+                if (qh->use_sg)
+                        qh->use_sg = false;
 
                 if (urb->status == -EINPROGRESS)
                         urb->status = status;
diff --git a/drivers/usb/musb/musb_host.h b/drivers/usb/musb/musb_host.h
index 5a9c8feec10c..738f7eb60df9 100644
--- a/drivers/usb/musb/musb_host.h
+++ b/drivers/usb/musb/musb_host.h
@@ -74,6 +74,7 @@ struct musb_qh {
         u16                     frame;          /* for periodic schedule */
         unsigned                iso_idx;        /* in urb->iso_frame_desc[] */
         struct sg_mapping_iter sg_miter;        /* for highmem in PIO mode */
+        bool                    use_sg;         /* to track urb using sglist */
 };
 
 /* map from control or bulk queue head to the first qh on that ring */
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 7ef3eb8617a6..13c09c299f15 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -180,15 +180,15 @@ config USB_MXS_PHY
           MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x.
 
 config USB_RCAR_PHY
-        tristate "Renesas R-Car USB phy support"
+        tristate "Renesas R-Car USB PHY support"
         depends on USB || USB_GADGET
         help
-          Say Y here to add support for the Renesas R-Car USB phy driver.
-          This chip is typically used as USB phy for USB host, gadget.
-          This driver supports: R8A7779
+          Say Y here to add support for the Renesas R-Car USB common PHY driver.
+          This chip is typically used as USB PHY for USB host, gadget.
+          This driver supports R8A7778 and R8A7779.
 
           To compile this driver as a module, choose M here: the
-          module will be called rcar-phy.
+          module will be called phy-rcar-usb.
 
 config USB_ULPI
         bool "Generic ULPI Transceiver Driver"
diff --git a/drivers/usb/phy/phy-rcar-usb.c b/drivers/usb/phy/phy-rcar-usb.c
index a35681b0c501..ae909408958d 100644
--- a/drivers/usb/phy/phy-rcar-usb.c
+++ b/drivers/usb/phy/phy-rcar-usb.c
@@ -1,8 +1,9 @@
 /*
  * Renesas R-Car USB phy driver
  *
- * Copyright (C) 2012 Renesas Solutions Corp.
+ * Copyright (C) 2012-2013 Renesas Solutions Corp.
  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ * Copyright (C) 2013 Cogent Embedded, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -15,17 +16,41 @@
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
 #include <linux/module.h>
-
-/* USBH common register */
-#define USBPCTRL0       0x0800
-#define USBPCTRL1       0x0804
-#define USBST           0x0808
-#define USBEH0          0x080C
-#define USBOH0          0x081C
-#define USBCTL0         0x0858
-#define EIIBC1          0x0094
-#define EIIBC2          0x009C
-
+#include <linux/platform_data/usb-rcar-phy.h>
+
+/* REGS block */
+#define USBPCTRL0       0x00
+#define USBPCTRL1       0x04
+#define USBST           0x08
+#define USBEH0          0x0C
+#define USBOH0          0x1C
+#define USBCTL0         0x58
+
+/* High-speed signal quality characteristic control registers (R8A7778 only) */
+#define HSQCTL1         0x24
+#define HSQCTL2         0x28
+
+/* USBPCTRL0 */
+#define OVC2            (1 << 10) /* (R8A7779 only)                     */
+                                /* Switches the OVC input pin for port 2: */
+                                /* 1: USB_OVC2, 0: OVC2                 */
+#define OVC1_VBUS1      (1 << 9) /* Switches the OVC input pin for port 1: */
+                                /* 1: USB_OVC1, 0: OVC1/VBUS1           */
+                                /* Function mode: set to 0              */
+#define OVC0            (1 << 8) /* Switches the OVC input pin for port 0: */
+                                /* 1: USB_OVC0 pin, 0: OVC0             */
+#define OVC2_ACT        (1 << 6) /* (R8A7779 only)                      */
+                                /* Host mode: OVC2 polarity:            */
+                                /* 1: active-high, 0: active-low        */
+#define PENC            (1 << 4) /* Function mode: output level of PENC1 pin: */
+                                /* 1: high, 0: low                      */
+#define OVC0_ACT        (1 << 3) /* Host mode: OVC0 polarity:           */
+                                /* 1: active-high, 0: active-low        */
+#define OVC1_ACT        (1 << 1) /* Host mode: OVC1 polarity:           */
+                                /* 1: active-high, 0: active-low        */
+                                /* Function mode: be sure to set to 1   */
+#define PORT1           (1 << 0) /* Selects port 1 mode:                */
+                                /* 1: function, 0: host                 */
 /* USBPCTRL1 */
 #define PHY_RST         (1 << 2)
 #define PLL_ENB         (1 << 1)
@@ -58,8 +83,10 @@ static int rcar_usb_phy_init(struct usb_phy *phy)
 {
         struct rcar_usb_phy_priv *priv = usb_phy_to_priv(phy);
         struct device *dev = phy->dev;
+        struct rcar_phy_platform_data *pdata = dev->platform_data;
         void __iomem *reg0 = priv->reg0;
         void __iomem *reg1 = priv->reg1;
+        static const u8 ovcn_act[] = { OVC0_ACT, OVC1_ACT, OVC2_ACT };
         int i;
         u32 val;
         unsigned long flags;
@@ -77,7 +104,16 @@ static int rcar_usb_phy_init(struct usb_phy *phy)
                 /* (2) start USB-PHY internal PLL */
                 iowrite32(PHY_ENB | PLL_ENB, (reg0 + USBPCTRL1));
 
-                /* (3) USB module status check */
+                /* (3) set USB-PHY in accord with the conditions of usage */
+                if (reg1) {
+                        u32 hsqctl1 = pdata->ferrite_bead ? 0x41 : 0;
+                        u32 hsqctl2 = pdata->ferrite_bead ? 0x0d : 7;
+
+                        iowrite32(hsqctl1, reg1 + HSQCTL1);
+                        iowrite32(hsqctl2, reg1 + HSQCTL2);
+                }
+
+                /* (4) USB module status check */
                 for (i = 0; i < 1024; i++) {
                         udelay(10);
                         val = ioread32(reg0 + USBST);
@@ -90,24 +126,24 @@ static int rcar_usb_phy_init(struct usb_phy *phy)
                         goto phy_init_end;
                 }
 
-                /* (4) USB-PHY reset clear */
+                /* (5) USB-PHY reset clear */
                 iowrite32(PHY_ENB | PLL_ENB | PHY_RST, (reg0 + USBPCTRL1));
 
-                /* set platform specific port settings */
-                iowrite32(0x00000000, (reg0 + USBPCTRL0));
-
-                /*
-                 * EHCI IP internal buffer setting
-                 * EHCI IP internal buffer enable
-                 *
-                 * These are recommended value of a datasheet
-                 * see [USB :: EHCI internal buffer setting]
-                 */
-                iowrite32(0x00ff0040, (reg0 + EIIBC1));
-                iowrite32(0x00ff0040, (reg1 + EIIBC1));
-
-                iowrite32(0x00000001, (reg0 + EIIBC2));
-                iowrite32(0x00000001, (reg1 + EIIBC2));
+                /* Board specific port settings */
+                val = 0;
+                if (pdata->port1_func)
+                        val |= PORT1;
+                if (pdata->penc1)
+                        val |= PENC;
+                for (i = 0; i < 3; i++) {
+                        /* OVCn bits follow each other in the right order */
+                        if (pdata->ovc_pin[i].select_3_3v)
+                                val |= OVC0 << i;
+                        /* OVCn_ACT bits are spaced by irregular intervals */
+                        if (pdata->ovc_pin[i].active_high)
+                                val |= ovcn_act[i];
+                }
+                iowrite32(val, (reg0 + USBPCTRL0));
 
                 /*
                  * Bus alignment settings
@@ -134,10 +170,8 @@ static void rcar_usb_phy_shutdown(struct usb_phy *phy)
 
         spin_lock_irqsave(&priv->lock, flags);
 
-        if (priv->counter-- == 1) { /* last user */
-                iowrite32(0x00000000, (reg0 + USBPCTRL0));
+        if (priv->counter-- == 1)       /* last user */
                 iowrite32(0x00000000, (reg0 + USBPCTRL1));
-        }
 
         spin_unlock_irqrestore(&priv->lock, flags);
 }
@@ -147,27 +181,29 @@ static int rcar_usb_phy_probe(struct platform_device *pdev)
         struct rcar_usb_phy_priv *priv;
         struct resource *res0, *res1;
         struct device *dev = &pdev->dev;
-        void __iomem *reg0, *reg1;
+        void __iomem *reg0, *reg1 = NULL;
         int ret;
 
+        if (!pdev->dev.platform_data) {
+                dev_err(dev, "No platform data\n");
+                return -EINVAL;
+        }
+
         res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-        if (!res0 || !res1) {
+        if (!res0) {
                 dev_err(dev, "Not enough platform resources\n");
                 return -EINVAL;
         }
 
-        /*
-         * CAUTION
-         *
-         * Because this phy address is also mapped under OHCI/EHCI address area,
-         * this driver can't use devm_request_and_ioremap(dev, res) here
-         */
-        reg0 = devm_ioremap_nocache(dev, res0->start, resource_size(res0));
-        reg1 = devm_ioremap_nocache(dev, res1->start, resource_size(res1));
-        if (!reg0 || !reg1) {
-                dev_err(dev, "ioremap error\n");
-                return -ENOMEM;
+        reg0 = devm_ioremap_resource(dev, res0);
+        if (IS_ERR(reg0))
+                return PTR_ERR(reg0);
+
+        res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+        if (res1) {
+                reg1 = devm_ioremap_resource(dev, res1);
+                if (IS_ERR(reg1))
+                        return PTR_ERR(reg1);
         }
 
         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
diff --git a/drivers/usb/serial/ark3116.c b/drivers/usb/serial/ark3116.c
index 3b16118cbf62..40e7fd94646f 100644
--- a/drivers/usb/serial/ark3116.c
+++ b/drivers/usb/serial/ark3116.c
@@ -43,7 +43,7 @@
 #define DRIVER_NAME "ark3116"
 
 /* usb timeout of 1 second */
-#define ARK_TIMEOUT (1*HZ)
+#define ARK_TIMEOUT 1000
 
 static const struct usb_device_id id_table[] = {
         { USB_DEVICE(0x6547, 0x0232) },
diff --git a/drivers/usb/serial/cypress_m8.c b/drivers/usb/serial/cypress_m8.c
index d341555d37d8..082120198f87 100644
--- a/drivers/usb/serial/cypress_m8.c
+++ b/drivers/usb/serial/cypress_m8.c
@@ -65,6 +65,7 @@ static const struct usb_device_id id_table_earthmate[] = {
 static const struct usb_device_id id_table_cyphidcomrs232[] = {
         { USB_DEVICE(VENDOR_ID_CYPRESS, PRODUCT_ID_CYPHIDCOM) },
         { USB_DEVICE(VENDOR_ID_POWERCOM, PRODUCT_ID_UPS) },
+        { USB_DEVICE(VENDOR_ID_FRWD, PRODUCT_ID_CYPHIDCOM_FRWD) },
         { }                                             /* Terminating entry */
 };
 
@@ -78,6 +79,7 @@ static const struct usb_device_id id_table_combined[] = {
         { USB_DEVICE(VENDOR_ID_DELORME, PRODUCT_ID_EARTHMATEUSB_LT20) },
         { USB_DEVICE(VENDOR_ID_CYPRESS, PRODUCT_ID_CYPHIDCOM) },
         { USB_DEVICE(VENDOR_ID_POWERCOM, PRODUCT_ID_UPS) },
+        { USB_DEVICE(VENDOR_ID_FRWD, PRODUCT_ID_CYPHIDCOM_FRWD) },
         { USB_DEVICE(VENDOR_ID_DAZZLE, PRODUCT_ID_CA42) },
         { }                                             /* Terminating entry */
 };
@@ -229,6 +231,12 @@ static struct usb_serial_driver * const serial_drivers[] = {
  * Cypress serial helper functions
  *****************************************************************************/
 
+/* FRWD Dongle hidcom needs to skip reset and speed checks */
+static inline bool is_frwd(struct usb_device *dev)
+{
+        return ((le16_to_cpu(dev->descriptor.idVendor) == VENDOR_ID_FRWD) &&
+                (le16_to_cpu(dev->descriptor.idProduct) == PRODUCT_ID_CYPHIDCOM_FRWD));
+}
 
 static int analyze_baud_rate(struct usb_serial_port *port, speed_t new_rate)
 {
@@ -238,6 +246,10 @@ static int analyze_baud_rate(struct usb_serial_port *port, speed_t new_rate)
         if (unstable_bauds)
                 return new_rate;
 
+        /* FRWD Dongle uses 115200 bps */
+        if (is_frwd(port->serial->dev))
+                return new_rate;
+
         /*
          * The general purpose firmware for the Cypress M8 allows for
          * a maximum speed of 57600bps (I have no idea whether DeLorme
@@ -448,7 +460,11 @@ static int cypress_generic_port_probe(struct usb_serial_port *port)
                 return -ENOMEM;
         }
 
-        usb_reset_configuration(serial->dev);
+        /* Skip reset for FRWD device. It is a workaound:
+           device hangs if it receives SET_CONFIGURE in Configured
+           state. */
+        if (!is_frwd(serial->dev))
+                usb_reset_configuration(serial->dev);
 
         priv->cmd_ctrl = 0;
         priv->line_control = 0;
diff --git a/drivers/usb/serial/cypress_m8.h b/drivers/usb/serial/cypress_m8.h
index 67cf60826884..b461311a2ae7 100644
--- a/drivers/usb/serial/cypress_m8.h
+++ b/drivers/usb/serial/cypress_m8.h
@@ -24,6 +24,10 @@
 #define VENDOR_ID_CYPRESS               0x04b4
 #define PRODUCT_ID_CYPHIDCOM            0x5500
 
+/* FRWD Dongle - a GPS sports watch */
+#define VENDOR_ID_FRWD                  0x6737
+#define PRODUCT_ID_CYPHIDCOM_FRWD       0x0001
+
 /* Powercom UPS, chip CY7C63723 */
 #define VENDOR_ID_POWERCOM              0x0d9f
 #define PRODUCT_ID_UPS                  0x0002
diff --git a/drivers/usb/serial/f81232.c b/drivers/usb/serial/f81232.c
index 090b411d893f..7d8dd5aad236 100644
--- a/drivers/usb/serial/f81232.c
+++ b/drivers/usb/serial/f81232.c
@@ -165,11 +165,12 @@ static void f81232_set_termios(struct tty_struct *tty,
         /* FIXME - Stubbed out for now */
 
         /* Don't change anything if nothing has changed */
-        if (!tty_termios_hw_change(&tty->termios, old_termios))
+        if (old_termios && !tty_termios_hw_change(&tty->termios, old_termios))
                 return;
 
         /* Do the real work here... */
-        tty_termios_copy_hw(&tty->termios, old_termios);
+        if (old_termios)
+                tty_termios_copy_hw(&tty->termios, old_termios);
 }
 
 static int f81232_tiocmget(struct tty_struct *tty)
@@ -187,12 +188,11 @@ static int f81232_tiocmset(struct tty_struct *tty,
 
 static int f81232_open(struct tty_struct *tty, struct usb_serial_port *port)
 {
-        struct ktermios tmp_termios;
         int result;
 
         /* Setup termios */
         if (tty)
-                f81232_set_termios(tty, port, &tmp_termios);
+                f81232_set_termios(tty, port, NULL);
 
         result = usb_submit_urb(port->interrupt_in_urb, GFP_KERNEL);
         if (result) {
diff --git a/drivers/usb/serial/iuu_phoenix.c b/drivers/usb/serial/iuu_phoenix.c
index 9d74c278b7b5..790673e5faa7 100644
--- a/drivers/usb/serial/iuu_phoenix.c
+++ b/drivers/usb/serial/iuu_phoenix.c
@@ -287,7 +287,7 @@ static int bulk_immediate(struct usb_serial_port *port, u8 *buf, u8 count)
             usb_bulk_msg(serial->dev,
                          usb_sndbulkpipe(serial->dev,
                                          port->bulk_out_endpointAddress), buf,
-                         count, &actual, HZ * 1);
+                         count, &actual, 1000);
 
         if (status != IUU_OPERATION_OK)
                 dev_dbg(&port->dev, "%s - error = %2x\n", __func__, status);
@@ -307,7 +307,7 @@ static int read_immediate(struct usb_serial_port *port, u8 *buf, u8 count)
             usb_bulk_msg(serial->dev,
                          usb_rcvbulkpipe(serial->dev,
                                          port->bulk_in_endpointAddress), buf,
-                         count, &actual, HZ * 1);
+                         count, &actual, 1000);
 
         if (status != IUU_OPERATION_OK)
                 dev_dbg(&port->dev, "%s - error = %2x\n", __func__, status);
diff --git a/drivers/usb/serial/keyspan.c b/drivers/usb/serial/keyspan.c
index eb30d7b01f36..3549d073df22 100644
--- a/drivers/usb/serial/keyspan.c
+++ b/drivers/usb/serial/keyspan.c
@@ -1548,7 +1548,6 @@ static int keyspan_usa26_send_setup(struct usb_serial *serial,
         struct keyspan_serial_private           *s_priv;
         struct keyspan_port_private             *p_priv;
         const struct keyspan_device_details     *d_details;
-        int                                     outcont_urb;
         struct urb                              *this_urb;
         int                                     device_port, err;
 
@@ -1559,7 +1558,6 @@ static int keyspan_usa26_send_setup(struct usb_serial *serial,
         d_details = s_priv->device_details;
         device_port = port->number - port->serial->minor;
 
-        outcont_urb = d_details->outcont_endpoints[port->number];
         this_urb = p_priv->outcont_urb;
 
         dev_dbg(&port->dev, "%s - endpoint %d\n", __func__, usb_pipeendpoint(this_urb->pipe));
@@ -1685,14 +1683,6 @@ static int keyspan_usa26_send_setup(struct usb_serial *serial,
         err = usb_submit_urb(this_urb, GFP_ATOMIC);
         if (err != 0)
                 dev_dbg(&port->dev, "%s - usb_submit_urb(setup) failed (%d)\n", __func__, err);
-#if 0
-        else {
-                dev_dbg(&port->dev, "%s - usb_submit_urb(%d) OK %d bytes (end %d)\n", __func__
-                        outcont_urb, this_urb->transfer_buffer_length,
-                        usb_pipeendpoint(this_urb->pipe));
-        }
-#endif
-
         return 0;
 }
 
diff --git a/drivers/usb/serial/mos7720.c b/drivers/usb/serial/mos7720.c
index cc0e54345df9..f27c621a9297 100644
--- a/drivers/usb/serial/mos7720.c
+++ b/drivers/usb/serial/mos7720.c
@@ -40,7 +40,7 @@
 #define DRIVER_DESC "Moschip USB Serial Driver"
 
 /* default urb timeout */
-#define MOS_WDR_TIMEOUT (HZ * 5)
+#define MOS_WDR_TIMEOUT 5000
 
 #define MOS_MAX_PORT    0x02
 #define MOS_WRITE       0x0E
@@ -227,11 +227,22 @@ static int read_mos_reg(struct usb_serial *serial, unsigned int serial_portnum,
         __u8 requesttype = (__u8)0xc0;
         __u16 index = get_reg_index(reg);
         __u16 value = get_reg_value(reg, serial_portnum);
-        int status = usb_control_msg(usbdev, pipe, request, requesttype, value,
-                                     index, data, 1, MOS_WDR_TIMEOUT);
-        if (status < 0)
+        u8 *buf;
+        int status;
+
+        buf = kmalloc(1, GFP_KERNEL);
+        if (!buf)
+                return -ENOMEM;
+
+        status = usb_control_msg(usbdev, pipe, request, requesttype, value,
+                                     index, buf, 1, MOS_WDR_TIMEOUT);
+        if (status == 1)
+                *data = *buf;
+        else if (status < 0)
                 dev_err(&usbdev->dev,
                         "mos7720: usb_control_msg() failed: %d", status);
+        kfree(buf);
+
         return status;
 }
 
@@ -1618,7 +1629,7 @@ static void change_port_settings(struct tty_struct *tty,
                 mos7720_port->shadowMCR |= (UART_MCR_XONANY);
                 /* To set hardware flow control to the specified *
                  * serial port, in SP1/2_CONTROL_REG             */
-                if (port->number)
+                if (port_number)
                         write_mos_reg(serial, dummy, SP_CONTROL_REG, 0x01);
                 else
                         write_mos_reg(serial, dummy, SP_CONTROL_REG, 0x02);
@@ -1927,7 +1938,7 @@ static int mos7720_startup(struct usb_serial *serial)
 
         /* setting configuration feature to one */
         usb_control_msg(serial->dev, usb_sndctrlpipe(serial->dev, 0),
-                        (__u8)0x03, 0x00, 0x01, 0x00, NULL, 0x00, 5*HZ);
+                        (__u8)0x03, 0x00, 0x01, 0x00, NULL, 0x00, 5000);
 
         /* start the interrupt urb */
         ret_val = usb_submit_urb(serial->port[0]->interrupt_in_urb, GFP_KERNEL);
@@ -1970,7 +1981,7 @@ static void mos7720_release(struct usb_serial *serial)
                 /* wait for synchronous usb calls to return */
                 if (mos_parport->msg_pending)
                         wait_for_completion_timeout(&mos_parport->syncmsg_compl,
-                                                    MOS_WDR_TIMEOUT);
+                                            msecs_to_jiffies(MOS_WDR_TIMEOUT));
 
                 parport_remove_port(mos_parport->pp);
                 usb_set_serial_data(serial, NULL);
diff --git a/drivers/usb/serial/mos7840.c b/drivers/usb/serial/mos7840.c
index a0d5ea545982..7e998081e1cd 100644
--- a/drivers/usb/serial/mos7840.c
+++ b/drivers/usb/serial/mos7840.c
@@ -2142,13 +2142,21 @@ static int mos7840_ioctl(struct tty_struct *tty,
 static int mos7810_check(struct usb_serial *serial)
 {
         int i, pass_count = 0;
+        u8 *buf;
         __u16 data = 0, mcr_data = 0;
         __u16 test_pattern = 0x55AA;
+        int res;
+
+        buf = kmalloc(VENDOR_READ_LENGTH, GFP_KERNEL);
+        if (!buf)
+                return 0;       /* failed to identify 7810 */
 
         /* Store MCR setting */
-        usb_control_msg(serial->dev, usb_rcvctrlpipe(serial->dev, 0),
+        res = usb_control_msg(serial->dev, usb_rcvctrlpipe(serial->dev, 0),
                 MCS_RDREQ, MCS_RD_RTYPE, 0x0300, MODEM_CONTROL_REGISTER,
-                &mcr_data, VENDOR_READ_LENGTH, MOS_WDR_TIMEOUT);
+                buf, VENDOR_READ_LENGTH, MOS_WDR_TIMEOUT);
+        if (res == VENDOR_READ_LENGTH)
+                mcr_data = *buf;
 
         for (i = 0; i < 16; i++) {
                 /* Send the 1-bit test pattern out to MCS7810 test pin */
@@ -2158,9 +2166,12 @@ static int mos7810_check(struct usb_serial *serial)
                         MODEM_CONTROL_REGISTER, NULL, 0, MOS_WDR_TIMEOUT);
 
                 /* Read the test pattern back */
-                usb_control_msg(serial->dev, usb_rcvctrlpipe(serial->dev, 0),
-                        MCS_RDREQ, MCS_RD_RTYPE, 0, GPIO_REGISTER, &data,
-                        VENDOR_READ_LENGTH, MOS_WDR_TIMEOUT);
+                res = usb_control_msg(serial->dev,
+                                usb_rcvctrlpipe(serial->dev, 0), MCS_RDREQ,
+                                MCS_RD_RTYPE, 0, GPIO_REGISTER, buf,
+                                VENDOR_READ_LENGTH, MOS_WDR_TIMEOUT);
+                if (res == VENDOR_READ_LENGTH)
+                        data = *buf;
 
                 /* If this is a MCS7810 device, both test patterns must match */
                 if (((test_pattern >> i) ^ (~data >> 1)) & 0x0001)
@@ -2174,6 +2185,8 @@ static int mos7810_check(struct usb_serial *serial)
                 MCS_WR_RTYPE, 0x0300 | mcr_data, MODEM_CONTROL_REGISTER, NULL,
                 0, MOS_WDR_TIMEOUT);
 
+        kfree(buf);
+
         if (pass_count == 16)
                 return 1;
 
@@ -2183,11 +2196,17 @@ static int mos7810_check(struct usb_serial *serial)
 static int mos7840_calc_num_ports(struct usb_serial *serial)
 {
         __u16 data = 0x00;
+        u8 *buf;
         int mos7840_num_ports;
 
-        usb_control_msg(serial->dev, usb_rcvctrlpipe(serial->dev, 0),
-                MCS_RDREQ, MCS_RD_RTYPE, 0, GPIO_REGISTER, &data,
-                VENDOR_READ_LENGTH, MOS_WDR_TIMEOUT);
+        buf = kzalloc(VENDOR_READ_LENGTH, GFP_KERNEL);
+        if (buf) {
+                usb_control_msg(serial->dev, usb_rcvctrlpipe(serial->dev, 0),
+                        MCS_RDREQ, MCS_RD_RTYPE, 0, GPIO_REGISTER, buf,
+                        VENDOR_READ_LENGTH, MOS_WDR_TIMEOUT);
+                data = *buf;
+                kfree(buf);
+        }
 
         if (serial->dev->descriptor.idProduct == MOSCHIP_DEVICE_ID_7810 ||
                 serial->dev->descriptor.idProduct == MOSCHIP_DEVICE_ID_7820) {
diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
index 93d02bc4eb52..bd4323ddae1a 100644
--- a/drivers/usb/serial/option.c
+++ b/drivers/usb/serial/option.c
@@ -250,13 +250,7 @@ static void option_instat_callback(struct urb *urb);
 #define ZTE_PRODUCT_MF622                       0x0001
 #define ZTE_PRODUCT_MF628                       0x0015
 #define ZTE_PRODUCT_MF626                       0x0031
-#define ZTE_PRODUCT_CDMA_TECH                   0xfffe
-#define ZTE_PRODUCT_AC8710                      0xfff1
-#define ZTE_PRODUCT_AC2726                      0xfff5
-#define ZTE_PRODUCT_AC8710T                     0xffff
 #define ZTE_PRODUCT_MC2718                      0xffe8
-#define ZTE_PRODUCT_AD3812                      0xffeb
-#define ZTE_PRODUCT_MC2716                      0xffed
 
 #define BENQ_VENDOR_ID                          0x04a5
 #define BENQ_PRODUCT_H10                        0x4068
@@ -495,18 +489,10 @@ static const struct option_blacklist_info zte_k3765_z_blacklist = {
         .reserved = BIT(4),
 };
 
-static const struct option_blacklist_info zte_ad3812_z_blacklist = {
-        .sendsetup = BIT(0) | BIT(1) | BIT(2),
-};
-
 static const struct option_blacklist_info zte_mc2718_z_blacklist = {
         .sendsetup = BIT(1) | BIT(2) | BIT(3) | BIT(4),
 };
 
-static const struct option_blacklist_info zte_mc2716_z_blacklist = {
-        .sendsetup = BIT(1) | BIT(2) | BIT(3),
-};
-
 static const struct option_blacklist_info huawei_cdc12_blacklist = {
         .reserved = BIT(1) | BIT(2),
 };
@@ -593,6 +579,8 @@ static const struct usb_device_id option_ids[] = {
                 .driver_info = (kernel_ulong_t) &huawei_cdc12_blacklist },
         { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_K3765, 0xff, 0xff, 0xff),
                 .driver_info = (kernel_ulong_t) &huawei_cdc12_blacklist },
+        { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, 0x14ac, 0xff, 0xff, 0xff),    /* Huawei E1820 */
+                .driver_info = (kernel_ulong_t) &net_intf1_blacklist },
         { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_K4605, 0xff, 0xff, 0xff),
                 .driver_info = (kernel_ulong_t) &huawei_cdc12_blacklist },
         { USB_VENDOR_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, 0xff, 0xff, 0xff) },
@@ -797,7 +785,6 @@ static const struct usb_device_id option_ids[] = {
         { USB_DEVICE_INTERFACE_CLASS(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_1012, 0xff) },
         { USB_DEVICE(KYOCERA_VENDOR_ID, KYOCERA_PRODUCT_KPC650) },
         { USB_DEVICE(KYOCERA_VENDOR_ID, KYOCERA_PRODUCT_KPC680) },
-        { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x6000)}, /* ZTE AC8700 */
         { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x6613)}, /* Onda H600/ZTE MF330 */
         { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000)}, /* SIMCom SIM5218 */
         { USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_6280) }, /* BP3-USB & BP3-EXT HSDPA */
@@ -1199,16 +1186,9 @@ static const struct usb_device_id option_ids[] = {
         { USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0178, 0xff, 0xff, 0xff),
                 .driver_info = (kernel_ulong_t)&net_intf3_blacklist },
 
-        { USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_CDMA_TECH, 0xff, 0xff, 0xff) },
-        { USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_AC8710, 0xff, 0xff, 0xff) },
-        { USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_AC2726, 0xff, 0xff, 0xff) },
-        { USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_AC8710T, 0xff, 0xff, 0xff) },
+        /* NOTE: most ZTE CDMA devices should be driven by zte_ev, not option */
         { USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_MC2718, 0xff, 0xff, 0xff),
          .driver_info = (kernel_ulong_t)&zte_mc2718_z_blacklist },
-        { USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_AD3812, 0xff, 0xff, 0xff),
-         .driver_info = (kernel_ulong_t)&zte_ad3812_z_blacklist },
-        { USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_MC2716, 0xff, 0xff, 0xff),
-         .driver_info = (kernel_ulong_t)&zte_mc2716_z_blacklist },
         { USB_VENDOR_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff, 0x02, 0x01) },
         { USB_VENDOR_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff, 0x02, 0x05) },
         { USB_VENDOR_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff, 0x86, 0x10) },
diff --git a/drivers/usb/serial/pl2303.c b/drivers/usb/serial/pl2303.c
index 7151659367a0..048cd44d51b1 100644
--- a/drivers/usb/serial/pl2303.c
+++ b/drivers/usb/serial/pl2303.c
@@ -284,7 +284,7 @@ static void pl2303_set_termios(struct tty_struct *tty,
            serial settings even to the same values as before. Thus
            we actually need to filter in this specific case */
 
-        if (!tty_termios_hw_change(&tty->termios, old_termios))
+        if (old_termios && !tty_termios_hw_change(&tty->termios, old_termios))
                 return;
 
         cflag = tty->termios.c_cflag;
@@ -293,7 +293,8 @@ static void pl2303_set_termios(struct tty_struct *tty,
         if (!buf) {
                 dev_err(&port->dev, "%s - out of memory.\n", __func__);
                 /* Report back no change occurred */
-                tty->termios = *old_termios;
+                if (old_termios)
+                        tty->termios = *old_termios;
                 return;
         }
 
@@ -433,7 +434,7 @@ static void pl2303_set_termios(struct tty_struct *tty,
         control = priv->line_control;
         if ((cflag & CBAUD) == B0)
                 priv->line_control &= ~(CONTROL_DTR | CONTROL_RTS);
-        else if ((old_termios->c_cflag & CBAUD) == B0)
+        else if (old_termios && (old_termios->c_cflag & CBAUD) == B0)
                 priv->line_control |= (CONTROL_DTR | CONTROL_RTS);
         if (control != priv->line_control) {
                 control = priv->line_control;
@@ -492,7 +493,6 @@ static void pl2303_close(struct usb_serial_port *port)
 
 static int pl2303_open(struct tty_struct *tty, struct usb_serial_port *port)
 {
-        struct ktermios tmp_termios;
         struct usb_serial *serial = port->serial;
         struct pl2303_serial_private *spriv = usb_get_serial_data(serial);
         int result;
@@ -508,7 +508,7 @@ static int pl2303_open(struct tty_struct *tty, struct usb_serial_port *port)
 
         /* Setup termios */
         if (tty)
-                pl2303_set_termios(tty, port, &tmp_termios);
+                pl2303_set_termios(tty, port, NULL);
 
         result = usb_submit_urb(port->interrupt_in_urb, GFP_KERNEL);
         if (result) {
diff --git a/drivers/usb/serial/qcserial.c b/drivers/usb/serial/qcserial.c
index 59b32b782126..bd794b43898c 100644
--- a/drivers/usb/serial/qcserial.c
+++ b/drivers/usb/serial/qcserial.c
@@ -118,6 +118,7 @@ static const struct usb_device_id id_table[] = {
         {USB_DEVICE(0x1199, 0x901b)},   /* Sierra Wireless MC7770 */
         {USB_DEVICE(0x12D1, 0x14F0)},   /* Sony Gobi 3000 QDL */
         {USB_DEVICE(0x12D1, 0x14F1)},   /* Sony Gobi 3000 Composite */
+        {USB_DEVICE(0x0AF0, 0x8120)},   /* Option GTM681W */
 
         /* non Gobi Qualcomm serial devices */
         {USB_DEVICE_INTERFACE_NUMBER(0x0f3d, 0x68a2, 0)},       /* Sierra Wireless MC7700 Device Management */
diff --git a/drivers/usb/serial/spcp8x5.c b/drivers/usb/serial/spcp8x5.c
index cf3df793c2b7..ddf6c47137dc 100644
--- a/drivers/usb/serial/spcp8x5.c
+++ b/drivers/usb/serial/spcp8x5.c
@@ -291,7 +291,6 @@ static void spcp8x5_set_termios(struct tty_struct *tty,
         struct spcp8x5_private *priv = usb_get_serial_port_data(port);
         unsigned long flags;
         unsigned int cflag = tty->termios.c_cflag;
-        unsigned int old_cflag = old_termios->c_cflag;
         unsigned short uartdata;
         unsigned char buf[2] = {0, 0};
         int baud;
@@ -299,15 +298,15 @@ static void spcp8x5_set_termios(struct tty_struct *tty,
         u8 control;
 
         /* check that they really want us to change something */
-        if (!tty_termios_hw_change(&tty->termios, old_termios))
+        if (old_termios && !tty_termios_hw_change(&tty->termios, old_termios))
                 return;
 
         /* set DTR/RTS active */
         spin_lock_irqsave(&priv->lock, flags);
         control = priv->line_control;
-        if ((old_cflag & CBAUD) == B0) {
+        if (old_termios && (old_termios->c_cflag & CBAUD) == B0) {
                 priv->line_control |= MCR_DTR;
-                if (!(old_cflag & CRTSCTS))
+                if (!(old_termios->c_cflag & CRTSCTS))
                         priv->line_control |= MCR_RTS;
         }
         if (control != priv->line_control) {
@@ -394,7 +393,6 @@ static void spcp8x5_set_termios(struct tty_struct *tty,
 
 static int spcp8x5_open(struct tty_struct *tty, struct usb_serial_port *port)
 {
-        struct ktermios tmp_termios;
         struct usb_serial *serial = port->serial;
         struct spcp8x5_private *priv = usb_get_serial_port_data(port);
         int ret;
@@ -411,7 +409,7 @@ static int spcp8x5_open(struct tty_struct *tty, struct usb_serial_port *port)
         spcp8x5_set_ctrl_line(port, priv->line_control);
 
         if (tty)
-                spcp8x5_set_termios(tty, port, &tmp_termios);
+                spcp8x5_set_termios(tty, port, NULL);
 
         port->port.drain_delay = 256;
 
diff --git a/drivers/usb/serial/usb-serial.c b/drivers/usb/serial/usb-serial.c
index 4753c005cfb6..5f6b1ff9d29e 100644
--- a/drivers/usb/serial/usb-serial.c
+++ b/drivers/usb/serial/usb-serial.c
@@ -408,7 +408,7 @@ static int serial_ioctl(struct tty_struct *tty,
                                         unsigned int cmd, unsigned long arg)
 {
         struct usb_serial_port *port = tty->driver_data;
-        int retval = -ENODEV;
+        int retval = -ENOIOCTLCMD;
 
         dev_dbg(tty->dev, "%s - cmd 0x%.4x\n", __func__, cmd);
 
@@ -420,8 +420,6 @@ static int serial_ioctl(struct tty_struct *tty,
         default:
                 if (port->serial->type->ioctl)
                         retval = port->serial->type->ioctl(tty, cmd, arg);
-                else
-                        retval = -ENOIOCTLCMD;
         }
 
         return retval;
diff --git a/drivers/usb/serial/visor.c b/drivers/usb/serial/visor.c
index 7573ec8a084f..9910aa2edf4b 100644
--- a/drivers/usb/serial/visor.c
+++ b/drivers/usb/serial/visor.c
@@ -560,10 +560,19 @@ static int treo_attach(struct usb_serial *serial)
         */
 #define COPY_PORT(dest, src)                                            \
         do { \
+                int i;                                                  \
+                                                                        \
+                for (i = 0; i < ARRAY_SIZE(src->read_urbs); ++i) {      \
+                        dest->read_urbs[i] = src->read_urbs[i];         \
+                        dest->read_urbs[i]->context = dest;             \
+                        dest->bulk_in_buffers[i] = src->bulk_in_buffers[i]; \
+                }                                                       \
                 dest->read_urb = src->read_urb;                         \
                 dest->bulk_in_endpointAddress = src->bulk_in_endpointAddress;\
                 dest->bulk_in_buffer = src->bulk_in_buffer;             \
+                dest->bulk_in_size = src->bulk_in_size;                 \
                 dest->interrupt_in_urb = src->interrupt_in_urb;         \
+                dest->interrupt_in_urb->context = dest;                 \
                 dest->interrupt_in_endpointAddress = \
                                         src->interrupt_in_endpointAddress;\
                 dest->interrupt_in_buffer = src->interrupt_in_buffer;   \
diff --git a/drivers/usb/serial/whiteheat.c b/drivers/usb/serial/whiteheat.c
index b9fca3586d74..347caad47a12 100644
--- a/drivers/usb/serial/whiteheat.c
+++ b/drivers/usb/serial/whiteheat.c
@@ -649,7 +649,7 @@ static void firm_setup_port(struct tty_struct *tty)
         struct whiteheat_port_settings port_settings;
         unsigned int cflag = tty->termios.c_cflag;
 
-        port_settings.port = port->number + 1;
+        port_settings.port = port->number - port->serial->minor + 1;
 
         /* get the byte size */
         switch (cflag & CSIZE) {
diff --git a/drivers/usb/serial/zte_ev.c b/drivers/usb/serial/zte_ev.c
index 39ee7373b4ee..fca4c752a4ed 100644
--- a/drivers/usb/serial/zte_ev.c
+++ b/drivers/usb/serial/zte_ev.c
@@ -41,9 +41,6 @@ static int zte_ev_usb_serial_open(struct tty_struct *tty,
         int len;
         unsigned char *buf;
 
-        if (port->number != 0)
-                return -ENODEV;
-
         buf = kmalloc(MAX_SETUP_DATA_SIZE, GFP_KERNEL);
         if (!buf)
                 return -ENOMEM;
@@ -53,7 +50,7 @@ static int zte_ev_usb_serial_open(struct tty_struct *tty,
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                                  0x22, 0x21,
                                  0x0001, 0x0000, NULL, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         dev_dbg(dev, "result = %d\n", result);
 
         /* send  2st cmd and recieve data */
@@ -65,7 +62,7 @@ static int zte_ev_usb_serial_open(struct tty_struct *tty,
         result = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
                                  0x21, 0xa1,
                                  0x0000, 0x0000, buf, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         debug_data(dev, __func__, len, buf, result);
 
         /* send 3 cmd */
@@ -84,7 +81,7 @@ static int zte_ev_usb_serial_open(struct tty_struct *tty,
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                                  0x20, 0x21,
                                  0x0000, 0x0000, buf, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         debug_data(dev, __func__, len, buf, result);
 
         /* send 4 cmd */
@@ -95,7 +92,7 @@ static int zte_ev_usb_serial_open(struct tty_struct *tty,
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                                  0x22, 0x21,
                                  0x0003, 0x0000, NULL, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         dev_dbg(dev, "result = %d\n", result);
 
         /* send 5 cmd */
@@ -107,7 +104,7 @@ static int zte_ev_usb_serial_open(struct tty_struct *tty,
         result = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
                                  0x21, 0xa1,
                                  0x0000, 0x0000, buf, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         debug_data(dev, __func__, len, buf, result);
 
         /* send 6 cmd */
@@ -126,7 +123,7 @@ static int zte_ev_usb_serial_open(struct tty_struct *tty,
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                                  0x20, 0x21,
                                  0x0000, 0x0000, buf, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         debug_data(dev, __func__, len, buf, result);
         kfree(buf);
 
@@ -166,9 +163,6 @@ static void zte_ev_usb_serial_close(struct usb_serial_port *port)
         int len;
         unsigned char *buf;
 
-        if (port->number != 0)
-                return;
-
         buf = kmalloc(MAX_SETUP_DATA_SIZE, GFP_KERNEL);
         if (!buf)
                 return;
@@ -178,7 +172,7 @@ static void zte_ev_usb_serial_close(struct usb_serial_port *port)
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                                  0x22, 0x21,
                                  0x0002, 0x0000, NULL, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         dev_dbg(dev, "result = %d\n", result);
 
         /* send 2st ctl cmd(CTL    21 22 03 00  00 00 00 00 ) */
@@ -186,7 +180,7 @@ static void zte_ev_usb_serial_close(struct usb_serial_port *port)
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                                  0x22, 0x21,
                                  0x0003, 0x0000, NULL, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         dev_dbg(dev, "result = %d\n", result);
 
         /* send  3st cmd and recieve data */
@@ -198,7 +192,7 @@ static void zte_ev_usb_serial_close(struct usb_serial_port *port)
         result = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
                                  0x21, 0xa1,
                                  0x0000, 0x0000, buf, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         debug_data(dev, __func__, len, buf, result);
 
         /* send 4 cmd */
@@ -217,7 +211,7 @@ static void zte_ev_usb_serial_close(struct usb_serial_port *port)
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                                  0x20, 0x21,
                                  0x0000, 0x0000, buf, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         debug_data(dev, __func__, len, buf, result);
 
         /* send 5 cmd */
@@ -228,7 +222,7 @@ static void zte_ev_usb_serial_close(struct usb_serial_port *port)
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                                  0x22, 0x21,
                                  0x0003, 0x0000, NULL, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         dev_dbg(dev, "result = %d\n", result);
 
         /* send 6 cmd */
@@ -240,7 +234,7 @@ static void zte_ev_usb_serial_close(struct usb_serial_port *port)
         result = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
                                  0x21, 0xa1,
                                  0x0000, 0x0000, buf, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         debug_data(dev, __func__, len, buf, result);
 
         /* send 7 cmd */
@@ -259,7 +253,7 @@ static void zte_ev_usb_serial_close(struct usb_serial_port *port)
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                                  0x20, 0x21,
                                  0x0000, 0x0000, buf, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         debug_data(dev, __func__, len, buf, result);
 
         /* send 8 cmd */
@@ -270,7 +264,7 @@ static void zte_ev_usb_serial_close(struct usb_serial_port *port)
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                                  0x22, 0x21,
                                  0x0003, 0x0000, NULL, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         dev_dbg(dev, "result = %d\n", result);
 
         kfree(buf);
@@ -279,11 +273,29 @@ static void zte_ev_usb_serial_close(struct usb_serial_port *port)
 }
 
 static const struct usb_device_id id_table[] = {
-        { USB_DEVICE(0x19d2, 0xffff) }, /* AC8700 */
-        { USB_DEVICE(0x19d2, 0xfffe) },
-        { USB_DEVICE(0x19d2, 0xfffd) }, /* MG880 */
+        /* AC8710, AC8710T */
+        { USB_DEVICE_AND_INTERFACE_INFO(0x19d2, 0xffff, 0xff, 0xff, 0xff) },
+         /* AC8700 */
+        { USB_DEVICE_AND_INTERFACE_INFO(0x19d2, 0xfffe, 0xff, 0xff, 0xff) },
+        /* MG880 */
+        { USB_DEVICE(0x19d2, 0xfffd) },
+        { USB_DEVICE(0x19d2, 0xfffc) },
+        { USB_DEVICE(0x19d2, 0xfffb) },
+        /* AC2726, AC8710_V3 */
+        { USB_DEVICE_AND_INTERFACE_INFO(0x19d2, 0xfff1, 0xff, 0xff, 0xff) },
+        { USB_DEVICE(0x19d2, 0xfff6) },
+        { USB_DEVICE(0x19d2, 0xfff7) },
+        { USB_DEVICE(0x19d2, 0xfff8) },
+        { USB_DEVICE(0x19d2, 0xfff9) },
+        { USB_DEVICE(0x19d2, 0xffee) },
+        /* AC2716, MC2716 */
+        { USB_DEVICE_AND_INTERFACE_INFO(0x19d2, 0xffed, 0xff, 0xff, 0xff) },
+        /* AD3812 */
+        { USB_DEVICE_AND_INTERFACE_INFO(0x19d2, 0xffeb, 0xff, 0xff, 0xff) },
+        { USB_DEVICE(0x19d2, 0xffec) },
         { USB_DEVICE(0x05C6, 0x3197) },
         { USB_DEVICE(0x05C6, 0x6000) },
+        { USB_DEVICE(0x05C6, 0x9008) },
         { },
 };
 MODULE_DEVICE_TABLE(usb, id_table);
diff --git a/drivers/vfio/vfio.c b/drivers/vfio/vfio.c
index acb7121a9316..6d78736563de 100644
--- a/drivers/vfio/vfio.c
+++ b/drivers/vfio/vfio.c
@@ -1360,7 +1360,7 @@ static const struct file_operations vfio_device_fops = {
  */
 static char *vfio_devnode(struct device *dev, umode_t *mode)
 {
-        if (MINOR(dev->devt) == 0)
+        if (mode && (MINOR(dev->devt) == 0))
                 *mode = S_IRUGO | S_IWUGO;
 
         return kasprintf(GFP_KERNEL, "vfio/%s", dev_name(dev));
diff --git a/drivers/vhost/net.c b/drivers/vhost/net.c
index 2b51e2336aa2..f80d3dd41d8c 100644
--- a/drivers/vhost/net.c
+++ b/drivers/vhost/net.c
@@ -155,14 +155,11 @@ static void vhost_net_ubuf_put_and_wait(struct vhost_net_ubuf_ref *ubufs)
 
 static void vhost_net_clear_ubuf_info(struct vhost_net *n)
 {
-
-        bool zcopy;
         int i;
 
-        for (i = 0; i < n->dev.nvqs; ++i) {
-                zcopy = vhost_net_zcopy_mask & (0x1 << i);
-                if (zcopy)
-                        kfree(n->vqs[i].ubuf_info);
+        for (i = 0; i < VHOST_NET_VQ_MAX; ++i) {
+                kfree(n->vqs[i].ubuf_info);
+                n->vqs[i].ubuf_info = NULL;
         }
 }
 
@@ -171,7 +168,7 @@ int vhost_net_set_ubuf_info(struct vhost_net *n)
         bool zcopy;
         int i;
 
-        for (i = 0; i < n->dev.nvqs; ++i) {
+        for (i = 0; i < VHOST_NET_VQ_MAX; ++i) {
                 zcopy = vhost_net_zcopy_mask & (0x1 << i);
                 if (!zcopy)
                         continue;
@@ -183,12 +180,7 @@ int vhost_net_set_ubuf_info(struct vhost_net *n)
         return 0;
 
 err:
-        while (i--) {
-                zcopy = vhost_net_zcopy_mask & (0x1 << i);
-                if (!zcopy)
-                        continue;
-                kfree(n->vqs[i].ubuf_info);
-        }
+        vhost_net_clear_ubuf_info(n);
         return -ENOMEM;
 }
 
@@ -196,12 +188,12 @@ void vhost_net_vq_reset(struct vhost_net *n)
 {
         int i;
 
+        vhost_net_clear_ubuf_info(n);
+
         for (i = 0; i < VHOST_NET_VQ_MAX; i++) {
                 n->vqs[i].done_idx = 0;
                 n->vqs[i].upend_idx = 0;
                 n->vqs[i].ubufs = NULL;
-                kfree(n->vqs[i].ubuf_info);
-                n->vqs[i].ubuf_info = NULL;
                 n->vqs[i].vhost_hlen = 0;
                 n->vqs[i].sock_hlen = 0;
         }
@@ -436,7 +428,8 @@ static void handle_tx(struct vhost_net *net)
                                 kref_get(&ubufs->kref);
                         }
                         nvq->upend_idx = (nvq->upend_idx + 1) % UIO_MAXIOV;
-                }
+                } else
+                        msg.msg_control = NULL;
                 /* TODO: Check specific error and bomb out unless ENOBUFS? */
                 err = sock->ops->sendmsg(NULL, sock, &msg, len);
                 if (unlikely(err < 0)) {
@@ -1053,6 +1046,10 @@ static long vhost_net_set_owner(struct vhost_net *n)
         int r;
 
         mutex_lock(&n->dev.mutex);
+        if (vhost_dev_has_owner(&n->dev)) {
+                r = -EBUSY;
+                goto out;
+        }
         r = vhost_net_set_ubuf_info(n);
         if (r)
                 goto out;
diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c
index beee7f5787e6..60aa5ad09a2f 100644
--- a/drivers/vhost/vhost.c
+++ b/drivers/vhost/vhost.c
@@ -344,13 +344,19 @@ static int vhost_attach_cgroups(struct vhost_dev *dev)
 }
 
 /* Caller should have device mutex */
+bool vhost_dev_has_owner(struct vhost_dev *dev)
+{
+        return dev->mm;
+}
+
+/* Caller should have device mutex */
 long vhost_dev_set_owner(struct vhost_dev *dev)
 {
         struct task_struct *worker;
         int err;
 
         /* Is there an owner already? */
-        if (dev->mm) {
+        if (vhost_dev_has_owner(dev)) {
                 err = -EBUSY;
                 goto err_mm;
         }
diff --git a/drivers/vhost/vhost.h b/drivers/vhost/vhost.h
index a7ad63592987..64adcf99ff33 100644
--- a/drivers/vhost/vhost.h
+++ b/drivers/vhost/vhost.h
@@ -133,6 +133,7 @@ struct vhost_dev {
 
 long vhost_dev_init(struct vhost_dev *, struct vhost_virtqueue **vqs, int nvqs);
 long vhost_dev_set_owner(struct vhost_dev *dev);
+bool vhost_dev_has_owner(struct vhost_dev *dev);
 long vhost_dev_check_owner(struct vhost_dev *);
 struct vhost_memory *vhost_dev_reset_owner_prepare(void);
 void vhost_dev_reset_owner(struct vhost_dev *, struct vhost_memory *);
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index 540909de6247..effdb373b8db 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -223,8 +223,14 @@ static void init_backlight(struct atmel_lcdfb_info *sinfo)
 
 static void exit_backlight(struct atmel_lcdfb_info *sinfo)
 {
-        if (sinfo->backlight)
-                backlight_device_unregister(sinfo->backlight);
+        if (!sinfo->backlight)
+                return;
+
+        if (sinfo->backlight->ops) {
+                sinfo->backlight->props.power = FB_BLANK_POWERDOWN;
+                sinfo->backlight->ops->update_status(sinfo->backlight);
+        }
+        backlight_device_unregister(sinfo->backlight);
 }
 
 #else
@@ -461,8 +467,11 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
         if (info->fix.smem_len) {
                 unsigned int smem_len = (var->xres_virtual * var->yres_virtual
                                          * ((var->bits_per_pixel + 7) / 8));
-                if (smem_len > info->fix.smem_len)
+                if (smem_len > info->fix.smem_len) {
+                        dev_err(dev, "Frame buffer is too small (%u) for screen size (need at least %u)\n",
+                                info->fix.smem_len, smem_len);
                         return -EINVAL;
+                }
         }
 
         /* Saturate vertical and horizontal timings at maximum values */
diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c
index 60cc6fee6548..c9c2252e3719 100644
--- a/drivers/video/omap2/dss/core.c
+++ b/drivers/video/omap2/dss/core.c
@@ -53,6 +53,8 @@ static char *def_disp_name;
 module_param_named(def_disp, def_disp_name, charp, 0);
 MODULE_PARM_DESC(def_disp, "default display name");
 
+static bool dss_initialized;
+
 const char *omapdss_get_default_display_name(void)
 {
         return core.default_display_name;
@@ -66,6 +68,12 @@ enum omapdss_version omapdss_get_version(void)
 }
 EXPORT_SYMBOL(omapdss_get_version);
 
+bool omapdss_is_initialized(void)
+{
+        return dss_initialized;
+}
+EXPORT_SYMBOL(omapdss_is_initialized);
+
 struct platform_device *dss_get_core_pdev(void)
 {
         return core.pdev;
@@ -603,6 +611,8 @@ static int __init omap_dss_init(void)
                 return r;
         }
 
+        dss_initialized = true;
+
         return 0;
 }
 
@@ -633,7 +643,15 @@ static int __init omap_dss_init(void)
 
 static int __init omap_dss_init2(void)
 {
-        return omap_dss_register_drivers();
+        int r;
+
+        r = omap_dss_register_drivers();
+        if (r)
+                return r;
+
+        dss_initialized = true;
+
+        return 0;
 }
 
 core_initcall(omap_dss_init);
diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
index c84bb8a4d0c4..856917b33616 100644
--- a/drivers/video/omap2/omapfb/omapfb-main.c
+++ b/drivers/video/omap2/omapfb/omapfb-main.c
@@ -2416,6 +2416,9 @@ static int omapfb_probe(struct platform_device *pdev)
 
         DBG("omapfb_probe\n");
 
+        if (omapdss_is_initialized() == false)
+                return -EPROBE_DEFER;
+
         if (pdev->num_resources != 0) {
                 dev_err(&pdev->dev, "probed for an unknown device\n");
                 r = -ENODEV;
diff --git a/drivers/video/ps3fb.c b/drivers/video/ps3fb.c
index d9f08c653d62..dbfe2c18a434 100644
--- a/drivers/video/ps3fb.c
+++ b/drivers/video/ps3fb.c
@@ -710,7 +710,7 @@ static int ps3fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
         r = vm_iomap_memory(vma, info->fix.smem_start, info->fix.smem_len);
 
         dev_dbg(info->device, "ps3fb: mmap framebuffer P(%lx)->V(%lx)\n",
-                info->fix.smem_start + vma->vm_pgoff << PAGE_SHIFT,
+                info->fix.smem_start + (vma->vm_pgoff << PAGE_SHIFT),
                 vma->vm_start);
 
         return r;
diff --git a/drivers/watchdog/coh901327_wdt.c b/drivers/watchdog/coh901327_wdt.c
index b9b8a8be6f12..4bd070f524e5 100644
--- a/drivers/watchdog/coh901327_wdt.c
+++ b/drivers/watchdog/coh901327_wdt.c
@@ -354,9 +354,9 @@ static int __init coh901327_probe(struct platform_device *pdev)
 
         clk_disable(clk);
 
-        if (margin < 1 || margin > 327)
-                margin = 60;
-        coh901327_wdt.timeout = margin;
+        ret = watchdog_init_timeout(&coh901327_wdt, margin, &pdev->dev);
+        if (ret < 0)
+                coh901327_wdt.timeout = 60;
 
         ret = watchdog_register_device(&coh901327_wdt);
         if (ret == 0)
@@ -441,10 +441,16 @@ void coh901327_watchdog_reset(void)
         /* Return and await doom */
 }
 
+static const struct of_device_id coh901327_dt_match[] = {
+        { .compatible = "stericsson,coh901327" },
+        {},
+};
+
 static struct platform_driver coh901327_driver = {
         .driver = {
                 .owner  = THIS_MODULE,
                 .name   = "coh901327_wdog",
+                .of_match_table = coh901327_dt_match,
         },
         .remove         = __exit_p(coh901327_remove),
         .suspend        = coh901327_suspend,
diff --git a/drivers/xen/tmem.c b/drivers/xen/tmem.c
index 18e8bd8fa947..0f0493c63371 100644
--- a/drivers/xen/tmem.c
+++ b/drivers/xen/tmem.c
@@ -41,6 +41,8 @@ module_param(selfballooning, bool, S_IRUGO);
 #ifdef CONFIG_FRONTSWAP
 static bool frontswap __read_mostly = true;
 module_param(frontswap, bool, S_IRUGO);
+#else /* CONFIG_FRONTSWAP */
+#define frontswap (0)
 #endif /* CONFIG_FRONTSWAP */
 
 #ifdef CONFIG_XEN_SELFBALLOONING
@@ -377,10 +379,10 @@ static int xen_tmem_init(void)
 #ifdef CONFIG_FRONTSWAP
         if (tmem_enabled && frontswap) {
                 char *s = "";
-                struct frontswap_ops *old_ops =
-                        frontswap_register_ops(&tmem_frontswap_ops);
+                struct frontswap_ops *old_ops;
 
                 tmem_frontswap_poolid = -1;
+                old_ops = frontswap_register_ops(&tmem_frontswap_ops);
                 if (IS_ERR(old_ops) || old_ops) {
                         if (IS_ERR(old_ops))
                                 return PTR_ERR(old_ops);
diff --git a/drivers/xen/xen-pciback/pci_stub.c b/drivers/xen/xen-pciback/pci_stub.c
index a2278ba7fb27..4e8ba38aa0c9 100644
--- a/drivers/xen/xen-pciback/pci_stub.c
+++ b/drivers/xen/xen-pciback/pci_stub.c
@@ -106,7 +106,7 @@ static void pcistub_device_release(struct kref *kref)
         else
                 pci_restore_state(dev);
 
-        if (pci_find_capability(dev, PCI_CAP_ID_MSIX)) {
+        if (dev->msix_cap) {
                 struct physdev_pci_device ppdev = {
                         .seg = pci_domain_nr(dev->bus),
                         .bus = dev->bus->number,
@@ -371,7 +371,7 @@ static int pcistub_init_device(struct pci_dev *dev)
         if (err)
                 goto config_release;
 
-        if (pci_find_capability(dev, PCI_CAP_ID_MSIX)) {
+        if (dev->msix_cap) {
                 struct physdev_pci_device ppdev = {
                         .seg = pci_domain_nr(dev->bus),
                         .bus = dev->bus->number,
diff --git a/drivers/xen/xenbus/xenbus_client.c b/drivers/xen/xenbus/xenbus_client.c
index 61786be9138b..ec097d6f964d 100644
--- a/drivers/xen/xenbus/xenbus_client.c
+++ b/drivers/xen/xenbus/xenbus_client.c
@@ -534,7 +534,7 @@ static int xenbus_map_ring_valloc_hvm(struct xenbus_device *dev,
 
         err = xenbus_map_ring(dev, gnt_ref, &node->handle, addr);
         if (err)
-                goto out_err;
+                goto out_err_free_ballooned_pages;
 
         spin_lock(&xenbus_valloc_lock);
         list_add(&node->next, &xenbus_valloc_pages);
@@ -543,8 +543,9 @@ static int xenbus_map_ring_valloc_hvm(struct xenbus_device *dev,
         *vaddr = addr;
         return 0;
 
- out_err:
+ out_err_free_ballooned_pages:
         free_xenballooned_pages(1, &node->page);
+ out_err:
         kfree(node);
         return err;
 }
diff --git a/drivers/xen/xenbus/xenbus_comms.h b/drivers/xen/xenbus/xenbus_comms.h
index c8abd3b8a6c4..e74f9c1fbd80 100644
--- a/drivers/xen/xenbus/xenbus_comms.h
+++ b/drivers/xen/xenbus/xenbus_comms.h
@@ -45,6 +45,7 @@ int xb_wait_for_data_to_read(void);
 int xs_input_avail(void);
 extern struct xenstore_domain_interface *xen_store_interface;
 extern int xen_store_evtchn;
+extern enum xenstore_init xen_store_domain_type;
 
 extern const struct file_operations xen_xenbus_fops;
 
diff --git a/drivers/xen/xenbus/xenbus_probe.c b/drivers/xen/xenbus/xenbus_probe.c
index 3325884c693f..56cfaaa9d006 100644
--- a/drivers/xen/xenbus/xenbus_probe.c
+++ b/drivers/xen/xenbus/xenbus_probe.c
@@ -69,6 +69,9 @@ EXPORT_SYMBOL_GPL(xen_store_evtchn);
 struct xenstore_domain_interface *xen_store_interface;
 EXPORT_SYMBOL_GPL(xen_store_interface);
 
+enum xenstore_init xen_store_domain_type;
+EXPORT_SYMBOL_GPL(xen_store_domain_type);
+
 static unsigned long xen_store_mfn;
 
 static BLOCKING_NOTIFIER_HEAD(xenstore_chain);
@@ -719,17 +722,11 @@ static int __init xenstored_local_init(void)
         return err;
 }
 
-enum xenstore_init {
-        UNKNOWN,
-        PV,
-        HVM,
-        LOCAL,
-};
 static int __init xenbus_init(void)
 {
         int err = 0;
-        enum xenstore_init usage = UNKNOWN;
         uint64_t v = 0;
+        xen_store_domain_type = XS_UNKNOWN;
 
         if (!xen_domain())
                 return -ENODEV;
@@ -737,29 +734,29 @@ static int __init xenbus_init(void)
         xenbus_ring_ops_init();
 
         if (xen_pv_domain())
-                usage = PV;
+                xen_store_domain_type = XS_PV;
         if (xen_hvm_domain())
-                usage = HVM;
+                xen_store_domain_type = XS_HVM;
         if (xen_hvm_domain() && xen_initial_domain())
-                usage = LOCAL;
+                xen_store_domain_type = XS_LOCAL;
         if (xen_pv_domain() && !xen_start_info->store_evtchn)
-                usage = LOCAL;
+                xen_store_domain_type = XS_LOCAL;
         if (xen_pv_domain() && xen_start_info->store_evtchn)
                 xenstored_ready = 1;
 
-        switch (usage) {
-        case LOCAL:
+        switch (xen_store_domain_type) {
+        case XS_LOCAL:
                 err = xenstored_local_init();
                 if (err)
                         goto out_error;
                 xen_store_interface = mfn_to_virt(xen_store_mfn);
                 break;
-        case PV:
+        case XS_PV:
                 xen_store_evtchn = xen_start_info->store_evtchn;
                 xen_store_mfn = xen_start_info->store_mfn;
                 xen_store_interface = mfn_to_virt(xen_store_mfn);
                 break;
-        case HVM:
+        case XS_HVM:
                 err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
                 if (err)
                         goto out_error;
diff --git a/drivers/xen/xenbus/xenbus_probe.h b/drivers/xen/xenbus/xenbus_probe.h
index bb4f92ed8730..146f857a36f8 100644
--- a/drivers/xen/xenbus/xenbus_probe.h
+++ b/drivers/xen/xenbus/xenbus_probe.h
@@ -47,6 +47,13 @@ struct xen_bus_type {
         struct bus_type bus;
 };
 
+enum xenstore_init {
+        XS_UNKNOWN,
+        XS_PV,
+        XS_HVM,
+        XS_LOCAL,
+};
+
 extern struct device_attribute xenbus_dev_attrs[];
 
 extern int xenbus_match(struct device *_dev, struct device_driver *_drv);
diff --git a/drivers/xen/xenbus/xenbus_probe_frontend.c b/drivers/xen/xenbus/xenbus_probe_frontend.c
index 3159a37d966d..a7e25073de19 100644
--- a/drivers/xen/xenbus/xenbus_probe_frontend.c
+++ b/drivers/xen/xenbus/xenbus_probe_frontend.c
@@ -29,6 +29,8 @@
 #include "xenbus_probe.h"
 
 
+static struct workqueue_struct *xenbus_frontend_wq;
+
 /* device/<type>/<id> => <type>-<id> */
 static int frontend_bus_id(char bus_id[XEN_BUS_ID_SIZE], const char *nodename)
 {
@@ -89,9 +91,40 @@ static void backend_changed(struct xenbus_watch *watch,
         xenbus_otherend_changed(watch, vec, len, 1);
 }
 
+static void xenbus_frontend_delayed_resume(struct work_struct *w)
+{
+        struct xenbus_device *xdev = container_of(w, struct xenbus_device, work);
+
+        xenbus_dev_resume(&xdev->dev);
+}
+
+static int xenbus_frontend_dev_resume(struct device *dev)
+{
+        /*
+         * If xenstored is running in this domain, we cannot access the backend
+         * state at the moment, so we need to defer xenbus_dev_resume
+         */
+        if (xen_store_domain_type == XS_LOCAL) {
+                struct xenbus_device *xdev = to_xenbus_device(dev);
+
+                if (!xenbus_frontend_wq) {
+                        pr_err("%s: no workqueue to process delayed resume\n",
+                               xdev->nodename);
+                        return -EFAULT;
+                }
+
+                INIT_WORK(&xdev->work, xenbus_frontend_delayed_resume);
+                queue_work(xenbus_frontend_wq, &xdev->work);
+
+                return 0;
+        }
+
+        return xenbus_dev_resume(dev);
+}
+
 static const struct dev_pm_ops xenbus_pm_ops = {
         .suspend        = xenbus_dev_suspend,
-        .resume         = xenbus_dev_resume,
+        .resume         = xenbus_frontend_dev_resume,
         .freeze         = xenbus_dev_suspend,
         .thaw           = xenbus_dev_cancel,
         .restore        = xenbus_dev_resume,
@@ -440,6 +473,8 @@ static int __init xenbus_probe_frontend_init(void)
 
         register_xenstore_notifier(&xenstore_notifier);
 
+        xenbus_frontend_wq = create_workqueue("xenbus_frontend");
+
         return 0;
 }
 subsys_initcall(xenbus_probe_frontend_init);
diff --git a/fs/aio.c b/fs/aio.c
index 7fe5bdee1630..2bbcacf74d0c 100644
--- a/fs/aio.c
+++ b/fs/aio.c
@@ -141,9 +141,6 @@ static void aio_free_ring(struct kioctx *ctx)
         for (i = 0; i < ctx->nr_pages; i++)
                 put_page(ctx->ring_pages[i]);
 
-        if (ctx->mmap_size)
-                vm_munmap(ctx->mmap_base, ctx->mmap_size);
-
         if (ctx->ring_pages && ctx->ring_pages != ctx->internal_pages)
                 kfree(ctx->ring_pages);
 }
@@ -322,11 +319,6 @@ static void free_ioctx(struct kioctx *ctx)
 
         aio_free_ring(ctx);
 
-        spin_lock(&aio_nr_lock);
-        BUG_ON(aio_nr - ctx->max_reqs > aio_nr);
-        aio_nr -= ctx->max_reqs;
-        spin_unlock(&aio_nr_lock);
-
         pr_debug("freeing %p\n", ctx);
 
         /*
@@ -435,17 +427,24 @@ static void kill_ioctx(struct kioctx *ctx)
 {
         if (!atomic_xchg(&ctx->dead, 1)) {
                 hlist_del_rcu(&ctx->list);
-                /* Between hlist_del_rcu() and dropping the initial ref */
-                synchronize_rcu();
 
                 /*
-                 * We can't punt to workqueue here because put_ioctx() ->
-                 * free_ioctx() will unmap the ringbuffer, and that has to be
-                 * done in the original process's context. kill_ioctx_rcu/work()
-                 * exist for exit_aio(), as in that path free_ioctx() won't do
-                 * the unmap.
+                 * It'd be more correct to do this in free_ioctx(), after all
+                 * the outstanding kiocbs have finished - but by then io_destroy
+                 * has already returned, so io_setup() could potentially return
+                 * -EAGAIN with no ioctxs actually in use (as far as userspace
+                 *  could tell).
                  */
-                kill_ioctx_work(&ctx->rcu_work);
+                spin_lock(&aio_nr_lock);
+                BUG_ON(aio_nr - ctx->max_reqs > aio_nr);
+                aio_nr -= ctx->max_reqs;
+                spin_unlock(&aio_nr_lock);
+
+                if (ctx->mmap_size)
+                        vm_munmap(ctx->mmap_base, ctx->mmap_size);
+
+                /* Between hlist_del_rcu() and dropping the initial ref */
+                call_rcu(&ctx->rcu_head, kill_ioctx_rcu);
         }
 }
 
@@ -495,10 +494,7 @@ void exit_aio(struct mm_struct *mm)
                  */
                 ctx->mmap_size = 0;
 
-                if (!atomic_xchg(&ctx->dead, 1)) {
-                        hlist_del_rcu(&ctx->list);
-                        call_rcu(&ctx->rcu_head, kill_ioctx_rcu);
-                }
+                kill_ioctx(ctx);
         }
 }
 
diff --git a/fs/befs/linuxvfs.c b/fs/befs/linuxvfs.c
index 8615ee89ab55..f95dddced968 100644
--- a/fs/befs/linuxvfs.c
+++ b/fs/befs/linuxvfs.c
@@ -265,8 +265,8 @@ befs_readdir(struct file *filp, void *dirent, filldir_t filldir)
                 result = filldir(dirent, keybuf, keysize, filp->f_pos,
                                  (ino_t) value, d_type);
         }
-
-        filp->f_pos++;
+        if (!result)
+                filp->f_pos++;
 
         befs_debug(sb, "<--- befs_readdir() filp->f_pos %Ld", filp->f_pos);
 
diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c
index e7b3cb5286a5..b8b60b660c8f 100644
--- a/fs/btrfs/disk-io.c
+++ b/fs/btrfs/disk-io.c
@@ -2859,8 +2859,8 @@ fail_qgroup:
         btrfs_free_qgroup_config(fs_info);
 fail_trans_kthread:
         kthread_stop(fs_info->transaction_kthread);
-        del_fs_roots(fs_info);
         btrfs_cleanup_transaction(fs_info->tree_root);
+        del_fs_roots(fs_info);
 fail_cleaner:
         kthread_stop(fs_info->cleaner_kthread);
 
@@ -3512,15 +3512,15 @@ int close_ctree(struct btrfs_root *root)
                        percpu_counter_sum(&fs_info->delalloc_bytes));
         }
 
-        free_root_pointers(fs_info, 1);
-
         btrfs_free_block_groups(fs_info);
 
+        btrfs_stop_all_workers(fs_info);
+
         del_fs_roots(fs_info);
 
-        iput(fs_info->btree_inode);
+        free_root_pointers(fs_info, 1);
 
-        btrfs_stop_all_workers(fs_info);
+        iput(fs_info->btree_inode);
 
 #ifdef CONFIG_BTRFS_FS_CHECK_INTEGRITY
         if (btrfs_test_opt(root, CHECK_INTEGRITY))
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index af978f7682b3..17f3064b4a3e 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -8012,6 +8012,9 @@ int btrfs_drop_inode(struct inode *inode)
 {
         struct btrfs_root *root = BTRFS_I(inode)->root;
 
+        if (root == NULL)
+                return 1;
+
         /* the snap/subvol tree is on deleting */
         if (btrfs_root_refs(&root->root_item) == 0 &&
             root != root->fs_info->tree_root)
diff --git a/fs/btrfs/relocation.c b/fs/btrfs/relocation.c
index 395b82031a42..4febca4fc2de 100644
--- a/fs/btrfs/relocation.c
+++ b/fs/btrfs/relocation.c
@@ -4082,7 +4082,7 @@ out:
         return inode;
 }
 
-static struct reloc_control *alloc_reloc_control(void)
+static struct reloc_control *alloc_reloc_control(struct btrfs_fs_info *fs_info)
 {
         struct reloc_control *rc;
 
@@ -4093,7 +4093,8 @@ static struct reloc_control *alloc_reloc_control(void)
         INIT_LIST_HEAD(&rc->reloc_roots);
         backref_cache_init(&rc->backref_cache);
         mapping_tree_init(&rc->reloc_root_tree);
-        extent_io_tree_init(&rc->processed_blocks, NULL);
+        extent_io_tree_init(&rc->processed_blocks,
+                            fs_info->btree_inode->i_mapping);
         return rc;
 }
 
@@ -4110,7 +4111,7 @@ int btrfs_relocate_block_group(struct btrfs_root *extent_root, u64 group_start)
         int rw = 0;
         int err = 0;
 
-        rc = alloc_reloc_control();
+        rc = alloc_reloc_control(fs_info);
         if (!rc)
                 return -ENOMEM;
 
@@ -4311,7 +4312,7 @@ int btrfs_recover_relocation(struct btrfs_root *root)
         if (list_empty(&reloc_roots))
                 goto out;
 
-        rc = alloc_reloc_control();
+        rc = alloc_reloc_control(root->fs_info);
         if (!rc) {
                 err = -ENOMEM;
                 goto out;
diff --git a/fs/ceph/locks.c b/fs/ceph/locks.c
index 202dd3d68be0..ebbf680378e2 100644
--- a/fs/ceph/locks.c
+++ b/fs/ceph/locks.c
@@ -191,27 +191,23 @@ void ceph_count_locks(struct inode *inode, int *fcntl_count, int *flock_count)
 }
 
 /**
- * Encode the flock and fcntl locks for the given inode into the pagelist.
- * Format is: #fcntl locks, sequential fcntl locks, #flock locks,
- * sequential flock locks.
- * Must be called with lock_flocks() already held.
- * If we encounter more of a specific lock type than expected,
- * we return the value 1.
+ * Encode the flock and fcntl locks for the given inode into the ceph_filelock
+ * array. Must be called with lock_flocks() already held.
+ * If we encounter more of a specific lock type than expected, return -ENOSPC.
  */
-int ceph_encode_locks(struct inode *inode, struct ceph_pagelist *pagelist,
-                      int num_fcntl_locks, int num_flock_locks)
+int ceph_encode_locks_to_buffer(struct inode *inode,
+                                struct ceph_filelock *flocks,
+                                int num_fcntl_locks, int num_flock_locks)
 {
         struct file_lock *lock;
-        struct ceph_filelock cephlock;
         int err = 0;
         int seen_fcntl = 0;
         int seen_flock = 0;
+        int l = 0;
 
         dout("encoding %d flock and %d fcntl locks", num_flock_locks,
              num_fcntl_locks);
-        err = ceph_pagelist_append(pagelist, &num_fcntl_locks, sizeof(u32));
-        if (err)
-                goto fail;
+
         for (lock = inode->i_flock; lock != NULL; lock = lock->fl_next) {
                 if (lock->fl_flags & FL_POSIX) {
                         ++seen_fcntl;
@@ -219,19 +215,12 @@ int ceph_encode_locks(struct inode *inode, struct ceph_pagelist *pagelist,
                                 err = -ENOSPC;
                                 goto fail;
                         }
-                        err = lock_to_ceph_filelock(lock, &cephlock);
+                        err = lock_to_ceph_filelock(lock, &flocks[l]);
                         if (err)
                                 goto fail;
-                        err = ceph_pagelist_append(pagelist, &cephlock,
-                                           sizeof(struct ceph_filelock));
+                        ++l;
                 }
-                if (err)
-                        goto fail;
         }
-
-        err = ceph_pagelist_append(pagelist, &num_flock_locks, sizeof(u32));
-        if (err)
-                goto fail;
         for (lock = inode->i_flock; lock != NULL; lock = lock->fl_next) {
                 if (lock->fl_flags & FL_FLOCK) {
                         ++seen_flock;
@@ -239,19 +228,51 @@ int ceph_encode_locks(struct inode *inode, struct ceph_pagelist *pagelist,
                                 err = -ENOSPC;
                                 goto fail;
                         }
-                        err = lock_to_ceph_filelock(lock, &cephlock);
+                        err = lock_to_ceph_filelock(lock, &flocks[l]);
                         if (err)
                                 goto fail;
-                        err = ceph_pagelist_append(pagelist, &cephlock,
-                                           sizeof(struct ceph_filelock));
+                        ++l;
                 }
-                if (err)
-                        goto fail;
         }
 fail:
         return err;
 }
 
+/**
+ * Copy the encoded flock and fcntl locks into the pagelist.
+ * Format is: #fcntl locks, sequential fcntl locks, #flock locks,
+ * sequential flock locks.
+ * Returns zero on success.
+ */
+int ceph_locks_to_pagelist(struct ceph_filelock *flocks,
+                           struct ceph_pagelist *pagelist,
+                           int num_fcntl_locks, int num_flock_locks)
+{
+        int err = 0;
+        __le32 nlocks;
+
+        nlocks = cpu_to_le32(num_fcntl_locks);
+        err = ceph_pagelist_append(pagelist, &nlocks, sizeof(nlocks));
+        if (err)
+                goto out_fail;
+
+        err = ceph_pagelist_append(pagelist, flocks,
+                                   num_fcntl_locks * sizeof(*flocks));
+        if (err)
+                goto out_fail;
+
+        nlocks = cpu_to_le32(num_flock_locks);
+        err = ceph_pagelist_append(pagelist, &nlocks, sizeof(nlocks));
+        if (err)
+                goto out_fail;
+
+        err = ceph_pagelist_append(pagelist,
+                                   &flocks[num_fcntl_locks],
+                                   num_flock_locks * sizeof(*flocks));
+out_fail:
+        return err;
+}
+
 /*
  * Given a pointer to a lock, convert it to a ceph filelock
  */
diff --git a/fs/ceph/mds_client.c b/fs/ceph/mds_client.c
index 4f22671a5bd4..4d2920304be8 100644
--- a/fs/ceph/mds_client.c
+++ b/fs/ceph/mds_client.c
@@ -2478,39 +2478,44 @@ static int encode_caps_cb(struct inode *inode, struct ceph_cap *cap,
 
         if (recon_state->flock) {
                 int num_fcntl_locks, num_flock_locks;
-                struct ceph_pagelist_cursor trunc_point;
-
-                ceph_pagelist_set_cursor(pagelist, &trunc_point);
-                do {
-                        lock_flocks();
-                        ceph_count_locks(inode, &num_fcntl_locks,
-                                         &num_flock_locks);
-                        rec.v2.flock_len = (2*sizeof(u32) +
-                                            (num_fcntl_locks+num_flock_locks) *
-                                            sizeof(struct ceph_filelock));
-                        unlock_flocks();
-
-                        /* pre-alloc pagelist */
-                        ceph_pagelist_truncate(pagelist, &trunc_point);
-                        err = ceph_pagelist_append(pagelist, &rec, reclen);
-                        if (!err)
-                                err = ceph_pagelist_reserve(pagelist,
-                                                            rec.v2.flock_len);
-
-                        /* encode locks */
-                        if (!err) {
-                                lock_flocks();
-                                err = ceph_encode_locks(inode,
-                                                        pagelist,
-                                                        num_fcntl_locks,
-                                                        num_flock_locks);
-                                unlock_flocks();
-                        }
-                } while (err == -ENOSPC);
+                struct ceph_filelock *flocks;
+
+encode_again:
+                lock_flocks();
+                ceph_count_locks(inode, &num_fcntl_locks, &num_flock_locks);
+                unlock_flocks();
+                flocks = kmalloc((num_fcntl_locks+num_flock_locks) *
+                                 sizeof(struct ceph_filelock), GFP_NOFS);
+                if (!flocks) {
+                        err = -ENOMEM;
+                        goto out_free;
+                }
+                lock_flocks();
+                err = ceph_encode_locks_to_buffer(inode, flocks,
+                                                  num_fcntl_locks,
+                                                  num_flock_locks);
+                unlock_flocks();
+                if (err) {
+                        kfree(flocks);
+                        if (err == -ENOSPC)
+                                goto encode_again;
+                        goto out_free;
+                }
+                /*
+                 * number of encoded locks is stable, so copy to pagelist
+                 */
+                rec.v2.flock_len = cpu_to_le32(2*sizeof(u32) +
+                                    (num_fcntl_locks+num_flock_locks) *
+                                    sizeof(struct ceph_filelock));
+                err = ceph_pagelist_append(pagelist, &rec, reclen);
+                if (!err)
+                        err = ceph_locks_to_pagelist(flocks, pagelist,
+                                                     num_fcntl_locks,
+                                                     num_flock_locks);
+                kfree(flocks);
         } else {
                 err = ceph_pagelist_append(pagelist, &rec, reclen);
         }
-
 out_free:
         kfree(path);
 out_dput:
diff --git a/fs/ceph/super.h b/fs/ceph/super.h
index 8696be2ff679..7ccfdb4aea2e 100644
--- a/fs/ceph/super.h
+++ b/fs/ceph/super.h
@@ -822,8 +822,13 @@ extern const struct export_operations ceph_export_ops;
 extern int ceph_lock(struct file *file, int cmd, struct file_lock *fl);
 extern int ceph_flock(struct file *file, int cmd, struct file_lock *fl);
 extern void ceph_count_locks(struct inode *inode, int *p_num, int *f_num);
-extern int ceph_encode_locks(struct inode *i, struct ceph_pagelist *p,
-                             int p_locks, int f_locks);
+extern int ceph_encode_locks_to_buffer(struct inode *inode,
+                                       struct ceph_filelock *flocks,
+                                       int num_fcntl_locks,
+                                       int num_flock_locks);
+extern int ceph_locks_to_pagelist(struct ceph_filelock *flocks,
+                                  struct ceph_pagelist *pagelist,
+                                  int num_fcntl_locks, int num_flock_locks);
 extern int lock_to_ceph_filelock(struct file_lock *fl, struct ceph_filelock *c);
 
 /* debugfs.c */
diff --git a/fs/cifs/cifs_dfs_ref.c b/fs/cifs/cifs_dfs_ref.c
index 8e33ec65847b..58df174deb10 100644
--- a/fs/cifs/cifs_dfs_ref.c
+++ b/fs/cifs/cifs_dfs_ref.c
@@ -18,6 +18,7 @@
 #include <linux/slab.h>
 #include <linux/vfs.h>
 #include <linux/fs.h>
+#include <linux/inet.h>
 #include "cifsglob.h"
 #include "cifsproto.h"
 #include "cifsfs.h"
@@ -48,58 +49,74 @@ void cifs_dfs_release_automount_timer(void)
 }
 
 /**
- * cifs_get_share_name  -       extracts share name from UNC
- * @node_name:  pointer to UNC string
+ * cifs_build_devname - build a devicename from a UNC and optional prepath
+ * @nodename:   pointer to UNC string
+ * @prepath:    pointer to prefixpath (or NULL if there isn't one)
  *
- * Extracts sharename form full UNC.
- * i.e. strips from UNC trailing path that is not part of share
- * name and fixup missing '\' in the beginning of DFS node refferal
- * if necessary.
- * Returns pointer to share name on success or ERR_PTR on error.
- * Caller is responsible for freeing returned string.
+ * Build a new cifs devicename after chasing a DFS referral. Allocate a buffer
+ * big enough to hold the final thing. Copy the UNC from the nodename, and
+ * concatenate the prepath onto the end of it if there is one.
+ *
+ * Returns pointer to the built string, or a ERR_PTR. Caller is responsible
+ * for freeing the returned string.
  */
-static char *cifs_get_share_name(const char *node_name)
+static char *
+cifs_build_devname(char *nodename, const char *prepath)
 {
-        int len;
-        char *UNC;
-        char *pSep;
-
-        len = strlen(node_name);
-        UNC = kmalloc(len+2 /*for term null and additional \ if it's missed */,
-                         GFP_KERNEL);
-        if (!UNC)
-                return ERR_PTR(-ENOMEM);
+        size_t pplen;
+        size_t unclen;
+        char *dev;
+        char *pos;
+
+        /* skip over any preceding delimiters */
+        nodename += strspn(nodename, "\\");
+        if (!*nodename)
+                return ERR_PTR(-EINVAL);
 
-        /* get share name and server name */
-        if (node_name[1] != '\\') {
-                UNC[0] = '\\';
-                strncpy(UNC+1, node_name, len);
-                len++;
-                UNC[len] = 0;
-        } else {
-                strncpy(UNC, node_name, len);
-                UNC[len] = 0;
-        }
+        /* get length of UNC and set pos to last char */
+        unclen = strlen(nodename);
+        pos = nodename + unclen - 1;
 
-        /* find server name end */
-        pSep = memchr(UNC+2, '\\', len-2);
-        if (!pSep) {
-                cifs_dbg(VFS, "%s: no server name end in node name: %s\n",
-                         __func__, node_name);
-                kfree(UNC);
-                return ERR_PTR(-EINVAL);
+        /* trim off any trailing delimiters */
+        while (*pos == '\\') {
+                --pos;
+                --unclen;
         }
 
-        /* find sharename end */
-        pSep++;
-        pSep = memchr(UNC+(pSep-UNC), '\\', len-(pSep-UNC));
-        if (pSep) {
-                /* trim path up to sharename end
-                 * now we have share name in UNC */
-                *pSep = 0;
+        /* allocate a buffer:
+         * +2 for preceding "//"
+         * +1 for delimiter between UNC and prepath
+         * +1 for trailing NULL
+         */
+        pplen = prepath ? strlen(prepath) : 0;
+        dev = kmalloc(2 + unclen + 1 + pplen + 1, GFP_KERNEL);
+        if (!dev)
+                return ERR_PTR(-ENOMEM);
+
+        pos = dev;
+        /* add the initial "//" */
+        *pos = '/';
+        ++pos;
+        *pos = '/';
+        ++pos;
+
+        /* copy in the UNC portion from referral */
+        memcpy(pos, nodename, unclen);
+        pos += unclen;
+
+        /* copy the prefixpath remainder (if there is one) */
+        if (pplen) {
+                *pos = '/';
+                ++pos;
+                memcpy(pos, prepath, pplen);
+                pos += pplen;
         }
 
-        return UNC;
+        /* NULL terminator */
+        *pos = '\0';
+
+        convert_delimiter(dev, '/');
+        return dev;
 }
 
 
@@ -123,6 +140,7 @@ char *cifs_compose_mount_options(const char *sb_mountdata,
 {
         int rc;
         char *mountdata = NULL;
+        const char *prepath = NULL;
         int md_len;
         char *tkn_e;
         char *srvIP = NULL;
@@ -132,7 +150,10 @@ char *cifs_compose_mount_options(const char *sb_mountdata,
         if (sb_mountdata == NULL)
                 return ERR_PTR(-EINVAL);
 
-        *devname = cifs_get_share_name(ref->node_name);
+        if (strlen(fullpath) - ref->path_consumed)
+                prepath = fullpath + ref->path_consumed;
+
+        *devname = cifs_build_devname(ref->node_name, prepath);
         if (IS_ERR(*devname)) {
                 rc = PTR_ERR(*devname);
                 *devname = NULL;
@@ -146,12 +167,14 @@ char *cifs_compose_mount_options(const char *sb_mountdata,
                 goto compose_mount_options_err;
         }
 
-        /* md_len = strlen(...) + 12 for 'sep+prefixpath='
-         * assuming that we have 'unc=' and 'ip=' in
-         * the original sb_mountdata
+        /*
+         * In most cases, we'll be building a shorter string than the original,
+         * but we do have to assume that the address in the ip= option may be
+         * much longer than the original. Add the max length of an address
+         * string to the length of the original string to allow for worst case.
          */
-        md_len = strlen(sb_mountdata) + rc + strlen(ref->node_name) + 12;
-        mountdata = kzalloc(md_len+1, GFP_KERNEL);
+        md_len = strlen(sb_mountdata) + INET6_ADDRSTRLEN;
+        mountdata = kzalloc(md_len + 1, GFP_KERNEL);
         if (mountdata == NULL) {
                 rc = -ENOMEM;
                 goto compose_mount_options_err;
@@ -195,26 +218,6 @@ char *cifs_compose_mount_options(const char *sb_mountdata,
                 strncat(mountdata, &sep, 1);
         strcat(mountdata, "ip=");
         strcat(mountdata, srvIP);
-        strncat(mountdata, &sep, 1);
-        strcat(mountdata, "unc=");
-        strcat(mountdata, *devname);
-
-        /* find & copy prefixpath */
-        tkn_e = strchr(ref->node_name + 2, '\\');
-        if (tkn_e == NULL) {
-                /* invalid unc, missing share name*/
-                rc = -EINVAL;
-                goto compose_mount_options_err;
-        }
-
-        tkn_e = strchr(tkn_e + 1, '\\');
-        if (tkn_e || (strlen(fullpath) - ref->path_consumed)) {
-                strncat(mountdata, &sep, 1);
-                strcat(mountdata, "prefixpath=");
-                if (tkn_e)
-                        strcat(mountdata, tkn_e + 1);
-                strcat(mountdata, fullpath + ref->path_consumed);
-        }
 
         /*cifs_dbg(FYI, "%s: parent mountdata: %s\n", __func__, sb_mountdata);*/
         /*cifs_dbg(FYI, "%s: submount mountdata: %s\n", __func__, mountdata );*/
diff --git a/fs/cifs/cifsfs.c b/fs/cifs/cifsfs.c
index 72e4efee1389..3752b9f6d9e4 100644
--- a/fs/cifs/cifsfs.c
+++ b/fs/cifs/cifsfs.c
@@ -372,9 +372,6 @@ cifs_show_options(struct seq_file *s, struct dentry *root)
         cifs_show_security(s, tcon->ses->server);
         cifs_show_cache_flavor(s, cifs_sb);
 
-        seq_printf(s, ",unc=");
-        seq_escape(s, tcon->treeName, " \t\n\\");
-
         if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_MULTIUSER)
                 seq_printf(s, ",multiuser");
         else if (tcon->ses->user_name)
diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index 99eeaa17ee00..e3bc39bb9d12 100644
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -1061,6 +1061,7 @@ static int cifs_parse_security_flavors(char *value,
 #endif
         case Opt_sec_none:
                 vol->nullauth = 1;
+                vol->secFlg |= CIFSSEC_MAY_NTLM;
                 break;
         default:
                 cifs_dbg(VFS, "bad security option: %s\n", value);
@@ -1257,14 +1258,18 @@ cifs_parse_mount_options(const char *mountdata, const char *devname,
         vol->backupuid_specified = false; /* no backup intent for a user */
         vol->backupgid_specified = false; /* no backup intent for a group */
 
-        /*
-         * For now, we ignore -EINVAL errors under the assumption that the
-         * unc= and prefixpath= options will be usable.
-         */
-        if (cifs_parse_devname(devname, vol) == -ENOMEM) {
-                printk(KERN_ERR "CIFS: Unable to allocate memory to parse "
-                                "device string.\n");
-                goto out_nomem;
+        switch (cifs_parse_devname(devname, vol)) {
+        case 0:
+                break;
+        case -ENOMEM:
+                cifs_dbg(VFS, "Unable to allocate memory for devname.\n");
+                goto cifs_parse_mount_err;
+        case -EINVAL:
+                cifs_dbg(VFS, "Malformed UNC in devname.\n");
+                goto cifs_parse_mount_err;
+        default:
+                cifs_dbg(VFS, "Unknown error parsing devname.\n");
+                goto cifs_parse_mount_err;
         }
 
         while ((data = strsep(&options, separator)) != NULL) {
@@ -1826,7 +1831,7 @@ cifs_parse_mount_options(const char *mountdata, const char *devname,
         }
 #endif
         if (!vol->UNC) {
-                cifs_dbg(VFS, "CIFS mount error: No usable UNC path provided in device string or in unc= option!\n");
+                cifs_dbg(VFS, "CIFS mount error: No usable UNC path provided in device string!\n");
                 goto cifs_parse_mount_err;
         }
 
@@ -3274,8 +3279,8 @@ build_unc_path_to_root(const struct smb_vol *vol,
         pos = full_path + unc_len;
 
         if (pplen) {
-                *pos++ = CIFS_DIR_SEP(cifs_sb);
-                strncpy(pos, vol->prepath, pplen);
+                *pos = CIFS_DIR_SEP(cifs_sb);
+                strncpy(pos + 1, vol->prepath, pplen);
                 pos += pplen;
         }
 
diff --git a/fs/cifs/dns_resolve.c b/fs/cifs/dns_resolve.c
index e7512e497611..7ede7306599f 100644
--- a/fs/cifs/dns_resolve.c
+++ b/fs/cifs/dns_resolve.c
@@ -34,7 +34,7 @@
 
 /**
  * dns_resolve_server_name_to_ip - Resolve UNC server name to ip address.
- * @unc: UNC path specifying the server
+ * @unc: UNC path specifying the server (with '/' as delimiter)
  * @ip_addr: Where to return the IP address.
  *
  * The IP address will be returned in string form, and the caller is
@@ -64,7 +64,7 @@ dns_resolve_server_name_to_ip(const char *unc, char **ip_addr)
         hostname = unc + 2;
 
         /* Search for server name delimiter */
-        sep = memchr(hostname, '\\', len);
+        sep = memchr(hostname, '/', len);
         if (sep)
                 len = sep - hostname;
         else
diff --git a/fs/ecryptfs/file.c b/fs/ecryptfs/file.c
index 201f0a0d6b0a..a7abbea2c096 100644
--- a/fs/ecryptfs/file.c
+++ b/fs/ecryptfs/file.c
@@ -295,6 +295,12 @@ static int ecryptfs_release(struct inode *inode, struct file *file)
 static int
 ecryptfs_fsync(struct file *file, loff_t start, loff_t end, int datasync)
 {
+        int rc;
+
+        rc = filemap_write_and_wait(file->f_mapping);
+        if (rc)
+                return rc;
+
         return vfs_fsync(ecryptfs_file_to_lower(file), datasync);
 }
 
diff --git a/fs/efivarfs/file.c b/fs/efivarfs/file.c
index bfb531564319..8dd524f32284 100644
--- a/fs/efivarfs/file.c
+++ b/fs/efivarfs/file.c
@@ -44,8 +44,11 @@ static ssize_t efivarfs_file_write(struct file *file,
 
         bytes = efivar_entry_set_get_size(var, attributes, &datasize,
                                           data, &set);
-        if (!set && bytes)
+        if (!set && bytes) {
+                if (bytes == -ENOENT)
+                        bytes = -EIO;
                 goto out;
+        }
 
         if (bytes == -ENOENT) {
                 drop_nlink(inode);
@@ -76,7 +79,14 @@ static ssize_t efivarfs_file_read(struct file *file, char __user *userbuf,
         int err;
 
         err = efivar_entry_size(var, &datasize);
-        if (err)
+
+        /*
+         * efivarfs represents uncommitted variables with
+         * zero-length files. Reading them should return EOF.
+         */
+        if (err == -ENOENT)
+                return 0;
+        else if (err)
                 return err;
 
         data = kmalloc(datasize + sizeof(attributes), GFP_KERNEL);
diff --git a/fs/file_table.c b/fs/file_table.c
index cd4d87a82951..485dc0eddd67 100644
--- a/fs/file_table.c
+++ b/fs/file_table.c
@@ -306,17 +306,18 @@ void fput(struct file *file)
 {
         if (atomic_long_dec_and_test(&file->f_count)) {
                 struct task_struct *task = current;
+                unsigned long flags;
+
                 file_sb_list_del(file);
-                if (unlikely(in_interrupt() || task->flags & PF_KTHREAD)) {
-                        unsigned long flags;
-                        spin_lock_irqsave(&delayed_fput_lock, flags);
-                        list_add(&file->f_u.fu_list, &delayed_fput_list);
-                        schedule_work(&delayed_fput_work);
-                        spin_unlock_irqrestore(&delayed_fput_lock, flags);
-                        return;
+                if (likely(!in_interrupt() && !(task->flags & PF_KTHREAD))) {
+                        init_task_work(&file->f_u.fu_rcuhead, ____fput);
+                        if (!task_work_add(task, &file->f_u.fu_rcuhead, true))
+                                return;
                 }
-                init_task_work(&file->f_u.fu_rcuhead, ____fput);
-                task_work_add(task, &file->f_u.fu_rcuhead, true);
+                spin_lock_irqsave(&delayed_fput_lock, flags);
+                list_add(&file->f_u.fu_list, &delayed_fput_list);
+                schedule_work(&delayed_fput_work);
+                spin_unlock_irqrestore(&delayed_fput_lock, flags);
         }
 }
 
diff --git a/fs/fuse/dir.c b/fs/fuse/dir.c
index 254df56b847b..f3f783dc4f75 100644
--- a/fs/fuse/dir.c
+++ b/fs/fuse/dir.c
@@ -180,6 +180,8 @@ u64 fuse_get_attr_version(struct fuse_conn *fc)
 static int fuse_dentry_revalidate(struct dentry *entry, unsigned int flags)
 {
         struct inode *inode;
+        struct dentry *parent;
+        struct fuse_conn *fc;
 
         inode = ACCESS_ONCE(entry->d_inode);
         if (inode && is_bad_inode(inode))
@@ -187,10 +189,8 @@ static int fuse_dentry_revalidate(struct dentry *entry, unsigned int flags)
         else if (fuse_dentry_time(entry) < get_jiffies_64()) {
                 int err;
                 struct fuse_entry_out outarg;
-                struct fuse_conn *fc;
                 struct fuse_req *req;
                 struct fuse_forget_link *forget;
-                struct dentry *parent;
                 u64 attr_version;
 
                 /* For negative dentries, always do a fresh lookup */
@@ -241,8 +241,14 @@ static int fuse_dentry_revalidate(struct dentry *entry, unsigned int flags)
                                        entry_attr_timeout(&outarg),
                                        attr_version);
                 fuse_change_entry_timeout(entry, &outarg);
+        } else if (inode) {
+                fc = get_fuse_conn(inode);
+                if (fc->readdirplus_auto) {
+                        parent = dget_parent(entry);
+                        fuse_advise_use_readdirplus(parent->d_inode);
+                        dput(parent);
+                }
         }
-        fuse_advise_use_readdirplus(inode);
         return 1;
 }
 
diff --git a/fs/fuse/file.c b/fs/fuse/file.c
index d1c9b85b3f58..e570081f9f76 100644
--- a/fs/fuse/file.c
+++ b/fs/fuse/file.c
@@ -16,6 +16,7 @@
 #include <linux/compat.h>
 #include <linux/swap.h>
 #include <linux/aio.h>
+#include <linux/falloc.h>
 
 static const struct file_operations fuse_direct_io_file_operations;
 
@@ -1278,7 +1279,10 @@ ssize_t fuse_direct_io(struct fuse_io_priv *io, const struct iovec *iov,
 
         iov_iter_init(&ii, iov, nr_segs, count, 0);
 
-        req = fuse_get_req(fc, fuse_iter_npages(&ii));
+        if (io->async)
+                req = fuse_get_req_for_background(fc, fuse_iter_npages(&ii));
+        else
+                req = fuse_get_req(fc, fuse_iter_npages(&ii));
         if (IS_ERR(req))
                 return PTR_ERR(req);
 
@@ -1314,7 +1318,11 @@ ssize_t fuse_direct_io(struct fuse_io_priv *io, const struct iovec *iov,
                         break;
                 if (count) {
                         fuse_put_request(fc, req);
-                        req = fuse_get_req(fc, fuse_iter_npages(&ii));
+                        if (io->async)
+                                req = fuse_get_req_for_background(fc,
+                                        fuse_iter_npages(&ii));
+                        else
+                                req = fuse_get_req(fc, fuse_iter_npages(&ii));
                         if (IS_ERR(req))
                                 break;
                 }
@@ -2365,6 +2373,11 @@ static void fuse_do_truncate(struct file *file)
         fuse_do_setattr(inode, &attr, file);
 }
 
+static inline loff_t fuse_round_up(loff_t off)
+{
+        return round_up(off, FUSE_MAX_PAGES_PER_REQ << PAGE_SHIFT);
+}
+
 static ssize_t
 fuse_direct_IO(int rw, struct kiocb *iocb, const struct iovec *iov,
                         loff_t offset, unsigned long nr_segs)
@@ -2372,6 +2385,7 @@ fuse_direct_IO(int rw, struct kiocb *iocb, const struct iovec *iov,
         ssize_t ret = 0;
         struct file *file = iocb->ki_filp;
         struct fuse_file *ff = file->private_data;
+        bool async_dio = ff->fc->async_dio;
         loff_t pos = 0;
         struct inode *inode;
         loff_t i_size;
@@ -2383,10 +2397,10 @@ fuse_direct_IO(int rw, struct kiocb *iocb, const struct iovec *iov,
         i_size = i_size_read(inode);
 
         /* optimization for short read */
-        if (rw != WRITE && offset + count > i_size) {
+        if (async_dio && rw != WRITE && offset + count > i_size) {
                 if (offset >= i_size)
                         return 0;
-                count = i_size - offset;
+                count = min_t(loff_t, count, fuse_round_up(i_size - offset));
         }
 
         io = kmalloc(sizeof(struct fuse_io_priv), GFP_KERNEL);
@@ -2404,7 +2418,7 @@ fuse_direct_IO(int rw, struct kiocb *iocb, const struct iovec *iov,
          * By default, we want to optimize all I/Os with async request
          * submission to the client filesystem if supported.
          */
-        io->async = ff->fc->async_dio;
+        io->async = async_dio;
         io->iocb = iocb;
 
         /*
@@ -2412,7 +2426,7 @@ fuse_direct_IO(int rw, struct kiocb *iocb, const struct iovec *iov,
          * to wait on real async I/O requests, so we must submit this request
          * synchronously.
          */
-        if (!is_sync_kiocb(iocb) && (offset + count > i_size))
+        if (!is_sync_kiocb(iocb) && (offset + count > i_size) && rw == WRITE)
                 io->async = false;
 
         if (rw == WRITE)
@@ -2424,7 +2438,7 @@ fuse_direct_IO(int rw, struct kiocb *iocb, const struct iovec *iov,
                 fuse_aio_complete(io, ret < 0 ? ret : 0, -1);
 
                 /* we have a non-extending, async request, so return */
-                if (ret > 0 && !is_sync_kiocb(iocb))
+                if (!is_sync_kiocb(iocb))
                         return -EIOCBQUEUED;
 
                 ret = wait_on_sync_kiocb(iocb);
@@ -2446,6 +2460,7 @@ static long fuse_file_fallocate(struct file *file, int mode, loff_t offset,
                                 loff_t length)
 {
         struct fuse_file *ff = file->private_data;
+        struct inode *inode = file->f_inode;
         struct fuse_conn *fc = ff->fc;
         struct fuse_req *req;
         struct fuse_fallocate_in inarg = {
@@ -2459,9 +2474,16 @@ static long fuse_file_fallocate(struct file *file, int mode, loff_t offset,
         if (fc->no_fallocate)
                 return -EOPNOTSUPP;
 
+        if (mode & FALLOC_FL_PUNCH_HOLE) {
+                mutex_lock(&inode->i_mutex);
+                fuse_set_nowrite(inode);
+        }
+
         req = fuse_get_req_nopages(fc);
-        if (IS_ERR(req))
-                return PTR_ERR(req);
+        if (IS_ERR(req)) {
+                err = PTR_ERR(req);
+                goto out;
+        }
 
         req->in.h.opcode = FUSE_FALLOCATE;
         req->in.h.nodeid = ff->nodeid;
@@ -2476,6 +2498,24 @@ static long fuse_file_fallocate(struct file *file, int mode, loff_t offset,
         }
         fuse_put_request(fc, req);
 
+        if (err)
+                goto out;
+
+        /* we could have extended the file */
+        if (!(mode & FALLOC_FL_KEEP_SIZE))
+                fuse_write_update_size(inode, offset + length);
+
+        if (mode & FALLOC_FL_PUNCH_HOLE)
+                truncate_pagecache_range(inode, offset, offset + length - 1);
+
+        fuse_invalidate_attr(inode);
+
+out:
+        if (mode & FALLOC_FL_PUNCH_HOLE) {
+                fuse_release_nowrite(inode);
+                mutex_unlock(&inode->i_mutex);
+        }
+
         return err;
 }
 
diff --git a/fs/fuse/inode.c b/fs/fuse/inode.c
index 6201f81e4d3a..9a0cdde14a08 100644
--- a/fs/fuse/inode.c
+++ b/fs/fuse/inode.c
@@ -867,10 +867,11 @@ static void process_init_reply(struct fuse_conn *fc, struct fuse_req *req)
                                 fc->dont_mask = 1;
                         if (arg->flags & FUSE_AUTO_INVAL_DATA)
                                 fc->auto_inval_data = 1;
-                        if (arg->flags & FUSE_DO_READDIRPLUS)
+                        if (arg->flags & FUSE_DO_READDIRPLUS) {
                                 fc->do_readdirplus = 1;
-                        if (arg->flags & FUSE_READDIRPLUS_AUTO)
-                                fc->readdirplus_auto = 1;
+                                if (arg->flags & FUSE_READDIRPLUS_AUTO)
+                                        fc->readdirplus_auto = 1;
+                        }
                         if (arg->flags & FUSE_ASYNC_DIO)
                                 fc->async_dio = 1;
                 } else {
diff --git a/fs/gfs2/bmap.c b/fs/gfs2/bmap.c
index 1dc9a13ce6bb..93b5809c20bb 100644
--- a/fs/gfs2/bmap.c
+++ b/fs/gfs2/bmap.c
@@ -1286,17 +1286,26 @@ int gfs2_setattr_size(struct inode *inode, u64 newsize)
         if (ret)
                 return ret;
 
+        ret = get_write_access(inode);
+        if (ret)
+                return ret;
+
         inode_dio_wait(inode);
 
         ret = gfs2_rs_alloc(GFS2_I(inode));
         if (ret)
-                return ret;
+                goto out;
 
         oldsize = inode->i_size;
-        if (newsize >= oldsize)
-                return do_grow(inode, newsize);
+        if (newsize >= oldsize) {
+                ret = do_grow(inode, newsize);
+                goto out;
+        }
 
-        return do_shrink(inode, oldsize, newsize);
+        ret = do_shrink(inode, oldsize, newsize);
+out:
+        put_write_access(inode);
+        return ret;
 }
 
 int gfs2_truncatei_resume(struct gfs2_inode *ip)
diff --git a/fs/gfs2/dir.c b/fs/gfs2/dir.c
index c3e82bd23179..b631c9043460 100644
--- a/fs/gfs2/dir.c
+++ b/fs/gfs2/dir.c
@@ -354,22 +354,31 @@ static __be64 *gfs2_dir_get_hash_table(struct gfs2_inode *ip)
                 return ERR_PTR(-EIO);
         }
 
-        hc = kmalloc(hsize, GFP_NOFS);
-        ret = -ENOMEM;
+        hc = kmalloc(hsize, GFP_NOFS | __GFP_NOWARN);
+        if (hc == NULL)
+                hc = __vmalloc(hsize, GFP_NOFS, PAGE_KERNEL);
+
         if (hc == NULL)
                 return ERR_PTR(-ENOMEM);
 
         ret = gfs2_dir_read_data(ip, hc, hsize);
         if (ret < 0) {
-                kfree(hc);
+                if (is_vmalloc_addr(hc))
+                        vfree(hc);
+                else
+                        kfree(hc);
                 return ERR_PTR(ret);
         }
 
         spin_lock(&inode->i_lock);
-        if (ip->i_hash_cache)
-                kfree(hc);
-        else
+        if (ip->i_hash_cache) {
+                if (is_vmalloc_addr(hc))
+                        vfree(hc);
+                else
+                        kfree(hc);
+        } else {
                 ip->i_hash_cache = hc;
+        }
         spin_unlock(&inode->i_lock);
 
         return ip->i_hash_cache;
@@ -385,7 +394,10 @@ void gfs2_dir_hash_inval(struct gfs2_inode *ip)
 {
         __be64 *hc = ip->i_hash_cache;
         ip->i_hash_cache = NULL;
-        kfree(hc);
+        if (is_vmalloc_addr(hc))
+                vfree(hc);
+        else
+                kfree(hc);
 }
 
 static inline int gfs2_dirent_sentinel(const struct gfs2_dirent *dent)
@@ -1113,7 +1125,10 @@ static int dir_double_exhash(struct gfs2_inode *dip)
         if (IS_ERR(hc))
                 return PTR_ERR(hc);
 
-        h = hc2 = kmalloc(hsize_bytes * 2, GFP_NOFS);
+        h = hc2 = kmalloc(hsize_bytes * 2, GFP_NOFS | __GFP_NOWARN);
+        if (hc2 == NULL)
+                hc2 = __vmalloc(hsize_bytes * 2, GFP_NOFS, PAGE_KERNEL);
+
         if (!hc2)
                 return -ENOMEM;
 
@@ -1145,7 +1160,10 @@ fail:
         gfs2_dinode_out(dip, dibh->b_data);
         brelse(dibh);
 out_kfree:
-        kfree(hc2);
+        if (is_vmalloc_addr(hc2))
+                vfree(hc2);
+        else
+                kfree(hc2);
         return error;
 }
 
@@ -1846,6 +1864,8 @@ static int leaf_dealloc(struct gfs2_inode *dip, u32 index, u32 len,
         memset(&rlist, 0, sizeof(struct gfs2_rgrp_list));
 
         ht = kzalloc(size, GFP_NOFS);
+        if (ht == NULL)
+                ht = vzalloc(size);
         if (!ht)
                 return -ENOMEM;
 
@@ -1933,7 +1953,10 @@ out_rlist:
         gfs2_rlist_free(&rlist);
         gfs2_quota_unhold(dip);
 out:
-        kfree(ht);
+        if (is_vmalloc_addr(ht))
+                vfree(ht);
+        else
+                kfree(ht);
         return error;
 }
 
diff --git a/fs/gfs2/file.c b/fs/gfs2/file.c
index acd16764b133..ad0dc38d87ab 100644
--- a/fs/gfs2/file.c
+++ b/fs/gfs2/file.c
@@ -402,16 +402,20 @@ static int gfs2_page_mkwrite(struct vm_area_struct *vma, struct vm_fault *vmf)
         /* Update file times before taking page lock */
         file_update_time(vma->vm_file);
 
+        ret = get_write_access(inode);
+        if (ret)
+                goto out;
+
         ret = gfs2_rs_alloc(ip);
         if (ret)
-                return ret;
+                goto out_write_access;
 
         gfs2_size_hint(vma->vm_file, pos, PAGE_CACHE_SIZE);
 
         gfs2_holder_init(ip->i_gl, LM_ST_EXCLUSIVE, 0, &gh);
         ret = gfs2_glock_nq(&gh);
         if (ret)
-                goto out;
+                goto out_uninit;
 
         set_bit(GLF_DIRTY, &ip->i_gl->gl_flags);
         set_bit(GIF_SW_PAGED, &ip->i_flags);
@@ -480,12 +484,15 @@ out_quota_unlock:
         gfs2_quota_unlock(ip);
 out_unlock:
         gfs2_glock_dq(&gh);
-out:
+out_uninit:
         gfs2_holder_uninit(&gh);
         if (ret == 0) {
                 set_page_dirty(page);
                 wait_for_stable_page(page);
         }
+out_write_access:
+        put_write_access(inode);
+out:
         sb_end_pagefault(inode->i_sb);
         return block_page_mkwrite_return(ret);
 }
@@ -594,10 +601,10 @@ static int gfs2_release(struct inode *inode, struct file *file)
         kfree(file->private_data);
         file->private_data = NULL;
 
-        if ((file->f_mode & FMODE_WRITE) &&
-            (atomic_read(&inode->i_writecount) == 1))
-                gfs2_rs_delete(ip);
+        if (!(file->f_mode & FMODE_WRITE))
+                return 0;
 
+        gfs2_rs_delete(ip);
         return 0;
 }
 
diff --git a/fs/gfs2/inode.c b/fs/gfs2/inode.c
index 8833a4f264e3..62b484e4a9e4 100644
--- a/fs/gfs2/inode.c
+++ b/fs/gfs2/inode.c
@@ -189,6 +189,7 @@ struct inode *gfs2_inode_lookup(struct super_block *sb, unsigned int type,
         return inode;
 
 fail_refresh:
+        ip->i_iopen_gh.gh_flags |= GL_NOCACHE;
         ip->i_iopen_gh.gh_gl->gl_object = NULL;
         gfs2_glock_dq_uninit(&ip->i_iopen_gh);
 fail_iopen:
diff --git a/fs/gfs2/lops.c b/fs/gfs2/lops.c
index 68b4c8f1fce8..6c33d7b6e0c4 100644
--- a/fs/gfs2/lops.c
+++ b/fs/gfs2/lops.c
@@ -419,7 +419,9 @@ static void gfs2_before_commit(struct gfs2_sbd *sdp, unsigned int limit,
                 if (total > limit)
                         num = limit;
                 gfs2_log_unlock(sdp);
-                page = gfs2_get_log_desc(sdp, GFS2_LOG_DESC_METADATA, num + 1, num);
+                page = gfs2_get_log_desc(sdp,
+                                         is_databuf ? GFS2_LOG_DESC_JDATA :
+                                         GFS2_LOG_DESC_METADATA, num + 1, num);
                 ld = page_address(page);
                 gfs2_log_lock(sdp);
                 ptr = (__be64 *)(ld + 1);
diff --git a/fs/gfs2/rgrp.c b/fs/gfs2/rgrp.c
index 5232525934ae..9809156e3d04 100644
--- a/fs/gfs2/rgrp.c
+++ b/fs/gfs2/rgrp.c
@@ -638,8 +638,10 @@ void gfs2_rs_deltree(struct gfs2_blkreserv *rs)
  */
 void gfs2_rs_delete(struct gfs2_inode *ip)
 {
+        struct inode *inode = &ip->i_inode;
+
         down_write(&ip->i_rw_mutex);
-        if (ip->i_res) {
+        if (ip->i_res && atomic_read(&inode->i_writecount) <= 1) {
                 gfs2_rs_deltree(ip->i_res);
                 BUG_ON(ip->i_res->rs_free);
                 kmem_cache_free(gfs2_rsrv_cachep, ip->i_res);
diff --git a/fs/gfs2/super.c b/fs/gfs2/super.c
index 917c8e1eb4ae..e5639dec66c4 100644
--- a/fs/gfs2/super.c
+++ b/fs/gfs2/super.c
@@ -1444,6 +1444,7 @@ static void gfs2_evict_inode(struct inode *inode)
         /* Must not read inode block until block type has been verified */
         error = gfs2_glock_nq_init(ip->i_gl, LM_ST_EXCLUSIVE, GL_SKIP, &gh);
         if (unlikely(error)) {
+                ip->i_iopen_gh.gh_flags |= GL_NOCACHE;
                 gfs2_glock_dq_uninit(&ip->i_iopen_gh);
                 goto out;
         }
@@ -1514,8 +1515,10 @@ out_unlock:
         if (gfs2_rs_active(ip->i_res))
                 gfs2_rs_deltree(ip->i_res);
 
-        if (test_bit(HIF_HOLDER, &ip->i_iopen_gh.gh_iflags))
+        if (test_bit(HIF_HOLDER, &ip->i_iopen_gh.gh_iflags)) {
+                ip->i_iopen_gh.gh_flags |= GL_NOCACHE;
                 gfs2_glock_dq(&ip->i_iopen_gh);
+        }
         gfs2_holder_uninit(&ip->i_iopen_gh);
         gfs2_glock_dq_uninit(&gh);
         if (error && error != GLR_TRYFAILED && error != -EROFS)
@@ -1534,6 +1537,7 @@ out:
         ip->i_gl = NULL;
         if (ip->i_iopen_gh.gh_gl) {
                 ip->i_iopen_gh.gh_gl->gl_object = NULL;
+                ip->i_iopen_gh.gh_flags |= GL_NOCACHE;
                 gfs2_glock_dq_uninit(&ip->i_iopen_gh);
         }
 }
diff --git a/fs/hpfs/dir.c b/fs/hpfs/dir.c
index 546f6d39713a..834ac13c04b7 100644
--- a/fs/hpfs/dir.c
+++ b/fs/hpfs/dir.c
@@ -33,25 +33,27 @@ static loff_t hpfs_dir_lseek(struct file *filp, loff_t off, int whence)
         if (whence == SEEK_DATA || whence == SEEK_HOLE)
                 return -EINVAL;
 
+        mutex_lock(&i->i_mutex);
         hpfs_lock(s);
 
         /*printk("dir lseek\n");*/
         if (new_off == 0 || new_off == 1 || new_off == 11 || new_off == 12 || new_off == 13) goto ok;
-        mutex_lock(&i->i_mutex);
         pos = ((loff_t) hpfs_de_as_down_as_possible(s, hpfs_inode->i_dno) << 4) + 1;
         while (pos != new_off) {
                 if (map_pos_dirent(i, &pos, &qbh)) hpfs_brelse4(&qbh);
                 else goto fail;
                 if (pos == 12) goto fail;
         }
-        mutex_unlock(&i->i_mutex);
+        hpfs_add_pos(i, &filp->f_pos);
 ok:
+        filp->f_pos = new_off;
         hpfs_unlock(s);
-        return filp->f_pos = new_off;
-fail:
         mutex_unlock(&i->i_mutex);
+        return new_off;
+fail:
         /*printk("illegal lseek: %016llx\n", new_off);*/
         hpfs_unlock(s);
+        mutex_unlock(&i->i_mutex);
         return -ESPIPE;
 }
 
diff --git a/fs/hpfs/file.c b/fs/hpfs/file.c
index 3027f4dbbab5..e4ba5fe4c3b5 100644
--- a/fs/hpfs/file.c
+++ b/fs/hpfs/file.c
@@ -109,10 +109,14 @@ static void hpfs_write_failed(struct address_space *mapping, loff_t to)
 {
         struct inode *inode = mapping->host;
 
+        hpfs_lock(inode->i_sb);
+
         if (to > inode->i_size) {
                 truncate_pagecache(inode, to, inode->i_size);
                 hpfs_truncate(inode);
         }
+
+        hpfs_unlock(inode->i_sb);
 }
 
 static int hpfs_write_begin(struct file *file, struct address_space *mapping,
diff --git a/fs/jfs/jfs_logmgr.c b/fs/jfs/jfs_logmgr.c
index c57499dca89c..360d27c48887 100644
--- a/fs/jfs/jfs_logmgr.c
+++ b/fs/jfs/jfs_logmgr.c
@@ -2009,7 +2009,13 @@ static int lbmRead(struct jfs_log * log, int pn, struct lbuf ** bpp)
 
         bio->bi_end_io = lbmIODone;
         bio->bi_private = bp;
-        submit_bio(READ_SYNC, bio);
+        /*check if journaling to disk has been disabled*/
+        if (log->no_integrity) {
+                bio->bi_size = 0;
+                lbmIODone(bio, 0);
+        } else {
+                submit_bio(READ_SYNC, bio);
+        }
 
         wait_event(bp->l_ioevent, (bp->l_flag != lbmREAD));
 
diff --git a/fs/jfs/super.c b/fs/jfs/super.c
index 2003e830ed1c..788e0a9c1fb0 100644
--- a/fs/jfs/super.c
+++ b/fs/jfs/super.c
@@ -611,11 +611,28 @@ static int jfs_freeze(struct super_block *sb)
 {
         struct jfs_sb_info *sbi = JFS_SBI(sb);
         struct jfs_log *log = sbi->log;
+        int rc = 0;
 
         if (!(sb->s_flags & MS_RDONLY)) {
                 txQuiesce(sb);
-                lmLogShutdown(log);
-                updateSuper(sb, FM_CLEAN);
+                rc = lmLogShutdown(log);
+                if (rc) {
+                        jfs_error(sb, "jfs_freeze: lmLogShutdown failed");
+
+                        /* let operations fail rather than hang */
+                        txResume(sb);
+
+                        return rc;
+                }
+                rc = updateSuper(sb, FM_CLEAN);
+                if (rc) {
+                        jfs_err("jfs_freeze: updateSuper failed\n");
+                        /*
+                         * Don't fail here. Everything succeeded except
+                         * marking the superblock clean, so there's really
+                         * no harm in leaving it frozen for now.
+                         */
+                }
         }
         return 0;
 }
@@ -627,13 +644,18 @@ static int jfs_unfreeze(struct super_block *sb)
         int rc = 0;
 
         if (!(sb->s_flags & MS_RDONLY)) {
-                updateSuper(sb, FM_MOUNT);
-                if ((rc = lmLogInit(log)))
-                        jfs_err("jfs_unlock failed with return code %d", rc);
-                else
-                        txResume(sb);
+                rc = updateSuper(sb, FM_MOUNT);
+                if (rc) {
+                        jfs_error(sb, "jfs_unfreeze: updateSuper failed");
+                        goto out;
+                }
+                rc = lmLogInit(log);
+                if (rc)
+                        jfs_error(sb, "jfs_unfreeze: lmLogInit failed");
+out:
+                txResume(sb);
         }
-        return 0;
+        return rc;
 }
 
 static struct dentry *jfs_do_mount(struct file_system_type *fs_type,
diff --git a/fs/namei.c b/fs/namei.c
index 85e40d1c0a8f..9ed9361223c0 100644
--- a/fs/namei.c
+++ b/fs/namei.c
@@ -1976,7 +1976,7 @@ static int path_lookupat(int dfd, const char *name,
                 err = complete_walk(nd);
 
         if (!err && nd->flags & LOOKUP_DIRECTORY) {
-                if (!nd->inode->i_op->lookup) {
+                if (!can_lookup(nd->inode)) {
                         path_put(&nd->path);
                         err = -ENOTDIR;
                 }
@@ -2850,7 +2850,7 @@ finish_lookup:
         if ((open_flag & O_CREAT) && S_ISDIR(nd->inode->i_mode))
                 goto out;
         error = -ENOTDIR;
-        if ((nd->flags & LOOKUP_DIRECTORY) && !nd->inode->i_op->lookup)
+        if ((nd->flags & LOOKUP_DIRECTORY) && !can_lookup(nd->inode))
                 goto out;
         audit_inode(name, nd->path.dentry, 0);
 finish_open:
diff --git a/fs/ncpfs/dir.c b/fs/ncpfs/dir.c
index 816326093656..6792ce11f2bf 100644
--- a/fs/ncpfs/dir.c
+++ b/fs/ncpfs/dir.c
@@ -1029,15 +1029,6 @@ static int ncp_rmdir(struct inode *dir, struct dentry *dentry)
         DPRINTK("ncp_rmdir: removing %s/%s\n",
                 dentry->d_parent->d_name.name, dentry->d_name.name);
 
-        /*
-         * fail with EBUSY if there are still references to this
-         * directory.
-         */
-        dentry_unhash(dentry);
-        error = -EBUSY;
-        if (!d_unhashed(dentry))
-                goto out;
-
         len = sizeof(__name);
         error = ncp_io2vol(server, __name, &len, dentry->d_name.name,
                            dentry->d_name.len, !ncp_preserve_case(dir));
diff --git a/fs/nfs/nfs4proc.c b/fs/nfs/nfs4proc.c
index 4e2fe714d5c2..d7ba5616989c 100644
--- a/fs/nfs/nfs4proc.c
+++ b/fs/nfs/nfs4proc.c
@@ -1078,7 +1078,7 @@ static struct nfs4_state *nfs4_try_open_cached(struct nfs4_opendata *opendata)
         struct nfs4_state *state = opendata->state;
         struct nfs_inode *nfsi = NFS_I(state->inode);
         struct nfs_delegation *delegation;
-        int open_mode = opendata->o_arg.open_flags & (O_EXCL|O_TRUNC);
+        int open_mode = opendata->o_arg.open_flags;
         fmode_t fmode = opendata->o_arg.fmode;
         nfs4_stateid stateid;
         int ret = -EAGAIN;
diff --git a/fs/nfs/super.c b/fs/nfs/super.c
index a366107a7331..2d7525fbcf25 100644
--- a/fs/nfs/super.c
+++ b/fs/nfs/super.c
@@ -1942,6 +1942,7 @@ static int nfs23_validate_mount_data(void *options,
                 args->namlen            = data->namlen;
                 args->bsize             = data->bsize;
 
+                args->auth_flavors[0] = RPC_AUTH_UNIX;
                 if (data->flags & NFS_MOUNT_SECFLAVOUR)
                         args->auth_flavors[0] = data->pseudoflavor;
                 if (!args->nfs_server.hostname)
@@ -2637,6 +2638,7 @@ static int nfs4_validate_mount_data(void *options,
                         goto out_no_address;
                 args->nfs_server.port = ntohs(((struct sockaddr_in *)sap)->sin_port);
 
+                args->auth_flavors[0] = RPC_AUTH_UNIX;
                 if (data->auth_flavourlen) {
                         if (data->auth_flavourlen > 1)
                                 goto out_inval_auth;
diff --git a/fs/ocfs2/dlm/dlmrecovery.c b/fs/ocfs2/dlm/dlmrecovery.c
index b3fdd1a323d6..e68588e6b1e8 100644
--- a/fs/ocfs2/dlm/dlmrecovery.c
+++ b/fs/ocfs2/dlm/dlmrecovery.c
@@ -1408,6 +1408,7 @@ int dlm_mig_lockres_handler(struct o2net_msg *msg, u32 len, void *data,
                                      mres->lockname_len, mres->lockname);
                                 ret = -EFAULT;
                                 spin_unlock(&res->spinlock);
+                                dlm_lockres_put(res);
                                 goto leave;
                         }
                         res->state |= DLM_LOCK_RES_MIGRATING;
diff --git a/fs/ocfs2/namei.c b/fs/ocfs2/namei.c
index 04ee1b57c243..b4a5cdf9dbc5 100644
--- a/fs/ocfs2/namei.c
+++ b/fs/ocfs2/namei.c
@@ -947,7 +947,7 @@ leave:
         ocfs2_free_dir_lookup_result(&orphan_insert);
         ocfs2_free_dir_lookup_result(&lookup);
 
-        if (status)
+        if (status && (status != -ENOTEMPTY))
                 mlog_errno(status);
 
         return status;
@@ -2216,7 +2216,7 @@ out:
 
         brelse(orphan_dir_bh);
 
-        return 0;
+        return ret;
 }
 
 int ocfs2_create_inode_in_orphan(struct inode *dir,
diff --git a/fs/pnode.c b/fs/pnode.c
index 3d2a7141b87a..9af0df15256e 100644
--- a/fs/pnode.c
+++ b/fs/pnode.c
@@ -83,7 +83,8 @@ static int do_make_slave(struct mount *mnt)
                 if (peer_mnt == mnt)
                         peer_mnt = NULL;
         }
-        if (IS_MNT_SHARED(mnt) && list_empty(&mnt->mnt_share))
+        if (mnt->mnt_group_id && IS_MNT_SHARED(mnt) &&
+            list_empty(&mnt->mnt_share))
                 mnt_release_group_id(mnt);
 
         list_del_init(&mnt->mnt_share);
diff --git a/fs/proc/base.c b/fs/proc/base.c
index dd51e50001fe..c3834dad09b3 100644
--- a/fs/proc/base.c
+++ b/fs/proc/base.c
@@ -2118,6 +2118,7 @@ static int show_timer(struct seq_file *m, void *v)
                 nstr[notify & ~SIGEV_THREAD_ID],
                 (notify & SIGEV_THREAD_ID) ? "tid" : "pid",
                 pid_nr_ns(timer->it_pid, tp->ns));
+        seq_printf(m, "ClockID: %d\n", timer->it_clock);
 
         return 0;
 }
diff --git a/fs/proc/kmsg.c b/fs/proc/kmsg.c
index bd4b5a740ff1..bdfabdaefdce 100644
--- a/fs/proc/kmsg.c
+++ b/fs/proc/kmsg.c
@@ -21,12 +21,12 @@ extern wait_queue_head_t log_wait;
 
 static int kmsg_open(struct inode * inode, struct file * file)
 {
-        return do_syslog(SYSLOG_ACTION_OPEN, NULL, 0, SYSLOG_FROM_FILE);
+        return do_syslog(SYSLOG_ACTION_OPEN, NULL, 0, SYSLOG_FROM_PROC);
 }
 
 static int kmsg_release(struct inode * inode, struct file * file)
 {
-        (void) do_syslog(SYSLOG_ACTION_CLOSE, NULL, 0, SYSLOG_FROM_FILE);
+        (void) do_syslog(SYSLOG_ACTION_CLOSE, NULL, 0, SYSLOG_FROM_PROC);
         return 0;
 }
 
@@ -34,15 +34,15 @@ static ssize_t kmsg_read(struct file *file, char __user *buf,
                          size_t count, loff_t *ppos)
 {
         if ((file->f_flags & O_NONBLOCK) &&
-            !do_syslog(SYSLOG_ACTION_SIZE_UNREAD, NULL, 0, SYSLOG_FROM_FILE))
+            !do_syslog(SYSLOG_ACTION_SIZE_UNREAD, NULL, 0, SYSLOG_FROM_PROC))
                 return -EAGAIN;
-        return do_syslog(SYSLOG_ACTION_READ, buf, count, SYSLOG_FROM_FILE);
+        return do_syslog(SYSLOG_ACTION_READ, buf, count, SYSLOG_FROM_PROC);
 }
 
 static unsigned int kmsg_poll(struct file *file, poll_table *wait)
 {
         poll_wait(file, &log_wait, wait);
-        if (do_syslog(SYSLOG_ACTION_SIZE_UNREAD, NULL, 0, SYSLOG_FROM_FILE))
+        if (do_syslog(SYSLOG_ACTION_SIZE_UNREAD, NULL, 0, SYSLOG_FROM_PROC))
                 return POLLIN | POLLRDNORM;
         return 0;
 }
diff --git a/fs/qnx6/dir.c b/fs/qnx6/dir.c
index 8798d065e400..afa6be6fc397 100644
--- a/fs/qnx6/dir.c
+++ b/fs/qnx6/dir.c
@@ -120,7 +120,7 @@ static int qnx6_readdir(struct file *filp, void *dirent, filldir_t filldir)
         struct inode *inode = file_inode(filp);
         struct super_block *s = inode->i_sb;
         struct qnx6_sb_info *sbi = QNX6_SB(s);
-        loff_t pos = filp->f_pos & (QNX6_DIR_ENTRY_SIZE - 1);
+        loff_t pos = filp->f_pos & ~(QNX6_DIR_ENTRY_SIZE - 1);
         unsigned long npages = dir_pages(inode);
         unsigned long n = pos >> PAGE_CACHE_SHIFT;
         unsigned start = (pos & ~PAGE_CACHE_MASK) / QNX6_DIR_ENTRY_SIZE;
diff --git a/fs/reiserfs/dir.c b/fs/reiserfs/dir.c
index 66c53b642a88..6c2d136561cb 100644
--- a/fs/reiserfs/dir.c
+++ b/fs/reiserfs/dir.c
@@ -204,6 +204,8 @@ int reiserfs_readdir_dentry(struct dentry *dentry, void *dirent,
                                 next_pos = deh_offset(deh) + 1;
 
                                 if (item_moved(&tmp_ih, &path_to_entry)) {
+                                        set_cpu_key_k_offset(&pos_key,
+                                                             next_pos);
                                         goto research;
                                 }
                         }       /* for */
diff --git a/fs/reiserfs/inode.c b/fs/reiserfs/inode.c
index 77d6d47abc83..f844533792ee 100644
--- a/fs/reiserfs/inode.c
+++ b/fs/reiserfs/inode.c
@@ -1811,11 +1811,16 @@ int reiserfs_new_inode(struct reiserfs_transaction_handle *th,
                                   TYPE_STAT_DATA, SD_SIZE, MAX_US_INT);
         memcpy(INODE_PKEY(inode), &(ih.ih_key), KEY_SIZE);
         args.dirid = le32_to_cpu(ih.ih_key.k_dir_id);
-        if (insert_inode_locked4(inode, args.objectid,
-                             reiserfs_find_actor, &args) < 0) {
+
+        reiserfs_write_unlock(inode->i_sb);
+        err = insert_inode_locked4(inode, args.objectid,
+                             reiserfs_find_actor, &args);
+        reiserfs_write_lock(inode->i_sb);
+        if (err) {
                 err = -EINVAL;
                 goto out_bad_inode;
         }
+
         if (old_format_only(sb))
                 /* not a perfect generation count, as object ids can be reused, but
                  ** this is as good as reiserfs can do right now.
diff --git a/fs/reiserfs/xattr.c b/fs/reiserfs/xattr.c
index 4cce1d9552fb..821bcf70e467 100644
--- a/fs/reiserfs/xattr.c
+++ b/fs/reiserfs/xattr.c
@@ -318,7 +318,19 @@ static int delete_one_xattr(struct dentry *dentry, void *data)
 static int chown_one_xattr(struct dentry *dentry, void *data)
 {
         struct iattr *attrs = data;
-        return reiserfs_setattr(dentry, attrs);
+        int ia_valid = attrs->ia_valid;
+        int err;
+
+        /*
+         * We only want the ownership bits. Otherwise, we'll do
+         * things like change a directory to a regular file if
+         * ATTR_MODE is set.
+         */
+        attrs->ia_valid &= (ATTR_UID|ATTR_GID);
+        err = reiserfs_setattr(dentry, attrs);
+        attrs->ia_valid = ia_valid;
+
+        return err;
 }
 
 /* No i_mutex, but the inode is unconnected. */
diff --git a/fs/reiserfs/xattr_acl.c b/fs/reiserfs/xattr_acl.c
index d7c01ef64eda..6c8767fdfc6a 100644
--- a/fs/reiserfs/xattr_acl.c
+++ b/fs/reiserfs/xattr_acl.c
@@ -443,6 +443,9 @@ int reiserfs_acl_chmod(struct inode *inode)
         int depth;
         int error;
 
+        if (IS_PRIVATE(inode))
+                return 0;
+
         if (S_ISLNK(inode->i_mode))
                 return -EOPNOTSUPP;
 
diff --git a/fs/xfs/xfs_acl.c b/fs/xfs/xfs_acl.c
index 1d32f1d52763..306d883d89bc 100644
--- a/fs/xfs/xfs_acl.c
+++ b/fs/xfs/xfs_acl.c
@@ -21,6 +21,8 @@
 #include "xfs_bmap_btree.h"
 #include "xfs_inode.h"
 #include "xfs_vnodeops.h"
+#include "xfs_sb.h"
+#include "xfs_mount.h"
 #include "xfs_trace.h"
 #include <linux/slab.h>
 #include <linux/xattr.h>
@@ -34,7 +36,9 @@
  */
 
 STATIC struct posix_acl *
-xfs_acl_from_disk(struct xfs_acl *aclp)
+xfs_acl_from_disk(
+        struct xfs_acl  *aclp,
+        int             max_entries)
 {
         struct posix_acl_entry *acl_e;
         struct posix_acl *acl;
@@ -42,7 +46,7 @@ xfs_acl_from_disk(struct xfs_acl *aclp)
         unsigned int count, i;
 
         count = be32_to_cpu(aclp->acl_cnt);
-        if (count > XFS_ACL_MAX_ENTRIES)
+        if (count > max_entries)
                 return ERR_PTR(-EFSCORRUPTED);
 
         acl = posix_acl_alloc(count, GFP_KERNEL);
@@ -108,9 +112,9 @@ xfs_get_acl(struct inode *inode, int type)
         struct xfs_inode *ip = XFS_I(inode);
         struct posix_acl *acl;
         struct xfs_acl *xfs_acl;
-        int len = sizeof(struct xfs_acl);
         unsigned char *ea_name;
         int error;
+        int len;
 
         acl = get_cached_acl(inode, type);
         if (acl != ACL_NOT_CACHED)
@@ -133,8 +137,8 @@ xfs_get_acl(struct inode *inode, int type)
          * If we have a cached ACLs value just return it, not need to
          * go out to the disk.
          */
-
-        xfs_acl = kzalloc(sizeof(struct xfs_acl), GFP_KERNEL);
+        len = XFS_ACL_MAX_SIZE(ip->i_mount);
+        xfs_acl = kzalloc(len, GFP_KERNEL);
         if (!xfs_acl)
                 return ERR_PTR(-ENOMEM);
 
@@ -153,7 +157,7 @@ xfs_get_acl(struct inode *inode, int type)
                 goto out;
         }
 
-        acl = xfs_acl_from_disk(xfs_acl);
+        acl = xfs_acl_from_disk(xfs_acl, XFS_ACL_MAX_ENTRIES(ip->i_mount));
         if (IS_ERR(acl))
                 goto out;
 
@@ -189,16 +193,17 @@ xfs_set_acl(struct inode *inode, int type, struct posix_acl *acl)
 
         if (acl) {
                 struct xfs_acl *xfs_acl;
-                int len;
+                int len = XFS_ACL_MAX_SIZE(ip->i_mount);
 
-                xfs_acl = kzalloc(sizeof(struct xfs_acl), GFP_KERNEL);
+                xfs_acl = kzalloc(len, GFP_KERNEL);
                 if (!xfs_acl)
                         return -ENOMEM;
 
                 xfs_acl_to_disk(xfs_acl, acl);
-                len = sizeof(struct xfs_acl) -
-                        (sizeof(struct xfs_acl_entry) *
-                         (XFS_ACL_MAX_ENTRIES - acl->a_count));
+
+                /* subtract away the unused acl entries */
+                len -= sizeof(struct xfs_acl_entry) *
+                         (XFS_ACL_MAX_ENTRIES(ip->i_mount) - acl->a_count);
 
                 error = -xfs_attr_set(ip, ea_name, (unsigned char *)xfs_acl,
                                 len, ATTR_ROOT);
@@ -243,7 +248,7 @@ xfs_set_mode(struct inode *inode, umode_t mode)
 static int
 xfs_acl_exists(struct inode *inode, unsigned char *name)
 {
-        int len = sizeof(struct xfs_acl);
+        int len = XFS_ACL_MAX_SIZE(XFS_M(inode->i_sb));
 
         return (xfs_attr_get(XFS_I(inode), name, NULL, &len,
                             ATTR_ROOT|ATTR_KERNOVAL) == 0);
@@ -379,7 +384,7 @@ xfs_xattr_acl_set(struct dentry *dentry, const char *name,
                 goto out_release;
 
         error = -EINVAL;
-        if (acl->a_count > XFS_ACL_MAX_ENTRIES)
+        if (acl->a_count > XFS_ACL_MAX_ENTRIES(XFS_M(inode->i_sb)))
                 goto out_release;
 
         if (type == ACL_TYPE_ACCESS) {
diff --git a/fs/xfs/xfs_acl.h b/fs/xfs/xfs_acl.h
index 39632d941354..4016a567b83c 100644
--- a/fs/xfs/xfs_acl.h
+++ b/fs/xfs/xfs_acl.h
@@ -22,19 +22,36 @@ struct inode;
 struct posix_acl;
 struct xfs_inode;
 
-#define XFS_ACL_MAX_ENTRIES 25
 #define XFS_ACL_NOT_PRESENT (-1)
 
 /* On-disk XFS access control list structure */
+struct xfs_acl_entry {
+        __be32  ae_tag;
+        __be32  ae_id;
+        __be16  ae_perm;
+        __be16  ae_pad;         /* fill the implicit hole in the structure */
+};
+
 struct xfs_acl {
-        __be32          acl_cnt;
-        struct xfs_acl_entry {
-                __be32  ae_tag;
-                __be32  ae_id;
-                __be16  ae_perm;
-        } acl_entry[XFS_ACL_MAX_ENTRIES];
+        __be32                  acl_cnt;
+        struct xfs_acl_entry    acl_entry[0];
 };
 
+/*
+ * The number of ACL entries allowed is defined by the on-disk format.
+ * For v4 superblocks, that is limited to 25 entries. For v5 superblocks, it is
+ * limited only by the maximum size of the xattr that stores the information.
+ */
+#define XFS_ACL_MAX_ENTRIES(mp) \
+        (xfs_sb_version_hascrc(&mp->m_sb) \
+                ?  (XATTR_SIZE_MAX - sizeof(struct xfs_acl)) / \
+                                                sizeof(struct xfs_acl_entry) \
+                : 25)
+
+#define XFS_ACL_MAX_SIZE(mp) \
+        (sizeof(struct xfs_acl) + \
+                sizeof(struct xfs_acl_entry) * XFS_ACL_MAX_ENTRIES((mp)))
+
 /* On-disk XFS extended attribute names */
 #define SGI_ACL_FILE            (unsigned char *)"SGI_ACL_FILE"
 #define SGI_ACL_DEFAULT         (unsigned char *)"SGI_ACL_DEFAULT"
diff --git a/fs/xfs/xfs_attr_leaf.c b/fs/xfs/xfs_attr_leaf.c
index 0bce1b348580..31d3cd129269 100644
--- a/fs/xfs/xfs_attr_leaf.c
+++ b/fs/xfs/xfs_attr_leaf.c
@@ -1412,7 +1412,7 @@ xfs_attr3_leaf_add_work(
                 name_rmt->valuelen = 0;
                 name_rmt->valueblk = 0;
                 args->rmtblkno = 1;
-                args->rmtblkcnt = XFS_B_TO_FSB(mp, args->valuelen);
+                args->rmtblkcnt = xfs_attr3_rmt_blocks(mp, args->valuelen);
         }
         xfs_trans_log_buf(args->trans, bp,
              XFS_DA_LOGRANGE(leaf, xfs_attr3_leaf_name(leaf, args->index),
@@ -1445,11 +1445,12 @@ xfs_attr3_leaf_add_work(
 STATIC void
 xfs_attr3_leaf_compact(
         struct xfs_da_args      *args,
-        struct xfs_attr3_icleaf_hdr *ichdr_d,
+        struct xfs_attr3_icleaf_hdr *ichdr_dst,
         struct xfs_buf          *bp)
 {
-        xfs_attr_leafblock_t    *leaf_s, *leaf_d;
-        struct xfs_attr3_icleaf_hdr ichdr_s;
+        struct xfs_attr_leafblock *leaf_src;
+        struct xfs_attr_leafblock *leaf_dst;
+        struct xfs_attr3_icleaf_hdr ichdr_src;
         struct xfs_trans        *trans = args->trans;
         struct xfs_mount        *mp = trans->t_mountp;
         char                    *tmpbuffer;
@@ -1457,29 +1458,38 @@ xfs_attr3_leaf_compact(
         trace_xfs_attr_leaf_compact(args);
 
         tmpbuffer = kmem_alloc(XFS_LBSIZE(mp), KM_SLEEP);
-        ASSERT(tmpbuffer != NULL);
         memcpy(tmpbuffer, bp->b_addr, XFS_LBSIZE(mp));
         memset(bp->b_addr, 0, XFS_LBSIZE(mp));
+        leaf_src = (xfs_attr_leafblock_t *)tmpbuffer;
+        leaf_dst = bp->b_addr;
 
         /*
-         * Copy basic information
+         * Copy the on-disk header back into the destination buffer to ensure
+         * all the information in the header that is not part of the incore
+         * header structure is preserved.
          */
-        leaf_s = (xfs_attr_leafblock_t *)tmpbuffer;
-        leaf_d = bp->b_addr;
-        ichdr_s = *ichdr_d;     /* struct copy */
-        ichdr_d->firstused = XFS_LBSIZE(mp);
-        ichdr_d->usedbytes = 0;
-        ichdr_d->count = 0;
-        ichdr_d->holes = 0;
-        ichdr_d->freemap[0].base = xfs_attr3_leaf_hdr_size(leaf_s);
-        ichdr_d->freemap[0].size = ichdr_d->firstused - ichdr_d->freemap[0].base;
+        memcpy(bp->b_addr, tmpbuffer, xfs_attr3_leaf_hdr_size(leaf_src));
+
+        /* Initialise the incore headers */
+        ichdr_src = *ichdr_dst; /* struct copy */
+        ichdr_dst->firstused = XFS_LBSIZE(mp);
+        ichdr_dst->usedbytes = 0;
+        ichdr_dst->count = 0;
+        ichdr_dst->holes = 0;
+        ichdr_dst->freemap[0].base = xfs_attr3_leaf_hdr_size(leaf_src);
+        ichdr_dst->freemap[0].size = ichdr_dst->firstused -
+                                                ichdr_dst->freemap[0].base;
+
+
+        /* write the header back to initialise the underlying buffer */
+        xfs_attr3_leaf_hdr_to_disk(leaf_dst, ichdr_dst);
 
         /*
          * Copy all entry's in the same (sorted) order,
          * but allocate name/value pairs packed and in sequence.
          */
-        xfs_attr3_leaf_moveents(leaf_s, &ichdr_s, 0, leaf_d, ichdr_d, 0,
-                                ichdr_s.count, mp);
+        xfs_attr3_leaf_moveents(leaf_src, &ichdr_src, 0, leaf_dst, ichdr_dst, 0,
+                                ichdr_src.count, mp);
         /*
          * this logs the entire buffer, but the caller must write the header
          * back to the buffer when it is finished modifying it.
@@ -2181,14 +2191,24 @@ xfs_attr3_leaf_unbalance(
                 struct xfs_attr_leafblock *tmp_leaf;
                 struct xfs_attr3_icleaf_hdr tmphdr;
 
-                tmp_leaf = kmem_alloc(state->blocksize, KM_SLEEP);
-                memset(tmp_leaf, 0, state->blocksize);
-                memset(&tmphdr, 0, sizeof(tmphdr));
+                tmp_leaf = kmem_zalloc(state->blocksize, KM_SLEEP);
 
+                /*
+                 * Copy the header into the temp leaf so that all the stuff
+                 * not in the incore header is present and gets copied back in
+                 * once we've moved all the entries.
+                 */
+                memcpy(tmp_leaf, save_leaf, xfs_attr3_leaf_hdr_size(save_leaf));
+
+                memset(&tmphdr, 0, sizeof(tmphdr));
                 tmphdr.magic = savehdr.magic;
                 tmphdr.forw = savehdr.forw;
                 tmphdr.back = savehdr.back;
                 tmphdr.firstused = state->blocksize;
+
+                /* write the header to the temp buffer to initialise it */
+                xfs_attr3_leaf_hdr_to_disk(tmp_leaf, &tmphdr);
+
                 if (xfs_attr3_leaf_order(save_blk->bp, &savehdr,
                                          drop_blk->bp, &drophdr)) {
                         xfs_attr3_leaf_moveents(drop_leaf, &drophdr, 0,
@@ -2334,8 +2354,9 @@ xfs_attr3_leaf_lookup_int(
                         args->index = probe;
                         args->valuelen = be32_to_cpu(name_rmt->valuelen);
                         args->rmtblkno = be32_to_cpu(name_rmt->valueblk);
-                        args->rmtblkcnt = XFS_B_TO_FSB(args->dp->i_mount,
-                                                       args->valuelen);
+                        args->rmtblkcnt = xfs_attr3_rmt_blocks(
+                                                        args->dp->i_mount,
+                                                        args->valuelen);
                         return XFS_ERROR(EEXIST);
                 }
         }
@@ -2386,7 +2407,8 @@ xfs_attr3_leaf_getvalue(
                 ASSERT(memcmp(args->name, name_rmt->name, args->namelen) == 0);
                 valuelen = be32_to_cpu(name_rmt->valuelen);
                 args->rmtblkno = be32_to_cpu(name_rmt->valueblk);
-                args->rmtblkcnt = XFS_B_TO_FSB(args->dp->i_mount, valuelen);
+                args->rmtblkcnt = xfs_attr3_rmt_blocks(args->dp->i_mount,
+                                                       valuelen);
                 if (args->flags & ATTR_KERNOVAL) {
                         args->valuelen = valuelen;
                         return 0;
@@ -2712,7 +2734,8 @@ xfs_attr3_leaf_list_int(
                                 args.valuelen = valuelen;
                                 args.value = kmem_alloc(valuelen, KM_SLEEP | KM_NOFS);
                                 args.rmtblkno = be32_to_cpu(name_rmt->valueblk);
-                                args.rmtblkcnt = XFS_B_TO_FSB(args.dp->i_mount, valuelen);
+                                args.rmtblkcnt = xfs_attr3_rmt_blocks(
+                                                        args.dp->i_mount, valuelen);
                                 retval = xfs_attr_rmtval_get(&args);
                                 if (retval)
                                         return retval;
@@ -3235,7 +3258,7 @@ xfs_attr3_leaf_inactive(
                         name_rmt = xfs_attr3_leaf_name_remote(leaf, i);
                         if (name_rmt->valueblk) {
                                 lp->valueblk = be32_to_cpu(name_rmt->valueblk);
-                                lp->valuelen = XFS_B_TO_FSB(dp->i_mount,
+                                lp->valuelen = xfs_attr3_rmt_blocks(dp->i_mount,
                                                     be32_to_cpu(name_rmt->valuelen));
                                 lp++;
                         }
diff --git a/fs/xfs/xfs_attr_leaf.h b/fs/xfs/xfs_attr_leaf.h
index f9d7846097e2..444a7704596c 100644
--- a/fs/xfs/xfs_attr_leaf.h
+++ b/fs/xfs/xfs_attr_leaf.h
@@ -128,6 +128,7 @@ struct xfs_attr3_leaf_hdr {
         __u8                    holes;
         __u8                    pad1;
         struct xfs_attr_leaf_map freemap[XFS_ATTR_LEAF_MAPSIZE];
+        __be32                  pad2;           /* 64 bit alignment */
 };
 
 #define XFS_ATTR3_LEAF_CRC_OFF  (offsetof(struct xfs_attr3_leaf_hdr, info.crc))
diff --git a/fs/xfs/xfs_attr_remote.c b/fs/xfs/xfs_attr_remote.c
index dee84466dcc9..ef6b0c124528 100644
--- a/fs/xfs/xfs_attr_remote.c
+++ b/fs/xfs/xfs_attr_remote.c
@@ -47,22 +47,55 @@
  * Each contiguous block has a header, so it is not just a simple attribute
  * length to FSB conversion.
  */
-static int
+int
 xfs_attr3_rmt_blocks(
         struct xfs_mount *mp,
         int             attrlen)
 {
-        int             buflen = XFS_ATTR3_RMT_BUF_SPACE(mp,
-                                                         mp->m_sb.sb_blocksize);
-        return (attrlen + buflen - 1) / buflen;
+        if (xfs_sb_version_hascrc(&mp->m_sb)) {
+                int buflen = XFS_ATTR3_RMT_BUF_SPACE(mp, mp->m_sb.sb_blocksize);
+                return (attrlen + buflen - 1) / buflen;
+        }
+        return XFS_B_TO_FSB(mp, attrlen);
+}
+
+/*
+ * Checking of the remote attribute header is split into two parts. The verifier
+ * does CRC, location and bounds checking, the unpacking function checks the
+ * attribute parameters and owner.
+ */
+static bool
+xfs_attr3_rmt_hdr_ok(
+        struct xfs_mount        *mp,
+        void                    *ptr,
+        xfs_ino_t               ino,
+        uint32_t                offset,
+        uint32_t                size,
+        xfs_daddr_t             bno)
+{
+        struct xfs_attr3_rmt_hdr *rmt = ptr;
+
+        if (bno != be64_to_cpu(rmt->rm_blkno))
+                return false;
+        if (offset != be32_to_cpu(rmt->rm_offset))
+                return false;
+        if (size != be32_to_cpu(rmt->rm_bytes))
+                return false;
+        if (ino != be64_to_cpu(rmt->rm_owner))
+                return false;
+
+        /* ok */
+        return true;
 }
 
 static bool
 xfs_attr3_rmt_verify(
-        struct xfs_buf          *bp)
+        struct xfs_mount        *mp,
+        void                    *ptr,
+        int                     fsbsize,
+        xfs_daddr_t             bno)
 {
-        struct xfs_mount        *mp = bp->b_target->bt_mount;
-        struct xfs_attr3_rmt_hdr *rmt = bp->b_addr;
+        struct xfs_attr3_rmt_hdr *rmt = ptr;
 
         if (!xfs_sb_version_hascrc(&mp->m_sb))
                 return false;
@@ -70,7 +103,9 @@ xfs_attr3_rmt_verify(
                 return false;
         if (!uuid_equal(&rmt->rm_uuid, &mp->m_sb.sb_uuid))
                 return false;
-        if (bp->b_bn != be64_to_cpu(rmt->rm_blkno))
+        if (be64_to_cpu(rmt->rm_blkno) != bno)
+                return false;
+        if (be32_to_cpu(rmt->rm_bytes) > fsbsize - sizeof(*rmt))
                 return false;
         if (be32_to_cpu(rmt->rm_offset) +
                                 be32_to_cpu(rmt->rm_bytes) >= XATTR_SIZE_MAX)
@@ -86,17 +121,40 @@ xfs_attr3_rmt_read_verify(
         struct xfs_buf  *bp)
 {
         struct xfs_mount *mp = bp->b_target->bt_mount;
+        char            *ptr;
+        int             len;
+        bool            corrupt = false;
+        xfs_daddr_t     bno;
 
         /* no verification of non-crc buffers */
         if (!xfs_sb_version_hascrc(&mp->m_sb))
                 return;
 
-        if (!xfs_verify_cksum(bp->b_addr, BBTOB(bp->b_length),
-                              XFS_ATTR3_RMT_CRC_OFF) ||
-            !xfs_attr3_rmt_verify(bp)) {
+        ptr = bp->b_addr;
+        bno = bp->b_bn;
+        len = BBTOB(bp->b_length);
+        ASSERT(len >= XFS_LBSIZE(mp));
+
+        while (len > 0) {
+                if (!xfs_verify_cksum(ptr, XFS_LBSIZE(mp),
+                                      XFS_ATTR3_RMT_CRC_OFF)) {
+                        corrupt = true;
+                        break;
+                }
+                if (!xfs_attr3_rmt_verify(mp, ptr, XFS_LBSIZE(mp), bno)) {
+                        corrupt = true;
+                        break;
+                }
+                len -= XFS_LBSIZE(mp);
+                ptr += XFS_LBSIZE(mp);
+                bno += mp->m_bsize;
+        }
+
+        if (corrupt) {
                 XFS_CORRUPTION_ERROR(__func__, XFS_ERRLEVEL_LOW, mp, bp->b_addr);
                 xfs_buf_ioerror(bp, EFSCORRUPTED);
-        }
+        } else
+                ASSERT(len == 0);
 }
 
 static void
@@ -105,23 +163,39 @@ xfs_attr3_rmt_write_verify(
 {
         struct xfs_mount *mp = bp->b_target->bt_mount;
         struct xfs_buf_log_item *bip = bp->b_fspriv;
+        char            *ptr;
+        int             len;
+        xfs_daddr_t     bno;
 
         /* no verification of non-crc buffers */
         if (!xfs_sb_version_hascrc(&mp->m_sb))
                 return;
 
-        if (!xfs_attr3_rmt_verify(bp)) {
-                XFS_CORRUPTION_ERROR(__func__, XFS_ERRLEVEL_LOW, mp, bp->b_addr);
-                xfs_buf_ioerror(bp, EFSCORRUPTED);
-                return;
-        }
+        ptr = bp->b_addr;
+        bno = bp->b_bn;
+        len = BBTOB(bp->b_length);
+        ASSERT(len >= XFS_LBSIZE(mp));
+
+        while (len > 0) {
+                if (!xfs_attr3_rmt_verify(mp, ptr, XFS_LBSIZE(mp), bno)) {
+                        XFS_CORRUPTION_ERROR(__func__,
+                                            XFS_ERRLEVEL_LOW, mp, bp->b_addr);
+                        xfs_buf_ioerror(bp, EFSCORRUPTED);
+                        return;
+                }
+                if (bip) {
+                        struct xfs_attr3_rmt_hdr *rmt;
+
+                        rmt = (struct xfs_attr3_rmt_hdr *)ptr;
+                        rmt->rm_lsn = cpu_to_be64(bip->bli_item.li_lsn);
+                }
+                xfs_update_cksum(ptr, XFS_LBSIZE(mp), XFS_ATTR3_RMT_CRC_OFF);
 
-        if (bip) {
-                struct xfs_attr3_rmt_hdr *rmt = bp->b_addr;
-                rmt->rm_lsn = cpu_to_be64(bip->bli_item.li_lsn);
+                len -= XFS_LBSIZE(mp);
+                ptr += XFS_LBSIZE(mp);
+                bno += mp->m_bsize;
         }
-        xfs_update_cksum(bp->b_addr, BBTOB(bp->b_length),
-                         XFS_ATTR3_RMT_CRC_OFF);
+        ASSERT(len == 0);
 }
 
 const struct xfs_buf_ops xfs_attr3_rmt_buf_ops = {
@@ -129,15 +203,16 @@ const struct xfs_buf_ops xfs_attr3_rmt_buf_ops = {
         .verify_write = xfs_attr3_rmt_write_verify,
 };
 
-static int
+STATIC int
 xfs_attr3_rmt_hdr_set(
         struct xfs_mount        *mp,
+        void                    *ptr,
         xfs_ino_t               ino,
         uint32_t                offset,
         uint32_t                size,
-        struct xfs_buf          *bp)
+        xfs_daddr_t             bno)
 {
-        struct xfs_attr3_rmt_hdr *rmt = bp->b_addr;
+        struct xfs_attr3_rmt_hdr *rmt = ptr;
 
         if (!xfs_sb_version_hascrc(&mp->m_sb))
                 return 0;
@@ -147,36 +222,107 @@ xfs_attr3_rmt_hdr_set(
         rmt->rm_bytes = cpu_to_be32(size);
         uuid_copy(&rmt->rm_uuid, &mp->m_sb.sb_uuid);
         rmt->rm_owner = cpu_to_be64(ino);
-        rmt->rm_blkno = cpu_to_be64(bp->b_bn);
-        bp->b_ops = &xfs_attr3_rmt_buf_ops;
+        rmt->rm_blkno = cpu_to_be64(bno);
 
         return sizeof(struct xfs_attr3_rmt_hdr);
 }
 
 /*
- * Checking of the remote attribute header is split into two parts. the verifier
- * does CRC, location and bounds checking, the unpacking function checks the
- * attribute parameters and owner.
+ * Helper functions to copy attribute data in and out of the one disk extents
  */
-static bool
-xfs_attr3_rmt_hdr_ok(
-        struct xfs_mount        *mp,
-        xfs_ino_t               ino,
-        uint32_t                offset,
-        uint32_t                size,
-        struct xfs_buf          *bp)
+STATIC int
+xfs_attr_rmtval_copyout(
+        struct xfs_mount *mp,
+        struct xfs_buf  *bp,
+        xfs_ino_t       ino,
+        int             *offset,
+        int             *valuelen,
+        char            **dst)
 {
-        struct xfs_attr3_rmt_hdr *rmt = bp->b_addr;
+        char            *src = bp->b_addr;
+        xfs_daddr_t     bno = bp->b_bn;
+        int             len = BBTOB(bp->b_length);
 
-        if (offset != be32_to_cpu(rmt->rm_offset))
-                return false;
-        if (size != be32_to_cpu(rmt->rm_bytes))
-                return false;
-        if (ino != be64_to_cpu(rmt->rm_owner))
-                return false;
+        ASSERT(len >= XFS_LBSIZE(mp));
 
-        /* ok */
-        return true;
+        while (len > 0 && *valuelen > 0) {
+                int hdr_size = 0;
+                int byte_cnt = XFS_ATTR3_RMT_BUF_SPACE(mp, XFS_LBSIZE(mp));
+
+                byte_cnt = min_t(int, *valuelen, byte_cnt);
+
+                if (xfs_sb_version_hascrc(&mp->m_sb)) {
+                        if (!xfs_attr3_rmt_hdr_ok(mp, src, ino, *offset,
+                                                  byte_cnt, bno)) {
+                                xfs_alert(mp,
+"remote attribute header mismatch bno/off/len/owner (0x%llx/0x%x/Ox%x/0x%llx)",
+                                        bno, *offset, byte_cnt, ino);
+                                return EFSCORRUPTED;
+                        }
+                        hdr_size = sizeof(struct xfs_attr3_rmt_hdr);
+                }
+
+                memcpy(*dst, src + hdr_size, byte_cnt);
+
+                /* roll buffer forwards */
+                len -= XFS_LBSIZE(mp);
+                src += XFS_LBSIZE(mp);
+                bno += mp->m_bsize;
+
+                /* roll attribute data forwards */
+                *valuelen -= byte_cnt;
+                *dst += byte_cnt;
+                *offset += byte_cnt;
+        }
+        return 0;
+}
+
+STATIC void
+xfs_attr_rmtval_copyin(
+        struct xfs_mount *mp,
+        struct xfs_buf  *bp,
+        xfs_ino_t       ino,
+        int             *offset,
+        int             *valuelen,
+        char            **src)
+{
+        char            *dst = bp->b_addr;
+        xfs_daddr_t     bno = bp->b_bn;
+        int             len = BBTOB(bp->b_length);
+
+        ASSERT(len >= XFS_LBSIZE(mp));
+
+        while (len > 0 && *valuelen > 0) {
+                int hdr_size;
+                int byte_cnt = XFS_ATTR3_RMT_BUF_SPACE(mp, XFS_LBSIZE(mp));
+
+                byte_cnt = min(*valuelen, byte_cnt);
+                hdr_size = xfs_attr3_rmt_hdr_set(mp, dst, ino, *offset,
+                                                 byte_cnt, bno);
+
+                memcpy(dst + hdr_size, *src, byte_cnt);
+
+                /*
+                 * If this is the last block, zero the remainder of it.
+                 * Check that we are actually the last block, too.
+                 */
+                if (byte_cnt + hdr_size < XFS_LBSIZE(mp)) {
+                        ASSERT(*valuelen - byte_cnt == 0);
+                        ASSERT(len == XFS_LBSIZE(mp));
+                        memset(dst + hdr_size + byte_cnt, 0,
+                                        XFS_LBSIZE(mp) - hdr_size - byte_cnt);
+                }
+
+                /* roll buffer forwards */
+                len -= XFS_LBSIZE(mp);
+                dst += XFS_LBSIZE(mp);
+                bno += mp->m_bsize;
+
+                /* roll attribute data forwards */
+                *valuelen -= byte_cnt;
+                *src += byte_cnt;
+                *offset += byte_cnt;
+        }
 }
 
 /*
@@ -190,13 +336,12 @@ xfs_attr_rmtval_get(
         struct xfs_bmbt_irec    map[ATTR_RMTVALUE_MAPSIZE];
         struct xfs_mount        *mp = args->dp->i_mount;
         struct xfs_buf          *bp;
-        xfs_daddr_t             dblkno;
         xfs_dablk_t             lblkno = args->rmtblkno;
-        void                    *dst = args->value;
+        char                    *dst = args->value;
         int                     valuelen = args->valuelen;
         int                     nmap;
         int                     error;
-        int                     blkcnt;
+        int                     blkcnt = args->rmtblkcnt;
         int                     i;
         int                     offset = 0;
 
@@ -207,52 +352,36 @@ xfs_attr_rmtval_get(
         while (valuelen > 0) {
                 nmap = ATTR_RMTVALUE_MAPSIZE;
                 error = xfs_bmapi_read(args->dp, (xfs_fileoff_t)lblkno,
-                                       args->rmtblkcnt, map, &nmap,
+                                       blkcnt, map, &nmap,
                                        XFS_BMAPI_ATTRFORK);
                 if (error)
                         return error;
                 ASSERT(nmap >= 1);
 
                 for (i = 0; (i < nmap) && (valuelen > 0); i++) {
-                        int     byte_cnt;
-                        char    *src;
+                        xfs_daddr_t     dblkno;
+                        int             dblkcnt;
 
                         ASSERT((map[i].br_startblock != DELAYSTARTBLOCK) &&
                                (map[i].br_startblock != HOLESTARTBLOCK));
                         dblkno = XFS_FSB_TO_DADDR(mp, map[i].br_startblock);
-                        blkcnt = XFS_FSB_TO_BB(mp, map[i].br_blockcount);
+                        dblkcnt = XFS_FSB_TO_BB(mp, map[i].br_blockcount);
                         error = xfs_trans_read_buf(mp, NULL, mp->m_ddev_targp,
-                                                   dblkno, blkcnt, 0, &bp,
+                                                   dblkno, dblkcnt, 0, &bp,
                                                    &xfs_attr3_rmt_buf_ops);
                         if (error)
                                 return error;
 
-                        byte_cnt = min_t(int, valuelen, BBTOB(bp->b_length));
-                        byte_cnt = XFS_ATTR3_RMT_BUF_SPACE(mp, byte_cnt);
-
-                        src = bp->b_addr;
-                        if (xfs_sb_version_hascrc(&mp->m_sb)) {
-                                if (!xfs_attr3_rmt_hdr_ok(mp, args->dp->i_ino,
-                                                        offset, byte_cnt, bp)) {
-                                        xfs_alert(mp,
-"remote attribute header does not match required off/len/owner (0x%x/Ox%x,0x%llx)",
-                                                offset, byte_cnt, args->dp->i_ino);
-                                        xfs_buf_relse(bp);
-                                        return EFSCORRUPTED;
-
-                                }
-
-                                src += sizeof(struct xfs_attr3_rmt_hdr);
-                        }
-
-                        memcpy(dst, src, byte_cnt);
+                        error = xfs_attr_rmtval_copyout(mp, bp, args->dp->i_ino,
+                                                        &offset, &valuelen,
+                                                        &dst);
                         xfs_buf_relse(bp);
+                        if (error)
+                                return error;
 
-                        offset += byte_cnt;
-                        dst += byte_cnt;
-                        valuelen -= byte_cnt;
-
+                        /* roll attribute extent map forwards */
                         lblkno += map[i].br_blockcount;
+                        blkcnt -= map[i].br_blockcount;
                 }
         }
         ASSERT(valuelen == 0);
@@ -270,17 +399,13 @@ xfs_attr_rmtval_set(
         struct xfs_inode        *dp = args->dp;
         struct xfs_mount        *mp = dp->i_mount;
         struct xfs_bmbt_irec    map;
-        struct xfs_buf          *bp;
-        xfs_daddr_t             dblkno;
         xfs_dablk_t             lblkno;
         xfs_fileoff_t           lfileoff = 0;
-        void                    *src = args->value;
+        char                    *src = args->value;
         int                     blkcnt;
         int                     valuelen;
         int                     nmap;
         int                     error;
-        int                     hdrcnt = 0;
-        bool                    crcs = xfs_sb_version_hascrc(&mp->m_sb);
         int                     offset = 0;
 
         trace_xfs_attr_rmtval_set(args);
@@ -289,24 +414,14 @@ xfs_attr_rmtval_set(
          * Find a "hole" in the attribute address space large enough for
          * us to drop the new attribute's value into. Because CRC enable
          * attributes have headers, we can't just do a straight byte to FSB
-         * conversion. We calculate the worst case block count in this case
-         * and we may not need that many, so we have to handle this when
-         * allocating the blocks below. 
+         * conversion and have to take the header space into account.
          */
-        if (!crcs)
-                blkcnt = XFS_B_TO_FSB(mp, args->valuelen);
-        else
-                blkcnt = xfs_attr3_rmt_blocks(mp, args->valuelen);
-
+        blkcnt = xfs_attr3_rmt_blocks(mp, args->valuelen);
         error = xfs_bmap_first_unused(args->trans, args->dp, blkcnt, &lfileoff,
                                                    XFS_ATTR_FORK);
         if (error)
                 return error;
 
-        /* Start with the attribute data. We'll allocate the rest afterwards. */
-        if (crcs)
-                blkcnt = XFS_B_TO_FSB(mp, args->valuelen);
-
         args->rmtblkno = lblkno = (xfs_dablk_t)lfileoff;
         args->rmtblkcnt = blkcnt;
 
@@ -349,26 +464,6 @@ xfs_attr_rmtval_set(
                        (map.br_startblock != HOLESTARTBLOCK));
                 lblkno += map.br_blockcount;
                 blkcnt -= map.br_blockcount;
-                hdrcnt++;
-
-                /*
-                 * If we have enough blocks for the attribute data, calculate
-                 * how many extra blocks we need for headers. We might run
-                 * through this multiple times in the case that the additional
-                 * headers in the blocks needed for the data fragments spills
-                 * into requiring more blocks. e.g. for 512 byte blocks, we'll
-                 * spill for another block every 9 headers we require in this
-                 * loop.
-                 */
-                if (crcs && blkcnt == 0) {
-                        int total_len;
-
-                        total_len = args->valuelen +
-                                    hdrcnt * sizeof(struct xfs_attr3_rmt_hdr);
-                        blkcnt = XFS_B_TO_FSB(mp, total_len);
-                        blkcnt -= args->rmtblkcnt;
-                        args->rmtblkcnt += blkcnt;
-                }
 
                 /*
                  * Start the next trans in the chain.
@@ -385,18 +480,19 @@ xfs_attr_rmtval_set(
          * the INCOMPLETE flag.
          */
         lblkno = args->rmtblkno;
+        blkcnt = args->rmtblkcnt;
         valuelen = args->valuelen;
         while (valuelen > 0) {
-                int     byte_cnt;
-                char    *buf;
+                struct xfs_buf  *bp;
+                xfs_daddr_t     dblkno;
+                int             dblkcnt;
+
+                ASSERT(blkcnt > 0);
 
-                /*
-                 * Try to remember where we decided to put the value.
-                 */
                 xfs_bmap_init(args->flist, args->firstblock);
                 nmap = 1;
                 error = xfs_bmapi_read(dp, (xfs_fileoff_t)lblkno,
-                                       args->rmtblkcnt, &map, &nmap,
+                                       blkcnt, &map, &nmap,
                                        XFS_BMAPI_ATTRFORK);
                 if (error)
                         return(error);
@@ -405,41 +501,27 @@ xfs_attr_rmtval_set(
                        (map.br_startblock != HOLESTARTBLOCK));
 
                 dblkno = XFS_FSB_TO_DADDR(mp, map.br_startblock),
-                blkcnt = XFS_FSB_TO_BB(mp, map.br_blockcount);
+                dblkcnt = XFS_FSB_TO_BB(mp, map.br_blockcount);
 
-                bp = xfs_buf_get(mp->m_ddev_targp, dblkno, blkcnt, 0);
+                bp = xfs_buf_get(mp->m_ddev_targp, dblkno, dblkcnt, 0);
                 if (!bp)
                         return ENOMEM;
                 bp->b_ops = &xfs_attr3_rmt_buf_ops;
 
-                byte_cnt = BBTOB(bp->b_length);
-                byte_cnt = XFS_ATTR3_RMT_BUF_SPACE(mp, byte_cnt);
-                if (valuelen < byte_cnt)
-                        byte_cnt = valuelen;
-
-                buf = bp->b_addr;
-                buf += xfs_attr3_rmt_hdr_set(mp, dp->i_ino, offset,
-                                             byte_cnt, bp);
-                memcpy(buf, src, byte_cnt);
-
-                if (byte_cnt < BBTOB(bp->b_length))
-                        xfs_buf_zero(bp, byte_cnt,
-                                     BBTOB(bp->b_length) - byte_cnt);
+                xfs_attr_rmtval_copyin(mp, bp, args->dp->i_ino, &offset,
+                                       &valuelen, &src);
 
                 error = xfs_bwrite(bp); /* GROT: NOTE: synchronous write */
                 xfs_buf_relse(bp);
                 if (error)
                         return error;
 
-                src += byte_cnt;
-                valuelen -= byte_cnt;
-                offset += byte_cnt;
-                hdrcnt--;
 
+                /* roll attribute extent map forwards */
                 lblkno += map.br_blockcount;
+                blkcnt -= map.br_blockcount;
         }
         ASSERT(valuelen == 0);
-        ASSERT(hdrcnt == 0);
         return 0;
 }
 
@@ -448,33 +530,40 @@ xfs_attr_rmtval_set(
  * out-of-line buffer that it is stored on.
  */
 int
-xfs_attr_rmtval_remove(xfs_da_args_t *args)
+xfs_attr_rmtval_remove(
+        struct xfs_da_args      *args)
 {
-        xfs_mount_t *mp;
-        xfs_bmbt_irec_t map;
-        xfs_buf_t *bp;
-        xfs_daddr_t dblkno;
-        xfs_dablk_t lblkno;
-        int valuelen, blkcnt, nmap, error, done, committed;
+        struct xfs_mount        *mp = args->dp->i_mount;
+        xfs_dablk_t             lblkno;
+        int                     blkcnt;
+        int                     error;
+        int                     done;
 
         trace_xfs_attr_rmtval_remove(args);
 
-        mp = args->dp->i_mount;
-
         /*
-         * Roll through the "value", invalidating the attribute value's
-         * blocks.
+         * Roll through the "value", invalidating the attribute value's blocks.
+         * Note that args->rmtblkcnt is the minimum number of data blocks we'll
+         * see for a CRC enabled remote attribute. Each extent will have a
+         * header, and so we may have more blocks than we realise here.  If we
+         * fail to map the blocks correctly, we'll have problems with the buffer
+         * lookups.
          */
         lblkno = args->rmtblkno;
-        valuelen = args->rmtblkcnt;
-        while (valuelen > 0) {
+        blkcnt = args->rmtblkcnt;
+        while (blkcnt > 0) {
+                struct xfs_bmbt_irec    map;
+                struct xfs_buf          *bp;
+                xfs_daddr_t             dblkno;
+                int                     dblkcnt;
+                int                     nmap;
+
                 /*
                  * Try to remember where we decided to put the value.
                  */
                 nmap = 1;
                 error = xfs_bmapi_read(args->dp, (xfs_fileoff_t)lblkno,
-                                       args->rmtblkcnt, &map, &nmap,
-                                       XFS_BMAPI_ATTRFORK);
+                                       blkcnt, &map, &nmap, XFS_BMAPI_ATTRFORK);
                 if (error)
                         return(error);
                 ASSERT(nmap == 1);
@@ -482,21 +571,20 @@ xfs_attr_rmtval_remove(xfs_da_args_t *args)
                        (map.br_startblock != HOLESTARTBLOCK));
 
                 dblkno = XFS_FSB_TO_DADDR(mp, map.br_startblock),
-                blkcnt = XFS_FSB_TO_BB(mp, map.br_blockcount);
+                dblkcnt = XFS_FSB_TO_BB(mp, map.br_blockcount);
 
                 /*
                  * If the "remote" value is in the cache, remove it.
                  */
-                bp = xfs_incore(mp->m_ddev_targp, dblkno, blkcnt, XBF_TRYLOCK);
+                bp = xfs_incore(mp->m_ddev_targp, dblkno, dblkcnt, XBF_TRYLOCK);
                 if (bp) {
                         xfs_buf_stale(bp);
                         xfs_buf_relse(bp);
                         bp = NULL;
                 }
 
-                valuelen -= map.br_blockcount;
-
                 lblkno += map.br_blockcount;
+                blkcnt -= map.br_blockcount;
         }
 
         /*
@@ -506,6 +594,8 @@ xfs_attr_rmtval_remove(xfs_da_args_t *args)
         blkcnt = args->rmtblkcnt;
         done = 0;
         while (!done) {
+                int committed;
+
                 xfs_bmap_init(args->flist, args->firstblock);
                 error = xfs_bunmapi(args->trans, args->dp, lblkno, blkcnt,
                                     XFS_BMAPI_ATTRFORK | XFS_BMAPI_METADATA,
diff --git a/fs/xfs/xfs_attr_remote.h b/fs/xfs/xfs_attr_remote.h
index c7cca60a062a..92a8fd7977cc 100644
--- a/fs/xfs/xfs_attr_remote.h
+++ b/fs/xfs/xfs_attr_remote.h
@@ -20,6 +20,14 @@
 
 #define XFS_ATTR3_RMT_MAGIC     0x5841524d      /* XARM */
 
+/*
+ * There is one of these headers per filesystem block in a remote attribute.
+ * This is done to ensure there is a 1:1 mapping between the attribute value
+ * length and the number of blocks needed to store the attribute. This makes the
+ * verification of a buffer a little more complex, but greatly simplifies the
+ * allocation, reading and writing of these attributes as we don't have to guess
+ * the number of blocks needed to store the attribute data.
+ */
 struct xfs_attr3_rmt_hdr {
         __be32  rm_magic;
         __be32  rm_offset;
@@ -39,6 +47,8 @@ struct xfs_attr3_rmt_hdr {
 
 extern const struct xfs_buf_ops xfs_attr3_rmt_buf_ops;
 
+int xfs_attr3_rmt_blocks(struct xfs_mount *mp, int attrlen);
+
 int xfs_attr_rmtval_get(struct xfs_da_args *args);
 int xfs_attr_rmtval_set(struct xfs_da_args *args);
 int xfs_attr_rmtval_remove(struct xfs_da_args *args);
diff --git a/fs/xfs/xfs_btree.c b/fs/xfs/xfs_btree.c
index 8804b8a3c310..0903960410a2 100644
--- a/fs/xfs/xfs_btree.c
+++ b/fs/xfs/xfs_btree.c
@@ -2544,7 +2544,17 @@ xfs_btree_new_iroot(
         if (error)
                 goto error0;
 
+        /*
+         * we can't just memcpy() the root in for CRC enabled btree blocks.
+         * In that case have to also ensure the blkno remains correct
+         */
         memcpy(cblock, block, xfs_btree_block_len(cur));
+        if (cur->bc_flags & XFS_BTREE_CRC_BLOCKS) {
+                if (cur->bc_flags & XFS_BTREE_LONG_PTRS)
+                        cblock->bb_u.l.bb_blkno = cpu_to_be64(cbp->b_bn);
+                else
+                        cblock->bb_u.s.bb_blkno = cpu_to_be64(cbp->b_bn);
+        }
 
         be16_add_cpu(&block->bb_level, 1);
         xfs_btree_set_numrecs(block, 1);
diff --git a/fs/xfs/xfs_buf.c b/fs/xfs/xfs_buf.c
index 0d2554299688..1b2472a46e46 100644
--- a/fs/xfs/xfs_buf.c
+++ b/fs/xfs/xfs_buf.c
@@ -513,6 +513,7 @@ _xfs_buf_find(
                 xfs_alert(btp->bt_mount,
                           "%s: Block out of range: block 0x%llx, EOFS 0x%llx ",
                           __func__, blkno, eofs);
+                WARN_ON(1);
                 return NULL;
         }
 
diff --git a/fs/xfs/xfs_buf_item.c b/fs/xfs/xfs_buf_item.c
index cf263476d6b4..4ec431777048 100644
--- a/fs/xfs/xfs_buf_item.c
+++ b/fs/xfs/xfs_buf_item.c
@@ -262,12 +262,7 @@ xfs_buf_item_format_segment(
                         vecp->i_addr = xfs_buf_offset(bp, buffer_offset);
                         vecp->i_len = nbits * XFS_BLF_CHUNK;
                         vecp->i_type = XLOG_REG_TYPE_BCHUNK;
-/*
- * You would think we need to bump the nvecs here too, but we do not
- * this number is used by recovery, and it gets confused by the boundary
- * split here
- *                      nvecs++;
- */
+                        nvecs++;
                         vecp++;
                         first_bit = next_bit;
                         last_bit = next_bit;
diff --git a/fs/xfs/xfs_dfrag.c b/fs/xfs/xfs_dfrag.c
index f852b082a084..c407e1ccff43 100644
--- a/fs/xfs/xfs_dfrag.c
+++ b/fs/xfs/xfs_dfrag.c
@@ -219,6 +219,14 @@ xfs_swap_extents(
         int             taforkblks = 0;
         __uint64_t      tmp;
 
+        /*
+         * We have no way of updating owner information in the BMBT blocks for
+         * each inode on CRC enabled filesystems, so to avoid corrupting the
+         * this metadata we simply don't allow extent swaps to occur.
+         */
+        if (xfs_sb_version_hascrc(&mp->m_sb))
+                return XFS_ERROR(EINVAL);
+
         tempifp = kmem_alloc(sizeof(xfs_ifork_t), KM_MAYFAIL);
         if (!tempifp) {
                 error = XFS_ERROR(ENOMEM);
diff --git a/fs/xfs/xfs_dir2_format.h b/fs/xfs/xfs_dir2_format.h
index a3b1bd841a80..7826782b8d78 100644
--- a/fs/xfs/xfs_dir2_format.h
+++ b/fs/xfs/xfs_dir2_format.h
@@ -266,6 +266,7 @@ struct xfs_dir3_blk_hdr {
 struct xfs_dir3_data_hdr {
         struct xfs_dir3_blk_hdr hdr;
         xfs_dir2_data_free_t    best_free[XFS_DIR2_DATA_FD_COUNT];
+        __be32                  pad;    /* 64 bit alignment */
 };
 
 #define XFS_DIR3_DATA_CRC_OFF  offsetof(struct xfs_dir3_data_hdr, hdr.crc)
@@ -477,7 +478,7 @@ struct xfs_dir3_leaf_hdr {
         struct xfs_da3_blkinfo  info;           /* header for da routines */
         __be16                  count;          /* count of entries */
         __be16                  stale;          /* count of stale entries */
-        __be32                  pad;
+        __be32                  pad;            /* 64 bit alignment */
 };
 
 struct xfs_dir3_icleaf_hdr {
@@ -715,6 +716,7 @@ struct xfs_dir3_free_hdr {
         __be32                  firstdb;        /* db of first entry */
         __be32                  nvalid;         /* count of valid entries */
         __be32                  nused;          /* count of used entries */
+        __be32                  pad;            /* 64 bit alignment */
 };
 
 struct xfs_dir3_free {
diff --git a/fs/xfs/xfs_dir2_node.c b/fs/xfs/xfs_dir2_node.c
index 5246de4912d4..2226a00acd15 100644
--- a/fs/xfs/xfs_dir2_node.c
+++ b/fs/xfs/xfs_dir2_node.c
@@ -263,18 +263,19 @@ xfs_dir3_free_get_buf(
          * Initialize the new block to be empty, and remember
          * its first slot as our empty slot.
          */
-        hdr.magic = XFS_DIR2_FREE_MAGIC;
-        hdr.firstdb = 0;
-        hdr.nused = 0;
-        hdr.nvalid = 0;
+        memset(bp->b_addr, 0, sizeof(struct xfs_dir3_free_hdr));
+        memset(&hdr, 0, sizeof(hdr));
+
         if (xfs_sb_version_hascrc(&mp->m_sb)) {
                 struct xfs_dir3_free_hdr *hdr3 = bp->b_addr;
 
                 hdr.magic = XFS_DIR3_FREE_MAGIC;
+
                 hdr3->hdr.blkno = cpu_to_be64(bp->b_bn);
                 hdr3->hdr.owner = cpu_to_be64(dp->i_ino);
                 uuid_copy(&hdr3->hdr.uuid, &mp->m_sb.sb_uuid);
-        }
+        } else
+                hdr.magic = XFS_DIR2_FREE_MAGIC;
         xfs_dir3_free_hdr_to_disk(bp->b_addr, &hdr);
         *bpp = bp;
         return 0;
@@ -1921,8 +1922,6 @@ xfs_dir2_node_addname_int(
                          */
                         freehdr.firstdb = (fbno - XFS_DIR2_FREE_FIRSTDB(mp)) *
                                         xfs_dir3_free_max_bests(mp);
-                        free->hdr.nvalid = 0;
-                        free->hdr.nused = 0;
                 } else {
                         free = fbp->b_addr;
                         bests = xfs_dir3_free_bests_p(mp, free);
diff --git a/fs/xfs/xfs_dquot.c b/fs/xfs/xfs_dquot.c
index a41f8bf1da37..044e97a33c8d 100644
--- a/fs/xfs/xfs_dquot.c
+++ b/fs/xfs/xfs_dquot.c
@@ -249,8 +249,11 @@ xfs_qm_init_dquot_blk(
                 d->dd_diskdq.d_version = XFS_DQUOT_VERSION;
                 d->dd_diskdq.d_id = cpu_to_be32(curid);
                 d->dd_diskdq.d_flags = type;
-                if (xfs_sb_version_hascrc(&mp->m_sb))
+                if (xfs_sb_version_hascrc(&mp->m_sb)) {
                         uuid_copy(&d->dd_uuid, &mp->m_sb.sb_uuid);
+                        xfs_update_cksum((char *)d, sizeof(struct xfs_dqblk),
+                                         XFS_DQUOT_CRC_OFF);
+                }
         }
 
         xfs_trans_dquot_buf(tp, bp,
@@ -286,23 +289,6 @@ xfs_dquot_set_prealloc_limits(struct xfs_dquot *dqp)
         dqp->q_low_space[XFS_QLOWSP_5_PCNT] = space * 5;
 }
 
-STATIC void
-xfs_dquot_buf_calc_crc(
-        struct xfs_mount        *mp,
-        struct xfs_buf          *bp)
-{
-        struct xfs_dqblk        *d = (struct xfs_dqblk *)bp->b_addr;
-        int                     i;
-
-        if (!xfs_sb_version_hascrc(&mp->m_sb))
-                return;
-
-        for (i = 0; i < mp->m_quotainfo->qi_dqperchunk; i++, d++) {
-                xfs_update_cksum((char *)d, sizeof(struct xfs_dqblk),
-                                 offsetof(struct xfs_dqblk, dd_crc));
-        }
-}
-
 STATIC bool
 xfs_dquot_buf_verify_crc(
         struct xfs_mount        *mp,
@@ -328,12 +314,11 @@ xfs_dquot_buf_verify_crc(
 
         for (i = 0; i < ndquots; i++, d++) {
                 if (!xfs_verify_cksum((char *)d, sizeof(struct xfs_dqblk),
-                                 offsetof(struct xfs_dqblk, dd_crc)))
+                                 XFS_DQUOT_CRC_OFF))
                         return false;
                 if (!uuid_equal(&d->dd_uuid, &mp->m_sb.sb_uuid))
                         return false;
         }
-
         return true;
 }
 
@@ -393,6 +378,11 @@ xfs_dquot_buf_read_verify(
         }
 }
 
+/*
+ * we don't calculate the CRC here as that is done when the dquot is flushed to
+ * the buffer after the update is done. This ensures that the dquot in the
+ * buffer always has an up-to-date CRC value.
+ */
 void
 xfs_dquot_buf_write_verify(
         struct xfs_buf  *bp)
@@ -404,7 +394,6 @@ xfs_dquot_buf_write_verify(
                 xfs_buf_ioerror(bp, EFSCORRUPTED);
                 return;
         }
-        xfs_dquot_buf_calc_crc(mp, bp);
 }
 
 const struct xfs_buf_ops xfs_dquot_buf_ops = {
@@ -1151,11 +1140,17 @@ xfs_qm_dqflush(
          * copy the lsn into the on-disk dquot now while we have the in memory
          * dquot here. This can't be done later in the write verifier as we
          * can't get access to the log item at that point in time.
+         *
+         * We also calculate the CRC here so that the on-disk dquot in the
+         * buffer always has a valid CRC. This ensures there is no possibility
+         * of a dquot without an up-to-date CRC getting to disk.
          */
         if (xfs_sb_version_hascrc(&mp->m_sb)) {
                 struct xfs_dqblk *dqb = (struct xfs_dqblk *)ddqp;
 
                 dqb->dd_lsn = cpu_to_be64(dqp->q_logitem.qli_item.li_lsn);
+                xfs_update_cksum((char *)dqb, sizeof(struct xfs_dqblk),
+                                 XFS_DQUOT_CRC_OFF);
         }
 
         /*
diff --git a/fs/xfs/xfs_fs.h b/fs/xfs/xfs_fs.h
index 6dda3f949b04..d04695545397 100644
--- a/fs/xfs/xfs_fs.h
+++ b/fs/xfs/xfs_fs.h
@@ -236,6 +236,7 @@ typedef struct xfs_fsop_resblks {
 #define XFS_FSOP_GEOM_FLAGS_PROJID32    0x0800  /* 32-bit project IDs   */
 #define XFS_FSOP_GEOM_FLAGS_DIRV2CI     0x1000  /* ASCII only CI names  */
 #define XFS_FSOP_GEOM_FLAGS_LAZYSB      0x4000  /* lazy superblock counters */
+#define XFS_FSOP_GEOM_FLAGS_V5SB        0x8000  /* version 5 superblock */
 
 
 /*
diff --git a/fs/xfs/xfs_fsops.c b/fs/xfs/xfs_fsops.c
index 87595b211da1..3c3644ea825b 100644
--- a/fs/xfs/xfs_fsops.c
+++ b/fs/xfs/xfs_fsops.c
@@ -99,7 +99,9 @@ xfs_fs_geometry(
                         (xfs_sb_version_hasattr2(&mp->m_sb) ?
                                 XFS_FSOP_GEOM_FLAGS_ATTR2 : 0) |
                         (xfs_sb_version_hasprojid32bit(&mp->m_sb) ?
-                                XFS_FSOP_GEOM_FLAGS_PROJID32 : 0);
+                                XFS_FSOP_GEOM_FLAGS_PROJID32 : 0) |
+                        (xfs_sb_version_hascrc(&mp->m_sb) ?
+                                XFS_FSOP_GEOM_FLAGS_V5SB : 0);
                 geo->logsectsize = xfs_sb_version_hassector(&mp->m_sb) ?
                                 mp->m_sb.sb_logsectsize : BBSIZE;
                 geo->rtsectsize = mp->m_sb.sb_blocksize;
diff --git a/fs/xfs/xfs_inode.c b/fs/xfs/xfs_inode.c
index efbe1accb6ca..7f7be5f98f52 100644
--- a/fs/xfs/xfs_inode.c
+++ b/fs/xfs/xfs_inode.c
@@ -1638,6 +1638,10 @@ xfs_iunlink(
                 dip->di_next_unlinked = agi->agi_unlinked[bucket_index];
                 offset = ip->i_imap.im_boffset +
                         offsetof(xfs_dinode_t, di_next_unlinked);
+
+                /* need to recalc the inode CRC if appropriate */
+                xfs_dinode_calc_crc(mp, dip);
+
                 xfs_trans_inode_buf(tp, ibp);
                 xfs_trans_log_buf(tp, ibp, offset,
                                   (offset + sizeof(xfs_agino_t) - 1));
@@ -1723,6 +1727,10 @@ xfs_iunlink_remove(
                         dip->di_next_unlinked = cpu_to_be32(NULLAGINO);
                         offset = ip->i_imap.im_boffset +
                                 offsetof(xfs_dinode_t, di_next_unlinked);
+
+                        /* need to recalc the inode CRC if appropriate */
+                        xfs_dinode_calc_crc(mp, dip);
+
                         xfs_trans_inode_buf(tp, ibp);
                         xfs_trans_log_buf(tp, ibp, offset,
                                           (offset + sizeof(xfs_agino_t) - 1));
@@ -1796,6 +1804,10 @@ xfs_iunlink_remove(
                         dip->di_next_unlinked = cpu_to_be32(NULLAGINO);
                         offset = ip->i_imap.im_boffset +
                                 offsetof(xfs_dinode_t, di_next_unlinked);
+
+                        /* need to recalc the inode CRC if appropriate */
+                        xfs_dinode_calc_crc(mp, dip);
+
                         xfs_trans_inode_buf(tp, ibp);
                         xfs_trans_log_buf(tp, ibp, offset,
                                           (offset + sizeof(xfs_agino_t) - 1));
@@ -1809,6 +1821,10 @@ xfs_iunlink_remove(
                 last_dip->di_next_unlinked = cpu_to_be32(next_agino);
                 ASSERT(next_agino != 0);
                 offset = last_offset + offsetof(xfs_dinode_t, di_next_unlinked);
+
+                /* need to recalc the inode CRC if appropriate */
+                xfs_dinode_calc_crc(mp, last_dip);
+
                 xfs_trans_inode_buf(tp, last_ibp);
                 xfs_trans_log_buf(tp, last_ibp, offset,
                                   (offset + sizeof(xfs_agino_t) - 1));
diff --git a/fs/xfs/xfs_iops.c b/fs/xfs/xfs_iops.c
index d82efaa2ac73..ca9ecaa81112 100644
--- a/fs/xfs/xfs_iops.c
+++ b/fs/xfs/xfs_iops.c
@@ -455,6 +455,28 @@ xfs_vn_getattr(
         return 0;
 }
 
+static void
+xfs_setattr_mode(
+        struct xfs_trans        *tp,
+        struct xfs_inode        *ip,
+        struct iattr            *iattr)
+{
+        struct inode    *inode = VFS_I(ip);
+        umode_t         mode = iattr->ia_mode;
+
+        ASSERT(tp);
+        ASSERT(xfs_isilocked(ip, XFS_ILOCK_EXCL));
+
+        if (!in_group_p(inode->i_gid) && !capable(CAP_FSETID))
+                mode &= ~S_ISGID;
+
+        ip->i_d.di_mode &= S_IFMT;
+        ip->i_d.di_mode |= mode & ~S_IFMT;
+
+        inode->i_mode &= S_IFMT;
+        inode->i_mode |= mode & ~S_IFMT;
+}
+
 int
 xfs_setattr_nonsize(
         struct xfs_inode        *ip,
@@ -606,18 +628,8 @@ xfs_setattr_nonsize(
         /*
          * Change file access modes.
          */
-        if (mask & ATTR_MODE) {
-                umode_t mode = iattr->ia_mode;
-
-                if (!in_group_p(inode->i_gid) && !capable(CAP_FSETID))
-                        mode &= ~S_ISGID;
-
-                ip->i_d.di_mode &= S_IFMT;
-                ip->i_d.di_mode |= mode & ~S_IFMT;
-
-                inode->i_mode &= S_IFMT;
-                inode->i_mode |= mode & ~S_IFMT;
-        }
+        if (mask & ATTR_MODE)
+                xfs_setattr_mode(tp, ip, iattr);
 
         /*
          * Change file access or modified times.
@@ -714,9 +726,8 @@ xfs_setattr_size(
                 return XFS_ERROR(error);
 
         ASSERT(S_ISREG(ip->i_d.di_mode));
-        ASSERT((mask & (ATTR_MODE|ATTR_UID|ATTR_GID|ATTR_ATIME|ATTR_ATIME_SET|
-                        ATTR_MTIME_SET|ATTR_KILL_SUID|ATTR_KILL_SGID|
-                        ATTR_KILL_PRIV|ATTR_TIMES_SET)) == 0);
+        ASSERT((mask & (ATTR_UID|ATTR_GID|ATTR_ATIME|ATTR_ATIME_SET|
+                        ATTR_MTIME_SET|ATTR_KILL_PRIV|ATTR_TIMES_SET)) == 0);
 
         if (!(flags & XFS_ATTR_NOLOCK)) {
                 lock_flags |= XFS_IOLOCK_EXCL;
@@ -860,6 +871,12 @@ xfs_setattr_size(
                 xfs_inode_clear_eofblocks_tag(ip);
         }
 
+        /*
+         * Change file access modes.
+         */
+        if (mask & ATTR_MODE)
+                xfs_setattr_mode(tp, ip, iattr);
+
         if (mask & ATTR_CTIME) {
                 inode->i_ctime = iattr->ia_ctime;
                 ip->i_d.di_ctime.t_sec = iattr->ia_ctime.tv_sec;
diff --git a/fs/xfs/xfs_log_recover.c b/fs/xfs/xfs_log_recover.c
index 93f03ec17eec..7cf5e4eafe28 100644
--- a/fs/xfs/xfs_log_recover.c
+++ b/fs/xfs/xfs_log_recover.c
@@ -1599,10 +1599,43 @@ xlog_recover_add_to_trans(
 }
 
 /*
- * Sort the log items in the transaction. Cancelled buffers need
- * to be put first so they are processed before any items that might
- * modify the buffers. If they are cancelled, then the modifications
- * don't need to be replayed.
+ * Sort the log items in the transaction.
+ *
+ * The ordering constraints are defined by the inode allocation and unlink
+ * behaviour. The rules are:
+ *
+ *      1. Every item is only logged once in a given transaction. Hence it
+ *         represents the last logged state of the item. Hence ordering is
+ *         dependent on the order in which operations need to be performed so
+ *         required initial conditions are always met.
+ *
+ *      2. Cancelled buffers are recorded in pass 1 in a separate table and
+ *         there's nothing to replay from them so we can simply cull them
+ *         from the transaction. However, we can't do that until after we've
+ *         replayed all the other items because they may be dependent on the
+ *         cancelled buffer and replaying the cancelled buffer can remove it
+ *         form the cancelled buffer table. Hence they have tobe done last.
+ *
+ *      3. Inode allocation buffers must be replayed before inode items that
+ *         read the buffer and replay changes into it.
+ *
+ *      4. Inode unlink buffers must be replayed after inode items are replayed.
+ *         This ensures that inodes are completely flushed to the inode buffer
+ *         in a "free" state before we remove the unlinked inode list pointer.
+ *
+ * Hence the ordering needs to be inode allocation buffers first, inode items
+ * second, inode unlink buffers third and cancelled buffers last.
+ *
+ * But there's a problem with that - we can't tell an inode allocation buffer
+ * apart from a regular buffer, so we can't separate them. We can, however,
+ * tell an inode unlink buffer from the others, and so we can separate them out
+ * from all the other buffers and move them to last.
+ *
+ * Hence, 4 lists, in order from head to tail:
+ *      - buffer_list for all buffers except cancelled/inode unlink buffers
+ *      - item_list for all non-buffer items
+ *      - inode_buffer_list for inode unlink buffers
+ *      - cancel_list for the cancelled buffers
  */
 STATIC int
 xlog_recover_reorder_trans(
@@ -1612,6 +1645,10 @@ xlog_recover_reorder_trans(
 {
         xlog_recover_item_t     *item, *n;
         LIST_HEAD(sort_list);
+        LIST_HEAD(cancel_list);
+        LIST_HEAD(buffer_list);
+        LIST_HEAD(inode_buffer_list);
+        LIST_HEAD(inode_list);
 
         list_splice_init(&trans->r_itemq, &sort_list);
         list_for_each_entry_safe(item, n, &sort_list, ri_list) {
@@ -1619,12 +1656,18 @@ xlog_recover_reorder_trans(
 
                 switch (ITEM_TYPE(item)) {
                 case XFS_LI_BUF:
-                        if (!(buf_f->blf_flags & XFS_BLF_CANCEL)) {
+                        if (buf_f->blf_flags & XFS_BLF_CANCEL) {
                                 trace_xfs_log_recover_item_reorder_head(log,
                                                         trans, item, pass);
-                                list_move(&item->ri_list, &trans->r_itemq);
+                                list_move(&item->ri_list, &cancel_list);
+                                break;
+                        }
+                        if (buf_f->blf_flags & XFS_BLF_INODE_BUF) {
+                                list_move(&item->ri_list, &inode_buffer_list);
                                 break;
                         }
+                        list_move_tail(&item->ri_list, &buffer_list);
+                        break;
                 case XFS_LI_INODE:
                 case XFS_LI_DQUOT:
                 case XFS_LI_QUOTAOFF:
@@ -1632,7 +1675,7 @@ xlog_recover_reorder_trans(
                 case XFS_LI_EFI:
                         trace_xfs_log_recover_item_reorder_tail(log,
                                                         trans, item, pass);
-                        list_move_tail(&item->ri_list, &trans->r_itemq);
+                        list_move_tail(&item->ri_list, &inode_list);
                         break;
                 default:
                         xfs_warn(log->l_mp,
@@ -1643,6 +1686,14 @@ xlog_recover_reorder_trans(
                 }
         }
         ASSERT(list_empty(&sort_list));
+        if (!list_empty(&buffer_list))
+                list_splice(&buffer_list, &trans->r_itemq);
+        if (!list_empty(&inode_list))
+                list_splice_tail(&inode_list, &trans->r_itemq);
+        if (!list_empty(&inode_buffer_list))
+                list_splice_tail(&inode_buffer_list, &trans->r_itemq);
+        if (!list_empty(&cancel_list))
+                list_splice_tail(&cancel_list, &trans->r_itemq);
         return 0;
 }
 
@@ -1794,7 +1845,13 @@ xlog_recover_do_inode_buffer(
         xfs_agino_t             *buffer_nextp;
 
         trace_xfs_log_recover_buf_inode_buf(mp->m_log, buf_f);
-        bp->b_ops = &xfs_inode_buf_ops;
+
+        /*
+         * Post recovery validation only works properly on CRC enabled
+         * filesystems.
+         */
+        if (xfs_sb_version_hascrc(&mp->m_sb))
+                bp->b_ops = &xfs_inode_buf_ops;
 
         inodes_per_buf = BBTOB(bp->b_io_length) >> mp->m_sb.sb_inodelog;
         for (i = 0; i < inodes_per_buf; i++) {
@@ -1861,6 +1918,15 @@ xlog_recover_do_inode_buffer(
                 buffer_nextp = (xfs_agino_t *)xfs_buf_offset(bp,
                                               next_unlinked_offset);
                 *buffer_nextp = *logged_nextp;
+
+                /*
+                 * If necessary, recalculate the CRC in the on-disk inode. We
+                 * have to leave the inode in a consistent state for whoever
+                 * reads it next....
+                 */
+                xfs_dinode_calc_crc(mp, (struct xfs_dinode *)
+                                xfs_buf_offset(bp, i * mp->m_sb.sb_inodesize));
+
         }
 
         return 0;
@@ -2097,6 +2163,17 @@ xlog_recover_do_reg_buffer(
                        ((uint)bit << XFS_BLF_SHIFT) + (nbits << XFS_BLF_SHIFT));
 
                 /*
+                 * The dirty regions logged in the buffer, even though
+                 * contiguous, may span multiple chunks. This is because the
+                 * dirty region may span a physical page boundary in a buffer
+                 * and hence be split into two separate vectors for writing into
+                 * the log. Hence we need to trim nbits back to the length of
+                 * the current region being copied out of the log.
+                 */
+                if (item->ri_buf[i].i_len < (nbits << XFS_BLF_SHIFT))
+                        nbits = item->ri_buf[i].i_len >> XFS_BLF_SHIFT;
+
+                /*
                  * Do a sanity check if this is a dquot buffer. Just checking
                  * the first dquot in the buffer should do. XXXThis is
                  * probably a good thing to do for other buf types also.
@@ -2134,7 +2211,16 @@ xlog_recover_do_reg_buffer(
         /* Shouldn't be any more regions */
         ASSERT(i == item->ri_total);
 
-        xlog_recovery_validate_buf_type(mp, bp, buf_f);
+        /*
+         * We can only do post recovery validation on items on CRC enabled
+         * fielsystems as we need to know when the buffer was written to be able
+         * to determine if we should have replayed the item. If we replay old
+         * metadata over a newer buffer, then it will enter a temporarily
+         * inconsistent state resulting in verification failures. Hence for now
+         * just avoid the verification stage for non-crc filesystems
+         */
+        if (xfs_sb_version_hascrc(&mp->m_sb))
+                xlog_recovery_validate_buf_type(mp, bp, buf_f);
 }
 
 /*
@@ -2255,6 +2341,12 @@ xfs_qm_dqcheck(
         d->dd_diskdq.d_flags = type;
         d->dd_diskdq.d_id = cpu_to_be32(id);
 
+        if (xfs_sb_version_hascrc(&mp->m_sb)) {
+                uuid_copy(&d->dd_uuid, &mp->m_sb.sb_uuid);
+                xfs_update_cksum((char *)d, sizeof(struct xfs_dqblk),
+                                 XFS_DQUOT_CRC_OFF);
+        }
+
         return errs;
 }
 
@@ -2782,6 +2874,10 @@ xlog_recover_dquot_pass2(
         }
 
         memcpy(ddq, recddq, item->ri_buf[1].i_len);
+        if (xfs_sb_version_hascrc(&mp->m_sb)) {
+                xfs_update_cksum((char *)ddq, sizeof(struct xfs_dqblk),
+                                 XFS_DQUOT_CRC_OFF);
+        }
 
         ASSERT(dq_f->qlf_size == 2);
         ASSERT(bp->b_target->bt_mount == mp);
diff --git a/fs/xfs/xfs_mount.c b/fs/xfs/xfs_mount.c
index f6bfbd734669..e8e310c05097 100644
--- a/fs/xfs/xfs_mount.c
+++ b/fs/xfs/xfs_mount.c
@@ -314,7 +314,8 @@ STATIC int
 xfs_mount_validate_sb(
         xfs_mount_t     *mp,
         xfs_sb_t        *sbp,
-        bool            check_inprogress)
+        bool            check_inprogress,
+        bool            check_version)
 {
 
         /*
@@ -337,9 +338,10 @@ xfs_mount_validate_sb(
 
         /*
          * Version 5 superblock feature mask validation. Reject combinations the
-         * kernel cannot support up front before checking anything else.
+         * kernel cannot support up front before checking anything else. For
+         * write validation, we don't need to check feature masks.
          */
-        if (XFS_SB_VERSION_NUM(sbp) == XFS_SB_VERSION_5) {
+        if (check_version && XFS_SB_VERSION_NUM(sbp) == XFS_SB_VERSION_5) {
                 xfs_alert(mp,
 "Version 5 superblock detected. This kernel has EXPERIMENTAL support enabled!\n"
 "Use of these features in this kernel is at your own risk!");
@@ -675,7 +677,8 @@ xfs_sb_to_disk(
 
 static int
 xfs_sb_verify(
-        struct xfs_buf  *bp)
+        struct xfs_buf  *bp,
+        bool            check_version)
 {
         struct xfs_mount *mp = bp->b_target->bt_mount;
         struct xfs_sb   sb;
@@ -686,7 +689,8 @@ xfs_sb_verify(
          * Only check the in progress field for the primary superblock as
          * mkfs.xfs doesn't clear it from secondary superblocks.
          */
-        return xfs_mount_validate_sb(mp, &sb, bp->b_bn == XFS_SB_DADDR);
+        return xfs_mount_validate_sb(mp, &sb, bp->b_bn == XFS_SB_DADDR,
+                                     check_version);
 }
 
 /*
@@ -719,7 +723,7 @@ xfs_sb_read_verify(
                         goto out_error;
                 }
         }
-        error = xfs_sb_verify(bp);
+        error = xfs_sb_verify(bp, true);
 
 out_error:
         if (error) {
@@ -758,7 +762,7 @@ xfs_sb_write_verify(
         struct xfs_buf_log_item *bip = bp->b_fspriv;
         int                     error;
 
-        error = xfs_sb_verify(bp);
+        error = xfs_sb_verify(bp, false);
         if (error) {
                 XFS_CORRUPTION_ERROR(__func__, XFS_ERRLEVEL_LOW, mp, bp->b_addr);
                 xfs_buf_ioerror(bp, error);
diff --git a/fs/xfs/xfs_qm.c b/fs/xfs/xfs_qm.c
index f41702b43003..b75c9bb6e71e 100644
--- a/fs/xfs/xfs_qm.c
+++ b/fs/xfs/xfs_qm.c
@@ -41,6 +41,7 @@
 #include "xfs_qm.h"
 #include "xfs_trace.h"
 #include "xfs_icache.h"
+#include "xfs_cksum.h"
 
 /*
  * The global quota manager. There is only one of these for the entire
@@ -839,7 +840,7 @@ xfs_qm_reset_dqcounts(
         xfs_dqid_t      id,
         uint            type)
 {
-        xfs_disk_dquot_t        *ddq;
+        struct xfs_dqblk        *dqb;
         int                     j;
 
         trace_xfs_reset_dqcounts(bp, _RET_IP_);
@@ -853,8 +854,12 @@ xfs_qm_reset_dqcounts(
         do_div(j, sizeof(xfs_dqblk_t));
         ASSERT(mp->m_quotainfo->qi_dqperchunk == j);
 #endif
-        ddq = bp->b_addr;
+        dqb = bp->b_addr;
         for (j = 0; j < mp->m_quotainfo->qi_dqperchunk; j++) {
+                struct xfs_disk_dquot   *ddq;
+
+                ddq = (struct xfs_disk_dquot *)&dqb[j];
+
                 /*
                  * Do a sanity check, and if needed, repair the dqblk. Don't
                  * output any warnings because it's perfectly possible to
@@ -871,7 +876,12 @@ xfs_qm_reset_dqcounts(
                 ddq->d_bwarns = 0;
                 ddq->d_iwarns = 0;
                 ddq->d_rtbwarns = 0;
-                ddq = (xfs_disk_dquot_t *) ((xfs_dqblk_t *)ddq + 1);
+
+                if (xfs_sb_version_hascrc(&mp->m_sb)) {
+                        xfs_update_cksum((char *)&dqb[j],
+                                         sizeof(struct xfs_dqblk),
+                                         XFS_DQUOT_CRC_OFF);
+                }
         }
 }
 
@@ -907,19 +917,29 @@ xfs_qm_dqiter_bufs(
                               XFS_FSB_TO_DADDR(mp, bno),
                               mp->m_quotainfo->qi_dqchunklen, 0, &bp,
                               &xfs_dquot_buf_ops);
-                if (error)
-                        break;
 
                 /*
-                 * XXX(hch): need to figure out if it makes sense to validate
-                 *           the CRC here.
+                 * CRC and validation errors will return a EFSCORRUPTED here. If
+                 * this occurs, re-read without CRC validation so that we can
+                 * repair the damage via xfs_qm_reset_dqcounts(). This process
+                 * will leave a trace in the log indicating corruption has
+                 * been detected.
                  */
+                if (error == EFSCORRUPTED) {
+                        error = xfs_trans_read_buf(mp, NULL, mp->m_ddev_targp,
+                                      XFS_FSB_TO_DADDR(mp, bno),
+                                      mp->m_quotainfo->qi_dqchunklen, 0, &bp,
+                                      NULL);
+                }
+
+                if (error)
+                        break;
+
                 xfs_qm_reset_dqcounts(mp, bp, firstid, type);
                 xfs_buf_delwri_queue(bp, buffer_list);
                 xfs_buf_relse(bp);
-                /*
-                 * goto the next block.
-                 */
+
+                /* goto the next block. */
                 bno++;
                 firstid += mp->m_quotainfo->qi_dqperchunk;
         }
diff --git a/fs/xfs/xfs_qm_syscalls.c b/fs/xfs/xfs_qm_syscalls.c
index c41190cad6e9..6cdf6ffc36a1 100644
--- a/fs/xfs/xfs_qm_syscalls.c
+++ b/fs/xfs/xfs_qm_syscalls.c
@@ -489,31 +489,36 @@ xfs_qm_scall_setqlim(
         if ((newlim->d_fieldmask & XFS_DQ_MASK) == 0)
                 return 0;
 
-        tp = xfs_trans_alloc(mp, XFS_TRANS_QM_SETQLIM);
-        error = xfs_trans_reserve(tp, 0, XFS_QM_SETQLIM_LOG_RES(mp),
-                                  0, 0, XFS_DEFAULT_LOG_COUNT);
-        if (error) {
-                xfs_trans_cancel(tp, 0);
-                return (error);
-        }
-
         /*
          * We don't want to race with a quotaoff so take the quotaoff lock.
-         * (We don't hold an inode lock, so there's nothing else to stop
-         * a quotaoff from happening). (XXXThis doesn't currently happen
-         * because we take the vfslock before calling xfs_qm_sysent).
+         * We don't hold an inode lock, so there's nothing else to stop
+         * a quotaoff from happening.
          */
         mutex_lock(&q->qi_quotaofflock);
 
         /*
-         * Get the dquot (locked), and join it to the transaction.
-         * Allocate the dquot if this doesn't exist.
+         * Get the dquot (locked) before we start, as we need to do a
+         * transaction to allocate it if it doesn't exist. Once we have the
+         * dquot, unlock it so we can start the next transaction safely. We hold
+         * a reference to the dquot, so it's safe to do this unlock/lock without
+         * it being reclaimed in the mean time.
          */
-        if ((error = xfs_qm_dqget(mp, NULL, id, type, XFS_QMOPT_DQALLOC, &dqp))) {
-                xfs_trans_cancel(tp, XFS_TRANS_ABORT);
+        error = xfs_qm_dqget(mp, NULL, id, type, XFS_QMOPT_DQALLOC, &dqp);
+        if (error) {
                 ASSERT(error != ENOENT);
                 goto out_unlock;
         }
+        xfs_dqunlock(dqp);
+
+        tp = xfs_trans_alloc(mp, XFS_TRANS_QM_SETQLIM);
+        error = xfs_trans_reserve(tp, 0, XFS_QM_SETQLIM_LOG_RES(mp),
+                                  0, 0, XFS_DEFAULT_LOG_COUNT);
+        if (error) {
+                xfs_trans_cancel(tp, 0);
+                goto out_rele;
+        }
+
+        xfs_dqlock(dqp);
         xfs_trans_dqjoin(tp, dqp);
         ddq = &dqp->q_core;
 
@@ -621,9 +626,10 @@ xfs_qm_scall_setqlim(
         xfs_trans_log_dquot(tp, dqp);
 
         error = xfs_trans_commit(tp, 0);
-        xfs_qm_dqrele(dqp);
 
- out_unlock:
+out_rele:
+        xfs_qm_dqrele(dqp);
+out_unlock:
         mutex_unlock(&q->qi_quotaofflock);
         return error;
 }
diff --git a/fs/xfs/xfs_quota.h b/fs/xfs/xfs_quota.h
index c61e31c7d997..c38068f26c55 100644
--- a/fs/xfs/xfs_quota.h
+++ b/fs/xfs/xfs_quota.h
@@ -87,6 +87,8 @@ typedef struct xfs_dqblk {
         uuid_t            dd_uuid;      /* location information */
 } xfs_dqblk_t;
 
+#define XFS_DQUOT_CRC_OFF       offsetof(struct xfs_dqblk, dd_crc)
+
 /*
  * flags for q_flags field in the dquot.
  */
diff --git a/fs/xfs/xfs_super.c b/fs/xfs/xfs_super.c
index ea341cea68cb..3033ba5e9762 100644
--- a/fs/xfs/xfs_super.c
+++ b/fs/xfs/xfs_super.c
@@ -1373,6 +1373,17 @@ xfs_finish_flags(
         }
 
         /*
+         * V5 filesystems always use attr2 format for attributes.
+         */
+        if (xfs_sb_version_hascrc(&mp->m_sb) &&
+            (mp->m_flags & XFS_MOUNT_NOATTR2)) {
+                xfs_warn(mp,
+"Cannot mount a V5 filesystem as %s. %s is always enabled for V5 filesystems.",
+                        MNTOPT_NOATTR2, MNTOPT_ATTR2);
+                return XFS_ERROR(EINVAL);
+        }
+
+        /*
          * mkfs'ed attr2 will turn on attr2 mount unless explicitly
          * told by noattr2 to turn it off
          */
diff --git a/fs/xfs/xfs_symlink.c b/fs/xfs/xfs_symlink.c
index 5f234389327c..195a403e1522 100644
--- a/fs/xfs/xfs_symlink.c
+++ b/fs/xfs/xfs_symlink.c
@@ -56,16 +56,9 @@ xfs_symlink_blocks(
         struct xfs_mount *mp,
         int             pathlen)
 {
-        int             fsblocks = 0;
-        int             len = pathlen;
+        int buflen = XFS_SYMLINK_BUF_SPACE(mp, mp->m_sb.sb_blocksize);
 
-        do {
-                fsblocks++;
-                len -= XFS_SYMLINK_BUF_SPACE(mp, mp->m_sb.sb_blocksize);
-        } while (len > 0);
-
-        ASSERT(fsblocks <= XFS_SYMLINK_MAPS);
-        return fsblocks;
+        return (pathlen + buflen - 1) / buflen;
 }
 
 static int
@@ -405,7 +398,7 @@ xfs_symlink(
         if (pathlen <= XFS_LITINO(mp, dp->i_d.di_version))
                 fs_blocks = 0;
         else
-                fs_blocks = XFS_B_TO_FSB(mp, pathlen);
+                fs_blocks = xfs_symlink_blocks(mp, pathlen);
         resblks = XFS_SYMLINK_SPACE_RES(mp, link_name->len, fs_blocks);
         error = xfs_trans_reserve(tp, resblks, XFS_SYMLINK_LOG_RES(mp), 0,
                         XFS_TRANS_PERM_LOG_RES, XFS_SYMLINK_LOG_COUNT);
@@ -512,7 +505,7 @@ xfs_symlink(
                 cur_chunk = target_path;
                 offset = 0;
                 for (n = 0; n < nmaps; n++) {
-                        char *buf;
+                        char    *buf;
 
                         d = XFS_FSB_TO_DADDR(mp, mval[n].br_startblock);
                         byte_cnt = XFS_FSB_TO_B(mp, mval[n].br_blockcount);
@@ -525,9 +518,7 @@ xfs_symlink(
                         bp->b_ops = &xfs_symlink_buf_ops;
 
                         byte_cnt = XFS_SYMLINK_BUF_SPACE(mp, byte_cnt);
-                        if (pathlen < byte_cnt) {
-                                byte_cnt = pathlen;
-                        }
+                        byte_cnt = min(byte_cnt, pathlen);
 
                         buf = bp->b_addr;
                         buf += xfs_symlink_hdr_set(mp, ip->i_ino, offset,
@@ -542,6 +533,7 @@ xfs_symlink(
                         xfs_trans_log_buf(tp, bp, 0, (buf + byte_cnt - 1) -
                                                         (char *)bp->b_addr);
                 }
+                ASSERT(pathlen == 0);
         }
 
         /*
diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index ac9da00e9f2c..d5afe96adba6 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -343,8 +343,12 @@ extern void ioport_unmap(void __iomem *p);
 #endif /* CONFIG_GENERIC_IOMAP */
 #endif /* CONFIG_HAS_IOPORT */
 
+#ifndef xlate_dev_kmem_ptr
 #define xlate_dev_kmem_ptr(p)   p
+#endif
+#ifndef xlate_dev_mem_ptr
 #define xlate_dev_mem_ptr(p)    __va(p)
+#endif
 
 #ifdef CONFIG_VIRT_TO_BUS
 #ifndef virt_to_bus
diff --git a/include/asm-generic/kvm_para.h b/include/asm-generic/kvm_para.h
index 9d96605f160a..fa25becbdcaf 100644
--- a/include/asm-generic/kvm_para.h
+++ b/include/asm-generic/kvm_para.h
@@ -18,4 +18,9 @@ static inline unsigned int kvm_arch_para_features(void)
         return 0;
 }
 
+static inline bool kvm_para_available(void)
+{
+        return false;
+}
+
 #endif
diff --git a/include/asm-generic/tlb.h b/include/asm-generic/tlb.h
index b1b1fa6ffffe..13821c339a41 100644
--- a/include/asm-generic/tlb.h
+++ b/include/asm-generic/tlb.h
@@ -97,11 +97,9 @@ struct mmu_gather {
         unsigned long           start;
         unsigned long           end;
         unsigned int            need_flush : 1, /* Did free PTEs */
-                                fast_mode  : 1; /* No batching   */
-
         /* we are in the middle of an operation to clear
          * a full mm and can make some optimizations */
-        unsigned int            fullmm : 1,
+                                fullmm : 1,
         /* we have performed an operation which
          * requires a complete flush of the tlb */
                                 need_flush_all : 1;
@@ -114,19 +112,6 @@ struct mmu_gather {
 
 #define HAVE_GENERIC_MMU_GATHER
 
-static inline int tlb_fast_mode(struct mmu_gather *tlb)
-{
-#ifdef CONFIG_SMP
-        return tlb->fast_mode;
-#else
-        /*
-         * For UP we don't need to worry about TLB flush
-         * and page free order so much..
-         */
-        return 1;
-#endif
-}
-
 void tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, bool fullmm);
 void tlb_flush_mmu(struct mmu_gather *tlb);
 void tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start,
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
new file mode 100644
index 000000000000..7fcdf90879f2
--- /dev/null
+++ b/include/dt-bindings/clock/imx6sl-clock.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H
+#define __DT_BINDINGS_CLOCK_IMX6SL_H
+
+#define IMX6SL_CLK_DUMMY                0
+#define IMX6SL_CLK_CKIL                 1
+#define IMX6SL_CLK_OSC                  2
+#define IMX6SL_CLK_PLL1_SYS             3
+#define IMX6SL_CLK_PLL2_BUS             4
+#define IMX6SL_CLK_PLL3_USB_OTG         5
+#define IMX6SL_CLK_PLL4_AUDIO           6
+#define IMX6SL_CLK_PLL5_VIDEO           7
+#define IMX6SL_CLK_PLL6_ENET            8
+#define IMX6SL_CLK_PLL7_USB_HOST        9
+#define IMX6SL_CLK_USBPHY1              10
+#define IMX6SL_CLK_USBPHY2              11
+#define IMX6SL_CLK_USBPHY1_GATE         12
+#define IMX6SL_CLK_USBPHY2_GATE         13
+#define IMX6SL_CLK_PLL4_POST_DIV        14
+#define IMX6SL_CLK_PLL5_POST_DIV        15
+#define IMX6SL_CLK_PLL5_VIDEO_DIV       16
+#define IMX6SL_CLK_ENET_REF             17
+#define IMX6SL_CLK_PLL2_PFD0            18
+#define IMX6SL_CLK_PLL2_PFD1            19
+#define IMX6SL_CLK_PLL2_PFD2            20
+#define IMX6SL_CLK_PLL3_PFD0            21
+#define IMX6SL_CLK_PLL3_PFD1            22
+#define IMX6SL_CLK_PLL3_PFD2            23
+#define IMX6SL_CLK_PLL3_PFD3            24
+#define IMX6SL_CLK_PLL2_198M            25
+#define IMX6SL_CLK_PLL3_120M            26
+#define IMX6SL_CLK_PLL3_80M             27
+#define IMX6SL_CLK_PLL3_60M             28
+#define IMX6SL_CLK_STEP                 29
+#define IMX6SL_CLK_PLL1_SW              30
+#define IMX6SL_CLK_OCRAM_ALT_SEL        31
+#define IMX6SL_CLK_OCRAM_SEL            32
+#define IMX6SL_CLK_PRE_PERIPH2_SEL      33
+#define IMX6SL_CLK_PRE_PERIPH_SEL       34
+#define IMX6SL_CLK_PERIPH2_CLK2_SEL     35
+#define IMX6SL_CLK_PERIPH_CLK2_SEL      36
+#define IMX6SL_CLK_CSI_SEL              37
+#define IMX6SL_CLK_LCDIF_AXI_SEL        38
+#define IMX6SL_CLK_USDHC1_SEL           39
+#define IMX6SL_CLK_USDHC2_SEL           40
+#define IMX6SL_CLK_USDHC3_SEL           41
+#define IMX6SL_CLK_USDHC4_SEL           42
+#define IMX6SL_CLK_SSI1_SEL             43
+#define IMX6SL_CLK_SSI2_SEL             44
+#define IMX6SL_CLK_SSI3_SEL             45
+#define IMX6SL_CLK_PERCLK_SEL           46
+#define IMX6SL_CLK_PXP_AXI_SEL          47
+#define IMX6SL_CLK_EPDC_AXI_SEL         48
+#define IMX6SL_CLK_GPU2D_OVG_SEL        49
+#define IMX6SL_CLK_GPU2D_SEL            50
+#define IMX6SL_CLK_LCDIF_PIX_SEL        51
+#define IMX6SL_CLK_EPDC_PIX_SEL         52
+#define IMX6SL_CLK_SPDIF0_SEL           53
+#define IMX6SL_CLK_SPDIF1_SEL           54
+#define IMX6SL_CLK_EXTERN_AUDIO_SEL     55
+#define IMX6SL_CLK_ECSPI_SEL            56
+#define IMX6SL_CLK_UART_SEL             57
+#define IMX6SL_CLK_PERIPH               58
+#define IMX6SL_CLK_PERIPH2              59
+#define IMX6SL_CLK_OCRAM_PODF           60
+#define IMX6SL_CLK_PERIPH_CLK2_PODF     61
+#define IMX6SL_CLK_PERIPH2_CLK2_PODF    62
+#define IMX6SL_CLK_IPG                  63
+#define IMX6SL_CLK_CSI_PODF             64
+#define IMX6SL_CLK_LCDIF_AXI_PODF       65
+#define IMX6SL_CLK_USDHC1_PODF          66
+#define IMX6SL_CLK_USDHC2_PODF          67
+#define IMX6SL_CLK_USDHC3_PODF          68
+#define IMX6SL_CLK_USDHC4_PODF          69
+#define IMX6SL_CLK_SSI1_PRED            70
+#define IMX6SL_CLK_SSI1_PODF            71
+#define IMX6SL_CLK_SSI2_PRED            72
+#define IMX6SL_CLK_SSI2_PODF            73
+#define IMX6SL_CLK_SSI3_PRED            74
+#define IMX6SL_CLK_SSI3_PODF            75
+#define IMX6SL_CLK_PERCLK               76
+#define IMX6SL_CLK_PXP_AXI_PODF         77
+#define IMX6SL_CLK_EPDC_AXI_PODF        78
+#define IMX6SL_CLK_GPU2D_OVG_PODF       79
+#define IMX6SL_CLK_GPU2D_PODF           80
+#define IMX6SL_CLK_LCDIF_PIX_PRED       81
+#define IMX6SL_CLK_EPDC_PIX_PRED        82
+#define IMX6SL_CLK_LCDIF_PIX_PODF       83
+#define IMX6SL_CLK_EPDC_PIX_PODF        84
+#define IMX6SL_CLK_SPDIF0_PRED          85
+#define IMX6SL_CLK_SPDIF0_PODF          86
+#define IMX6SL_CLK_SPDIF1_PRED          87
+#define IMX6SL_CLK_SPDIF1_PODF          88
+#define IMX6SL_CLK_EXTERN_AUDIO_PRED    89
+#define IMX6SL_CLK_EXTERN_AUDIO_PODF    90
+#define IMX6SL_CLK_ECSPI_ROOT           91
+#define IMX6SL_CLK_UART_ROOT            92
+#define IMX6SL_CLK_AHB                  93
+#define IMX6SL_CLK_MMDC_ROOT            94
+#define IMX6SL_CLK_ARM                  95
+#define IMX6SL_CLK_ECSPI1               96
+#define IMX6SL_CLK_ECSPI2               97
+#define IMX6SL_CLK_ECSPI3               98
+#define IMX6SL_CLK_ECSPI4               99
+#define IMX6SL_CLK_EPIT1                100
+#define IMX6SL_CLK_EPIT2                101
+#define IMX6SL_CLK_EXTERN_AUDIO         102
+#define IMX6SL_CLK_GPT                  103
+#define IMX6SL_CLK_GPT_SERIAL           104
+#define IMX6SL_CLK_GPU2D_OVG            105
+#define IMX6SL_CLK_I2C1                 106
+#define IMX6SL_CLK_I2C2                 107
+#define IMX6SL_CLK_I2C3                 108
+#define IMX6SL_CLK_OCOTP                109
+#define IMX6SL_CLK_CSI                  110
+#define IMX6SL_CLK_PXP_AXI              111
+#define IMX6SL_CLK_EPDC_AXI             112
+#define IMX6SL_CLK_LCDIF_AXI            113
+#define IMX6SL_CLK_LCDIF_PIX            114
+#define IMX6SL_CLK_EPDC_PIX             115
+#define IMX6SL_CLK_OCRAM                116
+#define IMX6SL_CLK_PWM1                 117
+#define IMX6SL_CLK_PWM2                 118
+#define IMX6SL_CLK_PWM3                 119
+#define IMX6SL_CLK_PWM4                 120
+#define IMX6SL_CLK_SDMA                 121
+#define IMX6SL_CLK_SPDIF                122
+#define IMX6SL_CLK_SSI1                 123
+#define IMX6SL_CLK_SSI2                 124
+#define IMX6SL_CLK_SSI3                 125
+#define IMX6SL_CLK_UART                 126
+#define IMX6SL_CLK_UART_SERIAL          127
+#define IMX6SL_CLK_USBOH3               128
+#define IMX6SL_CLK_USDHC1               129
+#define IMX6SL_CLK_USDHC2               130
+#define IMX6SL_CLK_USDHC3               131
+#define IMX6SL_CLK_USDHC4               132
+#define IMX6SL_CLK_CLK_END              133
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
new file mode 100644
index 000000000000..15e997fa78f2
--- /dev/null
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_VF610_H
+#define __DT_BINDINGS_CLOCK_VF610_H
+
+#define VF610_CLK_DUMMY                 0
+#define VF610_CLK_SIRC_128K             1
+#define VF610_CLK_SIRC_32K              2
+#define VF610_CLK_FIRC                  3
+#define VF610_CLK_SXOSC                 4
+#define VF610_CLK_FXOSC                 5
+#define VF610_CLK_FXOSC_HALF            6
+#define VF610_CLK_SLOW_CLK_SEL          7
+#define VF610_CLK_FASK_CLK_SEL          8
+#define VF610_CLK_AUDIO_EXT             9
+#define VF610_CLK_ENET_EXT              10
+#define VF610_CLK_PLL1_MAIN             11
+#define VF610_CLK_PLL1_PFD1             12
+#define VF610_CLK_PLL1_PFD2             13
+#define VF610_CLK_PLL1_PFD3             14
+#define VF610_CLK_PLL1_PFD4             15
+#define VF610_CLK_PLL2_MAIN             16
+#define VF610_CLK_PLL2_PFD1             17
+#define VF610_CLK_PLL2_PFD2             18
+#define VF610_CLK_PLL2_PFD3             19
+#define VF610_CLK_PLL2_PFD4             20
+#define VF610_CLK_PLL3_MAIN             21
+#define VF610_CLK_PLL3_PFD1             22
+#define VF610_CLK_PLL3_PFD2             23
+#define VF610_CLK_PLL3_PFD3             24
+#define VF610_CLK_PLL3_PFD4             25
+#define VF610_CLK_PLL4_MAIN             26
+#define VF610_CLK_PLL5_MAIN             27
+#define VF610_CLK_PLL6_MAIN             28
+#define VF610_CLK_PLL3_MAIN_DIV         29
+#define VF610_CLK_PLL4_MAIN_DIV         30
+#define VF610_CLK_PLL6_MAIN_DIV         31
+#define VF610_CLK_PLL1_PFD_SEL          32
+#define VF610_CLK_PLL2_PFD_SEL          33
+#define VF610_CLK_SYS_SEL               34
+#define VF610_CLK_DDR_SEL               35
+#define VF610_CLK_SYS_BUS               36
+#define VF610_CLK_PLATFORM_BUS          37
+#define VF610_CLK_IPG_BUS               38
+#define VF610_CLK_UART0                 39
+#define VF610_CLK_UART1                 40
+#define VF610_CLK_UART2                 41
+#define VF610_CLK_UART3                 42
+#define VF610_CLK_UART4                 43
+#define VF610_CLK_UART5                 44
+#define VF610_CLK_PIT                   45
+#define VF610_CLK_I2C0                  46
+#define VF610_CLK_I2C1                  47
+#define VF610_CLK_I2C2                  48
+#define VF610_CLK_I2C3                  49
+#define VF610_CLK_FTM0_EXT_SEL          50
+#define VF610_CLK_FTM0_FIX_SEL          51
+#define VF610_CLK_FTM0_EXT_FIX_EN       52
+#define VF610_CLK_FTM1_EXT_SEL          53
+#define VF610_CLK_FTM1_FIX_SEL          54
+#define VF610_CLK_FTM1_EXT_FIX_EN       55
+#define VF610_CLK_FTM2_EXT_SEL          56
+#define VF610_CLK_FTM2_FIX_SEL          57
+#define VF610_CLK_FTM2_EXT_FIX_EN       58
+#define VF610_CLK_FTM3_EXT_SEL          59
+#define VF610_CLK_FTM3_FIX_SEL          60
+#define VF610_CLK_FTM3_EXT_FIX_EN       61
+#define VF610_CLK_FTM0                  62
+#define VF610_CLK_FTM1                  63
+#define VF610_CLK_FTM2                  64
+#define VF610_CLK_FTM3                  65
+#define VF610_CLK_ENET_50M              66
+#define VF610_CLK_ENET_25M              67
+#define VF610_CLK_ENET_SEL              68
+#define VF610_CLK_ENET                  69
+#define VF610_CLK_ENET_TS_SEL           70
+#define VF610_CLK_ENET_TS               71
+#define VF610_CLK_DSPI0                 72
+#define VF610_CLK_DSPI1                 73
+#define VF610_CLK_DSPI2                 74
+#define VF610_CLK_DSPI3                 75
+#define VF610_CLK_WDT                   76
+#define VF610_CLK_ESDHC0_SEL            77
+#define VF610_CLK_ESDHC0_EN             78
+#define VF610_CLK_ESDHC0_DIV            79
+#define VF610_CLK_ESDHC0                80
+#define VF610_CLK_ESDHC1_SEL            81
+#define VF610_CLK_ESDHC1_EN             82
+#define VF610_CLK_ESDHC1_DIV            83
+#define VF610_CLK_ESDHC1                84
+#define VF610_CLK_DCU0_SEL              85
+#define VF610_CLK_DCU0_EN               86
+#define VF610_CLK_DCU0_DIV              87
+#define VF610_CLK_DCU0                  88
+#define VF610_CLK_DCU1_SEL              89
+#define VF610_CLK_DCU1_EN               90
+#define VF610_CLK_DCU1_DIV              91
+#define VF610_CLK_DCU1                  92
+#define VF610_CLK_ESAI_SEL              93
+#define VF610_CLK_ESAI_EN               94
+#define VF610_CLK_ESAI_DIV              95
+#define VF610_CLK_ESAI                  96
+#define VF610_CLK_SAI0_SEL              97
+#define VF610_CLK_SAI0_EN               98
+#define VF610_CLK_SAI0_DIV              99
+#define VF610_CLK_SAI0                  100
+#define VF610_CLK_SAI1_SEL              101
+#define VF610_CLK_SAI1_EN               102
+#define VF610_CLK_SAI1_DIV              103
+#define VF610_CLK_SAI1                  104
+#define VF610_CLK_SAI2_SEL              105
+#define VF610_CLK_SAI2_EN               106
+#define VF610_CLK_SAI2_DIV              107
+#define VF610_CLK_SAI2                  108
+#define VF610_CLK_SAI3_SEL              109
+#define VF610_CLK_SAI3_EN               110
+#define VF610_CLK_SAI3_DIV              111
+#define VF610_CLK_SAI3                  112
+#define VF610_CLK_USBC0                 113
+#define VF610_CLK_USBC1                 114
+#define VF610_CLK_QSPI0_SEL             115
+#define VF610_CLK_QSPI0_EN              116
+#define VF610_CLK_QSPI0_X4_DIV          117
+#define VF610_CLK_QSPI0_X2_DIV          118
+#define VF610_CLK_QSPI0_X1_DIV          119
+#define VF610_CLK_QSPI1_SEL             120
+#define VF610_CLK_QSPI1_EN              121
+#define VF610_CLK_QSPI1_X4_DIV          122
+#define VF610_CLK_QSPI1_X2_DIV          123
+#define VF610_CLK_QSPI1_X1_DIV          124
+#define VF610_CLK_QSPI0                 125
+#define VF610_CLK_QSPI1                 126
+#define VF610_CLK_NFC_SEL               127
+#define VF610_CLK_NFC_EN                128
+#define VF610_CLK_NFC_PRE_DIV           129
+#define VF610_CLK_NFC_FRAC_DIV          130
+#define VF610_CLK_NFC_INV               131
+#define VF610_CLK_NFC                   132
+#define VF610_CLK_VADC_SEL              133
+#define VF610_CLK_VADC_EN               134
+#define VF610_CLK_VADC_DIV              135
+#define VF610_CLK_VADC_DIV_HALF         136
+#define VF610_CLK_VADC                  137
+#define VF610_CLK_ADC0                  138
+#define VF610_CLK_ADC1                  139
+#define VF610_CLK_DAC0                  140
+#define VF610_CLK_DAC1                  141
+#define VF610_CLK_FLEXCAN0              142
+#define VF610_CLK_FLEXCAN1              143
+#define VF610_CLK_ASRC                  144
+#define VF610_CLK_GPU_SEL               145
+#define VF610_CLK_GPU_EN                146
+#define VF610_CLK_GPU2D                 147
+#define VF610_CLK_END                   148
+
+#endif /* __DT_BINDINGS_CLOCK_VF610_H */
diff --git a/include/linux/aer.h b/include/linux/aer.h
index ec10e1b24c1c..737f90ab4b62 100644
--- a/include/linux/aer.h
+++ b/include/linux/aer.h
@@ -49,10 +49,11 @@ static inline int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev)
 }
 #endif
 
-extern void cper_print_aer(const char *prefix, struct pci_dev *dev,
+extern void cper_print_aer(struct pci_dev *dev,
                            int cper_severity, struct aer_capability_regs *aer);
 extern int cper_severity_to_aer(int cper_severity);
 extern void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
-                              int severity);
+                              int severity,
+                              struct aer_capability_regs *aer_regs);
 #endif //_AER_H_
 
diff --git a/include/linux/arm-cci.h b/include/linux/arm-cci.h
new file mode 100644
index 000000000000..79d6edf446d5
--- /dev/null
+++ b/include/linux/arm-cci.h
@@ -0,0 +1,61 @@
+/*
+ * CCI cache coherent interconnect support
+ *
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __LINUX_ARM_CCI_H
+#define __LINUX_ARM_CCI_H
+
+#include <linux/errno.h>
+#include <linux/types.h>
+
+struct device_node;
+
+#ifdef CONFIG_ARM_CCI
+extern bool cci_probed(void);
+extern int cci_ace_get_port(struct device_node *dn);
+extern int cci_disable_port_by_cpu(u64 mpidr);
+extern int __cci_control_port_by_device(struct device_node *dn, bool enable);
+extern int __cci_control_port_by_index(u32 port, bool enable);
+#else
+static inline bool cci_probed(void) { return false; }
+static inline int cci_ace_get_port(struct device_node *dn)
+{
+        return -ENODEV;
+}
+static inline int cci_disable_port_by_cpu(u64 mpidr) { return -ENODEV; }
+static inline int __cci_control_port_by_device(struct device_node *dn,
+                                               bool enable)
+{
+        return -ENODEV;
+}
+static inline int __cci_control_port_by_index(u32 port, bool enable)
+{
+        return -ENODEV;
+}
+#endif
+#define cci_disable_port_by_device(dev) \
+        __cci_control_port_by_device(dev, false)
+#define cci_enable_port_by_device(dev) \
+        __cci_control_port_by_device(dev, true)
+#define cci_disable_port_by_index(dev) \
+        __cci_control_port_by_index(dev, false)
+#define cci_enable_port_by_index(dev) \
+        __cci_control_port_by_index(dev, true)
+
+#endif
diff --git a/include/linux/cgroup.h b/include/linux/cgroup.h
index 5047355b9a0f..8bda1294c035 100644
--- a/include/linux/cgroup.h
+++ b/include/linux/cgroup.h
@@ -707,7 +707,7 @@ struct cgroup *cgroup_rightmost_descendant(struct cgroup *pos);
  *
  * If a subsystem synchronizes against the parent in its ->css_online() and
  * before starting iterating, and synchronizes against @pos on each
- * iteration, any descendant cgroup which finished ->css_offline() is
+ * iteration, any descendant cgroup which finished ->css_online() is
  * guaranteed to be visible in the future iterations.
  *
  * In other words, the following guarantees that a descendant can't escape
diff --git a/include/linux/clk/mvebu.h b/include/linux/clk/mvebu.h
deleted file mode 100644
index 8c4ae713b063..000000000000
--- a/include/linux/clk/mvebu.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __CLK_MVEBU_H_
-#define __CLK_MVEBU_H_
-
-void __init mvebu_clocks_init(void);
-
-#endif
diff --git a/include/linux/clk/zynq.h b/include/linux/clk/zynq.h
index 56be7cd9aa8b..e062d317ccce 100644
--- a/include/linux/clk/zynq.h
+++ b/include/linux/clk/zynq.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright (C) 2013 Xilinx Inc.
  * Copyright (C) 2012 National Instruments
  *
  * This program is free software; you can redistribute it and/or modify
@@ -19,6 +20,11 @@
 #ifndef __LINUX_CLK_ZYNQ_H_
 #define __LINUX_CLK_ZYNQ_H_
 
-void __init xilinx_zynq_clocks_init(void __iomem *slcr);
+#include <linux/spinlock.h>
 
+void zynq_clock_init(void __iomem *slcr);
+
+struct clk *clk_register_zynq_pll(const char *name, const char *parent,
+                void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
+                spinlock_t *lock);
 #endif
diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index c6f6e0839b61..9f3c7e81270a 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -175,6 +175,8 @@ extern struct bus_type cpu_subsys;
 
 extern void get_online_cpus(void);
 extern void put_online_cpus(void);
+extern void cpu_hotplug_disable(void);
+extern void cpu_hotplug_enable(void);
 #define hotcpu_notifier(fn, pri)        cpu_notifier(fn, pri)
 #define register_hotcpu_notifier(nb)    register_cpu_notifier(nb)
 #define unregister_hotcpu_notifier(nb)  unregister_cpu_notifier(nb)
@@ -198,6 +200,8 @@ static inline void cpu_hotplug_driver_unlock(void)
 
 #define get_online_cpus()       do { } while (0)
 #define put_online_cpus()       do { } while (0)
+#define cpu_hotplug_disable()   do { } while (0)
+#define cpu_hotplug_enable()    do { } while (0)
 #define hotcpu_notifier(fn, pri)        do { (void)(fn); } while (0)
 /* These aren't inline functions due to a GCC bug. */
 #define register_hotcpu_notifier(nb)    ({ (void)(nb); 0; })
diff --git a/include/linux/filter.h b/include/linux/filter.h
index c050dcc322a4..f65f5a69db8f 100644
--- a/include/linux/filter.h
+++ b/include/linux/filter.h
@@ -46,6 +46,7 @@ extern int sk_attach_filter(struct sock_fprog *fprog, struct sock *sk);
 extern int sk_detach_filter(struct sock *sk);
 extern int sk_chk_filter(struct sock_filter *filter, unsigned int flen);
 extern int sk_get_filter(struct sock *sk, struct sock_filter __user *filter, unsigned len);
+extern void sk_decode_filter(struct sock_filter *filt, struct sock_filter *to);
 
 #ifdef CONFIG_BPF_JIT
 #include <stdarg.h>
diff --git a/include/linux/if_team.h b/include/linux/if_team.h
index 4474557904f6..16fae6436d0e 100644
--- a/include/linux/if_team.h
+++ b/include/linux/if_team.h
@@ -249,12 +249,12 @@ team_get_first_port_txable_rcu(struct team *team, struct team_port *port)
                 return port;
         cur = port;
         list_for_each_entry_continue_rcu(cur, &team->port_list, list)
-                if (team_port_txable(port))
+                if (team_port_txable(cur))
                         return cur;
         list_for_each_entry_rcu(cur, &team->port_list, list) {
                 if (cur == port)
                         break;
-                if (team_port_txable(port))
+                if (team_port_txable(cur))
                         return cur;
         }
         return NULL;
diff --git a/include/linux/list.h b/include/linux/list.h
index 6a1f8df9144b..b83e5657365a 100644
--- a/include/linux/list.h
+++ b/include/linux/list.h
@@ -362,6 +362,17 @@ static inline void list_splice_tail_init(struct list_head *list,
         list_entry((ptr)->next, type, member)
 
 /**
+ * list_first_entry_or_null - get the first element from a list
+ * @ptr:        the list head to take the element from.
+ * @type:       the type of the struct this is embedded in.
+ * @member:     the name of the list_struct within the struct.
+ *
+ * Note that if the list is empty, it returns NULL.
+ */
+#define list_first_entry_or_null(ptr, type, member) \
+        (!list_empty(ptr) ? list_first_entry(ptr, type, member) : NULL)
+
+/**
  * list_for_each        -       iterate over a list
  * @pos:        the &struct list_head to use as a loop cursor.
  * @head:       the head for your list.
diff --git a/include/linux/math64.h b/include/linux/math64.h
index b8ba85544721..2913b86eb12a 100644
--- a/include/linux/math64.h
+++ b/include/linux/math64.h
@@ -6,7 +6,8 @@
 
 #if BITS_PER_LONG == 64
 
-#define div64_long(x,y) div64_s64((x),(y))
+#define div64_long(x, y) div64_s64((x), (y))
+#define div64_ul(x, y)   div64_u64((x), (y))
 
 /**
  * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
@@ -47,7 +48,8 @@ static inline s64 div64_s64(s64 dividend, s64 divisor)
 
 #elif BITS_PER_LONG == 32
 
-#define div64_long(x,y) div_s64((x),(y))
+#define div64_long(x, y) div_s64((x), (y))
+#define div64_ul(x, y)   div_u64((x), (y))
 
 #ifndef div_u64_rem
 static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder)
diff --git a/include/linux/mfd/davinci_voicecodec.h b/include/linux/mfd/davinci_voicecodec.h
index 0ab61320ffa8..7dd6524d2aac 100644
--- a/include/linux/mfd/davinci_voicecodec.h
+++ b/include/linux/mfd/davinci_voicecodec.h
@@ -26,8 +26,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/mfd/core.h>
-
-#include <mach/edma.h>
+#include <linux/platform_data/edma.h>
 
 /*
  * Register values.
diff --git a/include/linux/mfd/syscon/clps711x.h b/include/linux/mfd/syscon/clps711x.h
new file mode 100644
index 000000000000..26355abae515
--- /dev/null
+++ b/include/linux/mfd/syscon/clps711x.h
@@ -0,0 +1,94 @@
+/*
+ *  CLPS711X system register bits definitions
+ *
+ *  Copyright (C) 2013 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _LINUX_MFD_SYSCON_CLPS711X_H_
+#define _LINUX_MFD_SYSCON_CLPS711X_H_
+
+#define SYSCON_OFFSET           (0x00)
+#define SYSFLG_OFFSET           (0x40)
+
+#define SYSCON1_KBDSCAN(x)      ((x) & 15)
+#define SYSCON1_KBDSCAN_MASK    (15)
+#define SYSCON1_TC1M            (1 << 4)
+#define SYSCON1_TC1S            (1 << 5)
+#define SYSCON1_TC2M            (1 << 6)
+#define SYSCON1_TC2S            (1 << 7)
+#define SYSCON1_BZTOG           (1 << 9)
+#define SYSCON1_BZMOD           (1 << 10)
+#define SYSCON1_DBGEN           (1 << 11)
+#define SYSCON1_LCDEN           (1 << 12)
+#define SYSCON1_CDENTX          (1 << 13)
+#define SYSCON1_CDENRX          (1 << 14)
+#define SYSCON1_SIREN           (1 << 15)
+#define SYSCON1_ADCKSEL(x)      (((x) & 3) << 16)
+#define SYSCON1_ADCKSEL_MASK    (3 << 16)
+#define SYSCON1_EXCKEN          (1 << 18)
+#define SYSCON1_WAKEDIS         (1 << 19)
+#define SYSCON1_IRTXM           (1 << 20)
+
+#define SYSCON2_SERSEL          (1 << 0)
+#define SYSCON2_KBD6            (1 << 1)
+#define SYSCON2_DRAMZ           (1 << 2)
+#define SYSCON2_KBWEN           (1 << 3)
+#define SYSCON2_SS2TXEN         (1 << 4)
+#define SYSCON2_PCCARD1         (1 << 5)
+#define SYSCON2_PCCARD2         (1 << 6)
+#define SYSCON2_SS2RXEN         (1 << 7)
+#define SYSCON2_SS2MAEN         (1 << 9)
+#define SYSCON2_OSTB            (1 << 12)
+#define SYSCON2_CLKENSL         (1 << 13)
+#define SYSCON2_BUZFREQ         (1 << 14)
+
+#define SYSCON3_ADCCON          (1 << 0)
+#define SYSCON3_CLKCTL0         (1 << 1)
+#define SYSCON3_CLKCTL1         (1 << 2)
+#define SYSCON3_DAISEL          (1 << 3)
+#define SYSCON3_ADCCKNSEN       (1 << 4)
+#define SYSCON3_VERSN(x)        (((x) >> 5) & 7)
+#define SYSCON3_VERSN_MASK      (7 << 5)
+#define SYSCON3_FASTWAKE        (1 << 8)
+#define SYSCON3_DAIEN           (1 << 9)
+#define SYSCON3_128FS           SYSCON3_DAIEN
+#define SYSCON3_ENPD67          (1 << 10)
+
+#define SYSCON_UARTEN           (1 << 8)
+
+#define SYSFLG1_MCDR            (1 << 0)
+#define SYSFLG1_DCDET           (1 << 1)
+#define SYSFLG1_WUDR            (1 << 2)
+#define SYSFLG1_WUON            (1 << 3)
+#define SYSFLG1_CTS             (1 << 8)
+#define SYSFLG1_DSR             (1 << 9)
+#define SYSFLG1_DCD             (1 << 10)
+#define SYSFLG1_NBFLG           (1 << 12)
+#define SYSFLG1_RSTFLG          (1 << 13)
+#define SYSFLG1_PFFLG           (1 << 14)
+#define SYSFLG1_CLDFLG          (1 << 15)
+#define SYSFLG1_CRXFE           (1 << 24)
+#define SYSFLG1_CTXFF           (1 << 25)
+#define SYSFLG1_SSIBUSY         (1 << 26)
+#define SYSFLG1_ID              (1 << 29)
+#define SYSFLG1_VERID(x)        (((x) >> 30) & 3)
+#define SYSFLG1_VERID_MASK      (3 << 30)
+
+#define SYSFLG2_SSRXOF          (1 << 0)
+#define SYSFLG2_RESVAL          (1 << 1)
+#define SYSFLG2_RESFRM          (1 << 2)
+#define SYSFLG2_SS2RXFE         (1 << 3)
+#define SYSFLG2_SS2TXFF         (1 << 4)
+#define SYSFLG2_SS2TXUF         (1 << 5)
+#define SYSFLG2_CKMODE          (1 << 6)
+
+#define SYSFLG_UBUSY            (1 << 11)
+#define SYSFLG_URXFE            (1 << 22)
+#define SYSFLG_UTXFF            (1 << 23)
+
+#endif
diff --git a/include/linux/netfilter_ipv6.h b/include/linux/netfilter_ipv6.h
index 98ffb54988b6..2d4df6ce043e 100644
--- a/include/linux/netfilter_ipv6.h
+++ b/include/linux/netfilter_ipv6.h
@@ -17,6 +17,22 @@ extern __sum16 nf_ip6_checksum(struct sk_buff *skb, unsigned int hook,
 
 extern int ipv6_netfilter_init(void);
 extern void ipv6_netfilter_fini(void);
+
+/*
+ * Hook functions for ipv6 to allow xt_* modules to be built-in even
+ * if IPv6 is a module.
+ */
+struct nf_ipv6_ops {
+        int (*chk_addr)(struct net *net, const struct in6_addr *addr,
+                        const struct net_device *dev, int strict);
+};
+
+extern const struct nf_ipv6_ops __rcu *nf_ipv6_ops;
+static inline const struct nf_ipv6_ops *nf_get_ipv6_ops(void)
+{
+        return rcu_dereference(nf_ipv6_ops);
+}
+
 #else /* CONFIG_NETFILTER */
 static inline int ipv6_netfilter_init(void) { return 0; }
 static inline void ipv6_netfilter_fini(void) { return; }
diff --git a/include/linux/of_address.h b/include/linux/of_address.h
index 0506eb53519b..4c2e6f26432c 100644
--- a/include/linux/of_address.h
+++ b/include/linux/of_address.h
@@ -4,6 +4,36 @@
 #include <linux/errno.h>
 #include <linux/of.h>
 
+struct of_pci_range_parser {
+        struct device_node *node;
+        const __be32 *range;
+        const __be32 *end;
+        int np;
+        int pna;
+};
+
+struct of_pci_range {
+        u32 pci_space;
+        u64 pci_addr;
+        u64 cpu_addr;
+        u64 size;
+        u32 flags;
+};
+
+#define for_each_of_pci_range(parser, range) \
+        for (; of_pci_range_parser_one(parser, range);)
+
+static inline void of_pci_range_to_resource(struct of_pci_range *range,
+                                            struct device_node *np,
+                                            struct resource *res)
+{
+        res->flags = range->flags;
+        res->start = range->cpu_addr;
+        res->end = range->cpu_addr + range->size - 1;
+        res->parent = res->child = res->sibling = NULL;
+        res->name = np->full_name;
+}
+
 #ifdef CONFIG_OF_ADDRESS
 extern u64 of_translate_address(struct device_node *np, const __be32 *addr);
 extern bool of_can_translate_address(struct device_node *dev);
@@ -27,6 +57,11 @@ static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
 #define pci_address_to_pio pci_address_to_pio
 #endif
 
+extern int of_pci_range_parser_init(struct of_pci_range_parser *parser,
+                        struct device_node *node);
+extern struct of_pci_range *of_pci_range_parser_one(
+                                        struct of_pci_range_parser *parser,
+                                        struct of_pci_range *range);
 #else /* CONFIG_OF_ADDRESS */
 #ifndef of_address_to_resource
 static inline int of_address_to_resource(struct device_node *dev, int index,
@@ -53,6 +88,19 @@ static inline const __be32 *of_get_address(struct device_node *dev, int index,
 {
         return NULL;
 }
+
+static inline int of_pci_range_parser_init(struct of_pci_range_parser *parser,
+                        struct device_node *node)
+{
+        return -1;
+}
+
+static inline struct of_pci_range *of_pci_range_parser_one(
+                                        struct of_pci_range_parser *parser,
+                                        struct of_pci_range *range)
+{
+        return NULL;
+}
 #endif /* CONFIG_OF_ADDRESS */
 
 
diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h
index bb115deb7612..7a04826018c0 100644
--- a/include/linux/of_pci.h
+++ b/include/linux/of_pci.h
@@ -10,5 +10,7 @@ int of_irq_map_pci(const struct pci_dev *pdev, struct of_irq *out_irq);
 struct device_node;
 struct device_node *of_pci_find_child_device(struct device_node *parent,
                                              unsigned int devfn);
+int of_pci_get_devfn(struct device_node *np);
+int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
 
 #endif
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/include/linux/platform_data/edma.h
index 7e84c906ceff..2344ea2675ad 100644
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ b/include/linux/platform_data/edma.h
@@ -1,28 +1,12 @@
 /*
- *  TI DAVINCI dma definitions
+ *  TI EDMA definitions
  *
- *  Copyright (C) 2006-2009 Texas Instruments.
+ *  Copyright (C) 2006-2013 Texas Instruments.
  *
  *  This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
  *  Free Software Foundation;  either version 2 of the  License, or (at your
  *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
  */
 
 /*
@@ -69,11 +53,6 @@ struct edmacc_param {
         unsigned int ccnt;
 };
 
-#define CCINT0_INTERRUPT     16
-#define CCERRINT_INTERRUPT   17
-#define TCERRINT0_INTERRUPT   18
-#define TCERRINT1_INTERRUPT   19
-
 /* fields in edmacc_param.opt */
 #define SAM             BIT(0)
 #define DAM             BIT(1)
@@ -87,70 +66,6 @@ struct edmacc_param {
 #define TCCHEN          BIT(22)
 #define ITCCHEN         BIT(23)
 
-#define TRWORD (0x7<<2)
-#define PAENTRY (0x1ff<<5)
-
-/* Drivers should avoid using these symbolic names for dm644x
- * channels, and use platform_device IORESOURCE_DMA resources
- * instead.  (Other DaVinci chips have different peripherals
- * and thus have different DMA channel mappings.)
- */
-#define DAVINCI_DMA_MCBSP_TX              2
-#define DAVINCI_DMA_MCBSP_RX              3
-#define DAVINCI_DMA_VPSS_HIST             4
-#define DAVINCI_DMA_VPSS_H3A              5
-#define DAVINCI_DMA_VPSS_PRVU             6
-#define DAVINCI_DMA_VPSS_RSZ              7
-#define DAVINCI_DMA_IMCOP_IMXINT          8
-#define DAVINCI_DMA_IMCOP_VLCDINT         9
-#define DAVINCI_DMA_IMCO_PASQINT         10
-#define DAVINCI_DMA_IMCOP_DSQINT         11
-#define DAVINCI_DMA_SPI_SPIX             16
-#define DAVINCI_DMA_SPI_SPIR             17
-#define DAVINCI_DMA_UART0_URXEVT0        18
-#define DAVINCI_DMA_UART0_UTXEVT0        19
-#define DAVINCI_DMA_UART1_URXEVT1        20
-#define DAVINCI_DMA_UART1_UTXEVT1        21
-#define DAVINCI_DMA_UART2_URXEVT2        22
-#define DAVINCI_DMA_UART2_UTXEVT2        23
-#define DAVINCI_DMA_MEMSTK_MSEVT         24
-#define DAVINCI_DMA_MMCRXEVT             26
-#define DAVINCI_DMA_MMCTXEVT             27
-#define DAVINCI_DMA_I2C_ICREVT           28
-#define DAVINCI_DMA_I2C_ICXEVT           29
-#define DAVINCI_DMA_GPIO_GPINT0          32
-#define DAVINCI_DMA_GPIO_GPINT1          33
-#define DAVINCI_DMA_GPIO_GPINT2          34
-#define DAVINCI_DMA_GPIO_GPINT3          35
-#define DAVINCI_DMA_GPIO_GPINT4          36
-#define DAVINCI_DMA_GPIO_GPINT5          37
-#define DAVINCI_DMA_GPIO_GPINT6          38
-#define DAVINCI_DMA_GPIO_GPINT7          39
-#define DAVINCI_DMA_GPIO_GPBNKINT0       40
-#define DAVINCI_DMA_GPIO_GPBNKINT1       41
-#define DAVINCI_DMA_GPIO_GPBNKINT2       42
-#define DAVINCI_DMA_GPIO_GPBNKINT3       43
-#define DAVINCI_DMA_GPIO_GPBNKINT4       44
-#define DAVINCI_DMA_TIMER0_TINT0         48
-#define DAVINCI_DMA_TIMER1_TINT1         49
-#define DAVINCI_DMA_TIMER2_TINT2         50
-#define DAVINCI_DMA_TIMER3_TINT3         51
-#define DAVINCI_DMA_PWM0                 52
-#define DAVINCI_DMA_PWM1                 53
-#define DAVINCI_DMA_PWM2                 54
-
-/* DA830 specific EDMA3 information */
-#define EDMA_DA830_NUM_DMACH            32
-#define EDMA_DA830_NUM_TCC              32
-#define EDMA_DA830_NUM_PARAMENTRY       128
-#define EDMA_DA830_NUM_EVQUE            2
-#define EDMA_DA830_NUM_TC               2
-#define EDMA_DA830_CHMAP_EXIST          0
-#define EDMA_DA830_NUM_REGIONS          4
-#define DA830_DMACH2EVENT_MAP0          0x000FC03Fu
-#define DA830_DMACH2EVENT_MAP1          0x00000000u
-#define DA830_EDMA_ARM_OWN              0x30FFCCFFu
-
 /*ch_status paramater of callback function possible values*/
 #define DMA_COMPLETE 1
 #define DMA_CC_ERROR 2
diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h
index b253f77a7ddf..2d8d69432813 100644
--- a/include/linux/platform_data/gpio-rcar.h
+++ b/include/linux/platform_data/gpio-rcar.h
@@ -17,10 +17,13 @@
 #define __GPIO_RCAR_H__
 
 struct gpio_rcar_config {
-        unsigned int gpio_base;
+        int gpio_base;
         unsigned int irq_base;
         unsigned int number_of_pins;
         const char *pctl_name;
+        unsigned has_both_edge_trigger:1;
 };
 
+#define RCAR_GP_PIN(bank, pin)          (((bank) * 32) + (pin))
+
 #endif /* __GPIO_RCAR_H__ */
diff --git a/include/linux/platform_data/pinctrl-coh901.h b/include/linux/platform_data/pinctrl-coh901.h
deleted file mode 100644
index dfbc65d10484..000000000000
--- a/include/linux/platform_data/pinctrl-coh901.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2007-2012 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * GPIO block resgister definitions and inline macros for
- * U300 GPIO COH 901 335 or COH 901 571/3
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-
-#ifndef __MACH_U300_GPIO_U300_H
-#define __MACH_U300_GPIO_U300_H
-
-/**
- * struct u300_gpio_platform - U300 GPIO platform data
- * @ports: number of GPIO block ports
- * @gpio_base: first GPIO number for this block (use a free range)
- */
-struct u300_gpio_platform {
-        u8 ports;
-        int gpio_base;
-};
-
-#endif /* __MACH_U300_GPIO_U300_H */
diff --git a/include/linux/platform_data/spi-davinci.h b/include/linux/platform_data/spi-davinci.h
index 7af305b37868..8dc2fa47a2aa 100644
--- a/include/linux/platform_data/spi-davinci.h
+++ b/include/linux/platform_data/spi-davinci.h
@@ -19,7 +19,7 @@
 #ifndef __ARCH_ARM_DAVINCI_SPI_H
 #define __ARCH_ARM_DAVINCI_SPI_H
 
-#include <mach/edma.h>
+#include <linux/platform_data/edma.h>
 
 #define SPI_INTERN_CS   0xFF
 
diff --git a/include/linux/platform_data/usb-rcar-phy.h b/include/linux/platform_data/usb-rcar-phy.h
new file mode 100644
index 000000000000..8ec6964a32a5
--- /dev/null
+++ b/include/linux/platform_data/usb-rcar-phy.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013 Cogent Embedded, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __USB_RCAR_PHY_H
+#define __USB_RCAR_PHY_H
+
+#include <linux/types.h>
+
+struct rcar_phy_platform_data {
+        bool ferrite_bead:1;    /* (R8A7778 only)                       */
+
+        bool port1_func:1;      /* true: port 1 used by function, false: host */
+        unsigned penc1:1;       /* Output of the PENC1 pin in function mode */
+        struct {                /* Overcurrent pin control for ports 0..2 */
+                bool select_3_3v:1; /* true: USB_OVCn pin, false: OVCn pin */
+                                /* Set to false on port 1 in function mode */
+                bool active_high:1; /* true: active  high, false: active low */
+                                /* Set to true  on port 1 in function mode */
+        } ovc_pin[3];           /* (R8A7778 only has 2 ports)           */
+};
+
+#endif /* __USB_RCAR_PHY_H */
diff --git a/include/linux/rculist.h b/include/linux/rculist.h
index 8089e35d47ac..f4b1001a4676 100644
--- a/include/linux/rculist.h
+++ b/include/linux/rculist.h
@@ -461,6 +461,26 @@ static inline void hlist_add_after_rcu(struct hlist_node *prev,
                         &(pos)->member)), typeof(*(pos)), member))
 
 /**
+ * hlist_for_each_entry_rcu_notrace - iterate over rcu list of given type (for tracing)
+ * @pos:        the type * to use as a loop cursor.
+ * @head:       the head for your list.
+ * @member:     the name of the hlist_node within the struct.
+ *
+ * This list-traversal primitive may safely run concurrently with
+ * the _rcu list-mutation primitives such as hlist_add_head_rcu()
+ * as long as the traversal is guarded by rcu_read_lock().
+ *
+ * This is the same as hlist_for_each_entry_rcu() except that it does
+ * not do any RCU debugging or tracing.
+ */
+#define hlist_for_each_entry_rcu_notrace(pos, head, member)                     \
+        for (pos = hlist_entry_safe (rcu_dereference_raw_notrace(hlist_first_rcu(head)),\
+                        typeof(*(pos)), member);                        \
+                pos;                                                    \
+                pos = hlist_entry_safe(rcu_dereference_raw_notrace(hlist_next_rcu(\
+                        &(pos)->member)), typeof(*(pos)), member))
+
+/**
  * hlist_for_each_entry_rcu_bh - iterate over rcu list of given type
  * @pos:        the type * to use as a loop cursor.
  * @head:       the head for your list.
diff --git a/include/linux/rculist_nulls.h b/include/linux/rculist_nulls.h
index 2ae13714828b..1c33dd7da4a7 100644
--- a/include/linux/rculist_nulls.h
+++ b/include/linux/rculist_nulls.h
@@ -105,9 +105,14 @@ static inline void hlist_nulls_add_head_rcu(struct hlist_nulls_node *n,
  * @head:       the head for your list.
  * @member:     the name of the hlist_nulls_node within the struct.
  *
+ * The barrier() is needed to make sure compiler doesn't cache first element [1],
+ * as this loop can be restarted [2]
+ * [1] Documentation/atomic_ops.txt around line 114
+ * [2] Documentation/RCU/rculist_nulls.txt around line 146
  */
 #define hlist_nulls_for_each_entry_rcu(tpos, pos, head, member)                 \
-        for (pos = rcu_dereference_raw(hlist_nulls_first_rcu(head));            \
+        for (({barrier();}),                                                    \
+             pos = rcu_dereference_raw(hlist_nulls_first_rcu(head));            \
                 (!is_a_nulls(pos)) &&                                           \
                 ({ tpos = hlist_nulls_entry(pos, typeof(*tpos), member); 1; }); \
                 pos = rcu_dereference_raw(hlist_nulls_next_rcu(pos)))
diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h
index 4ccd68e49b00..ddcc7826d907 100644
--- a/include/linux/rcupdate.h
+++ b/include/linux/rcupdate.h
@@ -640,6 +640,15 @@ static inline void rcu_preempt_sleep_check(void)
 
 #define rcu_dereference_raw(p) rcu_dereference_check(p, 1) /*@@@ needed? @@@*/
 
+/*
+ * The tracing infrastructure traces RCU (we want that), but unfortunately
+ * some of the RCU checks causes tracing to lock up the system.
+ *
+ * The tracing version of rcu_dereference_raw() must not call
+ * rcu_read_lock_held().
+ */
+#define rcu_dereference_raw_notrace(p) __rcu_dereference_check((p), 1, __rcu)
+
 /**
  * rcu_access_index() - fetch RCU index with no dereferencing
  * @p: The index to read
diff --git a/include/linux/scatterlist.h b/include/linux/scatterlist.h
index 5951e3f38878..26806775b11b 100644
--- a/include/linux/scatterlist.h
+++ b/include/linux/scatterlist.h
@@ -111,6 +111,9 @@ static inline struct page *sg_page(struct scatterlist *sg)
 static inline void sg_set_buf(struct scatterlist *sg, const void *buf,
                               unsigned int buflen)
 {
+#ifdef CONFIG_DEBUG_SG
+        BUG_ON(!virt_addr_valid(buf));
+#endif
         sg_set_page(sg, virt_to_page(buf), buflen, offset_in_page(buf));
 }
 
diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index 2e0ced1af3b1..9c676eae3968 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -2852,6 +2852,21 @@ static inline int skb_tnl_header_len(const struct sk_buff *inner_skb)
                 SKB_GSO_CB(inner_skb)->mac_offset;
 }
 
+static inline int gso_pskb_expand_head(struct sk_buff *skb, int extra)
+{
+        int new_headroom, headroom;
+        int ret;
+
+        headroom = skb_headroom(skb);
+        ret = pskb_expand_head(skb, extra, 0, GFP_ATOMIC);
+        if (ret)
+                return ret;
+
+        new_headroom = skb_headroom(skb);
+        SKB_GSO_CB(skb)->mac_offset += (new_headroom - headroom);
+        return 0;
+}
+
 static inline bool skb_is_gso(const struct sk_buff *skb)
 {
         return skb_shinfo(skb)->gso_size;
diff --git a/include/linux/smp.h b/include/linux/smp.h
index e6564c1dc552..c8488763277f 100644
--- a/include/linux/smp.h
+++ b/include/linux/smp.h
@@ -11,6 +11,7 @@
 #include <linux/list.h>
 #include <linux/cpumask.h>
 #include <linux/init.h>
+#include <linux/irqflags.h>
 
 extern void cpu_idle(void);
 
@@ -139,13 +140,17 @@ static inline int up_smp_call_function(smp_call_func_t func, void *info)
 }
 #define smp_call_function(func, info, wait) \
                         (up_smp_call_function(func, info))
-#define on_each_cpu(func,info,wait)             \
-        ({                                      \
-                local_irq_disable();            \
-                func(info);                     \
-                local_irq_enable();             \
-                0;                              \
-        })
+
+static inline int on_each_cpu(smp_call_func_t func, void *info, int wait)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        func(info);
+        local_irq_restore(flags);
+        return 0;
+}
+
 /*
  * Note we still need to test the mask even for UP
  * because we actually can get an empty mask from
diff --git a/include/linux/socket.h b/include/linux/socket.h
index 33bf2dfab19d..b10ce4b341ea 100644
--- a/include/linux/socket.h
+++ b/include/linux/socket.h
@@ -320,6 +320,9 @@ extern int put_cmsg(struct msghdr*, int level, int type, int len, void *data);
 
 struct timespec;
 
+/* The __sys_...msg variants allow MSG_CMSG_COMPAT */
+extern long __sys_recvmsg(int fd, struct msghdr __user *msg, unsigned flags);
+extern long __sys_sendmsg(int fd, struct msghdr __user *msg, unsigned flags);
 extern int __sys_recvmmsg(int fd, struct mmsghdr __user *mmsg, unsigned int vlen,
                           unsigned int flags, struct timespec *timeout);
 extern int __sys_sendmmsg(int fd, struct mmsghdr __user *mmsg,
diff --git a/include/linux/swapops.h b/include/linux/swapops.h
index 47ead515c811..c5fd30d2a415 100644
--- a/include/linux/swapops.h
+++ b/include/linux/swapops.h
@@ -137,6 +137,7 @@ static inline void make_migration_entry_read(swp_entry_t *entry)
 
 extern void migration_entry_wait(struct mm_struct *mm, pmd_t *pmd,
                                         unsigned long address);
+extern void migration_entry_wait_huge(struct mm_struct *mm, pte_t *pte);
 #else
 
 #define make_migration_entry(page, write) swp_entry(0, 0)
@@ -148,6 +149,8 @@ static inline int is_migration_entry(swp_entry_t swp)
 static inline void make_migration_entry_read(swp_entry_t *entryp) { }
 static inline void migration_entry_wait(struct mm_struct *mm, pmd_t *pmd,
                                          unsigned long address) { }
+static inline void migration_entry_wait_huge(struct mm_struct *mm,
+                                        pte_t *pte) { }
 static inline int is_write_migration_entry(swp_entry_t entry)
 {
         return 0;
diff --git a/include/linux/syslog.h b/include/linux/syslog.h
index 38911391a139..98a3153c0f96 100644
--- a/include/linux/syslog.h
+++ b/include/linux/syslog.h
@@ -44,8 +44,8 @@
 /* Return size of the log buffer */
 #define SYSLOG_ACTION_SIZE_BUFFER   10
 
-#define SYSLOG_FROM_CALL 0
-#define SYSLOG_FROM_FILE 1
+#define SYSLOG_FROM_READER           0
+#define SYSLOG_FROM_PROC             1
 
 int do_syslog(int type, char __user *buf, int count, bool from_file);
 
diff --git a/include/linux/tracepoint.h b/include/linux/tracepoint.h
index 2f322c38bd4d..f8e084d0fc77 100644
--- a/include/linux/tracepoint.h
+++ b/include/linux/tracepoint.h
@@ -145,8 +145,8 @@ static inline void tracepoint_synchronize_unregister(void)
                                 TP_PROTO(data_proto),                   \
                                 TP_ARGS(data_args),                     \
                                 TP_CONDITION(cond),                     \
-                                rcu_idle_exit(),                        \
-                                rcu_idle_enter());                      \
+                                rcu_irq_enter(),                        \
+                                rcu_irq_exit());                        \
         }
 #else
 #define __DECLARE_TRACE_RCU(name, proto, args, cond, data_proto, data_args)
diff --git a/include/linux/usb/ehci_pdriver.h b/include/linux/usb/ehci_pdriver.h
index 99238b096f7e..7eb4dcd0d386 100644
--- a/include/linux/usb/ehci_pdriver.h
+++ b/include/linux/usb/ehci_pdriver.h
@@ -19,6 +19,9 @@
 #ifndef __USB_CORE_EHCI_PDRIVER_H
 #define __USB_CORE_EHCI_PDRIVER_H
 
+struct platform_device;
+struct usb_hcd;
+
 /**
  * struct usb_ehci_pdata - platform_data for generic ehci driver
  *
@@ -50,6 +53,7 @@ struct usb_ehci_pdata {
         /* Turn on only VBUS suspend power and hotplug detection,
          * turn off everything else */
         void (*power_suspend)(struct platform_device *pdev);
+        int (*pre_setup)(struct usb_hcd *hcd);
 };
 
 #endif /* __USB_CORE_EHCI_PDRIVER_H */
diff --git a/include/net/addrconf.h b/include/net/addrconf.h
index 84a6440f1f19..21f702704f24 100644
--- a/include/net/addrconf.h
+++ b/include/net/addrconf.h
@@ -65,7 +65,7 @@ extern int			addrconf_set_dstaddr(struct net *net,
 
 extern int                      ipv6_chk_addr(struct net *net,
                                               const struct in6_addr *addr,
-                                              struct net_device *dev,
+                                              const struct net_device *dev,
                                               int strict);
 
 #if defined(CONFIG_IPV6_MIP6) || defined(CONFIG_IPV6_MIP6_MODULE)
diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h
index 35a57cd1704c..7cb6d360d147 100644
--- a/include/net/bluetooth/hci_core.h
+++ b/include/net/bluetooth/hci_core.h
@@ -1117,6 +1117,7 @@ void hci_sock_dev_event(struct hci_dev *hdev, int event);
 int mgmt_control(struct sock *sk, struct msghdr *msg, size_t len);
 int mgmt_index_added(struct hci_dev *hdev);
 int mgmt_index_removed(struct hci_dev *hdev);
+int mgmt_set_powered_failed(struct hci_dev *hdev, int err);
 int mgmt_powered(struct hci_dev *hdev, u8 powered);
 int mgmt_discoverable(struct hci_dev *hdev, u8 discoverable);
 int mgmt_connectable(struct hci_dev *hdev, u8 connectable);
diff --git a/include/net/bluetooth/mgmt.h b/include/net/bluetooth/mgmt.h
index 22980a7c3873..9944c3e68c5d 100644
--- a/include/net/bluetooth/mgmt.h
+++ b/include/net/bluetooth/mgmt.h
@@ -42,6 +42,7 @@
 #define MGMT_STATUS_NOT_POWERED         0x0f
 #define MGMT_STATUS_CANCELLED           0x10
 #define MGMT_STATUS_INVALID_INDEX       0x11
+#define MGMT_STATUS_RFKILLED            0x12
 
 struct mgmt_hdr {
         __le16  opcode;
diff --git a/include/net/ip_tunnels.h b/include/net/ip_tunnels.h
index 4b6f0b28f41f..09b1360e10bf 100644
--- a/include/net/ip_tunnels.h
+++ b/include/net/ip_tunnels.h
@@ -95,10 +95,10 @@ struct ip_tunnel_net {
 int ip_tunnel_init(struct net_device *dev);
 void ip_tunnel_uninit(struct net_device *dev);
 void  ip_tunnel_dellink(struct net_device *dev, struct list_head *head);
-int __net_init ip_tunnel_init_net(struct net *net, int ip_tnl_net_id,
-                                  struct rtnl_link_ops *ops, char *devname);
+int ip_tunnel_init_net(struct net *net, int ip_tnl_net_id,
+                       struct rtnl_link_ops *ops, char *devname);
 
-void __net_exit ip_tunnel_delete_net(struct ip_tunnel_net *itn);
+void ip_tunnel_delete_net(struct ip_tunnel_net *itn);
 
 void ip_tunnel_xmit(struct sk_buff *skb, struct net_device *dev,
                     const struct iphdr *tnl_params);
diff --git a/include/net/sch_generic.h b/include/net/sch_generic.h
index f10818fc8804..e7f4e21cc3e1 100644
--- a/include/net/sch_generic.h
+++ b/include/net/sch_generic.h
@@ -679,22 +679,26 @@ static inline struct sk_buff *skb_act_clone(struct sk_buff *skb, gfp_t gfp_mask,
 #endif
 
 struct psched_ratecfg {
-        u64 rate_bps;
-        u32 mult;
-        u32 shift;
+        u64     rate_bps;
+        u32     mult;
+        u16     overhead;
+        u8      shift;
 };
 
 static inline u64 psched_l2t_ns(const struct psched_ratecfg *r,
                                 unsigned int len)
 {
-        return ((u64)len * r->mult) >> r->shift;
+        return ((u64)(len + r->overhead) * r->mult) >> r->shift;
 }
 
-extern void psched_ratecfg_precompute(struct psched_ratecfg *r, u32 rate);
+extern void psched_ratecfg_precompute(struct psched_ratecfg *r, const struct tc_ratespec *conf);
 
-static inline u32 psched_ratecfg_getrate(const struct psched_ratecfg *r)
+static inline void psched_ratecfg_getrate(struct tc_ratespec *res,
+                                          const struct psched_ratecfg *r)
 {
-        return r->rate_bps >> 3;
+        memset(res, 0, sizeof(*res));
+        res->rate = r->rate_bps >> 3;
+        res->overhead = r->overhead;
 }
 
 #endif
diff --git a/include/net/xfrm.h b/include/net/xfrm.h
index ae16531d0d35..94ce082b29dc 100644
--- a/include/net/xfrm.h
+++ b/include/net/xfrm.h
@@ -1160,6 +1160,8 @@ static inline void xfrm_sk_free_policy(struct sock *sk)
         }
 }
 
+extern void xfrm_garbage_collect(struct net *net);
+
 #else
 
 static inline void xfrm_sk_free_policy(struct sock *sk) {}
@@ -1194,6 +1196,9 @@ static inline int xfrm6_policy_check_reverse(struct sock *sk, int dir,
 {
         return 1;
 }
+static inline void xfrm_garbage_collect(struct net *net)
+{
+}
 #endif
 
 static __inline__
diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h
index d4609029f014..385c6329a967 100644
--- a/include/sound/soc-dapm.h
+++ b/include/sound/soc-dapm.h
@@ -450,7 +450,8 @@ enum snd_soc_dapm_type {
         snd_soc_dapm_aif_in,            /* audio interface input */
         snd_soc_dapm_aif_out,           /* audio interface output */
         snd_soc_dapm_siggen,            /* signal generator */
-        snd_soc_dapm_dai,               /* link to DAI structure */
+        snd_soc_dapm_dai_in,            /* link to DAI structure */
+        snd_soc_dapm_dai_out,
         snd_soc_dapm_dai_link,          /* link between two DAI structures */
 };
 
diff --git a/include/target/target_core_base.h b/include/target/target_core_base.h
index e773dfa5f98f..4ea4f985f394 100644
--- a/include/target/target_core_base.h
+++ b/include/target/target_core_base.h
@@ -543,6 +543,7 @@ struct se_session {
         struct list_head        sess_list;
         struct list_head        sess_acl_list;
         struct list_head        sess_cmd_list;
+        struct list_head        sess_wait_list;
         spinlock_t              sess_cmd_lock;
         struct kref             sess_kref;
 };
diff --git a/include/target/target_core_fabric.h b/include/target/target_core_fabric.h
index ba3471b73c07..1dcce9cc99b9 100644
--- a/include/target/target_core_fabric.h
+++ b/include/target/target_core_fabric.h
@@ -114,7 +114,7 @@ sense_reason_t	transport_generic_new_cmd(struct se_cmd *);
 
 void    target_execute_cmd(struct se_cmd *cmd);
 
-void    transport_generic_free_cmd(struct se_cmd *, int);
+int     transport_generic_free_cmd(struct se_cmd *, int);
 
 bool    transport_wait_for_tasks(struct se_cmd *);
 int     transport_check_aborted_status(struct se_cmd *, int);
@@ -123,7 +123,7 @@ int	transport_send_check_condition_and_sense(struct se_cmd *,
 int     target_get_sess_cmd(struct se_session *, struct se_cmd *, bool);
 int     target_put_sess_cmd(struct se_session *, struct se_cmd *);
 void    target_sess_cmd_list_set_waiting(struct se_session *);
-void    target_wait_for_sess_cmds(struct se_session *, int);
+void    target_wait_for_sess_cmds(struct se_session *);
 
 int     core_alua_check_nonop_delay(struct se_cmd *);
 
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index a5c86fc34a37..d88c8ee00c8b 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -783,6 +783,7 @@ struct kvm_dirty_tlb {
 #define KVM_REG_IA64            0x3000000000000000ULL
 #define KVM_REG_ARM             0x4000000000000000ULL
 #define KVM_REG_S390            0x5000000000000000ULL
+#define KVM_REG_MIPS            0x7000000000000000ULL
 
 #define KVM_REG_SIZE_SHIFT      52
 #define KVM_REG_SIZE_MASK       0x00f0000000000000ULL
diff --git a/include/video/omapdss.h b/include/video/omapdss.h
index 62ca9a77c1d6..aeb4e9a0c5d1 100644
--- a/include/video/omapdss.h
+++ b/include/video/omapdss.h
@@ -748,6 +748,7 @@ struct omap_dss_driver {
 };
 
 enum omapdss_version omapdss_get_version(void);
+bool omapdss_is_initialized(void);
 
 int omap_dss_register_driver(struct omap_dss_driver *);
 void omap_dss_unregister_driver(struct omap_dss_driver *);
diff --git a/include/xen/xenbus.h b/include/xen/xenbus.h
index 0a7515c1e3a4..569c07f2e344 100644
--- a/include/xen/xenbus.h
+++ b/include/xen/xenbus.h
@@ -70,6 +70,7 @@ struct xenbus_device {
         struct device dev;
         enum xenbus_state state;
         struct completion down;
+        struct work_struct work;
 };
 
 static inline struct xenbus_device *to_xenbus_device(struct device *dev)
diff --git a/init/Kconfig b/init/Kconfig
index 9d3a7887a6d3..2d9b83104dcf 100644
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -431,6 +431,7 @@ choice
 config TREE_RCU
         bool "Tree-based hierarchical RCU"
         depends on !PREEMPT && SMP
+        select IRQ_WORK
         help
           This option selects the RCU implementation that is
           designed for very large SMP system with hundreds or
diff --git a/kernel/audit.c b/kernel/audit.c
index 21c7fa615bd3..91e53d04b6a9 100644
--- a/kernel/audit.c
+++ b/kernel/audit.c
@@ -1056,7 +1056,7 @@ static inline void audit_get_stamp(struct audit_context *ctx,
 static void wait_for_auditd(unsigned long sleep_time)
 {
         DECLARE_WAITQUEUE(wait, current);
-        set_current_state(TASK_INTERRUPTIBLE);
+        set_current_state(TASK_UNINTERRUPTIBLE);
         add_wait_queue(&audit_backlog_wait, &wait);
 
         if (audit_backlog_limit &&
diff --git a/kernel/audit_tree.c b/kernel/audit_tree.c
index a291aa23fb3f..43c307dc9453 100644
--- a/kernel/audit_tree.c
+++ b/kernel/audit_tree.c
@@ -658,6 +658,7 @@ int audit_add_tree_rule(struct audit_krule *rule)
         struct vfsmount *mnt;
         int err;
 
+        rule->tree = NULL;
         list_for_each_entry(tree, &tree_list, list) {
                 if (!strcmp(seed->pathname, tree->pathname)) {
                         put_tree(seed);
diff --git a/kernel/cgroup.c b/kernel/cgroup.c
index 2a9926275f80..a7c9e6ddb979 100644
--- a/kernel/cgroup.c
+++ b/kernel/cgroup.c
@@ -1686,11 +1686,14 @@ static struct dentry *cgroup_mount(struct file_system_type *fs_type,
                  */
                 cgroup_drop_root(opts.new_root);
 
-                if (((root->flags | opts.flags) & CGRP_ROOT_SANE_BEHAVIOR) &&
-                    root->flags != opts.flags) {
-                        pr_err("cgroup: sane_behavior: new mount options should match the existing superblock\n");
-                        ret = -EINVAL;
-                        goto drop_new_super;
+                if (root->flags != opts.flags) {
+                        if ((root->flags | opts.flags) & CGRP_ROOT_SANE_BEHAVIOR) {
+                                pr_err("cgroup: sane_behavior: new mount options should match the existing superblock\n");
+                                ret = -EINVAL;
+                                goto drop_new_super;
+                        } else {
+                                pr_warning("cgroup: new mount options do not match the existing superblock, will be ignored\n");
+                        }
                 }
 
                 /* no subsys rebinding, so refcounts don't change */
@@ -2699,13 +2702,14 @@ static int cgroup_add_file(struct cgroup *cgrp, struct cgroup_subsys *subsys,
                 goto out;
         }
 
+        cfe->type = (void *)cft;
+        cfe->dentry = dentry;
+        dentry->d_fsdata = cfe;
+        simple_xattrs_init(&cfe->xattrs);
+
         mode = cgroup_file_mode(cft);
         error = cgroup_create_file(dentry, mode | S_IFREG, cgrp->root->sb);
         if (!error) {
-                cfe->type = (void *)cft;
-                cfe->dentry = dentry;
-                dentry->d_fsdata = cfe;
-                simple_xattrs_init(&cfe->xattrs);
                 list_add_tail(&cfe->node, &parent->files);
                 cfe = NULL;
         }
@@ -2953,11 +2957,8 @@ struct cgroup *cgroup_next_descendant_pre(struct cgroup *pos,
         WARN_ON_ONCE(!rcu_read_lock_held());
 
         /* if first iteration, pretend we just visited @cgroup */
-        if (!pos) {
-                if (list_empty(&cgroup->children))
-                        return NULL;
+        if (!pos)
                 pos = cgroup;
-        }
 
         /* visit the first child if exists */
         next = list_first_or_null_rcu(&pos->children, struct cgroup, sibling);
@@ -2965,14 +2966,14 @@ struct cgroup *cgroup_next_descendant_pre(struct cgroup *pos,
                 return next;
 
         /* no child, visit my or the closest ancestor's next sibling */
-        do {
+        while (pos != cgroup) {
                 next = list_entry_rcu(pos->sibling.next, struct cgroup,
                                       sibling);
                 if (&next->sibling != &pos->parent->children)
                         return next;
 
                 pos = pos->parent;
-        } while (pos != cgroup);
+        }
 
         return NULL;
 }
diff --git a/kernel/cpu.c b/kernel/cpu.c
index b5e4ab2d427e..198a38883e64 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -133,6 +133,27 @@ static void cpu_hotplug_done(void)
         mutex_unlock(&cpu_hotplug.lock);
 }
 
+/*
+ * Wait for currently running CPU hotplug operations to complete (if any) and
+ * disable future CPU hotplug (from sysfs). The 'cpu_add_remove_lock' protects
+ * the 'cpu_hotplug_disabled' flag. The same lock is also acquired by the
+ * hotplug path before performing hotplug operations. So acquiring that lock
+ * guarantees mutual exclusion from any currently running hotplug operations.
+ */
+void cpu_hotplug_disable(void)
+{
+        cpu_maps_update_begin();
+        cpu_hotplug_disabled = 1;
+        cpu_maps_update_done();
+}
+
+void cpu_hotplug_enable(void)
+{
+        cpu_maps_update_begin();
+        cpu_hotplug_disabled = 0;
+        cpu_maps_update_done();
+}
+
 #else /* #if CONFIG_HOTPLUG_CPU */
 static void cpu_hotplug_begin(void) {}
 static void cpu_hotplug_done(void) {}
@@ -541,36 +562,6 @@ static int __init alloc_frozen_cpus(void)
 core_initcall(alloc_frozen_cpus);
 
 /*
- * Prevent regular CPU hotplug from racing with the freezer, by disabling CPU
- * hotplug when tasks are about to be frozen. Also, don't allow the freezer
- * to continue until any currently running CPU hotplug operation gets
- * completed.
- * To modify the 'cpu_hotplug_disabled' flag, we need to acquire the
- * 'cpu_add_remove_lock'. And this same lock is also taken by the regular
- * CPU hotplug path and released only after it is complete. Thus, we
- * (and hence the freezer) will block here until any currently running CPU
- * hotplug operation gets completed.
- */
-void cpu_hotplug_disable_before_freeze(void)
-{
-        cpu_maps_update_begin();
-        cpu_hotplug_disabled = 1;
-        cpu_maps_update_done();
-}
-
-
-/*
- * When tasks have been thawed, re-enable regular CPU hotplug (which had been
- * disabled while beginning to freeze tasks).
- */
-void cpu_hotplug_enable_after_thaw(void)
-{
-        cpu_maps_update_begin();
-        cpu_hotplug_disabled = 0;
-        cpu_maps_update_done();
-}
-
-/*
  * When callbacks for CPU hotplug notifications are being executed, we must
  * ensure that the state of the system with respect to the tasks being frozen
  * or not, as reported by the notification, remains unchanged *throughout the
@@ -589,12 +580,12 @@ cpu_hotplug_pm_callback(struct notifier_block *nb,
 
         case PM_SUSPEND_PREPARE:
         case PM_HIBERNATION_PREPARE:
-                cpu_hotplug_disable_before_freeze();
+                cpu_hotplug_disable();
                 break;
 
         case PM_POST_SUSPEND:
         case PM_POST_HIBERNATION:
-                cpu_hotplug_enable_after_thaw();
+                cpu_hotplug_enable();
                 break;
 
         default:
diff --git a/kernel/exit.c b/kernel/exit.c
index af2eb3cbd499..7bb73f9d09db 100644
--- a/kernel/exit.c
+++ b/kernel/exit.c
@@ -649,7 +649,6 @@ static void exit_notify(struct task_struct *tsk, int group_dead)
          *      jobs, send them a SIGHUP and then a SIGCONT.  (POSIX 3.2.2.2)
          */
         forget_original_parent(tsk);
-        exit_task_namespaces(tsk);
 
         write_lock_irq(&tasklist_lock);
         if (group_dead)
@@ -795,6 +794,7 @@ void do_exit(long code)
         exit_shm(tsk);
         exit_files(tsk);
         exit_fs(tsk);
+        exit_task_namespaces(tsk);
         exit_task_work(tsk);
         check_stack_usage();
         exit_thread();
diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c
index 5a83dde8ca0c..54a4d5223238 100644
--- a/kernel/irq/irqdomain.c
+++ b/kernel/irq/irqdomain.c
@@ -143,7 +143,10 @@ static unsigned int irq_domain_legacy_revmap(struct irq_domain *domain,
  * irq_domain_add_simple() - Allocate and register a simple irq_domain.
  * @of_node: pointer to interrupt controller's device tree node.
  * @size: total number of irqs in mapping
- * @first_irq: first number of irq block assigned to the domain
+ * @first_irq: first number of irq block assigned to the domain,
+ *      pass zero to assign irqs on-the-fly. This will result in a
+ *      linear IRQ domain so it is important to use irq_create_mapping()
+ *      for each used IRQ, especially when SPARSE_IRQ is enabled.
  * @ops: map/unmap domain callbacks
  * @host_data: Controller private data pointer
  *
@@ -191,6 +194,7 @@ struct irq_domain *irq_domain_add_simple(struct device_node *of_node,
         /* A linear domain is the default */
         return irq_domain_add_linear(of_node, size, ops, host_data);
 }
+EXPORT_SYMBOL_GPL(irq_domain_add_simple);
 
 /**
  * irq_domain_add_legacy() - Allocate and register a legacy revmap irq_domain.
@@ -397,11 +401,12 @@ static void irq_domain_disassociate_many(struct irq_domain *domain,
         while (count--) {
                 int irq = irq_base + count;
                 struct irq_data *irq_data = irq_get_irq_data(irq);
-                irq_hw_number_t hwirq = irq_data->hwirq;
+                irq_hw_number_t hwirq;
 
                 if (WARN_ON(!irq_data || irq_data->domain != domain))
                         continue;
 
+                hwirq = irq_data->hwirq;
                 irq_set_status_flags(irq, IRQ_NOREQUEST);
 
                 /* remove chip and handler */
diff --git a/kernel/printk.c b/kernel/printk.c
index fa36e1494420..8212c1aef125 100644
--- a/kernel/printk.c
+++ b/kernel/printk.c
@@ -363,6 +363,53 @@ static void log_store(int facility, int level,
         log_next_seq++;
 }
 
+#ifdef CONFIG_SECURITY_DMESG_RESTRICT
+int dmesg_restrict = 1;
+#else
+int dmesg_restrict;
+#endif
+
+static int syslog_action_restricted(int type)
+{
+        if (dmesg_restrict)
+                return 1;
+        /*
+         * Unless restricted, we allow "read all" and "get buffer size"
+         * for everybody.
+         */
+        return type != SYSLOG_ACTION_READ_ALL &&
+               type != SYSLOG_ACTION_SIZE_BUFFER;
+}
+
+static int check_syslog_permissions(int type, bool from_file)
+{
+        /*
+         * If this is from /proc/kmsg and we've already opened it, then we've
+         * already done the capabilities checks at open time.
+         */
+        if (from_file && type != SYSLOG_ACTION_OPEN)
+                return 0;
+
+        if (syslog_action_restricted(type)) {
+                if (capable(CAP_SYSLOG))
+                        return 0;
+                /*
+                 * For historical reasons, accept CAP_SYS_ADMIN too, with
+                 * a warning.
+                 */
+                if (capable(CAP_SYS_ADMIN)) {
+                        pr_warn_once("%s (%d): Attempt to access syslog with "
+                                     "CAP_SYS_ADMIN but no CAP_SYSLOG "
+                                     "(deprecated).\n",
+                                 current->comm, task_pid_nr(current));
+                        return 0;
+                }
+                return -EPERM;
+        }
+        return security_syslog(type);
+}
+
+
 /* /dev/kmsg - userspace message inject/listen interface */
 struct devkmsg_user {
         u64 seq;
@@ -620,7 +667,8 @@ static int devkmsg_open(struct inode *inode, struct file *file)
         if ((file->f_flags & O_ACCMODE) == O_WRONLY)
                 return 0;
 
-        err = security_syslog(SYSLOG_ACTION_READ_ALL);
+        err = check_syslog_permissions(SYSLOG_ACTION_READ_ALL,
+                                       SYSLOG_FROM_READER);
         if (err)
                 return err;
 
@@ -813,45 +861,6 @@ static inline void boot_delay_msec(int level)
 }
 #endif
 
-#ifdef CONFIG_SECURITY_DMESG_RESTRICT
-int dmesg_restrict = 1;
-#else
-int dmesg_restrict;
-#endif
-
-static int syslog_action_restricted(int type)
-{
-        if (dmesg_restrict)
-                return 1;
-        /* Unless restricted, we allow "read all" and "get buffer size" for everybody */
-        return type != SYSLOG_ACTION_READ_ALL && type != SYSLOG_ACTION_SIZE_BUFFER;
-}
-
-static int check_syslog_permissions(int type, bool from_file)
-{
-        /*
-         * If this is from /proc/kmsg and we've already opened it, then we've
-         * already done the capabilities checks at open time.
-         */
-        if (from_file && type != SYSLOG_ACTION_OPEN)
-                return 0;
-
-        if (syslog_action_restricted(type)) {
-                if (capable(CAP_SYSLOG))
-                        return 0;
-                /* For historical reasons, accept CAP_SYS_ADMIN too, with a warning */
-                if (capable(CAP_SYS_ADMIN)) {
-                        printk_once(KERN_WARNING "%s (%d): "
-                                 "Attempt to access syslog with CAP_SYS_ADMIN "
-                                 "but no CAP_SYSLOG (deprecated).\n",
-                                 current->comm, task_pid_nr(current));
-                        return 0;
-                }
-                return -EPERM;
-        }
-        return 0;
-}
-
 #if defined(CONFIG_PRINTK_TIME)
 static bool printk_time = 1;
 #else
@@ -1249,7 +1258,7 @@ out:
 
 SYSCALL_DEFINE3(syslog, int, type, char __user *, buf, int, len)
 {
-        return do_syslog(type, buf, len, SYSLOG_FROM_CALL);
+        return do_syslog(type, buf, len, SYSLOG_FROM_READER);
 }
 
 /*
diff --git a/kernel/range.c b/kernel/range.c
index 071b0ab455cb..eb911dbce267 100644
--- a/kernel/range.c
+++ b/kernel/range.c
@@ -48,9 +48,11 @@ int add_range_with_merge(struct range *range, int az, int nr_range,
                 final_start = min(range[i].start, start);
                 final_end = max(range[i].end, end);
 
-                range[i].start = final_start;
-                range[i].end =  final_end;
-                return nr_range;
+                /* clear it and add it back for further merge */
+                range[i].start = 0;
+                range[i].end =  0;
+                return add_range_with_merge(range, az, nr_range,
+                        final_start, final_end);
         }
 
         /* Need to add it: */
diff --git a/kernel/rcutree.c b/kernel/rcutree.c
index 16ea67925015..35380019f0fc 100644
--- a/kernel/rcutree.c
+++ b/kernel/rcutree.c
@@ -1451,9 +1451,9 @@ static int rcu_gp_init(struct rcu_state *rsp)
                                             rnp->grphi, rnp->qsmask);
                 raw_spin_unlock_irq(&rnp->lock);
 #ifdef CONFIG_PROVE_RCU_DELAY
-                if ((prandom_u32() % (rcu_num_nodes * 8)) == 0 &&
+                if ((prandom_u32() % (rcu_num_nodes + 1)) == 0 &&
                     system_state == SYSTEM_RUNNING)
-                        schedule_timeout_uninterruptible(2);
+                        udelay(200);
 #endif /* #ifdef CONFIG_PROVE_RCU_DELAY */
                 cond_resched();
         }
@@ -1613,6 +1613,14 @@ static int __noreturn rcu_gp_kthread(void *arg)
         }
 }
 
+static void rsp_wakeup(struct irq_work *work)
+{
+        struct rcu_state *rsp = container_of(work, struct rcu_state, wakeup_work);
+
+        /* Wake up rcu_gp_kthread() to start the grace period. */
+        wake_up(&rsp->gp_wq);
+}
+
 /*
  * Start a new RCU grace period if warranted, re-initializing the hierarchy
  * in preparation for detecting the next grace period.  The caller must hold
@@ -1637,8 +1645,12 @@ rcu_start_gp_advanced(struct rcu_state *rsp, struct rcu_node *rnp,
         }
         rsp->gp_flags = RCU_GP_FLAG_INIT;
 
-        /* Wake up rcu_gp_kthread() to start the grace period. */
-        wake_up(&rsp->gp_wq);
+        /*
+         * We can't do wakeups while holding the rnp->lock, as that
+         * could cause possible deadlocks with the rq->lock. Deter
+         * the wakeup to interrupt context.
+         */
+        irq_work_queue(&rsp->wakeup_work);
 }
 
 /*
@@ -3235,6 +3247,7 @@ static void __init rcu_init_one(struct rcu_state *rsp,
 
         rsp->rda = rda;
         init_waitqueue_head(&rsp->gp_wq);
+        init_irq_work(&rsp->wakeup_work, rsp_wakeup);
         rnp = rsp->level[rcu_num_lvls - 1];
         for_each_possible_cpu(i) {
                 while (i > rnp->grphi)
diff --git a/kernel/rcutree.h b/kernel/rcutree.h
index da77a8f57ff9..4df503470e42 100644
--- a/kernel/rcutree.h
+++ b/kernel/rcutree.h
@@ -27,6 +27,7 @@
 #include <linux/threads.h>
 #include <linux/cpumask.h>
 #include <linux/seqlock.h>
+#include <linux/irq_work.h>
 
 /*
  * Define shape of hierarchy based on NR_CPUS, CONFIG_RCU_FANOUT, and
@@ -442,6 +443,7 @@ struct rcu_state {
         char *name;                             /* Name of structure. */
         char abbr;                              /* Abbreviated name. */
         struct list_head flavors;               /* List of RCU flavors. */
+        struct irq_work wakeup_work;            /* Postponed wakeups */
 };
 
 /* Values for rcu_state structure's gp_flags field. */
diff --git a/kernel/softirq.c b/kernel/softirq.c
index b5197dcb0dad..3d6833f125d3 100644
--- a/kernel/softirq.c
+++ b/kernel/softirq.c
@@ -195,8 +195,12 @@ void local_bh_enable_ip(unsigned long ip)
 EXPORT_SYMBOL(local_bh_enable_ip);
 
 /*
- * We restart softirq processing for at most 2 ms,
- * and if need_resched() is not set.
+ * We restart softirq processing for at most MAX_SOFTIRQ_RESTART times,
+ * but break the loop if need_resched() is set or after 2 ms.
+ * The MAX_SOFTIRQ_TIME provides a nice upper bound in most cases, but in
+ * certain cases, such as stop_machine(), jiffies may cease to
+ * increment and so we need the MAX_SOFTIRQ_RESTART limit as
+ * well to make sure we eventually return from this method.
  *
  * These limits have been established via experimentation.
  * The two things to balance is latency against fairness -
@@ -204,6 +208,7 @@ EXPORT_SYMBOL(local_bh_enable_ip);
  * should not be able to lock up the box.
  */
 #define MAX_SOFTIRQ_TIME  msecs_to_jiffies(2)
+#define MAX_SOFTIRQ_RESTART 10
 
 asmlinkage void __do_softirq(void)
 {
@@ -212,6 +217,7 @@ asmlinkage void __do_softirq(void)
         unsigned long end = jiffies + MAX_SOFTIRQ_TIME;
         int cpu;
         unsigned long old_flags = current->flags;
+        int max_restart = MAX_SOFTIRQ_RESTART;
 
         /*
          * Mask out PF_MEMALLOC s current task context is borrowed for the
@@ -265,7 +271,8 @@ restart:
 
         pending = local_softirq_pending();
         if (pending) {
-                if (time_before(jiffies, end) && !need_resched())
+                if (time_before(jiffies, end) && !need_resched() &&
+                    --max_restart)
                         goto restart;
 
                 wakeup_softirqd();
diff --git a/kernel/sys.c b/kernel/sys.c
index b95d3c72ba21..2bbd9a73b54c 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -362,6 +362,29 @@ int unregister_reboot_notifier(struct notifier_block *nb)
 }
 EXPORT_SYMBOL(unregister_reboot_notifier);
 
+/* Add backwards compatibility for stable trees. */
+#ifndef PF_NO_SETAFFINITY
+#define PF_NO_SETAFFINITY               PF_THREAD_BOUND
+#endif
+
+static void migrate_to_reboot_cpu(void)
+{
+        /* The boot cpu is always logical cpu 0 */
+        int cpu = 0;
+
+        cpu_hotplug_disable();
+
+        /* Make certain the cpu I'm about to reboot on is online */
+        if (!cpu_online(cpu))
+                cpu = cpumask_first(cpu_online_mask);
+
+        /* Prevent races with other tasks migrating this task */
+        current->flags |= PF_NO_SETAFFINITY;
+
+        /* Make certain I only run on the appropriate processor */
+        set_cpus_allowed_ptr(current, cpumask_of(cpu));
+}
+
 /**
  *      kernel_restart - reboot the system
  *      @cmd: pointer to buffer containing command to execute for restart
@@ -373,7 +396,7 @@ EXPORT_SYMBOL(unregister_reboot_notifier);
 void kernel_restart(char *cmd)
 {
         kernel_restart_prepare(cmd);
-        disable_nonboot_cpus();
+        migrate_to_reboot_cpu();
         syscore_shutdown();
         if (!cmd)
                 printk(KERN_EMERG "Restarting system.\n");
@@ -400,7 +423,7 @@ static void kernel_shutdown_prepare(enum system_states state)
 void kernel_halt(void)
 {
         kernel_shutdown_prepare(SYSTEM_HALT);
-        disable_nonboot_cpus();
+        migrate_to_reboot_cpu();
         syscore_shutdown();
         printk(KERN_EMERG "System halted.\n");
         kmsg_dump(KMSG_DUMP_HALT);
@@ -419,7 +442,7 @@ void kernel_power_off(void)
         kernel_shutdown_prepare(SYSTEM_POWER_OFF);
         if (pm_power_off_prepare)
                 pm_power_off_prepare();
-        disable_nonboot_cpus();
+        migrate_to_reboot_cpu();
         syscore_shutdown();
         printk(KERN_EMERG "Power down.\n");
         kmsg_dump(KMSG_DUMP_POWEROFF);
diff --git a/kernel/time/ntp.c b/kernel/time/ntp.c
index 12ff13a838c6..8f5b3b98577b 100644
--- a/kernel/time/ntp.c
+++ b/kernel/time/ntp.c
@@ -874,7 +874,6 @@ static void hardpps_update_phase(long error)
 void __hardpps(const struct timespec *phase_ts, const struct timespec *raw_ts)
 {
         struct pps_normtime pts_norm, freq_norm;
-        unsigned long flags;
 
         pts_norm = pps_normalize_ts(*phase_ts);
 
diff --git a/kernel/time/tick-broadcast.c b/kernel/time/tick-broadcast.c
index 24938d577669..0c739423b0f9 100644
--- a/kernel/time/tick-broadcast.c
+++ b/kernel/time/tick-broadcast.c
@@ -511,6 +511,12 @@ again:
                 }
         }
 
+        /*
+         * Remove the current cpu from the pending mask. The event is
+         * delivered immediately in tick_do_broadcast() !
+         */
+        cpumask_clear_cpu(smp_processor_id(), tick_broadcast_pending_mask);
+
         /* Take care of enforced broadcast requests */
         cpumask_or(tmpmask, tmpmask, tick_broadcast_force_mask);
         cpumask_clear(tick_broadcast_force_mask);
@@ -575,8 +581,8 @@ void tick_broadcast_oneshot_control(unsigned long reason)
 
         raw_spin_lock_irqsave(&tick_broadcast_lock, flags);
         if (reason == CLOCK_EVT_NOTIFY_BROADCAST_ENTER) {
-                WARN_ON_ONCE(cpumask_test_cpu(cpu, tick_broadcast_pending_mask));
                 if (!cpumask_test_and_set_cpu(cpu, tick_broadcast_oneshot_mask)) {
+                        WARN_ON_ONCE(cpumask_test_cpu(cpu, tick_broadcast_pending_mask));
                         clockevents_set_mode(dev, CLOCK_EVT_MODE_SHUTDOWN);
                         /*
                          * We only reprogram the broadcast timer if we
diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c
index 98cd470bbe49..baeeb5c87cf1 100644
--- a/kernel/time/timekeeping.c
+++ b/kernel/time/timekeeping.c
@@ -975,6 +975,14 @@ static int timekeeping_suspend(void)
 
         read_persistent_clock(&timekeeping_suspend_time);
 
+        /*
+         * On some systems the persistent_clock can not be detected at
+         * timekeeping_init by its return value, so if we see a valid
+         * value returned, update the persistent_clock_exists flag.
+         */
+        if (timekeeping_suspend_time.tv_sec || timekeeping_suspend_time.tv_nsec)
+                persistent_clock_exist = true;
+
         raw_spin_lock_irqsave(&timekeeper_lock, flags);
         write_seqcount_begin(&timekeeper_seq);
         timekeeping_forward_now(tk);
diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c
index b549b0f5b977..6c508ff33c62 100644
--- a/kernel/trace/ftrace.c
+++ b/kernel/trace/ftrace.c
@@ -120,22 +120,22 @@ static void ftrace_ops_no_ops(unsigned long ip, unsigned long parent_ip);
 
 /*
  * Traverse the ftrace_global_list, invoking all entries.  The reason that we
- * can use rcu_dereference_raw() is that elements removed from this list
+ * can use rcu_dereference_raw_notrace() is that elements removed from this list
  * are simply leaked, so there is no need to interact with a grace-period
- * mechanism.  The rcu_dereference_raw() calls are needed to handle
+ * mechanism.  The rcu_dereference_raw_notrace() calls are needed to handle
  * concurrent insertions into the ftrace_global_list.
  *
  * Silly Alpha and silly pointer-speculation compiler optimizations!
  */
 #define do_for_each_ftrace_op(op, list)                 \
-        op = rcu_dereference_raw(list);                 \
+        op = rcu_dereference_raw_notrace(list);                 \
         do
 
 /*
  * Optimized for just a single item in the list (as that is the normal case).
  */
 #define while_for_each_ftrace_op(op)                            \
-        while (likely(op = rcu_dereference_raw((op)->next)) &&  \
+        while (likely(op = rcu_dereference_raw_notrace((op)->next)) &&  \
                unlikely((op) != &ftrace_list_end))
 
 static inline void ftrace_ops_init(struct ftrace_ops *ops)
@@ -779,7 +779,7 @@ ftrace_find_profiled_func(struct ftrace_profile_stat *stat, unsigned long ip)
         if (hlist_empty(hhd))
                 return NULL;
 
-        hlist_for_each_entry_rcu(rec, hhd, node) {
+        hlist_for_each_entry_rcu_notrace(rec, hhd, node) {
                 if (rec->ip == ip)
                         return rec;
         }
@@ -1165,7 +1165,7 @@ ftrace_lookup_ip(struct ftrace_hash *hash, unsigned long ip)
 
         hhd = &hash->buckets[key];
 
-        hlist_for_each_entry_rcu(entry, hhd, hlist) {
+        hlist_for_each_entry_rcu_notrace(entry, hhd, hlist) {
                 if (entry->ip == ip)
                         return entry;
         }
@@ -1422,8 +1422,8 @@ ftrace_ops_test(struct ftrace_ops *ops, unsigned long ip)
         struct ftrace_hash *notrace_hash;
         int ret;
 
-        filter_hash = rcu_dereference_raw(ops->filter_hash);
-        notrace_hash = rcu_dereference_raw(ops->notrace_hash);
+        filter_hash = rcu_dereference_raw_notrace(ops->filter_hash);
+        notrace_hash = rcu_dereference_raw_notrace(ops->notrace_hash);
 
         if ((ftrace_hash_empty(filter_hash) ||
              ftrace_lookup_ip(filter_hash, ip)) &&
@@ -2920,7 +2920,7 @@ static void function_trace_probe_call(unsigned long ip, unsigned long parent_ip,
          * on the hash. rcu_read_lock is too dangerous here.
          */
         preempt_disable_notrace();
-        hlist_for_each_entry_rcu(entry, hhd, node) {
+        hlist_for_each_entry_rcu_notrace(entry, hhd, node) {
                 if (entry->ip == ip)
                         entry->ops->func(ip, parent_ip, &entry->data);
         }
diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c
index b59aea2c48c2..e444ff88f0a4 100644
--- a/kernel/trace/ring_buffer.c
+++ b/kernel/trace/ring_buffer.c
@@ -620,6 +620,9 @@ int ring_buffer_poll_wait(struct ring_buffer *buffer, int cpu,
         if (cpu == RING_BUFFER_ALL_CPUS)
                 work = &buffer->irq_work;
         else {
+                if (!cpumask_test_cpu(cpu, buffer->cpumask))
+                        return -EINVAL;
+
                 cpu_buffer = buffer->buffers[cpu];
                 work = &cpu_buffer->irq_work;
         }
diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
index ae6fa2d1cdf7..e71a8be4a6ee 100644
--- a/kernel/trace/trace.c
+++ b/kernel/trace/trace.c
@@ -652,8 +652,6 @@ static struct {
         ARCH_TRACE_CLOCKS
 };
 
-int trace_clock_id;
-
 /*
  * trace_parser_get_init - gets the buffer for trace parser
  */
@@ -843,7 +841,15 @@ __update_max_tr(struct trace_array *tr, struct task_struct *tsk, int cpu)
 
         memcpy(max_data->comm, tsk->comm, TASK_COMM_LEN);
         max_data->pid = tsk->pid;
-        max_data->uid = task_uid(tsk);
+        /*
+         * If tsk == current, then use current_uid(), as that does not use
+         * RCU. The irq tracer can be called out of RCU scope.
+         */
+        if (tsk == current)
+                max_data->uid = current_uid();
+        else
+                max_data->uid = task_uid(tsk);
+
         max_data->nice = tsk->static_prio - 20 - MAX_RT_PRIO;
         max_data->policy = tsk->policy;
         max_data->rt_priority = tsk->rt_priority;
@@ -2818,7 +2824,7 @@ __tracing_open(struct inode *inode, struct file *file, bool snapshot)
                 iter->iter_flags |= TRACE_FILE_ANNOTATE;
 
         /* Output in nanoseconds only if we are using a clock in nanoseconds. */
-        if (trace_clocks[trace_clock_id].in_ns)
+        if (trace_clocks[tr->clock_id].in_ns)
                 iter->iter_flags |= TRACE_FILE_TIME_IN_NS;
 
         /* stop the trace while dumping if we are not opening "snapshot" */
@@ -3817,7 +3823,7 @@ static int tracing_open_pipe(struct inode *inode, struct file *filp)
                 iter->iter_flags |= TRACE_FILE_LAT_FMT;
 
         /* Output in nanoseconds only if we are using a clock in nanoseconds. */
-        if (trace_clocks[trace_clock_id].in_ns)
+        if (trace_clocks[tr->clock_id].in_ns)
                 iter->iter_flags |= TRACE_FILE_TIME_IN_NS;
 
         iter->cpu_file = tc->cpu;
@@ -5087,7 +5093,7 @@ tracing_stats_read(struct file *filp, char __user *ubuf,
         cnt = ring_buffer_bytes_cpu(trace_buf->buffer, cpu);
         trace_seq_printf(s, "bytes: %ld\n", cnt);
 
-        if (trace_clocks[trace_clock_id].in_ns) {
+        if (trace_clocks[tr->clock_id].in_ns) {
                 /* local or global for trace_clock */
                 t = ns2usecs(ring_buffer_oldest_event_ts(trace_buf->buffer, cpu));
                 usec_rem = do_div(t, USEC_PER_SEC);
@@ -6216,10 +6222,15 @@ __init static int tracer_alloc_buffers(void)
 
         trace_init_cmdlines();
 
-        register_tracer(&nop_trace);
-
+        /*
+         * register_tracer() might reference current_trace, so it
+         * needs to be set before we register anything. This is
+         * just a bootstrap of current_trace anyway.
+         */
         global_trace.current_trace = &nop_trace;
 
+        register_tracer(&nop_trace);
+
         /* All seems OK, enable tracing */
         tracing_disabled = 0;
 
diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h
index 711ca7d3e7f1..20572ed88c5c 100644
--- a/kernel/trace/trace.h
+++ b/kernel/trace/trace.h
@@ -700,8 +700,6 @@ enum print_line_t print_trace_line(struct trace_iterator *iter);
 
 extern unsigned long trace_flags;
 
-extern int trace_clock_id;
-
 /* Standard output formatting function used for function return traces */
 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
 
diff --git a/kernel/trace/trace_selftest.c b/kernel/trace/trace_selftest.c
index 55e2cf66967b..2901e3b88590 100644
--- a/kernel/trace/trace_selftest.c
+++ b/kernel/trace/trace_selftest.c
@@ -1159,7 +1159,7 @@ trace_selftest_startup_branch(struct tracer *trace, struct trace_array *tr)
         /* stop the tracing. */
         tracing_stop();
         /* check the trace buffer */
-        ret = trace_test_buffer(tr, &count);
+        ret = trace_test_buffer(&tr->trace_buffer, &count);
         trace->reset(tr);
         tracing_start();
 
diff --git a/lib/mpi/mpicoder.c b/lib/mpi/mpicoder.c
index 5f9c44cdf1f5..4cc6442733f4 100644
--- a/lib/mpi/mpicoder.c
+++ b/lib/mpi/mpicoder.c
@@ -37,7 +37,7 @@ MPI mpi_read_raw_data(const void *xbuffer, size_t nbytes)
         mpi_limb_t a;
         MPI val = NULL;
 
-        while (nbytes >= 0 && buffer[0] == 0) {
+        while (nbytes > 0 && buffer[0] == 0) {
                 buffer++;
                 nbytes--;
         }
diff --git a/mm/frontswap.c b/mm/frontswap.c
index 538367ef1372..1b24bdcb3197 100644
--- a/mm/frontswap.c
+++ b/mm/frontswap.c
@@ -319,7 +319,7 @@ void __frontswap_invalidate_area(unsigned type)
                         return;
                 frontswap_ops->invalidate_area(type);
                 atomic_set(&sis->frontswap_pages, 0);
-                memset(sis->frontswap_map, 0, sis->max / sizeof(long));
+                bitmap_zero(sis->frontswap_map, sis->max);
         }
         clear_bit(type, need_init);
 }
diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index f8feeeca6686..e2bfbf73a551 100644
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -2839,7 +2839,7 @@ int hugetlb_fault(struct mm_struct *mm, struct vm_area_struct *vma,
         if (ptep) {
                 entry = huge_ptep_get(ptep);
                 if (unlikely(is_hugetlb_entry_migration(entry))) {
-                        migration_entry_wait(mm, (pmd_t *)ptep, address);
+                        migration_entry_wait_huge(mm, ptep);
                         return 0;
                 } else if (unlikely(is_hugetlb_entry_hwpoisoned(entry)))
                         return VM_FAULT_HWPOISON_LARGE |
diff --git a/mm/memcontrol.c b/mm/memcontrol.c
index 010d6c14129a..194721839cf5 100644
--- a/mm/memcontrol.c
+++ b/mm/memcontrol.c
@@ -1199,7 +1199,6 @@ struct mem_cgroup *mem_cgroup_iter(struct mem_cgroup *root,
 
                         mz = mem_cgroup_zoneinfo(root, nid, zid);
                         iter = &mz->reclaim_iter[reclaim->priority];
-                        last_visited = iter->last_visited;
                         if (prev && reclaim->generation != iter->generation) {
                                 iter->last_visited = NULL;
                                 goto out_unlock;
@@ -1218,13 +1217,12 @@ struct mem_cgroup *mem_cgroup_iter(struct mem_cgroup *root,
                          * is alive.
                          */
                         dead_count = atomic_read(&root->dead_count);
-                        smp_rmb();
-                        last_visited = iter->last_visited;
-                        if (last_visited) {
-                                if ((dead_count != iter->last_dead_count) ||
-                                        !css_tryget(&last_visited->css)) {
+                        if (dead_count == iter->last_dead_count) {
+                                smp_rmb();
+                                last_visited = iter->last_visited;
+                                if (last_visited &&
+                                    !css_tryget(&last_visited->css))
                                         last_visited = NULL;
-                                }
                         }
                 }
 
@@ -3141,8 +3139,6 @@ int memcg_update_cache_size(struct kmem_cache *s, int num_groups)
                         return -ENOMEM;
                 }
 
-                INIT_WORK(&s->memcg_params->destroy,
-                                kmem_cache_destroy_work_func);
                 s->memcg_params->is_root_cache = true;
 
                 /*
diff --git a/mm/memory.c b/mm/memory.c
index 6dc1882fbd72..61a262b08e53 100644
--- a/mm/memory.c
+++ b/mm/memory.c
@@ -220,7 +220,6 @@ void tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, bool fullmm)
         tlb->start      = -1UL;
         tlb->end        = 0;
         tlb->need_flush = 0;
-        tlb->fast_mode  = (num_possible_cpus() == 1);
         tlb->local.next = NULL;
         tlb->local.nr   = 0;
         tlb->local.max  = ARRAY_SIZE(tlb->__pages);
@@ -244,9 +243,6 @@ void tlb_flush_mmu(struct mmu_gather *tlb)
         tlb_table_flush(tlb);
 #endif
 
-        if (tlb_fast_mode(tlb))
-                return;
-
         for (batch = &tlb->local; batch; batch = batch->next) {
                 free_pages_and_swap_cache(batch->pages, batch->nr);
                 batch->nr = 0;
@@ -288,11 +284,6 @@ int __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
 
         VM_BUG_ON(!tlb->need_flush);
 
-        if (tlb_fast_mode(tlb)) {
-                free_page_and_swap_cache(page);
-                return 1; /* avoid calling tlb_flush_mmu() */
-        }
-
         batch = tlb->active;
         batch->pages[batch->nr++] = page;
         if (batch->nr == batch->max) {
diff --git a/mm/migrate.c b/mm/migrate.c
index b1f57501de9c..6f0c24438bba 100644
--- a/mm/migrate.c
+++ b/mm/migrate.c
@@ -200,15 +200,14 @@ static void remove_migration_ptes(struct page *old, struct page *new)
  * get to the page and wait until migration is finished.
  * When we return from this function the fault will be retried.
  */
-void migration_entry_wait(struct mm_struct *mm, pmd_t *pmd,
-                                unsigned long address)
+static void __migration_entry_wait(struct mm_struct *mm, pte_t *ptep,
+                                spinlock_t *ptl)
 {
-        pte_t *ptep, pte;
-        spinlock_t *ptl;
+        pte_t pte;
         swp_entry_t entry;
         struct page *page;
 
-        ptep = pte_offset_map_lock(mm, pmd, address, &ptl);
+        spin_lock(ptl);
         pte = *ptep;
         if (!is_swap_pte(pte))
                 goto out;
@@ -236,6 +235,20 @@ out:
         pte_unmap_unlock(ptep, ptl);
 }
 
+void migration_entry_wait(struct mm_struct *mm, pmd_t *pmd,
+                                unsigned long address)
+{
+        spinlock_t *ptl = pte_lockptr(mm, pmd);
+        pte_t *ptep = pte_offset_map(pmd, address);
+        __migration_entry_wait(mm, ptep, ptl);
+}
+
+void migration_entry_wait_huge(struct mm_struct *mm, pte_t *pte)
+{
+        spinlock_t *ptl = &(mm)->page_table_lock;
+        __migration_entry_wait(mm, pte, ptl);
+}
+
 #ifdef CONFIG_BLOCK
 /* Returns true if all buffers are successfully locked */
 static bool buffer_migrate_lock_buffers(struct buffer_head *head,
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 378a15bcd649..c3edb624fccf 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -1628,6 +1628,7 @@ static bool __zone_watermark_ok(struct zone *z, int order, unsigned long mark,
         long min = mark;
         long lowmem_reserve = z->lowmem_reserve[classzone_idx];
         int o;
+        long free_cma = 0;
 
         free_pages -= (1 << order) - 1;
         if (alloc_flags & ALLOC_HIGH)
@@ -1637,9 +1638,10 @@ static bool __zone_watermark_ok(struct zone *z, int order, unsigned long mark,
 #ifdef CONFIG_CMA
         /* If allocation can't use CMA areas don't use free CMA pages */
         if (!(alloc_flags & ALLOC_CMA))
-                free_pages -= zone_page_state(z, NR_FREE_CMA_PAGES);
+                free_cma = zone_page_state(z, NR_FREE_CMA_PAGES);
 #endif
-        if (free_pages <= min + lowmem_reserve)
+
+        if (free_pages - free_cma <= min + lowmem_reserve)
                 return false;
         for (o = 0; o < order; o++) {
                 /* At the next order, this order's pages become unavailable */
diff --git a/mm/swap_state.c b/mm/swap_state.c
index b3d40dcf3624..f24ab0dff554 100644
--- a/mm/swap_state.c
+++ b/mm/swap_state.c
@@ -336,8 +336,24 @@ struct page *read_swap_cache_async(swp_entry_t entry, gfp_t gfp_mask,
                  * Swap entry may have been freed since our caller observed it.
                  */
                 err = swapcache_prepare(entry);
-                if (err == -EEXIST) {   /* seems racy */
+                if (err == -EEXIST) {
                         radix_tree_preload_end();
+                        /*
+                         * We might race against get_swap_page() and stumble
+                         * across a SWAP_HAS_CACHE swap_map entry whose page
+                         * has not been brought into the swapcache yet, while
+                         * the other end is scheduled away waiting on discard
+                         * I/O completion at scan_swap_map().
+                         *
+                         * In order to avoid turning this transitory state
+                         * into a permanent loop around this -EEXIST case
+                         * if !CONFIG_PREEMPT and the I/O completion happens
+                         * to be waiting on the CPU waitqueue where we are now
+                         * busy looping, we just conditionally invoke the
+                         * scheduler here, if there are some more important
+                         * tasks to run.
+                         */
+                        cond_resched();
                         continue;
                 }
                 if (err) {              /* swp entry is obsolete ? */
diff --git a/mm/swapfile.c b/mm/swapfile.c
index 6c340d908b27..746af55b8455 100644
--- a/mm/swapfile.c
+++ b/mm/swapfile.c
@@ -2116,7 +2116,7 @@ SYSCALL_DEFINE2(swapon, const char __user *, specialfile, int, swap_flags)
         }
         /* frontswap enabled? set up bit-per-page map for frontswap */
         if (frontswap_enabled)
-                frontswap_map = vzalloc(maxpages / sizeof(long));
+                frontswap_map = vzalloc(BITS_TO_LONGS(maxpages) * sizeof(long));
 
         if (p->bdev) {
                 if (blk_queue_nonrot(bdev_get_queue(p->bdev))) {
diff --git a/net/9p/client.c b/net/9p/client.c
index 8eb75425e6e6..addc116cecf0 100644
--- a/net/9p/client.c
+++ b/net/9p/client.c
@@ -562,36 +562,19 @@ static int p9_check_zc_errors(struct p9_client *c, struct p9_req_t *req,
 
         if (!p9_is_proto_dotl(c)) {
                 /* Error is reported in string format */
-                uint16_t len;
-                /* 7 = header size for RERROR, 2 is the size of string len; */
-                int inline_len = in_hdrlen - (7 + 2);
+                int len;
+                /* 7 = header size for RERROR; */
+                int inline_len = in_hdrlen - 7;
 
-                /* Read the size of error string */
-                err = p9pdu_readf(req->rc, c->proto_version, "w", &len);
-                if (err)
-                        goto out_err;
-
-                ename = kmalloc(len + 1, GFP_NOFS);
-                if (!ename) {
-                        err = -ENOMEM;
+                len =  req->rc->size - req->rc->offset;
+                if (len > (P9_ZC_HDR_SZ - 7)) {
+                        err = -EFAULT;
                         goto out_err;
                 }
-                if (len <= inline_len) {
-                        /* We have error in protocol buffer itself */
-                        if (pdu_read(req->rc, ename, len)) {
-                                err = -EFAULT;
-                                goto out_free;
 
-                        }
-                } else {
-                        /*
-                         *  Part of the data is in user space buffer.
-                         */
-                        if (pdu_read(req->rc, ename, inline_len)) {
-                                err = -EFAULT;
-                                goto out_free;
-
-                        }
+                ename = &req->rc->sdata[req->rc->offset];
+                if (len > inline_len) {
+                        /* We have error in external buffer */
                         if (kern_buf) {
                                 memcpy(ename + inline_len, uidata,
                                        len - inline_len);
@@ -600,19 +583,19 @@ static int p9_check_zc_errors(struct p9_client *c, struct p9_req_t *req,
                                                      uidata, len - inline_len);
                                 if (err) {
                                         err = -EFAULT;
-                                        goto out_free;
+                                        goto out_err;
                                 }
                         }
                 }
-                ename[len] = 0;
-                if (p9_is_proto_dotu(c)) {
-                        /* For dotu we also have error code */
-                        err = p9pdu_readf(req->rc,
-                                          c->proto_version, "d", &ecode);
-                        if (err)
-                                goto out_free;
+                ename = NULL;
+                err = p9pdu_readf(req->rc, c->proto_version, "s?d",
+                                  &ename, &ecode);
+                if (err)
+                        goto out_err;
+
+                if (p9_is_proto_dotu(c))
                         err = -ecode;
-                }
+
                 if (!err || !IS_ERR_VALUE(err)) {
                         err = p9_errstr2errno(ename, strlen(ename));
 
@@ -628,8 +611,6 @@ static int p9_check_zc_errors(struct p9_client *c, struct p9_req_t *req,
         }
         return err;
 
-out_free:
-        kfree(ename);
 out_err:
         p9_debug(P9_DEBUG_ERROR, "couldn't parse error%d\n", err);
         return err;
diff --git a/net/batman-adv/bat_iv_ogm.c b/net/batman-adv/bat_iv_ogm.c
index 071f288b77a8..f680ee101878 100644
--- a/net/batman-adv/bat_iv_ogm.c
+++ b/net/batman-adv/bat_iv_ogm.c
@@ -29,6 +29,21 @@
 #include "bat_algo.h"
 #include "network-coding.h"
 
+/**
+ * batadv_dup_status - duplicate status
+ * @BATADV_NO_DUP: the packet is a duplicate
+ * @BATADV_ORIG_DUP: OGM is a duplicate in the originator (but not for the
+ *  neighbor)
+ * @BATADV_NEIGH_DUP: OGM is a duplicate for the neighbor
+ * @BATADV_PROTECTED: originator is currently protected (after reboot)
+ */
+enum batadv_dup_status {
+        BATADV_NO_DUP = 0,
+        BATADV_ORIG_DUP,
+        BATADV_NEIGH_DUP,
+        BATADV_PROTECTED,
+};
+
 static struct batadv_neigh_node *
 batadv_iv_ogm_neigh_new(struct batadv_hard_iface *hard_iface,
                         const uint8_t *neigh_addr,
@@ -650,7 +665,7 @@ batadv_iv_ogm_orig_update(struct batadv_priv *bat_priv,
                           const struct batadv_ogm_packet *batadv_ogm_packet,
                           struct batadv_hard_iface *if_incoming,
                           const unsigned char *tt_buff,
-                          int is_duplicate)
+                          enum batadv_dup_status dup_status)
 {
         struct batadv_neigh_node *neigh_node = NULL, *tmp_neigh_node = NULL;
         struct batadv_neigh_node *router = NULL;
@@ -676,7 +691,7 @@ batadv_iv_ogm_orig_update(struct batadv_priv *bat_priv,
                         continue;
                 }
 
-                if (is_duplicate)
+                if (dup_status != BATADV_NO_DUP)
                         continue;
 
                 spin_lock_bh(&tmp_neigh_node->lq_update_lock);
@@ -718,7 +733,7 @@ batadv_iv_ogm_orig_update(struct batadv_priv *bat_priv,
         neigh_node->tq_avg = batadv_ring_buffer_avg(neigh_node->tq_recv);
         spin_unlock_bh(&neigh_node->lq_update_lock);
 
-        if (!is_duplicate) {
+        if (dup_status == BATADV_NO_DUP) {
                 orig_node->last_ttl = batadv_ogm_packet->header.ttl;
                 neigh_node->last_ttl = batadv_ogm_packet->header.ttl;
         }
@@ -902,15 +917,16 @@ out:
         return ret;
 }
 
-/* processes a batman packet for all interfaces, adjusts the sequence number and
- * finds out whether it is a duplicate.
- * returns:
- *   1 the packet is a duplicate
- *   0 the packet has not yet been received
- *  -1 the packet is old and has been received while the seqno window
- *     was protected. Caller should drop it.
+/**
+ * batadv_iv_ogm_update_seqnos -  process a batman packet for all interfaces,
+ *  adjust the sequence number and find out whether it is a duplicate
+ * @ethhdr: ethernet header of the packet
+ * @batadv_ogm_packet: OGM packet to be considered
+ * @if_incoming: interface on which the OGM packet was received
+ *
+ * Returns duplicate status as enum batadv_dup_status
  */
-static int
+static enum batadv_dup_status
 batadv_iv_ogm_update_seqnos(const struct ethhdr *ethhdr,
                             const struct batadv_ogm_packet *batadv_ogm_packet,
                             const struct batadv_hard_iface *if_incoming)
@@ -918,17 +934,18 @@ batadv_iv_ogm_update_seqnos(const struct ethhdr *ethhdr,
         struct batadv_priv *bat_priv = netdev_priv(if_incoming->soft_iface);
         struct batadv_orig_node *orig_node;
         struct batadv_neigh_node *tmp_neigh_node;
-        int is_duplicate = 0;
+        int is_dup;
         int32_t seq_diff;
         int need_update = 0;
-        int set_mark, ret = -1;
+        int set_mark;
+        enum batadv_dup_status ret = BATADV_NO_DUP;
         uint32_t seqno = ntohl(batadv_ogm_packet->seqno);
         uint8_t *neigh_addr;
         uint8_t packet_count;
 
         orig_node = batadv_get_orig_node(bat_priv, batadv_ogm_packet->orig);
         if (!orig_node)
-                return 0;
+                return BATADV_NO_DUP;
 
         spin_lock_bh(&orig_node->ogm_cnt_lock);
         seq_diff = seqno - orig_node->last_real_seqno;
@@ -936,22 +953,29 @@ batadv_iv_ogm_update_seqnos(const struct ethhdr *ethhdr,
         /* signalize caller that the packet is to be dropped. */
         if (!hlist_empty(&orig_node->neigh_list) &&
             batadv_window_protected(bat_priv, seq_diff,
-                                    &orig_node->batman_seqno_reset))
+                                    &orig_node->batman_seqno_reset)) {
+                ret = BATADV_PROTECTED;
                 goto out;
+        }
 
         rcu_read_lock();
         hlist_for_each_entry_rcu(tmp_neigh_node,
                                  &orig_node->neigh_list, list) {
-                is_duplicate |= batadv_test_bit(tmp_neigh_node->real_bits,
-                                                orig_node->last_real_seqno,
-                                                seqno);
-
                 neigh_addr = tmp_neigh_node->addr;
+                is_dup = batadv_test_bit(tmp_neigh_node->real_bits,
+                                         orig_node->last_real_seqno,
+                                         seqno);
+
                 if (batadv_compare_eth(neigh_addr, ethhdr->h_source) &&
-                    tmp_neigh_node->if_incoming == if_incoming)
+                    tmp_neigh_node->if_incoming == if_incoming) {
                         set_mark = 1;
-                else
+                        if (is_dup)
+                                ret = BATADV_NEIGH_DUP;
+                } else {
                         set_mark = 0;
+                        if (is_dup && (ret != BATADV_NEIGH_DUP))
+                                ret = BATADV_ORIG_DUP;
+                }
 
                 /* if the window moved, set the update flag. */
                 need_update |= batadv_bit_get_packet(bat_priv,
@@ -971,8 +995,6 @@ batadv_iv_ogm_update_seqnos(const struct ethhdr *ethhdr,
                 orig_node->last_real_seqno = seqno;
         }
 
-        ret = is_duplicate;
-
 out:
         spin_unlock_bh(&orig_node->ogm_cnt_lock);
         batadv_orig_node_free_ref(orig_node);
@@ -994,7 +1016,8 @@ static void batadv_iv_ogm_process(const struct ethhdr *ethhdr,
         int is_broadcast = 0, is_bidirect;
         bool is_single_hop_neigh = false;
         bool is_from_best_next_hop = false;
-        int is_duplicate, sameseq, simlar_ttl;
+        int sameseq, similar_ttl;
+        enum batadv_dup_status dup_status;
         uint32_t if_incoming_seqno;
         uint8_t *prev_sender;
 
@@ -1138,10 +1161,10 @@ static void batadv_iv_ogm_process(const struct ethhdr *ethhdr,
         if (!orig_node)
                 return;
 
-        is_duplicate = batadv_iv_ogm_update_seqnos(ethhdr, batadv_ogm_packet,
-                                                   if_incoming);
+        dup_status = batadv_iv_ogm_update_seqnos(ethhdr, batadv_ogm_packet,
+                                                 if_incoming);
 
-        if (is_duplicate == -1) {
+        if (dup_status == BATADV_PROTECTED) {
                 batadv_dbg(BATADV_DBG_BATMAN, bat_priv,
                            "Drop packet: packet within seqno protection time (sender: %pM)\n",
                            ethhdr->h_source);
@@ -1211,11 +1234,12 @@ static void batadv_iv_ogm_process(const struct ethhdr *ethhdr,
          * seqno and similar ttl as the non-duplicate
          */
         sameseq = orig_node->last_real_seqno == ntohl(batadv_ogm_packet->seqno);
-        simlar_ttl = orig_node->last_ttl - 3 <= batadv_ogm_packet->header.ttl;
-        if (is_bidirect && (!is_duplicate || (sameseq && simlar_ttl)))
+        similar_ttl = orig_node->last_ttl - 3 <= batadv_ogm_packet->header.ttl;
+        if (is_bidirect && ((dup_status == BATADV_NO_DUP) ||
+                            (sameseq && similar_ttl)))
                 batadv_iv_ogm_orig_update(bat_priv, orig_node, ethhdr,
                                           batadv_ogm_packet, if_incoming,
-                                          tt_buff, is_duplicate);
+                                          tt_buff, dup_status);
 
         /* is single hop (direct) neighbor */
         if (is_single_hop_neigh) {
@@ -1236,7 +1260,7 @@ static void batadv_iv_ogm_process(const struct ethhdr *ethhdr,
                 goto out_neigh;
         }
 
-        if (is_duplicate) {
+        if (dup_status == BATADV_NEIGH_DUP) {
                 batadv_dbg(BATADV_DBG_BATMAN, bat_priv,
                            "Drop packet: duplicate packet received\n");
                 goto out_neigh;
diff --git a/net/batman-adv/bridge_loop_avoidance.c b/net/batman-adv/bridge_loop_avoidance.c
index 379061c72549..de27b3175cfd 100644
--- a/net/batman-adv/bridge_loop_avoidance.c
+++ b/net/batman-adv/bridge_loop_avoidance.c
@@ -1067,6 +1067,10 @@ void batadv_bla_update_orig_address(struct batadv_priv *bat_priv,
         group = htons(crc16(0, primary_if->net_dev->dev_addr, ETH_ALEN));
         bat_priv->bla.claim_dest.group = group;
 
+        /* purge everything when bridge loop avoidance is turned off */
+        if (!atomic_read(&bat_priv->bridge_loop_avoidance))
+                oldif = NULL;
+
         if (!oldif) {
                 batadv_bla_purge_claims(bat_priv, NULL, 1);
                 batadv_bla_purge_backbone_gw(bat_priv, 1);
diff --git a/net/batman-adv/sysfs.c b/net/batman-adv/sysfs.c
index 15a22efa9a67..929e304dacb2 100644
--- a/net/batman-adv/sysfs.c
+++ b/net/batman-adv/sysfs.c
@@ -582,10 +582,7 @@ static ssize_t batadv_store_mesh_iface(struct kobject *kobj,
             (strncmp(hard_iface->soft_iface->name, buff, IFNAMSIZ) == 0))
                 goto out;
 
-        if (!rtnl_trylock()) {
-                ret = -ERESTARTSYS;
-                goto out;
-        }
+        rtnl_lock();
 
         if (status_tmp == BATADV_IF_NOT_IN_USE) {
                 batadv_hardif_disable_interface(hard_iface,
diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c
index 33843c5c4939..d817c932d634 100644
--- a/net/bluetooth/hci_core.c
+++ b/net/bluetooth/hci_core.c
@@ -1555,11 +1555,15 @@ static const struct rfkill_ops hci_rfkill_ops = {
 static void hci_power_on(struct work_struct *work)
 {
         struct hci_dev *hdev = container_of(work, struct hci_dev, power_on);
+        int err;
 
         BT_DBG("%s", hdev->name);
 
-        if (hci_dev_open(hdev->id) < 0)
+        err = hci_dev_open(hdev->id);
+        if (err < 0) {
+                mgmt_set_powered_failed(hdev, err);
                 return;
+        }
 
         if (test_bit(HCI_AUTO_OFF, &hdev->dev_flags))
                 queue_delayed_work(hdev->req_workqueue, &hdev->power_off,
diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c
index a76d1ac0321b..24bee07ee4ce 100644
--- a/net/bluetooth/l2cap_core.c
+++ b/net/bluetooth/l2cap_core.c
@@ -3677,10 +3677,14 @@ static void l2cap_conf_rfc_get(struct l2cap_chan *chan, void *rsp, int len)
 }
 
 static inline int l2cap_command_rej(struct l2cap_conn *conn,
-                                    struct l2cap_cmd_hdr *cmd, u8 *data)
+                                    struct l2cap_cmd_hdr *cmd, u16 cmd_len,
+                                    u8 *data)
 {
         struct l2cap_cmd_rej_unk *rej = (struct l2cap_cmd_rej_unk *) data;
 
+        if (cmd_len < sizeof(*rej))
+                return -EPROTO;
+
         if (rej->reason != L2CAP_REJ_NOT_UNDERSTOOD)
                 return 0;
 
@@ -3829,11 +3833,14 @@ sendresp:
 }
 
 static int l2cap_connect_req(struct l2cap_conn *conn,
-                             struct l2cap_cmd_hdr *cmd, u8 *data)
+                             struct l2cap_cmd_hdr *cmd, u16 cmd_len, u8 *data)
 {
         struct hci_dev *hdev = conn->hcon->hdev;
         struct hci_conn *hcon = conn->hcon;
 
+        if (cmd_len < sizeof(struct l2cap_conn_req))
+                return -EPROTO;
+
         hci_dev_lock(hdev);
         if (test_bit(HCI_MGMT, &hdev->dev_flags) &&
             !test_and_set_bit(HCI_CONN_MGMT_CONNECTED, &hcon->flags))
@@ -3847,7 +3854,8 @@ static int l2cap_connect_req(struct l2cap_conn *conn,
 }
 
 static int l2cap_connect_create_rsp(struct l2cap_conn *conn,
-                                    struct l2cap_cmd_hdr *cmd, u8 *data)
+                                    struct l2cap_cmd_hdr *cmd, u16 cmd_len,
+                                    u8 *data)
 {
         struct l2cap_conn_rsp *rsp = (struct l2cap_conn_rsp *) data;
         u16 scid, dcid, result, status;
@@ -3855,6 +3863,9 @@ static int l2cap_connect_create_rsp(struct l2cap_conn *conn,
         u8 req[128];
         int err;
 
+        if (cmd_len < sizeof(*rsp))
+                return -EPROTO;
+
         scid   = __le16_to_cpu(rsp->scid);
         dcid   = __le16_to_cpu(rsp->dcid);
         result = __le16_to_cpu(rsp->result);
@@ -3952,6 +3963,9 @@ static inline int l2cap_config_req(struct l2cap_conn *conn,
         struct l2cap_chan *chan;
         int len, err = 0;
 
+        if (cmd_len < sizeof(*req))
+                return -EPROTO;
+
         dcid  = __le16_to_cpu(req->dcid);
         flags = __le16_to_cpu(req->flags);
 
@@ -3975,7 +3989,7 @@ static inline int l2cap_config_req(struct l2cap_conn *conn,
 
         /* Reject if config buffer is too small. */
         len = cmd_len - sizeof(*req);
-        if (len < 0 || chan->conf_len + len > sizeof(chan->conf_req)) {
+        if (chan->conf_len + len > sizeof(chan->conf_req)) {
                 l2cap_send_cmd(conn, cmd->ident, L2CAP_CONF_RSP,
                                l2cap_build_conf_rsp(chan, rsp,
                                L2CAP_CONF_REJECT, flags), rsp);
@@ -4053,14 +4067,18 @@ unlock:
 }
 
 static inline int l2cap_config_rsp(struct l2cap_conn *conn,
-                                   struct l2cap_cmd_hdr *cmd, u8 *data)
+                                   struct l2cap_cmd_hdr *cmd, u16 cmd_len,
+                                   u8 *data)
 {
         struct l2cap_conf_rsp *rsp = (struct l2cap_conf_rsp *)data;
         u16 scid, flags, result;
         struct l2cap_chan *chan;
-        int len = le16_to_cpu(cmd->len) - sizeof(*rsp);
+        int len = cmd_len - sizeof(*rsp);
         int err = 0;
 
+        if (cmd_len < sizeof(*rsp))
+                return -EPROTO;
+
         scid   = __le16_to_cpu(rsp->scid);
         flags  = __le16_to_cpu(rsp->flags);
         result = __le16_to_cpu(rsp->result);
@@ -4161,7 +4179,8 @@ done:
 }
 
 static inline int l2cap_disconnect_req(struct l2cap_conn *conn,
-                                       struct l2cap_cmd_hdr *cmd, u8 *data)
+                                       struct l2cap_cmd_hdr *cmd, u16 cmd_len,
+                                       u8 *data)
 {
         struct l2cap_disconn_req *req = (struct l2cap_disconn_req *) data;
         struct l2cap_disconn_rsp rsp;
@@ -4169,6 +4188,9 @@ static inline int l2cap_disconnect_req(struct l2cap_conn *conn,
         struct l2cap_chan *chan;
         struct sock *sk;
 
+        if (cmd_len != sizeof(*req))
+                return -EPROTO;
+
         scid = __le16_to_cpu(req->scid);
         dcid = __le16_to_cpu(req->dcid);
 
@@ -4208,12 +4230,16 @@ static inline int l2cap_disconnect_req(struct l2cap_conn *conn,
 }
 
 static inline int l2cap_disconnect_rsp(struct l2cap_conn *conn,
-                                       struct l2cap_cmd_hdr *cmd, u8 *data)
+                                       struct l2cap_cmd_hdr *cmd, u16 cmd_len,
+                                       u8 *data)
 {
         struct l2cap_disconn_rsp *rsp = (struct l2cap_disconn_rsp *) data;
         u16 dcid, scid;
         struct l2cap_chan *chan;
 
+        if (cmd_len != sizeof(*rsp))
+                return -EPROTO;
+
         scid = __le16_to_cpu(rsp->scid);
         dcid = __le16_to_cpu(rsp->dcid);
 
@@ -4243,11 +4269,15 @@ static inline int l2cap_disconnect_rsp(struct l2cap_conn *conn,
 }
 
 static inline int l2cap_information_req(struct l2cap_conn *conn,
-                                        struct l2cap_cmd_hdr *cmd, u8 *data)
+                                        struct l2cap_cmd_hdr *cmd, u16 cmd_len,
+                                        u8 *data)
 {
         struct l2cap_info_req *req = (struct l2cap_info_req *) data;
         u16 type;
 
+        if (cmd_len != sizeof(*req))
+                return -EPROTO;
+
         type = __le16_to_cpu(req->type);
 
         BT_DBG("type 0x%4.4x", type);
@@ -4294,11 +4324,15 @@ static inline int l2cap_information_req(struct l2cap_conn *conn,
 }
 
 static inline int l2cap_information_rsp(struct l2cap_conn *conn,
-                                        struct l2cap_cmd_hdr *cmd, u8 *data)
+                                        struct l2cap_cmd_hdr *cmd, u16 cmd_len,
+                                        u8 *data)
 {
         struct l2cap_info_rsp *rsp = (struct l2cap_info_rsp *) data;
         u16 type, result;
 
+        if (cmd_len != sizeof(*rsp))
+                return -EPROTO;
+
         type   = __le16_to_cpu(rsp->type);
         result = __le16_to_cpu(rsp->result);
 
@@ -5164,16 +5198,16 @@ static inline int l2cap_bredr_sig_cmd(struct l2cap_conn *conn,
 
         switch (cmd->code) {
         case L2CAP_COMMAND_REJ:
-                l2cap_command_rej(conn, cmd, data);
+                l2cap_command_rej(conn, cmd, cmd_len, data);
                 break;
 
         case L2CAP_CONN_REQ:
-                err = l2cap_connect_req(conn, cmd, data);
+                err = l2cap_connect_req(conn, cmd, cmd_len, data);
                 break;
 
         case L2CAP_CONN_RSP:
         case L2CAP_CREATE_CHAN_RSP:
-                err = l2cap_connect_create_rsp(conn, cmd, data);
+                err = l2cap_connect_create_rsp(conn, cmd, cmd_len, data);
                 break;
 
         case L2CAP_CONF_REQ:
@@ -5181,15 +5215,15 @@ static inline int l2cap_bredr_sig_cmd(struct l2cap_conn *conn,
                 break;
 
         case L2CAP_CONF_RSP:
-                err = l2cap_config_rsp(conn, cmd, data);
+                err = l2cap_config_rsp(conn, cmd, cmd_len, data);
                 break;
 
         case L2CAP_DISCONN_REQ:
-                err = l2cap_disconnect_req(conn, cmd, data);
+                err = l2cap_disconnect_req(conn, cmd, cmd_len, data);
                 break;
 
         case L2CAP_DISCONN_RSP:
-                err = l2cap_disconnect_rsp(conn, cmd, data);
+                err = l2cap_disconnect_rsp(conn, cmd, cmd_len, data);
                 break;
 
         case L2CAP_ECHO_REQ:
@@ -5200,11 +5234,11 @@ static inline int l2cap_bredr_sig_cmd(struct l2cap_conn *conn,
                 break;
 
         case L2CAP_INFO_REQ:
-                err = l2cap_information_req(conn, cmd, data);
+                err = l2cap_information_req(conn, cmd, cmd_len, data);
                 break;
 
         case L2CAP_INFO_RSP:
-                err = l2cap_information_rsp(conn, cmd, data);
+                err = l2cap_information_rsp(conn, cmd, cmd_len, data);
                 break;
 
         case L2CAP_CREATE_CHAN_REQ:
diff --git a/net/bluetooth/mgmt.c b/net/bluetooth/mgmt.c
index 35fef22703e9..f8ecbc70293d 100644
--- a/net/bluetooth/mgmt.c
+++ b/net/bluetooth/mgmt.c
@@ -2700,7 +2700,7 @@ static int start_discovery(struct sock *sk, struct hci_dev *hdev,
                 break;
 
         case DISCOV_TYPE_LE:
-                if (!lmp_host_le_capable(hdev)) {
+                if (!test_bit(HCI_LE_ENABLED, &hdev->dev_flags)) {
                         err = cmd_status(sk, hdev->id, MGMT_OP_START_DISCOVERY,
                                          MGMT_STATUS_NOT_SUPPORTED);
                         mgmt_pending_remove(cmd);
@@ -3418,6 +3418,27 @@ new_settings:
         return err;
 }
 
+int mgmt_set_powered_failed(struct hci_dev *hdev, int err)
+{
+        struct pending_cmd *cmd;
+        u8 status;
+
+        cmd = mgmt_pending_find(MGMT_OP_SET_POWERED, hdev);
+        if (!cmd)
+                return -ENOENT;
+
+        if (err == -ERFKILL)
+                status = MGMT_STATUS_RFKILLED;
+        else
+                status = MGMT_STATUS_FAILED;
+
+        err = cmd_status(cmd->sk, hdev->id, MGMT_OP_SET_POWERED, status);
+
+        mgmt_pending_remove(cmd);
+
+        return err;
+}
+
 int mgmt_discoverable(struct hci_dev *hdev, u8 discoverable)
 {
         struct cmd_lookup match = { NULL, hdev };
diff --git a/net/bluetooth/smp.c b/net/bluetooth/smp.c
index b2296d3857a0..b5562abdd6e0 100644
--- a/net/bluetooth/smp.c
+++ b/net/bluetooth/smp.c
@@ -770,7 +770,7 @@ int smp_conn_security(struct hci_conn *hcon, __u8 sec_level)
 
         BT_DBG("conn %p hcon %p level 0x%2.2x", conn, hcon, sec_level);
 
-        if (!lmp_host_le_capable(hcon->hdev))
+        if (!test_bit(HCI_LE_ENABLED, &hcon->hdev->dev_flags))
                 return 1;
 
         if (sec_level == BT_SECURITY_LOW)
@@ -851,7 +851,7 @@ int smp_sig_channel(struct l2cap_conn *conn, struct sk_buff *skb)
         __u8 reason;
         int err = 0;
 
-        if (!lmp_host_le_capable(conn->hcon->hdev)) {
+        if (!test_bit(HCI_LE_ENABLED, &conn->hcon->hdev->dev_flags)) {
                 err = -ENOTSUPP;
                 reason = SMP_PAIRING_NOTSUPP;
                 goto done;
diff --git a/net/ceph/osd_client.c b/net/ceph/osd_client.c
index d5953b87918c..3a246a6cab47 100644
--- a/net/ceph/osd_client.c
+++ b/net/ceph/osd_client.c
@@ -1675,13 +1675,13 @@ static void kick_requests(struct ceph_osd_client *osdc, int force_resend)
                 __register_request(osdc, req);
                 __unregister_linger_request(osdc, req);
         }
+        reset_changed_osds(osdc);
         mutex_unlock(&osdc->request_mutex);
 
         if (needmap) {
                 dout("%d requests for down osds, need new map\n", needmap);
                 ceph_monc_request_next_osdmap(&osdc->client->monc);
         }
-        reset_changed_osds(osdc);
 }
 
 
diff --git a/net/compat.c b/net/compat.c
index 79ae88485001..f0a1ba6c8086 100644
--- a/net/compat.c
+++ b/net/compat.c
@@ -734,19 +734,25 @@ static unsigned char nas[21] = {
 
 asmlinkage long compat_sys_sendmsg(int fd, struct compat_msghdr __user *msg, unsigned int flags)
 {
-        return sys_sendmsg(fd, (struct msghdr __user *)msg, flags | MSG_CMSG_COMPAT);
+        if (flags & MSG_CMSG_COMPAT)
+                return -EINVAL;
+        return __sys_sendmsg(fd, (struct msghdr __user *)msg, flags | MSG_CMSG_COMPAT);
 }
 
 asmlinkage long compat_sys_sendmmsg(int fd, struct compat_mmsghdr __user *mmsg,
                                     unsigned int vlen, unsigned int flags)
 {
+        if (flags & MSG_CMSG_COMPAT)
+                return -EINVAL;
         return __sys_sendmmsg(fd, (struct mmsghdr __user *)mmsg, vlen,
                               flags | MSG_CMSG_COMPAT);
 }
 
 asmlinkage long compat_sys_recvmsg(int fd, struct compat_msghdr __user *msg, unsigned int flags)
 {
-        return sys_recvmsg(fd, (struct msghdr __user *)msg, flags | MSG_CMSG_COMPAT);
+        if (flags & MSG_CMSG_COMPAT)
+                return -EINVAL;
+        return __sys_recvmsg(fd, (struct msghdr __user *)msg, flags | MSG_CMSG_COMPAT);
 }
 
 asmlinkage long compat_sys_recv(int fd, void __user *buf, size_t len, unsigned int flags)
@@ -768,6 +774,9 @@ asmlinkage long compat_sys_recvmmsg(int fd, struct compat_mmsghdr __user *mmsg,
         int datagrams;
         struct timespec ktspec;
 
+        if (flags & MSG_CMSG_COMPAT)
+                return -EINVAL;
+
         if (COMPAT_USE_64BIT_TIME)
                 return __sys_recvmmsg(fd, (struct mmsghdr __user *)mmsg, vlen,
                                       flags | MSG_CMSG_COMPAT,
diff --git a/net/core/dev_addr_lists.c b/net/core/dev_addr_lists.c
index c013f38482a1..6cda4e2c2132 100644
--- a/net/core/dev_addr_lists.c
+++ b/net/core/dev_addr_lists.c
@@ -39,6 +39,7 @@ static int __hw_addr_create_ex(struct netdev_hw_addr_list *list,
         ha->refcount = 1;
         ha->global_use = global;
         ha->synced = sync;
+        ha->sync_cnt = 0;
         list_add_tail_rcu(&ha->list, &list->list);
         list->count++;
 
@@ -66,7 +67,7 @@ static int __hw_addr_add_ex(struct netdev_hw_addr_list *list,
                         }
                         if (sync) {
                                 if (ha->synced)
-                                        return 0;
+                                        return -EEXIST;
                                 else
                                         ha->synced = true;
                         }
@@ -139,10 +140,13 @@ static int __hw_addr_sync_one(struct netdev_hw_addr_list *to_list,
 
         err = __hw_addr_add_ex(to_list, ha->addr, addr_len, ha->type,
                                false, true);
-        if (err)
+        if (err && err != -EEXIST)
                 return err;
-        ha->sync_cnt++;
-        ha->refcount++;
+
+        if (!err) {
+                ha->sync_cnt++;
+                ha->refcount++;
+        }
 
         return 0;
 }
@@ -159,7 +163,8 @@ static void __hw_addr_unsync_one(struct netdev_hw_addr_list *to_list,
         if (err)
                 return;
         ha->sync_cnt--;
-        __hw_addr_del_entry(from_list, ha, false, true);
+        /* address on from list is not marked synced */
+        __hw_addr_del_entry(from_list, ha, false, false);
 }
 
 static int __hw_addr_sync_multiple(struct netdev_hw_addr_list *to_list,
@@ -796,7 +801,7 @@ int dev_mc_sync_multiple(struct net_device *to, struct net_device *from)
                 return -EINVAL;
 
         netif_addr_lock_nested(to);
-        err = __hw_addr_sync(&to->mc, &from->mc, to->addr_len);
+        err = __hw_addr_sync_multiple(&to->mc, &from->mc, to->addr_len);
         if (!err)
                 __dev_set_rx_mode(to);
         netif_addr_unlock(to);
diff --git a/net/core/filter.c b/net/core/filter.c
index dad2a178f9f8..6438f29ff266 100644
--- a/net/core/filter.c
+++ b/net/core/filter.c
@@ -778,7 +778,7 @@ int sk_detach_filter(struct sock *sk)
 }
 EXPORT_SYMBOL_GPL(sk_detach_filter);
 
-static void sk_decode_filter(struct sock_filter *filt, struct sock_filter *to)
+void sk_decode_filter(struct sock_filter *filt, struct sock_filter *to)
 {
         static const u16 decodes[] = {
                 [BPF_S_ALU_ADD_K]       = BPF_ALU|BPF_ADD|BPF_K,
diff --git a/net/core/skbuff.c b/net/core/skbuff.c
index af9185d0be6a..cfd777bd6bd0 100644
--- a/net/core/skbuff.c
+++ b/net/core/skbuff.c
@@ -195,7 +195,7 @@ struct sk_buff *__alloc_skb_head(gfp_t gfp_mask, int node)
          * the tail pointer in struct sk_buff!
          */
         memset(skb, 0, offsetof(struct sk_buff, tail));
-        skb->data = NULL;
+        skb->head = NULL;
         skb->truesize = sizeof(struct sk_buff);
         atomic_set(&skb->users, 1);
 
@@ -611,7 +611,7 @@ static void skb_release_head_state(struct sk_buff *skb)
 static void skb_release_all(struct sk_buff *skb)
 {
         skb_release_head_state(skb);
-        if (likely(skb->data))
+        if (likely(skb->head))
                 skb_release_data(skb);
 }
 
diff --git a/net/core/sock.c b/net/core/sock.c
index 6ba327da79e1..88868a9d21da 100644
--- a/net/core/sock.c
+++ b/net/core/sock.c
@@ -210,7 +210,7 @@ static const char *const af_family_key_strings[AF_MAX+1] = {
   "sk_lock-AF_TIPC"  , "sk_lock-AF_BLUETOOTH", "sk_lock-IUCV"        ,
   "sk_lock-AF_RXRPC" , "sk_lock-AF_ISDN"     , "sk_lock-AF_PHONET"   ,
   "sk_lock-AF_IEEE802154", "sk_lock-AF_CAIF" , "sk_lock-AF_ALG"      ,
-  "sk_lock-AF_NFC"   , "sk_lock-AF_MAX"
+  "sk_lock-AF_NFC"   , "sk_lock-AF_VSOCK"    , "sk_lock-AF_MAX"
 };
 static const char *const af_family_slock_key_strings[AF_MAX+1] = {
   "slock-AF_UNSPEC", "slock-AF_UNIX"     , "slock-AF_INET"     ,
@@ -226,7 +226,7 @@ static const char *const af_family_slock_key_strings[AF_MAX+1] = {
   "slock-AF_TIPC"  , "slock-AF_BLUETOOTH", "slock-AF_IUCV"     ,
   "slock-AF_RXRPC" , "slock-AF_ISDN"     , "slock-AF_PHONET"   ,
   "slock-AF_IEEE802154", "slock-AF_CAIF" , "slock-AF_ALG"      ,
-  "slock-AF_NFC"   , "slock-AF_MAX"
+  "slock-AF_NFC"   , "slock-AF_VSOCK"    ,"slock-AF_MAX"
 };
 static const char *const af_family_clock_key_strings[AF_MAX+1] = {
   "clock-AF_UNSPEC", "clock-AF_UNIX"     , "clock-AF_INET"     ,
@@ -242,7 +242,7 @@ static const char *const af_family_clock_key_strings[AF_MAX+1] = {
   "clock-AF_TIPC"  , "clock-AF_BLUETOOTH", "clock-AF_IUCV"     ,
   "clock-AF_RXRPC" , "clock-AF_ISDN"     , "clock-AF_PHONET"   ,
   "clock-AF_IEEE802154", "clock-AF_CAIF" , "clock-AF_ALG"      ,
-  "clock-AF_NFC"   , "clock-AF_MAX"
+  "clock-AF_NFC"   , "clock-AF_VSOCK"    , "clock-AF_MAX"
 };
 
 /*
diff --git a/net/core/sock_diag.c b/net/core/sock_diag.c
index d5bef0b0f639..a0e9cf6379de 100644
--- a/net/core/sock_diag.c
+++ b/net/core/sock_diag.c
@@ -73,8 +73,13 @@ int sock_diag_put_filterinfo(struct user_namespace *user_ns, struct sock *sk,
                 goto out;
         }
 
-        if (filter)
-                memcpy(nla_data(attr), filter->insns, len);
+        if (filter) {
+                struct sock_filter *fb = (struct sock_filter *)nla_data(attr);
+                int i;
+
+                for (i = 0; i < filter->len; i++, fb++)
+                        sk_decode_filter(&filter->insns[i], fb);
+        }
 
 out:
         rcu_read_unlock();
diff --git a/net/ipv4/ip_tunnel.c b/net/ipv4/ip_tunnel.c
index e4147ec1665a..7fa8f08fa7ae 100644
--- a/net/ipv4/ip_tunnel.c
+++ b/net/ipv4/ip_tunnel.c
@@ -503,6 +503,7 @@ void ip_tunnel_xmit(struct sk_buff *skb, struct net_device *dev,
 
         inner_iph = (const struct iphdr *)skb_inner_network_header(skb);
 
+        memset(IPCB(skb), 0, sizeof(*IPCB(skb)));
         dst = tnl_params->daddr;
         if (dst == 0) {
                 /* NBMA tunnel */
@@ -658,7 +659,6 @@ void ip_tunnel_xmit(struct sk_buff *skb, struct net_device *dev,
 
         skb_dst_drop(skb);
         skb_dst_set(skb, &rt->dst);
-        memset(IPCB(skb), 0, sizeof(*IPCB(skb)));
 
         /* Push down and install the IP header. */
         skb_push(skb, sizeof(struct iphdr));
@@ -853,7 +853,7 @@ void ip_tunnel_dellink(struct net_device *dev, struct list_head *head)
 }
 EXPORT_SYMBOL_GPL(ip_tunnel_dellink);
 
-int __net_init ip_tunnel_init_net(struct net *net, int ip_tnl_net_id,
+int ip_tunnel_init_net(struct net *net, int ip_tnl_net_id,
                                   struct rtnl_link_ops *ops, char *devname)
 {
         struct ip_tunnel_net *itn = net_generic(net, ip_tnl_net_id);
@@ -899,7 +899,7 @@ static void ip_tunnel_destroy(struct ip_tunnel_net *itn, struct list_head *head)
                 unregister_netdevice_queue(itn->fb_tunnel_dev, head);
 }
 
-void __net_exit ip_tunnel_delete_net(struct ip_tunnel_net *itn)
+void ip_tunnel_delete_net(struct ip_tunnel_net *itn)
 {
         LIST_HEAD(list);
 
diff --git a/net/ipv4/ip_vti.c b/net/ipv4/ip_vti.c
index 9d2bdb2c1d3f..c118f6b576bb 100644
--- a/net/ipv4/ip_vti.c
+++ b/net/ipv4/ip_vti.c
@@ -361,8 +361,7 @@ static netdev_tx_t vti_tunnel_xmit(struct sk_buff *skb, struct net_device *dev)
                         tunnel->err_count = 0;
         }
 
-        IPCB(skb)->flags &= ~(IPSKB_XFRM_TUNNEL_SIZE | IPSKB_XFRM_TRANSFORMED |
-                              IPSKB_REROUTED);
+        memset(IPCB(skb), 0, sizeof(*IPCB(skb)));
         skb_dst_drop(skb);
         skb_dst_set(skb, &rt->dst);
         nf_reset(skb);
diff --git a/net/ipv4/netfilter/ipt_ULOG.c b/net/ipv4/netfilter/ipt_ULOG.c
index cf08218ddbcf..ff4b781b1056 100644
--- a/net/ipv4/netfilter/ipt_ULOG.c
+++ b/net/ipv4/netfilter/ipt_ULOG.c
@@ -231,8 +231,10 @@ static void ipt_ulog_packet(struct net *net,
         put_unaligned(tv.tv_usec, &pm->timestamp_usec);
         put_unaligned(skb->mark, &pm->mark);
         pm->hook = hooknum;
-        if (prefix != NULL)
-                strncpy(pm->prefix, prefix, sizeof(pm->prefix));
+        if (prefix != NULL) {
+                strncpy(pm->prefix, prefix, sizeof(pm->prefix) - 1);
+                pm->prefix[sizeof(pm->prefix) - 1] = '\0';
+        }
         else if (loginfo->prefix[0] != '\0')
                 strncpy(pm->prefix, loginfo->prefix, sizeof(pm->prefix));
         else
diff --git a/net/ipv4/route.c b/net/ipv4/route.c
index 550781a17b34..d35bbf0cf404 100644
--- a/net/ipv4/route.c
+++ b/net/ipv4/route.c
@@ -737,10 +737,15 @@ static void ip_do_redirect(struct dst_entry *dst, struct sock *sk, struct sk_buf
 {
         struct rtable *rt;
         struct flowi4 fl4;
+        const struct iphdr *iph = (const struct iphdr *) skb->data;
+        int oif = skb->dev->ifindex;
+        u8 tos = RT_TOS(iph->tos);
+        u8 prot = iph->protocol;
+        u32 mark = skb->mark;
 
         rt = (struct rtable *) dst;
 
-        ip_rt_build_flow_key(&fl4, sk, skb);
+        __build_flow_key(&fl4, sk, iph, oif, tos, prot, mark, 0);
         __ip_do_redirect(rt, skb, &fl4, true);
 }
 
diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c
index d1ab6ab29a55..1bbf744c2cc3 100644
--- a/net/ipv6/addrconf.c
+++ b/net/ipv6/addrconf.c
@@ -1487,7 +1487,7 @@ static int ipv6_count_addresses(struct inet6_dev *idev)
 }
 
 int ipv6_chk_addr(struct net *net, const struct in6_addr *addr,
-                  struct net_device *dev, int strict)
+                  const struct net_device *dev, int strict)
 {
         struct inet6_ifaddr *ifp;
         unsigned int hash = inet6_addr_hash(addr);
@@ -2658,8 +2658,10 @@ static void init_loopback(struct net_device *dev)
                         sp_rt = addrconf_dst_alloc(idev, &sp_ifa->addr, 0);
 
                         /* Failure cases are ignored */
-                        if (!IS_ERR(sp_rt))
+                        if (!IS_ERR(sp_rt)) {
+                                sp_ifa->rt = sp_rt;
                                 ip6_ins_rt(sp_rt);
+                        }
                 }
                 read_unlock_bh(&idev->lock);
         }
diff --git a/net/ipv6/netfilter.c b/net/ipv6/netfilter.c
index 72836f40b730..95f3f1da0d7f 100644
--- a/net/ipv6/netfilter.c
+++ b/net/ipv6/netfilter.c
@@ -10,6 +10,7 @@
 #include <linux/netfilter.h>
 #include <linux/netfilter_ipv6.h>
 #include <linux/export.h>
+#include <net/addrconf.h>
 #include <net/dst.h>
 #include <net/ipv6.h>
 #include <net/ip6_route.h>
@@ -186,6 +187,10 @@ static __sum16 nf_ip6_checksum_partial(struct sk_buff *skb, unsigned int hook,
         return csum;
 };
 
+static const struct nf_ipv6_ops ipv6ops = {
+        .chk_addr       = ipv6_chk_addr,
+};
+
 static const struct nf_afinfo nf_ip6_afinfo = {
         .family                 = AF_INET6,
         .checksum               = nf_ip6_checksum,
@@ -198,6 +203,7 @@ static const struct nf_afinfo nf_ip6_afinfo = {
 
 int __init ipv6_netfilter_init(void)
 {
+        RCU_INIT_POINTER(nf_ipv6_ops, &ipv6ops);
         return nf_register_afinfo(&nf_ip6_afinfo);
 }
 
@@ -206,5 +212,6 @@ int __init ipv6_netfilter_init(void)
  */
 void ipv6_netfilter_fini(void)
 {
+        RCU_INIT_POINTER(nf_ipv6_ops, NULL);
         nf_unregister_afinfo(&nf_ip6_afinfo);
 }
diff --git a/net/ipv6/proc.c b/net/ipv6/proc.c
index f3c1ff4357ff..51c3285b5d9b 100644
--- a/net/ipv6/proc.c
+++ b/net/ipv6/proc.c
@@ -90,7 +90,7 @@ static const struct snmp_mib snmp6_ipstats_list[] = {
         SNMP_MIB_ITEM("Ip6OutMcastOctets", IPSTATS_MIB_OUTMCASTOCTETS),
         SNMP_MIB_ITEM("Ip6InBcastOctets", IPSTATS_MIB_INBCASTOCTETS),
         SNMP_MIB_ITEM("Ip6OutBcastOctets", IPSTATS_MIB_OUTBCASTOCTETS),
-        SNMP_MIB_ITEM("InCsumErrors", IPSTATS_MIB_CSUMERRORS),
+        /* IPSTATS_MIB_CSUMERRORS is not relevant in IPv6 (no checksum) */
         SNMP_MIB_SENTINEL
 };
 
diff --git a/net/ipv6/udp_offload.c b/net/ipv6/udp_offload.c
index 3bb3a891a424..d3cfaf9c7a08 100644
--- a/net/ipv6/udp_offload.c
+++ b/net/ipv6/udp_offload.c
@@ -46,11 +46,12 @@ static struct sk_buff *udp6_ufo_fragment(struct sk_buff *skb,
         unsigned int mss;
         unsigned int unfrag_ip6hlen, unfrag_len;
         struct frag_hdr *fptr;
-        u8 *mac_start, *prevhdr;
+        u8 *packet_start, *prevhdr;
         u8 nexthdr;
         u8 frag_hdr_sz = sizeof(struct frag_hdr);
         int offset;
         __wsum csum;
+        int tnl_hlen;
 
         mss = skb_shinfo(skb)->gso_size;
         if (unlikely(skb->len <= mss))
@@ -83,9 +84,11 @@ static struct sk_buff *udp6_ufo_fragment(struct sk_buff *skb,
         skb->ip_summed = CHECKSUM_NONE;
 
         /* Check if there is enough headroom to insert fragment header. */
-        if ((skb_mac_header(skb) < skb->head + frag_hdr_sz) &&
-            pskb_expand_head(skb, frag_hdr_sz, 0, GFP_ATOMIC))
-                goto out;
+        tnl_hlen = skb_tnl_header_len(skb);
+        if (skb_headroom(skb) < (tnl_hlen + frag_hdr_sz)) {
+                if (gso_pskb_expand_head(skb, tnl_hlen + frag_hdr_sz))
+                        goto out;
+        }
 
         /* Find the unfragmentable header and shift it left by frag_hdr_sz
          * bytes to insert fragment header.
@@ -93,11 +96,12 @@ static struct sk_buff *udp6_ufo_fragment(struct sk_buff *skb,
         unfrag_ip6hlen = ip6_find_1stfragopt(skb, &prevhdr);
         nexthdr = *prevhdr;
         *prevhdr = NEXTHDR_FRAGMENT;
-        unfrag_len = skb_network_header(skb) - skb_mac_header(skb) +
-                     unfrag_ip6hlen;
-        mac_start = skb_mac_header(skb);
-        memmove(mac_start-frag_hdr_sz, mac_start, unfrag_len);
+        unfrag_len = (skb_network_header(skb) - skb_mac_header(skb)) +
+                     unfrag_ip6hlen + tnl_hlen;
+        packet_start = (u8 *) skb->head + SKB_GSO_CB(skb)->mac_offset;
+        memmove(packet_start-frag_hdr_sz, packet_start, unfrag_len);
 
+        SKB_GSO_CB(skb)->mac_offset -= frag_hdr_sz;
         skb->mac_header -= frag_hdr_sz;
         skb->network_header -= frag_hdr_sz;
 
diff --git a/net/key/af_key.c b/net/key/af_key.c
index 5b1e5af25713..c5fbd7589681 100644
--- a/net/key/af_key.c
+++ b/net/key/af_key.c
@@ -2366,6 +2366,8 @@ static int pfkey_spddelete(struct sock *sk, struct sk_buff *skb, const struct sa
 
 out:
         xfrm_pol_put(xp);
+        if (err == 0)
+                xfrm_garbage_collect(net);
         return err;
 }
 
@@ -2615,6 +2617,8 @@ static int pfkey_spdget(struct sock *sk, struct sk_buff *skb, const struct sadb_
 
 out:
         xfrm_pol_put(xp);
+        if (delete && err == 0)
+                xfrm_garbage_collect(net);
         return err;
 }
 
diff --git a/net/l2tp/l2tp_ppp.c b/net/l2tp/l2tp_ppp.c
index 637a341c1e2d..8dec6876dc50 100644
--- a/net/l2tp/l2tp_ppp.c
+++ b/net/l2tp/l2tp_ppp.c
@@ -346,19 +346,19 @@ static int pppol2tp_sendmsg(struct kiocb *iocb, struct socket *sock, struct msgh
         skb_put(skb, 2);
 
         /* Copy user data into skb */
-        error = memcpy_fromiovec(skb->data, m->msg_iov, total_len);
+        error = memcpy_fromiovec(skb_put(skb, total_len), m->msg_iov,
+                                 total_len);
         if (error < 0) {
                 kfree_skb(skb);
                 goto error_put_sess_tun;
         }
-        skb_put(skb, total_len);
 
         l2tp_xmit_skb(session, skb, session->hdr_len);
 
         sock_put(ps->tunnel_sock);
         sock_put(sk);
 
-        return error;
+        return total_len;
 
 error_put_sess_tun:
         sock_put(ps->tunnel_sock);
diff --git a/net/mac80211/iface.c b/net/mac80211/iface.c
index 60f1ce5e5e52..98d20c0f6fed 100644
--- a/net/mac80211/iface.c
+++ b/net/mac80211/iface.c
@@ -159,9 +159,10 @@ static int ieee80211_change_mtu(struct net_device *dev, int new_mtu)
         return 0;
 }
 
-static int ieee80211_verify_mac(struct ieee80211_local *local, u8 *addr)
+static int ieee80211_verify_mac(struct ieee80211_sub_if_data *sdata, u8 *addr)
 {
-        struct ieee80211_sub_if_data *sdata;
+        struct ieee80211_local *local = sdata->local;
+        struct ieee80211_sub_if_data *iter;
         u64 new, mask, tmp;
         u8 *m;
         int ret = 0;
@@ -181,11 +182,14 @@ static int ieee80211_verify_mac(struct ieee80211_local *local, u8 *addr)
 
 
         mutex_lock(&local->iflist_mtx);
-        list_for_each_entry(sdata, &local->interfaces, list) {
-                if (sdata->vif.type == NL80211_IFTYPE_MONITOR)
+        list_for_each_entry(iter, &local->interfaces, list) {
+                if (iter == sdata)
+                        continue;
+
+                if (iter->vif.type == NL80211_IFTYPE_MONITOR)
                         continue;
 
-                m = sdata->vif.addr;
+                m = iter->vif.addr;
                 tmp =   ((u64)m[0] << 5*8) | ((u64)m[1] << 4*8) |
                         ((u64)m[2] << 3*8) | ((u64)m[3] << 2*8) |
                         ((u64)m[4] << 1*8) | ((u64)m[5] << 0*8);
@@ -209,7 +213,7 @@ static int ieee80211_change_mac(struct net_device *dev, void *addr)
         if (ieee80211_sdata_running(sdata))
                 return -EBUSY;
 
-        ret = ieee80211_verify_mac(sdata->local, sa->sa_data);
+        ret = ieee80211_verify_mac(sdata, sa->sa_data);
         if (ret)
                 return ret;
 
@@ -474,6 +478,9 @@ int ieee80211_do_open(struct wireless_dev *wdev, bool coming_up)
                         master->control_port_protocol;
                 sdata->control_port_no_encrypt =
                         master->control_port_no_encrypt;
+                sdata->vif.cab_queue = master->vif.cab_queue;
+                memcpy(sdata->vif.hw_queue, master->vif.hw_queue,
+                       sizeof(sdata->vif.hw_queue));
                 break;
                 }
         case NL80211_IFTYPE_AP:
@@ -653,7 +660,11 @@ int ieee80211_do_open(struct wireless_dev *wdev, bool coming_up)
 
         ieee80211_recalc_ps(local, -1);
 
-        if (dev) {
+        if (sdata->vif.type == NL80211_IFTYPE_MONITOR ||
+            sdata->vif.type == NL80211_IFTYPE_AP_VLAN) {
+                /* XXX: for AP_VLAN, actually track AP queues */
+                netif_tx_start_all_queues(dev);
+        } else if (dev) {
                 unsigned long flags;
                 int n_acs = IEEE80211_NUM_ACS;
                 int ac;
@@ -1479,7 +1490,17 @@ static void ieee80211_assign_perm_addr(struct ieee80211_local *local,
                         break;
                 }
 
+                /*
+                 * Pick address of existing interface in case user changed
+                 * MAC address manually, default to perm_addr.
+                 */
                 m = local->hw.wiphy->perm_addr;
+                list_for_each_entry(sdata, &local->interfaces, list) {
+                        if (sdata->vif.type == NL80211_IFTYPE_MONITOR)
+                                continue;
+                        m = sdata->vif.addr;
+                        break;
+                }
                 start = ((u64)m[0] << 5*8) | ((u64)m[1] << 4*8) |
                         ((u64)m[2] << 3*8) | ((u64)m[3] << 2*8) |
                         ((u64)m[4] << 1*8) | ((u64)m[5] << 0*8);
@@ -1696,6 +1717,15 @@ void ieee80211_remove_interfaces(struct ieee80211_local *local)
 
         ASSERT_RTNL();
 
+        /*
+         * Close all AP_VLAN interfaces first, as otherwise they
+         * might be closed while the AP interface they belong to
+         * is closed, causing unregister_netdevice_many() to crash.
+         */
+        list_for_each_entry(sdata, &local->interfaces, list)
+                if (sdata->vif.type == NL80211_IFTYPE_AP_VLAN)
+                        dev_close(sdata->dev);
+
         mutex_lock(&local->iflist_mtx);
         list_for_each_entry_safe(sdata, tmp, &local->interfaces, list) {
                 list_del(&sdata->list);
diff --git a/net/mac80211/mlme.c b/net/mac80211/mlme.c
index a46e490f20dd..a8c2130c8ba4 100644
--- a/net/mac80211/mlme.c
+++ b/net/mac80211/mlme.c
@@ -3321,10 +3321,6 @@ static int ieee80211_probe_auth(struct ieee80211_sub_if_data *sdata)
         if (WARN_ON_ONCE(!auth_data))
                 return -EINVAL;
 
-        if (local->hw.flags & IEEE80211_HW_REPORTS_TX_ACK_STATUS)
-                tx_flags = IEEE80211_TX_CTL_REQ_TX_STATUS |
-                           IEEE80211_TX_INTFL_MLME_CONN_TX;
-
         auth_data->tries++;
 
         if (auth_data->tries > IEEE80211_AUTH_MAX_TRIES) {
@@ -3358,6 +3354,10 @@ static int ieee80211_probe_auth(struct ieee80211_sub_if_data *sdata)
                         auth_data->expected_transaction = trans;
                 }
 
+                if (local->hw.flags & IEEE80211_HW_REPORTS_TX_ACK_STATUS)
+                        tx_flags = IEEE80211_TX_CTL_REQ_TX_STATUS |
+                                   IEEE80211_TX_INTFL_MLME_CONN_TX;
+
                 ieee80211_send_auth(sdata, trans, auth_data->algorithm, status,
                                     auth_data->data, auth_data->data_len,
                                     auth_data->bss->bssid,
@@ -3381,12 +3381,12 @@ static int ieee80211_probe_auth(struct ieee80211_sub_if_data *sdata)
                  * will not answer to direct packet in unassociated state.
                  */
                 ieee80211_send_probe_req(sdata, NULL, ssidie + 2, ssidie[1],
-                                         NULL, 0, (u32) -1, true, tx_flags,
+                                         NULL, 0, (u32) -1, true, 0,
                                          auth_data->bss->channel, false);
                 rcu_read_unlock();
         }
 
-        if (!(local->hw.flags & IEEE80211_HW_REPORTS_TX_ACK_STATUS)) {
+        if (tx_flags == 0) {
                 auth_data->timeout = jiffies + IEEE80211_AUTH_TIMEOUT;
                 ifmgd->auth_data->timeout_started = true;
                 run_again(ifmgd, auth_data->timeout);
diff --git a/net/netfilter/core.c b/net/netfilter/core.c
index 07c865a31a3d..857ca9f35177 100644
--- a/net/netfilter/core.c
+++ b/net/netfilter/core.c
@@ -30,6 +30,8 @@ static DEFINE_MUTEX(afinfo_mutex);
 
 const struct nf_afinfo __rcu *nf_afinfo[NFPROTO_NUMPROTO] __read_mostly;
 EXPORT_SYMBOL(nf_afinfo);
+const struct nf_ipv6_ops __rcu *nf_ipv6_ops __read_mostly;
+EXPORT_SYMBOL_GPL(nf_ipv6_ops);
 
 int nf_register_afinfo(const struct nf_afinfo *afinfo)
 {
diff --git a/net/netfilter/ipvs/ip_vs_core.c b/net/netfilter/ipvs/ip_vs_core.c
index 085b5880ab0d..05565d2b3a61 100644
--- a/net/netfilter/ipvs/ip_vs_core.c
+++ b/net/netfilter/ipvs/ip_vs_core.c
@@ -1001,6 +1001,32 @@ static inline int is_tcp_reset(const struct sk_buff *skb, int nh_len)
         return th->rst;
 }
 
+static inline bool is_new_conn(const struct sk_buff *skb,
+                               struct ip_vs_iphdr *iph)
+{
+        switch (iph->protocol) {
+        case IPPROTO_TCP: {
+                struct tcphdr _tcph, *th;
+
+                th = skb_header_pointer(skb, iph->len, sizeof(_tcph), &_tcph);
+                if (th == NULL)
+                        return false;
+                return th->syn;
+        }
+        case IPPROTO_SCTP: {
+                sctp_chunkhdr_t *sch, schunk;
+
+                sch = skb_header_pointer(skb, iph->len + sizeof(sctp_sctphdr_t),
+                                         sizeof(schunk), &schunk);
+                if (sch == NULL)
+                        return false;
+                return sch->type == SCTP_CID_INIT;
+        }
+        default:
+                return false;
+        }
+}
+
 /* Handle response packets: rewrite addresses and send away...
  */
 static unsigned int
@@ -1612,6 +1638,15 @@ ip_vs_in(unsigned int hooknum, struct sk_buff *skb, int af)
          * Check if the packet belongs to an existing connection entry
          */
         cp = pp->conn_in_get(af, skb, &iph, 0);
+
+        if (unlikely(sysctl_expire_nodest_conn(ipvs)) && cp && cp->dest &&
+            unlikely(!atomic_read(&cp->dest->weight)) && !iph.fragoffs &&
+            is_new_conn(skb, &iph)) {
+                ip_vs_conn_expire_now(cp);
+                __ip_vs_conn_put(cp);
+                cp = NULL;
+        }
+
         if (unlikely(!cp) && !iph.fragoffs) {
                 /* No (second) fragments need to enter here, as nf_defrag_ipv6
                  * replayed fragment zero will already have created the cp
diff --git a/net/netfilter/ipvs/ip_vs_ctl.c b/net/netfilter/ipvs/ip_vs_ctl.c
index 5b142fb16480..9e6c2a075a4c 100644
--- a/net/netfilter/ipvs/ip_vs_ctl.c
+++ b/net/netfilter/ipvs/ip_vs_ctl.c
@@ -2542,6 +2542,7 @@ __ip_vs_get_dest_entries(struct net *net, const struct ip_vs_get_dests *get,
                 struct ip_vs_dest *dest;
                 struct ip_vs_dest_entry entry;
 
+                memset(&entry, 0, sizeof(entry));
                 list_for_each_entry(dest, &svc->destinations, n_list) {
                         if (count >= get->num_dests)
                                 break;
diff --git a/net/netfilter/ipvs/ip_vs_sh.c b/net/netfilter/ipvs/ip_vs_sh.c
index 0df269d7c99f..a65edfe4b16c 100644
--- a/net/netfilter/ipvs/ip_vs_sh.c
+++ b/net/netfilter/ipvs/ip_vs_sh.c
@@ -67,8 +67,8 @@ struct ip_vs_sh_bucket {
 #define IP_VS_SH_TAB_MASK               (IP_VS_SH_TAB_SIZE - 1)
 
 struct ip_vs_sh_state {
-        struct ip_vs_sh_bucket          buckets[IP_VS_SH_TAB_SIZE];
         struct rcu_head                 rcu_head;
+        struct ip_vs_sh_bucket          buckets[IP_VS_SH_TAB_SIZE];
 };
 
 /*
diff --git a/net/netfilter/nfnetlink_acct.c b/net/netfilter/nfnetlink_acct.c
index dc3fd5d44464..c7b6d466a662 100644
--- a/net/netfilter/nfnetlink_acct.c
+++ b/net/netfilter/nfnetlink_acct.c
@@ -149,9 +149,12 @@ nfnl_acct_dump(struct sk_buff *skb, struct netlink_callback *cb)
 
         rcu_read_lock();
         list_for_each_entry_rcu(cur, &nfnl_acct_list, head) {
-                if (last && cur != last)
-                        continue;
+                if (last) {
+                        if (cur != last)
+                                continue;
 
+                        last = NULL;
+                }
                 if (nfnl_acct_fill_info(skb, NETLINK_CB(cb->skb).portid,
                                        cb->nlh->nlmsg_seq,
                                        NFNL_MSG_TYPE(cb->nlh->nlmsg_type),
diff --git a/net/netfilter/nfnetlink_cttimeout.c b/net/netfilter/nfnetlink_cttimeout.c
index 701c88a20fea..65074dfb9383 100644
--- a/net/netfilter/nfnetlink_cttimeout.c
+++ b/net/netfilter/nfnetlink_cttimeout.c
@@ -220,9 +220,12 @@ ctnl_timeout_dump(struct sk_buff *skb, struct netlink_callback *cb)
 
         rcu_read_lock();
         list_for_each_entry_rcu(cur, &cttimeout_list, head) {
-                if (last && cur != last)
-                        continue;
+                if (last) {
+                        if (cur != last)
+                                continue;
 
+                        last = NULL;
+                }
                 if (ctnl_timeout_fill_info(skb, NETLINK_CB(cb->skb).portid,
                                            cb->nlh->nlmsg_seq,
                                            NFNL_MSG_TYPE(cb->nlh->nlmsg_type),
diff --git a/net/netfilter/nfnetlink_queue_core.c b/net/netfilter/nfnetlink_queue_core.c
index 4e27fa035814..5352b2d2d5bf 100644
--- a/net/netfilter/nfnetlink_queue_core.c
+++ b/net/netfilter/nfnetlink_queue_core.c
@@ -637,9 +637,6 @@ nfqnl_enqueue_packet(struct nf_queue_entry *entry, unsigned int queuenum)
         if (queue->copy_mode == NFQNL_COPY_NONE)
                 return -EINVAL;
 
-        if ((queue->flags & NFQA_CFG_F_GSO) || !skb_is_gso(entry->skb))
-                return __nfqnl_enqueue_packet(net, queue, entry);
-
         skb = entry->skb;
 
         switch (entry->pf) {
@@ -651,6 +648,9 @@ nfqnl_enqueue_packet(struct nf_queue_entry *entry, unsigned int queuenum)
                 break;
         }
 
+        if ((queue->flags & NFQA_CFG_F_GSO) || !skb_is_gso(skb))
+                return __nfqnl_enqueue_packet(net, queue, entry);
+
         nf_bridge_adjust_skb_data(skb);
         segs = skb_gso_segment(skb, 0);
         /* Does not use PTR_ERR to limit the number of error codes that can be
diff --git a/net/netfilter/xt_LOG.c b/net/netfilter/xt_LOG.c
index 491c7d821a0b..5ab24843370a 100644
--- a/net/netfilter/xt_LOG.c
+++ b/net/netfilter/xt_LOG.c
@@ -737,7 +737,7 @@ static void dump_ipv6_packet(struct sbuff *m,
                 dump_sk_uid_gid(m, skb->sk);
 
         /* Max length: 16 "MARK=0xFFFFFFFF " */
-        if (!recurse && skb->mark)
+        if (recurse && skb->mark)
                 sb_add(m, "MARK=0x%x ", skb->mark);
 }
 
diff --git a/net/netfilter/xt_TCPMSS.c b/net/netfilter/xt_TCPMSS.c
index a75240f0d42b..afaebc766933 100644
--- a/net/netfilter/xt_TCPMSS.c
+++ b/net/netfilter/xt_TCPMSS.c
@@ -125,6 +125,12 @@ tcpmss_mangle_packet(struct sk_buff *skb,
 
         skb_put(skb, TCPOLEN_MSS);
 
+        /* RFC 879 states that the default MSS is 536 without specific
+         * knowledge that the destination host is prepared to accept larger.
+         * Since no MSS was provided, we MUST NOT set a value > 536.
+         */
+        newmss = min(newmss, (u16)536);
+
         opt = (u_int8_t *)tcph + sizeof(struct tcphdr);
         memmove(opt + TCPOLEN_MSS, opt, tcplen - sizeof(struct tcphdr));
 
diff --git a/net/netfilter/xt_addrtype.c b/net/netfilter/xt_addrtype.c
index 49c5ff7f6dd6..68ff29f60867 100644
--- a/net/netfilter/xt_addrtype.c
+++ b/net/netfilter/xt_addrtype.c
@@ -22,6 +22,7 @@
 #include <net/ip6_fib.h>
 #endif
 
+#include <linux/netfilter_ipv6.h>
 #include <linux/netfilter/xt_addrtype.h>
 #include <linux/netfilter/x_tables.h>
 
@@ -33,12 +34,12 @@ MODULE_ALIAS("ip6t_addrtype");
 
 #if IS_ENABLED(CONFIG_IP6_NF_IPTABLES)
 static u32 match_lookup_rt6(struct net *net, const struct net_device *dev,
-                            const struct in6_addr *addr)
+                            const struct in6_addr *addr, u16 mask)
 {
         const struct nf_afinfo *afinfo;
         struct flowi6 flow;
         struct rt6_info *rt;
-        u32 ret;
+        u32 ret = 0;
         int route_err;
 
         memset(&flow, 0, sizeof(flow));
@@ -49,12 +50,19 @@ static u32 match_lookup_rt6(struct net *net, const struct net_device *dev,
         rcu_read_lock();
 
         afinfo = nf_get_afinfo(NFPROTO_IPV6);
-        if (afinfo != NULL)
+        if (afinfo != NULL) {
+                const struct nf_ipv6_ops *v6ops;
+
+                if (dev && (mask & XT_ADDRTYPE_LOCAL)) {
+                        v6ops = nf_get_ipv6_ops();
+                        if (v6ops && v6ops->chk_addr(net, addr, dev, true))
+                                ret = XT_ADDRTYPE_LOCAL;
+                }
                 route_err = afinfo->route(net, (struct dst_entry **)&rt,
-                                        flowi6_to_flowi(&flow), !!dev);
-        else
+                                          flowi6_to_flowi(&flow), false);
+        } else {
                 route_err = 1;
-
+        }
         rcu_read_unlock();
 
         if (route_err)
@@ -62,15 +70,12 @@ static u32 match_lookup_rt6(struct net *net, const struct net_device *dev,
 
         if (rt->rt6i_flags & RTF_REJECT)
                 ret = XT_ADDRTYPE_UNREACHABLE;
-        else
-                ret = 0;
 
-        if (rt->rt6i_flags & RTF_LOCAL)
+        if (dev == NULL && rt->rt6i_flags & RTF_LOCAL)
                 ret |= XT_ADDRTYPE_LOCAL;
         if (rt->rt6i_flags & RTF_ANYCAST)
                 ret |= XT_ADDRTYPE_ANYCAST;
 
-
         dst_release(&rt->dst);
         return ret;
 }
@@ -90,7 +95,7 @@ static bool match_type6(struct net *net, const struct net_device *dev,
 
         if ((XT_ADDRTYPE_LOCAL | XT_ADDRTYPE_ANYCAST |
              XT_ADDRTYPE_UNREACHABLE) & mask)
-                return !!(mask & match_lookup_rt6(net, dev, addr));
+                return !!(mask & match_lookup_rt6(net, dev, addr, mask));
         return true;
 }
 
diff --git a/net/netlink/af_netlink.c b/net/netlink/af_netlink.c
index 12ac6b47a35c..57ee84d21470 100644
--- a/net/netlink/af_netlink.c
+++ b/net/netlink/af_netlink.c
@@ -371,7 +371,7 @@ static int netlink_mmap(struct file *file, struct socket *sock,
         err = 0;
 out:
         mutex_unlock(&nlk->pg_vec_lock);
-        return 0;
+        return err;
 }
 
 static void netlink_frame_flush_dcache(const struct nl_mmap_hdr *hdr)
@@ -747,7 +747,7 @@ static void netlink_skb_destructor(struct sk_buff *skb)
                 atomic_dec(&ring->pending);
                 sock_put(sk);
 
-                skb->data = NULL;
+                skb->head = NULL;
         }
 #endif
         if (skb->sk != NULL)
diff --git a/net/nfc/Makefile b/net/nfc/Makefile
index fb799deaed4f..a76f4533cb6c 100644
--- a/net/nfc/Makefile
+++ b/net/nfc/Makefile
@@ -5,7 +5,6 @@
 obj-$(CONFIG_NFC) += nfc.o
 obj-$(CONFIG_NFC_NCI) += nci/
 obj-$(CONFIG_NFC_HCI) += hci/
-#obj-$(CONFIG_NFC_LLCP) += llcp/
 
 nfc-objs := core.o netlink.o af_nfc.o rawsock.o llcp_core.o llcp_commands.o \
                 llcp_sock.o
diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c
index 8ec1bca7f859..20a1bd0e6549 100644
--- a/net/packet/af_packet.c
+++ b/net/packet/af_packet.c
@@ -2851,12 +2851,11 @@ static int packet_getname_spkt(struct socket *sock, struct sockaddr *uaddr,
                 return -EOPNOTSUPP;
 
         uaddr->sa_family = AF_PACKET;
+        memset(uaddr->sa_data, 0, sizeof(uaddr->sa_data));
         rcu_read_lock();
         dev = dev_get_by_index_rcu(sock_net(sk), pkt_sk(sk)->ifindex);
         if (dev)
-                strncpy(uaddr->sa_data, dev->name, 14);
-        else
-                memset(uaddr->sa_data, 0, 14);
+                strlcpy(uaddr->sa_data, dev->name, sizeof(uaddr->sa_data));
         rcu_read_unlock();
         *uaddr_len = sizeof(*uaddr);
 
diff --git a/net/sched/act_police.c b/net/sched/act_police.c
index 823463adbd21..189e3c5b3d09 100644
--- a/net/sched/act_police.c
+++ b/net/sched/act_police.c
@@ -231,14 +231,14 @@ override:
         }
         if (R_tab) {
                 police->rate_present = true;
-                psched_ratecfg_precompute(&police->rate, R_tab->rate.rate);
+                psched_ratecfg_precompute(&police->rate, &R_tab->rate);
                 qdisc_put_rtab(R_tab);
         } else {
                 police->rate_present = false;
         }
         if (P_tab) {
                 police->peak_present = true;
-                psched_ratecfg_precompute(&police->peak, P_tab->rate.rate);
+                psched_ratecfg_precompute(&police->peak, &P_tab->rate);
                 qdisc_put_rtab(P_tab);
         } else {
                 police->peak_present = false;
@@ -376,9 +376,9 @@ tcf_act_police_dump(struct sk_buff *skb, struct tc_action *a, int bind, int ref)
         };
 
         if (police->rate_present)
-                opt.rate.rate = psched_ratecfg_getrate(&police->rate);
+                psched_ratecfg_getrate(&opt.rate, &police->rate);
         if (police->peak_present)
-                opt.peakrate.rate = psched_ratecfg_getrate(&police->peak);
+                psched_ratecfg_getrate(&opt.peakrate, &police->peak);
         if (nla_put(skb, TCA_POLICE_TBF, sizeof(opt), &opt))
                 goto nla_put_failure;
         if (police->tcfp_result &&
diff --git a/net/sched/sch_api.c b/net/sched/sch_api.c
index 2b935e7cfe7b..281c1bded1f6 100644
--- a/net/sched/sch_api.c
+++ b/net/sched/sch_api.c
@@ -291,17 +291,18 @@ struct qdisc_rate_table *qdisc_get_rtab(struct tc_ratespec *r, struct nlattr *ta
 {
         struct qdisc_rate_table *rtab;
 
+        if (tab == NULL || r->rate == 0 || r->cell_log == 0 ||
+            nla_len(tab) != TC_RTAB_SIZE)
+                return NULL;
+
         for (rtab = qdisc_rtab_list; rtab; rtab = rtab->next) {
-                if (memcmp(&rtab->rate, r, sizeof(struct tc_ratespec)) == 0) {
+                if (!memcmp(&rtab->rate, r, sizeof(struct tc_ratespec)) &&
+                    !memcmp(&rtab->data, nla_data(tab), 1024)) {
                         rtab->refcnt++;
                         return rtab;
                 }
         }
 
-        if (tab == NULL || r->rate == 0 || r->cell_log == 0 ||
-            nla_len(tab) != TC_RTAB_SIZE)
-                return NULL;
-
         rtab = kmalloc(sizeof(*rtab), GFP_KERNEL);
         if (rtab) {
                 rtab->rate = *r;
diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c
index eac7e0ee23c1..20224086cc28 100644
--- a/net/sched/sch_generic.c
+++ b/net/sched/sch_generic.c
@@ -898,14 +898,16 @@ void dev_shutdown(struct net_device *dev)
         WARN_ON(timer_pending(&dev->watchdog_timer));
 }
 
-void psched_ratecfg_precompute(struct psched_ratecfg *r, u32 rate)
+void psched_ratecfg_precompute(struct psched_ratecfg *r,
+                               const struct tc_ratespec *conf)
 {
         u64 factor;
         u64 mult;
         int shift;
 
-        r->rate_bps = (u64)rate << 3;
-        r->shift = 0;
+        memset(r, 0, sizeof(*r));
+        r->overhead = conf->overhead;
+        r->rate_bps = (u64)conf->rate << 3;
         r->mult = 1;
         /*
          * Calibrate mult, shift so that token counting is accurate
diff --git a/net/sched/sch_htb.c b/net/sched/sch_htb.c
index 79b1876b6cd2..adaedd79389c 100644
--- a/net/sched/sch_htb.c
+++ b/net/sched/sch_htb.c
@@ -109,7 +109,7 @@ struct htb_class {
         } un;
         struct rb_node node[TC_HTB_NUMPRIO];    /* node for self or feed tree */
         struct rb_node pq_node; /* node for event queue */
-        psched_time_t pq_key;
+        s64     pq_key;
 
         int prio_activity;      /* for which prios are we active */
         enum htb_cmode cmode;   /* current mode of the class */
@@ -121,10 +121,10 @@ struct htb_class {
         /* token bucket parameters */
         struct psched_ratecfg rate;
         struct psched_ratecfg ceil;
-        s64 buffer, cbuffer;    /* token bucket depth/rate */
-        psched_tdiff_t mbuffer; /* max wait time */
-        s64 tokens, ctokens;    /* current number of tokens */
-        psched_time_t t_c;      /* checkpoint time */
+        s64     buffer, cbuffer;        /* token bucket depth/rate */
+        s64     mbuffer;                /* max wait time */
+        s64     tokens, ctokens;        /* current number of tokens */
+        s64     t_c;                    /* checkpoint time */
 };
 
 struct htb_sched {
@@ -141,15 +141,15 @@ struct htb_sched {
         struct rb_root wait_pq[TC_HTB_MAXDEPTH];
 
         /* time of nearest event per level (row) */
-        psched_time_t near_ev_cache[TC_HTB_MAXDEPTH];
+        s64     near_ev_cache[TC_HTB_MAXDEPTH];
 
         int defcls;             /* class where unclassified flows go to */
 
         /* filters for qdisc itself */
         struct tcf_proto *filter_list;
 
-        int rate2quantum;       /* quant = rate / rate2quantum */
-        psched_time_t now;      /* cached dequeue time */
+        int     rate2quantum;   /* quant = rate / rate2quantum */
+        s64     now;    /* cached dequeue time */
         struct qdisc_watchdog watchdog;
 
         /* non shaped skbs; let them go directly thru */
@@ -664,8 +664,8 @@ static void htb_charge_class(struct htb_sched *q, struct htb_class *cl,
  * next pending event (0 for no event in pq, q->now for too many events).
  * Note: Applied are events whose have cl->pq_key <= q->now.
  */
-static psched_time_t htb_do_events(struct htb_sched *q, int level,
-                                   unsigned long start)
+static s64 htb_do_events(struct htb_sched *q, int level,
+                         unsigned long start)
 {
         /* don't run for longer than 2 jiffies; 2 is used instead of
          * 1 to simplify things when jiffy is going to be incremented
@@ -857,7 +857,7 @@ static struct sk_buff *htb_dequeue(struct Qdisc *sch)
         struct sk_buff *skb;
         struct htb_sched *q = qdisc_priv(sch);
         int level;
-        psched_time_t next_event;
+        s64 next_event;
         unsigned long start_at;
 
         /* try to dequeue direct packets as high prio (!) to minimize cpu work */
@@ -880,7 +880,7 @@ ok:
         for (level = 0; level < TC_HTB_MAXDEPTH; level++) {
                 /* common case optimization - skip event handler quickly */
                 int m;
-                psched_time_t event;
+                s64 event;
 
                 if (q->now >= q->near_ev_cache[level]) {
                         event = htb_do_events(q, level, start_at);
@@ -1090,9 +1090,9 @@ static int htb_dump_class(struct Qdisc *sch, unsigned long arg,
 
         memset(&opt, 0, sizeof(opt));
 
-        opt.rate.rate = psched_ratecfg_getrate(&cl->rate);
+        psched_ratecfg_getrate(&opt.rate, &cl->rate);
         opt.buffer = PSCHED_NS2TICKS(cl->buffer);
-        opt.ceil.rate = psched_ratecfg_getrate(&cl->ceil);
+        psched_ratecfg_getrate(&opt.ceil, &cl->ceil);
         opt.cbuffer = PSCHED_NS2TICKS(cl->cbuffer);
         opt.quantum = cl->quantum;
         opt.prio = cl->prio;
@@ -1117,8 +1117,8 @@ htb_dump_class_stats(struct Qdisc *sch, unsigned long arg, struct gnet_dump *d)
 
         if (!cl->level && cl->un.leaf.q)
                 cl->qstats.qlen = cl->un.leaf.q->q.qlen;
-        cl->xstats.tokens = cl->tokens;
-        cl->xstats.ctokens = cl->ctokens;
+        cl->xstats.tokens = PSCHED_NS2TICKS(cl->tokens);
+        cl->xstats.ctokens = PSCHED_NS2TICKS(cl->ctokens);
 
         if (gnet_stats_copy_basic(d, &cl->bstats) < 0 ||
             gnet_stats_copy_rate_est(d, NULL, &cl->rate_est) < 0 ||
@@ -1200,7 +1200,7 @@ static void htb_parent_to_leaf(struct htb_sched *q, struct htb_class *cl,
         parent->un.leaf.q = new_q ? new_q : &noop_qdisc;
         parent->tokens = parent->buffer;
         parent->ctokens = parent->cbuffer;
-        parent->t_c = psched_get_time();
+        parent->t_c = ktime_to_ns(ktime_get());
         parent->cmode = HTB_CAN_SEND;
 }
 
@@ -1417,8 +1417,8 @@ static int htb_change_class(struct Qdisc *sch, u32 classid,
                 /* set class to be in HTB_CAN_SEND state */
                 cl->tokens = PSCHED_TICKS2NS(hopt->buffer);
                 cl->ctokens = PSCHED_TICKS2NS(hopt->cbuffer);
-                cl->mbuffer = 60 * PSCHED_TICKS_PER_SEC;        /* 1min */
-                cl->t_c = psched_get_time();
+                cl->mbuffer = 60ULL * NSEC_PER_SEC;     /* 1min */
+                cl->t_c = ktime_to_ns(ktime_get());
                 cl->cmode = HTB_CAN_SEND;
 
                 /* attach to the hash list and parent's family */
@@ -1459,8 +1459,8 @@ static int htb_change_class(struct Qdisc *sch, u32 classid,
                         cl->prio = TC_HTB_NUMPRIO - 1;
         }
 
-        psched_ratecfg_precompute(&cl->rate, hopt->rate.rate);
-        psched_ratecfg_precompute(&cl->ceil, hopt->ceil.rate);
+        psched_ratecfg_precompute(&cl->rate, &hopt->rate);
+        psched_ratecfg_precompute(&cl->ceil, &hopt->ceil);
 
         cl->buffer = PSCHED_TICKS2NS(hopt->buffer);
         cl->cbuffer = PSCHED_TICKS2NS(hopt->buffer);
diff --git a/net/sched/sch_tbf.c b/net/sched/sch_tbf.c
index c8388f3c3426..e478d316602b 100644
--- a/net/sched/sch_tbf.c
+++ b/net/sched/sch_tbf.c
@@ -298,9 +298,9 @@ static int tbf_change(struct Qdisc *sch, struct nlattr *opt)
         q->tokens = q->buffer;
         q->ptokens = q->mtu;
 
-        psched_ratecfg_precompute(&q->rate, rtab->rate.rate);
+        psched_ratecfg_precompute(&q->rate, &rtab->rate);
         if (ptab) {
-                psched_ratecfg_precompute(&q->peak, ptab->rate.rate);
+                psched_ratecfg_precompute(&q->peak, &ptab->rate);
                 q->peak_present = true;
         } else {
                 q->peak_present = false;
@@ -350,9 +350,9 @@ static int tbf_dump(struct Qdisc *sch, struct sk_buff *skb)
                 goto nla_put_failure;
 
         opt.limit = q->limit;
-        opt.rate.rate = psched_ratecfg_getrate(&q->rate);
+        psched_ratecfg_getrate(&opt.rate, &q->rate);
         if (q->peak_present)
-                opt.peakrate.rate = psched_ratecfg_getrate(&q->peak);
+                psched_ratecfg_getrate(&opt.peakrate, &q->peak);
         else
                 memset(&opt.peakrate, 0, sizeof(opt.peakrate));
         opt.mtu = PSCHED_NS2TICKS(q->mtu);
diff --git a/net/sctp/outqueue.c b/net/sctp/outqueue.c
index 32a4625fef77..be35e2dbcc9a 100644
--- a/net/sctp/outqueue.c
+++ b/net/sctp/outqueue.c
@@ -206,6 +206,8 @@ static inline int sctp_cacc_skip(struct sctp_transport *primary,
  */
 void sctp_outq_init(struct sctp_association *asoc, struct sctp_outq *q)
 {
+        memset(q, 0, sizeof(struct sctp_outq));
+
         q->asoc = asoc;
         INIT_LIST_HEAD(&q->out_chunk_list);
         INIT_LIST_HEAD(&q->control_chunk_list);
@@ -213,11 +215,7 @@ void sctp_outq_init(struct sctp_association *asoc, struct sctp_outq *q)
         INIT_LIST_HEAD(&q->sacked);
         INIT_LIST_HEAD(&q->abandoned);
 
-        q->fast_rtx = 0;
-        q->outstanding_bytes = 0;
         q->empty = 1;
-        q->cork  = 0;
-        q->out_qlen = 0;
 }
 
 /* Free the outqueue structure and any related pending chunks.
diff --git a/net/sctp/socket.c b/net/sctp/socket.c
index f631c5ff4dbf..6abb1caf9836 100644
--- a/net/sctp/socket.c
+++ b/net/sctp/socket.c
@@ -4003,6 +4003,12 @@ SCTP_STATIC void sctp_destroy_sock(struct sock *sk)
 
         /* Release our hold on the endpoint. */
         sp = sctp_sk(sk);
+        /* This could happen during socket init, thus we bail out
+         * early, since the rest of the below is not setup either.
+         */
+        if (sp->ep == NULL)
+                return;
+
         if (sp->do_auto_asconf) {
                 sp->do_auto_asconf = 0;
                 list_del(&sp->auto_asconf_list);
diff --git a/net/socket.c b/net/socket.c
index 6b94633ca61d..4ca1526db756 100644
--- a/net/socket.c
+++ b/net/socket.c
@@ -1956,7 +1956,7 @@ struct used_address {
         unsigned int name_len;
 };
 
-static int __sys_sendmsg(struct socket *sock, struct msghdr __user *msg,
+static int ___sys_sendmsg(struct socket *sock, struct msghdr __user *msg,
                          struct msghdr *msg_sys, unsigned int flags,
                          struct used_address *used_address)
 {
@@ -2071,22 +2071,30 @@ out:
  *      BSD sendmsg interface
  */
 
-SYSCALL_DEFINE3(sendmsg, int, fd, struct msghdr __user *, msg, unsigned int, flags)
+long __sys_sendmsg(int fd, struct msghdr __user *msg, unsigned flags)
 {
         int fput_needed, err;
         struct msghdr msg_sys;
-        struct socket *sock = sockfd_lookup_light(fd, &err, &fput_needed);
+        struct socket *sock;
 
+        sock = sockfd_lookup_light(fd, &err, &fput_needed);
         if (!sock)
                 goto out;
 
-        err = __sys_sendmsg(sock, msg, &msg_sys, flags, NULL);
+        err = ___sys_sendmsg(sock, msg, &msg_sys, flags, NULL);
 
         fput_light(sock->file, fput_needed);
 out:
         return err;
 }
 
+SYSCALL_DEFINE3(sendmsg, int, fd, struct msghdr __user *, msg, unsigned int, flags)
+{
+        if (flags & MSG_CMSG_COMPAT)
+                return -EINVAL;
+        return __sys_sendmsg(fd, msg, flags);
+}
+
 /*
  *      Linux sendmmsg interface
  */
@@ -2117,15 +2125,16 @@ int __sys_sendmmsg(int fd, struct mmsghdr __user *mmsg, unsigned int vlen,
 
         while (datagrams < vlen) {
                 if (MSG_CMSG_COMPAT & flags) {
-                        err = __sys_sendmsg(sock, (struct msghdr __user *)compat_entry,
-                                            &msg_sys, flags, &used_address);
+                        err = ___sys_sendmsg(sock, (struct msghdr __user *)compat_entry,
+                                             &msg_sys, flags, &used_address);
                         if (err < 0)
                                 break;
                         err = __put_user(err, &compat_entry->msg_len);
                         ++compat_entry;
                 } else {
-                        err = __sys_sendmsg(sock, (struct msghdr __user *)entry,
-                                            &msg_sys, flags, &used_address);
+                        err = ___sys_sendmsg(sock,
+                                             (struct msghdr __user *)entry,
+                                             &msg_sys, flags, &used_address);
                         if (err < 0)
                                 break;
                         err = put_user(err, &entry->msg_len);
@@ -2149,10 +2158,12 @@ int __sys_sendmmsg(int fd, struct mmsghdr __user *mmsg, unsigned int vlen,
 SYSCALL_DEFINE4(sendmmsg, int, fd, struct mmsghdr __user *, mmsg,
                 unsigned int, vlen, unsigned int, flags)
 {
+        if (flags & MSG_CMSG_COMPAT)
+                return -EINVAL;
         return __sys_sendmmsg(fd, mmsg, vlen, flags);
 }
 
-static int __sys_recvmsg(struct socket *sock, struct msghdr __user *msg,
+static int ___sys_recvmsg(struct socket *sock, struct msghdr __user *msg,
                          struct msghdr *msg_sys, unsigned int flags, int nosec)
 {
         struct compat_msghdr __user *msg_compat =
@@ -2244,23 +2255,31 @@ out:
  *      BSD recvmsg interface
  */
 
-SYSCALL_DEFINE3(recvmsg, int, fd, struct msghdr __user *, msg,
-                unsigned int, flags)
+long __sys_recvmsg(int fd, struct msghdr __user *msg, unsigned flags)
 {
         int fput_needed, err;
         struct msghdr msg_sys;
-        struct socket *sock = sockfd_lookup_light(fd, &err, &fput_needed);
+        struct socket *sock;
 
+        sock = sockfd_lookup_light(fd, &err, &fput_needed);
         if (!sock)
                 goto out;
 
-        err = __sys_recvmsg(sock, msg, &msg_sys, flags, 0);
+        err = ___sys_recvmsg(sock, msg, &msg_sys, flags, 0);
 
         fput_light(sock->file, fput_needed);
 out:
         return err;
 }
 
+SYSCALL_DEFINE3(recvmsg, int, fd, struct msghdr __user *, msg,
+                unsigned int, flags)
+{
+        if (flags & MSG_CMSG_COMPAT)
+                return -EINVAL;
+        return __sys_recvmsg(fd, msg, flags);
+}
+
 /*
  *     Linux recvmmsg interface
  */
@@ -2298,17 +2317,18 @@ int __sys_recvmmsg(int fd, struct mmsghdr __user *mmsg, unsigned int vlen,
                  * No need to ask LSM for more than the first datagram.
                  */
                 if (MSG_CMSG_COMPAT & flags) {
-                        err = __sys_recvmsg(sock, (struct msghdr __user *)compat_entry,
-                                            &msg_sys, flags & ~MSG_WAITFORONE,
-                                            datagrams);
+                        err = ___sys_recvmsg(sock, (struct msghdr __user *)compat_entry,
+                                             &msg_sys, flags & ~MSG_WAITFORONE,
+                                             datagrams);
                         if (err < 0)
                                 break;
                         err = __put_user(err, &compat_entry->msg_len);
                         ++compat_entry;
                 } else {
-                        err = __sys_recvmsg(sock, (struct msghdr __user *)entry,
-                                            &msg_sys, flags & ~MSG_WAITFORONE,
-                                            datagrams);
+                        err = ___sys_recvmsg(sock,
+                                             (struct msghdr __user *)entry,
+                                             &msg_sys, flags & ~MSG_WAITFORONE,
+                                             datagrams);
                         if (err < 0)
                                 break;
                         err = put_user(err, &entry->msg_len);
@@ -2375,6 +2395,9 @@ SYSCALL_DEFINE5(recvmmsg, int, fd, struct mmsghdr __user *, mmsg,
         int datagrams;
         struct timespec timeout_sys;
 
+        if (flags & MSG_CMSG_COMPAT)
+                return -EINVAL;
+
         if (!timeout)
                 return __sys_recvmmsg(fd, mmsg, vlen, flags, NULL);
 
diff --git a/net/sunrpc/auth_gss/svcauth_gss.c b/net/sunrpc/auth_gss/svcauth_gss.c
index 871c73c92165..29b4ba93ab3c 100644
--- a/net/sunrpc/auth_gss/svcauth_gss.c
+++ b/net/sunrpc/auth_gss/svcauth_gss.c
@@ -1287,7 +1287,7 @@ static bool use_gss_proxy(struct net *net)
 
 #ifdef CONFIG_PROC_FS
 
-static bool set_gss_proxy(struct net *net, int type)
+static int set_gss_proxy(struct net *net, int type)
 {
         struct sunrpc_net *sn = net_generic(net, sunrpc_net_id);
         int ret = 0;
@@ -1317,10 +1317,12 @@ static inline bool gssp_ready(struct sunrpc_net *sn)
         return false;
 }
 
-static int wait_for_gss_proxy(struct net *net)
+static int wait_for_gss_proxy(struct net *net, struct file *file)
 {
         struct sunrpc_net *sn = net_generic(net, sunrpc_net_id);
 
+        if (file->f_flags & O_NONBLOCK && !gssp_ready(sn))
+                return -EAGAIN;
         return wait_event_interruptible(sn->gssp_wq, gssp_ready(sn));
 }
 
@@ -1362,7 +1364,7 @@ static ssize_t read_gssp(struct file *file, char __user *buf,
         size_t len;
         int ret;
 
-        ret = wait_for_gss_proxy(net);
+        ret = wait_for_gss_proxy(net, file);
         if (ret)
                 return ret;
 
diff --git a/net/sunrpc/svcauth_unix.c b/net/sunrpc/svcauth_unix.c
index c3f9e1ef7f53..06bdf5a1082c 100644
--- a/net/sunrpc/svcauth_unix.c
+++ b/net/sunrpc/svcauth_unix.c
@@ -810,11 +810,15 @@ svcauth_unix_accept(struct svc_rqst *rqstp, __be32 *authp)
                 goto badcred;
         argv->iov_base = (void*)((__be32*)argv->iov_base + slen);       /* skip machname */
         argv->iov_len -= slen*4;
-
+        /*
+         * Note: we skip uid_valid()/gid_valid() checks here for
+         * backwards compatibility with clients that use -1 id's.
+         * Instead, -1 uid or gid is later mapped to the
+         * (export-specific) anonymous id by nfsd_setuser.
+         * Supplementary gid's will be left alone.
+         */
         cred->cr_uid = make_kuid(&init_user_ns, svc_getnl(argv)); /* uid */
         cred->cr_gid = make_kgid(&init_user_ns, svc_getnl(argv)); /* gid */
-        if (!uid_valid(cred->cr_uid) || !gid_valid(cred->cr_gid))
-                goto badcred;
         slen = svc_getnl(argv);                 /* gids length */
         if (slen > 16 || (len -= (slen + 2)*4) < 0)
                 goto badcred;
@@ -823,8 +827,6 @@ svcauth_unix_accept(struct svc_rqst *rqstp, __be32 *authp)
                 return SVC_CLOSE;
         for (i = 0; i < slen; i++) {
                 kgid_t kgid = make_kgid(&init_user_ns, svc_getnl(argv));
-                if (!gid_valid(kgid))
-                        goto badcred;
                 GROUP_AT(cred->cr_group_info, i) = kgid;
         }
         if (svc_getu32(argv) != htonl(RPC_AUTH_NULL) || svc_getu32(argv) != 0) {
diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c
index dfdb5e643211..d5aed3bb3945 100644
--- a/net/wireless/nl80211.c
+++ b/net/wireless/nl80211.c
@@ -3411,7 +3411,7 @@ static int nl80211_send_station(struct sk_buff *msg, u32 portid, u32 seq,
                         (u32)sinfo->rx_bytes))
                 goto nla_put_failure;
         if ((sinfo->filled & (STATION_INFO_TX_BYTES |
-                              NL80211_STA_INFO_TX_BYTES64)) &&
+                              STATION_INFO_TX_BYTES64)) &&
             nla_put_u32(msg, NL80211_STA_INFO_TX_BYTES,
                         (u32)sinfo->tx_bytes))
                 goto nla_put_failure;
diff --git a/net/wireless/sme.c b/net/wireless/sme.c
index 8b5eddfba1e5..3ed35c345cae 100644
--- a/net/wireless/sme.c
+++ b/net/wireless/sme.c
@@ -231,6 +231,9 @@ void cfg80211_conn_work(struct work_struct *work)
         mutex_lock(&rdev->sched_scan_mtx);
 
         list_for_each_entry(wdev, &rdev->wdev_list, list) {
+                if (!wdev->netdev)
+                        continue;
+
                 wdev_lock(wdev);
                 if (!netif_running(wdev->netdev)) {
                         wdev_unlock(wdev);
diff --git a/net/xfrm/xfrm_policy.c b/net/xfrm/xfrm_policy.c
index 23cea0f74336..ea970b8002a2 100644
--- a/net/xfrm/xfrm_policy.c
+++ b/net/xfrm/xfrm_policy.c
@@ -2557,11 +2557,12 @@ static void __xfrm_garbage_collect(struct net *net)
         }
 }
 
-static void xfrm_garbage_collect(struct net *net)
+void xfrm_garbage_collect(struct net *net)
 {
         flow_cache_flush();
         __xfrm_garbage_collect(net);
 }
+EXPORT_SYMBOL(xfrm_garbage_collect);
 
 static void xfrm_garbage_collect_deferred(struct net *net)
 {
diff --git a/net/xfrm/xfrm_user.c b/net/xfrm/xfrm_user.c
index aa778748c565..3f565e495ac6 100644
--- a/net/xfrm/xfrm_user.c
+++ b/net/xfrm/xfrm_user.c
@@ -1681,6 +1681,8 @@ static int xfrm_get_policy(struct sk_buff *skb, struct nlmsghdr *nlh,
 
 out:
         xfrm_pol_put(xp);
+        if (delete && err == 0)
+                xfrm_garbage_collect(net);
         return err;
 }
 
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 51bb3de680b6..f97869f1f09b 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -149,7 +149,7 @@ cpp_flags      = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(LINUXINCLUDE)     \
 
 ld_flags       = $(LDFLAGS) $(ldflags-y)
 
-dtc_cpp_flags  = -Wp,-MD,$(depfile).pre -nostdinc                        \
+dtc_cpp_flags  = -Wp,-MD,$(depfile).pre.tmp -nostdinc                    \
                  -I$(srctree)/arch/$(SRCARCH)/boot/dts                   \
                  -I$(srctree)/arch/$(SRCARCH)/boot/dts/include           \
                  -undef -D__DTS__
@@ -264,14 +264,14 @@ $(obj)/%.dtb.S: $(obj)/%.dtb
 quiet_cmd_dtc = DTC     $@
 cmd_dtc = $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
         $(objtree)/scripts/dtc/dtc -O dtb -o $@ -b 0 \
-                -i $(srctree)/arch/$(SRCARCH)/boot/dts $(DTC_FLAGS) \
-                -d $(depfile).dtc $(dtc-tmp) ; \
-        cat $(depfile).pre $(depfile).dtc > $(depfile)
+                -i $(dir $<) $(DTC_FLAGS) \
+                -d $(depfile).dtc.tmp $(dtc-tmp) ; \
+        cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
 
 $(obj)/%.dtb: $(src)/%.dts FORCE
         $(call if_changed_dep,dtc)
 
-dtc-tmp = $(subst $(comma),_,$(dot-target).dts)
+dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
 
 # Bzip2
 # ---------------------------------------------------------------------------
diff --git a/scripts/config b/scripts/config
index bb4d3deb6d1c..a65ecbbdd32a 100755
--- a/scripts/config
+++ b/scripts/config
@@ -105,7 +105,7 @@ while [ "$1" != "" ] ; do
                 ;;
         --refresh)
                 ;;
-        --*-after)
+        --*-after|-E|-D|-M)
                 checkarg "$1"
                 A=$ARG
                 checkarg "$2"
diff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l
index 254d5af88956..3b41bfca636c 100644
--- a/scripts/dtc/dtc-lexer.l
+++ b/scripts/dtc/dtc-lexer.l
@@ -71,7 +71,7 @@ static int pop_input_file(void);
                         push_input_file(name);
                 }
 
-<*>^"#"(line)?{WS}+[0-9]+{WS}+{STRING}({WS}+[0-9]+)? {
+<*>^"#"(line)?[ \t]+[0-9]+[ \t]+{STRING}([ \t]+[0-9]+)? {
                         char *line, *tmp, *fn;
                         /* skip text before line # */
                         line = yytext;
diff --git a/scripts/dtc/dtc-lexer.lex.c_shipped b/scripts/dtc/dtc-lexer.lex.c_shipped
index a6c5fcdfc032..2d30f41778b7 100644
--- a/scripts/dtc/dtc-lexer.lex.c_shipped
+++ b/scripts/dtc/dtc-lexer.lex.c_shipped
@@ -405,19 +405,19 @@ static yyconst flex_int16_t yy_accept[161] =
 static yyconst flex_int32_t yy_ec[256] =
     {   0,
         1,    1,    1,    1,    1,    1,    1,    1,    2,    3,
-        2,    2,    2,    1,    1,    1,    1,    1,    1,    1,
+        4,    4,    4,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    2,    4,    5,    6,    1,    1,    7,    8,    1,
-        1,    9,   10,   10,   11,   10,   12,   13,   14,   15,
-       15,   15,   15,   15,   15,   15,   15,   16,    1,   17,
-       18,   19,   10,   10,   20,   20,   20,   20,   20,   20,
-       21,   21,   21,   21,   21,   22,   21,   21,   21,   21,
-       21,   21,   21,   21,   23,   21,   21,   24,   21,   21,
-        1,   25,   26,    1,   21,    1,   20,   27,   28,   29,
-
-       30,   20,   21,   21,   31,   21,   21,   32,   33,   34,
-       35,   36,   21,   37,   38,   39,   40,   41,   21,   24,
-       42,   21,   43,   44,   45,    1,    1,    1,    1,    1,
+        1,    2,    5,    6,    7,    1,    1,    8,    9,    1,
+        1,   10,   11,   11,   12,   11,   13,   14,   15,   16,
+       16,   16,   16,   16,   16,   16,   16,   17,    1,   18,
+       19,   20,   11,   11,   21,   21,   21,   21,   21,   21,
+       22,   22,   22,   22,   22,   23,   22,   22,   22,   22,
+       22,   22,   22,   22,   24,   22,   22,   25,   22,   22,
+        1,   26,   27,    1,   22,    1,   21,   28,   29,   30,
+
+       31,   21,   22,   22,   32,   22,   22,   33,   34,   35,
+       36,   37,   22,   38,   39,   40,   41,   42,   22,   25,
+       43,   22,   44,   45,   46,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
@@ -434,36 +434,36 @@ static yyconst flex_int32_t yy_ec[256] =
         1,    1,    1,    1,    1
     } ;
 
-static yyconst flex_int32_t yy_meta[46] =
+static yyconst flex_int32_t yy_meta[47] =
     {   0,
-        1,    1,    1,    1,    1,    2,    3,    1,    2,    2,
-        2,    4,    5,    5,    5,    6,    1,    1,    1,    7,
-        8,    8,    8,    8,    1,    1,    7,    7,    7,    7,
-        8,    8,    8,    8,    8,    8,    8,    8,    8,    8,
-        8,    8,    3,    1,    1
+        1,    1,    1,    1,    1,    1,    2,    3,    1,    2,
+        2,    2,    4,    5,    5,    5,    6,    1,    1,    1,
+        7,    8,    8,    8,    8,    1,    1,    7,    7,    7,
+        7,    8,    8,    8,    8,    8,    8,    8,    8,    8,
+        8,    8,    8,    3,    1,    1
     } ;
 
 static yyconst flex_int16_t yy_base[175] =
     {   0,
-        0,  388,  381,   40,   41,  386,   71,  385,   34,   44,
-      390,  395,   60,   62,  371,  112,  111,  111,  111,  104,
-      370,  106,  371,  342,  124,  119,    0,  144,  395,    0,
-      123,    0,  159,  153,  165,  167,  395,  130,  395,  382,
-      395,    0,  372,  122,  395,  157,  374,  379,  350,   21,
-      346,  349,  395,  395,  395,  395,  395,  362,  395,  395,
-      181,  346,  342,  395,  359,    0,  191,  343,  190,  351,
-      350,    0,    0,    0,  173,  362,  177,  367,  357,  329,
-      335,  328,  337,  331,  206,  329,  334,  327,  395,  338,
-      170,  314,  346,  345,  318,  325,  343,  158,  316,  212,
-
-      322,  319,  320,  395,  340,  336,  308,  305,  314,  304,
-      295,  138,  208,  220,  395,  292,  305,  265,  264,  254,
-      201,  222,  285,  275,  273,  270,  236,  235,  225,  115,
-      395,  395,  252,  216,  216,  217,  214,  230,  209,  220,
-      213,  239,  211,  217,  216,  209,  229,  395,  240,  225,
-      206,  169,  395,  395,  116,  106,   99,   54,  395,  395,
-      254,  260,  268,  272,  276,  282,  289,  293,  301,  309,
-      313,  319,  327,  335
+        0,  385,  378,   40,   41,  383,   72,  382,   34,   44,
+      388,  393,   61,  117,  368,  116,  115,  115,  115,   48,
+      367,  107,  368,  339,  127,  120,    0,  147,  393,    0,
+      127,    0,  133,  156,  168,  153,  393,  125,  393,  380,
+      393,    0,  369,  127,  393,  160,  371,  377,  347,   21,
+      343,  346,  393,  393,  393,  393,  393,  359,  393,  393,
+      183,  343,  339,  393,  356,    0,  183,  340,  187,  348,
+      347,    0,    0,    0,  178,  359,  195,  365,  354,  326,
+      332,  325,  334,  328,  204,  326,  331,  324,  393,  335,
+      150,  311,  343,  342,  315,  322,  340,  179,  313,  207,
+
+      319,  316,  317,  393,  337,  333,  305,  302,  311,  301,
+      310,  190,  338,  337,  393,  307,  322,  301,  305,  277,
+      208,  311,  307,  278,  271,  270,  248,  246,  213,  130,
+      393,  393,  263,  235,  207,  221,  218,  229,  213,  213,
+      206,  234,  218,  210,  208,  193,  219,  393,  223,  204,
+      176,  157,  393,  393,  120,  106,   97,  119,  393,  393,
+      245,  251,  259,  263,  267,  273,  280,  284,  292,  300,
+      304,  310,  318,  326
     } ;
 
 static yyconst flex_int16_t yy_def[175] =
@@ -489,108 +489,108 @@ static yyconst flex_int16_t yy_def[175] =
       160,  160,  160,  160
     } ;
 
-static yyconst flex_int16_t yy_nxt[441] =
+static yyconst flex_int16_t yy_nxt[440] =
     {   0,
-       12,   13,   14,   15,   16,   12,   17,   18,   12,   12,
-       12,   19,   12,   12,   12,   12,   20,   21,   22,   23,
-       23,   23,   23,   23,   12,   12,   23,   23,   23,   23,
+       12,   13,   14,   13,   15,   16,   12,   17,   18,   12,
+       12,   12,   19,   12,   12,   12,   12,   20,   21,   22,
+       23,   23,   23,   23,   23,   12,   12,   23,   23,   23,
        23,   23,   23,   23,   23,   23,   23,   23,   23,   23,
-       23,   23,   12,   24,   12,   25,   34,   35,   35,   25,
-       81,   26,   26,   27,   27,   27,   34,   35,   35,   82,
-       28,   36,   36,   36,   36,  159,   29,   28,   28,   28,
-       28,   12,   13,   14,   15,   16,   30,   17,   18,   30,
-       30,   30,   26,   30,   30,   30,   12,   20,   21,   22,
-       31,   31,   31,   31,   31,   32,   12,   31,   31,   31,
+       23,   23,   23,   12,   24,   12,   25,   34,   35,   35,
+       25,   81,   26,   26,   27,   27,   27,   34,   35,   35,
+       82,   28,   36,   36,   36,   53,   54,   29,   28,   28,
+       28,   28,   12,   13,   14,   13,   15,   16,   30,   17,
+       18,   30,   30,   30,   26,   30,   30,   30,   12,   20,
+       21,   22,   31,   31,   31,   31,   31,   32,   12,   31,
 
        31,   31,   31,   31,   31,   31,   31,   31,   31,   31,
-       31,   31,   31,   12,   24,   12,   39,   41,   45,   47,
-       53,   54,   48,   56,   57,   61,   61,   47,   66,   45,
-       48,   66,   66,   66,   39,   46,   40,   49,   59,   50,
-      158,   51,  122,   52,  157,   49,   46,   50,  136,   63,
-      137,   52,  156,   43,   40,   62,   65,   65,   65,   59,
-       61,   61,  123,   65,   75,   69,   69,   69,   36,   36,
-       65,   65,   65,   65,   70,   71,   72,   69,   69,   69,
-       45,   46,   61,   61,  109,   77,   70,   71,   93,  110,
-       68,   70,   71,   85,   85,   85,   66,   46,  155,   66,
-
-       66,   66,   69,   69,   69,  122,   59,  100,  100,   61,
-       61,   70,   71,  100,  100,  148,  112,  154,   85,   85,
-       85,   61,   61,  129,  129,  123,  129,  129,  135,  135,
-      135,  142,  142,  148,  143,  149,  153,  135,  135,  135,
-      142,  142,  160,  143,  152,  151,  150,  146,  145,  144,
-      141,  140,  139,  149,   38,   38,   38,   38,   38,   38,
-       38,   38,   42,  138,  134,  133,   42,   42,   44,   44,
-       44,   44,   44,   44,   44,   44,   58,   58,   58,   58,
-       64,  132,   64,   66,  131,  130,   66,  160,   66,   66,
-       67,  128,  127,   67,   67,   67,   67,   73,  126,   73,
-
-       73,   76,   76,   76,   76,   76,   76,   76,   76,   78,
-       78,   78,   78,   78,   78,   78,   78,   91,  125,   91,
-       92,  124,   92,   92,  120,   92,   92,  121,  121,  121,
-      121,  121,  121,  121,  121,  147,  147,  147,  147,  147,
-      147,  147,  147,  119,  118,  117,  116,  115,   47,  114,
-      110,  113,  111,  108,  107,  106,   48,  105,  104,   89,
-      103,  102,  101,   99,   98,   97,   96,   95,   94,   79,
-       77,   90,   89,   88,   59,   87,   86,   59,   84,   83,
-       80,   79,   77,   74,  160,   60,   59,   55,   37,  160,
-       33,   25,   26,   25,   11,  160,  160,  160,  160,  160,
+       31,   31,   31,   31,   31,   12,   24,   12,   36,   36,
+       36,   39,   41,   45,   47,   56,   57,   48,   61,   47,
+       39,  159,   48,   66,   61,   45,   66,   66,   66,  158,
+       46,   40,   49,   59,   50,  157,   51,   49,   52,   50,
+       40,   63,   46,   52,   36,   36,   36,  156,   43,   62,
+       65,   65,   65,   59,  136,   68,  137,   65,   75,   69,
+       69,   69,   70,   71,   65,   65,   65,   65,   70,   71,
+       72,   69,   69,   69,   61,   46,   45,  155,  154,   66,
+       70,   71,   66,   66,   66,  122,   85,   85,   85,   59,
+
+       69,   69,   69,   46,   77,  100,  109,   93,  100,   70,
+       71,  110,  112,  122,  129,  123,  153,   85,   85,   85,
+      135,  135,  135,  148,  148,  160,  135,  135,  135,  152,
+      142,  142,  142,  123,  143,  142,  142,  142,  151,  143,
+      150,  146,  145,  149,  149,   38,   38,   38,   38,   38,
+       38,   38,   38,   42,  144,  141,  140,   42,   42,   44,
+       44,   44,   44,   44,   44,   44,   44,   58,   58,   58,
+       58,   64,  139,   64,   66,  138,  134,   66,  133,   66,
+       66,   67,  132,  131,   67,   67,   67,   67,   73,  130,
+       73,   73,   76,   76,   76,   76,   76,   76,   76,   76,
+
+       78,   78,   78,   78,   78,   78,   78,   78,   91,  160,
+       91,   92,  129,   92,   92,  128,   92,   92,  121,  121,
+      121,  121,  121,  121,  121,  121,  147,  147,  147,  147,
+      147,  147,  147,  147,  127,  126,  125,  124,   61,   61,
+      120,  119,  118,  117,  116,  115,   47,  114,  110,  113,
+      111,  108,  107,  106,   48,  105,  104,   89,  103,  102,
+      101,   99,   98,   97,   96,   95,   94,   79,   77,   90,
+       89,   88,   59,   87,   86,   59,   84,   83,   80,   79,
+       77,   74,  160,   60,   59,   55,   37,  160,   33,   25,
+       26,   25,   11,  160,  160,  160,  160,  160,  160,  160,
 
       160,  160,  160,  160,  160,  160,  160,  160,  160,  160,
       160,  160,  160,  160,  160,  160,  160,  160,  160,  160,
       160,  160,  160,  160,  160,  160,  160,  160,  160,  160,
-      160,  160,  160,  160,  160,  160,  160,  160,  160,  160
+      160,  160,  160,  160,  160,  160,  160,  160,  160
     } ;
 
-static yyconst flex_int16_t yy_chk[441] =
+static yyconst flex_int16_t yy_chk[440] =
     {   0,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    4,    9,    9,    9,   10,
-       50,    4,    5,    5,    5,    5,   10,   10,   10,   50,
-        5,   13,   13,   14,   14,  158,    5,    5,    5,    5,
-        5,    7,    7,    7,    7,    7,    7,    7,    7,    7,
+        1,    1,    1,    1,    1,    1,    4,    9,    9,    9,
+       10,   50,    4,    5,    5,    5,    5,   10,   10,   10,
+       50,    5,   13,   13,   13,   20,   20,    5,    5,    5,
+        5,    5,    7,    7,    7,    7,    7,    7,    7,    7,
         7,    7,    7,    7,    7,    7,    7,    7,    7,    7,
         7,    7,    7,    7,    7,    7,    7,    7,    7,    7,
 
         7,    7,    7,    7,    7,    7,    7,    7,    7,    7,
-        7,    7,    7,    7,    7,    7,   16,   17,   18,   19,
-       20,   20,   19,   22,   22,   25,   25,   26,   31,   44,
-       26,   31,   31,   31,   38,   18,   16,   19,   31,   19,
-      157,   19,  112,   19,  156,   26,   44,   26,  130,   26,
-      130,   26,  155,   17,   38,   25,   28,   28,   28,   28,
-       33,   33,  112,   28,   46,   34,   34,   34,   36,   36,
-       28,   28,   28,   28,   34,   34,   34,   35,   35,   35,
-       75,   46,   61,   61,   98,   77,   35,   35,   77,   98,
-       33,   91,   91,   61,   61,   61,   67,   75,  152,   67,
-
-       67,   67,   69,   69,   69,  121,   67,   85,   85,  113,
-      113,   69,   69,  100,  100,  143,  100,  151,   85,   85,
-       85,  114,  114,  122,  122,  121,  129,  129,  135,  135,
-      135,  138,  138,  147,  138,  143,  150,  129,  129,  129,
-      142,  142,  149,  142,  146,  145,  144,  141,  140,  139,
-      137,  136,  134,  147,  161,  161,  161,  161,  161,  161,
-      161,  161,  162,  133,  128,  127,  162,  162,  163,  163,
-      163,  163,  163,  163,  163,  163,  164,  164,  164,  164,
-      165,  126,  165,  166,  125,  124,  166,  123,  166,  166,
-      167,  120,  119,  167,  167,  167,  167,  168,  118,  168,
-
-      168,  169,  169,  169,  169,  169,  169,  169,  169,  170,
-      170,  170,  170,  170,  170,  170,  170,  171,  117,  171,
-      172,  116,  172,  172,  111,  172,  172,  173,  173,  173,
-      173,  173,  173,  173,  173,  174,  174,  174,  174,  174,
-      174,  174,  174,  110,  109,  108,  107,  106,  105,  103,
-      102,  101,   99,   97,   96,   95,   94,   93,   92,   90,
-       88,   87,   86,   84,   83,   82,   81,   80,   79,   78,
-       76,   71,   70,   68,   65,   63,   62,   58,   52,   51,
-       49,   48,   47,   43,   40,   24,   23,   21,   15,   11,
-        8,    6,    3,    2,  160,  160,  160,  160,  160,  160,
+        7,    7,    7,    7,    7,    7,    7,    7,   14,   14,
+       14,   16,   17,   18,   19,   22,   22,   19,   25,   26,
+       38,  158,   26,   31,   33,   44,   31,   31,   31,  157,
+       18,   16,   19,   31,   19,  156,   19,   26,   19,   26,
+       38,   26,   44,   26,   36,   36,   36,  155,   17,   25,
+       28,   28,   28,   28,  130,   33,  130,   28,   46,   34,
+       34,   34,   91,   91,   28,   28,   28,   28,   34,   34,
+       34,   35,   35,   35,   61,   46,   75,  152,  151,   67,
+       35,   35,   67,   67,   67,  112,   61,   61,   61,   67,
+
+       69,   69,   69,   75,   77,   85,   98,   77,  100,   69,
+       69,   98,  100,  121,  129,  112,  150,   85,   85,   85,
+      135,  135,  135,  143,  147,  149,  129,  129,  129,  146,
+      138,  138,  138,  121,  138,  142,  142,  142,  145,  142,
+      144,  141,  140,  143,  147,  161,  161,  161,  161,  161,
+      161,  161,  161,  162,  139,  137,  136,  162,  162,  163,
+      163,  163,  163,  163,  163,  163,  163,  164,  164,  164,
+      164,  165,  134,  165,  166,  133,  128,  166,  127,  166,
+      166,  167,  126,  125,  167,  167,  167,  167,  168,  124,
+      168,  168,  169,  169,  169,  169,  169,  169,  169,  169,
+
+      170,  170,  170,  170,  170,  170,  170,  170,  171,  123,
+      171,  172,  122,  172,  172,  120,  172,  172,  173,  173,
+      173,  173,  173,  173,  173,  173,  174,  174,  174,  174,
+      174,  174,  174,  174,  119,  118,  117,  116,  114,  113,
+      111,  110,  109,  108,  107,  106,  105,  103,  102,  101,
+       99,   97,   96,   95,   94,   93,   92,   90,   88,   87,
+       86,   84,   83,   82,   81,   80,   79,   78,   76,   71,
+       70,   68,   65,   63,   62,   58,   52,   51,   49,   48,
+       47,   43,   40,   24,   23,   21,   15,   11,    8,    6,
+        3,    2,  160,  160,  160,  160,  160,  160,  160,  160,
 
       160,  160,  160,  160,  160,  160,  160,  160,  160,  160,
       160,  160,  160,  160,  160,  160,  160,  160,  160,  160,
       160,  160,  160,  160,  160,  160,  160,  160,  160,  160,
-      160,  160,  160,  160,  160,  160,  160,  160,  160,  160
+      160,  160,  160,  160,  160,  160,  160,  160,  160
     } ;
 
 static yy_state_type yy_last_accepting_state;
diff --git a/scripts/dtc/dtc-parser.tab.c_shipped b/scripts/dtc/dtc-parser.tab.c_shipped
index 4af55900a15b..ee1d8c3042fb 100644
--- a/scripts/dtc/dtc-parser.tab.c_shipped
+++ b/scripts/dtc/dtc-parser.tab.c_shipped
@@ -1,10 +1,8 @@
+/* A Bison parser, made by GNU Bison 2.5.  */
 
-/* A Bison parser, made by GNU Bison 2.4.1.  */
-
-/* Skeleton implementation for Bison's Yacc-like parsers in C
+/* Bison implementation for Yacc-like parsers in C
    
-      Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006
-   Free Software Foundation, Inc.
+      Copyright (C) 1984, 1989-1990, 2000-2011 Free Software Foundation, Inc.
    
    This program is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
@@ -46,7 +44,7 @@
 #define YYBISON 1
 
 /* Bison version.  */
-#define YYBISON_VERSION "2.4.1"
+#define YYBISON_VERSION "2.5"
 
 /* Skeleton name.  */
 #define YYSKELETON_NAME "yacc.c"
@@ -67,7 +65,7 @@
 
 /* Copy the first part of user declarations.  */
 
-/* Line 189 of yacc.c  */
+/* Line 268 of yacc.c  */
 #line 21 "dtc-parser.y"
 
 #include <stdio.h>
@@ -88,8 +86,8 @@ static unsigned long long eval_literal(const char *s, int base, int bits);
 static unsigned char eval_char_literal(const char *s);
 
 
-/* Line 189 of yacc.c  */
-#line 93 "dtc-parser.tab.c"
+/* Line 268 of yacc.c  */
+#line 91 "dtc-parser.tab.c"
 
 /* Enabling traces.  */
 #ifndef YYDEBUG
@@ -147,7 +145,7 @@ static unsigned char eval_char_literal(const char *s);
 typedef union YYSTYPE
 {
 
-/* Line 214 of yacc.c  */
+/* Line 293 of yacc.c  */
 #line 40 "dtc-parser.y"
 
         char *propnodename;
@@ -171,8 +169,8 @@ typedef union YYSTYPE
 
 
 
-/* Line 214 of yacc.c  */
-#line 176 "dtc-parser.tab.c"
+/* Line 293 of yacc.c  */
+#line 174 "dtc-parser.tab.c"
 } YYSTYPE;
 # define YYSTYPE_IS_TRIVIAL 1
 # define yystype YYSTYPE /* obsolescent; will be withdrawn */
@@ -183,8 +181,8 @@ typedef union YYSTYPE
 /* Copy the second part of user declarations.  */
 
 
-/* Line 264 of yacc.c  */
-#line 188 "dtc-parser.tab.c"
+/* Line 343 of yacc.c  */
+#line 186 "dtc-parser.tab.c"
 
 #ifdef short
 # undef short
@@ -234,7 +232,7 @@ typedef short int yytype_int16;
 #define YYSIZE_MAXIMUM ((YYSIZE_T) -1)
 
 #ifndef YY_
-# if YYENABLE_NLS
+# if defined YYENABLE_NLS && YYENABLE_NLS
 #  if ENABLE_NLS
 #   include <libintl.h> /* INFRINGES ON USER NAME SPACE */
 #   define YY_(msgid) dgettext ("bison-runtime", msgid)
@@ -287,11 +285,11 @@ YYID (yyi)
 #    define alloca _alloca
 #   else
 #    define YYSTACK_ALLOC alloca
-#    if ! defined _ALLOCA_H && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
+#    if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \
      || defined __cplusplus || defined _MSC_VER)
 #     include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
-#     ifndef _STDLIB_H
-#      define _STDLIB_H 1
+#     ifndef EXIT_SUCCESS
+#      define EXIT_SUCCESS 0
 #     endif
 #    endif
 #   endif
@@ -314,24 +312,24 @@ YYID (yyi)
 #  ifndef YYSTACK_ALLOC_MAXIMUM
 #   define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM
 #  endif
-#  if (defined __cplusplus && ! defined _STDLIB_H \
+#  if (defined __cplusplus && ! defined EXIT_SUCCESS \
        && ! ((defined YYMALLOC || defined malloc) \
              && (defined YYFREE || defined free)))
 #   include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
-#   ifndef _STDLIB_H
-#    define _STDLIB_H 1
+#   ifndef EXIT_SUCCESS
+#    define EXIT_SUCCESS 0
 #   endif
 #  endif
 #  ifndef YYMALLOC
 #   define YYMALLOC malloc
-#   if ! defined malloc && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
+#   if ! defined malloc && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \
      || defined __cplusplus || defined _MSC_VER)
 void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
 #   endif
 #  endif
 #  ifndef YYFREE
 #   define YYFREE free
-#   if ! defined free && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
+#   if ! defined free && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \
      || defined __cplusplus || defined _MSC_VER)
 void free (void *); /* INFRINGES ON USER NAME SPACE */
 #   endif
@@ -360,23 +358,7 @@ union yyalloc
      ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \
       + YYSTACK_GAP_MAXIMUM)
 
-/* Copy COUNT objects from FROM to TO.  The source and destination do
-   not overlap.  */
-# ifndef YYCOPY
-#  if defined __GNUC__ && 1 < __GNUC__
-#   define YYCOPY(To, From, Count) \
-      __builtin_memcpy (To, From, (Count) * sizeof (*(From)))
-#  else
-#   define YYCOPY(To, From, Count)              \
-      do                                        \
-        {                                       \
-          YYSIZE_T yyi;                         \
-          for (yyi = 0; yyi < (Count); yyi++)   \
-            (To)[yyi] = (From)[yyi];            \
-        }                                       \
-      while (YYID (0))
-#  endif
-# endif
+# define YYCOPY_NEEDED 1
 
 /* Relocate STACK from its old location to the new one.  The
    local variables YYSIZE and YYSTACKSIZE give the old and new number of
@@ -396,6 +378,26 @@ union yyalloc
 
 #endif
 
+#if defined YYCOPY_NEEDED && YYCOPY_NEEDED
+/* Copy COUNT objects from FROM to TO.  The source and destination do
+   not overlap.  */
+# ifndef YYCOPY
+#  if defined __GNUC__ && 1 < __GNUC__
+#   define YYCOPY(To, From, Count) \
+      __builtin_memcpy (To, From, (Count) * sizeof (*(From)))
+#  else
+#   define YYCOPY(To, From, Count)              \
+      do                                        \
+        {                                       \
+          YYSIZE_T yyi;                         \
+          for (yyi = 0; yyi < (Count); yyi++)   \
+            (To)[yyi] = (From)[yyi];            \
+        }                                       \
+      while (YYID (0))
+#  endif
+# endif
+#endif /* !YYCOPY_NEEDED */
+
 /* YYFINAL -- State number of the termination state.  */
 #define YYFINAL  4
 /* YYLAST -- Last index in YYTABLE.  */
@@ -571,8 +573,8 @@ static const yytype_uint8 yyr2[] =
        2,     0,     2,     2,     0,     2,     2,     2,     3,     2
 };
 
-/* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state
-   STATE-NUM when YYTABLE doesn't specify something else to do.  Zero
+/* YYDEFACT[STATE-NAME] -- Default reduction number in state STATE-NUM.
+   Performed when YYTABLE doesn't specify something else to do.  Zero
    means the default is an error.  */
 static const yytype_uint8 yydefact[] =
 {
@@ -633,8 +635,7 @@ static const yytype_int8 yypgoto[] =
 
 /* YYTABLE[YYPACT[STATE-NUM]].  What to do in state STATE-NUM.  If
    positive, shift that token.  If negative, reduce the rule which
-   number is the opposite.  If zero, do what YYDEFACT says.
-   If YYTABLE_NINF, syntax error.  */
+   number is the opposite.  If YYTABLE_NINF, syntax error.  */
 #define YYTABLE_NINF -1
 static const yytype_uint8 yytable[] =
 {
@@ -654,6 +655,12 @@ static const yytype_uint8 yytable[] =
      137,     0,    73,   139
 };
 
+#define yypact_value_is_default(yystate) \
+  ((yystate) == (-78))
+
+#define yytable_value_is_error(yytable_value) \
+  YYID (0)
+
 static const yytype_int16 yycheck[] =
 {
        5,    38,    39,    17,    18,    19,    12,    12,    17,    18,
@@ -705,9 +712,18 @@ static const yytype_uint8 yystos[] =
 
 /* Like YYERROR except do call yyerror.  This remains here temporarily
    to ease the transition to the new meaning of YYERROR, for GCC.
-   Once GCC version 2 has supplanted version 1, this can go.  */
+   Once GCC version 2 has supplanted version 1, this can go.  However,
+   YYFAIL appears to be in use.  Nevertheless, it is formally deprecated
+   in Bison 2.4.2's NEWS entry, where a plan to phase it out is
+   discussed.  */
 
 #define YYFAIL          goto yyerrlab
+#if defined YYFAIL
+  /* This is here to suppress warnings from the GCC cpp's
+     -Wunused-macros.  Normally we don't worry about that warning, but
+     some users do, and we want to make it easy for users to remove
+     YYFAIL uses, which will produce warnings from Bison 2.5.  */
+#endif
 
 #define YYRECOVERING()  (!!yyerrstatus)
 
@@ -717,7 +733,6 @@ do								\
     {                                                           \
       yychar = (Token);                                         \
       yylval = (Value);                                         \
-      yytoken = YYTRANSLATE (yychar);                           \
       YYPOPSTACK (1);                                           \
       goto yybackup;                                            \
     }                                                           \
@@ -759,19 +774,10 @@ while (YYID (0))
 #endif
 
 
-/* YY_LOCATION_PRINT -- Print the location on the stream.
-   This macro was not mandated originally: define only if we know
-   we won't break user code: when these are the locations we know.  */
+/* This macro is provided for backward compatibility. */
 
 #ifndef YY_LOCATION_PRINT
-# if YYLTYPE_IS_TRIVIAL
-#  define YY_LOCATION_PRINT(File, Loc)                  \
-     fprintf (File, "%d.%d-%d.%d",                      \
-              (Loc).first_line, (Loc).first_column,     \
-              (Loc).last_line,  (Loc).last_column)
-# else
-#  define YY_LOCATION_PRINT(File, Loc) ((void) 0)
-# endif
+# define YY_LOCATION_PRINT(File, Loc) ((void) 0)
 #endif
 
 
@@ -963,7 +969,6 @@ int yydebug;
 # define YYMAXDEPTH 10000
 #endif
 
-
 
 #if YYERROR_VERBOSE
 
@@ -1066,115 +1071,142 @@ yytnamerr (char *yyres, const char *yystr)
 }
 # endif
 
-/* Copy into YYRESULT an error message about the unexpected token
-   YYCHAR while in state YYSTATE.  Return the number of bytes copied,
-   including the terminating null byte.  If YYRESULT is null, do not
-   copy anything; just return the number of bytes that would be
-   copied.  As a special case, return 0 if an ordinary "syntax error"
-   message will do.  Return YYSIZE_MAXIMUM if overflow occurs during
-   size calculation.  */
-static YYSIZE_T
-yysyntax_error (char *yyresult, int yystate, int yychar)
-{
-  int yyn = yypact[yystate];
+/* Copy into *YYMSG, which is of size *YYMSG_ALLOC, an error message
+   about the unexpected token YYTOKEN for the state stack whose top is
+   YYSSP.
 
-  if (! (YYPACT_NINF < yyn && yyn <= YYLAST))
-    return 0;
-  else
+   Return 0 if *YYMSG was successfully written.  Return 1 if *YYMSG is
+   not large enough to hold the message.  In that case, also set
+   *YYMSG_ALLOC to the required number of bytes.  Return 2 if the
+   required number of bytes is too large to store.  */
+static int
+yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg,
+                yytype_int16 *yyssp, int yytoken)
+{
+  YYSIZE_T yysize0 = yytnamerr (0, yytname[yytoken]);
+  YYSIZE_T yysize = yysize0;
+  YYSIZE_T yysize1;
+  enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };
+  /* Internationalized format string. */
+  const char *yyformat = 0;
+  /* Arguments of yyformat. */
+  char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
+  /* Number of reported tokens (one for the "unexpected", one per
+     "expected"). */
+  int yycount = 0;
+
+  /* There are many possibilities here to consider:
+     - Assume YYFAIL is not used.  It's too flawed to consider.  See
+       <http://lists.gnu.org/archive/html/bison-patches/2009-12/msg00024.html>
+       for details.  YYERROR is fine as it does not invoke this
+       function.
+     - If this state is a consistent state with a default action, then
+       the only way this function was invoked is if the default action
+       is an error action.  In that case, don't check for expected
+       tokens because there are none.
+     - The only way there can be no lookahead present (in yychar) is if
+       this state is a consistent state with a default action.  Thus,
+       detecting the absence of a lookahead is sufficient to determine
+       that there is no unexpected or expected token to report.  In that
+       case, just report a simple "syntax error".
+     - Don't assume there isn't a lookahead just because this state is a
+       consistent state with a default action.  There might have been a
+       previous inconsistent state, consistent state with a non-default
+       action, or user semantic action that manipulated yychar.
+     - Of course, the expected token list depends on states to have
+       correct lookahead information, and it depends on the parser not
+       to perform extra reductions after fetching a lookahead from the
+       scanner and before detecting a syntax error.  Thus, state merging
+       (from LALR or IELR) and default reductions corrupt the expected
+       token list.  However, the list is correct for canonical LR with
+       one exception: it will still contain any token that will not be
+       accepted due to an error action in a later state.
+  */
+  if (yytoken != YYEMPTY)
     {
-      int yytype = YYTRANSLATE (yychar);
-      YYSIZE_T yysize0 = yytnamerr (0, yytname[yytype]);
-      YYSIZE_T yysize = yysize0;
-      YYSIZE_T yysize1;
-      int yysize_overflow = 0;
-      enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };
-      char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
-      int yyx;
-
-# if 0
-      /* This is so xgettext sees the translatable formats that are
-         constructed on the fly.  */
-      YY_("syntax error, unexpected %s");
-      YY_("syntax error, unexpected %s, expecting %s");
-      YY_("syntax error, unexpected %s, expecting %s or %s");
-      YY_("syntax error, unexpected %s, expecting %s or %s or %s");
-      YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s");
-# endif
-      char *yyfmt;
-      char const *yyf;
-      static char const yyunexpected[] = "syntax error, unexpected %s";
-      static char const yyexpecting[] = ", expecting %s";
-      static char const yyor[] = " or %s";
-      char yyformat[sizeof yyunexpected
-                    + sizeof yyexpecting - 1
-                    + ((YYERROR_VERBOSE_ARGS_MAXIMUM - 2)
-                       * (sizeof yyor - 1))];
-      char const *yyprefix = yyexpecting;
-
-      /* Start YYX at -YYN if negative to avoid negative indexes in
-         YYCHECK.  */
-      int yyxbegin = yyn < 0 ? -yyn : 0;
-
-      /* Stay within bounds of both yycheck and yytname.  */
-      int yychecklim = YYLAST - yyn + 1;
-      int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
-      int yycount = 1;
-
-      yyarg[0] = yytname[yytype];
-      yyfmt = yystpcpy (yyformat, yyunexpected);
-
-      for (yyx = yyxbegin; yyx < yyxend; ++yyx)
-        if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR)
-          {
-            if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
-              {
-                yycount = 1;
-                yysize = yysize0;
-                yyformat[sizeof yyunexpected - 1] = '\0';
-                break;
-              }
-            yyarg[yycount++] = yytname[yyx];
-            yysize1 = yysize + yytnamerr (0, yytname[yyx]);
-            yysize_overflow |= (yysize1 < yysize);
-            yysize = yysize1;
-            yyfmt = yystpcpy (yyfmt, yyprefix);
-            yyprefix = yyor;
-          }
+      int yyn = yypact[*yyssp];
+      yyarg[yycount++] = yytname[yytoken];
+      if (!yypact_value_is_default (yyn))
+        {
+          /* Start YYX at -YYN if negative to avoid negative indexes in
+             YYCHECK.  In other words, skip the first -YYN actions for
+             this state because they are default actions.  */
+          int yyxbegin = yyn < 0 ? -yyn : 0;
+          /* Stay within bounds of both yycheck and yytname.  */
+          int yychecklim = YYLAST - yyn + 1;
+          int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
+          int yyx;
+
+          for (yyx = yyxbegin; yyx < yyxend; ++yyx)
+            if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR
+                && !yytable_value_is_error (yytable[yyx + yyn]))
+              {
+                if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
+                  {
+                    yycount = 1;
+                    yysize = yysize0;
+                    break;
+                  }
+                yyarg[yycount++] = yytname[yyx];
+                yysize1 = yysize + yytnamerr (0, yytname[yyx]);
+                if (! (yysize <= yysize1
+                       && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
+                  return 2;
+                yysize = yysize1;
+              }
+        }
+    }
 
-      yyf = YY_(yyformat);
-      yysize1 = yysize + yystrlen (yyf);
-      yysize_overflow |= (yysize1 < yysize);
-      yysize = yysize1;
+  switch (yycount)
+    {
+# define YYCASE_(N, S)                      \
+      case N:                               \
+        yyformat = S;                       \
+      break
+      YYCASE_(0, YY_("syntax error"));
+      YYCASE_(1, YY_("syntax error, unexpected %s"));
+      YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s"));
+      YYCASE_(3, YY_("syntax error, unexpected %s, expecting %s or %s"));
+      YYCASE_(4, YY_("syntax error, unexpected %s, expecting %s or %s or %s"));
+      YYCASE_(5, YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s"));
+# undef YYCASE_
+    }
 
-      if (yysize_overflow)
-        return YYSIZE_MAXIMUM;
+  yysize1 = yysize + yystrlen (yyformat);
+  if (! (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
+    return 2;
+  yysize = yysize1;
 
-      if (yyresult)
-        {
-          /* Avoid sprintf, as that infringes on the user's name space.
-             Don't have undefined behavior even if the translation
-             produced a string with the wrong number of "%s"s.  */
-          char *yyp = yyresult;
-          int yyi = 0;
-          while ((*yyp = *yyf) != '\0')
-            {
-              if (*yyp == '%' && yyf[1] == 's' && yyi < yycount)
-                {
-                  yyp += yytnamerr (yyp, yyarg[yyi++]);
-                  yyf += 2;
-                }
-              else
-                {
-                  yyp++;
-                  yyf++;
-                }
-            }
-        }
-      return yysize;
+  if (*yymsg_alloc < yysize)
+    {
+      *yymsg_alloc = 2 * yysize;
+      if (! (yysize <= *yymsg_alloc
+             && *yymsg_alloc <= YYSTACK_ALLOC_MAXIMUM))
+        *yymsg_alloc = YYSTACK_ALLOC_MAXIMUM;
+      return 1;
     }
+
+  /* Avoid sprintf, as that infringes on the user's name space.
+     Don't have undefined behavior even if the translation
+     produced a string with the wrong number of "%s"s.  */
+  {
+    char *yyp = *yymsg;
+    int yyi = 0;
+    while ((*yyp = *yyformat) != '\0')
+      if (*yyp == '%' && yyformat[1] == 's' && yyi < yycount)
+        {
+          yyp += yytnamerr (yyp, yyarg[yyi++]);
+          yyformat += 2;
+        }
+      else
+        {
+          yyp++;
+          yyformat++;
+        }
+  }
+  return 0;
 }
 #endif /* YYERROR_VERBOSE */
-
 
 /*-----------------------------------------------.
 | Release the memory associated to this symbol.  |
@@ -1207,6 +1239,7 @@ yydestruct (yymsg, yytype, yyvaluep)
     }
 }
 
+
 /* Prevent warnings from -Wmissing-prototypes.  */
 #ifdef YYPARSE_PARAM
 #if defined __STDC__ || defined __cplusplus
@@ -1233,10 +1266,9 @@ YYSTYPE yylval;
 int yynerrs;
 
 
-
-/*-------------------------.
-| yyparse or yypush_parse.  |
-`-------------------------*/
+/*----------.
+| yyparse.  |
+`----------*/
 
 #ifdef YYPARSE_PARAM
 #if (defined __STDC__ || defined __C99__FUNC__ \
@@ -1260,8 +1292,6 @@ yyparse ()
 #endif
 #endif
 {
-
-
     int yystate;
     /* Number of tokens to shift before error messages enabled.  */
     int yyerrstatus;
@@ -1416,7 +1446,7 @@ yybackup:
 
   /* First try to decide what to do without reference to lookahead token.  */
   yyn = yypact[yystate];
-  if (yyn == YYPACT_NINF)
+  if (yypact_value_is_default (yyn))
     goto yydefault;
 
   /* Not known => get a lookahead token if don't already have one.  */
@@ -1447,8 +1477,8 @@ yybackup:
   yyn = yytable[yyn];
   if (yyn <= 0)
     {
-      if (yyn == 0 || yyn == YYTABLE_NINF)
-        goto yyerrlab;
+      if (yytable_value_is_error (yyn))
+        goto yyerrlab;
       yyn = -yyn;
       goto yyreduce;
     }
@@ -1503,72 +1533,72 @@ yyreduce:
     {
         case 2:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 110 "dtc-parser.y"
     {
                         the_boot_info = build_boot_info((yyvsp[(3) - (4)].re), (yyvsp[(4) - (4)].node),
                                                         guess_boot_cpuid((yyvsp[(4) - (4)].node)));
-                ;}
+                }
     break;
 
   case 3:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 118 "dtc-parser.y"
     {
                         (yyval.re) = NULL;
-                ;}
+                }
     break;
 
   case 4:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 122 "dtc-parser.y"
     {
                         (yyval.re) = chain_reserve_entry((yyvsp[(1) - (2)].re), (yyvsp[(2) - (2)].re));
-                ;}
+                }
     break;
 
   case 5:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 129 "dtc-parser.y"
     {
                         (yyval.re) = build_reserve_entry((yyvsp[(2) - (4)].integer), (yyvsp[(3) - (4)].integer));
-                ;}
+                }
     break;
 
   case 6:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 133 "dtc-parser.y"
     {
                         add_label(&(yyvsp[(2) - (2)].re)->labels, (yyvsp[(1) - (2)].labelref));
                         (yyval.re) = (yyvsp[(2) - (2)].re);
-                ;}
+                }
     break;
 
   case 7:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 141 "dtc-parser.y"
     {
                         (yyval.node) = name_node((yyvsp[(2) - (2)].node), "");
-                ;}
+                }
     break;
 
   case 8:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 145 "dtc-parser.y"
     {
                         (yyval.node) = merge_nodes((yyvsp[(1) - (3)].node), (yyvsp[(3) - (3)].node));
-                ;}
+                }
     break;
 
   case 9:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 149 "dtc-parser.y"
     {
                         struct node *target = get_node_by_ref((yyvsp[(1) - (3)].node), (yyvsp[(2) - (3)].labelref));
@@ -1578,12 +1608,12 @@ yyreduce:
                         else
                                 print_error("label or path, '%s', not found", (yyvsp[(2) - (3)].labelref));
                         (yyval.node) = (yyvsp[(1) - (3)].node);
-                ;}
+                }
     break;
 
   case 10:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 159 "dtc-parser.y"
     {
                         struct node *target = get_node_by_ref((yyvsp[(1) - (4)].node), (yyvsp[(3) - (4)].labelref));
@@ -1594,112 +1624,112 @@ yyreduce:
                                 delete_node(target);
 
                         (yyval.node) = (yyvsp[(1) - (4)].node);
-                ;}
+                }
     break;
 
   case 11:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 173 "dtc-parser.y"
     {
                         (yyval.node) = build_node((yyvsp[(2) - (5)].proplist), (yyvsp[(3) - (5)].nodelist));
-                ;}
+                }
     break;
 
   case 12:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 180 "dtc-parser.y"
     {
                         (yyval.proplist) = NULL;
-                ;}
+                }
     break;
 
   case 13:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 184 "dtc-parser.y"
     {
                         (yyval.proplist) = chain_property((yyvsp[(2) - (2)].prop), (yyvsp[(1) - (2)].proplist));
-                ;}
+                }
     break;
 
   case 14:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 191 "dtc-parser.y"
     {
                         (yyval.prop) = build_property((yyvsp[(1) - (4)].propnodename), (yyvsp[(3) - (4)].data));
-                ;}
+                }
     break;
 
   case 15:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 195 "dtc-parser.y"
     {
                         (yyval.prop) = build_property((yyvsp[(1) - (2)].propnodename), empty_data);
-                ;}
+                }
     break;
 
   case 16:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 199 "dtc-parser.y"
     {
                         (yyval.prop) = build_property_delete((yyvsp[(2) - (3)].propnodename));
-                ;}
+                }
     break;
 
   case 17:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 203 "dtc-parser.y"
     {
                         add_label(&(yyvsp[(2) - (2)].prop)->labels, (yyvsp[(1) - (2)].labelref));
                         (yyval.prop) = (yyvsp[(2) - (2)].prop);
-                ;}
+                }
     break;
 
   case 18:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 211 "dtc-parser.y"
     {
                         (yyval.data) = data_merge((yyvsp[(1) - (2)].data), (yyvsp[(2) - (2)].data));
-                ;}
+                }
     break;
 
   case 19:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 215 "dtc-parser.y"
     {
                         (yyval.data) = data_merge((yyvsp[(1) - (3)].data), (yyvsp[(2) - (3)].array).data);
-                ;}
+                }
     break;
 
   case 20:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 219 "dtc-parser.y"
     {
                         (yyval.data) = data_merge((yyvsp[(1) - (4)].data), (yyvsp[(3) - (4)].data));
-                ;}
+                }
     break;
 
   case 21:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 223 "dtc-parser.y"
     {
                         (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), REF_PATH, (yyvsp[(2) - (2)].labelref));
-                ;}
+                }
     break;
 
   case 22:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 227 "dtc-parser.y"
     {
                         FILE *f = srcfile_relative_open((yyvsp[(4) - (9)].data).val, NULL);
@@ -1716,12 +1746,12 @@ yyreduce:
 
                         (yyval.data) = data_merge((yyvsp[(1) - (9)].data), d);
                         fclose(f);
-                ;}
+                }
     break;
 
   case 23:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 244 "dtc-parser.y"
     {
                         FILE *f = srcfile_relative_open((yyvsp[(4) - (5)].data).val, NULL);
@@ -1731,48 +1761,48 @@ yyreduce:
 
                         (yyval.data) = data_merge((yyvsp[(1) - (5)].data), d);
                         fclose(f);
-                ;}
+                }
     break;
 
   case 24:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 254 "dtc-parser.y"
     {
                         (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref));
-                ;}
+                }
     break;
 
   case 25:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 261 "dtc-parser.y"
     {
                         (yyval.data) = empty_data;
-                ;}
+                }
     break;
 
   case 26:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 265 "dtc-parser.y"
     {
                         (yyval.data) = (yyvsp[(1) - (2)].data);
-                ;}
+                }
     break;
 
   case 27:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 269 "dtc-parser.y"
     {
                         (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref));
-                ;}
+                }
     break;
 
   case 28:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 276 "dtc-parser.y"
     {
                         (yyval.array).data = empty_data;
@@ -1787,22 +1817,22 @@ yyreduce:
                                             " are currently supported");
                                 (yyval.array).bits = 32;
                         }
-                ;}
+                }
     break;
 
   case 29:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 291 "dtc-parser.y"
     {
                         (yyval.array).data = empty_data;
                         (yyval.array).bits = 32;
-                ;}
+                }
     break;
 
   case 30:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 296 "dtc-parser.y"
     {
                         if ((yyvsp[(1) - (2)].array).bits < 64) {
@@ -1822,12 +1852,12 @@ yyreduce:
                         }
 
                         (yyval.array).data = data_append_integer((yyvsp[(1) - (2)].array).data, (yyvsp[(2) - (2)].integer), (yyvsp[(1) - (2)].array).bits);
-                ;}
+                }
     break;
 
   case 31:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 316 "dtc-parser.y"
     {
                         uint64_t val = ~0ULL >> (64 - (yyvsp[(1) - (2)].array).bits);
@@ -1841,288 +1871,299 @@ yyreduce:
                                             "arrays with 32-bit elements.");
 
                         (yyval.array).data = data_append_integer((yyvsp[(1) - (2)].array).data, val, (yyvsp[(1) - (2)].array).bits);
-                ;}
+                }
     break;
 
   case 32:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 330 "dtc-parser.y"
     {
                         (yyval.array).data = data_add_marker((yyvsp[(1) - (2)].array).data, LABEL, (yyvsp[(2) - (2)].labelref));
-                ;}
+                }
     break;
 
   case 33:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 337 "dtc-parser.y"
     {
                         (yyval.integer) = eval_literal((yyvsp[(1) - (1)].literal), 0, 64);
-                ;}
+                }
     break;
 
   case 34:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 341 "dtc-parser.y"
     {
                         (yyval.integer) = eval_char_literal((yyvsp[(1) - (1)].literal));
-                ;}
+                }
     break;
 
   case 35:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 345 "dtc-parser.y"
     {
                         (yyval.integer) = (yyvsp[(2) - (3)].integer);
-                ;}
+                }
     break;
 
   case 38:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 356 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (5)].integer) ? (yyvsp[(3) - (5)].integer) : (yyvsp[(5) - (5)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (5)].integer) ? (yyvsp[(3) - (5)].integer) : (yyvsp[(5) - (5)].integer); }
     break;
 
   case 40:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 361 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) || (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) || (yyvsp[(3) - (3)].integer); }
     break;
 
   case 42:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 366 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) && (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) && (yyvsp[(3) - (3)].integer); }
     break;
 
   case 44:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 371 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) | (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) | (yyvsp[(3) - (3)].integer); }
     break;
 
   case 46:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 376 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) ^ (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) ^ (yyvsp[(3) - (3)].integer); }
     break;
 
   case 48:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 381 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) & (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) & (yyvsp[(3) - (3)].integer); }
     break;
 
   case 50:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 386 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) == (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) == (yyvsp[(3) - (3)].integer); }
     break;
 
   case 51:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 387 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) != (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) != (yyvsp[(3) - (3)].integer); }
     break;
 
   case 53:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 392 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) < (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) < (yyvsp[(3) - (3)].integer); }
     break;
 
   case 54:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 393 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) > (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) > (yyvsp[(3) - (3)].integer); }
     break;
 
   case 55:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 394 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) <= (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) <= (yyvsp[(3) - (3)].integer); }
     break;
 
   case 56:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 395 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) >= (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) >= (yyvsp[(3) - (3)].integer); }
     break;
 
   case 57:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 399 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) << (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) << (yyvsp[(3) - (3)].integer); }
     break;
 
   case 58:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 400 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) >> (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) >> (yyvsp[(3) - (3)].integer); }
     break;
 
   case 60:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 405 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) + (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) + (yyvsp[(3) - (3)].integer); }
     break;
 
   case 61:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 406 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) - (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) - (yyvsp[(3) - (3)].integer); }
     break;
 
   case 63:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 411 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) * (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) * (yyvsp[(3) - (3)].integer); }
     break;
 
   case 64:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 412 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) / (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) / (yyvsp[(3) - (3)].integer); }
     break;
 
   case 65:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 413 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) % (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) % (yyvsp[(3) - (3)].integer); }
     break;
 
   case 68:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 419 "dtc-parser.y"
-    { (yyval.integer) = -(yyvsp[(2) - (2)].integer); ;}
+    { (yyval.integer) = -(yyvsp[(2) - (2)].integer); }
     break;
 
   case 69:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 420 "dtc-parser.y"
-    { (yyval.integer) = ~(yyvsp[(2) - (2)].integer); ;}
+    { (yyval.integer) = ~(yyvsp[(2) - (2)].integer); }
     break;
 
   case 70:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 421 "dtc-parser.y"
-    { (yyval.integer) = !(yyvsp[(2) - (2)].integer); ;}
+    { (yyval.integer) = !(yyvsp[(2) - (2)].integer); }
     break;
 
   case 71:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 426 "dtc-parser.y"
     {
                         (yyval.data) = empty_data;
-                ;}
+                }
     break;
 
   case 72:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 430 "dtc-parser.y"
     {
                         (yyval.data) = data_append_byte((yyvsp[(1) - (2)].data), (yyvsp[(2) - (2)].byte));
-                ;}
+                }
     break;
 
   case 73:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 434 "dtc-parser.y"
     {
                         (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref));
-                ;}
+                }
     break;
 
   case 74:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 441 "dtc-parser.y"
     {
                         (yyval.nodelist) = NULL;
-                ;}
+                }
     break;
 
   case 75:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 445 "dtc-parser.y"
     {
                         (yyval.nodelist) = chain_node((yyvsp[(1) - (2)].node), (yyvsp[(2) - (2)].nodelist));
-                ;}
+                }
     break;
 
   case 76:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 449 "dtc-parser.y"
     {
                         print_error("syntax error: properties must precede subnodes");
                         YYERROR;
-                ;}
+                }
     break;
 
   case 77:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 457 "dtc-parser.y"
     {
                         (yyval.node) = name_node((yyvsp[(2) - (2)].node), (yyvsp[(1) - (2)].propnodename));
-                ;}
+                }
     break;
 
   case 78:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 461 "dtc-parser.y"
     {
                         (yyval.node) = name_node(build_node_delete(), (yyvsp[(2) - (3)].propnodename));
-                ;}
+                }
     break;
 
   case 79:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 465 "dtc-parser.y"
     {
                         add_label(&(yyvsp[(2) - (2)].node)->labels, (yyvsp[(1) - (2)].labelref));
                         (yyval.node) = (yyvsp[(2) - (2)].node);
-                ;}
+                }
     break;
 
 
 
-/* Line 1455 of yacc.c  */
-#line 2124 "dtc-parser.tab.c"
+/* Line 1806 of yacc.c  */
+#line 2154 "dtc-parser.tab.c"
       default: break;
     }
+  /* User semantic actions sometimes alter yychar, and that requires
+     that yytoken be updated with the new translation.  We take the
+     approach of translating immediately before every use of yytoken.
+     One alternative is translating here after every semantic action,
+     but that translation would be missed if the semantic action invokes
+     YYABORT, YYACCEPT, or YYERROR immediately after altering yychar or
+     if it invokes YYBACKUP.  In the case of YYABORT or YYACCEPT, an
+     incorrect destructor might then be invoked immediately.  In the
+     case of YYERROR or YYBACKUP, subsequent parser actions might lead
+     to an incorrect destructor call or verbose syntax error message
+     before the lookahead is translated.  */
   YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc);
 
   YYPOPSTACK (yylen);
@@ -2150,6 +2191,10 @@ yyreduce:
 | yyerrlab -- here on detecting error |
 `------------------------------------*/
 yyerrlab:
+  /* Make sure we have latest lookahead translation.  See comments at
+     user semantic actions for why this is necessary.  */
+  yytoken = yychar == YYEMPTY ? YYEMPTY : YYTRANSLATE (yychar);
+
   /* If not already recovering from an error, report this error.  */
   if (!yyerrstatus)
     {
@@ -2157,37 +2202,36 @@ yyerrlab:
 #if ! YYERROR_VERBOSE
       yyerror (YY_("syntax error"));
 #else
+# define YYSYNTAX_ERROR yysyntax_error (&yymsg_alloc, &yymsg, \
+                                        yyssp, yytoken)
       {
-        YYSIZE_T yysize = yysyntax_error (0, yystate, yychar);
-        if (yymsg_alloc < yysize && yymsg_alloc < YYSTACK_ALLOC_MAXIMUM)
-          {
-            YYSIZE_T yyalloc = 2 * yysize;
-            if (! (yysize <= yyalloc && yyalloc <= YYSTACK_ALLOC_MAXIMUM))
-              yyalloc = YYSTACK_ALLOC_MAXIMUM;
-            if (yymsg != yymsgbuf)
-              YYSTACK_FREE (yymsg);
-            yymsg = (char *) YYSTACK_ALLOC (yyalloc);
-            if (yymsg)
-              yymsg_alloc = yyalloc;
-            else
-              {
-                yymsg = yymsgbuf;
-                yymsg_alloc = sizeof yymsgbuf;
-              }
-          }
-
-        if (0 < yysize && yysize <= yymsg_alloc)
-          {
-            (void) yysyntax_error (yymsg, yystate, yychar);
-            yyerror (yymsg);
-          }
-        else
-          {
-            yyerror (YY_("syntax error"));
-            if (yysize != 0)
-              goto yyexhaustedlab;
-          }
+        char const *yymsgp = YY_("syntax error");
+        int yysyntax_error_status;
+        yysyntax_error_status = YYSYNTAX_ERROR;
+        if (yysyntax_error_status == 0)
+          yymsgp = yymsg;
+        else if (yysyntax_error_status == 1)
+          {
+            if (yymsg != yymsgbuf)
+              YYSTACK_FREE (yymsg);
+            yymsg = (char *) YYSTACK_ALLOC (yymsg_alloc);
+            if (!yymsg)
+              {
+                yymsg = yymsgbuf;
+                yymsg_alloc = sizeof yymsgbuf;
+                yysyntax_error_status = 2;
+              }
+            else
+              {
+                yysyntax_error_status = YYSYNTAX_ERROR;
+                yymsgp = yymsg;
+              }
+          }
+        yyerror (yymsgp);
+        if (yysyntax_error_status == 2)
+          goto yyexhaustedlab;
       }
+# undef YYSYNTAX_ERROR
 #endif
     }
 
@@ -2246,7 +2290,7 @@ yyerrlab1:
   for (;;)
     {
       yyn = yypact[yystate];
-      if (yyn != YYPACT_NINF)
+      if (!yypact_value_is_default (yyn))
         {
           yyn += YYTERROR;
           if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
@@ -2305,8 +2349,13 @@ yyexhaustedlab:
 
 yyreturn:
   if (yychar != YYEMPTY)
-     yydestruct ("Cleanup: discarding lookahead",
-                 yytoken, &yylval);
+    {
+      /* Make sure we have latest lookahead translation.  See comments at
+         user semantic actions for why this is necessary.  */
+      yytoken = YYTRANSLATE (yychar);
+      yydestruct ("Cleanup: discarding lookahead",
+                  yytoken, &yylval);
+    }
   /* Do not reclaim the symbols of the rule which action triggered
      this YYABORT or YYACCEPT.  */
   YYPOPSTACK (yylen);
@@ -2331,7 +2380,7 @@ yyreturn:
 
 
 
-/* Line 1675 of yacc.c  */
+/* Line 2067 of yacc.c  */
 #line 471 "dtc-parser.y"
 
 
diff --git a/scripts/dtc/dtc-parser.tab.h_shipped b/scripts/dtc/dtc-parser.tab.h_shipped
index 9d2dce41211f..25d3b88c6132 100644
--- a/scripts/dtc/dtc-parser.tab.h_shipped
+++ b/scripts/dtc/dtc-parser.tab.h_shipped
@@ -1,10 +1,8 @@
+/* A Bison parser, made by GNU Bison 2.5.  */
 
-/* A Bison parser, made by GNU Bison 2.4.1.  */
-
-/* Skeleton interface for Bison's Yacc-like parsers in C
+/* Bison interface for Yacc-like parsers in C
    
-      Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006
-   Free Software Foundation, Inc.
+      Copyright (C) 1984, 1989-1990, 2000-2011 Free Software Foundation, Inc.
    
    This program is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
@@ -70,7 +68,7 @@
 typedef union YYSTYPE
 {
 
-/* Line 1676 of yacc.c  */
+/* Line 2068 of yacc.c  */
 #line 40 "dtc-parser.y"
 
         char *propnodename;
@@ -94,8 +92,8 @@ typedef union YYSTYPE
 
 
 
-/* Line 1676 of yacc.c  */
-#line 99 "dtc-parser.tab.h"
+/* Line 2068 of yacc.c  */
+#line 97 "dtc-parser.tab.h"
 } YYSTYPE;
 # define YYSTYPE_IS_TRIVIAL 1
 # define yystype YYSTYPE /* obsolescent; will be withdrawn */
diff --git a/scripts/kconfig/lxdialog/menubox.c b/scripts/kconfig/lxdialog/menubox.c
index 48d382e7e374..38cd69c5660e 100644
--- a/scripts/kconfig/lxdialog/menubox.c
+++ b/scripts/kconfig/lxdialog/menubox.c
@@ -303,10 +303,11 @@ do_resize:
                                 }
                 }
 
-                if (i < max_choice ||
-                    key == KEY_UP || key == KEY_DOWN ||
-                    key == '-' || key == '+' ||
-                    key == KEY_PPAGE || key == KEY_NPAGE) {
+                if (item_count() != 0 &&
+                    (i < max_choice ||
+                     key == KEY_UP || key == KEY_DOWN ||
+                     key == '-' || key == '+' ||
+                     key == KEY_PPAGE || key == KEY_NPAGE)) {
                         /* Remove highligt of current item */
                         print_item(scroll + choice, choice, FALSE);
 
diff --git a/scripts/kconfig/mconf.c b/scripts/kconfig/mconf.c
index 387dc8daf7b2..a69cbd78fb38 100644
--- a/scripts/kconfig/mconf.c
+++ b/scripts/kconfig/mconf.c
@@ -670,11 +670,12 @@ static void conf(struct menu *menu, struct menu *active_menu)
                                   active_menu, &s_scroll);
                 if (res == 1 || res == KEY_ESC || res == -ERRDISPLAYTOOSMALL)
                         break;
-                if (!item_activate_selected())
-                        continue;
-                if (!item_tag())
-                        continue;
-
+                if (item_count() != 0) {
+                        if (!item_activate_selected())
+                                continue;
+                        if (!item_tag())
+                                continue;
+                }
                 submenu = item_data();
                 active_menu = item_data();
                 if (submenu)
diff --git a/scripts/kconfig/menu.c b/scripts/kconfig/menu.c
index b5c7d90df9df..fd3f0180e08f 100644
--- a/scripts/kconfig/menu.c
+++ b/scripts/kconfig/menu.c
@@ -146,11 +146,24 @@ struct property *menu_add_prop(enum prop_type type, char *prompt, struct expr *e
                         struct menu *menu = current_entry;
 
                         while ((menu = menu->parent) != NULL) {
+                                struct expr *dup_expr;
+
                                 if (!menu->visibility)
                                         continue;
+                                /*
+                                 * Do not add a reference to the
+                                 * menu's visibility expression but
+                                 * use a copy of it.  Otherwise the
+                                 * expression reduction functions
+                                 * will modify expressions that have
+                                 * multiple references which can
+                                 * cause unwanted side effects.
+                                 */
+                                dup_expr = expr_copy(menu->visibility);
+
                                 prop->visible.expr
                                         = expr_alloc_and(prop->visible.expr,
-                                                         menu->visibility);
+                                                         dup_expr);
                         }
                 }
 
diff --git a/security/selinux/xfrm.c b/security/selinux/xfrm.c
index 8ab295154517..d03081886214 100644
--- a/security/selinux/xfrm.c
+++ b/security/selinux/xfrm.c
@@ -316,6 +316,7 @@ int selinux_xfrm_policy_clone(struct xfrm_sec_ctx *old_ctx,
 
                 memcpy(new_ctx, old_ctx, sizeof(*new_ctx));
                 memcpy(new_ctx->ctx_str, old_ctx->ctx_str, new_ctx->ctx_len);
+                atomic_inc(&selinux_xfrm_refcount);
                 *new_ctxp = new_ctx;
         }
         return 0;
@@ -326,6 +327,7 @@ int selinux_xfrm_policy_clone(struct xfrm_sec_ctx *old_ctx,
  */
 void selinux_xfrm_policy_free(struct xfrm_sec_ctx *ctx)
 {
+        atomic_dec(&selinux_xfrm_refcount);
         kfree(ctx);
 }
 
@@ -335,17 +337,13 @@ void selinux_xfrm_policy_free(struct xfrm_sec_ctx *ctx)
 int selinux_xfrm_policy_delete(struct xfrm_sec_ctx *ctx)
 {
         const struct task_security_struct *tsec = current_security();
-        int rc = 0;
 
-        if (ctx) {
-                rc = avc_has_perm(tsec->sid, ctx->ctx_sid,
-                                  SECCLASS_ASSOCIATION,
-                                  ASSOCIATION__SETCONTEXT, NULL);
-                if (rc == 0)
-                        atomic_dec(&selinux_xfrm_refcount);
-        }
+        if (!ctx)
+                return 0;
 
-        return rc;
+        return avc_has_perm(tsec->sid, ctx->ctx_sid,
+                            SECCLASS_ASSOCIATION, ASSOCIATION__SETCONTEXT,
+                            NULL);
 }
 
 /*
@@ -370,8 +368,8 @@ int selinux_xfrm_state_alloc(struct xfrm_state *x, struct xfrm_user_sec_ctx *uct
  */
 void selinux_xfrm_state_free(struct xfrm_state *x)
 {
-        struct xfrm_sec_ctx *ctx = x->security;
-        kfree(ctx);
+        atomic_dec(&selinux_xfrm_refcount);
+        kfree(x->security);
 }
 
  /*
@@ -381,17 +379,13 @@ int selinux_xfrm_state_delete(struct xfrm_state *x)
 {
         const struct task_security_struct *tsec = current_security();
         struct xfrm_sec_ctx *ctx = x->security;
-        int rc = 0;
 
-        if (ctx) {
-                rc = avc_has_perm(tsec->sid, ctx->ctx_sid,
-                                  SECCLASS_ASSOCIATION,
-                                  ASSOCIATION__SETCONTEXT, NULL);
-                if (rc == 0)
-                        atomic_dec(&selinux_xfrm_refcount);
-        }
+        if (!ctx)
+                return 0;
 
-        return rc;
+        return avc_has_perm(tsec->sid, ctx->ctx_sid,
+                            SECCLASS_ASSOCIATION, ASSOCIATION__SETCONTEXT,
+                            NULL);
 }
 
 /*
diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c
index ccfa383f1fda..f92818155958 100644
--- a/sound/core/pcm_native.c
+++ b/sound/core/pcm_native.c
@@ -1649,6 +1649,7 @@ static int snd_pcm_link(struct snd_pcm_substream *substream, int fd)
         }
         if (!snd_pcm_stream_linked(substream)) {
                 substream->group = group;
+                group = NULL;
                 spin_lock_init(&substream->group->lock);
                 INIT_LIST_HEAD(&substream->group->substreams);
                 list_add_tail(&substream->link_list, &substream->group->substreams);
@@ -1663,8 +1664,7 @@ static int snd_pcm_link(struct snd_pcm_substream *substream, int fd)
  _nolock:
         snd_card_unref(substream1->pcm->card);
         fput_light(file, fput_needed);
-        if (res < 0)
-                kfree(group);
+        kfree(group);
         return res;
 }
 
diff --git a/sound/pci/hda/hda_generic.c b/sound/pci/hda/hda_generic.c
index ae85bbd2e6f8..4b1524a861f3 100644
--- a/sound/pci/hda/hda_generic.c
+++ b/sound/pci/hda/hda_generic.c
@@ -788,6 +788,8 @@ static void set_pin_eapd(struct hda_codec *codec, hda_nid_t pin, bool enable)
                 return;
         if (codec->inv_eapd)
                 enable = !enable;
+        if (spec->keep_eapd_on && !enable)
+                return;
         snd_hda_codec_update_cache(codec, pin, 0,
                                    AC_VERB_SET_EAPD_BTLENABLE,
                                    enable ? 0x02 : 0x00);
@@ -1938,17 +1940,7 @@ static int create_speaker_out_ctls(struct hda_codec *codec)
  * independent HP controls
  */
 
-/* update HP auto-mute state too */
-static void update_hp_automute_hook(struct hda_codec *codec)
-{
-        struct hda_gen_spec *spec = codec->spec;
-
-        if (spec->hp_automute_hook)
-                spec->hp_automute_hook(codec, NULL);
-        else
-                snd_hda_gen_hp_automute(codec, NULL);
-}
-
+static void call_hp_automute(struct hda_codec *codec, struct hda_jack_tbl *jack);
 static int indep_hp_info(struct snd_kcontrol *kcontrol,
                          struct snd_ctl_elem_info *uinfo)
 {
@@ -2009,7 +2001,7 @@ static int indep_hp_put(struct snd_kcontrol *kcontrol,
                 else
                         *dacp = spec->alt_dac_nid;
 
-                update_hp_automute_hook(codec);
+                call_hp_automute(codec, NULL);
                 ret = 1;
         }
  unlock:
@@ -2305,7 +2297,7 @@ static void update_hp_mic(struct hda_codec *codec, int adc_mux, bool force)
                 else
                         val = PIN_HP;
                 set_pin_target(codec, pin, val, true);
-                update_hp_automute_hook(codec);
+                call_hp_automute(codec, NULL);
         }
 }
 
@@ -2714,7 +2706,7 @@ static int hp_mic_jack_mode_put(struct snd_kcontrol *kcontrol,
                         val = snd_hda_get_default_vref(codec, nid);
         }
         snd_hda_set_pin_ctl_cache(codec, nid, val);
-        update_hp_automute_hook(codec);
+        call_hp_automute(codec, NULL);
 
         return 1;
 }
@@ -3859,20 +3851,42 @@ void snd_hda_gen_mic_autoswitch(struct hda_codec *codec, struct hda_jack_tbl *ja
 }
 EXPORT_SYMBOL_HDA(snd_hda_gen_mic_autoswitch);
 
-/* update jack retasking */
-static void update_automute_all(struct hda_codec *codec)
+/* call appropriate hooks */
+static void call_hp_automute(struct hda_codec *codec, struct hda_jack_tbl *jack)
 {
         struct hda_gen_spec *spec = codec->spec;
+        if (spec->hp_automute_hook)
+                spec->hp_automute_hook(codec, jack);
+        else
+                snd_hda_gen_hp_automute(codec, jack);
+}
 
-        update_hp_automute_hook(codec);
+static void call_line_automute(struct hda_codec *codec,
+                               struct hda_jack_tbl *jack)
+{
+        struct hda_gen_spec *spec = codec->spec;
         if (spec->line_automute_hook)
-                spec->line_automute_hook(codec, NULL);
+                spec->line_automute_hook(codec, jack);
         else
-                snd_hda_gen_line_automute(codec, NULL);
+                snd_hda_gen_line_automute(codec, jack);
+}
+
+static void call_mic_autoswitch(struct hda_codec *codec,
+                                struct hda_jack_tbl *jack)
+{
+        struct hda_gen_spec *spec = codec->spec;
         if (spec->mic_autoswitch_hook)
-                spec->mic_autoswitch_hook(codec, NULL);
+                spec->mic_autoswitch_hook(codec, jack);
         else
-                snd_hda_gen_mic_autoswitch(codec, NULL);
+                snd_hda_gen_mic_autoswitch(codec, jack);
+}
+
+/* update jack retasking */
+static void update_automute_all(struct hda_codec *codec)
+{
+        call_hp_automute(codec, NULL);
+        call_line_automute(codec, NULL);
+        call_mic_autoswitch(codec, NULL);
 }
 
 /*
@@ -4009,9 +4023,7 @@ static int check_auto_mute_availability(struct hda_codec *codec)
                 snd_printdd("hda-codec: Enable HP auto-muting on NID 0x%x\n",
                             nid);
                 snd_hda_jack_detect_enable_callback(codec, nid, HDA_GEN_HP_EVENT,
-                                                    spec->hp_automute_hook ?
-                                                    spec->hp_automute_hook :
-                                                    snd_hda_gen_hp_automute);
+                                                    call_hp_automute);
                 spec->detect_hp = 1;
         }
 
@@ -4024,9 +4036,7 @@ static int check_auto_mute_availability(struct hda_codec *codec)
                                 snd_printdd("hda-codec: Enable Line-Out auto-muting on NID 0x%x\n", nid);
                                 snd_hda_jack_detect_enable_callback(codec, nid,
                                                                     HDA_GEN_FRONT_EVENT,
-                                                                    spec->line_automute_hook ?
-                                                                    spec->line_automute_hook :
-                                                                    snd_hda_gen_line_automute);
+                                                                    call_line_automute);
                                 spec->detect_lo = 1;
                         }
                 spec->automute_lo_possible = spec->detect_hp;
@@ -4068,9 +4078,7 @@ static bool auto_mic_check_imux(struct hda_codec *codec)
                 snd_hda_jack_detect_enable_callback(codec,
                                                     spec->am_entry[i].pin,
                                                     HDA_GEN_MIC_EVENT,
-                                                    spec->mic_autoswitch_hook ?
-                                                    spec->mic_autoswitch_hook :
-                                                    snd_hda_gen_mic_autoswitch);
+                                                    call_mic_autoswitch);
         return true;
 }
 
diff --git a/sound/pci/hda/hda_generic.h b/sound/pci/hda/hda_generic.h
index 54e665160379..76200314ee95 100644
--- a/sound/pci/hda/hda_generic.h
+++ b/sound/pci/hda/hda_generic.h
@@ -222,6 +222,7 @@ struct hda_gen_spec {
         unsigned int multi_cap_vol:1; /* allow multiple capture xxx volumes */
         unsigned int inv_dmic_split:1; /* inverted dmic w/a for conexant */
         unsigned int own_eapd_ctl:1; /* set EAPD by own function */
+        unsigned int keep_eapd_on:1; /* don't turn off EAPD automatically */
         unsigned int vmaster_mute_enum:1; /* add vmaster mute mode enum */
         unsigned int indep_hp:1; /* independent HP supported */
         unsigned int prefer_hp_amp:1; /* enable HP amp for speaker if any */
diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index 59d2e91a9ab6..02e22b4458d2 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -3493,6 +3493,8 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
         SND_PCI_QUIRK(0x1028, 0x05f4, "Dell", ALC269_FIXUP_DELL1_MIC_NO_PRESENCE),
         SND_PCI_QUIRK(0x1028, 0x05f5, "Dell", ALC269_FIXUP_DELL1_MIC_NO_PRESENCE),
         SND_PCI_QUIRK(0x1028, 0x05f6, "Dell", ALC269_FIXUP_DELL1_MIC_NO_PRESENCE),
+        SND_PCI_QUIRK(0x1028, 0x05f8, "Dell", ALC269_FIXUP_DELL1_MIC_NO_PRESENCE),
+        SND_PCI_QUIRK(0x1028, 0x0609, "Dell", ALC269_FIXUP_DELL1_MIC_NO_PRESENCE),
         SND_PCI_QUIRK(0x103c, 0x1586, "HP", ALC269_FIXUP_HP_MUTE_LED_MIC2),
         SND_PCI_QUIRK(0x103c, 0x18e6, "HP", ALC269_FIXUP_HP_GPIO_LED),
         SND_PCI_QUIRK(0x103c, 0x1973, "HP Pavilion", ALC269_FIXUP_HP_MUTE_LED_MIC1),
@@ -3530,6 +3532,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
         SND_PCI_QUIRK(0x17aa, 0x21fa, "Thinkpad X230", ALC269_FIXUP_LENOVO_DOCK),
         SND_PCI_QUIRK(0x17aa, 0x21f3, "Thinkpad T430", ALC269_FIXUP_LENOVO_DOCK),
         SND_PCI_QUIRK(0x17aa, 0x21fb, "Thinkpad T430s", ALC269_FIXUP_LENOVO_DOCK),
+        SND_PCI_QUIRK(0x17aa, 0x2208, "Thinkpad T431s", ALC269_FIXUP_LENOVO_DOCK),
         SND_PCI_QUIRK(0x17aa, 0x2203, "Thinkpad X230 Tablet", ALC269_FIXUP_LENOVO_DOCK),
         SND_PCI_QUIRK(0x17aa, 0x3bf8, "Quanta FL1", ALC269_FIXUP_PCM_44K),
         SND_PCI_QUIRK(0x17aa, 0x9e54, "LENOVO NB", ALC269_FIXUP_LENOVO_EAPD),
diff --git a/sound/pci/hda/patch_via.c b/sound/pci/hda/patch_via.c
index e0dadcf2030d..e5245544eb52 100644
--- a/sound/pci/hda/patch_via.c
+++ b/sound/pci/hda/patch_via.c
@@ -136,6 +136,7 @@ static struct via_spec *via_new_spec(struct hda_codec *codec)
                 spec->codec_type = VT1708S;
         spec->no_pin_power_ctl = 1;
         spec->gen.indep_hp = 1;
+        spec->gen.keep_eapd_on = 1;
         spec->gen.pcm_playback_hook = via_playback_pcm_hook;
         return spec;
 }
@@ -231,9 +232,14 @@ static void vt1708_update_hp_work(struct hda_codec *codec)
 
 static void set_widgets_power_state(struct hda_codec *codec)
 {
+#if 0 /* FIXME: the assumed connections don't match always with the
+       * actual routes by the generic parser, so better to disable
+       * the control for safety.
+       */
         struct via_spec *spec = codec->spec;
         if (spec->set_widgets_power_state)
                 spec->set_widgets_power_state(codec);
+#endif
 }
 
 static void update_power_state(struct hda_codec *codec, hda_nid_t nid,
@@ -478,7 +484,9 @@ static int via_suspend(struct hda_codec *codec)
                 /* Fix pop noise on headphones */
                 int i;
                 for (i = 0; i < spec->gen.autocfg.hp_outs; i++)
-                        snd_hda_set_pin_ctl(codec, spec->gen.autocfg.hp_pins[i], 0);
+                        snd_hda_codec_write(codec, spec->gen.autocfg.hp_pins[i],
+                                            0, AC_VERB_SET_PIN_WIDGET_CONTROL,
+                                            0x00);
         }
 
         return 0;
diff --git a/sound/pci/sis7019.c b/sound/pci/sis7019.c
index d59abe1682c5..748e82d4d257 100644
--- a/sound/pci/sis7019.c
+++ b/sound/pci/sis7019.c
@@ -1341,7 +1341,8 @@ static int sis_chip_create(struct snd_card *card,
         if (rc)
                 goto error_out;
 
-        if (pci_set_dma_mask(pci, DMA_BIT_MASK(30)) < 0) {
+        rc = pci_set_dma_mask(pci, DMA_BIT_MASK(30));
+        if (rc < 0) {
                 dev_err(&pci->dev, "architecture does not support 30-bit PCI busmaster DMA");
                 goto error_out_enabled;
         }
diff --git a/sound/soc/codecs/cs42l52.c b/sound/soc/codecs/cs42l52.c
index 0f6f481cec09..987f728718c5 100644
--- a/sound/soc/codecs/cs42l52.c
+++ b/sound/soc/codecs/cs42l52.c
@@ -86,7 +86,7 @@ static const struct reg_default cs42l52_reg_defaults[] = {
         { CS42L52_BEEP_VOL, 0x00 },     /* r1D Beep Volume off Time */
         { CS42L52_BEEP_TONE_CTL, 0x00 },        /* r1E Beep Tone Cfg. */
         { CS42L52_TONE_CTL, 0x00 },     /* r1F Tone Ctl */
-        { CS42L52_MASTERA_VOL, 0x88 },  /* r20 Master A Volume */
+        { CS42L52_MASTERA_VOL, 0x00 },  /* r20 Master A Volume */
         { CS42L52_MASTERB_VOL, 0x00 },  /* r21 Master B Volume */
         { CS42L52_HPA_VOL, 0x00 },      /* r22 Headphone A Volume */
         { CS42L52_HPB_VOL, 0x00 },      /* r23 Headphone B Volume */
@@ -193,6 +193,8 @@ static DECLARE_TLV_DB_SCALE(mic_tlv, 1600, 100, 0);
 
 static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
 
+static DECLARE_TLV_DB_SCALE(mix_tlv, -50, 50, 0);
+
 static const unsigned int limiter_tlv[] = {
         TLV_DB_RANGE_HEAD(2),
         0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
@@ -225,7 +227,7 @@ static const char * const mic_bias_level_text[] = {
 };
 
 static const struct soc_enum mic_bias_level_enum =
-        SOC_ENUM_SINGLE(CS42L52_IFACE_CTL1, 0,
+        SOC_ENUM_SINGLE(CS42L52_IFACE_CTL2, 0,
                         ARRAY_SIZE(mic_bias_level_text), mic_bias_level_text);
 
 static const char * const cs42l52_mic_text[] = { "Single", "Differential" };
@@ -260,7 +262,7 @@ static const char * const hp_gain_num_text[] = {
 };
 
 static const struct soc_enum hp_gain_enum =
-        SOC_ENUM_SINGLE(CS42L52_PB_CTL1, 4,
+        SOC_ENUM_SINGLE(CS42L52_PB_CTL1, 5,
                 ARRAY_SIZE(hp_gain_num_text), hp_gain_num_text);
 
 static const char * const beep_pitch_text[] = {
@@ -413,7 +415,7 @@ static const struct snd_kcontrol_new cs42l52_snd_controls[] = {
         SOC_ENUM("Headphone Analog Gain", hp_gain_enum),
 
         SOC_DOUBLE_R_SX_TLV("Speaker Volume", CS42L52_SPKA_VOL,
-                              CS42L52_SPKB_VOL, 7, 0x1, 0xff, hl_tlv),
+                              CS42L52_SPKB_VOL, 0, 0x1, 0xff, hl_tlv),
 
         SOC_DOUBLE_R_SX_TLV("Bypass Volume", CS42L52_PASSTHRUA_VOL,
                               CS42L52_PASSTHRUB_VOL, 6, 0x18, 0x90, pga_tlv),
@@ -441,7 +443,7 @@ static const struct snd_kcontrol_new cs42l52_snd_controls[] = {
 
         SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume",
                             CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL,
-                                6, 0x7f, 0x19, hl_tlv),
+                                0, 0x7f, 0x19, mix_tlv),
         SOC_DOUBLE_R("PCM Mixer Switch",
                      CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL, 7, 1, 1),
 
diff --git a/sound/soc/codecs/cs42l52.h b/sound/soc/codecs/cs42l52.h
index 60985c059071..4277012c4719 100644
--- a/sound/soc/codecs/cs42l52.h
+++ b/sound/soc/codecs/cs42l52.h
@@ -157,7 +157,7 @@
 #define CS42L52_PB_CTL1_INV_PCMA                (1 << 2)
 #define CS42L52_PB_CTL1_MSTB_MUTE               (1 << 1)
 #define CS42L52_PB_CTL1_MSTA_MUTE               (1 << 0)
-#define CS42L52_PB_CTL1_MUTE_MASK               0xFFFD
+#define CS42L52_PB_CTL1_MUTE_MASK               0x03
 #define CS42L52_PB_CTL1_MUTE                    3
 #define CS42L52_PB_CTL1_UNMUTE                  0
 
diff --git a/sound/soc/codecs/max98090.c b/sound/soc/codecs/max98090.c
index ce0d36412c97..8d14a76c7249 100644
--- a/sound/soc/codecs/max98090.c
+++ b/sound/soc/codecs/max98090.c
@@ -2233,7 +2233,7 @@ static int max98090_probe(struct snd_soc_codec *codec)
         dev_dbg(codec->dev, "irq = %d\n", max98090->irq);
 
         ret = request_threaded_irq(max98090->irq, NULL,
-                max98090_interrupt, IRQF_TRIGGER_FALLING,
+                max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
                 "max98090_interrupt", codec);
         if (ret < 0) {
                 dev_err(codec->dev, "request_irq failed: %d\n",
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index 65d09d60b7c6..1514bf845e4b 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -187,14 +187,14 @@ static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
 
                         break;
                 }
-
-                if (found)
-                        snd_soc_dapm_sync(widget->dapm);
         }
 
-        ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
-
         mutex_unlock(&widget->codec->mutex);
+
+        if (found)
+                snd_soc_dapm_sync(widget->dapm);
+
+        ret = snd_soc_update_bits_locked(widget->codec, reg, val_mask, val);
         return ret;
 }
 
diff --git a/sound/soc/codecs/wm5102.c b/sound/soc/codecs/wm5102.c
index e895d3939eef..100fdadda56a 100644
--- a/sound/soc/codecs/wm5102.c
+++ b/sound/soc/codecs/wm5102.c
@@ -1120,7 +1120,8 @@ SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 0,
 ARIZONA_DSP_WIDGETS(DSP1, "DSP1"),
 
 SND_SOC_DAPM_VALUE_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1,
-                       ARIZONA_AEC_LOOPBACK_ENA, 0, &wm5102_aec_loopback_mux),
+                       ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0,
+                       &wm5102_aec_loopback_mux),
 
 SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM,
                    ARIZONA_OUT1L_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev,
diff --git a/sound/soc/codecs/wm5110.c b/sound/soc/codecs/wm5110.c
index 731884e04776..88ad7db52dde 100644
--- a/sound/soc/codecs/wm5110.c
+++ b/sound/soc/codecs/wm5110.c
@@ -190,7 +190,7 @@ ARIZONA_MIXER_CONTROLS("DSP2R", ARIZONA_DSP2RMIX_INPUT_1_SOURCE),
 ARIZONA_MIXER_CONTROLS("DSP3L", ARIZONA_DSP3LMIX_INPUT_1_SOURCE),
 ARIZONA_MIXER_CONTROLS("DSP3R", ARIZONA_DSP3RMIX_INPUT_1_SOURCE),
 ARIZONA_MIXER_CONTROLS("DSP4L", ARIZONA_DSP4LMIX_INPUT_1_SOURCE),
-ARIZONA_MIXER_CONTROLS("DSP5R", ARIZONA_DSP4RMIX_INPUT_1_SOURCE),
+ARIZONA_MIXER_CONTROLS("DSP4R", ARIZONA_DSP4RMIX_INPUT_1_SOURCE),
 
 ARIZONA_MIXER_CONTROLS("Mic", ARIZONA_MICMIX_INPUT_1_SOURCE),
 ARIZONA_MIXER_CONTROLS("Noise", ARIZONA_NOISEMIX_INPUT_1_SOURCE),
@@ -503,7 +503,8 @@ SND_SOC_DAPM_PGA("ASRC2R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2R_ENA_SHIFT, 0,
                  NULL, 0),
 
 SND_SOC_DAPM_VALUE_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1,
-                       ARIZONA_AEC_LOOPBACK_ENA, 0, &wm5110_aec_loopback_mux),
+                       ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0,
+                       &wm5110_aec_loopback_mux),
 
 SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0,
                      ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX1_ENA_SHIFT, 0),
@@ -976,6 +977,8 @@ static int wm5110_codec_probe(struct snd_soc_codec *codec)
         if (ret != 0)
                 return ret;
 
+        arizona_init_spk(codec);
+
         snd_soc_dapm_disable_pin(&codec->dapm, "HAPTICS");
 
         priv->core.arizona->dapm = &codec->dapm;
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index 1eb152cb1097..29e95f93d482 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -383,6 +383,8 @@ static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
         int drc = wm8994_get_drc(kcontrol->id.name);
 
+        if (drc < 0)
+                return drc;
         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 
         return 0;
@@ -488,6 +490,9 @@ static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 
+        if (block < 0)
+                return block;
+
         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 
         return 0;
@@ -1031,7 +1036,7 @@ static int aif1clk_ev(struct snd_soc_dapm_widget *w,
 {
         struct snd_soc_codec *codec = w->codec;
         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
-        struct wm8994 *control = codec->control_data;
+        struct wm8994 *control = wm8994->wm8994;
         int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
         int i;
         int dac;
@@ -3831,8 +3836,14 @@ static irqreturn_t wm8958_mic_irq(int irq, void *data)
                                 ret);
                 } else if (!(ret & WM1811_JACKDET_LVL)) {
                         dev_dbg(codec->dev, "Ignoring removed jack\n");
-                        return IRQ_HANDLED;
+                        goto out;
                 }
+        } else if (!(reg & WM8958_MICD_STS)) {
+                snd_soc_jack_report(wm8994->micdet[0].jack, 0,
+                                    SND_JACK_MECHANICAL | SND_JACK_HEADSET |
+                                    wm8994->btn_mask);
+                wm8994->mic_detecting = true;
+                goto out;
         }
 
         if (wm8994->mic_detecting)
diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
index 484b22c5df5d..fd7c45b9ed5a 100644
--- a/sound/soc/davinci/davinci-evm.c
+++ b/sound/soc/davinci/davinci-evm.c
@@ -14,6 +14,7 @@
 #include <linux/timer.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
+#include <linux/platform_data/edma.h>
 #include <linux/i2c.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c
index 56ecfc72f2e9..81490febac6d 100644
--- a/sound/soc/davinci/davinci-mcasp.c
+++ b/sound/soc/davinci/davinci-mcasp.c
@@ -631,7 +631,8 @@ static int davinci_config_channel_size(struct davinci_audio_dev *dev,
                                        int word_length)
 {
         u32 fmt;
-        u32 rotate = (word_length / 4) & 0x7;
+        u32 tx_rotate = (word_length / 4) & 0x7;
+        u32 rx_rotate = (32 - word_length) / 4;
         u32 mask = (1ULL << word_length) - 1;
 
         /*
@@ -655,9 +656,9 @@ static int davinci_config_channel_size(struct davinci_audio_dev *dev,
                 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
                                 TXSSZ(fmt), TXSSZ(0x0F));
                 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
-                                TXROT(rotate), TXROT(7));
+                                TXROT(tx_rotate), TXROT(7));
                 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
-                                RXROT(rotate), RXROT(7));
+                                RXROT(rx_rotate), RXROT(7));
                 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG,
                                 mask);
         }
diff --git a/sound/soc/davinci/davinci-pcm.c b/sound/soc/davinci/davinci-pcm.c
index b2f27c2e5fdc..8460edce1c3b 100644
--- a/sound/soc/davinci/davinci-pcm.c
+++ b/sound/soc/davinci/davinci-pcm.c
@@ -17,6 +17,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/kernel.h>
 #include <linux/genalloc.h>
+#include <linux/platform_data/edma.h>
 
 #include <sound/core.h>
 #include <sound/pcm.h>
diff --git a/sound/soc/davinci/davinci-pcm.h b/sound/soc/davinci/davinci-pcm.h
index b6ef7039dd09..fbb710c76c08 100644
--- a/sound/soc/davinci/davinci-pcm.h
+++ b/sound/soc/davinci/davinci-pcm.h
@@ -14,7 +14,7 @@
 
 #include <linux/genalloc.h>
 #include <linux/platform_data/davinci_asp.h>
-#include <mach/edma.h>
+#include <linux/platform_data/edma.h>
 
 struct davinci_pcm_dma_params {
         int channel;                    /* sync dma channel ID */
diff --git a/sound/soc/soc-compress.c b/sound/soc/soc-compress.c
index 3853f7eb3f28..06a8000aa07b 100644
--- a/sound/soc/soc-compress.c
+++ b/sound/soc/soc-compress.c
@@ -220,8 +220,12 @@ static int soc_compr_set_params(struct snd_compr_stream *cstream,
                         goto err;
         }
 
-        snd_soc_dapm_stream_event(rtd, SNDRV_PCM_STREAM_PLAYBACK,
-                                SND_SOC_DAPM_STREAM_START);
+        if (cstream->direction == SND_COMPRESS_PLAYBACK)
+                snd_soc_dapm_stream_event(rtd, SNDRV_PCM_STREAM_PLAYBACK,
+                                        SND_SOC_DAPM_STREAM_START);
+        else
+                snd_soc_dapm_stream_event(rtd, SNDRV_PCM_STREAM_CAPTURE,
+                                        SND_SOC_DAPM_STREAM_START);
 
         /* cancel any delayed stream shutdown that is pending */
         rtd->pop_wait = 0;
diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c
index a80c883bb8be..c7051c457b75 100644
--- a/sound/soc/soc-dapm.c
+++ b/sound/soc/soc-dapm.c
@@ -55,7 +55,8 @@ static int dapm_up_seq[] = {
         [snd_soc_dapm_clock_supply] = 1,
         [snd_soc_dapm_micbias] = 2,
         [snd_soc_dapm_dai_link] = 2,
-        [snd_soc_dapm_dai] = 3,
+        [snd_soc_dapm_dai_in] = 3,
+        [snd_soc_dapm_dai_out] = 3,
         [snd_soc_dapm_aif_in] = 3,
         [snd_soc_dapm_aif_out] = 3,
         [snd_soc_dapm_mic] = 4,
@@ -92,7 +93,8 @@ static int dapm_down_seq[] = {
         [snd_soc_dapm_value_mux] = 9,
         [snd_soc_dapm_aif_in] = 10,
         [snd_soc_dapm_aif_out] = 10,
-        [snd_soc_dapm_dai] = 10,
+        [snd_soc_dapm_dai_in] = 10,
+        [snd_soc_dapm_dai_out] = 10,
         [snd_soc_dapm_dai_link] = 11,
         [snd_soc_dapm_clock_supply] = 12,
         [snd_soc_dapm_regulator_supply] = 12,
@@ -419,7 +421,8 @@ static void dapm_set_path_status(struct snd_soc_dapm_widget *w,
         case snd_soc_dapm_clock_supply:
         case snd_soc_dapm_aif_in:
         case snd_soc_dapm_aif_out:
-        case snd_soc_dapm_dai:
+        case snd_soc_dapm_dai_in:
+        case snd_soc_dapm_dai_out:
         case snd_soc_dapm_hp:
         case snd_soc_dapm_mic:
         case snd_soc_dapm_spk:
@@ -820,7 +823,7 @@ static int is_connected_output_ep(struct snd_soc_dapm_widget *widget,
         switch (widget->id) {
         case snd_soc_dapm_adc:
         case snd_soc_dapm_aif_out:
-        case snd_soc_dapm_dai:
+        case snd_soc_dapm_dai_out:
                 if (widget->active) {
                         widget->outputs = snd_soc_dapm_suspend_check(widget);
                         return widget->outputs;
@@ -916,7 +919,7 @@ static int is_connected_input_ep(struct snd_soc_dapm_widget *widget,
         switch (widget->id) {
         case snd_soc_dapm_dac:
         case snd_soc_dapm_aif_in:
-        case snd_soc_dapm_dai:
+        case snd_soc_dapm_dai_in:
                 if (widget->active) {
                         widget->inputs = snd_soc_dapm_suspend_check(widget);
                         return widget->inputs;
@@ -1135,16 +1138,6 @@ static int dapm_generic_check_power(struct snd_soc_dapm_widget *w)
         return out != 0 && in != 0;
 }
 
-static int dapm_dai_check_power(struct snd_soc_dapm_widget *w)
-{
-        DAPM_UPDATE_STAT(w, power_checks);
-
-        if (w->active)
-                return w->active;
-
-        return dapm_generic_check_power(w);
-}
-
 /* Check to see if an ADC has power */
 static int dapm_adc_check_power(struct snd_soc_dapm_widget *w)
 {
@@ -2318,7 +2311,8 @@ static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm,
         case snd_soc_dapm_clock_supply:
         case snd_soc_dapm_aif_in:
         case snd_soc_dapm_aif_out:
-        case snd_soc_dapm_dai:
+        case snd_soc_dapm_dai_in:
+        case snd_soc_dapm_dai_out:
         case snd_soc_dapm_dai_link:
                 list_add(&path->list, &dapm->card->paths);
                 list_add(&path->list_sink, &wsink->sources);
@@ -3129,10 +3123,12 @@ snd_soc_dapm_new_control(struct snd_soc_dapm_context *dapm,
                 break;
         case snd_soc_dapm_adc:
         case snd_soc_dapm_aif_out:
+        case snd_soc_dapm_dai_out:
                 w->power_check = dapm_adc_check_power;
                 break;
         case snd_soc_dapm_dac:
         case snd_soc_dapm_aif_in:
+        case snd_soc_dapm_dai_in:
                 w->power_check = dapm_dac_check_power;
                 break;
         case snd_soc_dapm_pga:
@@ -3152,9 +3148,6 @@ snd_soc_dapm_new_control(struct snd_soc_dapm_context *dapm,
         case snd_soc_dapm_clock_supply:
                 w->power_check = dapm_supply_check_power;
                 break;
-        case snd_soc_dapm_dai:
-                w->power_check = dapm_dai_check_power;
-                break;
         default:
                 w->power_check = dapm_always_on_check_power;
                 break;
@@ -3375,7 +3368,7 @@ int snd_soc_dapm_new_dai_widgets(struct snd_soc_dapm_context *dapm,
         template.reg = SND_SOC_NOPM;
 
         if (dai->driver->playback.stream_name) {
-                template.id = snd_soc_dapm_dai;
+                template.id = snd_soc_dapm_dai_in;
                 template.name = dai->driver->playback.stream_name;
                 template.sname = dai->driver->playback.stream_name;
 
@@ -3393,7 +3386,7 @@ int snd_soc_dapm_new_dai_widgets(struct snd_soc_dapm_context *dapm,
         }
 
         if (dai->driver->capture.stream_name) {
-                template.id = snd_soc_dapm_dai;
+                template.id = snd_soc_dapm_dai_out;
                 template.name = dai->driver->capture.stream_name;
                 template.sname = dai->driver->capture.stream_name;
 
@@ -3423,8 +3416,13 @@ int snd_soc_dapm_link_dai_widgets(struct snd_soc_card *card)
 
         /* For each DAI widget... */
         list_for_each_entry(dai_w, &card->widgets, list) {
-                if (dai_w->id != snd_soc_dapm_dai)
+                switch (dai_w->id) {
+                case snd_soc_dapm_dai_in:
+                case snd_soc_dapm_dai_out:
+                        break;
+                default:
                         continue;
+                }
 
                 dai = dai_w->priv;
 
@@ -3433,8 +3431,13 @@ int snd_soc_dapm_link_dai_widgets(struct snd_soc_card *card)
                         if (w->dapm != dai_w->dapm)
                                 continue;
 
-                        if (w->id == snd_soc_dapm_dai)
+                        switch (w->id) {
+                        case snd_soc_dapm_dai_in:
+                        case snd_soc_dapm_dai_out:
                                 continue;
+                        default:
+                                break;
+                        }
 
                         if (!w->sname)
                                 continue;
diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c
index 73bb8eefa491..ccb6be4d658d 100644
--- a/sound/soc/soc-pcm.c
+++ b/sound/soc/soc-pcm.c
@@ -928,8 +928,13 @@ static int dpcm_add_paths(struct snd_soc_pcm_runtime *fe, int stream,
         /* Create any new FE <--> BE connections */
         for (i = 0; i < list->num_widgets; i++) {
 
-                if (list->widgets[i]->id != snd_soc_dapm_dai)
+                switch (list->widgets[i]->id) {
+                case snd_soc_dapm_dai_in:
+                case snd_soc_dapm_dai_out:
+                        break;
+                default:
                         continue;
+                }
 
                 /* is there a valid BE rtd for this widget */
                 be = dpcm_get_be(card, list->widgets[i], stream);
@@ -2011,9 +2016,11 @@ int soc_new_pcm(struct snd_soc_pcm_runtime *rtd, int num)
                 if (cpu_dai->driver->capture.channels_min)
                         capture = 1;
         } else {
-                if (codec_dai->driver->playback.channels_min)
+                if (codec_dai->driver->playback.channels_min &&
+                    cpu_dai->driver->playback.channels_min)
                         playback = 1;
-                if (codec_dai->driver->capture.channels_min)
+                if (codec_dai->driver->capture.channels_min &&
+                    cpu_dai->driver->capture.channels_min)
                         capture = 1;
         }
 
diff --git a/sound/usb/6fire/firmware.c b/sound/usb/6fire/firmware.c
index a1d9b0792a1e..b9defcdeb7ef 100644
--- a/sound/usb/6fire/firmware.c
+++ b/sound/usb/6fire/firmware.c
@@ -42,8 +42,8 @@ static const u8 ep_w_max_packet_size[] = {
         0x94, 0x01, 0x5c, 0x02  /* alt 3: 404 EP2 and 604 EP6 (25 fpp) */
 };
 
-static const u8 known_fw_versions[][4] = {
-        { 0x03, 0x01, 0x0b, 0x00 }
+static const u8 known_fw_versions[][2] = {
+        { 0x03, 0x01 }
 };
 
 struct ihex_record {
@@ -343,7 +343,7 @@ static int usb6fire_fw_check(u8 *version)
         int i;
 
         for (i = 0; i < ARRAY_SIZE(known_fw_versions); i++)
-                if (!memcmp(version, known_fw_versions + i, 4))
+                if (!memcmp(version, known_fw_versions + i, 2))
                         return 0;
 
         snd_printk(KERN_ERR PREFIX "invalid fimware version in device: %*ph. "
diff --git a/sound/usb/mixer.c b/sound/usb/mixer.c
index ca4739c3f650..e5c7f9f20fdd 100644
--- a/sound/usb/mixer.c
+++ b/sound/usb/mixer.c
@@ -886,6 +886,7 @@ static void volume_control_quirks(struct usb_mixer_elem_info *cval,
         case USB_ID(0x046d, 0x0808):
         case USB_ID(0x046d, 0x0809):
         case USB_ID(0x046d, 0x081d): /* HD Webcam c510 */
+        case USB_ID(0x046d, 0x0825): /* HD Webcam c270 */
         case USB_ID(0x046d, 0x0991):
         /* Most audio usb devices lie about volume resolution.
          * Most Logitech webcams have res = 384.
diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h
index 7f1722f82c89..8b75bcf136f6 100644
--- a/sound/usb/quirks-table.h
+++ b/sound/usb/quirks-table.h
@@ -215,7 +215,13 @@
         .bInterfaceSubClass = USB_SUBCLASS_AUDIOCONTROL
 },
 {
-        USB_DEVICE(0x046d, 0x0990),
+        .match_flags = USB_DEVICE_ID_MATCH_DEVICE |
+                       USB_DEVICE_ID_MATCH_INT_CLASS |
+                       USB_DEVICE_ID_MATCH_INT_SUBCLASS,
+        .idVendor = 0x046d,
+        .idProduct = 0x0990,
+        .bInterfaceClass = USB_CLASS_AUDIO,
+        .bInterfaceSubClass = USB_SUBCLASS_AUDIOCONTROL,
         .driver_info = (unsigned long) & (const struct snd_usb_audio_quirk) {
                 .vendor_name = "Logitech, Inc.",
                 .product_name = "QuickCam Pro 9000",
@@ -1792,7 +1798,11 @@ YAMAHA_DEVICE(0x7010, "UB99"),
         USB_DEVICE_VENDOR_SPEC(0x0582, 0x0108),
         .driver_info = (unsigned long) & (const struct snd_usb_audio_quirk) {
                 .ifnum = 0,
-                .type = QUIRK_MIDI_STANDARD_INTERFACE
+                .type = QUIRK_MIDI_FIXED_ENDPOINT,
+                .data = & (const struct snd_usb_midi_endpoint_info) {
+                        .out_cables = 0x0007,
+                        .in_cables  = 0x0007
+                }
         }
 },
 {
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
index 9e9d34871195..fe702076ca46 100644
--- a/tools/power/x86/turbostat/turbostat.c
+++ b/tools/power/x86/turbostat/turbostat.c
@@ -2191,7 +2191,7 @@ int initialize_counters(int cpu_id)
 
 void allocate_output_buffer()
 {
-        output_buffer = calloc(1, (1 + topo.num_cpus) * 128);
+        output_buffer = calloc(1, (1 + topo.num_cpus) * 256);
         outp = output_buffer;
         if (outp == NULL) {
                 perror("calloc");