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-rw-r--r--Documentation/devicetree/bindings/clock/hi3670-clock.txt43
-rw-r--r--Documentation/devicetree/bindings/clock/ingenic,cgu.txt7
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,camcc.txt18
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc.txt3
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt17
-rw-r--r--arch/arm/mach-davinci/include/mach/clock.h21
-rw-r--r--drivers/clk/Kconfig1
-rw-r--r--drivers/clk/Makefile3
-rw-r--r--drivers/clk/at91/clk-pll.c3
-rw-r--r--drivers/clk/axs10x/pll_clock.c4
-rw-r--r--drivers/clk/bcm/clk-kona-setup.c22
-rw-r--r--drivers/clk/clk-asm9260.c4
-rw-r--r--drivers/clk/clk-bulk.c80
-rw-r--r--drivers/clk/clk-cdce925.c11
-rw-r--r--drivers/clk/clk-devres.c24
-rw-r--r--drivers/clk/clk-fixed-factor.c8
-rw-r--r--drivers/clk/clk-gpio.c8
-rw-r--r--drivers/clk/clk-hsdk-pll.c4
-rw-r--r--drivers/clk/clk-max77686.c27
-rw-r--r--drivers/clk/clk-nomadik.c4
-rw-r--r--drivers/clk/clk-npcm7xx.c2
-rw-r--r--drivers/clk/clk-palmas.c4
-rw-r--r--drivers/clk/clk-qoriq.c14
-rw-r--r--drivers/clk/clk-s2mps11.c28
-rw-r--r--drivers/clk/clk-scmi.c2
-rw-r--r--drivers/clk/clk-scpi.c6
-rw-r--r--drivers/clk/clk-si5351.c4
-rw-r--r--drivers/clk/clk-stm32f4.c2
-rw-r--r--drivers/clk/clk-stm32h7.c2
-rw-r--r--drivers/clk/clk-stm32mp1.c2
-rw-r--r--drivers/clk/clk-tango4.c10
-rw-r--r--drivers/clk/clk.c95
-rw-r--r--drivers/clk/davinci/psc.c18
-rw-r--r--drivers/clk/hisilicon/Kconfig7
-rw-r--r--drivers/clk/hisilicon/Makefile1
-rw-r--r--drivers/clk/hisilicon/clk-hi3670.c1016
-rw-r--r--drivers/clk/hisilicon/reset.c5
-rw-r--r--drivers/clk/ingenic/Kconfig47
-rw-r--r--drivers/clk/ingenic/Makefile9
-rw-r--r--drivers/clk/ingenic/jz4725b-cgu.c225
-rw-r--r--drivers/clk/keystone/Kconfig2
-rw-r--r--drivers/clk/keystone/gate.c7
-rw-r--r--drivers/clk/keystone/pll.c7
-rw-r--r--drivers/clk/mediatek/clk-mt2701.c5
-rw-r--r--drivers/clk/meson/axg-audio.c34
-rw-r--r--drivers/clk/meson/axg.c332
-rw-r--r--drivers/clk/meson/axg.h8
-rw-r--r--drivers/clk/meson/clk-pll.c156
-rw-r--r--drivers/clk/meson/clkc.h16
-rw-r--r--drivers/clk/meson/gxbb.c518
-rw-r--r--drivers/clk/meson/gxbb.h10
-rw-r--r--drivers/clk/meson/meson8b.c280
-rw-r--r--drivers/clk/meson/meson8b.h5
-rw-r--r--drivers/clk/mvebu/ap806-system-controller.c5
-rw-r--r--drivers/clk/mvebu/armada-370.c4
-rw-r--r--drivers/clk/mvebu/armada-375.c4
-rw-r--r--drivers/clk/mvebu/armada-37xx-periph.c58
-rw-r--r--drivers/clk/mvebu/armada-37xx-tbg.c8
-rw-r--r--drivers/clk/mvebu/armada-37xx-xtal.c4
-rw-r--r--drivers/clk/mvebu/armada-38x.c4
-rw-r--r--drivers/clk/mvebu/armada-39x.c4
-rw-r--r--drivers/clk/mvebu/armada-xp.c4
-rw-r--r--drivers/clk/mvebu/clk-corediv.c4
-rw-r--r--drivers/clk/mvebu/clk-cpu.c4
-rw-r--r--drivers/clk/mvebu/common.c4
-rw-r--r--drivers/clk/mvebu/common.h4
-rw-r--r--drivers/clk/mvebu/cp110-system-controller.c4
-rw-r--r--drivers/clk/mvebu/dove.c4
-rw-r--r--drivers/clk/mvebu/kirkwood.c4
-rw-r--r--drivers/clk/mvebu/mv98dx3236.c4
-rw-r--r--drivers/clk/mvebu/orion.c4
-rw-r--r--drivers/clk/qcom/Kconfig25
-rw-r--r--drivers/clk/qcom/Makefile3
-rw-r--r--drivers/clk/qcom/camcc-sdm845.c1745
-rw-r--r--drivers/clk/qcom/clk-alpha-pll.c1
-rw-r--r--drivers/clk/qcom/clk-branch.c2
-rw-r--r--drivers/clk/qcom/clk-rcg.h11
-rw-r--r--drivers/clk/qcom/clk-rcg2.c195
-rw-r--r--drivers/clk/qcom/gcc-msm8996.c152
-rw-r--r--drivers/clk/qcom/gcc-qcs404.c2744
-rw-r--r--drivers/clk/qcom/gcc-sdm660.c2480
-rw-r--r--drivers/clk/qcom/gcc-sdm845.c305
-rw-r--r--drivers/clk/renesas/Kconfig19
-rw-r--r--drivers/clk/renesas/Makefile3
-rw-r--r--drivers/clk/renesas/clk-div6.c17
-rw-r--r--drivers/clk/renesas/clk-emev2.c22
-rw-r--r--drivers/clk/renesas/clk-mstp.c13
-rw-r--r--drivers/clk/renesas/clk-r8a73a4.c9
-rw-r--r--drivers/clk/renesas/clk-r8a7740.c9
-rw-r--r--drivers/clk/renesas/clk-r8a7778.c9
-rw-r--r--drivers/clk/renesas/clk-r8a7779.c9
-rw-r--r--drivers/clk/renesas/clk-rcar-gen2.c9
-rw-r--r--drivers/clk/renesas/clk-rz.c9
-rw-r--r--drivers/clk/renesas/clk-sh73a0.c9
-rw-r--r--drivers/clk/renesas/r7s9210-cpg-mssr.c217
-rw-r--r--drivers/clk/renesas/r8a7743-cpg-mssr.c18
-rw-r--r--drivers/clk/renesas/r8a7745-cpg-mssr.c5
-rw-r--r--drivers/clk/renesas/r8a774a1-cpg-mssr.c323
-rw-r--r--drivers/clk/renesas/r8a774c0-cpg-mssr.c286
-rw-r--r--drivers/clk/renesas/r8a7790-cpg-mssr.c5
-rw-r--r--drivers/clk/renesas/r8a7791-cpg-mssr.c5
-rw-r--r--drivers/clk/renesas/r8a7792-cpg-mssr.c5
-rw-r--r--drivers/clk/renesas/r8a7794-cpg-mssr.c5
-rw-r--r--drivers/clk/renesas/r8a7795-cpg-mssr.c72
-rw-r--r--drivers/clk/renesas/r8a7796-cpg-mssr.c72
-rw-r--r--drivers/clk/renesas/r8a77965-cpg-mssr.c69
-rw-r--r--drivers/clk/renesas/r8a77970-cpg-mssr.c81
-rw-r--r--drivers/clk/renesas/r8a77980-cpg-mssr.c32
-rw-r--r--drivers/clk/renesas/r8a77990-cpg-mssr.c17
-rw-r--r--drivers/clk/renesas/r8a77995-cpg-mssr.c17
-rw-r--r--drivers/clk/renesas/r9a06g032-clocks.c3
-rw-r--r--drivers/clk/renesas/rcar-gen2-cpg.c5
-rw-r--r--drivers/clk/renesas/rcar-gen2-cpg.h7
-rw-r--r--drivers/clk/renesas/rcar-gen3-cpg.c45
-rw-r--r--drivers/clk/renesas/rcar-gen3-cpg.h33
-rw-r--r--drivers/clk/renesas/rcar-usb2-clock-sel.c5
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.c205
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.h38
-rw-r--r--drivers/clk/samsung/clk-cpu.c6
-rw-r--r--drivers/clk/samsung/clk-cpu.h2
-rw-r--r--drivers/clk/samsung/clk-exynos-audss.c1
-rw-r--r--drivers/clk/samsung/clk-exynos3250.c1
-rw-r--r--drivers/clk/samsung/clk-exynos4.c226
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c42
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c76
-rw-r--r--drivers/clk/samsung/clk-exynos5433.c33
-rw-r--r--drivers/clk/samsung/clk-s3c2410.c43
-rw-r--r--drivers/clk/samsung/clk-s3c2412.c43
-rw-r--r--drivers/clk/samsung/clk-s3c2443.c43
-rw-r--r--drivers/clk/samsung/clk-s3c64xx.c66
-rw-r--r--drivers/clk/samsung/clk-s5pv210.c41
-rw-r--r--drivers/clk/samsung/clk.c23
-rw-r--r--drivers/clk/samsung/clk.h18
-rw-r--r--drivers/clk/st/clkgen-fsyn.c2
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun50i-a64.c48
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun50i-a64.h4
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun50i-h6.c53
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-a83t.c2
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-h3.c25
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-r40.c52
-rw-r--r--drivers/clk/sunxi-ng/ccu_nkmp.c7
-rw-r--r--drivers/clk/sunxi-ng/ccu_nkmp.h1
-rw-r--r--drivers/clk/sunxi-ng/ccu_nm.c7
-rw-r--r--drivers/clk/sunxi-ng/ccu_nm.h30
-rw-r--r--drivers/clk/sunxi/clk-mod0.c6
-rw-r--r--drivers/clk/sunxi/clk-sun9i-core.c20
-rw-r--r--drivers/clk/sunxi/clk-sunxi.c4
-rw-r--r--drivers/clk/ti/Makefile9
-rw-r--r--drivers/clk/ti/apll.c18
-rw-r--r--drivers/clk/ti/clk-33xx-compat.c218
-rw-r--r--drivers/clk/ti/clk-33xx.c232
-rw-r--r--drivers/clk/ti/clk-43xx-compat.c225
-rw-r--r--drivers/clk/ti/clk-43xx.c249
-rw-r--r--drivers/clk/ti/clk-7xx-compat.c823
-rw-r--r--drivers/clk/ti/clk-7xx.c590
-rw-r--r--drivers/clk/ti/clk-dra7-atl.c4
-rw-r--r--drivers/clk/ti/clk.c28
-rw-r--r--drivers/clk/ti/clkctrl.c101
-rw-r--r--drivers/clk/ti/clock.h11
-rw-r--r--drivers/clk/ti/composite.c14
-rw-r--r--drivers/clk/ti/divider.c40
-rw-r--r--drivers/clk/ti/dpll.c18
-rw-r--r--drivers/clk/ti/dpll3xxx.c124
-rw-r--r--drivers/clk/ti/fapll.c8
-rw-r--r--drivers/clk/ti/fixed-factor.c4
-rw-r--r--drivers/clk/ti/gate.c5
-rw-r--r--drivers/clk/ti/interface.c2
-rw-r--r--drivers/clk/ti/mux.c33
-rw-r--r--drivers/clk/zynq/clkc.c4
-rw-r--r--include/dt-bindings/clock/am3.h119
-rw-r--r--include/dt-bindings/clock/am4.h132
-rw-r--r--include/dt-bindings/clock/dra7.h326
-rw-r--r--include/dt-bindings/clock/exynos3250.h5
-rw-r--r--include/dt-bindings/clock/exynos4.h37
-rw-r--r--include/dt-bindings/clock/exynos5250.h7
-rw-r--r--include/dt-bindings/clock/exynos5260-clk.h7
-rw-r--r--include/dt-bindings/clock/exynos5410.h7
-rw-r--r--include/dt-bindings/clock/exynos5420.h7
-rw-r--r--include/dt-bindings/clock/exynos5433.h5
-rw-r--r--include/dt-bindings/clock/exynos7-clk.h7
-rw-r--r--include/dt-bindings/clock/hi3670-clock.h348
-rw-r--r--include/dt-bindings/clock/jz4725b-cgu.h35
-rw-r--r--include/dt-bindings/clock/maxim,max77686.h5
-rw-r--r--include/dt-bindings/clock/maxim,max77802.h5
-rw-r--r--include/dt-bindings/clock/qcom,camcc-sdm845.h116
-rw-r--r--include/dt-bindings/clock/qcom,gcc-msm8996.h9
-rw-r--r--include/dt-bindings/clock/qcom,gcc-qcs404.h165
-rw-r--r--include/dt-bindings/clock/qcom,gcc-sdm660.h156
-rw-r--r--include/dt-bindings/clock/qcom,gcc-sdm845.h3
-rw-r--r--include/dt-bindings/clock/r7s72100-clock.h7
-rw-r--r--include/dt-bindings/clock/r7s9210-cpg-mssr.h20
-rw-r--r--include/dt-bindings/clock/r8a7743-cpg-mssr.h8
-rw-r--r--include/dt-bindings/clock/r8a7744-cpg-mssr.h39
-rw-r--r--include/dt-bindings/clock/r8a7745-cpg-mssr.h8
-rw-r--r--include/dt-bindings/clock/r8a774a1-cpg-mssr.h58
-rw-r--r--include/dt-bindings/clock/r8a774c0-cpg-mssr.h60
-rw-r--r--include/dt-bindings/clock/r8a7790-cpg-mssr.h8
-rw-r--r--include/dt-bindings/clock/r8a7791-cpg-mssr.h8
-rw-r--r--include/dt-bindings/clock/r8a7792-cpg-mssr.h8
-rw-r--r--include/dt-bindings/clock/r8a7793-clock.h12
-rw-r--r--include/dt-bindings/clock/r8a7793-cpg-mssr.h8
-rw-r--r--include/dt-bindings/clock/r8a7794-clock.h8
-rw-r--r--include/dt-bindings/clock/r8a7794-cpg-mssr.h8
-rw-r--r--include/dt-bindings/clock/r8a7795-cpg-mssr.h8
-rw-r--r--include/dt-bindings/clock/r8a7796-cpg-mssr.h8
-rw-r--r--include/dt-bindings/clock/r8a77970-cpg-mssr.h8
-rw-r--r--include/dt-bindings/clock/r8a77995-cpg-mssr.h8
-rw-r--r--include/dt-bindings/clock/renesas-cpg-mssr.h8
-rw-r--r--include/dt-bindings/clock/s3c2410.h5
-rw-r--r--include/dt-bindings/clock/s3c2412.h5
-rw-r--r--include/dt-bindings/clock/s3c2443.h5
-rw-r--r--include/dt-bindings/clock/samsung,s2mps11.h5
-rw-r--r--include/dt-bindings/clock/samsung,s3c64xx-clock.h7
-rw-r--r--include/dt-bindings/clock/sun50i-a64-ccu.h1
-rw-r--r--include/linux/clk-provider.h9
-rw-r--r--include/linux/clk.h90
-rw-r--r--include/linux/clk/renesas.h8
-rw-r--r--include/linux/clk/ti.h7
218 files changed, 15601 insertions, 2719 deletions
diff --git a/Documentation/devicetree/bindings/clock/hi3670-clock.txt b/Documentation/devicetree/bindings/clock/hi3670-clock.txt
new file mode 100644
index 000000000000..66f3697eca78
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hi3670-clock.txt
@@ -0,0 +1,43 @@
1* Hisilicon Hi3670 Clock Controller
2
3The Hi3670 clock controller generates and supplies clock to various
4controllers within the Hi3670 SoC.
5
6Required Properties:
7
8- compatible: the compatible should be one of the following strings to
9 indicate the clock controller functionality.
10
11 - "hisilicon,hi3670-crgctrl"
12 - "hisilicon,hi3670-pctrl"
13 - "hisilicon,hi3670-pmuctrl"
14 - "hisilicon,hi3670-sctrl"
15 - "hisilicon,hi3670-iomcu"
16 - "hisilicon,hi3670-media1-crg"
17 - "hisilicon,hi3670-media2-crg"
18
19- reg: physical base address of the controller and length of memory mapped
20 region.
21
22- #clock-cells: should be 1.
23
24Each clock is assigned an identifier and client nodes use this identifier
25to specify the clock which they consume.
26
27All these identifier could be found in <dt-bindings/clock/hi3670-clock.h>.
28
29Examples:
30 crg_ctrl: clock-controller@fff35000 {
31 compatible = "hisilicon,hi3670-crgctrl", "syscon";
32 reg = <0x0 0xfff35000 0x0 0x1000>;
33 #clock-cells = <1>;
34 };
35
36 uart0: serial@fdf02000 {
37 compatible = "arm,pl011", "arm,primecell";
38 reg = <0x0 0xfdf02000 0x0 0x1000>;
39 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
40 clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
41 <&crg_ctrl HI3670_PCLK>;
42 clock-names = "uartclk", "apb_pclk";
43 };
diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
index f8d4134ae409..ba5a442026b7 100644
--- a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
+++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
@@ -6,8 +6,11 @@ to provide many different clock signals derived from only 2 external source
6clocks. 6clocks.
7 7
8Required properties: 8Required properties:
9- compatible : Should be "ingenic,<soctype>-cgu". 9- compatible : Should be one of:
10 For example "ingenic,jz4740-cgu" or "ingenic,jz4780-cgu". 10 * ingenic,jz4740-cgu
11 * ingenic,jz4725b-cgu
12 * ingenic,jz4770-cgu
13 * ingenic,jz4780-cgu
11- reg : The address & length of the CGU registers. 14- reg : The address & length of the CGU registers.
12- clocks : List of phandle & clock specifiers for clocks external to the CGU. 15- clocks : List of phandle & clock specifiers for clocks external to the CGU.
13 Two such external clocks should be specified - first the external crystal 16 Two such external clocks should be specified - first the external crystal
diff --git a/Documentation/devicetree/bindings/clock/qcom,camcc.txt b/Documentation/devicetree/bindings/clock/qcom,camcc.txt
new file mode 100644
index 000000000000..c5eb6694fda9
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,camcc.txt
@@ -0,0 +1,18 @@
1Qualcomm Camera Clock & Reset Controller Binding
2------------------------------------------------
3
4Required properties :
5- compatible : shall contain "qcom,sdm845-camcc".
6- reg : shall contain base register location and length.
7- #clock-cells : from common clock binding, shall contain 1.
8- #reset-cells : from common reset binding, shall contain 1.
9- #power-domain-cells : from generic power domain binding, shall contain 1.
10
11Example:
12 camcc: clock-controller@ad00000 {
13 compatible = "qcom,sdm845-camcc";
14 reg = <0xad00000 0x10000>;
15 #clock-cells = <1>;
16 #reset-cells = <1>;
17 #power-domain-cells = <1>;
18 };
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 664ea1fd6c76..52d9345c9927 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -19,6 +19,9 @@ Required properties :
19 "qcom,gcc-msm8996" 19 "qcom,gcc-msm8996"
20 "qcom,gcc-msm8998" 20 "qcom,gcc-msm8998"
21 "qcom,gcc-mdm9615" 21 "qcom,gcc-mdm9615"
22 "qcom,gcc-qcs404"
23 "qcom,gcc-sdm630"
24 "qcom,gcc-sdm660"
22 "qcom,gcc-sdm845" 25 "qcom,gcc-sdm845"
23 26
24- reg : shall contain base register location and length 27- reg : shall contain base register location and length
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
index db542abadb75..916a601b76a7 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -13,9 +13,13 @@ They provide the following functionalities:
13 13
14Required Properties: 14Required Properties:
15 - compatible: Must be one of: 15 - compatible: Must be one of:
16 - "renesas,r7s9210-cpg-mssr" for the r7s9210 SoC (RZ/A2)
16 - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M) 17 - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
18 - "renesas,r8a7744-cpg-mssr" for the r8a7744 SoC (RZ/G1N)
17 - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E) 19 - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
18 - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C) 20 - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
21 - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)
22 - "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E)
19 - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2) 23 - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
20 - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W) 24 - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
21 - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H) 25 - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
@@ -35,12 +39,13 @@ Required Properties:
35 - clocks: References to external parent clocks, one entry for each entry in 39 - clocks: References to external parent clocks, one entry for each entry in
36 clock-names 40 clock-names
37 - clock-names: List of external parent clock names. Valid names are: 41 - clock-names: List of external parent clock names. Valid names are:
38 - "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792, 42 - "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1,
39 r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970, 43 r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
40 r8a77980, r8a77990, r8a77995) 44 r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77990,
41 - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980) 45 r8a77995)
42 - "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793, 46 - "extalr" (r8a774a1, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
43 r8a7794) 47 - "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791,
48 r8a7793, r8a7794)
44 49
45 - #clock-cells: Must be 2 50 - #clock-cells: Must be 2
46 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" 51 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
diff --git a/arch/arm/mach-davinci/include/mach/clock.h b/arch/arm/mach-davinci/include/mach/clock.h
deleted file mode 100644
index 42ed4f2f5ce4..000000000000
--- a/arch/arm/mach-davinci/include/mach/clock.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * arch/arm/mach-davinci/include/mach/clock.h
3 *
4 * Clock control driver for DaVinci - header file
5 *
6 * Authors: Vladimir Barinov <source@mvista.com>
7 *
8 * 2007 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13#ifndef __ASM_ARCH_DAVINCI_CLOCK_H
14#define __ASM_ARCH_DAVINCI_CLOCK_H
15
16struct clk;
17
18int davinci_clk_reset_assert(struct clk *c);
19int davinci_clk_reset_deassert(struct clk *c);
20
21#endif
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 292056bbb30e..cd9b1d0cb23b 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -287,6 +287,7 @@ source "drivers/clk/actions/Kconfig"
287source "drivers/clk/bcm/Kconfig" 287source "drivers/clk/bcm/Kconfig"
288source "drivers/clk/hisilicon/Kconfig" 288source "drivers/clk/hisilicon/Kconfig"
289source "drivers/clk/imgtec/Kconfig" 289source "drivers/clk/imgtec/Kconfig"
290source "drivers/clk/ingenic/Kconfig"
290source "drivers/clk/keystone/Kconfig" 291source "drivers/clk/keystone/Kconfig"
291source "drivers/clk/mediatek/Kconfig" 292source "drivers/clk/mediatek/Kconfig"
292source "drivers/clk/meson/Kconfig" 293source "drivers/clk/meson/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index a84c5573cabe..b49d54fc0599 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -72,7 +72,8 @@ obj-$(CONFIG_H8300) += h8300/
72obj-$(CONFIG_ARCH_HISI) += hisilicon/ 72obj-$(CONFIG_ARCH_HISI) += hisilicon/
73obj-y += imgtec/ 73obj-y += imgtec/
74obj-$(CONFIG_ARCH_MXC) += imx/ 74obj-$(CONFIG_ARCH_MXC) += imx/
75obj-$(CONFIG_MACH_INGENIC) += ingenic/ 75obj-y += ingenic/
76obj-$(CONFIG_ARCH_K3) += keystone/
76obj-$(CONFIG_ARCH_KEYSTONE) += keystone/ 77obj-$(CONFIG_ARCH_KEYSTONE) += keystone/
77obj-$(CONFIG_MACH_LOONGSON32) += loongson1/ 78obj-$(CONFIG_MACH_LOONGSON32) += loongson1/
78obj-y += mediatek/ 79obj-y += mediatek/
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
index 72b6091eb7b9..dc7fbc796cb6 100644
--- a/drivers/clk/at91/clk-pll.c
+++ b/drivers/clk/at91/clk-pll.c
@@ -133,6 +133,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
133{ 133{
134 struct clk_pll *pll = to_clk_pll(hw); 134 struct clk_pll *pll = to_clk_pll(hw);
135 135
136 if (!pll->div || !pll->mul)
137 return 0;
138
136 return (parent_rate / pll->div) * (pll->mul + 1); 139 return (parent_rate / pll->div) * (pll->mul + 1);
137} 140}
138 141
diff --git a/drivers/clk/axs10x/pll_clock.c b/drivers/clk/axs10x/pll_clock.c
index 25d8c240ddfb..c68dada97316 100644
--- a/drivers/clk/axs10x/pll_clock.c
+++ b/drivers/clk/axs10x/pll_clock.c
@@ -301,13 +301,13 @@ static void __init of_axs10x_pll_clk_setup(struct device_node *node)
301 301
302 ret = clk_hw_register(NULL, &pll_clk->hw); 302 ret = clk_hw_register(NULL, &pll_clk->hw);
303 if (ret) { 303 if (ret) {
304 pr_err("failed to register %s clock\n", node->name); 304 pr_err("failed to register %pOFn clock\n", node);
305 goto err_unmap_lock; 305 goto err_unmap_lock;
306 } 306 }
307 307
308 ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw); 308 ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);
309 if (ret) { 309 if (ret) {
310 pr_err("failed to add hw provider for %s clock\n", node->name); 310 pr_err("failed to add hw provider for %pOFn clock\n", node);
311 goto err_unregister_clk; 311 goto err_unregister_clk;
312 } 312 }
313 313
diff --git a/drivers/clk/bcm/clk-kona-setup.c b/drivers/clk/bcm/clk-kona-setup.c
index 281f4322355c..e65eeef9cbaf 100644
--- a/drivers/clk/bcm/clk-kona-setup.c
+++ b/drivers/clk/bcm/clk-kona-setup.c
@@ -808,29 +808,29 @@ void __init kona_dt_ccu_setup(struct ccu_data *ccu,
808 808
809 ret = of_address_to_resource(node, 0, &res); 809 ret = of_address_to_resource(node, 0, &res);
810 if (ret) { 810 if (ret) {
811 pr_err("%s: no valid CCU registers found for %s\n", __func__, 811 pr_err("%s: no valid CCU registers found for %pOFn\n", __func__,
812 node->name); 812 node);
813 goto out_err; 813 goto out_err;
814 } 814 }
815 815
816 range = resource_size(&res); 816 range = resource_size(&res);
817 if (range > (resource_size_t)U32_MAX) { 817 if (range > (resource_size_t)U32_MAX) {
818 pr_err("%s: address range too large for %s\n", __func__, 818 pr_err("%s: address range too large for %pOFn\n", __func__,
819 node->name); 819 node);
820 goto out_err; 820 goto out_err;
821 } 821 }
822 822
823 ccu->range = (u32)range; 823 ccu->range = (u32)range;
824 824
825 if (!ccu_data_valid(ccu)) { 825 if (!ccu_data_valid(ccu)) {
826 pr_err("%s: ccu data not valid for %s\n", __func__, node->name); 826 pr_err("%s: ccu data not valid for %pOFn\n", __func__, node);
827 goto out_err; 827 goto out_err;
828 } 828 }
829 829
830 ccu->base = ioremap(res.start, ccu->range); 830 ccu->base = ioremap(res.start, ccu->range);
831 if (!ccu->base) { 831 if (!ccu->base) {
832 pr_err("%s: unable to map CCU registers for %s\n", __func__, 832 pr_err("%s: unable to map CCU registers for %pOFn\n", __func__,
833 node->name); 833 node);
834 goto out_err; 834 goto out_err;
835 } 835 }
836 ccu->node = of_node_get(node); 836 ccu->node = of_node_get(node);
@@ -848,16 +848,16 @@ void __init kona_dt_ccu_setup(struct ccu_data *ccu,
848 848
849 ret = of_clk_add_hw_provider(node, of_clk_kona_onecell_get, ccu); 849 ret = of_clk_add_hw_provider(node, of_clk_kona_onecell_get, ccu);
850 if (ret) { 850 if (ret) {
851 pr_err("%s: error adding ccu %s as provider (%d)\n", __func__, 851 pr_err("%s: error adding ccu %pOFn as provider (%d)\n", __func__,
852 node->name, ret); 852 node, ret);
853 goto out_err; 853 goto out_err;
854 } 854 }
855 855
856 if (!kona_ccu_init(ccu)) 856 if (!kona_ccu_init(ccu))
857 pr_err("Broadcom %s initialization had errors\n", node->name); 857 pr_err("Broadcom %pOFn initialization had errors\n", node);
858 858
859 return; 859 return;
860out_err: 860out_err:
861 kona_ccu_teardown(ccu); 861 kona_ccu_teardown(ccu);
862 pr_err("Broadcom %s setup aborted\n", node->name); 862 pr_err("Broadcom %pOFn setup aborted\n", node);
863} 863}
diff --git a/drivers/clk/clk-asm9260.c b/drivers/clk/clk-asm9260.c
index 44b544157121..d571a00b5282 100644
--- a/drivers/clk/clk-asm9260.c
+++ b/drivers/clk/clk-asm9260.c
@@ -281,7 +281,7 @@ static void __init asm9260_acc_init(struct device_node *np)
281 281
282 base = of_io_request_and_map(np, 0, np->name); 282 base = of_io_request_and_map(np, 0, np->name);
283 if (IS_ERR(base)) 283 if (IS_ERR(base))
284 panic("%s: unable to map resource", np->name); 284 panic("%pOFn: unable to map resource", np);
285 285
286 /* register pll */ 286 /* register pll */
287 rate = (ioread32(base + HW_SYSPLLCTRL) & 0xffff) * 1000000; 287 rate = (ioread32(base + HW_SYSPLLCTRL) & 0xffff) * 1000000;
@@ -292,7 +292,7 @@ static void __init asm9260_acc_init(struct device_node *np)
292 ref_clk, 0, rate, accuracy); 292 ref_clk, 0, rate, accuracy);
293 293
294 if (IS_ERR(hw)) 294 if (IS_ERR(hw))
295 panic("%s: can't register REFCLK. Check DT!", np->name); 295 panic("%pOFn: can't register REFCLK. Check DT!", np);
296 296
297 for (n = 0; n < ARRAY_SIZE(asm9260_mux_clks); n++) { 297 for (n = 0; n < ARRAY_SIZE(asm9260_mux_clks); n++) {
298 const struct asm9260_mux_clock *mc = &asm9260_mux_clks[n]; 298 const struct asm9260_mux_clock *mc = &asm9260_mux_clks[n];
diff --git a/drivers/clk/clk-bulk.c b/drivers/clk/clk-bulk.c
index 6904ed6da504..6a7118d4250a 100644
--- a/drivers/clk/clk-bulk.c
+++ b/drivers/clk/clk-bulk.c
@@ -17,8 +17,65 @@
17 */ 17 */
18 18
19#include <linux/clk.h> 19#include <linux/clk.h>
20#include <linux/clk-provider.h>
20#include <linux/device.h> 21#include <linux/device.h>
21#include <linux/export.h> 22#include <linux/export.h>
23#include <linux/of.h>
24#include <linux/slab.h>
25
26static int __must_check of_clk_bulk_get(struct device_node *np, int num_clks,
27 struct clk_bulk_data *clks)
28{
29 int ret;
30 int i;
31
32 for (i = 0; i < num_clks; i++)
33 clks[i].clk = NULL;
34
35 for (i = 0; i < num_clks; i++) {
36 clks[i].clk = of_clk_get(np, i);
37 if (IS_ERR(clks[i].clk)) {
38 ret = PTR_ERR(clks[i].clk);
39 pr_err("%pOF: Failed to get clk index: %d ret: %d\n",
40 np, i, ret);
41 clks[i].clk = NULL;
42 goto err;
43 }
44 }
45
46 return 0;
47
48err:
49 clk_bulk_put(i, clks);
50
51 return ret;
52}
53
54static int __must_check of_clk_bulk_get_all(struct device_node *np,
55 struct clk_bulk_data **clks)
56{
57 struct clk_bulk_data *clk_bulk;
58 int num_clks;
59 int ret;
60
61 num_clks = of_clk_get_parent_count(np);
62 if (!num_clks)
63 return 0;
64
65 clk_bulk = kmalloc_array(num_clks, sizeof(*clk_bulk), GFP_KERNEL);
66 if (!clk_bulk)
67 return -ENOMEM;
68
69 ret = of_clk_bulk_get(np, num_clks, clk_bulk);
70 if (ret) {
71 kfree(clk_bulk);
72 return ret;
73 }
74
75 *clks = clk_bulk;
76
77 return num_clks;
78}
22 79
23void clk_bulk_put(int num_clks, struct clk_bulk_data *clks) 80void clk_bulk_put(int num_clks, struct clk_bulk_data *clks)
24{ 81{
@@ -59,6 +116,29 @@ err:
59} 116}
60EXPORT_SYMBOL(clk_bulk_get); 117EXPORT_SYMBOL(clk_bulk_get);
61 118
119void clk_bulk_put_all(int num_clks, struct clk_bulk_data *clks)
120{
121 if (IS_ERR_OR_NULL(clks))
122 return;
123
124 clk_bulk_put(num_clks, clks);
125
126 kfree(clks);
127}
128EXPORT_SYMBOL(clk_bulk_put_all);
129
130int __must_check clk_bulk_get_all(struct device *dev,
131 struct clk_bulk_data **clks)
132{
133 struct device_node *np = dev_of_node(dev);
134
135 if (!np)
136 return 0;
137
138 return of_clk_bulk_get_all(np, clks);
139}
140EXPORT_SYMBOL(clk_bulk_get_all);
141
62#ifdef CONFIG_HAVE_CLK_PREPARE 142#ifdef CONFIG_HAVE_CLK_PREPARE
63 143
64/** 144/**
diff --git a/drivers/clk/clk-cdce925.c b/drivers/clk/clk-cdce925.c
index 0a7e7d5a7506..23c9326ea48c 100644
--- a/drivers/clk/clk-cdce925.c
+++ b/drivers/clk/clk-cdce925.c
@@ -669,8 +669,8 @@ static int cdce925_probe(struct i2c_client *client,
669 669
670 /* Register PLL clocks */ 670 /* Register PLL clocks */
671 for (i = 0; i < data->chip_info->num_plls; ++i) { 671 for (i = 0; i < data->chip_info->num_plls; ++i) {
672 pll_clk_name[i] = kasprintf(GFP_KERNEL, "%s.pll%d", 672 pll_clk_name[i] = kasprintf(GFP_KERNEL, "%pOFn.pll%d",
673 client->dev.of_node->name, i); 673 client->dev.of_node, i);
674 init.name = pll_clk_name[i]; 674 init.name = pll_clk_name[i];
675 data->pll[i].chip = data; 675 data->pll[i].chip = data;
676 data->pll[i].hw.init = &init; 676 data->pll[i].hw.init = &init;
@@ -703,6 +703,7 @@ static int cdce925_probe(struct i2c_client *client,
703 0x12 + (i*CDCE925_OFFSET_PLL), 703 0x12 + (i*CDCE925_OFFSET_PLL),
704 0x07, value & 0x07); 704 0x07, value & 0x07);
705 } 705 }
706 of_node_put(np_output);
706 } 707 }
707 708
708 /* Register output clock Y1 */ 709 /* Register output clock Y1 */
@@ -710,7 +711,7 @@ static int cdce925_probe(struct i2c_client *client,
710 init.flags = 0; 711 init.flags = 0;
711 init.num_parents = 1; 712 init.num_parents = 1;
712 init.parent_names = &parent_name; /* Mux Y1 to input */ 713 init.parent_names = &parent_name; /* Mux Y1 to input */
713 init.name = kasprintf(GFP_KERNEL, "%s.Y1", client->dev.of_node->name); 714 init.name = kasprintf(GFP_KERNEL, "%pOFn.Y1", client->dev.of_node);
714 data->clk[0].chip = data; 715 data->clk[0].chip = data;
715 data->clk[0].hw.init = &init; 716 data->clk[0].hw.init = &init;
716 data->clk[0].index = 0; 717 data->clk[0].index = 0;
@@ -727,8 +728,8 @@ static int cdce925_probe(struct i2c_client *client,
727 init.flags = CLK_SET_RATE_PARENT; 728 init.flags = CLK_SET_RATE_PARENT;
728 init.num_parents = 1; 729 init.num_parents = 1;
729 for (i = 1; i < data->chip_info->num_outputs; ++i) { 730 for (i = 1; i < data->chip_info->num_outputs; ++i) {
730 init.name = kasprintf(GFP_KERNEL, "%s.Y%d", 731 init.name = kasprintf(GFP_KERNEL, "%pOFn.Y%d",
731 client->dev.of_node->name, i+1); 732 client->dev.of_node, i+1);
732 data->clk[i].chip = data; 733 data->clk[i].chip = data;
733 data->clk[i].hw.init = &init; 734 data->clk[i].hw.init = &init;
734 data->clk[i].index = i; 735 data->clk[i].index = i;
diff --git a/drivers/clk/clk-devres.c b/drivers/clk/clk-devres.c
index d854e26a8ddb..12c87457eca1 100644
--- a/drivers/clk/clk-devres.c
+++ b/drivers/clk/clk-devres.c
@@ -70,6 +70,30 @@ int __must_check devm_clk_bulk_get(struct device *dev, int num_clks,
70} 70}
71EXPORT_SYMBOL_GPL(devm_clk_bulk_get); 71EXPORT_SYMBOL_GPL(devm_clk_bulk_get);
72 72
73int __must_check devm_clk_bulk_get_all(struct device *dev,
74 struct clk_bulk_data **clks)
75{
76 struct clk_bulk_devres *devres;
77 int ret;
78
79 devres = devres_alloc(devm_clk_bulk_release,
80 sizeof(*devres), GFP_KERNEL);
81 if (!devres)
82 return -ENOMEM;
83
84 ret = clk_bulk_get_all(dev, &devres->clks);
85 if (ret > 0) {
86 *clks = devres->clks;
87 devres->num_clks = ret;
88 devres_add(dev, devres);
89 } else {
90 devres_free(devres);
91 }
92
93 return ret;
94}
95EXPORT_SYMBOL_GPL(devm_clk_bulk_get_all);
96
73static int devm_clk_match(struct device *dev, void *res, void *data) 97static int devm_clk_match(struct device *dev, void *res, void *data)
74{ 98{
75 struct clk **c = res; 99 struct clk **c = res;
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 20724abd38bd..ef0ca9414f37 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -158,14 +158,14 @@ static struct clk *_of_fixed_factor_clk_setup(struct device_node *node)
158 int ret; 158 int ret;
159 159
160 if (of_property_read_u32(node, "clock-div", &div)) { 160 if (of_property_read_u32(node, "clock-div", &div)) {
161 pr_err("%s Fixed factor clock <%s> must have a clock-div property\n", 161 pr_err("%s Fixed factor clock <%pOFn> must have a clock-div property\n",
162 __func__, node->name); 162 __func__, node);
163 return ERR_PTR(-EIO); 163 return ERR_PTR(-EIO);
164 } 164 }
165 165
166 if (of_property_read_u32(node, "clock-mult", &mult)) { 166 if (of_property_read_u32(node, "clock-mult", &mult)) {
167 pr_err("%s Fixed factor clock <%s> must have a clock-mult property\n", 167 pr_err("%s Fixed factor clock <%pOFn> must have a clock-mult property\n",
168 __func__, node->name); 168 __func__, node);
169 return ERR_PTR(-EIO); 169 return ERR_PTR(-EIO);
170 } 170 }
171 171
diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c
index 40af4fbab4d2..6a43ce420492 100644
--- a/drivers/clk/clk-gpio.c
+++ b/drivers/clk/clk-gpio.c
@@ -233,11 +233,11 @@ static int gpio_clk_driver_probe(struct platform_device *pdev)
233 if (IS_ERR(gpiod)) { 233 if (IS_ERR(gpiod)) {
234 ret = PTR_ERR(gpiod); 234 ret = PTR_ERR(gpiod);
235 if (ret == -EPROBE_DEFER) 235 if (ret == -EPROBE_DEFER)
236 pr_debug("%s: %s: GPIOs not yet available, retry later\n", 236 pr_debug("%pOFn: %s: GPIOs not yet available, retry later\n",
237 node->name, __func__); 237 node, __func__);
238 else 238 else
239 pr_err("%s: %s: Can't get '%s' named GPIO property\n", 239 pr_err("%pOFn: %s: Can't get '%s' named GPIO property\n",
240 node->name, __func__, 240 node, __func__,
241 gpio_name); 241 gpio_name);
242 return ret; 242 return ret;
243 } 243 }
diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
index c4ee280f454d..a47c2b600f20 100644
--- a/drivers/clk/clk-hsdk-pll.c
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -390,13 +390,13 @@ static void __init of_hsdk_pll_clk_setup(struct device_node *node)
390 390
391 ret = clk_hw_register(NULL, &pll_clk->hw); 391 ret = clk_hw_register(NULL, &pll_clk->hw);
392 if (ret) { 392 if (ret) {
393 pr_err("failed to register %s clock\n", node->name); 393 pr_err("failed to register %pOFn clock\n", node);
394 goto err_unmap_spec_regs; 394 goto err_unmap_spec_regs;
395 } 395 }
396 396
397 ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw); 397 ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);
398 if (ret) { 398 if (ret) {
399 pr_err("failed to add hw provider for %s clock\n", node->name); 399 pr_err("failed to add hw provider for %pOFn clock\n", node);
400 goto err_unmap_spec_regs; 400 goto err_unmap_spec_regs;
401 } 401 }
402 402
diff --git a/drivers/clk/clk-max77686.c b/drivers/clk/clk-max77686.c
index eb953d3b0b69..02551fe4b87c 100644
--- a/drivers/clk/clk-max77686.c
+++ b/drivers/clk/clk-max77686.c
@@ -1,24 +1,9 @@
1/* 1// SPDX-License-Identifier: GPL-2.0+
2 * clk-max77686.c - Clock driver for Maxim 77686/MAX77802 2//
3 * 3// clk-max77686.c - Clock driver for Maxim 77686/MAX77802
4 * Copyright (C) 2012 Samsung Electornics 4//
5 * Jonghwa Lee <jonghwa3.lee@samsung.com> 5// Copyright (C) 2012 Samsung Electornics
6 * 6// Jonghwa Lee <jonghwa3.lee@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22 7
23#include <linux/kernel.h> 8#include <linux/kernel.h>
24#include <linux/slab.h> 9#include <linux/slab.h>
diff --git a/drivers/clk/clk-nomadik.c b/drivers/clk/clk-nomadik.c
index 13ad6d1e5090..84a24875c629 100644
--- a/drivers/clk/clk-nomadik.c
+++ b/drivers/clk/clk-nomadik.c
@@ -97,8 +97,8 @@ static void __init nomadik_src_init(void)
97 } 97 }
98 src_base = of_iomap(np, 0); 98 src_base = of_iomap(np, 0);
99 if (!src_base) { 99 if (!src_base) {
100 pr_err("%s: must have src parent node with REGS (%s)\n", 100 pr_err("%s: must have src parent node with REGS (%pOFn)\n",
101 __func__, np->name); 101 __func__, np);
102 return; 102 return;
103 } 103 }
104 104
diff --git a/drivers/clk/clk-npcm7xx.c b/drivers/clk/clk-npcm7xx.c
index 740af90a9508..afb0eb106953 100644
--- a/drivers/clk/clk-npcm7xx.c
+++ b/drivers/clk/clk-npcm7xx.c
@@ -549,7 +549,7 @@ static void __init npcm7xx_clk_init(struct device_node *clk_np)
549 549
550 ret = of_address_to_resource(clk_np, 0, &res); 550 ret = of_address_to_resource(clk_np, 0, &res);
551 if (ret) { 551 if (ret) {
552 pr_err("%s: failed to get resource, ret %d\n", clk_np->name, 552 pr_err("%pOFn: failed to get resource, ret %d\n", clk_np,
553 ret); 553 ret);
554 return; 554 return;
555 } 555 }
diff --git a/drivers/clk/clk-palmas.c b/drivers/clk/clk-palmas.c
index 7f51c01085ab..e9612e7068e9 100644
--- a/drivers/clk/clk-palmas.c
+++ b/drivers/clk/clk-palmas.c
@@ -195,8 +195,8 @@ static void palmas_clks_get_clk_data(struct platform_device *pdev,
195 prop = PALMAS_EXT_CONTROL_NSLEEP; 195 prop = PALMAS_EXT_CONTROL_NSLEEP;
196 break; 196 break;
197 default: 197 default:
198 dev_warn(&pdev->dev, "%s: Invalid ext control option: %u\n", 198 dev_warn(&pdev->dev, "%pOFn: Invalid ext control option: %u\n",
199 node->name, prop); 199 node, prop);
200 prop = 0; 200 prop = 0;
201 break; 201 break;
202 } 202 }
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 3a1812f65e5d..4c30b6e799ed 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -945,8 +945,8 @@ static void __init core_mux_init(struct device_node *np)
945 945
946 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk); 946 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
947 if (rc) { 947 if (rc) {
948 pr_err("%s: Couldn't register clk provider for node %s: %d\n", 948 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
949 __func__, np->name, rc); 949 __func__, np, rc);
950 return; 950 return;
951 } 951 }
952} 952}
@@ -1199,8 +1199,8 @@ static void __init legacy_pll_init(struct device_node *np, int idx)
1199 1199
1200 rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data); 1200 rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);
1201 if (rc) { 1201 if (rc) {
1202 pr_err("%s: Couldn't register clk provider for node %s: %d\n", 1202 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
1203 __func__, np->name, rc); 1203 __func__, np, rc);
1204 goto err_cell; 1204 goto err_cell;
1205 } 1205 }
1206 1206
@@ -1360,7 +1360,7 @@ static void __init clockgen_init(struct device_node *np)
1360 is_old_ls1021a = true; 1360 is_old_ls1021a = true;
1361 } 1361 }
1362 if (!clockgen.regs) { 1362 if (!clockgen.regs) {
1363 pr_err("%s(): %s: of_iomap() failed\n", __func__, np->name); 1363 pr_err("%s(): %pOFn: of_iomap() failed\n", __func__, np);
1364 return; 1364 return;
1365 } 1365 }
1366 1366
@@ -1406,8 +1406,8 @@ static void __init clockgen_init(struct device_node *np)
1406 1406
1407 ret = of_clk_add_provider(np, clockgen_clk_get, &clockgen); 1407 ret = of_clk_add_provider(np, clockgen_clk_get, &clockgen);
1408 if (ret) { 1408 if (ret) {
1409 pr_err("%s: Couldn't register clk provider for node %s: %d\n", 1409 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
1410 __func__, np->name, ret); 1410 __func__, np, ret);
1411 } 1411 }
1412 1412
1413 return; 1413 return;
diff --git a/drivers/clk/clk-s2mps11.c b/drivers/clk/clk-s2mps11.c
index d44e0eea31ec..56221647207d 100644
--- a/drivers/clk/clk-s2mps11.c
+++ b/drivers/clk/clk-s2mps11.c
@@ -1,19 +1,8 @@
1/* 1// SPDX-License-Identifier: GPL-2.0+
2 * clk-s2mps11.c - Clock driver for S2MPS11. 2//
3 * 3// clk-s2mps11.c - Clock driver for S2MPS11.
4 * Copyright (C) 2013,2014 Samsung Electornics 4//
5 * 5// Copyright (C) 2013,2014 Samsung Electornics
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17 6
18#include <linux/module.h> 7#include <linux/module.h>
19#include <linux/err.h> 8#include <linux/err.h>
@@ -28,12 +17,7 @@
28#include <linux/mfd/samsung/s5m8767.h> 17#include <linux/mfd/samsung/s5m8767.h>
29#include <linux/mfd/samsung/core.h> 18#include <linux/mfd/samsung/core.h>
30 19
31enum { 20#include <dt-bindings/clock/samsung,s2mps11.h>
32 S2MPS11_CLK_AP = 0,
33 S2MPS11_CLK_CP,
34 S2MPS11_CLK_BT,
35 S2MPS11_CLKS_NUM,
36};
37 21
38struct s2mps11_clk { 22struct s2mps11_clk {
39 struct sec_pmic_dev *iodev; 23 struct sec_pmic_dev *iodev;
diff --git a/drivers/clk/clk-scmi.c b/drivers/clk/clk-scmi.c
index a985bf5e1ac6..a2287c770d5c 100644
--- a/drivers/clk/clk-scmi.c
+++ b/drivers/clk/clk-scmi.c
@@ -132,7 +132,7 @@ static int scmi_clocks_probe(struct scmi_device *sdev)
132 132
133 count = handle->clk_ops->count_get(handle); 133 count = handle->clk_ops->count_get(handle);
134 if (count < 0) { 134 if (count < 0) {
135 dev_err(dev, "%s: invalid clock output count\n", np->name); 135 dev_err(dev, "%pOFn: invalid clock output count\n", np);
136 return -EINVAL; 136 return -EINVAL;
137 } 137 }
138 138
diff --git a/drivers/clk/clk-scpi.c b/drivers/clk/clk-scpi.c
index 25854722810e..d3ccc1cfccd5 100644
--- a/drivers/clk/clk-scpi.c
+++ b/drivers/clk/clk-scpi.c
@@ -207,7 +207,7 @@ static int scpi_clk_add(struct device *dev, struct device_node *np,
207 207
208 count = of_property_count_strings(np, "clock-output-names"); 208 count = of_property_count_strings(np, "clock-output-names");
209 if (count < 0) { 209 if (count < 0) {
210 dev_err(dev, "%s: invalid clock output count\n", np->name); 210 dev_err(dev, "%pOFn: invalid clock output count\n", np);
211 return -EINVAL; 211 return -EINVAL;
212 } 212 }
213 213
@@ -232,13 +232,13 @@ static int scpi_clk_add(struct device *dev, struct device_node *np,
232 232
233 if (of_property_read_string_index(np, "clock-output-names", 233 if (of_property_read_string_index(np, "clock-output-names",
234 idx, &name)) { 234 idx, &name)) {
235 dev_err(dev, "invalid clock name @ %s\n", np->name); 235 dev_err(dev, "invalid clock name @ %pOFn\n", np);
236 return -EINVAL; 236 return -EINVAL;
237 } 237 }
238 238
239 if (of_property_read_u32_index(np, "clock-indices", 239 if (of_property_read_u32_index(np, "clock-indices",
240 idx, &val)) { 240 idx, &val)) {
241 dev_err(dev, "invalid clock index @ %s\n", np->name); 241 dev_err(dev, "invalid clock index @ %pOFn\n", np);
242 return -EINVAL; 242 return -EINVAL;
243 } 243 }
244 244
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index 50e7c341e97e..8bdf91b56012 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -1215,8 +1215,8 @@ static int si5351_dt_parse(struct i2c_client *client,
1215 /* per clkout properties */ 1215 /* per clkout properties */
1216 for_each_child_of_node(np, child) { 1216 for_each_child_of_node(np, child) {
1217 if (of_property_read_u32(child, "reg", &num)) { 1217 if (of_property_read_u32(child, "reg", &num)) {
1218 dev_err(&client->dev, "missing reg property of %s\n", 1218 dev_err(&client->dev, "missing reg property of %pOFn\n",
1219 child->name); 1219 child);
1220 goto put_child; 1220 goto put_child;
1221 } 1221 }
1222 1222
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 294850bdc195..cdaa567c8042 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -1433,7 +1433,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
1433 1433
1434 base = of_iomap(np, 0); 1434 base = of_iomap(np, 0);
1435 if (!base) { 1435 if (!base) {
1436 pr_err("%s: unable to map resource\n", np->name); 1436 pr_err("%pOFn: unable to map resource\n", np);
1437 return; 1437 return;
1438 } 1438 }
1439 1439
diff --git a/drivers/clk/clk-stm32h7.c b/drivers/clk/clk-stm32h7.c
index d3271eca3779..0ea7261d15e0 100644
--- a/drivers/clk/clk-stm32h7.c
+++ b/drivers/clk/clk-stm32h7.c
@@ -1216,7 +1216,7 @@ static void __init stm32h7_rcc_init(struct device_node *np)
1216 /* get RCC base @ from DT */ 1216 /* get RCC base @ from DT */
1217 base = of_iomap(np, 0); 1217 base = of_iomap(np, 0);
1218 if (!base) { 1218 if (!base) {
1219 pr_err("%s: unable to map resource", np->name); 1219 pr_err("%pOFn: unable to map resource", np);
1220 goto err_free_clks; 1220 goto err_free_clks;
1221 } 1221 }
1222 1222
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index a907555b2a3d..4f48342bc280 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -2088,7 +2088,7 @@ static void stm32mp1_rcc_init(struct device_node *np)
2088 2088
2089 base = of_iomap(np, 0); 2089 base = of_iomap(np, 0);
2090 if (!base) { 2090 if (!base) {
2091 pr_err("%s: unable to map resource", np->name); 2091 pr_err("%pOFn: unable to map resource", np);
2092 of_node_put(np); 2092 of_node_put(np);
2093 return; 2093 return;
2094 } 2094 }
diff --git a/drivers/clk/clk-tango4.c b/drivers/clk/clk-tango4.c
index 34b22b7930fb..fe12a43f7a40 100644
--- a/drivers/clk/clk-tango4.c
+++ b/drivers/clk/clk-tango4.c
@@ -54,13 +54,13 @@ static void __init tango4_clkgen_setup(struct device_node *np)
54 const char *parent = of_clk_get_parent_name(np, 0); 54 const char *parent = of_clk_get_parent_name(np, 0);
55 55
56 if (!base) 56 if (!base)
57 panic("%s: invalid address\n", np->name); 57 panic("%pOFn: invalid address\n", np);
58 58
59 if (readl(base + CPUCLK_DIV) & DIV_BYPASS) 59 if (readl(base + CPUCLK_DIV) & DIV_BYPASS)
60 panic("%s: unsupported cpuclk setup\n", np->name); 60 panic("%pOFn: unsupported cpuclk setup\n", np);
61 61
62 if (readl(base + SYSCLK_DIV) & DIV_BYPASS) 62 if (readl(base + SYSCLK_DIV) & DIV_BYPASS)
63 panic("%s: unsupported sysclk setup\n", np->name); 63 panic("%pOFn: unsupported sysclk setup\n", np);
64 64
65 writel(0x100, base + CPUCLK_DIV); /* disable frequency ramping */ 65 writel(0x100, base + CPUCLK_DIV); /* disable frequency ramping */
66 66
@@ -77,9 +77,9 @@ static void __init tango4_clkgen_setup(struct device_node *np)
77 pp[3] = clk_register_fixed_factor(NULL, "sdio_clk", "cd6", 0, 1, 2); 77 pp[3] = clk_register_fixed_factor(NULL, "sdio_clk", "cd6", 0, 1, 2);
78 78
79 if (IS_ERR(pp[0]) || IS_ERR(pp[1]) || IS_ERR(pp[2]) || IS_ERR(pp[3])) 79 if (IS_ERR(pp[0]) || IS_ERR(pp[1]) || IS_ERR(pp[2]) || IS_ERR(pp[3]))
80 panic("%s: clk registration failed\n", np->name); 80 panic("%pOFn: clk registration failed\n", np);
81 81
82 if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) 82 if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data))
83 panic("%s: clk provider registration failed\n", np->name); 83 panic("%pOFn: clk provider registration failed\n", np);
84} 84}
85CLK_OF_DECLARE(tango4_clkgen, "sigma,tango4-clkgen", tango4_clkgen_setup); 85CLK_OF_DECLARE(tango4_clkgen, "sigma,tango4-clkgen", tango4_clkgen_setup);
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index d31055ae6ec6..af011974d4ec 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -924,6 +924,101 @@ static int clk_core_enable_lock(struct clk_core *core)
924} 924}
925 925
926/** 926/**
927 * clk_gate_restore_context - restore context for poweroff
928 * @hw: the clk_hw pointer of clock whose state is to be restored
929 *
930 * The clock gate restore context function enables or disables
931 * the gate clocks based on the enable_count. This is done in cases
932 * where the clock context is lost and based on the enable_count
933 * the clock either needs to be enabled/disabled. This
934 * helps restore the state of gate clocks.
935 */
936void clk_gate_restore_context(struct clk_hw *hw)
937{
938 struct clk_core *core = hw->core;
939
940 if (core->enable_count)
941 core->ops->enable(hw);
942 else
943 core->ops->disable(hw);
944}
945EXPORT_SYMBOL_GPL(clk_gate_restore_context);
946
947static int clk_core_save_context(struct clk_core *core)
948{
949 struct clk_core *child;
950 int ret = 0;
951
952 hlist_for_each_entry(child, &core->children, child_node) {
953 ret = clk_core_save_context(child);
954 if (ret < 0)
955 return ret;
956 }
957
958 if (core->ops && core->ops->save_context)
959 ret = core->ops->save_context(core->hw);
960
961 return ret;
962}
963
964static void clk_core_restore_context(struct clk_core *core)
965{
966 struct clk_core *child;
967
968 if (core->ops && core->ops->restore_context)
969 core->ops->restore_context(core->hw);
970
971 hlist_for_each_entry(child, &core->children, child_node)
972 clk_core_restore_context(child);
973}
974
975/**
976 * clk_save_context - save clock context for poweroff
977 *
978 * Saves the context of the clock register for powerstates in which the
979 * contents of the registers will be lost. Occurs deep within the suspend
980 * code. Returns 0 on success.
981 */
982int clk_save_context(void)
983{
984 struct clk_core *clk;
985 int ret;
986
987 hlist_for_each_entry(clk, &clk_root_list, child_node) {
988 ret = clk_core_save_context(clk);
989 if (ret < 0)
990 return ret;
991 }
992
993 hlist_for_each_entry(clk, &clk_orphan_list, child_node) {
994 ret = clk_core_save_context(clk);
995 if (ret < 0)
996 return ret;
997 }
998
999 return 0;
1000}
1001EXPORT_SYMBOL_GPL(clk_save_context);
1002
1003/**
1004 * clk_restore_context - restore clock context after poweroff
1005 *
1006 * Restore the saved clock context upon resume.
1007 *
1008 */
1009void clk_restore_context(void)
1010{
1011 struct clk_core *core;
1012
1013 hlist_for_each_entry(core, &clk_root_list, child_node)
1014 clk_core_restore_context(core);
1015
1016 hlist_for_each_entry(core, &clk_orphan_list, child_node)
1017 clk_core_restore_context(core);
1018}
1019EXPORT_SYMBOL_GPL(clk_restore_context);
1020
1021/**
927 * clk_enable - ungate a clock 1022 * clk_enable - ungate a clock
928 * @clk: the clk being ungated 1023 * @clk: the clk being ungated
929 * 1024 *
diff --git a/drivers/clk/davinci/psc.c b/drivers/clk/davinci/psc.c
index fffbed5e263b..5b69e24a224f 100644
--- a/drivers/clk/davinci/psc.c
+++ b/drivers/clk/davinci/psc.c
@@ -303,24 +303,6 @@ static int davinci_lpsc_clk_reset(struct clk *clk, bool reset)
303 return 0; 303 return 0;
304} 304}
305 305
306/*
307 * REVISIT: These exported functions can be removed after a non-DT lookup is
308 * added to the reset controller framework and the davinci-rproc driver is
309 * updated to use the generic reset controller framework.
310 */
311
312int davinci_clk_reset_assert(struct clk *clk)
313{
314 return davinci_lpsc_clk_reset(clk, true);
315}
316EXPORT_SYMBOL(davinci_clk_reset_assert);
317
318int davinci_clk_reset_deassert(struct clk *clk)
319{
320 return davinci_lpsc_clk_reset(clk, false);
321}
322EXPORT_SYMBOL(davinci_clk_reset_deassert);
323
324static int davinci_psc_reset_assert(struct reset_controller_dev *rcdev, 306static int davinci_psc_reset_assert(struct reset_controller_dev *rcdev,
325 unsigned long id) 307 unsigned long id)
326{ 308{
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
index becdb1dd21b5..30fad7ab0d88 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -21,6 +21,13 @@ config COMMON_CLK_HI3660
21 help 21 help
22 Build the clock driver for hi3660. 22 Build the clock driver for hi3660.
23 23
24config COMMON_CLK_HI3670
25 bool "Hi3670 Clock Driver"
26 depends on ARCH_HISI || COMPILE_TEST
27 default ARCH_HISI
28 help
29 Build the clock driver for hi3670.
30
24config COMMON_CLK_HI3798CV200 31config COMMON_CLK_HI3798CV200
25 tristate "Hi3798CV200 Clock Driver" 32 tristate "Hi3798CV200 Clock Driver"
26 depends on ARCH_HISI || COMPILE_TEST 33 depends on ARCH_HISI || COMPILE_TEST
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 2a714c0f9657..b2441b99f3d5 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
11obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o 11obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
12obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o 12obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
13obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o 13obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o
14obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o
14obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o 15obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
15obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o 16obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
16obj-$(CONFIG_RESET_HISI) += reset.o 17obj-$(CONFIG_RESET_HISI) += reset.o
diff --git a/drivers/clk/hisilicon/clk-hi3670.c b/drivers/clk/hisilicon/clk-hi3670.c
new file mode 100644
index 000000000000..fd8c837a6ea3
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3670.c
@@ -0,0 +1,1016 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd.
4 * Author: chenjun <chenjun14@huawei.com>
5 *
6 * Copyright (c) 2018, Linaro Ltd.
7 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
8 */
9
10#include <dt-bindings/clock/hi3670-clock.h>
11#include <linux/clk-provider.h>
12#include <linux/of_device.h>
13#include <linux/platform_device.h>
14#include "clk.h"
15
16static const struct hisi_fixed_rate_clock hi3670_fixed_rate_clks[] = {
17 { HI3670_CLKIN_SYS, "clkin_sys", NULL, 0, 19200000, },
18 { HI3670_CLKIN_REF, "clkin_ref", NULL, 0, 32764, },
19 { HI3670_CLK_FLL_SRC, "clk_fll_src", NULL, 0, 134400000, },
20 { HI3670_CLK_PPLL0, "clk_ppll0", NULL, 0, 1660000000, },
21 { HI3670_CLK_PPLL1, "clk_ppll1", NULL, 0, 1866000000, },
22 { HI3670_CLK_PPLL2, "clk_ppll2", NULL, 0, 1920000000, },
23 { HI3670_CLK_PPLL3, "clk_ppll3", NULL, 0, 1200000000, },
24 { HI3670_CLK_PPLL4, "clk_ppll4", NULL, 0, 900000000, },
25 { HI3670_CLK_PPLL6, "clk_ppll6", NULL, 0, 393216000, },
26 { HI3670_CLK_PPLL7, "clk_ppll7", NULL, 0, 1008000000, },
27 { HI3670_CLK_PPLL_PCIE, "clk_ppll_pcie", NULL, 0, 100000000, },
28 { HI3670_CLK_PCIEPLL_REV, "clk_pciepll_rev", NULL, 0, 100000000, },
29 { HI3670_CLK_SCPLL, "clk_scpll", NULL, 0, 245760000, },
30 { HI3670_PCLK, "pclk", NULL, 0, 20000000, },
31 { HI3670_CLK_UART0_DBG, "clk_uart0_dbg", NULL, 0, 19200000, },
32 { HI3670_CLK_UART6, "clk_uart6", NULL, 0, 19200000, },
33 { HI3670_OSC32K, "osc32k", NULL, 0, 32764, },
34 { HI3670_OSC19M, "osc19m", NULL, 0, 19200000, },
35 { HI3670_CLK_480M, "clk_480m", NULL, 0, 480000000, },
36 { HI3670_CLK_INVALID, "clk_invalid", NULL, 0, 10000000, },
37};
38
39/* crgctrl */
40static const struct hisi_fixed_factor_clock hi3670_crg_fixed_factor_clks[] = {
41 { HI3670_CLK_DIV_SYSBUS, "clk_div_sysbus", "clk_mux_sysbus",
42 1, 7, 0, },
43 { HI3670_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys",
44 1, 6, 0, },
45 { HI3670_CLK_SD_SYS, "clk_sd_sys", "clk_sd_sys_gt",
46 1, 6, 0, },
47 { HI3670_CLK_SDIO_SYS, "clk_sdio_sys", "clk_sdio_sys_gt",
48 1, 6, 0, },
49 { HI3670_CLK_DIV_A53HPM, "clk_div_a53hpm", "clk_a53hpm_andgt",
50 1, 4, 0, },
51 { HI3670_CLK_DIV_320M, "clk_div_320m", "clk_320m_pll_gt",
52 1, 5, 0, },
53 { HI3670_PCLK_GATE_UART0, "pclk_gate_uart0", "clk_mux_uartl",
54 1, 1, 0, },
55 { HI3670_CLK_FACTOR_UART0, "clk_factor_uart0", "clk_mux_uart0",
56 1, 1, 0, },
57 { HI3670_CLK_FACTOR_USB3PHY_PLL, "clk_factor_usb3phy_pll", "clk_ppll0",
58 1, 60, 0, },
59 { HI3670_CLK_GATE_ABB_USB, "clk_gate_abb_usb", "clk_gate_usb_tcxo_en",
60 1, 1, 0, },
61 { HI3670_CLK_GATE_UFSPHY_REF, "clk_gate_ufsphy_ref", "clkin_sys",
62 1, 1, 0, },
63 { HI3670_ICS_VOLT_HIGH, "ics_volt_high", "peri_volt_hold",
64 1, 1, 0, },
65 { HI3670_ICS_VOLT_MIDDLE, "ics_volt_middle", "peri_volt_middle",
66 1, 1, 0, },
67 { HI3670_VENC_VOLT_HOLD, "venc_volt_hold", "peri_volt_hold",
68 1, 1, 0, },
69 { HI3670_VDEC_VOLT_HOLD, "vdec_volt_hold", "peri_volt_hold",
70 1, 1, 0, },
71 { HI3670_EDC_VOLT_HOLD, "edc_volt_hold", "peri_volt_hold",
72 1, 1, 0, },
73 { HI3670_CLK_ISP_SNCLK_FAC, "clk_isp_snclk_fac", "clk_isp_snclk_angt",
74 1, 10, 0, },
75 { HI3670_CLK_FACTOR_RXDPHY, "clk_factor_rxdphy", "clk_andgt_rxdphy",
76 1, 6, 0, },
77};
78
79static const struct hisi_gate_clock hi3670_crgctrl_gate_sep_clks[] = {
80 { HI3670_PPLL1_EN_ACPU, "ppll1_en_acpu", "clk_ppll1",
81 CLK_SET_RATE_PARENT, 0x0, 0, 0, },
82 { HI3670_PPLL2_EN_ACPU, "ppll2_en_acpu", "clk_ppll2",
83 CLK_SET_RATE_PARENT, 0x0, 3, 0, },
84 { HI3670_PPLL3_EN_ACPU, "ppll3_en_acpu", "clk_ppll3",
85 CLK_SET_RATE_PARENT, 0x0, 27, 0, },
86 { HI3670_PPLL1_GT_CPU, "ppll1_gt_cpu", "clk_ppll1",
87 CLK_SET_RATE_PARENT, 0x460, 16, 0, },
88 { HI3670_PPLL2_GT_CPU, "ppll2_gt_cpu", "clk_ppll2",
89 CLK_SET_RATE_PARENT, 0x460, 18, 0, },
90 { HI3670_PPLL3_GT_CPU, "ppll3_gt_cpu", "clk_ppll3",
91 CLK_SET_RATE_PARENT, 0x460, 20, 0, },
92 { HI3670_CLK_GATE_PPLL2_MEDIA, "clk_gate_ppll2_media", "clk_ppll2",
93 CLK_SET_RATE_PARENT, 0x410, 27, 0, },
94 { HI3670_CLK_GATE_PPLL3_MEDIA, "clk_gate_ppll3_media", "clk_ppll3",
95 CLK_SET_RATE_PARENT, 0x410, 28, 0, },
96 { HI3670_CLK_GATE_PPLL4_MEDIA, "clk_gate_ppll4_media", "clk_ppll4",
97 CLK_SET_RATE_PARENT, 0x410, 26, 0, },
98 { HI3670_CLK_GATE_PPLL6_MEDIA, "clk_gate_ppll6_media", "clk_ppll6",
99 CLK_SET_RATE_PARENT, 0x410, 30, 0, },
100 { HI3670_CLK_GATE_PPLL7_MEDIA, "clk_gate_ppll7_media", "clk_ppll7",
101 CLK_SET_RATE_PARENT, 0x410, 29, 0, },
102 { HI3670_PCLK_GPIO0, "pclk_gpio0", "clk_div_cfgbus",
103 CLK_SET_RATE_PARENT, 0x10, 0, 0, },
104 { HI3670_PCLK_GPIO1, "pclk_gpio1", "clk_div_cfgbus",
105 CLK_SET_RATE_PARENT, 0x10, 1, 0, },
106 { HI3670_PCLK_GPIO2, "pclk_gpio2", "clk_div_cfgbus",
107 CLK_SET_RATE_PARENT, 0x10, 2, 0, },
108 { HI3670_PCLK_GPIO3, "pclk_gpio3", "clk_div_cfgbus",
109 CLK_SET_RATE_PARENT, 0x10, 3, 0, },
110 { HI3670_PCLK_GPIO4, "pclk_gpio4", "clk_div_cfgbus",
111 CLK_SET_RATE_PARENT, 0x10, 4, 0, },
112 { HI3670_PCLK_GPIO5, "pclk_gpio5", "clk_div_cfgbus",
113 CLK_SET_RATE_PARENT, 0x10, 5, 0, },
114 { HI3670_PCLK_GPIO6, "pclk_gpio6", "clk_div_cfgbus",
115 CLK_SET_RATE_PARENT, 0x10, 6, 0, },
116 { HI3670_PCLK_GPIO7, "pclk_gpio7", "clk_div_cfgbus",
117 CLK_SET_RATE_PARENT, 0x10, 7, 0, },
118 { HI3670_PCLK_GPIO8, "pclk_gpio8", "clk_div_cfgbus",
119 CLK_SET_RATE_PARENT, 0x10, 8, 0, },
120 { HI3670_PCLK_GPIO9, "pclk_gpio9", "clk_div_cfgbus",
121 CLK_SET_RATE_PARENT, 0x10, 9, 0, },
122 { HI3670_PCLK_GPIO10, "pclk_gpio10", "clk_div_cfgbus",
123 CLK_SET_RATE_PARENT, 0x10, 10, 0, },
124 { HI3670_PCLK_GPIO11, "pclk_gpio11", "clk_div_cfgbus",
125 CLK_SET_RATE_PARENT, 0x10, 11, 0, },
126 { HI3670_PCLK_GPIO12, "pclk_gpio12", "clk_div_cfgbus",
127 CLK_SET_RATE_PARENT, 0x10, 12, 0, },
128 { HI3670_PCLK_GPIO13, "pclk_gpio13", "clk_div_cfgbus",
129 CLK_SET_RATE_PARENT, 0x10, 13, 0, },
130 { HI3670_PCLK_GPIO14, "pclk_gpio14", "clk_div_cfgbus",
131 CLK_SET_RATE_PARENT, 0x10, 14, 0, },
132 { HI3670_PCLK_GPIO15, "pclk_gpio15", "clk_div_cfgbus",
133 CLK_SET_RATE_PARENT, 0x10, 15, 0, },
134 { HI3670_PCLK_GPIO16, "pclk_gpio16", "clk_div_cfgbus",
135 CLK_SET_RATE_PARENT, 0x10, 16, 0, },
136 { HI3670_PCLK_GPIO17, "pclk_gpio17", "clk_div_cfgbus",
137 CLK_SET_RATE_PARENT, 0x10, 17, 0, },
138 { HI3670_PCLK_GPIO20, "pclk_gpio20", "clk_div_cfgbus",
139 CLK_SET_RATE_PARENT, 0x10, 20, 0, },
140 { HI3670_PCLK_GPIO21, "pclk_gpio21", "clk_div_cfgbus",
141 CLK_SET_RATE_PARENT, 0x10, 21, 0, },
142 { HI3670_PCLK_GATE_DSI0, "pclk_gate_dsi0", "clk_div_cfgbus",
143 CLK_SET_RATE_PARENT, 0x50, 28, 0, },
144 { HI3670_PCLK_GATE_DSI1, "pclk_gate_dsi1", "clk_div_cfgbus",
145 CLK_SET_RATE_PARENT, 0x50, 29, 0, },
146 { HI3670_HCLK_GATE_USB3OTG, "hclk_gate_usb3otg", "clk_div_sysbus",
147 CLK_SET_RATE_PARENT, 0x0, 25, 0, },
148 { HI3670_ACLK_GATE_USB3DVFS, "aclk_gate_usb3dvfs", "autodiv_emmc0bus",
149 CLK_SET_RATE_PARENT, 0x40, 1, 0, },
150 { HI3670_HCLK_GATE_SDIO, "hclk_gate_sdio", "clk_div_sysbus",
151 CLK_SET_RATE_PARENT, 0x0, 21, 0, },
152 { HI3670_PCLK_GATE_PCIE_SYS, "pclk_gate_pcie_sys", "clk_div_mmc1bus",
153 CLK_SET_RATE_PARENT, 0x420, 7, 0, },
154 { HI3670_PCLK_GATE_PCIE_PHY, "pclk_gate_pcie_phy", "pclk_gate_mmc1_pcie",
155 CLK_SET_RATE_PARENT, 0x420, 9, 0, },
156 { HI3670_PCLK_GATE_MMC1_PCIE, "pclk_gate_mmc1_pcie", "pclk_div_mmc1_pcie",
157 CLK_SET_RATE_PARENT, 0x30, 12, 0, },
158 { HI3670_PCLK_GATE_MMC0_IOC, "pclk_gate_mmc0_ioc", "clk_div_mmc0bus",
159 CLK_SET_RATE_PARENT, 0x40, 13, 0, },
160 { HI3670_PCLK_GATE_MMC1_IOC, "pclk_gate_mmc1_ioc", "clk_div_mmc1bus",
161 CLK_SET_RATE_PARENT, 0x420, 21, 0, },
162 { HI3670_CLK_GATE_DMAC, "clk_gate_dmac", "clk_div_sysbus",
163 CLK_SET_RATE_PARENT, 0x30, 1, 0, },
164 { HI3670_CLK_GATE_VCODECBUS2DDR, "clk_gate_vcodecbus2ddr", "clk_div_vcodecbus",
165 CLK_SET_RATE_PARENT, 0x0, 5, 0, },
166 { HI3670_CLK_CCI400_BYPASS, "clk_cci400_bypass", "clk_ddrc_freq",
167 CLK_SET_RATE_PARENT, 0x22C, 28, 0, },
168 { HI3670_CLK_GATE_CCI400, "clk_gate_cci400", "clk_ddrc_freq",
169 CLK_SET_RATE_PARENT, 0x50, 14, 0, },
170 { HI3670_CLK_GATE_SD, "clk_gate_sd", "clk_mux_sd_sys",
171 CLK_SET_RATE_PARENT, 0x40, 17, 0, },
172 { HI3670_HCLK_GATE_SD, "hclk_gate_sd", "clk_div_sysbus",
173 CLK_SET_RATE_PARENT, 0x0, 30, 0, },
174 { HI3670_CLK_GATE_SDIO, "clk_gate_sdio", "clk_mux_sdio_sys",
175 CLK_SET_RATE_PARENT, 0x40, 19, 0, },
176 { HI3670_CLK_GATE_A57HPM, "clk_gate_a57hpm", "clk_div_a53hpm",
177 CLK_SET_RATE_PARENT, 0x050, 9, 0, },
178 { HI3670_CLK_GATE_A53HPM, "clk_gate_a53hpm", "clk_div_a53hpm",
179 CLK_SET_RATE_PARENT, 0x050, 13, 0, },
180 { HI3670_CLK_GATE_PA_A53, "clk_gate_pa_a53", "clk_div_a53hpm",
181 CLK_SET_RATE_PARENT, 0x480, 10, 0, },
182 { HI3670_CLK_GATE_PA_A57, "clk_gate_pa_a57", "clk_div_a53hpm",
183 CLK_SET_RATE_PARENT, 0x480, 9, 0, },
184 { HI3670_CLK_GATE_PA_G3D, "clk_gate_pa_g3d", "clk_div_a53hpm",
185 CLK_SET_RATE_PARENT, 0x480, 15, 0, },
186 { HI3670_CLK_GATE_GPUHPM, "clk_gate_gpuhpm", "clk_div_a53hpm",
187 CLK_SET_RATE_PARENT, 0x050, 15, 0, },
188 { HI3670_CLK_GATE_PERIHPM, "clk_gate_perihpm", "clk_div_a53hpm",
189 CLK_SET_RATE_PARENT, 0x050, 12, 0, },
190 { HI3670_CLK_GATE_AOHPM, "clk_gate_aohpm", "clk_div_a53hpm",
191 CLK_SET_RATE_PARENT, 0x050, 11, 0, },
192 { HI3670_CLK_GATE_UART1, "clk_gate_uart1", "clk_mux_uarth",
193 CLK_SET_RATE_PARENT, 0x20, 11, 0, },
194 { HI3670_CLK_GATE_UART4, "clk_gate_uart4", "clk_mux_uarth",
195 CLK_SET_RATE_PARENT, 0x20, 14, 0, },
196 { HI3670_PCLK_GATE_UART1, "pclk_gate_uart1", "clk_mux_uarth",
197 CLK_SET_RATE_PARENT, 0x20, 11, 0, },
198 { HI3670_PCLK_GATE_UART4, "pclk_gate_uart4", "clk_mux_uarth",
199 CLK_SET_RATE_PARENT, 0x20, 14, 0, },
200 { HI3670_CLK_GATE_UART2, "clk_gate_uart2", "clk_mux_uartl",
201 CLK_SET_RATE_PARENT, 0x20, 12, 0, },
202 { HI3670_CLK_GATE_UART5, "clk_gate_uart5", "clk_mux_uartl",
203 CLK_SET_RATE_PARENT, 0x20, 15, 0, },
204 { HI3670_PCLK_GATE_UART2, "pclk_gate_uart2", "clk_mux_uartl",
205 CLK_SET_RATE_PARENT, 0x20, 12, 0, },
206 { HI3670_PCLK_GATE_UART5, "pclk_gate_uart5", "clk_mux_uartl",
207 CLK_SET_RATE_PARENT, 0x20, 15, 0, },
208 { HI3670_CLK_GATE_UART0, "clk_gate_uart0", "clk_mux_uart0",
209 CLK_SET_RATE_PARENT, 0x20, 10, 0, },
210 { HI3670_CLK_GATE_I2C3, "clk_gate_i2c3", "clk_mux_i2c",
211 CLK_SET_RATE_PARENT, 0x20, 7, 0, },
212 { HI3670_CLK_GATE_I2C4, "clk_gate_i2c4", "clk_mux_i2c",
213 CLK_SET_RATE_PARENT, 0x20, 27, 0, },
214 { HI3670_CLK_GATE_I2C7, "clk_gate_i2c7", "clk_mux_i2c",
215 CLK_SET_RATE_PARENT, 0x10, 31, 0, },
216 { HI3670_PCLK_GATE_I2C3, "pclk_gate_i2c3", "clk_mux_i2c",
217 CLK_SET_RATE_PARENT, 0x20, 7, 0, },
218 { HI3670_PCLK_GATE_I2C4, "pclk_gate_i2c4", "clk_mux_i2c",
219 CLK_SET_RATE_PARENT, 0x20, 27, 0, },
220 { HI3670_PCLK_GATE_I2C7, "pclk_gate_i2c7", "clk_mux_i2c",
221 CLK_SET_RATE_PARENT, 0x10, 31, 0, },
222 { HI3670_CLK_GATE_SPI1, "clk_gate_spi1", "clk_mux_spi",
223 CLK_SET_RATE_PARENT, 0x20, 9, 0, },
224 { HI3670_CLK_GATE_SPI4, "clk_gate_spi4", "clk_mux_spi",
225 CLK_SET_RATE_PARENT, 0x40, 4, 0, },
226 { HI3670_PCLK_GATE_SPI1, "pclk_gate_spi1", "clk_mux_spi",
227 CLK_SET_RATE_PARENT, 0x20, 9, 0, },
228 { HI3670_PCLK_GATE_SPI4, "pclk_gate_spi4", "clk_mux_spi",
229 CLK_SET_RATE_PARENT, 0x40, 4, 0, },
230 { HI3670_CLK_GATE_USB3OTG_REF, "clk_gate_usb3otg_ref", "clkin_sys",
231 CLK_SET_RATE_PARENT, 0x40, 0, 0, },
232 { HI3670_CLK_GATE_USB2PHY_REF, "clk_gate_usb2phy_ref", "clkin_sys",
233 CLK_SET_RATE_PARENT, 0x410, 19, 0, },
234 { HI3670_CLK_GATE_PCIEAUX, "clk_gate_pcieaux", "clkin_sys",
235 CLK_SET_RATE_PARENT, 0x420, 8, 0, },
236 { HI3670_ACLK_GATE_PCIE, "aclk_gate_pcie", "clk_gate_mmc1_pcieaxi",
237 CLK_SET_RATE_PARENT, 0x420, 5, 0, },
238 { HI3670_CLK_GATE_MMC1_PCIEAXI, "clk_gate_mmc1_pcieaxi", "clk_div_pcieaxi",
239 CLK_SET_RATE_PARENT, 0x050, 4, 0, },
240 { HI3670_CLK_GATE_PCIEPHY_REF, "clk_gate_pciephy_ref", "clk_ppll_pcie",
241 CLK_SET_RATE_PARENT, 0x470, 14, 0, },
242 { HI3670_CLK_GATE_PCIE_DEBOUNCE, "clk_gate_pcie_debounce", "clk_ppll_pcie",
243 CLK_SET_RATE_PARENT, 0x470, 12, 0, },
244 { HI3670_CLK_GATE_PCIEIO, "clk_gate_pcieio", "clk_ppll_pcie",
245 CLK_SET_RATE_PARENT, 0x470, 13, 0, },
246 { HI3670_CLK_GATE_PCIE_HP, "clk_gate_pcie_hp", "clk_ppll_pcie",
247 CLK_SET_RATE_PARENT, 0x470, 15, 0, },
248 { HI3670_CLK_GATE_AO_ASP, "clk_gate_ao_asp", "clk_div_ao_asp",
249 CLK_SET_RATE_PARENT, 0x0, 26, 0, },
250 { HI3670_PCLK_GATE_PCTRL, "pclk_gate_pctrl", "clk_div_ptp",
251 CLK_SET_RATE_PARENT, 0x20, 31, 0, },
252 { HI3670_CLK_CSI_TRANS_GT, "clk_csi_trans_gt", "clk_div_csi_trans",
253 CLK_SET_RATE_PARENT, 0x30, 24, 0, },
254 { HI3670_CLK_DSI_TRANS_GT, "clk_dsi_trans_gt", "clk_div_dsi_trans",
255 CLK_SET_RATE_PARENT, 0x30, 25, 0, },
256 { HI3670_CLK_GATE_PWM, "clk_gate_pwm", "clk_div_ptp",
257 CLK_SET_RATE_PARENT, 0x20, 0, 0, },
258 { HI3670_ABB_AUDIO_EN0, "abb_audio_en0", "clk_gate_abb_192",
259 CLK_SET_RATE_PARENT, 0x30, 8, 0, },
260 { HI3670_ABB_AUDIO_EN1, "abb_audio_en1", "clk_gate_abb_192",
261 CLK_SET_RATE_PARENT, 0x30, 9, 0, },
262 { HI3670_ABB_AUDIO_GT_EN0, "abb_audio_gt_en0", "abb_audio_en0",
263 CLK_SET_RATE_PARENT, 0x30, 19, 0, },
264 { HI3670_ABB_AUDIO_GT_EN1, "abb_audio_gt_en1", "abb_audio_en1",
265 CLK_SET_RATE_PARENT, 0x40, 20, 0, },
266 { HI3670_CLK_GATE_DP_AUDIO_PLL_AO, "clk_gate_dp_audio_pll_ao", "clkdiv_dp_audio_pll_ao",
267 CLK_SET_RATE_PARENT, 0x00, 13, 0, },
268 { HI3670_PERI_VOLT_HOLD, "peri_volt_hold", "clkin_sys",
269 CLK_SET_RATE_PARENT, 0, 1, 0, },
270 { HI3670_PERI_VOLT_MIDDLE, "peri_volt_middle", "clkin_sys",
271 CLK_SET_RATE_PARENT, 0, 1, 0, },
272 { HI3670_CLK_GATE_ISP_SNCLK0, "clk_gate_isp_snclk0", "clk_isp_snclk_mux0",
273 CLK_SET_RATE_PARENT, 0x50, 16, 0, },
274 { HI3670_CLK_GATE_ISP_SNCLK1, "clk_gate_isp_snclk1", "clk_isp_snclk_mux1",
275 CLK_SET_RATE_PARENT, 0x50, 17, 0, },
276 { HI3670_CLK_GATE_ISP_SNCLK2, "clk_gate_isp_snclk2", "clk_isp_snclk_mux2",
277 CLK_SET_RATE_PARENT, 0x50, 18, 0, },
278 { HI3670_CLK_GATE_RXDPHY0_CFG, "clk_gate_rxdphy0_cfg", "clk_mux_rxdphy_cfg",
279 CLK_SET_RATE_PARENT, 0x030, 20, 0, },
280 { HI3670_CLK_GATE_RXDPHY1_CFG, "clk_gate_rxdphy1_cfg", "clk_mux_rxdphy_cfg",
281 CLK_SET_RATE_PARENT, 0x030, 21, 0, },
282 { HI3670_CLK_GATE_RXDPHY2_CFG, "clk_gate_rxdphy2_cfg", "clk_mux_rxdphy_cfg",
283 CLK_SET_RATE_PARENT, 0x030, 22, 0, },
284 { HI3670_CLK_GATE_TXDPHY0_CFG, "clk_gate_txdphy0_cfg", "clkin_sys",
285 CLK_SET_RATE_PARENT, 0x030, 28, 0, },
286 { HI3670_CLK_GATE_TXDPHY0_REF, "clk_gate_txdphy0_ref", "clkin_sys",
287 CLK_SET_RATE_PARENT, 0x030, 29, 0, },
288 { HI3670_CLK_GATE_TXDPHY1_CFG, "clk_gate_txdphy1_cfg", "clkin_sys",
289 CLK_SET_RATE_PARENT, 0x030, 30, 0, },
290 { HI3670_CLK_GATE_TXDPHY1_REF, "clk_gate_txdphy1_ref", "clkin_sys",
291 CLK_SET_RATE_PARENT, 0x030, 31, 0, },
292 { HI3670_CLK_GATE_MEDIA_TCXO, "clk_gate_media_tcxo", "clkin_sys",
293 CLK_SET_RATE_PARENT, 0x40, 6, 0, },
294};
295
296static const struct hisi_gate_clock hi3670_crgctrl_gate_clks[] = {
297 { HI3670_AUTODIV_SYSBUS, "autodiv_sysbus", "clk_div_sysbus",
298 CLK_SET_RATE_PARENT, 0x404, 5, CLK_GATE_HIWORD_MASK, 0, },
299 { HI3670_AUTODIV_EMMC0BUS, "autodiv_emmc0bus", "autodiv_sysbus",
300 CLK_SET_RATE_PARENT, 0x404, 1, CLK_GATE_HIWORD_MASK, 0, },
301 { HI3670_PCLK_ANDGT_MMC1_PCIE, "pclk_andgt_mmc1_pcie", "clk_div_320m",
302 CLK_SET_RATE_PARENT, 0xf8, 13, CLK_GATE_HIWORD_MASK, 0, },
303 { HI3670_CLK_GATE_VCODECBUS_GT, "clk_gate_vcodecbus_gt", "clk_mux_vcodecbus",
304 CLK_SET_RATE_PARENT, 0x0F0, 8, CLK_GATE_HIWORD_MASK, 0, },
305 { HI3670_CLK_ANDGT_SD, "clk_andgt_sd", "clk_mux_sd_pll",
306 CLK_SET_RATE_PARENT, 0xF4, 3, CLK_GATE_HIWORD_MASK, 0, },
307 { HI3670_CLK_SD_SYS_GT, "clk_sd_sys_gt", "clkin_sys",
308 CLK_SET_RATE_PARENT, 0xF4, 5, CLK_GATE_HIWORD_MASK, 0, },
309 { HI3670_CLK_ANDGT_SDIO, "clk_andgt_sdio", "clk_mux_sdio_pll",
310 CLK_SET_RATE_PARENT, 0xF4, 8, CLK_GATE_HIWORD_MASK, 0, },
311 { HI3670_CLK_SDIO_SYS_GT, "clk_sdio_sys_gt", "clkin_sys",
312 CLK_SET_RATE_PARENT, 0xF4, 6, CLK_GATE_HIWORD_MASK, 0, },
313 { HI3670_CLK_A53HPM_ANDGT, "clk_a53hpm_andgt", "clk_mux_a53hpm",
314 CLK_SET_RATE_PARENT, 0x0F4, 7, CLK_GATE_HIWORD_MASK, 0, },
315 { HI3670_CLK_320M_PLL_GT, "clk_320m_pll_gt", "clk_mux_320m",
316 CLK_SET_RATE_PARENT, 0xF8, 10, CLK_GATE_HIWORD_MASK, 0, },
317 { HI3670_CLK_ANDGT_UARTH, "clk_andgt_uarth", "clk_div_320m",
318 CLK_SET_RATE_PARENT, 0xF4, 11, CLK_GATE_HIWORD_MASK, 0, },
319 { HI3670_CLK_ANDGT_UARTL, "clk_andgt_uartl", "clk_div_320m",
320 CLK_SET_RATE_PARENT, 0xF4, 10, CLK_GATE_HIWORD_MASK, 0, },
321 { HI3670_CLK_ANDGT_UART0, "clk_andgt_uart0", "clk_div_320m",
322 CLK_SET_RATE_PARENT, 0xF4, 9, CLK_GATE_HIWORD_MASK, 0, },
323 { HI3670_CLK_ANDGT_SPI, "clk_andgt_spi", "clk_div_320m",
324 CLK_SET_RATE_PARENT, 0xF4, 13, CLK_GATE_HIWORD_MASK, 0, },
325 { HI3670_CLK_ANDGT_PCIEAXI, "clk_andgt_pcieaxi", "clk_mux_pcieaxi",
326 CLK_SET_RATE_PARENT, 0xfc, 15, CLK_GATE_HIWORD_MASK, 0, },
327 { HI3670_CLK_DIV_AO_ASP_GT, "clk_div_ao_asp_gt", "clk_mux_ao_asp",
328 CLK_SET_RATE_PARENT, 0xF4, 4, CLK_GATE_HIWORD_MASK, 0, },
329 { HI3670_CLK_GATE_CSI_TRANS, "clk_gate_csi_trans", "clk_ppll2",
330 CLK_SET_RATE_PARENT, 0xF4, 14, CLK_GATE_HIWORD_MASK, 0, },
331 { HI3670_CLK_GATE_DSI_TRANS, "clk_gate_dsi_trans", "clk_ppll2",
332 CLK_SET_RATE_PARENT, 0xF4, 1, CLK_GATE_HIWORD_MASK, 0, },
333 { HI3670_CLK_ANDGT_PTP, "clk_andgt_ptp", "clk_div_320m",
334 CLK_SET_RATE_PARENT, 0xF8, 5, CLK_GATE_HIWORD_MASK, 0, },
335 { HI3670_CLK_ANDGT_OUT0, "clk_andgt_out0", "clk_ppll0",
336 CLK_SET_RATE_PARENT, 0xF0, 10, CLK_GATE_HIWORD_MASK, 0, },
337 { HI3670_CLK_ANDGT_OUT1, "clk_andgt_out1", "clk_ppll0",
338 CLK_SET_RATE_PARENT, 0xF0, 11, CLK_GATE_HIWORD_MASK, 0, },
339 { HI3670_CLKGT_DP_AUDIO_PLL_AO, "clkgt_dp_audio_pll_ao", "clk_ppll6",
340 CLK_SET_RATE_PARENT, 0xF8, 15, CLK_GATE_HIWORD_MASK, 0, },
341 { HI3670_CLK_ANDGT_VDEC, "clk_andgt_vdec", "clk_mux_vdec",
342 CLK_SET_RATE_PARENT, 0xF0, 13, CLK_GATE_HIWORD_MASK, 0, },
343 { HI3670_CLK_ANDGT_VENC, "clk_andgt_venc", "clk_mux_venc",
344 CLK_SET_RATE_PARENT, 0xF0, 9, CLK_GATE_HIWORD_MASK, 0, },
345 { HI3670_CLK_ISP_SNCLK_ANGT, "clk_isp_snclk_angt", "clk_div_a53hpm",
346 CLK_SET_RATE_PARENT, 0x108, 2, CLK_GATE_HIWORD_MASK, 0, },
347 { HI3670_CLK_ANDGT_RXDPHY, "clk_andgt_rxdphy", "clk_div_a53hpm",
348 CLK_SET_RATE_PARENT, 0x0F0, 12, CLK_GATE_HIWORD_MASK, 0, },
349 { HI3670_CLK_ANDGT_ICS, "clk_andgt_ics", "clk_mux_ics",
350 CLK_SET_RATE_PARENT, 0xf0, 14, CLK_GATE_HIWORD_MASK, 0, },
351 { HI3670_AUTODIV_DMABUS, "autodiv_dmabus", "autodiv_sysbus",
352 CLK_SET_RATE_PARENT, 0x404, 3, CLK_GATE_HIWORD_MASK, 0, },
353};
354
355static const char *const
356clk_mux_sysbus_p[] = { "clk_ppll1", "clk_ppll0", };
357static const char *const
358clk_mux_vcodecbus_p[] = { "clk_invalid", "clk_ppll4", "clk_ppll0",
359 "clk_invalid", "clk_ppll2", "clk_invalid",
360 "clk_invalid", "clk_invalid", "clk_ppll3",
361 "clk_invalid", "clk_invalid", "clk_invalid",
362 "clk_invalid", "clk_invalid", "clk_invalid",
363 "clk_invalid", };
364static const char *const
365clk_mux_sd_sys_p[] = { "clk_sd_sys", "clk_div_sd", };
366static const char *const
367clk_mux_sd_pll_p[] = { "clk_ppll0", "clk_ppll3", "clk_ppll2", "clk_ppll2", };
368static const char *const
369clk_mux_sdio_sys_p[] = { "clk_sdio_sys", "clk_div_sdio", };
370static const char *const
371clk_mux_sdio_pll_p[] = { "clk_ppll0", "clk_ppll3", "clk_ppll2", "clk_ppll2", };
372static const char *const
373clk_mux_a53hpm_p[] = { "clk_ppll0", "clk_ppll2", };
374static const char *const
375clk_mux_320m_p[] = { "clk_ppll2", "clk_ppll0", };
376static const char *const
377clk_mux_uarth_p[] = { "clkin_sys", "clk_div_uarth", };
378static const char *const
379clk_mux_uartl_p[] = { "clkin_sys", "clk_div_uartl", };
380static const char *const
381clk_mux_uart0_p[] = { "clkin_sys", "clk_div_uart0", };
382static const char *const
383clk_mux_i2c_p[] = { "clkin_sys", "clk_div_i2c", };
384static const char *const
385clk_mux_spi_p[] = { "clkin_sys", "clk_div_spi", };
386static const char *const
387clk_mux_pcieaxi_p[] = { "clkin_sys", "clk_ppll0", };
388static const char *const
389clk_mux_ao_asp_p[] = { "clk_ppll2", "clk_ppll3", };
390static const char *const
391clk_mux_vdec_p[] = { "clk_invalid", "clk_ppll4", "clk_ppll0", "clk_invalid",
392 "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
393 "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
394 "clk_invalid", "clk_invalid", "clk_invalid",
395 "clk_invalid", };
396static const char *const
397clk_mux_venc_p[] = { "clk_invalid", "clk_ppll4", "clk_ppll0", "clk_invalid",
398 "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
399 "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
400 "clk_invalid", "clk_invalid", "clk_invalid",
401 "clk_invalid", };
402static const char *const
403clk_isp_snclk_mux0_p[] = { "clkin_sys", "clk_isp_snclk_div0", };
404static const char *const
405clk_isp_snclk_mux1_p[] = { "clkin_sys", "clk_isp_snclk_div1", };
406static const char *const
407clk_isp_snclk_mux2_p[] = { "clkin_sys", "clk_isp_snclk_div2", };
408static const char *const
409clk_mux_rxdphy_cfg_p[] = { "clk_factor_rxdphy", "clkin_sys", };
410static const char *const
411clk_mux_ics_p[] = { "clk_invalid", "clk_ppll4", "clk_ppll0", "clk_invalid",
412 "clk_ppll2", "clk_invalid", "clk_invalid", "clk_invalid",
413 "clk_ppll3", "clk_invalid", "clk_invalid", "clk_invalid",
414 "clk_invalid", "clk_invalid", "clk_invalid",
415 "clk_invalid", };
416
417static const struct hisi_mux_clock hi3670_crgctrl_mux_clks[] = {
418 { HI3670_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sysbus_p,
419 ARRAY_SIZE(clk_mux_sysbus_p), CLK_SET_RATE_PARENT,
420 0xAC, 0, 1, CLK_MUX_HIWORD_MASK, },
421 { HI3670_CLK_MUX_VCODECBUS, "clk_mux_vcodecbus", clk_mux_vcodecbus_p,
422 ARRAY_SIZE(clk_mux_vcodecbus_p), CLK_SET_RATE_PARENT,
423 0x0C8, 0, 4, CLK_MUX_HIWORD_MASK, },
424 { HI3670_CLK_MUX_SD_SYS, "clk_mux_sd_sys", clk_mux_sd_sys_p,
425 ARRAY_SIZE(clk_mux_sd_sys_p), CLK_SET_RATE_PARENT,
426 0x0B8, 6, 1, CLK_MUX_HIWORD_MASK, },
427 { HI3670_CLK_MUX_SD_PLL, "clk_mux_sd_pll", clk_mux_sd_pll_p,
428 ARRAY_SIZE(clk_mux_sd_pll_p), CLK_SET_RATE_PARENT,
429 0x0B8, 4, 2, CLK_MUX_HIWORD_MASK, },
430 { HI3670_CLK_MUX_SDIO_SYS, "clk_mux_sdio_sys", clk_mux_sdio_sys_p,
431 ARRAY_SIZE(clk_mux_sdio_sys_p), CLK_SET_RATE_PARENT,
432 0x0C0, 6, 1, CLK_MUX_HIWORD_MASK, },
433 { HI3670_CLK_MUX_SDIO_PLL, "clk_mux_sdio_pll", clk_mux_sdio_pll_p,
434 ARRAY_SIZE(clk_mux_sdio_pll_p), CLK_SET_RATE_PARENT,
435 0x0C0, 4, 2, CLK_MUX_HIWORD_MASK, },
436 { HI3670_CLK_MUX_A53HPM, "clk_mux_a53hpm", clk_mux_a53hpm_p,
437 ARRAY_SIZE(clk_mux_a53hpm_p), CLK_SET_RATE_PARENT,
438 0x0D4, 9, 1, CLK_MUX_HIWORD_MASK, },
439 { HI3670_CLK_MUX_320M, "clk_mux_320m", clk_mux_320m_p,
440 ARRAY_SIZE(clk_mux_320m_p), CLK_SET_RATE_PARENT,
441 0x100, 0, 1, CLK_MUX_HIWORD_MASK, },
442 { HI3670_CLK_MUX_UARTH, "clk_mux_uarth", clk_mux_uarth_p,
443 ARRAY_SIZE(clk_mux_uarth_p), CLK_SET_RATE_PARENT,
444 0xAC, 4, 1, CLK_MUX_HIWORD_MASK, },
445 { HI3670_CLK_MUX_UARTL, "clk_mux_uartl", clk_mux_uartl_p,
446 ARRAY_SIZE(clk_mux_uartl_p), CLK_SET_RATE_PARENT,
447 0xAC, 3, 1, CLK_MUX_HIWORD_MASK, },
448 { HI3670_CLK_MUX_UART0, "clk_mux_uart0", clk_mux_uart0_p,
449 ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT,
450 0xAC, 2, 1, CLK_MUX_HIWORD_MASK, },
451 { HI3670_CLK_MUX_I2C, "clk_mux_i2c", clk_mux_i2c_p,
452 ARRAY_SIZE(clk_mux_i2c_p), CLK_SET_RATE_PARENT,
453 0xAC, 13, 1, CLK_MUX_HIWORD_MASK, },
454 { HI3670_CLK_MUX_SPI, "clk_mux_spi", clk_mux_spi_p,
455 ARRAY_SIZE(clk_mux_spi_p), CLK_SET_RATE_PARENT,
456 0xAC, 8, 1, CLK_MUX_HIWORD_MASK, },
457 { HI3670_CLK_MUX_PCIEAXI, "clk_mux_pcieaxi", clk_mux_pcieaxi_p,
458 ARRAY_SIZE(clk_mux_pcieaxi_p), CLK_SET_RATE_PARENT,
459 0xb4, 5, 1, CLK_MUX_HIWORD_MASK, },
460 { HI3670_CLK_MUX_AO_ASP, "clk_mux_ao_asp", clk_mux_ao_asp_p,
461 ARRAY_SIZE(clk_mux_ao_asp_p), CLK_SET_RATE_PARENT,
462 0x100, 6, 1, CLK_MUX_HIWORD_MASK, },
463 { HI3670_CLK_MUX_VDEC, "clk_mux_vdec", clk_mux_vdec_p,
464 ARRAY_SIZE(clk_mux_vdec_p), CLK_SET_RATE_PARENT,
465 0xC8, 8, 4, CLK_MUX_HIWORD_MASK, },
466 { HI3670_CLK_MUX_VENC, "clk_mux_venc", clk_mux_venc_p,
467 ARRAY_SIZE(clk_mux_venc_p), CLK_SET_RATE_PARENT,
468 0xC8, 4, 4, CLK_MUX_HIWORD_MASK, },
469 { HI3670_CLK_ISP_SNCLK_MUX0, "clk_isp_snclk_mux0", clk_isp_snclk_mux0_p,
470 ARRAY_SIZE(clk_isp_snclk_mux0_p), CLK_SET_RATE_PARENT,
471 0x108, 3, 1, CLK_MUX_HIWORD_MASK, },
472 { HI3670_CLK_ISP_SNCLK_MUX1, "clk_isp_snclk_mux1", clk_isp_snclk_mux1_p,
473 ARRAY_SIZE(clk_isp_snclk_mux1_p), CLK_SET_RATE_PARENT,
474 0x10C, 13, 1, CLK_MUX_HIWORD_MASK, },
475 { HI3670_CLK_ISP_SNCLK_MUX2, "clk_isp_snclk_mux2", clk_isp_snclk_mux2_p,
476 ARRAY_SIZE(clk_isp_snclk_mux2_p), CLK_SET_RATE_PARENT,
477 0x10C, 10, 1, CLK_MUX_HIWORD_MASK, },
478 { HI3670_CLK_MUX_RXDPHY_CFG, "clk_mux_rxdphy_cfg", clk_mux_rxdphy_cfg_p,
479 ARRAY_SIZE(clk_mux_rxdphy_cfg_p), CLK_SET_RATE_PARENT,
480 0x0C4, 8, 1, CLK_MUX_HIWORD_MASK, },
481 { HI3670_CLK_MUX_ICS, "clk_mux_ics", clk_mux_ics_p,
482 ARRAY_SIZE(clk_mux_ics_p), CLK_SET_RATE_PARENT,
483 0xc8, 12, 4, CLK_MUX_HIWORD_MASK, },
484};
485
486static const struct hisi_divider_clock hi3670_crgctrl_divider_clks[] = {
487 { HI3670_CLK_DIV_CFGBUS, "clk_div_cfgbus", "clk_div_sysbus",
488 CLK_SET_RATE_PARENT, 0xEC, 0, 2, CLK_DIVIDER_HIWORD_MASK, 0, },
489 { HI3670_CLK_DIV_MMC0BUS, "clk_div_mmc0bus", "autodiv_emmc0bus",
490 CLK_SET_RATE_PARENT, 0x0EC, 2, 1, CLK_DIVIDER_HIWORD_MASK, 0, },
491 { HI3670_CLK_DIV_MMC1BUS, "clk_div_mmc1bus", "clk_div_sysbus",
492 CLK_SET_RATE_PARENT, 0x0EC, 3, 1, CLK_DIVIDER_HIWORD_MASK, 0, },
493 { HI3670_PCLK_DIV_MMC1_PCIE, "pclk_div_mmc1_pcie", "pclk_andgt_mmc1_pcie",
494 CLK_SET_RATE_PARENT, 0xb4, 6, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
495 { HI3670_CLK_DIV_VCODECBUS, "clk_div_vcodecbus", "clk_gate_vcodecbus_gt",
496 CLK_SET_RATE_PARENT, 0x0BC, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
497 { HI3670_CLK_DIV_SD, "clk_div_sd", "clk_andgt_sd",
498 CLK_SET_RATE_PARENT, 0xB8, 0, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
499 { HI3670_CLK_DIV_SDIO, "clk_div_sdio", "clk_andgt_sdio",
500 CLK_SET_RATE_PARENT, 0xC0, 0, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
501 { HI3670_CLK_DIV_UARTH, "clk_div_uarth", "clk_andgt_uarth",
502 CLK_SET_RATE_PARENT, 0xB0, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
503 { HI3670_CLK_DIV_UARTL, "clk_div_uartl", "clk_andgt_uartl",
504 CLK_SET_RATE_PARENT, 0xB0, 8, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
505 { HI3670_CLK_DIV_UART0, "clk_div_uart0", "clk_andgt_uart0",
506 CLK_SET_RATE_PARENT, 0xB0, 4, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
507 { HI3670_CLK_DIV_I2C, "clk_div_i2c", "clk_div_320m",
508 CLK_SET_RATE_PARENT, 0xE8, 4, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
509 { HI3670_CLK_DIV_SPI, "clk_div_spi", "clk_andgt_spi",
510 CLK_SET_RATE_PARENT, 0xC4, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
511 { HI3670_CLK_DIV_PCIEAXI, "clk_div_pcieaxi", "clk_andgt_pcieaxi",
512 CLK_SET_RATE_PARENT, 0xb4, 0, 5, CLK_DIVIDER_HIWORD_MASK, 0, },
513 { HI3670_CLK_DIV_AO_ASP, "clk_div_ao_asp", "clk_div_ao_asp_gt",
514 CLK_SET_RATE_PARENT, 0x108, 6, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
515 { HI3670_CLK_DIV_CSI_TRANS, "clk_div_csi_trans", "clk_gate_csi_trans",
516 CLK_SET_RATE_PARENT, 0xD4, 0, 5, CLK_DIVIDER_HIWORD_MASK, 0, },
517 { HI3670_CLK_DIV_DSI_TRANS, "clk_div_dsi_trans", "clk_gate_dsi_trans",
518 CLK_SET_RATE_PARENT, 0xD4, 10, 5, CLK_DIVIDER_HIWORD_MASK, 0, },
519 { HI3670_CLK_DIV_PTP, "clk_div_ptp", "clk_andgt_ptp",
520 CLK_SET_RATE_PARENT, 0xD8, 0, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
521 { HI3670_CLK_DIV_CLKOUT0_PLL, "clk_div_clkout0_pll", "clk_andgt_out0",
522 CLK_SET_RATE_PARENT, 0xe0, 4, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
523 { HI3670_CLK_DIV_CLKOUT1_PLL, "clk_div_clkout1_pll", "clk_andgt_out1",
524 CLK_SET_RATE_PARENT, 0xe0, 10, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
525 { HI3670_CLKDIV_DP_AUDIO_PLL_AO, "clkdiv_dp_audio_pll_ao", "clkgt_dp_audio_pll_ao",
526 CLK_SET_RATE_PARENT, 0xBC, 11, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
527 { HI3670_CLK_DIV_VDEC, "clk_div_vdec", "clk_andgt_vdec",
528 CLK_SET_RATE_PARENT, 0xC4, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
529 { HI3670_CLK_DIV_VENC, "clk_div_venc", "clk_andgt_venc",
530 CLK_SET_RATE_PARENT, 0xC0, 8, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
531 { HI3670_CLK_ISP_SNCLK_DIV0, "clk_isp_snclk_div0", "clk_isp_snclk_fac",
532 CLK_SET_RATE_PARENT, 0x108, 0, 2, CLK_DIVIDER_HIWORD_MASK, 0, },
533 { HI3670_CLK_ISP_SNCLK_DIV1, "clk_isp_snclk_div1", "clk_isp_snclk_fac",
534 CLK_SET_RATE_PARENT, 0x10C, 14, 2, CLK_DIVIDER_HIWORD_MASK, 0, },
535 { HI3670_CLK_ISP_SNCLK_DIV2, "clk_isp_snclk_div2", "clk_isp_snclk_fac",
536 CLK_SET_RATE_PARENT, 0x10C, 11, 2, CLK_DIVIDER_HIWORD_MASK, 0, },
537 { HI3670_CLK_DIV_ICS, "clk_div_ics", "clk_andgt_ics",
538 CLK_SET_RATE_PARENT, 0xE4, 9, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
539};
540
541/* clk_pmuctrl */
542static const struct hisi_gate_clock hi3670_pmu_gate_clks[] = {
543 { HI3670_GATE_ABB_192, "clk_gate_abb_192", "clkin_sys",
544 CLK_SET_RATE_PARENT, (0x037 << 2), 0, 0, },
545};
546
547/* clk_pctrl */
548static const struct hisi_gate_clock hi3670_pctrl_gate_clks[] = {
549 { HI3670_GATE_UFS_TCXO_EN, "clk_gate_ufs_tcxo_en", "clk_gate_abb_192",
550 CLK_SET_RATE_PARENT, 0x10, 0, CLK_GATE_HIWORD_MASK, },
551 { HI3670_GATE_USB_TCXO_EN, "clk_gate_usb_tcxo_en", "clk_gate_abb_192",
552 CLK_SET_RATE_PARENT, 0x10, 1, CLK_GATE_HIWORD_MASK, },
553};
554
555/* clk_sctrl */
556static const struct hisi_gate_clock hi3670_sctrl_gate_sep_clks[] = {
557 { HI3670_PPLL0_EN_ACPU, "ppll0_en_acpu", "clk_ppll0",
558 CLK_SET_RATE_PARENT, 0x190, 26, 0, },
559 { HI3670_PPLL0_GT_CPU, "ppll0_gt_cpu", "clk_ppll0",
560 CLK_SET_RATE_PARENT, 0x190, 15, 0, },
561 { HI3670_CLK_GATE_PPLL0_MEDIA, "clk_gate_ppll0_media", "clk_ppll0",
562 CLK_SET_RATE_PARENT, 0x1b0, 6, 0, },
563 { HI3670_PCLK_GPIO18, "pclk_gpio18", "clk_div_aobus",
564 CLK_SET_RATE_PARENT, 0x1B0, 9, 0, },
565 { HI3670_PCLK_GPIO19, "pclk_gpio19", "clk_div_aobus",
566 CLK_SET_RATE_PARENT, 0x1B0, 8, 0, },
567 { HI3670_CLK_GATE_SPI, "clk_gate_spi", "clk_div_ioperi",
568 CLK_SET_RATE_PARENT, 0x1B0, 10, 0, },
569 { HI3670_PCLK_GATE_SPI, "pclk_gate_spi", "clk_div_ioperi",
570 CLK_SET_RATE_PARENT, 0x1B0, 10, 0, },
571 { HI3670_CLK_GATE_UFS_SUBSYS, "clk_gate_ufs_subsys", "clk_div_ufs_subsys",
572 CLK_SET_RATE_PARENT, 0x1B0, 14, 0, },
573 { HI3670_CLK_GATE_UFSIO_REF, "clk_gate_ufsio_ref", "clkin_sys",
574 CLK_SET_RATE_PARENT, 0x1b0, 12, 0, },
575 { HI3670_PCLK_AO_GPIO0, "pclk_ao_gpio0", "clk_div_aobus",
576 CLK_SET_RATE_PARENT, 0x160, 11, 0, },
577 { HI3670_PCLK_AO_GPIO1, "pclk_ao_gpio1", "clk_div_aobus",
578 CLK_SET_RATE_PARENT, 0x160, 12, 0, },
579 { HI3670_PCLK_AO_GPIO2, "pclk_ao_gpio2", "clk_div_aobus",
580 CLK_SET_RATE_PARENT, 0x160, 13, 0, },
581 { HI3670_PCLK_AO_GPIO3, "pclk_ao_gpio3", "clk_div_aobus",
582 CLK_SET_RATE_PARENT, 0x160, 14, 0, },
583 { HI3670_PCLK_AO_GPIO4, "pclk_ao_gpio4", "clk_div_aobus",
584 CLK_SET_RATE_PARENT, 0x160, 21, 0, },
585 { HI3670_PCLK_AO_GPIO5, "pclk_ao_gpio5", "clk_div_aobus",
586 CLK_SET_RATE_PARENT, 0x160, 22, 0, },
587 { HI3670_PCLK_AO_GPIO6, "pclk_ao_gpio6", "clk_div_aobus",
588 CLK_SET_RATE_PARENT, 0x160, 25, 0, },
589 { HI3670_CLK_GATE_OUT0, "clk_gate_out0", "clk_mux_clkout0",
590 CLK_SET_RATE_PARENT, 0x160, 16, 0, },
591 { HI3670_CLK_GATE_OUT1, "clk_gate_out1", "clk_mux_clkout1",
592 CLK_SET_RATE_PARENT, 0x160, 17, 0, },
593 { HI3670_PCLK_GATE_SYSCNT, "pclk_gate_syscnt", "clk_div_aobus",
594 CLK_SET_RATE_PARENT, 0x160, 19, 0, },
595 { HI3670_CLK_GATE_SYSCNT, "clk_gate_syscnt", "clkin_sys",
596 CLK_SET_RATE_PARENT, 0x160, 20, 0, },
597 { HI3670_CLK_GATE_ASP_SUBSYS_PERI, "clk_gate_asp_subsys_peri",
598 "clk_mux_asp_subsys_peri",
599 CLK_SET_RATE_PARENT, 0x170, 6, 0, },
600 { HI3670_CLK_GATE_ASP_SUBSYS, "clk_gate_asp_subsys", "clk_mux_asp_pll",
601 CLK_SET_RATE_PARENT, 0x170, 4, 0, },
602 { HI3670_CLK_GATE_ASP_TCXO, "clk_gate_asp_tcxo", "clkin_sys",
603 CLK_SET_RATE_PARENT, 0x160, 27, 0, },
604 { HI3670_CLK_GATE_DP_AUDIO_PLL, "clk_gate_dp_audio_pll",
605 "clk_gate_dp_audio_pll_ao",
606 CLK_SET_RATE_PARENT, 0x1B0, 7, 0, },
607};
608
609static const struct hisi_gate_clock hi3670_sctrl_gate_clks[] = {
610 { HI3670_CLK_ANDGT_IOPERI, "clk_andgt_ioperi", "clk_ppll0",
611 CLK_SET_RATE_PARENT, 0x270, 6, CLK_GATE_HIWORD_MASK, 0, },
612 { HI3670_CLKANDGT_ASP_SUBSYS_PERI, "clkandgt_asp_subsys_peri",
613 "clk_ppll0",
614 CLK_SET_RATE_PARENT, 0x268, 3, CLK_GATE_HIWORD_MASK, 0, },
615 { HI3670_CLK_ANGT_ASP_SUBSYS, "clk_angt_asp_subsys", "clk_ppll0",
616 CLK_SET_RATE_PARENT, 0x258, 0, CLK_GATE_HIWORD_MASK, 0, },
617};
618
619static const char *const
620clk_mux_ufs_subsys_p[] = { "clkin_sys", "clk_ppll0", };
621static const char *const
622clk_mux_clkout0_p[] = { "clkin_ref", "clk_div_clkout0_tcxo",
623 "clk_div_clkout0_pll", "clk_div_clkout0_pll", };
624static const char *const
625clk_mux_clkout1_p[] = { "clkin_ref", "clk_div_clkout1_tcxo",
626 "clk_div_clkout1_pll", "clk_div_clkout1_pll", };
627static const char *const
628clk_mux_asp_subsys_peri_p[] = { "clk_ppll0", "clk_fll_src", };
629static const char *const
630clk_mux_asp_pll_p[] = { "clk_ppll0", "clk_fll_src", "clk_gate_ao_asp",
631 "clk_pciepll_rev", };
632
633static const struct hisi_mux_clock hi3670_sctrl_mux_clks[] = {
634 { HI3670_CLK_MUX_UFS_SUBSYS, "clk_mux_ufs_subsys", clk_mux_ufs_subsys_p,
635 ARRAY_SIZE(clk_mux_ufs_subsys_p), CLK_SET_RATE_PARENT,
636 0x274, 8, 1, CLK_MUX_HIWORD_MASK, },
637 { HI3670_CLK_MUX_CLKOUT0, "clk_mux_clkout0", clk_mux_clkout0_p,
638 ARRAY_SIZE(clk_mux_clkout0_p), CLK_SET_RATE_PARENT,
639 0x254, 12, 2, CLK_MUX_HIWORD_MASK, },
640 { HI3670_CLK_MUX_CLKOUT1, "clk_mux_clkout1", clk_mux_clkout1_p,
641 ARRAY_SIZE(clk_mux_clkout1_p), CLK_SET_RATE_PARENT,
642 0x254, 14, 2, CLK_MUX_HIWORD_MASK, },
643 { HI3670_CLK_MUX_ASP_SUBSYS_PERI, "clk_mux_asp_subsys_peri",
644 clk_mux_asp_subsys_peri_p, ARRAY_SIZE(clk_mux_asp_subsys_peri_p),
645 CLK_SET_RATE_PARENT, 0x268, 8, 1, CLK_MUX_HIWORD_MASK, },
646 { HI3670_CLK_MUX_ASP_PLL, "clk_mux_asp_pll", clk_mux_asp_pll_p,
647 ARRAY_SIZE(clk_mux_asp_pll_p), CLK_SET_RATE_PARENT,
648 0x268, 9, 2, CLK_MUX_HIWORD_MASK, },
649};
650
651static const struct hisi_divider_clock hi3670_sctrl_divider_clks[] = {
652 { HI3670_CLK_DIV_AOBUS, "clk_div_aobus", "clk_ppll0",
653 CLK_SET_RATE_PARENT, 0x254, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
654 { HI3670_CLK_DIV_UFS_SUBSYS, "clk_div_ufs_subsys", "clk_mux_ufs_subsys",
655 CLK_SET_RATE_PARENT, 0x274, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
656 { HI3670_CLK_DIV_IOPERI, "clk_div_ioperi", "clk_andgt_ioperi",
657 CLK_SET_RATE_PARENT, 0x270, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
658 { HI3670_CLK_DIV_CLKOUT0_TCXO, "clk_div_clkout0_tcxo", "clkin_sys",
659 CLK_SET_RATE_PARENT, 0x254, 6, 3, CLK_DIVIDER_HIWORD_MASK, 0, },
660 { HI3670_CLK_DIV_CLKOUT1_TCXO, "clk_div_clkout1_tcxo", "clkin_sys",
661 CLK_SET_RATE_PARENT, 0x254, 9, 3, CLK_DIVIDER_HIWORD_MASK, 0, },
662 { HI3670_CLK_ASP_SUBSYS_PERI_DIV, "clk_asp_subsys_peri_div", "clkandgt_asp_subsys_peri",
663 CLK_SET_RATE_PARENT, 0x268, 0, 3, CLK_DIVIDER_HIWORD_MASK, 0, },
664 { HI3670_CLK_DIV_ASP_SUBSYS, "clk_div_asp_subsys", "clk_angt_asp_subsys",
665 CLK_SET_RATE_PARENT, 0x250, 0, 3, CLK_DIVIDER_HIWORD_MASK, 0, },
666};
667
668/* clk_iomcu */
669static const struct hisi_fixed_factor_clock hi3670_iomcu_fixed_factor_clks[] = {
670 { HI3670_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_gate_iomcu", 1, 4, 0, },
671 { HI3670_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_gate_iomcu", 1, 4, 0, },
672 { HI3670_CLK_GATE_I2C2, "clk_gate_i2c2", "clk_i2c2_gate_iomcu", 1, 4, 0, },
673 { HI3670_CLK_GATE_SPI0, "clk_gate_spi0", "clk_spi0_gate_iomcu", 1, 1, 0, },
674 { HI3670_CLK_GATE_SPI2, "clk_gate_spi2", "clk_spi2_gate_iomcu", 1, 1, 0, },
675 { HI3670_CLK_GATE_UART3, "clk_gate_uart3", "clk_uart3_gate_iomcu", 1, 16, 0, },
676};
677
678static const struct hisi_gate_clock hi3670_iomcu_gate_sep_clks[] = {
679 { HI3670_CLK_I2C0_GATE_IOMCU, "clk_i2c0_gate_iomcu", "clk_fll_src",
680 CLK_SET_RATE_PARENT, 0x10, 3, 0, },
681 { HI3670_CLK_I2C1_GATE_IOMCU, "clk_i2c1_gate_iomcu", "clk_fll_src",
682 CLK_SET_RATE_PARENT, 0x10, 4, 0, },
683 { HI3670_CLK_I2C2_GATE_IOMCU, "clk_i2c2_gate_iomcu", "clk_fll_src",
684 CLK_SET_RATE_PARENT, 0x10, 5, 0, },
685 { HI3670_CLK_SPI0_GATE_IOMCU, "clk_spi0_gate_iomcu", "clk_fll_src",
686 CLK_SET_RATE_PARENT, 0x10, 10, 0, },
687 { HI3670_CLK_SPI2_GATE_IOMCU, "clk_spi2_gate_iomcu", "clk_fll_src",
688 CLK_SET_RATE_PARENT, 0x10, 30, 0, },
689 { HI3670_CLK_UART3_GATE_IOMCU, "clk_uart3_gate_iomcu", "clk_gate_iomcu_peri0",
690 CLK_SET_RATE_PARENT, 0x10, 11, 0, },
691 { HI3670_CLK_GATE_PERI0_IOMCU, "clk_gate_iomcu_peri0", "clk_ppll0",
692 CLK_SET_RATE_PARENT, 0x90, 0, 0, },
693};
694
695/* clk_media1 */
696static const struct hisi_gate_clock hi3670_media1_gate_sep_clks[] = {
697 { HI3670_ACLK_GATE_NOC_DSS, "aclk_gate_noc_dss", "aclk_gate_disp_noc_subsys",
698 CLK_SET_RATE_PARENT, 0x10, 21, 0, },
699 { HI3670_PCLK_GATE_NOC_DSS_CFG, "pclk_gate_noc_dss_cfg", "pclk_gate_disp_noc_subsys",
700 CLK_SET_RATE_PARENT, 0x10, 22, 0, },
701 { HI3670_PCLK_GATE_MMBUF_CFG, "pclk_gate_mmbuf_cfg", "pclk_gate_disp_noc_subsys",
702 CLK_SET_RATE_PARENT, 0x20, 5, 0, },
703 { HI3670_PCLK_GATE_DISP_NOC_SUBSYS, "pclk_gate_disp_noc_subsys", "clk_div_sysbus",
704 CLK_SET_RATE_PARENT, 0x10, 18, 0, },
705 { HI3670_ACLK_GATE_DISP_NOC_SUBSYS, "aclk_gate_disp_noc_subsys", "clk_gate_vivobusfreq",
706 CLK_SET_RATE_PARENT, 0x10, 17, 0, },
707 { HI3670_PCLK_GATE_DSS, "pclk_gate_dss", "pclk_gate_disp_noc_subsys",
708 CLK_SET_RATE_PARENT, 0x00, 14, 0, },
709 { HI3670_ACLK_GATE_DSS, "aclk_gate_dss", "aclk_gate_disp_noc_subsys",
710 CLK_SET_RATE_PARENT, 0x00, 19, 0, },
711 { HI3670_CLK_GATE_VIVOBUSFREQ, "clk_gate_vivobusfreq", "clk_div_vivobus",
712 CLK_SET_RATE_PARENT, 0x00, 18, 0, },
713 { HI3670_CLK_GATE_EDC0, "clk_gate_edc0", "clk_div_edc0",
714 CLK_SET_RATE_PARENT, 0x00, 15, 0, },
715 { HI3670_CLK_GATE_LDI0, "clk_gate_ldi0", "clk_div_ldi0",
716 CLK_SET_RATE_PARENT, 0x00, 16, 0, },
717 { HI3670_CLK_GATE_LDI1FREQ, "clk_gate_ldi1freq", "clk_div_ldi1",
718 CLK_SET_RATE_PARENT, 0x00, 17, 0, },
719 { HI3670_CLK_GATE_BRG, "clk_gate_brg", "clk_media_common_div",
720 CLK_SET_RATE_PARENT, 0x00, 29, 0, },
721 { HI3670_ACLK_GATE_ASC, "aclk_gate_asc", "clk_gate_mmbuf",
722 CLK_SET_RATE_PARENT, 0x20, 3, 0, },
723 { HI3670_CLK_GATE_DSS_AXI_MM, "clk_gate_dss_axi_mm", "clk_gate_mmbuf",
724 CLK_SET_RATE_PARENT, 0x20, 4, 0, },
725 { HI3670_CLK_GATE_MMBUF, "clk_gate_mmbuf", "aclk_div_mmbuf",
726 CLK_SET_RATE_PARENT, 0x20, 0, 0, },
727 { HI3670_PCLK_GATE_MMBUF, "pclk_gate_mmbuf", "pclk_div_mmbuf",
728 CLK_SET_RATE_PARENT, 0x20, 1, 0, },
729 { HI3670_CLK_GATE_ATDIV_VIVO, "clk_gate_atdiv_vivo", "clk_div_vivobus",
730 CLK_SET_RATE_PARENT, 0x010, 1, 0, },
731};
732
733static const struct hisi_gate_clock hi3670_media1_gate_clks[] = {
734 { HI3670_CLK_GATE_VIVOBUS_ANDGT, "clk_gate_vivobus_andgt", "clk_mux_vivobus",
735 CLK_SET_RATE_PARENT, 0x84, 3, CLK_GATE_HIWORD_MASK, 0, },
736 { HI3670_CLK_ANDGT_EDC0, "clk_andgt_edc0", "clk_mux_edc0",
737 CLK_SET_RATE_PARENT, 0x84, 7, CLK_GATE_HIWORD_MASK, 0, },
738 { HI3670_CLK_ANDGT_LDI0, "clk_andgt_ldi0", "clk_mux_ldi0",
739 CLK_SET_RATE_PARENT, 0x84, 9, CLK_GATE_HIWORD_MASK, 0, },
740 { HI3670_CLK_ANDGT_LDI1, "clk_andgt_ldi1", "clk_mux_ldi1",
741 CLK_SET_RATE_PARENT, 0x84, 8, CLK_GATE_HIWORD_MASK, 0, },
742 { HI3670_CLK_MMBUF_PLL_ANDGT, "clk_mmbuf_pll_andgt", "clk_sw_mmbuf",
743 CLK_SET_RATE_PARENT, 0x84, 14, CLK_GATE_HIWORD_MASK, 0, },
744 { HI3670_PCLK_MMBUF_ANDGT, "pclk_mmbuf_andgt", "aclk_div_mmbuf",
745 CLK_SET_RATE_PARENT, 0x84, 15, CLK_GATE_HIWORD_MASK, 0, },
746};
747
748static const char *const
749clk_mux_vivobus_p[] = { "clk_invalid", "clk_invalid", "clk_gate_ppll0_media",
750 "clk_invalid", "clk_gate_ppll2_media", "clk_invalid",
751 "clk_invalid", "clk_invalid", "clk_gate_ppll3_media",
752 "clk_invalid", "clk_invalid", "clk_invalid",
753 "clk_invalid", "clk_invalid", "clk_invalid",
754 "clk_invalid", };
755static const char *const
756clk_mux_edc0_p[] = { "clk_invalid", "clk_invalid", "clk_gate_ppll0_media",
757 "clk_invalid", "clk_gate_ppll2_media", "clk_invalid",
758 "clk_invalid", "clk_invalid", "clk_gate_ppll3_media",
759 "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
760 "clk_invalid", "clk_invalid", "clk_invalid", };
761static const char *const
762clk_mux_ldi0_p[] = { "clk_invalid", "clk_gate_ppll7_media",
763 "clk_gate_ppll0_media", "clk_invalid",
764 "clk_gate_ppll2_media", "clk_invalid", "clk_invalid",
765 "clk_invalid", "clk_gate_ppll3_media", "clk_invalid",
766 "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
767 "clk_invalid", "clk_invalid", };
768static const char *const
769clk_mux_ldi1_p[] = { "clk_invalid", "clk_gate_ppll7_media",
770 "clk_gate_ppll0_media", "clk_invalid",
771 "clk_gate_ppll2_media", "clk_invalid", "clk_invalid",
772 "clk_invalid", "clk_gate_ppll3_media", "clk_invalid",
773 "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
774 "clk_invalid", "clk_invalid", };
775static const char *const
776clk_sw_mmbuf_p[] = { "clk_invalid", "clk_invalid", "clk_gate_ppll0_media",
777 "clk_invalid", "clk_gate_ppll2_media", "clk_invalid",
778 "clk_invalid", "clk_invalid", "clk_gate_ppll3_media",
779 "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
780 "clk_invalid", "clk_invalid", "clk_invalid", };
781
782static const struct hisi_mux_clock hi3670_media1_mux_clks[] = {
783 { HI3670_CLK_MUX_VIVOBUS, "clk_mux_vivobus", clk_mux_vivobus_p,
784 ARRAY_SIZE(clk_mux_vivobus_p), CLK_SET_RATE_PARENT,
785 0x74, 6, 4, CLK_MUX_HIWORD_MASK, },
786 { HI3670_CLK_MUX_EDC0, "clk_mux_edc0", clk_mux_edc0_p,
787 ARRAY_SIZE(clk_mux_edc0_p), CLK_SET_RATE_PARENT,
788 0x68, 6, 4, CLK_MUX_HIWORD_MASK, },
789 { HI3670_CLK_MUX_LDI0, "clk_mux_ldi0", clk_mux_ldi0_p,
790 ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT,
791 0x60, 6, 4, CLK_MUX_HIWORD_MASK, },
792 { HI3670_CLK_MUX_LDI1, "clk_mux_ldi1", clk_mux_ldi1_p,
793 ARRAY_SIZE(clk_mux_ldi1_p), CLK_SET_RATE_PARENT,
794 0x64, 6, 4, CLK_MUX_HIWORD_MASK, },
795 { HI3670_CLK_SW_MMBUF, "clk_sw_mmbuf", clk_sw_mmbuf_p,
796 ARRAY_SIZE(clk_sw_mmbuf_p), CLK_SET_RATE_PARENT,
797 0x88, 0, 4, CLK_MUX_HIWORD_MASK, },
798};
799
800static const struct hisi_divider_clock hi3670_media1_divider_clks[] = {
801 { HI3670_CLK_DIV_VIVOBUS, "clk_div_vivobus", "clk_gate_vivobus_andgt",
802 CLK_SET_RATE_PARENT, 0x74, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
803 { HI3670_CLK_DIV_EDC0, "clk_div_edc0", "clk_andgt_edc0",
804 CLK_SET_RATE_PARENT, 0x68, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
805 { HI3670_CLK_DIV_LDI0, "clk_div_ldi0", "clk_andgt_ldi0",
806 CLK_SET_RATE_PARENT, 0x60, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
807 { HI3670_CLK_DIV_LDI1, "clk_div_ldi1", "clk_andgt_ldi1",
808 CLK_SET_RATE_PARENT, 0x64, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
809 { HI3670_ACLK_DIV_MMBUF, "aclk_div_mmbuf", "clk_mmbuf_pll_andgt",
810 CLK_SET_RATE_PARENT, 0x7C, 10, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
811 { HI3670_PCLK_DIV_MMBUF, "pclk_div_mmbuf", "pclk_mmbuf_andgt",
812 CLK_SET_RATE_PARENT, 0x78, 0, 2, CLK_DIVIDER_HIWORD_MASK, 0, },
813};
814
815/* clk_media2 */
816static const struct hisi_gate_clock hi3670_media2_gate_sep_clks[] = {
817 { HI3670_CLK_GATE_VDECFREQ, "clk_gate_vdecfreq", "clk_div_vdec",
818 CLK_SET_RATE_PARENT, 0x00, 8, 0, },
819 { HI3670_CLK_GATE_VENCFREQ, "clk_gate_vencfreq", "clk_div_venc",
820 CLK_SET_RATE_PARENT, 0x00, 5, 0, },
821 { HI3670_CLK_GATE_ICSFREQ, "clk_gate_icsfreq", "clk_div_ics",
822 CLK_SET_RATE_PARENT, 0x00, 2, 0, },
823};
824
825static void hi3670_clk_crgctrl_init(struct device_node *np)
826{
827 struct hisi_clock_data *clk_data;
828
829 int nr = ARRAY_SIZE(hi3670_fixed_rate_clks) +
830 ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks) +
831 ARRAY_SIZE(hi3670_crgctrl_gate_clks) +
832 ARRAY_SIZE(hi3670_crgctrl_mux_clks) +
833 ARRAY_SIZE(hi3670_crg_fixed_factor_clks) +
834 ARRAY_SIZE(hi3670_crgctrl_divider_clks);
835
836 clk_data = hisi_clk_init(np, nr);
837 if (!clk_data)
838 return;
839
840 hisi_clk_register_fixed_rate(hi3670_fixed_rate_clks,
841 ARRAY_SIZE(hi3670_fixed_rate_clks),
842 clk_data);
843 hisi_clk_register_gate_sep(hi3670_crgctrl_gate_sep_clks,
844 ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks),
845 clk_data);
846 hisi_clk_register_gate(hi3670_crgctrl_gate_clks,
847 ARRAY_SIZE(hi3670_crgctrl_gate_clks),
848 clk_data);
849 hisi_clk_register_mux(hi3670_crgctrl_mux_clks,
850 ARRAY_SIZE(hi3670_crgctrl_mux_clks),
851 clk_data);
852 hisi_clk_register_fixed_factor(hi3670_crg_fixed_factor_clks,
853 ARRAY_SIZE(hi3670_crg_fixed_factor_clks),
854 clk_data);
855 hisi_clk_register_divider(hi3670_crgctrl_divider_clks,
856 ARRAY_SIZE(hi3670_crgctrl_divider_clks),
857 clk_data);
858}
859
860static void hi3670_clk_pctrl_init(struct device_node *np)
861{
862 struct hisi_clock_data *clk_data;
863 int nr = ARRAY_SIZE(hi3670_pctrl_gate_clks);
864
865 clk_data = hisi_clk_init(np, nr);
866 if (!clk_data)
867 return;
868 hisi_clk_register_gate(hi3670_pctrl_gate_clks,
869 ARRAY_SIZE(hi3670_pctrl_gate_clks), clk_data);
870}
871
872static void hi3670_clk_pmuctrl_init(struct device_node *np)
873{
874 struct hisi_clock_data *clk_data;
875 int nr = ARRAY_SIZE(hi3670_pmu_gate_clks);
876
877 clk_data = hisi_clk_init(np, nr);
878 if (!clk_data)
879 return;
880
881 hisi_clk_register_gate(hi3670_pmu_gate_clks,
882 ARRAY_SIZE(hi3670_pmu_gate_clks), clk_data);
883}
884
885static void hi3670_clk_sctrl_init(struct device_node *np)
886{
887 struct hisi_clock_data *clk_data;
888 int nr = ARRAY_SIZE(hi3670_sctrl_gate_sep_clks) +
889 ARRAY_SIZE(hi3670_sctrl_gate_clks) +
890 ARRAY_SIZE(hi3670_sctrl_mux_clks) +
891 ARRAY_SIZE(hi3670_sctrl_divider_clks);
892
893 clk_data = hisi_clk_init(np, nr);
894 if (!clk_data)
895 return;
896
897 hisi_clk_register_gate_sep(hi3670_sctrl_gate_sep_clks,
898 ARRAY_SIZE(hi3670_sctrl_gate_sep_clks),
899 clk_data);
900 hisi_clk_register_gate(hi3670_sctrl_gate_clks,
901 ARRAY_SIZE(hi3670_sctrl_gate_clks),
902 clk_data);
903 hisi_clk_register_mux(hi3670_sctrl_mux_clks,
904 ARRAY_SIZE(hi3670_sctrl_mux_clks),
905 clk_data);
906 hisi_clk_register_divider(hi3670_sctrl_divider_clks,
907 ARRAY_SIZE(hi3670_sctrl_divider_clks),
908 clk_data);
909}
910
911static void hi3670_clk_iomcu_init(struct device_node *np)
912{
913 struct hisi_clock_data *clk_data;
914 int nr = ARRAY_SIZE(hi3670_iomcu_gate_sep_clks) +
915 ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks);
916
917 clk_data = hisi_clk_init(np, nr);
918 if (!clk_data)
919 return;
920
921 hisi_clk_register_gate(hi3670_iomcu_gate_sep_clks,
922 ARRAY_SIZE(hi3670_iomcu_gate_sep_clks), clk_data);
923
924 hisi_clk_register_fixed_factor(hi3670_iomcu_fixed_factor_clks,
925 ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks),
926 clk_data);
927}
928
929static void hi3670_clk_media1_init(struct device_node *np)
930{
931 struct hisi_clock_data *clk_data;
932
933 int nr = ARRAY_SIZE(hi3670_media1_gate_sep_clks) +
934 ARRAY_SIZE(hi3670_media1_gate_clks) +
935 ARRAY_SIZE(hi3670_media1_mux_clks) +
936 ARRAY_SIZE(hi3670_media1_divider_clks);
937
938 clk_data = hisi_clk_init(np, nr);
939 if (!clk_data)
940 return;
941
942 hisi_clk_register_gate_sep(hi3670_media1_gate_sep_clks,
943 ARRAY_SIZE(hi3670_media1_gate_sep_clks),
944 clk_data);
945 hisi_clk_register_gate(hi3670_media1_gate_clks,
946 ARRAY_SIZE(hi3670_media1_gate_clks),
947 clk_data);
948 hisi_clk_register_mux(hi3670_media1_mux_clks,
949 ARRAY_SIZE(hi3670_media1_mux_clks),
950 clk_data);
951 hisi_clk_register_divider(hi3670_media1_divider_clks,
952 ARRAY_SIZE(hi3670_media1_divider_clks),
953 clk_data);
954}
955
956static void hi3670_clk_media2_init(struct device_node *np)
957{
958 struct hisi_clock_data *clk_data;
959
960 int nr = ARRAY_SIZE(hi3670_media2_gate_sep_clks);
961
962 clk_data = hisi_clk_init(np, nr);
963 if (!clk_data)
964 return;
965
966 hisi_clk_register_gate_sep(hi3670_media2_gate_sep_clks,
967 ARRAY_SIZE(hi3670_media2_gate_sep_clks),
968 clk_data);
969}
970
971static const struct of_device_id hi3670_clk_match_table[] = {
972 { .compatible = "hisilicon,hi3670-crgctrl",
973 .data = hi3670_clk_crgctrl_init },
974 { .compatible = "hisilicon,hi3670-pctrl",
975 .data = hi3670_clk_pctrl_init },
976 { .compatible = "hisilicon,hi3670-pmuctrl",
977 .data = hi3670_clk_pmuctrl_init },
978 { .compatible = "hisilicon,hi3670-sctrl",
979 .data = hi3670_clk_sctrl_init },
980 { .compatible = "hisilicon,hi3670-iomcu",
981 .data = hi3670_clk_iomcu_init },
982 { .compatible = "hisilicon,hi3670-media1-crg",
983 .data = hi3670_clk_media1_init },
984 { .compatible = "hisilicon,hi3670-media2-crg",
985 .data = hi3670_clk_media2_init },
986 { }
987};
988
989static int hi3670_clk_probe(struct platform_device *pdev)
990{
991 struct device *dev = &pdev->dev;
992 struct device_node *np = pdev->dev.of_node;
993 void (*init_func)(struct device_node *np);
994
995 init_func = of_device_get_match_data(dev);
996 if (!init_func)
997 return -ENODEV;
998
999 init_func(np);
1000
1001 return 0;
1002}
1003
1004static struct platform_driver hi3670_clk_driver = {
1005 .probe = hi3670_clk_probe,
1006 .driver = {
1007 .name = "hi3670-clk",
1008 .of_match_table = hi3670_clk_match_table,
1009 },
1010};
1011
1012static int __init hi3670_clk_init(void)
1013{
1014 return platform_driver_register(&hi3670_clk_driver);
1015}
1016core_initcall(hi3670_clk_init);
diff --git a/drivers/clk/hisilicon/reset.c b/drivers/clk/hisilicon/reset.c
index 2a5015c736ce..43e82fa64422 100644
--- a/drivers/clk/hisilicon/reset.c
+++ b/drivers/clk/hisilicon/reset.c
@@ -109,9 +109,8 @@ struct hisi_reset_controller *hisi_reset_init(struct platform_device *pdev)
109 return NULL; 109 return NULL;
110 110
111 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 111 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
112 rstc->membase = devm_ioremap(&pdev->dev, 112 rstc->membase = devm_ioremap_resource(&pdev->dev, res);
113 res->start, resource_size(res)); 113 if (IS_ERR(rstc->membase))
114 if (!rstc->membase)
115 return NULL; 114 return NULL;
116 115
117 spin_lock_init(&rstc->lock); 116 spin_lock_init(&rstc->lock);
diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig
new file mode 100644
index 000000000000..34dc0da79c39
--- /dev/null
+++ b/drivers/clk/ingenic/Kconfig
@@ -0,0 +1,47 @@
1menu "Ingenic JZ47xx CGU drivers"
2 depends on MIPS
3
4config INGENIC_CGU_COMMON
5 bool
6
7config INGENIC_CGU_JZ4740
8 bool "Ingenic JZ4740 CGU driver"
9 default MACH_JZ4740
10 select INGENIC_CGU_COMMON
11 help
12 Support the clocks provided by the CGU hardware on Ingenic JZ4740
13 and compatible SoCs.
14
15 If building for a JZ4740 SoC, you want to say Y here.
16
17config INGENIC_CGU_JZ4725B
18 bool "Ingenic JZ4725B CGU driver"
19 default MACH_JZ4725B
20 select INGENIC_CGU_COMMON
21 help
22 Support the clocks provided by the CGU hardware on Ingenic JZ4725B
23 and compatible SoCs.
24
25 If building for a JZ4725B SoC, you want to say Y here.
26
27config INGENIC_CGU_JZ4770
28 bool "Ingenic JZ4770 CGU driver"
29 default MACH_JZ4770
30 select INGENIC_CGU_COMMON
31 help
32 Support the clocks provided by the CGU hardware on Ingenic JZ4770
33 and compatible SoCs.
34
35 If building for a JZ4770 SoC, you want to say Y here.
36
37config INGENIC_CGU_JZ4780
38 bool "Ingenic JZ4780 CGU driver"
39 default MACH_JZ4780
40 select INGENIC_CGU_COMMON
41 help
42 Support the clocks provided by the CGU hardware on Ingenic JZ4780
43 and compatible SoCs.
44
45 If building for a JZ4780 SoC, you want to say Y here.
46
47endmenu
diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile
index 1456e4cdb562..00a79b2fba10 100644
--- a/drivers/clk/ingenic/Makefile
+++ b/drivers/clk/ingenic/Makefile
@@ -1,4 +1,5 @@
1obj-y += cgu.o 1obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o
2obj-$(CONFIG_MACH_JZ4740) += jz4740-cgu.o 2obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
3obj-$(CONFIG_MACH_JZ4770) += jz4770-cgu.o 3obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
4obj-$(CONFIG_MACH_JZ4780) += jz4780-cgu.o 4obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
5obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o
diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c
new file mode 100644
index 000000000000..584ff4ff81c7
--- /dev/null
+++ b/drivers/clk/ingenic/jz4725b-cgu.c
@@ -0,0 +1,225 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Ingenic JZ4725B SoC CGU driver
4 *
5 * Copyright (C) 2018 Paul Cercueil
6 * Author: Paul Cercueil <paul@crapouillou.net>
7 */
8
9#include <linux/clk-provider.h>
10#include <linux/delay.h>
11#include <linux/of.h>
12#include <dt-bindings/clock/jz4725b-cgu.h>
13#include "cgu.h"
14
15/* CGU register offsets */
16#define CGU_REG_CPCCR 0x00
17#define CGU_REG_LCR 0x04
18#define CGU_REG_CPPCR 0x10
19#define CGU_REG_CLKGR 0x20
20#define CGU_REG_OPCR 0x24
21#define CGU_REG_I2SCDR 0x60
22#define CGU_REG_LPCDR 0x64
23#define CGU_REG_MSCCDR 0x68
24#define CGU_REG_SSICDR 0x74
25#define CGU_REG_CIMCDR 0x78
26
27/* bits within the LCR register */
28#define LCR_SLEEP BIT(0)
29
30static struct ingenic_cgu *cgu;
31
32static const s8 pll_od_encoding[4] = {
33 0x0, 0x1, -1, 0x3,
34};
35
36static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
37
38 /* External clocks */
39
40 [JZ4725B_CLK_EXT] = { "ext", CGU_CLK_EXT },
41 [JZ4725B_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
42
43 [JZ4725B_CLK_PLL] = {
44 "pll", CGU_CLK_PLL,
45 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
46 .pll = {
47 .reg = CGU_REG_CPPCR,
48 .m_shift = 23,
49 .m_bits = 9,
50 .m_offset = 2,
51 .n_shift = 18,
52 .n_bits = 5,
53 .n_offset = 2,
54 .od_shift = 16,
55 .od_bits = 2,
56 .od_max = 4,
57 .od_encoding = pll_od_encoding,
58 .stable_bit = 10,
59 .bypass_bit = 9,
60 .enable_bit = 8,
61 },
62 },
63
64 /* Muxes & dividers */
65
66 [JZ4725B_CLK_PLL_HALF] = {
67 "pll half", CGU_CLK_DIV,
68 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
69 .div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1 },
70 },
71
72 [JZ4725B_CLK_CCLK] = {
73 "cclk", CGU_CLK_DIV,
74 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
75 .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
76 },
77
78 [JZ4725B_CLK_HCLK] = {
79 "hclk", CGU_CLK_DIV,
80 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
81 .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
82 },
83
84 [JZ4725B_CLK_PCLK] = {
85 "pclk", CGU_CLK_DIV,
86 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
87 .div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1 },
88 },
89
90 [JZ4725B_CLK_MCLK] = {
91 "mclk", CGU_CLK_DIV,
92 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
93 .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1 },
94 },
95
96 [JZ4725B_CLK_IPU] = {
97 "ipu", CGU_CLK_DIV | CGU_CLK_GATE,
98 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
99 .div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1 },
100 .gate = { CGU_REG_CLKGR, 13 },
101 },
102
103 [JZ4725B_CLK_LCD] = {
104 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
105 .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
106 .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
107 .gate = { CGU_REG_CLKGR, 9 },
108 },
109
110 [JZ4725B_CLK_I2S] = {
111 "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
112 .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
113 .mux = { CGU_REG_CPCCR, 31, 1 },
114 .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
115 .gate = { CGU_REG_CLKGR, 6 },
116 },
117
118 [JZ4725B_CLK_SPI] = {
119 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
120 .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL, -1, -1 },
121 .mux = { CGU_REG_SSICDR, 31, 1 },
122 .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
123 .gate = { CGU_REG_CLKGR, 4 },
124 },
125
126 [JZ4725B_CLK_MMC_MUX] = {
127 "mmc_mux", CGU_CLK_DIV,
128 .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
129 .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
130 },
131
132 [JZ4725B_CLK_UDC] = {
133 "udc", CGU_CLK_MUX | CGU_CLK_DIV,
134 .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
135 .mux = { CGU_REG_CPCCR, 29, 1 },
136 .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
137 },
138
139 /* Gate-only clocks */
140
141 [JZ4725B_CLK_UART] = {
142 "uart", CGU_CLK_GATE,
143 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
144 .gate = { CGU_REG_CLKGR, 0 },
145 },
146
147 [JZ4725B_CLK_DMA] = {
148 "dma", CGU_CLK_GATE,
149 .parents = { JZ4725B_CLK_PCLK, -1, -1, -1 },
150 .gate = { CGU_REG_CLKGR, 12 },
151 },
152
153 [JZ4725B_CLK_ADC] = {
154 "adc", CGU_CLK_GATE,
155 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
156 .gate = { CGU_REG_CLKGR, 7 },
157 },
158
159 [JZ4725B_CLK_I2C] = {
160 "i2c", CGU_CLK_GATE,
161 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
162 .gate = { CGU_REG_CLKGR, 3 },
163 },
164
165 [JZ4725B_CLK_AIC] = {
166 "aic", CGU_CLK_GATE,
167 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
168 .gate = { CGU_REG_CLKGR, 5 },
169 },
170
171 [JZ4725B_CLK_MMC0] = {
172 "mmc0", CGU_CLK_GATE,
173 .parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
174 .gate = { CGU_REG_CLKGR, 6 },
175 },
176
177 [JZ4725B_CLK_MMC1] = {
178 "mmc1", CGU_CLK_GATE,
179 .parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
180 .gate = { CGU_REG_CLKGR, 16 },
181 },
182
183 [JZ4725B_CLK_BCH] = {
184 "bch", CGU_CLK_GATE,
185 .parents = { JZ4725B_CLK_MCLK/* not sure */, -1, -1, -1 },
186 .gate = { CGU_REG_CLKGR, 11 },
187 },
188
189 [JZ4725B_CLK_TCU] = {
190 "tcu", CGU_CLK_GATE,
191 .parents = { JZ4725B_CLK_EXT/* not sure */, -1, -1, -1 },
192 .gate = { CGU_REG_CLKGR, 1 },
193 },
194
195 [JZ4725B_CLK_EXT512] = {
196 "ext/512", CGU_CLK_FIXDIV,
197 .parents = { JZ4725B_CLK_EXT },
198
199 /* Doc calls it EXT512, but it seems to be /256... */
200 .fixdiv = { 256 },
201 },
202
203 [JZ4725B_CLK_RTC] = {
204 "rtc", CGU_CLK_MUX,
205 .parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 },
206 .mux = { CGU_REG_OPCR, 2, 1},
207 },
208};
209
210static void __init jz4725b_cgu_init(struct device_node *np)
211{
212 int retval;
213
214 cgu = ingenic_cgu_new(jz4725b_cgu_clocks,
215 ARRAY_SIZE(jz4725b_cgu_clocks), np);
216 if (!cgu) {
217 pr_err("%s: failed to initialise CGU\n", __func__);
218 return;
219 }
220
221 retval = ingenic_cgu_register_clocks(cgu);
222 if (retval)
223 pr_err("%s: failed to register CGU Clocks\n", __func__);
224}
225CLK_OF_DECLARE(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init);
diff --git a/drivers/clk/keystone/Kconfig b/drivers/clk/keystone/Kconfig
index 7e9f0176578a..b04927d06cd1 100644
--- a/drivers/clk/keystone/Kconfig
+++ b/drivers/clk/keystone/Kconfig
@@ -7,7 +7,7 @@ config COMMON_CLK_KEYSTONE
7 7
8config TI_SCI_CLK 8config TI_SCI_CLK
9 tristate "TI System Control Interface clock drivers" 9 tristate "TI System Control Interface clock drivers"
10 depends on (ARCH_KEYSTONE || COMPILE_TEST) && OF 10 depends on (ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST) && OF
11 depends on TI_SCI_PROTOCOL 11 depends on TI_SCI_PROTOCOL
12 default ARCH_KEYSTONE 12 default ARCH_KEYSTONE
13 ---help--- 13 ---help---
diff --git a/drivers/clk/keystone/gate.c b/drivers/clk/keystone/gate.c
index aed5af23895b..4ed9b29ba438 100644
--- a/drivers/clk/keystone/gate.c
+++ b/drivers/clk/keystone/gate.c
@@ -245,7 +245,7 @@ static void __init of_psc_clk_init(struct device_node *node, spinlock_t *lock)
245 return; 245 return;
246 } 246 }
247 247
248 pr_err("%s: error registering clk %s\n", __func__, node->name); 248 pr_err("%s: error registering clk %pOFn\n", __func__, node);
249 249
250unmap_domain: 250unmap_domain:
251 iounmap(data->domain_base); 251 iounmap(data->domain_base);
@@ -266,3 +266,8 @@ static void __init of_keystone_psc_clk_init(struct device_node *node)
266} 266}
267CLK_OF_DECLARE(keystone_gate_clk, "ti,keystone,psc-clock", 267CLK_OF_DECLARE(keystone_gate_clk, "ti,keystone,psc-clock",
268 of_keystone_psc_clk_init); 268 of_keystone_psc_clk_init);
269
270MODULE_LICENSE("GPL");
271MODULE_DESCRIPTION("Clock driver for Keystone 2 based devices");
272MODULE_AUTHOR("Murali Karicheri <m-karicheri2@ti.com>");
273MODULE_AUTHOR("Santosh Shilimkar <santosh.shilimkar@ti.com>");
diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c
index e7e840fb74ea..349540469fc0 100644
--- a/drivers/clk/keystone/pll.c
+++ b/drivers/clk/keystone/pll.c
@@ -219,7 +219,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)
219 } 219 }
220 220
221out: 221out:
222 pr_err("%s: error initializing pll %s\n", __func__, node->name); 222 pr_err("%s: error initializing pll %pOFn\n", __func__, node);
223 kfree(pll_data); 223 kfree(pll_data);
224} 224}
225 225
@@ -338,3 +338,8 @@ static void __init of_pll_mux_clk_init(struct device_node *node)
338 pr_err("%s: error registering mux %s\n", __func__, clk_name); 338 pr_err("%s: error registering mux %s\n", __func__, clk_name);
339} 339}
340CLK_OF_DECLARE(pll_mux_clock, "ti,keystone,pll-mux-clock", of_pll_mux_clk_init); 340CLK_OF_DECLARE(pll_mux_clock, "ti,keystone,pll-mux-clock", of_pll_mux_clk_init);
341
342MODULE_LICENSE("GPL");
343MODULE_DESCRIPTION("PLL clock driver for Keystone devices");
344MODULE_AUTHOR("Murali Karicheri <m-karicheri2@ti.com>");
345MODULE_AUTHOR("Santosh Shilimkar <santosh.shilimkar@ti.com>");
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 4dda8988b2f0..ab6ab07f53e6 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -249,11 +249,6 @@ static const char * const msdc30_parents[] = {
249 "univpll2_d4" 249 "univpll2_d4"
250}; 250};
251 251
252static const char * const audio_parents[] = {
253 "clk26m",
254 "syspll1_d16"
255};
256
257static const char * const aud_intbus_parents[] = { 252static const char * const aud_intbus_parents[] = {
258 "clk26m", 253 "clk26m",
259 "syspll1_d4", 254 "syspll1_d4",
diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index a0ed41e73bde..5f6c860aa122 100644
--- a/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
@@ -101,10 +101,16 @@ static const char * const mst_mux_parent_names[] = {
101 "axg_mst_in4", "axg_mst_in5", "axg_mst_in6", "axg_mst_in7", 101 "axg_mst_in4", "axg_mst_in5", "axg_mst_in6", "axg_mst_in7",
102}; 102};
103 103
104#define AXG_MST_MCLK_MUX(_name, _reg) \ 104#define AXG_MST_MUX(_name, _reg, _flag) \
105 AXG_AUD_MUX(_name##_sel, _reg, 0x7, 24, CLK_MUX_ROUND_CLOSEST, \ 105 AXG_AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \
106 mst_mux_parent_names, CLK_SET_RATE_PARENT) 106 mst_mux_parent_names, CLK_SET_RATE_PARENT)
107 107
108#define AXG_MST_MCLK_MUX(_name, _reg) \
109 AXG_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
110
111#define AXG_MST_SYS_MUX(_name, _reg) \
112 AXG_MST_MUX(_name, _reg, 0)
113
108static AXG_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL); 114static AXG_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
109static AXG_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL); 115static AXG_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL);
110static AXG_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL); 116static AXG_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL);
@@ -112,13 +118,19 @@ static AXG_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL);
112static AXG_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL); 118static AXG_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL);
113static AXG_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL); 119static AXG_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL);
114static AXG_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL); 120static AXG_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
115static AXG_MST_MCLK_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
116static AXG_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0); 121static AXG_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
117static AXG_MST_MCLK_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1); 122static AXG_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
123static AXG_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
124
125#define AXG_MST_DIV(_name, _reg, _flag) \
126 AXG_AUD_DIV(_name##_div, _reg, 0, 16, _flag, \
127 "axg_"#_name"_sel", CLK_SET_RATE_PARENT) \
128
129#define AXG_MST_MCLK_DIV(_name, _reg) \
130 AXG_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
118 131
119#define AXG_MST_MCLK_DIV(_name, _reg) \ 132#define AXG_MST_SYS_DIV(_name, _reg) \
120 AXG_AUD_DIV(_name##_div, _reg, 0, 16, CLK_DIVIDER_ROUND_CLOSEST, \ 133 AXG_MST_DIV(_name, _reg, 0)
121 "axg_"#_name"_sel", CLK_SET_RATE_PARENT) \
122 134
123static AXG_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL); 135static AXG_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL);
124static AXG_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL); 136static AXG_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL);
@@ -127,12 +139,12 @@ static AXG_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL);
127static AXG_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL); 139static AXG_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL);
128static AXG_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL); 140static AXG_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL);
129static AXG_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL); 141static AXG_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
130static AXG_MST_MCLK_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
131static AXG_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0); 142static AXG_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
132static AXG_MST_MCLK_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1); 143static AXG_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
144static AXG_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
133 145
134#define AXG_MST_MCLK_GATE(_name, _reg) \ 146#define AXG_MST_MCLK_GATE(_name, _reg) \
135 AXG_AUD_GATE(_name, _reg, 31, "axg_"#_name"_div", \ 147 AXG_AUD_GATE(_name, _reg, 31, "axg_"#_name"_div", \
136 CLK_SET_RATE_PARENT) 148 CLK_SET_RATE_PARENT)
137 149
138static AXG_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL); 150static AXG_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 00ce62ad6416..c981159b02c0 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -22,8 +22,13 @@
22 22
23static DEFINE_SPINLOCK(meson_clk_lock); 23static DEFINE_SPINLOCK(meson_clk_lock);
24 24
25static struct clk_regmap axg_fixed_pll = { 25static struct clk_regmap axg_fixed_pll_dco = {
26 .data = &(struct meson_clk_pll_data){ 26 .data = &(struct meson_clk_pll_data){
27 .en = {
28 .reg_off = HHI_MPLL_CNTL,
29 .shift = 30,
30 .width = 1,
31 },
27 .m = { 32 .m = {
28 .reg_off = HHI_MPLL_CNTL, 33 .reg_off = HHI_MPLL_CNTL,
29 .shift = 0, 34 .shift = 0,
@@ -34,11 +39,6 @@ static struct clk_regmap axg_fixed_pll = {
34 .shift = 9, 39 .shift = 9,
35 .width = 5, 40 .width = 5,
36 }, 41 },
37 .od = {
38 .reg_off = HHI_MPLL_CNTL,
39 .shift = 16,
40 .width = 2,
41 },
42 .frac = { 42 .frac = {
43 .reg_off = HHI_MPLL_CNTL2, 43 .reg_off = HHI_MPLL_CNTL2,
44 .shift = 0, 44 .shift = 0,
@@ -56,15 +56,39 @@ static struct clk_regmap axg_fixed_pll = {
56 }, 56 },
57 }, 57 },
58 .hw.init = &(struct clk_init_data){ 58 .hw.init = &(struct clk_init_data){
59 .name = "fixed_pll", 59 .name = "fixed_pll_dco",
60 .ops = &meson_clk_pll_ro_ops, 60 .ops = &meson_clk_pll_ro_ops,
61 .parent_names = (const char *[]){ "xtal" }, 61 .parent_names = (const char *[]){ "xtal" },
62 .num_parents = 1, 62 .num_parents = 1,
63 }, 63 },
64}; 64};
65 65
66static struct clk_regmap axg_sys_pll = { 66static struct clk_regmap axg_fixed_pll = {
67 .data = &(struct clk_regmap_div_data){
68 .offset = HHI_MPLL_CNTL,
69 .shift = 16,
70 .width = 2,
71 .flags = CLK_DIVIDER_POWER_OF_TWO,
72 },
73 .hw.init = &(struct clk_init_data){
74 .name = "fixed_pll",
75 .ops = &clk_regmap_divider_ro_ops,
76 .parent_names = (const char *[]){ "fixed_pll_dco" },
77 .num_parents = 1,
78 /*
79 * This clock won't ever change at runtime so
80 * CLK_SET_RATE_PARENT is not required
81 */
82 },
83};
84
85static struct clk_regmap axg_sys_pll_dco = {
67 .data = &(struct meson_clk_pll_data){ 86 .data = &(struct meson_clk_pll_data){
87 .en = {
88 .reg_off = HHI_SYS_PLL_CNTL,
89 .shift = 30,
90 .width = 1,
91 },
68 .m = { 92 .m = {
69 .reg_off = HHI_SYS_PLL_CNTL, 93 .reg_off = HHI_SYS_PLL_CNTL,
70 .shift = 0, 94 .shift = 0,
@@ -75,11 +99,6 @@ static struct clk_regmap axg_sys_pll = {
75 .shift = 9, 99 .shift = 9,
76 .width = 5, 100 .width = 5,
77 }, 101 },
78 .od = {
79 .reg_off = HHI_SYS_PLL_CNTL,
80 .shift = 16,
81 .width = 2,
82 },
83 .l = { 102 .l = {
84 .reg_off = HHI_SYS_PLL_CNTL, 103 .reg_off = HHI_SYS_PLL_CNTL,
85 .shift = 31, 104 .shift = 31,
@@ -92,102 +111,59 @@ static struct clk_regmap axg_sys_pll = {
92 }, 111 },
93 }, 112 },
94 .hw.init = &(struct clk_init_data){ 113 .hw.init = &(struct clk_init_data){
95 .name = "sys_pll", 114 .name = "sys_pll_dco",
96 .ops = &meson_clk_pll_ro_ops, 115 .ops = &meson_clk_pll_ro_ops,
97 .parent_names = (const char *[]){ "xtal" }, 116 .parent_names = (const char *[]){ "xtal" },
98 .num_parents = 1, 117 .num_parents = 1,
99 .flags = CLK_GET_RATE_NOCACHE,
100 }, 118 },
101}; 119};
102 120
103static const struct pll_rate_table axg_gp0_pll_rate_table[] = { 121static struct clk_regmap axg_sys_pll = {
104 PLL_RATE(240000000, 40, 1, 2), 122 .data = &(struct clk_regmap_div_data){
105 PLL_RATE(246000000, 41, 1, 2), 123 .offset = HHI_SYS_PLL_CNTL,
106 PLL_RATE(252000000, 42, 1, 2), 124 .shift = 16,
107 PLL_RATE(258000000, 43, 1, 2), 125 .width = 2,
108 PLL_RATE(264000000, 44, 1, 2), 126 .flags = CLK_DIVIDER_POWER_OF_TWO,
109 PLL_RATE(270000000, 45, 1, 2), 127 },
110 PLL_RATE(276000000, 46, 1, 2), 128 .hw.init = &(struct clk_init_data){
111 PLL_RATE(282000000, 47, 1, 2), 129 .name = "sys_pll",
112 PLL_RATE(288000000, 48, 1, 2), 130 .ops = &clk_regmap_divider_ro_ops,
113 PLL_RATE(294000000, 49, 1, 2), 131 .parent_names = (const char *[]){ "sys_pll_dco" },
114 PLL_RATE(300000000, 50, 1, 2), 132 .num_parents = 1,
115 PLL_RATE(306000000, 51, 1, 2), 133 .flags = CLK_SET_RATE_PARENT,
116 PLL_RATE(312000000, 52, 1, 2), 134 },
117 PLL_RATE(318000000, 53, 1, 2), 135};
118 PLL_RATE(324000000, 54, 1, 2), 136
119 PLL_RATE(330000000, 55, 1, 2), 137static const struct pll_params_table axg_gp0_pll_params_table[] = {
120 PLL_RATE(336000000, 56, 1, 2), 138 PLL_PARAMS(40, 1),
121 PLL_RATE(342000000, 57, 1, 2), 139 PLL_PARAMS(41, 1),
122 PLL_RATE(348000000, 58, 1, 2), 140 PLL_PARAMS(42, 1),
123 PLL_RATE(354000000, 59, 1, 2), 141 PLL_PARAMS(43, 1),
124 PLL_RATE(360000000, 60, 1, 2), 142 PLL_PARAMS(44, 1),
125 PLL_RATE(366000000, 61, 1, 2), 143 PLL_PARAMS(45, 1),
126 PLL_RATE(372000000, 62, 1, 2), 144 PLL_PARAMS(46, 1),
127 PLL_RATE(378000000, 63, 1, 2), 145 PLL_PARAMS(47, 1),
128 PLL_RATE(384000000, 64, 1, 2), 146 PLL_PARAMS(48, 1),
129 PLL_RATE(390000000, 65, 1, 3), 147 PLL_PARAMS(49, 1),
130 PLL_RATE(396000000, 66, 1, 3), 148 PLL_PARAMS(50, 1),
131 PLL_RATE(402000000, 67, 1, 3), 149 PLL_PARAMS(51, 1),
132 PLL_RATE(408000000, 68, 1, 3), 150 PLL_PARAMS(52, 1),
133 PLL_RATE(480000000, 40, 1, 1), 151 PLL_PARAMS(53, 1),
134 PLL_RATE(492000000, 41, 1, 1), 152 PLL_PARAMS(54, 1),
135 PLL_RATE(504000000, 42, 1, 1), 153 PLL_PARAMS(55, 1),
136 PLL_RATE(516000000, 43, 1, 1), 154 PLL_PARAMS(56, 1),
137 PLL_RATE(528000000, 44, 1, 1), 155 PLL_PARAMS(57, 1),
138 PLL_RATE(540000000, 45, 1, 1), 156 PLL_PARAMS(58, 1),
139 PLL_RATE(552000000, 46, 1, 1), 157 PLL_PARAMS(59, 1),
140 PLL_RATE(564000000, 47, 1, 1), 158 PLL_PARAMS(60, 1),
141 PLL_RATE(576000000, 48, 1, 1), 159 PLL_PARAMS(61, 1),
142 PLL_RATE(588000000, 49, 1, 1), 160 PLL_PARAMS(62, 1),
143 PLL_RATE(600000000, 50, 1, 1), 161 PLL_PARAMS(63, 1),
144 PLL_RATE(612000000, 51, 1, 1), 162 PLL_PARAMS(64, 1),
145 PLL_RATE(624000000, 52, 1, 1), 163 PLL_PARAMS(65, 1),
146 PLL_RATE(636000000, 53, 1, 1), 164 PLL_PARAMS(66, 1),
147 PLL_RATE(648000000, 54, 1, 1), 165 PLL_PARAMS(67, 1),
148 PLL_RATE(660000000, 55, 1, 1), 166 PLL_PARAMS(68, 1),
149 PLL_RATE(672000000, 56, 1, 1),
150 PLL_RATE(684000000, 57, 1, 1),
151 PLL_RATE(696000000, 58, 1, 1),
152 PLL_RATE(708000000, 59, 1, 1),
153 PLL_RATE(720000000, 60, 1, 1),
154 PLL_RATE(732000000, 61, 1, 1),
155 PLL_RATE(744000000, 62, 1, 1),
156 PLL_RATE(756000000, 63, 1, 1),
157 PLL_RATE(768000000, 64, 1, 1),
158 PLL_RATE(780000000, 65, 1, 1),
159 PLL_RATE(792000000, 66, 1, 1),
160 PLL_RATE(804000000, 67, 1, 1),
161 PLL_RATE(816000000, 68, 1, 1),
162 PLL_RATE(960000000, 40, 1, 0),
163 PLL_RATE(984000000, 41, 1, 0),
164 PLL_RATE(1008000000, 42, 1, 0),
165 PLL_RATE(1032000000, 43, 1, 0),
166 PLL_RATE(1056000000, 44, 1, 0),
167 PLL_RATE(1080000000, 45, 1, 0),
168 PLL_RATE(1104000000, 46, 1, 0),
169 PLL_RATE(1128000000, 47, 1, 0),
170 PLL_RATE(1152000000, 48, 1, 0),
171 PLL_RATE(1176000000, 49, 1, 0),
172 PLL_RATE(1200000000, 50, 1, 0),
173 PLL_RATE(1224000000, 51, 1, 0),
174 PLL_RATE(1248000000, 52, 1, 0),
175 PLL_RATE(1272000000, 53, 1, 0),
176 PLL_RATE(1296000000, 54, 1, 0),
177 PLL_RATE(1320000000, 55, 1, 0),
178 PLL_RATE(1344000000, 56, 1, 0),
179 PLL_RATE(1368000000, 57, 1, 0),
180 PLL_RATE(1392000000, 58, 1, 0),
181 PLL_RATE(1416000000, 59, 1, 0),
182 PLL_RATE(1440000000, 60, 1, 0),
183 PLL_RATE(1464000000, 61, 1, 0),
184 PLL_RATE(1488000000, 62, 1, 0),
185 PLL_RATE(1512000000, 63, 1, 0),
186 PLL_RATE(1536000000, 64, 1, 0),
187 PLL_RATE(1560000000, 65, 1, 0),
188 PLL_RATE(1584000000, 66, 1, 0),
189 PLL_RATE(1608000000, 67, 1, 0),
190 PLL_RATE(1632000000, 68, 1, 0),
191 { /* sentinel */ }, 167 { /* sentinel */ },
192}; 168};
193 169
@@ -197,11 +173,15 @@ static const struct reg_sequence axg_gp0_init_regs[] = {
197 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, 173 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
198 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, 174 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
199 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, 175 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
200 { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 },
201}; 176};
202 177
203static struct clk_regmap axg_gp0_pll = { 178static struct clk_regmap axg_gp0_pll_dco = {
204 .data = &(struct meson_clk_pll_data){ 179 .data = &(struct meson_clk_pll_data){
180 .en = {
181 .reg_off = HHI_GP0_PLL_CNTL,
182 .shift = 30,
183 .width = 1,
184 },
205 .m = { 185 .m = {
206 .reg_off = HHI_GP0_PLL_CNTL, 186 .reg_off = HHI_GP0_PLL_CNTL,
207 .shift = 0, 187 .shift = 0,
@@ -212,11 +192,6 @@ static struct clk_regmap axg_gp0_pll = {
212 .shift = 9, 192 .shift = 9,
213 .width = 5, 193 .width = 5,
214 }, 194 },
215 .od = {
216 .reg_off = HHI_GP0_PLL_CNTL,
217 .shift = 16,
218 .width = 2,
219 },
220 .frac = { 195 .frac = {
221 .reg_off = HHI_GP0_PLL_CNTL1, 196 .reg_off = HHI_GP0_PLL_CNTL1,
222 .shift = 0, 197 .shift = 0,
@@ -232,29 +207,49 @@ static struct clk_regmap axg_gp0_pll = {
232 .shift = 29, 207 .shift = 29,
233 .width = 1, 208 .width = 1,
234 }, 209 },
235 .table = axg_gp0_pll_rate_table, 210 .table = axg_gp0_pll_params_table,
236 .init_regs = axg_gp0_init_regs, 211 .init_regs = axg_gp0_init_regs,
237 .init_count = ARRAY_SIZE(axg_gp0_init_regs), 212 .init_count = ARRAY_SIZE(axg_gp0_init_regs),
238 }, 213 },
239 .hw.init = &(struct clk_init_data){ 214 .hw.init = &(struct clk_init_data){
240 .name = "gp0_pll", 215 .name = "gp0_pll_dco",
241 .ops = &meson_clk_pll_ops, 216 .ops = &meson_clk_pll_ops,
242 .parent_names = (const char *[]){ "xtal" }, 217 .parent_names = (const char *[]){ "xtal" },
243 .num_parents = 1, 218 .num_parents = 1,
244 }, 219 },
245}; 220};
246 221
222static struct clk_regmap axg_gp0_pll = {
223 .data = &(struct clk_regmap_div_data){
224 .offset = HHI_GP0_PLL_CNTL,
225 .shift = 16,
226 .width = 2,
227 .flags = CLK_DIVIDER_POWER_OF_TWO,
228 },
229 .hw.init = &(struct clk_init_data){
230 .name = "gp0_pll",
231 .ops = &clk_regmap_divider_ops,
232 .parent_names = (const char *[]){ "gp0_pll_dco" },
233 .num_parents = 1,
234 .flags = CLK_SET_RATE_PARENT,
235 },
236};
237
247static const struct reg_sequence axg_hifi_init_regs[] = { 238static const struct reg_sequence axg_hifi_init_regs[] = {
248 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 }, 239 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 },
249 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be }, 240 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be },
250 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 }, 241 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 },
251 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d }, 242 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d },
252 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 }, 243 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 },
253 { .reg = HHI_HIFI_PLL_CNTL, .def = 0x40010250 },
254}; 244};
255 245
256static struct clk_regmap axg_hifi_pll = { 246static struct clk_regmap axg_hifi_pll_dco = {
257 .data = &(struct meson_clk_pll_data){ 247 .data = &(struct meson_clk_pll_data){
248 .en = {
249 .reg_off = HHI_HIFI_PLL_CNTL,
250 .shift = 30,
251 .width = 1,
252 },
258 .m = { 253 .m = {
259 .reg_off = HHI_HIFI_PLL_CNTL, 254 .reg_off = HHI_HIFI_PLL_CNTL,
260 .shift = 0, 255 .shift = 0,
@@ -265,11 +260,6 @@ static struct clk_regmap axg_hifi_pll = {
265 .shift = 9, 260 .shift = 9,
266 .width = 5, 261 .width = 5,
267 }, 262 },
268 .od = {
269 .reg_off = HHI_HIFI_PLL_CNTL,
270 .shift = 16,
271 .width = 2,
272 },
273 .frac = { 263 .frac = {
274 .reg_off = HHI_HIFI_PLL_CNTL5, 264 .reg_off = HHI_HIFI_PLL_CNTL5,
275 .shift = 0, 265 .shift = 0,
@@ -285,19 +275,35 @@ static struct clk_regmap axg_hifi_pll = {
285 .shift = 29, 275 .shift = 29,
286 .width = 1, 276 .width = 1,
287 }, 277 },
288 .table = axg_gp0_pll_rate_table, 278 .table = axg_gp0_pll_params_table,
289 .init_regs = axg_hifi_init_regs, 279 .init_regs = axg_hifi_init_regs,
290 .init_count = ARRAY_SIZE(axg_hifi_init_regs), 280 .init_count = ARRAY_SIZE(axg_hifi_init_regs),
291 .flags = CLK_MESON_PLL_ROUND_CLOSEST, 281 .flags = CLK_MESON_PLL_ROUND_CLOSEST,
292 }, 282 },
293 .hw.init = &(struct clk_init_data){ 283 .hw.init = &(struct clk_init_data){
294 .name = "hifi_pll", 284 .name = "hifi_pll_dco",
295 .ops = &meson_clk_pll_ops, 285 .ops = &meson_clk_pll_ops,
296 .parent_names = (const char *[]){ "xtal" }, 286 .parent_names = (const char *[]){ "xtal" },
297 .num_parents = 1, 287 .num_parents = 1,
298 }, 288 },
299}; 289};
300 290
291static struct clk_regmap axg_hifi_pll = {
292 .data = &(struct clk_regmap_div_data){
293 .offset = HHI_HIFI_PLL_CNTL,
294 .shift = 16,
295 .width = 2,
296 .flags = CLK_DIVIDER_POWER_OF_TWO,
297 },
298 .hw.init = &(struct clk_init_data){
299 .name = "hifi_pll",
300 .ops = &clk_regmap_divider_ops,
301 .parent_names = (const char *[]){ "hifi_pll_dco" },
302 .num_parents = 1,
303 .flags = CLK_SET_RATE_PARENT,
304 },
305};
306
301static struct clk_fixed_factor axg_fclk_div2_div = { 307static struct clk_fixed_factor axg_fclk_div2_div = {
302 .mult = 1, 308 .mult = 1,
303 .div = 2, 309 .div = 2,
@@ -625,29 +631,31 @@ static struct clk_regmap axg_mpll3 = {
625 }, 631 },
626}; 632};
627 633
628static const struct pll_rate_table axg_pcie_pll_rate_table[] = { 634static const struct pll_params_table axg_pcie_pll_params_table[] = {
629 { 635 {
630 .rate = 100000000, 636 .m = 200,
631 .m = 200, 637 .n = 3,
632 .n = 3,
633 .od = 1,
634 .od2 = 3,
635 }, 638 },
636 { /* sentinel */ }, 639 { /* sentinel */ },
637}; 640};
638 641
639static const struct reg_sequence axg_pcie_init_regs[] = { 642static const struct reg_sequence axg_pcie_init_regs[] = {
640 { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 },
641 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa }, 643 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa },
642 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be }, 644 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be },
643 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e }, 645 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e },
644 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0xc000004d }, 646 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0xc000004d },
645 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x00078000 }, 647 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x00078000 },
646 { .reg = HHI_PCIE_PLL_CNTL6, .def = 0x002323c6 }, 648 { .reg = HHI_PCIE_PLL_CNTL6, .def = 0x002323c6 },
649 { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 },
647}; 650};
648 651
649static struct clk_regmap axg_pcie_pll = { 652static struct clk_regmap axg_pcie_pll_dco = {
650 .data = &(struct meson_clk_pll_data){ 653 .data = &(struct meson_clk_pll_data){
654 .en = {
655 .reg_off = HHI_PCIE_PLL_CNTL,
656 .shift = 30,
657 .width = 1,
658 },
651 .m = { 659 .m = {
652 .reg_off = HHI_PCIE_PLL_CNTL, 660 .reg_off = HHI_PCIE_PLL_CNTL,
653 .shift = 0, 661 .shift = 0,
@@ -658,16 +666,6 @@ static struct clk_regmap axg_pcie_pll = {
658 .shift = 9, 666 .shift = 9,
659 .width = 5, 667 .width = 5,
660 }, 668 },
661 .od = {
662 .reg_off = HHI_PCIE_PLL_CNTL,
663 .shift = 16,
664 .width = 2,
665 },
666 .od2 = {
667 .reg_off = HHI_PCIE_PLL_CNTL6,
668 .shift = 6,
669 .width = 2,
670 },
671 .frac = { 669 .frac = {
672 .reg_off = HHI_PCIE_PLL_CNTL1, 670 .reg_off = HHI_PCIE_PLL_CNTL1,
673 .shift = 0, 671 .shift = 0,
@@ -683,29 +681,63 @@ static struct clk_regmap axg_pcie_pll = {
683 .shift = 29, 681 .shift = 29,
684 .width = 1, 682 .width = 1,
685 }, 683 },
686 .table = axg_pcie_pll_rate_table, 684 .table = axg_pcie_pll_params_table,
687 .init_regs = axg_pcie_init_regs, 685 .init_regs = axg_pcie_init_regs,
688 .init_count = ARRAY_SIZE(axg_pcie_init_regs), 686 .init_count = ARRAY_SIZE(axg_pcie_init_regs),
689 }, 687 },
690 .hw.init = &(struct clk_init_data){ 688 .hw.init = &(struct clk_init_data){
691 .name = "pcie_pll", 689 .name = "pcie_pll_dco",
692 .ops = &meson_clk_pll_ops, 690 .ops = &meson_clk_pll_ops,
693 .parent_names = (const char *[]){ "xtal" }, 691 .parent_names = (const char *[]){ "xtal" },
694 .num_parents = 1, 692 .num_parents = 1,
695 }, 693 },
696}; 694};
697 695
696static struct clk_regmap axg_pcie_pll_od = {
697 .data = &(struct clk_regmap_div_data){
698 .offset = HHI_PCIE_PLL_CNTL,
699 .shift = 16,
700 .width = 2,
701 .flags = CLK_DIVIDER_POWER_OF_TWO,
702 },
703 .hw.init = &(struct clk_init_data){
704 .name = "pcie_pll_od",
705 .ops = &clk_regmap_divider_ops,
706 .parent_names = (const char *[]){ "pcie_pll_dco" },
707 .num_parents = 1,
708 .flags = CLK_SET_RATE_PARENT,
709 },
710};
711
712static struct clk_regmap axg_pcie_pll = {
713 .data = &(struct clk_regmap_div_data){
714 .offset = HHI_PCIE_PLL_CNTL6,
715 .shift = 6,
716 .width = 2,
717 .flags = CLK_DIVIDER_POWER_OF_TWO,
718 },
719 .hw.init = &(struct clk_init_data){
720 .name = "pcie_pll",
721 .ops = &clk_regmap_divider_ops,
722 .parent_names = (const char *[]){ "pcie_pll_od" },
723 .num_parents = 1,
724 .flags = CLK_SET_RATE_PARENT,
725 },
726};
727
698static struct clk_regmap axg_pcie_mux = { 728static struct clk_regmap axg_pcie_mux = {
699 .data = &(struct clk_regmap_mux_data){ 729 .data = &(struct clk_regmap_mux_data){
700 .offset = HHI_PCIE_PLL_CNTL6, 730 .offset = HHI_PCIE_PLL_CNTL6,
701 .mask = 0x1, 731 .mask = 0x1,
702 .shift = 2, 732 .shift = 2,
733 /* skip the parent mpll3, reserved for debug */
734 .table = (u32[]){ 1 },
703 }, 735 },
704 .hw.init = &(struct clk_init_data){ 736 .hw.init = &(struct clk_init_data){
705 .name = "pcie_mux", 737 .name = "pcie_mux",
706 .ops = &clk_regmap_mux_ops, 738 .ops = &clk_regmap_mux_ops,
707 .parent_names = (const char *[]){ "mpll3", "pcie_pll" }, 739 .parent_names = (const char *[]){ "pcie_pll" },
708 .num_parents = 2, 740 .num_parents = 1,
709 .flags = CLK_SET_RATE_PARENT, 741 .flags = CLK_SET_RATE_PARENT,
710 }, 742 },
711}; 743};
@@ -1107,6 +1139,12 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = {
1107 [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw, 1139 [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
1108 [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw, 1140 [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
1109 [CLKID_GEN_CLK] = &axg_gen_clk.hw, 1141 [CLKID_GEN_CLK] = &axg_gen_clk.hw,
1142 [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw,
1143 [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw,
1144 [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw,
1145 [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw,
1146 [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw,
1147 [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw,
1110 [NR_CLKS] = NULL, 1148 [NR_CLKS] = NULL,
1111 }, 1149 },
1112 .num = NR_CLKS, 1150 .num = NR_CLKS,
@@ -1185,6 +1223,8 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
1185 &axg_fclk_div4, 1223 &axg_fclk_div4,
1186 &axg_fclk_div5, 1224 &axg_fclk_div5,
1187 &axg_fclk_div7, 1225 &axg_fclk_div7,
1226 &axg_pcie_pll_dco,
1227 &axg_pcie_pll_od,
1188 &axg_pcie_pll, 1228 &axg_pcie_pll,
1189 &axg_pcie_mux, 1229 &axg_pcie_mux,
1190 &axg_pcie_ref, 1230 &axg_pcie_ref,
@@ -1194,6 +1234,12 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
1194 &axg_gen_clk_sel, 1234 &axg_gen_clk_sel,
1195 &axg_gen_clk_div, 1235 &axg_gen_clk_div,
1196 &axg_gen_clk, 1236 &axg_gen_clk,
1237 &axg_fixed_pll_dco,
1238 &axg_sys_pll_dco,
1239 &axg_gp0_pll_dco,
1240 &axg_hifi_pll_dco,
1241 &axg_pcie_pll_dco,
1242 &axg_pcie_pll_od,
1197}; 1243};
1198 1244
1199static const struct of_device_id clkc_match_table[] = { 1245static const struct of_device_id clkc_match_table[] = {
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h
index 1d04144a1b2c..0431dabac629 100644
--- a/drivers/clk/meson/axg.h
+++ b/drivers/clk/meson/axg.h
@@ -133,8 +133,14 @@
133#define CLKID_PCIE_REF 78 133#define CLKID_PCIE_REF 78
134#define CLKID_GEN_CLK_SEL 82 134#define CLKID_GEN_CLK_SEL 82
135#define CLKID_GEN_CLK_DIV 83 135#define CLKID_GEN_CLK_DIV 83
136#define CLKID_SYS_PLL_DCO 85
137#define CLKID_FIXED_PLL_DCO 86
138#define CLKID_GP0_PLL_DCO 87
139#define CLKID_HIFI_PLL_DCO 88
140#define CLKID_PCIE_PLL_DCO 89
141#define CLKID_PCIE_PLL_OD 90
136 142
137#define NR_CLKS 85 143#define NR_CLKS 91
138 144
139/* include the CLKIDs that have been made part of the DT binding */ 145/* include the CLKIDs that have been made part of the DT binding */
140#include <dt-bindings/clock/axg-clkc.h> 146#include <dt-bindings/clock/axg-clkc.h>
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 3e04617ac47f..f5b5b3fabe3c 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -11,15 +11,19 @@
11 * In the most basic form, a Meson PLL is composed as follows: 11 * In the most basic form, a Meson PLL is composed as follows:
12 * 12 *
13 * PLL 13 * PLL
14 * +------------------------------+ 14 * +--------------------------------+
15 * | | 15 * | |
16 * in -----[ /N ]---[ *M ]---[ >>OD ]----->> out 16 * | +--+ |
17 * | ^ ^ | 17 * in >>-----[ /N ]--->| | +-----+ |
18 * +------------------------------+ 18 * | | |------| DCO |---->> out
19 * | | 19 * | +--------->| | +--v--+ |
20 * FREF VCO 20 * | | +--+ | |
21 * | | | |
22 * | +--[ *(M + (F/Fmax) ]<--+ |
23 * | |
24 * +--------------------------------+
21 * 25 *
22 * out = in * (m + frac / frac_max) / (n << sum(ods)) 26 * out = in * (m + frac / frac_max) / n
23 */ 27 */
24 28
25#include <linux/clk-provider.h> 29#include <linux/clk-provider.h>
@@ -41,12 +45,11 @@ meson_clk_pll_data(struct clk_regmap *clk)
41} 45}
42 46
43static unsigned long __pll_params_to_rate(unsigned long parent_rate, 47static unsigned long __pll_params_to_rate(unsigned long parent_rate,
44 const struct pll_rate_table *pllt, 48 const struct pll_params_table *pllt,
45 u16 frac, 49 u16 frac,
46 struct meson_clk_pll_data *pll) 50 struct meson_clk_pll_data *pll)
47{ 51{
48 u64 rate = (u64)parent_rate * pllt->m; 52 u64 rate = (u64)parent_rate * pllt->m;
49 unsigned int od = pllt->od + pllt->od2 + pllt->od3;
50 53
51 if (frac && MESON_PARM_APPLICABLE(&pll->frac)) { 54 if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {
52 u64 frac_rate = (u64)parent_rate * frac; 55 u64 frac_rate = (u64)parent_rate * frac;
@@ -55,7 +58,7 @@ static unsigned long __pll_params_to_rate(unsigned long parent_rate,
55 (1 << pll->frac.width)); 58 (1 << pll->frac.width));
56 } 59 }
57 60
58 return DIV_ROUND_UP_ULL(rate, pllt->n << od); 61 return DIV_ROUND_UP_ULL(rate, pllt->n);
59} 62}
60 63
61static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, 64static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
@@ -63,20 +66,11 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
63{ 66{
64 struct clk_regmap *clk = to_clk_regmap(hw); 67 struct clk_regmap *clk = to_clk_regmap(hw);
65 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); 68 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
66 struct pll_rate_table pllt; 69 struct pll_params_table pllt;
67 u16 frac; 70 u16 frac;
68 71
69 pllt.n = meson_parm_read(clk->map, &pll->n); 72 pllt.n = meson_parm_read(clk->map, &pll->n);
70 pllt.m = meson_parm_read(clk->map, &pll->m); 73 pllt.m = meson_parm_read(clk->map, &pll->m);
71 pllt.od = meson_parm_read(clk->map, &pll->od);
72
73 pllt.od2 = MESON_PARM_APPLICABLE(&pll->od2) ?
74 meson_parm_read(clk->map, &pll->od2) :
75 0;
76
77 pllt.od3 = MESON_PARM_APPLICABLE(&pll->od3) ?
78 meson_parm_read(clk->map, &pll->od3) :
79 0;
80 74
81 frac = MESON_PARM_APPLICABLE(&pll->frac) ? 75 frac = MESON_PARM_APPLICABLE(&pll->frac) ?
82 meson_parm_read(clk->map, &pll->frac) : 76 meson_parm_read(clk->map, &pll->frac) :
@@ -87,14 +81,12 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
87 81
88static u16 __pll_params_with_frac(unsigned long rate, 82static u16 __pll_params_with_frac(unsigned long rate,
89 unsigned long parent_rate, 83 unsigned long parent_rate,
90 const struct pll_rate_table *pllt, 84 const struct pll_params_table *pllt,
91 struct meson_clk_pll_data *pll) 85 struct meson_clk_pll_data *pll)
92{ 86{
93 u16 frac_max = (1 << pll->frac.width); 87 u16 frac_max = (1 << pll->frac.width);
94 u64 val = (u64)rate * pllt->n; 88 u64 val = (u64)rate * pllt->n;
95 89
96 val <<= pllt->od + pllt->od2 + pllt->od3;
97
98 if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) 90 if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST)
99 val = DIV_ROUND_CLOSEST_ULL(val * frac_max, parent_rate); 91 val = DIV_ROUND_CLOSEST_ULL(val * frac_max, parent_rate);
100 else 92 else
@@ -105,29 +97,50 @@ static u16 __pll_params_with_frac(unsigned long rate,
105 return min((u16)val, (u16)(frac_max - 1)); 97 return min((u16)val, (u16)(frac_max - 1));
106} 98}
107 99
108static const struct pll_rate_table * 100static bool meson_clk_pll_is_better(unsigned long rate,
101 unsigned long best,
102 unsigned long now,
103 struct meson_clk_pll_data *pll)
104{
105 if (!(pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) ||
106 MESON_PARM_APPLICABLE(&pll->frac)) {
107 /* Round down */
108 if (now < rate && best < now)
109 return true;
110 } else {
111 /* Round Closest */
112 if (abs(now - rate) < abs(best - rate))
113 return true;
114 }
115
116 return false;
117}
118
119static const struct pll_params_table *
109meson_clk_get_pll_settings(unsigned long rate, 120meson_clk_get_pll_settings(unsigned long rate,
121 unsigned long parent_rate,
110 struct meson_clk_pll_data *pll) 122 struct meson_clk_pll_data *pll)
111{ 123{
112 const struct pll_rate_table *table = pll->table; 124 const struct pll_params_table *table = pll->table;
113 unsigned int i = 0; 125 unsigned long best = 0, now = 0;
126 unsigned int i, best_i = 0;
114 127
115 if (!table) 128 if (!table)
116 return NULL; 129 return NULL;
117 130
118 /* Find the first table element exceeding rate */ 131 for (i = 0; table[i].n; i++) {
119 while (table[i].rate && table[i].rate <= rate) 132 now = __pll_params_to_rate(parent_rate, &table[i], 0, pll);
120 i++;
121 133
122 if (i != 0) { 134 /* If we get an exact match, don't bother any further */
123 if (MESON_PARM_APPLICABLE(&pll->frac) || 135 if (now == rate) {
124 !(pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) || 136 return &table[i];
125 (abs(rate - table[i - 1].rate) < 137 } else if (meson_clk_pll_is_better(rate, best, now, pll)) {
126 abs(rate - table[i].rate))) 138 best = now;
127 i--; 139 best_i = i;
140 }
128 } 141 }
129 142
130 return (struct pll_rate_table *)&table[i]; 143 return (struct pll_params_table *)&table[best_i];
131} 144}
132 145
133static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, 146static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -135,16 +148,18 @@ static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
135{ 148{
136 struct clk_regmap *clk = to_clk_regmap(hw); 149 struct clk_regmap *clk = to_clk_regmap(hw);
137 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); 150 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
138 const struct pll_rate_table *pllt = 151 const struct pll_params_table *pllt =
139 meson_clk_get_pll_settings(rate, pll); 152 meson_clk_get_pll_settings(rate, *parent_rate, pll);
153 unsigned long round;
140 u16 frac; 154 u16 frac;
141 155
142 if (!pllt) 156 if (!pllt)
143 return meson_clk_pll_recalc_rate(hw, *parent_rate); 157 return meson_clk_pll_recalc_rate(hw, *parent_rate);
144 158
145 if (!MESON_PARM_APPLICABLE(&pll->frac) 159 round = __pll_params_to_rate(*parent_rate, pllt, 0, pll);
146 || rate == pllt->rate) 160
147 return pllt->rate; 161 if (!MESON_PARM_APPLICABLE(&pll->frac) || rate == round)
162 return round;
148 163
149 /* 164 /*
150 * The rate provided by the setting is not an exact match, let's 165 * The rate provided by the setting is not an exact match, let's
@@ -185,12 +200,45 @@ static void meson_clk_pll_init(struct clk_hw *hw)
185 } 200 }
186} 201}
187 202
203static int meson_clk_pll_enable(struct clk_hw *hw)
204{
205 struct clk_regmap *clk = to_clk_regmap(hw);
206 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
207
208 /* Make sure the pll is in reset */
209 meson_parm_write(clk->map, &pll->rst, 1);
210
211 /* Enable the pll */
212 meson_parm_write(clk->map, &pll->en, 1);
213
214 /* Take the pll out reset */
215 meson_parm_write(clk->map, &pll->rst, 0);
216
217 if (meson_clk_pll_wait_lock(hw))
218 return -EIO;
219
220 return 0;
221}
222
223static void meson_clk_pll_disable(struct clk_hw *hw)
224{
225 struct clk_regmap *clk = to_clk_regmap(hw);
226 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
227
228 /* Put the pll is in reset */
229 meson_parm_write(clk->map, &pll->rst, 1);
230
231 /* Disable the pll */
232 meson_parm_write(clk->map, &pll->en, 0);
233}
234
188static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 235static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
189 unsigned long parent_rate) 236 unsigned long parent_rate)
190{ 237{
191 struct clk_regmap *clk = to_clk_regmap(hw); 238 struct clk_regmap *clk = to_clk_regmap(hw);
192 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); 239 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
193 const struct pll_rate_table *pllt; 240 const struct pll_params_table *pllt;
241 unsigned int enabled;
194 unsigned long old_rate; 242 unsigned long old_rate;
195 u16 frac = 0; 243 u16 frac = 0;
196 244
@@ -199,32 +247,28 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
199 247
200 old_rate = rate; 248 old_rate = rate;
201 249
202 pllt = meson_clk_get_pll_settings(rate, pll); 250 pllt = meson_clk_get_pll_settings(rate, parent_rate, pll);
203 if (!pllt) 251 if (!pllt)
204 return -EINVAL; 252 return -EINVAL;
205 253
206 /* Put the pll in reset to write the params */ 254 enabled = meson_parm_read(clk->map, &pll->en);
207 meson_parm_write(clk->map, &pll->rst, 1); 255 if (enabled)
256 meson_clk_pll_disable(hw);
208 257
209 meson_parm_write(clk->map, &pll->n, pllt->n); 258 meson_parm_write(clk->map, &pll->n, pllt->n);
210 meson_parm_write(clk->map, &pll->m, pllt->m); 259 meson_parm_write(clk->map, &pll->m, pllt->m);
211 meson_parm_write(clk->map, &pll->od, pllt->od);
212 260
213 if (MESON_PARM_APPLICABLE(&pll->od2))
214 meson_parm_write(clk->map, &pll->od2, pllt->od2);
215
216 if (MESON_PARM_APPLICABLE(&pll->od3))
217 meson_parm_write(clk->map, &pll->od3, pllt->od3);
218 261
219 if (MESON_PARM_APPLICABLE(&pll->frac)) { 262 if (MESON_PARM_APPLICABLE(&pll->frac)) {
220 frac = __pll_params_with_frac(rate, parent_rate, pllt, pll); 263 frac = __pll_params_with_frac(rate, parent_rate, pllt, pll);
221 meson_parm_write(clk->map, &pll->frac, frac); 264 meson_parm_write(clk->map, &pll->frac, frac);
222 } 265 }
223 266
224 /* make sure the reset is cleared at this point */ 267 /* If the pll is stopped, bail out now */
225 meson_parm_write(clk->map, &pll->rst, 0); 268 if (!enabled)
269 return 0;
226 270
227 if (meson_clk_pll_wait_lock(hw)) { 271 if (meson_clk_pll_enable(hw)) {
228 pr_warn("%s: pll did not lock, trying to restore old rate %lu\n", 272 pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
229 __func__, old_rate); 273 __func__, old_rate);
230 /* 274 /*
@@ -244,6 +288,8 @@ const struct clk_ops meson_clk_pll_ops = {
244 .recalc_rate = meson_clk_pll_recalc_rate, 288 .recalc_rate = meson_clk_pll_recalc_rate,
245 .round_rate = meson_clk_pll_round_rate, 289 .round_rate = meson_clk_pll_round_rate,
246 .set_rate = meson_clk_pll_set_rate, 290 .set_rate = meson_clk_pll_set_rate,
291 .enable = meson_clk_pll_enable,
292 .disable = meson_clk_pll_disable
247}; 293};
248 294
249const struct clk_ops meson_clk_pll_ro_ops = { 295const struct clk_ops meson_clk_pll_ro_ops = {
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 24cec16b6038..6b96d55c047d 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -43,37 +43,29 @@ static inline void meson_parm_write(struct regmap *map, struct parm *p,
43} 43}
44 44
45 45
46struct pll_rate_table { 46struct pll_params_table {
47 unsigned long rate;
48 u16 m; 47 u16 m;
49 u16 n; 48 u16 n;
50 u16 od;
51 u16 od2;
52 u16 od3;
53}; 49};
54 50
55#define PLL_RATE(_r, _m, _n, _od) \ 51#define PLL_PARAMS(_m, _n) \
56 { \ 52 { \
57 .rate = (_r), \
58 .m = (_m), \ 53 .m = (_m), \
59 .n = (_n), \ 54 .n = (_n), \
60 .od = (_od), \
61 } 55 }
62 56
63#define CLK_MESON_PLL_ROUND_CLOSEST BIT(0) 57#define CLK_MESON_PLL_ROUND_CLOSEST BIT(0)
64 58
65struct meson_clk_pll_data { 59struct meson_clk_pll_data {
60 struct parm en;
66 struct parm m; 61 struct parm m;
67 struct parm n; 62 struct parm n;
68 struct parm frac; 63 struct parm frac;
69 struct parm od;
70 struct parm od2;
71 struct parm od3;
72 struct parm l; 64 struct parm l;
73 struct parm rst; 65 struct parm rst;
74 const struct reg_sequence *init_regs; 66 const struct reg_sequence *init_regs;
75 unsigned int init_count; 67 unsigned int init_count;
76 const struct pll_rate_table *table; 68 const struct pll_params_table *table;
77 u8 flags; 69 u8 flags;
78}; 70};
79 71
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 86d3ae58e84c..9309cfaaa464 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -18,165 +18,77 @@
18 18
19static DEFINE_SPINLOCK(meson_clk_lock); 19static DEFINE_SPINLOCK(meson_clk_lock);
20 20
21static const struct pll_rate_table gxbb_gp0_pll_rate_table[] = { 21static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
22 PLL_RATE(96000000, 32, 1, 3), 22 PLL_PARAMS(32, 1),
23 PLL_RATE(99000000, 33, 1, 3), 23 PLL_PARAMS(33, 1),
24 PLL_RATE(102000000, 34, 1, 3), 24 PLL_PARAMS(34, 1),
25 PLL_RATE(105000000, 35, 1, 3), 25 PLL_PARAMS(35, 1),
26 PLL_RATE(108000000, 36, 1, 3), 26 PLL_PARAMS(36, 1),
27 PLL_RATE(111000000, 37, 1, 3), 27 PLL_PARAMS(37, 1),
28 PLL_RATE(114000000, 38, 1, 3), 28 PLL_PARAMS(38, 1),
29 PLL_RATE(117000000, 39, 1, 3), 29 PLL_PARAMS(39, 1),
30 PLL_RATE(120000000, 40, 1, 3), 30 PLL_PARAMS(40, 1),
31 PLL_RATE(123000000, 41, 1, 3), 31 PLL_PARAMS(41, 1),
32 PLL_RATE(126000000, 42, 1, 3), 32 PLL_PARAMS(42, 1),
33 PLL_RATE(129000000, 43, 1, 3), 33 PLL_PARAMS(43, 1),
34 PLL_RATE(132000000, 44, 1, 3), 34 PLL_PARAMS(44, 1),
35 PLL_RATE(135000000, 45, 1, 3), 35 PLL_PARAMS(45, 1),
36 PLL_RATE(138000000, 46, 1, 3), 36 PLL_PARAMS(46, 1),
37 PLL_RATE(141000000, 47, 1, 3), 37 PLL_PARAMS(47, 1),
38 PLL_RATE(144000000, 48, 1, 3), 38 PLL_PARAMS(48, 1),
39 PLL_RATE(147000000, 49, 1, 3), 39 PLL_PARAMS(49, 1),
40 PLL_RATE(150000000, 50, 1, 3), 40 PLL_PARAMS(50, 1),
41 PLL_RATE(153000000, 51, 1, 3), 41 PLL_PARAMS(51, 1),
42 PLL_RATE(156000000, 52, 1, 3), 42 PLL_PARAMS(52, 1),
43 PLL_RATE(159000000, 53, 1, 3), 43 PLL_PARAMS(53, 1),
44 PLL_RATE(162000000, 54, 1, 3), 44 PLL_PARAMS(54, 1),
45 PLL_RATE(165000000, 55, 1, 3), 45 PLL_PARAMS(55, 1),
46 PLL_RATE(168000000, 56, 1, 3), 46 PLL_PARAMS(56, 1),
47 PLL_RATE(171000000, 57, 1, 3), 47 PLL_PARAMS(57, 1),
48 PLL_RATE(174000000, 58, 1, 3), 48 PLL_PARAMS(58, 1),
49 PLL_RATE(177000000, 59, 1, 3), 49 PLL_PARAMS(59, 1),
50 PLL_RATE(180000000, 60, 1, 3), 50 PLL_PARAMS(60, 1),
51 PLL_RATE(183000000, 61, 1, 3), 51 PLL_PARAMS(61, 1),
52 PLL_RATE(186000000, 62, 1, 3), 52 PLL_PARAMS(62, 1),
53 PLL_RATE(192000000, 32, 1, 2),
54 PLL_RATE(198000000, 33, 1, 2),
55 PLL_RATE(204000000, 34, 1, 2),
56 PLL_RATE(210000000, 35, 1, 2),
57 PLL_RATE(216000000, 36, 1, 2),
58 PLL_RATE(222000000, 37, 1, 2),
59 PLL_RATE(228000000, 38, 1, 2),
60 PLL_RATE(234000000, 39, 1, 2),
61 PLL_RATE(240000000, 40, 1, 2),
62 PLL_RATE(246000000, 41, 1, 2),
63 PLL_RATE(252000000, 42, 1, 2),
64 PLL_RATE(258000000, 43, 1, 2),
65 PLL_RATE(264000000, 44, 1, 2),
66 PLL_RATE(270000000, 45, 1, 2),
67 PLL_RATE(276000000, 46, 1, 2),
68 PLL_RATE(282000000, 47, 1, 2),
69 PLL_RATE(288000000, 48, 1, 2),
70 PLL_RATE(294000000, 49, 1, 2),
71 PLL_RATE(300000000, 50, 1, 2),
72 PLL_RATE(306000000, 51, 1, 2),
73 PLL_RATE(312000000, 52, 1, 2),
74 PLL_RATE(318000000, 53, 1, 2),
75 PLL_RATE(324000000, 54, 1, 2),
76 PLL_RATE(330000000, 55, 1, 2),
77 PLL_RATE(336000000, 56, 1, 2),
78 PLL_RATE(342000000, 57, 1, 2),
79 PLL_RATE(348000000, 58, 1, 2),
80 PLL_RATE(354000000, 59, 1, 2),
81 PLL_RATE(360000000, 60, 1, 2),
82 PLL_RATE(366000000, 61, 1, 2),
83 PLL_RATE(372000000, 62, 1, 2),
84 PLL_RATE(384000000, 32, 1, 1),
85 PLL_RATE(396000000, 33, 1, 1),
86 PLL_RATE(408000000, 34, 1, 1),
87 PLL_RATE(420000000, 35, 1, 1),
88 PLL_RATE(432000000, 36, 1, 1),
89 PLL_RATE(444000000, 37, 1, 1),
90 PLL_RATE(456000000, 38, 1, 1),
91 PLL_RATE(468000000, 39, 1, 1),
92 PLL_RATE(480000000, 40, 1, 1),
93 PLL_RATE(492000000, 41, 1, 1),
94 PLL_RATE(504000000, 42, 1, 1),
95 PLL_RATE(516000000, 43, 1, 1),
96 PLL_RATE(528000000, 44, 1, 1),
97 PLL_RATE(540000000, 45, 1, 1),
98 PLL_RATE(552000000, 46, 1, 1),
99 PLL_RATE(564000000, 47, 1, 1),
100 PLL_RATE(576000000, 48, 1, 1),
101 PLL_RATE(588000000, 49, 1, 1),
102 PLL_RATE(600000000, 50, 1, 1),
103 PLL_RATE(612000000, 51, 1, 1),
104 PLL_RATE(624000000, 52, 1, 1),
105 PLL_RATE(636000000, 53, 1, 1),
106 PLL_RATE(648000000, 54, 1, 1),
107 PLL_RATE(660000000, 55, 1, 1),
108 PLL_RATE(672000000, 56, 1, 1),
109 PLL_RATE(684000000, 57, 1, 1),
110 PLL_RATE(696000000, 58, 1, 1),
111 PLL_RATE(708000000, 59, 1, 1),
112 PLL_RATE(720000000, 60, 1, 1),
113 PLL_RATE(732000000, 61, 1, 1),
114 PLL_RATE(744000000, 62, 1, 1),
115 PLL_RATE(768000000, 32, 1, 0),
116 PLL_RATE(792000000, 33, 1, 0),
117 PLL_RATE(816000000, 34, 1, 0),
118 PLL_RATE(840000000, 35, 1, 0),
119 PLL_RATE(864000000, 36, 1, 0),
120 PLL_RATE(888000000, 37, 1, 0),
121 PLL_RATE(912000000, 38, 1, 0),
122 PLL_RATE(936000000, 39, 1, 0),
123 PLL_RATE(960000000, 40, 1, 0),
124 PLL_RATE(984000000, 41, 1, 0),
125 PLL_RATE(1008000000, 42, 1, 0),
126 PLL_RATE(1032000000, 43, 1, 0),
127 PLL_RATE(1056000000, 44, 1, 0),
128 PLL_RATE(1080000000, 45, 1, 0),
129 PLL_RATE(1104000000, 46, 1, 0),
130 PLL_RATE(1128000000, 47, 1, 0),
131 PLL_RATE(1152000000, 48, 1, 0),
132 PLL_RATE(1176000000, 49, 1, 0),
133 PLL_RATE(1200000000, 50, 1, 0),
134 PLL_RATE(1224000000, 51, 1, 0),
135 PLL_RATE(1248000000, 52, 1, 0),
136 PLL_RATE(1272000000, 53, 1, 0),
137 PLL_RATE(1296000000, 54, 1, 0),
138 PLL_RATE(1320000000, 55, 1, 0),
139 PLL_RATE(1344000000, 56, 1, 0),
140 PLL_RATE(1368000000, 57, 1, 0),
141 PLL_RATE(1392000000, 58, 1, 0),
142 PLL_RATE(1416000000, 59, 1, 0),
143 PLL_RATE(1440000000, 60, 1, 0),
144 PLL_RATE(1464000000, 61, 1, 0),
145 PLL_RATE(1488000000, 62, 1, 0),
146 { /* sentinel */ }, 53 { /* sentinel */ },
147}; 54};
148 55
149static const struct pll_rate_table gxl_gp0_pll_rate_table[] = { 56static const struct pll_params_table gxl_gp0_pll_params_table[] = {
150 PLL_RATE(504000000, 42, 1, 1), 57 PLL_PARAMS(42, 1),
151 PLL_RATE(516000000, 43, 1, 1), 58 PLL_PARAMS(43, 1),
152 PLL_RATE(528000000, 44, 1, 1), 59 PLL_PARAMS(44, 1),
153 PLL_RATE(540000000, 45, 1, 1), 60 PLL_PARAMS(45, 1),
154 PLL_RATE(552000000, 46, 1, 1), 61 PLL_PARAMS(46, 1),
155 PLL_RATE(564000000, 47, 1, 1), 62 PLL_PARAMS(47, 1),
156 PLL_RATE(576000000, 48, 1, 1), 63 PLL_PARAMS(48, 1),
157 PLL_RATE(588000000, 49, 1, 1), 64 PLL_PARAMS(49, 1),
158 PLL_RATE(600000000, 50, 1, 1), 65 PLL_PARAMS(50, 1),
159 PLL_RATE(612000000, 51, 1, 1), 66 PLL_PARAMS(51, 1),
160 PLL_RATE(624000000, 52, 1, 1), 67 PLL_PARAMS(52, 1),
161 PLL_RATE(636000000, 53, 1, 1), 68 PLL_PARAMS(53, 1),
162 PLL_RATE(648000000, 54, 1, 1), 69 PLL_PARAMS(54, 1),
163 PLL_RATE(660000000, 55, 1, 1), 70 PLL_PARAMS(55, 1),
164 PLL_RATE(672000000, 56, 1, 1), 71 PLL_PARAMS(56, 1),
165 PLL_RATE(684000000, 57, 1, 1), 72 PLL_PARAMS(57, 1),
166 PLL_RATE(696000000, 58, 1, 1), 73 PLL_PARAMS(58, 1),
167 PLL_RATE(708000000, 59, 1, 1), 74 PLL_PARAMS(59, 1),
168 PLL_RATE(720000000, 60, 1, 1), 75 PLL_PARAMS(60, 1),
169 PLL_RATE(732000000, 61, 1, 1), 76 PLL_PARAMS(61, 1),
170 PLL_RATE(744000000, 62, 1, 1), 77 PLL_PARAMS(62, 1),
171 PLL_RATE(756000000, 63, 1, 1), 78 PLL_PARAMS(63, 1),
172 PLL_RATE(768000000, 64, 1, 1), 79 PLL_PARAMS(64, 1),
173 PLL_RATE(780000000, 65, 1, 1), 80 PLL_PARAMS(65, 1),
174 PLL_RATE(792000000, 66, 1, 1), 81 PLL_PARAMS(66, 1),
175 { /* sentinel */ }, 82 { /* sentinel */ },
176}; 83};
177 84
178static struct clk_regmap gxbb_fixed_pll = { 85static struct clk_regmap gxbb_fixed_pll_dco = {
179 .data = &(struct meson_clk_pll_data){ 86 .data = &(struct meson_clk_pll_data){
87 .en = {
88 .reg_off = HHI_MPLL_CNTL,
89 .shift = 30,
90 .width = 1,
91 },
180 .m = { 92 .m = {
181 .reg_off = HHI_MPLL_CNTL, 93 .reg_off = HHI_MPLL_CNTL,
182 .shift = 0, 94 .shift = 0,
@@ -187,11 +99,6 @@ static struct clk_regmap gxbb_fixed_pll = {
187 .shift = 9, 99 .shift = 9,
188 .width = 5, 100 .width = 5,
189 }, 101 },
190 .od = {
191 .reg_off = HHI_MPLL_CNTL,
192 .shift = 16,
193 .width = 2,
194 },
195 .frac = { 102 .frac = {
196 .reg_off = HHI_MPLL_CNTL2, 103 .reg_off = HHI_MPLL_CNTL2,
197 .shift = 0, 104 .shift = 0,
@@ -209,11 +116,29 @@ static struct clk_regmap gxbb_fixed_pll = {
209 }, 116 },
210 }, 117 },
211 .hw.init = &(struct clk_init_data){ 118 .hw.init = &(struct clk_init_data){
212 .name = "fixed_pll", 119 .name = "fixed_pll_dco",
213 .ops = &meson_clk_pll_ro_ops, 120 .ops = &meson_clk_pll_ro_ops,
214 .parent_names = (const char *[]){ "xtal" }, 121 .parent_names = (const char *[]){ "xtal" },
215 .num_parents = 1, 122 .num_parents = 1,
216 .flags = CLK_GET_RATE_NOCACHE, 123 },
124};
125
126static struct clk_regmap gxbb_fixed_pll = {
127 .data = &(struct clk_regmap_div_data){
128 .offset = HHI_MPLL_CNTL,
129 .shift = 16,
130 .width = 2,
131 .flags = CLK_DIVIDER_POWER_OF_TWO,
132 },
133 .hw.init = &(struct clk_init_data){
134 .name = "fixed_pll",
135 .ops = &clk_regmap_divider_ro_ops,
136 .parent_names = (const char *[]){ "fixed_pll_dco" },
137 .num_parents = 1,
138 /*
139 * This clock won't ever change at runtime so
140 * CLK_SET_RATE_PARENT is not required
141 */
217 }, 142 },
218}; 143};
219 144
@@ -228,8 +153,13 @@ static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
228 }, 153 },
229}; 154};
230 155
231static struct clk_regmap gxbb_hdmi_pll = { 156static struct clk_regmap gxbb_hdmi_pll_dco = {
232 .data = &(struct meson_clk_pll_data){ 157 .data = &(struct meson_clk_pll_data){
158 .en = {
159 .reg_off = HHI_HDMI_PLL_CNTL,
160 .shift = 30,
161 .width = 1,
162 },
233 .m = { 163 .m = {
234 .reg_off = HHI_HDMI_PLL_CNTL, 164 .reg_off = HHI_HDMI_PLL_CNTL,
235 .shift = 0, 165 .shift = 0,
@@ -245,21 +175,6 @@ static struct clk_regmap gxbb_hdmi_pll = {
245 .shift = 0, 175 .shift = 0,
246 .width = 12, 176 .width = 12,
247 }, 177 },
248 .od = {
249 .reg_off = HHI_HDMI_PLL_CNTL2,
250 .shift = 16,
251 .width = 2,
252 },
253 .od2 = {
254 .reg_off = HHI_HDMI_PLL_CNTL2,
255 .shift = 22,
256 .width = 2,
257 },
258 .od3 = {
259 .reg_off = HHI_HDMI_PLL_CNTL2,
260 .shift = 18,
261 .width = 2,
262 },
263 .l = { 178 .l = {
264 .reg_off = HHI_HDMI_PLL_CNTL, 179 .reg_off = HHI_HDMI_PLL_CNTL,
265 .shift = 31, 180 .shift = 31,
@@ -272,74 +187,121 @@ static struct clk_regmap gxbb_hdmi_pll = {
272 }, 187 },
273 }, 188 },
274 .hw.init = &(struct clk_init_data){ 189 .hw.init = &(struct clk_init_data){
275 .name = "hdmi_pll", 190 .name = "hdmi_pll_dco",
276 .ops = &meson_clk_pll_ro_ops, 191 .ops = &meson_clk_pll_ro_ops,
277 .parent_names = (const char *[]){ "hdmi_pll_pre_mult" }, 192 .parent_names = (const char *[]){ "hdmi_pll_pre_mult" },
278 .num_parents = 1, 193 .num_parents = 1,
194 /*
195 * Display directly handle hdmi pll registers ATM, we need
196 * NOCACHE to keep our view of the clock as accurate as possible
197 */
279 .flags = CLK_GET_RATE_NOCACHE, 198 .flags = CLK_GET_RATE_NOCACHE,
280 }, 199 },
281}; 200};
282 201
202static struct clk_regmap gxbb_hdmi_pll_od = {
203 .data = &(struct clk_regmap_div_data){
204 .offset = HHI_HDMI_PLL_CNTL2,
205 .shift = 16,
206 .width = 2,
207 .flags = CLK_DIVIDER_POWER_OF_TWO,
208 },
209 .hw.init = &(struct clk_init_data){
210 .name = "hdmi_pll_od",
211 .ops = &clk_regmap_divider_ro_ops,
212 .parent_names = (const char *[]){ "hdmi_pll_dco" },
213 .num_parents = 1,
214 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
215 },
216};
217
218static struct clk_regmap gxbb_hdmi_pll_od2 = {
219 .data = &(struct clk_regmap_div_data){
220 .offset = HHI_HDMI_PLL_CNTL2,
221 .shift = 22,
222 .width = 2,
223 .flags = CLK_DIVIDER_POWER_OF_TWO,
224 },
225 .hw.init = &(struct clk_init_data){
226 .name = "hdmi_pll_od2",
227 .ops = &clk_regmap_divider_ro_ops,
228 .parent_names = (const char *[]){ "hdmi_pll_od" },
229 .num_parents = 1,
230 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
231 },
232};
233
234static struct clk_regmap gxbb_hdmi_pll = {
235 .data = &(struct clk_regmap_div_data){
236 .offset = HHI_HDMI_PLL_CNTL2,
237 .shift = 18,
238 .width = 2,
239 .flags = CLK_DIVIDER_POWER_OF_TWO,
240 },
241 .hw.init = &(struct clk_init_data){
242 .name = "hdmi_pll",
243 .ops = &clk_regmap_divider_ro_ops,
244 .parent_names = (const char *[]){ "hdmi_pll_od2" },
245 .num_parents = 1,
246 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
247 },
248};
249
250static struct clk_regmap gxl_hdmi_pll_od = {
251 .data = &(struct clk_regmap_div_data){
252 .offset = HHI_HDMI_PLL_CNTL + 8,
253 .shift = 21,
254 .width = 2,
255 .flags = CLK_DIVIDER_POWER_OF_TWO,
256 },
257 .hw.init = &(struct clk_init_data){
258 .name = "hdmi_pll_od",
259 .ops = &clk_regmap_divider_ro_ops,
260 .parent_names = (const char *[]){ "hdmi_pll_dco" },
261 .num_parents = 1,
262 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
263 },
264};
265
266static struct clk_regmap gxl_hdmi_pll_od2 = {
267 .data = &(struct clk_regmap_div_data){
268 .offset = HHI_HDMI_PLL_CNTL + 8,
269 .shift = 23,
270 .width = 2,
271 .flags = CLK_DIVIDER_POWER_OF_TWO,
272 },
273 .hw.init = &(struct clk_init_data){
274 .name = "hdmi_pll_od2",
275 .ops = &clk_regmap_divider_ro_ops,
276 .parent_names = (const char *[]){ "hdmi_pll_od" },
277 .num_parents = 1,
278 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
279 },
280};
281
283static struct clk_regmap gxl_hdmi_pll = { 282static struct clk_regmap gxl_hdmi_pll = {
284 .data = &(struct meson_clk_pll_data){ 283 .data = &(struct clk_regmap_div_data){
285 .m = { 284 .offset = HHI_HDMI_PLL_CNTL + 8,
286 .reg_off = HHI_HDMI_PLL_CNTL, 285 .shift = 19,
287 .shift = 0, 286 .width = 2,
288 .width = 9, 287 .flags = CLK_DIVIDER_POWER_OF_TWO,
289 },
290 .n = {
291 .reg_off = HHI_HDMI_PLL_CNTL,
292 .shift = 9,
293 .width = 5,
294 },
295 .frac = {
296 /*
297 * On gxl, there is a register shift due to
298 * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
299 * so we compute the register offset based on the PLL
300 * base to get it right
301 */
302 .reg_off = HHI_HDMI_PLL_CNTL + 4,
303 .shift = 0,
304 .width = 12,
305 },
306 .od = {
307 .reg_off = HHI_HDMI_PLL_CNTL + 8,
308 .shift = 21,
309 .width = 2,
310 },
311 .od2 = {
312 .reg_off = HHI_HDMI_PLL_CNTL + 8,
313 .shift = 23,
314 .width = 2,
315 },
316 .od3 = {
317 .reg_off = HHI_HDMI_PLL_CNTL + 8,
318 .shift = 19,
319 .width = 2,
320 },
321 .l = {
322 .reg_off = HHI_HDMI_PLL_CNTL,
323 .shift = 31,
324 .width = 1,
325 },
326 .rst = {
327 .reg_off = HHI_HDMI_PLL_CNTL,
328 .shift = 29,
329 .width = 1,
330 },
331 }, 288 },
332 .hw.init = &(struct clk_init_data){ 289 .hw.init = &(struct clk_init_data){
333 .name = "hdmi_pll", 290 .name = "hdmi_pll",
334 .ops = &meson_clk_pll_ro_ops, 291 .ops = &clk_regmap_divider_ro_ops,
335 .parent_names = (const char *[]){ "xtal" }, 292 .parent_names = (const char *[]){ "hdmi_pll_od2" },
336 .num_parents = 1, 293 .num_parents = 1,
337 .flags = CLK_GET_RATE_NOCACHE, 294 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
338 }, 295 },
339}; 296};
340 297
341static struct clk_regmap gxbb_sys_pll = { 298static struct clk_regmap gxbb_sys_pll_dco = {
342 .data = &(struct meson_clk_pll_data){ 299 .data = &(struct meson_clk_pll_data){
300 .en = {
301 .reg_off = HHI_SYS_PLL_CNTL,
302 .shift = 30,
303 .width = 1,
304 },
343 .m = { 305 .m = {
344 .reg_off = HHI_SYS_PLL_CNTL, 306 .reg_off = HHI_SYS_PLL_CNTL,
345 .shift = 0, 307 .shift = 0,
@@ -350,11 +312,6 @@ static struct clk_regmap gxbb_sys_pll = {
350 .shift = 9, 312 .shift = 9,
351 .width = 5, 313 .width = 5,
352 }, 314 },
353 .od = {
354 .reg_off = HHI_SYS_PLL_CNTL,
355 .shift = 10,
356 .width = 2,
357 },
358 .l = { 315 .l = {
359 .reg_off = HHI_SYS_PLL_CNTL, 316 .reg_off = HHI_SYS_PLL_CNTL,
360 .shift = 31, 317 .shift = 31,
@@ -367,11 +324,26 @@ static struct clk_regmap gxbb_sys_pll = {
367 }, 324 },
368 }, 325 },
369 .hw.init = &(struct clk_init_data){ 326 .hw.init = &(struct clk_init_data){
370 .name = "sys_pll", 327 .name = "sys_pll_dco",
371 .ops = &meson_clk_pll_ro_ops, 328 .ops = &meson_clk_pll_ro_ops,
372 .parent_names = (const char *[]){ "xtal" }, 329 .parent_names = (const char *[]){ "xtal" },
373 .num_parents = 1, 330 .num_parents = 1,
374 .flags = CLK_GET_RATE_NOCACHE, 331 },
332};
333
334static struct clk_regmap gxbb_sys_pll = {
335 .data = &(struct clk_regmap_div_data){
336 .offset = HHI_SYS_PLL_CNTL,
337 .shift = 10,
338 .width = 2,
339 .flags = CLK_DIVIDER_POWER_OF_TWO,
340 },
341 .hw.init = &(struct clk_init_data){
342 .name = "sys_pll",
343 .ops = &clk_regmap_divider_ro_ops,
344 .parent_names = (const char *[]){ "sys_pll_dco" },
345 .num_parents = 1,
346 .flags = CLK_SET_RATE_PARENT,
375 }, 347 },
376}; 348};
377 349
@@ -379,11 +351,15 @@ static const struct reg_sequence gxbb_gp0_init_regs[] = {
379 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 }, 351 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 },
380 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 }, 352 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 },
381 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d }, 353 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d },
382 { .reg = HHI_GP0_PLL_CNTL, .def = 0x4a000228 },
383}; 354};
384 355
385static struct clk_regmap gxbb_gp0_pll = { 356static struct clk_regmap gxbb_gp0_pll_dco = {
386 .data = &(struct meson_clk_pll_data){ 357 .data = &(struct meson_clk_pll_data){
358 .en = {
359 .reg_off = HHI_GP0_PLL_CNTL,
360 .shift = 30,
361 .width = 1,
362 },
387 .m = { 363 .m = {
388 .reg_off = HHI_GP0_PLL_CNTL, 364 .reg_off = HHI_GP0_PLL_CNTL,
389 .shift = 0, 365 .shift = 0,
@@ -394,11 +370,6 @@ static struct clk_regmap gxbb_gp0_pll = {
394 .shift = 9, 370 .shift = 9,
395 .width = 5, 371 .width = 5,
396 }, 372 },
397 .od = {
398 .reg_off = HHI_GP0_PLL_CNTL,
399 .shift = 16,
400 .width = 2,
401 },
402 .l = { 373 .l = {
403 .reg_off = HHI_GP0_PLL_CNTL, 374 .reg_off = HHI_GP0_PLL_CNTL,
404 .shift = 31, 375 .shift = 31,
@@ -409,16 +380,15 @@ static struct clk_regmap gxbb_gp0_pll = {
409 .shift = 29, 380 .shift = 29,
410 .width = 1, 381 .width = 1,
411 }, 382 },
412 .table = gxbb_gp0_pll_rate_table, 383 .table = gxbb_gp0_pll_params_table,
413 .init_regs = gxbb_gp0_init_regs, 384 .init_regs = gxbb_gp0_init_regs,
414 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs), 385 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
415 }, 386 },
416 .hw.init = &(struct clk_init_data){ 387 .hw.init = &(struct clk_init_data){
417 .name = "gp0_pll", 388 .name = "gp0_pll_dco",
418 .ops = &meson_clk_pll_ops, 389 .ops = &meson_clk_pll_ops,
419 .parent_names = (const char *[]){ "xtal" }, 390 .parent_names = (const char *[]){ "xtal" },
420 .num_parents = 1, 391 .num_parents = 1,
421 .flags = CLK_GET_RATE_NOCACHE,
422 }, 392 },
423}; 393};
424 394
@@ -428,11 +398,15 @@ static const struct reg_sequence gxl_gp0_init_regs[] = {
428 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, 398 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
429 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, 399 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
430 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, 400 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
431 { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 },
432}; 401};
433 402
434static struct clk_regmap gxl_gp0_pll = { 403static struct clk_regmap gxl_gp0_pll_dco = {
435 .data = &(struct meson_clk_pll_data){ 404 .data = &(struct meson_clk_pll_data){
405 .en = {
406 .reg_off = HHI_GP0_PLL_CNTL,
407 .shift = 30,
408 .width = 1,
409 },
436 .m = { 410 .m = {
437 .reg_off = HHI_GP0_PLL_CNTL, 411 .reg_off = HHI_GP0_PLL_CNTL,
438 .shift = 0, 412 .shift = 0,
@@ -443,11 +417,6 @@ static struct clk_regmap gxl_gp0_pll = {
443 .shift = 9, 417 .shift = 9,
444 .width = 5, 418 .width = 5,
445 }, 419 },
446 .od = {
447 .reg_off = HHI_GP0_PLL_CNTL,
448 .shift = 16,
449 .width = 2,
450 },
451 .frac = { 420 .frac = {
452 .reg_off = HHI_GP0_PLL_CNTL1, 421 .reg_off = HHI_GP0_PLL_CNTL1,
453 .shift = 0, 422 .shift = 0,
@@ -463,16 +432,31 @@ static struct clk_regmap gxl_gp0_pll = {
463 .shift = 29, 432 .shift = 29,
464 .width = 1, 433 .width = 1,
465 }, 434 },
466 .table = gxl_gp0_pll_rate_table, 435 .table = gxl_gp0_pll_params_table,
467 .init_regs = gxl_gp0_init_regs, 436 .init_regs = gxl_gp0_init_regs,
468 .init_count = ARRAY_SIZE(gxl_gp0_init_regs), 437 .init_count = ARRAY_SIZE(gxl_gp0_init_regs),
469 }, 438 },
470 .hw.init = &(struct clk_init_data){ 439 .hw.init = &(struct clk_init_data){
471 .name = "gp0_pll", 440 .name = "gp0_pll_dco",
472 .ops = &meson_clk_pll_ops, 441 .ops = &meson_clk_pll_ops,
473 .parent_names = (const char *[]){ "xtal" }, 442 .parent_names = (const char *[]){ "xtal" },
474 .num_parents = 1, 443 .num_parents = 1,
475 .flags = CLK_GET_RATE_NOCACHE, 444 },
445};
446
447static struct clk_regmap gxbb_gp0_pll = {
448 .data = &(struct clk_regmap_div_data){
449 .offset = HHI_GP0_PLL_CNTL,
450 .shift = 16,
451 .width = 2,
452 .flags = CLK_DIVIDER_POWER_OF_TWO,
453 },
454 .hw.init = &(struct clk_init_data){
455 .name = "gp0_pll",
456 .ops = &clk_regmap_divider_ops,
457 .parent_names = (const char *[]){ "gp0_pll_dco" },
458 .num_parents = 1,
459 .flags = CLK_SET_RATE_PARENT,
476 }, 460 },
477}; 461};
478 462
@@ -1933,6 +1917,12 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
1933 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 1917 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
1934 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 1918 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
1935 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 1919 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
1920 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
1921 [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw,
1922 [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw,
1923 [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw,
1924 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
1925 [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw,
1936 [NR_CLKS] = NULL, 1926 [NR_CLKS] = NULL,
1937 }, 1927 },
1938 .num = NR_CLKS, 1928 .num = NR_CLKS,
@@ -1948,7 +1938,7 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
1948 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 1938 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
1949 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 1939 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
1950 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 1940 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
1951 [CLKID_GP0_PLL] = &gxl_gp0_pll.hw, 1941 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
1952 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 1942 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
1953 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 1943 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
1954 [CLKID_CLK81] = &gxbb_clk81.hw, 1944 [CLKID_CLK81] = &gxbb_clk81.hw,
@@ -2098,19 +2088,29 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
2098 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 2088 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
2099 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 2089 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
2100 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 2090 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
2091 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
2092 [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw,
2093 [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw,
2094 [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw,
2095 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
2096 [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw,
2101 [NR_CLKS] = NULL, 2097 [NR_CLKS] = NULL,
2102 }, 2098 },
2103 .num = NR_CLKS, 2099 .num = NR_CLKS,
2104}; 2100};
2105 2101
2106static struct clk_regmap *const gxbb_clk_regmaps[] = { 2102static struct clk_regmap *const gxbb_clk_regmaps[] = {
2107 &gxbb_gp0_pll, 2103 &gxbb_gp0_pll_dco,
2108 &gxbb_hdmi_pll, 2104 &gxbb_hdmi_pll,
2105 &gxbb_hdmi_pll_od,
2106 &gxbb_hdmi_pll_od2,
2109}; 2107};
2110 2108
2111static struct clk_regmap *const gxl_clk_regmaps[] = { 2109static struct clk_regmap *const gxl_clk_regmaps[] = {
2112 &gxl_gp0_pll, 2110 &gxl_gp0_pll_dco,
2113 &gxl_hdmi_pll, 2111 &gxl_hdmi_pll,
2112 &gxl_hdmi_pll_od,
2113 &gxl_hdmi_pll_od2,
2114}; 2114};
2115 2115
2116static struct clk_regmap *const gx_clk_regmaps[] = { 2116static struct clk_regmap *const gx_clk_regmaps[] = {
@@ -2265,6 +2265,10 @@ static struct clk_regmap *const gx_clk_regmaps[] = {
2265 &gxbb_gen_clk_sel, 2265 &gxbb_gen_clk_sel,
2266 &gxbb_gen_clk_div, 2266 &gxbb_gen_clk_div,
2267 &gxbb_gen_clk, 2267 &gxbb_gen_clk,
2268 &gxbb_fixed_pll_dco,
2269 &gxbb_hdmi_pll_dco,
2270 &gxbb_sys_pll_dco,
2271 &gxbb_gp0_pll,
2268}; 2272};
2269 2273
2270struct clkc_data { 2274struct clkc_data {
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 20dfb1daf5b8..72bc077d9663 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -159,8 +159,14 @@
159#define CLKID_VDEC_HEVC_DIV 155 159#define CLKID_VDEC_HEVC_DIV 155
160#define CLKID_GEN_CLK_SEL 157 160#define CLKID_GEN_CLK_SEL 157
161#define CLKID_GEN_CLK_DIV 158 161#define CLKID_GEN_CLK_DIV 158
162 162#define CLKID_FIXED_PLL_DCO 160
163#define NR_CLKS 160 163#define CLKID_HDMI_PLL_DCO 161
164#define CLKID_HDMI_PLL_OD 162
165#define CLKID_HDMI_PLL_OD2 163
166#define CLKID_SYS_PLL_DCO 164
167#define CLKID_GP0_PLL_DCO 165
168
169#define NR_CLKS 166
164 170
165/* include the CLKIDs that have been made part of the DT binding */ 171/* include the CLKIDs that have been made part of the DT binding */
166#include <dt-bindings/clock/gxbb-clkc.h> 172#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 7447d96a265f..346b9e165b7a 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -11,7 +11,6 @@
11#include <linux/clk-provider.h> 11#include <linux/clk-provider.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/of_address.h> 13#include <linux/of_address.h>
14#include <linux/platform_device.h>
15#include <linux/reset-controller.h> 14#include <linux/reset-controller.h>
16#include <linux/slab.h> 15#include <linux/slab.h>
17#include <linux/regmap.h> 16#include <linux/regmap.h>
@@ -22,66 +21,27 @@
22 21
23static DEFINE_SPINLOCK(meson_clk_lock); 22static DEFINE_SPINLOCK(meson_clk_lock);
24 23
25static void __iomem *clk_base;
26
27struct meson8b_clk_reset { 24struct meson8b_clk_reset {
28 struct reset_controller_dev reset; 25 struct reset_controller_dev reset;
29 void __iomem *base; 26 struct regmap *regmap;
30}; 27};
31 28
32static const struct pll_rate_table sys_pll_rate_table[] = { 29static const struct pll_params_table sys_pll_params_table[] = {
33 PLL_RATE(312000000, 52, 1, 2), 30 PLL_PARAMS(50, 1),
34 PLL_RATE(336000000, 56, 1, 2), 31 PLL_PARAMS(51, 1),
35 PLL_RATE(360000000, 60, 1, 2), 32 PLL_PARAMS(52, 1),
36 PLL_RATE(384000000, 64, 1, 2), 33 PLL_PARAMS(53, 1),
37 PLL_RATE(408000000, 68, 1, 2), 34 PLL_PARAMS(54, 1),
38 PLL_RATE(432000000, 72, 1, 2), 35 PLL_PARAMS(55, 1),
39 PLL_RATE(456000000, 76, 1, 2), 36 PLL_PARAMS(56, 1),
40 PLL_RATE(480000000, 80, 1, 2), 37 PLL_PARAMS(57, 1),
41 PLL_RATE(504000000, 84, 1, 2), 38 PLL_PARAMS(58, 1),
42 PLL_RATE(528000000, 88, 1, 2), 39 PLL_PARAMS(59, 1),
43 PLL_RATE(552000000, 92, 1, 2), 40 PLL_PARAMS(60, 1),
44 PLL_RATE(576000000, 96, 1, 2), 41 PLL_PARAMS(61, 1),
45 PLL_RATE(600000000, 50, 1, 1), 42 PLL_PARAMS(62, 1),
46 PLL_RATE(624000000, 52, 1, 1), 43 PLL_PARAMS(63, 1),
47 PLL_RATE(648000000, 54, 1, 1), 44 PLL_PARAMS(64, 1),
48 PLL_RATE(672000000, 56, 1, 1),
49 PLL_RATE(696000000, 58, 1, 1),
50 PLL_RATE(720000000, 60, 1, 1),
51 PLL_RATE(744000000, 62, 1, 1),
52 PLL_RATE(768000000, 64, 1, 1),
53 PLL_RATE(792000000, 66, 1, 1),
54 PLL_RATE(816000000, 68, 1, 1),
55 PLL_RATE(840000000, 70, 1, 1),
56 PLL_RATE(864000000, 72, 1, 1),
57 PLL_RATE(888000000, 74, 1, 1),
58 PLL_RATE(912000000, 76, 1, 1),
59 PLL_RATE(936000000, 78, 1, 1),
60 PLL_RATE(960000000, 80, 1, 1),
61 PLL_RATE(984000000, 82, 1, 1),
62 PLL_RATE(1008000000, 84, 1, 1),
63 PLL_RATE(1032000000, 86, 1, 1),
64 PLL_RATE(1056000000, 88, 1, 1),
65 PLL_RATE(1080000000, 90, 1, 1),
66 PLL_RATE(1104000000, 92, 1, 1),
67 PLL_RATE(1128000000, 94, 1, 1),
68 PLL_RATE(1152000000, 96, 1, 1),
69 PLL_RATE(1176000000, 98, 1, 1),
70 PLL_RATE(1200000000, 50, 1, 0),
71 PLL_RATE(1224000000, 51, 1, 0),
72 PLL_RATE(1248000000, 52, 1, 0),
73 PLL_RATE(1272000000, 53, 1, 0),
74 PLL_RATE(1296000000, 54, 1, 0),
75 PLL_RATE(1320000000, 55, 1, 0),
76 PLL_RATE(1344000000, 56, 1, 0),
77 PLL_RATE(1368000000, 57, 1, 0),
78 PLL_RATE(1392000000, 58, 1, 0),
79 PLL_RATE(1416000000, 59, 1, 0),
80 PLL_RATE(1440000000, 60, 1, 0),
81 PLL_RATE(1464000000, 61, 1, 0),
82 PLL_RATE(1488000000, 62, 1, 0),
83 PLL_RATE(1512000000, 63, 1, 0),
84 PLL_RATE(1536000000, 64, 1, 0),
85 { /* sentinel */ }, 45 { /* sentinel */ },
86}; 46};
87 47
@@ -94,8 +54,13 @@ static struct clk_fixed_rate meson8b_xtal = {
94 }, 54 },
95}; 55};
96 56
97static struct clk_regmap meson8b_fixed_pll = { 57static struct clk_regmap meson8b_fixed_pll_dco = {
98 .data = &(struct meson_clk_pll_data){ 58 .data = &(struct meson_clk_pll_data){
59 .en = {
60 .reg_off = HHI_MPLL_CNTL,
61 .shift = 30,
62 .width = 1,
63 },
99 .m = { 64 .m = {
100 .reg_off = HHI_MPLL_CNTL, 65 .reg_off = HHI_MPLL_CNTL,
101 .shift = 0, 66 .shift = 0,
@@ -106,11 +71,6 @@ static struct clk_regmap meson8b_fixed_pll = {
106 .shift = 9, 71 .shift = 9,
107 .width = 5, 72 .width = 5,
108 }, 73 },
109 .od = {
110 .reg_off = HHI_MPLL_CNTL,
111 .shift = 16,
112 .width = 2,
113 },
114 .frac = { 74 .frac = {
115 .reg_off = HHI_MPLL_CNTL2, 75 .reg_off = HHI_MPLL_CNTL2,
116 .shift = 0, 76 .shift = 0,
@@ -128,16 +88,39 @@ static struct clk_regmap meson8b_fixed_pll = {
128 }, 88 },
129 }, 89 },
130 .hw.init = &(struct clk_init_data){ 90 .hw.init = &(struct clk_init_data){
131 .name = "fixed_pll", 91 .name = "fixed_pll_dco",
132 .ops = &meson_clk_pll_ro_ops, 92 .ops = &meson_clk_pll_ro_ops,
133 .parent_names = (const char *[]){ "xtal" }, 93 .parent_names = (const char *[]){ "xtal" },
134 .num_parents = 1, 94 .num_parents = 1,
135 .flags = CLK_GET_RATE_NOCACHE,
136 }, 95 },
137}; 96};
138 97
139static struct clk_regmap meson8b_vid_pll = { 98static struct clk_regmap meson8b_fixed_pll = {
99 .data = &(struct clk_regmap_div_data){
100 .offset = HHI_MPLL_CNTL,
101 .shift = 16,
102 .width = 2,
103 .flags = CLK_DIVIDER_POWER_OF_TWO,
104 },
105 .hw.init = &(struct clk_init_data){
106 .name = "fixed_pll",
107 .ops = &clk_regmap_divider_ro_ops,
108 .parent_names = (const char *[]){ "fixed_pll_dco" },
109 .num_parents = 1,
110 /*
111 * This clock won't ever change at runtime so
112 * CLK_SET_RATE_PARENT is not required
113 */
114 },
115};
116
117static struct clk_regmap meson8b_vid_pll_dco = {
140 .data = &(struct meson_clk_pll_data){ 118 .data = &(struct meson_clk_pll_data){
119 .en = {
120 .reg_off = HHI_VID_PLL_CNTL,
121 .shift = 30,
122 .width = 1,
123 },
141 .m = { 124 .m = {
142 .reg_off = HHI_VID_PLL_CNTL, 125 .reg_off = HHI_VID_PLL_CNTL,
143 .shift = 0, 126 .shift = 0,
@@ -148,11 +131,6 @@ static struct clk_regmap meson8b_vid_pll = {
148 .shift = 9, 131 .shift = 9,
149 .width = 5, 132 .width = 5,
150 }, 133 },
151 .od = {
152 .reg_off = HHI_VID_PLL_CNTL,
153 .shift = 16,
154 .width = 2,
155 },
156 .l = { 134 .l = {
157 .reg_off = HHI_VID_PLL_CNTL, 135 .reg_off = HHI_VID_PLL_CNTL,
158 .shift = 31, 136 .shift = 31,
@@ -165,16 +143,36 @@ static struct clk_regmap meson8b_vid_pll = {
165 }, 143 },
166 }, 144 },
167 .hw.init = &(struct clk_init_data){ 145 .hw.init = &(struct clk_init_data){
168 .name = "vid_pll", 146 .name = "vid_pll_dco",
169 .ops = &meson_clk_pll_ro_ops, 147 .ops = &meson_clk_pll_ro_ops,
170 .parent_names = (const char *[]){ "xtal" }, 148 .parent_names = (const char *[]){ "xtal" },
171 .num_parents = 1, 149 .num_parents = 1,
172 .flags = CLK_GET_RATE_NOCACHE,
173 }, 150 },
174}; 151};
175 152
176static struct clk_regmap meson8b_sys_pll = { 153static struct clk_regmap meson8b_vid_pll = {
154 .data = &(struct clk_regmap_div_data){
155 .offset = HHI_VID_PLL_CNTL,
156 .shift = 16,
157 .width = 2,
158 .flags = CLK_DIVIDER_POWER_OF_TWO,
159 },
160 .hw.init = &(struct clk_init_data){
161 .name = "vid_pll",
162 .ops = &clk_regmap_divider_ro_ops,
163 .parent_names = (const char *[]){ "vid_pll_dco" },
164 .num_parents = 1,
165 .flags = CLK_SET_RATE_PARENT,
166 },
167};
168
169static struct clk_regmap meson8b_sys_pll_dco = {
177 .data = &(struct meson_clk_pll_data){ 170 .data = &(struct meson_clk_pll_data){
171 .en = {
172 .reg_off = HHI_SYS_PLL_CNTL,
173 .shift = 30,
174 .width = 1,
175 },
178 .m = { 176 .m = {
179 .reg_off = HHI_SYS_PLL_CNTL, 177 .reg_off = HHI_SYS_PLL_CNTL,
180 .shift = 0, 178 .shift = 0,
@@ -185,11 +183,6 @@ static struct clk_regmap meson8b_sys_pll = {
185 .shift = 9, 183 .shift = 9,
186 .width = 5, 184 .width = 5,
187 }, 185 },
188 .od = {
189 .reg_off = HHI_SYS_PLL_CNTL,
190 .shift = 16,
191 .width = 2,
192 },
193 .l = { 186 .l = {
194 .reg_off = HHI_SYS_PLL_CNTL, 187 .reg_off = HHI_SYS_PLL_CNTL,
195 .shift = 31, 188 .shift = 31,
@@ -200,14 +193,29 @@ static struct clk_regmap meson8b_sys_pll = {
200 .shift = 29, 193 .shift = 29,
201 .width = 1, 194 .width = 1,
202 }, 195 },
203 .table = sys_pll_rate_table, 196 .table = sys_pll_params_table,
204 }, 197 },
205 .hw.init = &(struct clk_init_data){ 198 .hw.init = &(struct clk_init_data){
206 .name = "sys_pll", 199 .name = "sys_pll_dco",
207 .ops = &meson_clk_pll_ro_ops, 200 .ops = &meson_clk_pll_ro_ops,
208 .parent_names = (const char *[]){ "xtal" }, 201 .parent_names = (const char *[]){ "xtal" },
209 .num_parents = 1, 202 .num_parents = 1,
210 .flags = CLK_GET_RATE_NOCACHE, 203 },
204};
205
206static struct clk_regmap meson8b_sys_pll = {
207 .data = &(struct clk_regmap_div_data){
208 .offset = HHI_SYS_PLL_CNTL,
209 .shift = 16,
210 .width = 2,
211 .flags = CLK_DIVIDER_POWER_OF_TWO,
212 },
213 .hw.init = &(struct clk_init_data){
214 .name = "sys_pll",
215 .ops = &clk_regmap_divider_ro_ops,
216 .parent_names = (const char *[]){ "sys_pll_dco" },
217 .num_parents = 1,
218 .flags = CLK_SET_RATE_PARENT,
211 }, 219 },
212}; 220};
213 221
@@ -879,6 +887,9 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
879 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw, 887 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
880 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw, 888 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
881 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw, 889 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
890 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
891 [CLKID_PLL_VID_DCO] = &meson8b_vid_pll_dco.hw,
892 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
882 [CLK_NR_CLKS] = NULL, 893 [CLK_NR_CLKS] = NULL,
883 }, 894 },
884 .num = CLK_NR_CLKS, 895 .num = CLK_NR_CLKS,
@@ -987,6 +998,9 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
987 &meson8b_nand_clk_sel, 998 &meson8b_nand_clk_sel,
988 &meson8b_nand_clk_div, 999 &meson8b_nand_clk_div,
989 &meson8b_nand_clk_gate, 1000 &meson8b_nand_clk_gate,
1001 &meson8b_fixed_pll_dco,
1002 &meson8b_vid_pll_dco,
1003 &meson8b_sys_pll_dco,
990}; 1004};
991 1005
992static const struct meson8b_clk_reset_line { 1006static const struct meson8b_clk_reset_line {
@@ -1050,7 +1064,6 @@ static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
1050 container_of(rcdev, struct meson8b_clk_reset, reset); 1064 container_of(rcdev, struct meson8b_clk_reset, reset);
1051 unsigned long flags; 1065 unsigned long flags;
1052 const struct meson8b_clk_reset_line *reset; 1066 const struct meson8b_clk_reset_line *reset;
1053 u32 val;
1054 1067
1055 if (id >= ARRAY_SIZE(meson8b_clk_reset_bits)) 1068 if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
1056 return -EINVAL; 1069 return -EINVAL;
@@ -1059,12 +1072,12 @@ static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
1059 1072
1060 spin_lock_irqsave(&meson_clk_lock, flags); 1073 spin_lock_irqsave(&meson_clk_lock, flags);
1061 1074
1062 val = readl(meson8b_clk_reset->base + reset->reg);
1063 if (assert) 1075 if (assert)
1064 val |= BIT(reset->bit_idx); 1076 regmap_update_bits(meson8b_clk_reset->regmap, reset->reg,
1077 BIT(reset->bit_idx), BIT(reset->bit_idx));
1065 else 1078 else
1066 val &= ~BIT(reset->bit_idx); 1079 regmap_update_bits(meson8b_clk_reset->regmap, reset->reg,
1067 writel(val, meson8b_clk_reset->base + reset->reg); 1080 BIT(reset->bit_idx), 0);
1068 1081
1069 spin_unlock_irqrestore(&meson_clk_lock, flags); 1082 spin_unlock_irqrestore(&meson_clk_lock, flags);
1070 1083
@@ -1094,62 +1107,12 @@ static const struct regmap_config clkc_regmap_config = {
1094 .reg_stride = 4, 1107 .reg_stride = 4,
1095}; 1108};
1096 1109
1097static int meson8b_clkc_probe(struct platform_device *pdev) 1110static void __init meson8b_clkc_init(struct device_node *np)
1098{
1099 int ret, i;
1100 struct device *dev = &pdev->dev;
1101 struct regmap *map;
1102
1103 if (!clk_base)
1104 return -ENXIO;
1105
1106 map = devm_regmap_init_mmio(dev, clk_base, &clkc_regmap_config);
1107 if (IS_ERR(map))
1108 return PTR_ERR(map);
1109
1110 /* Populate regmap for the regmap backed clocks */
1111 for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++)
1112 meson8b_clk_regmaps[i]->map = map;
1113
1114 /*
1115 * register all clks
1116 * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
1117 */
1118 for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) {
1119 /* array might be sparse */
1120 if (!meson8b_hw_onecell_data.hws[i])
1121 continue;
1122
1123 ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[i]);
1124 if (ret)
1125 return ret;
1126 }
1127
1128 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1129 &meson8b_hw_onecell_data);
1130}
1131
1132static const struct of_device_id meson8b_clkc_match_table[] = {
1133 { .compatible = "amlogic,meson8-clkc" },
1134 { .compatible = "amlogic,meson8b-clkc" },
1135 { .compatible = "amlogic,meson8m2-clkc" },
1136 { }
1137};
1138
1139static struct platform_driver meson8b_driver = {
1140 .probe = meson8b_clkc_probe,
1141 .driver = {
1142 .name = "meson8b-clkc",
1143 .of_match_table = meson8b_clkc_match_table,
1144 },
1145};
1146
1147builtin_platform_driver(meson8b_driver);
1148
1149static void __init meson8b_clkc_reset_init(struct device_node *np)
1150{ 1111{
1151 struct meson8b_clk_reset *rstc; 1112 struct meson8b_clk_reset *rstc;
1152 int ret; 1113 void __iomem *clk_base;
1114 struct regmap *map;
1115 int i, ret;
1153 1116
1154 /* Generic clocks, PLLs and some of the reset-bits */ 1117 /* Generic clocks, PLLs and some of the reset-bits */
1155 clk_base = of_iomap(np, 1); 1118 clk_base = of_iomap(np, 1);
@@ -1158,12 +1121,16 @@ static void __init meson8b_clkc_reset_init(struct device_node *np)
1158 return; 1121 return;
1159 } 1122 }
1160 1123
1124 map = regmap_init_mmio(NULL, clk_base, &clkc_regmap_config);
1125 if (IS_ERR(map))
1126 return;
1127
1161 rstc = kzalloc(sizeof(*rstc), GFP_KERNEL); 1128 rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
1162 if (!rstc) 1129 if (!rstc)
1163 return; 1130 return;
1164 1131
1165 /* Reset Controller */ 1132 /* Reset Controller */
1166 rstc->base = clk_base; 1133 rstc->regmap = map;
1167 rstc->reset.ops = &meson8b_clk_reset_ops; 1134 rstc->reset.ops = &meson8b_clk_reset_ops;
1168 rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits); 1135 rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits);
1169 rstc->reset.of_node = np; 1136 rstc->reset.of_node = np;
@@ -1173,11 +1140,34 @@ static void __init meson8b_clkc_reset_init(struct device_node *np)
1173 __func__, ret); 1140 __func__, ret);
1174 return; 1141 return;
1175 } 1142 }
1143
1144 /* Populate regmap for the regmap backed clocks */
1145 for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++)
1146 meson8b_clk_regmaps[i]->map = map;
1147
1148 /*
1149 * register all clks
1150 * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
1151 */
1152 for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) {
1153 /* array might be sparse */
1154 if (!meson8b_hw_onecell_data.hws[i])
1155 continue;
1156
1157 ret = clk_hw_register(NULL, meson8b_hw_onecell_data.hws[i]);
1158 if (ret)
1159 return;
1160 }
1161
1162 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
1163 &meson8b_hw_onecell_data);
1164 if (ret)
1165 pr_err("%s: failed to register clock provider\n", __func__);
1176} 1166}
1177 1167
1178CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc", 1168CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
1179 meson8b_clkc_reset_init); 1169 meson8b_clkc_init);
1180CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc", 1170CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
1181 meson8b_clkc_reset_init); 1171 meson8b_clkc_init);
1182CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc", 1172CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
1183 meson8b_clkc_reset_init); 1173 meson8b_clkc_init);
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 5d09412b5084..1c6fb180e6a2 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -75,8 +75,11 @@
75#define CLKID_FCLK_DIV7_DIV 109 75#define CLKID_FCLK_DIV7_DIV 109
76#define CLKID_NAND_SEL 110 76#define CLKID_NAND_SEL 110
77#define CLKID_NAND_DIV 111 77#define CLKID_NAND_DIV 111
78#define CLKID_PLL_FIXED_DCO 113
79#define CLKID_PLL_VID_DCO 114
80#define CLKID_PLL_SYS_DCO 115
78 81
79#define CLK_NR_CLKS 113 82#define CLK_NR_CLKS 116
80 83
81/* 84/*
82 * include the CLKID and RESETID that have 85 * include the CLKID and RESETID that have
diff --git a/drivers/clk/mvebu/ap806-system-controller.c b/drivers/clk/mvebu/ap806-system-controller.c
index fa2fbd2cef4a..ea54a874bbda 100644
--- a/drivers/clk/mvebu/ap806-system-controller.c
+++ b/drivers/clk/mvebu/ap806-system-controller.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Marvell Armada AP806 System Controller 3 * Marvell Armada AP806 System Controller
3 * 4 *
@@ -5,9 +6,6 @@
5 * 6 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * 8 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */ 9 */
12 10
13#define pr_fmt(fmt) "ap806-system-controller: " fmt 11#define pr_fmt(fmt) "ap806-system-controller: " fmt
@@ -155,7 +153,6 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
155 goto fail4; 153 goto fail4;
156 } 154 }
157 155
158 of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
159 ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data); 156 ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
160 if (ret) 157 if (ret)
161 goto fail_clk_add; 158 goto fail_clk_add;
diff --git a/drivers/clk/mvebu/armada-370.c b/drivers/clk/mvebu/armada-370.c
index 2c7c1085f883..7dedfaa6e152 100644
--- a/drivers/clk/mvebu/armada-370.c
+++ b/drivers/clk/mvebu/armada-370.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Marvell Armada 370 SoC clocks 3 * Marvell Armada 370 SoC clocks
3 * 4 *
@@ -7,9 +8,6 @@
7 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
8 * Andrew Lunn <andrew@lunn.ch> 9 * Andrew Lunn <andrew@lunn.ch>
9 * 10 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */ 11 */
14 12
15#include <linux/kernel.h> 13#include <linux/kernel.h>
diff --git a/drivers/clk/mvebu/armada-375.c b/drivers/clk/mvebu/armada-375.c
index c7af2242b796..a7157c690238 100644
--- a/drivers/clk/mvebu/armada-375.c
+++ b/drivers/clk/mvebu/armada-375.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Marvell Armada 375 SoC clocks 3 * Marvell Armada 375 SoC clocks
3 * 4 *
@@ -7,9 +8,6 @@
7 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
8 * Andrew Lunn <andrew@lunn.ch> 9 * Andrew Lunn <andrew@lunn.ch>
9 * 10 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */ 11 */
14 12
15#include <linux/kernel.h> 13#include <linux/kernel.h>
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
index 499f5962c8b0..1f1cff428d78 100644
--- a/drivers/clk/mvebu/armada-37xx-periph.c
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
@@ -56,6 +56,15 @@
56struct clk_periph_driver_data { 56struct clk_periph_driver_data {
57 struct clk_hw_onecell_data *hw_data; 57 struct clk_hw_onecell_data *hw_data;
58 spinlock_t lock; 58 spinlock_t lock;
59 void __iomem *reg;
60
61 /* Storage registers for suspend/resume operations */
62 u32 tbg_sel;
63 u32 div_sel0;
64 u32 div_sel1;
65 u32 div_sel2;
66 u32 clk_sel;
67 u32 clk_dis;
59}; 68};
60 69
61struct clk_double_div { 70struct clk_double_div {
@@ -672,6 +681,40 @@ static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
672 return PTR_ERR_OR_ZERO(*hw); 681 return PTR_ERR_OR_ZERO(*hw);
673} 682}
674 683
684static int __maybe_unused armada_3700_periph_clock_suspend(struct device *dev)
685{
686 struct clk_periph_driver_data *data = dev_get_drvdata(dev);
687
688 data->tbg_sel = readl(data->reg + TBG_SEL);
689 data->div_sel0 = readl(data->reg + DIV_SEL0);
690 data->div_sel1 = readl(data->reg + DIV_SEL1);
691 data->div_sel2 = readl(data->reg + DIV_SEL2);
692 data->clk_sel = readl(data->reg + CLK_SEL);
693 data->clk_dis = readl(data->reg + CLK_DIS);
694
695 return 0;
696}
697
698static int __maybe_unused armada_3700_periph_clock_resume(struct device *dev)
699{
700 struct clk_periph_driver_data *data = dev_get_drvdata(dev);
701
702 /* Follow the same order than what the Cortex-M3 does (ATF code) */
703 writel(data->clk_dis, data->reg + CLK_DIS);
704 writel(data->div_sel0, data->reg + DIV_SEL0);
705 writel(data->div_sel1, data->reg + DIV_SEL1);
706 writel(data->div_sel2, data->reg + DIV_SEL2);
707 writel(data->tbg_sel, data->reg + TBG_SEL);
708 writel(data->clk_sel, data->reg + CLK_SEL);
709
710 return 0;
711}
712
713static const struct dev_pm_ops armada_3700_periph_clock_pm_ops = {
714 SET_SYSTEM_SLEEP_PM_OPS(armada_3700_periph_clock_suspend,
715 armada_3700_periph_clock_resume)
716};
717
675static int armada_3700_periph_clock_probe(struct platform_device *pdev) 718static int armada_3700_periph_clock_probe(struct platform_device *pdev)
676{ 719{
677 struct clk_periph_driver_data *driver_data; 720 struct clk_periph_driver_data *driver_data;
@@ -680,7 +723,6 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
680 struct device *dev = &pdev->dev; 723 struct device *dev = &pdev->dev;
681 int num_periph = 0, i, ret; 724 int num_periph = 0, i, ret;
682 struct resource *res; 725 struct resource *res;
683 void __iomem *reg;
684 726
685 data = of_device_get_match_data(dev); 727 data = of_device_get_match_data(dev);
686 if (!data) 728 if (!data)
@@ -689,11 +731,6 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
689 while (data[num_periph].name) 731 while (data[num_periph].name)
690 num_periph++; 732 num_periph++;
691 733
692 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
693 reg = devm_ioremap_resource(dev, res);
694 if (IS_ERR(reg))
695 return PTR_ERR(reg);
696
697 driver_data = devm_kzalloc(dev, sizeof(*driver_data), GFP_KERNEL); 734 driver_data = devm_kzalloc(dev, sizeof(*driver_data), GFP_KERNEL);
698 if (!driver_data) 735 if (!driver_data)
699 return -ENOMEM; 736 return -ENOMEM;
@@ -706,12 +743,16 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
706 return -ENOMEM; 743 return -ENOMEM;
707 driver_data->hw_data->num = num_periph; 744 driver_data->hw_data->num = num_periph;
708 745
746 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
747 driver_data->reg = devm_ioremap_resource(dev, res);
748 if (IS_ERR(driver_data->reg))
749 return PTR_ERR(driver_data->reg);
750
709 spin_lock_init(&driver_data->lock); 751 spin_lock_init(&driver_data->lock);
710 752
711 for (i = 0; i < num_periph; i++) { 753 for (i = 0; i < num_periph; i++) {
712 struct clk_hw **hw = &driver_data->hw_data->hws[i]; 754 struct clk_hw **hw = &driver_data->hw_data->hws[i];
713 755 if (armada_3700_add_composite_clk(&data[i], driver_data->reg,
714 if (armada_3700_add_composite_clk(&data[i], reg,
715 &driver_data->lock, dev, hw)) 756 &driver_data->lock, dev, hw))
716 dev_err(dev, "Can't register periph clock %s\n", 757 dev_err(dev, "Can't register periph clock %s\n",
717 data[i].name); 758 data[i].name);
@@ -749,6 +790,7 @@ static struct platform_driver armada_3700_periph_clock_driver = {
749 .driver = { 790 .driver = {
750 .name = "marvell-armada-3700-periph-clock", 791 .name = "marvell-armada-3700-periph-clock",
751 .of_match_table = armada_3700_periph_clock_of_match, 792 .of_match_table = armada_3700_periph_clock_of_match,
793 .pm = &armada_3700_periph_clock_pm_ops,
752 }, 794 },
753}; 795};
754 796
diff --git a/drivers/clk/mvebu/armada-37xx-tbg.c b/drivers/clk/mvebu/armada-37xx-tbg.c
index 7ff041f73b55..ee272d4d8c24 100644
--- a/drivers/clk/mvebu/armada-37xx-tbg.c
+++ b/drivers/clk/mvebu/armada-37xx-tbg.c
@@ -1,13 +1,10 @@
1// SPDX-License-Identifier: GPL-2.0+
1/* 2/*
2 * Marvell Armada 37xx SoC Time Base Generator clocks 3 * Marvell Armada 37xx SoC Time Base Generator clocks
3 * 4 *
4 * Copyright (C) 2016 Marvell 5 * Copyright (C) 2016 Marvell
5 * 6 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2 or later. This program is licensed "as is"
10 * without any warranty of any kind, whether express or implied.
11 */ 8 */
12 9
13#include <linux/clk-provider.h> 10#include <linux/clk-provider.h>
@@ -99,12 +96,13 @@ static int armada_3700_tbg_clock_probe(struct platform_device *pdev)
99 hw_tbg_data->num = NUM_TBG; 96 hw_tbg_data->num = NUM_TBG;
100 platform_set_drvdata(pdev, hw_tbg_data); 97 platform_set_drvdata(pdev, hw_tbg_data);
101 98
102 parent = devm_clk_get(dev, NULL); 99 parent = clk_get(dev, NULL);
103 if (IS_ERR(parent)) { 100 if (IS_ERR(parent)) {
104 dev_err(dev, "Could get the clock parent\n"); 101 dev_err(dev, "Could get the clock parent\n");
105 return -EINVAL; 102 return -EINVAL;
106 } 103 }
107 parent_name = __clk_get_name(parent); 104 parent_name = __clk_get_name(parent);
105 clk_put(parent);
108 106
109 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 107 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
110 reg = devm_ioremap_resource(dev, res); 108 reg = devm_ioremap_resource(dev, res);
diff --git a/drivers/clk/mvebu/armada-37xx-xtal.c b/drivers/clk/mvebu/armada-37xx-xtal.c
index 612d65ede10a..e9e306d4e9af 100644
--- a/drivers/clk/mvebu/armada-37xx-xtal.c
+++ b/drivers/clk/mvebu/armada-37xx-xtal.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Marvell Armada 37xx SoC xtal clocks 3 * Marvell Armada 37xx SoC xtal clocks
3 * 4 *
@@ -5,9 +6,6 @@
5 * 6 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * 8 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */ 9 */
12 10
13#include <linux/clk-provider.h> 11#include <linux/clk-provider.h>
diff --git a/drivers/clk/mvebu/armada-38x.c b/drivers/clk/mvebu/armada-38x.c
index 9ff4ea63932d..ef2ab81f087d 100644
--- a/drivers/clk/mvebu/armada-38x.c
+++ b/drivers/clk/mvebu/armada-38x.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Marvell Armada 380/385 SoC clocks 3 * Marvell Armada 380/385 SoC clocks
3 * 4 *
@@ -7,9 +8,6 @@
7 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
8 * Andrew Lunn <andrew@lunn.ch> 9 * Andrew Lunn <andrew@lunn.ch>
9 * 10 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */ 11 */
14 12
15#include <linux/kernel.h> 13#include <linux/kernel.h>
diff --git a/drivers/clk/mvebu/armada-39x.c b/drivers/clk/mvebu/armada-39x.c
index 4fdfd32247a9..674ccfd6236e 100644
--- a/drivers/clk/mvebu/armada-39x.c
+++ b/drivers/clk/mvebu/armada-39x.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Marvell Armada 39x SoC clocks 3 * Marvell Armada 39x SoC clocks
3 * 4 *
@@ -8,9 +9,6 @@
8 * Andrew Lunn <andrew@lunn.ch> 9 * Andrew Lunn <andrew@lunn.ch>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * 11 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */ 12 */
15 13
16#include <linux/kernel.h> 14#include <linux/kernel.h>
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
index 0ec44ae9a2a2..e8f03293ec83 100644
--- a/drivers/clk/mvebu/armada-xp.c
+++ b/drivers/clk/mvebu/armada-xp.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Marvell Armada XP SoC clocks 3 * Marvell Armada XP SoC clocks
3 * 4 *
@@ -7,9 +8,6 @@
7 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
8 * Andrew Lunn <andrew@lunn.ch> 9 * Andrew Lunn <andrew@lunn.ch>
9 * 10 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */ 11 */
14 12
15#include <linux/kernel.h> 13#include <linux/kernel.h>
diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c
index 68f05c53d40e..1fc84b0e72ee 100644
--- a/drivers/clk/mvebu/clk-corediv.c
+++ b/drivers/clk/mvebu/clk-corediv.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * MVEBU Core divider clock 3 * MVEBU Core divider clock
3 * 4 *
@@ -5,9 +6,6 @@
5 * 6 *
6 * Ezequiel Garcia <ezequiel.garcia@free-electrons.com> 7 * Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
7 * 8 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */ 9 */
12 10
13#include <linux/kernel.h> 11#include <linux/kernel.h>
diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
index 072aa38374ce..d1a715767364 100644
--- a/drivers/clk/mvebu/clk-cpu.c
+++ b/drivers/clk/mvebu/clk-cpu.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Marvell MVEBU CPU clock handling. 3 * Marvell MVEBU CPU clock handling.
3 * 4 *
@@ -5,9 +6,6 @@
5 * 6 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * 8 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */ 9 */
12#include <linux/kernel.h> 10#include <linux/kernel.h>
13#include <linux/slab.h> 11#include <linux/slab.h>
diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
index 472c88b90256..6ab3c2e627c7 100644
--- a/drivers/clk/mvebu/common.c
+++ b/drivers/clk/mvebu/common.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Marvell EBU SoC common clock handling 3 * Marvell EBU SoC common clock handling
3 * 4 *
@@ -7,9 +8,6 @@
7 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
8 * Andrew Lunn <andrew@lunn.ch> 9 * Andrew Lunn <andrew@lunn.ch>
9 * 10 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */ 11 */
14 12
15#include <linux/kernel.h> 13#include <linux/kernel.h>
diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h
index f0de6c8a494a..d1ab79b43105 100644
--- a/drivers/clk/mvebu/common.h
+++ b/drivers/clk/mvebu/common.h
@@ -1,3 +1,4 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Marvell EBU SoC common clock handling 3 * Marvell EBU SoC common clock handling
3 * 4 *
@@ -7,9 +8,6 @@
7 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
8 * Andrew Lunn <andrew@lunn.ch> 9 * Andrew Lunn <andrew@lunn.ch>
9 * 10 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */ 11 */
14 12
15#ifndef __CLK_MVEBU_COMMON_H_ 13#ifndef __CLK_MVEBU_COMMON_H_
diff --git a/drivers/clk/mvebu/cp110-system-controller.c b/drivers/clk/mvebu/cp110-system-controller.c
index 75bf7b8f282f..9781b1bf5998 100644
--- a/drivers/clk/mvebu/cp110-system-controller.c
+++ b/drivers/clk/mvebu/cp110-system-controller.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Marvell Armada CP110 System Controller 3 * Marvell Armada CP110 System Controller
3 * 4 *
@@ -5,9 +6,6 @@
5 * 6 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * 8 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */ 9 */
12 10
13/* 11/*
diff --git a/drivers/clk/mvebu/dove.c b/drivers/clk/mvebu/dove.c
index 59fad9546c84..e0dd99f36bf4 100644
--- a/drivers/clk/mvebu/dove.c
+++ b/drivers/clk/mvebu/dove.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Marvell Dove SoC clocks 3 * Marvell Dove SoC clocks
3 * 4 *
@@ -7,9 +8,6 @@
7 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
8 * Andrew Lunn <andrew@lunn.ch> 9 * Andrew Lunn <andrew@lunn.ch>
9 * 10 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */ 11 */
14 12
15#include <linux/kernel.h> 13#include <linux/kernel.h>
diff --git a/drivers/clk/mvebu/kirkwood.c b/drivers/clk/mvebu/kirkwood.c
index a2a8d614039d..6f784167bda4 100644
--- a/drivers/clk/mvebu/kirkwood.c
+++ b/drivers/clk/mvebu/kirkwood.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Marvell Kirkwood SoC clocks 3 * Marvell Kirkwood SoC clocks
3 * 4 *
@@ -7,9 +8,6 @@
7 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
8 * Andrew Lunn <andrew@lunn.ch> 9 * Andrew Lunn <andrew@lunn.ch>
9 * 10 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */ 11 */
14 12
15#include <linux/kernel.h> 13#include <linux/kernel.h>
diff --git a/drivers/clk/mvebu/mv98dx3236.c b/drivers/clk/mvebu/mv98dx3236.c
index 6e203af73cac..0a74cf7a7725 100644
--- a/drivers/clk/mvebu/mv98dx3236.c
+++ b/drivers/clk/mvebu/mv98dx3236.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Marvell MV98DX3236 SoC clocks 3 * Marvell MV98DX3236 SoC clocks
3 * 4 *
@@ -7,9 +8,6 @@
7 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
8 * Andrew Lunn <andrew@lunn.ch> 9 * Andrew Lunn <andrew@lunn.ch>
9 * 10 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */ 11 */
14 12
15#include <linux/kernel.h> 13#include <linux/kernel.h>
diff --git a/drivers/clk/mvebu/orion.c b/drivers/clk/mvebu/orion.c
index a6e5bee23385..f681a65be20a 100644
--- a/drivers/clk/mvebu/orion.c
+++ b/drivers/clk/mvebu/orion.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Marvell Orion SoC clocks 3 * Marvell Orion SoC clocks
3 * 4 *
@@ -5,9 +6,6 @@
5 * 6 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * 8 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */ 9 */
12 10
13#include <linux/kernel.h> 11#include <linux/kernel.h>
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 064768699fe7..178b0c4c06e5 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -235,6 +235,31 @@ config MSM_GCC_8998
235 Say Y if you want to use peripheral devices such as UART, SPI, 235 Say Y if you want to use peripheral devices such as UART, SPI,
236 i2c, USB, UFS, SD/eMMC, PCIe, etc. 236 i2c, USB, UFS, SD/eMMC, PCIe, etc.
237 237
238config QCS_GCC_404
239 tristate "QCS404 Global Clock Controller"
240 depends on COMMON_CLK_QCOM
241 help
242 Support for the global clock controller on QCS404 devices.
243 Say Y if you want to use multimedia devices or peripheral
244 devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
245
246config SDM_CAMCC_845
247 tristate "SDM845 Camera Clock Controller"
248 depends on COMMON_CLK_QCOM
249 select SDM_GCC_845
250 help
251 Support for the camera clock controller on SDM845 devices.
252 Say Y if you want to support camera devices and camera functionality.
253
254config SDM_GCC_660
255 tristate "SDM660 Global Clock Controller"
256 select QCOM_GDSC
257 depends on COMMON_CLK_QCOM
258 help
259 Support for the global clock controller on SDM660 devices.
260 Say Y if you want to use peripheral devices such as UART, SPI,
261 i2C, USB, UFS, SDDC, PCIe, etc.
262
238config SDM_GCC_845 263config SDM_GCC_845
239 tristate "SDM845 Global Clock Controller" 264 tristate "SDM845 Global Clock Controller"
240 select QCOM_GDSC 265 select QCOM_GDSC
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 21a45035930d..191367eddfc0 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -39,7 +39,10 @@ obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
39obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o 39obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
40obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o 40obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
41obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o 41obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
42obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o
43obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o
42obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o 44obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
45obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o
43obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o 46obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
44obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o 47obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
45obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o 48obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c
new file mode 100644
index 000000000000..1b2cefef7431
--- /dev/null
+++ b/drivers/clk/qcom/camcc-sdm845.c
@@ -0,0 +1,1745 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk-provider.h>
7#include <linux/module.h>
8#include <linux/platform_device.h>
9#include <linux/regmap.h>
10
11#include <dt-bindings/clock/qcom,camcc-sdm845.h>
12
13#include "common.h"
14#include "clk-alpha-pll.h"
15#include "clk-branch.h"
16#include "clk-rcg.h"
17#include "clk-regmap.h"
18#include "gdsc.h"
19
20enum {
21 P_BI_TCXO,
22 P_CAM_CC_PLL0_OUT_EVEN,
23 P_CAM_CC_PLL1_OUT_EVEN,
24 P_CAM_CC_PLL2_OUT_EVEN,
25 P_CAM_CC_PLL3_OUT_EVEN,
26 P_CORE_BI_PLL_TEST_SE,
27};
28
29static const struct parent_map cam_cc_parent_map_0[] = {
30 { P_BI_TCXO, 0 },
31 { P_CAM_CC_PLL2_OUT_EVEN, 1 },
32 { P_CAM_CC_PLL1_OUT_EVEN, 2 },
33 { P_CAM_CC_PLL3_OUT_EVEN, 5 },
34 { P_CAM_CC_PLL0_OUT_EVEN, 6 },
35 { P_CORE_BI_PLL_TEST_SE, 7 },
36};
37
38static const char * const cam_cc_parent_names_0[] = {
39 "bi_tcxo",
40 "cam_cc_pll2_out_even",
41 "cam_cc_pll1_out_even",
42 "cam_cc_pll3_out_even",
43 "cam_cc_pll0_out_even",
44 "core_bi_pll_test_se",
45};
46
47static struct clk_alpha_pll cam_cc_pll0 = {
48 .offset = 0x0,
49 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
50 .clkr = {
51 .hw.init = &(struct clk_init_data){
52 .name = "cam_cc_pll0",
53 .parent_names = (const char *[]){ "bi_tcxo" },
54 .num_parents = 1,
55 .ops = &clk_alpha_pll_fabia_ops,
56 },
57 },
58};
59
60static const struct clk_div_table post_div_table_fabia_even[] = {
61 { 0x0, 1 },
62 { 0x1, 2 },
63 { }
64};
65
66static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
67 .offset = 0x0,
68 .post_div_shift = 8,
69 .post_div_table = post_div_table_fabia_even,
70 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
71 .width = 4,
72 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
73 .clkr.hw.init = &(struct clk_init_data){
74 .name = "cam_cc_pll0_out_even",
75 .parent_names = (const char *[]){ "cam_cc_pll0" },
76 .num_parents = 1,
77 .ops = &clk_alpha_pll_postdiv_fabia_ops,
78 },
79};
80
81static struct clk_alpha_pll cam_cc_pll1 = {
82 .offset = 0x1000,
83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
84 .clkr = {
85 .hw.init = &(struct clk_init_data){
86 .name = "cam_cc_pll1",
87 .parent_names = (const char *[]){ "bi_tcxo" },
88 .num_parents = 1,
89 .ops = &clk_alpha_pll_fabia_ops,
90 },
91 },
92};
93
94static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
95 .offset = 0x1000,
96 .post_div_shift = 8,
97 .post_div_table = post_div_table_fabia_even,
98 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
99 .width = 4,
100 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
101 .clkr.hw.init = &(struct clk_init_data){
102 .name = "cam_cc_pll1_out_even",
103 .parent_names = (const char *[]){ "cam_cc_pll1" },
104 .num_parents = 1,
105 .ops = &clk_alpha_pll_postdiv_fabia_ops,
106 },
107};
108
109static struct clk_alpha_pll cam_cc_pll2 = {
110 .offset = 0x2000,
111 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
112 .clkr = {
113 .hw.init = &(struct clk_init_data){
114 .name = "cam_cc_pll2",
115 .parent_names = (const char *[]){ "bi_tcxo" },
116 .num_parents = 1,
117 .ops = &clk_alpha_pll_fabia_ops,
118 },
119 },
120};
121
122static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = {
123 .offset = 0x2000,
124 .post_div_shift = 8,
125 .post_div_table = post_div_table_fabia_even,
126 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
127 .width = 4,
128 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
129 .clkr.hw.init = &(struct clk_init_data){
130 .name = "cam_cc_pll2_out_even",
131 .parent_names = (const char *[]){ "cam_cc_pll2" },
132 .num_parents = 1,
133 .ops = &clk_alpha_pll_postdiv_fabia_ops,
134 },
135};
136
137static struct clk_alpha_pll cam_cc_pll3 = {
138 .offset = 0x3000,
139 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
140 .clkr = {
141 .hw.init = &(struct clk_init_data){
142 .name = "cam_cc_pll3",
143 .parent_names = (const char *[]){ "bi_tcxo" },
144 .num_parents = 1,
145 .ops = &clk_alpha_pll_fabia_ops,
146 },
147 },
148};
149
150static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
151 .offset = 0x3000,
152 .post_div_shift = 8,
153 .post_div_table = post_div_table_fabia_even,
154 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
155 .width = 4,
156 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
157 .clkr.hw.init = &(struct clk_init_data){
158 .name = "cam_cc_pll3_out_even",
159 .parent_names = (const char *[]){ "cam_cc_pll3" },
160 .num_parents = 1,
161 .ops = &clk_alpha_pll_postdiv_fabia_ops,
162 },
163};
164
165static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
166 F(19200000, P_BI_TCXO, 1, 0, 0),
167 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
168 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
169 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
170 F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
171 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
172 { }
173};
174
175/*
176 * As per HW design, some of the CAMCC RCGs needs to
177 * move to XO clock during their clock disable so using
178 * clk_rcg2_shared_ops for such RCGs. This is required
179 * to power down the camera memories gracefully.
180 * Also, use CLK_SET_RATE_PARENT flag for the RCGs which
181 * have CAM_CC_PLL2_OUT_EVEN PLL as parent in frequency
182 * table and requires reconfiguration of the PLL frequency.
183 */
184static struct clk_rcg2 cam_cc_bps_clk_src = {
185 .cmd_rcgr = 0x600c,
186 .mnd_width = 0,
187 .hid_width = 5,
188 .parent_map = cam_cc_parent_map_0,
189 .freq_tbl = ftbl_cam_cc_bps_clk_src,
190 .clkr.hw.init = &(struct clk_init_data){
191 .name = "cam_cc_bps_clk_src",
192 .parent_names = cam_cc_parent_names_0,
193 .num_parents = 6,
194 .flags = CLK_SET_RATE_PARENT,
195 .ops = &clk_rcg2_shared_ops,
196 },
197};
198
199static const struct freq_tbl ftbl_cam_cc_cci_clk_src[] = {
200 F(19200000, P_BI_TCXO, 1, 0, 0),
201 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
202 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
203 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
204 { }
205};
206
207static struct clk_rcg2 cam_cc_cci_clk_src = {
208 .cmd_rcgr = 0xb0d8,
209 .mnd_width = 8,
210 .hid_width = 5,
211 .parent_map = cam_cc_parent_map_0,
212 .freq_tbl = ftbl_cam_cc_cci_clk_src,
213 .clkr.hw.init = &(struct clk_init_data){
214 .name = "cam_cc_cci_clk_src",
215 .parent_names = cam_cc_parent_names_0,
216 .num_parents = 6,
217 .ops = &clk_rcg2_ops,
218 },
219};
220
221static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
222 F(19200000, P_BI_TCXO, 1, 0, 0),
223 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
224 { }
225};
226
227static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
228 .cmd_rcgr = 0x9060,
229 .mnd_width = 0,
230 .hid_width = 5,
231 .parent_map = cam_cc_parent_map_0,
232 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
233 .clkr.hw.init = &(struct clk_init_data){
234 .name = "cam_cc_cphy_rx_clk_src",
235 .parent_names = cam_cc_parent_names_0,
236 .num_parents = 6,
237 .ops = &clk_rcg2_ops,
238 },
239};
240
241static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
242 F(19200000, P_BI_TCXO, 1, 0, 0),
243 F(240000000, P_CAM_CC_PLL2_OUT_EVEN, 2, 0, 0),
244 F(269333333, P_CAM_CC_PLL1_OUT_EVEN, 3, 0, 0),
245 { }
246};
247
248static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
249 .cmd_rcgr = 0x5004,
250 .mnd_width = 0,
251 .hid_width = 5,
252 .parent_map = cam_cc_parent_map_0,
253 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
254 .clkr.hw.init = &(struct clk_init_data){
255 .name = "cam_cc_csi0phytimer_clk_src",
256 .parent_names = cam_cc_parent_names_0,
257 .num_parents = 6,
258 .flags = CLK_SET_RATE_PARENT,
259 .ops = &clk_rcg2_ops,
260 },
261};
262
263static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
264 .cmd_rcgr = 0x5028,
265 .mnd_width = 0,
266 .hid_width = 5,
267 .parent_map = cam_cc_parent_map_0,
268 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
269 .clkr.hw.init = &(struct clk_init_data){
270 .name = "cam_cc_csi1phytimer_clk_src",
271 .parent_names = cam_cc_parent_names_0,
272 .num_parents = 6,
273 .flags = CLK_SET_RATE_PARENT,
274 .ops = &clk_rcg2_ops,
275 },
276};
277
278static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
279 .cmd_rcgr = 0x504c,
280 .mnd_width = 0,
281 .hid_width = 5,
282 .parent_map = cam_cc_parent_map_0,
283 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
284 .clkr.hw.init = &(struct clk_init_data){
285 .name = "cam_cc_csi2phytimer_clk_src",
286 .parent_names = cam_cc_parent_names_0,
287 .num_parents = 6,
288 .flags = CLK_SET_RATE_PARENT,
289 .ops = &clk_rcg2_ops,
290 },
291};
292
293static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
294 .cmd_rcgr = 0x5070,
295 .mnd_width = 0,
296 .hid_width = 5,
297 .parent_map = cam_cc_parent_map_0,
298 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
299 .clkr.hw.init = &(struct clk_init_data){
300 .name = "cam_cc_csi3phytimer_clk_src",
301 .parent_names = cam_cc_parent_names_0,
302 .num_parents = 6,
303 .flags = CLK_SET_RATE_PARENT,
304 .ops = &clk_rcg2_ops,
305 },
306};
307
308static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
309 F(19200000, P_BI_TCXO, 1, 0, 0),
310 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
311 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
312 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
313 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
314 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
315 { }
316};
317
318static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
319 .cmd_rcgr = 0x6038,
320 .mnd_width = 0,
321 .hid_width = 5,
322 .parent_map = cam_cc_parent_map_0,
323 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
324 .clkr.hw.init = &(struct clk_init_data){
325 .name = "cam_cc_fast_ahb_clk_src",
326 .parent_names = cam_cc_parent_names_0,
327 .num_parents = 6,
328 .ops = &clk_rcg2_ops,
329 },
330};
331
332static const struct freq_tbl ftbl_cam_cc_fd_core_clk_src[] = {
333 F(19200000, P_BI_TCXO, 1, 0, 0),
334 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
335 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
336 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),
337 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
338 { }
339};
340
341static struct clk_rcg2 cam_cc_fd_core_clk_src = {
342 .cmd_rcgr = 0xb0b0,
343 .mnd_width = 0,
344 .hid_width = 5,
345 .parent_map = cam_cc_parent_map_0,
346 .freq_tbl = ftbl_cam_cc_fd_core_clk_src,
347 .clkr.hw.init = &(struct clk_init_data){
348 .name = "cam_cc_fd_core_clk_src",
349 .parent_names = cam_cc_parent_names_0,
350 .num_parents = 6,
351 .ops = &clk_rcg2_shared_ops,
352 },
353};
354
355static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
356 F(19200000, P_BI_TCXO, 1, 0, 0),
357 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
358 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
359 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),
360 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
361 { }
362};
363
364static struct clk_rcg2 cam_cc_icp_clk_src = {
365 .cmd_rcgr = 0xb088,
366 .mnd_width = 0,
367 .hid_width = 5,
368 .parent_map = cam_cc_parent_map_0,
369 .freq_tbl = ftbl_cam_cc_icp_clk_src,
370 .clkr.hw.init = &(struct clk_init_data){
371 .name = "cam_cc_icp_clk_src",
372 .parent_names = cam_cc_parent_names_0,
373 .num_parents = 6,
374 .ops = &clk_rcg2_shared_ops,
375 },
376};
377
378static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
379 F(19200000, P_BI_TCXO, 1, 0, 0),
380 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
381 F(320000000, P_CAM_CC_PLL2_OUT_EVEN, 1.5, 0, 0),
382 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
383 F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
384 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
385 { }
386};
387
388static struct clk_rcg2 cam_cc_ife_0_clk_src = {
389 .cmd_rcgr = 0x900c,
390 .mnd_width = 0,
391 .hid_width = 5,
392 .parent_map = cam_cc_parent_map_0,
393 .freq_tbl = ftbl_cam_cc_ife_0_clk_src,
394 .clkr.hw.init = &(struct clk_init_data){
395 .name = "cam_cc_ife_0_clk_src",
396 .parent_names = cam_cc_parent_names_0,
397 .num_parents = 6,
398 .flags = CLK_SET_RATE_PARENT,
399 .ops = &clk_rcg2_shared_ops,
400 },
401};
402
403static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = {
404 F(19200000, P_BI_TCXO, 1, 0, 0),
405 F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
406 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
407 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),
408 { }
409};
410
411static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
412 .cmd_rcgr = 0x9038,
413 .mnd_width = 0,
414 .hid_width = 5,
415 .parent_map = cam_cc_parent_map_0,
416 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
417 .clkr.hw.init = &(struct clk_init_data){
418 .name = "cam_cc_ife_0_csid_clk_src",
419 .parent_names = cam_cc_parent_names_0,
420 .num_parents = 6,
421 .ops = &clk_rcg2_shared_ops,
422 },
423};
424
425static struct clk_rcg2 cam_cc_ife_1_clk_src = {
426 .cmd_rcgr = 0xa00c,
427 .mnd_width = 0,
428 .hid_width = 5,
429 .parent_map = cam_cc_parent_map_0,
430 .freq_tbl = ftbl_cam_cc_ife_0_clk_src,
431 .clkr.hw.init = &(struct clk_init_data){
432 .name = "cam_cc_ife_1_clk_src",
433 .parent_names = cam_cc_parent_names_0,
434 .num_parents = 6,
435 .flags = CLK_SET_RATE_PARENT,
436 .ops = &clk_rcg2_shared_ops,
437 },
438};
439
440static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
441 .cmd_rcgr = 0xa030,
442 .mnd_width = 0,
443 .hid_width = 5,
444 .parent_map = cam_cc_parent_map_0,
445 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
446 .clkr.hw.init = &(struct clk_init_data){
447 .name = "cam_cc_ife_1_csid_clk_src",
448 .parent_names = cam_cc_parent_names_0,
449 .num_parents = 6,
450 .ops = &clk_rcg2_shared_ops,
451 },
452};
453
454static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
455 .cmd_rcgr = 0xb004,
456 .mnd_width = 0,
457 .hid_width = 5,
458 .parent_map = cam_cc_parent_map_0,
459 .freq_tbl = ftbl_cam_cc_ife_0_clk_src,
460 .clkr.hw.init = &(struct clk_init_data){
461 .name = "cam_cc_ife_lite_clk_src",
462 .parent_names = cam_cc_parent_names_0,
463 .num_parents = 6,
464 .flags = CLK_SET_RATE_PARENT,
465 .ops = &clk_rcg2_shared_ops,
466 },
467};
468
469static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
470 .cmd_rcgr = 0xb024,
471 .mnd_width = 0,
472 .hid_width = 5,
473 .parent_map = cam_cc_parent_map_0,
474 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
475 .clkr.hw.init = &(struct clk_init_data){
476 .name = "cam_cc_ife_lite_csid_clk_src",
477 .parent_names = cam_cc_parent_names_0,
478 .num_parents = 6,
479 .ops = &clk_rcg2_shared_ops,
480 },
481};
482
483static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = {
484 F(19200000, P_BI_TCXO, 1, 0, 0),
485 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
486 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
487 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
488 F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
489 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),
490 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
491 { }
492};
493
494static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
495 .cmd_rcgr = 0x700c,
496 .mnd_width = 0,
497 .hid_width = 5,
498 .parent_map = cam_cc_parent_map_0,
499 .freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
500 .clkr.hw.init = &(struct clk_init_data){
501 .name = "cam_cc_ipe_0_clk_src",
502 .parent_names = cam_cc_parent_names_0,
503 .num_parents = 6,
504 .flags = CLK_SET_RATE_PARENT,
505 .ops = &clk_rcg2_shared_ops,
506 },
507};
508
509static struct clk_rcg2 cam_cc_ipe_1_clk_src = {
510 .cmd_rcgr = 0x800c,
511 .mnd_width = 0,
512 .hid_width = 5,
513 .parent_map = cam_cc_parent_map_0,
514 .freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
515 .clkr.hw.init = &(struct clk_init_data){
516 .name = "cam_cc_ipe_1_clk_src",
517 .parent_names = cam_cc_parent_names_0,
518 .num_parents = 6,
519 .flags = CLK_SET_RATE_PARENT,
520 .ops = &clk_rcg2_shared_ops,
521 },
522};
523
524static struct clk_rcg2 cam_cc_jpeg_clk_src = {
525 .cmd_rcgr = 0xb04c,
526 .mnd_width = 0,
527 .hid_width = 5,
528 .parent_map = cam_cc_parent_map_0,
529 .freq_tbl = ftbl_cam_cc_bps_clk_src,
530 .clkr.hw.init = &(struct clk_init_data){
531 .name = "cam_cc_jpeg_clk_src",
532 .parent_names = cam_cc_parent_names_0,
533 .num_parents = 6,
534 .flags = CLK_SET_RATE_PARENT,
535 .ops = &clk_rcg2_shared_ops,
536 },
537};
538
539static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = {
540 F(19200000, P_BI_TCXO, 1, 0, 0),
541 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
542 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
543 F(269333333, P_CAM_CC_PLL1_OUT_EVEN, 3, 0, 0),
544 F(320000000, P_CAM_CC_PLL2_OUT_EVEN, 1.5, 0, 0),
545 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
546 { }
547};
548
549static struct clk_rcg2 cam_cc_lrme_clk_src = {
550 .cmd_rcgr = 0xb0f8,
551 .mnd_width = 0,
552 .hid_width = 5,
553 .parent_map = cam_cc_parent_map_0,
554 .freq_tbl = ftbl_cam_cc_lrme_clk_src,
555 .clkr.hw.init = &(struct clk_init_data){
556 .name = "cam_cc_lrme_clk_src",
557 .parent_names = cam_cc_parent_names_0,
558 .num_parents = 6,
559 .flags = CLK_SET_RATE_PARENT,
560 .ops = &clk_rcg2_shared_ops,
561 },
562};
563
564static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
565 F(19200000, P_BI_TCXO, 1, 0, 0),
566 F(24000000, P_CAM_CC_PLL2_OUT_EVEN, 10, 1, 2),
567 F(33333333, P_CAM_CC_PLL0_OUT_EVEN, 2, 1, 9),
568 F(34285714, P_CAM_CC_PLL2_OUT_EVEN, 14, 0, 0),
569 { }
570};
571
572static struct clk_rcg2 cam_cc_mclk0_clk_src = {
573 .cmd_rcgr = 0x4004,
574 .mnd_width = 8,
575 .hid_width = 5,
576 .parent_map = cam_cc_parent_map_0,
577 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
578 .clkr.hw.init = &(struct clk_init_data){
579 .name = "cam_cc_mclk0_clk_src",
580 .parent_names = cam_cc_parent_names_0,
581 .num_parents = 6,
582 .flags = CLK_SET_RATE_PARENT,
583 .ops = &clk_rcg2_ops,
584 },
585};
586
587static struct clk_rcg2 cam_cc_mclk1_clk_src = {
588 .cmd_rcgr = 0x4024,
589 .mnd_width = 8,
590 .hid_width = 5,
591 .parent_map = cam_cc_parent_map_0,
592 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
593 .clkr.hw.init = &(struct clk_init_data){
594 .name = "cam_cc_mclk1_clk_src",
595 .parent_names = cam_cc_parent_names_0,
596 .num_parents = 6,
597 .flags = CLK_SET_RATE_PARENT,
598 .ops = &clk_rcg2_ops,
599 },
600};
601
602static struct clk_rcg2 cam_cc_mclk2_clk_src = {
603 .cmd_rcgr = 0x4044,
604 .mnd_width = 8,
605 .hid_width = 5,
606 .parent_map = cam_cc_parent_map_0,
607 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
608 .clkr.hw.init = &(struct clk_init_data){
609 .name = "cam_cc_mclk2_clk_src",
610 .parent_names = cam_cc_parent_names_0,
611 .num_parents = 6,
612 .flags = CLK_SET_RATE_PARENT,
613 .ops = &clk_rcg2_ops,
614 },
615};
616
617static struct clk_rcg2 cam_cc_mclk3_clk_src = {
618 .cmd_rcgr = 0x4064,
619 .mnd_width = 8,
620 .hid_width = 5,
621 .parent_map = cam_cc_parent_map_0,
622 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
623 .clkr.hw.init = &(struct clk_init_data){
624 .name = "cam_cc_mclk3_clk_src",
625 .parent_names = cam_cc_parent_names_0,
626 .num_parents = 6,
627 .flags = CLK_SET_RATE_PARENT,
628 .ops = &clk_rcg2_ops,
629 },
630};
631
632static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
633 F(19200000, P_BI_TCXO, 1, 0, 0),
634 F(60000000, P_CAM_CC_PLL0_OUT_EVEN, 10, 0, 0),
635 F(66666667, P_CAM_CC_PLL0_OUT_EVEN, 9, 0, 0),
636 F(73846154, P_CAM_CC_PLL2_OUT_EVEN, 6.5, 0, 0),
637 F(80000000, P_CAM_CC_PLL2_OUT_EVEN, 6, 0, 0),
638 { }
639};
640
641static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
642 .cmd_rcgr = 0x6054,
643 .mnd_width = 0,
644 .hid_width = 5,
645 .parent_map = cam_cc_parent_map_0,
646 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
647 .clkr.hw.init = &(struct clk_init_data){
648 .name = "cam_cc_slow_ahb_clk_src",
649 .parent_names = cam_cc_parent_names_0,
650 .num_parents = 6,
651 .flags = CLK_SET_RATE_PARENT,
652 .ops = &clk_rcg2_ops,
653 },
654};
655
656static struct clk_branch cam_cc_bps_ahb_clk = {
657 .halt_reg = 0x606c,
658 .halt_check = BRANCH_HALT,
659 .clkr = {
660 .enable_reg = 0x606c,
661 .enable_mask = BIT(0),
662 .hw.init = &(struct clk_init_data){
663 .name = "cam_cc_bps_ahb_clk",
664 .parent_names = (const char *[]){
665 "cam_cc_slow_ahb_clk_src",
666 },
667 .num_parents = 1,
668 .flags = CLK_SET_RATE_PARENT,
669 .ops = &clk_branch2_ops,
670 },
671 },
672};
673
674static struct clk_branch cam_cc_bps_areg_clk = {
675 .halt_reg = 0x6050,
676 .halt_check = BRANCH_HALT,
677 .clkr = {
678 .enable_reg = 0x6050,
679 .enable_mask = BIT(0),
680 .hw.init = &(struct clk_init_data){
681 .name = "cam_cc_bps_areg_clk",
682 .parent_names = (const char *[]){
683 "cam_cc_fast_ahb_clk_src",
684 },
685 .num_parents = 1,
686 .flags = CLK_SET_RATE_PARENT,
687 .ops = &clk_branch2_ops,
688 },
689 },
690};
691
692static struct clk_branch cam_cc_bps_axi_clk = {
693 .halt_reg = 0x6034,
694 .halt_check = BRANCH_HALT,
695 .clkr = {
696 .enable_reg = 0x6034,
697 .enable_mask = BIT(0),
698 .hw.init = &(struct clk_init_data){
699 .name = "cam_cc_bps_axi_clk",
700 .ops = &clk_branch2_ops,
701 },
702 },
703};
704
705static struct clk_branch cam_cc_bps_clk = {
706 .halt_reg = 0x6024,
707 .halt_check = BRANCH_HALT,
708 .clkr = {
709 .enable_reg = 0x6024,
710 .enable_mask = BIT(0),
711 .hw.init = &(struct clk_init_data){
712 .name = "cam_cc_bps_clk",
713 .parent_names = (const char *[]){
714 "cam_cc_bps_clk_src",
715 },
716 .num_parents = 1,
717 .flags = CLK_SET_RATE_PARENT,
718 .ops = &clk_branch2_ops,
719 },
720 },
721};
722
723static struct clk_branch cam_cc_camnoc_atb_clk = {
724 .halt_reg = 0xb12c,
725 .halt_check = BRANCH_HALT,
726 .clkr = {
727 .enable_reg = 0xb12c,
728 .enable_mask = BIT(0),
729 .hw.init = &(struct clk_init_data){
730 .name = "cam_cc_camnoc_atb_clk",
731 .ops = &clk_branch2_ops,
732 },
733 },
734};
735
736static struct clk_branch cam_cc_camnoc_axi_clk = {
737 .halt_reg = 0xb124,
738 .halt_check = BRANCH_HALT,
739 .clkr = {
740 .enable_reg = 0xb124,
741 .enable_mask = BIT(0),
742 .hw.init = &(struct clk_init_data){
743 .name = "cam_cc_camnoc_axi_clk",
744 .ops = &clk_branch2_ops,
745 },
746 },
747};
748
749static struct clk_branch cam_cc_cci_clk = {
750 .halt_reg = 0xb0f0,
751 .halt_check = BRANCH_HALT,
752 .clkr = {
753 .enable_reg = 0xb0f0,
754 .enable_mask = BIT(0),
755 .hw.init = &(struct clk_init_data){
756 .name = "cam_cc_cci_clk",
757 .parent_names = (const char *[]){
758 "cam_cc_cci_clk_src",
759 },
760 .num_parents = 1,
761 .flags = CLK_SET_RATE_PARENT,
762 .ops = &clk_branch2_ops,
763 },
764 },
765};
766
767static struct clk_branch cam_cc_cpas_ahb_clk = {
768 .halt_reg = 0xb11c,
769 .halt_check = BRANCH_HALT,
770 .clkr = {
771 .enable_reg = 0xb11c,
772 .enable_mask = BIT(0),
773 .hw.init = &(struct clk_init_data){
774 .name = "cam_cc_cpas_ahb_clk",
775 .parent_names = (const char *[]){
776 "cam_cc_slow_ahb_clk_src",
777 },
778 .num_parents = 1,
779 .flags = CLK_SET_RATE_PARENT,
780 .ops = &clk_branch2_ops,
781 },
782 },
783};
784
785static struct clk_branch cam_cc_csi0phytimer_clk = {
786 .halt_reg = 0x501c,
787 .halt_check = BRANCH_HALT,
788 .clkr = {
789 .enable_reg = 0x501c,
790 .enable_mask = BIT(0),
791 .hw.init = &(struct clk_init_data){
792 .name = "cam_cc_csi0phytimer_clk",
793 .parent_names = (const char *[]){
794 "cam_cc_csi0phytimer_clk_src",
795 },
796 .num_parents = 1,
797 .flags = CLK_SET_RATE_PARENT,
798 .ops = &clk_branch2_ops,
799 },
800 },
801};
802
803static struct clk_branch cam_cc_csi1phytimer_clk = {
804 .halt_reg = 0x5040,
805 .halt_check = BRANCH_HALT,
806 .clkr = {
807 .enable_reg = 0x5040,
808 .enable_mask = BIT(0),
809 .hw.init = &(struct clk_init_data){
810 .name = "cam_cc_csi1phytimer_clk",
811 .parent_names = (const char *[]){
812 "cam_cc_csi1phytimer_clk_src",
813 },
814 .num_parents = 1,
815 .flags = CLK_SET_RATE_PARENT,
816 .ops = &clk_branch2_ops,
817 },
818 },
819};
820
821static struct clk_branch cam_cc_csi2phytimer_clk = {
822 .halt_reg = 0x5064,
823 .halt_check = BRANCH_HALT,
824 .clkr = {
825 .enable_reg = 0x5064,
826 .enable_mask = BIT(0),
827 .hw.init = &(struct clk_init_data){
828 .name = "cam_cc_csi2phytimer_clk",
829 .parent_names = (const char *[]){
830 "cam_cc_csi2phytimer_clk_src",
831 },
832 .num_parents = 1,
833 .flags = CLK_SET_RATE_PARENT,
834 .ops = &clk_branch2_ops,
835 },
836 },
837};
838
839static struct clk_branch cam_cc_csi3phytimer_clk = {
840 .halt_reg = 0x5088,
841 .halt_check = BRANCH_HALT,
842 .clkr = {
843 .enable_reg = 0x5088,
844 .enable_mask = BIT(0),
845 .hw.init = &(struct clk_init_data){
846 .name = "cam_cc_csi3phytimer_clk",
847 .parent_names = (const char *[]){
848 "cam_cc_csi3phytimer_clk_src",
849 },
850 .num_parents = 1,
851 .flags = CLK_SET_RATE_PARENT,
852 .ops = &clk_branch2_ops,
853 },
854 },
855};
856
857static struct clk_branch cam_cc_csiphy0_clk = {
858 .halt_reg = 0x5020,
859 .halt_check = BRANCH_HALT,
860 .clkr = {
861 .enable_reg = 0x5020,
862 .enable_mask = BIT(0),
863 .hw.init = &(struct clk_init_data){
864 .name = "cam_cc_csiphy0_clk",
865 .parent_names = (const char *[]){
866 "cam_cc_cphy_rx_clk_src",
867 },
868 .num_parents = 1,
869 .flags = CLK_SET_RATE_PARENT,
870 .ops = &clk_branch2_ops,
871 },
872 },
873};
874
875static struct clk_branch cam_cc_csiphy1_clk = {
876 .halt_reg = 0x5044,
877 .halt_check = BRANCH_HALT,
878 .clkr = {
879 .enable_reg = 0x5044,
880 .enable_mask = BIT(0),
881 .hw.init = &(struct clk_init_data){
882 .name = "cam_cc_csiphy1_clk",
883 .parent_names = (const char *[]){
884 "cam_cc_cphy_rx_clk_src",
885 },
886 .num_parents = 1,
887 .flags = CLK_SET_RATE_PARENT,
888 .ops = &clk_branch2_ops,
889 },
890 },
891};
892
893static struct clk_branch cam_cc_csiphy2_clk = {
894 .halt_reg = 0x5068,
895 .halt_check = BRANCH_HALT,
896 .clkr = {
897 .enable_reg = 0x5068,
898 .enable_mask = BIT(0),
899 .hw.init = &(struct clk_init_data){
900 .name = "cam_cc_csiphy2_clk",
901 .parent_names = (const char *[]){
902 "cam_cc_cphy_rx_clk_src",
903 },
904 .num_parents = 1,
905 .flags = CLK_SET_RATE_PARENT,
906 .ops = &clk_branch2_ops,
907 },
908 },
909};
910
911static struct clk_branch cam_cc_csiphy3_clk = {
912 .halt_reg = 0x508c,
913 .halt_check = BRANCH_HALT,
914 .clkr = {
915 .enable_reg = 0x508c,
916 .enable_mask = BIT(0),
917 .hw.init = &(struct clk_init_data){
918 .name = "cam_cc_csiphy3_clk",
919 .parent_names = (const char *[]){
920 "cam_cc_cphy_rx_clk_src",
921 },
922 .num_parents = 1,
923 .flags = CLK_SET_RATE_PARENT,
924 .ops = &clk_branch2_ops,
925 },
926 },
927};
928
929static struct clk_branch cam_cc_fd_core_clk = {
930 .halt_reg = 0xb0c8,
931 .halt_check = BRANCH_HALT,
932 .clkr = {
933 .enable_reg = 0xb0c8,
934 .enable_mask = BIT(0),
935 .hw.init = &(struct clk_init_data){
936 .name = "cam_cc_fd_core_clk",
937 .parent_names = (const char *[]){
938 "cam_cc_fd_core_clk_src",
939 },
940 .num_parents = 1,
941 .flags = CLK_SET_RATE_PARENT,
942 .ops = &clk_branch2_ops,
943 },
944 },
945};
946
947static struct clk_branch cam_cc_fd_core_uar_clk = {
948 .halt_reg = 0xb0d0,
949 .halt_check = BRANCH_HALT,
950 .clkr = {
951 .enable_reg = 0xb0d0,
952 .enable_mask = BIT(0),
953 .hw.init = &(struct clk_init_data){
954 .name = "cam_cc_fd_core_uar_clk",
955 .parent_names = (const char *[]){
956 "cam_cc_fd_core_clk_src",
957 },
958 .num_parents = 1,
959 .ops = &clk_branch2_ops,
960 },
961 },
962};
963
964static struct clk_branch cam_cc_icp_apb_clk = {
965 .halt_reg = 0xb084,
966 .halt_check = BRANCH_HALT,
967 .clkr = {
968 .enable_reg = 0xb084,
969 .enable_mask = BIT(0),
970 .hw.init = &(struct clk_init_data){
971 .name = "cam_cc_icp_apb_clk",
972 .ops = &clk_branch2_ops,
973 },
974 },
975};
976
977static struct clk_branch cam_cc_icp_atb_clk = {
978 .halt_reg = 0xb078,
979 .halt_check = BRANCH_HALT,
980 .clkr = {
981 .enable_reg = 0xb078,
982 .enable_mask = BIT(0),
983 .hw.init = &(struct clk_init_data){
984 .name = "cam_cc_icp_atb_clk",
985 .ops = &clk_branch2_ops,
986 },
987 },
988};
989
990static struct clk_branch cam_cc_icp_clk = {
991 .halt_reg = 0xb0a0,
992 .halt_check = BRANCH_HALT,
993 .clkr = {
994 .enable_reg = 0xb0a0,
995 .enable_mask = BIT(0),
996 .hw.init = &(struct clk_init_data){
997 .name = "cam_cc_icp_clk",
998 .parent_names = (const char *[]){
999 "cam_cc_icp_clk_src",
1000 },
1001 .num_parents = 1,
1002 .flags = CLK_SET_RATE_PARENT,
1003 .ops = &clk_branch2_ops,
1004 },
1005 },
1006};
1007
1008static struct clk_branch cam_cc_icp_cti_clk = {
1009 .halt_reg = 0xb07c,
1010 .halt_check = BRANCH_HALT,
1011 .clkr = {
1012 .enable_reg = 0xb07c,
1013 .enable_mask = BIT(0),
1014 .hw.init = &(struct clk_init_data){
1015 .name = "cam_cc_icp_cti_clk",
1016 .ops = &clk_branch2_ops,
1017 },
1018 },
1019};
1020
1021static struct clk_branch cam_cc_icp_ts_clk = {
1022 .halt_reg = 0xb080,
1023 .halt_check = BRANCH_HALT,
1024 .clkr = {
1025 .enable_reg = 0xb080,
1026 .enable_mask = BIT(0),
1027 .hw.init = &(struct clk_init_data){
1028 .name = "cam_cc_icp_ts_clk",
1029 .ops = &clk_branch2_ops,
1030 },
1031 },
1032};
1033
1034static struct clk_branch cam_cc_ife_0_axi_clk = {
1035 .halt_reg = 0x907c,
1036 .halt_check = BRANCH_HALT,
1037 .clkr = {
1038 .enable_reg = 0x907c,
1039 .enable_mask = BIT(0),
1040 .hw.init = &(struct clk_init_data){
1041 .name = "cam_cc_ife_0_axi_clk",
1042 .ops = &clk_branch2_ops,
1043 },
1044 },
1045};
1046
1047static struct clk_branch cam_cc_ife_0_clk = {
1048 .halt_reg = 0x9024,
1049 .halt_check = BRANCH_HALT,
1050 .clkr = {
1051 .enable_reg = 0x9024,
1052 .enable_mask = BIT(0),
1053 .hw.init = &(struct clk_init_data){
1054 .name = "cam_cc_ife_0_clk",
1055 .parent_names = (const char *[]){
1056 "cam_cc_ife_0_clk_src",
1057 },
1058 .num_parents = 1,
1059 .flags = CLK_SET_RATE_PARENT,
1060 .ops = &clk_branch2_ops,
1061 },
1062 },
1063};
1064
1065static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
1066 .halt_reg = 0x9078,
1067 .halt_check = BRANCH_HALT,
1068 .clkr = {
1069 .enable_reg = 0x9078,
1070 .enable_mask = BIT(0),
1071 .hw.init = &(struct clk_init_data){
1072 .name = "cam_cc_ife_0_cphy_rx_clk",
1073 .parent_names = (const char *[]){
1074 "cam_cc_cphy_rx_clk_src",
1075 },
1076 .num_parents = 1,
1077 .flags = CLK_SET_RATE_PARENT,
1078 .ops = &clk_branch2_ops,
1079 },
1080 },
1081};
1082
1083static struct clk_branch cam_cc_ife_0_csid_clk = {
1084 .halt_reg = 0x9050,
1085 .halt_check = BRANCH_HALT,
1086 .clkr = {
1087 .enable_reg = 0x9050,
1088 .enable_mask = BIT(0),
1089 .hw.init = &(struct clk_init_data){
1090 .name = "cam_cc_ife_0_csid_clk",
1091 .parent_names = (const char *[]){
1092 "cam_cc_ife_0_csid_clk_src",
1093 },
1094 .num_parents = 1,
1095 .flags = CLK_SET_RATE_PARENT,
1096 .ops = &clk_branch2_ops,
1097 },
1098 },
1099};
1100
1101static struct clk_branch cam_cc_ife_0_dsp_clk = {
1102 .halt_reg = 0x9034,
1103 .halt_check = BRANCH_HALT,
1104 .clkr = {
1105 .enable_reg = 0x9034,
1106 .enable_mask = BIT(0),
1107 .hw.init = &(struct clk_init_data){
1108 .name = "cam_cc_ife_0_dsp_clk",
1109 .parent_names = (const char *[]){
1110 "cam_cc_ife_0_clk_src",
1111 },
1112 .num_parents = 1,
1113 .ops = &clk_branch2_ops,
1114 },
1115 },
1116};
1117
1118static struct clk_branch cam_cc_ife_1_axi_clk = {
1119 .halt_reg = 0xa054,
1120 .halt_check = BRANCH_HALT,
1121 .clkr = {
1122 .enable_reg = 0xa054,
1123 .enable_mask = BIT(0),
1124 .hw.init = &(struct clk_init_data){
1125 .name = "cam_cc_ife_1_axi_clk",
1126 .ops = &clk_branch2_ops,
1127 },
1128 },
1129};
1130
1131static struct clk_branch cam_cc_ife_1_clk = {
1132 .halt_reg = 0xa024,
1133 .halt_check = BRANCH_HALT,
1134 .clkr = {
1135 .enable_reg = 0xa024,
1136 .enable_mask = BIT(0),
1137 .hw.init = &(struct clk_init_data){
1138 .name = "cam_cc_ife_1_clk",
1139 .parent_names = (const char *[]){
1140 "cam_cc_ife_1_clk_src",
1141 },
1142 .num_parents = 1,
1143 .flags = CLK_SET_RATE_PARENT,
1144 .ops = &clk_branch2_ops,
1145 },
1146 },
1147};
1148
1149static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
1150 .halt_reg = 0xa050,
1151 .halt_check = BRANCH_HALT,
1152 .clkr = {
1153 .enable_reg = 0xa050,
1154 .enable_mask = BIT(0),
1155 .hw.init = &(struct clk_init_data){
1156 .name = "cam_cc_ife_1_cphy_rx_clk",
1157 .parent_names = (const char *[]){
1158 "cam_cc_cphy_rx_clk_src",
1159 },
1160 .num_parents = 1,
1161 .flags = CLK_SET_RATE_PARENT,
1162 .ops = &clk_branch2_ops,
1163 },
1164 },
1165};
1166
1167static struct clk_branch cam_cc_ife_1_csid_clk = {
1168 .halt_reg = 0xa048,
1169 .halt_check = BRANCH_HALT,
1170 .clkr = {
1171 .enable_reg = 0xa048,
1172 .enable_mask = BIT(0),
1173 .hw.init = &(struct clk_init_data){
1174 .name = "cam_cc_ife_1_csid_clk",
1175 .parent_names = (const char *[]){
1176 "cam_cc_ife_1_csid_clk_src",
1177 },
1178 .num_parents = 1,
1179 .flags = CLK_SET_RATE_PARENT,
1180 .ops = &clk_branch2_ops,
1181 },
1182 },
1183};
1184
1185static struct clk_branch cam_cc_ife_1_dsp_clk = {
1186 .halt_reg = 0xa02c,
1187 .halt_check = BRANCH_HALT,
1188 .clkr = {
1189 .enable_reg = 0xa02c,
1190 .enable_mask = BIT(0),
1191 .hw.init = &(struct clk_init_data){
1192 .name = "cam_cc_ife_1_dsp_clk",
1193 .parent_names = (const char *[]){
1194 "cam_cc_ife_1_clk_src",
1195 },
1196 .num_parents = 1,
1197 .ops = &clk_branch2_ops,
1198 },
1199 },
1200};
1201
1202static struct clk_branch cam_cc_ife_lite_clk = {
1203 .halt_reg = 0xb01c,
1204 .halt_check = BRANCH_HALT,
1205 .clkr = {
1206 .enable_reg = 0xb01c,
1207 .enable_mask = BIT(0),
1208 .hw.init = &(struct clk_init_data){
1209 .name = "cam_cc_ife_lite_clk",
1210 .parent_names = (const char *[]){
1211 "cam_cc_ife_lite_clk_src",
1212 },
1213 .num_parents = 1,
1214 .flags = CLK_SET_RATE_PARENT,
1215 .ops = &clk_branch2_ops,
1216 },
1217 },
1218};
1219
1220static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
1221 .halt_reg = 0xb044,
1222 .halt_check = BRANCH_HALT,
1223 .clkr = {
1224 .enable_reg = 0xb044,
1225 .enable_mask = BIT(0),
1226 .hw.init = &(struct clk_init_data){
1227 .name = "cam_cc_ife_lite_cphy_rx_clk",
1228 .parent_names = (const char *[]){
1229 "cam_cc_cphy_rx_clk_src",
1230 },
1231 .num_parents = 1,
1232 .flags = CLK_SET_RATE_PARENT,
1233 .ops = &clk_branch2_ops,
1234 },
1235 },
1236};
1237
1238static struct clk_branch cam_cc_ife_lite_csid_clk = {
1239 .halt_reg = 0xb03c,
1240 .halt_check = BRANCH_HALT,
1241 .clkr = {
1242 .enable_reg = 0xb03c,
1243 .enable_mask = BIT(0),
1244 .hw.init = &(struct clk_init_data){
1245 .name = "cam_cc_ife_lite_csid_clk",
1246 .parent_names = (const char *[]){
1247 "cam_cc_ife_lite_csid_clk_src",
1248 },
1249 .num_parents = 1,
1250 .flags = CLK_SET_RATE_PARENT,
1251 .ops = &clk_branch2_ops,
1252 },
1253 },
1254};
1255
1256static struct clk_branch cam_cc_ipe_0_ahb_clk = {
1257 .halt_reg = 0x703c,
1258 .halt_check = BRANCH_HALT,
1259 .clkr = {
1260 .enable_reg = 0x703c,
1261 .enable_mask = BIT(0),
1262 .hw.init = &(struct clk_init_data){
1263 .name = "cam_cc_ipe_0_ahb_clk",
1264 .parent_names = (const char *[]){
1265 "cam_cc_slow_ahb_clk_src",
1266 },
1267 .num_parents = 1,
1268 .flags = CLK_SET_RATE_PARENT,
1269 .ops = &clk_branch2_ops,
1270 },
1271 },
1272};
1273
1274static struct clk_branch cam_cc_ipe_0_areg_clk = {
1275 .halt_reg = 0x7038,
1276 .halt_check = BRANCH_HALT,
1277 .clkr = {
1278 .enable_reg = 0x7038,
1279 .enable_mask = BIT(0),
1280 .hw.init = &(struct clk_init_data){
1281 .name = "cam_cc_ipe_0_areg_clk",
1282 .parent_names = (const char *[]){
1283 "cam_cc_fast_ahb_clk_src",
1284 },
1285 .num_parents = 1,
1286 .flags = CLK_SET_RATE_PARENT,
1287 .ops = &clk_branch2_ops,
1288 },
1289 },
1290};
1291
1292static struct clk_branch cam_cc_ipe_0_axi_clk = {
1293 .halt_reg = 0x7034,
1294 .halt_check = BRANCH_HALT,
1295 .clkr = {
1296 .enable_reg = 0x7034,
1297 .enable_mask = BIT(0),
1298 .hw.init = &(struct clk_init_data){
1299 .name = "cam_cc_ipe_0_axi_clk",
1300 .ops = &clk_branch2_ops,
1301 },
1302 },
1303};
1304
1305static struct clk_branch cam_cc_ipe_0_clk = {
1306 .halt_reg = 0x7024,
1307 .halt_check = BRANCH_HALT,
1308 .clkr = {
1309 .enable_reg = 0x7024,
1310 .enable_mask = BIT(0),
1311 .hw.init = &(struct clk_init_data){
1312 .name = "cam_cc_ipe_0_clk",
1313 .parent_names = (const char *[]){
1314 "cam_cc_ipe_0_clk_src",
1315 },
1316 .num_parents = 1,
1317 .flags = CLK_SET_RATE_PARENT,
1318 .ops = &clk_branch2_ops,
1319 },
1320 },
1321};
1322
1323static struct clk_branch cam_cc_ipe_1_ahb_clk = {
1324 .halt_reg = 0x803c,
1325 .halt_check = BRANCH_HALT,
1326 .clkr = {
1327 .enable_reg = 0x803c,
1328 .enable_mask = BIT(0),
1329 .hw.init = &(struct clk_init_data){
1330 .name = "cam_cc_ipe_1_ahb_clk",
1331 .parent_names = (const char *[]){
1332 "cam_cc_slow_ahb_clk_src",
1333 },
1334 .num_parents = 1,
1335 .flags = CLK_SET_RATE_PARENT,
1336 .ops = &clk_branch2_ops,
1337 },
1338 },
1339};
1340
1341static struct clk_branch cam_cc_ipe_1_areg_clk = {
1342 .halt_reg = 0x8038,
1343 .halt_check = BRANCH_HALT,
1344 .clkr = {
1345 .enable_reg = 0x8038,
1346 .enable_mask = BIT(0),
1347 .hw.init = &(struct clk_init_data){
1348 .name = "cam_cc_ipe_1_areg_clk",
1349 .parent_names = (const char *[]){
1350 "cam_cc_fast_ahb_clk_src",
1351 },
1352 .num_parents = 1,
1353 .flags = CLK_SET_RATE_PARENT,
1354 .ops = &clk_branch2_ops,
1355 },
1356 },
1357};
1358
1359static struct clk_branch cam_cc_ipe_1_axi_clk = {
1360 .halt_reg = 0x8034,
1361 .halt_check = BRANCH_HALT,
1362 .clkr = {
1363 .enable_reg = 0x8034,
1364 .enable_mask = BIT(0),
1365 .hw.init = &(struct clk_init_data){
1366 .name = "cam_cc_ipe_1_axi_clk",
1367 .ops = &clk_branch2_ops,
1368 },
1369 },
1370};
1371
1372static struct clk_branch cam_cc_ipe_1_clk = {
1373 .halt_reg = 0x8024,
1374 .halt_check = BRANCH_HALT,
1375 .clkr = {
1376 .enable_reg = 0x8024,
1377 .enable_mask = BIT(0),
1378 .hw.init = &(struct clk_init_data){
1379 .name = "cam_cc_ipe_1_clk",
1380 .parent_names = (const char *[]){
1381 "cam_cc_ipe_1_clk_src",
1382 },
1383 .num_parents = 1,
1384 .flags = CLK_SET_RATE_PARENT,
1385 .ops = &clk_branch2_ops,
1386 },
1387 },
1388};
1389
1390static struct clk_branch cam_cc_jpeg_clk = {
1391 .halt_reg = 0xb064,
1392 .halt_check = BRANCH_HALT,
1393 .clkr = {
1394 .enable_reg = 0xb064,
1395 .enable_mask = BIT(0),
1396 .hw.init = &(struct clk_init_data){
1397 .name = "cam_cc_jpeg_clk",
1398 .parent_names = (const char *[]){
1399 "cam_cc_jpeg_clk_src",
1400 },
1401 .num_parents = 1,
1402 .flags = CLK_SET_RATE_PARENT,
1403 .ops = &clk_branch2_ops,
1404 },
1405 },
1406};
1407
1408static struct clk_branch cam_cc_lrme_clk = {
1409 .halt_reg = 0xb110,
1410 .halt_check = BRANCH_HALT,
1411 .clkr = {
1412 .enable_reg = 0xb110,
1413 .enable_mask = BIT(0),
1414 .hw.init = &(struct clk_init_data){
1415 .name = "cam_cc_lrme_clk",
1416 .parent_names = (const char *[]){
1417 "cam_cc_lrme_clk_src",
1418 },
1419 .num_parents = 1,
1420 .flags = CLK_SET_RATE_PARENT,
1421 .ops = &clk_branch2_ops,
1422 },
1423 },
1424};
1425
1426static struct clk_branch cam_cc_mclk0_clk = {
1427 .halt_reg = 0x401c,
1428 .halt_check = BRANCH_HALT,
1429 .clkr = {
1430 .enable_reg = 0x401c,
1431 .enable_mask = BIT(0),
1432 .hw.init = &(struct clk_init_data){
1433 .name = "cam_cc_mclk0_clk",
1434 .parent_names = (const char *[]){
1435 "cam_cc_mclk0_clk_src",
1436 },
1437 .num_parents = 1,
1438 .flags = CLK_SET_RATE_PARENT,
1439 .ops = &clk_branch2_ops,
1440 },
1441 },
1442};
1443
1444static struct clk_branch cam_cc_mclk1_clk = {
1445 .halt_reg = 0x403c,
1446 .halt_check = BRANCH_HALT,
1447 .clkr = {
1448 .enable_reg = 0x403c,
1449 .enable_mask = BIT(0),
1450 .hw.init = &(struct clk_init_data){
1451 .name = "cam_cc_mclk1_clk",
1452 .parent_names = (const char *[]){
1453 "cam_cc_mclk1_clk_src",
1454 },
1455 .num_parents = 1,
1456 .flags = CLK_SET_RATE_PARENT,
1457 .ops = &clk_branch2_ops,
1458 },
1459 },
1460};
1461
1462static struct clk_branch cam_cc_mclk2_clk = {
1463 .halt_reg = 0x405c,
1464 .halt_check = BRANCH_HALT,
1465 .clkr = {
1466 .enable_reg = 0x405c,
1467 .enable_mask = BIT(0),
1468 .hw.init = &(struct clk_init_data){
1469 .name = "cam_cc_mclk2_clk",
1470 .parent_names = (const char *[]){
1471 "cam_cc_mclk2_clk_src",
1472 },
1473 .num_parents = 1,
1474 .flags = CLK_SET_RATE_PARENT,
1475 .ops = &clk_branch2_ops,
1476 },
1477 },
1478};
1479
1480static struct clk_branch cam_cc_mclk3_clk = {
1481 .halt_reg = 0x407c,
1482 .halt_check = BRANCH_HALT,
1483 .clkr = {
1484 .enable_reg = 0x407c,
1485 .enable_mask = BIT(0),
1486 .hw.init = &(struct clk_init_data){
1487 .name = "cam_cc_mclk3_clk",
1488 .parent_names = (const char *[]){
1489 "cam_cc_mclk3_clk_src",
1490 },
1491 .num_parents = 1,
1492 .flags = CLK_SET_RATE_PARENT,
1493 .ops = &clk_branch2_ops,
1494 },
1495 },
1496};
1497
1498static struct clk_branch cam_cc_soc_ahb_clk = {
1499 .halt_reg = 0xb13c,
1500 .halt_check = BRANCH_HALT,
1501 .clkr = {
1502 .enable_reg = 0xb13c,
1503 .enable_mask = BIT(0),
1504 .hw.init = &(struct clk_init_data){
1505 .name = "cam_cc_soc_ahb_clk",
1506 .ops = &clk_branch2_ops,
1507 },
1508 },
1509};
1510
1511static struct clk_branch cam_cc_sys_tmr_clk = {
1512 .halt_reg = 0xb0a8,
1513 .halt_check = BRANCH_HALT,
1514 .clkr = {
1515 .enable_reg = 0xb0a8,
1516 .enable_mask = BIT(0),
1517 .hw.init = &(struct clk_init_data){
1518 .name = "cam_cc_sys_tmr_clk",
1519 .ops = &clk_branch2_ops,
1520 },
1521 },
1522};
1523
1524static struct gdsc bps_gdsc = {
1525 .gdscr = 0x6004,
1526 .pd = {
1527 .name = "bps_gdsc",
1528 },
1529 .flags = HW_CTRL | POLL_CFG_GDSCR,
1530 .pwrsts = PWRSTS_OFF_ON,
1531};
1532
1533static struct gdsc ipe_0_gdsc = {
1534 .gdscr = 0x7004,
1535 .pd = {
1536 .name = "ipe_0_gdsc",
1537 },
1538 .flags = HW_CTRL | POLL_CFG_GDSCR,
1539 .pwrsts = PWRSTS_OFF_ON,
1540};
1541
1542static struct gdsc ipe_1_gdsc = {
1543 .gdscr = 0x8004,
1544 .pd = {
1545 .name = "ipe_1_gdsc",
1546 },
1547 .flags = HW_CTRL | POLL_CFG_GDSCR,
1548 .pwrsts = PWRSTS_OFF_ON,
1549};
1550
1551static struct gdsc ife_0_gdsc = {
1552 .gdscr = 0x9004,
1553 .pd = {
1554 .name = "ife_0_gdsc",
1555 },
1556 .flags = POLL_CFG_GDSCR,
1557 .pwrsts = PWRSTS_OFF_ON,
1558};
1559
1560static struct gdsc ife_1_gdsc = {
1561 .gdscr = 0xa004,
1562 .pd = {
1563 .name = "ife_1_gdsc",
1564 },
1565 .flags = POLL_CFG_GDSCR,
1566 .pwrsts = PWRSTS_OFF_ON,
1567};
1568
1569static struct gdsc titan_top_gdsc = {
1570 .gdscr = 0xb134,
1571 .pd = {
1572 .name = "titan_top_gdsc",
1573 },
1574 .flags = POLL_CFG_GDSCR,
1575 .pwrsts = PWRSTS_OFF_ON,
1576};
1577
1578static struct clk_regmap *cam_cc_sdm845_clocks[] = {
1579 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
1580 [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr,
1581 [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr,
1582 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
1583 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
1584 [CAM_CC_CAMNOC_ATB_CLK] = &cam_cc_camnoc_atb_clk.clkr,
1585 [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
1586 [CAM_CC_CCI_CLK] = &cam_cc_cci_clk.clkr,
1587 [CAM_CC_CCI_CLK_SRC] = &cam_cc_cci_clk_src.clkr,
1588 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
1589 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
1590 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
1591 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
1592 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
1593 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
1594 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
1595 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
1596 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
1597 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
1598 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
1599 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
1600 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
1601 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
1602 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
1603 [CAM_CC_FD_CORE_CLK] = &cam_cc_fd_core_clk.clkr,
1604 [CAM_CC_FD_CORE_CLK_SRC] = &cam_cc_fd_core_clk_src.clkr,
1605 [CAM_CC_FD_CORE_UAR_CLK] = &cam_cc_fd_core_uar_clk.clkr,
1606 [CAM_CC_ICP_APB_CLK] = &cam_cc_icp_apb_clk.clkr,
1607 [CAM_CC_ICP_ATB_CLK] = &cam_cc_icp_atb_clk.clkr,
1608 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
1609 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
1610 [CAM_CC_ICP_CTI_CLK] = &cam_cc_icp_cti_clk.clkr,
1611 [CAM_CC_ICP_TS_CLK] = &cam_cc_icp_ts_clk.clkr,
1612 [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr,
1613 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
1614 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
1615 [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr,
1616 [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr,
1617 [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr,
1618 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
1619 [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr,
1620 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
1621 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
1622 [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr,
1623 [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr,
1624 [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr,
1625 [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
1626 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
1627 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
1628 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
1629 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
1630 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
1631 [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr,
1632 [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr,
1633 [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr,
1634 [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr,
1635 [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr,
1636 [CAM_CC_IPE_1_AHB_CLK] = &cam_cc_ipe_1_ahb_clk.clkr,
1637 [CAM_CC_IPE_1_AREG_CLK] = &cam_cc_ipe_1_areg_clk.clkr,
1638 [CAM_CC_IPE_1_AXI_CLK] = &cam_cc_ipe_1_axi_clk.clkr,
1639 [CAM_CC_IPE_1_CLK] = &cam_cc_ipe_1_clk.clkr,
1640 [CAM_CC_IPE_1_CLK_SRC] = &cam_cc_ipe_1_clk_src.clkr,
1641 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
1642 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
1643 [CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr,
1644 [CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr,
1645 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
1646 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
1647 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
1648 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
1649 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
1650 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
1651 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
1652 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
1653 [CAM_CC_PLL0] = &cam_cc_pll0.clkr,
1654 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
1655 [CAM_CC_PLL1] = &cam_cc_pll1.clkr,
1656 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
1657 [CAM_CC_PLL2] = &cam_cc_pll2.clkr,
1658 [CAM_CC_PLL2_OUT_EVEN] = &cam_cc_pll2_out_even.clkr,
1659 [CAM_CC_PLL3] = &cam_cc_pll3.clkr,
1660 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
1661 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
1662 [CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr,
1663 [CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr,
1664};
1665
1666static struct gdsc *cam_cc_sdm845_gdscs[] = {
1667 [BPS_GDSC] = &bps_gdsc,
1668 [IPE_0_GDSC] = &ipe_0_gdsc,
1669 [IPE_1_GDSC] = &ipe_1_gdsc,
1670 [IFE_0_GDSC] = &ife_0_gdsc,
1671 [IFE_1_GDSC] = &ife_1_gdsc,
1672 [TITAN_TOP_GDSC] = &titan_top_gdsc,
1673};
1674
1675static const struct regmap_config cam_cc_sdm845_regmap_config = {
1676 .reg_bits = 32,
1677 .reg_stride = 4,
1678 .val_bits = 32,
1679 .max_register = 0xd004,
1680 .fast_io = true,
1681};
1682
1683static const struct qcom_cc_desc cam_cc_sdm845_desc = {
1684 .config = &cam_cc_sdm845_regmap_config,
1685 .clks = cam_cc_sdm845_clocks,
1686 .num_clks = ARRAY_SIZE(cam_cc_sdm845_clocks),
1687 .gdscs = cam_cc_sdm845_gdscs,
1688 .num_gdscs = ARRAY_SIZE(cam_cc_sdm845_gdscs),
1689};
1690
1691static const struct of_device_id cam_cc_sdm845_match_table[] = {
1692 { .compatible = "qcom,sdm845-camcc" },
1693 { }
1694};
1695MODULE_DEVICE_TABLE(of, cam_cc_sdm845_match_table);
1696
1697static int cam_cc_sdm845_probe(struct platform_device *pdev)
1698{
1699 struct regmap *regmap;
1700 struct alpha_pll_config cam_cc_pll_config = { };
1701
1702 regmap = qcom_cc_map(pdev, &cam_cc_sdm845_desc);
1703 if (IS_ERR(regmap))
1704 return PTR_ERR(regmap);
1705
1706 cam_cc_pll_config.l = 0x1f;
1707 cam_cc_pll_config.alpha = 0x4000;
1708 clk_fabia_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll_config);
1709
1710 cam_cc_pll_config.l = 0x2a;
1711 cam_cc_pll_config.alpha = 0x1556;
1712 clk_fabia_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll_config);
1713
1714 cam_cc_pll_config.l = 0x32;
1715 cam_cc_pll_config.alpha = 0x0;
1716 clk_fabia_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll_config);
1717
1718 cam_cc_pll_config.l = 0x14;
1719 clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll_config);
1720
1721 return qcom_cc_really_probe(pdev, &cam_cc_sdm845_desc, regmap);
1722}
1723
1724static struct platform_driver cam_cc_sdm845_driver = {
1725 .probe = cam_cc_sdm845_probe,
1726 .driver = {
1727 .name = "sdm845-camcc",
1728 .of_match_table = cam_cc_sdm845_match_table,
1729 },
1730};
1731
1732static int __init cam_cc_sdm845_init(void)
1733{
1734 return platform_driver_register(&cam_cc_sdm845_driver);
1735}
1736subsys_initcall(cam_cc_sdm845_init);
1737
1738static void __exit cam_cc_sdm845_exit(void)
1739{
1740 platform_driver_unregister(&cam_cc_sdm845_driver);
1741}
1742module_exit(cam_cc_sdm845_exit);
1743
1744MODULE_DESCRIPTION("QTI CAM_CC SDM845 Driver");
1745MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index a91d97cecbad..0ced4a5a9a17 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -220,6 +220,7 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
220 if (pll->flags & SUPPORTS_FSM_MODE) 220 if (pll->flags & SUPPORTS_FSM_MODE)
221 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 221 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
222} 222}
223EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
223 224
224static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) 225static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
225{ 226{
diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c
index bc2205c450b6..99446bf630aa 100644
--- a/drivers/clk/qcom/clk-branch.c
+++ b/drivers/clk/qcom/clk-branch.c
@@ -18,7 +18,7 @@ static bool clk_branch_in_hwcg_mode(const struct clk_branch *br)
18 u32 val; 18 u32 val;
19 19
20 if (!br->hwcg_reg) 20 if (!br->hwcg_reg)
21 return 0; 21 return false;
22 22
23 regmap_read(br->clkr.regmap, br->hwcg_reg, &val); 23 regmap_read(br->clkr.regmap, br->hwcg_reg, &val);
24 24
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index dbd5a9e83554..e5eca8a1abe4 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -163,4 +163,15 @@ extern const struct clk_ops clk_pixel_ops;
163extern const struct clk_ops clk_gfx3d_ops; 163extern const struct clk_ops clk_gfx3d_ops;
164extern const struct clk_ops clk_rcg2_shared_ops; 164extern const struct clk_ops clk_rcg2_shared_ops;
165 165
166struct clk_rcg_dfs_data {
167 struct clk_rcg2 *rcg;
168 struct clk_init_data *init;
169};
170
171#define DEFINE_RCG_DFS(r) \
172 { .rcg = &r##_src, .init = &r##_init }
173
174extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
175 const struct clk_rcg_dfs_data *rcgs,
176 size_t len);
166#endif 177#endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 52208d4165f4..6e3bd195d012 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -12,6 +12,7 @@
12#include <linux/delay.h> 12#include <linux/delay.h>
13#include <linux/regmap.h> 13#include <linux/regmap.h>
14#include <linux/math64.h> 14#include <linux/math64.h>
15#include <linux/slab.h>
15 16
16#include <asm/div64.h> 17#include <asm/div64.h>
17 18
@@ -40,6 +41,14 @@
40#define N_REG 0xc 41#define N_REG 0xc
41#define D_REG 0x10 42#define D_REG 0x10
42 43
44/* Dynamic Frequency Scaling */
45#define MAX_PERF_LEVEL 8
46#define SE_CMD_DFSR_OFFSET 0x14
47#define SE_CMD_DFS_EN BIT(0)
48#define SE_PERF_DFSR(level) (0x1c + 0x4 * (level))
49#define SE_PERF_M_DFSR(level) (0x5c + 0x4 * (level))
50#define SE_PERF_N_DFSR(level) (0x9c + 0x4 * (level))
51
43enum freq_policy { 52enum freq_policy {
44 FLOOR, 53 FLOOR,
45 CEIL, 54 CEIL,
@@ -929,3 +938,189 @@ const struct clk_ops clk_rcg2_shared_ops = {
929 .set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent, 938 .set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,
930}; 939};
931EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops); 940EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
941
942/* Common APIs to be used for DFS based RCGR */
943static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
944 struct freq_tbl *f)
945{
946 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
947 struct clk_hw *p;
948 unsigned long prate = 0;
949 u32 val, mask, cfg, mode;
950 int i, num_parents;
951
952 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg);
953
954 mask = BIT(rcg->hid_width) - 1;
955 f->pre_div = 1;
956 if (cfg & mask)
957 f->pre_div = cfg & mask;
958
959 cfg &= CFG_SRC_SEL_MASK;
960 cfg >>= CFG_SRC_SEL_SHIFT;
961
962 num_parents = clk_hw_get_num_parents(hw);
963 for (i = 0; i < num_parents; i++) {
964 if (cfg == rcg->parent_map[i].cfg) {
965 f->src = rcg->parent_map[i].src;
966 p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i);
967 prate = clk_hw_get_rate(p);
968 }
969 }
970
971 mode = cfg & CFG_MODE_MASK;
972 mode >>= CFG_MODE_SHIFT;
973 if (mode) {
974 mask = BIT(rcg->mnd_width) - 1;
975 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l),
976 &val);
977 val &= mask;
978 f->m = val;
979
980 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_N_DFSR(l),
981 &val);
982 val = ~val;
983 val &= mask;
984 val += f->m;
985 f->n = val;
986 }
987
988 f->freq = calc_rate(prate, f->m, f->n, mode, f->pre_div);
989}
990
991static int clk_rcg2_dfs_populate_freq_table(struct clk_rcg2 *rcg)
992{
993 struct freq_tbl *freq_tbl;
994 int i;
995
996 /* Allocate space for 1 extra since table is NULL terminated */
997 freq_tbl = kcalloc(MAX_PERF_LEVEL + 1, sizeof(*freq_tbl), GFP_KERNEL);
998 if (!freq_tbl)
999 return -ENOMEM;
1000 rcg->freq_tbl = freq_tbl;
1001
1002 for (i = 0; i < MAX_PERF_LEVEL; i++)
1003 clk_rcg2_dfs_populate_freq(&rcg->clkr.hw, i, freq_tbl + i);
1004
1005 return 0;
1006}
1007
1008static int clk_rcg2_dfs_determine_rate(struct clk_hw *hw,
1009 struct clk_rate_request *req)
1010{
1011 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1012 int ret;
1013
1014 if (!rcg->freq_tbl) {
1015 ret = clk_rcg2_dfs_populate_freq_table(rcg);
1016 if (ret) {
1017 pr_err("Failed to update DFS tables for %s\n",
1018 clk_hw_get_name(hw));
1019 return ret;
1020 }
1021 }
1022
1023 return clk_rcg2_determine_rate(hw, req);
1024}
1025
1026static unsigned long
1027clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1028{
1029 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1030 u32 level, mask, cfg, m = 0, n = 0, mode, pre_div;
1031
1032 regmap_read(rcg->clkr.regmap,
1033 rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &level);
1034 level &= GENMASK(4, 1);
1035 level >>= 1;
1036
1037 if (rcg->freq_tbl)
1038 return rcg->freq_tbl[level].freq;
1039
1040 /*
1041 * Assume that parent_rate is actually the parent because
1042 * we can't do any better at figuring it out when the table
1043 * hasn't been populated yet. We only populate the table
1044 * in determine_rate because we can't guarantee the parents
1045 * will be registered with the framework until then.
1046 */
1047 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(level),
1048 &cfg);
1049
1050 mask = BIT(rcg->hid_width) - 1;
1051 pre_div = 1;
1052 if (cfg & mask)
1053 pre_div = cfg & mask;
1054
1055 mode = cfg & CFG_MODE_MASK;
1056 mode >>= CFG_MODE_SHIFT;
1057 if (mode) {
1058 mask = BIT(rcg->mnd_width) - 1;
1059 regmap_read(rcg->clkr.regmap,
1060 rcg->cmd_rcgr + SE_PERF_M_DFSR(level), &m);
1061 m &= mask;
1062
1063 regmap_read(rcg->clkr.regmap,
1064 rcg->cmd_rcgr + SE_PERF_N_DFSR(level), &n);
1065 n = ~n;
1066 n &= mask;
1067 n += m;
1068 }
1069
1070 return calc_rate(parent_rate, m, n, mode, pre_div);
1071}
1072
1073static const struct clk_ops clk_rcg2_dfs_ops = {
1074 .is_enabled = clk_rcg2_is_enabled,
1075 .get_parent = clk_rcg2_get_parent,
1076 .determine_rate = clk_rcg2_dfs_determine_rate,
1077 .recalc_rate = clk_rcg2_dfs_recalc_rate,
1078};
1079
1080static int clk_rcg2_enable_dfs(const struct clk_rcg_dfs_data *data,
1081 struct regmap *regmap)
1082{
1083 struct clk_rcg2 *rcg = data->rcg;
1084 struct clk_init_data *init = data->init;
1085 u32 val;
1086 int ret;
1087
1088 ret = regmap_read(regmap, rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &val);
1089 if (ret)
1090 return -EINVAL;
1091
1092 if (!(val & SE_CMD_DFS_EN))
1093 return 0;
1094
1095 /*
1096 * Rate changes with consumer writing a register in
1097 * their own I/O region
1098 */
1099 init->flags |= CLK_GET_RATE_NOCACHE;
1100 init->ops = &clk_rcg2_dfs_ops;
1101
1102 rcg->freq_tbl = NULL;
1103
1104 pr_debug("DFS registered for clk %s\n", init->name);
1105
1106 return 0;
1107}
1108
1109int qcom_cc_register_rcg_dfs(struct regmap *regmap,
1110 const struct clk_rcg_dfs_data *rcgs, size_t len)
1111{
1112 int i, ret;
1113
1114 for (i = 0; i < len; i++) {
1115 ret = clk_rcg2_enable_dfs(&rcgs[i], regmap);
1116 if (ret) {
1117 const char *name = rcgs[i].init->name;
1118
1119 pr_err("DFS register failed for clk %s\n", name);
1120 return ret;
1121 }
1122 }
1123
1124 return 0;
1125}
1126EXPORT_SYMBOL_GPL(qcom_cc_register_rcg_dfs);
diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index 9a3290fdd01b..9d136172c27c 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -260,6 +260,36 @@ static struct clk_alpha_pll_postdiv gpll0 = {
260 }, 260 },
261}; 261};
262 262
263static struct clk_branch gcc_mmss_gpll0_div_clk = {
264 .halt_check = BRANCH_HALT_DELAY,
265 .clkr = {
266 .enable_reg = 0x5200c,
267 .enable_mask = BIT(0),
268 .hw.init = &(struct clk_init_data){
269 .name = "gcc_mmss_gpll0_div_clk",
270 .parent_names = (const char *[]){ "gpll0" },
271 .num_parents = 1,
272 .flags = CLK_SET_RATE_PARENT,
273 .ops = &clk_branch2_ops,
274 },
275 },
276};
277
278static struct clk_branch gcc_mss_gpll0_div_clk = {
279 .halt_check = BRANCH_HALT_DELAY,
280 .clkr = {
281 .enable_reg = 0x5200c,
282 .enable_mask = BIT(2),
283 .hw.init = &(struct clk_init_data){
284 .name = "gcc_mss_gpll0_div_clk",
285 .parent_names = (const char *[]){ "gpll0" },
286 .num_parents = 1,
287 .flags = CLK_SET_RATE_PARENT,
288 .ops = &clk_branch2_ops
289 },
290 },
291};
292
263static struct clk_alpha_pll gpll4_early = { 293static struct clk_alpha_pll gpll4_early = {
264 .offset = 0x77000, 294 .offset = 0x77000,
265 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 295 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
@@ -2951,6 +2981,20 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
2951 }, 2981 },
2952}; 2982};
2953 2983
2984static struct clk_branch gcc_aggre1_pnoc_ahb_clk = {
2985 .halt_reg = 0x82014,
2986 .clkr = {
2987 .enable_reg = 0x82014,
2988 .enable_mask = BIT(0),
2989 .hw.init = &(struct clk_init_data){
2990 .name = "gcc_aggre1_pnoc_ahb_clk",
2991 .parent_names = (const char *[]){ "periph_noc_clk_src" },
2992 .num_parents = 1,
2993 .ops = &clk_branch2_ops,
2994 },
2995 },
2996};
2997
2954static struct clk_branch gcc_aggre2_ufs_axi_clk = { 2998static struct clk_branch gcc_aggre2_ufs_axi_clk = {
2955 .halt_reg = 0x83014, 2999 .halt_reg = 0x83014,
2956 .clkr = { 3000 .clkr = {
@@ -2981,6 +3025,34 @@ static struct clk_branch gcc_aggre2_usb3_axi_clk = {
2981 }, 3025 },
2982}; 3026};
2983 3027
3028static struct clk_branch gcc_dcc_ahb_clk = {
3029 .halt_reg = 0x84004,
3030 .clkr = {
3031 .enable_reg = 0x84004,
3032 .enable_mask = BIT(0),
3033 .hw.init = &(struct clk_init_data){
3034 .name = "gcc_dcc_ahb_clk",
3035 .parent_names = (const char *[]){ "config_noc_clk_src" },
3036 .num_parents = 1,
3037 .ops = &clk_branch2_ops,
3038 },
3039 },
3040};
3041
3042static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
3043 .halt_reg = 0x85000,
3044 .clkr = {
3045 .enable_reg = 0x85000,
3046 .enable_mask = BIT(0),
3047 .hw.init = &(struct clk_init_data){
3048 .name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
3049 .parent_names = (const char *[]){ "config_noc_clk_src" },
3050 .num_parents = 1,
3051 .ops = &clk_branch2_ops,
3052 },
3053 },
3054};
3055
2984static struct clk_branch gcc_qspi_ahb_clk = { 3056static struct clk_branch gcc_qspi_ahb_clk = {
2985 .halt_reg = 0x8b004, 3057 .halt_reg = 0x8b004,
2986 .clkr = { 3058 .clkr = {
@@ -3039,6 +3111,20 @@ static struct clk_branch gcc_hdmi_clkref_clk = {
3039 }, 3111 },
3040}; 3112};
3041 3113
3114static struct clk_branch gcc_edp_clkref_clk = {
3115 .halt_reg = 0x88004,
3116 .clkr = {
3117 .enable_reg = 0x88004,
3118 .enable_mask = BIT(0),
3119 .hw.init = &(struct clk_init_data){
3120 .name = "gcc_edp_clkref_clk",
3121 .parent_names = (const char *[]){ "xo" },
3122 .num_parents = 1,
3123 .ops = &clk_branch2_ops,
3124 },
3125 },
3126};
3127
3042static struct clk_branch gcc_ufs_clkref_clk = { 3128static struct clk_branch gcc_ufs_clkref_clk = {
3043 .halt_reg = 0x88008, 3129 .halt_reg = 0x88008,
3044 .clkr = { 3130 .clkr = {
@@ -3095,6 +3181,62 @@ static struct clk_branch gcc_rx1_usb2_clkref_clk = {
3095 }, 3181 },
3096}; 3182};
3097 3183
3184static struct clk_branch gcc_mss_cfg_ahb_clk = {
3185 .halt_reg = 0x8a000,
3186 .clkr = {
3187 .enable_reg = 0x8a000,
3188 .enable_mask = BIT(0),
3189 .hw.init = &(struct clk_init_data){
3190 .name = "gcc_mss_cfg_ahb_clk",
3191 .parent_names = (const char *[]){ "config_noc_clk_src" },
3192 .num_parents = 1,
3193 .ops = &clk_branch2_ops,
3194 },
3195 },
3196};
3197
3198static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
3199 .halt_reg = 0x8a004,
3200 .clkr = {
3201 .enable_reg = 0x8a004,
3202 .enable_mask = BIT(0),
3203 .hw.init = &(struct clk_init_data){
3204 .name = "gcc_mss_mnoc_bimc_axi_clk",
3205 .parent_names = (const char *[]){ "system_noc_clk_src" },
3206 .num_parents = 1,
3207 .ops = &clk_branch2_ops,
3208 },
3209 },
3210};
3211
3212static struct clk_branch gcc_mss_snoc_axi_clk = {
3213 .halt_reg = 0x8a024,
3214 .clkr = {
3215 .enable_reg = 0x8a024,
3216 .enable_mask = BIT(0),
3217 .hw.init = &(struct clk_init_data){
3218 .name = "gcc_mss_snoc_axi_clk",
3219 .parent_names = (const char *[]){ "system_noc_clk_src" },
3220 .num_parents = 1,
3221 .ops = &clk_branch2_ops,
3222 },
3223 },
3224};
3225
3226static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
3227 .halt_reg = 0x8a028,
3228 .clkr = {
3229 .enable_reg = 0x8a028,
3230 .enable_mask = BIT(0),
3231 .hw.init = &(struct clk_init_data){
3232 .name = "gcc_mss_q6_bimc_axi_clk",
3233 .parent_names = (const char *[]){ "system_noc_clk_src" },
3234 .num_parents = 1,
3235 .ops = &clk_branch2_ops,
3236 },
3237 },
3238};
3239
3098static struct clk_hw *gcc_msm8996_hws[] = { 3240static struct clk_hw *gcc_msm8996_hws[] = {
3099 &xo.hw, 3241 &xo.hw,
3100 &gpll0_early_div.hw, 3242 &gpll0_early_div.hw,
@@ -3355,6 +3497,7 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
3355 [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr, 3497 [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
3356 [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr, 3498 [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
3357 [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr, 3499 [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
3500 [GCC_AGGRE1_PNOC_AHB_CLK] = &gcc_aggre1_pnoc_ahb_clk.clkr,
3358 [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr, 3501 [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
3359 [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr, 3502 [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
3360 [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr, 3503 [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
@@ -3365,6 +3508,15 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
3365 [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr, 3508 [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
3366 [GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr, 3509 [GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
3367 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr, 3510 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
3511 [GCC_EDP_CLKREF_CLK] = &gcc_edp_clkref_clk.clkr,
3512 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3513 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3514 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3515 [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
3516 [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
3517 [GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK] = &gcc_aggre0_noc_mpu_cfg_ahb_clk.clkr,
3518 [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
3519 [GCC_MSS_GPLL0_DIV_CLK] = &gcc_mss_gpll0_div_clk.clkr,
3368}; 3520};
3369 3521
3370static struct gdsc *gcc_msm8996_gdscs[] = { 3522static struct gdsc *gcc_msm8996_gdscs[] = {
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
new file mode 100644
index 000000000000..e4ca6a45f313
--- /dev/null
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -0,0 +1,2744 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/kernel.h>
7#include <linux/platform_device.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/clk-provider.h>
11#include <linux/regmap.h>
12#include <linux/reset-controller.h>
13
14#include <dt-bindings/clock/qcom,gcc-qcs404.h>
15
16#include "clk-alpha-pll.h"
17#include "clk-branch.h"
18#include "clk-pll.h"
19#include "clk-rcg.h"
20#include "clk-regmap.h"
21#include "common.h"
22#include "reset.h"
23
24enum {
25 P_CORE_BI_PLL_TEST_SE,
26 P_DSI0_PHY_PLL_OUT_BYTECLK,
27 P_DSI0_PHY_PLL_OUT_DSICLK,
28 P_GPLL0_OUT_AUX,
29 P_GPLL0_OUT_MAIN,
30 P_GPLL1_OUT_MAIN,
31 P_GPLL3_OUT_MAIN,
32 P_GPLL4_OUT_AUX,
33 P_GPLL4_OUT_MAIN,
34 P_GPLL6_OUT_AUX,
35 P_HDMI_PHY_PLL_CLK,
36 P_PCIE_0_PIPE_CLK,
37 P_SLEEP_CLK,
38 P_XO,
39};
40
41static const struct parent_map gcc_parent_map_0[] = {
42 { P_XO, 0 },
43 { P_GPLL0_OUT_MAIN, 1 },
44 { P_CORE_BI_PLL_TEST_SE, 7 },
45};
46
47static const char * const gcc_parent_names_0[] = {
48 "cxo",
49 "gpll0_out_main",
50 "core_bi_pll_test_se",
51};
52
53static const char * const gcc_parent_names_ao_0[] = {
54 "cxo",
55 "gpll0_ao_out_main",
56 "core_bi_pll_test_se",
57};
58
59static const struct parent_map gcc_parent_map_1[] = {
60 { P_XO, 0 },
61 { P_CORE_BI_PLL_TEST_SE, 7 },
62};
63
64static const char * const gcc_parent_names_1[] = {
65 "cxo",
66 "core_bi_pll_test_se",
67};
68
69static const struct parent_map gcc_parent_map_2[] = {
70 { P_XO, 0 },
71 { P_GPLL0_OUT_MAIN, 1 },
72 { P_GPLL6_OUT_AUX, 2 },
73 { P_SLEEP_CLK, 6 },
74};
75
76static const char * const gcc_parent_names_2[] = {
77 "cxo",
78 "gpll0_out_main",
79 "gpll6_out_aux",
80 "sleep_clk",
81};
82
83static const struct parent_map gcc_parent_map_3[] = {
84 { P_XO, 0 },
85 { P_GPLL0_OUT_MAIN, 1 },
86 { P_GPLL6_OUT_AUX, 2 },
87 { P_CORE_BI_PLL_TEST_SE, 7 },
88};
89
90static const char * const gcc_parent_names_3[] = {
91 "cxo",
92 "gpll0_out_main",
93 "gpll6_out_aux",
94 "core_bi_pll_test_se",
95};
96
97static const struct parent_map gcc_parent_map_4[] = {
98 { P_XO, 0 },
99 { P_GPLL1_OUT_MAIN, 1 },
100 { P_CORE_BI_PLL_TEST_SE, 7 },
101};
102
103static const char * const gcc_parent_names_4[] = {
104 "cxo",
105 "gpll1_out_main",
106 "core_bi_pll_test_se",
107};
108
109static const struct parent_map gcc_parent_map_5[] = {
110 { P_XO, 0 },
111 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
112 { P_GPLL0_OUT_AUX, 2 },
113 { P_CORE_BI_PLL_TEST_SE, 7 },
114};
115
116static const char * const gcc_parent_names_5[] = {
117 "cxo",
118 "dsi0pll_byteclk_src",
119 "gpll0_out_aux",
120 "core_bi_pll_test_se",
121};
122
123static const struct parent_map gcc_parent_map_6[] = {
124 { P_XO, 0 },
125 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
126 { P_GPLL0_OUT_AUX, 3 },
127 { P_CORE_BI_PLL_TEST_SE, 7 },
128};
129
130static const char * const gcc_parent_names_6[] = {
131 "cxo",
132 "dsi0_phy_pll_out_byteclk",
133 "gpll0_out_aux",
134 "core_bi_pll_test_se",
135};
136
137static const struct parent_map gcc_parent_map_7[] = {
138 { P_XO, 0 },
139 { P_GPLL0_OUT_MAIN, 1 },
140 { P_GPLL3_OUT_MAIN, 2 },
141 { P_GPLL6_OUT_AUX, 3 },
142 { P_GPLL4_OUT_AUX, 4 },
143 { P_CORE_BI_PLL_TEST_SE, 7 },
144};
145
146static const char * const gcc_parent_names_7[] = {
147 "cxo",
148 "gpll0_out_main",
149 "gpll3_out_main",
150 "gpll6_out_aux",
151 "gpll4_out_aux",
152 "core_bi_pll_test_se",
153};
154
155static const struct parent_map gcc_parent_map_8[] = {
156 { P_XO, 0 },
157 { P_HDMI_PHY_PLL_CLK, 1 },
158 { P_CORE_BI_PLL_TEST_SE, 7 },
159};
160
161static const char * const gcc_parent_names_8[] = {
162 "cxo",
163 "hdmi_phy_pll_clk",
164 "core_bi_pll_test_se",
165};
166
167static const struct parent_map gcc_parent_map_9[] = {
168 { P_XO, 0 },
169 { P_GPLL0_OUT_MAIN, 1 },
170 { P_DSI0_PHY_PLL_OUT_DSICLK, 2 },
171 { P_GPLL6_OUT_AUX, 3 },
172 { P_CORE_BI_PLL_TEST_SE, 7 },
173};
174
175static const char * const gcc_parent_names_9[] = {
176 "cxo",
177 "gpll0_out_main",
178 "dsi0_phy_pll_out_dsiclk",
179 "gpll6_out_aux",
180 "core_bi_pll_test_se",
181};
182
183static const struct parent_map gcc_parent_map_10[] = {
184 { P_XO, 0 },
185 { P_SLEEP_CLK, 1 },
186 { P_CORE_BI_PLL_TEST_SE, 7 },
187};
188
189static const char * const gcc_parent_names_10[] = {
190 "cxo",
191 "sleep_clk",
192 "core_bi_pll_test_se",
193};
194
195static const struct parent_map gcc_parent_map_11[] = {
196 { P_XO, 0 },
197 { P_PCIE_0_PIPE_CLK, 1 },
198 { P_CORE_BI_PLL_TEST_SE, 7 },
199};
200
201static const char * const gcc_parent_names_11[] = {
202 "cxo",
203 "pcie_0_pipe_clk",
204 "core_bi_pll_test_se",
205};
206
207static const struct parent_map gcc_parent_map_12[] = {
208 { P_XO, 0 },
209 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
210 { P_GPLL0_OUT_AUX, 2 },
211 { P_CORE_BI_PLL_TEST_SE, 7 },
212};
213
214static const char * const gcc_parent_names_12[] = {
215 "cxo",
216 "dsi0pll_pclk_src",
217 "gpll0_out_aux",
218 "core_bi_pll_test_se",
219};
220
221static const struct parent_map gcc_parent_map_13[] = {
222 { P_XO, 0 },
223 { P_GPLL0_OUT_MAIN, 1 },
224 { P_GPLL4_OUT_MAIN, 2 },
225 { P_GPLL6_OUT_AUX, 3 },
226 { P_CORE_BI_PLL_TEST_SE, 7 },
227};
228
229static const char * const gcc_parent_names_13[] = {
230 "cxo",
231 "gpll0_out_main",
232 "gpll4_out_main",
233 "gpll6_out_aux",
234 "core_bi_pll_test_se",
235};
236
237static const struct parent_map gcc_parent_map_14[] = {
238 { P_XO, 0 },
239 { P_GPLL0_OUT_MAIN, 1 },
240 { P_GPLL4_OUT_AUX, 2 },
241 { P_CORE_BI_PLL_TEST_SE, 7 },
242};
243
244static const char * const gcc_parent_names_14[] = {
245 "cxo",
246 "gpll0_out_main",
247 "gpll4_out_aux",
248 "core_bi_pll_test_se",
249};
250
251static const struct parent_map gcc_parent_map_15[] = {
252 { P_XO, 0 },
253 { P_GPLL0_OUT_AUX, 2 },
254 { P_CORE_BI_PLL_TEST_SE, 7 },
255};
256
257static const char * const gcc_parent_names_15[] = {
258 "cxo",
259 "gpll0_out_aux",
260 "core_bi_pll_test_se",
261};
262
263static struct clk_fixed_factor cxo = {
264 .mult = 1,
265 .div = 1,
266 .hw.init = &(struct clk_init_data){
267 .name = "cxo",
268 .parent_names = (const char *[]){ "xo_board" },
269 .num_parents = 1,
270 .ops = &clk_fixed_factor_ops,
271 },
272};
273
274static struct clk_alpha_pll gpll0_sleep_clk_src = {
275 .offset = 0x21000,
276 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
277 .clkr = {
278 .enable_reg = 0x45008,
279 .enable_mask = BIT(23),
280 .enable_is_inverted = true,
281 .hw.init = &(struct clk_init_data){
282 .name = "gpll0_sleep_clk_src",
283 .parent_names = (const char *[]){ "cxo" },
284 .num_parents = 1,
285 .ops = &clk_alpha_pll_ops,
286 },
287 },
288};
289
290static struct clk_alpha_pll gpll0_out_main = {
291 .offset = 0x21000,
292 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
293 .flags = SUPPORTS_FSM_MODE,
294 .clkr = {
295 .enable_reg = 0x45000,
296 .enable_mask = BIT(0),
297 .hw.init = &(struct clk_init_data){
298 .name = "gpll0_out_main",
299 .parent_names = (const char *[])
300 { "gpll0_sleep_clk_src" },
301 .num_parents = 1,
302 .ops = &clk_alpha_pll_ops,
303 },
304 },
305};
306
307static struct clk_alpha_pll gpll0_ao_out_main = {
308 .offset = 0x21000,
309 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
310 .flags = SUPPORTS_FSM_MODE,
311 .clkr = {
312 .enable_reg = 0x45000,
313 .enable_mask = BIT(0),
314 .hw.init = &(struct clk_init_data){
315 .name = "gpll0_ao_out_main",
316 .parent_names = (const char *[]){ "cxo" },
317 .num_parents = 1,
318 .flags = CLK_IS_CRITICAL,
319 .ops = &clk_alpha_pll_ops,
320 },
321 },
322};
323
324static struct clk_alpha_pll gpll1_out_main = {
325 .offset = 0x20000,
326 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
327 .clkr = {
328 .enable_reg = 0x45000,
329 .enable_mask = BIT(1),
330 .hw.init = &(struct clk_init_data){
331 .name = "gpll1_out_main",
332 .parent_names = (const char *[]){ "cxo" },
333 .num_parents = 1,
334 .ops = &clk_alpha_pll_ops,
335 },
336 },
337};
338
339/* 930MHz configuration */
340static const struct alpha_pll_config gpll3_config = {
341 .l = 48,
342 .alpha = 0x0,
343 .alpha_en_mask = BIT(24),
344 .post_div_mask = 0xf << 8,
345 .post_div_val = 0x1 << 8,
346 .vco_mask = 0x3 << 20,
347 .main_output_mask = 0x1,
348 .config_ctl_val = 0x4001055b,
349};
350
351static const struct pll_vco gpll3_vco[] = {
352 { 700000000, 1400000000, 0 },
353};
354
355static struct clk_alpha_pll gpll3_out_main = {
356 .offset = 0x22000,
357 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
358 .vco_table = gpll3_vco,
359 .num_vco = ARRAY_SIZE(gpll3_vco),
360 .clkr = {
361 .hw.init = &(struct clk_init_data){
362 .name = "gpll3_out_main",
363 .parent_names = (const char *[]){ "cxo" },
364 .num_parents = 1,
365 .ops = &clk_alpha_pll_ops,
366 },
367 },
368};
369
370static struct clk_alpha_pll gpll4_out_main = {
371 .offset = 0x24000,
372 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
373 .clkr = {
374 .enable_reg = 0x45000,
375 .enable_mask = BIT(5),
376 .hw.init = &(struct clk_init_data){
377 .name = "gpll4_out_main",
378 .parent_names = (const char *[]){ "cxo" },
379 .num_parents = 1,
380 .ops = &clk_alpha_pll_ops,
381 },
382 },
383};
384
385static struct clk_pll gpll6 = {
386 .l_reg = 0x37004,
387 .m_reg = 0x37008,
388 .n_reg = 0x3700C,
389 .config_reg = 0x37014,
390 .mode_reg = 0x37000,
391 .status_reg = 0x3701C,
392 .status_bit = 17,
393 .clkr.hw.init = &(struct clk_init_data){
394 .name = "gpll6",
395 .parent_names = (const char *[]){ "cxo" },
396 .num_parents = 1,
397 .ops = &clk_pll_ops,
398 },
399};
400
401static struct clk_regmap gpll6_out_aux = {
402 .enable_reg = 0x45000,
403 .enable_mask = BIT(7),
404 .hw.init = &(struct clk_init_data){
405 .name = "gpll6_out_aux",
406 .parent_names = (const char *[]){ "gpll6" },
407 .num_parents = 1,
408 .ops = &clk_pll_vote_ops,
409 },
410};
411
412static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
413 F(19200000, P_XO, 1, 0, 0),
414 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
415 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
416 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
417 { }
418};
419
420static struct clk_rcg2 apss_ahb_clk_src = {
421 .cmd_rcgr = 0x46000,
422 .mnd_width = 0,
423 .hid_width = 5,
424 .parent_map = gcc_parent_map_0,
425 .freq_tbl = ftbl_apss_ahb_clk_src,
426 .clkr.hw.init = &(struct clk_init_data){
427 .name = "apss_ahb_clk_src",
428 .parent_names = gcc_parent_names_ao_0,
429 .num_parents = 3,
430 .flags = CLK_IS_CRITICAL,
431 .ops = &clk_rcg2_ops,
432 },
433};
434
435static const struct freq_tbl ftbl_blsp1_qup0_i2c_apps_clk_src[] = {
436 F(19200000, P_XO, 1, 0, 0),
437 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
438 { }
439};
440
441static struct clk_rcg2 blsp1_qup0_i2c_apps_clk_src = {
442 .cmd_rcgr = 0x602c,
443 .mnd_width = 0,
444 .hid_width = 5,
445 .parent_map = gcc_parent_map_0,
446 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
447 .clkr.hw.init = &(struct clk_init_data){
448 .name = "blsp1_qup0_i2c_apps_clk_src",
449 .parent_names = gcc_parent_names_0,
450 .num_parents = 3,
451 .ops = &clk_rcg2_ops,
452 },
453};
454
455static const struct freq_tbl ftbl_blsp1_qup0_spi_apps_clk_src[] = {
456 F(960000, P_XO, 10, 1, 2),
457 F(4800000, P_XO, 4, 0, 0),
458 F(9600000, P_XO, 2, 0, 0),
459 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
460 F(19200000, P_XO, 1, 0, 0),
461 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
462 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
463 { }
464};
465
466static struct clk_rcg2 blsp1_qup0_spi_apps_clk_src = {
467 .cmd_rcgr = 0x6034,
468 .mnd_width = 8,
469 .hid_width = 5,
470 .parent_map = gcc_parent_map_0,
471 .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
472 .clkr.hw.init = &(struct clk_init_data){
473 .name = "blsp1_qup0_spi_apps_clk_src",
474 .parent_names = gcc_parent_names_0,
475 .num_parents = 3,
476 .ops = &clk_rcg2_ops,
477 },
478};
479
480static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
481 .cmd_rcgr = 0x200c,
482 .mnd_width = 0,
483 .hid_width = 5,
484 .parent_map = gcc_parent_map_0,
485 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
486 .clkr.hw.init = &(struct clk_init_data){
487 .name = "blsp1_qup1_i2c_apps_clk_src",
488 .parent_names = gcc_parent_names_0,
489 .num_parents = 3,
490 .ops = &clk_rcg2_ops,
491 },
492};
493
494static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
495 F(960000, P_XO, 10, 1, 2),
496 F(4800000, P_XO, 4, 0, 0),
497 F(9600000, P_XO, 2, 0, 0),
498 F(10480000, P_GPLL0_OUT_MAIN, 1, 3, 229),
499 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
500 F(19200000, P_XO, 1, 0, 0),
501 F(20961000, P_GPLL0_OUT_MAIN, 1, 6, 229),
502 { }
503};
504
505static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
506 .cmd_rcgr = 0x2024,
507 .mnd_width = 8,
508 .hid_width = 5,
509 .parent_map = gcc_parent_map_0,
510 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
511 .clkr.hw.init = &(struct clk_init_data){
512 .name = "blsp1_qup1_spi_apps_clk_src",
513 .parent_names = gcc_parent_names_0,
514 .num_parents = 3,
515 .ops = &clk_rcg2_ops,
516 },
517};
518
519static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
520 .cmd_rcgr = 0x3000,
521 .mnd_width = 0,
522 .hid_width = 5,
523 .parent_map = gcc_parent_map_0,
524 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
525 .clkr.hw.init = &(struct clk_init_data){
526 .name = "blsp1_qup2_i2c_apps_clk_src",
527 .parent_names = gcc_parent_names_0,
528 .num_parents = 3,
529 .ops = &clk_rcg2_ops,
530 },
531};
532
533static const struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
534 F(960000, P_XO, 10, 1, 2),
535 F(4800000, P_XO, 4, 0, 0),
536 F(9600000, P_XO, 2, 0, 0),
537 F(15000000, P_GPLL0_OUT_MAIN, 1, 3, 160),
538 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
539 F(19200000, P_XO, 1, 0, 0),
540 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
541 F(30000000, P_GPLL0_OUT_MAIN, 1, 3, 80),
542 { }
543};
544
545static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
546 .cmd_rcgr = 0x3014,
547 .mnd_width = 8,
548 .hid_width = 5,
549 .parent_map = gcc_parent_map_0,
550 .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
551 .clkr.hw.init = &(struct clk_init_data){
552 .name = "blsp1_qup2_spi_apps_clk_src",
553 .parent_names = gcc_parent_names_0,
554 .num_parents = 3,
555 .ops = &clk_rcg2_ops,
556 },
557};
558
559static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
560 .cmd_rcgr = 0x4000,
561 .mnd_width = 0,
562 .hid_width = 5,
563 .parent_map = gcc_parent_map_0,
564 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
565 .clkr.hw.init = &(struct clk_init_data){
566 .name = "blsp1_qup3_i2c_apps_clk_src",
567 .parent_names = gcc_parent_names_0,
568 .num_parents = 3,
569 .ops = &clk_rcg2_ops,
570 },
571};
572
573static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
574 .cmd_rcgr = 0x4024,
575 .mnd_width = 8,
576 .hid_width = 5,
577 .parent_map = gcc_parent_map_0,
578 .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
579 .clkr.hw.init = &(struct clk_init_data){
580 .name = "blsp1_qup3_spi_apps_clk_src",
581 .parent_names = gcc_parent_names_0,
582 .num_parents = 3,
583 .ops = &clk_rcg2_ops,
584 },
585};
586
587static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
588 .cmd_rcgr = 0x5000,
589 .mnd_width = 0,
590 .hid_width = 5,
591 .parent_map = gcc_parent_map_0,
592 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
593 .clkr.hw.init = &(struct clk_init_data){
594 .name = "blsp1_qup4_i2c_apps_clk_src",
595 .parent_names = gcc_parent_names_0,
596 .num_parents = 3,
597 .ops = &clk_rcg2_ops,
598 },
599};
600
601static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
602 .cmd_rcgr = 0x5024,
603 .mnd_width = 8,
604 .hid_width = 5,
605 .parent_map = gcc_parent_map_0,
606 .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
607 .clkr.hw.init = &(struct clk_init_data){
608 .name = "blsp1_qup4_spi_apps_clk_src",
609 .parent_names = gcc_parent_names_0,
610 .num_parents = 3,
611 .ops = &clk_rcg2_ops,
612 },
613};
614
615static const struct freq_tbl ftbl_blsp1_uart0_apps_clk_src[] = {
616 F(3686400, P_GPLL0_OUT_MAIN, 1, 72, 15625),
617 F(7372800, P_GPLL0_OUT_MAIN, 1, 144, 15625),
618 F(14745600, P_GPLL0_OUT_MAIN, 1, 288, 15625),
619 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
620 F(19200000, P_XO, 1, 0, 0),
621 F(24000000, P_GPLL0_OUT_MAIN, 1, 3, 100),
622 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
623 F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
624 F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
625 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),
626 F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
627 F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
628 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
629 F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),
630 F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
631 F(64000000, P_GPLL0_OUT_MAIN, 1, 2, 25),
632 { }
633};
634
635static struct clk_rcg2 blsp1_uart0_apps_clk_src = {
636 .cmd_rcgr = 0x600c,
637 .mnd_width = 16,
638 .hid_width = 5,
639 .parent_map = gcc_parent_map_0,
640 .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
641 .clkr.hw.init = &(struct clk_init_data){
642 .name = "blsp1_uart0_apps_clk_src",
643 .parent_names = gcc_parent_names_0,
644 .num_parents = 3,
645 .ops = &clk_rcg2_ops,
646 },
647};
648
649static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
650 .cmd_rcgr = 0x2044,
651 .mnd_width = 16,
652 .hid_width = 5,
653 .parent_map = gcc_parent_map_0,
654 .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
655 .clkr.hw.init = &(struct clk_init_data){
656 .name = "blsp1_uart1_apps_clk_src",
657 .parent_names = gcc_parent_names_0,
658 .num_parents = 3,
659 .ops = &clk_rcg2_ops,
660 },
661};
662
663static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
664 .cmd_rcgr = 0x3034,
665 .mnd_width = 16,
666 .hid_width = 5,
667 .parent_map = gcc_parent_map_0,
668 .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
669 .clkr.hw.init = &(struct clk_init_data){
670 .name = "blsp1_uart2_apps_clk_src",
671 .parent_names = gcc_parent_names_0,
672 .num_parents = 3,
673 .ops = &clk_rcg2_ops,
674 },
675};
676
677static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
678 .cmd_rcgr = 0x4014,
679 .mnd_width = 16,
680 .hid_width = 5,
681 .parent_map = gcc_parent_map_0,
682 .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
683 .clkr.hw.init = &(struct clk_init_data){
684 .name = "blsp1_uart3_apps_clk_src",
685 .parent_names = gcc_parent_names_0,
686 .num_parents = 3,
687 .ops = &clk_rcg2_ops,
688 },
689};
690
691static struct clk_rcg2 blsp2_qup0_i2c_apps_clk_src = {
692 .cmd_rcgr = 0xc00c,
693 .mnd_width = 0,
694 .hid_width = 5,
695 .parent_map = gcc_parent_map_0,
696 .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
697 .clkr.hw.init = &(struct clk_init_data){
698 .name = "blsp2_qup0_i2c_apps_clk_src",
699 .parent_names = gcc_parent_names_0,
700 .num_parents = 3,
701 .ops = &clk_rcg2_ops,
702 },
703};
704
705static struct clk_rcg2 blsp2_qup0_spi_apps_clk_src = {
706 .cmd_rcgr = 0xc024,
707 .mnd_width = 8,
708 .hid_width = 5,
709 .parent_map = gcc_parent_map_0,
710 .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
711 .clkr.hw.init = &(struct clk_init_data){
712 .name = "blsp2_qup0_spi_apps_clk_src",
713 .parent_names = gcc_parent_names_0,
714 .num_parents = 3,
715 .ops = &clk_rcg2_ops,
716 },
717};
718
719static struct clk_rcg2 blsp2_uart0_apps_clk_src = {
720 .cmd_rcgr = 0xc044,
721 .mnd_width = 16,
722 .hid_width = 5,
723 .parent_map = gcc_parent_map_0,
724 .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
725 .clkr.hw.init = &(struct clk_init_data){
726 .name = "blsp2_uart0_apps_clk_src",
727 .parent_names = gcc_parent_names_0,
728 .num_parents = 3,
729 .ops = &clk_rcg2_ops,
730 },
731};
732
733static struct clk_rcg2 byte0_clk_src = {
734 .cmd_rcgr = 0x4d044,
735 .mnd_width = 0,
736 .hid_width = 5,
737 .parent_map = gcc_parent_map_5,
738 .clkr.hw.init = &(struct clk_init_data){
739 .name = "byte0_clk_src",
740 .parent_names = gcc_parent_names_5,
741 .num_parents = 4,
742 .flags = CLK_SET_RATE_PARENT,
743 .ops = &clk_byte2_ops,
744 },
745};
746
747static const struct freq_tbl ftbl_emac_clk_src[] = {
748 F(5000000, P_GPLL1_OUT_MAIN, 2, 1, 50),
749 F(50000000, P_GPLL1_OUT_MAIN, 10, 0, 0),
750 F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
751 F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
752 { }
753};
754
755static struct clk_rcg2 emac_clk_src = {
756 .cmd_rcgr = 0x4e01c,
757 .mnd_width = 8,
758 .hid_width = 5,
759 .parent_map = gcc_parent_map_4,
760 .freq_tbl = ftbl_emac_clk_src,
761 .clkr.hw.init = &(struct clk_init_data){
762 .name = "emac_clk_src",
763 .parent_names = gcc_parent_names_4,
764 .num_parents = 3,
765 .ops = &clk_rcg2_ops,
766 },
767};
768
769static const struct freq_tbl ftbl_emac_ptp_clk_src[] = {
770 F(50000000, P_GPLL1_OUT_MAIN, 10, 0, 0),
771 F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
772 F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
773 { }
774};
775
776static struct clk_rcg2 emac_ptp_clk_src = {
777 .cmd_rcgr = 0x4e014,
778 .mnd_width = 0,
779 .hid_width = 5,
780 .parent_map = gcc_parent_map_4,
781 .freq_tbl = ftbl_emac_ptp_clk_src,
782 .clkr.hw.init = &(struct clk_init_data){
783 .name = "emac_ptp_clk_src",
784 .parent_names = gcc_parent_names_4,
785 .num_parents = 3,
786 .ops = &clk_rcg2_ops,
787 },
788};
789
790static const struct freq_tbl ftbl_esc0_clk_src[] = {
791 F(19200000, P_XO, 1, 0, 0),
792 { }
793};
794
795static struct clk_rcg2 esc0_clk_src = {
796 .cmd_rcgr = 0x4d05c,
797 .mnd_width = 0,
798 .hid_width = 5,
799 .parent_map = gcc_parent_map_6,
800 .freq_tbl = ftbl_esc0_clk_src,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "esc0_clk_src",
803 .parent_names = gcc_parent_names_6,
804 .num_parents = 4,
805 .ops = &clk_rcg2_ops,
806 },
807};
808
809static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
810 F(19200000, P_XO, 1, 0, 0),
811 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
812 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
813 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
814 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
815 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
816 F(228571429, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
817 F(240000000, P_GPLL6_OUT_AUX, 4.5, 0, 0),
818 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
819 F(270000000, P_GPLL6_OUT_AUX, 4, 0, 0),
820 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
821 F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
822 F(484800000, P_GPLL3_OUT_MAIN, 1, 0, 0),
823 F(523200000, P_GPLL3_OUT_MAIN, 1, 0, 0),
824 F(550000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
825 F(598000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
826 { }
827};
828
829static struct clk_rcg2 gfx3d_clk_src = {
830 .cmd_rcgr = 0x59000,
831 .mnd_width = 0,
832 .hid_width = 5,
833 .parent_map = gcc_parent_map_7,
834 .freq_tbl = ftbl_gfx3d_clk_src,
835 .clkr.hw.init = &(struct clk_init_data){
836 .name = "gfx3d_clk_src",
837 .parent_names = gcc_parent_names_7,
838 .num_parents = 6,
839 .ops = &clk_rcg2_ops,
840 },
841};
842
843static const struct freq_tbl ftbl_gp1_clk_src[] = {
844 F(19200000, P_XO, 1, 0, 0),
845 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
846 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
847 { }
848};
849
850static struct clk_rcg2 gp1_clk_src = {
851 .cmd_rcgr = 0x8004,
852 .mnd_width = 8,
853 .hid_width = 5,
854 .parent_map = gcc_parent_map_2,
855 .freq_tbl = ftbl_gp1_clk_src,
856 .clkr.hw.init = &(struct clk_init_data){
857 .name = "gp1_clk_src",
858 .parent_names = gcc_parent_names_2,
859 .num_parents = 4,
860 .ops = &clk_rcg2_ops,
861 },
862};
863
864static struct clk_rcg2 gp2_clk_src = {
865 .cmd_rcgr = 0x9004,
866 .mnd_width = 8,
867 .hid_width = 5,
868 .parent_map = gcc_parent_map_2,
869 .freq_tbl = ftbl_gp1_clk_src,
870 .clkr.hw.init = &(struct clk_init_data){
871 .name = "gp2_clk_src",
872 .parent_names = gcc_parent_names_2,
873 .num_parents = 4,
874 .ops = &clk_rcg2_ops,
875 },
876};
877
878static struct clk_rcg2 gp3_clk_src = {
879 .cmd_rcgr = 0xa004,
880 .mnd_width = 8,
881 .hid_width = 5,
882 .parent_map = gcc_parent_map_2,
883 .freq_tbl = ftbl_gp1_clk_src,
884 .clkr.hw.init = &(struct clk_init_data){
885 .name = "gp3_clk_src",
886 .parent_names = gcc_parent_names_2,
887 .num_parents = 4,
888 .ops = &clk_rcg2_ops,
889 },
890};
891
892static struct clk_rcg2 hdmi_app_clk_src = {
893 .cmd_rcgr = 0x4d0e4,
894 .mnd_width = 0,
895 .hid_width = 5,
896 .parent_map = gcc_parent_map_1,
897 .freq_tbl = ftbl_esc0_clk_src,
898 .clkr.hw.init = &(struct clk_init_data){
899 .name = "hdmi_app_clk_src",
900 .parent_names = gcc_parent_names_1,
901 .num_parents = 2,
902 .ops = &clk_rcg2_ops,
903 },
904};
905
906static struct clk_rcg2 hdmi_pclk_clk_src = {
907 .cmd_rcgr = 0x4d0dc,
908 .mnd_width = 0,
909 .hid_width = 5,
910 .parent_map = gcc_parent_map_8,
911 .freq_tbl = ftbl_esc0_clk_src,
912 .clkr.hw.init = &(struct clk_init_data){
913 .name = "hdmi_pclk_clk_src",
914 .parent_names = gcc_parent_names_8,
915 .num_parents = 3,
916 .ops = &clk_rcg2_ops,
917 },
918};
919
920static const struct freq_tbl ftbl_mdp_clk_src[] = {
921 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
922 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
923 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
924 F(145454545, P_GPLL0_OUT_MAIN, 5.5, 0, 0),
925 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
926 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
927 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
928 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
929 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
930 { }
931};
932
933static struct clk_rcg2 mdp_clk_src = {
934 .cmd_rcgr = 0x4d014,
935 .mnd_width = 0,
936 .hid_width = 5,
937 .parent_map = gcc_parent_map_9,
938 .freq_tbl = ftbl_mdp_clk_src,
939 .clkr.hw.init = &(struct clk_init_data){
940 .name = "mdp_clk_src",
941 .parent_names = gcc_parent_names_9,
942 .num_parents = 5,
943 .ops = &clk_rcg2_ops,
944 },
945};
946
947static const struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
948 F(1200000, P_XO, 16, 0, 0),
949 { }
950};
951
952static struct clk_rcg2 pcie_0_aux_clk_src = {
953 .cmd_rcgr = 0x3e024,
954 .mnd_width = 16,
955 .hid_width = 5,
956 .parent_map = gcc_parent_map_10,
957 .freq_tbl = ftbl_pcie_0_aux_clk_src,
958 .clkr.hw.init = &(struct clk_init_data){
959 .name = "pcie_0_aux_clk_src",
960 .parent_names = gcc_parent_names_10,
961 .num_parents = 3,
962 .ops = &clk_rcg2_ops,
963 },
964};
965
966static const struct freq_tbl ftbl_pcie_0_pipe_clk_src[] = {
967 F(19200000, P_XO, 1, 0, 0),
968 F(125000000, P_PCIE_0_PIPE_CLK, 2, 0, 0),
969 F(250000000, P_PCIE_0_PIPE_CLK, 1, 0, 0),
970 { }
971};
972
973static struct clk_rcg2 pcie_0_pipe_clk_src = {
974 .cmd_rcgr = 0x3e01c,
975 .mnd_width = 0,
976 .hid_width = 5,
977 .parent_map = gcc_parent_map_11,
978 .freq_tbl = ftbl_pcie_0_pipe_clk_src,
979 .clkr.hw.init = &(struct clk_init_data){
980 .name = "pcie_0_pipe_clk_src",
981 .parent_names = gcc_parent_names_11,
982 .num_parents = 3,
983 .ops = &clk_rcg2_ops,
984 },
985};
986
987static struct clk_rcg2 pclk0_clk_src = {
988 .cmd_rcgr = 0x4d000,
989 .mnd_width = 8,
990 .hid_width = 5,
991 .parent_map = gcc_parent_map_12,
992 .clkr.hw.init = &(struct clk_init_data){
993 .name = "pclk0_clk_src",
994 .parent_names = gcc_parent_names_12,
995 .num_parents = 4,
996 .flags = CLK_SET_RATE_PARENT,
997 .ops = &clk_pixel_ops,
998 },
999};
1000
1001static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1002 F(19200000, P_XO, 1, 0, 0),
1003 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
1004 { }
1005};
1006
1007static struct clk_rcg2 pdm2_clk_src = {
1008 .cmd_rcgr = 0x44010,
1009 .mnd_width = 0,
1010 .hid_width = 5,
1011 .parent_map = gcc_parent_map_0,
1012 .freq_tbl = ftbl_pdm2_clk_src,
1013 .clkr.hw.init = &(struct clk_init_data){
1014 .name = "pdm2_clk_src",
1015 .parent_names = gcc_parent_names_0,
1016 .num_parents = 3,
1017 .ops = &clk_rcg2_ops,
1018 },
1019};
1020
1021static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
1022 F(144000, P_XO, 16, 3, 25),
1023 F(400000, P_XO, 12, 1, 4),
1024 F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
1025 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
1026 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1027 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1028 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1029 F(192000000, P_GPLL4_OUT_MAIN, 6, 0, 0),
1030 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1031 F(384000000, P_GPLL4_OUT_MAIN, 3, 0, 0),
1032 { }
1033};
1034
1035static struct clk_rcg2 sdcc1_apps_clk_src = {
1036 .cmd_rcgr = 0x42004,
1037 .mnd_width = 8,
1038 .hid_width = 5,
1039 .parent_map = gcc_parent_map_13,
1040 .freq_tbl = ftbl_sdcc1_apps_clk_src,
1041 .clkr.hw.init = &(struct clk_init_data){
1042 .name = "sdcc1_apps_clk_src",
1043 .parent_names = gcc_parent_names_13,
1044 .num_parents = 5,
1045 .ops = &clk_rcg2_ops,
1046 },
1047};
1048
1049static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
1050 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1051 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1052 { }
1053};
1054
1055static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1056 .cmd_rcgr = 0x5d000,
1057 .mnd_width = 8,
1058 .hid_width = 5,
1059 .parent_map = gcc_parent_map_3,
1060 .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
1061 .clkr.hw.init = &(struct clk_init_data){
1062 .name = "sdcc1_ice_core_clk_src",
1063 .parent_names = gcc_parent_names_3,
1064 .num_parents = 4,
1065 .ops = &clk_rcg2_ops,
1066 },
1067};
1068
1069static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
1070 F(144000, P_XO, 16, 3, 25),
1071 F(400000, P_XO, 12, 1, 4),
1072 F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
1073 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
1074 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1075 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1076 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1077 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1078 { }
1079};
1080
1081static struct clk_rcg2 sdcc2_apps_clk_src = {
1082 .cmd_rcgr = 0x43004,
1083 .mnd_width = 8,
1084 .hid_width = 5,
1085 .parent_map = gcc_parent_map_14,
1086 .freq_tbl = ftbl_sdcc2_apps_clk_src,
1087 .clkr.hw.init = &(struct clk_init_data){
1088 .name = "sdcc2_apps_clk_src",
1089 .parent_names = gcc_parent_names_14,
1090 .num_parents = 4,
1091 .ops = &clk_rcg2_ops,
1092 },
1093};
1094
1095static struct clk_rcg2 usb20_mock_utmi_clk_src = {
1096 .cmd_rcgr = 0x41048,
1097 .mnd_width = 0,
1098 .hid_width = 5,
1099 .parent_map = gcc_parent_map_1,
1100 .freq_tbl = ftbl_esc0_clk_src,
1101 .clkr.hw.init = &(struct clk_init_data){
1102 .name = "usb20_mock_utmi_clk_src",
1103 .parent_names = gcc_parent_names_1,
1104 .num_parents = 2,
1105 .ops = &clk_rcg2_ops,
1106 },
1107};
1108
1109static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
1110 F(19200000, P_XO, 1, 0, 0),
1111 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1112 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1113 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1114 { }
1115};
1116
1117static struct clk_rcg2 usb30_master_clk_src = {
1118 .cmd_rcgr = 0x39028,
1119 .mnd_width = 8,
1120 .hid_width = 5,
1121 .parent_map = gcc_parent_map_0,
1122 .freq_tbl = ftbl_usb30_master_clk_src,
1123 .clkr.hw.init = &(struct clk_init_data){
1124 .name = "usb30_master_clk_src",
1125 .parent_names = gcc_parent_names_0,
1126 .num_parents = 3,
1127 .ops = &clk_rcg2_ops,
1128 },
1129};
1130
1131static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1132 .cmd_rcgr = 0x3901c,
1133 .mnd_width = 0,
1134 .hid_width = 5,
1135 .parent_map = gcc_parent_map_1,
1136 .freq_tbl = ftbl_esc0_clk_src,
1137 .clkr.hw.init = &(struct clk_init_data){
1138 .name = "usb30_mock_utmi_clk_src",
1139 .parent_names = gcc_parent_names_1,
1140 .num_parents = 2,
1141 .ops = &clk_rcg2_ops,
1142 },
1143};
1144
1145static struct clk_rcg2 usb3_phy_aux_clk_src = {
1146 .cmd_rcgr = 0x3903c,
1147 .mnd_width = 0,
1148 .hid_width = 5,
1149 .parent_map = gcc_parent_map_1,
1150 .freq_tbl = ftbl_pcie_0_aux_clk_src,
1151 .clkr.hw.init = &(struct clk_init_data){
1152 .name = "usb3_phy_aux_clk_src",
1153 .parent_names = gcc_parent_names_1,
1154 .num_parents = 2,
1155 .ops = &clk_rcg2_ops,
1156 },
1157};
1158
1159static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1160 F(19200000, P_XO, 1, 0, 0),
1161 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1162 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1163 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1164 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1165 { }
1166};
1167
1168static struct clk_rcg2 usb_hs_system_clk_src = {
1169 .cmd_rcgr = 0x41010,
1170 .mnd_width = 0,
1171 .hid_width = 5,
1172 .parent_map = gcc_parent_map_3,
1173 .freq_tbl = ftbl_usb_hs_system_clk_src,
1174 .clkr.hw.init = &(struct clk_init_data){
1175 .name = "usb_hs_system_clk_src",
1176 .parent_names = gcc_parent_names_3,
1177 .num_parents = 4,
1178 .ops = &clk_rcg2_ops,
1179 },
1180};
1181
1182static struct clk_rcg2 vsync_clk_src = {
1183 .cmd_rcgr = 0x4d02c,
1184 .mnd_width = 0,
1185 .hid_width = 5,
1186 .parent_map = gcc_parent_map_15,
1187 .freq_tbl = ftbl_esc0_clk_src,
1188 .clkr.hw.init = &(struct clk_init_data){
1189 .name = "vsync_clk_src",
1190 .parent_names = gcc_parent_names_15,
1191 .num_parents = 3,
1192 .ops = &clk_rcg2_ops,
1193 },
1194};
1195
1196static struct clk_branch gcc_apss_ahb_clk = {
1197 .halt_reg = 0x4601c,
1198 .halt_check = BRANCH_HALT_VOTED,
1199 .clkr = {
1200 .enable_reg = 0x45004,
1201 .enable_mask = BIT(14),
1202 .hw.init = &(struct clk_init_data){
1203 .name = "gcc_apss_ahb_clk",
1204 .parent_names = (const char *[]){
1205 "apss_ahb_clk_src",
1206 },
1207 .num_parents = 1,
1208 .flags = CLK_SET_RATE_PARENT,
1209 .ops = &clk_branch2_ops,
1210 },
1211 },
1212};
1213
1214static struct clk_branch gcc_apss_tcu_clk = {
1215 .halt_reg = 0x5b004,
1216 .halt_check = BRANCH_VOTED,
1217 .clkr = {
1218 .enable_reg = 0x4500c,
1219 .enable_mask = BIT(1),
1220 .hw.init = &(struct clk_init_data){
1221 .name = "gcc_apss_tcu_clk",
1222 .ops = &clk_branch2_ops,
1223 },
1224 },
1225};
1226
1227static struct clk_branch gcc_bimc_gfx_clk = {
1228 .halt_reg = 0x59034,
1229 .halt_check = BRANCH_HALT,
1230 .clkr = {
1231 .enable_reg = 0x59034,
1232 .enable_mask = BIT(0),
1233 .hw.init = &(struct clk_init_data){
1234 .name = "gcc_bimc_gfx_clk",
1235 .ops = &clk_branch2_ops,
1236 .parent_names = (const char *[]){
1237 "gcc_apss_tcu_clk",
1238 },
1239
1240 },
1241 },
1242};
1243
1244static struct clk_branch gcc_bimc_gpu_clk = {
1245 .halt_reg = 0x59030,
1246 .halt_check = BRANCH_HALT,
1247 .clkr = {
1248 .enable_reg = 0x59030,
1249 .enable_mask = BIT(0),
1250 .hw.init = &(struct clk_init_data){
1251 .name = "gcc_bimc_gpu_clk",
1252 .ops = &clk_branch2_ops,
1253 },
1254 },
1255};
1256
1257static struct clk_branch gcc_bimc_mdss_clk = {
1258 .halt_reg = 0x31038,
1259 .halt_check = BRANCH_HALT,
1260 .clkr = {
1261 .enable_reg = 0x31038,
1262 .enable_mask = BIT(0),
1263 .hw.init = &(struct clk_init_data){
1264 .name = "gcc_bimc_mdss_clk",
1265 .ops = &clk_branch2_ops,
1266 },
1267 },
1268};
1269
1270static struct clk_branch gcc_blsp1_ahb_clk = {
1271 .halt_reg = 0x1008,
1272 .halt_check = BRANCH_HALT_VOTED,
1273 .clkr = {
1274 .enable_reg = 0x45004,
1275 .enable_mask = BIT(10),
1276 .hw.init = &(struct clk_init_data){
1277 .name = "gcc_blsp1_ahb_clk",
1278 .ops = &clk_branch2_ops,
1279 },
1280 },
1281};
1282
1283static struct clk_branch gcc_dcc_clk = {
1284 .halt_reg = 0x77004,
1285 .halt_check = BRANCH_HALT,
1286 .clkr = {
1287 .enable_reg = 0x77004,
1288 .enable_mask = BIT(0),
1289 .hw.init = &(struct clk_init_data){
1290 .name = "gcc_dcc_clk",
1291 .ops = &clk_branch2_ops,
1292 },
1293 },
1294};
1295
1296static struct clk_branch gcc_dcc_xo_clk = {
1297 .halt_reg = 0x77008,
1298 .halt_check = BRANCH_HALT,
1299 .clkr = {
1300 .enable_reg = 0x77008,
1301 .enable_mask = BIT(0),
1302 .hw.init = &(struct clk_init_data){
1303 .name = "gcc_dcc_xo_clk",
1304 .ops = &clk_branch2_ops,
1305 },
1306 },
1307};
1308
1309static struct clk_branch gcc_blsp1_qup0_i2c_apps_clk = {
1310 .halt_reg = 0x6028,
1311 .halt_check = BRANCH_HALT,
1312 .clkr = {
1313 .enable_reg = 0x6028,
1314 .enable_mask = BIT(0),
1315 .hw.init = &(struct clk_init_data){
1316 .name = "gcc_blsp1_qup0_i2c_apps_clk",
1317 .parent_names = (const char *[]){
1318 "blsp1_qup0_i2c_apps_clk_src",
1319 },
1320 .num_parents = 1,
1321 .flags = CLK_SET_RATE_PARENT,
1322 .ops = &clk_branch2_ops,
1323 },
1324 },
1325};
1326
1327static struct clk_branch gcc_blsp1_qup0_spi_apps_clk = {
1328 .halt_reg = 0x6024,
1329 .halt_check = BRANCH_HALT,
1330 .clkr = {
1331 .enable_reg = 0x6024,
1332 .enable_mask = BIT(0),
1333 .hw.init = &(struct clk_init_data){
1334 .name = "gcc_blsp1_qup0_spi_apps_clk",
1335 .parent_names = (const char *[]){
1336 "blsp1_qup0_spi_apps_clk_src",
1337 },
1338 .num_parents = 1,
1339 .flags = CLK_SET_RATE_PARENT,
1340 .ops = &clk_branch2_ops,
1341 },
1342 },
1343};
1344
1345static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1346 .halt_reg = 0x2008,
1347 .halt_check = BRANCH_HALT,
1348 .clkr = {
1349 .enable_reg = 0x2008,
1350 .enable_mask = BIT(0),
1351 .hw.init = &(struct clk_init_data){
1352 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1353 .parent_names = (const char *[]){
1354 "blsp1_qup1_i2c_apps_clk_src",
1355 },
1356 .num_parents = 1,
1357 .flags = CLK_SET_RATE_PARENT,
1358 .ops = &clk_branch2_ops,
1359 },
1360 },
1361};
1362
1363static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1364 .halt_reg = 0x2004,
1365 .halt_check = BRANCH_HALT,
1366 .clkr = {
1367 .enable_reg = 0x2004,
1368 .enable_mask = BIT(0),
1369 .hw.init = &(struct clk_init_data){
1370 .name = "gcc_blsp1_qup1_spi_apps_clk",
1371 .parent_names = (const char *[]){
1372 "blsp1_qup1_spi_apps_clk_src",
1373 },
1374 .num_parents = 1,
1375 .flags = CLK_SET_RATE_PARENT,
1376 .ops = &clk_branch2_ops,
1377 },
1378 },
1379};
1380
1381static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1382 .halt_reg = 0x3010,
1383 .halt_check = BRANCH_HALT,
1384 .clkr = {
1385 .enable_reg = 0x3010,
1386 .enable_mask = BIT(0),
1387 .hw.init = &(struct clk_init_data){
1388 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1389 .parent_names = (const char *[]){
1390 "blsp1_qup2_i2c_apps_clk_src",
1391 },
1392 .num_parents = 1,
1393 .flags = CLK_SET_RATE_PARENT,
1394 .ops = &clk_branch2_ops,
1395 },
1396 },
1397};
1398
1399static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1400 .halt_reg = 0x300c,
1401 .halt_check = BRANCH_HALT,
1402 .clkr = {
1403 .enable_reg = 0x300c,
1404 .enable_mask = BIT(0),
1405 .hw.init = &(struct clk_init_data){
1406 .name = "gcc_blsp1_qup2_spi_apps_clk",
1407 .parent_names = (const char *[]){
1408 "blsp1_qup2_spi_apps_clk_src",
1409 },
1410 .num_parents = 1,
1411 .flags = CLK_SET_RATE_PARENT,
1412 .ops = &clk_branch2_ops,
1413 },
1414 },
1415};
1416
1417static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1418 .halt_reg = 0x4020,
1419 .halt_check = BRANCH_HALT,
1420 .clkr = {
1421 .enable_reg = 0x4020,
1422 .enable_mask = BIT(0),
1423 .hw.init = &(struct clk_init_data){
1424 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1425 .parent_names = (const char *[]){
1426 "blsp1_qup3_i2c_apps_clk_src",
1427 },
1428 .num_parents = 1,
1429 .flags = CLK_SET_RATE_PARENT,
1430 .ops = &clk_branch2_ops,
1431 },
1432 },
1433};
1434
1435static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1436 .halt_reg = 0x401c,
1437 .halt_check = BRANCH_HALT,
1438 .clkr = {
1439 .enable_reg = 0x401c,
1440 .enable_mask = BIT(0),
1441 .hw.init = &(struct clk_init_data){
1442 .name = "gcc_blsp1_qup3_spi_apps_clk",
1443 .parent_names = (const char *[]){
1444 "blsp1_qup3_spi_apps_clk_src",
1445 },
1446 .num_parents = 1,
1447 .flags = CLK_SET_RATE_PARENT,
1448 .ops = &clk_branch2_ops,
1449 },
1450 },
1451};
1452
1453static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1454 .halt_reg = 0x5020,
1455 .halt_check = BRANCH_HALT,
1456 .clkr = {
1457 .enable_reg = 0x5020,
1458 .enable_mask = BIT(0),
1459 .hw.init = &(struct clk_init_data){
1460 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1461 .parent_names = (const char *[]){
1462 "blsp1_qup4_i2c_apps_clk_src",
1463 },
1464 .num_parents = 1,
1465 .flags = CLK_SET_RATE_PARENT,
1466 .ops = &clk_branch2_ops,
1467 },
1468 },
1469};
1470
1471static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1472 .halt_reg = 0x501c,
1473 .halt_check = BRANCH_HALT,
1474 .clkr = {
1475 .enable_reg = 0x501c,
1476 .enable_mask = BIT(0),
1477 .hw.init = &(struct clk_init_data){
1478 .name = "gcc_blsp1_qup4_spi_apps_clk",
1479 .parent_names = (const char *[]){
1480 "blsp1_qup4_spi_apps_clk_src",
1481 },
1482 .num_parents = 1,
1483 .flags = CLK_SET_RATE_PARENT,
1484 .ops = &clk_branch2_ops,
1485 },
1486 },
1487};
1488
1489static struct clk_branch gcc_blsp1_uart0_apps_clk = {
1490 .halt_reg = 0x6004,
1491 .halt_check = BRANCH_HALT,
1492 .clkr = {
1493 .enable_reg = 0x6004,
1494 .enable_mask = BIT(0),
1495 .hw.init = &(struct clk_init_data){
1496 .name = "gcc_blsp1_uart0_apps_clk",
1497 .parent_names = (const char *[]){
1498 "blsp1_uart0_apps_clk_src",
1499 },
1500 .num_parents = 1,
1501 .flags = CLK_SET_RATE_PARENT,
1502 .ops = &clk_branch2_ops,
1503 },
1504 },
1505};
1506
1507static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1508 .halt_reg = 0x203c,
1509 .halt_check = BRANCH_HALT,
1510 .clkr = {
1511 .enable_reg = 0x203c,
1512 .enable_mask = BIT(0),
1513 .hw.init = &(struct clk_init_data){
1514 .name = "gcc_blsp1_uart1_apps_clk",
1515 .parent_names = (const char *[]){
1516 "blsp1_uart1_apps_clk_src",
1517 },
1518 .num_parents = 1,
1519 .flags = CLK_SET_RATE_PARENT,
1520 .ops = &clk_branch2_ops,
1521 },
1522 },
1523};
1524
1525static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1526 .halt_reg = 0x302c,
1527 .halt_check = BRANCH_HALT,
1528 .clkr = {
1529 .enable_reg = 0x302c,
1530 .enable_mask = BIT(0),
1531 .hw.init = &(struct clk_init_data){
1532 .name = "gcc_blsp1_uart2_apps_clk",
1533 .parent_names = (const char *[]){
1534 "blsp1_uart2_apps_clk_src",
1535 },
1536 .num_parents = 1,
1537 .flags = CLK_SET_RATE_PARENT,
1538 .ops = &clk_branch2_ops,
1539 },
1540 },
1541};
1542
1543static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1544 .halt_reg = 0x400c,
1545 .halt_check = BRANCH_HALT,
1546 .clkr = {
1547 .enable_reg = 0x400c,
1548 .enable_mask = BIT(0),
1549 .hw.init = &(struct clk_init_data){
1550 .name = "gcc_blsp1_uart3_apps_clk",
1551 .parent_names = (const char *[]){
1552 "blsp1_uart3_apps_clk_src",
1553 },
1554 .num_parents = 1,
1555 .flags = CLK_SET_RATE_PARENT,
1556 .ops = &clk_branch2_ops,
1557 },
1558 },
1559};
1560
1561static struct clk_branch gcc_blsp2_ahb_clk = {
1562 .halt_reg = 0xb008,
1563 .halt_check = BRANCH_HALT_VOTED,
1564 .clkr = {
1565 .enable_reg = 0x45004,
1566 .enable_mask = BIT(20),
1567 .hw.init = &(struct clk_init_data){
1568 .name = "gcc_blsp2_ahb_clk",
1569 .ops = &clk_branch2_ops,
1570 },
1571 },
1572};
1573
1574static struct clk_branch gcc_blsp2_qup0_i2c_apps_clk = {
1575 .halt_reg = 0xc008,
1576 .halt_check = BRANCH_HALT,
1577 .clkr = {
1578 .enable_reg = 0xc008,
1579 .enable_mask = BIT(0),
1580 .hw.init = &(struct clk_init_data){
1581 .name = "gcc_blsp2_qup0_i2c_apps_clk",
1582 .parent_names = (const char *[]){
1583 "blsp2_qup0_i2c_apps_clk_src",
1584 },
1585 .num_parents = 1,
1586 .flags = CLK_SET_RATE_PARENT,
1587 .ops = &clk_branch2_ops,
1588 },
1589 },
1590};
1591
1592static struct clk_branch gcc_blsp2_qup0_spi_apps_clk = {
1593 .halt_reg = 0xc004,
1594 .halt_check = BRANCH_HALT,
1595 .clkr = {
1596 .enable_reg = 0xc004,
1597 .enable_mask = BIT(0),
1598 .hw.init = &(struct clk_init_data){
1599 .name = "gcc_blsp2_qup0_spi_apps_clk",
1600 .parent_names = (const char *[]){
1601 "blsp2_qup0_spi_apps_clk_src",
1602 },
1603 .num_parents = 1,
1604 .flags = CLK_SET_RATE_PARENT,
1605 .ops = &clk_branch2_ops,
1606 },
1607 },
1608};
1609
1610static struct clk_branch gcc_blsp2_uart0_apps_clk = {
1611 .halt_reg = 0xc03c,
1612 .halt_check = BRANCH_HALT,
1613 .clkr = {
1614 .enable_reg = 0xc03c,
1615 .enable_mask = BIT(0),
1616 .hw.init = &(struct clk_init_data){
1617 .name = "gcc_blsp2_uart0_apps_clk",
1618 .parent_names = (const char *[]){
1619 "blsp2_uart0_apps_clk_src",
1620 },
1621 .num_parents = 1,
1622 .flags = CLK_SET_RATE_PARENT,
1623 .ops = &clk_branch2_ops,
1624 },
1625 },
1626};
1627
1628static struct clk_branch gcc_boot_rom_ahb_clk = {
1629 .halt_reg = 0x1300c,
1630 .halt_check = BRANCH_HALT_VOTED,
1631 .clkr = {
1632 .enable_reg = 0x45004,
1633 .enable_mask = BIT(7),
1634 .hw.init = &(struct clk_init_data){
1635 .name = "gcc_boot_rom_ahb_clk",
1636 .ops = &clk_branch2_ops,
1637 },
1638 },
1639};
1640
1641static struct clk_branch gcc_crypto_ahb_clk = {
1642 .halt_reg = 0x16024,
1643 .halt_check = BRANCH_VOTED,
1644 .clkr = {
1645 .enable_reg = 0x45004,
1646 .enable_mask = BIT(0),
1647 .hw.init = &(struct clk_init_data){
1648 .name = "gcc_crypto_ahb_clk",
1649 .ops = &clk_branch2_ops,
1650 },
1651 },
1652};
1653
1654static struct clk_branch gcc_crypto_axi_clk = {
1655 .halt_reg = 0x16020,
1656 .halt_check = BRANCH_VOTED,
1657 .clkr = {
1658 .enable_reg = 0x45004,
1659 .enable_mask = BIT(1),
1660 .hw.init = &(struct clk_init_data){
1661 .name = "gcc_crypto_axi_clk",
1662 .ops = &clk_branch2_ops,
1663 },
1664 },
1665};
1666
1667static struct clk_branch gcc_crypto_clk = {
1668 .halt_reg = 0x1601c,
1669 .halt_check = BRANCH_VOTED,
1670 .clkr = {
1671 .enable_reg = 0x45004,
1672 .enable_mask = BIT(2),
1673 .hw.init = &(struct clk_init_data){
1674 .name = "gcc_crypto_clk",
1675 .ops = &clk_branch2_ops,
1676 },
1677 },
1678};
1679
1680static struct clk_branch gcc_eth_axi_clk = {
1681 .halt_reg = 0x4e010,
1682 .halt_check = BRANCH_HALT,
1683 .clkr = {
1684 .enable_reg = 0x4e010,
1685 .enable_mask = BIT(0),
1686 .hw.init = &(struct clk_init_data){
1687 .name = "gcc_eth_axi_clk",
1688 .ops = &clk_branch2_ops,
1689 },
1690 },
1691};
1692
1693static struct clk_branch gcc_eth_ptp_clk = {
1694 .halt_reg = 0x4e004,
1695 .halt_check = BRANCH_HALT,
1696 .clkr = {
1697 .enable_reg = 0x4e004,
1698 .enable_mask = BIT(0),
1699 .hw.init = &(struct clk_init_data){
1700 .name = "gcc_eth_ptp_clk",
1701 .parent_names = (const char *[]){
1702 "emac_ptp_clk_src",
1703 },
1704 .num_parents = 1,
1705 .flags = CLK_SET_RATE_PARENT,
1706 .ops = &clk_branch2_ops,
1707 },
1708 },
1709};
1710
1711static struct clk_branch gcc_eth_rgmii_clk = {
1712 .halt_reg = 0x4e008,
1713 .halt_check = BRANCH_HALT,
1714 .clkr = {
1715 .enable_reg = 0x4e008,
1716 .enable_mask = BIT(0),
1717 .hw.init = &(struct clk_init_data){
1718 .name = "gcc_eth_rgmii_clk",
1719 .parent_names = (const char *[]){
1720 "emac_clk_src",
1721 },
1722 .num_parents = 1,
1723 .flags = CLK_SET_RATE_PARENT,
1724 .ops = &clk_branch2_ops,
1725 },
1726 },
1727};
1728
1729static struct clk_branch gcc_eth_slave_ahb_clk = {
1730 .halt_reg = 0x4e00c,
1731 .halt_check = BRANCH_HALT,
1732 .clkr = {
1733 .enable_reg = 0x4e00c,
1734 .enable_mask = BIT(0),
1735 .hw.init = &(struct clk_init_data){
1736 .name = "gcc_eth_slave_ahb_clk",
1737 .ops = &clk_branch2_ops,
1738 },
1739 },
1740};
1741
1742static struct clk_branch gcc_geni_ir_s_clk = {
1743 .halt_reg = 0xf008,
1744 .halt_check = BRANCH_HALT,
1745 .clkr = {
1746 .enable_reg = 0xf008,
1747 .enable_mask = BIT(0),
1748 .hw.init = &(struct clk_init_data){
1749 .name = "gcc_geni_ir_s_clk",
1750 .ops = &clk_branch2_ops,
1751 },
1752 },
1753};
1754
1755static struct clk_branch gcc_geni_ir_h_clk = {
1756 .halt_reg = 0xf004,
1757 .halt_check = BRANCH_HALT,
1758 .clkr = {
1759 .enable_reg = 0xf004,
1760 .enable_mask = BIT(0),
1761 .hw.init = &(struct clk_init_data){
1762 .name = "gcc_geni_ir_h_clk",
1763 .ops = &clk_branch2_ops,
1764 },
1765 },
1766};
1767
1768static struct clk_branch gcc_gfx_tcu_clk = {
1769 .halt_reg = 0x12020,
1770 .halt_check = BRANCH_VOTED,
1771 .clkr = {
1772 .enable_reg = 0x4500C,
1773 .enable_mask = BIT(2),
1774 .hw.init = &(struct clk_init_data){
1775 .name = "gcc_gfx_tcu_clk",
1776 .ops = &clk_branch2_ops,
1777 },
1778 },
1779};
1780
1781static struct clk_branch gcc_gfx_tbu_clk = {
1782 .halt_reg = 0x12010,
1783 .halt_check = BRANCH_VOTED,
1784 .clkr = {
1785 .enable_reg = 0x4500C,
1786 .enable_mask = BIT(3),
1787 .hw.init = &(struct clk_init_data){
1788 .name = "gcc_gfx_tbu_clk",
1789 .ops = &clk_branch2_ops,
1790 },
1791 },
1792};
1793
1794static struct clk_branch gcc_gp1_clk = {
1795 .halt_reg = 0x8000,
1796 .halt_check = BRANCH_HALT,
1797 .clkr = {
1798 .enable_reg = 0x8000,
1799 .enable_mask = BIT(0),
1800 .hw.init = &(struct clk_init_data){
1801 .name = "gcc_gp1_clk",
1802 .parent_names = (const char *[]){
1803 "gp1_clk_src",
1804 },
1805 .num_parents = 1,
1806 .flags = CLK_SET_RATE_PARENT,
1807 .ops = &clk_branch2_ops,
1808 },
1809 },
1810};
1811
1812static struct clk_branch gcc_gp2_clk = {
1813 .halt_reg = 0x9000,
1814 .halt_check = BRANCH_HALT,
1815 .clkr = {
1816 .enable_reg = 0x9000,
1817 .enable_mask = BIT(0),
1818 .hw.init = &(struct clk_init_data){
1819 .name = "gcc_gp2_clk",
1820 .parent_names = (const char *[]){
1821 "gp2_clk_src",
1822 },
1823 .num_parents = 1,
1824 .flags = CLK_SET_RATE_PARENT,
1825 .ops = &clk_branch2_ops,
1826 },
1827 },
1828};
1829
1830static struct clk_branch gcc_gp3_clk = {
1831 .halt_reg = 0xa000,
1832 .halt_check = BRANCH_HALT,
1833 .clkr = {
1834 .enable_reg = 0xa000,
1835 .enable_mask = BIT(0),
1836 .hw.init = &(struct clk_init_data){
1837 .name = "gcc_gp3_clk",
1838 .parent_names = (const char *[]){
1839 "gp3_clk_src",
1840 },
1841 .num_parents = 1,
1842 .flags = CLK_SET_RATE_PARENT,
1843 .ops = &clk_branch2_ops,
1844 },
1845 },
1846};
1847
1848static struct clk_branch gcc_gtcu_ahb_clk = {
1849 .halt_reg = 0x12044,
1850 .halt_check = BRANCH_VOTED,
1851 .clkr = {
1852 .enable_reg = 0x4500c,
1853 .enable_mask = BIT(13),
1854 .hw.init = &(struct clk_init_data){
1855 .name = "gcc_gtcu_ahb_clk",
1856 .ops = &clk_branch2_ops,
1857 },
1858 },
1859};
1860
1861static struct clk_branch gcc_mdp_tbu_clk = {
1862 .halt_reg = 0x1201c,
1863 .halt_check = BRANCH_VOTED,
1864 .clkr = {
1865 .enable_reg = 0x4500c,
1866 .enable_mask = BIT(4),
1867 .hw.init = &(struct clk_init_data){
1868 .name = "gcc_mdp_tbu_clk",
1869 .ops = &clk_branch2_ops,
1870 },
1871 },
1872};
1873
1874static struct clk_branch gcc_mdss_ahb_clk = {
1875 .halt_reg = 0x4d07c,
1876 .halt_check = BRANCH_HALT,
1877 .clkr = {
1878 .enable_reg = 0x4d07c,
1879 .enable_mask = BIT(0),
1880 .hw.init = &(struct clk_init_data){
1881 .name = "gcc_mdss_ahb_clk",
1882 .ops = &clk_branch2_ops,
1883 },
1884 },
1885};
1886
1887static struct clk_branch gcc_mdss_axi_clk = {
1888 .halt_reg = 0x4d080,
1889 .halt_check = BRANCH_HALT,
1890 .clkr = {
1891 .enable_reg = 0x4d080,
1892 .enable_mask = BIT(0),
1893 .hw.init = &(struct clk_init_data){
1894 .name = "gcc_mdss_axi_clk",
1895 .ops = &clk_branch2_ops,
1896 },
1897 },
1898};
1899
1900static struct clk_branch gcc_mdss_byte0_clk = {
1901 .halt_reg = 0x4d094,
1902 .halt_check = BRANCH_HALT,
1903 .clkr = {
1904 .enable_reg = 0x4d094,
1905 .enable_mask = BIT(0),
1906 .hw.init = &(struct clk_init_data){
1907 .name = "gcc_mdss_byte0_clk",
1908 .parent_names = (const char *[]){
1909 "byte0_clk_src",
1910 },
1911 .num_parents = 1,
1912 .flags = CLK_SET_RATE_PARENT,
1913 .ops = &clk_branch2_ops,
1914 },
1915 },
1916};
1917
1918static struct clk_branch gcc_mdss_esc0_clk = {
1919 .halt_reg = 0x4d098,
1920 .halt_check = BRANCH_HALT,
1921 .clkr = {
1922 .enable_reg = 0x4d098,
1923 .enable_mask = BIT(0),
1924 .hw.init = &(struct clk_init_data){
1925 .name = "gcc_mdss_esc0_clk",
1926 .parent_names = (const char *[]){
1927 "esc0_clk_src",
1928 },
1929 .num_parents = 1,
1930 .flags = CLK_SET_RATE_PARENT,
1931 .ops = &clk_branch2_ops,
1932 },
1933 },
1934};
1935
1936static struct clk_branch gcc_mdss_hdmi_app_clk = {
1937 .halt_reg = 0x4d0d8,
1938 .halt_check = BRANCH_HALT,
1939 .clkr = {
1940 .enable_reg = 0x4d0d8,
1941 .enable_mask = BIT(0),
1942 .hw.init = &(struct clk_init_data){
1943 .name = "gcc_mdss_hdmi_app_clk",
1944 .parent_names = (const char *[]){
1945 "hdmi_app_clk_src",
1946 },
1947 .num_parents = 1,
1948 .flags = CLK_SET_RATE_PARENT,
1949 .ops = &clk_branch2_ops,
1950 },
1951 },
1952};
1953
1954static struct clk_branch gcc_mdss_hdmi_pclk_clk = {
1955 .halt_reg = 0x4d0d4,
1956 .halt_check = BRANCH_HALT,
1957 .clkr = {
1958 .enable_reg = 0x4d0d4,
1959 .enable_mask = BIT(0),
1960 .hw.init = &(struct clk_init_data){
1961 .name = "gcc_mdss_hdmi_pclk_clk",
1962 .parent_names = (const char *[]){
1963 "hdmi_pclk_clk_src",
1964 },
1965 .num_parents = 1,
1966 .flags = CLK_SET_RATE_PARENT,
1967 .ops = &clk_branch2_ops,
1968 },
1969 },
1970};
1971
1972static struct clk_branch gcc_mdss_mdp_clk = {
1973 .halt_reg = 0x4d088,
1974 .halt_check = BRANCH_HALT,
1975 .clkr = {
1976 .enable_reg = 0x4d088,
1977 .enable_mask = BIT(0),
1978 .hw.init = &(struct clk_init_data){
1979 .name = "gcc_mdss_mdp_clk",
1980 .parent_names = (const char *[]){
1981 "mdp_clk_src",
1982 },
1983 .num_parents = 1,
1984 .flags = CLK_SET_RATE_PARENT,
1985 .ops = &clk_branch2_ops,
1986 },
1987 },
1988};
1989
1990static struct clk_branch gcc_mdss_pclk0_clk = {
1991 .halt_reg = 0x4d084,
1992 .halt_check = BRANCH_HALT,
1993 .clkr = {
1994 .enable_reg = 0x4d084,
1995 .enable_mask = BIT(0),
1996 .hw.init = &(struct clk_init_data){
1997 .name = "gcc_mdss_pclk0_clk",
1998 .parent_names = (const char *[]){
1999 "pclk0_clk_src",
2000 },
2001 .num_parents = 1,
2002 .flags = CLK_SET_RATE_PARENT,
2003 .ops = &clk_branch2_ops,
2004 },
2005 },
2006};
2007
2008static struct clk_branch gcc_mdss_vsync_clk = {
2009 .halt_reg = 0x4d090,
2010 .halt_check = BRANCH_HALT,
2011 .clkr = {
2012 .enable_reg = 0x4d090,
2013 .enable_mask = BIT(0),
2014 .hw.init = &(struct clk_init_data){
2015 .name = "gcc_mdss_vsync_clk",
2016 .parent_names = (const char *[]){
2017 "vsync_clk_src",
2018 },
2019 .num_parents = 1,
2020 .flags = CLK_SET_RATE_PARENT,
2021 .ops = &clk_branch2_ops,
2022 },
2023 },
2024};
2025
2026static struct clk_branch gcc_oxili_ahb_clk = {
2027 .halt_reg = 0x59028,
2028 .halt_check = BRANCH_HALT,
2029 .clkr = {
2030 .enable_reg = 0x59028,
2031 .enable_mask = BIT(0),
2032 .hw.init = &(struct clk_init_data){
2033 .name = "gcc_oxili_ahb_clk",
2034 .ops = &clk_branch2_ops,
2035 },
2036 },
2037};
2038
2039static struct clk_branch gcc_oxili_gfx3d_clk = {
2040 .halt_reg = 0x59020,
2041 .halt_check = BRANCH_HALT,
2042 .clkr = {
2043 .enable_reg = 0x59020,
2044 .enable_mask = BIT(0),
2045 .hw.init = &(struct clk_init_data){
2046 .name = "gcc_oxili_gfx3d_clk",
2047 .parent_names = (const char *[]){
2048 "gfx3d_clk_src",
2049 },
2050 .num_parents = 1,
2051 .flags = CLK_SET_RATE_PARENT,
2052 .ops = &clk_branch2_ops,
2053 },
2054 },
2055};
2056
2057static struct clk_branch gcc_pcie_0_aux_clk = {
2058 .halt_reg = 0x3e014,
2059 .halt_check = BRANCH_HALT_VOTED,
2060 .clkr = {
2061 .enable_reg = 0x45004,
2062 .enable_mask = BIT(27),
2063 .hw.init = &(struct clk_init_data){
2064 .name = "gcc_pcie_0_aux_clk",
2065 .parent_names = (const char *[]){
2066 "pcie_0_aux_clk_src",
2067 },
2068 .num_parents = 1,
2069 .flags = CLK_SET_RATE_PARENT,
2070 .ops = &clk_branch2_ops,
2071 },
2072 },
2073};
2074
2075static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2076 .halt_reg = 0x3e008,
2077 .halt_check = BRANCH_HALT_VOTED,
2078 .clkr = {
2079 .enable_reg = 0x45004,
2080 .enable_mask = BIT(11),
2081 .hw.init = &(struct clk_init_data){
2082 .name = "gcc_pcie_0_cfg_ahb_clk",
2083 .ops = &clk_branch2_ops,
2084 },
2085 },
2086};
2087
2088static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2089 .halt_reg = 0x3e018,
2090 .halt_check = BRANCH_HALT_VOTED,
2091 .clkr = {
2092 .enable_reg = 0x45004,
2093 .enable_mask = BIT(18),
2094 .hw.init = &(struct clk_init_data){
2095 .name = "gcc_pcie_0_mstr_axi_clk",
2096 .ops = &clk_branch2_ops,
2097 },
2098 },
2099};
2100
2101static struct clk_branch gcc_pcie_0_pipe_clk = {
2102 .halt_reg = 0x3e00c,
2103 .halt_check = BRANCH_HALT_VOTED,
2104 .clkr = {
2105 .enable_reg = 0x45004,
2106 .enable_mask = BIT(28),
2107 .hw.init = &(struct clk_init_data){
2108 .name = "gcc_pcie_0_pipe_clk",
2109 .parent_names = (const char *[]){
2110 "pcie_0_pipe_clk_src",
2111 },
2112 .num_parents = 1,
2113 .flags = CLK_SET_RATE_PARENT,
2114 .ops = &clk_branch2_ops,
2115 },
2116 },
2117};
2118
2119static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2120 .halt_reg = 0x3e010,
2121 .halt_check = BRANCH_HALT_VOTED,
2122 .clkr = {
2123 .enable_reg = 0x45004,
2124 .enable_mask = BIT(22),
2125 .hw.init = &(struct clk_init_data){
2126 .name = "gcc_pcie_0_slv_axi_clk",
2127 .ops = &clk_branch2_ops,
2128 },
2129 },
2130};
2131
2132static struct clk_branch gcc_pcnoc_usb2_clk = {
2133 .halt_reg = 0x27008,
2134 .halt_check = BRANCH_HALT,
2135 .clkr = {
2136 .enable_reg = 0x27008,
2137 .enable_mask = BIT(0),
2138 .hw.init = &(struct clk_init_data){
2139 .name = "gcc_pcnoc_usb2_clk",
2140 .flags = CLK_IS_CRITICAL,
2141 .ops = &clk_branch2_ops,
2142 },
2143 },
2144};
2145
2146static struct clk_branch gcc_pcnoc_usb3_clk = {
2147 .halt_reg = 0x2700c,
2148 .halt_check = BRANCH_HALT,
2149 .clkr = {
2150 .enable_reg = 0x2700c,
2151 .enable_mask = BIT(0),
2152 .hw.init = &(struct clk_init_data){
2153 .name = "gcc_pcnoc_usb3_clk",
2154 .flags = CLK_IS_CRITICAL,
2155 .ops = &clk_branch2_ops,
2156 },
2157 },
2158};
2159
2160static struct clk_branch gcc_pdm2_clk = {
2161 .halt_reg = 0x4400c,
2162 .halt_check = BRANCH_HALT,
2163 .clkr = {
2164 .enable_reg = 0x4400c,
2165 .enable_mask = BIT(0),
2166 .hw.init = &(struct clk_init_data){
2167 .name = "gcc_pdm2_clk",
2168 .parent_names = (const char *[]){
2169 "pdm2_clk_src",
2170 },
2171 .num_parents = 1,
2172 .flags = CLK_SET_RATE_PARENT,
2173 .ops = &clk_branch2_ops,
2174 },
2175 },
2176};
2177
2178static struct clk_branch gcc_pdm_ahb_clk = {
2179 .halt_reg = 0x44004,
2180 .halt_check = BRANCH_HALT,
2181 .clkr = {
2182 .enable_reg = 0x44004,
2183 .enable_mask = BIT(0),
2184 .hw.init = &(struct clk_init_data){
2185 .name = "gcc_pdm_ahb_clk",
2186 .ops = &clk_branch2_ops,
2187 },
2188 },
2189};
2190
2191static struct clk_branch gcc_prng_ahb_clk = {
2192 .halt_reg = 0x13004,
2193 .halt_check = BRANCH_HALT_VOTED,
2194 .clkr = {
2195 .enable_reg = 0x45004,
2196 .enable_mask = BIT(8),
2197 .hw.init = &(struct clk_init_data){
2198 .name = "gcc_prng_ahb_clk",
2199 .ops = &clk_branch2_ops,
2200 },
2201 },
2202};
2203
2204/* PWM clks do not have XO as parent as src clk is a balance root */
2205static struct clk_branch gcc_pwm0_xo512_clk = {
2206 .halt_reg = 0x44018,
2207 .halt_check = BRANCH_HALT,
2208 .clkr = {
2209 .enable_reg = 0x44018,
2210 .enable_mask = BIT(0),
2211 .hw.init = &(struct clk_init_data){
2212 .name = "gcc_pwm0_xo512_clk",
2213 .ops = &clk_branch2_ops,
2214 },
2215 },
2216};
2217
2218static struct clk_branch gcc_pwm1_xo512_clk = {
2219 .halt_reg = 0x49004,
2220 .halt_check = BRANCH_HALT,
2221 .clkr = {
2222 .enable_reg = 0x49004,
2223 .enable_mask = BIT(0),
2224 .hw.init = &(struct clk_init_data){
2225 .name = "gcc_pwm1_xo512_clk",
2226 .ops = &clk_branch2_ops,
2227 },
2228 },
2229};
2230
2231static struct clk_branch gcc_pwm2_xo512_clk = {
2232 .halt_reg = 0x4a004,
2233 .halt_check = BRANCH_HALT,
2234 .clkr = {
2235 .enable_reg = 0x4a004,
2236 .enable_mask = BIT(0),
2237 .hw.init = &(struct clk_init_data){
2238 .name = "gcc_pwm2_xo512_clk",
2239 .ops = &clk_branch2_ops,
2240 },
2241 },
2242};
2243
2244static struct clk_branch gcc_qdss_dap_clk = {
2245 .halt_reg = 0x29084,
2246 .halt_check = BRANCH_VOTED,
2247 .clkr = {
2248 .enable_reg = 0x45004,
2249 .enable_mask = BIT(21),
2250 .hw.init = &(struct clk_init_data){
2251 .name = "gcc_qdss_dap_clk",
2252 .ops = &clk_branch2_ops,
2253 },
2254 },
2255};
2256
2257static struct clk_branch gcc_sdcc1_ahb_clk = {
2258 .halt_reg = 0x4201c,
2259 .halt_check = BRANCH_HALT,
2260 .clkr = {
2261 .enable_reg = 0x4201c,
2262 .enable_mask = BIT(0),
2263 .hw.init = &(struct clk_init_data){
2264 .name = "gcc_sdcc1_ahb_clk",
2265 .ops = &clk_branch2_ops,
2266 },
2267 },
2268};
2269
2270static struct clk_branch gcc_sdcc1_apps_clk = {
2271 .halt_reg = 0x42018,
2272 .halt_check = BRANCH_HALT,
2273 .clkr = {
2274 .enable_reg = 0x42018,
2275 .enable_mask = BIT(0),
2276 .hw.init = &(struct clk_init_data){
2277 .name = "gcc_sdcc1_apps_clk",
2278 .parent_names = (const char *[]){
2279 "sdcc1_apps_clk_src",
2280 },
2281 .num_parents = 1,
2282 .flags = CLK_SET_RATE_PARENT,
2283 .ops = &clk_branch2_ops,
2284 },
2285 },
2286};
2287
2288static struct clk_branch gcc_sdcc1_ice_core_clk = {
2289 .halt_reg = 0x5d014,
2290 .halt_check = BRANCH_HALT,
2291 .clkr = {
2292 .enable_reg = 0x5d014,
2293 .enable_mask = BIT(0),
2294 .hw.init = &(struct clk_init_data){
2295 .name = "gcc_sdcc1_ice_core_clk",
2296 .parent_names = (const char *[]){
2297 "sdcc1_ice_core_clk_src",
2298 },
2299 .num_parents = 1,
2300 .flags = CLK_SET_RATE_PARENT,
2301 .ops = &clk_branch2_ops,
2302 },
2303 },
2304};
2305
2306static struct clk_branch gcc_sdcc2_ahb_clk = {
2307 .halt_reg = 0x4301c,
2308 .halt_check = BRANCH_HALT,
2309 .clkr = {
2310 .enable_reg = 0x4301c,
2311 .enable_mask = BIT(0),
2312 .hw.init = &(struct clk_init_data){
2313 .name = "gcc_sdcc2_ahb_clk",
2314 .ops = &clk_branch2_ops,
2315 },
2316 },
2317};
2318
2319static struct clk_branch gcc_sdcc2_apps_clk = {
2320 .halt_reg = 0x43018,
2321 .halt_check = BRANCH_HALT,
2322 .clkr = {
2323 .enable_reg = 0x43018,
2324 .enable_mask = BIT(0),
2325 .hw.init = &(struct clk_init_data){
2326 .name = "gcc_sdcc2_apps_clk",
2327 .parent_names = (const char *[]){
2328 "sdcc2_apps_clk_src",
2329 },
2330 .num_parents = 1,
2331 .flags = CLK_SET_RATE_PARENT,
2332 .ops = &clk_branch2_ops,
2333 },
2334 },
2335};
2336
2337static struct clk_branch gcc_smmu_cfg_clk = {
2338 .halt_reg = 0x12038,
2339 .halt_check = BRANCH_VOTED,
2340 .clkr = {
2341 .enable_reg = 0x3600C,
2342 .enable_mask = BIT(12),
2343 .hw.init = &(struct clk_init_data){
2344 .name = "gcc_smmu_cfg_clk",
2345 .ops = &clk_branch2_ops,
2346 },
2347 },
2348};
2349
2350static struct clk_branch gcc_sys_noc_usb3_clk = {
2351 .halt_reg = 0x26014,
2352 .halt_check = BRANCH_HALT,
2353 .clkr = {
2354 .enable_reg = 0x26014,
2355 .enable_mask = BIT(0),
2356 .hw.init = &(struct clk_init_data){
2357 .name = "gcc_sys_noc_usb3_clk",
2358 .parent_names = (const char *[]){
2359 "usb30_master_clk_src",
2360 },
2361 .num_parents = 1,
2362 .ops = &clk_branch2_ops,
2363 },
2364 },
2365};
2366
2367static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
2368 .halt_reg = 0x4100C,
2369 .halt_check = BRANCH_HALT,
2370 .clkr = {
2371 .enable_reg = 0x4100C,
2372 .enable_mask = BIT(0),
2373 .hw.init = &(struct clk_init_data){
2374 .name = "gcc_usb_hs_inactivity_timers_clk",
2375 .ops = &clk_branch2_ops,
2376 },
2377 },
2378};
2379
2380static struct clk_branch gcc_usb20_mock_utmi_clk = {
2381 .halt_reg = 0x41044,
2382 .halt_check = BRANCH_HALT,
2383 .clkr = {
2384 .enable_reg = 0x41044,
2385 .enable_mask = BIT(0),
2386 .hw.init = &(struct clk_init_data){
2387 .name = "gcc_usb20_mock_utmi_clk",
2388 .parent_names = (const char *[]){
2389 "usb20_mock_utmi_clk_src",
2390 },
2391 .num_parents = 1,
2392 .flags = CLK_SET_RATE_PARENT,
2393 .ops = &clk_branch2_ops,
2394 },
2395 },
2396};
2397
2398static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2399 .halt_reg = 0x4102c,
2400 .halt_check = BRANCH_HALT,
2401 .clkr = {
2402 .enable_reg = 0x4102c,
2403 .enable_mask = BIT(0),
2404 .hw.init = &(struct clk_init_data){
2405 .name = "gcc_usb2a_phy_sleep_clk",
2406 .ops = &clk_branch2_ops,
2407 },
2408 },
2409};
2410
2411static struct clk_branch gcc_usb30_master_clk = {
2412 .halt_reg = 0x3900c,
2413 .halt_check = BRANCH_HALT,
2414 .clkr = {
2415 .enable_reg = 0x3900c,
2416 .enable_mask = BIT(0),
2417 .hw.init = &(struct clk_init_data){
2418 .name = "gcc_usb30_master_clk",
2419 .parent_names = (const char *[]){
2420 "usb30_master_clk_src",
2421 },
2422 .num_parents = 1,
2423 .flags = CLK_SET_RATE_PARENT,
2424 .ops = &clk_branch2_ops,
2425 },
2426 },
2427};
2428
2429static struct clk_branch gcc_usb30_mock_utmi_clk = {
2430 .halt_reg = 0x39014,
2431 .halt_check = BRANCH_HALT,
2432 .clkr = {
2433 .enable_reg = 0x39014,
2434 .enable_mask = BIT(0),
2435 .hw.init = &(struct clk_init_data){
2436 .name = "gcc_usb30_mock_utmi_clk",
2437 .parent_names = (const char *[]){
2438 "usb30_mock_utmi_clk_src",
2439 },
2440 .num_parents = 1,
2441 .flags = CLK_SET_RATE_PARENT,
2442 .ops = &clk_branch2_ops,
2443 },
2444 },
2445};
2446
2447static struct clk_branch gcc_usb30_sleep_clk = {
2448 .halt_reg = 0x39010,
2449 .halt_check = BRANCH_HALT,
2450 .clkr = {
2451 .enable_reg = 0x39010,
2452 .enable_mask = BIT(0),
2453 .hw.init = &(struct clk_init_data){
2454 .name = "gcc_usb30_sleep_clk",
2455 .ops = &clk_branch2_ops,
2456 },
2457 },
2458};
2459
2460static struct clk_branch gcc_usb3_phy_aux_clk = {
2461 .halt_reg = 0x39044,
2462 .halt_check = BRANCH_HALT,
2463 .clkr = {
2464 .enable_reg = 0x39044,
2465 .enable_mask = BIT(0),
2466 .hw.init = &(struct clk_init_data){
2467 .name = "gcc_usb3_phy_aux_clk",
2468 .parent_names = (const char *[]){
2469 "usb3_phy_aux_clk_src",
2470 },
2471 .num_parents = 1,
2472 .flags = CLK_SET_RATE_PARENT,
2473 .ops = &clk_branch2_ops,
2474 },
2475 },
2476};
2477
2478static struct clk_branch gcc_usb3_phy_pipe_clk = {
2479 .halt_check = BRANCH_HALT_SKIP,
2480 .clkr = {
2481 .enable_reg = 0x39018,
2482 .enable_mask = BIT(0),
2483 .hw.init = &(struct clk_init_data){
2484 .name = "gcc_usb3_phy_pipe_clk",
2485 .ops = &clk_branch2_ops,
2486 },
2487 },
2488};
2489
2490static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {
2491 .halt_reg = 0x41030,
2492 .halt_check = BRANCH_HALT,
2493 .clkr = {
2494 .enable_reg = 0x41030,
2495 .enable_mask = BIT(0),
2496 .hw.init = &(struct clk_init_data){
2497 .name = "gcc_usb_hs_phy_cfg_ahb_clk",
2498 .ops = &clk_branch2_ops,
2499 },
2500 },
2501};
2502
2503static struct clk_branch gcc_usb_hs_system_clk = {
2504 .halt_reg = 0x41004,
2505 .halt_check = BRANCH_HALT,
2506 .clkr = {
2507 .enable_reg = 0x41004,
2508 .enable_mask = BIT(0),
2509 .hw.init = &(struct clk_init_data){
2510 .name = "gcc_usb_hs_system_clk",
2511 .parent_names = (const char *[]){
2512 "usb_hs_system_clk_src",
2513 },
2514 .num_parents = 1,
2515 .flags = CLK_SET_RATE_PARENT,
2516 .ops = &clk_branch2_ops,
2517 },
2518 },
2519};
2520
2521static struct clk_hw *gcc_qcs404_hws[] = {
2522 &cxo.hw,
2523};
2524
2525static struct clk_regmap *gcc_qcs404_clocks[] = {
2526 [GCC_APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
2527 [GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC] = &blsp1_qup0_i2c_apps_clk_src.clkr,
2528 [GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC] = &blsp1_qup0_spi_apps_clk_src.clkr,
2529 [GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2530 [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2531 [GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2532 [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2533 [GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2534 [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2535 [GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2536 [GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2537 [GCC_BLSP1_UART0_APPS_CLK_SRC] = &blsp1_uart0_apps_clk_src.clkr,
2538 [GCC_BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2539 [GCC_BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2540 [GCC_BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2541 [GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC] = &blsp2_qup0_i2c_apps_clk_src.clkr,
2542 [GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC] = &blsp2_qup0_spi_apps_clk_src.clkr,
2543 [GCC_BLSP2_UART0_APPS_CLK_SRC] = &blsp2_uart0_apps_clk_src.clkr,
2544 [GCC_BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2545 [GCC_EMAC_CLK_SRC] = &emac_clk_src.clkr,
2546 [GCC_EMAC_PTP_CLK_SRC] = &emac_ptp_clk_src.clkr,
2547 [GCC_ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2548 [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
2549 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
2550 [GCC_BIMC_MDSS_CLK] = &gcc_bimc_mdss_clk.clkr,
2551 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2552 [GCC_BLSP1_QUP0_I2C_APPS_CLK] = &gcc_blsp1_qup0_i2c_apps_clk.clkr,
2553 [GCC_BLSP1_QUP0_SPI_APPS_CLK] = &gcc_blsp1_qup0_spi_apps_clk.clkr,
2554 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2555 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2556 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2557 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2558 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2559 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2560 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2561 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2562 [GCC_BLSP1_UART0_APPS_CLK] = &gcc_blsp1_uart0_apps_clk.clkr,
2563 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2564 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2565 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2566 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2567 [GCC_BLSP2_QUP0_I2C_APPS_CLK] = &gcc_blsp2_qup0_i2c_apps_clk.clkr,
2568 [GCC_BLSP2_QUP0_SPI_APPS_CLK] = &gcc_blsp2_qup0_spi_apps_clk.clkr,
2569 [GCC_BLSP2_UART0_APPS_CLK] = &gcc_blsp2_uart0_apps_clk.clkr,
2570 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2571 [GCC_ETH_AXI_CLK] = &gcc_eth_axi_clk.clkr,
2572 [GCC_ETH_PTP_CLK] = &gcc_eth_ptp_clk.clkr,
2573 [GCC_ETH_RGMII_CLK] = &gcc_eth_rgmii_clk.clkr,
2574 [GCC_ETH_SLAVE_AHB_CLK] = &gcc_eth_slave_ahb_clk.clkr,
2575 [GCC_GENI_IR_S_CLK] = &gcc_geni_ir_s_clk.clkr,
2576 [GCC_GENI_IR_H_CLK] = &gcc_geni_ir_h_clk.clkr,
2577 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2578 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2579 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2580 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
2581 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
2582 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
2583 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
2584 [GCC_MDSS_HDMI_APP_CLK] = &gcc_mdss_hdmi_app_clk.clkr,
2585 [GCC_MDSS_HDMI_PCLK_CLK] = &gcc_mdss_hdmi_pclk_clk.clkr,
2586 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
2587 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
2588 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
2589 [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
2590 [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
2591 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2592 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2593 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2594 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2595 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2596 [GCC_PCNOC_USB2_CLK] = &gcc_pcnoc_usb2_clk.clkr,
2597 [GCC_PCNOC_USB3_CLK] = &gcc_pcnoc_usb3_clk.clkr,
2598 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2599 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2600 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2601 [GCC_PWM0_XO512_CLK] = &gcc_pwm0_xo512_clk.clkr,
2602 [GCC_PWM1_XO512_CLK] = &gcc_pwm1_xo512_clk.clkr,
2603 [GCC_PWM2_XO512_CLK] = &gcc_pwm2_xo512_clk.clkr,
2604 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2605 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2606 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2607 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2608 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2609 [GCC_SYS_NOC_USB3_CLK] = &gcc_sys_noc_usb3_clk.clkr,
2610 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
2611 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2612 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2613 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2614 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2615 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2616 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2617 [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
2618 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2619 [GCC_GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2620 [GCC_GP1_CLK_SRC] = &gp1_clk_src.clkr,
2621 [GCC_GP2_CLK_SRC] = &gp2_clk_src.clkr,
2622 [GCC_GP3_CLK_SRC] = &gp3_clk_src.clkr,
2623 [GCC_GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
2624 [GCC_GPLL0_AO_OUT_MAIN] = &gpll0_ao_out_main.clkr,
2625 [GCC_GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
2626 [GCC_GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
2627 [GCC_GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
2628 [GCC_GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
2629 [GCC_GPLL6] = &gpll6.clkr,
2630 [GCC_GPLL6_OUT_AUX] = &gpll6_out_aux,
2631 [GCC_HDMI_APP_CLK_SRC] = &hdmi_app_clk_src.clkr,
2632 [GCC_HDMI_PCLK_CLK_SRC] = &hdmi_pclk_clk_src.clkr,
2633 [GCC_MDP_CLK_SRC] = &mdp_clk_src.clkr,
2634 [GCC_PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2635 [GCC_PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2636 [GCC_PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2637 [GCC_PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2638 [GCC_SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2639 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
2640 [GCC_SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2641 [GCC_USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
2642 [GCC_USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2643 [GCC_USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2644 [GCC_USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2645 [GCC_USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2646 [GCC_VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2647 [GCC_USB_HS_INACTIVITY_TIMERS_CLK] =
2648 &gcc_usb_hs_inactivity_timers_clk.clkr,
2649 [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
2650 [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
2651 [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
2652 [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
2653 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
2654 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
2655 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
2656 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
2657 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
2658 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
2659 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
2660 [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
2661 [GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr,
2662};
2663
2664static const struct qcom_reset_map gcc_qcs404_resets[] = {
2665 [GCC_GENI_IR_BCR] = { 0x0F000 },
2666 [GCC_USB_HS_BCR] = { 0x41000 },
2667 [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
2668 [GCC_QUSB2_PHY_BCR] = { 0x4103c },
2669 [GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },
2670 [GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },
2671 [GCC_USB3_PHY_BCR] = { 0x39004 },
2672 [GCC_USB_30_BCR] = { 0x39000 },
2673 [GCC_USB3PHY_PHY_BCR] = { 0x39008 },
2674 [GCC_PCIE_0_BCR] = { 0x3e000 },
2675 [GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
2676 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
2677 [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
2678 [GCC_EMAC_BCR] = { 0x4e000 },
2679};
2680
2681static const struct regmap_config gcc_qcs404_regmap_config = {
2682 .reg_bits = 32,
2683 .reg_stride = 4,
2684 .val_bits = 32,
2685 .max_register = 0x7f000,
2686 .fast_io = true,
2687};
2688
2689static const struct qcom_cc_desc gcc_qcs404_desc = {
2690 .config = &gcc_qcs404_regmap_config,
2691 .clks = gcc_qcs404_clocks,
2692 .num_clks = ARRAY_SIZE(gcc_qcs404_clocks),
2693 .resets = gcc_qcs404_resets,
2694 .num_resets = ARRAY_SIZE(gcc_qcs404_resets),
2695};
2696
2697static const struct of_device_id gcc_qcs404_match_table[] = {
2698 { .compatible = "qcom,gcc-qcs404" },
2699 { }
2700};
2701MODULE_DEVICE_TABLE(of, gcc_qcs404_match_table);
2702
2703static int gcc_qcs404_probe(struct platform_device *pdev)
2704{
2705 struct regmap *regmap;
2706 int ret, i;
2707
2708 regmap = qcom_cc_map(pdev, &gcc_qcs404_desc);
2709 if (IS_ERR(regmap))
2710 return PTR_ERR(regmap);
2711
2712 clk_alpha_pll_configure(&gpll3_out_main, regmap, &gpll3_config);
2713
2714 for (i = 0; i < ARRAY_SIZE(gcc_qcs404_hws); i++) {
2715 ret = devm_clk_hw_register(&pdev->dev, gcc_qcs404_hws[i]);
2716 if (ret)
2717 return ret;
2718 }
2719
2720 return qcom_cc_really_probe(pdev, &gcc_qcs404_desc, regmap);
2721}
2722
2723static struct platform_driver gcc_qcs404_driver = {
2724 .probe = gcc_qcs404_probe,
2725 .driver = {
2726 .name = "gcc-qcs404",
2727 .of_match_table = gcc_qcs404_match_table,
2728 },
2729};
2730
2731static int __init gcc_qcs404_init(void)
2732{
2733 return platform_driver_register(&gcc_qcs404_driver);
2734}
2735subsys_initcall(gcc_qcs404_init);
2736
2737static void __exit gcc_qcs404_exit(void)
2738{
2739 platform_driver_unregister(&gcc_qcs404_driver);
2740}
2741module_exit(gcc_qcs404_exit);
2742
2743MODULE_DESCRIPTION("Qualcomm GCC QCS404 Driver");
2744MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
new file mode 100644
index 000000000000..ba239ea4c842
--- /dev/null
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -0,0 +1,2480 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2018, Craig Tatlor.
5 */
6
7#include <linux/kernel.h>
8#include <linux/bitops.h>
9#include <linux/err.h>
10#include <linux/platform_device.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/of_device.h>
14#include <linux/clk-provider.h>
15#include <linux/regmap.h>
16#include <linux/reset-controller.h>
17
18#include <dt-bindings/clock/qcom,gcc-sdm660.h>
19
20#include "common.h"
21#include "clk-regmap.h"
22#include "clk-alpha-pll.h"
23#include "clk-rcg.h"
24#include "clk-branch.h"
25#include "reset.h"
26#include "gdsc.h"
27
28#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
29
30enum {
31 P_XO,
32 P_SLEEP_CLK,
33 P_GPLL0,
34 P_GPLL1,
35 P_GPLL4,
36 P_GPLL0_EARLY_DIV,
37 P_GPLL1_EARLY_DIV,
38};
39
40static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div[] = {
41 { P_XO, 0 },
42 { P_GPLL0, 1 },
43 { P_GPLL0_EARLY_DIV, 6 },
44};
45
46static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div[] = {
47 "xo",
48 "gpll0",
49 "gpll0_early_div",
50};
51
52static const struct parent_map gcc_parent_map_xo_gpll0[] = {
53 { P_XO, 0 },
54 { P_GPLL0, 1 },
55};
56
57static const char * const gcc_parent_names_xo_gpll0[] = {
58 "xo",
59 "gpll0",
60};
61
62static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = {
63 { P_XO, 0 },
64 { P_GPLL0, 1 },
65 { P_SLEEP_CLK, 5 },
66 { P_GPLL0_EARLY_DIV, 6 },
67};
68
69static const char * const gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div[] = {
70 "xo",
71 "gpll0",
72 "sleep_clk",
73 "gpll0_early_div",
74};
75
76static const struct parent_map gcc_parent_map_xo_sleep_clk[] = {
77 { P_XO, 0 },
78 { P_SLEEP_CLK, 5 },
79};
80
81static const char * const gcc_parent_names_xo_sleep_clk[] = {
82 "xo",
83 "sleep_clk",
84};
85
86static const struct parent_map gcc_parent_map_xo_gpll4[] = {
87 { P_XO, 0 },
88 { P_GPLL4, 5 },
89};
90
91static const char * const gcc_parent_names_xo_gpll4[] = {
92 "xo",
93 "gpll4",
94};
95
96static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
97 { P_XO, 0 },
98 { P_GPLL0, 1 },
99 { P_GPLL0_EARLY_DIV, 3 },
100 { P_GPLL1, 4 },
101 { P_GPLL4, 5 },
102 { P_GPLL1_EARLY_DIV, 6 },
103};
104
105static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
106 "xo",
107 "gpll0",
108 "gpll0_early_div",
109 "gpll1",
110 "gpll4",
111 "gpll1_early_div",
112};
113
114static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = {
115 { P_XO, 0 },
116 { P_GPLL0, 1 },
117 { P_GPLL4, 5 },
118 { P_GPLL0_EARLY_DIV, 6 },
119};
120
121static const char * const gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div[] = {
122 "xo",
123 "gpll0",
124 "gpll4",
125 "gpll0_early_div",
126};
127
128static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = {
129 { P_XO, 0 },
130 { P_GPLL0, 1 },
131 { P_GPLL0_EARLY_DIV, 2 },
132 { P_GPLL4, 5 },
133};
134
135static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4[] = {
136 "xo",
137 "gpll0",
138 "gpll0_early_div",
139 "gpll4",
140};
141
142static struct clk_fixed_factor xo = {
143 .mult = 1,
144 .div = 1,
145 .hw.init = &(struct clk_init_data){
146 .name = "xo",
147 .parent_names = (const char *[]){ "xo_board" },
148 .num_parents = 1,
149 .ops = &clk_fixed_factor_ops,
150 },
151};
152
153static struct clk_alpha_pll gpll0_early = {
154 .offset = 0x0,
155 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
156 .clkr = {
157 .enable_reg = 0x52000,
158 .enable_mask = BIT(0),
159 .hw.init = &(struct clk_init_data){
160 .name = "gpll0_early",
161 .parent_names = (const char *[]){ "xo" },
162 .num_parents = 1,
163 .ops = &clk_alpha_pll_ops,
164 },
165 },
166};
167
168static struct clk_fixed_factor gpll0_early_div = {
169 .mult = 1,
170 .div = 2,
171 .hw.init = &(struct clk_init_data){
172 .name = "gpll0_early_div",
173 .parent_names = (const char *[]){ "gpll0_early" },
174 .num_parents = 1,
175 .ops = &clk_fixed_factor_ops,
176 },
177};
178
179static struct clk_alpha_pll_postdiv gpll0 = {
180 .offset = 0x00000,
181 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
182 .clkr.hw.init = &(struct clk_init_data){
183 .name = "gpll0",
184 .parent_names = (const char *[]){ "gpll0_early" },
185 .num_parents = 1,
186 .ops = &clk_alpha_pll_postdiv_ops,
187 },
188};
189
190static struct clk_alpha_pll gpll1_early = {
191 .offset = 0x1000,
192 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
193 .clkr = {
194 .enable_reg = 0x52000,
195 .enable_mask = BIT(1),
196 .hw.init = &(struct clk_init_data){
197 .name = "gpll1_early",
198 .parent_names = (const char *[]){ "xo" },
199 .num_parents = 1,
200 .ops = &clk_alpha_pll_ops,
201 },
202 },
203};
204
205static struct clk_fixed_factor gpll1_early_div = {
206 .mult = 1,
207 .div = 2,
208 .hw.init = &(struct clk_init_data){
209 .name = "gpll1_early_div",
210 .parent_names = (const char *[]){ "gpll1_early" },
211 .num_parents = 1,
212 .ops = &clk_fixed_factor_ops,
213 },
214};
215
216static struct clk_alpha_pll_postdiv gpll1 = {
217 .offset = 0x1000,
218 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
219 .clkr.hw.init = &(struct clk_init_data){
220 .name = "gpll1",
221 .parent_names = (const char *[]){ "gpll1_early" },
222 .num_parents = 1,
223 .ops = &clk_alpha_pll_postdiv_ops,
224 },
225};
226
227static struct clk_alpha_pll gpll4_early = {
228 .offset = 0x77000,
229 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
230 .clkr = {
231 .enable_reg = 0x52000,
232 .enable_mask = BIT(4),
233 .hw.init = &(struct clk_init_data){
234 .name = "gpll4_early",
235 .parent_names = (const char *[]){ "xo" },
236 .num_parents = 1,
237 .ops = &clk_alpha_pll_ops,
238 },
239 },
240};
241
242static struct clk_alpha_pll_postdiv gpll4 = {
243 .offset = 0x77000,
244 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
245 .clkr.hw.init = &(struct clk_init_data)
246 {
247 .name = "gpll4",
248 .parent_names = (const char *[]) { "gpll4_early" },
249 .num_parents = 1,
250 .ops = &clk_alpha_pll_postdiv_ops,
251 },
252};
253
254static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
255 F(19200000, P_XO, 1, 0, 0),
256 F(50000000, P_GPLL0, 12, 0, 0),
257 { }
258};
259
260static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
261 .cmd_rcgr = 0x19020,
262 .mnd_width = 0,
263 .hid_width = 5,
264 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
265 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
266 .clkr.hw.init = &(struct clk_init_data){
267 .name = "blsp1_qup1_i2c_apps_clk_src",
268 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
269 .num_parents = 3,
270 .ops = &clk_rcg2_ops,
271 },
272};
273
274static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
275 F(960000, P_XO, 10, 1, 2),
276 F(4800000, P_XO, 4, 0, 0),
277 F(9600000, P_XO, 2, 0, 0),
278 F(15000000, P_GPLL0, 10, 1, 4),
279 F(19200000, P_XO, 1, 0, 0),
280 F(25000000, P_GPLL0, 12, 1, 2),
281 F(50000000, P_GPLL0, 12, 0, 0),
282 { }
283};
284
285static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
286 .cmd_rcgr = 0x1900c,
287 .mnd_width = 8,
288 .hid_width = 5,
289 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
290 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
291 .clkr.hw.init = &(struct clk_init_data){
292 .name = "blsp1_qup1_spi_apps_clk_src",
293 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
294 .num_parents = 3,
295 .ops = &clk_rcg2_ops,
296 },
297};
298
299static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
300 .cmd_rcgr = 0x1b020,
301 .mnd_width = 0,
302 .hid_width = 5,
303 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
304 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
305 .clkr.hw.init = &(struct clk_init_data){
306 .name = "blsp1_qup2_i2c_apps_clk_src",
307 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
308 .num_parents = 3,
309 .ops = &clk_rcg2_ops,
310 },
311};
312
313static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
314 .cmd_rcgr = 0x1b00c,
315 .mnd_width = 8,
316 .hid_width = 5,
317 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
318 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
319 .clkr.hw.init = &(struct clk_init_data){
320 .name = "blsp1_qup2_spi_apps_clk_src",
321 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
322 .num_parents = 3,
323 .ops = &clk_rcg2_ops,
324 },
325};
326
327static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
328 .cmd_rcgr = 0x1d020,
329 .mnd_width = 0,
330 .hid_width = 5,
331 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
332 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
333 .clkr.hw.init = &(struct clk_init_data){
334 .name = "blsp1_qup3_i2c_apps_clk_src",
335 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
336 .num_parents = 3,
337 .ops = &clk_rcg2_ops,
338 },
339};
340
341static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
342 .cmd_rcgr = 0x1d00c,
343 .mnd_width = 8,
344 .hid_width = 5,
345 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
346 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
347 .clkr.hw.init = &(struct clk_init_data){
348 .name = "blsp1_qup3_spi_apps_clk_src",
349 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
350 .num_parents = 3,
351 .ops = &clk_rcg2_ops,
352 },
353};
354
355static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
356 .cmd_rcgr = 0x1f020,
357 .mnd_width = 0,
358 .hid_width = 5,
359 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
360 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
361 .clkr.hw.init = &(struct clk_init_data){
362 .name = "blsp1_qup4_i2c_apps_clk_src",
363 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
364 .num_parents = 3,
365 .ops = &clk_rcg2_ops,
366 },
367};
368
369static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
370 .cmd_rcgr = 0x1f00c,
371 .mnd_width = 8,
372 .hid_width = 5,
373 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
374 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
375 .clkr.hw.init = &(struct clk_init_data){
376 .name = "blsp1_qup4_spi_apps_clk_src",
377 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
378 .num_parents = 3,
379 .ops = &clk_rcg2_ops,
380 },
381};
382
383static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
384 F(3686400, P_GPLL0, 1, 96, 15625),
385 F(7372800, P_GPLL0, 1, 192, 15625),
386 F(14745600, P_GPLL0, 1, 384, 15625),
387 F(16000000, P_GPLL0, 5, 2, 15),
388 F(19200000, P_XO, 1, 0, 0),
389 F(24000000, P_GPLL0, 5, 1, 5),
390 F(32000000, P_GPLL0, 1, 4, 75),
391 F(40000000, P_GPLL0, 15, 0, 0),
392 F(46400000, P_GPLL0, 1, 29, 375),
393 F(48000000, P_GPLL0, 12.5, 0, 0),
394 F(51200000, P_GPLL0, 1, 32, 375),
395 F(56000000, P_GPLL0, 1, 7, 75),
396 F(58982400, P_GPLL0, 1, 1536, 15625),
397 F(60000000, P_GPLL0, 10, 0, 0),
398 F(63157895, P_GPLL0, 9.5, 0, 0),
399 { }
400};
401
402static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
403 .cmd_rcgr = 0x1a00c,
404 .mnd_width = 16,
405 .hid_width = 5,
406 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
407 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
408 .clkr.hw.init = &(struct clk_init_data){
409 .name = "blsp1_uart1_apps_clk_src",
410 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
411 .num_parents = 3,
412 .ops = &clk_rcg2_ops,
413 },
414};
415
416static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
417 .cmd_rcgr = 0x1c00c,
418 .mnd_width = 16,
419 .hid_width = 5,
420 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
421 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
422 .clkr.hw.init = &(struct clk_init_data){
423 .name = "blsp1_uart2_apps_clk_src",
424 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
425 .num_parents = 3,
426 .ops = &clk_rcg2_ops,
427 },
428};
429
430static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
431 .cmd_rcgr = 0x26020,
432 .mnd_width = 0,
433 .hid_width = 5,
434 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
435 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
436 .clkr.hw.init = &(struct clk_init_data){
437 .name = "blsp2_qup1_i2c_apps_clk_src",
438 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
439 .num_parents = 3,
440 .ops = &clk_rcg2_ops,
441 },
442};
443
444static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
445 .cmd_rcgr = 0x2600c,
446 .mnd_width = 8,
447 .hid_width = 5,
448 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
449 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
450 .clkr.hw.init = &(struct clk_init_data){
451 .name = "blsp2_qup1_spi_apps_clk_src",
452 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
453 .num_parents = 3,
454 .ops = &clk_rcg2_ops,
455 },
456};
457
458static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
459 .cmd_rcgr = 0x28020,
460 .mnd_width = 0,
461 .hid_width = 5,
462 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
463 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
464 .clkr.hw.init = &(struct clk_init_data){
465 .name = "blsp2_qup2_i2c_apps_clk_src",
466 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
467 .num_parents = 3,
468 .ops = &clk_rcg2_ops,
469 },
470};
471
472static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
473 .cmd_rcgr = 0x2800c,
474 .mnd_width = 8,
475 .hid_width = 5,
476 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
477 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
478 .clkr.hw.init = &(struct clk_init_data){
479 .name = "blsp2_qup2_spi_apps_clk_src",
480 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
481 .num_parents = 3,
482 .ops = &clk_rcg2_ops,
483 },
484};
485
486static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
487 .cmd_rcgr = 0x2a020,
488 .mnd_width = 0,
489 .hid_width = 5,
490 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
491 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
492 .clkr.hw.init = &(struct clk_init_data){
493 .name = "blsp2_qup3_i2c_apps_clk_src",
494 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
495 .num_parents = 3,
496 .ops = &clk_rcg2_ops,
497 },
498};
499
500static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
501 .cmd_rcgr = 0x2a00c,
502 .mnd_width = 8,
503 .hid_width = 5,
504 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
505 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
506 .clkr.hw.init = &(struct clk_init_data){
507 .name = "blsp2_qup3_spi_apps_clk_src",
508 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
509 .num_parents = 3,
510 .ops = &clk_rcg2_ops,
511 },
512};
513
514static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
515 .cmd_rcgr = 0x2c020,
516 .mnd_width = 0,
517 .hid_width = 5,
518 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
519 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
520 .clkr.hw.init = &(struct clk_init_data){
521 .name = "blsp2_qup4_i2c_apps_clk_src",
522 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
523 .num_parents = 3,
524 .ops = &clk_rcg2_ops,
525 },
526};
527
528static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
529 .cmd_rcgr = 0x2c00c,
530 .mnd_width = 8,
531 .hid_width = 5,
532 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
533 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
534 .clkr.hw.init = &(struct clk_init_data){
535 .name = "blsp2_qup4_spi_apps_clk_src",
536 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
537 .num_parents = 3,
538 .ops = &clk_rcg2_ops,
539 },
540};
541
542static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
543 .cmd_rcgr = 0x2700c,
544 .mnd_width = 16,
545 .hid_width = 5,
546 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
547 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
548 .clkr.hw.init = &(struct clk_init_data){
549 .name = "blsp2_uart1_apps_clk_src",
550 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
551 .num_parents = 3,
552 .ops = &clk_rcg2_ops,
553 },
554};
555
556static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
557 .cmd_rcgr = 0x2900c,
558 .mnd_width = 16,
559 .hid_width = 5,
560 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
561 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
562 .clkr.hw.init = &(struct clk_init_data){
563 .name = "blsp2_uart2_apps_clk_src",
564 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
565 .num_parents = 3,
566 .ops = &clk_rcg2_ops,
567 },
568};
569
570static const struct freq_tbl ftbl_gp1_clk_src[] = {
571 F(19200000, P_XO, 1, 0, 0),
572 F(100000000, P_GPLL0, 6, 0, 0),
573 F(200000000, P_GPLL0, 3, 0, 0),
574 { }
575};
576
577static struct clk_rcg2 gp1_clk_src = {
578 .cmd_rcgr = 0x64004,
579 .mnd_width = 8,
580 .hid_width = 5,
581 .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
582 .freq_tbl = ftbl_gp1_clk_src,
583 .clkr.hw.init = &(struct clk_init_data){
584 .name = "gp1_clk_src",
585 .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
586 .num_parents = 4,
587 .ops = &clk_rcg2_ops,
588 },
589};
590
591static struct clk_rcg2 gp2_clk_src = {
592 .cmd_rcgr = 0x65004,
593 .mnd_width = 8,
594 .hid_width = 5,
595 .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
596 .freq_tbl = ftbl_gp1_clk_src,
597 .clkr.hw.init = &(struct clk_init_data){
598 .name = "gp2_clk_src",
599 .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
600 .num_parents = 4,
601 .ops = &clk_rcg2_ops,
602 },
603};
604
605static struct clk_rcg2 gp3_clk_src = {
606 .cmd_rcgr = 0x66004,
607 .mnd_width = 8,
608 .hid_width = 5,
609 .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
610 .freq_tbl = ftbl_gp1_clk_src,
611 .clkr.hw.init = &(struct clk_init_data){
612 .name = "gp3_clk_src",
613 .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
614 .num_parents = 4,
615 .ops = &clk_rcg2_ops,
616 },
617};
618
619static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
620 F(300000000, P_GPLL0, 2, 0, 0),
621 F(600000000, P_GPLL0, 1, 0, 0),
622 { }
623};
624
625static struct clk_rcg2 hmss_gpll0_clk_src = {
626 .cmd_rcgr = 0x4805c,
627 .mnd_width = 0,
628 .hid_width = 5,
629 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
630 .freq_tbl = ftbl_hmss_gpll0_clk_src,
631 .clkr.hw.init = &(struct clk_init_data){
632 .name = "hmss_gpll0_clk_src",
633 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
634 .num_parents = 3,
635 .ops = &clk_rcg2_ops,
636 },
637};
638
639static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = {
640 F(384000000, P_GPLL4, 4, 0, 0),
641 F(768000000, P_GPLL4, 2, 0, 0),
642 F(1536000000, P_GPLL4, 1, 0, 0),
643 { }
644};
645
646static struct clk_rcg2 hmss_gpll4_clk_src = {
647 .cmd_rcgr = 0x48074,
648 .mnd_width = 0,
649 .hid_width = 5,
650 .parent_map = gcc_parent_map_xo_gpll4,
651 .freq_tbl = ftbl_hmss_gpll4_clk_src,
652 .clkr.hw.init = &(struct clk_init_data){
653 .name = "hmss_gpll4_clk_src",
654 .parent_names = gcc_parent_names_xo_gpll4,
655 .num_parents = 2,
656 .ops = &clk_rcg2_ops,
657 },
658};
659
660static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
661 F(19200000, P_XO, 1, 0, 0),
662 { }
663};
664
665static struct clk_rcg2 hmss_rbcpr_clk_src = {
666 .cmd_rcgr = 0x48044,
667 .mnd_width = 0,
668 .hid_width = 5,
669 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
670 .freq_tbl = ftbl_hmss_rbcpr_clk_src,
671 .clkr.hw.init = &(struct clk_init_data){
672 .name = "hmss_rbcpr_clk_src",
673 .parent_names = gcc_parent_names_xo_gpll0,
674 .num_parents = 2,
675 .ops = &clk_rcg2_ops,
676 },
677};
678
679static const struct freq_tbl ftbl_pdm2_clk_src[] = {
680 F(60000000, P_GPLL0, 10, 0, 0),
681 { }
682};
683
684static struct clk_rcg2 pdm2_clk_src = {
685 .cmd_rcgr = 0x33010,
686 .mnd_width = 0,
687 .hid_width = 5,
688 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
689 .freq_tbl = ftbl_pdm2_clk_src,
690 .clkr.hw.init = &(struct clk_init_data){
691 .name = "pdm2_clk_src",
692 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
693 .num_parents = 3,
694 .ops = &clk_rcg2_ops,
695 },
696};
697
698static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
699 F(19200000, P_XO, 1, 0, 0),
700 F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0),
701 F(160400000, P_GPLL1, 5, 0, 0),
702 F(267333333, P_GPLL1, 3, 0, 0),
703 { }
704};
705
706static struct clk_rcg2 qspi_ser_clk_src = {
707 .cmd_rcgr = 0x4d00c,
708 .mnd_width = 0,
709 .hid_width = 5,
710 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
711 .freq_tbl = ftbl_qspi_ser_clk_src,
712 .clkr.hw.init = &(struct clk_init_data){
713 .name = "qspi_ser_clk_src",
714 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
715 .num_parents = 6,
716 .ops = &clk_rcg2_ops,
717 },
718};
719
720static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
721 F(144000, P_XO, 16, 3, 25),
722 F(400000, P_XO, 12, 1, 4),
723 F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
724 F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
725 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
726 F(100000000, P_GPLL0, 6, 0, 0),
727 F(192000000, P_GPLL4, 8, 0, 0),
728 F(384000000, P_GPLL4, 4, 0, 0),
729 { }
730};
731
732static struct clk_rcg2 sdcc1_apps_clk_src = {
733 .cmd_rcgr = 0x1602c,
734 .mnd_width = 8,
735 .hid_width = 5,
736 .parent_map = gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div,
737 .freq_tbl = ftbl_sdcc1_apps_clk_src,
738 .clkr.hw.init = &(struct clk_init_data){
739 .name = "sdcc1_apps_clk_src",
740 .parent_names = gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div,
741 .num_parents = 4,
742 .ops = &clk_rcg2_ops,
743 },
744};
745
746static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
747 F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
748 F(150000000, P_GPLL0, 4, 0, 0),
749 F(200000000, P_GPLL0, 3, 0, 0),
750 F(300000000, P_GPLL0, 2, 0, 0),
751 { }
752};
753
754static struct clk_rcg2 sdcc1_ice_core_clk_src = {
755 .cmd_rcgr = 0x16010,
756 .mnd_width = 0,
757 .hid_width = 5,
758 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
759 .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
760 .clkr.hw.init = &(struct clk_init_data){
761 .name = "sdcc1_ice_core_clk_src",
762 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
763 .num_parents = 3,
764 .ops = &clk_rcg2_ops,
765 },
766};
767
768static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
769 F(144000, P_XO, 16, 3, 25),
770 F(400000, P_XO, 12, 1, 4),
771 F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
772 F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
773 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
774 F(100000000, P_GPLL0, 6, 0, 0),
775 F(192000000, P_GPLL4, 8, 0, 0),
776 F(200000000, P_GPLL0, 3, 0, 0),
777 { }
778};
779
780static struct clk_rcg2 sdcc2_apps_clk_src = {
781 .cmd_rcgr = 0x14010,
782 .mnd_width = 8,
783 .hid_width = 5,
784 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4,
785 .freq_tbl = ftbl_sdcc2_apps_clk_src,
786 .clkr.hw.init = &(struct clk_init_data){
787 .name = "sdcc2_apps_clk_src",
788 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4,
789 .num_parents = 4,
790 .ops = &clk_rcg2_ops,
791 },
792};
793
794static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
795 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
796 F(100000000, P_GPLL0, 6, 0, 0),
797 F(150000000, P_GPLL0, 4, 0, 0),
798 F(200000000, P_GPLL0, 3, 0, 0),
799 F(240000000, P_GPLL0, 2.5, 0, 0),
800 { }
801};
802
803static struct clk_rcg2 ufs_axi_clk_src = {
804 .cmd_rcgr = 0x75018,
805 .mnd_width = 8,
806 .hid_width = 5,
807 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
808 .freq_tbl = ftbl_ufs_axi_clk_src,
809 .clkr.hw.init = &(struct clk_init_data){
810 .name = "ufs_axi_clk_src",
811 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
812 .num_parents = 3,
813 .ops = &clk_rcg2_ops,
814 },
815};
816
817static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
818 F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
819 F(150000000, P_GPLL0, 4, 0, 0),
820 F(300000000, P_GPLL0, 2, 0, 0),
821 { }
822};
823
824static struct clk_rcg2 ufs_ice_core_clk_src = {
825 .cmd_rcgr = 0x76010,
826 .mnd_width = 0,
827 .hid_width = 5,
828 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
829 .freq_tbl = ftbl_ufs_ice_core_clk_src,
830 .clkr.hw.init = &(struct clk_init_data){
831 .name = "ufs_ice_core_clk_src",
832 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
833 .num_parents = 3,
834 .ops = &clk_rcg2_ops,
835 },
836};
837
838static struct clk_rcg2 ufs_phy_aux_clk_src = {
839 .cmd_rcgr = 0x76044,
840 .mnd_width = 0,
841 .hid_width = 5,
842 .parent_map = gcc_parent_map_xo_sleep_clk,
843 .freq_tbl = ftbl_hmss_rbcpr_clk_src,
844 .clkr.hw.init = &(struct clk_init_data){
845 .name = "ufs_phy_aux_clk_src",
846 .parent_names = gcc_parent_names_xo_sleep_clk,
847 .num_parents = 2,
848 .ops = &clk_rcg2_ops,
849 },
850};
851
852static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {
853 F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0),
854 F(75000000, P_GPLL0, 8, 0, 0),
855 F(150000000, P_GPLL0, 4, 0, 0),
856 { }
857};
858
859static struct clk_rcg2 ufs_unipro_core_clk_src = {
860 .cmd_rcgr = 0x76028,
861 .mnd_width = 0,
862 .hid_width = 5,
863 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
864 .freq_tbl = ftbl_ufs_unipro_core_clk_src,
865 .clkr.hw.init = &(struct clk_init_data){
866 .name = "ufs_unipro_core_clk_src",
867 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
868 .num_parents = 3,
869 .ops = &clk_rcg2_ops,
870 },
871};
872
873static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
874 F(19200000, P_XO, 1, 0, 0),
875 F(60000000, P_GPLL0, 10, 0, 0),
876 F(120000000, P_GPLL0, 5, 0, 0),
877 { }
878};
879
880static struct clk_rcg2 usb20_master_clk_src = {
881 .cmd_rcgr = 0x2f010,
882 .mnd_width = 8,
883 .hid_width = 5,
884 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
885 .freq_tbl = ftbl_usb20_master_clk_src,
886 .clkr.hw.init = &(struct clk_init_data){
887 .name = "usb20_master_clk_src",
888 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
889 .num_parents = 3,
890 .ops = &clk_rcg2_ops,
891 },
892};
893
894static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] = {
895 F(19200000, P_XO, 1, 0, 0),
896 F(60000000, P_GPLL0, 10, 0, 0),
897 { }
898};
899
900static struct clk_rcg2 usb20_mock_utmi_clk_src = {
901 .cmd_rcgr = 0x2f024,
902 .mnd_width = 0,
903 .hid_width = 5,
904 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
905 .freq_tbl = ftbl_usb20_mock_utmi_clk_src,
906 .clkr.hw.init = &(struct clk_init_data){
907 .name = "usb20_mock_utmi_clk_src",
908 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
909 .num_parents = 3,
910 .ops = &clk_rcg2_ops,
911 },
912};
913
914static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
915 F(19200000, P_XO, 1, 0, 0),
916 F(66666667, P_GPLL0_EARLY_DIV, 4.5, 0, 0),
917 F(120000000, P_GPLL0, 5, 0, 0),
918 F(133333333, P_GPLL0, 4.5, 0, 0),
919 F(150000000, P_GPLL0, 4, 0, 0),
920 F(200000000, P_GPLL0, 3, 0, 0),
921 F(240000000, P_GPLL0, 2.5, 0, 0),
922 { }
923};
924
925static struct clk_rcg2 usb30_master_clk_src = {
926 .cmd_rcgr = 0xf014,
927 .mnd_width = 8,
928 .hid_width = 5,
929 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
930 .freq_tbl = ftbl_usb30_master_clk_src,
931 .clkr.hw.init = &(struct clk_init_data){
932 .name = "usb30_master_clk_src",
933 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
934 .num_parents = 3,
935 .ops = &clk_rcg2_ops,
936 },
937};
938
939static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
940 F(19200000, P_XO, 1, 0, 0),
941 F(40000000, P_GPLL0_EARLY_DIV, 7.5, 0, 0),
942 F(60000000, P_GPLL0, 10, 0, 0),
943 { }
944};
945
946static struct clk_rcg2 usb30_mock_utmi_clk_src = {
947 .cmd_rcgr = 0xf028,
948 .mnd_width = 0,
949 .hid_width = 5,
950 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
951 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
952 .clkr.hw.init = &(struct clk_init_data){
953 .name = "usb30_mock_utmi_clk_src",
954 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
955 .num_parents = 3,
956 .ops = &clk_rcg2_ops,
957 },
958};
959
960static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
961 F(1200000, P_XO, 16, 0, 0),
962 F(19200000, P_XO, 1, 0, 0),
963 { }
964};
965
966static struct clk_rcg2 usb3_phy_aux_clk_src = {
967 .cmd_rcgr = 0x5000c,
968 .mnd_width = 0,
969 .hid_width = 5,
970 .parent_map = gcc_parent_map_xo_sleep_clk,
971 .freq_tbl = ftbl_usb3_phy_aux_clk_src,
972 .clkr.hw.init = &(struct clk_init_data){
973 .name = "usb3_phy_aux_clk_src",
974 .parent_names = gcc_parent_names_xo_sleep_clk,
975 .num_parents = 2,
976 .ops = &clk_rcg2_ops,
977 },
978};
979
980static struct clk_branch gcc_aggre2_ufs_axi_clk = {
981 .halt_reg = 0x75034,
982 .halt_check = BRANCH_HALT,
983 .clkr = {
984 .enable_reg = 0x75034,
985 .enable_mask = BIT(0),
986 .hw.init = &(struct clk_init_data){
987 .name = "gcc_aggre2_ufs_axi_clk",
988 .parent_names = (const char *[]){
989 "ufs_axi_clk_src",
990 },
991 .num_parents = 1,
992 .ops = &clk_branch2_ops,
993 },
994 },
995};
996
997static struct clk_branch gcc_aggre2_usb3_axi_clk = {
998 .halt_reg = 0xf03c,
999 .halt_check = BRANCH_HALT,
1000 .clkr = {
1001 .enable_reg = 0xf03c,
1002 .enable_mask = BIT(0),
1003 .hw.init = &(struct clk_init_data){
1004 .name = "gcc_aggre2_usb3_axi_clk",
1005 .parent_names = (const char *[]){
1006 "usb30_master_clk_src",
1007 },
1008 .num_parents = 1,
1009 .ops = &clk_branch2_ops,
1010 },
1011 },
1012};
1013
1014static struct clk_branch gcc_bimc_gfx_clk = {
1015 .halt_reg = 0x7106c,
1016 .halt_check = BRANCH_VOTED,
1017 .clkr = {
1018 .enable_reg = 0x7106c,
1019 .enable_mask = BIT(0),
1020 .hw.init = &(struct clk_init_data){
1021 .name = "gcc_bimc_gfx_clk",
1022 .ops = &clk_branch2_ops,
1023 },
1024 },
1025};
1026
1027static struct clk_branch gcc_bimc_hmss_axi_clk = {
1028 .halt_reg = 0x48004,
1029 .halt_check = BRANCH_HALT_VOTED,
1030 .clkr = {
1031 .enable_reg = 0x52004,
1032 .enable_mask = BIT(22),
1033 .hw.init = &(struct clk_init_data){
1034 .name = "gcc_bimc_hmss_axi_clk",
1035 .ops = &clk_branch2_ops,
1036 },
1037 },
1038};
1039
1040static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
1041 .halt_reg = 0x4401c,
1042 .halt_check = BRANCH_HALT,
1043 .clkr = {
1044 .enable_reg = 0x4401c,
1045 .enable_mask = BIT(0),
1046 .hw.init = &(struct clk_init_data){
1047 .name = "gcc_bimc_mss_q6_axi_clk",
1048 .ops = &clk_branch2_ops,
1049 },
1050 },
1051};
1052
1053static struct clk_branch gcc_blsp1_ahb_clk = {
1054 .halt_reg = 0x17004,
1055 .halt_check = BRANCH_HALT_VOTED,
1056 .clkr = {
1057 .enable_reg = 0x52004,
1058 .enable_mask = BIT(17),
1059 .hw.init = &(struct clk_init_data){
1060 .name = "gcc_blsp1_ahb_clk",
1061 .ops = &clk_branch2_ops,
1062 },
1063 },
1064};
1065
1066static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1067 .halt_reg = 0x19008,
1068 .halt_check = BRANCH_HALT,
1069 .clkr = {
1070 .enable_reg = 0x19008,
1071 .enable_mask = BIT(0),
1072 .hw.init = &(struct clk_init_data){
1073 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1074 .parent_names = (const char *[]){
1075 "blsp1_qup1_i2c_apps_clk_src",
1076 },
1077 .num_parents = 1,
1078 .flags = CLK_SET_RATE_PARENT,
1079 .ops = &clk_branch2_ops,
1080 },
1081 },
1082};
1083
1084static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1085 .halt_reg = 0x19004,
1086 .halt_check = BRANCH_HALT,
1087 .clkr = {
1088 .enable_reg = 0x19004,
1089 .enable_mask = BIT(0),
1090 .hw.init = &(struct clk_init_data){
1091 .name = "gcc_blsp1_qup1_spi_apps_clk",
1092 .parent_names = (const char *[]){
1093 "blsp1_qup1_spi_apps_clk_src",
1094 },
1095 .num_parents = 1,
1096 .flags = CLK_SET_RATE_PARENT,
1097 .ops = &clk_branch2_ops,
1098 },
1099 },
1100};
1101
1102static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1103 .halt_reg = 0x1b008,
1104 .halt_check = BRANCH_HALT,
1105 .clkr = {
1106 .enable_reg = 0x1b008,
1107 .enable_mask = BIT(0),
1108 .hw.init = &(struct clk_init_data){
1109 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1110 .parent_names = (const char *[]){
1111 "blsp1_qup2_i2c_apps_clk_src",
1112 },
1113 .num_parents = 1,
1114 .flags = CLK_SET_RATE_PARENT,
1115 .ops = &clk_branch2_ops,
1116 },
1117 },
1118};
1119
1120static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1121 .halt_reg = 0x1b004,
1122 .halt_check = BRANCH_HALT,
1123 .clkr = {
1124 .enable_reg = 0x1b004,
1125 .enable_mask = BIT(0),
1126 .hw.init = &(struct clk_init_data){
1127 .name = "gcc_blsp1_qup2_spi_apps_clk",
1128 .parent_names = (const char *[]){
1129 "blsp1_qup2_spi_apps_clk_src",
1130 },
1131 .num_parents = 1,
1132 .flags = CLK_SET_RATE_PARENT,
1133 .ops = &clk_branch2_ops,
1134 },
1135 },
1136};
1137
1138static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1139 .halt_reg = 0x1d008,
1140 .halt_check = BRANCH_HALT,
1141 .clkr = {
1142 .enable_reg = 0x1d008,
1143 .enable_mask = BIT(0),
1144 .hw.init = &(struct clk_init_data){
1145 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1146 .parent_names = (const char *[]){
1147 "blsp1_qup3_i2c_apps_clk_src",
1148 },
1149 .num_parents = 1,
1150 .flags = CLK_SET_RATE_PARENT,
1151 .ops = &clk_branch2_ops,
1152 },
1153 },
1154};
1155
1156static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1157 .halt_reg = 0x1d004,
1158 .halt_check = BRANCH_HALT,
1159 .clkr = {
1160 .enable_reg = 0x1d004,
1161 .enable_mask = BIT(0),
1162 .hw.init = &(struct clk_init_data){
1163 .name = "gcc_blsp1_qup3_spi_apps_clk",
1164 .parent_names = (const char *[]){
1165 "blsp1_qup3_spi_apps_clk_src",
1166 },
1167 .num_parents = 1,
1168 .flags = CLK_SET_RATE_PARENT,
1169 .ops = &clk_branch2_ops,
1170 },
1171 },
1172};
1173
1174static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1175 .halt_reg = 0x1f008,
1176 .halt_check = BRANCH_HALT,
1177 .clkr = {
1178 .enable_reg = 0x1f008,
1179 .enable_mask = BIT(0),
1180 .hw.init = &(struct clk_init_data){
1181 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1182 .parent_names = (const char *[]){
1183 "blsp1_qup4_i2c_apps_clk_src",
1184 },
1185 .num_parents = 1,
1186 .flags = CLK_SET_RATE_PARENT,
1187 .ops = &clk_branch2_ops,
1188 },
1189 },
1190};
1191
1192static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1193 .halt_reg = 0x1f004,
1194 .halt_check = BRANCH_HALT,
1195 .clkr = {
1196 .enable_reg = 0x1f004,
1197 .enable_mask = BIT(0),
1198 .hw.init = &(struct clk_init_data){
1199 .name = "gcc_blsp1_qup4_spi_apps_clk",
1200 .parent_names = (const char *[]){
1201 "blsp1_qup4_spi_apps_clk_src",
1202 },
1203 .num_parents = 1,
1204 .flags = CLK_SET_RATE_PARENT,
1205 .ops = &clk_branch2_ops,
1206 },
1207 },
1208};
1209
1210static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1211 .halt_reg = 0x1a004,
1212 .halt_check = BRANCH_HALT,
1213 .clkr = {
1214 .enable_reg = 0x1a004,
1215 .enable_mask = BIT(0),
1216 .hw.init = &(struct clk_init_data){
1217 .name = "gcc_blsp1_uart1_apps_clk",
1218 .parent_names = (const char *[]){
1219 "blsp1_uart1_apps_clk_src",
1220 },
1221 .num_parents = 1,
1222 .flags = CLK_SET_RATE_PARENT,
1223 .ops = &clk_branch2_ops,
1224 },
1225 },
1226};
1227
1228static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1229 .halt_reg = 0x1c004,
1230 .halt_check = BRANCH_HALT,
1231 .clkr = {
1232 .enable_reg = 0x1c004,
1233 .enable_mask = BIT(0),
1234 .hw.init = &(struct clk_init_data){
1235 .name = "gcc_blsp1_uart2_apps_clk",
1236 .parent_names = (const char *[]){
1237 "blsp1_uart2_apps_clk_src",
1238 },
1239 .num_parents = 1,
1240 .flags = CLK_SET_RATE_PARENT,
1241 .ops = &clk_branch2_ops,
1242 },
1243 },
1244};
1245
1246static struct clk_branch gcc_blsp2_ahb_clk = {
1247 .halt_reg = 0x25004,
1248 .halt_check = BRANCH_HALT_VOTED,
1249 .clkr = {
1250 .enable_reg = 0x52004,
1251 .enable_mask = BIT(15),
1252 .hw.init = &(struct clk_init_data){
1253 .name = "gcc_blsp2_ahb_clk",
1254 .ops = &clk_branch2_ops,
1255 },
1256 },
1257};
1258
1259static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1260 .halt_reg = 0x26008,
1261 .halt_check = BRANCH_HALT,
1262 .clkr = {
1263 .enable_reg = 0x26008,
1264 .enable_mask = BIT(0),
1265 .hw.init = &(struct clk_init_data){
1266 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1267 .parent_names = (const char *[]){
1268 "blsp2_qup1_i2c_apps_clk_src",
1269 },
1270 .num_parents = 1,
1271 .flags = CLK_SET_RATE_PARENT,
1272 .ops = &clk_branch2_ops,
1273 },
1274 },
1275};
1276
1277static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1278 .halt_reg = 0x26004,
1279 .halt_check = BRANCH_HALT,
1280 .clkr = {
1281 .enable_reg = 0x26004,
1282 .enable_mask = BIT(0),
1283 .hw.init = &(struct clk_init_data){
1284 .name = "gcc_blsp2_qup1_spi_apps_clk",
1285 .parent_names = (const char *[]){
1286 "blsp2_qup1_spi_apps_clk_src",
1287 },
1288 .num_parents = 1,
1289 .flags = CLK_SET_RATE_PARENT,
1290 .ops = &clk_branch2_ops,
1291 },
1292 },
1293};
1294
1295static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1296 .halt_reg = 0x28008,
1297 .halt_check = BRANCH_HALT,
1298 .clkr = {
1299 .enable_reg = 0x28008,
1300 .enable_mask = BIT(0),
1301 .hw.init = &(struct clk_init_data){
1302 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1303 .parent_names = (const char *[]){
1304 "blsp2_qup2_i2c_apps_clk_src",
1305 },
1306 .num_parents = 1,
1307 .flags = CLK_SET_RATE_PARENT,
1308 .ops = &clk_branch2_ops,
1309 },
1310 },
1311};
1312
1313static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1314 .halt_reg = 0x28004,
1315 .halt_check = BRANCH_HALT,
1316 .clkr = {
1317 .enable_reg = 0x28004,
1318 .enable_mask = BIT(0),
1319 .hw.init = &(struct clk_init_data){
1320 .name = "gcc_blsp2_qup2_spi_apps_clk",
1321 .parent_names = (const char *[]){
1322 "blsp2_qup2_spi_apps_clk_src",
1323 },
1324 .num_parents = 1,
1325 .flags = CLK_SET_RATE_PARENT,
1326 .ops = &clk_branch2_ops,
1327 },
1328 },
1329};
1330
1331static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1332 .halt_reg = 0x2a008,
1333 .halt_check = BRANCH_HALT,
1334 .clkr = {
1335 .enable_reg = 0x2a008,
1336 .enable_mask = BIT(0),
1337 .hw.init = &(struct clk_init_data){
1338 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1339 .parent_names = (const char *[]){
1340 "blsp2_qup3_i2c_apps_clk_src",
1341 },
1342 .num_parents = 1,
1343 .flags = CLK_SET_RATE_PARENT,
1344 .ops = &clk_branch2_ops,
1345 },
1346 },
1347};
1348
1349static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1350 .halt_reg = 0x2a004,
1351 .halt_check = BRANCH_HALT,
1352 .clkr = {
1353 .enable_reg = 0x2a004,
1354 .enable_mask = BIT(0),
1355 .hw.init = &(struct clk_init_data){
1356 .name = "gcc_blsp2_qup3_spi_apps_clk",
1357 .parent_names = (const char *[]){
1358 "blsp2_qup3_spi_apps_clk_src",
1359 },
1360 .num_parents = 1,
1361 .flags = CLK_SET_RATE_PARENT,
1362 .ops = &clk_branch2_ops,
1363 },
1364 },
1365};
1366
1367static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1368 .halt_reg = 0x2c008,
1369 .halt_check = BRANCH_HALT,
1370 .clkr = {
1371 .enable_reg = 0x2c008,
1372 .enable_mask = BIT(0),
1373 .hw.init = &(struct clk_init_data){
1374 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1375 .parent_names = (const char *[]){
1376 "blsp2_qup4_i2c_apps_clk_src",
1377 },
1378 .num_parents = 1,
1379 .flags = CLK_SET_RATE_PARENT,
1380 .ops = &clk_branch2_ops,
1381 },
1382 },
1383};
1384
1385static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1386 .halt_reg = 0x2c004,
1387 .halt_check = BRANCH_HALT,
1388 .clkr = {
1389 .enable_reg = 0x2c004,
1390 .enable_mask = BIT(0),
1391 .hw.init = &(struct clk_init_data){
1392 .name = "gcc_blsp2_qup4_spi_apps_clk",
1393 .parent_names = (const char *[]){
1394 "blsp2_qup4_spi_apps_clk_src",
1395 },
1396 .num_parents = 1,
1397 .flags = CLK_SET_RATE_PARENT,
1398 .ops = &clk_branch2_ops,
1399 },
1400 },
1401};
1402
1403static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1404 .halt_reg = 0x27004,
1405 .halt_check = BRANCH_HALT,
1406 .clkr = {
1407 .enable_reg = 0x27004,
1408 .enable_mask = BIT(0),
1409 .hw.init = &(struct clk_init_data){
1410 .name = "gcc_blsp2_uart1_apps_clk",
1411 .parent_names = (const char *[]){
1412 "blsp2_uart1_apps_clk_src",
1413 },
1414 .num_parents = 1,
1415 .flags = CLK_SET_RATE_PARENT,
1416 .ops = &clk_branch2_ops,
1417 },
1418 },
1419};
1420
1421static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1422 .halt_reg = 0x29004,
1423 .halt_check = BRANCH_HALT,
1424 .clkr = {
1425 .enable_reg = 0x29004,
1426 .enable_mask = BIT(0),
1427 .hw.init = &(struct clk_init_data){
1428 .name = "gcc_blsp2_uart2_apps_clk",
1429 .parent_names = (const char *[]){
1430 "blsp2_uart2_apps_clk_src",
1431 },
1432 .num_parents = 1,
1433 .flags = CLK_SET_RATE_PARENT,
1434 .ops = &clk_branch2_ops,
1435 },
1436 },
1437};
1438
1439static struct clk_branch gcc_boot_rom_ahb_clk = {
1440 .halt_reg = 0x38004,
1441 .halt_check = BRANCH_HALT_VOTED,
1442 .clkr = {
1443 .enable_reg = 0x52004,
1444 .enable_mask = BIT(10),
1445 .hw.init = &(struct clk_init_data){
1446 .name = "gcc_boot_rom_ahb_clk",
1447 .ops = &clk_branch2_ops,
1448 },
1449 },
1450};
1451
1452static struct clk_branch gcc_cfg_noc_usb2_axi_clk = {
1453 .halt_reg = 0x5058,
1454 .halt_check = BRANCH_HALT,
1455 .clkr = {
1456 .enable_reg = 0x5058,
1457 .enable_mask = BIT(0),
1458 .hw.init = &(struct clk_init_data){
1459 .name = "gcc_cfg_noc_usb2_axi_clk",
1460 .parent_names = (const char *[]){
1461 "usb20_master_clk_src",
1462 },
1463 .num_parents = 1,
1464 .ops = &clk_branch2_ops,
1465 },
1466 },
1467};
1468
1469static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
1470 .halt_reg = 0x5018,
1471 .halt_check = BRANCH_HALT,
1472 .clkr = {
1473 .enable_reg = 0x5018,
1474 .enable_mask = BIT(0),
1475 .hw.init = &(struct clk_init_data){
1476 .name = "gcc_cfg_noc_usb3_axi_clk",
1477 .parent_names = (const char *[]){
1478 "usb30_master_clk_src",
1479 },
1480 .num_parents = 1,
1481 .ops = &clk_branch2_ops,
1482 },
1483 },
1484};
1485
1486static struct clk_branch gcc_dcc_ahb_clk = {
1487 .halt_reg = 0x84004,
1488 .clkr = {
1489 .enable_reg = 0x84004,
1490 .enable_mask = BIT(0),
1491 .hw.init = &(struct clk_init_data){
1492 .name = "gcc_dcc_ahb_clk",
1493 .ops = &clk_branch2_ops,
1494 },
1495 },
1496};
1497
1498static struct clk_branch gcc_gp1_clk = {
1499 .halt_reg = 0x64000,
1500 .halt_check = BRANCH_HALT,
1501 .clkr = {
1502 .enable_reg = 0x64000,
1503 .enable_mask = BIT(0),
1504 .hw.init = &(struct clk_init_data){
1505 .name = "gcc_gp1_clk",
1506 .parent_names = (const char *[]){
1507 "gp1_clk_src",
1508 },
1509 .num_parents = 1,
1510 .flags = CLK_SET_RATE_PARENT,
1511 .ops = &clk_branch2_ops,
1512 },
1513 },
1514};
1515
1516static struct clk_branch gcc_gp2_clk = {
1517 .halt_reg = 0x65000,
1518 .halt_check = BRANCH_HALT,
1519 .clkr = {
1520 .enable_reg = 0x65000,
1521 .enable_mask = BIT(0),
1522 .hw.init = &(struct clk_init_data){
1523 .name = "gcc_gp2_clk",
1524 .parent_names = (const char *[]){
1525 "gp2_clk_src",
1526 },
1527 .num_parents = 1,
1528 .flags = CLK_SET_RATE_PARENT,
1529 .ops = &clk_branch2_ops,
1530 },
1531 },
1532};
1533
1534static struct clk_branch gcc_gp3_clk = {
1535 .halt_reg = 0x66000,
1536 .halt_check = BRANCH_HALT,
1537 .clkr = {
1538 .enable_reg = 0x66000,
1539 .enable_mask = BIT(0),
1540 .hw.init = &(struct clk_init_data){
1541 .name = "gcc_gp3_clk",
1542 .parent_names = (const char *[]){
1543 "gp3_clk_src",
1544 },
1545 .num_parents = 1,
1546 .flags = CLK_SET_RATE_PARENT,
1547 .ops = &clk_branch2_ops,
1548 },
1549 },
1550};
1551
1552static struct clk_branch gcc_gpu_bimc_gfx_clk = {
1553 .halt_reg = 0x71010,
1554 .halt_check = BRANCH_VOTED,
1555 .clkr = {
1556 .enable_reg = 0x71010,
1557 .enable_mask = BIT(0),
1558 .hw.init = &(struct clk_init_data){
1559 .name = "gcc_gpu_bimc_gfx_clk",
1560 .ops = &clk_branch2_ops,
1561 },
1562 },
1563};
1564
1565static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1566 .halt_reg = 0x71004,
1567 .halt_check = BRANCH_VOTED,
1568 .clkr = {
1569 .enable_reg = 0x71004,
1570 .enable_mask = BIT(0),
1571 .hw.init = &(struct clk_init_data){
1572 .name = "gcc_gpu_cfg_ahb_clk",
1573 .ops = &clk_branch2_ops,
1574 },
1575 },
1576};
1577
1578static struct clk_branch gcc_gpu_gpll0_clk = {
1579 .halt_reg = 0x5200c,
1580 .halt_check = BRANCH_HALT_DELAY,
1581 .clkr = {
1582 .enable_reg = 0x5200c,
1583 .enable_mask = BIT(4),
1584 .hw.init = &(struct clk_init_data){
1585 .name = "gcc_gpu_gpll0_clk",
1586 .parent_names = (const char *[]){
1587 "gpll0",
1588 },
1589 .num_parents = 1,
1590 .ops = &clk_branch2_ops,
1591 },
1592 },
1593};
1594
1595static struct clk_branch gcc_gpu_gpll0_div_clk = {
1596 .halt_reg = 0x5200c,
1597 .halt_check = BRANCH_HALT_DELAY,
1598 .clkr = {
1599 .enable_reg = 0x5200c,
1600 .enable_mask = BIT(3),
1601 .hw.init = &(struct clk_init_data){
1602 .name = "gcc_gpu_gpll0_div_clk",
1603 .parent_names = (const char *[]){
1604 "gpll0_early_div",
1605 },
1606 .num_parents = 1,
1607 .ops = &clk_branch2_ops,
1608 },
1609 },
1610};
1611
1612static struct clk_branch gcc_hmss_dvm_bus_clk = {
1613 .halt_reg = 0x4808c,
1614 .halt_check = BRANCH_HALT,
1615 .clkr = {
1616 .enable_reg = 0x4808c,
1617 .enable_mask = BIT(0),
1618 .hw.init = &(struct clk_init_data){
1619 .name = "gcc_hmss_dvm_bus_clk",
1620 .ops = &clk_branch2_ops,
1621 .flags = CLK_IGNORE_UNUSED,
1622 },
1623 },
1624};
1625
1626static struct clk_branch gcc_hmss_rbcpr_clk = {
1627 .halt_reg = 0x48008,
1628 .halt_check = BRANCH_HALT,
1629 .clkr = {
1630 .enable_reg = 0x48008,
1631 .enable_mask = BIT(0),
1632 .hw.init = &(struct clk_init_data){
1633 .name = "gcc_hmss_rbcpr_clk",
1634 .parent_names = (const char *[]){
1635 "hmss_rbcpr_clk_src",
1636 },
1637 .num_parents = 1,
1638 .flags = CLK_SET_RATE_PARENT,
1639 .ops = &clk_branch2_ops,
1640 },
1641 },
1642};
1643
1644static struct clk_branch gcc_mmss_gpll0_clk = {
1645 .halt_reg = 0x5200c,
1646 .halt_check = BRANCH_HALT_DELAY,
1647 .clkr = {
1648 .enable_reg = 0x5200c,
1649 .enable_mask = BIT(1),
1650 .hw.init = &(struct clk_init_data){
1651 .name = "gcc_mmss_gpll0_clk",
1652 .parent_names = (const char *[]){
1653 "gpll0",
1654 },
1655 .num_parents = 1,
1656 .ops = &clk_branch2_ops,
1657 },
1658 },
1659};
1660
1661static struct clk_branch gcc_mmss_gpll0_div_clk = {
1662 .halt_reg = 0x5200c,
1663 .halt_check = BRANCH_HALT_DELAY,
1664 .clkr = {
1665 .enable_reg = 0x5200c,
1666 .enable_mask = BIT(0),
1667 .hw.init = &(struct clk_init_data){
1668 .name = "gcc_mmss_gpll0_div_clk",
1669 .parent_names = (const char *[]){
1670 "gpll0_early_div",
1671 },
1672 .num_parents = 1,
1673 .ops = &clk_branch2_ops,
1674 },
1675 },
1676};
1677
1678static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1679 .halt_reg = 0x9004,
1680 .halt_check = BRANCH_HALT,
1681 .clkr = {
1682 .enable_reg = 0x9004,
1683 .enable_mask = BIT(0),
1684 .hw.init = &(struct clk_init_data){
1685 .name = "gcc_mmss_noc_cfg_ahb_clk",
1686 .ops = &clk_branch2_ops,
1687 },
1688 },
1689};
1690
1691static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
1692 .halt_reg = 0x9000,
1693 .halt_check = BRANCH_HALT,
1694 .clkr = {
1695 .enable_reg = 0x9000,
1696 .enable_mask = BIT(0),
1697 .hw.init = &(struct clk_init_data){
1698 .name = "gcc_mmss_sys_noc_axi_clk",
1699 .ops = &clk_branch2_ops,
1700 },
1701 },
1702};
1703
1704static struct clk_branch gcc_mss_cfg_ahb_clk = {
1705 .halt_reg = 0x8a000,
1706 .clkr = {
1707 .enable_reg = 0x8a000,
1708 .enable_mask = BIT(0),
1709 .hw.init = &(struct clk_init_data){
1710 .name = "gcc_mss_cfg_ahb_clk",
1711 .ops = &clk_branch2_ops,
1712 },
1713 },
1714};
1715
1716static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
1717 .halt_reg = 0x8a004,
1718 .clkr = {
1719 .enable_reg = 0x8a004,
1720 .enable_mask = BIT(0),
1721 .hw.init = &(struct clk_init_data){
1722 .name = "gcc_mss_mnoc_bimc_axi_clk",
1723 .ops = &clk_branch2_ops,
1724 },
1725 },
1726};
1727
1728static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
1729 .halt_reg = 0x8a040,
1730 .clkr = {
1731 .enable_reg = 0x8a040,
1732 .enable_mask = BIT(0),
1733 .hw.init = &(struct clk_init_data){
1734 .name = "gcc_mss_q6_bimc_axi_clk",
1735 .ops = &clk_branch2_ops,
1736 },
1737 },
1738};
1739
1740static struct clk_branch gcc_mss_snoc_axi_clk = {
1741 .halt_reg = 0x8a03c,
1742 .clkr = {
1743 .enable_reg = 0x8a03c,
1744 .enable_mask = BIT(0),
1745 .hw.init = &(struct clk_init_data){
1746 .name = "gcc_mss_snoc_axi_clk",
1747 .ops = &clk_branch2_ops,
1748 },
1749 },
1750};
1751
1752static struct clk_branch gcc_pdm2_clk = {
1753 .halt_reg = 0x3300c,
1754 .halt_check = BRANCH_HALT,
1755 .clkr = {
1756 .enable_reg = 0x3300c,
1757 .enable_mask = BIT(0),
1758 .hw.init = &(struct clk_init_data){
1759 .name = "gcc_pdm2_clk",
1760 .parent_names = (const char *[]){
1761 "pdm2_clk_src",
1762 },
1763 .num_parents = 1,
1764 .flags = CLK_SET_RATE_PARENT,
1765 .ops = &clk_branch2_ops,
1766 },
1767 },
1768};
1769
1770static struct clk_branch gcc_pdm_ahb_clk = {
1771 .halt_reg = 0x33004,
1772 .halt_check = BRANCH_HALT,
1773 .clkr = {
1774 .enable_reg = 0x33004,
1775 .enable_mask = BIT(0),
1776 .hw.init = &(struct clk_init_data){
1777 .name = "gcc_pdm_ahb_clk",
1778 .ops = &clk_branch2_ops,
1779 },
1780 },
1781};
1782
1783static struct clk_branch gcc_prng_ahb_clk = {
1784 .halt_reg = 0x34004,
1785 .halt_check = BRANCH_HALT_VOTED,
1786 .clkr = {
1787 .enable_reg = 0x52004,
1788 .enable_mask = BIT(13),
1789 .hw.init = &(struct clk_init_data){
1790 .name = "gcc_prng_ahb_clk",
1791 .ops = &clk_branch2_ops,
1792 },
1793 },
1794};
1795
1796static struct clk_branch gcc_qspi_ahb_clk = {
1797 .halt_reg = 0x4d004,
1798 .halt_check = BRANCH_HALT,
1799 .clkr = {
1800 .enable_reg = 0x4d004,
1801 .enable_mask = BIT(0),
1802 .hw.init = &(struct clk_init_data){
1803 .name = "gcc_qspi_ahb_clk",
1804 .ops = &clk_branch2_ops,
1805 },
1806 },
1807};
1808
1809static struct clk_branch gcc_qspi_ser_clk = {
1810 .halt_reg = 0x4d008,
1811 .halt_check = BRANCH_HALT,
1812 .clkr = {
1813 .enable_reg = 0x4d008,
1814 .enable_mask = BIT(0),
1815 .hw.init = &(struct clk_init_data){
1816 .name = "gcc_qspi_ser_clk",
1817 .parent_names = (const char *[]){
1818 "qspi_ser_clk_src",
1819 },
1820 .num_parents = 1,
1821 .flags = CLK_SET_RATE_PARENT,
1822 .ops = &clk_branch2_ops,
1823 },
1824 },
1825};
1826
1827static struct clk_branch gcc_rx0_usb2_clkref_clk = {
1828 .halt_reg = 0x88018,
1829 .halt_check = BRANCH_HALT_VOTED,
1830 .clkr = {
1831 .enable_reg = 0x88018,
1832 .enable_mask = BIT(0),
1833 .hw.init = &(struct clk_init_data){
1834 .name = "gcc_rx0_usb2_clkref_clk",
1835 .ops = &clk_branch2_ops,
1836 },
1837 },
1838};
1839
1840static struct clk_branch gcc_rx1_usb2_clkref_clk = {
1841 .halt_reg = 0x88014,
1842 .halt_check = BRANCH_HALT_VOTED,
1843 .clkr = {
1844 .enable_reg = 0x88014,
1845 .enable_mask = BIT(0),
1846 .hw.init = &(struct clk_init_data){
1847 .name = "gcc_rx1_usb2_clkref_clk",
1848 .ops = &clk_branch2_ops,
1849 },
1850 },
1851};
1852
1853static struct clk_branch gcc_sdcc1_ahb_clk = {
1854 .halt_reg = 0x16008,
1855 .halt_check = BRANCH_HALT,
1856 .clkr = {
1857 .enable_reg = 0x16008,
1858 .enable_mask = BIT(0),
1859 .hw.init = &(struct clk_init_data){
1860 .name = "gcc_sdcc1_ahb_clk",
1861 .ops = &clk_branch2_ops,
1862 },
1863 },
1864};
1865
1866static struct clk_branch gcc_sdcc1_apps_clk = {
1867 .halt_reg = 0x16004,
1868 .halt_check = BRANCH_HALT,
1869 .clkr = {
1870 .enable_reg = 0x16004,
1871 .enable_mask = BIT(0),
1872 .hw.init = &(struct clk_init_data){
1873 .name = "gcc_sdcc1_apps_clk",
1874 .parent_names = (const char *[]){
1875 "sdcc1_apps_clk_src",
1876 },
1877 .num_parents = 1,
1878 .flags = CLK_SET_RATE_PARENT,
1879 .ops = &clk_branch2_ops,
1880 },
1881 },
1882};
1883
1884static struct clk_branch gcc_sdcc1_ice_core_clk = {
1885 .halt_reg = 0x1600c,
1886 .halt_check = BRANCH_HALT,
1887 .clkr = {
1888 .enable_reg = 0x1600c,
1889 .enable_mask = BIT(0),
1890 .hw.init = &(struct clk_init_data){
1891 .name = "gcc_sdcc1_ice_core_clk",
1892 .parent_names = (const char *[]){
1893 "sdcc1_ice_core_clk_src",
1894 },
1895 .num_parents = 1,
1896 .flags = CLK_SET_RATE_PARENT,
1897 .ops = &clk_branch2_ops,
1898 },
1899 },
1900};
1901
1902static struct clk_branch gcc_sdcc2_ahb_clk = {
1903 .halt_reg = 0x14008,
1904 .halt_check = BRANCH_HALT,
1905 .clkr = {
1906 .enable_reg = 0x14008,
1907 .enable_mask = BIT(0),
1908 .hw.init = &(struct clk_init_data){
1909 .name = "gcc_sdcc2_ahb_clk",
1910 .ops = &clk_branch2_ops,
1911 },
1912 },
1913};
1914
1915static struct clk_branch gcc_sdcc2_apps_clk = {
1916 .halt_reg = 0x14004,
1917 .halt_check = BRANCH_HALT,
1918 .clkr = {
1919 .enable_reg = 0x14004,
1920 .enable_mask = BIT(0),
1921 .hw.init = &(struct clk_init_data){
1922 .name = "gcc_sdcc2_apps_clk",
1923 .parent_names = (const char *[]){
1924 "sdcc2_apps_clk_src",
1925 },
1926 .num_parents = 1,
1927 .flags = CLK_SET_RATE_PARENT,
1928 .ops = &clk_branch2_ops,
1929 },
1930 },
1931};
1932
1933static struct clk_branch gcc_ufs_ahb_clk = {
1934 .halt_reg = 0x7500c,
1935 .halt_check = BRANCH_HALT,
1936 .clkr = {
1937 .enable_reg = 0x7500c,
1938 .enable_mask = BIT(0),
1939 .hw.init = &(struct clk_init_data){
1940 .name = "gcc_ufs_ahb_clk",
1941 .ops = &clk_branch2_ops,
1942 },
1943 },
1944};
1945
1946static struct clk_branch gcc_ufs_axi_clk = {
1947 .halt_reg = 0x75008,
1948 .halt_check = BRANCH_HALT,
1949 .clkr = {
1950 .enable_reg = 0x75008,
1951 .enable_mask = BIT(0),
1952 .hw.init = &(struct clk_init_data){
1953 .name = "gcc_ufs_axi_clk",
1954 .parent_names = (const char *[]){
1955 "ufs_axi_clk_src",
1956 },
1957 .num_parents = 1,
1958 .flags = CLK_SET_RATE_PARENT,
1959 .ops = &clk_branch2_ops,
1960 },
1961 },
1962};
1963
1964static struct clk_branch gcc_ufs_clkref_clk = {
1965 .halt_reg = 0x88008,
1966 .halt_check = BRANCH_HALT,
1967 .clkr = {
1968 .enable_reg = 0x88008,
1969 .enable_mask = BIT(0),
1970 .hw.init = &(struct clk_init_data){
1971 .name = "gcc_ufs_clkref_clk",
1972 .ops = &clk_branch2_ops,
1973 },
1974 },
1975};
1976
1977static struct clk_branch gcc_ufs_ice_core_clk = {
1978 .halt_reg = 0x7600c,
1979 .halt_check = BRANCH_HALT,
1980 .clkr = {
1981 .enable_reg = 0x7600c,
1982 .enable_mask = BIT(0),
1983 .hw.init = &(struct clk_init_data){
1984 .name = "gcc_ufs_ice_core_clk",
1985 .parent_names = (const char *[]){
1986 "ufs_ice_core_clk_src",
1987 },
1988 .num_parents = 1,
1989 .flags = CLK_SET_RATE_PARENT,
1990 .ops = &clk_branch2_ops,
1991 },
1992 },
1993};
1994
1995static struct clk_branch gcc_ufs_phy_aux_clk = {
1996 .halt_reg = 0x76040,
1997 .halt_check = BRANCH_HALT,
1998 .clkr = {
1999 .enable_reg = 0x76040,
2000 .enable_mask = BIT(0),
2001 .hw.init = &(struct clk_init_data){
2002 .name = "gcc_ufs_phy_aux_clk",
2003 .parent_names = (const char *[]){
2004 "ufs_phy_aux_clk_src",
2005 },
2006 .num_parents = 1,
2007 .flags = CLK_SET_RATE_PARENT,
2008 .ops = &clk_branch2_ops,
2009 },
2010 },
2011};
2012
2013static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2014 .halt_reg = 0x75014,
2015 .halt_check = BRANCH_HALT_SKIP,
2016 .clkr = {
2017 .enable_reg = 0x75014,
2018 .enable_mask = BIT(0),
2019 .hw.init = &(struct clk_init_data){
2020 .name = "gcc_ufs_rx_symbol_0_clk",
2021 .ops = &clk_branch2_ops,
2022 },
2023 },
2024};
2025
2026static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2027 .halt_reg = 0x7605c,
2028 .halt_check = BRANCH_HALT_SKIP,
2029 .clkr = {
2030 .enable_reg = 0x7605c,
2031 .enable_mask = BIT(0),
2032 .hw.init = &(struct clk_init_data){
2033 .name = "gcc_ufs_rx_symbol_1_clk",
2034 .ops = &clk_branch2_ops,
2035 },
2036 },
2037};
2038
2039static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2040 .halt_reg = 0x75010,
2041 .halt_check = BRANCH_HALT_SKIP,
2042 .clkr = {
2043 .enable_reg = 0x75010,
2044 .enable_mask = BIT(0),
2045 .hw.init = &(struct clk_init_data){
2046 .name = "gcc_ufs_tx_symbol_0_clk",
2047 .ops = &clk_branch2_ops,
2048 },
2049 },
2050};
2051
2052static struct clk_branch gcc_ufs_unipro_core_clk = {
2053 .halt_reg = 0x76008,
2054 .halt_check = BRANCH_HALT,
2055 .clkr = {
2056 .enable_reg = 0x76008,
2057 .enable_mask = BIT(0),
2058 .hw.init = &(struct clk_init_data){
2059 .name = "gcc_ufs_unipro_core_clk",
2060 .parent_names = (const char *[]){
2061 "ufs_unipro_core_clk_src",
2062 },
2063 .flags = CLK_SET_RATE_PARENT,
2064 .num_parents = 1,
2065 .ops = &clk_branch2_ops,
2066 },
2067 },
2068};
2069
2070static struct clk_branch gcc_usb20_master_clk = {
2071 .halt_reg = 0x2f004,
2072 .halt_check = BRANCH_HALT,
2073 .clkr = {
2074 .enable_reg = 0x2f004,
2075 .enable_mask = BIT(0),
2076 .hw.init = &(struct clk_init_data){
2077 .name = "gcc_usb20_master_clk",
2078 .parent_names = (const char *[]){
2079 "usb20_master_clk_src"
2080 },
2081 .flags = CLK_SET_RATE_PARENT,
2082 .num_parents = 1,
2083 .ops = &clk_branch2_ops,
2084 },
2085 },
2086};
2087
2088static struct clk_branch gcc_usb20_mock_utmi_clk = {
2089 .halt_reg = 0x2f00c,
2090 .halt_check = BRANCH_HALT,
2091 .clkr = {
2092 .enable_reg = 0x2f00c,
2093 .enable_mask = BIT(0),
2094 .hw.init = &(struct clk_init_data){
2095 .name = "gcc_usb20_mock_utmi_clk",
2096 .parent_names = (const char *[]){
2097 "usb20_mock_utmi_clk_src",
2098 },
2099 .num_parents = 1,
2100 .flags = CLK_SET_RATE_PARENT,
2101 .ops = &clk_branch2_ops,
2102 },
2103 },
2104};
2105
2106static struct clk_branch gcc_usb20_sleep_clk = {
2107 .halt_reg = 0x2f008,
2108 .halt_check = BRANCH_HALT,
2109 .clkr = {
2110 .enable_reg = 0x2f008,
2111 .enable_mask = BIT(0),
2112 .hw.init = &(struct clk_init_data){
2113 .name = "gcc_usb20_sleep_clk",
2114 .ops = &clk_branch2_ops,
2115 },
2116 },
2117};
2118
2119static struct clk_branch gcc_usb30_master_clk = {
2120 .halt_reg = 0xf008,
2121 .halt_check = BRANCH_HALT,
2122 .clkr = {
2123 .enable_reg = 0xf008,
2124 .enable_mask = BIT(0),
2125 .hw.init = &(struct clk_init_data){
2126 .name = "gcc_usb30_master_clk",
2127 .parent_names = (const char *[]){
2128 "usb30_master_clk_src",
2129 },
2130 .num_parents = 1,
2131 .flags = CLK_SET_RATE_PARENT,
2132 .ops = &clk_branch2_ops,
2133 },
2134 },
2135};
2136
2137static struct clk_branch gcc_usb30_mock_utmi_clk = {
2138 .halt_reg = 0xf010,
2139 .halt_check = BRANCH_HALT,
2140 .clkr = {
2141 .enable_reg = 0xf010,
2142 .enable_mask = BIT(0),
2143 .hw.init = &(struct clk_init_data){
2144 .name = "gcc_usb30_mock_utmi_clk",
2145 .parent_names = (const char *[]){
2146 "usb30_mock_utmi_clk_src",
2147 },
2148 .num_parents = 1,
2149 .flags = CLK_SET_RATE_PARENT,
2150 .ops = &clk_branch2_ops,
2151 },
2152 },
2153};
2154
2155static struct clk_branch gcc_usb30_sleep_clk = {
2156 .halt_reg = 0xf00c,
2157 .halt_check = BRANCH_HALT,
2158 .clkr = {
2159 .enable_reg = 0xf00c,
2160 .enable_mask = BIT(0),
2161 .hw.init = &(struct clk_init_data){
2162 .name = "gcc_usb30_sleep_clk",
2163 .ops = &clk_branch2_ops,
2164 },
2165 },
2166};
2167
2168static struct clk_branch gcc_usb3_clkref_clk = {
2169 .halt_reg = 0x8800c,
2170 .halt_check = BRANCH_HALT,
2171 .clkr = {
2172 .enable_reg = 0x8800c,
2173 .enable_mask = BIT(0),
2174 .hw.init = &(struct clk_init_data){
2175 .name = "gcc_usb3_clkref_clk",
2176 .ops = &clk_branch2_ops,
2177 },
2178 },
2179};
2180
2181static struct clk_branch gcc_usb3_phy_aux_clk = {
2182 .halt_reg = 0x50000,
2183 .halt_check = BRANCH_HALT,
2184 .clkr = {
2185 .enable_reg = 0x50000,
2186 .enable_mask = BIT(0),
2187 .hw.init = &(struct clk_init_data){
2188 .name = "gcc_usb3_phy_aux_clk",
2189 .parent_names = (const char *[]){
2190 "usb3_phy_aux_clk_src",
2191 },
2192 .num_parents = 1,
2193 .flags = CLK_SET_RATE_PARENT,
2194 .ops = &clk_branch2_ops,
2195 },
2196 },
2197};
2198
2199static struct clk_branch gcc_usb3_phy_pipe_clk = {
2200 .halt_reg = 0x50004,
2201 .halt_check = BRANCH_HALT_DELAY,
2202 .clkr = {
2203 .enable_reg = 0x50004,
2204 .enable_mask = BIT(0),
2205 .hw.init = &(struct clk_init_data){
2206 .name = "gcc_usb3_phy_pipe_clk",
2207 .ops = &clk_branch2_ops,
2208 },
2209 },
2210};
2211
2212static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2213 .halt_reg = 0x6a004,
2214 .halt_check = BRANCH_HALT,
2215 .clkr = {
2216 .enable_reg = 0x6a004,
2217 .enable_mask = BIT(0),
2218 .hw.init = &(struct clk_init_data){
2219 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2220 .ops = &clk_branch2_ops,
2221 },
2222 },
2223};
2224
2225static struct gdsc ufs_gdsc = {
2226 .gdscr = 0x75004,
2227 .gds_hw_ctrl = 0x0,
2228 .pd = {
2229 .name = "ufs_gdsc",
2230 },
2231 .pwrsts = PWRSTS_OFF_ON,
2232 .flags = VOTABLE,
2233};
2234
2235static struct gdsc usb_30_gdsc = {
2236 .gdscr = 0xf004,
2237 .gds_hw_ctrl = 0x0,
2238 .pd = {
2239 .name = "usb_30_gdsc",
2240 },
2241 .pwrsts = PWRSTS_OFF_ON,
2242 .flags = VOTABLE,
2243};
2244
2245static struct gdsc pcie_0_gdsc = {
2246 .gdscr = 0x6b004,
2247 .gds_hw_ctrl = 0x0,
2248 .pd = {
2249 .name = "pcie_0_gdsc",
2250 },
2251 .pwrsts = PWRSTS_OFF_ON,
2252 .flags = VOTABLE,
2253};
2254
2255static struct clk_hw *gcc_sdm660_hws[] = {
2256 &xo.hw,
2257 &gpll0_early_div.hw,
2258 &gpll1_early_div.hw,
2259};
2260
2261static struct clk_regmap *gcc_sdm660_clocks[] = {
2262 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2263 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2264 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2265 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2266 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2267 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2268 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2269 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2270 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2271 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2272 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2273 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2274 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2275 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2276 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2277 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2278 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2279 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2280 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2281 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2282 [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
2283 [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
2284 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
2285 [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
2286 [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
2287 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2288 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2289 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2290 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2291 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2292 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2293 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2294 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2295 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2296 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2297 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2298 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2299 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2300 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2301 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2302 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2303 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2304 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2305 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2306 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2307 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2308 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2309 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2310 [GCC_CFG_NOC_USB2_AXI_CLK] = &gcc_cfg_noc_usb2_axi_clk.clkr,
2311 [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
2312 [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
2313 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2314 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2315 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2316 [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
2317 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
2318 [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
2319 [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
2320 [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
2321 [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
2322 [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
2323 [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
2324 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
2325 [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
2326 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2327 [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
2328 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
2329 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
2330 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2331 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2332 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2333 [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
2334 [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
2335 [GCC_RX0_USB2_CLKREF_CLK] = &gcc_rx0_usb2_clkref_clk.clkr,
2336 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
2337 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2338 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2339 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2340 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2341 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2342 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
2343 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2344 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
2345 [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
2346 [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
2347 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
2348 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
2349 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
2350 [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
2351 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
2352 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
2353 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
2354 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2355 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2356 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2357 [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
2358 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2359 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2360 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2361 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2362 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2363 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2364 [GPLL0] = &gpll0.clkr,
2365 [GPLL0_EARLY] = &gpll0_early.clkr,
2366 [GPLL1] = &gpll1.clkr,
2367 [GPLL1_EARLY] = &gpll1_early.clkr,
2368 [GPLL4] = &gpll4.clkr,
2369 [GPLL4_EARLY] = &gpll4_early.clkr,
2370 [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
2371 [HMSS_GPLL4_CLK_SRC] = &hmss_gpll4_clk_src.clkr,
2372 [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
2373 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2374 [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
2375 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2376 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
2377 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2378 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2379 [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
2380 [UFS_PHY_AUX_CLK_SRC] = &ufs_phy_aux_clk_src.clkr,
2381 [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr,
2382 [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
2383 [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
2384 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2385 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2386 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2387};
2388
2389static struct gdsc *gcc_sdm660_gdscs[] = {
2390 [UFS_GDSC] = &ufs_gdsc,
2391 [USB_30_GDSC] = &usb_30_gdsc,
2392 [PCIE_0_GDSC] = &pcie_0_gdsc,
2393};
2394
2395static const struct qcom_reset_map gcc_sdm660_resets[] = {
2396 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
2397 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
2398 [GCC_UFS_BCR] = { 0x75000 },
2399 [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
2400 [GCC_USB3_PHY_BCR] = { 0x50020 },
2401 [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
2402 [GCC_USB_20_BCR] = { 0x2f000 },
2403 [GCC_USB_30_BCR] = { 0xf000 },
2404 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
2405};
2406
2407static const struct regmap_config gcc_sdm660_regmap_config = {
2408 .reg_bits = 32,
2409 .reg_stride = 4,
2410 .val_bits = 32,
2411 .max_register = 0x94000,
2412 .fast_io = true,
2413};
2414
2415static const struct qcom_cc_desc gcc_sdm660_desc = {
2416 .config = &gcc_sdm660_regmap_config,
2417 .clks = gcc_sdm660_clocks,
2418 .num_clks = ARRAY_SIZE(gcc_sdm660_clocks),
2419 .resets = gcc_sdm660_resets,
2420 .num_resets = ARRAY_SIZE(gcc_sdm660_resets),
2421 .gdscs = gcc_sdm660_gdscs,
2422 .num_gdscs = ARRAY_SIZE(gcc_sdm660_gdscs),
2423};
2424
2425static const struct of_device_id gcc_sdm660_match_table[] = {
2426 { .compatible = "qcom,gcc-sdm630" },
2427 { .compatible = "qcom,gcc-sdm660" },
2428 { }
2429};
2430MODULE_DEVICE_TABLE(of, gcc_sdm660_match_table);
2431
2432static int gcc_sdm660_probe(struct platform_device *pdev)
2433{
2434 int i, ret;
2435 struct regmap *regmap;
2436
2437 regmap = qcom_cc_map(pdev, &gcc_sdm660_desc);
2438 if (IS_ERR(regmap))
2439 return PTR_ERR(regmap);
2440
2441 /*
2442 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
2443 * turned off by hardware during certain apps low power modes.
2444 */
2445 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
2446 if (ret)
2447 return ret;
2448
2449 /* Register the hws */
2450 for (i = 0; i < ARRAY_SIZE(gcc_sdm660_hws); i++) {
2451 ret = devm_clk_hw_register(&pdev->dev, gcc_sdm660_hws[i]);
2452 if (ret)
2453 return ret;
2454 }
2455
2456 return qcom_cc_really_probe(pdev, &gcc_sdm660_desc, regmap);
2457}
2458
2459static struct platform_driver gcc_sdm660_driver = {
2460 .probe = gcc_sdm660_probe,
2461 .driver = {
2462 .name = "gcc-sdm660",
2463 .of_match_table = gcc_sdm660_match_table,
2464 },
2465};
2466
2467static int __init gcc_sdm660_init(void)
2468{
2469 return platform_driver_register(&gcc_sdm660_driver);
2470}
2471core_initcall_sync(gcc_sdm660_init);
2472
2473static void __exit gcc_sdm660_exit(void)
2474{
2475 platform_driver_unregister(&gcc_sdm660_driver);
2476}
2477module_exit(gcc_sdm660_exit);
2478
2479MODULE_LICENSE("GPL v2");
2480MODULE_DESCRIPTION("QCOM GCC sdm660 Driver");
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index fa1a196350f1..08d593ed2ed6 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -356,6 +356,28 @@ static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
356 }, 356 },
357}; 357};
358 358
359static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
360 F(19200000, P_BI_TCXO, 1, 0, 0),
361 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
362 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
363 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
364 { }
365};
366
367static struct clk_rcg2 gcc_qspi_core_clk_src = {
368 .cmd_rcgr = 0x4b008,
369 .mnd_width = 0,
370 .hid_width = 5,
371 .parent_map = gcc_parent_map_0,
372 .freq_tbl = ftbl_gcc_qspi_core_clk_src,
373 .clkr.hw.init = &(struct clk_init_data){
374 .name = "gcc_qspi_core_clk_src",
375 .parent_names = gcc_parent_names_0,
376 .num_parents = 4,
377 .ops = &clk_rcg2_floor_ops,
378 },
379};
380
359static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 381static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
360 F(9600000, P_BI_TCXO, 2, 0, 0), 382 F(9600000, P_BI_TCXO, 2, 0, 0),
361 F(19200000, P_BI_TCXO, 1, 0, 0), 383 F(19200000, P_BI_TCXO, 1, 0, 0),
@@ -396,18 +418,27 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
396 { } 418 { }
397}; 419};
398 420
421static struct clk_init_data gcc_qupv3_wrap0_s0_clk_init = {
422 .name = "gcc_qupv3_wrap0_s0_clk_src",
423 .parent_names = gcc_parent_names_0,
424 .num_parents = 4,
425 .ops = &clk_rcg2_shared_ops,
426};
427
399static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 428static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
400 .cmd_rcgr = 0x17034, 429 .cmd_rcgr = 0x17034,
401 .mnd_width = 16, 430 .mnd_width = 16,
402 .hid_width = 5, 431 .hid_width = 5,
403 .parent_map = gcc_parent_map_0, 432 .parent_map = gcc_parent_map_0,
404 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 433 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
405 .clkr.hw.init = &(struct clk_init_data){ 434 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_init,
406 .name = "gcc_qupv3_wrap0_s0_clk_src", 435};
407 .parent_names = gcc_parent_names_0, 436
408 .num_parents = 4, 437static struct clk_init_data gcc_qupv3_wrap0_s1_clk_init = {
409 .ops = &clk_rcg2_shared_ops, 438 .name = "gcc_qupv3_wrap0_s1_clk_src",
410 }, 439 .parent_names = gcc_parent_names_0,
440 .num_parents = 4,
441 .ops = &clk_rcg2_shared_ops,
411}; 442};
412 443
413static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { 444static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
@@ -416,12 +447,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
416 .hid_width = 5, 447 .hid_width = 5,
417 .parent_map = gcc_parent_map_0, 448 .parent_map = gcc_parent_map_0,
418 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 449 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
419 .clkr.hw.init = &(struct clk_init_data){ 450 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_init,
420 .name = "gcc_qupv3_wrap0_s1_clk_src", 451};
421 .parent_names = gcc_parent_names_0, 452
422 .num_parents = 4, 453static struct clk_init_data gcc_qupv3_wrap0_s2_clk_init = {
423 .ops = &clk_rcg2_shared_ops, 454 .name = "gcc_qupv3_wrap0_s2_clk_src",
424 }, 455 .parent_names = gcc_parent_names_0,
456 .num_parents = 4,
457 .ops = &clk_rcg2_shared_ops,
425}; 458};
426 459
427static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { 460static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
@@ -430,12 +463,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
430 .hid_width = 5, 463 .hid_width = 5,
431 .parent_map = gcc_parent_map_0, 464 .parent_map = gcc_parent_map_0,
432 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 465 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
433 .clkr.hw.init = &(struct clk_init_data){ 466 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_init,
434 .name = "gcc_qupv3_wrap0_s2_clk_src", 467};
435 .parent_names = gcc_parent_names_0, 468
436 .num_parents = 4, 469static struct clk_init_data gcc_qupv3_wrap0_s3_clk_init = {
437 .ops = &clk_rcg2_shared_ops, 470 .name = "gcc_qupv3_wrap0_s3_clk_src",
438 }, 471 .parent_names = gcc_parent_names_0,
472 .num_parents = 4,
473 .ops = &clk_rcg2_shared_ops,
439}; 474};
440 475
441static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { 476static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
@@ -444,12 +479,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
444 .hid_width = 5, 479 .hid_width = 5,
445 .parent_map = gcc_parent_map_0, 480 .parent_map = gcc_parent_map_0,
446 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 481 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
447 .clkr.hw.init = &(struct clk_init_data){ 482 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_init,
448 .name = "gcc_qupv3_wrap0_s3_clk_src", 483};
449 .parent_names = gcc_parent_names_0, 484
450 .num_parents = 4, 485static struct clk_init_data gcc_qupv3_wrap0_s4_clk_init = {
451 .ops = &clk_rcg2_shared_ops, 486 .name = "gcc_qupv3_wrap0_s4_clk_src",
452 }, 487 .parent_names = gcc_parent_names_0,
488 .num_parents = 4,
489 .ops = &clk_rcg2_shared_ops,
453}; 490};
454 491
455static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { 492static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
@@ -458,12 +495,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
458 .hid_width = 5, 495 .hid_width = 5,
459 .parent_map = gcc_parent_map_0, 496 .parent_map = gcc_parent_map_0,
460 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 497 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
461 .clkr.hw.init = &(struct clk_init_data){ 498 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_init,
462 .name = "gcc_qupv3_wrap0_s4_clk_src", 499};
463 .parent_names = gcc_parent_names_0, 500
464 .num_parents = 4, 501static struct clk_init_data gcc_qupv3_wrap0_s5_clk_init = {
465 .ops = &clk_rcg2_shared_ops, 502 .name = "gcc_qupv3_wrap0_s5_clk_src",
466 }, 503 .parent_names = gcc_parent_names_0,
504 .num_parents = 4,
505 .ops = &clk_rcg2_shared_ops,
467}; 506};
468 507
469static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { 508static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
@@ -472,12 +511,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
472 .hid_width = 5, 511 .hid_width = 5,
473 .parent_map = gcc_parent_map_0, 512 .parent_map = gcc_parent_map_0,
474 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 513 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
475 .clkr.hw.init = &(struct clk_init_data){ 514 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_init,
476 .name = "gcc_qupv3_wrap0_s5_clk_src", 515};
477 .parent_names = gcc_parent_names_0, 516
478 .num_parents = 4, 517static struct clk_init_data gcc_qupv3_wrap0_s6_clk_init = {
479 .ops = &clk_rcg2_shared_ops, 518 .name = "gcc_qupv3_wrap0_s6_clk_src",
480 }, 519 .parent_names = gcc_parent_names_0,
520 .num_parents = 4,
521 .ops = &clk_rcg2_shared_ops,
481}; 522};
482 523
483static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { 524static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
@@ -486,12 +527,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
486 .hid_width = 5, 527 .hid_width = 5,
487 .parent_map = gcc_parent_map_0, 528 .parent_map = gcc_parent_map_0,
488 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 529 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
489 .clkr.hw.init = &(struct clk_init_data){ 530 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_init,
490 .name = "gcc_qupv3_wrap0_s6_clk_src", 531};
491 .parent_names = gcc_parent_names_0, 532
492 .num_parents = 4, 533static struct clk_init_data gcc_qupv3_wrap0_s7_clk_init = {
493 .ops = &clk_rcg2_shared_ops, 534 .name = "gcc_qupv3_wrap0_s7_clk_src",
494 }, 535 .parent_names = gcc_parent_names_0,
536 .num_parents = 4,
537 .ops = &clk_rcg2_shared_ops,
495}; 538};
496 539
497static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { 540static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
@@ -500,12 +543,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
500 .hid_width = 5, 543 .hid_width = 5,
501 .parent_map = gcc_parent_map_0, 544 .parent_map = gcc_parent_map_0,
502 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 545 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
503 .clkr.hw.init = &(struct clk_init_data){ 546 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_init,
504 .name = "gcc_qupv3_wrap0_s7_clk_src", 547};
505 .parent_names = gcc_parent_names_0, 548
506 .num_parents = 4, 549static struct clk_init_data gcc_qupv3_wrap1_s0_clk_init = {
507 .ops = &clk_rcg2_shared_ops, 550 .name = "gcc_qupv3_wrap1_s0_clk_src",
508 }, 551 .parent_names = gcc_parent_names_0,
552 .num_parents = 4,
553 .ops = &clk_rcg2_shared_ops,
509}; 554};
510 555
511static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 556static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
@@ -514,12 +559,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
514 .hid_width = 5, 559 .hid_width = 5,
515 .parent_map = gcc_parent_map_0, 560 .parent_map = gcc_parent_map_0,
516 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 561 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
517 .clkr.hw.init = &(struct clk_init_data){ 562 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_init,
518 .name = "gcc_qupv3_wrap1_s0_clk_src", 563};
519 .parent_names = gcc_parent_names_0, 564
520 .num_parents = 4, 565static struct clk_init_data gcc_qupv3_wrap1_s1_clk_init = {
521 .ops = &clk_rcg2_shared_ops, 566 .name = "gcc_qupv3_wrap1_s1_clk_src",
522 }, 567 .parent_names = gcc_parent_names_0,
568 .num_parents = 4,
569 .ops = &clk_rcg2_shared_ops,
523}; 570};
524 571
525static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 572static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
@@ -528,12 +575,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
528 .hid_width = 5, 575 .hid_width = 5,
529 .parent_map = gcc_parent_map_0, 576 .parent_map = gcc_parent_map_0,
530 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 577 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
531 .clkr.hw.init = &(struct clk_init_data){ 578 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_init,
532 .name = "gcc_qupv3_wrap1_s1_clk_src", 579};
533 .parent_names = gcc_parent_names_0, 580
534 .num_parents = 4, 581static struct clk_init_data gcc_qupv3_wrap1_s2_clk_init = {
535 .ops = &clk_rcg2_shared_ops, 582 .name = "gcc_qupv3_wrap1_s2_clk_src",
536 }, 583 .parent_names = gcc_parent_names_0,
584 .num_parents = 4,
585 .ops = &clk_rcg2_shared_ops,
537}; 586};
538 587
539static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { 588static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
@@ -542,12 +591,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
542 .hid_width = 5, 591 .hid_width = 5,
543 .parent_map = gcc_parent_map_0, 592 .parent_map = gcc_parent_map_0,
544 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 593 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
545 .clkr.hw.init = &(struct clk_init_data){ 594 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_init,
546 .name = "gcc_qupv3_wrap1_s2_clk_src", 595};
547 .parent_names = gcc_parent_names_0, 596
548 .num_parents = 4, 597static struct clk_init_data gcc_qupv3_wrap1_s3_clk_init = {
549 .ops = &clk_rcg2_shared_ops, 598 .name = "gcc_qupv3_wrap1_s3_clk_src",
550 }, 599 .parent_names = gcc_parent_names_0,
600 .num_parents = 4,
601 .ops = &clk_rcg2_shared_ops,
551}; 602};
552 603
553static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 604static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
@@ -556,12 +607,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
556 .hid_width = 5, 607 .hid_width = 5,
557 .parent_map = gcc_parent_map_0, 608 .parent_map = gcc_parent_map_0,
558 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 609 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
559 .clkr.hw.init = &(struct clk_init_data){ 610 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_init,
560 .name = "gcc_qupv3_wrap1_s3_clk_src", 611};
561 .parent_names = gcc_parent_names_0, 612
562 .num_parents = 4, 613static struct clk_init_data gcc_qupv3_wrap1_s4_clk_init = {
563 .ops = &clk_rcg2_shared_ops, 614 .name = "gcc_qupv3_wrap1_s4_clk_src",
564 }, 615 .parent_names = gcc_parent_names_0,
616 .num_parents = 4,
617 .ops = &clk_rcg2_shared_ops,
565}; 618};
566 619
567static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 620static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
@@ -570,12 +623,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
570 .hid_width = 5, 623 .hid_width = 5,
571 .parent_map = gcc_parent_map_0, 624 .parent_map = gcc_parent_map_0,
572 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 625 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
573 .clkr.hw.init = &(struct clk_init_data){ 626 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_init,
574 .name = "gcc_qupv3_wrap1_s4_clk_src", 627};
575 .parent_names = gcc_parent_names_0, 628
576 .num_parents = 4, 629static struct clk_init_data gcc_qupv3_wrap1_s5_clk_init = {
577 .ops = &clk_rcg2_shared_ops, 630 .name = "gcc_qupv3_wrap1_s5_clk_src",
578 }, 631 .parent_names = gcc_parent_names_0,
632 .num_parents = 4,
633 .ops = &clk_rcg2_shared_ops,
579}; 634};
580 635
581static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 636static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
@@ -584,12 +639,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
584 .hid_width = 5, 639 .hid_width = 5,
585 .parent_map = gcc_parent_map_0, 640 .parent_map = gcc_parent_map_0,
586 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 641 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
587 .clkr.hw.init = &(struct clk_init_data){ 642 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_init,
588 .name = "gcc_qupv3_wrap1_s5_clk_src", 643};
589 .parent_names = gcc_parent_names_0, 644
590 .num_parents = 4, 645static struct clk_init_data gcc_qupv3_wrap1_s6_clk_init = {
591 .ops = &clk_rcg2_shared_ops, 646 .name = "gcc_qupv3_wrap1_s6_clk_src",
592 }, 647 .parent_names = gcc_parent_names_0,
648 .num_parents = 4,
649 .ops = &clk_rcg2_shared_ops,
593}; 650};
594 651
595static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 652static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
@@ -598,12 +655,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
598 .hid_width = 5, 655 .hid_width = 5,
599 .parent_map = gcc_parent_map_0, 656 .parent_map = gcc_parent_map_0,
600 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 657 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
601 .clkr.hw.init = &(struct clk_init_data){ 658 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_init,
602 .name = "gcc_qupv3_wrap1_s6_clk_src", 659};
603 .parent_names = gcc_parent_names_0, 660
604 .num_parents = 4, 661static struct clk_init_data gcc_qupv3_wrap1_s7_clk_init = {
605 .ops = &clk_rcg2_shared_ops, 662 .name = "gcc_qupv3_wrap1_s7_clk_src",
606 }, 663 .parent_names = gcc_parent_names_0,
664 .num_parents = 4,
665 .ops = &clk_rcg2_shared_ops,
607}; 666};
608 667
609static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 668static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
@@ -612,12 +671,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
612 .hid_width = 5, 671 .hid_width = 5,
613 .parent_map = gcc_parent_map_0, 672 .parent_map = gcc_parent_map_0,
614 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 673 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
615 .clkr.hw.init = &(struct clk_init_data){ 674 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_init,
616 .name = "gcc_qupv3_wrap1_s7_clk_src",
617 .parent_names = gcc_parent_names_0,
618 .num_parents = 4,
619 .ops = &clk_rcg2_shared_ops,
620 },
621}; 675};
622 676
623static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 677static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
@@ -1933,6 +1987,37 @@ static struct clk_branch gcc_qmip_video_ahb_clk = {
1933 }, 1987 },
1934}; 1988};
1935 1989
1990static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
1991 .halt_reg = 0x4b000,
1992 .halt_check = BRANCH_HALT,
1993 .clkr = {
1994 .enable_reg = 0x4b000,
1995 .enable_mask = BIT(0),
1996 .hw.init = &(struct clk_init_data){
1997 .name = "gcc_qspi_cnoc_periph_ahb_clk",
1998 .ops = &clk_branch2_ops,
1999 },
2000 },
2001};
2002
2003static struct clk_branch gcc_qspi_core_clk = {
2004 .halt_reg = 0x4b004,
2005 .halt_check = BRANCH_HALT,
2006 .clkr = {
2007 .enable_reg = 0x4b004,
2008 .enable_mask = BIT(0),
2009 .hw.init = &(struct clk_init_data){
2010 .name = "gcc_qspi_core_clk",
2011 .parent_names = (const char *[]){
2012 "gcc_qspi_core_clk_src",
2013 },
2014 .num_parents = 1,
2015 .flags = CLK_SET_RATE_PARENT,
2016 .ops = &clk_branch2_ops,
2017 },
2018 },
2019};
2020
1936static struct clk_branch gcc_qupv3_wrap0_s0_clk = { 2021static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1937 .halt_reg = 0x17030, 2022 .halt_reg = 0x17030,
1938 .halt_check = BRANCH_HALT_VOTED, 2023 .halt_check = BRANCH_HALT_VOTED,
@@ -3381,6 +3466,9 @@ static struct clk_regmap *gcc_sdm845_clocks[] = {
3381 [GPLL4] = &gpll4.clkr, 3466 [GPLL4] = &gpll4.clkr,
3382 [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr, 3467 [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
3383 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, 3468 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3469 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3470 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3471 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3384}; 3472};
3385 3473
3386static const struct qcom_reset_map gcc_sdm845_resets[] = { 3474static const struct qcom_reset_map gcc_sdm845_resets[] = {
@@ -3458,9 +3546,29 @@ static const struct of_device_id gcc_sdm845_match_table[] = {
3458}; 3546};
3459MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table); 3547MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);
3460 3548
3549static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3550 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk),
3551 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk),
3552 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk),
3553 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk),
3554 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk),
3555 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk),
3556 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk),
3557 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk),
3558 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk),
3559 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk),
3560 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk),
3561 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk),
3562 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk),
3563 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk),
3564 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk),
3565 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk),
3566};
3567
3461static int gcc_sdm845_probe(struct platform_device *pdev) 3568static int gcc_sdm845_probe(struct platform_device *pdev)
3462{ 3569{
3463 struct regmap *regmap; 3570 struct regmap *regmap;
3571 int ret;
3464 3572
3465 regmap = qcom_cc_map(pdev, &gcc_sdm845_desc); 3573 regmap = qcom_cc_map(pdev, &gcc_sdm845_desc);
3466 if (IS_ERR(regmap)) 3574 if (IS_ERR(regmap))
@@ -3470,6 +3578,11 @@ static int gcc_sdm845_probe(struct platform_device *pdev)
3470 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); 3578 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
3471 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 3579 regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
3472 3580
3581 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
3582 ARRAY_SIZE(gcc_dfs_clocks));
3583 if (ret)
3584 return ret;
3585
3473 return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap); 3586 return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
3474} 3587}
3475 3588
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 9022bbe1297e..b879e3e3a6b4 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -1,13 +1,18 @@
1# SPDX-License-Identifier: GPL-2.0
2
1config CLK_RENESAS 3config CLK_RENESAS
2 bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS 4 bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
3 default y if ARCH_RENESAS 5 default y if ARCH_RENESAS
4 select CLK_EMEV2 if ARCH_EMEV2 6 select CLK_EMEV2 if ARCH_EMEV2
5 select CLK_RZA1 if ARCH_R7S72100 7 select CLK_RZA1 if ARCH_R7S72100
8 select CLK_R7S9210 if ARCH_R7S9210
6 select CLK_R8A73A4 if ARCH_R8A73A4 9 select CLK_R8A73A4 if ARCH_R8A73A4
7 select CLK_R8A7740 if ARCH_R8A7740 10 select CLK_R8A7740 if ARCH_R8A7740
8 select CLK_R8A7743 if ARCH_R8A7743 11 select CLK_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744
9 select CLK_R8A7745 if ARCH_R8A7745 12 select CLK_R8A7745 if ARCH_R8A7745
10 select CLK_R8A77470 if ARCH_R8A77470 13 select CLK_R8A77470 if ARCH_R8A77470
14 select CLK_R8A774A1 if ARCH_R8A774A1
15 select CLK_R8A774C0 if ARCH_R8A774C0
11 select CLK_R8A7778 if ARCH_R8A7778 16 select CLK_R8A7778 if ARCH_R8A7778
12 select CLK_R8A7779 if ARCH_R8A7779 17 select CLK_R8A7779 if ARCH_R8A7779
13 select CLK_R8A7790 if ARCH_R8A7790 18 select CLK_R8A7790 if ARCH_R8A7790
@@ -45,6 +50,10 @@ config CLK_RZA1
45 bool "RZ/A1H clock support" if COMPILE_TEST 50 bool "RZ/A1H clock support" if COMPILE_TEST
46 select CLK_RENESAS_CPG_MSTP 51 select CLK_RENESAS_CPG_MSTP
47 52
53config CLK_R7S9210
54 bool "RZ/A2 clock support" if COMPILE_TEST
55 select CLK_RENESAS_CPG_MSSR
56
48config CLK_R8A73A4 57config CLK_R8A73A4
49 bool "R-Mobile APE6 clock support" if COMPILE_TEST 58 bool "R-Mobile APE6 clock support" if COMPILE_TEST
50 select CLK_RENESAS_CPG_MSTP 59 select CLK_RENESAS_CPG_MSTP
@@ -67,6 +76,14 @@ config CLK_R8A77470
67 bool "RZ/G1C clock support" if COMPILE_TEST 76 bool "RZ/G1C clock support" if COMPILE_TEST
68 select CLK_RCAR_GEN2_CPG 77 select CLK_RCAR_GEN2_CPG
69 78
79config CLK_R8A774A1
80 bool "RZ/G2M clock support" if COMPILE_TEST
81 select CLK_RCAR_GEN3_CPG
82
83config CLK_R8A774C0
84 bool "RZ/G2E clock support" if COMPILE_TEST
85 select CLK_RCAR_GEN3_CPG
86
70config CLK_R8A7778 87config CLK_R8A7778
71 bool "R-Car M1A clock support" if COMPILE_TEST 88 bool "R-Car M1A clock support" if COMPILE_TEST
72 select CLK_RENESAS_CPG_MSTP 89 select CLK_RENESAS_CPG_MSTP
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index e4aa3d6143d2..c793e3cc9452 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -2,11 +2,14 @@
2# SoC 2# SoC
3obj-$(CONFIG_CLK_EMEV2) += clk-emev2.o 3obj-$(CONFIG_CLK_EMEV2) += clk-emev2.o
4obj-$(CONFIG_CLK_RZA1) += clk-rz.o 4obj-$(CONFIG_CLK_RZA1) += clk-rz.o
5obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
5obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o 6obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o
6obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o 7obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o
7obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o 8obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
8obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o 9obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
9obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o 10obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
11obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
12obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
10obj-$(CONFIG_CLK_R8A7778) += clk-r8a7778.o 13obj-$(CONFIG_CLK_R8A7778) += clk-r8a7778.o
11obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o 14obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o
12obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o 15obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c
index 9febbf42c3df..57c934164306 100644
--- a/drivers/clk/renesas/clk-div6.c
+++ b/drivers/clk/renesas/clk-div6.c
@@ -1,13 +1,10 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * r8a7790 Common Clock Framework support 3 * r8a7790 Common Clock Framework support
3 * 4 *
4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Renesas Solutions Corp.
5 * 6 *
6 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 7 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 */ 8 */
12 9
13#include <linux/clk-provider.h> 10#include <linux/clk-provider.h>
@@ -312,8 +309,8 @@ static void __init cpg_div6_clock_init(struct device_node *np)
312 309
313 num_parents = of_clk_get_parent_count(np); 310 num_parents = of_clk_get_parent_count(np);
314 if (num_parents < 1) { 311 if (num_parents < 1) {
315 pr_err("%s: no parent found for %s DIV6 clock\n", 312 pr_err("%s: no parent found for %pOFn DIV6 clock\n",
316 __func__, np->name); 313 __func__, np);
317 return; 314 return;
318 } 315 }
319 316
@@ -324,8 +321,8 @@ static void __init cpg_div6_clock_init(struct device_node *np)
324 321
325 reg = of_iomap(np, 0); 322 reg = of_iomap(np, 0);
326 if (reg == NULL) { 323 if (reg == NULL) {
327 pr_err("%s: failed to map %s DIV6 clock register\n", 324 pr_err("%s: failed to map %pOFn DIV6 clock register\n",
328 __func__, np->name); 325 __func__, np);
329 goto error; 326 goto error;
330 } 327 }
331 328
@@ -337,8 +334,8 @@ static void __init cpg_div6_clock_init(struct device_node *np)
337 334
338 clk = cpg_div6_register(clk_name, num_parents, parent_names, reg, NULL); 335 clk = cpg_div6_register(clk_name, num_parents, parent_names, reg, NULL);
339 if (IS_ERR(clk)) { 336 if (IS_ERR(clk)) {
340 pr_err("%s: failed to register %s DIV6 clock (%ld)\n", 337 pr_err("%s: failed to register %pOFn DIV6 clock (%ld)\n",
341 __func__, np->name, PTR_ERR(clk)); 338 __func__, np, PTR_ERR(clk));
342 goto error; 339 goto error;
343 } 340 }
344 341
diff --git a/drivers/clk/renesas/clk-emev2.c b/drivers/clk/renesas/clk-emev2.c
index a91825471c79..7807b30a5bbb 100644
--- a/drivers/clk/renesas/clk-emev2.c
+++ b/drivers/clk/renesas/clk-emev2.c
@@ -1,21 +1,9 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * EMMA Mobile EV2 common clock framework support 3 * EMMA Mobile EV2 common clock framework support
3 * 4 *
4 * Copyright (C) 2013 Takashi Yoshii <takashi.yoshii.ze@renesas.com> 5 * Copyright (C) 2013 Takashi Yoshii <takashi.yoshii.ze@renesas.com>
5 * Copyright (C) 2012 Magnus Damm 6 * Copyright (C) 2012 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 7 */
20#include <linux/clk-provider.h> 8#include <linux/clk-provider.h>
21#include <linux/clkdev.h> 9#include <linux/clkdev.h>
@@ -86,8 +74,8 @@ static void __init emev2_smu_clkdiv_init(struct device_node *np)
86 clk = clk_register_divider(NULL, np->name, parent_name, 0, 74 clk = clk_register_divider(NULL, np->name, parent_name, 0,
87 smu_base + reg[0], reg[1], 8, 0, &lock); 75 smu_base + reg[0], reg[1], 8, 0, &lock);
88 of_clk_add_provider(np, of_clk_src_simple_get, clk); 76 of_clk_add_provider(np, of_clk_src_simple_get, clk);
89 clk_register_clkdev(clk, np->name, NULL); 77 clk_register_clkdev(clk, np->full_name, NULL);
90 pr_debug("## %s %s %p\n", __func__, np->name, clk); 78 pr_debug("## %s %pOFn %p\n", __func__, np, clk);
91} 79}
92CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv", 80CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv",
93 emev2_smu_clkdiv_init); 81 emev2_smu_clkdiv_init);
@@ -104,7 +92,7 @@ static void __init emev2_smu_gclk_init(struct device_node *np)
104 clk = clk_register_gate(NULL, np->name, parent_name, 0, 92 clk = clk_register_gate(NULL, np->name, parent_name, 0,
105 smu_base + reg[0], reg[1], 0, &lock); 93 smu_base + reg[0], reg[1], 0, &lock);
106 of_clk_add_provider(np, of_clk_src_simple_get, clk); 94 of_clk_add_provider(np, of_clk_src_simple_get, clk);
107 clk_register_clkdev(clk, np->name, NULL); 95 clk_register_clkdev(clk, np->full_name, NULL);
108 pr_debug("## %s %s %p\n", __func__, np->name, clk); 96 pr_debug("## %s %pOFn %p\n", __func__, np, clk);
109} 97}
110CLK_OF_DECLARE(emev2_smu_gclk, "renesas,emev2-smu-gclk", emev2_smu_gclk_init); 98CLK_OF_DECLARE(emev2_smu_gclk, "renesas,emev2-smu-gclk", emev2_smu_gclk_init);
diff --git a/drivers/clk/renesas/clk-mstp.c b/drivers/clk/renesas/clk-mstp.c
index e82adcb16a52..1c1768c2cc82 100644
--- a/drivers/clk/renesas/clk-mstp.c
+++ b/drivers/clk/renesas/clk-mstp.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * R-Car MSTP clocks 3 * R-Car MSTP clocks
3 * 4 *
@@ -5,10 +6,6 @@
5 * Copyright (C) 2015 Glider bvba 6 * Copyright (C) 2015 Glider bvba
6 * 7 *
7 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 8 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 */ 9 */
13 10
14#include <linux/clk.h> 11#include <linux/clk.h>
@@ -239,8 +236,8 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
239 break; 236 break;
240 237
241 if (clkidx >= MSTP_MAX_CLOCKS) { 238 if (clkidx >= MSTP_MAX_CLOCKS) {
242 pr_err("%s: invalid clock %s %s index %u\n", 239 pr_err("%s: invalid clock %pOFn %s index %u\n",
243 __func__, np->name, name, clkidx); 240 __func__, np, name, clkidx);
244 continue; 241 continue;
245 } 242 }
246 243
@@ -259,8 +256,8 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
259 */ 256 */
260 clk_register_clkdev(clks[clkidx], name, NULL); 257 clk_register_clkdev(clks[clkidx], name, NULL);
261 } else { 258 } else {
262 pr_err("%s: failed to register %s %s clock (%ld)\n", 259 pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
263 __func__, np->name, name, PTR_ERR(clks[clkidx])); 260 __func__, np, name, PTR_ERR(clks[clkidx]));
264 } 261 }
265 } 262 }
266 263
diff --git a/drivers/clk/renesas/clk-r8a73a4.c b/drivers/clk/renesas/clk-r8a73a4.c
index 7b903ce4c901..2719c248c67b 100644
--- a/drivers/clk/renesas/clk-r8a73a4.c
+++ b/drivers/clk/renesas/clk-r8a73a4.c
@@ -1,11 +1,8 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * r8a73a4 Core CPG Clocks 3 * r8a73a4 Core CPG Clocks
3 * 4 *
4 * Copyright (C) 2014 Ulrich Hecht 5 * Copyright (C) 2014 Ulrich Hecht
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */ 6 */
10 7
11#include <linux/clk-provider.h> 8#include <linux/clk-provider.h>
@@ -228,8 +225,8 @@ static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
228 225
229 clk = r8a73a4_cpg_register_clock(np, cpg, name); 226 clk = r8a73a4_cpg_register_clock(np, cpg, name);
230 if (IS_ERR(clk)) 227 if (IS_ERR(clk))
231 pr_err("%s: failed to register %s %s clock (%ld)\n", 228 pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
232 __func__, np->name, name, PTR_ERR(clk)); 229 __func__, np, name, PTR_ERR(clk));
233 else 230 else
234 cpg->data.clks[i] = clk; 231 cpg->data.clks[i] = clk;
235 } 232 }
diff --git a/drivers/clk/renesas/clk-r8a7740.c b/drivers/clk/renesas/clk-r8a7740.c
index a7a30d2eca41..5967656c13cc 100644
--- a/drivers/clk/renesas/clk-r8a7740.c
+++ b/drivers/clk/renesas/clk-r8a7740.c
@@ -1,11 +1,8 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * r8a7740 Core CPG Clocks 3 * r8a7740 Core CPG Clocks
3 * 4 *
4 * Copyright (C) 2014 Ulrich Hecht 5 * Copyright (C) 2014 Ulrich Hecht
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */ 6 */
10 7
11#include <linux/clk-provider.h> 8#include <linux/clk-provider.h>
@@ -187,8 +184,8 @@ static void __init r8a7740_cpg_clocks_init(struct device_node *np)
187 184
188 clk = r8a7740_cpg_register_clock(np, cpg, name); 185 clk = r8a7740_cpg_register_clock(np, cpg, name);
189 if (IS_ERR(clk)) 186 if (IS_ERR(clk))
190 pr_err("%s: failed to register %s %s clock (%ld)\n", 187 pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
191 __func__, np->name, name, PTR_ERR(clk)); 188 __func__, np, name, PTR_ERR(clk));
192 else 189 else
193 cpg->data.clks[i] = clk; 190 cpg->data.clks[i] = clk;
194 } 191 }
diff --git a/drivers/clk/renesas/clk-r8a7778.c b/drivers/clk/renesas/clk-r8a7778.c
index 886a8380e912..3ccc53685bdd 100644
--- a/drivers/clk/renesas/clk-r8a7778.c
+++ b/drivers/clk/renesas/clk-r8a7778.c
@@ -1,11 +1,8 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * r8a7778 Core CPG Clocks 3 * r8a7778 Core CPG Clocks
3 * 4 *
4 * Copyright (C) 2014 Ulrich Hecht 5 * Copyright (C) 2014 Ulrich Hecht
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */ 6 */
10 7
11#include <linux/clk-provider.h> 8#include <linux/clk-provider.h>
@@ -130,8 +127,8 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np)
130 127
131 clk = r8a7778_cpg_register_clock(np, cpg, name); 128 clk = r8a7778_cpg_register_clock(np, cpg, name);
132 if (IS_ERR(clk)) 129 if (IS_ERR(clk))
133 pr_err("%s: failed to register %s %s clock (%ld)\n", 130 pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
134 __func__, np->name, name, PTR_ERR(clk)); 131 __func__, np, name, PTR_ERR(clk));
135 else 132 else
136 cpg->data.clks[i] = clk; 133 cpg->data.clks[i] = clk;
137 } 134 }
diff --git a/drivers/clk/renesas/clk-r8a7779.c b/drivers/clk/renesas/clk-r8a7779.c
index 5adcca4656c3..9f3b5522eef5 100644
--- a/drivers/clk/renesas/clk-r8a7779.c
+++ b/drivers/clk/renesas/clk-r8a7779.c
@@ -1,13 +1,10 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * r8a7779 Core CPG Clocks 3 * r8a7779 Core CPG Clocks
3 * 4 *
4 * Copyright (C) 2013, 2014 Horms Solutions Ltd. 5 * Copyright (C) 2013, 2014 Horms Solutions Ltd.
5 * 6 *
6 * Contact: Simon Horman <horms@verge.net.au> 7 * Contact: Simon Horman <horms@verge.net.au>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 */ 8 */
12 9
13#include <linux/clk-provider.h> 10#include <linux/clk-provider.h>
@@ -164,8 +161,8 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np)
164 clk = r8a7779_cpg_register_clock(np, cpg, config, 161 clk = r8a7779_cpg_register_clock(np, cpg, config,
165 plla_mult, name); 162 plla_mult, name);
166 if (IS_ERR(clk)) 163 if (IS_ERR(clk))
167 pr_err("%s: failed to register %s %s clock (%ld)\n", 164 pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
168 __func__, np->name, name, PTR_ERR(clk)); 165 __func__, np, name, PTR_ERR(clk));
169 else 166 else
170 cpg->data.clks[i] = clk; 167 cpg->data.clks[i] = clk;
171 } 168 }
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c
index bccd62f2cb09..2913b4148157 100644
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -1,13 +1,10 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * rcar_gen2 Core CPG Clocks 3 * rcar_gen2 Core CPG Clocks
3 * 4 *
4 * Copyright (C) 2013 Ideas On Board SPRL 5 * Copyright (C) 2013 Ideas On Board SPRL
5 * 6 *
6 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 7 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 */ 8 */
12 9
13#include <linux/clk-provider.h> 10#include <linux/clk-provider.h>
@@ -445,8 +442,8 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
445 442
446 clk = rcar_gen2_cpg_register_clock(np, cpg, config, name); 443 clk = rcar_gen2_cpg_register_clock(np, cpg, config, name);
447 if (IS_ERR(clk)) 444 if (IS_ERR(clk))
448 pr_err("%s: failed to register %s %s clock (%ld)\n", 445 pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
449 __func__, np->name, name, PTR_ERR(clk)); 446 __func__, np, name, PTR_ERR(clk));
450 else 447 else
451 cpg->data.clks[i] = clk; 448 cpg->data.clks[i] = clk;
452 } 449 }
diff --git a/drivers/clk/renesas/clk-rz.c b/drivers/clk/renesas/clk-rz.c
index ac2f86d626b6..3cda53a97f4e 100644
--- a/drivers/clk/renesas/clk-rz.c
+++ b/drivers/clk/renesas/clk-rz.c
@@ -1,12 +1,9 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * RZ/A1 Core CPG Clocks 3 * RZ/A1 Core CPG Clocks
3 * 4 *
4 * Copyright (C) 2013 Ideas On Board SPRL 5 * Copyright (C) 2013 Ideas On Board SPRL
5 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> 6 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 */ 7 */
11 8
12#include <linux/clk-provider.h> 9#include <linux/clk-provider.h>
@@ -113,8 +110,8 @@ static void __init rz_cpg_clocks_init(struct device_node *np)
113 110
114 clk = rz_cpg_register_clock(np, cpg, name); 111 clk = rz_cpg_register_clock(np, cpg, name);
115 if (IS_ERR(clk)) 112 if (IS_ERR(clk))
116 pr_err("%s: failed to register %s %s clock (%ld)\n", 113 pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
117 __func__, np->name, name, PTR_ERR(clk)); 114 __func__, np, name, PTR_ERR(clk));
118 else 115 else
119 cpg->data.clks[i] = clk; 116 cpg->data.clks[i] = clk;
120 } 117 }
diff --git a/drivers/clk/renesas/clk-sh73a0.c b/drivers/clk/renesas/clk-sh73a0.c
index bab33610eb6c..dc8ffc7c727a 100644
--- a/drivers/clk/renesas/clk-sh73a0.c
+++ b/drivers/clk/renesas/clk-sh73a0.c
@@ -1,11 +1,8 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * sh73a0 Core CPG Clocks 3 * sh73a0 Core CPG Clocks
3 * 4 *
4 * Copyright (C) 2014 Ulrich Hecht 5 * Copyright (C) 2014 Ulrich Hecht
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */ 6 */
10 7
11#include <linux/clk-provider.h> 8#include <linux/clk-provider.h>
@@ -206,8 +203,8 @@ static void __init sh73a0_cpg_clocks_init(struct device_node *np)
206 203
207 clk = sh73a0_cpg_register_clock(np, cpg, name); 204 clk = sh73a0_cpg_register_clock(np, cpg, name);
208 if (IS_ERR(clk)) 205 if (IS_ERR(clk))
209 pr_err("%s: failed to register %s %s clock (%ld)\n", 206 pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
210 __func__, np->name, name, PTR_ERR(clk)); 207 __func__, np, name, PTR_ERR(clk));
211 else 208 else
212 cpg->data.clks[i] = clk; 209 cpg->data.clks[i] = clk;
213 } 210 }
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c b/drivers/clk/renesas/r7s9210-cpg-mssr.c
new file mode 100644
index 000000000000..5135f13ec628
--- /dev/null
+++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c
@@ -0,0 +1,217 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R7S9210 Clock Pulse Generator / Module Standby
4 *
5 * Based on r8a7795-cpg-mssr.c
6 *
7 * Copyright (C) 2018 Chris Brandt
8 * Copyright (C) 2018 Renesas Electronics Corp.
9 *
10 */
11
12#include <linux/clk.h>
13#include <linux/clk-provider.h>
14#include <dt-bindings/clock/r7s9210-cpg-mssr.h>
15#include "renesas-cpg-mssr.h"
16
17#define CPG_FRQCR 0x00
18
19static u8 cpg_mode;
20
21/* Internal Clock ratio table */
22static const struct {
23 unsigned int i;
24 unsigned int g;
25 unsigned int b;
26 unsigned int p1;
27 /* p0 is always 32 */;
28} ratio_tab[5] = { /* I, G, B, P1 */
29 { 2, 4, 8, 16}, /* FRQCR = 0x012 */
30 { 4, 4, 8, 16}, /* FRQCR = 0x112 */
31 { 8, 4, 8, 16}, /* FRQCR = 0x212 */
32 { 16, 8, 16, 16}, /* FRQCR = 0x322 */
33 { 16, 16, 32, 32}, /* FRQCR = 0x333 */
34 };
35
36enum rz_clk_types {
37 CLK_TYPE_RZA_MAIN = CLK_TYPE_CUSTOM,
38 CLK_TYPE_RZA_PLL,
39};
40
41enum clk_ids {
42 /* Core Clock Outputs exported to DT */
43 LAST_DT_CORE_CLK = R7S9210_CLK_P0,
44
45 /* External Input Clocks */
46 CLK_EXTAL,
47
48 /* Internal Core Clocks */
49 CLK_MAIN,
50 CLK_PLL,
51
52 /* Module Clocks */
53 MOD_CLK_BASE
54};
55
56static struct cpg_core_clk r7s9210_early_core_clks[] = {
57 /* External Clock Inputs */
58 DEF_INPUT("extal", CLK_EXTAL),
59
60 /* Internal Core Clocks */
61 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_RZA_MAIN, CLK_EXTAL),
62 DEF_BASE(".pll", CLK_PLL, CLK_TYPE_RZA_PLL, CLK_MAIN),
63
64 /* Core Clock Outputs */
65 DEF_FIXED("p1c", R7S9210_CLK_P1C, CLK_PLL, 16, 1),
66};
67
68static const struct mssr_mod_clk r7s9210_early_mod_clks[] __initconst = {
69 DEF_MOD_STB("ostm2", 34, R7S9210_CLK_P1C),
70 DEF_MOD_STB("ostm1", 35, R7S9210_CLK_P1C),
71 DEF_MOD_STB("ostm0", 36, R7S9210_CLK_P1C),
72};
73
74static struct cpg_core_clk r7s9210_core_clks[] = {
75 /* Core Clock Outputs */
76 DEF_FIXED("i", R7S9210_CLK_I, CLK_PLL, 2, 1),
77 DEF_FIXED("g", R7S9210_CLK_G, CLK_PLL, 4, 1),
78 DEF_FIXED("b", R7S9210_CLK_B, CLK_PLL, 8, 1),
79 DEF_FIXED("p1", R7S9210_CLK_P1, CLK_PLL, 16, 1),
80 DEF_FIXED("p0", R7S9210_CLK_P0, CLK_PLL, 32, 1),
81};
82
83static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = {
84 DEF_MOD_STB("scif4", 43, R7S9210_CLK_P1C),
85 DEF_MOD_STB("scif3", 44, R7S9210_CLK_P1C),
86 DEF_MOD_STB("scif2", 45, R7S9210_CLK_P1C),
87 DEF_MOD_STB("scif1", 46, R7S9210_CLK_P1C),
88 DEF_MOD_STB("scif0", 47, R7S9210_CLK_P1C),
89
90 DEF_MOD_STB("ether1", 64, R7S9210_CLK_B),
91 DEF_MOD_STB("ether0", 65, R7S9210_CLK_B),
92
93 DEF_MOD_STB("i2c3", 84, R7S9210_CLK_P1),
94 DEF_MOD_STB("i2c2", 85, R7S9210_CLK_P1),
95 DEF_MOD_STB("i2c1", 86, R7S9210_CLK_P1),
96 DEF_MOD_STB("i2c0", 87, R7S9210_CLK_P1),
97
98 DEF_MOD_STB("spi2", 95, R7S9210_CLK_P1),
99 DEF_MOD_STB("spi1", 96, R7S9210_CLK_P1),
100 DEF_MOD_STB("spi0", 97, R7S9210_CLK_P1),
101};
102
103/* The clock dividers in the table vary based on DT and register settings */
104static void __init r7s9210_update_clk_table(struct clk *extal_clk,
105 void __iomem *base)
106{
107 int i;
108 u16 frqcr;
109 u8 index;
110
111 /* If EXTAL is above 12MHz, then we know it is Mode 1 */
112 if (clk_get_rate(extal_clk) > 12000000)
113 cpg_mode = 1;
114
115 frqcr = clk_readl(base + CPG_FRQCR) & 0xFFF;
116 if (frqcr == 0x012)
117 index = 0;
118 else if (frqcr == 0x112)
119 index = 1;
120 else if (frqcr == 0x212)
121 index = 2;
122 else if (frqcr == 0x322)
123 index = 3;
124 else if (frqcr == 0x333)
125 index = 4;
126 else
127 BUG_ON(1); /* Illegal FRQCR value */
128
129 for (i = 0; i < ARRAY_SIZE(r7s9210_core_clks); i++) {
130 switch (r7s9210_core_clks[i].id) {
131 case R7S9210_CLK_I:
132 r7s9210_core_clks[i].div = ratio_tab[index].i;
133 break;
134 case R7S9210_CLK_G:
135 r7s9210_core_clks[i].div = ratio_tab[index].g;
136 break;
137 case R7S9210_CLK_B:
138 r7s9210_core_clks[i].div = ratio_tab[index].b;
139 break;
140 case R7S9210_CLK_P1:
141 case R7S9210_CLK_P1C:
142 r7s9210_core_clks[i].div = ratio_tab[index].p1;
143 break;
144 case R7S9210_CLK_P0:
145 r7s9210_core_clks[i].div = 32;
146 break;
147 }
148 }
149}
150
151struct clk * __init rza2_cpg_clk_register(struct device *dev,
152 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
153 struct clk **clks, void __iomem *base,
154 struct raw_notifier_head *notifiers)
155{
156 struct clk *parent;
157 unsigned int mult = 1;
158 unsigned int div = 1;
159
160 parent = clks[core->parent];
161 if (IS_ERR(parent))
162 return ERR_CAST(parent);
163
164 switch (core->id) {
165 case CLK_MAIN:
166 break;
167
168 case CLK_PLL:
169 if (cpg_mode)
170 mult = 44; /* Divider 1 is 1/2 */
171 else
172 mult = 88; /* Divider 1 is 1 */
173 break;
174
175 default:
176 return ERR_PTR(-EINVAL);
177 }
178
179 if (core->id == CLK_MAIN)
180 r7s9210_update_clk_table(parent, base);
181
182 return clk_register_fixed_factor(NULL, core->name,
183 __clk_get_name(parent), 0, mult, div);
184}
185
186const struct cpg_mssr_info r7s9210_cpg_mssr_info __initconst = {
187 /* Early Clocks */
188 .early_core_clks = r7s9210_early_core_clks,
189 .num_early_core_clks = ARRAY_SIZE(r7s9210_early_core_clks),
190 .early_mod_clks = r7s9210_early_mod_clks,
191 .num_early_mod_clks = ARRAY_SIZE(r7s9210_early_mod_clks),
192
193 /* Core Clocks */
194 .core_clks = r7s9210_core_clks,
195 .num_core_clks = ARRAY_SIZE(r7s9210_core_clks),
196 .last_dt_core_clk = LAST_DT_CORE_CLK,
197 .num_total_core_clks = MOD_CLK_BASE,
198
199 /* Module Clocks */
200 .mod_clks = r7s9210_mod_clks,
201 .num_mod_clks = ARRAY_SIZE(r7s9210_mod_clks),
202 .num_hw_mod_clks = 11 * 32, /* includes STBCR0 which doesn't exist */
203
204 /* Callbacks */
205 .cpg_clk_register = rza2_cpg_clk_register,
206
207 /* RZ/A2 has Standby Control Registers */
208 .stbyctrl = true,
209};
210
211static void __init r7s9210_cpg_mssr_early_init(struct device_node *np)
212{
213 cpg_mssr_early_init(np, &r7s9210_cpg_mssr_info);
214}
215
216CLK_OF_DECLARE_DRIVER(cpg_mstp_clks, "renesas,r7s9210-cpg-mssr",
217 r7s9210_cpg_mssr_early_init);
diff --git a/drivers/clk/renesas/r8a7743-cpg-mssr.c b/drivers/clk/renesas/r8a7743-cpg-mssr.c
index 011c170ec3f9..c01d9af2525a 100644
--- a/drivers/clk/renesas/r8a7743-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7743-cpg-mssr.c
@@ -1,16 +1,14 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * r8a7743 Clock Pulse Generator / Module Standby and Software Reset 3 * r8a7743 Clock Pulse Generator / Module Standby and Software Reset
3 * 4 *
4 * Copyright (C) 2016 Cogent Embedded Inc. 5 * Copyright (C) 2016 Cogent Embedded Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation; of the License.
9 */ 6 */
10 7
11#include <linux/device.h> 8#include <linux/device.h>
12#include <linux/init.h> 9#include <linux/init.h>
13#include <linux/kernel.h> 10#include <linux/kernel.h>
11#include <linux/of.h>
14#include <linux/soc/renesas/rcar-rst.h> 12#include <linux/soc/renesas/rcar-rst.h>
15 13
16#include <dt-bindings/clock/r8a7743-cpg-mssr.h> 14#include <dt-bindings/clock/r8a7743-cpg-mssr.h>
@@ -37,7 +35,7 @@ enum clk_ids {
37 MOD_CLK_BASE 35 MOD_CLK_BASE
38}; 36};
39 37
40static const struct cpg_core_clk r8a7743_core_clks[] __initconst = { 38static struct cpg_core_clk r8a7743_core_clks[] __initdata = {
41 /* External Clock Inputs */ 39 /* External Clock Inputs */
42 DEF_INPUT("extal", CLK_EXTAL), 40 DEF_INPUT("extal", CLK_EXTAL),
43 DEF_INPUT("usb_extal", CLK_USB_EXTAL), 41 DEF_INPUT("usb_extal", CLK_USB_EXTAL),
@@ -238,6 +236,8 @@ static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
238static int __init r8a7743_cpg_mssr_init(struct device *dev) 236static int __init r8a7743_cpg_mssr_init(struct device *dev)
239{ 237{
240 const struct rcar_gen2_cpg_pll_config *cpg_pll_config; 238 const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
239 struct device_node *np = dev->of_node;
240 unsigned int i;
241 u32 cpg_mode; 241 u32 cpg_mode;
242 int error; 242 int error;
243 243
@@ -247,6 +247,14 @@ static int __init r8a7743_cpg_mssr_init(struct device *dev)
247 247
248 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 248 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
249 249
250 if (of_device_is_compatible(np, "renesas,r8a7744-cpg-mssr")) {
251 /* RZ/G1N uses a 1/5 divider for ZG */
252 for (i = 0; i < ARRAY_SIZE(r8a7743_core_clks); i++)
253 if (r8a7743_core_clks[i].id == R8A7743_CLK_ZG) {
254 r8a7743_core_clks[i].div = 5;
255 break;
256 }
257 }
250 return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode); 258 return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
251} 259}
252 260
diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas/r8a7745-cpg-mssr.c
index 4b0a9243b748..493874e5ebee 100644
--- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
@@ -1,11 +1,8 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * r8a7745 Clock Pulse Generator / Module Standby and Software Reset 3 * r8a7745 Clock Pulse Generator / Module Standby and Software Reset
3 * 4 *
4 * Copyright (C) 2016 Cogent Embedded Inc. 5 * Copyright (C) 2016 Cogent Embedded Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation; of the License.
9 */ 6 */
10 7
11#include <linux/device.h> 8#include <linux/device.h>
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
new file mode 100644
index 000000000000..b0da34217bdf
--- /dev/null
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -0,0 +1,323 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * r8a774a1 Clock Pulse Generator / Module Standby and Software Reset
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 *
7 * Based on r8a7796-cpg-mssr.c
8 *
9 * Copyright (C) 2016 Glider bvba
10 */
11
12#include <linux/device.h>
13#include <linux/init.h>
14#include <linux/kernel.h>
15#include <linux/soc/renesas/rcar-rst.h>
16
17#include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
18
19#include "renesas-cpg-mssr.h"
20#include "rcar-gen3-cpg.h"
21
22enum clk_ids {
23 /* Core Clock Outputs exported to DT */
24 LAST_DT_CORE_CLK = R8A774A1_CLK_OSC,
25
26 /* External Input Clocks */
27 CLK_EXTAL,
28 CLK_EXTALR,
29
30 /* Internal Core Clocks */
31 CLK_MAIN,
32 CLK_PLL0,
33 CLK_PLL1,
34 CLK_PLL2,
35 CLK_PLL3,
36 CLK_PLL4,
37 CLK_PLL1_DIV2,
38 CLK_PLL1_DIV4,
39 CLK_S0,
40 CLK_S1,
41 CLK_S2,
42 CLK_S3,
43 CLK_SDSRC,
44 CLK_RINT,
45
46 /* Module Clocks */
47 MOD_CLK_BASE
48};
49
50static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
51 /* External Clock Inputs */
52 DEF_INPUT("extal", CLK_EXTAL),
53 DEF_INPUT("extalr", CLK_EXTALR),
54
55 /* Internal Core Clocks */
56 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
57 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
58 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
59 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
60 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
61 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
62
63 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
64 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
65 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
66 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
67 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
68 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
69 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
70
71 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
72
73 /* Core Clock Outputs */
74 DEF_BASE("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
75 DEF_BASE("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
76 DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
77 DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
78 DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
79 DEF_FIXED("zx", R8A774A1_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
80 DEF_FIXED("s0d1", R8A774A1_CLK_S0D1, CLK_S0, 1, 1),
81 DEF_FIXED("s0d2", R8A774A1_CLK_S0D2, CLK_S0, 2, 1),
82 DEF_FIXED("s0d3", R8A774A1_CLK_S0D3, CLK_S0, 3, 1),
83 DEF_FIXED("s0d4", R8A774A1_CLK_S0D4, CLK_S0, 4, 1),
84 DEF_FIXED("s0d6", R8A774A1_CLK_S0D6, CLK_S0, 6, 1),
85 DEF_FIXED("s0d8", R8A774A1_CLK_S0D8, CLK_S0, 8, 1),
86 DEF_FIXED("s0d12", R8A774A1_CLK_S0D12, CLK_S0, 12, 1),
87 DEF_FIXED("s1d2", R8A774A1_CLK_S1D2, CLK_S1, 2, 1),
88 DEF_FIXED("s1d4", R8A774A1_CLK_S1D4, CLK_S1, 4, 1),
89 DEF_FIXED("s2d1", R8A774A1_CLK_S2D1, CLK_S2, 1, 1),
90 DEF_FIXED("s2d2", R8A774A1_CLK_S2D2, CLK_S2, 2, 1),
91 DEF_FIXED("s2d4", R8A774A1_CLK_S2D4, CLK_S2, 4, 1),
92 DEF_FIXED("s3d1", R8A774A1_CLK_S3D1, CLK_S3, 1, 1),
93 DEF_FIXED("s3d2", R8A774A1_CLK_S3D2, CLK_S3, 2, 1),
94 DEF_FIXED("s3d4", R8A774A1_CLK_S3D4, CLK_S3, 4, 1),
95
96 DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, CLK_SDSRC, 0x074),
97 DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078),
98 DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268),
99 DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c),
100
101 DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
102 DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1),
103
104 DEF_DIV6P1("csi0", R8A774A1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
105 DEF_DIV6P1("mso", R8A774A1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
106 DEF_DIV6P1("hdmi", R8A774A1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
107
108 DEF_GEN3_OSC("osc", R8A774A1_CLK_OSC, CLK_EXTAL, 8),
109
110 DEF_BASE("r", R8A774A1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
111};
112
113static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
114 DEF_MOD("fdp1-0", 119, R8A774A1_CLK_S0D1),
115 DEF_MOD("scif5", 202, R8A774A1_CLK_S3D4),
116 DEF_MOD("scif4", 203, R8A774A1_CLK_S3D4),
117 DEF_MOD("scif3", 204, R8A774A1_CLK_S3D4),
118 DEF_MOD("scif1", 206, R8A774A1_CLK_S3D4),
119 DEF_MOD("scif0", 207, R8A774A1_CLK_S3D4),
120 DEF_MOD("msiof3", 208, R8A774A1_CLK_MSO),
121 DEF_MOD("msiof2", 209, R8A774A1_CLK_MSO),
122 DEF_MOD("msiof1", 210, R8A774A1_CLK_MSO),
123 DEF_MOD("msiof0", 211, R8A774A1_CLK_MSO),
124 DEF_MOD("sys-dmac2", 217, R8A774A1_CLK_S0D3),
125 DEF_MOD("sys-dmac1", 218, R8A774A1_CLK_S0D3),
126 DEF_MOD("sys-dmac0", 219, R8A774A1_CLK_S0D3),
127 DEF_MOD("cmt3", 300, R8A774A1_CLK_R),
128 DEF_MOD("cmt2", 301, R8A774A1_CLK_R),
129 DEF_MOD("cmt1", 302, R8A774A1_CLK_R),
130 DEF_MOD("cmt0", 303, R8A774A1_CLK_R),
131 DEF_MOD("scif2", 310, R8A774A1_CLK_S3D4),
132 DEF_MOD("sdif3", 311, R8A774A1_CLK_SD3),
133 DEF_MOD("sdif2", 312, R8A774A1_CLK_SD2),
134 DEF_MOD("sdif1", 313, R8A774A1_CLK_SD1),
135 DEF_MOD("sdif0", 314, R8A774A1_CLK_SD0),
136 DEF_MOD("pcie1", 318, R8A774A1_CLK_S3D1),
137 DEF_MOD("pcie0", 319, R8A774A1_CLK_S3D1),
138 DEF_MOD("usb3-if0", 328, R8A774A1_CLK_S3D1),
139 DEF_MOD("usb-dmac0", 330, R8A774A1_CLK_S3D1),
140 DEF_MOD("usb-dmac1", 331, R8A774A1_CLK_S3D1),
141 DEF_MOD("rwdt", 402, R8A774A1_CLK_R),
142 DEF_MOD("intc-ex", 407, R8A774A1_CLK_CP),
143 DEF_MOD("intc-ap", 408, R8A774A1_CLK_S0D3),
144 DEF_MOD("audmac1", 501, R8A774A1_CLK_S0D3),
145 DEF_MOD("audmac0", 502, R8A774A1_CLK_S0D3),
146 DEF_MOD("hscif4", 516, R8A774A1_CLK_S3D1),
147 DEF_MOD("hscif3", 517, R8A774A1_CLK_S3D1),
148 DEF_MOD("hscif2", 518, R8A774A1_CLK_S3D1),
149 DEF_MOD("hscif1", 519, R8A774A1_CLK_S3D1),
150 DEF_MOD("hscif0", 520, R8A774A1_CLK_S3D1),
151 DEF_MOD("thermal", 522, R8A774A1_CLK_CP),
152 DEF_MOD("pwm", 523, R8A774A1_CLK_S0D12),
153 DEF_MOD("fcpvd2", 601, R8A774A1_CLK_S0D2),
154 DEF_MOD("fcpvd1", 602, R8A774A1_CLK_S0D2),
155 DEF_MOD("fcpvd0", 603, R8A774A1_CLK_S0D2),
156 DEF_MOD("fcpvb0", 607, R8A774A1_CLK_S0D1),
157 DEF_MOD("fcpvi0", 611, R8A774A1_CLK_S0D1),
158 DEF_MOD("fcpf0", 615, R8A774A1_CLK_S0D1),
159 DEF_MOD("fcpci0", 617, R8A774A1_CLK_S0D2),
160 DEF_MOD("fcpcs", 619, R8A774A1_CLK_S0D2),
161 DEF_MOD("vspd2", 621, R8A774A1_CLK_S0D2),
162 DEF_MOD("vspd1", 622, R8A774A1_CLK_S0D2),
163 DEF_MOD("vspd0", 623, R8A774A1_CLK_S0D2),
164 DEF_MOD("vspb", 626, R8A774A1_CLK_S0D1),
165 DEF_MOD("vspi0", 631, R8A774A1_CLK_S0D1),
166 DEF_MOD("ehci1", 702, R8A774A1_CLK_S3D4),
167 DEF_MOD("ehci0", 703, R8A774A1_CLK_S3D4),
168 DEF_MOD("hsusb", 704, R8A774A1_CLK_S3D4),
169 DEF_MOD("csi20", 714, R8A774A1_CLK_CSI0),
170 DEF_MOD("csi40", 716, R8A774A1_CLK_CSI0),
171 DEF_MOD("du2", 722, R8A774A1_CLK_S2D1),
172 DEF_MOD("du1", 723, R8A774A1_CLK_S2D1),
173 DEF_MOD("du0", 724, R8A774A1_CLK_S2D1),
174 DEF_MOD("lvds", 727, R8A774A1_CLK_S2D1),
175 DEF_MOD("hdmi0", 729, R8A774A1_CLK_HDMI),
176 DEF_MOD("vin7", 804, R8A774A1_CLK_S0D2),
177 DEF_MOD("vin6", 805, R8A774A1_CLK_S0D2),
178 DEF_MOD("vin5", 806, R8A774A1_CLK_S0D2),
179 DEF_MOD("vin4", 807, R8A774A1_CLK_S0D2),
180 DEF_MOD("vin3", 808, R8A774A1_CLK_S0D2),
181 DEF_MOD("vin2", 809, R8A774A1_CLK_S0D2),
182 DEF_MOD("vin1", 810, R8A774A1_CLK_S0D2),
183 DEF_MOD("vin0", 811, R8A774A1_CLK_S0D2),
184 DEF_MOD("etheravb", 812, R8A774A1_CLK_S0D6),
185 DEF_MOD("gpio7", 905, R8A774A1_CLK_S3D4),
186 DEF_MOD("gpio6", 906, R8A774A1_CLK_S3D4),
187 DEF_MOD("gpio5", 907, R8A774A1_CLK_S3D4),
188 DEF_MOD("gpio4", 908, R8A774A1_CLK_S3D4),
189 DEF_MOD("gpio3", 909, R8A774A1_CLK_S3D4),
190 DEF_MOD("gpio2", 910, R8A774A1_CLK_S3D4),
191 DEF_MOD("gpio1", 911, R8A774A1_CLK_S3D4),
192 DEF_MOD("gpio0", 912, R8A774A1_CLK_S3D4),
193 DEF_MOD("can-if1", 915, R8A774A1_CLK_S3D4),
194 DEF_MOD("can-if0", 916, R8A774A1_CLK_S3D4),
195 DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6),
196 DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6),
197 DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP),
198 DEF_MOD("i2c4", 927, R8A774A1_CLK_S0D6),
199 DEF_MOD("i2c3", 928, R8A774A1_CLK_S0D6),
200 DEF_MOD("i2c2", 929, R8A774A1_CLK_S3D2),
201 DEF_MOD("i2c1", 930, R8A774A1_CLK_S3D2),
202 DEF_MOD("i2c0", 931, R8A774A1_CLK_S3D2),
203 DEF_MOD("ssi-all", 1005, R8A774A1_CLK_S3D4),
204 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
205 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
206 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
207 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
208 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
209 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
210 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
211 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
212 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
213 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
214 DEF_MOD("scu-all", 1017, R8A774A1_CLK_S3D4),
215 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
216 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
217 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
218 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
219 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
220 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
221 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
222 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
223 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
224 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
225 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
226 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
227 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
228 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
229};
230
231static const unsigned int r8a774a1_crit_mod_clks[] __initconst = {
232 MOD_CLK_ID(408), /* INTC-AP (GIC) */
233};
234
235/*
236 * CPG Clock Data
237 */
238
239/*
240 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
241 * 14 13 19 17 (MHz)
242 *-------------------------------------------------------------------------
243 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
244 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
245 * 0 0 1 0 Prohibited setting
246 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
247 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
248 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
249 * 0 1 1 0 Prohibited setting
250 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
251 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
252 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
253 * 1 0 1 0 Prohibited setting
254 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
255 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
256 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
257 * 1 1 1 0 Prohibited setting
258 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
259 */
260#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
261 (((md) & BIT(13)) >> 11) | \
262 (((md) & BIT(19)) >> 18) | \
263 (((md) & BIT(17)) >> 17))
264
265static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
266 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
267 { 1, 192, 1, 192, 1, 16, },
268 { 1, 192, 1, 128, 1, 16, },
269 { 0, /* Prohibited setting */ },
270 { 1, 192, 1, 192, 1, 16, },
271 { 1, 160, 1, 160, 1, 19, },
272 { 1, 160, 1, 106, 1, 19, },
273 { 0, /* Prohibited setting */ },
274 { 1, 160, 1, 160, 1, 19, },
275 { 1, 128, 1, 128, 1, 24, },
276 { 1, 128, 1, 84, 1, 24, },
277 { 0, /* Prohibited setting */ },
278 { 1, 128, 1, 128, 1, 24, },
279 { 2, 192, 1, 192, 1, 32, },
280 { 2, 192, 1, 128, 1, 32, },
281 { 0, /* Prohibited setting */ },
282 { 2, 192, 1, 192, 1, 32, },
283};
284
285static int __init r8a774a1_cpg_mssr_init(struct device *dev)
286{
287 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
288 u32 cpg_mode;
289 int error;
290
291 error = rcar_rst_read_mode_pins(&cpg_mode);
292 if (error)
293 return error;
294
295 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
296 if (!cpg_pll_config->extal_div) {
297 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
298 return -EINVAL;
299 }
300
301 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
302}
303
304const struct cpg_mssr_info r8a774a1_cpg_mssr_info __initconst = {
305 /* Core Clocks */
306 .core_clks = r8a774a1_core_clks,
307 .num_core_clks = ARRAY_SIZE(r8a774a1_core_clks),
308 .last_dt_core_clk = LAST_DT_CORE_CLK,
309 .num_total_core_clks = MOD_CLK_BASE,
310
311 /* Module Clocks */
312 .mod_clks = r8a774a1_mod_clks,
313 .num_mod_clks = ARRAY_SIZE(r8a774a1_mod_clks),
314 .num_hw_mod_clks = 12 * 32,
315
316 /* Critical Module Clocks */
317 .crit_mod_clks = r8a774a1_crit_mod_clks,
318 .num_crit_mod_clks = ARRAY_SIZE(r8a774a1_crit_mod_clks),
319
320 /* Callbacks */
321 .init = r8a774a1_cpg_mssr_init,
322 .cpg_clk_register = rcar_gen3_cpg_clk_register,
323};
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
new file mode 100644
index 000000000000..10b96895d452
--- /dev/null
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -0,0 +1,286 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * r8a774c0 Clock Pulse Generator / Module Standby and Software Reset
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 *
7 * Based on r8a77990-cpg-mssr.c
8 *
9 * Copyright (C) 2015 Glider bvba
10 * Copyright (C) 2015 Renesas Electronics Corp.
11 */
12
13#include <linux/device.h>
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/soc/renesas/rcar-rst.h>
17
18#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
19
20#include "renesas-cpg-mssr.h"
21#include "rcar-gen3-cpg.h"
22
23enum clk_ids {
24 /* Core Clock Outputs exported to DT */
25 LAST_DT_CORE_CLK = R8A774C0_CLK_CPEX,
26
27 /* External Input Clocks */
28 CLK_EXTAL,
29
30 /* Internal Core Clocks */
31 CLK_MAIN,
32 CLK_PLL0,
33 CLK_PLL1,
34 CLK_PLL3,
35 CLK_PLL0D4,
36 CLK_PLL0D8,
37 CLK_PLL0D20,
38 CLK_PLL0D24,
39 CLK_PLL1D2,
40 CLK_PE,
41 CLK_S0,
42 CLK_S1,
43 CLK_S2,
44 CLK_S3,
45 CLK_SDSRC,
46 CLK_RINT,
47 CLK_OCO,
48
49 /* Module Clocks */
50 MOD_CLK_BASE
51};
52
53static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
54 /* External Clock Inputs */
55 DEF_INPUT("extal", CLK_EXTAL),
56
57 /* Internal Core Clocks */
58 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
59 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
60 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
61
62 DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100),
63 DEF_FIXED(".pll0d4", CLK_PLL0D4, CLK_PLL0, 4, 1),
64 DEF_FIXED(".pll0d8", CLK_PLL0D8, CLK_PLL0, 8, 1),
65 DEF_FIXED(".pll0d20", CLK_PLL0D20, CLK_PLL0, 20, 1),
66 DEF_FIXED(".pll0d24", CLK_PLL0D24, CLK_PLL0, 24, 1),
67 DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
68 DEF_FIXED(".pe", CLK_PE, CLK_PLL0D20, 1, 1),
69 DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
70 DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
71 DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
72 DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
73 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
74
75 DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
76
77 DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
78
79 /* Core Clock Outputs */
80 DEF_FIXED("za2", R8A774C0_CLK_ZA2, CLK_PLL0D24, 1, 1),
81 DEF_FIXED("za8", R8A774C0_CLK_ZA8, CLK_PLL0D8, 1, 1),
82 DEF_FIXED("ztr", R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1),
83 DEF_FIXED("zt", R8A774C0_CLK_ZT, CLK_PLL1, 4, 1),
84 DEF_FIXED("zx", R8A774C0_CLK_ZX, CLK_PLL1, 3, 1),
85 DEF_FIXED("s0d1", R8A774C0_CLK_S0D1, CLK_S0, 1, 1),
86 DEF_FIXED("s0d3", R8A774C0_CLK_S0D3, CLK_S0, 3, 1),
87 DEF_FIXED("s0d6", R8A774C0_CLK_S0D6, CLK_S0, 6, 1),
88 DEF_FIXED("s0d12", R8A774C0_CLK_S0D12, CLK_S0, 12, 1),
89 DEF_FIXED("s0d24", R8A774C0_CLK_S0D24, CLK_S0, 24, 1),
90 DEF_FIXED("s1d1", R8A774C0_CLK_S1D1, CLK_S1, 1, 1),
91 DEF_FIXED("s1d2", R8A774C0_CLK_S1D2, CLK_S1, 2, 1),
92 DEF_FIXED("s1d4", R8A774C0_CLK_S1D4, CLK_S1, 4, 1),
93 DEF_FIXED("s2d1", R8A774C0_CLK_S2D1, CLK_S2, 1, 1),
94 DEF_FIXED("s2d2", R8A774C0_CLK_S2D2, CLK_S2, 2, 1),
95 DEF_FIXED("s2d4", R8A774C0_CLK_S2D4, CLK_S2, 4, 1),
96 DEF_FIXED("s3d1", R8A774C0_CLK_S3D1, CLK_S3, 1, 1),
97 DEF_FIXED("s3d2", R8A774C0_CLK_S3D2, CLK_S3, 2, 1),
98 DEF_FIXED("s3d4", R8A774C0_CLK_S3D4, CLK_S3, 4, 1),
99
100 DEF_GEN3_SD("sd0", R8A774C0_CLK_SD0, CLK_SDSRC, 0x0074),
101 DEF_GEN3_SD("sd1", R8A774C0_CLK_SD1, CLK_SDSRC, 0x0078),
102 DEF_GEN3_SD("sd3", R8A774C0_CLK_SD3, CLK_SDSRC, 0x026c),
103
104 DEF_FIXED("cl", R8A774C0_CLK_CL, CLK_PLL1, 48, 1),
105 DEF_FIXED("cp", R8A774C0_CLK_CP, CLK_EXTAL, 2, 1),
106 DEF_FIXED("cpex", R8A774C0_CLK_CPEX, CLK_EXTAL, 4, 1),
107
108 DEF_DIV6_RO("osc", R8A774C0_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
109
110 DEF_GEN3_PE("s0d6c", R8A774C0_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),
111 DEF_GEN3_PE("s3d1c", R8A774C0_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
112 DEF_GEN3_PE("s3d2c", R8A774C0_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
113 DEF_GEN3_PE("s3d4c", R8A774C0_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
114
115 DEF_DIV6P1("csi0", R8A774C0_CLK_CSI0, CLK_PLL1D2, 0x00c),
116 DEF_DIV6P1("mso", R8A774C0_CLK_MSO, CLK_PLL1D2, 0x014),
117
118 DEF_GEN3_RCKSEL("r", R8A774C0_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
119};
120
121static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
122 DEF_MOD("scif5", 202, R8A774C0_CLK_S3D4C),
123 DEF_MOD("scif4", 203, R8A774C0_CLK_S3D4C),
124 DEF_MOD("scif3", 204, R8A774C0_CLK_S3D4C),
125 DEF_MOD("scif1", 206, R8A774C0_CLK_S3D4C),
126 DEF_MOD("scif0", 207, R8A774C0_CLK_S3D4C),
127 DEF_MOD("msiof3", 208, R8A774C0_CLK_MSO),
128 DEF_MOD("msiof2", 209, R8A774C0_CLK_MSO),
129 DEF_MOD("msiof1", 210, R8A774C0_CLK_MSO),
130 DEF_MOD("msiof0", 211, R8A774C0_CLK_MSO),
131 DEF_MOD("sys-dmac2", 217, R8A774C0_CLK_S3D1),
132 DEF_MOD("sys-dmac1", 218, R8A774C0_CLK_S3D1),
133 DEF_MOD("sys-dmac0", 219, R8A774C0_CLK_S3D1),
134
135 DEF_MOD("cmt3", 300, R8A774C0_CLK_R),
136 DEF_MOD("cmt2", 301, R8A774C0_CLK_R),
137 DEF_MOD("cmt1", 302, R8A774C0_CLK_R),
138 DEF_MOD("cmt0", 303, R8A774C0_CLK_R),
139 DEF_MOD("scif2", 310, R8A774C0_CLK_S3D4C),
140 DEF_MOD("sdif3", 311, R8A774C0_CLK_SD3),
141 DEF_MOD("sdif1", 313, R8A774C0_CLK_SD1),
142 DEF_MOD("sdif0", 314, R8A774C0_CLK_SD0),
143 DEF_MOD("pcie0", 319, R8A774C0_CLK_S3D1),
144 DEF_MOD("usb3-if0", 328, R8A774C0_CLK_S3D1),
145 DEF_MOD("usb-dmac0", 330, R8A774C0_CLK_S3D1),
146 DEF_MOD("usb-dmac1", 331, R8A774C0_CLK_S3D1),
147
148 DEF_MOD("rwdt", 402, R8A774C0_CLK_R),
149 DEF_MOD("intc-ex", 407, R8A774C0_CLK_CP),
150 DEF_MOD("intc-ap", 408, R8A774C0_CLK_S0D3),
151
152 DEF_MOD("audmac0", 502, R8A774C0_CLK_S3D4),
153 DEF_MOD("hscif4", 516, R8A774C0_CLK_S3D1C),
154 DEF_MOD("hscif3", 517, R8A774C0_CLK_S3D1C),
155 DEF_MOD("hscif2", 518, R8A774C0_CLK_S3D1C),
156 DEF_MOD("hscif1", 519, R8A774C0_CLK_S3D1C),
157 DEF_MOD("hscif0", 520, R8A774C0_CLK_S3D1C),
158 DEF_MOD("thermal", 522, R8A774C0_CLK_CP),
159 DEF_MOD("pwm", 523, R8A774C0_CLK_S3D4C),
160
161 DEF_MOD("fcpvd1", 602, R8A774C0_CLK_S1D2),
162 DEF_MOD("fcpvd0", 603, R8A774C0_CLK_S1D2),
163 DEF_MOD("fcpvb0", 607, R8A774C0_CLK_S0D1),
164 DEF_MOD("fcpvi0", 611, R8A774C0_CLK_S0D1),
165 DEF_MOD("fcpf0", 615, R8A774C0_CLK_S0D1),
166 DEF_MOD("fcpcs", 619, R8A774C0_CLK_S0D1),
167 DEF_MOD("vspd1", 622, R8A774C0_CLK_S1D2),
168 DEF_MOD("vspd0", 623, R8A774C0_CLK_S1D2),
169 DEF_MOD("vspb", 626, R8A774C0_CLK_S0D1),
170 DEF_MOD("vspi0", 631, R8A774C0_CLK_S0D1),
171
172 DEF_MOD("ehci0", 703, R8A774C0_CLK_S3D4),
173 DEF_MOD("hsusb", 704, R8A774C0_CLK_S3D4),
174 DEF_MOD("csi40", 716, R8A774C0_CLK_CSI0),
175 DEF_MOD("du1", 723, R8A774C0_CLK_S2D1),
176 DEF_MOD("du0", 724, R8A774C0_CLK_S2D1),
177 DEF_MOD("lvds", 727, R8A774C0_CLK_S2D1),
178
179 DEF_MOD("vin5", 806, R8A774C0_CLK_S1D2),
180 DEF_MOD("vin4", 807, R8A774C0_CLK_S1D2),
181 DEF_MOD("etheravb", 812, R8A774C0_CLK_S3D2),
182
183 DEF_MOD("gpio6", 906, R8A774C0_CLK_S3D4),
184 DEF_MOD("gpio5", 907, R8A774C0_CLK_S3D4),
185 DEF_MOD("gpio4", 908, R8A774C0_CLK_S3D4),
186 DEF_MOD("gpio3", 909, R8A774C0_CLK_S3D4),
187 DEF_MOD("gpio2", 910, R8A774C0_CLK_S3D4),
188 DEF_MOD("gpio1", 911, R8A774C0_CLK_S3D4),
189 DEF_MOD("gpio0", 912, R8A774C0_CLK_S3D4),
190 DEF_MOD("can-if1", 915, R8A774C0_CLK_S3D4),
191 DEF_MOD("can-if0", 916, R8A774C0_CLK_S3D4),
192 DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2),
193 DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2),
194 DEF_MOD("i2c-dvfs", 926, R8A774C0_CLK_CP),
195 DEF_MOD("i2c4", 927, R8A774C0_CLK_S3D2),
196 DEF_MOD("i2c3", 928, R8A774C0_CLK_S3D2),
197 DEF_MOD("i2c2", 929, R8A774C0_CLK_S3D2),
198 DEF_MOD("i2c1", 930, R8A774C0_CLK_S3D2),
199 DEF_MOD("i2c0", 931, R8A774C0_CLK_S3D2),
200
201 DEF_MOD("i2c7", 1003, R8A774C0_CLK_S3D2),
202 DEF_MOD("ssi-all", 1005, R8A774C0_CLK_S3D4),
203 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
204 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
205 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
206 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
207 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
208 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
209 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
210 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
211 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
212 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
213 DEF_MOD("scu-all", 1017, R8A774C0_CLK_S3D4),
214 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
215 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
216 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
217 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
218 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
219 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
220 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
221 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
222 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
223 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
224 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
225 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
226 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
227 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
228};
229
230static const unsigned int r8a774c0_crit_mod_clks[] __initconst = {
231 MOD_CLK_ID(408), /* INTC-AP (GIC) */
232};
233
234/*
235 * CPG Clock Data
236 */
237
238/*
239 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
240 *--------------------------------------------------------------------
241 * 0 48 x 1 x100/1 x100/3 x100/3
242 * 1 48 x 1 x100/1 x100/3 x58/3
243 */
244#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
245
246static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
247 /* EXTAL div PLL1 mult/div PLL3 mult/div */
248 { 1, 100, 3, 100, 3, },
249 { 1, 100, 3, 58, 3, },
250};
251
252static int __init r8a774c0_cpg_mssr_init(struct device *dev)
253{
254 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
255 u32 cpg_mode;
256 int error;
257
258 error = rcar_rst_read_mode_pins(&cpg_mode);
259 if (error)
260 return error;
261
262 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
263
264 return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
265}
266
267const struct cpg_mssr_info r8a774c0_cpg_mssr_info __initconst = {
268 /* Core Clocks */
269 .core_clks = r8a774c0_core_clks,
270 .num_core_clks = ARRAY_SIZE(r8a774c0_core_clks),
271 .last_dt_core_clk = LAST_DT_CORE_CLK,
272 .num_total_core_clks = MOD_CLK_BASE,
273
274 /* Module Clocks */
275 .mod_clks = r8a774c0_mod_clks,
276 .num_mod_clks = ARRAY_SIZE(r8a774c0_mod_clks),
277 .num_hw_mod_clks = 12 * 32,
278
279 /* Critical Module Clocks */
280 .crit_mod_clks = r8a774c0_crit_mod_clks,
281 .num_crit_mod_clks = ARRAY_SIZE(r8a774c0_crit_mod_clks),
282
283 /* Callbacks */
284 .init = r8a774c0_cpg_mssr_init,
285 .cpg_clk_register = rcar_gen3_cpg_clk_register,
286};
diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c b/drivers/clk/renesas/r8a7790-cpg-mssr.c
index f936cb74b681..c57cb93f8315 100644
--- a/drivers/clk/renesas/r8a7790-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * r8a7790 Clock Pulse Generator / Module Standby and Software Reset 3 * r8a7790 Clock Pulse Generator / Module Standby and Software Reset
3 * 4 *
@@ -6,10 +7,6 @@
6 * Based on clk-rcar-gen2.c 7 * Based on clk-rcar-gen2.c
7 * 8 *
8 * Copyright (C) 2013 Ideas On Board SPRL 9 * Copyright (C) 2013 Ideas On Board SPRL
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 */ 10 */
14 11
15#include <linux/device.h> 12#include <linux/device.h>
diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c b/drivers/clk/renesas/r8a7791-cpg-mssr.c
index 1b91f03b7598..65702debcabb 100644
--- a/drivers/clk/renesas/r8a7791-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * r8a7791 Clock Pulse Generator / Module Standby and Software Reset 3 * r8a7791 Clock Pulse Generator / Module Standby and Software Reset
3 * 4 *
@@ -6,10 +7,6 @@
6 * Based on clk-rcar-gen2.c 7 * Based on clk-rcar-gen2.c
7 * 8 *
8 * Copyright (C) 2013 Ideas On Board SPRL 9 * Copyright (C) 2013 Ideas On Board SPRL
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 */ 10 */
14 11
15#include <linux/device.h> 12#include <linux/device.h>
diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c
index 493e07859f5f..cf8b84a3a060 100644
--- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * r8a7792 Clock Pulse Generator / Module Standby and Software Reset 3 * r8a7792 Clock Pulse Generator / Module Standby and Software Reset
3 * 4 *
@@ -6,10 +7,6 @@
6 * Based on clk-rcar-gen2.c 7 * Based on clk-rcar-gen2.c
7 * 8 *
8 * Copyright (C) 2013 Ideas On Board SPRL 9 * Copyright (C) 2013 Ideas On Board SPRL
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 */ 10 */
14 11
15#include <linux/device.h> 12#include <linux/device.h>
diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c
index 088f4b79fdfc..c1948693c5c1 100644
--- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * r8a7794 Clock Pulse Generator / Module Standby and Software Reset 3 * r8a7794 Clock Pulse Generator / Module Standby and Software Reset
3 * 4 *
@@ -6,10 +7,6 @@
6 * Based on clk-rcar-gen2.c 7 * Based on clk-rcar-gen2.c
7 * 8 *
8 * Copyright (C) 2013 Ideas On Board SPRL 9 * Copyright (C) 2013 Ideas On Board SPRL
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 */ 10 */
14 11
15#include <linux/device.h> 12#include <linux/device.h>
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index a85dd50e8911..119c02440726 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset 3 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
3 * 4 *
@@ -6,10 +7,6 @@
6 * Based on clk-rcar-gen3.c 7 * Based on clk-rcar-gen3.c
7 * 8 *
8 * Copyright (C) 2015 Renesas Electronics Corp. 9 * Copyright (C) 2015 Renesas Electronics Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 */ 10 */
14 11
15#include <linux/device.h> 12#include <linux/device.h>
@@ -73,6 +70,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
73 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), 70 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
74 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), 71 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
75 72
73 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
74
76 /* Core Clock Outputs */ 75 /* Core Clock Outputs */
77 DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), 76 DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
78 DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), 77 DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
@@ -111,8 +110,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
111 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014), 110 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
112 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250), 111 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
113 112
114 DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), 113 DEF_GEN3_OSC("osc", R8A7795_CLK_OSC, CLK_EXTAL, 8),
115 DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
116 114
117 DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), 115 DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
118}; 116};
@@ -283,25 +281,25 @@ static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
283 */ 281 */
284 282
285/* 283/*
286 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 284 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
287 * 14 13 19 17 (MHz) 285 * 14 13 19 17 (MHz)
288 *------------------------------------------------------------------- 286 *-------------------------------------------------------------------------
289 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 287 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
290 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 288 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
291 * 0 0 1 0 Prohibited setting 289 * 0 0 1 0 Prohibited setting
292 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 290 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
293 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 291 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
294 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 292 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
295 * 0 1 1 0 Prohibited setting 293 * 0 1 1 0 Prohibited setting
296 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 294 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
297 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 295 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
298 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 296 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
299 * 1 0 1 0 Prohibited setting 297 * 1 0 1 0 Prohibited setting
300 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 298 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
301 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 299 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
302 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 300 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
303 * 1 1 1 0 Prohibited setting 301 * 1 1 1 0 Prohibited setting
304 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 302 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
305 */ 303 */
306#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ 304#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
307 (((md) & BIT(13)) >> 11) | \ 305 (((md) & BIT(13)) >> 11) | \
@@ -309,23 +307,23 @@ static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
309 (((md) & BIT(17)) >> 17)) 307 (((md) & BIT(17)) >> 17))
310 308
311static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { 309static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
312 /* EXTAL div PLL1 mult/div PLL3 mult/div */ 310 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
313 { 1, 192, 1, 192, 1, }, 311 { 1, 192, 1, 192, 1, 16, },
314 { 1, 192, 1, 128, 1, }, 312 { 1, 192, 1, 128, 1, 16, },
315 { 0, /* Prohibited setting */ }, 313 { 0, /* Prohibited setting */ },
316 { 1, 192, 1, 192, 1, }, 314 { 1, 192, 1, 192, 1, 16, },
317 { 1, 160, 1, 160, 1, }, 315 { 1, 160, 1, 160, 1, 19, },
318 { 1, 160, 1, 106, 1, }, 316 { 1, 160, 1, 106, 1, 19, },
319 { 0, /* Prohibited setting */ }, 317 { 0, /* Prohibited setting */ },
320 { 1, 160, 1, 160, 1, }, 318 { 1, 160, 1, 160, 1, 19, },
321 { 1, 128, 1, 128, 1, }, 319 { 1, 128, 1, 128, 1, 24, },
322 { 1, 128, 1, 84, 1, }, 320 { 1, 128, 1, 84, 1, 24, },
323 { 0, /* Prohibited setting */ }, 321 { 0, /* Prohibited setting */ },
324 { 1, 128, 1, 128, 1, }, 322 { 1, 128, 1, 128, 1, 24, },
325 { 2, 192, 1, 192, 1, }, 323 { 2, 192, 1, 192, 1, 32, },
326 { 2, 192, 1, 128, 1, }, 324 { 2, 192, 1, 128, 1, 32, },
327 { 0, /* Prohibited setting */ }, 325 { 0, /* Prohibited setting */ },
328 { 2, 192, 1, 192, 1, }, 326 { 2, 192, 1, 192, 1, 32, },
329}; 327};
330 328
331static const struct soc_device_attribute r8a7795es1[] __initconst = { 329static const struct soc_device_attribute r8a7795es1[] __initconst = {
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index dfb267a92f2a..10567386e6dd 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset 3 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
3 * 4 *
@@ -7,10 +8,6 @@
7 * 8 *
8 * Copyright (C) 2015 Glider bvba 9 * Copyright (C) 2015 Glider bvba
9 * Copyright (C) 2015 Renesas Electronics Corp. 10 * Copyright (C) 2015 Renesas Electronics Corp.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 */ 11 */
15 12
16#include <linux/device.h> 13#include <linux/device.h>
@@ -73,6 +70,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
73 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), 70 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
74 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), 71 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
75 72
73 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
74
76 /* Core Clock Outputs */ 75 /* Core Clock Outputs */
77 DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), 76 DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
78 DEF_BASE("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), 77 DEF_BASE("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
@@ -110,8 +109,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
110 DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014), 109 DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014),
111 DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250), 110 DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
112 111
113 DEF_DIV6_RO("osc", R8A7796_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), 112 DEF_GEN3_OSC("osc", R8A7796_CLK_OSC, CLK_EXTAL, 8),
114 DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
115 113
116 DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), 114 DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
117}; 115};
@@ -255,25 +253,25 @@ static const unsigned int r8a7796_crit_mod_clks[] __initconst = {
255 */ 253 */
256 254
257/* 255/*
258 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 256 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
259 * 14 13 19 17 (MHz) 257 * 14 13 19 17 (MHz)
260 *------------------------------------------------------------------- 258 *-------------------------------------------------------------------------
261 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 259 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
262 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 260 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
263 * 0 0 1 0 Prohibited setting 261 * 0 0 1 0 Prohibited setting
264 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 262 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
265 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 263 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
266 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 264 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
267 * 0 1 1 0 Prohibited setting 265 * 0 1 1 0 Prohibited setting
268 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 266 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
269 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 267 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
270 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 268 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
271 * 1 0 1 0 Prohibited setting 269 * 1 0 1 0 Prohibited setting
272 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 270 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
273 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 271 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
274 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 272 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
275 * 1 1 1 0 Prohibited setting 273 * 1 1 1 0 Prohibited setting
276 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 274 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
277 */ 275 */
278#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ 276#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
279 (((md) & BIT(13)) >> 11) | \ 277 (((md) & BIT(13)) >> 11) | \
@@ -281,23 +279,23 @@ static const unsigned int r8a7796_crit_mod_clks[] __initconst = {
281 (((md) & BIT(17)) >> 17)) 279 (((md) & BIT(17)) >> 17))
282 280
283static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { 281static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
284 /* EXTAL div PLL1 mult/div PLL3 mult/div */ 282 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
285 { 1, 192, 1, 192, 1, }, 283 { 1, 192, 1, 192, 1, 16, },
286 { 1, 192, 1, 128, 1, }, 284 { 1, 192, 1, 128, 1, 16, },
287 { 0, /* Prohibited setting */ }, 285 { 0, /* Prohibited setting */ },
288 { 1, 192, 1, 192, 1, }, 286 { 1, 192, 1, 192, 1, 16, },
289 { 1, 160, 1, 160, 1, }, 287 { 1, 160, 1, 160, 1, 19, },
290 { 1, 160, 1, 106, 1, }, 288 { 1, 160, 1, 106, 1, 19, },
291 { 0, /* Prohibited setting */ }, 289 { 0, /* Prohibited setting */ },
292 { 1, 160, 1, 160, 1, }, 290 { 1, 160, 1, 160, 1, 19, },
293 { 1, 128, 1, 128, 1, }, 291 { 1, 128, 1, 128, 1, 24, },
294 { 1, 128, 1, 84, 1, }, 292 { 1, 128, 1, 84, 1, 24, },
295 { 0, /* Prohibited setting */ }, 293 { 0, /* Prohibited setting */ },
296 { 1, 128, 1, 128, 1, }, 294 { 1, 128, 1, 128, 1, 24, },
297 { 2, 192, 1, 192, 1, }, 295 { 2, 192, 1, 192, 1, 32, },
298 { 2, 192, 1, 128, 1, }, 296 { 2, 192, 1, 128, 1, 32, },
299 { 0, /* Prohibited setting */ }, 297 { 0, /* Prohibited setting */ },
300 { 2, 192, 1, 192, 1, }, 298 { 2, 192, 1, 192, 1, 32, },
301}; 299};
302 300
303static int __init r8a7796_cpg_mssr_init(struct device *dev) 301static int __init r8a7796_cpg_mssr_init(struct device *dev)
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index 8fae5e9c4a77..1fcc411502da 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -68,6 +68,8 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
68 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), 68 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
69 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), 69 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
70 70
71 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
72
71 /* Core Clock Outputs */ 73 /* Core Clock Outputs */
72 DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), 74 DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
73 DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 75 DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
@@ -104,13 +106,13 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
104 DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014), 106 DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014),
105 DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250), 107 DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
106 108
107 DEF_DIV6_RO("osc", R8A77965_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), 109 DEF_GEN3_OSC("osc", R8A77965_CLK_OSC, CLK_EXTAL, 8),
108 DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
109 110
110 DEF_BASE("r", R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), 111 DEF_BASE("r", R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
111}; 112};
112 113
113static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { 114static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
115 DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
114 DEF_MOD("scif5", 202, R8A77965_CLK_S3D4), 116 DEF_MOD("scif5", 202, R8A77965_CLK_S3D4),
115 DEF_MOD("scif4", 203, R8A77965_CLK_S3D4), 117 DEF_MOD("scif4", 203, R8A77965_CLK_S3D4),
116 DEF_MOD("scif3", 204, R8A77965_CLK_S3D4), 118 DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),
@@ -192,6 +194,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
192 DEF_MOD("vin1", 810, R8A77965_CLK_S0D2), 194 DEF_MOD("vin1", 810, R8A77965_CLK_S0D2),
193 DEF_MOD("vin0", 811, R8A77965_CLK_S0D2), 195 DEF_MOD("vin0", 811, R8A77965_CLK_S0D2),
194 DEF_MOD("etheravb", 812, R8A77965_CLK_S0D6), 196 DEF_MOD("etheravb", 812, R8A77965_CLK_S0D6),
197 DEF_MOD("sata0", 815, R8A77965_CLK_S3D2),
195 DEF_MOD("imr1", 822, R8A77965_CLK_S0D2), 198 DEF_MOD("imr1", 822, R8A77965_CLK_S0D2),
196 DEF_MOD("imr0", 823, R8A77965_CLK_S0D2), 199 DEF_MOD("imr0", 823, R8A77965_CLK_S0D2),
197 200
@@ -252,25 +255,25 @@ static const unsigned int r8a77965_crit_mod_clks[] __initconst = {
252 */ 255 */
253 256
254/* 257/*
255 * MD EXTAL PLL0 PLL1 PLL3 PLL4 258 * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
256 * 14 13 19 17 (MHz) 259 * 14 13 19 17 (MHz)
257 *----------------------------------------------------------- 260 *-----------------------------------------------------------------
258 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 261 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
259 * 0 0 0 1 16.66 x 1 x180 x192 x128 x144 262 * 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16
260 * 0 0 1 0 Prohibited setting 263 * 0 0 1 0 Prohibited setting
261 * 0 0 1 1 16.66 x 1 x180 x192 x192 x144 264 * 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16
262 * 0 1 0 0 20 x 1 x150 x160 x160 x120 265 * 0 1 0 0 20 x 1 x150 x160 x160 x120 /19
263 * 0 1 0 1 20 x 1 x150 x160 x106 x120 266 * 0 1 0 1 20 x 1 x150 x160 x106 x120 /19
264 * 0 1 1 0 Prohibited setting 267 * 0 1 1 0 Prohibited setting
265 * 0 1 1 1 20 x 1 x150 x160 x160 x120 268 * 0 1 1 1 20 x 1 x150 x160 x160 x120 /19
266 * 1 0 0 0 25 x 1 x120 x128 x128 x96 269 * 1 0 0 0 25 x 1 x120 x128 x128 x96 /24
267 * 1 0 0 1 25 x 1 x120 x128 x84 x96 270 * 1 0 0 1 25 x 1 x120 x128 x84 x96 /24
268 * 1 0 1 0 Prohibited setting 271 * 1 0 1 0 Prohibited setting
269 * 1 0 1 1 25 x 1 x120 x128 x128 x96 272 * 1 0 1 1 25 x 1 x120 x128 x128 x96 /24
270 * 1 1 0 0 33.33 / 2 x180 x192 x192 x144 273 * 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32
271 * 1 1 0 1 33.33 / 2 x180 x192 x128 x144 274 * 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32
272 * 1 1 1 0 Prohibited setting 275 * 1 1 1 0 Prohibited setting
273 * 1 1 1 1 33.33 / 2 x180 x192 x192 x144 276 * 1 1 1 1 33.33 / 2 x180 x192 x192 x144 /32
274 */ 277 */
275#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ 278#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
276 (((md) & BIT(13)) >> 11) | \ 279 (((md) & BIT(13)) >> 11) | \
@@ -278,23 +281,23 @@ static const unsigned int r8a77965_crit_mod_clks[] __initconst = {
278 (((md) & BIT(17)) >> 17)) 281 (((md) & BIT(17)) >> 17))
279 282
280static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { 283static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
281 /* EXTAL div PLL1 mult/div PLL3 mult/div */ 284 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
282 { 1, 192, 1, 192, 1, }, 285 { 1, 192, 1, 192, 1, 16, },
283 { 1, 192, 1, 128, 1, }, 286 { 1, 192, 1, 128, 1, 16, },
284 { 0, /* Prohibited setting */ }, 287 { 0, /* Prohibited setting */ },
285 { 1, 192, 1, 192, 1, }, 288 { 1, 192, 1, 192, 1, 16, },
286 { 1, 160, 1, 160, 1, }, 289 { 1, 160, 1, 160, 1, 19, },
287 { 1, 160, 1, 106, 1, }, 290 { 1, 160, 1, 106, 1, 19, },
288 { 0, /* Prohibited setting */ }, 291 { 0, /* Prohibited setting */ },
289 { 1, 160, 1, 160, 1, }, 292 { 1, 160, 1, 160, 1, 19, },
290 { 1, 128, 1, 128, 1, }, 293 { 1, 128, 1, 128, 1, 24, },
291 { 1, 128, 1, 84, 1, }, 294 { 1, 128, 1, 84, 1, 24, },
292 { 0, /* Prohibited setting */ }, 295 { 0, /* Prohibited setting */ },
293 { 1, 128, 1, 128, 1, }, 296 { 1, 128, 1, 128, 1, 24, },
294 { 2, 192, 1, 192, 1, }, 297 { 2, 192, 1, 192, 1, 32, },
295 { 2, 192, 1, 128, 1, }, 298 { 2, 192, 1, 128, 1, 32, },
296 { 0, /* Prohibited setting */ }, 299 { 0, /* Prohibited setting */ },
297 { 2, 192, 1, 192, 1, }, 300 { 2, 192, 1, 192, 1, 32, },
298}; 301};
299 302
300static int __init r8a77965_cpg_mssr_init(struct device *dev) 303static int __init r8a77965_cpg_mssr_init(struct device *dev)
diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c
index f55842917e8d..2015e45543e9 100644
--- a/drivers/clk/renesas/r8a77970-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -1,17 +1,15 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * r8a77970 Clock Pulse Generator / Module Standby and Software Reset 3 * r8a77970 Clock Pulse Generator / Module Standby and Software Reset
3 * 4 *
4 * Copyright (C) 2017 Cogent Embedded Inc. 5 * Copyright (C) 2017-2018 Cogent Embedded Inc.
5 * 6 *
6 * Based on r8a7795-cpg-mssr.c 7 * Based on r8a7795-cpg-mssr.c
7 * 8 *
8 * Copyright (C) 2015 Glider bvba 9 * Copyright (C) 2015 Glider bvba
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 */ 10 */
14 11
12#include <linux/clk-provider.h>
15#include <linux/device.h> 13#include <linux/device.h>
16#include <linux/init.h> 14#include <linux/init.h>
17#include <linux/kernel.h> 15#include <linux/kernel.h>
@@ -22,6 +20,13 @@
22#include "renesas-cpg-mssr.h" 20#include "renesas-cpg-mssr.h"
23#include "rcar-gen3-cpg.h" 21#include "rcar-gen3-cpg.h"
24 22
23#define CPG_SD0CKCR 0x0074
24
25enum r8a77970_clk_types {
26 CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE,
27 CLK_TYPE_R8A77970_SD0,
28};
29
25enum clk_ids { 30enum clk_ids {
26 /* Core Clock Outputs exported to DT */ 31 /* Core Clock Outputs exported to DT */
27 LAST_DT_CORE_CLK = R8A77970_CLK_OSC, 32 LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
@@ -42,6 +47,20 @@ enum clk_ids {
42 MOD_CLK_BASE 47 MOD_CLK_BASE
43}; 48};
44 49
50static spinlock_t cpg_lock;
51
52static const struct clk_div_table cpg_sd0h_div_table[] = {
53 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
54 { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
55 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
56};
57
58static const struct clk_div_table cpg_sd0_div_table[] = {
59 { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
60 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
61 { 0, 0 },
62};
63
45static const struct cpg_core_clk r8a77970_core_clks[] __initconst = { 64static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
46 /* External Clock Inputs */ 65 /* External Clock Inputs */
47 DEF_INPUT("extal", CLK_EXTAL), 66 DEF_INPUT("extal", CLK_EXTAL),
@@ -68,6 +87,10 @@ static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
68 DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_PLL1_DIV2, 12, 1), 87 DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_PLL1_DIV2, 12, 1),
69 DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_PLL1_DIV2, 24, 1), 88 DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_PLL1_DIV2, 24, 1),
70 89
90 DEF_BASE("sd0h", R8A77970_CLK_SD0H, CLK_TYPE_R8A77970_SD0H,
91 CLK_PLL1_DIV2),
92 DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2),
93
71 DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1), 94 DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
72 DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1), 95 DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
73 96
@@ -80,6 +103,11 @@ static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
80}; 103};
81 104
82static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = { 105static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
106 DEF_MOD("tmu4", 121, R8A77970_CLK_S2D2),
107 DEF_MOD("tmu3", 122, R8A77970_CLK_S2D2),
108 DEF_MOD("tmu2", 123, R8A77970_CLK_S2D2),
109 DEF_MOD("tmu1", 124, R8A77970_CLK_S2D2),
110 DEF_MOD("tmu0", 125, R8A77970_CLK_CP),
83 DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1), 111 DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
84 DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), 112 DEF_MOD("scif4", 203, R8A77970_CLK_S2D4),
85 DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), 113 DEF_MOD("scif3", 204, R8A77970_CLK_S2D4),
@@ -92,6 +120,12 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
92 DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), 120 DEF_MOD("mfis", 213, R8A77970_CLK_S2D2),
93 DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), 121 DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
94 DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), 122 DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
123 DEF_MOD("cmt3", 300, R8A77970_CLK_R),
124 DEF_MOD("cmt2", 301, R8A77970_CLK_R),
125 DEF_MOD("cmt1", 302, R8A77970_CLK_R),
126 DEF_MOD("cmt0", 303, R8A77970_CLK_R),
127 DEF_MOD("tpu0", 304, R8A77970_CLK_S2D4),
128 DEF_MOD("sd-if", 314, R8A77970_CLK_SD0),
95 DEF_MOD("rwdt", 402, R8A77970_CLK_R), 129 DEF_MOD("rwdt", 402, R8A77970_CLK_R),
96 DEF_MOD("intc-ex", 407, R8A77970_CLK_CP), 130 DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
97 DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), 131 DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1),
@@ -173,11 +207,46 @@ static int __init r8a77970_cpg_mssr_init(struct device *dev)
173 if (error) 207 if (error)
174 return error; 208 return error;
175 209
210 spin_lock_init(&cpg_lock);
211
176 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 212 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
177 213
178 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); 214 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
179} 215}
180 216
217static struct clk * __init r8a77970_cpg_clk_register(struct device *dev,
218 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
219 struct clk **clks, void __iomem *base,
220 struct raw_notifier_head *notifiers)
221{
222 const struct clk_div_table *table;
223 const struct clk *parent;
224 unsigned int shift;
225
226 switch (core->type) {
227 case CLK_TYPE_R8A77970_SD0H:
228 table = cpg_sd0h_div_table;
229 shift = 8;
230 break;
231 case CLK_TYPE_R8A77970_SD0:
232 table = cpg_sd0_div_table;
233 shift = 4;
234 break;
235 default:
236 return rcar_gen3_cpg_clk_register(dev, core, info, clks, base,
237 notifiers);
238 }
239
240 parent = clks[core->parent];
241 if (IS_ERR(parent))
242 return ERR_CAST(parent);
243
244 return clk_register_divider_table(NULL, core->name,
245 __clk_get_name(parent), 0,
246 base + CPG_SD0CKCR,
247 shift, 4, 0, table, &cpg_lock);
248}
249
181const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = { 250const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = {
182 /* Core Clocks */ 251 /* Core Clocks */
183 .core_clks = r8a77970_core_clks, 252 .core_clks = r8a77970_core_clks,
@@ -196,5 +265,5 @@ const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = {
196 265
197 /* Callbacks */ 266 /* Callbacks */
198 .init = r8a77970_cpg_mssr_init, 267 .init = r8a77970_cpg_mssr_init,
199 .cpg_clk_register = rcar_gen3_cpg_clk_register, 268 .cpg_clk_register = r8a77970_cpg_clk_register,
200}; 269};
diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c
index d7ebd9ec0059..25a3083b6764 100644
--- a/drivers/clk/renesas/r8a77980-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -41,6 +41,7 @@ enum clk_ids {
41 CLK_S2, 41 CLK_S2,
42 CLK_S3, 42 CLK_S3,
43 CLK_SDSRC, 43 CLK_SDSRC,
44 CLK_OCO,
44 45
45 /* Module Clocks */ 46 /* Module Clocks */
46 MOD_CLK_BASE 47 MOD_CLK_BASE
@@ -64,6 +65,7 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
64 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), 65 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
65 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), 66 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
66 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), 67 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
68 DEF_RATE(".oco", CLK_OCO, 32768),
67 69
68 /* Core Clock Outputs */ 70 /* Core Clock Outputs */
69 DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 71 DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
@@ -96,6 +98,9 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
96 DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244), 98 DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
97 DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), 99 DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
98 DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014), 100 DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014),
101
102 DEF_GEN3_OSC("osc", R8A77980_CLK_OSC, CLK_EXTAL, 8),
103 DEF_GEN3_MDSEL("r", R8A77980_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
99}; 104};
100 105
101static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = { 106static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
@@ -114,9 +119,14 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
114 DEF_MOD("msiof0", 211, R8A77980_CLK_MSO), 119 DEF_MOD("msiof0", 211, R8A77980_CLK_MSO),
115 DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3), 120 DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
116 DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3), 121 DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
122 DEF_MOD("cmt3", 300, R8A77980_CLK_R),
123 DEF_MOD("cmt2", 301, R8A77980_CLK_R),
124 DEF_MOD("cmt1", 302, R8A77980_CLK_R),
125 DEF_MOD("cmt0", 303, R8A77980_CLK_R),
117 DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4), 126 DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4),
118 DEF_MOD("sdif", 314, R8A77980_CLK_SD0), 127 DEF_MOD("sdif", 314, R8A77980_CLK_SD0),
119 DEF_MOD("pciec0", 319, R8A77980_CLK_S2D2), 128 DEF_MOD("pciec0", 319, R8A77980_CLK_S2D2),
129 DEF_MOD("rwdt", 402, R8A77980_CLK_R),
120 DEF_MOD("intc-ex", 407, R8A77980_CLK_CP), 130 DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
121 DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3), 131 DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
122 DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1), 132 DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1),
@@ -171,23 +181,23 @@ static const unsigned int r8a77980_crit_mod_clks[] __initconst = {
171 */ 181 */
172 182
173/* 183/*
174 * MD EXTAL PLL2 PLL1 PLL3 184 * MD EXTAL PLL2 PLL1 PLL3 OSC
175 * 14 13 (MHz) 185 * 14 13 (MHz)
176 * -------------------------------------------------- 186 * --------------------------------------------------------
177 * 0 0 16.66 x 1 x240 x192 x192 187 * 0 0 16.66 x 1 x240 x192 x192 /16
178 * 0 1 20 x 1 x200 x160 x160 188 * 0 1 20 x 1 x200 x160 x160 /19
179 * 1 0 27 x 1 x148 x118 x118 189 * 1 0 27 x 1 x148 x118 x118 /26
180 * 1 1 33.33 / 2 x240 x192 x192 190 * 1 1 33.33 / 2 x240 x192 x192 /32
181 */ 191 */
182#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ 192#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
183 (((md) & BIT(13)) >> 13)) 193 (((md) & BIT(13)) >> 13))
184 194
185static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = { 195static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = {
186 /* EXTAL div PLL1 mult/div PLL3 mult/div */ 196 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
187 { 1, 192, 1, 192, 1, }, 197 { 1, 192, 1, 192, 1, 16, },
188 { 1, 160, 1, 160, 1, }, 198 { 1, 160, 1, 160, 1, 19, },
189 { 1, 118, 1, 118, 1, }, 199 { 1, 118, 1, 118, 1, 26, },
190 { 2, 192, 1, 192, 1, }, 200 { 2, 192, 1, 192, 1, 32, },
191}; 201};
192 202
193static int __init r8a77980_cpg_mssr_init(struct device *dev) 203static int __init r8a77980_cpg_mssr_init(struct device *dev)
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 9e14f1486fbb..9eb80180eea0 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -44,6 +44,8 @@ enum clk_ids {
44 CLK_S2, 44 CLK_S2,
45 CLK_S3, 45 CLK_S3,
46 CLK_SDSRC, 46 CLK_SDSRC,
47 CLK_RINT,
48 CLK_OCO,
47 49
48 /* Module Clocks */ 50 /* Module Clocks */
49 MOD_CLK_BASE 51 MOD_CLK_BASE
@@ -72,6 +74,10 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
72 DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), 74 DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
73 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), 75 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
74 76
77 DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
78
79 DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
80
75 /* Core Clock Outputs */ 81 /* Core Clock Outputs */
76 DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1), 82 DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1),
77 DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1), 83 DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1),
@@ -100,8 +106,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
100 DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1), 106 DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
101 DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1), 107 DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1),
102 DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1), 108 DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1),
103 DEF_FIXED("osc", R8A77990_CLK_OSC, CLK_EXTAL, 384, 1), 109
104 DEF_FIXED("r", R8A77990_CLK_R, CLK_EXTAL, 1536, 1), 110 DEF_DIV6_RO("osc", R8A77990_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
105 111
106 DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2), 112 DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),
107 DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), 113 DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
@@ -111,6 +117,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
111 DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244), 117 DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
112 DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c), 118 DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c),
113 DEF_DIV6P1("mso", R8A77990_CLK_MSO, CLK_PLL1D2, 0x014), 119 DEF_DIV6P1("mso", R8A77990_CLK_MSO, CLK_PLL1D2, 0x014),
120
121 DEF_GEN3_RCKSEL("r", R8A77990_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
114}; 122};
115 123
116static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = { 124static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
@@ -202,6 +210,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
202 DEF_MOD("i2c1", 930, R8A77990_CLK_S3D2), 210 DEF_MOD("i2c1", 930, R8A77990_CLK_S3D2),
203 DEF_MOD("i2c0", 931, R8A77990_CLK_S3D2), 211 DEF_MOD("i2c0", 931, R8A77990_CLK_S3D2),
204 212
213 DEF_MOD("i2c7", 1003, R8A77990_CLK_S3D2),
205 DEF_MOD("ssi-all", 1005, R8A77990_CLK_S3D4), 214 DEF_MOD("ssi-all", 1005, R8A77990_CLK_S3D4),
206 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), 215 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
207 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), 216 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
@@ -241,8 +250,8 @@ static const unsigned int r8a77990_crit_mod_clks[] __initconst = {
241/* 250/*
242 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3 251 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
243 *-------------------------------------------------------------------- 252 *--------------------------------------------------------------------
244 * 0 48 x 1 x100/4 x100/3 x100/3 253 * 0 48 x 1 x100/1 x100/3 x100/3
245 * 1 48 x 1 x100/4 x100/3 x58/3 254 * 1 48 x 1 x100/1 x100/3 x58/3
246 */ 255 */
247#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19) 256#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
248 257
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index ea4cafbe6e85..47e60e3dbe05 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * r8a77995 Clock Pulse Generator / Module Standby and Software Reset 3 * r8a77995 Clock Pulse Generator / Module Standby and Software Reset
3 * 4 *
@@ -7,10 +8,6 @@
7 * 8 *
8 * Copyright (C) 2015 Glider bvba 9 * Copyright (C) 2015 Glider bvba
9 * Copyright (C) 2015 Renesas Electronics Corp. 10 * Copyright (C) 2015 Renesas Electronics Corp.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 */ 11 */
15 12
16#include <linux/device.h> 13#include <linux/device.h>
@@ -46,6 +43,8 @@ enum clk_ids {
46 CLK_S3, 43 CLK_S3,
47 CLK_SDSRC, 44 CLK_SDSRC,
48 CLK_SSPSRC, 45 CLK_SSPSRC,
46 CLK_RINT,
47 CLK_OCO,
49 48
50 /* Module Clocks */ 49 /* Module Clocks */
51 MOD_CLK_BASE 50 MOD_CLK_BASE
@@ -72,6 +71,10 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
72 DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), 71 DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
73 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), 72 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
74 73
74 DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
75
76 DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
77
75 /* Core Clock Outputs */ 78 /* Core Clock Outputs */
76 DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1), 79 DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
77 DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1), 80 DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
@@ -90,8 +93,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
90 93
91 DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1), 94 DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
92 DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1), 95 DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
93 DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1), 96
94 DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1), 97 DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
95 98
96 DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2), 99 DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
97 DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), 100 DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
@@ -102,6 +105,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
102 105
103 DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244), 106 DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244),
104 DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014), 107 DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014),
108
109 DEF_GEN3_RCKSEL("r", R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
105}; 110};
106 111
107static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = { 112static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c
index a0b6ecdc63dd..6d2b56891559 100644
--- a/drivers/clk/renesas/r9a06g032-clocks.c
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -539,7 +539,8 @@ r9a06g032_div_round_rate(struct clk_hw *hw,
539 * several uarts attached to this divider, and changing this impacts 539 * several uarts attached to this divider, and changing this impacts
540 * everyone. 540 * everyone.
541 */ 541 */
542 if (clk->index == R9A06G032_DIV_UART) { 542 if (clk->index == R9A06G032_DIV_UART ||
543 clk->index == R9A06G032_DIV_P2_PG) {
543 pr_devel("%s div uart hack!\n", __func__); 544 pr_devel("%s div uart hack!\n", __func__);
544 return clk_get_rate(hw->clk); 545 return clk_get_rate(hw->clk);
545 } 546 }
diff --git a/drivers/clk/renesas/rcar-gen2-cpg.c b/drivers/clk/renesas/rcar-gen2-cpg.c
index daf88bc2cdae..f596a2dafcf4 100644
--- a/drivers/clk/renesas/rcar-gen2-cpg.c
+++ b/drivers/clk/renesas/rcar-gen2-cpg.c
@@ -1,11 +1,8 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * R-Car Gen2 Clock Pulse Generator 3 * R-Car Gen2 Clock Pulse Generator
3 * 4 *
4 * Copyright (C) 2016 Cogent Embedded Inc. 5 * Copyright (C) 2016 Cogent Embedded Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */ 6 */
10 7
11#include <linux/bug.h> 8#include <linux/bug.h>
diff --git a/drivers/clk/renesas/rcar-gen2-cpg.h b/drivers/clk/renesas/rcar-gen2-cpg.h
index 020a3baad015..bff9551c7a38 100644
--- a/drivers/clk/renesas/rcar-gen2-cpg.h
+++ b/drivers/clk/renesas/rcar-gen2-cpg.h
@@ -1,11 +1,8 @@
1/* 1/* SPDX-License-Identifier: GPL-2.0
2 *
2 * R-Car Gen2 Clock Pulse Generator 3 * R-Car Gen2 Clock Pulse Generator
3 * 4 *
4 * Copyright (C) 2016 Cogent Embedded Inc. 5 * Copyright (C) 2016 Cogent Embedded Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation; version 2 of the License.
9 */ 6 */
10 7
11#ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__ 8#ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 628b63b85d3f..4ba38f98cc7b 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -1,15 +1,12 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * R-Car Gen3 Clock Pulse Generator 3 * R-Car Gen3 Clock Pulse Generator
3 * 4 *
4 * Copyright (C) 2015-2016 Glider bvba 5 * Copyright (C) 2015-2018 Glider bvba
5 * 6 *
6 * Based on clk-rcar-gen3.c 7 * Based on clk-rcar-gen3.c
7 * 8 *
8 * Copyright (C) 2015 Renesas Electronics Corp. 9 * Copyright (C) 2015 Renesas Electronics Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 */ 10 */
14 11
15#include <linux/bug.h> 12#include <linux/bug.h>
@@ -31,6 +28,8 @@
31#define CPG_PLL2CR 0x002c 28#define CPG_PLL2CR 0x002c
32#define CPG_PLL4CR 0x01f4 29#define CPG_PLL4CR 0x01f4
33 30
31#define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
32
34struct cpg_simple_notifier { 33struct cpg_simple_notifier {
35 struct notifier_block nb; 34 struct notifier_block nb;
36 void __iomem *reg; 35 void __iomem *reg;
@@ -444,7 +443,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
444 unsigned int div = 1; 443 unsigned int div = 1;
445 u32 value; 444 u32 value;
446 445
447 parent = clks[core->parent & 0xffff]; /* CLK_TYPE_PE uses high bits */ 446 parent = clks[core->parent & 0xffff]; /* some types use high bits */
448 if (IS_ERR(parent)) 447 if (IS_ERR(parent))
449 return ERR_CAST(parent); 448 return ERR_CAST(parent);
450 449
@@ -524,7 +523,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
524 523
525 if (clk_get_rate(clks[cpg_clk_extalr])) { 524 if (clk_get_rate(clks[cpg_clk_extalr])) {
526 parent = clks[cpg_clk_extalr]; 525 parent = clks[cpg_clk_extalr];
527 value |= BIT(15); 526 value |= CPG_RCKCR_CKSEL;
528 } 527 }
529 528
530 writel(value, csn->reg); 529 writel(value, csn->reg);
@@ -537,16 +536,14 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
537 parent = clks[cpg_clk_extalr]; 536 parent = clks[cpg_clk_extalr];
538 break; 537 break;
539 538
540 case CLK_TYPE_GEN3_PE: 539 case CLK_TYPE_GEN3_MDSEL:
541 /* 540 /*
542 * Peripheral clock with a fixed divider, selectable between 541 * Clock selectable between two parents and two fixed dividers
543 * clean and spread spectrum parents using MD12 542 * using a mode pin
544 */ 543 */
545 if (cpg_mode & BIT(12)) { 544 if (cpg_mode & BIT(core->offset)) {
546 /* Clean */
547 div = core->div & 0xffff; 545 div = core->div & 0xffff;
548 } else { 546 } else {
549 /* SCCG */
550 parent = clks[core->parent >> 16]; 547 parent = clks[core->parent >> 16];
551 if (IS_ERR(parent)) 548 if (IS_ERR(parent))
552 return ERR_CAST(parent); 549 return ERR_CAST(parent);
@@ -563,6 +560,28 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
563 return cpg_z_clk_register(core->name, __clk_get_name(parent), 560 return cpg_z_clk_register(core->name, __clk_get_name(parent),
564 base, CPG_FRQCRC_Z2FC_MASK); 561 base, CPG_FRQCRC_Z2FC_MASK);
565 562
563 case CLK_TYPE_GEN3_OSC:
564 /*
565 * Clock combining OSC EXTAL predivider and a fixed divider
566 */
567 div = cpg_pll_config->osc_prediv * core->div;
568 break;
569
570 case CLK_TYPE_GEN3_RCKSEL:
571 /*
572 * Clock selectable between two parents and two fixed dividers
573 * using RCKCR.CKSEL
574 */
575 if (readl(base + CPG_RCKCR) & CPG_RCKCR_CKSEL) {
576 div = core->div & 0xffff;
577 } else {
578 parent = clks[core->parent >> 16];
579 if (IS_ERR(parent))
580 return ERR_CAST(parent);
581 div = core->div >> 16;
582 }
583 break;
584
566 default: 585 default:
567 return ERR_PTR(-EINVAL); 586 return ERR_PTR(-EINVAL);
568 } 587 }
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index ea4f8fc3c4c9..f4fb6cf16688 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -1,11 +1,9 @@
1/* 1/* SPDX-License-Identifier: GPL-2.0
2 *
2 * R-Car Gen3 Clock Pulse Generator 3 * R-Car Gen3 Clock Pulse Generator
3 * 4 *
4 * Copyright (C) 2015-2016 Glider bvba 5 * Copyright (C) 2015-2018 Glider bvba
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */ 7 */
10 8
11#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__ 9#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
@@ -20,19 +18,35 @@ enum rcar_gen3_clk_types {
20 CLK_TYPE_GEN3_PLL4, 18 CLK_TYPE_GEN3_PLL4,
21 CLK_TYPE_GEN3_SD, 19 CLK_TYPE_GEN3_SD,
22 CLK_TYPE_GEN3_R, 20 CLK_TYPE_GEN3_R,
23 CLK_TYPE_GEN3_PE, 21 CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
24 CLK_TYPE_GEN3_Z, 22 CLK_TYPE_GEN3_Z,
25 CLK_TYPE_GEN3_Z2, 23 CLK_TYPE_GEN3_Z2,
24 CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
25 CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
26
27 /* SoC specific definitions start here */
28 CLK_TYPE_GEN3_SOC_BASE,
26}; 29};
27 30
28#define DEF_GEN3_SD(_name, _id, _parent, _offset) \ 31#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
29 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) 32 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
30 33
34#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
35 DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
36 (_parent0) << 16 | (_parent1), \
37 .div = (_div0) << 16 | (_div1), .offset = _md)
38
31#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ 39#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
32 _div_clean) \ 40 _div_clean) \
33 DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \ 41 DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
34 (_parent_sscg) << 16 | (_parent_clean), \ 42 _parent_clean, _div_clean)
35 .div = (_div_sscg) << 16 | (_div_clean)) 43
44#define DEF_GEN3_OSC(_name, _id, _parent, _div) \
45 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
46
47#define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
48 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
49 (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
36 50
37struct rcar_gen3_cpg_pll_config { 51struct rcar_gen3_cpg_pll_config {
38 u8 extal_div; 52 u8 extal_div;
@@ -40,6 +54,7 @@ struct rcar_gen3_cpg_pll_config {
40 u8 pll1_div; 54 u8 pll1_div;
41 u8 pll3_mult; 55 u8 pll3_mult;
42 u8 pll3_div; 56 u8 pll3_div;
57 u8 osc_prediv;
43}; 58};
44 59
45#define CPG_RCKCR 0x240 60#define CPG_RCKCR 0x240
diff --git a/drivers/clk/renesas/rcar-usb2-clock-sel.c b/drivers/clk/renesas/rcar-usb2-clock-sel.c
index 6cd030a58964..b241f9ca3d71 100644
--- a/drivers/clk/renesas/rcar-usb2-clock-sel.c
+++ b/drivers/clk/renesas/rcar-usb2-clock-sel.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Renesas R-Car USB2.0 clock selector 3 * Renesas R-Car USB2.0 clock selector
3 * 4 *
@@ -6,10 +7,6 @@
6 * Based on renesas-cpg-mssr.c 7 * Based on renesas-cpg-mssr.c
7 * 8 *
8 * Copyright (C) 2015 Glider bvba 9 * Copyright (C) 2015 Glider bvba
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 */ 10 */
14 11
15#include <linux/clk.h> 12#include <linux/clk.h>
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index f4b013e9352d..f7bb817420b4 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Renesas Clock Pulse Generator / Module Standby and Software Reset 3 * Renesas Clock Pulse Generator / Module Standby and Software Reset
3 * 4 *
@@ -7,10 +8,6 @@
7 * 8 *
8 * Copyright (C) 2013 Ideas On Board SPRL 9 * Copyright (C) 2013 Ideas On Board SPRL
9 * Copyright (C) 2015 Renesas Electronics Corp. 10 * Copyright (C) 2015 Renesas Electronics Corp.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 */ 11 */
15 12
16#include <linux/clk.h> 13#include <linux/clk.h>
@@ -73,6 +70,17 @@ static const u16 smstpcr[] = {
73 70
74#define SMSTPCR(i) smstpcr[i] 71#define SMSTPCR(i) smstpcr[i]
75 72
73/*
74 * Standby Control Register offsets (RZ/A)
75 * Base address is FRQCR register
76 */
77
78static const u16 stbcr[] = {
79 0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420,
80 0x424, 0x428, 0x42C,
81};
82
83#define STBCR(i) stbcr[i]
76 84
77/* 85/*
78 * Software Reset Register offsets 86 * Software Reset Register offsets
@@ -110,6 +118,7 @@ static const u16 srcr[] = {
110 * @notifiers: Notifier chain to save/restore clock state for system resume 118 * @notifiers: Notifier chain to save/restore clock state for system resume
111 * @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control 119 * @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control
112 * @smstpcr_saved[].val: Saved values of SMSTPCR[] 120 * @smstpcr_saved[].val: Saved values of SMSTPCR[]
121 * @stbyctrl: This device has Standby Control Registers
113 */ 122 */
114struct cpg_mssr_priv { 123struct cpg_mssr_priv {
115#ifdef CONFIG_RESET_CONTROLLER 124#ifdef CONFIG_RESET_CONTROLLER
@@ -118,11 +127,13 @@ struct cpg_mssr_priv {
118 struct device *dev; 127 struct device *dev;
119 void __iomem *base; 128 void __iomem *base;
120 spinlock_t rmw_lock; 129 spinlock_t rmw_lock;
130 struct device_node *np;
121 131
122 struct clk **clks; 132 struct clk **clks;
123 unsigned int num_core_clks; 133 unsigned int num_core_clks;
124 unsigned int num_mod_clks; 134 unsigned int num_mod_clks;
125 unsigned int last_dt_core_clk; 135 unsigned int last_dt_core_clk;
136 bool stbyctrl;
126 137
127 struct raw_notifier_head notifiers; 138 struct raw_notifier_head notifiers;
128 struct { 139 struct {
@@ -131,6 +142,7 @@ struct cpg_mssr_priv {
131 } smstpcr_saved[ARRAY_SIZE(smstpcr)]; 142 } smstpcr_saved[ARRAY_SIZE(smstpcr)];
132}; 143};
133 144
145static struct cpg_mssr_priv *cpg_mssr_priv;
134 146
135/** 147/**
136 * struct mstp_clock - MSTP gating clock 148 * struct mstp_clock - MSTP gating clock
@@ -162,16 +174,29 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
162 enable ? "ON" : "OFF"); 174 enable ? "ON" : "OFF");
163 spin_lock_irqsave(&priv->rmw_lock, flags); 175 spin_lock_irqsave(&priv->rmw_lock, flags);
164 176
165 value = readl(priv->base + SMSTPCR(reg)); 177 if (priv->stbyctrl) {
166 if (enable) 178 value = readb(priv->base + STBCR(reg));
167 value &= ~bitmask; 179 if (enable)
168 else 180 value &= ~bitmask;
169 value |= bitmask; 181 else
170 writel(value, priv->base + SMSTPCR(reg)); 182 value |= bitmask;
183 writeb(value, priv->base + STBCR(reg));
184
185 /* dummy read to ensure write has completed */
186 readb(priv->base + STBCR(reg));
187 barrier_data(priv->base + STBCR(reg));
188 } else {
189 value = readl(priv->base + SMSTPCR(reg));
190 if (enable)
191 value &= ~bitmask;
192 else
193 value |= bitmask;
194 writel(value, priv->base + SMSTPCR(reg));
195 }
171 196
172 spin_unlock_irqrestore(&priv->rmw_lock, flags); 197 spin_unlock_irqrestore(&priv->rmw_lock, flags);
173 198
174 if (!enable) 199 if (!enable || priv->stbyctrl)
175 return 0; 200 return 0;
176 201
177 for (i = 1000; i > 0; --i) { 202 for (i = 1000; i > 0; --i) {
@@ -205,7 +230,10 @@ static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
205 struct cpg_mssr_priv *priv = clock->priv; 230 struct cpg_mssr_priv *priv = clock->priv;
206 u32 value; 231 u32 value;
207 232
208 value = readl(priv->base + MSTPSR(clock->index / 32)); 233 if (priv->stbyctrl)
234 value = readb(priv->base + STBCR(clock->index / 32));
235 else
236 value = readl(priv->base + MSTPSR(clock->index / 32));
209 237
210 return !(value & BIT(clock->index % 32)); 238 return !(value & BIT(clock->index % 32));
211} 239}
@@ -226,6 +254,7 @@ struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
226 unsigned int idx; 254 unsigned int idx;
227 const char *type; 255 const char *type;
228 struct clk *clk; 256 struct clk *clk;
257 int range_check;
229 258
230 switch (clkspec->args[0]) { 259 switch (clkspec->args[0]) {
231 case CPG_CORE: 260 case CPG_CORE:
@@ -240,8 +269,14 @@ struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
240 269
241 case CPG_MOD: 270 case CPG_MOD:
242 type = "module"; 271 type = "module";
243 idx = MOD_CLK_PACK(clkidx); 272 if (priv->stbyctrl) {
244 if (clkidx % 100 > 31 || idx >= priv->num_mod_clks) { 273 idx = MOD_CLK_PACK_10(clkidx);
274 range_check = 7 - (clkidx % 10);
275 } else {
276 idx = MOD_CLK_PACK(clkidx);
277 range_check = 31 - (clkidx % 100);
278 }
279 if (range_check < 0 || idx >= priv->num_mod_clks) {
245 dev_err(dev, "Invalid %s clock index %u\n", type, 280 dev_err(dev, "Invalid %s clock index %u\n", type,
246 clkidx); 281 clkidx);
247 return ERR_PTR(-EINVAL); 282 return ERR_PTR(-EINVAL);
@@ -283,7 +318,7 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
283 318
284 switch (core->type) { 319 switch (core->type) {
285 case CLK_TYPE_IN: 320 case CLK_TYPE_IN:
286 clk = of_clk_get_by_name(priv->dev->of_node, core->name); 321 clk = of_clk_get_by_name(priv->np, core->name);
287 break; 322 break;
288 323
289 case CLK_TYPE_FF: 324 case CLK_TYPE_FF:
@@ -313,6 +348,11 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
313 } 348 }
314 break; 349 break;
315 350
351 case CLK_TYPE_FR:
352 clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,
353 core->mult);
354 break;
355
316 default: 356 default:
317 if (info->cpg_clk_register) 357 if (info->cpg_clk_register)
318 clk = info->cpg_clk_register(dev, core, info, 358 clk = info->cpg_clk_register(dev, core, info,
@@ -641,11 +681,22 @@ static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
641 681
642 682
643static const struct of_device_id cpg_mssr_match[] = { 683static const struct of_device_id cpg_mssr_match[] = {
684#ifdef CONFIG_CLK_R7S9210
685 {
686 .compatible = "renesas,r7s9210-cpg-mssr",
687 .data = &r7s9210_cpg_mssr_info,
688 },
689#endif
644#ifdef CONFIG_CLK_R8A7743 690#ifdef CONFIG_CLK_R8A7743
645 { 691 {
646 .compatible = "renesas,r8a7743-cpg-mssr", 692 .compatible = "renesas,r8a7743-cpg-mssr",
647 .data = &r8a7743_cpg_mssr_info, 693 .data = &r8a7743_cpg_mssr_info,
648 }, 694 },
695 /* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */
696 {
697 .compatible = "renesas,r8a7744-cpg-mssr",
698 .data = &r8a7743_cpg_mssr_info,
699 },
649#endif 700#endif
650#ifdef CONFIG_CLK_R8A7745 701#ifdef CONFIG_CLK_R8A7745
651 { 702 {
@@ -659,6 +710,18 @@ static const struct of_device_id cpg_mssr_match[] = {
659 .data = &r8a77470_cpg_mssr_info, 710 .data = &r8a77470_cpg_mssr_info,
660 }, 711 },
661#endif 712#endif
713#ifdef CONFIG_CLK_R8A774A1
714 {
715 .compatible = "renesas,r8a774a1-cpg-mssr",
716 .data = &r8a774a1_cpg_mssr_info,
717 },
718#endif
719#ifdef CONFIG_CLK_R8A774C0
720 {
721 .compatible = "renesas,r8a774c0-cpg-mssr",
722 .data = &r8a774c0_cpg_mssr_info,
723 },
724#endif
662#ifdef CONFIG_CLK_R8A7790 725#ifdef CONFIG_CLK_R8A7790
663 { 726 {
664 .compatible = "renesas,r8a7790-cpg-mssr", 727 .compatible = "renesas,r8a7790-cpg-mssr",
@@ -780,13 +843,23 @@ static int cpg_mssr_resume_noirq(struct device *dev)
780 if (!mask) 843 if (!mask)
781 continue; 844 continue;
782 845
783 oldval = readl(priv->base + SMSTPCR(reg)); 846 if (priv->stbyctrl)
847 oldval = readb(priv->base + STBCR(reg));
848 else
849 oldval = readl(priv->base + SMSTPCR(reg));
784 newval = oldval & ~mask; 850 newval = oldval & ~mask;
785 newval |= priv->smstpcr_saved[reg].val & mask; 851 newval |= priv->smstpcr_saved[reg].val & mask;
786 if (newval == oldval) 852 if (newval == oldval)
787 continue; 853 continue;
788 854
789 writel(newval, priv->base + SMSTPCR(reg)); 855 if (priv->stbyctrl) {
856 writeb(newval, priv->base + STBCR(reg));
857 /* dummy read to ensure write has completed */
858 readb(priv->base + STBCR(reg));
859 barrier_data(priv->base + STBCR(reg));
860 continue;
861 } else
862 writel(newval, priv->base + SMSTPCR(reg));
790 863
791 /* Wait until enabled clocks are really enabled */ 864 /* Wait until enabled clocks are really enabled */
792 mask &= ~priv->smstpcr_saved[reg].val; 865 mask &= ~priv->smstpcr_saved[reg].val;
@@ -817,61 +890,115 @@ static const struct dev_pm_ops cpg_mssr_pm = {
817#define DEV_PM_OPS NULL 890#define DEV_PM_OPS NULL
818#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */ 891#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
819 892
820static int __init cpg_mssr_probe(struct platform_device *pdev) 893static int __init cpg_mssr_common_init(struct device *dev,
894 struct device_node *np,
895 const struct cpg_mssr_info *info)
821{ 896{
822 struct device *dev = &pdev->dev;
823 struct device_node *np = dev->of_node;
824 const struct cpg_mssr_info *info;
825 struct cpg_mssr_priv *priv; 897 struct cpg_mssr_priv *priv;
898 struct clk **clks = NULL;
826 unsigned int nclks, i; 899 unsigned int nclks, i;
827 struct resource *res;
828 struct clk **clks;
829 int error; 900 int error;
830 901
831 info = of_device_get_match_data(dev);
832 if (info->init) { 902 if (info->init) {
833 error = info->init(dev); 903 error = info->init(dev);
834 if (error) 904 if (error)
835 return error; 905 return error;
836 } 906 }
837 907
838 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 908 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
839 if (!priv) 909 if (!priv)
840 return -ENOMEM; 910 return -ENOMEM;
841 911
912 priv->np = np;
842 priv->dev = dev; 913 priv->dev = dev;
843 spin_lock_init(&priv->rmw_lock); 914 spin_lock_init(&priv->rmw_lock);
844 915
845 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 916 priv->base = of_iomap(np, 0);
846 priv->base = devm_ioremap_resource(dev, res); 917 if (!priv->base) {
847 if (IS_ERR(priv->base)) 918 error = -ENOMEM;
848 return PTR_ERR(priv->base); 919 goto out_err;
920 }
849 921
850 nclks = info->num_total_core_clks + info->num_hw_mod_clks; 922 nclks = info->num_total_core_clks + info->num_hw_mod_clks;
851 clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL); 923 clks = kmalloc_array(nclks, sizeof(*clks), GFP_KERNEL);
852 if (!clks) 924 if (!clks) {
853 return -ENOMEM; 925 error = -ENOMEM;
926 goto out_err;
927 }
854 928
855 dev_set_drvdata(dev, priv); 929 cpg_mssr_priv = priv;
856 priv->clks = clks; 930 priv->clks = clks;
857 priv->num_core_clks = info->num_total_core_clks; 931 priv->num_core_clks = info->num_total_core_clks;
858 priv->num_mod_clks = info->num_hw_mod_clks; 932 priv->num_mod_clks = info->num_hw_mod_clks;
859 priv->last_dt_core_clk = info->last_dt_core_clk; 933 priv->last_dt_core_clk = info->last_dt_core_clk;
860 RAW_INIT_NOTIFIER_HEAD(&priv->notifiers); 934 RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
935 priv->stbyctrl = info->stbyctrl;
861 936
862 for (i = 0; i < nclks; i++) 937 for (i = 0; i < nclks; i++)
863 clks[i] = ERR_PTR(-ENOENT); 938 clks[i] = ERR_PTR(-ENOENT);
864 939
940 error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
941 if (error)
942 goto out_err;
943
944 return 0;
945
946out_err:
947 kfree(clks);
948 if (priv->base)
949 iounmap(priv->base);
950 kfree(priv);
951
952 return error;
953}
954
955void __init cpg_mssr_early_init(struct device_node *np,
956 const struct cpg_mssr_info *info)
957{
958 int error;
959 int i;
960
961 error = cpg_mssr_common_init(NULL, np, info);
962 if (error)
963 return;
964
965 for (i = 0; i < info->num_early_core_clks; i++)
966 cpg_mssr_register_core_clk(&info->early_core_clks[i], info,
967 cpg_mssr_priv);
968
969 for (i = 0; i < info->num_early_mod_clks; i++)
970 cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info,
971 cpg_mssr_priv);
972
973}
974
975static int __init cpg_mssr_probe(struct platform_device *pdev)
976{
977 struct device *dev = &pdev->dev;
978 struct device_node *np = dev->of_node;
979 const struct cpg_mssr_info *info;
980 struct cpg_mssr_priv *priv;
981 unsigned int i;
982 int error;
983
984 info = of_device_get_match_data(dev);
985
986 if (!cpg_mssr_priv) {
987 error = cpg_mssr_common_init(dev, dev->of_node, info);
988 if (error)
989 return error;
990 }
991
992 priv = cpg_mssr_priv;
993 priv->dev = dev;
994 dev_set_drvdata(dev, priv);
995
865 for (i = 0; i < info->num_core_clks; i++) 996 for (i = 0; i < info->num_core_clks; i++)
866 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv); 997 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
867 998
868 for (i = 0; i < info->num_mod_clks; i++) 999 for (i = 0; i < info->num_mod_clks; i++)
869 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv); 1000 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
870 1001
871 error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
872 if (error)
873 return error;
874
875 error = devm_add_action_or_reset(dev, 1002 error = devm_add_action_or_reset(dev,
876 cpg_mssr_del_clk_provider, 1003 cpg_mssr_del_clk_provider,
877 np); 1004 np);
@@ -883,6 +1010,10 @@ static int __init cpg_mssr_probe(struct platform_device *pdev)
883 if (error) 1010 if (error)
884 return error; 1011 return error;
885 1012
1013 /* Reset Controller not supported for Standby Control SoCs */
1014 if (info->stbyctrl)
1015 return 0;
1016
886 error = cpg_mssr_reset_controller_register(priv); 1017 error = cpg_mssr_reset_controller_register(priv);
887 if (error) 1018 if (error)
888 return error; 1019 return error;
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 642f720b9b05..c4ec9df146fd 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -1,11 +1,8 @@
1/* 1/* SPDX-License-Identifier: GPL-2.0
2 *
2 * Renesas Clock Pulse Generator / Module Standby and Software Reset 3 * Renesas Clock Pulse Generator / Module Standby and Software Reset
3 * 4 *
4 * Copyright (C) 2015 Glider bvba 5 * Copyright (C) 2015 Glider bvba
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */ 6 */
10 7
11#ifndef __CLK_RENESAS_CPG_MSSR_H__ 8#ifndef __CLK_RENESAS_CPG_MSSR_H__
@@ -38,6 +35,7 @@ enum clk_types {
38 CLK_TYPE_FF, /* Fixed Factor Clock */ 35 CLK_TYPE_FF, /* Fixed Factor Clock */
39 CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */ 36 CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
40 CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */ 37 CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
38 CLK_TYPE_FR, /* Fixed Rate Clock */
41 39
42 /* Custom definitions start here */ 40 /* Custom definitions start here */
43 CLK_TYPE_CUSTOM, 41 CLK_TYPE_CUSTOM,
@@ -56,6 +54,8 @@ enum clk_types {
56 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset) 54 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
57#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ 55#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
58 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1) 56 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
57#define DEF_RATE(_name, _id, _rate) \
58 DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
59 59
60 /* 60 /*
61 * Definitions of Module Clocks 61 * Definitions of Module Clocks
@@ -75,12 +75,24 @@ struct mssr_mod_clk {
75#define DEF_MOD(_name, _mod, _parent...) \ 75#define DEF_MOD(_name, _mod, _parent...) \
76 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent } 76 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
77 77
78/* Convert from sparse base-10 to packed index space */
79#define MOD_CLK_PACK_10(x) ((x / 10) * 32 + (x % 10))
80
81#define MOD_CLK_ID_10(x) (MOD_CLK_BASE + MOD_CLK_PACK_10(x))
82
83#define DEF_MOD_STB(_name, _mod, _parent...) \
84 { .name = _name, .id = MOD_CLK_ID_10(_mod), .parent = _parent }
78 85
79struct device_node; 86struct device_node;
80 87
81 /** 88 /**
82 * SoC-specific CPG/MSSR Description 89 * SoC-specific CPG/MSSR Description
83 * 90 *
91 * @early_core_clks: Array of Early Core Clock definitions
92 * @num_early_core_clks: Number of entries in early_core_clks[]
93 * @early_mod_clks: Array of Early Module Clock definitions
94 * @num_early_mod_clks: Number of entries in early_mod_clks[]
95 *
84 * @core_clks: Array of Core Clock definitions 96 * @core_clks: Array of Core Clock definitions
85 * @num_core_clks: Number of entries in core_clks[] 97 * @num_core_clks: Number of entries in core_clks[]
86 * @last_dt_core_clk: ID of the last Core Clock exported to DT 98 * @last_dt_core_clk: ID of the last Core Clock exported to DT
@@ -100,14 +112,25 @@ struct device_node;
100 * 112 *
101 * @init: Optional callback to perform SoC-specific initialization 113 * @init: Optional callback to perform SoC-specific initialization
102 * @cpg_clk_register: Optional callback to handle special Core Clock types 114 * @cpg_clk_register: Optional callback to handle special Core Clock types
115 *
116 * @stbyctrl: This device has Standby Control Registers which are 8-bits
117 * wide, no status registers (MSTPSR) and have different address
118 * offsets.
103 */ 119 */
104 120
105struct cpg_mssr_info { 121struct cpg_mssr_info {
122 /* Early Clocks */
123 const struct cpg_core_clk *early_core_clks;
124 unsigned int num_early_core_clks;
125 const struct mssr_mod_clk *early_mod_clks;
126 unsigned int num_early_mod_clks;
127
106 /* Core Clocks */ 128 /* Core Clocks */
107 const struct cpg_core_clk *core_clks; 129 const struct cpg_core_clk *core_clks;
108 unsigned int num_core_clks; 130 unsigned int num_core_clks;
109 unsigned int last_dt_core_clk; 131 unsigned int last_dt_core_clk;
110 unsigned int num_total_core_clks; 132 unsigned int num_total_core_clks;
133 bool stbyctrl;
111 134
112 /* Module Clocks */ 135 /* Module Clocks */
113 const struct mssr_mod_clk *mod_clks; 136 const struct mssr_mod_clk *mod_clks;
@@ -131,9 +154,12 @@ struct cpg_mssr_info {
131 struct raw_notifier_head *notifiers); 154 struct raw_notifier_head *notifiers);
132}; 155};
133 156
157extern const struct cpg_mssr_info r7s9210_cpg_mssr_info;
134extern const struct cpg_mssr_info r8a7743_cpg_mssr_info; 158extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
135extern const struct cpg_mssr_info r8a7745_cpg_mssr_info; 159extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
136extern const struct cpg_mssr_info r8a77470_cpg_mssr_info; 160extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
161extern const struct cpg_mssr_info r8a774a1_cpg_mssr_info;
162extern const struct cpg_mssr_info r8a774c0_cpg_mssr_info;
137extern const struct cpg_mssr_info r8a7790_cpg_mssr_info; 163extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
138extern const struct cpg_mssr_info r8a7791_cpg_mssr_info; 164extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
139extern const struct cpg_mssr_info r8a7792_cpg_mssr_info; 165extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
@@ -146,6 +172,8 @@ extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
146extern const struct cpg_mssr_info r8a77990_cpg_mssr_info; 172extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
147extern const struct cpg_mssr_info r8a77995_cpg_mssr_info; 173extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
148 174
175void __init cpg_mssr_early_init(struct device_node *np,
176 const struct cpg_mssr_info *info);
149 177
150 /* 178 /*
151 * Helpers for fixing up clock tables depending on SoC revision 179 * Helpers for fixing up clock tables depending on SoC revision
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index d2c99d8916b8..a5fddebbe530 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -152,7 +152,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
152 struct exynos_cpuclk *cpuclk, void __iomem *base) 152 struct exynos_cpuclk *cpuclk, void __iomem *base)
153{ 153{
154 const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; 154 const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
155 unsigned long alt_prate = clk_get_rate(cpuclk->alt_parent); 155 unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
156 unsigned long alt_div = 0, alt_div_mask = DIV_MASK; 156 unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
157 unsigned long div0, div1 = 0, mux_reg; 157 unsigned long div0, div1 = 0, mux_reg;
158 unsigned long flags; 158 unsigned long flags;
@@ -280,7 +280,7 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
280 struct exynos_cpuclk *cpuclk, void __iomem *base) 280 struct exynos_cpuclk *cpuclk, void __iomem *base)
281{ 281{
282 const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; 282 const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
283 unsigned long alt_prate = clk_get_rate(cpuclk->alt_parent); 283 unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
284 unsigned long alt_div = 0, alt_div_mask = DIV_MASK; 284 unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
285 unsigned long div0, div1 = 0, mux_reg; 285 unsigned long div0, div1 = 0, mux_reg;
286 unsigned long flags; 286 unsigned long flags;
@@ -432,7 +432,7 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
432 else 432 else
433 cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb; 433 cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
434 434
435 cpuclk->alt_parent = __clk_lookup(alt_parent); 435 cpuclk->alt_parent = __clk_get_hw(__clk_lookup(alt_parent));
436 if (!cpuclk->alt_parent) { 436 if (!cpuclk->alt_parent) {
437 pr_err("%s: could not lookup alternate parent %s\n", 437 pr_err("%s: could not lookup alternate parent %s\n",
438 __func__, alt_parent); 438 __func__, alt_parent);
diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h
index d4b6b517fe1b..bd38c6aa3897 100644
--- a/drivers/clk/samsung/clk-cpu.h
+++ b/drivers/clk/samsung/clk-cpu.h
@@ -49,7 +49,7 @@ struct exynos_cpuclk_cfg_data {
49 */ 49 */
50struct exynos_cpuclk { 50struct exynos_cpuclk {
51 struct clk_hw hw; 51 struct clk_hw hw;
52 struct clk *alt_parent; 52 struct clk_hw *alt_parent;
53 void __iomem *ctrl_base; 53 void __iomem *ctrl_base;
54 spinlock_t *lock; 54 spinlock_t *lock;
55 const struct exynos_cpuclk_cfg_data *cfg; 55 const struct exynos_cpuclk_cfg_data *cfg;
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index f659c5cbf1d5..8f8a0f9fc842 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -15,7 +15,6 @@
15#include <linux/clk-provider.h> 15#include <linux/clk-provider.h>
16#include <linux/of_address.h> 16#include <linux/of_address.h>
17#include <linux/of_device.h> 17#include <linux/of_device.h>
18#include <linux/syscore_ops.h>
19#include <linux/module.h> 18#include <linux/module.h>
20#include <linux/platform_device.h> 19#include <linux/platform_device.h>
21#include <linux/pm_runtime.h> 20#include <linux/pm_runtime.h>
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index 27c9d23657b3..0e9a41a4cac8 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -12,7 +12,6 @@
12#include <linux/of.h> 12#include <linux/of.h>
13#include <linux/of_address.h> 13#include <linux/of_address.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/syscore_ops.h>
16 15
17#include <dt-bindings/clock/exynos3250.h> 16#include <dt-bindings/clock/exynos3250.h>
18 17
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 0421960eb963..59d4d46667ce 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -16,7 +16,6 @@
16#include <linux/clk-provider.h> 16#include <linux/clk-provider.h>
17#include <linux/of.h> 17#include <linux/of.h>
18#include <linux/of_address.h> 18#include <linux/of_address.h>
19#include <linux/syscore_ops.h>
20 19
21#include "clk.h" 20#include "clk.h"
22#include "clk-cpu.h" 21#include "clk-cpu.h"
@@ -123,10 +122,6 @@
123#define CLKOUT_CMU_CPU 0x14a00 122#define CLKOUT_CMU_CPU 0x14a00
124#define PWR_CTRL1 0x15020 123#define PWR_CTRL1 0x15020
125#define E4X12_PWR_CTRL2 0x15024 124#define E4X12_PWR_CTRL2 0x15024
126#define E4X12_DIV_ISP0 0x18300
127#define E4X12_DIV_ISP1 0x18304
128#define E4X12_GATE_ISP0 0x18800
129#define E4X12_GATE_ISP1 0x18804
130 125
131/* Below definitions are used for PWR_CTRL settings */ 126/* Below definitions are used for PWR_CTRL settings */
132#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28) 127#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
@@ -158,14 +153,6 @@ static void __iomem *reg_base;
158static enum exynos4_soc exynos4_soc; 153static enum exynos4_soc exynos4_soc;
159 154
160/* 155/*
161 * Support for CMU save/restore across system suspends
162 */
163#ifdef CONFIG_PM_SLEEP
164static struct samsung_clk_reg_dump *exynos4_save_common;
165static struct samsung_clk_reg_dump *exynos4_save_soc;
166static struct samsung_clk_reg_dump *exynos4_save_pll;
167
168/*
169 * list of controller registers to be saved and restored during a 156 * list of controller registers to be saved and restored during a
170 * suspend/resume cycle. 157 * suspend/resume cycle.
171 */ 158 */
@@ -192,7 +179,7 @@ static const unsigned long exynos4x12_clk_save[] __initconst = {
192 E4X12_PWR_CTRL2, 179 E4X12_PWR_CTRL2,
193}; 180};
194 181
195static const unsigned long exynos4_clk_pll_regs[] __initconst = { 182static const unsigned long exynos4_clk_regs[] __initconst = {
196 EPLL_LOCK, 183 EPLL_LOCK,
197 VPLL_LOCK, 184 VPLL_LOCK,
198 EPLL_CON0, 185 EPLL_CON0,
@@ -201,9 +188,6 @@ static const unsigned long exynos4_clk_pll_regs[] __initconst = {
201 VPLL_CON0, 188 VPLL_CON0,
202 VPLL_CON1, 189 VPLL_CON1,
203 VPLL_CON2, 190 VPLL_CON2,
204};
205
206static const unsigned long exynos4_clk_regs[] __initconst = {
207 SRC_LEFTBUS, 191 SRC_LEFTBUS,
208 DIV_LEFTBUS, 192 DIV_LEFTBUS,
209 GATE_IP_LEFTBUS, 193 GATE_IP_LEFTBUS,
@@ -276,6 +260,8 @@ static const unsigned long exynos4_clk_regs[] __initconst = {
276}; 260};
277 261
278static const struct samsung_clk_reg_dump src_mask_suspend[] = { 262static const struct samsung_clk_reg_dump src_mask_suspend[] = {
263 { .offset = VPLL_CON0, .value = 0x80600302, },
264 { .offset = EPLL_CON0, .value = 0x806F0302, },
279 { .offset = SRC_MASK_TOP, .value = 0x00000001, }, 265 { .offset = SRC_MASK_TOP, .value = 0x00000001, },
280 { .offset = SRC_MASK_CAM, .value = 0x11111111, }, 266 { .offset = SRC_MASK_CAM, .value = 0x11111111, },
281 { .offset = SRC_MASK_TV, .value = 0x00000111, }, 267 { .offset = SRC_MASK_TV, .value = 0x00000111, },
@@ -291,123 +277,6 @@ static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = {
291 { .offset = E4210_SRC_MASK_LCD1, .value = 0x00001111, }, 277 { .offset = E4210_SRC_MASK_LCD1, .value = 0x00001111, },
292}; 278};
293 279
294#define PLL_ENABLED (1 << 31)
295#define PLL_LOCKED (1 << 29)
296
297static void exynos4_clk_enable_pll(u32 reg)
298{
299 u32 pll_con = readl(reg_base + reg);
300 pll_con |= PLL_ENABLED;
301 writel(pll_con, reg_base + reg);
302
303 while (!(pll_con & PLL_LOCKED)) {
304 cpu_relax();
305 pll_con = readl(reg_base + reg);
306 }
307}
308
309static void exynos4_clk_wait_for_pll(u32 reg)
310{
311 u32 pll_con;
312
313 pll_con = readl(reg_base + reg);
314 if (!(pll_con & PLL_ENABLED))
315 return;
316
317 while (!(pll_con & PLL_LOCKED)) {
318 cpu_relax();
319 pll_con = readl(reg_base + reg);
320 }
321}
322
323static int exynos4_clk_suspend(void)
324{
325 samsung_clk_save(reg_base, exynos4_save_common,
326 ARRAY_SIZE(exynos4_clk_regs));
327 samsung_clk_save(reg_base, exynos4_save_pll,
328 ARRAY_SIZE(exynos4_clk_pll_regs));
329
330 exynos4_clk_enable_pll(EPLL_CON0);
331 exynos4_clk_enable_pll(VPLL_CON0);
332
333 if (exynos4_soc == EXYNOS4210) {
334 samsung_clk_save(reg_base, exynos4_save_soc,
335 ARRAY_SIZE(exynos4210_clk_save));
336 samsung_clk_restore(reg_base, src_mask_suspend_e4210,
337 ARRAY_SIZE(src_mask_suspend_e4210));
338 } else {
339 samsung_clk_save(reg_base, exynos4_save_soc,
340 ARRAY_SIZE(exynos4x12_clk_save));
341 }
342
343 samsung_clk_restore(reg_base, src_mask_suspend,
344 ARRAY_SIZE(src_mask_suspend));
345
346 return 0;
347}
348
349static void exynos4_clk_resume(void)
350{
351 samsung_clk_restore(reg_base, exynos4_save_pll,
352 ARRAY_SIZE(exynos4_clk_pll_regs));
353
354 exynos4_clk_wait_for_pll(EPLL_CON0);
355 exynos4_clk_wait_for_pll(VPLL_CON0);
356
357 samsung_clk_restore(reg_base, exynos4_save_common,
358 ARRAY_SIZE(exynos4_clk_regs));
359
360 if (exynos4_soc == EXYNOS4210)
361 samsung_clk_restore(reg_base, exynos4_save_soc,
362 ARRAY_SIZE(exynos4210_clk_save));
363 else
364 samsung_clk_restore(reg_base, exynos4_save_soc,
365 ARRAY_SIZE(exynos4x12_clk_save));
366}
367
368static struct syscore_ops exynos4_clk_syscore_ops = {
369 .suspend = exynos4_clk_suspend,
370 .resume = exynos4_clk_resume,
371};
372
373static void __init exynos4_clk_sleep_init(void)
374{
375 exynos4_save_common = samsung_clk_alloc_reg_dump(exynos4_clk_regs,
376 ARRAY_SIZE(exynos4_clk_regs));
377 if (!exynos4_save_common)
378 goto err_warn;
379
380 if (exynos4_soc == EXYNOS4210)
381 exynos4_save_soc = samsung_clk_alloc_reg_dump(
382 exynos4210_clk_save,
383 ARRAY_SIZE(exynos4210_clk_save));
384 else
385 exynos4_save_soc = samsung_clk_alloc_reg_dump(
386 exynos4x12_clk_save,
387 ARRAY_SIZE(exynos4x12_clk_save));
388 if (!exynos4_save_soc)
389 goto err_common;
390
391 exynos4_save_pll = samsung_clk_alloc_reg_dump(exynos4_clk_pll_regs,
392 ARRAY_SIZE(exynos4_clk_pll_regs));
393 if (!exynos4_save_pll)
394 goto err_soc;
395
396 register_syscore_ops(&exynos4_clk_syscore_ops);
397 return;
398
399err_soc:
400 kfree(exynos4_save_soc);
401err_common:
402 kfree(exynos4_save_common);
403err_warn:
404 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
405 __func__);
406}
407#else
408static void __init exynos4_clk_sleep_init(void) {}
409#endif
410
411/* list of all parent clock list */ 280/* list of all parent clock list */
412PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; 281PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
413PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", }; 282PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
@@ -841,18 +710,6 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
841 DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3), 710 DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
842}; 711};
843 712
844static struct samsung_div_clock exynos4x12_isp_div_clks[] = {
845 DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3,
846 CLK_GET_RATE_NOCACHE, 0),
847 DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3,
848 CLK_GET_RATE_NOCACHE, 0),
849 DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
850 DIV_F(CLK_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1,
851 4, 3, CLK_GET_RATE_NOCACHE, 0),
852 DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
853 8, 3, CLK_GET_RATE_NOCACHE, 0),
854};
855
856/* list of gate clocks supported in all exynos4 soc's */ 713/* list of gate clocks supported in all exynos4 soc's */
857static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = { 714static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = {
858 GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0), 715 GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
@@ -1150,61 +1007,6 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
1150 0), 1007 0),
1151}; 1008};
1152 1009
1153static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = {
1154 GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0,
1155 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1156 GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1,
1157 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1158 GATE(CLK_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2,
1159 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1160 GATE(CLK_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
1161 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1162 GATE(CLK_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
1163 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1164 GATE(CLK_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5,
1165 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1166 GATE(CLK_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7,
1167 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1168 GATE(CLK_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8,
1169 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1170 GATE(CLK_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9,
1171 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1172 GATE(CLK_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10,
1173 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1174 GATE(CLK_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
1175 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1176 GATE(CLK_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
1177 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1178 GATE(CLK_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
1179 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1180 GATE(CLK_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
1181 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1182 GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
1183 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1184 GATE(CLK_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
1185 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1186 GATE(CLK_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
1187 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1188 GATE(CLK_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
1189 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1190 GATE(CLK_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
1191 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1192 GATE(CLK_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28,
1193 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1194 GATE(CLK_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30,
1195 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1196 GATE(CLK_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
1197 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1198 GATE(CLK_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
1199 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1200 GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
1201 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1202 GATE(CLK_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
1203 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1204 GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
1205 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1206};
1207
1208/* 1010/*
1209 * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit 1011 * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
1210 * resides in chipid register space, outside of the clock controller memory 1012 * resides in chipid register space, outside of the clock controller memory
@@ -1504,8 +1306,6 @@ static void __init exynos4_clk_init(struct device_node *np,
1504 e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d), 1306 e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
1505 CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); 1307 CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
1506 } else { 1308 } else {
1507 struct resource res;
1508
1509 samsung_clk_register_mux(ctx, exynos4x12_mux_clks, 1309 samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
1510 ARRAY_SIZE(exynos4x12_mux_clks)); 1310 ARRAY_SIZE(exynos4x12_mux_clks));
1511 samsung_clk_register_div(ctx, exynos4x12_div_clks, 1311 samsung_clk_register_div(ctx, exynos4x12_div_clks,
@@ -1516,14 +1316,6 @@ static void __init exynos4_clk_init(struct device_node *np,
1516 exynos4x12_fixed_factor_clks, 1316 exynos4x12_fixed_factor_clks,
1517 ARRAY_SIZE(exynos4x12_fixed_factor_clks)); 1317 ARRAY_SIZE(exynos4x12_fixed_factor_clks));
1518 1318
1519 of_address_to_resource(np, 0, &res);
1520 if (resource_size(&res) > 0x18000) {
1521 samsung_clk_register_div(ctx, exynos4x12_isp_div_clks,
1522 ARRAY_SIZE(exynos4x12_isp_div_clks));
1523 samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks,
1524 ARRAY_SIZE(exynos4x12_isp_gate_clks));
1525 }
1526
1527 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1319 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1528 mout_core_p4x12[0], mout_core_p4x12[1], 0x14200, 1320 mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
1529 e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d), 1321 e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
@@ -1532,7 +1324,17 @@ static void __init exynos4_clk_init(struct device_node *np,
1532 1324
1533 if (soc == EXYNOS4X12) 1325 if (soc == EXYNOS4X12)
1534 exynos4x12_core_down_clock(); 1326 exynos4x12_core_down_clock();
1535 exynos4_clk_sleep_init(); 1327
1328 samsung_clk_extended_sleep_init(reg_base,
1329 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
1330 src_mask_suspend, ARRAY_SIZE(src_mask_suspend));
1331 if (exynos4_soc == EXYNOS4210)
1332 samsung_clk_extended_sleep_init(reg_base,
1333 exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save),
1334 src_mask_suspend_e4210, ARRAY_SIZE(src_mask_suspend_e4210));
1335 else
1336 samsung_clk_sleep_init(reg_base, exynos4x12_clk_save,
1337 ARRAY_SIZE(exynos4x12_clk_save));
1536 1338
1537 samsung_clk_of_add_provider(np, ctx); 1339 samsung_clk_of_add_provider(np, ctx);
1538 1340
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 347fd80c351b..f14139bcb0c1 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -14,7 +14,6 @@
14#include <linux/clk-provider.h> 14#include <linux/clk-provider.h>
15#include <linux/of.h> 15#include <linux/of.h>
16#include <linux/of_address.h> 16#include <linux/of_address.h>
17#include <linux/syscore_ops.h>
18 17
19#include "clk.h" 18#include "clk.h"
20#include "clk-cpu.h" 19#include "clk-cpu.h"
@@ -111,9 +110,6 @@ enum exynos5250_plls {
111 110
112static void __iomem *reg_base; 111static void __iomem *reg_base;
113 112
114#ifdef CONFIG_PM_SLEEP
115static struct samsung_clk_reg_dump *exynos5250_save;
116
117/* 113/*
118 * list of controller registers to be saved and restored during a 114 * list of controller registers to be saved and restored during a
119 * suspend/resume cycle. 115 * suspend/resume cycle.
@@ -172,41 +168,6 @@ static const unsigned long exynos5250_clk_regs[] __initconst = {
172 GATE_IP_ISP1, 168 GATE_IP_ISP1,
173}; 169};
174 170
175static int exynos5250_clk_suspend(void)
176{
177 samsung_clk_save(reg_base, exynos5250_save,
178 ARRAY_SIZE(exynos5250_clk_regs));
179
180 return 0;
181}
182
183static void exynos5250_clk_resume(void)
184{
185 samsung_clk_restore(reg_base, exynos5250_save,
186 ARRAY_SIZE(exynos5250_clk_regs));
187}
188
189static struct syscore_ops exynos5250_clk_syscore_ops = {
190 .suspend = exynos5250_clk_suspend,
191 .resume = exynos5250_clk_resume,
192};
193
194static void __init exynos5250_clk_sleep_init(void)
195{
196 exynos5250_save = samsung_clk_alloc_reg_dump(exynos5250_clk_regs,
197 ARRAY_SIZE(exynos5250_clk_regs));
198 if (!exynos5250_save) {
199 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
200 __func__);
201 return;
202 }
203
204 register_syscore_ops(&exynos5250_clk_syscore_ops);
205}
206#else
207static void __init exynos5250_clk_sleep_init(void) {}
208#endif
209
210/* list of all parent clock list */ 171/* list of all parent clock list */
211PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; 172PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
212PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", }; 173PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", };
@@ -882,7 +843,8 @@ static void __init exynos5250_clk_init(struct device_node *np)
882 PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO); 843 PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
883 __raw_writel(tmp, reg_base + PWR_CTRL2); 844 __raw_writel(tmp, reg_base + PWR_CTRL2);
884 845
885 exynos5250_clk_sleep_init(); 846 samsung_clk_sleep_init(reg_base, exynos5250_clk_regs,
847 ARRAY_SIZE(exynos5250_clk_regs));
886 exynos5_subcmus_init(ctx, 1, &exynos5250_disp_subcmu); 848 exynos5_subcmus_init(ctx, 1, &exynos5250_disp_subcmu);
887 849
888 samsung_clk_of_add_provider(np, ctx); 850 samsung_clk_of_add_provider(np, ctx);
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 95e1bf69449b..34cce3c5898f 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -15,7 +15,6 @@
15#include <linux/clk-provider.h> 15#include <linux/clk-provider.h>
16#include <linux/of.h> 16#include <linux/of.h>
17#include <linux/of_address.h> 17#include <linux/of_address.h>
18#include <linux/syscore_ops.h>
19 18
20#include "clk.h" 19#include "clk.h"
21#include "clk-cpu.h" 20#include "clk-cpu.h"
@@ -156,10 +155,6 @@ enum exynos5x_plls {
156static void __iomem *reg_base; 155static void __iomem *reg_base;
157static enum exynos5x_soc exynos5x_soc; 156static enum exynos5x_soc exynos5x_soc;
158 157
159#ifdef CONFIG_PM_SLEEP
160static struct samsung_clk_reg_dump *exynos5x_save;
161static struct samsung_clk_reg_dump *exynos5800_save;
162
163/* 158/*
164 * list of controller registers to be saved and restored during a 159 * list of controller registers to be saved and restored during a
165 * suspend/resume cycle. 160 * suspend/resume cycle.
@@ -281,68 +276,9 @@ static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
281 { .offset = GATE_BUS_TOP, .value = 0xffffffff, }, 276 { .offset = GATE_BUS_TOP, .value = 0xffffffff, },
282 { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, 277 { .offset = GATE_BUS_DISP1, .value = 0xffffffff, },
283 { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, 278 { .offset = GATE_IP_PERIC, .value = 0xffffffff, },
279 { .offset = GATE_IP_PERIS, .value = 0xffffffff, },
284}; 280};
285 281
286static int exynos5420_clk_suspend(void)
287{
288 samsung_clk_save(reg_base, exynos5x_save,
289 ARRAY_SIZE(exynos5x_clk_regs));
290
291 if (exynos5x_soc == EXYNOS5800)
292 samsung_clk_save(reg_base, exynos5800_save,
293 ARRAY_SIZE(exynos5800_clk_regs));
294
295 samsung_clk_restore(reg_base, exynos5420_set_clksrc,
296 ARRAY_SIZE(exynos5420_set_clksrc));
297
298 return 0;
299}
300
301static void exynos5420_clk_resume(void)
302{
303 samsung_clk_restore(reg_base, exynos5x_save,
304 ARRAY_SIZE(exynos5x_clk_regs));
305
306 if (exynos5x_soc == EXYNOS5800)
307 samsung_clk_restore(reg_base, exynos5800_save,
308 ARRAY_SIZE(exynos5800_clk_regs));
309}
310
311static struct syscore_ops exynos5420_clk_syscore_ops = {
312 .suspend = exynos5420_clk_suspend,
313 .resume = exynos5420_clk_resume,
314};
315
316static void __init exynos5420_clk_sleep_init(void)
317{
318 exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs,
319 ARRAY_SIZE(exynos5x_clk_regs));
320 if (!exynos5x_save) {
321 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
322 __func__);
323 return;
324 }
325
326 if (exynos5x_soc == EXYNOS5800) {
327 exynos5800_save =
328 samsung_clk_alloc_reg_dump(exynos5800_clk_regs,
329 ARRAY_SIZE(exynos5800_clk_regs));
330 if (!exynos5800_save)
331 goto err_soc;
332 }
333
334 register_syscore_ops(&exynos5420_clk_syscore_ops);
335 return;
336err_soc:
337 kfree(exynos5x_save);
338 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
339 __func__);
340 return;
341}
342#else
343static void __init exynos5420_clk_sleep_init(void) {}
344#endif
345
346/* list of all parent clocks */ 282/* list of all parent clocks */
347PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 283PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
348 "mout_sclk_mpll", "mout_sclk_spll"}; 284 "mout_sclk_mpll", "mout_sclk_spll"};
@@ -633,6 +569,7 @@ static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
633}; 569};
634 570
635static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { 571static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
572 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
636 GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", 573 GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
637 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 574 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
638}; 575};
@@ -1162,8 +1099,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
1162 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0), 1099 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
1163 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0), 1100 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
1164 1101
1165 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
1166
1167 /* GEN Block */ 1102 /* GEN Block */
1168 GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0), 1103 GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
1169 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 1104 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
@@ -1540,7 +1475,12 @@ static void __init exynos5x_clk_init(struct device_node *np,
1540 mout_kfc_p[0], mout_kfc_p[1], 0x28200, 1475 mout_kfc_p[0], mout_kfc_p[1], 0x28200,
1541 exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); 1476 exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
1542 1477
1543 exynos5420_clk_sleep_init(); 1478 samsung_clk_extended_sleep_init(reg_base,
1479 exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs),
1480 exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc));
1481 if (soc == EXYNOS5800)
1482 samsung_clk_sleep_init(reg_base, exynos5800_clk_regs,
1483 ARRAY_SIZE(exynos5800_clk_regs));
1544 exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus), 1484 exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus),
1545 exynos5x_subcmus); 1485 exynos5x_subcmus);
1546 1486
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 162de44df099..751e2c4fb65b 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -177,6 +177,17 @@ static const unsigned long top_clk_regs[] __initconst = {
177 ENABLE_CMU_TOP_DIV_STAT, 177 ENABLE_CMU_TOP_DIV_STAT,
178}; 178};
179 179
180static const struct samsung_clk_reg_dump top_suspend_regs[] = {
181 /* force all aclk clocks enabled */
182 { ENABLE_ACLK_TOP, 0x67ecffed },
183 /* force all sclk_uart clocks enabled */
184 { ENABLE_SCLK_TOP_PERIC, 0x38 },
185 /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
186 { ISP_PLL_CON0, 0x85cc0502 },
187 /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
188 { AUD_PLL_CON0, 0x84830202 },
189};
190
180/* list of all parent clock list */ 191/* list of all parent clock list */
181PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", }; 192PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
182PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", }; 193PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
@@ -792,6 +803,8 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
792 .nr_clk_ids = TOP_NR_CLK, 803 .nr_clk_ids = TOP_NR_CLK,
793 .clk_regs = top_clk_regs, 804 .clk_regs = top_clk_regs,
794 .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 805 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
806 .suspend_regs = top_suspend_regs,
807 .nr_suspend_regs = ARRAY_SIZE(top_suspend_regs),
795}; 808};
796 809
797static void __init exynos5433_cmu_top_init(struct device_node *np) 810static void __init exynos5433_cmu_top_init(struct device_node *np)
@@ -822,6 +835,13 @@ static const unsigned long cpif_clk_regs[] __initconst = {
822 ENABLE_SCLK_CPIF, 835 ENABLE_SCLK_CPIF,
823}; 836};
824 837
838static const struct samsung_clk_reg_dump cpif_suspend_regs[] = {
839 /* force all sclk clocks enabled */
840 { ENABLE_SCLK_CPIF, 0x3ff },
841 /* MPHY PLL has to be enabled for suspend: reset value + ENABLE bit */
842 { MPHY_PLL_CON0, 0x81c70601 },
843};
844
825/* list of all parent clock list */ 845/* list of all parent clock list */
826PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", }; 846PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", };
827 847
@@ -862,6 +882,8 @@ static const struct samsung_cmu_info cpif_cmu_info __initconst = {
862 .nr_clk_ids = CPIF_NR_CLK, 882 .nr_clk_ids = CPIF_NR_CLK,
863 .clk_regs = cpif_clk_regs, 883 .clk_regs = cpif_clk_regs,
864 .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs), 884 .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs),
885 .suspend_regs = cpif_suspend_regs,
886 .nr_suspend_regs = ARRAY_SIZE(cpif_suspend_regs),
865}; 887};
866 888
867static void __init exynos5433_cmu_cpif_init(struct device_node *np) 889static void __init exynos5433_cmu_cpif_init(struct device_node *np)
@@ -1547,6 +1569,13 @@ static const unsigned long peric_clk_regs[] __initconst = {
1547 ENABLE_IP_PERIC2, 1569 ENABLE_IP_PERIC2,
1548}; 1570};
1549 1571
1572static const struct samsung_clk_reg_dump peric_suspend_regs[] = {
1573 /* pclk: sci, pmu, sysreg, gpio_{finger, ese, touch, nfc}, uart2-0 */
1574 { ENABLE_PCLK_PERIC0, 0xe00ff000 },
1575 /* sclk: uart2-0 */
1576 { ENABLE_SCLK_PERIC, 0x7 },
1577};
1578
1550static const struct samsung_div_clock peric_div_clks[] __initconst = { 1579static const struct samsung_div_clock peric_div_clks[] __initconst = {
1551 /* DIV_PERIC */ 1580 /* DIV_PERIC */
1552 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4), 1581 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
@@ -1705,6 +1734,8 @@ static const struct samsung_cmu_info peric_cmu_info __initconst = {
1705 .nr_clk_ids = PERIC_NR_CLK, 1734 .nr_clk_ids = PERIC_NR_CLK,
1706 .clk_regs = peric_clk_regs, 1735 .clk_regs = peric_clk_regs,
1707 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), 1736 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
1737 .suspend_regs = peric_suspend_regs,
1738 .nr_suspend_regs = ARRAY_SIZE(peric_suspend_regs),
1708}; 1739};
1709 1740
1710static void __init exynos5433_cmu_peric_init(struct device_node *np) 1741static void __init exynos5433_cmu_peric_init(struct device_node *np)
@@ -5630,7 +5661,7 @@ static const struct of_device_id exynos5433_cmu_of_match[] = {
5630static const struct dev_pm_ops exynos5433_cmu_pm_ops = { 5661static const struct dev_pm_ops exynos5433_cmu_pm_ops = {
5631 SET_RUNTIME_PM_OPS(exynos5433_cmu_suspend, exynos5433_cmu_resume, 5662 SET_RUNTIME_PM_OPS(exynos5433_cmu_suspend, exynos5433_cmu_resume,
5632 NULL) 5663 NULL)
5633 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 5664 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
5634 pm_runtime_force_resume) 5665 pm_runtime_force_resume)
5635}; 5666};
5636 5667
diff --git a/drivers/clk/samsung/clk-s3c2410.c b/drivers/clk/samsung/clk-s3c2410.c
index a9c887475054..8cb868f06257 100644
--- a/drivers/clk/samsung/clk-s3c2410.c
+++ b/drivers/clk/samsung/clk-s3c2410.c
@@ -11,7 +11,6 @@
11#include <linux/clk-provider.h> 11#include <linux/clk-provider.h>
12#include <linux/of.h> 12#include <linux/of.h>
13#include <linux/of_address.h> 13#include <linux/of_address.h>
14#include <linux/syscore_ops.h>
15 14
16#include <dt-bindings/clock/s3c2410.h> 15#include <dt-bindings/clock/s3c2410.h>
17 16
@@ -40,9 +39,6 @@ enum s3c2410_plls {
40 39
41static void __iomem *reg_base; 40static void __iomem *reg_base;
42 41
43#ifdef CONFIG_PM_SLEEP
44static struct samsung_clk_reg_dump *s3c2410_save;
45
46/* 42/*
47 * list of controller registers to be saved and restored during a 43 * list of controller registers to be saved and restored during a
48 * suspend/resume cycle. 44 * suspend/resume cycle.
@@ -57,42 +53,6 @@ static unsigned long s3c2410_clk_regs[] __initdata = {
57 CAMDIVN, 53 CAMDIVN,
58}; 54};
59 55
60static int s3c2410_clk_suspend(void)
61{
62 samsung_clk_save(reg_base, s3c2410_save,
63 ARRAY_SIZE(s3c2410_clk_regs));
64
65 return 0;
66}
67
68static void s3c2410_clk_resume(void)
69{
70 samsung_clk_restore(reg_base, s3c2410_save,
71 ARRAY_SIZE(s3c2410_clk_regs));
72}
73
74static struct syscore_ops s3c2410_clk_syscore_ops = {
75 .suspend = s3c2410_clk_suspend,
76 .resume = s3c2410_clk_resume,
77};
78
79static void __init s3c2410_clk_sleep_init(void)
80{
81 s3c2410_save = samsung_clk_alloc_reg_dump(s3c2410_clk_regs,
82 ARRAY_SIZE(s3c2410_clk_regs));
83 if (!s3c2410_save) {
84 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
85 __func__);
86 return;
87 }
88
89 register_syscore_ops(&s3c2410_clk_syscore_ops);
90 return;
91}
92#else
93static void __init s3c2410_clk_sleep_init(void) {}
94#endif
95
96PNAME(fclk_p) = { "mpll", "div_slow" }; 56PNAME(fclk_p) = { "mpll", "div_slow" };
97 57
98static struct samsung_mux_clock s3c2410_common_muxes[] __initdata = { 58static struct samsung_mux_clock s3c2410_common_muxes[] __initdata = {
@@ -461,7 +421,8 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
461 ARRAY_SIZE(s3c244x_common_aliases)); 421 ARRAY_SIZE(s3c244x_common_aliases));
462 } 422 }
463 423
464 s3c2410_clk_sleep_init(); 424 samsung_clk_sleep_init(reg_base, s3c2410_clk_regs,
425 ARRAY_SIZE(s3c2410_clk_regs));
465 426
466 samsung_clk_of_add_provider(np, ctx); 427 samsung_clk_of_add_provider(np, ctx);
467} 428}
diff --git a/drivers/clk/samsung/clk-s3c2412.c b/drivers/clk/samsung/clk-s3c2412.c
index 6bc94d3aff78..dd1159050a5a 100644
--- a/drivers/clk/samsung/clk-s3c2412.c
+++ b/drivers/clk/samsung/clk-s3c2412.c
@@ -11,7 +11,6 @@
11#include <linux/clk-provider.h> 11#include <linux/clk-provider.h>
12#include <linux/of.h> 12#include <linux/of.h>
13#include <linux/of_address.h> 13#include <linux/of_address.h>
14#include <linux/syscore_ops.h>
15#include <linux/reboot.h> 14#include <linux/reboot.h>
16 15
17#include <dt-bindings/clock/s3c2412.h> 16#include <dt-bindings/clock/s3c2412.h>
@@ -29,9 +28,6 @@
29 28
30static void __iomem *reg_base; 29static void __iomem *reg_base;
31 30
32#ifdef CONFIG_PM_SLEEP
33static struct samsung_clk_reg_dump *s3c2412_save;
34
35/* 31/*
36 * list of controller registers to be saved and restored during a 32 * list of controller registers to be saved and restored during a
37 * suspend/resume cycle. 33 * suspend/resume cycle.
@@ -45,42 +41,6 @@ static unsigned long s3c2412_clk_regs[] __initdata = {
45 CLKSRC, 41 CLKSRC,
46}; 42};
47 43
48static int s3c2412_clk_suspend(void)
49{
50 samsung_clk_save(reg_base, s3c2412_save,
51 ARRAY_SIZE(s3c2412_clk_regs));
52
53 return 0;
54}
55
56static void s3c2412_clk_resume(void)
57{
58 samsung_clk_restore(reg_base, s3c2412_save,
59 ARRAY_SIZE(s3c2412_clk_regs));
60}
61
62static struct syscore_ops s3c2412_clk_syscore_ops = {
63 .suspend = s3c2412_clk_suspend,
64 .resume = s3c2412_clk_resume,
65};
66
67static void __init s3c2412_clk_sleep_init(void)
68{
69 s3c2412_save = samsung_clk_alloc_reg_dump(s3c2412_clk_regs,
70 ARRAY_SIZE(s3c2412_clk_regs));
71 if (!s3c2412_save) {
72 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
73 __func__);
74 return;
75 }
76
77 register_syscore_ops(&s3c2412_clk_syscore_ops);
78 return;
79}
80#else
81static void __init s3c2412_clk_sleep_init(void) {}
82#endif
83
84static struct clk_div_table divxti_d[] = { 44static struct clk_div_table divxti_d[] = {
85 { .val = 0, .div = 1 }, 45 { .val = 0, .div = 1 },
86 { .val = 1, .div = 2 }, 46 { .val = 1, .div = 2 },
@@ -278,7 +238,8 @@ void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
278 samsung_clk_register_alias(ctx, s3c2412_aliases, 238 samsung_clk_register_alias(ctx, s3c2412_aliases,
279 ARRAY_SIZE(s3c2412_aliases)); 239 ARRAY_SIZE(s3c2412_aliases));
280 240
281 s3c2412_clk_sleep_init(); 241 samsung_clk_sleep_init(reg_base, s3c2412_clk_regs,
242 ARRAY_SIZE(s3c2412_clk_regs));
282 243
283 samsung_clk_of_add_provider(np, ctx); 244 samsung_clk_of_add_provider(np, ctx);
284 245
diff --git a/drivers/clk/samsung/clk-s3c2443.c b/drivers/clk/samsung/clk-s3c2443.c
index c46e6d5bc9bc..884067e4f1a1 100644
--- a/drivers/clk/samsung/clk-s3c2443.c
+++ b/drivers/clk/samsung/clk-s3c2443.c
@@ -11,7 +11,6 @@
11#include <linux/clk-provider.h> 11#include <linux/clk-provider.h>
12#include <linux/of.h> 12#include <linux/of.h>
13#include <linux/of_address.h> 13#include <linux/of_address.h>
14#include <linux/syscore_ops.h>
15#include <linux/reboot.h> 14#include <linux/reboot.h>
16 15
17#include <dt-bindings/clock/s3c2443.h> 16#include <dt-bindings/clock/s3c2443.h>
@@ -43,9 +42,6 @@ enum supported_socs {
43 42
44static void __iomem *reg_base; 43static void __iomem *reg_base;
45 44
46#ifdef CONFIG_PM_SLEEP
47static struct samsung_clk_reg_dump *s3c2443_save;
48
49/* 45/*
50 * list of controller registers to be saved and restored during a 46 * list of controller registers to be saved and restored during a
51 * suspend/resume cycle. 47 * suspend/resume cycle.
@@ -65,42 +61,6 @@ static unsigned long s3c2443_clk_regs[] __initdata = {
65 SCLKCON, 61 SCLKCON,
66}; 62};
67 63
68static int s3c2443_clk_suspend(void)
69{
70 samsung_clk_save(reg_base, s3c2443_save,
71 ARRAY_SIZE(s3c2443_clk_regs));
72
73 return 0;
74}
75
76static void s3c2443_clk_resume(void)
77{
78 samsung_clk_restore(reg_base, s3c2443_save,
79 ARRAY_SIZE(s3c2443_clk_regs));
80}
81
82static struct syscore_ops s3c2443_clk_syscore_ops = {
83 .suspend = s3c2443_clk_suspend,
84 .resume = s3c2443_clk_resume,
85};
86
87static void __init s3c2443_clk_sleep_init(void)
88{
89 s3c2443_save = samsung_clk_alloc_reg_dump(s3c2443_clk_regs,
90 ARRAY_SIZE(s3c2443_clk_regs));
91 if (!s3c2443_save) {
92 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
93 __func__);
94 return;
95 }
96
97 register_syscore_ops(&s3c2443_clk_syscore_ops);
98 return;
99}
100#else
101static void __init s3c2443_clk_sleep_init(void) {}
102#endif
103
104PNAME(epllref_p) = { "mpllref", "mpllref", "xti", "ext" }; 64PNAME(epllref_p) = { "mpllref", "mpllref", "xti", "ext" };
105PNAME(esysclk_p) = { "epllref", "epll" }; 65PNAME(esysclk_p) = { "epllref", "epll" };
106PNAME(mpllref_p) = { "xti", "mdivclk" }; 66PNAME(mpllref_p) = { "xti", "mdivclk" };
@@ -450,7 +410,8 @@ void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
450 break; 410 break;
451 } 411 }
452 412
453 s3c2443_clk_sleep_init(); 413 samsung_clk_sleep_init(reg_base, s3c2443_clk_regs,
414 ARRAY_SIZE(s3c2443_clk_regs));
454 415
455 samsung_clk_of_add_provider(np, ctx); 416 samsung_clk_of_add_provider(np, ctx);
456 417
diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c
index 6db01cf5ab83..54916c7bdb06 100644
--- a/drivers/clk/samsung/clk-s3c64xx.c
+++ b/drivers/clk/samsung/clk-s3c64xx.c
@@ -12,7 +12,6 @@
12#include <linux/clk-provider.h> 12#include <linux/clk-provider.h>
13#include <linux/of.h> 13#include <linux/of.h>
14#include <linux/of_address.h> 14#include <linux/of_address.h>
15#include <linux/syscore_ops.h>
16 15
17#include <dt-bindings/clock/samsung,s3c64xx-clock.h> 16#include <dt-bindings/clock/samsung,s3c64xx-clock.h>
18 17
@@ -59,10 +58,6 @@
59static void __iomem *reg_base; 58static void __iomem *reg_base;
60static bool is_s3c6400; 59static bool is_s3c6400;
61 60
62#ifdef CONFIG_PM_SLEEP
63static struct samsung_clk_reg_dump *s3c64xx_save_common;
64static struct samsung_clk_reg_dump *s3c64xx_save_soc;
65
66/* 61/*
67 * List of controller registers to be saved and restored during 62 * List of controller registers to be saved and restored during
68 * a suspend/resume cycle. 63 * a suspend/resume cycle.
@@ -89,60 +84,6 @@ static unsigned long s3c6410_clk_regs[] __initdata = {
89 MEM0_GATE, 84 MEM0_GATE,
90}; 85};
91 86
92static int s3c64xx_clk_suspend(void)
93{
94 samsung_clk_save(reg_base, s3c64xx_save_common,
95 ARRAY_SIZE(s3c64xx_clk_regs));
96
97 if (!is_s3c6400)
98 samsung_clk_save(reg_base, s3c64xx_save_soc,
99 ARRAY_SIZE(s3c6410_clk_regs));
100
101 return 0;
102}
103
104static void s3c64xx_clk_resume(void)
105{
106 samsung_clk_restore(reg_base, s3c64xx_save_common,
107 ARRAY_SIZE(s3c64xx_clk_regs));
108
109 if (!is_s3c6400)
110 samsung_clk_restore(reg_base, s3c64xx_save_soc,
111 ARRAY_SIZE(s3c6410_clk_regs));
112}
113
114static struct syscore_ops s3c64xx_clk_syscore_ops = {
115 .suspend = s3c64xx_clk_suspend,
116 .resume = s3c64xx_clk_resume,
117};
118
119static void __init s3c64xx_clk_sleep_init(void)
120{
121 s3c64xx_save_common = samsung_clk_alloc_reg_dump(s3c64xx_clk_regs,
122 ARRAY_SIZE(s3c64xx_clk_regs));
123 if (!s3c64xx_save_common)
124 goto err_warn;
125
126 if (!is_s3c6400) {
127 s3c64xx_save_soc = samsung_clk_alloc_reg_dump(s3c6410_clk_regs,
128 ARRAY_SIZE(s3c6410_clk_regs));
129 if (!s3c64xx_save_soc)
130 goto err_soc;
131 }
132
133 register_syscore_ops(&s3c64xx_clk_syscore_ops);
134 return;
135
136err_soc:
137 kfree(s3c64xx_save_common);
138err_warn:
139 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
140 __func__);
141}
142#else
143static void __init s3c64xx_clk_sleep_init(void) {}
144#endif
145
146/* List of parent clocks common for all S3C64xx SoCs. */ 87/* List of parent clocks common for all S3C64xx SoCs. */
147PNAME(spi_mmc_p) = { "mout_epll", "dout_mpll", "fin_pll", "clk27m" }; 88PNAME(spi_mmc_p) = { "mout_epll", "dout_mpll", "fin_pll", "clk27m" };
148PNAME(uart_p) = { "mout_epll", "dout_mpll" }; 89PNAME(uart_p) = { "mout_epll", "dout_mpll" };
@@ -508,7 +449,12 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
508 449
509 samsung_clk_register_alias(ctx, s3c64xx_clock_aliases, 450 samsung_clk_register_alias(ctx, s3c64xx_clock_aliases,
510 ARRAY_SIZE(s3c64xx_clock_aliases)); 451 ARRAY_SIZE(s3c64xx_clock_aliases));
511 s3c64xx_clk_sleep_init(); 452
453 samsung_clk_sleep_init(reg_base, s3c64xx_clk_regs,
454 ARRAY_SIZE(s3c64xx_clk_regs));
455 if (!is_s3c6400)
456 samsung_clk_sleep_init(reg_base, s3c6410_clk_regs,
457 ARRAY_SIZE(s3c6410_clk_regs));
512 458
513 samsung_clk_of_add_provider(np, ctx); 459 samsung_clk_of_add_provider(np, ctx);
514 460
diff --git a/drivers/clk/samsung/clk-s5pv210.c b/drivers/clk/samsung/clk-s5pv210.c
index fd2725710a6f..41d2337fe030 100644
--- a/drivers/clk/samsung/clk-s5pv210.c
+++ b/drivers/clk/samsung/clk-s5pv210.c
@@ -14,7 +14,6 @@
14#include <linux/clk-provider.h> 14#include <linux/clk-provider.h>
15#include <linux/of.h> 15#include <linux/of.h>
16#include <linux/of_address.h> 16#include <linux/of_address.h>
17#include <linux/syscore_ops.h>
18 17
19#include "clk.h" 18#include "clk.h"
20#include "clk-pll.h" 19#include "clk-pll.h"
@@ -83,9 +82,6 @@ enum {
83 82
84static void __iomem *reg_base; 83static void __iomem *reg_base;
85 84
86#ifdef CONFIG_PM_SLEEP
87static struct samsung_clk_reg_dump *s5pv210_clk_dump;
88
89/* List of registers that need to be preserved across suspend/resume. */ 85/* List of registers that need to be preserved across suspend/resume. */
90static unsigned long s5pv210_clk_regs[] __initdata = { 86static unsigned long s5pv210_clk_regs[] __initdata = {
91 CLK_SRC0, 87 CLK_SRC0,
@@ -132,40 +128,6 @@ static unsigned long s5pv210_clk_regs[] __initdata = {
132 CLK_OUT, 128 CLK_OUT,
133}; 129};
134 130
135static int s5pv210_clk_suspend(void)
136{
137 samsung_clk_save(reg_base, s5pv210_clk_dump,
138 ARRAY_SIZE(s5pv210_clk_regs));
139 return 0;
140}
141
142static void s5pv210_clk_resume(void)
143{
144 samsung_clk_restore(reg_base, s5pv210_clk_dump,
145 ARRAY_SIZE(s5pv210_clk_regs));
146}
147
148static struct syscore_ops s5pv210_clk_syscore_ops = {
149 .suspend = s5pv210_clk_suspend,
150 .resume = s5pv210_clk_resume,
151};
152
153static void s5pv210_clk_sleep_init(void)
154{
155 s5pv210_clk_dump =
156 samsung_clk_alloc_reg_dump(s5pv210_clk_regs,
157 ARRAY_SIZE(s5pv210_clk_regs));
158 if (!s5pv210_clk_dump) {
159 pr_warn("%s: Failed to allocate sleep save data\n", __func__);
160 return;
161 }
162
163 register_syscore_ops(&s5pv210_clk_syscore_ops);
164}
165#else
166static inline void s5pv210_clk_sleep_init(void) { }
167#endif
168
169/* Mux parent lists. */ 131/* Mux parent lists. */
170static const char *const fin_pll_p[] __initconst = { 132static const char *const fin_pll_p[] __initconst = {
171 "xxti", 133 "xxti",
@@ -822,7 +784,8 @@ static void __init __s5pv210_clk_init(struct device_node *np,
822 samsung_clk_register_alias(ctx, s5pv210_aliases, 784 samsung_clk_register_alias(ctx, s5pv210_aliases,
823 ARRAY_SIZE(s5pv210_aliases)); 785 ARRAY_SIZE(s5pv210_aliases));
824 786
825 s5pv210_clk_sleep_init(); 787 samsung_clk_sleep_init(reg_base, s5pv210_clk_regs,
788 ARRAY_SIZE(s5pv210_clk_regs));
826 789
827 samsung_clk_of_add_provider(np, ctx); 790 samsung_clk_of_add_provider(np, ctx);
828 791
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 8634884aa11c..1f6e47cd327d 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -290,9 +290,12 @@ static int samsung_clk_suspend(void)
290{ 290{
291 struct samsung_clock_reg_cache *reg_cache; 291 struct samsung_clock_reg_cache *reg_cache;
292 292
293 list_for_each_entry(reg_cache, &clock_reg_cache_list, node) 293 list_for_each_entry(reg_cache, &clock_reg_cache_list, node) {
294 samsung_clk_save(reg_cache->reg_base, reg_cache->rdump, 294 samsung_clk_save(reg_cache->reg_base, reg_cache->rdump,
295 reg_cache->rd_num); 295 reg_cache->rd_num);
296 samsung_clk_restore(reg_cache->reg_base, reg_cache->rsuspend,
297 reg_cache->rsuspend_num);
298 }
296 return 0; 299 return 0;
297} 300}
298 301
@@ -310,9 +313,11 @@ static struct syscore_ops samsung_clk_syscore_ops = {
310 .resume = samsung_clk_resume, 313 .resume = samsung_clk_resume,
311}; 314};
312 315
313void samsung_clk_sleep_init(void __iomem *reg_base, 316void samsung_clk_extended_sleep_init(void __iomem *reg_base,
314 const unsigned long *rdump, 317 const unsigned long *rdump,
315 unsigned long nr_rdump) 318 unsigned long nr_rdump,
319 const struct samsung_clk_reg_dump *rsuspend,
320 unsigned long nr_rsuspend)
316{ 321{
317 struct samsung_clock_reg_cache *reg_cache; 322 struct samsung_clock_reg_cache *reg_cache;
318 323
@@ -330,13 +335,10 @@ void samsung_clk_sleep_init(void __iomem *reg_base,
330 335
331 reg_cache->reg_base = reg_base; 336 reg_cache->reg_base = reg_base;
332 reg_cache->rd_num = nr_rdump; 337 reg_cache->rd_num = nr_rdump;
338 reg_cache->rsuspend = rsuspend;
339 reg_cache->rsuspend_num = nr_rsuspend;
333 list_add_tail(&reg_cache->node, &clock_reg_cache_list); 340 list_add_tail(&reg_cache->node, &clock_reg_cache_list);
334} 341}
335
336#else
337void samsung_clk_sleep_init(void __iomem *reg_base,
338 const unsigned long *rdump,
339 unsigned long nr_rdump) {}
340#endif 342#endif
341 343
342/* 344/*
@@ -380,8 +382,9 @@ struct samsung_clk_provider * __init samsung_cmu_register_one(
380 samsung_clk_register_fixed_factor(ctx, cmu->fixed_factor_clks, 382 samsung_clk_register_fixed_factor(ctx, cmu->fixed_factor_clks,
381 cmu->nr_fixed_factor_clks); 383 cmu->nr_fixed_factor_clks);
382 if (cmu->clk_regs) 384 if (cmu->clk_regs)
383 samsung_clk_sleep_init(reg_base, cmu->clk_regs, 385 samsung_clk_extended_sleep_init(reg_base,
384 cmu->nr_clk_regs); 386 cmu->clk_regs, cmu->nr_clk_regs,
387 cmu->suspend_regs, cmu->nr_suspend_regs);
385 388
386 samsung_clk_of_add_provider(np, ctx); 389 samsung_clk_of_add_provider(np, ctx);
387 390
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 3880d2f9d582..c3f309d7100d 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -279,6 +279,8 @@ struct samsung_clock_reg_cache {
279 void __iomem *reg_base; 279 void __iomem *reg_base;
280 struct samsung_clk_reg_dump *rdump; 280 struct samsung_clk_reg_dump *rdump;
281 unsigned int rd_num; 281 unsigned int rd_num;
282 const struct samsung_clk_reg_dump *rsuspend;
283 unsigned int rsuspend_num;
282}; 284};
283 285
284struct samsung_cmu_info { 286struct samsung_cmu_info {
@@ -358,9 +360,21 @@ extern struct samsung_clk_provider __init *samsung_cmu_register_one(
358 360
359extern unsigned long _get_rate(const char *clk_name); 361extern unsigned long _get_rate(const char *clk_name);
360 362
361extern void samsung_clk_sleep_init(void __iomem *reg_base, 363#ifdef CONFIG_PM_SLEEP
364extern void samsung_clk_extended_sleep_init(void __iomem *reg_base,
362 const unsigned long *rdump, 365 const unsigned long *rdump,
363 unsigned long nr_rdump); 366 unsigned long nr_rdump,
367 const struct samsung_clk_reg_dump *rsuspend,
368 unsigned long nr_rsuspend);
369#else
370static inline void samsung_clk_extended_sleep_init(void __iomem *reg_base,
371 const unsigned long *rdump,
372 unsigned long nr_rdump,
373 const struct samsung_clk_reg_dump *rsuspend,
374 unsigned long nr_rsuspend) {}
375#endif
376#define samsung_clk_sleep_init(reg_base, rdump, nr_rdump) \
377 samsung_clk_extended_sleep_init(reg_base, rdump, nr_rdump, NULL, 0)
364 378
365extern void samsung_clk_save(void __iomem *base, 379extern void samsung_clk_save(void __iomem *base,
366 struct samsung_clk_reg_dump *rd, 380 struct samsung_clk_reg_dump *rd,
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index a79d81985c4e..cfa000007622 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -936,7 +936,7 @@ static void __init st_of_quadfs_setup(struct device_node *np,
936 if (!clk_parent_name) 936 if (!clk_parent_name)
937 return; 937 return;
938 938
939 pll_name = kasprintf(GFP_KERNEL, "%s.pll", np->name); 939 pll_name = kasprintf(GFP_KERNEL, "%pOFn.pll", np);
940 if (!pll_name) 940 if (!pll_name)
941 return; 941 return;
942 942
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index ee9c12cf3f08..5f80eb018014 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -64,17 +64,19 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
64 BIT(28), /* lock */ 64 BIT(28), /* lock */
65 CLK_SET_RATE_UNGATE); 65 CLK_SET_RATE_UNGATE);
66 66
67static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", 67static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
68 "osc24M", 0x010, 68 "osc24M", 0x010,
69 8, 7, /* N */ 69 192000000, /* Minimum rate */
70 0, 4, /* M */ 70 1008000000, /* Maximum rate */
71 BIT(24), /* frac enable */ 71 8, 7, /* N */
72 BIT(25), /* frac select */ 72 0, 4, /* M */
73 270000000, /* frac rate 0 */ 73 BIT(24), /* frac enable */
74 297000000, /* frac rate 1 */ 74 BIT(25), /* frac select */
75 BIT(31), /* gate */ 75 270000000, /* frac rate 0 */
76 BIT(28), /* lock */ 76 297000000, /* frac rate 1 */
77 CLK_SET_RATE_UNGATE); 77 BIT(31), /* gate */
78 BIT(28), /* lock */
79 CLK_SET_RATE_UNGATE);
78 80
79static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", 81static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
80 "osc24M", 0x018, 82 "osc24M", 0x018,
@@ -125,17 +127,19 @@ static struct ccu_nk pll_periph1_clk = {
125 }, 127 },
126}; 128};
127 129
128static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1", 130static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
129 "osc24M", 0x030, 131 "osc24M", 0x030,
130 8, 7, /* N */ 132 192000000, /* Minimum rate */
131 0, 4, /* M */ 133 1008000000, /* Maximum rate */
132 BIT(24), /* frac enable */ 134 8, 7, /* N */
133 BIT(25), /* frac select */ 135 0, 4, /* M */
134 270000000, /* frac rate 0 */ 136 BIT(24), /* frac enable */
135 297000000, /* frac rate 1 */ 137 BIT(25), /* frac select */
136 BIT(31), /* gate */ 138 270000000, /* frac rate 0 */
137 BIT(28), /* lock */ 139 297000000, /* frac rate 1 */
138 CLK_SET_RATE_UNGATE); 140 BIT(31), /* gate */
141 BIT(28), /* lock */
142 CLK_SET_RATE_UNGATE);
139 143
140static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", 144static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
141 "osc24M", 0x038, 145 "osc24M", 0x038,
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
index 061b6fbb4f95..cd415b968e8c 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
@@ -27,7 +27,9 @@
27#define CLK_PLL_AUDIO_2X 4 27#define CLK_PLL_AUDIO_2X 4
28#define CLK_PLL_AUDIO_4X 5 28#define CLK_PLL_AUDIO_4X 5
29#define CLK_PLL_AUDIO_8X 6 29#define CLK_PLL_AUDIO_8X 6
30#define CLK_PLL_VIDEO0 7 30
31/* PLL_VIDEO0 exported for HDMI PHY */
32
31#define CLK_PLL_VIDEO0_2X 8 33#define CLK_PLL_VIDEO0_2X 8
32#define CLK_PLL_VE 9 34#define CLK_PLL_VE 9
33#define CLK_PLL_DDR0 10 35#define CLK_PLL_DDR0 10
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index bdbfe78fe133..2193e1495086 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -224,7 +224,7 @@ static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
224 psi_ahb1_ahb2_parents, 224 psi_ahb1_ahb2_parents,
225 0x510, 225 0x510,
226 0, 5, /* M */ 226 0, 5, /* M */
227 16, 2, /* P */ 227 8, 2, /* P */
228 24, 2, /* mux */ 228 24, 2, /* mux */
229 0); 229 0);
230 230
@@ -233,19 +233,19 @@ static const char * const ahb3_apb1_apb2_parents[] = { "osc24M", "osc32k",
233 "pll-periph0" }; 233 "pll-periph0" };
234static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c, 234static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,
235 0, 5, /* M */ 235 0, 5, /* M */
236 16, 2, /* P */ 236 8, 2, /* P */
237 24, 2, /* mux */ 237 24, 2, /* mux */
238 0); 238 0);
239 239
240static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520, 240static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,
241 0, 5, /* M */ 241 0, 5, /* M */
242 16, 2, /* P */ 242 8, 2, /* P */
243 24, 2, /* mux */ 243 24, 2, /* mux */
244 0); 244 0);
245 245
246static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524, 246static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
247 0, 5, /* M */ 247 0, 5, /* M */
248 16, 2, /* P */ 248 8, 2, /* P */
249 24, 2, /* mux */ 249 24, 2, /* mux */
250 0); 250 0);
251 251
@@ -352,7 +352,7 @@ static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2",
352static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2", 352static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2",
353 0x79c, BIT(0), 0); 353 0x79c, BIT(0), 0);
354 354
355static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x79c, BIT(0), 0); 355static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);
356 356
357static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0); 357static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0);
358 358
@@ -408,26 +408,29 @@ static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0);
408 408
409static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x", 409static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x",
410 "pll-periph1-2x" }; 410 "pll-periph1-2x" };
411static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc_parents, 0x830, 411static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,
412 0, 4, /* M */ 412 0, 4, /* M */
413 8, 2, /* N */ 413 8, 2, /* N */
414 24, 3, /* mux */ 414 24, 3, /* mux */
415 BIT(31),/* gate */ 415 BIT(31), /* gate */
416 0); 416 2, /* post-div */
417 417 0);
418static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc_parents, 0x834, 418
419 0, 4, /* M */ 419static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
420 8, 2, /* N */ 420 0, 4, /* M */
421 24, 3, /* mux */ 421 8, 2, /* N */
422 BIT(31),/* gate */ 422 24, 3, /* mux */
423 0); 423 BIT(31), /* gate */
424 424 2, /* post-div */
425static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc_parents, 0x838, 425 0);
426 0, 4, /* M */ 426
427 8, 2, /* N */ 427static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,
428 24, 3, /* mux */ 428 0, 4, /* M */
429 BIT(31),/* gate */ 429 8, 2, /* N */
430 0); 430 24, 3, /* mux */
431 BIT(31), /* gate */
432 2, /* post-div */
433 0);
431 434
432static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0); 435static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
433static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0); 436static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
index 7d08015b980d..2d6555d73170 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
@@ -108,6 +108,7 @@ static struct ccu_nkmp pll_video0_clk = {
108 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 108 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
109 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ 109 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
110 .p = _SUNXI_CCU_DIV(0, 2), /* output divider */ 110 .p = _SUNXI_CCU_DIV(0, 2), /* output divider */
111 .max_rate = 3000000000UL,
111 .common = { 112 .common = {
112 .reg = 0x010, 113 .reg = 0x010,
113 .lock_reg = CCU_SUN8I_A83T_LOCK_REG, 114 .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
@@ -220,6 +221,7 @@ static struct ccu_nkmp pll_video1_clk = {
220 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 221 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
221 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ 222 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
222 .p = _SUNXI_CCU_DIV(0, 2), /* external divider p */ 223 .p = _SUNXI_CCU_DIV(0, 2), /* external divider p */
224 .max_rate = 3000000000UL,
223 .common = { 225 .common = {
224 .reg = 0x04c, 226 .reg = 0x04c,
225 .lock_reg = CCU_SUN8I_A83T_LOCK_REG, 227 .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 77ed0b0ba681..eb5c608428fa 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -69,18 +69,19 @@ static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
69 BIT(28), /* lock */ 69 BIT(28), /* lock */
70 CLK_SET_RATE_UNGATE); 70 CLK_SET_RATE_UNGATE);
71 71
72static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video_clk, "pll-video", 72static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video_clk, "pll-video",
73 "osc24M", 0x0010, 73 "osc24M", 0x0010,
74 192000000, /* Minimum rate */ 74 192000000, /* Minimum rate */
75 8, 7, /* N */ 75 912000000, /* Maximum rate */
76 0, 4, /* M */ 76 8, 7, /* N */
77 BIT(24), /* frac enable */ 77 0, 4, /* M */
78 BIT(25), /* frac select */ 78 BIT(24), /* frac enable */
79 270000000, /* frac rate 0 */ 79 BIT(25), /* frac select */
80 297000000, /* frac rate 1 */ 80 270000000, /* frac rate 0 */
81 BIT(31), /* gate */ 81 297000000, /* frac rate 1 */
82 BIT(28), /* lock */ 82 BIT(31), /* gate */
83 CLK_SET_RATE_UNGATE); 83 BIT(28), /* lock */
84 CLK_SET_RATE_UNGATE);
84 85
85static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", 86static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
86 "osc24M", 0x0018, 87 "osc24M", 0x0018,
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index 0f388f6944d5..582ebd41d20d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -65,19 +65,19 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
65 BIT(28), /* lock */ 65 BIT(28), /* lock */
66 CLK_SET_RATE_UNGATE); 66 CLK_SET_RATE_UNGATE);
67 67
68/* TODO: The result of N/M is required to be in [8, 25] range. */ 68static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
69static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0", 69 "osc24M", 0x0010,
70 "osc24M", 0x0010, 70 192000000, /* Minimum rate */
71 192000000, /* Minimum rate */ 71 1008000000, /* Maximum rate */
72 8, 7, /* N */ 72 8, 7, /* N */
73 0, 4, /* M */ 73 0, 4, /* M */
74 BIT(24), /* frac enable */ 74 BIT(24), /* frac enable */
75 BIT(25), /* frac select */ 75 BIT(25), /* frac select */
76 270000000, /* frac rate 0 */ 76 270000000, /* frac rate 0 */
77 297000000, /* frac rate 1 */ 77 297000000, /* frac rate 1 */
78 BIT(31), /* gate */ 78 BIT(31), /* gate */
79 BIT(28), /* lock */ 79 BIT(28), /* lock */
80 CLK_SET_RATE_UNGATE); 80 CLK_SET_RATE_UNGATE);
81 81
82/* TODO: The result of N/M is required to be in [8, 25] range. */ 82/* TODO: The result of N/M is required to be in [8, 25] range. */
83static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", 83static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
@@ -152,19 +152,19 @@ static struct ccu_nk pll_periph1_clk = {
152 }, 152 },
153}; 153};
154 154
155/* TODO: The result of N/M is required to be in [8, 25] range. */ 155static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
156static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1", 156 "osc24M", 0x030,
157 "osc24M", 0x030, 157 192000000, /* Minimum rate */
158 192000000, /* Minimum rate */ 158 1008000000, /* Maximum rate */
159 8, 7, /* N */ 159 8, 7, /* N */
160 0, 4, /* M */ 160 0, 4, /* M */
161 BIT(24), /* frac enable */ 161 BIT(24), /* frac enable */
162 BIT(25), /* frac select */ 162 BIT(25), /* frac select */
163 270000000, /* frac rate 0 */ 163 270000000, /* frac rate 0 */
164 297000000, /* frac rate 1 */ 164 297000000, /* frac rate 1 */
165 BIT(31), /* gate */ 165 BIT(31), /* gate */
166 BIT(28), /* lock */ 166 BIT(28), /* lock */
167 CLK_SET_RATE_UNGATE); 167 CLK_SET_RATE_UNGATE);
168 168
169static struct ccu_nkm pll_sata_clk = { 169static struct ccu_nkm pll_sata_clk = {
170 .enable = BIT(31), 170 .enable = BIT(31),
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
index ebd9436d2c7c..9b49adb20d07 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.c
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
@@ -137,6 +137,13 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
137 if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV) 137 if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
138 rate *= nkmp->fixed_post_div; 138 rate *= nkmp->fixed_post_div;
139 139
140 if (nkmp->max_rate && rate > nkmp->max_rate) {
141 rate = nkmp->max_rate;
142 if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
143 rate /= nkmp->fixed_post_div;
144 return rate;
145 }
146
140 _nkmp.min_n = nkmp->n.min ?: 1; 147 _nkmp.min_n = nkmp->n.min ?: 1;
141 _nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width; 148 _nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width;
142 _nkmp.min_k = nkmp->k.min ?: 1; 149 _nkmp.min_k = nkmp->k.min ?: 1;
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.h b/drivers/clk/sunxi-ng/ccu_nkmp.h
index 6940503e7fc4..a9f8c116a745 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.h
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.h
@@ -35,6 +35,7 @@ struct ccu_nkmp {
35 struct ccu_div_internal p; 35 struct ccu_div_internal p;
36 36
37 unsigned int fixed_post_div; 37 unsigned int fixed_post_div;
38 unsigned int max_rate;
38 39
39 struct ccu_common common; 40 struct ccu_common common;
40}; 41};
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
index 4e2073307f34..6fe3c14f7b2d 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.c
+++ b/drivers/clk/sunxi-ng/ccu_nm.c
@@ -124,6 +124,13 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
124 return rate; 124 return rate;
125 } 125 }
126 126
127 if (nm->max_rate && rate > nm->max_rate) {
128 rate = nm->max_rate;
129 if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
130 rate /= nm->fixed_post_div;
131 return rate;
132 }
133
127 if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) { 134 if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) {
128 if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) 135 if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
129 rate /= nm->fixed_post_div; 136 rate /= nm->fixed_post_div;
diff --git a/drivers/clk/sunxi-ng/ccu_nm.h b/drivers/clk/sunxi-ng/ccu_nm.h
index 1d8b459c50b7..de232f2199a6 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.h
+++ b/drivers/clk/sunxi-ng/ccu_nm.h
@@ -38,6 +38,7 @@ struct ccu_nm {
38 38
39 unsigned int fixed_post_div; 39 unsigned int fixed_post_div;
40 unsigned int min_rate; 40 unsigned int min_rate;
41 unsigned int max_rate;
41 42
42 struct ccu_common common; 43 struct ccu_common common;
43}; 44};
@@ -115,6 +116,35 @@ struct ccu_nm {
115 }, \ 116 }, \
116 } 117 }
117 118
119#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(_struct, _name, \
120 _parent, _reg, \
121 _min_rate, _max_rate, \
122 _nshift, _nwidth, \
123 _mshift, _mwidth, \
124 _frac_en, _frac_sel, \
125 _frac_rate_0, \
126 _frac_rate_1, \
127 _gate, _lock, _flags) \
128 struct ccu_nm _struct = { \
129 .enable = _gate, \
130 .lock = _lock, \
131 .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
132 .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
133 .frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \
134 _frac_rate_0, \
135 _frac_rate_1), \
136 .min_rate = _min_rate, \
137 .max_rate = _max_rate, \
138 .common = { \
139 .reg = _reg, \
140 .features = CCU_FEATURE_FRACTIONAL, \
141 .hw.init = CLK_HW_INIT(_name, \
142 _parent, \
143 &ccu_nm_ops, \
144 _flags), \
145 }, \
146 }
147
118#define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ 148#define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \
119 _nshift, _nwidth, \ 149 _nshift, _nwidth, \
120 _mshift, _mwidth, \ 150 _mshift, _mwidth, \
diff --git a/drivers/clk/sunxi/clk-mod0.c b/drivers/clk/sunxi/clk-mod0.c
index a27c264cc9b4..fc0278a1acc7 100644
--- a/drivers/clk/sunxi/clk-mod0.c
+++ b/drivers/clk/sunxi/clk-mod0.c
@@ -140,8 +140,8 @@ static void __init sun9i_a80_mod0_setup(struct device_node *node)
140 140
141 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 141 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
142 if (IS_ERR(reg)) { 142 if (IS_ERR(reg)) {
143 pr_err("Could not get registers for mod0-clk: %s\n", 143 pr_err("Could not get registers for mod0-clk: %pOFn\n",
144 node->name); 144 node);
145 return; 145 return;
146 } 146 }
147 147
@@ -306,7 +306,7 @@ static void __init sunxi_mmc_setup(struct device_node *node,
306 306
307 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 307 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
308 if (IS_ERR(reg)) { 308 if (IS_ERR(reg)) {
309 pr_err("Couldn't map the %s clock registers\n", node->name); 309 pr_err("Couldn't map the %pOFn clock registers\n", node);
310 return; 310 return;
311 } 311 }
312 312
diff --git a/drivers/clk/sunxi/clk-sun9i-core.c b/drivers/clk/sunxi/clk-sun9i-core.c
index e9295c286d5d..7e21b2b10c94 100644
--- a/drivers/clk/sunxi/clk-sun9i-core.c
+++ b/drivers/clk/sunxi/clk-sun9i-core.c
@@ -88,8 +88,8 @@ static void __init sun9i_a80_pll4_setup(struct device_node *node)
88 88
89 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 89 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
90 if (IS_ERR(reg)) { 90 if (IS_ERR(reg)) {
91 pr_err("Could not get registers for a80-pll4-clk: %s\n", 91 pr_err("Could not get registers for a80-pll4-clk: %pOFn\n",
92 node->name); 92 node);
93 return; 93 return;
94 } 94 }
95 95
@@ -142,8 +142,8 @@ static void __init sun9i_a80_gt_setup(struct device_node *node)
142 142
143 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 143 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
144 if (IS_ERR(reg)) { 144 if (IS_ERR(reg)) {
145 pr_err("Could not get registers for a80-gt-clk: %s\n", 145 pr_err("Could not get registers for a80-gt-clk: %pOFn\n",
146 node->name); 146 node);
147 return; 147 return;
148 } 148 }
149 149
@@ -197,8 +197,8 @@ static void __init sun9i_a80_ahb_setup(struct device_node *node)
197 197
198 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 198 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
199 if (IS_ERR(reg)) { 199 if (IS_ERR(reg)) {
200 pr_err("Could not get registers for a80-ahb-clk: %s\n", 200 pr_err("Could not get registers for a80-ahb-clk: %pOFn\n",
201 node->name); 201 node);
202 return; 202 return;
203 } 203 }
204 204
@@ -223,8 +223,8 @@ static void __init sun9i_a80_apb0_setup(struct device_node *node)
223 223
224 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 224 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
225 if (IS_ERR(reg)) { 225 if (IS_ERR(reg)) {
226 pr_err("Could not get registers for a80-apb0-clk: %s\n", 226 pr_err("Could not get registers for a80-apb0-clk: %pOFn\n",
227 node->name); 227 node);
228 return; 228 return;
229 } 229 }
230 230
@@ -280,8 +280,8 @@ static void __init sun9i_a80_apb1_setup(struct device_node *node)
280 280
281 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 281 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
282 if (IS_ERR(reg)) { 282 if (IS_ERR(reg)) {
283 pr_err("Could not get registers for a80-apb1-clk: %s\n", 283 pr_err("Could not get registers for a80-apb1-clk: %pOFn\n",
284 node->name); 284 node);
285 return; 285 return;
286 } 286 }
287 287
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 012714d94b42..892c29030b7b 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -568,8 +568,8 @@ static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
568 568
569 reg = of_iomap(node, 0); 569 reg = of_iomap(node, 0);
570 if (!reg) { 570 if (!reg) {
571 pr_err("Could not get registers for factors-clk: %s\n", 571 pr_err("Could not get registers for factors-clk: %pOFn\n",
572 node->name); 572 node);
573 return NULL; 573 return NULL;
574 } 574 }
575 575
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 5ab295d2a3cb..5ca1e39dd88a 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -6,7 +6,8 @@ clk-common = dpll.o composite.o divider.o gate.o \
6 fixed-factor.o mux.o apll.o \ 6 fixed-factor.o mux.o apll.o \
7 clkt_dpll.o clkt_iclk.o clkt_dflt.o \ 7 clkt_dpll.o clkt_iclk.o clkt_dflt.o \
8 clkctrl.o 8 clkctrl.o
9obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o 9obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o \
10 clk-33xx-compat.o
10obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o 11obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o
11obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o 12obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
12obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \ 13obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \
@@ -16,8 +17,10 @@ obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o \
16obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o \ 17obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o \
17 dpll3xxx.o dpll44xx.o 18 dpll3xxx.o dpll44xx.o
18obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \ 19obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \
19 clk-dra7-atl.o dpll3xxx.o dpll44xx.o 20 clk-dra7-atl.o dpll3xxx.o \
20obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o 21 dpll44xx.o clk-7xx-compat.o
22obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o \
23 clk-43xx-compat.o
21 24
22endif # CONFIG_ARCH_OMAP2PLUS 25endif # CONFIG_ARCH_OMAP2PLUS
23 26
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index 61c126a5d26a..222f68bc3f2a 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -143,8 +143,8 @@ static void __init omap_clk_register_apll(void *user,
143 143
144 clk = of_clk_get(node, 0); 144 clk = of_clk_get(node, 0);
145 if (IS_ERR(clk)) { 145 if (IS_ERR(clk)) {
146 pr_debug("clk-ref for %s not ready, retry\n", 146 pr_debug("clk-ref for %pOFn not ready, retry\n",
147 node->name); 147 node);
148 if (!ti_clk_retry_init(node, hw, omap_clk_register_apll)) 148 if (!ti_clk_retry_init(node, hw, omap_clk_register_apll))
149 return; 149 return;
150 150
@@ -155,8 +155,8 @@ static void __init omap_clk_register_apll(void *user,
155 155
156 clk = of_clk_get(node, 1); 156 clk = of_clk_get(node, 1);
157 if (IS_ERR(clk)) { 157 if (IS_ERR(clk)) {
158 pr_debug("clk-bypass for %s not ready, retry\n", 158 pr_debug("clk-bypass for %pOFn not ready, retry\n",
159 node->name); 159 node);
160 if (!ti_clk_retry_init(node, hw, omap_clk_register_apll)) 160 if (!ti_clk_retry_init(node, hw, omap_clk_register_apll))
161 return; 161 return;
162 162
@@ -202,7 +202,7 @@ static void __init of_dra7_apll_setup(struct device_node *node)
202 202
203 init->num_parents = of_clk_get_parent_count(node); 203 init->num_parents = of_clk_get_parent_count(node);
204 if (init->num_parents < 1) { 204 if (init->num_parents < 1) {
205 pr_err("dra7 apll %s must have parent(s)\n", node->name); 205 pr_err("dra7 apll %pOFn must have parent(s)\n", node);
206 goto cleanup; 206 goto cleanup;
207 } 207 }
208 208
@@ -366,7 +366,7 @@ static void __init of_omap2_apll_setup(struct device_node *node)
366 366
367 init->num_parents = of_clk_get_parent_count(node); 367 init->num_parents = of_clk_get_parent_count(node);
368 if (init->num_parents != 1) { 368 if (init->num_parents != 1) {
369 pr_err("%s must have one parent\n", node->name); 369 pr_err("%pOFn must have one parent\n", node);
370 goto cleanup; 370 goto cleanup;
371 } 371 }
372 372
@@ -374,13 +374,13 @@ static void __init of_omap2_apll_setup(struct device_node *node)
374 init->parent_names = &parent_name; 374 init->parent_names = &parent_name;
375 375
376 if (of_property_read_u32(node, "ti,clock-frequency", &val)) { 376 if (of_property_read_u32(node, "ti,clock-frequency", &val)) {
377 pr_err("%s missing clock-frequency\n", node->name); 377 pr_err("%pOFn missing clock-frequency\n", node);
378 goto cleanup; 378 goto cleanup;
379 } 379 }
380 clk_hw->fixed_rate = val; 380 clk_hw->fixed_rate = val;
381 381
382 if (of_property_read_u32(node, "ti,bit-shift", &val)) { 382 if (of_property_read_u32(node, "ti,bit-shift", &val)) {
383 pr_err("%s missing bit-shift\n", node->name); 383 pr_err("%pOFn missing bit-shift\n", node);
384 goto cleanup; 384 goto cleanup;
385 } 385 }
386 386
@@ -389,7 +389,7 @@ static void __init of_omap2_apll_setup(struct device_node *node)
389 ad->autoidle_mask = 0x3 << val; 389 ad->autoidle_mask = 0x3 << val;
390 390
391 if (of_property_read_u32(node, "ti,idlest-shift", &val)) { 391 if (of_property_read_u32(node, "ti,idlest-shift", &val)) {
392 pr_err("%s missing idlest-shift\n", node->name); 392 pr_err("%pOFn missing idlest-shift\n", node);
393 goto cleanup; 393 goto cleanup;
394 } 394 }
395 395
diff --git a/drivers/clk/ti/clk-33xx-compat.c b/drivers/clk/ti/clk-33xx-compat.c
new file mode 100644
index 000000000000..3e07f127912a
--- /dev/null
+++ b/drivers/clk/ti/clk-33xx-compat.c
@@ -0,0 +1,218 @@
1/*
2 * AM33XX Clock init
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc
5 * Tero Kristo (t-kristo@ti.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/clk.h>
20#include <linux/clk-provider.h>
21#include <linux/clk/ti.h>
22#include <dt-bindings/clock/am3.h>
23
24#include "clock.h"
25
26static const char * const am3_gpio1_dbclk_parents[] __initconst = {
27 "l4_per_cm:clk:0138:0",
28 NULL,
29};
30
31static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
32 { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
33 { 0 },
34};
35
36static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
37 { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
38 { 0 },
39};
40
41static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
42 { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
43 { 0 },
44};
45
46static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = {
47 { AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
48 { AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk", "lcdc_clkdm" },
49 { AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" },
50 { AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
51 { AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" },
52 { AM3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
53 { AM3_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
54 { AM3_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
55 { AM3_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
56 { AM3_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
57 { AM3_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
58 { AM3_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
59 { AM3_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
60 { AM3_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
61 { AM3_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
62 { AM3_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
63 { AM3_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
64 { AM3_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
65 { AM3_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
66 { AM3_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
67 { AM3_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
68 { AM3_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
69 { AM3_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
70 { AM3_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
71 { AM3_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
72 { AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
73 { AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
74 { AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
75 { AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
76 { AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
77 { AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
78 { AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
79 { AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
80 { AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
81 { AM3_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
82 { AM3_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
83 { AM3_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
84 { AM3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
85 { AM3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
86 { AM3_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
87 { AM3_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
88 { AM3_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
89 { AM3_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
90 { AM3_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
91 { AM3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
92 { AM3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
93 { AM3_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
94 { AM3_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
95 { AM3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l4hs_clkdm" },
96 { AM3_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
97 { AM3_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck", "clk_24mhz_clkdm" },
98 { 0 },
99};
100
101static const char * const am3_gpio0_dbclk_parents[] __initconst = {
102 "gpio0_dbclk_mux_ck",
103 NULL,
104};
105
106static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
107 { 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
108 { 0 },
109};
110
111static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
112 "sys_clkin_ck",
113 NULL,
114};
115
116static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
117 "l4_wkup_cm:clk:0010:19",
118 "l4_wkup_cm:clk:0010:30",
119 NULL,
120};
121
122static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
123 "l4_wkup_cm:clk:0010:20",
124 NULL,
125};
126
127static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = {
128 .max_div = 64,
129 .flags = CLK_DIVIDER_POWER_OF_TWO,
130};
131
132static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
133 "l4_wkup_cm:clk:0010:22",
134 NULL,
135};
136
137static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = {
138 .max_div = 64,
139 .flags = CLK_DIVIDER_POWER_OF_TWO,
140};
141
142static const char * const am3_dbg_clka_ck_parents[] __initconst = {
143 "dpll_core_m4_ck",
144 NULL,
145};
146
147static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
148 { 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL },
149 { 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
150 { 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
151 { 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data },
152 { 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data },
153 { 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
154 { 0 },
155};
156
157static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
158 { AM3_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
159 { AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
160 { AM3_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
161 { AM3_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0010:24", "l3_aon_clkdm" },
162 { AM3_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck", "l4_wkup_aon_clkdm" },
163 { AM3_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
164 { AM3_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
165 { AM3_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
166 { AM3_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
167 { AM3_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
168 { AM3_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
169 { AM3_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
170 { 0 },
171};
172
173static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
174 { AM3_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
175 { 0 },
176};
177
178static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
179 { AM3_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
180 { 0 },
181};
182
183static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
184 { AM3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
185 { 0 },
186};
187
188static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
189 { AM3_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
190 { 0 },
191};
192
193const struct omap_clkctrl_data am3_clkctrl_compat_data[] __initconst = {
194 { 0x44e00014, am3_l4_per_clkctrl_regs },
195 { 0x44e00404, am3_l4_wkup_clkctrl_regs },
196 { 0x44e00604, am3_mpu_clkctrl_regs },
197 { 0x44e00800, am3_l4_rtc_clkctrl_regs },
198 { 0x44e00904, am3_gfx_l3_clkctrl_regs },
199 { 0x44e00a20, am3_l4_cefuse_clkctrl_regs },
200 { 0 },
201};
202
203struct ti_dt_clk am33xx_compat_clks[] = {
204 DT_CLK(NULL, "timer_32k_ck", "l4_per_cm:0138:0"),
205 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
206 DT_CLK(NULL, "clkdiv32k_ick", "l4_per_cm:0138:0"),
207 DT_CLK(NULL, "dbg_clka_ck", "l4_wkup_cm:0010:30"),
208 DT_CLK(NULL, "dbg_sysclk_ck", "l4_wkup_cm:0010:19"),
209 DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0004:18"),
210 DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0098:18"),
211 DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:009c:18"),
212 DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:00a0:18"),
213 DT_CLK(NULL, "stm_clk_div_ck", "l4_wkup_cm:0010:27"),
214 DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l4_wkup_cm:0010:22"),
215 DT_CLK(NULL, "trace_clk_div_ck", "l4_wkup_cm:0010:24"),
216 DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l4_wkup_cm:0010:20"),
217 { .node_name = NULL },
218};
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
index 12e0a2d19911..a360d3109555 100644
--- a/drivers/clk/ti/clk-33xx.c
+++ b/drivers/clk/ti/clk-33xx.c
@@ -24,7 +24,7 @@
24#include "clock.h" 24#include "clock.h"
25 25
26static const char * const am3_gpio1_dbclk_parents[] __initconst = { 26static const char * const am3_gpio1_dbclk_parents[] __initconst = {
27 "l4_per_cm:clk:0138:0", 27 "clk-24mhz-clkctrl:0000:0",
28 NULL, 28 NULL,
29}; 29};
30 30
@@ -43,58 +43,86 @@ static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
43 { 0 }, 43 { 0 },
44}; 44};
45 45
46static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = { 46static const struct omap_clkctrl_reg_data am3_l4ls_clkctrl_regs[] __initconst = {
47 { AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" }, 47 { AM3_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
48 { AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk", "lcdc_clkdm" }, 48 { AM3_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
49 { AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" }, 49 { AM3_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
50 { AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 50 { AM3_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
51 { AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" }, 51 { AM3_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
52 { AM3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 52 { AM3_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
53 { AM3_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" }, 53 { AM3_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
54 { AM3_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" }, 54 { AM3_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
55 { AM3_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 55 { AM3_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
56 { AM3_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, 56 { AM3_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
57 { AM3_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 57 { AM3_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
58 { AM3_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 58 { AM3_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
59 { AM3_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 59 { AM3_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
60 { AM3_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 60 { AM3_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
61 { AM3_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 61 { AM3_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
62 { AM3_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 62 { AM3_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
63 { AM3_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" }, 63 { AM3_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
64 { AM3_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 64 { AM3_L4LS_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
65 { AM3_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 65 { AM3_L4LS_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
66 { AM3_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 66 { AM3_L4LS_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
67 { AM3_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 67 { AM3_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
68 { AM3_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" }, 68 { AM3_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
69 { AM3_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" }, 69 { AM3_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
70 { AM3_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" }, 70 { AM3_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
71 { AM3_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" }, 71 { AM3_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
72 { AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" }, 72 { AM3_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
73 { AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" }, 73 { AM3_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
74 { AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 74 { AM3_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
75 { AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 75 { AM3_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
76 { AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 76 { AM3_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
77 { AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 77 { AM3_L4LS_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
78 { AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 78 { 0 },
79 { AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" }, 79};
80 { AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" }, 80
81 { AM3_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 81static const struct omap_clkctrl_reg_data am3_l3s_clkctrl_regs[] __initconst = {
82 { AM3_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 82 { AM3_L3S_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck" },
83 { AM3_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 83 { AM3_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
84 { AM3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 84 { AM3_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" },
85 { AM3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 85 { AM3_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" },
86 { AM3_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" }, 86 { AM3_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
87 { AM3_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" }, 87 { 0 },
88 { AM3_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" }, 88};
89 { AM3_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, 89
90 { AM3_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" }, 90static const struct omap_clkctrl_reg_data am3_l3_clkctrl_regs[] __initconst = {
91 { AM3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 91 { AM3_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
92 { AM3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 92 { AM3_L3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck" },
93 { AM3_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 93 { AM3_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
94 { AM3_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 94 { AM3_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" },
95 { AM3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l4hs_clkdm" }, 95 { AM3_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
96 { AM3_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 96 { AM3_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
97 { AM3_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck", "clk_24mhz_clkdm" }, 97 { AM3_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
98 { AM3_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
99 { AM3_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
100 { AM3_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
101 { 0 },
102};
103
104static const struct omap_clkctrl_reg_data am3_l4hs_clkctrl_regs[] __initconst = {
105 { AM3_L4HS_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" },
106 { 0 },
107};
108
109static const struct omap_clkctrl_reg_data am3_pruss_ocp_clkctrl_regs[] __initconst = {
110 { AM3_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk" },
111 { 0 },
112};
113
114static const struct omap_clkctrl_reg_data am3_cpsw_125mhz_clkctrl_regs[] __initconst = {
115 { AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
116 { 0 },
117};
118
119static const struct omap_clkctrl_reg_data am3_lcdc_clkctrl_regs[] __initconst = {
120 { AM3_LCDC_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk" },
121 { 0 },
122};
123
124static const struct omap_clkctrl_reg_data am3_clk_24mhz_clkctrl_regs[] __initconst = {
125 { AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck" },
98 { 0 }, 126 { 0 },
99}; 127};
100 128
@@ -108,19 +136,33 @@ static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
108 { 0 }, 136 { 0 },
109}; 137};
110 138
139static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
140 { AM3_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
141 { AM3_L4_WKUP_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
142 { AM3_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
143 { AM3_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
144 { AM3_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
145 { AM3_L4_WKUP_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
146 { AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
147 { AM3_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
148 { AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
149 { AM3_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
150 { 0 },
151};
152
111static const char * const am3_dbg_sysclk_ck_parents[] __initconst = { 153static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
112 "sys_clkin_ck", 154 "sys_clkin_ck",
113 NULL, 155 NULL,
114}; 156};
115 157
116static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = { 158static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
117 "l4_wkup_cm:clk:0010:19", 159 "l3-aon-clkctrl:0000:19",
118 "l4_wkup_cm:clk:0010:30", 160 "l3-aon-clkctrl:0000:30",
119 NULL, 161 NULL,
120}; 162};
121 163
122static const char * const am3_trace_clk_div_ck_parents[] __initconst = { 164static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
123 "l4_wkup_cm:clk:0010:20", 165 "l3-aon-clkctrl:0000:20",
124 NULL, 166 NULL,
125}; 167};
126 168
@@ -130,7 +172,7 @@ static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst
130}; 172};
131 173
132static const char * const am3_stm_clk_div_ck_parents[] __initconst = { 174static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
133 "l4_wkup_cm:clk:0010:22", 175 "l3-aon-clkctrl:0000:22",
134 NULL, 176 NULL,
135}; 177};
136 178
@@ -154,66 +196,69 @@ static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
154 { 0 }, 196 { 0 },
155}; 197};
156 198
157static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = { 199static const struct omap_clkctrl_reg_data am3_l3_aon_clkctrl_regs[] __initconst = {
158 { AM3_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, 200 { AM3_L3_AON_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l3-aon-clkctrl:0000:24" },
159 { AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, 201 { 0 },
160 { AM3_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, 202};
161 { AM3_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0010:24", "l3_aon_clkdm" }, 203
162 { AM3_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck", "l4_wkup_aon_clkdm" }, 204static const struct omap_clkctrl_reg_data am3_l4_wkup_aon_clkctrl_regs[] __initconst = {
163 { AM3_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" }, 205 { AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck" },
164 { AM3_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
165 { AM3_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
166 { AM3_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
167 { AM3_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
168 { AM3_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
169 { AM3_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
170 { 0 }, 206 { 0 },
171}; 207};
172 208
173static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = { 209static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
174 { AM3_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" }, 210 { AM3_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
175 { 0 }, 211 { 0 },
176}; 212};
177 213
178static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = { 214static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
179 { AM3_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" }, 215 { AM3_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
180 { 0 }, 216 { 0 },
181}; 217};
182 218
183static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = { 219static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
184 { AM3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" }, 220 { AM3_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
185 { 0 }, 221 { 0 },
186}; 222};
187 223
188static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = { 224static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
189 { AM3_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" }, 225 { AM3_L4_CEFUSE_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
190 { 0 }, 226 { 0 },
191}; 227};
192 228
193const struct omap_clkctrl_data am3_clkctrl_data[] __initconst = { 229const struct omap_clkctrl_data am3_clkctrl_data[] __initconst = {
194 { 0x44e00014, am3_l4_per_clkctrl_regs }, 230 { 0x44e00038, am3_l4ls_clkctrl_regs },
195 { 0x44e00404, am3_l4_wkup_clkctrl_regs }, 231 { 0x44e0001c, am3_l3s_clkctrl_regs },
196 { 0x44e00604, am3_mpu_clkctrl_regs }, 232 { 0x44e00024, am3_l3_clkctrl_regs },
233 { 0x44e00120, am3_l4hs_clkctrl_regs },
234 { 0x44e000e8, am3_pruss_ocp_clkctrl_regs },
235 { 0x44e00000, am3_cpsw_125mhz_clkctrl_regs },
236 { 0x44e00018, am3_lcdc_clkctrl_regs },
237 { 0x44e0014c, am3_clk_24mhz_clkctrl_regs },
238 { 0x44e00400, am3_l4_wkup_clkctrl_regs },
239 { 0x44e00414, am3_l3_aon_clkctrl_regs },
240 { 0x44e004b0, am3_l4_wkup_aon_clkctrl_regs },
241 { 0x44e00600, am3_mpu_clkctrl_regs },
197 { 0x44e00800, am3_l4_rtc_clkctrl_regs }, 242 { 0x44e00800, am3_l4_rtc_clkctrl_regs },
198 { 0x44e00904, am3_gfx_l3_clkctrl_regs }, 243 { 0x44e00900, am3_gfx_l3_clkctrl_regs },
199 { 0x44e00a20, am3_l4_cefuse_clkctrl_regs }, 244 { 0x44e00a00, am3_l4_cefuse_clkctrl_regs },
200 { 0 }, 245 { 0 },
201}; 246};
202 247
203static struct ti_dt_clk am33xx_clks[] = { 248static struct ti_dt_clk am33xx_clks[] = {
204 DT_CLK(NULL, "timer_32k_ck", "l4_per_cm:0138:0"), 249 DT_CLK(NULL, "timer_32k_ck", "clk-24mhz-clkctrl:0000:0"),
205 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), 250 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
206 DT_CLK(NULL, "clkdiv32k_ick", "l4_per_cm:0138:0"), 251 DT_CLK(NULL, "clkdiv32k_ick", "clk-24mhz-clkctrl:0000:0"),
207 DT_CLK(NULL, "dbg_clka_ck", "l4_wkup_cm:0010:30"), 252 DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"),
208 DT_CLK(NULL, "dbg_sysclk_ck", "l4_wkup_cm:0010:19"), 253 DT_CLK(NULL, "dbg_sysclk_ck", "l3-aon-clkctrl:0000:19"),
209 DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0004:18"), 254 DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0008:18"),
210 DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0098:18"), 255 DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0074:18"),
211 DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:009c:18"), 256 DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0078:18"),
212 DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:00a0:18"), 257 DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:007c:18"),
213 DT_CLK(NULL, "stm_clk_div_ck", "l4_wkup_cm:0010:27"), 258 DT_CLK(NULL, "stm_clk_div_ck", "l3-aon-clkctrl:0000:27"),
214 DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l4_wkup_cm:0010:22"), 259 DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l3-aon-clkctrl:0000:22"),
215 DT_CLK(NULL, "trace_clk_div_ck", "l4_wkup_cm:0010:24"), 260 DT_CLK(NULL, "trace_clk_div_ck", "l3-aon-clkctrl:0000:24"),
216 DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l4_wkup_cm:0010:20"), 261 DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l3-aon-clkctrl:0000:20"),
217 { .node_name = NULL }, 262 { .node_name = NULL },
218}; 263};
219 264
@@ -232,7 +277,10 @@ int __init am33xx_dt_clk_init(void)
232{ 277{
233 struct clk *clk1, *clk2; 278 struct clk *clk1, *clk2;
234 279
235 ti_dt_clocks_register(am33xx_clks); 280 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
281 ti_dt_clocks_register(am33xx_compat_clks);
282 else
283 ti_dt_clocks_register(am33xx_clks);
236 284
237 omap2_clk_disable_autoidle_all(); 285 omap2_clk_disable_autoidle_all();
238 286
diff --git a/drivers/clk/ti/clk-43xx-compat.c b/drivers/clk/ti/clk-43xx-compat.c
new file mode 100644
index 000000000000..513039843392
--- /dev/null
+++ b/drivers/clk/ti/clk-43xx-compat.c
@@ -0,0 +1,225 @@
1/*
2 * AM43XX Clock init
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc
5 * Tero Kristo (t-kristo@ti.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/clk.h>
20#include <linux/clk-provider.h>
21#include <linux/clk/ti.h>
22#include <dt-bindings/clock/am4.h>
23
24#include "clock.h"
25
26static const char * const am4_synctimer_32kclk_parents[] __initconst = {
27 "mux_synctimer32k_ck",
28 NULL,
29};
30
31static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = {
32 { 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL },
33 { 0 },
34};
35
36static const char * const am4_gpio0_dbclk_parents[] __initconst = {
37 "gpio0_dbclk_mux_ck",
38 NULL,
39};
40
41static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
42 { 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL },
43 { 0 },
44};
45
46static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
47 { AM4_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck", "l3s_tsc_clkdm" },
48 { AM4_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
49 { AM4_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "sys_clkin_ck" },
50 { AM4_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0210:8" },
51 { AM4_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck", "l4_wkup_clkdm" },
52 { AM4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck", "l4_wkup_clkdm" },
53 { AM4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
54 { AM4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
55 { AM4_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck", "l4_wkup_clkdm" },
56 { AM4_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck", "l4_wkup_clkdm" },
57 { AM4_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
58 { AM4_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
59 { 0 },
60};
61
62static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
63 { AM4_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
64 { 0 },
65};
66
67static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
68 { AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
69 { 0 },
70};
71
72static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
73 { AM4_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
74 { 0 },
75};
76
77static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = {
78 "dpll_per_clkdcoldo",
79 NULL,
80};
81
82static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = {
83 { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
84 { 0 },
85};
86
87static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst = {
88 { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
89 { 0 },
90};
91
92static const char * const am4_gpio1_dbclk_parents[] __initconst = {
93 "clkdiv32k_ick",
94 NULL,
95};
96
97static const struct omap_clkctrl_bit_data am4_gpio2_bit_data[] __initconst = {
98 { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
99 { 0 },
100};
101
102static const struct omap_clkctrl_bit_data am4_gpio3_bit_data[] __initconst = {
103 { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
104 { 0 },
105};
106
107static const struct omap_clkctrl_bit_data am4_gpio4_bit_data[] __initconst = {
108 { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
109 { 0 },
110};
111
112static const struct omap_clkctrl_bit_data am4_gpio5_bit_data[] __initconst = {
113 { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
114 { 0 },
115};
116
117static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = {
118 { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
119 { 0 },
120};
121
122static const struct omap_clkctrl_reg_data am4_l4_per_clkctrl_regs[] __initconst = {
123 { AM4_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
124 { AM4_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
125 { AM4_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
126 { AM4_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
127 { AM4_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
128 { AM4_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
129 { AM4_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
130 { AM4_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
131 { AM4_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
132 { AM4_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
133 { AM4_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
134 { AM4_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
135 { AM4_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l3_clkdm" },
136 { AM4_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
137 { AM4_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
138 { AM4_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
139 { AM4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
140 { AM4_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
141 { AM4_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
142 { AM4_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
143 { AM4_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
144 { AM4_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
145 { AM4_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
146 { AM4_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
147 { AM4_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
148 { AM4_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
149 { AM4_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
150 { AM4_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
151 { AM4_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
152 { AM4_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
153 { AM4_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
154 { AM4_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
155 { AM4_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
156 { AM4_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
157 { AM4_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
158 { AM4_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
159 { AM4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },
160 { AM4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
161 { AM4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
162 { AM4_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
163 { AM4_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
164 { AM4_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
165 { AM4_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
166 { AM4_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
167 { AM4_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
168 { AM4_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
169 { AM4_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
170 { AM4_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
171 { AM4_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
172 { AM4_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
173 { AM4_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
174 { AM4_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
175 { AM4_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
176 { AM4_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
177 { AM4_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
178 { AM4_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },
179 { AM4_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },
180 { AM4_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },
181 { AM4_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },
182 { AM4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
183 { AM4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
184 { AM4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
185 { AM4_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
186 { AM4_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
187 { AM4_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
188 { AM4_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
189 { AM4_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck", "emif_clkdm" },
190 { AM4_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk", "dss_clkdm" },
191 { AM4_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
192 { 0 },
193};
194
195const struct omap_clkctrl_data am4_clkctrl_compat_data[] __initconst = {
196 { 0x44df2820, am4_l4_wkup_clkctrl_regs },
197 { 0x44df8320, am4_mpu_clkctrl_regs },
198 { 0x44df8420, am4_gfx_l3_clkctrl_regs },
199 { 0x44df8520, am4_l4_rtc_clkctrl_regs },
200 { 0x44df8820, am4_l4_per_clkctrl_regs },
201 { 0 },
202};
203
204const struct omap_clkctrl_data am438x_clkctrl_compat_data[] __initconst = {
205 { 0x44df2820, am4_l4_wkup_clkctrl_regs },
206 { 0x44df8320, am4_mpu_clkctrl_regs },
207 { 0x44df8420, am4_gfx_l3_clkctrl_regs },
208 { 0x44df8820, am4_l4_per_clkctrl_regs },
209 { 0 },
210};
211
212struct ti_dt_clk am43xx_compat_clks[] = {
213 DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
214 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
215 DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0348:8"),
216 DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0458:8"),
217 DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0460:8"),
218 DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0468:8"),
219 DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0470:8"),
220 DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0478:8"),
221 DT_CLK(NULL, "synctimer_32kclk", "l4_wkup_cm:0210:8"),
222 DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l4_per_cm:0240:8"),
223 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l4_per_cm:0248:8"),
224 { .node_name = NULL },
225};
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index 63c5ddb50187..2782d91838ac 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -23,6 +23,11 @@
23 23
24#include "clock.h" 24#include "clock.h"
25 25
26static const struct omap_clkctrl_reg_data am4_l3s_tsc_clkctrl_regs[] __initconst = {
27 { AM4_L3S_TSC_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
28 { 0 },
29};
30
26static const char * const am4_synctimer_32kclk_parents[] __initconst = { 31static const char * const am4_synctimer_32kclk_parents[] __initconst = {
27 "mux_synctimer32k_ck", 32 "mux_synctimer32k_ck",
28 NULL, 33 NULL,
@@ -33,6 +38,12 @@ static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst
33 { 0 }, 38 { 0 },
34}; 39};
35 40
41static const struct omap_clkctrl_reg_data am4_l4_wkup_aon_clkctrl_regs[] __initconst = {
42 { AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sys_clkin_ck" },
43 { AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4-wkup-aon-clkctrl:0008:8" },
44 { 0 },
45};
46
36static const char * const am4_gpio0_dbclk_parents[] __initconst = { 47static const char * const am4_gpio0_dbclk_parents[] __initconst = {
37 "gpio0_dbclk_mux_ck", 48 "gpio0_dbclk_mux_ck",
38 NULL, 49 NULL,
@@ -44,33 +55,45 @@ static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
44}; 55};
45 56
46static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = { 57static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
47 { AM4_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck", "l3s_tsc_clkdm" }, 58 { AM4_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
48 { AM4_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" }, 59 { AM4_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
49 { AM4_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "sys_clkin_ck" }, 60 { AM4_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
50 { AM4_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0210:8" }, 61 { AM4_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
51 { AM4_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck", "l4_wkup_clkdm" }, 62 { AM4_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
52 { AM4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck", "l4_wkup_clkdm" }, 63 { AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
53 { AM4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" }, 64 { AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
54 { AM4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" }, 65 { AM4_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
55 { AM4_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck", "l4_wkup_clkdm" }, 66 { AM4_L4_WKUP_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck" },
56 { AM4_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck", "l4_wkup_clkdm" },
57 { AM4_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
58 { AM4_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
59 { 0 }, 67 { 0 },
60}; 68};
61 69
62static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = { 70static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
63 { AM4_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" }, 71 { AM4_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
64 { 0 }, 72 { 0 },
65}; 73};
66 74
67static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = { 75static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
68 { AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" }, 76 { AM4_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
69 { 0 }, 77 { 0 },
70}; 78};
71 79
72static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = { 80static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
73 { AM4_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" }, 81 { AM4_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
82 { 0 },
83};
84
85static const struct omap_clkctrl_reg_data am4_l3_clkctrl_regs[] __initconst = {
86 { AM4_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
87 { AM4_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" },
88 { AM4_L3_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
89 { AM4_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
90 { AM4_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
91 { AM4_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
92 { AM4_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
93 { AM4_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
94 { AM4_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
95 { AM4_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
96 { AM4_L3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" },
74 { 0 }, 97 { 0 },
75}; 98};
76 99
@@ -89,6 +112,24 @@ static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst
89 { 0 }, 112 { 0 },
90}; 113};
91 114
115static const struct omap_clkctrl_reg_data am4_l3s_clkctrl_regs[] __initconst = {
116 { AM4_L3S_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
117 { AM4_L3S_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
118 { AM4_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
119 { AM4_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" },
120 { AM4_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" },
121 { AM4_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
122 { AM4_L3S_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
123 { AM4_L3S_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk" },
124 { AM4_L3S_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk" },
125 { 0 },
126};
127
128static const struct omap_clkctrl_reg_data am4_pruss_ocp_clkctrl_regs[] __initconst = {
129 { AM4_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk" },
130 { 0 },
131};
132
92static const char * const am4_gpio1_dbclk_parents[] __initconst = { 133static const char * const am4_gpio1_dbclk_parents[] __initconst = {
93 "clkdiv32k_ick", 134 "clkdiv32k_ick",
94 NULL, 135 NULL,
@@ -119,108 +160,115 @@ static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = {
119 { 0 }, 160 { 0 },
120}; 161};
121 162
122static const struct omap_clkctrl_reg_data am4_l4_per_clkctrl_regs[] __initconst = { 163static const struct omap_clkctrl_reg_data am4_l4ls_clkctrl_regs[] __initconst = {
123 { AM4_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 164 { AM4_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
124 { AM4_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" }, 165 { AM4_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
125 { AM4_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 166 { AM4_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
126 { AM4_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 167 { AM4_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
127 { AM4_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 168 { AM4_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
128 { AM4_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 169 { AM4_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
129 { AM4_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" }, 170 { AM4_L4LS_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
130 { AM4_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" }, 171 { AM4_L4LS_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
131 { AM4_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 172 { AM4_L4LS_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
132 { AM4_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 173 { AM4_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
133 { AM4_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 174 { AM4_L4LS_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
134 { AM4_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, 175 { AM4_L4LS_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
135 { AM4_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l3_clkdm" }, 176 { AM4_L4LS_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
136 { AM4_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" }, 177 { AM4_L4LS_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
137 { AM4_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" }, 178 { AM4_L4LS_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
138 { AM4_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" }, 179 { AM4_L4LS_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },
139 { AM4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" }, 180 { AM4_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
140 { AM4_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" }, 181 { AM4_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
141 { AM4_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" }, 182 { AM4_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
142 { AM4_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" }, 183 { AM4_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
143 { AM4_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" }, 184 { AM4_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
144 { AM4_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 185 { AM4_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
145 { AM4_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" }, 186 { AM4_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
146 { AM4_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" }, 187 { AM4_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
147 { AM4_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 188 { AM4_L4LS_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
148 { AM4_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 189 { AM4_L4LS_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
149 { AM4_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 190 { AM4_L4LS_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
150 { AM4_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 191 { AM4_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
151 { AM4_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 192 { AM4_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
152 { AM4_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 193 { AM4_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
153 { AM4_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 194 { AM4_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
154 { AM4_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 195 { AM4_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
155 { AM4_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 196 { AM4_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
156 { AM4_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 197 { AM4_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
157 { AM4_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 198 { AM4_L4LS_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },
158 { AM4_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, 199 { AM4_L4LS_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },
159 { AM4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" }, 200 { AM4_L4LS_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },
160 { AM4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 201 { AM4_L4LS_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },
161 { AM4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 202 { AM4_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
162 { AM4_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 203 { AM4_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
163 { AM4_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, 204 { AM4_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
164 { AM4_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, 205 { AM4_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
165 { AM4_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" }, 206 { AM4_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
166 { AM4_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 207 { AM4_L4LS_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
167 { AM4_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 208 { AM4_L4LS_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
168 { AM4_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 209 { 0 },
169 { AM4_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 210};
170 { AM4_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 211
171 { AM4_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, 212static const struct omap_clkctrl_reg_data am4_emif_clkctrl_regs[] __initconst = {
172 { AM4_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" }, 213 { AM4_EMIF_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck" },
173 { AM4_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" }, 214 { 0 },
174 { AM4_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" }, 215};
175 { AM4_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" }, 216
176 { AM4_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" }, 217static const struct omap_clkctrl_reg_data am4_dss_clkctrl_regs[] __initconst = {
177 { AM4_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" }, 218 { AM4_DSS_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk" },
178 { AM4_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" }, 219 { 0 },
179 { AM4_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" }, 220};
180 { AM4_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" }, 221
181 { AM4_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" }, 222static const struct omap_clkctrl_reg_data am4_cpsw_125mhz_clkctrl_regs[] __initconst = {
182 { AM4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, 223 { AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
183 { AM4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
184 { AM4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
185 { AM4_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
186 { AM4_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
187 { AM4_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
188 { AM4_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
189 { AM4_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck", "emif_clkdm" },
190 { AM4_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk", "dss_clkdm" },
191 { AM4_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
192 { 0 }, 224 { 0 },
193}; 225};
194 226
195const struct omap_clkctrl_data am4_clkctrl_data[] __initconst = { 227const struct omap_clkctrl_data am4_clkctrl_data[] __initconst = {
196 { 0x44df2820, am4_l4_wkup_clkctrl_regs }, 228 { 0x44df2920, am4_l3s_tsc_clkctrl_regs },
229 { 0x44df2a28, am4_l4_wkup_aon_clkctrl_regs },
230 { 0x44df2a20, am4_l4_wkup_clkctrl_regs },
197 { 0x44df8320, am4_mpu_clkctrl_regs }, 231 { 0x44df8320, am4_mpu_clkctrl_regs },
198 { 0x44df8420, am4_gfx_l3_clkctrl_regs }, 232 { 0x44df8420, am4_gfx_l3_clkctrl_regs },
199 { 0x44df8520, am4_l4_rtc_clkctrl_regs }, 233 { 0x44df8520, am4_l4_rtc_clkctrl_regs },
200 { 0x44df8820, am4_l4_per_clkctrl_regs }, 234 { 0x44df8820, am4_l3_clkctrl_regs },
235 { 0x44df8868, am4_l3s_clkctrl_regs },
236 { 0x44df8b20, am4_pruss_ocp_clkctrl_regs },
237 { 0x44df8c20, am4_l4ls_clkctrl_regs },
238 { 0x44df8f20, am4_emif_clkctrl_regs },
239 { 0x44df9220, am4_dss_clkctrl_regs },
240 { 0x44df9320, am4_cpsw_125mhz_clkctrl_regs },
201 { 0 }, 241 { 0 },
202}; 242};
203 243
204const struct omap_clkctrl_data am438x_clkctrl_data[] __initconst = { 244const struct omap_clkctrl_data am438x_clkctrl_data[] __initconst = {
205 { 0x44df2820, am4_l4_wkup_clkctrl_regs }, 245 { 0x44df2920, am4_l3s_tsc_clkctrl_regs },
246 { 0x44df2a28, am4_l4_wkup_aon_clkctrl_regs },
247 { 0x44df2a20, am4_l4_wkup_clkctrl_regs },
206 { 0x44df8320, am4_mpu_clkctrl_regs }, 248 { 0x44df8320, am4_mpu_clkctrl_regs },
207 { 0x44df8420, am4_gfx_l3_clkctrl_regs }, 249 { 0x44df8420, am4_gfx_l3_clkctrl_regs },
208 { 0x44df8820, am4_l4_per_clkctrl_regs }, 250 { 0x44df8820, am4_l3_clkctrl_regs },
251 { 0x44df8868, am4_l3s_clkctrl_regs },
252 { 0x44df8b20, am4_pruss_ocp_clkctrl_regs },
253 { 0x44df8c20, am4_l4ls_clkctrl_regs },
254 { 0x44df8f20, am4_emif_clkctrl_regs },
255 { 0x44df9220, am4_dss_clkctrl_regs },
256 { 0x44df9320, am4_cpsw_125mhz_clkctrl_regs },
209 { 0 }, 257 { 0 },
210}; 258};
211 259
212static struct ti_dt_clk am43xx_clks[] = { 260static struct ti_dt_clk am43xx_clks[] = {
213 DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"), 261 DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
214 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), 262 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
215 DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0348:8"), 263 DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0148:8"),
216 DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0458:8"), 264 DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0058:8"),
217 DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0460:8"), 265 DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0060:8"),
218 DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0468:8"), 266 DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:0068:8"),
219 DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0470:8"), 267 DT_CLK(NULL, "gpio4_dbclk", "l4ls-clkctrl:0070:8"),
220 DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0478:8"), 268 DT_CLK(NULL, "gpio5_dbclk", "l4ls-clkctrl:0078:8"),
221 DT_CLK(NULL, "synctimer_32kclk", "l4_wkup_cm:0210:8"), 269 DT_CLK(NULL, "synctimer_32kclk", "l4-wkup-aon-clkctrl:0008:8"),
222 DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l4_per_cm:0240:8"), 270 DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l3s-clkctrl:01f8:8"),
223 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l4_per_cm:0248:8"), 271 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3s-clkctrl:0200:8"),
224 { .node_name = NULL }, 272 { .node_name = NULL },
225}; 273};
226 274
@@ -228,7 +276,10 @@ int __init am43xx_dt_clk_init(void)
228{ 276{
229 struct clk *clk1, *clk2; 277 struct clk *clk1, *clk2;
230 278
231 ti_dt_clocks_register(am43xx_clks); 279 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
280 ti_dt_clocks_register(am43xx_compat_clks);
281 else
282 ti_dt_clocks_register(am43xx_clks);
232 283
233 omap2_clk_disable_autoidle_all(); 284 omap2_clk_disable_autoidle_all();
234 285
diff --git a/drivers/clk/ti/clk-7xx-compat.c b/drivers/clk/ti/clk-7xx-compat.c
new file mode 100644
index 000000000000..e3cb7f0b03ae
--- /dev/null
+++ b/drivers/clk/ti/clk-7xx-compat.c
@@ -0,0 +1,823 @@
1/*
2 * DRA7 Clock init
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * Tero Kristo (t-kristo@ti.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/list.h>
15#include <linux/clk.h>
16#include <linux/clkdev.h>
17#include <linux/clk/ti.h>
18#include <dt-bindings/clock/dra7.h>
19
20#include "clock.h"
21
22#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
23#define DRA7_DPLL_USB_DEFFREQ 960000000
24
25static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
26 { DRA7_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
27 { 0 },
28};
29
30static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
31 "per_abe_x1_gfclk2_div",
32 "video1_clk2_div",
33 "video2_clk2_div",
34 "hdmi_clk2_div",
35 NULL,
36};
37
38static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
39 "abe_24m_fclk",
40 "abe_sys_clk_div",
41 "func_24m_clk",
42 "atl_clkin3_ck",
43 "atl_clkin2_ck",
44 "atl_clkin1_ck",
45 "atl_clkin0_ck",
46 "sys_clkin2",
47 "ref_clkin0_ck",
48 "ref_clkin1_ck",
49 "ref_clkin2_ck",
50 "ref_clkin3_ck",
51 "mlb_clk",
52 "mlbp_clk",
53 NULL,
54};
55
56static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
57 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
58 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
59 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
60 { 0 },
61};
62
63static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
64 "timer_sys_clk_div",
65 "sys_32k_ck",
66 "sys_clkin2",
67 "ref_clkin0_ck",
68 "ref_clkin1_ck",
69 "ref_clkin2_ck",
70 "ref_clkin3_ck",
71 "abe_giclk_div",
72 "video1_div_clk",
73 "video2_div_clk",
74 "hdmi_div_clk",
75 "clkoutmux0_clk_mux",
76 NULL,
77};
78
79static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
80 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
81 { 0 },
82};
83
84static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
85 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
86 { 0 },
87};
88
89static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
90 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
91 { 0 },
92};
93
94static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
95 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
96 { 0 },
97};
98
99static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
100 "func_48m_fclk",
101 "dpll_per_m2x2_ck",
102 NULL,
103};
104
105static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
106 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
107 { 0 },
108};
109
110static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
111 { DRA7_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0010:22" },
112 { DRA7_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0018:24" },
113 { DRA7_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0020:24" },
114 { DRA7_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0028:24" },
115 { DRA7_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0030:24" },
116 { DRA7_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
117 { DRA7_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0040:24" },
118 { 0 },
119};
120
121static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
122 { DRA7_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
123 { 0 },
124};
125
126static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
127 { DRA7_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
128 { DRA7_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
129 { 0 },
130};
131
132static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
133 { DRA7_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
134 { DRA7_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
135 { DRA7_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
136 { DRA7_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
137 { DRA7_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
138 { DRA7_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
139 { DRA7_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
140 { 0 },
141};
142
143static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
144 { DRA7_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
145 { 0 },
146};
147
148static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
149 { DRA7_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
150 { 0 },
151};
152
153static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
154 "sys_32k_ck",
155 "video1_clkin_ck",
156 "video2_clkin_ck",
157 "hdmi_clkin_ck",
158 NULL,
159};
160
161static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
162 "l3_iclk_div",
163 "dpll_abe_m2_ck",
164 "atl_cm:clk:0000:24",
165 NULL,
166};
167
168static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
169 { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
170 { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
171 { 0 },
172};
173
174static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
175 { DRA7_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl_cm:clk:0000:26" },
176 { 0 },
177};
178
179static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
180 { DRA7_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
181 { DRA7_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
182 { DRA7_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
183 { DRA7_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
184 { DRA7_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
185 { DRA7_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
186 { DRA7_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
187 { DRA7_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
188 { DRA7_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
189 { DRA7_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
190 { DRA7_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
191 { DRA7_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
192 { DRA7_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
193 { DRA7_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
194 { DRA7_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
195 { 0 },
196};
197
198static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
199 { DRA7_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
200 { DRA7_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
201 { 0 },
202};
203
204static const char * const dra7_dss_dss_clk_parents[] __initconst = {
205 "dpll_per_h12x2_ck",
206 NULL,
207};
208
209static const char * const dra7_dss_48mhz_clk_parents[] __initconst = {
210 "func_48m_fclk",
211 NULL,
212};
213
214static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {
215 "hdmi_dpll_clk_mux",
216 NULL,
217};
218
219static const char * const dra7_dss_32khz_clk_parents[] __initconst = {
220 "sys_32k_ck",
221 NULL,
222};
223
224static const char * const dra7_dss_video1_clk_parents[] __initconst = {
225 "video1_dpll_clk_mux",
226 NULL,
227};
228
229static const char * const dra7_dss_video2_clk_parents[] __initconst = {
230 "video2_dpll_clk_mux",
231 NULL,
232};
233
234static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = {
235 { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
236 { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
237 { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
238 { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
239 { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
240 { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
241 { 0 },
242};
243
244static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
245 { DRA7_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
246 { DRA7_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
247 { 0 },
248};
249
250static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
251 "func_128m_clk",
252 "dpll_per_m2x2_ck",
253 NULL,
254};
255
256static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
257 "l3init_cm:clk:0008:24",
258 NULL,
259};
260
261static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = {
262 .max_div = 4,
263 .flags = CLK_DIVIDER_POWER_OF_TWO,
264};
265
266static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
267 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
268 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
269 { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data },
270 { 0 },
271};
272
273static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
274 "l3init_cm:clk:0010:24",
275 NULL,
276};
277
278static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = {
279 .max_div = 4,
280 .flags = CLK_DIVIDER_POWER_OF_TWO,
281};
282
283static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = {
284 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
285 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
286 { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data },
287 { 0 },
288};
289
290static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = {
291 "l3init_960m_gfclk",
292 NULL,
293};
294
295static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = {
296 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
297 { 0 },
298};
299
300static const char * const dra7_sata_ref_clk_parents[] __initconst = {
301 "sys_clkin1",
302 NULL,
303};
304
305static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
306 { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
307 { 0 },
308};
309
310static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
311 "apll_pcie_ck",
312 NULL,
313};
314
315static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = {
316 "optfclk_pciephy_div",
317 NULL,
318};
319
320static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = {
321 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
322 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
323 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
324 { 0 },
325};
326
327static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
328 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
329 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
330 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
331 { 0 },
332};
333
334static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
335 "dpll_gmac_h11x2_ck",
336 "rmii_clk_ck",
337 NULL,
338};
339
340static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = {
341 "video1_clkin_ck",
342 "video2_clkin_ck",
343 "dpll_abe_m2_ck",
344 "hdmi_clkin_ck",
345 "l3_iclk_div",
346 NULL,
347};
348
349static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
350 { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
351 { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
352 { 0 },
353};
354
355static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
356 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
357 { 0 },
358};
359
360static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
361 { DRA7_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
362 { DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
363 { DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
364 { DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
365 { DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
366 { DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
367 { DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
368 { DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
369 { DRA7_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck", "gmac_clkdm" },
370 { DRA7_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
371 { DRA7_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
372 { DRA7_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
373 { 0 },
374};
375
376static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = {
377 "timer_sys_clk_div",
378 "sys_32k_ck",
379 "sys_clkin2",
380 "ref_clkin0_ck",
381 "ref_clkin1_ck",
382 "ref_clkin2_ck",
383 "ref_clkin3_ck",
384 "abe_giclk_div",
385 "video1_div_clk",
386 "video2_div_clk",
387 "hdmi_div_clk",
388 NULL,
389};
390
391static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = {
392 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
393 { 0 },
394};
395
396static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = {
397 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
398 { 0 },
399};
400
401static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = {
402 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
403 { 0 },
404};
405
406static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = {
407 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
408 { 0 },
409};
410
411static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = {
412 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
413 { 0 },
414};
415
416static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = {
417 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
418 { 0 },
419};
420
421static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = {
422 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
423 { 0 },
424};
425
426static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = {
427 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
428 { 0 },
429};
430
431static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = {
432 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
433 { 0 },
434};
435
436static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = {
437 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
438 { 0 },
439};
440
441static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
442 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
443 { 0 },
444};
445
446static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
447 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
448 { 0 },
449};
450
451static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
452 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
453 { 0 },
454};
455
456static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
457 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
458 { 0 },
459};
460
461static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
462 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
463 { 0 },
464};
465
466static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
467 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
468 { 0 },
469};
470
471static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
472 "l4per_cm:clk:0120:24",
473 NULL,
474};
475
476static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = {
477 .max_div = 4,
478 .flags = CLK_DIVIDER_POWER_OF_TWO,
479};
480
481static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
482 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
483 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
484 { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data },
485 { 0 },
486};
487
488static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
489 "l4per_cm:clk:0128:24",
490 NULL,
491};
492
493static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = {
494 .max_div = 4,
495 .flags = CLK_DIVIDER_POWER_OF_TWO,
496};
497
498static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
499 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
500 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
501 { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data },
502 { 0 },
503};
504
505static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
506 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
507 { 0 },
508};
509
510static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
511 "func_128m_clk",
512 "dpll_per_h13x2_ck",
513 NULL,
514};
515
516static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
517 "l4per_cm:clk:0138:24",
518 NULL,
519};
520
521static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
522 .max_div = 4,
523 .flags = CLK_DIVIDER_POWER_OF_TWO,
524};
525
526static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
527 { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
528 { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
529 { 0 },
530};
531
532static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
533 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
534 { 0 },
535};
536
537static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
538 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
539 { 0 },
540};
541
542static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
543 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
544 { 0 },
545};
546
547static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
548 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
549 { 0 },
550};
551
552static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
553 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
554 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
555 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
556 { 0 },
557};
558
559static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
560 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
561 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
562 { 0 },
563};
564
565static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
566 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
567 { 0 },
568};
569
570static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
571 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
572 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
573 { 0 },
574};
575
576static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = {
577 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
578 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
579 { 0 },
580};
581
582static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = {
583 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
584 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
585 { 0 },
586};
587
588static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = {
589 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
590 { 0 },
591};
592
593static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = {
594 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
595 { 0 },
596};
597
598static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = {
599 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
600 { 0 },
601};
602
603static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = {
604 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
605 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
606 { 0 },
607};
608
609static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
610 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
611 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
612 { 0 },
613};
614
615static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
616 { DRA7_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per2_clkdm" },
617 { DRA7_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per3_clkdm" },
618 { DRA7_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
619 { DRA7_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
620 { DRA7_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0038:24" },
621 { DRA7_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0040:24" },
622 { DRA7_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0048:24" },
623 { DRA7_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0050:24" },
624 { DRA7_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
625 { DRA7_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
626 { DRA7_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
627 { DRA7_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
628 { DRA7_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
629 { DRA7_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
630 { DRA7_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
631 { DRA7_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
632 { DRA7_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
633 { DRA7_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
634 { DRA7_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
635 { DRA7_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
636 { DRA7_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
637 { DRA7_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
638 { DRA7_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
639 { DRA7_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00c8:24", "l4per3_clkdm" },
640 { DRA7_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d0:24", "l4per3_clkdm" },
641 { DRA7_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d8:24", "l4per3_clkdm" },
642 { DRA7_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
643 { DRA7_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
644 { DRA7_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
645 { DRA7_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
646 { DRA7_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
647 { DRA7_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
648 { DRA7_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0120:25" },
649 { DRA7_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0128:25" },
650 { DRA7_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0130:24", "l4per3_clkdm" },
651 { DRA7_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0138:25", "l4per2_clkdm" },
652 { DRA7_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0140:24" },
653 { DRA7_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0148:24" },
654 { DRA7_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0150:24" },
655 { DRA7_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0158:24" },
656 { DRA7_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0160:22", "l4per2_clkdm" },
657 { DRA7_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0168:22", "l4per2_clkdm" },
658 { DRA7_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0170:24" },
659 { DRA7_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0178:22", "l4per2_clkdm" },
660 { DRA7_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0190:24", "l4per2_clkdm" },
661 { DRA7_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0198:22", "l4per2_clkdm" },
662 { DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
663 { DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
664 { DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
665 { DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
666 { DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
667 { DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" },
668 { DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" },
669 { DRA7_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e8:24", "l4per2_clkdm" },
670 { DRA7_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1", "l4per2_clkdm" },
671 { DRA7_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0204:22", "l4per2_clkdm" },
672 { DRA7_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0208:22", "l4per2_clkdm" },
673 { 0 },
674};
675
676static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = {
677 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
678 { 0 },
679};
680
681static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = {
682 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
683 { 0 },
684};
685
686static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = {
687 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
688 { 0 },
689};
690
691static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = {
692 "sys_clkin1",
693 "sys_clkin2",
694 NULL,
695};
696
697static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
698 { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
699 { 0 },
700};
701
702static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
703 { DRA7_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
704 { DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
705 { DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
706 { DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
707 { DRA7_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" },
708 { DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
709 { DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" },
710 { DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" },
711 { DRA7_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk"},
712 { 0 },
713};
714
715const struct omap_clkctrl_data dra7_clkctrl_compat_data[] __initconst = {
716 { 0x4a005320, dra7_mpu_clkctrl_regs },
717 { 0x4a005540, dra7_ipu_clkctrl_regs },
718 { 0x4a005740, dra7_rtc_clkctrl_regs },
719 { 0x4a008620, dra7_coreaon_clkctrl_regs },
720 { 0x4a008720, dra7_l3main1_clkctrl_regs },
721 { 0x4a008a20, dra7_dma_clkctrl_regs },
722 { 0x4a008b20, dra7_emif_clkctrl_regs },
723 { 0x4a008c00, dra7_atl_clkctrl_regs },
724 { 0x4a008d20, dra7_l4cfg_clkctrl_regs },
725 { 0x4a008e20, dra7_l3instr_clkctrl_regs },
726 { 0x4a009120, dra7_dss_clkctrl_regs },
727 { 0x4a009320, dra7_l3init_clkctrl_regs },
728 { 0x4a009700, dra7_l4per_clkctrl_regs },
729 { 0x4ae07820, dra7_wkupaon_clkctrl_regs },
730 { 0 },
731};
732
733struct ti_dt_clk dra7xx_compat_clks[] = {
734 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
735 DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
736 DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
737 DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"),
738 DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"),
739 DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"),
740 DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
741 DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
742 DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
743 DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"),
744 DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"),
745 DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"),
746 DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"),
747 DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
748 DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"),
749 DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"),
750 DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0070:8"),
751 DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0078:8"),
752 DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0080:8"),
753 DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:0110:8"),
754 DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:0118:8"),
755 DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu_cm:0010:28"),
756 DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"),
757 DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu_cm:0010:22"),
758 DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per_cm:0160:28"),
759 DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"),
760 DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per_cm:0160:22"),
761 DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"),
762 DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per_cm:0168:22"),
763 DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"),
764 DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per_cm:0198:22"),
765 DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"),
766 DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per_cm:0178:22"),
767 DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"),
768 DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per_cm:0204:22"),
769 DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"),
770 DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per_cm:0208:22"),
771 DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per_cm:0190:22"),
772 DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"),
773 DT_CLK(NULL, "mmc1_clk32k", "l3init_cm:0008:8"),
774 DT_CLK(NULL, "mmc1_fclk_div", "l3init_cm:0008:25"),
775 DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
776 DT_CLK(NULL, "mmc2_clk32k", "l3init_cm:0010:8"),
777 DT_CLK(NULL, "mmc2_fclk_div", "l3init_cm:0010:25"),
778 DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
779 DT_CLK(NULL, "mmc3_clk32k", "l4per_cm:0120:8"),
780 DT_CLK(NULL, "mmc3_gfclk_div", "l4per_cm:0120:25"),
781 DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"),
782 DT_CLK(NULL, "mmc4_clk32k", "l4per_cm:0128:8"),
783 DT_CLK(NULL, "mmc4_gfclk_div", "l4per_cm:0128:25"),
784 DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"),
785 DT_CLK(NULL, "optfclk_pciephy1_32khz", "l3init_cm:0090:8"),
786 DT_CLK(NULL, "optfclk_pciephy1_clk", "l3init_cm:0090:9"),
787 DT_CLK(NULL, "optfclk_pciephy1_div_clk", "l3init_cm:0090:10"),
788 DT_CLK(NULL, "optfclk_pciephy2_32khz", "l3init_cm:0098:8"),
789 DT_CLK(NULL, "optfclk_pciephy2_clk", "l3init_cm:0098:9"),
790 DT_CLK(NULL, "optfclk_pciephy2_div_clk", "l3init_cm:0098:10"),
791 DT_CLK(NULL, "qspi_gfclk_div", "l4per_cm:0138:25"),
792 DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"),
793 DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"),
794 DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
795 DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"),
796 DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"),
797 DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"),
798 DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"),
799 DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"),
800 DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"),
801 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
802 DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"),
803 DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"),
804 DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"),
805 DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"),
806 DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"),
807 DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"),
808 DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"),
809 DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"),
810 DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"),
811 DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"),
812 DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"),
813 DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"),
814 DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"),
815 DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"),
816 DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"),
817 DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"),
818 DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"),
819 DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"),
820 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init_cm:00d0:8"),
821 DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init_cm:0020:8"),
822 { .node_name = NULL },
823};
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index 71a122b2dc67..597fb4a59318 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -23,7 +23,28 @@
23#define DRA7_DPLL_USB_DEFFREQ 960000000 23#define DRA7_DPLL_USB_DEFFREQ 960000000
24 24
25static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = { 25static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
26 { DRA7_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" }, 26 { DRA7_MPU_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
27 { 0 },
28};
29
30static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = {
31 { DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_dsp_m2_ck" },
32 { 0 },
33};
34
35static const char * const dra7_ipu1_gfclk_mux_parents[] __initconst = {
36 "dpll_abe_m2x2_ck",
37 "dpll_core_h22x2_ck",
38 NULL,
39};
40
41static const struct omap_clkctrl_bit_data dra7_mmu_ipu1_bit_data[] __initconst = {
42 { 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL },
43 { 0 },
44};
45
46static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = {
47 { DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP, "ipu1-clkctrl:0000:24" },
27 { 0 }, 48 { 0 },
28}; 49};
29 50
@@ -108,45 +129,55 @@ static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
108}; 129};
109 130
110static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = { 131static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
111 { DRA7_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0010:22" }, 132 { DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0000:22" },
112 { DRA7_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0018:24" }, 133 { DRA7_IPU_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0008:24" },
113 { DRA7_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0020:24" }, 134 { DRA7_IPU_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0010:24" },
114 { DRA7_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0028:24" }, 135 { DRA7_IPU_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0018:24" },
115 { DRA7_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0030:24" }, 136 { DRA7_IPU_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0020:24" },
116 { DRA7_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 137 { DRA7_IPU_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
117 { DRA7_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0040:24" }, 138 { DRA7_IPU_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0030:24" },
139 { 0 },
140};
141
142static const struct omap_clkctrl_reg_data dra7_dsp2_clkctrl_regs[] __initconst = {
143 { DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_dsp_m2_ck" },
118 { 0 }, 144 { 0 },
119}; 145};
120 146
121static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = { 147static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
122 { DRA7_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 148 { DRA7_RTC_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
123 { 0 }, 149 { 0 },
124}; 150};
125 151
126static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = { 152static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
127 { DRA7_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" }, 153 { DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
128 { DRA7_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" }, 154 { DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
129 { 0 }, 155 { 0 },
130}; 156};
131 157
132static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = { 158static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
133 { DRA7_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 159 { DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
134 { DRA7_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 160 { DRA7_L3MAIN1_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
135 { DRA7_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" }, 161 { DRA7_L3MAIN1_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
136 { DRA7_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 162 { DRA7_L3MAIN1_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
137 { DRA7_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 163 { DRA7_L3MAIN1_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
138 { DRA7_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 164 { DRA7_L3MAIN1_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
139 { DRA7_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" }, 165 { DRA7_L3MAIN1_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
166 { 0 },
167};
168
169static const struct omap_clkctrl_reg_data dra7_ipu2_clkctrl_regs[] __initconst = {
170 { DRA7_IPU2_MMU_IPU2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h22x2_ck" },
140 { 0 }, 171 { 0 },
141}; 172};
142 173
143static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = { 174static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
144 { DRA7_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 175 { DRA7_DMA_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
145 { 0 }, 176 { 0 },
146}; 177};
147 178
148static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = { 179static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
149 { DRA7_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 180 { DRA7_EMIF_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
150 { 0 }, 181 { 0 },
151}; 182};
152 183
@@ -161,7 +192,7 @@ static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
161static const char * const dra7_atl_gfclk_mux_parents[] __initconst = { 192static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
162 "l3_iclk_div", 193 "l3_iclk_div",
163 "dpll_abe_m2_ck", 194 "dpll_abe_m2_ck",
164 "atl_cm:clk:0000:24", 195 "atl-clkctrl:0000:24",
165 NULL, 196 NULL,
166}; 197};
167 198
@@ -172,32 +203,32 @@ static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
172}; 203};
173 204
174static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = { 205static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
175 { DRA7_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl_cm:clk:0000:26" }, 206 { DRA7_ATL_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl-clkctrl:0000:26" },
176 { 0 }, 207 { 0 },
177}; 208};
178 209
179static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = { 210static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
180 { DRA7_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" }, 211 { DRA7_L4CFG_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
181 { DRA7_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" }, 212 { DRA7_L4CFG_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
182 { DRA7_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 213 { DRA7_L4CFG_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
183 { DRA7_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" }, 214 { DRA7_L4CFG_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
184 { DRA7_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" }, 215 { DRA7_L4CFG_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
185 { DRA7_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" }, 216 { DRA7_L4CFG_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
186 { DRA7_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" }, 217 { DRA7_L4CFG_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
187 { DRA7_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" }, 218 { DRA7_L4CFG_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
188 { DRA7_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" }, 219 { DRA7_L4CFG_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
189 { DRA7_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" }, 220 { DRA7_L4CFG_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
190 { DRA7_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" }, 221 { DRA7_L4CFG_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
191 { DRA7_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" }, 222 { DRA7_L4CFG_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
192 { DRA7_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" }, 223 { DRA7_L4CFG_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
193 { DRA7_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" }, 224 { DRA7_L4CFG_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
194 { DRA7_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" }, 225 { DRA7_L4CFG_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
195 { 0 }, 226 { 0 },
196}; 227};
197 228
198static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = { 229static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
199 { DRA7_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 230 { DRA7_L3INSTR_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
200 { DRA7_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 231 { DRA7_L3INSTR_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
201 { 0 }, 232 { 0 },
202}; 233};
203 234
@@ -242,8 +273,8 @@ static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst =
242}; 273};
243 274
244static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = { 275static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
245 { DRA7_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" }, 276 { DRA7_DSS_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
246 { DRA7_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" }, 277 { DRA7_DSS_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
247 { 0 }, 278 { 0 },
248}; 279};
249 280
@@ -254,7 +285,7 @@ static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
254}; 285};
255 286
256static const char * const dra7_mmc1_fclk_div_parents[] __initconst = { 287static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
257 "l3init_cm:clk:0008:24", 288 "l3init-clkctrl:0008:24",
258 NULL, 289 NULL,
259}; 290};
260 291
@@ -271,7 +302,7 @@ static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
271}; 302};
272 303
273static const char * const dra7_mmc2_fclk_div_parents[] __initconst = { 304static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
274 "l3init_cm:clk:0010:24", 305 "l3init-clkctrl:0010:24",
275 NULL, 306 NULL,
276}; 307};
277 308
@@ -307,6 +338,24 @@ static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
307 { 0 }, 338 { 0 },
308}; 339};
309 340
341static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
342 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
343 { 0 },
344};
345
346static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
347 { DRA7_L3INIT_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" },
348 { DRA7_L3INIT_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
349 { DRA7_L3INIT_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
350 { DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
351 { DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
352 { DRA7_L3INIT_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
353 { DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
354 { DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
355 { DRA7_L3INIT_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
356 { 0 },
357};
358
310static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = { 359static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
311 "apll_pcie_ck", 360 "apll_pcie_ck",
312 NULL, 361 NULL,
@@ -331,6 +380,12 @@ static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
331 { 0 }, 380 { 0 },
332}; 381};
333 382
383static const struct omap_clkctrl_reg_data dra7_pcie_clkctrl_regs[] __initconst = {
384 { DRA7_PCIE_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },
385 { DRA7_PCIE_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },
386 { 0 },
387};
388
334static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = { 389static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
335 "dpll_gmac_h11x2_ck", 390 "dpll_gmac_h11x2_ck",
336 "rmii_clk_ck", 391 "rmii_clk_ck",
@@ -352,24 +407,8 @@ static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
352 { 0 }, 407 { 0 },
353}; 408};
354 409
355static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = { 410static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = {
356 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL }, 411 { DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck" },
357 { 0 },
358};
359
360static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
361 { DRA7_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
362 { DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
363 { DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
364 { DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
365 { DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
366 { DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
367 { DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
368 { DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
369 { DRA7_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck", "gmac_clkdm" },
370 { DRA7_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
371 { DRA7_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
372 { DRA7_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
373 { 0 }, 412 { 0 },
374}; 413};
375 414
@@ -443,21 +482,6 @@ static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
443 { 0 }, 482 { 0 },
444}; 483};
445 484
446static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
447 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
448 { 0 },
449};
450
451static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
452 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
453 { 0 },
454};
455
456static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
457 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
458 { 0 },
459};
460
461static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = { 485static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
462 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 486 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
463 { 0 }, 487 { 0 },
@@ -469,7 +493,7 @@ static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
469}; 493};
470 494
471static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = { 495static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
472 "l4per_cm:clk:0120:24", 496 "l4per-clkctrl:00f8:24",
473 NULL, 497 NULL,
474}; 498};
475 499
@@ -486,7 +510,7 @@ static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
486}; 510};
487 511
488static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = { 512static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
489 "l4per_cm:clk:0128:24", 513 "l4per-clkctrl:0100:24",
490 NULL, 514 NULL,
491}; 515};
492 516
@@ -502,8 +526,72 @@ static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
502 { 0 }, 526 { 0 },
503}; 527};
504 528
505static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = { 529static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
506 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 530 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
531 { 0 },
532};
533
534static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
535 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
536 { 0 },
537};
538
539static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
540 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
541 { 0 },
542};
543
544static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
545 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
546 { 0 },
547};
548
549static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
550 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
551 { 0 },
552};
553
554static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
555 { DRA7_L4PER_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0000:24" },
556 { DRA7_L4PER_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
557 { DRA7_L4PER_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
558 { DRA7_L4PER_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
559 { DRA7_L4PER_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
560 { DRA7_L4PER_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
561 { DRA7_L4PER_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
562 { DRA7_L4PER_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
563 { DRA7_L4PER_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
564 { DRA7_L4PER_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
565 { DRA7_L4PER_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
566 { DRA7_L4PER_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
567 { DRA7_L4PER_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
568 { DRA7_L4PER_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
569 { DRA7_L4PER_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
570 { DRA7_L4PER_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
571 { DRA7_L4PER_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
572 { DRA7_L4PER_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
573 { DRA7_L4PER_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
574 { DRA7_L4PER_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
575 { DRA7_L4PER_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
576 { DRA7_L4PER_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
577 { DRA7_L4PER_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
578 { DRA7_L4PER_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
579 { DRA7_L4PER_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:00f8:25" },
580 { DRA7_L4PER_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0100:25" },
581 { DRA7_L4PER_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0118:24" },
582 { DRA7_L4PER_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0120:24" },
583 { DRA7_L4PER_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0128:24" },
584 { DRA7_L4PER_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0130:24" },
585 { DRA7_L4PER_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0148:24" },
586 { 0 },
587};
588
589static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst = {
590 { DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
591 { DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
592 { DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
593 { DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "" },
594 { DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
507 { 0 }, 595 { 0 },
508}; 596};
509 597
@@ -514,7 +602,7 @@ static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
514}; 602};
515 603
516static const char * const dra7_qspi_gfclk_div_parents[] __initconst = { 604static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
517 "l4per_cm:clk:0138:24", 605 "l4per2-clkctrl:012c:24",
518 NULL, 606 NULL,
519}; 607};
520 608
@@ -529,26 +617,6 @@ static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
529 { 0 }, 617 { 0 },
530}; 618};
531 619
532static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
533 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
534 { 0 },
535};
536
537static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
538 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
539 { 0 },
540};
541
542static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
543 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
544 { 0 },
545};
546
547static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
548 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
549 { 0 },
550};
551
552static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = { 620static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
553 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 621 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
554 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 622 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
@@ -562,11 +630,6 @@ static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
562 { 0 }, 630 { 0 },
563}; 631};
564 632
565static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
566 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
567 { 0 },
568};
569
570static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = { 633static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
571 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 634 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
572 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 635 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
@@ -612,64 +675,54 @@ static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
612 { 0 }, 675 { 0 },
613}; 676};
614 677
615static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = { 678static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst = {
616 { DRA7_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per2_clkdm" }, 679 { DRA7_L4PER2_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div" },
617 { DRA7_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per3_clkdm" }, 680 { DRA7_L4PER2_PRUSS1_CLKCTRL, NULL, CLKF_SW_SUP, "" },
618 { DRA7_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" }, 681 { DRA7_L4PER2_PRUSS2_CLKCTRL, NULL, CLKF_SW_SUP, "" },
619 { DRA7_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" }, 682 { DRA7_L4PER2_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
620 { DRA7_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0038:24" }, 683 { DRA7_L4PER2_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
621 { DRA7_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0040:24" }, 684 { DRA7_L4PER2_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
622 { DRA7_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0048:24" }, 685 { DRA7_L4PER2_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:012c:25" },
623 { DRA7_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0050:24" }, 686 { DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" },
624 { DRA7_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 687 { DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" },
625 { DRA7_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 688 { DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" },
626 { DRA7_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 689 { DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:24" },
627 { DRA7_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 690 { DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" },
628 { DRA7_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 691 { DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" },
629 { DRA7_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 692 { DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" },
630 { DRA7_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" }, 693 { DRA7_L4PER2_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01dc:24" },
631 { DRA7_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" }, 694 { DRA7_L4PER2_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1" },
632 { DRA7_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" }, 695 { DRA7_L4PER2_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01f8:22" },
633 { DRA7_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 696 { DRA7_L4PER2_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01fc:22" },
634 { DRA7_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 697 { 0 },
635 { DRA7_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 698};
636 { DRA7_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 699
637 { DRA7_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 700static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
638 { DRA7_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" }, 701 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
639 { DRA7_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00c8:24", "l4per3_clkdm" }, 702 { 0 },
640 { DRA7_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d0:24", "l4per3_clkdm" }, 703};
641 { DRA7_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d8:24", "l4per3_clkdm" }, 704
642 { DRA7_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 705static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
643 { DRA7_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 706 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
644 { DRA7_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 707 { 0 },
645 { DRA7_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 708};
646 { DRA7_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 709
647 { DRA7_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 710static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
648 { DRA7_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0120:25" }, 711 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
649 { DRA7_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0128:25" }, 712 { 0 },
650 { DRA7_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0130:24", "l4per3_clkdm" }, 713};
651 { DRA7_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0138:25", "l4per2_clkdm" }, 714
652 { DRA7_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0140:24" }, 715static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
653 { DRA7_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0148:24" }, 716 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
654 { DRA7_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0150:24" }, 717 { 0 },
655 { DRA7_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0158:24" }, 718};
656 { DRA7_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0160:22", "l4per2_clkdm" }, 719
657 { DRA7_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0168:22", "l4per2_clkdm" }, 720static const struct omap_clkctrl_reg_data dra7_l4per3_clkctrl_regs[] __initconst = {
658 { DRA7_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0170:24" }, 721 { DRA7_L4PER3_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div" },
659 { DRA7_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0178:22", "l4per2_clkdm" }, 722 { DRA7_L4PER3_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00b4:24" },
660 { DRA7_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0190:24", "l4per2_clkdm" }, 723 { DRA7_L4PER3_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00bc:24" },
661 { DRA7_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0198:22", "l4per2_clkdm" }, 724 { DRA7_L4PER3_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00c4:24" },
662 { DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" }, 725 { DRA7_L4PER3_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:011c:24" },
663 { DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
664 { DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
665 { DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
666 { DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
667 { DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" },
668 { DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" },
669 { DRA7_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e8:24", "l4per2_clkdm" },
670 { DRA7_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1", "l4per2_clkdm" },
671 { DRA7_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0204:22", "l4per2_clkdm" },
672 { DRA7_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0208:22", "l4per2_clkdm" },
673 { 0 }, 726 { 0 },
674}; 727};
675 728
@@ -700,24 +753,28 @@ static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
700}; 753};
701 754
702static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = { 755static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
703 { DRA7_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 756 { DRA7_WKUPAON_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
704 { DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 757 { DRA7_WKUPAON_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
705 { DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" }, 758 { DRA7_WKUPAON_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
706 { DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" }, 759 { DRA7_WKUPAON_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
707 { DRA7_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" }, 760 { DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" },
708 { DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 761 { DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
709 { DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" }, 762 { DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" },
710 { DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" }, 763 { DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" },
711 { DRA7_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk"}, 764 { DRA7_WKUPAON_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk" },
712 { 0 }, 765 { 0 },
713}; 766};
714 767
715const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = { 768const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
716 { 0x4a005320, dra7_mpu_clkctrl_regs }, 769 { 0x4a005320, dra7_mpu_clkctrl_regs },
717 { 0x4a005540, dra7_ipu_clkctrl_regs }, 770 { 0x4a005420, dra7_dsp1_clkctrl_regs },
718 { 0x4a005740, dra7_rtc_clkctrl_regs }, 771 { 0x4a005520, dra7_ipu1_clkctrl_regs },
772 { 0x4a005550, dra7_ipu_clkctrl_regs },
773 { 0x4a005620, dra7_dsp2_clkctrl_regs },
774 { 0x4a005720, dra7_rtc_clkctrl_regs },
719 { 0x4a008620, dra7_coreaon_clkctrl_regs }, 775 { 0x4a008620, dra7_coreaon_clkctrl_regs },
720 { 0x4a008720, dra7_l3main1_clkctrl_regs }, 776 { 0x4a008720, dra7_l3main1_clkctrl_regs },
777 { 0x4a008920, dra7_ipu2_clkctrl_regs },
721 { 0x4a008a20, dra7_dma_clkctrl_regs }, 778 { 0x4a008a20, dra7_dma_clkctrl_regs },
722 { 0x4a008b20, dra7_emif_clkctrl_regs }, 779 { 0x4a008b20, dra7_emif_clkctrl_regs },
723 { 0x4a008c00, dra7_atl_clkctrl_regs }, 780 { 0x4a008c00, dra7_atl_clkctrl_regs },
@@ -725,7 +782,12 @@ const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
725 { 0x4a008e20, dra7_l3instr_clkctrl_regs }, 782 { 0x4a008e20, dra7_l3instr_clkctrl_regs },
726 { 0x4a009120, dra7_dss_clkctrl_regs }, 783 { 0x4a009120, dra7_dss_clkctrl_regs },
727 { 0x4a009320, dra7_l3init_clkctrl_regs }, 784 { 0x4a009320, dra7_l3init_clkctrl_regs },
728 { 0x4a009700, dra7_l4per_clkctrl_regs }, 785 { 0x4a0093b0, dra7_pcie_clkctrl_regs },
786 { 0x4a0093d0, dra7_gmac_clkctrl_regs },
787 { 0x4a009728, dra7_l4per_clkctrl_regs },
788 { 0x4a0098a0, dra7_l4sec_clkctrl_regs },
789 { 0x4a00970c, dra7_l4per2_clkctrl_regs },
790 { 0x4a009714, dra7_l4per3_clkctrl_regs },
729 { 0x4ae07820, dra7_wkupaon_clkctrl_regs }, 791 { 0x4ae07820, dra7_wkupaon_clkctrl_regs },
730 { 0 }, 792 { 0 },
731}; 793};
@@ -734,91 +796,92 @@ static struct ti_dt_clk dra7xx_clks[] = {
734 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 796 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
735 DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"), 797 DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
736 DT_CLK(NULL, "sys_clkin", "sys_clkin1"), 798 DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
737 DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"), 799 DT_CLK(NULL, "atl_dpll_clk_mux", "atl-clkctrl:0000:24"),
738 DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"), 800 DT_CLK(NULL, "atl_gfclk_mux", "atl-clkctrl:0000:26"),
739 DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"), 801 DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon-clkctrl:0068:24"),
740 DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"), 802 DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
741 DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"), 803 DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
742 DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"), 804 DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
743 DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"), 805 DT_CLK(NULL, "dss_hdmi_clk", "dss-clkctrl:0000:10"),
744 DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"), 806 DT_CLK(NULL, "dss_video1_clk", "dss-clkctrl:0000:12"),
745 DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"), 807 DT_CLK(NULL, "dss_video2_clk", "dss-clkctrl:0000:13"),
746 DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"), 808 DT_CLK(NULL, "gmac_rft_clk_mux", "gmac-clkctrl:0000:25"),
747 DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"), 809 DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
748 DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"), 810 DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0038:8"),
749 DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"), 811 DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0040:8"),
750 DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0070:8"), 812 DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0048:8"),
751 DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0078:8"), 813 DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0050:8"),
752 DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0080:8"), 814 DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0058:8"),
753 DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:0110:8"), 815 DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00e8:8"),
754 DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:0118:8"), 816 DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f0:8"),
755 DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu_cm:0010:28"), 817 DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1-clkctrl:0000:24"),
756 DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"), 818 DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu-clkctrl:0000:28"),
757 DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu_cm:0010:22"), 819 DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu-clkctrl:0000:24"),
758 DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per_cm:0160:28"), 820 DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu-clkctrl:0000:22"),
759 DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"), 821 DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per2-clkctrl:0154:28"),
760 DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per_cm:0160:22"), 822 DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per2-clkctrl:0154:24"),
761 DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"), 823 DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per2-clkctrl:0154:22"),
762 DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per_cm:0168:22"), 824 DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per2-clkctrl:015c:24"),
763 DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"), 825 DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per2-clkctrl:015c:22"),
764 DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per_cm:0198:22"), 826 DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per2-clkctrl:018c:24"),
765 DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"), 827 DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per2-clkctrl:018c:22"),
766 DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per_cm:0178:22"), 828 DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per2-clkctrl:016c:24"),
767 DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"), 829 DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per2-clkctrl:016c:22"),
768 DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per_cm:0204:22"), 830 DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per2-clkctrl:01f8:24"),
769 DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"), 831 DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"),
770 DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per_cm:0208:22"), 832 DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),
771 DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per_cm:0190:22"), 833 DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"),
772 DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"), 834 DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:22"),
773 DT_CLK(NULL, "mmc1_clk32k", "l3init_cm:0008:8"), 835 DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:24"),
774 DT_CLK(NULL, "mmc1_fclk_div", "l3init_cm:0008:25"), 836 DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"),
775 DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"), 837 DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"),
776 DT_CLK(NULL, "mmc2_clk32k", "l3init_cm:0010:8"), 838 DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
777 DT_CLK(NULL, "mmc2_fclk_div", "l3init_cm:0010:25"), 839 DT_CLK(NULL, "mmc2_clk32k", "l3init-clkctrl:0010:8"),
778 DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"), 840 DT_CLK(NULL, "mmc2_fclk_div", "l3init-clkctrl:0010:25"),
779 DT_CLK(NULL, "mmc3_clk32k", "l4per_cm:0120:8"), 841 DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
780 DT_CLK(NULL, "mmc3_gfclk_div", "l4per_cm:0120:25"), 842 DT_CLK(NULL, "mmc3_clk32k", "l4per-clkctrl:00f8:8"),
781 DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"), 843 DT_CLK(NULL, "mmc3_gfclk_div", "l4per-clkctrl:00f8:25"),
782 DT_CLK(NULL, "mmc4_clk32k", "l4per_cm:0128:8"), 844 DT_CLK(NULL, "mmc3_gfclk_mux", "l4per-clkctrl:00f8:24"),
783 DT_CLK(NULL, "mmc4_gfclk_div", "l4per_cm:0128:25"), 845 DT_CLK(NULL, "mmc4_clk32k", "l4per-clkctrl:0100:8"),
784 DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"), 846 DT_CLK(NULL, "mmc4_gfclk_div", "l4per-clkctrl:0100:25"),
785 DT_CLK(NULL, "optfclk_pciephy1_32khz", "l3init_cm:0090:8"), 847 DT_CLK(NULL, "mmc4_gfclk_mux", "l4per-clkctrl:0100:24"),
786 DT_CLK(NULL, "optfclk_pciephy1_clk", "l3init_cm:0090:9"), 848 DT_CLK(NULL, "optfclk_pciephy1_32khz", "pcie-clkctrl:0000:8"),
787 DT_CLK(NULL, "optfclk_pciephy1_div_clk", "l3init_cm:0090:10"), 849 DT_CLK(NULL, "optfclk_pciephy1_clk", "pcie-clkctrl:0000:9"),
788 DT_CLK(NULL, "optfclk_pciephy2_32khz", "l3init_cm:0098:8"), 850 DT_CLK(NULL, "optfclk_pciephy1_div_clk", "pcie-clkctrl:0000:10"),
789 DT_CLK(NULL, "optfclk_pciephy2_clk", "l3init_cm:0098:9"), 851 DT_CLK(NULL, "optfclk_pciephy2_32khz", "pcie-clkctrl:0008:8"),
790 DT_CLK(NULL, "optfclk_pciephy2_div_clk", "l3init_cm:0098:10"), 852 DT_CLK(NULL, "optfclk_pciephy2_clk", "pcie-clkctrl:0008:9"),
791 DT_CLK(NULL, "qspi_gfclk_div", "l4per_cm:0138:25"), 853 DT_CLK(NULL, "optfclk_pciephy2_div_clk", "pcie-clkctrl:0008:10"),
792 DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"), 854 DT_CLK(NULL, "qspi_gfclk_div", "l4per2-clkctrl:012c:25"),
793 DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"), 855 DT_CLK(NULL, "qspi_gfclk_mux", "l4per2-clkctrl:012c:24"),
794 DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"), 856 DT_CLK(NULL, "rmii_50mhz_clk_mux", "gmac-clkctrl:0000:24"),
795 DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"), 857 DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
796 DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"), 858 DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0000:24"),
797 DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"), 859 DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0008:24"),
798 DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"), 860 DT_CLK(NULL, "timer13_gfclk_mux", "l4per3-clkctrl:00b4:24"),
799 DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"), 861 DT_CLK(NULL, "timer14_gfclk_mux", "l4per3-clkctrl:00bc:24"),
800 DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"), 862 DT_CLK(NULL, "timer15_gfclk_mux", "l4per3-clkctrl:00c4:24"),
801 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"), 863 DT_CLK(NULL, "timer16_gfclk_mux", "l4per3-clkctrl:011c:24"),
802 DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"), 864 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
803 DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"), 865 DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0010:24"),
804 DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"), 866 DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0018:24"),
805 DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"), 867 DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0020:24"),
806 DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"), 868 DT_CLK(NULL, "timer5_gfclk_mux", "ipu-clkctrl:0008:24"),
807 DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"), 869 DT_CLK(NULL, "timer6_gfclk_mux", "ipu-clkctrl:0010:24"),
808 DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"), 870 DT_CLK(NULL, "timer7_gfclk_mux", "ipu-clkctrl:0018:24"),
809 DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"), 871 DT_CLK(NULL, "timer8_gfclk_mux", "ipu-clkctrl:0020:24"),
810 DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"), 872 DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0028:24"),
811 DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"), 873 DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon-clkctrl:0060:24"),
812 DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"), 874 DT_CLK(NULL, "uart1_gfclk_mux", "l4per-clkctrl:0118:24"),
813 DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"), 875 DT_CLK(NULL, "uart2_gfclk_mux", "l4per-clkctrl:0120:24"),
814 DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"), 876 DT_CLK(NULL, "uart3_gfclk_mux", "l4per-clkctrl:0128:24"),
815 DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"), 877 DT_CLK(NULL, "uart4_gfclk_mux", "l4per-clkctrl:0130:24"),
816 DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"), 878 DT_CLK(NULL, "uart5_gfclk_mux", "l4per-clkctrl:0148:24"),
817 DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"), 879 DT_CLK(NULL, "uart6_gfclk_mux", "ipu-clkctrl:0030:24"),
818 DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"), 880 DT_CLK(NULL, "uart7_gfclk_mux", "l4per2-clkctrl:01c4:24"),
819 DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"), 881 DT_CLK(NULL, "uart8_gfclk_mux", "l4per2-clkctrl:01d4:24"),
820 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init_cm:00d0:8"), 882 DT_CLK(NULL, "uart9_gfclk_mux", "l4per2-clkctrl:01dc:24"),
821 DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init_cm:0020:8"), 883 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init-clkctrl:00d0:8"),
884 DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init-clkctrl:0020:8"),
822 { .node_name = NULL }, 885 { .node_name = NULL },
823}; 886};
824 887
@@ -827,7 +890,10 @@ int __init dra7xx_dt_clk_init(void)
827 int rc; 890 int rc;
828 struct clk *dpll_ck, *hdcp_ck; 891 struct clk *dpll_ck, *hdcp_ck;
829 892
830 ti_dt_clocks_register(dra7xx_clks); 893 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
894 ti_dt_clocks_register(dra7xx_compat_clks);
895 else
896 ti_dt_clocks_register(dra7xx_clks);
831 897
832 omap2_clk_disable_autoidle_all(); 898 omap2_clk_disable_autoidle_all();
833 899
diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c
index 148815470431..a01ca9395179 100644
--- a/drivers/clk/ti/clk-dra7-atl.c
+++ b/drivers/clk/ti/clk-dra7-atl.c
@@ -190,8 +190,8 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node)
190 init.num_parents = of_clk_get_parent_count(node); 190 init.num_parents = of_clk_get_parent_count(node);
191 191
192 if (init.num_parents != 1) { 192 if (init.num_parents != 1) {
193 pr_err("%s: atl clock %s must have 1 parent\n", __func__, 193 pr_err("%s: atl clock %pOFn must have 1 parent\n", __func__,
194 node->name); 194 node);
195 goto cleanup; 195 goto cleanup;
196 } 196 }
197 197
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index 7d22e1af2247..1c690e57a3f1 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -34,7 +34,7 @@
34struct ti_clk_ll_ops *ti_clk_ll_ops; 34struct ti_clk_ll_ops *ti_clk_ll_ops;
35static struct device_node *clocks_node_ptr[CLK_MAX_MEMMAPS]; 35static struct device_node *clocks_node_ptr[CLK_MAX_MEMMAPS];
36 36
37static struct ti_clk_features ti_clk_features; 37struct ti_clk_features ti_clk_features;
38 38
39struct clk_iomap { 39struct clk_iomap {
40 struct regmap *regmap; 40 struct regmap *regmap;
@@ -129,7 +129,7 @@ int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops)
129void __init ti_dt_clocks_register(struct ti_dt_clk oclks[]) 129void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
130{ 130{
131 struct ti_dt_clk *c; 131 struct ti_dt_clk *c;
132 struct device_node *node; 132 struct device_node *node, *parent;
133 struct clk *clk; 133 struct clk *clk;
134 struct of_phandle_args clkspec; 134 struct of_phandle_args clkspec;
135 char buf[64]; 135 char buf[64];
@@ -140,6 +140,9 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
140 int ret; 140 int ret;
141 static bool clkctrl_nodes_missing; 141 static bool clkctrl_nodes_missing;
142 static bool has_clkctrl_data; 142 static bool has_clkctrl_data;
143 static bool compat_mode;
144
145 compat_mode = ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT;
143 146
144 for (c = oclks; c->node_name != NULL; c++) { 147 for (c = oclks; c->node_name != NULL; c++) {
145 strcpy(buf, c->node_name); 148 strcpy(buf, c->node_name);
@@ -164,8 +167,12 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
164 continue; 167 continue;
165 168
166 node = of_find_node_by_name(NULL, buf); 169 node = of_find_node_by_name(NULL, buf);
167 if (num_args) 170 if (num_args && compat_mode) {
168 node = of_find_node_by_name(node, "clk"); 171 parent = node;
172 node = of_get_child_by_name(parent, "clk");
173 of_node_put(parent);
174 }
175
169 clkspec.np = node; 176 clkspec.np = node;
170 clkspec.args_count = num_args; 177 clkspec.args_count = num_args;
171 for (i = 0; i < num_args; i++) { 178 for (i = 0; i < num_args; i++) {
@@ -173,11 +180,12 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
173 if (ret) { 180 if (ret) {
174 pr_warn("Bad tag in %s at %d: %s\n", 181 pr_warn("Bad tag in %s at %d: %s\n",
175 c->node_name, i, tags[i]); 182 c->node_name, i, tags[i]);
183 of_node_put(node);
176 return; 184 return;
177 } 185 }
178 } 186 }
179 clk = of_clk_get_from_provider(&clkspec); 187 clk = of_clk_get_from_provider(&clkspec);
180 188 of_node_put(node);
181 if (!IS_ERR(clk)) { 189 if (!IS_ERR(clk)) {
182 c->lk.clk = clk; 190 c->lk.clk = clk;
183 clkdev_add(&c->lk); 191 clkdev_add(&c->lk);
@@ -223,7 +231,7 @@ int __init ti_clk_retry_init(struct device_node *node, void *user,
223{ 231{
224 struct clk_init_item *retry; 232 struct clk_init_item *retry;
225 233
226 pr_debug("%s: adding to retry list...\n", node->name); 234 pr_debug("%pOFn: adding to retry list...\n", node);
227 retry = kzalloc(sizeof(*retry), GFP_KERNEL); 235 retry = kzalloc(sizeof(*retry), GFP_KERNEL);
228 if (!retry) 236 if (!retry)
229 return -ENOMEM; 237 return -ENOMEM;
@@ -258,14 +266,14 @@ int ti_clk_get_reg_addr(struct device_node *node, int index,
258 } 266 }
259 267
260 if (i == CLK_MAX_MEMMAPS) { 268 if (i == CLK_MAX_MEMMAPS) {
261 pr_err("clk-provider not found for %s!\n", node->name); 269 pr_err("clk-provider not found for %pOFn!\n", node);
262 return -ENOENT; 270 return -ENOENT;
263 } 271 }
264 272
265 reg->index = i; 273 reg->index = i;
266 274
267 if (of_property_read_u32_index(node, "reg", index, &val)) { 275 if (of_property_read_u32_index(node, "reg", index, &val)) {
268 pr_err("%s must have reg[%d]!\n", node->name, index); 276 pr_err("%pOFn must have reg[%d]!\n", node, index);
269 return -EINVAL; 277 return -EINVAL;
270 } 278 }
271 279
@@ -312,7 +320,7 @@ int __init omap2_clk_provider_init(struct device_node *parent, int index,
312 /* get clocks for this parent */ 320 /* get clocks for this parent */
313 clocks = of_get_child_by_name(parent, "clocks"); 321 clocks = of_get_child_by_name(parent, "clocks");
314 if (!clocks) { 322 if (!clocks) {
315 pr_err("%s missing 'clocks' child node.\n", parent->name); 323 pr_err("%pOFn missing 'clocks' child node.\n", parent);
316 return -EINVAL; 324 return -EINVAL;
317 } 325 }
318 326
@@ -365,7 +373,7 @@ void ti_dt_clk_init_retry_clks(void)
365 373
366 while (!list_empty(&retry_list) && retries) { 374 while (!list_empty(&retry_list) && retries) {
367 list_for_each_entry_safe(retry, tmp, &retry_list, link) { 375 list_for_each_entry_safe(retry, tmp, &retry_list, link) {
368 pr_debug("retry-init: %s\n", retry->node->name); 376 pr_debug("retry-init: %pOFn\n", retry->node);
369 retry->func(retry->user, retry->node); 377 retry->func(retry->user, retry->node);
370 list_del(&retry->link); 378 list_del(&retry->link);
371 kfree(retry); 379 kfree(retry);
diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c
index 421b05392220..469f560ae1cf 100644
--- a/drivers/clk/ti/clkctrl.c
+++ b/drivers/clk/ti/clkctrl.c
@@ -259,8 +259,13 @@ _ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider,
259 struct omap_clkctrl_clk *clkctrl_clk; 259 struct omap_clkctrl_clk *clkctrl_clk;
260 int ret = 0; 260 int ret = 0;
261 261
262 init.name = kasprintf(GFP_KERNEL, "%s:%s:%04x:%d", node->parent->name, 262 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
263 node->name, offset, bit); 263 init.name = kasprintf(GFP_KERNEL, "%pOFn:%pOFn:%04x:%d",
264 node->parent, node, offset,
265 bit);
266 else
267 init.name = kasprintf(GFP_KERNEL, "%pOFn:%04x:%d", node,
268 offset, bit);
264 clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL); 269 clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
265 if (!init.name || !clkctrl_clk) { 270 if (!init.name || !clkctrl_clk) {
266 ret = -ENOMEM; 271 ret = -ENOMEM;
@@ -440,6 +445,11 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
440 const __be32 *addrp; 445 const __be32 *addrp;
441 u32 addr; 446 u32 addr;
442 int ret; 447 int ret;
448 char *c;
449
450 if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) &&
451 !strcmp(node->name, "clk"))
452 ti_clk_features.flags |= TI_CLK_CLKCTRL_COMPAT;
443 453
444 addrp = of_get_address(node, 0, NULL, NULL); 454 addrp = of_get_address(node, 0, NULL, NULL);
445 addr = (u32)of_translate_address(node, addrp); 455 addr = (u32)of_translate_address(node, addrp);
@@ -453,18 +463,35 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
453 data = omap5_clkctrl_data; 463 data = omap5_clkctrl_data;
454#endif 464#endif
455#ifdef CONFIG_SOC_DRA7XX 465#ifdef CONFIG_SOC_DRA7XX
456 if (of_machine_is_compatible("ti,dra7")) 466 if (of_machine_is_compatible("ti,dra7")) {
457 data = dra7_clkctrl_data; 467 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
468 data = dra7_clkctrl_compat_data;
469 else
470 data = dra7_clkctrl_data;
471 }
458#endif 472#endif
459#ifdef CONFIG_SOC_AM33XX 473#ifdef CONFIG_SOC_AM33XX
460 if (of_machine_is_compatible("ti,am33xx")) 474 if (of_machine_is_compatible("ti,am33xx")) {
461 data = am3_clkctrl_data; 475 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
476 data = am3_clkctrl_compat_data;
477 else
478 data = am3_clkctrl_data;
479 }
462#endif 480#endif
463#ifdef CONFIG_SOC_AM43XX 481#ifdef CONFIG_SOC_AM43XX
464 if (of_machine_is_compatible("ti,am4372")) 482 if (of_machine_is_compatible("ti,am4372")) {
465 data = am4_clkctrl_data; 483 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
466 if (of_machine_is_compatible("ti,am438x")) 484 data = am4_clkctrl_compat_data;
467 data = am438x_clkctrl_data; 485 else
486 data = am4_clkctrl_data;
487 }
488
489 if (of_machine_is_compatible("ti,am438x")) {
490 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
491 data = am438x_clkctrl_compat_data;
492 else
493 data = am438x_clkctrl_data;
494 }
468#endif 495#endif
469#ifdef CONFIG_SOC_TI81XX 496#ifdef CONFIG_SOC_TI81XX
470 if (of_machine_is_compatible("ti,dm814")) 497 if (of_machine_is_compatible("ti,dm814"))
@@ -492,21 +519,43 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
492 519
493 provider->base = of_iomap(node, 0); 520 provider->base = of_iomap(node, 0);
494 521
495 provider->clkdm_name = kmalloc(strlen(node->parent->name) + 3, 522 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) {
496 GFP_KERNEL); 523 provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFnxxx", node->parent);
497 if (!provider->clkdm_name) { 524 if (!provider->clkdm_name) {
498 kfree(provider); 525 kfree(provider);
499 return; 526 return;
527 }
528
529 /*
530 * Create default clkdm name, replace _cm from end of parent
531 * node name with _clkdm
532 */
533 provider->clkdm_name[strlen(provider->clkdm_name) - 5] = 0;
534 } else {
535 provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFn", node);
536 if (!provider->clkdm_name) {
537 kfree(provider);
538 return;
539 }
540
541 /*
542 * Create default clkdm name, replace _clkctrl from end of
543 * node name with _clkdm
544 */
545 provider->clkdm_name[strlen(provider->clkdm_name) - 7] = 0;
500 } 546 }
501 547
502 /*
503 * Create default clkdm name, replace _cm from end of parent node
504 * name with _clkdm
505 */
506 strcpy(provider->clkdm_name, node->parent->name);
507 provider->clkdm_name[strlen(provider->clkdm_name) - 2] = 0;
508 strcat(provider->clkdm_name, "clkdm"); 548 strcat(provider->clkdm_name, "clkdm");
509 549
550 /* Replace any dash from the clkdm name with underscore */
551 c = provider->clkdm_name;
552
553 while (*c) {
554 if (*c == '-')
555 *c = '_';
556 c++;
557 }
558
510 INIT_LIST_HEAD(&provider->clocks); 559 INIT_LIST_HEAD(&provider->clocks);
511 560
512 /* Generate clocks */ 561 /* Generate clocks */
@@ -539,9 +588,13 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
539 init.flags = 0; 588 init.flags = 0;
540 if (reg_data->flags & CLKF_SET_RATE_PARENT) 589 if (reg_data->flags & CLKF_SET_RATE_PARENT)
541 init.flags |= CLK_SET_RATE_PARENT; 590 init.flags |= CLK_SET_RATE_PARENT;
542 init.name = kasprintf(GFP_KERNEL, "%s:%s:%04x:%d", 591 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
543 node->parent->name, node->name, 592 init.name = kasprintf(GFP_KERNEL, "%pOFn:%pOFn:%04x:%d",
544 reg_data->offset, 0); 593 node->parent, node,
594 reg_data->offset, 0);
595 else
596 init.name = kasprintf(GFP_KERNEL, "%pOFn:%04x:%d",
597 node, reg_data->offset, 0);
545 clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL); 598 clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
546 if (!init.name || !clkctrl_clk) 599 if (!init.name || !clkctrl_clk)
547 goto cleanup; 600 goto cleanup;
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index b58278077226..9f312a219510 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -24,6 +24,7 @@ struct clk_omap_divider {
24 u8 flags; 24 u8 flags;
25 s8 latch; 25 s8 latch;
26 const struct clk_div_table *table; 26 const struct clk_div_table *table;
27 u32 context;
27}; 28};
28 29
29#define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw) 30#define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw)
@@ -36,6 +37,7 @@ struct clk_omap_mux {
36 u8 shift; 37 u8 shift;
37 s8 latch; 38 s8 latch;
38 u8 flags; 39 u8 flags;
40 u8 saved_parent;
39}; 41};
40 42
41#define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw) 43#define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw)
@@ -184,9 +186,16 @@ struct omap_clkctrl_data {
184extern const struct omap_clkctrl_data omap4_clkctrl_data[]; 186extern const struct omap_clkctrl_data omap4_clkctrl_data[];
185extern const struct omap_clkctrl_data omap5_clkctrl_data[]; 187extern const struct omap_clkctrl_data omap5_clkctrl_data[];
186extern const struct omap_clkctrl_data dra7_clkctrl_data[]; 188extern const struct omap_clkctrl_data dra7_clkctrl_data[];
189extern const struct omap_clkctrl_data dra7_clkctrl_compat_data[];
190extern struct ti_dt_clk dra7xx_compat_clks[];
187extern const struct omap_clkctrl_data am3_clkctrl_data[]; 191extern const struct omap_clkctrl_data am3_clkctrl_data[];
192extern const struct omap_clkctrl_data am3_clkctrl_compat_data[];
193extern struct ti_dt_clk am33xx_compat_clks[];
188extern const struct omap_clkctrl_data am4_clkctrl_data[]; 194extern const struct omap_clkctrl_data am4_clkctrl_data[];
195extern const struct omap_clkctrl_data am4_clkctrl_compat_data[];
196extern struct ti_dt_clk am43xx_compat_clks[];
189extern const struct omap_clkctrl_data am438x_clkctrl_data[]; 197extern const struct omap_clkctrl_data am438x_clkctrl_data[];
198extern const struct omap_clkctrl_data am438x_clkctrl_compat_data[];
190extern const struct omap_clkctrl_data dm814_clkctrl_data[]; 199extern const struct omap_clkctrl_data dm814_clkctrl_data[];
191extern const struct omap_clkctrl_data dm816_clkctrl_data[]; 200extern const struct omap_clkctrl_data dm816_clkctrl_data[];
192 201
@@ -233,6 +242,8 @@ extern const struct clk_ops ti_clk_divider_ops;
233extern const struct clk_ops ti_clk_mux_ops; 242extern const struct clk_ops ti_clk_mux_ops;
234extern const struct clk_ops omap_gate_clk_ops; 243extern const struct clk_ops omap_gate_clk_ops;
235 244
245extern struct ti_clk_features ti_clk_features;
246
236void omap2_init_clk_clkdm(struct clk_hw *hw); 247void omap2_init_clk_clkdm(struct clk_hw *hw);
237int omap2_clkops_enable_clkdm(struct clk_hw *hw); 248int omap2_clkops_enable_clkdm(struct clk_hw *hw);
238void omap2_clkops_disable_clkdm(struct clk_hw *hw); 249void omap2_clkops_disable_clkdm(struct clk_hw *hw);
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
index 030e8b2c1050..6a89936ba03a 100644
--- a/drivers/clk/ti/composite.c
+++ b/drivers/clk/ti/composite.c
@@ -135,8 +135,8 @@ static void __init _register_composite(void *user,
135 135
136 comp = _lookup_component(cclk->comp_nodes[i]); 136 comp = _lookup_component(cclk->comp_nodes[i]);
137 if (!comp) { 137 if (!comp) {
138 pr_debug("component %s not ready for %s, retry\n", 138 pr_debug("component %s not ready for %pOFn, retry\n",
139 cclk->comp_nodes[i]->name, node->name); 139 cclk->comp_nodes[i]->name, node);
140 if (!ti_clk_retry_init(node, hw, 140 if (!ti_clk_retry_init(node, hw,
141 _register_composite)) 141 _register_composite))
142 return; 142 return;
@@ -144,8 +144,8 @@ static void __init _register_composite(void *user,
144 goto cleanup; 144 goto cleanup;
145 } 145 }
146 if (cclk->comp_clks[comp->type] != NULL) { 146 if (cclk->comp_clks[comp->type] != NULL) {
147 pr_err("duplicate component types for %s (%s)!\n", 147 pr_err("duplicate component types for %pOFn (%s)!\n",
148 node->name, component_clk_types[comp->type]); 148 node, component_clk_types[comp->type]);
149 goto cleanup; 149 goto cleanup;
150 } 150 }
151 151
@@ -168,7 +168,7 @@ static void __init _register_composite(void *user,
168 } 168 }
169 169
170 if (!num_parents) { 170 if (!num_parents) {
171 pr_err("%s: no parents found for %s!\n", __func__, node->name); 171 pr_err("%s: no parents found for %pOFn!\n", __func__, node);
172 goto cleanup; 172 goto cleanup;
173 } 173 }
174 174
@@ -212,7 +212,7 @@ static void __init of_ti_composite_clk_setup(struct device_node *node)
212 num_clks = of_clk_get_parent_count(node); 212 num_clks = of_clk_get_parent_count(node);
213 213
214 if (!num_clks) { 214 if (!num_clks) {
215 pr_err("composite clk %s must have component(s)\n", node->name); 215 pr_err("composite clk %pOFn must have component(s)\n", node);
216 return; 216 return;
217 } 217 }
218 218
@@ -248,7 +248,7 @@ int __init ti_clk_add_component(struct device_node *node, struct clk_hw *hw,
248 num_parents = of_clk_get_parent_count(node); 248 num_parents = of_clk_get_parent_count(node);
249 249
250 if (!num_parents) { 250 if (!num_parents) {
251 pr_err("component-clock %s must have parent(s)\n", node->name); 251 pr_err("component-clock %pOFn must have parent(s)\n", node);
252 return -EINVAL; 252 return -EINVAL;
253 } 253 }
254 254
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
index ccfb4d9a152a..8d77090ad94a 100644
--- a/drivers/clk/ti/divider.c
+++ b/drivers/clk/ti/divider.c
@@ -268,10 +268,46 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
268 return 0; 268 return 0;
269} 269}
270 270
271/**
272 * clk_divider_save_context - Save the divider value
273 * @hw: pointer struct clk_hw
274 *
275 * Save the divider value
276 */
277static int clk_divider_save_context(struct clk_hw *hw)
278{
279 struct clk_omap_divider *divider = to_clk_omap_divider(hw);
280 u32 val;
281
282 val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift;
283 divider->context = val & div_mask(divider);
284
285 return 0;
286}
287
288/**
289 * clk_divider_restore_context - restore the saved the divider value
290 * @hw: pointer struct clk_hw
291 *
292 * Restore the saved the divider value
293 */
294static void clk_divider_restore_context(struct clk_hw *hw)
295{
296 struct clk_omap_divider *divider = to_clk_omap_divider(hw);
297 u32 val;
298
299 val = ti_clk_ll_ops->clk_readl(&divider->reg);
300 val &= ~(div_mask(divider) << divider->shift);
301 val |= divider->context << divider->shift;
302 ti_clk_ll_ops->clk_writel(val, &divider->reg);
303}
304
271const struct clk_ops ti_clk_divider_ops = { 305const struct clk_ops ti_clk_divider_ops = {
272 .recalc_rate = ti_clk_divider_recalc_rate, 306 .recalc_rate = ti_clk_divider_recalc_rate,
273 .round_rate = ti_clk_divider_round_rate, 307 .round_rate = ti_clk_divider_round_rate,
274 .set_rate = ti_clk_divider_set_rate, 308 .set_rate = ti_clk_divider_set_rate,
309 .save_context = clk_divider_save_context,
310 .restore_context = clk_divider_restore_context,
275}; 311};
276 312
277static struct clk *_register_divider(struct device *dev, const char *name, 313static struct clk *_register_divider(struct device *dev, const char *name,
@@ -492,7 +528,7 @@ __init ti_clk_get_div_table(struct device_node *node)
492 } 528 }
493 529
494 if (!valid_div) { 530 if (!valid_div) {
495 pr_err("no valid dividers for %s table\n", node->name); 531 pr_err("no valid dividers for %pOFn table\n", node);
496 return ERR_PTR(-EINVAL); 532 return ERR_PTR(-EINVAL);
497 } 533 }
498 534
@@ -530,7 +566,7 @@ static int _get_divider_width(struct device_node *node,
530 min_div = 1; 566 min_div = 1;
531 567
532 if (of_property_read_u32(node, "ti,max-div", &max_div)) { 568 if (of_property_read_u32(node, "ti,max-div", &max_div)) {
533 pr_err("no max-div for %s!\n", node->name); 569 pr_err("no max-div for %pOFn!\n", node);
534 return -EINVAL; 570 return -EINVAL;
535 } 571 }
536 572
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index dc86d07d0921..92e28af7afba 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -39,6 +39,8 @@ static const struct clk_ops dpll_m4xen_ck_ops = {
39 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 39 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
40 .determine_rate = &omap4_dpll_regm4xen_determine_rate, 40 .determine_rate = &omap4_dpll_regm4xen_determine_rate,
41 .get_parent = &omap2_init_dpll_parent, 41 .get_parent = &omap2_init_dpll_parent,
42 .save_context = &omap3_core_dpll_save_context,
43 .restore_context = &omap3_core_dpll_restore_context,
42}; 44};
43#else 45#else
44static const struct clk_ops dpll_m4xen_ck_ops = {}; 46static const struct clk_ops dpll_m4xen_ck_ops = {};
@@ -62,6 +64,8 @@ static const struct clk_ops dpll_ck_ops = {
62 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 64 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
63 .determine_rate = &omap3_noncore_dpll_determine_rate, 65 .determine_rate = &omap3_noncore_dpll_determine_rate,
64 .get_parent = &omap2_init_dpll_parent, 66 .get_parent = &omap2_init_dpll_parent,
67 .save_context = &omap3_noncore_dpll_save_context,
68 .restore_context = &omap3_noncore_dpll_restore_context,
65}; 69};
66 70
67static const struct clk_ops dpll_no_gate_ck_ops = { 71static const struct clk_ops dpll_no_gate_ck_ops = {
@@ -72,6 +76,8 @@ static const struct clk_ops dpll_no_gate_ck_ops = {
72 .set_parent = &omap3_noncore_dpll_set_parent, 76 .set_parent = &omap3_noncore_dpll_set_parent,
73 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 77 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
74 .determine_rate = &omap3_noncore_dpll_determine_rate, 78 .determine_rate = &omap3_noncore_dpll_determine_rate,
79 .save_context = &omap3_noncore_dpll_save_context,
80 .restore_context = &omap3_noncore_dpll_restore_context
75}; 81};
76#else 82#else
77static const struct clk_ops dpll_core_ck_ops = {}; 83static const struct clk_ops dpll_core_ck_ops = {};
@@ -162,8 +168,8 @@ static void __init _register_dpll(void *user,
162 168
163 clk = of_clk_get(node, 0); 169 clk = of_clk_get(node, 0);
164 if (IS_ERR(clk)) { 170 if (IS_ERR(clk)) {
165 pr_debug("clk-ref missing for %s, retry later\n", 171 pr_debug("clk-ref missing for %pOFn, retry later\n",
166 node->name); 172 node);
167 if (!ti_clk_retry_init(node, hw, _register_dpll)) 173 if (!ti_clk_retry_init(node, hw, _register_dpll))
168 return; 174 return;
169 175
@@ -175,8 +181,8 @@ static void __init _register_dpll(void *user,
175 clk = of_clk_get(node, 1); 181 clk = of_clk_get(node, 1);
176 182
177 if (IS_ERR(clk)) { 183 if (IS_ERR(clk)) {
178 pr_debug("clk-bypass missing for %s, retry later\n", 184 pr_debug("clk-bypass missing for %pOFn, retry later\n",
179 node->name); 185 node);
180 if (!ti_clk_retry_init(node, hw, _register_dpll)) 186 if (!ti_clk_retry_init(node, hw, _register_dpll))
181 return; 187 return;
182 188
@@ -226,7 +232,7 @@ static void _register_dpll_x2(struct device_node *node,
226 232
227 parent_name = of_clk_get_parent_name(node, 0); 233 parent_name = of_clk_get_parent_name(node, 0);
228 if (!parent_name) { 234 if (!parent_name) {
229 pr_err("%s must have parent\n", node->name); 235 pr_err("%pOFn must have parent\n", node);
230 return; 236 return;
231 } 237 }
232 238
@@ -305,7 +311,7 @@ static void __init of_ti_dpll_setup(struct device_node *node,
305 311
306 init->num_parents = of_clk_get_parent_count(node); 312 init->num_parents = of_clk_get_parent_count(node);
307 if (!init->num_parents) { 313 if (!init->num_parents) {
308 pr_err("%s must have parent(s)\n", node->name); 314 pr_err("%pOFn must have parent(s)\n", node);
309 goto cleanup; 315 goto cleanup;
310 } 316 }
311 317
diff --git a/drivers/clk/ti/dpll3xxx.c b/drivers/clk/ti/dpll3xxx.c
index 4534de2ef455..44b6b6403753 100644
--- a/drivers/clk/ti/dpll3xxx.c
+++ b/drivers/clk/ti/dpll3xxx.c
@@ -782,6 +782,130 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
782 return rate; 782 return rate;
783} 783}
784 784
785/**
786 * omap3_core_dpll_save_context - Save the m and n values of the divider
787 * @hw: pointer struct clk_hw
788 *
789 * Before the dpll registers are lost save the last rounded rate m and n
790 * and the enable mask.
791 */
792int omap3_core_dpll_save_context(struct clk_hw *hw)
793{
794 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
795 struct dpll_data *dd;
796 u32 v;
797
798 dd = clk->dpll_data;
799
800 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
801 clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
802
803 if (clk->context == DPLL_LOCKED) {
804 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
805 dd->last_rounded_m = (v & dd->mult_mask) >>
806 __ffs(dd->mult_mask);
807 dd->last_rounded_n = ((v & dd->div1_mask) >>
808 __ffs(dd->div1_mask)) + 1;
809 }
810
811 return 0;
812}
813
814/**
815 * omap3_core_dpll_restore_context - restore the m and n values of the divider
816 * @hw: pointer struct clk_hw
817 *
818 * Restore the last rounded rate m and n
819 * and the enable mask.
820 */
821void omap3_core_dpll_restore_context(struct clk_hw *hw)
822{
823 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
824 const struct dpll_data *dd;
825 u32 v;
826
827 dd = clk->dpll_data;
828
829 if (clk->context == DPLL_LOCKED) {
830 _omap3_dpll_write_clken(clk, 0x4);
831 _omap3_wait_dpll_status(clk, 0);
832
833 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
834 v &= ~(dd->mult_mask | dd->div1_mask);
835 v |= dd->last_rounded_m << __ffs(dd->mult_mask);
836 v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
837 ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
838
839 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
840 _omap3_wait_dpll_status(clk, 1);
841 } else {
842 _omap3_dpll_write_clken(clk, clk->context);
843 }
844}
845
846/**
847 * omap3_non_core_dpll_save_context - Save the m and n values of the divider
848 * @hw: pointer struct clk_hw
849 *
850 * Before the dpll registers are lost save the last rounded rate m and n
851 * and the enable mask.
852 */
853int omap3_noncore_dpll_save_context(struct clk_hw *hw)
854{
855 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
856 struct dpll_data *dd;
857 u32 v;
858
859 dd = clk->dpll_data;
860
861 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
862 clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
863
864 if (clk->context == DPLL_LOCKED) {
865 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
866 dd->last_rounded_m = (v & dd->mult_mask) >>
867 __ffs(dd->mult_mask);
868 dd->last_rounded_n = ((v & dd->div1_mask) >>
869 __ffs(dd->div1_mask)) + 1;
870 }
871
872 return 0;
873}
874
875/**
876 * omap3_core_dpll_restore_context - restore the m and n values of the divider
877 * @hw: pointer struct clk_hw
878 *
879 * Restore the last rounded rate m and n
880 * and the enable mask.
881 */
882void omap3_noncore_dpll_restore_context(struct clk_hw *hw)
883{
884 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
885 const struct dpll_data *dd;
886 u32 ctrl, mult_div1;
887
888 dd = clk->dpll_data;
889
890 ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg);
891 mult_div1 = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
892
893 if (clk->context == ((ctrl & dd->enable_mask) >>
894 __ffs(dd->enable_mask)) &&
895 dd->last_rounded_m == ((mult_div1 & dd->mult_mask) >>
896 __ffs(dd->mult_mask)) &&
897 dd->last_rounded_n == ((mult_div1 & dd->div1_mask) >>
898 __ffs(dd->div1_mask)) + 1) {
899 /* nothing to be done */
900 return;
901 }
902
903 if (clk->context == DPLL_LOCKED)
904 omap3_noncore_dpll_program(clk, 0);
905 else
906 _omap3_dpll_write_clken(clk, clk->context);
907}
908
785/* OMAP3/4 non-CORE DPLL clkops */ 909/* OMAP3/4 non-CORE DPLL clkops */
786const struct clk_hw_omap_ops clkhwops_omap3_dpll = { 910const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
787 .allow_idle = omap3_dpll_allow_idle, 911 .allow_idle = omap3_dpll_allow_idle,
diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
index 071af44b1ba8..ed24f20f63c7 100644
--- a/drivers/clk/ti/fapll.c
+++ b/drivers/clk/ti/fapll.c
@@ -555,7 +555,7 @@ static void __init ti_fapll_setup(struct device_node *node)
555 555
556 init->num_parents = of_clk_get_parent_count(node); 556 init->num_parents = of_clk_get_parent_count(node);
557 if (init->num_parents != 2) { 557 if (init->num_parents != 2) {
558 pr_err("%s must have two parents\n", node->name); 558 pr_err("%pOFn must have two parents\n", node);
559 goto free; 559 goto free;
560 } 560 }
561 561
@@ -564,19 +564,19 @@ static void __init ti_fapll_setup(struct device_node *node)
564 564
565 fd->clk_ref = of_clk_get(node, 0); 565 fd->clk_ref = of_clk_get(node, 0);
566 if (IS_ERR(fd->clk_ref)) { 566 if (IS_ERR(fd->clk_ref)) {
567 pr_err("%s could not get clk_ref\n", node->name); 567 pr_err("%pOFn could not get clk_ref\n", node);
568 goto free; 568 goto free;
569 } 569 }
570 570
571 fd->clk_bypass = of_clk_get(node, 1); 571 fd->clk_bypass = of_clk_get(node, 1);
572 if (IS_ERR(fd->clk_bypass)) { 572 if (IS_ERR(fd->clk_bypass)) {
573 pr_err("%s could not get clk_bypass\n", node->name); 573 pr_err("%pOFn could not get clk_bypass\n", node);
574 goto free; 574 goto free;
575 } 575 }
576 576
577 fd->base = of_iomap(node, 0); 577 fd->base = of_iomap(node, 0);
578 if (!fd->base) { 578 if (!fd->base) {
579 pr_err("%s could not get IO base\n", node->name); 579 pr_err("%pOFn could not get IO base\n", node);
580 goto free; 580 goto free;
581 } 581 }
582 582
diff --git a/drivers/clk/ti/fixed-factor.c b/drivers/clk/ti/fixed-factor.c
index 0174a51a4ba6..7cbe896db071 100644
--- a/drivers/clk/ti/fixed-factor.c
+++ b/drivers/clk/ti/fixed-factor.c
@@ -42,12 +42,12 @@ static void __init of_ti_fixed_factor_clk_setup(struct device_node *node)
42 u32 flags = 0; 42 u32 flags = 0;
43 43
44 if (of_property_read_u32(node, "ti,clock-div", &div)) { 44 if (of_property_read_u32(node, "ti,clock-div", &div)) {
45 pr_err("%s must have a clock-div property\n", node->name); 45 pr_err("%pOFn must have a clock-div property\n", node);
46 return; 46 return;
47 } 47 }
48 48
49 if (of_property_read_u32(node, "ti,clock-mult", &mult)) { 49 if (of_property_read_u32(node, "ti,clock-mult", &mult)) {
50 pr_err("%s must have a clock-mult property\n", node->name); 50 pr_err("%pOFn must have a clock-mult property\n", node);
51 return; 51 return;
52 } 52 }
53 53
diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c
index 935b2de5fb88..1c78fff5513c 100644
--- a/drivers/clk/ti/gate.c
+++ b/drivers/clk/ti/gate.c
@@ -33,6 +33,7 @@ static const struct clk_ops omap_gate_clkdm_clk_ops = {
33 .init = &omap2_init_clk_clkdm, 33 .init = &omap2_init_clk_clkdm,
34 .enable = &omap2_clkops_enable_clkdm, 34 .enable = &omap2_clkops_enable_clkdm,
35 .disable = &omap2_clkops_disable_clkdm, 35 .disable = &omap2_clkops_disable_clkdm,
36 .restore_context = clk_gate_restore_context,
36}; 37};
37 38
38const struct clk_ops omap_gate_clk_ops = { 39const struct clk_ops omap_gate_clk_ops = {
@@ -40,6 +41,7 @@ const struct clk_ops omap_gate_clk_ops = {
40 .enable = &omap2_dflt_clk_enable, 41 .enable = &omap2_dflt_clk_enable,
41 .disable = &omap2_dflt_clk_disable, 42 .disable = &omap2_dflt_clk_disable,
42 .is_enabled = &omap2_dflt_clk_is_enabled, 43 .is_enabled = &omap2_dflt_clk_is_enabled,
44 .restore_context = clk_gate_restore_context,
43}; 45};
44 46
45static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = { 47static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
@@ -47,6 +49,7 @@ static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
47 .enable = &omap36xx_gate_clk_enable_with_hsdiv_restore, 49 .enable = &omap36xx_gate_clk_enable_with_hsdiv_restore,
48 .disable = &omap2_dflt_clk_disable, 50 .disable = &omap2_dflt_clk_disable,
49 .is_enabled = &omap2_dflt_clk_is_enabled, 51 .is_enabled = &omap2_dflt_clk_is_enabled,
52 .restore_context = clk_gate_restore_context,
50}; 53};
51 54
52/** 55/**
@@ -179,7 +182,7 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node,
179 } 182 }
180 183
181 if (of_clk_get_parent_count(node) != 1) { 184 if (of_clk_get_parent_count(node) != 1) {
182 pr_err("%s must have 1 parent\n", node->name); 185 pr_err("%pOFn must have 1 parent\n", node);
183 return; 186 return;
184 } 187 }
185 188
diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c
index 41ae7021670e..87e00c2ee957 100644
--- a/drivers/clk/ti/interface.c
+++ b/drivers/clk/ti/interface.c
@@ -84,7 +84,7 @@ static void __init _of_ti_interface_clk_setup(struct device_node *node,
84 84
85 parent_name = of_clk_get_parent_name(node, 0); 85 parent_name = of_clk_get_parent_name(node, 0);
86 if (!parent_name) { 86 if (!parent_name) {
87 pr_err("%s must have a parent\n", node->name); 87 pr_err("%pOFn must have a parent\n", node);
88 return; 88 return;
89 } 89 }
90 90
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
index 69a4308a5a98..883bdde94d04 100644
--- a/drivers/clk/ti/mux.c
+++ b/drivers/clk/ti/mux.c
@@ -91,10 +91,39 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
91 return 0; 91 return 0;
92} 92}
93 93
94/**
95 * clk_mux_save_context - Save the parent selcted in the mux
96 * @hw: pointer struct clk_hw
97 *
98 * Save the parent mux value.
99 */
100static int clk_mux_save_context(struct clk_hw *hw)
101{
102 struct clk_omap_mux *mux = to_clk_omap_mux(hw);
103
104 mux->saved_parent = ti_clk_mux_get_parent(hw);
105 return 0;
106}
107
108/**
109 * clk_mux_restore_context - Restore the parent in the mux
110 * @hw: pointer struct clk_hw
111 *
112 * Restore the saved parent mux value.
113 */
114static void clk_mux_restore_context(struct clk_hw *hw)
115{
116 struct clk_omap_mux *mux = to_clk_omap_mux(hw);
117
118 ti_clk_mux_set_parent(hw, mux->saved_parent);
119}
120
94const struct clk_ops ti_clk_mux_ops = { 121const struct clk_ops ti_clk_mux_ops = {
95 .get_parent = ti_clk_mux_get_parent, 122 .get_parent = ti_clk_mux_get_parent,
96 .set_parent = ti_clk_mux_set_parent, 123 .set_parent = ti_clk_mux_set_parent,
97 .determine_rate = __clk_mux_determine_rate, 124 .determine_rate = __clk_mux_determine_rate,
125 .save_context = clk_mux_save_context,
126 .restore_context = clk_mux_restore_context,
98}; 127};
99 128
100static struct clk *_register_mux(struct device *dev, const char *name, 129static struct clk *_register_mux(struct device *dev, const char *name,
@@ -186,7 +215,7 @@ static void of_mux_clk_setup(struct device_node *node)
186 215
187 num_parents = of_clk_get_parent_count(node); 216 num_parents = of_clk_get_parent_count(node);
188 if (num_parents < 2) { 217 if (num_parents < 2) {
189 pr_err("mux-clock %s must have parents\n", node->name); 218 pr_err("mux-clock %pOFn must have parents\n", node);
190 return; 219 return;
191 } 220 }
192 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); 221 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
@@ -278,7 +307,7 @@ static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
278 num_parents = of_clk_get_parent_count(node); 307 num_parents = of_clk_get_parent_count(node);
279 308
280 if (num_parents < 2) { 309 if (num_parents < 2) {
281 pr_err("%s must have parents\n", node->name); 310 pr_err("%pOFn must have parents\n", node);
282 goto cleanup; 311 goto cleanup;
283 } 312 }
284 313
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index 88a2cab37f62..d7b53ac8ad11 100644
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -602,7 +602,7 @@ void __init zynq_clock_init(void)
602 } 602 }
603 603
604 if (of_address_to_resource(np, 0, &res)) { 604 if (of_address_to_resource(np, 0, &res)) {
605 pr_err("%s: failed to get resource\n", np->name); 605 pr_err("%pOFn: failed to get resource\n", np);
606 goto np_err; 606 goto np_err;
607 } 607 }
608 608
@@ -611,7 +611,7 @@ void __init zynq_clock_init(void)
611 if (slcr->data) { 611 if (slcr->data) {
612 zynq_clkc_base = (__force void __iomem *)slcr->data + res.start; 612 zynq_clkc_base = (__force void __iomem *)slcr->data + res.start;
613 } else { 613 } else {
614 pr_err("%s: Unable to get I/O memory\n", np->name); 614 pr_err("%pOFn: Unable to get I/O memory\n", np);
615 of_node_put(slcr); 615 of_node_put(slcr);
616 goto np_err; 616 goto np_err;
617 } 617 }
diff --git a/include/dt-bindings/clock/am3.h b/include/dt-bindings/clock/am3.h
index b396f00e481d..86a8806e2140 100644
--- a/include/dt-bindings/clock/am3.h
+++ b/include/dt-bindings/clock/am3.h
@@ -16,6 +16,8 @@
16#define AM3_CLKCTRL_OFFSET 0x0 16#define AM3_CLKCTRL_OFFSET 0x0
17#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) 17#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET)
18 18
19/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
20
19/* l4_per clocks */ 21/* l4_per clocks */
20#define AM3_L4_PER_CLKCTRL_OFFSET 0x14 22#define AM3_L4_PER_CLKCTRL_OFFSET 0x14
21#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET) 23#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
@@ -105,4 +107,121 @@
105#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET) 107#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
106#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20) 108#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
107 109
110/* XXX: Compatibility part end */
111
112/* l4ls clocks */
113#define AM3_L4LS_CLKCTRL_OFFSET 0x38
114#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET)
115#define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38)
116#define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c)
117#define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40)
118#define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44)
119#define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48)
120#define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c)
121#define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50)
122#define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60)
123#define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c)
124#define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70)
125#define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74)
126#define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78)
127#define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c)
128#define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80)
129#define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84)
130#define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88)
131#define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x90)
132#define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac)
133#define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0)
134#define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4)
135#define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0)
136#define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4)
137#define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xcc)
138#define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd4)
139#define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd8)
140#define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec)
141#define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0)
142#define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf4)
143#define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x10c)
144#define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110)
145#define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130)
146
147/* l3s clocks */
148#define AM3_L3S_CLKCTRL_OFFSET 0x1c
149#define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET)
150#define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x1c)
151#define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x30)
152#define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34)
153#define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68)
154#define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0xf8)
155
156/* l3 clocks */
157#define AM3_L3_CLKCTRL_OFFSET 0x24
158#define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET)
159#define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x24)
160#define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28)
161#define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c)
162#define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x94)
163#define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0)
164#define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc)
165#define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc)
166#define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0)
167#define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xfc)
168#define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x100)
169
170/* l4hs clocks */
171#define AM3_L4HS_CLKCTRL_OFFSET 0x120
172#define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET)
173#define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120)
174
175/* pruss_ocp clocks */
176#define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0xe8
177#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET)
178#define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8)
179
180/* cpsw_125mhz clocks */
181#define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14)
182
183/* lcdc clocks */
184#define AM3_LCDC_CLKCTRL_OFFSET 0x18
185#define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET)
186#define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0x18)
187
188/* clk_24mhz clocks */
189#define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0x14c
190#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET)
191#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c)
192
193/* l4_wkup clocks */
194#define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
195#define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0x8)
196#define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc)
197#define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0xb4)
198#define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0xb8)
199#define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc)
200#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0xc0)
201#define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0xc4)
202#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0xc8)
203#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0xd4)
204
205/* l3_aon clocks */
206#define AM3_L3_AON_CLKCTRL_OFFSET 0x14
207#define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET)
208#define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0x14)
209
210/* l4_wkup_aon clocks */
211#define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0
212#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET)
213#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0)
214
215/* mpu clocks */
216#define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
217
218/* l4_rtc clocks */
219#define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0)
220
221/* gfx_l3 clocks */
222#define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
223
224/* l4_cefuse clocks */
225#define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0x20)
226
108#endif 227#endif
diff --git a/include/dt-bindings/clock/am4.h b/include/dt-bindings/clock/am4.h
index d21df00b3270..0f545b5afd60 100644
--- a/include/dt-bindings/clock/am4.h
+++ b/include/dt-bindings/clock/am4.h
@@ -16,6 +16,8 @@
16#define AM4_CLKCTRL_OFFSET 0x20 16#define AM4_CLKCTRL_OFFSET 0x20
17#define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET) 17#define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET)
18 18
19/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
20
19/* l4_wkup clocks */ 21/* l4_wkup clocks */
20#define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120) 22#define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120)
21#define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220) 23#define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
@@ -110,4 +112,134 @@
110#define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20) 112#define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20)
111#define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20) 113#define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20)
112 114
115/* XXX: Compatibility part end. */
116
117/* l3s_tsc clocks */
118#define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
119#define AM4_L3S_TSC_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET)
120#define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
121
122/* l4_wkup_aon clocks */
123#define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
124#define AM4_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_AON_CLKCTRL_OFFSET)
125#define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
126#define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
127
128/* l4_wkup clocks */
129#define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
130#define AM4_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_CLKCTRL_OFFSET)
131#define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
132#define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
133#define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
134#define AM4_L4_WKUP_I2C1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x340)
135#define AM4_L4_WKUP_UART1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x348)
136#define AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x350)
137#define AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x358)
138#define AM4_L4_WKUP_CONTROL_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x360)
139#define AM4_L4_WKUP_GPIO1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x368)
140
141/* mpu clocks */
142#define AM4_MPU_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
143
144/* gfx_l3 clocks */
145#define AM4_GFX_L3_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
146
147/* l4_rtc clocks */
148#define AM4_L4_RTC_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
149
150/* l3 clocks */
151#define AM4_L3_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
152#define AM4_L3_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28)
153#define AM4_L3_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30)
154#define AM4_L3_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40)
155#define AM4_L3_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50)
156#define AM4_L3_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58)
157#define AM4_L3_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78)
158#define AM4_L3_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80)
159#define AM4_L3_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88)
160#define AM4_L3_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90)
161#define AM4_L3_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0)
162
163/* l3s clocks */
164#define AM4_L3S_CLKCTRL_OFFSET 0x68
165#define AM4_L3S_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_CLKCTRL_OFFSET)
166#define AM4_L3S_VPFE0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x68)
167#define AM4_L3S_VPFE1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x70)
168#define AM4_L3S_GPMC_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x220)
169#define AM4_L3S_MCASP0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x238)
170#define AM4_L3S_MCASP1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x240)
171#define AM4_L3S_MMC3_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x248)
172#define AM4_L3S_QSPI_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x258)
173#define AM4_L3S_USB_OTG_SS0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x260)
174#define AM4_L3S_USB_OTG_SS1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x268)
175
176/* pruss_ocp clocks */
177#define AM4_PRUSS_OCP_CLKCTRL_OFFSET 0x320
178#define AM4_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM4_PRUSS_OCP_CLKCTRL_OFFSET)
179#define AM4_PRUSS_OCP_PRUSS_CLKCTRL AM4_PRUSS_OCP_CLKCTRL_INDEX(0x320)
180
181/* l4ls clocks */
182#define AM4_L4LS_CLKCTRL_OFFSET 0x420
183#define AM4_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM4_L4LS_CLKCTRL_OFFSET)
184#define AM4_L4LS_L4_LS_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x420)
185#define AM4_L4LS_D_CAN0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x428)
186#define AM4_L4LS_D_CAN1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x430)
187#define AM4_L4LS_EPWMSS0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x438)
188#define AM4_L4LS_EPWMSS1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x440)
189#define AM4_L4LS_EPWMSS2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x448)
190#define AM4_L4LS_EPWMSS3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x450)
191#define AM4_L4LS_EPWMSS4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x458)
192#define AM4_L4LS_EPWMSS5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x460)
193#define AM4_L4LS_ELM_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x468)
194#define AM4_L4LS_GPIO2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x478)
195#define AM4_L4LS_GPIO3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x480)
196#define AM4_L4LS_GPIO4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x488)
197#define AM4_L4LS_GPIO5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x490)
198#define AM4_L4LS_GPIO6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x498)
199#define AM4_L4LS_HDQ1W_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a0)
200#define AM4_L4LS_I2C2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a8)
201#define AM4_L4LS_I2C3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b0)
202#define AM4_L4LS_MAILBOX_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b8)
203#define AM4_L4LS_MMC1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c0)
204#define AM4_L4LS_MMC2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c8)
205#define AM4_L4LS_RNG_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4e0)
206#define AM4_L4LS_SPI0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x500)
207#define AM4_L4LS_SPI1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x508)
208#define AM4_L4LS_SPI2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x510)
209#define AM4_L4LS_SPI3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x518)
210#define AM4_L4LS_SPI4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x520)
211#define AM4_L4LS_SPINLOCK_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x528)
212#define AM4_L4LS_TIMER2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x530)
213#define AM4_L4LS_TIMER3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x538)
214#define AM4_L4LS_TIMER4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x540)
215#define AM4_L4LS_TIMER5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x548)
216#define AM4_L4LS_TIMER6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x550)
217#define AM4_L4LS_TIMER7_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x558)
218#define AM4_L4LS_TIMER8_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x560)
219#define AM4_L4LS_TIMER9_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x568)
220#define AM4_L4LS_TIMER10_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x570)
221#define AM4_L4LS_TIMER11_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x578)
222#define AM4_L4LS_UART2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x580)
223#define AM4_L4LS_UART3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x588)
224#define AM4_L4LS_UART4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x590)
225#define AM4_L4LS_UART5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x598)
226#define AM4_L4LS_UART6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5a0)
227#define AM4_L4LS_OCP2SCP0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5b8)
228#define AM4_L4LS_OCP2SCP1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5c0)
229
230/* emif clocks */
231#define AM4_EMIF_CLKCTRL_OFFSET 0x720
232#define AM4_EMIF_CLKCTRL_INDEX(offset) ((offset) - AM4_EMIF_CLKCTRL_OFFSET)
233#define AM4_EMIF_EMIF_CLKCTRL AM4_EMIF_CLKCTRL_INDEX(0x720)
234
235/* dss clocks */
236#define AM4_DSS_CLKCTRL_OFFSET 0xa20
237#define AM4_DSS_CLKCTRL_INDEX(offset) ((offset) - AM4_DSS_CLKCTRL_OFFSET)
238#define AM4_DSS_DSS_CORE_CLKCTRL AM4_DSS_CLKCTRL_INDEX(0xa20)
239
240/* cpsw_125mhz clocks */
241#define AM4_CPSW_125MHZ_CLKCTRL_OFFSET 0xb20
242#define AM4_CPSW_125MHZ_CLKCTRL_INDEX(offset) ((offset) - AM4_CPSW_125MHZ_CLKCTRL_OFFSET)
243#define AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL AM4_CPSW_125MHZ_CLKCTRL_INDEX(0xb20)
244
113#endif 245#endif
diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings/clock/dra7.h
index d7549c57cac3..ec969b5aeb25 100644
--- a/include/dt-bindings/clock/dra7.h
+++ b/include/dt-bindings/clock/dra7.h
@@ -16,19 +16,21 @@
16#define DRA7_CLKCTRL_OFFSET 0x20 16#define DRA7_CLKCTRL_OFFSET 0x20
17#define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET) 17#define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET)
18 18
19/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
20
19/* mpu clocks */ 21/* mpu clocks */
20#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 22#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
21 23
22/* ipu clocks */ 24/* ipu clocks */
23#define DRA7_IPU_CLKCTRL_OFFSET 0x40 25#define _DRA7_IPU_CLKCTRL_OFFSET 0x40
24#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET) 26#define _DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - _DRA7_IPU_CLKCTRL_OFFSET)
25#define DRA7_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50) 27#define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50)
26#define DRA7_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58) 28#define DRA7_TIMER5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x58)
27#define DRA7_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60) 29#define DRA7_TIMER6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x60)
28#define DRA7_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68) 30#define DRA7_TIMER7_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x68)
29#define DRA7_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70) 31#define DRA7_TIMER8_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x70)
30#define DRA7_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78) 32#define DRA7_I2C5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x78)
31#define DRA7_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80) 33#define DRA7_UART6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x80)
32 34
33/* rtc clocks */ 35/* rtc clocks */
34#define DRA7_RTC_CLKCTRL_OFFSET 0x40 36#define DRA7_RTC_CLKCTRL_OFFSET 0x40
@@ -99,65 +101,65 @@
99#define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) 101#define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
100 102
101/* l4per clocks */ 103/* l4per clocks */
102#define DRA7_L4PER_CLKCTRL_OFFSET 0x0 104#define _DRA7_L4PER_CLKCTRL_OFFSET 0x0
103#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET) 105#define _DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - _DRA7_L4PER_CLKCTRL_OFFSET)
104#define DRA7_L4_PER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc) 106#define DRA7_L4_PER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc)
105#define DRA7_L4_PER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x14) 107#define DRA7_L4_PER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x14)
106#define DRA7_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28) 108#define DRA7_TIMER10_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x28)
107#define DRA7_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30) 109#define DRA7_TIMER11_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x30)
108#define DRA7_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38) 110#define DRA7_TIMER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x38)
109#define DRA7_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40) 111#define DRA7_TIMER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x40)
110#define DRA7_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48) 112#define DRA7_TIMER4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x48)
111#define DRA7_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50) 113#define DRA7_TIMER9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x50)
112#define DRA7_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58) 114#define DRA7_ELM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x58)
113#define DRA7_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60) 115#define DRA7_GPIO2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x60)
114#define DRA7_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68) 116#define DRA7_GPIO3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x68)
115#define DRA7_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70) 117#define DRA7_GPIO4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x70)
116#define DRA7_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78) 118#define DRA7_GPIO5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x78)
117#define DRA7_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80) 119#define DRA7_GPIO6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x80)
118#define DRA7_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88) 120#define DRA7_HDQ1W_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x88)
119#define DRA7_EPWMSS1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x90) 121#define DRA7_EPWMSS1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x90)
120#define DRA7_EPWMSS2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x98) 122#define DRA7_EPWMSS2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x98)
121#define DRA7_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0) 123#define DRA7_I2C1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa0)
122#define DRA7_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8) 124#define DRA7_I2C2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa8)
123#define DRA7_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0) 125#define DRA7_I2C3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb0)
124#define DRA7_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8) 126#define DRA7_I2C4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb8)
125#define DRA7_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0) 127#define DRA7_L4_PER1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc0)
126#define DRA7_EPWMSS0_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc4) 128#define DRA7_EPWMSS0_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc4)
127#define DRA7_TIMER13_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc8) 129#define DRA7_TIMER13_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc8)
128#define DRA7_TIMER14_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd0) 130#define DRA7_TIMER14_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd0)
129#define DRA7_TIMER15_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd8) 131#define DRA7_TIMER15_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd8)
130#define DRA7_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0) 132#define DRA7_MCSPI1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf0)
131#define DRA7_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8) 133#define DRA7_MCSPI2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf8)
132#define DRA7_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100) 134#define DRA7_MCSPI3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x100)
133#define DRA7_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108) 135#define DRA7_MCSPI4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x108)
134#define DRA7_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110) 136#define DRA7_GPIO7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x110)
135#define DRA7_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118) 137#define DRA7_GPIO8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x118)
136#define DRA7_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120) 138#define DRA7_MMC3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x120)
137#define DRA7_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128) 139#define DRA7_MMC4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x128)
138#define DRA7_TIMER16_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x130) 140#define DRA7_TIMER16_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x130)
139#define DRA7_QSPI_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x138) 141#define DRA7_QSPI_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x138)
140#define DRA7_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140) 142#define DRA7_UART1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x140)
141#define DRA7_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148) 143#define DRA7_UART2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x148)
142#define DRA7_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150) 144#define DRA7_UART3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x150)
143#define DRA7_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158) 145#define DRA7_UART4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x158)
144#define DRA7_MCASP2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x160) 146#define DRA7_MCASP2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x160)
145#define DRA7_MCASP3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x168) 147#define DRA7_MCASP3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x168)
146#define DRA7_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170) 148#define DRA7_UART5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x170)
147#define DRA7_MCASP5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x178) 149#define DRA7_MCASP5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x178)
148#define DRA7_MCASP8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x190) 150#define DRA7_MCASP8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x190)
149#define DRA7_MCASP4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x198) 151#define DRA7_MCASP4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x198)
150#define DRA7_AES1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a0) 152#define DRA7_AES1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
151#define DRA7_AES2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a8) 153#define DRA7_AES2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
152#define DRA7_DES_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1b0) 154#define DRA7_DES_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
153#define DRA7_RNG_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c0) 155#define DRA7_RNG_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
154#define DRA7_SHAM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c8) 156#define DRA7_SHAM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
155#define DRA7_UART7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1d0) 157#define DRA7_UART7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
156#define DRA7_UART8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e0) 158#define DRA7_UART8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
157#define DRA7_UART9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e8) 159#define DRA7_UART9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
158#define DRA7_DCAN2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1f0) 160#define DRA7_DCAN2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
159#define DRA7_MCASP6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x204) 161#define DRA7_MCASP6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x204)
160#define DRA7_MCASP7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x208) 162#define DRA7_MCASP7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x208)
161 163
162/* wkupaon clocks */ 164/* wkupaon clocks */
163#define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) 165#define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
@@ -170,4 +172,192 @@
170#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) 172#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
171#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) 173#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
172 174
175/* XXX: Compatibility part end. */
176
177/* mpu clocks */
178#define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
179
180/* dsp1 clocks */
181#define DRA7_DSP1_MMU0_DSP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
182
183/* ipu1 clocks */
184#define DRA7_IPU1_MMU_IPU1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
185
186/* ipu clocks */
187#define DRA7_IPU_CLKCTRL_OFFSET 0x50
188#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET)
189#define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
190#define DRA7_IPU_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
191#define DRA7_IPU_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
192#define DRA7_IPU_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
193#define DRA7_IPU_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
194#define DRA7_IPU_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78)
195#define DRA7_IPU_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80)
196
197/* dsp2 clocks */
198#define DRA7_DSP2_MMU0_DSP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
199
200/* rtc clocks */
201#define DRA7_RTC_RTCSS_CLKCTRL DRA7_CLKCTRL_INDEX(0x44)
202
203/* coreaon clocks */
204#define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
205#define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
206
207/* l3main1 clocks */
208#define DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
209#define DRA7_L3MAIN1_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
210#define DRA7_L3MAIN1_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
211#define DRA7_L3MAIN1_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
212#define DRA7_L3MAIN1_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
213#define DRA7_L3MAIN1_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
214#define DRA7_L3MAIN1_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
215
216/* ipu2 clocks */
217#define DRA7_IPU2_MMU_IPU2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
218
219/* dma clocks */
220#define DRA7_DMA_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
221
222/* emif clocks */
223#define DRA7_EMIF_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
224
225/* atl clocks */
226#define DRA7_ATL_CLKCTRL_OFFSET 0x0
227#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET)
228#define DRA7_ATL_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0)
229
230/* l4cfg clocks */
231#define DRA7_L4CFG_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
232#define DRA7_L4CFG_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
233#define DRA7_L4CFG_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
234#define DRA7_L4CFG_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
235#define DRA7_L4CFG_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
236#define DRA7_L4CFG_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58)
237#define DRA7_L4CFG_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60)
238#define DRA7_L4CFG_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68)
239#define DRA7_L4CFG_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
240#define DRA7_L4CFG_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
241#define DRA7_L4CFG_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
242#define DRA7_L4CFG_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
243#define DRA7_L4CFG_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
244#define DRA7_L4CFG_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98)
245#define DRA7_L4CFG_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
246
247/* l3instr clocks */
248#define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
249#define DRA7_L3INSTR_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
250
251/* dss clocks */
252#define DRA7_DSS_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
253#define DRA7_DSS_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
254
255/* l3init clocks */
256#define DRA7_L3INIT_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
257#define DRA7_L3INIT_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
258#define DRA7_L3INIT_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
259#define DRA7_L3INIT_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
260#define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
261#define DRA7_L3INIT_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
262#define DRA7_L3INIT_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0)
263#define DRA7_L3INIT_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8)
264#define DRA7_L3INIT_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
265
266/* pcie clocks */
267#define DRA7_PCIE_CLKCTRL_OFFSET 0xb0
268#define DRA7_PCIE_CLKCTRL_INDEX(offset) ((offset) - DRA7_PCIE_CLKCTRL_OFFSET)
269#define DRA7_PCIE_PCIE1_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb0)
270#define DRA7_PCIE_PCIE2_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb8)
271
272/* gmac clocks */
273#define DRA7_GMAC_CLKCTRL_OFFSET 0xd0
274#define DRA7_GMAC_CLKCTRL_INDEX(offset) ((offset) - DRA7_GMAC_CLKCTRL_OFFSET)
275#define DRA7_GMAC_GMAC_CLKCTRL DRA7_GMAC_CLKCTRL_INDEX(0xd0)
276
277/* l4per clocks */
278#define DRA7_L4PER_CLKCTRL_OFFSET 0x28
279#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
280#define DRA7_L4PER_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28)
281#define DRA7_L4PER_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30)
282#define DRA7_L4PER_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38)
283#define DRA7_L4PER_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40)
284#define DRA7_L4PER_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48)
285#define DRA7_L4PER_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50)
286#define DRA7_L4PER_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58)
287#define DRA7_L4PER_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60)
288#define DRA7_L4PER_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68)
289#define DRA7_L4PER_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70)
290#define DRA7_L4PER_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78)
291#define DRA7_L4PER_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80)
292#define DRA7_L4PER_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88)
293#define DRA7_L4PER_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0)
294#define DRA7_L4PER_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8)
295#define DRA7_L4PER_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0)
296#define DRA7_L4PER_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8)
297#define DRA7_L4PER_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0)
298#define DRA7_L4PER_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0)
299#define DRA7_L4PER_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8)
300#define DRA7_L4PER_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100)
301#define DRA7_L4PER_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108)
302#define DRA7_L4PER_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110)
303#define DRA7_L4PER_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118)
304#define DRA7_L4PER_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120)
305#define DRA7_L4PER_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128)
306#define DRA7_L4PER_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140)
307#define DRA7_L4PER_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148)
308#define DRA7_L4PER_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150)
309#define DRA7_L4PER_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158)
310#define DRA7_L4PER_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170)
311
312/* l4sec clocks */
313#define DRA7_L4SEC_CLKCTRL_OFFSET 0x1a0
314#define DRA7_L4SEC_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4SEC_CLKCTRL_OFFSET)
315#define DRA7_L4SEC_AES1_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a0)
316#define DRA7_L4SEC_AES2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a8)
317#define DRA7_L4SEC_DES_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1b0)
318#define DRA7_L4SEC_RNG_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c0)
319#define DRA7_L4SEC_SHAM_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c8)
320
321/* l4per2 clocks */
322#define DRA7_L4PER2_CLKCTRL_OFFSET 0xc
323#define DRA7_L4PER2_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER2_CLKCTRL_OFFSET)
324#define DRA7_L4PER2_L4_PER2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc)
325#define DRA7_L4PER2_PRUSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x18)
326#define DRA7_L4PER2_PRUSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x20)
327#define DRA7_L4PER2_EPWMSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x90)
328#define DRA7_L4PER2_EPWMSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x98)
329#define DRA7_L4PER2_EPWMSS0_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc4)
330#define DRA7_L4PER2_QSPI_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x138)
331#define DRA7_L4PER2_MCASP2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x160)
332#define DRA7_L4PER2_MCASP3_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x168)
333#define DRA7_L4PER2_MCASP5_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x178)
334#define DRA7_L4PER2_MCASP8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x190)
335#define DRA7_L4PER2_MCASP4_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x198)
336#define DRA7_L4PER2_UART7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1d0)
337#define DRA7_L4PER2_UART8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e0)
338#define DRA7_L4PER2_UART9_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e8)
339#define DRA7_L4PER2_DCAN2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1f0)
340#define DRA7_L4PER2_MCASP6_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x204)
341#define DRA7_L4PER2_MCASP7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x208)
342
343/* l4per3 clocks */
344#define DRA7_L4PER3_CLKCTRL_OFFSET 0x14
345#define DRA7_L4PER3_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER3_CLKCTRL_OFFSET)
346#define DRA7_L4PER3_L4_PER3_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x14)
347#define DRA7_L4PER3_TIMER13_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xc8)
348#define DRA7_L4PER3_TIMER14_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd0)
349#define DRA7_L4PER3_TIMER15_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd8)
350#define DRA7_L4PER3_TIMER16_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x130)
351
352/* wkupaon clocks */
353#define DRA7_WKUPAON_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
354#define DRA7_WKUPAON_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
355#define DRA7_WKUPAON_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
356#define DRA7_WKUPAON_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
357#define DRA7_WKUPAON_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
358#define DRA7_WKUPAON_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
359#define DRA7_WKUPAON_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
360#define DRA7_WKUPAON_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
361#define DRA7_WKUPAON_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
362
173#endif 363#endif
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
index c796ff02ceeb..fe8214017b46 100644
--- a/include/dt-bindings/clock/exynos3250.h
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -1,11 +1,8 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Tomasz Figa <t.figa@samsung.com> 4 * Author: Tomasz Figa <t.figa@samsung.com>
4 * 5 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Device Tree binding constants for Samsung Exynos3250 clock controllers. 6 * Device Tree binding constants for Samsung Exynos3250 clock controllers.
10 */ 7 */
11 8
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index e9f9d400c322..a0439ce8e8d3 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -1,13 +1,10 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Author: Andrzej Hajda <a.hajda@samsung.com> 4 * Author: Andrzej Hajda <a.hajda@samsung.com>
4 * 5 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Device Tree binding constants for Exynos4 clock controller. 6 * Device Tree binding constants for Exynos4 clock controller.
10*/ 7 */
11 8
12#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H 9#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H
13#define _DT_BINDINGS_CLOCK_EXYNOS_4_H 10#define _DT_BINDINGS_CLOCK_EXYNOS_4_H
@@ -190,32 +187,6 @@
190#define CLK_MIPI_HSI 349 /* Exynos4210 only */ 187#define CLK_MIPI_HSI 349 /* Exynos4210 only */
191#define CLK_PIXELASYNCM0 351 188#define CLK_PIXELASYNCM0 351
192#define CLK_PIXELASYNCM1 352 189#define CLK_PIXELASYNCM1 352
193#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */
194#define CLK_FIMC_LITE1 354 /* Exynos4x12 only */
195#define CLK_PPMUISPX 355 /* Exynos4x12 only */
196#define CLK_PPMUISPMX 356 /* Exynos4x12 only */
197#define CLK_FIMC_ISP 357 /* Exynos4x12 only */
198#define CLK_FIMC_DRC 358 /* Exynos4x12 only */
199#define CLK_FIMC_FD 359 /* Exynos4x12 only */
200#define CLK_MCUISP 360 /* Exynos4x12 only */
201#define CLK_GICISP 361 /* Exynos4x12 only */
202#define CLK_SMMU_ISP 362 /* Exynos4x12 only */
203#define CLK_SMMU_DRC 363 /* Exynos4x12 only */
204#define CLK_SMMU_FD 364 /* Exynos4x12 only */
205#define CLK_SMMU_LITE0 365 /* Exynos4x12 only */
206#define CLK_SMMU_LITE1 366 /* Exynos4x12 only */
207#define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */
208#define CLK_MPWM_ISP 368 /* Exynos4x12 only */
209#define CLK_I2C0_ISP 369 /* Exynos4x12 only */
210#define CLK_I2C1_ISP 370 /* Exynos4x12 only */
211#define CLK_MTCADC_ISP 371 /* Exynos4x12 only */
212#define CLK_PWM_ISP 372 /* Exynos4x12 only */
213#define CLK_WDT_ISP 373 /* Exynos4x12 only */
214#define CLK_UART_ISP 374 /* Exynos4x12 only */
215#define CLK_ASYNCAXIM 375 /* Exynos4x12 only */
216#define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */
217#define CLK_SPI0_ISP 377 /* Exynos4x12 only */
218#define CLK_SPI1_ISP 378 /* Exynos4x12 only */
219#define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ 190#define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */
220#define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ 191#define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */
221#define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */ 192#define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */
@@ -257,10 +228,6 @@
257#define CLK_PPMUACP 415 228#define CLK_PPMUACP 415
258 229
259/* div clocks */ 230/* div clocks */
260#define CLK_DIV_ISP0 450 /* Exynos4x12 only */
261#define CLK_DIV_ISP1 451 /* Exynos4x12 only */
262#define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */
263#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
264#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ 231#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
265#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ 232#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
266#define CLK_DIV_ACP 456 233#define CLK_DIV_ACP 456
diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h
index 15508adcdfde..bc8a3c53a54b 100644
--- a/include/dt-bindings/clock/exynos5250.h
+++ b/include/dt-bindings/clock/exynos5250.h
@@ -1,13 +1,10 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Author: Andrzej Hajda <a.hajda@samsung.com> 4 * Author: Andrzej Hajda <a.hajda@samsung.com>
4 * 5 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Device Tree binding constants for Exynos5250 clock controller. 6 * Device Tree binding constants for Exynos5250 clock controller.
10*/ 7 */
11 8
12#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H 9#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H
13#define _DT_BINDINGS_CLOCK_EXYNOS_5250_H 10#define _DT_BINDINGS_CLOCK_EXYNOS_5250_H
diff --git a/include/dt-bindings/clock/exynos5260-clk.h b/include/dt-bindings/clock/exynos5260-clk.h
index a4bac9a1764f..98a58cbd81b2 100644
--- a/include/dt-bindings/clock/exynos5260-clk.h
+++ b/include/dt-bindings/clock/exynos5260-clk.h
@@ -1,13 +1,10 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Rahul Sharma <rahul.sharma@samsung.com> 4 * Author: Rahul Sharma <rahul.sharma@samsung.com>
4 * 5 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Provides Constants for Exynos5260 clocks. 6 * Provides Constants for Exynos5260 clocks.
10*/ 7 */
11 8
12#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H 9#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H
13#define _DT_BINDINGS_CLK_EXYNOS5260_H 10#define _DT_BINDINGS_CLK_EXYNOS5260_H
diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
index 6cb4e90f81fc..f179eabbcdb7 100644
--- a/include/dt-bindings/clock/exynos5410.h
+++ b/include/dt-bindings/clock/exynos5410.h
@@ -1,13 +1,10 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2016 Krzysztof Kozlowski 4 * Copyright (c) 2016 Krzysztof Kozlowski
4 * 5 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Device Tree binding constants for Exynos5421 clock controller. 6 * Device Tree binding constants for Exynos5421 clock controller.
10*/ 7 */
11 8
12#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H 9#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
13#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H 10#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 2740ae0424a9..355f469943f1 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -1,13 +1,10 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Author: Andrzej Hajda <a.hajda@samsung.com> 4 * Author: Andrzej Hajda <a.hajda@samsung.com>
4 * 5 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Device Tree binding constants for Exynos5420 clock controller. 6 * Device Tree binding constants for Exynos5420 clock controller.
10*/ 7 */
11 8
12#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H 9#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H
13#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H 10#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index be39d23e6a32..98bd85ce1e45 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -1,10 +1,7 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com> 4 * Author: Chanwoo Choi <cw00.choi@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */ 5 */
9 6
10#ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H 7#ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 10c558611085..fce33c7050c8 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -1,11 +1,8 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> 4 * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
4 * 5 */
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8*/
9 6
10#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H 7#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
11#define _DT_BINDINGS_CLOCK_EXYNOS7_H 8#define _DT_BINDINGS_CLOCK_EXYNOS7_H
diff --git a/include/dt-bindings/clock/hi3670-clock.h b/include/dt-bindings/clock/hi3670-clock.h
new file mode 100644
index 000000000000..fa48583f87d6
--- /dev/null
+++ b/include/dt-bindings/clock/hi3670-clock.h
@@ -0,0 +1,348 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Device Tree binding constants for HiSilicon Hi3670 SoC
4 *
5 * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd.
6 * Copyright (c) 2018 Linaro Ltd.
7 */
8
9#ifndef __DT_BINDINGS_CLOCK_HI3670_H
10#define __DT_BINDINGS_CLOCK_HI3670_H
11
12/* clk in stub clock */
13#define HI3670_CLK_STUB_CLUSTER0 0
14#define HI3670_CLK_STUB_CLUSTER1 1
15#define HI3670_CLK_STUB_GPU 2
16#define HI3670_CLK_STUB_DDR 3
17#define HI3670_CLK_STUB_DDR_VOTE 4
18#define HI3670_CLK_STUB_DDR_LIMIT 5
19#define HI3670_CLK_STUB_NUM 6
20
21/* clk in crg clock */
22#define HI3670_CLKIN_SYS 0
23#define HI3670_CLKIN_REF 1
24#define HI3670_CLK_FLL_SRC 2
25#define HI3670_CLK_PPLL0 3
26#define HI3670_CLK_PPLL1 4
27#define HI3670_CLK_PPLL2 5
28#define HI3670_CLK_PPLL3 6
29#define HI3670_CLK_PPLL4 7
30#define HI3670_CLK_PPLL6 8
31#define HI3670_CLK_PPLL7 9
32#define HI3670_CLK_PPLL_PCIE 10
33#define HI3670_CLK_PCIEPLL_REV 11
34#define HI3670_CLK_SCPLL 12
35#define HI3670_PCLK 13
36#define HI3670_CLK_UART0_DBG 14
37#define HI3670_CLK_UART6 15
38#define HI3670_OSC32K 16
39#define HI3670_OSC19M 17
40#define HI3670_CLK_480M 18
41#define HI3670_CLK_INVALID 19
42#define HI3670_CLK_DIV_SYSBUS 20
43#define HI3670_CLK_FACTOR_MMC 21
44#define HI3670_CLK_SD_SYS 22
45#define HI3670_CLK_SDIO_SYS 23
46#define HI3670_CLK_DIV_A53HPM 24
47#define HI3670_CLK_DIV_320M 25
48#define HI3670_PCLK_GATE_UART0 26
49#define HI3670_CLK_FACTOR_UART0 27
50#define HI3670_CLK_FACTOR_USB3PHY_PLL 28
51#define HI3670_CLK_GATE_ABB_USB 29
52#define HI3670_CLK_GATE_UFSPHY_REF 30
53#define HI3670_ICS_VOLT_HIGH 31
54#define HI3670_ICS_VOLT_MIDDLE 32
55#define HI3670_VENC_VOLT_HOLD 33
56#define HI3670_VDEC_VOLT_HOLD 34
57#define HI3670_EDC_VOLT_HOLD 35
58#define HI3670_CLK_ISP_SNCLK_FAC 36
59#define HI3670_CLK_FACTOR_RXDPHY 37
60#define HI3670_AUTODIV_SYSBUS 38
61#define HI3670_AUTODIV_EMMC0BUS 39
62#define HI3670_PCLK_ANDGT_MMC1_PCIE 40
63#define HI3670_CLK_GATE_VCODECBUS_GT 41
64#define HI3670_CLK_ANDGT_SD 42
65#define HI3670_CLK_SD_SYS_GT 43
66#define HI3670_CLK_ANDGT_SDIO 44
67#define HI3670_CLK_SDIO_SYS_GT 45
68#define HI3670_CLK_A53HPM_ANDGT 46
69#define HI3670_CLK_320M_PLL_GT 47
70#define HI3670_CLK_ANDGT_UARTH 48
71#define HI3670_CLK_ANDGT_UARTL 49
72#define HI3670_CLK_ANDGT_UART0 50
73#define HI3670_CLK_ANDGT_SPI 51
74#define HI3670_CLK_ANDGT_PCIEAXI 52
75#define HI3670_CLK_DIV_AO_ASP_GT 53
76#define HI3670_CLK_GATE_CSI_TRANS 54
77#define HI3670_CLK_GATE_DSI_TRANS 55
78#define HI3670_CLK_ANDGT_PTP 56
79#define HI3670_CLK_ANDGT_OUT0 57
80#define HI3670_CLK_ANDGT_OUT1 58
81#define HI3670_CLKGT_DP_AUDIO_PLL_AO 59
82#define HI3670_CLK_ANDGT_VDEC 60
83#define HI3670_CLK_ANDGT_VENC 61
84#define HI3670_CLK_ISP_SNCLK_ANGT 62
85#define HI3670_CLK_ANDGT_RXDPHY 63
86#define HI3670_CLK_ANDGT_ICS 64
87#define HI3670_AUTODIV_DMABUS 65
88#define HI3670_CLK_MUX_SYSBUS 66
89#define HI3670_CLK_MUX_VCODECBUS 67
90#define HI3670_CLK_MUX_SD_SYS 68
91#define HI3670_CLK_MUX_SD_PLL 69
92#define HI3670_CLK_MUX_SDIO_SYS 70
93#define HI3670_CLK_MUX_SDIO_PLL 71
94#define HI3670_CLK_MUX_A53HPM 72
95#define HI3670_CLK_MUX_320M 73
96#define HI3670_CLK_MUX_UARTH 74
97#define HI3670_CLK_MUX_UARTL 75
98#define HI3670_CLK_MUX_UART0 76
99#define HI3670_CLK_MUX_I2C 77
100#define HI3670_CLK_MUX_SPI 78
101#define HI3670_CLK_MUX_PCIEAXI 79
102#define HI3670_CLK_MUX_AO_ASP 80
103#define HI3670_CLK_MUX_VDEC 81
104#define HI3670_CLK_MUX_VENC 82
105#define HI3670_CLK_ISP_SNCLK_MUX0 83
106#define HI3670_CLK_ISP_SNCLK_MUX1 84
107#define HI3670_CLK_ISP_SNCLK_MUX2 85
108#define HI3670_CLK_MUX_RXDPHY_CFG 86
109#define HI3670_CLK_MUX_ICS 87
110#define HI3670_CLK_DIV_CFGBUS 88
111#define HI3670_CLK_DIV_MMC0BUS 89
112#define HI3670_CLK_DIV_MMC1BUS 90
113#define HI3670_PCLK_DIV_MMC1_PCIE 91
114#define HI3670_CLK_DIV_VCODECBUS 92
115#define HI3670_CLK_DIV_SD 93
116#define HI3670_CLK_DIV_SDIO 94
117#define HI3670_CLK_DIV_UARTH 95
118#define HI3670_CLK_DIV_UARTL 96
119#define HI3670_CLK_DIV_UART0 97
120#define HI3670_CLK_DIV_I2C 98
121#define HI3670_CLK_DIV_SPI 99
122#define HI3670_CLK_DIV_PCIEAXI 100
123#define HI3670_CLK_DIV_AO_ASP 101
124#define HI3670_CLK_DIV_CSI_TRANS 102
125#define HI3670_CLK_DIV_DSI_TRANS 103
126#define HI3670_CLK_DIV_PTP 104
127#define HI3670_CLK_DIV_CLKOUT0_PLL 105
128#define HI3670_CLK_DIV_CLKOUT1_PLL 106
129#define HI3670_CLKDIV_DP_AUDIO_PLL_AO 107
130#define HI3670_CLK_DIV_VDEC 108
131#define HI3670_CLK_DIV_VENC 109
132#define HI3670_CLK_ISP_SNCLK_DIV0 110
133#define HI3670_CLK_ISP_SNCLK_DIV1 111
134#define HI3670_CLK_ISP_SNCLK_DIV2 112
135#define HI3670_CLK_DIV_ICS 113
136#define HI3670_PPLL1_EN_ACPU 114
137#define HI3670_PPLL2_EN_ACPU 115
138#define HI3670_PPLL3_EN_ACPU 116
139#define HI3670_PPLL1_GT_CPU 117
140#define HI3670_PPLL2_GT_CPU 118
141#define HI3670_PPLL3_GT_CPU 119
142#define HI3670_CLK_GATE_PPLL2_MEDIA 120
143#define HI3670_CLK_GATE_PPLL3_MEDIA 121
144#define HI3670_CLK_GATE_PPLL4_MEDIA 122
145#define HI3670_CLK_GATE_PPLL6_MEDIA 123
146#define HI3670_CLK_GATE_PPLL7_MEDIA 124
147#define HI3670_PCLK_GPIO0 125
148#define HI3670_PCLK_GPIO1 126
149#define HI3670_PCLK_GPIO2 127
150#define HI3670_PCLK_GPIO3 128
151#define HI3670_PCLK_GPIO4 129
152#define HI3670_PCLK_GPIO5 130
153#define HI3670_PCLK_GPIO6 131
154#define HI3670_PCLK_GPIO7 132
155#define HI3670_PCLK_GPIO8 133
156#define HI3670_PCLK_GPIO9 134
157#define HI3670_PCLK_GPIO10 135
158#define HI3670_PCLK_GPIO11 136
159#define HI3670_PCLK_GPIO12 137
160#define HI3670_PCLK_GPIO13 138
161#define HI3670_PCLK_GPIO14 139
162#define HI3670_PCLK_GPIO15 140
163#define HI3670_PCLK_GPIO16 141
164#define HI3670_PCLK_GPIO17 142
165#define HI3670_PCLK_GPIO20 143
166#define HI3670_PCLK_GPIO21 144
167#define HI3670_PCLK_GATE_DSI0 145
168#define HI3670_PCLK_GATE_DSI1 146
169#define HI3670_HCLK_GATE_USB3OTG 147
170#define HI3670_ACLK_GATE_USB3DVFS 148
171#define HI3670_HCLK_GATE_SDIO 149
172#define HI3670_PCLK_GATE_PCIE_SYS 150
173#define HI3670_PCLK_GATE_PCIE_PHY 151
174#define HI3670_PCLK_GATE_MMC1_PCIE 152
175#define HI3670_PCLK_GATE_MMC0_IOC 153
176#define HI3670_PCLK_GATE_MMC1_IOC 154
177#define HI3670_CLK_GATE_DMAC 155
178#define HI3670_CLK_GATE_VCODECBUS2DDR 156
179#define HI3670_CLK_CCI400_BYPASS 157
180#define HI3670_CLK_GATE_CCI400 158
181#define HI3670_CLK_GATE_SD 159
182#define HI3670_HCLK_GATE_SD 160
183#define HI3670_CLK_GATE_SDIO 161
184#define HI3670_CLK_GATE_A57HPM 162
185#define HI3670_CLK_GATE_A53HPM 163
186#define HI3670_CLK_GATE_PA_A53 164
187#define HI3670_CLK_GATE_PA_A57 165
188#define HI3670_CLK_GATE_PA_G3D 166
189#define HI3670_CLK_GATE_GPUHPM 167
190#define HI3670_CLK_GATE_PERIHPM 168
191#define HI3670_CLK_GATE_AOHPM 169
192#define HI3670_CLK_GATE_UART1 170
193#define HI3670_CLK_GATE_UART4 171
194#define HI3670_PCLK_GATE_UART1 172
195#define HI3670_PCLK_GATE_UART4 173
196#define HI3670_CLK_GATE_UART2 174
197#define HI3670_CLK_GATE_UART5 175
198#define HI3670_PCLK_GATE_UART2 176
199#define HI3670_PCLK_GATE_UART5 177
200#define HI3670_CLK_GATE_UART0 178
201#define HI3670_CLK_GATE_I2C3 179
202#define HI3670_CLK_GATE_I2C4 180
203#define HI3670_CLK_GATE_I2C7 181
204#define HI3670_PCLK_GATE_I2C3 182
205#define HI3670_PCLK_GATE_I2C4 183
206#define HI3670_PCLK_GATE_I2C7 184
207#define HI3670_CLK_GATE_SPI1 185
208#define HI3670_CLK_GATE_SPI4 186
209#define HI3670_PCLK_GATE_SPI1 187
210#define HI3670_PCLK_GATE_SPI4 188
211#define HI3670_CLK_GATE_USB3OTG_REF 189
212#define HI3670_CLK_GATE_USB2PHY_REF 190
213#define HI3670_CLK_GATE_PCIEAUX 191
214#define HI3670_ACLK_GATE_PCIE 192
215#define HI3670_CLK_GATE_MMC1_PCIEAXI 193
216#define HI3670_CLK_GATE_PCIEPHY_REF 194
217#define HI3670_CLK_GATE_PCIE_DEBOUNCE 195
218#define HI3670_CLK_GATE_PCIEIO 196
219#define HI3670_CLK_GATE_PCIE_HP 197
220#define HI3670_CLK_GATE_AO_ASP 198
221#define HI3670_PCLK_GATE_PCTRL 199
222#define HI3670_CLK_CSI_TRANS_GT 200
223#define HI3670_CLK_DSI_TRANS_GT 201
224#define HI3670_CLK_GATE_PWM 202
225#define HI3670_ABB_AUDIO_EN0 203
226#define HI3670_ABB_AUDIO_EN1 204
227#define HI3670_ABB_AUDIO_GT_EN0 205
228#define HI3670_ABB_AUDIO_GT_EN1 206
229#define HI3670_CLK_GATE_DP_AUDIO_PLL_AO 207
230#define HI3670_PERI_VOLT_HOLD 208
231#define HI3670_PERI_VOLT_MIDDLE 209
232#define HI3670_CLK_GATE_ISP_SNCLK0 210
233#define HI3670_CLK_GATE_ISP_SNCLK1 211
234#define HI3670_CLK_GATE_ISP_SNCLK2 212
235#define HI3670_CLK_GATE_RXDPHY0_CFG 213
236#define HI3670_CLK_GATE_RXDPHY1_CFG 214
237#define HI3670_CLK_GATE_RXDPHY2_CFG 215
238#define HI3670_CLK_GATE_TXDPHY0_CFG 216
239#define HI3670_CLK_GATE_TXDPHY0_REF 217
240#define HI3670_CLK_GATE_TXDPHY1_CFG 218
241#define HI3670_CLK_GATE_TXDPHY1_REF 219
242#define HI3670_CLK_GATE_MEDIA_TCXO 220
243
244/* clk in sctrl */
245#define HI3670_CLK_ANDGT_IOPERI 0
246#define HI3670_CLKANDGT_ASP_SUBSYS_PERI 1
247#define HI3670_CLK_ANGT_ASP_SUBSYS 2
248#define HI3670_CLK_MUX_UFS_SUBSYS 3
249#define HI3670_CLK_MUX_CLKOUT0 4
250#define HI3670_CLK_MUX_CLKOUT1 5
251#define HI3670_CLK_MUX_ASP_SUBSYS_PERI 6
252#define HI3670_CLK_MUX_ASP_PLL 7
253#define HI3670_CLK_DIV_AOBUS 8
254#define HI3670_CLK_DIV_UFS_SUBSYS 9
255#define HI3670_CLK_DIV_IOPERI 10
256#define HI3670_CLK_DIV_CLKOUT0_TCXO 11
257#define HI3670_CLK_DIV_CLKOUT1_TCXO 12
258#define HI3670_CLK_ASP_SUBSYS_PERI_DIV 13
259#define HI3670_CLK_DIV_ASP_SUBSYS 14
260#define HI3670_PPLL0_EN_ACPU 15
261#define HI3670_PPLL0_GT_CPU 16
262#define HI3670_CLK_GATE_PPLL0_MEDIA 17
263#define HI3670_PCLK_GPIO18 18
264#define HI3670_PCLK_GPIO19 19
265#define HI3670_CLK_GATE_SPI 20
266#define HI3670_PCLK_GATE_SPI 21
267#define HI3670_CLK_GATE_UFS_SUBSYS 22
268#define HI3670_CLK_GATE_UFSIO_REF 23
269#define HI3670_PCLK_AO_GPIO0 24
270#define HI3670_PCLK_AO_GPIO1 25
271#define HI3670_PCLK_AO_GPIO2 26
272#define HI3670_PCLK_AO_GPIO3 27
273#define HI3670_PCLK_AO_GPIO4 28
274#define HI3670_PCLK_AO_GPIO5 29
275#define HI3670_PCLK_AO_GPIO6 30
276#define HI3670_CLK_GATE_OUT0 31
277#define HI3670_CLK_GATE_OUT1 32
278#define HI3670_PCLK_GATE_SYSCNT 33
279#define HI3670_CLK_GATE_SYSCNT 34
280#define HI3670_CLK_GATE_ASP_SUBSYS_PERI 35
281#define HI3670_CLK_GATE_ASP_SUBSYS 36
282#define HI3670_CLK_GATE_ASP_TCXO 37
283#define HI3670_CLK_GATE_DP_AUDIO_PLL 38
284
285/* clk in pmuctrl */
286#define HI3670_GATE_ABB_192 0
287
288/* clk in pctrl */
289#define HI3670_GATE_UFS_TCXO_EN 0
290#define HI3670_GATE_USB_TCXO_EN 1
291
292/* clk in iomcu */
293#define HI3670_CLK_GATE_I2C0 0
294#define HI3670_CLK_GATE_I2C1 1
295#define HI3670_CLK_GATE_I2C2 2
296#define HI3670_CLK_GATE_SPI0 3
297#define HI3670_CLK_GATE_SPI2 4
298#define HI3670_CLK_GATE_UART3 5
299#define HI3670_CLK_I2C0_GATE_IOMCU 6
300#define HI3670_CLK_I2C1_GATE_IOMCU 7
301#define HI3670_CLK_I2C2_GATE_IOMCU 8
302#define HI3670_CLK_SPI0_GATE_IOMCU 9
303#define HI3670_CLK_SPI2_GATE_IOMCU 10
304#define HI3670_CLK_UART3_GATE_IOMCU 11
305#define HI3670_CLK_GATE_PERI0_IOMCU 12
306
307/* clk in media1 */
308#define HI3670_CLK_GATE_VIVOBUS_ANDGT 0
309#define HI3670_CLK_ANDGT_EDC0 1
310#define HI3670_CLK_ANDGT_LDI0 2
311#define HI3670_CLK_ANDGT_LDI1 3
312#define HI3670_CLK_MMBUF_PLL_ANDGT 4
313#define HI3670_PCLK_MMBUF_ANDGT 5
314#define HI3670_CLK_MUX_VIVOBUS 6
315#define HI3670_CLK_MUX_EDC0 7
316#define HI3670_CLK_MUX_LDI0 8
317#define HI3670_CLK_MUX_LDI1 9
318#define HI3670_CLK_SW_MMBUF 10
319#define HI3670_CLK_DIV_VIVOBUS 11
320#define HI3670_CLK_DIV_EDC0 12
321#define HI3670_CLK_DIV_LDI0 13
322#define HI3670_CLK_DIV_LDI1 14
323#define HI3670_ACLK_DIV_MMBUF 15
324#define HI3670_PCLK_DIV_MMBUF 16
325#define HI3670_ACLK_GATE_NOC_DSS 17
326#define HI3670_PCLK_GATE_NOC_DSS_CFG 18
327#define HI3670_PCLK_GATE_MMBUF_CFG 19
328#define HI3670_PCLK_GATE_DISP_NOC_SUBSYS 20
329#define HI3670_ACLK_GATE_DISP_NOC_SUBSYS 21
330#define HI3670_PCLK_GATE_DSS 22
331#define HI3670_ACLK_GATE_DSS 23
332#define HI3670_CLK_GATE_VIVOBUSFREQ 24
333#define HI3670_CLK_GATE_EDC0 25
334#define HI3670_CLK_GATE_LDI0 26
335#define HI3670_CLK_GATE_LDI1FREQ 27
336#define HI3670_CLK_GATE_BRG 28
337#define HI3670_ACLK_GATE_ASC 29
338#define HI3670_CLK_GATE_DSS_AXI_MM 30
339#define HI3670_CLK_GATE_MMBUF 31
340#define HI3670_PCLK_GATE_MMBUF 32
341#define HI3670_CLK_GATE_ATDIV_VIVO 33
342
343/* clk in media2 */
344#define HI3670_CLK_GATE_VDECFREQ 0
345#define HI3670_CLK_GATE_VENCFREQ 1
346#define HI3670_CLK_GATE_ICSFREQ 2
347
348#endif /* __DT_BINDINGS_CLOCK_HI3670_H */
diff --git a/include/dt-bindings/clock/jz4725b-cgu.h b/include/dt-bindings/clock/jz4725b-cgu.h
new file mode 100644
index 000000000000..460bbeff6ab8
--- /dev/null
+++ b/include/dt-bindings/clock/jz4725b-cgu.h
@@ -0,0 +1,35 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * This header provides clock numbers for the ingenic,jz4725b-cgu DT binding.
4 */
5
6#ifndef __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__
7#define __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__
8
9#define JZ4725B_CLK_EXT 0
10#define JZ4725B_CLK_OSC32K 1
11#define JZ4725B_CLK_PLL 2
12#define JZ4725B_CLK_PLL_HALF 3
13#define JZ4725B_CLK_CCLK 4
14#define JZ4725B_CLK_HCLK 5
15#define JZ4725B_CLK_PCLK 6
16#define JZ4725B_CLK_MCLK 7
17#define JZ4725B_CLK_IPU 8
18#define JZ4725B_CLK_LCD 9
19#define JZ4725B_CLK_I2S 10
20#define JZ4725B_CLK_SPI 11
21#define JZ4725B_CLK_MMC_MUX 12
22#define JZ4725B_CLK_UDC 13
23#define JZ4725B_CLK_UART 14
24#define JZ4725B_CLK_DMA 15
25#define JZ4725B_CLK_ADC 16
26#define JZ4725B_CLK_I2C 17
27#define JZ4725B_CLK_AIC 18
28#define JZ4725B_CLK_MMC0 19
29#define JZ4725B_CLK_MMC1 20
30#define JZ4725B_CLK_BCH 21
31#define JZ4725B_CLK_TCU 22
32#define JZ4725B_CLK_EXT512 23
33#define JZ4725B_CLK_RTC 24
34
35#endif /* __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ */
diff --git a/include/dt-bindings/clock/maxim,max77686.h b/include/dt-bindings/clock/maxim,max77686.h
index 7b28b0905869..af8261dcace1 100644
--- a/include/dt-bindings/clock/maxim,max77686.h
+++ b/include/dt-bindings/clock/maxim,max77686.h
@@ -1,10 +1,7 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (C) 2014 Google, Inc 3 * Copyright (C) 2014 Google, Inc
3 * 4 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Device Tree binding constants clocks for the Maxim 77686 PMIC. 5 * Device Tree binding constants clocks for the Maxim 77686 PMIC.
9 */ 6 */
10 7
diff --git a/include/dt-bindings/clock/maxim,max77802.h b/include/dt-bindings/clock/maxim,max77802.h
index 997312edcbb5..51adcbaed697 100644
--- a/include/dt-bindings/clock/maxim,max77802.h
+++ b/include/dt-bindings/clock/maxim,max77802.h
@@ -1,10 +1,7 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (C) 2014 Google, Inc 3 * Copyright (C) 2014 Google, Inc
3 * 4 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Device Tree binding constants clocks for the Maxim 77802 PMIC. 5 * Device Tree binding constants clocks for the Maxim 77802 PMIC.
9 */ 6 */
10 7
diff --git a/include/dt-bindings/clock/qcom,camcc-sdm845.h b/include/dt-bindings/clock/qcom,camcc-sdm845.h
new file mode 100644
index 000000000000..4f7a2d2320bf
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,camcc-sdm845.h
@@ -0,0 +1,116 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
7#define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
8
9/* CAM_CC clock registers */
10#define CAM_CC_BPS_AHB_CLK 0
11#define CAM_CC_BPS_AREG_CLK 1
12#define CAM_CC_BPS_AXI_CLK 2
13#define CAM_CC_BPS_CLK 3
14#define CAM_CC_BPS_CLK_SRC 4
15#define CAM_CC_CAMNOC_ATB_CLK 5
16#define CAM_CC_CAMNOC_AXI_CLK 6
17#define CAM_CC_CCI_CLK 7
18#define CAM_CC_CCI_CLK_SRC 8
19#define CAM_CC_CPAS_AHB_CLK 9
20#define CAM_CC_CPHY_RX_CLK_SRC 10
21#define CAM_CC_CSI0PHYTIMER_CLK 11
22#define CAM_CC_CSI0PHYTIMER_CLK_SRC 12
23#define CAM_CC_CSI1PHYTIMER_CLK 13
24#define CAM_CC_CSI1PHYTIMER_CLK_SRC 14
25#define CAM_CC_CSI2PHYTIMER_CLK 15
26#define CAM_CC_CSI2PHYTIMER_CLK_SRC 16
27#define CAM_CC_CSI3PHYTIMER_CLK 17
28#define CAM_CC_CSI3PHYTIMER_CLK_SRC 18
29#define CAM_CC_CSIPHY0_CLK 19
30#define CAM_CC_CSIPHY1_CLK 20
31#define CAM_CC_CSIPHY2_CLK 21
32#define CAM_CC_CSIPHY3_CLK 22
33#define CAM_CC_FAST_AHB_CLK_SRC 23
34#define CAM_CC_FD_CORE_CLK 24
35#define CAM_CC_FD_CORE_CLK_SRC 25
36#define CAM_CC_FD_CORE_UAR_CLK 26
37#define CAM_CC_ICP_APB_CLK 27
38#define CAM_CC_ICP_ATB_CLK 28
39#define CAM_CC_ICP_CLK 29
40#define CAM_CC_ICP_CLK_SRC 30
41#define CAM_CC_ICP_CTI_CLK 31
42#define CAM_CC_ICP_TS_CLK 32
43#define CAM_CC_IFE_0_AXI_CLK 33
44#define CAM_CC_IFE_0_CLK 34
45#define CAM_CC_IFE_0_CLK_SRC 35
46#define CAM_CC_IFE_0_CPHY_RX_CLK 36
47#define CAM_CC_IFE_0_CSID_CLK 37
48#define CAM_CC_IFE_0_CSID_CLK_SRC 38
49#define CAM_CC_IFE_0_DSP_CLK 39
50#define CAM_CC_IFE_1_AXI_CLK 40
51#define CAM_CC_IFE_1_CLK 41
52#define CAM_CC_IFE_1_CLK_SRC 42
53#define CAM_CC_IFE_1_CPHY_RX_CLK 43
54#define CAM_CC_IFE_1_CSID_CLK 44
55#define CAM_CC_IFE_1_CSID_CLK_SRC 45
56#define CAM_CC_IFE_1_DSP_CLK 46
57#define CAM_CC_IFE_LITE_CLK 47
58#define CAM_CC_IFE_LITE_CLK_SRC 48
59#define CAM_CC_IFE_LITE_CPHY_RX_CLK 49
60#define CAM_CC_IFE_LITE_CSID_CLK 50
61#define CAM_CC_IFE_LITE_CSID_CLK_SRC 51
62#define CAM_CC_IPE_0_AHB_CLK 52
63#define CAM_CC_IPE_0_AREG_CLK 53
64#define CAM_CC_IPE_0_AXI_CLK 54
65#define CAM_CC_IPE_0_CLK 55
66#define CAM_CC_IPE_0_CLK_SRC 56
67#define CAM_CC_IPE_1_AHB_CLK 57
68#define CAM_CC_IPE_1_AREG_CLK 58
69#define CAM_CC_IPE_1_AXI_CLK 59
70#define CAM_CC_IPE_1_CLK 60
71#define CAM_CC_IPE_1_CLK_SRC 61
72#define CAM_CC_JPEG_CLK 62
73#define CAM_CC_JPEG_CLK_SRC 63
74#define CAM_CC_LRME_CLK 64
75#define CAM_CC_LRME_CLK_SRC 65
76#define CAM_CC_MCLK0_CLK 66
77#define CAM_CC_MCLK0_CLK_SRC 67
78#define CAM_CC_MCLK1_CLK 68
79#define CAM_CC_MCLK1_CLK_SRC 69
80#define CAM_CC_MCLK2_CLK 70
81#define CAM_CC_MCLK2_CLK_SRC 71
82#define CAM_CC_MCLK3_CLK 72
83#define CAM_CC_MCLK3_CLK_SRC 73
84#define CAM_CC_PLL0 74
85#define CAM_CC_PLL0_OUT_EVEN 75
86#define CAM_CC_PLL1 76
87#define CAM_CC_PLL1_OUT_EVEN 77
88#define CAM_CC_PLL2 78
89#define CAM_CC_PLL2_OUT_EVEN 79
90#define CAM_CC_PLL3 80
91#define CAM_CC_PLL3_OUT_EVEN 81
92#define CAM_CC_SLOW_AHB_CLK_SRC 82
93#define CAM_CC_SOC_AHB_CLK 83
94#define CAM_CC_SYS_TMR_CLK 84
95
96/* CAM_CC Resets */
97#define TITAN_CAM_CC_CCI_BCR 0
98#define TITAN_CAM_CC_CPAS_BCR 1
99#define TITAN_CAM_CC_CSI0PHY_BCR 2
100#define TITAN_CAM_CC_CSI1PHY_BCR 3
101#define TITAN_CAM_CC_CSI2PHY_BCR 4
102#define TITAN_CAM_CC_MCLK0_BCR 5
103#define TITAN_CAM_CC_MCLK1_BCR 6
104#define TITAN_CAM_CC_MCLK2_BCR 7
105#define TITAN_CAM_CC_MCLK3_BCR 8
106#define TITAN_CAM_CC_TITAN_TOP_BCR 9
107
108/* CAM_CC GDSCRs */
109#define BPS_GDSC 0
110#define IPE_0_GDSC 1
111#define IPE_1_GDSC 2
112#define IFE_0_GDSC 3
113#define IFE_1_GDSC 4
114#define TITAN_TOP_GDSC 5
115
116#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h
index 75b07cf5eed0..db80f2ee571b 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8996.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h
@@ -235,6 +235,15 @@
235#define GCC_RX1_USB2_CLKREF_CLK 218 235#define GCC_RX1_USB2_CLKREF_CLK 218
236#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219 236#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219
237#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220 237#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220
238#define GCC_EDP_CLKREF_CLK 221
239#define GCC_MSS_CFG_AHB_CLK 222
240#define GCC_MSS_Q6_BIMC_AXI_CLK 223
241#define GCC_MSS_SNOC_AXI_CLK 224
242#define GCC_MSS_MNOC_BIMC_AXI_CLK 225
243#define GCC_DCC_AHB_CLK 226
244#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 227
245#define GCC_MMSS_GPLL0_DIV_CLK 228
246#define GCC_MSS_GPLL0_DIV_CLK 229
238 247
239#define GCC_SYSTEM_NOC_BCR 0 248#define GCC_SYSTEM_NOC_BCR 0
240#define GCC_CONFIG_NOC_BCR 1 249#define GCC_CONFIG_NOC_BCR 1
diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
new file mode 100644
index 000000000000..6ceb55ed72c6
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
@@ -0,0 +1,165 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
7#define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
8
9#define GCC_APSS_AHB_CLK_SRC 0
10#define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC 1
11#define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC 2
12#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 3
13#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 4
14#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 5
15#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 6
16#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 7
17#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 8
18#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 9
19#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 10
20#define GCC_BLSP1_UART0_APPS_CLK_SRC 11
21#define GCC_BLSP1_UART1_APPS_CLK_SRC 12
22#define GCC_BLSP1_UART2_APPS_CLK_SRC 13
23#define GCC_BLSP1_UART3_APPS_CLK_SRC 14
24#define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC 15
25#define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC 16
26#define GCC_BLSP2_UART0_APPS_CLK_SRC 17
27#define GCC_BYTE0_CLK_SRC 18
28#define GCC_EMAC_CLK_SRC 19
29#define GCC_EMAC_PTP_CLK_SRC 20
30#define GCC_ESC0_CLK_SRC 21
31#define GCC_APSS_AHB_CLK 22
32#define GCC_APSS_AXI_CLK 23
33#define GCC_BIMC_APSS_AXI_CLK 24
34#define GCC_BIMC_GFX_CLK 25
35#define GCC_BIMC_MDSS_CLK 26
36#define GCC_BLSP1_AHB_CLK 27
37#define GCC_BLSP1_QUP0_I2C_APPS_CLK 28
38#define GCC_BLSP1_QUP0_SPI_APPS_CLK 29
39#define GCC_BLSP1_QUP1_I2C_APPS_CLK 30
40#define GCC_BLSP1_QUP1_SPI_APPS_CLK 31
41#define GCC_BLSP1_QUP2_I2C_APPS_CLK 32
42#define GCC_BLSP1_QUP2_SPI_APPS_CLK 33
43#define GCC_BLSP1_QUP3_I2C_APPS_CLK 34
44#define GCC_BLSP1_QUP3_SPI_APPS_CLK 35
45#define GCC_BLSP1_QUP4_I2C_APPS_CLK 36
46#define GCC_BLSP1_QUP4_SPI_APPS_CLK 37
47#define GCC_BLSP1_UART0_APPS_CLK 38
48#define GCC_BLSP1_UART1_APPS_CLK 39
49#define GCC_BLSP1_UART2_APPS_CLK 40
50#define GCC_BLSP1_UART3_APPS_CLK 41
51#define GCC_BLSP2_AHB_CLK 42
52#define GCC_BLSP2_QUP0_I2C_APPS_CLK 43
53#define GCC_BLSP2_QUP0_SPI_APPS_CLK 44
54#define GCC_BLSP2_UART0_APPS_CLK 45
55#define GCC_BOOT_ROM_AHB_CLK 46
56#define GCC_DCC_CLK 47
57#define GCC_GENI_IR_H_CLK 48
58#define GCC_ETH_AXI_CLK 49
59#define GCC_ETH_PTP_CLK 50
60#define GCC_ETH_RGMII_CLK 51
61#define GCC_ETH_SLAVE_AHB_CLK 52
62#define GCC_GENI_IR_S_CLK 53
63#define GCC_GP1_CLK 54
64#define GCC_GP2_CLK 55
65#define GCC_GP3_CLK 56
66#define GCC_MDSS_AHB_CLK 57
67#define GCC_MDSS_AXI_CLK 58
68#define GCC_MDSS_BYTE0_CLK 59
69#define GCC_MDSS_ESC0_CLK 60
70#define GCC_MDSS_HDMI_APP_CLK 61
71#define GCC_MDSS_HDMI_PCLK_CLK 62
72#define GCC_MDSS_MDP_CLK 63
73#define GCC_MDSS_PCLK0_CLK 64
74#define GCC_MDSS_VSYNC_CLK 65
75#define GCC_OXILI_AHB_CLK 66
76#define GCC_OXILI_GFX3D_CLK 67
77#define GCC_PCIE_0_AUX_CLK 68
78#define GCC_PCIE_0_CFG_AHB_CLK 69
79#define GCC_PCIE_0_MSTR_AXI_CLK 70
80#define GCC_PCIE_0_PIPE_CLK 71
81#define GCC_PCIE_0_SLV_AXI_CLK 72
82#define GCC_PCNOC_USB2_CLK 73
83#define GCC_PCNOC_USB3_CLK 74
84#define GCC_PDM2_CLK 75
85#define GCC_PDM_AHB_CLK 76
86#define GCC_VSYNC_CLK_SRC 77
87#define GCC_PRNG_AHB_CLK 78
88#define GCC_PWM0_XO512_CLK 79
89#define GCC_PWM1_XO512_CLK 80
90#define GCC_PWM2_XO512_CLK 81
91#define GCC_SDCC1_AHB_CLK 82
92#define GCC_SDCC1_APPS_CLK 83
93#define GCC_SDCC1_ICE_CORE_CLK 84
94#define GCC_SDCC2_AHB_CLK 85
95#define GCC_SDCC2_APPS_CLK 86
96#define GCC_SYS_NOC_USB3_CLK 87
97#define GCC_USB20_MOCK_UTMI_CLK 88
98#define GCC_USB2A_PHY_SLEEP_CLK 89
99#define GCC_USB30_MASTER_CLK 90
100#define GCC_USB30_MOCK_UTMI_CLK 91
101#define GCC_USB30_SLEEP_CLK 92
102#define GCC_USB3_PHY_AUX_CLK 93
103#define GCC_USB3_PHY_PIPE_CLK 94
104#define GCC_USB_HS_PHY_CFG_AHB_CLK 95
105#define GCC_USB_HS_SYSTEM_CLK 96
106#define GCC_GFX3D_CLK_SRC 97
107#define GCC_GP1_CLK_SRC 98
108#define GCC_GP2_CLK_SRC 99
109#define GCC_GP3_CLK_SRC 100
110#define GCC_GPLL0_OUT_MAIN 101
111#define GCC_GPLL1_OUT_MAIN 102
112#define GCC_GPLL3_OUT_MAIN 103
113#define GCC_GPLL4_OUT_MAIN 104
114#define GCC_HDMI_APP_CLK_SRC 105
115#define GCC_HDMI_PCLK_CLK_SRC 106
116#define GCC_MDP_CLK_SRC 107
117#define GCC_PCIE_0_AUX_CLK_SRC 108
118#define GCC_PCIE_0_PIPE_CLK_SRC 109
119#define GCC_PCLK0_CLK_SRC 110
120#define GCC_PDM2_CLK_SRC 111
121#define GCC_SDCC1_APPS_CLK_SRC 112
122#define GCC_SDCC1_ICE_CORE_CLK_SRC 113
123#define GCC_SDCC2_APPS_CLK_SRC 114
124#define GCC_USB20_MOCK_UTMI_CLK_SRC 115
125#define GCC_USB30_MASTER_CLK_SRC 116
126#define GCC_USB30_MOCK_UTMI_CLK_SRC 117
127#define GCC_USB3_PHY_AUX_CLK_SRC 118
128#define GCC_USB_HS_SYSTEM_CLK_SRC 119
129#define GCC_GPLL0_AO_CLK_SRC 120
130#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 122
131#define GCC_GPLL0_AO_OUT_MAIN 123
132#define GCC_GPLL0_SLEEP_CLK_SRC 124
133#define GCC_GPLL6 125
134#define GCC_GPLL6_OUT_AUX 126
135#define GCC_MDSS_MDP_VOTE_CLK 127
136#define GCC_MDSS_ROTATOR_VOTE_CLK 128
137#define GCC_BIMC_GPU_CLK 129
138#define GCC_GTCU_AHB_CLK 130
139#define GCC_GFX_TCU_CLK 131
140#define GCC_GFX_TBU_CLK 132
141#define GCC_SMMU_CFG_CLK 133
142#define GCC_APSS_TCU_CLK 134
143#define GCC_CRYPTO_AHB_CLK 135
144#define GCC_CRYPTO_AXI_CLK 136
145#define GCC_CRYPTO_CLK 137
146#define GCC_MDP_TBU_CLK 138
147#define GCC_QDSS_DAP_CLK 139
148#define GCC_DCC_XO_CLK 140
149
150#define GCC_GENI_IR_BCR 0
151#define GCC_USB_HS_BCR 1
152#define GCC_USB2_HS_PHY_ONLY_BCR 2
153#define GCC_QUSB2_PHY_BCR 3
154#define GCC_USB_HS_PHY_CFG_AHB_BCR 4
155#define GCC_USB2A_PHY_BCR 5
156#define GCC_USB3_PHY_BCR 6
157#define GCC_USB_30_BCR 7
158#define GCC_USB3PHY_PHY_BCR 8
159#define GCC_PCIE_0_BCR 9
160#define GCC_PCIE_0_PHY_BCR 10
161#define GCC_PCIE_0_LINK_DOWN_BCR 11
162#define GCC_PCIEPHY_0_PHY_BCR 12
163#define GCC_EMAC_BCR 13
164
165#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm660.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h
new file mode 100644
index 000000000000..468302282913
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h
@@ -0,0 +1,156 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2018, Craig Tatlor.
5 */
6
7#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H
8#define _DT_BINDINGS_CLK_MSM_GCC_660_H
9
10#define BLSP1_QUP1_I2C_APPS_CLK_SRC 0
11#define BLSP1_QUP1_SPI_APPS_CLK_SRC 1
12#define BLSP1_QUP2_I2C_APPS_CLK_SRC 2
13#define BLSP1_QUP2_SPI_APPS_CLK_SRC 3
14#define BLSP1_QUP3_I2C_APPS_CLK_SRC 4
15#define BLSP1_QUP3_SPI_APPS_CLK_SRC 5
16#define BLSP1_QUP4_I2C_APPS_CLK_SRC 6
17#define BLSP1_QUP4_SPI_APPS_CLK_SRC 7
18#define BLSP1_UART1_APPS_CLK_SRC 8
19#define BLSP1_UART2_APPS_CLK_SRC 9
20#define BLSP2_QUP1_I2C_APPS_CLK_SRC 10
21#define BLSP2_QUP1_SPI_APPS_CLK_SRC 11
22#define BLSP2_QUP2_I2C_APPS_CLK_SRC 12
23#define BLSP2_QUP2_SPI_APPS_CLK_SRC 13
24#define BLSP2_QUP3_I2C_APPS_CLK_SRC 14
25#define BLSP2_QUP3_SPI_APPS_CLK_SRC 15
26#define BLSP2_QUP4_I2C_APPS_CLK_SRC 16
27#define BLSP2_QUP4_SPI_APPS_CLK_SRC 17
28#define BLSP2_UART1_APPS_CLK_SRC 18
29#define BLSP2_UART2_APPS_CLK_SRC 19
30#define GCC_AGGRE2_UFS_AXI_CLK 20
31#define GCC_AGGRE2_USB3_AXI_CLK 21
32#define GCC_BIMC_GFX_CLK 22
33#define GCC_BIMC_HMSS_AXI_CLK 23
34#define GCC_BIMC_MSS_Q6_AXI_CLK 24
35#define GCC_BLSP1_AHB_CLK 25
36#define GCC_BLSP1_QUP1_I2C_APPS_CLK 26
37#define GCC_BLSP1_QUP1_SPI_APPS_CLK 27
38#define GCC_BLSP1_QUP2_I2C_APPS_CLK 28
39#define GCC_BLSP1_QUP2_SPI_APPS_CLK 29
40#define GCC_BLSP1_QUP3_I2C_APPS_CLK 30
41#define GCC_BLSP1_QUP3_SPI_APPS_CLK 31
42#define GCC_BLSP1_QUP4_I2C_APPS_CLK 32
43#define GCC_BLSP1_QUP4_SPI_APPS_CLK 33
44#define GCC_BLSP1_UART1_APPS_CLK 34
45#define GCC_BLSP1_UART2_APPS_CLK 35
46#define GCC_BLSP2_AHB_CLK 36
47#define GCC_BLSP2_QUP1_I2C_APPS_CLK 37
48#define GCC_BLSP2_QUP1_SPI_APPS_CLK 38
49#define GCC_BLSP2_QUP2_I2C_APPS_CLK 39
50#define GCC_BLSP2_QUP2_SPI_APPS_CLK 40
51#define GCC_BLSP2_QUP3_I2C_APPS_CLK 41
52#define GCC_BLSP2_QUP3_SPI_APPS_CLK 42
53#define GCC_BLSP2_QUP4_I2C_APPS_CLK 43
54#define GCC_BLSP2_QUP4_SPI_APPS_CLK 44
55#define GCC_BLSP2_UART1_APPS_CLK 45
56#define GCC_BLSP2_UART2_APPS_CLK 46
57#define GCC_BOOT_ROM_AHB_CLK 47
58#define GCC_CFG_NOC_USB2_AXI_CLK 48
59#define GCC_CFG_NOC_USB3_AXI_CLK 49
60#define GCC_DCC_AHB_CLK 50
61#define GCC_GP1_CLK 51
62#define GCC_GP2_CLK 52
63#define GCC_GP3_CLK 53
64#define GCC_GPU_BIMC_GFX_CLK 54
65#define GCC_GPU_CFG_AHB_CLK 55
66#define GCC_GPU_GPLL0_CLK 56
67#define GCC_GPU_GPLL0_DIV_CLK 57
68#define GCC_HMSS_DVM_BUS_CLK 58
69#define GCC_HMSS_RBCPR_CLK 59
70#define GCC_MMSS_GPLL0_CLK 60
71#define GCC_MMSS_GPLL0_DIV_CLK 61
72#define GCC_MMSS_NOC_CFG_AHB_CLK 62
73#define GCC_MMSS_SYS_NOC_AXI_CLK 63
74#define GCC_MSS_CFG_AHB_CLK 64
75#define GCC_MSS_GPLL0_DIV_CLK 65
76#define GCC_MSS_MNOC_BIMC_AXI_CLK 66
77#define GCC_MSS_Q6_BIMC_AXI_CLK 67
78#define GCC_MSS_SNOC_AXI_CLK 68
79#define GCC_PDM2_CLK 69
80#define GCC_PDM_AHB_CLK 70
81#define GCC_PRNG_AHB_CLK 71
82#define GCC_QSPI_AHB_CLK 72
83#define GCC_QSPI_SER_CLK 73
84#define GCC_SDCC1_AHB_CLK 74
85#define GCC_SDCC1_APPS_CLK 75
86#define GCC_SDCC1_ICE_CORE_CLK 76
87#define GCC_SDCC2_AHB_CLK 77
88#define GCC_SDCC2_APPS_CLK 78
89#define GCC_UFS_AHB_CLK 79
90#define GCC_UFS_AXI_CLK 80
91#define GCC_UFS_CLKREF_CLK 81
92#define GCC_UFS_ICE_CORE_CLK 82
93#define GCC_UFS_PHY_AUX_CLK 83
94#define GCC_UFS_RX_SYMBOL_0_CLK 84
95#define GCC_UFS_RX_SYMBOL_1_CLK 85
96#define GCC_UFS_TX_SYMBOL_0_CLK 86
97#define GCC_UFS_UNIPRO_CORE_CLK 87
98#define GCC_USB20_MASTER_CLK 88
99#define GCC_USB20_MOCK_UTMI_CLK 89
100#define GCC_USB20_SLEEP_CLK 90
101#define GCC_USB30_MASTER_CLK 91
102#define GCC_USB30_MOCK_UTMI_CLK 92
103#define GCC_USB30_SLEEP_CLK 93
104#define GCC_USB3_CLKREF_CLK 94
105#define GCC_USB3_PHY_AUX_CLK 95
106#define GCC_USB3_PHY_PIPE_CLK 96
107#define GCC_USB_PHY_CFG_AHB2PHY_CLK 97
108#define GP1_CLK_SRC 98
109#define GP2_CLK_SRC 99
110#define GP3_CLK_SRC 100
111#define GPLL0 101
112#define GPLL0_EARLY 102
113#define GPLL1 103
114#define GPLL1_EARLY 104
115#define GPLL4 105
116#define GPLL4_EARLY 106
117#define HMSS_GPLL0_CLK_SRC 107
118#define HMSS_GPLL4_CLK_SRC 108
119#define HMSS_RBCPR_CLK_SRC 109
120#define PDM2_CLK_SRC 110
121#define QSPI_SER_CLK_SRC 111
122#define SDCC1_APPS_CLK_SRC 112
123#define SDCC1_ICE_CORE_CLK_SRC 113
124#define SDCC2_APPS_CLK_SRC 114
125#define UFS_AXI_CLK_SRC 115
126#define UFS_ICE_CORE_CLK_SRC 116
127#define UFS_PHY_AUX_CLK_SRC 117
128#define UFS_UNIPRO_CORE_CLK_SRC 118
129#define USB20_MASTER_CLK_SRC 119
130#define USB20_MOCK_UTMI_CLK_SRC 120
131#define USB30_MASTER_CLK_SRC 121
132#define USB30_MOCK_UTMI_CLK_SRC 122
133#define USB3_PHY_AUX_CLK_SRC 123
134#define GPLL0_OUT_MSSCC 124
135#define GCC_UFS_AXI_HW_CTL_CLK 125
136#define GCC_UFS_ICE_CORE_HW_CTL_CLK 126
137#define GCC_UFS_PHY_AUX_HW_CTL_CLK 127
138#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 128
139#define GCC_RX0_USB2_CLKREF_CLK 129
140#define GCC_RX1_USB2_CLKREF_CLK 130
141
142#define PCIE_0_GDSC 0
143#define UFS_GDSC 1
144#define USB_30_GDSC 2
145
146#define GCC_QUSB2PHY_PRIM_BCR 0
147#define GCC_QUSB2PHY_SEC_BCR 1
148#define GCC_UFS_BCR 2
149#define GCC_USB3_DP_PHY_BCR 3
150#define GCC_USB3_PHY_BCR 4
151#define GCC_USB3PHY_PHY_BCR 5
152#define GCC_USB_20_BCR 6
153#define GCC_USB_30_BCR 7
154#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8
155
156#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h b/include/dt-bindings/clock/qcom,gcc-sdm845.h
index f96fc2dbf60e..b8eae5a76503 100644
--- a/include/dt-bindings/clock/qcom,gcc-sdm845.h
+++ b/include/dt-bindings/clock/qcom,gcc-sdm845.h
@@ -194,6 +194,9 @@
194#define GPLL4 184 194#define GPLL4 184
195#define GCC_CPUSS_DVM_BUS_CLK 185 195#define GCC_CPUSS_DVM_BUS_CLK 185
196#define GCC_CPUSS_GNOC_CLK 186 196#define GCC_CPUSS_GNOC_CLK 186
197#define GCC_QSPI_CORE_CLK_SRC 187
198#define GCC_QSPI_CORE_CLK 188
199#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189
197 200
198/* GCC Resets */ 201/* GCC Resets */
199#define GCC_MMSS_BCR 0 202#define GCC_MMSS_BCR 0
diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h
index 0dcb3e87d44c..a267ac250143 100644
--- a/include/dt-bindings/clock/r7s72100-clock.h
+++ b/include/dt-bindings/clock/r7s72100-clock.h
@@ -1,10 +1,7 @@
1/* 1/* SPDX-License-Identifier: GPL-2.0
2 *
2 * Copyright (C) 2014 Renesas Solutions Corp. 3 * Copyright (C) 2014 Renesas Solutions Corp.
3 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> 4 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 */ 5 */
9 6
10#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__ 7#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__
diff --git a/include/dt-bindings/clock/r7s9210-cpg-mssr.h b/include/dt-bindings/clock/r7s9210-cpg-mssr.h
new file mode 100644
index 000000000000..b6f85ca149aa
--- /dev/null
+++ b/include/dt-bindings/clock/r7s9210-cpg-mssr.h
@@ -0,0 +1,20 @@
1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright (C) 2018 Renesas Electronics Corp.
4 *
5 */
6
7#ifndef __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__
8#define __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__
9
10#include <dt-bindings/clock/renesas-cpg-mssr.h>
11
12/* R7S9210 CPG Core Clocks */
13#define R7S9210_CLK_I 0
14#define R7S9210_CLK_G 1
15#define R7S9210_CLK_B 2
16#define R7S9210_CLK_P1 3
17#define R7S9210_CLK_P1C 4
18#define R7S9210_CLK_P0 5
19
20#endif /* __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7743-cpg-mssr.h b/include/dt-bindings/clock/r8a7743-cpg-mssr.h
index e1d1f3c6a99e..3ba936029d9f 100644
--- a/include/dt-bindings/clock/r8a7743-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a7743-cpg-mssr.h
@@ -1,10 +1,6 @@
1/* 1/* SPDX-License-Identifier: GPL-2.0+
2 * Copyright (C) 2016 Cogent Embedded Inc.
3 * 2 *
4 * This program is free software; you can redistribute it and/or modify 3 * Copyright (C) 2016 Cogent Embedded Inc.
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */ 4 */
9#ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ 5#ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
10#define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ 6#define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
diff --git a/include/dt-bindings/clock/r8a7744-cpg-mssr.h b/include/dt-bindings/clock/r8a7744-cpg-mssr.h
new file mode 100644
index 000000000000..2690be0c3e22
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7744-cpg-mssr.h
@@ -0,0 +1,39 @@
1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright (C) 2018 Renesas Electronics Corp.
4 */
5#ifndef __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__
6#define __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__
7
8#include <dt-bindings/clock/renesas-cpg-mssr.h>
9
10/* r8a7744 CPG Core Clocks */
11#define R8A7744_CLK_Z 0
12#define R8A7744_CLK_ZG 1
13#define R8A7744_CLK_ZTR 2
14#define R8A7744_CLK_ZTRD2 3
15#define R8A7744_CLK_ZT 4
16#define R8A7744_CLK_ZX 5
17#define R8A7744_CLK_ZS 6
18#define R8A7744_CLK_HP 7
19#define R8A7744_CLK_B 9
20#define R8A7744_CLK_LB 10
21#define R8A7744_CLK_P 11
22#define R8A7744_CLK_CL 12
23#define R8A7744_CLK_M2 13
24#define R8A7744_CLK_ZB3 15
25#define R8A7744_CLK_ZB3D2 16
26#define R8A7744_CLK_DDR 17
27#define R8A7744_CLK_SDH 18
28#define R8A7744_CLK_SD0 19
29#define R8A7744_CLK_SD2 20
30#define R8A7744_CLK_SD3 21
31#define R8A7744_CLK_MMC0 22
32#define R8A7744_CLK_MP 23
33#define R8A7744_CLK_QSPI 26
34#define R8A7744_CLK_CP 27
35#define R8A7744_CLK_RCAN 28
36#define R8A7744_CLK_R 29
37#define R8A7744_CLK_OSC 30
38
39#endif /* __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7745-cpg-mssr.h b/include/dt-bindings/clock/r8a7745-cpg-mssr.h
index 56ad6f0c6760..f81066c9d192 100644
--- a/include/dt-bindings/clock/r8a7745-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a7745-cpg-mssr.h
@@ -1,10 +1,6 @@
1/* 1/* SPDX-License-Identifier: GPL-2.0+
2 * Copyright (C) 2016 Cogent Embedded Inc.
3 * 2 *
4 * This program is free software; you can redistribute it and/or modify 3 * Copyright (C) 2016 Cogent Embedded Inc.
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */ 4 */
9#ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ 5#ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
10#define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ 6#define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
diff --git a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
new file mode 100644
index 000000000000..9bc5d45ff4b5
--- /dev/null
+++ b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
@@ -0,0 +1,58 @@
1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright (C) 2018 Renesas Electronics Corp.
4 */
5#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
6#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
7
8#include <dt-bindings/clock/renesas-cpg-mssr.h>
9
10/* r8a774a1 CPG Core Clocks */
11#define R8A774A1_CLK_Z 0
12#define R8A774A1_CLK_Z2 1
13#define R8A774A1_CLK_ZG 2
14#define R8A774A1_CLK_ZTR 3
15#define R8A774A1_CLK_ZTRD2 4
16#define R8A774A1_CLK_ZT 5
17#define R8A774A1_CLK_ZX 6
18#define R8A774A1_CLK_S0D1 7
19#define R8A774A1_CLK_S0D2 8
20#define R8A774A1_CLK_S0D3 9
21#define R8A774A1_CLK_S0D4 10
22#define R8A774A1_CLK_S0D6 11
23#define R8A774A1_CLK_S0D8 12
24#define R8A774A1_CLK_S0D12 13
25#define R8A774A1_CLK_S1D2 14
26#define R8A774A1_CLK_S1D4 15
27#define R8A774A1_CLK_S2D1 16
28#define R8A774A1_CLK_S2D2 17
29#define R8A774A1_CLK_S2D4 18
30#define R8A774A1_CLK_S3D1 19
31#define R8A774A1_CLK_S3D2 20
32#define R8A774A1_CLK_S3D4 21
33#define R8A774A1_CLK_LB 22
34#define R8A774A1_CLK_CL 23
35#define R8A774A1_CLK_ZB3 24
36#define R8A774A1_CLK_ZB3D2 25
37#define R8A774A1_CLK_ZB3D4 26
38#define R8A774A1_CLK_CR 27
39#define R8A774A1_CLK_CRD2 28
40#define R8A774A1_CLK_SD0H 29
41#define R8A774A1_CLK_SD0 30
42#define R8A774A1_CLK_SD1H 31
43#define R8A774A1_CLK_SD1 32
44#define R8A774A1_CLK_SD2H 33
45#define R8A774A1_CLK_SD2 34
46#define R8A774A1_CLK_SD3H 35
47#define R8A774A1_CLK_SD3 36
48#define R8A774A1_CLK_RPC 37
49#define R8A774A1_CLK_RPCD2 38
50#define R8A774A1_CLK_MSO 39
51#define R8A774A1_CLK_HDMI 40
52#define R8A774A1_CLK_CSI0 41
53#define R8A774A1_CLK_CP 42
54#define R8A774A1_CLK_CPEX 43
55#define R8A774A1_CLK_R 44
56#define R8A774A1_CLK_OSC 45
57
58#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a774c0-cpg-mssr.h b/include/dt-bindings/clock/r8a774c0-cpg-mssr.h
new file mode 100644
index 000000000000..8fe51b6aca28
--- /dev/null
+++ b/include/dt-bindings/clock/r8a774c0-cpg-mssr.h
@@ -0,0 +1,60 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2018 Renesas Electronics Corp.
4 */
5#ifndef __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
6#define __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
7
8#include <dt-bindings/clock/renesas-cpg-mssr.h>
9
10/* r8a774c0 CPG Core Clocks */
11#define R8A774C0_CLK_Z2 0
12#define R8A774C0_CLK_ZG 1
13#define R8A774C0_CLK_ZTR 2
14#define R8A774C0_CLK_ZT 3
15#define R8A774C0_CLK_ZX 4
16#define R8A774C0_CLK_S0D1 5
17#define R8A774C0_CLK_S0D3 6
18#define R8A774C0_CLK_S0D6 7
19#define R8A774C0_CLK_S0D12 8
20#define R8A774C0_CLK_S0D24 9
21#define R8A774C0_CLK_S1D1 10
22#define R8A774C0_CLK_S1D2 11
23#define R8A774C0_CLK_S1D4 12
24#define R8A774C0_CLK_S2D1 13
25#define R8A774C0_CLK_S2D2 14
26#define R8A774C0_CLK_S2D4 15
27#define R8A774C0_CLK_S3D1 16
28#define R8A774C0_CLK_S3D2 17
29#define R8A774C0_CLK_S3D4 18
30#define R8A774C0_CLK_S0D6C 19
31#define R8A774C0_CLK_S3D1C 20
32#define R8A774C0_CLK_S3D2C 21
33#define R8A774C0_CLK_S3D4C 22
34#define R8A774C0_CLK_LB 23
35#define R8A774C0_CLK_CL 24
36#define R8A774C0_CLK_ZB3 25
37#define R8A774C0_CLK_ZB3D2 26
38#define R8A774C0_CLK_CR 27
39#define R8A774C0_CLK_CRD2 28
40#define R8A774C0_CLK_SD0H 29
41#define R8A774C0_CLK_SD0 30
42#define R8A774C0_CLK_SD1H 31
43#define R8A774C0_CLK_SD1 32
44#define R8A774C0_CLK_SD3H 33
45#define R8A774C0_CLK_SD3 34
46#define R8A774C0_CLK_RPC 35
47#define R8A774C0_CLK_RPCD2 36
48#define R8A774C0_CLK_ZA2 37
49#define R8A774C0_CLK_ZA8 38
50#define R8A774C0_CLK_Z2D 39
51#define R8A774C0_CLK_MSO 40
52#define R8A774C0_CLK_R 41
53#define R8A774C0_CLK_OSC 42
54#define R8A774C0_CLK_LV0 43
55#define R8A774C0_CLK_LV1 44
56#define R8A774C0_CLK_CSI0 45
57#define R8A774C0_CLK_CP 46
58#define R8A774C0_CLK_CPEX 47
59
60#endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7790-cpg-mssr.h b/include/dt-bindings/clock/r8a7790-cpg-mssr.h
index 1625b8bf3482..c5955b56b36d 100644
--- a/include/dt-bindings/clock/r8a7790-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a7790-cpg-mssr.h
@@ -1,10 +1,6 @@
1/* 1/* SPDX-License-Identifier: GPL-2.0+
2 * Copyright (C) 2015 Renesas Electronics Corp.
3 * 2 *
4 * This program is free software; you can redistribute it and/or modify 3 * Copyright (C) 2015 Renesas Electronics Corp.
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */ 4 */
9 5
10#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ 6#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
diff --git a/include/dt-bindings/clock/r8a7791-cpg-mssr.h b/include/dt-bindings/clock/r8a7791-cpg-mssr.h
index e8823410c01c..aadd06c566c0 100644
--- a/include/dt-bindings/clock/r8a7791-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a7791-cpg-mssr.h
@@ -1,10 +1,6 @@
1/* 1/* SPDX-License-Identifier: GPL-2.0+
2 * Copyright (C) 2015 Renesas Electronics Corp.
3 * 2 *
4 * This program is free software; you can redistribute it and/or modify 3 * Copyright (C) 2015 Renesas Electronics Corp.
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */ 4 */
9 5
10#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ 6#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
diff --git a/include/dt-bindings/clock/r8a7792-cpg-mssr.h b/include/dt-bindings/clock/r8a7792-cpg-mssr.h
index 72ce85cb2f94..829c44db0271 100644
--- a/include/dt-bindings/clock/r8a7792-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a7792-cpg-mssr.h
@@ -1,10 +1,6 @@
1/* 1/* SPDX-License-Identifier: GPL-2.0+
2 * Copyright (C) 2015 Renesas Electronics Corp.
3 * 2 *
4 * This program is free software; you can redistribute it and/or modify 3 * Copyright (C) 2015 Renesas Electronics Corp.
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */ 4 */
9 5
10#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ 6#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
diff --git a/include/dt-bindings/clock/r8a7793-clock.h b/include/dt-bindings/clock/r8a7793-clock.h
index 7318d45d4e7e..49c66d8ed178 100644
--- a/include/dt-bindings/clock/r8a7793-clock.h
+++ b/include/dt-bindings/clock/r8a7793-clock.h
@@ -1,16 +1,8 @@
1/* 1/* SPDX-License-Identifier: GPL-2.0
2 *
2 * r8a7793 clock definition 3 * r8a7793 clock definition
3 * 4 *
4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * Copyright (C) 2014 Renesas Electronics Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */ 6 */
15 7
16#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__ 8#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__
diff --git a/include/dt-bindings/clock/r8a7793-cpg-mssr.h b/include/dt-bindings/clock/r8a7793-cpg-mssr.h
index 8809b0f62d61..d1ff646c31f2 100644
--- a/include/dt-bindings/clock/r8a7793-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a7793-cpg-mssr.h
@@ -1,10 +1,6 @@
1/* 1/* SPDX-License-Identifier: GPL-2.0+
2 * Copyright (C) 2015 Renesas Electronics Corp.
3 * 2 *
4 * This program is free software; you can redistribute it and/or modify 3 * Copyright (C) 2015 Renesas Electronics Corp.
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */ 4 */
9 5
10#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ 6#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h
index 93e99c3ffc8d..649f005782d0 100644
--- a/include/dt-bindings/clock/r8a7794-clock.h
+++ b/include/dt-bindings/clock/r8a7794-clock.h
@@ -1,11 +1,7 @@
1/* 1/* SPDX-License-Identifier: GPL-2.0+
2 *
2 * Copyright (C) 2014 Renesas Electronics Corporation 3 * Copyright (C) 2014 Renesas Electronics Corporation
3 * Copyright 2013 Ideas On Board SPRL 4 * Copyright 2013 Ideas On Board SPRL
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */ 5 */
10 6
11#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__ 7#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
diff --git a/include/dt-bindings/clock/r8a7794-cpg-mssr.h b/include/dt-bindings/clock/r8a7794-cpg-mssr.h
index 9d720311ae3a..6314e23b51af 100644
--- a/include/dt-bindings/clock/r8a7794-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a7794-cpg-mssr.h
@@ -1,10 +1,6 @@
1/* 1/* SPDX-License-Identifier: GPL-2.0+
2 * Copyright (C) 2015 Renesas Electronics Corp.
3 * 2 *
4 * This program is free software; you can redistribute it and/or modify 3 * Copyright (C) 2015 Renesas Electronics Corp.
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */ 4 */
9 5
10#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ 6#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
index f047eaf261f3..948389641565 100644
--- a/include/dt-bindings/clock/r8a7795-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
@@ -1,10 +1,6 @@
1/* 1/* SPDX-License-Identifier: GPL-2.0+
2 * Copyright (C) 2015 Renesas Electronics Corp.
3 * 2 *
4 * This program is free software; you can redistribute it and/or modify 3 * Copyright (C) 2015 Renesas Electronics Corp.
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */ 4 */
9#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ 5#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
10#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ 6#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
diff --git a/include/dt-bindings/clock/r8a7796-cpg-mssr.h b/include/dt-bindings/clock/r8a7796-cpg-mssr.h
index 1e5942695f0d..e6087f2f7e3a 100644
--- a/include/dt-bindings/clock/r8a7796-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a7796-cpg-mssr.h
@@ -1,10 +1,6 @@
1/* 1/* SPDX-License-Identifier: GPL-2.0+
2 * Copyright (C) 2016 Renesas Electronics Corp.
3 * 2 *
4 * This program is free software; you can redistribute it and/or modify 3 * Copyright (C) 2016 Renesas Electronics Corp.
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */ 4 */
9#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ 5#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
10#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ 6#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
diff --git a/include/dt-bindings/clock/r8a77970-cpg-mssr.h b/include/dt-bindings/clock/r8a77970-cpg-mssr.h
index 4146395595b1..6145ebe66361 100644
--- a/include/dt-bindings/clock/r8a77970-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a77970-cpg-mssr.h
@@ -1,11 +1,7 @@
1/* 1/* SPDX-License-Identifier: GPL-2.0+
2 *
2 * Copyright (C) 2016 Renesas Electronics Corp. 3 * Copyright (C) 2016 Renesas Electronics Corp.
3 * Copyright (C) 2017 Cogent Embedded, Inc. 4 * Copyright (C) 2017 Cogent Embedded, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */ 5 */
10#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ 6#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
11#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ 7#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
diff --git a/include/dt-bindings/clock/r8a77995-cpg-mssr.h b/include/dt-bindings/clock/r8a77995-cpg-mssr.h
index 4e8ae3dee590..1eb11acfa563 100644
--- a/include/dt-bindings/clock/r8a77995-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a77995-cpg-mssr.h
@@ -1,10 +1,6 @@
1/* 1/* SPDX-License-Identifier: GPL-2.0+
2 * Copyright (C) 2017 Glider bvba
3 * 2 *
4 * This program is free software; you can redistribute it and/or modify 3 * Copyright (C) 2017 Glider bvba
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */ 4 */
9#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ 5#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
10#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ 6#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
diff --git a/include/dt-bindings/clock/renesas-cpg-mssr.h b/include/dt-bindings/clock/renesas-cpg-mssr.h
index 569a3cc33ffb..8169ad063f0a 100644
--- a/include/dt-bindings/clock/renesas-cpg-mssr.h
+++ b/include/dt-bindings/clock/renesas-cpg-mssr.h
@@ -1,10 +1,6 @@
1/* 1/* SPDX-License-Identifier: GPL-2.0+
2 * Copyright (C) 2015 Renesas Electronics Corp.
3 * 2 *
4 * This program is free software; you can redistribute it and/or modify 3 * Copyright (C) 2015 Renesas Electronics Corp.
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */ 4 */
9#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ 5#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
10#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ 6#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
diff --git a/include/dt-bindings/clock/s3c2410.h b/include/dt-bindings/clock/s3c2410.h
index 352a7673fc69..0fb65c3f2f59 100644
--- a/include/dt-bindings/clock/s3c2410.h
+++ b/include/dt-bindings/clock/s3c2410.h
@@ -1,10 +1,7 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> 3 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
3 * 4 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Device Tree binding constants clock controllers of Samsung S3C2410 and later. 5 * Device Tree binding constants clock controllers of Samsung S3C2410 and later.
9 */ 6 */
10 7
diff --git a/include/dt-bindings/clock/s3c2412.h b/include/dt-bindings/clock/s3c2412.h
index aac1dcfda81c..b4656156cc0f 100644
--- a/include/dt-bindings/clock/s3c2412.h
+++ b/include/dt-bindings/clock/s3c2412.h
@@ -1,10 +1,7 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> 3 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
3 * 4 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Device Tree binding constants clock controllers of Samsung S3C2412. 5 * Device Tree binding constants clock controllers of Samsung S3C2412.
9 */ 6 */
10 7
diff --git a/include/dt-bindings/clock/s3c2443.h b/include/dt-bindings/clock/s3c2443.h
index f3ba68a25ecb..a9d2f105d536 100644
--- a/include/dt-bindings/clock/s3c2443.h
+++ b/include/dt-bindings/clock/s3c2443.h
@@ -1,10 +1,7 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> 3 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
3 * 4 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Device Tree binding constants clock controllers of Samsung S3C2443 and later. 5 * Device Tree binding constants clock controllers of Samsung S3C2443 and later.
9 */ 6 */
10 7
diff --git a/include/dt-bindings/clock/samsung,s2mps11.h b/include/dt-bindings/clock/samsung,s2mps11.h
index b903d7de27c9..5ece35d429ff 100644
--- a/include/dt-bindings/clock/samsung,s2mps11.h
+++ b/include/dt-bindings/clock/samsung,s2mps11.h
@@ -1,10 +1,7 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (C) 2015 Markus Reichl 3 * Copyright (C) 2015 Markus Reichl
3 * 4 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Device Tree binding constants clocks for the Samsung S2MPS11 PMIC. 5 * Device Tree binding constants clocks for the Samsung S2MPS11 PMIC.
9 */ 6 */
10 7
diff --git a/include/dt-bindings/clock/samsung,s3c64xx-clock.h b/include/dt-bindings/clock/samsung,s3c64xx-clock.h
index ad95c7f50090..19d233f37e2f 100644
--- a/include/dt-bindings/clock/samsung,s3c64xx-clock.h
+++ b/include/dt-bindings/clock/samsung,s3c64xx-clock.h
@@ -1,12 +1,9 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com> 3 * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
3 * 4 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Device Tree binding constants for Samsung S3C64xx clock controller. 5 * Device Tree binding constants for Samsung S3C64xx clock controller.
9*/ 6 */
10 7
11#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H 8#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H
12#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H 9#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H
diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h
index d66432c6e675..a8ac4cfcdcbc 100644
--- a/include/dt-bindings/clock/sun50i-a64-ccu.h
+++ b/include/dt-bindings/clock/sun50i-a64-ccu.h
@@ -43,6 +43,7 @@
43#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ 43#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
44#define _DT_BINDINGS_CLK_SUN50I_A64_H_ 44#define _DT_BINDINGS_CLK_SUN50I_A64_H_
45 45
46#define CLK_PLL_VIDEO0 7
46#define CLK_PLL_PERIPH0 11 47#define CLK_PLL_PERIPH0 11
47 48
48#define CLK_BUS_MIPI_DSI 28 49#define CLK_BUS_MIPI_DSI 28
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 08b1aa70a38d..60c51871b04b 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -119,6 +119,11 @@ struct clk_duty {
119 * Called with enable_lock held. This function must not 119 * Called with enable_lock held. This function must not
120 * sleep. 120 * sleep.
121 * 121 *
122 * @save_context: Save the context of the clock in prepration for poweroff.
123 *
124 * @restore_context: Restore the context of the clock after a restoration
125 * of power.
126 *
122 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The 127 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
123 * parent rate is an input parameter. It is up to the caller to 128 * parent rate is an input parameter. It is up to the caller to
124 * ensure that the prepare_mutex is held across this call. 129 * ensure that the prepare_mutex is held across this call.
@@ -223,6 +228,8 @@ struct clk_ops {
223 void (*disable)(struct clk_hw *hw); 228 void (*disable)(struct clk_hw *hw);
224 int (*is_enabled)(struct clk_hw *hw); 229 int (*is_enabled)(struct clk_hw *hw);
225 void (*disable_unused)(struct clk_hw *hw); 230 void (*disable_unused)(struct clk_hw *hw);
231 int (*save_context)(struct clk_hw *hw);
232 void (*restore_context)(struct clk_hw *hw);
226 unsigned long (*recalc_rate)(struct clk_hw *hw, 233 unsigned long (*recalc_rate)(struct clk_hw *hw,
227 unsigned long parent_rate); 234 unsigned long parent_rate);
228 long (*round_rate)(struct clk_hw *hw, unsigned long rate, 235 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
@@ -1011,5 +1018,7 @@ static inline void clk_writel(u32 val, u32 __iomem *reg)
1011 1018
1012#endif /* platform dependent I/O accessors */ 1019#endif /* platform dependent I/O accessors */
1013 1020
1021void clk_gate_restore_context(struct clk_hw *hw);
1022
1014#endif /* CONFIG_COMMON_CLK */ 1023#endif /* CONFIG_COMMON_CLK */
1015#endif /* CLK_PROVIDER_H */ 1024#endif /* CLK_PROVIDER_H */
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 4f750c481b82..a7773b5c0b9f 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -312,7 +312,26 @@ struct clk *clk_get(struct device *dev, const char *id);
312 */ 312 */
313int __must_check clk_bulk_get(struct device *dev, int num_clks, 313int __must_check clk_bulk_get(struct device *dev, int num_clks,
314 struct clk_bulk_data *clks); 314 struct clk_bulk_data *clks);
315 315/**
316 * clk_bulk_get_all - lookup and obtain all available references to clock
317 * producer.
318 * @dev: device for clock "consumer"
319 * @clks: pointer to the clk_bulk_data table of consumer
320 *
321 * This helper function allows drivers to get all clk consumers in one
322 * operation. If any of the clk cannot be acquired then any clks
323 * that were obtained will be freed before returning to the caller.
324 *
325 * Returns a positive value for the number of clocks obtained while the
326 * clock references are stored in the clk_bulk_data table in @clks field.
327 * Returns 0 if there're none and a negative value if something failed.
328 *
329 * Drivers must assume that the clock source is not enabled.
330 *
331 * clk_bulk_get should not be called from within interrupt context.
332 */
333int __must_check clk_bulk_get_all(struct device *dev,
334 struct clk_bulk_data **clks);
316/** 335/**
317 * devm_clk_bulk_get - managed get multiple clk consumers 336 * devm_clk_bulk_get - managed get multiple clk consumers
318 * @dev: device for clock "consumer" 337 * @dev: device for clock "consumer"
@@ -327,6 +346,22 @@ int __must_check clk_bulk_get(struct device *dev, int num_clks,
327 */ 346 */
328int __must_check devm_clk_bulk_get(struct device *dev, int num_clks, 347int __must_check devm_clk_bulk_get(struct device *dev, int num_clks,
329 struct clk_bulk_data *clks); 348 struct clk_bulk_data *clks);
349/**
350 * devm_clk_bulk_get_all - managed get multiple clk consumers
351 * @dev: device for clock "consumer"
352 * @clks: pointer to the clk_bulk_data table of consumer
353 *
354 * Returns a positive value for the number of clocks obtained while the
355 * clock references are stored in the clk_bulk_data table in @clks field.
356 * Returns 0 if there're none and a negative value if something failed.
357 *
358 * This helper function allows drivers to get several clk
359 * consumers in one operation with management, the clks will
360 * automatically be freed when the device is unbound.
361 */
362
363int __must_check devm_clk_bulk_get_all(struct device *dev,
364 struct clk_bulk_data **clks);
330 365
331/** 366/**
332 * devm_clk_get - lookup and obtain a managed reference to a clock producer. 367 * devm_clk_get - lookup and obtain a managed reference to a clock producer.
@@ -488,6 +523,19 @@ void clk_put(struct clk *clk);
488void clk_bulk_put(int num_clks, struct clk_bulk_data *clks); 523void clk_bulk_put(int num_clks, struct clk_bulk_data *clks);
489 524
490/** 525/**
526 * clk_bulk_put_all - "free" all the clock source
527 * @num_clks: the number of clk_bulk_data
528 * @clks: the clk_bulk_data table of consumer
529 *
530 * Note: drivers must ensure that all clk_bulk_enable calls made on this
531 * clock source are balanced by clk_bulk_disable calls prior to calling
532 * this function.
533 *
534 * clk_bulk_put_all should not be called from within interrupt context.
535 */
536void clk_bulk_put_all(int num_clks, struct clk_bulk_data *clks);
537
538/**
491 * devm_clk_put - "free" a managed clock source 539 * devm_clk_put - "free" a managed clock source
492 * @dev: device used to acquire the clock 540 * @dev: device used to acquire the clock
493 * @clk: clock source acquired with devm_clk_get() 541 * @clk: clock source acquired with devm_clk_get()
@@ -629,6 +677,23 @@ struct clk *clk_get_parent(struct clk *clk);
629 */ 677 */
630struct clk *clk_get_sys(const char *dev_id, const char *con_id); 678struct clk *clk_get_sys(const char *dev_id, const char *con_id);
631 679
680/**
681 * clk_save_context - save clock context for poweroff
682 *
683 * Saves the context of the clock register for powerstates in which the
684 * contents of the registers will be lost. Occurs deep within the suspend
685 * code so locking is not necessary.
686 */
687int clk_save_context(void);
688
689/**
690 * clk_restore_context - restore clock context after poweroff
691 *
692 * This occurs with all clocks enabled. Occurs deep within the resume code
693 * so locking is not necessary.
694 */
695void clk_restore_context(void);
696
632#else /* !CONFIG_HAVE_CLK */ 697#else /* !CONFIG_HAVE_CLK */
633 698
634static inline struct clk *clk_get(struct device *dev, const char *id) 699static inline struct clk *clk_get(struct device *dev, const char *id)
@@ -642,6 +707,12 @@ static inline int __must_check clk_bulk_get(struct device *dev, int num_clks,
642 return 0; 707 return 0;
643} 708}
644 709
710static inline int __must_check clk_bulk_get_all(struct device *dev,
711 struct clk_bulk_data **clks)
712{
713 return 0;
714}
715
645static inline struct clk *devm_clk_get(struct device *dev, const char *id) 716static inline struct clk *devm_clk_get(struct device *dev, const char *id)
646{ 717{
647 return NULL; 718 return NULL;
@@ -653,6 +724,13 @@ static inline int __must_check devm_clk_bulk_get(struct device *dev, int num_clk
653 return 0; 724 return 0;
654} 725}
655 726
727static inline int __must_check devm_clk_bulk_get_all(struct device *dev,
728 struct clk_bulk_data **clks)
729{
730
731 return 0;
732}
733
656static inline struct clk *devm_get_clk_from_child(struct device *dev, 734static inline struct clk *devm_get_clk_from_child(struct device *dev,
657 struct device_node *np, const char *con_id) 735 struct device_node *np, const char *con_id)
658{ 736{
@@ -663,6 +741,8 @@ static inline void clk_put(struct clk *clk) {}
663 741
664static inline void clk_bulk_put(int num_clks, struct clk_bulk_data *clks) {} 742static inline void clk_bulk_put(int num_clks, struct clk_bulk_data *clks) {}
665 743
744static inline void clk_bulk_put_all(int num_clks, struct clk_bulk_data *clks) {}
745
666static inline void devm_clk_put(struct device *dev, struct clk *clk) {} 746static inline void devm_clk_put(struct device *dev, struct clk *clk) {}
667 747
668 748
@@ -728,6 +808,14 @@ static inline struct clk *clk_get_sys(const char *dev_id, const char *con_id)
728{ 808{
729 return NULL; 809 return NULL;
730} 810}
811
812static inline int clk_save_context(void)
813{
814 return 0;
815}
816
817static inline void clk_restore_context(void) {}
818
731#endif 819#endif
732 820
733/* clk_prepare_enable helps cases using clk_enable in non-atomic context. */ 821/* clk_prepare_enable helps cases using clk_enable in non-atomic context. */
diff --git a/include/linux/clk/renesas.h b/include/linux/clk/renesas.h
index 9ebf1f8243bb..0ebbe2f0b45e 100644
--- a/include/linux/clk/renesas.h
+++ b/include/linux/clk/renesas.h
@@ -1,14 +1,10 @@
1/* 1/* SPDX-License-Identifier: GPL-2.0+
2 *
2 * Copyright 2013 Ideas On Board SPRL 3 * Copyright 2013 Ideas On Board SPRL
3 * Copyright 2013, 2014 Horms Solutions Ltd. 4 * Copyright 2013, 2014 Horms Solutions Ltd.
4 * 5 *
5 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 6 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
6 * Contact: Simon Horman <horms@verge.net.au> 7 * Contact: Simon Horman <horms@verge.net.au>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */ 8 */
13 9
14#ifndef __LINUX_CLK_RENESAS_H_ 10#ifndef __LINUX_CLK_RENESAS_H_
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index a8faa38b1ed6..eacc5df57b99 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -159,6 +159,7 @@ struct clk_hw_omap {
159 const char *clkdm_name; 159 const char *clkdm_name;
160 struct clockdomain *clkdm; 160 struct clockdomain *clkdm;
161 const struct clk_hw_omap_ops *ops; 161 const struct clk_hw_omap_ops *ops;
162 u32 context;
162}; 163};
163 164
164/* 165/*
@@ -290,9 +291,15 @@ struct ti_clk_features {
290#define TI_CLK_DPLL4_DENY_REPROGRAM BIT(1) 291#define TI_CLK_DPLL4_DENY_REPROGRAM BIT(1)
291#define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2) 292#define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2)
292#define TI_CLK_ERRATA_I810 BIT(3) 293#define TI_CLK_ERRATA_I810 BIT(3)
294#define TI_CLK_CLKCTRL_COMPAT BIT(4)
293 295
294void ti_clk_setup_features(struct ti_clk_features *features); 296void ti_clk_setup_features(struct ti_clk_features *features);
295const struct ti_clk_features *ti_clk_get_features(void); 297const struct ti_clk_features *ti_clk_get_features(void);
298int omap3_noncore_dpll_save_context(struct clk_hw *hw);
299void omap3_noncore_dpll_restore_context(struct clk_hw *hw);
300
301int omap3_core_dpll_save_context(struct clk_hw *hw);
302void omap3_core_dpll_restore_context(struct clk_hw *hw);
296 303
297extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; 304extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
298 305
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-11 04:11:10 -0400