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-rw-r--r--Documentation/clk.txt2
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt30
-rw-r--r--Documentation/devicetree/bindings/clock/actions,s900-cmu.txt47
-rw-r--r--Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt26
-rw-r--r--Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt100
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc.txt2
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt22
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,videocc.txt19
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt10
-rw-r--r--Documentation/devicetree/bindings/clock/rockchip.txt77
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi-ccu.txt3
-rw-r--r--MAINTAINERS1
-rw-r--r--arch/arm/boot/dts/imx7d.dtsi2
-rw-r--r--arch/arm/boot/dts/imx7s.dtsi2
-rw-r--r--drivers/clk/Kconfig1
-rw-r--r--drivers/clk/Makefile2
-rw-r--r--drivers/clk/actions/Kconfig14
-rw-r--r--drivers/clk/actions/Makefile12
-rw-r--r--drivers/clk/actions/owl-common.c89
-rw-r--r--drivers/clk/actions/owl-common.h41
-rw-r--r--drivers/clk/actions/owl-composite.c199
-rw-r--r--drivers/clk/actions/owl-composite.h124
-rw-r--r--drivers/clk/actions/owl-divider.c94
-rw-r--r--drivers/clk/actions/owl-divider.h75
-rw-r--r--drivers/clk/actions/owl-factor.c222
-rw-r--r--drivers/clk/actions/owl-factor.h83
-rw-r--r--drivers/clk/actions/owl-fixed-factor.h28
-rw-r--r--drivers/clk/actions/owl-gate.c77
-rw-r--r--drivers/clk/actions/owl-gate.h73
-rw-r--r--drivers/clk/actions/owl-mux.c60
-rw-r--r--drivers/clk/actions/owl-mux.h61
-rw-r--r--drivers/clk/actions/owl-pll.c194
-rw-r--r--drivers/clk/actions/owl-pll.h92
-rw-r--r--drivers/clk/actions/owl-s900.c721
-rw-r--r--drivers/clk/at91/clk-pll.c13
-rw-r--r--drivers/clk/bcm/clk-bcm2835.c42
-rw-r--r--drivers/clk/bcm/clk-sr.c135
-rw-r--r--drivers/clk/berlin/berlin2-avpll.c13
-rw-r--r--drivers/clk/berlin/berlin2-avpll.h13
-rw-r--r--drivers/clk/berlin/berlin2-div.c13
-rw-r--r--drivers/clk/berlin/berlin2-div.h13
-rw-r--r--drivers/clk/berlin/berlin2-pll.c13
-rw-r--r--drivers/clk/berlin/berlin2-pll.h13
-rw-r--r--drivers/clk/berlin/bg2.c13
-rw-r--r--drivers/clk/berlin/bg2q.c13
-rw-r--r--drivers/clk/berlin/common.h13
-rw-r--r--drivers/clk/clk-aspeed.c57
-rw-r--r--drivers/clk/clk-bulk.c5
-rw-r--r--drivers/clk/clk-npcm7xx.c656
-rw-r--r--drivers/clk/clk-si544.c1
-rw-r--r--drivers/clk/clk-stm32mp1.c66
-rw-r--r--drivers/clk/clk.c171
-rw-r--r--drivers/clk/davinci/pll.c15
-rw-r--r--drivers/clk/davinci/psc-da830.c3
-rw-r--r--drivers/clk/hisilicon/Kconfig13
-rw-r--r--drivers/clk/hisilicon/crg-hi3798cv200.c17
-rw-r--r--drivers/clk/imx/clk-imx6q.c2
-rw-r--r--drivers/clk/imx/clk-imx6sl.c2
-rw-r--r--drivers/clk/imx/clk-imx6sx.c17
-rw-r--r--drivers/clk/imx/clk-imx6ul.c18
-rw-r--r--drivers/clk/imx/clk-imx7d.c17
-rw-r--r--drivers/clk/ingenic/cgu.c8
-rw-r--r--drivers/clk/ingenic/cgu.h4
-rw-r--r--drivers/clk/ingenic/jz4770-cgu.c49
-rw-r--r--drivers/clk/mediatek/Kconfig6
-rw-r--r--drivers/clk/mediatek/Makefile1
-rw-r--r--drivers/clk/mediatek/clk-mt2701-g3d.c95
-rw-r--r--drivers/clk/mediatek/clk-mt2701.c8
-rw-r--r--drivers/clk/meson/Kconfig8
-rw-r--r--drivers/clk/meson/Makefile3
-rw-r--r--drivers/clk/meson/axg-aoclk.c164
-rw-r--r--drivers/clk/meson/axg-aoclk.h29
-rw-r--r--drivers/clk/meson/axg.c4
-rw-r--r--drivers/clk/meson/clk-audio-divider.c13
-rw-r--r--drivers/clk/meson/clk-mpll.c76
-rw-r--r--drivers/clk/meson/clk-pll.c13
-rw-r--r--drivers/clk/meson/clk-regmap.c6
-rw-r--r--drivers/clk/meson/clk-regmap.h8
-rw-r--r--drivers/clk/meson/clkc.h16
-rw-r--r--drivers/clk/meson/gxbb-aoclk-32k.c3
-rw-r--r--drivers/clk/meson/gxbb-aoclk.c147
-rw-r--r--drivers/clk/meson/gxbb-aoclk.h8
-rw-r--r--drivers/clk/meson/gxbb.c129
-rw-r--r--drivers/clk/meson/gxbb.h58
-rw-r--r--drivers/clk/meson/meson-aoclk.c81
-rw-r--r--drivers/clk/meson/meson-aoclk.h34
-rw-r--r--drivers/clk/meson/meson8b.c77
-rw-r--r--drivers/clk/meson/meson8b.h18
-rw-r--r--drivers/clk/mvebu/clk-corediv.c2
-rw-r--r--drivers/clk/qcom/Kconfig27
-rw-r--r--drivers/clk/qcom/Makefile3
-rw-r--r--drivers/clk/qcom/clk-alpha-pll.c302
-rw-r--r--drivers/clk/qcom/clk-alpha-pll.h18
-rw-r--r--drivers/clk/qcom/clk-branch.c7
-rw-r--r--drivers/clk/qcom/clk-branch.h1
-rw-r--r--drivers/clk/qcom/clk-rcg.h17
-rw-r--r--drivers/clk/qcom/clk-rcg2.c168
-rw-r--r--drivers/clk/qcom/common.c32
-rw-r--r--drivers/clk/qcom/gcc-msm8996.c8
-rw-r--r--drivers/clk/qcom/gcc-msm8998.c2834
-rw-r--r--drivers/clk/qcom/gcc-sdm845.c3465
-rw-r--r--drivers/clk/qcom/gdsc.c102
-rw-r--r--drivers/clk/qcom/gdsc.h6
-rw-r--r--drivers/clk/qcom/mmcc-msm8996.c22
-rw-r--r--drivers/clk/qcom/videocc-sdm845.c358
-rw-r--r--drivers/clk/renesas/Kconfig10
-rw-r--r--drivers/clk/renesas/Makefile2
-rw-r--r--drivers/clk/renesas/r8a7743-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a7745-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a77470-cpg-mssr.c229
-rw-r--r--drivers/clk/renesas/r8a7791-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a7792-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a7794-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a77965-cpg-mssr.c4
-rw-r--r--drivers/clk/renesas/r8a77980-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a77990-cpg-mssr.c289
-rw-r--r--drivers/clk/renesas/rcar-gen2-cpg.c24
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.c12
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.h2
-rw-r--r--drivers/clk/rockchip/Makefile1
-rw-r--r--drivers/clk/rockchip/clk-rockchip.c98
-rw-r--r--drivers/clk/rockchip/clk.c16
-rw-r--r--drivers/clk/samsung/clk-s3c2410-dclk.c6
-rw-r--r--drivers/clk/socfpga/clk-s10.c40
-rw-r--r--drivers/clk/spear/spear6xx_clock.c2
-rw-r--r--drivers/clk/sunxi-ng/Kconfig5
-rw-r--r--drivers/clk/sunxi-ng/Makefile1
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c207
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h19
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-r40.c72
-rw-r--r--drivers/clk/tegra/clk-dfll.c42
-rw-r--r--drivers/clk/tegra/clk-tegra114.c2
-rw-r--r--drivers/clk/tegra/clk-tegra124.c2
-rw-r--r--drivers/clk/tegra/clk-tegra20.c52
-rw-r--r--drivers/clk/tegra/clk-tegra210.c2
-rw-r--r--drivers/clk/tegra/clk-tegra30.c2
-rw-r--r--drivers/clk/tegra/clk.c5
-rw-r--r--drivers/clk/tegra/clk.h2
-rw-r--r--drivers/clk/uniphier/clk-uniphier-sys.c5
-rw-r--r--drivers/clocksource/timer-sp804.c3
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.c4
-rw-r--r--drivers/soc/rockchip/pm_domains.c4
-rw-r--r--drivers/soc/tegra/pmc.c3
-rw-r--r--include/dt-bindings/clock/actions,s900-cmu.h129
-rw-r--r--include/dt-bindings/clock/aspeed-clock.h4
-rw-r--r--include/dt-bindings/clock/axg-aoclkc.h26
-rw-r--r--include/dt-bindings/clock/bcm-sr.h24
-rw-r--r--include/dt-bindings/clock/gxbb-clkc.h2
-rw-r--r--include/dt-bindings/clock/histb-clock.h8
-rw-r--r--include/dt-bindings/clock/imx6qdl-clock.h4
-rw-r--r--include/dt-bindings/clock/imx6sx-clock.h6
-rw-r--r--include/dt-bindings/clock/imx6ul-clock.h33
-rw-r--r--include/dt-bindings/clock/imx7d-clock.h4
-rw-r--r--include/dt-bindings/clock/meson8b-clkc.h1
-rw-r--r--include/dt-bindings/clock/mt2701-clk.h20
-rw-r--r--include/dt-bindings/clock/nuvoton,npcm7xx-clock.h44
-rw-r--r--include/dt-bindings/clock/qcom,gcc-msm8998.h208
-rw-r--r--include/dt-bindings/clock/qcom,gcc-sdm845.h239
-rw-r--r--include/dt-bindings/clock/qcom,rpmh.h22
-rw-r--r--include/dt-bindings/clock/qcom,videocc-sdm845.h35
-rw-r--r--include/dt-bindings/clock/r8a77470-cpg-mssr.h36
-rw-r--r--include/dt-bindings/clock/r8a77990-cpg-mssr.h62
-rw-r--r--include/dt-bindings/clock/stm32mp1-clks.h4
-rw-r--r--include/dt-bindings/clock/sun50i-h6-r-ccu.h24
-rw-r--r--include/dt-bindings/reset/axg-aoclkc.h20
-rw-r--r--include/dt-bindings/reset/mt2701-resets.h3
-rw-r--r--include/dt-bindings/reset/sun50i-h6-r-ccu.h17
-rw-r--r--include/linux/clk-provider.h23
-rw-r--r--include/linux/of_clk.h30
170 files changed, 13448 insertions, 1170 deletions
diff --git a/Documentation/clk.txt b/Documentation/clk.txt
index 511628bb3d3a..593cca5058b1 100644
--- a/Documentation/clk.txt
+++ b/Documentation/clk.txt
@@ -96,7 +96,7 @@ the operations defined in clk-provider.h::
96 int (*get_phase)(struct clk_hw *hw); 96 int (*get_phase)(struct clk_hw *hw);
97 int (*set_phase)(struct clk_hw *hw, int degrees); 97 int (*set_phase)(struct clk_hw *hw, int degrees);
98 void (*init)(struct clk_hw *hw); 98 void (*init)(struct clk_hw *hw);
99 int (*debug_init)(struct clk_hw *hw, 99 void (*debug_init)(struct clk_hw *hw,
100 struct dentry *dentry); 100 struct dentry *dentry);
101 }; 101 };
102 102
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
new file mode 100644
index 000000000000..7de43bf41fdc
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
@@ -0,0 +1,30 @@
1MediaTek g3dsys controller
2============================
3
4The MediaTek g3dsys controller provides various clocks and reset controller to
5the GPU.
6
7Required Properties:
8
9- compatible: Should be:
10 - "mediatek,mt2701-g3dsys", "syscon":
11 for MT2701 SoC
12 - "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon":
13 for MT7623 SoC
14- #clock-cells: Must be 1
15- #reset-cells: Must be 1
16
17The g3dsys controller uses the common clk binding from
18Documentation/devicetree/bindings/clock/clock-bindings.txt
19The available clocks are defined in dt-bindings/clock/mt*-clk.h.
20
21Example:
22
23g3dsys: clock-controller@13000000 {
24 compatible = "mediatek,mt7623-g3dsys",
25 "mediatek,mt2701-g3dsys",
26 "syscon";
27 reg = <0 0x13000000 0 0x200>;
28 #clock-cells = <1>;
29 #reset-cells = <1>;
30};
diff --git a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt b/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
new file mode 100644
index 000000000000..93e4fb827cd6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
@@ -0,0 +1,47 @@
1* Actions S900 Clock Management Unit (CMU)
2
3The Actions S900 clock management unit generates and supplies clock to various
4controllers within the SoC. The clock binding described here is applicable to
5S900 SoC.
6
7Required Properties:
8
9- compatible: should be "actions,s900-cmu"
10- reg: physical base address of the controller and length of memory mapped
11 region.
12- clocks: Reference to the parent clocks ("hosc", "losc")
13- #clock-cells: should be 1.
14
15Each clock is assigned an identifier, and client nodes can use this identifier
16to specify the clock which they consume.
17
18All available clocks are defined as preprocessor macros in
19dt-bindings/clock/actions,s900-cmu.h header and can be used in device
20tree sources.
21
22External clocks:
23
24The hosc clock used as input for the plls is generated outside the SoC. It is
25expected that it is defined using standard clock bindings as "hosc".
26
27Actions S900 CMU also requires one more clock:
28 - "losc" - internal low frequency oscillator
29
30Example: Clock Management Unit node:
31
32 cmu: clock-controller@e0160000 {
33 compatible = "actions,s900-cmu";
34 reg = <0x0 0xe0160000 0x0 0x1000>;
35 clocks = <&hosc>, <&losc>;
36 #clock-cells = <1>;
37 };
38
39Example: UART controller node that consumes clock generated by the clock
40management unit:
41
42 uart: serial@e012a000 {
43 compatible = "actions,s900-uart", "actions,owl-uart";
44 reg = <0x0 0xe012a000 0x0 0x2000>;
45 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
46 clocks = <&cmu CLK_UART5>;
47 };
diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
index 786dc39ca904..3a880528030e 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
@@ -9,6 +9,7 @@ Required Properties:
9 - GXBB (S905) : "amlogic,meson-gxbb-aoclkc" 9 - GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
10 - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc" 10 - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
11 - GXM (S912) : "amlogic,meson-gxm-aoclkc" 11 - GXM (S912) : "amlogic,meson-gxm-aoclkc"
12 - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
12 followed by the common "amlogic,meson-gx-aoclkc" 13 followed by the common "amlogic,meson-gx-aoclkc"
13 14
14- #clock-cells: should be 1. 15- #clock-cells: should be 1.
diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
index f8e4a93466cb..ab730ea0a560 100644
--- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
@@ -276,36 +276,38 @@ These clock IDs are defined in:
276 clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK 276 clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
277 clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK 277 clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
278 clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK 278 clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
279 clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH 279 clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK
280 clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK
280 281
281 genpll3 crystal 0 BCM_SR_GENPLL3 282 genpll3 crystal 0 BCM_SR_GENPLL3
282 clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK 283 clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
283 clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK 284 clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
284 285
285 genpll4 crystal 0 BCM_SR_GENPLL4 286 genpll4 crystal 0 BCM_SR_GENPLL4
286 ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK 287 clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
287 clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK 288 clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
288 noc_clk genpll4 3 BCM_SR_GENPLL4_NOC_CLK 289 clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK
289 clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK 290 clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
290 clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 291 clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
291 292
292
293 genpll5 crystal 0 BCM_SR_GENPLL5 293 genpll5 crystal 0 BCM_SR_GENPLL5
294 fs4_hf_clk genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK 294 clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
295 crypto_ae_clk genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK 295 clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
296 raid_ae_clk genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK 296 clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
297 297
298 genpll6 crystal 0 BCM_SR_GENPLL6 298 genpll6 crystal 0 BCM_SR_GENPLL6
299 48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK 299 clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
300 300
301 lcpll0 crystal 0 BCM_SR_LCPLL0 301 lcpll0 crystal 0 BCM_SR_LCPLL0
302 clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK 302 clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
303 clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK 303 clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
304 clk_usb_ref lcpll0 3 BCM_SR_LCPLL0_USB_REF_CLK 304 clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK
305 sata_refpn lcpll0 3 BCM_SR_LCPLL0_SATA_REFPN_CLK 305 clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK
306 306
307 lcpll1 crystal 0 BCM_SR_LCPLL1 307 lcpll1 crystal 0 BCM_SR_LCPLL1
308 wan lcpll1 1 BCM_SR_LCPLL0_WAN_CLK 308 clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK
309 clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK
310 clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK
309 311
310 lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE 312 lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
311 pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK 313 clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK
diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt b/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt
new file mode 100644
index 000000000000..f82064546d11
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt
@@ -0,0 +1,100 @@
1* Nuvoton NPCM7XX Clock Controller
2
3Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
4generates and supplies clocks to all modules within the BMC.
5
6External clocks:
7
8There are six fixed clocks that are generated outside the BMC. All clocks are of
9a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and
10clk_sysbypck are inputs to the clock controller.
11clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the
12network. They are set on the device tree, but not used by the clock module. The
13network devices use them directly.
14Example can be found below.
15
16All available clocks are defined as preprocessor macros in:
17dt-bindings/clock/nuvoton,npcm7xx-clock.h
18and can be reused as DT sources.
19
20Required Properties of clock controller:
21
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
23 Poleg BMC NPCM750
24
25 - reg: physical base address of the clock controller and length of
26 memory mapped region.
27
28 - #clock-cells: should be 1.
29
30Example: Clock controller node:
31
32 clk: clock-controller@f0801000 {
33 compatible = "nuvoton,npcm750-clk";
34 #clock-cells = <1>;
35 reg = <0xf0801000 0x1000>;
36 clock-names = "refclk", "sysbypck", "mcbypck";
37 clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
38 };
39
40Example: Required external clocks for network:
41
42 /* external reference clock */
43 clk_refclk: clk-refclk {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <25000000>;
47 clock-output-names = "refclk";
48 };
49
50 /* external reference clock for cpu. float in normal operation */
51 clk_sysbypck: clk-sysbypck {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <800000000>;
55 clock-output-names = "sysbypck";
56 };
57
58 /* external reference clock for MC. float in normal operation */
59 clk_mcbypck: clk-mcbypck {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <800000000>;
63 clock-output-names = "mcbypck";
64 };
65
66 /* external clock signal rg1refck, supplied by the phy */
67 clk_rg1refck: clk-rg1refck {
68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <125000000>;
71 clock-output-names = "clk_rg1refck";
72 };
73
74 /* external clock signal rg2refck, supplied by the phy */
75 clk_rg2refck: clk-rg2refck {
76 compatible = "fixed-clock";
77 #clock-cells = <0>;
78 clock-frequency = <125000000>;
79 clock-output-names = "clk_rg2refck";
80 };
81
82 clk_xin: clk-xin {
83 compatible = "fixed-clock";
84 #clock-cells = <0>;
85 clock-frequency = <50000000>;
86 clock-output-names = "clk_xin";
87 };
88
89
90Example: GMAC controller node that consumes two clocks: a generated clk by the
91clock controller and a fixed clock from DT (clk_rg1refck).
92
93 ethernet0: ethernet@f0802000 {
94 compatible = "snps,dwmac";
95 reg = <0xf0802000 0x2000>;
96 interrupts = <0 14 4>;
97 interrupt-names = "macirq";
98 clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
99 clock-names = "stmmaceth", "clk_gmac";
100 };
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 551d03be9665..664ea1fd6c76 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -17,7 +17,9 @@ Required properties :
17 "qcom,gcc-msm8974pro-ac" 17 "qcom,gcc-msm8974pro-ac"
18 "qcom,gcc-msm8994" 18 "qcom,gcc-msm8994"
19 "qcom,gcc-msm8996" 19 "qcom,gcc-msm8996"
20 "qcom,gcc-msm8998"
20 "qcom,gcc-mdm9615" 21 "qcom,gcc-mdm9615"
22 "qcom,gcc-sdm845"
21 23
22- reg : shall contain base register location and length 24- reg : shall contain base register location and length
23- #clock-cells : shall contain 1 25- #clock-cells : shall contain 1
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt b/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt
new file mode 100644
index 000000000000..3c007653da31
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt
@@ -0,0 +1,22 @@
1Qualcomm Technologies, Inc. RPMh Clocks
2-------------------------------------------------------
3
4Resource Power Manager Hardened (RPMh) manages shared resources on
5some Qualcomm Technologies Inc. SoCs. It accepts clock requests from
6other hardware subsystems via RSC to control clocks.
7
8Required properties :
9- compatible : shall contain "qcom,sdm845-rpmh-clk"
10
11- #clock-cells : must contain 1
12
13Example :
14
15#include <dt-bindings/clock/qcom,rpmh.h>
16
17 &apps_rsc {
18 rpmhcc: clock-controller {
19 compatible = "qcom,sdm845-rpmh-clk";
20 #clock-cells = <1>;
21 };
22 };
diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.txt b/Documentation/devicetree/bindings/clock/qcom,videocc.txt
new file mode 100644
index 000000000000..e7c035afa778
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,videocc.txt
@@ -0,0 +1,19 @@
1Qualcomm Video Clock & Reset Controller Binding
2-----------------------------------------------
3
4Required properties :
5- compatible : shall contain "qcom,sdm845-videocc"
6- reg : shall contain base register location and length
7- #clock-cells : from common clock binding, shall contain 1.
8- #power-domain-cells : from generic power domain binding, shall contain 1.
9
10Optional properties :
11- #reset-cells : from common reset binding, shall contain 1.
12
13Example:
14 videocc: clock-controller@ab00000 {
15 compatible = "qcom,sdm845-videocc";
16 reg = <0xab00000 0x10000>;
17 #clock-cells = <1>;
18 #power-domain-cells = <1>;
19 };
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
index 773a5226342f..db542abadb75 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -15,6 +15,7 @@ Required Properties:
15 - compatible: Must be one of: 15 - compatible: Must be one of:
16 - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M) 16 - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
17 - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E) 17 - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
18 - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
18 - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2) 19 - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
19 - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W) 20 - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
20 - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H) 21 - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
@@ -25,6 +26,7 @@ Required Properties:
25 - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N) 26 - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
26 - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M) 27 - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
27 - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H) 28 - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
29 - "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3)
28 - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3) 30 - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
29 31
30 - reg: Base address and length of the memory resource used by the CPG/MSSR 32 - reg: Base address and length of the memory resource used by the CPG/MSSR
@@ -33,10 +35,12 @@ Required Properties:
33 - clocks: References to external parent clocks, one entry for each entry in 35 - clocks: References to external parent clocks, one entry for each entry in
34 clock-names 36 clock-names
35 - clock-names: List of external parent clock names. Valid names are: 37 - clock-names: List of external parent clock names. Valid names are:
36 - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794, 38 - "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792,
37 r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77995) 39 r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970,
40 r8a77980, r8a77990, r8a77995)
38 - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980) 41 - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
39 - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794) 42 - "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793,
43 r8a7794)
40 44
41 - #clock-cells: Must be 2 45 - #clock-cells: Must be 2
42 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" 46 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
diff --git a/Documentation/devicetree/bindings/clock/rockchip.txt b/Documentation/devicetree/bindings/clock/rockchip.txt
deleted file mode 100644
index 22f6769e5d4a..000000000000
--- a/Documentation/devicetree/bindings/clock/rockchip.txt
+++ /dev/null
@@ -1,77 +0,0 @@
1Device Tree Clock bindings for arch-rockchip
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7== Gate clocks ==
8
9These bindings are deprecated!
10Please use the soc specific CRU bindings instead.
11
12The gate registers form a continuos block which makes the dt node
13structure a matter of taste, as either all gates can be put into
14one gate clock spanning all registers or they can be divided into
15the 10 individual gates containing 16 clocks each.
16The code supports both approaches.
17
18Required properties:
19- compatible : "rockchip,rk2928-gate-clk"
20- reg : shall be the control register address(es) for the clock.
21- #clock-cells : from common clock binding; shall be set to 1
22- clock-output-names : the corresponding gate names that the clock controls
23- clocks : should contain the parent clock for each individual gate,
24 therefore the number of clocks elements should match the number of
25 clock-output-names
26
27Example using multiple gate clocks:
28
29 clk_gates0: gate-clk@200000d0 {
30 compatible = "rockchip,rk2928-gate-clk";
31 reg = <0x200000d0 0x4>;
32 clocks = <&dummy>, <&dummy>,
33 <&dummy>, <&dummy>,
34 <&dummy>, <&dummy>,
35 <&dummy>, <&dummy>,
36 <&dummy>, <&dummy>,
37 <&dummy>, <&dummy>,
38 <&dummy>, <&dummy>,
39 <&dummy>, <&dummy>;
40
41 clock-output-names =
42 "gate_core_periph", "gate_cpu_gpll",
43 "gate_ddrphy", "gate_aclk_cpu",
44 "gate_hclk_cpu", "gate_pclk_cpu",
45 "gate_atclk_cpu", "gate_i2s0",
46 "gate_i2s0_frac", "gate_i2s1",
47 "gate_i2s1_frac", "gate_i2s2",
48 "gate_i2s2_frac", "gate_spdif",
49 "gate_spdif_frac", "gate_testclk";
50
51 #clock-cells = <1>;
52 };
53
54 clk_gates1: gate-clk@200000d4 {
55 compatible = "rockchip,rk2928-gate-clk";
56 reg = <0x200000d4 0x4>;
57 clocks = <&xin24m>, <&xin24m>,
58 <&xin24m>, <&dummy>,
59 <&dummy>, <&xin24m>,
60 <&xin24m>, <&dummy>,
61 <&xin24m>, <&dummy>,
62 <&xin24m>, <&dummy>,
63 <&xin24m>, <&dummy>,
64 <&xin24m>, <&dummy>;
65
66 clock-output-names =
67 "gate_timer0", "gate_timer1",
68 "gate_timer2", "gate_jtag",
69 "gate_aclk_lcdc1_src", "gate_otgphy0",
70 "gate_otgphy1", "gate_ddr_gpll",
71 "gate_uart0", "gate_frac_uart0",
72 "gate_uart1", "gate_frac_uart1",
73 "gate_uart2", "gate_frac_uart2",
74 "gate_uart3", "gate_frac_uart3";
75
76 #clock-cells = <1>;
77 };
diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index 460ef27b1008..47d2e902ced4 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -21,6 +21,7 @@ Required properties :
21 - "allwinner,sun50i-a64-r-ccu" 21 - "allwinner,sun50i-a64-r-ccu"
22 - "allwinner,sun50i-h5-ccu" 22 - "allwinner,sun50i-h5-ccu"
23 - "allwinner,sun50i-h6-ccu" 23 - "allwinner,sun50i-h6-ccu"
24 - "allwinner,sun50i-h6-r-ccu"
24 - "nextthing,gr8-ccu" 25 - "nextthing,gr8-ccu"
25 26
26- reg: Must contain the registers base address and length 27- reg: Must contain the registers base address and length
@@ -35,7 +36,7 @@ Required properties :
35For the main CCU on H6, one more clock is needed: 36For the main CCU on H6, one more clock is needed:
36- "iosc": the SoC's internal frequency oscillator 37- "iosc": the SoC's internal frequency oscillator
37 38
38For the PRCM CCUs on A83T/H3/A64, two more clocks are needed: 39For the PRCM CCUs on A83T/H3/A64/H6, two more clocks are needed:
39- "pll-periph": the SoC's peripheral PLL from the main CCU 40- "pll-periph": the SoC's peripheral PLL from the main CCU
40- "iosc": the SoC's internal frequency oscillator 41- "iosc": the SoC's internal frequency oscillator
41 42
diff --git a/MAINTAINERS b/MAINTAINERS
index 0a1410d5a621..b61b2bf1eb75 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3556,6 +3556,7 @@ F: drivers/clk/
3556X: drivers/clk/clkdev.c 3556X: drivers/clk/clkdev.c
3557F: include/linux/clk-pr* 3557F: include/linux/clk-pr*
3558F: include/linux/clk/ 3558F: include/linux/clk/
3559F: include/linux/of_clk.h
3559 3560
3560COMMON INTERNET FILE SYSTEM (CIFS) 3561COMMON INTERNET FILE SYSTEM (CIFS)
3561M: Steve French <sfrench@samba.org> 3562M: Steve French <sfrench@samba.org>
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index 200714e3feea..d74dd7f19507 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -120,7 +120,7 @@
120 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
121 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
122 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 122 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
123 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, 123 clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
124 <&clks IMX7D_ENET_AXI_ROOT_CLK>, 124 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
125 <&clks IMX7D_ENET2_TIME_ROOT_CLK>, 125 <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
126 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, 126 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 4d42335c0dee..b90769de6893 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -1091,7 +1091,7 @@
1091 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1092 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1093 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1093 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1094 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, 1094 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1095 <&clks IMX7D_ENET_AXI_ROOT_CLK>, 1095 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1096 <&clks IMX7D_ENET1_TIME_ROOT_CLK>, 1096 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1097 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, 1097 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 41492e980ef4..24a5bc3a2ddb 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -279,6 +279,7 @@ config COMMON_CLK_STM32H7
279 ---help--- 279 ---help---
280 Support for stm32h7 SoC family clocks 280 Support for stm32h7 SoC family clocks
281 281
282source "drivers/clk/actions/Kconfig"
282source "drivers/clk/bcm/Kconfig" 283source "drivers/clk/bcm/Kconfig"
283source "drivers/clk/hisilicon/Kconfig" 284source "drivers/clk/hisilicon/Kconfig"
284source "drivers/clk/imgtec/Kconfig" 285source "drivers/clk/imgtec/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index de6d06ac790b..ae40cbe770f0 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
33obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o 33obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
34obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o 34obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
35obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o 35obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
36obj-$(CONFIG_ARCH_NPCM7XX) += clk-npcm7xx.o
36obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o 37obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
37obj-$(CONFIG_COMMON_CLK_OXNAS) += clk-oxnas.o 38obj-$(CONFIG_COMMON_CLK_OXNAS) += clk-oxnas.o
38obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o 39obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o
@@ -59,6 +60,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
59obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o 60obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
60 61
61# please keep this section sorted lexicographically by directory path name 62# please keep this section sorted lexicographically by directory path name
63obj-y += actions/
62obj-$(CONFIG_COMMON_CLK_AT91) += at91/ 64obj-$(CONFIG_COMMON_CLK_AT91) += at91/
63obj-$(CONFIG_ARCH_ARTPEC) += axis/ 65obj-$(CONFIG_ARCH_ARTPEC) += axis/
64obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/ 66obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/
diff --git a/drivers/clk/actions/Kconfig b/drivers/clk/actions/Kconfig
new file mode 100644
index 000000000000..8854adb37847
--- /dev/null
+++ b/drivers/clk/actions/Kconfig
@@ -0,0 +1,14 @@
1config CLK_ACTIONS
2 bool "Clock driver for Actions Semi SoCs"
3 depends on ARCH_ACTIONS || COMPILE_TEST
4 default ARCH_ACTIONS
5
6if CLK_ACTIONS
7
8# SoC Drivers
9
10config CLK_OWL_S900
11 bool "Support for the Actions Semi OWL S900 clocks"
12 depends on (ARM64 && ARCH_ACTIONS) || COMPILE_TEST
13 default ARM64 && ARCH_ACTIONS
14endif
diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile
new file mode 100644
index 000000000000..76e431434d10
--- /dev/null
+++ b/drivers/clk/actions/Makefile
@@ -0,0 +1,12 @@
1obj-$(CONFIG_CLK_ACTIONS) += clk-owl.o
2
3clk-owl-y += owl-common.o
4clk-owl-y += owl-gate.o
5clk-owl-y += owl-mux.o
6clk-owl-y += owl-divider.o
7clk-owl-y += owl-factor.o
8clk-owl-y += owl-composite.o
9clk-owl-y += owl-pll.o
10
11# SoC support
12obj-$(CONFIG_CLK_OWL_S900) += owl-s900.o
diff --git a/drivers/clk/actions/owl-common.c b/drivers/clk/actions/owl-common.c
new file mode 100644
index 000000000000..61c1071b5180
--- /dev/null
+++ b/drivers/clk/actions/owl-common.c
@@ -0,0 +1,89 @@
1// SPDX-License-Identifier: GPL-2.0+
2//
3// OWL common clock driver
4//
5// Copyright (c) 2014 Actions Semi Inc.
6// Author: David Liu <liuwei@actions-semi.com>
7//
8// Copyright (c) 2018 Linaro Ltd.
9// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10
11#include <linux/of_address.h>
12#include <linux/of_platform.h>
13#include <linux/platform_device.h>
14#include <linux/regmap.h>
15
16#include "owl-common.h"
17
18static const struct regmap_config owl_regmap_config = {
19 .reg_bits = 32,
20 .reg_stride = 4,
21 .val_bits = 32,
22 .max_register = 0x00cc,
23 .fast_io = true,
24};
25
26static void owl_clk_set_regmap(const struct owl_clk_desc *desc,
27 struct regmap *regmap)
28{
29 int i;
30 struct owl_clk_common *clks;
31
32 for (i = 0; i < desc->num_clks; i++) {
33 clks = desc->clks[i];
34 if (!clks)
35 continue;
36
37 clks->regmap = regmap;
38 }
39}
40
41int owl_clk_regmap_init(struct platform_device *pdev,
42 const struct owl_clk_desc *desc)
43{
44 void __iomem *base;
45 struct regmap *regmap;
46 struct resource *res;
47
48 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
49 base = devm_ioremap_resource(&pdev->dev, res);
50 if (IS_ERR(base))
51 return PTR_ERR(base);
52
53 regmap = devm_regmap_init_mmio(&pdev->dev, base, &owl_regmap_config);
54 if (IS_ERR(regmap)) {
55 pr_err("failed to init regmap\n");
56 return PTR_ERR(regmap);
57 }
58
59 owl_clk_set_regmap(desc, regmap);
60
61 return 0;
62}
63
64int owl_clk_probe(struct device *dev, struct clk_hw_onecell_data *hw_clks)
65{
66 int i, ret;
67 struct clk_hw *hw;
68
69 for (i = 0; i < hw_clks->num; i++) {
70
71 hw = hw_clks->hws[i];
72
73 if (IS_ERR_OR_NULL(hw))
74 continue;
75
76 ret = devm_clk_hw_register(dev, hw);
77 if (ret) {
78 dev_err(dev, "Couldn't register clock %d - %s\n",
79 i, hw->init->name);
80 return ret;
81 }
82 }
83
84 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_clks);
85 if (ret)
86 dev_err(dev, "Failed to add clock provider\n");
87
88 return ret;
89}
diff --git a/drivers/clk/actions/owl-common.h b/drivers/clk/actions/owl-common.h
new file mode 100644
index 000000000000..4fd726ec54a6
--- /dev/null
+++ b/drivers/clk/actions/owl-common.h
@@ -0,0 +1,41 @@
1// SPDX-License-Identifier: GPL-2.0+
2//
3// OWL common clock driver
4//
5// Copyright (c) 2014 Actions Semi Inc.
6// Author: David Liu <liuwei@actions-semi.com>
7//
8// Copyright (c) 2018 Linaro Ltd.
9// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10
11#ifndef _OWL_COMMON_H_
12#define _OWL_COMMON_H_
13
14#include <linux/clk-provider.h>
15#include <linux/of_platform.h>
16#include <linux/regmap.h>
17
18struct device_node;
19
20struct owl_clk_common {
21 struct regmap *regmap;
22 struct clk_hw hw;
23};
24
25struct owl_clk_desc {
26 struct owl_clk_common **clks;
27 unsigned long num_clks;
28 struct clk_hw_onecell_data *hw_clks;
29};
30
31static inline struct owl_clk_common *
32 hw_to_owl_clk_common(const struct clk_hw *hw)
33{
34 return container_of(hw, struct owl_clk_common, hw);
35}
36
37int owl_clk_regmap_init(struct platform_device *pdev,
38 const struct owl_clk_desc *desc);
39int owl_clk_probe(struct device *dev, struct clk_hw_onecell_data *hw_clks);
40
41#endif /* _OWL_COMMON_H_ */
diff --git a/drivers/clk/actions/owl-composite.c b/drivers/clk/actions/owl-composite.c
new file mode 100644
index 000000000000..101706e0c66f
--- /dev/null
+++ b/drivers/clk/actions/owl-composite.c
@@ -0,0 +1,199 @@
1// SPDX-License-Identifier: GPL-2.0+
2//
3// OWL composite clock driver
4//
5// Copyright (c) 2014 Actions Semi Inc.
6// Author: David Liu <liuwei@actions-semi.com>
7//
8// Copyright (c) 2018 Linaro Ltd.
9// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10
11#include <linux/clk-provider.h>
12#include <linux/regmap.h>
13
14#include "owl-composite.h"
15
16static u8 owl_comp_get_parent(struct clk_hw *hw)
17{
18 struct owl_composite *comp = hw_to_owl_comp(hw);
19
20 return owl_mux_helper_get_parent(&comp->common, &comp->mux_hw);
21}
22
23static int owl_comp_set_parent(struct clk_hw *hw, u8 index)
24{
25 struct owl_composite *comp = hw_to_owl_comp(hw);
26
27 return owl_mux_helper_set_parent(&comp->common, &comp->mux_hw, index);
28}
29
30static void owl_comp_disable(struct clk_hw *hw)
31{
32 struct owl_composite *comp = hw_to_owl_comp(hw);
33 struct owl_clk_common *common = &comp->common;
34
35 owl_gate_set(common, &comp->gate_hw, false);
36}
37
38static int owl_comp_enable(struct clk_hw *hw)
39{
40 struct owl_composite *comp = hw_to_owl_comp(hw);
41 struct owl_clk_common *common = &comp->common;
42
43 owl_gate_set(common, &comp->gate_hw, true);
44
45 return 0;
46}
47
48static int owl_comp_is_enabled(struct clk_hw *hw)
49{
50 struct owl_composite *comp = hw_to_owl_comp(hw);
51 struct owl_clk_common *common = &comp->common;
52
53 return owl_gate_clk_is_enabled(common, &comp->gate_hw);
54}
55
56static long owl_comp_div_round_rate(struct clk_hw *hw, unsigned long rate,
57 unsigned long *parent_rate)
58{
59 struct owl_composite *comp = hw_to_owl_comp(hw);
60
61 return owl_divider_helper_round_rate(&comp->common, &comp->rate.div_hw,
62 rate, parent_rate);
63}
64
65static unsigned long owl_comp_div_recalc_rate(struct clk_hw *hw,
66 unsigned long parent_rate)
67{
68 struct owl_composite *comp = hw_to_owl_comp(hw);
69
70 return owl_divider_helper_recalc_rate(&comp->common, &comp->rate.div_hw,
71 parent_rate);
72}
73
74static int owl_comp_div_set_rate(struct clk_hw *hw, unsigned long rate,
75 unsigned long parent_rate)
76{
77 struct owl_composite *comp = hw_to_owl_comp(hw);
78
79 return owl_divider_helper_set_rate(&comp->common, &comp->rate.div_hw,
80 rate, parent_rate);
81}
82
83static long owl_comp_fact_round_rate(struct clk_hw *hw, unsigned long rate,
84 unsigned long *parent_rate)
85{
86 struct owl_composite *comp = hw_to_owl_comp(hw);
87
88 return owl_factor_helper_round_rate(&comp->common,
89 &comp->rate.factor_hw,
90 rate, parent_rate);
91}
92
93static unsigned long owl_comp_fact_recalc_rate(struct clk_hw *hw,
94 unsigned long parent_rate)
95{
96 struct owl_composite *comp = hw_to_owl_comp(hw);
97
98 return owl_factor_helper_recalc_rate(&comp->common,
99 &comp->rate.factor_hw,
100 parent_rate);
101}
102
103static int owl_comp_fact_set_rate(struct clk_hw *hw, unsigned long rate,
104 unsigned long parent_rate)
105{
106 struct owl_composite *comp = hw_to_owl_comp(hw);
107
108 return owl_factor_helper_set_rate(&comp->common,
109 &comp->rate.factor_hw,
110 rate, parent_rate);
111}
112
113static long owl_comp_fix_fact_round_rate(struct clk_hw *hw, unsigned long rate,
114 unsigned long *parent_rate)
115{
116 struct owl_composite *comp = hw_to_owl_comp(hw);
117 struct clk_fixed_factor *fix_fact_hw = &comp->rate.fix_fact_hw;
118
119 return comp->fix_fact_ops->round_rate(&fix_fact_hw->hw, rate, parent_rate);
120}
121
122static unsigned long owl_comp_fix_fact_recalc_rate(struct clk_hw *hw,
123 unsigned long parent_rate)
124{
125 struct owl_composite *comp = hw_to_owl_comp(hw);
126 struct clk_fixed_factor *fix_fact_hw = &comp->rate.fix_fact_hw;
127
128 return comp->fix_fact_ops->recalc_rate(&fix_fact_hw->hw, parent_rate);
129
130}
131
132static int owl_comp_fix_fact_set_rate(struct clk_hw *hw, unsigned long rate,
133 unsigned long parent_rate)
134{
135 /*
136 * We must report success but we can do so unconditionally because
137 * owl_comp_fix_fact_round_rate returns values that ensure this call is
138 * a nop.
139 */
140
141 return 0;
142}
143
144const struct clk_ops owl_comp_div_ops = {
145 /* mux_ops */
146 .get_parent = owl_comp_get_parent,
147 .set_parent = owl_comp_set_parent,
148
149 /* gate_ops */
150 .disable = owl_comp_disable,
151 .enable = owl_comp_enable,
152 .is_enabled = owl_comp_is_enabled,
153
154 /* div_ops */
155 .round_rate = owl_comp_div_round_rate,
156 .recalc_rate = owl_comp_div_recalc_rate,
157 .set_rate = owl_comp_div_set_rate,
158};
159
160
161const struct clk_ops owl_comp_fact_ops = {
162 /* mux_ops */
163 .get_parent = owl_comp_get_parent,
164 .set_parent = owl_comp_set_parent,
165
166 /* gate_ops */
167 .disable = owl_comp_disable,
168 .enable = owl_comp_enable,
169 .is_enabled = owl_comp_is_enabled,
170
171 /* fact_ops */
172 .round_rate = owl_comp_fact_round_rate,
173 .recalc_rate = owl_comp_fact_recalc_rate,
174 .set_rate = owl_comp_fact_set_rate,
175};
176
177const struct clk_ops owl_comp_fix_fact_ops = {
178 /* gate_ops */
179 .disable = owl_comp_disable,
180 .enable = owl_comp_enable,
181 .is_enabled = owl_comp_is_enabled,
182
183 /* fix_fact_ops */
184 .round_rate = owl_comp_fix_fact_round_rate,
185 .recalc_rate = owl_comp_fix_fact_recalc_rate,
186 .set_rate = owl_comp_fix_fact_set_rate,
187};
188
189
190const struct clk_ops owl_comp_pass_ops = {
191 /* mux_ops */
192 .get_parent = owl_comp_get_parent,
193 .set_parent = owl_comp_set_parent,
194
195 /* gate_ops */
196 .disable = owl_comp_disable,
197 .enable = owl_comp_enable,
198 .is_enabled = owl_comp_is_enabled,
199};
diff --git a/drivers/clk/actions/owl-composite.h b/drivers/clk/actions/owl-composite.h
new file mode 100644
index 000000000000..b410ed5bf308
--- /dev/null
+++ b/drivers/clk/actions/owl-composite.h
@@ -0,0 +1,124 @@
1// SPDX-License-Identifier: GPL-2.0+
2//
3// OWL composite clock driver
4//
5// Copyright (c) 2014 Actions Semi Inc.
6// Author: David Liu <liuwei@actions-semi.com>
7//
8// Copyright (c) 2018 Linaro Ltd.
9// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10
11#ifndef _OWL_COMPOSITE_H_
12#define _OWL_COMPOSITE_H_
13
14#include "owl-common.h"
15#include "owl-mux.h"
16#include "owl-gate.h"
17#include "owl-factor.h"
18#include "owl-fixed-factor.h"
19#include "owl-divider.h"
20
21union owl_rate {
22 struct owl_divider_hw div_hw;
23 struct owl_factor_hw factor_hw;
24 struct clk_fixed_factor fix_fact_hw;
25};
26
27struct owl_composite {
28 struct owl_mux_hw mux_hw;
29 struct owl_gate_hw gate_hw;
30 union owl_rate rate;
31
32 const struct clk_ops *fix_fact_ops;
33
34 struct owl_clk_common common;
35};
36
37#define OWL_COMP_DIV(_struct, _name, _parent, \
38 _mux, _gate, _div, _flags) \
39 struct owl_composite _struct = { \
40 .mux_hw = _mux, \
41 .gate_hw = _gate, \
42 .rate.div_hw = _div, \
43 .common = { \
44 .regmap = NULL, \
45 .hw.init = CLK_HW_INIT_PARENTS(_name, \
46 _parent, \
47 &owl_comp_div_ops,\
48 _flags), \
49 }, \
50 }
51
52#define OWL_COMP_DIV_FIXED(_struct, _name, _parent, \
53 _gate, _div, _flags) \
54 struct owl_composite _struct = { \
55 .gate_hw = _gate, \
56 .rate.div_hw = _div, \
57 .common = { \
58 .regmap = NULL, \
59 .hw.init = CLK_HW_INIT(_name, \
60 _parent, \
61 &owl_comp_div_ops,\
62 _flags), \
63 }, \
64 }
65
66#define OWL_COMP_FACTOR(_struct, _name, _parent, \
67 _mux, _gate, _factor, _flags) \
68 struct owl_composite _struct = { \
69 .mux_hw = _mux, \
70 .gate_hw = _gate, \
71 .rate.factor_hw = _factor, \
72 .common = { \
73 .regmap = NULL, \
74 .hw.init = CLK_HW_INIT_PARENTS(_name, \
75 _parent, \
76 &owl_comp_fact_ops,\
77 _flags), \
78 }, \
79 }
80
81#define OWL_COMP_FIXED_FACTOR(_struct, _name, _parent, \
82 _gate, _mul, _div, _flags) \
83 struct owl_composite _struct = { \
84 .gate_hw = _gate, \
85 .rate.fix_fact_hw.mult = _mul, \
86 .rate.fix_fact_hw.div = _div, \
87 .fix_fact_ops = &clk_fixed_factor_ops, \
88 .common = { \
89 .regmap = NULL, \
90 .hw.init = CLK_HW_INIT(_name, \
91 _parent, \
92 &owl_comp_fix_fact_ops,\
93 _flags), \
94 }, \
95 }
96
97#define OWL_COMP_PASS(_struct, _name, _parent, \
98 _mux, _gate, _flags) \
99 struct owl_composite _struct = { \
100 .mux_hw = _mux, \
101 .gate_hw = _gate, \
102 .common = { \
103 .regmap = NULL, \
104 .hw.init = CLK_HW_INIT_PARENTS(_name, \
105 _parent, \
106 &owl_comp_pass_ops,\
107 _flags), \
108 }, \
109 }
110
111static inline struct owl_composite *hw_to_owl_comp(const struct clk_hw *hw)
112{
113 struct owl_clk_common *common = hw_to_owl_clk_common(hw);
114
115 return container_of(common, struct owl_composite, common);
116}
117
118extern const struct clk_ops owl_comp_div_ops;
119extern const struct clk_ops owl_comp_fact_ops;
120extern const struct clk_ops owl_comp_fix_fact_ops;
121extern const struct clk_ops owl_comp_pass_ops;
122extern const struct clk_ops clk_fixed_factor_ops;
123
124#endif /* _OWL_COMPOSITE_H_ */
diff --git a/drivers/clk/actions/owl-divider.c b/drivers/clk/actions/owl-divider.c
new file mode 100644
index 000000000000..cddac00fe324
--- /dev/null
+++ b/drivers/clk/actions/owl-divider.c
@@ -0,0 +1,94 @@
1// SPDX-License-Identifier: GPL-2.0+
2//
3// OWL divider clock driver
4//
5// Copyright (c) 2014 Actions Semi Inc.
6// Author: David Liu <liuwei@actions-semi.com>
7//
8// Copyright (c) 2018 Linaro Ltd.
9// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10
11#include <linux/clk-provider.h>
12#include <linux/regmap.h>
13
14#include "owl-divider.h"
15
16long owl_divider_helper_round_rate(struct owl_clk_common *common,
17 const struct owl_divider_hw *div_hw,
18 unsigned long rate,
19 unsigned long *parent_rate)
20{
21 return divider_round_rate(&common->hw, rate, parent_rate,
22 div_hw->table, div_hw->width,
23 div_hw->div_flags);
24}
25
26static long owl_divider_round_rate(struct clk_hw *hw, unsigned long rate,
27 unsigned long *parent_rate)
28{
29 struct owl_divider *div = hw_to_owl_divider(hw);
30
31 return owl_divider_helper_round_rate(&div->common, &div->div_hw,
32 rate, parent_rate);
33}
34
35unsigned long owl_divider_helper_recalc_rate(struct owl_clk_common *common,
36 const struct owl_divider_hw *div_hw,
37 unsigned long parent_rate)
38{
39 unsigned long val;
40 unsigned int reg;
41
42 regmap_read(common->regmap, div_hw->reg, &reg);
43 val = reg >> div_hw->shift;
44 val &= (1 << div_hw->width) - 1;
45
46 return divider_recalc_rate(&common->hw, parent_rate,
47 val, div_hw->table,
48 div_hw->div_flags,
49 div_hw->width);
50}
51
52static unsigned long owl_divider_recalc_rate(struct clk_hw *hw,
53 unsigned long parent_rate)
54{
55 struct owl_divider *div = hw_to_owl_divider(hw);
56
57 return owl_divider_helper_recalc_rate(&div->common,
58 &div->div_hw, parent_rate);
59}
60
61int owl_divider_helper_set_rate(const struct owl_clk_common *common,
62 const struct owl_divider_hw *div_hw,
63 unsigned long rate,
64 unsigned long parent_rate)
65{
66 unsigned long val;
67 unsigned int reg;
68
69 val = divider_get_val(rate, parent_rate, div_hw->table,
70 div_hw->width, 0);
71
72 regmap_read(common->regmap, div_hw->reg, &reg);
73 reg &= ~GENMASK(div_hw->width + div_hw->shift - 1, div_hw->shift);
74
75 regmap_write(common->regmap, div_hw->reg,
76 reg | (val << div_hw->shift));
77
78 return 0;
79}
80
81static int owl_divider_set_rate(struct clk_hw *hw, unsigned long rate,
82 unsigned long parent_rate)
83{
84 struct owl_divider *div = hw_to_owl_divider(hw);
85
86 return owl_divider_helper_set_rate(&div->common, &div->div_hw,
87 rate, parent_rate);
88}
89
90const struct clk_ops owl_divider_ops = {
91 .recalc_rate = owl_divider_recalc_rate,
92 .round_rate = owl_divider_round_rate,
93 .set_rate = owl_divider_set_rate,
94};
diff --git a/drivers/clk/actions/owl-divider.h b/drivers/clk/actions/owl-divider.h
new file mode 100644
index 000000000000..92d3e3d23967
--- /dev/null
+++ b/drivers/clk/actions/owl-divider.h
@@ -0,0 +1,75 @@
1// SPDX-License-Identifier: GPL-2.0+
2//
3// OWL divider clock driver
4//
5// Copyright (c) 2014 Actions Semi Inc.
6// Author: David Liu <liuwei@actions-semi.com>
7//
8// Copyright (c) 2018 Linaro Ltd.
9// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10
11#ifndef _OWL_DIVIDER_H_
12#define _OWL_DIVIDER_H_
13
14#include "owl-common.h"
15
16struct owl_divider_hw {
17 u32 reg;
18 u8 shift;
19 u8 width;
20 u8 div_flags;
21 struct clk_div_table *table;
22};
23
24struct owl_divider {
25 struct owl_divider_hw div_hw;
26 struct owl_clk_common common;
27};
28
29#define OWL_DIVIDER_HW(_reg, _shift, _width, _div_flags, _table) \
30 { \
31 .reg = _reg, \
32 .shift = _shift, \
33 .width = _width, \
34 .div_flags = _div_flags, \
35 .table = _table, \
36 }
37
38#define OWL_DIVIDER(_struct, _name, _parent, _reg, \
39 _shift, _width, _table, _div_flags, _flags) \
40 struct owl_divider _struct = { \
41 .div_hw = OWL_DIVIDER_HW(_reg, _shift, _width, \
42 _div_flags, _table), \
43 .common = { \
44 .regmap = NULL, \
45 .hw.init = CLK_HW_INIT(_name, \
46 _parent, \
47 &owl_divider_ops, \
48 _flags), \
49 }, \
50 }
51
52static inline struct owl_divider *hw_to_owl_divider(const struct clk_hw *hw)
53{
54 struct owl_clk_common *common = hw_to_owl_clk_common(hw);
55
56 return container_of(common, struct owl_divider, common);
57}
58
59long owl_divider_helper_round_rate(struct owl_clk_common *common,
60 const struct owl_divider_hw *div_hw,
61 unsigned long rate,
62 unsigned long *parent_rate);
63
64unsigned long owl_divider_helper_recalc_rate(struct owl_clk_common *common,
65 const struct owl_divider_hw *div_hw,
66 unsigned long parent_rate);
67
68int owl_divider_helper_set_rate(const struct owl_clk_common *common,
69 const struct owl_divider_hw *div_hw,
70 unsigned long rate,
71 unsigned long parent_rate);
72
73extern const struct clk_ops owl_divider_ops;
74
75#endif /* _OWL_DIVIDER_H_ */
diff --git a/drivers/clk/actions/owl-factor.c b/drivers/clk/actions/owl-factor.c
new file mode 100644
index 000000000000..317d4a9e112e
--- /dev/null
+++ b/drivers/clk/actions/owl-factor.c
@@ -0,0 +1,222 @@
1// SPDX-License-Identifier: GPL-2.0+
2//
3// OWL factor clock driver
4//
5// Copyright (c) 2014 Actions Semi Inc.
6// Author: David Liu <liuwei@actions-semi.com>
7//
8// Copyright (c) 2018 Linaro Ltd.
9// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10
11#include <linux/clk-provider.h>
12#include <linux/regmap.h>
13#include <linux/slab.h>
14
15#include "owl-factor.h"
16
17static unsigned int _get_table_maxval(const struct clk_factor_table *table)
18{
19 unsigned int maxval = 0;
20 const struct clk_factor_table *clkt;
21
22 for (clkt = table; clkt->div; clkt++)
23 if (clkt->val > maxval)
24 maxval = clkt->val;
25 return maxval;
26}
27
28static int _get_table_div_mul(const struct clk_factor_table *table,
29 unsigned int val, unsigned int *mul, unsigned int *div)
30{
31 const struct clk_factor_table *clkt;
32
33 for (clkt = table; clkt->div; clkt++) {
34 if (clkt->val == val) {
35 *mul = clkt->mul;
36 *div = clkt->div;
37 return 1;
38 }
39 }
40
41 return 0;
42}
43
44static unsigned int _get_table_val(const struct clk_factor_table *table,
45 unsigned long rate, unsigned long parent_rate)
46{
47 const struct clk_factor_table *clkt;
48 int val = -1;
49 u64 calc_rate;
50
51 for (clkt = table; clkt->div; clkt++) {
52 calc_rate = parent_rate * clkt->mul;
53 do_div(calc_rate, clkt->div);
54
55 if ((unsigned long)calc_rate <= rate) {
56 val = clkt->val;
57 break;
58 }
59 }
60
61 if (val == -1)
62 val = _get_table_maxval(table);
63
64 return val;
65}
66
67static int clk_val_best(struct clk_hw *hw, unsigned long rate,
68 unsigned long *best_parent_rate)
69{
70 struct owl_factor *factor = hw_to_owl_factor(hw);
71 struct owl_factor_hw *factor_hw = &factor->factor_hw;
72 const struct clk_factor_table *clkt = factor_hw->table;
73 unsigned long parent_rate, try_parent_rate, best = 0, cur_rate;
74 unsigned long parent_rate_saved = *best_parent_rate;
75 int bestval = 0;
76
77 if (!rate)
78 rate = 1;
79
80 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
81 parent_rate = *best_parent_rate;
82 bestval = _get_table_val(clkt, rate, parent_rate);
83 return bestval;
84 }
85
86 for (clkt = factor_hw->table; clkt->div; clkt++) {
87 try_parent_rate = rate * clkt->div / clkt->mul;
88
89 if (try_parent_rate == parent_rate_saved) {
90 pr_debug("%s: [%d %d %d] found try_parent_rate %ld\n",
91 __func__, clkt->val, clkt->mul, clkt->div,
92 try_parent_rate);
93 /*
94 * It's the most ideal case if the requested rate can be
95 * divided from parent clock without any need to change
96 * parent rate, so return the divider immediately.
97 */
98 *best_parent_rate = parent_rate_saved;
99 return clkt->val;
100 }
101
102 parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
103 try_parent_rate);
104 cur_rate = DIV_ROUND_UP(parent_rate, clkt->div) * clkt->mul;
105 if (cur_rate <= rate && cur_rate > best) {
106 bestval = clkt->val;
107 best = cur_rate;
108 *best_parent_rate = parent_rate;
109 }
110 }
111
112 if (!bestval) {
113 bestval = _get_table_maxval(clkt);
114 *best_parent_rate = clk_hw_round_rate(
115 clk_hw_get_parent(hw), 1);
116 }
117
118 return bestval;
119}
120
121long owl_factor_helper_round_rate(struct owl_clk_common *common,
122 const struct owl_factor_hw *factor_hw,
123 unsigned long rate,
124 unsigned long *parent_rate)
125{
126 const struct clk_factor_table *clkt = factor_hw->table;
127 unsigned int val, mul = 0, div = 1;
128
129 val = clk_val_best(&common->hw, rate, parent_rate);
130 _get_table_div_mul(clkt, val, &mul, &div);
131
132 return *parent_rate * mul / div;
133}
134
135static long owl_factor_round_rate(struct clk_hw *hw, unsigned long rate,
136 unsigned long *parent_rate)
137{
138 struct owl_factor *factor = hw_to_owl_factor(hw);
139 struct owl_factor_hw *factor_hw = &factor->factor_hw;
140
141 return owl_factor_helper_round_rate(&factor->common, factor_hw,
142 rate, parent_rate);
143}
144
145unsigned long owl_factor_helper_recalc_rate(struct owl_clk_common *common,
146 const struct owl_factor_hw *factor_hw,
147 unsigned long parent_rate)
148{
149 const struct clk_factor_table *clkt = factor_hw->table;
150 unsigned long long int rate;
151 u32 reg, val, mul, div;
152
153 div = 0;
154 mul = 0;
155
156 regmap_read(common->regmap, factor_hw->reg, &reg);
157
158 val = reg >> factor_hw->shift;
159 val &= div_mask(factor_hw);
160
161 _get_table_div_mul(clkt, val, &mul, &div);
162 if (!div) {
163 WARN(!(factor_hw->fct_flags & CLK_DIVIDER_ALLOW_ZERO),
164 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
165 __clk_get_name(common->hw.clk));
166 return parent_rate;
167 }
168
169 rate = (unsigned long long int)parent_rate * mul;
170 do_div(rate, div);
171
172 return rate;
173}
174
175static unsigned long owl_factor_recalc_rate(struct clk_hw *hw,
176 unsigned long parent_rate)
177{
178 struct owl_factor *factor = hw_to_owl_factor(hw);
179 struct owl_factor_hw *factor_hw = &factor->factor_hw;
180 struct owl_clk_common *common = &factor->common;
181
182 return owl_factor_helper_recalc_rate(common, factor_hw, parent_rate);
183}
184
185int owl_factor_helper_set_rate(const struct owl_clk_common *common,
186 const struct owl_factor_hw *factor_hw,
187 unsigned long rate,
188 unsigned long parent_rate)
189{
190 u32 val, reg;
191
192 val = _get_table_val(factor_hw->table, rate, parent_rate);
193
194 if (val > div_mask(factor_hw))
195 val = div_mask(factor_hw);
196
197 regmap_read(common->regmap, factor_hw->reg, &reg);
198
199 reg &= ~(div_mask(factor_hw) << factor_hw->shift);
200 reg |= val << factor_hw->shift;
201
202 regmap_write(common->regmap, factor_hw->reg, reg);
203
204 return 0;
205}
206
207static int owl_factor_set_rate(struct clk_hw *hw, unsigned long rate,
208 unsigned long parent_rate)
209{
210 struct owl_factor *factor = hw_to_owl_factor(hw);
211 struct owl_factor_hw *factor_hw = &factor->factor_hw;
212 struct owl_clk_common *common = &factor->common;
213
214 return owl_factor_helper_set_rate(common, factor_hw,
215 rate, parent_rate);
216}
217
218const struct clk_ops owl_factor_ops = {
219 .round_rate = owl_factor_round_rate,
220 .recalc_rate = owl_factor_recalc_rate,
221 .set_rate = owl_factor_set_rate,
222};
diff --git a/drivers/clk/actions/owl-factor.h b/drivers/clk/actions/owl-factor.h
new file mode 100644
index 000000000000..f1a7ffe896e1
--- /dev/null
+++ b/drivers/clk/actions/owl-factor.h
@@ -0,0 +1,83 @@
1// SPDX-License-Identifier: GPL-2.0+
2//
3// OWL factor clock driver
4//
5// Copyright (c) 2014 Actions Semi Inc.
6// Author: David Liu <liuwei@actions-semi.com>
7//
8// Copyright (c) 2018 Linaro Ltd.
9// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10
11#ifndef _OWL_FACTOR_H_
12#define _OWL_FACTOR_H_
13
14#include "owl-common.h"
15
16struct clk_factor_table {
17 unsigned int val;
18 unsigned int mul;
19 unsigned int div;
20};
21
22struct owl_factor_hw {
23 u32 reg;
24 u8 shift;
25 u8 width;
26 u8 fct_flags;
27 struct clk_factor_table *table;
28};
29
30struct owl_factor {
31 struct owl_factor_hw factor_hw;
32 struct owl_clk_common common;
33};
34
35#define OWL_FACTOR_HW(_reg, _shift, _width, _fct_flags, _table) \
36 { \
37 .reg = _reg, \
38 .shift = _shift, \
39 .width = _width, \
40 .fct_flags = _fct_flags, \
41 .table = _table, \
42 }
43
44#define OWL_FACTOR(_struct, _name, _parent, _reg, \
45 _shift, _width, _table, _fct_flags, _flags) \
46 struct owl_factor _struct = { \
47 .factor_hw = OWL_FACTOR_HW(_reg, _shift, \
48 _width, _fct_flags, _table), \
49 .common = { \
50 .regmap = NULL, \
51 .hw.init = CLK_HW_INIT(_name, \
52 _parent, \
53 &owl_factor_ops, \
54 _flags), \
55 }, \
56 }
57
58#define div_mask(d) ((1 << ((d)->width)) - 1)
59
60static inline struct owl_factor *hw_to_owl_factor(const struct clk_hw *hw)
61{
62 struct owl_clk_common *common = hw_to_owl_clk_common(hw);
63
64 return container_of(common, struct owl_factor, common);
65}
66
67long owl_factor_helper_round_rate(struct owl_clk_common *common,
68 const struct owl_factor_hw *factor_hw,
69 unsigned long rate,
70 unsigned long *parent_rate);
71
72unsigned long owl_factor_helper_recalc_rate(struct owl_clk_common *common,
73 const struct owl_factor_hw *factor_hw,
74 unsigned long parent_rate);
75
76int owl_factor_helper_set_rate(const struct owl_clk_common *common,
77 const struct owl_factor_hw *factor_hw,
78 unsigned long rate,
79 unsigned long parent_rate);
80
81extern const struct clk_ops owl_factor_ops;
82
83#endif /* _OWL_FACTOR_H_ */
diff --git a/drivers/clk/actions/owl-fixed-factor.h b/drivers/clk/actions/owl-fixed-factor.h
new file mode 100644
index 000000000000..cc9fe36c0964
--- /dev/null
+++ b/drivers/clk/actions/owl-fixed-factor.h
@@ -0,0 +1,28 @@
1// SPDX-License-Identifier: GPL-2.0+
2//
3// OWL fixed factor clock driver
4//
5// Copyright (c) 2014 Actions Semi Inc.
6// Author: David Liu <liuwei@actions-semi.com>
7//
8// Copyright (c) 2018 Linaro Ltd.
9// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10
11#ifndef _OWL_FIXED_FACTOR_H_
12#define _OWL_FIXED_FACTOR_H_
13
14#include "owl-common.h"
15
16#define OWL_FIX_FACT(_struct, _name, _parent, _mul, _div, _flags) \
17 struct clk_fixed_factor _struct = { \
18 .mult = _mul, \
19 .div = _div, \
20 .hw.init = CLK_HW_INIT(_name, \
21 _parent, \
22 &clk_fixed_factor_ops, \
23 _flags), \
24 }
25
26extern const struct clk_ops clk_fixed_factor_ops;
27
28#endif /* _OWL_FIXED_FACTOR_H_ */
diff --git a/drivers/clk/actions/owl-gate.c b/drivers/clk/actions/owl-gate.c
new file mode 100644
index 000000000000..f11500ba46a7
--- /dev/null
+++ b/drivers/clk/actions/owl-gate.c
@@ -0,0 +1,77 @@
1// SPDX-License-Identifier: GPL-2.0+
2//
3// OWL gate clock driver
4//
5// Copyright (c) 2014 Actions Semi Inc.
6// Author: David Liu <liuwei@actions-semi.com>
7//
8// Copyright (c) 2018 Linaro Ltd.
9// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10
11#include <linux/clk-provider.h>
12#include <linux/regmap.h>
13
14#include "owl-gate.h"
15
16void owl_gate_set(const struct owl_clk_common *common,
17 const struct owl_gate_hw *gate_hw, bool enable)
18{
19 int set = gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
20 u32 reg;
21
22 set ^= enable;
23
24 regmap_read(common->regmap, gate_hw->reg, &reg);
25
26 if (set)
27 reg |= BIT(gate_hw->bit_idx);
28 else
29 reg &= ~BIT(gate_hw->bit_idx);
30
31 regmap_write(common->regmap, gate_hw->reg, reg);
32}
33
34static void owl_gate_disable(struct clk_hw *hw)
35{
36 struct owl_gate *gate = hw_to_owl_gate(hw);
37 struct owl_clk_common *common = &gate->common;
38
39 owl_gate_set(common, &gate->gate_hw, false);
40}
41
42static int owl_gate_enable(struct clk_hw *hw)
43{
44 struct owl_gate *gate = hw_to_owl_gate(hw);
45 struct owl_clk_common *common = &gate->common;
46
47 owl_gate_set(common, &gate->gate_hw, true);
48
49 return 0;
50}
51
52int owl_gate_clk_is_enabled(const struct owl_clk_common *common,
53 const struct owl_gate_hw *gate_hw)
54{
55 u32 reg;
56
57 regmap_read(common->regmap, gate_hw->reg, &reg);
58
59 if (gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE)
60 reg ^= BIT(gate_hw->bit_idx);
61
62 return !!(reg & BIT(gate_hw->bit_idx));
63}
64
65static int owl_gate_is_enabled(struct clk_hw *hw)
66{
67 struct owl_gate *gate = hw_to_owl_gate(hw);
68 struct owl_clk_common *common = &gate->common;
69
70 return owl_gate_clk_is_enabled(common, &gate->gate_hw);
71}
72
73const struct clk_ops owl_gate_ops = {
74 .disable = owl_gate_disable,
75 .enable = owl_gate_enable,
76 .is_enabled = owl_gate_is_enabled,
77};
diff --git a/drivers/clk/actions/owl-gate.h b/drivers/clk/actions/owl-gate.h
new file mode 100644
index 000000000000..c2d61ceebce2
--- /dev/null
+++ b/drivers/clk/actions/owl-gate.h
@@ -0,0 +1,73 @@
1// SPDX-License-Identifier: GPL-2.0+
2//
3// OWL gate clock driver
4//
5// Copyright (c) 2014 Actions Semi Inc.
6// Author: David Liu <liuwei@actions-semi.com>
7//
8// Copyright (c) 2018 Linaro Ltd.
9// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10
11#ifndef _OWL_GATE_H_
12#define _OWL_GATE_H_
13
14#include "owl-common.h"
15
16struct owl_gate_hw {
17 u32 reg;
18 u8 bit_idx;
19 u8 gate_flags;
20};
21
22struct owl_gate {
23 struct owl_gate_hw gate_hw;
24 struct owl_clk_common common;
25};
26
27#define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \
28 { \
29 .reg = _reg, \
30 .bit_idx = _bit_idx, \
31 .gate_flags = _gate_flags, \
32 }
33
34#define OWL_GATE(_struct, _name, _parent, _reg, \
35 _bit_idx, _gate_flags, _flags) \
36 struct owl_gate _struct = { \
37 .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
38 .common = { \
39 .regmap = NULL, \
40 .hw.init = CLK_HW_INIT(_name, \
41 _parent, \
42 &owl_gate_ops, \
43 _flags), \
44 } \
45 } \
46
47#define OWL_GATE_NO_PARENT(_struct, _name, _reg, \
48 _bit_idx, _gate_flags, _flags) \
49 struct owl_gate _struct = { \
50 .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
51 .common = { \
52 .regmap = NULL, \
53 .hw.init = CLK_HW_INIT_NO_PARENT(_name, \
54 &owl_gate_ops, \
55 _flags), \
56 }, \
57 } \
58
59static inline struct owl_gate *hw_to_owl_gate(const struct clk_hw *hw)
60{
61 struct owl_clk_common *common = hw_to_owl_clk_common(hw);
62
63 return container_of(common, struct owl_gate, common);
64}
65
66void owl_gate_set(const struct owl_clk_common *common,
67 const struct owl_gate_hw *gate_hw, bool enable);
68int owl_gate_clk_is_enabled(const struct owl_clk_common *common,
69 const struct owl_gate_hw *gate_hw);
70
71extern const struct clk_ops owl_gate_ops;
72
73#endif /* _OWL_GATE_H_ */
diff --git a/drivers/clk/actions/owl-mux.c b/drivers/clk/actions/owl-mux.c
new file mode 100644
index 000000000000..f9c6cf2540e4
--- /dev/null
+++ b/drivers/clk/actions/owl-mux.c
@@ -0,0 +1,60 @@
1// SPDX-License-Identifier: GPL-2.0+
2//
3// OWL mux clock driver
4//
5// Copyright (c) 2014 Actions Semi Inc.
6// Author: David Liu <liuwei@actions-semi.com>
7//
8// Copyright (c) 2018 Linaro Ltd.
9// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10
11#include <linux/clk-provider.h>
12#include <linux/regmap.h>
13
14#include "owl-mux.h"
15
16u8 owl_mux_helper_get_parent(const struct owl_clk_common *common,
17 const struct owl_mux_hw *mux_hw)
18{
19 u32 reg;
20 u8 parent;
21
22 regmap_read(common->regmap, mux_hw->reg, &reg);
23 parent = reg >> mux_hw->shift;
24 parent &= BIT(mux_hw->width) - 1;
25
26 return parent;
27}
28
29static u8 owl_mux_get_parent(struct clk_hw *hw)
30{
31 struct owl_mux *mux = hw_to_owl_mux(hw);
32
33 return owl_mux_helper_get_parent(&mux->common, &mux->mux_hw);
34}
35
36int owl_mux_helper_set_parent(const struct owl_clk_common *common,
37 struct owl_mux_hw *mux_hw, u8 index)
38{
39 u32 reg;
40
41 regmap_read(common->regmap, mux_hw->reg, &reg);
42 reg &= ~GENMASK(mux_hw->width + mux_hw->shift - 1, mux_hw->shift);
43 regmap_write(common->regmap, mux_hw->reg,
44 reg | (index << mux_hw->shift));
45
46 return 0;
47}
48
49static int owl_mux_set_parent(struct clk_hw *hw, u8 index)
50{
51 struct owl_mux *mux = hw_to_owl_mux(hw);
52
53 return owl_mux_helper_set_parent(&mux->common, &mux->mux_hw, index);
54}
55
56const struct clk_ops owl_mux_ops = {
57 .get_parent = owl_mux_get_parent,
58 .set_parent = owl_mux_set_parent,
59 .determine_rate = __clk_mux_determine_rate,
60};
diff --git a/drivers/clk/actions/owl-mux.h b/drivers/clk/actions/owl-mux.h
new file mode 100644
index 000000000000..834284c8c3ae
--- /dev/null
+++ b/drivers/clk/actions/owl-mux.h
@@ -0,0 +1,61 @@
1// SPDX-License-Identifier: GPL-2.0+
2//
3// OWL mux clock driver
4//
5// Copyright (c) 2014 Actions Semi Inc.
6// Author: David Liu <liuwei@actions-semi.com>
7//
8// Copyright (c) 2018 Linaro Ltd.
9// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10
11#ifndef _OWL_MUX_H_
12#define _OWL_MUX_H_
13
14#include "owl-common.h"
15
16struct owl_mux_hw {
17 u32 reg;
18 u8 shift;
19 u8 width;
20};
21
22struct owl_mux {
23 struct owl_mux_hw mux_hw;
24 struct owl_clk_common common;
25};
26
27#define OWL_MUX_HW(_reg, _shift, _width) \
28 { \
29 .reg = _reg, \
30 .shift = _shift, \
31 .width = _width, \
32 }
33
34#define OWL_MUX(_struct, _name, _parents, _reg, \
35 _shift, _width, _flags) \
36 struct owl_mux _struct = { \
37 .mux_hw = OWL_MUX_HW(_reg, _shift, _width), \
38 .common = { \
39 .regmap = NULL, \
40 .hw.init = CLK_HW_INIT_PARENTS(_name, \
41 _parents, \
42 &owl_mux_ops, \
43 _flags), \
44 }, \
45 }
46
47static inline struct owl_mux *hw_to_owl_mux(const struct clk_hw *hw)
48{
49 struct owl_clk_common *common = hw_to_owl_clk_common(hw);
50
51 return container_of(common, struct owl_mux, common);
52}
53
54u8 owl_mux_helper_get_parent(const struct owl_clk_common *common,
55 const struct owl_mux_hw *mux_hw);
56int owl_mux_helper_set_parent(const struct owl_clk_common *common,
57 struct owl_mux_hw *mux_hw, u8 index);
58
59extern const struct clk_ops owl_mux_ops;
60
61#endif /* _OWL_MUX_H_ */
diff --git a/drivers/clk/actions/owl-pll.c b/drivers/clk/actions/owl-pll.c
new file mode 100644
index 000000000000..058e06d7099f
--- /dev/null
+++ b/drivers/clk/actions/owl-pll.c
@@ -0,0 +1,194 @@
1// SPDX-License-Identifier: GPL-2.0+
2//
3// OWL pll clock driver
4//
5// Copyright (c) 2014 Actions Semi Inc.
6// Author: David Liu <liuwei@actions-semi.com>
7//
8// Copyright (c) 2018 Linaro Ltd.
9// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10
11#include <linux/clk-provider.h>
12#include <linux/slab.h>
13#include <linux/io.h>
14#include <linux/delay.h>
15
16#include "owl-pll.h"
17
18static u32 owl_pll_calculate_mul(struct owl_pll_hw *pll_hw, unsigned long rate)
19{
20 u32 mul;
21
22 mul = DIV_ROUND_CLOSEST(rate, pll_hw->bfreq);
23 if (mul < pll_hw->min_mul)
24 mul = pll_hw->min_mul;
25 else if (mul > pll_hw->max_mul)
26 mul = pll_hw->max_mul;
27
28 return mul &= mul_mask(pll_hw);
29}
30
31static unsigned long _get_table_rate(const struct clk_pll_table *table,
32 unsigned int val)
33{
34 const struct clk_pll_table *clkt;
35
36 for (clkt = table; clkt->rate; clkt++)
37 if (clkt->val == val)
38 return clkt->rate;
39
40 return 0;
41}
42
43static const struct clk_pll_table *_get_pll_table(
44 const struct clk_pll_table *table, unsigned long rate)
45{
46 const struct clk_pll_table *clkt;
47
48 for (clkt = table; clkt->rate; clkt++) {
49 if (clkt->rate == rate) {
50 table = clkt;
51 break;
52 } else if (clkt->rate < rate)
53 table = clkt;
54 }
55
56 return table;
57}
58
59static long owl_pll_round_rate(struct clk_hw *hw, unsigned long rate,
60 unsigned long *parent_rate)
61{
62 struct owl_pll *pll = hw_to_owl_pll(hw);
63 struct owl_pll_hw *pll_hw = &pll->pll_hw;
64 const struct clk_pll_table *clkt;
65 u32 mul;
66
67 if (pll_hw->table) {
68 clkt = _get_pll_table(pll_hw->table, rate);
69 return clkt->rate;
70 }
71
72 /* fixed frequency */
73 if (pll_hw->width == 0)
74 return pll_hw->bfreq;
75
76 mul = owl_pll_calculate_mul(pll_hw, rate);
77
78 return pll_hw->bfreq * mul;
79}
80
81static unsigned long owl_pll_recalc_rate(struct clk_hw *hw,
82 unsigned long parent_rate)
83{
84 struct owl_pll *pll = hw_to_owl_pll(hw);
85 struct owl_pll_hw *pll_hw = &pll->pll_hw;
86 const struct owl_clk_common *common = &pll->common;
87 u32 val;
88
89 if (pll_hw->table) {
90 regmap_read(common->regmap, pll_hw->reg, &val);
91
92 val = val >> pll_hw->shift;
93 val &= mul_mask(pll_hw);
94
95 return _get_table_rate(pll_hw->table, val);
96 }
97
98 /* fixed frequency */
99 if (pll_hw->width == 0)
100 return pll_hw->bfreq;
101
102 regmap_read(common->regmap, pll_hw->reg, &val);
103
104 val = val >> pll_hw->shift;
105 val &= mul_mask(pll_hw);
106
107 return pll_hw->bfreq * val;
108}
109
110static int owl_pll_is_enabled(struct clk_hw *hw)
111{
112 struct owl_pll *pll = hw_to_owl_pll(hw);
113 struct owl_pll_hw *pll_hw = &pll->pll_hw;
114 const struct owl_clk_common *common = &pll->common;
115 u32 reg;
116
117 regmap_read(common->regmap, pll_hw->reg, &reg);
118
119 return !!(reg & BIT(pll_hw->bit_idx));
120}
121
122static void owl_pll_set(const struct owl_clk_common *common,
123 const struct owl_pll_hw *pll_hw, bool enable)
124{
125 u32 reg;
126
127 regmap_read(common->regmap, pll_hw->reg, &reg);
128
129 if (enable)
130 reg |= BIT(pll_hw->bit_idx);
131 else
132 reg &= ~BIT(pll_hw->bit_idx);
133
134 regmap_write(common->regmap, pll_hw->reg, reg);
135}
136
137static int owl_pll_enable(struct clk_hw *hw)
138{
139 struct owl_pll *pll = hw_to_owl_pll(hw);
140 const struct owl_clk_common *common = &pll->common;
141
142 owl_pll_set(common, &pll->pll_hw, true);
143
144 return 0;
145}
146
147static void owl_pll_disable(struct clk_hw *hw)
148{
149 struct owl_pll *pll = hw_to_owl_pll(hw);
150 const struct owl_clk_common *common = &pll->common;
151
152 owl_pll_set(common, &pll->pll_hw, false);
153}
154
155static int owl_pll_set_rate(struct clk_hw *hw, unsigned long rate,
156 unsigned long parent_rate)
157{
158 struct owl_pll *pll = hw_to_owl_pll(hw);
159 struct owl_pll_hw *pll_hw = &pll->pll_hw;
160 const struct owl_clk_common *common = &pll->common;
161 const struct clk_pll_table *clkt;
162 u32 val, reg;
163
164 /* fixed frequency */
165 if (pll_hw->width == 0)
166 return 0;
167
168 if (pll_hw->table) {
169 clkt = _get_pll_table(pll_hw->table, rate);
170 val = clkt->val;
171 } else {
172 val = owl_pll_calculate_mul(pll_hw, rate);
173 }
174
175 regmap_read(common->regmap, pll_hw->reg, &reg);
176
177 reg &= ~mul_mask(pll_hw);
178 reg |= val << pll_hw->shift;
179
180 regmap_write(common->regmap, pll_hw->reg, reg);
181
182 udelay(PLL_STABILITY_WAIT_US);
183
184 return 0;
185}
186
187const struct clk_ops owl_pll_ops = {
188 .enable = owl_pll_enable,
189 .disable = owl_pll_disable,
190 .is_enabled = owl_pll_is_enabled,
191 .round_rate = owl_pll_round_rate,
192 .recalc_rate = owl_pll_recalc_rate,
193 .set_rate = owl_pll_set_rate,
194};
diff --git a/drivers/clk/actions/owl-pll.h b/drivers/clk/actions/owl-pll.h
new file mode 100644
index 000000000000..0aae30abd5dc
--- /dev/null
+++ b/drivers/clk/actions/owl-pll.h
@@ -0,0 +1,92 @@
1// SPDX-License-Identifier: GPL-2.0+
2//
3// OWL pll clock driver
4//
5// Copyright (c) 2014 Actions Semi Inc.
6// Author: David Liu <liuwei@actions-semi.com>
7//
8// Copyright (c) 2018 Linaro Ltd.
9// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10
11#ifndef _OWL_PLL_H_
12#define _OWL_PLL_H_
13
14#include "owl-common.h"
15
16/* last entry should have rate = 0 */
17struct clk_pll_table {
18 unsigned int val;
19 unsigned long rate;
20};
21
22struct owl_pll_hw {
23 u32 reg;
24 u32 bfreq;
25 u8 bit_idx;
26 u8 shift;
27 u8 width;
28 u8 min_mul;
29 u8 max_mul;
30 const struct clk_pll_table *table;
31};
32
33struct owl_pll {
34 struct owl_pll_hw pll_hw;
35 struct owl_clk_common common;
36};
37
38#define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
39 _width, _min_mul, _max_mul, _table) \
40 { \
41 .reg = _reg, \
42 .bfreq = _bfreq, \
43 .bit_idx = _bit_idx, \
44 .shift = _shift, \
45 .width = _width, \
46 .min_mul = _min_mul, \
47 .max_mul = _max_mul, \
48 .table = _table, \
49 }
50
51#define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \
52 _shift, _width, _min_mul, _max_mul, _table, _flags) \
53 struct owl_pll _struct = { \
54 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
55 _width, _min_mul, \
56 _max_mul, _table), \
57 .common = { \
58 .regmap = NULL, \
59 .hw.init = CLK_HW_INIT(_name, \
60 _parent, \
61 &owl_pll_ops, \
62 _flags), \
63 }, \
64 }
65
66#define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \
67 _shift, _width, _min_mul, _max_mul, _table, _flags) \
68 struct owl_pll _struct = { \
69 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
70 _width, _min_mul, \
71 _max_mul, _table), \
72 .common = { \
73 .regmap = NULL, \
74 .hw.init = CLK_HW_INIT_NO_PARENT(_name, \
75 &owl_pll_ops, \
76 _flags), \
77 }, \
78 }
79
80#define mul_mask(m) ((1 << ((m)->width)) - 1)
81#define PLL_STABILITY_WAIT_US (50)
82
83static inline struct owl_pll *hw_to_owl_pll(const struct clk_hw *hw)
84{
85 struct owl_clk_common *common = hw_to_owl_clk_common(hw);
86
87 return container_of(common, struct owl_pll, common);
88}
89
90extern const struct clk_ops owl_pll_ops;
91
92#endif /* _OWL_PLL_H_ */
diff --git a/drivers/clk/actions/owl-s900.c b/drivers/clk/actions/owl-s900.c
new file mode 100644
index 000000000000..7f60ed6afe63
--- /dev/null
+++ b/drivers/clk/actions/owl-s900.c
@@ -0,0 +1,721 @@
1// SPDX-License-Identifier: GPL-2.0+
2//
3// OWL S900 SoC clock driver
4//
5// Copyright (c) 2014 Actions Semi Inc.
6// Author: David Liu <liuwei@actions-semi.com>
7//
8// Copyright (c) 2018 Linaro Ltd.
9// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10
11#include <linux/clk-provider.h>
12#include <linux/platform_device.h>
13
14#include "owl-common.h"
15#include "owl-composite.h"
16#include "owl-divider.h"
17#include "owl-factor.h"
18#include "owl-fixed-factor.h"
19#include "owl-gate.h"
20#include "owl-mux.h"
21#include "owl-pll.h"
22
23#include <dt-bindings/clock/actions,s900-cmu.h>
24
25#define CMU_COREPLL (0x0000)
26#define CMU_DEVPLL (0x0004)
27#define CMU_DDRPLL (0x0008)
28#define CMU_NANDPLL (0x000C)
29#define CMU_DISPLAYPLL (0x0010)
30#define CMU_AUDIOPLL (0x0014)
31#define CMU_TVOUTPLL (0x0018)
32#define CMU_BUSCLK (0x001C)
33#define CMU_SENSORCLK (0x0020)
34#define CMU_LCDCLK (0x0024)
35#define CMU_DSICLK (0x0028)
36#define CMU_CSICLK (0x002C)
37#define CMU_DECLK (0x0030)
38#define CMU_BISPCLK (0x0034)
39#define CMU_IMXCLK (0x0038)
40#define CMU_HDECLK (0x003C)
41#define CMU_VDECLK (0x0040)
42#define CMU_VCECLK (0x0044)
43#define CMU_NANDCCLK (0x004C)
44#define CMU_SD0CLK (0x0050)
45#define CMU_SD1CLK (0x0054)
46#define CMU_SD2CLK (0x0058)
47#define CMU_UART0CLK (0x005C)
48#define CMU_UART1CLK (0x0060)
49#define CMU_UART2CLK (0x0064)
50#define CMU_PWM0CLK (0x0070)
51#define CMU_PWM1CLK (0x0074)
52#define CMU_PWM2CLK (0x0078)
53#define CMU_PWM3CLK (0x007C)
54#define CMU_USBPLL (0x0080)
55#define CMU_ASSISTPLL (0x0084)
56#define CMU_EDPCLK (0x0088)
57#define CMU_GPU3DCLK (0x0090)
58#define CMU_CORECTL (0x009C)
59#define CMU_DEVCLKEN0 (0x00A0)
60#define CMU_DEVCLKEN1 (0x00A4)
61#define CMU_DEVRST0 (0x00A8)
62#define CMU_DEVRST1 (0x00AC)
63#define CMU_UART3CLK (0x00B0)
64#define CMU_UART4CLK (0x00B4)
65#define CMU_UART5CLK (0x00B8)
66#define CMU_UART6CLK (0x00BC)
67#define CMU_TLSCLK (0x00C0)
68#define CMU_SD3CLK (0x00C4)
69#define CMU_PWM4CLK (0x00C8)
70#define CMU_PWM5CLK (0x00CC)
71
72static struct clk_pll_table clk_audio_pll_table[] = {
73 { 0, 45158400 }, { 1, 49152000 },
74 { 0, 0 },
75};
76
77static struct clk_pll_table clk_edp_pll_table[] = {
78 { 0, 810000000 }, { 1, 135000000 }, { 2, 270000000 },
79 { 0, 0 },
80};
81
82/* pll clocks */
83static OWL_PLL_NO_PARENT(core_pll_clk, "core_pll_clk", CMU_COREPLL, 24000000, 9, 0, 8, 5, 107, NULL, CLK_IGNORE_UNUSED);
84static OWL_PLL_NO_PARENT(dev_pll_clk, "dev_pll_clk", CMU_DEVPLL, 6000000, 8, 0, 8, 20, 180, NULL, CLK_IGNORE_UNUSED);
85static OWL_PLL_NO_PARENT(ddr_pll_clk, "ddr_pll_clk", CMU_DDRPLL, 24000000, 8, 0, 8, 5, 45, NULL, CLK_IGNORE_UNUSED);
86static OWL_PLL_NO_PARENT(nand_pll_clk, "nand_pll_clk", CMU_NANDPLL, 6000000, 8, 0, 8, 4, 100, NULL, CLK_IGNORE_UNUSED);
87static OWL_PLL_NO_PARENT(display_pll_clk, "display_pll_clk", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 20, 180, NULL, CLK_IGNORE_UNUSED);
88static OWL_PLL_NO_PARENT(assist_pll_clk, "assist_pll_clk", CMU_ASSISTPLL, 500000000, 0, 0, 0, 0, 0, NULL, CLK_IGNORE_UNUSED);
89static OWL_PLL_NO_PARENT(audio_pll_clk, "audio_pll_clk", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, clk_audio_pll_table, CLK_IGNORE_UNUSED);
90static OWL_PLL(edp_pll_clk, "edp_pll_clk", "edp24M_clk", CMU_EDPCLK, 0, 9, 0, 2, 0, 0, clk_edp_pll_table, CLK_IGNORE_UNUSED);
91
92static const char *cpu_clk_mux_p[] = { "losc", "hosc", "core_pll_clk", };
93static const char *dev_clk_p[] = { "hosc", "dev_pll_clk", };
94static const char *noc_clk_mux_p[] = { "dev_clk", "assist_pll_clk", };
95static const char *dmm_clk_mux_p[] = { "dev_clk", "nand_pll_clk", "assist_pll_clk", "ddr_clk_src", };
96static const char *bisp_clk_mux_p[] = { "assist_pll_clk", "dev_clk", };
97static const char *csi_clk_mux_p[] = { "display_pll_clk", "dev_clk", };
98static const char *de_clk_mux_p[] = { "assist_pll_clk", "dev_clk", };
99static const char *gpu_clk_mux_p[] = { "dev_clk", "display_pll_clk", "ddr_clk_src", };
100static const char *hde_clk_mux_p[] = { "dev_clk", "display_pll_clk", "ddr_clk_src", };
101static const char *imx_clk_mux_p[] = { "assist_pll_clk", "dev_clk", };
102static const char *lcd_clk_mux_p[] = { "display_pll_clk", "nand_pll_clk", };
103static const char *nand_clk_mux_p[] = { "dev_clk", "nand_pll_clk", };
104static const char *sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk", };
105static const char *sensor_clk_mux_p[] = { "hosc", "bisp_clk", };
106static const char *uart_clk_mux_p[] = { "hosc", "dev_pll_clk", };
107static const char *vce_clk_mux_p[] = { "dev_clk", "display_pll_clk", "assist_pll_clk", "ddr_clk_src", };
108static const char *i2s_clk_mux_p[] = { "audio_pll_clk", };
109static const char *edp_clk_mux_p[] = { "assist_pll_clk", "display_pll_clk", };
110
111/* mux clocks */
112static OWL_MUX(cpu_clk, "cpu_clk", cpu_clk_mux_p, CMU_BUSCLK, 0, 2, CLK_SET_RATE_PARENT);
113static OWL_MUX(dev_clk, "dev_clk", dev_clk_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
114static OWL_MUX(noc_clk_mux, "noc_clk_mux", noc_clk_mux_p, CMU_BUSCLK, 7, 1, CLK_SET_RATE_PARENT);
115
116static struct clk_div_table nand_div_table[] = {
117 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 6 },
118 { 4, 8 }, { 5, 10 }, { 6, 12 }, { 7, 14 },
119 { 8, 16 }, { 9, 18 }, { 10, 20 }, { 11, 22 },
120 { 12, 24 }, { 13, 26 }, { 14, 28 }, { 15, 30 },
121 { 0, 0 },
122};
123
124static struct clk_div_table apb_div_table[] = {
125 { 1, 2 }, { 2, 3 }, { 3, 4 },
126 { 0, 0 },
127};
128
129static struct clk_div_table eth_mac_div_table[] = {
130 { 0, 2 }, { 1, 4 },
131 { 0, 0 },
132};
133
134static struct clk_div_table rmii_ref_div_table[] = {
135 { 0, 4 }, { 1, 10 },
136 { 0, 0 },
137};
138
139static struct clk_div_table usb3_mac_div_table[] = {
140 { 1, 2 }, { 2, 3 }, { 3, 4 },
141 { 0, 8 },
142};
143
144static struct clk_div_table i2s_div_table[] = {
145 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
146 { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
147 { 8, 24 },
148 { 0, 0 },
149};
150
151static struct clk_div_table hdmia_div_table[] = {
152 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
153 { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
154 { 8, 24 },
155 { 0, 0 },
156};
157
158/* divider clocks */
159static OWL_DIVIDER(noc_clk_div, "noc_clk_div", "noc_clk", CMU_BUSCLK, 19, 1, NULL, 0, 0);
160static OWL_DIVIDER(ahb_clk, "ahb_clk", "noc_clk_div", CMU_BUSCLK, 4, 1, NULL, 0, 0);
161static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK, 8, 2, apb_div_table, 0, 0);
162static OWL_DIVIDER(usb3_mac_clk, "usb3_mac_clk", "assist_pll_clk", CMU_ASSISTPLL, 12, 2, usb3_mac_div_table, 0, 0);
163static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "assist_pll_clk", CMU_ASSISTPLL, 8, 1, rmii_ref_div_table, 0, 0);
164
165static struct clk_factor_table sd_factor_table[] = {
166 /* bit0 ~ 4 */
167 { 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 },
168 { 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 },
169 { 8, 1, 9 }, { 9, 1, 10 }, { 10, 1, 11 }, { 11, 1, 12 },
170 { 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 },
171 { 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 },
172 { 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 },
173 { 24, 1, 25 }, { 25, 1, 26 }, { 26, 1, 27 }, { 27, 1, 28 },
174 { 28, 1, 29 }, { 29, 1, 30 }, { 30, 1, 31 }, { 31, 1, 32 },
175
176 /* bit8: /128 */
177 { 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 },
178 { 260, 1, 5 * 128 }, { 261, 1, 6 * 128 }, { 262, 1, 7 * 128 }, { 263, 1, 8 * 128 },
179 { 264, 1, 9 * 128 }, { 265, 1, 10 * 128 }, { 266, 1, 11 * 128 }, { 267, 1, 12 * 128 },
180 { 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 },
181 { 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 },
182 { 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 },
183 { 280, 1, 25 * 128 }, { 281, 1, 26 * 128 }, { 282, 1, 27 * 128 }, { 283, 1, 28 * 128 },
184 { 284, 1, 29 * 128 }, { 285, 1, 30 * 128 }, { 286, 1, 31 * 128 }, { 287, 1, 32 * 128 },
185
186 { 0, 0 },
187};
188
189static struct clk_factor_table dmm_factor_table[] = {
190 { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 1, 3 },
191 { 4, 1, 4 },
192 { 0, 0, 0 },
193};
194
195static struct clk_factor_table noc_factor_table[] = {
196 { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 1, 3 }, { 4, 1, 4 },
197 { 0, 0, 0 },
198};
199
200static struct clk_factor_table bisp_factor_table[] = {
201 { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
202 { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
203 { 0, 0, 0 },
204};
205
206/* factor clocks */
207static OWL_FACTOR(noc_clk, "noc_clk", "noc_clk_mux", CMU_BUSCLK, 16, 3, noc_factor_table, 0, 0);
208static OWL_FACTOR(de_clk1, "de_clk1", "de_clk", CMU_DECLK, 0, 3, bisp_factor_table, 0, 0);
209static OWL_FACTOR(de_clk2, "de_clk2", "de_clk", CMU_DECLK, 4, 3, bisp_factor_table, 0, 0);
210static OWL_FACTOR(de_clk3, "de_clk3", "de_clk", CMU_DECLK, 8, 3, bisp_factor_table, 0, 0);
211
212/* gate clocks */
213static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
214static OWL_GATE_NO_PARENT(gpu_clk, "gpu_clk", CMU_DEVCLKEN0, 30, 0, 0);
215static OWL_GATE(dmac_clk, "dmac_clk", "noc_clk_div", CMU_DEVCLKEN0, 1, 0, 0);
216static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
217static OWL_GATE_NO_PARENT(dsi_clk, "dsi_clk", CMU_DEVCLKEN0, 12, 0, 0);
218static OWL_GATE(ddr0_clk, "ddr0_clk", "ddr_pll_clk", CMU_DEVCLKEN0, 31, 0, CLK_IGNORE_UNUSED);
219static OWL_GATE(ddr1_clk, "ddr1_clk", "ddr_pll_clk", CMU_DEVCLKEN0, 29, 0, CLK_IGNORE_UNUSED);
220static OWL_GATE_NO_PARENT(usb3_480mpll0_clk, "usb3_480mpll0_clk", CMU_USBPLL, 3, 0, 0);
221static OWL_GATE_NO_PARENT(usb3_480mphy0_clk, "usb3_480mphy0_clk", CMU_USBPLL, 2, 0, 0);
222static OWL_GATE_NO_PARENT(usb3_5gphy_clk, "usb3_5gphy_clk", CMU_USBPLL, 1, 0, 0);
223static OWL_GATE_NO_PARENT(usb3_cce_clk, "usb3_cce_clk", CMU_USBPLL, 0, 0, 0);
224static OWL_GATE(edp24M_clk, "edp24M_clk", "diff24M", CMU_EDPCLK, 8, 0, 0);
225static OWL_GATE(edp_link_clk, "edp_link_clk", "edp_pll_clk", CMU_DEVCLKEN0, 10, 0, 0);
226static OWL_GATE_NO_PARENT(usbh0_pllen_clk, "usbh0_pllen_clk", CMU_USBPLL, 12, 0, 0);
227static OWL_GATE_NO_PARENT(usbh0_phy_clk, "usbh0_phy_clk", CMU_USBPLL, 10, 0, 0);
228static OWL_GATE_NO_PARENT(usbh0_cce_clk, "usbh0_cce_clk", CMU_USBPLL, 8, 0, 0);
229static OWL_GATE_NO_PARENT(usbh1_pllen_clk, "usbh1_pllen_clk", CMU_USBPLL, 13, 0, 0);
230static OWL_GATE_NO_PARENT(usbh1_phy_clk, "usbh1_phy_clk", CMU_USBPLL, 11, 0, 0);
231static OWL_GATE_NO_PARENT(usbh1_cce_clk, "usbh1_cce_clk", CMU_USBPLL, 9, 0, 0);
232static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED);
233static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED);
234static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED);
235static OWL_GATE(spi3_clk, "spi3_clk", "ahb_clk", CMU_DEVCLKEN1, 13, 0, CLK_IGNORE_UNUSED);
236
237/* composite clocks */
238static OWL_COMP_FACTOR(bisp_clk, "bisp_clk", bisp_clk_mux_p,
239 OWL_MUX_HW(CMU_BISPCLK, 4, 1),
240 OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
241 OWL_FACTOR_HW(CMU_BISPCLK, 0, 3, 0, bisp_factor_table),
242 0);
243
244static OWL_COMP_DIV(csi0_clk, "csi0_clk", csi_clk_mux_p,
245 OWL_MUX_HW(CMU_CSICLK, 4, 1),
246 OWL_GATE_HW(CMU_DEVCLKEN0, 13, 0),
247 OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
248 0);
249
250static OWL_COMP_DIV(csi1_clk, "csi1_clk", csi_clk_mux_p,
251 OWL_MUX_HW(CMU_CSICLK, 20, 1),
252 OWL_GATE_HW(CMU_DEVCLKEN0, 15, 0),
253 OWL_DIVIDER_HW(CMU_CSICLK, 16, 4, 0, NULL),
254 0);
255
256static OWL_COMP_PASS(de_clk, "de_clk", de_clk_mux_p,
257 OWL_MUX_HW(CMU_DECLK, 12, 1),
258 OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
259 0);
260
261static OWL_COMP_FACTOR(dmm_clk, "dmm_clk", dmm_clk_mux_p,
262 OWL_MUX_HW(CMU_BUSCLK, 10, 2),
263 OWL_GATE_HW(CMU_DEVCLKEN0, 19, 0),
264 OWL_FACTOR_HW(CMU_BUSCLK, 12, 3, 0, dmm_factor_table),
265 CLK_IGNORE_UNUSED);
266
267static OWL_COMP_FACTOR(edp_clk, "edp_clk", edp_clk_mux_p,
268 OWL_MUX_HW(CMU_EDPCLK, 19, 1),
269 OWL_GATE_HW(CMU_DEVCLKEN0, 10, 0),
270 OWL_FACTOR_HW(CMU_EDPCLK, 16, 3, 0, bisp_factor_table),
271 0);
272
273static OWL_COMP_DIV_FIXED(eth_mac_clk, "eth_mac_clk", "assist_pll_clk",
274 OWL_GATE_HW(CMU_DEVCLKEN1, 22, 0),
275 OWL_DIVIDER_HW(CMU_ASSISTPLL, 10, 1, 0, eth_mac_div_table),
276 0);
277
278static OWL_COMP_FACTOR(gpu_core_clk, "gpu_core_clk", gpu_clk_mux_p,
279 OWL_MUX_HW(CMU_GPU3DCLK, 4, 2),
280 OWL_GATE_HW(CMU_GPU3DCLK, 15, 0),
281 OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, bisp_factor_table),
282 0);
283
284static OWL_COMP_FACTOR(gpu_mem_clk, "gpu_mem_clk", gpu_clk_mux_p,
285 OWL_MUX_HW(CMU_GPU3DCLK, 20, 2),
286 OWL_GATE_HW(CMU_GPU3DCLK, 14, 0),
287 OWL_FACTOR_HW(CMU_GPU3DCLK, 16, 3, 0, bisp_factor_table),
288 0);
289
290static OWL_COMP_FACTOR(gpu_sys_clk, "gpu_sys_clk", gpu_clk_mux_p,
291 OWL_MUX_HW(CMU_GPU3DCLK, 28, 2),
292 OWL_GATE_HW(CMU_GPU3DCLK, 13, 0),
293 OWL_FACTOR_HW(CMU_GPU3DCLK, 24, 3, 0, bisp_factor_table),
294 0);
295
296static OWL_COMP_FACTOR(hde_clk, "hde_clk", hde_clk_mux_p,
297 OWL_MUX_HW(CMU_HDECLK, 4, 2),
298 OWL_GATE_HW(CMU_DEVCLKEN0, 27, 0),
299 OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, bisp_factor_table),
300 0);
301
302static OWL_COMP_DIV(hdmia_clk, "hdmia_clk", i2s_clk_mux_p,
303 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
304 OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
305 OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
306 0);
307
308static OWL_COMP_FIXED_FACTOR(i2c0_clk, "i2c0_clk", "assist_pll_clk",
309 OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
310 1, 5, 0);
311
312static OWL_COMP_FIXED_FACTOR(i2c1_clk, "i2c1_clk", "assist_pll_clk",
313 OWL_GATE_HW(CMU_DEVCLKEN1, 15, 0),
314 1, 5, 0);
315
316static OWL_COMP_FIXED_FACTOR(i2c2_clk, "i2c2_clk", "assist_pll_clk",
317 OWL_GATE_HW(CMU_DEVCLKEN1, 30, 0),
318 1, 5, 0);
319
320static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "assist_pll_clk",
321 OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
322 1, 5, 0);
323
324static OWL_COMP_FIXED_FACTOR(i2c4_clk, "i2c4_clk", "assist_pll_clk",
325 OWL_GATE_HW(CMU_DEVCLKEN0, 17, 0),
326 1, 5, 0);
327
328static OWL_COMP_FIXED_FACTOR(i2c5_clk, "i2c5_clk", "assist_pll_clk",
329 OWL_GATE_HW(CMU_DEVCLKEN1, 1, 0),
330 1, 5, 0);
331
332static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p,
333 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
334 OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
335 OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table),
336 0);
337
338static OWL_COMP_DIV(i2stx_clk, "i2stx_clk", i2s_clk_mux_p,
339 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
340 OWL_GATE_HW(CMU_DEVCLKEN0, 20, 0),
341 OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table),
342 0);
343
344static OWL_COMP_FACTOR(imx_clk, "imx_clk", imx_clk_mux_p,
345 OWL_MUX_HW(CMU_IMXCLK, 4, 1),
346 OWL_GATE_HW(CMU_DEVCLKEN1, 17, 0),
347 OWL_FACTOR_HW(CMU_IMXCLK, 0, 3, 0, bisp_factor_table),
348 0);
349
350static OWL_COMP_DIV(lcd_clk, "lcd_clk", lcd_clk_mux_p,
351 OWL_MUX_HW(CMU_LCDCLK, 12, 2),
352 OWL_GATE_HW(CMU_DEVCLKEN0, 9, 0),
353 OWL_DIVIDER_HW(CMU_LCDCLK, 0, 5, 0, NULL),
354 0);
355
356static OWL_COMP_DIV(nand0_clk, "nand0_clk", nand_clk_mux_p,
357 OWL_MUX_HW(CMU_NANDCCLK, 8, 1),
358 OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0),
359 OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 4, 0, nand_div_table),
360 CLK_SET_RATE_PARENT);
361
362static OWL_COMP_DIV(nand1_clk, "nand1_clk", nand_clk_mux_p,
363 OWL_MUX_HW(CMU_NANDCCLK, 24, 1),
364 OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
365 OWL_DIVIDER_HW(CMU_NANDCCLK, 16, 4, 0, nand_div_table),
366 CLK_SET_RATE_PARENT);
367
368static OWL_COMP_DIV_FIXED(pwm0_clk, "pwm0_clk", "hosc",
369 OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
370 OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 6, 0, NULL),
371 0);
372
373static OWL_COMP_DIV_FIXED(pwm1_clk, "pwm1_clk", "hosc",
374 OWL_GATE_HW(CMU_DEVCLKEN1, 24, 0),
375 OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 6, 0, NULL),
376 0);
377/*
378 * pwm2 may be for backlight, do not gate it
379 * even it is "unused", because it may be
380 * enabled at boot stage, and in kernel, driver
381 * has no effective method to know the real status,
382 * so, the best way is keeping it as what it was.
383 */
384static OWL_COMP_DIV_FIXED(pwm2_clk, "pwm2_clk", "hosc",
385 OWL_GATE_HW(CMU_DEVCLKEN1, 25, 0),
386 OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 6, 0, NULL),
387 CLK_IGNORE_UNUSED);
388
389static OWL_COMP_DIV_FIXED(pwm3_clk, "pwm3_clk", "hosc",
390 OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
391 OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 6, 0, NULL),
392 0);
393
394static OWL_COMP_DIV_FIXED(pwm4_clk, "pwm4_clk", "hosc",
395 OWL_GATE_HW(CMU_DEVCLKEN1, 4, 0),
396 OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 6, 0, NULL),
397 0);
398
399static OWL_COMP_DIV_FIXED(pwm5_clk, "pwm5_clk", "hosc",
400 OWL_GATE_HW(CMU_DEVCLKEN1, 5, 0),
401 OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 6, 0, NULL),
402 0);
403
404static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p,
405 OWL_MUX_HW(CMU_SD0CLK, 9, 1),
406 OWL_GATE_HW(CMU_DEVCLKEN0, 5, 0),
407 OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
408 0);
409
410static OWL_COMP_FACTOR(sd1_clk, "sd1_clk", sd_clk_mux_p,
411 OWL_MUX_HW(CMU_SD1CLK, 9, 1),
412 OWL_GATE_HW(CMU_DEVCLKEN0, 6, 0),
413 OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
414 0);
415
416static OWL_COMP_FACTOR(sd2_clk, "sd2_clk", sd_clk_mux_p,
417 OWL_MUX_HW(CMU_SD2CLK, 9, 1),
418 OWL_GATE_HW(CMU_DEVCLKEN0, 7, 0),
419 OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
420 0);
421
422static OWL_COMP_FACTOR(sd3_clk, "sd3_clk", sd_clk_mux_p,
423 OWL_MUX_HW(CMU_SD3CLK, 9, 1),
424 OWL_GATE_HW(CMU_DEVCLKEN0, 16, 0),
425 OWL_FACTOR_HW(CMU_SD3CLK, 0, 9, 0, sd_factor_table),
426 0);
427
428static OWL_COMP_DIV(sensor_clk, "sensor_clk", sensor_clk_mux_p,
429 OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
430 OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
431 OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, NULL),
432 0);
433
434static OWL_COMP_DIV_FIXED(speed_sensor_clk, "speed_sensor_clk",
435 "hosc",
436 OWL_GATE_HW(CMU_DEVCLKEN1, 0, 0),
437 OWL_DIVIDER_HW(CMU_TLSCLK, 0, 4, CLK_DIVIDER_POWER_OF_TWO, NULL),
438 0);
439
440static OWL_COMP_DIV_FIXED(thermal_sensor_clk, "thermal_sensor_clk",
441 "hosc",
442 OWL_GATE_HW(CMU_DEVCLKEN1, 2, 0),
443 OWL_DIVIDER_HW(CMU_TLSCLK, 8, 4, CLK_DIVIDER_POWER_OF_TWO, NULL),
444 0);
445
446static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p,
447 OWL_MUX_HW(CMU_UART0CLK, 16, 1),
448 OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0),
449 OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
450 CLK_IGNORE_UNUSED);
451
452static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
453 OWL_MUX_HW(CMU_UART1CLK, 16, 1),
454 OWL_GATE_HW(CMU_DEVCLKEN1, 7, 0),
455 OWL_DIVIDER_HW(CMU_UART1CLK, 1, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
456 CLK_IGNORE_UNUSED);
457
458static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p,
459 OWL_MUX_HW(CMU_UART2CLK, 16, 1),
460 OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
461 OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
462 CLK_IGNORE_UNUSED);
463
464static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p,
465 OWL_MUX_HW(CMU_UART3CLK, 16, 1),
466 OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
467 OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
468 CLK_IGNORE_UNUSED);
469
470static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p,
471 OWL_MUX_HW(CMU_UART4CLK, 16, 1),
472 OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
473 OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
474 CLK_IGNORE_UNUSED);
475
476static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p,
477 OWL_MUX_HW(CMU_UART5CLK, 16, 1),
478 OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
479 OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
480 CLK_IGNORE_UNUSED);
481
482static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p,
483 OWL_MUX_HW(CMU_UART6CLK, 16, 1),
484 OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
485 OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
486 CLK_IGNORE_UNUSED);
487
488static OWL_COMP_FACTOR(vce_clk, "vce_clk", vce_clk_mux_p,
489 OWL_MUX_HW(CMU_VCECLK, 4, 2),
490 OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
491 OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, bisp_factor_table),
492 0);
493
494static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p,
495 OWL_MUX_HW(CMU_VDECLK, 4, 2),
496 OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0),
497 OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, bisp_factor_table),
498 0);
499
500static struct owl_clk_common *s900_clks[] = {
501 &core_pll_clk.common,
502 &dev_pll_clk.common,
503 &ddr_pll_clk.common,
504 &nand_pll_clk.common,
505 &display_pll_clk.common,
506 &assist_pll_clk.common,
507 &audio_pll_clk.common,
508 &edp_pll_clk.common,
509 &cpu_clk.common,
510 &dev_clk.common,
511 &noc_clk_mux.common,
512 &noc_clk_div.common,
513 &ahb_clk.common,
514 &apb_clk.common,
515 &usb3_mac_clk.common,
516 &rmii_ref_clk.common,
517 &noc_clk.common,
518 &de_clk1.common,
519 &de_clk2.common,
520 &de_clk3.common,
521 &gpio_clk.common,
522 &gpu_clk.common,
523 &dmac_clk.common,
524 &timer_clk.common,
525 &dsi_clk.common,
526 &ddr0_clk.common,
527 &ddr1_clk.common,
528 &usb3_480mpll0_clk.common,
529 &usb3_480mphy0_clk.common,
530 &usb3_5gphy_clk.common,
531 &usb3_cce_clk.common,
532 &edp24M_clk.common,
533 &edp_link_clk.common,
534 &usbh0_pllen_clk.common,
535 &usbh0_phy_clk.common,
536 &usbh0_cce_clk.common,
537 &usbh1_pllen_clk.common,
538 &usbh1_phy_clk.common,
539 &usbh1_cce_clk.common,
540 &i2c0_clk.common,
541 &i2c1_clk.common,
542 &i2c2_clk.common,
543 &i2c3_clk.common,
544 &i2c4_clk.common,
545 &i2c5_clk.common,
546 &spi0_clk.common,
547 &spi1_clk.common,
548 &spi2_clk.common,
549 &spi3_clk.common,
550 &bisp_clk.common,
551 &csi0_clk.common,
552 &csi1_clk.common,
553 &de_clk.common,
554 &dmm_clk.common,
555 &edp_clk.common,
556 &eth_mac_clk.common,
557 &gpu_core_clk.common,
558 &gpu_mem_clk.common,
559 &gpu_sys_clk.common,
560 &hde_clk.common,
561 &hdmia_clk.common,
562 &i2srx_clk.common,
563 &i2stx_clk.common,
564 &imx_clk.common,
565 &lcd_clk.common,
566 &nand0_clk.common,
567 &nand1_clk.common,
568 &pwm0_clk.common,
569 &pwm1_clk.common,
570 &pwm2_clk.common,
571 &pwm3_clk.common,
572 &pwm4_clk.common,
573 &pwm5_clk.common,
574 &sd0_clk.common,
575 &sd1_clk.common,
576 &sd2_clk.common,
577 &sd3_clk.common,
578 &sensor_clk.common,
579 &speed_sensor_clk.common,
580 &thermal_sensor_clk.common,
581 &uart0_clk.common,
582 &uart1_clk.common,
583 &uart2_clk.common,
584 &uart3_clk.common,
585 &uart4_clk.common,
586 &uart5_clk.common,
587 &uart6_clk.common,
588 &vce_clk.common,
589 &vde_clk.common,
590};
591
592static struct clk_hw_onecell_data s900_hw_clks = {
593 .hws = {
594 [CLK_CORE_PLL] = &core_pll_clk.common.hw,
595 [CLK_DEV_PLL] = &dev_pll_clk.common.hw,
596 [CLK_DDR_PLL] = &ddr_pll_clk.common.hw,
597 [CLK_NAND_PLL] = &nand_pll_clk.common.hw,
598 [CLK_DISPLAY_PLL] = &display_pll_clk.common.hw,
599 [CLK_ASSIST_PLL] = &assist_pll_clk.common.hw,
600 [CLK_AUDIO_PLL] = &audio_pll_clk.common.hw,
601 [CLK_EDP_PLL] = &edp_pll_clk.common.hw,
602 [CLK_CPU] = &cpu_clk.common.hw,
603 [CLK_DEV] = &dev_clk.common.hw,
604 [CLK_NOC_MUX] = &noc_clk_mux.common.hw,
605 [CLK_NOC_DIV] = &noc_clk_div.common.hw,
606 [CLK_AHB] = &ahb_clk.common.hw,
607 [CLK_APB] = &apb_clk.common.hw,
608 [CLK_USB3_MAC] = &usb3_mac_clk.common.hw,
609 [CLK_RMII_REF] = &rmii_ref_clk.common.hw,
610 [CLK_NOC] = &noc_clk.common.hw,
611 [CLK_DE1] = &de_clk1.common.hw,
612 [CLK_DE2] = &de_clk2.common.hw,
613 [CLK_DE3] = &de_clk3.common.hw,
614 [CLK_GPIO] = &gpio_clk.common.hw,
615 [CLK_GPU] = &gpu_clk.common.hw,
616 [CLK_DMAC] = &dmac_clk.common.hw,
617 [CLK_TIMER] = &timer_clk.common.hw,
618 [CLK_DSI] = &dsi_clk.common.hw,
619 [CLK_DDR0] = &ddr0_clk.common.hw,
620 [CLK_DDR1] = &ddr1_clk.common.hw,
621 [CLK_USB3_480MPLL0] = &usb3_480mpll0_clk.common.hw,
622 [CLK_USB3_480MPHY0] = &usb3_480mphy0_clk.common.hw,
623 [CLK_USB3_5GPHY] = &usb3_5gphy_clk.common.hw,
624 [CLK_USB3_CCE] = &usb3_cce_clk.common.hw,
625 [CLK_24M_EDP] = &edp24M_clk.common.hw,
626 [CLK_EDP_LINK] = &edp_link_clk.common.hw,
627 [CLK_USB2H0_PLLEN] = &usbh0_pllen_clk.common.hw,
628 [CLK_USB2H0_PHY] = &usbh0_phy_clk.common.hw,
629 [CLK_USB2H0_CCE] = &usbh0_cce_clk.common.hw,
630 [CLK_USB2H1_PLLEN] = &usbh1_pllen_clk.common.hw,
631 [CLK_USB2H1_PHY] = &usbh1_phy_clk.common.hw,
632 [CLK_USB2H1_CCE] = &usbh1_cce_clk.common.hw,
633 [CLK_I2C0] = &i2c0_clk.common.hw,
634 [CLK_I2C1] = &i2c1_clk.common.hw,
635 [CLK_I2C2] = &i2c2_clk.common.hw,
636 [CLK_I2C3] = &i2c3_clk.common.hw,
637 [CLK_I2C4] = &i2c4_clk.common.hw,
638 [CLK_I2C5] = &i2c5_clk.common.hw,
639 [CLK_SPI0] = &spi0_clk.common.hw,
640 [CLK_SPI1] = &spi1_clk.common.hw,
641 [CLK_SPI2] = &spi2_clk.common.hw,
642 [CLK_SPI3] = &spi3_clk.common.hw,
643 [CLK_BISP] = &bisp_clk.common.hw,
644 [CLK_CSI0] = &csi0_clk.common.hw,
645 [CLK_CSI1] = &csi1_clk.common.hw,
646 [CLK_DE0] = &de_clk.common.hw,
647 [CLK_DMM] = &dmm_clk.common.hw,
648 [CLK_EDP] = &edp_clk.common.hw,
649 [CLK_ETH_MAC] = &eth_mac_clk.common.hw,
650 [CLK_GPU_CORE] = &gpu_core_clk.common.hw,
651 [CLK_GPU_MEM] = &gpu_mem_clk.common.hw,
652 [CLK_GPU_SYS] = &gpu_sys_clk.common.hw,
653 [CLK_HDE] = &hde_clk.common.hw,
654 [CLK_HDMI_AUDIO] = &hdmia_clk.common.hw,
655 [CLK_I2SRX] = &i2srx_clk.common.hw,
656 [CLK_I2STX] = &i2stx_clk.common.hw,
657 [CLK_IMX] = &imx_clk.common.hw,
658 [CLK_LCD] = &lcd_clk.common.hw,
659 [CLK_NAND0] = &nand0_clk.common.hw,
660 [CLK_NAND1] = &nand1_clk.common.hw,
661 [CLK_PWM0] = &pwm0_clk.common.hw,
662 [CLK_PWM1] = &pwm1_clk.common.hw,
663 [CLK_PWM2] = &pwm2_clk.common.hw,
664 [CLK_PWM3] = &pwm3_clk.common.hw,
665 [CLK_PWM4] = &pwm4_clk.common.hw,
666 [CLK_PWM5] = &pwm5_clk.common.hw,
667 [CLK_SD0] = &sd0_clk.common.hw,
668 [CLK_SD1] = &sd1_clk.common.hw,
669 [CLK_SD2] = &sd2_clk.common.hw,
670 [CLK_SD3] = &sd3_clk.common.hw,
671 [CLK_SENSOR] = &sensor_clk.common.hw,
672 [CLK_SPEED_SENSOR] = &speed_sensor_clk.common.hw,
673 [CLK_THERMAL_SENSOR] = &thermal_sensor_clk.common.hw,
674 [CLK_UART0] = &uart0_clk.common.hw,
675 [CLK_UART1] = &uart1_clk.common.hw,
676 [CLK_UART2] = &uart2_clk.common.hw,
677 [CLK_UART3] = &uart3_clk.common.hw,
678 [CLK_UART4] = &uart4_clk.common.hw,
679 [CLK_UART5] = &uart5_clk.common.hw,
680 [CLK_UART6] = &uart6_clk.common.hw,
681 [CLK_VCE] = &vce_clk.common.hw,
682 [CLK_VDE] = &vde_clk.common.hw,
683 },
684 .num = CLK_NR_CLKS,
685};
686
687static const struct owl_clk_desc s900_clk_desc = {
688 .clks = s900_clks,
689 .num_clks = ARRAY_SIZE(s900_clks),
690
691 .hw_clks = &s900_hw_clks,
692};
693
694static int s900_clk_probe(struct platform_device *pdev)
695{
696 const struct owl_clk_desc *desc;
697
698 desc = &s900_clk_desc;
699 owl_clk_regmap_init(pdev, desc);
700
701 return owl_clk_probe(&pdev->dev, desc->hw_clks);
702}
703
704static const struct of_device_id s900_clk_of_match[] = {
705 { .compatible = "actions,s900-cmu", },
706 { /* sentinel */ }
707};
708
709static struct platform_driver s900_clk_driver = {
710 .probe = s900_clk_probe,
711 .driver = {
712 .name = "s900-cmu",
713 .of_match_table = s900_clk_of_match,
714 },
715};
716
717static int __init s900_clk_init(void)
718{
719 return platform_driver_register(&s900_clk_driver);
720}
721core_initcall(s900_clk_init);
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
index 7d3223fc7161..72b6091eb7b9 100644
--- a/drivers/clk/at91/clk-pll.c
+++ b/drivers/clk/at91/clk-pll.c
@@ -132,19 +132,8 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
132 unsigned long parent_rate) 132 unsigned long parent_rate)
133{ 133{
134 struct clk_pll *pll = to_clk_pll(hw); 134 struct clk_pll *pll = to_clk_pll(hw);
135 unsigned int pllr;
136 u16 mul;
137 u8 div;
138
139 regmap_read(pll->regmap, PLL_REG(pll->id), &pllr);
140
141 div = PLL_DIV(pllr);
142 mul = PLL_MUL(pllr, pll->layout);
143
144 if (!div || !mul)
145 return 0;
146 135
147 return (parent_rate / div) * (mul + 1); 136 return (parent_rate / pll->div) * (pll->mul + 1);
148} 137}
149 138
150static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate, 139static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index fa0d5c8611a0..860c08a328b7 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -394,25 +394,21 @@ out:
394 return count * 1000; 394 return count * 1000;
395} 395}
396 396
397static int bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base, 397static void bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
398 struct debugfs_reg32 *regs, size_t nregs, 398 struct debugfs_reg32 *regs, size_t nregs,
399 struct dentry *dentry) 399 struct dentry *dentry)
400{ 400{
401 struct dentry *regdump;
402 struct debugfs_regset32 *regset; 401 struct debugfs_regset32 *regset;
403 402
404 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL); 403 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL);
405 if (!regset) 404 if (!regset)
406 return -ENOMEM; 405 return;
407 406
408 regset->regs = regs; 407 regset->regs = regs;
409 regset->nregs = nregs; 408 regset->nregs = nregs;
410 regset->base = cprman->regs + base; 409 regset->base = cprman->regs + base;
411 410
412 regdump = debugfs_create_regset32("regdump", S_IRUGO, dentry, 411 debugfs_create_regset32("regdump", S_IRUGO, dentry, regset);
413 regset);
414
415 return regdump ? 0 : -ENOMEM;
416} 412}
417 413
418struct bcm2835_pll_data { 414struct bcm2835_pll_data {
@@ -730,7 +726,7 @@ static int bcm2835_pll_set_rate(struct clk_hw *hw,
730 return 0; 726 return 0;
731} 727}
732 728
733static int bcm2835_pll_debug_init(struct clk_hw *hw, 729static void bcm2835_pll_debug_init(struct clk_hw *hw,
734 struct dentry *dentry) 730 struct dentry *dentry)
735{ 731{
736 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 732 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
@@ -740,7 +736,7 @@ static int bcm2835_pll_debug_init(struct clk_hw *hw,
740 736
741 regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL); 737 regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL);
742 if (!regs) 738 if (!regs)
743 return -ENOMEM; 739 return;
744 740
745 regs[0].name = "cm_ctrl"; 741 regs[0].name = "cm_ctrl";
746 regs[0].offset = data->cm_ctrl_reg; 742 regs[0].offset = data->cm_ctrl_reg;
@@ -757,7 +753,7 @@ static int bcm2835_pll_debug_init(struct clk_hw *hw,
757 regs[6].name = "ana3"; 753 regs[6].name = "ana3";
758 regs[6].offset = data->ana_reg_base + 3 * 4; 754 regs[6].offset = data->ana_reg_base + 3 * 4;
759 755
760 return bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry); 756 bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);
761} 757}
762 758
763static const struct clk_ops bcm2835_pll_clk_ops = { 759static const struct clk_ops bcm2835_pll_clk_ops = {
@@ -861,8 +857,8 @@ static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,
861 return 0; 857 return 0;
862} 858}
863 859
864static int bcm2835_pll_divider_debug_init(struct clk_hw *hw, 860static void bcm2835_pll_divider_debug_init(struct clk_hw *hw,
865 struct dentry *dentry) 861 struct dentry *dentry)
866{ 862{
867 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 863 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
868 struct bcm2835_cprman *cprman = divider->cprman; 864 struct bcm2835_cprman *cprman = divider->cprman;
@@ -871,14 +867,14 @@ static int bcm2835_pll_divider_debug_init(struct clk_hw *hw,
871 867
872 regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL); 868 regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL);
873 if (!regs) 869 if (!regs)
874 return -ENOMEM; 870 return;
875 871
876 regs[0].name = "cm"; 872 regs[0].name = "cm";
877 regs[0].offset = data->cm_reg; 873 regs[0].offset = data->cm_reg;
878 regs[1].name = "a2w"; 874 regs[1].name = "a2w";
879 regs[1].offset = data->a2w_reg; 875 regs[1].offset = data->a2w_reg;
880 876
881 return bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry); 877 bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);
882} 878}
883 879
884static const struct clk_ops bcm2835_pll_divider_clk_ops = { 880static const struct clk_ops bcm2835_pll_divider_clk_ops = {
@@ -1254,15 +1250,14 @@ static struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {
1254 }, 1250 },
1255}; 1251};
1256 1252
1257static int bcm2835_clock_debug_init(struct clk_hw *hw, 1253static void bcm2835_clock_debug_init(struct clk_hw *hw,
1258 struct dentry *dentry) 1254 struct dentry *dentry)
1259{ 1255{
1260 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1256 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1261 struct bcm2835_cprman *cprman = clock->cprman; 1257 struct bcm2835_cprman *cprman = clock->cprman;
1262 const struct bcm2835_clock_data *data = clock->data; 1258 const struct bcm2835_clock_data *data = clock->data;
1263 1259
1264 return bcm2835_debugfs_regset( 1260 bcm2835_debugfs_regset(cprman, data->ctl_reg,
1265 cprman, data->ctl_reg,
1266 bcm2835_debugfs_clock_reg32, 1261 bcm2835_debugfs_clock_reg32,
1267 ARRAY_SIZE(bcm2835_debugfs_clock_reg32), 1262 ARRAY_SIZE(bcm2835_debugfs_clock_reg32),
1268 dentry); 1263 dentry);
@@ -1395,7 +1390,7 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
1395 struct bcm2835_clock *clock; 1390 struct bcm2835_clock *clock;
1396 struct clk_init_data init; 1391 struct clk_init_data init;
1397 const char *parents[1 << CM_SRC_BITS]; 1392 const char *parents[1 << CM_SRC_BITS];
1398 size_t i, j; 1393 size_t i;
1399 int ret; 1394 int ret;
1400 1395
1401 /* 1396 /*
@@ -1405,12 +1400,11 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
1405 for (i = 0; i < data->num_mux_parents; i++) { 1400 for (i = 0; i < data->num_mux_parents; i++) {
1406 parents[i] = data->parents[i]; 1401 parents[i] = data->parents[i];
1407 1402
1408 for (j = 0; j < ARRAY_SIZE(cprman_parent_names); j++) { 1403 ret = match_string(cprman_parent_names,
1409 if (strcmp(parents[i], cprman_parent_names[j]) == 0) { 1404 ARRAY_SIZE(cprman_parent_names),
1410 parents[i] = cprman->real_parent_names[j]; 1405 parents[i]);
1411 break; 1406 if (ret >= 0)
1412 } 1407 parents[i] = cprman->real_parent_names[ret];
1413 }
1414 } 1408 }
1415 1409
1416 memset(&init, 0, sizeof(init)); 1410 memset(&init, 0, sizeof(init));
diff --git a/drivers/clk/bcm/clk-sr.c b/drivers/clk/bcm/clk-sr.c
index adc74f4584cf..7b9efc0212a8 100644
--- a/drivers/clk/bcm/clk-sr.c
+++ b/drivers/clk/bcm/clk-sr.c
@@ -56,8 +56,8 @@ static const struct iproc_pll_ctrl sr_genpll0 = {
56}; 56};
57 57
58static const struct iproc_clk_ctrl sr_genpll0_clk[] = { 58static const struct iproc_clk_ctrl sr_genpll0_clk[] = {
59 [BCM_SR_GENPLL0_SATA_CLK] = { 59 [BCM_SR_GENPLL0_125M_CLK] = {
60 .channel = BCM_SR_GENPLL0_SATA_CLK, 60 .channel = BCM_SR_GENPLL0_125M_CLK,
61 .flags = IPROC_CLK_AON, 61 .flags = IPROC_CLK_AON,
62 .enable = ENABLE_VAL(0x4, 6, 0, 12), 62 .enable = ENABLE_VAL(0x4, 6, 0, 12),
63 .mdiv = REG_VAL(0x18, 0, 9), 63 .mdiv = REG_VAL(0x18, 0, 9),
@@ -102,6 +102,65 @@ static int sr_genpll0_clk_init(struct platform_device *pdev)
102 return 0; 102 return 0;
103} 103}
104 104
105static const struct iproc_pll_ctrl sr_genpll2 = {
106 .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
107 IPROC_CLK_PLL_NEEDS_SW_CFG,
108 .aon = AON_VAL(0x0, 1, 13, 12),
109 .reset = RESET_VAL(0x0, 12, 11),
110 .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
111 .sw_ctrl = SW_CTRL_VAL(0x10, 31),
112 .ndiv_int = REG_VAL(0x10, 20, 10),
113 .ndiv_frac = REG_VAL(0x10, 0, 20),
114 .pdiv = REG_VAL(0x14, 0, 4),
115 .status = REG_VAL(0x30, 12, 1),
116};
117
118static const struct iproc_clk_ctrl sr_genpll2_clk[] = {
119 [BCM_SR_GENPLL2_NIC_CLK] = {
120 .channel = BCM_SR_GENPLL2_NIC_CLK,
121 .flags = IPROC_CLK_AON,
122 .enable = ENABLE_VAL(0x4, 6, 0, 12),
123 .mdiv = REG_VAL(0x18, 0, 9),
124 },
125 [BCM_SR_GENPLL2_TS_500_CLK] = {
126 .channel = BCM_SR_GENPLL2_TS_500_CLK,
127 .flags = IPROC_CLK_AON,
128 .enable = ENABLE_VAL(0x4, 7, 1, 13),
129 .mdiv = REG_VAL(0x18, 10, 9),
130 },
131 [BCM_SR_GENPLL2_125_NITRO_CLK] = {
132 .channel = BCM_SR_GENPLL2_125_NITRO_CLK,
133 .flags = IPROC_CLK_AON,
134 .enable = ENABLE_VAL(0x4, 8, 2, 14),
135 .mdiv = REG_VAL(0x18, 20, 9),
136 },
137 [BCM_SR_GENPLL2_CHIMP_CLK] = {
138 .channel = BCM_SR_GENPLL2_CHIMP_CLK,
139 .flags = IPROC_CLK_AON,
140 .enable = ENABLE_VAL(0x4, 9, 3, 15),
141 .mdiv = REG_VAL(0x1c, 0, 9),
142 },
143 [BCM_SR_GENPLL2_NIC_FLASH_CLK] = {
144 .channel = BCM_SR_GENPLL2_NIC_FLASH_CLK,
145 .flags = IPROC_CLK_AON,
146 .enable = ENABLE_VAL(0x4, 10, 4, 16),
147 .mdiv = REG_VAL(0x1c, 10, 9),
148 },
149 [BCM_SR_GENPLL2_FS4_CLK] = {
150 .channel = BCM_SR_GENPLL2_FS4_CLK,
151 .enable = ENABLE_VAL(0x4, 11, 5, 17),
152 .mdiv = REG_VAL(0x1c, 20, 9),
153 },
154};
155
156static int sr_genpll2_clk_init(struct platform_device *pdev)
157{
158 iproc_pll_clk_setup(pdev->dev.of_node,
159 &sr_genpll2, NULL, 0, sr_genpll2_clk,
160 ARRAY_SIZE(sr_genpll2_clk));
161 return 0;
162}
163
105static const struct iproc_pll_ctrl sr_genpll3 = { 164static const struct iproc_pll_ctrl sr_genpll3 = {
106 .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC | 165 .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
107 IPROC_CLK_PLL_NEEDS_SW_CFG, 166 IPROC_CLK_PLL_NEEDS_SW_CFG,
@@ -157,6 +216,30 @@ static const struct iproc_clk_ctrl sr_genpll4_clk[] = {
157 .enable = ENABLE_VAL(0x4, 6, 0, 12), 216 .enable = ENABLE_VAL(0x4, 6, 0, 12),
158 .mdiv = REG_VAL(0x18, 0, 9), 217 .mdiv = REG_VAL(0x18, 0, 9),
159 }, 218 },
219 [BCM_SR_GENPLL4_TPIU_PLL_CLK] = {
220 .channel = BCM_SR_GENPLL4_TPIU_PLL_CLK,
221 .flags = IPROC_CLK_AON,
222 .enable = ENABLE_VAL(0x4, 7, 1, 13),
223 .mdiv = REG_VAL(0x18, 10, 9),
224 },
225 [BCM_SR_GENPLL4_NOC_CLK] = {
226 .channel = BCM_SR_GENPLL4_NOC_CLK,
227 .flags = IPROC_CLK_AON,
228 .enable = ENABLE_VAL(0x4, 8, 2, 14),
229 .mdiv = REG_VAL(0x18, 20, 9),
230 },
231 [BCM_SR_GENPLL4_CHCLK_FS4_CLK] = {
232 .channel = BCM_SR_GENPLL4_CHCLK_FS4_CLK,
233 .flags = IPROC_CLK_AON,
234 .enable = ENABLE_VAL(0x4, 9, 3, 15),
235 .mdiv = REG_VAL(0x1c, 0, 9),
236 },
237 [BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK] = {
238 .channel = BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK,
239 .flags = IPROC_CLK_AON,
240 .enable = ENABLE_VAL(0x4, 10, 4, 16),
241 .mdiv = REG_VAL(0x1c, 10, 9),
242 },
160}; 243};
161 244
162static int sr_genpll4_clk_init(struct platform_device *pdev) 245static int sr_genpll4_clk_init(struct platform_device *pdev)
@@ -181,18 +264,21 @@ static const struct iproc_pll_ctrl sr_genpll5 = {
181}; 264};
182 265
183static const struct iproc_clk_ctrl sr_genpll5_clk[] = { 266static const struct iproc_clk_ctrl sr_genpll5_clk[] = {
184 [BCM_SR_GENPLL5_FS_CLK] = { 267 [BCM_SR_GENPLL5_FS4_HF_CLK] = {
185 .channel = BCM_SR_GENPLL5_FS_CLK, 268 .channel = BCM_SR_GENPLL5_FS4_HF_CLK,
186 .flags = IPROC_CLK_AON,
187 .enable = ENABLE_VAL(0x4, 6, 0, 12), 269 .enable = ENABLE_VAL(0x4, 6, 0, 12),
188 .mdiv = REG_VAL(0x18, 0, 9), 270 .mdiv = REG_VAL(0x18, 0, 9),
189 }, 271 },
190 [BCM_SR_GENPLL5_SPU_CLK] = { 272 [BCM_SR_GENPLL5_CRYPTO_AE_CLK] = {
191 .channel = BCM_SR_GENPLL5_SPU_CLK, 273 .channel = BCM_SR_GENPLL5_CRYPTO_AE_CLK,
192 .flags = IPROC_CLK_AON, 274 .enable = ENABLE_VAL(0x4, 7, 1, 12),
193 .enable = ENABLE_VAL(0x4, 6, 0, 12),
194 .mdiv = REG_VAL(0x18, 10, 9), 275 .mdiv = REG_VAL(0x18, 10, 9),
195 }, 276 },
277 [BCM_SR_GENPLL5_RAID_AE_CLK] = {
278 .channel = BCM_SR_GENPLL5_RAID_AE_CLK,
279 .enable = ENABLE_VAL(0x4, 8, 2, 14),
280 .mdiv = REG_VAL(0x18, 20, 9),
281 },
196}; 282};
197 283
198static int sr_genpll5_clk_init(struct platform_device *pdev) 284static int sr_genpll5_clk_init(struct platform_device *pdev)
@@ -214,24 +300,30 @@ static const struct iproc_pll_ctrl sr_lcpll0 = {
214}; 300};
215 301
216static const struct iproc_clk_ctrl sr_lcpll0_clk[] = { 302static const struct iproc_clk_ctrl sr_lcpll0_clk[] = {
217 [BCM_SR_LCPLL0_SATA_REF_CLK] = { 303 [BCM_SR_LCPLL0_SATA_REFP_CLK] = {
218 .channel = BCM_SR_LCPLL0_SATA_REF_CLK, 304 .channel = BCM_SR_LCPLL0_SATA_REFP_CLK,
219 .flags = IPROC_CLK_AON, 305 .flags = IPROC_CLK_AON,
220 .enable = ENABLE_VAL(0x0, 7, 1, 13), 306 .enable = ENABLE_VAL(0x0, 7, 1, 13),
221 .mdiv = REG_VAL(0x14, 0, 9), 307 .mdiv = REG_VAL(0x14, 0, 9),
222 }, 308 },
223 [BCM_SR_LCPLL0_USB_REF_CLK] = { 309 [BCM_SR_LCPLL0_SATA_REFN_CLK] = {
224 .channel = BCM_SR_LCPLL0_USB_REF_CLK, 310 .channel = BCM_SR_LCPLL0_SATA_REFN_CLK,
225 .flags = IPROC_CLK_AON, 311 .flags = IPROC_CLK_AON,
226 .enable = ENABLE_VAL(0x0, 8, 2, 14), 312 .enable = ENABLE_VAL(0x0, 8, 2, 14),
227 .mdiv = REG_VAL(0x14, 10, 9), 313 .mdiv = REG_VAL(0x14, 10, 9),
228 }, 314 },
229 [BCM_SR_LCPLL0_SATA_REFPN_CLK] = { 315 [BCM_SR_LCPLL0_SATA_350_CLK] = {
230 .channel = BCM_SR_LCPLL0_SATA_REFPN_CLK, 316 .channel = BCM_SR_LCPLL0_SATA_350_CLK,
231 .flags = IPROC_CLK_AON, 317 .flags = IPROC_CLK_AON,
232 .enable = ENABLE_VAL(0x0, 9, 3, 15), 318 .enable = ENABLE_VAL(0x0, 9, 3, 15),
233 .mdiv = REG_VAL(0x14, 20, 9), 319 .mdiv = REG_VAL(0x14, 20, 9),
234 }, 320 },
321 [BCM_SR_LCPLL0_SATA_500_CLK] = {
322 .channel = BCM_SR_LCPLL0_SATA_500_CLK,
323 .flags = IPROC_CLK_AON,
324 .enable = ENABLE_VAL(0x0, 10, 4, 16),
325 .mdiv = REG_VAL(0x18, 0, 9),
326 },
235}; 327};
236 328
237static int sr_lcpll0_clk_init(struct platform_device *pdev) 329static int sr_lcpll0_clk_init(struct platform_device *pdev)
@@ -259,6 +351,18 @@ static const struct iproc_clk_ctrl sr_lcpll1_clk[] = {
259 .enable = ENABLE_VAL(0x0, 7, 1, 13), 351 .enable = ENABLE_VAL(0x0, 7, 1, 13),
260 .mdiv = REG_VAL(0x14, 0, 9), 352 .mdiv = REG_VAL(0x14, 0, 9),
261 }, 353 },
354 [BCM_SR_LCPLL1_USB_REF_CLK] = {
355 .channel = BCM_SR_LCPLL1_USB_REF_CLK,
356 .flags = IPROC_CLK_AON,
357 .enable = ENABLE_VAL(0x0, 8, 2, 14),
358 .mdiv = REG_VAL(0x14, 10, 9),
359 },
360 [BCM_SR_LCPLL1_CRMU_TS_CLK] = {
361 .channel = BCM_SR_LCPLL1_CRMU_TS_CLK,
362 .flags = IPROC_CLK_AON,
363 .enable = ENABLE_VAL(0x0, 9, 3, 15),
364 .mdiv = REG_VAL(0x14, 20, 9),
365 },
262}; 366};
263 367
264static int sr_lcpll1_clk_init(struct platform_device *pdev) 368static int sr_lcpll1_clk_init(struct platform_device *pdev)
@@ -298,6 +402,7 @@ static int sr_lcpll_pcie_clk_init(struct platform_device *pdev)
298 402
299static const struct of_device_id sr_clk_dt_ids[] = { 403static const struct of_device_id sr_clk_dt_ids[] = {
300 { .compatible = "brcm,sr-genpll0", .data = sr_genpll0_clk_init }, 404 { .compatible = "brcm,sr-genpll0", .data = sr_genpll0_clk_init },
405 { .compatible = "brcm,sr-genpll2", .data = sr_genpll2_clk_init },
301 { .compatible = "brcm,sr-genpll4", .data = sr_genpll4_clk_init }, 406 { .compatible = "brcm,sr-genpll4", .data = sr_genpll4_clk_init },
302 { .compatible = "brcm,sr-genpll5", .data = sr_genpll5_clk_init }, 407 { .compatible = "brcm,sr-genpll5", .data = sr_genpll5_clk_init },
303 { .compatible = "brcm,sr-lcpll0", .data = sr_lcpll0_clk_init }, 408 { .compatible = "brcm,sr-lcpll0", .data = sr_lcpll0_clk_init },
diff --git a/drivers/clk/berlin/berlin2-avpll.c b/drivers/clk/berlin/berlin2-avpll.c
index cfcae468e989..aa89b4c9464e 100644
--- a/drivers/clk/berlin/berlin2-avpll.c
+++ b/drivers/clk/berlin/berlin2-avpll.c
@@ -1,20 +1,9 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Copyright (c) 2014 Marvell Technology Group Ltd. 3 * Copyright (c) 2014 Marvell Technology Group Ltd.
3 * 4 *
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 * Alexandre Belloni <alexandre.belloni@free-electrons.com> 6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */ 7 */
19#include <linux/clk-provider.h> 8#include <linux/clk-provider.h>
20#include <linux/io.h> 9#include <linux/io.h>
diff --git a/drivers/clk/berlin/berlin2-avpll.h b/drivers/clk/berlin/berlin2-avpll.h
index 17e311153b42..f3af34dc2bee 100644
--- a/drivers/clk/berlin/berlin2-avpll.h
+++ b/drivers/clk/berlin/berlin2-avpll.h
@@ -1,20 +1,9 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (c) 2014 Marvell Technology Group Ltd. 3 * Copyright (c) 2014 Marvell Technology Group Ltd.
3 * 4 *
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 * Alexandre Belloni <alexandre.belloni@free-electrons.com> 6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */ 7 */
19#ifndef __BERLIN2_AVPLL_H 8#ifndef __BERLIN2_AVPLL_H
20#define __BERLIN2_AVPLL_H 9#define __BERLIN2_AVPLL_H
diff --git a/drivers/clk/berlin/berlin2-div.c b/drivers/clk/berlin/berlin2-div.c
index 41ab2d392c57..4d0be66aa6a8 100644
--- a/drivers/clk/berlin/berlin2-div.c
+++ b/drivers/clk/berlin/berlin2-div.c
@@ -1,20 +1,9 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Copyright (c) 2014 Marvell Technology Group Ltd. 3 * Copyright (c) 2014 Marvell Technology Group Ltd.
3 * 4 *
4 * Alexandre Belloni <alexandre.belloni@free-electrons.com> 5 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 6 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */ 7 */
19#include <linux/bitops.h> 8#include <linux/bitops.h>
20#include <linux/clk-provider.h> 9#include <linux/clk-provider.h>
diff --git a/drivers/clk/berlin/berlin2-div.h b/drivers/clk/berlin/berlin2-div.h
index e835ddf8374a..d4da64325190 100644
--- a/drivers/clk/berlin/berlin2-div.h
+++ b/drivers/clk/berlin/berlin2-div.h
@@ -1,20 +1,9 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (c) 2014 Marvell Technology Group Ltd. 3 * Copyright (c) 2014 Marvell Technology Group Ltd.
3 * 4 *
4 * Alexandre Belloni <alexandre.belloni@free-electrons.com> 5 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 6 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */ 7 */
19#ifndef __BERLIN2_DIV_H 8#ifndef __BERLIN2_DIV_H
20#define __BERLIN2_DIV_H 9#define __BERLIN2_DIV_H
diff --git a/drivers/clk/berlin/berlin2-pll.c b/drivers/clk/berlin/berlin2-pll.c
index 4ffbe80f6323..9661820717a5 100644
--- a/drivers/clk/berlin/berlin2-pll.c
+++ b/drivers/clk/berlin/berlin2-pll.c
@@ -1,20 +1,9 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Copyright (c) 2014 Marvell Technology Group Ltd. 3 * Copyright (c) 2014 Marvell Technology Group Ltd.
3 * 4 *
4 * Alexandre Belloni <alexandre.belloni@free-electrons.com> 5 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 6 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */ 7 */
19#include <linux/clk-provider.h> 8#include <linux/clk-provider.h>
20#include <linux/io.h> 9#include <linux/io.h>
diff --git a/drivers/clk/berlin/berlin2-pll.h b/drivers/clk/berlin/berlin2-pll.h
index 583e024b9bed..3757fb25c4e8 100644
--- a/drivers/clk/berlin/berlin2-pll.h
+++ b/drivers/clk/berlin/berlin2-pll.h
@@ -1,20 +1,9 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (c) 2014 Marvell Technology Group Ltd. 3 * Copyright (c) 2014 Marvell Technology Group Ltd.
3 * 4 *
4 * Alexandre Belloni <alexandre.belloni@free-electrons.com> 5 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 6 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */ 7 */
19#ifndef __BERLIN2_PLL_H 8#ifndef __BERLIN2_PLL_H
20#define __BERLIN2_PLL_H 9#define __BERLIN2_PLL_H
diff --git a/drivers/clk/berlin/bg2.c b/drivers/clk/berlin/bg2.c
index e7331ace0337..cd2905364261 100644
--- a/drivers/clk/berlin/bg2.c
+++ b/drivers/clk/berlin/bg2.c
@@ -1,20 +1,9 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Copyright (c) 2014 Marvell Technology Group Ltd. 3 * Copyright (c) 2014 Marvell Technology Group Ltd.
3 * 4 *
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 * Alexandre Belloni <alexandre.belloni@free-electrons.com> 6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */ 7 */
19 8
20#include <linux/clk.h> 9#include <linux/clk.h>
diff --git a/drivers/clk/berlin/bg2q.c b/drivers/clk/berlin/bg2q.c
index 67c270b143f7..9ca26f3bc6e6 100644
--- a/drivers/clk/berlin/bg2q.c
+++ b/drivers/clk/berlin/bg2q.c
@@ -1,20 +1,9 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Copyright (c) 2014 Marvell Technology Group Ltd. 3 * Copyright (c) 2014 Marvell Technology Group Ltd.
3 * 4 *
4 * Alexandre Belloni <alexandre.belloni@free-electrons.com> 5 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 6 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */ 7 */
19 8
20#include <linux/clk.h> 9#include <linux/clk.h>
diff --git a/drivers/clk/berlin/common.h b/drivers/clk/berlin/common.h
index bc68a14c4550..1afb3c29b796 100644
--- a/drivers/clk/berlin/common.h
+++ b/drivers/clk/berlin/common.h
@@ -1,20 +1,9 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (c) 2014 Marvell Technology Group Ltd. 3 * Copyright (c) 2014 Marvell Technology Group Ltd.
3 * 4 *
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 * Alexandre Belloni <alexandre.belloni@free-electrons.com> 6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */ 7 */
19#ifndef __BERLIN2_COMMON_H 8#ifndef __BERLIN2_COMMON_H
20#define __BERLIN2_COMMON_H 9#define __BERLIN2_COMMON_H
diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
index 5eb50c31e455..4d425594999d 100644
--- a/drivers/clk/clk-aspeed.c
+++ b/drivers/clk/clk-aspeed.c
@@ -14,7 +14,9 @@
14 14
15#include <dt-bindings/clock/aspeed-clock.h> 15#include <dt-bindings/clock/aspeed-clock.h>
16 16
17#define ASPEED_NUM_CLKS 35 17#define ASPEED_NUM_CLKS 36
18
19#define ASPEED_RESET2_OFFSET 32
18 20
19#define ASPEED_RESET_CTRL 0x04 21#define ASPEED_RESET_CTRL 0x04
20#define ASPEED_CLK_SELECTION 0x08 22#define ASPEED_CLK_SELECTION 0x08
@@ -30,6 +32,7 @@
30#define CLKIN_25MHZ_EN BIT(23) 32#define CLKIN_25MHZ_EN BIT(23)
31#define AST2400_CLK_SOURCE_SEL BIT(18) 33#define AST2400_CLK_SOURCE_SEL BIT(18)
32#define ASPEED_CLK_SELECTION_2 0xd8 34#define ASPEED_CLK_SELECTION_2 0xd8
35#define ASPEED_RESET_CTRL2 0xd4
33 36
34/* Globally visible clocks */ 37/* Globally visible clocks */
35static DEFINE_SPINLOCK(aspeed_clk_lock); 38static DEFINE_SPINLOCK(aspeed_clk_lock);
@@ -88,7 +91,7 @@ static const struct aspeed_gate_data aspeed_gates[] = {
88 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */ 91 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
89 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */ 92 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
90 [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */ 93 [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
91 [ASPEED_CLK_GATE_BCLK] = { 4, 10, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */ 94 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
92 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, 0 }, /* DAC */ 95 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, 0 }, /* DAC */
93 [ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL }, 96 [ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL },
94 [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */ 97 [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
@@ -291,47 +294,72 @@ struct aspeed_reset {
291#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev) 294#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
292 295
293static const u8 aspeed_resets[] = { 296static const u8 aspeed_resets[] = {
297 /* SCU04 resets */
294 [ASPEED_RESET_XDMA] = 25, 298 [ASPEED_RESET_XDMA] = 25,
295 [ASPEED_RESET_MCTP] = 24, 299 [ASPEED_RESET_MCTP] = 24,
296 [ASPEED_RESET_ADC] = 23, 300 [ASPEED_RESET_ADC] = 23,
297 [ASPEED_RESET_JTAG_MASTER] = 22, 301 [ASPEED_RESET_JTAG_MASTER] = 22,
298 [ASPEED_RESET_MIC] = 18, 302 [ASPEED_RESET_MIC] = 18,
299 [ASPEED_RESET_PWM] = 9, 303 [ASPEED_RESET_PWM] = 9,
300 [ASPEED_RESET_PCIVGA] = 8, 304 [ASPEED_RESET_PECI] = 10,
301 [ASPEED_RESET_I2C] = 2, 305 [ASPEED_RESET_I2C] = 2,
302 [ASPEED_RESET_AHB] = 1, 306 [ASPEED_RESET_AHB] = 1,
307
308 /*
309 * SCUD4 resets start at an offset to separate them from
310 * the SCU04 resets.
311 */
312 [ASPEED_RESET_CRT1] = ASPEED_RESET2_OFFSET + 5,
303}; 313};
304 314
305static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, 315static int aspeed_reset_deassert(struct reset_controller_dev *rcdev,
306 unsigned long id) 316 unsigned long id)
307{ 317{
308 struct aspeed_reset *ar = to_aspeed_reset(rcdev); 318 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
309 u32 rst = BIT(aspeed_resets[id]); 319 u32 reg = ASPEED_RESET_CTRL;
320 u32 bit = aspeed_resets[id];
310 321
311 return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0); 322 if (bit >= ASPEED_RESET2_OFFSET) {
323 bit -= ASPEED_RESET2_OFFSET;
324 reg = ASPEED_RESET_CTRL2;
325 }
326
327 return regmap_update_bits(ar->map, reg, BIT(bit), 0);
312} 328}
313 329
314static int aspeed_reset_assert(struct reset_controller_dev *rcdev, 330static int aspeed_reset_assert(struct reset_controller_dev *rcdev,
315 unsigned long id) 331 unsigned long id)
316{ 332{
317 struct aspeed_reset *ar = to_aspeed_reset(rcdev); 333 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
318 u32 rst = BIT(aspeed_resets[id]); 334 u32 reg = ASPEED_RESET_CTRL;
335 u32 bit = aspeed_resets[id];
336
337 if (bit >= ASPEED_RESET2_OFFSET) {
338 bit -= ASPEED_RESET2_OFFSET;
339 reg = ASPEED_RESET_CTRL2;
340 }
319 341
320 return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst); 342 return regmap_update_bits(ar->map, reg, BIT(bit), BIT(bit));
321} 343}
322 344
323static int aspeed_reset_status(struct reset_controller_dev *rcdev, 345static int aspeed_reset_status(struct reset_controller_dev *rcdev,
324 unsigned long id) 346 unsigned long id)
325{ 347{
326 struct aspeed_reset *ar = to_aspeed_reset(rcdev); 348 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
327 u32 val, rst = BIT(aspeed_resets[id]); 349 u32 reg = ASPEED_RESET_CTRL;
328 int ret; 350 u32 bit = aspeed_resets[id];
351 int ret, val;
352
353 if (bit >= ASPEED_RESET2_OFFSET) {
354 bit -= ASPEED_RESET2_OFFSET;
355 reg = ASPEED_RESET_CTRL2;
356 }
329 357
330 ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val); 358 ret = regmap_read(ar->map, reg, &val);
331 if (ret) 359 if (ret)
332 return ret; 360 return ret;
333 361
334 return !!(val & rst); 362 return !!(val & BIT(bit));
335} 363}
336 364
337static const struct reset_control_ops aspeed_reset_ops = { 365static const struct reset_control_ops aspeed_reset_ops = {
@@ -474,6 +502,13 @@ static int aspeed_clk_probe(struct platform_device *pdev)
474 return PTR_ERR(hw); 502 return PTR_ERR(hw);
475 aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; 503 aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw;
476 504
505 /* Fixed 24MHz clock */
506 hw = clk_hw_register_fixed_rate(NULL, "fixed-24m", "clkin",
507 0, 24000000);
508 if (IS_ERR(hw))
509 return PTR_ERR(hw);
510 aspeed_clk_data->hws[ASPEED_CLK_24M] = hw;
511
477 /* 512 /*
478 * TODO: There are a number of clocks that not included in this driver 513 * TODO: There are a number of clocks that not included in this driver
479 * as more information is required: 514 * as more information is required:
diff --git a/drivers/clk/clk-bulk.c b/drivers/clk/clk-bulk.c
index 4c10456f8a32..6904ed6da504 100644
--- a/drivers/clk/clk-bulk.c
+++ b/drivers/clk/clk-bulk.c
@@ -42,8 +42,9 @@ int __must_check clk_bulk_get(struct device *dev, int num_clks,
42 clks[i].clk = clk_get(dev, clks[i].id); 42 clks[i].clk = clk_get(dev, clks[i].id);
43 if (IS_ERR(clks[i].clk)) { 43 if (IS_ERR(clks[i].clk)) {
44 ret = PTR_ERR(clks[i].clk); 44 ret = PTR_ERR(clks[i].clk);
45 dev_err(dev, "Failed to get clk '%s': %d\n", 45 if (ret != -EPROBE_DEFER)
46 clks[i].id, ret); 46 dev_err(dev, "Failed to get clk '%s': %d\n",
47 clks[i].id, ret);
47 clks[i].clk = NULL; 48 clks[i].clk = NULL;
48 goto err; 49 goto err;
49 } 50 }
diff --git a/drivers/clk/clk-npcm7xx.c b/drivers/clk/clk-npcm7xx.c
new file mode 100644
index 000000000000..740af90a9508
--- /dev/null
+++ b/drivers/clk/clk-npcm7xx.c
@@ -0,0 +1,656 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Nuvoton NPCM7xx Clock Generator
4 * All the clocks are initialized by the bootloader, so this driver allow only
5 * reading of current settings directly from the hardware.
6 *
7 * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com
8 */
9
10#include <linux/module.h>
11#include <linux/clk-provider.h>
12#include <linux/io.h>
13#include <linux/kernel.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/slab.h>
17#include <linux/err.h>
18#include <linux/bitfield.h>
19
20#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
21
22struct npcm7xx_clk_pll {
23 struct clk_hw hw;
24 void __iomem *pllcon;
25 u8 flags;
26};
27
28#define to_npcm7xx_clk_pll(_hw) container_of(_hw, struct npcm7xx_clk_pll, hw)
29
30#define PLLCON_LOKI BIT(31)
31#define PLLCON_LOKS BIT(30)
32#define PLLCON_FBDV GENMASK(27, 16)
33#define PLLCON_OTDV2 GENMASK(15, 13)
34#define PLLCON_PWDEN BIT(12)
35#define PLLCON_OTDV1 GENMASK(10, 8)
36#define PLLCON_INDV GENMASK(5, 0)
37
38static unsigned long npcm7xx_clk_pll_recalc_rate(struct clk_hw *hw,
39 unsigned long parent_rate)
40{
41 struct npcm7xx_clk_pll *pll = to_npcm7xx_clk_pll(hw);
42 unsigned long fbdv, indv, otdv1, otdv2;
43 unsigned int val;
44 u64 ret;
45
46 if (parent_rate == 0) {
47 pr_err("%s: parent rate is zero", __func__);
48 return 0;
49 }
50
51 val = readl_relaxed(pll->pllcon);
52
53 indv = FIELD_GET(PLLCON_INDV, val);
54 fbdv = FIELD_GET(PLLCON_FBDV, val);
55 otdv1 = FIELD_GET(PLLCON_OTDV1, val);
56 otdv2 = FIELD_GET(PLLCON_OTDV2, val);
57
58 ret = (u64)parent_rate * fbdv;
59 do_div(ret, indv * otdv1 * otdv2);
60
61 return ret;
62}
63
64static const struct clk_ops npcm7xx_clk_pll_ops = {
65 .recalc_rate = npcm7xx_clk_pll_recalc_rate,
66};
67
68static struct clk_hw *
69npcm7xx_clk_register_pll(void __iomem *pllcon, const char *name,
70 const char *parent_name, unsigned long flags)
71{
72 struct npcm7xx_clk_pll *pll;
73 struct clk_init_data init;
74 struct clk_hw *hw;
75 int ret;
76
77 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
78 if (!pll)
79 return ERR_PTR(-ENOMEM);
80
81 pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name);
82
83 init.name = name;
84 init.ops = &npcm7xx_clk_pll_ops;
85 init.parent_names = &parent_name;
86 init.num_parents = 1;
87 init.flags = flags;
88
89 pll->pllcon = pllcon;
90 pll->hw.init = &init;
91
92 hw = &pll->hw;
93
94 ret = clk_hw_register(NULL, hw);
95 if (ret) {
96 kfree(pll);
97 hw = ERR_PTR(ret);
98 }
99
100 return hw;
101}
102
103#define NPCM7XX_CLKEN1 (0x00)
104#define NPCM7XX_CLKEN2 (0x28)
105#define NPCM7XX_CLKEN3 (0x30)
106#define NPCM7XX_CLKSEL (0x04)
107#define NPCM7XX_CLKDIV1 (0x08)
108#define NPCM7XX_CLKDIV2 (0x2C)
109#define NPCM7XX_CLKDIV3 (0x58)
110#define NPCM7XX_PLLCON0 (0x0C)
111#define NPCM7XX_PLLCON1 (0x10)
112#define NPCM7XX_PLLCON2 (0x54)
113#define NPCM7XX_SWRSTR (0x14)
114#define NPCM7XX_IRQWAKECON (0x18)
115#define NPCM7XX_IRQWAKEFLAG (0x1C)
116#define NPCM7XX_IPSRST1 (0x20)
117#define NPCM7XX_IPSRST2 (0x24)
118#define NPCM7XX_IPSRST3 (0x34)
119#define NPCM7XX_WD0RCR (0x38)
120#define NPCM7XX_WD1RCR (0x3C)
121#define NPCM7XX_WD2RCR (0x40)
122#define NPCM7XX_SWRSTC1 (0x44)
123#define NPCM7XX_SWRSTC2 (0x48)
124#define NPCM7XX_SWRSTC3 (0x4C)
125#define NPCM7XX_SWRSTC4 (0x50)
126#define NPCM7XX_CORSTC (0x5C)
127#define NPCM7XX_PLLCONG (0x60)
128#define NPCM7XX_AHBCKFI (0x64)
129#define NPCM7XX_SECCNT (0x68)
130#define NPCM7XX_CNTR25M (0x6C)
131
132struct npcm7xx_clk_gate_data {
133 u32 reg;
134 u8 bit_idx;
135 const char *name;
136 const char *parent_name;
137 unsigned long flags;
138 /*
139 * If this clock is exported via DT, set onecell_idx to constant
140 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
141 * this specific clock. Otherwise, set to -1.
142 */
143 int onecell_idx;
144};
145
146struct npcm7xx_clk_mux_data {
147 u8 shift;
148 u8 mask;
149 u32 *table;
150 const char *name;
151 const char * const *parent_names;
152 u8 num_parents;
153 unsigned long flags;
154 /*
155 * If this clock is exported via DT, set onecell_idx to constant
156 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
157 * this specific clock. Otherwise, set to -1.
158 */
159 int onecell_idx;
160
161};
162
163struct npcm7xx_clk_div_fixed_data {
164 u8 mult;
165 u8 div;
166 const char *name;
167 const char *parent_name;
168 u8 clk_divider_flags;
169 /*
170 * If this clock is exported via DT, set onecell_idx to constant
171 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
172 * this specific clock. Otherwise, set to -1.
173 */
174 int onecell_idx;
175};
176
177
178struct npcm7xx_clk_div_data {
179 u32 reg;
180 u8 shift;
181 u8 width;
182 const char *name;
183 const char *parent_name;
184 u8 clk_divider_flags;
185 unsigned long flags;
186 /*
187 * If this clock is exported via DT, set onecell_idx to constant
188 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
189 * this specific clock. Otherwise, set to -1.
190 */
191 int onecell_idx;
192};
193
194struct npcm7xx_clk_pll_data {
195 u32 reg;
196 const char *name;
197 const char *parent_name;
198 unsigned long flags;
199 /*
200 * If this clock is exported via DT, set onecell_idx to constant
201 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
202 * this specific clock. Otherwise, set to -1.
203 */
204 int onecell_idx;
205};
206
207/*
208 * Single copy of strings used to refer to clocks within this driver indexed by
209 * above enum.
210 */
211#define NPCM7XX_CLK_S_REFCLK "refclk"
212#define NPCM7XX_CLK_S_SYSBYPCK "sysbypck"
213#define NPCM7XX_CLK_S_MCBYPCK "mcbypck"
214#define NPCM7XX_CLK_S_GFXBYPCK "gfxbypck"
215#define NPCM7XX_CLK_S_PLL0 "pll0"
216#define NPCM7XX_CLK_S_PLL1 "pll1"
217#define NPCM7XX_CLK_S_PLL1_DIV2 "pll1_div2"
218#define NPCM7XX_CLK_S_PLL2 "pll2"
219#define NPCM7XX_CLK_S_PLL_GFX "pll_gfx"
220#define NPCM7XX_CLK_S_PLL2_DIV2 "pll2_div2"
221#define NPCM7XX_CLK_S_PIX_MUX "gfx_pixel"
222#define NPCM7XX_CLK_S_GPRFSEL_MUX "gprfsel_mux"
223#define NPCM7XX_CLK_S_MC_MUX "mc_phy"
224#define NPCM7XX_CLK_S_CPU_MUX "cpu" /*AKA system clock.*/
225#define NPCM7XX_CLK_S_MC "mc"
226#define NPCM7XX_CLK_S_AXI "axi" /*AKA CLK2*/
227#define NPCM7XX_CLK_S_AHB "ahb" /*AKA CLK4*/
228#define NPCM7XX_CLK_S_CLKOUT_MUX "clkout_mux"
229#define NPCM7XX_CLK_S_UART_MUX "uart_mux"
230#define NPCM7XX_CLK_S_TIM_MUX "timer_mux"
231#define NPCM7XX_CLK_S_SD_MUX "sd_mux"
232#define NPCM7XX_CLK_S_GFXM_MUX "gfxm_mux"
233#define NPCM7XX_CLK_S_SU_MUX "serial_usb_mux"
234#define NPCM7XX_CLK_S_DVC_MUX "dvc_mux"
235#define NPCM7XX_CLK_S_GFX_MUX "gfx_mux"
236#define NPCM7XX_CLK_S_GFX_PIXEL "gfx_pixel"
237#define NPCM7XX_CLK_S_SPI0 "spi0"
238#define NPCM7XX_CLK_S_SPI3 "spi3"
239#define NPCM7XX_CLK_S_SPIX "spix"
240#define NPCM7XX_CLK_S_APB1 "apb1"
241#define NPCM7XX_CLK_S_APB2 "apb2"
242#define NPCM7XX_CLK_S_APB3 "apb3"
243#define NPCM7XX_CLK_S_APB4 "apb4"
244#define NPCM7XX_CLK_S_APB5 "apb5"
245#define NPCM7XX_CLK_S_TOCK "tock"
246#define NPCM7XX_CLK_S_CLKOUT "clkout"
247#define NPCM7XX_CLK_S_UART "uart"
248#define NPCM7XX_CLK_S_TIMER "timer"
249#define NPCM7XX_CLK_S_MMC "mmc"
250#define NPCM7XX_CLK_S_SDHC "sdhc"
251#define NPCM7XX_CLK_S_ADC "adc"
252#define NPCM7XX_CLK_S_GFX "gfx0_gfx1_mem"
253#define NPCM7XX_CLK_S_USBIF "serial_usbif"
254#define NPCM7XX_CLK_S_USB_HOST "usb_host"
255#define NPCM7XX_CLK_S_USB_BRIDGE "usb_bridge"
256#define NPCM7XX_CLK_S_PCI "pci"
257
258static u32 pll_mux_table[] = {0, 1, 2, 3};
259static const char * const pll_mux_parents[] __initconst = {
260 NPCM7XX_CLK_S_PLL0,
261 NPCM7XX_CLK_S_PLL1_DIV2,
262 NPCM7XX_CLK_S_REFCLK,
263 NPCM7XX_CLK_S_PLL2_DIV2,
264};
265
266static u32 cpuck_mux_table[] = {0, 1, 2, 3};
267static const char * const cpuck_mux_parents[] __initconst = {
268 NPCM7XX_CLK_S_PLL0,
269 NPCM7XX_CLK_S_PLL1_DIV2,
270 NPCM7XX_CLK_S_REFCLK,
271 NPCM7XX_CLK_S_SYSBYPCK,
272};
273
274static u32 pixcksel_mux_table[] = {0, 2};
275static const char * const pixcksel_mux_parents[] __initconst = {
276 NPCM7XX_CLK_S_PLL_GFX,
277 NPCM7XX_CLK_S_REFCLK,
278};
279
280static u32 sucksel_mux_table[] = {2, 3};
281static const char * const sucksel_mux_parents[] __initconst = {
282 NPCM7XX_CLK_S_REFCLK,
283 NPCM7XX_CLK_S_PLL2_DIV2,
284};
285
286static u32 mccksel_mux_table[] = {0, 2, 3};
287static const char * const mccksel_mux_parents[] __initconst = {
288 NPCM7XX_CLK_S_PLL1_DIV2,
289 NPCM7XX_CLK_S_REFCLK,
290 NPCM7XX_CLK_S_MCBYPCK,
291};
292
293static u32 clkoutsel_mux_table[] = {0, 1, 2, 3, 4};
294static const char * const clkoutsel_mux_parents[] __initconst = {
295 NPCM7XX_CLK_S_PLL0,
296 NPCM7XX_CLK_S_PLL1_DIV2,
297 NPCM7XX_CLK_S_REFCLK,
298 NPCM7XX_CLK_S_PLL_GFX, // divided by 2
299 NPCM7XX_CLK_S_PLL2_DIV2,
300};
301
302static u32 gfxmsel_mux_table[] = {2, 3};
303static const char * const gfxmsel_mux_parents[] __initconst = {
304 NPCM7XX_CLK_S_REFCLK,
305 NPCM7XX_CLK_S_PLL2_DIV2,
306};
307
308static u32 dvcssel_mux_table[] = {2, 3};
309static const char * const dvcssel_mux_parents[] __initconst = {
310 NPCM7XX_CLK_S_REFCLK,
311 NPCM7XX_CLK_S_PLL2,
312};
313
314static const struct npcm7xx_clk_pll_data npcm7xx_plls[] __initconst = {
315 {NPCM7XX_PLLCON0, NPCM7XX_CLK_S_PLL0, NPCM7XX_CLK_S_REFCLK, 0, -1},
316
317 {NPCM7XX_PLLCON1, NPCM7XX_CLK_S_PLL1,
318 NPCM7XX_CLK_S_REFCLK, 0, -1},
319
320 {NPCM7XX_PLLCON2, NPCM7XX_CLK_S_PLL2,
321 NPCM7XX_CLK_S_REFCLK, 0, -1},
322
323 {NPCM7XX_PLLCONG, NPCM7XX_CLK_S_PLL_GFX,
324 NPCM7XX_CLK_S_REFCLK, 0, -1},
325};
326
327static const struct npcm7xx_clk_mux_data npcm7xx_muxes[] __initconst = {
328 {0, GENMASK(1, 0), cpuck_mux_table, NPCM7XX_CLK_S_CPU_MUX,
329 cpuck_mux_parents, ARRAY_SIZE(cpuck_mux_parents), CLK_IS_CRITICAL,
330 NPCM7XX_CLK_CPU},
331
332 {4, GENMASK(1, 0), pixcksel_mux_table, NPCM7XX_CLK_S_PIX_MUX,
333 pixcksel_mux_parents, ARRAY_SIZE(pixcksel_mux_parents), 0,
334 NPCM7XX_CLK_GFX_PIXEL},
335
336 {6, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_SD_MUX,
337 pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
338
339 {8, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_UART_MUX,
340 pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
341
342 {10, GENMASK(1, 0), sucksel_mux_table, NPCM7XX_CLK_S_SU_MUX,
343 sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1},
344
345 {12, GENMASK(1, 0), mccksel_mux_table, NPCM7XX_CLK_S_MC_MUX,
346 mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1},
347
348 {14, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_TIM_MUX,
349 pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
350
351 {16, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_GFX_MUX,
352 pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
353
354 {18, GENMASK(2, 0), clkoutsel_mux_table, NPCM7XX_CLK_S_CLKOUT_MUX,
355 clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1},
356
357 {21, GENMASK(1, 0), gfxmsel_mux_table, NPCM7XX_CLK_S_GFXM_MUX,
358 gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1},
359
360 {23, GENMASK(1, 0), dvcssel_mux_table, NPCM7XX_CLK_S_DVC_MUX,
361 dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1},
362};
363
364/* fixed ratio dividers (no register): */
365static const struct npcm7xx_clk_div_fixed_data npcm7xx_divs_fx[] __initconst = {
366 { 1, 2, NPCM7XX_CLK_S_MC, NPCM7XX_CLK_S_MC_MUX, 0, NPCM7XX_CLK_MC},
367 { 1, 2, NPCM7XX_CLK_S_PLL1_DIV2, NPCM7XX_CLK_S_PLL1, 0, -1},
368 { 1, 2, NPCM7XX_CLK_S_PLL2_DIV2, NPCM7XX_CLK_S_PLL2, 0, -1},
369};
370
371/* configurable dividers: */
372static const struct npcm7xx_clk_div_data npcm7xx_divs[] __initconst = {
373 {NPCM7XX_CLKDIV1, 28, 3, NPCM7XX_CLK_S_ADC,
374 NPCM7XX_CLK_S_TIMER, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_ADC},
375 /*30-28 ADCCKDIV*/
376 {NPCM7XX_CLKDIV1, 26, 2, NPCM7XX_CLK_S_AHB,
377 NPCM7XX_CLK_S_AXI, 0, CLK_IS_CRITICAL, NPCM7XX_CLK_AHB},
378 /*27-26 CLK4DIV*/
379 {NPCM7XX_CLKDIV1, 21, 5, NPCM7XX_CLK_S_TIMER,
380 NPCM7XX_CLK_S_TIM_MUX, 0, 0, NPCM7XX_CLK_TIMER},
381 /*25-21 TIMCKDIV*/
382 {NPCM7XX_CLKDIV1, 16, 5, NPCM7XX_CLK_S_UART,
383 NPCM7XX_CLK_S_UART_MUX, 0, 0, NPCM7XX_CLK_UART},
384 /*20-16 UARTDIV*/
385 {NPCM7XX_CLKDIV1, 11, 5, NPCM7XX_CLK_S_MMC,
386 NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_MMC},
387 /*15-11 MMCCKDIV*/
388 {NPCM7XX_CLKDIV1, 6, 5, NPCM7XX_CLK_S_SPI3,
389 NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI3},
390 /*10-6 AHB3CKDIV*/
391 {NPCM7XX_CLKDIV1, 2, 4, NPCM7XX_CLK_S_PCI,
392 NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_PCI},
393 /*5-2 PCICKDIV*/
394 {NPCM7XX_CLKDIV1, 0, 1, NPCM7XX_CLK_S_AXI,
395 NPCM7XX_CLK_S_CPU_MUX, CLK_DIVIDER_POWER_OF_TWO, CLK_IS_CRITICAL,
396 NPCM7XX_CLK_AXI},/*0 CLK2DIV*/
397
398 {NPCM7XX_CLKDIV2, 30, 2, NPCM7XX_CLK_S_APB4,
399 NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB4},
400 /*31-30 APB4CKDIV*/
401 {NPCM7XX_CLKDIV2, 28, 2, NPCM7XX_CLK_S_APB3,
402 NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB3},
403 /*29-28 APB3CKDIV*/
404 {NPCM7XX_CLKDIV2, 26, 2, NPCM7XX_CLK_S_APB2,
405 NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB2},
406 /*27-26 APB2CKDIV*/
407 {NPCM7XX_CLKDIV2, 24, 2, NPCM7XX_CLK_S_APB1,
408 NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB1},
409 /*25-24 APB1CKDIV*/
410 {NPCM7XX_CLKDIV2, 22, 2, NPCM7XX_CLK_S_APB5,
411 NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB5},
412 /*23-22 APB5CKDIV*/
413 {NPCM7XX_CLKDIV2, 16, 5, NPCM7XX_CLK_S_CLKOUT,
414 NPCM7XX_CLK_S_CLKOUT_MUX, 0, 0, NPCM7XX_CLK_CLKOUT},
415 /*20-16 CLKOUTDIV*/
416 {NPCM7XX_CLKDIV2, 13, 3, NPCM7XX_CLK_S_GFX,
417 NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_GFX},
418 /*15-13 GFXCKDIV*/
419 {NPCM7XX_CLKDIV2, 8, 5, NPCM7XX_CLK_S_USB_BRIDGE,
420 NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU},
421 /*12-8 SUCKDIV*/
422 {NPCM7XX_CLKDIV2, 4, 4, NPCM7XX_CLK_S_USB_HOST,
423 NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU48},
424 /*7-4 SU48CKDIV*/
425 {NPCM7XX_CLKDIV2, 0, 4, NPCM7XX_CLK_S_SDHC,
426 NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_SDHC}
427 ,/*3-0 SD1CKDIV*/
428
429 {NPCM7XX_CLKDIV3, 6, 5, NPCM7XX_CLK_S_SPI0,
430 NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI0},
431 /*10-6 SPI0CKDV*/
432 {NPCM7XX_CLKDIV3, 1, 5, NPCM7XX_CLK_S_SPIX,
433 NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPIX},
434 /*5-1 SPIXCKDV*/
435
436};
437
438static const struct npcm7xx_clk_gate_data npcm7xx_gates[] __initconst = {
439 {NPCM7XX_CLKEN1, 31, "smb1-gate", NPCM7XX_CLK_S_APB2, 0},
440 {NPCM7XX_CLKEN1, 30, "smb0-gate", NPCM7XX_CLK_S_APB2, 0},
441 {NPCM7XX_CLKEN1, 29, "smb7-gate", NPCM7XX_CLK_S_APB2, 0},
442 {NPCM7XX_CLKEN1, 28, "smb6-gate", NPCM7XX_CLK_S_APB2, 0},
443 {NPCM7XX_CLKEN1, 27, "adc-gate", NPCM7XX_CLK_S_APB1, 0},
444 {NPCM7XX_CLKEN1, 26, "wdt-gate", NPCM7XX_CLK_S_TIMER, 0},
445 {NPCM7XX_CLKEN1, 25, "usbdev3-gate", NPCM7XX_CLK_S_AHB, 0},
446 {NPCM7XX_CLKEN1, 24, "usbdev6-gate", NPCM7XX_CLK_S_AHB, 0},
447 {NPCM7XX_CLKEN1, 23, "usbdev5-gate", NPCM7XX_CLK_S_AHB, 0},
448 {NPCM7XX_CLKEN1, 22, "usbdev4-gate", NPCM7XX_CLK_S_AHB, 0},
449 {NPCM7XX_CLKEN1, 21, "emc2-gate", NPCM7XX_CLK_S_AHB, 0},
450 {NPCM7XX_CLKEN1, 20, "timer5_9-gate", NPCM7XX_CLK_S_APB1, 0},
451 {NPCM7XX_CLKEN1, 19, "timer0_4-gate", NPCM7XX_CLK_S_APB1, 0},
452 {NPCM7XX_CLKEN1, 18, "pwmm0-gate", NPCM7XX_CLK_S_APB3, 0},
453 {NPCM7XX_CLKEN1, 17, "huart-gate", NPCM7XX_CLK_S_UART, 0},
454 {NPCM7XX_CLKEN1, 16, "smb5-gate", NPCM7XX_CLK_S_APB2, 0},
455 {NPCM7XX_CLKEN1, 15, "smb4-gate", NPCM7XX_CLK_S_APB2, 0},
456 {NPCM7XX_CLKEN1, 14, "smb3-gate", NPCM7XX_CLK_S_APB2, 0},
457 {NPCM7XX_CLKEN1, 13, "smb2-gate", NPCM7XX_CLK_S_APB2, 0},
458 {NPCM7XX_CLKEN1, 12, "mc-gate", NPCM7XX_CLK_S_MC, 0},
459 {NPCM7XX_CLKEN1, 11, "uart01-gate", NPCM7XX_CLK_S_APB1, 0},
460 {NPCM7XX_CLKEN1, 10, "aes-gate", NPCM7XX_CLK_S_AHB, 0},
461 {NPCM7XX_CLKEN1, 9, "peci-gate", NPCM7XX_CLK_S_APB3, 0},
462 {NPCM7XX_CLKEN1, 8, "usbdev2-gate", NPCM7XX_CLK_S_AHB, 0},
463 {NPCM7XX_CLKEN1, 7, "uart23-gate", NPCM7XX_CLK_S_APB1, 0},
464 {NPCM7XX_CLKEN1, 6, "emc1-gate", NPCM7XX_CLK_S_AHB, 0},
465 {NPCM7XX_CLKEN1, 5, "usbdev1-gate", NPCM7XX_CLK_S_AHB, 0},
466 {NPCM7XX_CLKEN1, 4, "shm-gate", NPCM7XX_CLK_S_AHB, 0},
467 /* bit 3 is reserved */
468 {NPCM7XX_CLKEN1, 2, "kcs-gate", NPCM7XX_CLK_S_APB1, 0},
469 {NPCM7XX_CLKEN1, 1, "spi3-gate", NPCM7XX_CLK_S_AHB, 0},
470 {NPCM7XX_CLKEN1, 0, "spi0-gate", NPCM7XX_CLK_S_AHB, 0},
471
472 {NPCM7XX_CLKEN2, 31, "cp-gate", NPCM7XX_CLK_S_AHB, 0},
473 {NPCM7XX_CLKEN2, 30, "tock-gate", NPCM7XX_CLK_S_TOCK, 0},
474 /* bit 29 is reserved */
475 {NPCM7XX_CLKEN2, 28, "gmac1-gate", NPCM7XX_CLK_S_AHB, 0},
476 {NPCM7XX_CLKEN2, 27, "usbif-gate", NPCM7XX_CLK_S_USBIF, 0},
477 {NPCM7XX_CLKEN2, 26, "usbhost-gate", NPCM7XX_CLK_S_AHB, 0},
478 {NPCM7XX_CLKEN2, 25, "gmac2-gate", NPCM7XX_CLK_S_AHB, 0},
479 /* bit 24 is reserved */
480 {NPCM7XX_CLKEN2, 23, "pspi2-gate", NPCM7XX_CLK_S_APB5, 0},
481 {NPCM7XX_CLKEN2, 22, "pspi1-gate", NPCM7XX_CLK_S_APB5, 0},
482 {NPCM7XX_CLKEN2, 21, "3des-gate", NPCM7XX_CLK_S_AHB, 0},
483 /* bit 20 is reserved */
484 {NPCM7XX_CLKEN2, 19, "siox2-gate", NPCM7XX_CLK_S_APB3, 0},
485 {NPCM7XX_CLKEN2, 18, "siox1-gate", NPCM7XX_CLK_S_APB3, 0},
486 /* bit 17 is reserved */
487 {NPCM7XX_CLKEN2, 16, "fuse-gate", NPCM7XX_CLK_S_APB4, 0},
488 /* bit 15 is reserved */
489 {NPCM7XX_CLKEN2, 14, "vcd-gate", NPCM7XX_CLK_S_AHB, 0},
490 {NPCM7XX_CLKEN2, 13, "ece-gate", NPCM7XX_CLK_S_AHB, 0},
491 {NPCM7XX_CLKEN2, 12, "vdma-gate", NPCM7XX_CLK_S_AHB, 0},
492 {NPCM7XX_CLKEN2, 11, "ahbpcibrg-gate", NPCM7XX_CLK_S_AHB, 0},
493 {NPCM7XX_CLKEN2, 10, "gfxsys-gate", NPCM7XX_CLK_S_APB1, 0},
494 {NPCM7XX_CLKEN2, 9, "sdhc-gate", NPCM7XX_CLK_S_AHB, 0},
495 {NPCM7XX_CLKEN2, 8, "mmc-gate", NPCM7XX_CLK_S_AHB, 0},
496 {NPCM7XX_CLKEN2, 7, "mft7-gate", NPCM7XX_CLK_S_APB4, 0},
497 {NPCM7XX_CLKEN2, 6, "mft6-gate", NPCM7XX_CLK_S_APB4, 0},
498 {NPCM7XX_CLKEN2, 5, "mft5-gate", NPCM7XX_CLK_S_APB4, 0},
499 {NPCM7XX_CLKEN2, 4, "mft4-gate", NPCM7XX_CLK_S_APB4, 0},
500 {NPCM7XX_CLKEN2, 3, "mft3-gate", NPCM7XX_CLK_S_APB4, 0},
501 {NPCM7XX_CLKEN2, 2, "mft2-gate", NPCM7XX_CLK_S_APB4, 0},
502 {NPCM7XX_CLKEN2, 1, "mft1-gate", NPCM7XX_CLK_S_APB4, 0},
503 {NPCM7XX_CLKEN2, 0, "mft0-gate", NPCM7XX_CLK_S_APB4, 0},
504
505 {NPCM7XX_CLKEN3, 31, "gpiom7-gate", NPCM7XX_CLK_S_APB1, 0},
506 {NPCM7XX_CLKEN3, 30, "gpiom6-gate", NPCM7XX_CLK_S_APB1, 0},
507 {NPCM7XX_CLKEN3, 29, "gpiom5-gate", NPCM7XX_CLK_S_APB1, 0},
508 {NPCM7XX_CLKEN3, 28, "gpiom4-gate", NPCM7XX_CLK_S_APB1, 0},
509 {NPCM7XX_CLKEN3, 27, "gpiom3-gate", NPCM7XX_CLK_S_APB1, 0},
510 {NPCM7XX_CLKEN3, 26, "gpiom2-gate", NPCM7XX_CLK_S_APB1, 0},
511 {NPCM7XX_CLKEN3, 25, "gpiom1-gate", NPCM7XX_CLK_S_APB1, 0},
512 {NPCM7XX_CLKEN3, 24, "gpiom0-gate", NPCM7XX_CLK_S_APB1, 0},
513 {NPCM7XX_CLKEN3, 23, "espi-gate", NPCM7XX_CLK_S_APB2, 0},
514 {NPCM7XX_CLKEN3, 22, "smb11-gate", NPCM7XX_CLK_S_APB2, 0},
515 {NPCM7XX_CLKEN3, 21, "smb10-gate", NPCM7XX_CLK_S_APB2, 0},
516 {NPCM7XX_CLKEN3, 20, "smb9-gate", NPCM7XX_CLK_S_APB2, 0},
517 {NPCM7XX_CLKEN3, 19, "smb8-gate", NPCM7XX_CLK_S_APB2, 0},
518 {NPCM7XX_CLKEN3, 18, "smb15-gate", NPCM7XX_CLK_S_APB2, 0},
519 {NPCM7XX_CLKEN3, 17, "rng-gate", NPCM7XX_CLK_S_APB1, 0},
520 {NPCM7XX_CLKEN3, 16, "timer10_14-gate", NPCM7XX_CLK_S_APB1, 0},
521 {NPCM7XX_CLKEN3, 15, "pcirc-gate", NPCM7XX_CLK_S_AHB, 0},
522 {NPCM7XX_CLKEN3, 14, "sececc-gate", NPCM7XX_CLK_S_AHB, 0},
523 {NPCM7XX_CLKEN3, 13, "sha-gate", NPCM7XX_CLK_S_AHB, 0},
524 {NPCM7XX_CLKEN3, 12, "smb14-gate", NPCM7XX_CLK_S_APB2, 0},
525 /* bit 11 is reserved */
526 /* bit 10 is reserved */
527 {NPCM7XX_CLKEN3, 9, "pcimbx-gate", NPCM7XX_CLK_S_AHB, 0},
528 /* bit 8 is reserved */
529 {NPCM7XX_CLKEN3, 7, "usbdev9-gate", NPCM7XX_CLK_S_AHB, 0},
530 {NPCM7XX_CLKEN3, 6, "usbdev8-gate", NPCM7XX_CLK_S_AHB, 0},
531 {NPCM7XX_CLKEN3, 5, "usbdev7-gate", NPCM7XX_CLK_S_AHB, 0},
532 {NPCM7XX_CLKEN3, 4, "usbdev0-gate", NPCM7XX_CLK_S_AHB, 0},
533 {NPCM7XX_CLKEN3, 3, "smb13-gate", NPCM7XX_CLK_S_APB2, 0},
534 {NPCM7XX_CLKEN3, 2, "spix-gate", NPCM7XX_CLK_S_AHB, 0},
535 {NPCM7XX_CLKEN3, 1, "smb12-gate", NPCM7XX_CLK_S_APB2, 0},
536 {NPCM7XX_CLKEN3, 0, "pwmm1-gate", NPCM7XX_CLK_S_APB3, 0},
537};
538
539static DEFINE_SPINLOCK(npcm7xx_clk_lock);
540
541static void __init npcm7xx_clk_init(struct device_node *clk_np)
542{
543 struct clk_hw_onecell_data *npcm7xx_clk_data;
544 void __iomem *clk_base;
545 struct resource res;
546 struct clk_hw *hw;
547 int ret;
548 int i;
549
550 ret = of_address_to_resource(clk_np, 0, &res);
551 if (ret) {
552 pr_err("%s: failed to get resource, ret %d\n", clk_np->name,
553 ret);
554 return;
555 }
556
557 clk_base = ioremap(res.start, resource_size(&res));
558 if (!clk_base)
559 goto npcm7xx_init_error;
560
561 npcm7xx_clk_data = kzalloc(sizeof(*npcm7xx_clk_data->hws) *
562 NPCM7XX_NUM_CLOCKS + sizeof(npcm7xx_clk_data), GFP_KERNEL);
563 if (!npcm7xx_clk_data)
564 goto npcm7xx_init_np_err;
565
566 npcm7xx_clk_data->num = NPCM7XX_NUM_CLOCKS;
567
568 for (i = 0; i < NPCM7XX_NUM_CLOCKS; i++)
569 npcm7xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
570
571 /* Register plls */
572 for (i = 0; i < ARRAY_SIZE(npcm7xx_plls); i++) {
573 const struct npcm7xx_clk_pll_data *pll_data = &npcm7xx_plls[i];
574
575 hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg,
576 pll_data->name, pll_data->parent_name, pll_data->flags);
577 if (IS_ERR(hw)) {
578 pr_err("npcm7xx_clk: Can't register pll\n");
579 goto npcm7xx_init_fail;
580 }
581
582 if (pll_data->onecell_idx >= 0)
583 npcm7xx_clk_data->hws[pll_data->onecell_idx] = hw;
584 }
585
586 /* Register fixed dividers */
587 hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL1_DIV2,
588 NPCM7XX_CLK_S_PLL1, 0, 1, 2);
589 if (IS_ERR(hw)) {
590 pr_err("npcm7xx_clk: Can't register fixed div\n");
591 goto npcm7xx_init_fail;
592 }
593
594 hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL2_DIV2,
595 NPCM7XX_CLK_S_PLL2, 0, 1, 2);
596 if (IS_ERR(hw)) {
597 pr_err("npcm7xx_clk: Can't register div2\n");
598 goto npcm7xx_init_fail;
599 }
600
601 /* Register muxes */
602 for (i = 0; i < ARRAY_SIZE(npcm7xx_muxes); i++) {
603 const struct npcm7xx_clk_mux_data *mux_data = &npcm7xx_muxes[i];
604
605 hw = clk_hw_register_mux_table(NULL,
606 mux_data->name,
607 mux_data->parent_names, mux_data->num_parents,
608 mux_data->flags, clk_base + NPCM7XX_CLKSEL,
609 mux_data->shift, mux_data->mask, 0,
610 mux_data->table, &npcm7xx_clk_lock);
611
612 if (IS_ERR(hw)) {
613 pr_err("npcm7xx_clk: Can't register mux\n");
614 goto npcm7xx_init_fail;
615 }
616
617 if (mux_data->onecell_idx >= 0)
618 npcm7xx_clk_data->hws[mux_data->onecell_idx] = hw;
619 }
620
621 /* Register clock dividers specified in npcm7xx_divs */
622 for (i = 0; i < ARRAY_SIZE(npcm7xx_divs); i++) {
623 const struct npcm7xx_clk_div_data *div_data = &npcm7xx_divs[i];
624
625 hw = clk_hw_register_divider(NULL, div_data->name,
626 div_data->parent_name,
627 div_data->flags,
628 clk_base + div_data->reg,
629 div_data->shift, div_data->width,
630 div_data->clk_divider_flags, &npcm7xx_clk_lock);
631 if (IS_ERR(hw)) {
632 pr_err("npcm7xx_clk: Can't register div table\n");
633 goto npcm7xx_init_fail;
634 }
635
636 if (div_data->onecell_idx >= 0)
637 npcm7xx_clk_data->hws[div_data->onecell_idx] = hw;
638 }
639
640 ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get,
641 npcm7xx_clk_data);
642 if (ret)
643 pr_err("failed to add DT provider: %d\n", ret);
644
645 of_node_put(clk_np);
646
647 return;
648
649npcm7xx_init_fail:
650 kfree(npcm7xx_clk_data->hws);
651npcm7xx_init_np_err:
652 iounmap(clk_base);
653npcm7xx_init_error:
654 of_node_put(clk_np);
655}
656CLK_OF_DECLARE(npcm7xx_clk_init, "nuvoton,npcm750-clk", npcm7xx_clk_init);
diff --git a/drivers/clk/clk-si544.c b/drivers/clk/clk-si544.c
index 1c96a9f6c022..1e2a3b8f9454 100644
--- a/drivers/clk/clk-si544.c
+++ b/drivers/clk/clk-si544.c
@@ -207,6 +207,7 @@ static int si544_calc_muldiv(struct clk_si544_muldiv *settings,
207 207
208 /* And the fractional bits using the remainder */ 208 /* And the fractional bits using the remainder */
209 vco = (u64)tmp << 32; 209 vco = (u64)tmp << 32;
210 vco += FXO / 2; /* Round to nearest multiple */
210 do_div(vco, FXO); 211 do_div(vco, FXO);
211 settings->fb_div_frac = vco; 212 settings->fb_div_frac = vco;
212 213
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index f1d5967b4b39..e68cb478f21f 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -216,7 +216,7 @@ static const char * const usart1_src[] = {
216 "pclk5", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse" 216 "pclk5", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
217}; 217};
218 218
219const char * const usart234578_src[] = { 219static const char * const usart234578_src[] = {
220 "pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse" 220 "pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
221}; 221};
222 222
@@ -224,10 +224,6 @@ static const char * const usart6_src[] = {
224 "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse" 224 "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
225}; 225};
226 226
227static const char * const dfsdm_src[] = {
228 "pclk2", "ck_mcu"
229};
230
231static const char * const fdcan_src[] = { 227static const char * const fdcan_src[] = {
232 "ck_hse", "pll3_q", "pll4_q" 228 "ck_hse", "pll3_q", "pll4_q"
233}; 229};
@@ -316,10 +312,8 @@ struct stm32_clk_mgate {
316struct clock_config { 312struct clock_config {
317 u32 id; 313 u32 id;
318 const char *name; 314 const char *name;
319 union { 315 const char *parent_name;
320 const char *parent_name; 316 const char * const *parent_names;
321 const char * const *parent_names;
322 };
323 int num_parents; 317 int num_parents;
324 unsigned long flags; 318 unsigned long flags;
325 void *cfg; 319 void *cfg;
@@ -469,7 +463,7 @@ static void mp1_gate_clk_disable(struct clk_hw *hw)
469 } 463 }
470} 464}
471 465
472const struct clk_ops mp1_gate_clk_ops = { 466static const struct clk_ops mp1_gate_clk_ops = {
473 .enable = mp1_gate_clk_enable, 467 .enable = mp1_gate_clk_enable,
474 .disable = mp1_gate_clk_disable, 468 .disable = mp1_gate_clk_disable,
475 .is_enabled = clk_gate_is_enabled, 469 .is_enabled = clk_gate_is_enabled,
@@ -585,14 +579,9 @@ clk_stm32_register_gate_ops(struct device *dev,
585 spinlock_t *lock) 579 spinlock_t *lock)
586{ 580{
587 struct clk_init_data init = { NULL }; 581 struct clk_init_data init = { NULL };
588 struct clk_gate *gate;
589 struct clk_hw *hw; 582 struct clk_hw *hw;
590 int ret; 583 int ret;
591 584
592 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
593 if (!gate)
594 return ERR_PTR(-ENOMEM);
595
596 init.name = name; 585 init.name = name;
597 init.parent_names = &parent_name; 586 init.parent_names = &parent_name;
598 init.num_parents = 1; 587 init.num_parents = 1;
@@ -610,10 +599,8 @@ clk_stm32_register_gate_ops(struct device *dev,
610 hw->init = &init; 599 hw->init = &init;
611 600
612 ret = clk_hw_register(dev, hw); 601 ret = clk_hw_register(dev, hw);
613 if (ret) { 602 if (ret)
614 kfree(gate);
615 hw = ERR_PTR(ret); 603 hw = ERR_PTR(ret);
616 }
617 604
618 return hw; 605 return hw;
619} 606}
@@ -698,7 +685,7 @@ static void mp1_mgate_clk_disable(struct clk_hw *hw)
698 mp1_gate_clk_disable(hw); 685 mp1_gate_clk_disable(hw);
699} 686}
700 687
701const struct clk_ops mp1_mgate_clk_ops = { 688static const struct clk_ops mp1_mgate_clk_ops = {
702 .enable = mp1_mgate_clk_enable, 689 .enable = mp1_mgate_clk_enable,
703 .disable = mp1_mgate_clk_disable, 690 .disable = mp1_mgate_clk_disable,
704 .is_enabled = clk_gate_is_enabled, 691 .is_enabled = clk_gate_is_enabled,
@@ -732,7 +719,7 @@ static int clk_mmux_set_parent(struct clk_hw *hw, u8 index)
732 return 0; 719 return 0;
733} 720}
734 721
735const struct clk_ops clk_mmux_ops = { 722static const struct clk_ops clk_mmux_ops = {
736 .get_parent = clk_mmux_get_parent, 723 .get_parent = clk_mmux_get_parent,
737 .set_parent = clk_mmux_set_parent, 724 .set_parent = clk_mmux_set_parent,
738 .determine_rate = __clk_mux_determine_rate, 725 .determine_rate = __clk_mux_determine_rate,
@@ -1048,10 +1035,10 @@ struct stm32_pll_cfg {
1048 u32 offset; 1035 u32 offset;
1049}; 1036};
1050 1037
1051struct clk_hw *_clk_register_pll(struct device *dev, 1038static struct clk_hw *_clk_register_pll(struct device *dev,
1052 struct clk_hw_onecell_data *clk_data, 1039 struct clk_hw_onecell_data *clk_data,
1053 void __iomem *base, spinlock_t *lock, 1040 void __iomem *base, spinlock_t *lock,
1054 const struct clock_config *cfg) 1041 const struct clock_config *cfg)
1055{ 1042{
1056 struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg; 1043 struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
1057 1044
@@ -1405,7 +1392,8 @@ enum {
1405 G_USBH, 1392 G_USBH,
1406 G_ETHSTP, 1393 G_ETHSTP,
1407 G_RTCAPB, 1394 G_RTCAPB,
1408 G_TZC, 1395 G_TZC1,
1396 G_TZC2,
1409 G_TZPC, 1397 G_TZPC,
1410 G_IWDG1, 1398 G_IWDG1,
1411 G_BSEC, 1399 G_BSEC,
@@ -1417,7 +1405,7 @@ enum {
1417 G_LAST 1405 G_LAST
1418}; 1406};
1419 1407
1420struct stm32_mgate mp1_mgate[G_LAST]; 1408static struct stm32_mgate mp1_mgate[G_LAST];
1421 1409
1422#define _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\ 1410#define _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
1423 _mgate, _ops)\ 1411 _mgate, _ops)\
@@ -1440,7 +1428,7 @@ struct stm32_mgate mp1_mgate[G_LAST];
1440 &mp1_mgate[_id], &mp1_mgate_clk_ops) 1428 &mp1_mgate[_id], &mp1_mgate_clk_ops)
1441 1429
1442/* Peripheral gates */ 1430/* Peripheral gates */
1443struct stm32_gate_cfg per_gate_cfg[G_LAST] = { 1431static struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
1444 /* Multi gates */ 1432 /* Multi gates */
1445 K_GATE(G_MDIO, RCC_APB1ENSETR, 31, 0), 1433 K_GATE(G_MDIO, RCC_APB1ENSETR, 31, 0),
1446 K_MGATE(G_DAC12, RCC_APB1ENSETR, 29, 0), 1434 K_MGATE(G_DAC12, RCC_APB1ENSETR, 29, 0),
@@ -1506,7 +1494,8 @@ struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
1506 K_GATE(G_BSEC, RCC_APB5ENSETR, 16, 0), 1494 K_GATE(G_BSEC, RCC_APB5ENSETR, 16, 0),
1507 K_GATE(G_IWDG1, RCC_APB5ENSETR, 15, 0), 1495 K_GATE(G_IWDG1, RCC_APB5ENSETR, 15, 0),
1508 K_GATE(G_TZPC, RCC_APB5ENSETR, 13, 0), 1496 K_GATE(G_TZPC, RCC_APB5ENSETR, 13, 0),
1509 K_GATE(G_TZC, RCC_APB5ENSETR, 12, 0), 1497 K_GATE(G_TZC2, RCC_APB5ENSETR, 12, 0),
1498 K_GATE(G_TZC1, RCC_APB5ENSETR, 11, 0),
1510 K_GATE(G_RTCAPB, RCC_APB5ENSETR, 8, 0), 1499 K_GATE(G_RTCAPB, RCC_APB5ENSETR, 8, 0),
1511 K_MGATE(G_USART1, RCC_APB5ENSETR, 4, 0), 1500 K_MGATE(G_USART1, RCC_APB5ENSETR, 4, 0),
1512 K_MGATE(G_I2C6, RCC_APB5ENSETR, 3, 0), 1501 K_MGATE(G_I2C6, RCC_APB5ENSETR, 3, 0),
@@ -1600,7 +1589,7 @@ enum {
1600 M_LAST 1589 M_LAST
1601}; 1590};
1602 1591
1603struct stm32_mmux ker_mux[M_LAST]; 1592static struct stm32_mmux ker_mux[M_LAST];
1604 1593
1605#define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\ 1594#define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\
1606 [_id] = {\ 1595 [_id] = {\
@@ -1623,7 +1612,7 @@ struct stm32_mmux ker_mux[M_LAST];
1623 _K_MUX(_id, _offset, _shift, _width, _mux_flags,\ 1612 _K_MUX(_id, _offset, _shift, _width, _mux_flags,\
1624 &ker_mux[_id], &clk_mmux_ops) 1613 &ker_mux[_id], &clk_mmux_ops)
1625 1614
1626const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = { 1615static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
1627 /* Kernel multi mux */ 1616 /* Kernel multi mux */
1628 K_MMUX(M_SDMMC12, RCC_SDMMC12CKSELR, 0, 3, 0), 1617 K_MMUX(M_SDMMC12, RCC_SDMMC12CKSELR, 0, 3, 0),
1629 K_MMUX(M_SPI23, RCC_SPI2S23CKSELR, 0, 3, 0), 1618 K_MMUX(M_SPI23, RCC_SPI2S23CKSELR, 0, 3, 0),
@@ -1860,7 +1849,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
1860 PCLK(USART1, "usart1", "pclk5", 0, G_USART1), 1849 PCLK(USART1, "usart1", "pclk5", 0, G_USART1),
1861 PCLK(RTCAPB, "rtcapb", "pclk5", CLK_IGNORE_UNUSED | 1850 PCLK(RTCAPB, "rtcapb", "pclk5", CLK_IGNORE_UNUSED |
1862 CLK_IS_CRITICAL, G_RTCAPB), 1851 CLK_IS_CRITICAL, G_RTCAPB),
1863 PCLK(TZC, "tzc", "pclk5", CLK_IGNORE_UNUSED, G_TZC), 1852 PCLK(TZC1, "tzc1", "ck_axi", CLK_IGNORE_UNUSED, G_TZC1),
1853 PCLK(TZC2, "tzc2", "ck_axi", CLK_IGNORE_UNUSED, G_TZC2),
1864 PCLK(TZPC, "tzpc", "pclk5", CLK_IGNORE_UNUSED, G_TZPC), 1854 PCLK(TZPC, "tzpc", "pclk5", CLK_IGNORE_UNUSED, G_TZPC),
1865 PCLK(IWDG1, "iwdg1", "pclk5", 0, G_IWDG1), 1855 PCLK(IWDG1, "iwdg1", "pclk5", 0, G_IWDG1),
1866 PCLK(BSEC, "bsec", "pclk5", CLK_IGNORE_UNUSED, G_BSEC), 1856 PCLK(BSEC, "bsec", "pclk5", CLK_IGNORE_UNUSED, G_BSEC),
@@ -1916,8 +1906,7 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
1916 KCLK(RNG1_K, "rng1_k", rng_src, 0, G_RNG1, M_RNG1), 1906 KCLK(RNG1_K, "rng1_k", rng_src, 0, G_RNG1, M_RNG1),
1917 KCLK(RNG2_K, "rng2_k", rng_src, 0, G_RNG2, M_RNG2), 1907 KCLK(RNG2_K, "rng2_k", rng_src, 0, G_RNG2, M_RNG2),
1918 KCLK(USBPHY_K, "usbphy_k", usbphy_src, 0, G_USBPHY, M_USBPHY), 1908 KCLK(USBPHY_K, "usbphy_k", usbphy_src, 0, G_USBPHY, M_USBPHY),
1919 KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IGNORE_UNUSED, 1909 KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IS_CRITICAL, G_STGEN, M_STGEN),
1920 G_STGEN, M_STGEN),
1921 KCLK(SPDIF_K, "spdif_k", spdif_src, 0, G_SPDIF, M_SPDIF), 1910 KCLK(SPDIF_K, "spdif_k", spdif_src, 0, G_SPDIF, M_SPDIF),
1922 KCLK(SPI1_K, "spi1_k", spi123_src, 0, G_SPI1, M_SPI1), 1911 KCLK(SPI1_K, "spi1_k", spi123_src, 0, G_SPI1, M_SPI1),
1923 KCLK(SPI2_K, "spi2_k", spi123_src, 0, G_SPI2, M_SPI23), 1912 KCLK(SPI2_K, "spi2_k", spi123_src, 0, G_SPI2, M_SPI23),
@@ -1948,8 +1937,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
1948 KCLK(FDCAN_K, "fdcan_k", fdcan_src, 0, G_FDCAN, M_FDCAN), 1937 KCLK(FDCAN_K, "fdcan_k", fdcan_src, 0, G_FDCAN, M_FDCAN),
1949 KCLK(SAI1_K, "sai1_k", sai_src, 0, G_SAI1, M_SAI1), 1938 KCLK(SAI1_K, "sai1_k", sai_src, 0, G_SAI1, M_SAI1),
1950 KCLK(SAI2_K, "sai2_k", sai2_src, 0, G_SAI2, M_SAI2), 1939 KCLK(SAI2_K, "sai2_k", sai2_src, 0, G_SAI2, M_SAI2),
1951 KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI2, M_SAI3), 1940 KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI3, M_SAI3),
1952 KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI2, M_SAI4), 1941 KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI4, M_SAI4),
1953 KCLK(ADC12_K, "adc12_k", adc12_src, 0, G_ADC12, M_ADC12), 1942 KCLK(ADC12_K, "adc12_k", adc12_src, 0, G_ADC12, M_ADC12),
1954 KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI), 1943 KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI),
1955 KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1), 1944 KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1),
@@ -1992,11 +1981,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
1992 _DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)), 1981 _DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
1993 1982
1994 /* Debug clocks */ 1983 /* Debug clocks */
1995 FIXED_FACTOR(NO_ID, "ck_axi_div2", "ck_axi", 0, 1, 2), 1984 GATE(CK_DBG, "ck_sys_dbg", "ck_axi", CLK_IGNORE_UNUSED,
1996 1985 RCC_DBGCFGR, 8, 0),
1997 GATE(DBG, "ck_apb_dbg", "ck_axi_div2", 0, RCC_DBGCFGR, 8, 0),
1998
1999 GATE(CK_DBG, "ck_sys_dbg", "ck_axi", 0, RCC_DBGCFGR, 8, 0),
2000 1986
2001 COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE, 1987 COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
2002 _GATE(RCC_DBGCFGR, 9, 0), 1988 _GATE(RCC_DBGCFGR, 9, 0),
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index ea67ac81c6f9..940347e38c16 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -548,7 +548,8 @@ static void clk_core_rate_unprotect(struct clk_core *core)
548 if (!core) 548 if (!core)
549 return; 549 return;
550 550
551 if (WARN_ON(core->protect_count == 0)) 551 if (WARN(core->protect_count == 0,
552 "%s already unprotected\n", core->name))
552 return; 553 return;
553 554
554 if (--core->protect_count > 0) 555 if (--core->protect_count > 0)
@@ -681,16 +682,18 @@ static void clk_core_unprepare(struct clk_core *core)
681 if (!core) 682 if (!core)
682 return; 683 return;
683 684
684 if (WARN_ON(core->prepare_count == 0)) 685 if (WARN(core->prepare_count == 0,
686 "%s already unprepared\n", core->name))
685 return; 687 return;
686 688
687 if (WARN_ON(core->prepare_count == 1 && core->flags & CLK_IS_CRITICAL)) 689 if (WARN(core->prepare_count == 1 && core->flags & CLK_IS_CRITICAL,
690 "Unpreparing critical %s\n", core->name))
688 return; 691 return;
689 692
690 if (--core->prepare_count > 0) 693 if (--core->prepare_count > 0)
691 return; 694 return;
692 695
693 WARN_ON(core->enable_count > 0); 696 WARN(core->enable_count > 0, "Unpreparing enabled %s\n", core->name);
694 697
695 trace_clk_unprepare(core); 698 trace_clk_unprepare(core);
696 699
@@ -808,10 +811,11 @@ static void clk_core_disable(struct clk_core *core)
808 if (!core) 811 if (!core)
809 return; 812 return;
810 813
811 if (WARN_ON(core->enable_count == 0)) 814 if (WARN(core->enable_count == 0, "%s already disabled\n", core->name))
812 return; 815 return;
813 816
814 if (WARN_ON(core->enable_count == 1 && core->flags & CLK_IS_CRITICAL)) 817 if (WARN(core->enable_count == 1 && core->flags & CLK_IS_CRITICAL,
818 "Disabling critical %s\n", core->name))
815 return; 819 return;
816 820
817 if (--core->enable_count > 0) 821 if (--core->enable_count > 0)
@@ -866,7 +870,8 @@ static int clk_core_enable(struct clk_core *core)
866 if (!core) 870 if (!core)
867 return 0; 871 return 0;
868 872
869 if (WARN_ON(core->prepare_count == 0)) 873 if (WARN(core->prepare_count == 0,
874 "Enabling unprepared %s\n", core->name))
870 return -ESHUTDOWN; 875 return -ESHUTDOWN;
871 876
872 if (core->enable_count == 0) { 877 if (core->enable_count == 0) {
@@ -2170,7 +2175,6 @@ void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent)
2170bool clk_has_parent(struct clk *clk, struct clk *parent) 2175bool clk_has_parent(struct clk *clk, struct clk *parent)
2171{ 2176{
2172 struct clk_core *core, *parent_core; 2177 struct clk_core *core, *parent_core;
2173 unsigned int i;
2174 2178
2175 /* NULL clocks should be nops, so return success if either is NULL. */ 2179 /* NULL clocks should be nops, so return success if either is NULL. */
2176 if (!clk || !parent) 2180 if (!clk || !parent)
@@ -2183,11 +2187,8 @@ bool clk_has_parent(struct clk *clk, struct clk *parent)
2183 if (core->parent == parent_core) 2187 if (core->parent == parent_core)
2184 return true; 2188 return true;
2185 2189
2186 for (i = 0; i < core->num_parents; i++) 2190 return match_string(core->parent_names, core->num_parents,
2187 if (strcmp(core->parent_names[i], parent_core->name) == 0) 2191 parent_core->name) >= 0;
2188 return true;
2189
2190 return false;
2191} 2192}
2192EXPORT_SYMBOL_GPL(clk_has_parent); 2193EXPORT_SYMBOL_GPL(clk_has_parent);
2193 2194
@@ -2608,81 +2609,31 @@ static int possible_parents_show(struct seq_file *s, void *data)
2608} 2609}
2609DEFINE_SHOW_ATTRIBUTE(possible_parents); 2610DEFINE_SHOW_ATTRIBUTE(possible_parents);
2610 2611
2611static int clk_debug_create_one(struct clk_core *core, struct dentry *pdentry) 2612static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
2612{ 2613{
2613 struct dentry *d; 2614 struct dentry *root;
2614 int ret = -ENOMEM;
2615
2616 if (!core || !pdentry) {
2617 ret = -EINVAL;
2618 goto out;
2619 }
2620
2621 d = debugfs_create_dir(core->name, pdentry);
2622 if (!d)
2623 goto out;
2624 2615
2625 core->dentry = d; 2616 if (!core || !pdentry)
2626 2617 return;
2627 d = debugfs_create_ulong("clk_rate", 0444, core->dentry, &core->rate);
2628 if (!d)
2629 goto err_out;
2630
2631 d = debugfs_create_ulong("clk_accuracy", 0444, core->dentry,
2632 &core->accuracy);
2633 if (!d)
2634 goto err_out;
2635
2636 d = debugfs_create_u32("clk_phase", 0444, core->dentry, &core->phase);
2637 if (!d)
2638 goto err_out;
2639
2640 d = debugfs_create_file("clk_flags", 0444, core->dentry, core,
2641 &clk_flags_fops);
2642 if (!d)
2643 goto err_out;
2644
2645 d = debugfs_create_u32("clk_prepare_count", 0444, core->dentry,
2646 &core->prepare_count);
2647 if (!d)
2648 goto err_out;
2649
2650 d = debugfs_create_u32("clk_enable_count", 0444, core->dentry,
2651 &core->enable_count);
2652 if (!d)
2653 goto err_out;
2654
2655 d = debugfs_create_u32("clk_protect_count", 0444, core->dentry,
2656 &core->protect_count);
2657 if (!d)
2658 goto err_out;
2659
2660 d = debugfs_create_u32("clk_notifier_count", 0444, core->dentry,
2661 &core->notifier_count);
2662 if (!d)
2663 goto err_out;
2664 2618
2665 if (core->num_parents > 1) { 2619 root = debugfs_create_dir(core->name, pdentry);
2666 d = debugfs_create_file("clk_possible_parents", 0444, 2620 core->dentry = root;
2667 core->dentry, core, &possible_parents_fops);
2668 if (!d)
2669 goto err_out;
2670 }
2671 2621
2672 if (core->ops->debug_init) { 2622 debugfs_create_ulong("clk_rate", 0444, root, &core->rate);
2673 ret = core->ops->debug_init(core->hw, core->dentry); 2623 debugfs_create_ulong("clk_accuracy", 0444, root, &core->accuracy);
2674 if (ret) 2624 debugfs_create_u32("clk_phase", 0444, root, &core->phase);
2675 goto err_out; 2625 debugfs_create_file("clk_flags", 0444, root, core, &clk_flags_fops);
2676 } 2626 debugfs_create_u32("clk_prepare_count", 0444, root, &core->prepare_count);
2627 debugfs_create_u32("clk_enable_count", 0444, root, &core->enable_count);
2628 debugfs_create_u32("clk_protect_count", 0444, root, &core->protect_count);
2629 debugfs_create_u32("clk_notifier_count", 0444, root, &core->notifier_count);
2677 2630
2678 ret = 0; 2631 if (core->num_parents > 1)
2679 goto out; 2632 debugfs_create_file("clk_possible_parents", 0444, root, core,
2633 &possible_parents_fops);
2680 2634
2681err_out: 2635 if (core->ops->debug_init)
2682 debugfs_remove_recursive(core->dentry); 2636 core->ops->debug_init(core->hw, core->dentry);
2683 core->dentry = NULL;
2684out:
2685 return ret;
2686} 2637}
2687 2638
2688/** 2639/**
@@ -2693,17 +2644,13 @@ out:
2693 * initialized. Otherwise it bails out early since the debugfs clk directory 2644 * initialized. Otherwise it bails out early since the debugfs clk directory
2694 * will be created lazily by clk_debug_init as part of a late_initcall. 2645 * will be created lazily by clk_debug_init as part of a late_initcall.
2695 */ 2646 */
2696static int clk_debug_register(struct clk_core *core) 2647static void clk_debug_register(struct clk_core *core)
2697{ 2648{
2698 int ret = 0;
2699
2700 mutex_lock(&clk_debug_lock); 2649 mutex_lock(&clk_debug_lock);
2701 hlist_add_head(&core->debug_node, &clk_debug_list); 2650 hlist_add_head(&core->debug_node, &clk_debug_list);
2702 if (inited) 2651 if (inited)
2703 ret = clk_debug_create_one(core, rootdir); 2652 clk_debug_create_one(core, rootdir);
2704 mutex_unlock(&clk_debug_lock); 2653 mutex_unlock(&clk_debug_lock);
2705
2706 return ret;
2707} 2654}
2708 2655
2709 /** 2656 /**
@@ -2723,19 +2670,6 @@ static void clk_debug_unregister(struct clk_core *core)
2723 mutex_unlock(&clk_debug_lock); 2670 mutex_unlock(&clk_debug_lock);
2724} 2671}
2725 2672
2726struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
2727 void *data, const struct file_operations *fops)
2728{
2729 struct dentry *d = NULL;
2730
2731 if (hw->core->dentry)
2732 d = debugfs_create_file(name, mode, hw->core->dentry, data,
2733 fops);
2734
2735 return d;
2736}
2737EXPORT_SYMBOL_GPL(clk_debugfs_add_file);
2738
2739/** 2673/**
2740 * clk_debug_init - lazily populate the debugfs clk directory 2674 * clk_debug_init - lazily populate the debugfs clk directory
2741 * 2675 *
@@ -2748,32 +2682,17 @@ EXPORT_SYMBOL_GPL(clk_debugfs_add_file);
2748static int __init clk_debug_init(void) 2682static int __init clk_debug_init(void)
2749{ 2683{
2750 struct clk_core *core; 2684 struct clk_core *core;
2751 struct dentry *d;
2752 2685
2753 rootdir = debugfs_create_dir("clk", NULL); 2686 rootdir = debugfs_create_dir("clk", NULL);
2754 2687
2755 if (!rootdir) 2688 debugfs_create_file("clk_summary", 0444, rootdir, &all_lists,
2756 return -ENOMEM; 2689 &clk_summary_fops);
2757 2690 debugfs_create_file("clk_dump", 0444, rootdir, &all_lists,
2758 d = debugfs_create_file("clk_summary", 0444, rootdir, &all_lists, 2691 &clk_dump_fops);
2759 &clk_summary_fops); 2692 debugfs_create_file("clk_orphan_summary", 0444, rootdir, &orphan_list,
2760 if (!d) 2693 &clk_summary_fops);
2761 return -ENOMEM; 2694 debugfs_create_file("clk_orphan_dump", 0444, rootdir, &orphan_list,
2762 2695 &clk_dump_fops);
2763 d = debugfs_create_file("clk_dump", 0444, rootdir, &all_lists,
2764 &clk_dump_fops);
2765 if (!d)
2766 return -ENOMEM;
2767
2768 d = debugfs_create_file("clk_orphan_summary", 0444, rootdir,
2769 &orphan_list, &clk_summary_fops);
2770 if (!d)
2771 return -ENOMEM;
2772
2773 d = debugfs_create_file("clk_orphan_dump", 0444, rootdir,
2774 &orphan_list, &clk_dump_fops);
2775 if (!d)
2776 return -ENOMEM;
2777 2696
2778 mutex_lock(&clk_debug_lock); 2697 mutex_lock(&clk_debug_lock);
2779 hlist_for_each_entry(core, &clk_debug_list, debug_node) 2698 hlist_for_each_entry(core, &clk_debug_list, debug_node)
@@ -2786,7 +2705,7 @@ static int __init clk_debug_init(void)
2786} 2705}
2787late_initcall(clk_debug_init); 2706late_initcall(clk_debug_init);
2788#else 2707#else
2789static inline int clk_debug_register(struct clk_core *core) { return 0; } 2708static inline void clk_debug_register(struct clk_core *core) { }
2790static inline void clk_debug_reparent(struct clk_core *core, 2709static inline void clk_debug_reparent(struct clk_core *core,
2791 struct clk_core *new_parent) 2710 struct clk_core *new_parent)
2792{ 2711{
@@ -3906,7 +3825,7 @@ int of_clk_parent_fill(struct device_node *np, const char **parents,
3906EXPORT_SYMBOL_GPL(of_clk_parent_fill); 3825EXPORT_SYMBOL_GPL(of_clk_parent_fill);
3907 3826
3908struct clock_provider { 3827struct clock_provider {
3909 of_clk_init_cb_t clk_init_cb; 3828 void (*clk_init_cb)(struct device_node *);
3910 struct device_node *np; 3829 struct device_node *np;
3911 struct list_head node; 3830 struct list_head node;
3912}; 3831};
diff --git a/drivers/clk/davinci/pll.c b/drivers/clk/davinci/pll.c
index 65abd371692d..1c99e992d638 100644
--- a/drivers/clk/davinci/pll.c
+++ b/drivers/clk/davinci/pll.c
@@ -191,7 +191,7 @@ static int davinci_pll_set_rate(struct clk_hw *hw, unsigned long rate,
191} 191}
192 192
193#ifdef CONFIG_DEBUG_FS 193#ifdef CONFIG_DEBUG_FS
194static int davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry); 194static void davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry);
195#else 195#else
196#define davinci_pll_debug_init NULL 196#define davinci_pll_debug_init NULL
197#endif 197#endif
@@ -989,26 +989,19 @@ static const struct debugfs_reg32 davinci_pll_regs[] = {
989 DEBUG_REG(PLLDIV9), 989 DEBUG_REG(PLLDIV9),
990}; 990};
991 991
992static int davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry) 992static void davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
993{ 993{
994 struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); 994 struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
995 struct debugfs_regset32 *regset; 995 struct debugfs_regset32 *regset;
996 struct dentry *d;
997 996
998 regset = kzalloc(sizeof(*regset), GFP_KERNEL); 997 regset = kzalloc(sizeof(*regset), GFP_KERNEL);
999 if (!regset) 998 if (!regset)
1000 return -ENOMEM; 999 return;
1001 1000
1002 regset->regs = davinci_pll_regs; 1001 regset->regs = davinci_pll_regs;
1003 regset->nregs = ARRAY_SIZE(davinci_pll_regs); 1002 regset->nregs = ARRAY_SIZE(davinci_pll_regs);
1004 regset->base = pll->base; 1003 regset->base = pll->base;
1005 1004
1006 d = debugfs_create_regset32("registers", 0400, dentry, regset); 1005 debugfs_create_regset32("registers", 0400, dentry, regset);
1007 if (IS_ERR(d)) {
1008 kfree(regset);
1009 return PTR_ERR(d);
1010 }
1011
1012 return 0;
1013} 1006}
1014#endif 1007#endif
diff --git a/drivers/clk/davinci/psc-da830.c b/drivers/clk/davinci/psc-da830.c
index f61abf5632ff..081b039fcb02 100644
--- a/drivers/clk/davinci/psc-da830.c
+++ b/drivers/clk/davinci/psc-da830.c
@@ -55,7 +55,8 @@ const struct davinci_psc_init_data da830_psc0_init_data = {
55 .psc_init = &da830_psc0_init, 55 .psc_init = &da830_psc0_init,
56}; 56};
57 57
58LPSC_CLKDEV2(usb0_clkdev, NULL, "musb-da8xx", 58LPSC_CLKDEV3(usb0_clkdev, "fck", "da830-usb-phy-clks",
59 NULL, "musb-da8xx",
59 NULL, "cppi41-dmaengine"); 60 NULL, "cppi41-dmaengine");
60LPSC_CLKDEV1(usb1_clkdev, NULL, "ohci-da8xx"); 61LPSC_CLKDEV1(usb1_clkdev, NULL, "ohci-da8xx");
61/* REVISIT: gpio-davinci.c should be modified to drop con_id */ 62/* REVISIT: gpio-davinci.c should be modified to drop con_id */
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
index 1bd43550e4c8..becdb1dd21b5 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -44,14 +44,17 @@ config RESET_HISI
44 Build reset controller driver for HiSilicon device chipsets. 44 Build reset controller driver for HiSilicon device chipsets.
45 45
46config STUB_CLK_HI6220 46config STUB_CLK_HI6220
47 bool "Hi6220 Stub Clock Driver" 47 bool "Hi6220 Stub Clock Driver" if EXPERT
48 depends on COMMON_CLK_HI6220 && MAILBOX 48 depends on (COMMON_CLK_HI6220 || COMPILE_TEST)
49 default ARCH_HISI 49 depends on MAILBOX
50 default COMMON_CLK_HI6220
50 help 51 help
51 Build the Hisilicon Hi6220 stub clock driver. 52 Build the Hisilicon Hi6220 stub clock driver.
52 53
53config STUB_CLK_HI3660 54config STUB_CLK_HI3660
54 bool "Hi3660 Stub Clock Driver" 55 bool "Hi3660 Stub Clock Driver" if EXPERT
55 depends on COMMON_CLK_HI3660 && MAILBOX 56 depends on (COMMON_CLK_HI3660 || COMPILE_TEST)
57 depends on MAILBOX
58 default COMMON_CLK_HI3660
56 help 59 help
57 Build the Hisilicon Hi3660 stub clock driver. 60 Build the Hisilicon Hi3660 stub clock driver.
diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c
index 743eec131528..4fe0b2a9baf1 100644
--- a/drivers/clk/hisilicon/crg-hi3798cv200.c
+++ b/drivers/clk/hisilicon/crg-hi3798cv200.c
@@ -186,6 +186,23 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
186 CLK_SET_RATE_PARENT, 0xbc, 0, 0 }, 186 CLK_SET_RATE_PARENT, 0xbc, 0, 0 },
187 { HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m", 187 { HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m",
188 CLK_SET_RATE_PARENT, 0xbc, 2, 0 }, 188 CLK_SET_RATE_PARENT, 0xbc, 2, 0 },
189 /* USB3 */
190 { HISTB_USB3_BUS_CLK, "clk_u3_bus", NULL,
191 CLK_SET_RATE_PARENT, 0xb0, 0, 0 },
192 { HISTB_USB3_UTMI_CLK, "clk_u3_utmi", NULL,
193 CLK_SET_RATE_PARENT, 0xb0, 4, 0 },
194 { HISTB_USB3_PIPE_CLK, "clk_u3_pipe", NULL,
195 CLK_SET_RATE_PARENT, 0xb0, 3, 0 },
196 { HISTB_USB3_SUSPEND_CLK, "clk_u3_suspend", NULL,
197 CLK_SET_RATE_PARENT, 0xb0, 2, 0 },
198 { HISTB_USB3_BUS_CLK1, "clk_u3_bus1", NULL,
199 CLK_SET_RATE_PARENT, 0xb0, 16, 0 },
200 { HISTB_USB3_UTMI_CLK1, "clk_u3_utmi1", NULL,
201 CLK_SET_RATE_PARENT, 0xb0, 20, 0 },
202 { HISTB_USB3_PIPE_CLK1, "clk_u3_pipe1", NULL,
203 CLK_SET_RATE_PARENT, 0xb0, 19, 0 },
204 { HISTB_USB3_SUSPEND_CLK1, "clk_u3_suspend1", NULL,
205 CLK_SET_RATE_PARENT, 0xb0, 18, 0 },
189}; 206};
190 207
191static struct hisi_clock_data *hi3798cv200_clk_register( 208static struct hisi_clock_data *hi3798cv200_clk_register(
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index 8d518ad5dc13..b9ea7037e193 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -753,6 +753,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
753 else 753 else
754 clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); 754 clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
755 clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); 755 clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
756 clk[IMX6QDL_CLK_EPIT1] = imx_clk_gate2("epit1", "ipg", base + 0x6c, 12);
757 clk[IMX6QDL_CLK_EPIT2] = imx_clk_gate2("epit2", "ipg", base + 0x6c, 14);
756 clk[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai); 758 clk[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai);
757 clk[IMX6QDL_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai); 759 clk[IMX6QDL_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai);
758 clk[IMX6QDL_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai); 760 clk[IMX6QDL_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai);
diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c
index 9642cdf0fb88..66b1dd1cfad0 100644
--- a/drivers/clk/imx/clk-imx6sl.c
+++ b/drivers/clk/imx/clk-imx6sl.c
@@ -330,7 +330,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
330 clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); 330 clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
331 331
332 /* name parent_name reg shift width */ 332 /* name parent_name reg shift width */
333 clks[IMX6SL_CLK_OCRAM_PODF] = imx_clk_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3); 333 clks[IMX6SL_CLK_OCRAM_PODF] = imx_clk_busy_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3, base + 0x48, 0);
334 clks[IMX6SL_CLK_PERIPH_CLK2_PODF] = imx_clk_divider("periph_clk2_podf", "periph_clk2_sel", base + 0x14, 27, 3); 334 clks[IMX6SL_CLK_PERIPH_CLK2_PODF] = imx_clk_divider("periph_clk2_podf", "periph_clk2_sel", base + 0x14, 27, 3);
335 clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel", base + 0x14, 0, 3); 335 clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel", base + 0x14, 0, 3);
336 clks[IMX6SL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); 336 clks[IMX6SL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c
index bc3f9ebf2d9e..10c771b91ef6 100644
--- a/drivers/clk/imx/clk-imx6sx.c
+++ b/drivers/clk/imx/clk-imx6sx.c
@@ -80,7 +80,7 @@ static const char *lvds_sels[] = {
80 "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div", 80 "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div",
81 "dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2", 81 "dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2",
82}; 82};
83static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", }; 83static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };
84static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", }; 84static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
85static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", }; 85static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
86static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", }; 86static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
@@ -97,12 +97,7 @@ static int const clks_init_on[] __initconst = {
97 IMX6SX_CLK_IPMUX1, IMX6SX_CLK_IPMUX2, IMX6SX_CLK_IPMUX3, 97 IMX6SX_CLK_IPMUX1, IMX6SX_CLK_IPMUX2, IMX6SX_CLK_IPMUX3,
98 IMX6SX_CLK_WAKEUP, IMX6SX_CLK_MMDC_P0_FAST, IMX6SX_CLK_MMDC_P0_IPG, 98 IMX6SX_CLK_WAKEUP, IMX6SX_CLK_MMDC_P0_FAST, IMX6SX_CLK_MMDC_P0_IPG,
99 IMX6SX_CLK_ROM, IMX6SX_CLK_ARM, IMX6SX_CLK_IPG, IMX6SX_CLK_OCRAM, 99 IMX6SX_CLK_ROM, IMX6SX_CLK_ARM, IMX6SX_CLK_IPG, IMX6SX_CLK_OCRAM,
100 IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK, IMX6SX_CLK_M4, 100 IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK, IMX6SX_CLK_TZASC1,
101 IMX6SX_CLK_QSPI1, IMX6SX_CLK_QSPI2, IMX6SX_CLK_UART_IPG,
102 IMX6SX_CLK_UART_SERIAL, IMX6SX_CLK_I2C3, IMX6SX_CLK_ECSPI5,
103 IMX6SX_CLK_CAN1_IPG, IMX6SX_CLK_CAN1_SERIAL, IMX6SX_CLK_CAN2_IPG,
104 IMX6SX_CLK_CAN2_SERIAL, IMX6SX_CLK_CANFD, IMX6SX_CLK_EPIT1,
105 IMX6SX_CLK_EPIT2,
106}; 101};
107 102
108static const struct clk_div_table clk_enet_ref_table[] = { 103static const struct clk_div_table clk_enet_ref_table[] = {
@@ -158,8 +153,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
158 clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0"); 153 clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0");
159 clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1"); 154 clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1");
160 155
161 /* Clock source from external clock via CLK1 PAD */ 156 /* Clock source from external clock via CLK1/2 PAD */
162 clks[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0); 157 clks[IMX6SX_CLK_ANACLK1] = of_clk_get_by_name(ccm_node, "anaclk1");
158 clks[IMX6SX_CLK_ANACLK2] = of_clk_get_by_name(ccm_node, "anaclk2");
163 159
164 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop"); 160 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");
165 base = of_iomap(np, 0); 161 base = of_iomap(np, 0);
@@ -228,7 +224,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
228 clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); 224 clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
229 225
230 clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12)); 226 clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12));
227 clks[IMX6SX_CLK_LVDS2_OUT] = imx_clk_gate_exclusive("lvds2_out", "lvds2_sel", base + 0x160, 11, BIT(13));
231 clks[IMX6SX_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10)); 228 clks[IMX6SX_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
229 clks[IMX6SX_CLK_LVDS2_IN] = imx_clk_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11));
232 230
233 clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, 231 clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
234 base + 0xe0, 0, 2, 0, clk_enet_ref_table, 232 base + 0xe0, 0, 2, 0, clk_enet_ref_table,
@@ -270,6 +268,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
270 268
271 /* name reg shift width parent_names num_parents */ 269 /* name reg shift width parent_names num_parents */
272 clks[IMX6SX_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); 270 clks[IMX6SX_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
271 clks[IMX6SX_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
273 272
274 np = ccm_node; 273 np = ccm_node;
275 base = of_iomap(np, 0); 274 base = of_iomap(np, 0);
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index 114ecbb94ec5..9bfef1acee63 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -68,6 +68,13 @@ static const char *sim_sels[] = { "sim_podf", "ipp_di0", "ipp_di1", "ldb_di0", "
68static const char *epdc_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", }; 68static const char *epdc_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
69static const char *esai_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", }; 69static const char *esai_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
70static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; 70static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
71static const char *cko1_sels[] = { "dummy", "dummy", "dummy", "dummy", "dummy", "axi", "enfc", "dummy", "dummy",
72 "dummy", "lcdif_pix", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
73static const char *cko2_sels[] = { "dummy", "dummy", "dummy", "usdhc1", "dummy", "dummy", "ecspi_root", "dummy",
74 "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "osc", "dummy",
75 "dummy", "usdhc2", "sai1", "sai2", "sai3", "dummy", "dummy", "can_root",
76 "dummy", "dummy", "dummy", "dummy", "uart_serial", "spdif", "dummy", "dummy", };
77static const char *cko_sels[] = { "cko1", "cko2", };
71 78
72static struct clk *clks[IMX6UL_CLK_END]; 79static struct clk *clks[IMX6UL_CLK_END];
73static struct clk_onecell_data clk_data; 80static struct clk_onecell_data clk_data;
@@ -273,6 +280,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
273 clks[IMX6UL_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux("ldb_di0", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels)); 280 clks[IMX6UL_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux("ldb_di0", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels));
274 clks[IMX6UL_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux("ldb_di1", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels)); 281 clks[IMX6UL_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux("ldb_di1", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels));
275 282
283 clks[IMX6UL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
284 clks[IMX6UL_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
285 clks[IMX6UL_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
286
276 clks[IMX6UL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); 287 clks[IMX6UL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
277 clks[IMX6UL_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7); 288 clks[IMX6UL_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7);
278 clks[IMX6UL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "qspi1_sel", 2, 7); 289 clks[IMX6UL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "qspi1_sel", 2, 7);
@@ -316,6 +327,9 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
316 clks[IMX6UL_CLK_LCDIF_PRED] = imx_clk_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3); 327 clks[IMX6UL_CLK_LCDIF_PRED] = imx_clk_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3);
317 clks[IMX6UL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3); 328 clks[IMX6UL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3);
318 329
330 clks[IMX6UL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
331 clks[IMX6UL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
332
319 clks[IMX6UL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); 333 clks[IMX6UL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
320 clks[IMX6UL_CLK_MMDC_PODF] = imx_clk_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); 334 clks[IMX6UL_CLK_MMDC_PODF] = imx_clk_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
321 clks[IMX6UL_CLK_AXI_PODF] = imx_clk_busy_divider("axi_podf", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); 335 clks[IMX6UL_CLK_AXI_PODF] = imx_clk_busy_divider("axi_podf", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
@@ -445,6 +459,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
445 clks[IMX6UL_CLK_PWM6] = imx_clk_gate2("pwm6", "perclk", base + 0x80, 28); 459 clks[IMX6UL_CLK_PWM6] = imx_clk_gate2("pwm6", "perclk", base + 0x80, 28);
446 clks[IMX6UL_CLK_PWM7] = imx_clk_gate2("pwm7", "perclk", base + 0x80, 30); 460 clks[IMX6UL_CLK_PWM7] = imx_clk_gate2("pwm7", "perclk", base + 0x80, 30);
447 461
462 /* CCOSR */
463 clks[IMX6UL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
464 clks[IMX6UL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
465
448 /* mask handshake of mmdc */ 466 /* mask handshake of mmdc */
449 writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR); 467 writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
450 468
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 975a20d3cc94..27217a7ea17e 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -26,6 +26,8 @@ static u32 share_count_sai1;
26static u32 share_count_sai2; 26static u32 share_count_sai2;
27static u32 share_count_sai3; 27static u32 share_count_sai3;
28static u32 share_count_nand; 28static u32 share_count_nand;
29static u32 share_count_enet1;
30static u32 share_count_enet2;
29 31
30static const struct clk_div_table test_div_table[] = { 32static const struct clk_div_table test_div_table[] = {
31 { .val = 3, .div = 1, }, 33 { .val = 3, .div = 1, },
@@ -729,7 +731,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
729 clks[IMX7D_LCDIF_PIXEL_ROOT_DIV] = imx_clk_divider2("lcdif_pixel_post_div", "lcdif_pixel_pre_div", base + 0xa300, 0, 6); 731 clks[IMX7D_LCDIF_PIXEL_ROOT_DIV] = imx_clk_divider2("lcdif_pixel_post_div", "lcdif_pixel_pre_div", base + 0xa300, 0, 6);
730 clks[IMX7D_MIPI_DSI_ROOT_DIV] = imx_clk_divider2("mipi_dsi_post_div", "mipi_dsi_pre_div", base + 0xa380, 0, 6); 732 clks[IMX7D_MIPI_DSI_ROOT_DIV] = imx_clk_divider2("mipi_dsi_post_div", "mipi_dsi_pre_div", base + 0xa380, 0, 6);
731 clks[IMX7D_MIPI_CSI_ROOT_DIV] = imx_clk_divider2("mipi_csi_post_div", "mipi_csi_pre_div", base + 0xa400, 0, 6); 733 clks[IMX7D_MIPI_CSI_ROOT_DIV] = imx_clk_divider2("mipi_csi_post_div", "mipi_csi_pre_div", base + 0xa400, 0, 6);
732 clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider2("mipi_dphy_post_div", "mipi_csi_dphy_div", base + 0xa480, 0, 6); 734 clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider2("mipi_dphy_post_div", "mipi_dphy_pre_div", base + 0xa480, 0, 6);
733 clks[IMX7D_SAI1_ROOT_DIV] = imx_clk_divider2("sai1_post_div", "sai1_pre_div", base + 0xa500, 0, 6); 735 clks[IMX7D_SAI1_ROOT_DIV] = imx_clk_divider2("sai1_post_div", "sai1_pre_div", base + 0xa500, 0, 6);
734 clks[IMX7D_SAI2_ROOT_DIV] = imx_clk_divider2("sai2_post_div", "sai2_pre_div", base + 0xa580, 0, 6); 736 clks[IMX7D_SAI2_ROOT_DIV] = imx_clk_divider2("sai2_post_div", "sai2_pre_div", base + 0xa580, 0, 6);
735 clks[IMX7D_SAI3_ROOT_DIV] = imx_clk_divider2("sai3_post_div", "sai3_pre_div", base + 0xa600, 0, 6); 737 clks[IMX7D_SAI3_ROOT_DIV] = imx_clk_divider2("sai3_post_div", "sai3_pre_div", base + 0xa600, 0, 6);
@@ -738,7 +740,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
738 clks[IMX7D_ENET1_TIME_ROOT_DIV] = imx_clk_divider2("enet1_time_post_div", "enet1_time_pre_div", base + 0xa780, 0, 6); 740 clks[IMX7D_ENET1_TIME_ROOT_DIV] = imx_clk_divider2("enet1_time_post_div", "enet1_time_pre_div", base + 0xa780, 0, 6);
739 clks[IMX7D_ENET2_REF_ROOT_DIV] = imx_clk_divider2("enet2_ref_post_div", "enet2_ref_pre_div", base + 0xa800, 0, 6); 741 clks[IMX7D_ENET2_REF_ROOT_DIV] = imx_clk_divider2("enet2_ref_post_div", "enet2_ref_pre_div", base + 0xa800, 0, 6);
740 clks[IMX7D_ENET2_TIME_ROOT_DIV] = imx_clk_divider2("enet2_time_post_div", "enet2_time_pre_div", base + 0xa880, 0, 6); 742 clks[IMX7D_ENET2_TIME_ROOT_DIV] = imx_clk_divider2("enet2_time_post_div", "enet2_time_pre_div", base + 0xa880, 0, 6);
741 clks[IMX7D_ENET_PHY_REF_ROOT_DIV] = imx_clk_divider2("enet_phy_ref_post_div", "enet_phy_ref_pre_div", base + 0xa900, 0, 6); 743 clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_divider2("enet_phy_ref_root_clk", "enet_phy_ref_pre_div", base + 0xa900, 0, 6);
742 clks[IMX7D_EIM_ROOT_DIV] = imx_clk_divider2("eim_post_div", "eim_pre_div", base + 0xa980, 0, 6); 744 clks[IMX7D_EIM_ROOT_DIV] = imx_clk_divider2("eim_post_div", "eim_pre_div", base + 0xa980, 0, 6);
743 clks[IMX7D_NAND_ROOT_CLK] = imx_clk_divider2("nand_root_clk", "nand_pre_div", base + 0xaa00, 0, 6); 745 clks[IMX7D_NAND_ROOT_CLK] = imx_clk_divider2("nand_root_clk", "nand_pre_div", base + 0xaa00, 0, 6);
744 clks[IMX7D_QSPI_ROOT_DIV] = imx_clk_divider2("qspi_post_div", "qspi_pre_div", base + 0xaa80, 0, 6); 746 clks[IMX7D_QSPI_ROOT_DIV] = imx_clk_divider2("qspi_post_div", "qspi_pre_div", base + 0xaa80, 0, 6);
@@ -805,6 +807,10 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
805 clks[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_gate4("mipi_dsi_root_clk", "mipi_dsi_post_div", base + 0x4650, 0); 807 clks[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_gate4("mipi_dsi_root_clk", "mipi_dsi_post_div", base + 0x4650, 0);
806 clks[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_gate4("mipi_csi_root_clk", "mipi_csi_post_div", base + 0x4640, 0); 808 clks[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_gate4("mipi_csi_root_clk", "mipi_csi_post_div", base + 0x4640, 0);
807 clks[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_gate4("mipi_dphy_root_clk", "mipi_dphy_post_div", base + 0x4660, 0); 809 clks[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_gate4("mipi_dphy_root_clk", "mipi_dphy_post_div", base + 0x4660, 0);
810 clks[IMX7D_ENET1_IPG_ROOT_CLK] = imx_clk_gate2_shared2("enet1_ipg_root_clk", "enet_axi_post_div", base + 0x4700, 0, &share_count_enet1);
811 clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate2_shared2("enet1_time_root_clk", "enet1_time_post_div", base + 0x4700, 0, &share_count_enet1);
812 clks[IMX7D_ENET2_IPG_ROOT_CLK] = imx_clk_gate2_shared2("enet2_ipg_root_clk", "enet_axi_post_div", base + 0x4710, 0, &share_count_enet2);
813 clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate2_shared2("enet2_time_root_clk", "enet2_time_post_div", base + 0x4710, 0, &share_count_enet2);
808 clks[IMX7D_SAI1_ROOT_CLK] = imx_clk_gate2_shared2("sai1_root_clk", "sai1_post_div", base + 0x48c0, 0, &share_count_sai1); 814 clks[IMX7D_SAI1_ROOT_CLK] = imx_clk_gate2_shared2("sai1_root_clk", "sai1_post_div", base + 0x48c0, 0, &share_count_sai1);
809 clks[IMX7D_SAI1_IPG_CLK] = imx_clk_gate2_shared2("sai1_ipg_clk", "ipg_root_clk", base + 0x48c0, 0, &share_count_sai1); 815 clks[IMX7D_SAI1_IPG_CLK] = imx_clk_gate2_shared2("sai1_ipg_clk", "ipg_root_clk", base + 0x48c0, 0, &share_count_sai1);
810 clks[IMX7D_SAI2_ROOT_CLK] = imx_clk_gate2_shared2("sai2_root_clk", "sai2_post_div", base + 0x48d0, 0, &share_count_sai2); 816 clks[IMX7D_SAI2_ROOT_CLK] = imx_clk_gate2_shared2("sai2_root_clk", "sai2_post_div", base + 0x48d0, 0, &share_count_sai2);
@@ -812,11 +818,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
812 clks[IMX7D_SAI3_ROOT_CLK] = imx_clk_gate2_shared2("sai3_root_clk", "sai3_post_div", base + 0x48e0, 0, &share_count_sai3); 818 clks[IMX7D_SAI3_ROOT_CLK] = imx_clk_gate2_shared2("sai3_root_clk", "sai3_post_div", base + 0x48e0, 0, &share_count_sai3);
813 clks[IMX7D_SAI3_IPG_CLK] = imx_clk_gate2_shared2("sai3_ipg_clk", "ipg_root_clk", base + 0x48e0, 0, &share_count_sai3); 819 clks[IMX7D_SAI3_IPG_CLK] = imx_clk_gate2_shared2("sai3_ipg_clk", "ipg_root_clk", base + 0x48e0, 0, &share_count_sai3);
814 clks[IMX7D_SPDIF_ROOT_CLK] = imx_clk_gate4("spdif_root_clk", "spdif_post_div", base + 0x44d0, 0); 820 clks[IMX7D_SPDIF_ROOT_CLK] = imx_clk_gate4("spdif_root_clk", "spdif_post_div", base + 0x44d0, 0);
815 clks[IMX7D_ENET1_REF_ROOT_CLK] = imx_clk_gate4("enet1_ref_root_clk", "enet1_ref_post_div", base + 0x44e0, 0);
816 clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate4("enet1_time_root_clk", "enet1_time_post_div", base + 0x44f0, 0);
817 clks[IMX7D_ENET2_REF_ROOT_CLK] = imx_clk_gate4("enet2_ref_root_clk", "enet2_ref_post_div", base + 0x4500, 0);
818 clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate4("enet2_time_root_clk", "enet2_time_post_div", base + 0x4510, 0);
819 clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_gate4("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base + 0x4520, 0);
820 clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk", "eim_post_div", base + 0x4160, 0); 821 clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk", "eim_post_div", base + 0x4160, 0);
821 clks[IMX7D_NAND_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_rawnand_clk", "nand_root_clk", base + 0x4140, 0, &share_count_nand); 822 clks[IMX7D_NAND_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_rawnand_clk", "nand_root_clk", base + 0x4140, 0, &share_count_nand);
822 clks[IMX7D_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_root_clk", base + 0x4140, 0, &share_count_nand); 823 clks[IMX7D_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_root_clk", base + 0x4140, 0, &share_count_nand);
@@ -891,6 +892,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
891 clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]); 892 clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
892 clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]); 893 clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
893 894
895 clk_set_parent(clks[IMX7D_MIPI_CSI_ROOT_SRC], clks[IMX7D_PLL_SYS_PFD3_CLK]);
896
894 /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */ 897 /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
895 clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]); 898 clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
896 899
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index 56a712c9075f..5ef7d9ba2195 100644
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -43,7 +43,8 @@ static inline bool
43ingenic_cgu_gate_get(struct ingenic_cgu *cgu, 43ingenic_cgu_gate_get(struct ingenic_cgu *cgu,
44 const struct ingenic_cgu_gate_info *info) 44 const struct ingenic_cgu_gate_info *info)
45{ 45{
46 return readl(cgu->base + info->reg) & BIT(info->bit); 46 return !!(readl(cgu->base + info->reg) & BIT(info->bit))
47 ^ info->clear_to_gate;
47} 48}
48 49
49/** 50/**
@@ -62,7 +63,7 @@ ingenic_cgu_gate_set(struct ingenic_cgu *cgu,
62{ 63{
63 u32 clkgr = readl(cgu->base + info->reg); 64 u32 clkgr = readl(cgu->base + info->reg);
64 65
65 if (val) 66 if (val ^ info->clear_to_gate)
66 clkgr |= BIT(info->bit); 67 clkgr |= BIT(info->bit);
67 else 68 else
68 clkgr &= ~BIT(info->bit); 69 clkgr &= ~BIT(info->bit);
@@ -511,6 +512,9 @@ static int ingenic_clk_enable(struct clk_hw *hw)
511 spin_lock_irqsave(&cgu->lock, flags); 512 spin_lock_irqsave(&cgu->lock, flags);
512 ingenic_cgu_gate_set(cgu, &clk_info->gate, false); 513 ingenic_cgu_gate_set(cgu, &clk_info->gate, false);
513 spin_unlock_irqrestore(&cgu->lock, flags); 514 spin_unlock_irqrestore(&cgu->lock, flags);
515
516 if (clk_info->gate.delay_us)
517 udelay(clk_info->gate.delay_us);
514 } 518 }
515 519
516 return 0; 520 return 0;
diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h
index 9da34910bd80..542192376ebf 100644
--- a/drivers/clk/ingenic/cgu.h
+++ b/drivers/clk/ingenic/cgu.h
@@ -111,10 +111,14 @@ struct ingenic_cgu_fixdiv_info {
111 * struct ingenic_cgu_gate_info - information about a clock gate 111 * struct ingenic_cgu_gate_info - information about a clock gate
112 * @reg: offset of the gate control register within the CGU 112 * @reg: offset of the gate control register within the CGU
113 * @bit: offset of the bit in the register that controls the gate 113 * @bit: offset of the bit in the register that controls the gate
114 * @clear_to_gate: if set, the clock is gated when the bit is cleared
115 * @delay_us: delay in microseconds after which the clock is considered stable
114 */ 116 */
115struct ingenic_cgu_gate_info { 117struct ingenic_cgu_gate_info {
116 unsigned reg; 118 unsigned reg;
117 u8 bit; 119 u8 bit;
120 bool clear_to_gate;
121 u16 delay_us;
118}; 122};
119 123
120/** 124/**
diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c
index c78d369b9403..bf46a0df2004 100644
--- a/drivers/clk/ingenic/jz4770-cgu.c
+++ b/drivers/clk/ingenic/jz4770-cgu.c
@@ -42,7 +42,6 @@
42 42
43/* bits within the OPCR register */ 43/* bits within the OPCR register */
44#define OPCR_SPENDH BIT(5) /* UHC PHY suspend */ 44#define OPCR_SPENDH BIT(5) /* UHC PHY suspend */
45#define OPCR_SPENDN BIT(7) /* OTG PHY suspend */
46 45
47/* bits within the USBPCR1 register */ 46/* bits within the USBPCR1 register */
48#define USBPCR1_UHC_POWER BIT(5) /* UHC PHY power down */ 47#define USBPCR1_UHC_POWER BIT(5) /* UHC PHY power down */
@@ -83,37 +82,6 @@ static const struct clk_ops jz4770_uhc_phy_ops = {
83 .is_enabled = jz4770_uhc_phy_is_enabled, 82 .is_enabled = jz4770_uhc_phy_is_enabled,
84}; 83};
85 84
86static int jz4770_otg_phy_enable(struct clk_hw *hw)
87{
88 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
89
90 writel(readl(reg_opcr) | OPCR_SPENDN, reg_opcr);
91
92 /* Wait for the clock to be stable */
93 udelay(50);
94 return 0;
95}
96
97static void jz4770_otg_phy_disable(struct clk_hw *hw)
98{
99 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
100
101 writel(readl(reg_opcr) & ~OPCR_SPENDN, reg_opcr);
102}
103
104static int jz4770_otg_phy_is_enabled(struct clk_hw *hw)
105{
106 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
107
108 return !!(readl(reg_opcr) & OPCR_SPENDN);
109}
110
111static const struct clk_ops jz4770_otg_phy_ops = {
112 .enable = jz4770_otg_phy_enable,
113 .disable = jz4770_otg_phy_disable,
114 .is_enabled = jz4770_otg_phy_is_enabled,
115};
116
117static const s8 pll_od_encoding[8] = { 85static const s8 pll_od_encoding[8] = {
118 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3, 86 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
119}; 87};
@@ -186,7 +154,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
186 "h1clk", CGU_CLK_DIV | CGU_CLK_GATE, 154 "h1clk", CGU_CLK_DIV | CGU_CLK_GATE,
187 .parents = { JZ4770_CLK_PLL0, }, 155 .parents = { JZ4770_CLK_PLL0, },
188 .div = { CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1 }, 156 .div = { CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1 },
189 .gate = { CGU_REG_LCR, 30 }, 157 .gate = { CGU_REG_CLKGR1, 7 },
190 }, 158 },
191 [JZ4770_CLK_H2CLK] = { 159 [JZ4770_CLK_H2CLK] = {
192 "h2clk", CGU_CLK_DIV, 160 "h2clk", CGU_CLK_DIV,
@@ -194,9 +162,10 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
194 .div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1 }, 162 .div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1 },
195 }, 163 },
196 [JZ4770_CLK_C1CLK] = { 164 [JZ4770_CLK_C1CLK] = {
197 "c1clk", CGU_CLK_DIV, 165 "c1clk", CGU_CLK_DIV | CGU_CLK_GATE,
198 .parents = { JZ4770_CLK_PLL0, }, 166 .parents = { JZ4770_CLK_PLL0, },
199 .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1 }, 167 .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1 },
168 .gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle
200 }, 169 },
201 [JZ4770_CLK_PCLK] = { 170 [JZ4770_CLK_PCLK] = {
202 "pclk", CGU_CLK_DIV, 171 "pclk", CGU_CLK_DIV,
@@ -393,7 +362,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
393 [JZ4770_CLK_VPU] = { 362 [JZ4770_CLK_VPU] = {
394 "vpu", CGU_CLK_GATE, 363 "vpu", CGU_CLK_GATE,
395 .parents = { JZ4770_CLK_H1CLK, }, 364 .parents = { JZ4770_CLK_H1CLK, },
396 .gate = { CGU_REG_CLKGR1, 7 }, 365 .gate = { CGU_REG_LCR, 30, false, 150 },
397 }, 366 },
398 [JZ4770_CLK_MMC0] = { 367 [JZ4770_CLK_MMC0] = {
399 "mmc0", CGU_CLK_GATE, 368 "mmc0", CGU_CLK_GATE,
@@ -410,6 +379,11 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
410 .parents = { JZ4770_CLK_MMC2_MUX, }, 379 .parents = { JZ4770_CLK_MMC2_MUX, },
411 .gate = { CGU_REG_CLKGR0, 12 }, 380 .gate = { CGU_REG_CLKGR0, 12 },
412 }, 381 },
382 [JZ4770_CLK_OTG_PHY] = {
383 "usb_phy", CGU_CLK_GATE,
384 .parents = { JZ4770_CLK_OTG },
385 .gate = { CGU_REG_OPCR, 7, true, 50 },
386 },
413 387
414 /* Custom clocks */ 388 /* Custom clocks */
415 389
@@ -418,11 +392,6 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
418 .parents = { JZ4770_CLK_UHC, -1, -1, -1 }, 392 .parents = { JZ4770_CLK_UHC, -1, -1, -1 },
419 .custom = { &jz4770_uhc_phy_ops }, 393 .custom = { &jz4770_uhc_phy_ops },
420 }, 394 },
421 [JZ4770_CLK_OTG_PHY] = {
422 "usb_phy", CGU_CLK_CUSTOM,
423 .parents = { JZ4770_CLK_OTG, -1, -1, -1 },
424 .custom = { &jz4770_otg_phy_ops },
425 },
426 395
427 [JZ4770_CLK_EXT512] = { 396 [JZ4770_CLK_EXT512] = {
428 "ext/512", CGU_CLK_FIXDIV, 397 "ext/512", CGU_CLK_FIXDIV,
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 92afe5989e97..3dd1dab92223 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -60,6 +60,12 @@ config COMMON_CLK_MT2701_AUDSYS
60 ---help--- 60 ---help---
61 This driver supports Mediatek MT2701 audsys clocks. 61 This driver supports Mediatek MT2701 audsys clocks.
62 62
63config COMMON_CLK_MT2701_G3DSYS
64 bool "Clock driver for MediaTek MT2701 g3dsys"
65 depends on COMMON_CLK_MT2701
66 ---help---
67 This driver supports MediaTek MT2701 g3dsys clocks.
68
63config COMMON_CLK_MT2712 69config COMMON_CLK_MT2712
64 bool "Clock driver for MediaTek MT2712" 70 bool "Clock driver for MediaTek MT2712"
65 depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST 71 depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index b80eff2abb31..844b55d2770d 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
9obj-$(CONFIG_COMMON_CLK_MT2701_AUDSYS) += clk-mt2701-aud.o 9obj-$(CONFIG_COMMON_CLK_MT2701_AUDSYS) += clk-mt2701-aud.o
10obj-$(CONFIG_COMMON_CLK_MT2701_BDPSYS) += clk-mt2701-bdp.o 10obj-$(CONFIG_COMMON_CLK_MT2701_BDPSYS) += clk-mt2701-bdp.o
11obj-$(CONFIG_COMMON_CLK_MT2701_ETHSYS) += clk-mt2701-eth.o 11obj-$(CONFIG_COMMON_CLK_MT2701_ETHSYS) += clk-mt2701-eth.o
12obj-$(CONFIG_COMMON_CLK_MT2701_G3DSYS) += clk-mt2701-g3d.o
12obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o 13obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
13obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o 14obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o
14obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o 15obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o
diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c
new file mode 100644
index 000000000000..1328c112a38f
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
@@ -0,0 +1,95 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Sean Wang <sean.wang@mediatek.com>
5 *
6 */
7
8#include <linux/clk-provider.h>
9#include <linux/of.h>
10#include <linux/of_address.h>
11#include <linux/of_device.h>
12#include <linux/platform_device.h>
13
14#include "clk-mtk.h"
15#include "clk-gate.h"
16
17#include <dt-bindings/clock/mt2701-clk.h>
18
19#define GATE_G3D(_id, _name, _parent, _shift) { \
20 .id = _id, \
21 .name = _name, \
22 .parent_name = _parent, \
23 .regs = &g3d_cg_regs, \
24 .shift = _shift, \
25 .ops = &mtk_clk_gate_ops_setclr, \
26 }
27
28static const struct mtk_gate_regs g3d_cg_regs = {
29 .sta_ofs = 0x0,
30 .set_ofs = 0x4,
31 .clr_ofs = 0x8,
32};
33
34static const struct mtk_gate g3d_clks[] = {
35 GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
36};
37
38static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
39{
40 struct clk_onecell_data *clk_data;
41 struct device_node *node = pdev->dev.of_node;
42 int r;
43
44 clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
45
46 mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks),
47 clk_data);
48
49 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
50 if (r)
51 dev_err(&pdev->dev,
52 "could not register clock provider: %s: %d\n",
53 pdev->name, r);
54
55 mtk_register_reset_controller(node, 1, 0xc);
56
57 return r;
58}
59
60static const struct of_device_id of_match_clk_mt2701_g3d[] = {
61 {
62 .compatible = "mediatek,mt2701-g3dsys",
63 .data = clk_mt2701_g3dsys_init,
64 }, {
65 /* sentinel */
66 }
67};
68
69static int clk_mt2701_g3d_probe(struct platform_device *pdev)
70{
71 int (*clk_init)(struct platform_device *);
72 int r;
73
74 clk_init = of_device_get_match_data(&pdev->dev);
75 if (!clk_init)
76 return -EINVAL;
77
78 r = clk_init(pdev);
79 if (r)
80 dev_err(&pdev->dev,
81 "could not register clock provider: %s: %d\n",
82 pdev->name, r);
83
84 return r;
85}
86
87static struct platform_driver clk_mt2701_g3d_drv = {
88 .probe = clk_mt2701_g3d_probe,
89 .driver = {
90 .name = "clk-mt2701-g3d",
91 .of_match_table = of_match_clk_mt2701_g3d,
92 },
93};
94
95builtin_platform_driver(clk_mt2701_g3d_drv);
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index deca7527f92f..4dda8988b2f0 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -46,8 +46,6 @@ static const struct mtk_fixed_clk top_fixed_clks[] = {
46 340 * MHZ), 46 340 * MHZ),
47 FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m", 47 FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m",
48 340 * MHZ), 48 340 * MHZ),
49 FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_dig_cts", "clk26m",
50 300 * MHZ),
51 FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m", 49 FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m",
52 27 * MHZ), 50 27 * MHZ),
53 FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m", 51 FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m",
@@ -977,6 +975,10 @@ static const struct mtk_pll_data apmixed_plls[] = {
977 21, 0x2d0, 4, 0x0, 0x2d4, 0), 975 21, 0x2d0, 4, 0x0, 0x2d4, 0),
978}; 976};
979 977
978static const struct mtk_fixed_factor apmixed_fixed_divs[] = {
979 FACTOR(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", 1, 1),
980};
981
980static int mtk_apmixedsys_init(struct platform_device *pdev) 982static int mtk_apmixedsys_init(struct platform_device *pdev)
981{ 983{
982 struct clk_onecell_data *clk_data; 984 struct clk_onecell_data *clk_data;
@@ -988,6 +990,8 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
988 990
989 mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls), 991 mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls),
990 clk_data); 992 clk_data);
993 mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs),
994 clk_data);
991 995
992 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 996 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
993} 997}
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index d5cbec522aec..815659eebea3 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -3,6 +3,12 @@ config COMMON_CLK_AMLOGIC
3 depends on OF 3 depends on OF
4 depends on ARCH_MESON || COMPILE_TEST 4 depends on ARCH_MESON || COMPILE_TEST
5 5
6config COMMON_CLK_MESON_AO
7 bool
8 depends on OF
9 depends on ARCH_MESON || COMPILE_TEST
10 select COMMON_CLK_REGMAP_MESON
11
6config COMMON_CLK_REGMAP_MESON 12config COMMON_CLK_REGMAP_MESON
7 bool 13 bool
8 select REGMAP 14 select REGMAP
@@ -21,6 +27,7 @@ config COMMON_CLK_GXBB
21 bool 27 bool
22 depends on COMMON_CLK_AMLOGIC 28 depends on COMMON_CLK_AMLOGIC
23 select RESET_CONTROLLER 29 select RESET_CONTROLLER
30 select COMMON_CLK_MESON_AO
24 select COMMON_CLK_REGMAP_MESON 31 select COMMON_CLK_REGMAP_MESON
25 select MFD_SYSCON 32 select MFD_SYSCON
26 help 33 help
@@ -31,6 +38,7 @@ config COMMON_CLK_AXG
31 bool 38 bool
32 depends on COMMON_CLK_AMLOGIC 39 depends on COMMON_CLK_AMLOGIC
33 select RESET_CONTROLLER 40 select RESET_CONTROLLER
41 select COMMON_CLK_MESON_AO
34 select COMMON_CLK_REGMAP_MESON 42 select COMMON_CLK_REGMAP_MESON
35 select MFD_SYSCON 43 select MFD_SYSCON
36 help 44 help
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index ffee82e60b7a..d0d13aeb369a 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -3,7 +3,8 @@
3# 3#
4 4
5obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o 5obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
6obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
6obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o 7obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
7obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o 8obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
8obj-$(CONFIG_COMMON_CLK_AXG) += axg.o 9obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
9obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o 10obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
new file mode 100644
index 000000000000..29e088542387
--- /dev/null
+++ b/drivers/clk/meson/axg-aoclk.c
@@ -0,0 +1,164 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Amlogic Meson-AXG Clock Controller Driver
4 *
5 * Copyright (c) 2016 Baylibre SAS.
6 * Author: Michael Turquette <mturquette@baylibre.com>
7 *
8 * Copyright (c) 2018 Amlogic, inc.
9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
10 */
11#include <linux/clk-provider.h>
12#include <linux/platform_device.h>
13#include <linux/reset-controller.h>
14#include <linux/mfd/syscon.h>
15#include "clk-regmap.h"
16#include "meson-aoclk.h"
17#include "axg-aoclk.h"
18
19#define AXG_AO_GATE(_name, _bit) \
20static struct clk_regmap axg_aoclk_##_name = { \
21 .data = &(struct clk_regmap_gate_data) { \
22 .offset = (AO_RTI_GEN_CNTL_REG0), \
23 .bit_idx = (_bit), \
24 }, \
25 .hw.init = &(struct clk_init_data) { \
26 .name = "axg_ao_" #_name, \
27 .ops = &clk_regmap_gate_ops, \
28 .parent_names = (const char *[]){ "clk81" }, \
29 .num_parents = 1, \
30 .flags = CLK_IGNORE_UNUSED, \
31 }, \
32}
33
34AXG_AO_GATE(remote, 0);
35AXG_AO_GATE(i2c_master, 1);
36AXG_AO_GATE(i2c_slave, 2);
37AXG_AO_GATE(uart1, 3);
38AXG_AO_GATE(uart2, 5);
39AXG_AO_GATE(ir_blaster, 6);
40AXG_AO_GATE(saradc, 7);
41
42static struct clk_regmap axg_aoclk_clk81 = {
43 .data = &(struct clk_regmap_mux_data) {
44 .offset = AO_RTI_PWR_CNTL_REG0,
45 .mask = 0x1,
46 .shift = 8,
47 },
48 .hw.init = &(struct clk_init_data){
49 .name = "axg_ao_clk81",
50 .ops = &clk_regmap_mux_ro_ops,
51 .parent_names = (const char *[]){ "clk81", "ao_alt_xtal"},
52 .num_parents = 2,
53 },
54};
55
56static struct clk_regmap axg_aoclk_saradc_mux = {
57 .data = &(struct clk_regmap_mux_data) {
58 .offset = AO_SAR_CLK,
59 .mask = 0x3,
60 .shift = 9,
61 },
62 .hw.init = &(struct clk_init_data){
63 .name = "axg_ao_saradc_mux",
64 .ops = &clk_regmap_mux_ops,
65 .parent_names = (const char *[]){ "xtal", "axg_ao_clk81" },
66 .num_parents = 2,
67 },
68};
69
70static struct clk_regmap axg_aoclk_saradc_div = {
71 .data = &(struct clk_regmap_div_data) {
72 .offset = AO_SAR_CLK,
73 .shift = 0,
74 .width = 8,
75 },
76 .hw.init = &(struct clk_init_data){
77 .name = "axg_ao_saradc_div",
78 .ops = &clk_regmap_divider_ops,
79 .parent_names = (const char *[]){ "axg_ao_saradc_mux" },
80 .num_parents = 1,
81 .flags = CLK_SET_RATE_PARENT,
82 },
83};
84
85static struct clk_regmap axg_aoclk_saradc_gate = {
86 .data = &(struct clk_regmap_gate_data) {
87 .offset = AO_SAR_CLK,
88 .bit_idx = 8,
89 },
90 .hw.init = &(struct clk_init_data){
91 .name = "axg_ao_saradc_gate",
92 .ops = &clk_regmap_gate_ops,
93 .parent_names = (const char *[]){ "axg_ao_saradc_div" },
94 .num_parents = 1,
95 .flags = CLK_SET_RATE_PARENT,
96 },
97};
98
99static const unsigned int axg_aoclk_reset[] = {
100 [RESET_AO_REMOTE] = 16,
101 [RESET_AO_I2C_MASTER] = 18,
102 [RESET_AO_I2C_SLAVE] = 19,
103 [RESET_AO_UART1] = 17,
104 [RESET_AO_UART2] = 22,
105 [RESET_AO_IR_BLASTER] = 23,
106};
107
108static struct clk_regmap *axg_aoclk_regmap[] = {
109 [CLKID_AO_REMOTE] = &axg_aoclk_remote,
110 [CLKID_AO_I2C_MASTER] = &axg_aoclk_i2c_master,
111 [CLKID_AO_I2C_SLAVE] = &axg_aoclk_i2c_slave,
112 [CLKID_AO_UART1] = &axg_aoclk_uart1,
113 [CLKID_AO_UART2] = &axg_aoclk_uart2,
114 [CLKID_AO_IR_BLASTER] = &axg_aoclk_ir_blaster,
115 [CLKID_AO_SAR_ADC] = &axg_aoclk_saradc,
116 [CLKID_AO_CLK81] = &axg_aoclk_clk81,
117 [CLKID_AO_SAR_ADC_SEL] = &axg_aoclk_saradc_mux,
118 [CLKID_AO_SAR_ADC_DIV] = &axg_aoclk_saradc_div,
119 [CLKID_AO_SAR_ADC_CLK] = &axg_aoclk_saradc_gate,
120};
121
122static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
123 .hws = {
124 [CLKID_AO_REMOTE] = &axg_aoclk_remote.hw,
125 [CLKID_AO_I2C_MASTER] = &axg_aoclk_i2c_master.hw,
126 [CLKID_AO_I2C_SLAVE] = &axg_aoclk_i2c_slave.hw,
127 [CLKID_AO_UART1] = &axg_aoclk_uart1.hw,
128 [CLKID_AO_UART2] = &axg_aoclk_uart2.hw,
129 [CLKID_AO_IR_BLASTER] = &axg_aoclk_ir_blaster.hw,
130 [CLKID_AO_SAR_ADC] = &axg_aoclk_saradc.hw,
131 [CLKID_AO_CLK81] = &axg_aoclk_clk81.hw,
132 [CLKID_AO_SAR_ADC_SEL] = &axg_aoclk_saradc_mux.hw,
133 [CLKID_AO_SAR_ADC_DIV] = &axg_aoclk_saradc_div.hw,
134 [CLKID_AO_SAR_ADC_CLK] = &axg_aoclk_saradc_gate.hw,
135 },
136 .num = NR_CLKS,
137};
138
139static const struct meson_aoclk_data axg_aoclkc_data = {
140 .reset_reg = AO_RTI_GEN_CNTL_REG0,
141 .num_reset = ARRAY_SIZE(axg_aoclk_reset),
142 .reset = axg_aoclk_reset,
143 .num_clks = ARRAY_SIZE(axg_aoclk_regmap),
144 .clks = axg_aoclk_regmap,
145 .hw_data = &axg_aoclk_onecell_data,
146};
147
148static const struct of_device_id axg_aoclkc_match_table[] = {
149 {
150 .compatible = "amlogic,meson-axg-aoclkc",
151 .data = &axg_aoclkc_data,
152 },
153 { }
154};
155
156static struct platform_driver axg_aoclkc_driver = {
157 .probe = meson_aoclkc_probe,
158 .driver = {
159 .name = "axg-aoclkc",
160 .of_match_table = axg_aoclkc_match_table,
161 },
162};
163
164builtin_platform_driver(axg_aoclkc_driver);
diff --git a/drivers/clk/meson/axg-aoclk.h b/drivers/clk/meson/axg-aoclk.h
new file mode 100644
index 000000000000..91384d8dd844
--- /dev/null
+++ b/drivers/clk/meson/axg-aoclk.h
@@ -0,0 +1,29 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2017 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 *
6 * Copyright (c) 2018 Amlogic, inc.
7 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
8 */
9
10#ifndef __AXG_AOCLKC_H
11#define __AXG_AOCLKC_H
12
13#define NR_CLKS 11
14/* AO Configuration Clock registers offsets
15 * Register offsets from the data sheet must be multiplied by 4.
16 */
17#define AO_RTI_PWR_CNTL_REG1 0x0C
18#define AO_RTI_PWR_CNTL_REG0 0x10
19#define AO_RTI_GEN_CNTL_REG0 0x40
20#define AO_OSCIN_CNTL 0x58
21#define AO_CRT_CLK_CNTL1 0x68
22#define AO_SAR_CLK 0x90
23#define AO_RTC_ALT_CLK_CNTL0 0x94
24#define AO_RTC_ALT_CLK_CNTL1 0x98
25
26#include <dt-bindings/clock/axg-aoclkc.h>
27#include <dt-bindings/reset/axg-aoclkc.h>
28
29#endif /* __AXG_AOCLKC_H */
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 5f5d468c1efe..bd4dbc696b88 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -461,6 +461,7 @@ static struct clk_regmap axg_mpll0_div = {
461 .width = 1, 461 .width = 1,
462 }, 462 },
463 .lock = &meson_clk_lock, 463 .lock = &meson_clk_lock,
464 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
464 }, 465 },
465 .hw.init = &(struct clk_init_data){ 466 .hw.init = &(struct clk_init_data){
466 .name = "mpll0_div", 467 .name = "mpll0_div",
@@ -507,6 +508,7 @@ static struct clk_regmap axg_mpll1_div = {
507 .width = 1, 508 .width = 1,
508 }, 509 },
509 .lock = &meson_clk_lock, 510 .lock = &meson_clk_lock,
511 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
510 }, 512 },
511 .hw.init = &(struct clk_init_data){ 513 .hw.init = &(struct clk_init_data){
512 .name = "mpll1_div", 514 .name = "mpll1_div",
@@ -553,6 +555,7 @@ static struct clk_regmap axg_mpll2_div = {
553 .width = 1, 555 .width = 1,
554 }, 556 },
555 .lock = &meson_clk_lock, 557 .lock = &meson_clk_lock,
558 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
556 }, 559 },
557 .hw.init = &(struct clk_init_data){ 560 .hw.init = &(struct clk_init_data){
558 .name = "mpll2_div", 561 .name = "mpll2_div",
@@ -599,6 +602,7 @@ static struct clk_regmap axg_mpll3_div = {
599 .width = 1, 602 .width = 1,
600 }, 603 },
601 .lock = &meson_clk_lock, 604 .lock = &meson_clk_lock,
605 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
602 }, 606 },
603 .hw.init = &(struct clk_init_data){ 607 .hw.init = &(struct clk_init_data){
604 .name = "mpll3_div", 608 .name = "mpll3_div",
diff --git a/drivers/clk/meson/clk-audio-divider.c b/drivers/clk/meson/clk-audio-divider.c
index f7ab5b1db342..58f546e04807 100644
--- a/drivers/clk/meson/clk-audio-divider.c
+++ b/drivers/clk/meson/clk-audio-divider.c
@@ -1,18 +1,7 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Copyright (c) 2017 AmLogic, Inc. 3 * Copyright (c) 2017 AmLogic, Inc.
3 * Author: Jerome Brunet <jbrunet@baylibre.com> 4 * Author: Jerome Brunet <jbrunet@baylibre.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */ 5 */
17 6
18/* 7/*
diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c
index 0df1227b65b3..650f75cc15a9 100644
--- a/drivers/clk/meson/clk-mpll.c
+++ b/drivers/clk/meson/clk-mpll.c
@@ -1,57 +1,7 @@
1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
1/* 2/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright (c) 2016 AmLogic, Inc.
8 * Author: Michael Turquette <mturquette@baylibre.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING
24 *
25 * BSD LICENSE
26 *
27 * Copyright (c) 2016 AmLogic, Inc. 3 * Copyright (c) 2016 AmLogic, Inc.
28 * Author: Michael Turquette <mturquette@baylibre.com> 4 * Author: Michael Turquette <mturquette@baylibre.com>
29 *
30 * Redistribution and use in source and binary forms, with or without
31 * modification, are permitted provided that the following conditions
32 * are met:
33 *
34 * * Redistributions of source code must retain the above copyright
35 * notice, this list of conditions and the following disclaimer.
36 * * Redistributions in binary form must reproduce the above copyright
37 * notice, this list of conditions and the following disclaimer in
38 * the documentation and/or other materials provided with the
39 * distribution.
40 * * Neither the name of Intel Corporation nor the names of its
41 * contributors may be used to endorse or promote products derived
42 * from this software without specific prior written permission.
43 *
44 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
45 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
46 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
47 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
48 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
49 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
54 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 */ 5 */
56 6
57/* 7/*
@@ -89,10 +39,23 @@ static long rate_from_params(unsigned long parent_rate,
89static void params_from_rate(unsigned long requested_rate, 39static void params_from_rate(unsigned long requested_rate,
90 unsigned long parent_rate, 40 unsigned long parent_rate,
91 unsigned int *sdm, 41 unsigned int *sdm,
92 unsigned int *n2) 42 unsigned int *n2,
43 u8 flags)
93{ 44{
94 uint64_t div = parent_rate; 45 uint64_t div = parent_rate;
95 unsigned long rem = do_div(div, requested_rate); 46 uint64_t frac = do_div(div, requested_rate);
47
48 frac *= SDM_DEN;
49
50 if (flags & CLK_MESON_MPLL_ROUND_CLOSEST)
51 *sdm = DIV_ROUND_CLOSEST_ULL(frac, requested_rate);
52 else
53 *sdm = DIV_ROUND_UP_ULL(frac, requested_rate);
54
55 if (*sdm == SDM_DEN) {
56 *sdm = 0;
57 div += 1;
58 }
96 59
97 if (div < N2_MIN) { 60 if (div < N2_MIN) {
98 *n2 = N2_MIN; 61 *n2 = N2_MIN;
@@ -102,7 +65,6 @@ static void params_from_rate(unsigned long requested_rate,
102 *sdm = SDM_DEN - 1; 65 *sdm = SDM_DEN - 1;
103 } else { 66 } else {
104 *n2 = div; 67 *n2 = div;
105 *sdm = DIV_ROUND_UP_ULL((u64)rem * SDM_DEN, requested_rate);
106 } 68 }
107} 69}
108 70
@@ -125,9 +87,11 @@ static long mpll_round_rate(struct clk_hw *hw,
125 unsigned long rate, 87 unsigned long rate,
126 unsigned long *parent_rate) 88 unsigned long *parent_rate)
127{ 89{
90 struct clk_regmap *clk = to_clk_regmap(hw);
91 struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
128 unsigned int sdm, n2; 92 unsigned int sdm, n2;
129 93
130 params_from_rate(rate, *parent_rate, &sdm, &n2); 94 params_from_rate(rate, *parent_rate, &sdm, &n2, mpll->flags);
131 return rate_from_params(*parent_rate, sdm, n2); 95 return rate_from_params(*parent_rate, sdm, n2);
132} 96}
133 97
@@ -140,7 +104,7 @@ static int mpll_set_rate(struct clk_hw *hw,
140 unsigned int sdm, n2; 104 unsigned int sdm, n2;
141 unsigned long flags = 0; 105 unsigned long flags = 0;
142 106
143 params_from_rate(rate, parent_rate, &sdm, &n2); 107 params_from_rate(rate, parent_rate, &sdm, &n2, mpll->flags);
144 108
145 if (mpll->lock) 109 if (mpll->lock)
146 spin_lock_irqsave(mpll->lock, flags); 110 spin_lock_irqsave(mpll->lock, flags);
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 65a7bd903551..3e04617ac47f 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -1,21 +1,10 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Copyright (c) 2015 Endless Mobile, Inc. 3 * Copyright (c) 2015 Endless Mobile, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com> 4 * Author: Carlo Caione <carlo@endlessm.com>
4 * 5 *
5 * Copyright (c) 2018 Baylibre, SAS. 6 * Copyright (c) 2018 Baylibre, SAS.
6 * Author: Jerome Brunet <jbrunet@baylibre.com> 7 * Author: Jerome Brunet <jbrunet@baylibre.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */ 8 */
20 9
21/* 10/*
diff --git a/drivers/clk/meson/clk-regmap.c b/drivers/clk/meson/clk-regmap.c
index 3645fdb62343..bd8dbcbdc73c 100644
--- a/drivers/clk/meson/clk-regmap.c
+++ b/drivers/clk/meson/clk-regmap.c
@@ -1,6 +1,8 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2018 BayLibre, SAS. 2/*
3// Author: Jerome Brunet <jbrunet@baylibre.com> 3 * Copyright (c) 2018 BayLibre, SAS.
4 * Author: Jerome Brunet <jbrunet@baylibre.com>
5 */
4 6
5#include "clk-regmap.h" 7#include "clk-regmap.h"
6 8
diff --git a/drivers/clk/meson/clk-regmap.h b/drivers/clk/meson/clk-regmap.h
index 627c888026d7..ed2d4348dbe2 100644
--- a/drivers/clk/meson/clk-regmap.h
+++ b/drivers/clk/meson/clk-regmap.h
@@ -1,6 +1,8 @@
1// SPDX-License-Identifier: GPL-2.0 1/* SPDX-License-Identifier: GPL-2.0 */
2// Copyright (c) 2018 BayLibre, SAS. 2/*
3// Author: Jerome Brunet <jbrunet@baylibre.com> 3 * Copyright (c) 2018 BayLibre, SAS.
4 * Author: Jerome Brunet <jbrunet@baylibre.com>
5 */
4 6
5#ifndef __CLK_REGMAP_H 7#ifndef __CLK_REGMAP_H
6#define __CLK_REGMAP_H 8#define __CLK_REGMAP_H
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 8fe73c4edca8..2fb084330ee9 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -1,18 +1,7 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (c) 2015 Endless Mobile, Inc. 3 * Copyright (c) 2015 Endless Mobile, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com> 4 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */ 5 */
17 6
18#ifndef __CLKC_H 7#ifndef __CLKC_H
@@ -97,8 +86,11 @@ struct meson_clk_mpll_data {
97 struct parm ssen; 86 struct parm ssen;
98 struct parm misc; 87 struct parm misc;
99 spinlock_t *lock; 88 spinlock_t *lock;
89 u8 flags;
100}; 90};
101 91
92#define CLK_MESON_MPLL_ROUND_CLOSEST BIT(0)
93
102struct meson_clk_audio_div_data { 94struct meson_clk_audio_div_data {
103 struct parm div; 95 struct parm div;
104 u8 flags; 96 u8 flags;
diff --git a/drivers/clk/meson/gxbb-aoclk-32k.c b/drivers/clk/meson/gxbb-aoclk-32k.c
index 491634dbc985..680467141a1d 100644
--- a/drivers/clk/meson/gxbb-aoclk-32k.c
+++ b/drivers/clk/meson/gxbb-aoclk-32k.c
@@ -1,8 +1,7 @@
1// SPDX-License-Identifier: GPL-2.0+
1/* 2/*
2 * Copyright (c) 2017 BayLibre, SAS. 3 * Copyright (c) 2017 BayLibre, SAS.
3 * Author: Neil Armstrong <narmstrong@baylibre.com> 4 * Author: Neil Armstrong <narmstrong@baylibre.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */ 5 */
7 6
8#include <linux/clk-provider.h> 7#include <linux/clk-provider.h>
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index 9ec23ae9a219..42ed61d3c3fb 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -1,90 +1,14 @@
1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
1/* 2/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright (c) 2016 BayLibre, SAS. 3 * Copyright (c) 2016 BayLibre, SAS.
8 * Author: Neil Armstrong <narmstrong@baylibre.com> 4 * Author: Neil Armstrong <narmstrong@baylibre.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 * The full GNU General Public License is included in this distribution
22 * in the file called COPYING.
23 *
24 * BSD LICENSE
25 *
26 * Copyright (c) 2016 BayLibre, SAS.
27 * Author: Neil Armstrong <narmstrong@baylibre.com>
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
31 * are met:
32 *
33 * * Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * * Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in
37 * the documentation and/or other materials provided with the
38 * distribution.
39 * * Neither the name of Intel Corporation nor the names of its
40 * contributors may be used to endorse or promote products derived
41 * from this software without specific prior written permission.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 */ 5 */
55#include <linux/clk-provider.h>
56#include <linux/of_address.h>
57#include <linux/platform_device.h> 6#include <linux/platform_device.h>
58#include <linux/reset-controller.h>
59#include <linux/mfd/syscon.h> 7#include <linux/mfd/syscon.h>
60#include <linux/regmap.h>
61#include <linux/init.h>
62#include <linux/delay.h>
63#include <dt-bindings/clock/gxbb-aoclkc.h>
64#include <dt-bindings/reset/gxbb-aoclkc.h>
65#include "clk-regmap.h" 8#include "clk-regmap.h"
9#include "meson-aoclk.h"
66#include "gxbb-aoclk.h" 10#include "gxbb-aoclk.h"
67 11
68struct gxbb_aoclk_reset_controller {
69 struct reset_controller_dev reset;
70 unsigned int *data;
71 struct regmap *regmap;
72};
73
74static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
75 unsigned long id)
76{
77 struct gxbb_aoclk_reset_controller *reset =
78 container_of(rcdev, struct gxbb_aoclk_reset_controller, reset);
79
80 return regmap_write(reset->regmap, AO_RTI_GEN_CNTL_REG0,
81 BIT(reset->data[id]));
82}
83
84static const struct reset_control_ops gxbb_aoclk_reset_ops = {
85 .reset = gxbb_aoclk_do_reset,
86};
87
88#define GXBB_AO_GATE(_name, _bit) \ 12#define GXBB_AO_GATE(_name, _bit) \
89static struct clk_regmap _name##_ao = { \ 13static struct clk_regmap _name##_ao = { \
90 .data = &(struct clk_regmap_gate_data) { \ 14 .data = &(struct clk_regmap_gate_data) { \
@@ -96,7 +20,7 @@ static struct clk_regmap _name##_ao = { \
96 .ops = &clk_regmap_gate_ops, \ 20 .ops = &clk_regmap_gate_ops, \
97 .parent_names = (const char *[]){ "clk81" }, \ 21 .parent_names = (const char *[]){ "clk81" }, \
98 .num_parents = 1, \ 22 .num_parents = 1, \
99 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ 23 .flags = CLK_IGNORE_UNUSED, \
100 }, \ 24 }, \
101} 25}
102 26
@@ -117,7 +41,7 @@ static struct aoclk_cec_32k cec_32k_ao = {
117 }, 41 },
118}; 42};
119 43
120static unsigned int gxbb_aoclk_reset[] = { 44static const unsigned int gxbb_aoclk_reset[] = {
121 [RESET_AO_REMOTE] = 16, 45 [RESET_AO_REMOTE] = 16,
122 [RESET_AO_I2C_MASTER] = 18, 46 [RESET_AO_I2C_MASTER] = 18,
123 [RESET_AO_I2C_SLAVE] = 19, 47 [RESET_AO_I2C_SLAVE] = 19,
@@ -135,7 +59,7 @@ static struct clk_regmap *gxbb_aoclk_gate[] = {
135 [CLKID_AO_IR_BLASTER] = &ir_blaster_ao, 59 [CLKID_AO_IR_BLASTER] = &ir_blaster_ao,
136}; 60};
137 61
138static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = { 62static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
139 .hws = { 63 .hws = {
140 [CLKID_AO_REMOTE] = &remote_ao.hw, 64 [CLKID_AO_REMOTE] = &remote_ao.hw,
141 [CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw, 65 [CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
@@ -145,58 +69,55 @@ static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
145 [CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw, 69 [CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
146 [CLKID_AO_CEC_32K] = &cec_32k_ao.hw, 70 [CLKID_AO_CEC_32K] = &cec_32k_ao.hw,
147 }, 71 },
148 .num = 7, 72 .num = NR_CLKS,
149}; 73};
150 74
151static int gxbb_aoclkc_probe(struct platform_device *pdev) 75static int gxbb_register_cec_ao_32k(struct platform_device *pdev)
152{ 76{
153 struct gxbb_aoclk_reset_controller *rstc;
154 struct device *dev = &pdev->dev; 77 struct device *dev = &pdev->dev;
155 struct regmap *regmap; 78 struct regmap *regmap;
156 int ret, clkid; 79 int ret;
157
158 rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
159 if (!rstc)
160 return -ENOMEM;
161 80
162 regmap = syscon_node_to_regmap(of_get_parent(dev->of_node)); 81 regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
163 if (IS_ERR(regmap)) { 82 if (IS_ERR(regmap)) {
164 dev_err(dev, "failed to get regmap\n"); 83 dev_err(dev, "failed to get regmap\n");
165 return -ENODEV; 84 return PTR_ERR(regmap);
166 }
167
168 /* Reset Controller */
169 rstc->regmap = regmap;
170 rstc->data = gxbb_aoclk_reset;
171 rstc->reset.ops = &gxbb_aoclk_reset_ops;
172 rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
173 rstc->reset.of_node = dev->of_node;
174 ret = devm_reset_controller_register(dev, &rstc->reset);
175
176 /*
177 * Populate regmap and register all clks
178 */
179 for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) {
180 gxbb_aoclk_gate[clkid]->map = regmap;
181
182 ret = devm_clk_hw_register(dev,
183 gxbb_aoclk_onecell_data.hws[clkid]);
184 if (ret)
185 return ret;
186 } 85 }
187 86
188 /* Specific clocks */ 87 /* Specific clocks */
189 cec_32k_ao.regmap = regmap; 88 cec_32k_ao.regmap = regmap;
190 ret = devm_clk_hw_register(dev, &cec_32k_ao.hw); 89 ret = devm_clk_hw_register(dev, &cec_32k_ao.hw);
90 if (ret) {
91 dev_err(&pdev->dev, "clk cec_32k_ao register failed.\n");
92 return ret;
93 }
94
95 return 0;
96}
97
98static const struct meson_aoclk_data gxbb_aoclkc_data = {
99 .reset_reg = AO_RTI_GEN_CNTL_REG0,
100 .num_reset = ARRAY_SIZE(gxbb_aoclk_reset),
101 .reset = gxbb_aoclk_reset,
102 .num_clks = ARRAY_SIZE(gxbb_aoclk_gate),
103 .clks = gxbb_aoclk_gate,
104 .hw_data = &gxbb_aoclk_onecell_data,
105};
106
107static int gxbb_aoclkc_probe(struct platform_device *pdev)
108{
109 int ret = gxbb_register_cec_ao_32k(pdev);
191 if (ret) 110 if (ret)
192 return ret; 111 return ret;
193 112
194 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, 113 return meson_aoclkc_probe(pdev);
195 &gxbb_aoclk_onecell_data);
196} 114}
197 115
198static const struct of_device_id gxbb_aoclkc_match_table[] = { 116static const struct of_device_id gxbb_aoclkc_match_table[] = {
199 { .compatible = "amlogic,meson-gx-aoclkc" }, 117 {
118 .compatible = "amlogic,meson-gx-aoclkc",
119 .data = &gxbb_aoclkc_data,
120 },
200 { } 121 { }
201}; 122};
202 123
diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h
index 0be78383f257..3aa638d4ed21 100644
--- a/drivers/clk/meson/gxbb-aoclk.h
+++ b/drivers/clk/meson/gxbb-aoclk.h
@@ -1,13 +1,14 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
1/* 2/*
2 * Copyright (c) 2017 BayLibre, SAS 3 * Copyright (c) 2017 BayLibre, SAS
3 * Author: Neil Armstrong <narmstrong@baylibre.com> 4 * Author: Neil Armstrong <narmstrong@baylibre.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */ 5 */
7 6
8#ifndef __GXBB_AOCLKC_H 7#ifndef __GXBB_AOCLKC_H
9#define __GXBB_AOCLKC_H 8#define __GXBB_AOCLKC_H
10 9
10#define NR_CLKS 7
11
11/* AO Configuration Clock registers offsets */ 12/* AO Configuration Clock registers offsets */
12#define AO_RTI_PWR_CNTL_REG1 0x0c 13#define AO_RTI_PWR_CNTL_REG1 0x0c
13#define AO_RTI_PWR_CNTL_REG0 0x10 14#define AO_RTI_PWR_CNTL_REG0 0x10
@@ -28,4 +29,7 @@ struct aoclk_cec_32k {
28 29
29extern const struct clk_ops meson_aoclk_cec_32k_ops; 30extern const struct clk_ops meson_aoclk_cec_32k_ops;
30 31
32#include <dt-bindings/clock/gxbb-aoclkc.h>
33#include <dt-bindings/reset/gxbb-aoclkc.h>
34
31#endif /* __GXBB_AOCLKC_H */ 35#endif /* __GXBB_AOCLKC_H */
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index b1e4d9557610..240658404367 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -1,20 +1,7 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * AmLogic S905 / GXBB Clock Controller Driver
3 *
4 * Copyright (c) 2016 AmLogic, Inc. 3 * Copyright (c) 2016 AmLogic, Inc.
5 * Michael Turquette <mturquette@baylibre.com> 4 * Michael Turquette <mturquette@baylibre.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */ 5 */
19 6
20#include <linux/clk.h> 7#include <linux/clk.h>
@@ -1543,6 +1530,102 @@ static struct clk_regmap gxbb_vapb = {
1543 }, 1530 },
1544}; 1531};
1545 1532
1533/* VDEC clocks */
1534
1535static const char * const gxbb_vdec_parent_names[] = {
1536 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1537};
1538
1539static struct clk_regmap gxbb_vdec_1_sel = {
1540 .data = &(struct clk_regmap_mux_data){
1541 .offset = HHI_VDEC_CLK_CNTL,
1542 .mask = 0x3,
1543 .shift = 9,
1544 .flags = CLK_MUX_ROUND_CLOSEST,
1545 },
1546 .hw.init = &(struct clk_init_data){
1547 .name = "vdec_1_sel",
1548 .ops = &clk_regmap_mux_ops,
1549 .parent_names = gxbb_vdec_parent_names,
1550 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
1551 .flags = CLK_SET_RATE_PARENT,
1552 },
1553};
1554
1555static struct clk_regmap gxbb_vdec_1_div = {
1556 .data = &(struct clk_regmap_div_data){
1557 .offset = HHI_VDEC_CLK_CNTL,
1558 .shift = 0,
1559 .width = 7,
1560 },
1561 .hw.init = &(struct clk_init_data){
1562 .name = "vdec_1_div",
1563 .ops = &clk_regmap_divider_ops,
1564 .parent_names = (const char *[]){ "vdec_1_sel" },
1565 .num_parents = 1,
1566 .flags = CLK_SET_RATE_PARENT,
1567 },
1568};
1569
1570static struct clk_regmap gxbb_vdec_1 = {
1571 .data = &(struct clk_regmap_gate_data){
1572 .offset = HHI_VDEC_CLK_CNTL,
1573 .bit_idx = 8,
1574 },
1575 .hw.init = &(struct clk_init_data) {
1576 .name = "vdec_1",
1577 .ops = &clk_regmap_gate_ops,
1578 .parent_names = (const char *[]){ "vdec_1_div" },
1579 .num_parents = 1,
1580 .flags = CLK_SET_RATE_PARENT,
1581 },
1582};
1583
1584static struct clk_regmap gxbb_vdec_hevc_sel = {
1585 .data = &(struct clk_regmap_mux_data){
1586 .offset = HHI_VDEC2_CLK_CNTL,
1587 .mask = 0x3,
1588 .shift = 25,
1589 .flags = CLK_MUX_ROUND_CLOSEST,
1590 },
1591 .hw.init = &(struct clk_init_data){
1592 .name = "vdec_hevc_sel",
1593 .ops = &clk_regmap_mux_ops,
1594 .parent_names = gxbb_vdec_parent_names,
1595 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
1596 .flags = CLK_SET_RATE_PARENT,
1597 },
1598};
1599
1600static struct clk_regmap gxbb_vdec_hevc_div = {
1601 .data = &(struct clk_regmap_div_data){
1602 .offset = HHI_VDEC2_CLK_CNTL,
1603 .shift = 16,
1604 .width = 7,
1605 },
1606 .hw.init = &(struct clk_init_data){
1607 .name = "vdec_hevc_div",
1608 .ops = &clk_regmap_divider_ops,
1609 .parent_names = (const char *[]){ "vdec_hevc_sel" },
1610 .num_parents = 1,
1611 .flags = CLK_SET_RATE_PARENT,
1612 },
1613};
1614
1615static struct clk_regmap gxbb_vdec_hevc = {
1616 .data = &(struct clk_regmap_gate_data){
1617 .offset = HHI_VDEC2_CLK_CNTL,
1618 .bit_idx = 24,
1619 },
1620 .hw.init = &(struct clk_init_data) {
1621 .name = "vdec_hevc",
1622 .ops = &clk_regmap_gate_ops,
1623 .parent_names = (const char *[]){ "vdec_hevc_div" },
1624 .num_parents = 1,
1625 .flags = CLK_SET_RATE_PARENT,
1626 },
1627};
1628
1546/* Everything Else (EE) domain gates */ 1629/* Everything Else (EE) domain gates */
1547static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); 1630static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
1548static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); 1631static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -1786,6 +1869,12 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
1786 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 1869 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
1787 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 1870 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
1788 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 1871 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
1872 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
1873 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
1874 [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
1875 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
1876 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
1877 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
1789 [NR_CLKS] = NULL, 1878 [NR_CLKS] = NULL,
1790 }, 1879 },
1791 .num = NR_CLKS, 1880 .num = NR_CLKS,
@@ -1942,6 +2031,12 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
1942 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 2031 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
1943 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 2032 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
1944 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 2033 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
2034 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
2035 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
2036 [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
2037 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
2038 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
2039 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
1945 [NR_CLKS] = NULL, 2040 [NR_CLKS] = NULL,
1946 }, 2041 },
1947 .num = NR_CLKS, 2042 .num = NR_CLKS,
@@ -2100,6 +2195,12 @@ static struct clk_regmap *const gx_clk_regmaps[] = {
2100 &gxbb_fclk_div4, 2195 &gxbb_fclk_div4,
2101 &gxbb_fclk_div5, 2196 &gxbb_fclk_div5,
2102 &gxbb_fclk_div7, 2197 &gxbb_fclk_div7,
2198 &gxbb_vdec_1_sel,
2199 &gxbb_vdec_1_div,
2200 &gxbb_vdec_1,
2201 &gxbb_vdec_hevc_sel,
2202 &gxbb_vdec_hevc_div,
2203 &gxbb_vdec_hevc,
2103}; 2204};
2104 2205
2105struct clkc_data { 2206struct clkc_data {
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 9febf3f03739..ec1a812bf1fd 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -1,57 +1,7 @@
1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
1/* 2/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright (c) 2016 AmLogic, Inc. 3 * Copyright (c) 2016 AmLogic, Inc.
8 * Author: Michael Turquette <mturquette@baylibre.com> 4 * Author: Michael Turquette <mturquette@baylibre.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING
24 *
25 * BSD LICENSE
26 *
27 * Copyright (c) 2016 BayLibre, Inc.
28 * Author: Michael Turquette <mturquette@baylibre.com>
29 *
30 * Redistribution and use in source and binary forms, with or without
31 * modification, are permitted provided that the following conditions
32 * are met:
33 *
34 * * Redistributions of source code must retain the above copyright
35 * notice, this list of conditions and the following disclaimer.
36 * * Redistributions in binary form must reproduce the above copyright
37 * notice, this list of conditions and the following disclaimer in
38 * the documentation and/or other materials provided with the
39 * distribution.
40 * * Neither the name of Intel Corporation nor the names of its
41 * contributors may be used to endorse or promote products derived
42 * from this software without specific prior written permission.
43 *
44 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
45 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
46 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
47 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
48 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
49 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
54 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 */ 5 */
56 6
57#ifndef __GXBB_H 7#ifndef __GXBB_H
@@ -204,8 +154,12 @@
204#define CLKID_FCLK_DIV4_DIV 148 154#define CLKID_FCLK_DIV4_DIV 148
205#define CLKID_FCLK_DIV5_DIV 149 155#define CLKID_FCLK_DIV5_DIV 149
206#define CLKID_FCLK_DIV7_DIV 150 156#define CLKID_FCLK_DIV7_DIV 150
157#define CLKID_VDEC_1_SEL 151
158#define CLKID_VDEC_1_DIV 152
159#define CLKID_VDEC_HEVC_SEL 154
160#define CLKID_VDEC_HEVC_DIV 155
207 161
208#define NR_CLKS 151 162#define NR_CLKS 157
209 163
210/* include the CLKIDs that have been made part of the DT binding */ 164/* include the CLKIDs that have been made part of the DT binding */
211#include <dt-bindings/clock/gxbb-clkc.h> 165#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
new file mode 100644
index 000000000000..f965845917e3
--- /dev/null
+++ b/drivers/clk/meson/meson-aoclk.c
@@ -0,0 +1,81 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Amlogic Meson-AXG Clock Controller Driver
4 *
5 * Copyright (c) 2016 BayLibre, SAS.
6 * Author: Neil Armstrong <narmstrong@baylibre.com>
7 *
8 * Copyright (c) 2018 Amlogic, inc.
9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
10 * Author: Yixun Lan <yixun.lan@amlogic.com>
11 */
12
13#include <linux/platform_device.h>
14#include <linux/reset-controller.h>
15#include <linux/mfd/syscon.h>
16#include <linux/of_device.h>
17#include "clk-regmap.h"
18#include "meson-aoclk.h"
19
20static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
21 unsigned long id)
22{
23 struct meson_aoclk_reset_controller *rstc =
24 container_of(rcdev, struct meson_aoclk_reset_controller, reset);
25
26 return regmap_write(rstc->regmap, rstc->data->reset_reg,
27 BIT(rstc->data->reset[id]));
28}
29
30static const struct reset_control_ops meson_aoclk_reset_ops = {
31 .reset = meson_aoclk_do_reset,
32};
33
34int meson_aoclkc_probe(struct platform_device *pdev)
35{
36 struct meson_aoclk_reset_controller *rstc;
37 struct meson_aoclk_data *data;
38 struct device *dev = &pdev->dev;
39 struct regmap *regmap;
40 int ret, clkid;
41
42 data = (struct meson_aoclk_data *) of_device_get_match_data(dev);
43 if (!data)
44 return -ENODEV;
45
46 rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
47 if (!rstc)
48 return -ENOMEM;
49
50 regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
51 if (IS_ERR(regmap)) {
52 dev_err(dev, "failed to get regmap\n");
53 return PTR_ERR(regmap);
54 }
55
56 /* Reset Controller */
57 rstc->data = data;
58 rstc->regmap = regmap;
59 rstc->reset.ops = &meson_aoclk_reset_ops;
60 rstc->reset.nr_resets = data->num_reset,
61 rstc->reset.of_node = dev->of_node;
62 ret = devm_reset_controller_register(dev, &rstc->reset);
63 if (ret) {
64 dev_err(dev, "failed to register reset controller\n");
65 return ret;
66 }
67
68 /*
69 * Populate regmap and register all clks
70 */
71 for (clkid = 0; clkid < data->num_clks; clkid++) {
72 data->clks[clkid]->map = regmap;
73
74 ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
75 if (ret)
76 return ret;
77 }
78
79 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
80 (void *) data->hw_data);
81}
diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aoclk.h
new file mode 100644
index 000000000000..ab2819e88922
--- /dev/null
+++ b/drivers/clk/meson/meson-aoclk.h
@@ -0,0 +1,34 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2017 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 *
6 * Copyright (c) 2018 Amlogic, inc.
7 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
8 * Author: Yixun Lan <yixun.lan@amlogic.com>
9 */
10
11#ifndef __MESON_AOCLK_H__
12#define __MESON_AOCLK_H__
13
14#include <linux/platform_device.h>
15#include <linux/reset-controller.h>
16#include "clk-regmap.h"
17
18struct meson_aoclk_data {
19 const unsigned int reset_reg;
20 const int num_reset;
21 const unsigned int *reset;
22 int num_clks;
23 struct clk_regmap **clks;
24 const struct clk_hw_onecell_data *hw_data;
25};
26
27struct meson_aoclk_reset_controller {
28 struct reset_controller_dev reset;
29 const struct meson_aoclk_data *data;
30 struct regmap *regmap;
31};
32
33int meson_aoclkc_probe(struct platform_device *pdev);
34#endif
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index cc2992493e0b..98f96d801de6 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -1,24 +1,10 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller
3 * Driver
4 *
5 * Copyright (c) 2015 Endless Mobile, Inc. 3 * Copyright (c) 2015 Endless Mobile, Inc.
6 * Author: Carlo Caione <carlo@endlessm.com> 4 * Author: Carlo Caione <carlo@endlessm.com>
7 * 5 *
8 * Copyright (c) 2016 BayLibre, Inc. 6 * Copyright (c) 2016 BayLibre, Inc.
9 * Michael Turquette <mturquette@baylibre.com> 7 * Michael Turquette <mturquette@baylibre.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms and conditions of the GNU General Public License,
13 * version 2, as published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program. If not, see <http://www.gnu.org/licenses/>.
22 */ 8 */
23 9
24#include <linux/clk.h> 10#include <linux/clk.h>
@@ -246,6 +232,13 @@ static struct clk_regmap meson8b_fclk_div2 = {
246 .ops = &clk_regmap_gate_ops, 232 .ops = &clk_regmap_gate_ops,
247 .parent_names = (const char *[]){ "fclk_div2_div" }, 233 .parent_names = (const char *[]){ "fclk_div2_div" },
248 .num_parents = 1, 234 .num_parents = 1,
235 /*
236 * FIXME: Ethernet with a RGMII PHYs is not working if
237 * fclk_div2 is disabled. it is currently unclear why this
238 * is. keep it enabled until the Ethernet driver knows how
239 * to manage this clock.
240 */
241 .flags = CLK_IS_CRITICAL,
249 }, 242 },
250}; 243};
251 244
@@ -639,6 +632,54 @@ static struct clk_regmap meson8b_cpu_clk = {
639 }, 632 },
640}; 633};
641 634
635static struct clk_regmap meson8b_nand_clk_sel = {
636 .data = &(struct clk_regmap_mux_data){
637 .offset = HHI_NAND_CLK_CNTL,
638 .mask = 0x7,
639 .shift = 9,
640 .flags = CLK_MUX_ROUND_CLOSEST,
641 },
642 .hw.init = &(struct clk_init_data){
643 .name = "nand_clk_sel",
644 .ops = &clk_regmap_mux_ops,
645 /* FIXME all other parents are unknown: */
646 .parent_names = (const char *[]){ "fclk_div4", "fclk_div3",
647 "fclk_div5", "fclk_div7", "xtal" },
648 .num_parents = 5,
649 .flags = CLK_SET_RATE_PARENT,
650 },
651};
652
653static struct clk_regmap meson8b_nand_clk_div = {
654 .data = &(struct clk_regmap_div_data){
655 .offset = HHI_NAND_CLK_CNTL,
656 .shift = 0,
657 .width = 7,
658 .flags = CLK_DIVIDER_ROUND_CLOSEST,
659 },
660 .hw.init = &(struct clk_init_data){
661 .name = "nand_clk_div",
662 .ops = &clk_regmap_divider_ops,
663 .parent_names = (const char *[]){ "nand_clk_sel" },
664 .num_parents = 1,
665 .flags = CLK_SET_RATE_PARENT,
666 },
667};
668
669static struct clk_regmap meson8b_nand_clk_gate = {
670 .data = &(struct clk_regmap_gate_data){
671 .offset = HHI_NAND_CLK_CNTL,
672 .bit_idx = 8,
673 },
674 .hw.init = &(struct clk_init_data){
675 .name = "nand_clk_gate",
676 .ops = &clk_regmap_gate_ops,
677 .parent_names = (const char *[]){ "nand_clk_div" },
678 .num_parents = 1,
679 .flags = CLK_SET_RATE_PARENT,
680 },
681};
682
642/* Everything Else (EE) domain gates */ 683/* Everything Else (EE) domain gates */
643 684
644static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0); 685static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
@@ -834,6 +875,9 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
834 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw, 875 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
835 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw, 876 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
836 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw, 877 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
878 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
879 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
880 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
837 [CLK_NR_CLKS] = NULL, 881 [CLK_NR_CLKS] = NULL,
838 }, 882 },
839 .num = CLK_NR_CLKS, 883 .num = CLK_NR_CLKS,
@@ -939,6 +983,9 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
939 &meson8b_fclk_div4, 983 &meson8b_fclk_div4,
940 &meson8b_fclk_div5, 984 &meson8b_fclk_div5,
941 &meson8b_fclk_div7, 985 &meson8b_fclk_div7,
986 &meson8b_nand_clk_sel,
987 &meson8b_nand_clk_div,
988 &meson8b_nand_clk_gate,
942}; 989};
943 990
944static const struct meson8b_clk_reset_line { 991static const struct meson8b_clk_reset_line {
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 6e414bd36981..5d09412b5084 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -1,21 +1,10 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright (c) 2015 Endless Mobile, Inc. 3 * Copyright (c) 2015 Endless Mobile, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com> 4 * Author: Carlo Caione <carlo@endlessm.com>
4 * 5 *
5 * Copyright (c) 2016 BayLibre, Inc. 6 * Copyright (c) 2016 BayLibre, Inc.
6 * Michael Turquette <mturquette@baylibre.com> 7 * Michael Turquette <mturquette@baylibre.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */ 8 */
20 9
21#ifndef __MESON8B_H 10#ifndef __MESON8B_H
@@ -40,6 +29,7 @@
40#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ 29#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
41#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */ 30#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */
42#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ 31#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
32#define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */
43#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 33#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
44#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ 34#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
45#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ 35#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
@@ -83,8 +73,10 @@
83#define CLKID_FCLK_DIV4_DIV 107 73#define CLKID_FCLK_DIV4_DIV 107
84#define CLKID_FCLK_DIV5_DIV 108 74#define CLKID_FCLK_DIV5_DIV 108
85#define CLKID_FCLK_DIV7_DIV 109 75#define CLKID_FCLK_DIV7_DIV 109
76#define CLKID_NAND_SEL 110
77#define CLKID_NAND_DIV 111
86 78
87#define CLK_NR_CLKS 110 79#define CLK_NR_CLKS 113
88 80
89/* 81/*
90 * include the CLKID and RESETID that have 82 * include the CLKID and RESETID that have
diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c
index 8491979f4096..68f05c53d40e 100644
--- a/drivers/clk/mvebu/clk-corediv.c
+++ b/drivers/clk/mvebu/clk-corediv.c
@@ -72,7 +72,7 @@ static const struct clk_corediv_desc mvebu_corediv_desc[] = {
72}; 72};
73 73
74static const struct clk_corediv_desc mv98dx3236_corediv_desc[] = { 74static const struct clk_corediv_desc mv98dx3236_corediv_desc[] = {
75 { .mask = 0x0f, .offset = 6, .fieldbit = 26 }, /* NAND clock */ 75 { .mask = 0x0f, .offset = 6, .fieldbit = 27 }, /* NAND clock */
76}; 76};
77 77
78#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw) 78#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index fbf4532f94b8..9c3480dcc38a 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -218,6 +218,33 @@ config MSM_MMCC_8996
218 Say Y if you want to support multimedia devices such as display, 218 Say Y if you want to support multimedia devices such as display,
219 graphics, video encode/decode, camera, etc. 219 graphics, video encode/decode, camera, etc.
220 220
221config MSM_GCC_8998
222 tristate "MSM8998 Global Clock Controller"
223 depends on COMMON_CLK_QCOM
224 help
225 Support for the global clock controller on msm8998 devices.
226 Say Y if you want to use peripheral devices such as UART, SPI,
227 i2c, USB, UFS, SD/eMMC, PCIe, etc.
228
229config SDM_GCC_845
230 tristate "SDM845 Global Clock Controller"
231 select QCOM_GDSC
232 depends on COMMON_CLK_QCOM
233 help
234 Support for the global clock controller on SDM845 devices.
235 Say Y if you want to use peripheral devices such as UART, SPI,
236 i2C, USB, UFS, SDDC, PCIe, etc.
237
238config SDM_VIDEOCC_845
239 tristate "SDM845 Video Clock Controller"
240 depends on COMMON_CLK_QCOM
241 select SDM_GCC_845
242 select QCOM_GDSC
243 help
244 Support for the video clock controller on SDM845 devices.
245 Say Y if you want to support video devices and functionality such as
246 video encode and decode.
247
221config SPMI_PMIC_CLKDIV 248config SPMI_PMIC_CLKDIV
222 tristate "SPMI PMIC clkdiv Support" 249 tristate "SPMI PMIC clkdiv Support"
223 depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST 250 depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 230332cf317e..762c01137c2f 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
30obj-$(CONFIG_MSM_GCC_8994) += gcc-msm8994.o 30obj-$(CONFIG_MSM_GCC_8994) += gcc-msm8994.o
31obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o 31obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
32obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o 32obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
33obj-$(CONFIG_MSM_GCC_8998) += gcc-msm8998.o
33obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o 34obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
34obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o 35obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
35obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o 36obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
@@ -37,4 +38,6 @@ obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o
37obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o 38obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
38obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o 39obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
39obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o 40obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
41obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
42obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
40obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o 43obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 6d04cd96482a..3c49a60072f1 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 2 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
3 * 3 *
4 * This software is licensed under the terms of the GNU General Public 4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and 5 * License version 2, as published by the Free Software Foundation, and
@@ -58,6 +58,8 @@
58#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) 58#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
59#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) 59#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
60#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) 60#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
61#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
62#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
61 63
62const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 64const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
63 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 65 [CLK_ALPHA_PLL_TYPE_DEFAULT] = {
@@ -90,6 +92,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
90 [PLL_OFF_TEST_CTL] = 0x1c, 92 [PLL_OFF_TEST_CTL] = 0x1c,
91 [PLL_OFF_STATUS] = 0x24, 93 [PLL_OFF_STATUS] = 0x24,
92 }, 94 },
95 [CLK_ALPHA_PLL_TYPE_FABIA] = {
96 [PLL_OFF_L_VAL] = 0x04,
97 [PLL_OFF_USER_CTL] = 0x0c,
98 [PLL_OFF_USER_CTL_U] = 0x10,
99 [PLL_OFF_CONFIG_CTL] = 0x14,
100 [PLL_OFF_CONFIG_CTL_U] = 0x18,
101 [PLL_OFF_TEST_CTL] = 0x1c,
102 [PLL_OFF_TEST_CTL_U] = 0x20,
103 [PLL_OFF_STATUS] = 0x24,
104 [PLL_OFF_OPMODE] = 0x2c,
105 [PLL_OFF_FRAC] = 0x38,
106 },
93}; 107};
94EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 108EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
95 109
@@ -108,6 +122,12 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
108#define PLL_HUAYRA_N_MASK 0xff 122#define PLL_HUAYRA_N_MASK 0xff
109#define PLL_HUAYRA_ALPHA_WIDTH 16 123#define PLL_HUAYRA_ALPHA_WIDTH 16
110 124
125#define FABIA_OPMODE_STANDBY 0x0
126#define FABIA_OPMODE_RUN 0x1
127
128#define FABIA_PLL_OUT_MASK 0x7
129#define FABIA_PLL_RATE_MARGIN 500
130
111#define pll_alpha_width(p) \ 131#define pll_alpha_width(p) \
112 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ 132 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
113 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) 133 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
@@ -441,16 +461,12 @@ clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
441 return alpha_pll_calc_rate(prate, l, a, alpha_width); 461 return alpha_pll_calc_rate(prate, l, a, alpha_width);
442} 462}
443 463
444static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, 464
445 int (*is_enabled)(struct clk_hw *)) 465static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
446{ 466{
447 int ret; 467 int ret;
448 u32 mode; 468 u32 mode;
449 469
450 if (!is_enabled(&pll->clkr.hw) ||
451 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
452 return 0;
453
454 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); 470 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
455 471
456 /* Latch the input to the PLL */ 472 /* Latch the input to the PLL */
@@ -489,6 +505,16 @@ static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
489 return 0; 505 return 0;
490} 506}
491 507
508static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
509 int (*is_enabled)(struct clk_hw *))
510{
511 if (!is_enabled(&pll->clkr.hw) ||
512 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
513 return 0;
514
515 return __clk_alpha_pll_update_latch(pll);
516}
517
492static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 518static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
493 unsigned long prate, 519 unsigned long prate,
494 int (*is_enabled)(struct clk_hw *)) 520 int (*is_enabled)(struct clk_hw *))
@@ -832,3 +858,265 @@ const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
832 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 858 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
833}; 859};
834EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops); 860EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
861
862void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
863 const struct alpha_pll_config *config)
864{
865 u32 val, mask;
866
867 if (config->l)
868 regmap_write(regmap, PLL_L_VAL(pll), config->l);
869
870 if (config->alpha)
871 regmap_write(regmap, PLL_FRAC(pll), config->alpha);
872
873 if (config->config_ctl_val)
874 regmap_write(regmap, PLL_CONFIG_CTL(pll),
875 config->config_ctl_val);
876
877 if (config->post_div_mask) {
878 mask = config->post_div_mask;
879 val = config->post_div_val;
880 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
881 }
882
883 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
884 PLL_UPDATE_BYPASS);
885
886 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
887}
888EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
889
890static int alpha_pll_fabia_enable(struct clk_hw *hw)
891{
892 int ret;
893 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
894 u32 val, opmode_val;
895 struct regmap *regmap = pll->clkr.regmap;
896
897 ret = regmap_read(regmap, PLL_MODE(pll), &val);
898 if (ret)
899 return ret;
900
901 /* If in FSM mode, just vote for it */
902 if (val & PLL_VOTE_FSM_ENA) {
903 ret = clk_enable_regmap(hw);
904 if (ret)
905 return ret;
906 return wait_for_pll_enable_active(pll);
907 }
908
909 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
910 if (ret)
911 return ret;
912
913 /* Skip If PLL is already running */
914 if ((opmode_val & FABIA_OPMODE_RUN) && (val & PLL_OUTCTRL))
915 return 0;
916
917 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
918 if (ret)
919 return ret;
920
921 ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
922 if (ret)
923 return ret;
924
925 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
926 PLL_RESET_N);
927 if (ret)
928 return ret;
929
930 ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_RUN);
931 if (ret)
932 return ret;
933
934 ret = wait_for_pll_enable_lock(pll);
935 if (ret)
936 return ret;
937
938 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
939 FABIA_PLL_OUT_MASK, FABIA_PLL_OUT_MASK);
940 if (ret)
941 return ret;
942
943 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
944 PLL_OUTCTRL);
945}
946
947static void alpha_pll_fabia_disable(struct clk_hw *hw)
948{
949 int ret;
950 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
951 u32 val;
952 struct regmap *regmap = pll->clkr.regmap;
953
954 ret = regmap_read(regmap, PLL_MODE(pll), &val);
955 if (ret)
956 return;
957
958 /* If in FSM mode, just unvote it */
959 if (val & PLL_FSM_ENA) {
960 clk_disable_regmap(hw);
961 return;
962 }
963
964 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
965 if (ret)
966 return;
967
968 /* Disable main outputs */
969 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), FABIA_PLL_OUT_MASK,
970 0);
971 if (ret)
972 return;
973
974 /* Place the PLL in STANDBY */
975 regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
976}
977
978static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
979 unsigned long parent_rate)
980{
981 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
982 u32 l, frac, alpha_width = pll_alpha_width(pll);
983
984 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
985 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
986
987 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
988}
989
990static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
991 unsigned long prate)
992{
993 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
994 u32 val, l, alpha_width = pll_alpha_width(pll);
995 u64 a;
996 unsigned long rrate;
997 int ret = 0;
998
999 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1000 if (ret)
1001 return ret;
1002
1003 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1004
1005 /*
1006 * Due to limited number of bits for fractional rate programming, the
1007 * rounded up rate could be marginally higher than the requested rate.
1008 */
1009 if (rrate > (rate + FABIA_PLL_RATE_MARGIN) || rrate < rate) {
1010 pr_err("Call set rate on the PLL with rounded rates!\n");
1011 return -EINVAL;
1012 }
1013
1014 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1015 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
1016
1017 return __clk_alpha_pll_update_latch(pll);
1018}
1019
1020const struct clk_ops clk_alpha_pll_fabia_ops = {
1021 .enable = alpha_pll_fabia_enable,
1022 .disable = alpha_pll_fabia_disable,
1023 .is_enabled = clk_alpha_pll_is_enabled,
1024 .set_rate = alpha_pll_fabia_set_rate,
1025 .recalc_rate = alpha_pll_fabia_recalc_rate,
1026 .round_rate = clk_alpha_pll_round_rate,
1027};
1028EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
1029
1030const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
1031 .enable = alpha_pll_fabia_enable,
1032 .disable = alpha_pll_fabia_disable,
1033 .is_enabled = clk_alpha_pll_is_enabled,
1034 .recalc_rate = alpha_pll_fabia_recalc_rate,
1035 .round_rate = clk_alpha_pll_round_rate,
1036};
1037EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
1038
1039static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1040 unsigned long parent_rate)
1041{
1042 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1043 u32 i, div = 1, val;
1044 int ret;
1045
1046 if (!pll->post_div_table) {
1047 pr_err("Missing the post_div_table for the PLL\n");
1048 return -EINVAL;
1049 }
1050
1051 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1052 if (ret)
1053 return ret;
1054
1055 val >>= pll->post_div_shift;
1056 val &= BIT(pll->width) - 1;
1057
1058 for (i = 0; i < pll->num_post_div; i++) {
1059 if (pll->post_div_table[i].val == val) {
1060 div = pll->post_div_table[i].div;
1061 break;
1062 }
1063 }
1064
1065 return (parent_rate / div);
1066}
1067
1068static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
1069 unsigned long rate, unsigned long *prate)
1070{
1071 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1072
1073 if (!pll->post_div_table) {
1074 pr_err("Missing the post_div_table for the PLL\n");
1075 return -EINVAL;
1076 }
1077
1078 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1079 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1080}
1081
1082static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
1083 unsigned long rate, unsigned long parent_rate)
1084{
1085 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1086 int i, val = 0, div, ret;
1087
1088 /*
1089 * If the PLL is in FSM mode, then treat set_rate callback as a
1090 * no-operation.
1091 */
1092 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1093 if (ret)
1094 return ret;
1095
1096 if (val & PLL_VOTE_FSM_ENA)
1097 return 0;
1098
1099 if (!pll->post_div_table) {
1100 pr_err("Missing the post_div_table for the PLL\n");
1101 return -EINVAL;
1102 }
1103
1104 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
1105 for (i = 0; i < pll->num_post_div; i++) {
1106 if (pll->post_div_table[i].div == div) {
1107 val = pll->post_div_table[i].val;
1108 break;
1109 }
1110 }
1111
1112 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1113 (BIT(pll->width) - 1) << pll->post_div_shift,
1114 val << pll->post_div_shift);
1115}
1116
1117const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
1118 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1119 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1120 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1121};
1122EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 7593e8a56cf2..f981b486c468 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 2 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
3 * 3 *
4 * This software is licensed under the terms of the GNU General Public 4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and 5 * License version 2, as published by the Free Software Foundation, and
@@ -22,6 +22,7 @@ enum {
22 CLK_ALPHA_PLL_TYPE_DEFAULT, 22 CLK_ALPHA_PLL_TYPE_DEFAULT,
23 CLK_ALPHA_PLL_TYPE_HUAYRA, 23 CLK_ALPHA_PLL_TYPE_HUAYRA,
24 CLK_ALPHA_PLL_TYPE_BRAMMO, 24 CLK_ALPHA_PLL_TYPE_BRAMMO,
25 CLK_ALPHA_PLL_TYPE_FABIA,
25 CLK_ALPHA_PLL_TYPE_MAX, 26 CLK_ALPHA_PLL_TYPE_MAX,
26}; 27};
27 28
@@ -36,6 +37,8 @@ enum {
36 PLL_OFF_TEST_CTL, 37 PLL_OFF_TEST_CTL,
37 PLL_OFF_TEST_CTL_U, 38 PLL_OFF_TEST_CTL_U,
38 PLL_OFF_STATUS, 39 PLL_OFF_STATUS,
40 PLL_OFF_OPMODE,
41 PLL_OFF_FRAC,
39 PLL_OFF_MAX_REGS 42 PLL_OFF_MAX_REGS
40}; 43};
41 44
@@ -73,6 +76,10 @@ struct clk_alpha_pll {
73 * @offset: base address of registers 76 * @offset: base address of registers
74 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 77 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
75 * @width: width of post-divider 78 * @width: width of post-divider
79 * @post_div_shift: shift to differentiate between odd & even post-divider
80 * @post_div_table: table with PLL odd and even post-divider settings
81 * @num_post_div: Number of PLL post-divider settings
82 *
76 * @clkr: regmap clock handle 83 * @clkr: regmap clock handle
77 */ 84 */
78struct clk_alpha_pll_postdiv { 85struct clk_alpha_pll_postdiv {
@@ -81,6 +88,9 @@ struct clk_alpha_pll_postdiv {
81 const u8 *regs; 88 const u8 *regs;
82 89
83 struct clk_regmap clkr; 90 struct clk_regmap clkr;
91 int post_div_shift;
92 const struct clk_div_table *post_div_table;
93 size_t num_post_div;
84}; 94};
85 95
86struct alpha_pll_config { 96struct alpha_pll_config {
@@ -109,7 +119,13 @@ extern const struct clk_ops clk_alpha_pll_postdiv_ops;
109extern const struct clk_ops clk_alpha_pll_huayra_ops; 119extern const struct clk_ops clk_alpha_pll_huayra_ops;
110extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; 120extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
111 121
122extern const struct clk_ops clk_alpha_pll_fabia_ops;
123extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
124extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
125
112void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 126void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
113 const struct alpha_pll_config *config); 127 const struct alpha_pll_config *config);
128void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
129 const struct alpha_pll_config *config);
114 130
115#endif 131#endif
diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c
index 26f7af315066..c58c5538b1b6 100644
--- a/drivers/clk/qcom/clk-branch.c
+++ b/drivers/clk/qcom/clk-branch.c
@@ -77,8 +77,11 @@ static int clk_branch_wait(const struct clk_branch *br, bool enabling,
77 bool voted = br->halt_check & BRANCH_VOTED; 77 bool voted = br->halt_check & BRANCH_VOTED;
78 const char *name = clk_hw_get_name(&br->clkr.hw); 78 const char *name = clk_hw_get_name(&br->clkr.hw);
79 79
80 /* Skip checking halt bit if the clock is in hardware gated mode */ 80 /*
81 if (clk_branch_in_hwcg_mode(br)) 81 * Skip checking halt bit if we're explicitly ignoring the bit or the
82 * clock is in hardware gated mode
83 */
84 if (br->halt_check == BRANCH_HALT_SKIP || clk_branch_in_hwcg_mode(br))
82 return 0; 85 return 0;
83 86
84 if (br->halt_check == BRANCH_HALT_DELAY || (!enabling && voted)) { 87 if (br->halt_check == BRANCH_HALT_DELAY || (!enabling && voted)) {
diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h
index 284df3f3c55f..1702efb1c511 100644
--- a/drivers/clk/qcom/clk-branch.h
+++ b/drivers/clk/qcom/clk-branch.h
@@ -42,6 +42,7 @@ struct clk_branch {
42#define BRANCH_HALT_ENABLE 1 /* pol: 0 = halt */ 42#define BRANCH_HALT_ENABLE 1 /* pol: 0 = halt */
43#define BRANCH_HALT_ENABLE_VOTED (BRANCH_HALT_ENABLE | BRANCH_VOTED) 43#define BRANCH_HALT_ENABLE_VOTED (BRANCH_HALT_ENABLE | BRANCH_VOTED)
44#define BRANCH_HALT_DELAY 2 /* No bit to check; just delay */ 44#define BRANCH_HALT_DELAY 2 /* No bit to check; just delay */
45#define BRANCH_HALT_SKIP 3 /* Don't check halt bit */
45 46
46 struct clk_regmap clkr; 47 struct clk_regmap clkr;
47}; 48};
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index 2a7489a84e69..b209a2fe86b9 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -1,15 +1,5 @@
1/* 1/* SPDX-License-Identifier: GPL-2.0 */
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 2/* Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved. */
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13 3
14#ifndef __QCOM_CLK_RCG_H__ 4#ifndef __QCOM_CLK_RCG_H__
15#define __QCOM_CLK_RCG_H__ 5#define __QCOM_CLK_RCG_H__
@@ -144,6 +134,7 @@ extern const struct clk_ops clk_dyn_rcg_ops;
144 * @cmd_rcgr: corresponds to *_CMD_RCGR 134 * @cmd_rcgr: corresponds to *_CMD_RCGR
145 * @mnd_width: number of bits in m/n/d values 135 * @mnd_width: number of bits in m/n/d values
146 * @hid_width: number of bits in half integer divider 136 * @hid_width: number of bits in half integer divider
137 * @safe_src_index: safe src index value
147 * @parent_map: map from software's parent index to hardware's src_sel field 138 * @parent_map: map from software's parent index to hardware's src_sel field
148 * @freq_tbl: frequency table 139 * @freq_tbl: frequency table
149 * @clkr: regmap clock handle 140 * @clkr: regmap clock handle
@@ -153,6 +144,7 @@ struct clk_rcg2 {
153 u32 cmd_rcgr; 144 u32 cmd_rcgr;
154 u8 mnd_width; 145 u8 mnd_width;
155 u8 hid_width; 146 u8 hid_width;
147 u8 safe_src_index;
156 const struct parent_map *parent_map; 148 const struct parent_map *parent_map;
157 const struct freq_tbl *freq_tbl; 149 const struct freq_tbl *freq_tbl;
158 struct clk_regmap clkr; 150 struct clk_regmap clkr;
@@ -167,5 +159,6 @@ extern const struct clk_ops clk_byte_ops;
167extern const struct clk_ops clk_byte2_ops; 159extern const struct clk_ops clk_byte2_ops;
168extern const struct clk_ops clk_pixel_ops; 160extern const struct clk_ops clk_pixel_ops;
169extern const struct clk_ops clk_gfx3d_ops; 161extern const struct clk_ops clk_gfx3d_ops;
162extern const struct clk_ops clk_rcg2_shared_ops;
170 163
171#endif 164#endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index bbeaf9c09dbb..52208d4165f4 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -1,14 +1,6 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */ 4 */
13 5
14#include <linux/kernel.h> 6#include <linux/kernel.h>
@@ -42,6 +34,7 @@
42#define CFG_MODE_SHIFT 12 34#define CFG_MODE_SHIFT 12
43#define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT) 35#define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT)
44#define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT) 36#define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT)
37#define CFG_HW_CLK_CTRL_MASK BIT(20)
45 38
46#define M_REG 0x8 39#define M_REG 0x8
47#define N_REG 0xc 40#define N_REG 0xc
@@ -211,6 +204,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
211 clk_flags = clk_hw_get_flags(hw); 204 clk_flags = clk_hw_get_flags(hw);
212 p = clk_hw_get_parent_by_index(hw, index); 205 p = clk_hw_get_parent_by_index(hw, index);
213 if (clk_flags & CLK_SET_RATE_PARENT) { 206 if (clk_flags & CLK_SET_RATE_PARENT) {
207 rate = f->freq;
214 if (f->pre_div) { 208 if (f->pre_div) {
215 rate /= 2; 209 rate /= 2;
216 rate *= f->pre_div + 1; 210 rate *= f->pre_div + 1;
@@ -248,7 +242,7 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,
248 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR); 242 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR);
249} 243}
250 244
251static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) 245static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
252{ 246{
253 u32 cfg, mask; 247 u32 cfg, mask;
254 struct clk_hw *hw = &rcg->clkr.hw; 248 struct clk_hw *hw = &rcg->clkr.hw;
@@ -276,13 +270,21 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
276 } 270 }
277 271
278 mask = BIT(rcg->hid_width) - 1; 272 mask = BIT(rcg->hid_width) - 1;
279 mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK; 273 mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK;
280 cfg = f->pre_div << CFG_SRC_DIV_SHIFT; 274 cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
281 cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; 275 cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
282 if (rcg->mnd_width && f->n && (f->m != f->n)) 276 if (rcg->mnd_width && f->n && (f->m != f->n))
283 cfg |= CFG_MODE_DUAL_EDGE; 277 cfg |= CFG_MODE_DUAL_EDGE;
284 ret = regmap_update_bits(rcg->clkr.regmap, 278
285 rcg->cmd_rcgr + CFG_REG, mask, cfg); 279 return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
280 mask, cfg);
281}
282
283static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
284{
285 int ret;
286
287 ret = __clk_rcg2_configure(rcg, f);
286 if (ret) 288 if (ret)
287 return ret; 289 return ret;
288 290
@@ -789,3 +791,141 @@ const struct clk_ops clk_gfx3d_ops = {
789 .determine_rate = clk_gfx3d_determine_rate, 791 .determine_rate = clk_gfx3d_determine_rate,
790}; 792};
791EXPORT_SYMBOL_GPL(clk_gfx3d_ops); 793EXPORT_SYMBOL_GPL(clk_gfx3d_ops);
794
795static int clk_rcg2_set_force_enable(struct clk_hw *hw)
796{
797 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
798 const char *name = clk_hw_get_name(hw);
799 int ret, count;
800
801 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
802 CMD_ROOT_EN, CMD_ROOT_EN);
803 if (ret)
804 return ret;
805
806 /* wait for RCG to turn ON */
807 for (count = 500; count > 0; count--) {
808 if (clk_rcg2_is_enabled(hw))
809 return 0;
810
811 udelay(1);
812 }
813
814 pr_err("%s: RCG did not turn on\n", name);
815 return -ETIMEDOUT;
816}
817
818static int clk_rcg2_clear_force_enable(struct clk_hw *hw)
819{
820 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
821
822 return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
823 CMD_ROOT_EN, 0);
824}
825
826static int
827clk_rcg2_shared_force_enable_clear(struct clk_hw *hw, const struct freq_tbl *f)
828{
829 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
830 int ret;
831
832 ret = clk_rcg2_set_force_enable(hw);
833 if (ret)
834 return ret;
835
836 ret = clk_rcg2_configure(rcg, f);
837 if (ret)
838 return ret;
839
840 return clk_rcg2_clear_force_enable(hw);
841}
842
843static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate,
844 unsigned long parent_rate)
845{
846 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
847 const struct freq_tbl *f;
848
849 f = qcom_find_freq(rcg->freq_tbl, rate);
850 if (!f)
851 return -EINVAL;
852
853 /*
854 * In case clock is disabled, update the CFG, M, N and D registers
855 * and don't hit the update bit of CMD register.
856 */
857 if (!__clk_is_enabled(hw->clk))
858 return __clk_rcg2_configure(rcg, f);
859
860 return clk_rcg2_shared_force_enable_clear(hw, f);
861}
862
863static int clk_rcg2_shared_set_rate_and_parent(struct clk_hw *hw,
864 unsigned long rate, unsigned long parent_rate, u8 index)
865{
866 return clk_rcg2_shared_set_rate(hw, rate, parent_rate);
867}
868
869static int clk_rcg2_shared_enable(struct clk_hw *hw)
870{
871 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
872 int ret;
873
874 /*
875 * Set the update bit because required configuration has already
876 * been written in clk_rcg2_shared_set_rate()
877 */
878 ret = clk_rcg2_set_force_enable(hw);
879 if (ret)
880 return ret;
881
882 ret = update_config(rcg);
883 if (ret)
884 return ret;
885
886 return clk_rcg2_clear_force_enable(hw);
887}
888
889static void clk_rcg2_shared_disable(struct clk_hw *hw)
890{
891 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
892 u32 cfg;
893
894 /*
895 * Store current configuration as switching to safe source would clear
896 * the SRC and DIV of CFG register
897 */
898 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
899
900 /*
901 * Park the RCG at a safe configuration - sourced off of safe source.
902 * Force enable and disable the RCG while configuring it to safeguard
903 * against any update signal coming from the downstream clock.
904 * The current parent is still prepared and enabled at this point, and
905 * the safe source is always on while application processor subsystem
906 * is online. Therefore, the RCG can safely switch its parent.
907 */
908 clk_rcg2_set_force_enable(hw);
909
910 regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
911 rcg->safe_src_index << CFG_SRC_SEL_SHIFT);
912
913 update_config(rcg);
914
915 clk_rcg2_clear_force_enable(hw);
916
917 /* Write back the stored configuration corresponding to current rate */
918 regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);
919}
920
921const struct clk_ops clk_rcg2_shared_ops = {
922 .enable = clk_rcg2_shared_enable,
923 .disable = clk_rcg2_shared_disable,
924 .get_parent = clk_rcg2_get_parent,
925 .set_parent = clk_rcg2_set_parent,
926 .recalc_rate = clk_rcg2_recalc_rate,
927 .determine_rate = clk_rcg2_determine_rate,
928 .set_rate = clk_rcg2_shared_set_rate,
929 .set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,
930};
931EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index b8064a336d46..39ce64c2783b 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -228,22 +228,6 @@ int qcom_cc_really_probe(struct platform_device *pdev,
228 if (!cc) 228 if (!cc)
229 return -ENOMEM; 229 return -ENOMEM;
230 230
231 cc->rclks = rclks;
232 cc->num_rclks = num_clks;
233
234 for (i = 0; i < num_clks; i++) {
235 if (!rclks[i])
236 continue;
237
238 ret = devm_clk_register_regmap(dev, rclks[i]);
239 if (ret)
240 return ret;
241 }
242
243 ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc);
244 if (ret)
245 return ret;
246
247 reset = &cc->reset; 231 reset = &cc->reset;
248 reset->rcdev.of_node = dev->of_node; 232 reset->rcdev.of_node = dev->of_node;
249 reset->rcdev.ops = &qcom_reset_ops; 233 reset->rcdev.ops = &qcom_reset_ops;
@@ -272,6 +256,22 @@ int qcom_cc_really_probe(struct platform_device *pdev,
272 return ret; 256 return ret;
273 } 257 }
274 258
259 cc->rclks = rclks;
260 cc->num_rclks = num_clks;
261
262 for (i = 0; i < num_clks; i++) {
263 if (!rclks[i])
264 continue;
265
266 ret = devm_clk_register_regmap(dev, rclks[i]);
267 if (ret)
268 return ret;
269 }
270
271 ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc);
272 if (ret)
273 return ret;
274
275 return 0; 275 return 0;
276} 276}
277EXPORT_SYMBOL_GPL(qcom_cc_really_probe); 277EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index 3d6452932797..9f35b3fe1d97 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -1418,6 +1418,7 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
1418 1418
1419static struct clk_branch gcc_usb3_phy_pipe_clk = { 1419static struct clk_branch gcc_usb3_phy_pipe_clk = {
1420 .halt_reg = 0x50004, 1420 .halt_reg = 0x50004,
1421 .halt_check = BRANCH_HALT_SKIP,
1421 .clkr = { 1422 .clkr = {
1422 .enable_reg = 0x50004, 1423 .enable_reg = 0x50004,
1423 .enable_mask = BIT(0), 1424 .enable_mask = BIT(0),
@@ -2472,6 +2473,7 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
2472 2473
2473static struct clk_branch gcc_pcie_0_pipe_clk = { 2474static struct clk_branch gcc_pcie_0_pipe_clk = {
2474 .halt_reg = 0x6b018, 2475 .halt_reg = 0x6b018,
2476 .halt_check = BRANCH_HALT_SKIP,
2475 .clkr = { 2477 .clkr = {
2476 .enable_reg = 0x6b018, 2478 .enable_reg = 0x6b018,
2477 .enable_mask = BIT(0), 2479 .enable_mask = BIT(0),
@@ -2547,6 +2549,7 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
2547 2549
2548static struct clk_branch gcc_pcie_1_pipe_clk = { 2550static struct clk_branch gcc_pcie_1_pipe_clk = {
2549 .halt_reg = 0x6d018, 2551 .halt_reg = 0x6d018,
2552 .halt_check = BRANCH_HALT_SKIP,
2550 .clkr = { 2553 .clkr = {
2551 .enable_reg = 0x6d018, 2554 .enable_reg = 0x6d018,
2552 .enable_mask = BIT(0), 2555 .enable_mask = BIT(0),
@@ -2622,6 +2625,7 @@ static struct clk_branch gcc_pcie_2_aux_clk = {
2622 2625
2623static struct clk_branch gcc_pcie_2_pipe_clk = { 2626static struct clk_branch gcc_pcie_2_pipe_clk = {
2624 .halt_reg = 0x6e018, 2627 .halt_reg = 0x6e018,
2628 .halt_check = BRANCH_HALT_SKIP,
2625 .clkr = { 2629 .clkr = {
2626 .enable_reg = 0x6e018, 2630 .enable_reg = 0x6e018,
2627 .enable_mask = BIT(0), 2631 .enable_mask = BIT(0),
@@ -2792,6 +2796,7 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2792 2796
2793static struct clk_branch gcc_ufs_rx_symbol_0_clk = { 2797static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2794 .halt_reg = 0x7501c, 2798 .halt_reg = 0x7501c,
2799 .halt_check = BRANCH_HALT_SKIP,
2795 .clkr = { 2800 .clkr = {
2796 .enable_reg = 0x7501c, 2801 .enable_reg = 0x7501c,
2797 .enable_mask = BIT(0), 2802 .enable_mask = BIT(0),
@@ -2807,6 +2812,7 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2807 2812
2808static struct clk_branch gcc_ufs_rx_symbol_1_clk = { 2813static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2809 .halt_reg = 0x75020, 2814 .halt_reg = 0x75020,
2815 .halt_check = BRANCH_HALT_SKIP,
2810 .clkr = { 2816 .clkr = {
2811 .enable_reg = 0x75020, 2817 .enable_reg = 0x75020,
2812 .enable_mask = BIT(0), 2818 .enable_mask = BIT(0),
@@ -3105,7 +3111,7 @@ static struct gdsc aggre0_noc_gdsc = {
3105 .name = "aggre0_noc", 3111 .name = "aggre0_noc",
3106 }, 3112 },
3107 .pwrsts = PWRSTS_OFF_ON, 3113 .pwrsts = PWRSTS_OFF_ON,
3108 .flags = VOTABLE, 3114 .flags = VOTABLE | ALWAYS_ON,
3109}; 3115};
3110 3116
3111static struct gdsc hlos1_vote_aggre0_noc_gdsc = { 3117static struct gdsc hlos1_vote_aggre0_noc_gdsc = {
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
new file mode 100644
index 000000000000..78d87f5c7098
--- /dev/null
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -0,0 +1,2834 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/kernel.h>
7#include <linux/bitops.h>
8#include <linux/err.h>
9#include <linux/platform_device.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_device.h>
13#include <linux/clk-provider.h>
14#include <linux/regmap.h>
15#include <linux/reset-controller.h>
16
17#include <dt-bindings/clock/qcom,gcc-msm8998.h>
18
19#include "common.h"
20#include "clk-regmap.h"
21#include "clk-alpha-pll.h"
22#include "clk-pll.h"
23#include "clk-rcg.h"
24#include "clk-branch.h"
25#include "reset.h"
26#include "gdsc.h"
27
28#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
29
30enum {
31 P_AUD_REF_CLK,
32 P_CORE_BI_PLL_TEST_SE,
33 P_GPLL0_OUT_MAIN,
34 P_GPLL4_OUT_MAIN,
35 P_PLL0_EARLY_DIV_CLK_SRC,
36 P_SLEEP_CLK,
37 P_XO,
38};
39
40static const struct parent_map gcc_parent_map_0[] = {
41 { P_XO, 0 },
42 { P_GPLL0_OUT_MAIN, 1 },
43 { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
44 { P_CORE_BI_PLL_TEST_SE, 7 },
45};
46
47static const char * const gcc_parent_names_0[] = {
48 "xo",
49 "gpll0_out_main",
50 "gpll0_out_main",
51 "core_bi_pll_test_se",
52};
53
54static const struct parent_map gcc_parent_map_1[] = {
55 { P_XO, 0 },
56 { P_GPLL0_OUT_MAIN, 1 },
57 { P_CORE_BI_PLL_TEST_SE, 7 },
58};
59
60static const char * const gcc_parent_names_1[] = {
61 "xo",
62 "gpll0_out_main",
63 "core_bi_pll_test_se",
64};
65
66static const struct parent_map gcc_parent_map_2[] = {
67 { P_XO, 0 },
68 { P_GPLL0_OUT_MAIN, 1 },
69 { P_SLEEP_CLK, 5 },
70 { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
71 { P_CORE_BI_PLL_TEST_SE, 7 },
72};
73
74static const char * const gcc_parent_names_2[] = {
75 "xo",
76 "gpll0_out_main",
77 "core_pi_sleep_clk",
78 "gpll0_out_main",
79 "core_bi_pll_test_se",
80};
81
82static const struct parent_map gcc_parent_map_3[] = {
83 { P_XO, 0 },
84 { P_SLEEP_CLK, 5 },
85 { P_CORE_BI_PLL_TEST_SE, 7 },
86};
87
88static const char * const gcc_parent_names_3[] = {
89 "xo",
90 "core_pi_sleep_clk",
91 "core_bi_pll_test_se",
92};
93
94static const struct parent_map gcc_parent_map_4[] = {
95 { P_XO, 0 },
96 { P_GPLL0_OUT_MAIN, 1 },
97 { P_GPLL4_OUT_MAIN, 5 },
98 { P_CORE_BI_PLL_TEST_SE, 7 },
99};
100
101static const char * const gcc_parent_names_4[] = {
102 "xo",
103 "gpll0_out_main",
104 "gpll4_out_main",
105 "core_bi_pll_test_se",
106};
107
108static const struct parent_map gcc_parent_map_5[] = {
109 { P_XO, 0 },
110 { P_GPLL0_OUT_MAIN, 1 },
111 { P_AUD_REF_CLK, 2 },
112 { P_CORE_BI_PLL_TEST_SE, 7 },
113};
114
115static const char * const gcc_parent_names_5[] = {
116 "xo",
117 "gpll0_out_main",
118 "aud_ref_clk",
119 "core_bi_pll_test_se",
120};
121
122static struct pll_vco fabia_vco[] = {
123 { 250000000, 2000000000, 0 },
124 { 125000000, 1000000000, 1 },
125};
126
127static struct clk_alpha_pll gpll0 = {
128 .offset = 0x0,
129 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
130 .vco_table = fabia_vco,
131 .num_vco = ARRAY_SIZE(fabia_vco),
132 .clkr = {
133 .enable_reg = 0x52000,
134 .enable_mask = BIT(0),
135 .hw.init = &(struct clk_init_data){
136 .name = "gpll0",
137 .parent_names = (const char *[]){ "xo" },
138 .num_parents = 1,
139 .ops = &clk_alpha_pll_ops,
140 }
141 },
142};
143
144static struct clk_alpha_pll_postdiv gpll0_out_even = {
145 .offset = 0x0,
146 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
147 .clkr.hw.init = &(struct clk_init_data){
148 .name = "gpll0_out_even",
149 .parent_names = (const char *[]){ "gpll0" },
150 .num_parents = 1,
151 .ops = &clk_alpha_pll_postdiv_ops,
152 },
153};
154
155static struct clk_alpha_pll_postdiv gpll0_out_main = {
156 .offset = 0x0,
157 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
158 .clkr.hw.init = &(struct clk_init_data){
159 .name = "gpll0_out_main",
160 .parent_names = (const char *[]){ "gpll0" },
161 .num_parents = 1,
162 .ops = &clk_alpha_pll_postdiv_ops,
163 },
164};
165
166static struct clk_alpha_pll_postdiv gpll0_out_odd = {
167 .offset = 0x0,
168 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
169 .clkr.hw.init = &(struct clk_init_data){
170 .name = "gpll0_out_odd",
171 .parent_names = (const char *[]){ "gpll0" },
172 .num_parents = 1,
173 .ops = &clk_alpha_pll_postdiv_ops,
174 },
175};
176
177static struct clk_alpha_pll_postdiv gpll0_out_test = {
178 .offset = 0x0,
179 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
180 .clkr.hw.init = &(struct clk_init_data){
181 .name = "gpll0_out_test",
182 .parent_names = (const char *[]){ "gpll0" },
183 .num_parents = 1,
184 .ops = &clk_alpha_pll_postdiv_ops,
185 },
186};
187
188static struct clk_alpha_pll gpll1 = {
189 .offset = 0x1000,
190 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
191 .vco_table = fabia_vco,
192 .num_vco = ARRAY_SIZE(fabia_vco),
193 .clkr = {
194 .enable_reg = 0x52000,
195 .enable_mask = BIT(1),
196 .hw.init = &(struct clk_init_data){
197 .name = "gpll1",
198 .parent_names = (const char *[]){ "xo" },
199 .num_parents = 1,
200 .ops = &clk_alpha_pll_ops,
201 }
202 },
203};
204
205static struct clk_alpha_pll_postdiv gpll1_out_even = {
206 .offset = 0x1000,
207 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
208 .clkr.hw.init = &(struct clk_init_data){
209 .name = "gpll1_out_even",
210 .parent_names = (const char *[]){ "gpll1" },
211 .num_parents = 1,
212 .ops = &clk_alpha_pll_postdiv_ops,
213 },
214};
215
216static struct clk_alpha_pll_postdiv gpll1_out_main = {
217 .offset = 0x1000,
218 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
219 .clkr.hw.init = &(struct clk_init_data){
220 .name = "gpll1_out_main",
221 .parent_names = (const char *[]){ "gpll1" },
222 .num_parents = 1,
223 .ops = &clk_alpha_pll_postdiv_ops,
224 },
225};
226
227static struct clk_alpha_pll_postdiv gpll1_out_odd = {
228 .offset = 0x1000,
229 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
230 .clkr.hw.init = &(struct clk_init_data){
231 .name = "gpll1_out_odd",
232 .parent_names = (const char *[]){ "gpll1" },
233 .num_parents = 1,
234 .ops = &clk_alpha_pll_postdiv_ops,
235 },
236};
237
238static struct clk_alpha_pll_postdiv gpll1_out_test = {
239 .offset = 0x1000,
240 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
241 .clkr.hw.init = &(struct clk_init_data){
242 .name = "gpll1_out_test",
243 .parent_names = (const char *[]){ "gpll1" },
244 .num_parents = 1,
245 .ops = &clk_alpha_pll_postdiv_ops,
246 },
247};
248
249static struct clk_alpha_pll gpll2 = {
250 .offset = 0x2000,
251 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
252 .vco_table = fabia_vco,
253 .num_vco = ARRAY_SIZE(fabia_vco),
254 .clkr = {
255 .enable_reg = 0x52000,
256 .enable_mask = BIT(2),
257 .hw.init = &(struct clk_init_data){
258 .name = "gpll2",
259 .parent_names = (const char *[]){ "xo" },
260 .num_parents = 1,
261 .ops = &clk_alpha_pll_ops,
262 }
263 },
264};
265
266static struct clk_alpha_pll_postdiv gpll2_out_even = {
267 .offset = 0x2000,
268 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
269 .clkr.hw.init = &(struct clk_init_data){
270 .name = "gpll2_out_even",
271 .parent_names = (const char *[]){ "gpll2" },
272 .num_parents = 1,
273 .ops = &clk_alpha_pll_postdiv_ops,
274 },
275};
276
277static struct clk_alpha_pll_postdiv gpll2_out_main = {
278 .offset = 0x2000,
279 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
280 .clkr.hw.init = &(struct clk_init_data){
281 .name = "gpll2_out_main",
282 .parent_names = (const char *[]){ "gpll2" },
283 .num_parents = 1,
284 .ops = &clk_alpha_pll_postdiv_ops,
285 },
286};
287
288static struct clk_alpha_pll_postdiv gpll2_out_odd = {
289 .offset = 0x2000,
290 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
291 .clkr.hw.init = &(struct clk_init_data){
292 .name = "gpll2_out_odd",
293 .parent_names = (const char *[]){ "gpll2" },
294 .num_parents = 1,
295 .ops = &clk_alpha_pll_postdiv_ops,
296 },
297};
298
299static struct clk_alpha_pll_postdiv gpll2_out_test = {
300 .offset = 0x2000,
301 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
302 .clkr.hw.init = &(struct clk_init_data){
303 .name = "gpll2_out_test",
304 .parent_names = (const char *[]){ "gpll2" },
305 .num_parents = 1,
306 .ops = &clk_alpha_pll_postdiv_ops,
307 },
308};
309
310static struct clk_alpha_pll gpll3 = {
311 .offset = 0x3000,
312 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
313 .vco_table = fabia_vco,
314 .num_vco = ARRAY_SIZE(fabia_vco),
315 .clkr = {
316 .enable_reg = 0x52000,
317 .enable_mask = BIT(3),
318 .hw.init = &(struct clk_init_data){
319 .name = "gpll3",
320 .parent_names = (const char *[]){ "xo" },
321 .num_parents = 1,
322 .ops = &clk_alpha_pll_ops,
323 }
324 },
325};
326
327static struct clk_alpha_pll_postdiv gpll3_out_even = {
328 .offset = 0x3000,
329 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
330 .clkr.hw.init = &(struct clk_init_data){
331 .name = "gpll3_out_even",
332 .parent_names = (const char *[]){ "gpll3" },
333 .num_parents = 1,
334 .ops = &clk_alpha_pll_postdiv_ops,
335 },
336};
337
338static struct clk_alpha_pll_postdiv gpll3_out_main = {
339 .offset = 0x3000,
340 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
341 .clkr.hw.init = &(struct clk_init_data){
342 .name = "gpll3_out_main",
343 .parent_names = (const char *[]){ "gpll3" },
344 .num_parents = 1,
345 .ops = &clk_alpha_pll_postdiv_ops,
346 },
347};
348
349static struct clk_alpha_pll_postdiv gpll3_out_odd = {
350 .offset = 0x3000,
351 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
352 .clkr.hw.init = &(struct clk_init_data){
353 .name = "gpll3_out_odd",
354 .parent_names = (const char *[]){ "gpll3" },
355 .num_parents = 1,
356 .ops = &clk_alpha_pll_postdiv_ops,
357 },
358};
359
360static struct clk_alpha_pll_postdiv gpll3_out_test = {
361 .offset = 0x3000,
362 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
363 .clkr.hw.init = &(struct clk_init_data){
364 .name = "gpll3_out_test",
365 .parent_names = (const char *[]){ "gpll3" },
366 .num_parents = 1,
367 .ops = &clk_alpha_pll_postdiv_ops,
368 },
369};
370
371static struct clk_alpha_pll gpll4 = {
372 .offset = 0x77000,
373 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
374 .vco_table = fabia_vco,
375 .num_vco = ARRAY_SIZE(fabia_vco),
376 .clkr = {
377 .enable_reg = 0x52000,
378 .enable_mask = BIT(4),
379 .hw.init = &(struct clk_init_data){
380 .name = "gpll4",
381 .parent_names = (const char *[]){ "xo" },
382 .num_parents = 1,
383 .ops = &clk_alpha_pll_ops,
384 }
385 },
386};
387
388static struct clk_alpha_pll_postdiv gpll4_out_even = {
389 .offset = 0x77000,
390 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
391 .clkr.hw.init = &(struct clk_init_data){
392 .name = "gpll4_out_even",
393 .parent_names = (const char *[]){ "gpll4" },
394 .num_parents = 1,
395 .ops = &clk_alpha_pll_postdiv_ops,
396 },
397};
398
399static struct clk_alpha_pll_postdiv gpll4_out_main = {
400 .offset = 0x77000,
401 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
402 .clkr.hw.init = &(struct clk_init_data){
403 .name = "gpll4_out_main",
404 .parent_names = (const char *[]){ "gpll4" },
405 .num_parents = 1,
406 .ops = &clk_alpha_pll_postdiv_ops,
407 },
408};
409
410static struct clk_alpha_pll_postdiv gpll4_out_odd = {
411 .offset = 0x77000,
412 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
413 .clkr.hw.init = &(struct clk_init_data){
414 .name = "gpll4_out_odd",
415 .parent_names = (const char *[]){ "gpll4" },
416 .num_parents = 1,
417 .ops = &clk_alpha_pll_postdiv_ops,
418 },
419};
420
421static struct clk_alpha_pll_postdiv gpll4_out_test = {
422 .offset = 0x77000,
423 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
424 .clkr.hw.init = &(struct clk_init_data){
425 .name = "gpll4_out_test",
426 .parent_names = (const char *[]){ "gpll4" },
427 .num_parents = 1,
428 .ops = &clk_alpha_pll_postdiv_ops,
429 },
430};
431
432static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
433 F(19200000, P_XO, 1, 0, 0),
434 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
435 { }
436};
437
438static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
439 .cmd_rcgr = 0x19020,
440 .mnd_width = 0,
441 .hid_width = 5,
442 .parent_map = gcc_parent_map_1,
443 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
444 .clkr.hw.init = &(struct clk_init_data){
445 .name = "blsp1_qup1_i2c_apps_clk_src",
446 .parent_names = gcc_parent_names_1,
447 .num_parents = 3,
448 .ops = &clk_rcg2_ops,
449 },
450};
451
452static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
453 F(960000, P_XO, 10, 1, 2),
454 F(4800000, P_XO, 4, 0, 0),
455 F(9600000, P_XO, 2, 0, 0),
456 F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
457 F(19200000, P_XO, 1, 0, 0),
458 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
459 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
460 { }
461};
462
463static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
464 .cmd_rcgr = 0x1900c,
465 .mnd_width = 8,
466 .hid_width = 5,
467 .parent_map = gcc_parent_map_0,
468 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
469 .clkr.hw.init = &(struct clk_init_data){
470 .name = "blsp1_qup1_spi_apps_clk_src",
471 .parent_names = gcc_parent_names_0,
472 .num_parents = 4,
473 .ops = &clk_rcg2_ops,
474 },
475};
476
477static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
478 .cmd_rcgr = 0x1b020,
479 .mnd_width = 0,
480 .hid_width = 5,
481 .parent_map = gcc_parent_map_1,
482 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
483 .clkr.hw.init = &(struct clk_init_data){
484 .name = "blsp1_qup2_i2c_apps_clk_src",
485 .parent_names = gcc_parent_names_1,
486 .num_parents = 3,
487 .ops = &clk_rcg2_ops,
488 },
489};
490
491static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
492 .cmd_rcgr = 0x1b00c,
493 .mnd_width = 8,
494 .hid_width = 5,
495 .parent_map = gcc_parent_map_0,
496 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
497 .clkr.hw.init = &(struct clk_init_data){
498 .name = "blsp1_qup2_spi_apps_clk_src",
499 .parent_names = gcc_parent_names_0,
500 .num_parents = 4,
501 .ops = &clk_rcg2_ops,
502 },
503};
504
505static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
506 .cmd_rcgr = 0x1d020,
507 .mnd_width = 0,
508 .hid_width = 5,
509 .parent_map = gcc_parent_map_1,
510 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
511 .clkr.hw.init = &(struct clk_init_data){
512 .name = "blsp1_qup3_i2c_apps_clk_src",
513 .parent_names = gcc_parent_names_1,
514 .num_parents = 3,
515 .ops = &clk_rcg2_ops,
516 },
517};
518
519static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
520 .cmd_rcgr = 0x1d00c,
521 .mnd_width = 8,
522 .hid_width = 5,
523 .parent_map = gcc_parent_map_0,
524 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
525 .clkr.hw.init = &(struct clk_init_data){
526 .name = "blsp1_qup3_spi_apps_clk_src",
527 .parent_names = gcc_parent_names_0,
528 .num_parents = 4,
529 .ops = &clk_rcg2_ops,
530 },
531};
532
533static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
534 .cmd_rcgr = 0x1f020,
535 .mnd_width = 0,
536 .hid_width = 5,
537 .parent_map = gcc_parent_map_1,
538 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
539 .clkr.hw.init = &(struct clk_init_data){
540 .name = "blsp1_qup4_i2c_apps_clk_src",
541 .parent_names = gcc_parent_names_1,
542 .num_parents = 3,
543 .ops = &clk_rcg2_ops,
544 },
545};
546
547static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
548 .cmd_rcgr = 0x1f00c,
549 .mnd_width = 8,
550 .hid_width = 5,
551 .parent_map = gcc_parent_map_0,
552 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
553 .clkr.hw.init = &(struct clk_init_data){
554 .name = "blsp1_qup4_spi_apps_clk_src",
555 .parent_names = gcc_parent_names_0,
556 .num_parents = 4,
557 .ops = &clk_rcg2_ops,
558 },
559};
560
561static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
562 .cmd_rcgr = 0x21020,
563 .mnd_width = 0,
564 .hid_width = 5,
565 .parent_map = gcc_parent_map_1,
566 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
567 .clkr.hw.init = &(struct clk_init_data){
568 .name = "blsp1_qup5_i2c_apps_clk_src",
569 .parent_names = gcc_parent_names_1,
570 .num_parents = 3,
571 .ops = &clk_rcg2_ops,
572 },
573};
574
575static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
576 .cmd_rcgr = 0x2100c,
577 .mnd_width = 8,
578 .hid_width = 5,
579 .parent_map = gcc_parent_map_0,
580 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
581 .clkr.hw.init = &(struct clk_init_data){
582 .name = "blsp1_qup5_spi_apps_clk_src",
583 .parent_names = gcc_parent_names_0,
584 .num_parents = 4,
585 .ops = &clk_rcg2_ops,
586 },
587};
588
589static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
590 .cmd_rcgr = 0x23020,
591 .mnd_width = 0,
592 .hid_width = 5,
593 .parent_map = gcc_parent_map_1,
594 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
595 .clkr.hw.init = &(struct clk_init_data){
596 .name = "blsp1_qup6_i2c_apps_clk_src",
597 .parent_names = gcc_parent_names_1,
598 .num_parents = 3,
599 .ops = &clk_rcg2_ops,
600 },
601};
602
603static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
604 .cmd_rcgr = 0x2300c,
605 .mnd_width = 8,
606 .hid_width = 5,
607 .parent_map = gcc_parent_map_0,
608 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
609 .clkr.hw.init = &(struct clk_init_data){
610 .name = "blsp1_qup6_spi_apps_clk_src",
611 .parent_names = gcc_parent_names_0,
612 .num_parents = 4,
613 .ops = &clk_rcg2_ops,
614 },
615};
616
617static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
618 F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625),
619 F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625),
620 F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625),
621 F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15),
622 F(19200000, P_XO, 1, 0, 0),
623 F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5),
624 F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75),
625 F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
626 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375),
627 F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
628 F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375),
629 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75),
630 F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625),
631 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
632 F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
633 { }
634};
635
636static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
637 .cmd_rcgr = 0x1a00c,
638 .mnd_width = 16,
639 .hid_width = 5,
640 .parent_map = gcc_parent_map_0,
641 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
642 .clkr.hw.init = &(struct clk_init_data){
643 .name = "blsp1_uart1_apps_clk_src",
644 .parent_names = gcc_parent_names_0,
645 .num_parents = 4,
646 .ops = &clk_rcg2_ops,
647 },
648};
649
650static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
651 .cmd_rcgr = 0x1c00c,
652 .mnd_width = 16,
653 .hid_width = 5,
654 .parent_map = gcc_parent_map_0,
655 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
656 .clkr.hw.init = &(struct clk_init_data){
657 .name = "blsp1_uart2_apps_clk_src",
658 .parent_names = gcc_parent_names_0,
659 .num_parents = 4,
660 .ops = &clk_rcg2_ops,
661 },
662};
663
664static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
665 .cmd_rcgr = 0x1e00c,
666 .mnd_width = 16,
667 .hid_width = 5,
668 .parent_map = gcc_parent_map_0,
669 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
670 .clkr.hw.init = &(struct clk_init_data){
671 .name = "blsp1_uart3_apps_clk_src",
672 .parent_names = gcc_parent_names_0,
673 .num_parents = 4,
674 .ops = &clk_rcg2_ops,
675 },
676};
677
678static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
679 .cmd_rcgr = 0x26020,
680 .mnd_width = 0,
681 .hid_width = 5,
682 .parent_map = gcc_parent_map_1,
683 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
684 .clkr.hw.init = &(struct clk_init_data){
685 .name = "blsp2_qup1_i2c_apps_clk_src",
686 .parent_names = gcc_parent_names_1,
687 .num_parents = 3,
688 .ops = &clk_rcg2_ops,
689 },
690};
691
692static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
693 .cmd_rcgr = 0x2600c,
694 .mnd_width = 8,
695 .hid_width = 5,
696 .parent_map = gcc_parent_map_0,
697 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
698 .clkr.hw.init = &(struct clk_init_data){
699 .name = "blsp2_qup1_spi_apps_clk_src",
700 .parent_names = gcc_parent_names_0,
701 .num_parents = 4,
702 .ops = &clk_rcg2_ops,
703 },
704};
705
706static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
707 .cmd_rcgr = 0x28020,
708 .mnd_width = 0,
709 .hid_width = 5,
710 .parent_map = gcc_parent_map_1,
711 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
712 .clkr.hw.init = &(struct clk_init_data){
713 .name = "blsp2_qup2_i2c_apps_clk_src",
714 .parent_names = gcc_parent_names_1,
715 .num_parents = 3,
716 .ops = &clk_rcg2_ops,
717 },
718};
719
720static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
721 .cmd_rcgr = 0x2800c,
722 .mnd_width = 8,
723 .hid_width = 5,
724 .parent_map = gcc_parent_map_0,
725 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
726 .clkr.hw.init = &(struct clk_init_data){
727 .name = "blsp2_qup2_spi_apps_clk_src",
728 .parent_names = gcc_parent_names_0,
729 .num_parents = 4,
730 .ops = &clk_rcg2_ops,
731 },
732};
733
734static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
735 .cmd_rcgr = 0x2a020,
736 .mnd_width = 0,
737 .hid_width = 5,
738 .parent_map = gcc_parent_map_1,
739 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
740 .clkr.hw.init = &(struct clk_init_data){
741 .name = "blsp2_qup3_i2c_apps_clk_src",
742 .parent_names = gcc_parent_names_1,
743 .num_parents = 3,
744 .ops = &clk_rcg2_ops,
745 },
746};
747
748static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
749 .cmd_rcgr = 0x2a00c,
750 .mnd_width = 8,
751 .hid_width = 5,
752 .parent_map = gcc_parent_map_0,
753 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
754 .clkr.hw.init = &(struct clk_init_data){
755 .name = "blsp2_qup3_spi_apps_clk_src",
756 .parent_names = gcc_parent_names_0,
757 .num_parents = 4,
758 .ops = &clk_rcg2_ops,
759 },
760};
761
762static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
763 .cmd_rcgr = 0x2c020,
764 .mnd_width = 0,
765 .hid_width = 5,
766 .parent_map = gcc_parent_map_1,
767 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
768 .clkr.hw.init = &(struct clk_init_data){
769 .name = "blsp2_qup4_i2c_apps_clk_src",
770 .parent_names = gcc_parent_names_1,
771 .num_parents = 3,
772 .ops = &clk_rcg2_ops,
773 },
774};
775
776static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
777 .cmd_rcgr = 0x2c00c,
778 .mnd_width = 8,
779 .hid_width = 5,
780 .parent_map = gcc_parent_map_0,
781 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
782 .clkr.hw.init = &(struct clk_init_data){
783 .name = "blsp2_qup4_spi_apps_clk_src",
784 .parent_names = gcc_parent_names_0,
785 .num_parents = 4,
786 .ops = &clk_rcg2_ops,
787 },
788};
789
790static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
791 .cmd_rcgr = 0x2e020,
792 .mnd_width = 0,
793 .hid_width = 5,
794 .parent_map = gcc_parent_map_1,
795 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
796 .clkr.hw.init = &(struct clk_init_data){
797 .name = "blsp2_qup5_i2c_apps_clk_src",
798 .parent_names = gcc_parent_names_1,
799 .num_parents = 3,
800 .ops = &clk_rcg2_ops,
801 },
802};
803
804static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
805 .cmd_rcgr = 0x2e00c,
806 .mnd_width = 8,
807 .hid_width = 5,
808 .parent_map = gcc_parent_map_0,
809 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
810 .clkr.hw.init = &(struct clk_init_data){
811 .name = "blsp2_qup5_spi_apps_clk_src",
812 .parent_names = gcc_parent_names_0,
813 .num_parents = 4,
814 .ops = &clk_rcg2_ops,
815 },
816};
817
818static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
819 .cmd_rcgr = 0x30020,
820 .mnd_width = 0,
821 .hid_width = 5,
822 .parent_map = gcc_parent_map_1,
823 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
824 .clkr.hw.init = &(struct clk_init_data){
825 .name = "blsp2_qup6_i2c_apps_clk_src",
826 .parent_names = gcc_parent_names_1,
827 .num_parents = 3,
828 .ops = &clk_rcg2_ops,
829 },
830};
831
832static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
833 .cmd_rcgr = 0x3000c,
834 .mnd_width = 8,
835 .hid_width = 5,
836 .parent_map = gcc_parent_map_0,
837 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
838 .clkr.hw.init = &(struct clk_init_data){
839 .name = "blsp2_qup6_spi_apps_clk_src",
840 .parent_names = gcc_parent_names_0,
841 .num_parents = 4,
842 .ops = &clk_rcg2_ops,
843 },
844};
845
846static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
847 .cmd_rcgr = 0x2700c,
848 .mnd_width = 16,
849 .hid_width = 5,
850 .parent_map = gcc_parent_map_0,
851 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
852 .clkr.hw.init = &(struct clk_init_data){
853 .name = "blsp2_uart1_apps_clk_src",
854 .parent_names = gcc_parent_names_0,
855 .num_parents = 4,
856 .ops = &clk_rcg2_ops,
857 },
858};
859
860static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
861 .cmd_rcgr = 0x2900c,
862 .mnd_width = 16,
863 .hid_width = 5,
864 .parent_map = gcc_parent_map_0,
865 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
866 .clkr.hw.init = &(struct clk_init_data){
867 .name = "blsp2_uart2_apps_clk_src",
868 .parent_names = gcc_parent_names_0,
869 .num_parents = 4,
870 .ops = &clk_rcg2_ops,
871 },
872};
873
874static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
875 .cmd_rcgr = 0x2b00c,
876 .mnd_width = 16,
877 .hid_width = 5,
878 .parent_map = gcc_parent_map_0,
879 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
880 .clkr.hw.init = &(struct clk_init_data){
881 .name = "blsp2_uart3_apps_clk_src",
882 .parent_names = gcc_parent_names_0,
883 .num_parents = 4,
884 .ops = &clk_rcg2_ops,
885 },
886};
887
888static const struct freq_tbl ftbl_gp1_clk_src[] = {
889 F(19200000, P_XO, 1, 0, 0),
890 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
891 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
892 { }
893};
894
895static struct clk_rcg2 gp1_clk_src = {
896 .cmd_rcgr = 0x64004,
897 .mnd_width = 8,
898 .hid_width = 5,
899 .parent_map = gcc_parent_map_2,
900 .freq_tbl = ftbl_gp1_clk_src,
901 .clkr.hw.init = &(struct clk_init_data){
902 .name = "gp1_clk_src",
903 .parent_names = gcc_parent_names_2,
904 .num_parents = 5,
905 .ops = &clk_rcg2_ops,
906 },
907};
908
909static struct clk_rcg2 gp2_clk_src = {
910 .cmd_rcgr = 0x65004,
911 .mnd_width = 8,
912 .hid_width = 5,
913 .parent_map = gcc_parent_map_2,
914 .freq_tbl = ftbl_gp1_clk_src,
915 .clkr.hw.init = &(struct clk_init_data){
916 .name = "gp2_clk_src",
917 .parent_names = gcc_parent_names_2,
918 .num_parents = 5,
919 .ops = &clk_rcg2_ops,
920 },
921};
922
923static struct clk_rcg2 gp3_clk_src = {
924 .cmd_rcgr = 0x66004,
925 .mnd_width = 8,
926 .hid_width = 5,
927 .parent_map = gcc_parent_map_2,
928 .freq_tbl = ftbl_gp1_clk_src,
929 .clkr.hw.init = &(struct clk_init_data){
930 .name = "gp3_clk_src",
931 .parent_names = gcc_parent_names_2,
932 .num_parents = 5,
933 .ops = &clk_rcg2_ops,
934 },
935};
936
937static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = {
938 F(19200000, P_XO, 1, 0, 0),
939 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
940 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
941 { }
942};
943
944static struct clk_rcg2 hmss_ahb_clk_src = {
945 .cmd_rcgr = 0x48014,
946 .mnd_width = 0,
947 .hid_width = 5,
948 .parent_map = gcc_parent_map_1,
949 .freq_tbl = ftbl_hmss_ahb_clk_src,
950 .clkr.hw.init = &(struct clk_init_data){
951 .name = "hmss_ahb_clk_src",
952 .parent_names = gcc_parent_names_1,
953 .num_parents = 3,
954 .ops = &clk_rcg2_ops,
955 },
956};
957
958static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
959 F(19200000, P_XO, 1, 0, 0),
960 { }
961};
962
963static struct clk_rcg2 hmss_rbcpr_clk_src = {
964 .cmd_rcgr = 0x48044,
965 .mnd_width = 0,
966 .hid_width = 5,
967 .parent_map = gcc_parent_map_1,
968 .freq_tbl = ftbl_hmss_rbcpr_clk_src,
969 .clkr.hw.init = &(struct clk_init_data){
970 .name = "hmss_rbcpr_clk_src",
971 .parent_names = gcc_parent_names_1,
972 .num_parents = 3,
973 .ops = &clk_rcg2_ops,
974 },
975};
976
977static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
978 F(1010526, P_XO, 1, 1, 19),
979 { }
980};
981
982static struct clk_rcg2 pcie_aux_clk_src = {
983 .cmd_rcgr = 0x6c000,
984 .mnd_width = 16,
985 .hid_width = 5,
986 .parent_map = gcc_parent_map_3,
987 .freq_tbl = ftbl_pcie_aux_clk_src,
988 .clkr.hw.init = &(struct clk_init_data){
989 .name = "pcie_aux_clk_src",
990 .parent_names = gcc_parent_names_3,
991 .num_parents = 3,
992 .ops = &clk_rcg2_ops,
993 },
994};
995
996static const struct freq_tbl ftbl_pdm2_clk_src[] = {
997 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
998 { }
999};
1000
1001static struct clk_rcg2 pdm2_clk_src = {
1002 .cmd_rcgr = 0x33010,
1003 .mnd_width = 0,
1004 .hid_width = 5,
1005 .parent_map = gcc_parent_map_1,
1006 .freq_tbl = ftbl_pdm2_clk_src,
1007 .clkr.hw.init = &(struct clk_init_data){
1008 .name = "pdm2_clk_src",
1009 .parent_names = gcc_parent_names_1,
1010 .num_parents = 3,
1011 .ops = &clk_rcg2_ops,
1012 },
1013};
1014
1015static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
1016 F(144000, P_XO, 16, 3, 25),
1017 F(400000, P_XO, 12, 1, 4),
1018 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
1019 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
1020 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1021 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1022 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1023 { }
1024};
1025
1026static struct clk_rcg2 sdcc2_apps_clk_src = {
1027 .cmd_rcgr = 0x14010,
1028 .mnd_width = 8,
1029 .hid_width = 5,
1030 .parent_map = gcc_parent_map_4,
1031 .freq_tbl = ftbl_sdcc2_apps_clk_src,
1032 .clkr.hw.init = &(struct clk_init_data){
1033 .name = "sdcc2_apps_clk_src",
1034 .parent_names = gcc_parent_names_4,
1035 .num_parents = 4,
1036 .ops = &clk_rcg2_ops,
1037 },
1038};
1039
1040static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
1041 F(144000, P_XO, 16, 3, 25),
1042 F(400000, P_XO, 12, 1, 4),
1043 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
1044 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
1045 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1046 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1047 { }
1048};
1049
1050static struct clk_rcg2 sdcc4_apps_clk_src = {
1051 .cmd_rcgr = 0x16010,
1052 .mnd_width = 8,
1053 .hid_width = 5,
1054 .parent_map = gcc_parent_map_1,
1055 .freq_tbl = ftbl_sdcc4_apps_clk_src,
1056 .clkr.hw.init = &(struct clk_init_data){
1057 .name = "sdcc4_apps_clk_src",
1058 .parent_names = gcc_parent_names_1,
1059 .num_parents = 3,
1060 .ops = &clk_rcg2_ops,
1061 },
1062};
1063
1064static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1065 F(105495, P_XO, 1, 1, 182),
1066 { }
1067};
1068
1069static struct clk_rcg2 tsif_ref_clk_src = {
1070 .cmd_rcgr = 0x36010,
1071 .mnd_width = 8,
1072 .hid_width = 5,
1073 .parent_map = gcc_parent_map_5,
1074 .freq_tbl = ftbl_tsif_ref_clk_src,
1075 .clkr.hw.init = &(struct clk_init_data){
1076 .name = "tsif_ref_clk_src",
1077 .parent_names = gcc_parent_names_5,
1078 .num_parents = 4,
1079 .ops = &clk_rcg2_ops,
1080 },
1081};
1082
1083static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
1084 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1085 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1086 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1087 { }
1088};
1089
1090static struct clk_rcg2 ufs_axi_clk_src = {
1091 .cmd_rcgr = 0x75018,
1092 .mnd_width = 8,
1093 .hid_width = 5,
1094 .parent_map = gcc_parent_map_0,
1095 .freq_tbl = ftbl_ufs_axi_clk_src,
1096 .clkr.hw.init = &(struct clk_init_data){
1097 .name = "ufs_axi_clk_src",
1098 .parent_names = gcc_parent_names_0,
1099 .num_parents = 4,
1100 .ops = &clk_rcg2_ops,
1101 },
1102};
1103
1104static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
1105 F(19200000, P_XO, 1, 0, 0),
1106 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1107 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1108 { }
1109};
1110
1111static struct clk_rcg2 usb30_master_clk_src = {
1112 .cmd_rcgr = 0xf014,
1113 .mnd_width = 8,
1114 .hid_width = 5,
1115 .parent_map = gcc_parent_map_0,
1116 .freq_tbl = ftbl_usb30_master_clk_src,
1117 .clkr.hw.init = &(struct clk_init_data){
1118 .name = "usb30_master_clk_src",
1119 .parent_names = gcc_parent_names_0,
1120 .num_parents = 4,
1121 .ops = &clk_rcg2_ops,
1122 },
1123};
1124
1125static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1126 .cmd_rcgr = 0xf028,
1127 .mnd_width = 0,
1128 .hid_width = 5,
1129 .parent_map = gcc_parent_map_0,
1130 .freq_tbl = ftbl_hmss_rbcpr_clk_src,
1131 .clkr.hw.init = &(struct clk_init_data){
1132 .name = "usb30_mock_utmi_clk_src",
1133 .parent_names = gcc_parent_names_0,
1134 .num_parents = 4,
1135 .ops = &clk_rcg2_ops,
1136 },
1137};
1138
1139static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1140 F(1200000, P_XO, 16, 0, 0),
1141 { }
1142};
1143
1144static struct clk_rcg2 usb3_phy_aux_clk_src = {
1145 .cmd_rcgr = 0x5000c,
1146 .mnd_width = 0,
1147 .hid_width = 5,
1148 .parent_map = gcc_parent_map_3,
1149 .freq_tbl = ftbl_usb3_phy_aux_clk_src,
1150 .clkr.hw.init = &(struct clk_init_data){
1151 .name = "usb3_phy_aux_clk_src",
1152 .parent_names = gcc_parent_names_3,
1153 .num_parents = 3,
1154 .ops = &clk_rcg2_ops,
1155 },
1156};
1157
1158static struct clk_branch gcc_aggre1_noc_xo_clk = {
1159 .halt_reg = 0x8202c,
1160 .halt_check = BRANCH_HALT,
1161 .clkr = {
1162 .enable_reg = 0x8202c,
1163 .enable_mask = BIT(0),
1164 .hw.init = &(struct clk_init_data){
1165 .name = "gcc_aggre1_noc_xo_clk",
1166 .ops = &clk_branch2_ops,
1167 },
1168 },
1169};
1170
1171static struct clk_branch gcc_aggre1_ufs_axi_clk = {
1172 .halt_reg = 0x82028,
1173 .halt_check = BRANCH_HALT,
1174 .clkr = {
1175 .enable_reg = 0x82028,
1176 .enable_mask = BIT(0),
1177 .hw.init = &(struct clk_init_data){
1178 .name = "gcc_aggre1_ufs_axi_clk",
1179 .parent_names = (const char *[]){
1180 "ufs_axi_clk_src",
1181 },
1182 .num_parents = 1,
1183 .ops = &clk_branch2_ops,
1184 },
1185 },
1186};
1187
1188static struct clk_branch gcc_aggre1_usb3_axi_clk = {
1189 .halt_reg = 0x82024,
1190 .halt_check = BRANCH_HALT,
1191 .clkr = {
1192 .enable_reg = 0x82024,
1193 .enable_mask = BIT(0),
1194 .hw.init = &(struct clk_init_data){
1195 .name = "gcc_aggre1_usb3_axi_clk",
1196 .parent_names = (const char *[]){
1197 "usb30_master_clk_src",
1198 },
1199 .num_parents = 1,
1200 .ops = &clk_branch2_ops,
1201 },
1202 },
1203};
1204
1205static struct clk_branch gcc_apss_qdss_tsctr_div2_clk = {
1206 .halt_reg = 0x48090,
1207 .halt_check = BRANCH_HALT,
1208 .clkr = {
1209 .enable_reg = 0x48090,
1210 .enable_mask = BIT(0),
1211 .hw.init = &(struct clk_init_data){
1212 .name = "gcc_apss_qdss_tsctr_div2_clk",
1213 .ops = &clk_branch2_ops,
1214 },
1215 },
1216};
1217
1218static struct clk_branch gcc_apss_qdss_tsctr_div8_clk = {
1219 .halt_reg = 0x48094,
1220 .halt_check = BRANCH_HALT,
1221 .clkr = {
1222 .enable_reg = 0x48094,
1223 .enable_mask = BIT(0),
1224 .hw.init = &(struct clk_init_data){
1225 .name = "gcc_apss_qdss_tsctr_div8_clk",
1226 .ops = &clk_branch2_ops,
1227 },
1228 },
1229};
1230
1231static struct clk_branch gcc_bimc_hmss_axi_clk = {
1232 .halt_reg = 0x48004,
1233 .halt_check = BRANCH_HALT_VOTED,
1234 .clkr = {
1235 .enable_reg = 0x52004,
1236 .enable_mask = BIT(22),
1237 .hw.init = &(struct clk_init_data){
1238 .name = "gcc_bimc_hmss_axi_clk",
1239 .ops = &clk_branch2_ops,
1240 },
1241 },
1242};
1243
1244static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
1245 .halt_reg = 0x4401c,
1246 .halt_check = BRANCH_HALT,
1247 .clkr = {
1248 .enable_reg = 0x4401c,
1249 .enable_mask = BIT(0),
1250 .hw.init = &(struct clk_init_data){
1251 .name = "gcc_bimc_mss_q6_axi_clk",
1252 .ops = &clk_branch2_ops,
1253 },
1254 },
1255};
1256
1257static struct clk_branch gcc_blsp1_ahb_clk = {
1258 .halt_reg = 0x17004,
1259 .halt_check = BRANCH_HALT_VOTED,
1260 .clkr = {
1261 .enable_reg = 0x52004,
1262 .enable_mask = BIT(17),
1263 .hw.init = &(struct clk_init_data){
1264 .name = "gcc_blsp1_ahb_clk",
1265 .ops = &clk_branch2_ops,
1266 },
1267 },
1268};
1269
1270static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1271 .halt_reg = 0x19008,
1272 .halt_check = BRANCH_HALT,
1273 .clkr = {
1274 .enable_reg = 0x19008,
1275 .enable_mask = BIT(0),
1276 .hw.init = &(struct clk_init_data){
1277 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1278 .parent_names = (const char *[]){
1279 "blsp1_qup1_i2c_apps_clk_src",
1280 },
1281 .num_parents = 1,
1282 .ops = &clk_branch2_ops,
1283 },
1284 },
1285};
1286
1287static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1288 .halt_reg = 0x19004,
1289 .halt_check = BRANCH_HALT,
1290 .clkr = {
1291 .enable_reg = 0x19004,
1292 .enable_mask = BIT(0),
1293 .hw.init = &(struct clk_init_data){
1294 .name = "gcc_blsp1_qup1_spi_apps_clk",
1295 .parent_names = (const char *[]){
1296 "blsp1_qup1_spi_apps_clk_src",
1297 },
1298 .num_parents = 1,
1299 .ops = &clk_branch2_ops,
1300 },
1301 },
1302};
1303
1304static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1305 .halt_reg = 0x1b008,
1306 .halt_check = BRANCH_HALT,
1307 .clkr = {
1308 .enable_reg = 0x1b008,
1309 .enable_mask = BIT(0),
1310 .hw.init = &(struct clk_init_data){
1311 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1312 .parent_names = (const char *[]){
1313 "blsp1_qup2_i2c_apps_clk_src",
1314 },
1315 .num_parents = 1,
1316 .ops = &clk_branch2_ops,
1317 },
1318 },
1319};
1320
1321static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1322 .halt_reg = 0x1b004,
1323 .halt_check = BRANCH_HALT,
1324 .clkr = {
1325 .enable_reg = 0x1b004,
1326 .enable_mask = BIT(0),
1327 .hw.init = &(struct clk_init_data){
1328 .name = "gcc_blsp1_qup2_spi_apps_clk",
1329 .parent_names = (const char *[]){
1330 "blsp1_qup2_spi_apps_clk_src",
1331 },
1332 .num_parents = 1,
1333 .ops = &clk_branch2_ops,
1334 },
1335 },
1336};
1337
1338static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1339 .halt_reg = 0x1d008,
1340 .halt_check = BRANCH_HALT,
1341 .clkr = {
1342 .enable_reg = 0x1d008,
1343 .enable_mask = BIT(0),
1344 .hw.init = &(struct clk_init_data){
1345 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1346 .parent_names = (const char *[]){
1347 "blsp1_qup3_i2c_apps_clk_src",
1348 },
1349 .num_parents = 1,
1350 .ops = &clk_branch2_ops,
1351 },
1352 },
1353};
1354
1355static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1356 .halt_reg = 0x1d004,
1357 .halt_check = BRANCH_HALT,
1358 .clkr = {
1359 .enable_reg = 0x1d004,
1360 .enable_mask = BIT(0),
1361 .hw.init = &(struct clk_init_data){
1362 .name = "gcc_blsp1_qup3_spi_apps_clk",
1363 .parent_names = (const char *[]){
1364 "blsp1_qup3_spi_apps_clk_src",
1365 },
1366 .num_parents = 1,
1367 .ops = &clk_branch2_ops,
1368 },
1369 },
1370};
1371
1372static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1373 .halt_reg = 0x1f008,
1374 .halt_check = BRANCH_HALT,
1375 .clkr = {
1376 .enable_reg = 0x1f008,
1377 .enable_mask = BIT(0),
1378 .hw.init = &(struct clk_init_data){
1379 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1380 .parent_names = (const char *[]){
1381 "blsp1_qup4_i2c_apps_clk_src",
1382 },
1383 .num_parents = 1,
1384 .ops = &clk_branch2_ops,
1385 },
1386 },
1387};
1388
1389static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1390 .halt_reg = 0x1f004,
1391 .halt_check = BRANCH_HALT,
1392 .clkr = {
1393 .enable_reg = 0x1f004,
1394 .enable_mask = BIT(0),
1395 .hw.init = &(struct clk_init_data){
1396 .name = "gcc_blsp1_qup4_spi_apps_clk",
1397 .parent_names = (const char *[]){
1398 "blsp1_qup4_spi_apps_clk_src",
1399 },
1400 .num_parents = 1,
1401 .ops = &clk_branch2_ops,
1402 },
1403 },
1404};
1405
1406static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1407 .halt_reg = 0x21008,
1408 .halt_check = BRANCH_HALT,
1409 .clkr = {
1410 .enable_reg = 0x21008,
1411 .enable_mask = BIT(0),
1412 .hw.init = &(struct clk_init_data){
1413 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1414 .parent_names = (const char *[]){
1415 "blsp1_qup5_i2c_apps_clk_src",
1416 },
1417 .num_parents = 1,
1418 .ops = &clk_branch2_ops,
1419 },
1420 },
1421};
1422
1423static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1424 .halt_reg = 0x21004,
1425 .halt_check = BRANCH_HALT,
1426 .clkr = {
1427 .enable_reg = 0x21004,
1428 .enable_mask = BIT(0),
1429 .hw.init = &(struct clk_init_data){
1430 .name = "gcc_blsp1_qup5_spi_apps_clk",
1431 .parent_names = (const char *[]){
1432 "blsp1_qup5_spi_apps_clk_src",
1433 },
1434 .num_parents = 1,
1435 .ops = &clk_branch2_ops,
1436 },
1437 },
1438};
1439
1440static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1441 .halt_reg = 0x23008,
1442 .halt_check = BRANCH_HALT,
1443 .clkr = {
1444 .enable_reg = 0x23008,
1445 .enable_mask = BIT(0),
1446 .hw.init = &(struct clk_init_data){
1447 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1448 .parent_names = (const char *[]){
1449 "blsp1_qup6_i2c_apps_clk_src",
1450 },
1451 .num_parents = 1,
1452 .ops = &clk_branch2_ops,
1453 },
1454 },
1455};
1456
1457static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1458 .halt_reg = 0x23004,
1459 .halt_check = BRANCH_HALT,
1460 .clkr = {
1461 .enable_reg = 0x23004,
1462 .enable_mask = BIT(0),
1463 .hw.init = &(struct clk_init_data){
1464 .name = "gcc_blsp1_qup6_spi_apps_clk",
1465 .parent_names = (const char *[]){
1466 "blsp1_qup6_spi_apps_clk_src",
1467 },
1468 .num_parents = 1,
1469 .ops = &clk_branch2_ops,
1470 },
1471 },
1472};
1473
1474static struct clk_branch gcc_blsp1_sleep_clk = {
1475 .halt_reg = 0x17008,
1476 .halt_check = BRANCH_HALT_VOTED,
1477 .clkr = {
1478 .enable_reg = 0x52004,
1479 .enable_mask = BIT(16),
1480 .hw.init = &(struct clk_init_data){
1481 .name = "gcc_blsp1_sleep_clk",
1482 .ops = &clk_branch2_ops,
1483 },
1484 },
1485};
1486
1487static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1488 .halt_reg = 0x1a004,
1489 .halt_check = BRANCH_HALT,
1490 .clkr = {
1491 .enable_reg = 0x1a004,
1492 .enable_mask = BIT(0),
1493 .hw.init = &(struct clk_init_data){
1494 .name = "gcc_blsp1_uart1_apps_clk",
1495 .parent_names = (const char *[]){
1496 "blsp1_uart1_apps_clk_src",
1497 },
1498 .num_parents = 1,
1499 .ops = &clk_branch2_ops,
1500 },
1501 },
1502};
1503
1504static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1505 .halt_reg = 0x1c004,
1506 .halt_check = BRANCH_HALT,
1507 .clkr = {
1508 .enable_reg = 0x1c004,
1509 .enable_mask = BIT(0),
1510 .hw.init = &(struct clk_init_data){
1511 .name = "gcc_blsp1_uart2_apps_clk",
1512 .parent_names = (const char *[]){
1513 "blsp1_uart2_apps_clk_src",
1514 },
1515 .num_parents = 1,
1516 .ops = &clk_branch2_ops,
1517 },
1518 },
1519};
1520
1521static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1522 .halt_reg = 0x1e004,
1523 .halt_check = BRANCH_HALT,
1524 .clkr = {
1525 .enable_reg = 0x1e004,
1526 .enable_mask = BIT(0),
1527 .hw.init = &(struct clk_init_data){
1528 .name = "gcc_blsp1_uart3_apps_clk",
1529 .parent_names = (const char *[]){
1530 "blsp1_uart3_apps_clk_src",
1531 },
1532 .num_parents = 1,
1533 .ops = &clk_branch2_ops,
1534 },
1535 },
1536};
1537
1538static struct clk_branch gcc_blsp2_ahb_clk = {
1539 .halt_reg = 0x25004,
1540 .halt_check = BRANCH_HALT_VOTED,
1541 .clkr = {
1542 .enable_reg = 0x52004,
1543 .enable_mask = BIT(15),
1544 .hw.init = &(struct clk_init_data){
1545 .name = "gcc_blsp2_ahb_clk",
1546 .ops = &clk_branch2_ops,
1547 },
1548 },
1549};
1550
1551static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1552 .halt_reg = 0x26008,
1553 .halt_check = BRANCH_HALT,
1554 .clkr = {
1555 .enable_reg = 0x26008,
1556 .enable_mask = BIT(0),
1557 .hw.init = &(struct clk_init_data){
1558 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1559 .parent_names = (const char *[]){
1560 "blsp2_qup1_i2c_apps_clk_src",
1561 },
1562 .num_parents = 1,
1563 .ops = &clk_branch2_ops,
1564 },
1565 },
1566};
1567
1568static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1569 .halt_reg = 0x26004,
1570 .halt_check = BRANCH_HALT,
1571 .clkr = {
1572 .enable_reg = 0x26004,
1573 .enable_mask = BIT(0),
1574 .hw.init = &(struct clk_init_data){
1575 .name = "gcc_blsp2_qup1_spi_apps_clk",
1576 .parent_names = (const char *[]){
1577 "blsp2_qup1_spi_apps_clk_src",
1578 },
1579 .num_parents = 1,
1580 .ops = &clk_branch2_ops,
1581 },
1582 },
1583};
1584
1585static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1586 .halt_reg = 0x28008,
1587 .halt_check = BRANCH_HALT,
1588 .clkr = {
1589 .enable_reg = 0x28008,
1590 .enable_mask = BIT(0),
1591 .hw.init = &(struct clk_init_data){
1592 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1593 .parent_names = (const char *[]){
1594 "blsp2_qup2_i2c_apps_clk_src",
1595 },
1596 .num_parents = 1,
1597 .ops = &clk_branch2_ops,
1598 },
1599 },
1600};
1601
1602static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1603 .halt_reg = 0x28004,
1604 .halt_check = BRANCH_HALT,
1605 .clkr = {
1606 .enable_reg = 0x28004,
1607 .enable_mask = BIT(0),
1608 .hw.init = &(struct clk_init_data){
1609 .name = "gcc_blsp2_qup2_spi_apps_clk",
1610 .parent_names = (const char *[]){
1611 "blsp2_qup2_spi_apps_clk_src",
1612 },
1613 .num_parents = 1,
1614 .ops = &clk_branch2_ops,
1615 },
1616 },
1617};
1618
1619static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1620 .halt_reg = 0x2a008,
1621 .halt_check = BRANCH_HALT,
1622 .clkr = {
1623 .enable_reg = 0x2a008,
1624 .enable_mask = BIT(0),
1625 .hw.init = &(struct clk_init_data){
1626 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1627 .parent_names = (const char *[]){
1628 "blsp2_qup3_i2c_apps_clk_src",
1629 },
1630 .num_parents = 1,
1631 .ops = &clk_branch2_ops,
1632 },
1633 },
1634};
1635
1636static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1637 .halt_reg = 0x2a004,
1638 .halt_check = BRANCH_HALT,
1639 .clkr = {
1640 .enable_reg = 0x2a004,
1641 .enable_mask = BIT(0),
1642 .hw.init = &(struct clk_init_data){
1643 .name = "gcc_blsp2_qup3_spi_apps_clk",
1644 .parent_names = (const char *[]){
1645 "blsp2_qup3_spi_apps_clk_src",
1646 },
1647 .num_parents = 1,
1648 .ops = &clk_branch2_ops,
1649 },
1650 },
1651};
1652
1653static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1654 .halt_reg = 0x2c008,
1655 .halt_check = BRANCH_HALT,
1656 .clkr = {
1657 .enable_reg = 0x2c008,
1658 .enable_mask = BIT(0),
1659 .hw.init = &(struct clk_init_data){
1660 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1661 .parent_names = (const char *[]){
1662 "blsp2_qup4_i2c_apps_clk_src",
1663 },
1664 .num_parents = 1,
1665 .ops = &clk_branch2_ops,
1666 },
1667 },
1668};
1669
1670static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1671 .halt_reg = 0x2c004,
1672 .halt_check = BRANCH_HALT,
1673 .clkr = {
1674 .enable_reg = 0x2c004,
1675 .enable_mask = BIT(0),
1676 .hw.init = &(struct clk_init_data){
1677 .name = "gcc_blsp2_qup4_spi_apps_clk",
1678 .parent_names = (const char *[]){
1679 "blsp2_qup4_spi_apps_clk_src",
1680 },
1681 .num_parents = 1,
1682 .ops = &clk_branch2_ops,
1683 },
1684 },
1685};
1686
1687static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1688 .halt_reg = 0x2e008,
1689 .halt_check = BRANCH_HALT,
1690 .clkr = {
1691 .enable_reg = 0x2e008,
1692 .enable_mask = BIT(0),
1693 .hw.init = &(struct clk_init_data){
1694 .name = "gcc_blsp2_qup5_i2c_apps_clk",
1695 .parent_names = (const char *[]){
1696 "blsp2_qup5_i2c_apps_clk_src",
1697 },
1698 .num_parents = 1,
1699 .ops = &clk_branch2_ops,
1700 },
1701 },
1702};
1703
1704static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1705 .halt_reg = 0x2e004,
1706 .halt_check = BRANCH_HALT,
1707 .clkr = {
1708 .enable_reg = 0x2e004,
1709 .enable_mask = BIT(0),
1710 .hw.init = &(struct clk_init_data){
1711 .name = "gcc_blsp2_qup5_spi_apps_clk",
1712 .parent_names = (const char *[]){
1713 "blsp2_qup5_spi_apps_clk_src",
1714 },
1715 .num_parents = 1,
1716 .ops = &clk_branch2_ops,
1717 },
1718 },
1719};
1720
1721static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1722 .halt_reg = 0x30008,
1723 .halt_check = BRANCH_HALT,
1724 .clkr = {
1725 .enable_reg = 0x30008,
1726 .enable_mask = BIT(0),
1727 .hw.init = &(struct clk_init_data){
1728 .name = "gcc_blsp2_qup6_i2c_apps_clk",
1729 .parent_names = (const char *[]){
1730 "blsp2_qup6_i2c_apps_clk_src",
1731 },
1732 .num_parents = 1,
1733 .ops = &clk_branch2_ops,
1734 },
1735 },
1736};
1737
1738static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1739 .halt_reg = 0x30004,
1740 .halt_check = BRANCH_HALT,
1741 .clkr = {
1742 .enable_reg = 0x30004,
1743 .enable_mask = BIT(0),
1744 .hw.init = &(struct clk_init_data){
1745 .name = "gcc_blsp2_qup6_spi_apps_clk",
1746 .parent_names = (const char *[]){
1747 "blsp2_qup6_spi_apps_clk_src",
1748 },
1749 .num_parents = 1,
1750 .ops = &clk_branch2_ops,
1751 },
1752 },
1753};
1754
1755static struct clk_branch gcc_blsp2_sleep_clk = {
1756 .halt_reg = 0x25008,
1757 .halt_check = BRANCH_HALT_VOTED,
1758 .clkr = {
1759 .enable_reg = 0x52004,
1760 .enable_mask = BIT(14),
1761 .hw.init = &(struct clk_init_data){
1762 .name = "gcc_blsp2_sleep_clk",
1763 .ops = &clk_branch2_ops,
1764 },
1765 },
1766};
1767
1768static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1769 .halt_reg = 0x27004,
1770 .halt_check = BRANCH_HALT,
1771 .clkr = {
1772 .enable_reg = 0x27004,
1773 .enable_mask = BIT(0),
1774 .hw.init = &(struct clk_init_data){
1775 .name = "gcc_blsp2_uart1_apps_clk",
1776 .parent_names = (const char *[]){
1777 "blsp2_uart1_apps_clk_src",
1778 },
1779 .num_parents = 1,
1780 .ops = &clk_branch2_ops,
1781 },
1782 },
1783};
1784
1785static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1786 .halt_reg = 0x29004,
1787 .halt_check = BRANCH_HALT,
1788 .clkr = {
1789 .enable_reg = 0x29004,
1790 .enable_mask = BIT(0),
1791 .hw.init = &(struct clk_init_data){
1792 .name = "gcc_blsp2_uart2_apps_clk",
1793 .parent_names = (const char *[]){
1794 "blsp2_uart2_apps_clk_src",
1795 },
1796 .num_parents = 1,
1797 .ops = &clk_branch2_ops,
1798 },
1799 },
1800};
1801
1802static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1803 .halt_reg = 0x2b004,
1804 .halt_check = BRANCH_HALT,
1805 .clkr = {
1806 .enable_reg = 0x2b004,
1807 .enable_mask = BIT(0),
1808 .hw.init = &(struct clk_init_data){
1809 .name = "gcc_blsp2_uart3_apps_clk",
1810 .parent_names = (const char *[]){
1811 "blsp2_uart3_apps_clk_src",
1812 },
1813 .num_parents = 1,
1814 .ops = &clk_branch2_ops,
1815 },
1816 },
1817};
1818
1819static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
1820 .halt_reg = 0x5018,
1821 .halt_check = BRANCH_HALT,
1822 .clkr = {
1823 .enable_reg = 0x5018,
1824 .enable_mask = BIT(0),
1825 .hw.init = &(struct clk_init_data){
1826 .name = "gcc_cfg_noc_usb3_axi_clk",
1827 .parent_names = (const char *[]){
1828 "usb30_master_clk_src",
1829 },
1830 .num_parents = 1,
1831 .ops = &clk_branch2_ops,
1832 },
1833 },
1834};
1835
1836static struct clk_branch gcc_gp1_clk = {
1837 .halt_reg = 0x64000,
1838 .halt_check = BRANCH_HALT,
1839 .clkr = {
1840 .enable_reg = 0x64000,
1841 .enable_mask = BIT(0),
1842 .hw.init = &(struct clk_init_data){
1843 .name = "gcc_gp1_clk",
1844 .parent_names = (const char *[]){
1845 "gp1_clk_src",
1846 },
1847 .num_parents = 1,
1848 .ops = &clk_branch2_ops,
1849 },
1850 },
1851};
1852
1853static struct clk_branch gcc_gp2_clk = {
1854 .halt_reg = 0x65000,
1855 .halt_check = BRANCH_HALT,
1856 .clkr = {
1857 .enable_reg = 0x65000,
1858 .enable_mask = BIT(0),
1859 .hw.init = &(struct clk_init_data){
1860 .name = "gcc_gp2_clk",
1861 .parent_names = (const char *[]){
1862 "gp2_clk_src",
1863 },
1864 .num_parents = 1,
1865 .ops = &clk_branch2_ops,
1866 },
1867 },
1868};
1869
1870static struct clk_branch gcc_gp3_clk = {
1871 .halt_reg = 0x66000,
1872 .halt_check = BRANCH_HALT,
1873 .clkr = {
1874 .enable_reg = 0x66000,
1875 .enable_mask = BIT(0),
1876 .hw.init = &(struct clk_init_data){
1877 .name = "gcc_gp3_clk",
1878 .parent_names = (const char *[]){
1879 "gp3_clk_src",
1880 },
1881 .num_parents = 1,
1882 .ops = &clk_branch2_ops,
1883 },
1884 },
1885};
1886
1887static struct clk_branch gcc_gpu_bimc_gfx_clk = {
1888 .halt_reg = 0x71010,
1889 .halt_check = BRANCH_HALT,
1890 .clkr = {
1891 .enable_reg = 0x71010,
1892 .enable_mask = BIT(0),
1893 .hw.init = &(struct clk_init_data){
1894 .name = "gcc_gpu_bimc_gfx_clk",
1895 .ops = &clk_branch2_ops,
1896 },
1897 },
1898};
1899
1900static struct clk_branch gcc_gpu_bimc_gfx_src_clk = {
1901 .halt_reg = 0x7100c,
1902 .halt_check = BRANCH_HALT,
1903 .clkr = {
1904 .enable_reg = 0x7100c,
1905 .enable_mask = BIT(0),
1906 .hw.init = &(struct clk_init_data){
1907 .name = "gcc_gpu_bimc_gfx_src_clk",
1908 .ops = &clk_branch2_ops,
1909 },
1910 },
1911};
1912
1913static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1914 .halt_reg = 0x71004,
1915 .halt_check = BRANCH_HALT,
1916 .clkr = {
1917 .enable_reg = 0x71004,
1918 .enable_mask = BIT(0),
1919 .hw.init = &(struct clk_init_data){
1920 .name = "gcc_gpu_cfg_ahb_clk",
1921 .ops = &clk_branch2_ops,
1922 },
1923 },
1924};
1925
1926static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1927 .halt_reg = 0x71018,
1928 .halt_check = BRANCH_HALT,
1929 .clkr = {
1930 .enable_reg = 0x71018,
1931 .enable_mask = BIT(0),
1932 .hw.init = &(struct clk_init_data){
1933 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1934 .ops = &clk_branch2_ops,
1935 },
1936 },
1937};
1938
1939static struct clk_branch gcc_hmss_ahb_clk = {
1940 .halt_reg = 0x48000,
1941 .halt_check = BRANCH_HALT_VOTED,
1942 .clkr = {
1943 .enable_reg = 0x52004,
1944 .enable_mask = BIT(21),
1945 .hw.init = &(struct clk_init_data){
1946 .name = "gcc_hmss_ahb_clk",
1947 .parent_names = (const char *[]){
1948 "hmss_ahb_clk_src",
1949 },
1950 .num_parents = 1,
1951 .ops = &clk_branch2_ops,
1952 },
1953 },
1954};
1955
1956static struct clk_branch gcc_hmss_at_clk = {
1957 .halt_reg = 0x48010,
1958 .halt_check = BRANCH_HALT,
1959 .clkr = {
1960 .enable_reg = 0x48010,
1961 .enable_mask = BIT(0),
1962 .hw.init = &(struct clk_init_data){
1963 .name = "gcc_hmss_at_clk",
1964 .ops = &clk_branch2_ops,
1965 },
1966 },
1967};
1968
1969static struct clk_branch gcc_hmss_dvm_bus_clk = {
1970 .halt_reg = 0x4808c,
1971 .halt_check = BRANCH_HALT,
1972 .clkr = {
1973 .enable_reg = 0x4808c,
1974 .enable_mask = BIT(0),
1975 .hw.init = &(struct clk_init_data){
1976 .name = "gcc_hmss_dvm_bus_clk",
1977 .ops = &clk_branch2_ops,
1978 },
1979 },
1980};
1981
1982static struct clk_branch gcc_hmss_rbcpr_clk = {
1983 .halt_reg = 0x48008,
1984 .halt_check = BRANCH_HALT,
1985 .clkr = {
1986 .enable_reg = 0x48008,
1987 .enable_mask = BIT(0),
1988 .hw.init = &(struct clk_init_data){
1989 .name = "gcc_hmss_rbcpr_clk",
1990 .parent_names = (const char *[]){
1991 "hmss_rbcpr_clk_src",
1992 },
1993 .num_parents = 1,
1994 .ops = &clk_branch2_ops,
1995 },
1996 },
1997};
1998
1999static struct clk_branch gcc_hmss_trig_clk = {
2000 .halt_reg = 0x4800c,
2001 .halt_check = BRANCH_HALT,
2002 .clkr = {
2003 .enable_reg = 0x4800c,
2004 .enable_mask = BIT(0),
2005 .hw.init = &(struct clk_init_data){
2006 .name = "gcc_hmss_trig_clk",
2007 .ops = &clk_branch2_ops,
2008 },
2009 },
2010};
2011
2012static struct clk_branch gcc_lpass_at_clk = {
2013 .halt_reg = 0x47020,
2014 .halt_check = BRANCH_HALT,
2015 .clkr = {
2016 .enable_reg = 0x47020,
2017 .enable_mask = BIT(0),
2018 .hw.init = &(struct clk_init_data){
2019 .name = "gcc_lpass_at_clk",
2020 .ops = &clk_branch2_ops,
2021 },
2022 },
2023};
2024
2025static struct clk_branch gcc_lpass_trig_clk = {
2026 .halt_reg = 0x4701c,
2027 .halt_check = BRANCH_HALT,
2028 .clkr = {
2029 .enable_reg = 0x4701c,
2030 .enable_mask = BIT(0),
2031 .hw.init = &(struct clk_init_data){
2032 .name = "gcc_lpass_trig_clk",
2033 .ops = &clk_branch2_ops,
2034 },
2035 },
2036};
2037
2038static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
2039 .halt_reg = 0x9004,
2040 .halt_check = BRANCH_HALT,
2041 .clkr = {
2042 .enable_reg = 0x9004,
2043 .enable_mask = BIT(0),
2044 .hw.init = &(struct clk_init_data){
2045 .name = "gcc_mmss_noc_cfg_ahb_clk",
2046 .ops = &clk_branch2_ops,
2047 },
2048 },
2049};
2050
2051static struct clk_branch gcc_mmss_qm_ahb_clk = {
2052 .halt_reg = 0x9030,
2053 .halt_check = BRANCH_HALT,
2054 .clkr = {
2055 .enable_reg = 0x9030,
2056 .enable_mask = BIT(0),
2057 .hw.init = &(struct clk_init_data){
2058 .name = "gcc_mmss_qm_ahb_clk",
2059 .ops = &clk_branch2_ops,
2060 },
2061 },
2062};
2063
2064static struct clk_branch gcc_mmss_qm_core_clk = {
2065 .halt_reg = 0x900c,
2066 .halt_check = BRANCH_HALT,
2067 .clkr = {
2068 .enable_reg = 0x900c,
2069 .enable_mask = BIT(0),
2070 .hw.init = &(struct clk_init_data){
2071 .name = "gcc_mmss_qm_core_clk",
2072 .ops = &clk_branch2_ops,
2073 },
2074 },
2075};
2076
2077static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
2078 .halt_reg = 0x9000,
2079 .halt_check = BRANCH_HALT,
2080 .clkr = {
2081 .enable_reg = 0x9000,
2082 .enable_mask = BIT(0),
2083 .hw.init = &(struct clk_init_data){
2084 .name = "gcc_mmss_sys_noc_axi_clk",
2085 .ops = &clk_branch2_ops,
2086 },
2087 },
2088};
2089
2090static struct clk_branch gcc_mss_at_clk = {
2091 .halt_reg = 0x8a00c,
2092 .halt_check = BRANCH_HALT,
2093 .clkr = {
2094 .enable_reg = 0x8a00c,
2095 .enable_mask = BIT(0),
2096 .hw.init = &(struct clk_init_data){
2097 .name = "gcc_mss_at_clk",
2098 .ops = &clk_branch2_ops,
2099 },
2100 },
2101};
2102
2103static struct clk_branch gcc_pcie_0_aux_clk = {
2104 .halt_reg = 0x6b014,
2105 .halt_check = BRANCH_HALT,
2106 .clkr = {
2107 .enable_reg = 0x6b014,
2108 .enable_mask = BIT(0),
2109 .hw.init = &(struct clk_init_data){
2110 .name = "gcc_pcie_0_aux_clk",
2111 .parent_names = (const char *[]){
2112 "pcie_aux_clk_src",
2113 },
2114 .num_parents = 1,
2115 .ops = &clk_branch2_ops,
2116 },
2117 },
2118};
2119
2120static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2121 .halt_reg = 0x6b010,
2122 .halt_check = BRANCH_HALT,
2123 .clkr = {
2124 .enable_reg = 0x6b010,
2125 .enable_mask = BIT(0),
2126 .hw.init = &(struct clk_init_data){
2127 .name = "gcc_pcie_0_cfg_ahb_clk",
2128 .ops = &clk_branch2_ops,
2129 },
2130 },
2131};
2132
2133static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2134 .halt_reg = 0x6b00c,
2135 .halt_check = BRANCH_HALT,
2136 .clkr = {
2137 .enable_reg = 0x6b00c,
2138 .enable_mask = BIT(0),
2139 .hw.init = &(struct clk_init_data){
2140 .name = "gcc_pcie_0_mstr_axi_clk",
2141 .ops = &clk_branch2_ops,
2142 },
2143 },
2144};
2145
2146static struct clk_branch gcc_pcie_0_pipe_clk = {
2147 .halt_reg = 0x6b018,
2148 .halt_check = BRANCH_HALT,
2149 .clkr = {
2150 .enable_reg = 0x6b018,
2151 .enable_mask = BIT(0),
2152 .hw.init = &(struct clk_init_data){
2153 .name = "gcc_pcie_0_pipe_clk",
2154 .ops = &clk_branch2_ops,
2155 },
2156 },
2157};
2158
2159static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2160 .halt_reg = 0x6b008,
2161 .halt_check = BRANCH_HALT,
2162 .clkr = {
2163 .enable_reg = 0x6b008,
2164 .enable_mask = BIT(0),
2165 .hw.init = &(struct clk_init_data){
2166 .name = "gcc_pcie_0_slv_axi_clk",
2167 .ops = &clk_branch2_ops,
2168 },
2169 },
2170};
2171
2172static struct clk_branch gcc_pcie_phy_aux_clk = {
2173 .halt_reg = 0x6f004,
2174 .halt_check = BRANCH_HALT,
2175 .clkr = {
2176 .enable_reg = 0x6f004,
2177 .enable_mask = BIT(0),
2178 .hw.init = &(struct clk_init_data){
2179 .name = "gcc_pcie_phy_aux_clk",
2180 .parent_names = (const char *[]){
2181 "pcie_aux_clk_src",
2182 },
2183 .num_parents = 1,
2184 .ops = &clk_branch2_ops,
2185 },
2186 },
2187};
2188
2189static struct clk_branch gcc_pdm2_clk = {
2190 .halt_reg = 0x3300c,
2191 .halt_check = BRANCH_HALT,
2192 .clkr = {
2193 .enable_reg = 0x3300c,
2194 .enable_mask = BIT(0),
2195 .hw.init = &(struct clk_init_data){
2196 .name = "gcc_pdm2_clk",
2197 .parent_names = (const char *[]){
2198 "pdm2_clk_src",
2199 },
2200 .num_parents = 1,
2201 .ops = &clk_branch2_ops,
2202 },
2203 },
2204};
2205
2206static struct clk_branch gcc_pdm_ahb_clk = {
2207 .halt_reg = 0x33004,
2208 .halt_check = BRANCH_HALT,
2209 .clkr = {
2210 .enable_reg = 0x33004,
2211 .enable_mask = BIT(0),
2212 .hw.init = &(struct clk_init_data){
2213 .name = "gcc_pdm_ahb_clk",
2214 .ops = &clk_branch2_ops,
2215 },
2216 },
2217};
2218
2219static struct clk_branch gcc_pdm_xo4_clk = {
2220 .halt_reg = 0x33008,
2221 .halt_check = BRANCH_HALT,
2222 .clkr = {
2223 .enable_reg = 0x33008,
2224 .enable_mask = BIT(0),
2225 .hw.init = &(struct clk_init_data){
2226 .name = "gcc_pdm_xo4_clk",
2227 .ops = &clk_branch2_ops,
2228 },
2229 },
2230};
2231
2232static struct clk_branch gcc_prng_ahb_clk = {
2233 .halt_reg = 0x34004,
2234 .halt_check = BRANCH_HALT_VOTED,
2235 .clkr = {
2236 .enable_reg = 0x52004,
2237 .enable_mask = BIT(13),
2238 .hw.init = &(struct clk_init_data){
2239 .name = "gcc_prng_ahb_clk",
2240 .ops = &clk_branch2_ops,
2241 },
2242 },
2243};
2244
2245static struct clk_branch gcc_sdcc2_ahb_clk = {
2246 .halt_reg = 0x14008,
2247 .halt_check = BRANCH_HALT,
2248 .clkr = {
2249 .enable_reg = 0x14008,
2250 .enable_mask = BIT(0),
2251 .hw.init = &(struct clk_init_data){
2252 .name = "gcc_sdcc2_ahb_clk",
2253 .ops = &clk_branch2_ops,
2254 },
2255 },
2256};
2257
2258static struct clk_branch gcc_sdcc2_apps_clk = {
2259 .halt_reg = 0x14004,
2260 .halt_check = BRANCH_HALT,
2261 .clkr = {
2262 .enable_reg = 0x14004,
2263 .enable_mask = BIT(0),
2264 .hw.init = &(struct clk_init_data){
2265 .name = "gcc_sdcc2_apps_clk",
2266 .parent_names = (const char *[]){
2267 "sdcc2_apps_clk_src",
2268 },
2269 .num_parents = 1,
2270 .ops = &clk_branch2_ops,
2271 },
2272 },
2273};
2274
2275static struct clk_branch gcc_sdcc4_ahb_clk = {
2276 .halt_reg = 0x16008,
2277 .halt_check = BRANCH_HALT,
2278 .clkr = {
2279 .enable_reg = 0x16008,
2280 .enable_mask = BIT(0),
2281 .hw.init = &(struct clk_init_data){
2282 .name = "gcc_sdcc4_ahb_clk",
2283 .ops = &clk_branch2_ops,
2284 },
2285 },
2286};
2287
2288static struct clk_branch gcc_sdcc4_apps_clk = {
2289 .halt_reg = 0x16004,
2290 .halt_check = BRANCH_HALT,
2291 .clkr = {
2292 .enable_reg = 0x16004,
2293 .enable_mask = BIT(0),
2294 .hw.init = &(struct clk_init_data){
2295 .name = "gcc_sdcc4_apps_clk",
2296 .parent_names = (const char *[]){
2297 "sdcc4_apps_clk_src",
2298 },
2299 .num_parents = 1,
2300 .ops = &clk_branch2_ops,
2301 },
2302 },
2303};
2304
2305static struct clk_branch gcc_tsif_ahb_clk = {
2306 .halt_reg = 0x36004,
2307 .halt_check = BRANCH_HALT,
2308 .clkr = {
2309 .enable_reg = 0x36004,
2310 .enable_mask = BIT(0),
2311 .hw.init = &(struct clk_init_data){
2312 .name = "gcc_tsif_ahb_clk",
2313 .ops = &clk_branch2_ops,
2314 },
2315 },
2316};
2317
2318static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2319 .halt_reg = 0x3600c,
2320 .halt_check = BRANCH_HALT,
2321 .clkr = {
2322 .enable_reg = 0x3600c,
2323 .enable_mask = BIT(0),
2324 .hw.init = &(struct clk_init_data){
2325 .name = "gcc_tsif_inactivity_timers_clk",
2326 .ops = &clk_branch2_ops,
2327 },
2328 },
2329};
2330
2331static struct clk_branch gcc_tsif_ref_clk = {
2332 .halt_reg = 0x36008,
2333 .halt_check = BRANCH_HALT,
2334 .clkr = {
2335 .enable_reg = 0x36008,
2336 .enable_mask = BIT(0),
2337 .hw.init = &(struct clk_init_data){
2338 .name = "gcc_tsif_ref_clk",
2339 .parent_names = (const char *[]){
2340 "tsif_ref_clk_src",
2341 },
2342 .num_parents = 1,
2343 .ops = &clk_branch2_ops,
2344 },
2345 },
2346};
2347
2348static struct clk_branch gcc_ufs_ahb_clk = {
2349 .halt_reg = 0x7500c,
2350 .halt_check = BRANCH_HALT,
2351 .clkr = {
2352 .enable_reg = 0x7500c,
2353 .enable_mask = BIT(0),
2354 .hw.init = &(struct clk_init_data){
2355 .name = "gcc_ufs_ahb_clk",
2356 .ops = &clk_branch2_ops,
2357 },
2358 },
2359};
2360
2361static struct clk_branch gcc_ufs_axi_clk = {
2362 .halt_reg = 0x75008,
2363 .halt_check = BRANCH_HALT,
2364 .clkr = {
2365 .enable_reg = 0x75008,
2366 .enable_mask = BIT(0),
2367 .hw.init = &(struct clk_init_data){
2368 .name = "gcc_ufs_axi_clk",
2369 .parent_names = (const char *[]){
2370 "ufs_axi_clk_src",
2371 },
2372 .num_parents = 1,
2373 .ops = &clk_branch2_ops,
2374 },
2375 },
2376};
2377
2378static struct clk_branch gcc_ufs_ice_core_clk = {
2379 .halt_reg = 0x7600c,
2380 .halt_check = BRANCH_HALT,
2381 .clkr = {
2382 .enable_reg = 0x7600c,
2383 .enable_mask = BIT(0),
2384 .hw.init = &(struct clk_init_data){
2385 .name = "gcc_ufs_ice_core_clk",
2386 .ops = &clk_branch2_ops,
2387 },
2388 },
2389};
2390
2391static struct clk_branch gcc_ufs_phy_aux_clk = {
2392 .halt_reg = 0x76040,
2393 .halt_check = BRANCH_HALT,
2394 .clkr = {
2395 .enable_reg = 0x76040,
2396 .enable_mask = BIT(0),
2397 .hw.init = &(struct clk_init_data){
2398 .name = "gcc_ufs_phy_aux_clk",
2399 .ops = &clk_branch2_ops,
2400 },
2401 },
2402};
2403
2404static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2405 .halt_reg = 0x75014,
2406 .halt_check = BRANCH_HALT,
2407 .clkr = {
2408 .enable_reg = 0x75014,
2409 .enable_mask = BIT(0),
2410 .hw.init = &(struct clk_init_data){
2411 .name = "gcc_ufs_rx_symbol_0_clk",
2412 .ops = &clk_branch2_ops,
2413 },
2414 },
2415};
2416
2417static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2418 .halt_reg = 0x7605c,
2419 .halt_check = BRANCH_HALT,
2420 .clkr = {
2421 .enable_reg = 0x7605c,
2422 .enable_mask = BIT(0),
2423 .hw.init = &(struct clk_init_data){
2424 .name = "gcc_ufs_rx_symbol_1_clk",
2425 .ops = &clk_branch2_ops,
2426 },
2427 },
2428};
2429
2430static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2431 .halt_reg = 0x75010,
2432 .halt_check = BRANCH_HALT,
2433 .clkr = {
2434 .enable_reg = 0x75010,
2435 .enable_mask = BIT(0),
2436 .hw.init = &(struct clk_init_data){
2437 .name = "gcc_ufs_tx_symbol_0_clk",
2438 .ops = &clk_branch2_ops,
2439 },
2440 },
2441};
2442
2443static struct clk_branch gcc_ufs_unipro_core_clk = {
2444 .halt_reg = 0x76008,
2445 .halt_check = BRANCH_HALT,
2446 .clkr = {
2447 .enable_reg = 0x76008,
2448 .enable_mask = BIT(0),
2449 .hw.init = &(struct clk_init_data){
2450 .name = "gcc_ufs_unipro_core_clk",
2451 .ops = &clk_branch2_ops,
2452 },
2453 },
2454};
2455
2456static struct clk_branch gcc_usb30_master_clk = {
2457 .halt_reg = 0xf008,
2458 .halt_check = BRANCH_HALT,
2459 .clkr = {
2460 .enable_reg = 0xf008,
2461 .enable_mask = BIT(0),
2462 .hw.init = &(struct clk_init_data){
2463 .name = "gcc_usb30_master_clk",
2464 .parent_names = (const char *[]){
2465 "usb30_master_clk_src",
2466 },
2467 .num_parents = 1,
2468 .ops = &clk_branch2_ops,
2469 },
2470 },
2471};
2472
2473static struct clk_branch gcc_usb30_mock_utmi_clk = {
2474 .halt_reg = 0xf010,
2475 .halt_check = BRANCH_HALT,
2476 .clkr = {
2477 .enable_reg = 0xf010,
2478 .enable_mask = BIT(0),
2479 .hw.init = &(struct clk_init_data){
2480 .name = "gcc_usb30_mock_utmi_clk",
2481 .parent_names = (const char *[]){
2482 "usb30_mock_utmi_clk_src",
2483 },
2484 .num_parents = 1,
2485 .ops = &clk_branch2_ops,
2486 },
2487 },
2488};
2489
2490static struct clk_branch gcc_usb30_sleep_clk = {
2491 .halt_reg = 0xf00c,
2492 .halt_check = BRANCH_HALT,
2493 .clkr = {
2494 .enable_reg = 0xf00c,
2495 .enable_mask = BIT(0),
2496 .hw.init = &(struct clk_init_data){
2497 .name = "gcc_usb30_sleep_clk",
2498 .ops = &clk_branch2_ops,
2499 },
2500 },
2501};
2502
2503static struct clk_branch gcc_usb3_phy_aux_clk = {
2504 .halt_reg = 0x50000,
2505 .halt_check = BRANCH_HALT,
2506 .clkr = {
2507 .enable_reg = 0x50000,
2508 .enable_mask = BIT(0),
2509 .hw.init = &(struct clk_init_data){
2510 .name = "gcc_usb3_phy_aux_clk",
2511 .parent_names = (const char *[]){
2512 "usb3_phy_aux_clk_src",
2513 },
2514 .num_parents = 1,
2515 .ops = &clk_branch2_ops,
2516 },
2517 },
2518};
2519
2520static struct clk_branch gcc_usb3_phy_pipe_clk = {
2521 .halt_reg = 0x50004,
2522 .halt_check = BRANCH_HALT,
2523 .clkr = {
2524 .enable_reg = 0x50004,
2525 .enable_mask = BIT(0),
2526 .hw.init = &(struct clk_init_data){
2527 .name = "gcc_usb3_phy_pipe_clk",
2528 .ops = &clk_branch2_ops,
2529 },
2530 },
2531};
2532
2533static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2534 .halt_reg = 0x6a004,
2535 .halt_check = BRANCH_HALT,
2536 .clkr = {
2537 .enable_reg = 0x6a004,
2538 .enable_mask = BIT(0),
2539 .hw.init = &(struct clk_init_data){
2540 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2541 .ops = &clk_branch2_ops,
2542 },
2543 },
2544};
2545
2546static struct gdsc pcie_0_gdsc = {
2547 .gdscr = 0x6b004,
2548 .gds_hw_ctrl = 0x0,
2549 .pd = {
2550 .name = "pcie_0_gdsc",
2551 },
2552 .pwrsts = PWRSTS_OFF_ON,
2553 .flags = VOTABLE,
2554};
2555
2556static struct gdsc ufs_gdsc = {
2557 .gdscr = 0x75004,
2558 .gds_hw_ctrl = 0x0,
2559 .pd = {
2560 .name = "ufs_gdsc",
2561 },
2562 .pwrsts = PWRSTS_OFF_ON,
2563 .flags = VOTABLE,
2564};
2565
2566static struct gdsc usb_30_gdsc = {
2567 .gdscr = 0xf004,
2568 .gds_hw_ctrl = 0x0,
2569 .pd = {
2570 .name = "usb_30_gdsc",
2571 },
2572 .pwrsts = PWRSTS_OFF_ON,
2573 .flags = VOTABLE,
2574};
2575
2576static struct clk_regmap *gcc_msm8998_clocks[] = {
2577 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2578 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2579 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2580 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2581 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2582 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2583 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2584 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2585 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2586 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2587 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2588 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2589 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2590 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2591 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2592 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2593 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2594 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2595 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2596 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2597 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2598 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2599 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2600 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2601 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2602 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2603 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2604 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2605 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2606 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2607 [GCC_AGGRE1_NOC_XO_CLK] = &gcc_aggre1_noc_xo_clk.clkr,
2608 [GCC_AGGRE1_UFS_AXI_CLK] = &gcc_aggre1_ufs_axi_clk.clkr,
2609 [GCC_AGGRE1_USB3_AXI_CLK] = &gcc_aggre1_usb3_axi_clk.clkr,
2610 [GCC_APSS_QDSS_TSCTR_DIV2_CLK] = &gcc_apss_qdss_tsctr_div2_clk.clkr,
2611 [GCC_APSS_QDSS_TSCTR_DIV8_CLK] = &gcc_apss_qdss_tsctr_div8_clk.clkr,
2612 [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
2613 [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
2614 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2615 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2616 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2617 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2618 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2619 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2620 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2621 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2622 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2623 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2624 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2625 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2626 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2627 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
2628 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2629 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2630 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2631 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2632 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2633 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2634 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2635 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2636 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2637 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2638 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2639 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2640 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2641 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2642 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2643 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2644 [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
2645 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2646 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2647 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2648 [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
2649 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2650 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2651 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2652 [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
2653 [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr,
2654 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
2655 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2656 [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr,
2657 [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr,
2658 [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
2659 [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
2660 [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr,
2661 [GCC_LPASS_AT_CLK] = &gcc_lpass_at_clk.clkr,
2662 [GCC_LPASS_TRIG_CLK] = &gcc_lpass_trig_clk.clkr,
2663 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
2664 [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr,
2665 [GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr,
2666 [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
2667 [GCC_MSS_AT_CLK] = &gcc_mss_at_clk.clkr,
2668 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2669 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2670 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2671 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2672 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2673 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
2674 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2675 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2676 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2677 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2678 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2679 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2680 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2681 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2682 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2683 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
2684 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2685 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
2686 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2687 [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
2688 [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
2689 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
2690 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
2691 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
2692 [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
2693 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2694 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2695 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2696 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2697 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2698 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2699 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2700 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2701 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2702 [GPLL0] = &gpll0.clkr,
2703 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
2704 [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
2705 [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,
2706 [GPLL0_OUT_TEST] = &gpll0_out_test.clkr,
2707 [GPLL1] = &gpll1.clkr,
2708 [GPLL1_OUT_EVEN] = &gpll1_out_even.clkr,
2709 [GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
2710 [GPLL1_OUT_ODD] = &gpll1_out_odd.clkr,
2711 [GPLL1_OUT_TEST] = &gpll1_out_test.clkr,
2712 [GPLL2] = &gpll2.clkr,
2713 [GPLL2_OUT_EVEN] = &gpll2_out_even.clkr,
2714 [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr,
2715 [GPLL2_OUT_ODD] = &gpll2_out_odd.clkr,
2716 [GPLL2_OUT_TEST] = &gpll2_out_test.clkr,
2717 [GPLL3] = &gpll3.clkr,
2718 [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr,
2719 [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
2720 [GPLL3_OUT_ODD] = &gpll3_out_odd.clkr,
2721 [GPLL3_OUT_TEST] = &gpll3_out_test.clkr,
2722 [GPLL4] = &gpll4.clkr,
2723 [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr,
2724 [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
2725 [GPLL4_OUT_ODD] = &gpll4_out_odd.clkr,
2726 [GPLL4_OUT_TEST] = &gpll4_out_test.clkr,
2727 [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr,
2728 [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
2729 [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
2730 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2731 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2732 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2733 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2734 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2735 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2736 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2737 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2738};
2739
2740static struct gdsc *gcc_msm8998_gdscs[] = {
2741 [PCIE_0_GDSC] = &pcie_0_gdsc,
2742 [UFS_GDSC] = &ufs_gdsc,
2743 [USB_30_GDSC] = &usb_30_gdsc,
2744};
2745
2746static const struct qcom_reset_map gcc_msm8998_resets[] = {
2747 [GCC_BLSP1_QUP1_BCR] = { 0x102400 },
2748 [GCC_BLSP1_QUP2_BCR] = { 0x110592 },
2749 [GCC_BLSP1_QUP3_BCR] = { 0x118784 },
2750 [GCC_BLSP1_QUP4_BCR] = { 0x126976 },
2751 [GCC_BLSP1_QUP5_BCR] = { 0x135168 },
2752 [GCC_BLSP1_QUP6_BCR] = { 0x143360 },
2753 [GCC_BLSP2_QUP1_BCR] = { 0x155648 },
2754 [GCC_BLSP2_QUP2_BCR] = { 0x163840 },
2755 [GCC_BLSP2_QUP3_BCR] = { 0x172032 },
2756 [GCC_BLSP2_QUP4_BCR] = { 0x180224 },
2757 [GCC_BLSP2_QUP5_BCR] = { 0x188416 },
2758 [GCC_BLSP2_QUP6_BCR] = { 0x196608 },
2759 [GCC_PCIE_0_BCR] = { 0x438272 },
2760 [GCC_PDM_BCR] = { 0x208896 },
2761 [GCC_SDCC2_BCR] = { 0x81920 },
2762 [GCC_SDCC4_BCR] = { 0x90112 },
2763 [GCC_TSIF_BCR] = { 0x221184 },
2764 [GCC_UFS_BCR] = { 0x479232 },
2765 [GCC_USB_30_BCR] = { 0x61440 },
2766};
2767
2768static const struct regmap_config gcc_msm8998_regmap_config = {
2769 .reg_bits = 32,
2770 .reg_stride = 4,
2771 .val_bits = 32,
2772 .max_register = 0x8f000,
2773 .fast_io = true,
2774};
2775
2776static const struct qcom_cc_desc gcc_msm8998_desc = {
2777 .config = &gcc_msm8998_regmap_config,
2778 .clks = gcc_msm8998_clocks,
2779 .num_clks = ARRAY_SIZE(gcc_msm8998_clocks),
2780 .resets = gcc_msm8998_resets,
2781 .num_resets = ARRAY_SIZE(gcc_msm8998_resets),
2782 .gdscs = gcc_msm8998_gdscs,
2783 .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs),
2784};
2785
2786static int gcc_msm8998_probe(struct platform_device *pdev)
2787{
2788 struct regmap *regmap;
2789 int ret;
2790
2791 regmap = qcom_cc_map(pdev, &gcc_msm8998_desc);
2792 if (IS_ERR(regmap))
2793 return PTR_ERR(regmap);
2794
2795 /*
2796 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
2797 * turned off by hardware during certain apps low power modes.
2798 */
2799 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
2800 if (ret)
2801 return ret;
2802
2803 return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap);
2804}
2805
2806static const struct of_device_id gcc_msm8998_match_table[] = {
2807 { .compatible = "qcom,gcc-msm8998" },
2808 { }
2809};
2810MODULE_DEVICE_TABLE(of, gcc_msm8998_match_table);
2811
2812static struct platform_driver gcc_msm8998_driver = {
2813 .probe = gcc_msm8998_probe,
2814 .driver = {
2815 .name = "gcc-msm8998",
2816 .of_match_table = gcc_msm8998_match_table,
2817 },
2818};
2819
2820static int __init gcc_msm8998_init(void)
2821{
2822 return platform_driver_register(&gcc_msm8998_driver);
2823}
2824core_initcall(gcc_msm8998_init);
2825
2826static void __exit gcc_msm8998_exit(void)
2827{
2828 platform_driver_unregister(&gcc_msm8998_driver);
2829}
2830module_exit(gcc_msm8998_exit);
2831
2832MODULE_DESCRIPTION("QCOM GCC msm8998 Driver");
2833MODULE_LICENSE("GPL v2");
2834MODULE_ALIAS("platform:gcc-msm8998");
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
new file mode 100644
index 000000000000..e78e6f5b99fc
--- /dev/null
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -0,0 +1,3465 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/kernel.h>
7#include <linux/bitops.h>
8#include <linux/err.h>
9#include <linux/platform_device.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_device.h>
13#include <linux/clk-provider.h>
14#include <linux/regmap.h>
15#include <linux/reset-controller.h>
16
17#include <dt-bindings/clock/qcom,gcc-sdm845.h>
18
19#include "common.h"
20#include "clk-regmap.h"
21#include "clk-pll.h"
22#include "clk-rcg.h"
23#include "clk-branch.h"
24#include "clk-alpha-pll.h"
25#include "gdsc.h"
26#include "reset.h"
27
28#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
29
30enum {
31 P_BI_TCXO,
32 P_AUD_REF_CLK,
33 P_CORE_BI_PLL_TEST_SE,
34 P_GPLL0_OUT_EVEN,
35 P_GPLL0_OUT_MAIN,
36 P_GPLL4_OUT_MAIN,
37 P_SLEEP_CLK,
38};
39
40static const struct parent_map gcc_parent_map_0[] = {
41 { P_BI_TCXO, 0 },
42 { P_GPLL0_OUT_MAIN, 1 },
43 { P_GPLL0_OUT_EVEN, 6 },
44 { P_CORE_BI_PLL_TEST_SE, 7 },
45};
46
47static const char * const gcc_parent_names_0[] = {
48 "bi_tcxo",
49 "gpll0",
50 "gpll0_out_even",
51 "core_bi_pll_test_se",
52};
53
54static const struct parent_map gcc_parent_map_1[] = {
55 { P_BI_TCXO, 0 },
56 { P_GPLL0_OUT_MAIN, 1 },
57 { P_SLEEP_CLK, 5 },
58 { P_GPLL0_OUT_EVEN, 6 },
59 { P_CORE_BI_PLL_TEST_SE, 7 },
60};
61
62static const char * const gcc_parent_names_1[] = {
63 "bi_tcxo",
64 "gpll0",
65 "core_pi_sleep_clk",
66 "gpll0_out_even",
67 "core_bi_pll_test_se",
68};
69
70static const struct parent_map gcc_parent_map_2[] = {
71 { P_BI_TCXO, 0 },
72 { P_SLEEP_CLK, 5 },
73 { P_CORE_BI_PLL_TEST_SE, 7 },
74};
75
76static const char * const gcc_parent_names_2[] = {
77 "bi_tcxo",
78 "core_pi_sleep_clk",
79 "core_bi_pll_test_se",
80};
81
82static const struct parent_map gcc_parent_map_3[] = {
83 { P_BI_TCXO, 0 },
84 { P_GPLL0_OUT_MAIN, 1 },
85 { P_CORE_BI_PLL_TEST_SE, 7 },
86};
87
88static const char * const gcc_parent_names_3[] = {
89 "bi_tcxo",
90 "gpll0",
91 "core_bi_pll_test_se",
92};
93
94static const struct parent_map gcc_parent_map_4[] = {
95 { P_BI_TCXO, 0 },
96 { P_CORE_BI_PLL_TEST_SE, 7 },
97};
98
99static const char * const gcc_parent_names_4[] = {
100 "bi_tcxo",
101 "core_bi_pll_test_se",
102};
103
104static const struct parent_map gcc_parent_map_5[] = {
105 { P_BI_TCXO, 0 },
106 { P_GPLL0_OUT_MAIN, 1 },
107 { P_GPLL4_OUT_MAIN, 5 },
108 { P_GPLL0_OUT_EVEN, 6 },
109 { P_CORE_BI_PLL_TEST_SE, 7 },
110};
111
112static const char * const gcc_parent_names_5[] = {
113 "bi_tcxo",
114 "gpll0",
115 "gpll4",
116 "gpll0_out_even",
117 "core_bi_pll_test_se",
118};
119
120static const struct parent_map gcc_parent_map_6[] = {
121 { P_BI_TCXO, 0 },
122 { P_GPLL0_OUT_MAIN, 1 },
123 { P_AUD_REF_CLK, 2 },
124 { P_GPLL0_OUT_EVEN, 6 },
125 { P_CORE_BI_PLL_TEST_SE, 7 },
126};
127
128static const char * const gcc_parent_names_6[] = {
129 "bi_tcxo",
130 "gpll0",
131 "aud_ref_clk",
132 "gpll0_out_even",
133 "core_bi_pll_test_se",
134};
135
136static const char * const gcc_parent_names_7[] = {
137 "bi_tcxo",
138 "gpll0",
139 "gpll0_out_even",
140 "core_bi_pll_test_se",
141};
142
143static const char * const gcc_parent_names_8[] = {
144 "bi_tcxo",
145 "gpll0",
146 "core_bi_pll_test_se",
147};
148
149static const struct parent_map gcc_parent_map_10[] = {
150 { P_BI_TCXO, 0 },
151 { P_GPLL0_OUT_MAIN, 1 },
152 { P_GPLL4_OUT_MAIN, 5 },
153 { P_GPLL0_OUT_EVEN, 6 },
154 { P_CORE_BI_PLL_TEST_SE, 7 },
155};
156
157static const char * const gcc_parent_names_10[] = {
158 "bi_tcxo",
159 "gpll0",
160 "gpll4",
161 "gpll0_out_even",
162 "core_bi_pll_test_se",
163};
164
165static struct clk_alpha_pll gpll0 = {
166 .offset = 0x0,
167 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
168 .clkr = {
169 .enable_reg = 0x52000,
170 .enable_mask = BIT(0),
171 .hw.init = &(struct clk_init_data){
172 .name = "gpll0",
173 .parent_names = (const char *[]){ "bi_tcxo" },
174 .num_parents = 1,
175 .ops = &clk_alpha_pll_fixed_fabia_ops,
176 },
177 },
178};
179
180static struct clk_alpha_pll gpll4 = {
181 .offset = 0x76000,
182 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
183 .clkr = {
184 .enable_reg = 0x52000,
185 .enable_mask = BIT(4),
186 .hw.init = &(struct clk_init_data){
187 .name = "gpll4",
188 .parent_names = (const char *[]){ "bi_tcxo" },
189 .num_parents = 1,
190 .ops = &clk_alpha_pll_fixed_fabia_ops,
191 },
192 },
193};
194
195static const struct clk_div_table post_div_table_fabia_even[] = {
196 { 0x0, 1 },
197 { 0x1, 2 },
198 { 0x3, 4 },
199 { 0x7, 8 },
200 { }
201};
202
203static struct clk_alpha_pll_postdiv gpll0_out_even = {
204 .offset = 0x0,
205 .post_div_shift = 8,
206 .post_div_table = post_div_table_fabia_even,
207 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
208 .width = 4,
209 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
210 .clkr.hw.init = &(struct clk_init_data){
211 .name = "gpll0_out_even",
212 .parent_names = (const char *[]){ "gpll0" },
213 .num_parents = 1,
214 .ops = &clk_alpha_pll_postdiv_fabia_ops,
215 },
216};
217
218static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
219 F(19200000, P_BI_TCXO, 1, 0, 0),
220 { }
221};
222
223static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
224 .cmd_rcgr = 0x48014,
225 .mnd_width = 0,
226 .hid_width = 5,
227 .parent_map = gcc_parent_map_0,
228 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
229 .clkr.hw.init = &(struct clk_init_data){
230 .name = "gcc_cpuss_ahb_clk_src",
231 .parent_names = gcc_parent_names_7,
232 .num_parents = 4,
233 .ops = &clk_rcg2_ops,
234 },
235};
236
237static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = {
238 F(19200000, P_BI_TCXO, 1, 0, 0),
239 { }
240};
241
242static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
243 .cmd_rcgr = 0x4815c,
244 .mnd_width = 0,
245 .hid_width = 5,
246 .parent_map = gcc_parent_map_3,
247 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
248 .clkr.hw.init = &(struct clk_init_data){
249 .name = "gcc_cpuss_rbcpr_clk_src",
250 .parent_names = gcc_parent_names_8,
251 .num_parents = 3,
252 .ops = &clk_rcg2_ops,
253 },
254};
255
256static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
257 F(19200000, P_BI_TCXO, 1, 0, 0),
258 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
259 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
260 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
261 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
262 { }
263};
264
265static struct clk_rcg2 gcc_gp1_clk_src = {
266 .cmd_rcgr = 0x64004,
267 .mnd_width = 8,
268 .hid_width = 5,
269 .parent_map = gcc_parent_map_1,
270 .freq_tbl = ftbl_gcc_gp1_clk_src,
271 .clkr.hw.init = &(struct clk_init_data){
272 .name = "gcc_gp1_clk_src",
273 .parent_names = gcc_parent_names_1,
274 .num_parents = 5,
275 .ops = &clk_rcg2_ops,
276 },
277};
278
279static struct clk_rcg2 gcc_gp2_clk_src = {
280 .cmd_rcgr = 0x65004,
281 .mnd_width = 8,
282 .hid_width = 5,
283 .parent_map = gcc_parent_map_1,
284 .freq_tbl = ftbl_gcc_gp1_clk_src,
285 .clkr.hw.init = &(struct clk_init_data){
286 .name = "gcc_gp2_clk_src",
287 .parent_names = gcc_parent_names_1,
288 .num_parents = 5,
289 .ops = &clk_rcg2_ops,
290 },
291};
292
293static struct clk_rcg2 gcc_gp3_clk_src = {
294 .cmd_rcgr = 0x66004,
295 .mnd_width = 8,
296 .hid_width = 5,
297 .parent_map = gcc_parent_map_1,
298 .freq_tbl = ftbl_gcc_gp1_clk_src,
299 .clkr.hw.init = &(struct clk_init_data){
300 .name = "gcc_gp3_clk_src",
301 .parent_names = gcc_parent_names_1,
302 .num_parents = 5,
303 .ops = &clk_rcg2_ops,
304 },
305};
306
307static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
308 F(9600000, P_BI_TCXO, 2, 0, 0),
309 F(19200000, P_BI_TCXO, 1, 0, 0),
310 { }
311};
312
313static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
314 .cmd_rcgr = 0x6b028,
315 .mnd_width = 16,
316 .hid_width = 5,
317 .parent_map = gcc_parent_map_2,
318 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
319 .clkr.hw.init = &(struct clk_init_data){
320 .name = "gcc_pcie_0_aux_clk_src",
321 .parent_names = gcc_parent_names_2,
322 .num_parents = 3,
323 .ops = &clk_rcg2_ops,
324 },
325};
326
327static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
328 .cmd_rcgr = 0x8d028,
329 .mnd_width = 16,
330 .hid_width = 5,
331 .parent_map = gcc_parent_map_2,
332 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
333 .clkr.hw.init = &(struct clk_init_data){
334 .name = "gcc_pcie_1_aux_clk_src",
335 .parent_names = gcc_parent_names_2,
336 .num_parents = 3,
337 .ops = &clk_rcg2_ops,
338 },
339};
340
341static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
342 F(19200000, P_BI_TCXO, 1, 0, 0),
343 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
344 { }
345};
346
347static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
348 .cmd_rcgr = 0x6f014,
349 .mnd_width = 0,
350 .hid_width = 5,
351 .parent_map = gcc_parent_map_0,
352 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
353 .clkr.hw.init = &(struct clk_init_data){
354 .name = "gcc_pcie_phy_refgen_clk_src",
355 .parent_names = gcc_parent_names_0,
356 .num_parents = 4,
357 .ops = &clk_rcg2_ops,
358 },
359};
360
361static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
362 F(9600000, P_BI_TCXO, 2, 0, 0),
363 F(19200000, P_BI_TCXO, 1, 0, 0),
364 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
365 { }
366};
367
368static struct clk_rcg2 gcc_pdm2_clk_src = {
369 .cmd_rcgr = 0x33010,
370 .mnd_width = 0,
371 .hid_width = 5,
372 .parent_map = gcc_parent_map_0,
373 .freq_tbl = ftbl_gcc_pdm2_clk_src,
374 .clkr.hw.init = &(struct clk_init_data){
375 .name = "gcc_pdm2_clk_src",
376 .parent_names = gcc_parent_names_0,
377 .num_parents = 4,
378 .ops = &clk_rcg2_ops,
379 },
380};
381
382static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
383 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
384 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
385 F(19200000, P_BI_TCXO, 1, 0, 0),
386 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
387 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
388 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
389 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
390 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
391 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
392 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
393 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
394 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
395 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
396 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
397 F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
398 { }
399};
400
401static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
402 .cmd_rcgr = 0x17034,
403 .mnd_width = 16,
404 .hid_width = 5,
405 .parent_map = gcc_parent_map_0,
406 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
407 .clkr.hw.init = &(struct clk_init_data){
408 .name = "gcc_qupv3_wrap0_s0_clk_src",
409 .parent_names = gcc_parent_names_0,
410 .num_parents = 4,
411 .ops = &clk_rcg2_shared_ops,
412 },
413};
414
415static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
416 .cmd_rcgr = 0x17164,
417 .mnd_width = 16,
418 .hid_width = 5,
419 .parent_map = gcc_parent_map_0,
420 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
421 .clkr.hw.init = &(struct clk_init_data){
422 .name = "gcc_qupv3_wrap0_s1_clk_src",
423 .parent_names = gcc_parent_names_0,
424 .num_parents = 4,
425 .ops = &clk_rcg2_shared_ops,
426 },
427};
428
429static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
430 .cmd_rcgr = 0x17294,
431 .mnd_width = 16,
432 .hid_width = 5,
433 .parent_map = gcc_parent_map_0,
434 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
435 .clkr.hw.init = &(struct clk_init_data){
436 .name = "gcc_qupv3_wrap0_s2_clk_src",
437 .parent_names = gcc_parent_names_0,
438 .num_parents = 4,
439 .ops = &clk_rcg2_shared_ops,
440 },
441};
442
443static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
444 .cmd_rcgr = 0x173c4,
445 .mnd_width = 16,
446 .hid_width = 5,
447 .parent_map = gcc_parent_map_0,
448 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
449 .clkr.hw.init = &(struct clk_init_data){
450 .name = "gcc_qupv3_wrap0_s3_clk_src",
451 .parent_names = gcc_parent_names_0,
452 .num_parents = 4,
453 .ops = &clk_rcg2_shared_ops,
454 },
455};
456
457static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
458 .cmd_rcgr = 0x174f4,
459 .mnd_width = 16,
460 .hid_width = 5,
461 .parent_map = gcc_parent_map_0,
462 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
463 .clkr.hw.init = &(struct clk_init_data){
464 .name = "gcc_qupv3_wrap0_s4_clk_src",
465 .parent_names = gcc_parent_names_0,
466 .num_parents = 4,
467 .ops = &clk_rcg2_shared_ops,
468 },
469};
470
471static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
472 .cmd_rcgr = 0x17624,
473 .mnd_width = 16,
474 .hid_width = 5,
475 .parent_map = gcc_parent_map_0,
476 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
477 .clkr.hw.init = &(struct clk_init_data){
478 .name = "gcc_qupv3_wrap0_s5_clk_src",
479 .parent_names = gcc_parent_names_0,
480 .num_parents = 4,
481 .ops = &clk_rcg2_shared_ops,
482 },
483};
484
485static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
486 .cmd_rcgr = 0x17754,
487 .mnd_width = 16,
488 .hid_width = 5,
489 .parent_map = gcc_parent_map_0,
490 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
491 .clkr.hw.init = &(struct clk_init_data){
492 .name = "gcc_qupv3_wrap0_s6_clk_src",
493 .parent_names = gcc_parent_names_0,
494 .num_parents = 4,
495 .ops = &clk_rcg2_shared_ops,
496 },
497};
498
499static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
500 .cmd_rcgr = 0x17884,
501 .mnd_width = 16,
502 .hid_width = 5,
503 .parent_map = gcc_parent_map_0,
504 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
505 .clkr.hw.init = &(struct clk_init_data){
506 .name = "gcc_qupv3_wrap0_s7_clk_src",
507 .parent_names = gcc_parent_names_0,
508 .num_parents = 4,
509 .ops = &clk_rcg2_shared_ops,
510 },
511};
512
513static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
514 .cmd_rcgr = 0x18018,
515 .mnd_width = 16,
516 .hid_width = 5,
517 .parent_map = gcc_parent_map_0,
518 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
519 .clkr.hw.init = &(struct clk_init_data){
520 .name = "gcc_qupv3_wrap1_s0_clk_src",
521 .parent_names = gcc_parent_names_0,
522 .num_parents = 4,
523 .ops = &clk_rcg2_shared_ops,
524 },
525};
526
527static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
528 .cmd_rcgr = 0x18148,
529 .mnd_width = 16,
530 .hid_width = 5,
531 .parent_map = gcc_parent_map_0,
532 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
533 .clkr.hw.init = &(struct clk_init_data){
534 .name = "gcc_qupv3_wrap1_s1_clk_src",
535 .parent_names = gcc_parent_names_0,
536 .num_parents = 4,
537 .ops = &clk_rcg2_shared_ops,
538 },
539};
540
541static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
542 .cmd_rcgr = 0x18278,
543 .mnd_width = 16,
544 .hid_width = 5,
545 .parent_map = gcc_parent_map_0,
546 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
547 .clkr.hw.init = &(struct clk_init_data){
548 .name = "gcc_qupv3_wrap1_s2_clk_src",
549 .parent_names = gcc_parent_names_0,
550 .num_parents = 4,
551 .ops = &clk_rcg2_shared_ops,
552 },
553};
554
555static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
556 .cmd_rcgr = 0x183a8,
557 .mnd_width = 16,
558 .hid_width = 5,
559 .parent_map = gcc_parent_map_0,
560 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
561 .clkr.hw.init = &(struct clk_init_data){
562 .name = "gcc_qupv3_wrap1_s3_clk_src",
563 .parent_names = gcc_parent_names_0,
564 .num_parents = 4,
565 .ops = &clk_rcg2_shared_ops,
566 },
567};
568
569static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
570 .cmd_rcgr = 0x184d8,
571 .mnd_width = 16,
572 .hid_width = 5,
573 .parent_map = gcc_parent_map_0,
574 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
575 .clkr.hw.init = &(struct clk_init_data){
576 .name = "gcc_qupv3_wrap1_s4_clk_src",
577 .parent_names = gcc_parent_names_0,
578 .num_parents = 4,
579 .ops = &clk_rcg2_shared_ops,
580 },
581};
582
583static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
584 .cmd_rcgr = 0x18608,
585 .mnd_width = 16,
586 .hid_width = 5,
587 .parent_map = gcc_parent_map_0,
588 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
589 .clkr.hw.init = &(struct clk_init_data){
590 .name = "gcc_qupv3_wrap1_s5_clk_src",
591 .parent_names = gcc_parent_names_0,
592 .num_parents = 4,
593 .ops = &clk_rcg2_shared_ops,
594 },
595};
596
597static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
598 .cmd_rcgr = 0x18738,
599 .mnd_width = 16,
600 .hid_width = 5,
601 .parent_map = gcc_parent_map_0,
602 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
603 .clkr.hw.init = &(struct clk_init_data){
604 .name = "gcc_qupv3_wrap1_s6_clk_src",
605 .parent_names = gcc_parent_names_0,
606 .num_parents = 4,
607 .ops = &clk_rcg2_shared_ops,
608 },
609};
610
611static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
612 .cmd_rcgr = 0x18868,
613 .mnd_width = 16,
614 .hid_width = 5,
615 .parent_map = gcc_parent_map_0,
616 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
617 .clkr.hw.init = &(struct clk_init_data){
618 .name = "gcc_qupv3_wrap1_s7_clk_src",
619 .parent_names = gcc_parent_names_0,
620 .num_parents = 4,
621 .ops = &clk_rcg2_shared_ops,
622 },
623};
624
625static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
626 F(400000, P_BI_TCXO, 12, 1, 4),
627 F(9600000, P_BI_TCXO, 2, 0, 0),
628 F(19200000, P_BI_TCXO, 1, 0, 0),
629 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
630 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
631 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
632 F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0),
633 { }
634};
635
636static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
637 .cmd_rcgr = 0x1400c,
638 .mnd_width = 8,
639 .hid_width = 5,
640 .parent_map = gcc_parent_map_10,
641 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
642 .clkr.hw.init = &(struct clk_init_data){
643 .name = "gcc_sdcc2_apps_clk_src",
644 .parent_names = gcc_parent_names_10,
645 .num_parents = 5,
646 .ops = &clk_rcg2_ops,
647 },
648};
649
650static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
651 F(400000, P_BI_TCXO, 12, 1, 4),
652 F(9600000, P_BI_TCXO, 2, 0, 0),
653 F(19200000, P_BI_TCXO, 1, 0, 0),
654 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
655 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
656 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
657 { }
658};
659
660static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
661 .cmd_rcgr = 0x1600c,
662 .mnd_width = 8,
663 .hid_width = 5,
664 .parent_map = gcc_parent_map_0,
665 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
666 .clkr.hw.init = &(struct clk_init_data){
667 .name = "gcc_sdcc4_apps_clk_src",
668 .parent_names = gcc_parent_names_0,
669 .num_parents = 4,
670 .ops = &clk_rcg2_ops,
671 },
672};
673
674static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
675 F(105495, P_BI_TCXO, 2, 1, 91),
676 { }
677};
678
679static struct clk_rcg2 gcc_tsif_ref_clk_src = {
680 .cmd_rcgr = 0x36010,
681 .mnd_width = 8,
682 .hid_width = 5,
683 .parent_map = gcc_parent_map_6,
684 .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
685 .clkr.hw.init = &(struct clk_init_data){
686 .name = "gcc_tsif_ref_clk_src",
687 .parent_names = gcc_parent_names_6,
688 .num_parents = 5,
689 .ops = &clk_rcg2_ops,
690 },
691};
692
693static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
694 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
695 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
696 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
697 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
698 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
699 { }
700};
701
702static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
703 .cmd_rcgr = 0x7501c,
704 .mnd_width = 8,
705 .hid_width = 5,
706 .parent_map = gcc_parent_map_0,
707 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
708 .clkr.hw.init = &(struct clk_init_data){
709 .name = "gcc_ufs_card_axi_clk_src",
710 .parent_names = gcc_parent_names_0,
711 .num_parents = 4,
712 .ops = &clk_rcg2_shared_ops,
713 },
714};
715
716static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
717 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
718 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
719 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
720 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
721 { }
722};
723
724static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
725 .cmd_rcgr = 0x7505c,
726 .mnd_width = 0,
727 .hid_width = 5,
728 .parent_map = gcc_parent_map_0,
729 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
730 .clkr.hw.init = &(struct clk_init_data){
731 .name = "gcc_ufs_card_ice_core_clk_src",
732 .parent_names = gcc_parent_names_0,
733 .num_parents = 4,
734 .ops = &clk_rcg2_shared_ops,
735 },
736};
737
738static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
739 .cmd_rcgr = 0x75090,
740 .mnd_width = 0,
741 .hid_width = 5,
742 .parent_map = gcc_parent_map_4,
743 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
744 .clkr.hw.init = &(struct clk_init_data){
745 .name = "gcc_ufs_card_phy_aux_clk_src",
746 .parent_names = gcc_parent_names_4,
747 .num_parents = 2,
748 .ops = &clk_rcg2_ops,
749 },
750};
751
752static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
753 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
754 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
755 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
756 { }
757};
758
759static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
760 .cmd_rcgr = 0x75074,
761 .mnd_width = 0,
762 .hid_width = 5,
763 .parent_map = gcc_parent_map_0,
764 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
765 .clkr.hw.init = &(struct clk_init_data){
766 .name = "gcc_ufs_card_unipro_core_clk_src",
767 .parent_names = gcc_parent_names_0,
768 .num_parents = 4,
769 .ops = &clk_rcg2_shared_ops,
770 },
771};
772
773static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
774 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
775 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
776 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
777 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
778 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
779 { }
780};
781
782static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
783 .cmd_rcgr = 0x7701c,
784 .mnd_width = 8,
785 .hid_width = 5,
786 .parent_map = gcc_parent_map_0,
787 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
788 .clkr.hw.init = &(struct clk_init_data){
789 .name = "gcc_ufs_phy_axi_clk_src",
790 .parent_names = gcc_parent_names_0,
791 .num_parents = 4,
792 .ops = &clk_rcg2_shared_ops,
793 },
794};
795
796static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
797 .cmd_rcgr = 0x7705c,
798 .mnd_width = 0,
799 .hid_width = 5,
800 .parent_map = gcc_parent_map_0,
801 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
802 .clkr.hw.init = &(struct clk_init_data){
803 .name = "gcc_ufs_phy_ice_core_clk_src",
804 .parent_names = gcc_parent_names_0,
805 .num_parents = 4,
806 .ops = &clk_rcg2_shared_ops,
807 },
808};
809
810static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
811 .cmd_rcgr = 0x77090,
812 .mnd_width = 0,
813 .hid_width = 5,
814 .parent_map = gcc_parent_map_4,
815 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
816 .clkr.hw.init = &(struct clk_init_data){
817 .name = "gcc_ufs_phy_phy_aux_clk_src",
818 .parent_names = gcc_parent_names_4,
819 .num_parents = 2,
820 .ops = &clk_rcg2_shared_ops,
821 },
822};
823
824static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
825 .cmd_rcgr = 0x77074,
826 .mnd_width = 0,
827 .hid_width = 5,
828 .parent_map = gcc_parent_map_0,
829 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
830 .clkr.hw.init = &(struct clk_init_data){
831 .name = "gcc_ufs_phy_unipro_core_clk_src",
832 .parent_names = gcc_parent_names_0,
833 .num_parents = 4,
834 .ops = &clk_rcg2_shared_ops,
835 },
836};
837
838static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
839 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
840 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
841 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
842 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
843 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
844 { }
845};
846
847static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
848 .cmd_rcgr = 0xf018,
849 .mnd_width = 8,
850 .hid_width = 5,
851 .parent_map = gcc_parent_map_0,
852 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
853 .clkr.hw.init = &(struct clk_init_data){
854 .name = "gcc_usb30_prim_master_clk_src",
855 .parent_names = gcc_parent_names_0,
856 .num_parents = 4,
857 .ops = &clk_rcg2_shared_ops,
858 },
859};
860
861static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
862 F(19200000, P_BI_TCXO, 1, 0, 0),
863 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
864 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
865 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
866 { }
867};
868
869static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
870 .cmd_rcgr = 0xf030,
871 .mnd_width = 0,
872 .hid_width = 5,
873 .parent_map = gcc_parent_map_0,
874 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
875 .clkr.hw.init = &(struct clk_init_data){
876 .name = "gcc_usb30_prim_mock_utmi_clk_src",
877 .parent_names = gcc_parent_names_0,
878 .num_parents = 4,
879 .ops = &clk_rcg2_shared_ops,
880 },
881};
882
883static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
884 .cmd_rcgr = 0x10018,
885 .mnd_width = 8,
886 .hid_width = 5,
887 .parent_map = gcc_parent_map_0,
888 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
889 .clkr.hw.init = &(struct clk_init_data){
890 .name = "gcc_usb30_sec_master_clk_src",
891 .parent_names = gcc_parent_names_0,
892 .num_parents = 4,
893 .ops = &clk_rcg2_ops,
894 },
895};
896
897static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
898 .cmd_rcgr = 0x10030,
899 .mnd_width = 0,
900 .hid_width = 5,
901 .parent_map = gcc_parent_map_0,
902 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
903 .clkr.hw.init = &(struct clk_init_data){
904 .name = "gcc_usb30_sec_mock_utmi_clk_src",
905 .parent_names = gcc_parent_names_0,
906 .num_parents = 4,
907 .ops = &clk_rcg2_ops,
908 },
909};
910
911static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
912 .cmd_rcgr = 0xf05c,
913 .mnd_width = 0,
914 .hid_width = 5,
915 .parent_map = gcc_parent_map_2,
916 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
917 .clkr.hw.init = &(struct clk_init_data){
918 .name = "gcc_usb3_prim_phy_aux_clk_src",
919 .parent_names = gcc_parent_names_2,
920 .num_parents = 3,
921 .ops = &clk_rcg2_ops,
922 },
923};
924
925static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
926 .cmd_rcgr = 0x1005c,
927 .mnd_width = 0,
928 .hid_width = 5,
929 .parent_map = gcc_parent_map_2,
930 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
931 .clkr.hw.init = &(struct clk_init_data){
932 .name = "gcc_usb3_sec_phy_aux_clk_src",
933 .parent_names = gcc_parent_names_2,
934 .num_parents = 3,
935 .ops = &clk_rcg2_shared_ops,
936 },
937};
938
939static struct clk_rcg2 gcc_vs_ctrl_clk_src = {
940 .cmd_rcgr = 0x7a030,
941 .mnd_width = 0,
942 .hid_width = 5,
943 .parent_map = gcc_parent_map_3,
944 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
945 .clkr.hw.init = &(struct clk_init_data){
946 .name = "gcc_vs_ctrl_clk_src",
947 .parent_names = gcc_parent_names_3,
948 .num_parents = 3,
949 .ops = &clk_rcg2_ops,
950 },
951};
952
953static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = {
954 F(19200000, P_BI_TCXO, 1, 0, 0),
955 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
956 F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
957 { }
958};
959
960static struct clk_rcg2 gcc_vsensor_clk_src = {
961 .cmd_rcgr = 0x7a018,
962 .mnd_width = 0,
963 .hid_width = 5,
964 .parent_map = gcc_parent_map_3,
965 .freq_tbl = ftbl_gcc_vsensor_clk_src,
966 .clkr.hw.init = &(struct clk_init_data){
967 .name = "gcc_vsensor_clk_src",
968 .parent_names = gcc_parent_names_8,
969 .num_parents = 3,
970 .ops = &clk_rcg2_ops,
971 },
972};
973
974static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
975 .halt_reg = 0x90014,
976 .halt_check = BRANCH_HALT,
977 .clkr = {
978 .enable_reg = 0x90014,
979 .enable_mask = BIT(0),
980 .hw.init = &(struct clk_init_data){
981 .name = "gcc_aggre_noc_pcie_tbu_clk",
982 .ops = &clk_branch2_ops,
983 },
984 },
985};
986
987static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
988 .halt_reg = 0x82028,
989 .halt_check = BRANCH_HALT,
990 .hwcg_reg = 0x82028,
991 .hwcg_bit = 1,
992 .clkr = {
993 .enable_reg = 0x82028,
994 .enable_mask = BIT(0),
995 .hw.init = &(struct clk_init_data){
996 .name = "gcc_aggre_ufs_card_axi_clk",
997 .parent_names = (const char *[]){
998 "gcc_ufs_card_axi_clk_src",
999 },
1000 .num_parents = 1,
1001 .flags = CLK_SET_RATE_PARENT,
1002 .ops = &clk_branch2_ops,
1003 },
1004 },
1005};
1006
1007static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1008 .halt_reg = 0x82024,
1009 .halt_check = BRANCH_HALT,
1010 .hwcg_reg = 0x82024,
1011 .hwcg_bit = 1,
1012 .clkr = {
1013 .enable_reg = 0x82024,
1014 .enable_mask = BIT(0),
1015 .hw.init = &(struct clk_init_data){
1016 .name = "gcc_aggre_ufs_phy_axi_clk",
1017 .parent_names = (const char *[]){
1018 "gcc_ufs_phy_axi_clk_src",
1019 },
1020 .num_parents = 1,
1021 .flags = CLK_SET_RATE_PARENT,
1022 .ops = &clk_branch2_ops,
1023 },
1024 },
1025};
1026
1027static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1028 .halt_reg = 0x8201c,
1029 .halt_check = BRANCH_HALT,
1030 .clkr = {
1031 .enable_reg = 0x8201c,
1032 .enable_mask = BIT(0),
1033 .hw.init = &(struct clk_init_data){
1034 .name = "gcc_aggre_usb3_prim_axi_clk",
1035 .parent_names = (const char *[]){
1036 "gcc_usb30_prim_master_clk_src",
1037 },
1038 .num_parents = 1,
1039 .flags = CLK_SET_RATE_PARENT,
1040 .ops = &clk_branch2_ops,
1041 },
1042 },
1043};
1044
1045static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1046 .halt_reg = 0x82020,
1047 .halt_check = BRANCH_HALT,
1048 .clkr = {
1049 .enable_reg = 0x82020,
1050 .enable_mask = BIT(0),
1051 .hw.init = &(struct clk_init_data){
1052 .name = "gcc_aggre_usb3_sec_axi_clk",
1053 .parent_names = (const char *[]){
1054 "gcc_usb30_sec_master_clk_src",
1055 },
1056 .num_parents = 1,
1057 .flags = CLK_SET_RATE_PARENT,
1058 .ops = &clk_branch2_ops,
1059 },
1060 },
1061};
1062
1063static struct clk_branch gcc_apc_vs_clk = {
1064 .halt_reg = 0x7a050,
1065 .halt_check = BRANCH_HALT,
1066 .clkr = {
1067 .enable_reg = 0x7a050,
1068 .enable_mask = BIT(0),
1069 .hw.init = &(struct clk_init_data){
1070 .name = "gcc_apc_vs_clk",
1071 .parent_names = (const char *[]){
1072 "gcc_vsensor_clk_src",
1073 },
1074 .num_parents = 1,
1075 .flags = CLK_SET_RATE_PARENT,
1076 .ops = &clk_branch2_ops,
1077 },
1078 },
1079};
1080
1081static struct clk_branch gcc_boot_rom_ahb_clk = {
1082 .halt_reg = 0x38004,
1083 .halt_check = BRANCH_HALT_VOTED,
1084 .hwcg_reg = 0x38004,
1085 .hwcg_bit = 1,
1086 .clkr = {
1087 .enable_reg = 0x52004,
1088 .enable_mask = BIT(10),
1089 .hw.init = &(struct clk_init_data){
1090 .name = "gcc_boot_rom_ahb_clk",
1091 .ops = &clk_branch2_ops,
1092 },
1093 },
1094};
1095
1096static struct clk_branch gcc_camera_ahb_clk = {
1097 .halt_reg = 0xb008,
1098 .halt_check = BRANCH_HALT,
1099 .hwcg_reg = 0xb008,
1100 .hwcg_bit = 1,
1101 .clkr = {
1102 .enable_reg = 0xb008,
1103 .enable_mask = BIT(0),
1104 .hw.init = &(struct clk_init_data){
1105 .name = "gcc_camera_ahb_clk",
1106 .ops = &clk_branch2_ops,
1107 },
1108 },
1109};
1110
1111static struct clk_branch gcc_camera_axi_clk = {
1112 .halt_reg = 0xb020,
1113 .halt_check = BRANCH_VOTED,
1114 .clkr = {
1115 .enable_reg = 0xb020,
1116 .enable_mask = BIT(0),
1117 .hw.init = &(struct clk_init_data){
1118 .name = "gcc_camera_axi_clk",
1119 .ops = &clk_branch2_ops,
1120 },
1121 },
1122};
1123
1124static struct clk_branch gcc_camera_xo_clk = {
1125 .halt_reg = 0xb02c,
1126 .halt_check = BRANCH_HALT,
1127 .clkr = {
1128 .enable_reg = 0xb02c,
1129 .enable_mask = BIT(0),
1130 .hw.init = &(struct clk_init_data){
1131 .name = "gcc_camera_xo_clk",
1132 .ops = &clk_branch2_ops,
1133 },
1134 },
1135};
1136
1137static struct clk_branch gcc_ce1_ahb_clk = {
1138 .halt_reg = 0x4100c,
1139 .halt_check = BRANCH_HALT_VOTED,
1140 .hwcg_reg = 0x4100c,
1141 .hwcg_bit = 1,
1142 .clkr = {
1143 .enable_reg = 0x52004,
1144 .enable_mask = BIT(3),
1145 .hw.init = &(struct clk_init_data){
1146 .name = "gcc_ce1_ahb_clk",
1147 .ops = &clk_branch2_ops,
1148 },
1149 },
1150};
1151
1152static struct clk_branch gcc_ce1_axi_clk = {
1153 .halt_reg = 0x41008,
1154 .halt_check = BRANCH_HALT_VOTED,
1155 .clkr = {
1156 .enable_reg = 0x52004,
1157 .enable_mask = BIT(4),
1158 .hw.init = &(struct clk_init_data){
1159 .name = "gcc_ce1_axi_clk",
1160 .ops = &clk_branch2_ops,
1161 },
1162 },
1163};
1164
1165static struct clk_branch gcc_ce1_clk = {
1166 .halt_reg = 0x41004,
1167 .halt_check = BRANCH_HALT_VOTED,
1168 .clkr = {
1169 .enable_reg = 0x52004,
1170 .enable_mask = BIT(5),
1171 .hw.init = &(struct clk_init_data){
1172 .name = "gcc_ce1_clk",
1173 .ops = &clk_branch2_ops,
1174 },
1175 },
1176};
1177
1178static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1179 .halt_reg = 0x502c,
1180 .halt_check = BRANCH_HALT,
1181 .clkr = {
1182 .enable_reg = 0x502c,
1183 .enable_mask = BIT(0),
1184 .hw.init = &(struct clk_init_data){
1185 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1186 .parent_names = (const char *[]){
1187 "gcc_usb30_prim_master_clk_src",
1188 },
1189 .num_parents = 1,
1190 .flags = CLK_SET_RATE_PARENT,
1191 .ops = &clk_branch2_ops,
1192 },
1193 },
1194};
1195
1196static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1197 .halt_reg = 0x5030,
1198 .halt_check = BRANCH_HALT,
1199 .clkr = {
1200 .enable_reg = 0x5030,
1201 .enable_mask = BIT(0),
1202 .hw.init = &(struct clk_init_data){
1203 .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1204 .parent_names = (const char *[]){
1205 "gcc_usb30_sec_master_clk_src",
1206 },
1207 .num_parents = 1,
1208 .flags = CLK_SET_RATE_PARENT,
1209 .ops = &clk_branch2_ops,
1210 },
1211 },
1212};
1213
1214static struct clk_branch gcc_cpuss_ahb_clk = {
1215 .halt_reg = 0x48000,
1216 .halt_check = BRANCH_HALT_VOTED,
1217 .clkr = {
1218 .enable_reg = 0x52004,
1219 .enable_mask = BIT(21),
1220 .hw.init = &(struct clk_init_data){
1221 .name = "gcc_cpuss_ahb_clk",
1222 .parent_names = (const char *[]){
1223 "gcc_cpuss_ahb_clk_src",
1224 },
1225 .num_parents = 1,
1226 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1227 .ops = &clk_branch2_ops,
1228 },
1229 },
1230};
1231
1232static struct clk_branch gcc_cpuss_rbcpr_clk = {
1233 .halt_reg = 0x48008,
1234 .halt_check = BRANCH_HALT,
1235 .clkr = {
1236 .enable_reg = 0x48008,
1237 .enable_mask = BIT(0),
1238 .hw.init = &(struct clk_init_data){
1239 .name = "gcc_cpuss_rbcpr_clk",
1240 .parent_names = (const char *[]){
1241 "gcc_cpuss_rbcpr_clk_src",
1242 },
1243 .num_parents = 1,
1244 .flags = CLK_SET_RATE_PARENT,
1245 .ops = &clk_branch2_ops,
1246 },
1247 },
1248};
1249
1250static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1251 .halt_reg = 0x44038,
1252 .halt_check = BRANCH_VOTED,
1253 .clkr = {
1254 .enable_reg = 0x44038,
1255 .enable_mask = BIT(0),
1256 .hw.init = &(struct clk_init_data){
1257 .name = "gcc_ddrss_gpu_axi_clk",
1258 .ops = &clk_branch2_ops,
1259 },
1260 },
1261};
1262
1263static struct clk_branch gcc_disp_ahb_clk = {
1264 .halt_reg = 0xb00c,
1265 .halt_check = BRANCH_HALT,
1266 .hwcg_reg = 0xb00c,
1267 .hwcg_bit = 1,
1268 .clkr = {
1269 .enable_reg = 0xb00c,
1270 .enable_mask = BIT(0),
1271 .hw.init = &(struct clk_init_data){
1272 .name = "gcc_disp_ahb_clk",
1273 .ops = &clk_branch2_ops,
1274 },
1275 },
1276};
1277
1278static struct clk_branch gcc_disp_axi_clk = {
1279 .halt_reg = 0xb024,
1280 .halt_check = BRANCH_VOTED,
1281 .clkr = {
1282 .enable_reg = 0xb024,
1283 .enable_mask = BIT(0),
1284 .hw.init = &(struct clk_init_data){
1285 .name = "gcc_disp_axi_clk",
1286 .ops = &clk_branch2_ops,
1287 },
1288 },
1289};
1290
1291static struct clk_branch gcc_disp_gpll0_clk_src = {
1292 .halt_check = BRANCH_HALT_DELAY,
1293 .clkr = {
1294 .enable_reg = 0x52004,
1295 .enable_mask = BIT(18),
1296 .hw.init = &(struct clk_init_data){
1297 .name = "gcc_disp_gpll0_clk_src",
1298 .parent_names = (const char *[]){
1299 "gpll0",
1300 },
1301 .num_parents = 1,
1302 .ops = &clk_branch2_ops,
1303 },
1304 },
1305};
1306
1307static struct clk_branch gcc_disp_gpll0_div_clk_src = {
1308 .halt_check = BRANCH_HALT_DELAY,
1309 .clkr = {
1310 .enable_reg = 0x52004,
1311 .enable_mask = BIT(19),
1312 .hw.init = &(struct clk_init_data){
1313 .name = "gcc_disp_gpll0_div_clk_src",
1314 .parent_names = (const char *[]){
1315 "gpll0_out_even",
1316 },
1317 .num_parents = 1,
1318 .ops = &clk_branch2_ops,
1319 },
1320 },
1321};
1322
1323static struct clk_branch gcc_disp_xo_clk = {
1324 .halt_reg = 0xb030,
1325 .halt_check = BRANCH_HALT,
1326 .clkr = {
1327 .enable_reg = 0xb030,
1328 .enable_mask = BIT(0),
1329 .hw.init = &(struct clk_init_data){
1330 .name = "gcc_disp_xo_clk",
1331 .ops = &clk_branch2_ops,
1332 },
1333 },
1334};
1335
1336static struct clk_branch gcc_gp1_clk = {
1337 .halt_reg = 0x64000,
1338 .halt_check = BRANCH_HALT,
1339 .clkr = {
1340 .enable_reg = 0x64000,
1341 .enable_mask = BIT(0),
1342 .hw.init = &(struct clk_init_data){
1343 .name = "gcc_gp1_clk",
1344 .parent_names = (const char *[]){
1345 "gcc_gp1_clk_src",
1346 },
1347 .num_parents = 1,
1348 .flags = CLK_SET_RATE_PARENT,
1349 .ops = &clk_branch2_ops,
1350 },
1351 },
1352};
1353
1354static struct clk_branch gcc_gp2_clk = {
1355 .halt_reg = 0x65000,
1356 .halt_check = BRANCH_HALT,
1357 .clkr = {
1358 .enable_reg = 0x65000,
1359 .enable_mask = BIT(0),
1360 .hw.init = &(struct clk_init_data){
1361 .name = "gcc_gp2_clk",
1362 .parent_names = (const char *[]){
1363 "gcc_gp2_clk_src",
1364 },
1365 .num_parents = 1,
1366 .flags = CLK_SET_RATE_PARENT,
1367 .ops = &clk_branch2_ops,
1368 },
1369 },
1370};
1371
1372static struct clk_branch gcc_gp3_clk = {
1373 .halt_reg = 0x66000,
1374 .halt_check = BRANCH_HALT,
1375 .clkr = {
1376 .enable_reg = 0x66000,
1377 .enable_mask = BIT(0),
1378 .hw.init = &(struct clk_init_data){
1379 .name = "gcc_gp3_clk",
1380 .parent_names = (const char *[]){
1381 "gcc_gp3_clk_src",
1382 },
1383 .num_parents = 1,
1384 .flags = CLK_SET_RATE_PARENT,
1385 .ops = &clk_branch2_ops,
1386 },
1387 },
1388};
1389
1390static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1391 .halt_reg = 0x71004,
1392 .halt_check = BRANCH_HALT,
1393 .hwcg_reg = 0x71004,
1394 .hwcg_bit = 1,
1395 .clkr = {
1396 .enable_reg = 0x71004,
1397 .enable_mask = BIT(0),
1398 .hw.init = &(struct clk_init_data){
1399 .name = "gcc_gpu_cfg_ahb_clk",
1400 .ops = &clk_branch2_ops,
1401 },
1402 },
1403};
1404
1405static struct clk_branch gcc_gpu_gpll0_clk_src = {
1406 .halt_check = BRANCH_HALT_DELAY,
1407 .clkr = {
1408 .enable_reg = 0x52004,
1409 .enable_mask = BIT(15),
1410 .hw.init = &(struct clk_init_data){
1411 .name = "gcc_gpu_gpll0_clk_src",
1412 .parent_names = (const char *[]){
1413 "gpll0",
1414 },
1415 .num_parents = 1,
1416 .ops = &clk_branch2_ops,
1417 },
1418 },
1419};
1420
1421static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1422 .halt_check = BRANCH_HALT_DELAY,
1423 .clkr = {
1424 .enable_reg = 0x52004,
1425 .enable_mask = BIT(16),
1426 .hw.init = &(struct clk_init_data){
1427 .name = "gcc_gpu_gpll0_div_clk_src",
1428 .parent_names = (const char *[]){
1429 "gpll0_out_even",
1430 },
1431 .num_parents = 1,
1432 .ops = &clk_branch2_ops,
1433 },
1434 },
1435};
1436
1437static struct clk_branch gcc_gpu_iref_clk = {
1438 .halt_reg = 0x8c010,
1439 .halt_check = BRANCH_HALT,
1440 .clkr = {
1441 .enable_reg = 0x8c010,
1442 .enable_mask = BIT(0),
1443 .hw.init = &(struct clk_init_data){
1444 .name = "gcc_gpu_iref_clk",
1445 .ops = &clk_branch2_ops,
1446 },
1447 },
1448};
1449
1450static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1451 .halt_reg = 0x7100c,
1452 .halt_check = BRANCH_VOTED,
1453 .clkr = {
1454 .enable_reg = 0x7100c,
1455 .enable_mask = BIT(0),
1456 .hw.init = &(struct clk_init_data){
1457 .name = "gcc_gpu_memnoc_gfx_clk",
1458 .ops = &clk_branch2_ops,
1459 },
1460 },
1461};
1462
1463static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1464 .halt_reg = 0x71018,
1465 .halt_check = BRANCH_HALT,
1466 .clkr = {
1467 .enable_reg = 0x71018,
1468 .enable_mask = BIT(0),
1469 .hw.init = &(struct clk_init_data){
1470 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1471 .ops = &clk_branch2_ops,
1472 },
1473 },
1474};
1475
1476static struct clk_branch gcc_gpu_vs_clk = {
1477 .halt_reg = 0x7a04c,
1478 .halt_check = BRANCH_HALT,
1479 .clkr = {
1480 .enable_reg = 0x7a04c,
1481 .enable_mask = BIT(0),
1482 .hw.init = &(struct clk_init_data){
1483 .name = "gcc_gpu_vs_clk",
1484 .parent_names = (const char *[]){
1485 "gcc_vsensor_clk_src",
1486 },
1487 .num_parents = 1,
1488 .flags = CLK_SET_RATE_PARENT,
1489 .ops = &clk_branch2_ops,
1490 },
1491 },
1492};
1493
1494static struct clk_branch gcc_mss_axis2_clk = {
1495 .halt_reg = 0x8a008,
1496 .halt_check = BRANCH_HALT,
1497 .clkr = {
1498 .enable_reg = 0x8a008,
1499 .enable_mask = BIT(0),
1500 .hw.init = &(struct clk_init_data){
1501 .name = "gcc_mss_axis2_clk",
1502 .ops = &clk_branch2_ops,
1503 },
1504 },
1505};
1506
1507static struct clk_branch gcc_mss_cfg_ahb_clk = {
1508 .halt_reg = 0x8a000,
1509 .halt_check = BRANCH_HALT,
1510 .hwcg_reg = 0x8a000,
1511 .hwcg_bit = 1,
1512 .clkr = {
1513 .enable_reg = 0x8a000,
1514 .enable_mask = BIT(0),
1515 .hw.init = &(struct clk_init_data){
1516 .name = "gcc_mss_cfg_ahb_clk",
1517 .ops = &clk_branch2_ops,
1518 },
1519 },
1520};
1521
1522static struct clk_branch gcc_mss_gpll0_div_clk_src = {
1523 .halt_check = BRANCH_HALT_DELAY,
1524 .clkr = {
1525 .enable_reg = 0x52004,
1526 .enable_mask = BIT(17),
1527 .hw.init = &(struct clk_init_data){
1528 .name = "gcc_mss_gpll0_div_clk_src",
1529 .ops = &clk_branch2_ops,
1530 },
1531 },
1532};
1533
1534static struct clk_branch gcc_mss_mfab_axis_clk = {
1535 .halt_reg = 0x8a004,
1536 .halt_check = BRANCH_VOTED,
1537 .hwcg_reg = 0x8a004,
1538 .hwcg_bit = 1,
1539 .clkr = {
1540 .enable_reg = 0x8a004,
1541 .enable_mask = BIT(0),
1542 .hw.init = &(struct clk_init_data){
1543 .name = "gcc_mss_mfab_axis_clk",
1544 .ops = &clk_branch2_ops,
1545 },
1546 },
1547};
1548
1549static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
1550 .halt_reg = 0x8a154,
1551 .halt_check = BRANCH_VOTED,
1552 .clkr = {
1553 .enable_reg = 0x8a154,
1554 .enable_mask = BIT(0),
1555 .hw.init = &(struct clk_init_data){
1556 .name = "gcc_mss_q6_memnoc_axi_clk",
1557 .ops = &clk_branch2_ops,
1558 },
1559 },
1560};
1561
1562static struct clk_branch gcc_mss_snoc_axi_clk = {
1563 .halt_reg = 0x8a150,
1564 .halt_check = BRANCH_HALT,
1565 .clkr = {
1566 .enable_reg = 0x8a150,
1567 .enable_mask = BIT(0),
1568 .hw.init = &(struct clk_init_data){
1569 .name = "gcc_mss_snoc_axi_clk",
1570 .ops = &clk_branch2_ops,
1571 },
1572 },
1573};
1574
1575static struct clk_branch gcc_mss_vs_clk = {
1576 .halt_reg = 0x7a048,
1577 .halt_check = BRANCH_HALT,
1578 .clkr = {
1579 .enable_reg = 0x7a048,
1580 .enable_mask = BIT(0),
1581 .hw.init = &(struct clk_init_data){
1582 .name = "gcc_mss_vs_clk",
1583 .parent_names = (const char *[]){
1584 "gcc_vsensor_clk_src",
1585 },
1586 .num_parents = 1,
1587 .flags = CLK_SET_RATE_PARENT,
1588 .ops = &clk_branch2_ops,
1589 },
1590 },
1591};
1592
1593static struct clk_branch gcc_pcie_0_aux_clk = {
1594 .halt_reg = 0x6b01c,
1595 .halt_check = BRANCH_HALT_VOTED,
1596 .clkr = {
1597 .enable_reg = 0x5200c,
1598 .enable_mask = BIT(3),
1599 .hw.init = &(struct clk_init_data){
1600 .name = "gcc_pcie_0_aux_clk",
1601 .parent_names = (const char *[]){
1602 "gcc_pcie_0_aux_clk_src",
1603 },
1604 .num_parents = 1,
1605 .flags = CLK_SET_RATE_PARENT,
1606 .ops = &clk_branch2_ops,
1607 },
1608 },
1609};
1610
1611static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1612 .halt_reg = 0x6b018,
1613 .halt_check = BRANCH_HALT_VOTED,
1614 .hwcg_reg = 0x6b018,
1615 .hwcg_bit = 1,
1616 .clkr = {
1617 .enable_reg = 0x5200c,
1618 .enable_mask = BIT(2),
1619 .hw.init = &(struct clk_init_data){
1620 .name = "gcc_pcie_0_cfg_ahb_clk",
1621 .ops = &clk_branch2_ops,
1622 },
1623 },
1624};
1625
1626static struct clk_branch gcc_pcie_0_clkref_clk = {
1627 .halt_reg = 0x8c00c,
1628 .halt_check = BRANCH_HALT,
1629 .clkr = {
1630 .enable_reg = 0x8c00c,
1631 .enable_mask = BIT(0),
1632 .hw.init = &(struct clk_init_data){
1633 .name = "gcc_pcie_0_clkref_clk",
1634 .ops = &clk_branch2_ops,
1635 },
1636 },
1637};
1638
1639static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1640 .halt_reg = 0x6b014,
1641 .halt_check = BRANCH_HALT_VOTED,
1642 .clkr = {
1643 .enable_reg = 0x5200c,
1644 .enable_mask = BIT(1),
1645 .hw.init = &(struct clk_init_data){
1646 .name = "gcc_pcie_0_mstr_axi_clk",
1647 .ops = &clk_branch2_ops,
1648 },
1649 },
1650};
1651
1652static struct clk_branch gcc_pcie_0_pipe_clk = {
1653 .halt_check = BRANCH_HALT_SKIP,
1654 .clkr = {
1655 .enable_reg = 0x5200c,
1656 .enable_mask = BIT(4),
1657 .hw.init = &(struct clk_init_data){
1658 .name = "gcc_pcie_0_pipe_clk",
1659 .ops = &clk_branch2_ops,
1660 },
1661 },
1662};
1663
1664static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1665 .halt_reg = 0x6b010,
1666 .halt_check = BRANCH_HALT_VOTED,
1667 .hwcg_reg = 0x6b010,
1668 .hwcg_bit = 1,
1669 .clkr = {
1670 .enable_reg = 0x5200c,
1671 .enable_mask = BIT(0),
1672 .hw.init = &(struct clk_init_data){
1673 .name = "gcc_pcie_0_slv_axi_clk",
1674 .ops = &clk_branch2_ops,
1675 },
1676 },
1677};
1678
1679static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1680 .halt_reg = 0x6b00c,
1681 .halt_check = BRANCH_HALT_VOTED,
1682 .clkr = {
1683 .enable_reg = 0x5200c,
1684 .enable_mask = BIT(5),
1685 .hw.init = &(struct clk_init_data){
1686 .name = "gcc_pcie_0_slv_q2a_axi_clk",
1687 .ops = &clk_branch2_ops,
1688 },
1689 },
1690};
1691
1692static struct clk_branch gcc_pcie_1_aux_clk = {
1693 .halt_reg = 0x8d01c,
1694 .halt_check = BRANCH_HALT_VOTED,
1695 .clkr = {
1696 .enable_reg = 0x52004,
1697 .enable_mask = BIT(29),
1698 .hw.init = &(struct clk_init_data){
1699 .name = "gcc_pcie_1_aux_clk",
1700 .parent_names = (const char *[]){
1701 "gcc_pcie_1_aux_clk_src",
1702 },
1703 .num_parents = 1,
1704 .flags = CLK_SET_RATE_PARENT,
1705 .ops = &clk_branch2_ops,
1706 },
1707 },
1708};
1709
1710static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1711 .halt_reg = 0x8d018,
1712 .halt_check = BRANCH_HALT_VOTED,
1713 .hwcg_reg = 0x8d018,
1714 .hwcg_bit = 1,
1715 .clkr = {
1716 .enable_reg = 0x52004,
1717 .enable_mask = BIT(28),
1718 .hw.init = &(struct clk_init_data){
1719 .name = "gcc_pcie_1_cfg_ahb_clk",
1720 .ops = &clk_branch2_ops,
1721 },
1722 },
1723};
1724
1725static struct clk_branch gcc_pcie_1_clkref_clk = {
1726 .halt_reg = 0x8c02c,
1727 .halt_check = BRANCH_HALT,
1728 .clkr = {
1729 .enable_reg = 0x8c02c,
1730 .enable_mask = BIT(0),
1731 .hw.init = &(struct clk_init_data){
1732 .name = "gcc_pcie_1_clkref_clk",
1733 .ops = &clk_branch2_ops,
1734 },
1735 },
1736};
1737
1738static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1739 .halt_reg = 0x8d014,
1740 .halt_check = BRANCH_HALT_VOTED,
1741 .clkr = {
1742 .enable_reg = 0x52004,
1743 .enable_mask = BIT(27),
1744 .hw.init = &(struct clk_init_data){
1745 .name = "gcc_pcie_1_mstr_axi_clk",
1746 .ops = &clk_branch2_ops,
1747 },
1748 },
1749};
1750
1751static struct clk_branch gcc_pcie_1_pipe_clk = {
1752 .halt_check = BRANCH_HALT_SKIP,
1753 .clkr = {
1754 .enable_reg = 0x52004,
1755 .enable_mask = BIT(30),
1756 .hw.init = &(struct clk_init_data){
1757 .name = "gcc_pcie_1_pipe_clk",
1758 .ops = &clk_branch2_ops,
1759 },
1760 },
1761};
1762
1763static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1764 .halt_reg = 0x8d010,
1765 .halt_check = BRANCH_HALT_VOTED,
1766 .hwcg_reg = 0x8d010,
1767 .hwcg_bit = 1,
1768 .clkr = {
1769 .enable_reg = 0x52004,
1770 .enable_mask = BIT(26),
1771 .hw.init = &(struct clk_init_data){
1772 .name = "gcc_pcie_1_slv_axi_clk",
1773 .ops = &clk_branch2_ops,
1774 },
1775 },
1776};
1777
1778static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1779 .halt_reg = 0x8d00c,
1780 .halt_check = BRANCH_HALT_VOTED,
1781 .clkr = {
1782 .enable_reg = 0x52004,
1783 .enable_mask = BIT(25),
1784 .hw.init = &(struct clk_init_data){
1785 .name = "gcc_pcie_1_slv_q2a_axi_clk",
1786 .ops = &clk_branch2_ops,
1787 },
1788 },
1789};
1790
1791static struct clk_branch gcc_pcie_phy_aux_clk = {
1792 .halt_reg = 0x6f004,
1793 .halt_check = BRANCH_HALT,
1794 .clkr = {
1795 .enable_reg = 0x6f004,
1796 .enable_mask = BIT(0),
1797 .hw.init = &(struct clk_init_data){
1798 .name = "gcc_pcie_phy_aux_clk",
1799 .parent_names = (const char *[]){
1800 "gcc_pcie_0_aux_clk_src",
1801 },
1802 .num_parents = 1,
1803 .flags = CLK_SET_RATE_PARENT,
1804 .ops = &clk_branch2_ops,
1805 },
1806 },
1807};
1808
1809static struct clk_branch gcc_pcie_phy_refgen_clk = {
1810 .halt_reg = 0x6f02c,
1811 .halt_check = BRANCH_HALT,
1812 .clkr = {
1813 .enable_reg = 0x6f02c,
1814 .enable_mask = BIT(0),
1815 .hw.init = &(struct clk_init_data){
1816 .name = "gcc_pcie_phy_refgen_clk",
1817 .parent_names = (const char *[]){
1818 "gcc_pcie_phy_refgen_clk_src",
1819 },
1820 .num_parents = 1,
1821 .flags = CLK_SET_RATE_PARENT,
1822 .ops = &clk_branch2_ops,
1823 },
1824 },
1825};
1826
1827static struct clk_branch gcc_pdm2_clk = {
1828 .halt_reg = 0x3300c,
1829 .halt_check = BRANCH_HALT,
1830 .clkr = {
1831 .enable_reg = 0x3300c,
1832 .enable_mask = BIT(0),
1833 .hw.init = &(struct clk_init_data){
1834 .name = "gcc_pdm2_clk",
1835 .parent_names = (const char *[]){
1836 "gcc_pdm2_clk_src",
1837 },
1838 .num_parents = 1,
1839 .flags = CLK_SET_RATE_PARENT,
1840 .ops = &clk_branch2_ops,
1841 },
1842 },
1843};
1844
1845static struct clk_branch gcc_pdm_ahb_clk = {
1846 .halt_reg = 0x33004,
1847 .halt_check = BRANCH_HALT,
1848 .hwcg_reg = 0x33004,
1849 .hwcg_bit = 1,
1850 .clkr = {
1851 .enable_reg = 0x33004,
1852 .enable_mask = BIT(0),
1853 .hw.init = &(struct clk_init_data){
1854 .name = "gcc_pdm_ahb_clk",
1855 .ops = &clk_branch2_ops,
1856 },
1857 },
1858};
1859
1860static struct clk_branch gcc_pdm_xo4_clk = {
1861 .halt_reg = 0x33008,
1862 .halt_check = BRANCH_HALT,
1863 .clkr = {
1864 .enable_reg = 0x33008,
1865 .enable_mask = BIT(0),
1866 .hw.init = &(struct clk_init_data){
1867 .name = "gcc_pdm_xo4_clk",
1868 .ops = &clk_branch2_ops,
1869 },
1870 },
1871};
1872
1873static struct clk_branch gcc_prng_ahb_clk = {
1874 .halt_reg = 0x34004,
1875 .halt_check = BRANCH_HALT_VOTED,
1876 .hwcg_reg = 0x34004,
1877 .hwcg_bit = 1,
1878 .clkr = {
1879 .enable_reg = 0x52004,
1880 .enable_mask = BIT(13),
1881 .hw.init = &(struct clk_init_data){
1882 .name = "gcc_prng_ahb_clk",
1883 .ops = &clk_branch2_ops,
1884 },
1885 },
1886};
1887
1888static struct clk_branch gcc_qmip_camera_ahb_clk = {
1889 .halt_reg = 0xb014,
1890 .halt_check = BRANCH_HALT,
1891 .hwcg_reg = 0xb014,
1892 .hwcg_bit = 1,
1893 .clkr = {
1894 .enable_reg = 0xb014,
1895 .enable_mask = BIT(0),
1896 .hw.init = &(struct clk_init_data){
1897 .name = "gcc_qmip_camera_ahb_clk",
1898 .ops = &clk_branch2_ops,
1899 },
1900 },
1901};
1902
1903static struct clk_branch gcc_qmip_disp_ahb_clk = {
1904 .halt_reg = 0xb018,
1905 .halt_check = BRANCH_HALT,
1906 .hwcg_reg = 0xb018,
1907 .hwcg_bit = 1,
1908 .clkr = {
1909 .enable_reg = 0xb018,
1910 .enable_mask = BIT(0),
1911 .hw.init = &(struct clk_init_data){
1912 .name = "gcc_qmip_disp_ahb_clk",
1913 .ops = &clk_branch2_ops,
1914 },
1915 },
1916};
1917
1918static struct clk_branch gcc_qmip_video_ahb_clk = {
1919 .halt_reg = 0xb010,
1920 .halt_check = BRANCH_HALT,
1921 .hwcg_reg = 0xb010,
1922 .hwcg_bit = 1,
1923 .clkr = {
1924 .enable_reg = 0xb010,
1925 .enable_mask = BIT(0),
1926 .hw.init = &(struct clk_init_data){
1927 .name = "gcc_qmip_video_ahb_clk",
1928 .ops = &clk_branch2_ops,
1929 },
1930 },
1931};
1932
1933static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1934 .halt_reg = 0x17030,
1935 .halt_check = BRANCH_HALT_VOTED,
1936 .clkr = {
1937 .enable_reg = 0x5200c,
1938 .enable_mask = BIT(10),
1939 .hw.init = &(struct clk_init_data){
1940 .name = "gcc_qupv3_wrap0_s0_clk",
1941 .parent_names = (const char *[]){
1942 "gcc_qupv3_wrap0_s0_clk_src",
1943 },
1944 .num_parents = 1,
1945 .flags = CLK_SET_RATE_PARENT,
1946 .ops = &clk_branch2_ops,
1947 },
1948 },
1949};
1950
1951static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
1952 .halt_reg = 0x17160,
1953 .halt_check = BRANCH_HALT_VOTED,
1954 .clkr = {
1955 .enable_reg = 0x5200c,
1956 .enable_mask = BIT(11),
1957 .hw.init = &(struct clk_init_data){
1958 .name = "gcc_qupv3_wrap0_s1_clk",
1959 .parent_names = (const char *[]){
1960 "gcc_qupv3_wrap0_s1_clk_src",
1961 },
1962 .num_parents = 1,
1963 .flags = CLK_SET_RATE_PARENT,
1964 .ops = &clk_branch2_ops,
1965 },
1966 },
1967};
1968
1969static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
1970 .halt_reg = 0x17290,
1971 .halt_check = BRANCH_HALT_VOTED,
1972 .clkr = {
1973 .enable_reg = 0x5200c,
1974 .enable_mask = BIT(12),
1975 .hw.init = &(struct clk_init_data){
1976 .name = "gcc_qupv3_wrap0_s2_clk",
1977 .parent_names = (const char *[]){
1978 "gcc_qupv3_wrap0_s2_clk_src",
1979 },
1980 .num_parents = 1,
1981 .flags = CLK_SET_RATE_PARENT,
1982 .ops = &clk_branch2_ops,
1983 },
1984 },
1985};
1986
1987static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
1988 .halt_reg = 0x173c0,
1989 .halt_check = BRANCH_HALT_VOTED,
1990 .clkr = {
1991 .enable_reg = 0x5200c,
1992 .enable_mask = BIT(13),
1993 .hw.init = &(struct clk_init_data){
1994 .name = "gcc_qupv3_wrap0_s3_clk",
1995 .parent_names = (const char *[]){
1996 "gcc_qupv3_wrap0_s3_clk_src",
1997 },
1998 .num_parents = 1,
1999 .flags = CLK_SET_RATE_PARENT,
2000 .ops = &clk_branch2_ops,
2001 },
2002 },
2003};
2004
2005static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2006 .halt_reg = 0x174f0,
2007 .halt_check = BRANCH_HALT_VOTED,
2008 .clkr = {
2009 .enable_reg = 0x5200c,
2010 .enable_mask = BIT(14),
2011 .hw.init = &(struct clk_init_data){
2012 .name = "gcc_qupv3_wrap0_s4_clk",
2013 .parent_names = (const char *[]){
2014 "gcc_qupv3_wrap0_s4_clk_src",
2015 },
2016 .num_parents = 1,
2017 .flags = CLK_SET_RATE_PARENT,
2018 .ops = &clk_branch2_ops,
2019 },
2020 },
2021};
2022
2023static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2024 .halt_reg = 0x17620,
2025 .halt_check = BRANCH_HALT_VOTED,
2026 .clkr = {
2027 .enable_reg = 0x5200c,
2028 .enable_mask = BIT(15),
2029 .hw.init = &(struct clk_init_data){
2030 .name = "gcc_qupv3_wrap0_s5_clk",
2031 .parent_names = (const char *[]){
2032 "gcc_qupv3_wrap0_s5_clk_src",
2033 },
2034 .num_parents = 1,
2035 .flags = CLK_SET_RATE_PARENT,
2036 .ops = &clk_branch2_ops,
2037 },
2038 },
2039};
2040
2041static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2042 .halt_reg = 0x17750,
2043 .halt_check = BRANCH_HALT_VOTED,
2044 .clkr = {
2045 .enable_reg = 0x5200c,
2046 .enable_mask = BIT(16),
2047 .hw.init = &(struct clk_init_data){
2048 .name = "gcc_qupv3_wrap0_s6_clk",
2049 .parent_names = (const char *[]){
2050 "gcc_qupv3_wrap0_s6_clk_src",
2051 },
2052 .num_parents = 1,
2053 .flags = CLK_SET_RATE_PARENT,
2054 .ops = &clk_branch2_ops,
2055 },
2056 },
2057};
2058
2059static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2060 .halt_reg = 0x17880,
2061 .halt_check = BRANCH_HALT_VOTED,
2062 .clkr = {
2063 .enable_reg = 0x5200c,
2064 .enable_mask = BIT(17),
2065 .hw.init = &(struct clk_init_data){
2066 .name = "gcc_qupv3_wrap0_s7_clk",
2067 .parent_names = (const char *[]){
2068 "gcc_qupv3_wrap0_s7_clk_src",
2069 },
2070 .num_parents = 1,
2071 .flags = CLK_SET_RATE_PARENT,
2072 .ops = &clk_branch2_ops,
2073 },
2074 },
2075};
2076
2077static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2078 .halt_reg = 0x18014,
2079 .halt_check = BRANCH_HALT_VOTED,
2080 .clkr = {
2081 .enable_reg = 0x5200c,
2082 .enable_mask = BIT(22),
2083 .hw.init = &(struct clk_init_data){
2084 .name = "gcc_qupv3_wrap1_s0_clk",
2085 .parent_names = (const char *[]){
2086 "gcc_qupv3_wrap1_s0_clk_src",
2087 },
2088 .num_parents = 1,
2089 .flags = CLK_SET_RATE_PARENT,
2090 .ops = &clk_branch2_ops,
2091 },
2092 },
2093};
2094
2095static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2096 .halt_reg = 0x18144,
2097 .halt_check = BRANCH_HALT_VOTED,
2098 .clkr = {
2099 .enable_reg = 0x5200c,
2100 .enable_mask = BIT(23),
2101 .hw.init = &(struct clk_init_data){
2102 .name = "gcc_qupv3_wrap1_s1_clk",
2103 .parent_names = (const char *[]){
2104 "gcc_qupv3_wrap1_s1_clk_src",
2105 },
2106 .num_parents = 1,
2107 .flags = CLK_SET_RATE_PARENT,
2108 .ops = &clk_branch2_ops,
2109 },
2110 },
2111};
2112
2113static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2114 .halt_reg = 0x18274,
2115 .halt_check = BRANCH_HALT_VOTED,
2116 .clkr = {
2117 .enable_reg = 0x5200c,
2118 .enable_mask = BIT(24),
2119 .hw.init = &(struct clk_init_data){
2120 .name = "gcc_qupv3_wrap1_s2_clk",
2121 .parent_names = (const char *[]){
2122 "gcc_qupv3_wrap1_s2_clk_src",
2123 },
2124 .num_parents = 1,
2125 .flags = CLK_SET_RATE_PARENT,
2126 .ops = &clk_branch2_ops,
2127 },
2128 },
2129};
2130
2131static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2132 .halt_reg = 0x183a4,
2133 .halt_check = BRANCH_HALT_VOTED,
2134 .clkr = {
2135 .enable_reg = 0x5200c,
2136 .enable_mask = BIT(25),
2137 .hw.init = &(struct clk_init_data){
2138 .name = "gcc_qupv3_wrap1_s3_clk",
2139 .parent_names = (const char *[]){
2140 "gcc_qupv3_wrap1_s3_clk_src",
2141 },
2142 .num_parents = 1,
2143 .flags = CLK_SET_RATE_PARENT,
2144 .ops = &clk_branch2_ops,
2145 },
2146 },
2147};
2148
2149static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2150 .halt_reg = 0x184d4,
2151 .halt_check = BRANCH_HALT_VOTED,
2152 .clkr = {
2153 .enable_reg = 0x5200c,
2154 .enable_mask = BIT(26),
2155 .hw.init = &(struct clk_init_data){
2156 .name = "gcc_qupv3_wrap1_s4_clk",
2157 .parent_names = (const char *[]){
2158 "gcc_qupv3_wrap1_s4_clk_src",
2159 },
2160 .num_parents = 1,
2161 .flags = CLK_SET_RATE_PARENT,
2162 .ops = &clk_branch2_ops,
2163 },
2164 },
2165};
2166
2167static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2168 .halt_reg = 0x18604,
2169 .halt_check = BRANCH_HALT_VOTED,
2170 .clkr = {
2171 .enable_reg = 0x5200c,
2172 .enable_mask = BIT(27),
2173 .hw.init = &(struct clk_init_data){
2174 .name = "gcc_qupv3_wrap1_s5_clk",
2175 .parent_names = (const char *[]){
2176 "gcc_qupv3_wrap1_s5_clk_src",
2177 },
2178 .num_parents = 1,
2179 .flags = CLK_SET_RATE_PARENT,
2180 .ops = &clk_branch2_ops,
2181 },
2182 },
2183};
2184
2185static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2186 .halt_reg = 0x18734,
2187 .halt_check = BRANCH_HALT_VOTED,
2188 .clkr = {
2189 .enable_reg = 0x5200c,
2190 .enable_mask = BIT(28),
2191 .hw.init = &(struct clk_init_data){
2192 .name = "gcc_qupv3_wrap1_s6_clk",
2193 .parent_names = (const char *[]){
2194 "gcc_qupv3_wrap1_s6_clk_src",
2195 },
2196 .num_parents = 1,
2197 .flags = CLK_SET_RATE_PARENT,
2198 .ops = &clk_branch2_ops,
2199 },
2200 },
2201};
2202
2203static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
2204 .halt_reg = 0x18864,
2205 .halt_check = BRANCH_HALT_VOTED,
2206 .clkr = {
2207 .enable_reg = 0x5200c,
2208 .enable_mask = BIT(29),
2209 .hw.init = &(struct clk_init_data){
2210 .name = "gcc_qupv3_wrap1_s7_clk",
2211 .parent_names = (const char *[]){
2212 "gcc_qupv3_wrap1_s7_clk_src",
2213 },
2214 .num_parents = 1,
2215 .flags = CLK_SET_RATE_PARENT,
2216 .ops = &clk_branch2_ops,
2217 },
2218 },
2219};
2220
2221static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2222 .halt_reg = 0x17004,
2223 .halt_check = BRANCH_HALT_VOTED,
2224 .clkr = {
2225 .enable_reg = 0x5200c,
2226 .enable_mask = BIT(6),
2227 .hw.init = &(struct clk_init_data){
2228 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2229 .ops = &clk_branch2_ops,
2230 },
2231 },
2232};
2233
2234static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2235 .halt_reg = 0x17008,
2236 .halt_check = BRANCH_HALT_VOTED,
2237 .hwcg_reg = 0x17008,
2238 .hwcg_bit = 1,
2239 .clkr = {
2240 .enable_reg = 0x5200c,
2241 .enable_mask = BIT(7),
2242 .hw.init = &(struct clk_init_data){
2243 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2244 .ops = &clk_branch2_ops,
2245 },
2246 },
2247};
2248
2249static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2250 .halt_reg = 0x1800c,
2251 .halt_check = BRANCH_HALT_VOTED,
2252 .clkr = {
2253 .enable_reg = 0x5200c,
2254 .enable_mask = BIT(20),
2255 .hw.init = &(struct clk_init_data){
2256 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2257 .ops = &clk_branch2_ops,
2258 },
2259 },
2260};
2261
2262static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2263 .halt_reg = 0x18010,
2264 .halt_check = BRANCH_HALT_VOTED,
2265 .hwcg_reg = 0x18010,
2266 .hwcg_bit = 1,
2267 .clkr = {
2268 .enable_reg = 0x5200c,
2269 .enable_mask = BIT(21),
2270 .hw.init = &(struct clk_init_data){
2271 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2272 .ops = &clk_branch2_ops,
2273 },
2274 },
2275};
2276
2277static struct clk_branch gcc_sdcc2_ahb_clk = {
2278 .halt_reg = 0x14008,
2279 .halt_check = BRANCH_HALT,
2280 .clkr = {
2281 .enable_reg = 0x14008,
2282 .enable_mask = BIT(0),
2283 .hw.init = &(struct clk_init_data){
2284 .name = "gcc_sdcc2_ahb_clk",
2285 .ops = &clk_branch2_ops,
2286 },
2287 },
2288};
2289
2290static struct clk_branch gcc_sdcc2_apps_clk = {
2291 .halt_reg = 0x14004,
2292 .halt_check = BRANCH_HALT,
2293 .clkr = {
2294 .enable_reg = 0x14004,
2295 .enable_mask = BIT(0),
2296 .hw.init = &(struct clk_init_data){
2297 .name = "gcc_sdcc2_apps_clk",
2298 .parent_names = (const char *[]){
2299 "gcc_sdcc2_apps_clk_src",
2300 },
2301 .num_parents = 1,
2302 .flags = CLK_SET_RATE_PARENT,
2303 .ops = &clk_branch2_ops,
2304 },
2305 },
2306};
2307
2308static struct clk_branch gcc_sdcc4_ahb_clk = {
2309 .halt_reg = 0x16008,
2310 .halt_check = BRANCH_HALT,
2311 .clkr = {
2312 .enable_reg = 0x16008,
2313 .enable_mask = BIT(0),
2314 .hw.init = &(struct clk_init_data){
2315 .name = "gcc_sdcc4_ahb_clk",
2316 .ops = &clk_branch2_ops,
2317 },
2318 },
2319};
2320
2321static struct clk_branch gcc_sdcc4_apps_clk = {
2322 .halt_reg = 0x16004,
2323 .halt_check = BRANCH_HALT,
2324 .clkr = {
2325 .enable_reg = 0x16004,
2326 .enable_mask = BIT(0),
2327 .hw.init = &(struct clk_init_data){
2328 .name = "gcc_sdcc4_apps_clk",
2329 .parent_names = (const char *[]){
2330 "gcc_sdcc4_apps_clk_src",
2331 },
2332 .num_parents = 1,
2333 .flags = CLK_SET_RATE_PARENT,
2334 .ops = &clk_branch2_ops,
2335 },
2336 },
2337};
2338
2339static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2340 .halt_reg = 0x414c,
2341 .halt_check = BRANCH_HALT_VOTED,
2342 .clkr = {
2343 .enable_reg = 0x52004,
2344 .enable_mask = BIT(0),
2345 .hw.init = &(struct clk_init_data){
2346 .name = "gcc_sys_noc_cpuss_ahb_clk",
2347 .parent_names = (const char *[]){
2348 "gcc_cpuss_ahb_clk_src",
2349 },
2350 .num_parents = 1,
2351 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2352 .ops = &clk_branch2_ops,
2353 },
2354 },
2355};
2356
2357static struct clk_branch gcc_tsif_ahb_clk = {
2358 .halt_reg = 0x36004,
2359 .halt_check = BRANCH_HALT,
2360 .clkr = {
2361 .enable_reg = 0x36004,
2362 .enable_mask = BIT(0),
2363 .hw.init = &(struct clk_init_data){
2364 .name = "gcc_tsif_ahb_clk",
2365 .ops = &clk_branch2_ops,
2366 },
2367 },
2368};
2369
2370static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2371 .halt_reg = 0x3600c,
2372 .halt_check = BRANCH_HALT,
2373 .clkr = {
2374 .enable_reg = 0x3600c,
2375 .enable_mask = BIT(0),
2376 .hw.init = &(struct clk_init_data){
2377 .name = "gcc_tsif_inactivity_timers_clk",
2378 .ops = &clk_branch2_ops,
2379 },
2380 },
2381};
2382
2383static struct clk_branch gcc_tsif_ref_clk = {
2384 .halt_reg = 0x36008,
2385 .halt_check = BRANCH_HALT,
2386 .clkr = {
2387 .enable_reg = 0x36008,
2388 .enable_mask = BIT(0),
2389 .hw.init = &(struct clk_init_data){
2390 .name = "gcc_tsif_ref_clk",
2391 .parent_names = (const char *[]){
2392 "gcc_tsif_ref_clk_src",
2393 },
2394 .num_parents = 1,
2395 .flags = CLK_SET_RATE_PARENT,
2396 .ops = &clk_branch2_ops,
2397 },
2398 },
2399};
2400
2401static struct clk_branch gcc_ufs_card_ahb_clk = {
2402 .halt_reg = 0x75010,
2403 .halt_check = BRANCH_HALT,
2404 .hwcg_reg = 0x75010,
2405 .hwcg_bit = 1,
2406 .clkr = {
2407 .enable_reg = 0x75010,
2408 .enable_mask = BIT(0),
2409 .hw.init = &(struct clk_init_data){
2410 .name = "gcc_ufs_card_ahb_clk",
2411 .ops = &clk_branch2_ops,
2412 },
2413 },
2414};
2415
2416static struct clk_branch gcc_ufs_card_axi_clk = {
2417 .halt_reg = 0x7500c,
2418 .halt_check = BRANCH_HALT,
2419 .hwcg_reg = 0x7500c,
2420 .hwcg_bit = 1,
2421 .clkr = {
2422 .enable_reg = 0x7500c,
2423 .enable_mask = BIT(0),
2424 .hw.init = &(struct clk_init_data){
2425 .name = "gcc_ufs_card_axi_clk",
2426 .parent_names = (const char *[]){
2427 "gcc_ufs_card_axi_clk_src",
2428 },
2429 .num_parents = 1,
2430 .flags = CLK_SET_RATE_PARENT,
2431 .ops = &clk_branch2_ops,
2432 },
2433 },
2434};
2435
2436static struct clk_branch gcc_ufs_card_clkref_clk = {
2437 .halt_reg = 0x8c004,
2438 .halt_check = BRANCH_HALT,
2439 .clkr = {
2440 .enable_reg = 0x8c004,
2441 .enable_mask = BIT(0),
2442 .hw.init = &(struct clk_init_data){
2443 .name = "gcc_ufs_card_clkref_clk",
2444 .ops = &clk_branch2_ops,
2445 },
2446 },
2447};
2448
2449static struct clk_branch gcc_ufs_card_ice_core_clk = {
2450 .halt_reg = 0x75058,
2451 .halt_check = BRANCH_HALT,
2452 .hwcg_reg = 0x75058,
2453 .hwcg_bit = 1,
2454 .clkr = {
2455 .enable_reg = 0x75058,
2456 .enable_mask = BIT(0),
2457 .hw.init = &(struct clk_init_data){
2458 .name = "gcc_ufs_card_ice_core_clk",
2459 .parent_names = (const char *[]){
2460 "gcc_ufs_card_ice_core_clk_src",
2461 },
2462 .num_parents = 1,
2463 .flags = CLK_SET_RATE_PARENT,
2464 .ops = &clk_branch2_ops,
2465 },
2466 },
2467};
2468
2469static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2470 .halt_reg = 0x7508c,
2471 .halt_check = BRANCH_HALT,
2472 .hwcg_reg = 0x7508c,
2473 .hwcg_bit = 1,
2474 .clkr = {
2475 .enable_reg = 0x7508c,
2476 .enable_mask = BIT(0),
2477 .hw.init = &(struct clk_init_data){
2478 .name = "gcc_ufs_card_phy_aux_clk",
2479 .parent_names = (const char *[]){
2480 "gcc_ufs_card_phy_aux_clk_src",
2481 },
2482 .num_parents = 1,
2483 .flags = CLK_SET_RATE_PARENT,
2484 .ops = &clk_branch2_ops,
2485 },
2486 },
2487};
2488
2489static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
2490 .halt_check = BRANCH_HALT_SKIP,
2491 .clkr = {
2492 .enable_reg = 0x75018,
2493 .enable_mask = BIT(0),
2494 .hw.init = &(struct clk_init_data){
2495 .name = "gcc_ufs_card_rx_symbol_0_clk",
2496 .ops = &clk_branch2_ops,
2497 },
2498 },
2499};
2500
2501static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
2502 .halt_check = BRANCH_HALT_SKIP,
2503 .clkr = {
2504 .enable_reg = 0x750a8,
2505 .enable_mask = BIT(0),
2506 .hw.init = &(struct clk_init_data){
2507 .name = "gcc_ufs_card_rx_symbol_1_clk",
2508 .ops = &clk_branch2_ops,
2509 },
2510 },
2511};
2512
2513static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
2514 .halt_check = BRANCH_HALT_SKIP,
2515 .clkr = {
2516 .enable_reg = 0x75014,
2517 .enable_mask = BIT(0),
2518 .hw.init = &(struct clk_init_data){
2519 .name = "gcc_ufs_card_tx_symbol_0_clk",
2520 .ops = &clk_branch2_ops,
2521 },
2522 },
2523};
2524
2525static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2526 .halt_reg = 0x75054,
2527 .halt_check = BRANCH_HALT,
2528 .hwcg_reg = 0x75054,
2529 .hwcg_bit = 1,
2530 .clkr = {
2531 .enable_reg = 0x75054,
2532 .enable_mask = BIT(0),
2533 .hw.init = &(struct clk_init_data){
2534 .name = "gcc_ufs_card_unipro_core_clk",
2535 .parent_names = (const char *[]){
2536 "gcc_ufs_card_unipro_core_clk_src",
2537 },
2538 .num_parents = 1,
2539 .flags = CLK_SET_RATE_PARENT,
2540 .ops = &clk_branch2_ops,
2541 },
2542 },
2543};
2544
2545static struct clk_branch gcc_ufs_mem_clkref_clk = {
2546 .halt_reg = 0x8c000,
2547 .halt_check = BRANCH_HALT,
2548 .clkr = {
2549 .enable_reg = 0x8c000,
2550 .enable_mask = BIT(0),
2551 .hw.init = &(struct clk_init_data){
2552 .name = "gcc_ufs_mem_clkref_clk",
2553 .ops = &clk_branch2_ops,
2554 },
2555 },
2556};
2557
2558static struct clk_branch gcc_ufs_phy_ahb_clk = {
2559 .halt_reg = 0x77010,
2560 .halt_check = BRANCH_HALT,
2561 .hwcg_reg = 0x77010,
2562 .hwcg_bit = 1,
2563 .clkr = {
2564 .enable_reg = 0x77010,
2565 .enable_mask = BIT(0),
2566 .hw.init = &(struct clk_init_data){
2567 .name = "gcc_ufs_phy_ahb_clk",
2568 .ops = &clk_branch2_ops,
2569 },
2570 },
2571};
2572
2573static struct clk_branch gcc_ufs_phy_axi_clk = {
2574 .halt_reg = 0x7700c,
2575 .halt_check = BRANCH_HALT,
2576 .hwcg_reg = 0x7700c,
2577 .hwcg_bit = 1,
2578 .clkr = {
2579 .enable_reg = 0x7700c,
2580 .enable_mask = BIT(0),
2581 .hw.init = &(struct clk_init_data){
2582 .name = "gcc_ufs_phy_axi_clk",
2583 .parent_names = (const char *[]){
2584 "gcc_ufs_phy_axi_clk_src",
2585 },
2586 .num_parents = 1,
2587 .flags = CLK_SET_RATE_PARENT,
2588 .ops = &clk_branch2_ops,
2589 },
2590 },
2591};
2592
2593static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2594 .halt_reg = 0x77058,
2595 .halt_check = BRANCH_HALT,
2596 .hwcg_reg = 0x77058,
2597 .hwcg_bit = 1,
2598 .clkr = {
2599 .enable_reg = 0x77058,
2600 .enable_mask = BIT(0),
2601 .hw.init = &(struct clk_init_data){
2602 .name = "gcc_ufs_phy_ice_core_clk",
2603 .parent_names = (const char *[]){
2604 "gcc_ufs_phy_ice_core_clk_src",
2605 },
2606 .num_parents = 1,
2607 .flags = CLK_SET_RATE_PARENT,
2608 .ops = &clk_branch2_ops,
2609 },
2610 },
2611};
2612
2613static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2614 .halt_reg = 0x7708c,
2615 .halt_check = BRANCH_HALT,
2616 .hwcg_reg = 0x7708c,
2617 .hwcg_bit = 1,
2618 .clkr = {
2619 .enable_reg = 0x7708c,
2620 .enable_mask = BIT(0),
2621 .hw.init = &(struct clk_init_data){
2622 .name = "gcc_ufs_phy_phy_aux_clk",
2623 .parent_names = (const char *[]){
2624 "gcc_ufs_phy_phy_aux_clk_src",
2625 },
2626 .num_parents = 1,
2627 .flags = CLK_SET_RATE_PARENT,
2628 .ops = &clk_branch2_ops,
2629 },
2630 },
2631};
2632
2633static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2634 .halt_check = BRANCH_HALT_SKIP,
2635 .clkr = {
2636 .enable_reg = 0x77018,
2637 .enable_mask = BIT(0),
2638 .hw.init = &(struct clk_init_data){
2639 .name = "gcc_ufs_phy_rx_symbol_0_clk",
2640 .ops = &clk_branch2_ops,
2641 },
2642 },
2643};
2644
2645static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2646 .halt_check = BRANCH_HALT_SKIP,
2647 .clkr = {
2648 .enable_reg = 0x770a8,
2649 .enable_mask = BIT(0),
2650 .hw.init = &(struct clk_init_data){
2651 .name = "gcc_ufs_phy_rx_symbol_1_clk",
2652 .ops = &clk_branch2_ops,
2653 },
2654 },
2655};
2656
2657static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2658 .halt_check = BRANCH_HALT_SKIP,
2659 .clkr = {
2660 .enable_reg = 0x77014,
2661 .enable_mask = BIT(0),
2662 .hw.init = &(struct clk_init_data){
2663 .name = "gcc_ufs_phy_tx_symbol_0_clk",
2664 .ops = &clk_branch2_ops,
2665 },
2666 },
2667};
2668
2669static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2670 .halt_reg = 0x77054,
2671 .halt_check = BRANCH_HALT,
2672 .hwcg_reg = 0x77054,
2673 .hwcg_bit = 1,
2674 .clkr = {
2675 .enable_reg = 0x77054,
2676 .enable_mask = BIT(0),
2677 .hw.init = &(struct clk_init_data){
2678 .name = "gcc_ufs_phy_unipro_core_clk",
2679 .parent_names = (const char *[]){
2680 "gcc_ufs_phy_unipro_core_clk_src",
2681 },
2682 .num_parents = 1,
2683 .flags = CLK_SET_RATE_PARENT,
2684 .ops = &clk_branch2_ops,
2685 },
2686 },
2687};
2688
2689static struct clk_branch gcc_usb30_prim_master_clk = {
2690 .halt_reg = 0xf00c,
2691 .halt_check = BRANCH_HALT,
2692 .clkr = {
2693 .enable_reg = 0xf00c,
2694 .enable_mask = BIT(0),
2695 .hw.init = &(struct clk_init_data){
2696 .name = "gcc_usb30_prim_master_clk",
2697 .parent_names = (const char *[]){
2698 "gcc_usb30_prim_master_clk_src",
2699 },
2700 .num_parents = 1,
2701 .flags = CLK_SET_RATE_PARENT,
2702 .ops = &clk_branch2_ops,
2703 },
2704 },
2705};
2706
2707static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2708 .halt_reg = 0xf014,
2709 .halt_check = BRANCH_HALT,
2710 .clkr = {
2711 .enable_reg = 0xf014,
2712 .enable_mask = BIT(0),
2713 .hw.init = &(struct clk_init_data){
2714 .name = "gcc_usb30_prim_mock_utmi_clk",
2715 .parent_names = (const char *[]){
2716 "gcc_usb30_prim_mock_utmi_clk_src",
2717 },
2718 .num_parents = 1,
2719 .flags = CLK_SET_RATE_PARENT,
2720 .ops = &clk_branch2_ops,
2721 },
2722 },
2723};
2724
2725static struct clk_branch gcc_usb30_prim_sleep_clk = {
2726 .halt_reg = 0xf010,
2727 .halt_check = BRANCH_HALT,
2728 .clkr = {
2729 .enable_reg = 0xf010,
2730 .enable_mask = BIT(0),
2731 .hw.init = &(struct clk_init_data){
2732 .name = "gcc_usb30_prim_sleep_clk",
2733 .ops = &clk_branch2_ops,
2734 },
2735 },
2736};
2737
2738static struct clk_branch gcc_usb30_sec_master_clk = {
2739 .halt_reg = 0x1000c,
2740 .halt_check = BRANCH_HALT,
2741 .clkr = {
2742 .enable_reg = 0x1000c,
2743 .enable_mask = BIT(0),
2744 .hw.init = &(struct clk_init_data){
2745 .name = "gcc_usb30_sec_master_clk",
2746 .parent_names = (const char *[]){
2747 "gcc_usb30_sec_master_clk_src",
2748 },
2749 .num_parents = 1,
2750 .flags = CLK_SET_RATE_PARENT,
2751 .ops = &clk_branch2_ops,
2752 },
2753 },
2754};
2755
2756static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
2757 .halt_reg = 0x10014,
2758 .halt_check = BRANCH_HALT,
2759 .clkr = {
2760 .enable_reg = 0x10014,
2761 .enable_mask = BIT(0),
2762 .hw.init = &(struct clk_init_data){
2763 .name = "gcc_usb30_sec_mock_utmi_clk",
2764 .parent_names = (const char *[]){
2765 "gcc_usb30_sec_mock_utmi_clk_src",
2766 },
2767 .num_parents = 1,
2768 .flags = CLK_SET_RATE_PARENT,
2769 .ops = &clk_branch2_ops,
2770 },
2771 },
2772};
2773
2774static struct clk_branch gcc_usb30_sec_sleep_clk = {
2775 .halt_reg = 0x10010,
2776 .halt_check = BRANCH_HALT,
2777 .clkr = {
2778 .enable_reg = 0x10010,
2779 .enable_mask = BIT(0),
2780 .hw.init = &(struct clk_init_data){
2781 .name = "gcc_usb30_sec_sleep_clk",
2782 .ops = &clk_branch2_ops,
2783 },
2784 },
2785};
2786
2787static struct clk_branch gcc_usb3_prim_clkref_clk = {
2788 .halt_reg = 0x8c008,
2789 .halt_check = BRANCH_HALT,
2790 .clkr = {
2791 .enable_reg = 0x8c008,
2792 .enable_mask = BIT(0),
2793 .hw.init = &(struct clk_init_data){
2794 .name = "gcc_usb3_prim_clkref_clk",
2795 .ops = &clk_branch2_ops,
2796 },
2797 },
2798};
2799
2800static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2801 .halt_reg = 0xf04c,
2802 .halt_check = BRANCH_HALT,
2803 .clkr = {
2804 .enable_reg = 0xf04c,
2805 .enable_mask = BIT(0),
2806 .hw.init = &(struct clk_init_data){
2807 .name = "gcc_usb3_prim_phy_aux_clk",
2808 .parent_names = (const char *[]){
2809 "gcc_usb3_prim_phy_aux_clk_src",
2810 },
2811 .num_parents = 1,
2812 .flags = CLK_SET_RATE_PARENT,
2813 .ops = &clk_branch2_ops,
2814 },
2815 },
2816};
2817
2818static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2819 .halt_reg = 0xf050,
2820 .halt_check = BRANCH_HALT,
2821 .clkr = {
2822 .enable_reg = 0xf050,
2823 .enable_mask = BIT(0),
2824 .hw.init = &(struct clk_init_data){
2825 .name = "gcc_usb3_prim_phy_com_aux_clk",
2826 .parent_names = (const char *[]){
2827 "gcc_usb3_prim_phy_aux_clk_src",
2828 },
2829 .num_parents = 1,
2830 .flags = CLK_SET_RATE_PARENT,
2831 .ops = &clk_branch2_ops,
2832 },
2833 },
2834};
2835
2836static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2837 .halt_check = BRANCH_HALT_SKIP,
2838 .clkr = {
2839 .enable_reg = 0xf054,
2840 .enable_mask = BIT(0),
2841 .hw.init = &(struct clk_init_data){
2842 .name = "gcc_usb3_prim_phy_pipe_clk",
2843 .ops = &clk_branch2_ops,
2844 },
2845 },
2846};
2847
2848static struct clk_branch gcc_usb3_sec_clkref_clk = {
2849 .halt_reg = 0x8c028,
2850 .halt_check = BRANCH_HALT,
2851 .clkr = {
2852 .enable_reg = 0x8c028,
2853 .enable_mask = BIT(0),
2854 .hw.init = &(struct clk_init_data){
2855 .name = "gcc_usb3_sec_clkref_clk",
2856 .ops = &clk_branch2_ops,
2857 },
2858 },
2859};
2860
2861static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
2862 .halt_reg = 0x1004c,
2863 .halt_check = BRANCH_HALT,
2864 .clkr = {
2865 .enable_reg = 0x1004c,
2866 .enable_mask = BIT(0),
2867 .hw.init = &(struct clk_init_data){
2868 .name = "gcc_usb3_sec_phy_aux_clk",
2869 .parent_names = (const char *[]){
2870 "gcc_usb3_sec_phy_aux_clk_src",
2871 },
2872 .num_parents = 1,
2873 .flags = CLK_SET_RATE_PARENT,
2874 .ops = &clk_branch2_ops,
2875 },
2876 },
2877};
2878
2879static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
2880 .halt_reg = 0x10050,
2881 .halt_check = BRANCH_HALT,
2882 .clkr = {
2883 .enable_reg = 0x10050,
2884 .enable_mask = BIT(0),
2885 .hw.init = &(struct clk_init_data){
2886 .name = "gcc_usb3_sec_phy_com_aux_clk",
2887 .parent_names = (const char *[]){
2888 "gcc_usb3_sec_phy_aux_clk_src",
2889 },
2890 .num_parents = 1,
2891 .flags = CLK_SET_RATE_PARENT,
2892 .ops = &clk_branch2_ops,
2893 },
2894 },
2895};
2896
2897static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
2898 .halt_check = BRANCH_HALT_SKIP,
2899 .clkr = {
2900 .enable_reg = 0x10054,
2901 .enable_mask = BIT(0),
2902 .hw.init = &(struct clk_init_data){
2903 .name = "gcc_usb3_sec_phy_pipe_clk",
2904 .ops = &clk_branch2_ops,
2905 },
2906 },
2907};
2908
2909static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2910 .halt_reg = 0x6a004,
2911 .halt_check = BRANCH_HALT,
2912 .hwcg_reg = 0x6a004,
2913 .hwcg_bit = 1,
2914 .clkr = {
2915 .enable_reg = 0x6a004,
2916 .enable_mask = BIT(0),
2917 .hw.init = &(struct clk_init_data){
2918 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2919 .ops = &clk_branch2_ops,
2920 },
2921 },
2922};
2923
2924static struct clk_branch gcc_vdda_vs_clk = {
2925 .halt_reg = 0x7a00c,
2926 .halt_check = BRANCH_HALT,
2927 .clkr = {
2928 .enable_reg = 0x7a00c,
2929 .enable_mask = BIT(0),
2930 .hw.init = &(struct clk_init_data){
2931 .name = "gcc_vdda_vs_clk",
2932 .parent_names = (const char *[]){
2933 "gcc_vsensor_clk_src",
2934 },
2935 .num_parents = 1,
2936 .flags = CLK_SET_RATE_PARENT,
2937 .ops = &clk_branch2_ops,
2938 },
2939 },
2940};
2941
2942static struct clk_branch gcc_vddcx_vs_clk = {
2943 .halt_reg = 0x7a004,
2944 .halt_check = BRANCH_HALT,
2945 .clkr = {
2946 .enable_reg = 0x7a004,
2947 .enable_mask = BIT(0),
2948 .hw.init = &(struct clk_init_data){
2949 .name = "gcc_vddcx_vs_clk",
2950 .parent_names = (const char *[]){
2951 "gcc_vsensor_clk_src",
2952 },
2953 .num_parents = 1,
2954 .flags = CLK_SET_RATE_PARENT,
2955 .ops = &clk_branch2_ops,
2956 },
2957 },
2958};
2959
2960static struct clk_branch gcc_vddmx_vs_clk = {
2961 .halt_reg = 0x7a008,
2962 .halt_check = BRANCH_HALT,
2963 .clkr = {
2964 .enable_reg = 0x7a008,
2965 .enable_mask = BIT(0),
2966 .hw.init = &(struct clk_init_data){
2967 .name = "gcc_vddmx_vs_clk",
2968 .parent_names = (const char *[]){
2969 "gcc_vsensor_clk_src",
2970 },
2971 .num_parents = 1,
2972 .flags = CLK_SET_RATE_PARENT,
2973 .ops = &clk_branch2_ops,
2974 },
2975 },
2976};
2977
2978static struct clk_branch gcc_video_ahb_clk = {
2979 .halt_reg = 0xb004,
2980 .halt_check = BRANCH_HALT,
2981 .hwcg_reg = 0xb004,
2982 .hwcg_bit = 1,
2983 .clkr = {
2984 .enable_reg = 0xb004,
2985 .enable_mask = BIT(0),
2986 .hw.init = &(struct clk_init_data){
2987 .name = "gcc_video_ahb_clk",
2988 .ops = &clk_branch2_ops,
2989 },
2990 },
2991};
2992
2993static struct clk_branch gcc_video_axi_clk = {
2994 .halt_reg = 0xb01c,
2995 .halt_check = BRANCH_VOTED,
2996 .clkr = {
2997 .enable_reg = 0xb01c,
2998 .enable_mask = BIT(0),
2999 .hw.init = &(struct clk_init_data){
3000 .name = "gcc_video_axi_clk",
3001 .ops = &clk_branch2_ops,
3002 },
3003 },
3004};
3005
3006static struct clk_branch gcc_video_xo_clk = {
3007 .halt_reg = 0xb028,
3008 .halt_check = BRANCH_HALT,
3009 .clkr = {
3010 .enable_reg = 0xb028,
3011 .enable_mask = BIT(0),
3012 .hw.init = &(struct clk_init_data){
3013 .name = "gcc_video_xo_clk",
3014 .ops = &clk_branch2_ops,
3015 },
3016 },
3017};
3018
3019static struct clk_branch gcc_vs_ctrl_ahb_clk = {
3020 .halt_reg = 0x7a014,
3021 .halt_check = BRANCH_HALT,
3022 .hwcg_reg = 0x7a014,
3023 .hwcg_bit = 1,
3024 .clkr = {
3025 .enable_reg = 0x7a014,
3026 .enable_mask = BIT(0),
3027 .hw.init = &(struct clk_init_data){
3028 .name = "gcc_vs_ctrl_ahb_clk",
3029 .ops = &clk_branch2_ops,
3030 },
3031 },
3032};
3033
3034static struct clk_branch gcc_vs_ctrl_clk = {
3035 .halt_reg = 0x7a010,
3036 .halt_check = BRANCH_HALT,
3037 .clkr = {
3038 .enable_reg = 0x7a010,
3039 .enable_mask = BIT(0),
3040 .hw.init = &(struct clk_init_data){
3041 .name = "gcc_vs_ctrl_clk",
3042 .parent_names = (const char *[]){
3043 "gcc_vs_ctrl_clk_src",
3044 },
3045 .num_parents = 1,
3046 .flags = CLK_SET_RATE_PARENT,
3047 .ops = &clk_branch2_ops,
3048 },
3049 },
3050};
3051
3052static struct gdsc pcie_0_gdsc = {
3053 .gdscr = 0x6b004,
3054 .pd = {
3055 .name = "pcie_0_gdsc",
3056 },
3057 .pwrsts = PWRSTS_OFF_ON,
3058 .flags = POLL_CFG_GDSCR,
3059};
3060
3061static struct gdsc pcie_1_gdsc = {
3062 .gdscr = 0x8d004,
3063 .pd = {
3064 .name = "pcie_1_gdsc",
3065 },
3066 .pwrsts = PWRSTS_OFF_ON,
3067 .flags = POLL_CFG_GDSCR,
3068};
3069
3070static struct gdsc ufs_card_gdsc = {
3071 .gdscr = 0x75004,
3072 .pd = {
3073 .name = "ufs_card_gdsc",
3074 },
3075 .pwrsts = PWRSTS_OFF_ON,
3076 .flags = POLL_CFG_GDSCR,
3077};
3078
3079static struct gdsc ufs_phy_gdsc = {
3080 .gdscr = 0x77004,
3081 .pd = {
3082 .name = "ufs_phy_gdsc",
3083 },
3084 .pwrsts = PWRSTS_OFF_ON,
3085 .flags = POLL_CFG_GDSCR,
3086};
3087
3088static struct gdsc usb30_prim_gdsc = {
3089 .gdscr = 0xf004,
3090 .pd = {
3091 .name = "usb30_prim_gdsc",
3092 },
3093 .pwrsts = PWRSTS_OFF_ON,
3094 .flags = POLL_CFG_GDSCR,
3095};
3096
3097static struct gdsc usb30_sec_gdsc = {
3098 .gdscr = 0x10004,
3099 .pd = {
3100 .name = "usb30_sec_gdsc",
3101 },
3102 .pwrsts = PWRSTS_OFF_ON,
3103 .flags = POLL_CFG_GDSCR,
3104};
3105
3106static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = {
3107 .gdscr = 0x7d030,
3108 .pd = {
3109 .name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc",
3110 },
3111 .pwrsts = PWRSTS_OFF_ON,
3112};
3113
3114static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = {
3115 .gdscr = 0x7d03c,
3116 .pd = {
3117 .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc",
3118 },
3119 .pwrsts = PWRSTS_OFF_ON,
3120};
3121
3122static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = {
3123 .gdscr = 0x7d034,
3124 .pd = {
3125 .name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc",
3126 },
3127 .pwrsts = PWRSTS_OFF_ON,
3128};
3129
3130static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = {
3131 .gdscr = 0x7d038,
3132 .pd = {
3133 .name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc",
3134 },
3135 .pwrsts = PWRSTS_OFF_ON,
3136};
3137
3138static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
3139 .gdscr = 0x7d040,
3140 .pd = {
3141 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
3142 },
3143 .pwrsts = PWRSTS_OFF_ON,
3144};
3145
3146static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
3147 .gdscr = 0x7d048,
3148 .pd = {
3149 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
3150 },
3151 .pwrsts = PWRSTS_OFF_ON,
3152};
3153
3154static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
3155 .gdscr = 0x7d044,
3156 .pd = {
3157 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
3158 },
3159 .pwrsts = PWRSTS_OFF_ON,
3160};
3161
3162static struct clk_regmap *gcc_sdm845_clocks[] = {
3163 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3164 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3165 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3166 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3167 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3168 [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
3169 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3170 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3171 [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
3172 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3173 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
3174 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
3175 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
3176 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3177 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3178 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3179 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3180 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
3181 [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr,
3182 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3183 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3184 [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
3185 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
3186 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
3187 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3188 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3189 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3190 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3191 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3192 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3193 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3194 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3195 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3196 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3197 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
3198 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3199 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3200 [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr,
3201 [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr,
3202 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3203 [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
3204 [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
3205 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
3206 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3207 [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr,
3208 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3209 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3210 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3211 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
3212 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3213 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3214 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3215 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3216 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3217 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3218 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3219 [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
3220 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3221 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3222 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3223 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3224 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3225 [GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr,
3226 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
3227 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3228 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3229 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3230 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3231 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3232 [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr,
3233 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3234 [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr,
3235 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3236 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3237 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3238 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3239 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3240 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3241 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3242 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3243 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3244 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3245 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3246 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3247 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3248 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3249 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3250 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3251 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3252 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3253 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3254 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3255 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3256 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3257 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3258 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3259 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3260 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3261 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3262 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3263 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3264 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3265 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
3266 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
3267 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3268 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3269 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3270 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3271 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3272 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3273 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3274 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3275 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3276 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3277 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3278 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3279 [GCC_TSIF_INACTIVITY_TIMERS_CLK] =
3280 &gcc_tsif_inactivity_timers_clk.clkr,
3281 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3282 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
3283 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3284 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3285 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3286 [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
3287 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3288 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3289 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3290 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3291 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
3292 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
3293 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
3294 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3295 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
3296 &gcc_ufs_card_unipro_core_clk_src.clkr,
3297 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
3298 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3299 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3300 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3301 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3302 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3303 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3304 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3305 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3306 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3307 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3308 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3309 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3310 &gcc_ufs_phy_unipro_core_clk_src.clkr,
3311 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3312 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3313 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3314 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3315 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3316 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3317 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3318 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3319 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3320 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3321 &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3322 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3323 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3324 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3325 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3326 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3327 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3328 [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
3329 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3330 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3331 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3332 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3333 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3334 [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
3335 [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
3336 [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
3337 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3338 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
3339 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3340 [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
3341 [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
3342 [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
3343 [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
3344 [GPLL0] = &gpll0.clkr,
3345 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3346 [GPLL4] = &gpll4.clkr,
3347};
3348
3349static const struct qcom_reset_map gcc_sdm845_resets[] = {
3350 [GCC_MMSS_BCR] = { 0xb000 },
3351 [GCC_PCIE_0_BCR] = { 0x6b000 },
3352 [GCC_PCIE_1_BCR] = { 0x8d000 },
3353 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3354 [GCC_PDM_BCR] = { 0x33000 },
3355 [GCC_PRNG_BCR] = { 0x34000 },
3356 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3357 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3358 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3359 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3360 [GCC_SDCC2_BCR] = { 0x14000 },
3361 [GCC_SDCC4_BCR] = { 0x16000 },
3362 [GCC_TSIF_BCR] = { 0x36000 },
3363 [GCC_UFS_CARD_BCR] = { 0x75000 },
3364 [GCC_UFS_PHY_BCR] = { 0x77000 },
3365 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3366 [GCC_USB30_SEC_BCR] = { 0x10000 },
3367 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3368 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3369 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3370 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3371 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3372 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3373 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3374 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3375 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3376};
3377
3378static struct gdsc *gcc_sdm845_gdscs[] = {
3379 [PCIE_0_GDSC] = &pcie_0_gdsc,
3380 [PCIE_1_GDSC] = &pcie_1_gdsc,
3381 [UFS_CARD_GDSC] = &ufs_card_gdsc,
3382 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
3383 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3384 [USB30_SEC_GDSC] = &usb30_sec_gdsc,
3385 [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] =
3386 &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc,
3387 [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] =
3388 &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc,
3389 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] =
3390 &hlos1_vote_aggre_noc_mmu_tbu1_gdsc,
3391 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] =
3392 &hlos1_vote_aggre_noc_mmu_tbu2_gdsc,
3393 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
3394 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3395 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
3396 &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3397 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
3398};
3399
3400static const struct regmap_config gcc_sdm845_regmap_config = {
3401 .reg_bits = 32,
3402 .reg_stride = 4,
3403 .val_bits = 32,
3404 .max_register = 0x182090,
3405 .fast_io = true,
3406};
3407
3408static const struct qcom_cc_desc gcc_sdm845_desc = {
3409 .config = &gcc_sdm845_regmap_config,
3410 .clks = gcc_sdm845_clocks,
3411 .num_clks = ARRAY_SIZE(gcc_sdm845_clocks),
3412 .resets = gcc_sdm845_resets,
3413 .num_resets = ARRAY_SIZE(gcc_sdm845_resets),
3414 .gdscs = gcc_sdm845_gdscs,
3415 .num_gdscs = ARRAY_SIZE(gcc_sdm845_gdscs),
3416};
3417
3418static const struct of_device_id gcc_sdm845_match_table[] = {
3419 { .compatible = "qcom,gcc-sdm845" },
3420 { }
3421};
3422MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);
3423
3424static int gcc_sdm845_probe(struct platform_device *pdev)
3425{
3426 struct regmap *regmap;
3427
3428 regmap = qcom_cc_map(pdev, &gcc_sdm845_desc);
3429 if (IS_ERR(regmap))
3430 return PTR_ERR(regmap);
3431
3432 /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */
3433 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
3434 regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
3435
3436 /* Enable CPUSS clocks */
3437 regmap_update_bits(regmap, 0x48190, BIT(0), 0x1);
3438 regmap_update_bits(regmap, 0x52004, BIT(22), 0x1);
3439
3440 return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
3441}
3442
3443static struct platform_driver gcc_sdm845_driver = {
3444 .probe = gcc_sdm845_probe,
3445 .driver = {
3446 .name = "gcc-sdm845",
3447 .of_match_table = gcc_sdm845_match_table,
3448 },
3449};
3450
3451static int __init gcc_sdm845_init(void)
3452{
3453 return platform_driver_register(&gcc_sdm845_driver);
3454}
3455subsys_initcall(gcc_sdm845_init);
3456
3457static void __exit gcc_sdm845_exit(void)
3458{
3459 platform_driver_unregister(&gcc_sdm845_driver);
3460}
3461module_exit(gcc_sdm845_exit);
3462
3463MODULE_DESCRIPTION("QTI GCC SDM845 Driver");
3464MODULE_LICENSE("GPL v2");
3465MODULE_ALIAS("platform:gcc-sdm845");
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index a4f3580587b7..a077133c7ce3 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 2 * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and 5 * it under the terms of the GNU General Public License version 2 and
@@ -31,6 +31,12 @@
31#define HW_CONTROL_MASK BIT(1) 31#define HW_CONTROL_MASK BIT(1)
32#define SW_COLLAPSE_MASK BIT(0) 32#define SW_COLLAPSE_MASK BIT(0)
33#define GMEM_CLAMP_IO_MASK BIT(0) 33#define GMEM_CLAMP_IO_MASK BIT(0)
34#define GMEM_RESET_MASK BIT(4)
35
36/* CFG_GDSCR */
37#define GDSC_POWER_UP_COMPLETE BIT(16)
38#define GDSC_POWER_DOWN_COMPLETE BIT(15)
39#define CFG_GDSCR_OFFSET 0x4
34 40
35/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */ 41/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
36#define EN_REST_WAIT_VAL (0x2 << 20) 42#define EN_REST_WAIT_VAL (0x2 << 20)
@@ -40,20 +46,50 @@
40#define RETAIN_MEM BIT(14) 46#define RETAIN_MEM BIT(14)
41#define RETAIN_PERIPH BIT(13) 47#define RETAIN_PERIPH BIT(13)
42 48
43#define TIMEOUT_US 100 49#define TIMEOUT_US 500
44 50
45#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd) 51#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
46 52
47static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg) 53enum gdsc_status {
54 GDSC_OFF,
55 GDSC_ON
56};
57
58/* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
59static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
48{ 60{
61 unsigned int reg;
49 u32 val; 62 u32 val;
50 int ret; 63 int ret;
51 64
65 if (sc->flags & POLL_CFG_GDSCR)
66 reg = sc->gdscr + CFG_GDSCR_OFFSET;
67 else if (sc->gds_hw_ctrl)
68 reg = sc->gds_hw_ctrl;
69 else
70 reg = sc->gdscr;
71
52 ret = regmap_read(sc->regmap, reg, &val); 72 ret = regmap_read(sc->regmap, reg, &val);
53 if (ret) 73 if (ret)
54 return ret; 74 return ret;
55 75
56 return !!(val & PWR_ON_MASK); 76 if (sc->flags & POLL_CFG_GDSCR) {
77 switch (status) {
78 case GDSC_ON:
79 return !!(val & GDSC_POWER_UP_COMPLETE);
80 case GDSC_OFF:
81 return !!(val & GDSC_POWER_DOWN_COMPLETE);
82 }
83 }
84
85 switch (status) {
86 case GDSC_ON:
87 return !!(val & PWR_ON_MASK);
88 case GDSC_OFF:
89 return !(val & PWR_ON_MASK);
90 }
91
92 return -EINVAL;
57} 93}
58 94
59static int gdsc_hwctrl(struct gdsc *sc, bool en) 95static int gdsc_hwctrl(struct gdsc *sc, bool en)
@@ -63,34 +99,33 @@ static int gdsc_hwctrl(struct gdsc *sc, bool en)
63 return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val); 99 return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
64} 100}
65 101
66static int gdsc_poll_status(struct gdsc *sc, unsigned int reg, bool en) 102static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
67{ 103{
68 ktime_t start; 104 ktime_t start;
69 105
70 start = ktime_get(); 106 start = ktime_get();
71 do { 107 do {
72 if (gdsc_is_enabled(sc, reg) == en) 108 if (gdsc_check_status(sc, status))
73 return 0; 109 return 0;
74 } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US); 110 } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
75 111
76 if (gdsc_is_enabled(sc, reg) == en) 112 if (gdsc_check_status(sc, status))
77 return 0; 113 return 0;
78 114
79 return -ETIMEDOUT; 115 return -ETIMEDOUT;
80} 116}
81 117
82static int gdsc_toggle_logic(struct gdsc *sc, bool en) 118static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
83{ 119{
84 int ret; 120 int ret;
85 u32 val = en ? 0 : SW_COLLAPSE_MASK; 121 u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK;
86 unsigned int status_reg = sc->gdscr;
87 122
88 ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val); 123 ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
89 if (ret) 124 if (ret)
90 return ret; 125 return ret;
91 126
92 /* If disabling votable gdscs, don't poll on status */ 127 /* If disabling votable gdscs, don't poll on status */
93 if ((sc->flags & VOTABLE) && !en) { 128 if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
94 /* 129 /*
95 * Add a short delay here to ensure that an enable 130 * Add a short delay here to ensure that an enable
96 * right after it was disabled does not put it in an 131 * right after it was disabled does not put it in an
@@ -101,7 +136,6 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
101 } 136 }
102 137
103 if (sc->gds_hw_ctrl) { 138 if (sc->gds_hw_ctrl) {
104 status_reg = sc->gds_hw_ctrl;
105 /* 139 /*
106 * The gds hw controller asserts/de-asserts the status bit soon 140 * The gds hw controller asserts/de-asserts the status bit soon
107 * after it receives a power on/off request from a master. 141 * after it receives a power on/off request from a master.
@@ -115,7 +149,7 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
115 udelay(1); 149 udelay(1);
116 } 150 }
117 151
118 return gdsc_poll_status(sc, status_reg, en); 152 return gdsc_poll_status(sc, status);
119} 153}
120 154
121static inline int gdsc_deassert_reset(struct gdsc *sc) 155static inline int gdsc_deassert_reset(struct gdsc *sc)
@@ -166,6 +200,14 @@ static inline void gdsc_assert_clamp_io(struct gdsc *sc)
166 GMEM_CLAMP_IO_MASK, 1); 200 GMEM_CLAMP_IO_MASK, 1);
167} 201}
168 202
203static inline void gdsc_assert_reset_aon(struct gdsc *sc)
204{
205 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
206 GMEM_RESET_MASK, 1);
207 udelay(1);
208 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
209 GMEM_RESET_MASK, 0);
210}
169static int gdsc_enable(struct generic_pm_domain *domain) 211static int gdsc_enable(struct generic_pm_domain *domain)
170{ 212{
171 struct gdsc *sc = domain_to_gdsc(domain); 213 struct gdsc *sc = domain_to_gdsc(domain);
@@ -174,10 +216,19 @@ static int gdsc_enable(struct generic_pm_domain *domain)
174 if (sc->pwrsts == PWRSTS_ON) 216 if (sc->pwrsts == PWRSTS_ON)
175 return gdsc_deassert_reset(sc); 217 return gdsc_deassert_reset(sc);
176 218
177 if (sc->flags & CLAMP_IO) 219 if (sc->flags & SW_RESET) {
220 gdsc_assert_reset(sc);
221 udelay(1);
222 gdsc_deassert_reset(sc);
223 }
224
225 if (sc->flags & CLAMP_IO) {
226 if (sc->flags & AON_RESET)
227 gdsc_assert_reset_aon(sc);
178 gdsc_deassert_clamp_io(sc); 228 gdsc_deassert_clamp_io(sc);
229 }
179 230
180 ret = gdsc_toggle_logic(sc, true); 231 ret = gdsc_toggle_logic(sc, GDSC_ON);
181 if (ret) 232 if (ret)
182 return ret; 233 return ret;
183 234
@@ -222,8 +273,6 @@ static int gdsc_disable(struct generic_pm_domain *domain)
222 273
223 /* Turn off HW trigger mode if supported */ 274 /* Turn off HW trigger mode if supported */
224 if (sc->flags & HW_CTRL) { 275 if (sc->flags & HW_CTRL) {
225 unsigned int reg;
226
227 ret = gdsc_hwctrl(sc, false); 276 ret = gdsc_hwctrl(sc, false);
228 if (ret < 0) 277 if (ret < 0)
229 return ret; 278 return ret;
@@ -235,8 +284,7 @@ static int gdsc_disable(struct generic_pm_domain *domain)
235 */ 284 */
236 udelay(1); 285 udelay(1);
237 286
238 reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr; 287 ret = gdsc_poll_status(sc, GDSC_ON);
239 ret = gdsc_poll_status(sc, reg, true);
240 if (ret) 288 if (ret)
241 return ret; 289 return ret;
242 } 290 }
@@ -244,7 +292,7 @@ static int gdsc_disable(struct generic_pm_domain *domain)
244 if (sc->pwrsts & PWRSTS_OFF) 292 if (sc->pwrsts & PWRSTS_OFF)
245 gdsc_clear_mem_on(sc); 293 gdsc_clear_mem_on(sc);
246 294
247 ret = gdsc_toggle_logic(sc, false); 295 ret = gdsc_toggle_logic(sc, GDSC_OFF);
248 if (ret) 296 if (ret)
249 return ret; 297 return ret;
250 298
@@ -258,7 +306,6 @@ static int gdsc_init(struct gdsc *sc)
258{ 306{
259 u32 mask, val; 307 u32 mask, val;
260 int on, ret; 308 int on, ret;
261 unsigned int reg;
262 309
263 /* 310 /*
264 * Disable HW trigger: collapse/restore occur based on registers writes. 311 * Disable HW trigger: collapse/restore occur based on registers writes.
@@ -274,13 +321,12 @@ static int gdsc_init(struct gdsc *sc)
274 321
275 /* Force gdsc ON if only ON state is supported */ 322 /* Force gdsc ON if only ON state is supported */
276 if (sc->pwrsts == PWRSTS_ON) { 323 if (sc->pwrsts == PWRSTS_ON) {
277 ret = gdsc_toggle_logic(sc, true); 324 ret = gdsc_toggle_logic(sc, GDSC_ON);
278 if (ret) 325 if (ret)
279 return ret; 326 return ret;
280 } 327 }
281 328
282 reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr; 329 on = gdsc_check_status(sc, GDSC_ON);
283 on = gdsc_is_enabled(sc, reg);
284 if (on < 0) 330 if (on < 0)
285 return on; 331 return on;
286 332
@@ -291,6 +337,14 @@ static int gdsc_init(struct gdsc *sc)
291 if ((sc->flags & VOTABLE) && on) 337 if ((sc->flags & VOTABLE) && on)
292 gdsc_enable(&sc->pd); 338 gdsc_enable(&sc->pd);
293 339
340 /* If ALWAYS_ON GDSCs are not ON, turn them ON */
341 if (sc->flags & ALWAYS_ON) {
342 if (!on)
343 gdsc_enable(&sc->pd);
344 on = true;
345 sc->pd.flags |= GENPD_FLAG_ALWAYS_ON;
346 }
347
294 if (on || (sc->pwrsts & PWRSTS_RET)) 348 if (on || (sc->pwrsts & PWRSTS_RET))
295 gdsc_force_mem_on(sc); 349 gdsc_force_mem_on(sc);
296 else 350 else
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index 39648348e5ec..bd1f2c780d0a 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 2 * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and 5 * it under the terms of the GNU General Public License version 2 and
@@ -53,6 +53,10 @@ struct gdsc {
53#define VOTABLE BIT(0) 53#define VOTABLE BIT(0)
54#define CLAMP_IO BIT(1) 54#define CLAMP_IO BIT(1)
55#define HW_CTRL BIT(2) 55#define HW_CTRL BIT(2)
56#define SW_RESET BIT(3)
57#define AON_RESET BIT(4)
58#define POLL_CFG_GDSCR BIT(5)
59#define ALWAYS_ON BIT(6)
56 struct reset_controller_dev *rcdev; 60 struct reset_controller_dev *rcdev;
57 unsigned int *resets; 61 unsigned int *resets;
58 unsigned int reset_count; 62 unsigned int reset_count;
diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
index 66a2fa4ec93c..1a25ee4f3658 100644
--- a/drivers/clk/qcom/mmcc-msm8996.c
+++ b/drivers/clk/qcom/mmcc-msm8996.c
@@ -1245,7 +1245,7 @@ static struct clk_branch mmss_mmagic_ahb_clk = {
1245 .name = "mmss_mmagic_ahb_clk", 1245 .name = "mmss_mmagic_ahb_clk",
1246 .parent_names = (const char *[]){ "ahb_clk_src" }, 1246 .parent_names = (const char *[]){ "ahb_clk_src" },
1247 .num_parents = 1, 1247 .num_parents = 1,
1248 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1248 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1249 .ops = &clk_branch2_ops, 1249 .ops = &clk_branch2_ops,
1250 }, 1250 },
1251 }, 1251 },
@@ -1260,7 +1260,7 @@ static struct clk_branch mmss_mmagic_cfg_ahb_clk = {
1260 .name = "mmss_mmagic_cfg_ahb_clk", 1260 .name = "mmss_mmagic_cfg_ahb_clk",
1261 .parent_names = (const char *[]){ "ahb_clk_src" }, 1261 .parent_names = (const char *[]){ "ahb_clk_src" },
1262 .num_parents = 1, 1262 .num_parents = 1,
1263 .flags = CLK_SET_RATE_PARENT, 1263 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1264 .ops = &clk_branch2_ops, 1264 .ops = &clk_branch2_ops,
1265 }, 1265 },
1266 }, 1266 },
@@ -1319,7 +1319,7 @@ static struct clk_branch mmagic_camss_axi_clk = {
1319 .name = "mmagic_camss_axi_clk", 1319 .name = "mmagic_camss_axi_clk",
1320 .parent_names = (const char *[]){ "axi_clk_src" }, 1320 .parent_names = (const char *[]){ "axi_clk_src" },
1321 .num_parents = 1, 1321 .num_parents = 1,
1322 .flags = CLK_SET_RATE_PARENT, 1322 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1323 .ops = &clk_branch2_ops, 1323 .ops = &clk_branch2_ops,
1324 }, 1324 },
1325 }, 1325 },
@@ -1334,7 +1334,7 @@ static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = {
1334 .name = "mmagic_camss_noc_cfg_ahb_clk", 1334 .name = "mmagic_camss_noc_cfg_ahb_clk",
1335 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1335 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1336 .num_parents = 1, 1336 .num_parents = 1,
1337 .flags = CLK_SET_RATE_PARENT, 1337 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1338 .ops = &clk_branch2_ops, 1338 .ops = &clk_branch2_ops,
1339 }, 1339 },
1340 }, 1340 },
@@ -1439,7 +1439,7 @@ static struct clk_branch mmagic_mdss_axi_clk = {
1439 .name = "mmagic_mdss_axi_clk", 1439 .name = "mmagic_mdss_axi_clk",
1440 .parent_names = (const char *[]){ "axi_clk_src" }, 1440 .parent_names = (const char *[]){ "axi_clk_src" },
1441 .num_parents = 1, 1441 .num_parents = 1,
1442 .flags = CLK_SET_RATE_PARENT, 1442 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1443 .ops = &clk_branch2_ops, 1443 .ops = &clk_branch2_ops,
1444 }, 1444 },
1445 }, 1445 },
@@ -1454,7 +1454,7 @@ static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = {
1454 .name = "mmagic_mdss_noc_cfg_ahb_clk", 1454 .name = "mmagic_mdss_noc_cfg_ahb_clk",
1455 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1455 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1456 .num_parents = 1, 1456 .num_parents = 1,
1457 .flags = CLK_SET_RATE_PARENT, 1457 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1458 .ops = &clk_branch2_ops, 1458 .ops = &clk_branch2_ops,
1459 }, 1459 },
1460 }, 1460 },
@@ -1529,7 +1529,7 @@ static struct clk_branch mmagic_video_axi_clk = {
1529 .name = "mmagic_video_axi_clk", 1529 .name = "mmagic_video_axi_clk",
1530 .parent_names = (const char *[]){ "axi_clk_src" }, 1530 .parent_names = (const char *[]){ "axi_clk_src" },
1531 .num_parents = 1, 1531 .num_parents = 1,
1532 .flags = CLK_SET_RATE_PARENT, 1532 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1533 .ops = &clk_branch2_ops, 1533 .ops = &clk_branch2_ops,
1534 }, 1534 },
1535 }, 1535 },
@@ -1544,7 +1544,7 @@ static struct clk_branch mmagic_video_noc_cfg_ahb_clk = {
1544 .name = "mmagic_video_noc_cfg_ahb_clk", 1544 .name = "mmagic_video_noc_cfg_ahb_clk",
1545 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, 1545 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1546 .num_parents = 1, 1546 .num_parents = 1,
1547 .flags = CLK_SET_RATE_PARENT, 1547 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1548 .ops = &clk_branch2_ops, 1548 .ops = &clk_branch2_ops,
1549 }, 1549 },
1550 }, 1550 },
@@ -2919,7 +2919,7 @@ static struct gdsc mmagic_video_gdsc = {
2919 .name = "mmagic_video", 2919 .name = "mmagic_video",
2920 }, 2920 },
2921 .pwrsts = PWRSTS_OFF_ON, 2921 .pwrsts = PWRSTS_OFF_ON,
2922 .flags = VOTABLE, 2922 .flags = VOTABLE | ALWAYS_ON,
2923}; 2923};
2924 2924
2925static struct gdsc mmagic_mdss_gdsc = { 2925static struct gdsc mmagic_mdss_gdsc = {
@@ -2929,7 +2929,7 @@ static struct gdsc mmagic_mdss_gdsc = {
2929 .name = "mmagic_mdss", 2929 .name = "mmagic_mdss",
2930 }, 2930 },
2931 .pwrsts = PWRSTS_OFF_ON, 2931 .pwrsts = PWRSTS_OFF_ON,
2932 .flags = VOTABLE, 2932 .flags = VOTABLE | ALWAYS_ON,
2933}; 2933};
2934 2934
2935static struct gdsc mmagic_camss_gdsc = { 2935static struct gdsc mmagic_camss_gdsc = {
@@ -2939,7 +2939,7 @@ static struct gdsc mmagic_camss_gdsc = {
2939 .name = "mmagic_camss", 2939 .name = "mmagic_camss",
2940 }, 2940 },
2941 .pwrsts = PWRSTS_OFF_ON, 2941 .pwrsts = PWRSTS_OFF_ON,
2942 .flags = VOTABLE, 2942 .flags = VOTABLE | ALWAYS_ON,
2943}; 2943};
2944 2944
2945static struct gdsc venus_gdsc = { 2945static struct gdsc venus_gdsc = {
diff --git a/drivers/clk/qcom/videocc-sdm845.c b/drivers/clk/qcom/videocc-sdm845.c
new file mode 100644
index 000000000000..9073b7a710ac
--- /dev/null
+++ b/drivers/clk/qcom/videocc-sdm845.c
@@ -0,0 +1,358 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk-provider.h>
7#include <linux/module.h>
8#include <linux/platform_device.h>
9#include <linux/regmap.h>
10
11#include <dt-bindings/clock/qcom,videocc-sdm845.h>
12
13#include "common.h"
14#include "clk-alpha-pll.h"
15#include "clk-branch.h"
16#include "clk-rcg.h"
17#include "clk-regmap.h"
18#include "clk-pll.h"
19#include "gdsc.h"
20
21#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
22
23enum {
24 P_BI_TCXO,
25 P_CORE_BI_PLL_TEST_SE,
26 P_VIDEO_PLL0_OUT_EVEN,
27 P_VIDEO_PLL0_OUT_MAIN,
28 P_VIDEO_PLL0_OUT_ODD,
29};
30
31static const struct parent_map video_cc_parent_map_0[] = {
32 { P_BI_TCXO, 0 },
33 { P_VIDEO_PLL0_OUT_MAIN, 1 },
34 { P_VIDEO_PLL0_OUT_EVEN, 2 },
35 { P_VIDEO_PLL0_OUT_ODD, 3 },
36 { P_CORE_BI_PLL_TEST_SE, 4 },
37};
38
39static const char * const video_cc_parent_names_0[] = {
40 "bi_tcxo",
41 "video_pll0",
42 "video_pll0_out_even",
43 "video_pll0_out_odd",
44 "core_bi_pll_test_se",
45};
46
47static const struct alpha_pll_config video_pll0_config = {
48 .l = 0x10,
49 .alpha = 0xaaab,
50};
51
52static struct clk_alpha_pll video_pll0 = {
53 .offset = 0x42c,
54 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
55 .clkr = {
56 .hw.init = &(struct clk_init_data){
57 .name = "video_pll0",
58 .parent_names = (const char *[]){ "bi_tcxo" },
59 .num_parents = 1,
60 .ops = &clk_alpha_pll_fabia_ops,
61 },
62 },
63};
64
65static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = {
66 F(100000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
67 F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
68 F(330000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
69 F(404000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
70 F(444000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
71 F(533000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
72 { }
73};
74
75static struct clk_rcg2 video_cc_venus_clk_src = {
76 .cmd_rcgr = 0x7f0,
77 .mnd_width = 0,
78 .hid_width = 5,
79 .parent_map = video_cc_parent_map_0,
80 .freq_tbl = ftbl_video_cc_venus_clk_src,
81 .clkr.hw.init = &(struct clk_init_data){
82 .name = "video_cc_venus_clk_src",
83 .parent_names = video_cc_parent_names_0,
84 .num_parents = 5,
85 .flags = CLK_SET_RATE_PARENT,
86 .ops = &clk_rcg2_shared_ops,
87 },
88};
89
90static struct clk_branch video_cc_apb_clk = {
91 .halt_reg = 0x990,
92 .halt_check = BRANCH_HALT,
93 .clkr = {
94 .enable_reg = 0x990,
95 .enable_mask = BIT(0),
96 .hw.init = &(struct clk_init_data){
97 .name = "video_cc_apb_clk",
98 .ops = &clk_branch2_ops,
99 },
100 },
101};
102
103static struct clk_branch video_cc_at_clk = {
104 .halt_reg = 0x9f0,
105 .halt_check = BRANCH_HALT,
106 .clkr = {
107 .enable_reg = 0x9f0,
108 .enable_mask = BIT(0),
109 .hw.init = &(struct clk_init_data){
110 .name = "video_cc_at_clk",
111 .ops = &clk_branch2_ops,
112 },
113 },
114};
115
116static struct clk_branch video_cc_qdss_trig_clk = {
117 .halt_reg = 0x970,
118 .halt_check = BRANCH_HALT,
119 .clkr = {
120 .enable_reg = 0x970,
121 .enable_mask = BIT(0),
122 .hw.init = &(struct clk_init_data){
123 .name = "video_cc_qdss_trig_clk",
124 .ops = &clk_branch2_ops,
125 },
126 },
127};
128
129static struct clk_branch video_cc_qdss_tsctr_div8_clk = {
130 .halt_reg = 0x9d0,
131 .halt_check = BRANCH_HALT,
132 .clkr = {
133 .enable_reg = 0x9d0,
134 .enable_mask = BIT(0),
135 .hw.init = &(struct clk_init_data){
136 .name = "video_cc_qdss_tsctr_div8_clk",
137 .ops = &clk_branch2_ops,
138 },
139 },
140};
141
142static struct clk_branch video_cc_vcodec0_axi_clk = {
143 .halt_reg = 0x930,
144 .halt_check = BRANCH_HALT,
145 .clkr = {
146 .enable_reg = 0x930,
147 .enable_mask = BIT(0),
148 .hw.init = &(struct clk_init_data){
149 .name = "video_cc_vcodec0_axi_clk",
150 .ops = &clk_branch2_ops,
151 },
152 },
153};
154
155static struct clk_branch video_cc_vcodec0_core_clk = {
156 .halt_reg = 0x890,
157 .halt_check = BRANCH_VOTED,
158 .clkr = {
159 .enable_reg = 0x890,
160 .enable_mask = BIT(0),
161 .hw.init = &(struct clk_init_data){
162 .name = "video_cc_vcodec0_core_clk",
163 .parent_names = (const char *[]){
164 "video_cc_venus_clk_src",
165 },
166 .num_parents = 1,
167 .flags = CLK_SET_RATE_PARENT,
168 .ops = &clk_branch2_ops,
169 },
170 },
171};
172
173static struct clk_branch video_cc_vcodec1_axi_clk = {
174 .halt_reg = 0x950,
175 .halt_check = BRANCH_HALT,
176 .clkr = {
177 .enable_reg = 0x950,
178 .enable_mask = BIT(0),
179 .hw.init = &(struct clk_init_data){
180 .name = "video_cc_vcodec1_axi_clk",
181 .ops = &clk_branch2_ops,
182 },
183 },
184};
185
186static struct clk_branch video_cc_vcodec1_core_clk = {
187 .halt_reg = 0x8d0,
188 .halt_check = BRANCH_VOTED,
189 .clkr = {
190 .enable_reg = 0x8d0,
191 .enable_mask = BIT(0),
192 .hw.init = &(struct clk_init_data){
193 .name = "video_cc_vcodec1_core_clk",
194 .parent_names = (const char *[]){
195 "video_cc_venus_clk_src",
196 },
197 .num_parents = 1,
198 .flags = CLK_SET_RATE_PARENT,
199 .ops = &clk_branch2_ops,
200 },
201 },
202};
203
204static struct clk_branch video_cc_venus_ahb_clk = {
205 .halt_reg = 0x9b0,
206 .halt_check = BRANCH_HALT,
207 .clkr = {
208 .enable_reg = 0x9b0,
209 .enable_mask = BIT(0),
210 .hw.init = &(struct clk_init_data){
211 .name = "video_cc_venus_ahb_clk",
212 .ops = &clk_branch2_ops,
213 },
214 },
215};
216
217static struct clk_branch video_cc_venus_ctl_axi_clk = {
218 .halt_reg = 0x910,
219 .halt_check = BRANCH_HALT,
220 .clkr = {
221 .enable_reg = 0x910,
222 .enable_mask = BIT(0),
223 .hw.init = &(struct clk_init_data){
224 .name = "video_cc_venus_ctl_axi_clk",
225 .ops = &clk_branch2_ops,
226 },
227 },
228};
229
230static struct clk_branch video_cc_venus_ctl_core_clk = {
231 .halt_reg = 0x850,
232 .halt_check = BRANCH_HALT,
233 .clkr = {
234 .enable_reg = 0x850,
235 .enable_mask = BIT(0),
236 .hw.init = &(struct clk_init_data){
237 .name = "video_cc_venus_ctl_core_clk",
238 .parent_names = (const char *[]){
239 "video_cc_venus_clk_src",
240 },
241 .num_parents = 1,
242 .flags = CLK_SET_RATE_PARENT,
243 .ops = &clk_branch2_ops,
244 },
245 },
246};
247
248static struct gdsc venus_gdsc = {
249 .gdscr = 0x814,
250 .pd = {
251 .name = "venus_gdsc",
252 },
253 .cxcs = (unsigned int []){ 0x850, 0x910 },
254 .cxc_count = 2,
255 .pwrsts = PWRSTS_OFF_ON,
256 .flags = POLL_CFG_GDSCR,
257};
258
259static struct gdsc vcodec0_gdsc = {
260 .gdscr = 0x874,
261 .pd = {
262 .name = "vcodec0_gdsc",
263 },
264 .cxcs = (unsigned int []){ 0x890, 0x930 },
265 .cxc_count = 2,
266 .flags = HW_CTRL | POLL_CFG_GDSCR,
267 .pwrsts = PWRSTS_OFF_ON,
268};
269
270static struct gdsc vcodec1_gdsc = {
271 .gdscr = 0x8b4,
272 .pd = {
273 .name = "vcodec1_gdsc",
274 },
275 .cxcs = (unsigned int []){ 0x8d0, 0x950 },
276 .cxc_count = 2,
277 .flags = HW_CTRL | POLL_CFG_GDSCR,
278 .pwrsts = PWRSTS_OFF_ON,
279};
280
281static struct clk_regmap *video_cc_sdm845_clocks[] = {
282 [VIDEO_CC_APB_CLK] = &video_cc_apb_clk.clkr,
283 [VIDEO_CC_AT_CLK] = &video_cc_at_clk.clkr,
284 [VIDEO_CC_QDSS_TRIG_CLK] = &video_cc_qdss_trig_clk.clkr,
285 [VIDEO_CC_QDSS_TSCTR_DIV8_CLK] = &video_cc_qdss_tsctr_div8_clk.clkr,
286 [VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr,
287 [VIDEO_CC_VCODEC0_CORE_CLK] = &video_cc_vcodec0_core_clk.clkr,
288 [VIDEO_CC_VCODEC1_AXI_CLK] = &video_cc_vcodec1_axi_clk.clkr,
289 [VIDEO_CC_VCODEC1_CORE_CLK] = &video_cc_vcodec1_core_clk.clkr,
290 [VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr,
291 [VIDEO_CC_VENUS_CLK_SRC] = &video_cc_venus_clk_src.clkr,
292 [VIDEO_CC_VENUS_CTL_AXI_CLK] = &video_cc_venus_ctl_axi_clk.clkr,
293 [VIDEO_CC_VENUS_CTL_CORE_CLK] = &video_cc_venus_ctl_core_clk.clkr,
294 [VIDEO_PLL0] = &video_pll0.clkr,
295};
296
297static struct gdsc *video_cc_sdm845_gdscs[] = {
298 [VENUS_GDSC] = &venus_gdsc,
299 [VCODEC0_GDSC] = &vcodec0_gdsc,
300 [VCODEC1_GDSC] = &vcodec1_gdsc,
301};
302
303static const struct regmap_config video_cc_sdm845_regmap_config = {
304 .reg_bits = 32,
305 .reg_stride = 4,
306 .val_bits = 32,
307 .max_register = 0xb90,
308 .fast_io = true,
309};
310
311static const struct qcom_cc_desc video_cc_sdm845_desc = {
312 .config = &video_cc_sdm845_regmap_config,
313 .clks = video_cc_sdm845_clocks,
314 .num_clks = ARRAY_SIZE(video_cc_sdm845_clocks),
315 .gdscs = video_cc_sdm845_gdscs,
316 .num_gdscs = ARRAY_SIZE(video_cc_sdm845_gdscs),
317};
318
319static const struct of_device_id video_cc_sdm845_match_table[] = {
320 { .compatible = "qcom,sdm845-videocc" },
321 { }
322};
323MODULE_DEVICE_TABLE(of, video_cc_sdm845_match_table);
324
325static int video_cc_sdm845_probe(struct platform_device *pdev)
326{
327 struct regmap *regmap;
328
329 regmap = qcom_cc_map(pdev, &video_cc_sdm845_desc);
330 if (IS_ERR(regmap))
331 return PTR_ERR(regmap);
332
333 clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config);
334
335 return qcom_cc_really_probe(pdev, &video_cc_sdm845_desc, regmap);
336}
337
338static struct platform_driver video_cc_sdm845_driver = {
339 .probe = video_cc_sdm845_probe,
340 .driver = {
341 .name = "sdm845-videocc",
342 .of_match_table = video_cc_sdm845_match_table,
343 },
344};
345
346static int __init video_cc_sdm845_init(void)
347{
348 return platform_driver_register(&video_cc_sdm845_driver);
349}
350subsys_initcall(video_cc_sdm845_init);
351
352static void __exit video_cc_sdm845_exit(void)
353{
354 platform_driver_unregister(&video_cc_sdm845_driver);
355}
356module_exit(video_cc_sdm845_exit);
357
358MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index ef76c861ec84..f9ba71311727 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -7,6 +7,7 @@ config CLK_RENESAS
7 select CLK_R8A7740 if ARCH_R8A7740 7 select CLK_R8A7740 if ARCH_R8A7740
8 select CLK_R8A7743 if ARCH_R8A7743 8 select CLK_R8A7743 if ARCH_R8A7743
9 select CLK_R8A7745 if ARCH_R8A7745 9 select CLK_R8A7745 if ARCH_R8A7745
10 select CLK_R8A77470 if ARCH_R8A77470
10 select CLK_R8A7778 if ARCH_R8A7778 11 select CLK_R8A7778 if ARCH_R8A7778
11 select CLK_R8A7779 if ARCH_R8A7779 12 select CLK_R8A7779 if ARCH_R8A7779
12 select CLK_R8A7790 if ARCH_R8A7790 13 select CLK_R8A7790 if ARCH_R8A7790
@@ -18,6 +19,7 @@ config CLK_RENESAS
18 select CLK_R8A77965 if ARCH_R8A77965 19 select CLK_R8A77965 if ARCH_R8A77965
19 select CLK_R8A77970 if ARCH_R8A77970 20 select CLK_R8A77970 if ARCH_R8A77970
20 select CLK_R8A77980 if ARCH_R8A77980 21 select CLK_R8A77980 if ARCH_R8A77980
22 select CLK_R8A77990 if ARCH_R8A77990
21 select CLK_R8A77995 if ARCH_R8A77995 23 select CLK_R8A77995 if ARCH_R8A77995
22 select CLK_SH73A0 if ARCH_SH73A0 24 select CLK_SH73A0 if ARCH_SH73A0
23 25
@@ -60,6 +62,10 @@ config CLK_R8A7745
60 bool "RZ/G1E clock support" if COMPILE_TEST 62 bool "RZ/G1E clock support" if COMPILE_TEST
61 select CLK_RCAR_GEN2_CPG 63 select CLK_RCAR_GEN2_CPG
62 64
65config CLK_R8A77470
66 bool "RZ/G1C clock support" if COMPILE_TEST
67 select CLK_RCAR_GEN2_CPG
68
63config CLK_R8A7778 69config CLK_R8A7778
64 bool "R-Car M1A clock support" if COMPILE_TEST 70 bool "R-Car M1A clock support" if COMPILE_TEST
65 select CLK_RENESAS_CPG_MSTP 71 select CLK_RENESAS_CPG_MSTP
@@ -111,6 +117,10 @@ config CLK_R8A77980
111 bool "R-Car V3H clock support" if COMPILE_TEST 117 bool "R-Car V3H clock support" if COMPILE_TEST
112 select CLK_RCAR_GEN3_CPG 118 select CLK_RCAR_GEN3_CPG
113 119
120config CLK_R8A77990
121 bool "R-Car E3 clock support" if COMPILE_TEST
122 select CLK_RCAR_GEN3_CPG
123
114config CLK_R8A77995 124config CLK_R8A77995
115 bool "R-Car D3 clock support" if COMPILE_TEST 125 bool "R-Car D3 clock support" if COMPILE_TEST
116 select CLK_RCAR_GEN3_CPG 126 select CLK_RCAR_GEN3_CPG
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 6c0f19636e3e..fe5bac9215e5 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o
6obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o 6obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o
7obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o 7obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
8obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o 8obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
9obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
9obj-$(CONFIG_CLK_R8A7778) += clk-r8a7778.o 10obj-$(CONFIG_CLK_R8A7778) += clk-r8a7778.o
10obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o 11obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o
11obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o 12obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
@@ -17,6 +18,7 @@ obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
17obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o 18obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
18obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o 19obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
19obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o 20obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
21obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
20obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o 22obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
21obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o 23obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
22 24
diff --git a/drivers/clk/renesas/r8a7743-cpg-mssr.c b/drivers/clk/renesas/r8a7743-cpg-mssr.c
index d3c8b1e2969f..011c170ec3f9 100644
--- a/drivers/clk/renesas/r8a7743-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7743-cpg-mssr.c
@@ -52,7 +52,6 @@ static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
52 52
53 /* Core Clock Outputs */ 53 /* Core Clock Outputs */
54 DEF_BASE("z", R8A7743_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0), 54 DEF_BASE("z", R8A7743_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
55 DEF_BASE("lb", R8A7743_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
56 DEF_BASE("sdh", R8A7743_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1), 55 DEF_BASE("sdh", R8A7743_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
57 DEF_BASE("sd0", R8A7743_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1), 56 DEF_BASE("sd0", R8A7743_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
58 DEF_BASE("qspi", R8A7743_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2), 57 DEF_BASE("qspi", R8A7743_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
@@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
63 DEF_FIXED("zs", R8A7743_CLK_ZS, CLK_PLL1, 6, 1), 62 DEF_FIXED("zs", R8A7743_CLK_ZS, CLK_PLL1, 6, 1),
64 DEF_FIXED("hp", R8A7743_CLK_HP, CLK_PLL1, 12, 1), 63 DEF_FIXED("hp", R8A7743_CLK_HP, CLK_PLL1, 12, 1),
65 DEF_FIXED("b", R8A7743_CLK_B, CLK_PLL1, 12, 1), 64 DEF_FIXED("b", R8A7743_CLK_B, CLK_PLL1, 12, 1),
65 DEF_FIXED("lb", R8A7743_CLK_LB, CLK_PLL1, 24, 1),
66 DEF_FIXED("p", R8A7743_CLK_P, CLK_PLL1, 24, 1), 66 DEF_FIXED("p", R8A7743_CLK_P, CLK_PLL1, 24, 1),
67 DEF_FIXED("cl", R8A7743_CLK_CL, CLK_PLL1, 48, 1), 67 DEF_FIXED("cl", R8A7743_CLK_CL, CLK_PLL1, 48, 1),
68 DEF_FIXED("m2", R8A7743_CLK_M2, CLK_PLL1, 8, 1), 68 DEF_FIXED("m2", R8A7743_CLK_M2, CLK_PLL1, 8, 1),
diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas/r8a7745-cpg-mssr.c
index 87f5a3619e4f..4b0a9243b748 100644
--- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
@@ -51,7 +51,6 @@ static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {
51 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 51 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
52 52
53 /* Core Clock Outputs */ 53 /* Core Clock Outputs */
54 DEF_BASE("lb", R8A7745_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
55 DEF_BASE("sdh", R8A7745_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1), 54 DEF_BASE("sdh", R8A7745_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
56 DEF_BASE("sd0", R8A7745_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1), 55 DEF_BASE("sd0", R8A7745_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
57 DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2), 56 DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
@@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {
63 DEF_FIXED("zs", R8A7745_CLK_ZS, CLK_PLL1, 6, 1), 62 DEF_FIXED("zs", R8A7745_CLK_ZS, CLK_PLL1, 6, 1),
64 DEF_FIXED("hp", R8A7745_CLK_HP, CLK_PLL1, 12, 1), 63 DEF_FIXED("hp", R8A7745_CLK_HP, CLK_PLL1, 12, 1),
65 DEF_FIXED("b", R8A7745_CLK_B, CLK_PLL1, 12, 1), 64 DEF_FIXED("b", R8A7745_CLK_B, CLK_PLL1, 12, 1),
65 DEF_FIXED("lb", R8A7745_CLK_LB, CLK_PLL1, 24, 1),
66 DEF_FIXED("p", R8A7745_CLK_P, CLK_PLL1, 24, 1), 66 DEF_FIXED("p", R8A7745_CLK_P, CLK_PLL1, 24, 1),
67 DEF_FIXED("cl", R8A7745_CLK_CL, CLK_PLL1, 48, 1), 67 DEF_FIXED("cl", R8A7745_CLK_CL, CLK_PLL1, 48, 1),
68 DEF_FIXED("cp", R8A7745_CLK_CP, CLK_PLL1, 48, 1), 68 DEF_FIXED("cp", R8A7745_CLK_CP, CLK_PLL1, 48, 1),
diff --git a/drivers/clk/renesas/r8a77470-cpg-mssr.c b/drivers/clk/renesas/r8a77470-cpg-mssr.c
new file mode 100644
index 000000000000..ab0fb10b6bf0
--- /dev/null
+++ b/drivers/clk/renesas/r8a77470-cpg-mssr.c
@@ -0,0 +1,229 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * r8a77470 Clock Pulse Generator / Module Standby and Software Reset
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <linux/device.h>
9#include <linux/init.h>
10#include <linux/kernel.h>
11#include <linux/soc/renesas/rcar-rst.h>
12
13#include <dt-bindings/clock/r8a77470-cpg-mssr.h>
14
15#include "renesas-cpg-mssr.h"
16#include "rcar-gen2-cpg.h"
17
18enum clk_ids {
19 /* Core Clock Outputs exported to DT */
20 LAST_DT_CORE_CLK = R8A77470_CLK_OSC,
21
22 /* External Input Clocks */
23 CLK_EXTAL,
24 CLK_USB_EXTAL,
25
26 /* Internal Core Clocks */
27 CLK_MAIN,
28 CLK_PLL0,
29 CLK_PLL1,
30 CLK_PLL3,
31 CLK_PLL1_DIV2,
32
33 /* Module Clocks */
34 MOD_CLK_BASE
35};
36
37static const struct cpg_core_clk r8a77470_core_clks[] __initconst = {
38 /* External Clock Inputs */
39 DEF_INPUT("extal", CLK_EXTAL),
40 DEF_INPUT("usb_extal", CLK_USB_EXTAL),
41
42 /* Internal Core Clocks */
43 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
44 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
45 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
46 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
47
48 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
49
50 /* Core Clock Outputs */
51 DEF_BASE("sdh", R8A77470_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
52 DEF_BASE("sd0", R8A77470_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
53 DEF_BASE("sd1", R8A77470_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1),
54 DEF_BASE("qspi", R8A77470_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
55 DEF_BASE("rcan", R8A77470_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
56
57 DEF_FIXED("z2", R8A77470_CLK_Z2, CLK_PLL0, 1, 1),
58 DEF_FIXED("zx", R8A77470_CLK_ZX, CLK_PLL1, 3, 1),
59 DEF_FIXED("zs", R8A77470_CLK_ZS, CLK_PLL1, 6, 1),
60 DEF_FIXED("hp", R8A77470_CLK_HP, CLK_PLL1, 12, 1),
61 DEF_FIXED("b", R8A77470_CLK_B, CLK_PLL1, 12, 1),
62 DEF_FIXED("lb", R8A77470_CLK_LB, CLK_PLL1, 24, 1),
63 DEF_FIXED("p", R8A77470_CLK_P, CLK_PLL1, 24, 1),
64 DEF_FIXED("cl", R8A77470_CLK_CL, CLK_PLL1, 48, 1),
65 DEF_FIXED("cp", R8A77470_CLK_CP, CLK_PLL1, 48, 1),
66 DEF_FIXED("m2", R8A77470_CLK_M2, CLK_PLL1, 8, 1),
67 DEF_FIXED("zb3", R8A77470_CLK_ZB3, CLK_PLL3, 4, 1),
68 DEF_FIXED("mp", R8A77470_CLK_MP, CLK_PLL1_DIV2, 15, 1),
69 DEF_FIXED("cpex", R8A77470_CLK_CPEX, CLK_EXTAL, 2, 1),
70 DEF_FIXED("r", R8A77470_CLK_R, CLK_PLL1, 49152, 1),
71 DEF_FIXED("osc", R8A77470_CLK_OSC, CLK_PLL1, 12288, 1),
72
73 DEF_DIV6P1("sd2", R8A77470_CLK_SD2, CLK_PLL1_DIV2, 0x078),
74};
75
76static const struct mssr_mod_clk r8a77470_mod_clks[] __initconst = {
77 DEF_MOD("msiof0", 0, R8A77470_CLK_MP),
78 DEF_MOD("vcp0", 101, R8A77470_CLK_ZS),
79 DEF_MOD("vpc0", 103, R8A77470_CLK_ZS),
80 DEF_MOD("tmu1", 111, R8A77470_CLK_P),
81 DEF_MOD("3dg", 112, R8A77470_CLK_ZS),
82 DEF_MOD("2d-dmac", 115, R8A77470_CLK_ZS),
83 DEF_MOD("fdp1-0", 119, R8A77470_CLK_ZS),
84 DEF_MOD("tmu3", 121, R8A77470_CLK_P),
85 DEF_MOD("tmu2", 122, R8A77470_CLK_P),
86 DEF_MOD("cmt0", 124, R8A77470_CLK_R),
87 DEF_MOD("vsp1du0", 128, R8A77470_CLK_ZS),
88 DEF_MOD("vsp1-sy", 131, R8A77470_CLK_ZS),
89 DEF_MOD("msiof2", 205, R8A77470_CLK_MP),
90 DEF_MOD("msiof1", 208, R8A77470_CLK_MP),
91 DEF_MOD("sys-dmac1", 218, R8A77470_CLK_ZS),
92 DEF_MOD("sys-dmac0", 219, R8A77470_CLK_ZS),
93 DEF_MOD("sdhi2", 312, R8A77470_CLK_SD2),
94 DEF_MOD("sdhi1", 313, R8A77470_CLK_SD1),
95 DEF_MOD("sdhi0", 314, R8A77470_CLK_SD0),
96 DEF_MOD("usbhs-dmac0-ch1", 326, R8A77470_CLK_HP),
97 DEF_MOD("usbhs-dmac1-ch1", 327, R8A77470_CLK_HP),
98 DEF_MOD("cmt1", 329, R8A77470_CLK_R),
99 DEF_MOD("usbhs-dmac0-ch0", 330, R8A77470_CLK_HP),
100 DEF_MOD("usbhs-dmac1-ch0", 331, R8A77470_CLK_HP),
101 DEF_MOD("rwdt", 402, R8A77470_CLK_R),
102 DEF_MOD("irqc", 407, R8A77470_CLK_CP),
103 DEF_MOD("intc-sys", 408, R8A77470_CLK_ZS),
104 DEF_MOD("audio-dmac0", 502, R8A77470_CLK_HP),
105 DEF_MOD("pwm", 523, R8A77470_CLK_P),
106 DEF_MOD("usb-ehci-0", 703, R8A77470_CLK_MP),
107 DEF_MOD("usbhs-0", 704, R8A77470_CLK_HP),
108 DEF_MOD("usb-ehci-1", 705, R8A77470_CLK_MP),
109 DEF_MOD("usbhs-1", 706, R8A77470_CLK_HP),
110 DEF_MOD("hscif2", 713, R8A77470_CLK_ZS),
111 DEF_MOD("scif5", 714, R8A77470_CLK_P),
112 DEF_MOD("scif4", 715, R8A77470_CLK_P),
113 DEF_MOD("hscif1", 716, R8A77470_CLK_ZS),
114 DEF_MOD("hscif0", 717, R8A77470_CLK_ZS),
115 DEF_MOD("scif3", 718, R8A77470_CLK_P),
116 DEF_MOD("scif2", 719, R8A77470_CLK_P),
117 DEF_MOD("scif1", 720, R8A77470_CLK_P),
118 DEF_MOD("scif0", 721, R8A77470_CLK_P),
119 DEF_MOD("du1", 723, R8A77470_CLK_ZX),
120 DEF_MOD("du0", 724, R8A77470_CLK_ZX),
121 DEF_MOD("ipmmu-sgx", 800, R8A77470_CLK_ZX),
122 DEF_MOD("etheravb", 812, R8A77470_CLK_HP),
123 DEF_MOD("ether", 813, R8A77470_CLK_P),
124 DEF_MOD("gpio5", 907, R8A77470_CLK_CP),
125 DEF_MOD("gpio4", 908, R8A77470_CLK_CP),
126 DEF_MOD("gpio3", 909, R8A77470_CLK_CP),
127 DEF_MOD("gpio2", 910, R8A77470_CLK_CP),
128 DEF_MOD("gpio1", 911, R8A77470_CLK_CP),
129 DEF_MOD("gpio0", 912, R8A77470_CLK_CP),
130 DEF_MOD("can1", 915, R8A77470_CLK_P),
131 DEF_MOD("can0", 916, R8A77470_CLK_P),
132 DEF_MOD("qspi_mod-1", 917, R8A77470_CLK_QSPI),
133 DEF_MOD("qspi_mod-0", 918, R8A77470_CLK_QSPI),
134 DEF_MOD("i2c4", 927, R8A77470_CLK_HP),
135 DEF_MOD("i2c3", 928, R8A77470_CLK_HP),
136 DEF_MOD("i2c2", 929, R8A77470_CLK_HP),
137 DEF_MOD("i2c1", 930, R8A77470_CLK_HP),
138 DEF_MOD("i2c0", 931, R8A77470_CLK_HP),
139 DEF_MOD("ssi-all", 1005, R8A77470_CLK_P),
140 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
141 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
142 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
143 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
144 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
145 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
146 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
147 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
148 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
149 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
150 DEF_MOD("scu-all", 1017, R8A77470_CLK_P),
151 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
152 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
153 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
154 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
155 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
156 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
157 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
158 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
159 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
160 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
161};
162
163static const unsigned int r8a77470_crit_mod_clks[] __initconst = {
164 MOD_CLK_ID(402), /* RWDT */
165 MOD_CLK_ID(408), /* INTC-SYS (GIC) */
166};
167
168/*
169 * CPG Clock Data
170 */
171
172/*
173 * MD EXTAL PLL0 PLL1 PLL3
174 * 14 13 (MHz) *1 *2
175 *---------------------------------------------------
176 * 0 0 20 x80 x78 x50
177 * 0 1 26 x60 x60 x56
178 * 1 0 Prohibitted setting
179 * 1 1 30 x52 x52 x50
180 *
181 * *1 : Table 7.4 indicates VCO output (PLL0 = VCO)
182 * *2 : Table 7.4 indicates VCO output (PLL1 = VCO)
183 */
184#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
185 (((md) & BIT(13)) >> 13))
186
187static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = {
188 /* EXTAL div PLL1 mult x2 PLL3 mult */
189 { 1, 156, 50, },
190 { 1, 120, 56, },
191 { /* Invalid*/ },
192 { 1, 104, 50, },
193};
194
195static int __init r8a77470_cpg_mssr_init(struct device *dev)
196{
197 const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
198 u32 cpg_mode;
199 int error;
200
201 error = rcar_rst_read_mode_pins(&cpg_mode);
202 if (error)
203 return error;
204
205 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
206
207 return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
208}
209
210const struct cpg_mssr_info r8a77470_cpg_mssr_info __initconst = {
211 /* Core Clocks */
212 .core_clks = r8a77470_core_clks,
213 .num_core_clks = ARRAY_SIZE(r8a77470_core_clks),
214 .last_dt_core_clk = LAST_DT_CORE_CLK,
215 .num_total_core_clks = MOD_CLK_BASE,
216
217 /* Module Clocks */
218 .mod_clks = r8a77470_mod_clks,
219 .num_mod_clks = ARRAY_SIZE(r8a77470_mod_clks),
220 .num_hw_mod_clks = 12 * 32,
221
222 /* Critical Module Clocks */
223 .crit_mod_clks = r8a77470_crit_mod_clks,
224 .num_crit_mod_clks = ARRAY_SIZE(r8a77470_crit_mod_clks),
225
226 /* Callbacks */
227 .init = r8a77470_cpg_mssr_init,
228 .cpg_clk_register = rcar_gen2_cpg_clk_register,
229};
diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c b/drivers/clk/renesas/r8a7791-cpg-mssr.c
index 820b220b09cc..1b91f03b7598 100644
--- a/drivers/clk/renesas/r8a7791-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
@@ -57,7 +57,6 @@ static struct cpg_core_clk r8a7791_core_clks[] __initdata = {
57 57
58 /* Core Clock Outputs */ 58 /* Core Clock Outputs */
59 DEF_BASE("z", R8A7791_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0), 59 DEF_BASE("z", R8A7791_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
60 DEF_BASE("lb", R8A7791_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
61 DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1), 60 DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
62 DEF_BASE("sdh", R8A7791_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1), 61 DEF_BASE("sdh", R8A7791_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
63 DEF_BASE("sd0", R8A7791_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1), 62 DEF_BASE("sd0", R8A7791_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
@@ -70,6 +69,7 @@ static struct cpg_core_clk r8a7791_core_clks[] __initdata = {
70 DEF_FIXED("hp", R8A7791_CLK_HP, CLK_PLL1, 12, 1), 69 DEF_FIXED("hp", R8A7791_CLK_HP, CLK_PLL1, 12, 1),
71 DEF_FIXED("i", R8A7791_CLK_I, CLK_PLL1, 2, 1), 70 DEF_FIXED("i", R8A7791_CLK_I, CLK_PLL1, 2, 1),
72 DEF_FIXED("b", R8A7791_CLK_B, CLK_PLL1, 12, 1), 71 DEF_FIXED("b", R8A7791_CLK_B, CLK_PLL1, 12, 1),
72 DEF_FIXED("lb", R8A7791_CLK_LB, CLK_PLL1, 24, 1),
73 DEF_FIXED("p", R8A7791_CLK_P, CLK_PLL1, 24, 1), 73 DEF_FIXED("p", R8A7791_CLK_P, CLK_PLL1, 24, 1),
74 DEF_FIXED("cl", R8A7791_CLK_CL, CLK_PLL1, 48, 1), 74 DEF_FIXED("cl", R8A7791_CLK_CL, CLK_PLL1, 48, 1),
75 DEF_FIXED("m2", R8A7791_CLK_M2, CLK_PLL1, 8, 1), 75 DEF_FIXED("m2", R8A7791_CLK_M2, CLK_PLL1, 8, 1),
diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c
index 609a54080496..493e07859f5f 100644
--- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
@@ -53,7 +53,6 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
53 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 53 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
54 54
55 /* Core Clock Outputs */ 55 /* Core Clock Outputs */
56 DEF_BASE("lb", R8A7792_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
57 DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2), 56 DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
58 57
59 DEF_FIXED("z", R8A7792_CLK_Z, CLK_PLL0, 1, 1), 58 DEF_FIXED("z", R8A7792_CLK_Z, CLK_PLL0, 1, 1),
@@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
63 DEF_FIXED("hp", R8A7792_CLK_HP, CLK_PLL1, 12, 1), 62 DEF_FIXED("hp", R8A7792_CLK_HP, CLK_PLL1, 12, 1),
64 DEF_FIXED("i", R8A7792_CLK_I, CLK_PLL1, 3, 1), 63 DEF_FIXED("i", R8A7792_CLK_I, CLK_PLL1, 3, 1),
65 DEF_FIXED("b", R8A7792_CLK_B, CLK_PLL1, 12, 1), 64 DEF_FIXED("b", R8A7792_CLK_B, CLK_PLL1, 12, 1),
65 DEF_FIXED("lb", R8A7792_CLK_LB, CLK_PLL1, 24, 1),
66 DEF_FIXED("p", R8A7792_CLK_P, CLK_PLL1, 24, 1), 66 DEF_FIXED("p", R8A7792_CLK_P, CLK_PLL1, 24, 1),
67 DEF_FIXED("cl", R8A7792_CLK_CL, CLK_PLL1, 48, 1), 67 DEF_FIXED("cl", R8A7792_CLK_CL, CLK_PLL1, 48, 1),
68 DEF_FIXED("m2", R8A7792_CLK_M2, CLK_PLL1, 8, 1), 68 DEF_FIXED("m2", R8A7792_CLK_M2, CLK_PLL1, 8, 1),
diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c
index 2a40bbeaeeaf..088f4b79fdfc 100644
--- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
@@ -55,7 +55,6 @@ static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
55 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 55 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
56 56
57 /* Core Clock Outputs */ 57 /* Core Clock Outputs */
58 DEF_BASE("lb", R8A7794_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
59 DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1), 58 DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
60 DEF_BASE("sdh", R8A7794_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1), 59 DEF_BASE("sdh", R8A7794_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
61 DEF_BASE("sd0", R8A7794_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1), 60 DEF_BASE("sd0", R8A7794_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
@@ -69,6 +68,7 @@ static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
69 DEF_FIXED("hp", R8A7794_CLK_HP, CLK_PLL1, 12, 1), 68 DEF_FIXED("hp", R8A7794_CLK_HP, CLK_PLL1, 12, 1),
70 DEF_FIXED("i", R8A7794_CLK_I, CLK_PLL1, 2, 1), 69 DEF_FIXED("i", R8A7794_CLK_I, CLK_PLL1, 2, 1),
71 DEF_FIXED("b", R8A7794_CLK_B, CLK_PLL1, 12, 1), 70 DEF_FIXED("b", R8A7794_CLK_B, CLK_PLL1, 12, 1),
71 DEF_FIXED("lb", R8A7794_CLK_LB, CLK_PLL1, 24, 1),
72 DEF_FIXED("p", R8A7794_CLK_P, CLK_PLL1, 24, 1), 72 DEF_FIXED("p", R8A7794_CLK_P, CLK_PLL1, 24, 1),
73 DEF_FIXED("cl", R8A7794_CLK_CL, CLK_PLL1, 48, 1), 73 DEF_FIXED("cl", R8A7794_CLK_CL, CLK_PLL1, 48, 1),
74 DEF_FIXED("cp", R8A7794_CLK_CP, CLK_PLL1, 48, 1), 74 DEF_FIXED("cp", R8A7794_CLK_CP, CLK_PLL1, 48, 1),
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index b1acfb60351c..8fae5e9c4a77 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -116,6 +116,10 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
116 DEF_MOD("scif3", 204, R8A77965_CLK_S3D4), 116 DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),
117 DEF_MOD("scif1", 206, R8A77965_CLK_S3D4), 117 DEF_MOD("scif1", 206, R8A77965_CLK_S3D4),
118 DEF_MOD("scif0", 207, R8A77965_CLK_S3D4), 118 DEF_MOD("scif0", 207, R8A77965_CLK_S3D4),
119 DEF_MOD("msiof3", 208, R8A77965_CLK_MSO),
120 DEF_MOD("msiof2", 209, R8A77965_CLK_MSO),
121 DEF_MOD("msiof1", 210, R8A77965_CLK_MSO),
122 DEF_MOD("msiof0", 211, R8A77965_CLK_MSO),
119 DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S0D3), 123 DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S0D3),
120 DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3), 124 DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3),
121 DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3), 125 DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c
index 7aaae73a321a..d7ebd9ec0059 100644
--- a/drivers/clk/renesas/r8a77980-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -116,7 +116,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
116 DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3), 116 DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
117 DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4), 117 DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4),
118 DEF_MOD("sdif", 314, R8A77980_CLK_SD0), 118 DEF_MOD("sdif", 314, R8A77980_CLK_SD0),
119 DEF_MOD("pciec0", 319, R8A77980_CLK_S3D1), 119 DEF_MOD("pciec0", 319, R8A77980_CLK_S2D2),
120 DEF_MOD("intc-ex", 407, R8A77980_CLK_CP), 120 DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
121 DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3), 121 DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
122 DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1), 122 DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1),
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
new file mode 100644
index 000000000000..9e14f1486fbb
--- /dev/null
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -0,0 +1,289 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * r8a77990 Clock Pulse Generator / Module Standby and Software Reset
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 *
7 * Based on r8a7795-cpg-mssr.c
8 *
9 * Copyright (C) 2015 Glider bvba
10 * Copyright (C) 2015 Renesas Electronics Corp.
11 */
12
13#include <linux/device.h>
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/soc/renesas/rcar-rst.h>
17
18#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
19
20#include "renesas-cpg-mssr.h"
21#include "rcar-gen3-cpg.h"
22
23enum clk_ids {
24 /* Core Clock Outputs exported to DT */
25 LAST_DT_CORE_CLK = R8A77990_CLK_CPEX,
26
27 /* External Input Clocks */
28 CLK_EXTAL,
29
30 /* Internal Core Clocks */
31 CLK_MAIN,
32 CLK_PLL0,
33 CLK_PLL1,
34 CLK_PLL3,
35 CLK_PLL0D4,
36 CLK_PLL0D6,
37 CLK_PLL0D8,
38 CLK_PLL0D20,
39 CLK_PLL0D24,
40 CLK_PLL1D2,
41 CLK_PE,
42 CLK_S0,
43 CLK_S1,
44 CLK_S2,
45 CLK_S3,
46 CLK_SDSRC,
47
48 /* Module Clocks */
49 MOD_CLK_BASE
50};
51
52static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
53 /* External Clock Inputs */
54 DEF_INPUT("extal", CLK_EXTAL),
55
56 /* Internal Core Clocks */
57 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
58 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
59 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
60
61 DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100),
62 DEF_FIXED(".pll0d4", CLK_PLL0D4, CLK_PLL0, 4, 1),
63 DEF_FIXED(".pll0d6", CLK_PLL0D6, CLK_PLL0, 6, 1),
64 DEF_FIXED(".pll0d8", CLK_PLL0D8, CLK_PLL0, 8, 1),
65 DEF_FIXED(".pll0d20", CLK_PLL0D20, CLK_PLL0, 20, 1),
66 DEF_FIXED(".pll0d24", CLK_PLL0D24, CLK_PLL0, 24, 1),
67 DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
68 DEF_FIXED(".pe", CLK_PE, CLK_PLL0D20, 1, 1),
69 DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
70 DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
71 DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
72 DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
73 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
74
75 /* Core Clock Outputs */
76 DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1),
77 DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1),
78 DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1),
79 DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1),
80 DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1),
81 DEF_FIXED("s0d1", R8A77990_CLK_S0D1, CLK_S0, 1, 1),
82 DEF_FIXED("s0d3", R8A77990_CLK_S0D3, CLK_S0, 3, 1),
83 DEF_FIXED("s0d6", R8A77990_CLK_S0D6, CLK_S0, 6, 1),
84 DEF_FIXED("s0d12", R8A77990_CLK_S0D12, CLK_S0, 12, 1),
85 DEF_FIXED("s0d24", R8A77990_CLK_S0D24, CLK_S0, 24, 1),
86 DEF_FIXED("s1d1", R8A77990_CLK_S1D1, CLK_S1, 1, 1),
87 DEF_FIXED("s1d2", R8A77990_CLK_S1D2, CLK_S1, 2, 1),
88 DEF_FIXED("s1d4", R8A77990_CLK_S1D4, CLK_S1, 4, 1),
89 DEF_FIXED("s2d1", R8A77990_CLK_S2D1, CLK_S2, 1, 1),
90 DEF_FIXED("s2d2", R8A77990_CLK_S2D2, CLK_S2, 2, 1),
91 DEF_FIXED("s2d4", R8A77990_CLK_S2D4, CLK_S2, 4, 1),
92 DEF_FIXED("s3d1", R8A77990_CLK_S3D1, CLK_S3, 1, 1),
93 DEF_FIXED("s3d2", R8A77990_CLK_S3D2, CLK_S3, 2, 1),
94 DEF_FIXED("s3d4", R8A77990_CLK_S3D4, CLK_S3, 4, 1),
95
96 DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, CLK_SDSRC, 0x0074),
97 DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, CLK_SDSRC, 0x0078),
98 DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c),
99
100 DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
101 DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1),
102 DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1),
103 DEF_FIXED("osc", R8A77990_CLK_OSC, CLK_EXTAL, 384, 1),
104 DEF_FIXED("r", R8A77990_CLK_R, CLK_EXTAL, 1536, 1),
105
106 DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),
107 DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
108 DEF_GEN3_PE("s3d2c", R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
109 DEF_GEN3_PE("s3d4c", R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
110
111 DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
112 DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c),
113 DEF_DIV6P1("mso", R8A77990_CLK_MSO, CLK_PLL1D2, 0x014),
114};
115
116static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
117 DEF_MOD("scif5", 202, R8A77990_CLK_S3D4C),
118 DEF_MOD("scif4", 203, R8A77990_CLK_S3D4C),
119 DEF_MOD("scif3", 204, R8A77990_CLK_S3D4C),
120 DEF_MOD("scif1", 206, R8A77990_CLK_S3D4C),
121 DEF_MOD("scif0", 207, R8A77990_CLK_S3D4C),
122 DEF_MOD("msiof3", 208, R8A77990_CLK_MSO),
123 DEF_MOD("msiof2", 209, R8A77990_CLK_MSO),
124 DEF_MOD("msiof1", 210, R8A77990_CLK_MSO),
125 DEF_MOD("msiof0", 211, R8A77990_CLK_MSO),
126 DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1),
127 DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1),
128 DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1),
129
130 DEF_MOD("cmt3", 300, R8A77990_CLK_R),
131 DEF_MOD("cmt2", 301, R8A77990_CLK_R),
132 DEF_MOD("cmt1", 302, R8A77990_CLK_R),
133 DEF_MOD("cmt0", 303, R8A77990_CLK_R),
134 DEF_MOD("scif2", 310, R8A77990_CLK_S3D4C),
135 DEF_MOD("sdif3", 311, R8A77990_CLK_SD3),
136 DEF_MOD("sdif1", 313, R8A77990_CLK_SD1),
137 DEF_MOD("sdif0", 314, R8A77990_CLK_SD0),
138 DEF_MOD("pcie0", 319, R8A77990_CLK_S3D1),
139 DEF_MOD("usb3-if0", 328, R8A77990_CLK_S3D1),
140 DEF_MOD("usb-dmac0", 330, R8A77990_CLK_S3D1),
141 DEF_MOD("usb-dmac1", 331, R8A77990_CLK_S3D1),
142
143 DEF_MOD("rwdt", 402, R8A77990_CLK_R),
144 DEF_MOD("intc-ex", 407, R8A77990_CLK_CP),
145 DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3),
146
147 DEF_MOD("audmac0", 502, R8A77990_CLK_S3D4),
148 DEF_MOD("drif7", 508, R8A77990_CLK_S3D2),
149 DEF_MOD("drif6", 509, R8A77990_CLK_S3D2),
150 DEF_MOD("drif5", 510, R8A77990_CLK_S3D2),
151 DEF_MOD("drif4", 511, R8A77990_CLK_S3D2),
152 DEF_MOD("drif3", 512, R8A77990_CLK_S3D2),
153 DEF_MOD("drif2", 513, R8A77990_CLK_S3D2),
154 DEF_MOD("drif1", 514, R8A77990_CLK_S3D2),
155 DEF_MOD("drif0", 515, R8A77990_CLK_S3D2),
156 DEF_MOD("hscif4", 516, R8A77990_CLK_S3D1C),
157 DEF_MOD("hscif3", 517, R8A77990_CLK_S3D1C),
158 DEF_MOD("hscif2", 518, R8A77990_CLK_S3D1C),
159 DEF_MOD("hscif1", 519, R8A77990_CLK_S3D1C),
160 DEF_MOD("hscif0", 520, R8A77990_CLK_S3D1C),
161 DEF_MOD("thermal", 522, R8A77990_CLK_CP),
162 DEF_MOD("pwm", 523, R8A77990_CLK_S3D4C),
163
164 DEF_MOD("fcpvd1", 602, R8A77990_CLK_S1D2),
165 DEF_MOD("fcpvd0", 603, R8A77990_CLK_S1D2),
166 DEF_MOD("fcpvb0", 607, R8A77990_CLK_S0D1),
167 DEF_MOD("fcpvi0", 611, R8A77990_CLK_S0D1),
168 DEF_MOD("fcpf0", 615, R8A77990_CLK_S0D1),
169 DEF_MOD("fcpcs", 619, R8A77990_CLK_S0D1),
170 DEF_MOD("vspd1", 622, R8A77990_CLK_S1D2),
171 DEF_MOD("vspd0", 623, R8A77990_CLK_S1D2),
172 DEF_MOD("vspb", 626, R8A77990_CLK_S0D1),
173 DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1),
174
175 DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4),
176 DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4),
177 DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
178 DEF_MOD("du1", 723, R8A77990_CLK_S2D1),
179 DEF_MOD("du0", 724, R8A77990_CLK_S2D1),
180 DEF_MOD("lvds", 727, R8A77990_CLK_S2D1),
181
182 DEF_MOD("vin5", 806, R8A77990_CLK_S1D2),
183 DEF_MOD("vin4", 807, R8A77990_CLK_S1D2),
184 DEF_MOD("etheravb", 812, R8A77990_CLK_S3D2),
185
186 DEF_MOD("gpio6", 906, R8A77990_CLK_S3D4),
187 DEF_MOD("gpio5", 907, R8A77990_CLK_S3D4),
188 DEF_MOD("gpio4", 908, R8A77990_CLK_S3D4),
189 DEF_MOD("gpio3", 909, R8A77990_CLK_S3D4),
190 DEF_MOD("gpio2", 910, R8A77990_CLK_S3D4),
191 DEF_MOD("gpio1", 911, R8A77990_CLK_S3D4),
192 DEF_MOD("gpio0", 912, R8A77990_CLK_S3D4),
193 DEF_MOD("can-fd", 914, R8A77990_CLK_S3D2),
194 DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4),
195 DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4),
196 DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2),
197 DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2),
198 DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP),
199 DEF_MOD("i2c4", 927, R8A77990_CLK_S3D2),
200 DEF_MOD("i2c3", 928, R8A77990_CLK_S3D2),
201 DEF_MOD("i2c2", 929, R8A77990_CLK_S3D2),
202 DEF_MOD("i2c1", 930, R8A77990_CLK_S3D2),
203 DEF_MOD("i2c0", 931, R8A77990_CLK_S3D2),
204
205 DEF_MOD("ssi-all", 1005, R8A77990_CLK_S3D4),
206 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
207 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
208 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
209 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
210 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
211 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
212 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
213 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
214 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
215 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
216 DEF_MOD("scu-all", 1017, R8A77990_CLK_S3D4),
217 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
218 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
219 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
220 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
221 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
222 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
223 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
224 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
225 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
226 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
227 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
228 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
229 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
230 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
231};
232
233static const unsigned int r8a77990_crit_mod_clks[] __initconst = {
234 MOD_CLK_ID(408), /* INTC-AP (GIC) */
235};
236
237/*
238 * CPG Clock Data
239 */
240
241/*
242 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
243 *--------------------------------------------------------------------
244 * 0 48 x 1 x100/4 x100/3 x100/3
245 * 1 48 x 1 x100/4 x100/3 x58/3
246 */
247#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
248
249static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
250 /* EXTAL div PLL1 mult/div PLL3 mult/div */
251 { 1, 100, 3, 100, 3, },
252 { 1, 100, 3, 58, 3, },
253};
254
255static int __init r8a77990_cpg_mssr_init(struct device *dev)
256{
257 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
258 u32 cpg_mode;
259 int error;
260
261 error = rcar_rst_read_mode_pins(&cpg_mode);
262 if (error)
263 return error;
264
265 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
266
267 return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
268}
269
270const struct cpg_mssr_info r8a77990_cpg_mssr_info __initconst = {
271 /* Core Clocks */
272 .core_clks = r8a77990_core_clks,
273 .num_core_clks = ARRAY_SIZE(r8a77990_core_clks),
274 .last_dt_core_clk = LAST_DT_CORE_CLK,
275 .num_total_core_clks = MOD_CLK_BASE,
276
277 /* Module Clocks */
278 .mod_clks = r8a77990_mod_clks,
279 .num_mod_clks = ARRAY_SIZE(r8a77990_mod_clks),
280 .num_hw_mod_clks = 12 * 32,
281
282 /* Critical Module Clocks */
283 .crit_mod_clks = r8a77990_crit_mod_clks,
284 .num_crit_mod_clks = ARRAY_SIZE(r8a77990_crit_mod_clks),
285
286 /* Callbacks */
287 .init = r8a77990_cpg_mssr_init,
288 .cpg_clk_register = rcar_gen3_cpg_clk_register,
289};
diff --git a/drivers/clk/renesas/rcar-gen2-cpg.c b/drivers/clk/renesas/rcar-gen2-cpg.c
index feb14579a71b..daf88bc2cdae 100644
--- a/drivers/clk/renesas/rcar-gen2-cpg.c
+++ b/drivers/clk/renesas/rcar-gen2-cpg.c
@@ -16,6 +16,7 @@
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/slab.h> 18#include <linux/slab.h>
19#include <linux/sys_soc.h>
19 20
20#include "renesas-cpg-mssr.h" 21#include "renesas-cpg-mssr.h"
21#include "rcar-gen2-cpg.h" 22#include "rcar-gen2-cpg.h"
@@ -260,6 +261,17 @@ static const struct clk_div_table cpg_sd01_div_table[] = {
260static const struct rcar_gen2_cpg_pll_config *cpg_pll_config __initdata; 261static const struct rcar_gen2_cpg_pll_config *cpg_pll_config __initdata;
261static unsigned int cpg_pll0_div __initdata; 262static unsigned int cpg_pll0_div __initdata;
262static u32 cpg_mode __initdata; 263static u32 cpg_mode __initdata;
264static u32 cpg_quirks __initdata;
265
266#define SD_SKIP_FIRST BIT(0) /* Skip first clock in SD table */
267
268static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
269 {
270 .soc_id = "r8a77470",
271 .data = (void *)SD_SKIP_FIRST,
272 },
273 { /* sentinel */ }
274};
263 275
264struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev, 276struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
265 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 277 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
@@ -327,11 +339,17 @@ struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
327 339
328 case CLK_TYPE_GEN2_SD0: 340 case CLK_TYPE_GEN2_SD0:
329 table = cpg_sd01_div_table; 341 table = cpg_sd01_div_table;
342 if (cpg_quirks & SD_SKIP_FIRST)
343 table++;
344
330 shift = 4; 345 shift = 4;
331 break; 346 break;
332 347
333 case CLK_TYPE_GEN2_SD1: 348 case CLK_TYPE_GEN2_SD1:
334 table = cpg_sd01_div_table; 349 table = cpg_sd01_div_table;
350 if (cpg_quirks & SD_SKIP_FIRST)
351 table++;
352
335 shift = 0; 353 shift = 0;
336 break; 354 break;
337 355
@@ -360,9 +378,15 @@ struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
360int __init rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config, 378int __init rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
361 unsigned int pll0_div, u32 mode) 379 unsigned int pll0_div, u32 mode)
362{ 380{
381 const struct soc_device_attribute *attr;
382
363 cpg_pll_config = config; 383 cpg_pll_config = config;
364 cpg_pll0_div = pll0_div; 384 cpg_pll0_div = pll0_div;
365 cpg_mode = mode; 385 cpg_mode = mode;
386 attr = soc_device_match(cpg_quirks_match);
387 if (attr)
388 cpg_quirks = (uintptr_t)attr->data;
389 pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
366 390
367 spin_lock_init(&cpg_lock); 391 spin_lock_init(&cpg_lock);
368 392
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 4e88e980fb76..49e510691eee 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -652,6 +652,12 @@ static const struct of_device_id cpg_mssr_match[] = {
652 .data = &r8a7745_cpg_mssr_info, 652 .data = &r8a7745_cpg_mssr_info,
653 }, 653 },
654#endif 654#endif
655#ifdef CONFIG_CLK_R8A77470
656 {
657 .compatible = "renesas,r8a77470-cpg-mssr",
658 .data = &r8a77470_cpg_mssr_info,
659 },
660#endif
655#ifdef CONFIG_CLK_R8A7790 661#ifdef CONFIG_CLK_R8A7790
656 { 662 {
657 .compatible = "renesas,r8a7790-cpg-mssr", 663 .compatible = "renesas,r8a7790-cpg-mssr",
@@ -711,6 +717,12 @@ static const struct of_device_id cpg_mssr_match[] = {
711 .data = &r8a77980_cpg_mssr_info, 717 .data = &r8a77980_cpg_mssr_info,
712 }, 718 },
713#endif 719#endif
720#ifdef CONFIG_CLK_R8A77990
721 {
722 .compatible = "renesas,r8a77990-cpg-mssr",
723 .data = &r8a77990_cpg_mssr_info,
724 },
725#endif
714#ifdef CONFIG_CLK_R8A77995 726#ifdef CONFIG_CLK_R8A77995
715 { 727 {
716 .compatible = "renesas,r8a77995-cpg-mssr", 728 .compatible = "renesas,r8a77995-cpg-mssr",
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 97ccb093c10f..642f720b9b05 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -133,6 +133,7 @@ struct cpg_mssr_info {
133 133
134extern const struct cpg_mssr_info r8a7743_cpg_mssr_info; 134extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
135extern const struct cpg_mssr_info r8a7745_cpg_mssr_info; 135extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
136extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
136extern const struct cpg_mssr_info r8a7790_cpg_mssr_info; 137extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
137extern const struct cpg_mssr_info r8a7791_cpg_mssr_info; 138extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
138extern const struct cpg_mssr_info r8a7792_cpg_mssr_info; 139extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
@@ -142,6 +143,7 @@ extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
142extern const struct cpg_mssr_info r8a77965_cpg_mssr_info; 143extern const struct cpg_mssr_info r8a77965_cpg_mssr_info;
143extern const struct cpg_mssr_info r8a77970_cpg_mssr_info; 144extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
144extern const struct cpg_mssr_info r8a77980_cpg_mssr_info; 145extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
146extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
145extern const struct cpg_mssr_info r8a77995_cpg_mssr_info; 147extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
146 148
147 149
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 59b8d320960a..98e7b9429b83 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -3,7 +3,6 @@
3# Rockchip Clock specific Makefile 3# Rockchip Clock specific Makefile
4# 4#
5 5
6obj-y += clk-rockchip.o
7obj-y += clk.o 6obj-y += clk.o
8obj-y += clk-pll.o 7obj-y += clk-pll.o
9obj-y += clk-cpu.o 8obj-y += clk-cpu.o
diff --git a/drivers/clk/rockchip/clk-rockchip.c b/drivers/clk/rockchip/clk-rockchip.c
deleted file mode 100644
index 2c9bb81144c9..000000000000
--- a/drivers/clk/rockchip/clk-rockchip.c
+++ /dev/null
@@ -1,98 +0,0 @@
1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk-provider.h>
17#include <linux/clkdev.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20
21static DEFINE_SPINLOCK(clk_lock);
22
23/*
24 * Gate clocks
25 */
26
27static void __init rk2928_gate_clk_init(struct device_node *node)
28{
29 struct clk_onecell_data *clk_data;
30 const char *clk_parent;
31 const char *clk_name;
32 void __iomem *reg;
33 void __iomem *reg_idx;
34 int flags;
35 int qty;
36 int reg_bit;
37 int clkflags = CLK_SET_RATE_PARENT;
38 int i;
39
40 qty = of_property_count_strings(node, "clock-output-names");
41 if (qty < 0) {
42 pr_err("%s: error in clock-output-names %d\n", __func__, qty);
43 return;
44 }
45
46 if (qty == 0) {
47 pr_info("%s: nothing to do\n", __func__);
48 return;
49 }
50
51 reg = of_iomap(node, 0);
52 if (!reg)
53 return;
54
55 clk_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
56 if (!clk_data) {
57 iounmap(reg);
58 return;
59 }
60
61 clk_data->clks = kzalloc(qty * sizeof(struct clk *), GFP_KERNEL);
62 if (!clk_data->clks) {
63 kfree(clk_data);
64 iounmap(reg);
65 return;
66 }
67
68 flags = CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE;
69
70 for (i = 0; i < qty; i++) {
71 of_property_read_string_index(node, "clock-output-names",
72 i, &clk_name);
73
74 /* ignore empty slots */
75 if (!strcmp("reserved", clk_name))
76 continue;
77
78 clk_parent = of_clk_get_parent_name(node, i);
79
80 /* keep all gates untouched for now */
81 clkflags |= CLK_IGNORE_UNUSED;
82
83 reg_idx = reg + (4 * (i / 16));
84 reg_bit = (i % 16);
85
86 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
87 clk_parent, clkflags,
88 reg_idx, reg_bit,
89 flags,
90 &clk_lock);
91 WARN_ON(IS_ERR(clk_data->clks[i]));
92 }
93
94 clk_data->clk_num = qty;
95
96 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
97}
98CLK_OF_DECLARE(rk2928_gate, "rockchip,rk2928-gate-clk", rk2928_gate_clk_init);
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 3cd8ad59e0b7..326b3fa44f5d 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -274,18 +274,10 @@ static struct clk *rockchip_clk_register_frac_branch(
274 struct clk_mux *frac_mux = &frac->mux; 274 struct clk_mux *frac_mux = &frac->mux;
275 struct clk_init_data init; 275 struct clk_init_data init;
276 struct clk *mux_clk; 276 struct clk *mux_clk;
277 int i, ret; 277 int ret;
278
279 frac->mux_frac_idx = -1;
280 for (i = 0; i < child->num_parents; i++) {
281 if (!strcmp(name, child->parent_names[i])) {
282 pr_debug("%s: found fractional parent in mux at pos %d\n",
283 __func__, i);
284 frac->mux_frac_idx = i;
285 break;
286 }
287 }
288 278
279 frac->mux_frac_idx = match_string(child->parent_names,
280 child->num_parents, name);
289 frac->mux_ops = &clk_mux_ops; 281 frac->mux_ops = &clk_mux_ops;
290 frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb; 282 frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb;
291 283
@@ -312,6 +304,8 @@ static struct clk *rockchip_clk_register_frac_branch(
312 304
313 /* notifier on the fraction divider to catch rate changes */ 305 /* notifier on the fraction divider to catch rate changes */
314 if (frac->mux_frac_idx >= 0) { 306 if (frac->mux_frac_idx >= 0) {
307 pr_debug("%s: found fractional parent in mux at pos %d\n",
308 __func__, frac->mux_frac_idx);
315 ret = clk_notifier_register(clk, &frac->clk_nb); 309 ret = clk_notifier_register(clk, &frac->clk_nb);
316 if (ret) 310 if (ret)
317 pr_err("%s: failed to register clock notifier for %s\n", 311 pr_err("%s: failed to register clock notifier for %s\n",
diff --git a/drivers/clk/samsung/clk-s3c2410-dclk.c b/drivers/clk/samsung/clk-s3c2410-dclk.c
index 077df3e539a7..f41d89cef0f1 100644
--- a/drivers/clk/samsung/clk-s3c2410-dclk.c
+++ b/drivers/clk/samsung/clk-s3c2410-dclk.c
@@ -219,8 +219,7 @@ static int s3c24xx_dclk1_div_notify(struct notifier_block *nb,
219#ifdef CONFIG_PM_SLEEP 219#ifdef CONFIG_PM_SLEEP
220static int s3c24xx_dclk_suspend(struct device *dev) 220static int s3c24xx_dclk_suspend(struct device *dev)
221{ 221{
222 struct platform_device *pdev = to_platform_device(dev); 222 struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);
223 struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
224 223
225 s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base); 224 s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base);
226 return 0; 225 return 0;
@@ -228,8 +227,7 @@ static int s3c24xx_dclk_suspend(struct device *dev)
228 227
229static int s3c24xx_dclk_resume(struct device *dev) 228static int s3c24xx_dclk_resume(struct device *dev)
230{ 229{
231 struct platform_device *pdev = to_platform_device(dev); 230 struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);
232 struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
233 231
234 writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base); 232 writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base);
235 return 0; 233 return 0;
diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
index 3a11c382a663..72714633e39c 100644
--- a/drivers/clk/socfpga/clk-s10.c
+++ b/drivers/clk/socfpga/clk-s10.c
@@ -260,46 +260,45 @@ static int s10_clk_register_pll(const struct stratix10_pll_clock *clks,
260 return 0; 260 return 0;
261} 261}
262 262
263static struct stratix10_clock_data *__socfpga_s10_clk_init(struct device_node *np, 263static struct stratix10_clock_data *__socfpga_s10_clk_init(struct platform_device *pdev,
264 int nr_clks) 264 int nr_clks)
265{ 265{
266 struct device_node *np = pdev->dev.of_node;
267 struct device *dev = &pdev->dev;
266 struct stratix10_clock_data *clk_data; 268 struct stratix10_clock_data *clk_data;
267 struct clk **clk_table; 269 struct clk **clk_table;
270 struct resource *res;
268 void __iomem *base; 271 void __iomem *base;
269 272
270 base = of_iomap(np, 0); 273 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
271 if (!base) { 274 base = devm_ioremap_resource(dev, res);
275 if (IS_ERR(base)) {
272 pr_err("%s: failed to map clock registers\n", __func__); 276 pr_err("%s: failed to map clock registers\n", __func__);
273 goto err; 277 return ERR_CAST(base);
274 } 278 }
275 279
276 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); 280 clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
277 if (!clk_data) 281 if (!clk_data)
278 goto err; 282 return ERR_PTR(-ENOMEM);
279 283
280 clk_data->base = base; 284 clk_data->base = base;
281 clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL); 285 clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL);
282 if (!clk_table) 286 if (!clk_table)
283 goto err_data; 287 return ERR_PTR(-ENOMEM);
284 288
285 clk_data->clk_data.clks = clk_table; 289 clk_data->clk_data.clks = clk_table;
286 clk_data->clk_data.clk_num = nr_clks; 290 clk_data->clk_data.clk_num = nr_clks;
287 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data); 291 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
288 return clk_data; 292 return clk_data;
289
290err_data:
291 kfree(clk_data);
292err:
293 return NULL;
294} 293}
295 294
296static int s10_clkmgr_init(struct device_node *np) 295static int s10_clkmgr_init(struct platform_device *pdev)
297{ 296{
298 struct stratix10_clock_data *clk_data; 297 struct stratix10_clock_data *clk_data;
299 298
300 clk_data = __socfpga_s10_clk_init(np, STRATIX10_NUM_CLKS); 299 clk_data = __socfpga_s10_clk_init(pdev, STRATIX10_NUM_CLKS);
301 if (!clk_data) 300 if (IS_ERR(clk_data))
302 return -ENOMEM; 301 return PTR_ERR(clk_data);
303 302
304 s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data); 303 s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data);
305 304
@@ -317,11 +316,7 @@ static int s10_clkmgr_init(struct device_node *np)
317 316
318static int s10_clkmgr_probe(struct platform_device *pdev) 317static int s10_clkmgr_probe(struct platform_device *pdev)
319{ 318{
320 struct device_node *np = pdev->dev.of_node; 319 return s10_clkmgr_init(pdev);
321
322 s10_clkmgr_init(np);
323
324 return 0;
325} 320}
326 321
327static const struct of_device_id stratix10_clkmgr_match_table[] = { 322static const struct of_device_id stratix10_clkmgr_match_table[] = {
@@ -334,6 +329,7 @@ static struct platform_driver stratix10_clkmgr_driver = {
334 .probe = s10_clkmgr_probe, 329 .probe = s10_clkmgr_probe,
335 .driver = { 330 .driver = {
336 .name = "stratix10-clkmgr", 331 .name = "stratix10-clkmgr",
332 .suppress_bind_attrs = true,
337 .of_match_table = stratix10_clkmgr_match_table, 333 .of_match_table = stratix10_clkmgr_match_table,
338 }, 334 },
339}; 335};
diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c
index f911d9f77763..47810be7f15c 100644
--- a/drivers/clk/spear/spear6xx_clock.c
+++ b/drivers/clk/spear/spear6xx_clock.c
@@ -147,7 +147,7 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
147 147
148 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1, 148 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
149 1); 149 1);
150 clk_register_clkdev(clk, NULL, "wdt"); 150 clk_register_clkdev(clk, NULL, "fc880000.wdt");
151 151
152 /* clock derived from pll1 clk */ 152 /* clock derived from pll1 clk */
153 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 153 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 79dfd296c3d1..826674d090fd 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -16,6 +16,11 @@ config SUN50I_H6_CCU
16 default ARM64 && ARCH_SUNXI 16 default ARM64 && ARCH_SUNXI
17 depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST 17 depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
18 18
19config SUN50I_H6_R_CCU
20 bool "Support for the Allwinner H6 PRCM CCU"
21 default ARM64 && ARCH_SUNXI
22 depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
23
19config SUN4I_A10_CCU 24config SUN4I_A10_CCU
20 bool "Support for the Allwinner A10/A20 CCU" 25 bool "Support for the Allwinner A10/A20 CCU"
21 default MACH_SUN4I 26 default MACH_SUN4I
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 128a40ee5c5e..acaa14cfa25c 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -23,6 +23,7 @@ lib-$(CONFIG_SUNXI_CCU) += ccu_mp.o
23# SoC support 23# SoC support
24obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o 24obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
25obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o 25obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o
26obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
26obj-$(CONFIG_SUN4I_A10_CCU) += ccu-sun4i-a10.o 27obj-$(CONFIG_SUN4I_A10_CCU) += ccu-sun4i-a10.o
27obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o 28obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o
28obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o 29obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
new file mode 100644
index 000000000000..27554eaf6929
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -0,0 +1,207 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
4 */
5
6#include <linux/clk-provider.h>
7#include <linux/of_address.h>
8#include <linux/platform_device.h>
9
10#include "ccu_common.h"
11#include "ccu_reset.h"
12
13#include "ccu_div.h"
14#include "ccu_gate.h"
15#include "ccu_mp.h"
16#include "ccu_nm.h"
17
18#include "ccu-sun50i-h6-r.h"
19
20/*
21 * Information about AR100 and AHB/APB clocks in R_CCU are gathered from
22 * clock definitions in the BSP source code.
23 */
24
25static const char * const ar100_r_apb2_parents[] = { "osc24M", "osc32k",
26 "pll-periph0", "iosc" };
27static const struct ccu_mux_var_prediv ar100_r_apb2_predivs[] = {
28 { .index = 2, .shift = 0, .width = 5 },
29};
30
31static struct ccu_div ar100_clk = {
32 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
33
34 .mux = {
35 .shift = 24,
36 .width = 2,
37
38 .var_predivs = ar100_r_apb2_predivs,
39 .n_var_predivs = ARRAY_SIZE(ar100_r_apb2_predivs),
40 },
41
42 .common = {
43 .reg = 0x000,
44 .features = CCU_FEATURE_VARIABLE_PREDIV,
45 .hw.init = CLK_HW_INIT_PARENTS("ar100",
46 ar100_r_apb2_parents,
47 &ccu_div_ops,
48 0),
49 },
50};
51
52static CLK_FIXED_FACTOR(r_ahb_clk, "r-ahb", "ar100", 1, 1, 0);
53
54static struct ccu_div r_apb1_clk = {
55 .div = _SUNXI_CCU_DIV(0, 2),
56
57 .common = {
58 .reg = 0x00c,
59 .hw.init = CLK_HW_INIT("r-apb1",
60 "r-ahb",
61 &ccu_div_ops,
62 0),
63 },
64};
65
66static struct ccu_div r_apb2_clk = {
67 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
68
69 .mux = {
70 .shift = 24,
71 .width = 2,
72
73 .var_predivs = ar100_r_apb2_predivs,
74 .n_var_predivs = ARRAY_SIZE(ar100_r_apb2_predivs),
75 },
76
77 .common = {
78 .reg = 0x010,
79 .features = CCU_FEATURE_VARIABLE_PREDIV,
80 .hw.init = CLK_HW_INIT_PARENTS("r-apb2",
81 ar100_r_apb2_parents,
82 &ccu_div_ops,
83 0),
84 },
85};
86
87/*
88 * Information about the gate/resets are gathered from the clock header file
89 * in the BSP source code, although most of them are unused. The existence
90 * of the hardware block is verified with "3.1 Memory Mapping" chapter in
91 * "Allwinner H6 V200 User Manual V1.1"; and the parent APB buses are verified
92 * with "3.3.2.1 System Bus Tree" chapter inthe same document.
93 */
94static SUNXI_CCU_GATE(r_apb1_timer_clk, "r-apb1-timer", "r-apb1",
95 0x11c, BIT(0), 0);
96static SUNXI_CCU_GATE(r_apb1_twd_clk, "r-apb1-twd", "r-apb1",
97 0x12c, BIT(0), 0);
98static SUNXI_CCU_GATE(r_apb1_pwm_clk, "r-apb1-pwm", "r-apb1",
99 0x13c, BIT(0), 0);
100static SUNXI_CCU_GATE(r_apb2_uart_clk, "r-apb2-uart", "r-apb2",
101 0x18c, BIT(0), 0);
102static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
103 0x19c, BIT(0), 0);
104static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
105 0x1cc, BIT(0), 0);
106static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
107 0x1cc, BIT(0), 0);
108
109/* Information of IR(RX) mod clock is gathered from BSP source code */
110static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
111static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
112 r_mod0_default_parents, 0x1c0,
113 0, 5, /* M */
114 8, 2, /* P */
115 24, 1, /* mux */
116 BIT(31), /* gate */
117 0);
118
119/*
120 * BSP didn't use the 1-wire function at all now, and the information about
121 * this mod clock is guessed from the IR mod clock above. The existence of
122 * this mod clock is proven by BSP clock header, and the dividers are verified
123 * by contents in the 1-wire related chapter of the User Manual.
124 */
125
126static SUNXI_CCU_MP_WITH_MUX_GATE(w1_clk, "w1",
127 r_mod0_default_parents, 0x1e0,
128 0, 5, /* M */
129 8, 2, /* P */
130 24, 1, /* mux */
131 BIT(31), /* gate */
132 0);
133
134static struct ccu_common *sun50i_h6_r_ccu_clks[] = {
135 &ar100_clk.common,
136 &r_apb1_clk.common,
137 &r_apb2_clk.common,
138 &r_apb1_timer_clk.common,
139 &r_apb1_twd_clk.common,
140 &r_apb1_pwm_clk.common,
141 &r_apb2_uart_clk.common,
142 &r_apb2_i2c_clk.common,
143 &r_apb1_ir_clk.common,
144 &r_apb1_w1_clk.common,
145 &ir_clk.common,
146 &w1_clk.common,
147};
148
149static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
150 .hws = {
151 [CLK_AR100] = &ar100_clk.common.hw,
152 [CLK_R_AHB] = &r_ahb_clk.hw,
153 [CLK_R_APB1] = &r_apb1_clk.common.hw,
154 [CLK_R_APB2] = &r_apb2_clk.common.hw,
155 [CLK_R_APB1_TIMER] = &r_apb1_timer_clk.common.hw,
156 [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw,
157 [CLK_R_APB1_PWM] = &r_apb1_pwm_clk.common.hw,
158 [CLK_R_APB2_UART] = &r_apb2_uart_clk.common.hw,
159 [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw,
160 [CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw,
161 [CLK_R_APB1_W1] = &r_apb1_w1_clk.common.hw,
162 [CLK_IR] = &ir_clk.common.hw,
163 [CLK_W1] = &w1_clk.common.hw,
164 },
165 .num = CLK_NUMBER,
166};
167
168static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
169 [RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
170 [RST_R_APB1_TWD] = { 0x12c, BIT(16) },
171 [RST_R_APB1_PWM] = { 0x13c, BIT(16) },
172 [RST_R_APB2_UART] = { 0x18c, BIT(16) },
173 [RST_R_APB2_I2C] = { 0x19c, BIT(16) },
174 [RST_R_APB1_IR] = { 0x1cc, BIT(16) },
175 [RST_R_APB1_W1] = { 0x1ec, BIT(16) },
176};
177
178static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
179 .ccu_clks = sun50i_h6_r_ccu_clks,
180 .num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks),
181
182 .hw_clks = &sun50i_h6_r_hw_clks,
183
184 .resets = sun50i_h6_r_ccu_resets,
185 .num_resets = ARRAY_SIZE(sun50i_h6_r_ccu_resets),
186};
187
188static void __init sunxi_r_ccu_init(struct device_node *node,
189 const struct sunxi_ccu_desc *desc)
190{
191 void __iomem *reg;
192
193 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
194 if (IS_ERR(reg)) {
195 pr_err("%pOF: Could not map the clock registers\n", node);
196 return;
197 }
198
199 sunxi_ccu_probe(node, reg, desc);
200}
201
202static void __init sun50i_h6_r_ccu_setup(struct device_node *node)
203{
204 sunxi_r_ccu_init(node, &sun50i_h6_r_ccu_desc);
205}
206CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu",
207 sun50i_h6_r_ccu_setup);
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
new file mode 100644
index 000000000000..782117dc0b28
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
@@ -0,0 +1,19 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.xyz>
4 */
5
6#ifndef _CCU_SUN50I_H6_R_H
7#define _CCU_SUN50I_H6_R_H
8
9#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
10#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
11
12/* AHB/APB bus clocks are not exported except APB1 for R_PIO */
13#define CLK_R_AHB 1
14
15#define CLK_R_APB2 3
16
17#define CLK_NUMBER (CLK_W1 + 1)
18
19#endif /* _CCU_SUN50I_H6_R_H */
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index 933f2e68f42a..65ba6455feb7 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -12,7 +12,8 @@
12 */ 12 */
13 13
14#include <linux/clk-provider.h> 14#include <linux/clk-provider.h>
15#include <linux/of_address.h> 15#include <linux/platform_device.h>
16#include <linux/regmap.h>
16 17
17#include "ccu_common.h" 18#include "ccu_common.h"
18#include "ccu_reset.h" 19#include "ccu_reset.h"
@@ -1250,17 +1251,45 @@ static struct ccu_mux_nb sun8i_r40_cpu_nb = {
1250 .bypass_index = 1, /* index of 24 MHz oscillator */ 1251 .bypass_index = 1, /* index of 24 MHz oscillator */
1251}; 1252};
1252 1253
1253static void __init sun8i_r40_ccu_setup(struct device_node *node) 1254/*
1255 * Add a regmap for the GMAC driver (dwmac-sun8i) to access the
1256 * GMAC configuration register.
1257 * Only this register is allowed to be written, in order to
1258 * prevent overriding critical clock configuration.
1259 */
1260
1261#define SUN8I_R40_GMAC_CFG_REG 0x164
1262static bool sun8i_r40_ccu_regmap_accessible_reg(struct device *dev,
1263 unsigned int reg)
1264{
1265 if (reg == SUN8I_R40_GMAC_CFG_REG)
1266 return true;
1267 return false;
1268}
1269
1270static struct regmap_config sun8i_r40_ccu_regmap_config = {
1271 .reg_bits = 32,
1272 .val_bits = 32,
1273 .reg_stride = 4,
1274 .max_register = 0x320, /* PLL_LOCK_CTRL_REG */
1275
1276 /* other devices have no business accessing other registers */
1277 .readable_reg = sun8i_r40_ccu_regmap_accessible_reg,
1278 .writeable_reg = sun8i_r40_ccu_regmap_accessible_reg,
1279};
1280
1281static int sun8i_r40_ccu_probe(struct platform_device *pdev)
1254{ 1282{
1283 struct resource *res;
1284 struct regmap *regmap;
1255 void __iomem *reg; 1285 void __iomem *reg;
1256 u32 val; 1286 u32 val;
1287 int ret;
1257 1288
1258 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 1289 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1259 if (IS_ERR(reg)) { 1290 reg = devm_ioremap_resource(&pdev->dev, res);
1260 pr_err("%s: Could not map the clock registers\n", 1291 if (IS_ERR(reg))
1261 of_node_full_name(node)); 1292 return PTR_ERR(reg);
1262 return;
1263 }
1264 1293
1265 /* Force the PLL-Audio-1x divider to 4 */ 1294 /* Force the PLL-Audio-1x divider to 4 */
1266 val = readl(reg + SUN8I_R40_PLL_AUDIO_REG); 1295 val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
@@ -1277,7 +1306,14 @@ static void __init sun8i_r40_ccu_setup(struct device_node *node)
1277 val &= ~GENMASK(25, 20); 1306 val &= ~GENMASK(25, 20);
1278 writel(val, reg + SUN8I_R40_USB_CLK_REG); 1307 writel(val, reg + SUN8I_R40_USB_CLK_REG);
1279 1308
1280 sunxi_ccu_probe(node, reg, &sun8i_r40_ccu_desc); 1309 regmap = devm_regmap_init_mmio(&pdev->dev, reg,
1310 &sun8i_r40_ccu_regmap_config);
1311 if (IS_ERR(regmap))
1312 return PTR_ERR(regmap);
1313
1314 ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8i_r40_ccu_desc);
1315 if (ret)
1316 return ret;
1281 1317
1282 /* Gate then ungate PLL CPU after any rate changes */ 1318 /* Gate then ungate PLL CPU after any rate changes */
1283 ccu_pll_notifier_register(&sun8i_r40_pll_cpu_nb); 1319 ccu_pll_notifier_register(&sun8i_r40_pll_cpu_nb);
@@ -1285,6 +1321,20 @@ static void __init sun8i_r40_ccu_setup(struct device_node *node)
1285 /* Reparent CPU during PLL CPU rate changes */ 1321 /* Reparent CPU during PLL CPU rate changes */
1286 ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk, 1322 ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
1287 &sun8i_r40_cpu_nb); 1323 &sun8i_r40_cpu_nb);
1324
1325 return 0;
1288} 1326}
1289CLK_OF_DECLARE(sun8i_r40_ccu, "allwinner,sun8i-r40-ccu", 1327
1290 sun8i_r40_ccu_setup); 1328static const struct of_device_id sun8i_r40_ccu_ids[] = {
1329 { .compatible = "allwinner,sun8i-r40-ccu" },
1330 { }
1331};
1332
1333static struct platform_driver sun8i_r40_ccu_driver = {
1334 .probe = sun8i_r40_ccu_probe,
1335 .driver = {
1336 .name = "sun8i-r40-ccu",
1337 .of_match_table = sun8i_r40_ccu_ids,
1338 },
1339};
1340builtin_platform_driver(sun8i_r40_ccu_driver);
diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
index 0a7deee74eea..48ee43734e05 100644
--- a/drivers/clk/tegra/clk-dfll.c
+++ b/drivers/clk/tegra/clk-dfll.c
@@ -1196,42 +1196,24 @@ static const struct file_operations attr_registers_fops = {
1196 .release = single_release, 1196 .release = single_release,
1197}; 1197};
1198 1198
1199static int dfll_debug_init(struct tegra_dfll *td) 1199static void dfll_debug_init(struct tegra_dfll *td)
1200{ 1200{
1201 int ret; 1201 struct dentry *root;
1202 1202
1203 if (!td || (td->mode == DFLL_UNINITIALIZED)) 1203 if (!td || (td->mode == DFLL_UNINITIALIZED))
1204 return 0; 1204 return;
1205
1206 td->debugfs_dir = debugfs_create_dir("tegra_dfll_fcpu", NULL);
1207 if (!td->debugfs_dir)
1208 return -ENOMEM;
1209
1210 ret = -ENOMEM;
1211
1212 if (!debugfs_create_file("enable", S_IRUGO | S_IWUSR,
1213 td->debugfs_dir, td, &enable_fops))
1214 goto err_out;
1215
1216 if (!debugfs_create_file("lock", S_IRUGO,
1217 td->debugfs_dir, td, &lock_fops))
1218 goto err_out;
1219 1205
1220 if (!debugfs_create_file("rate", S_IRUGO, 1206 root = debugfs_create_dir("tegra_dfll_fcpu", NULL);
1221 td->debugfs_dir, td, &rate_fops)) 1207 td->debugfs_dir = root;
1222 goto err_out;
1223 1208
1224 if (!debugfs_create_file("registers", S_IRUGO, 1209 debugfs_create_file("enable", S_IRUGO | S_IWUSR, root, td, &enable_fops);
1225 td->debugfs_dir, td, &attr_registers_fops)) 1210 debugfs_create_file("lock", S_IRUGO, root, td, &lock_fops);
1226 goto err_out; 1211 debugfs_create_file("rate", S_IRUGO, root, td, &rate_fops);
1227 1212 debugfs_create_file("registers", S_IRUGO, root, td, &attr_registers_fops);
1228 return 0;
1229
1230err_out:
1231 debugfs_remove_recursive(td->debugfs_dir);
1232 return ret;
1233} 1213}
1234 1214
1215#else
1216static void inline dfll_debug_init(struct tegra_dfll *td) { }
1235#endif /* CONFIG_DEBUG_FS */ 1217#endif /* CONFIG_DEBUG_FS */
1236 1218
1237/* 1219/*
@@ -1715,9 +1697,7 @@ int tegra_dfll_register(struct platform_device *pdev,
1715 return ret; 1697 return ret;
1716 } 1698 }
1717 1699
1718#ifdef CONFIG_DEBUG_FS
1719 dfll_debug_init(td); 1700 dfll_debug_init(td);
1720#endif
1721 1701
1722 return 0; 1702 return 0;
1723} 1703}
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 5d5a22d529f5..1824f014202b 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1367,7 +1367,7 @@ static void __init tegra114_clock_init(struct device_node *np)
1367 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks, 1367 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
1368 &pll_x_params); 1368 &pll_x_params);
1369 1369
1370 tegra_add_of_provider(np); 1370 tegra_add_of_provider(np, of_clk_src_onecell_get);
1371 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 1371 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1372 1372
1373 tegra_clk_apply_init_table = tegra114_clock_apply_init_table; 1373 tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 50088e976611..0c69c7970950 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1479,7 +1479,7 @@ static void __init tegra124_132_clock_init_post(struct device_node *np)
1479 &pll_x_params); 1479 &pll_x_params);
1480 tegra_init_special_resets(1, tegra124_reset_assert, 1480 tegra_init_special_resets(1, tegra124_reset_assert,
1481 tegra124_reset_deassert); 1481 tegra124_reset_deassert);
1482 tegra_add_of_provider(np); 1482 tegra_add_of_provider(np, of_clk_src_onecell_get);
1483 1483
1484 clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np, 1484 clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np,
1485 &emc_lock); 1485 &emc_lock);
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 0ee56dd04cec..cc857d4d4a86 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -26,6 +26,8 @@
26#include "clk.h" 26#include "clk.h"
27#include "clk-id.h" 27#include "clk-id.h"
28 28
29#define MISC_CLK_ENB 0x48
30
29#define OSC_CTRL 0x50 31#define OSC_CTRL 0x50
30#define OSC_CTRL_OSC_FREQ_MASK (3<<30) 32#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
31#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30) 33#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
@@ -831,15 +833,25 @@ static void __init tegra20_periph_clk_init(void)
831 periph_clk_enb_refcnt); 833 periph_clk_enb_refcnt);
832 clks[TEGRA20_CLK_PEX] = clk; 834 clks[TEGRA20_CLK_PEX] = clk;
833 835
836 /* dev1 OSC divider */
837 clk_register_divider(NULL, "dev1_osc_div", "clk_m",
838 0, clk_base + MISC_CLK_ENB, 22, 2,
839 CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY,
840 NULL);
841
842 /* dev2 OSC divider */
843 clk_register_divider(NULL, "dev2_osc_div", "clk_m",
844 0, clk_base + MISC_CLK_ENB, 20, 2,
845 CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY,
846 NULL);
847
834 /* cdev1 */ 848 /* cdev1 */
835 clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, 0, 26000000); 849 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_mux", 0,
836 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0,
837 clk_base, 0, 94, periph_clk_enb_refcnt); 850 clk_base, 0, 94, periph_clk_enb_refcnt);
838 clks[TEGRA20_CLK_CDEV1] = clk; 851 clks[TEGRA20_CLK_CDEV1] = clk;
839 852
840 /* cdev2 */ 853 /* cdev2 */
841 clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, 0, 26000000); 854 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_mux", 0,
842 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0,
843 clk_base, 0, 93, periph_clk_enb_refcnt); 855 clk_base, 0, 93, periph_clk_enb_refcnt);
844 clks[TEGRA20_CLK_CDEV2] = clk; 856 clks[TEGRA20_CLK_CDEV2] = clk;
845 857
@@ -1077,6 +1089,36 @@ static const struct of_device_id pmc_match[] __initconst = {
1077 { }, 1089 { },
1078}; 1090};
1079 1091
1092static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec,
1093 void *data)
1094{
1095 struct clk_hw *parent_hw;
1096 struct clk_hw *hw;
1097 struct clk *clk;
1098
1099 clk = of_clk_src_onecell_get(clkspec, data);
1100 if (IS_ERR(clk))
1101 return clk;
1102
1103 /*
1104 * Tegra20 CDEV1 and CDEV2 clocks are a bit special case, their parent
1105 * clock is created by the pinctrl driver. It is possible for clk user
1106 * to request these clocks before pinctrl driver got probed and hence
1107 * user will get an orphaned clock. That might be undesirable because
1108 * user may expect parent clock to be enabled by the child.
1109 */
1110 if (clkspec->args[0] == TEGRA20_CLK_CDEV1 ||
1111 clkspec->args[0] == TEGRA20_CLK_CDEV2) {
1112 hw = __clk_get_hw(clk);
1113
1114 parent_hw = clk_hw_get_parent(hw);
1115 if (!parent_hw)
1116 return ERR_PTR(-EPROBE_DEFER);
1117 }
1118
1119 return clk;
1120}
1121
1080static void __init tegra20_clock_init(struct device_node *np) 1122static void __init tegra20_clock_init(struct device_node *np)
1081{ 1123{
1082 struct device_node *node; 1124 struct device_node *node;
@@ -1115,7 +1157,7 @@ static void __init tegra20_clock_init(struct device_node *np)
1115 1157
1116 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX); 1158 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX);
1117 1159
1118 tegra_add_of_provider(np); 1160 tegra_add_of_provider(np, tegra20_clk_src_onecell_get);
1119 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 1161 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1120 1162
1121 tegra_clk_apply_init_table = tegra20_clock_apply_init_table; 1163 tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 9fb5d51ccce4..5435d01c636a 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -3567,7 +3567,7 @@ static void __init tegra210_clock_init(struct device_node *np)
3567 tegra_init_special_resets(2, tegra210_reset_assert, 3567 tegra_init_special_resets(2, tegra210_reset_assert,
3568 tegra210_reset_deassert); 3568 tegra210_reset_deassert);
3569 3569
3570 tegra_add_of_provider(np); 3570 tegra_add_of_provider(np, of_clk_src_onecell_get);
3571 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 3571 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
3572 3572
3573 tegra210_mbist_clk_init(); 3573 tegra210_mbist_clk_init();
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index b316dfb6f6c7..acfe661b2ae7 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1349,7 +1349,7 @@ static void __init tegra30_clock_init(struct device_node *np)
1349 1349
1350 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX); 1350 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
1351 1351
1352 tegra_add_of_provider(np); 1352 tegra_add_of_provider(np, of_clk_src_onecell_get);
1353 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 1353 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1354 1354
1355 tegra_clk_apply_init_table = tegra30_clock_apply_init_table; 1355 tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index ba923f0d5953..593d76a114f9 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -298,7 +298,8 @@ static struct reset_controller_dev rst_ctlr = {
298 .of_reset_n_cells = 1, 298 .of_reset_n_cells = 1,
299}; 299};
300 300
301void __init tegra_add_of_provider(struct device_node *np) 301void __init tegra_add_of_provider(struct device_node *np,
302 void *clk_src_onecell_get)
302{ 303{
303 int i; 304 int i;
304 305
@@ -314,7 +315,7 @@ void __init tegra_add_of_provider(struct device_node *np)
314 315
315 clk_data.clks = clks; 316 clk_data.clks = clks;
316 clk_data.clk_num = clk_num; 317 clk_data.clk_num = clk_num;
317 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 318 of_clk_add_provider(np, clk_src_onecell_get, &clk_data);
318 319
319 rst_ctlr.of_node = np; 320 rst_ctlr.of_node = np;
320 rst_ctlr.nr_resets = periph_banks * 32 + num_special_reset; 321 rst_ctlr.nr_resets = periph_banks * 32 + num_special_reset;
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index ba7e20e6a82b..e1f88463b600 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -763,7 +763,7 @@ struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks);
763 763
764struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk); 764struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk);
765 765
766void tegra_add_of_provider(struct device_node *np); 766void tegra_add_of_provider(struct device_node *np, void *clk_src_onecell_get);
767void tegra_register_devclks(struct tegra_devclk *dev_clks, int num); 767void tegra_register_devclks(struct tegra_devclk *dev_clks, int num);
768 768
769void tegra_audio_clk_init(void __iomem *clk_base, 769void tegra_audio_clk_init(void __iomem *clk_base,
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index ebc78ab2df05..4f5ff9fa11fd 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -51,6 +51,9 @@
51#define UNIPHIER_LD11_SYS_CLK_STDMAC(idx) \ 51#define UNIPHIER_LD11_SYS_CLK_STDMAC(idx) \
52 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8) 52 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
53 53
54#define UNIPHIER_LD11_SYS_CLK_HSC(idx) \
55 UNIPHIER_CLK_GATE("hsc", (idx), NULL, 0x210c, 9)
56
54#define UNIPHIER_PRO4_SYS_CLK_GIO(idx) \ 57#define UNIPHIER_PRO4_SYS_CLK_GIO(idx) \
55 UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6) 58 UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
56 59
@@ -182,6 +185,7 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
182 /* Index 5 reserved for eMMC PHY */ 185 /* Index 5 reserved for eMMC PHY */
183 UNIPHIER_LD11_SYS_CLK_ETHER(6), 186 UNIPHIER_LD11_SYS_CLK_ETHER(6),
184 UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC, MIO */ 187 UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC, MIO */
188 UNIPHIER_LD11_SYS_CLK_HSC(9),
185 UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25), 189 UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
186 UNIPHIER_LD11_SYS_CLK_AIO(40), 190 UNIPHIER_LD11_SYS_CLK_AIO(40),
187 UNIPHIER_LD11_SYS_CLK_EVEA(41), 191 UNIPHIER_LD11_SYS_CLK_EVEA(41),
@@ -215,6 +219,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
215 UNIPHIER_LD20_SYS_CLK_SD, 219 UNIPHIER_LD20_SYS_CLK_SD,
216 UNIPHIER_LD11_SYS_CLK_ETHER(6), 220 UNIPHIER_LD11_SYS_CLK_ETHER(6),
217 UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC */ 221 UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC */
222 UNIPHIER_LD11_SYS_CLK_HSC(9),
218 /* GIO is always clock-enabled: no function for 0x210c bit5 */ 223 /* GIO is always clock-enabled: no function for 0x210c bit5 */
219 /* 224 /*
220 * clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15. 225 * clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15.
diff --git a/drivers/clocksource/timer-sp804.c b/drivers/clocksource/timer-sp804.c
index 3ac9dec9a038..e01222ea888f 100644
--- a/drivers/clocksource/timer-sp804.c
+++ b/drivers/clocksource/timer-sp804.c
@@ -27,6 +27,7 @@
27#include <linux/io.h> 27#include <linux/io.h>
28#include <linux/of.h> 28#include <linux/of.h>
29#include <linux/of_address.h> 29#include <linux/of_address.h>
30#include <linux/of_clk.h>
30#include <linux/of_irq.h> 31#include <linux/of_irq.h>
31#include <linux/sched_clock.h> 32#include <linux/sched_clock.h>
32 33
@@ -245,7 +246,7 @@ static int __init sp804_of_init(struct device_node *np)
245 clk1 = NULL; 246 clk1 = NULL;
246 247
247 /* Get the 2nd clock if the timer has 3 timer clocks */ 248 /* Get the 2nd clock if the timer has 3 timer clocks */
248 if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) { 249 if (of_clk_get_parent_count(np) == 3) {
249 clk2 = of_clk_get(np, 1); 250 clk2 = of_clk_get(np, 1);
250 if (IS_ERR(clk2)) { 251 if (IS_ERR(clk2)) {
251 pr_err("sp804: %s clock not found: %d\n", np->name, 252 pr_err("sp804: %s clock not found: %d\n", np->name,
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 020d6d84639c..25e80a5370ca 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -12,12 +12,12 @@
12 12
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/clk.h> 14#include <linux/clk.h>
15#include <linux/clk-provider.h>
16#include <linux/gpio/driver.h> 15#include <linux/gpio/driver.h>
17#include <linux/irqdomain.h> 16#include <linux/irqdomain.h>
18#include <linux/irqchip/chained_irq.h> 17#include <linux/irqchip/chained_irq.h>
19#include <linux/export.h> 18#include <linux/export.h>
20#include <linux/of.h> 19#include <linux/of.h>
20#include <linux/of_clk.h>
21#include <linux/of_address.h> 21#include <linux/of_address.h>
22#include <linux/of_device.h> 22#include <linux/of_device.h>
23#include <linux/of_irq.h> 23#include <linux/of_irq.h>
@@ -1361,7 +1361,7 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
1361 goto gpiochip_error; 1361 goto gpiochip_error;
1362 } 1362 }
1363 1363
1364 ret = of_count_phandle_with_args(node, "clocks", "#clock-cells"); 1364 ret = of_clk_get_parent_count(node);
1365 clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb"); 1365 clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb");
1366 if (IS_ERR(clk)) { 1366 if (IS_ERR(clk)) {
1367 ret = PTR_ERR(clk); 1367 ret = PTR_ERR(clk);
diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
index 53efc386b1ad..13913d40c821 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -14,6 +14,7 @@
14#include <linux/pm_clock.h> 14#include <linux/pm_clock.h>
15#include <linux/pm_domain.h> 15#include <linux/pm_domain.h>
16#include <linux/of_address.h> 16#include <linux/of_address.h>
17#include <linux/of_clk.h>
17#include <linux/of_platform.h> 18#include <linux/of_platform.h>
18#include <linux/clk.h> 19#include <linux/clk.h>
19#include <linux/regmap.h> 20#include <linux/regmap.h>
@@ -400,8 +401,7 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
400 pd->info = pd_info; 401 pd->info = pd_info;
401 pd->pmu = pmu; 402 pd->pmu = pmu;
402 403
403 pd->num_clks = of_count_phandle_with_args(node, "clocks", 404 pd->num_clks = of_clk_get_parent_count(node);
404 "#clock-cells");
405 if (pd->num_clks > 0) { 405 if (pd->num_clks > 0) {
406 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks, 406 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
407 sizeof(*pd->clks), GFP_KERNEL); 407 sizeof(*pd->clks), GFP_KERNEL);
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index d9fcdb592b39..d8cb48a4b8eb 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -31,6 +31,7 @@
31#include <linux/iopoll.h> 31#include <linux/iopoll.h>
32#include <linux/of.h> 32#include <linux/of.h>
33#include <linux/of_address.h> 33#include <linux/of_address.h>
34#include <linux/of_clk.h>
34#include <linux/of_platform.h> 35#include <linux/of_platform.h>
35#include <linux/platform_device.h> 36#include <linux/platform_device.h>
36#include <linux/pm_domain.h> 37#include <linux/pm_domain.h>
@@ -725,7 +726,7 @@ static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
725 unsigned int i, count; 726 unsigned int i, count;
726 int err; 727 int err;
727 728
728 count = of_count_phandle_with_args(np, "clocks", "#clock-cells"); 729 count = of_clk_get_parent_count(np);
729 if (count == 0) 730 if (count == 0)
730 return -ENODEV; 731 return -ENODEV;
731 732
diff --git a/include/dt-bindings/clock/actions,s900-cmu.h b/include/dt-bindings/clock/actions,s900-cmu.h
new file mode 100644
index 000000000000..7c1251565f43
--- /dev/null
+++ b/include/dt-bindings/clock/actions,s900-cmu.h
@@ -0,0 +1,129 @@
1// SPDX-License-Identifier: GPL-2.0+
2//
3// Device Tree binding constants for Actions Semi S900 Clock Management Unit
4//
5// Copyright (c) 2014 Actions Semi Inc.
6// Copyright (c) 2018 Linaro Ltd.
7
8#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H
9#define __DT_BINDINGS_CLOCK_S900_CMU_H
10
11#define CLK_NONE 0
12
13/* fixed rate clocks */
14#define CLK_LOSC 1
15#define CLK_HOSC 2
16
17/* pll clocks */
18#define CLK_CORE_PLL 3
19#define CLK_DEV_PLL 4
20#define CLK_DDR_PLL 5
21#define CLK_NAND_PLL 6
22#define CLK_DISPLAY_PLL 7
23#define CLK_DSI_PLL 8
24#define CLK_ASSIST_PLL 9
25#define CLK_AUDIO_PLL 10
26
27/* system clock */
28#define CLK_CPU 15
29#define CLK_DEV 16
30#define CLK_NOC 17
31#define CLK_NOC_MUX 18
32#define CLK_NOC_DIV 19
33#define CLK_AHB 20
34#define CLK_APB 21
35#define CLK_DMAC 22
36
37/* peripheral device clock */
38#define CLK_GPIO 23
39
40#define CLK_BISP 24
41#define CLK_CSI0 25
42#define CLK_CSI1 26
43
44#define CLK_DE0 27
45#define CLK_DE1 28
46#define CLK_DE2 29
47#define CLK_DE3 30
48#define CLK_DSI 32
49
50#define CLK_GPU 33
51#define CLK_GPU_CORE 34
52#define CLK_GPU_MEM 35
53#define CLK_GPU_SYS 36
54
55#define CLK_HDE 37
56#define CLK_I2C0 38
57#define CLK_I2C1 39
58#define CLK_I2C2 40
59#define CLK_I2C3 41
60#define CLK_I2C4 42
61#define CLK_I2C5 43
62#define CLK_I2SRX 44
63#define CLK_I2STX 45
64#define CLK_IMX 46
65#define CLK_LCD 47
66#define CLK_NAND0 48
67#define CLK_NAND1 49
68#define CLK_PWM0 50
69#define CLK_PWM1 51
70#define CLK_PWM2 52
71#define CLK_PWM3 53
72#define CLK_PWM4 54
73#define CLK_PWM5 55
74#define CLK_SD0 56
75#define CLK_SD1 57
76#define CLK_SD2 58
77#define CLK_SD3 59
78#define CLK_SENSOR 60
79#define CLK_SPEED_SENSOR 61
80#define CLK_SPI0 62
81#define CLK_SPI1 63
82#define CLK_SPI2 64
83#define CLK_SPI3 65
84#define CLK_THERMAL_SENSOR 66
85#define CLK_UART0 67
86#define CLK_UART1 68
87#define CLK_UART2 69
88#define CLK_UART3 70
89#define CLK_UART4 71
90#define CLK_UART5 72
91#define CLK_UART6 73
92#define CLK_VCE 74
93#define CLK_VDE 75
94
95#define CLK_USB3_480MPLL0 76
96#define CLK_USB3_480MPHY0 77
97#define CLK_USB3_5GPHY 78
98#define CLK_USB3_CCE 79
99#define CLK_USB3_MAC 80
100
101#define CLK_TIMER 83
102
103#define CLK_HDMI_AUDIO 84
104
105#define CLK_24M 85
106
107#define CLK_EDP 86
108
109#define CLK_24M_EDP 87
110#define CLK_EDP_PLL 88
111#define CLK_EDP_LINK 89
112
113#define CLK_USB2H0_PLLEN 90
114#define CLK_USB2H0_PHY 91
115#define CLK_USB2H0_CCE 92
116#define CLK_USB2H1_PLLEN 93
117#define CLK_USB2H1_PHY 94
118#define CLK_USB2H1_CCE 95
119
120#define CLK_DDR0 96
121#define CLK_DDR1 97
122#define CLK_DMM 98
123
124#define CLK_ETH_MAC 99
125#define CLK_RMII_REF 100
126
127#define CLK_NR_CLKS (CLK_RMII_REF + 1)
128
129#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */
diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h
index d3558d897a4d..44761849fcbe 100644
--- a/include/dt-bindings/clock/aspeed-clock.h
+++ b/include/dt-bindings/clock/aspeed-clock.h
@@ -38,6 +38,7 @@
38#define ASPEED_CLK_MAC 32 38#define ASPEED_CLK_MAC 32
39#define ASPEED_CLK_BCLK 33 39#define ASPEED_CLK_BCLK 33
40#define ASPEED_CLK_MPLL 34 40#define ASPEED_CLK_MPLL 34
41#define ASPEED_CLK_24M 35
41 42
42#define ASPEED_RESET_XDMA 0 43#define ASPEED_RESET_XDMA 0
43#define ASPEED_RESET_MCTP 1 44#define ASPEED_RESET_MCTP 1
@@ -45,8 +46,9 @@
45#define ASPEED_RESET_JTAG_MASTER 3 46#define ASPEED_RESET_JTAG_MASTER 3
46#define ASPEED_RESET_MIC 4 47#define ASPEED_RESET_MIC 4
47#define ASPEED_RESET_PWM 5 48#define ASPEED_RESET_PWM 5
48#define ASPEED_RESET_PCIVGA 6 49#define ASPEED_RESET_PECI 6
49#define ASPEED_RESET_I2C 7 50#define ASPEED_RESET_I2C 7
50#define ASPEED_RESET_AHB 8 51#define ASPEED_RESET_AHB 8
52#define ASPEED_RESET_CRT1 9
51 53
52#endif 54#endif
diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h
new file mode 100644
index 000000000000..61955016a55b
--- /dev/null
+++ b/include/dt-bindings/clock/axg-aoclkc.h
@@ -0,0 +1,26 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2/*
3 * Copyright (c) 2016 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 *
6 * Copyright (c) 2018 Amlogic, inc.
7 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
8 */
9
10#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
11#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
12
13#define CLKID_AO_REMOTE 0
14#define CLKID_AO_I2C_MASTER 1
15#define CLKID_AO_I2C_SLAVE 2
16#define CLKID_AO_UART1 3
17#define CLKID_AO_UART2 4
18#define CLKID_AO_IR_BLASTER 5
19#define CLKID_AO_SAR_ADC 6
20#define CLKID_AO_CLK81 7
21#define CLKID_AO_SAR_ADC_SEL 8
22#define CLKID_AO_SAR_ADC_DIV 9
23#define CLKID_AO_SAR_ADC_CLK 10
24#define CLKID_AO_ALT_XTAL 11
25
26#endif
diff --git a/include/dt-bindings/clock/bcm-sr.h b/include/dt-bindings/clock/bcm-sr.h
index cff6c6fe2947..419011ba1a94 100644
--- a/include/dt-bindings/clock/bcm-sr.h
+++ b/include/dt-bindings/clock/bcm-sr.h
@@ -35,7 +35,7 @@
35 35
36/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */ 36/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
37#define BCM_SR_GENPLL0 0 37#define BCM_SR_GENPLL0 0
38#define BCM_SR_GENPLL0_SATA_CLK 1 38#define BCM_SR_GENPLL0_125M_CLK 1
39#define BCM_SR_GENPLL0_SCR_CLK 2 39#define BCM_SR_GENPLL0_SCR_CLK 2
40#define BCM_SR_GENPLL0_250M_CLK 3 40#define BCM_SR_GENPLL0_250M_CLK 3
41#define BCM_SR_GENPLL0_PCIE_AXI_CLK 4 41#define BCM_SR_GENPLL0_PCIE_AXI_CLK 4
@@ -50,9 +50,11 @@
50/* GENPLL 2 clock channel ID NITRO MHB*/ 50/* GENPLL 2 clock channel ID NITRO MHB*/
51#define BCM_SR_GENPLL2 0 51#define BCM_SR_GENPLL2 0
52#define BCM_SR_GENPLL2_NIC_CLK 1 52#define BCM_SR_GENPLL2_NIC_CLK 1
53#define BCM_SR_GENPLL2_250_NITRO_CLK 2 53#define BCM_SR_GENPLL2_TS_500_CLK 2
54#define BCM_SR_GENPLL2_125_NITRO_CLK 3 54#define BCM_SR_GENPLL2_125_NITRO_CLK 3
55#define BCM_SR_GENPLL2_CHIMP_CLK 4 55#define BCM_SR_GENPLL2_CHIMP_CLK 4
56#define BCM_SR_GENPLL2_NIC_FLASH_CLK 5
57#define BCM_SR_GENPLL2_FS4_CLK 6
56 58
57/* GENPLL 3 HSLS clock channel ID */ 59/* GENPLL 3 HSLS clock channel ID */
58#define BCM_SR_GENPLL3 0 60#define BCM_SR_GENPLL3 0
@@ -62,11 +64,16 @@
62/* GENPLL 4 SCR clock channel ID */ 64/* GENPLL 4 SCR clock channel ID */
63#define BCM_SR_GENPLL4 0 65#define BCM_SR_GENPLL4 0
64#define BCM_SR_GENPLL4_CCN_CLK 1 66#define BCM_SR_GENPLL4_CCN_CLK 1
67#define BCM_SR_GENPLL4_TPIU_PLL_CLK 2
68#define BCM_SR_GENPLL4_NOC_CLK 3
69#define BCM_SR_GENPLL4_CHCLK_FS4_CLK 4
70#define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 5
65 71
66/* GENPLL 5 FS4 clock channel ID */ 72/* GENPLL 5 FS4 clock channel ID */
67#define BCM_SR_GENPLL5 0 73#define BCM_SR_GENPLL5 0
68#define BCM_SR_GENPLL5_FS_CLK 1 74#define BCM_SR_GENPLL5_FS4_HF_CLK 1
69#define BCM_SR_GENPLL5_SPU_CLK 2 75#define BCM_SR_GENPLL5_CRYPTO_AE_CLK 2
76#define BCM_SR_GENPLL5_RAID_AE_CLK 3
70 77
71/* GENPLL 6 NITRO clock channel ID */ 78/* GENPLL 6 NITRO clock channel ID */
72#define BCM_SR_GENPLL6 0 79#define BCM_SR_GENPLL6 0
@@ -74,13 +81,16 @@
74 81
75/* LCPLL0 clock channel ID */ 82/* LCPLL0 clock channel ID */
76#define BCM_SR_LCPLL0 0 83#define BCM_SR_LCPLL0 0
77#define BCM_SR_LCPLL0_SATA_REF_CLK 1 84#define BCM_SR_LCPLL0_SATA_REFP_CLK 1
78#define BCM_SR_LCPLL0_USB_REF_CLK 2 85#define BCM_SR_LCPLL0_SATA_REFN_CLK 2
79#define BCM_SR_LCPLL0_SATA_REFPN_CLK 3 86#define BCM_SR_LCPLL0_SATA_350_CLK 3
87#define BCM_SR_LCPLL0_SATA_500_CLK 4
80 88
81/* LCPLL1 clock channel ID */ 89/* LCPLL1 clock channel ID */
82#define BCM_SR_LCPLL1 0 90#define BCM_SR_LCPLL1 0
83#define BCM_SR_LCPLL1_WAN_CLK 1 91#define BCM_SR_LCPLL1_WAN_CLK 1
92#define BCM_SR_LCPLL1_USB_REF_CLK 2
93#define BCM_SR_LCPLL1_CRMU_TS_CLK 3
84 94
85/* LCPLL PCIE clock channel ID */ 95/* LCPLL PCIE clock channel ID */
86#define BCM_SR_LCPLL_PCIE 0 96#define BCM_SR_LCPLL_PCIE 0
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 8ba99a5e3fd3..7a892be90549 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -125,5 +125,7 @@
125#define CLKID_VAPB_1 138 125#define CLKID_VAPB_1 138
126#define CLKID_VAPB_SEL 139 126#define CLKID_VAPB_SEL 139
127#define CLKID_VAPB 140 127#define CLKID_VAPB 140
128#define CLKID_VDEC_1 153
129#define CLKID_VDEC_HEVC 156
128 130
129#endif /* __GXBB_CLKC_H */ 131#endif /* __GXBB_CLKC_H */
diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h
index fab30b3f78b2..136de24733be 100644
--- a/include/dt-bindings/clock/histb-clock.h
+++ b/include/dt-bindings/clock/histb-clock.h
@@ -62,6 +62,14 @@
62#define HISTB_USB2_PHY1_REF_CLK 40 62#define HISTB_USB2_PHY1_REF_CLK 40
63#define HISTB_USB2_PHY2_REF_CLK 41 63#define HISTB_USB2_PHY2_REF_CLK 41
64#define HISTB_COMBPHY0_CLK 42 64#define HISTB_COMBPHY0_CLK 42
65#define HISTB_USB3_BUS_CLK 43
66#define HISTB_USB3_UTMI_CLK 44
67#define HISTB_USB3_PIPE_CLK 45
68#define HISTB_USB3_SUSPEND_CLK 46
69#define HISTB_USB3_BUS_CLK1 47
70#define HISTB_USB3_UTMI_CLK1 48
71#define HISTB_USB3_PIPE_CLK1 49
72#define HISTB_USB3_SUSPEND_CLK1 50
65 73
66/* clocks provided by mcu CRG */ 74/* clocks provided by mcu CRG */
67#define HISTB_MCE_CLK 1 75#define HISTB_MCE_CLK 1
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index da59fd9cdb5e..7ad171b8f3bf 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -271,6 +271,8 @@
271#define IMX6QDL_CLK_PRE_AXI 258 271#define IMX6QDL_CLK_PRE_AXI 258
272#define IMX6QDL_CLK_MLB_SEL 259 272#define IMX6QDL_CLK_MLB_SEL 259
273#define IMX6QDL_CLK_MLB_PODF 260 273#define IMX6QDL_CLK_MLB_PODF 260
274#define IMX6QDL_CLK_END 261 274#define IMX6QDL_CLK_EPIT1 261
275#define IMX6QDL_CLK_EPIT2 262
276#define IMX6QDL_CLK_END 263
275 277
276#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ 278#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
index 36f0324902a5..cd2d6c570e86 100644
--- a/include/dt-bindings/clock/imx6sx-clock.h
+++ b/include/dt-bindings/clock/imx6sx-clock.h
@@ -275,6 +275,10 @@
275#define IMX6SX_PLL6_BYPASS 262 275#define IMX6SX_PLL6_BYPASS 262
276#define IMX6SX_PLL7_BYPASS 263 276#define IMX6SX_PLL7_BYPASS 263
277#define IMX6SX_CLK_SPDIF_GCLK 264 277#define IMX6SX_CLK_SPDIF_GCLK 264
278#define IMX6SX_CLK_CLK_END 265 278#define IMX6SX_CLK_LVDS2_SEL 265
279#define IMX6SX_CLK_LVDS2_OUT 266
280#define IMX6SX_CLK_LVDS2_IN 267
281#define IMX6SX_CLK_ANACLK2 268
282#define IMX6SX_CLK_CLK_END 269
279 283
280#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */ 284#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h
index ee9f1a508d2f..9564597cbfac 100644
--- a/include/dt-bindings/clock/imx6ul-clock.h
+++ b/include/dt-bindings/clock/imx6ul-clock.h
@@ -235,20 +235,27 @@
235#define IMX6UL_CLK_CSI_PODF 222 235#define IMX6UL_CLK_CSI_PODF 222
236#define IMX6UL_CLK_PLL3_120M 223 236#define IMX6UL_CLK_PLL3_120M 223
237#define IMX6UL_CLK_KPP 224 237#define IMX6UL_CLK_KPP 224
238#define IMX6UL_CLK_CKO1_SEL 225
239#define IMX6UL_CLK_CKO1_PODF 226
240#define IMX6UL_CLK_CKO1 227
241#define IMX6UL_CLK_CKO2_SEL 228
242#define IMX6UL_CLK_CKO2_PODF 229
243#define IMX6UL_CLK_CKO2 230
244#define IMX6UL_CLK_CKO 231
238 245
239/* For i.MX6ULL */ 246/* For i.MX6ULL */
240#define IMX6ULL_CLK_ESAI_PRED 225 247#define IMX6ULL_CLK_ESAI_PRED 232
241#define IMX6ULL_CLK_ESAI_PODF 226 248#define IMX6ULL_CLK_ESAI_PODF 233
242#define IMX6ULL_CLK_ESAI_EXTAL 227 249#define IMX6ULL_CLK_ESAI_EXTAL 234
243#define IMX6ULL_CLK_ESAI_MEM 228 250#define IMX6ULL_CLK_ESAI_MEM 235
244#define IMX6ULL_CLK_ESAI_IPG 229 251#define IMX6ULL_CLK_ESAI_IPG 236
245#define IMX6ULL_CLK_DCP_CLK 230 252#define IMX6ULL_CLK_DCP_CLK 237
246#define IMX6ULL_CLK_EPDC_PRE_SEL 231 253#define IMX6ULL_CLK_EPDC_PRE_SEL 238
247#define IMX6ULL_CLK_EPDC_SEL 232 254#define IMX6ULL_CLK_EPDC_SEL 239
248#define IMX6ULL_CLK_EPDC_PODF 233 255#define IMX6ULL_CLK_EPDC_PODF 240
249#define IMX6ULL_CLK_EPDC_ACLK 234 256#define IMX6ULL_CLK_EPDC_ACLK 241
250#define IMX6ULL_CLK_EPDC_PIX 235 257#define IMX6ULL_CLK_EPDC_PIX 242
251#define IMX6ULL_CLK_ESAI_SEL 236 258#define IMX6ULL_CLK_ESAI_SEL 243
252#define IMX6UL_CLK_END 237 259#define IMX6UL_CLK_END 244
253 260
254#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ 261#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
index b2325d3e236a..0d67f53bba93 100644
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -168,7 +168,7 @@
168#define IMX7D_SPDIF_ROOT_SRC 155 168#define IMX7D_SPDIF_ROOT_SRC 155
169#define IMX7D_SPDIF_ROOT_CG 156 169#define IMX7D_SPDIF_ROOT_CG 156
170#define IMX7D_SPDIF_ROOT_DIV 157 170#define IMX7D_SPDIF_ROOT_DIV 157
171#define IMX7D_ENET1_REF_ROOT_CLK 158 171#define IMX7D_ENET1_IPG_ROOT_CLK 158
172#define IMX7D_ENET1_REF_ROOT_SRC 159 172#define IMX7D_ENET1_REF_ROOT_SRC 159
173#define IMX7D_ENET1_REF_ROOT_CG 160 173#define IMX7D_ENET1_REF_ROOT_CG 160
174#define IMX7D_ENET1_REF_ROOT_DIV 161 174#define IMX7D_ENET1_REF_ROOT_DIV 161
@@ -176,7 +176,7 @@
176#define IMX7D_ENET1_TIME_ROOT_SRC 163 176#define IMX7D_ENET1_TIME_ROOT_SRC 163
177#define IMX7D_ENET1_TIME_ROOT_CG 164 177#define IMX7D_ENET1_TIME_ROOT_CG 164
178#define IMX7D_ENET1_TIME_ROOT_DIV 165 178#define IMX7D_ENET1_TIME_ROOT_DIV 165
179#define IMX7D_ENET2_REF_ROOT_CLK 166 179#define IMX7D_ENET2_IPG_ROOT_CLK 166
180#define IMX7D_ENET2_REF_ROOT_SRC 167 180#define IMX7D_ENET2_REF_ROOT_SRC 167
181#define IMX7D_ENET2_REF_ROOT_CG 168 181#define IMX7D_ENET2_REF_ROOT_CG 168
182#define IMX7D_ENET2_REF_ROOT_DIV 169 182#define IMX7D_ENET2_REF_ROOT_DIV 169
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index dea9d46d4fa7..a60f47b49231 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -102,5 +102,6 @@
102#define CLKID_MPLL0 93 102#define CLKID_MPLL0 93
103#define CLKID_MPLL1 94 103#define CLKID_MPLL1 94
104#define CLKID_MPLL2 95 104#define CLKID_MPLL2 95
105#define CLKID_NAND_CLK 112
105 106
106#endif /* __MESON8B_CLKC_H */ 107#endif /* __MESON8B_CLKC_H */
diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h
index 24e93dfcee9f..9ac2f2b5710a 100644
--- a/include/dt-bindings/clock/mt2701-clk.h
+++ b/include/dt-bindings/clock/mt2701-clk.h
@@ -171,13 +171,12 @@
171#define CLK_TOP_8BDAC 151 171#define CLK_TOP_8BDAC 151
172#define CLK_TOP_WBG_DIG_416M 152 172#define CLK_TOP_WBG_DIG_416M 152
173#define CLK_TOP_DPI 153 173#define CLK_TOP_DPI 153
174#define CLK_TOP_HDMITX_CLKDIG_CTS 154 174#define CLK_TOP_DSI0_LNTC_DSI 154
175#define CLK_TOP_DSI0_LNTC_DSI 155 175#define CLK_TOP_AUD_EXT1 155
176#define CLK_TOP_AUD_EXT1 156 176#define CLK_TOP_AUD_EXT2 156
177#define CLK_TOP_AUD_EXT2 157 177#define CLK_TOP_NFI1X_PAD 157
178#define CLK_TOP_NFI1X_PAD 158 178#define CLK_TOP_AXISEL_D4 158
179#define CLK_TOP_AXISEL_D4 159 179#define CLK_TOP_NR 159
180#define CLK_TOP_NR 160
181 180
182/* APMIXEDSYS */ 181/* APMIXEDSYS */
183 182
@@ -194,7 +193,8 @@
194#define CLK_APMIXED_HADDS2PLL 11 193#define CLK_APMIXED_HADDS2PLL 11
195#define CLK_APMIXED_AUD2PLL 12 194#define CLK_APMIXED_AUD2PLL 12
196#define CLK_APMIXED_TVD2PLL 13 195#define CLK_APMIXED_TVD2PLL 13
197#define CLK_APMIXED_NR 14 196#define CLK_APMIXED_HDMI_REF 14
197#define CLK_APMIXED_NR 15
198 198
199/* DDRPHY */ 199/* DDRPHY */
200 200
@@ -431,6 +431,10 @@
431#define CLK_ETHSYS_CRYPTO 8 431#define CLK_ETHSYS_CRYPTO 8
432#define CLK_ETHSYS_NR 9 432#define CLK_ETHSYS_NR 9
433 433
434/* G3DSYS */
435#define CLK_G3DSYS_CORE 1
436#define CLK_G3DSYS_NR 2
437
434/* BDP */ 438/* BDP */
435 439
436#define CLK_BDP_BRG_BA 1 440#define CLK_BDP_BRG_BA 1
diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
new file mode 100644
index 000000000000..f21522605b94
--- /dev/null
+++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
@@ -0,0 +1,44 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Nuvoton NPCM7xx Clock Generator binding
4 * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk
5 *
6 * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com
7 *
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H
11#define __DT_BINDINGS_CLOCK_NPCM7XX_H
12
13
14#define NPCM7XX_CLK_CPU 0
15#define NPCM7XX_CLK_GFX_PIXEL 1
16#define NPCM7XX_CLK_MC 2
17#define NPCM7XX_CLK_ADC 3
18#define NPCM7XX_CLK_AHB 4
19#define NPCM7XX_CLK_TIMER 5
20#define NPCM7XX_CLK_UART 6
21#define NPCM7XX_CLK_MMC 7
22#define NPCM7XX_CLK_SPI3 8
23#define NPCM7XX_CLK_PCI 9
24#define NPCM7XX_CLK_AXI 10
25#define NPCM7XX_CLK_APB4 11
26#define NPCM7XX_CLK_APB3 12
27#define NPCM7XX_CLK_APB2 13
28#define NPCM7XX_CLK_APB1 14
29#define NPCM7XX_CLK_APB5 15
30#define NPCM7XX_CLK_CLKOUT 16
31#define NPCM7XX_CLK_GFX 17
32#define NPCM7XX_CLK_SU 18
33#define NPCM7XX_CLK_SU48 19
34#define NPCM7XX_CLK_SDHC 20
35#define NPCM7XX_CLK_SPI0 21
36#define NPCM7XX_CLK_SPIX 22
37
38#define NPCM7XX_CLK_REFCLK 23
39#define NPCM7XX_CLK_SYSBYPCK 24
40#define NPCM7XX_CLK_MCBYPCK 25
41
42#define NPCM7XX_NUM_CLOCKS (NPCM7XX_CLK_MCBYPCK+1)
43
44#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h
new file mode 100644
index 000000000000..58a242e656b1
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h
@@ -0,0 +1,208 @@
1/*
2 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
15#define _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
16
17#define BLSP1_QUP1_I2C_APPS_CLK_SRC 0
18#define BLSP1_QUP1_SPI_APPS_CLK_SRC 1
19#define BLSP1_QUP2_I2C_APPS_CLK_SRC 2
20#define BLSP1_QUP2_SPI_APPS_CLK_SRC 3
21#define BLSP1_QUP3_I2C_APPS_CLK_SRC 4
22#define BLSP1_QUP3_SPI_APPS_CLK_SRC 5
23#define BLSP1_QUP4_I2C_APPS_CLK_SRC 6
24#define BLSP1_QUP4_SPI_APPS_CLK_SRC 7
25#define BLSP1_QUP5_I2C_APPS_CLK_SRC 8
26#define BLSP1_QUP5_SPI_APPS_CLK_SRC 9
27#define BLSP1_QUP6_I2C_APPS_CLK_SRC 10
28#define BLSP1_QUP6_SPI_APPS_CLK_SRC 11
29#define BLSP1_UART1_APPS_CLK_SRC 12
30#define BLSP1_UART2_APPS_CLK_SRC 13
31#define BLSP1_UART3_APPS_CLK_SRC 14
32#define BLSP2_QUP1_I2C_APPS_CLK_SRC 15
33#define BLSP2_QUP1_SPI_APPS_CLK_SRC 16
34#define BLSP2_QUP2_I2C_APPS_CLK_SRC 17
35#define BLSP2_QUP2_SPI_APPS_CLK_SRC 18
36#define BLSP2_QUP3_I2C_APPS_CLK_SRC 19
37#define BLSP2_QUP3_SPI_APPS_CLK_SRC 20
38#define BLSP2_QUP4_I2C_APPS_CLK_SRC 21
39#define BLSP2_QUP4_SPI_APPS_CLK_SRC 22
40#define BLSP2_QUP5_I2C_APPS_CLK_SRC 23
41#define BLSP2_QUP5_SPI_APPS_CLK_SRC 24
42#define BLSP2_QUP6_I2C_APPS_CLK_SRC 25
43#define BLSP2_QUP6_SPI_APPS_CLK_SRC 26
44#define BLSP2_UART1_APPS_CLK_SRC 27
45#define BLSP2_UART2_APPS_CLK_SRC 28
46#define BLSP2_UART3_APPS_CLK_SRC 29
47#define GCC_AGGRE1_NOC_XO_CLK 30
48#define GCC_AGGRE1_UFS_AXI_CLK 31
49#define GCC_AGGRE1_USB3_AXI_CLK 32
50#define GCC_APSS_QDSS_TSCTR_DIV2_CLK 33
51#define GCC_APSS_QDSS_TSCTR_DIV8_CLK 34
52#define GCC_BIMC_HMSS_AXI_CLK 35
53#define GCC_BIMC_MSS_Q6_AXI_CLK 36
54#define GCC_BLSP1_AHB_CLK 37
55#define GCC_BLSP1_QUP1_I2C_APPS_CLK 38
56#define GCC_BLSP1_QUP1_SPI_APPS_CLK 39
57#define GCC_BLSP1_QUP2_I2C_APPS_CLK 40
58#define GCC_BLSP1_QUP2_SPI_APPS_CLK 41
59#define GCC_BLSP1_QUP3_I2C_APPS_CLK 42
60#define GCC_BLSP1_QUP3_SPI_APPS_CLK 43
61#define GCC_BLSP1_QUP4_I2C_APPS_CLK 44
62#define GCC_BLSP1_QUP4_SPI_APPS_CLK 45
63#define GCC_BLSP1_QUP5_I2C_APPS_CLK 46
64#define GCC_BLSP1_QUP5_SPI_APPS_CLK 47
65#define GCC_BLSP1_QUP6_I2C_APPS_CLK 48
66#define GCC_BLSP1_QUP6_SPI_APPS_CLK 49
67#define GCC_BLSP1_SLEEP_CLK 50
68#define GCC_BLSP1_UART1_APPS_CLK 51
69#define GCC_BLSP1_UART2_APPS_CLK 52
70#define GCC_BLSP1_UART3_APPS_CLK 53
71#define GCC_BLSP2_AHB_CLK 54
72#define GCC_BLSP2_QUP1_I2C_APPS_CLK 55
73#define GCC_BLSP2_QUP1_SPI_APPS_CLK 56
74#define GCC_BLSP2_QUP2_I2C_APPS_CLK 57
75#define GCC_BLSP2_QUP2_SPI_APPS_CLK 58
76#define GCC_BLSP2_QUP3_I2C_APPS_CLK 59
77#define GCC_BLSP2_QUP3_SPI_APPS_CLK 60
78#define GCC_BLSP2_QUP4_I2C_APPS_CLK 61
79#define GCC_BLSP2_QUP4_SPI_APPS_CLK 62
80#define GCC_BLSP2_QUP5_I2C_APPS_CLK 63
81#define GCC_BLSP2_QUP5_SPI_APPS_CLK 64
82#define GCC_BLSP2_QUP6_I2C_APPS_CLK 65
83#define GCC_BLSP2_QUP6_SPI_APPS_CLK 66
84#define GCC_BLSP2_SLEEP_CLK 67
85#define GCC_BLSP2_UART1_APPS_CLK 68
86#define GCC_BLSP2_UART2_APPS_CLK 69
87#define GCC_BLSP2_UART3_APPS_CLK 70
88#define GCC_CFG_NOC_USB3_AXI_CLK 71
89#define GCC_GP1_CLK 72
90#define GCC_GP2_CLK 73
91#define GCC_GP3_CLK 74
92#define GCC_GPU_BIMC_GFX_CLK 75
93#define GCC_GPU_BIMC_GFX_SRC_CLK 76
94#define GCC_GPU_CFG_AHB_CLK 77
95#define GCC_GPU_SNOC_DVM_GFX_CLK 78
96#define GCC_HMSS_AHB_CLK 79
97#define GCC_HMSS_AT_CLK 80
98#define GCC_HMSS_DVM_BUS_CLK 81
99#define GCC_HMSS_RBCPR_CLK 82
100#define GCC_HMSS_TRIG_CLK 83
101#define GCC_LPASS_AT_CLK 84
102#define GCC_LPASS_TRIG_CLK 85
103#define GCC_MMSS_NOC_CFG_AHB_CLK 86
104#define GCC_MMSS_QM_AHB_CLK 87
105#define GCC_MMSS_QM_CORE_CLK 88
106#define GCC_MMSS_SYS_NOC_AXI_CLK 89
107#define GCC_MSS_AT_CLK 90
108#define GCC_PCIE_0_AUX_CLK 91
109#define GCC_PCIE_0_CFG_AHB_CLK 92
110#define GCC_PCIE_0_MSTR_AXI_CLK 93
111#define GCC_PCIE_0_PIPE_CLK 94
112#define GCC_PCIE_0_SLV_AXI_CLK 95
113#define GCC_PCIE_PHY_AUX_CLK 96
114#define GCC_PDM2_CLK 97
115#define GCC_PDM_AHB_CLK 98
116#define GCC_PDM_XO4_CLK 99
117#define GCC_PRNG_AHB_CLK 100
118#define GCC_SDCC2_AHB_CLK 101
119#define GCC_SDCC2_APPS_CLK 102
120#define GCC_SDCC4_AHB_CLK 103
121#define GCC_SDCC4_APPS_CLK 104
122#define GCC_TSIF_AHB_CLK 105
123#define GCC_TSIF_INACTIVITY_TIMERS_CLK 106
124#define GCC_TSIF_REF_CLK 107
125#define GCC_UFS_AHB_CLK 108
126#define GCC_UFS_AXI_CLK 109
127#define GCC_UFS_ICE_CORE_CLK 110
128#define GCC_UFS_PHY_AUX_CLK 111
129#define GCC_UFS_RX_SYMBOL_0_CLK 112
130#define GCC_UFS_RX_SYMBOL_1_CLK 113
131#define GCC_UFS_TX_SYMBOL_0_CLK 114
132#define GCC_UFS_UNIPRO_CORE_CLK 115
133#define GCC_USB30_MASTER_CLK 116
134#define GCC_USB30_MOCK_UTMI_CLK 117
135#define GCC_USB30_SLEEP_CLK 118
136#define GCC_USB3_PHY_AUX_CLK 119
137#define GCC_USB3_PHY_PIPE_CLK 120
138#define GCC_USB_PHY_CFG_AHB2PHY_CLK 121
139#define GP1_CLK_SRC 122
140#define GP2_CLK_SRC 123
141#define GP3_CLK_SRC 124
142#define GPLL0 125
143#define GPLL0_OUT_EVEN 126
144#define GPLL0_OUT_MAIN 127
145#define GPLL0_OUT_ODD 128
146#define GPLL0_OUT_TEST 129
147#define GPLL1 130
148#define GPLL1_OUT_EVEN 131
149#define GPLL1_OUT_MAIN 132
150#define GPLL1_OUT_ODD 133
151#define GPLL1_OUT_TEST 134
152#define GPLL2 135
153#define GPLL2_OUT_EVEN 136
154#define GPLL2_OUT_MAIN 137
155#define GPLL2_OUT_ODD 138
156#define GPLL2_OUT_TEST 139
157#define GPLL3 140
158#define GPLL3_OUT_EVEN 141
159#define GPLL3_OUT_MAIN 142
160#define GPLL3_OUT_ODD 143
161#define GPLL3_OUT_TEST 144
162#define GPLL4 145
163#define GPLL4_OUT_EVEN 146
164#define GPLL4_OUT_MAIN 147
165#define GPLL4_OUT_ODD 148
166#define GPLL4_OUT_TEST 149
167#define GPLL6 150
168#define GPLL6_OUT_EVEN 151
169#define GPLL6_OUT_MAIN 152
170#define GPLL6_OUT_ODD 153
171#define GPLL6_OUT_TEST 154
172#define HMSS_AHB_CLK_SRC 155
173#define HMSS_RBCPR_CLK_SRC 156
174#define PCIE_AUX_CLK_SRC 157
175#define PDM2_CLK_SRC 158
176#define SDCC2_APPS_CLK_SRC 159
177#define SDCC4_APPS_CLK_SRC 160
178#define TSIF_REF_CLK_SRC 161
179#define UFS_AXI_CLK_SRC 162
180#define USB30_MASTER_CLK_SRC 163
181#define USB30_MOCK_UTMI_CLK_SRC 164
182#define USB3_PHY_AUX_CLK_SRC 165
183
184#define PCIE_0_GDSC 0
185#define UFS_GDSC 1
186#define USB_30_GDSC 2
187
188#define GCC_BLSP1_QUP1_BCR 0
189#define GCC_BLSP1_QUP2_BCR 1
190#define GCC_BLSP1_QUP3_BCR 2
191#define GCC_BLSP1_QUP4_BCR 3
192#define GCC_BLSP1_QUP5_BCR 4
193#define GCC_BLSP1_QUP6_BCR 5
194#define GCC_BLSP2_QUP1_BCR 6
195#define GCC_BLSP2_QUP2_BCR 7
196#define GCC_BLSP2_QUP3_BCR 8
197#define GCC_BLSP2_QUP4_BCR 9
198#define GCC_BLSP2_QUP5_BCR 10
199#define GCC_BLSP2_QUP6_BCR 11
200#define GCC_PCIE_0_BCR 12
201#define GCC_PDM_BCR 13
202#define GCC_SDCC2_BCR 14
203#define GCC_SDCC4_BCR 15
204#define GCC_TSIF_BCR 16
205#define GCC_UFS_BCR 17
206#define GCC_USB_30_BCR 18
207
208#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h b/include/dt-bindings/clock/qcom,gcc-sdm845.h
new file mode 100644
index 000000000000..aca61264f12c
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sdm845.h
@@ -0,0 +1,239 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
7#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
8
9/* GCC clock registers */
10#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0
11#define GCC_AGGRE_UFS_CARD_AXI_CLK 1
12#define GCC_AGGRE_UFS_PHY_AXI_CLK 2
13#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3
14#define GCC_AGGRE_USB3_SEC_AXI_CLK 4
15#define GCC_BOOT_ROM_AHB_CLK 5
16#define GCC_CAMERA_AHB_CLK 6
17#define GCC_CAMERA_AXI_CLK 7
18#define GCC_CAMERA_XO_CLK 8
19#define GCC_CE1_AHB_CLK 9
20#define GCC_CE1_AXI_CLK 10
21#define GCC_CE1_CLK 11
22#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12
23#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13
24#define GCC_CPUSS_AHB_CLK 14
25#define GCC_CPUSS_AHB_CLK_SRC 15
26#define GCC_CPUSS_RBCPR_CLK 16
27#define GCC_CPUSS_RBCPR_CLK_SRC 17
28#define GCC_DDRSS_GPU_AXI_CLK 18
29#define GCC_DISP_AHB_CLK 19
30#define GCC_DISP_AXI_CLK 20
31#define GCC_DISP_GPLL0_CLK_SRC 21
32#define GCC_DISP_GPLL0_DIV_CLK_SRC 22
33#define GCC_DISP_XO_CLK 23
34#define GCC_GP1_CLK 24
35#define GCC_GP1_CLK_SRC 25
36#define GCC_GP2_CLK 26
37#define GCC_GP2_CLK_SRC 27
38#define GCC_GP3_CLK 28
39#define GCC_GP3_CLK_SRC 29
40#define GCC_GPU_CFG_AHB_CLK 30
41#define GCC_GPU_GPLL0_CLK_SRC 31
42#define GCC_GPU_GPLL0_DIV_CLK_SRC 32
43#define GCC_GPU_MEMNOC_GFX_CLK 33
44#define GCC_GPU_SNOC_DVM_GFX_CLK 34
45#define GCC_MSS_AXIS2_CLK 35
46#define GCC_MSS_CFG_AHB_CLK 36
47#define GCC_MSS_GPLL0_DIV_CLK_SRC 37
48#define GCC_MSS_MFAB_AXIS_CLK 38
49#define GCC_MSS_Q6_MEMNOC_AXI_CLK 39
50#define GCC_MSS_SNOC_AXI_CLK 40
51#define GCC_PCIE_0_AUX_CLK 41
52#define GCC_PCIE_0_AUX_CLK_SRC 42
53#define GCC_PCIE_0_CFG_AHB_CLK 43
54#define GCC_PCIE_0_CLKREF_CLK 44
55#define GCC_PCIE_0_MSTR_AXI_CLK 45
56#define GCC_PCIE_0_PIPE_CLK 46
57#define GCC_PCIE_0_SLV_AXI_CLK 47
58#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48
59#define GCC_PCIE_1_AUX_CLK 49
60#define GCC_PCIE_1_AUX_CLK_SRC 50
61#define GCC_PCIE_1_CFG_AHB_CLK 51
62#define GCC_PCIE_1_CLKREF_CLK 52
63#define GCC_PCIE_1_MSTR_AXI_CLK 53
64#define GCC_PCIE_1_PIPE_CLK 54
65#define GCC_PCIE_1_SLV_AXI_CLK 55
66#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 56
67#define GCC_PCIE_PHY_AUX_CLK 57
68#define GCC_PCIE_PHY_REFGEN_CLK 58
69#define GCC_PCIE_PHY_REFGEN_CLK_SRC 59
70#define GCC_PDM2_CLK 60
71#define GCC_PDM2_CLK_SRC 61
72#define GCC_PDM_AHB_CLK 62
73#define GCC_PDM_XO4_CLK 63
74#define GCC_PRNG_AHB_CLK 64
75#define GCC_QMIP_CAMERA_AHB_CLK 65
76#define GCC_QMIP_DISP_AHB_CLK 66
77#define GCC_QMIP_VIDEO_AHB_CLK 67
78#define GCC_QUPV3_WRAP0_S0_CLK 68
79#define GCC_QUPV3_WRAP0_S0_CLK_SRC 69
80#define GCC_QUPV3_WRAP0_S1_CLK 70
81#define GCC_QUPV3_WRAP0_S1_CLK_SRC 71
82#define GCC_QUPV3_WRAP0_S2_CLK 72
83#define GCC_QUPV3_WRAP0_S2_CLK_SRC 73
84#define GCC_QUPV3_WRAP0_S3_CLK 74
85#define GCC_QUPV3_WRAP0_S3_CLK_SRC 75
86#define GCC_QUPV3_WRAP0_S4_CLK 76
87#define GCC_QUPV3_WRAP0_S4_CLK_SRC 77
88#define GCC_QUPV3_WRAP0_S5_CLK 78
89#define GCC_QUPV3_WRAP0_S5_CLK_SRC 79
90#define GCC_QUPV3_WRAP0_S6_CLK 80
91#define GCC_QUPV3_WRAP0_S6_CLK_SRC 81
92#define GCC_QUPV3_WRAP0_S7_CLK 82
93#define GCC_QUPV3_WRAP0_S7_CLK_SRC 83
94#define GCC_QUPV3_WRAP1_S0_CLK 84
95#define GCC_QUPV3_WRAP1_S0_CLK_SRC 85
96#define GCC_QUPV3_WRAP1_S1_CLK 86
97#define GCC_QUPV3_WRAP1_S1_CLK_SRC 87
98#define GCC_QUPV3_WRAP1_S2_CLK 88
99#define GCC_QUPV3_WRAP1_S2_CLK_SRC 89
100#define GCC_QUPV3_WRAP1_S3_CLK 90
101#define GCC_QUPV3_WRAP1_S3_CLK_SRC 91
102#define GCC_QUPV3_WRAP1_S4_CLK 92
103#define GCC_QUPV3_WRAP1_S4_CLK_SRC 93
104#define GCC_QUPV3_WRAP1_S5_CLK 94
105#define GCC_QUPV3_WRAP1_S5_CLK_SRC 95
106#define GCC_QUPV3_WRAP1_S6_CLK 96
107#define GCC_QUPV3_WRAP1_S6_CLK_SRC 97
108#define GCC_QUPV3_WRAP1_S7_CLK 98
109#define GCC_QUPV3_WRAP1_S7_CLK_SRC 99
110#define GCC_QUPV3_WRAP_0_M_AHB_CLK 100
111#define GCC_QUPV3_WRAP_0_S_AHB_CLK 101
112#define GCC_QUPV3_WRAP_1_M_AHB_CLK 102
113#define GCC_QUPV3_WRAP_1_S_AHB_CLK 103
114#define GCC_SDCC2_AHB_CLK 104
115#define GCC_SDCC2_APPS_CLK 105
116#define GCC_SDCC2_APPS_CLK_SRC 106
117#define GCC_SDCC4_AHB_CLK 107
118#define GCC_SDCC4_APPS_CLK 108
119#define GCC_SDCC4_APPS_CLK_SRC 109
120#define GCC_SYS_NOC_CPUSS_AHB_CLK 110
121#define GCC_TSIF_AHB_CLK 111
122#define GCC_TSIF_INACTIVITY_TIMERS_CLK 112
123#define GCC_TSIF_REF_CLK 113
124#define GCC_TSIF_REF_CLK_SRC 114
125#define GCC_UFS_CARD_AHB_CLK 115
126#define GCC_UFS_CARD_AXI_CLK 116
127#define GCC_UFS_CARD_AXI_CLK_SRC 117
128#define GCC_UFS_CARD_CLKREF_CLK 118
129#define GCC_UFS_CARD_ICE_CORE_CLK 119
130#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 120
131#define GCC_UFS_CARD_PHY_AUX_CLK 121
132#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 122
133#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 123
134#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 124
135#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 125
136#define GCC_UFS_CARD_UNIPRO_CORE_CLK 126
137#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 127
138#define GCC_UFS_MEM_CLKREF_CLK 128
139#define GCC_UFS_PHY_AHB_CLK 129
140#define GCC_UFS_PHY_AXI_CLK 130
141#define GCC_UFS_PHY_AXI_CLK_SRC 131
142#define GCC_UFS_PHY_ICE_CORE_CLK 132
143#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 133
144#define GCC_UFS_PHY_PHY_AUX_CLK 134
145#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 135
146#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 136
147#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 137
148#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138
149#define GCC_UFS_PHY_UNIPRO_CORE_CLK 139
150#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 140
151#define GCC_USB30_PRIM_MASTER_CLK 141
152#define GCC_USB30_PRIM_MASTER_CLK_SRC 142
153#define GCC_USB30_PRIM_MOCK_UTMI_CLK 143
154#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 144
155#define GCC_USB30_PRIM_SLEEP_CLK 145
156#define GCC_USB30_SEC_MASTER_CLK 146
157#define GCC_USB30_SEC_MASTER_CLK_SRC 147
158#define GCC_USB30_SEC_MOCK_UTMI_CLK 148
159#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 149
160#define GCC_USB30_SEC_SLEEP_CLK 150
161#define GCC_USB3_PRIM_CLKREF_CLK 151
162#define GCC_USB3_PRIM_PHY_AUX_CLK 152
163#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 153
164#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 154
165#define GCC_USB3_PRIM_PHY_PIPE_CLK 155
166#define GCC_USB3_SEC_CLKREF_CLK 156
167#define GCC_USB3_SEC_PHY_AUX_CLK 157
168#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 158
169#define GCC_USB3_SEC_PHY_PIPE_CLK 159
170#define GCC_USB3_SEC_PHY_COM_AUX_CLK 160
171#define GCC_USB_PHY_CFG_AHB2PHY_CLK 161
172#define GCC_VIDEO_AHB_CLK 162
173#define GCC_VIDEO_AXI_CLK 163
174#define GCC_VIDEO_XO_CLK 164
175#define GPLL0 165
176#define GPLL0_OUT_EVEN 166
177#define GPLL0_OUT_MAIN 167
178#define GCC_GPU_IREF_CLK 168
179#define GCC_SDCC1_AHB_CLK 169
180#define GCC_SDCC1_APPS_CLK 170
181#define GCC_SDCC1_ICE_CORE_CLK 171
182#define GCC_SDCC1_APPS_CLK_SRC 172
183#define GCC_SDCC1_ICE_CORE_CLK_SRC 173
184#define GCC_APC_VS_CLK 174
185#define GCC_GPU_VS_CLK 175
186#define GCC_MSS_VS_CLK 176
187#define GCC_VDDA_VS_CLK 177
188#define GCC_VDDCX_VS_CLK 178
189#define GCC_VDDMX_VS_CLK 179
190#define GCC_VS_CTRL_AHB_CLK 180
191#define GCC_VS_CTRL_CLK 181
192#define GCC_VS_CTRL_CLK_SRC 182
193#define GCC_VSENSOR_CLK_SRC 183
194#define GPLL4 184
195
196/* GCC Resets */
197#define GCC_MMSS_BCR 0
198#define GCC_PCIE_0_BCR 1
199#define GCC_PCIE_1_BCR 2
200#define GCC_PCIE_PHY_BCR 3
201#define GCC_PDM_BCR 4
202#define GCC_PRNG_BCR 5
203#define GCC_QUPV3_WRAPPER_0_BCR 6
204#define GCC_QUPV3_WRAPPER_1_BCR 7
205#define GCC_QUSB2PHY_PRIM_BCR 8
206#define GCC_QUSB2PHY_SEC_BCR 9
207#define GCC_SDCC2_BCR 10
208#define GCC_SDCC4_BCR 11
209#define GCC_TSIF_BCR 12
210#define GCC_UFS_CARD_BCR 13
211#define GCC_UFS_PHY_BCR 14
212#define GCC_USB30_PRIM_BCR 15
213#define GCC_USB30_SEC_BCR 16
214#define GCC_USB3_PHY_PRIM_BCR 17
215#define GCC_USB3PHY_PHY_PRIM_BCR 18
216#define GCC_USB3_DP_PHY_PRIM_BCR 19
217#define GCC_USB3_PHY_SEC_BCR 20
218#define GCC_USB3PHY_PHY_SEC_BCR 21
219#define GCC_USB3_DP_PHY_SEC_BCR 22
220#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23
221#define GCC_PCIE_0_PHY_BCR 24
222#define GCC_PCIE_1_PHY_BCR 25
223
224/* GCC GDSCRs */
225#define PCIE_0_GDSC 0
226#define PCIE_1_GDSC 1
227#define UFS_CARD_GDSC 2
228#define UFS_PHY_GDSC 3
229#define USB30_PRIM_GDSC 4
230#define USB30_SEC_GDSC 5
231#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 6
232#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 7
233#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 8
234#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 9
235#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 10
236#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11
237#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 12
238
239#endif
diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h
new file mode 100644
index 000000000000..f48fbd6f2095
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,rpmh.h
@@ -0,0 +1,22 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
3
4
5#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H
6#define _DT_BINDINGS_CLK_MSM_RPMH_H
7
8/* RPMh controlled clocks */
9#define RPMH_CXO_CLK 0
10#define RPMH_CXO_CLK_A 1
11#define RPMH_LN_BB_CLK2 2
12#define RPMH_LN_BB_CLK2_A 3
13#define RPMH_LN_BB_CLK3 4
14#define RPMH_LN_BB_CLK3_A 5
15#define RPMH_RF_CLK1 6
16#define RPMH_RF_CLK1_A 7
17#define RPMH_RF_CLK2 8
18#define RPMH_RF_CLK2_A 9
19#define RPMH_RF_CLK3 10
20#define RPMH_RF_CLK3_A 11
21
22#endif
diff --git a/include/dt-bindings/clock/qcom,videocc-sdm845.h b/include/dt-bindings/clock/qcom,videocc-sdm845.h
new file mode 100644
index 000000000000..1b868165e8ce
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,videocc-sdm845.h
@@ -0,0 +1,35 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
7#define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
8
9/* VIDEO_CC clock registers */
10#define VIDEO_CC_APB_CLK 0
11#define VIDEO_CC_AT_CLK 1
12#define VIDEO_CC_QDSS_TRIG_CLK 2
13#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK 3
14#define VIDEO_CC_VCODEC0_AXI_CLK 4
15#define VIDEO_CC_VCODEC0_CORE_CLK 5
16#define VIDEO_CC_VCODEC1_AXI_CLK 6
17#define VIDEO_CC_VCODEC1_CORE_CLK 7
18#define VIDEO_CC_VENUS_AHB_CLK 8
19#define VIDEO_CC_VENUS_CLK_SRC 9
20#define VIDEO_CC_VENUS_CTL_AXI_CLK 10
21#define VIDEO_CC_VENUS_CTL_CORE_CLK 11
22#define VIDEO_PLL0 12
23
24/* VIDEO_CC Resets */
25#define VIDEO_CC_VENUS_BCR 0
26#define VIDEO_CC_VCODEC0_BCR 1
27#define VIDEO_CC_VCODEC1_BCR 2
28#define VIDEO_CC_INTERFACE_BCR 3
29
30/* VIDEO_CC GDSCRs */
31#define VENUS_GDSC 0
32#define VCODEC0_GDSC 1
33#define VCODEC1_GDSC 2
34
35#endif
diff --git a/include/dt-bindings/clock/r8a77470-cpg-mssr.h b/include/dt-bindings/clock/r8a77470-cpg-mssr.h
new file mode 100644
index 000000000000..34cba49d0f84
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77470-cpg-mssr.h
@@ -0,0 +1,36 @@
1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright (C) 2018 Renesas Electronics Corp.
4 */
5#ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
6#define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
7
8#include <dt-bindings/clock/renesas-cpg-mssr.h>
9
10/* r8a77470 CPG Core Clocks */
11#define R8A77470_CLK_Z2 0
12#define R8A77470_CLK_ZTR 1
13#define R8A77470_CLK_ZTRD2 2
14#define R8A77470_CLK_ZT 3
15#define R8A77470_CLK_ZX 4
16#define R8A77470_CLK_ZS 5
17#define R8A77470_CLK_HP 6
18#define R8A77470_CLK_B 7
19#define R8A77470_CLK_LB 8
20#define R8A77470_CLK_P 9
21#define R8A77470_CLK_CL 10
22#define R8A77470_CLK_CP 11
23#define R8A77470_CLK_M2 12
24#define R8A77470_CLK_ZB3 13
25#define R8A77470_CLK_SDH 14
26#define R8A77470_CLK_SD0 15
27#define R8A77470_CLK_SD1 16
28#define R8A77470_CLK_SD2 17
29#define R8A77470_CLK_MP 18
30#define R8A77470_CLK_QSPI 19
31#define R8A77470_CLK_CPEX 20
32#define R8A77470_CLK_RCAN 21
33#define R8A77470_CLK_R 22
34#define R8A77470_CLK_OSC 23
35
36#endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77990-cpg-mssr.h b/include/dt-bindings/clock/r8a77990-cpg-mssr.h
new file mode 100644
index 000000000000..a596a482f3a9
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77990-cpg-mssr.h
@@ -0,0 +1,62 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2018 Renesas Electronics Corp.
4 */
5#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
6#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
7
8#include <dt-bindings/clock/renesas-cpg-mssr.h>
9
10/* r8a77990 CPG Core Clocks */
11#define R8A77990_CLK_Z2 0
12#define R8A77990_CLK_ZR 1
13#define R8A77990_CLK_ZG 2
14#define R8A77990_CLK_ZTR 3
15#define R8A77990_CLK_ZT 4
16#define R8A77990_CLK_ZX 5
17#define R8A77990_CLK_S0D1 6
18#define R8A77990_CLK_S0D3 7
19#define R8A77990_CLK_S0D6 8
20#define R8A77990_CLK_S0D12 9
21#define R8A77990_CLK_S0D24 10
22#define R8A77990_CLK_S1D1 11
23#define R8A77990_CLK_S1D2 12
24#define R8A77990_CLK_S1D4 13
25#define R8A77990_CLK_S2D1 14
26#define R8A77990_CLK_S2D2 15
27#define R8A77990_CLK_S2D4 16
28#define R8A77990_CLK_S3D1 17
29#define R8A77990_CLK_S3D2 18
30#define R8A77990_CLK_S3D4 19
31#define R8A77990_CLK_S0D6C 20
32#define R8A77990_CLK_S3D1C 21
33#define R8A77990_CLK_S3D2C 22
34#define R8A77990_CLK_S3D4C 23
35#define R8A77990_CLK_LB 24
36#define R8A77990_CLK_CL 25
37#define R8A77990_CLK_ZB3 26
38#define R8A77990_CLK_ZB3D2 27
39#define R8A77990_CLK_CR 28
40#define R8A77990_CLK_CRD2 29
41#define R8A77990_CLK_SD0H 30
42#define R8A77990_CLK_SD0 31
43#define R8A77990_CLK_SD1H 32
44#define R8A77990_CLK_SD1 33
45#define R8A77990_CLK_SD3H 34
46#define R8A77990_CLK_SD3 35
47#define R8A77990_CLK_RPC 36
48#define R8A77990_CLK_RPCD2 37
49#define R8A77990_CLK_ZA2 38
50#define R8A77990_CLK_ZA8 39
51#define R8A77990_CLK_Z2D 40
52#define R8A77990_CLK_CANFD 41
53#define R8A77990_CLK_MSO 42
54#define R8A77990_CLK_R 43
55#define R8A77990_CLK_OSC 44
56#define R8A77990_CLK_LV0 45
57#define R8A77990_CLK_LV1 46
58#define R8A77990_CLK_CSI0 47
59#define R8A77990_CLK_CP 48
60#define R8A77990_CLK_CPEX 49
61
62#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h
index 86e3ec662ef4..90ec780bfc68 100644
--- a/include/dt-bindings/clock/stm32mp1-clks.h
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -76,7 +76,7 @@
76#define I2C6 63 76#define I2C6 63
77#define USART1 64 77#define USART1 64
78#define RTCAPB 65 78#define RTCAPB 65
79#define TZC 66 79#define TZC1 66
80#define TZPC 67 80#define TZPC 67
81#define IWDG1 68 81#define IWDG1 68
82#define BSEC 69 82#define BSEC 69
@@ -123,6 +123,7 @@
123#define CRC1 110 123#define CRC1 110
124#define USBH 111 124#define USBH 111
125#define ETHSTP 112 125#define ETHSTP 112
126#define TZC2 113
126 127
127/* Kernel clocks */ 128/* Kernel clocks */
128#define SDMMC1_K 118 129#define SDMMC1_K 118
@@ -228,7 +229,6 @@
228#define CK_MCO2 212 229#define CK_MCO2 212
229 230
230/* TRACE & DEBUG clocks */ 231/* TRACE & DEBUG clocks */
231#define DBG 213
232#define CK_DBG 214 232#define CK_DBG 214
233#define CK_TRACE 215 233#define CK_TRACE 215
234 234
diff --git a/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/include/dt-bindings/clock/sun50i-h6-r-ccu.h
new file mode 100644
index 000000000000..76136132a13e
--- /dev/null
+++ b/include/dt-bindings/clock/sun50i-h6-r-ccu.h
@@ -0,0 +1,24 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
4 */
5
6#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
7#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
8
9#define CLK_AR100 0
10
11#define CLK_R_APB1 2
12
13#define CLK_R_APB1_TIMER 4
14#define CLK_R_APB1_TWD 5
15#define CLK_R_APB1_PWM 6
16#define CLK_R_APB2_UART 7
17#define CLK_R_APB2_I2C 8
18#define CLK_R_APB1_IR 9
19#define CLK_R_APB1_W1 10
20
21#define CLK_IR 11
22#define CLK_W1 12
23
24#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */
diff --git a/include/dt-bindings/reset/axg-aoclkc.h b/include/dt-bindings/reset/axg-aoclkc.h
new file mode 100644
index 000000000000..d342c0b6b2a7
--- /dev/null
+++ b/include/dt-bindings/reset/axg-aoclkc.h
@@ -0,0 +1,20 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2/*
3 * Copyright (c) 2016 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 *
6 * Copyright (c) 2018 Amlogic, inc.
7 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
8 */
9
10#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
11#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
12
13#define RESET_AO_REMOTE 0
14#define RESET_AO_I2C_MASTER 1
15#define RESET_AO_I2C_SLAVE 2
16#define RESET_AO_UART1 3
17#define RESET_AO_UART2 4
18#define RESET_AO_IR_BLASTER 5
19
20#endif
diff --git a/include/dt-bindings/reset/mt2701-resets.h b/include/dt-bindings/reset/mt2701-resets.h
index 21deb547cfa4..50b7f066da9a 100644
--- a/include/dt-bindings/reset/mt2701-resets.h
+++ b/include/dt-bindings/reset/mt2701-resets.h
@@ -87,4 +87,7 @@
87#define MT2701_ETHSYS_GMAC_RST 23 87#define MT2701_ETHSYS_GMAC_RST 23
88#define MT2701_ETHSYS_PPE_RST 31 88#define MT2701_ETHSYS_PPE_RST 31
89 89
90/* G3DSYS resets */
91#define MT2701_G3DSYS_CORE_RST 0
92
90#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */ 93#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */
diff --git a/include/dt-bindings/reset/sun50i-h6-r-ccu.h b/include/dt-bindings/reset/sun50i-h6-r-ccu.h
new file mode 100644
index 000000000000..01c84dba49a4
--- /dev/null
+++ b/include/dt-bindings/reset/sun50i-h6-r-ccu.h
@@ -0,0 +1,17 @@
1/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
2/*
3 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
4 */
5
6#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
7#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
8
9#define RST_R_APB1_TIMER 0
10#define RST_R_APB1_TWD 1
11#define RST_R_APB1_PWM 2
12#define RST_R_APB2_UART 3
13#define RST_R_APB2_I2C 4
14#define RST_R_APB1_IR 5
15#define RST_R_APB1_W1 6
16
17#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 210a890008f9..1d8d5493d531 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -13,6 +13,7 @@
13 13
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/of.h> 15#include <linux/of.h>
16#include <linux/of_clk.h>
16 17
17#ifdef CONFIG_COMMON_CLK 18#ifdef CONFIG_COMMON_CLK
18 19
@@ -218,7 +219,7 @@ struct clk_ops {
218 int (*get_phase)(struct clk_hw *hw); 219 int (*get_phase)(struct clk_hw *hw);
219 int (*set_phase)(struct clk_hw *hw, int degrees); 220 int (*set_phase)(struct clk_hw *hw, int degrees);
220 void (*init)(struct clk_hw *hw); 221 void (*init)(struct clk_hw *hw);
221 int (*debug_init)(struct clk_hw *hw, struct dentry *dentry); 222 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
222}; 223};
223 224
224/** 225/**
@@ -802,8 +803,6 @@ unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
802 803
803struct of_device_id; 804struct of_device_id;
804 805
805typedef void (*of_clk_init_cb_t)(struct device_node *);
806
807struct clk_onecell_data { 806struct clk_onecell_data {
808 struct clk **clks; 807 struct clk **clks;
809 unsigned int clk_num; 808 unsigned int clk_num;
@@ -890,13 +889,10 @@ struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
890struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); 889struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
891struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, 890struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
892 void *data); 891 void *data);
893unsigned int of_clk_get_parent_count(struct device_node *np);
894int of_clk_parent_fill(struct device_node *np, const char **parents, 892int of_clk_parent_fill(struct device_node *np, const char **parents,
895 unsigned int size); 893 unsigned int size);
896const char *of_clk_get_parent_name(struct device_node *np, int index);
897int of_clk_detect_critical(struct device_node *np, int index, 894int of_clk_detect_critical(struct device_node *np, int index,
898 unsigned long *flags); 895 unsigned long *flags);
899void of_clk_init(const struct of_device_id *matches);
900 896
901#else /* !CONFIG_OF */ 897#else /* !CONFIG_OF */
902 898
@@ -943,26 +939,16 @@ of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
943{ 939{
944 return ERR_PTR(-ENOENT); 940 return ERR_PTR(-ENOENT);
945} 941}
946static inline unsigned int of_clk_get_parent_count(struct device_node *np)
947{
948 return 0;
949}
950static inline int of_clk_parent_fill(struct device_node *np, 942static inline int of_clk_parent_fill(struct device_node *np,
951 const char **parents, unsigned int size) 943 const char **parents, unsigned int size)
952{ 944{
953 return 0; 945 return 0;
954} 946}
955static inline const char *of_clk_get_parent_name(struct device_node *np,
956 int index)
957{
958 return NULL;
959}
960static inline int of_clk_detect_critical(struct device_node *np, int index, 947static inline int of_clk_detect_critical(struct device_node *np, int index,
961 unsigned long *flags) 948 unsigned long *flags)
962{ 949{
963 return 0; 950 return 0;
964} 951}
965static inline void of_clk_init(const struct of_device_id *matches) {}
966#endif /* CONFIG_OF */ 952#endif /* CONFIG_OF */
967 953
968/* 954/*
@@ -996,10 +982,5 @@ static inline void clk_writel(u32 val, u32 __iomem *reg)
996 982
997#endif /* platform dependent I/O accessors */ 983#endif /* platform dependent I/O accessors */
998 984
999#ifdef CONFIG_DEBUG_FS
1000struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
1001 void *data, const struct file_operations *fops);
1002#endif
1003
1004#endif /* CONFIG_COMMON_CLK */ 985#endif /* CONFIG_COMMON_CLK */
1005#endif /* CLK_PROVIDER_H */ 986#endif /* CLK_PROVIDER_H */
diff --git a/include/linux/of_clk.h b/include/linux/of_clk.h
new file mode 100644
index 000000000000..b27da9f164cb
--- /dev/null
+++ b/include/linux/of_clk.h
@@ -0,0 +1,30 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * OF clock helpers
4 */
5
6#ifndef __LINUX_OF_CLK_H
7#define __LINUX_OF_CLK_H
8
9#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_OF)
10
11unsigned int of_clk_get_parent_count(struct device_node *np);
12const char *of_clk_get_parent_name(struct device_node *np, int index);
13void of_clk_init(const struct of_device_id *matches);
14
15#else /* !CONFIG_COMMON_CLK || !CONFIG_OF */
16
17static inline unsigned int of_clk_get_parent_count(struct device_node *np)
18{
19 return 0;
20}
21static inline const char *of_clk_get_parent_name(struct device_node *np,
22 int index)
23{
24 return NULL;
25}
26static inline void of_clk_init(const struct of_device_id *matches) {}
27
28#endif /* !CONFIG_COMMON_CLK || !CONFIG_OF */
29
30#endif /* __LINUX_OF_CLK_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-31 09:50:22 -0500